From abe0a5f51a86a42ed88efe6f2c90bd3d5444f3d0 Mon Sep 17 00:00:00 2001 From: Michael McMaster Date: Sun, 23 Mar 2014 08:36:29 +1000 Subject: [PATCH] Powerbook firmware! Includes updates to the bootloderhost utility to compare the USB device release number against an expected firmware filename to prevent loading the Powerbook firmware on the normal board, and vice-versa. --- CHANGELOG | 2 + .../Generated_Source/PSoC5/SCSI_CMD_TIMER.h | 439 - .../Generated_Source/PSoC5/cyfitter.h | 234 +- .../Generated_Source/PSoC5/cyfitter_cfg.c | 1671 +- .../Generated_Source/PSoC5/cyfittergnu.inc | 234 +- .../Generated_Source/PSoC5/cyfitteriar.inc | 234 +- .../Generated_Source/PSoC5/cyfitterrv.inc | 234 +- .../Generated_Source/PSoC5/project.h | 2 - software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx | 104 +- software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit | Bin 231806 -> 226302 bytes software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyprj | 62 +- software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.svd | 296 +- .../SCSI2SD.cydsn/TopDesign/TopDesign.cysch | Bin 169955 -> 162742 bytes .../ARM_GCC_473/Release/.deps/ARM_C_FILE.P | 170 +- .../ARM_GCC_473/Release/.deps/C_FILE.P | 70 +- .../Release/.deps/GNU_ARM_ASM_FILE.P | 10 +- .../CortexM3/ARM_GCC_473/Release/BL.lst | 1139 +- .../CortexM3/ARM_GCC_473/Release/BL.o | Bin 21988 -> 22004 bytes .../CortexM3/ARM_GCC_473/Release/Cm3Start.lst | 491 +- .../CortexM3/ARM_GCC_473/Release/Cm3Start.o | Bin 7940 -> 7956 bytes .../ARM_GCC_473/Release/CyBootAsmGnu.lst | 1759 +- .../ARM_GCC_473/Release/CyBootAsmGnu.o | Bin 433988 -> 435620 bytes .../CortexM3/ARM_GCC_473/Release/CyDmac.lst | 1019 +- .../CortexM3/ARM_GCC_473/Release/CyDmac.o | Bin 22020 -> 22040 bytes .../CortexM3/ARM_GCC_473/Release/CyFlash.lst | 607 +- .../CortexM3/ARM_GCC_473/Release/CyFlash.o | Bin 14360 -> 14380 bytes .../CortexM3/ARM_GCC_473/Release/CyLib.lst | 1665 +- .../CortexM3/ARM_GCC_473/Release/CyLib.o | Bin 38320 -> 38336 bytes .../CortexM3/ARM_GCC_473/Release/CySpc.lst | 621 +- .../CortexM3/ARM_GCC_473/Release/CySpc.o | Bin 11424 -> 11440 bytes .../CortexM3/ARM_GCC_473/Release/USBFS.lst | 811 +- .../CortexM3/ARM_GCC_473/Release/USBFS.o | Bin 18372 -> 18388 bytes .../CortexM3/ARM_GCC_473/Release/USBFS_Dm.lst | 201 +- .../CortexM3/ARM_GCC_473/Release/USBFS_Dm.o | Bin 4116 -> 4132 bytes .../CortexM3/ARM_GCC_473/Release/USBFS_Dp.lst | 239 +- .../CortexM3/ARM_GCC_473/Release/USBFS_Dp.o | Bin 4476 -> 4496 bytes .../ARM_GCC_473/Release/USBFS_audio.lst | 29 +- .../ARM_GCC_473/Release/USBFS_audio.o | Bin 1880 -> 1896 bytes .../ARM_GCC_473/Release/USBFS_boot.lst | 443 +- .../CortexM3/ARM_GCC_473/Release/USBFS_boot.o | Bin 8540 -> 8556 bytes .../ARM_GCC_473/Release/USBFS_cdc.lst | 29 +- .../CortexM3/ARM_GCC_473/Release/USBFS_cdc.o | Bin 1880 -> 1896 bytes .../ARM_GCC_473/Release/USBFS_cls.lst | 313 +- .../CortexM3/ARM_GCC_473/Release/USBFS_cls.o | Bin 4072 -> 4092 bytes .../ARM_GCC_473/Release/USBFS_descr.lst | 435 +- .../ARM_GCC_473/Release/USBFS_descr.o | Bin 6088 -> 6108 bytes .../ARM_GCC_473/Release/USBFS_drv.lst | 881 +- .../CortexM3/ARM_GCC_473/Release/USBFS_drv.o | Bin 15588 -> 15604 bytes .../ARM_GCC_473/Release/USBFS_episr.lst | 321 +- .../ARM_GCC_473/Release/USBFS_episr.o | Bin 4528 -> 4544 bytes .../ARM_GCC_473/Release/USBFS_hid.lst | 507 +- .../CortexM3/ARM_GCC_473/Release/USBFS_hid.o | Bin 9672 -> 9688 bytes .../ARM_GCC_473/Release/USBFS_midi.lst | 29 +- .../CortexM3/ARM_GCC_473/Release/USBFS_midi.o | Bin 1880 -> 1896 bytes .../CortexM3/ARM_GCC_473/Release/USBFS_pm.lst | 487 +- .../CortexM3/ARM_GCC_473/Release/USBFS_pm.o | Bin 7184 -> 7200 bytes .../ARM_GCC_473/Release/USBFS_std.lst | 951 +- .../CortexM3/ARM_GCC_473/Release/USBFS_std.o | Bin 17944 -> 17960 bytes .../ARM_GCC_473/Release/USBFS_vnd.lst | 95 +- .../CortexM3/ARM_GCC_473/Release/USBFS_vnd.o | Bin 2780 -> 2796 bytes ...B_Bootloader-ARM_GCC_473-Release-BUILD.log | 56 +- .../ARM_GCC_473/Release/USB_Bootloader.a | Bin 687832 -> 694336 bytes .../ARM_GCC_473/Release/USB_Bootloader.elf | Bin 719329 -> 721062 bytes .../ARM_GCC_473/Release/USB_Bootloader.hex | 274 +- .../ARM_GCC_473/Release/USB_Bootloader.map | 586 +- .../CortexM3/ARM_GCC_473/Release/cyPm.lst | 1201 +- .../CortexM3/ARM_GCC_473/Release/cyPm.o | Bin 17976 -> 17992 bytes .../ARM_GCC_473/Release/cyfitter_cfg.lst | 4398 ++--- .../ARM_GCC_473/Release/cyfitter_cfg.o | Bin 8200 -> 8336 bytes .../ARM_GCC_473/Release/cymetadata.lst | 231 +- .../CortexM3/ARM_GCC_473/Release/cymetadata.o | Bin 3272 -> 3292 bytes .../CortexM3/ARM_GCC_473/Release/cyutils.lst | 173 +- .../CortexM3/ARM_GCC_473/Release/cyutils.o | Bin 2980 -> 2996 bytes .../CortexM3/ARM_GCC_473/Release/library.deps | 2 +- .../CortexM3/ARM_GCC_473/Release/main.lst | 69 +- .../CortexM3/ARM_GCC_473/Release/main.o | Bin 3560 -> 3576 bytes .../Generated_Source/PSoC5/SD_PULLUP.c | 141 + .../Generated_Source/PSoC5/SD_PULLUP.h | 130 + .../PSoC5/SD_PULLUP_aliases.h | 36 + .../Generated_Source/PSoC5/cydevice.h | 2 +- .../Generated_Source/PSoC5/cydevice_trm.h | 2 +- .../Generated_Source/PSoC5/cydevicegnu.inc | 2 +- .../PSoC5/cydevicegnu_trm.inc | 2 +- .../Generated_Source/PSoC5/cydeviceiar.inc | 2 +- .../PSoC5/cydeviceiar_trm.inc | 2 +- .../Generated_Source/PSoC5/cydevicerv.inc | 2 +- .../Generated_Source/PSoC5/cydevicerv_trm.inc | 2 +- .../Generated_Source/PSoC5/cyfitter.h | 48 + .../Generated_Source/PSoC5/cyfitter_cfg.c | 12 +- .../Generated_Source/PSoC5/cyfitter_cfg.h | 2 +- .../Generated_Source/PSoC5/cyfittergnu.inc | 48 + .../Generated_Source/PSoC5/cyfitteriar.inc | 48 + .../Generated_Source/PSoC5/cyfitterrv.inc | 48 + .../Generated_Source/PSoC5/cymetadata.c | 4 +- .../Generated_Source/PSoC5/project.h | 4 +- .../Generated_Source/PSoCCreatorExportIDE.xml | 39 +- .../TopDesign/TopDesign.cysch | Bin 104999 -> 107373 bytes .../USB_Bootloader.cydsn/USB_Bootloader.cycdx | 3 +- .../USB_Bootloader.cydsn/USB_Bootloader.cydwr | Bin 74823 -> 75517 bytes .../USB_Bootloader.cydsn/USB_Bootloader.cyfit | Bin 157426 -> 159511 bytes .../USB_Bootloader.cydsn/USB_Bootloader.cyprj | 41 +- .../USB_Bootloader.cyprj.Micha_000 | 638 +- .../USB_Bootloader.cydsn/USB_Bootloader.rpt | 492 +- .../USB_Bootloader_timing.html | 2 +- .../codegentemp/USB_Bootloader.ctl | 2 +- .../codegentemp/USB_Bootloader.cycdx | 3 +- .../codegentemp/USB_Bootloader.cyfit | Bin 157426 -> 159511 bytes .../codegentemp/USB_Bootloader.pci | 7 +- .../codegentemp/USB_Bootloader.pco | 7 +- .../codegentemp/USB_Bootloader.plc_log | 2 +- .../codegentemp/USB_Bootloader.route | 10 + .../codegentemp/USB_Bootloader.rpt | 492 +- .../codegentemp/USB_Bootloader.sdc | 10 +- .../codegentemp/USB_Bootloader.sdf | 12 +- .../codegentemp/USB_Bootloader.v | 75 +- .../codegentemp/USB_Bootloader.vh2 | 90 +- .../codegentemp/USB_Bootloader_p.lib | 337 +- .../codegentemp/USB_Bootloader_p.pco | 5 + .../codegentemp/USB_Bootloader_p.vh2 | 190 +- .../codegentemp/USB_Bootloader_r.lib | 337 +- .../codegentemp/USB_Bootloader_r.vh2 | 190 +- .../codegentemp/USB_Bootloader_t.lib | 337 +- .../codegentemp/USB_Bootloader_t.vh2 | 192 +- .../codegentemp/USB_Bootloader_timing.html | 2 +- .../codegentemp/USB_Bootloader_u.sdc | 6 +- .../codegentemp/bitstream.txt | 1241 +- .../codegentemp/cydevice.h | 2 +- .../codegentemp/cydevice_trm.h | 2 +- .../codegentemp/cydevicegnu.inc | 2 +- .../codegentemp/cydevicegnu_trm.inc | 2 +- .../codegentemp/cydeviceiar.inc | 2 +- .../codegentemp/cydeviceiar_trm.inc | 2 +- .../codegentemp/cydevicerv.inc | 2 +- .../codegentemp/cydevicerv_trm.inc | 2 +- .../codegentemp/cyfitter.h | 48 + .../codegentemp/cyfitter_cfg.c | 12 +- .../codegentemp/cyfitter_cfg.h | 2 +- .../codegentemp/cyfittergnu.inc | 48 + .../codegentemp/cyfitteriar.inc | 48 + .../codegentemp/cyfitterrv.inc | 48 + .../codegentemp/cymetadata.c | 4 +- .../codegentemp/elab_dependencies.txt | 42 +- .../codegentemp/generated_files.txt | 153 +- .../codegentemp/lcpsoc3/index | Bin 1792 -> 1792 bytes .../codegentemp/placer.log | 6 +- .../codegentemp/project.h | 4 +- .../Generated_Source/PSoC5/BL.c | 1462 ++ .../Generated_Source/PSoC5/BL.h | 318 + .../Generated_Source/PSoC5/BL_PVT.h | 315 + .../Generated_Source/PSoC5/Cm3Iar.icf | 113 + .../Generated_Source/PSoC5/Cm3RealView.scat | 190 + .../Generated_Source/PSoC5/Cm3Start.c | 461 + .../Generated_Source/PSoC5/CyBootAsmGnu.s | 174 + .../Generated_Source/PSoC5/CyBootAsmIar.s | 156 + .../Generated_Source/PSoC5/CyBootAsmRv.s | 161 + .../Generated_Source/PSoC5/CyDmac.c | 1131 ++ .../Generated_Source/PSoC5/CyDmac.h | 218 + .../Generated_Source/PSoC5/CyFlash.c | 694 + .../Generated_Source/PSoC5/CyFlash.h | 239 + .../Generated_Source/PSoC5/CyLib.c | 2710 +++ .../Generated_Source/PSoC5/CyLib.h | 1281 ++ .../Generated_Source/PSoC5/CySpc.c | 554 + .../Generated_Source/PSoC5/CySpc.h | 154 + .../Generated_Source/PSoC5/LED.c | 137 + .../Generated_Source/PSoC5/LED.h | 130 + .../Generated_Source/PSoC5/LED_aliases.h | 32 + .../PSoC5/SCSI_Out_DBx_aliases.h | 48 + .../Generated_Source/PSoC5/SCSI_Out_aliases.h | 52 + .../Generated_Source/PSoC5/SD_PULLUP.c | 141 + .../Generated_Source/PSoC5/SD_PULLUP.h | 130 + .../PSoC5/SD_PULLUP_aliases.h | 36 + .../Generated_Source/PSoC5/USBFS.c | 1335 ++ .../Generated_Source/PSoC5/USBFS.h | 1189 ++ .../Generated_Source/PSoC5/USBFS_Dm.c | 137 + .../Generated_Source/PSoC5/USBFS_Dm.h | 130 + .../Generated_Source/PSoC5/USBFS_Dm_aliases.h | 32 + .../Generated_Source/PSoC5/USBFS_Dp.c | 137 + .../Generated_Source/PSoC5/USBFS_Dp.h | 130 + .../Generated_Source/PSoC5/USBFS_Dp_aliases.h | 32 + .../Generated_Source/PSoC5/USBFS_audio.c | 318 + .../Generated_Source/PSoC5/USBFS_audio.h | 95 + .../Generated_Source/PSoC5/USBFS_boot.c | 262 + .../Generated_Source/PSoC5/USBFS_cdc.c | 706 + .../Generated_Source/PSoC5/USBFS_cdc.h | 92 + .../Generated_Source/PSoC5/USBFS_cdc.inf | 122 + .../Generated_Source/PSoC5/USBFS_cls.c | 107 + .../Generated_Source/PSoC5/USBFS_descr.c | 323 + .../Generated_Source/PSoC5/USBFS_drv.c | 781 + .../Generated_Source/PSoC5/USBFS_episr.c | 658 + .../Generated_Source/PSoC5/USBFS_hid.c | 422 + .../Generated_Source/PSoC5/USBFS_hid.h | 64 + .../Generated_Source/PSoC5/USBFS_midi.c | 1341 ++ .../Generated_Source/PSoC5/USBFS_midi.h | 200 + .../Generated_Source/PSoC5/USBFS_pm.c | 277 + .../Generated_Source/PSoC5/USBFS_pvt.h | 203 + .../Generated_Source/PSoC5/USBFS_std.c | 1134 ++ .../Generated_Source/PSoC5/USBFS_vnd.c | 96 + .../Generated_Source/PSoC5/cm3gcc.ld | 295 + .../Generated_Source/PSoC5/core_cm3.h | 1627 ++ .../Generated_Source/PSoC5/core_cm3_psoc5.h | 54 + .../Generated_Source/PSoC5/core_cmFunc.h | 636 + .../Generated_Source/PSoC5/core_cmInstr.h | 688 + .../Generated_Source/PSoC5/cyPm.c | 1819 ++ .../Generated_Source/PSoC5/cyPm.h | 635 + .../Generated_Source/PSoC5/cydevice.h | 5360 ++++++ .../Generated_Source/PSoC5/cydevice_trm.h | 5360 ++++++ .../Generated_Source/PSoC5/cydevicegnu.inc | 5357 ++++++ .../PSoC5/cydevicegnu_trm.inc | 5357 ++++++ .../Generated_Source/PSoC5/cydeviceiar.inc | 5356 ++++++ .../PSoC5/cydeviceiar_trm.inc | 5356 ++++++ .../Generated_Source/PSoC5/cydevicerv.inc | 16039 ++++++++++++++++ .../Generated_Source/PSoC5/cydevicerv_trm.inc | 16039 ++++++++++++++++ .../Generated_Source/PSoC5/cydisabledsheets.h | 5 + .../Generated_Source/PSoC5/cyfitter.h | 1441 ++ .../Generated_Source/PSoC5/cyfitter_cfg.c | 444 + .../Generated_Source/PSoC5/cyfitter_cfg.h | 28 + .../Generated_Source/PSoC5/cyfittergnu.inc | 1434 ++ .../Generated_Source/PSoC5/cyfitteriar.inc | 1435 ++ .../Generated_Source/PSoC5/cyfitterrv.inc | 1435 ++ .../Generated_Source/PSoC5/cymetadata.c | 108 + .../Generated_Source/PSoC5/cypins.h | 295 + .../Generated_Source/PSoC5/cytypes.h | 438 + .../Generated_Source/PSoC5/cyutils.c | 87 + .../Generated_Source/PSoC5/eeprom.hex | 0 .../Generated_Source/PSoC5/project.h | 53 + .../Generated_Source/PSoC5/protect.hex | 3 + .../TopDesign/TopDesign.cysch | Bin 0 -> 108793 bytes .../pbook/bootloader.cydsn/bootloader.cycdx | 86 + .../pbook/bootloader.cydsn/bootloader.cydwr | Bin 0 -> 75774 bytes .../pbook/bootloader.cydsn/bootloader.cyfit | Bin 0 -> 160805 bytes .../pbook/bootloader.cydsn/bootloader.cyprj | 1139 ++ .../pbook/bootloader.cydsn/bootloader.svd | 494 + .../SCSI2SD/pbook/bootloader.cydsn/main.c | 54 + software/SCSI2SD/pbook/pbook.cydsn/.gitignore | 7 + .../Generated_Source/PSoC5/Bootloadable_1.c | 84 + .../Generated_Source/PSoC5/Bootloadable_1.h | 155 + .../Generated_Source/PSoC5/CFG_EEPROM.c | 511 + .../Generated_Source/PSoC5/CFG_EEPROM.h | 60 + .../Generated_Source/PSoC5/Cm3Iar.icf | 113 + .../Generated_Source/PSoC5/Cm3RealView.scat | 190 + .../Generated_Source/PSoC5/Cm3Start.c | 461 + .../Generated_Source/PSoC5/CyBootAsmGnu.s | 174 + .../Generated_Source/PSoC5/CyBootAsmIar.s | 156 + .../Generated_Source/PSoC5/CyBootAsmRv.s | 161 + .../Generated_Source/PSoC5/CyDmac.c | 1131 ++ .../Generated_Source/PSoC5/CyDmac.h | 218 + .../Generated_Source/PSoC5/CyFlash.c | 694 + .../Generated_Source/PSoC5/CyFlash.h | 239 + .../Generated_Source/PSoC5/CyLib.c | 2710 +++ .../Generated_Source/PSoC5/CyLib.h | 1281 ++ .../Generated_Source/PSoC5/CySpc.c | 554 + .../Generated_Source/PSoC5/CySpc.h | 154 + .../pbook.cydsn/Generated_Source/PSoC5/LED1.c | 137 + .../pbook.cydsn/Generated_Source/PSoC5/LED1.h | 130 + .../Generated_Source/PSoC5/LED1_aliases.h | 32 + .../Generated_Source/PSoC5/SCSI_ATN.c | 137 + .../Generated_Source/PSoC5/SCSI_ATN.h | 130 + .../Generated_Source/PSoC5/SCSI_ATN_aliases.h | 34 + .../Generated_Source/PSoC5/SCSI_CTL_IO.c | 63 + .../Generated_Source/PSoC5/SCSI_CTL_IO.h | 42 + .../PSoC5/SCSI_In_DBx_aliases.h | 48 + .../Generated_Source/PSoC5/SCSI_In_aliases.h | 48 + .../PSoC5/SCSI_Out_DBx_aliases.h | 48 + .../Generated_Source/PSoC5/SCSI_Out_aliases.h | 52 + .../Generated_Source/PSoC5/SCSI_RST.c | 137 + .../Generated_Source/PSoC5/SCSI_RST.h | 130 + .../Generated_Source/PSoC5/SCSI_RST_ISR.c | 356 + .../Generated_Source/PSoC5/SCSI_RST_ISR.h | 70 + .../Generated_Source/PSoC5/SCSI_RST_aliases.h | 34 + .../Generated_Source/PSoC5/SDCard.c | 1155 ++ .../Generated_Source/PSoC5/SDCard.h | 389 + .../Generated_Source/PSoC5/SDCard_INT.c | 189 + .../Generated_Source/PSoC5/SDCard_PM.c | 180 + .../Generated_Source/PSoC5/SDCard_PVT.h | 53 + .../Generated_Source/PSoC5/SD_CD.c | 137 + .../Generated_Source/PSoC5/SD_CD.h | 130 + .../Generated_Source/PSoC5/SD_CD_aliases.h | 32 + .../Generated_Source/PSoC5/SD_CS.c | 137 + .../Generated_Source/PSoC5/SD_CS.h | 130 + .../Generated_Source/PSoC5/SD_CS_aliases.h | 32 + .../Generated_Source/PSoC5/SD_Clk_Ctl.c | 63 + .../Generated_Source/PSoC5/SD_Clk_Ctl.h | 42 + .../Generated_Source/PSoC5/SD_Data_Clk.c | 521 + .../Generated_Source/PSoC5/SD_Data_Clk.h | 124 + .../Generated_Source/PSoC5/SD_Init_Clk.c | 521 + .../Generated_Source/PSoC5/SD_Init_Clk.h | 124 + .../Generated_Source/PSoC5/SD_MISO.c | 137 + .../Generated_Source/PSoC5/SD_MISO.h | 130 + .../Generated_Source/PSoC5/SD_MISO_aliases.h | 32 + .../Generated_Source/PSoC5/SD_MOSI.c | 137 + .../Generated_Source/PSoC5/SD_MOSI.h | 130 + .../Generated_Source/PSoC5/SD_MOSI_aliases.h | 32 + .../Generated_Source/PSoC5/SD_SCK.c | 137 + .../Generated_Source/PSoC5/SD_SCK.h | 130 + .../Generated_Source/PSoC5/SD_SCK_aliases.h | 32 + .../Generated_Source/PSoC5/USBFS.c | 1335 ++ .../Generated_Source/PSoC5/USBFS.h | 1189 ++ .../Generated_Source/PSoC5/USBFS_Dm.c | 137 + .../Generated_Source/PSoC5/USBFS_Dm.h | 130 + .../Generated_Source/PSoC5/USBFS_Dm_aliases.h | 32 + .../Generated_Source/PSoC5/USBFS_Dp.c | 137 + .../Generated_Source/PSoC5/USBFS_Dp.h | 130 + .../Generated_Source/PSoC5/USBFS_Dp_aliases.h | 32 + .../Generated_Source/PSoC5/USBFS_audio.c | 318 + .../Generated_Source/PSoC5/USBFS_audio.h | 95 + .../Generated_Source/PSoC5/USBFS_boot.c | 262 + .../Generated_Source/PSoC5/USBFS_cdc.c | 706 + .../Generated_Source/PSoC5/USBFS_cdc.h | 92 + .../Generated_Source/PSoC5/USBFS_cdc.inf | 122 + .../Generated_Source/PSoC5/USBFS_cls.c | 107 + .../Generated_Source/PSoC5/USBFS_descr.c | 319 + .../Generated_Source/PSoC5/USBFS_drv.c | 781 + .../Generated_Source/PSoC5/USBFS_episr.c | 658 + .../Generated_Source/PSoC5/USBFS_hid.c | 422 + .../Generated_Source/PSoC5/USBFS_hid.h | 64 + .../Generated_Source/PSoC5/USBFS_midi.c | 1341 ++ .../Generated_Source/PSoC5/USBFS_midi.h | 200 + .../Generated_Source/PSoC5/USBFS_pm.c | 277 + .../Generated_Source/PSoC5/USBFS_pvt.h | 203 + .../Generated_Source/PSoC5/USBFS_std.c | 1134 ++ .../Generated_Source/PSoC5/USBFS_vnd.c | 96 + .../Generated_Source/PSoC5/cm3gcc.ld | 295 + .../Generated_Source/PSoC5/core_cm3.h | 1627 ++ .../Generated_Source/PSoC5/core_cm3_psoc5.h | 54 + .../Generated_Source/PSoC5/core_cmFunc.h | 636 + .../Generated_Source/PSoC5/core_cmInstr.h | 688 + .../pbook.cydsn/Generated_Source/PSoC5/cyPm.c | 1819 ++ .../pbook.cydsn/Generated_Source/PSoC5/cyPm.h | 635 + .../Generated_Source/PSoC5/cybootloader.c | 1206 ++ .../Generated_Source/PSoC5/cybootloader.icf | 3 + .../Generated_Source/PSoC5/cydevice.h | 5360 ++++++ .../Generated_Source/PSoC5/cydevice_trm.h | 5360 ++++++ .../Generated_Source/PSoC5/cydevicegnu.inc | 5357 ++++++ .../PSoC5/cydevicegnu_trm.inc | 5357 ++++++ .../Generated_Source/PSoC5/cydeviceiar.inc | 5356 ++++++ .../PSoC5/cydeviceiar_trm.inc | 5356 ++++++ .../Generated_Source/PSoC5/cydevicerv.inc | 16039 ++++++++++++++++ .../Generated_Source/PSoC5/cydevicerv_trm.inc | 16039 ++++++++++++++++ .../Generated_Source/PSoC5/cydisabledsheets.h | 5 + .../Generated_Source/PSoC5/cyfitter.h | 2684 +++ .../Generated_Source/PSoC5/cyfitter_cfg.c | 1359 ++ .../Generated_Source/PSoC5/cyfitter_cfg.h | 28 + .../Generated_Source/PSoC5/cyfittergnu.inc | 2676 +++ .../Generated_Source/PSoC5/cyfitteriar.inc | 2677 +++ .../Generated_Source/PSoC5/cyfitterrv.inc | 2677 +++ .../Generated_Source/PSoC5/cymetadata.c | 48 + .../Generated_Source/PSoC5/cypins.h | 295 + .../Generated_Source/PSoC5/cytypes.h | 438 + .../Generated_Source/PSoC5/cyutils.c | 87 + .../Generated_Source/PSoC5/eeprom.hex | 0 .../Generated_Source/PSoC5/project.h | 74 + .../Generated_Source/PSoC5/protect.hex | 3 + .../SCSI2SD/pbook/pbook.cydsn/OddParityGen | 1 + .../pbook.cydsn/TopDesign/TopDesign.cysch | Bin 0 -> 159595 bytes software/SCSI2SD/pbook/pbook.cydsn/device.h | 18 + .../SCSI2SD/pbook/pbook.cydsn/pbook.cycdx | 115 + .../SCSI2SD/pbook/pbook.cydsn/pbook.cydwr | Bin 0 -> 134863 bytes .../SCSI2SD/pbook/pbook.cydsn/pbook.cyfit | Bin 0 -> 223978 bytes .../SCSI2SD/pbook/pbook.cydsn/pbook.cyprj | 2216 +++ software/SCSI2SD/pbook/pbook.cydsn/pbook.svd | 536 + software/SCSI2SD/pbook/pbook.cydsn/scsiTarget | 1 + .../SCSI2SD/{SCSI2SD.cydsn => src}/bits.c | 0 .../SCSI2SD/{SCSI2SD.cydsn => src}/bits.h | 0 .../SCSI2SD/{SCSI2SD.cydsn => src}/config.c | 0 .../SCSI2SD/{SCSI2SD.cydsn => src}/config.h | 0 .../{SCSI2SD.cydsn => src}/diagnostic.c | 0 .../{SCSI2SD.cydsn => src}/diagnostic.h | 0 .../SCSI2SD/{SCSI2SD.cydsn => src}/disk.c | 0 .../SCSI2SD/{SCSI2SD.cydsn => src}/disk.h | 0 .../SCSI2SD/{SCSI2SD.cydsn => src}/geometry.c | 0 .../SCSI2SD/{SCSI2SD.cydsn => src}/geometry.h | 0 .../SCSI2SD/{SCSI2SD.cydsn => src}/inquiry.c | 4 +- .../SCSI2SD/{SCSI2SD.cydsn => src}/inquiry.h | 0 software/SCSI2SD/{SCSI2SD.cydsn => src}/led.h | 0 .../SCSI2SD/{SCSI2SD.cydsn => src}/main.c | 0 .../SCSI2SD/{SCSI2SD.cydsn => src}/mode.c | 0 .../SCSI2SD/{SCSI2SD.cydsn => src}/mode.h | 0 .../SCSI2SD/{SCSI2SD.cydsn => src}/scsi.c | 75 +- .../SCSI2SD/{SCSI2SD.cydsn => src}/scsi.h | 15 +- .../SCSI2SD/{SCSI2SD.cydsn => src}/scsiPhy.c | 11 +- .../SCSI2SD/{SCSI2SD.cydsn => src}/scsiPhy.h | 0 software/SCSI2SD/{SCSI2SD.cydsn => src}/sd.c | 10 + software/SCSI2SD/{SCSI2SD.cydsn => src}/sd.h | 0 .../SCSI2SD/{SCSI2SD.cydsn => src}/sense.h | 0 software/bootloaderhost/main.c | 45 +- 385 files changed, 229806 insertions(+), 13206 deletions(-) delete mode 100755 software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER.h create mode 100755 software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.c create mode 100755 software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.h create mode 100755 software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP_aliases.h mode change 100644 => 100755 software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h mode change 100644 => 100755 software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h mode change 100644 => 100755 software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu.inc mode change 100644 => 100755 software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc mode change 100644 => 100755 software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar.inc mode change 100644 => 100755 software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc mode change 100644 => 100755 software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv.inc mode change 100644 => 100755 software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc mode change 100644 => 100755 software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h mode change 100644 => 100755 software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c mode change 100644 => 100755 software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h mode change 100644 => 100755 software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfittergnu.inc mode change 100644 => 100755 software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitteriar.inc mode change 100644 => 100755 software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitterrv.inc mode change 100644 => 100755 software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c mode change 100644 => 100755 software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/project.h create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/BL.c create mode 100755 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/BL.h create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/BL_PVT.h create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/Cm3Iar.icf create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/Cm3RealView.scat create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/Cm3Start.c create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyDmac.c create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyFlash.c create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyLib.c create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyLib.h create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CySpc.c create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CySpc.h create mode 100755 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/LED.c create mode 100755 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/LED.h create mode 100755 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/LED_aliases.h create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h create mode 100755 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.c create mode 100755 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.h create mode 100755 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP_aliases.h create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS.c create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS.h create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.c create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.h create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.c create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.h create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.c create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.h create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_boot.c create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.c create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.h create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_cls.c create mode 100755 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_descr.c create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_drv.c create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_episr.c create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.c create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.h create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.c create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.h create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_pm.c create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_std.c create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_vnd.c create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cm3gcc.ld create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/core_cm3.h create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/core_cmFunc.h create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/core_cmInstr.h create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyPm.c create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyPm.h create mode 100755 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydevice.h create mode 100755 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h create mode 100755 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu.inc create mode 100755 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc create mode 100755 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar.inc create mode 100755 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc create mode 100755 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydevicerv.inc create mode 100755 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydisabledsheets.h create mode 100755 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h create mode 100755 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c create mode 100755 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h create mode 100755 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyfittergnu.inc create mode 100755 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyfitteriar.inc create mode 100755 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyfitterrv.inc create mode 100755 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cypins.h create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cytypes.h create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyutils.c create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/eeprom.hex create mode 100755 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/project.h create mode 100644 software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/protect.hex create mode 100755 software/SCSI2SD/pbook/bootloader.cydsn/TopDesign/TopDesign.cysch create mode 100755 software/SCSI2SD/pbook/bootloader.cydsn/bootloader.cycdx create mode 100755 software/SCSI2SD/pbook/bootloader.cydsn/bootloader.cydwr create mode 100755 software/SCSI2SD/pbook/bootloader.cydsn/bootloader.cyfit create mode 100755 software/SCSI2SD/pbook/bootloader.cydsn/bootloader.cyprj create mode 100755 software/SCSI2SD/pbook/bootloader.cydsn/bootloader.svd create mode 100755 software/SCSI2SD/pbook/bootloader.cydsn/main.c create mode 100644 software/SCSI2SD/pbook/pbook.cydsn/.gitignore create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/Bootloadable_1.c create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/Bootloadable_1.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CFG_EEPROM.c create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CFG_EEPROM.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/Cm3Iar.icf create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/Cm3RealView.scat create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/Cm3Start.c create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyDmac.c create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyDmac.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyFlash.c create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyFlash.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyLib.c create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyLib.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CySpc.c create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CySpc.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/LED1.c create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/LED1.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/LED1_aliases.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_ATN.c create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_ATN.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_ATN_aliases.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.c create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_In_DBx_aliases.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_RST.c create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_RST.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_RST_ISR.c create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_RST_ISR.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_RST_aliases.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SDCard.c create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SDCard.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SDCard_INT.c create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SDCard_PM.c create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SDCard_PVT.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_CD.c create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_CD.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_CD_aliases.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_CS.c create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_CS.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_CS_aliases.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_Clk_Ctl.c create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_Clk_Ctl.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_Data_Clk.c create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_Data_Clk.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_Init_Clk.c create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_Init_Clk.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_MISO.c create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_MISO.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_MISO_aliases.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_MOSI.c create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_MOSI.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_MOSI_aliases.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_SCK.c create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_SCK.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_SCK_aliases.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS.c create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_Dm.c create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_Dm.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_Dp.c create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_Dp.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_audio.c create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_audio.h create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_boot.c create mode 100755 software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_cdc.c create mode 100755 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(100%) rename software/SCSI2SD/{SCSI2SD.cydsn => src}/diagnostic.c (100%) rename software/SCSI2SD/{SCSI2SD.cydsn => src}/diagnostic.h (100%) rename software/SCSI2SD/{SCSI2SD.cydsn => src}/disk.c (100%) rename software/SCSI2SD/{SCSI2SD.cydsn => src}/disk.h (100%) rename software/SCSI2SD/{SCSI2SD.cydsn => src}/geometry.c (100%) rename software/SCSI2SD/{SCSI2SD.cydsn => src}/geometry.h (100%) rename software/SCSI2SD/{SCSI2SD.cydsn => src}/inquiry.c (95%) rename software/SCSI2SD/{SCSI2SD.cydsn => src}/inquiry.h (100%) rename software/SCSI2SD/{SCSI2SD.cydsn => src}/led.h (100%) rename software/SCSI2SD/{SCSI2SD.cydsn => src}/main.c (100%) rename software/SCSI2SD/{SCSI2SD.cydsn => src}/mode.c (100%) rename software/SCSI2SD/{SCSI2SD.cydsn => src}/mode.h (100%) rename software/SCSI2SD/{SCSI2SD.cydsn => src}/scsi.c (89%) rename software/SCSI2SD/{SCSI2SD.cydsn => src}/scsi.h (90%) rename software/SCSI2SD/{SCSI2SD.cydsn => src}/scsiPhy.c (90%) rename software/SCSI2SD/{SCSI2SD.cydsn => src}/scsiPhy.h (100%) rename software/SCSI2SD/{SCSI2SD.cydsn => src}/sd.c (93%) rename software/SCSI2SD/{SCSI2SD.cydsn => src}/sd.h (100%) rename software/SCSI2SD/{SCSI2SD.cydsn => src}/sense.h (100%) diff --git a/CHANGELOG b/CHANGELOG index 81e04ecf..ef651479 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -4,6 +4,8 @@ - Bug fix for Unit Attention Condition, which is now enabled by default. - scsi2sd-config can be used to disable it for those systems that truely require it (eg. Mac Plus). + - Added Linked commands support. + - Powerbook firmware added 20140214 3.2 - Remove hacks around ATN handling, and implement proper select-with-atn diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER.h deleted file mode 100755 index fc4e09bd..00000000 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER.h +++ /dev/null @@ -1,439 +0,0 @@ -/******************************************************************************* -* File Name: SCSI_CMD_TIMER.h -* Version 2.50 -* -* Description: -* Contains the function prototypes and constants available to the timer -* user module. -* -* Note: -* None -* -******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -********************************************************************************/ - -#if !defined(CY_Timer_v2_30_SCSI_CMD_TIMER_H) -#define CY_Timer_v2_30_SCSI_CMD_TIMER_H - -#include "cytypes.h" -#include "cyfitter.h" -#include "CyLib.h" /* For CyEnterCriticalSection() and CyExitCriticalSection() functions */ - -extern uint8 SCSI_CMD_TIMER_initVar; - -/* Check to see if required defines such as CY_PSOC5LP are available */ -/* They are defined starting with cy_boot v3.0 */ -#if !defined (CY_PSOC5LP) - #error Component Timer_v2_50 requires cy_boot v3.0 or later -#endif /* (CY_ PSOC5LP) */ - - -/************************************** -* Parameter Defaults -**************************************/ - -#define SCSI_CMD_TIMER_Resolution 16u -#define SCSI_CMD_TIMER_UsingFixedFunction 1u -#define SCSI_CMD_TIMER_UsingHWCaptureCounter 0u -#define SCSI_CMD_TIMER_SoftwareCaptureMode 0u -#define SCSI_CMD_TIMER_SoftwareTriggerMode 0u -#define SCSI_CMD_TIMER_UsingHWEnable 0u -#define SCSI_CMD_TIMER_EnableTriggerMode 0u -#define SCSI_CMD_TIMER_InterruptOnCaptureCount 0u -#define SCSI_CMD_TIMER_RunModeUsed 1u -#define SCSI_CMD_TIMER_ControlRegRemoved 0u - - -/*************************************** -* Type defines -***************************************/ - - -/************************************************************************** - * Sleep Wakeup Backup structure for Timer Component - *************************************************************************/ -typedef struct -{ - uint8 TimerEnableState; - #if(!SCSI_CMD_TIMER_UsingFixedFunction) - #if (CY_UDB_V0) - uint16 TimerUdb; /* Timer internal counter value */ - uint16 TimerPeriod; /* Timer Period value */ - uint8 InterruptMaskValue; /* Timer Compare Value */ - #if (SCSI_CMD_TIMER_UsingHWCaptureCounter) - uint8 TimerCaptureCounter; /* Timer Capture Counter Value */ - #endif /* variable declaration for backing up Capture Counter value*/ - #endif /* variables for non retention registers in CY_UDB_V0 */ - - #if (CY_UDB_V1) - uint16 TimerUdb; - uint8 InterruptMaskValue; - #if (SCSI_CMD_TIMER_UsingHWCaptureCounter) - uint8 TimerCaptureCounter; - #endif /* variable declarations for backing up non retention registers in CY_UDB_V1 */ - #endif /* (CY_UDB_V1) */ - - #if (!SCSI_CMD_TIMER_ControlRegRemoved) - uint8 TimerControlRegister; - #endif /* variable declaration for backing up enable state of the Timer */ - #endif /* define backup variables only for UDB implementation. Fixed function registers are all retention */ -}SCSI_CMD_TIMER_backupStruct; - - -/*************************************** -* Function Prototypes -***************************************/ - -void SCSI_CMD_TIMER_Start(void) ; -void SCSI_CMD_TIMER_Stop(void) ; - -void SCSI_CMD_TIMER_SetInterruptMode(uint8 interruptMode) ; -uint8 SCSI_CMD_TIMER_ReadStatusRegister(void) ; -/* Deprecated function. Do not use this in future. Retained for backward compatibility */ -#define SCSI_CMD_TIMER_GetInterruptSource() SCSI_CMD_TIMER_ReadStatusRegister() - -#if(!SCSI_CMD_TIMER_ControlRegRemoved) - uint8 SCSI_CMD_TIMER_ReadControlRegister(void) ; - void SCSI_CMD_TIMER_WriteControlRegister(uint8 control) \ - ; -#endif /* (!SCSI_CMD_TIMER_ControlRegRemoved) */ - -uint16 SCSI_CMD_TIMER_ReadPeriod(void) ; -void SCSI_CMD_TIMER_WritePeriod(uint16 period) \ - ; -uint16 SCSI_CMD_TIMER_ReadCounter(void) ; -void SCSI_CMD_TIMER_WriteCounter(uint16 counter) \ - ; -uint16 SCSI_CMD_TIMER_ReadCapture(void) ; -void SCSI_CMD_TIMER_SoftwareCapture(void) ; - - -#if(!SCSI_CMD_TIMER_UsingFixedFunction) /* UDB Prototypes */ - #if (SCSI_CMD_TIMER_SoftwareCaptureMode) - void SCSI_CMD_TIMER_SetCaptureMode(uint8 captureMode) ; - #endif /* (!SCSI_CMD_TIMER_UsingFixedFunction) */ - - #if (SCSI_CMD_TIMER_SoftwareTriggerMode) - void SCSI_CMD_TIMER_SetTriggerMode(uint8 triggerMode) ; - #endif /* (SCSI_CMD_TIMER_SoftwareTriggerMode) */ - #if (SCSI_CMD_TIMER_EnableTriggerMode) - void SCSI_CMD_TIMER_EnableTrigger(void) ; - void SCSI_CMD_TIMER_DisableTrigger(void) ; - #endif /* (SCSI_CMD_TIMER_EnableTriggerMode) */ - - #if(SCSI_CMD_TIMER_InterruptOnCaptureCount) - #if(!SCSI_CMD_TIMER_ControlRegRemoved) - void SCSI_CMD_TIMER_SetInterruptCount(uint8 interruptCount) \ - ; - #endif /* (!SCSI_CMD_TIMER_ControlRegRemoved) */ - #endif /* (SCSI_CMD_TIMER_InterruptOnCaptureCount) */ - - #if (SCSI_CMD_TIMER_UsingHWCaptureCounter) - void SCSI_CMD_TIMER_SetCaptureCount(uint8 captureCount) \ - ; - uint8 SCSI_CMD_TIMER_ReadCaptureCount(void) ; - #endif /* (SCSI_CMD_TIMER_UsingHWCaptureCounter) */ - - void SCSI_CMD_TIMER_ClearFIFO(void) ; -#endif /* UDB Prototypes */ - -/* Sleep Retention APIs */ -void SCSI_CMD_TIMER_Init(void) ; -void SCSI_CMD_TIMER_Enable(void) ; -void SCSI_CMD_TIMER_SaveConfig(void) ; -void SCSI_CMD_TIMER_RestoreConfig(void) ; -void SCSI_CMD_TIMER_Sleep(void) ; -void SCSI_CMD_TIMER_Wakeup(void) ; - - -/*************************************** -* Enumerated Types and Parameters -***************************************/ - -/* Enumerated Type B_Timer__CaptureModes, Used in Capture Mode */ -#define SCSI_CMD_TIMER__B_TIMER__CM_NONE 0 -#define SCSI_CMD_TIMER__B_TIMER__CM_RISINGEDGE 1 -#define SCSI_CMD_TIMER__B_TIMER__CM_FALLINGEDGE 2 -#define SCSI_CMD_TIMER__B_TIMER__CM_EITHEREDGE 3 -#define SCSI_CMD_TIMER__B_TIMER__CM_SOFTWARE 4 - - - -/* Enumerated Type B_Timer__TriggerModes, Used in Trigger Mode */ -#define SCSI_CMD_TIMER__B_TIMER__TM_NONE 0x00u -#define SCSI_CMD_TIMER__B_TIMER__TM_RISINGEDGE 0x04u -#define SCSI_CMD_TIMER__B_TIMER__TM_FALLINGEDGE 0x08u -#define SCSI_CMD_TIMER__B_TIMER__TM_EITHEREDGE 0x0Cu -#define SCSI_CMD_TIMER__B_TIMER__TM_SOFTWARE 0x10u - - -/*************************************** -* Initialial Parameter Constants -***************************************/ - -#define SCSI_CMD_TIMER_INIT_PERIOD 1199u -#define SCSI_CMD_TIMER_INIT_CAPTURE_MODE ((uint8)((uint8)0u << SCSI_CMD_TIMER_CTRL_CAP_MODE_SHIFT)) -#define SCSI_CMD_TIMER_INIT_TRIGGER_MODE ((uint8)((uint8)0u << SCSI_CMD_TIMER_CTRL_TRIG_MODE_SHIFT)) -#if (SCSI_CMD_TIMER_UsingFixedFunction) - #define SCSI_CMD_TIMER_INIT_INTERRUPT_MODE (((uint8)((uint8)0u << SCSI_CMD_TIMER_STATUS_TC_INT_MASK_SHIFT)) | \ - ((uint8)((uint8)0 << SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK_SHIFT))) -#else - #define SCSI_CMD_TIMER_INIT_INTERRUPT_MODE (((uint8)((uint8)0u << SCSI_CMD_TIMER_STATUS_TC_INT_MASK_SHIFT)) | \ - ((uint8)((uint8)0 << SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK_SHIFT)) | \ - ((uint8)((uint8)0 << SCSI_CMD_TIMER_STATUS_FIFOFULL_INT_MASK_SHIFT))) -#endif /* (SCSI_CMD_TIMER_UsingFixedFunction) */ -#define SCSI_CMD_TIMER_INIT_CAPTURE_COUNT (2u) -#define SCSI_CMD_TIMER_INIT_INT_CAPTURE_COUNT ((uint8)((uint8)(1u - 1u) << SCSI_CMD_TIMER_CTRL_INTCNT_SHIFT)) - - -/*************************************** -* Registers -***************************************/ - -#if (SCSI_CMD_TIMER_UsingFixedFunction) /* Implementation Specific Registers and Register Constants */ - - - /*************************************** - * Fixed Function Registers - ***************************************/ - - #define SCSI_CMD_TIMER_STATUS (*(reg8 *) SCSI_CMD_TIMER_TimerHW__SR0 ) - /* In Fixed Function Block Status and Mask are the same register */ - #define SCSI_CMD_TIMER_STATUS_MASK (*(reg8 *) SCSI_CMD_TIMER_TimerHW__SR0 ) - #define SCSI_CMD_TIMER_CONTROL (*(reg8 *) SCSI_CMD_TIMER_TimerHW__CFG0) - #define SCSI_CMD_TIMER_CONTROL2 (*(reg8 *) SCSI_CMD_TIMER_TimerHW__CFG1) - #define SCSI_CMD_TIMER_CONTROL2_PTR ( (reg8 *) SCSI_CMD_TIMER_TimerHW__CFG1) - #define SCSI_CMD_TIMER_RT1 (*(reg8 *) SCSI_CMD_TIMER_TimerHW__RT1) - #define SCSI_CMD_TIMER_RT1_PTR ( (reg8 *) SCSI_CMD_TIMER_TimerHW__RT1) - - #if (CY_PSOC3 || CY_PSOC5LP) - #define SCSI_CMD_TIMER_CONTROL3 (*(reg8 *) SCSI_CMD_TIMER_TimerHW__CFG2) - #define SCSI_CMD_TIMER_CONTROL3_PTR ( (reg8 *) SCSI_CMD_TIMER_TimerHW__CFG2) - #endif /* (CY_PSOC3 || CY_PSOC5LP) */ - #define SCSI_CMD_TIMER_GLOBAL_ENABLE (*(reg8 *) SCSI_CMD_TIMER_TimerHW__PM_ACT_CFG) - #define SCSI_CMD_TIMER_GLOBAL_STBY_ENABLE (*(reg8 *) SCSI_CMD_TIMER_TimerHW__PM_STBY_CFG) - - #define SCSI_CMD_TIMER_CAPTURE_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerHW__CAP0 ) - #define SCSI_CMD_TIMER_CAPTURE_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerHW__CAP0 ) - #define SCSI_CMD_TIMER_PERIOD_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerHW__PER0 ) - #define SCSI_CMD_TIMER_PERIOD_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerHW__PER0 ) - #define SCSI_CMD_TIMER_COUNTER_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerHW__CNT_CMP0 ) - #define SCSI_CMD_TIMER_COUNTER_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerHW__CNT_CMP0 ) - - - /*************************************** - * Register Constants - ***************************************/ - - /* Fixed Function Block Chosen */ - #define SCSI_CMD_TIMER_BLOCK_EN_MASK SCSI_CMD_TIMER_TimerHW__PM_ACT_MSK - #define SCSI_CMD_TIMER_BLOCK_STBY_EN_MASK SCSI_CMD_TIMER_TimerHW__PM_STBY_MSK - - /* Control Register Bit Locations */ - /* Interrupt Count - Not valid for Fixed Function Block */ - #define SCSI_CMD_TIMER_CTRL_INTCNT_SHIFT 0x00u - /* Trigger Polarity - Not valid for Fixed Function Block */ - #define SCSI_CMD_TIMER_CTRL_TRIG_MODE_SHIFT 0x00u - /* Trigger Enable - Not valid for Fixed Function Block */ - #define SCSI_CMD_TIMER_CTRL_TRIG_EN_SHIFT 0x00u - /* Capture Polarity - Not valid for Fixed Function Block */ - #define SCSI_CMD_TIMER_CTRL_CAP_MODE_SHIFT 0x00u - /* Timer Enable - As defined in Register Map, part of TMRX_CFG0 register */ - #define SCSI_CMD_TIMER_CTRL_ENABLE_SHIFT 0x00u - - /* Control Register Bit Masks */ - #define SCSI_CMD_TIMER_CTRL_ENABLE ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_CTRL_ENABLE_SHIFT)) - - /* Control2 Register Bit Masks */ - /* As defined in Register Map, Part of the TMRX_CFG1 register */ - #define SCSI_CMD_TIMER_CTRL2_IRQ_SEL_SHIFT 0x00u - #define SCSI_CMD_TIMER_CTRL2_IRQ_SEL ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_CTRL2_IRQ_SEL_SHIFT)) - - #if (CY_PSOC5A) - /* Use CFG1 Mode bits to set run mode */ - /* As defined by Verilog Implementation */ - #define SCSI_CMD_TIMER_CTRL_MODE_SHIFT 0x01u - #define SCSI_CMD_TIMER_CTRL_MODE_MASK ((uint8)((uint8)0x07u << SCSI_CMD_TIMER_CTRL_MODE_SHIFT)) - #endif /* (CY_PSOC5A) */ - #if (CY_PSOC3 || CY_PSOC5LP) - /* Control3 Register Bit Locations */ - #define SCSI_CMD_TIMER_CTRL_RCOD_SHIFT 0x02u - #define SCSI_CMD_TIMER_CTRL_ENBL_SHIFT 0x00u - #define SCSI_CMD_TIMER_CTRL_MODE_SHIFT 0x00u - - /* Control3 Register Bit Masks */ - #define SCSI_CMD_TIMER_CTRL_RCOD_MASK ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_CTRL_RCOD_SHIFT)) /* ROD and COD bit masks */ - #define SCSI_CMD_TIMER_CTRL_ENBL_MASK ((uint8)((uint8)0x80u << SCSI_CMD_TIMER_CTRL_ENBL_SHIFT)) /* HW_EN bit mask */ - #define SCSI_CMD_TIMER_CTRL_MODE_MASK ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_CTRL_MODE_SHIFT)) /* Run mode bit mask */ - - #define SCSI_CMD_TIMER_CTRL_RCOD ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_CTRL_RCOD_SHIFT)) - #define SCSI_CMD_TIMER_CTRL_ENBL ((uint8)((uint8)0x80u << SCSI_CMD_TIMER_CTRL_ENBL_SHIFT)) - #endif /* (CY_PSOC3 || CY_PSOC5LP) */ - - /*RT1 Synch Constants: Applicable for PSoC3 and PSoC5LP */ - #define SCSI_CMD_TIMER_RT1_SHIFT 0x04u - /* Sync TC and CMP bit masks */ - #define SCSI_CMD_TIMER_RT1_MASK ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_RT1_SHIFT)) - #define SCSI_CMD_TIMER_SYNC ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_RT1_SHIFT)) - #define SCSI_CMD_TIMER_SYNCDSI_SHIFT 0x00u - /* Sync all DSI inputs with Mask */ - #define SCSI_CMD_TIMER_SYNCDSI_MASK ((uint8)((uint8)0x0Fu << SCSI_CMD_TIMER_SYNCDSI_SHIFT)) - /* Sync all DSI inputs */ - #define SCSI_CMD_TIMER_SYNCDSI_EN ((uint8)((uint8)0x0Fu << SCSI_CMD_TIMER_SYNCDSI_SHIFT)) - - #define SCSI_CMD_TIMER_CTRL_MODE_PULSEWIDTH ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_CTRL_MODE_SHIFT)) - #define SCSI_CMD_TIMER_CTRL_MODE_PERIOD ((uint8)((uint8)0x02u << SCSI_CMD_TIMER_CTRL_MODE_SHIFT)) - #define SCSI_CMD_TIMER_CTRL_MODE_CONTINUOUS ((uint8)((uint8)0x00u << SCSI_CMD_TIMER_CTRL_MODE_SHIFT)) - - /* Status Register Bit Locations */ - /* As defined in Register Map, part of TMRX_SR0 register */ - #define SCSI_CMD_TIMER_STATUS_TC_SHIFT 0x07u - /* As defined in Register Map, part of TMRX_SR0 register, Shared with Compare Status */ - #define SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT 0x06u - /* As defined in Register Map, part of TMRX_SR0 register */ - #define SCSI_CMD_TIMER_STATUS_TC_INT_MASK_SHIFT (SCSI_CMD_TIMER_STATUS_TC_SHIFT - 0x04u) - /* As defined in Register Map, part of TMRX_SR0 register, Shared with Compare Status */ - #define SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK_SHIFT (SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT - 0x04u) - - /* Status Register Bit Masks */ - #define SCSI_CMD_TIMER_STATUS_TC ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_TC_SHIFT)) - #define SCSI_CMD_TIMER_STATUS_CAPTURE ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT)) - /* Interrupt Enable Bit-Mask for interrupt on TC */ - #define SCSI_CMD_TIMER_STATUS_TC_INT_MASK ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_TC_INT_MASK_SHIFT)) - /* Interrupt Enable Bit-Mask for interrupt on Capture */ - #define SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK_SHIFT)) - -#else /* UDB Registers and Register Constants */ - - - /*************************************** - * UDB Registers - ***************************************/ - - #define SCSI_CMD_TIMER_STATUS (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_rstSts_stsreg__STATUS_REG ) - #define SCSI_CMD_TIMER_STATUS_MASK (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_rstSts_stsreg__MASK_REG) - #define SCSI_CMD_TIMER_STATUS_AUX_CTRL (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_rstSts_stsreg__STATUS_AUX_CTL_REG) - #define SCSI_CMD_TIMER_CONTROL (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG ) - - #if(SCSI_CMD_TIMER_Resolution <= 8u) /* 8-bit Timer */ - #define SCSI_CMD_TIMER_CAPTURE_LSB (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG ) - #define SCSI_CMD_TIMER_CAPTURE_LSB_PTR ((reg8 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG ) - #define SCSI_CMD_TIMER_PERIOD_LSB (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG ) - #define SCSI_CMD_TIMER_PERIOD_LSB_PTR ((reg8 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG ) - #define SCSI_CMD_TIMER_COUNTER_LSB (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG ) - #define SCSI_CMD_TIMER_COUNTER_LSB_PTR ((reg8 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG ) - #elif(SCSI_CMD_TIMER_Resolution <= 16u) /* 8-bit Timer */ - #if(CY_PSOC3) /* 8-bit addres space */ - #define SCSI_CMD_TIMER_CAPTURE_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG ) - #define SCSI_CMD_TIMER_CAPTURE_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG ) - #define SCSI_CMD_TIMER_PERIOD_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG ) - #define SCSI_CMD_TIMER_PERIOD_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG ) - #define SCSI_CMD_TIMER_COUNTER_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG ) - #define SCSI_CMD_TIMER_COUNTER_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG ) - #else /* 16-bit address space */ - #define SCSI_CMD_TIMER_CAPTURE_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG ) - #define SCSI_CMD_TIMER_CAPTURE_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG ) - #define SCSI_CMD_TIMER_PERIOD_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG ) - #define SCSI_CMD_TIMER_PERIOD_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG ) - #define SCSI_CMD_TIMER_COUNTER_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG ) - #define SCSI_CMD_TIMER_COUNTER_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG ) - #endif /* CY_PSOC3 */ - #elif(SCSI_CMD_TIMER_Resolution <= 24u)/* 24-bit Timer */ - #define SCSI_CMD_TIMER_CAPTURE_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG ) - #define SCSI_CMD_TIMER_CAPTURE_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG ) - #define SCSI_CMD_TIMER_PERIOD_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG ) - #define SCSI_CMD_TIMER_PERIOD_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG ) - #define SCSI_CMD_TIMER_COUNTER_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG ) - #define SCSI_CMD_TIMER_COUNTER_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG ) - #else /* 32-bit Timer */ - #if(CY_PSOC3 || CY_PSOC5) /* 8-bit address space */ - #define SCSI_CMD_TIMER_CAPTURE_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG ) - #define SCSI_CMD_TIMER_CAPTURE_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG ) - #define SCSI_CMD_TIMER_PERIOD_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG ) - #define SCSI_CMD_TIMER_PERIOD_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG ) - #define SCSI_CMD_TIMER_COUNTER_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG ) - #define SCSI_CMD_TIMER_COUNTER_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG ) - #else /* 32-bit address space */ - #define SCSI_CMD_TIMER_CAPTURE_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__32BIT_F0_REG ) - #define SCSI_CMD_TIMER_CAPTURE_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__32BIT_F0_REG ) - #define SCSI_CMD_TIMER_PERIOD_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__32BIT_D0_REG ) - #define SCSI_CMD_TIMER_PERIOD_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__32BIT_D0_REG ) - #define SCSI_CMD_TIMER_COUNTER_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__32BIT_A0_REG ) - #define SCSI_CMD_TIMER_COUNTER_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__32BIT_A0_REG ) - #endif /* CY_PSOC3 || CY_PSOC5 */ - #endif - - #if (SCSI_CMD_TIMER_UsingHWCaptureCounter) - #define SCSI_CMD_TIMER_CAP_COUNT (*(reg8 *) SCSI_CMD_TIMER_TimerUDB_sCapCount_counter__PERIOD_REG ) - #define SCSI_CMD_TIMER_CAP_COUNT_PTR ( (reg8 *) SCSI_CMD_TIMER_TimerUDB_sCapCount_counter__PERIOD_REG ) - #define SCSI_CMD_TIMER_CAPTURE_COUNT_CTRL (*(reg8 *) SCSI_CMD_TIMER_TimerUDB_sCapCount_counter__CONTROL_AUX_CTL_REG ) - #define SCSI_CMD_TIMER_CAPTURE_COUNT_CTRL_PTR ( (reg8 *) SCSI_CMD_TIMER_TimerUDB_sCapCount_counter__CONTROL_AUX_CTL_REG ) - #endif /* (SCSI_CMD_TIMER_UsingHWCaptureCounter) */ - - - /*************************************** - * Register Constants - ***************************************/ - - /* Control Register Bit Locations */ - #define SCSI_CMD_TIMER_CTRL_INTCNT_SHIFT 0x00u /* As defined by Verilog Implementation */ - #define SCSI_CMD_TIMER_CTRL_TRIG_MODE_SHIFT 0x02u /* As defined by Verilog Implementation */ - #define SCSI_CMD_TIMER_CTRL_TRIG_EN_SHIFT 0x04u /* As defined by Verilog Implementation */ - #define SCSI_CMD_TIMER_CTRL_CAP_MODE_SHIFT 0x05u /* As defined by Verilog Implementation */ - #define SCSI_CMD_TIMER_CTRL_ENABLE_SHIFT 0x07u /* As defined by Verilog Implementation */ - - /* Control Register Bit Masks */ - #define SCSI_CMD_TIMER_CTRL_INTCNT_MASK ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_CTRL_INTCNT_SHIFT)) - #define SCSI_CMD_TIMER_CTRL_TRIG_MODE_MASK ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_CTRL_TRIG_MODE_SHIFT)) - #define SCSI_CMD_TIMER_CTRL_TRIG_EN ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_CTRL_TRIG_EN_SHIFT)) - #define SCSI_CMD_TIMER_CTRL_CAP_MODE_MASK ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_CTRL_CAP_MODE_SHIFT)) - #define SCSI_CMD_TIMER_CTRL_ENABLE ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_CTRL_ENABLE_SHIFT)) - - /* Bit Counter (7-bit) Control Register Bit Definitions */ - /* As defined by the Register map for the AUX Control Register */ - #define SCSI_CMD_TIMER_CNTR_ENABLE 0x20u - - /* Status Register Bit Locations */ - #define SCSI_CMD_TIMER_STATUS_TC_SHIFT 0x00u /* As defined by Verilog Implementation */ - #define SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT 0x01u /* As defined by Verilog Implementation */ - #define SCSI_CMD_TIMER_STATUS_TC_INT_MASK_SHIFT SCSI_CMD_TIMER_STATUS_TC_SHIFT - #define SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK_SHIFT SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT - #define SCSI_CMD_TIMER_STATUS_FIFOFULL_SHIFT 0x02u /* As defined by Verilog Implementation */ - #define SCSI_CMD_TIMER_STATUS_FIFONEMP_SHIFT 0x03u /* As defined by Verilog Implementation */ - #define SCSI_CMD_TIMER_STATUS_FIFOFULL_INT_MASK_SHIFT SCSI_CMD_TIMER_STATUS_FIFOFULL_SHIFT - - /* Status Register Bit Masks */ - /* Sticky TC Event Bit-Mask */ - #define SCSI_CMD_TIMER_STATUS_TC ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_TC_SHIFT)) - /* Sticky Capture Event Bit-Mask */ - #define SCSI_CMD_TIMER_STATUS_CAPTURE ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT)) - /* Interrupt Enable Bit-Mask */ - #define SCSI_CMD_TIMER_STATUS_TC_INT_MASK ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_TC_SHIFT)) - /* Interrupt Enable Bit-Mask */ - #define SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT)) - /* NOT-Sticky FIFO Full Bit-Mask */ - #define SCSI_CMD_TIMER_STATUS_FIFOFULL ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_FIFOFULL_SHIFT)) - /* NOT-Sticky FIFO Not Empty Bit-Mask */ - #define SCSI_CMD_TIMER_STATUS_FIFONEMP ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_FIFONEMP_SHIFT)) - /* Interrupt Enable Bit-Mask */ - #define SCSI_CMD_TIMER_STATUS_FIFOFULL_INT_MASK ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_FIFOFULL_SHIFT)) - - #define SCSI_CMD_TIMER_STATUS_ACTL_INT_EN 0x10u /* As defined for the ACTL Register */ - - /* Datapath Auxillary Control Register definitions */ - #define SCSI_CMD_TIMER_AUX_CTRL_FIFO0_CLR 0x01u /* As defined by Register map */ - #define SCSI_CMD_TIMER_AUX_CTRL_FIFO1_CLR 0x02u /* As defined by Register map */ - #define SCSI_CMD_TIMER_AUX_CTRL_FIFO0_LVL 0x04u /* As defined by Register map */ - #define SCSI_CMD_TIMER_AUX_CTRL_FIFO1_LVL 0x08u /* As defined by Register map */ - #define SCSI_CMD_TIMER_STATUS_ACTL_INT_EN_MASK 0x10u /* As defined for the ACTL Register */ - -#endif /* Implementation Specific Registers and Register Constants */ - -#endif /* CY_Timer_v2_30_SCSI_CMD_TIMER_H */ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h index 9a5677e7..7d179bd1 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -3,34 +3,6 @@ #include #include -/* SCSI_CMD_TIMER_TimerHW */ -#define SCSI_CMD_TIMER_TimerHW__CAP0 CYREG_TMR0_CAP0 -#define SCSI_CMD_TIMER_TimerHW__CAP1 CYREG_TMR0_CAP1 -#define SCSI_CMD_TIMER_TimerHW__CFG0 CYREG_TMR0_CFG0 -#define SCSI_CMD_TIMER_TimerHW__CFG1 CYREG_TMR0_CFG1 -#define SCSI_CMD_TIMER_TimerHW__CFG2 CYREG_TMR0_CFG2 -#define SCSI_CMD_TIMER_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0 -#define SCSI_CMD_TIMER_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1 -#define SCSI_CMD_TIMER_TimerHW__PER0 CYREG_TMR0_PER0 -#define SCSI_CMD_TIMER_TimerHW__PER1 CYREG_TMR0_PER1 -#define SCSI_CMD_TIMER_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3 -#define SCSI_CMD_TIMER_TimerHW__PM_ACT_MSK 0x01u -#define SCSI_CMD_TIMER_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3 -#define SCSI_CMD_TIMER_TimerHW__PM_STBY_MSK 0x01u -#define SCSI_CMD_TIMER_TimerHW__RT0 CYREG_TMR0_RT0 -#define SCSI_CMD_TIMER_TimerHW__RT1 CYREG_TMR0_RT1 -#define SCSI_CMD_TIMER_TimerHW__SR0 CYREG_TMR0_SR0 - -/* SCSI_CMD_TIMER_ISR */ -#define SCSI_CMD_TIMER_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define SCSI_CMD_TIMER_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_CMD_TIMER_ISR__INTC_MASK 0x01u -#define SCSI_CMD_TIMER_ISR__INTC_NUMBER 0u -#define SCSI_CMD_TIMER_ISR__INTC_PRIOR_NUM 7u -#define SCSI_CMD_TIMER_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_0 -#define SCSI_CMD_TIMER_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define SCSI_CMD_TIMER_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - /* USBFS_bus_reset */ #define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 @@ -532,8 +504,8 @@ #define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL #define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB06_MSK #define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u #define SDCard_BSPIM_RxStsReg__4__POS 4 #define SDCard_BSPIM_RxStsReg__5__MASK 0x20u @@ -541,13 +513,13 @@ #define SDCard_BSPIM_RxStsReg__6__MASK 0x40u #define SDCard_BSPIM_RxStsReg__6__POS 6 #define SDCard_BSPIM_RxStsReg__MASK 0x70u -#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB05_MSK -#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL -#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB05_ST +#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB07_MSK +#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL +#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB07_ST #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u #define SDCard_BSPIM_TxStsReg__0__POS 0 -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u #define SDCard_BSPIM_TxStsReg__1__POS 1 #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u @@ -557,9 +529,9 @@ #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u #define SDCard_BSPIM_TxStsReg__4__POS 4 #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu -#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB06_MSK -#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL -#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB06_ST +#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB05_MSK +#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL +#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB05_ST #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB06_07_A0 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB06_07_A1 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB06_07_D0 @@ -593,24 +565,24 @@ /* SCSI_CTL_IO */ #define SCSI_CTL_IO_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_CTL_IO_Sync_ctrl_reg__0__POS 0 -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK -#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL -#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL -#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL -#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL -#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK +#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL +#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL #define SCSI_CTL_IO_Sync_ctrl_reg__MASK 0x01u -#define SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL -#define SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK -#define SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL +#define SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL +#define SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK +#define SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL /* SCSI_In_DBx */ #define SCSI_In_DBx__0__AG CYREG_PRT12_AG @@ -1069,8 +1041,8 @@ /* scsiTarget */ #define scsiTarget_StatusReg__0__MASK 0x01u #define scsiTarget_StatusReg__0__POS 0 -#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL -#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST +#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL +#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB14_15_ST #define scsiTarget_StatusReg__1__MASK 0x02u #define scsiTarget_StatusReg__1__POS 1 #define scsiTarget_StatusReg__2__MASK 0x04u @@ -1078,80 +1050,76 @@ #define scsiTarget_StatusReg__3__MASK 0x08u #define scsiTarget_StatusReg__3__POS 3 #define scsiTarget_StatusReg__MASK 0x0Fu -#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB12_MSK -#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL -#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL -#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL -#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB12_ST_CTL -#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB12_ST_CTL -#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB12_ST -#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL -#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST -#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB03_MSK -#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL -#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL -#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL -#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB03_ST_CTL -#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB03_ST_CTL -#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB03_ST -#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL -#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL -#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL -#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL -#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL -#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK -#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK -#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK -#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK -#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL -#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB03_CTL -#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL -#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB03_CTL -#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL -#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL -#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB03_MSK -#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL -#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB03_04_A0 -#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB03_04_A1 -#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB03_04_D0 -#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB03_04_D1 -#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL -#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB03_04_F0 -#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB03_04_F1 -#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB03_A0_A1 -#define scsiTarget_datapath__A0_REG CYREG_B0_UDB03_A0 -#define scsiTarget_datapath__A1_REG CYREG_B0_UDB03_A1 -#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB03_D0_D1 -#define scsiTarget_datapath__D0_REG CYREG_B0_UDB03_D0 -#define scsiTarget_datapath__D1_REG CYREG_B0_UDB03_D1 -#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB03_ACTL -#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB03_F0_F1 -#define scsiTarget_datapath__F0_REG CYREG_B0_UDB03_F0 -#define scsiTarget_datapath__F1_REG CYREG_B0_UDB03_F1 -#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL -#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL +#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB14_MSK +#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB14_ACTL +#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB14_ST +#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL +#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB13_14_ST +#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB13_MSK +#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL +#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL +#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB13_ACTL +#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB13_ST_CTL +#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB13_ST_CTL +#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB13_ST +#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL +#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL +#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL +#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL +#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL +#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK +#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK +#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK +#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK +#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL +#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB13_CTL +#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL +#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB13_CTL +#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL +#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL +#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB13_MSK +#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL +#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB13_14_A0 +#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB13_14_A1 +#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB13_14_D0 +#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB13_14_D1 +#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL +#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB13_14_F0 +#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB13_14_F1 +#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB13_A0_A1 +#define scsiTarget_datapath__A0_REG CYREG_B0_UDB13_A0 +#define scsiTarget_datapath__A1_REG CYREG_B0_UDB13_A1 +#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB13_D0_D1 +#define scsiTarget_datapath__D0_REG CYREG_B0_UDB13_D0 +#define scsiTarget_datapath__D1_REG CYREG_B0_UDB13_D1 +#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB13_ACTL +#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB13_F0_F1 +#define scsiTarget_datapath__F0_REG CYREG_B0_UDB13_F0 +#define scsiTarget_datapath__F1_REG CYREG_B0_UDB13_F1 +#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL +#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL /* SD_Clk_Ctl */ #define SD_Clk_Ctl_Sync_ctrl_reg__0__MASK 0x01u #define SD_Clk_Ctl_Sync_ctrl_reg__0__POS 0 -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK -#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL -#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK +#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL +#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL #define SD_Clk_Ctl_Sync_ctrl_reg__MASK 0x01u -#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL -#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK -#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL +#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL +#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK +#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL /* USBFS_ep_0 */ #define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 @@ -1166,20 +1134,20 @@ /* USBFS_ep_1 */ #define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_1__INTC_MASK 0x02u -#define USBFS_ep_1__INTC_NUMBER 1u +#define USBFS_ep_1__INTC_MASK 0x01u +#define USBFS_ep_1__INTC_NUMBER 0u #define USBFS_ep_1__INTC_PRIOR_NUM 7u -#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_1 +#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_0 #define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 /* USBFS_ep_2 */ #define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_2__INTC_MASK 0x04u -#define USBFS_ep_2__INTC_NUMBER 2u +#define USBFS_ep_2__INTC_MASK 0x02u +#define USBFS_ep_2__INTC_NUMBER 1u #define USBFS_ep_2__INTC_PRIOR_NUM 7u -#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_2 +#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_1 #define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 @@ -2754,7 +2722,7 @@ #define CYDEV_ECC_ENABLE 0 #define CYDEV_HEAP_SIZE 0x1000 #define CYDEV_INSTRUCT_CACHE_ENABLED 1 -#define CYDEV_INTR_RISING 0x00000001u +#define CYDEV_INTR_RISING 0x00000000u #define CYDEV_PROJ_TYPE 2 #define CYDEV_PROJ_TYPE_BOOTLOADER 1 #define CYDEV_PROJ_TYPE_LOADABLE 2 diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c index 13e06dca..d3600d72 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -121,7 +121,7 @@ static void CyClockStartupError(uint8 errorCode) } #endif -#define CY_CFG_BASE_ADDR_COUNT 35u +#define CY_CFG_BASE_ADDR_COUNT 33u CYPACKED typedef struct { uint8 offset; @@ -363,38 +363,36 @@ void cyfitter_cfg(void) { static const uint32 CYCODE cy_cfg_addr_table[] = { 0x40004502u, /* Base address: 0x40004500 Count: 2 */ - 0x40004F02u, /* Base address: 0x40004F00 Count: 2 */ 0x4000520Au, /* Base address: 0x40005200 Count: 10 */ 0x40006402u, /* Base address: 0x40006400 Count: 2 */ - 0x40010046u, /* Base address: 0x40010000 Count: 70 */ - 0x40010136u, /* Base address: 0x40010100 Count: 54 */ - 0x4001023Eu, /* Base address: 0x40010200 Count: 62 */ - 0x4001035Bu, /* Base address: 0x40010300 Count: 91 */ - 0x40010447u, /* Base address: 0x40010400 Count: 71 */ - 0x40010546u, /* Base address: 0x40010500 Count: 70 */ - 0x4001060Bu, /* Base address: 0x40010600 Count: 11 */ - 0x4001074Au, /* Base address: 0x40010700 Count: 74 */ - 0x40010906u, /* Base address: 0x40010900 Count: 6 */ - 0x40010A04u, /* Base address: 0x40010A00 Count: 4 */ - 0x40010B10u, /* Base address: 0x40010B00 Count: 16 */ - 0x40010C36u, /* Base address: 0x40010C00 Count: 54 */ - 0x40010D36u, /* Base address: 0x40010D00 Count: 54 */ - 0x40010F04u, /* Base address: 0x40010F00 Count: 4 */ + 0x40010101u, /* Base address: 0x40010100 Count: 1 */ + 0x40010308u, /* Base address: 0x40010300 Count: 8 */ + 0x40010442u, /* Base address: 0x40010400 Count: 66 */ + 0x4001053Cu, /* Base address: 0x40010500 Count: 60 */ + 0x40010604u, /* Base address: 0x40010600 Count: 4 */ + 0x40010747u, /* Base address: 0x40010700 Count: 71 */ + 0x40010908u, /* Base address: 0x40010900 Count: 8 */ + 0x40010A44u, /* Base address: 0x40010A00 Count: 68 */ + 0x40010B40u, /* Base address: 0x40010B00 Count: 64 */ + 0x40010C35u, /* Base address: 0x40010C00 Count: 53 */ + 0x40010D49u, /* Base address: 0x40010D00 Count: 73 */ + 0x40010E43u, /* Base address: 0x40010E00 Count: 67 */ + 0x40010F2Fu, /* Base address: 0x40010F00 Count: 47 */ 0x40011504u, /* Base address: 0x40011500 Count: 4 */ - 0x4001164Bu, /* Base address: 0x40011600 Count: 75 */ - 0x40011749u, /* Base address: 0x40011700 Count: 73 */ - 0x40011902u, /* Base address: 0x40011900 Count: 2 */ - 0x4001400Du, /* Base address: 0x40014000 Count: 13 */ - 0x4001410Eu, /* Base address: 0x40014100 Count: 14 */ - 0x4001420Cu, /* Base address: 0x40014200 Count: 12 */ - 0x4001430Du, /* Base address: 0x40014300 Count: 13 */ - 0x40014410u, /* Base address: 0x40014400 Count: 16 */ - 0x40014515u, /* Base address: 0x40014500 Count: 21 */ - 0x40014603u, /* Base address: 0x40014600 Count: 3 */ - 0x40014703u, /* Base address: 0x40014700 Count: 3 */ - 0x4001480Eu, /* Base address: 0x40014800 Count: 14 */ - 0x4001490Au, /* Base address: 0x40014900 Count: 10 */ - 0x40014C02u, /* Base address: 0x40014C00 Count: 2 */ + 0x40011648u, /* Base address: 0x40011600 Count: 72 */ + 0x40011740u, /* Base address: 0x40011700 Count: 64 */ + 0x40011904u, /* Base address: 0x40011900 Count: 4 */ + 0x4001400Bu, /* Base address: 0x40014000 Count: 11 */ + 0x4001410Fu, /* Base address: 0x40014100 Count: 15 */ + 0x40014207u, /* Base address: 0x40014200 Count: 7 */ + 0x40014303u, /* Base address: 0x40014300 Count: 3 */ + 0x4001440Cu, /* Base address: 0x40014400 Count: 12 */ + 0x40014516u, /* Base address: 0x40014500 Count: 22 */ + 0x40014608u, /* Base address: 0x40014600 Count: 8 */ + 0x40014708u, /* Base address: 0x40014700 Count: 8 */ + 0x4001480Au, /* Base address: 0x40014800 Count: 10 */ + 0x4001490Bu, /* Base address: 0x40014900 Count: 11 */ + 0x40014C01u, /* Base address: 0x40014C00 Count: 1 */ 0x40015006u, /* Base address: 0x40015000 Count: 6 */ 0x40015101u, /* Base address: 0x40015100 Count: 1 */ }; @@ -402,188 +400,403 @@ void cyfitter_cfg(void) static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x36u, 0x02u}, {0x7Eu, 0x02u}, - {0x01u, 0x80u}, - {0x0Au, 0x4Bu}, - {0x00u, 0x02u}, + {0x00u, 0x01u}, {0x01u, 0x03u}, - {0x18u, 0x08u}, + {0x18u, 0x04u}, {0x19u, 0x0Cu}, {0x1Cu, 0x61u}, - {0x20u, 0xC0u}, - {0x21u, 0x90u}, - {0x30u, 0x0Au}, - {0x31u, 0x09u}, + {0x20u, 0x98u}, + {0x21u, 0x38u}, + {0x30u, 0x03u}, + {0x31u, 0x05u}, {0x7Cu, 0x40u}, - {0x33u, 0x03u}, + {0x3Du, 0x03u}, {0x86u, 0x0Fu}, - {0x03u, 0x04u}, - {0x06u, 0x10u}, - {0x07u, 0x44u}, - {0x0Bu, 0x40u}, - {0x0Du, 0x44u}, - {0x0Eu, 0x0Cu}, - {0x0Fu, 0x22u}, - {0x12u, 0x01u}, + {0xE2u, 0x80u}, + {0x81u, 0x40u}, + {0x85u, 0x04u}, + {0xA0u, 0x04u}, + {0xACu, 0x04u}, + {0xE2u, 0x08u}, + {0xE6u, 0x25u}, + {0xEAu, 0x01u}, + {0xEEu, 0x02u}, + {0x07u, 0x04u}, + {0x0Bu, 0x04u}, + {0x0Du, 0x04u}, + {0x0Fu, 0x02u}, {0x13u, 0x03u}, - {0x16u, 0x10u}, - {0x18u, 0x10u}, - {0x1Au, 0x04u}, - {0x1Cu, 0x01u}, - {0x1Eu, 0x02u}, - {0x1Fu, 0x30u}, - {0x21u, 0x08u}, - {0x22u, 0x02u}, - {0x24u, 0x20u}, - {0x29u, 0x44u}, - {0x2Bu, 0x11u}, - {0x2Cu, 0x10u}, - {0x2Eu, 0x08u}, - {0x30u, 0x1Cu}, + {0x19u, 0x04u}, + {0x1Bu, 0x01u}, {0x31u, 0x07u}, - {0x32u, 0x03u}, - {0x33u, 0x08u}, - {0x36u, 0x20u}, - {0x37u, 0x70u}, - {0x3Eu, 0x44u}, - {0x3Fu, 0x04u}, {0x56u, 0x08u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x90u}, + {0x5Du, 0x90u}, + {0x5Fu, 0x01u}, + {0x80u, 0xD6u}, + {0x81u, 0x2Cu}, + {0x84u, 0x17u}, + {0x86u, 0x28u}, + {0x88u, 0xD2u}, + {0x89u, 0x31u}, + {0x8Au, 0x04u}, + {0x8Bu, 0x42u}, + {0x8Cu, 0xD6u}, + {0x8Du, 0x2Cu}, + {0x91u, 0xC0u}, + {0x94u, 0x29u}, + {0x96u, 0x46u}, + {0x97u, 0x2Cu}, + {0x98u, 0x20u}, + {0x99u, 0x40u}, + {0x9Au, 0xD0u}, + {0x9Bu, 0x2Fu}, + {0x9Cu, 0x04u}, + {0x9Du, 0x24u}, + {0xA0u, 0xD6u}, + {0xA1u, 0x08u}, + {0xA3u, 0x10u}, + {0xA4u, 0xD0u}, + {0xA5u, 0x24u}, + {0xA6u, 0x06u}, + {0xA7u, 0x08u}, + {0xA8u, 0x21u}, + {0xA9u, 0x11u}, + {0xAAu, 0x8Eu}, + {0xABu, 0x8Eu}, + {0xACu, 0x02u}, + {0xADu, 0x2Cu}, + {0xB0u, 0x01u}, + {0xB1u, 0xC1u}, + {0xB2u, 0x0Fu}, + {0xB3u, 0x31u}, + {0xB4u, 0xF0u}, + {0xB5u, 0x0Fu}, + {0xB6u, 0x08u}, + {0xB8u, 0x08u}, + {0xB9u, 0x02u}, + {0xBAu, 0x20u}, + {0xBBu, 0x0Cu}, + {0xBEu, 0x41u}, + {0xD4u, 0x09u}, + {0xD8u, 0x0Bu}, + {0xD9u, 0x0Bu}, + {0xDBu, 0x0Bu}, + {0xDCu, 0x99u}, + {0xDDu, 0x90u}, + {0xDFu, 0x01u}, + {0x04u, 0x29u}, + {0x06u, 0x02u}, + {0x0Eu, 0x28u}, + {0x0Fu, 0x02u}, + {0x17u, 0x65u}, + {0x1Cu, 0x10u}, + {0x1Du, 0x48u}, + {0x1Eu, 0x28u}, + {0x1Fu, 0x09u}, + {0x21u, 0x02u}, + {0x23u, 0x40u}, + {0x24u, 0x08u}, + {0x25u, 0x10u}, + {0x26u, 0x02u}, + {0x27u, 0x38u}, + {0x29u, 0xC0u}, + {0x2Du, 0x02u}, + {0x2Fu, 0x2Au}, + {0x31u, 0x02u}, + {0x32u, 0x10u}, + {0x34u, 0x01u}, + {0x36u, 0x02u}, + {0x37u, 0x54u}, + {0x39u, 0x48u}, + {0x3Au, 0x10u}, + {0x3Cu, 0x81u}, + {0x3Du, 0x20u}, + {0x3Eu, 0x01u}, + {0x58u, 0x80u}, + {0x5Du, 0x98u}, + {0x5Eu, 0x02u}, + {0x60u, 0x02u}, + {0x62u, 0x80u}, + {0x65u, 0x08u}, + {0x66u, 0x04u}, + {0x67u, 0x02u}, + {0x7Eu, 0x80u}, + {0x89u, 0x02u}, + {0x8Cu, 0x20u}, + {0x91u, 0x48u}, + {0x92u, 0x20u}, + {0x9Au, 0x10u}, + {0xA0u, 0x04u}, + {0xA4u, 0x10u}, + {0xAEu, 0x10u}, + {0xB0u, 0x10u}, + {0xB6u, 0x10u}, + {0xC0u, 0xF0u}, + {0xC2u, 0xE0u}, + {0xC4u, 0xF0u}, + {0xCAu, 0xF0u}, + {0xCCu, 0xF5u}, + {0xCEu, 0xBEu}, + {0xD6u, 0xF8u}, + {0xD8u, 0x18u}, + {0xDEu, 0x80u}, + {0xE2u, 0x40u}, + {0xE6u, 0x20u}, + {0xEAu, 0x02u}, + {0xEEu, 0x08u}, + {0xD4u, 0x40u}, + {0xDBu, 0x0Bu}, + {0xDDu, 0x90u}, + {0xDFu, 0x01u}, + {0x04u, 0x20u}, + {0x06u, 0x02u}, + {0x07u, 0x60u}, + {0x0Eu, 0xA1u}, + {0x0Fu, 0x04u}, + {0x15u, 0x14u}, + {0x17u, 0x09u}, + {0x1Fu, 0x08u}, + {0x25u, 0x40u}, + {0x26u, 0x40u}, + {0x27u, 0x80u}, + {0x2Cu, 0x80u}, + {0x2Fu, 0x2Au}, + {0x36u, 0x02u}, + {0x37u, 0xA8u}, + {0x3Cu, 0x10u}, + {0x3Du, 0x80u}, + {0x3Eu, 0x01u}, + {0x3Fu, 0x04u}, + {0x45u, 0x88u}, + {0x46u, 0x40u}, + {0x47u, 0x20u}, + {0x4Cu, 0x04u}, + {0x4Du, 0x0Au}, + {0x4Fu, 0x06u}, + {0x55u, 0x20u}, + {0x56u, 0x84u}, + {0x61u, 0x20u}, + {0x62u, 0x08u}, + {0x63u, 0x01u}, + {0x65u, 0x80u}, + {0x6Cu, 0x10u}, + {0x6Du, 0x11u}, + {0x6Eu, 0x09u}, + {0x6Fu, 0x27u}, + {0x74u, 0xC0u}, + {0x76u, 0x02u}, + {0x78u, 0x02u}, + {0x7Eu, 0x80u}, + {0x81u, 0x48u}, + {0x90u, 0x18u}, + {0x92u, 0x80u}, + {0x93u, 0x40u}, + {0x94u, 0x20u}, + {0x96u, 0x01u}, + {0x98u, 0x23u}, + {0x9Bu, 0x38u}, + {0x9Du, 0x02u}, + {0x9Eu, 0x06u}, + {0x9Fu, 0x45u}, + {0xA0u, 0x04u}, + {0xA1u, 0x08u}, + {0xA2u, 0x90u}, + {0xA4u, 0x50u}, + {0xA6u, 0x01u}, + {0xA7u, 0x23u}, + {0xAAu, 0x40u}, + {0xACu, 0x80u}, + {0xB1u, 0x12u}, + {0xC0u, 0xF0u}, + {0xC2u, 0xF0u}, + {0xC4u, 0x70u}, + {0xCAu, 0xF0u}, + {0xCCu, 0xF0u}, + {0xCEu, 0xF0u}, + {0xD0u, 0xF0u}, + {0xD2u, 0x20u}, + {0xD8u, 0x1Eu}, + {0xDEu, 0x81u}, + {0xE8u, 0x40u}, + {0xEEu, 0x03u}, + {0x9Cu, 0x04u}, + {0xA7u, 0x40u}, + {0xAEu, 0x11u}, + {0xB0u, 0x80u}, + {0xB6u, 0x10u}, + {0xE8u, 0x40u}, + {0xEAu, 0x02u}, + {0xEEu, 0x01u}, + {0x04u, 0x24u}, + {0x06u, 0x12u}, + {0x07u, 0x03u}, + {0x0Au, 0x24u}, + {0x0Bu, 0x04u}, + {0x0Eu, 0x03u}, + {0x10u, 0x40u}, + {0x12u, 0x80u}, + {0x13u, 0x20u}, + {0x16u, 0x80u}, + {0x1Au, 0x18u}, + {0x1Bu, 0x24u}, + {0x1Fu, 0x18u}, + {0x21u, 0x40u}, + {0x22u, 0x20u}, + {0x25u, 0x24u}, + {0x26u, 0x04u}, + {0x27u, 0x12u}, + {0x29u, 0x80u}, + {0x2Au, 0x40u}, + {0x2Cu, 0x24u}, + {0x2Du, 0x24u}, + {0x2Eu, 0x09u}, + {0x2Fu, 0x09u}, + {0x30u, 0x07u}, + {0x31u, 0x80u}, + {0x33u, 0x40u}, + {0x34u, 0x38u}, + {0x35u, 0x07u}, + {0x36u, 0xC0u}, + {0x37u, 0x38u}, + {0x3Eu, 0x40u}, + {0x3Fu, 0x05u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, {0x5Cu, 0x99u}, - {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x81u, 0x33u}, - {0x82u, 0x02u}, - {0x83u, 0xCCu}, - {0x85u, 0x55u}, - {0x86u, 0x20u}, - {0x87u, 0xAAu}, - {0x88u, 0x20u}, - {0x89u, 0x96u}, - {0x8Au, 0x08u}, - {0x8Bu, 0x69u}, - {0x8Fu, 0xFFu}, - {0x90u, 0x20u}, - {0x92u, 0x10u}, + {0x85u, 0x33u}, + {0x86u, 0xFFu}, + {0x87u, 0xCCu}, + {0x89u, 0xFFu}, + {0x8Du, 0x0Fu}, + {0x8Eu, 0xFFu}, + {0x8Fu, 0xF0u}, + {0x90u, 0x96u}, + {0x92u, 0x69u}, {0x93u, 0xFFu}, - {0x95u, 0xFFu}, - {0x96u, 0x20u}, - {0x9Au, 0x18u}, - {0x9Eu, 0x07u}, - {0xA0u, 0x07u}, - {0xA4u, 0x01u}, - {0xA5u, 0x0Fu}, - {0xA7u, 0xF0u}, - {0xA8u, 0x04u}, - {0xB2u, 0x07u}, - {0xB4u, 0x38u}, - {0xB7u, 0xFFu}, + {0x94u, 0xFFu}, + {0x98u, 0x33u}, + {0x9Au, 0xCCu}, + {0x9Du, 0x96u}, + {0x9Fu, 0x69u}, + {0xA0u, 0x55u}, + {0xA1u, 0x55u}, + {0xA2u, 0xAAu}, + {0xA3u, 0xAAu}, + {0xA7u, 0xFFu}, + {0xACu, 0x0Fu}, + {0xAEu, 0xF0u}, + {0xB2u, 0xFFu}, + {0xB3u, 0xFFu}, {0xBEu, 0x04u}, - {0xBFu, 0x40u}, + {0xBFu, 0x04u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x09u}, {0xDFu, 0x01u}, - {0x00u, 0x40u}, - {0x03u, 0x10u}, - {0x05u, 0x10u}, - {0x06u, 0x80u}, - {0x07u, 0x20u}, - {0x09u, 0x08u}, - {0x0Au, 0x04u}, - {0x0Bu, 0x82u}, - {0x0Du, 0x24u}, - {0x0Eu, 0x01u}, - {0x0Fu, 0x40u}, - {0x10u, 0x40u}, - {0x13u, 0x48u}, - {0x14u, 0x90u}, - {0x16u, 0x04u}, + {0x00u, 0x50u}, + {0x03u, 0x20u}, + {0x05u, 0x04u}, + {0x06u, 0x20u}, + {0x07u, 0x01u}, + {0x0Au, 0x64u}, + {0x0Eu, 0x80u}, + {0x0Fu, 0xA4u}, + {0x10u, 0xA5u}, + {0x13u, 0x40u}, + {0x14u, 0x40u}, + {0x15u, 0x40u}, {0x18u, 0x40u}, - {0x19u, 0x84u}, - {0x1Du, 0x20u}, - {0x1Fu, 0x14u}, - {0x20u, 0x02u}, - {0x21u, 0xC0u}, - {0x22u, 0x03u}, - {0x23u, 0x10u}, - {0x25u, 0x40u}, - {0x29u, 0x10u}, - {0x2Au, 0x01u}, - {0x2Fu, 0x20u}, - {0x31u, 0x80u}, - {0x32u, 0x01u}, - {0x36u, 0x06u}, - {0x39u, 0x18u}, - {0x3Au, 0x02u}, - {0x3Bu, 0x40u}, - {0x3Cu, 0x02u}, - {0x3Du, 0x60u}, - {0x3Fu, 0x0Cu}, - {0x5Bu, 0x40u}, - {0x60u, 0x02u}, - {0x6Du, 0x40u}, - {0x80u, 0x40u}, - {0x81u, 0x80u}, - {0x83u, 0x20u}, - {0x86u, 0x01u}, - {0x8Bu, 0x08u}, - {0x8Eu, 0x01u}, - {0xC0u, 0x75u}, - {0xC2u, 0xFFu}, - {0xC4u, 0x7Du}, - {0xCAu, 0x45u}, - {0xCCu, 0xC9u}, - {0xCEu, 0xFFu}, - {0xD6u, 0x08u}, - {0xD8u, 0x08u}, - {0xE4u, 0x05u}, - {0x01u, 0x03u}, - {0x03u, 0x0Cu}, - {0x25u, 0x05u}, - {0x27u, 0x0Au}, - {0x29u, 0x06u}, - {0x2Bu, 0x09u}, - {0x35u, 0x0Fu}, - {0x3Fu, 0x10u}, - {0x59u, 0x04u}, - {0x5Fu, 0x01u}, - {0x85u, 0x10u}, - {0x87u, 0x2Du}, + {0x1Au, 0x06u}, + {0x1Bu, 0x10u}, + {0x1Fu, 0x04u}, + {0x22u, 0x46u}, + {0x23u, 0x04u}, + {0x25u, 0x08u}, + {0x28u, 0x81u}, + {0x2Au, 0x10u}, + {0x2Bu, 0x20u}, + {0x2Cu, 0x40u}, + {0x2Eu, 0x04u}, + {0x30u, 0x42u}, + {0x31u, 0x20u}, + {0x32u, 0x40u}, + {0x36u, 0x40u}, + {0x37u, 0x01u}, + {0x39u, 0x10u}, + {0x3Bu, 0x04u}, + {0x3Du, 0x40u}, + {0x3Eu, 0x20u}, + {0x3Fu, 0x04u}, + {0x6Au, 0x40u}, + {0x6Fu, 0x01u}, + {0x8Cu, 0x40u}, + {0x90u, 0x10u}, + {0x91u, 0x50u}, + {0x93u, 0x40u}, + {0x96u, 0x08u}, + {0x97u, 0x0Cu}, + {0x99u, 0x04u}, + {0x9Cu, 0x40u}, + {0x9Fu, 0x01u}, + {0xA0u, 0xA2u}, + {0xA1u, 0x20u}, + {0xA3u, 0x20u}, + {0xA5u, 0x08u}, + {0xA6u, 0x02u}, + {0xA7u, 0x50u}, + {0xADu, 0x50u}, + {0xB2u, 0xC0u}, + {0xB3u, 0x08u}, + {0xB4u, 0x42u}, + {0xC0u, 0xA7u}, + {0xC2u, 0x7Eu}, + {0xC4u, 0x9Fu}, + {0xCAu, 0xCFu}, + {0xCCu, 0x9Du}, + {0xCEu, 0x76u}, + {0xE2u, 0x40u}, + {0xEAu, 0x40u}, + {0xECu, 0x80u}, + {0x80u, 0x10u}, + {0x84u, 0x0Eu}, {0x89u, 0x01u}, - {0x8Bu, 0x02u}, - {0x8Cu, 0x01u}, - {0x8Du, 0x67u}, - {0x8Fu, 0x18u}, - {0x90u, 0x04u}, - {0x92u, 0x03u}, - {0x96u, 0x12u}, - {0x98u, 0x03u}, - {0x9Au, 0x14u}, - {0x9Fu, 0x40u}, - {0xA1u, 0x02u}, - {0xA4u, 0x08u}, - {0xA5u, 0x02u}, - {0xA9u, 0x16u}, - {0xAAu, 0x07u}, - {0xABu, 0x48u}, - {0xAFu, 0x77u}, - {0xB0u, 0x08u}, - {0xB1u, 0x07u}, - {0xB3u, 0x70u}, - {0xB4u, 0x07u}, - {0xB5u, 0x08u}, - {0xB6u, 0x10u}, + {0x8Au, 0x0Eu}, + {0x8Bu, 0x92u}, + {0x8Cu, 0x04u}, + {0x8Du, 0x19u}, + {0x8Fu, 0xA4u}, + {0x90u, 0x0Cu}, + {0x91u, 0x08u}, + {0x92u, 0x01u}, + {0x94u, 0x02u}, + {0x96u, 0x04u}, + {0x97u, 0x3Fu}, + {0x9Au, 0x0Bu}, + {0xA4u, 0x04u}, + {0xA7u, 0x04u}, + {0xA9u, 0x26u}, + {0xABu, 0x99u}, + {0xADu, 0x40u}, + {0xB0u, 0x10u}, + {0xB1u, 0x38u}, + {0xB3u, 0x40u}, + {0xB4u, 0x0Eu}, + {0xB5u, 0x07u}, + {0xB6u, 0x01u}, + {0xB7u, 0x80u}, {0xBEu, 0x41u}, - {0xBFu, 0x10u}, - {0xC0u, 0x34u}, - {0xC1u, 0x02u}, - {0xC2u, 0x60u}, - {0xC5u, 0xCDu}, - {0xC6u, 0xF2u}, - {0xC7u, 0x0Eu}, + {0xBFu, 0x44u}, + {0xC0u, 0x26u}, + {0xC1u, 0x04u}, + {0xC2u, 0x50u}, + {0xC5u, 0xD2u}, + {0xC6u, 0xCEu}, + {0xC7u, 0x0Fu}, {0xC8u, 0x1Fu}, {0xC9u, 0xFFu}, {0xCAu, 0xFFu}, @@ -602,743 +815,452 @@ void cyfitter_cfg(void) {0xE8u, 0x40u}, {0xE9u, 0x40u}, {0xEEu, 0x08u}, - {0x01u, 0x40u}, - {0x03u, 0x01u}, - {0x09u, 0x08u}, - {0x0Au, 0x04u}, - {0x0Bu, 0x40u}, - {0x12u, 0x08u}, + {0x00u, 0x80u}, + {0x02u, 0x80u}, + {0x03u, 0x28u}, + {0x04u, 0x08u}, + {0x07u, 0x10u}, + {0x09u, 0x20u}, + {0x0Bu, 0x60u}, + {0x12u, 0x10u}, {0x13u, 0x08u}, - {0x18u, 0x40u}, - {0x19u, 0x10u}, - {0x1Au, 0x0Cu}, - {0x1Bu, 0x40u}, - {0x20u, 0x28u}, - {0x21u, 0x0Du}, + {0x19u, 0x52u}, + {0x1Bu, 0x20u}, + {0x20u, 0x42u}, + {0x21u, 0x31u}, + {0x22u, 0x08u}, {0x23u, 0x40u}, - {0x24u, 0x08u}, - {0x25u, 0x10u}, - {0x27u, 0x04u}, - {0x29u, 0x1Au}, - {0x2Bu, 0x02u}, - {0x2Du, 0x20u}, - {0x2Fu, 0x10u}, - {0x33u, 0x80u}, - {0x38u, 0x20u}, - {0x39u, 0x08u}, - {0x3Bu, 0x40u}, - {0x3Fu, 0x01u}, - {0x41u, 0x05u}, - {0x42u, 0x04u}, - {0x48u, 0x84u}, - {0x49u, 0x0Au}, - {0x50u, 0x08u}, - {0x52u, 0x20u}, + {0x28u, 0x02u}, + {0x29u, 0x18u}, + {0x33u, 0x09u}, + {0x38u, 0x50u}, + {0x39u, 0x20u}, + {0x40u, 0x40u}, + {0x41u, 0x10u}, + {0x48u, 0x41u}, + {0x49u, 0x19u}, + {0x50u, 0x04u}, + {0x52u, 0x10u}, {0x53u, 0x80u}, - {0x58u, 0x24u}, - {0x59u, 0x80u}, - {0x5Bu, 0x02u}, - {0x60u, 0x48u}, - {0x61u, 0x80u}, - {0x63u, 0x10u}, - {0x68u, 0x02u}, - {0x69u, 0x10u}, - {0x6Bu, 0x50u}, - {0x71u, 0x01u}, - {0x72u, 0x02u}, - {0x73u, 0x24u}, - {0x80u, 0x06u}, - {0x81u, 0x40u}, - {0x83u, 0x01u}, - {0x85u, 0x09u}, - {0x86u, 0x04u}, - {0x87u, 0x08u}, - {0x89u, 0x04u}, - {0x8Au, 0x01u}, - {0x8Eu, 0x28u}, - {0x8Fu, 0x02u}, - {0x90u, 0x20u}, - {0x91u, 0xC0u}, - {0x92u, 0x02u}, - {0x93u, 0x38u}, - {0x95u, 0x18u}, - {0x96u, 0x05u}, - {0x97u, 0xC0u}, - {0x98u, 0x02u}, - {0x99u, 0x80u}, - {0x9Cu, 0xD0u}, - {0x9Du, 0x10u}, - {0x9Eu, 0x86u}, - {0x9Fu, 0x30u}, - {0xA1u, 0x40u}, - {0xA3u, 0x24u}, - {0xA5u, 0x18u}, - {0xA6u, 0x04u}, - {0xA8u, 0x10u}, - {0xB3u, 0x04u}, - {0xB5u, 0x24u}, - {0xB7u, 0x41u}, - {0xC0u, 0x01u}, + {0x59u, 0x02u}, + {0x5Au, 0xA8u}, + {0x60u, 0x04u}, + {0x62u, 0x4Au}, + {0x68u, 0x82u}, + {0x69u, 0x14u}, + {0x70u, 0x20u}, + {0x72u, 0x80u}, + {0x73u, 0x12u}, + {0x81u, 0x10u}, + {0x84u, 0x01u}, + {0x87u, 0x10u}, + {0x8Bu, 0x11u}, + {0x90u, 0x04u}, + {0x91u, 0x40u}, + {0x92u, 0xA0u}, + {0x95u, 0x26u}, + {0x97u, 0x4Cu}, + {0x99u, 0x04u}, + {0x9Cu, 0x41u}, + {0x9Du, 0x11u}, + {0x9Eu, 0x80u}, + {0x9Fu, 0x1Bu}, + {0xA5u, 0x28u}, + {0xA7u, 0xF0u}, + {0xA8u, 0x40u}, + {0xAAu, 0x10u}, + {0xACu, 0x40u}, + {0xAEu, 0x01u}, + {0xAFu, 0x04u}, + {0xB2u, 0x02u}, + {0xB7u, 0x10u}, + {0xC0u, 0x0Fu}, {0xC2u, 0x0Eu}, - {0xC4u, 0x06u}, - {0xCAu, 0x6Fu}, - {0xCCu, 0x08u}, - {0xCEu, 0x8Eu}, - {0xD0u, 0x07u}, - {0xD2u, 0x04u}, + {0xC4u, 0x04u}, + {0xCAu, 0x0Eu}, + {0xCCu, 0x03u}, + {0xCEu, 0x0Cu}, + {0xD0u, 0x05u}, + {0xD2u, 0x0Cu}, {0xD6u, 0x0Fu}, {0xD8u, 0x0Fu}, - {0xE0u, 0x06u}, - {0xE2u, 0x08u}, - {0xE4u, 0x0Fu}, - {0xEAu, 0x04u}, - {0xEEu, 0x40u}, - {0x00u, 0x08u}, - {0x05u, 0xFFu}, - {0x06u, 0x03u}, - {0x0Au, 0x04u}, - {0x0Du, 0x33u}, - {0x0Fu, 0xCCu}, - {0x10u, 0x04u}, - {0x12u, 0x02u}, - {0x13u, 0xFFu}, - {0x15u, 0x96u}, - {0x17u, 0x69u}, - {0x18u, 0x04u}, - {0x1Au, 0x01u}, - {0x20u, 0x08u}, - {0x25u, 0x0Fu}, - {0x26u, 0x04u}, - {0x27u, 0xF0u}, - {0x28u, 0x08u}, - {0x29u, 0x55u}, - {0x2Bu, 0xAAu}, - {0x2Cu, 0x08u}, - {0x2Fu, 0xFFu}, - {0x30u, 0x08u}, - {0x33u, 0xFFu}, - {0x34u, 0x07u}, - {0x38u, 0x02u}, - {0x3Eu, 0x01u}, - {0x3Fu, 0x04u}, - {0x58u, 0x04u}, - {0x59u, 0x04u}, - {0x5Cu, 0x09u}, - {0x5Fu, 0x01u}, - {0x81u, 0x02u}, - {0x83u, 0x0Du}, - {0x84u, 0x04u}, - {0x86u, 0x03u}, - {0x87u, 0x10u}, - {0x88u, 0x08u}, - {0x89u, 0x02u}, - {0x8Au, 0x03u}, - {0x8Bu, 0x54u}, - {0x8Du, 0x8Du}, - {0x91u, 0x8Du}, - {0x94u, 0x01u}, - {0x95u, 0x62u}, - {0x96u, 0x02u}, - {0x97u, 0x08u}, - {0x99u, 0x01u}, - {0x9Au, 0x01u}, - {0x9Bu, 0x32u}, - {0x9Eu, 0x0Cu}, - {0xA3u, 0x80u}, - {0xA5u, 0x8Du}, - {0xA9u, 0x8Du}, - {0xADu, 0x0Du}, - {0xAEu, 0x12u}, - {0xAFu, 0x80u}, - {0xB1u, 0x0Fu}, - {0xB3u, 0x70u}, - {0xB4u, 0x10u}, - {0xB5u, 0x80u}, - {0xB6u, 0x0Fu}, - {0xBBu, 0x02u}, - {0xBFu, 0x10u}, - {0xD4u, 0x40u}, - {0xD8u, 0x0Bu}, - {0xD9u, 0x0Bu}, - {0xDBu, 0x0Bu}, - {0xDCu, 0x99u}, - {0xDDu, 0x90u}, - {0xDFu, 0x01u}, - {0x00u, 0x24u}, - {0x02u, 0x40u}, - {0x04u, 0x28u}, - {0x06u, 0x04u}, - {0x0Au, 0x08u}, - {0x0Bu, 0x40u}, - {0x0Eu, 0x25u}, - {0x10u, 0x80u}, - {0x11u, 0x80u}, - {0x13u, 0x24u}, - {0x16u, 0x02u}, - {0x18u, 0x04u}, - {0x19u, 0x20u}, - {0x1Au, 0x80u}, - {0x1Eu, 0x05u}, - {0x23u, 0x20u}, - {0x25u, 0x25u}, - {0x2Bu, 0x25u}, - {0x2Cu, 0x20u}, - {0x2Du, 0x02u}, - {0x2Eu, 0x10u}, - {0x2Fu, 0x02u}, - {0x33u, 0x05u}, - {0x34u, 0x10u}, - {0x36u, 0x19u}, - {0x39u, 0x84u}, - {0x3Cu, 0x80u}, - {0x3Du, 0x2Au}, - {0x45u, 0x20u}, - {0x46u, 0x08u}, - {0x66u, 0x28u}, - {0x67u, 0x01u}, - {0x7Cu, 0x02u}, - {0x80u, 0x80u}, - {0x8Du, 0x04u}, - {0x91u, 0x8Cu}, - {0x92u, 0x08u}, - {0x93u, 0x4Cu}, - {0x96u, 0x01u}, - {0x97u, 0x80u}, - {0x98u, 0x02u}, - {0x99u, 0x11u}, - {0x9Bu, 0x45u}, - {0x9Cu, 0xD0u}, - {0x9Du, 0x20u}, - {0x9Eu, 0x84u}, - {0xA0u, 0x10u}, - {0xA1u, 0x40u}, - {0xA3u, 0x24u}, - {0xA6u, 0x04u}, - {0xA8u, 0x80u}, - {0xACu, 0x0Cu}, - {0xADu, 0x80u}, - {0xB1u, 0x04u}, - {0xB3u, 0x02u}, - {0xB4u, 0x28u}, - {0xB7u, 0x40u}, - {0xC0u, 0x6Eu}, - {0xC2u, 0xEAu}, - {0xC4u, 0x8Fu}, - {0xCAu, 0xFEu}, - {0xCCu, 0xE3u}, - {0xCEu, 0xFAu}, - {0xD8u, 0x70u}, - {0xDEu, 0x80u}, - {0xE2u, 0x04u}, - {0xE6u, 0x40u}, - {0xE8u, 0x04u}, - {0xEAu, 0x08u}, - {0xEEu, 0x4Au}, - {0x82u, 0x04u}, - {0x8Au, 0x04u}, - {0x8Eu, 0x03u}, - {0x98u, 0x04u}, - {0x9Au, 0x01u}, - {0xACu, 0x04u}, - {0xAEu, 0x02u}, - {0xB0u, 0x07u}, - {0xD8u, 0x04u}, - {0xDCu, 0x09u}, - {0xDFu, 0x01u}, - {0x00u, 0x60u}, - {0x03u, 0x40u}, - {0x04u, 0x29u}, - {0x06u, 0x02u}, - {0x0Au, 0x08u}, - {0x0Du, 0x20u}, - {0x0Eu, 0x62u}, - {0x13u, 0x40u}, - {0x17u, 0x15u}, - {0x18u, 0x40u}, - {0x1Bu, 0x01u}, - {0x1Eu, 0x01u}, - {0x24u, 0x2Eu}, - {0x25u, 0x10u}, - {0x26u, 0x08u}, - {0x27u, 0x02u}, - {0x2Cu, 0x20u}, - {0x2Eu, 0x10u}, - {0x36u, 0x59u}, - {0x39u, 0x04u}, - {0x3Au, 0x08u}, - {0x3Cu, 0x81u}, - {0x3Du, 0x20u}, - {0x3Fu, 0x08u}, - {0x45u, 0x1Au}, - {0x4Cu, 0x01u}, - {0x4Du, 0x02u}, - {0x4Eu, 0x08u}, - {0x4Fu, 0x09u}, - {0x56u, 0x2Au}, - {0x65u, 0x20u}, - {0x6Cu, 0x20u}, - {0x6Du, 0x03u}, - {0x6Eu, 0xD2u}, - {0x6Fu, 0x16u}, - {0x74u, 0x40u}, - {0x77u, 0x01u}, - {0x7Cu, 0x02u}, - {0x81u, 0x02u}, - {0x8Cu, 0x40u}, - {0x8Eu, 0x04u}, - {0x91u, 0x08u}, - {0x92u, 0x08u}, - {0x93u, 0x48u}, - {0x94u, 0x28u}, - {0x96u, 0x10u}, - {0x97u, 0x01u}, - {0x98u, 0x02u}, - {0x99u, 0x11u}, - {0x9Bu, 0x40u}, - {0x9Cu, 0xC0u}, - {0x9Du, 0x02u}, - {0x9Eu, 0x22u}, - {0xA0u, 0x10u}, - {0xA4u, 0x60u}, - {0xA5u, 0x10u}, - {0xA6u, 0x1Du}, - {0xA7u, 0x03u}, - {0xA9u, 0x10u}, - {0xAAu, 0xC0u}, - {0xAFu, 0x40u}, - {0xB2u, 0x40u}, - {0xB4u, 0x04u}, - {0xC0u, 0xFBu}, - {0xC2u, 0xF2u}, - {0xC4u, 0x71u}, - {0xCAu, 0x60u}, - {0xCCu, 0xF0u}, - {0xCEu, 0xF0u}, - {0xD0u, 0xE0u}, - {0xD2u, 0x30u}, - {0xD8u, 0x20u}, - {0xDEu, 0x80u}, - {0xEEu, 0x42u}, - {0x8Du, 0x40u}, - {0x95u, 0x40u}, - {0xAFu, 0x08u}, - {0xB3u, 0x40u}, - {0xE0u, 0x40u}, - {0xEEu, 0x80u}, - {0x38u, 0x08u}, - {0x3Eu, 0x04u}, - {0x58u, 0x04u}, - {0x5Fu, 0x01u}, - {0x1Bu, 0x08u}, - {0x80u, 0x10u}, - {0x90u, 0x20u}, - {0x93u, 0x80u}, - {0x95u, 0x40u}, - {0xA8u, 0x20u}, - {0xABu, 0x08u}, - {0xACu, 0x05u}, - {0xADu, 0x04u}, - {0xB0u, 0x04u}, - {0xB2u, 0x20u}, - {0xB4u, 0x40u}, - {0xB7u, 0x90u}, - {0xEAu, 0x60u}, - {0xECu, 0x90u}, - {0xEEu, 0x04u}, - {0x04u, 0x0Fu}, - {0x05u, 0x04u}, - {0x06u, 0xF0u}, - {0x07u, 0x02u}, - {0x0Cu, 0x55u}, - {0x0Du, 0x04u}, - {0x0Eu, 0xAAu}, - {0x0Fu, 0x01u}, - {0x10u, 0x33u}, - {0x12u, 0xCCu}, + {0xE2u, 0x02u}, + {0xE6u, 0x21u}, + {0xE8u, 0x02u}, + {0xECu, 0x0Cu}, + {0x01u, 0x04u}, + {0x03u, 0x01u}, + {0x04u, 0x24u}, + {0x05u, 0x10u}, + {0x06u, 0x12u}, + {0x0Bu, 0x04u}, + {0x0Eu, 0x18u}, + {0x0Fu, 0x04u}, + {0x10u, 0x40u}, {0x13u, 0x03u}, - {0x17u, 0x04u}, - {0x19u, 0x08u}, - {0x1Au, 0xFFu}, - {0x1Cu, 0x69u}, - {0x1Eu, 0x96u}, - {0x20u, 0xFFu}, - {0x2Bu, 0x04u}, - {0x2Cu, 0xFFu}, + {0x15u, 0x10u}, + {0x16u, 0x03u}, + {0x19u, 0x04u}, + {0x1Au, 0x24u}, + {0x1Bu, 0x02u}, + {0x1Du, 0x10u}, + {0x21u, 0x20u}, + {0x22u, 0x04u}, + {0x26u, 0x20u}, + {0x29u, 0x08u}, + {0x2Cu, 0x24u}, + {0x2Du, 0x10u}, + {0x2Eu, 0x09u}, + {0x30u, 0x38u}, + {0x31u, 0x07u}, + {0x32u, 0x07u}, + {0x33u, 0x10u}, + {0x34u, 0x40u}, {0x35u, 0x08u}, - {0x36u, 0xFFu}, - {0x37u, 0x07u}, - {0x3Eu, 0x40u}, - {0x3Fu, 0x10u}, + {0x37u, 0x20u}, + {0x39u, 0x08u}, + {0x3Eu, 0x10u}, + {0x3Fu, 0x54u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x90u}, + {0x5Cu, 0x99u}, {0x5Fu, 0x01u}, - {0x84u, 0x0Fu}, - {0x86u, 0xF0u}, - {0x88u, 0x69u}, - {0x89u, 0x02u}, - {0x8Au, 0x96u}, - {0x8Cu, 0x55u}, - {0x8Eu, 0xAAu}, - {0x90u, 0x33u}, - {0x92u, 0xCCu}, - {0x95u, 0x01u}, - {0x9Eu, 0xFFu}, - {0xA1u, 0x04u}, - {0xA2u, 0xFFu}, - {0xA5u, 0x08u}, - {0xAEu, 0xFFu}, - {0xB1u, 0x04u}, - {0xB2u, 0xFFu}, - {0xB3u, 0x01u}, - {0xB5u, 0x02u}, - {0xB7u, 0x08u}, - {0xBEu, 0x04u}, - {0xBFu, 0x55u}, + {0x85u, 0x33u}, + {0x86u, 0xFFu}, + {0x87u, 0xCCu}, + {0x89u, 0xFFu}, + {0x8Du, 0x0Fu}, + {0x8Eu, 0xFFu}, + {0x8Fu, 0xF0u}, + {0x90u, 0x69u}, + {0x92u, 0x96u}, + {0x93u, 0xFFu}, + {0x96u, 0xFFu}, + {0x98u, 0x33u}, + {0x9Au, 0xCCu}, + {0x9Du, 0x69u}, + {0x9Fu, 0x96u}, + {0xA0u, 0x55u}, + {0xA1u, 0x55u}, + {0xA2u, 0xAAu}, + {0xA3u, 0xAAu}, + {0xA9u, 0xFFu}, + {0xACu, 0x0Fu}, + {0xAEu, 0xF0u}, + {0xB0u, 0xFFu}, + {0xB7u, 0xFFu}, + {0xBEu, 0x01u}, + {0xBFu, 0x40u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDFu, 0x01u}, - {0x01u, 0x08u}, - {0x03u, 0x09u}, - {0x05u, 0x08u}, + {0x00u, 0x40u}, + {0x01u, 0x40u}, + {0x03u, 0x20u}, + {0x05u, 0x04u}, {0x07u, 0x01u}, - {0x08u, 0x81u}, - {0x0Au, 0x80u}, - {0x0Cu, 0x01u}, - {0x0Eu, 0x0Au}, - {0x11u, 0x40u}, - {0x12u, 0x80u}, - {0x14u, 0x80u}, + {0x08u, 0x01u}, + {0x09u, 0x20u}, + {0x0Au, 0x10u}, + {0x0Cu, 0x08u}, + {0x0Eu, 0x80u}, + {0x0Fu, 0xA4u}, + {0x11u, 0x04u}, + {0x13u, 0x42u}, + {0x14u, 0x40u}, {0x15u, 0x40u}, - {0x18u, 0x20u}, - {0x1Fu, 0x40u}, - {0x20u, 0x4Au}, - {0x21u, 0x04u}, - {0x26u, 0x20u}, - {0x27u, 0x03u}, - {0x28u, 0x20u}, - {0x2Bu, 0x80u}, - {0x2Cu, 0x04u}, - {0x33u, 0x04u}, - {0x36u, 0x08u}, - {0x37u, 0x12u}, - {0x3Au, 0x20u}, - {0x3Du, 0x84u}, - {0x5Du, 0x22u}, - {0x5Fu, 0x88u}, - {0x6Cu, 0x01u}, - {0x82u, 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0x03u}, - {0x02u, 0x01u}, - {0x04u, 0x40u}, - {0x06u, 0x20u}, - {0x0Bu, 0x11u}, - {0x0Fu, 0x82u}, - {0x83u, 0x01u}, - {0x86u, 0x20u}, - {0x8Bu, 0x11u}, - {0x8Du, 0x20u}, - {0x8Fu, 0x01u}, - {0x97u, 0x02u}, - {0x9Eu, 0x01u}, - {0xA1u, 0x20u}, - {0xABu, 0x40u}, - {0xB3u, 0x80u}, + {0x01u, 0x20u}, + {0x06u, 0x80u}, + {0x07u, 0x01u}, + {0x09u, 0x01u}, + {0x0Au, 0x02u}, + {0x0Cu, 0x80u}, + {0x0Eu, 0x20u}, + {0x82u, 0x40u}, + {0x87u, 0x01u}, + {0x8Bu, 0x40u}, + {0x93u, 0x40u}, + {0x98u, 0x80u}, + {0xA4u, 0x80u}, + {0xABu, 0x80u}, + {0xAFu, 0x24u}, + {0xB2u, 0x80u}, + {0xB4u, 0x10u}, {0xC0u, 0x07u}, {0xC2u, 0x0Fu}, - {0xE0u, 0x02u}, - {0xE2u, 0x01u}, - {0xE6u, 0x03u}, - {0xECu, 0x04u}, - {0xA8u, 0x40u}, - {0xB7u, 0x40u}, - {0xEEu, 0x02u}, - {0x0Bu, 0x40u}, - {0x0Du, 0x08u}, + {0xE2u, 0x04u}, + {0xE8u, 0x08u}, + {0xEAu, 0x01u}, + {0x92u, 0x02u}, + {0x96u, 0x80u}, + {0x9Au, 0x80u}, + {0xA1u, 0x01u}, + {0xB0u, 0x80u}, + {0xB2u, 0x10u}, + {0xB5u, 0x20u}, + {0xEAu, 0x0Du}, + {0x0Au, 0x80u}, + {0x0Fu, 0x40u}, + {0x96u, 0x80u}, + {0xA9u, 0x01u}, + {0xAEu, 0x80u}, + {0xB2u, 0x01u}, {0xC2u, 0x0Cu}, - {0x23u, 0x10u}, - {0x26u, 0x10u}, - {0x89u, 0x08u}, - {0x94u, 0x01u}, - {0x97u, 0x10u}, - {0xA3u, 0x02u}, - {0xA5u, 0x08u}, - {0xA6u, 0x10u}, - {0xAEu, 0x50u}, - {0xAFu, 0x01u}, + {0xEAu, 0x04u}, + {0x22u, 0x08u}, + {0x24u, 0x02u}, + {0x94u, 0x02u}, + {0x9Eu, 0x20u}, + {0xA6u, 0x08u}, + {0xAEu, 0x60u}, + {0xB2u, 0x08u}, {0xC8u, 0x60u}, - {0xEAu, 0x40u}, - {0xECu, 0x10u}, + {0xE8u, 0x10u}, {0xEEu, 0x40u}, - {0x04u, 0x01u}, - {0x53u, 0x02u}, - {0x57u, 0x01u}, - {0x87u, 0x01u}, - {0x94u, 0x01u}, - {0xA3u, 0x02u}, + {0x06u, 0x20u}, + {0x53u, 0x01u}, + {0x5Du, 0x20u}, + {0x83u, 0x01u}, + {0x99u, 0x20u}, + {0x9Eu, 0x20u}, + {0xB1u, 0x20u}, {0xC0u, 0x20u}, {0xD4u, 0x80u}, {0xD6u, 0x20u}, - {0xE6u, 0x10u}, - {0xADu, 0x08u}, + {0xE6u, 0x20u}, {0xAFu, 0x40u}, {0x01u, 0x01u}, - {0x09u, 0x01u}, {0x0Bu, 0x01u}, + {0x0Du, 0x01u}, {0x0Fu, 0x01u}, {0x11u, 0x01u}, {0x1Bu, 0x01u}, - {0x00u, 0x2Bu}, + {0x00u, 0x0Au}, }; @@ -1357,7 +1279,6 @@ void cyfitter_cfg(void) static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ - {(void CYFAR *)(CYREG_TMR0_CFG0), 12u}, {(void CYFAR *)(CYREG_PRT1_DR), 16u}, {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1536u}, {(void CYFAR *)(CYDEV_UCFG_B0_P3_U1_BASE), 2432u}, @@ -1369,12 +1290,12 @@ void cyfitter_cfg(void) /* UDB_1_2_1_CONFIG Address: CYDEV_UCFG_B0_P3_U0_BASE Size (bytes): 128 */ static const uint8 CYCODE BS_UDB_1_2_1_CONFIG_VAL[] = { - 0x80u, 0x42u, 0x00u, 0x00u, 0x00u, 0x04u, 0xFFu, 0x20u, 0x7Fu, 0x39u, 0x80u, 0x06u, 0x00u, 0xC6u, 0x9Fu, 0x00u, - 0x90u, 0xC6u, 0x40u, 0x00u, 0x1Fu, 0x01u, 0x20u, 0x5Eu, 0x00u, 0x77u, 0x60u, 0x08u, 0xC0u, 0x46u, 0x02u, 0x80u, - 0xC0u, 0x00u, 0x01u, 0x00u, 0xC0u, 0xC2u, 0x08u, 0x04u, 0xC0u, 0x80u, 0x04u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x70u, 0x00u, 0x0Fu, 0xFFu, 0x80u, 0x00u, 0x20u, 0x00u, 0x0Cu, 0x00u, 0x00u, 0x40u, 0x40u, - 0x26u, 0x03u, 0x50u, 0x00u, 0x04u, 0xDCu, 0xF0u, 0xBEu, 0x3Bu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, - 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x24u, 0x04u, 0x0Bu, 0x0Bu, 0x0Bu, 0x90u, 0x99u, 0x00u, 0x01u, + 0x80u, 0x01u, 0x00u, 0x00u, 0x7Fu, 0x10u, 0x80u, 0x00u, 0xC0u, 0x08u, 0x04u, 0x21u, 0xC0u, 0x04u, 0x01u, 0x00u, + 0x00u, 0x01u, 0x60u, 0x00u, 0x00u, 0x07u, 0xFFu, 0x18u, 0x00u, 0x22u, 0x9Fu, 0x08u, 0xC0u, 0x40u, 0x02u, 0x00u, + 0x90u, 0x01u, 0x40u, 0x00u, 0x1Fu, 0x01u, 0x20u, 0x00u, 0xC0u, 0x40u, 0x08u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, + 0x00u, 0x3Fu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x40u, 0x00u, 0x82u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x01u, + 0x32u, 0x06u, 0x10u, 0x00u, 0x04u, 0xCBu, 0xFDu, 0x0Eu, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, + 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x20u, 0x04u, 0x0Bu, 0x0Bu, 0x0Bu, 0x90u, 0x99u, 0x00u, 0x01u, 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc index 07652353..25148f44 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -3,34 +3,6 @@ .include "cydevicegnu.inc" .include "cydevicegnu_trm.inc" -/* SCSI_CMD_TIMER_TimerHW */ -.set SCSI_CMD_TIMER_TimerHW__CAP0, CYREG_TMR0_CAP0 -.set SCSI_CMD_TIMER_TimerHW__CAP1, CYREG_TMR0_CAP1 -.set SCSI_CMD_TIMER_TimerHW__CFG0, CYREG_TMR0_CFG0 -.set SCSI_CMD_TIMER_TimerHW__CFG1, CYREG_TMR0_CFG1 -.set SCSI_CMD_TIMER_TimerHW__CFG2, CYREG_TMR0_CFG2 -.set SCSI_CMD_TIMER_TimerHW__CNT_CMP0, CYREG_TMR0_CNT_CMP0 -.set SCSI_CMD_TIMER_TimerHW__CNT_CMP1, CYREG_TMR0_CNT_CMP1 -.set SCSI_CMD_TIMER_TimerHW__PER0, CYREG_TMR0_PER0 -.set SCSI_CMD_TIMER_TimerHW__PER1, CYREG_TMR0_PER1 -.set SCSI_CMD_TIMER_TimerHW__PM_ACT_CFG, CYREG_PM_ACT_CFG3 -.set SCSI_CMD_TIMER_TimerHW__PM_ACT_MSK, 0x01 -.set SCSI_CMD_TIMER_TimerHW__PM_STBY_CFG, CYREG_PM_STBY_CFG3 -.set SCSI_CMD_TIMER_TimerHW__PM_STBY_MSK, 0x01 -.set SCSI_CMD_TIMER_TimerHW__RT0, CYREG_TMR0_RT0 -.set SCSI_CMD_TIMER_TimerHW__RT1, CYREG_TMR0_RT1 -.set SCSI_CMD_TIMER_TimerHW__SR0, CYREG_TMR0_SR0 - -/* SCSI_CMD_TIMER_ISR */ -.set SCSI_CMD_TIMER_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set SCSI_CMD_TIMER_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_CMD_TIMER_ISR__INTC_MASK, 0x01 -.set SCSI_CMD_TIMER_ISR__INTC_NUMBER, 0 -.set SCSI_CMD_TIMER_ISR__INTC_PRIOR_NUM, 7 -.set SCSI_CMD_TIMER_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_0 -.set SCSI_CMD_TIMER_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set SCSI_CMD_TIMER_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - /* USBFS_bus_reset */ .set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 @@ -532,8 +504,8 @@ .set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL .set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB06_MSK .set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_RxStsReg__4__POS, 4 .set SDCard_BSPIM_RxStsReg__5__MASK, 0x20 @@ -541,13 +513,13 @@ .set SDCard_BSPIM_RxStsReg__6__MASK, 0x40 .set SDCard_BSPIM_RxStsReg__6__POS, 6 .set SDCard_BSPIM_RxStsReg__MASK, 0x70 -.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB05_MSK -.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL -.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB05_ST +.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB07_MSK +.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL +.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB07_ST .set SDCard_BSPIM_TxStsReg__0__MASK, 0x01 .set SDCard_BSPIM_TxStsReg__0__POS, 0 -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 .set SDCard_BSPIM_TxStsReg__1__POS, 1 .set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 @@ -557,9 +529,9 @@ .set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_TxStsReg__4__POS, 4 .set SDCard_BSPIM_TxStsReg__MASK, 0x1F -.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB06_MSK -.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL -.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB06_ST +.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB05_MSK +.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL +.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB05_ST .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB06_07_A0 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB06_07_A1 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB06_07_D0 @@ -593,24 +565,24 @@ /* SCSI_CTL_IO */ .set SCSI_CTL_IO_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_CTL_IO_Sync_ctrl_reg__0__POS, 0 -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK -.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL -.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL -.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL -.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL -.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK +.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL +.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL .set SCSI_CTL_IO_Sync_ctrl_reg__MASK, 0x01 -.set SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL -.set SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK -.set SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL +.set SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL +.set SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK +.set SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL /* SCSI_In_DBx */ .set SCSI_In_DBx__0__AG, CYREG_PRT12_AG @@ -1069,8 +1041,8 @@ /* scsiTarget */ .set scsiTarget_StatusReg__0__MASK, 0x01 .set scsiTarget_StatusReg__0__POS, 0 -.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL -.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST +.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL +.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB14_15_ST .set scsiTarget_StatusReg__1__MASK, 0x02 .set scsiTarget_StatusReg__1__POS, 1 .set scsiTarget_StatusReg__2__MASK, 0x04 @@ -1078,80 +1050,76 @@ .set scsiTarget_StatusReg__3__MASK, 0x08 .set scsiTarget_StatusReg__3__POS, 3 .set scsiTarget_StatusReg__MASK, 0x0F -.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB12_MSK -.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL -.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL -.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL -.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB12_ST_CTL -.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB12_ST_CTL -.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB12_ST -.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL -.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST -.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB03_MSK -.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL -.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL -.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL -.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB03_ST_CTL -.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB03_ST_CTL -.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB03_ST -.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL -.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL -.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL -.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL -.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL -.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK -.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK -.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK -.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK -.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL -.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB03_CTL -.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL -.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB03_CTL -.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL -.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL -.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB03_MSK -.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL -.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB03_04_A0 -.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB03_04_A1 -.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB03_04_D0 -.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB03_04_D1 -.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL -.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB03_04_F0 -.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB03_04_F1 -.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB03_A0_A1 -.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB03_A0 -.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB03_A1 -.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB03_D0_D1 -.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB03_D0 -.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB03_D1 -.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB03_ACTL -.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB03_F0_F1 -.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB03_F0 -.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB03_F1 -.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL -.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL +.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB14_MSK +.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB14_ACTL +.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB14_ST +.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL +.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB13_14_ST +.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB13_MSK +.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL +.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL +.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB13_ACTL +.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB13_ST_CTL +.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB13_ST_CTL +.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB13_ST +.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL +.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB13_14_CTL +.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB13_14_CTL +.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB13_14_CTL +.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB13_14_CTL +.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB13_14_MSK +.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB13_14_MSK +.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB13_14_MSK +.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB13_14_MSK +.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_ACTL +.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB13_CTL +.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB13_ST_CTL +.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB13_CTL +.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB13_ST_CTL +.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL +.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB13_MSK +.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL +.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB13_14_A0 +.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB13_14_A1 +.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB13_14_D0 +.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB13_14_D1 +.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL +.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB13_14_F0 +.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB13_14_F1 +.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB13_A0_A1 +.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB13_A0 +.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB13_A1 +.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB13_D0_D1 +.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB13_D0 +.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB13_D1 +.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB13_ACTL +.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB13_F0_F1 +.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB13_F0 +.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB13_F1 +.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL +.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL /* SD_Clk_Ctl */ .set SD_Clk_Ctl_Sync_ctrl_reg__0__MASK, 0x01 .set SD_Clk_Ctl_Sync_ctrl_reg__0__POS, 0 -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK -.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL -.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK +.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL +.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL .set SD_Clk_Ctl_Sync_ctrl_reg__MASK, 0x01 -.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL -.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK -.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL +.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL +.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK +.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL /* USBFS_ep_0 */ .set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 @@ -1166,20 +1134,20 @@ /* USBFS_ep_1 */ .set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_1__INTC_MASK, 0x02 -.set USBFS_ep_1__INTC_NUMBER, 1 +.set USBFS_ep_1__INTC_MASK, 0x01 +.set USBFS_ep_1__INTC_NUMBER, 0 .set USBFS_ep_1__INTC_PRIOR_NUM, 7 -.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_1 +.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_0 .set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 /* USBFS_ep_2 */ .set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_2__INTC_MASK, 0x04 -.set USBFS_ep_2__INTC_NUMBER, 2 +.set USBFS_ep_2__INTC_MASK, 0x02 +.set USBFS_ep_2__INTC_NUMBER, 1 .set USBFS_ep_2__INTC_PRIOR_NUM, 7 -.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_2 +.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_1 .set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 @@ -2754,7 +2722,7 @@ .set CYDEV_ECC_ENABLE, 0 .set CYDEV_HEAP_SIZE, 0x1000 .set CYDEV_INSTRUCT_CACHE_ENABLED, 1 -.set CYDEV_INTR_RISING, 0x00000001 +.set CYDEV_INTR_RISING, 0x00000000 .set CYDEV_PROJ_TYPE, 2 .set CYDEV_PROJ_TYPE_BOOTLOADER, 1 .set CYDEV_PROJ_TYPE_LOADABLE, 2 diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc index 7e0fb107..94834410 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc @@ -3,34 +3,6 @@ INCLUDE cydeviceiar.inc INCLUDE cydeviceiar_trm.inc -/* SCSI_CMD_TIMER_TimerHW */ -SCSI_CMD_TIMER_TimerHW__CAP0 EQU CYREG_TMR0_CAP0 -SCSI_CMD_TIMER_TimerHW__CAP1 EQU CYREG_TMR0_CAP1 -SCSI_CMD_TIMER_TimerHW__CFG0 EQU CYREG_TMR0_CFG0 -SCSI_CMD_TIMER_TimerHW__CFG1 EQU CYREG_TMR0_CFG1 -SCSI_CMD_TIMER_TimerHW__CFG2 EQU CYREG_TMR0_CFG2 -SCSI_CMD_TIMER_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0 -SCSI_CMD_TIMER_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1 -SCSI_CMD_TIMER_TimerHW__PER0 EQU CYREG_TMR0_PER0 -SCSI_CMD_TIMER_TimerHW__PER1 EQU CYREG_TMR0_PER1 -SCSI_CMD_TIMER_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3 -SCSI_CMD_TIMER_TimerHW__PM_ACT_MSK EQU 0x01 -SCSI_CMD_TIMER_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3 -SCSI_CMD_TIMER_TimerHW__PM_STBY_MSK EQU 0x01 -SCSI_CMD_TIMER_TimerHW__RT0 EQU CYREG_TMR0_RT0 -SCSI_CMD_TIMER_TimerHW__RT1 EQU CYREG_TMR0_RT1 -SCSI_CMD_TIMER_TimerHW__SR0 EQU CYREG_TMR0_SR0 - -/* SCSI_CMD_TIMER_ISR */ -SCSI_CMD_TIMER_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_CMD_TIMER_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_CMD_TIMER_ISR__INTC_MASK EQU 0x01 -SCSI_CMD_TIMER_ISR__INTC_NUMBER EQU 0 -SCSI_CMD_TIMER_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_CMD_TIMER_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 -SCSI_CMD_TIMER_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_CMD_TIMER_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - /* USBFS_bus_reset */ USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 @@ -532,8 +504,8 @@ SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -541,13 +513,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 @@ -557,9 +529,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0 @@ -593,24 +565,24 @@ USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* SCSI_CTL_IO */ SCSI_CTL_IO_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_IO_Sync_ctrl_reg__0__POS EQU 0 -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK -SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL -SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL -SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL -SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL -SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL +SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL +SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL +SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL SCSI_CTL_IO_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL -SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK -SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK +SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL /* SCSI_In_DBx */ SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG @@ -1069,8 +1041,8 @@ SD_Init_Clk__PM_STBY_MSK EQU 0x02 /* scsiTarget */ scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 -scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL -scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 scsiTarget_StatusReg__2__MASK EQU 0x04 @@ -1078,80 +1050,76 @@ scsiTarget_StatusReg__2__POS EQU 2 scsiTarget_StatusReg__3__MASK EQU 0x08 scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__MASK EQU 0x0F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK -scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL -scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL -scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST -scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST -scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK -scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL -scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL -scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB03_ST -scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK -scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK -scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB03_CTL -scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL -scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB03_CTL -scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL -scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB03_MSK -scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB03_04_A0 -scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB03_04_A1 -scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB03_04_D0 -scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB03_04_D1 -scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB03_04_F0 -scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB03_04_F1 -scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB03_A0_A1 -scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB03_A0 -scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB03_A1 -scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB03_D0_D1 -scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB03_D0 -scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB03_D1 -scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB03_F0_F1 -scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB03_F0 -scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB03_F1 -scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB14_MSK +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB14_ST +scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL +scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST +scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB13_MSK +scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL +scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB13_ST_CTL +scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB13_ST_CTL +scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB13_ST +scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL +scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL +scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL +scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL +scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL +scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK +scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK +scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL +scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB13_CTL +scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL +scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB13_CTL +scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL +scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB13_MSK +scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB13_14_A0 +scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB13_14_A1 +scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB13_14_D0 +scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB13_14_D1 +scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL +scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB13_14_F0 +scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB13_14_F1 +scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB13_A0_A1 +scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB13_A0 +scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB13_A1 +scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB13_D0_D1 +scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB13_D0 +scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB13_D1 +scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL +scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB13_F0_F1 +scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB13_F0 +scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB13_F1 +scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL /* SD_Clk_Ctl */ SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK -SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL -SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL -SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL -SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL -SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK +SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL +SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL +SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL +SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK -SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK +SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL /* USBFS_ep_0 */ USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -1166,20 +1134,20 @@ USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* USBFS_ep_1 */ USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_1__INTC_MASK EQU 0x02 -USBFS_ep_1__INTC_NUMBER EQU 1 +USBFS_ep_1__INTC_MASK EQU 0x01 +USBFS_ep_1__INTC_NUMBER EQU 0 USBFS_ep_1__INTC_PRIOR_NUM EQU 7 -USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* USBFS_ep_2 */ USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_2__INTC_MASK EQU 0x04 -USBFS_ep_2__INTC_NUMBER EQU 2 +USBFS_ep_2__INTC_MASK EQU 0x02 +USBFS_ep_2__INTC_NUMBER EQU 1 USBFS_ep_2__INTC_PRIOR_NUM EQU 7 -USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 @@ -2754,7 +2722,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24 CYDEV_ECC_ENABLE EQU 0 CYDEV_HEAP_SIZE EQU 0x1000 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1 -CYDEV_INTR_RISING EQU 0x00000001 +CYDEV_INTR_RISING EQU 0x00000000 CYDEV_PROJ_TYPE EQU 2 CYDEV_PROJ_TYPE_BOOTLOADER EQU 1 CYDEV_PROJ_TYPE_LOADABLE EQU 2 diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc index 257ff861..d2068011 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -3,34 +3,6 @@ INCLUDED_CYFITTERRV_INC EQU 1 GET cydevicerv.inc GET cydevicerv_trm.inc -; SCSI_CMD_TIMER_TimerHW -SCSI_CMD_TIMER_TimerHW__CAP0 EQU CYREG_TMR0_CAP0 -SCSI_CMD_TIMER_TimerHW__CAP1 EQU CYREG_TMR0_CAP1 -SCSI_CMD_TIMER_TimerHW__CFG0 EQU CYREG_TMR0_CFG0 -SCSI_CMD_TIMER_TimerHW__CFG1 EQU CYREG_TMR0_CFG1 -SCSI_CMD_TIMER_TimerHW__CFG2 EQU CYREG_TMR0_CFG2 -SCSI_CMD_TIMER_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0 -SCSI_CMD_TIMER_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1 -SCSI_CMD_TIMER_TimerHW__PER0 EQU CYREG_TMR0_PER0 -SCSI_CMD_TIMER_TimerHW__PER1 EQU CYREG_TMR0_PER1 -SCSI_CMD_TIMER_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3 -SCSI_CMD_TIMER_TimerHW__PM_ACT_MSK EQU 0x01 -SCSI_CMD_TIMER_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3 -SCSI_CMD_TIMER_TimerHW__PM_STBY_MSK EQU 0x01 -SCSI_CMD_TIMER_TimerHW__RT0 EQU CYREG_TMR0_RT0 -SCSI_CMD_TIMER_TimerHW__RT1 EQU CYREG_TMR0_RT1 -SCSI_CMD_TIMER_TimerHW__SR0 EQU CYREG_TMR0_SR0 - -; SCSI_CMD_TIMER_ISR -SCSI_CMD_TIMER_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_CMD_TIMER_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_CMD_TIMER_ISR__INTC_MASK EQU 0x01 -SCSI_CMD_TIMER_ISR__INTC_NUMBER EQU 0 -SCSI_CMD_TIMER_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_CMD_TIMER_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 -SCSI_CMD_TIMER_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_CMD_TIMER_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - ; USBFS_bus_reset USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 @@ -532,8 +504,8 @@ SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -541,13 +513,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 @@ -557,9 +529,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0 @@ -593,24 +565,24 @@ USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; SCSI_CTL_IO SCSI_CTL_IO_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_IO_Sync_ctrl_reg__0__POS EQU 0 -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK -SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL -SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL -SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL -SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL -SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL +SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL +SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL +SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL SCSI_CTL_IO_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL -SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK -SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK +SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL ; SCSI_In_DBx SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG @@ -1069,8 +1041,8 @@ SD_Init_Clk__PM_STBY_MSK EQU 0x02 ; scsiTarget scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 -scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL -scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 scsiTarget_StatusReg__2__MASK EQU 0x04 @@ -1078,80 +1050,76 @@ scsiTarget_StatusReg__2__POS EQU 2 scsiTarget_StatusReg__3__MASK EQU 0x08 scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__MASK EQU 0x0F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK -scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL -scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL -scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST -scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST -scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK -scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL -scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL -scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB03_ST -scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK -scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK -scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB03_CTL -scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL -scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB03_CTL -scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL -scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB03_MSK -scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB03_04_A0 -scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB03_04_A1 -scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB03_04_D0 -scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB03_04_D1 -scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB03_04_F0 -scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB03_04_F1 -scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB03_A0_A1 -scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB03_A0 -scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB03_A1 -scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB03_D0_D1 -scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB03_D0 -scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB03_D1 -scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB03_F0_F1 -scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB03_F0 -scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB03_F1 -scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB14_MSK +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB14_ST +scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL +scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST +scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB13_MSK +scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL +scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB13_ST_CTL +scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB13_ST_CTL +scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB13_ST +scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL +scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL +scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL +scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL +scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL +scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK +scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK +scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL +scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB13_CTL +scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL +scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB13_CTL +scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL +scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB13_MSK +scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB13_14_A0 +scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB13_14_A1 +scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB13_14_D0 +scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB13_14_D1 +scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL +scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB13_14_F0 +scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB13_14_F1 +scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB13_A0_A1 +scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB13_A0 +scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB13_A1 +scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB13_D0_D1 +scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB13_D0 +scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB13_D1 +scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL +scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB13_F0_F1 +scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB13_F0 +scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB13_F1 +scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL ; SD_Clk_Ctl SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK -SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL -SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL -SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL -SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL -SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK +SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL +SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL +SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL +SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK -SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK +SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL ; USBFS_ep_0 USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -1166,20 +1134,20 @@ USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; USBFS_ep_1 USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_1__INTC_MASK EQU 0x02 -USBFS_ep_1__INTC_NUMBER EQU 1 +USBFS_ep_1__INTC_MASK EQU 0x01 +USBFS_ep_1__INTC_NUMBER EQU 0 USBFS_ep_1__INTC_PRIOR_NUM EQU 7 -USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; USBFS_ep_2 USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_2__INTC_MASK EQU 0x04 -USBFS_ep_2__INTC_NUMBER EQU 2 +USBFS_ep_2__INTC_MASK EQU 0x02 +USBFS_ep_2__INTC_NUMBER EQU 1 USBFS_ep_2__INTC_PRIOR_NUM EQU 7 -USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 @@ -2754,7 +2722,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24 CYDEV_ECC_ENABLE EQU 0 CYDEV_HEAP_SIZE EQU 0x1000 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1 -CYDEV_INTR_RISING EQU 0x00000001 +CYDEV_INTR_RISING EQU 0x00000000 CYDEV_PROJ_TYPE EQU 2 CYDEV_PROJ_TYPE_BOOTLOADER EQU 1 CYDEV_PROJ_TYPE_LOADABLE EQU 2 diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h index 1252396c..92a14ac9 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h @@ -58,8 +58,6 @@ #include #include #include -#include -#include #include #include #include diff --git a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx index 4575072c..ad440cf0 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx +++ b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx @@ -1,79 +1,12 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + @@ -154,24 +87,31 @@ - + + + + + + + + + + + - - - + - - - - + + + + - + - \ No newline at end of file diff --git a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit index f94969fef12b8511b2314ceab1cb59c9992fadba..e8e530bdb2728d8c3b3ff0a8dfe636a741ec39f2 100755 GIT binary patch literal 226302 zcmbTebyOeA(k>hzL4pN$cXtS`KioaIySr;}cXxMp5AN<3Ah^53g=C+5&wju2p1s!h z2disls;jG>s(!j)%^)oX@)7aFhY#Q%^poucG*&VPv}`_nc(Moi0P=QMKuPwv4Kh)E zUSZc+EXc=K7aT8*2RAF4tvhkD|&9Ao!XuT0#KVX=-D# zQxE*3FbhapewH_5nk8_W@xwW^gw!4on;n?{$X8YX6hk-E2#YvNdL%ZK)6VPi;YrOc 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b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.svd index ac6018c9..6c18cab7 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.svd +++ b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.svd @@ -6,298 +6,6 @@ 8 32 - - SCSI_CMD_TIMER - No description available - 0x400043A3 - - 0 - 0xB64 - registers - - - - SCSI_CMD_TIMER_GLOBAL_ENABLE - PM.ACT.CFG - 0x0 - 8 - read-write - 0 - 0 - - - en_timer - Enable timer/counters. - 0 - 3 - read-write - - - - - SCSI_CMD_TIMER_CONTROL - TMRx.CFG0 - 0xB5D - 8 - read-write - 0 - 0 - - - EN - Enables timer/comparator. - 0 - 0 - read-write - - - MODE - Mode. (0 = Timer; 1 = Comparator) - 1 - 1 - read-write - - - Timer - Timer mode. CNT/CMP register holds timer count value. - 0 - - - Comparator - Comparator mode. CNT/CMP register holds comparator threshold value. - 1 - - - - - ONESHOT - Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block. - 2 - 2 - read-write - - - CMP_BUFF - Buffer compare register. Compare register updates only on timer terminal count. - 3 - 3 - read-write - - - INV - Invert sense of TIMEREN signal - 4 - 4 - read-write - - - DB - Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively. - 5 - 5 - read-write - - - Timer - CMP and TC are output. - 0 - - - Deadband - PHI1 (instead of CMP) and PHI2 (instead of TC) are output. - 1 - - - - - DEADBAND_PERIOD - Deadband Period - 6 - 7 - read-write - - - - - SCSI_CMD_TIMER_CONTROL2 - TMRx.CFG1 - 0xB5E - 8 - read-write - 0 - 0 - - - IRQ_SEL - Irq selection. (0 = raw interrupts; 1 = status register interrupts) - 0 - 0 - read-write - - - FTC - First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled. - 1 - 1 - read-write - - - Disable_FTC - Disable the single cycle pulse, which signifies the timer is starting. - 0 - - - Enable_FTC - Enable the single cycle pulse, which signifies the timer is starting. - 1 - - - - - DCOR - Disable Clear on Read (DCOR) of Status Register SR0. - 2 - 2 - read-write - - - DBMODE - Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND). - 3 - 3 - read-write - - - CLK_BUS_EN_SEL - Digital Global Clock selection. - 4 - 6 - read-write - - - BUS_CLK_SEL - Bus Clock selection. - 7 - 7 - read-write - - - - - SCSI_CMD_TIMER_CONTROL3_ - TMRx.CFG2 - 0xB5F - 8 - read-write - 0 - 0 - - - TMR_CFG - Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ - 0 - 1 - read-write - - - Continuous - Timer runs while EN bit of CFG0 register is set to '1'. - 0 - - - Pulsewidth - Timer runs from positive to negative edge of TIMEREN. - 1 - - - Period - Timer runs from positive to positive edge of TIMEREN. - 2 - - - Irq - Timer runs until IRQ. - 3 - - - - - COD - Clear On Disable (COD). Clears or gates outputs to zero. - 2 - 2 - read-write - - - ROD - Reset On Disable (ROD). Resets internal state of output logic - 3 - 3 - read-write - - - CMP_CFG - Comparator configurations - 4 - 6 - read-write - - - Equal - Compare Equal - 0 - - - Less_than - Compare Less Than - 1 - - - Less_than_or_equal - Compare Less Than or Equal . - 2 - - - Greater - Compare Greater Than . - 3 - - - Greater_than_or_equal - Compare Greater Than or Equal - 4 - - - - - HW_EN - When set Timer Enable controls counting. - 7 - 7 - read-write - - - - - SCSI_CMD_TIMER_PERIOD - TMRx.PER0 - Assigned Period - 0xB61 - 16 - read-write - 0 - 0 - - - SCSI_CMD_TIMER_COUNTER - TMRx.CNT_CMP0 - Current Down Counter Value - 0xB63 - 16 - read-write - 0 - 0 - - - USBFS USBFS @@ -785,7 +493,7 @@ SD_Clk_Ctl No description available - 0x4000647C + 0x4000647A 0 0x1 @@ -806,7 +514,7 @@ SCSI_CTL_IO No description available - 0x40006471 + 0x4000647B 0 0x1 diff --git a/software/SCSI2SD/SCSI2SD.cydsn/TopDesign/TopDesign.cysch b/software/SCSI2SD/SCSI2SD.cydsn/TopDesign/TopDesign.cysch index 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zmBakr1Pn(6;%N(b&AJo_;Od%gcLFZ*h%9X}EMQrI;+)QRz_C3PRRx^a*IC`Htu zN^9XA!IC+EN`!(GJ$WFzapE2CPoeuTZjWfrl(JUfjFNM@8jyI^l_X0w}KY zbymdeZK;Fy);Pq%-<;5<6g(TX*JTeU4^13)qRfwZ5p>G;Nik0*0IwA}Jy(Owg-MIm z=Arl+0nOzU(J!E&cg{;7U@6s@=LaOb^tOe(eY&lJ*KvH9zq?|x@^H)cWw(Q-K`URPk&{~!$O(Rl z`U6e9nU-2m{7mW~7Sv>Jza9mRMw6DB49;3z+DRP^zK_eQdt(CEOL778ku)BRg`sHh zl9k_u0}6eu`JkO(`9BJt2fJH+M1L@2Hmx}K>_h`= PM_ALT_ACT_TIME_FTW(1u)) && (wakeupTime <= PM_ALT_ACT_TIME_FTW(256u))) 602:.\Generated_Source\PSoC5/cyPm.c **** { - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 12 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 12 603:.\Generated_Source\PSoC5/cyPm.c **** CyPmFtwSetInterval(PM_ALT_ACT_FTW_INTERVAL(wakeupTime)); @@ -718,7 +718,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 657:.\Generated_Source\PSoC5/cyPm.c **** /* Execute WFI instruction (for ARM-based devices only) */ 658:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WFI; 659:.\Generated_Source\PSoC5/cyPm.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 13 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 13 660:.\Generated_Source\PSoC5/cyPm.c **** /* Point of return from Alternate Active Mode */ @@ -778,7 +778,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 714:.\Generated_Source\PSoC5/cyPm.c **** * 715:.\Generated_Source\PSoC5/cyPm.c **** * Define Time 716:.\Generated_Source\PSoC5/cyPm.c **** * PM_SLEEP_TIME_NONE None - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 14 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 14 717:.\Generated_Source\PSoC5/cyPm.c **** * PM_SLEEP_TIME_ONE_PPS One PPS: 1 second @@ -838,7 +838,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 771:.\Generated_Source\PSoC5/cyPm.c **** * used as wake up time) will be left started. 772:.\Generated_Source\PSoC5/cyPm.c **** * 773:.\Generated_Source\PSoC5/cyPm.c **** * The 1 kHz ILO clock is expected to be enabled for PSoC 3 and PSoC 5LP to - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 15 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 15 774:.\Generated_Source\PSoC5/cyPm.c **** * measure Hibernate/Sleep regulator settling time after a reset. The holdoff @@ -898,7 +898,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 828:.\Generated_Source\PSoC5/cyPm.c **** 829:.\Generated_Source\PSoC5/cyPm.c **** /* Silicon Revision ID is below TO6 */ 830:.\Generated_Source\PSoC5/cyPm.c **** if(CYDEV_CHIP_REV_ACTUAL < 5u) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 16 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 16 831:.\Generated_Source\PSoC5/cyPm.c **** { @@ -958,7 +958,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 885:.\Generated_Source\PSoC5/cyPm.c **** #if(CY_PSOC3) 886:.\Generated_Source\PSoC5/cyPm.c **** 887:.\Generated_Source\PSoC5/cyPm.c **** /* CTW - save current and set new configuration */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 17 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 17 888:.\Generated_Source\PSoC5/cyPm.c **** if((wakeupTime >= PM_SLEEP_TIME_CTW_2MS) && (wakeupTime <= PM_SLEEP_TIME_CTW_4096MS)) @@ -1018,7 +1018,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 942:.\Generated_Source\PSoC5/cyPm.c **** /* IMO frequency is not 12 MHz */ 943:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.imoActFreq12Mhz = CY_PM_DISABLED; 944:.\Generated_Source\PSoC5/cyPm.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 18 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 18 945:.\Generated_Source\PSoC5/cyPm.c **** /* Save IMO frequency */ @@ -1078,7 +1078,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 999:.\Generated_Source\PSoC5/cyPm.c **** } 1000:.\Generated_Source\PSoC5/cyPm.c **** } 1001:.\Generated_Source\PSoC5/cyPm.c **** } - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 19 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 19 1002:.\Generated_Source\PSoC5/cyPm.c **** @@ -1138,7 +1138,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1056:.\Generated_Source\PSoC5/cyPm.c **** * delay is measured using rising edges of the 1 kHz ILO. 1057:.\Generated_Source\PSoC5/cyPm.c **** * 1058:.\Generated_Source\PSoC5/cyPm.c **** *******************************************************************************/ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 20 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 20 1059:.\Generated_Source\PSoC5/cyPm.c **** void CyPmHibernate(void) @@ -1198,7 +1198,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1113:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.imoActFreq = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK; 1114:.\Generated_Source\PSoC5/cyPm.c **** 1115:.\Generated_Source\PSoC5/cyPm.c **** /* Set IMO frequency to 12 MHz */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 21 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 21 1116:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_FASTCLK_IMO_CR_REG &= ((uint8) (~CY_PM_FASTCLK_IMO_CR_FREQ_MASK)); @@ -1258,7 +1258,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1170:.\Generated_Source\PSoC5/cyPm.c **** * from this value and written back to the shadow register. 1171:.\Generated_Source\PSoC5/cyPm.c **** * 1172:.\Generated_Source\PSoC5/cyPm.c **** * Note You must call this function within 1 ms (1 clock cycle of the ILO) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 22 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 22 1173:.\Generated_Source\PSoC5/cyPm.c **** * after a CTW event has occurred. @@ -1318,7 +1318,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1227:.\Generated_Source\PSoC5/cyPm.c **** * Reentrant: 1228:.\Generated_Source\PSoC5/cyPm.c **** * No 1229:.\Generated_Source\PSoC5/cyPm.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 23 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 23 1230:.\Generated_Source\PSoC5/cyPm.c **** *******************************************************************************/ @@ -1378,7 +1378,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1284:.\Generated_Source\PSoC5/cyPm.c **** CyPmHviLviSaveDisable(); 1285:.\Generated_Source\PSoC5/cyPm.c **** 1286:.\Generated_Source\PSoC5/cyPm.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 24 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 24 1287:.\Generated_Source\PSoC5/cyPm.c **** /* Make the same preparations for Hibernate and Sleep modes */ @@ -1438,7 +1438,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1341:.\Generated_Source\PSoC5/cyPm.c **** } 1342:.\Generated_Source\PSoC5/cyPm.c **** 1343:.\Generated_Source\PSoC5/cyPm.c **** /* Restore ILO power mode */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 25 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 25 1344:.\Generated_Source\PSoC5/cyPm.c **** (void) CyILO_SetPowerMode(cyPmBackup.iloPowerMode); @@ -1498,7 +1498,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1398:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_TW_CFG1_REG = ctwInterval; 1399:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_TW_CFG2_REG |= CY_PM_CTW_EN; 1400:.\Generated_Source\PSoC5/cyPm.c **** } /* Required interval is already set */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 26 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 26 1401:.\Generated_Source\PSoC5/cyPm.c **** } @@ -1558,7 +1558,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1455:.\Generated_Source\PSoC5/cyPm.c **** * Summary: 1456:.\Generated_Source\PSoC5/cyPm.c **** * Performs FTW configuration: 1457:.\Generated_Source\PSoC5/cyPm.c **** * - Disables FTW interrupt - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 27 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 27 1458:.\Generated_Source\PSoC5/cyPm.c **** * - Enables 100 kHz ILO @@ -1618,7 +1618,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1512:.\Generated_Source\PSoC5/cyPm.c **** * modes entry: 1513:.\Generated_Source\PSoC5/cyPm.c **** * - Saves COMP, VIDAC, DSM and SAR routing connections (PSoC 5) 1514:.\Generated_Source\PSoC5/cyPm.c **** * - Saves SC/CT routing connections (PSoC 3/5/5LP) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 28 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 28 1515:.\Generated_Source\PSoC5/cyPm.c **** * - Disables Serial Wire Viewer (SWV) (PSoC 3) @@ -1678,7 +1678,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1535:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[4u] = CY_GET_REG8(CYREG_SC0_SW6 ); 1536:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[5u] = CY_GET_REG8(CYREG_SC0_SW8 ); 1537:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[6u] = CY_GET_REG8(CYREG_SC0_SW10); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 29 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 29 1538:.\Generated_Source\PSoC5/cyPm.c **** @@ -1738,7 +1738,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 85 003e 1C74 strb r4, [r3, #16] 1540:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[8u] = CY_GET_REG8(CYREG_SC1_SW2 ); 86 .loc 1 1540 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 30 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 30 87 0040 FD7B ldrb r5, [r7, #15] @ zero_extendqisi2 @@ -1798,7 +1798,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 126 .loc 1 1553 0 127 0080 5A77 strb r2, [r3, #29] 1555:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[21u] = CY_GET_REG8(CYREG_SC3_SW0 ); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 31 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 31 128 .loc 1 1555 0 @@ -1858,7 +1858,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1567:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC0_SW6 , 0u); 168 .loc 1 1567 0 169 00ca BA70 strb r2, [r7, #2] - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 32 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 32 1568:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC0_SW8 , 0u); @@ -1918,7 +1918,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1588:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC3_SW2 , 0u); 204 .loc 1 1588 0 205 00f8 87F82E20 strb r2, [r7, #46] - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 33 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 33 1589:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC3_SW3 , 0u); @@ -1978,7 +1978,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 218 .loc 1 1629 0 219 010a 0178 ldrb r1, [r0, #0] @ zero_extendqisi2 1588:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC3_SW2 , 0u); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 34 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 34 220 .loc 1 1588 0 @@ -2038,7 +2038,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1641:.\Generated_Source\PSoC5/cyPm.c **** /******************************************************************************* 1642:.\Generated_Source\PSoC5/cyPm.c **** * Function Name: CyPmHibSlpRestore 1643:.\Generated_Source\PSoC5/cyPm.c **** ******************************************************************************** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 35 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 35 1644:.\Generated_Source\PSoC5/cyPm.c **** * @@ -2098,7 +2098,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1670:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC1_SW0 , cyPmBackup.scctData[7u] ); 291 .loc 1 1670 0 292 0020 187C ldrb r0, [r3, #16] @ zero_extendqisi2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 36 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 36 293 0022 1074 strb r0, [r2, #16] @@ -2158,7 +2158,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 333 0058 9174 strb r1, [r2, #18] 1685:.\Generated_Source\PSoC5/cyPm.c **** 1686:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC3_SW0 , cyPmBackup.scctData[21u]); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 37 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 37 334 .loc 1 1686 0 @@ -2218,7 +2218,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 360 008c 0449 ldr r1, .L9+8 361 008e 0A78 ldrb r2, [r1, #0] @ zero_extendqisi2 362 0090 42F00800 orr r0, r2, #8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 38 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 38 363 0094 0870 strb r0, [r1, #0] @@ -2278,7 +2278,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 410 0022 0022 movs r2, #0 411 0024 1A70 strb r2, [r3, #0] 89:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.flashWaitCycles = CY_PM_CACHE_CR_CYCLES_MASK & CY_PM_CACHE_CR_REG; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 39 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 39 412 .loc 1 89 0 @@ -2338,7 +2338,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 455 .L14: 120:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.imoEnable = CY_PM_DISABLED; 456 .loc 1 120 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 40 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 40 457 0078 81F83630 strb r3, [r1, #54] @@ -2398,7 +2398,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 500 00c4 0178 ldrb r1, [r0, #0] @ zero_extendqisi2 501 00c6 01F0CF02 and r2, r1, #207 502 00ca 0270 strb r2, [r0, #0] - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 41 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 41 503 .L19: @@ -2458,7 +2458,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 546 010c 0302 lsls r3, r0, #8 547 010e 9387 strh r3, [r2, #60] @ movhi 177:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.clkBusDiv |= CY_PM_CLK_BUS_LSB_DIV_REG; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 42 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 42 548 .loc 1 177 0 @@ -2518,7 +2518,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 204:.\Generated_Source\PSoC5/cyPm.c **** CyXTAL_Stop(); 593 .loc 1 204 0 594 015c FFF7FEFF bl CyXTAL_Stop - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 43 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 43 595 .LVL10: @@ -2578,7 +2578,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 644 .LVL11: 264:.\Generated_Source\PSoC5/cyPm.c **** const uint8 CYCODE cyPmImoFreqMhz2Reg[7u] = { 645 .loc 1 264 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 44 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 44 646 0000 774A ldr r2, .L76 @@ -2638,7 +2638,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 686 .loc 1 275 0 687 0034 6D48 ldr r0, .L76+12 688 0036 0178 ldrb r1, [r0, #0] @ zero_extendqisi2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 45 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 45 689 0038 41F00404 orr r4, r1, #4 @@ -2698,7 +2698,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 735 0082 E1D5 bpl .L53 736 0084 013C subs r4, r4, #1 737 0086 A4B2 uxth r4, r4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 46 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 46 295:.\Generated_Source\PSoC5/cyPm.c **** for(i = CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US; i > 0u; i--) @@ -2758,7 +2758,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 783 00d6 11F8080C ldrb r0, [r1, #-8] @ zero_extendqisi2 784 00da FFF7FEFF bl CyIMO_SetFreq 785 .LVL20: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 47 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 47 351:.\Generated_Source\PSoC5/cyPm.c **** if(0u != (cyPmClockBackup.imoUsbClk & CY_PM_FASTCLK_IMO_CR_USB)) @@ -2818,7 +2818,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 373:.\Generated_Source\PSoC5/cyPm.c **** CyIMO_Stop(); 830 .loc 1 373 0 831 012a FFF7FEFF bl CyIMO_Stop - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 48 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 48 832 .LVL22: @@ -2878,7 +2878,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 878 .LVL26: 879 .L63: 411:.\Generated_Source\PSoC5/cyPm.c **** if((CY_PM_MASTER_CLK_SRC_IMO == cyPmClockBackup.masterClkSrc) || - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 49 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 49 880 .loc 1 411 0 @@ -2938,7 +2938,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 924 01c4 0178 ldrb r1, [r0, #0] @ zero_extendqisi2 925 01c6 01F03F03 and r3, r1, #63 926 01ca 1343 orrs r3, r3, r2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 50 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 50 927 01cc 0370 strb r3, [r0, #0] @@ -2998,7 +2998,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 636:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG0_REG = (uint8) (wakeupSource >> 4u); 976 .loc 1 636 0 977 0008 0809 lsrs r0, r1, #4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 51 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 51 978 .LVL34: @@ -3058,7 +3058,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1018 1019 @ 0 "" 2 658:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WFI; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 52 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 52 1020 .loc 1 658 0 @@ -3118,7 +3118,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 792:.\Generated_Source\PSoC5/cyPm.c **** interruptState = CyEnterCriticalSection(); 1069 .loc 1 792 0 1070 0004 FFF7FEFF bl CyEnterCriticalSection - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 53 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 53 1071 .LVL37: @@ -3178,7 +3178,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1110 .loc 1 922 0 1111 003a C4F30034 ubfx r4, r4, #12, #1 921:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 54 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 54 1112 .loc 1 921 0 @@ -3238,7 +3238,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1155 007e 00BF NOP 1156 1157 @ 0 "" 2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 55 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 55 963:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WFI; @@ -3298,7 +3298,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1201 .LVL43: 1202 .L94: 1203 00be 00BF .align 2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 56 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 56 1204 .L93: @@ -3358,7 +3358,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1234:.\Generated_Source\PSoC5/cyPm.c **** if(0u != (CY_PM_PWRSYS_CR1_REG & CY_PM_PWRSYS_CR1_I2CREG_BACKUP)) 1252 .loc 1 1234 0 1253 001a 7C4B ldr r3, .L125+8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 57 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 57 1254 .LBE11: @@ -3418,7 +3418,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1296 005a 05D1 bne .L98 1268:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.slpTrBypass = CY_PM_DISABLED; 1297 .loc 1 1268 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 58 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 58 1298 005c DA70 strb r2, [r3, #3] @@ -3478,7 +3478,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1322 007c 83F82510 strb r1, [r3, #37] 1323 .loc 1 1741 0 1324 0080 2278 ldrb r2, [r4, #0] @ zero_extendqisi2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 59 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 59 1742:.\Generated_Source\PSoC5/cyPm.c **** @@ -3538,7 +3538,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1760:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.lviaRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESA_EN)) ? \ 1358 .loc 1 1760 0 1359 00b6 5A4A ldr r2, .L125+28 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 60 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 60 1757:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.lviaTrip = CY_VD_LVI_TRIP_REG >> 4u; @@ -3598,7 +3598,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1395 .LBE12: 1294:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupTrim0 = CY_PM_PWRSYS_WAKE_TR0_REG; 1396 .loc 1 1294 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 61 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 61 1397 00ec 4D4C ldr r4, .L125+32 @@ -3658,7 +3658,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1435 0114 5C71 strb r4, [r3, #5] 1095:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG1_REG = 0x00u; 1436 .loc 1 1095 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 62 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 62 1437 0116 5170 strb r1, [r2, #1] @@ -3718,7 +3718,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1128:.\Generated_Source\PSoC5/cyPm.c **** CY_NOP; 1480 .loc 1 1128 0 1481 @ 1128 ".\Generated_Source\PSoC5\cyPm.c" 1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 63 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 63 1482 015a 00BF NOP @@ -3778,7 +3778,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1508 .loc 1 1802 0 1509 0178 94F82540 ldrb r4, [r4, #37] @ zero_extendqisi2 1510 017c 244B ldr r3, .L125+12 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 64 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 64 1511 017e 012C cmp r4, #1 @@ -3838,7 +3838,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1549 .loc 1 1333 0 1550 01bc FFF7FEFF bl CyILO_Start1K 1551 .LVL56: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 65 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 65 1552 .L113: @@ -3898,7 +3898,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1594 .loc 1 1151 0 1595 01f6 8079 ldrb r0, [r0, #6] @ zero_extendqisi2 1596 01f8 0870 strb r0, [r1, #0] - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 66 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 66 1154:.\Generated_Source\PSoC5/cyPm.c **** CyExitCriticalSection(interruptState); @@ -3958,7 +3958,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1646 0002 0546 mov r5, r0 1194:.\Generated_Source\PSoC5/cyPm.c **** interruptState = CyEnterCriticalSection(); 1647 .loc 1 1194 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 67 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 67 1648 0004 FFF7FEFF bl CyEnterCriticalSection @@ -4018,7 +4018,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1383:.\Generated_Source\PSoC5/cyPm.c **** { 1696 .loc 1 1383 0 1697 0004 0546 mov r5, r0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 68 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 68 1385:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_CTW_IE)); @@ -4078,7 +4078,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1742 .L134: 1743 004c 82430040 .word 1073759106 1744 0050 81430040 .word 1073759105 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 69 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 69 1745 .cfi_endproc @@ -4138,7 +4138,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1794 .global CyPmFtwSetInterval 1795 .thumb 1796 .thumb_func - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 70 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 70 1797 .type CyPmFtwSetInterval, %function @@ -4198,7 +4198,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1841 002e 43F00102 orr r2, r3, #1 1842 0032 2270 strb r2, [r4, #0] 1843 0034 38BD pop {r3, r4, r5, pc} - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 71 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 71 1844 .L141: @@ -4258,7 +4258,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1891 00000000 1892 002f 00 .space 1 1893 .type cyPmClockBackup, %object - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 72 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 72 1894 .size cyPmClockBackup, 18 @@ -4285,10 +4285,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1911 0006 00000000 .4byte .Ldebug_abbrev0 1912 000a 04 .byte 0x4 1913 000b 01 .uleb128 0x1 - 1914 000c 4A040000 .4byte .LASF111 + 1914 000c 5B040000 .4byte .LASF111 1915 0010 01 .byte 0x1 1916 0011 A4010000 .4byte .LASF112 - 1917 0015 EA010000 .4byte .LASF113 + 1917 0015 53030000 .4byte .LASF113 1918 0019 18000000 .4byte .Ldebug_ranges0+0x18 1919 001d 00000000 .4byte 0 1920 0021 00000000 .4byte 0 @@ -4300,15 +4300,15 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1926 0030 02 .uleb128 0x2 1927 0031 01 .byte 0x1 1928 0032 08 .byte 0x8 - 1929 0033 A4040000 .4byte .LASF1 + 1929 0033 B5040000 .4byte .LASF1 1930 0037 02 .uleb128 0x2 1931 0038 02 .byte 0x2 1932 0039 05 .byte 0x5 - 1933 003a DD040000 .4byte .LASF2 + 1933 003a EE040000 .4byte .LASF2 1934 003e 02 .uleb128 0x2 1935 003f 02 .byte 0x2 1936 0040 07 .byte 0x7 - 1937 0041 D7020000 .4byte .LASF3 + 1937 0041 B7020000 .4byte .LASF3 1938 0045 02 .uleb128 0x2 1939 0046 04 .byte 0x4 1940 0047 05 .byte 0x5 @@ -4316,9 +4316,9 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1942 004c 02 .uleb128 0x2 1943 004d 04 .byte 0x4 1944 004e 07 .byte 0x7 - 1945 004f 48020000 .4byte .LASF5 + 1945 004f 28020000 .4byte .LASF5 1946 0053 02 .uleb128 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 73 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 73 1947 0054 08 .byte 0x8 @@ -4335,7 +4335,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1958 0068 02 .uleb128 0x2 1959 0069 04 .byte 0x4 1960 006a 07 .byte 0x7 - 1961 006b 1A020000 .4byte .LASF8 + 1961 006b FA010000 .4byte .LASF8 1962 006f 04 .uleb128 0x4 1963 0070 87010000 .4byte .LASF9 1964 0074 02 .byte 0x2 @@ -4354,7 +4354,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1977 0090 02 .uleb128 0x2 1978 0091 04 .byte 0x4 1979 0092 04 .byte 0x4 - 1980 0093 03040000 .4byte .LASF12 + 1980 0093 14040000 .4byte .LASF12 1981 0097 02 .uleb128 0x2 1982 0098 08 .byte 0x8 1983 0099 04 .byte 0x4 @@ -4362,14 +4362,14 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 1985 009e 02 .uleb128 0x2 1986 009f 01 .byte 0x1 1987 00a0 08 .byte 0x8 - 1988 00a1 07050000 .4byte .LASF14 + 1988 00a1 18050000 .4byte .LASF14 1989 00a5 04 .uleb128 0x4 - 1990 00a6 27060000 .4byte .LASF15 + 1990 00a6 38060000 .4byte .LASF15 1991 00aa 02 .byte 0x2 1992 00ab E8 .byte 0xe8 1993 00ac 4C000000 .4byte 0x4c 1994 00b0 04 .uleb128 0x4 - 1995 00b1 93040000 .4byte .LASF16 + 1995 00b1 A4040000 .4byte .LASF16 1996 00b5 02 .byte 0x2 1997 00b6 F0 .byte 0xf0 1998 00b7 BB000000 .4byte 0xbb @@ -4378,18 +4378,18 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2001 00c0 02 .uleb128 0x2 2002 00c1 04 .byte 0x4 2003 00c2 07 .byte 0x7 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 74 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 74 - 2004 00c3 8C030000 .4byte .LASF17 + 2004 00c3 9D030000 .4byte .LASF17 2005 00c7 06 .uleb128 0x6 - 2006 00c8 61020000 .4byte .LASF34 + 2006 00c8 41020000 .4byte .LASF34 2007 00cc 12 .byte 0x12 2008 00cd 03 .byte 0x3 2009 00ce F1 .byte 0xf1 2010 00cf A9010000 .4byte 0x1a9 2011 00d3 07 .uleb128 0x7 - 2012 00d4 A8030000 .4byte .LASF18 + 2012 00d4 B9030000 .4byte .LASF18 2013 00d8 03 .byte 0x3 2014 00d9 F4 .byte 0xf4 2015 00da 6F000000 .4byte 0x6f @@ -4397,7 +4397,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2017 00df 23 .byte 0x23 2018 00e0 00 .uleb128 0 2019 00e1 07 .uleb128 0x7 - 2020 00e2 AF030000 .4byte .LASF19 + 2020 00e2 C0030000 .4byte .LASF19 2021 00e6 03 .byte 0x3 2022 00e7 F5 .byte 0xf5 2023 00e8 6F000000 .4byte 0x6f @@ -4413,7 +4413,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2033 00fb 23 .byte 0x23 2034 00fc 02 .uleb128 0x2 2035 00fd 07 .uleb128 0x7 - 2036 00fe 40020000 .4byte .LASF21 + 2036 00fe 20020000 .4byte .LASF21 2037 0102 03 .byte 0x3 2038 0103 F7 .byte 0xf7 2039 0104 6F000000 .4byte 0x6f @@ -4429,7 +4429,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2049 0117 23 .byte 0x23 2050 0118 04 .uleb128 0x4 2051 0119 07 .uleb128 0x7 - 2052 011a 30060000 .4byte .LASF23 + 2052 011a 41060000 .4byte .LASF23 2053 011e 03 .byte 0x3 2054 011f F9 .byte 0xf9 2055 0120 6F000000 .4byte 0x6f @@ -4437,8 +4437,8 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2057 0125 23 .byte 0x23 2058 0126 05 .uleb128 0x5 2059 0127 07 .uleb128 0x7 - 2060 0128 7B060000 .4byte .LASF24 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 75 + 2060 0128 8C060000 .4byte .LASF24 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 75 2061 012c 03 .byte 0x3 @@ -4448,7 +4448,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2065 0133 23 .byte 0x23 2066 0134 06 .uleb128 0x6 2067 0135 07 .uleb128 0x7 - 2068 0136 F9030000 .4byte .LASF25 + 2068 0136 0A040000 .4byte .LASF25 2069 013a 03 .byte 0x3 2070 013b FB .byte 0xfb 2071 013c 6F000000 .4byte 0x6f @@ -4456,7 +4456,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2073 0141 23 .byte 0x23 2074 0142 07 .uleb128 0x7 2075 0143 07 .uleb128 0x7 - 2076 0144 5A030000 .4byte .LASF26 + 2076 0144 3A030000 .4byte .LASF26 2077 0148 03 .byte 0x3 2078 0149 FC .byte 0xfc 2079 014a 6F000000 .4byte 0x6f @@ -4488,7 +4488,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2105 0179 23 .byte 0x23 2106 017a 0C .uleb128 0xc 2107 017b 08 .uleb128 0x8 - 2108 017c C2040000 .4byte .LASF30 + 2108 017c D3040000 .4byte .LASF30 2109 0180 03 .byte 0x3 2110 0181 0001 .2byte 0x100 2111 0183 6F000000 .4byte 0x6f @@ -4498,7 +4498,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2115 018a 08 .uleb128 0x8 2116 018b CB010000 .4byte .LASF31 2117 018f 03 .byte 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 76 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 76 2118 0190 0101 .2byte 0x101 @@ -4507,7 +4507,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2121 0197 23 .byte 0x23 2122 0198 0F .uleb128 0xf 2123 0199 08 .uleb128 0x8 - 2124 019a AA050000 .4byte .LASF32 + 2124 019a BB050000 .4byte .LASF32 2125 019e 03 .byte 0x3 2126 019f 0201 .2byte 0x102 2127 01a1 6F000000 .4byte 0x6f @@ -4516,12 +4516,12 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2130 01a7 10 .uleb128 0x10 2131 01a8 00 .byte 0 2132 01a9 09 .uleb128 0x9 - 2133 01aa BD020000 .4byte .LASF33 + 2133 01aa 9D020000 .4byte .LASF33 2134 01ae 03 .byte 0x3 2135 01af 0401 .2byte 0x104 2136 01b1 C7000000 .4byte 0xc7 2137 01b5 0A .uleb128 0xa - 2138 01b6 8E020000 .4byte .LASF35 + 2138 01b6 6E020000 .4byte .LASF35 2139 01ba 2F .byte 0x2f 2140 01bb 03 .byte 0x3 2141 01bc 0701 .2byte 0x107 @@ -4535,7 +4535,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2149 01cf 23 .byte 0x23 2150 01d0 00 .uleb128 0 2151 01d1 08 .uleb128 0x8 - 2152 01d2 D1040000 .4byte .LASF37 + 2152 01d2 E2040000 .4byte .LASF37 2153 01d6 03 .byte 0x3 2154 01d7 0A01 .2byte 0x10a 2155 01d9 6F000000 .4byte 0x6f @@ -4543,7 +4543,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2157 01de 23 .byte 0x23 2158 01df 01 .uleb128 0x1 2159 01e0 08 .uleb128 0x8 - 2160 01e1 F9040000 .4byte .LASF38 + 2160 01e1 0A050000 .4byte .LASF38 2161 01e5 03 .byte 0x3 2162 01e6 0B01 .2byte 0x10b 2163 01e8 6F000000 .4byte 0x6f @@ -4551,18 +4551,18 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2165 01ed 23 .byte 0x23 2166 01ee 02 .uleb128 0x2 2167 01ef 08 .uleb128 0x8 - 2168 01f0 80030000 .4byte .LASF39 + 2168 01f0 91030000 .4byte .LASF39 2169 01f4 03 .byte 0x3 2170 01f5 0D01 .2byte 0x10d 2171 01f7 6F000000 .4byte 0x6f 2172 01fb 02 .byte 0x2 2173 01fc 23 .byte 0x23 2174 01fd 03 .uleb128 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 77 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 77 2175 01fe 08 .uleb128 0x8 - 2176 01ff 20030000 .4byte .LASF40 + 2176 01ff 00030000 .4byte .LASF40 2177 0203 03 .byte 0x3 2178 0204 1701 .2byte 0x117 2179 0206 6F000000 .4byte 0x6f @@ -4570,7 +4570,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2181 020b 23 .byte 0x23 2182 020c 04 .uleb128 0x4 2183 020d 08 .uleb128 0x8 - 2184 020e 2B030000 .4byte .LASF41 + 2184 020e 0B030000 .4byte .LASF41 2185 0212 03 .byte 0x3 2186 0213 1801 .2byte 0x118 2187 0215 6F000000 .4byte 0x6f @@ -4578,7 +4578,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2189 021a 23 .byte 0x23 2190 021b 05 .uleb128 0x5 2191 021c 08 .uleb128 0x8 - 2192 021d 36030000 .4byte .LASF42 + 2192 021d 16030000 .4byte .LASF42 2193 0221 03 .byte 0x3 2194 0222 1901 .2byte 0x119 2195 0224 6F000000 .4byte 0x6f @@ -4602,7 +4602,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2213 0247 23 .byte 0x23 2214 0248 08 .uleb128 0x8 2215 0249 08 .uleb128 0x8 - 2216 024a 27020000 .4byte .LASF45 + 2216 024a 07020000 .4byte .LASF45 2217 024e 03 .byte 0x3 2218 024f 1E01 .2byte 0x11e 2219 0251 EF020000 .4byte 0x2ef @@ -4610,7 +4610,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2221 0256 23 .byte 0x23 2222 0257 09 .uleb128 0x9 2223 0258 08 .uleb128 0x8 - 2224 0259 5A020000 .4byte .LASF46 + 2224 0259 3A020000 .4byte .LASF46 2225 025d 03 .byte 0x3 2226 025e 2101 .2byte 0x121 2227 0260 6F000000 .4byte 0x6f @@ -4618,10 +4618,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2229 0265 23 .byte 0x23 2230 0266 25 .uleb128 0x25 2231 0267 08 .uleb128 0x8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 78 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 78 - 2232 0268 72060000 .4byte .LASF47 + 2232 0268 83060000 .4byte .LASF47 2233 026c 03 .byte 0x3 2234 026d 2201 .2byte 0x122 2235 026f 6F000000 .4byte 0x6f @@ -4629,7 +4629,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2237 0274 23 .byte 0x23 2238 0275 26 .uleb128 0x26 2239 0276 08 .uleb128 0x8 - 2240 0277 D1050000 .4byte .LASF48 + 2240 0277 E2050000 .4byte .LASF48 2241 027b 03 .byte 0x3 2242 027c 2301 .2byte 0x123 2243 027e 6F000000 .4byte 0x6f @@ -4653,7 +4653,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2261 02a1 23 .byte 0x23 2262 02a2 29 .uleb128 0x29 2263 02a3 08 .uleb128 0x8 - 2264 02a4 29040000 .4byte .LASF51 + 2264 02a4 3A040000 .4byte .LASF51 2265 02a8 03 .byte 0x3 2266 02a9 2601 .2byte 0x126 2267 02ab 6F000000 .4byte 0x6f @@ -4661,7 +4661,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2269 02b0 23 .byte 0x23 2270 02b1 2A .uleb128 0x2a 2271 02b2 08 .uleb128 0x8 - 2272 02b3 40060000 .4byte .LASF52 + 2272 02b3 51060000 .4byte .LASF52 2273 02b7 03 .byte 0x3 2274 02b8 2701 .2byte 0x127 2275 02ba 6F000000 .4byte 0x6f @@ -4669,7 +4669,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2277 02bf 23 .byte 0x23 2278 02c0 2B .uleb128 0x2b 2279 02c1 08 .uleb128 0x8 - 2280 02c2 0F020000 .4byte .LASF53 + 2280 02c2 EF010000 .4byte .LASF53 2281 02c6 03 .byte 0x3 2282 02c7 2901 .2byte 0x129 2283 02c9 6F000000 .4byte 0x6f @@ -4677,8 +4677,8 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2285 02ce 23 .byte 0x23 2286 02cf 2C .uleb128 0x2c 2287 02d0 08 .uleb128 0x8 - 2288 02d1 34050000 .4byte .LASF54 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 79 + 2288 02d1 45050000 .4byte .LASF54 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 79 2289 02d5 03 .byte 0x3 @@ -4688,7 +4688,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2293 02dd 23 .byte 0x23 2294 02de 2D .uleb128 0x2d 2295 02df 08 .uleb128 0x8 - 2296 02e0 4E030000 .4byte .LASF55 + 2296 02e0 2E030000 .4byte .LASF55 2297 02e4 03 .byte 0x3 2298 02e5 2C01 .2byte 0x12c 2299 02e7 6F000000 .4byte 0x6f @@ -4709,7 +4709,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2314 0305 2E01 .2byte 0x12e 2315 0307 B5010000 .4byte 0x1b5 2316 030b 0D .uleb128 0xd - 2317 030c E7040000 .4byte .LASF57 + 2317 030c F8040000 .4byte .LASF57 2318 0310 01 .byte 0x1 2319 0311 F805 .2byte 0x5f8 2320 0313 01 .byte 0x1 @@ -4730,7 +4730,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2335 0335 01 .byte 0x1 2336 0336 0F .uleb128 0xf 2337 0337 01 .byte 0x1 - 2338 0338 64030000 .4byte .LASF59 + 2338 0338 44030000 .4byte .LASF59 2339 033c 01 .byte 0x1 2340 033d 50 .byte 0x50 2341 033e 01 .byte 0x1 @@ -4738,7 +4738,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2343 0343 B4010000 .4byte .LFE0 2344 0347 20000000 .4byte .LLST1 2345 034b 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 80 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 80 2346 034c F1030000 .4byte 0x3f1 @@ -4798,7 +4798,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2400 03be 50 .byte 0x50 2401 03bf 01 .byte 0x1 2402 03c0 30 .byte 0x30 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 81 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 81 2403 03c1 00 .byte 0 @@ -4834,7 +4834,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2433 0407 01 .byte 0x1 2434 0408 3B050000 .4byte 0x53b 2435 040c 14 .uleb128 0x14 - 2436 040d CA050000 .4byte .LASF61 + 2436 040d DB050000 .4byte .LASF61 2437 0411 01 .byte 0x1 2438 0412 0201 .2byte 0x102 2439 0414 A5000000 .4byte 0xa5 @@ -4845,20 +4845,20 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2444 041d 0301 .2byte 0x103 2445 041f 7A000000 .4byte 0x7a 2446 0423 16 .uleb128 0x16 - 2447 0424 41030000 .4byte .LASF62 + 2447 0424 21030000 .4byte .LASF62 2448 0428 01 .byte 0x1 2449 0429 0401 .2byte 0x104 2450 042b 7A000000 .4byte 0x7a 2451 042f 60000000 .4byte .LLST3 2452 0433 17 .uleb128 0x17 - 2453 0434 95030000 .4byte .LASF63 + 2453 0434 A6030000 .4byte .LASF63 2454 0438 01 .byte 0x1 2455 0439 0801 .2byte 0x108 2456 043b 4B050000 .4byte 0x54b 2457 043f 02 .byte 0x2 2458 0440 91 .byte 0x91 2459 0441 70 .sleb128 -16 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 82 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 82 2460 0442 10 .uleb128 0x10 @@ -4918,7 +4918,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2514 04a8 10 .uleb128 0x10 2515 04a9 CC000000 .4byte .LVL19 2516 04ad 7B080000 .4byte 0x87b - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 83 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 83 2517 04b1 BB040000 .4byte 0x4bb @@ -4978,7 +4978,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2571 051d 1E .byte 0x1e 2572 051e 00 .byte 0 2573 051f 12 .uleb128 0x12 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 84 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 84 2574 0520 9E010000 .4byte .LVL27 @@ -5001,7 +5001,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2591 054c 3B050000 .4byte 0x53b 2592 0550 13 .uleb128 0x13 2593 0551 01 .byte 0x1 - 2594 0552 31040000 .4byte .LASF64 + 2594 0552 42040000 .4byte .LASF64 2595 0556 01 .byte 0x1 2596 0557 4702 .2byte 0x247 2597 0559 01 .byte 0x1 @@ -5011,13 +5011,13 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2601 0566 01 .byte 0x1 2602 0567 8C050000 .4byte 0x58c 2603 056b 19 .uleb128 0x19 - 2604 056c 09060000 .4byte .LASF65 + 2604 056c 1A060000 .4byte .LASF65 2605 0570 01 .byte 0x1 2606 0571 4702 .2byte 0x247 2607 0573 7A000000 .4byte 0x7a 2608 0577 AC000000 .4byte .LLST5 2609 057b 19 .uleb128 0x19 - 2610 057c C6030000 .4byte .LASF66 + 2610 057c D7030000 .4byte .LASF66 2611 0580 01 .byte 0x1 2612 0581 4702 .2byte 0x247 2613 0583 7A000000 .4byte 0x7a @@ -5025,7 +5025,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2615 058b 00 .byte 0 2616 058c 13 .uleb128 0x13 2617 058d 01 .byte 0x1 - 2618 058e 1F040000 .4byte .LASF67 + 2618 058e 30040000 .4byte .LASF67 2619 0592 01 .byte 0x1 2620 0593 1303 .2byte 0x313 2621 0595 01 .byte 0x1 @@ -5035,16 +5035,16 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2625 05a2 01 .byte 0x1 2626 05a3 FD050000 .4byte 0x5fd 2627 05a7 19 .uleb128 0x19 - 2628 05a8 09060000 .4byte .LASF65 + 2628 05a8 1A060000 .4byte .LASF65 2629 05ac 01 .byte 0x1 2630 05ad 1303 .2byte 0x313 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 85 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 85 2631 05af 6F000000 .4byte 0x6f 2632 05b3 0E010000 .4byte .LLST8 2633 05b7 19 .uleb128 0x19 - 2634 05b8 C6030000 .4byte .LASF66 + 2634 05b8 D7030000 .4byte .LASF66 2635 05bc 01 .byte 0x1 2636 05bd 1303 .2byte 0x313 2637 05bf 7A000000 .4byte 0x7a @@ -5070,7 +5070,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2657 05f8 77090000 .4byte 0x977 2658 05fc 00 .byte 0 2659 05fd 1B .uleb128 0x1b - 2660 05fe FA050000 .4byte .LASF69 + 2660 05fe 0B060000 .4byte .LASF69 2661 0602 01 .byte 0x1 2662 0603 CF04 .2byte 0x4cf 2663 0605 01 .byte 0x1 @@ -5095,10 +5095,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2682 0624 01 .byte 0x1 2683 0625 13 .uleb128 0x13 2684 0626 01 .byte 0x1 - 2685 0627 44050000 .4byte .LASF73 + 2685 0627 55050000 .4byte .LASF73 2686 062b 01 .byte 0x1 2687 062c 2304 .2byte 0x423 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 86 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 86 2688 062e 01 .byte 0x1 @@ -5158,7 +5158,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2742 06be 01 .byte 0x1 2743 06bf 7A04 .2byte 0x47a 2744 06c1 1A070000 .4byte 0x71a - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 87 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 87 2745 06c5 1D .uleb128 0x1d @@ -5201,7 +5201,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2782 072d 00 .byte 0 2783 072e 1E .uleb128 0x1e 2784 072f 01 .byte 0x1 - 2785 0730 87050000 .4byte .LASF114 + 2785 0730 98050000 .4byte .LASF114 2786 0734 01 .byte 0x1 2787 0735 A304 .2byte 0x4a3 2788 0737 01 .byte 0x1 @@ -5212,16 +5212,16 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2793 0748 01 .byte 0x1 2794 0749 A0070000 .4byte 0x7a0 2795 074d 19 .uleb128 0x19 - 2796 074e 0A020000 .4byte .LASF74 + 2796 074e EA010000 .4byte .LASF74 2797 0752 01 .byte 0x1 2798 0753 A304 .2byte 0x4a3 2799 0755 6F000000 .4byte 0x6f 2800 0759 F8010000 .4byte .LLST14 2801 075d 17 .uleb128 0x17 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 88 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 88 - 2802 075e 85060000 .4byte .LASF75 + 2802 075e 96060000 .4byte .LASF75 2803 0762 01 .byte 0x1 2804 0763 A504 .2byte 0x4a5 2805 0765 6F000000 .4byte 0x6f @@ -5250,7 +5250,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2828 079f 00 .byte 0 2829 07a0 13 .uleb128 0x13 2830 07a1 01 .byte 0x1 - 2831 07a2 B7050000 .4byte .LASF77 + 2831 07a2 C8050000 .4byte .LASF77 2832 07a6 01 .byte 0x1 2833 07a7 6605 .2byte 0x566 2834 07a9 01 .byte 0x1 @@ -5260,7 +5260,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2838 07b6 01 .byte 0x1 2839 07b7 D5070000 .4byte 0x7d5 2840 07bb 19 .uleb128 0x19 - 2841 07bc EA020000 .4byte .LASF78 + 2841 07bc CA020000 .4byte .LASF78 2842 07c0 01 .byte 0x1 2843 07c1 6605 .2byte 0x566 2844 07c3 6F000000 .4byte 0x6f @@ -5271,14 +5271,14 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2849 07d4 00 .byte 0 2850 07d5 13 .uleb128 0x13 2851 07d6 01 .byte 0x1 - 2852 07d7 98040000 .4byte .LASF79 + 2852 07d7 A9040000 .4byte .LASF79 2853 07db 01 .byte 0x1 2854 07dc 9A05 .2byte 0x59a 2855 07de 01 .byte 0x1 2856 07df 00000000 .4byte .LFB9 2857 07e3 2C000000 .4byte .LFE9 2858 07e7 6D020000 .4byte .LLST18 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 89 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 89 2859 07eb 01 .byte 0x1 @@ -5299,7 +5299,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2874 0810 01 .byte 0x1 2875 0811 2F080000 .4byte 0x82f 2876 0815 19 .uleb128 0x19 - 2877 0816 68050000 .4byte .LASF81 + 2877 0816 79050000 .4byte .LASF81 2878 081a 01 .byte 0x1 2879 081b BF05 .2byte 0x5bf 2880 081d 6F000000 .4byte 0x6f @@ -5309,7 +5309,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2884 082a 070A0000 .4byte 0xa07 2885 082e 00 .byte 0 2886 082f 1F .uleb128 0x1f - 2887 0830 67060000 .4byte .LASF82 + 2887 0830 78060000 .4byte .LASF82 2888 0834 01 .byte 0x1 2889 0835 1F .byte 0x1f 2890 0836 FF020000 .4byte 0x2ff @@ -5317,7 +5317,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2892 083b 03 .byte 0x3 2893 083c 00000000 .4byte cyPmBackup 2894 0840 1F .uleb128 0x1f - 2895 0841 B2040000 .4byte .LASF83 + 2895 0841 C3040000 .4byte .LASF83 2896 0845 01 .byte 0x1 2897 0846 20 .byte 0x20 2898 0847 A9010000 .4byte 0x1a9 @@ -5325,7 +5325,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2900 084c 03 .byte 0x3 2901 084d 30000000 .4byte cyPmClockBackup 2902 0851 1F .uleb128 0x1f - 2903 0852 74050000 .4byte .LASF84 + 2903 0852 85050000 .4byte .LASF84 2904 0856 01 .byte 0x1 2905 0857 23 .byte 0x23 2906 0858 62080000 .4byte 0x862 @@ -5336,9 +5336,9 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2911 0863 3B050000 .4byte 0x53b 2912 0867 20 .uleb128 0x20 2913 0868 01 .byte 0x1 - 2914 0869 52050000 .4byte .LASF85 + 2914 0869 63050000 .4byte .LASF85 2915 086d 04 .byte 0x4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 90 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 90 2916 086e 4B .byte 0x4b @@ -5350,7 +5350,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2922 087a 00 .byte 0 2923 087b 20 .uleb128 0x20 2924 087c 01 .byte 0x1 - 2925 087d D8050000 .4byte .LASF86 + 2925 087d E9050000 .4byte .LASF86 2926 0881 05 .byte 0x5 2927 0882 49 .byte 0x49 2928 0883 01 .byte 0x1 @@ -5372,7 +5372,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2944 08a2 00 .byte 0 2945 08a3 20 .uleb128 0x20 2946 08a4 01 .byte 0x1 - 2947 08a5 30020000 .4byte .LASF88 + 2947 08a5 10020000 .4byte .LASF88 2948 08a9 05 .byte 0x5 2949 08aa 4A .byte 0x4a 2950 08ab 01 .byte 0x1 @@ -5383,14 +5383,14 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2955 08b6 00 .byte 0 2956 08b7 22 .uleb128 0x22 2957 08b8 01 .byte 0x1 - 2958 08b9 0C050000 .4byte .LASF92 + 2958 08b9 1D050000 .4byte .LASF92 2959 08bd 05 .byte 0x5 2960 08be 4C .byte 0x4c 2961 08bf 01 .byte 0x1 2962 08c0 01 .byte 0x1 2963 08c1 20 .uleb128 0x20 2964 08c2 01 .byte 0x1 - 2965 08c3 E2030000 .4byte .LASF89 + 2965 08c3 F3030000 .4byte .LASF89 2966 08c7 05 .byte 0x5 2967 08c8 4F .byte 0x4f 2968 08c9 01 .byte 0x1 @@ -5398,13 +5398,13 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2970 08cb D5080000 .4byte 0x8d5 2971 08cf 21 .uleb128 0x21 2972 08d0 6F000000 .4byte 0x6f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 91 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 91 2973 08d4 00 .byte 0 2974 08d5 20 .uleb128 0x20 2975 08d6 01 .byte 0x1 - 2976 08d7 0A030000 .4byte .LASF90 + 2976 08d7 EA020000 .4byte .LASF90 2977 08db 05 .byte 0x5 2978 08dc 4E .byte 0x4e 2979 08dd 01 .byte 0x1 @@ -5415,7 +5415,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2984 08e8 00 .byte 0 2985 08e9 20 .uleb128 0x20 2986 08ea 01 .byte 0x1 - 2987 08eb 96050000 .4byte .LASF91 + 2987 08eb A7050000 .4byte .LASF91 2988 08ef 05 .byte 0x5 2989 08f0 50 .byte 0x50 2990 08f1 01 .byte 0x1 @@ -5426,21 +5426,21 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 2995 08fc 00 .byte 0 2996 08fd 22 .uleb128 0x22 2997 08fe 01 .byte 0x1 - 2998 08ff D3030000 .4byte .LASF93 + 2998 08ff E4030000 .4byte .LASF93 2999 0903 05 .byte 0x5 3000 0904 43 .byte 0x43 3001 0905 01 .byte 0x1 3002 0906 01 .byte 0x1 3003 0907 22 .uleb128 0x22 3004 0908 01 .byte 0x1 - 3005 0909 5B060000 .4byte .LASF94 + 3005 0909 6C060000 .4byte .LASF94 3006 090d 05 .byte 0x5 3007 090e 67 .byte 0x67 3008 090f 01 .byte 0x1 3009 0910 01 .byte 0x1 3010 0911 20 .uleb128 0x20 3011 0912 01 .byte 0x1 - 3012 0913 3C040000 .4byte .LASF95 + 3012 0913 4D040000 .4byte .LASF95 3013 0917 05 .byte 0x5 3014 0918 7A .byte 0x7a 3015 0919 01 .byte 0x1 @@ -5451,14 +5451,14 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 3020 0924 00 .byte 0 3021 0925 23 .uleb128 0x23 3022 0926 01 .byte 0x1 - 3023 0927 73030000 .4byte .LASF98 + 3023 0927 84030000 .4byte .LASF98 3024 092b 05 .byte 0x5 3025 092c 66 .byte 0x66 3026 092d 01 .byte 0x1 3027 092e A5000000 .4byte 0xa5 3028 0932 01 .byte 0x1 3029 0933 3D090000 .4byte 0x93d - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 92 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 92 3030 0937 21 .uleb128 0x21 @@ -5466,14 +5466,14 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 3032 093c 00 .byte 0 3033 093d 22 .uleb128 0x22 3034 093e 01 .byte 0x1 - 3035 093f B2020000 .4byte .LASF96 + 3035 093f 92020000 .4byte .LASF96 3036 0943 05 .byte 0x5 3037 0944 48 .byte 0x48 3038 0945 01 .byte 0x1 3039 0946 01 .byte 0x1 3040 0947 22 .uleb128 0x22 3041 0948 01 .byte 0x1 - 3042 0949 E6050000 .4byte .LASF97 + 3042 0949 F7050000 .4byte .LASF97 3043 094d 05 .byte 0x5 3044 094e 4B .byte 0x4b 3045 094f 01 .byte 0x1 @@ -5492,7 +5492,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 3058 0968 00 .byte 0 3059 0969 24 .uleb128 0x24 3060 096a 01 .byte 0x1 - 3061 096b 77020000 .4byte .LASF115 + 3061 096b 57020000 .4byte .LASF115 3062 096f 05 .byte 0x5 3063 0970 7E .byte 0x7e 3064 0971 01 .byte 0x1 @@ -5500,7 +5500,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 3066 0976 01 .byte 0x1 3067 0977 20 .uleb128 0x20 3068 0978 01 .byte 0x1 - 3069 0979 09040000 .4byte .LASF100 + 3069 0979 1A040000 .4byte .LASF100 3070 097d 05 .byte 0x5 3071 097e 7F .byte 0x7f 3072 097f 01 .byte 0x1 @@ -5511,14 +5511,14 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 3077 098a 00 .byte 0 3078 098b 22 .uleb128 0x22 3079 098c 01 .byte 0x1 - 3080 098d 21050000 .4byte .LASF101 + 3080 098d 32050000 .4byte .LASF101 3081 0991 05 .byte 0x5 3082 0992 9D .byte 0x9d 3083 0993 01 .byte 0x1 3084 0994 01 .byte 0x1 3085 0995 22 .uleb128 0x22 3086 0996 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 93 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 93 3087 0997 00000000 .4byte .LASF102 @@ -5528,14 +5528,14 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 3091 099e 01 .byte 0x1 3092 099f 22 .uleb128 0x22 3093 09a0 01 .byte 0x1 - 3094 09a1 F6020000 .4byte .LASF103 + 3094 09a1 D6020000 .4byte .LASF103 3095 09a5 05 .byte 0x5 3096 09a6 A0 .byte 0xa0 3097 09a7 01 .byte 0x1 3098 09a8 01 .byte 0x1 3099 09a9 23 .uleb128 0x23 3100 09aa 01 .byte 0x1 - 3101 09ab 9F020000 .4byte .LASF104 + 3101 09ab 7F020000 .4byte .LASF104 3102 09af 05 .byte 0x5 3103 09b0 5F .byte 0x5f 3104 09b1 01 .byte 0x1 @@ -5560,7 +5560,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 3123 09d9 00 .byte 0 3124 09da 20 .uleb128 0x20 3125 09db 01 .byte 0x1 - 3126 09dc 14060000 .4byte .LASF106 + 3126 09dc 25060000 .4byte .LASF106 3127 09e0 05 .byte 0x5 3128 09e1 9C .byte 0x9c 3129 09e2 01 .byte 0x1 @@ -5573,12 +5573,12 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 3136 09f2 00 .byte 0 3137 09f3 22 .uleb128 0x22 3138 09f4 01 .byte 0x1 - 3139 09f5 48060000 .4byte .LASF107 + 3139 09f5 59060000 .4byte .LASF107 3140 09f9 05 .byte 0x5 3141 09fa 9F .byte 0x9f 3142 09fb 01 .byte 0x1 3143 09fc 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 94 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 94 3144 09fd 22 .uleb128 0x22 @@ -5590,7 +5590,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 3150 0a06 01 .byte 0x1 3151 0a07 22 .uleb128 0x22 3152 0a08 01 .byte 0x1 - 3153 0a09 B6030000 .4byte .LASF109 + 3153 0a09 C7030000 .4byte .LASF109 3154 0a0d 05 .byte 0x5 3155 0a0e 5A .byte 0x5a 3156 0a0f 01 .byte 0x1 @@ -5638,7 +5638,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 3198 001e 00 .byte 0 3199 001f 00 .byte 0 3200 0020 03 .uleb128 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 95 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 95 3201 0021 24 .uleb128 0x24 @@ -5698,7 +5698,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 3255 0057 49 .uleb128 0x49 3256 0058 13 .uleb128 0x13 3257 0059 38 .uleb128 0x38 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 96 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 96 3258 005a 0A .uleb128 0xa @@ -5758,7 +5758,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 3312 0090 00 .byte 0 3313 0091 0C .uleb128 0xc 3314 0092 21 .uleb128 0x21 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 97 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 97 3315 0093 00 .byte 0 @@ -5818,7 +5818,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 3369 00cb 03 .uleb128 0x3 3370 00cc 0E .uleb128 0xe 3371 00cd 3A .uleb128 0x3a - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 98 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 98 3372 00ce 0B .uleb128 0xb @@ -5878,7 +5878,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 3426 010c 0B .uleb128 0xb 3427 010d 3B .uleb128 0x3b 3428 010e 05 .uleb128 0x5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 99 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 99 3429 010f 27 .uleb128 0x27 @@ -5938,7 +5938,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 3483 0146 06 .uleb128 0x6 3484 0147 00 .byte 0 3485 0148 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 100 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 100 3486 0149 17 .uleb128 0x17 @@ -5998,7 +5998,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 3540 0182 0B .uleb128 0xb 3541 0183 3B .uleb128 0x3b 3542 0184 05 .uleb128 0x5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 101 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 101 3543 0185 27 .uleb128 0x27 @@ -6058,7 +6058,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 3597 01bb 13 .uleb128 0x13 3598 01bc 11 .uleb128 0x11 3599 01bd 01 .uleb128 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 102 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 102 3600 01be 12 .uleb128 0x12 @@ -6118,7 +6118,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 3654 01f5 3F .uleb128 0x3f 3655 01f6 0C .uleb128 0xc 3656 01f7 03 .uleb128 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 103 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 103 3657 01f8 0E .uleb128 0xe @@ -6178,7 +6178,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 3711 .LLST0: 3712 0000 00000000 .4byte .LFB11 3713 0004 04000000 .4byte .LCFI0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 104 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 104 3714 0008 0200 .2byte 0x2 @@ -6238,7 +6238,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 3768 007f 08 .byte 0x8 3769 0080 FF .byte 0xff 3770 0081 1A .byte 0x1a - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 105 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 105 3771 0082 21 .byte 0x21 @@ -6298,7 +6298,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 3825 0104 7D .byte 0x7d 3826 0105 10 .sleb128 16 3827 0106 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 106 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 106 3828 010a 00000000 .4byte 0 @@ -6358,7 +6358,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 3882 0190 02000000 .4byte .LCFI5 3883 0194 38020000 .4byte .LFE4 3884 0198 0200 .2byte 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 107 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 107 3885 019a 7D .byte 0x7d @@ -6418,7 +6418,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 3939 0223 50 .byte 0x50 3940 0224 00000000 .4byte 0 3941 0228 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 108 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 108 3942 .LLST16: @@ -6478,7 +6478,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 3996 02ad 00000000 .4byte .LVL69 3997 02b1 0C000000 .4byte .LVL70 3998 02b5 0100 .2byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 109 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 109 3999 02b7 50 .byte 0x50 @@ -6538,7 +6538,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 4053 0028 00000000 .4byte .LFB0 4054 002c B4010000 .4byte .LFE0 4055 0030 00000000 .4byte .LFB1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 110 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 110 4056 0034 08020000 .4byte .LFE1 @@ -6598,7 +6598,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 4089 6B537263 4089 00 4090 .LASF56: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 111 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 111 4091 005e 43595F50 .ascii "CY_PM_BACKUP_STRUCT\000" @@ -6658,7 +6658,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 4112 .LASF105: 4113 0106 43795664 .ascii "CyVdLvDigitEnable\000" 4113 4C764469 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 112 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 112 4113 67697445 @@ -6718,7 +6718,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 4137 6C6500 4138 .LASF112: 4139 01a4 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\cyPm.c\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 113 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 113 4139 6E657261 @@ -6738,411 +6738,412 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 1 4145 48696252 4145 6573746F 4145 726500 - 4146 .LASF113: - 4147 01ea 573A5C53 .ascii "W:\\SCSI2SD\\USB_Bootloader.cydsn\000" - 4147 43534932 - 4147 53445C55 - 4147 53425F42 - 4147 6F6F746C - 4148 .LASF74: - 4149 020a 6D61736B .ascii "mask\000" - 4149 00 - 4150 .LASF53: - 4151 020f 696D6F41 .ascii "imoActFreq\000" - 4151 63744672 - 4151 657100 - 4152 .LASF8: - 4153 021a 756E7369 .ascii "unsigned int\000" - 4153 676E6564 - 4153 20696E74 + 4146 .LASF74: + 4147 01ea 6D61736B .ascii "mask\000" + 4147 00 + 4148 .LASF53: + 4149 01ef 696D6F41 .ascii "imoActFreq\000" + 4149 63744672 + 4149 657100 + 4150 .LASF8: + 4151 01fa 756E7369 .ascii "unsigned int\000" + 4151 676E6564 + 4151 20696E74 + 4151 00 + 4152 .LASF45: + 4153 0207 73636374 .ascii "scctData\000" + 4153 44617461 4153 00 - 4154 .LASF45: - 4155 0227 73636374 .ascii "scctData\000" - 4155 44617461 - 4155 00 - 4156 .LASF88: - 4157 0230 4379494D .ascii "CyIMO_SetSource\000" - 4157 4F5F5365 - 4157 74536F75 - 4157 72636500 - 4158 .LASF21: - 4159 0240 696D6F46 .ascii "imoFreq\000" - 4159 72657100 - 4160 .LASF5: - 4161 0248 6C6F6E67 .ascii "long unsigned int\000" - 4161 20756E73 - 4161 69676E65 - 4161 6420696E - 4161 7400 - 4162 .LASF46: - 4163 025a 6C766964 .ascii "lvidEn\000" - 4163 456E00 - 4164 .LASF34: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 114 - - - 4165 0261 6379506D .ascii "cyPmClockBackupStruct\000" - 4165 436C6F63 - 4165 6B426163 - 4165 6B757053 - 4165 74727563 - 4166 .LASF115: - 4167 0277 4379456E .ascii "CyEnterCriticalSection\000" - 4167 74657243 - 4167 72697469 - 4167 63616C53 - 4167 65637469 - 4168 .LASF35: - 4169 028e 6379506D .ascii "cyPmBackupStruct\000" - 4169 4261636B - 4169 75705374 - 4169 72756374 - 4169 00 - 4170 .LASF104: - 4171 029f 4379494C .ascii "CyILO_SetPowerMode\000" - 4171 4F5F5365 - 4171 74506F77 - 4171 65724D6F - 4171 646500 - 4172 .LASF96: - 4173 02b2 4379494D .ascii "CyIMO_Stop\000" - 4173 4F5F5374 - 4173 6F7000 - 4174 .LASF33: - 4175 02bd 43595F50 .ascii "CY_PM_CLOCK_BACKUP_STRUCT\000" - 4175 4D5F434C - 4175 4F434B5F - 4175 4241434B - 4175 55505F53 - 4176 .LASF3: - 4177 02d7 73686F72 .ascii "short unsigned int\000" - 4177 7420756E - 4177 7369676E - 4177 65642069 - 4177 6E7400 - 4178 .LASF78: - 4179 02ea 63747749 .ascii "ctwInterval\000" - 4179 6E746572 - 4179 76616C00 - 4180 .LASF103: - 4181 02f6 43795664 .ascii "CyVdHvAnalogDisable\000" - 4181 4876416E - 4181 616C6F67 - 4181 44697361 - 4181 626C6500 - 4182 .LASF90: - 4183 030a 43794D61 .ascii "CyMasterClk_SetSource\000" - 4183 73746572 - 4183 436C6B5F - 4183 53657453 - 4183 6F757263 - 4184 .LASF40: - 4185 0320 77616B65 .ascii "wakeupCfg0\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 115 + 4154 .LASF88: + 4155 0210 4379494D .ascii "CyIMO_SetSource\000" + 4155 4F5F5365 + 4155 74536F75 + 4155 72636500 + 4156 .LASF21: + 4157 0220 696D6F46 .ascii "imoFreq\000" + 4157 72657100 + 4158 .LASF5: + 4159 0228 6C6F6E67 .ascii "long unsigned int\000" + 4159 20756E73 + 4159 69676E65 + 4159 6420696E + 4159 7400 + 4160 .LASF46: + 4161 023a 6C766964 .ascii "lvidEn\000" + 4161 456E00 + 4162 .LASF34: + 4163 0241 6379506D .ascii "cyPmClockBackupStruct\000" + 4163 436C6F63 + 4163 6B426163 + 4163 6B757053 + 4163 74727563 + 4164 .LASF115: + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 114 + + + 4165 0257 4379456E .ascii "CyEnterCriticalSection\000" + 4165 74657243 + 4165 72697469 + 4165 63616C53 + 4165 65637469 + 4166 .LASF35: + 4167 026e 6379506D .ascii "cyPmBackupStruct\000" + 4167 4261636B + 4167 75705374 + 4167 72756374 + 4167 00 + 4168 .LASF104: + 4169 027f 4379494C .ascii "CyILO_SetPowerMode\000" + 4169 4F5F5365 + 4169 74506F77 + 4169 65724D6F + 4169 646500 + 4170 .LASF96: + 4171 0292 4379494D .ascii "CyIMO_Stop\000" + 4171 4F5F5374 + 4171 6F7000 + 4172 .LASF33: + 4173 029d 43595F50 .ascii "CY_PM_CLOCK_BACKUP_STRUCT\000" + 4173 4D5F434C + 4173 4F434B5F + 4173 4241434B + 4173 55505F53 + 4174 .LASF3: + 4175 02b7 73686F72 .ascii "short unsigned int\000" + 4175 7420756E + 4175 7369676E + 4175 65642069 + 4175 6E7400 + 4176 .LASF78: + 4177 02ca 63747749 .ascii "ctwInterval\000" + 4177 6E746572 + 4177 76616C00 + 4178 .LASF103: + 4179 02d6 43795664 .ascii "CyVdHvAnalogDisable\000" + 4179 4876416E + 4179 616C6F67 + 4179 44697361 + 4179 626C6500 + 4180 .LASF90: + 4181 02ea 43794D61 .ascii "CyMasterClk_SetSource\000" + 4181 73746572 + 4181 436C6B5F + 4181 53657453 + 4181 6F757263 + 4182 .LASF40: + 4183 0300 77616B65 .ascii "wakeupCfg0\000" + 4183 75704366 + 4183 673000 + 4184 .LASF41: + 4185 030b 77616B65 .ascii "wakeupCfg1\000" + 4185 75704366 + 4185 673100 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 115 - 4185 75704366 - 4185 673000 - 4186 .LASF41: - 4187 032b 77616B65 .ascii "wakeupCfg1\000" + 4186 .LASF42: + 4187 0316 77616B65 .ascii "wakeupCfg2\000" 4187 75704366 - 4187 673100 - 4188 .LASF42: - 4189 0336 77616B65 .ascii "wakeupCfg2\000" - 4189 75704366 - 4189 673200 - 4190 .LASF62: - 4191 0341 636C6B42 .ascii "clkBusDivTmp\000" - 4191 75734469 - 4191 76546D70 - 4191 00 - 4192 .LASF55: - 4193 034e 626F6F73 .ascii "boostRefExt\000" - 4193 74526566 - 4193 45787400 - 4194 .LASF26: - 4195 035a 636C6B49 .ascii "clkImoSrc\000" - 4195 6D6F5372 - 4195 6300 - 4196 .LASF59: - 4197 0364 4379506D .ascii "CyPmSaveClocks\000" - 4197 53617665 - 4197 436C6F63 - 4197 6B7300 - 4198 .LASF98: - 4199 0373 43795854 .ascii "CyXTAL_Start\000" - 4199 414C5F53 - 4199 74617274 - 4199 00 - 4200 .LASF39: - 4201 0380 736C7054 .ascii "slpTrBypass\000" - 4201 72427970 - 4201 61737300 - 4202 .LASF17: - 4203 038c 73697A65 .ascii "sizetype\000" - 4203 74797065 - 4203 00 - 4204 .LASF63: - 4205 0395 6379506D .ascii "cyPmImoFreqMhz2Reg\000" - 4205 496D6F46 - 4205 7265714D - 4205 687A3252 - 4205 656700 - 4206 .LASF18: - 4207 03a8 656E436C .ascii "enClkA\000" - 4207 6B4100 - 4208 .LASF19: - 4209 03af 656E436C .ascii "enClkD\000" - 4209 6B4400 - 4210 .LASF109: - 4211 03b6 4379494C .ascii "CyILO_Start100K\000" - 4211 4F5F5374 - 4211 61727431 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 116 - - - 4211 30304B00 - 4212 .LASF66: - 4213 03c6 77616B65 .ascii "wakeupSource\000" - 4213 7570536F - 4213 75726365 - 4213 00 - 4214 .LASF93: - 4215 03d3 4379504C .ascii "CyPLL_OUT_Stop\000" - 4215 4C5F4F55 - 4215 545F5374 - 4215 6F7000 - 4216 .LASF89: - 4217 03e2 43794D61 .ascii "CyMasterClk_SetDivider\000" - 4217 73746572 - 4217 436C6B5F - 4217 53657444 - 4217 69766964 - 4218 .LASF25: - 4219 03f9 696D6F43 .ascii "imoClkSrc\000" - 4219 6C6B5372 - 4219 6300 - 4220 .LASF12: - 4221 0403 666C6F61 .ascii "float\000" - 4221 7400 - 4222 .LASF100: - 4223 0409 43794578 .ascii "CyExitCriticalSection\000" - 4223 69744372 - 4223 69746963 - 4223 616C5365 - 4223 6374696F - 4224 .LASF67: - 4225 041f 4379506D .ascii "CyPmSleep\000" - 4225 536C6565 - 4225 7000 - 4226 .LASF51: - 4227 0429 6C766964 .ascii "lvidRst\000" - 4227 52737400 - 4228 .LASF64: - 4229 0431 4379506D .ascii "CyPmAltAct\000" - 4229 416C7441 - 4229 637400 - 4230 .LASF95: - 4231 043c 43794465 .ascii "CyDelayCycles\000" - 4231 6C617943 - 4231 79636C65 - 4231 7300 - 4232 .LASF111: - 4233 044a 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 4233 4320342E - 4233 372E3320 - 4233 32303133 - 4233 30333132 - 4234 047d 616E6368 .ascii "anch revision 196615]\000" - 4234 20726576 - 4234 6973696F - 4234 6E203139 - 4234 36363135 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 117 - - - 4235 .LASF16: - 4236 0493 72656738 .ascii "reg8\000" - 4236 00 - 4237 .LASF79: - 4238 0498 4379506D .ascii "CyPmOppsSet\000" - 4238 4F707073 - 4238 53657400 - 4239 .LASF1: - 4240 04a4 756E7369 .ascii "unsigned char\000" - 4240 676E6564 - 4240 20636861 - 4240 7200 - 4241 .LASF83: - 4242 04b2 6379506D .ascii "cyPmClockBackup\000" - 4242 436C6F63 - 4242 6B426163 - 4242 6B757000 - 4243 .LASF30: - 4244 04c2 706C6C45 .ascii "pllEnableState\000" - 4244 6E61626C - 4244 65537461 - 4244 746500 - 4245 .LASF37: - 4246 04d1 696C6F31 .ascii "ilo1kEnable\000" - 4246 6B456E61 - 4246 626C6500 - 4247 .LASF2: - 4248 04dd 73686F72 .ascii "short int\000" - 4248 7420696E - 4248 7400 - 4249 .LASF57: - 4250 04e7 4379506D .ascii "CyPmHibSlpSaveSet\000" - 4250 48696253 - 4250 6C705361 - 4250 76655365 - 4250 7400 - 4251 .LASF38: - 4252 04f9 696C6F31 .ascii "ilo100kEnable\000" - 4252 30306B45 - 4252 6E61626C - 4252 6500 - 4253 .LASF14: - 4254 0507 63686172 .ascii "char\000" - 4254 00 - 4255 .LASF92: - 4256 050c 4379494D .ascii "CyIMO_DisableDoubler\000" - 4256 4F5F4469 - 4256 7361626C - 4256 65446F75 - 4256 626C6572 - 4257 .LASF101: - 4258 0521 43795664 .ascii "CyVdLvDigitDisable\000" - 4258 4C764469 - 4258 67697444 - 4258 69736162 - 4258 6C6500 - 4259 .LASF54: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 118 - - - 4260 0534 696D6F41 .ascii "imoActFreq12Mhz\000" - 4260 63744672 - 4260 65713132 - 4260 4D687A00 - 4261 .LASF73: - 4262 0544 4379506D .ascii "CyPmHibernate\000" - 4262 48696265 - 4262 726E6174 - 4262 6500 - 4263 .LASF85: - 4264 0552 4379466C .ascii "CyFlash_SetWaitCycles\000" - 4264 6173685F - 4264 53657457 - 4264 61697443 - 4264 79636C65 - 4265 .LASF81: - 4266 0568 66747749 .ascii "ftwInterval\000" - 4266 6E746572 - 4266 76616C00 - 4267 .LASF84: - 4268 0574 6379506D .ascii "cyPmImoFreqReg2Mhz\000" - 4268 496D6F46 - 4268 72657152 - 4268 6567324D - 4268 687A00 - 4269 .LASF114: - 4270 0587 4379506D .ascii "CyPmReadStatus\000" - 4270 52656164 - 4270 53746174 - 4270 757300 - 4271 .LASF91: - 4272 0596 43794275 .ascii "CyBusClk_SetDivider\000" - 4272 73436C6B - 4272 5F536574 - 4272 44697669 - 4272 64657200 - 4273 .LASF32: - 4274 05aa 636C6B44 .ascii "clkDistDelay\000" - 4274 69737444 - 4274 656C6179 - 4274 00 - 4275 .LASF77: - 4276 05b7 4379506D .ascii "CyPmCtwSetInterval\000" - 4276 43747753 - 4276 6574496E - 4276 74657276 - 4276 616C00 - 4277 .LASF61: - 4278 05ca 73746174 .ascii "status\000" - 4278 757300 - 4279 .LASF48: - 4280 05d1 6C766961 .ascii "lviaEn\000" - 4280 456E00 - 4281 .LASF86: - 4282 05d8 4379494D .ascii "CyIMO_SetFreq\000" - 4282 4F5F5365 - 4282 74467265 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 119 - - - 4282 7100 - 4283 .LASF97: - 4284 05e6 4379494D .ascii "CyIMO_EnableDoubler\000" - 4284 4F5F456E - 4284 61626C65 - 4284 446F7562 - 4284 6C657200 - 4285 .LASF69: - 4286 05fa 4379506D .ascii "CyPmHibSaveSet\000" - 4286 48696253 - 4286 61766553 - 4286 657400 - 4287 .LASF65: - 4288 0609 77616B65 .ascii "wakeupTime\000" - 4288 75705469 - 4288 6D6500 - 4289 .LASF106: - 4290 0614 43795664 .ascii "CyVdLvAnalogEnable\000" - 4290 4C76416E - 4290 616C6F67 - 4290 456E6162 - 4290 6C6500 - 4291 .LASF15: - 4292 0627 63797374 .ascii "cystatus\000" - 4292 61747573 - 4292 00 - 4293 .LASF23: - 4294 0630 666C6173 .ascii "flashWaitCycles\000" - 4294 68576169 - 4294 74437963 - 4294 6C657300 - 4295 .LASF52: - 4296 0640 6C766961 .ascii "lviaRst\000" - 4296 52737400 - 4297 .LASF107: - 4298 0648 43795664 .ascii "CyVdHvAnalogEnable\000" - 4298 4876416E - 4298 616C6F67 - 4298 456E6162 - 4298 6C6500 - 4299 .LASF94: - 4300 065b 43795854 .ascii "CyXTAL_Stop\000" - 4300 414C5F53 - 4300 746F7000 - 4301 .LASF82: - 4302 0667 6379506D .ascii "cyPmBackup\000" - 4302 4261636B - 4302 757000 - 4303 .LASF47: - 4304 0672 6C766964 .ascii "lvidTrip\000" - 4304 54726970 - 4304 00 - 4305 .LASF24: - 4306 067b 696D6F45 .ascii "imoEnable\000" - 4306 6E61626C - 4306 6500 - 4307 .LASF75: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cccYZJXD.s page 120 - - - 4308 0685 696E7465 .ascii "interruptStatus\000" - 4308 72727570 - 4308 74537461 - 4308 74757300 - 4309 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br + 4187 673200 + 4188 .LASF62: + 4189 0321 636C6B42 .ascii "clkBusDivTmp\000" + 4189 75734469 + 4189 76546D70 + 4189 00 + 4190 .LASF55: + 4191 032e 626F6F73 .ascii "boostRefExt\000" + 4191 74526566 + 4191 45787400 + 4192 .LASF26: + 4193 033a 636C6B49 .ascii "clkImoSrc\000" + 4193 6D6F5372 + 4193 6300 + 4194 .LASF59: + 4195 0344 4379506D .ascii "CyPmSaveClocks\000" + 4195 53617665 + 4195 436C6F63 + 4195 6B7300 + 4196 .LASF113: + 4197 0353 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" + 4197 43534932 + 4197 53445C73 + 4197 6F667477 + 4197 6172655C + 4198 0382 6E00 .ascii "n\000" + 4199 .LASF98: + 4200 0384 43795854 .ascii "CyXTAL_Start\000" + 4200 414C5F53 + 4200 74617274 + 4200 00 + 4201 .LASF39: + 4202 0391 736C7054 .ascii "slpTrBypass\000" + 4202 72427970 + 4202 61737300 + 4203 .LASF17: + 4204 039d 73697A65 .ascii "sizetype\000" + 4204 74797065 + 4204 00 + 4205 .LASF63: + 4206 03a6 6379506D .ascii "cyPmImoFreqMhz2Reg\000" + 4206 496D6F46 + 4206 7265714D + 4206 687A3252 + 4206 656700 + 4207 .LASF18: + 4208 03b9 656E436C .ascii "enClkA\000" + 4208 6B4100 + 4209 .LASF19: + 4210 03c0 656E436C .ascii "enClkD\000" + 4210 6B4400 + 4211 .LASF109: + 4212 03c7 4379494C .ascii "CyILO_Start100K\000" + 4212 4F5F5374 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 116 + + + 4212 61727431 + 4212 30304B00 + 4213 .LASF66: + 4214 03d7 77616B65 .ascii "wakeupSource\000" + 4214 7570536F + 4214 75726365 + 4214 00 + 4215 .LASF93: + 4216 03e4 4379504C .ascii "CyPLL_OUT_Stop\000" + 4216 4C5F4F55 + 4216 545F5374 + 4216 6F7000 + 4217 .LASF89: + 4218 03f3 43794D61 .ascii "CyMasterClk_SetDivider\000" + 4218 73746572 + 4218 436C6B5F + 4218 53657444 + 4218 69766964 + 4219 .LASF25: + 4220 040a 696D6F43 .ascii "imoClkSrc\000" + 4220 6C6B5372 + 4220 6300 + 4221 .LASF12: + 4222 0414 666C6F61 .ascii "float\000" + 4222 7400 + 4223 .LASF100: + 4224 041a 43794578 .ascii "CyExitCriticalSection\000" + 4224 69744372 + 4224 69746963 + 4224 616C5365 + 4224 6374696F + 4225 .LASF67: + 4226 0430 4379506D .ascii "CyPmSleep\000" + 4226 536C6565 + 4226 7000 + 4227 .LASF51: + 4228 043a 6C766964 .ascii "lvidRst\000" + 4228 52737400 + 4229 .LASF64: + 4230 0442 4379506D .ascii "CyPmAltAct\000" + 4230 416C7441 + 4230 637400 + 4231 .LASF95: + 4232 044d 43794465 .ascii "CyDelayCycles\000" + 4232 6C617943 + 4232 79636C65 + 4232 7300 + 4233 .LASF111: + 4234 045b 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" + 4234 4320342E + 4234 372E3320 + 4234 32303133 + 4234 30333132 + 4235 048e 616E6368 .ascii "anch revision 196615]\000" + 4235 20726576 + 4235 6973696F + 4235 6E203139 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 117 + + + 4235 36363135 + 4236 .LASF16: + 4237 04a4 72656738 .ascii "reg8\000" + 4237 00 + 4238 .LASF79: + 4239 04a9 4379506D .ascii "CyPmOppsSet\000" + 4239 4F707073 + 4239 53657400 + 4240 .LASF1: + 4241 04b5 756E7369 .ascii "unsigned char\000" + 4241 676E6564 + 4241 20636861 + 4241 7200 + 4242 .LASF83: + 4243 04c3 6379506D .ascii "cyPmClockBackup\000" + 4243 436C6F63 + 4243 6B426163 + 4243 6B757000 + 4244 .LASF30: + 4245 04d3 706C6C45 .ascii "pllEnableState\000" + 4245 6E61626C + 4245 65537461 + 4245 746500 + 4246 .LASF37: + 4247 04e2 696C6F31 .ascii "ilo1kEnable\000" + 4247 6B456E61 + 4247 626C6500 + 4248 .LASF2: + 4249 04ee 73686F72 .ascii "short int\000" + 4249 7420696E + 4249 7400 + 4250 .LASF57: + 4251 04f8 4379506D .ascii "CyPmHibSlpSaveSet\000" + 4251 48696253 + 4251 6C705361 + 4251 76655365 + 4251 7400 + 4252 .LASF38: + 4253 050a 696C6F31 .ascii "ilo100kEnable\000" + 4253 30306B45 + 4253 6E61626C + 4253 6500 + 4254 .LASF14: + 4255 0518 63686172 .ascii "char\000" + 4255 00 + 4256 .LASF92: + 4257 051d 4379494D .ascii "CyIMO_DisableDoubler\000" + 4257 4F5F4469 + 4257 7361626C + 4257 65446F75 + 4257 626C6572 + 4258 .LASF101: + 4259 0532 43795664 .ascii "CyVdLvDigitDisable\000" + 4259 4C764469 + 4259 67697444 + 4259 69736162 + 4259 6C6500 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 118 + + + 4260 .LASF54: + 4261 0545 696D6F41 .ascii "imoActFreq12Mhz\000" + 4261 63744672 + 4261 65713132 + 4261 4D687A00 + 4262 .LASF73: + 4263 0555 4379506D .ascii "CyPmHibernate\000" + 4263 48696265 + 4263 726E6174 + 4263 6500 + 4264 .LASF85: + 4265 0563 4379466C .ascii "CyFlash_SetWaitCycles\000" + 4265 6173685F + 4265 53657457 + 4265 61697443 + 4265 79636C65 + 4266 .LASF81: + 4267 0579 66747749 .ascii "ftwInterval\000" + 4267 6E746572 + 4267 76616C00 + 4268 .LASF84: + 4269 0585 6379506D .ascii "cyPmImoFreqReg2Mhz\000" + 4269 496D6F46 + 4269 72657152 + 4269 6567324D + 4269 687A00 + 4270 .LASF114: + 4271 0598 4379506D .ascii "CyPmReadStatus\000" + 4271 52656164 + 4271 53746174 + 4271 757300 + 4272 .LASF91: + 4273 05a7 43794275 .ascii "CyBusClk_SetDivider\000" + 4273 73436C6B + 4273 5F536574 + 4273 44697669 + 4273 64657200 + 4274 .LASF32: + 4275 05bb 636C6B44 .ascii "clkDistDelay\000" + 4275 69737444 + 4275 656C6179 + 4275 00 + 4276 .LASF77: + 4277 05c8 4379506D .ascii "CyPmCtwSetInterval\000" + 4277 43747753 + 4277 6574496E + 4277 74657276 + 4277 616C00 + 4278 .LASF61: + 4279 05db 73746174 .ascii "status\000" + 4279 757300 + 4280 .LASF48: + 4281 05e2 6C766961 .ascii "lviaEn\000" + 4281 456E00 + 4282 .LASF86: + 4283 05e9 4379494D .ascii "CyIMO_SetFreq\000" + 4283 4F5F5365 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 119 + + + 4283 74467265 + 4283 7100 + 4284 .LASF97: + 4285 05f7 4379494D .ascii "CyIMO_EnableDoubler\000" + 4285 4F5F456E + 4285 61626C65 + 4285 446F7562 + 4285 6C657200 + 4286 .LASF69: + 4287 060b 4379506D .ascii "CyPmHibSaveSet\000" + 4287 48696253 + 4287 61766553 + 4287 657400 + 4288 .LASF65: + 4289 061a 77616B65 .ascii "wakeupTime\000" + 4289 75705469 + 4289 6D6500 + 4290 .LASF106: + 4291 0625 43795664 .ascii "CyVdLvAnalogEnable\000" + 4291 4C76416E + 4291 616C6F67 + 4291 456E6162 + 4291 6C6500 + 4292 .LASF15: + 4293 0638 63797374 .ascii "cystatus\000" + 4293 61747573 + 4293 00 + 4294 .LASF23: + 4295 0641 666C6173 .ascii "flashWaitCycles\000" + 4295 68576169 + 4295 74437963 + 4295 6C657300 + 4296 .LASF52: + 4297 0651 6C766961 .ascii "lviaRst\000" + 4297 52737400 + 4298 .LASF107: + 4299 0659 43795664 .ascii "CyVdHvAnalogEnable\000" + 4299 4876416E + 4299 616C6F67 + 4299 456E6162 + 4299 6C6500 + 4300 .LASF94: + 4301 066c 43795854 .ascii "CyXTAL_Stop\000" + 4301 414C5F53 + 4301 746F7000 + 4302 .LASF82: + 4303 0678 6379506D .ascii "cyPmBackup\000" + 4303 4261636B + 4303 757000 + 4304 .LASF47: + 4305 0683 6C766964 .ascii "lvidTrip\000" + 4305 54726970 + 4305 00 + 4306 .LASF24: + 4307 068c 696D6F45 .ascii "imoEnable\000" + 4307 6E61626C + 4307 6500 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 120 + + + 4308 .LASF75: + 4309 0696 696E7465 .ascii "interruptStatus\000" + 4309 72727570 + 4309 74537461 + 4309 74757300 + 4310 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/cyPm.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/cyPm.o index 200e226c02758de3334cfc3ef77d7c550b74a830..70070848f5368a71ddd9e656f7ff2d159372444c 100755 GIT binary patch delta 1307 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a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/cyfitter_cfg.lst b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/cyfitter_cfg.lst index a551fd4e..7e94b9e9 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/cyfitter_cfg.lst +++ b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/cyfitter_cfg.lst @@ -1,4 +1,4 @@ -ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 1 +ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 1 1 .syntax unified @@ -29,7 +29,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 1 26 .file 1 ".\\Generated_Source\\PSoC5\\cyfitter_cfg.c" 1:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /******************************************************************************* 2:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * FILENAME: cyfitter_cfg.c - 3:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * PSoC Creator 3.0 + 3:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * PSoC Creator 3.0 Component Pack 7 4:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * 5:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Description: 6:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * This file is automatically generated by PSoC Creator with device @@ -58,7 +58,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 1 29:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #define CYPACKED_ATTR __attribute__ ((packed)) 30:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #define CYALIGNED __attribute__ ((aligned)) 31:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #define CY_CFG_UNUSED __attribute__ ((unused)) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 2 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 2 32:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #define CY_CFG_SECTION __attribute__ ((section(".psocinit"))) @@ -118,7 +118,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 1 86:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #ifdef CY_NEED_CYCLOCKSTARTUPERROR 87:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /******************************************************************************* 88:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Function Name: CyClockStartupError - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 3 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 3 89:.\Generated_Source\PSoC5/cyfitter_cfg.c **** ******************************************************************************** @@ -178,7 +178,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 1 143:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Return: 144:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * void 145:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 4 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 4 146:.\Generated_Source\PSoC5/cyfitter_cfg.c **** *******************************************************************************/ @@ -238,7 +238,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 1 200:.\Generated_Source\PSoC5/cyfitter_cfg.c **** pllLock = 0u; 201:.\Generated_Source\PSoC5/cyfitter_cfg.c **** for (timeout = 250u / 10u; (timeout > 0u) && (pllLock != 0x03u); timeout--) 202:.\Generated_Source\PSoC5/cyfitter_cfg.c **** { - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 5 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 5 203:.\Generated_Source\PSoC5/cyfitter_cfg.c **** pllLock = 0x03u & ((uint8)((uint8)pllLock << 1) | ((CY_GET_XTND_REG8((void CYFAR *)CYREG_FASTCLK_ @@ -298,7 +298,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 1 257:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Summary: 258:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Enables or disables the analog pumps feeding analog routing switches. 259:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Intended to be called at startup, based on the Vdda system configuration; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 6 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 6 260:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * may be called during operation when the user informs us that the Vdda voltage @@ -358,7 +358,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 1 286:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 287:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /******************************************************************************* 288:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Function Name: cyfitter_cfg - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 7 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 7 289:.\Generated_Source\PSoC5/cyfitter_cfg.c **** ******************************************************************************** @@ -399,35 +399,39 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 1 311:.\Generated_Source\PSoC5/cyfitter_cfg.c **** static const uint8 CYCODE BS_IOPINS0_8_VAL[] = { 312:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xC0u, 0x00u}; 313:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 314:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* IOPINS0_4 Address: CYREG_PRT4_DM0 Size (bytes): 8 */ - 315:.\Generated_Source\PSoC5/cyfitter_cfg.c **** static const uint8 CYCODE BS_IOPINS0_4_VAL[] = { - 316:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x00u, 0xFCu, 0xFCu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + 314:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* IOPINS0_3 Address: CYREG_PRT3_DM0 Size (bytes): 8 */ + 315:.\Generated_Source\PSoC5/cyfitter_cfg.c **** static const uint8 CYCODE BS_IOPINS0_3_VAL[] = { + 316:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x00u, 0x3Eu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; 317:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 318:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* IOPINS0_6 Address: CYREG_PRT6_DM0 Size (bytes): 8 */ - 319:.\Generated_Source\PSoC5/cyfitter_cfg.c **** static const uint8 CYCODE BS_IOPINS0_6_VAL[] = { - 320:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x00u, 0x0Fu, 0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + 318:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* IOPINS0_4 Address: CYREG_PRT4_DM0 Size (bytes): 8 */ + 319:.\Generated_Source\PSoC5/cyfitter_cfg.c **** static const uint8 CYCODE BS_IOPINS0_4_VAL[] = { + 320:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x00u, 0xFCu, 0xFCu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; 321:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 322:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #ifdef CYGlobalIntDisable - 323:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Disable interrupts by default. Let user enable if/when they want. */ - 324:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CYGlobalIntDisable - 68 .loc 1 324 0 - 69 @ 324 ".\Generated_Source\PSoC5\cyfitter_cfg.c" 1 + 322:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* IOPINS0_6 Address: CYREG_PRT6_DM0 Size (bytes): 8 */ + 323:.\Generated_Source\PSoC5/cyfitter_cfg.c **** static const uint8 CYCODE BS_IOPINS0_6_VAL[] = { + 324:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x00u, 0x0Fu, 0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + 325:.\Generated_Source\PSoC5/cyfitter_cfg.c **** + 326:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #ifdef CYGlobalIntDisable + 327:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Disable interrupts by default. Let user enable if/when they want. */ + 328:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CYGlobalIntDisable + 68 .loc 1 328 0 + 69 @ 328 ".\Generated_Source\PSoC5\cyfitter_cfg.c" 1 70 0002 72B6 CPSID i 71 @ 0 "" 2 - 325:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #endif - 326:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 327:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 328:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 8 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 8 - 329:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x01 - 72 .loc 1 329 0 + 329:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #endif + 330:.\Generated_Source\PSoC5/cyfitter_cfg.c **** + 331:.\Generated_Source\PSoC5/cyfitter_cfg.c **** + 332:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). * + 333:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x01 + 72 .loc 1 333 0 73 .thumb - 74 0004 5A4B ldr r3, .L23 + 74 0004 5E4B ldr r3, .L23 75 0006 0122 movs r2, #1 - 76 .LBB30: - 77 .LBB31: + 76 .LBB32: + 77 .LBB33: 190:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u); 78 .loc 1 190 0 79 0008 A3F5A061 sub r1, r3, #1280 @@ -442,13 +446,13 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 1 85 0012 5224 movs r4, #82 194:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_ 86 .loc 1 194 0 - 87 0014 574E ldr r6, .L23+4 - 88 .LBE31: - 89 .LBE30: - 90 .loc 1 329 0 + 87 0014 5B4E ldr r6, .L23+4 + 88 .LBE33: + 89 .LBE32: + 90 .loc 1 333 0 91 0016 1A70 strb r2, [r3, #0] - 92 .LBB34: - 93 .LBB32: + 92 .LBB36: + 93 .LBB34: 190:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u); 94 .loc 1 190 0 95 0018 0870 strb r0, [r1, #0] @@ -460,10 +464,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 1 99 001c 3778 ldrb r7, [r6, #0] @ zero_extendqisi2 197:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0818u); 100 .loc 1 197 0 - 101 001e 564B ldr r3, .L23+8 + 101 001e 5A4B ldr r3, .L23+8 194:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_ 102 .loc 1 194 0 - 103 0020 564A ldr r2, .L23+12 + 103 0020 5A4A ldr r2, .L23+12 197:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0818u); 104 .loc 1 197 0 105 0022 40F61800 movw r0, #2072 @@ -474,13 +478,13 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 1 108 .loc 1 194 0 109 002a 1770 strb r7, [r2, #0] 198:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1251u); + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 9 + + 110 .loc 1 198 0 111 002c 1925 movs r5, #25 197:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0818u); 112 .loc 1 197 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 9 - - 113 002e 1880 strh r0, [r3, #0] @ movhi 200:.\Generated_Source\PSoC5/cyfitter_cfg.c **** pllLock = 0u; 114 .loc 1 200 0 @@ -492,7 +496,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 1 119 .L6: 203:.\Generated_Source\PSoC5/cyfitter_cfg.c **** pllLock = 0x03u & ((uint8)((uint8)pllLock << 1) | ((CY_GET_XTND_REG8((void CYFAR *)CYREG_FASTCLK_ 120 .loc 1 203 0 - 121 0036 524E ldr r6, .L23+16 + 121 0036 564E ldr r6, .L23+16 204:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CyDelayCycles(10u * 48u); /* Delay 10us based on 48MHz clock */ 122 .loc 1 204 0 123 0038 4FF4F070 mov r0, #480 @@ -519,28 +523,28 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 1 139 0054 EFD1 bne .L6 213:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x0100u); 140 .loc 1 213 0 - 141 0056 4B48 ldr r0, .L23+20 + 141 0056 4F48 ldr r0, .L23+20 215:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG0), 0x00u); 142 .loc 1 215 0 - 143 0058 4B4F ldr r7, .L23+24 + 143 0058 4F4F ldr r7, .L23+24 144 005a 0026 movs r6, #0 213:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x0100u); 145 .loc 1 213 0 146 005c 4FF48073 mov r3, #256 - 147 .LBE32: - 148 .LBE34: - 330:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Setup clocks based on selections from Clock DWR */ - 331:.\Generated_Source\PSoC5/cyfitter_cfg.c **** ClockSetup(); - 332:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Enable/Disable Debug functionality based on settings from System DWR */ - 333:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG, (CY_GET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DE - 149 .loc 1 333 0 - 150 0060 4A4D ldr r5, .L23+28 - 151 .LBB35: - 152 .LBB33: + 147 .LBE34: + 148 .LBE36: + 334:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Setup clocks based on selections from Clock DWR */ + 335:.\Generated_Source\PSoC5/cyfitter_cfg.c **** ClockSetup(); + 336:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Enable/Disable Debug functionality based on settings from System DWR */ + 337:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG, (CY_GET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DE + 149 .loc 1 337 0 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 10 + + + 150 0060 4E4D ldr r5, .L23+28 + 151 .LBB37: + 152 .LBB35: 214:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x07u); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 10 - - 153 .loc 1 214 0 154 0062 0721 movs r1, #7 216:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG2), 0x48u); @@ -571,9 +575,9 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 1 221:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u); 172 .loc 1 221 0 173 0074 00F8034C strb r4, [r0, #-3] - 174 .LBE33: - 175 .LBE35: - 176 .loc 1 333 0 + 174 .LBE35: + 175 .LBE37: + 176 .loc 1 337 0 177 0078 2878 ldrb r0, [r5, #0] @ zero_extendqisi2 178 007a 40F00403 orr r3, r0, #4 179 007e 2B70 strb r3, [r5, #0] @@ -584,88 +588,89 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 1 184 0082 FEE7 b .L5 185 .LVL8: 186 .L8: - 187 .LBB36: - 188 .LBB37: - 334:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 335:.\Generated_Source\PSoC5/cyfitter_cfg.c **** { - 336:.\Generated_Source\PSoC5/cyfitter_cfg.c **** static const uint32 CYCODE cy_cfg_addr_table[] = { - 337:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40004501u, /* Base address: 0x40004500 Count: 1 */ - 338:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40005201u, /* Base address: 0x40005200 Count: 1 */ - 339:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40011701u, /* Base address: 0x40011700 Count: 1 */ - 340:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40011901u, /* Base address: 0x40011900 Count: 1 */ - 341:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40014003u, /* Base address: 0x40014000 Count: 3 */ - 342:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40014102u, /* Base address: 0x40014100 Count: 2 */ - 343:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40014202u, /* Base address: 0x40014200 Count: 2 */ - 344:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40014302u, /* Base address: 0x40014300 Count: 2 */ - 345:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40014703u, /* Base address: 0x40014700 Count: 3 */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 11 - - - 346:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40014803u, /* Base address: 0x40014800 Count: 3 */ - 347:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40014C02u, /* Base address: 0x40014C00 Count: 2 */ - 348:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40015101u, /* Base address: 0x40015100 Count: 1 */ - 349:.\Generated_Source\PSoC5/cyfitter_cfg.c **** }; - 350:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 351:.\Generated_Source\PSoC5/cyfitter_cfg.c **** static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { - 352:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0x7Eu, 0x02u}, - 353:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0x7Cu, 0x40u}, - 354:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xEEu, 0x0Au}, - 355:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xEEu, 0x0Au}, - 356:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0x33u, 0x80u}, - 357:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0x36u, 0x40u}, - 358:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xCCu, 0x30u}, - 359:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xA6u, 0x40u}, - 360:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xA7u, 0x80u}, - 361:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xA6u, 0x40u}, - 362:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xA7u, 0x80u}, - 363:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xA6u, 0x40u}, - 364:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xA7u, 0x80u}, - 365:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0x08u, 0x08u}, - 366:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0x0Fu, 0x40u}, - 367:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xC2u, 0x0Cu}, - 368:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xAEu, 0x40u}, - 369:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xAFu, 0x80u}, - 370:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xEEu, 0x50u}, - 371:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xACu, 0x08u}, - 372:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xAFu, 0x40u}, - 373:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0x00u, 0x0Au}, - 374:.\Generated_Source\PSoC5/cyfitter_cfg.c **** }; - 375:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 376:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 377:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 378:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CYPACKED typedef struct { - 379:.\Generated_Source\PSoC5/cyfitter_cfg.c **** void CYFAR *address; - 380:.\Generated_Source\PSoC5/cyfitter_cfg.c **** uint16 size; - 381:.\Generated_Source\PSoC5/cyfitter_cfg.c **** } CYPACKED_ATTR cfg_memset_t; + 187 .LBB38: + 188 .LBB39: + 338:.\Generated_Source\PSoC5/cyfitter_cfg.c **** + 339:.\Generated_Source\PSoC5/cyfitter_cfg.c **** { + 340:.\Generated_Source\PSoC5/cyfitter_cfg.c **** static const uint32 CYCODE cy_cfg_addr_table[] = { + 341:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40004501u, /* Base address: 0x40004500 Count: 1 */ + 342:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40005202u, /* Base address: 0x40005200 Count: 2 */ + 343:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40011701u, /* Base address: 0x40011700 Count: 1 */ + 344:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40011901u, /* Base address: 0x40011900 Count: 1 */ + 345:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40014003u, /* Base address: 0x40014000 Count: 3 */ + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 11 + + + 346:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40014102u, /* Base address: 0x40014100 Count: 2 */ + 347:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40014202u, /* Base address: 0x40014200 Count: 2 */ + 348:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40014302u, /* Base address: 0x40014300 Count: 2 */ + 349:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40014703u, /* Base address: 0x40014700 Count: 3 */ + 350:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40014803u, /* Base address: 0x40014800 Count: 3 */ + 351:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40014C02u, /* Base address: 0x40014C00 Count: 2 */ + 352:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40015101u, /* Base address: 0x40015100 Count: 1 */ + 353:.\Generated_Source\PSoC5/cyfitter_cfg.c **** }; + 354:.\Generated_Source\PSoC5/cyfitter_cfg.c **** + 355:.\Generated_Source\PSoC5/cyfitter_cfg.c **** static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { + 356:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0x7Eu, 0x02u}, + 357:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0x1Cu, 0x3Eu}, + 358:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0x7Cu, 0x40u}, + 359:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xEEu, 0x0Au}, + 360:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xEEu, 0x0Au}, + 361:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0x33u, 0x80u}, + 362:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0x36u, 0x40u}, + 363:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xCCu, 0x30u}, + 364:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xA6u, 0x40u}, + 365:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xA7u, 0x80u}, + 366:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xA6u, 0x40u}, + 367:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xA7u, 0x80u}, + 368:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xA6u, 0x40u}, + 369:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xA7u, 0x80u}, + 370:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0x08u, 0x08u}, + 371:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0x0Fu, 0x40u}, + 372:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xC2u, 0x0Cu}, + 373:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xAEu, 0x40u}, + 374:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xAFu, 0x80u}, + 375:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xEEu, 0x50u}, + 376:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xACu, 0x08u}, + 377:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xAFu, 0x40u}, + 378:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0x00u, 0x0Au}, + 379:.\Generated_Source\PSoC5/cyfitter_cfg.c **** }; + 380:.\Generated_Source\PSoC5/cyfitter_cfg.c **** + 381:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 382:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 383:.\Generated_Source\PSoC5/cyfitter_cfg.c **** static const cfg_memset_t CYCODE cfg_memset_list [] = { - 384:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* address, size */ - 385:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {(void CYFAR *)(CYREG_PRT1_DR), 48u}, - 386:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {(void CYFAR *)(CYREG_PRT5_DR), 16u}, - 387:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {(void CYFAR *)(CYREG_PRT12_DR), 16u}, - 388:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u}, - 389:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u}, - 390:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u}, - 391:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u}, - 392:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u}, - 393:.\Generated_Source\PSoC5/cyfitter_cfg.c **** }; - 394:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 395:.\Generated_Source\PSoC5/cyfitter_cfg.c **** uint8 CYDATA i; - 396:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 397:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Zero out critical memory blocks before beginning configuration */ - 398:.\Generated_Source\PSoC5/cyfitter_cfg.c **** for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) - 399:.\Generated_Source\PSoC5/cyfitter_cfg.c **** { - 400:.\Generated_Source\PSoC5/cyfitter_cfg.c **** const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; - 189 .loc 1 400 0 discriminator 2 - 190 0084 424F ldr r7, .L23+32 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 12 - - + 383:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CYPACKED typedef struct { + 384:.\Generated_Source\PSoC5/cyfitter_cfg.c **** void CYFAR *address; + 385:.\Generated_Source\PSoC5/cyfitter_cfg.c **** uint16 size; + 386:.\Generated_Source\PSoC5/cyfitter_cfg.c **** } CYPACKED_ATTR cfg_memset_t; + 387:.\Generated_Source\PSoC5/cyfitter_cfg.c **** + 388:.\Generated_Source\PSoC5/cyfitter_cfg.c **** static const cfg_memset_t CYCODE cfg_memset_list [] = { + 389:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* address, size */ + 390:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {(void CYFAR *)(CYREG_PRT1_DR), 32u}, + 391:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {(void CYFAR *)(CYREG_PRT5_DR), 16u}, + 392:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {(void CYFAR *)(CYREG_PRT12_DR), 16u}, + 393:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u}, + 394:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u}, + 395:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u}, + 396:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u}, + 397:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u}, + 398:.\Generated_Source\PSoC5/cyfitter_cfg.c **** }; + 399:.\Generated_Source\PSoC5/cyfitter_cfg.c **** + 400:.\Generated_Source\PSoC5/cyfitter_cfg.c **** uint8 CYDATA i; + 401:.\Generated_Source\PSoC5/cyfitter_cfg.c **** + 402:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Zero out critical memory blocks before beginning configuration */ + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 12 + + + 403:.\Generated_Source\PSoC5/cyfitter_cfg.c **** for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) + 404:.\Generated_Source\PSoC5/cyfitter_cfg.c **** { + 405:.\Generated_Source\PSoC5/cyfitter_cfg.c **** const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; + 189 .loc 1 405 0 discriminator 2 + 190 0084 464F ldr r7, .L23+32 191 0086 0621 movs r1, #6 192 0088 01FB0672 mla r2, r1, r6, r7 193 .LVL9: - 194 .LBB38: - 195 .LBB39: + 194 .LBB40: + 195 .LBB41: 61:.\Generated_Source\PSoC5/cyfitter_cfg.c **** (void)memset(s, 0, n); 196 .loc 1 61 0 discriminator 2 197 008c 0021 movs r1, #0 @@ -676,34 +681,34 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 1 202 .LVL11: 203 0094 FFF7FEFF bl memset 204 .LVL12: - 205 .LBE39: - 206 .LBE38: - 207 .LBE37: - 398:.\Generated_Source\PSoC5/cyfitter_cfg.c **** for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) - 208 .loc 1 398 0 discriminator 2 + 205 .LBE41: + 206 .LBE40: + 207 .LBE39: + 403:.\Generated_Source\PSoC5/cyfitter_cfg.c **** for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) + 208 .loc 1 403 0 discriminator 2 209 0098 082E cmp r6, #8 210 009a F3D1 bne .L8 - 398:.\Generated_Source\PSoC5/cyfitter_cfg.c **** for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) - 211 .loc 1 398 0 is_stmt 0 + 403:.\Generated_Source\PSoC5/cyfitter_cfg.c **** for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) + 211 .loc 1 403 0 is_stmt 0 212 009c 0023 movs r3, #0 213 009e 1946 mov r1, r3 214 .LVL13: 215 .L11: - 216 .LBB40: - 217 .LBB41: - 218 .LBB42: + 216 .LBB42: + 217 .LBB43: + 218 .LBB44: 154:.\Generated_Source\PSoC5/cyfitter_cfg.c **** uint32 baseAddr = addr_table[i]; 219 .loc 1 154 0 is_stmt 1 - 220 00a0 3C4C ldr r4, .L23+36 - 221 .LBE42: - 222 .LBE41: - 223 .LBE40: + 220 00a0 404C ldr r4, .L23+36 + 221 .LBE44: + 222 .LBE43: + 223 .LBE42: 304:.\Generated_Source\PSoC5/cyfitter_cfg.c **** void cyfitter_cfg(void) 224 .loc 1 304 0 225 00a2 0022 movs r2, #0 - 226 .LBB45: - 227 .LBB44: - 228 .LBB43: + 226 .LBB47: + 227 .LBB46: + 228 .LBB45: 154:.\Generated_Source\PSoC5/cyfitter_cfg.c **** uint32 baseAddr = addr_table[i]; 229 .loc 1 154 0 230 00a4 1859 ldr r0, [r3, r4] @@ -713,14 +718,14 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 1 233 00a6 3034 adds r4, r4, #48 155:.\Generated_Source\PSoC5/cyfitter_cfg.c **** uint8 count = (uint8)baseAddr; 234 .loc 1 155 0 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 13 + + 235 00a8 C6B2 uxtb r6, r0 236 .LVL15: 156:.\Generated_Source\PSoC5/cyfitter_cfg.c **** baseAddr &= 0xFFFFFF00u; 237 .loc 1 156 0 238 00aa 20F0FF07 bic r7, r0, #255 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 13 - - 239 .LVL16: 304:.\Generated_Source\PSoC5/cyfitter_cfg.c **** void cyfitter_cfg(void) 240 .loc 1 304 0 @@ -748,65 +753,65 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 1 304:.\Generated_Source\PSoC5/cyfitter_cfg.c **** void cyfitter_cfg(void) 259 .loc 1 304 0 260 00ce C0B2 uxtb r0, r0 - 261 .LBE43: + 261 .LBE45: 152:.\Generated_Source\PSoC5/cyfitter_cfg.c **** for (i = 0u; i < CY_CFG_BASE_ADDR_COUNT; i++) 262 .loc 1 152 0 263 00d0 302B cmp r3, #48 264 00d2 0144 add r1, r1, r0 265 .LVL18: 266 00d4 E4D1 bne .L11 - 267 .LBE44: - 268 .LBE45: - 401:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CYMEMZERO(ms->address, (uint32)(ms->size)); - 402:.\Generated_Source\PSoC5/cyfitter_cfg.c **** } - 403:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 404:.\Generated_Source\PSoC5/cyfitter_cfg.c **** cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); - 405:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 406:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Enable digital routing */ - 407:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL0_B - 269 .loc 1 407 0 - 270 00d6 304C ldr r4, .L23+40 + 267 .LBE46: + 268 .LBE47: + 406:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CYMEMZERO(ms->address, (uint32)(ms->size)); + 407:.\Generated_Source\PSoC5/cyfitter_cfg.c **** } + 408:.\Generated_Source\PSoC5/cyfitter_cfg.c **** + 409:.\Generated_Source\PSoC5/cyfitter_cfg.c **** cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); + 410:.\Generated_Source\PSoC5/cyfitter_cfg.c **** + 411:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Enable digital routing */ + 412:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL0_B + 269 .loc 1 412 0 + 270 00d6 344C ldr r4, .L23+40 271 00d8 2278 ldrb r2, [r4, #0] @ zero_extendqisi2 272 00da 42F00200 orr r0, r2, #2 273 00de 2070 strb r0, [r4, #0] - 408:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_B - 274 .loc 1 408 0 + 413:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_B + 274 .loc 1 413 0 275 00e0 217C ldrb r1, [r4, #16] @ zero_extendqisi2 276 .LVL19: - 409:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 410:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Enable UDB array */ - 411:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG - 412:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_ - 277 .loc 1 412 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 14 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 14 - 278 00e2 2E48 ldr r0, .L23+44 - 408:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_B - 279 .loc 1 408 0 + 414:.\Generated_Source\PSoC5/cyfitter_cfg.c **** + 415:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Enable UDB array */ + 416:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG + 417:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_ + 277 .loc 1 417 0 + 278 00e2 3248 ldr r0, .L23+44 + 413:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_B + 279 .loc 1 413 0 280 00e4 41F00203 orr r3, r1, #2 - 411:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG - 281 .loc 1 411 0 - 282 00e8 2D49 ldr r1, .L23+48 - 408:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_B - 283 .loc 1 408 0 + 416:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG + 281 .loc 1 416 0 + 282 00e8 3149 ldr r1, .L23+48 + 413:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_B + 283 .loc 1 413 0 284 00ea 2374 strb r3, [r4, #16] - 411:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG - 285 .loc 1 411 0 + 416:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG + 285 .loc 1 416 0 286 00ec 0C78 ldrb r4, [r1, #0] @ zero_extendqisi2 287 00ee 44F04002 orr r2, r4, #64 288 00f2 0A70 strb r2, [r1, #0] - 289 .loc 1 412 0 + 289 .loc 1 417 0 290 00f4 0378 ldrb r3, [r0, #0] @ zero_extendqisi2 75:.\Generated_Source\PSoC5/cyfitter_cfg.c **** (void)memcpy(dest, src, n); 291 .loc 1 75 0 - 292 00f6 2B4A ldr r2, .L23+52 - 293 .loc 1 412 0 + 292 00f6 2F4A ldr r2, .L23+52 + 293 .loc 1 417 0 294 00f8 43F01004 orr r4, r3, #16 75:.\Generated_Source\PSoC5/cyfitter_cfg.c **** (void)memcpy(dest, src, n); 295 .loc 1 75 0 - 296 00fc 2A4B ldr r3, .L23+56 - 297 .loc 1 412 0 + 296 00fc 2E4B ldr r3, .L23+56 + 297 .loc 1 417 0 298 00fe 0470 strb r4, [r0, #0] 299 .LVL20: 75:.\Generated_Source\PSoC5/cyfitter_cfg.c **** (void)memcpy(dest, src, n); @@ -817,7 +822,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 1 304 0106 5460 str r4, [r2, #4] @ unaligned 305 .LVL21: 306 0108 1A46 mov r2, r3 - 307 010a 2848 ldr r0, .L23+60 + 307 010a 2C48 ldr r0, .L23+60 308 010c 52F8084F ldr r4, [r2, #8]! @ unaligned 309 0110 0460 str r4, [r0, #0] @ unaligned 310 0112 5468 ldr r4, [r2, #4] @ unaligned @@ -828,2002 +833,2039 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 1 315 011a 1A46 mov r2, r3 316 011c 52F8124F ldr r4, [r2, #18]! @ unaligned 317 0120 5268 ldr r2, [r2, #4] @ unaligned - 318 0122 40F8AE4C str r4, [r0, #-174] @ unaligned - 319 0126 40F8AA2C str r2, [r0, #-170] @ unaligned + 318 0122 40F8BE4C str r4, [r0, #-190] @ unaligned + 319 0126 40F8BA2C str r2, [r0, #-186] @ unaligned 320 .LVL23: - 321 012a 53F81A0F ldr r0, [r3, #26]! @ unaligned - 322 012e 204A ldr r2, .L23+64 - 323 0130 5B68 ldr r3, [r3, #4] @ unaligned - 324 0132 1060 str r0, [r2, #0] @ unaligned - 325 .LBE36: - 413:.\Generated_Source\PSoC5/cyfitter_cfg.c **** } - 414:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 15 - - - 415:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Perform second pass device configuration. These items must be configured in specific order afte - 416:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT0_DM0), (const void CYCODE *)(BS_IOPINS0_0_VAL), 8u); - 417:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT15_DR), (const void CYCODE *)(BS_IOPINS0_8_VAL), 10u); - 418:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT4_DM0), (const void CYCODE *)(BS_IOPINS0_4_VAL), 8u); - 419:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT6_DM0), (const void CYCODE *)(BS_IOPINS0_6_VAL), 8u); - 420:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 421:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Switch Boost to the precision bandgap reference from its internal reference */ - 422:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_REG8((void CYXDATA *)CYREG_BOOST_CR2, (CY_GET_REG8((void CYXDATA *)CYREG_BOOST_CR2) | 0x08u - 326 .loc 1 422 0 - 327 0134 1F48 ldr r0, .L23+68 - 328 .LBB46: + 321 012a 1A46 mov r2, r3 + 322 012c 52F81A4F ldr r4, [r2, #26]! @ unaligned + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 15 + + + 323 0130 5268 ldr r2, [r2, #4] @ unaligned + 324 0132 40F8AE4C str r4, [r0, #-174] @ unaligned + 325 0136 40F8AA2C str r2, [r0, #-170] @ unaligned + 326 .LVL24: + 327 013a 53F8220F ldr r0, [r3, #34]! @ unaligned + 328 013e 204A ldr r2, .L23+64 + 329 0140 5B68 ldr r3, [r3, #4] @ unaligned + 330 0142 1060 str r0, [r2, #0] @ unaligned + 331 .LBE38: + 418:.\Generated_Source\PSoC5/cyfitter_cfg.c **** } + 419:.\Generated_Source\PSoC5/cyfitter_cfg.c **** + 420:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Perform second pass device configuration. These items must be configured in specific order afte + 421:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT0_DM0), (const void CYCODE *)(BS_IOPINS0_0_VAL), 8u); + 422:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT15_DR), (const void CYCODE *)(BS_IOPINS0_8_VAL), 10u); + 423:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT3_DM0), (const void CYCODE *)(BS_IOPINS0_3_VAL), 8u); + 424:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT4_DM0), (const void CYCODE *)(BS_IOPINS0_4_VAL), 8u); + 425:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT6_DM0), (const void CYCODE *)(BS_IOPINS0_6_VAL), 8u); + 426:.\Generated_Source\PSoC5/cyfitter_cfg.c **** + 427:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Switch Boost to the precision bandgap reference from its internal reference */ + 428:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_REG8((void CYXDATA *)CYREG_BOOST_CR2, (CY_GET_REG8((void CYXDATA *)CYREG_BOOST_CR2) | 0x08u + 332 .loc 1 428 0 + 333 0144 1F48 ldr r0, .L23+68 + 334 .LBB48: 75:.\Generated_Source\PSoC5/cyfitter_cfg.c **** (void)memcpy(dest, src, n); - 329 .loc 1 75 0 - 330 0136 5360 str r3, [r2, #4] @ unaligned - 331 .LBE46: - 332 .loc 1 422 0 - 333 0138 0278 ldrb r2, [r0, #0] @ zero_extendqisi2 - 334 013a 42F00803 orr r3, r2, #8 - 335 013e 0370 strb r3, [r0, #0] - 336 .LBB47: - 337 .LBB48: + 335 .loc 1 75 0 + 336 0146 5360 str r3, [r2, #4] @ unaligned + 337 .LBE48: + 338 .loc 1 428 0 + 339 0148 0278 ldrb r2, [r0, #0] @ zero_extendqisi2 + 340 014a 42F00803 orr r3, r2, #8 + 341 014e 0370 strb r3, [r0, #0] + 342 .LBB49: + 343 .LBB50: 246:.\Generated_Source\PSoC5/cyfitter_cfg.c **** uint8 bg_xover_inl_trim = CY_GET_XTND_REG8((void CYFAR *)(CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM + - 338 .loc 1 246 0 - 339 0140 1D48 ldr r0, .L23+72 + 344 .loc 1 246 0 + 345 0150 1D48 ldr r0, .L23+72 247:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT0), (bg_xover_inl_trim & 0x07u)); - 340 .loc 1 247 0 - 341 0142 1E4A ldr r2, .L23+76 + 346 .loc 1 247 0 + 347 0152 1E4A ldr r2, .L23+76 246:.\Generated_Source\PSoC5/cyfitter_cfg.c **** uint8 bg_xover_inl_trim = CY_GET_XTND_REG8((void CYFAR *)(CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM + - 342 .loc 1 246 0 - 343 0144 0378 ldrb r3, [r0, #0] @ zero_extendqisi2 - 344 .LVL24: + 348 .loc 1 246 0 + 349 0154 0378 ldrb r3, [r0, #0] @ zero_extendqisi2 + 350 .LVL25: 247:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT0), (bg_xover_inl_trim & 0x07u)); - 345 .loc 1 247 0 - 346 0146 03F00700 and r0, r3, #7 + 351 .loc 1 247 0 + 352 0156 03F00700 and r0, r3, #7 248:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT1), ((bg_xover_inl_trim >> 4) & 0x0Fu)); - 347 .loc 1 248 0 - 348 014a 1B09 lsrs r3, r3, #4 - 349 .LVL25: + 353 .loc 1 248 0 + 354 015a 1B09 lsrs r3, r3, #4 + 355 .LVL26: 247:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT0), (bg_xover_inl_trim & 0x07u)); - 350 .loc 1 247 0 - 351 014c 1070 strb r0, [r2, #0] + 356 .loc 1 247 0 + 357 015c 1070 strb r0, [r2, #0] 248:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT1), ((bg_xover_inl_trim >> 4) & 0x0Fu)); - 352 .loc 1 248 0 - 353 014e 5370 strb r3, [r2, #1] + 358 .loc 1 248 0 + 359 015e 5370 strb r3, [r2, #1] 249:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, 0x44u); - 354 .loc 1 249 0 - 355 0150 1B4A ldr r2, .L23+80 - 356 0152 4420 movs r0, #68 - 357 0154 1070 strb r0, [r2, #0] - 358 .LVL26: - 359 .LBE48: - 360 .LBE47: - 361 .LBB49: - 362 .LBB50: + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 16 + + + 360 .loc 1 249 0 + 361 0160 1B4A ldr r2, .L23+80 + 362 0162 4420 movs r0, #68 + 363 0164 1070 strb r0, [r2, #0] + 364 .LVL27: + 365 .LBE50: + 366 .LBE49: + 367 .LBB51: + 368 .LBB52: 68:.\Generated_Source\PSoC5/cyfitter_cfg.c **** (void)memcpy(dest, src, n); - 363 .loc 1 68 0 - 364 0156 1B4A ldr r2, .L23+84 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 16 - - - 365 0158 0B46 mov r3, r1 - 366 015a 0C31 adds r1, r1, #12 - 367 .L12: - 368 015c 53F8040B ldr r0, [r3], #4 @ unaligned - 369 0160 8B42 cmp r3, r1 - 370 0162 42F8040B str r0, [r2], #4 @ unaligned - 371 0166 F9D1 bne .L12 - 372 0168 1988 ldrh r1, [r3, #0] @ unaligned - 373 016a 1180 strh r1, [r2, #0] @ unaligned - 374 016c F8BD pop {r3, r4, r5, r6, r7, pc} - 375 .L24: - 376 016e 00BF .align 2 - 377 .L23: - 378 0170 00480040 .word 1073760256 - 379 0174 0F010049 .word 1224737039 - 380 0178 22420040 .word 1073758754 - 381 017c A1460040 .word 1073759905 - 382 0180 25420040 .word 1073758757 - 383 0184 04400040 .word 1073758212 - 384 0188 06400040 .word 1073758214 - 385 018c E8460040 .word 1073759976 - 386 0190 00000000 .word .LANCHOR0 - 387 0194 30000000 .word .LANCHOR0+48 - 388 0198 03500140 .word 1073827843 - 389 019c C2430040 .word 1073759170 - 390 01a0 A0430040 .word 1073759136 - 391 01a4 02510040 .word 1073762562 - 392 01a8 8C000000 .word .LANCHOR0+140 - 393 01ac F0510040 .word 1073762800 - 394 01b0 62510040 .word 1073762658 - 395 01b4 22430040 .word 1073759010 - 396 01b8 CF010049 .word 1224737231 - 397 01bc 6E580040 .word 1073764462 - 398 01c0 76580040 .word 1073764470 - 399 01c4 B0430040 .word 1073759152 - 400 .LBE50: - 401 .LBE49: - 402 .cfi_endproc - 403 .LFE8: - 404 .size cyfitter_cfg, .-cyfitter_cfg - 405 .section .rodata - 406 .align 2 - 407 .set .LANCHOR0,. + 0 - 408 .type cfg_memset_list.4818, %object - 409 .size cfg_memset_list.4818, 48 - 410 cfg_memset_list.4818: - 411 0000 10510040 .4byte 1073762576 - 412 0004 3000 .2byte 48 - 413 0006 50510040 .4byte 1073762640 - 414 000a 1000 .2byte 16 - 415 000c C0510040 .4byte 1073762752 - 416 0010 1000 .2byte 16 - 417 0012 00000140 .4byte 1073807360 - 418 0016 0010 .2byte 4096 - 419 0018 00140140 .4byte 1073812480 - 420 001c 0008 .2byte 2048 - 421 001e 00400140 .4byte 1073823744 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 17 - - - 422 0022 000A .2byte 2560 - 423 0024 004C0140 .4byte 1073826816 - 424 0028 0002 .2byte 512 - 425 002a 00500140 .4byte 1073827840 - 426 002e 2000 .2byte 32 - 427 .type cy_cfg_addr_table.4812, %object - 428 .size cy_cfg_addr_table.4812, 48 - 429 cy_cfg_addr_table.4812: - 430 0030 01450040 .word 1073759489 - 431 0034 01520040 .word 1073762817 - 432 0038 01170140 .word 1073813249 - 433 003c 01190140 .word 1073813761 - 434 0040 03400140 .word 1073823747 - 435 0044 02410140 .word 1073824002 - 436 0048 02420140 .word 1073824258 - 437 004c 02430140 .word 1073824514 - 438 0050 03470140 .word 1073825539 - 439 0054 03480140 .word 1073825795 - 440 0058 024C0140 .word 1073826818 - 441 005c 01510140 .word 1073828097 - 442 .type cy_cfg_data_table.4813, %object - 443 .size cy_cfg_data_table.4813, 44 - 444 cy_cfg_data_table.4813: - 445 0060 7E .byte 126 - 446 0061 02 .byte 2 - 447 0062 7C .byte 124 - 448 0063 40 .byte 64 - 449 0064 EE .byte -18 - 450 0065 0A .byte 10 - 451 0066 EE .byte -18 - 452 0067 0A .byte 10 - 453 0068 33 .byte 51 - 454 0069 80 .byte -128 - 455 006a 36 .byte 54 - 456 006b 40 .byte 64 - 457 006c CC .byte -52 - 458 006d 30 .byte 48 - 459 006e A6 .byte -90 - 460 006f 40 .byte 64 - 461 0070 A7 .byte -89 - 462 0071 80 .byte -128 - 463 0072 A6 .byte -90 - 464 0073 40 .byte 64 - 465 0074 A7 .byte -89 - 466 0075 80 .byte -128 - 467 0076 A6 .byte -90 - 468 0077 40 .byte 64 - 469 0078 A7 .byte -89 - 470 0079 80 .byte -128 - 471 007a 08 .byte 8 - 472 007b 08 .byte 8 - 473 007c 0F .byte 15 - 474 007d 40 .byte 64 - 475 007e C2 .byte -62 - 476 007f 0C .byte 12 - 477 0080 AE .byte -82 - 478 0081 40 .byte 64 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 18 - - - 479 0082 AF .byte -81 - 480 0083 80 .byte -128 - 481 0084 EE .byte -18 - 482 0085 50 .byte 80 - 483 0086 AC .byte -84 - 484 0087 08 .byte 8 - 485 0088 AF .byte -81 - 486 0089 40 .byte 64 - 487 008a 00 .byte 0 - 488 008b 0A .byte 10 - 489 .type BS_IOPINS0_0_VAL.4808, %object - 490 .size BS_IOPINS0_0_VAL.4808, 8 - 491 BS_IOPINS0_0_VAL.4808: - 492 008c 00 .byte 0 - 493 008d FF .byte -1 - 494 008e FF .byte -1 - 495 008f 00 .byte 0 - 496 0090 00 .byte 0 - 497 0091 00 .byte 0 - 498 0092 00 .byte 0 - 499 0093 00 .byte 0 - 500 .type BS_IOPINS0_8_VAL.4809, %object - 501 .size BS_IOPINS0_8_VAL.4809, 10 - 502 BS_IOPINS0_8_VAL.4809: - 503 0094 00 .byte 0 - 504 0095 00 .byte 0 - 505 0096 00 .byte 0 - 506 0097 00 .byte 0 - 507 0098 00 .byte 0 - 508 0099 00 .byte 0 - 509 009a 00 .byte 0 - 510 009b 00 .byte 0 - 511 009c C0 .byte -64 - 512 009d 00 .byte 0 - 513 .type BS_IOPINS0_4_VAL.4810, %object - 514 .size BS_IOPINS0_4_VAL.4810, 8 - 515 BS_IOPINS0_4_VAL.4810: - 516 009e 00 .byte 0 - 517 009f FC .byte -4 - 518 00a0 FC .byte -4 - 519 00a1 00 .byte 0 - 520 00a2 00 .byte 0 - 521 00a3 00 .byte 0 - 522 00a4 00 .byte 0 - 523 00a5 00 .byte 0 - 524 .type BS_IOPINS0_6_VAL.4811, %object - 525 .size BS_IOPINS0_6_VAL.4811, 8 - 526 BS_IOPINS0_6_VAL.4811: - 527 00a6 00 .byte 0 - 528 00a7 0F .byte 15 - 529 00a8 0F .byte 15 - 530 00a9 00 .byte 0 - 531 00aa 00 .byte 0 - 532 00ab 00 .byte 0 - 533 00ac 00 .byte 0 - 534 00ad 00 .byte 0 - 535 00ae 0000 .text - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 19 - - - 536 .Letext0: - 537 .file 2 "c:\\program files (x86)\\cypress\\psoc creator\\3.0\\psoc creator\\import\\gnu_cs\\arm\\4 - 538 .file 3 "./Generated_Source/PSoC5/cytypes.h" - 539 .file 4 "./Generated_Source/PSoC5/CyLib.h" - 540 .section .debug_info,"",%progbits - 541 .Ldebug_info0: - 542 0000 2E050000 .4byte 0x52e - 543 0004 0200 .2byte 0x2 - 544 0006 00000000 .4byte .Ldebug_abbrev0 - 545 000a 04 .byte 0x4 - 546 000b 01 .uleb128 0x1 - 547 000c 1A020000 .4byte .LASF51 - 548 0010 01 .byte 0x1 - 549 0011 4E010000 .4byte .LASF52 - 550 0015 12010000 .4byte .LASF53 - 551 0019 A0000000 .4byte .Ldebug_ranges0+0xa0 - 552 001d 00000000 .4byte 0 - 553 0021 00000000 .4byte 0 - 554 0025 00000000 .4byte .Ldebug_line0 - 555 0029 02 .uleb128 0x2 - 556 002a 01 .byte 0x1 - 557 002b 06 .byte 0x6 - 558 002c 8F000000 .4byte .LASF0 - 559 0030 02 .uleb128 0x2 - 560 0031 01 .byte 0x1 - 561 0032 08 .byte 0x8 - 562 0033 68020000 .4byte .LASF1 - 563 0037 02 .uleb128 0x2 - 564 0038 02 .byte 0x2 - 565 0039 05 .byte 0x5 - 566 003a 76020000 .4byte .LASF2 - 567 003e 02 .uleb128 0x2 - 568 003f 02 .byte 0x2 - 569 0040 07 .byte 0x7 - 570 0041 95010000 .4byte .LASF3 - 571 0045 03 .uleb128 0x3 - 572 0046 04 .byte 0x4 - 573 0047 05 .byte 0x5 - 574 0048 696E7400 .ascii "int\000" - 575 004c 02 .uleb128 0x2 - 576 004d 04 .byte 0x4 - 577 004e 07 .byte 0x7 - 578 004f 41010000 .4byte .LASF4 - 579 0053 02 .uleb128 0x2 - 580 0054 08 .byte 0x8 - 581 0055 05 .byte 0x5 - 582 0056 81000000 .4byte .LASF5 - 583 005a 02 .uleb128 0x2 - 584 005b 08 .byte 0x8 - 585 005c 07 .byte 0x7 - 586 005d 3C000000 .4byte .LASF6 - 587 0061 02 .uleb128 0x2 - 588 0062 04 .byte 0x4 - 589 0063 05 .byte 0x5 - 590 0064 E5000000 .4byte .LASF7 - 591 0068 02 .uleb128 0x2 - 592 0069 04 .byte 0x4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 20 - - - 593 006a 07 .byte 0x7 - 594 006b C9010000 .4byte .LASF8 - 595 006f 04 .uleb128 0x4 - 596 0070 04 .byte 0x4 - 597 0071 02 .uleb128 0x2 - 598 0072 04 .byte 0x4 - 599 0073 07 .byte 0x7 - 600 0074 76010000 .4byte .LASF9 - 601 0078 02 .uleb128 0x2 - 602 0079 01 .byte 0x1 - 603 007a 08 .byte 0x8 - 604 007b BD020000 .4byte .LASF10 - 605 007f 05 .uleb128 0x5 - 606 0080 16000000 .4byte .LASF11 - 607 0084 02 .byte 0x2 - 608 0085 D5 .byte 0xd5 - 609 0086 4C000000 .4byte 0x4c - 610 008a 05 .uleb128 0x5 - 611 008b F4000000 .4byte .LASF12 - 612 008f 03 .byte 0x3 - 613 0090 5B .byte 0x5b - 614 0091 30000000 .4byte 0x30 - 615 0095 05 .uleb128 0x5 - 616 0096 06000000 .4byte .LASF13 - 617 009a 03 .byte 0x3 - 618 009b 5C .byte 0x5c - 619 009c 3E000000 .4byte 0x3e - 620 00a0 05 .uleb128 0x5 - 621 00a1 0B010000 .4byte .LASF14 - 622 00a5 03 .byte 0x3 - 623 00a6 5D .byte 0x5d - 624 00a7 71000000 .4byte 0x71 - 625 00ab 02 .uleb128 0x2 - 626 00ac 04 .byte 0x4 - 627 00ad 04 .byte 0x4 - 628 00ae 06020000 .4byte .LASF15 - 629 00b2 02 .uleb128 0x2 - 630 00b3 08 .byte 0x8 - 631 00b4 04 .byte 0x4 - 632 00b5 FA000000 .4byte .LASF16 - 633 00b9 05 .uleb128 0x5 - 634 00ba 63020000 .4byte .LASF17 - 635 00be 03 .byte 0x3 - 636 00bf F0 .byte 0xf0 - 637 00c0 C4000000 .4byte 0xc4 - 638 00c4 06 .uleb128 0x6 - 639 00c5 8A000000 .4byte 0x8a - 640 00c9 05 .uleb128 0x5 - 641 00ca EE000000 .4byte .LASF18 - 642 00ce 03 .byte 0x3 - 643 00cf F1 .byte 0xf1 - 644 00d0 D4000000 .4byte 0xd4 - 645 00d4 06 .uleb128 0x6 - 646 00d5 95000000 .4byte 0x95 - 647 00d9 07 .uleb128 0x7 - 648 00da 02 .byte 0x2 - 649 00db 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 21 - - - 650 00dc 7D .byte 0x7d - 651 00dd FE000000 .4byte 0xfe - 652 00e1 08 .uleb128 0x8 - 653 00e2 D8020000 .4byte .LASF19 - 654 00e6 01 .byte 0x1 - 655 00e7 7F .byte 0x7f - 656 00e8 8A000000 .4byte 0x8a - 657 00ec 02 .byte 0x2 - 658 00ed 23 .byte 0x23 - 659 00ee 00 .uleb128 0 - 660 00ef 08 .uleb128 0x8 - 661 00f0 3B010000 .4byte .LASF20 - 662 00f4 01 .byte 0x1 - 663 00f5 80 .byte 0x80 - 664 00f6 8A000000 .4byte 0x8a - 665 00fa 02 .byte 0x2 - 666 00fb 23 .byte 0x23 - 667 00fc 01 .uleb128 0x1 - 668 00fd 00 .byte 0 - 669 00fe 05 .uleb128 0x5 - 670 00ff AA020000 .4byte .LASF21 - 671 0103 01 .byte 0x1 - 672 0104 81 .byte 0x81 - 673 0105 D9000000 .4byte 0xd9 - 674 0109 09 .uleb128 0x9 - 675 010a 1D000000 .4byte .LASF22 - 676 010e 01 .byte 0x1 - 677 010f 69 .byte 0x69 - 678 0110 01 .byte 0x1 - 679 0111 01 .byte 0x1 - 680 0112 22010000 .4byte 0x122 - 681 0116 0A .uleb128 0xa - 682 0117 CA000000 .4byte .LASF24 - 683 011b 01 .byte 0x1 - 684 011c 69 .byte 0x69 - 685 011d 8A000000 .4byte 0x8a - 686 0121 00 .byte 0 - 687 0122 09 .uleb128 0x9 - 688 0123 B9010000 .4byte .LASF23 - 689 0127 01 .byte 0x1 - 690 0128 49 .byte 0x49 - 691 0129 01 .byte 0x1 - 692 012a 01 .byte 0x1 - 693 012b 4F010000 .4byte 0x14f - 694 012f 0A .uleb128 0xa - 695 0130 01020000 .4byte .LASF25 - 696 0134 01 .byte 0x1 - 697 0135 49 .byte 0x49 - 698 0136 6F000000 .4byte 0x6f - 699 013a 0B .uleb128 0xb - 700 013b 73726300 .ascii "src\000" - 701 013f 01 .byte 0x1 - 702 0140 49 .byte 0x49 - 703 0141 4F010000 .4byte 0x14f - 704 0145 0B .uleb128 0xb - 705 0146 6E00 .ascii "n\000" - 706 0148 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 22 - - - 707 0149 49 .byte 0x49 - 708 014a 7F000000 .4byte 0x7f - 709 014e 00 .byte 0 - 710 014f 0C .uleb128 0xc - 711 0150 04 .byte 0x4 - 712 0151 55010000 .4byte 0x155 - 713 0155 0D .uleb128 0xd - 714 0156 09 .uleb128 0x9 - 715 0157 EE020000 .4byte .LASF26 - 716 015b 01 .byte 0x1 - 717 015c 42 .byte 0x42 - 718 015d 01 .byte 0x1 - 719 015e 01 .byte 0x1 - 720 015f 83010000 .4byte 0x183 - 721 0163 0A .uleb128 0xa - 722 0164 01020000 .4byte .LASF25 - 723 0168 01 .byte 0x1 - 724 0169 42 .byte 0x42 - 725 016a 6F000000 .4byte 0x6f - 726 016e 0B .uleb128 0xb - 727 016f 73726300 .ascii "src\000" - 728 0173 01 .byte 0x1 - 729 0174 42 .byte 0x42 - 730 0175 4F010000 .4byte 0x14f - 731 0179 0B .uleb128 0xb - 732 017a 6E00 .ascii "n\000" - 733 017c 01 .byte 0x1 - 734 017d 42 .byte 0x42 - 735 017e 7F000000 .4byte 0x7f - 736 0182 00 .byte 0 - 737 0183 09 .uleb128 0x9 - 738 0184 AD000000 .4byte .LASF27 - 739 0188 01 .byte 0x1 - 740 0189 94 .byte 0x94 - 741 018a 01 .byte 0x1 - 742 018b 01 .byte 0x1 - 743 018c D1010000 .4byte 0x1d1 - 744 0190 0A .uleb128 0xa - 745 0191 53000000 .4byte .LASF28 - 746 0195 01 .byte 0x1 - 747 0196 94 .byte 0x94 - 748 0197 D1010000 .4byte 0x1d1 - 749 019b 0A .uleb128 0xa - 750 019c 31000000 .4byte .LASF29 - 751 01a0 01 .byte 0x1 - 752 01a1 94 .byte 0x94 - 753 01a2 DC010000 .4byte 0x1dc - 754 01a6 0E .uleb128 0xe - 755 01a7 6900 .ascii "i\000" - 756 01a9 01 .byte 0x1 - 757 01aa 97 .byte 0x97 - 758 01ab A0000000 .4byte 0xa0 - 759 01af 0E .uleb128 0xe - 760 01b0 6A00 .ascii "j\000" - 761 01b2 01 .byte 0x1 - 762 01b3 97 .byte 0x97 - 763 01b4 A0000000 .4byte 0xa0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 23 - - - 764 01b8 0F .uleb128 0xf - 765 01b9 10 .uleb128 0x10 - 766 01ba 0D000000 .4byte .LASF30 - 767 01be 01 .byte 0x1 - 768 01bf 9A .byte 0x9a - 769 01c0 A0000000 .4byte 0xa0 - 770 01c4 10 .uleb128 0x10 - 771 01c5 00000000 .4byte .LASF31 - 772 01c9 01 .byte 0x1 - 773 01ca 9B .byte 0x9b - 774 01cb 8A000000 .4byte 0x8a - 775 01cf 00 .byte 0 - 776 01d0 00 .byte 0 - 777 01d1 0C .uleb128 0xc - 778 01d2 04 .byte 0x4 - 779 01d3 D7010000 .4byte 0x1d7 - 780 01d7 11 .uleb128 0x11 - 781 01d8 A0000000 .4byte 0xa0 - 782 01dc 0C .uleb128 0xc - 783 01dd 04 .byte 0x4 - 784 01de E2010000 .4byte 0x1e2 - 785 01e2 11 .uleb128 0x11 - 786 01e3 FE000000 .4byte 0xfe - 787 01e7 12 .uleb128 0x12 - 788 01e8 01 .byte 0x1 - 789 01e9 C2020000 .4byte .LASF38 - 790 01ed 01 .byte 0x1 - 791 01ee 0E01 .2byte 0x10e - 792 01f0 01 .byte 0x1 - 793 01f1 00000000 .4byte .LFB7 - 794 01f5 0C000000 .4byte .LFE7 - 795 01f9 02 .byte 0x2 - 796 01fa 7D .byte 0x7d - 797 01fb 00 .sleb128 0 - 798 01fc 01 .byte 0x1 - 799 01fd 1E020000 .4byte 0x21e - 800 0201 13 .uleb128 0x13 - 801 0202 DF020000 .4byte .LASF54 - 802 0206 01 .byte 0x1 - 803 0207 0E01 .2byte 0x10e - 804 0209 8A000000 .4byte 0x8a - 805 020d 01 .byte 0x1 - 806 020e 50 .byte 0x50 - 807 020f 14 .uleb128 0x14 - 808 0210 32010000 .4byte .LASF40 - 809 0214 01 .byte 0x1 - 810 0215 1001 .2byte 0x110 - 811 0217 8A000000 .4byte 0x8a - 812 021b 01 .byte 0x1 - 813 021c 52 .byte 0x52 - 814 021d 00 .byte 0 - 815 021e 09 .uleb128 0x9 - 816 021f BF000000 .4byte .LASF32 - 817 0223 01 .byte 0x1 - 818 0224 B7 .byte 0xb7 - 819 0225 01 .byte 0x1 - 820 0226 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 24 - - - 821 0227 42020000 .4byte 0x242 - 822 022b 10 .uleb128 0x10 - 823 022c 88010000 .4byte .LASF33 - 824 0230 01 .byte 0x1 - 825 0231 B9 .byte 0xb9 - 826 0232 A0000000 .4byte 0xa0 - 827 0236 10 .uleb128 0x10 - 828 0237 91020000 .4byte .LASF34 - 829 023b 01 .byte 0x1 - 830 023c BA .byte 0xba - 831 023d 8A000000 .4byte 0x8a - 832 0241 00 .byte 0 - 833 0242 09 .uleb128 0x9 - 834 0243 01010000 .4byte .LASF35 - 835 0247 01 .byte 0x1 - 836 0248 3B .byte 0x3b - 837 0249 01 .byte 0x1 - 838 024a 01 .byte 0x1 - 839 024b 62020000 .4byte 0x262 - 840 024f 0B .uleb128 0xb - 841 0250 7300 .ascii "s\000" - 842 0252 01 .byte 0x1 - 843 0253 3B .byte 0x3b - 844 0254 6F000000 .4byte 0x6f - 845 0258 0B .uleb128 0xb - 846 0259 6E00 .ascii "n\000" - 847 025b 01 .byte 0x1 - 848 025c 3B .byte 0x3b - 849 025d 7F000000 .4byte 0x7f - 850 0261 00 .byte 0 - 851 0262 09 .uleb128 0x9 - 852 0263 70000000 .4byte .LASF36 - 853 0267 01 .byte 0x1 - 854 0268 F4 .byte 0xf4 - 855 0269 01 .byte 0x1 - 856 026a 01 .byte 0x1 - 857 026b 7B020000 .4byte 0x27b - 858 026f 10 .uleb128 0x10 - 859 0270 D2010000 .4byte .LASF37 - 860 0274 01 .byte 0x1 - 861 0275 F6 .byte 0xf6 - 862 0276 8A000000 .4byte 0x8a - 863 027a 00 .byte 0 - 864 027b 15 .uleb128 0x15 - 865 027c 01 .byte 0x1 - 866 027d 02030000 .4byte .LASF39 - 867 0281 01 .byte 0x1 - 868 0282 3001 .2byte 0x130 - 869 0284 01 .byte 0x1 - 870 0285 00000000 .4byte .LFB8 - 871 0289 C8010000 .4byte .LFE8 - 872 028d 00000000 .4byte .LLST0 - 873 0291 01 .byte 0x1 - 874 0292 A2040000 .4byte 0x4a2 - 875 0296 14 .uleb128 0x14 - 876 0297 80020000 .4byte .LASF41 - 877 029b 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 25 - - - 878 029c 3301 .2byte 0x133 - 879 029e B2040000 .4byte 0x4b2 - 880 02a2 05 .byte 0x5 - 881 02a3 03 .byte 0x3 - 882 02a4 8C000000 .4byte BS_IOPINS0_0_VAL.4808 - 883 02a8 14 .uleb128 0x14 - 884 02a9 99020000 .4byte .LASF42 - 885 02ad 01 .byte 0x1 - 886 02ae 3701 .2byte 0x137 - 887 02b0 C7040000 .4byte 0x4c7 - 888 02b4 05 .byte 0x5 - 889 02b5 03 .byte 0x3 - 890 02b6 94000000 .4byte BS_IOPINS0_8_VAL.4809 - 891 02ba 14 .uleb128 0x14 - 892 02bb D4000000 .4byte .LASF43 - 893 02bf 01 .byte 0x1 - 894 02c0 3B01 .2byte 0x13b - 895 02c2 CC040000 .4byte 0x4cc - 896 02c6 05 .byte 0x5 - 897 02c7 03 .byte 0x3 - 898 02c8 9E000000 .4byte BS_IOPINS0_4_VAL.4810 - 899 02cc 14 .uleb128 0x14 - 900 02cd A8010000 .4byte .LASF44 - 901 02d1 01 .byte 0x1 - 902 02d2 3F01 .2byte 0x13f - 903 02d4 D1040000 .4byte 0x4d1 - 904 02d8 05 .byte 0x5 - 905 02d9 03 .byte 0x3 - 906 02da A6000000 .4byte BS_IOPINS0_6_VAL.4811 - 907 02de 16 .uleb128 0x16 - 908 02df 1E020000 .4byte 0x21e - 909 02e3 08000000 .4byte .LBB30 - 910 02e7 00000000 .4byte .Ldebug_ranges0+0 - 911 02eb 01 .byte 0x1 - 912 02ec 4B01 .2byte 0x14b - 913 02ee 18030000 .4byte 0x318 - 914 02f2 17 .uleb128 0x17 - 915 02f3 20000000 .4byte .Ldebug_ranges0+0x20 - 916 02f7 18 .uleb128 0x18 - 917 02f8 2B020000 .4byte 0x22b - 918 02fc 19 .uleb128 0x19 - 919 02fd 36020000 .4byte 0x236 - 920 0301 20000000 .4byte .LLST1 - 921 0305 1A .uleb128 0x1a - 922 0306 4A000000 .4byte .LVL3 - 923 030a 00050000 .4byte 0x500 - 924 030e 1B .uleb128 0x1b - 925 030f 01 .byte 0x1 - 926 0310 50 .byte 0x50 - 927 0311 03 .byte 0x3 - 928 0312 0A .byte 0xa - 929 0313 E001 .2byte 0x1e0 - 930 0315 00 .byte 0 - 931 0316 00 .byte 0 - 932 0317 00 .byte 0 - 933 0318 1C .uleb128 0x1c - 934 0319 40000000 .4byte .Ldebug_ranges0+0x40 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 26 - - - 935 031d 50040000 .4byte 0x450 - 936 0321 14 .uleb128 0x14 - 937 0322 9B000000 .4byte .LASF45 - 938 0326 01 .byte 0x1 - 939 0327 5001 .2byte 0x150 - 940 0329 E6040000 .4byte 0x4e6 - 941 032d 05 .byte 0x5 - 942 032e 03 .byte 0x3 - 943 032f 30000000 .4byte cy_cfg_addr_table.4812 - 944 0333 14 .uleb128 0x14 - 945 0334 5E000000 .4byte .LASF46 - 946 0338 01 .byte 0x1 - 947 0339 5F01 .2byte 0x15f - 948 033b FB040000 .4byte 0x4fb - 949 033f 05 .byte 0x5 - 950 0340 03 .byte 0x3 - 951 0341 60000000 .4byte cy_cfg_data_table.4813 - 952 0345 1D .uleb128 0x1d - 953 0346 06 .byte 0x6 - 954 0347 01 .byte 0x1 - 955 0348 7A01 .2byte 0x17a - 956 034a 6D030000 .4byte 0x36d - 957 034e 1E .uleb128 0x1e - 958 034f FA020000 .4byte .LASF47 - 959 0353 01 .byte 0x1 - 960 0354 7B01 .2byte 0x17b - 961 0356 6F000000 .4byte 0x6f - 962 035a 02 .byte 0x2 - 963 035b 23 .byte 0x23 - 964 035c 00 .uleb128 0 - 965 035d 1E .uleb128 0x1e - 966 035e 90010000 .4byte .LASF48 - 967 0362 01 .byte 0x1 - 968 0363 7C01 .2byte 0x17c - 969 0365 95000000 .4byte 0x95 - 970 0369 02 .byte 0x2 - 971 036a 23 .byte 0x23 - 972 036b 04 .uleb128 0x4 - 973 036c 00 .byte 0 - 974 036d 1F .uleb128 0x1f - 975 036e E4010000 .4byte .LASF49 - 976 0372 01 .byte 0x1 - 977 0373 7D01 .2byte 0x17d - 978 0375 45030000 .4byte 0x345 - 979 0379 20 .uleb128 0x20 - 980 037a 6D030000 .4byte 0x36d - 981 037e 89030000 .4byte 0x389 - 982 0382 21 .uleb128 0x21 - 983 0383 68000000 .4byte 0x68 - 984 0387 07 .byte 0x7 - 985 0388 00 .byte 0 - 986 0389 14 .uleb128 0x14 - 987 038a F1010000 .4byte .LASF50 - 988 038e 01 .byte 0x1 - 989 038f 7F01 .2byte 0x17f - 990 0391 9B030000 .4byte 0x39b - 991 0395 05 .byte 0x5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 27 - - - 992 0396 03 .byte 0x3 - 993 0397 00000000 .4byte cfg_memset_list.4818 - 994 039b 11 .uleb128 0x11 - 995 039c 79030000 .4byte 0x379 - 996 03a0 22 .uleb128 0x22 - 997 03a1 6900 .ascii "i\000" - 998 03a3 01 .byte 0x1 - 999 03a4 8B01 .2byte 0x18b - 1000 03a6 8A000000 .4byte 0x8a - 1001 03aa 3E000000 .4byte .LLST2 - 1002 03ae 23 .uleb128 0x23 - 1003 03af 84000000 .4byte .LBB37 - 1004 03b3 98000000 .4byte .LBE37 - 1005 03b7 08040000 .4byte 0x408 - 1006 03bb 22 .uleb128 0x22 - 1007 03bc 6D7300 .ascii "ms\000" - 1008 03bf 01 .byte 0x1 - 1009 03c0 9001 .2byte 0x190 - 1010 03c2 CA030000 .4byte 0x3ca - 1011 03c6 52000000 .4byte .LLST3 - 1012 03ca 0C .uleb128 0xc - 1013 03cb 04 .byte 0x4 - 1014 03cc D0030000 .4byte 0x3d0 - 1015 03d0 11 .uleb128 0x11 - 1016 03d1 6D030000 .4byte 0x36d - 1017 03d5 24 .uleb128 0x24 - 1018 03d6 42020000 .4byte 0x242 - 1019 03da 8C000000 .4byte .LBB38 - 1020 03de 98000000 .4byte .LBE38 - 1021 03e2 01 .byte 0x1 - 1022 03e3 9101 .2byte 0x191 - 1023 03e5 25 .uleb128 0x25 - 1024 03e6 58020000 .4byte 0x258 - 1025 03ea 77000000 .4byte .LLST4 - 1026 03ee 25 .uleb128 0x25 - 1027 03ef 4F020000 .4byte 0x24f - 1028 03f3 AC000000 .4byte .LLST5 - 1029 03f7 1A .uleb128 0x1a - 1030 03f8 98000000 .4byte .LVL12 - 1031 03fc 14050000 .4byte 0x514 - 1032 0400 1B .uleb128 0x1b - 1033 0401 01 .byte 0x1 - 1034 0402 51 .byte 0x51 - 1035 0403 01 .byte 0x1 - 1036 0404 30 .byte 0x30 - 1037 0405 00 .byte 0 - 1038 0406 00 .byte 0 - 1039 0407 00 .byte 0 - 1040 0408 26 .uleb128 0x26 - 1041 0409 83010000 .4byte 0x183 - 1042 040d A0000000 .4byte .LBB40 - 1043 0411 58000000 .4byte .Ldebug_ranges0+0x58 - 1044 0415 01 .byte 0x1 - 1045 0416 9401 .2byte 0x194 - 1046 0418 17 .uleb128 0x17 - 1047 0419 70000000 .4byte .Ldebug_ranges0+0x70 - 1048 041d 18 .uleb128 0x18 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 28 - - - 1049 041e A6010000 .4byte 0x1a6 - 1050 0422 19 .uleb128 0x19 - 1051 0423 AF010000 .4byte 0x1af - 1052 0427 DC000000 .4byte .LLST6 - 1053 042b 27 .uleb128 0x27 - 1054 042c 9B010000 .4byte 0x19b - 1055 0430 27 .uleb128 0x27 - 1056 0431 90010000 .4byte 0x190 - 1057 0435 17 .uleb128 0x17 - 1058 0436 88000000 .4byte .Ldebug_ranges0+0x88 - 1059 043a 19 .uleb128 0x19 - 1060 043b B9010000 .4byte 0x1b9 - 1061 043f EF000000 .4byte .LLST7 - 1062 0443 19 .uleb128 0x19 - 1063 0444 C4010000 .4byte 0x1c4 - 1064 0448 0D010000 .4byte .LLST8 - 1065 044c 00 .byte 0 - 1066 044d 00 .byte 0 - 1067 044e 00 .byte 0 - 1068 044f 00 .byte 0 - 1069 0450 28 .uleb128 0x28 - 1070 0451 62020000 .4byte 0x262 - 1071 0455 40010000 .4byte .LBB47 - 1072 0459 56010000 .4byte .LBE47 - 1073 045d 01 .byte 0x1 - 1074 045e A901 .2byte 0x1a9 - 1075 0460 78040000 .4byte 0x478 - 1076 0464 29 .uleb128 0x29 - 1077 0465 40010000 .4byte .LBB48 - 1078 0469 56010000 .4byte .LBE48 - 1079 046d 19 .uleb128 0x19 - 1080 046e 6F020000 .4byte 0x26f - 1081 0472 20010000 .4byte .LLST9 - 1082 0476 00 .byte 0 - 1083 0477 00 .byte 0 - 1084 0478 24 .uleb128 0x24 - 1085 0479 56010000 .4byte 0x156 - 1086 047d 56010000 .4byte .LBB49 - 1087 0481 C8010000 .4byte .LBE49 - 1088 0485 01 .byte 0x1 - 1089 0486 AC01 .2byte 0x1ac - 1090 0488 2A .uleb128 0x2a - 1091 0489 79010000 .4byte 0x179 - 1092 048d 0E .byte 0xe - 1093 048e 2B .uleb128 0x2b - 1094 048f 6E010000 .4byte 0x16e - 1095 0493 A0430040 .4byte 0x400043a0 - 1096 0497 2B .uleb128 0x2b - 1097 0498 63010000 .4byte 0x163 - 1098 049c B0430040 .4byte 0x400043b0 - 1099 04a0 00 .byte 0 - 1100 04a1 00 .byte 0 - 1101 04a2 20 .uleb128 0x20 - 1102 04a3 8A000000 .4byte 0x8a - 1103 04a7 B2040000 .4byte 0x4b2 - 1104 04ab 21 .uleb128 0x21 - 1105 04ac 68000000 .4byte 0x68 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 29 - - - 1106 04b0 07 .byte 0x7 - 1107 04b1 00 .byte 0 - 1108 04b2 11 .uleb128 0x11 - 1109 04b3 A2040000 .4byte 0x4a2 - 1110 04b7 20 .uleb128 0x20 - 1111 04b8 8A000000 .4byte 0x8a - 1112 04bc C7040000 .4byte 0x4c7 - 1113 04c0 21 .uleb128 0x21 - 1114 04c1 68000000 .4byte 0x68 - 1115 04c5 09 .byte 0x9 - 1116 04c6 00 .byte 0 - 1117 04c7 11 .uleb128 0x11 - 1118 04c8 B7040000 .4byte 0x4b7 - 1119 04cc 11 .uleb128 0x11 - 1120 04cd A2040000 .4byte 0x4a2 - 1121 04d1 11 .uleb128 0x11 - 1122 04d2 A2040000 .4byte 0x4a2 - 1123 04d6 20 .uleb128 0x20 - 1124 04d7 A0000000 .4byte 0xa0 - 1125 04db E6040000 .4byte 0x4e6 - 1126 04df 21 .uleb128 0x21 - 1127 04e0 68000000 .4byte 0x68 - 1128 04e4 0B .byte 0xb - 1129 04e5 00 .byte 0 - 1130 04e6 11 .uleb128 0x11 - 1131 04e7 D6040000 .4byte 0x4d6 - 1132 04eb 20 .uleb128 0x20 - 1133 04ec FE000000 .4byte 0xfe - 1134 04f0 FB040000 .4byte 0x4fb - 1135 04f4 21 .uleb128 0x21 - 1136 04f5 68000000 .4byte 0x68 - 1137 04f9 15 .byte 0x15 - 1138 04fa 00 .byte 0 - 1139 04fb 11 .uleb128 0x11 - 1140 04fc EB040000 .4byte 0x4eb - 1141 0500 2C .uleb128 0x2c - 1142 0501 01 .byte 0x1 - 1143 0502 0C020000 .4byte .LASF55 - 1144 0506 04 .byte 0x4 - 1145 0507 7A .byte 0x7a - 1146 0508 01 .byte 0x1 - 1147 0509 01 .byte 0x1 - 1148 050a 14050000 .4byte 0x514 - 1149 050e 2D .uleb128 0x2d - 1150 050f A0000000 .4byte 0xa0 - 1151 0513 00 .byte 0 - 1152 0514 2E .uleb128 0x2e - 1153 0515 01 .byte 0x1 - 1154 0516 E7020000 .4byte .LASF56 - 1155 051a 01 .byte 0x1 - 1156 051b 6F000000 .4byte 0x6f - 1157 051f 01 .byte 0x1 - 1158 0520 01 .byte 0x1 - 1159 0521 2D .uleb128 0x2d - 1160 0522 6F000000 .4byte 0x6f - 1161 0526 2D .uleb128 0x2d - 1162 0527 45000000 .4byte 0x45 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 30 - - - 1163 052b 2D .uleb128 0x2d - 1164 052c 68000000 .4byte 0x68 - 1165 0530 00 .byte 0 - 1166 0531 00 .byte 0 - 1167 .section .debug_abbrev,"",%progbits - 1168 .Ldebug_abbrev0: - 1169 0000 01 .uleb128 0x1 - 1170 0001 11 .uleb128 0x11 - 1171 0002 01 .byte 0x1 - 1172 0003 25 .uleb128 0x25 - 1173 0004 0E .uleb128 0xe - 1174 0005 13 .uleb128 0x13 - 1175 0006 0B .uleb128 0xb - 1176 0007 03 .uleb128 0x3 - 1177 0008 0E .uleb128 0xe - 1178 0009 1B .uleb128 0x1b - 1179 000a 0E .uleb128 0xe - 1180 000b 55 .uleb128 0x55 - 1181 000c 06 .uleb128 0x6 - 1182 000d 11 .uleb128 0x11 - 1183 000e 01 .uleb128 0x1 - 1184 000f 52 .uleb128 0x52 - 1185 0010 01 .uleb128 0x1 - 1186 0011 10 .uleb128 0x10 - 1187 0012 06 .uleb128 0x6 - 1188 0013 00 .byte 0 - 1189 0014 00 .byte 0 - 1190 0015 02 .uleb128 0x2 - 1191 0016 24 .uleb128 0x24 - 1192 0017 00 .byte 0 - 1193 0018 0B .uleb128 0xb - 1194 0019 0B .uleb128 0xb - 1195 001a 3E .uleb128 0x3e - 1196 001b 0B .uleb128 0xb - 1197 001c 03 .uleb128 0x3 - 1198 001d 0E .uleb128 0xe - 1199 001e 00 .byte 0 - 1200 001f 00 .byte 0 - 1201 0020 03 .uleb128 0x3 - 1202 0021 24 .uleb128 0x24 - 1203 0022 00 .byte 0 - 1204 0023 0B .uleb128 0xb - 1205 0024 0B .uleb128 0xb - 1206 0025 3E .uleb128 0x3e - 1207 0026 0B .uleb128 0xb - 1208 0027 03 .uleb128 0x3 - 1209 0028 08 .uleb128 0x8 - 1210 0029 00 .byte 0 - 1211 002a 00 .byte 0 - 1212 002b 04 .uleb128 0x4 - 1213 002c 0F .uleb128 0xf - 1214 002d 00 .byte 0 - 1215 002e 0B .uleb128 0xb - 1216 002f 0B .uleb128 0xb - 1217 0030 00 .byte 0 - 1218 0031 00 .byte 0 - 1219 0032 05 .uleb128 0x5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 31 - - - 1220 0033 16 .uleb128 0x16 - 1221 0034 00 .byte 0 - 1222 0035 03 .uleb128 0x3 - 1223 0036 0E .uleb128 0xe - 1224 0037 3A .uleb128 0x3a - 1225 0038 0B .uleb128 0xb - 1226 0039 3B .uleb128 0x3b - 1227 003a 0B .uleb128 0xb - 1228 003b 49 .uleb128 0x49 - 1229 003c 13 .uleb128 0x13 - 1230 003d 00 .byte 0 - 1231 003e 00 .byte 0 - 1232 003f 06 .uleb128 0x6 - 1233 0040 35 .uleb128 0x35 - 1234 0041 00 .byte 0 - 1235 0042 49 .uleb128 0x49 - 1236 0043 13 .uleb128 0x13 - 1237 0044 00 .byte 0 - 1238 0045 00 .byte 0 - 1239 0046 07 .uleb128 0x7 - 1240 0047 13 .uleb128 0x13 - 1241 0048 01 .byte 0x1 - 1242 0049 0B .uleb128 0xb - 1243 004a 0B .uleb128 0xb - 1244 004b 3A .uleb128 0x3a - 1245 004c 0B .uleb128 0xb - 1246 004d 3B .uleb128 0x3b - 1247 004e 0B .uleb128 0xb - 1248 004f 01 .uleb128 0x1 - 1249 0050 13 .uleb128 0x13 - 1250 0051 00 .byte 0 - 1251 0052 00 .byte 0 - 1252 0053 08 .uleb128 0x8 - 1253 0054 0D .uleb128 0xd - 1254 0055 00 .byte 0 - 1255 0056 03 .uleb128 0x3 - 1256 0057 0E .uleb128 0xe - 1257 0058 3A .uleb128 0x3a - 1258 0059 0B .uleb128 0xb - 1259 005a 3B .uleb128 0x3b - 1260 005b 0B .uleb128 0xb - 1261 005c 49 .uleb128 0x49 - 1262 005d 13 .uleb128 0x13 - 1263 005e 38 .uleb128 0x38 - 1264 005f 0A .uleb128 0xa - 1265 0060 00 .byte 0 - 1266 0061 00 .byte 0 - 1267 0062 09 .uleb128 0x9 - 1268 0063 2E .uleb128 0x2e - 1269 0064 01 .byte 0x1 - 1270 0065 03 .uleb128 0x3 - 1271 0066 0E .uleb128 0xe - 1272 0067 3A .uleb128 0x3a - 1273 0068 0B .uleb128 0xb - 1274 0069 3B .uleb128 0x3b - 1275 006a 0B .uleb128 0xb - 1276 006b 27 .uleb128 0x27 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 32 - - - 1277 006c 0C .uleb128 0xc - 1278 006d 20 .uleb128 0x20 - 1279 006e 0B .uleb128 0xb - 1280 006f 01 .uleb128 0x1 - 1281 0070 13 .uleb128 0x13 - 1282 0071 00 .byte 0 - 1283 0072 00 .byte 0 - 1284 0073 0A .uleb128 0xa - 1285 0074 05 .uleb128 0x5 - 1286 0075 00 .byte 0 - 1287 0076 03 .uleb128 0x3 - 1288 0077 0E .uleb128 0xe - 1289 0078 3A .uleb128 0x3a - 1290 0079 0B .uleb128 0xb - 1291 007a 3B .uleb128 0x3b - 1292 007b 0B .uleb128 0xb - 1293 007c 49 .uleb128 0x49 - 1294 007d 13 .uleb128 0x13 - 1295 007e 00 .byte 0 - 1296 007f 00 .byte 0 - 1297 0080 0B .uleb128 0xb - 1298 0081 05 .uleb128 0x5 - 1299 0082 00 .byte 0 - 1300 0083 03 .uleb128 0x3 - 1301 0084 08 .uleb128 0x8 - 1302 0085 3A .uleb128 0x3a - 1303 0086 0B .uleb128 0xb - 1304 0087 3B .uleb128 0x3b - 1305 0088 0B .uleb128 0xb - 1306 0089 49 .uleb128 0x49 - 1307 008a 13 .uleb128 0x13 - 1308 008b 00 .byte 0 - 1309 008c 00 .byte 0 - 1310 008d 0C .uleb128 0xc - 1311 008e 0F .uleb128 0xf - 1312 008f 00 .byte 0 - 1313 0090 0B .uleb128 0xb - 1314 0091 0B .uleb128 0xb - 1315 0092 49 .uleb128 0x49 - 1316 0093 13 .uleb128 0x13 - 1317 0094 00 .byte 0 - 1318 0095 00 .byte 0 - 1319 0096 0D .uleb128 0xd - 1320 0097 26 .uleb128 0x26 - 1321 0098 00 .byte 0 - 1322 0099 00 .byte 0 - 1323 009a 00 .byte 0 - 1324 009b 0E .uleb128 0xe - 1325 009c 34 .uleb128 0x34 - 1326 009d 00 .byte 0 - 1327 009e 03 .uleb128 0x3 - 1328 009f 08 .uleb128 0x8 - 1329 00a0 3A .uleb128 0x3a - 1330 00a1 0B .uleb128 0xb - 1331 00a2 3B .uleb128 0x3b - 1332 00a3 0B .uleb128 0xb - 1333 00a4 49 .uleb128 0x49 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 33 - - - 1334 00a5 13 .uleb128 0x13 - 1335 00a6 00 .byte 0 - 1336 00a7 00 .byte 0 - 1337 00a8 0F .uleb128 0xf - 1338 00a9 0B .uleb128 0xb - 1339 00aa 01 .byte 0x1 - 1340 00ab 00 .byte 0 - 1341 00ac 00 .byte 0 - 1342 00ad 10 .uleb128 0x10 - 1343 00ae 34 .uleb128 0x34 - 1344 00af 00 .byte 0 - 1345 00b0 03 .uleb128 0x3 - 1346 00b1 0E .uleb128 0xe - 1347 00b2 3A .uleb128 0x3a - 1348 00b3 0B .uleb128 0xb - 1349 00b4 3B .uleb128 0x3b - 1350 00b5 0B .uleb128 0xb - 1351 00b6 49 .uleb128 0x49 - 1352 00b7 13 .uleb128 0x13 - 1353 00b8 00 .byte 0 - 1354 00b9 00 .byte 0 - 1355 00ba 11 .uleb128 0x11 - 1356 00bb 26 .uleb128 0x26 - 1357 00bc 00 .byte 0 - 1358 00bd 49 .uleb128 0x49 - 1359 00be 13 .uleb128 0x13 - 1360 00bf 00 .byte 0 - 1361 00c0 00 .byte 0 - 1362 00c1 12 .uleb128 0x12 - 1363 00c2 2E .uleb128 0x2e - 1364 00c3 01 .byte 0x1 - 1365 00c4 3F .uleb128 0x3f - 1366 00c5 0C .uleb128 0xc - 1367 00c6 03 .uleb128 0x3 - 1368 00c7 0E .uleb128 0xe - 1369 00c8 3A .uleb128 0x3a - 1370 00c9 0B .uleb128 0xb - 1371 00ca 3B .uleb128 0x3b - 1372 00cb 05 .uleb128 0x5 - 1373 00cc 27 .uleb128 0x27 - 1374 00cd 0C .uleb128 0xc - 1375 00ce 11 .uleb128 0x11 - 1376 00cf 01 .uleb128 0x1 - 1377 00d0 12 .uleb128 0x12 - 1378 00d1 01 .uleb128 0x1 - 1379 00d2 40 .uleb128 0x40 - 1380 00d3 0A .uleb128 0xa - 1381 00d4 9742 .uleb128 0x2117 - 1382 00d6 0C .uleb128 0xc - 1383 00d7 01 .uleb128 0x1 - 1384 00d8 13 .uleb128 0x13 - 1385 00d9 00 .byte 0 - 1386 00da 00 .byte 0 - 1387 00db 13 .uleb128 0x13 - 1388 00dc 05 .uleb128 0x5 - 1389 00dd 00 .byte 0 - 1390 00de 03 .uleb128 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 34 - - - 1391 00df 0E .uleb128 0xe - 1392 00e0 3A .uleb128 0x3a - 1393 00e1 0B .uleb128 0xb - 1394 00e2 3B .uleb128 0x3b - 1395 00e3 05 .uleb128 0x5 - 1396 00e4 49 .uleb128 0x49 - 1397 00e5 13 .uleb128 0x13 - 1398 00e6 02 .uleb128 0x2 - 1399 00e7 0A .uleb128 0xa - 1400 00e8 00 .byte 0 - 1401 00e9 00 .byte 0 - 1402 00ea 14 .uleb128 0x14 - 1403 00eb 34 .uleb128 0x34 - 1404 00ec 00 .byte 0 - 1405 00ed 03 .uleb128 0x3 - 1406 00ee 0E .uleb128 0xe - 1407 00ef 3A .uleb128 0x3a - 1408 00f0 0B .uleb128 0xb - 1409 00f1 3B .uleb128 0x3b - 1410 00f2 05 .uleb128 0x5 - 1411 00f3 49 .uleb128 0x49 - 1412 00f4 13 .uleb128 0x13 - 1413 00f5 02 .uleb128 0x2 - 1414 00f6 0A .uleb128 0xa - 1415 00f7 00 .byte 0 - 1416 00f8 00 .byte 0 - 1417 00f9 15 .uleb128 0x15 - 1418 00fa 2E .uleb128 0x2e - 1419 00fb 01 .byte 0x1 - 1420 00fc 3F .uleb128 0x3f - 1421 00fd 0C .uleb128 0xc - 1422 00fe 03 .uleb128 0x3 - 1423 00ff 0E .uleb128 0xe - 1424 0100 3A .uleb128 0x3a - 1425 0101 0B .uleb128 0xb - 1426 0102 3B .uleb128 0x3b - 1427 0103 05 .uleb128 0x5 - 1428 0104 27 .uleb128 0x27 - 1429 0105 0C .uleb128 0xc - 1430 0106 11 .uleb128 0x11 - 1431 0107 01 .uleb128 0x1 - 1432 0108 12 .uleb128 0x12 - 1433 0109 01 .uleb128 0x1 - 1434 010a 40 .uleb128 0x40 - 1435 010b 06 .uleb128 0x6 - 1436 010c 9742 .uleb128 0x2117 - 1437 010e 0C .uleb128 0xc - 1438 010f 01 .uleb128 0x1 - 1439 0110 13 .uleb128 0x13 - 1440 0111 00 .byte 0 - 1441 0112 00 .byte 0 - 1442 0113 16 .uleb128 0x16 - 1443 0114 1D .uleb128 0x1d - 1444 0115 01 .byte 0x1 - 1445 0116 31 .uleb128 0x31 - 1446 0117 13 .uleb128 0x13 - 1447 0118 52 .uleb128 0x52 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 35 - - - 1448 0119 01 .uleb128 0x1 - 1449 011a 55 .uleb128 0x55 - 1450 011b 06 .uleb128 0x6 - 1451 011c 58 .uleb128 0x58 - 1452 011d 0B .uleb128 0xb - 1453 011e 59 .uleb128 0x59 - 1454 011f 05 .uleb128 0x5 - 1455 0120 01 .uleb128 0x1 - 1456 0121 13 .uleb128 0x13 - 1457 0122 00 .byte 0 - 1458 0123 00 .byte 0 - 1459 0124 17 .uleb128 0x17 - 1460 0125 0B .uleb128 0xb - 1461 0126 01 .byte 0x1 - 1462 0127 55 .uleb128 0x55 - 1463 0128 06 .uleb128 0x6 - 1464 0129 00 .byte 0 - 1465 012a 00 .byte 0 - 1466 012b 18 .uleb128 0x18 - 1467 012c 34 .uleb128 0x34 - 1468 012d 00 .byte 0 - 1469 012e 31 .uleb128 0x31 - 1470 012f 13 .uleb128 0x13 - 1471 0130 00 .byte 0 - 1472 0131 00 .byte 0 - 1473 0132 19 .uleb128 0x19 - 1474 0133 34 .uleb128 0x34 - 1475 0134 00 .byte 0 - 1476 0135 31 .uleb128 0x31 - 1477 0136 13 .uleb128 0x13 - 1478 0137 02 .uleb128 0x2 - 1479 0138 06 .uleb128 0x6 - 1480 0139 00 .byte 0 - 1481 013a 00 .byte 0 - 1482 013b 1A .uleb128 0x1a - 1483 013c 898201 .uleb128 0x4109 - 1484 013f 01 .byte 0x1 - 1485 0140 11 .uleb128 0x11 - 1486 0141 01 .uleb128 0x1 - 1487 0142 31 .uleb128 0x31 - 1488 0143 13 .uleb128 0x13 - 1489 0144 00 .byte 0 - 1490 0145 00 .byte 0 - 1491 0146 1B .uleb128 0x1b - 1492 0147 8A8201 .uleb128 0x410a - 1493 014a 00 .byte 0 - 1494 014b 02 .uleb128 0x2 - 1495 014c 0A .uleb128 0xa - 1496 014d 9142 .uleb128 0x2111 - 1497 014f 0A .uleb128 0xa - 1498 0150 00 .byte 0 - 1499 0151 00 .byte 0 - 1500 0152 1C .uleb128 0x1c - 1501 0153 0B .uleb128 0xb - 1502 0154 01 .byte 0x1 - 1503 0155 55 .uleb128 0x55 - 1504 0156 06 .uleb128 0x6 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 36 - - - 1505 0157 01 .uleb128 0x1 - 1506 0158 13 .uleb128 0x13 - 1507 0159 00 .byte 0 - 1508 015a 00 .byte 0 - 1509 015b 1D .uleb128 0x1d - 1510 015c 13 .uleb128 0x13 - 1511 015d 01 .byte 0x1 - 1512 015e 0B .uleb128 0xb - 1513 015f 0B .uleb128 0xb - 1514 0160 3A .uleb128 0x3a - 1515 0161 0B .uleb128 0xb - 1516 0162 3B .uleb128 0x3b - 1517 0163 05 .uleb128 0x5 - 1518 0164 01 .uleb128 0x1 - 1519 0165 13 .uleb128 0x13 - 1520 0166 00 .byte 0 - 1521 0167 00 .byte 0 - 1522 0168 1E .uleb128 0x1e - 1523 0169 0D .uleb128 0xd - 1524 016a 00 .byte 0 - 1525 016b 03 .uleb128 0x3 - 1526 016c 0E .uleb128 0xe - 1527 016d 3A .uleb128 0x3a - 1528 016e 0B .uleb128 0xb - 1529 016f 3B .uleb128 0x3b - 1530 0170 05 .uleb128 0x5 - 1531 0171 49 .uleb128 0x49 - 1532 0172 13 .uleb128 0x13 - 1533 0173 38 .uleb128 0x38 - 1534 0174 0A .uleb128 0xa - 1535 0175 00 .byte 0 - 1536 0176 00 .byte 0 - 1537 0177 1F .uleb128 0x1f - 1538 0178 16 .uleb128 0x16 - 1539 0179 00 .byte 0 - 1540 017a 03 .uleb128 0x3 - 1541 017b 0E .uleb128 0xe - 1542 017c 3A .uleb128 0x3a - 1543 017d 0B .uleb128 0xb - 1544 017e 3B .uleb128 0x3b - 1545 017f 05 .uleb128 0x5 - 1546 0180 49 .uleb128 0x49 - 1547 0181 13 .uleb128 0x13 - 1548 0182 00 .byte 0 - 1549 0183 00 .byte 0 - 1550 0184 20 .uleb128 0x20 - 1551 0185 01 .uleb128 0x1 - 1552 0186 01 .byte 0x1 - 1553 0187 49 .uleb128 0x49 - 1554 0188 13 .uleb128 0x13 - 1555 0189 01 .uleb128 0x1 - 1556 018a 13 .uleb128 0x13 - 1557 018b 00 .byte 0 - 1558 018c 00 .byte 0 - 1559 018d 21 .uleb128 0x21 - 1560 018e 21 .uleb128 0x21 - 1561 018f 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 37 - - - 1562 0190 49 .uleb128 0x49 - 1563 0191 13 .uleb128 0x13 - 1564 0192 2F .uleb128 0x2f - 1565 0193 0B .uleb128 0xb - 1566 0194 00 .byte 0 - 1567 0195 00 .byte 0 - 1568 0196 22 .uleb128 0x22 - 1569 0197 34 .uleb128 0x34 - 1570 0198 00 .byte 0 - 1571 0199 03 .uleb128 0x3 - 1572 019a 08 .uleb128 0x8 - 1573 019b 3A .uleb128 0x3a - 1574 019c 0B .uleb128 0xb - 1575 019d 3B .uleb128 0x3b - 1576 019e 05 .uleb128 0x5 - 1577 019f 49 .uleb128 0x49 - 1578 01a0 13 .uleb128 0x13 - 1579 01a1 02 .uleb128 0x2 - 1580 01a2 06 .uleb128 0x6 - 1581 01a3 00 .byte 0 - 1582 01a4 00 .byte 0 - 1583 01a5 23 .uleb128 0x23 - 1584 01a6 0B .uleb128 0xb - 1585 01a7 01 .byte 0x1 - 1586 01a8 11 .uleb128 0x11 - 1587 01a9 01 .uleb128 0x1 - 1588 01aa 12 .uleb128 0x12 - 1589 01ab 01 .uleb128 0x1 - 1590 01ac 01 .uleb128 0x1 - 1591 01ad 13 .uleb128 0x13 - 1592 01ae 00 .byte 0 - 1593 01af 00 .byte 0 - 1594 01b0 24 .uleb128 0x24 - 1595 01b1 1D .uleb128 0x1d - 1596 01b2 01 .byte 0x1 - 1597 01b3 31 .uleb128 0x31 - 1598 01b4 13 .uleb128 0x13 - 1599 01b5 11 .uleb128 0x11 - 1600 01b6 01 .uleb128 0x1 - 1601 01b7 12 .uleb128 0x12 - 1602 01b8 01 .uleb128 0x1 - 1603 01b9 58 .uleb128 0x58 - 1604 01ba 0B .uleb128 0xb - 1605 01bb 59 .uleb128 0x59 - 1606 01bc 05 .uleb128 0x5 - 1607 01bd 00 .byte 0 - 1608 01be 00 .byte 0 - 1609 01bf 25 .uleb128 0x25 - 1610 01c0 05 .uleb128 0x5 - 1611 01c1 00 .byte 0 - 1612 01c2 31 .uleb128 0x31 - 1613 01c3 13 .uleb128 0x13 - 1614 01c4 02 .uleb128 0x2 - 1615 01c5 06 .uleb128 0x6 - 1616 01c6 00 .byte 0 - 1617 01c7 00 .byte 0 - 1618 01c8 26 .uleb128 0x26 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 38 - - - 1619 01c9 1D .uleb128 0x1d - 1620 01ca 01 .byte 0x1 - 1621 01cb 31 .uleb128 0x31 - 1622 01cc 13 .uleb128 0x13 - 1623 01cd 52 .uleb128 0x52 - 1624 01ce 01 .uleb128 0x1 - 1625 01cf 55 .uleb128 0x55 - 1626 01d0 06 .uleb128 0x6 - 1627 01d1 58 .uleb128 0x58 - 1628 01d2 0B .uleb128 0xb - 1629 01d3 59 .uleb128 0x59 - 1630 01d4 05 .uleb128 0x5 - 1631 01d5 00 .byte 0 - 1632 01d6 00 .byte 0 - 1633 01d7 27 .uleb128 0x27 - 1634 01d8 05 .uleb128 0x5 - 1635 01d9 00 .byte 0 - 1636 01da 31 .uleb128 0x31 - 1637 01db 13 .uleb128 0x13 - 1638 01dc 00 .byte 0 - 1639 01dd 00 .byte 0 - 1640 01de 28 .uleb128 0x28 - 1641 01df 1D .uleb128 0x1d - 1642 01e0 01 .byte 0x1 - 1643 01e1 31 .uleb128 0x31 - 1644 01e2 13 .uleb128 0x13 - 1645 01e3 11 .uleb128 0x11 - 1646 01e4 01 .uleb128 0x1 - 1647 01e5 12 .uleb128 0x12 - 1648 01e6 01 .uleb128 0x1 - 1649 01e7 58 .uleb128 0x58 - 1650 01e8 0B .uleb128 0xb - 1651 01e9 59 .uleb128 0x59 - 1652 01ea 05 .uleb128 0x5 - 1653 01eb 01 .uleb128 0x1 - 1654 01ec 13 .uleb128 0x13 - 1655 01ed 00 .byte 0 - 1656 01ee 00 .byte 0 - 1657 01ef 29 .uleb128 0x29 - 1658 01f0 0B .uleb128 0xb - 1659 01f1 01 .byte 0x1 - 1660 01f2 11 .uleb128 0x11 - 1661 01f3 01 .uleb128 0x1 - 1662 01f4 12 .uleb128 0x12 - 1663 01f5 01 .uleb128 0x1 - 1664 01f6 00 .byte 0 - 1665 01f7 00 .byte 0 - 1666 01f8 2A .uleb128 0x2a - 1667 01f9 05 .uleb128 0x5 - 1668 01fa 00 .byte 0 - 1669 01fb 31 .uleb128 0x31 - 1670 01fc 13 .uleb128 0x13 - 1671 01fd 1C .uleb128 0x1c - 1672 01fe 0B .uleb128 0xb - 1673 01ff 00 .byte 0 - 1674 0200 00 .byte 0 - 1675 0201 2B .uleb128 0x2b - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 39 - - - 1676 0202 05 .uleb128 0x5 - 1677 0203 00 .byte 0 - 1678 0204 31 .uleb128 0x31 - 1679 0205 13 .uleb128 0x13 - 1680 0206 1C .uleb128 0x1c - 1681 0207 06 .uleb128 0x6 - 1682 0208 00 .byte 0 - 1683 0209 00 .byte 0 - 1684 020a 2C .uleb128 0x2c - 1685 020b 2E .uleb128 0x2e - 1686 020c 01 .byte 0x1 - 1687 020d 3F .uleb128 0x3f - 1688 020e 0C .uleb128 0xc - 1689 020f 03 .uleb128 0x3 - 1690 0210 0E .uleb128 0xe - 1691 0211 3A .uleb128 0x3a - 1692 0212 0B .uleb128 0xb - 1693 0213 3B .uleb128 0x3b - 1694 0214 0B .uleb128 0xb - 1695 0215 27 .uleb128 0x27 - 1696 0216 0C .uleb128 0xc - 1697 0217 3C .uleb128 0x3c - 1698 0218 0C .uleb128 0xc - 1699 0219 01 .uleb128 0x1 - 1700 021a 13 .uleb128 0x13 - 1701 021b 00 .byte 0 - 1702 021c 00 .byte 0 - 1703 021d 2D .uleb128 0x2d - 1704 021e 05 .uleb128 0x5 - 1705 021f 00 .byte 0 - 1706 0220 49 .uleb128 0x49 - 1707 0221 13 .uleb128 0x13 - 1708 0222 00 .byte 0 - 1709 0223 00 .byte 0 - 1710 0224 2E .uleb128 0x2e - 1711 0225 2E .uleb128 0x2e - 1712 0226 01 .byte 0x1 - 1713 0227 3F .uleb128 0x3f - 1714 0228 0C .uleb128 0xc - 1715 0229 03 .uleb128 0x3 - 1716 022a 0E .uleb128 0xe - 1717 022b 27 .uleb128 0x27 - 1718 022c 0C .uleb128 0xc - 1719 022d 49 .uleb128 0x49 - 1720 022e 13 .uleb128 0x13 - 1721 022f 34 .uleb128 0x34 - 1722 0230 0C .uleb128 0xc - 1723 0231 3C .uleb128 0x3c - 1724 0232 0C .uleb128 0xc - 1725 0233 00 .byte 0 - 1726 0234 00 .byte 0 - 1727 0235 00 .byte 0 - 1728 .section .debug_loc,"",%progbits - 1729 .Ldebug_loc0: - 1730 .LLST0: - 1731 0000 00000000 .4byte .LFB8 - 1732 0004 02000000 .4byte .LCFI0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 40 - - - 1733 0008 0200 .2byte 0x2 - 1734 000a 7D .byte 0x7d - 1735 000b 00 .sleb128 0 - 1736 000c 02000000 .4byte .LCFI0 - 1737 0010 C8010000 .4byte .LFE8 - 1738 0014 0200 .2byte 0x2 - 1739 0016 7D .byte 0x7d - 1740 0017 18 .sleb128 24 - 1741 0018 00000000 .4byte 0 - 1742 001c 00000000 .4byte 0 - 1743 .LLST1: - 1744 0020 50000000 .4byte .LVL4 - 1745 0024 68000000 .4byte .LVL5 - 1746 0028 0100 .2byte 0x1 - 1747 002a 54 .byte 0x54 - 1748 002b 82000000 .4byte .LVL7 - 1749 002f 84000000 .4byte .LVL8 - 1750 0033 0100 .2byte 0x1 - 1751 0035 54 .byte 0x54 - 1752 0036 00000000 .4byte 0 - 1753 003a 00000000 .4byte 0 - 1754 .LLST2: - 1755 003e 80000000 .4byte .LVL6 - 1756 0042 82000000 .4byte .LVL7 - 1757 0046 0200 .2byte 0x2 - 1758 0048 30 .byte 0x30 - 1759 0049 9F .byte 0x9f - 1760 004a 00000000 .4byte 0 - 1761 004e 00000000 .4byte 0 - 1762 .LLST3: - 1763 0052 8C000000 .4byte .LVL9 - 1764 0056 94000000 .4byte .LVL11 - 1765 005a 0100 .2byte 0x1 - 1766 005c 52 .byte 0x52 - 1767 005d 94000000 .4byte .LVL11 - 1768 0061 A0000000 .4byte .LVL13 - 1769 0065 0800 .2byte 0x8 - 1770 0067 76 .byte 0x76 - 1771 0068 7F .sleb128 -1 - 1772 0069 36 .byte 0x36 - 1773 006a 1E .byte 0x1e - 1774 006b 77 .byte 0x77 - 1775 006c 00 .sleb128 0 - 1776 006d 22 .byte 0x22 - 1777 006e 9F .byte 0x9f - 1778 006f 00000000 .4byte 0 - 1779 0073 00000000 .4byte 0 - 1780 .LLST4: - 1781 0077 8C000000 .4byte .LVL9 - 1782 007b 94000000 .4byte .LVL11 - 1783 007f 0900 .2byte 0x9 - 1784 0081 72 .byte 0x72 - 1785 0082 04 .sleb128 4 - 1786 0083 94 .byte 0x94 - 1787 0084 02 .byte 0x2 - 1788 0085 0A .byte 0xa - 1789 0086 FFFF .2byte 0xffff - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 41 - - - 1790 0088 1A .byte 0x1a - 1791 0089 9F .byte 0x9f - 1792 008a 94000000 .4byte .LVL11 - 1793 008e 97000000 .4byte .LVL12-1 - 1794 0092 1000 .2byte 0x10 - 1795 0094 76 .byte 0x76 - 1796 0095 7F .sleb128 -1 - 1797 0096 36 .byte 0x36 - 1798 0097 1E .byte 0x1e - 1799 0098 77 .byte 0x77 - 1800 0099 00 .sleb128 0 - 1801 009a 22 .byte 0x22 - 1802 009b 23 .byte 0x23 - 1803 009c 04 .uleb128 0x4 - 1804 009d 94 .byte 0x94 - 1805 009e 02 .byte 0x2 - 1806 009f 0A .byte 0xa - 1807 00a0 FFFF .2byte 0xffff - 1808 00a2 1A .byte 0x1a - 1809 00a3 9F .byte 0x9f - 1810 00a4 00000000 .4byte 0 - 1811 00a8 00000000 .4byte 0 - 1812 .LLST5: - 1813 00ac 8C000000 .4byte .LVL9 - 1814 00b0 92000000 .4byte .LVL10 - 1815 00b4 0A00 .2byte 0xa - 1816 00b6 76 .byte 0x76 - 1817 00b7 00 .sleb128 0 - 1818 00b8 36 .byte 0x36 - 1819 00b9 1E .byte 0x1e - 1820 00ba 03 .byte 0x3 - 1821 00bb 00000000 .4byte .LANCHOR0 - 1822 00bf 22 .byte 0x22 - 1823 00c0 92000000 .4byte .LVL10 - 1824 00c4 97000000 .4byte .LVL12-1 - 1825 00c8 0A00 .2byte 0xa - 1826 00ca 76 .byte 0x76 - 1827 00cb 7F .sleb128 -1 - 1828 00cc 36 .byte 0x36 - 1829 00cd 1E .byte 0x1e - 1830 00ce 03 .byte 0x3 - 1831 00cf 00000000 .4byte .LANCHOR0 - 1832 00d3 22 .byte 0x22 - 1833 00d4 00000000 .4byte 0 - 1834 00d8 00000000 .4byte 0 - 1835 .LLST6: - 1836 00dc D4000000 .4byte .LVL18 - 1837 00e0 E2000000 .4byte .LVL19 - 1838 00e4 0100 .2byte 0x1 - 1839 00e6 51 .byte 0x51 - 1840 00e7 00000000 .4byte 0 - 1841 00eb 00000000 .4byte 0 - 1842 .LLST7: - 1843 00ef A6000000 .4byte .LVL14 - 1844 00f3 AE000000 .4byte .LVL16 - 1845 00f7 0100 .2byte 0x1 - 1846 00f9 50 .byte 0x50 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 42 - - - 1847 00fa AE000000 .4byte .LVL16 - 1848 00fe C8010000 .4byte .LFE8 - 1849 0102 0100 .2byte 0x1 - 1850 0104 57 .byte 0x57 - 1851 0105 00000000 .4byte 0 - 1852 0109 00000000 .4byte 0 - 1853 .LLST8: - 1854 010d AA000000 .4byte .LVL15 - 1855 0111 B2000000 .4byte .LVL17 - 1856 0115 0100 .2byte 0x1 - 1857 0117 50 .byte 0x50 - 1858 0118 00000000 .4byte 0 - 1859 011c 00000000 .4byte 0 - 1860 .LLST9: - 1861 0120 46010000 .4byte .LVL24 - 1862 0124 4C010000 .4byte .LVL25 - 1863 0128 0100 .2byte 0x1 - 1864 012a 53 .byte 0x53 - 1865 012b 00000000 .4byte 0 - 1866 012f 00000000 .4byte 0 - 1867 .section .debug_aranges,"",%progbits - 1868 0000 24000000 .4byte 0x24 - 1869 0004 0200 .2byte 0x2 - 1870 0006 00000000 .4byte .Ldebug_info0 - 1871 000a 04 .byte 0x4 - 1872 000b 00 .byte 0 - 1873 000c 0000 .2byte 0 - 1874 000e 0000 .2byte 0 - 1875 0010 00000000 .4byte .LFB7 - 1876 0014 0C000000 .4byte .LFE7-.LFB7 - 1877 0018 00000000 .4byte .LFB8 - 1878 001c C8010000 .4byte .LFE8-.LFB8 - 1879 0020 00000000 .4byte 0 - 1880 0024 00000000 .4byte 0 - 1881 .section .debug_ranges,"",%progbits - 1882 .Ldebug_ranges0: - 1883 0000 08000000 .4byte .LBB30 - 1884 0004 16000000 .4byte .LBE30 - 1885 0008 18000000 .4byte .LBB34 - 1886 000c 60000000 .4byte .LBE34 - 1887 0010 62000000 .4byte .LBB35 - 1888 0014 78000000 .4byte .LBE35 - 1889 0018 00000000 .4byte 0 - 1890 001c 00000000 .4byte 0 - 1891 0020 08000000 .4byte .LBB31 - 1892 0024 16000000 .4byte .LBE31 - 1893 0028 18000000 .4byte .LBB32 - 1894 002c 60000000 .4byte .LBE32 - 1895 0030 62000000 .4byte .LBB33 - 1896 0034 78000000 .4byte .LBE33 - 1897 0038 00000000 .4byte 0 - 1898 003c 00000000 .4byte 0 - 1899 0040 84000000 .4byte .LBB36 - 1900 0044 34010000 .4byte .LBE36 - 1901 0048 36010000 .4byte .LBB46 - 1902 004c 38010000 .4byte .LBE46 - 1903 0050 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 43 - - - 1904 0054 00000000 .4byte 0 - 1905 0058 A0000000 .4byte .LBB40 - 1906 005c A2000000 .4byte .LBE40 - 1907 0060 A4000000 .4byte .LBB45 - 1908 0064 D6000000 .4byte .LBE45 - 1909 0068 00000000 .4byte 0 - 1910 006c 00000000 .4byte 0 - 1911 0070 A0000000 .4byte .LBB41 - 1912 0074 A2000000 .4byte .LBE41 - 1913 0078 A4000000 .4byte .LBB44 - 1914 007c D6000000 .4byte .LBE44 - 1915 0080 00000000 .4byte 0 - 1916 0084 00000000 .4byte 0 - 1917 0088 A0000000 .4byte .LBB42 - 1918 008c A2000000 .4byte .LBE42 - 1919 0090 A4000000 .4byte .LBB43 - 1920 0094 D0000000 .4byte .LBE43 - 1921 0098 00000000 .4byte 0 - 1922 009c 00000000 .4byte 0 - 1923 00a0 00000000 .4byte .LFB7 - 1924 00a4 0C000000 .4byte .LFE7 - 1925 00a8 00000000 .4byte .LFB8 - 1926 00ac C8010000 .4byte .LFE8 - 1927 00b0 00000000 .4byte 0 - 1928 00b4 00000000 .4byte 0 - 1929 .section .debug_line,"",%progbits - 1930 .Ldebug_line0: - 1931 0000 D1010000 .section .debug_str,"MS",%progbits,1 - 1931 0200E200 - 1931 00000201 - 1931 FB0E0D00 - 1931 01010101 - 1932 .LASF31: - 1933 0000 636F756E .ascii "count\000" - 1933 7400 - 1934 .LASF13: - 1935 0006 75696E74 .ascii "uint16\000" - 1935 313600 - 1936 .LASF30: - 1937 000d 62617365 .ascii "baseAddr\000" - 1937 41646472 - 1937 00 - 1938 .LASF11: - 1939 0016 73697A65 .ascii "size_t\000" - 1939 5F7400 - 1940 .LASF22: - 1941 001d 4379436C .ascii "CyClockStartupError\000" - 1941 6F636B53 - 1941 74617274 - 1941 75704572 - 1941 726F7200 - 1942 .LASF29: - 1943 0031 64617461 .ascii "data_table\000" - 1943 5F746162 - 1943 6C6500 - 1944 .LASF6: - 1945 003c 6C6F6E67 .ascii "long long unsigned int\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 44 - - - 1945 206C6F6E - 1945 6720756E - 1945 7369676E - 1945 65642069 - 1946 .LASF28: - 1947 0053 61646472 .ascii "addr_table\000" - 1947 5F746162 - 1947 6C6500 - 1948 .LASF46: - 1949 005e 63795F63 .ascii "cy_cfg_data_table\000" - 1949 66675F64 - 1949 6174615F - 1949 7461626C - 1949 6500 - 1950 .LASF36: - 1951 0070 416E616C .ascii "AnalogSetDefault\000" - 1951 6F675365 - 1951 74446566 - 1951 61756C74 - 1951 00 - 1952 .LASF5: - 1953 0081 6C6F6E67 .ascii "long long int\000" - 1953 206C6F6E - 1953 6720696E - 1953 7400 - 1954 .LASF0: - 1955 008f 7369676E .ascii "signed char\000" - 1955 65642063 - 1955 68617200 - 1956 .LASF45: - 1957 009b 63795F63 .ascii "cy_cfg_addr_table\000" - 1957 66675F61 - 1957 6464725F - 1957 7461626C - 1957 6500 - 1958 .LASF27: - 1959 00ad 6366675F .ascii "cfg_write_bytes32\000" - 1959 77726974 - 1959 655F6279 - 1959 74657333 - 1959 3200 - 1960 .LASF32: - 1961 00bf 436C6F63 .ascii "ClockSetup\000" - 1961 6B536574 - 1961 757000 - 1962 .LASF24: - 1963 00ca 6572726F .ascii "errorCode\000" - 1963 72436F64 - 1963 6500 - 1964 .LASF43: - 1965 00d4 42535F49 .ascii "BS_IOPINS0_4_VAL\000" - 1965 4F50494E - 1965 53305F34 - 1965 5F56414C - 1965 00 - 1966 .LASF7: - 1967 00e5 6C6F6E67 .ascii "long int\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 45 - - - 1967 20696E74 - 1967 00 - 1968 .LASF18: - 1969 00ee 72656731 .ascii "reg16\000" - 1969 3600 - 1970 .LASF12: - 1971 00f4 75696E74 .ascii "uint8\000" - 1971 3800 - 1972 .LASF16: - 1973 00fa 646F7562 .ascii "double\000" - 1973 6C6500 - 1974 .LASF35: - 1975 0101 43594D45 .ascii "CYMEMZERO\000" - 1975 4D5A4552 - 1975 4F00 - 1976 .LASF14: - 1977 010b 75696E74 .ascii "uint32\000" - 1977 333200 - 1978 .LASF53: - 1979 0112 573A5C53 .ascii "W:\\SCSI2SD\\USB_Bootloader.cydsn\000" - 1979 43534932 - 1979 53445C55 - 1979 53425F42 - 1979 6F6F746C - 1980 .LASF40: - 1981 0132 72656756 .ascii "regValue\000" - 1981 616C7565 - 1981 00 - 1982 .LASF20: - 1983 013b 76616C75 .ascii "value\000" - 1983 6500 - 1984 .LASF4: - 1985 0141 756E7369 .ascii "unsigned int\000" - 1985 676E6564 - 1985 20696E74 - 1985 00 - 1986 .LASF52: - 1987 014e 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\cyfitter_cfg.c\000" - 1987 6E657261 - 1987 7465645F - 1987 536F7572 - 1987 63655C50 - 1988 .LASF9: - 1989 0176 6C6F6E67 .ascii "long unsigned int\000" - 1989 20756E73 - 1989 69676E65 - 1989 6420696E - 1989 7400 - 1990 .LASF33: - 1991 0188 74696D65 .ascii "timeout\000" - 1991 6F757400 - 1992 .LASF48: - 1993 0190 73697A65 .ascii "size\000" - 1993 00 - 1994 .LASF3: - 1995 0195 73686F72 .ascii "short unsigned int\000" - 1995 7420756E - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 46 - - - 1995 7369676E - 1995 65642069 - 1995 6E7400 - 1996 .LASF44: - 1997 01a8 42535F49 .ascii "BS_IOPINS0_6_VAL\000" - 1997 4F50494E - 1997 53305F36 - 1997 5F56414C - 1997 00 - 1998 .LASF23: - 1999 01b9 4359434F .ascii "CYCONFIGCPYCODE\000" - 1999 4E464947 - 1999 43505943 - 1999 4F444500 - 2000 .LASF8: - 2001 01c9 73697A65 .ascii "sizetype\000" - 2001 74797065 - 2001 00 - 2002 .LASF37: - 2003 01d2 62675F78 .ascii "bg_xover_inl_trim\000" - 2003 6F766572 - 2003 5F696E6C - 2003 5F747269 - 2003 6D00 - 2004 .LASF49: - 2005 01e4 6366675F .ascii "cfg_memset_t\000" - 2005 6D656D73 - 2005 65745F74 - 2005 00 - 2006 .LASF50: - 2007 01f1 6366675F .ascii "cfg_memset_list\000" - 2007 6D656D73 - 2007 65745F6C - 2007 69737400 - 2008 .LASF25: - 2009 0201 64657374 .ascii "dest\000" - 2009 00 - 2010 .LASF15: - 2011 0206 666C6F61 .ascii "float\000" - 2011 7400 - 2012 .LASF55: - 2013 020c 43794465 .ascii "CyDelayCycles\000" - 2013 6C617943 - 2013 79636C65 - 2013 7300 - 2014 .LASF51: - 2015 021a 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 2015 4320342E - 2015 372E3320 - 2015 32303133 - 2015 30333132 - 2016 024d 616E6368 .ascii "anch revision 196615]\000" - 2016 20726576 - 2016 6973696F - 2016 6E203139 - 2016 36363135 - 2017 .LASF17: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 47 - - - 2018 0263 72656738 .ascii "reg8\000" - 2018 00 - 2019 .LASF1: - 2020 0268 756E7369 .ascii "unsigned char\000" - 2020 676E6564 - 2020 20636861 - 2020 7200 - 2021 .LASF2: - 2022 0276 73686F72 .ascii "short int\000" - 2022 7420696E - 2022 7400 - 2023 .LASF41: - 2024 0280 42535F49 .ascii "BS_IOPINS0_0_VAL\000" + 369 .loc 1 68 0 + 370 0166 1B4A ldr r2, .L23+84 + 371 0168 0B46 mov r3, r1 + 372 016a 0C31 adds r1, r1, #12 + 373 .L12: + 374 016c 53F8040B ldr r0, [r3], #4 @ unaligned + 375 0170 8B42 cmp r3, r1 + 376 0172 42F8040B str r0, [r2], #4 @ unaligned + 377 0176 F9D1 bne .L12 + 378 0178 1988 ldrh r1, [r3, #0] @ unaligned + 379 017a 1180 strh r1, [r2, #0] @ unaligned + 380 017c F8BD pop {r3, r4, r5, r6, r7, pc} + 381 .L24: + 382 017e 00BF .align 2 + 383 .L23: + 384 0180 00480040 .word 1073760256 + 385 0184 0F010049 .word 1224737039 + 386 0188 22420040 .word 1073758754 + 387 018c A1460040 .word 1073759905 + 388 0190 25420040 .word 1073758757 + 389 0194 04400040 .word 1073758212 + 390 0198 06400040 .word 1073758214 + 391 019c E8460040 .word 1073759976 + 392 01a0 00000000 .word .LANCHOR0 + 393 01a4 30000000 .word .LANCHOR0+48 + 394 01a8 03500140 .word 1073827843 + 395 01ac C2430040 .word 1073759170 + 396 01b0 A0430040 .word 1073759136 + 397 01b4 02510040 .word 1073762562 + 398 01b8 8E000000 .word .LANCHOR0+142 + 399 01bc F0510040 .word 1073762800 + 400 01c0 62510040 .word 1073762658 + 401 01c4 22430040 .word 1073759010 + 402 01c8 CF010049 .word 1224737231 + 403 01cc 6E580040 .word 1073764462 + 404 01d0 76580040 .word 1073764470 + 405 01d4 B0430040 .word 1073759152 + 406 .LBE52: + 407 .LBE51: + 408 .cfi_endproc + 409 .LFE8: + 410 .size cyfitter_cfg, .-cyfitter_cfg + 411 .section .rodata + 412 .align 2 + 413 .set .LANCHOR0,. + 0 + 414 .type cfg_memset_list.4819, %object + 415 .size cfg_memset_list.4819, 48 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 17 + + + 416 cfg_memset_list.4819: + 417 0000 10510040 .4byte 1073762576 + 418 0004 2000 .2byte 32 + 419 0006 50510040 .4byte 1073762640 + 420 000a 1000 .2byte 16 + 421 000c C0510040 .4byte 1073762752 + 422 0010 1000 .2byte 16 + 423 0012 00000140 .4byte 1073807360 + 424 0016 0010 .2byte 4096 + 425 0018 00140140 .4byte 1073812480 + 426 001c 0008 .2byte 2048 + 427 001e 00400140 .4byte 1073823744 + 428 0022 000A .2byte 2560 + 429 0024 004C0140 .4byte 1073826816 + 430 0028 0002 .2byte 512 + 431 002a 00500140 .4byte 1073827840 + 432 002e 2000 .2byte 32 + 433 .type cy_cfg_addr_table.4813, %object + 434 .size cy_cfg_addr_table.4813, 48 + 435 cy_cfg_addr_table.4813: + 436 0030 01450040 .word 1073759489 + 437 0034 02520040 .word 1073762818 + 438 0038 01170140 .word 1073813249 + 439 003c 01190140 .word 1073813761 + 440 0040 03400140 .word 1073823747 + 441 0044 02410140 .word 1073824002 + 442 0048 02420140 .word 1073824258 + 443 004c 02430140 .word 1073824514 + 444 0050 03470140 .word 1073825539 + 445 0054 03480140 .word 1073825795 + 446 0058 024C0140 .word 1073826818 + 447 005c 01510140 .word 1073828097 + 448 .type cy_cfg_data_table.4814, %object + 449 .size cy_cfg_data_table.4814, 46 + 450 cy_cfg_data_table.4814: + 451 0060 7E .byte 126 + 452 0061 02 .byte 2 + 453 0062 1C .byte 28 + 454 0063 3E .byte 62 + 455 0064 7C .byte 124 + 456 0065 40 .byte 64 + 457 0066 EE .byte -18 + 458 0067 0A .byte 10 + 459 0068 EE .byte -18 + 460 0069 0A .byte 10 + 461 006a 33 .byte 51 + 462 006b 80 .byte -128 + 463 006c 36 .byte 54 + 464 006d 40 .byte 64 + 465 006e CC .byte -52 + 466 006f 30 .byte 48 + 467 0070 A6 .byte -90 + 468 0071 40 .byte 64 + 469 0072 A7 .byte -89 + 470 0073 80 .byte -128 + 471 0074 A6 .byte -90 + 472 0075 40 .byte 64 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 18 + + + 473 0076 A7 .byte -89 + 474 0077 80 .byte -128 + 475 0078 A6 .byte -90 + 476 0079 40 .byte 64 + 477 007a A7 .byte -89 + 478 007b 80 .byte -128 + 479 007c 08 .byte 8 + 480 007d 08 .byte 8 + 481 007e 0F .byte 15 + 482 007f 40 .byte 64 + 483 0080 C2 .byte -62 + 484 0081 0C .byte 12 + 485 0082 AE .byte -82 + 486 0083 40 .byte 64 + 487 0084 AF .byte -81 + 488 0085 80 .byte -128 + 489 0086 EE .byte -18 + 490 0087 50 .byte 80 + 491 0088 AC .byte -84 + 492 0089 08 .byte 8 + 493 008a AF .byte -81 + 494 008b 40 .byte 64 + 495 008c 00 .byte 0 + 496 008d 0A .byte 10 + 497 .type BS_IOPINS0_0_VAL.4808, %object + 498 .size BS_IOPINS0_0_VAL.4808, 8 + 499 BS_IOPINS0_0_VAL.4808: + 500 008e 00 .byte 0 + 501 008f FF .byte -1 + 502 0090 FF .byte -1 + 503 0091 00 .byte 0 + 504 0092 00 .byte 0 + 505 0093 00 .byte 0 + 506 0094 00 .byte 0 + 507 0095 00 .byte 0 + 508 .type BS_IOPINS0_8_VAL.4809, %object + 509 .size BS_IOPINS0_8_VAL.4809, 10 + 510 BS_IOPINS0_8_VAL.4809: + 511 0096 00 .byte 0 + 512 0097 00 .byte 0 + 513 0098 00 .byte 0 + 514 0099 00 .byte 0 + 515 009a 00 .byte 0 + 516 009b 00 .byte 0 + 517 009c 00 .byte 0 + 518 009d 00 .byte 0 + 519 009e C0 .byte -64 + 520 009f 00 .byte 0 + 521 .type BS_IOPINS0_3_VAL.4810, %object + 522 .size BS_IOPINS0_3_VAL.4810, 8 + 523 BS_IOPINS0_3_VAL.4810: + 524 00a0 00 .byte 0 + 525 00a1 3E .byte 62 + 526 00a2 00 .byte 0 + 527 00a3 00 .byte 0 + 528 00a4 00 .byte 0 + 529 00a5 00 .byte 0 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 19 + + + 530 00a6 00 .byte 0 + 531 00a7 00 .byte 0 + 532 .type BS_IOPINS0_4_VAL.4811, %object + 533 .size BS_IOPINS0_4_VAL.4811, 8 + 534 BS_IOPINS0_4_VAL.4811: + 535 00a8 00 .byte 0 + 536 00a9 FC .byte -4 + 537 00aa FC .byte -4 + 538 00ab 00 .byte 0 + 539 00ac 00 .byte 0 + 540 00ad 00 .byte 0 + 541 00ae 00 .byte 0 + 542 00af 00 .byte 0 + 543 .type BS_IOPINS0_6_VAL.4812, %object + 544 .size BS_IOPINS0_6_VAL.4812, 8 + 545 BS_IOPINS0_6_VAL.4812: + 546 00b0 00 .byte 0 + 547 00b1 0F .byte 15 + 548 00b2 0F .byte 15 + 549 00b3 00 .byte 0 + 550 00b4 00 .byte 0 + 551 00b5 00 .byte 0 + 552 00b6 00 .byte 0 + 553 00b7 00 .byte 0 + 554 .text + 555 .Letext0: + 556 .file 2 "c:\\program files (x86)\\cypress\\psoc creator\\3.0\\psoc creator\\import\\gnu_cs\\arm\\4 + 557 .file 3 "./Generated_Source/PSoC5/cytypes.h" + 558 .file 4 "./Generated_Source/PSoC5/CyLib.h" + 559 .section .debug_info,"",%progbits + 560 .Ldebug_info0: + 561 0000 45050000 .4byte 0x545 + 562 0004 0200 .2byte 0x2 + 563 0006 00000000 .4byte .Ldebug_abbrev0 + 564 000a 04 .byte 0x4 + 565 000b 01 .uleb128 0x1 + 566 000c 3C020000 .4byte .LASF52 + 567 0010 01 .byte 0x1 + 568 0011 2E010000 .4byte .LASF53 + 569 0015 99010000 .4byte .LASF54 + 570 0019 A0000000 .4byte .Ldebug_ranges0+0xa0 + 571 001d 00000000 .4byte 0 + 572 0021 00000000 .4byte 0 + 573 0025 00000000 .4byte .Ldebug_line0 + 574 0029 02 .uleb128 0x2 + 575 002a 01 .byte 0x1 + 576 002b 06 .byte 0x6 + 577 002c 8F000000 .4byte .LASF0 + 578 0030 02 .uleb128 0x2 + 579 0031 01 .byte 0x1 + 580 0032 08 .byte 0x8 + 581 0033 8A020000 .4byte .LASF1 + 582 0037 02 .uleb128 0x2 + 583 0038 02 .byte 0x2 + 584 0039 05 .byte 0x5 + 585 003a 98020000 .4byte .LASF2 + 586 003e 02 .uleb128 0x2 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 20 + + + 587 003f 02 .byte 0x2 + 588 0040 07 .byte 0x7 + 589 0041 75010000 .4byte .LASF3 + 590 0045 03 .uleb128 0x3 + 591 0046 04 .byte 0x4 + 592 0047 05 .byte 0x5 + 593 0048 696E7400 .ascii "int\000" + 594 004c 02 .uleb128 0x2 + 595 004d 04 .byte 0x4 + 596 004e 07 .byte 0x7 + 597 004f 21010000 .4byte .LASF4 + 598 0053 02 .uleb128 0x2 + 599 0054 08 .byte 0x8 + 600 0055 05 .byte 0x5 + 601 0056 81000000 .4byte .LASF5 + 602 005a 02 .uleb128 0x2 + 603 005b 08 .byte 0x8 + 604 005c 07 .byte 0x7 + 605 005d 3C000000 .4byte .LASF6 + 606 0061 02 .uleb128 0x2 + 607 0062 04 .byte 0x4 + 608 0063 05 .byte 0x5 + 609 0064 E5000000 .4byte .LASF7 + 610 0068 02 .uleb128 0x2 + 611 0069 04 .byte 0x4 + 612 006a 07 .byte 0x7 + 613 006b DA010000 .4byte .LASF8 + 614 006f 04 .uleb128 0x4 + 615 0070 04 .byte 0x4 + 616 0071 02 .uleb128 0x2 + 617 0072 04 .byte 0x4 + 618 0073 07 .byte 0x7 + 619 0074 56010000 .4byte .LASF9 + 620 0078 02 .uleb128 0x2 + 621 0079 01 .byte 0x1 + 622 007a 08 .byte 0x8 + 623 007b DF020000 .4byte .LASF10 + 624 007f 05 .uleb128 0x5 + 625 0080 16000000 .4byte .LASF11 + 626 0084 02 .byte 0x2 + 627 0085 D5 .byte 0xd5 + 628 0086 4C000000 .4byte 0x4c + 629 008a 05 .uleb128 0x5 + 630 008b F4000000 .4byte .LASF12 + 631 008f 03 .byte 0x3 + 632 0090 5B .byte 0x5b + 633 0091 30000000 .4byte 0x30 + 634 0095 05 .uleb128 0x5 + 635 0096 06000000 .4byte .LASF13 + 636 009a 03 .byte 0x3 + 637 009b 5C .byte 0x5c + 638 009c 3E000000 .4byte 0x3e + 639 00a0 05 .uleb128 0x5 + 640 00a1 0B010000 .4byte .LASF14 + 641 00a5 03 .byte 0x3 + 642 00a6 5D .byte 0x5d + 643 00a7 71000000 .4byte 0x71 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 21 + + + 644 00ab 02 .uleb128 0x2 + 645 00ac 04 .byte 0x4 + 646 00ad 04 .byte 0x4 + 647 00ae 28020000 .4byte .LASF15 + 648 00b2 02 .uleb128 0x2 + 649 00b3 08 .byte 0x8 + 650 00b4 04 .byte 0x4 + 651 00b5 FA000000 .4byte .LASF16 + 652 00b9 05 .uleb128 0x5 + 653 00ba 85020000 .4byte .LASF17 + 654 00be 03 .byte 0x3 + 655 00bf F0 .byte 0xf0 + 656 00c0 C4000000 .4byte 0xc4 + 657 00c4 06 .uleb128 0x6 + 658 00c5 8A000000 .4byte 0x8a + 659 00c9 05 .uleb128 0x5 + 660 00ca EE000000 .4byte .LASF18 + 661 00ce 03 .byte 0x3 + 662 00cf F1 .byte 0xf1 + 663 00d0 D4000000 .4byte 0xd4 + 664 00d4 06 .uleb128 0x6 + 665 00d5 95000000 .4byte 0x95 + 666 00d9 07 .uleb128 0x7 + 667 00da 02 .byte 0x2 + 668 00db 01 .byte 0x1 + 669 00dc 7D .byte 0x7d + 670 00dd FE000000 .4byte 0xfe + 671 00e1 08 .uleb128 0x8 + 672 00e2 FA020000 .4byte .LASF19 + 673 00e6 01 .byte 0x1 + 674 00e7 7F .byte 0x7f + 675 00e8 8A000000 .4byte 0x8a + 676 00ec 02 .byte 0x2 + 677 00ed 23 .byte 0x23 + 678 00ee 00 .uleb128 0 + 679 00ef 08 .uleb128 0x8 + 680 00f0 1B010000 .4byte .LASF20 + 681 00f4 01 .byte 0x1 + 682 00f5 80 .byte 0x80 + 683 00f6 8A000000 .4byte 0x8a + 684 00fa 02 .byte 0x2 + 685 00fb 23 .byte 0x23 + 686 00fc 01 .uleb128 0x1 + 687 00fd 00 .byte 0 + 688 00fe 05 .uleb128 0x5 + 689 00ff CC020000 .4byte .LASF21 + 690 0103 01 .byte 0x1 + 691 0104 81 .byte 0x81 + 692 0105 D9000000 .4byte 0xd9 + 693 0109 09 .uleb128 0x9 + 694 010a 1D000000 .4byte .LASF22 + 695 010e 01 .byte 0x1 + 696 010f 69 .byte 0x69 + 697 0110 01 .byte 0x1 + 698 0111 01 .byte 0x1 + 699 0112 22010000 .4byte 0x122 + 700 0116 0A .uleb128 0xa + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 22 + + + 701 0117 CA000000 .4byte .LASF24 + 702 011b 01 .byte 0x1 + 703 011c 69 .byte 0x69 + 704 011d 8A000000 .4byte 0x8a + 705 0121 00 .byte 0 + 706 0122 09 .uleb128 0x9 + 707 0123 CA010000 .4byte .LASF23 + 708 0127 01 .byte 0x1 + 709 0128 49 .byte 0x49 + 710 0129 01 .byte 0x1 + 711 012a 01 .byte 0x1 + 712 012b 4F010000 .4byte 0x14f + 713 012f 0A .uleb128 0xa + 714 0130 23020000 .4byte .LASF25 + 715 0134 01 .byte 0x1 + 716 0135 49 .byte 0x49 + 717 0136 6F000000 .4byte 0x6f + 718 013a 0B .uleb128 0xb + 719 013b 73726300 .ascii "src\000" + 720 013f 01 .byte 0x1 + 721 0140 49 .byte 0x49 + 722 0141 4F010000 .4byte 0x14f + 723 0145 0B .uleb128 0xb + 724 0146 6E00 .ascii "n\000" + 725 0148 01 .byte 0x1 + 726 0149 49 .byte 0x49 + 727 014a 7F000000 .4byte 0x7f + 728 014e 00 .byte 0 + 729 014f 0C .uleb128 0xc + 730 0150 04 .byte 0x4 + 731 0151 55010000 .4byte 0x155 + 732 0155 0D .uleb128 0xd + 733 0156 09 .uleb128 0x9 + 734 0157 10030000 .4byte .LASF26 + 735 015b 01 .byte 0x1 + 736 015c 42 .byte 0x42 + 737 015d 01 .byte 0x1 + 738 015e 01 .byte 0x1 + 739 015f 83010000 .4byte 0x183 + 740 0163 0A .uleb128 0xa + 741 0164 23020000 .4byte .LASF25 + 742 0168 01 .byte 0x1 + 743 0169 42 .byte 0x42 + 744 016a 6F000000 .4byte 0x6f + 745 016e 0B .uleb128 0xb + 746 016f 73726300 .ascii "src\000" + 747 0173 01 .byte 0x1 + 748 0174 42 .byte 0x42 + 749 0175 4F010000 .4byte 0x14f + 750 0179 0B .uleb128 0xb + 751 017a 6E00 .ascii "n\000" + 752 017c 01 .byte 0x1 + 753 017d 42 .byte 0x42 + 754 017e 7F000000 .4byte 0x7f + 755 0182 00 .byte 0 + 756 0183 09 .uleb128 0x9 + 757 0184 AD000000 .4byte .LASF27 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 23 + + + 758 0188 01 .byte 0x1 + 759 0189 94 .byte 0x94 + 760 018a 01 .byte 0x1 + 761 018b 01 .byte 0x1 + 762 018c D1010000 .4byte 0x1d1 + 763 0190 0A .uleb128 0xa + 764 0191 53000000 .4byte .LASF28 + 765 0195 01 .byte 0x1 + 766 0196 94 .byte 0x94 + 767 0197 D1010000 .4byte 0x1d1 + 768 019b 0A .uleb128 0xa + 769 019c 31000000 .4byte .LASF29 + 770 01a0 01 .byte 0x1 + 771 01a1 94 .byte 0x94 + 772 01a2 DC010000 .4byte 0x1dc + 773 01a6 0E .uleb128 0xe + 774 01a7 6900 .ascii "i\000" + 775 01a9 01 .byte 0x1 + 776 01aa 97 .byte 0x97 + 777 01ab A0000000 .4byte 0xa0 + 778 01af 0E .uleb128 0xe + 779 01b0 6A00 .ascii "j\000" + 780 01b2 01 .byte 0x1 + 781 01b3 97 .byte 0x97 + 782 01b4 A0000000 .4byte 0xa0 + 783 01b8 0F .uleb128 0xf + 784 01b9 10 .uleb128 0x10 + 785 01ba 0D000000 .4byte .LASF30 + 786 01be 01 .byte 0x1 + 787 01bf 9A .byte 0x9a + 788 01c0 A0000000 .4byte 0xa0 + 789 01c4 10 .uleb128 0x10 + 790 01c5 00000000 .4byte .LASF31 + 791 01c9 01 .byte 0x1 + 792 01ca 9B .byte 0x9b + 793 01cb 8A000000 .4byte 0x8a + 794 01cf 00 .byte 0 + 795 01d0 00 .byte 0 + 796 01d1 0C .uleb128 0xc + 797 01d2 04 .byte 0x4 + 798 01d3 D7010000 .4byte 0x1d7 + 799 01d7 11 .uleb128 0x11 + 800 01d8 A0000000 .4byte 0xa0 + 801 01dc 0C .uleb128 0xc + 802 01dd 04 .byte 0x4 + 803 01de E2010000 .4byte 0x1e2 + 804 01e2 11 .uleb128 0x11 + 805 01e3 FE000000 .4byte 0xfe + 806 01e7 12 .uleb128 0x12 + 807 01e8 01 .byte 0x1 + 808 01e9 E4020000 .4byte .LASF38 + 809 01ed 01 .byte 0x1 + 810 01ee 0E01 .2byte 0x10e + 811 01f0 01 .byte 0x1 + 812 01f1 00000000 .4byte .LFB7 + 813 01f5 0C000000 .4byte .LFE7 + 814 01f9 02 .byte 0x2 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 24 + + + 815 01fa 7D .byte 0x7d + 816 01fb 00 .sleb128 0 + 817 01fc 01 .byte 0x1 + 818 01fd 1E020000 .4byte 0x21e + 819 0201 13 .uleb128 0x13 + 820 0202 01030000 .4byte .LASF55 + 821 0206 01 .byte 0x1 + 822 0207 0E01 .2byte 0x10e + 823 0209 8A000000 .4byte 0x8a + 824 020d 01 .byte 0x1 + 825 020e 50 .byte 0x50 + 826 020f 14 .uleb128 0x14 + 827 0210 12010000 .4byte .LASF40 + 828 0214 01 .byte 0x1 + 829 0215 1001 .2byte 0x110 + 830 0217 8A000000 .4byte 0x8a + 831 021b 01 .byte 0x1 + 832 021c 52 .byte 0x52 + 833 021d 00 .byte 0 + 834 021e 09 .uleb128 0x9 + 835 021f BF000000 .4byte .LASF32 + 836 0223 01 .byte 0x1 + 837 0224 B7 .byte 0xb7 + 838 0225 01 .byte 0x1 + 839 0226 01 .byte 0x1 + 840 0227 42020000 .4byte 0x242 + 841 022b 10 .uleb128 0x10 + 842 022c 68010000 .4byte .LASF33 + 843 0230 01 .byte 0x1 + 844 0231 B9 .byte 0xb9 + 845 0232 A0000000 .4byte 0xa0 + 846 0236 10 .uleb128 0x10 + 847 0237 B3020000 .4byte .LASF34 + 848 023b 01 .byte 0x1 + 849 023c BA .byte 0xba + 850 023d 8A000000 .4byte 0x8a + 851 0241 00 .byte 0 + 852 0242 09 .uleb128 0x9 + 853 0243 01010000 .4byte .LASF35 + 854 0247 01 .byte 0x1 + 855 0248 3B .byte 0x3b + 856 0249 01 .byte 0x1 + 857 024a 01 .byte 0x1 + 858 024b 62020000 .4byte 0x262 + 859 024f 0B .uleb128 0xb + 860 0250 7300 .ascii "s\000" + 861 0252 01 .byte 0x1 + 862 0253 3B .byte 0x3b + 863 0254 6F000000 .4byte 0x6f + 864 0258 0B .uleb128 0xb + 865 0259 6E00 .ascii "n\000" + 866 025b 01 .byte 0x1 + 867 025c 3B .byte 0x3b + 868 025d 7F000000 .4byte 0x7f + 869 0261 00 .byte 0 + 870 0262 09 .uleb128 0x9 + 871 0263 70000000 .4byte .LASF36 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 25 + + + 872 0267 01 .byte 0x1 + 873 0268 F4 .byte 0xf4 + 874 0269 01 .byte 0x1 + 875 026a 01 .byte 0x1 + 876 026b 7B020000 .4byte 0x27b + 877 026f 10 .uleb128 0x10 + 878 0270 E3010000 .4byte .LASF37 + 879 0274 01 .byte 0x1 + 880 0275 F6 .byte 0xf6 + 881 0276 8A000000 .4byte 0x8a + 882 027a 00 .byte 0 + 883 027b 15 .uleb128 0x15 + 884 027c 01 .byte 0x1 + 885 027d 24030000 .4byte .LASF39 + 886 0281 01 .byte 0x1 + 887 0282 3001 .2byte 0x130 + 888 0284 01 .byte 0x1 + 889 0285 00000000 .4byte .LFB8 + 890 0289 D8010000 .4byte .LFE8 + 891 028d 00000000 .4byte .LLST0 + 892 0291 01 .byte 0x1 + 893 0292 B4040000 .4byte 0x4b4 + 894 0296 14 .uleb128 0x14 + 895 0297 A2020000 .4byte .LASF41 + 896 029b 01 .byte 0x1 + 897 029c 3301 .2byte 0x133 + 898 029e C4040000 .4byte 0x4c4 + 899 02a2 05 .byte 0x5 + 900 02a3 03 .byte 0x3 + 901 02a4 8E000000 .4byte BS_IOPINS0_0_VAL.4808 + 902 02a8 14 .uleb128 0x14 + 903 02a9 BB020000 .4byte .LASF42 + 904 02ad 01 .byte 0x1 + 905 02ae 3701 .2byte 0x137 + 906 02b0 D9040000 .4byte 0x4d9 + 907 02b4 05 .byte 0x5 + 908 02b5 03 .byte 0x3 + 909 02b6 96000000 .4byte BS_IOPINS0_8_VAL.4809 + 910 02ba 14 .uleb128 0x14 + 911 02bb 12020000 .4byte .LASF43 + 912 02bf 01 .byte 0x1 + 913 02c0 3B01 .2byte 0x13b + 914 02c2 DE040000 .4byte 0x4de + 915 02c6 05 .byte 0x5 + 916 02c7 03 .byte 0x3 + 917 02c8 A0000000 .4byte BS_IOPINS0_3_VAL.4810 + 918 02cc 14 .uleb128 0x14 + 919 02cd D4000000 .4byte .LASF44 + 920 02d1 01 .byte 0x1 + 921 02d2 3F01 .2byte 0x13f + 922 02d4 E3040000 .4byte 0x4e3 + 923 02d8 05 .byte 0x5 + 924 02d9 03 .byte 0x3 + 925 02da A8000000 .4byte BS_IOPINS0_4_VAL.4811 + 926 02de 14 .uleb128 0x14 + 927 02df 88010000 .4byte .LASF45 + 928 02e3 01 .byte 0x1 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 26 + + + 929 02e4 4301 .2byte 0x143 + 930 02e6 E8040000 .4byte 0x4e8 + 931 02ea 05 .byte 0x5 + 932 02eb 03 .byte 0x3 + 933 02ec B0000000 .4byte BS_IOPINS0_6_VAL.4812 + 934 02f0 16 .uleb128 0x16 + 935 02f1 1E020000 .4byte 0x21e + 936 02f5 08000000 .4byte .LBB32 + 937 02f9 00000000 .4byte .Ldebug_ranges0+0 + 938 02fd 01 .byte 0x1 + 939 02fe 4F01 .2byte 0x14f + 940 0300 2A030000 .4byte 0x32a + 941 0304 17 .uleb128 0x17 + 942 0305 20000000 .4byte .Ldebug_ranges0+0x20 + 943 0309 18 .uleb128 0x18 + 944 030a 2B020000 .4byte 0x22b + 945 030e 19 .uleb128 0x19 + 946 030f 36020000 .4byte 0x236 + 947 0313 20000000 .4byte .LLST1 + 948 0317 1A .uleb128 0x1a + 949 0318 4A000000 .4byte .LVL3 + 950 031c 17050000 .4byte 0x517 + 951 0320 1B .uleb128 0x1b + 952 0321 01 .byte 0x1 + 953 0322 50 .byte 0x50 + 954 0323 03 .byte 0x3 + 955 0324 0A .byte 0xa + 956 0325 E001 .2byte 0x1e0 + 957 0327 00 .byte 0 + 958 0328 00 .byte 0 + 959 0329 00 .byte 0 + 960 032a 1C .uleb128 0x1c + 961 032b 40000000 .4byte .Ldebug_ranges0+0x40 + 962 032f 62040000 .4byte 0x462 + 963 0333 14 .uleb128 0x14 + 964 0334 9B000000 .4byte .LASF46 + 965 0338 01 .byte 0x1 + 966 0339 5401 .2byte 0x154 + 967 033b FD040000 .4byte 0x4fd + 968 033f 05 .byte 0x5 + 969 0340 03 .byte 0x3 + 970 0341 30000000 .4byte cy_cfg_addr_table.4813 + 971 0345 14 .uleb128 0x14 + 972 0346 5E000000 .4byte .LASF47 + 973 034a 01 .byte 0x1 + 974 034b 6301 .2byte 0x163 + 975 034d 12050000 .4byte 0x512 + 976 0351 05 .byte 0x5 + 977 0352 03 .byte 0x3 + 978 0353 60000000 .4byte cy_cfg_data_table.4814 + 979 0357 1D .uleb128 0x1d + 980 0358 06 .byte 0x6 + 981 0359 01 .byte 0x1 + 982 035a 7F01 .2byte 0x17f + 983 035c 7F030000 .4byte 0x37f + 984 0360 1E .uleb128 0x1e + 985 0361 1C030000 .4byte .LASF48 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 27 + + + 986 0365 01 .byte 0x1 + 987 0366 8001 .2byte 0x180 + 988 0368 6F000000 .4byte 0x6f + 989 036c 02 .byte 0x2 + 990 036d 23 .byte 0x23 + 991 036e 00 .uleb128 0 + 992 036f 1E .uleb128 0x1e + 993 0370 70010000 .4byte .LASF49 + 994 0374 01 .byte 0x1 + 995 0375 8101 .2byte 0x181 + 996 0377 95000000 .4byte 0x95 + 997 037b 02 .byte 0x2 + 998 037c 23 .byte 0x23 + 999 037d 04 .uleb128 0x4 + 1000 037e 00 .byte 0 + 1001 037f 1F .uleb128 0x1f + 1002 0380 F5010000 .4byte .LASF50 + 1003 0384 01 .byte 0x1 + 1004 0385 8201 .2byte 0x182 + 1005 0387 57030000 .4byte 0x357 + 1006 038b 20 .uleb128 0x20 + 1007 038c 7F030000 .4byte 0x37f + 1008 0390 9B030000 .4byte 0x39b + 1009 0394 21 .uleb128 0x21 + 1010 0395 68000000 .4byte 0x68 + 1011 0399 07 .byte 0x7 + 1012 039a 00 .byte 0 + 1013 039b 14 .uleb128 0x14 + 1014 039c 02020000 .4byte .LASF51 + 1015 03a0 01 .byte 0x1 + 1016 03a1 8401 .2byte 0x184 + 1017 03a3 AD030000 .4byte 0x3ad + 1018 03a7 05 .byte 0x5 + 1019 03a8 03 .byte 0x3 + 1020 03a9 00000000 .4byte cfg_memset_list.4819 + 1021 03ad 11 .uleb128 0x11 + 1022 03ae 8B030000 .4byte 0x38b + 1023 03b2 22 .uleb128 0x22 + 1024 03b3 6900 .ascii "i\000" + 1025 03b5 01 .byte 0x1 + 1026 03b6 9001 .2byte 0x190 + 1027 03b8 8A000000 .4byte 0x8a + 1028 03bc 3E000000 .4byte .LLST2 + 1029 03c0 23 .uleb128 0x23 + 1030 03c1 84000000 .4byte .LBB39 + 1031 03c5 98000000 .4byte .LBE39 + 1032 03c9 1A040000 .4byte 0x41a + 1033 03cd 22 .uleb128 0x22 + 1034 03ce 6D7300 .ascii "ms\000" + 1035 03d1 01 .byte 0x1 + 1036 03d2 9501 .2byte 0x195 + 1037 03d4 DC030000 .4byte 0x3dc + 1038 03d8 52000000 .4byte .LLST3 + 1039 03dc 0C .uleb128 0xc + 1040 03dd 04 .byte 0x4 + 1041 03de E2030000 .4byte 0x3e2 + 1042 03e2 11 .uleb128 0x11 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 28 + + + 1043 03e3 7F030000 .4byte 0x37f + 1044 03e7 24 .uleb128 0x24 + 1045 03e8 42020000 .4byte 0x242 + 1046 03ec 8C000000 .4byte .LBB40 + 1047 03f0 98000000 .4byte .LBE40 + 1048 03f4 01 .byte 0x1 + 1049 03f5 9601 .2byte 0x196 + 1050 03f7 25 .uleb128 0x25 + 1051 03f8 58020000 .4byte 0x258 + 1052 03fc 77000000 .4byte .LLST4 + 1053 0400 25 .uleb128 0x25 + 1054 0401 4F020000 .4byte 0x24f + 1055 0405 AC000000 .4byte .LLST5 + 1056 0409 1A .uleb128 0x1a + 1057 040a 98000000 .4byte .LVL12 + 1058 040e 2B050000 .4byte 0x52b + 1059 0412 1B .uleb128 0x1b + 1060 0413 01 .byte 0x1 + 1061 0414 51 .byte 0x51 + 1062 0415 01 .byte 0x1 + 1063 0416 30 .byte 0x30 + 1064 0417 00 .byte 0 + 1065 0418 00 .byte 0 + 1066 0419 00 .byte 0 + 1067 041a 26 .uleb128 0x26 + 1068 041b 83010000 .4byte 0x183 + 1069 041f A0000000 .4byte .LBB42 + 1070 0423 58000000 .4byte .Ldebug_ranges0+0x58 + 1071 0427 01 .byte 0x1 + 1072 0428 9901 .2byte 0x199 + 1073 042a 17 .uleb128 0x17 + 1074 042b 70000000 .4byte .Ldebug_ranges0+0x70 + 1075 042f 18 .uleb128 0x18 + 1076 0430 A6010000 .4byte 0x1a6 + 1077 0434 19 .uleb128 0x19 + 1078 0435 AF010000 .4byte 0x1af + 1079 0439 DC000000 .4byte .LLST6 + 1080 043d 27 .uleb128 0x27 + 1081 043e 9B010000 .4byte 0x19b + 1082 0442 27 .uleb128 0x27 + 1083 0443 90010000 .4byte 0x190 + 1084 0447 17 .uleb128 0x17 + 1085 0448 88000000 .4byte .Ldebug_ranges0+0x88 + 1086 044c 19 .uleb128 0x19 + 1087 044d B9010000 .4byte 0x1b9 + 1088 0451 EF000000 .4byte .LLST7 + 1089 0455 19 .uleb128 0x19 + 1090 0456 C4010000 .4byte 0x1c4 + 1091 045a 0D010000 .4byte .LLST8 + 1092 045e 00 .byte 0 + 1093 045f 00 .byte 0 + 1094 0460 00 .byte 0 + 1095 0461 00 .byte 0 + 1096 0462 28 .uleb128 0x28 + 1097 0463 62020000 .4byte 0x262 + 1098 0467 50010000 .4byte .LBB49 + 1099 046b 66010000 .4byte .LBE49 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 29 + + + 1100 046f 01 .byte 0x1 + 1101 0470 AF01 .2byte 0x1af + 1102 0472 8A040000 .4byte 0x48a + 1103 0476 29 .uleb128 0x29 + 1104 0477 50010000 .4byte .LBB50 + 1105 047b 66010000 .4byte .LBE50 + 1106 047f 19 .uleb128 0x19 + 1107 0480 6F020000 .4byte 0x26f + 1108 0484 20010000 .4byte .LLST9 + 1109 0488 00 .byte 0 + 1110 0489 00 .byte 0 + 1111 048a 24 .uleb128 0x24 + 1112 048b 56010000 .4byte 0x156 + 1113 048f 66010000 .4byte .LBB51 + 1114 0493 D8010000 .4byte .LBE51 + 1115 0497 01 .byte 0x1 + 1116 0498 B201 .2byte 0x1b2 + 1117 049a 2A .uleb128 0x2a + 1118 049b 79010000 .4byte 0x179 + 1119 049f 0E .byte 0xe + 1120 04a0 2B .uleb128 0x2b + 1121 04a1 6E010000 .4byte 0x16e + 1122 04a5 A0430040 .4byte 0x400043a0 + 1123 04a9 2B .uleb128 0x2b + 1124 04aa 63010000 .4byte 0x163 + 1125 04ae B0430040 .4byte 0x400043b0 + 1126 04b2 00 .byte 0 + 1127 04b3 00 .byte 0 + 1128 04b4 20 .uleb128 0x20 + 1129 04b5 8A000000 .4byte 0x8a + 1130 04b9 C4040000 .4byte 0x4c4 + 1131 04bd 21 .uleb128 0x21 + 1132 04be 68000000 .4byte 0x68 + 1133 04c2 07 .byte 0x7 + 1134 04c3 00 .byte 0 + 1135 04c4 11 .uleb128 0x11 + 1136 04c5 B4040000 .4byte 0x4b4 + 1137 04c9 20 .uleb128 0x20 + 1138 04ca 8A000000 .4byte 0x8a + 1139 04ce D9040000 .4byte 0x4d9 + 1140 04d2 21 .uleb128 0x21 + 1141 04d3 68000000 .4byte 0x68 + 1142 04d7 09 .byte 0x9 + 1143 04d8 00 .byte 0 + 1144 04d9 11 .uleb128 0x11 + 1145 04da C9040000 .4byte 0x4c9 + 1146 04de 11 .uleb128 0x11 + 1147 04df B4040000 .4byte 0x4b4 + 1148 04e3 11 .uleb128 0x11 + 1149 04e4 B4040000 .4byte 0x4b4 + 1150 04e8 11 .uleb128 0x11 + 1151 04e9 B4040000 .4byte 0x4b4 + 1152 04ed 20 .uleb128 0x20 + 1153 04ee A0000000 .4byte 0xa0 + 1154 04f2 FD040000 .4byte 0x4fd + 1155 04f6 21 .uleb128 0x21 + 1156 04f7 68000000 .4byte 0x68 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 30 + + + 1157 04fb 0B .byte 0xb + 1158 04fc 00 .byte 0 + 1159 04fd 11 .uleb128 0x11 + 1160 04fe ED040000 .4byte 0x4ed + 1161 0502 20 .uleb128 0x20 + 1162 0503 FE000000 .4byte 0xfe + 1163 0507 12050000 .4byte 0x512 + 1164 050b 21 .uleb128 0x21 + 1165 050c 68000000 .4byte 0x68 + 1166 0510 16 .byte 0x16 + 1167 0511 00 .byte 0 + 1168 0512 11 .uleb128 0x11 + 1169 0513 02050000 .4byte 0x502 + 1170 0517 2C .uleb128 0x2c + 1171 0518 01 .byte 0x1 + 1172 0519 2E020000 .4byte .LASF56 + 1173 051d 04 .byte 0x4 + 1174 051e 7A .byte 0x7a + 1175 051f 01 .byte 0x1 + 1176 0520 01 .byte 0x1 + 1177 0521 2B050000 .4byte 0x52b + 1178 0525 2D .uleb128 0x2d + 1179 0526 A0000000 .4byte 0xa0 + 1180 052a 00 .byte 0 + 1181 052b 2E .uleb128 0x2e + 1182 052c 01 .byte 0x1 + 1183 052d 09030000 .4byte .LASF57 + 1184 0531 01 .byte 0x1 + 1185 0532 6F000000 .4byte 0x6f + 1186 0536 01 .byte 0x1 + 1187 0537 01 .byte 0x1 + 1188 0538 2D .uleb128 0x2d + 1189 0539 6F000000 .4byte 0x6f + 1190 053d 2D .uleb128 0x2d + 1191 053e 45000000 .4byte 0x45 + 1192 0542 2D .uleb128 0x2d + 1193 0543 68000000 .4byte 0x68 + 1194 0547 00 .byte 0 + 1195 0548 00 .byte 0 + 1196 .section .debug_abbrev,"",%progbits + 1197 .Ldebug_abbrev0: + 1198 0000 01 .uleb128 0x1 + 1199 0001 11 .uleb128 0x11 + 1200 0002 01 .byte 0x1 + 1201 0003 25 .uleb128 0x25 + 1202 0004 0E .uleb128 0xe + 1203 0005 13 .uleb128 0x13 + 1204 0006 0B .uleb128 0xb + 1205 0007 03 .uleb128 0x3 + 1206 0008 0E .uleb128 0xe + 1207 0009 1B .uleb128 0x1b + 1208 000a 0E .uleb128 0xe + 1209 000b 55 .uleb128 0x55 + 1210 000c 06 .uleb128 0x6 + 1211 000d 11 .uleb128 0x11 + 1212 000e 01 .uleb128 0x1 + 1213 000f 52 .uleb128 0x52 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 31 + + + 1214 0010 01 .uleb128 0x1 + 1215 0011 10 .uleb128 0x10 + 1216 0012 06 .uleb128 0x6 + 1217 0013 00 .byte 0 + 1218 0014 00 .byte 0 + 1219 0015 02 .uleb128 0x2 + 1220 0016 24 .uleb128 0x24 + 1221 0017 00 .byte 0 + 1222 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.uleb128 0x13 + 1469 0111 00 .byte 0 + 1470 0112 00 .byte 0 + 1471 0113 16 .uleb128 0x16 + 1472 0114 1D .uleb128 0x1d + 1473 0115 01 .byte 0x1 + 1474 0116 31 .uleb128 0x31 + 1475 0117 13 .uleb128 0x13 + 1476 0118 52 .uleb128 0x52 + 1477 0119 01 .uleb128 0x1 + 1478 011a 55 .uleb128 0x55 + 1479 011b 06 .uleb128 0x6 + 1480 011c 58 .uleb128 0x58 + 1481 011d 0B .uleb128 0xb + 1482 011e 59 .uleb128 0x59 + 1483 011f 05 .uleb128 0x5 + 1484 0120 01 .uleb128 0x1 + 1485 0121 13 .uleb128 0x13 + 1486 0122 00 .byte 0 + 1487 0123 00 .byte 0 + 1488 0124 17 .uleb128 0x17 + 1489 0125 0B .uleb128 0xb + 1490 0126 01 .byte 0x1 + 1491 0127 55 .uleb128 0x55 + 1492 0128 06 .uleb128 0x6 + 1493 0129 00 .byte 0 + 1494 012a 00 .byte 0 + 1495 012b 18 .uleb128 0x18 + 1496 012c 34 .uleb128 0x34 + 1497 012d 00 .byte 0 + 1498 012e 31 .uleb128 0x31 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 36 + + + 1499 012f 13 .uleb128 0x13 + 1500 0130 00 .byte 0 + 1501 0131 00 .byte 0 + 1502 0132 19 .uleb128 0x19 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.uleb128 0x13 + 1540 015d 01 .byte 0x1 + 1541 015e 0B .uleb128 0xb + 1542 015f 0B .uleb128 0xb + 1543 0160 3A .uleb128 0x3a + 1544 0161 0B .uleb128 0xb + 1545 0162 3B .uleb128 0x3b + 1546 0163 05 .uleb128 0x5 + 1547 0164 01 .uleb128 0x1 + 1548 0165 13 .uleb128 0x13 + 1549 0166 00 .byte 0 + 1550 0167 00 .byte 0 + 1551 0168 1E .uleb128 0x1e + 1552 0169 0D .uleb128 0xd + 1553 016a 00 .byte 0 + 1554 016b 03 .uleb128 0x3 + 1555 016c 0E .uleb128 0xe + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 37 + + + 1556 016d 3A .uleb128 0x3a + 1557 016e 0B .uleb128 0xb + 1558 016f 3B .uleb128 0x3b + 1559 0170 05 .uleb128 0x5 + 1560 0171 49 .uleb128 0x49 + 1561 0172 13 .uleb128 0x13 + 1562 0173 38 .uleb128 0x38 + 1563 0174 0A .uleb128 0xa + 1564 0175 00 .byte 0 + 1565 0176 00 .byte 0 + 1566 0177 1F .uleb128 0x1f + 1567 0178 16 .uleb128 0x16 + 1568 0179 00 .byte 0 + 1569 017a 03 .uleb128 0x3 + 1570 017b 0E .uleb128 0xe + 1571 017c 3A .uleb128 0x3a + 1572 017d 0B .uleb128 0xb + 1573 017e 3B .uleb128 0x3b + 1574 017f 05 .uleb128 0x5 + 1575 0180 49 .uleb128 0x49 + 1576 0181 13 .uleb128 0x13 + 1577 0182 00 .byte 0 + 1578 0183 00 .byte 0 + 1579 0184 20 .uleb128 0x20 + 1580 0185 01 .uleb128 0x1 + 1581 0186 01 .byte 0x1 + 1582 0187 49 .uleb128 0x49 + 1583 0188 13 .uleb128 0x13 + 1584 0189 01 .uleb128 0x1 + 1585 018a 13 .uleb128 0x13 + 1586 018b 00 .byte 0 + 1587 018c 00 .byte 0 + 1588 018d 21 .uleb128 0x21 + 1589 018e 21 .uleb128 0x21 + 1590 018f 00 .byte 0 + 1591 0190 49 .uleb128 0x49 + 1592 0191 13 .uleb128 0x13 + 1593 0192 2F .uleb128 0x2f + 1594 0193 0B .uleb128 0xb + 1595 0194 00 .byte 0 + 1596 0195 00 .byte 0 + 1597 0196 22 .uleb128 0x22 + 1598 0197 34 .uleb128 0x34 + 1599 0198 00 .byte 0 + 1600 0199 03 .uleb128 0x3 + 1601 019a 08 .uleb128 0x8 + 1602 019b 3A .uleb128 0x3a + 1603 019c 0B .uleb128 0xb + 1604 019d 3B .uleb128 0x3b + 1605 019e 05 .uleb128 0x5 + 1606 019f 49 .uleb128 0x49 + 1607 01a0 13 .uleb128 0x13 + 1608 01a1 02 .uleb128 0x2 + 1609 01a2 06 .uleb128 0x6 + 1610 01a3 00 .byte 0 + 1611 01a4 00 .byte 0 + 1612 01a5 23 .uleb128 0x23 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 38 + + + 1613 01a6 0B .uleb128 0xb + 1614 01a7 01 .byte 0x1 + 1615 01a8 11 .uleb128 0x11 + 1616 01a9 01 .uleb128 0x1 + 1617 01aa 12 .uleb128 0x12 + 1618 01ab 01 .uleb128 0x1 + 1619 01ac 01 .uleb128 0x1 + 1620 01ad 13 .uleb128 0x13 + 1621 01ae 00 .byte 0 + 1622 01af 00 .byte 0 + 1623 01b0 24 .uleb128 0x24 + 1624 01b1 1D .uleb128 0x1d + 1625 01b2 01 .byte 0x1 + 1626 01b3 31 .uleb128 0x31 + 1627 01b4 13 .uleb128 0x13 + 1628 01b5 11 .uleb128 0x11 + 1629 01b6 01 .uleb128 0x1 + 1630 01b7 12 .uleb128 0x12 + 1631 01b8 01 .uleb128 0x1 + 1632 01b9 58 .uleb128 0x58 + 1633 01ba 0B .uleb128 0xb + 1634 01bb 59 .uleb128 0x59 + 1635 01bc 05 .uleb128 0x5 + 1636 01bd 00 .byte 0 + 1637 01be 00 .byte 0 + 1638 01bf 25 .uleb128 0x25 + 1639 01c0 05 .uleb128 0x5 + 1640 01c1 00 .byte 0 + 1641 01c2 31 .uleb128 0x31 + 1642 01c3 13 .uleb128 0x13 + 1643 01c4 02 .uleb128 0x2 + 1644 01c5 06 .uleb128 0x6 + 1645 01c6 00 .byte 0 + 1646 01c7 00 .byte 0 + 1647 01c8 26 .uleb128 0x26 + 1648 01c9 1D .uleb128 0x1d + 1649 01ca 01 .byte 0x1 + 1650 01cb 31 .uleb128 0x31 + 1651 01cc 13 .uleb128 0x13 + 1652 01cd 52 .uleb128 0x52 + 1653 01ce 01 .uleb128 0x1 + 1654 01cf 55 .uleb128 0x55 + 1655 01d0 06 .uleb128 0x6 + 1656 01d1 58 .uleb128 0x58 + 1657 01d2 0B .uleb128 0xb + 1658 01d3 59 .uleb128 0x59 + 1659 01d4 05 .uleb128 0x5 + 1660 01d5 00 .byte 0 + 1661 01d6 00 .byte 0 + 1662 01d7 27 .uleb128 0x27 + 1663 01d8 05 .uleb128 0x5 + 1664 01d9 00 .byte 0 + 1665 01da 31 .uleb128 0x31 + 1666 01db 13 .uleb128 0x13 + 1667 01dc 00 .byte 0 + 1668 01dd 00 .byte 0 + 1669 01de 28 .uleb128 0x28 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 39 + + + 1670 01df 1D .uleb128 0x1d + 1671 01e0 01 .byte 0x1 + 1672 01e1 31 .uleb128 0x31 + 1673 01e2 13 .uleb128 0x13 + 1674 01e3 11 .uleb128 0x11 + 1675 01e4 01 .uleb128 0x1 + 1676 01e5 12 .uleb128 0x12 + 1677 01e6 01 .uleb128 0x1 + 1678 01e7 58 .uleb128 0x58 + 1679 01e8 0B .uleb128 0xb + 1680 01e9 59 .uleb128 0x59 + 1681 01ea 05 .uleb128 0x5 + 1682 01eb 01 .uleb128 0x1 + 1683 01ec 13 .uleb128 0x13 + 1684 01ed 00 .byte 0 + 1685 01ee 00 .byte 0 + 1686 01ef 29 .uleb128 0x29 + 1687 01f0 0B .uleb128 0xb + 1688 01f1 01 .byte 0x1 + 1689 01f2 11 .uleb128 0x11 + 1690 01f3 01 .uleb128 0x1 + 1691 01f4 12 .uleb128 0x12 + 1692 01f5 01 .uleb128 0x1 + 1693 01f6 00 .byte 0 + 1694 01f7 00 .byte 0 + 1695 01f8 2A .uleb128 0x2a + 1696 01f9 05 .uleb128 0x5 + 1697 01fa 00 .byte 0 + 1698 01fb 31 .uleb128 0x31 + 1699 01fc 13 .uleb128 0x13 + 1700 01fd 1C .uleb128 0x1c + 1701 01fe 0B .uleb128 0xb + 1702 01ff 00 .byte 0 + 1703 0200 00 .byte 0 + 1704 0201 2B .uleb128 0x2b + 1705 0202 05 .uleb128 0x5 + 1706 0203 00 .byte 0 + 1707 0204 31 .uleb128 0x31 + 1708 0205 13 .uleb128 0x13 + 1709 0206 1C .uleb128 0x1c + 1710 0207 06 .uleb128 0x6 + 1711 0208 00 .byte 0 + 1712 0209 00 .byte 0 + 1713 020a 2C .uleb128 0x2c + 1714 020b 2E .uleb128 0x2e + 1715 020c 01 .byte 0x1 + 1716 020d 3F .uleb128 0x3f + 1717 020e 0C .uleb128 0xc + 1718 020f 03 .uleb128 0x3 + 1719 0210 0E .uleb128 0xe + 1720 0211 3A .uleb128 0x3a + 1721 0212 0B .uleb128 0xb + 1722 0213 3B .uleb128 0x3b + 1723 0214 0B .uleb128 0xb + 1724 0215 27 .uleb128 0x27 + 1725 0216 0C .uleb128 0xc + 1726 0217 3C .uleb128 0x3c + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 40 + + + 1727 0218 0C .uleb128 0xc + 1728 0219 01 .uleb128 0x1 + 1729 021a 13 .uleb128 0x13 + 1730 021b 00 .byte 0 + 1731 021c 00 .byte 0 + 1732 021d 2D .uleb128 0x2d + 1733 021e 05 .uleb128 0x5 + 1734 021f 00 .byte 0 + 1735 0220 49 .uleb128 0x49 + 1736 0221 13 .uleb128 0x13 + 1737 0222 00 .byte 0 + 1738 0223 00 .byte 0 + 1739 0224 2E .uleb128 0x2e + 1740 0225 2E .uleb128 0x2e + 1741 0226 01 .byte 0x1 + 1742 0227 3F .uleb128 0x3f + 1743 0228 0C .uleb128 0xc + 1744 0229 03 .uleb128 0x3 + 1745 022a 0E .uleb128 0xe + 1746 022b 27 .uleb128 0x27 + 1747 022c 0C .uleb128 0xc + 1748 022d 49 .uleb128 0x49 + 1749 022e 13 .uleb128 0x13 + 1750 022f 34 .uleb128 0x34 + 1751 0230 0C .uleb128 0xc + 1752 0231 3C .uleb128 0x3c + 1753 0232 0C .uleb128 0xc + 1754 0233 00 .byte 0 + 1755 0234 00 .byte 0 + 1756 0235 00 .byte 0 + 1757 .section .debug_loc,"",%progbits + 1758 .Ldebug_loc0: + 1759 .LLST0: + 1760 0000 00000000 .4byte .LFB8 + 1761 0004 02000000 .4byte .LCFI0 + 1762 0008 0200 .2byte 0x2 + 1763 000a 7D .byte 0x7d + 1764 000b 00 .sleb128 0 + 1765 000c 02000000 .4byte .LCFI0 + 1766 0010 D8010000 .4byte .LFE8 + 1767 0014 0200 .2byte 0x2 + 1768 0016 7D .byte 0x7d + 1769 0017 18 .sleb128 24 + 1770 0018 00000000 .4byte 0 + 1771 001c 00000000 .4byte 0 + 1772 .LLST1: + 1773 0020 50000000 .4byte .LVL4 + 1774 0024 68000000 .4byte .LVL5 + 1775 0028 0100 .2byte 0x1 + 1776 002a 54 .byte 0x54 + 1777 002b 82000000 .4byte .LVL7 + 1778 002f 84000000 .4byte .LVL8 + 1779 0033 0100 .2byte 0x1 + 1780 0035 54 .byte 0x54 + 1781 0036 00000000 .4byte 0 + 1782 003a 00000000 .4byte 0 + 1783 .LLST2: + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 41 + + + 1784 003e 80000000 .4byte .LVL6 + 1785 0042 82000000 .4byte .LVL7 + 1786 0046 0200 .2byte 0x2 + 1787 0048 30 .byte 0x30 + 1788 0049 9F .byte 0x9f + 1789 004a 00000000 .4byte 0 + 1790 004e 00000000 .4byte 0 + 1791 .LLST3: + 1792 0052 8C000000 .4byte .LVL9 + 1793 0056 94000000 .4byte .LVL11 + 1794 005a 0100 .2byte 0x1 + 1795 005c 52 .byte 0x52 + 1796 005d 94000000 .4byte .LVL11 + 1797 0061 A0000000 .4byte .LVL13 + 1798 0065 0800 .2byte 0x8 + 1799 0067 76 .byte 0x76 + 1800 0068 7F .sleb128 -1 + 1801 0069 36 .byte 0x36 + 1802 006a 1E .byte 0x1e + 1803 006b 77 .byte 0x77 + 1804 006c 00 .sleb128 0 + 1805 006d 22 .byte 0x22 + 1806 006e 9F .byte 0x9f + 1807 006f 00000000 .4byte 0 + 1808 0073 00000000 .4byte 0 + 1809 .LLST4: + 1810 0077 8C000000 .4byte .LVL9 + 1811 007b 94000000 .4byte .LVL11 + 1812 007f 0900 .2byte 0x9 + 1813 0081 72 .byte 0x72 + 1814 0082 04 .sleb128 4 + 1815 0083 94 .byte 0x94 + 1816 0084 02 .byte 0x2 + 1817 0085 0A .byte 0xa + 1818 0086 FFFF .2byte 0xffff + 1819 0088 1A .byte 0x1a + 1820 0089 9F .byte 0x9f + 1821 008a 94000000 .4byte .LVL11 + 1822 008e 97000000 .4byte .LVL12-1 + 1823 0092 1000 .2byte 0x10 + 1824 0094 76 .byte 0x76 + 1825 0095 7F .sleb128 -1 + 1826 0096 36 .byte 0x36 + 1827 0097 1E .byte 0x1e + 1828 0098 77 .byte 0x77 + 1829 0099 00 .sleb128 0 + 1830 009a 22 .byte 0x22 + 1831 009b 23 .byte 0x23 + 1832 009c 04 .uleb128 0x4 + 1833 009d 94 .byte 0x94 + 1834 009e 02 .byte 0x2 + 1835 009f 0A .byte 0xa + 1836 00a0 FFFF .2byte 0xffff + 1837 00a2 1A .byte 0x1a + 1838 00a3 9F .byte 0x9f + 1839 00a4 00000000 .4byte 0 + 1840 00a8 00000000 .4byte 0 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 42 + + + 1841 .LLST5: + 1842 00ac 8C000000 .4byte .LVL9 + 1843 00b0 92000000 .4byte .LVL10 + 1844 00b4 0A00 .2byte 0xa + 1845 00b6 76 .byte 0x76 + 1846 00b7 00 .sleb128 0 + 1847 00b8 36 .byte 0x36 + 1848 00b9 1E .byte 0x1e + 1849 00ba 03 .byte 0x3 + 1850 00bb 00000000 .4byte .LANCHOR0 + 1851 00bf 22 .byte 0x22 + 1852 00c0 92000000 .4byte .LVL10 + 1853 00c4 97000000 .4byte .LVL12-1 + 1854 00c8 0A00 .2byte 0xa + 1855 00ca 76 .byte 0x76 + 1856 00cb 7F .sleb128 -1 + 1857 00cc 36 .byte 0x36 + 1858 00cd 1E .byte 0x1e + 1859 00ce 03 .byte 0x3 + 1860 00cf 00000000 .4byte .LANCHOR0 + 1861 00d3 22 .byte 0x22 + 1862 00d4 00000000 .4byte 0 + 1863 00d8 00000000 .4byte 0 + 1864 .LLST6: + 1865 00dc D4000000 .4byte .LVL18 + 1866 00e0 E2000000 .4byte .LVL19 + 1867 00e4 0100 .2byte 0x1 + 1868 00e6 51 .byte 0x51 + 1869 00e7 00000000 .4byte 0 + 1870 00eb 00000000 .4byte 0 + 1871 .LLST7: + 1872 00ef A6000000 .4byte .LVL14 + 1873 00f3 AE000000 .4byte .LVL16 + 1874 00f7 0100 .2byte 0x1 + 1875 00f9 50 .byte 0x50 + 1876 00fa AE000000 .4byte .LVL16 + 1877 00fe D8010000 .4byte .LFE8 + 1878 0102 0100 .2byte 0x1 + 1879 0104 57 .byte 0x57 + 1880 0105 00000000 .4byte 0 + 1881 0109 00000000 .4byte 0 + 1882 .LLST8: + 1883 010d AA000000 .4byte .LVL15 + 1884 0111 B2000000 .4byte .LVL17 + 1885 0115 0100 .2byte 0x1 + 1886 0117 50 .byte 0x50 + 1887 0118 00000000 .4byte 0 + 1888 011c 00000000 .4byte 0 + 1889 .LLST9: + 1890 0120 56010000 .4byte .LVL25 + 1891 0124 5C010000 .4byte .LVL26 + 1892 0128 0100 .2byte 0x1 + 1893 012a 53 .byte 0x53 + 1894 012b 00000000 .4byte 0 + 1895 012f 00000000 .4byte 0 + 1896 .section .debug_aranges,"",%progbits + 1897 0000 24000000 .4byte 0x24 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 43 + + + 1898 0004 0200 .2byte 0x2 + 1899 0006 00000000 .4byte .Ldebug_info0 + 1900 000a 04 .byte 0x4 + 1901 000b 00 .byte 0 + 1902 000c 0000 .2byte 0 + 1903 000e 0000 .2byte 0 + 1904 0010 00000000 .4byte .LFB7 + 1905 0014 0C000000 .4byte .LFE7-.LFB7 + 1906 0018 00000000 .4byte .LFB8 + 1907 001c D8010000 .4byte .LFE8-.LFB8 + 1908 0020 00000000 .4byte 0 + 1909 0024 00000000 .4byte 0 + 1910 .section .debug_ranges,"",%progbits + 1911 .Ldebug_ranges0: + 1912 0000 08000000 .4byte .LBB32 + 1913 0004 16000000 .4byte .LBE32 + 1914 0008 18000000 .4byte .LBB36 + 1915 000c 60000000 .4byte .LBE36 + 1916 0010 62000000 .4byte .LBB37 + 1917 0014 78000000 .4byte .LBE37 + 1918 0018 00000000 .4byte 0 + 1919 001c 00000000 .4byte 0 + 1920 0020 08000000 .4byte .LBB33 + 1921 0024 16000000 .4byte .LBE33 + 1922 0028 18000000 .4byte .LBB34 + 1923 002c 60000000 .4byte .LBE34 + 1924 0030 62000000 .4byte .LBB35 + 1925 0034 78000000 .4byte .LBE35 + 1926 0038 00000000 .4byte 0 + 1927 003c 00000000 .4byte 0 + 1928 0040 84000000 .4byte .LBB38 + 1929 0044 44010000 .4byte .LBE38 + 1930 0048 46010000 .4byte .LBB48 + 1931 004c 48010000 .4byte .LBE48 + 1932 0050 00000000 .4byte 0 + 1933 0054 00000000 .4byte 0 + 1934 0058 A0000000 .4byte .LBB42 + 1935 005c A2000000 .4byte .LBE42 + 1936 0060 A4000000 .4byte .LBB47 + 1937 0064 D6000000 .4byte .LBE47 + 1938 0068 00000000 .4byte 0 + 1939 006c 00000000 .4byte 0 + 1940 0070 A0000000 .4byte .LBB43 + 1941 0074 A2000000 .4byte .LBE43 + 1942 0078 A4000000 .4byte .LBB46 + 1943 007c D6000000 .4byte .LBE46 + 1944 0080 00000000 .4byte 0 + 1945 0084 00000000 .4byte 0 + 1946 0088 A0000000 .4byte .LBB44 + 1947 008c A2000000 .4byte .LBE44 + 1948 0090 A4000000 .4byte .LBB45 + 1949 0094 D0000000 .4byte .LBE45 + 1950 0098 00000000 .4byte 0 + 1951 009c 00000000 .4byte 0 + 1952 00a0 00000000 .4byte .LFB7 + 1953 00a4 0C000000 .4byte .LFE7 + 1954 00a8 00000000 .4byte .LFB8 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 44 + + + 1955 00ac D8010000 .4byte .LFE8 + 1956 00b0 00000000 .4byte 0 + 1957 00b4 00000000 .4byte 0 + 1958 .section .debug_line,"",%progbits + 1959 .Ldebug_line0: + 1960 0000 D2010000 .section .debug_str,"MS",%progbits,1 + 1960 0200E200 + 1960 00000201 + 1960 FB0E0D00 + 1960 01010101 + 1961 .LASF31: + 1962 0000 636F756E .ascii "count\000" + 1962 7400 + 1963 .LASF13: + 1964 0006 75696E74 .ascii "uint16\000" + 1964 313600 + 1965 .LASF30: + 1966 000d 62617365 .ascii "baseAddr\000" + 1966 41646472 + 1966 00 + 1967 .LASF11: + 1968 0016 73697A65 .ascii "size_t\000" + 1968 5F7400 + 1969 .LASF22: + 1970 001d 4379436C .ascii "CyClockStartupError\000" + 1970 6F636B53 + 1970 74617274 + 1970 75704572 + 1970 726F7200 + 1971 .LASF29: + 1972 0031 64617461 .ascii "data_table\000" + 1972 5F746162 + 1972 6C6500 + 1973 .LASF6: + 1974 003c 6C6F6E67 .ascii "long long unsigned int\000" + 1974 206C6F6E + 1974 6720756E + 1974 7369676E + 1974 65642069 + 1975 .LASF28: + 1976 0053 61646472 .ascii "addr_table\000" + 1976 5F746162 + 1976 6C6500 + 1977 .LASF47: + 1978 005e 63795F63 .ascii "cy_cfg_data_table\000" + 1978 66675F64 + 1978 6174615F + 1978 7461626C + 1978 6500 + 1979 .LASF36: + 1980 0070 416E616C .ascii "AnalogSetDefault\000" + 1980 6F675365 + 1980 74446566 + 1980 61756C74 + 1980 00 + 1981 .LASF5: + 1982 0081 6C6F6E67 .ascii "long long int\000" + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 45 + + + 1982 206C6F6E + 1982 6720696E + 1982 7400 + 1983 .LASF0: + 1984 008f 7369676E .ascii "signed char\000" + 1984 65642063 + 1984 68617200 + 1985 .LASF46: + 1986 009b 63795F63 .ascii "cy_cfg_addr_table\000" + 1986 66675F61 + 1986 6464725F + 1986 7461626C + 1986 6500 + 1987 .LASF27: + 1988 00ad 6366675F .ascii "cfg_write_bytes32\000" + 1988 77726974 + 1988 655F6279 + 1988 74657333 + 1988 3200 + 1989 .LASF32: + 1990 00bf 436C6F63 .ascii "ClockSetup\000" + 1990 6B536574 + 1990 757000 + 1991 .LASF24: + 1992 00ca 6572726F .ascii "errorCode\000" + 1992 72436F64 + 1992 6500 + 1993 .LASF44: + 1994 00d4 42535F49 .ascii "BS_IOPINS0_4_VAL\000" + 1994 4F50494E + 1994 53305F34 + 1994 5F56414C + 1994 00 + 1995 .LASF7: + 1996 00e5 6C6F6E67 .ascii "long int\000" + 1996 20696E74 + 1996 00 + 1997 .LASF18: + 1998 00ee 72656731 .ascii "reg16\000" + 1998 3600 + 1999 .LASF12: + 2000 00f4 75696E74 .ascii "uint8\000" + 2000 3800 + 2001 .LASF16: + 2002 00fa 646F7562 .ascii "double\000" + 2002 6C6500 + 2003 .LASF35: + 2004 0101 43594D45 .ascii "CYMEMZERO\000" + 2004 4D5A4552 + 2004 4F00 + 2005 .LASF14: + 2006 010b 75696E74 .ascii "uint32\000" + 2006 333200 + 2007 .LASF40: + 2008 0112 72656756 .ascii "regValue\000" + 2008 616C7565 + 2008 00 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 46 + + + 2009 .LASF20: + 2010 011b 76616C75 .ascii "value\000" + 2010 6500 + 2011 .LASF4: + 2012 0121 756E7369 .ascii "unsigned int\000" + 2012 676E6564 + 2012 20696E74 + 2012 00 + 2013 .LASF53: + 2014 012e 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\cyfitter_cfg.c\000" + 2014 6E657261 + 2014 7465645F + 2014 536F7572 + 2014 63655C50 + 2015 .LASF9: + 2016 0156 6C6F6E67 .ascii "long unsigned int\000" + 2016 20756E73 + 2016 69676E65 + 2016 6420696E + 2016 7400 + 2017 .LASF33: + 2018 0168 74696D65 .ascii "timeout\000" + 2018 6F757400 + 2019 .LASF49: + 2020 0170 73697A65 .ascii "size\000" + 2020 00 + 2021 .LASF3: + 2022 0175 73686F72 .ascii "short unsigned int\000" + 2022 7420756E + 2022 7369676E + 2022 65642069 + 2022 6E7400 + 2023 .LASF45: + 2024 0188 42535F49 .ascii "BS_IOPINS0_6_VAL\000" 2024 4F50494E - 2024 53305F30 + 2024 53305F36 2024 5F56414C 2024 00 - 2025 .LASF34: - 2026 0291 706C6C4C .ascii "pllLock\000" - 2026 6F636B00 - 2027 .LASF42: - 2028 0299 42535F49 .ascii "BS_IOPINS0_8_VAL\000" - 2028 4F50494E - 2028 53305F38 - 2028 5F56414C - 2028 00 - 2029 .LASF21: - 2030 02aa 63795F63 .ascii "cy_cfg_addrvalue_t\000" - 2030 66675F61 - 2030 64647276 - 2030 616C7565 - 2030 5F7400 - 2031 .LASF10: - 2032 02bd 63686172 .ascii "char\000" - 2032 00 - 2033 .LASF38: - 2034 02c2 53657441 .ascii "SetAnalogRoutingPumps\000" - 2034 6E616C6F - 2034 67526F75 - 2034 74696E67 - 2034 50756D70 - 2035 .LASF19: - 2036 02d8 6F666673 .ascii "offset\000" - 2036 657400 - 2037 .LASF54: - 2038 02df 656E6162 .ascii "enabled\000" - 2038 6C656400 - 2039 .LASF56: - 2040 02e7 6D656D73 .ascii "memset\000" - 2040 657400 - 2041 .LASF26: - 2042 02ee 4359434F .ascii "CYCONFIGCPY\000" - 2042 4E464947 - 2042 43505900 - 2043 .LASF47: - 2044 02fa 61646472 .ascii "address\000" - 2044 65737300 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuuLLS2.s page 48 - - - 2045 .LASF39: - 2046 0302 63796669 .ascii "cyfitter_cfg\000" - 2046 74746572 - 2046 5F636667 - 2046 00 - 2047 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br + 2025 .LASF54: + 2026 0199 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" + 2026 43534932 + 2026 53445C73 + 2026 6F667477 + 2026 6172655C + 2027 01c8 6E00 .ascii "n\000" + 2028 .LASF23: + 2029 01ca 4359434F .ascii "CYCONFIGCPYCODE\000" + 2029 4E464947 + 2029 43505943 + 2029 4F444500 + 2030 .LASF8: + 2031 01da 73697A65 .ascii "sizetype\000" + 2031 74797065 + 2031 00 + 2032 .LASF37: + 2033 01e3 62675F78 .ascii "bg_xover_inl_trim\000" + 2033 6F766572 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 47 + + + 2033 5F696E6C + 2033 5F747269 + 2033 6D00 + 2034 .LASF50: + 2035 01f5 6366675F .ascii "cfg_memset_t\000" + 2035 6D656D73 + 2035 65745F74 + 2035 00 + 2036 .LASF51: + 2037 0202 6366675F .ascii "cfg_memset_list\000" + 2037 6D656D73 + 2037 65745F6C + 2037 69737400 + 2038 .LASF43: + 2039 0212 42535F49 .ascii "BS_IOPINS0_3_VAL\000" + 2039 4F50494E + 2039 53305F33 + 2039 5F56414C + 2039 00 + 2040 .LASF25: + 2041 0223 64657374 .ascii "dest\000" + 2041 00 + 2042 .LASF15: + 2043 0228 666C6F61 .ascii "float\000" + 2043 7400 + 2044 .LASF56: + 2045 022e 43794465 .ascii "CyDelayCycles\000" + 2045 6C617943 + 2045 79636C65 + 2045 7300 + 2046 .LASF52: + 2047 023c 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" + 2047 4320342E + 2047 372E3320 + 2047 32303133 + 2047 30333132 + 2048 026f 616E6368 .ascii "anch revision 196615]\000" + 2048 20726576 + 2048 6973696F + 2048 6E203139 + 2048 36363135 + 2049 .LASF17: + 2050 0285 72656738 .ascii "reg8\000" + 2050 00 + 2051 .LASF1: + 2052 028a 756E7369 .ascii "unsigned char\000" + 2052 676E6564 + 2052 20636861 + 2052 7200 + 2053 .LASF2: + 2054 0298 73686F72 .ascii "short int\000" + 2054 7420696E + 2054 7400 + 2055 .LASF41: + 2056 02a2 42535F49 .ascii "BS_IOPINS0_0_VAL\000" + 2056 4F50494E + 2056 53305F30 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 48 + + + 2056 5F56414C + 2056 00 + 2057 .LASF34: + 2058 02b3 706C6C4C .ascii "pllLock\000" + 2058 6F636B00 + 2059 .LASF42: + 2060 02bb 42535F49 .ascii "BS_IOPINS0_8_VAL\000" + 2060 4F50494E + 2060 53305F38 + 2060 5F56414C + 2060 00 + 2061 .LASF21: + 2062 02cc 63795F63 .ascii "cy_cfg_addrvalue_t\000" + 2062 66675F61 + 2062 64647276 + 2062 616C7565 + 2062 5F7400 + 2063 .LASF10: + 2064 02df 63686172 .ascii "char\000" + 2064 00 + 2065 .LASF38: + 2066 02e4 53657441 .ascii "SetAnalogRoutingPumps\000" + 2066 6E616C6F + 2066 67526F75 + 2066 74696E67 + 2066 50756D70 + 2067 .LASF19: + 2068 02fa 6F666673 .ascii "offset\000" + 2068 657400 + 2069 .LASF55: + 2070 0301 656E6162 .ascii "enabled\000" + 2070 6C656400 + 2071 .LASF57: + 2072 0309 6D656D73 .ascii "memset\000" + 2072 657400 + 2073 .LASF26: + 2074 0310 4359434F .ascii "CYCONFIGCPY\000" + 2074 4E464947 + 2074 43505900 + 2075 .LASF48: + 2076 031c 61646472 .ascii "address\000" + 2076 65737300 + 2077 .LASF39: + 2078 0324 63796669 .ascii "cyfitter_cfg\000" + 2078 74746572 + 2078 5F636667 + 2078 00 + 2079 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/cyfitter_cfg.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/cyfitter_cfg.o index 370e05afae44ef19150398e6d23e14b001c61227..80b2555ee90ad30b297df417333c00f53baf6b96 100755 GIT binary patch delta 2705 zcmYk73v3is6o&7)GqYWG``B&w(cO02*-mNEwoA7yP!X{OY+8zJrG}SaTd1|D$O<)7 z5w~E82tKG+5F^H-#vqCKs2T)gLV_>i1C1d_RIIOv!K6mPstBGlJ&jH>_q*pm=brnX z*;==weuoK*2clNw#%3sb_S|5{-gA9-I?M&dH_Q(woyqd#wBDu7O9wjquy9~~p*zu- zNQjce?|tj$5A3xf4GBjS{&uVtQBOBaeRS)kKQ3N!#(w)$SfPfxf#E4rYUUO7&Ki-z zOh)giYOEiTTD-~XN$;IAQYT$Wt#|U=*&`l3)~qLUyO(u)+OKa9H zHm@;+kakUn8CZcB2=RpaSVo$*p(&-Y+eX@*sB5~h>h>NX^|UBj(rIkMmeQFvgPD`p_%|VnrLuy2?O?^kgd5RH!D5e&bW2sKs3DJH{7sB@pby5vSv2JJ&W3cZqDbwH! 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zcmew%{X%+z0;9=BMGi(r@yS|@28{fZqZ!i}9VQ=Q3}Q6jEXrig%$1o}Vr&#&!VqpX zIi6K+ax3fh&DLxW85uh!%X0WLPMDm_Q4S=Z0@)iTn{xUy9+=z;Bri<9%BjuhIhm15 znXzrMDwjIbch<>%TxyIulS{eO8E;IU%cag5!N$OFYw|^Q;mLQn1Q=x|zXgir@GvmQ OOg7{e-)z8rf(ZaO#4jcQ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.c b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.c new file mode 100755 index 00000000..a5aa27ee --- /dev/null +++ b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.c @@ -0,0 +1,141 @@ +/******************************************************************************* +* File Name: SD_PULLUP.c +* Version 1.90 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SD_PULLUP.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + SD_PULLUP__PORT == 15 && ((SD_PULLUP__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: SD_PULLUP_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void SD_PULLUP_Write(uint8 value) +{ + uint8 staticBits = (SD_PULLUP_DR & (uint8)(~SD_PULLUP_MASK)); + SD_PULLUP_DR = staticBits | ((uint8)(value << SD_PULLUP_SHIFT) & SD_PULLUP_MASK); +} + + +/******************************************************************************* +* Function Name: SD_PULLUP_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to this drive mode. +* +* Return: +* None +* +*******************************************************************************/ +void SD_PULLUP_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(SD_PULLUP_0, mode); + CyPins_SetPinDriveMode(SD_PULLUP_1, mode); + CyPins_SetPinDriveMode(SD_PULLUP_2, mode); + CyPins_SetPinDriveMode(SD_PULLUP_3, mode); + CyPins_SetPinDriveMode(SD_PULLUP_4, mode); +} + + +/******************************************************************************* +* Function Name: SD_PULLUP_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro SD_PULLUP_ReadPS calls this function. +* +*******************************************************************************/ +uint8 SD_PULLUP_Read(void) +{ + return (SD_PULLUP_PS & SD_PULLUP_MASK) >> SD_PULLUP_SHIFT; +} + + +/******************************************************************************* +* Function Name: SD_PULLUP_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 SD_PULLUP_ReadDataReg(void) +{ + return (SD_PULLUP_DR & SD_PULLUP_MASK) >> SD_PULLUP_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(SD_PULLUP_INTSTAT) + + /******************************************************************************* + * Function Name: SD_PULLUP_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 SD_PULLUP_ClearInterrupt(void) + { + return (SD_PULLUP_INTSTAT & SD_PULLUP_MASK) >> SD_PULLUP_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.h b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.h new file mode 100755 index 00000000..07394f01 --- /dev/null +++ b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: SD_PULLUP.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_PULLUP_H) /* Pins SD_PULLUP_H */ +#define CY_PINS_SD_PULLUP_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SD_PULLUP_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SD_PULLUP__PORT == 15 && ((SD_PULLUP__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void SD_PULLUP_Write(uint8 value) ; +void SD_PULLUP_SetDriveMode(uint8 mode) ; +uint8 SD_PULLUP_ReadDataReg(void) ; +uint8 SD_PULLUP_Read(void) ; +uint8 SD_PULLUP_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define SD_PULLUP_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define SD_PULLUP_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define SD_PULLUP_DM_RES_UP PIN_DM_RES_UP +#define SD_PULLUP_DM_RES_DWN PIN_DM_RES_DWN +#define SD_PULLUP_DM_OD_LO PIN_DM_OD_LO +#define SD_PULLUP_DM_OD_HI PIN_DM_OD_HI +#define SD_PULLUP_DM_STRONG PIN_DM_STRONG +#define SD_PULLUP_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define SD_PULLUP_MASK SD_PULLUP__MASK +#define SD_PULLUP_SHIFT SD_PULLUP__SHIFT +#define SD_PULLUP_WIDTH 5u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SD_PULLUP_PS (* (reg8 *) SD_PULLUP__PS) +/* Data Register */ +#define SD_PULLUP_DR (* (reg8 *) SD_PULLUP__DR) +/* Port Number */ +#define SD_PULLUP_PRT_NUM (* (reg8 *) SD_PULLUP__PRT) +/* Connect to Analog Globals */ +#define SD_PULLUP_AG (* (reg8 *) SD_PULLUP__AG) +/* Analog MUX bux enable */ +#define SD_PULLUP_AMUX (* (reg8 *) SD_PULLUP__AMUX) +/* Bidirectional Enable */ +#define SD_PULLUP_BIE (* (reg8 *) SD_PULLUP__BIE) +/* Bit-mask for Aliased Register Access */ +#define SD_PULLUP_BIT_MASK (* (reg8 *) SD_PULLUP__BIT_MASK) +/* Bypass Enable */ +#define SD_PULLUP_BYP (* (reg8 *) SD_PULLUP__BYP) +/* Port wide control signals */ +#define SD_PULLUP_CTL (* (reg8 *) SD_PULLUP__CTL) +/* Drive Modes */ +#define SD_PULLUP_DM0 (* (reg8 *) SD_PULLUP__DM0) +#define SD_PULLUP_DM1 (* (reg8 *) SD_PULLUP__DM1) +#define SD_PULLUP_DM2 (* (reg8 *) SD_PULLUP__DM2) +/* Input Buffer Disable Override */ +#define SD_PULLUP_INP_DIS (* (reg8 *) SD_PULLUP__INP_DIS) +/* LCD Common or Segment Drive */ +#define SD_PULLUP_LCD_COM_SEG (* (reg8 *) SD_PULLUP__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SD_PULLUP_LCD_EN (* (reg8 *) SD_PULLUP__LCD_EN) +/* Slew Rate Control */ +#define SD_PULLUP_SLW (* (reg8 *) SD_PULLUP__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SD_PULLUP_PRTDSI__CAPS_SEL (* (reg8 *) SD_PULLUP__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SD_PULLUP_PRTDSI__DBL_SYNC_IN (* (reg8 *) SD_PULLUP__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SD_PULLUP_PRTDSI__OE_SEL0 (* (reg8 *) SD_PULLUP__PRTDSI__OE_SEL0) +#define SD_PULLUP_PRTDSI__OE_SEL1 (* (reg8 *) SD_PULLUP__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SD_PULLUP_PRTDSI__OUT_SEL0 (* (reg8 *) SD_PULLUP__PRTDSI__OUT_SEL0) +#define SD_PULLUP_PRTDSI__OUT_SEL1 (* (reg8 *) SD_PULLUP__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SD_PULLUP_PRTDSI__SYNC_OUT (* (reg8 *) SD_PULLUP__PRTDSI__SYNC_OUT) + + +#if defined(SD_PULLUP__INTSTAT) /* Interrupt Registers */ + + #define SD_PULLUP_INTSTAT (* (reg8 *) SD_PULLUP__INTSTAT) + #define SD_PULLUP_SNAP (* (reg8 *) SD_PULLUP__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SD_PULLUP_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP_aliases.h b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP_aliases.h new file mode 100755 index 00000000..bf8bd1df --- /dev/null +++ b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP_aliases.h @@ -0,0 +1,36 @@ +/******************************************************************************* +* File Name: SD_PULLUP.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_PULLUP_ALIASES_H) /* Pins SD_PULLUP_ALIASES_H */ +#define CY_PINS_SD_PULLUP_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SD_PULLUP_0 SD_PULLUP__0__PC +#define SD_PULLUP_1 SD_PULLUP__1__PC +#define SD_PULLUP_2 SD_PULLUP__2__PC +#define SD_PULLUP_3 SD_PULLUP__3__PC +#define SD_PULLUP_4 SD_PULLUP__4__PC + +#endif /* End Pins SD_PULLUP_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h old mode 100644 new mode 100755 index 8263e30a..5f1b198d --- a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h +++ b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h @@ -1,7 +1,7 @@ /******************************************************************************* * FILENAME: cydevice.h * OBSOLETE: Do not use this file. Use the _trm version instead. -* PSoC Creator 3.0 +* PSoC Creator 3.0 Component Pack 7 * * DESCRIPTION: * This file provides all of the address values for the entire PSoC device. diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h old mode 100644 new mode 100755 index 08d77aa1..e2c0687f --- a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h +++ b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h @@ -1,7 +1,7 @@ /******************************************************************************* * FILENAME: cydevice_trm.h * -* PSoC Creator 3.0 +* PSoC Creator 3.0 Component Pack 7 * * DESCRIPTION: * This file provides all of the address values for the entire PSoC device. diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu.inc b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu.inc old mode 100644 new mode 100755 index 833c2b6f..1776ef90 --- a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu.inc +++ b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu.inc @@ -1,7 +1,7 @@ /******************************************************************************* * FILENAME: cydevicegnu.inc * OBSOLETE: Do not use this file. Use the _trm version instead. -* PSoC Creator 3.0 +* PSoC Creator 3.0 Component Pack 7 * * DESCRIPTION: * This file provides all of the address values for the entire PSoC device. diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc old mode 100644 new mode 100755 index ffbe68b0..3c24869c --- a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc +++ b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc @@ -1,7 +1,7 @@ /******************************************************************************* * FILENAME: cydevicegnu_trm.inc * -* PSoC Creator 3.0 +* PSoC Creator 3.0 Component Pack 7 * * DESCRIPTION: * This file provides all of the address values for the entire PSoC device. diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar.inc b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar.inc old mode 100644 new mode 100755 index 8556d0a3..e4f1a443 --- a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar.inc +++ b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar.inc @@ -1,7 +1,7 @@ ; ; FILENAME: cydeviceiar.inc ; OBSOLETE: Do not use this file. Use the _trm version instead. -; PSoC Creator 3.0 +; PSoC Creator 3.0 Component Pack 7 ; ; DESCRIPTION: ; This file provides all of the address values for the entire PSoC device. diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc old mode 100644 new mode 100755 index ea4e01d4..ebd1b1dc --- a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc +++ b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc @@ -1,7 +1,7 @@ ; ; FILENAME: cydeviceiar_trm.inc ; -; PSoC Creator 3.0 +; PSoC Creator 3.0 Component Pack 7 ; ; DESCRIPTION: ; This file provides all of the address values for the entire PSoC device. diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv.inc b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv.inc old mode 100644 new mode 100755 index 4c8a5376..4ed74edd --- a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv.inc +++ b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv.inc @@ -1,7 +1,7 @@ ; ; FILENAME: cydevicerv.inc ; OBSOLETE: Do not use this file. Use the _trm version instead. -; PSoC Creator 3.0 +; PSoC Creator 3.0 Component Pack 7 ; ; DESCRIPTION: ; This file provides all of the address values for the entire PSoC device. diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc old mode 100644 new mode 100755 index 232c2fc0..d4d800c6 --- a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc +++ b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc @@ -1,7 +1,7 @@ ; ; FILENAME: cydevicerv_trm.inc ; -; PSoC Creator 3.0 +; PSoC Creator 3.0 Component Pack 7 ; ; DESCRIPTION: ; This file provides all of the address values for the entire PSoC device. diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h old mode 100644 new mode 100755 index 8c2b1e86..c8ba6468 --- a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h +++ b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -507,6 +507,54 @@ #define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +/* SD_PULLUP */ +#define SD_PULLUP__0__MASK 0x02u +#define SD_PULLUP__0__PC CYREG_PRT3_PC1 +#define SD_PULLUP__0__PORT 3u +#define SD_PULLUP__0__SHIFT 1 +#define SD_PULLUP__1__MASK 0x04u +#define SD_PULLUP__1__PC CYREG_PRT3_PC2 +#define SD_PULLUP__1__PORT 3u +#define SD_PULLUP__1__SHIFT 2 +#define SD_PULLUP__2__MASK 0x08u +#define SD_PULLUP__2__PC CYREG_PRT3_PC3 +#define SD_PULLUP__2__PORT 3u +#define SD_PULLUP__2__SHIFT 3 +#define SD_PULLUP__3__MASK 0x10u +#define SD_PULLUP__3__PC CYREG_PRT3_PC4 +#define SD_PULLUP__3__PORT 3u +#define SD_PULLUP__3__SHIFT 4 +#define SD_PULLUP__4__MASK 0x20u +#define SD_PULLUP__4__PC CYREG_PRT3_PC5 +#define SD_PULLUP__4__PORT 3u +#define SD_PULLUP__4__SHIFT 5 +#define SD_PULLUP__AG CYREG_PRT3_AG +#define SD_PULLUP__AMUX CYREG_PRT3_AMUX +#define SD_PULLUP__BIE CYREG_PRT3_BIE +#define SD_PULLUP__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_PULLUP__BYP CYREG_PRT3_BYP +#define SD_PULLUP__CTL CYREG_PRT3_CTL +#define SD_PULLUP__DM0 CYREG_PRT3_DM0 +#define SD_PULLUP__DM1 CYREG_PRT3_DM1 +#define SD_PULLUP__DM2 CYREG_PRT3_DM2 +#define SD_PULLUP__DR CYREG_PRT3_DR +#define SD_PULLUP__INP_DIS CYREG_PRT3_INP_DIS +#define SD_PULLUP__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_PULLUP__LCD_EN CYREG_PRT3_LCD_EN +#define SD_PULLUP__MASK 0x3Eu +#define SD_PULLUP__PORT 3u +#define SD_PULLUP__PRT CYREG_PRT3_PRT +#define SD_PULLUP__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_PULLUP__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_PULLUP__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_PULLUP__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_PULLUP__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_PULLUP__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_PULLUP__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_PULLUP__PS CYREG_PRT3_PS +#define SD_PULLUP__SHIFT 1 +#define SD_PULLUP__SLW CYREG_PRT3_SLW + /* USBFS_USB */ #define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG #define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c old mode 100644 new mode 100755 index 090e521d..c15b7b65 --- a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c +++ b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -1,6 +1,6 @@ /******************************************************************************* * FILENAME: cyfitter_cfg.c -* PSoC Creator 3.0 +* PSoC Creator 3.0 Component Pack 7 * * Description: * This file is automatically generated by PSoC Creator with device @@ -311,6 +311,10 @@ void cyfitter_cfg(void) static const uint8 CYCODE BS_IOPINS0_8_VAL[] = { 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xC0u, 0x00u}; + /* IOPINS0_3 Address: CYREG_PRT3_DM0 Size (bytes): 8 */ + static const uint8 CYCODE BS_IOPINS0_3_VAL[] = { + 0x00u, 0x3Eu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + /* IOPINS0_4 Address: CYREG_PRT4_DM0 Size (bytes): 8 */ static const uint8 CYCODE BS_IOPINS0_4_VAL[] = { 0x00u, 0xFCu, 0xFCu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; @@ -335,7 +339,7 @@ void cyfitter_cfg(void) { static const uint32 CYCODE cy_cfg_addr_table[] = { 0x40004501u, /* Base address: 0x40004500 Count: 1 */ - 0x40005201u, /* Base address: 0x40005200 Count: 1 */ + 0x40005202u, /* Base address: 0x40005200 Count: 2 */ 0x40011701u, /* Base address: 0x40011700 Count: 1 */ 0x40011901u, /* Base address: 0x40011900 Count: 1 */ 0x40014003u, /* Base address: 0x40014000 Count: 3 */ @@ -350,6 +354,7 @@ void cyfitter_cfg(void) static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x7Eu, 0x02u}, + {0x1Cu, 0x3Eu}, {0x7Cu, 0x40u}, {0xEEu, 0x0Au}, {0xEEu, 0x0Au}, @@ -382,7 +387,7 @@ void cyfitter_cfg(void) static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ - {(void CYFAR *)(CYREG_PRT1_DR), 48u}, + {(void CYFAR *)(CYREG_PRT1_DR), 32u}, {(void CYFAR *)(CYREG_PRT5_DR), 16u}, {(void CYFAR *)(CYREG_PRT12_DR), 16u}, {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u}, @@ -415,6 +420,7 @@ void cyfitter_cfg(void) /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT0_DM0), (const void CYCODE *)(BS_IOPINS0_0_VAL), 8u); CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT15_DR), (const void CYCODE *)(BS_IOPINS0_8_VAL), 10u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT3_DM0), (const void CYCODE *)(BS_IOPINS0_3_VAL), 8u); CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT4_DM0), (const void CYCODE *)(BS_IOPINS0_4_VAL), 8u); CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT6_DM0), (const void CYCODE *)(BS_IOPINS0_6_VAL), 8u); diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h old mode 100644 new mode 100755 index 02880d0e..9481fd38 --- a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h +++ b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h @@ -1,6 +1,6 @@ /******************************************************************************* * FILENAME: cyfitter_cfg.h -* PSoC Creator 3.0 +* PSoC Creator 3.0 Component Pack 7 * * Description: * This file is automatically generated by PSoC Creator. diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfittergnu.inc old mode 100644 new mode 100755 index 95fa17a3..e370ffad --- a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfittergnu.inc +++ b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -507,6 +507,54 @@ .set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +/* SD_PULLUP */ +.set SD_PULLUP__0__MASK, 0x02 +.set SD_PULLUP__0__PC, CYREG_PRT3_PC1 +.set SD_PULLUP__0__PORT, 3 +.set SD_PULLUP__0__SHIFT, 1 +.set SD_PULLUP__1__MASK, 0x04 +.set SD_PULLUP__1__PC, CYREG_PRT3_PC2 +.set SD_PULLUP__1__PORT, 3 +.set SD_PULLUP__1__SHIFT, 2 +.set SD_PULLUP__2__MASK, 0x08 +.set SD_PULLUP__2__PC, CYREG_PRT3_PC3 +.set SD_PULLUP__2__PORT, 3 +.set SD_PULLUP__2__SHIFT, 3 +.set SD_PULLUP__3__MASK, 0x10 +.set SD_PULLUP__3__PC, CYREG_PRT3_PC4 +.set SD_PULLUP__3__PORT, 3 +.set SD_PULLUP__3__SHIFT, 4 +.set SD_PULLUP__4__MASK, 0x20 +.set SD_PULLUP__4__PC, CYREG_PRT3_PC5 +.set SD_PULLUP__4__PORT, 3 +.set SD_PULLUP__4__SHIFT, 5 +.set SD_PULLUP__AG, CYREG_PRT3_AG +.set SD_PULLUP__AMUX, CYREG_PRT3_AMUX +.set SD_PULLUP__BIE, CYREG_PRT3_BIE +.set SD_PULLUP__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_PULLUP__BYP, CYREG_PRT3_BYP +.set SD_PULLUP__CTL, CYREG_PRT3_CTL +.set SD_PULLUP__DM0, CYREG_PRT3_DM0 +.set SD_PULLUP__DM1, CYREG_PRT3_DM1 +.set SD_PULLUP__DM2, CYREG_PRT3_DM2 +.set SD_PULLUP__DR, CYREG_PRT3_DR +.set SD_PULLUP__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_PULLUP__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_PULLUP__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_PULLUP__MASK, 0x3E +.set SD_PULLUP__PORT, 3 +.set SD_PULLUP__PRT, CYREG_PRT3_PRT +.set SD_PULLUP__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_PULLUP__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_PULLUP__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_PULLUP__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_PULLUP__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_PULLUP__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_PULLUP__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_PULLUP__PS, CYREG_PRT3_PS +.set SD_PULLUP__SHIFT, 1 +.set SD_PULLUP__SLW, CYREG_PRT3_SLW + /* USBFS_USB */ .set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG .set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitteriar.inc old mode 100644 new mode 100755 index d0d0f630..fb84c624 --- a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitteriar.inc +++ b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitteriar.inc @@ -507,6 +507,54 @@ USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +/* SD_PULLUP */ +SD_PULLUP__0__MASK EQU 0x02 +SD_PULLUP__0__PC EQU CYREG_PRT3_PC1 +SD_PULLUP__0__PORT EQU 3 +SD_PULLUP__0__SHIFT EQU 1 +SD_PULLUP__1__MASK EQU 0x04 +SD_PULLUP__1__PC EQU CYREG_PRT3_PC2 +SD_PULLUP__1__PORT EQU 3 +SD_PULLUP__1__SHIFT EQU 2 +SD_PULLUP__2__MASK EQU 0x08 +SD_PULLUP__2__PC EQU CYREG_PRT3_PC3 +SD_PULLUP__2__PORT EQU 3 +SD_PULLUP__2__SHIFT EQU 3 +SD_PULLUP__3__MASK EQU 0x10 +SD_PULLUP__3__PC EQU CYREG_PRT3_PC4 +SD_PULLUP__3__PORT EQU 3 +SD_PULLUP__3__SHIFT EQU 4 +SD_PULLUP__4__MASK EQU 0x20 +SD_PULLUP__4__PC EQU CYREG_PRT3_PC5 +SD_PULLUP__4__PORT EQU 3 +SD_PULLUP__4__SHIFT EQU 5 +SD_PULLUP__AG EQU CYREG_PRT3_AG +SD_PULLUP__AMUX EQU CYREG_PRT3_AMUX +SD_PULLUP__BIE EQU CYREG_PRT3_BIE +SD_PULLUP__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_PULLUP__BYP EQU CYREG_PRT3_BYP +SD_PULLUP__CTL EQU CYREG_PRT3_CTL +SD_PULLUP__DM0 EQU CYREG_PRT3_DM0 +SD_PULLUP__DM1 EQU CYREG_PRT3_DM1 +SD_PULLUP__DM2 EQU CYREG_PRT3_DM2 +SD_PULLUP__DR EQU CYREG_PRT3_DR +SD_PULLUP__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_PULLUP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_PULLUP__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_PULLUP__MASK EQU 0x3E +SD_PULLUP__PORT EQU 3 +SD_PULLUP__PRT EQU CYREG_PRT3_PRT +SD_PULLUP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_PULLUP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_PULLUP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_PULLUP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_PULLUP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_PULLUP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_PULLUP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_PULLUP__PS EQU CYREG_PRT3_PS +SD_PULLUP__SHIFT EQU 1 +SD_PULLUP__SLW EQU CYREG_PRT3_SLW + /* USBFS_USB */ USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitterrv.inc old mode 100644 new mode 100755 index bc000e20..2f81aaf1 --- a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitterrv.inc +++ b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -507,6 +507,54 @@ USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +; SD_PULLUP +SD_PULLUP__0__MASK EQU 0x02 +SD_PULLUP__0__PC EQU CYREG_PRT3_PC1 +SD_PULLUP__0__PORT EQU 3 +SD_PULLUP__0__SHIFT EQU 1 +SD_PULLUP__1__MASK EQU 0x04 +SD_PULLUP__1__PC EQU CYREG_PRT3_PC2 +SD_PULLUP__1__PORT EQU 3 +SD_PULLUP__1__SHIFT EQU 2 +SD_PULLUP__2__MASK EQU 0x08 +SD_PULLUP__2__PC EQU CYREG_PRT3_PC3 +SD_PULLUP__2__PORT EQU 3 +SD_PULLUP__2__SHIFT EQU 3 +SD_PULLUP__3__MASK EQU 0x10 +SD_PULLUP__3__PC EQU CYREG_PRT3_PC4 +SD_PULLUP__3__PORT EQU 3 +SD_PULLUP__3__SHIFT EQU 4 +SD_PULLUP__4__MASK EQU 0x20 +SD_PULLUP__4__PC EQU CYREG_PRT3_PC5 +SD_PULLUP__4__PORT EQU 3 +SD_PULLUP__4__SHIFT EQU 5 +SD_PULLUP__AG EQU CYREG_PRT3_AG +SD_PULLUP__AMUX EQU CYREG_PRT3_AMUX +SD_PULLUP__BIE EQU CYREG_PRT3_BIE +SD_PULLUP__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_PULLUP__BYP EQU CYREG_PRT3_BYP +SD_PULLUP__CTL EQU CYREG_PRT3_CTL +SD_PULLUP__DM0 EQU CYREG_PRT3_DM0 +SD_PULLUP__DM1 EQU CYREG_PRT3_DM1 +SD_PULLUP__DM2 EQU CYREG_PRT3_DM2 +SD_PULLUP__DR EQU CYREG_PRT3_DR +SD_PULLUP__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_PULLUP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_PULLUP__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_PULLUP__MASK EQU 0x3E +SD_PULLUP__PORT EQU 3 +SD_PULLUP__PRT EQU CYREG_PRT3_PRT +SD_PULLUP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_PULLUP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_PULLUP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_PULLUP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_PULLUP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_PULLUP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_PULLUP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_PULLUP__PS EQU CYREG_PRT3_PS +SD_PULLUP__SHIFT EQU 1 +SD_PULLUP__SLW EQU CYREG_PRT3_SLW + ; USBFS_USB USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c old mode 100644 new mode 100755 index 8310348e..00c7240a --- a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c +++ b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c @@ -1,7 +1,7 @@ /******************************************************************************* * FILENAME: cymetadata.c * -* PSoC Creator 3.0 +* PSoC Creator 3.0 Component Pack 7 * * DESCRIPTION: * This file defines all extra memory spaces that need to be included. @@ -55,7 +55,7 @@ __attribute__ ((__section__(".cycustnvl"), used)) #error "Unsupported toolchain" #endif const uint8 cy_meta_custnvl[] = { - 0x00u, 0x00u, 0x40u, 0x05u + 0x80u, 0x00u, 0x40u, 0x05u }; #if defined(__GNUC__) || defined(__ARMCC_VERSION) diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/project.h old mode 100644 new mode 100755 index c454b9a0..0027c911 --- a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/project.h +++ b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/project.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: project.h - * PSoC Creator 3.0 + * PSoC Creator 3.0 Component Pack 7 * * Description: * This file is automatically generated by PSoC Creator and should not @@ -29,6 +29,8 @@ #include #include #include +#include +#include #include #include #include diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoCCreatorExportIDE.xml b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoCCreatorExportIDE.xml index c0600231..75099ceb 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoCCreatorExportIDE.xml +++ b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoCCreatorExportIDE.xml @@ -18,7 +18,7 @@ - + USB_Bootloader.svd @@ -27,13 +27,13 @@ .\Generated_Source\PSoC5\Cm3Iar.icf - - + + .\main.c - - + + .\Generated_Source\PSoC5\cyfitter_cfg.h .\Generated_Source\PSoC5\cyfitter_cfg.c .\Generated_Source\PSoC5\cymetadata.c @@ -102,47 +102,50 @@ .\Generated_Source\PSoC5\core_cmInstr.h .\Generated_Source\PSoC5\CyBootAsmIar.s .\Generated_Source\PSoC5\project.h + .\Generated_Source\PSoC5\SD_PULLUP_aliases.h + .\Generated_Source\PSoC5\SD_PULLUP.c + .\Generated_Source\PSoC5\SD_PULLUP.h .\Generated_Source\PSoC5\prebuild.bat .\Generated_Source\PSoC5\postbuild.bat .\Generated_Source\PSoC5\CyElfTool.exe .\Generated_Source\PSoC5\libelf.dll - - + + .\Generated_Source\PSoC5\ARM_GCC\CyComponentLibrary.a - - + + .\Generated_Source\PSoC5\ARM_Keil_MDK\CyComponentLibrary.a - - + + .\Generated_Source\PSoC5\IAR\CyComponentLibrary.a - + - + - + - + - + - + - + diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/TopDesign/TopDesign.cysch b/software/SCSI2SD/USB_Bootloader.cydsn/TopDesign/TopDesign.cysch index 0e7873ac9f26407bb35d924b99d9851632deffae..fa108fe0d7db973e1d70786b20602ebd125afc7a 100755 GIT binary patch delta 5827 zcmcgwdr(x@89(3M* z;7G1UCyh<<6^%)5I!rsGQ72l_Q3q{H#>+&SSd(c(>LWIjI@*5UIeX#m+_uv{5@%=k zeCPN5e&_L>bH01_9{MP>`+Vs8g+55upY>&W!uQ^8zVzp~_A36UAXV23k^pw|_DPBT zR)iV~lxjhVqpg;`F_h`HpIep(PCm3O zH7srtW2Xz4U|m^Jt%S`5##G}uec|dZ;I}r#!*lxVHBFANe6V=2E{I)I;8|D}6d}t62jN(mfvd8F6(gttfBd=^&g-7auaua}NU?r}j=yJc30f~Oj*fFG!I@yJ0_`SJ2_{!v{`{0U@v zZmPz|f*qIuFRD**cOYUJ3sqI)Q@*o)0=&kr)DMZ0bE8?QMxFkBy{d#z%wzd4ug2>+ z4Ua+j0{G1$H&3tf@fA(e6FwKzuHbgD%1@l~h*|dGGZdJoKi}+dz-_*8&n$O$Fqx{V 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z+}+JNiS&fov`XfxWG*DeUhi1Mv5$Kuw#V~!MA01(wAKm&vt!SD+Q~IfUzs@RJ&eQQD0{}D3000UU z?E1T5nE?QDju!8goUL7CrT^{CL2vl@%^Lt97rJ5oErK37+X4X6>gqbG>Qb_DTL0n0 z{wY3!UexUZk+TXO9{@n42K)yn``baDT_&X?3@O|x)GSld5r!D-<^ljHIeUQI+&o=9 z{^{v2lN9swF=-emeu@MDKw;B=G(2}GrS?wh-vZe};zApE0Dv7A0D$iP(R@4s02xOY zONalKz(C_z`zsC@|NrTib#bz=b9Vo4Geep5OPkwh1OR|vr@czrQTU_R}6AX>>U!LZ?y0ia!bd=ETFGBb4wv-GVJ3AW+|3q<@|IKY;9 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -1033,7 +1072,7 @@ - + diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cyprj.Micha_000 b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cyprj.Micha_000 index c974aa29..c307d3ab 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cyprj.Micha_000 +++ b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cyprj.Micha_000 @@ -12,7 +12,7 @@ - + @@ -21,6 +21,8 @@ + + @@ -44,7 +46,7 @@ - + @@ -54,6 +56,8 @@ + + @@ -77,8 +81,8 @@ - - + + @@ -87,6 +91,8 @@ + + @@ -110,9 +116,9 @@ - + - + @@ -176,6 +182,17 @@ + + + + + + + + + + + @@ -357,6 +374,8 @@ + + @@ -467,6 +486,482 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -501,11 +996,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -543,9 +1075,42 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + @@ -564,16 +1129,18 @@ Off-Chip - + Cypress Component Catalog -Cypress Component Catalog\Communications +Cypress Component Catalog\Digital +Cypress Component Catalog\Digital\Functions +Cypress Component Catalog\Ports and Pins Cypress Component Catalog\System -Cypress Component Catalog\Display -Cypress Component Catalog\Filters -Cypress Component Catalog\Ports and Pins +Cypress Component Catalog\Ports and Pins\Digital Bidirectional Pin [v1.90] +Cypress Component Catalog\Ports and Pins\Digital Input Pin [v1.90] +Cypress Component Catalog\Ports and Pins\Digital Output Pin [v1.90] Cypress Component Catalog\Power Supervision Cypress Component Catalog\System Cypress Component Catalog\System\Boost Converter [v5.0] @@ -583,7 +1150,7 @@ Cypress Component Catalog\System\Die Temperature [v2.0] Cypress Component Catalog\System\DMA [v1.70] Cypress Component Catalog\System\EEPROM [v2.10] -Cypress Component Catalog\System\Emulated EEPROM [v1.0] +Cypress Component Catalog\System\Emulated EEPROM [v1.10] Cypress Component Catalog\System\External Memory Interface Cypress Component Catalog\System\Global Signal Reference [v2.0] Cypress Component Catalog\System\ILO Trim [v1.0] @@ -948,6 +1515,44 @@ ${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\PSoC5\API\aliases.h ${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\PSoC5\API\pins.c ${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\PSoC5\API\pins.h +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\cy_pins_v1_90.cyprimitive +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\cy_pins_v1_90.cysym +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\cy_pins_v1_90.pdf +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\cy_pins_v1_90.cystate +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90 +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\custom.cs +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cygeneralcontrol.cs +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cygeneralcontrol.Designer.cs +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cyinputcontrol.cs +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cyinputcontrol.Designer.cs +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cymappingcontrol.cs +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cymappingcontrol.Designer.cs +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cyoutputcontrol.cs +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cyoutputcontrol.Designer.cs +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cypinaliasdialog.cs +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cypinaliasdialog.Designer.cs +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cypinscontrol.cs +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cypinscontrol.Designer.cs +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cyporcontrol.cs +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cyporcontrol.Designer.cs +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cytypecontrol.cs +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cytypecontrol.Designer.cs +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\Resource1.Designer.cs +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cyclockingcontrol.cs +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cyclockingcontrol.Designer.cs +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cygeneralcontrol.resx +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cyinputcontrol.resx +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cymappingcontrol.resx +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cyoutputcontrol.resx +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cypinaliasdialog.resx +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cypinscontrol.resx +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cyporcontrol.resx +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cytypecontrol.resx +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\Resource1.resx +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cyclockingcontrol.resx +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\PSoC5\API\aliases.h +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\PSoC5\API\pins.c +${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\PSoC5\API\pins.h .\USB_Bootloader.cydwr ${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_0\PSoC5\API\cm3gcc.ld ${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_0\PSoC5\API\Cm3RealView.scat @@ -1049,20 +1654,23 @@ .\Generated_Source\PSoC5\Cm3Iar.icf .\Generated_Source\PSoC5\CyBootAsmIar.s .\Generated_Source\PSoC5\project.h +.\Generated_Source\PSoC5\SD_PULLUP_aliases.h +.\Generated_Source\PSoC5\SD_PULLUP.c +.\Generated_Source\PSoC5\SD_PULLUP.h C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\ieee\work\stdlogic.vif C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif - + - + diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.rpt b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.rpt index 81f4824a..7a8943b3 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.rpt +++ b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.rpt @@ -1,13 +1,13 @@ -Loading plugins phase: Elapsed time ==> 0s.499ms -Initializing data phase: Elapsed time ==> 3s.765ms +Loading plugins phase: Elapsed time ==> 0s.500ms +Initializing data phase: Elapsed time ==> 3s.890ms -cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -p W:\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 -s W:\SCSI2SD\USB_Bootloader.cydsn\Generated_Source\PSoC5 -- -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE +cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -p W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 -s W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\Generated_Source\PSoC5 -- -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -Elaboration phase: Elapsed time ==> 7s.219ms +Elaboration phase: Elapsed time ==> 7s.406ms -HDL generation phase: Elapsed time ==> 0s.140ms +HDL generation phase: Elapsed time ==> 0s.109ms | | | | | | | @@ -25,23 +25,23 @@ HDL generation phase: Elapsed time ==> 0s.140ms ====================================================================== Compiling: USB_Bootloader.v Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe -Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog +Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog ====================================================================== ====================================================================== Compiling: USB_Bootloader.v Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe -Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog +Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog ====================================================================== ====================================================================== Compiling: USB_Bootloader.v Program : vlogfe -Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v +Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v ====================================================================== vlogfe V6.3 IR 41: Verilog parser -Sat Oct 26 18:55:16 2013 +Sat Mar 22 22:32:47 2014 ====================================================================== @@ -51,7 +51,7 @@ Options : -yv2 -q10 USB_Bootloader.v ====================================================================== vpp V6.3 IR 41: Verilog Pre-Processor -Sat Oct 26 18:55:16 2013 +Sat Mar 22 22:32:47 2014 vpp: No errors. @@ -76,11 +76,11 @@ vlogfe: No errors. ====================================================================== Compiling: USB_Bootloader.v Program : tovif -Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v +Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v ====================================================================== tovif V6.3 IR 41: High-level synthesis -Sat Oct 26 18:55:16 2013 +Sat Mar 22 22:32:47 2014 Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'. @@ -91,8 +91,8 @@ Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\c Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. -Linking 'W:\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'. -Linking 'W:\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'. +Linking 'W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'. +Linking 'W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'. tovif: No errors. @@ -100,11 +100,11 @@ tovif: No errors. ====================================================================== Compiling: USB_Bootloader.v Program : topld -Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v +Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v ====================================================================== topld V6.3 IR 41: Synthesis and optimization -Sat Oct 26 18:55:16 2013 +Sat Mar 22 22:32:48 2014 Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'. @@ -115,8 +115,8 @@ Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\c Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. -Linking 'W:\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'. -Linking 'W:\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'. +Linking 'W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'. +Linking 'W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\lcpsoc3\stdlogic\cpsoc3.vif'. ---------------------------------------------------------- @@ -148,6 +148,11 @@ Aliasing tmpOE__SCSI_Out_net_3 to \USBFS:tmpOE__Dm_net_0\ Aliasing tmpOE__SCSI_Out_net_2 to \USBFS:tmpOE__Dm_net_0\ Aliasing tmpOE__SCSI_Out_net_1 to \USBFS:tmpOE__Dm_net_0\ Aliasing tmpOE__SCSI_Out_net_0 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SD_PULLUP_net_4 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SD_PULLUP_net_3 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SD_PULLUP_net_2 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SD_PULLUP_net_1 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SD_PULLUP_net_0 to \USBFS:tmpOE__Dm_net_0\ Removing Rhs of wire one[37] = \USBFS:tmpOE__Dm_net_0\[32] Removing Lhs of wire \USBFS:tmpOE__Dp_net_0\[40] = one[37] Removing Lhs of wire tmpOE__SCSI_Out_DBx_net_7[49] = one[37] @@ -168,9 +173,14 @@ Removing Lhs of wire tmpOE__SCSI_Out_net_3[90] = one[37] Removing Lhs of wire tmpOE__SCSI_Out_net_2[91] = one[37] Removing Lhs of wire tmpOE__SCSI_Out_net_1[92] = one[37] Removing Lhs of wire tmpOE__SCSI_Out_net_0[93] = one[37] +Removing Lhs of wire tmpOE__SD_PULLUP_net_4[127] = one[37] +Removing Lhs of wire tmpOE__SD_PULLUP_net_3[128] = one[37] +Removing Lhs of wire tmpOE__SD_PULLUP_net_2[129] = one[37] +Removing Lhs of wire tmpOE__SD_PULLUP_net_1[130] = one[37] +Removing Lhs of wire tmpOE__SD_PULLUP_net_0[131] = one[37] ------------------------------------------------------ -Aliased 0 equations, 20 wires. +Aliased 0 equations, 25 wires. ------------------------------------------------------ ---------------------------------------------------------- @@ -192,16 +202,16 @@ topld: No errors. CYPRESS_DIR : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp Warp Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe -Warp Arguments : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog +Warp Arguments : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog -Warp synthesis phase: Elapsed time ==> 1s.359ms +Warp synthesis phase: Elapsed time ==> 1s.468ms -cyp3fit: V3.0.0.1539, Family: PSoC3, Started at: Saturday, 26 October 2013 18:55:17 -Options: -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 USB_Bootloader.v -verilog +cyp3fit: V3.0.0.1539, Family: PSoC3, Started at: Saturday, 22 March 2014 22:32:48 +Options: -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 USB_Bootloader.v -verilog -Design parsing phase: Elapsed time ==> 0s.031ms +Design parsing phase: Elapsed time ==> 0s.046ms @@ -928,6 +938,196 @@ Design Equations { } + Pin : Name = SD_PULLUP(0) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO RefSel: VCC_IO + Required Capabilitites: DIGITAL + Initial Value: 1 + IO Voltage: 3.3 + PORT MAP ( + pa_out => SD_PULLUP(0)__PA , + pad => SD_PULLUP(0)_PAD ); + Properties: + { + } + + Pin : Name = SD_PULLUP(1) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO RefSel: VCC_IO + Required Capabilitites: DIGITAL + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SD_PULLUP(1)__PA , + pad => SD_PULLUP(1)_PAD ); + Properties: + { + } + + Pin : Name = SD_PULLUP(2) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO RefSel: VCC_IO + Required Capabilitites: DIGITAL + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SD_PULLUP(2)__PA , + pad => SD_PULLUP(2)_PAD ); + Properties: + { + } + + Pin : Name = SD_PULLUP(3) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO RefSel: VCC_IO + Required Capabilitites: DIGITAL + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SD_PULLUP(3)__PA , + pad => SD_PULLUP(3)_PAD ); + Properties: + { + } + + Pin : Name = SD_PULLUP(4) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO RefSel: VCC_IO + Required Capabilitites: DIGITAL + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SD_PULLUP(4)__PA , + pad => SD_PULLUP(4)_PAD ); + Properties: + { + } + Pin : Name = \USBFS:Dm(0)\ Attributes: In Group/Port: True @@ -1095,7 +1295,7 @@ Resource Type : Used : Free : Max : % Used ============================================================ Digital clock dividers : 0 : 8 : 8 : 0.00% Analog clock dividers : 0 : 4 : 4 : 0.00% -Pins : 23 : 49 : 72 : 31.94% +Pins : 28 : 44 : 72 : 38.89% UDB Macrocells : 0 : 192 : 192 : 0.00% UDB Unique Pterms : 0 : 384 : 384 : 0.00% UDB Datapath Cells : 0 : 24 : 24 : 0.00% @@ -1114,8 +1314,8 @@ EMIF Fixed Blocks : 0 : 1 : 1 : 0.00% LPF Fixed Blocks : 0 : 2 : 2 : 0.00% SAR Fixed Blocks : 0 : 1 : 1 : 0.00% -Technology Mapping: Elapsed time ==> 0s.016ms -Tech mapping phase: Elapsed time ==> 0s.281ms +Technology Mapping: Elapsed time ==> 0s.030ms +Tech mapping phase: Elapsed time ==> 0s.265ms Initial Analog Placement Results: @@ -1137,10 +1337,15 @@ IO_7@[IOP=(4)][IoId=(7)] : SCSI_Out_DBx(4) (fixed) IO_6@[IOP=(4)][IoId=(6)] : SCSI_Out_DBx(5) (fixed) IO_5@[IOP=(4)][IoId=(5)] : SCSI_Out_DBx(6) (fixed) IO_4@[IOP=(4)][IoId=(4)] : SCSI_Out_DBx(7) (fixed) +IO_1@[IOP=(3)][IoId=(1)] : SD_PULLUP(0) (fixed) +IO_2@[IOP=(3)][IoId=(2)] : SD_PULLUP(1) (fixed) +IO_3@[IOP=(3)][IoId=(3)] : SD_PULLUP(2) (fixed) +IO_4@[IOP=(3)][IoId=(4)] : SD_PULLUP(3) (fixed) +IO_5@[IOP=(3)][IoId=(5)] : SD_PULLUP(4) (fixed) IO_7@[IOP=(15)][IoId=(7)] : \USBFS:Dm(0)\ (fixed) IO_6@[IOP=(15)][IoId=(6)] : \USBFS:Dp(0)\ (fixed) USB[0]@[FFB(USB,0)] : \USBFS:USB\ -Analog Placement phase: Elapsed time ==> 0s.093ms +Analog Placement phase: Elapsed time ==> 0s.109ms Analog Routing phase: Elapsed time ==> 0s.000ms @@ -1158,12 +1363,12 @@ Dump of CyP35AnalogRoutingResultsDB IsVddaHalfUsedForComp = False IsVddaHalfUsedForSar0 = False IsVddaHalfUsedForSar1 = False -Analog Code Generation phase: Elapsed time ==> 0s.984ms +Analog Code Generation phase: Elapsed time ==> 1s.000ms I2659: No Constrained paths were found. The placer will run in non-timing driven mode. -I2076: Total run-time: 1.3 sec. +I2076: Total run-time: 1.2 sec. @@ -1177,7 +1382,7 @@ PLD Packing: Elapsed time ==> 0s.000ms Initial Partitioning Summary not displayed at this verbose level. Final Partitioning Summary not displayed at this verbose level. -Partitioning: Elapsed time ==> 0s.063ms +Partitioning: Elapsed time ==> 0s.093ms Annealing: Elapsed time ==> 0s.000ms @@ -1605,7 +1810,202 @@ Pin : Name = SCSI_Out(2) Port 1 is empty Port 2 is empty -Port 3 is empty +Port 3 contains the following IO cells: +[IoId=1]: +Pin : Name = SD_PULLUP(0) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO RefSel: VCC_IO + Required Capabilitites: DIGITAL + Initial Value: 1 + IO Voltage: 3.3 + PORT MAP ( + pa_out => SD_PULLUP(0)__PA , + pad => SD_PULLUP(0)_PAD ); + Properties: + { + } + +[IoId=2]: +Pin : Name = SD_PULLUP(1) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO RefSel: VCC_IO + Required Capabilitites: DIGITAL + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SD_PULLUP(1)__PA , + pad => SD_PULLUP(1)_PAD ); + Properties: + { + } + +[IoId=3]: +Pin : Name = SD_PULLUP(2) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO RefSel: VCC_IO + Required Capabilitites: DIGITAL + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SD_PULLUP(2)__PA , + pad => SD_PULLUP(2)_PAD ); + Properties: + { + } + +[IoId=4]: +Pin : Name = SD_PULLUP(3) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO RefSel: VCC_IO + Required Capabilitites: DIGITAL + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SD_PULLUP(3)__PA , + pad => SD_PULLUP(3)_PAD ); + Properties: + { + } + +[IoId=5]: +Pin : Name = SD_PULLUP(4) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO RefSel: VCC_IO + Required Capabilitites: DIGITAL + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SD_PULLUP(4)__PA , + pad => SD_PULLUP(4)_PAD ); + Properties: + { + } + Port 4 contains the following IO cells: [IoId=2]: Pin : Name = SCSI_Out(1) @@ -2239,6 +2639,12 @@ Port | Pin | Fixed | Type | Drive Mode | Name | Connection | 5 | * | NONE | CMOS_OUT | SCSI_Out(4) | | 6 | * | NONE | CMOS_OUT | SCSI_Out(3) | | 7 | * | NONE | CMOS_OUT | SCSI_Out(2) | +-----+-----+-------+-----------+------------------+-----------------+------------------------- + 3 | 1 | * | NONE | RES_PULL_UP | SD_PULLUP(0) | + | 2 | * | NONE | RES_PULL_UP | SD_PULLUP(1) | + | 3 | * | NONE | RES_PULL_UP | SD_PULLUP(2) | + | 4 | * | NONE | RES_PULL_UP | SD_PULLUP(3) | + | 5 | * | NONE | RES_PULL_UP | SD_PULLUP(4) | -----+-----+-------+-----------+------------------+-----------------+------------------------- 4 | 2 | * | NONE | CMOS_OUT | SCSI_Out(1) | | 3 | * | NONE | CMOS_OUT | SCSI_Out(0) | @@ -2259,31 +2665,31 @@ Port | Pin | Fixed | Type | Drive Mode | Name | Connection Digital component placer commit/Report: Elapsed time ==> 0s.014ms -Digital Placement phase: Elapsed time ==> 2s.140ms +Digital Placement phase: Elapsed time ==> 2s.172ms Routing successful. -Digital Routing phase: Elapsed time ==> 2s.955ms +Digital Routing phase: Elapsed time ==> 3s.093ms -Bitstream and API generation phase: Elapsed time ==> 0s.732ms +Bitstream and API generation phase: Elapsed time ==> 0s.702ms -Bitstream verification phase: Elapsed time ==> 0s.127ms +Bitstream verification phase: Elapsed time ==> 0s.140ms Timing report is in USB_Bootloader_timing.html. -Static timing analysis phase: Elapsed time ==> 0s.638ms +Static timing analysis phase: Elapsed time ==> 0s.719ms Data reporting phase: Elapsed time ==> 0s.000ms -Design database save phase: Elapsed time ==> 0s.609ms +Design database save phase: Elapsed time ==> 0s.406ms -cydsfit: Elapsed time ==> 8s.672ms +cydsfit: Elapsed time ==> 8s.765ms -Fitter phase: Elapsed time ==> 8s.750ms -API generation phase: Elapsed time ==> 3s.081ms -Dependency generation phase: Elapsed time ==> 0s.028ms -Cleanup phase: Elapsed time ==> 0s.031ms +Fitter phase: Elapsed time ==> 8s.859ms +API generation phase: Elapsed time ==> 3s.296ms +Dependency generation phase: Elapsed time ==> 0s.016ms +Cleanup phase: Elapsed time ==> 0s.047ms diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader_timing.html b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader_timing.html index 517ee041..83b2bc27 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader_timing.html +++ b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader_timing.html @@ -539,7 +539,7 @@ function getElementsByClass(rootNode, elemName, className) Project : USB_Bootloader Build Time : - 10/26/13 18:55:25 + 03/22/14 22:32:57 Device : CY8C5267AXI-LP051 Temperature : diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.ctl b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.ctl index 0c134297..3e249a5c 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.ctl +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.ctl @@ -1,6 +1,6 @@ -- ====================================================================== -- USB_Bootloader.ctl generated from USB_Bootloader --- 10/26/2013 at 18:55 +-- 03/22/2014 at 22:32 -- This file is auto generated. ANY EDITS YOU MAKE MAY BE LOST WHEN THIS FILE IS REGENERATED!!! -- ====================================================================== diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.cycdx b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.cycdx index 3b663c70..8f6ac4e9 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.cycdx +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.cycdx @@ -1,7 +1,8 @@ - + + diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.cyfit b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.cyfit index f632ee63ab0ee58dec7c9f7af44b806218ae5006..c3c2e9014b992dd8596aed85189accdd08130253 100755 GIT binary patch delta 131249 zcmZs?V{~NQ7d{x99ox3kvE4B{9osglJMK8CbZpzUla6iMHmCai{b$XZS@Yr6skQIM zvsHC&?Nc}7@JSo+0A+bdC`>RgFgP%rdUpv5kN2T$12C}600=Nh5LH4;^}GWyL2p@S z(@WkyrE%4czY((kuG?+VNq&&YtwdcTo^Z98SXKT)vn+Owr7g`_aNhYenD{*LT4ab@ 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z+}+JNiS&fov`XfxWG*DeUhi1Mv5$Kuw#V~!MA01(wAKm&vt!SD+Q~IfUzs@RJ&eQQD0{}D3000UU z?E1T5nE?QDju!8goUL7CrT^{CL2vl@%^Lt97rJ5oErK37+X4X6>gqbG>Qb_DTL0n0 z{wY3!UexUZk+TXO9{@n42K)yn``baDT_&X?3@O|x)GSld5r!D-<^ljHIeUQI+&o=9 z{^{v2lN9swF=-emeu@MDKw;B=G(2}GrS?wh-vZe};zApE0Dv7A0D$iP(R@4s02xOY zONalKz(C_z`zsC@|NrTib#bz=b9Vo4Geep5OPkwh1OR|vr@czrQTU_R}6AX>>U!LZ?y0ia!bd=ETFGBb4wv-GVJ3AW+|3q<@|IKY;9:ioport3:pin1.in_clock" + term ":ioport3:pin1.in_clock" + switch ":clockblockcell.clk_bus_glb==>:ioport3:pin2.in_clock" + term ":ioport3:pin2.in_clock" + switch ":clockblockcell.clk_bus_glb==>:ioport3:pin3.in_clock" + term ":ioport3:pin3.in_clock" + switch ":clockblockcell.clk_bus_glb==>:ioport3:pin4.in_clock" + term ":ioport3:pin4.in_clock" + switch ":clockblockcell.clk_bus_glb==>:ioport3:pin5.in_clock" + term ":ioport3:pin5.in_clock" switch ":clockblockcell.clk_bus_glb==>:ioport15:pin6.in_clock" term ":ioport15:pin6.in_clock" switch ":clockblockcell.clk_bus_glb==>:interrupt_22.clock" diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.rpt b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.rpt index 81f4824a..7a8943b3 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.rpt +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.rpt @@ -1,13 +1,13 @@ -Loading plugins phase: Elapsed time ==> 0s.499ms -Initializing data phase: Elapsed time ==> 3s.765ms +Loading plugins phase: Elapsed time ==> 0s.500ms +Initializing data phase: Elapsed time ==> 3s.890ms -cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -p W:\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 -s W:\SCSI2SD\USB_Bootloader.cydsn\Generated_Source\PSoC5 -- -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE +cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -p W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 -s W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\Generated_Source\PSoC5 -- -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -Elaboration phase: Elapsed time ==> 7s.219ms +Elaboration phase: Elapsed time ==> 7s.406ms -HDL generation phase: Elapsed time ==> 0s.140ms +HDL generation phase: Elapsed time ==> 0s.109ms | | | | | | | @@ -25,23 +25,23 @@ HDL generation phase: Elapsed time ==> 0s.140ms ====================================================================== Compiling: USB_Bootloader.v Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe -Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog +Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog ====================================================================== ====================================================================== Compiling: USB_Bootloader.v Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe -Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog +Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog ====================================================================== ====================================================================== Compiling: USB_Bootloader.v Program : vlogfe -Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v +Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v ====================================================================== vlogfe V6.3 IR 41: Verilog parser -Sat Oct 26 18:55:16 2013 +Sat Mar 22 22:32:47 2014 ====================================================================== @@ -51,7 +51,7 @@ Options : -yv2 -q10 USB_Bootloader.v ====================================================================== vpp V6.3 IR 41: Verilog Pre-Processor -Sat Oct 26 18:55:16 2013 +Sat Mar 22 22:32:47 2014 vpp: No errors. @@ -76,11 +76,11 @@ vlogfe: No errors. ====================================================================== Compiling: USB_Bootloader.v Program : tovif -Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v +Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v ====================================================================== tovif V6.3 IR 41: High-level synthesis -Sat Oct 26 18:55:16 2013 +Sat Mar 22 22:32:47 2014 Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'. @@ -91,8 +91,8 @@ Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\c Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. -Linking 'W:\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'. -Linking 'W:\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'. +Linking 'W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'. +Linking 'W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'. tovif: No errors. @@ -100,11 +100,11 @@ tovif: No errors. ====================================================================== Compiling: USB_Bootloader.v Program : topld -Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v +Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v ====================================================================== topld V6.3 IR 41: Synthesis and optimization -Sat Oct 26 18:55:16 2013 +Sat Mar 22 22:32:48 2014 Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'. @@ -115,8 +115,8 @@ Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\c Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. -Linking 'W:\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'. -Linking 'W:\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'. +Linking 'W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'. +Linking 'W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\lcpsoc3\stdlogic\cpsoc3.vif'. ---------------------------------------------------------- @@ -148,6 +148,11 @@ Aliasing tmpOE__SCSI_Out_net_3 to \USBFS:tmpOE__Dm_net_0\ Aliasing tmpOE__SCSI_Out_net_2 to \USBFS:tmpOE__Dm_net_0\ Aliasing tmpOE__SCSI_Out_net_1 to \USBFS:tmpOE__Dm_net_0\ Aliasing tmpOE__SCSI_Out_net_0 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SD_PULLUP_net_4 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SD_PULLUP_net_3 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SD_PULLUP_net_2 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SD_PULLUP_net_1 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SD_PULLUP_net_0 to \USBFS:tmpOE__Dm_net_0\ Removing Rhs of wire one[37] = \USBFS:tmpOE__Dm_net_0\[32] Removing Lhs of wire \USBFS:tmpOE__Dp_net_0\[40] = one[37] Removing Lhs of wire tmpOE__SCSI_Out_DBx_net_7[49] = one[37] @@ -168,9 +173,14 @@ Removing Lhs of wire tmpOE__SCSI_Out_net_3[90] = one[37] Removing Lhs of wire tmpOE__SCSI_Out_net_2[91] = one[37] Removing Lhs of wire tmpOE__SCSI_Out_net_1[92] = one[37] Removing Lhs of wire tmpOE__SCSI_Out_net_0[93] = one[37] +Removing Lhs of wire tmpOE__SD_PULLUP_net_4[127] = one[37] +Removing Lhs of wire tmpOE__SD_PULLUP_net_3[128] = one[37] +Removing Lhs of wire tmpOE__SD_PULLUP_net_2[129] = one[37] +Removing Lhs of wire tmpOE__SD_PULLUP_net_1[130] = one[37] +Removing Lhs of wire tmpOE__SD_PULLUP_net_0[131] = one[37] ------------------------------------------------------ -Aliased 0 equations, 20 wires. +Aliased 0 equations, 25 wires. ------------------------------------------------------ ---------------------------------------------------------- @@ -192,16 +202,16 @@ topld: No errors. CYPRESS_DIR : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp Warp Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe -Warp Arguments : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog +Warp Arguments : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog -Warp synthesis phase: Elapsed time ==> 1s.359ms +Warp synthesis phase: Elapsed time ==> 1s.468ms -cyp3fit: V3.0.0.1539, Family: PSoC3, Started at: Saturday, 26 October 2013 18:55:17 -Options: -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 USB_Bootloader.v -verilog +cyp3fit: V3.0.0.1539, Family: PSoC3, Started at: Saturday, 22 March 2014 22:32:48 +Options: -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 USB_Bootloader.v -verilog -Design parsing phase: Elapsed time ==> 0s.031ms +Design parsing phase: Elapsed time ==> 0s.046ms @@ -928,6 +938,196 @@ Design Equations { } + Pin : Name = SD_PULLUP(0) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO RefSel: VCC_IO + Required Capabilitites: DIGITAL + Initial Value: 1 + IO Voltage: 3.3 + PORT MAP ( + pa_out => SD_PULLUP(0)__PA , + pad => SD_PULLUP(0)_PAD ); + Properties: + { + } + + Pin : Name = SD_PULLUP(1) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO RefSel: VCC_IO + Required Capabilitites: DIGITAL + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SD_PULLUP(1)__PA , + pad => SD_PULLUP(1)_PAD ); + Properties: + { + } + + Pin : Name = SD_PULLUP(2) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO RefSel: VCC_IO + Required Capabilitites: DIGITAL + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SD_PULLUP(2)__PA , + pad => SD_PULLUP(2)_PAD ); + Properties: + { + } + + Pin : Name = SD_PULLUP(3) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO RefSel: VCC_IO + Required Capabilitites: DIGITAL + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SD_PULLUP(3)__PA , + pad => SD_PULLUP(3)_PAD ); + Properties: + { + } + + Pin : Name = SD_PULLUP(4) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO RefSel: VCC_IO + Required Capabilitites: DIGITAL + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SD_PULLUP(4)__PA , + pad => SD_PULLUP(4)_PAD ); + Properties: + { + } + Pin : Name = \USBFS:Dm(0)\ Attributes: In Group/Port: True @@ -1095,7 +1295,7 @@ Resource Type : Used : Free : Max : % Used ============================================================ Digital clock dividers : 0 : 8 : 8 : 0.00% Analog clock dividers : 0 : 4 : 4 : 0.00% -Pins : 23 : 49 : 72 : 31.94% +Pins : 28 : 44 : 72 : 38.89% UDB Macrocells : 0 : 192 : 192 : 0.00% UDB Unique Pterms : 0 : 384 : 384 : 0.00% UDB Datapath Cells : 0 : 24 : 24 : 0.00% @@ -1114,8 +1314,8 @@ EMIF Fixed Blocks : 0 : 1 : 1 : 0.00% LPF Fixed Blocks : 0 : 2 : 2 : 0.00% SAR Fixed Blocks : 0 : 1 : 1 : 0.00% -Technology Mapping: Elapsed time ==> 0s.016ms -Tech mapping phase: Elapsed time ==> 0s.281ms +Technology Mapping: Elapsed time ==> 0s.030ms +Tech mapping phase: Elapsed time ==> 0s.265ms Initial Analog Placement Results: @@ -1137,10 +1337,15 @@ IO_7@[IOP=(4)][IoId=(7)] : SCSI_Out_DBx(4) (fixed) IO_6@[IOP=(4)][IoId=(6)] : SCSI_Out_DBx(5) (fixed) IO_5@[IOP=(4)][IoId=(5)] : SCSI_Out_DBx(6) (fixed) IO_4@[IOP=(4)][IoId=(4)] : SCSI_Out_DBx(7) (fixed) +IO_1@[IOP=(3)][IoId=(1)] : SD_PULLUP(0) (fixed) +IO_2@[IOP=(3)][IoId=(2)] : SD_PULLUP(1) (fixed) +IO_3@[IOP=(3)][IoId=(3)] : SD_PULLUP(2) (fixed) +IO_4@[IOP=(3)][IoId=(4)] : SD_PULLUP(3) (fixed) +IO_5@[IOP=(3)][IoId=(5)] : SD_PULLUP(4) (fixed) IO_7@[IOP=(15)][IoId=(7)] : \USBFS:Dm(0)\ (fixed) IO_6@[IOP=(15)][IoId=(6)] : \USBFS:Dp(0)\ (fixed) USB[0]@[FFB(USB,0)] : \USBFS:USB\ -Analog Placement phase: Elapsed time ==> 0s.093ms +Analog Placement phase: Elapsed time ==> 0s.109ms Analog Routing phase: Elapsed time ==> 0s.000ms @@ -1158,12 +1363,12 @@ Dump of CyP35AnalogRoutingResultsDB IsVddaHalfUsedForComp = False IsVddaHalfUsedForSar0 = False IsVddaHalfUsedForSar1 = False -Analog Code Generation phase: Elapsed time ==> 0s.984ms +Analog Code Generation phase: Elapsed time ==> 1s.000ms I2659: No Constrained paths were found. The placer will run in non-timing driven mode. -I2076: Total run-time: 1.3 sec. +I2076: Total run-time: 1.2 sec. @@ -1177,7 +1382,7 @@ PLD Packing: Elapsed time ==> 0s.000ms Initial Partitioning Summary not displayed at this verbose level. Final Partitioning Summary not displayed at this verbose level. -Partitioning: Elapsed time ==> 0s.063ms +Partitioning: Elapsed time ==> 0s.093ms Annealing: Elapsed time ==> 0s.000ms @@ -1605,7 +1810,202 @@ Pin : Name = SCSI_Out(2) Port 1 is empty Port 2 is empty -Port 3 is empty +Port 3 contains the following IO cells: +[IoId=1]: +Pin : Name = SD_PULLUP(0) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO RefSel: VCC_IO + Required Capabilitites: DIGITAL + Initial Value: 1 + IO Voltage: 3.3 + PORT MAP ( + pa_out => SD_PULLUP(0)__PA , + pad => SD_PULLUP(0)_PAD ); + Properties: + { + } + +[IoId=2]: +Pin : Name = SD_PULLUP(1) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO RefSel: VCC_IO + Required Capabilitites: DIGITAL + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SD_PULLUP(1)__PA , + pad => SD_PULLUP(1)_PAD ); + Properties: + { + } + +[IoId=3]: +Pin : Name = SD_PULLUP(2) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO RefSel: VCC_IO + Required Capabilitites: DIGITAL + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SD_PULLUP(2)__PA , + pad => SD_PULLUP(2)_PAD ); + Properties: + { + } + +[IoId=4]: +Pin : Name = SD_PULLUP(3) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO RefSel: VCC_IO + Required Capabilitites: DIGITAL + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SD_PULLUP(3)__PA , + pad => SD_PULLUP(3)_PAD ); + Properties: + { + } + +[IoId=5]: +Pin : Name = SD_PULLUP(4) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO RefSel: VCC_IO + Required Capabilitites: DIGITAL + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SD_PULLUP(4)__PA , + pad => SD_PULLUP(4)_PAD ); + Properties: + { + } + Port 4 contains the following IO cells: [IoId=2]: Pin : Name = SCSI_Out(1) @@ -2239,6 +2639,12 @@ Port | Pin | Fixed | Type | Drive Mode | Name | Connection | 5 | * | NONE | CMOS_OUT | SCSI_Out(4) | | 6 | * | NONE | CMOS_OUT | SCSI_Out(3) | | 7 | * | NONE | CMOS_OUT | SCSI_Out(2) | +-----+-----+-------+-----------+------------------+-----------------+------------------------- + 3 | 1 | * | NONE | RES_PULL_UP | SD_PULLUP(0) | + | 2 | * | NONE | RES_PULL_UP | SD_PULLUP(1) | + | 3 | * | NONE | RES_PULL_UP | SD_PULLUP(2) | + | 4 | * | NONE | RES_PULL_UP | SD_PULLUP(3) | + | 5 | * | NONE | RES_PULL_UP | SD_PULLUP(4) | -----+-----+-------+-----------+------------------+-----------------+------------------------- 4 | 2 | * | NONE | CMOS_OUT | SCSI_Out(1) | | 3 | * | NONE | CMOS_OUT | SCSI_Out(0) | @@ -2259,31 +2665,31 @@ Port | Pin | Fixed | Type | Drive Mode | Name | Connection Digital component placer commit/Report: Elapsed time ==> 0s.014ms -Digital Placement phase: Elapsed time ==> 2s.140ms +Digital Placement phase: Elapsed time ==> 2s.172ms Routing successful. -Digital Routing phase: Elapsed time ==> 2s.955ms +Digital Routing phase: Elapsed time ==> 3s.093ms -Bitstream and API generation phase: Elapsed time ==> 0s.732ms +Bitstream and API generation phase: Elapsed time ==> 0s.702ms -Bitstream verification phase: Elapsed time ==> 0s.127ms +Bitstream verification phase: Elapsed time ==> 0s.140ms Timing report is in USB_Bootloader_timing.html. -Static timing analysis phase: Elapsed time ==> 0s.638ms +Static timing analysis phase: Elapsed time ==> 0s.719ms Data reporting phase: Elapsed time ==> 0s.000ms -Design database save phase: Elapsed time ==> 0s.609ms +Design database save phase: Elapsed time ==> 0s.406ms -cydsfit: Elapsed time ==> 8s.672ms +cydsfit: Elapsed time ==> 8s.765ms -Fitter phase: Elapsed time ==> 8s.750ms -API generation phase: Elapsed time ==> 3s.081ms -Dependency generation phase: Elapsed time ==> 0s.028ms -Cleanup phase: Elapsed time ==> 0s.031ms +Fitter phase: Elapsed time ==> 8s.859ms +API generation phase: Elapsed time ==> 3s.296ms +Dependency generation phase: Elapsed time ==> 0s.016ms +Cleanup phase: Elapsed time ==> 0s.047ms diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.sdc b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.sdc index 31b0bbd6..9b303408 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.sdc +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.sdc @@ -1,6 +1,6 @@ # THIS FILE IS AUTOMATICALLY GENERATED -# Project: W:\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -# Date: Sat, 26 Oct 2013 08:55:25 GMT +# Project: W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj +# Date: Sat, 22 Mar 2014 12:32:56 GMT #set_units -time ns create_clock -name {CyIMO} -period 41.666666666666664 -waveform {0 20.8333333333333} [list [get_pins {ClockBlock/imo}]] create_clock -name {CyPLL_OUT} -period 15.625 -waveform {0 7.8125} [list [get_pins {ClockBlock/pllout}]] @@ -9,6 +9,6 @@ create_clock -name {CyMASTER_CLK} -period 15.625 -waveform {0 7.8125} [list [get create_generated_clock -name {CyBUS_CLK} -source [get_pins {ClockBlock/clk_sync}] -edges {1 2 3} [list [get_pins {ClockBlock/clk_bus_glb}]] -# Component constraints for W:\SCSI2SD\USB_Bootloader.cydsn\TopDesign\TopDesign.cysch -# Project: W:\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -# Date: Sat, 26 Oct 2013 08:55:15 GMT +# Component constraints for W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\TopDesign\TopDesign.cysch +# Project: W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj +# Date: Sat, 22 Mar 2014 12:32:47 GMT diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.sdf b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.sdf index c196de5a..97e14149 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.sdf +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.sdf @@ -1,6 +1,6 @@ (DELAYFILE (SDFVERSION "IEEE 1497 4.0") - (DATE "2013-10-26T08:55:25Z") + (DATE "2014-03-22T12:32:56Z") (DESIGN "USB_Bootloader") (VENDOR "Cypress Semiconductor") (PROGRAM "cydsfit") @@ -12,7 +12,12 @@ (INSTANCE *) (DELAY (ABSOLUTE + (INTERCONNECT ClockBlock.clk_bus_glb SD_PULLUP\(0\).in_clock (0.000:0.000:0.000)) (INTERCONNECT ClockBlock.clk_bus_glb \\USBFS\:arb_int\\.clock (0.000:0.000:0.000)) + (INTERCONNECT ClockBlock.clk_bus_glb SD_PULLUP\(1\).in_clock (0.000:0.000:0.000)) + (INTERCONNECT ClockBlock.clk_bus_glb SD_PULLUP\(2\).in_clock (0.000:0.000:0.000)) + (INTERCONNECT ClockBlock.clk_bus_glb SD_PULLUP\(3\).in_clock (0.000:0.000:0.000)) + (INTERCONNECT ClockBlock.clk_bus_glb SD_PULLUP\(4\).in_clock (0.000:0.000:0.000)) (INTERCONNECT ClockBlock.clk_bus_glb \\USBFS\:Dp\(0\)\\.in_clock (0.000:0.000:0.000)) (INTERCONNECT ClockBlock.clk_bus_glb \\USBFS\:bus_reset\\.clock (0.000:0.000:0.000)) (INTERCONNECT ClockBlock.clk_bus_glb \\USBFS\:dp_int\\.clock (0.000:0.000:0.000)) @@ -45,6 +50,11 @@ (INTERCONNECT SCSI_Out_DBx\(5\)_PAD SCSI_Out_DBx\(5\).pad_in (0.000:0.000:0.000)) (INTERCONNECT SCSI_Out_DBx\(6\)_PAD SCSI_Out_DBx\(6\).pad_in (0.000:0.000:0.000)) (INTERCONNECT SCSI_Out_DBx\(7\)_PAD SCSI_Out_DBx\(7\).pad_in (0.000:0.000:0.000)) + (INTERCONNECT SD_PULLUP\(0\)_PAD SD_PULLUP\(0\).pad_in (0.000:0.000:0.000)) + (INTERCONNECT SD_PULLUP\(1\)_PAD SD_PULLUP\(1\).pad_in (0.000:0.000:0.000)) + (INTERCONNECT SD_PULLUP\(2\)_PAD SD_PULLUP\(2\).pad_in (0.000:0.000:0.000)) + (INTERCONNECT SD_PULLUP\(3\)_PAD SD_PULLUP\(3\).pad_in (0.000:0.000:0.000)) + (INTERCONNECT SD_PULLUP\(4\)_PAD SD_PULLUP\(4\).pad_in (0.000:0.000:0.000)) ) ) ) diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.v b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.v index 1ae17d1e..ad431b1a 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.v +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.v @@ -1,6 +1,6 @@ // ====================================================================== // USB_Bootloader.v generated from TopDesign.cysch -// 10/26/2013 at 18:55 +// 03/22/2014 at 22:32 // This file is auto generated. ANY EDITS YOU MAKE MAY BE LOST WHEN THIS FILE IS REGENERATED!!! // ====================================================================== @@ -302,6 +302,11 @@ endmodule // top module top ; + wire Net_88; + wire Net_87; + wire Net_86; + wire Net_85; + wire Net_84; electrical Net_36; electrical Net_35; electrical Net_34; @@ -460,6 +465,74 @@ module top ; assign tmpOE__SCSI_Out_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{10'b1111111111} : {10'b1111111111}; + wire [4:0] tmpOE__SD_PULLUP_net; + wire [4:0] tmpIO_4__SD_PULLUP_net; + wire [0:0] tmpINTERRUPT_0__SD_PULLUP_net; + electrical [0:0] tmpSIOVREF__SD_PULLUP_net; + + cy_psoc3_pins_v1_10 + #(.id("4c15b41e-e284-4978-99e7-5aaee19bd0ce"), + .drive_mode(15'b010_010_010_010_010), + .ibuf_enabled(5'b1_1_1_1_1), + .init_dr_st(5'b1_1_1_1_1), + .input_clk_en(0), + .input_sync(5'b1_1_1_1_1), + .input_sync_mode(5'b0_0_0_0_0), + .intr_mode(10'b00_00_00_00_00), + .invert_in_clock(0), + .invert_in_clock_en(0), + .invert_in_reset(0), + .invert_out_clock(0), + .invert_out_clock_en(0), + .invert_out_reset(0), + .io_voltage("3.3, , , , "), + .layout_mode("CONTIGUOUS"), + .oe_conn(5'b0_0_0_0_0), + .oe_reset(0), + .oe_sync(5'b0_0_0_0_0), + .output_clk_en(0), + .output_clock_mode(5'b0_0_0_0_0), + .output_conn(5'b0_0_0_0_0), + .output_mode(5'b0_0_0_0_0), + .output_reset(0), + .output_sync(5'b0_0_0_0_0), + .pa_in_clock(-1), + .pa_in_clock_en(-1), + .pa_in_reset(-1), + .pa_out_clock(-1), + .pa_out_clock_en(-1), + .pa_out_reset(-1), + .pin_aliases(",,,,"), + .pin_mode("IIIII"), + .por_state(2), + .use_annotation(5'b0_0_0_0_0), + .sio_group_cnt(0), + .sio_hyst(5'b0_0_0_0_0), + .sio_ibuf(""), + .sio_info(10'b00_00_00_00_00), + .sio_obuf(""), + .sio_refsel(""), + .sio_vtrip(""), + .slew_rate(5'b0_0_0_0_0), + .spanning(0), + .vtrip(10'b00_00_00_00_00), + .width(5)) + SD_PULLUP + (.oe(tmpOE__SD_PULLUP_net), + .y({5'b0}), + .fb({Net_88, Net_87, Net_86, Net_85, Net_84}), + .io({tmpIO_4__SD_PULLUP_net[4:0]}), + .siovref(tmpSIOVREF__SD_PULLUP_net), + .interrupt({tmpINTERRUPT_0__SD_PULLUP_net[0:0]}), + .in_clock({1'b0}), + .in_clock_en({1'b1}), + .in_reset({1'b0}), + .out_clock({1'b0}), + .out_clock_en({1'b1}), + .out_reset({1'b0})); + + assign tmpOE__SD_PULLUP_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{5'b11111} : {5'b11111}; + endmodule diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.vh2 b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.vh2 index 6b1877ce..bf8fbe58 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.vh2 +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.vh2 @@ -2,7 +2,7 @@ -- Conversion of USB_Bootloader.v to vh2: -- -- Cypress Semiconductor - WARP Version 6.3 IR 41 --- Sat Oct 26 18:55:17 2013 +-- Sat Mar 22 22:32:48 2014 -- USE cypress.cypress.all; @@ -125,6 +125,23 @@ TERMINAL Net_29 : bit; TERMINAL Net_28 : bit; TERMINAL Net_27 : bit; SIGNAL tmpINTERRUPT_0__SCSI_Out_net_0 : bit; +SIGNAL tmpOE__SD_PULLUP_net_4 : bit; +SIGNAL tmpOE__SD_PULLUP_net_3 : bit; +SIGNAL tmpOE__SD_PULLUP_net_2 : bit; +SIGNAL tmpOE__SD_PULLUP_net_1 : bit; +SIGNAL tmpOE__SD_PULLUP_net_0 : bit; +SIGNAL Net_88 : bit; +SIGNAL Net_87 : bit; +SIGNAL Net_86 : bit; +SIGNAL Net_85 : bit; +SIGNAL Net_84 : bit; +SIGNAL tmpIO_4__SD_PULLUP_net_4 : bit; +SIGNAL tmpIO_4__SD_PULLUP_net_3 : bit; +SIGNAL tmpIO_4__SD_PULLUP_net_2 : bit; +SIGNAL tmpIO_4__SD_PULLUP_net_1 : bit; +SIGNAL tmpIO_4__SD_PULLUP_net_0 : bit; +TERMINAL tmpSIOVREF__SD_PULLUP_net_0 : bit; +SIGNAL tmpINTERRUPT_0__SD_PULLUP_net_0 : bit; BEGIN zero <= ('0') ; @@ -454,5 +471,76 @@ SCSI_Out:cy_psoc3_pins_v1_10 out_clock_en=>one, out_reset=>zero, interrupt=>tmpINTERRUPT_0__SCSI_Out_net_0); +SD_PULLUP:cy_psoc3_pins_v1_10 + GENERIC MAP(id=>"4c15b41e-e284-4978-99e7-5aaee19bd0ce", + drive_mode=>"010010010010010", + ibuf_enabled=>"11111", + init_dr_st=>"11111", + input_sync=>"11111", + input_clk_en=>'0', + input_sync_mode=>"00000", + intr_mode=>"0000000000", + invert_in_clock=>'0', + invert_in_clock_en=>'0', + invert_in_reset=>'0', + invert_out_clock=>'0', + invert_out_clock_en=>'0', + invert_out_reset=>'0', + io_voltage=>"3.3, , , , ", + layout_mode=>"CONTIGUOUS", + output_conn=>"00000", + output_sync=>"00000", + output_clk_en=>'0', + output_mode=>"00000", + output_reset=>'0', + output_clock_mode=>"00000", + oe_sync=>"00000", + oe_conn=>"00000", + oe_reset=>'0', + pin_aliases=>",,,,", + pin_mode=>"IIIII", + por_state=>2, + sio_group_cnt=>0, + sio_hifreq=>"", + sio_hyst=>"00000", + sio_ibuf=>"00000000", + sio_info=>"0000000000", + sio_obuf=>"00000000", + sio_refsel=>"00000000", + sio_vtrip=>"00000000", + slew_rate=>"00000", + spanning=>'0', + sw_only=>'0', + vtrip=>"0000000000", + width=>5, + port_alias_required=>'0', + port_alias_group=>"", + use_annotation=>"00000", + pa_in_clock=>-1, + pa_in_clock_en=>-1, + pa_in_reset=>-1, + pa_out_clock=>-1, + pa_out_clock_en=>-1, + pa_out_reset=>-1) + PORT MAP(oe=>(one, one, one, one, + one), + y=>(zero, zero, zero, zero, + zero), + fb=>(Net_88, Net_87, Net_86, Net_85, + Net_84), + analog=>(open, open, open, open, + open), + io=>(tmpIO_4__SD_PULLUP_net_4, tmpIO_4__SD_PULLUP_net_3, tmpIO_4__SD_PULLUP_net_2, tmpIO_4__SD_PULLUP_net_1, + tmpIO_4__SD_PULLUP_net_0), + siovref=>(tmpSIOVREF__SD_PULLUP_net_0), + annotation=>(open, open, open, open, + open), + in_clock=>zero, + in_clock_en=>one, + in_reset=>zero, + out_clock=>zero, + out_clock_en=>one, + out_reset=>zero, + interrupt=>tmpINTERRUPT_0__SD_PULLUP_net_0); END R_T_L; diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_p.lib b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_p.lib index ddcbe3af..b4f81be7 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_p.lib +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_p.lib @@ -1227,6 +1227,341 @@ library (timing) { } } cell (iocell19) { + pin (in_clock) { + direction : input; + clock : true; + } + pin (in_clock_en) { + direction : input; + } + pin (in_reset) { + direction : input; + } + pin (out_clock) { + direction : input; + clock : true; + } + pin (out_clock_en) { + direction : input; + } + pin (out_reset) { + direction : input; + } + pin (pin_input) { + direction : input; + } + pin (pa_out) { + direction : output; + } + pin (oe) { + direction : input; + } + pin (pad_in) { + direction : input; + } + pin (pad_out) { + direction : output; + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 16.419; + intrinsic_fall : 16.419; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 16.419; + intrinsic_fall : 16.419; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 14.979; + intrinsic_fall : 14.979; + } + } + pin (fb) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "in_clock"; + intrinsic_rise : 1.661; + intrinsic_fall : 1.661; + } + } + } + cell (iocell20) { + pin (in_clock) { + direction : input; + clock : true; + } + pin (in_clock_en) { + direction : input; + } + pin (in_reset) { + direction : input; + } + pin (out_clock) { + direction : input; + clock : true; + } + pin (out_clock_en) { + direction : input; + } + pin (out_reset) { + direction : input; + } + pin (pin_input) { + direction : input; + } + pin (pa_out) { + direction : output; + } + pin (oe) { + direction : input; + } + pin (pad_in) { + direction : input; + } + pin (pad_out) { + direction : output; + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 17.643; + intrinsic_fall : 17.643; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 17.643; + intrinsic_fall : 17.643; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 14.995; + intrinsic_fall : 14.995; + } + } + pin (fb) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "in_clock"; + intrinsic_rise : 1.852; + intrinsic_fall : 1.852; + } + } + } + cell (iocell21) { + pin (in_clock) { + direction : input; + clock : true; + } + pin (in_clock_en) { + direction : input; + } + pin (in_reset) { + direction : input; + } + pin (out_clock) { + direction : input; + clock : true; + } + pin (out_clock_en) { + direction : input; + } + pin (out_reset) { + direction : input; + } + pin (pin_input) { + direction : input; + } + pin (pa_out) { + direction : output; + } + pin (oe) { + direction : input; + } + pin (pad_in) { + direction : input; + } + pin (pad_out) { + direction : output; + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 17.081; + intrinsic_fall : 17.081; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 17.081; + intrinsic_fall : 17.081; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 14.591; + intrinsic_fall : 14.591; + } + } + pin (fb) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "in_clock"; + intrinsic_rise : 3.163; + intrinsic_fall : 3.163; + } + } + } + cell (iocell22) { + pin (in_clock) { + direction : input; + clock : true; + } + pin (in_clock_en) { + direction : input; + } + pin (in_reset) { + direction : input; + } + pin (out_clock) { + direction : input; + clock : true; + } + pin (out_clock_en) { + direction : input; + } + pin (out_reset) { + direction : input; + } + pin (pin_input) { + direction : input; + } + pin (pa_out) { + direction : output; + } + pin (oe) { + direction : input; + } + pin (pad_in) { + direction : input; + } + pin (pad_out) { + direction : output; + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 16.646; + intrinsic_fall : 16.646; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 16.646; + intrinsic_fall : 16.646; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 14.987; + intrinsic_fall : 14.987; + } + } + pin (fb) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "in_clock"; + intrinsic_rise : 2.191; + intrinsic_fall : 2.191; + } + } + } + cell (iocell23) { + pin (in_clock) { + direction : input; + clock : true; + } + pin (in_clock_en) { + direction : input; + } + pin (in_reset) { + direction : input; + } + pin (out_clock) { + direction : input; + clock : true; + } + pin (out_clock_en) { + direction : input; + } + pin (out_reset) { + direction : input; + } + pin (pin_input) { + direction : input; + } + pin (pa_out) { + direction : output; + } + pin (oe) { + direction : input; + } + pin (pad_in) { + direction : input; + } + pin (pad_out) { + direction : output; + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 17.787; + intrinsic_fall : 17.787; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 17.787; + intrinsic_fall : 17.787; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 15.338; + intrinsic_fall : 15.338; + } + } + pin (fb) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "in_clock"; + intrinsic_rise : 2.064; + intrinsic_fall : 2.064; + } + } + } + cell (iocell24) { pin (in_clock) { direction : input; clock : true; @@ -1294,7 +1629,7 @@ library (timing) { } } } - cell (iocell20) { + cell (iocell25) { pin (in_clock) { direction : input; clock : true; diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_p.pco b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_p.pco index 60d37b3b..9bc042e2 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_p.pco +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_p.pco @@ -17,6 +17,7 @@ dont_use_location abufcell -1 -1 1 dont_use_location abufcell -1 -1 3 set_io "SCSI_Out(4)" iocell 0 5 set_io "SCSI_Out_DBx(4)" iocell 4 7 +set_io "SD_PULLUP(2)" iocell 3 3 set_io "SCSI_Out(7)" iocell 0 2 set_io "SCSI_Out_DBx(7)" iocell 4 4 set_location "\USBFS:ep_0\" interrupt -1 -1 24 @@ -34,8 +35,12 @@ set_io "SCSI_Out(2)" iocell 0 7 set_io "SCSI_Out_DBx(2)" iocell 6 1 set_io "SCSI_Out(8)" iocell 0 1 set_location "\USBFS:USB\" usbcell -1 -1 0 +set_io "SD_PULLUP(0)" iocell 3 1 +set_io "SD_PULLUP(4)" iocell 3 5 set_location "\USBFS:arb_int\" interrupt -1 -1 22 set_location "\USBFS:sof_int\" interrupt -1 -1 21 +set_io "SD_PULLUP(1)" iocell 3 2 +set_io "SD_PULLUP(3)" iocell 3 4 set_io "SCSI_Out(1)" iocell 4 2 set_io "SCSI_Out_DBx(1)" iocell 6 2 set_io "SCSI_Out(0)" iocell 4 3 diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_p.vh2 b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_p.vh2 index cb3edc50..93f1fead 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_p.vh2 +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_p.vh2 @@ -1,5 +1,5 @@ -- Project: USB_Bootloader --- Generated: 10/26/2013 18:55:19 +-- Generated: 03/22/2014 22:32:51 -- ENTITY USB_Bootloader IS @@ -21,7 +21,12 @@ ENTITY USB_Bootloader IS SCSI_Out_DBx(4)_PAD : OUT std_ulogic; SCSI_Out_DBx(5)_PAD : OUT std_ulogic; SCSI_Out_DBx(6)_PAD : OUT std_ulogic; - SCSI_Out_DBx(7)_PAD : OUT std_ulogic); + SCSI_Out_DBx(7)_PAD : OUT std_ulogic; + SD_PULLUP(0)_PAD : IN std_ulogic; + SD_PULLUP(1)_PAD : IN std_ulogic; + SD_PULLUP(2)_PAD : IN std_ulogic; + SD_PULLUP(3)_PAD : IN std_ulogic; + SD_PULLUP(4)_PAD : IN std_ulogic); ATTRIBUTE voltage_Vio1 OF __DEFAULT__ : ENTITY IS 5e0; ATTRIBUTE voltage_Vusb OF __DEFAULT__ : ENTITY IS 5e0; ATTRIBUTE voltage_Vddd OF __DEFAULT__ : ENTITY IS 5e0; @@ -63,6 +68,11 @@ ARCHITECTURE __DEFAULT__ OF USB_Bootloader IS SIGNAL SCSI_Out_DBx(5)__PA : bit; SIGNAL SCSI_Out_DBx(6)__PA : bit; SIGNAL SCSI_Out_DBx(7)__PA : bit; + SIGNAL SD_PULLUP(0)__PA : bit; + SIGNAL SD_PULLUP(1)__PA : bit; + SIGNAL SD_PULLUP(2)__PA : bit; + SIGNAL SD_PULLUP(3)__PA : bit; + SIGNAL SD_PULLUP(4)__PA : bit; SIGNAL \\\USBFS:Dm(0)\\__PA\ : bit; SIGNAL \\\USBFS:Dp(0)\\__PA\ : bit; SIGNAL \USBFS:Net_1010\ : bit; @@ -131,9 +141,19 @@ ARCHITECTURE __DEFAULT__ OF USB_Bootloader IS ATTRIBUTE Location OF SCSI_Out_DBx(6) : LABEL IS "P4[5]"; ATTRIBUTE lib_model OF SCSI_Out_DBx(7) : LABEL IS "iocell18"; ATTRIBUTE Location OF SCSI_Out_DBx(7) : LABEL IS "P4[4]"; - ATTRIBUTE lib_model OF \USBFS:Dm(0)\ : LABEL IS "iocell19"; + ATTRIBUTE lib_model OF SD_PULLUP(0) : LABEL IS "iocell19"; + ATTRIBUTE Location OF SD_PULLUP(0) : LABEL IS "P3[1]"; + ATTRIBUTE lib_model OF SD_PULLUP(1) : LABEL IS "iocell20"; + ATTRIBUTE Location OF SD_PULLUP(1) : LABEL IS "P3[2]"; + ATTRIBUTE lib_model OF SD_PULLUP(2) : LABEL IS "iocell21"; + ATTRIBUTE Location OF SD_PULLUP(2) : LABEL IS "P3[3]"; + ATTRIBUTE lib_model OF SD_PULLUP(3) : LABEL IS "iocell22"; + ATTRIBUTE Location OF SD_PULLUP(3) : LABEL IS "P3[4]"; + ATTRIBUTE lib_model OF SD_PULLUP(4) : LABEL IS "iocell23"; + ATTRIBUTE Location OF SD_PULLUP(4) : LABEL IS "P3[5]"; + ATTRIBUTE lib_model OF \USBFS:Dm(0)\ : LABEL IS "iocell24"; ATTRIBUTE Location OF \USBFS:Dm(0)\ : LABEL IS "P15[7]"; - ATTRIBUTE lib_model OF \USBFS:Dp(0)\ : LABEL IS "iocell20"; + ATTRIBUTE lib_model OF \USBFS:Dp(0)\ : LABEL IS "iocell25"; ATTRIBUTE Location OF \USBFS:Dp(0)\ : LABEL IS "P15[6]"; ATTRIBUTE Location OF \USBFS:USB\ : LABEL IS "F(USB,0)"; COMPONENT abufcell @@ -1559,6 +1579,168 @@ BEGIN out_clock_en => '1', out_reset => '0'); + SD_PULLUP:logicalport + GENERIC MAP( + drive_mode => "010010010010010", + ibuf_enabled => "11111", + id => "4c15b41e-e284-4978-99e7-5aaee19bd0ce", + init_dr_st => "11111", + input_clk_en => 0, + input_sync => "11111", + input_sync_mode => "00000", + intr_mode => "0000000000", + invert_in_clock => 0, + invert_in_clock_en => 0, + invert_in_reset => 0, + invert_out_clock => 0, + invert_out_clock_en => 0, + invert_out_reset => 0, + io_voltage => "3.3, , , , ", + layout_mode => "CONTIGUOUS", + oe_conn => "00000", + oe_reset => 0, + oe_sync => "00000", + output_clk_en => 0, + output_clock_mode => "00000", + output_conn => "00000", + output_mode => "00000", + output_reset => 0, + output_sync => "00000", + pa_in_clock => -1, + pa_in_clock_en => -1, + pa_in_reset => -1, + pa_out_clock => -1, + pa_out_clock_en => -1, + pa_out_reset => -1, + pin_aliases => ",,,,", + pin_mode => "IIIII", + por_state => 2, + port_alias_group => "", + port_alias_required => 0, + sio_group_cnt => 0, + sio_hifreq => "", + sio_hyst => "00000", + sio_ibuf => "00000000", + sio_info => "0000000000", + sio_obuf => "00000000", + sio_refsel => "00000000", + sio_vtrip => "00000000", + slew_rate => "00000", + spanning => 0, + sw_only => 0, + use_annotation => "00000", + vtrip => "0000000000", + width => 5, + in_clk_inv => 0, + in_clken_inv => 0, + in_clken_mode => 1, + in_rst_inv => 0, + out_clk_inv => 0, + out_clken_inv => 0, + out_clken_mode => 1, + out_rst_inv => 0) + PORT MAP( + in_clock_en => open, + in_reset => open, + out_clock_en => open, + out_reset => open, + in_clock => open); + + SD_PULLUP(0):iocell + GENERIC MAP( + in_sync_mode => 2, + out_sync_mode => 0, + oe_sync_mode => 0, + logicalport => "SD_PULLUP", + logicalport_pin_id => 0, + io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") + PORT MAP( + pa_out => SD_PULLUP(0)__PA, + oe => open, + pad_in => SD_PULLUP(0)_PAD, + in_clock => ClockBlock_BUS_CLK, + in_clock_en => '1', + in_reset => '0', + out_clock => open, + out_clock_en => '1', + out_reset => '0'); + + SD_PULLUP(1):iocell + GENERIC MAP( + in_sync_mode => 2, + out_sync_mode => 0, + oe_sync_mode => 0, + logicalport => "SD_PULLUP", + logicalport_pin_id => 1, + io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") + PORT MAP( + pa_out => SD_PULLUP(1)__PA, + oe => open, + pad_in => SD_PULLUP(1)_PAD, + in_clock => ClockBlock_BUS_CLK, + in_clock_en => '1', + in_reset => '0', + out_clock => open, + out_clock_en => '1', + out_reset => '0'); + + SD_PULLUP(2):iocell + GENERIC MAP( + in_sync_mode => 2, + out_sync_mode => 0, + oe_sync_mode => 0, + logicalport => "SD_PULLUP", + logicalport_pin_id => 2, + io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") + PORT MAP( + pa_out => SD_PULLUP(2)__PA, + oe => open, + pad_in => SD_PULLUP(2)_PAD, + in_clock => ClockBlock_BUS_CLK, + in_clock_en => '1', + in_reset => '0', + out_clock => open, + out_clock_en => '1', + out_reset => '0'); + + SD_PULLUP(3):iocell + GENERIC MAP( + in_sync_mode => 2, + out_sync_mode => 0, + oe_sync_mode => 0, + logicalport => "SD_PULLUP", + logicalport_pin_id => 3, + io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") + PORT MAP( + pa_out => SD_PULLUP(3)__PA, + oe => open, + pad_in => SD_PULLUP(3)_PAD, + in_clock => ClockBlock_BUS_CLK, + in_clock_en => '1', + in_reset => '0', + out_clock => open, + out_clock_en => '1', + out_reset => '0'); + + SD_PULLUP(4):iocell + GENERIC MAP( + in_sync_mode => 2, + out_sync_mode => 0, + oe_sync_mode => 0, + logicalport => "SD_PULLUP", + logicalport_pin_id => 4, + io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") + PORT MAP( + pa_out => SD_PULLUP(4)__PA, + oe => open, + pad_in => SD_PULLUP(4)_PAD, + in_clock => ClockBlock_BUS_CLK, + in_clock_en => '1', + in_reset => '0', + out_clock => open, + out_clock_en => '1', + out_reset => '0'); + \USBFS:Dm(0)\:iocell GENERIC MAP( in_sync_mode => 0, diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_r.lib b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_r.lib index ddcbe3af..b4f81be7 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_r.lib +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_r.lib @@ -1227,6 +1227,341 @@ library (timing) { } } cell (iocell19) { + pin (in_clock) { + direction : input; + clock : true; + } + pin (in_clock_en) { + direction : input; + } + pin (in_reset) { + direction : input; + } + pin (out_clock) { + direction : input; + clock : true; + } + pin (out_clock_en) { + direction : input; + } + pin (out_reset) { + direction : input; + } + pin (pin_input) { + direction : input; + } + pin (pa_out) { + direction : output; + } + pin (oe) { + direction : input; + } + pin (pad_in) { + direction : input; + } + pin (pad_out) { + direction : output; + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 16.419; + intrinsic_fall : 16.419; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 16.419; + intrinsic_fall : 16.419; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 14.979; + intrinsic_fall : 14.979; + } + } + pin (fb) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "in_clock"; + intrinsic_rise : 1.661; + intrinsic_fall : 1.661; + } + } + } + cell (iocell20) { + pin (in_clock) { + direction : input; + clock : true; + } + pin (in_clock_en) { + direction : input; + } + pin (in_reset) { + direction : input; + } + pin (out_clock) { + direction : input; + clock : true; + } + pin (out_clock_en) { + direction : input; + } + pin (out_reset) { + direction : input; + } + pin (pin_input) { + direction : input; + } + pin (pa_out) { + direction : output; + } + pin (oe) { + direction : input; + } + pin (pad_in) { + direction : input; + } + pin (pad_out) { + direction : output; + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 17.643; + intrinsic_fall : 17.643; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 17.643; + intrinsic_fall : 17.643; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 14.995; + intrinsic_fall : 14.995; + } + } + pin (fb) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "in_clock"; + intrinsic_rise : 1.852; + intrinsic_fall : 1.852; + } + } + } + cell (iocell21) { + pin (in_clock) { + direction : input; + clock : true; + } + pin (in_clock_en) { + direction : input; + } + pin (in_reset) { + direction : input; + } + pin (out_clock) { + direction : input; + clock : true; + } + pin (out_clock_en) { + direction : input; + } + pin (out_reset) { + direction : input; + } + pin (pin_input) { + direction : input; + } + pin (pa_out) { + direction : output; + } + pin (oe) { + direction : input; + } + pin (pad_in) { + direction : input; + } + pin (pad_out) { + direction : output; + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 17.081; + intrinsic_fall : 17.081; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 17.081; + intrinsic_fall : 17.081; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 14.591; + intrinsic_fall : 14.591; + } + } + pin (fb) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "in_clock"; + intrinsic_rise : 3.163; + intrinsic_fall : 3.163; + } + } + } + cell (iocell22) { + pin (in_clock) { + direction : input; + clock : true; + } + pin (in_clock_en) { + direction : input; + } + pin (in_reset) { + direction : input; + } + pin (out_clock) { + direction : input; + clock : true; + } + pin (out_clock_en) { + direction : input; + } + pin (out_reset) { + direction : input; + } + pin (pin_input) { + direction : input; + } + pin (pa_out) { + direction : output; + } + pin (oe) { + direction : input; + } + pin (pad_in) { + direction : input; + } + pin (pad_out) { + direction : output; + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 16.646; + intrinsic_fall : 16.646; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 16.646; + intrinsic_fall : 16.646; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 14.987; + intrinsic_fall : 14.987; + } + } + pin (fb) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "in_clock"; + intrinsic_rise : 2.191; + intrinsic_fall : 2.191; + } + } + } + cell (iocell23) { + pin (in_clock) { + direction : input; + clock : true; + } + pin (in_clock_en) { + direction : input; + } + pin (in_reset) { + direction : input; + } + pin (out_clock) { + direction : input; + clock : true; + } + pin (out_clock_en) { + direction : input; + } + pin (out_reset) { + direction : input; + } + pin (pin_input) { + direction : input; + } + pin (pa_out) { + direction : output; + } + pin (oe) { + direction : input; + } + pin (pad_in) { + direction : input; + } + pin (pad_out) { + direction : output; + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 17.787; + intrinsic_fall : 17.787; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 17.787; + intrinsic_fall : 17.787; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 15.338; + intrinsic_fall : 15.338; + } + } + pin (fb) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "in_clock"; + intrinsic_rise : 2.064; + intrinsic_fall : 2.064; + } + } + } + cell (iocell24) { pin (in_clock) { direction : input; clock : true; @@ -1294,7 +1629,7 @@ library (timing) { } } } - cell (iocell20) { + cell (iocell25) { pin (in_clock) { direction : input; clock : true; diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_r.vh2 b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_r.vh2 index 66183198..eb4dbe89 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_r.vh2 +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_r.vh2 @@ -1,5 +1,5 @@ -- Project: USB_Bootloader --- Generated: 10/26/2013 18:55:21 +-- Generated: 03/22/2014 22:32:52 -- ENTITY USB_Bootloader IS @@ -21,7 +21,12 @@ ENTITY USB_Bootloader IS SCSI_Out_DBx(4)_PAD : OUT std_ulogic; SCSI_Out_DBx(5)_PAD : OUT std_ulogic; SCSI_Out_DBx(6)_PAD : OUT std_ulogic; - SCSI_Out_DBx(7)_PAD : OUT std_ulogic); + SCSI_Out_DBx(7)_PAD : OUT std_ulogic; + SD_PULLUP(0)_PAD : IN std_ulogic; + SD_PULLUP(1)_PAD : IN std_ulogic; + SD_PULLUP(2)_PAD : IN std_ulogic; + SD_PULLUP(3)_PAD : IN std_ulogic; + SD_PULLUP(4)_PAD : IN std_ulogic); ATTRIBUTE voltage_Vio1 OF __DEFAULT__ : ENTITY IS 5e0; ATTRIBUTE voltage_Vusb OF __DEFAULT__ : ENTITY IS 5e0; ATTRIBUTE voltage_Vddd OF __DEFAULT__ : ENTITY IS 5e0; @@ -63,6 +68,11 @@ ARCHITECTURE __DEFAULT__ OF USB_Bootloader IS SIGNAL SCSI_Out_DBx(5)__PA : bit; SIGNAL SCSI_Out_DBx(6)__PA : bit; SIGNAL SCSI_Out_DBx(7)__PA : bit; + SIGNAL SD_PULLUP(0)__PA : bit; + SIGNAL SD_PULLUP(1)__PA : bit; + SIGNAL SD_PULLUP(2)__PA : bit; + SIGNAL SD_PULLUP(3)__PA : bit; + SIGNAL SD_PULLUP(4)__PA : bit; SIGNAL \\\USBFS:Dm(0)\\__PA\ : bit; SIGNAL \\\USBFS:Dp(0)\\__PA\ : bit; SIGNAL \USBFS:Net_1010\ : bit; @@ -132,9 +142,19 @@ ARCHITECTURE __DEFAULT__ OF USB_Bootloader IS ATTRIBUTE Location OF SCSI_Out_DBx(6) : LABEL IS "P4[5]"; ATTRIBUTE lib_model OF SCSI_Out_DBx(7) : LABEL IS "iocell18"; ATTRIBUTE Location OF SCSI_Out_DBx(7) : LABEL IS "P4[4]"; - ATTRIBUTE lib_model OF \USBFS:Dm(0)\ : LABEL IS "iocell19"; + ATTRIBUTE lib_model OF SD_PULLUP(0) : LABEL IS "iocell19"; + ATTRIBUTE Location OF SD_PULLUP(0) : LABEL IS "P3[1]"; + ATTRIBUTE lib_model OF SD_PULLUP(1) : LABEL IS "iocell20"; + ATTRIBUTE Location OF SD_PULLUP(1) : LABEL IS "P3[2]"; + ATTRIBUTE lib_model OF SD_PULLUP(2) : LABEL IS "iocell21"; + ATTRIBUTE Location OF SD_PULLUP(2) : LABEL IS "P3[3]"; + ATTRIBUTE lib_model OF SD_PULLUP(3) : LABEL IS "iocell22"; + ATTRIBUTE Location OF SD_PULLUP(3) : LABEL IS "P3[4]"; + ATTRIBUTE lib_model OF SD_PULLUP(4) : LABEL IS "iocell23"; + ATTRIBUTE Location OF SD_PULLUP(4) : LABEL IS "P3[5]"; + ATTRIBUTE lib_model OF \USBFS:Dm(0)\ : LABEL IS "iocell24"; ATTRIBUTE Location OF \USBFS:Dm(0)\ : LABEL IS "P15[7]"; - ATTRIBUTE lib_model OF \USBFS:Dp(0)\ : LABEL IS "iocell20"; + ATTRIBUTE lib_model OF \USBFS:Dp(0)\ : LABEL IS "iocell25"; ATTRIBUTE Location OF \USBFS:Dp(0)\ : LABEL IS "P15[6]"; ATTRIBUTE Location OF \USBFS:Dp\ : LABEL IS "F(PICU,8)"; ATTRIBUTE Location OF \USBFS:USB\ : LABEL IS "F(USB,0)"; @@ -1541,6 +1561,168 @@ BEGIN out_clock_en => '1', out_reset => '0'); + SD_PULLUP:logicalport + GENERIC MAP( + drive_mode => "010010010010010", + ibuf_enabled => "11111", + id => "4c15b41e-e284-4978-99e7-5aaee19bd0ce", + init_dr_st => "11111", + input_clk_en => 0, + input_sync => "11111", + input_sync_mode => "00000", + intr_mode => "0000000000", + invert_in_clock => 0, + invert_in_clock_en => 0, + invert_in_reset => 0, + invert_out_clock => 0, + invert_out_clock_en => 0, + invert_out_reset => 0, + io_voltage => "3.3, , , , ", + layout_mode => "CONTIGUOUS", + oe_conn => "00000", + oe_reset => 0, + oe_sync => "00000", + output_clk_en => 0, + output_clock_mode => "00000", + output_conn => "00000", + output_mode => "00000", + output_reset => 0, + output_sync => "00000", + pa_in_clock => -1, + pa_in_clock_en => -1, + pa_in_reset => -1, + pa_out_clock => -1, + pa_out_clock_en => -1, + pa_out_reset => -1, + pin_aliases => ",,,,", + pin_mode => "IIIII", + por_state => 2, + port_alias_group => "", + port_alias_required => 0, + sio_group_cnt => 0, + sio_hifreq => "", + sio_hyst => "00000", + sio_ibuf => "00000000", + sio_info => "0000000000", + sio_obuf => "00000000", + sio_refsel => "00000000", + sio_vtrip => "00000000", + slew_rate => "00000", + spanning => 0, + sw_only => 0, + use_annotation => "00000", + vtrip => "0000000000", + width => 5, + in_clk_inv => 0, + in_clken_inv => 0, + in_clken_mode => 1, + in_rst_inv => 0, + out_clk_inv => 0, + out_clken_inv => 0, + out_clken_mode => 1, + out_rst_inv => 0) + PORT MAP( + in_clock_en => open, + in_reset => open, + out_clock_en => open, + out_reset => open, + in_clock => open); + + SD_PULLUP(0):iocell + GENERIC MAP( + in_sync_mode => 2, + out_sync_mode => 0, + oe_sync_mode => 0, + logicalport => "SD_PULLUP", + logicalport_pin_id => 0, + io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") + PORT MAP( + pa_out => SD_PULLUP(0)__PA, + oe => open, + pad_in => SD_PULLUP(0)_PAD, + in_clock => ClockBlock_BUS_CLK, + in_clock_en => '1', + in_reset => '0', + out_clock => open, + out_clock_en => '1', + out_reset => '0'); + + SD_PULLUP(1):iocell + GENERIC MAP( + in_sync_mode => 2, + out_sync_mode => 0, + oe_sync_mode => 0, + logicalport => "SD_PULLUP", + logicalport_pin_id => 1, + io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") + PORT MAP( + pa_out => SD_PULLUP(1)__PA, + oe => open, + pad_in => SD_PULLUP(1)_PAD, + in_clock => ClockBlock_BUS_CLK, + in_clock_en => '1', + in_reset => '0', + out_clock => open, + out_clock_en => '1', + out_reset => '0'); + + SD_PULLUP(2):iocell + GENERIC MAP( + in_sync_mode => 2, + out_sync_mode => 0, + oe_sync_mode => 0, + logicalport => "SD_PULLUP", + logicalport_pin_id => 2, + io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") + PORT MAP( + pa_out => SD_PULLUP(2)__PA, + oe => open, + pad_in => SD_PULLUP(2)_PAD, + in_clock => ClockBlock_BUS_CLK, + in_clock_en => '1', + in_reset => '0', + out_clock => open, + out_clock_en => '1', + out_reset => '0'); + + SD_PULLUP(3):iocell + GENERIC MAP( + in_sync_mode => 2, + out_sync_mode => 0, + oe_sync_mode => 0, + logicalport => "SD_PULLUP", + logicalport_pin_id => 3, + io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") + PORT MAP( + pa_out => SD_PULLUP(3)__PA, + oe => open, + pad_in => SD_PULLUP(3)_PAD, + in_clock => ClockBlock_BUS_CLK, + in_clock_en => '1', + in_reset => '0', + out_clock => open, + out_clock_en => '1', + out_reset => '0'); + + SD_PULLUP(4):iocell + GENERIC MAP( + in_sync_mode => 2, + out_sync_mode => 0, + oe_sync_mode => 0, + logicalport => "SD_PULLUP", + logicalport_pin_id => 4, + io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") + PORT MAP( + pa_out => SD_PULLUP(4)__PA, + oe => open, + pad_in => SD_PULLUP(4)_PAD, + in_clock => ClockBlock_BUS_CLK, + in_clock_en => '1', + in_reset => '0', + out_clock => open, + out_clock_en => '1', + out_reset => '0'); + \USBFS:Dm(0)\:iocell GENERIC MAP( in_sync_mode => 0, diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_t.lib b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_t.lib index ddcbe3af..b4f81be7 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_t.lib +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_t.lib @@ -1227,6 +1227,341 @@ library (timing) { } } cell (iocell19) { + pin (in_clock) { + direction : input; + clock : true; + } + pin (in_clock_en) { + direction : input; + } + pin (in_reset) { + direction : input; + } + pin (out_clock) { + direction : input; + clock : true; + } + pin (out_clock_en) { + direction : input; + } + pin (out_reset) { + direction : input; + } + pin (pin_input) { + direction : input; + } + pin (pa_out) { + direction : output; + } + pin (oe) { + direction : input; + } + pin (pad_in) { + direction : input; + } + pin (pad_out) { + direction : output; + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 16.419; + intrinsic_fall : 16.419; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 16.419; + intrinsic_fall : 16.419; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 14.979; + intrinsic_fall : 14.979; + } + } + pin (fb) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "in_clock"; + intrinsic_rise : 1.661; + intrinsic_fall : 1.661; + } + } + } + cell (iocell20) { + pin (in_clock) { + direction : input; + clock : true; + } + pin (in_clock_en) { + direction : input; + } + pin (in_reset) { + direction : input; + } + pin (out_clock) { + direction : input; + clock : true; + } + pin (out_clock_en) { + direction : input; + } + pin (out_reset) { + direction : input; + } + pin (pin_input) { + direction : input; + } + pin (pa_out) { + direction : output; + } + pin (oe) { + direction : input; + } + pin (pad_in) { + direction : input; + } + pin (pad_out) { + direction : output; + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 17.643; + intrinsic_fall : 17.643; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 17.643; + intrinsic_fall : 17.643; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 14.995; + intrinsic_fall : 14.995; + } + } + pin (fb) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "in_clock"; + intrinsic_rise : 1.852; + intrinsic_fall : 1.852; + } + } + } + cell (iocell21) { + pin (in_clock) { + direction : input; + clock : true; + } + pin (in_clock_en) { + direction : input; + } + pin (in_reset) { + direction : input; + } + pin (out_clock) { + direction : input; + clock : true; + } + pin (out_clock_en) { + direction : input; + } + pin (out_reset) { + direction : input; + } + pin (pin_input) { + direction : input; + } + pin (pa_out) { + direction : output; + } + pin (oe) { + direction : input; + } + pin (pad_in) { + direction : input; + } + pin (pad_out) { + direction : output; + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 17.081; + intrinsic_fall : 17.081; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 17.081; + intrinsic_fall : 17.081; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 14.591; + intrinsic_fall : 14.591; + } + } + pin (fb) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "in_clock"; + intrinsic_rise : 3.163; + intrinsic_fall : 3.163; + } + } + } + cell (iocell22) { + pin (in_clock) { + direction : input; + clock : true; + } + pin (in_clock_en) { + direction : input; + } + pin (in_reset) { + direction : input; + } + pin (out_clock) { + direction : input; + clock : true; + } + pin (out_clock_en) { + direction : input; + } + pin (out_reset) { + direction : input; + } + pin (pin_input) { + direction : input; + } + pin (pa_out) { + direction : output; + } + pin (oe) { + direction : input; + } + pin (pad_in) { + direction : input; + } + pin (pad_out) { + direction : output; + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 16.646; + intrinsic_fall : 16.646; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 16.646; + intrinsic_fall : 16.646; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 14.987; + intrinsic_fall : 14.987; + } + } + pin (fb) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "in_clock"; + intrinsic_rise : 2.191; + intrinsic_fall : 2.191; + } + } + } + cell (iocell23) { + pin (in_clock) { + direction : input; + clock : true; + } + pin (in_clock_en) { + direction : input; + } + pin (in_reset) { + direction : input; + } + pin (out_clock) { + direction : input; + clock : true; + } + pin (out_clock_en) { + direction : input; + } + pin (out_reset) { + direction : input; + } + pin (pin_input) { + direction : input; + } + pin (pa_out) { + direction : output; + } + pin (oe) { + direction : input; + } + pin (pad_in) { + direction : input; + } + pin (pad_out) { + direction : output; + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 17.787; + intrinsic_fall : 17.787; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 17.787; + intrinsic_fall : 17.787; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 15.338; + intrinsic_fall : 15.338; + } + } + pin (fb) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "in_clock"; + intrinsic_rise : 2.064; + intrinsic_fall : 2.064; + } + } + } + cell (iocell24) { pin (in_clock) { direction : input; clock : true; @@ -1294,7 +1629,7 @@ library (timing) { } } } - cell (iocell20) { + cell (iocell25) { pin (in_clock) { direction : input; clock : true; diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_t.vh2 b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_t.vh2 index ea0fe503..fa0079fc 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_t.vh2 +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_t.vh2 @@ -1,5 +1,5 @@ --- Project: W:\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj --- Generated: 10/26/2013 18:55:25 +-- Project: W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj +-- Generated: 03/22/2014 22:32:56 -- ENTITY USB_Bootloader IS @@ -21,7 +21,12 @@ ENTITY USB_Bootloader IS SCSI_Out_DBx(4)_PAD : OUT std_ulogic; SCSI_Out_DBx(5)_PAD : OUT std_ulogic; SCSI_Out_DBx(6)_PAD : OUT std_ulogic; - SCSI_Out_DBx(7)_PAD : OUT std_ulogic); + SCSI_Out_DBx(7)_PAD : OUT std_ulogic; + SD_PULLUP(0)_PAD : IN std_ulogic; + SD_PULLUP(1)_PAD : IN std_ulogic; + SD_PULLUP(2)_PAD : IN std_ulogic; + SD_PULLUP(3)_PAD : IN std_ulogic; + SD_PULLUP(4)_PAD : IN std_ulogic); ATTRIBUTE voltage_Vio1 OF __DEFAULT__ : ENTITY IS 5e0; ATTRIBUTE voltage_Vusb OF __DEFAULT__ : ENTITY IS 5e0; ATTRIBUTE voltage_Vddd OF __DEFAULT__ : ENTITY IS 5e0; @@ -63,6 +68,11 @@ ARCHITECTURE __DEFAULT__ OF USB_Bootloader IS SIGNAL SCSI_Out_DBx(5)__PA : bit; SIGNAL SCSI_Out_DBx(6)__PA : bit; SIGNAL SCSI_Out_DBx(7)__PA : bit; + SIGNAL SD_PULLUP(0)__PA : bit; + SIGNAL SD_PULLUP(1)__PA : bit; + SIGNAL SD_PULLUP(2)__PA : bit; + SIGNAL SD_PULLUP(3)__PA : bit; + SIGNAL SD_PULLUP(4)__PA : bit; SIGNAL \\\USBFS:Dm(0)\\__PA\ : bit; SIGNAL \\\USBFS:Dp(0)\\__PA\ : bit; SIGNAL \USBFS:Net_1010\ : bit; @@ -132,9 +142,19 @@ ARCHITECTURE __DEFAULT__ OF USB_Bootloader IS ATTRIBUTE Location OF SCSI_Out_DBx(6) : LABEL IS "P4[5]"; ATTRIBUTE lib_model OF SCSI_Out_DBx(7) : LABEL IS "iocell18"; ATTRIBUTE Location OF SCSI_Out_DBx(7) : LABEL IS "P4[4]"; - ATTRIBUTE lib_model OF \USBFS:Dm(0)\ : LABEL IS "iocell19"; + ATTRIBUTE lib_model OF SD_PULLUP(0) : LABEL IS "iocell19"; + ATTRIBUTE Location OF SD_PULLUP(0) : LABEL IS "P3[1]"; + ATTRIBUTE lib_model OF SD_PULLUP(1) : LABEL IS "iocell20"; + ATTRIBUTE Location OF SD_PULLUP(1) : LABEL IS "P3[2]"; + ATTRIBUTE lib_model OF SD_PULLUP(2) : LABEL IS "iocell21"; + ATTRIBUTE Location OF SD_PULLUP(2) : LABEL IS "P3[3]"; + ATTRIBUTE lib_model OF SD_PULLUP(3) : LABEL IS "iocell22"; + ATTRIBUTE Location OF SD_PULLUP(3) : LABEL IS "P3[4]"; + ATTRIBUTE lib_model OF SD_PULLUP(4) : LABEL IS "iocell23"; + ATTRIBUTE Location OF SD_PULLUP(4) : LABEL IS "P3[5]"; + ATTRIBUTE lib_model OF \USBFS:Dm(0)\ : LABEL IS "iocell24"; ATTRIBUTE Location OF \USBFS:Dm(0)\ : LABEL IS "P15[7]"; - ATTRIBUTE lib_model OF \USBFS:Dp(0)\ : LABEL IS "iocell20"; + ATTRIBUTE lib_model OF \USBFS:Dp(0)\ : LABEL IS "iocell25"; ATTRIBUTE Location OF \USBFS:Dp(0)\ : LABEL IS "P15[6]"; ATTRIBUTE Location OF \USBFS:Dp\ : LABEL IS "F(PICU,8)"; ATTRIBUTE Location OF \USBFS:USB\ : LABEL IS "F(USB,0)"; @@ -1541,6 +1561,168 @@ BEGIN out_clock_en => '1', out_reset => '0'); + SD_PULLUP:logicalport + GENERIC MAP( + drive_mode => "010010010010010", + ibuf_enabled => "11111", + id => "4c15b41e-e284-4978-99e7-5aaee19bd0ce", + init_dr_st => "11111", + input_clk_en => 0, + input_sync => "11111", + input_sync_mode => "00000", + intr_mode => "0000000000", + invert_in_clock => 0, + invert_in_clock_en => 0, + invert_in_reset => 0, + invert_out_clock => 0, + invert_out_clock_en => 0, + invert_out_reset => 0, + io_voltage => "3.3, , , , ", + layout_mode => "CONTIGUOUS", + oe_conn => "00000", + oe_reset => 0, + oe_sync => "00000", + output_clk_en => 0, + output_clock_mode => "00000", + output_conn => "00000", + output_mode => "00000", + output_reset => 0, + output_sync => "00000", + pa_in_clock => -1, + pa_in_clock_en => -1, + pa_in_reset => -1, + pa_out_clock => -1, + pa_out_clock_en => -1, + pa_out_reset => -1, + pin_aliases => ",,,,", + pin_mode => "IIIII", + por_state => 2, + port_alias_group => "", + port_alias_required => 0, + sio_group_cnt => 0, + sio_hifreq => "", + sio_hyst => "00000", + sio_ibuf => "00000000", + sio_info => "0000000000", + sio_obuf => "00000000", + sio_refsel => "00000000", + sio_vtrip => "00000000", + slew_rate => "00000", + spanning => 0, + sw_only => 0, + use_annotation => "00000", + vtrip => "0000000000", + width => 5, + in_clk_inv => 0, + in_clken_inv => 0, + in_clken_mode => 1, + in_rst_inv => 0, + out_clk_inv => 0, + out_clken_inv => 0, + out_clken_mode => 1, + out_rst_inv => 0) + PORT MAP( + in_clock_en => open, + in_reset => open, + out_clock_en => open, + out_reset => open, + in_clock => open); + + SD_PULLUP(0):iocell + GENERIC MAP( + in_sync_mode => 2, + out_sync_mode => 0, + oe_sync_mode => 0, + logicalport => "SD_PULLUP", + logicalport_pin_id => 0, + io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") + PORT MAP( + pa_out => SD_PULLUP(0)__PA, + oe => open, + pad_in => SD_PULLUP(0)_PAD, + in_clock => ClockBlock_BUS_CLK, + in_clock_en => '1', + in_reset => '0', + out_clock => open, + out_clock_en => '1', + out_reset => '0'); + + SD_PULLUP(1):iocell + GENERIC MAP( + in_sync_mode => 2, + out_sync_mode => 0, + oe_sync_mode => 0, + logicalport => "SD_PULLUP", + logicalport_pin_id => 1, + io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") + PORT MAP( + pa_out => SD_PULLUP(1)__PA, + oe => open, + pad_in => SD_PULLUP(1)_PAD, + in_clock => ClockBlock_BUS_CLK, + in_clock_en => '1', + in_reset => '0', + out_clock => open, + out_clock_en => '1', + out_reset => '0'); + + SD_PULLUP(2):iocell + GENERIC MAP( + in_sync_mode => 2, + out_sync_mode => 0, + oe_sync_mode => 0, + logicalport => "SD_PULLUP", + logicalport_pin_id => 2, + io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") + PORT MAP( + pa_out => SD_PULLUP(2)__PA, + oe => open, + pad_in => SD_PULLUP(2)_PAD, + in_clock => ClockBlock_BUS_CLK, + in_clock_en => '1', + in_reset => '0', + out_clock => open, + out_clock_en => '1', + out_reset => '0'); + + SD_PULLUP(3):iocell + GENERIC MAP( + in_sync_mode => 2, + out_sync_mode => 0, + oe_sync_mode => 0, + logicalport => "SD_PULLUP", + logicalport_pin_id => 3, + io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") + PORT MAP( + pa_out => SD_PULLUP(3)__PA, + oe => open, + pad_in => SD_PULLUP(3)_PAD, + in_clock => ClockBlock_BUS_CLK, + in_clock_en => '1', + in_reset => '0', + out_clock => open, + out_clock_en => '1', + out_reset => '0'); + + SD_PULLUP(4):iocell + GENERIC MAP( + in_sync_mode => 2, + out_sync_mode => 0, + oe_sync_mode => 0, + logicalport => "SD_PULLUP", + logicalport_pin_id => 4, + io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") + PORT MAP( + pa_out => SD_PULLUP(4)__PA, + oe => open, + pad_in => SD_PULLUP(4)_PAD, + in_clock => ClockBlock_BUS_CLK, + in_clock_en => '1', + in_reset => '0', + out_clock => open, + out_clock_en => '1', + out_reset => '0'); + \USBFS:Dm(0)\:iocell GENERIC MAP( in_sync_mode => 0, diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_timing.html b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_timing.html index 517ee041..83b2bc27 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_timing.html +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_timing.html @@ -539,7 +539,7 @@ function getElementsByClass(rootNode, elemName, className) Project : USB_Bootloader Build Time : - 10/26/13 18:55:25 + 03/22/14 22:32:57 Device : CY8C5267AXI-LP051 Temperature : diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_u.sdc b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_u.sdc index 4ce34e26..9a6a7313 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_u.sdc +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_u.sdc @@ -1,3 +1,3 @@ -# Component constraints for W:\SCSI2SD\USB_Bootloader.cydsn\TopDesign\TopDesign.cysch -# Project: W:\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -# Date: Sat, 26 Oct 2013 08:55:15 GMT +# Component constraints for W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\TopDesign\TopDesign.cysch +# Project: W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj +# Date: Sat, 22 Mar 2014 12:32:47 GMT diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/bitstream.txt b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/bitstream.txt index b4c04047..50436bf8 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/bitstream.txt +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/bitstream.txt @@ -18,807 +18,808 @@ 00000038: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # IOPORT_3 (count=7) -00000048: 00 00 00 00 00 00 00 -# IOPINS0_3 (count=16) -0000004f: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - +00000048: 00 00 00 00 3e 00 00 +# IOPINS0_3 (count=8) +0000004f: 00 3e 00 00 00 00 00 00 +# IOPINS1_3 + 0x00000009 (count=5) +00000057: 00 00 00 00 00 # IOPORT_4 (count=7) -0000005f: 00 00 00 00 00 00 00 +0000005c: 00 00 00 00 00 00 00 # IOPINS0_4 (count=8) -00000066: 00 fc fc 00 00 00 00 00 +00000063: 00 fc fc 00 00 00 00 00 # IOPINS1_4 + 0x00000009 (count=5) -0000006e: 00 00 00 00 00 +0000006b: 00 00 00 00 00 # IOPORT_5 (count=7) -00000073: 00 00 00 00 00 00 00 +00000070: 00 00 00 00 00 00 00 # IOPINS0_5 (count=16) -0000007a: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000077: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # IOPORT_6 (count=7) -0000008a: 00 00 00 00 00 00 00 +00000087: 00 00 00 00 00 00 00 # IOPINS0_6 (count=8) -00000091: 00 0f 0f 00 00 00 00 00 +0000008e: 00 0f 0f 00 00 00 00 00 # IOPINS1_6 + 0x00000009 (count=5) -00000099: 00 00 00 00 00 +00000096: 00 00 00 00 00 # IOPORT_7 (count=6) -0000009e: 00 00 00 00 00 00 +0000009b: 00 00 00 00 00 00 # IOPINS0_7 (count=16) -000000a4: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000000a1: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # IOPORT_8 (count=7) -000000b4: 00 00 00 00 40 00 00 +000000b1: 00 00 00 00 40 00 00 # IOPINS0_8 (count=10) -000000bb: 00 00 00 00 00 00 00 00 c0 00 +000000b8: 00 00 00 00 00 00 00 00 c0 00 # IOPINS1_8 + 0x0000000B (count=5) -000000c5: 00 00 00 00 00 +000000c2: 00 00 00 00 00 # IDMUX_IRQ (count=8) -000000ca: 0a 00 00 00 00 00 00 00 +000000c7: 0a 00 00 00 00 00 00 00 # CYDEV_SLOWCLK_ILO_CR0 (count=1) -000000d2: 06 +000000cf: 06 # CYDEV_FASTCLK_IMO_CR (count=1) -000000d3: 52 +000000d0: 52 # CYDEV_FASTCLK_PLL_P (count=2) -000000d4: 18 08 +000000d1: 18 08 # CYDEV_FASTCLK_PLL_CFG0 (count=2) -000000d6: 51 12 +000000d3: 51 12 # CYDEV_CLKDIST_MSTR0 (count=2) -000000d8: 00 01 +000000d5: 00 01 # CYDEV_CLKDIST_MSTR0 (count=1) -000000da: 07 +000000d7: 07 # CYDEV_CLKDIST_BCFG0 (count=1) -000000db: 00 +000000d8: 00 # CYDEV_CLKDIST_BCFG2 (count=1) -000000dc: 48 +000000d9: 48 # CYDEV_CLKDIST_MSTR0 (count=1) -000000dd: 00 +000000da: 00 # CYDEV_CLKDIST_UCFG (count=1) -000000de: 00 +000000db: 00 # CYDEV_CLKDIST_LD (count=1) -000000df: 02 +000000dc: 02 # PICU_8 (count=8) -000000e0: 00 00 00 00 00 00 02 00 +000000dd: 00 00 00 00 00 00 02 00 # UDB_1_5_0_CONFIG (count=128) -000000e8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000000f8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000108: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000118: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000128: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000138: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000148: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000158: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000000e5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000000f5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000105: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000115: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000125: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000135: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000145: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000155: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # UDB_1_5_1_CONFIG (count=128) -00000168: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000178: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000188: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000198: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000001a8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000001b8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000001c8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000001d8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000165: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000175: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000185: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000195: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000001a5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000001b5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000001c5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000001d5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # UDB_1_4_1_CONFIG (count=128) -000001e8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000001f8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000208: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000218: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000228: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000238: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000248: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000258: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000001e5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000001f5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000205: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000215: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000225: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000235: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000245: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000255: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # UDB_1_4_0_CONFIG (count=128) -00000268: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000278: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000288: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000298: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000002a8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000002b8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000002c8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000002d8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000265: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000275: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000285: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000295: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000002a5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000002b5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000002c5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000002d5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # UDB_1_3_0_CONFIG (count=128) -000002e8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000002f8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000308: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000318: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000328: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000338: 00 00 00 00 00 00 00 00 00 00 00 00 00 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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002205: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002215: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002225: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002235: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # DSI3_2_HV_ROUTING + 0x00000080 (count=128) -00002248: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002258: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002268: 00 00 00 00 00 00 40 80 00 00 00 00 00 00 00 00 -00002278: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002288: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002298: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000022a8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000022b8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002245: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002255: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002265: 00 00 00 00 00 00 40 80 00 00 00 00 00 00 00 00 +00002275: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002285: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002295: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000022a5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000022b5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # DSISWITCH_1_3 (count=128) -000022c8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000022d8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000022e8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000022f8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002308: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002318: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002328: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002338: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000022c5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000022d5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000022e5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000022f5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002305: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002315: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002325: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002335: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # DSI3_3_HV_ROUTING + 0x00000080 (count=128) -00002348: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002358: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002368: 00 00 00 00 00 00 40 80 00 00 00 00 00 00 00 00 -00002378: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002388: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002398: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000023a8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000023b8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002345: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002355: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002365: 00 00 00 00 00 00 40 80 00 00 00 00 00 00 00 00 +00002375: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002385: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002395: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000023a5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000023b5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # DSISWITCH_1_4 (count=128) -000023c8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000023d8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000023e8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000023f8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002408: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002418: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002428: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002438: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000023c5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000023d5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000023e5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000023f5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002405: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002415: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002425: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002435: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # DSI3_4_HV_ROUTING + 0x00000080 (count=128) -00002448: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002458: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002468: 00 00 00 00 00 00 40 80 00 00 00 00 00 00 00 00 -00002478: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002488: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002498: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000024a8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000024b8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002445: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002455: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002465: 00 00 00 00 00 00 40 80 00 00 00 00 00 00 00 00 +00002475: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002485: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002495: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000024a5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000024b5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # DSISWITCH_1_5 (count=128) -000024c8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000024d8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000024e8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000024f8: 00 00 00 80 00 00 40 00 00 00 00 00 00 00 00 00 -00002508: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002518: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002528: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002538: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000024c5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000024d5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000024e5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000024f5: 00 00 00 80 00 00 40 00 00 00 00 00 00 00 00 00 +00002505: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002515: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002525: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002535: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # DSI3_5_HV_ROUTING + 0x00000080 (count=128) -00002548: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002558: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002568: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002578: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002588: 00 00 00 00 00 00 00 00 00 00 00 00 30 00 00 00 -00002598: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000025a8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000025b8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002545: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002555: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002565: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002575: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00002585: 00 00 00 00 00 00 00 00 00 00 00 00 30 00 00 00 +00002595: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000025a5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000025b5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevice.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevice.h index 8263e30a..5f1b198d 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevice.h +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevice.h @@ -1,7 +1,7 @@ /******************************************************************************* * FILENAME: cydevice.h * OBSOLETE: Do not use this file. Use the _trm version instead. -* PSoC Creator 3.0 +* PSoC Creator 3.0 Component Pack 7 * * DESCRIPTION: * This file provides all of the address values for the entire PSoC device. diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevice_trm.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevice_trm.h index 08d77aa1..e2c0687f 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevice_trm.h +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevice_trm.h @@ -1,7 +1,7 @@ /******************************************************************************* * FILENAME: cydevice_trm.h * -* PSoC Creator 3.0 +* PSoC Creator 3.0 Component Pack 7 * * DESCRIPTION: * This file provides all of the address values for the entire PSoC device. diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevicegnu.inc b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevicegnu.inc index 833c2b6f..1776ef90 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevicegnu.inc +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevicegnu.inc @@ -1,7 +1,7 @@ /******************************************************************************* * FILENAME: cydevicegnu.inc * OBSOLETE: Do not use this file. Use the _trm version instead. -* PSoC Creator 3.0 +* PSoC Creator 3.0 Component Pack 7 * * DESCRIPTION: * This file provides all of the address values for the entire PSoC device. diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevicegnu_trm.inc b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevicegnu_trm.inc index ffbe68b0..3c24869c 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevicegnu_trm.inc +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevicegnu_trm.inc @@ -1,7 +1,7 @@ /******************************************************************************* * FILENAME: cydevicegnu_trm.inc * -* PSoC Creator 3.0 +* PSoC Creator 3.0 Component Pack 7 * * DESCRIPTION: * This file provides all of the address values for the entire PSoC device. diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydeviceiar.inc b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydeviceiar.inc index 8556d0a3..e4f1a443 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydeviceiar.inc +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydeviceiar.inc @@ -1,7 +1,7 @@ ; ; FILENAME: cydeviceiar.inc ; OBSOLETE: Do not use this file. Use the _trm version instead. -; PSoC Creator 3.0 +; PSoC Creator 3.0 Component Pack 7 ; ; DESCRIPTION: ; This file provides all of the address values for the entire PSoC device. diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydeviceiar_trm.inc b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydeviceiar_trm.inc index ea4e01d4..ebd1b1dc 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydeviceiar_trm.inc +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydeviceiar_trm.inc @@ -1,7 +1,7 @@ ; ; FILENAME: cydeviceiar_trm.inc ; -; PSoC Creator 3.0 +; PSoC Creator 3.0 Component Pack 7 ; ; DESCRIPTION: ; This file provides all of the address values for the entire PSoC device. diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevicerv.inc b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevicerv.inc index 4c8a5376..4ed74edd 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevicerv.inc +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevicerv.inc @@ -1,7 +1,7 @@ ; ; FILENAME: cydevicerv.inc ; OBSOLETE: Do not use this file. Use the _trm version instead. -; PSoC Creator 3.0 +; PSoC Creator 3.0 Component Pack 7 ; ; DESCRIPTION: ; This file provides all of the address values for the entire PSoC device. diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevicerv_trm.inc b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevicerv_trm.inc index 232c2fc0..d4d800c6 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevicerv_trm.inc +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevicerv_trm.inc @@ -1,7 +1,7 @@ ; ; FILENAME: cydevicerv_trm.inc ; -; PSoC Creator 3.0 +; PSoC Creator 3.0 Component Pack 7 ; ; DESCRIPTION: ; This file provides all of the address values for the entire PSoC device. diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitter.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitter.h index 8c2b1e86..c8ba6468 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitter.h +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitter.h @@ -507,6 +507,54 @@ #define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +/* SD_PULLUP */ +#define SD_PULLUP__0__MASK 0x02u +#define SD_PULLUP__0__PC CYREG_PRT3_PC1 +#define SD_PULLUP__0__PORT 3u +#define SD_PULLUP__0__SHIFT 1 +#define SD_PULLUP__1__MASK 0x04u +#define SD_PULLUP__1__PC CYREG_PRT3_PC2 +#define SD_PULLUP__1__PORT 3u +#define SD_PULLUP__1__SHIFT 2 +#define SD_PULLUP__2__MASK 0x08u +#define SD_PULLUP__2__PC CYREG_PRT3_PC3 +#define SD_PULLUP__2__PORT 3u +#define SD_PULLUP__2__SHIFT 3 +#define SD_PULLUP__3__MASK 0x10u +#define SD_PULLUP__3__PC CYREG_PRT3_PC4 +#define SD_PULLUP__3__PORT 3u +#define SD_PULLUP__3__SHIFT 4 +#define SD_PULLUP__4__MASK 0x20u +#define SD_PULLUP__4__PC CYREG_PRT3_PC5 +#define SD_PULLUP__4__PORT 3u +#define SD_PULLUP__4__SHIFT 5 +#define SD_PULLUP__AG CYREG_PRT3_AG +#define SD_PULLUP__AMUX CYREG_PRT3_AMUX +#define SD_PULLUP__BIE CYREG_PRT3_BIE +#define SD_PULLUP__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_PULLUP__BYP CYREG_PRT3_BYP +#define SD_PULLUP__CTL CYREG_PRT3_CTL +#define SD_PULLUP__DM0 CYREG_PRT3_DM0 +#define SD_PULLUP__DM1 CYREG_PRT3_DM1 +#define SD_PULLUP__DM2 CYREG_PRT3_DM2 +#define SD_PULLUP__DR CYREG_PRT3_DR +#define SD_PULLUP__INP_DIS CYREG_PRT3_INP_DIS +#define SD_PULLUP__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_PULLUP__LCD_EN CYREG_PRT3_LCD_EN +#define SD_PULLUP__MASK 0x3Eu +#define SD_PULLUP__PORT 3u +#define SD_PULLUP__PRT CYREG_PRT3_PRT +#define SD_PULLUP__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_PULLUP__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_PULLUP__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_PULLUP__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_PULLUP__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_PULLUP__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_PULLUP__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_PULLUP__PS CYREG_PRT3_PS +#define SD_PULLUP__SHIFT 1 +#define SD_PULLUP__SLW CYREG_PRT3_SLW + /* USBFS_USB */ #define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG #define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitter_cfg.c b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitter_cfg.c index 090e521d..c15b7b65 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitter_cfg.c +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitter_cfg.c @@ -1,6 +1,6 @@ /******************************************************************************* * FILENAME: cyfitter_cfg.c -* PSoC Creator 3.0 +* PSoC Creator 3.0 Component Pack 7 * * Description: * This file is automatically generated by PSoC Creator with device @@ -311,6 +311,10 @@ void cyfitter_cfg(void) static const uint8 CYCODE BS_IOPINS0_8_VAL[] = { 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xC0u, 0x00u}; + /* IOPINS0_3 Address: CYREG_PRT3_DM0 Size (bytes): 8 */ + static const uint8 CYCODE BS_IOPINS0_3_VAL[] = { + 0x00u, 0x3Eu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + /* IOPINS0_4 Address: CYREG_PRT4_DM0 Size (bytes): 8 */ static const uint8 CYCODE BS_IOPINS0_4_VAL[] = { 0x00u, 0xFCu, 0xFCu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; @@ -335,7 +339,7 @@ void cyfitter_cfg(void) { static const uint32 CYCODE cy_cfg_addr_table[] = { 0x40004501u, /* Base address: 0x40004500 Count: 1 */ - 0x40005201u, /* Base address: 0x40005200 Count: 1 */ + 0x40005202u, /* Base address: 0x40005200 Count: 2 */ 0x40011701u, /* Base address: 0x40011700 Count: 1 */ 0x40011901u, /* Base address: 0x40011900 Count: 1 */ 0x40014003u, /* Base address: 0x40014000 Count: 3 */ @@ -350,6 +354,7 @@ void cyfitter_cfg(void) static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x7Eu, 0x02u}, + {0x1Cu, 0x3Eu}, {0x7Cu, 0x40u}, {0xEEu, 0x0Au}, {0xEEu, 0x0Au}, @@ -382,7 +387,7 @@ void cyfitter_cfg(void) static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ - {(void CYFAR *)(CYREG_PRT1_DR), 48u}, + {(void CYFAR *)(CYREG_PRT1_DR), 32u}, {(void CYFAR *)(CYREG_PRT5_DR), 16u}, {(void CYFAR *)(CYREG_PRT12_DR), 16u}, {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u}, @@ -415,6 +420,7 @@ void cyfitter_cfg(void) /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT0_DM0), (const void CYCODE *)(BS_IOPINS0_0_VAL), 8u); CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT15_DR), (const void CYCODE *)(BS_IOPINS0_8_VAL), 10u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT3_DM0), (const void CYCODE *)(BS_IOPINS0_3_VAL), 8u); CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT4_DM0), (const void CYCODE *)(BS_IOPINS0_4_VAL), 8u); CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT6_DM0), (const void CYCODE *)(BS_IOPINS0_6_VAL), 8u); diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitter_cfg.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitter_cfg.h index 02880d0e..9481fd38 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitter_cfg.h +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitter_cfg.h @@ -1,6 +1,6 @@ /******************************************************************************* * FILENAME: cyfitter_cfg.h -* PSoC Creator 3.0 +* PSoC Creator 3.0 Component Pack 7 * * Description: * This file is automatically generated by PSoC Creator. diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfittergnu.inc b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfittergnu.inc index 95fa17a3..e370ffad 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfittergnu.inc +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfittergnu.inc @@ -507,6 +507,54 @@ .set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +/* SD_PULLUP */ +.set SD_PULLUP__0__MASK, 0x02 +.set SD_PULLUP__0__PC, CYREG_PRT3_PC1 +.set SD_PULLUP__0__PORT, 3 +.set SD_PULLUP__0__SHIFT, 1 +.set SD_PULLUP__1__MASK, 0x04 +.set SD_PULLUP__1__PC, CYREG_PRT3_PC2 +.set SD_PULLUP__1__PORT, 3 +.set SD_PULLUP__1__SHIFT, 2 +.set SD_PULLUP__2__MASK, 0x08 +.set SD_PULLUP__2__PC, CYREG_PRT3_PC3 +.set SD_PULLUP__2__PORT, 3 +.set SD_PULLUP__2__SHIFT, 3 +.set SD_PULLUP__3__MASK, 0x10 +.set SD_PULLUP__3__PC, CYREG_PRT3_PC4 +.set SD_PULLUP__3__PORT, 3 +.set SD_PULLUP__3__SHIFT, 4 +.set SD_PULLUP__4__MASK, 0x20 +.set SD_PULLUP__4__PC, CYREG_PRT3_PC5 +.set SD_PULLUP__4__PORT, 3 +.set SD_PULLUP__4__SHIFT, 5 +.set SD_PULLUP__AG, CYREG_PRT3_AG +.set SD_PULLUP__AMUX, CYREG_PRT3_AMUX +.set SD_PULLUP__BIE, CYREG_PRT3_BIE +.set SD_PULLUP__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_PULLUP__BYP, CYREG_PRT3_BYP +.set SD_PULLUP__CTL, CYREG_PRT3_CTL +.set SD_PULLUP__DM0, CYREG_PRT3_DM0 +.set SD_PULLUP__DM1, CYREG_PRT3_DM1 +.set SD_PULLUP__DM2, CYREG_PRT3_DM2 +.set SD_PULLUP__DR, CYREG_PRT3_DR +.set SD_PULLUP__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_PULLUP__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_PULLUP__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_PULLUP__MASK, 0x3E +.set SD_PULLUP__PORT, 3 +.set SD_PULLUP__PRT, CYREG_PRT3_PRT +.set SD_PULLUP__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_PULLUP__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_PULLUP__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_PULLUP__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_PULLUP__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_PULLUP__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_PULLUP__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_PULLUP__PS, CYREG_PRT3_PS +.set SD_PULLUP__SHIFT, 1 +.set SD_PULLUP__SLW, CYREG_PRT3_SLW + /* USBFS_USB */ .set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG .set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitteriar.inc b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitteriar.inc index d0d0f630..fb84c624 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitteriar.inc +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitteriar.inc @@ -507,6 +507,54 @@ USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +/* SD_PULLUP */ +SD_PULLUP__0__MASK EQU 0x02 +SD_PULLUP__0__PC EQU CYREG_PRT3_PC1 +SD_PULLUP__0__PORT EQU 3 +SD_PULLUP__0__SHIFT EQU 1 +SD_PULLUP__1__MASK EQU 0x04 +SD_PULLUP__1__PC EQU CYREG_PRT3_PC2 +SD_PULLUP__1__PORT EQU 3 +SD_PULLUP__1__SHIFT EQU 2 +SD_PULLUP__2__MASK EQU 0x08 +SD_PULLUP__2__PC EQU CYREG_PRT3_PC3 +SD_PULLUP__2__PORT EQU 3 +SD_PULLUP__2__SHIFT EQU 3 +SD_PULLUP__3__MASK EQU 0x10 +SD_PULLUP__3__PC EQU CYREG_PRT3_PC4 +SD_PULLUP__3__PORT EQU 3 +SD_PULLUP__3__SHIFT EQU 4 +SD_PULLUP__4__MASK EQU 0x20 +SD_PULLUP__4__PC EQU CYREG_PRT3_PC5 +SD_PULLUP__4__PORT EQU 3 +SD_PULLUP__4__SHIFT EQU 5 +SD_PULLUP__AG EQU CYREG_PRT3_AG +SD_PULLUP__AMUX EQU CYREG_PRT3_AMUX +SD_PULLUP__BIE EQU CYREG_PRT3_BIE +SD_PULLUP__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_PULLUP__BYP EQU CYREG_PRT3_BYP +SD_PULLUP__CTL EQU CYREG_PRT3_CTL +SD_PULLUP__DM0 EQU CYREG_PRT3_DM0 +SD_PULLUP__DM1 EQU CYREG_PRT3_DM1 +SD_PULLUP__DM2 EQU CYREG_PRT3_DM2 +SD_PULLUP__DR EQU CYREG_PRT3_DR +SD_PULLUP__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_PULLUP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_PULLUP__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_PULLUP__MASK EQU 0x3E +SD_PULLUP__PORT EQU 3 +SD_PULLUP__PRT EQU CYREG_PRT3_PRT +SD_PULLUP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_PULLUP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_PULLUP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_PULLUP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_PULLUP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_PULLUP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_PULLUP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_PULLUP__PS EQU CYREG_PRT3_PS +SD_PULLUP__SHIFT EQU 1 +SD_PULLUP__SLW EQU CYREG_PRT3_SLW + /* USBFS_USB */ USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitterrv.inc b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitterrv.inc index bc000e20..2f81aaf1 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitterrv.inc +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitterrv.inc @@ -507,6 +507,54 @@ USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +; SD_PULLUP +SD_PULLUP__0__MASK EQU 0x02 +SD_PULLUP__0__PC EQU CYREG_PRT3_PC1 +SD_PULLUP__0__PORT EQU 3 +SD_PULLUP__0__SHIFT EQU 1 +SD_PULLUP__1__MASK EQU 0x04 +SD_PULLUP__1__PC EQU CYREG_PRT3_PC2 +SD_PULLUP__1__PORT EQU 3 +SD_PULLUP__1__SHIFT EQU 2 +SD_PULLUP__2__MASK EQU 0x08 +SD_PULLUP__2__PC EQU CYREG_PRT3_PC3 +SD_PULLUP__2__PORT EQU 3 +SD_PULLUP__2__SHIFT EQU 3 +SD_PULLUP__3__MASK EQU 0x10 +SD_PULLUP__3__PC EQU CYREG_PRT3_PC4 +SD_PULLUP__3__PORT EQU 3 +SD_PULLUP__3__SHIFT EQU 4 +SD_PULLUP__4__MASK EQU 0x20 +SD_PULLUP__4__PC EQU CYREG_PRT3_PC5 +SD_PULLUP__4__PORT EQU 3 +SD_PULLUP__4__SHIFT EQU 5 +SD_PULLUP__AG EQU CYREG_PRT3_AG +SD_PULLUP__AMUX EQU CYREG_PRT3_AMUX +SD_PULLUP__BIE EQU CYREG_PRT3_BIE +SD_PULLUP__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_PULLUP__BYP EQU CYREG_PRT3_BYP +SD_PULLUP__CTL EQU CYREG_PRT3_CTL +SD_PULLUP__DM0 EQU CYREG_PRT3_DM0 +SD_PULLUP__DM1 EQU CYREG_PRT3_DM1 +SD_PULLUP__DM2 EQU CYREG_PRT3_DM2 +SD_PULLUP__DR EQU CYREG_PRT3_DR +SD_PULLUP__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_PULLUP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_PULLUP__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_PULLUP__MASK EQU 0x3E +SD_PULLUP__PORT EQU 3 +SD_PULLUP__PRT EQU CYREG_PRT3_PRT +SD_PULLUP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_PULLUP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_PULLUP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_PULLUP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_PULLUP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_PULLUP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_PULLUP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_PULLUP__PS EQU CYREG_PRT3_PS +SD_PULLUP__SHIFT EQU 1 +SD_PULLUP__SLW EQU CYREG_PRT3_SLW + ; USBFS_USB USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cymetadata.c b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cymetadata.c index 8310348e..00c7240a 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cymetadata.c +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cymetadata.c @@ -1,7 +1,7 @@ /******************************************************************************* * FILENAME: cymetadata.c * -* PSoC Creator 3.0 +* PSoC Creator 3.0 Component Pack 7 * * DESCRIPTION: * This file defines all extra memory spaces that need to be included. @@ -55,7 +55,7 @@ __attribute__ ((__section__(".cycustnvl"), used)) #error "Unsupported toolchain" #endif const uint8 cy_meta_custnvl[] = { - 0x00u, 0x00u, 0x40u, 0x05u + 0x80u, 0x00u, 0x40u, 0x05u }; #if defined(__GNUC__) || defined(__ARMCC_VERSION) diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/elab_dependencies.txt b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/elab_dependencies.txt index 6da3b47b..df6ae4f3 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/elab_dependencies.txt +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/elab_dependencies.txt @@ -1,4 +1,4 @@ -W:\SCSI2SD\USB_Bootloader.cydsn\TopDesign\TopDesign.cysch +W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\TopDesign\TopDesign.cysch C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\USBFS_v2_60.cysym C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\USBFS_v2_60.pdf C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\USBFS_v2_60.cycdx @@ -332,7 +332,45 @@ C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprim C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\PSoC5\API\aliases.h C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\PSoC5\API\pins.c C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\PSoC5\API\pins.h -W:\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cydwr +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\cy_pins_v1_90.cyprimitive +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\cy_pins_v1_90.cysym +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\cy_pins_v1_90.pdf +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\cy_pins_v1_90.cystate +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90 +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\custom.cs +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cygeneralcontrol.cs +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cygeneralcontrol.Designer.cs +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cyinputcontrol.cs +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cyinputcontrol.Designer.cs +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cymappingcontrol.cs +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cymappingcontrol.Designer.cs +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cyoutputcontrol.cs +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cyoutputcontrol.Designer.cs +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cypinaliasdialog.cs +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cypinaliasdialog.Designer.cs +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cypinscontrol.cs +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cypinscontrol.Designer.cs +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cyporcontrol.cs +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cyporcontrol.Designer.cs +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cytypecontrol.cs +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cytypecontrol.Designer.cs +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\Resource1.Designer.cs +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cyclockingcontrol.cs +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cyclockingcontrol.Designer.cs +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cygeneralcontrol.resx +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cyinputcontrol.resx +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cymappingcontrol.resx +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cyoutputcontrol.resx +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cypinaliasdialog.resx +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cypinscontrol.resx +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cyporcontrol.resx +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cytypecontrol.resx +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\Resource1.resx +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cyclockingcontrol.resx +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\PSoC5\API\aliases.h +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\PSoC5\API\pins.c +C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\PSoC5\API\pins.h +W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cydwr C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_0\PSoC5\API\cm3gcc.ld C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_0\PSoC5\API\Cm3RealView.scat C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_0\PSoC5\API\Cm3Start.c diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/generated_files.txt b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/generated_files.txt index 0b918a10..da62bdda 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/generated_files.txt +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/generated_files.txt @@ -1,78 +1,81 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/lcpsoc3/index b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/lcpsoc3/index index ad1d54387b19e244559af2db18871ad9407484f9..e427f5cd846ed2c7ae3e9fe9d5f16a8ed4f200db 100755 GIT binary patch literal 1792 zcmZQzVPQZ3CI*2Y5@0TfY(Pjbm;l8kbvBkWFvNpJ3v}ZdT!3O$Krs;81}NHdU_<$y zA3>!cb_!4~2Z%X*8ffNT&jDBD*CV($UsUMo)qR-hP2JsdpvTh9aKFal{YrM+)K zT#y>a0uKgeAPvHB091bhXjUmuPJ~mFf#;_LgOfePTpu8PO&OvetRAQqM1#x)*?R-z drjhP{R#0fbzzB?gnAb*8ffNT&DD3L1%vG)LRuazeQD^Lui9u6M-t>=Mq7=g5IqMZeZ z3sU1);K9HQq(K-Cfa*^G%_;@TiEu_U@cfiuaI%M(>jR|UCP4Iq)dSUnXpp%edvAc; dG}8Ug3JMJv7=iH*^ZF<~8UiCR1V(uN2LRk|vKasX diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/placer.log b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/placer.log index ee39a729..ebb40486 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/placer.log +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/placer.log @@ -6,7 +6,7 @@ #Build Date: Mar 26 2013 14:54:34 -#File Generated: Oct 26 2013 18:55:19 +#File Generated: Mar 22 2014 22:32:51 #Purpose: @@ -56,7 +56,7 @@ Design Statistics after Packing Device Utilization Summary after Packing Macrocells : 0/192 UDBS : 0/24 - IOs : 20/72 + IOs : 25/72 D2088: Phase 3, elapsed time : 0.0 (sec) @@ -72,5 +72,5 @@ D2088: Phase 8, elapsed time : 0.0 (sec) D2054: Placement of the design completed successfully -I2076: Total run-time: 1.3 sec. +I2076: Total run-time: 1.2 sec. diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/project.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/project.h index c454b9a0..0027c911 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/project.h +++ b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/project.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: project.h - * PSoC Creator 3.0 + * PSoC Creator 3.0 Component Pack 7 * * Description: * This file is automatically generated by PSoC Creator and should not @@ -29,6 +29,8 @@ #include #include #include +#include +#include #include #include #include diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/BL.c b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/BL.c new file mode 100644 index 00000000..3f24c96e --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/BL.c @@ -0,0 +1,1462 @@ +/******************************************************************************* +* File Name: BL.c +* Version 1.20 +* +* Description: +* Provides an API for the Bootloader component. The API includes functions +* for starting boot loading operations, validating the application and +* jumping to the application. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "BL_PVT.h" + +#include "project.h" +#include + + +/******************************************************************************* +* The Checksum and SizeBytes are forcefully set in code. We then post process +* the hex file from the linker and inject their values then. When the hex file +* is loaded onto the device these two variables should have valid values. +* Because the compiler can do optimizations remove the constant +* accesses, these should not be accessed directly. Instead, the variables +* CyBtldr_ChecksumAccess & CyBtldr_SizeBytesAccess should be used to get the +* proper values at runtime. +*******************************************************************************/ +#if defined(__ARMCC_VERSION) || defined (__GNUC__) + __attribute__((section (".bootloader"))) +#elif defined (__ICCARM__) + #pragma location=".bootloader" +#endif /* defined(__ARMCC_VERSION) || defined (__GNUC__) */ + +const uint8 CYCODE BL_Checksum = 0u; +const uint8 CYCODE *BL_ChecksumAccess = (const uint8 CYCODE *)(&BL_Checksum); + +#if defined(__ARMCC_VERSION) || defined (__GNUC__) + __attribute__((section (".bootloader"))) +#elif defined (__ICCARM__) + #pragma location=".bootloader" +#endif /* defined(__ARMCC_VERSION) || defined (__GNUC__) */ + +const uint32 CYCODE BL_SizeBytes = 0xFFFFFFFFu; +const uint32 CYCODE *BL_SizeBytesAccess = (const uint32 CYCODE *)(&BL_SizeBytes); + + +#if(0u != BL_DUAL_APP_BOOTLOADER) + uint8 BL_activeApp = BL_MD_BTLDB_ACTIVE_NONE; +#else + #define BL_activeApp (BL_MD_BTLDB_ACTIVE_0) +#endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ + + +/*************************************** +* Function Prototypes +***************************************/ +static cystatus BL_WritePacket(uint8 status, uint8 buffer[], uint16 size) CYSMALL \ + ; + +static uint16 BL_CalcPacketChecksum(const uint8 buffer[], uint16 size) CYSMALL \ + ; + +static uint8 BL_Calc8BitFlashSum(uint32 start, uint32 size) CYSMALL \ + ; +#if(!CY_PSOC4) +static uint8 BL_Calc8BitEepromSum(uint32 start, uint32 size) CYSMALL \ + ; +#endif /* (!CY_PSOC4) */ + +static void BL_HostLink(uint8 timeOut) \ + ; + +static void BL_LaunchApplication(void) CYSMALL \ + ; + +static cystatus BL_ValidateBootloadable(uint8 appId) CYSMALL \ + ; + +static uint32 BL_GetMetadata(uint8 fieldName, uint8 appId)\ + ; + +#if(!CY_PSOC3) + /* Implementation for the PSoC 3 resides in a BL_psoc3.a51 file. */ + static void BL_LaunchBootloadable(uint32 appAddr); +#endif /* (!CY_PSOC3) */ + + +/******************************************************************************* +* Function Name: BL_CalcPacketChecksum +******************************************************************************** +* +* Summary: +* This computes the 16 bit checksum for the provided number of bytes contained +* in the provided buffer +* +* Parameters: +* buffer: +* The buffer containing the data to compute the checksum for +* size: +* The number of bytes in buffer to compute the checksum for +* +* Returns: +* 16 bit checksum for the provided data +* +*******************************************************************************/ +static uint16 BL_CalcPacketChecksum(const uint8 buffer[], uint16 size) \ + CYSMALL +{ + #if(0u != BL_PACKET_CHECKSUM_CRC) + + uint16 CYDATA crc = BL_CRC_CCITT_INITIAL_VALUE; + uint16 CYDATA tmp; + uint8 CYDATA i; + uint16 CYDATA tmpIndex = size; + + if(0u == size) + { + crc = ~crc; + } + else + { + do + { + tmp = buffer[tmpIndex - size]; + + for (i = 0u; i < 8u; i++) + { + if (0u != ((crc & 0x0001u) ^ (tmp & 0x0001u))) + { + crc = (crc >> 1u) ^ BL_CRC_CCITT_POLYNOMIAL; + } + else + { + crc >>= 1u; + } + + tmp >>= 1u; + } + + size--; + } + while(0u != size); + + crc = ~crc; + tmp = crc; + crc = ( uint16 )(crc << 8u) | (tmp >> 8u); + } + + return(crc); + + #else + + uint16 CYDATA sum = 0u; + + while (size > 0u) + { + sum += buffer[size - 1u]; + size--; + } + + return(( uint16 )1u + ( uint16 )(~sum)); + + #endif /* (0u != BL_PACKET_CHECKSUM_CRC) */ +} + + +/******************************************************************************* +* Function Name: BL_Calc8BitFlashSum +******************************************************************************** +* +* Summary: +* This computes the 8 bit sum for the provided number of bytes contained in +* flash. +* +* Parameters: +* start: +* The starting address to start summing data for +* size: +* The number of bytes to read and compute the sum for +* +* Returns: +* 8 bit sum for the provided data +* +*******************************************************************************/ +static uint8 BL_Calc8BitFlashSum(uint32 start, uint32 size) \ + CYSMALL +{ + uint8 CYDATA sum = 0u; + + while (size > 0u) + { + size--; + sum += BL_GET_CODE_BYTE(start + size); + } + + return(sum); +} + + +#if(!CY_PSOC4) + + /******************************************************************************* + * Function Name: BL_Calc8BitEepromSum + ******************************************************************************** + * + * Summary: + * This computes the 8 bit sum for the provided number of bytes contained in + * EEPROM. + * + * Parameters: + * start: + * The starting address to start summing data for + * size: + * The number of bytes to read and compute the sum for + * + * Returns: + * 8 bit sum for the provided data + * + *******************************************************************************/ + static uint8 BL_Calc8BitEepromSum(uint32 start, uint32 size) \ + CYSMALL + { + uint8 CYDATA sum = 0u; + + while (size > 0u) + { + size--; + sum += BL_GET_EEPROM_BYTE(start + size); + } + + return(sum); + } + +#endif /* (!CY_PSOC4) */ + + +/******************************************************************************* +* Function Name: BL_Start +******************************************************************************** +* Summary: +* This function is called in order executing following algorithm: +* +* - Identify active bootloadable application (applicable only to +* Multi-application bootloader) +* +* - Validate bootloader application (desing-time configurable, Bootloader +* application validation option of the component customizer) +* +* - Validate active bootloadable application +* +* - Run communication subroutine (desing-time configurable, Wait for command +* option of the component customizer) +* +* - Schedule bootloadable and reset device +* +* Parameters: +* None +* +* Return: +* This method will never return. It will either load a new application and +* reset the device or it will jump directly to the existing application. +* +* Side Effects: +* If this method determines that the bootloader appliation itself is corrupt, +* this method will not return, instead it will simply hang the application. +* +*******************************************************************************/ +void BL_Start(void) CYSMALL +{ + #if(0u != BL_BOOTLOADER_APP_VALIDATION) + uint8 CYDATA calcedChecksum; + #endif /* (0u != BL_BOOTLOADER_APP_VALIDATION) */ + + #if(!CY_PSOC4) + uint8 CYXDATA BL_flashBuffer[BL_FROW_SIZE]; + #endif /* (!CY_PSOC4) */ + + cystatus tmpStatus; + + + /* Identify active bootloadable application */ + #if(0u != BL_DUAL_APP_BOOTLOADER) + + if(BL_MD_BTLDB_ACTIVE_VALUE(0u) == BL_MD_BTLDB_IS_ACTIVE) + { + BL_activeApp = BL_MD_BTLDB_ACTIVE_0; + } + else if (BL_MD_BTLDB_ACTIVE_VALUE(1u) == BL_MD_BTLDB_IS_ACTIVE) + { + BL_activeApp = BL_MD_BTLDB_ACTIVE_1; + } + else + { + BL_activeApp = BL_MD_BTLDB_ACTIVE_NONE; + } + + #endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ + + + /* Initialize Flash subsystem for non-PSoC 4 devices */ + #if(!CY_PSOC4) + if (CYRET_SUCCESS != CySetTemp()) + { + CyHalt(0x00u); + } + + if (CYRET_SUCCESS != CySetFlashEEBuffer(BL_flashBuffer)) + { + CyHalt(0x00u); + } + #endif /* (CY_PSOC4) */ + + + /*********************************************************************** + * Bootloader Application Validation + * + * Halt device if: + * - Calculated checksum does not much one stored in metadata section + * - Invalid pointer to the place where bootloader application ends + * - Flash subsystem where not initialized correctly + ***********************************************************************/ + #if(0u != BL_BOOTLOADER_APP_VALIDATION) + + /* Calculate Bootloader application checksum */ + calcedChecksum = BL_Calc8BitFlashSum(BL_MD_BTLDR_ADDR_PTR, + *BL_SizeBytesAccess - BL_MD_BTLDR_ADDR_PTR); + + /* we actually included the checksum, so remove it */ + calcedChecksum -= *BL_ChecksumAccess; + calcedChecksum = ( uint8 )1u + ( uint8 )(~calcedChecksum); + + /* Checksum and pointer to bootloader verification */ + if((calcedChecksum != *BL_ChecksumAccess) || + (0u == *BL_SizeBytesAccess)) + { + CyHalt(0x00u); + } + + #endif /* (0u != BL_BOOTLOADER_APP_VALIDATION) */ + + + /*********************************************************************** + * Active Bootloadable Application Validation + * + * If active bootloadable application is invalid or bootloader + * application is scheduled - do the following: + * - schedule bootloader application to be run after software reset + * - Go to the communication subroutine. Will wait for commands forever + ***********************************************************************/ + tmpStatus = BL_ValidateBootloadable(BL_activeApp); + + if ((BL_GET_RUN_TYPE == BL_START_BTLDR) || + (CYRET_SUCCESS != tmpStatus)) + { + BL_SET_RUN_TYPE(0u); + + BL_HostLink(BL_WAIT_FOR_COMMAND_FOREVER); + } + + + /* Go to the communication subroutine. Will wait for commands specifed time */ + #if(0u != BL_WAIT_FOR_COMMAND) + + /* Timeout is in 100s of miliseconds */ + BL_HostLink(BL_WAIT_FOR_COMMAND_TIME); + + #endif /* (0u != BL_WAIT_FOR_COMMAND) */ + + + /* Schedule bootloadable application and perform software reset */ + BL_LaunchApplication(); +} + + +/******************************************************************************* +* Function Name: BL_LaunchApplication +******************************************************************************** +* +* Summary: +* Jumps the PC to the start address of the user application in flash. +* +* Parameters: +* None +* +* Returns: +* This method will never return if it succesfully goes to the user application. +* +*******************************************************************************/ +static void BL_LaunchApplication(void) CYSMALL +{ + /* Schedule Bootloadable to start after reset */ + BL_SET_RUN_TYPE(BL_START_APP); + + CySoftwareReset(); +} + + +/******************************************************************************* +* Function Name: CyBtldr_CheckLaunch +******************************************************************************** +* +* Summary: +* This routine checks to see if the bootloader or the bootloadable application +* should be run. If the application is to be run, it will start executing. +* If the bootloader is to be run, it will return so the bootloader can +* continue starting up. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void CyBtldr_CheckLaunch(void) CYSMALL +{ + +#if(CY_PSOC4) + + /******************************************************************************* + * Set cyBtldrRunType to zero in case of non-software reset occured. This means + * that bootloader application is scheduled - that is initial clean state. The + * value of cyBtldrRunType is valid only in case of software reset. + *******************************************************************************/ + if (0u == (BL_RES_CAUSE_REG & BL_RES_CAUSE_RESET_SOFT)) + { + cyBtldrRunType = 0u; + } + +#endif /* (CY_PSOC4) */ + + + if (BL_GET_RUN_TYPE == BL_START_APP) + { + BL_SET_RUN_TYPE(0u); + + /******************************************************************************* + * Indicates that we have told ourselves to jump to the application since we have + * already told ourselves to jump, we do not do any expensive verification of the + * application. We just check to make sure that the value at CY_APP_ADDR_ADDRESS + * is something other than 0. + *******************************************************************************/ + if(0u != BL_GetMetadata(BL_GET_METADATA_BTLDB_ADDR, BL_activeApp)) + { + /* Never return from this method */ + BL_LaunchBootloadable(BL_GetMetadata(BL_GET_METADATA_BTLDB_ADDR, + BL_activeApp)); + } + } +} + + +/* Moves the arguement appAddr (RO) into PC, moving execution to the appAddr */ +#if defined (__ARMCC_VERSION) + + __asm static void BL_LaunchBootloadable(uint32 appAddr) + { + BX R0 + ALIGN + } + +#elif defined(__GNUC__) + + __attribute__((noinline)) /* Workaround for GCC toolchain bug with inlining */ + __attribute__((naked)) + static void BL_LaunchBootloadable(uint32 appAddr) + { + __asm volatile(" BX R0\n"); + } + +#elif defined (__ICCARM__) + + static void BL_LaunchBootloadable(uint32 appAddr) + { + __asm volatile(" BX R0\n"); + } + +#endif /* (__ARMCC_VERSION) */ + + +/******************************************************************************* +* Function Name: BL_ValidateBootloadable +******************************************************************************** +* Summary: +* This routine computes the checksum, zero check, 0xFF check of the +* application area to determine whether a valid application is loaded. +* +* Parameters: +* appId: +* The application number to verify +* +* Returns: +* CYRET_SUCCESS - if successful +* CYRET_BAD_DATA - if the bootloadable is corrupt +* +*******************************************************************************/ +static cystatus BL_ValidateBootloadable(uint8 appId) CYSMALL \ + + { + uint32 CYDATA idx; + + uint32 CYDATA end = BL_FIRST_APP_BYTE(appId) + + BL_GetMetadata(BL_GET_METADATA_BTLDB_LENGTH, + appId); + + CYBIT valid = 0u; /* Assume bad flash image */ + uint8 CYDATA calcedChecksum = 0u; + + + #if(0u != BL_DUAL_APP_BOOTLOADER) + + if(appId > 1u) + { + return(CYRET_BAD_DATA); + } + + #endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ + + + #if(0u != BL_FAST_APP_VALIDATION) + + if(BL_MD_BTLDB_VERIFIED_VALUE(appId) == BL_MD_BTLDB_IS_VERIFIED) + { + return(CYRET_SUCCESS); + } + + #endif /* (0u != BL_FAST_APP_VALIDATION) */ + + + /* Calculate checksum of bootloadable image */ + for(idx = BL_FIRST_APP_BYTE(appId); idx < end; ++idx) + { + uint8 CYDATA curByte = BL_GET_CODE_BYTE(idx); + + if((curByte != 0u) && (curByte != 0xFFu)) + { + valid = 1u; + } + + calcedChecksum += curByte; + } + + + /*************************************************************************** + * We do not compute checksum over the meta data section, so no need to + * subtract off App Verified or App Active information here like we do when + * verifying a row. + ***************************************************************************/ + + + #if((!CY_PSOC4) && (CYDEV_ECC_ENABLE == 0u)) + + /* Add ECC data to checksum */ + idx = ((BL_FIRST_APP_BYTE(appId)) >> 3u); + + /* Flash may run into meta data, ECC does not so use full row */ + end = (end == (CY_FLASH_SIZE - BL_MD_SIZEOF)) + ? (CY_FLASH_SIZE >> 3u) + : (end >> 3u); + + for (; idx < end; ++idx) + { + calcedChecksum += CY_GET_XTND_REG8((volatile uint8 *)(CYDEV_ECC_BASE + idx)); + } + + #endif /* ((!CY_PSOC4) && (CYDEV_ECC_ENABLE == 0u)) */ + + + calcedChecksum = ( uint8 )1u + ( uint8 )(~calcedChecksum); + + if((calcedChecksum != BL_MD_BTLDB_CHECKSUM_VALUE(appId)) || + (0u == valid)) + { + return(CYRET_BAD_DATA); + } + + + #if(0u != BL_FAST_APP_VALIDATION) + BL_SetFlashByte((uint32) BL_MD_BTLDB_VERIFIED_OFFSET(appId), + BL_MD_BTLDB_IS_VERIFIED); + #endif /* (0u != BL_FAST_APP_VALIDATION) */ + + + return(CYRET_SUCCESS); +} + + +/******************************************************************************* +* Function Name: BL_HostLink +******************************************************************************** +* +* Summary: +* Causes the bootloader to attempt to read data being transmitted by the +* host application. If data is sent from the host, this establishes the +* communication interface to process all requests. +* +* Parameters: +* timeOut: +* The amount of time to listen for data before giving up. Timeout is +* measured in 10s of ms. Use 0 for infinite wait. +* +* Return: +* None +* +*******************************************************************************/ +static void BL_HostLink(uint8 timeOut) +{ + uint16 CYDATA numberRead; + uint16 CYDATA rspSize; + uint8 CYDATA ackCode; + uint16 CYDATA pktChecksum; + cystatus CYDATA readStat; + uint16 CYDATA pktSize = 0u; + uint16 CYDATA dataOffset = 0u; + uint8 CYDATA timeOutCnt = 10u; + + #if(0u == BL_DUAL_APP_BOOTLOADER) + uint8 CYDATA clearedMetaData = 0u; + #endif /* (0u == BL_DUAL_APP_BOOTLOADER) */ + + CYBIT communicationState = BL_COMMUNICATION_STATE_IDLE; + + uint8 packetBuffer[BL_SIZEOF_COMMAND_BUFFER]; + uint8 dataBuffer [BL_SIZEOF_COMMAND_BUFFER]; + + + /* Initialize communications channel. */ + CyBtldrCommStart(); + + /* Enable global interrupts */ + CyGlobalIntEnable; + + do + { + ackCode = CYRET_SUCCESS; + + do + { + readStat = CyBtldrCommRead(packetBuffer, + BL_SIZEOF_COMMAND_BUFFER, + &numberRead, + (0u == timeOut) ? 0xFFu : timeOut); + if (0u != timeOut) + { + timeOutCnt--; + } + + } while ( (0u != timeOutCnt) && (readStat != CYRET_SUCCESS) ); + + + if( readStat != CYRET_SUCCESS ) + { + continue; + } + + if((numberRead < BL_MIN_PKT_SIZE) || + (packetBuffer[BL_SOP_ADDR] != BL_SOP)) + { + ackCode = BL_ERR_DATA; + } + else + { + pktSize = ((uint16)((uint16)packetBuffer[BL_SIZE_ADDR + 1u] << 8u)) | + packetBuffer[BL_SIZE_ADDR]; + + pktChecksum = ((uint16)((uint16)packetBuffer[BL_CHK_ADDR(pktSize) + 1u] << 8u)) | + packetBuffer[BL_CHK_ADDR(pktSize)]; + + if((pktSize + BL_MIN_PKT_SIZE) > numberRead) + { + ackCode = BL_ERR_LENGTH; + } + else if(packetBuffer[BL_EOP_ADDR(pktSize)] != BL_EOP) + { + ackCode = BL_ERR_DATA; + } + else if(pktChecksum != BL_CalcPacketChecksum(packetBuffer, + pktSize + BL_DATA_ADDR)) + { + ackCode = BL_ERR_CHECKSUM; + } + else + { + /* Empty section */ + } + } + + rspSize = 0u; + if(ackCode == CYRET_SUCCESS) + { + uint8 CYDATA btldrData = packetBuffer[BL_DATA_ADDR]; + + ackCode = BL_ERR_DATA; + switch(packetBuffer[BL_CMD_ADDR]) + { + + + /*************************************************************************** + * Get metadata + ***************************************************************************/ + #if(0u != BL_CMD_GET_METADATA) + + case BL_COMMAND_GET_METADATA: + + if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 1u)) + { + if (btldrData >= BL_MAX_NUM_OF_BTLDB) + { + ackCode = BL_ERR_APP; + } + else if(CYRET_SUCCESS == BL_ValidateBootloadable(btldrData)) + { + #if(CY_PSOC3) + (void) memcpy(&packetBuffer[BL_DATA_ADDR], + ((uint8 CYCODE *) (BL_META_BASE(btldrData))), 56); + #else + (void) memcpy(&packetBuffer[BL_DATA_ADDR], + (uint8 *) BL_META_BASE(btldrData), 56u); + #endif /* (CY_PSOC3) */ + + rspSize = 56u; + ackCode = CYRET_SUCCESS; + } + else + { + ackCode = BL_ERR_APP; + } + } + break; + + #endif /* (0u != BL_CMD_GET_METADATA) */ + + + /*************************************************************************** + * Verify checksum + ***************************************************************************/ + case BL_COMMAND_CHECKSUM: + + if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 0u)) + { + packetBuffer[BL_DATA_ADDR] = + (uint8)(BL_ValidateBootloadable(BL_activeApp) == CYRET_SUCCESS); + + rspSize = 1u; + ackCode = CYRET_SUCCESS; + } + break; + + + /*************************************************************************** + * Get flash size + ***************************************************************************/ + #if(0u != BL_CMD_GET_FLASH_SIZE_AVAIL) + + case BL_COMMAND_REPORT_SIZE: + + if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 1u)) + { + /* btldrData holds flash array ID sent by host */ + if(btldrData < BL_NUM_OF_FLASH_ARRAYS) + { + #if (1u == BL_NUM_OF_FLASH_ARRAYS) + uint16 CYDATA startRow = (uint16)*BL_SizeBytesAccess / CYDEV_FLS_ROW_SIZE; + #else + uint16 CYDATA startRow = 0u; + #endif /* (1u == BL_NUM_OF_FLASH_ARRAYS) */ + + packetBuffer[BL_DATA_ADDR] = LO8(startRow); + packetBuffer[BL_DATA_ADDR + 1u] = HI8(startRow); + packetBuffer[BL_DATA_ADDR + 2u] = LO8(CY_FLASH_NUMBER_ROWS - 1u); + packetBuffer[BL_DATA_ADDR + 3u] = HI8(CY_FLASH_NUMBER_ROWS - 1u); + + rspSize = 4u; + ackCode = CYRET_SUCCESS; + } + + } + break; + + #endif /* (0u != BL_CMD_GET_FLASH_SIZE_AVAIL) */ + + + /*************************************************************************** + * Get application status + ***************************************************************************/ + #if(0u != BL_DUAL_APP_BOOTLOADER) + + #if(0u != BL_CMD_GET_APP_STATUS_AVAIL) + + case BL_COMMAND_APP_STATUS: + + if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 1u)) + { + + packetBuffer[BL_DATA_ADDR] = + (uint8)BL_ValidateBootloadable(btldrData); + + packetBuffer[BL_DATA_ADDR + 1u] = + (uint8)BL_MD_BTLDB_ACTIVE_VALUE(btldrData); + + rspSize = 2u; + ackCode = CYRET_SUCCESS; + } + break; + + #endif /* (0u != BL_CMD_GET_APP_STATUS_AVAIL) */ + + #endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ + + + /*************************************************************************** + * Program / Erase row + ***************************************************************************/ + case BL_COMMAND_PROGRAM: + + /* The btldrData variable holds Flash Array ID */ + + #if (0u != BL_CMD_ERASE_ROW_AVAIL) + + case BL_COMMAND_ERASE: + if (BL_COMMAND_ERASE == packetBuffer[BL_CMD_ADDR]) + { + if ((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 3u)) + { + #if(!CY_PSOC4) + if((btldrData >= BL_FIRST_EE_ARRAYID) && + (btldrData <= BL_LAST_EE_ARRAYID)) + { + /* Size of EEPROM row */ + dataOffset = CY_EEPROM_SIZEOF_ROW; + } + else + { + /* Size of FLASH row (depends on ECC configuration) */ + dataOffset = BL_FROW_SIZE; + } + #else + /* Size of FLASH row (no ECC available) */ + dataOffset = BL_FROW_SIZE; + #endif /* (!CY_PSOC4) */ + + #if(CY_PSOC3) + (void) memset(dataBuffer, (char8) 0, (int16) dataOffset); + #else + (void) memset(dataBuffer, 0, dataOffset); + #endif /* (CY_PSOC3) */ + } + else + { + break; + } + } + + #endif /* (0u != BL_CMD_ERASE_ROW_AVAIL) */ + + + if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize >= 3u)) + { + + /* The command may be sent along with the last block of data, to program the row. */ + #if(CY_PSOC3) + (void) memcpy(&dataBuffer[dataOffset], + &packetBuffer[BL_DATA_ADDR + 3u], + ( int16 )pktSize - 3); + #else + (void) memcpy(&dataBuffer[dataOffset], + &packetBuffer[BL_DATA_ADDR + 3u], + pktSize - 3u); + #endif /* (CY_PSOC3) */ + + dataOffset += (pktSize - 3u); + + #if(!CY_PSOC4) + if((btldrData >= BL_FIRST_EE_ARRAYID) && + (btldrData <= BL_LAST_EE_ARRAYID)) + { + + CyEEPROM_Start(); + + /* Size of EEPROM row */ + pktSize = CY_EEPROM_SIZEOF_ROW; + } + else + { + /* Size of FLASH row (depends on ECC configuration) */ + pktSize = BL_FROW_SIZE; + } + #else + /* Size of FLASH row (no ECC available) */ + pktSize = BL_FROW_SIZE; + #endif /* (!CY_PSOC4) */ + + + /* Check if we have all data to program */ + if(dataOffset == pktSize) + { + /* Get FLASH/EEPROM row number */ + dataOffset = ((uint16)((uint16)packetBuffer[BL_DATA_ADDR + 2u] << 8u)) | + packetBuffer[BL_DATA_ADDR + 1u]; + + #if(!CY_PSOC4) + if(btldrData <= BL_LAST_FLASH_ARRAYID) + { + #endif /* (!CY_PSOC4) */ + + #if(0u == BL_DUAL_APP_BOOTLOADER) + + if(0u == clearedMetaData) + { + /* Metadata section must be filled with zeroes */ + + uint8 erase[BL_FROW_SIZE]; + + #if(CY_PSOC3) + (void) memset(erase, (char8) 0, (int16) BL_FROW_SIZE); + #else + (void) memset(erase, 0, BL_FROW_SIZE); + #endif /* (CY_PSOC3) */ + + #if(CY_PSOC4) + (void) CySysFlashWriteRow(BL_MD_ROW, erase); + #else + (void) CyWriteRowFull((uint8) BL_MD_FLASH_ARRAY_NUM, + (uint16) BL_MD_ROW, + erase, + BL_FROW_SIZE); + #endif /* (CY_PSOC4) */ + + /* Set up flag that metadata was cleared */ + clearedMetaData = 1u; + } + + #else + + if(BL_activeApp < BL_MD_BTLDB_ACTIVE_NONE) + { + /* First active bootloadable application row */ + uint16 firstRow = (uint16) 1u + + (uint16) BL_GetMetadata(BL_GET_METADATA_BTLDR_LAST_ROW, + BL_activeApp); + + #if(CY_PSOC4) + uint16 row = dataOffset; + #else + uint16 row = (uint16)(btldrData * (CYDEV_FLS_SECTOR_SIZE / CYDEV_FLS_ROW_SIZE)) + + dataOffset; + #endif /* (CY_PSOC4) */ + + + /******************************************************************************* + * Last row is equal to the first row plus the number of rows available for each + * app. To compute this, we first subtract the number of appliaction images from + * the total flash rows: (CY_FLASH_NUMBER_ROWS - 2u). + * + * Then subtract off the first row: + * App Rows = (CY_FLASH_NUMBER_ROWS - 2u - firstRow) + * Then divide that number by the number of application that must fit within the + * space, if we are app1 then that number is 2, if app2 then 1. Our divisor is + * then: (2u - BL_activeApp). + * + * Adding this number to firstRow gives the address right beyond our valid range + * so we subtract 1. + *******************************************************************************/ + uint16 lastRow = (firstRow - 1u) + + ((uint16)((CYDEV_FLASH_SIZE / CYDEV_FLS_ROW_SIZE) - 2u - firstRow) / + ((uint16)2u - (uint16)BL_activeApp)); + + + /******************************************************************************* + * Check to see if the row to program is within the range of the active + * application, or if it maches the active application's metadata row. If so, + * refuse to program as it would corrupt the active app. + *******************************************************************************/ + if(((row >= firstRow) && (row <= lastRow)) || + ((btldrData == BL_MD_FLASH_ARRAY_NUM) && + (dataOffset == BL_MD_ROW_NUM(BL_activeApp)))) + { + ackCode = BL_ERR_ACTIVE; + dataOffset = 0u; + break; + } + } + + #endif /* (0u == BL_DUAL_APP_BOOTLOADER) */ + + #if(!CY_PSOC4) + } + #endif /* (!CY_PSOC4) */ + + #if(CY_PSOC4) + + ackCode = (CYRET_SUCCESS != CySysFlashWriteRow((uint32) dataOffset, dataBuffer)) \ + ? BL_ERR_ROW \ + : CYRET_SUCCESS; + + #else + + ackCode = (CYRET_SUCCESS != CyWriteRowFull(btldrData, dataOffset, dataBuffer, pktSize)) \ + ? BL_ERR_ROW \ + : CYRET_SUCCESS; + + #endif /* (CY_PSOC4) */ + + } + else + { + ackCode = BL_ERR_LENGTH; + } + + dataOffset = 0u; + } + break; + + + /*************************************************************************** + * Sync bootloader + ***************************************************************************/ + #if(0u != BL_CMD_SYNC_BOOTLOADER_AVAIL) + + case BL_COMMAND_SYNC: + + if(BL_COMMUNICATION_STATE_ACTIVE == communicationState) + { + /* If something failed the host would send this command to reset the bootloader. */ + dataOffset = 0u; + + /* Don't ack the packet, just get ready to accept the next one */ + continue; + } + break; + + #endif /* (0u != BL_CMD_SYNC_BOOTLOADER_AVAIL) */ + + + /*************************************************************************** + * Set active application + ***************************************************************************/ + #if(0u != BL_DUAL_APP_BOOTLOADER) + + case BL_COMMAND_APP_ACTIVE: + + if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 1u)) + { + if(CYRET_SUCCESS == BL_ValidateBootloadable(btldrData)) + { + uint8 CYDATA idx; + + for(idx = 0u; idx < BL_MAX_NUM_OF_BTLDB; idx++) + { + BL_SetFlashByte((uint32) BL_MD_BTLDB_ACTIVE_OFFSET(idx), + (uint8 )(idx == btldrData)); + } + BL_activeApp = btldrData; + ackCode = CYRET_SUCCESS; + } + else + { + ackCode = BL_ERR_APP; + } + } + break; + + #endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ + + + /*************************************************************************** + * Send data + ***************************************************************************/ + #if (0u != BL_CMD_SEND_DATA_AVAIL) + + case BL_COMMAND_DATA: + + if(BL_COMMUNICATION_STATE_ACTIVE == communicationState) + { + /* Make sure that dataOffset is valid before copying the data */ + if((dataOffset + pktSize) <= BL_SIZEOF_COMMAND_BUFFER) + { + ackCode = CYRET_SUCCESS; + + #if(CY_PSOC3) + (void) memcpy(&dataBuffer[dataOffset], + &packetBuffer[BL_DATA_ADDR], + ( int16 )pktSize); + #else + (void) memcpy(&dataBuffer[dataOffset], + &packetBuffer[BL_DATA_ADDR], + pktSize); + #endif /* (CY_PSOC3) */ + + dataOffset += pktSize; + } + else + { + ackCode = BL_ERR_LENGTH; + } + } + + break; + + #endif /* (0u != BL_CMD_SEND_DATA_AVAIL) */ + + + /*************************************************************************** + * Enter bootloader + ***************************************************************************/ + case BL_COMMAND_ENTER: + + if(pktSize == 0u) + { + #if(CY_PSOC3) + + BL_ENTER CYDATA BtldrVersion = + {CYSWAP_ENDIAN32(CYDEV_CHIP_JTAG_ID), CYDEV_CHIP_REV_EXPECT, BL_VERSION}; + + #else + + BL_ENTER CYDATA BtldrVersion = + {CYDEV_CHIP_JTAG_ID, CYDEV_CHIP_REV_EXPECT, BL_VERSION}; + + #endif /* (CY_PSOC3) */ + + communicationState = BL_COMMUNICATION_STATE_ACTIVE; + + rspSize = sizeof(BL_ENTER); + + #if(CY_PSOC3) + (void) memcpy(&packetBuffer[BL_DATA_ADDR], + &BtldrVersion, + ( int16 )rspSize); + #else + (void) memcpy(&packetBuffer[BL_DATA_ADDR], + &BtldrVersion, + rspSize); + #endif /* (CY_PSOC3) */ + + ackCode = CYRET_SUCCESS; + } + break; + + + /*************************************************************************** + * Verify row + ***************************************************************************/ + case BL_COMMAND_VERIFY: + + if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 3u)) + { + /* Get FLASH/EEPROM row number */ + uint16 CYDATA rowNum = ((uint16)((uint16)packetBuffer[BL_DATA_ADDR + 2u] << 8u)) | + packetBuffer[BL_DATA_ADDR + 1u]; + + #if(!CY_PSOC4) + + uint32 CYDATA rowAddr; + uint8 CYDATA checksum; + + if((btldrData >= BL_FIRST_EE_ARRAYID) && + (btldrData <= BL_LAST_EE_ARRAYID)) + { + /* EEPROM */ + /* Both PSoC 3 and PSoC 5LP architectures have one EEPROM array. */ + rowAddr = (uint32)rowNum * CYDEV_EEPROM_ROW_SIZE; + + checksum = BL_Calc8BitEepromSum(rowAddr, CYDEV_EEPROM_ROW_SIZE); + } + else + { + /* FLASH */ + rowAddr = ((uint32)btldrData * CYDEV_FLS_SECTOR_SIZE) + + ((uint32)rowNum * CYDEV_FLS_ROW_SIZE); + + checksum = BL_Calc8BitFlashSum(rowAddr, CYDEV_FLS_ROW_SIZE); + } + + #else + + uint32 CYDATA rowAddr = ((uint32)btldrData * CYDEV_FLS_SECTOR_SIZE) + + ((uint32)rowNum * CYDEV_FLS_ROW_SIZE); + + uint8 CYDATA checksum = BL_Calc8BitFlashSum(rowAddr, CYDEV_FLS_ROW_SIZE); + + #endif /* (!CY_PSOC4) */ + + + /* Calculate checksum on data from ECC */ + #if(!CY_PSOC4) && (CYDEV_ECC_ENABLE == 0u) + + if(btldrData <= BL_LAST_FLASH_ARRAYID) + { + uint16 CYDATA tmpIndex; + + rowAddr = CYDEV_ECC_BASE + ((uint32)btldrData * (CYDEV_FLS_SECTOR_SIZE / 8u)) + + ((uint32)rowNum * CYDEV_ECC_ROW_SIZE); + + for(tmpIndex = 0u; tmpIndex < CYDEV_ECC_ROW_SIZE; tmpIndex++) + { + checksum += CY_GET_XTND_REG8((uint8 CYFAR *)(rowAddr + tmpIndex)); + } + } + + #endif /* (!CY_PSOC4) && (CYDEV_ECC_ENABLE == 0u) */ + + + /******************************************************************************* + * App Verified & App Active are information that is updated in flash at runtime + * remove these items from the checksum to allow the host to verify everything is + * correct. + ******************************************************************************/ + if((BL_MD_FLASH_ARRAY_NUM == btldrData) && + (BL_CONTAIN_METADATA(rowNum))) + { + checksum -= BL_MD_BTLDB_ACTIVE_VALUE (BL_GET_APP_ID(rowNum)); + checksum -= BL_MD_BTLDB_VERIFIED_VALUE(BL_GET_APP_ID(rowNum)); + } + + packetBuffer[BL_DATA_ADDR] = (uint8)1u + (uint8)(~checksum); + ackCode = CYRET_SUCCESS; + rspSize = 1u; + } + break; + + + /*************************************************************************** + * Exit bootloader + ***************************************************************************/ + case BL_COMMAND_EXIT: + + if(CYRET_SUCCESS == BL_ValidateBootloadable(BL_activeApp)) + { + BL_SET_RUN_TYPE(BL_START_APP); + } + + CySoftwareReset(); + + /* Will never get here */ + break; + + + /*************************************************************************** + * Unsupported command + ***************************************************************************/ + default: + ackCode = BL_ERR_CMD; + break; + } + } + + /* ?CK the packet and function. */ + (void) BL_WritePacket(ackCode, packetBuffer, rspSize); + + } while ((0u == timeOut) || (BL_COMMUNICATION_STATE_ACTIVE == communicationState)); +} + + +/******************************************************************************* +* Function Name: BL_WritePacket +******************************************************************************** +* +* Summary: +* Creates a bootloader responce packet and transmits it back to the bootloader +* host application over the already established communications protocol. +* +* Parameters: +* status: +* The status code to pass back as the second byte of the packet +* buffer: +* The buffer containing the data portion of the packet +* size: +* The number of bytes contained within the buffer to pass back +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_UNKNOWN if there was an error tranmitting the packet. +* +*******************************************************************************/ +static cystatus BL_WritePacket(uint8 status, uint8 buffer[], uint16 size) CYSMALL \ + +{ + uint16 CYDATA checksum; + + /* Start of the packet. */ + buffer[BL_SOP_ADDR] = BL_SOP; + buffer[BL_CMD_ADDR] = status; + buffer[BL_SIZE_ADDR] = LO8(size); + buffer[BL_SIZE_ADDR + 1u] = HI8(size); + + /* Compute the checksum. */ + checksum = BL_CalcPacketChecksum(buffer, size + BL_DATA_ADDR); + + buffer[BL_CHK_ADDR(size)] = LO8(checksum); + buffer[BL_CHK_ADDR(1u + size)] = HI8(checksum); + buffer[BL_EOP_ADDR(size)] = BL_EOP; + + /* Start the packet transmit. */ + return(CyBtldrCommWrite(buffer, size + BL_MIN_PKT_SIZE, &size, 150u)); +} + + +/******************************************************************************* +* Function Name: BL_SetFlashByte +******************************************************************************** +* +* Summary: +* Writes byte a flash memory location +* +* Parameters: +* address: +* Address in Flash memory where data will be written +* +* runType: +* Byte to be written +* +* Return: +* None +* +*******************************************************************************/ +void BL_SetFlashByte(uint32 address, uint8 runType) +{ + uint32 flsAddr = address - CYDEV_FLASH_BASE; + uint8 rowData[CYDEV_FLS_ROW_SIZE]; + + #if !(CY_PSOC4) + uint8 arrayId = ( uint8 )(flsAddr / CYDEV_FLS_SECTOR_SIZE); + #endif /* !(CY_PSOC4) */ + + uint16 rowNum = ( uint16 )((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE); + uint32 baseAddr = address - (address % CYDEV_FLS_ROW_SIZE); + uint16 idx; + + for(idx = 0u; idx < CYDEV_FLS_ROW_SIZE; idx++) + { + rowData[idx] = BL_GET_CODE_BYTE(baseAddr + idx); + } + + rowData[address % CYDEV_FLS_ROW_SIZE] = runType; + + #if(CY_PSOC4) + (void) CySysFlashWriteRow((uint32) rowNum, rowData); + #else + (void) CyWriteRowData(arrayId, rowNum, rowData); + #endif /* (CY_PSOC4) */ +} + + +/******************************************************************************* +* Function Name: BL_GetMetadata +******************************************************************************** +* +* Summary: +* Returns value of the multi-byte field. +* +* Parameters: +* fieldName: +* The field to get data from: +* BL_GET_METADATA_BTLDB_ADDR +* BL_GET_METADATA_BTLDR_LAST_ROW +* BL_GET_METADATA_BTLDB_LENGTH +* BL_GET_METADATA_BTLDR_APP_VERSION +* BL_GET_METADATA_BTLDB_APP_VERSION +* BL_GET_METADATA_BTLDB_APP_ID +* BL_GET_METADATA_BTLDB_APP_CUST_ID +* +* appId: +* Number of the bootlodable application. +* +* Return: +* None +* +*******************************************************************************/ +static uint32 BL_GetMetadata(uint8 fieldName, uint8 appId) +{ + uint32 fieldPtr; + uint8 fieldSize = 2u; + uint32 result; + + switch (fieldName) + { + case BL_GET_METADATA_BTLDB_APP_CUST_ID: + fieldPtr = BL_MD_BTLDB_APP_CUST_ID_OFFSET(appId); + fieldSize = 4u; + break; + + case BL_GET_METADATA_BTLDR_APP_VERSION: + fieldPtr = BL_MD_BTLDR_APP_VERSION_OFFSET(appId); + break; + + case BL_GET_METADATA_BTLDB_ADDR: + fieldPtr = BL_MD_BTLDB_ADDR_OFFSET(appId); + #if(!CY_PSOC3) + fieldSize = 4u; + #endif /* (!CY_PSOC3) */ + break; + + case BL_GET_METADATA_BTLDR_LAST_ROW: + fieldPtr = BL_MD_BTLDR_LAST_ROW_OFFSET(appId); + break; + + case BL_GET_METADATA_BTLDB_LENGTH: + fieldPtr = BL_MD_BTLDB_LENGTH_OFFSET(appId); + #if(!CY_PSOC3) + fieldSize = 4u; + #endif /* (!CY_PSOC3) */ + break; + + case BL_GET_METADATA_BTLDB_APP_VERSION: + fieldPtr = BL_MD_BTLDB_APP_VERSION_OFFSET(appId); + break; + + case BL_GET_METADATA_BTLDB_APP_ID: + fieldPtr = BL_MD_BTLDB_APP_ID_OFFSET(appId); + break; + + default: + /* Should never be here */ + CYASSERT(0u != 0u); + fieldPtr = 0u; + break; + } + + + /* Read all fields as big-endian */ + if (2u == fieldSize) + { + result = (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 1u)); + result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *) fieldPtr ) << 8u; + } + else + { + result = (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 3u)); + result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 2u)) << 8u; + result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 1u)) << 16u; + result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr )) << 24u; + } + + /* Following fields should be little-endian */ +#if(!CY_PSOC3) + switch (fieldName) + { + case BL_GET_METADATA_BTLDR_LAST_ROW: + result = CYSWAP_ENDIAN16(result); + break; + + case BL_GET_METADATA_BTLDB_ADDR: + case BL_GET_METADATA_BTLDB_LENGTH: + result = CYSWAP_ENDIAN32(result); + break; + + default: + break; + } + +#endif /* (!CY_PSOC3) */ + + return (result); +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/BL.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/BL.h new file mode 100755 index 00000000..edb0301b --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/BL.h @@ -0,0 +1,318 @@ +/******************************************************************************* +* File Name: BL.h +* Version 1.20 +* +* Description: +* Provides an API for the Bootloader. The API includes functions for starting +* boot loading operations, validating the application and jumping to the +* application. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOTLOADER_BL_H) +#define CY_BOOTLOADER_BL_H + +#include "cytypes.h" + + +/* Check to see if required defines such as CY_PSOC5LP are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5LP) + #error Component Bootloader_v1_20 requires cy_boot v3.0 or later +#endif /* (CY_ PSOC5X) */ + + +#define BL_DUAL_APP_BOOTLOADER (0u) +#define BL_BOOTLOADER_APP_VERSION (0u) +#define BL_FAST_APP_VALIDATION (0u) +#define BL_PACKET_CHECKSUM_CRC (0u) +#define BL_WAIT_FOR_COMMAND (1u) +#define BL_WAIT_FOR_COMMAND_TIME (20u) +#define BL_BOOTLOADER_APP_VALIDATION (1u) + +#define BL_CMD_GET_FLASH_SIZE_AVAIL (1u) +#define BL_CMD_ERASE_ROW_AVAIL (1u) +#define BL_CMD_VERIFY_ROW_AVAIL (1u) +#define BL_CMD_SYNC_BOOTLOADER_AVAIL (1u) +#define BL_CMD_SEND_DATA_AVAIL (1u) +#define BL_CMD_GET_METADATA (0u) + +#if(0u != BL_DUAL_APP_BOOTLOADER) + #define BL_CMD_GET_APP_STATUS_AVAIL (1u) +#endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ + + +/******************************************************************************* +* Bootloadable applications identification +*******************************************************************************/ +#define BL_MD_BTLDB_ACTIVE_0 (0x00u) +#if(0u != BL_DUAL_APP_BOOTLOADER) + #define BL_MD_BTLDB_ACTIVE_1 (0x01u) + #define BL_MD_BTLDB_ACTIVE_NONE (0x02u) +#endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ + + +/* Mask used to indicate starting application */ +#define BL_SCHEDULE_BTLDB (0x80u) +#define BL_SCHEDULE_BTLDR (0x40u) +#define BL_SCHEDULE_MASK (0xC0u) + + +#if defined(__ARMCC_VERSION) || defined (__GNUC__) + __attribute__((section (".bootloader"))) +#elif defined (__ICCARM__) + #pragma location=".bootloader" +#endif /* defined(__ARMCC_VERSION) || defined (__GNUC__) */ +extern const uint8 CYCODE BL_Checksum; +extern const uint8 CYCODE *BL_ChecksumAccess; + + +#if defined(__ARMCC_VERSION) || defined (__GNUC__) + __attribute__((section (".bootloader"))) +#elif defined (__ICCARM__) + #pragma location=".bootloader" +#endif /* defined(__ARMCC_VERSION) || defined (__GNUC__) */ +extern const uint32 CYCODE BL_SizeBytes; +extern const uint32 CYCODE *BL_SizeBytesAccess; + + +/******************************************************************************* +* This variable is used by Bootloader/Bootloadable components to schedule what +* application will be started after software reset. +*******************************************************************************/ +#if (CY_PSOC4) + #if defined(__ARMCC_VERSION) + __attribute__ ((section(".bootloaderruntype"), zero_init)) + #elif defined (__GNUC__) + __attribute__ ((section(".bootloaderruntype"))) + #elif defined (__ICCARM__) + #pragma location=".bootloaderruntype" + #endif /* defined(__ARMCC_VERSION) */ + extern volatile uint32 cyBtldrRunType; +#endif /* (CY_PSOC4) */ + + +#if(0u != BL_DUAL_APP_BOOTLOADER) + extern uint8 BL_activeApp; +#endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ + + +#if(CY_PSOC4) + /* Reset Cause Observation Register */ + #define BL_RES_CAUSE_REG (* (reg32 *) CYREG_RES_CAUSE) + #define BL_RES_CAUSE_PTR ( (reg32 *) CYREG_RES_CAUSE) +#else + #define BL_RESET_SR0_REG (* (reg8 *) CYREG_RESET_SR0) + #define BL_RESET_SR0_PTR ( (reg8 *) CYREG_RESET_SR0) +#endif /* (CY_PSOC4) */ + + +/******************************************************************************* +* Get the reason of the device reset +* Return cyBtldrRunType in case if software reset was reset reason and +* set cyBtldrRunType to zero (bootloader application is scheduled - that is +* initial clean state) and return zero. +*******************************************************************************/ +#if(CY_PSOC4) + #define BL_GET_RUN_TYPE (cyBtldrRunType) +#else + #define BL_GET_RUN_TYPE (BL_RESET_SR0_REG & BL_SCHEDULE_MASK) +#endif /* (CY_PSOC4) */ + + +/******************************************************************************* +* Schedule Bootloader/Bootloadable to be run after software reset +*******************************************************************************/ +#if(CY_PSOC4) + #define BL_SET_RUN_TYPE(x) (cyBtldrRunType = (x)) +#else + #define BL_SET_RUN_TYPE(x) (BL_RESET_SR0_REG = (x)) +#endif /* (CY_PSOC4) */ + + +/* Returns the number of Flash arrays availalbe in the device */ +#define BL_NUM_OF_FLASH_ARRAYS (CYDEV_FLASH_SIZE / CYDEV_FLS_SECTOR_SIZE) + + +/******************************************************************************* +* External References +*******************************************************************************/ +void BL_SetFlashByte(uint32 address, uint8 runType); +void CyBtldr_CheckLaunch(void) CYSMALL ; +void BL_Start(void) CYSMALL ; + +#if(CY_PSOC3) + /* Implementation for the PSoC 3 resides in a BL_psoc3.a51 file. */ + extern void BL_LaunchBootloadable(uint32 appAddr); +#endif /* (CY_PSOC3) */ + +/* If using custom interface as the IO Component, user must provide these functions */ +#if defined(CYDEV_BOOTLOADER_IO_COMP) && (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface) + + extern void CyBtldrCommStart(void); + extern void CyBtldrCommStop (void); + extern void CyBtldrCommReset(void); + extern cystatus CyBtldrCommWrite(uint8* buffer, uint16 size, uint16* count, uint8 timeOut); + extern cystatus CyBtldrCommRead (uint8* buffer, uint16 size, uint16* count, uint8 timeOut); + +#endif /* defined(CYDEV_BOOTLOADER_IO_COMP) && (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface) */ + + +/******************************************************************************* +* Kept for backward compatibility. +*******************************************************************************/ +#if(0u != BL_DUAL_APP_BOOTLOADER) + #define BL_ValidateApp(x) BL_ValidateBootloadable((x)) + #define BL_ValidateApplication \ + BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_0) +#else + #define BL_ValidateApplication \ + BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_0) + #define BL_ValidateApp(x) BL_ValidateBootloadable((x)) +#endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from version 1.10 +*******************************************************************************/ +#define BL_BOOTLOADABLE_APP_VALID (BL_BOOTLOADER_APP_VALIDATION) +#define CyBtldr_Start BL_Start + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from version 1.20 +*******************************************************************************/ +#define BL_META_BASE(x) (CYDEV_FLASH_BASE + \ + (CYDEV_FLASH_SIZE - (( uint32 )(x) * CYDEV_FLS_ROW_SIZE) - \ + BL_META_DATA_SIZE)) +#define BL_META_ARRAY (BL_NUM_OF_FLASH_ARRAYS - 1u) +#define BL_META_APP_ENTRY_POINT_ADDR(x) (BL_META_BASE(x) + \ + BL_META_APP_ADDR_OFFSET) +#define BL_META_APP_BYTE_LEN(x) (BL_META_BASE(x) + \ + BL_META_APP_BYTE_LEN_OFFSET) +#define BL_META_APP_RUN_ADDR(x) (BL_META_BASE(x) + \ + BL_META_APP_RUN_TYPE_OFFSET) +#define BL_META_APP_ACTIVE_ADDR(x) (BL_META_BASE(x) + \ + BL_META_APP_ACTIVE_OFFSET) +#define BL_META_APP_VERIFIED_ADDR(x) (BL_META_BASE(x) + \ + BL_META_APP_VERIFIED_OFFSET) +#define BL_META_APP_BLDBL_VER_ADDR(x) (BL_META_BASE(x) + \ + BL_META_APP_BL_BUILD_VER_OFFSET) +#define BL_META_APP_VER_ADDR(x) (BL_META_BASE(x) + \ + BL_META_APP_VER_OFFSET) +#define BL_META_APP_ID_ADDR(x) (BL_META_BASE(x) + \ + BL_META_APP_ID_OFFSET) +#define BL_META_APP_CUST_ID_ADDR(x) (BL_META_BASE(x) + \ + BL_META_APP_CUST_ID_OFFSET) +#define BL_META_LAST_BLDR_ROW_ADDR(x) (BL_META_BASE(x) + \ + BL_META_APP_BL_LAST_ROW_OFFSET) +#define BL_META_CHECKSUM_ADDR(x) (BL_META_BASE(x) + \ + BL_META_APP_CHECKSUM_OFFSET) +#if(0u == BL_DUAL_APP_BOOTLOADER) + #define BL_MD_BASE BL_META_BASE(0u) + #define BL_MD_ROW ((CY_FLASH_NUMBER_ROWS / BL_NUM_OF_FLASH_ARRAYS) \ + - 1u) + #define BL_MD_CHECKSUM_ADDR BL_META_CHECKSUM_ADDR(0u) + #define BL_MD_LAST_BLDR_ROW_ADDR BL_META_LAST_BLDR_ROW_ADDR(0u) + #define BL_MD_APP_BYTE_LEN BL_META_APP_BYTE_LEN(0u) + #define BL_MD_APP_VERIFIED_ADDR BL_META_APP_VERIFIED_ADDR(0u) + #define BL_MD_APP_ENTRY_POINT_ADDR BL_META_APP_ENTRY_POINT_ADDR(0u) + #define BL_MD_APP_RUN_ADDR BL_META_APP_RUN_ADDR(0u) +#else + #define BL_MD_ROW(x) ((CY_FLASH_NUMBER_ROWS / BL_NUM_OF_FLASH_ARRAYS) \ + - 1u - ( uint32 )(x)) + #define BL_MD_CHECKSUM_ADDR BL_META_CHECKSUM_ADDR(appId) + #define BL_MD_LAST_BLDR_ROW_ADDR BL_META_LAST_BLDR_ROW_ADDR(appId) + #define BL_MD_APP_BYTE_LEN BL_META_APP_BYTE_LEN(appId) + #define BL_MD_APP_VERIFIED_ADDR BL_META_APP_VERIFIED_ADDR(appId) + #define BL_MD_APP_ENTRY_POINT_ADDR \ + BL_META_APP_ENTRY_POINT_ADDR(BL_activeApp) + #define BL_MD_APP_RUN_ADDR BL_META_APP_RUN_ADDR(BL_activeApp) +#endif /* (0u == BL_DUAL_APP_BOOTLOADER) */ + +#define BL_P_APP_ACTIVE(x) ((uint8 CYCODE *) BL_META_APP_ACTIVE_ADDR(x)) +#define BL_MD_PTR_CHECKSUM ((uint8 CYCODE *) BL_MD_CHECKSUM_ADDR) +#define BL_MD_PTR_APP_ENTRY_POINT ((BL_APP_ADDRESS CYCODE *) \ + BL_MD_APP_ENTRY_POINT_ADDR) +#define BL_MD_PTR_LAST_BLDR_ROW ((uint16 CYCODE *) BL_MD_LAST_BLDR_ROW_ADDR) +#define BL_MD_PTR_APP_BYTE_LEN ((BL_APP_ADDRESS CYCODE *) \ + BL_MD_APP_BYTE_LEN) +#define BL_MD_PTR_APP_RUN_ADDR ((uint8 CYCODE *) BL_MD_APP_RUN_ADDR) +#define BL_MD_PTR_APP_VERIFIED ((uint8 CYCODE *) BL_MD_APP_VERIFIED_ADDR) +#define BL_MD_PTR_APP_BLD_BL_VER ((uint16 CYCODE *) BL_MD_APP_BLDBL_VER_ADDR) +#define BL_MD_PTR_APP_VER ((uint16 CYCODE *) BL_MD_APP_VER_ADDR) +#define BL_MD_PTR_APP_ID ((uint16 CYCODE *) BL_MD_APP_ID_ADDR) +#define BL_MD_PTR_APP_CUST_ID ((uint32 CYCODE *) BL_MD_APP_CUST_ID_ADDR) +#if(CY_PSOC3) + #define BL_APP_ADDRESS uint16 + #define BL_GET_CODE_DATA(idx) (*((uint8 CYCODE *) (idx))) + #define BL_GET_CODE_WORD(idx) (*((uint32 CYCODE *) (idx))) + #define BL_META_APP_ADDR_OFFSET (3u) + #define BL_META_APP_BL_LAST_ROW_OFFSET (7u) + #define BL_META_APP_BYTE_LEN_OFFSET (11u) + #define BL_META_APP_RUN_TYPE_OFFSET (15u) +#else + #define BL_APP_ADDRESS uint32 + #define BL_GET_CODE_DATA(idx) (*((uint8 *)(CYDEV_FLASH_BASE + (idx)))) + #define BL_GET_CODE_WORD(idx) (*((uint32 *)(CYDEV_FLASH_BASE + (idx)))) + #define BL_META_APP_ADDR_OFFSET (1u) + #define BL_META_APP_BL_LAST_ROW_OFFSET (5u) + #define BL_META_APP_BYTE_LEN_OFFSET (9u) + #define BL_META_APP_RUN_TYPE_OFFSET (13u) +#endif /* (CY_PSOC3) */ +#define BL_META_APP_ACTIVE_OFFSET (16u) +#define BL_META_APP_VERIFIED_OFFSET (17u) +#define BL_META_APP_BL_BUILD_VER_OFFSET (18u) +#define BL_META_APP_ID_OFFSET (20u) +#define BL_META_APP_VER_OFFSET (22u) +#define BL_META_APP_CUST_ID_OFFSET (24u) +#if (CY_PSOC4) + #define BL_GET_REG16(x) ((uint16)( \ + (( uint16 )(( uint16 )CY_GET_XTND_REG8((x) ) )) | \ + (( uint16 )(( uint16 )CY_GET_XTND_REG8((x) + 1u) << 8u)) \ + )) + + #define BL_GET_REG32(x) ( \ + (( uint32 )(( uint32 ) CY_GET_XTND_REG8((x) ) )) | \ + (( uint32 )(( uint32 ) CY_GET_XTND_REG8((x) + 1u) << 8u)) | \ + (( uint32 )(( uint32 ) CY_GET_XTND_REG8((x) + 2u) << 16u)) | \ + (( uint32 )(( uint32 ) CY_GET_XTND_REG8((x) + 3u) << 24u)) \ + ) +#endif /* (CY_PSOC4) */ +#define BL_META_APP_CHECKSUM_OFFSET (0u) +#define BL_META_DATA_SIZE (64u) +#if(CY_PSOC4) + extern uint8 appRunType; +#endif /* (CY_PSOC4) */ + +#if(CY_PSOC4) + #define BL_SOFTWARE_RESET CY_SET_REG32(CYREG_CM0_AIRCR, 0x05FA0004u) +#else + #define BL_SOFTWARE_RESET CY_SET_REG8(CYREG_RESET_CR2, 0x01u) +#endif /* (CY_PSOC4) */ + +#define BL_SetFlashRunType(runType) BL_SetFlashByte( \ + BL_MD_APP_RUN_ADDR(0), (runType)) + +#define BL_START_APP (BL_SCHEDULE_BTLDB) +#define BL_START_BTLDR (BL_SCHEDULE_BTLDR) + +/* Some PSoC Creator versions used to generate only one name types */ +#if !defined (CYDEV_FLASH_BASE) + #define CYDEV_FLASH_BASE (CYDEV_FLS_BASE) +#endif /* !defined (CYDEV_FLASH_BASE) */ + +#if !defined (CYDEV_FLASH_SIZE) + #define CYDEV_FLASH_SIZE (CYDEV_FLS_SIZE) +#endif /* CYDEV_FLASH_SIZE */ + + +#endif /* CY_BOOTLOADER_BL_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/BL_PVT.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/BL_PVT.h new file mode 100644 index 00000000..400edde5 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/BL_PVT.h @@ -0,0 +1,315 @@ +/******************************************************************************* +* File Name: BL_PVT.h +* Version 1.20 +* +* Description: +* Provides an API for the Bootloader. +* +******************************************************************************** +* Copyright 2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOTLOADER_BL_PVT_H) +#define CY_BOOTLOADER_BL_PVT_H + +#include "BL.h" + + +typedef struct +{ + uint32 SiliconId; + uint8 Revision; + uint8 BootLoaderVersion[3u]; + +} BL_ENTER; + + +#define BL_VERSION {\ + (uint8)20, \ + (uint8)1, \ + (uint8)0x01u \ + } + +/* Packet framing constants. */ +#define BL_SOP (0x01u) /* Start of Packet */ +#define BL_EOP (0x17u) /* End of Packet */ + + +/* Bootloader command responces */ +#define BL_ERR_KEY (0x01u) /* The provided key does not match the expected value */ +#define BL_ERR_VERIFY (0x02u) /* The verification of flash failed */ +#define BL_ERR_LENGTH (0x03u) /* The amount of data available is outside the expected range */ +#define BL_ERR_DATA (0x04u) /* The data is not of the proper form */ +#define BL_ERR_CMD (0x05u) /* The command is not recognized */ +#define BL_ERR_DEVICE (0x06u) /* The expected device does not match the detected device */ +#define BL_ERR_VERSION (0x07u) /* The bootloader version detected is not supported */ +#define BL_ERR_CHECKSUM (0x08u) /* The checksum does not match the expected value */ +#define BL_ERR_ARRAY (0x09u) /* The flash array is not valid */ +#define BL_ERR_ROW (0x0Au) /* The flash row is not valid */ +#define BL_ERR_PROTECT (0x0Bu) /* The flash row is protected and can not be programmed */ +#define BL_ERR_APP (0x0Cu) /* The application is not valid and cannot be set as active */ +#define BL_ERR_ACTIVE (0x0Du) /* The application is currently marked as active */ +#define BL_ERR_UNK (0x0Fu) /* An unknown error occurred */ + + +/* Bootloader command definitions. */ +#define BL_COMMAND_CHECKSUM (0x31u) /* Verify the checksum for the bootloadable project */ +#define BL_COMMAND_REPORT_SIZE (0x32u) /* Report the programmable portions of flash */ +#define BL_COMMAND_APP_STATUS (0x33u) /* Gets status info about the provided app status */ +#define BL_COMMAND_ERASE (0x34u) /* Erase the specified flash row */ +#define BL_COMMAND_SYNC (0x35u) /* Sync the bootloader and host application */ +#define BL_COMMAND_APP_ACTIVE (0x36u) /* Sets the active application */ +#define BL_COMMAND_DATA (0x37u) /* Queue up a block of data for programming */ +#define BL_COMMAND_ENTER (0x38u) /* Enter the bootloader */ +#define BL_COMMAND_PROGRAM (0x39u) /* Program the specified row */ +#define BL_COMMAND_VERIFY (0x3Au) /* Compute flash row checksum for verification */ +#define BL_COMMAND_EXIT (0x3Bu) /* Exits the bootloader & resets the chip */ +#define BL_COMMAND_GET_METADATA (0x3Cu) /* Reports the metadata for a selected application */ + + +/******************************************************************************* +* Bootloader packet byte addresses: +* [1-byte] [1-byte ] [2-byte] [n-byte] [ 2-byte ] [1-byte] +* [ SOP ] [Command] [ Size ] [ Data ] [Checksum] [ EOP ] +*******************************************************************************/ +#define BL_SOP_ADDR (0x00u) /* Start of packet offset from beginning */ +#define BL_CMD_ADDR (0x01u) /* Command offset from beginning */ +#define BL_SIZE_ADDR (0x02u) /* Packet size offset from beginning */ +#define BL_DATA_ADDR (0x04u) /* Packet data offset from beginning */ +#define BL_CHK_ADDR(x) (0x04u + (x)) /* Packet checksum offset from end */ +#define BL_EOP_ADDR(x) (0x06u + (x)) /* End of packet offset from end */ +#define BL_MIN_PKT_SIZE (7u) /* The minimum number of bytes in a packet */ + + +/******************************************************************************* +BL_ValidateBootloadable() +*******************************************************************************/ +#define BL_FIRST_APP_BYTE(appId) ((uint32)CYDEV_FLS_ROW_SIZE * \ + ((uint32) BL_GetMetadata(BL_GET_METADATA_BTLDR_LAST_ROW, appId) + \ + (uint32) 1u)) + +#define BL_MD_BTLDB_IS_VERIFIED (0x01u) + + +/******************************************************************************* +* BL_Start() +*******************************************************************************/ +#define BL_MD_BTLDB_IS_ACTIVE (0x01u) +#define BL_WAIT_FOR_COMMAND_FOREVER (0x00u) + + + /* Maximum number of bytes accepted in a packet plus some */ +#define BL_SIZEOF_COMMAND_BUFFER (300u) + + +/******************************************************************************* +* BL_HostLink() +*******************************************************************************/ +#define BL_COMMUNICATION_STATE_IDLE (0u) +#define BL_COMMUNICATION_STATE_ACTIVE (1u) + +#if(!CY_PSOC4) + + /******************************************************************************* + * The Array ID indicates the unique ID of the SONOS array being accessed: + * - 0x00-0x3E : Flash Arrays + * - 0x3F : Selects all Flash arrays simultaneously + * - 0x40-0x7F : Embedded EEPROM Arrays + *******************************************************************************/ + #define BL_FIRST_FLASH_ARRAYID (0x00u) + #define BL_LAST_FLASH_ARRAYID (0x3Fu) + #define BL_FIRST_EE_ARRAYID (0x40u) + #define BL_LAST_EE_ARRAYID (0x7Fu) + +#endif /* (!CY_PSOC4) */ + + +/******************************************************************************* +* BL_CalcPacketChecksum() +*******************************************************************************/ +#if(0u != BL_PACKET_CHECKSUM_CRC) + #define BL_CRC_CCITT_POLYNOMIAL (0x8408u) /* x^16 + x^12 + x^5 + 1 */ + #define BL_CRC_CCITT_INITIAL_VALUE (0xffffu) +#endif /* (0u != BL_PACKET_CHECKSUM_CRC) */ + + +/******************************************************************************* +* BL_GetMetadata() +*******************************************************************************/ +#define BL_GET_METADATA_BTLDB_ADDR (1u) +#define BL_GET_METADATA_BTLDR_LAST_ROW (2u) +#define BL_GET_METADATA_BTLDB_LENGTH (3u) +#define BL_GET_METADATA_BTLDR_APP_VERSION (4u) +#define BL_GET_METADATA_BTLDB_APP_VERSION (5u) +#define BL_GET_METADATA_BTLDB_APP_ID (6u) +#define BL_GET_METADATA_BTLDB_APP_CUST_ID (7u) + + +/******************************************************************************* +* CyBtldr_CheckLaunch() +*******************************************************************************/ +#define BL_RES_CAUSE_RESET_SOFT (0x10u) + + +/******************************************************************************* +* Metadata addresses and pointer defines +*******************************************************************************/ +#define BL_MD_SIZEOF (64u) + + +/******************************************************************************* +* Metadata base address. In case of bootloader application, the metadata is +* placed at row N-1; in case of multi-application bootloader, the bootloadable +* application number 1 will use row N-1, and application number 2 will use row +* N-2 to store its metadata, where N is the total number of rows for the +* selected device. +*******************************************************************************/ +#define BL_MD_BASE_ADDR(appId) (CYDEV_FLASH_BASE + \ + (CYDEV_FLASH_SIZE - ((uint32)(appId) * CYDEV_FLS_ROW_SIZE) - \ + BL_MD_SIZEOF)) + +#define BL_MD_FLASH_ARRAY_NUM (BL_NUM_OF_FLASH_ARRAYS - 1u) + +#define BL_MD_ROW_NUM(appId) ((CY_FLASH_NUMBER_ROWS / BL_NUM_OF_FLASH_ARRAYS) - \ + 1u - (uint32)(appId)) + +#define BL_MD_BTLDB_CHECKSUM_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 0u) +#if(CY_PSOC3) + #define BL_MD_BTLDB_ADDR_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 3u) + #define BL_MD_BTLDR_LAST_ROW_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 7u) + #define BL_MD_BTLDB_LENGTH_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 11u) +#else + #define BL_MD_BTLDB_ADDR_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 1u) + #define BL_MD_BTLDR_LAST_ROW_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 5u) + #define BL_MD_BTLDB_LENGTH_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 9u) +#endif /* (CY_PSOC3) */ +#define BL_MD_BTLDB_ACTIVE_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 16u) +#define BL_MD_BTLDB_VERIFIED_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 17u) +#define BL_MD_BTLDR_APP_VERSION_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 18u) +#define BL_MD_BTLDB_APP_ID_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 20u) +#define BL_MD_BTLDB_APP_VERSION_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 22u) +#define BL_MD_BTLDB_APP_CUST_ID_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 24u) + + +/******************************************************************************* +* Macro for 1 byte long metadata fields +*******************************************************************************/ +#define BL_MD_BTLDB_CHECKSUM_PTR (appId) \ + ((reg8 *)(BL_MD_BTLDB_CHECKSUM_OFFSET(appId))) +#define BL_MD_BTLDB_CHECKSUM_VALUE(appId) \ + (CY_GET_XTND_REG8(BL_MD_BTLDB_CHECKSUM_OFFSET(appId))) + +#define BL_MD_BTLDB_ACTIVE_PTR(appId) \ + ((reg8 *)(BL_MD_BTLDB_ACTIVE_OFFSET(appId))) +#define BL_MD_BTLDB_ACTIVE_VALUE(appId) \ + (CY_GET_XTND_REG8(BL_MD_BTLDB_ACTIVE_OFFSET(appId))) + +#define BL_MD_BTLDB_VERIFIED_PTR(appId) \ + ((reg8 *)(BL_MD_BTLDB_VERIFIED_OFFSET(appId))) +#define BL_MD_BTLDB_VERIFIED_VALUE(appId) \ + (CY_GET_XTND_REG8(BL_MD_BTLDB_VERIFIED_OFFSET(appId))) + + +/******************************************************************************* +* Macro for multiple bytes long metadata fields pointers +*******************************************************************************/ +#define BL_MD_BTLDB_ADDR_PTR (appId) \ + ((reg8 *)(BL_MD_BTLDB_ADDR_OFFSET(appId))) + +#define BL_MD_BTLDR_LAST_ROW_PTR (appId) \ + ((reg8 *)(BL_MD_BTLDR_LAST_ROW_OFFSET(appId))) + +#define BL_MD_BTLDB_LENGTH_PTR(appId) \ + ((reg8 *)(BL_MD_BTLDB_LENGTH_OFFSET(appId))) + +#define BL_MD_BTLDR_APP_VERSION_PTR(appId) \ + ((reg8 *)(BL_MD_BTLDR_APP_VERSION_OFFSET(appId))) + +#define BL_MD_BTLDB_APP_ID_PTR(appId) \ + ((reg8 *)(BL_MD_BTLDB_APP_ID_OFFSET(appId))) + +#define BL_MD_BTLDB_APP_VERSION_PTR(appId) \ + ((reg8 *)(BL_MD_BTLDB_APP_VERSION_OFFSET(appId))) + +#define BL_MD_BTLDB_APP_CUST_ID_PTR(appId) \ + ((reg8 *)(BL_MD_BTLDB_APP_CUST_ID_OFFSET(appId))) + + +/******************************************************************************* +* Get data byte from FLASH +*******************************************************************************/ +#if(CY_PSOC3) + #define BL_GET_CODE_BYTE(addr) (*((uint8 CYCODE *) (addr))) +#else + #define BL_GET_CODE_BYTE(addr) (*((uint8 *)(CYDEV_FLASH_BASE + (addr)))) +#endif /* (CY_PSOC3) */ + + +#if(!CY_PSOC4) + #define BL_GET_EEPROM_BYTE(addr) (*((uint8 *)(CYDEV_EE_BASE + (addr)))) +#endif /* (CY_PSOC3) */ + + +/* Our definition of a row size. */ +#if((!CY_PSOC4) && (CYDEV_ECC_ENABLE == 0)) + #define BL_FROW_SIZE ((CYDEV_FLS_ROW_SIZE) + (CYDEV_ECC_ROW_SIZE)) +#else + #define BL_FROW_SIZE CYDEV_FLS_ROW_SIZE +#endif /* ((!CY_PSOC4) && (CYDEV_ECC_ENABLE == 0)) */ + + +/******************************************************************************* +* Offset of the Bootloader application in flash +*******************************************************************************/ +#if(CY_PSOC4) + #define BL_MD_BTLDR_ADDR_PTR (0xC0u) /* Exclude the vector */ +#else + #define BL_MD_BTLDR_ADDR_PTR (0x00u) +#endif /* (CY_PSOC4) */ + + +/******************************************************************************* +* Maximum number of Bootloadable applications +*******************************************************************************/ +#if(1u == BL_DUAL_APP_BOOTLOADER) + #define BL_MAX_NUM_OF_BTLDB (0x02u) +#else + #define BL_MAX_NUM_OF_BTLDB (0x01u) +#endif /* (1u == BL_DUAL_APP_BOOTLOADER) */ + + +/******************************************************************************* +* Returns TRUE if row specified as parameter contains metadata section +*******************************************************************************/ +#if(0u != BL_DUAL_APP_BOOTLOADER) + #define BL_CONTAIN_METADATA(row) \ + ((BL_MD_ROW_NUM(BL_MD_BTLDB_ACTIVE_0) == (row)) || \ + (BL_MD_ROW_NUM(BL_MD_BTLDB_ACTIVE_1) == (row))) +#else + #define BL_CONTAIN_METADATA(row) \ + (BL_MD_ROW_NUM(BL_MD_BTLDB_ACTIVE_0) == (row)) +#endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ + + +/******************************************************************************* +* Metadata section is located at the last flash row for the Boootloader, for the +* Multi-Application Bootloader, metadata section of the Bootloadable application +* # 0 is located at the last flash row, and metadata section of the Bootloadable +* application # 1 is located in the flash row before last. +*******************************************************************************/ +#if(0u != BL_DUAL_APP_BOOTLOADER) + #define BL_GET_APP_ID(row) \ + ((BL_MD_ROW_NUM(BL_MD_BTLDB_ACTIVE_0) == (row)) ? \ + BL_MD_BTLDB_ACTIVE_0 : \ + BL_MD_BTLDB_ACTIVE_1) +#else + #define BL_GET_APP_ID(row) (BL_MD_BTLDB_ACTIVE_0) +#endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ + +#endif /* CY_BOOTLOADER_BL_PVT_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/Cm3Iar.icf b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/Cm3Iar.icf new file mode 100644 index 00000000..c8b4bcc8 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/Cm3Iar.icf @@ -0,0 +1,113 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x0; +define symbol __ICFEDIT_region_ROM_end__ = 131072 - 1; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000 - (32768 / 2); +define symbol __ICFEDIT_region_RAM_end__ = 0x20000000 + (32768 / 2) - 1; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_heap__ = 0x0800; +/**** End of ICF editor section. ###ICF###*/ + + +/******** Definitions ********/ +define symbol CY_APPL_LOADABLE = 0; +define symbol CY_APPL_LOADER = 1; +define symbol CY_APPL_NUM = 1; +define symbol CY_APPL_MAX = 1; +define symbol CY_METADATA_SIZE = 64; +define symbol CY_EE_IN_BTLDR = 0x0; +define symbol CY_EE_SIZE = 2048; + +if (!CY_APPL_LOADABLE) { + define symbol CYDEV_BTLDR_SIZE = 0; +} + +define symbol CY_FLASH_SIZE = 131072; +define symbol CY_APPL_ORIGIN = 0; +define symbol CY_FLASH_ROW_SIZE = 256; +define symbol CY_ECC_ROW_SIZE = 32; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, last block CSTACK}; + +define block LOADER { readonly section .cybootloader }; +define block APPL with fixed order {readonly section .romvectors, readonly}; + +/* The address of Flash row next after Bootloader image */ +define symbol CY_BTLDR_END = CYDEV_BTLDR_SIZE + + ((CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE) ? + (CY_FLASH_ROW_SIZE - (CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE)) : 0); + +/* The start address of Standard/Loader/Loadable#1 image */ +define symbol CY_APPL1_START = CY_APPL_ORIGIN ? CY_APPL_ORIGIN : CY_BTLDR_END; + +/* The number of metadata records located at the end of Flash */ +define symbol CY_METADATA_CNT = (CY_APPL_NUM == 2) ? 2 : ((CY_APPL_LOADER || CY_APPL_LOADABLE) ? 1 : 0); + +/* The application area size measured in rows */ +define symbol CY_APPL_ROW_CNT = ((CY_FLASH_SIZE - CY_APPL1_START) / CY_FLASH_ROW_SIZE) - CY_METADATA_CNT; + +/* The start address of Loadable#2 image if any */ +define symbol CY_APPL2_START = CY_APPL1_START + (CY_APPL_ROW_CNT / 2 + CY_APPL_ROW_CNT % 2) * CY_FLASH_ROW_SIZE; + +/* The current image (Standard/Loader/Loadable) start address */ +define symbol CY_APPL_START = (CY_APPL_NUM == 1) ? CY_APPL1_START : CY_APPL2_START; + +/* The ECC data placement address */ +define exported symbol CY_ECC_OFFSET = (CY_APPL_START / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE; + +/* The EEPROM offset and size that can be used by current application (Standard/Loader/Loadable) */ +define symbol CY_EE_OFFSET = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? ((CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1)) : 0; +define symbol CY_EE_IN_USE = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? (CY_EE_SIZE / CY_APPL_MAX) : CY_EE_SIZE; + +/* Define EEPROM region */ +define region EEPROM_region = mem:[from (0x90200000 + CY_EE_OFFSET) size CY_EE_IN_USE]; + +/* Define APPL region that will limit application size */ +define region APPL_region = mem:[from CY_APPL_START size CY_APPL_ROW_CNT * CY_FLASH_ROW_SIZE]; + + +/****** Initializations ******/ +initialize by copy { readwrite }; +do not initialize { section .noinit }; +do not initialize { readwrite section .ramvectors }; + +/******** Placements *********/ +".cybootloader" : place at start of ROM_region {block LOADER}; +"APPL" : place at start of APPL_region {block APPL}; + +"RAMVEC" : place at start of RAM_region { readwrite section .ramvectors }; +"readwrite" : place in RAM_region { readwrite }; +"HSTACK" : place at end of RAM_region { block HSTACK}; + +keep { section .cybootloader, + section .cyloadermeta, + section .cyloadablemeta, + section .cyconfigecc, + section .cycustnvl, + section .cywolatch, + section .cyeeprom, + section .cyflashprotect, + section .cymeta }; + +".cyloadermeta" : place at address mem : (CY_APPL_LOADER ? (CY_FLASH_SIZE - CY_METADATA_SIZE) : 0xF0000000) { readonly section .cyloadermeta }; +".cyloadablemeta" : place at address mem : (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) { readonly section .cyloadablemeta }; +".cyconfigecc" : place at address mem : (0x80000000 + CY_ECC_OFFSET) { readonly section .cyconfigecc }; +".cycustnvl" : place at address mem : 0x90000000 { readonly section .cycustnvl }; +".cywolatch" : place at address mem : 0x90100000 { readonly section .cywolatch }; +".cyeeprom" : place in EEPROM_region { readonly section .cyeeprom }; +".cyflashprotect" : place at address mem : 0x90400000 { readonly section .cyflashprotect }; +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +/* EOF */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/Cm3RealView.scat b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/Cm3RealView.scat new file mode 100644 index 00000000..d3772112 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/Cm3RealView.scat @@ -0,0 +1,190 @@ +#! armcc -E +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************** +;* File Name: Cm3RealView.scat +;* Version 4.0 +;* +;* Description: +;* This Linker Descriptor file describes the memory layout of the PSoC5 +;* device. The memory layout of the final binary and hex images as well as +;* the placement in PSoC5 memory is described. +;* +;* +;* Note: +;* +;* romvectors: Cypress default Interrupt sevice routine vector table. +;* +;* This is the ISR vector table at bootup. Used only for the reset vector. +;* +;* +;* ramvectors: Cypress ram interrupt service routine vector table. +;* +;* This is the ISR vector table used by the application. +;* +;* +;******************************************************************************** +;* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +;* You may use this file only in accordance with the license, terms, conditions, +;* disclaimers, and limitations in the end user license agreement accompanying +;* the software package with which this file was provided. +;********************************************************************************/ +#include "cyfitter.h" + +#define CY_FLASH_SIZE 131072 +#define CY_APPL_ORIGIN 0 +#define CY_FLASH_ROW_SIZE 256 +#define CY_ECC_ROW_SIZE 32 +#define CY_EE_SIZE 2048 +#define CY_METADATA_SIZE 64 + + +; Define application base address +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) + #define CY_APPL_NUM 1 + #define CY_APPL_MAX 1 + #define CY_EE_IN_BTLDR + + #if CY_APPL_ORIGIN + #define APPL1_START CY_APPL_ORIGIN + #else + #define APPL1_START AlignExpr(ImageLimit(CYBOOTLOADER), CY_FLASH_ROW_SIZE) + #endif + + #define APPL_START (APPL1_START + AlignExpr(((CY_FLASH_SIZE - APPL1_START - 2 * CY_FLASH_ROW_SIZE) / 2 ) * (CY_APPL_NUM - 1), CY_FLASH_ROW_SIZE)) + #define ECC_OFFSET ((APPL_START / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE) + #define EE_OFFSET (CY_EE_IN_BTLDR ? 0 : (CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1)) + #define EE_SIZE (CY_EE_IN_BTLDR ? CY_EE_SIZE : (CY_EE_SIZE / CY_APPL_MAX)) + +#else + + #define APPL_START 0 + #define ECC_OFFSET 0 + #define EE_OFFSET 0 + #define EE_SIZE CY_EE_SIZE + +#endif + + +; Place Bootloader at the beginning of Flash +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) + + CYBOOTLOADER 0 + { + .cybootloader +0 + { + * (.cybootloader) + } + } + + #if CY_APPL_ORIGIN + ScatterAssert(APPL_START > LoadLimit(CYBOOTLOADER)) + #endif + +#endif + + +APPLICATION APPL_START (CY_FLASH_SIZE - APPL_START) +{ + VECTORS +0 + { + * (.romvectors) + } + + CODE +0 + { + * (+RO) + } + + ISRVECTORS (0x20000000 - (32768 / 2)) UNINIT + { + * (.ramvectors) + } + + NOINIT_DATA +0 UNINIT + { + * (.noinit) + } + + DATA +0 + { + .ANY (+RW, +ZI) + } + + ARM_LIB_HEAP (0x20000000 + (32768 / 2) - 0x0800 - 0x2000) EMPTY 0x0800 + { + } + + ARM_LIB_STACK (0x20000000 + (32768 / 2)) EMPTY -0x2000 + { + } +} + + +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_BOOTLOADER || CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER) + + CYLOADERMETA (CY_FLASH_SIZE - CY_METADATA_SIZE) + { + .cyloadermeta +0 { * (.cyloadermeta) } + } + +#else + + #if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) + + CYLOADABLEMETA (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) + { + .cyloadablemeta +0 { * (.cyloadablemeta) } + } + + #endif + +#endif + +#if (CYDEV_ECC_ENABLE == 0) + + CYCONFIGECC (0x80000000 + ECC_OFFSET) + { + .cyconfigecc +0 { * (.cyconfigecc) } + } + +#endif + +CYCUSTNVL 0x90000000 +{ + .cycustnvl +0 { * (.cycustnvl) } +} + +CYWOLATCH 0x90100000 +{ + .cywolatch +0 { * (.cywolatch) } +} + +#if defined(CYDEV_ALLOCATE_EEPROM) + + CYEEPROM 0x90200000 + EE_OFFSET (EE_SIZE) + { + .cyeeprom +0 { * (.cyeeprom) } + } + +#endif + +CYFLASHPROTECT 0x90400000 +{ + .cyflashprotect +0 { * (.cyflashprotect) } +} + +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) + + CYLOADERMETA +0 + { + .cyloadermeta +0 { * (.cyloadermeta) } + } + +#endif diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/Cm3Start.c b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/Cm3Start.c new file mode 100644 index 00000000..14bcbf8d --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/Cm3Start.c @@ -0,0 +1,461 @@ +/******************************************************************************* +* File Name: Cm3Start.c +* Version 4.0 +* +* Description: +* Startup code for the ARM CM3. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "cydevice_trm.h" +#include "cytypes.h" +#include "cyfitter_cfg.h" +#include "CyLib.h" +#include "CyDmac.h" +#include "cyfitter.h" + +#define CY_NUM_INTERRUPTS (32u) +#define CY_NUM_VECTORS (CYINT_IRQ_BASE + CY_NUM_INTERRUPTS) +#define CY_NUM_ROM_VECTORS (4u) +#define CY_NVIC_APINT_PTR ((reg32 *) CYREG_NVIC_APPLN_INTR) +#define CY_NVIC_CFG_CTRL_PTR ((reg32 *) CYREG_NVIC_CFG_CONTROL) +#define CY_NVIC_APINT_PRIGROUP_3_5 (0x00000400u) /* Priority group 3.5 split */ +#define CY_NVIC_APINT_VECTKEY (0x05FA0000u) /* This key is required in order to write the NVIC_APINT register */ +#define CY_NVIC_CFG_STACKALIGN (0x00000200u) /* This specifies that the exception stack must be 8 byte aligned */ + + +/* Extern functions */ +extern void CyBtldr_CheckLaunch(void); + +/* Function prototypes */ +void initialize_psoc(void); +CY_ISR(IntDefaultHandler); +void Reset(void); +CY_ISR(IntDefaultHandler); + +#if defined(__ARMCC_VERSION) + #define INITIAL_STACK_POINTER ((cyisraddress)(uint32)&Image$$ARM_LIB_STACK$$ZI$$Limit) +#elif defined (__GNUC__) + #define INITIAL_STACK_POINTER (&__cy_stack) +#elif defined (__ICCARM__) + #pragma language=extended + #pragma segment="CSTACK" + #define INITIAL_STACK_POINTER { .__ptr = __sfe( "CSTACK" ) } + + extern void __iar_program_start( void ); + extern void __iar_data_init3 (void); +#endif /* (__ARMCC_VERSION) */ + +/* Global variables */ +#if !defined (__ICCARM__) + CY_NOINIT static uint32 cySysNoInitDataValid; +#endif /* !defined (__ICCARM__) */ + + +/******************************************************************************* +* Default Ram Interrupt Vector table storage area. Must be 256-byte aligned. +*******************************************************************************/ +#if defined (__ICCARM__) + #pragma location=".ramvectors" + #pragma data_alignment=256 +#else + CY_SECTION(".ramvectors") + CY_ALIGN(256) +#endif /* defined (__ICCARM__) */ +cyisraddress CyRamVectors[CY_NUM_VECTORS]; + + +/******************************************************************************* +* Function Name: IntDefaultHandler +******************************************************************************** +* +* Summary: +* This function is called for all interrupts, other than reset, that get +* called before the system is setup. +* +* Parameters: +* None +* +* Return: +* None +* +* Theory: +* Any value other than zero is acceptable. +* +*******************************************************************************/ +CY_ISR(IntDefaultHandler) +{ + + while(1) + { + /*********************************************************************** + * We should never get here. If we do, a serious problem occured, so go + * into an infinite loop. + ***********************************************************************/ + } +} + + +#if defined(__ARMCC_VERSION) + +/* Local function for the device reset. */ +extern void Reset(void); + +/* Application entry point. */ +extern void $Super$$main(void); + +/* Linker-generated Stack Base addresses, Two Region and One Region */ +extern uint32 Image$$ARM_LIB_STACK$$ZI$$Limit; + +/* RealView C Library initialization. */ +extern int __main(void); + + +/******************************************************************************* +* Function Name: Reset +******************************************************************************** +* +* Summary: +* This function handles the reset interrupt for the RVDS/MDK toolchains. +* This is the first bit of code that is executed at startup. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void Reset(void) +{ + #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) + + /* For PSoC 5LP, debugging is enabled by default */ + #if(CYDEV_DEBUGGING_ENABLE == 0) + *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK; + #endif /* (CYDEV_DEBUGGING_ENABLE) */ + + /* Reset Status Register has Read-to-clear SW access mode. + * Preserve current RESET_SR0 state to make it available for next reading. + */ + *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0); + + #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */ + + #if(CYDEV_BOOTLOADER_ENABLE) + CyBtldr_CheckLaunch(); + #endif /* (CYDEV_BOOTLOADER_ENABLE) */ + + __main(); +} + + +/******************************************************************************* +* Function Name: $Sub$$main +******************************************************************************** +* +* Summary: +* This function is called imediatly before the users main +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void $Sub$$main(void) +{ + initialize_psoc(); + + /* Call original main */ + $Super$$main(); + + while (1) + { + /* If main returns it is undefined what we should do. */ + } +} + +#elif defined(__GNUC__) + +void Start_c(void); + +/* Stack Base address */ +extern void __cy_stack(void); + +/* Application entry point. */ +extern int main(void); + +/* The static objects constructors initializer */ +extern void __libc_init_array(void); + +typedef unsigned char __cy_byte_align8 __attribute ((aligned (8))); + +struct __cy_region +{ + __cy_byte_align8 *init; /* Initial contents of this region. */ + __cy_byte_align8 *data; /* Start address of region. */ + size_t init_size; /* Size of initial data. */ + size_t zero_size; /* Additional size to be zeroed. */ +}; + +extern const struct __cy_region __cy_regions[]; +extern const char __cy_region_num __attribute__((weak)); +#define __cy_region_num ((size_t)&__cy_region_num) + + +/******************************************************************************* +* Function Name: Reset +******************************************************************************** +* +* Summary: +* This function handles the reset interrupt for the GCC toolchain. This is the +* first bit of code that is executed at startup. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void Reset(void) +{ + #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) + + /* For PSoC 5LP, debugging is enabled by default */ + #if(CYDEV_DEBUGGING_ENABLE == 0) + *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK; + #endif /* (CYDEV_DEBUGGING_ENABLE) */ + + /* Reset Status Register has Read-to-clear SW access mode. + * Preserve current RESET_SR0 state to make it available for next reading. + */ + *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0); + + #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */ + + #if(CYDEV_BOOTLOADER_ENABLE) + CyBtldr_CheckLaunch(); + #endif /* (CYDEV_BOOTLOADER_ENABLE) */ + + Start_c(); +} + +__attribute__((weak)) +void _exit(int status) +{ + /* Cause a divide by 0 exception */ + int x = status / INT_MAX; + x = 4 / x; + + while(1) + { + } +} + +/******************************************************************************* +* Function Name: Start_c +******************************************************************************** +* +* Summary: +* This function handles initializing the .data and .bss sections in +* preperation for running standard C code. Once initialization is complete +* it will call main(). This function will never return. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void Start_c(void) __attribute__ ((noreturn)); +void Start_c(void) +{ + unsigned regions = __cy_region_num; + const struct __cy_region *rptr = __cy_regions; + + /* Initialize memory */ + for (regions = __cy_region_num, rptr = __cy_regions; regions--; rptr++) + { + uint32 *src = (uint32 *)rptr->init; + uint32 *dst = (uint32 *)rptr->data; + unsigned limit = rptr->init_size; + unsigned count; + + for (count = 0u; count != limit; count += sizeof (uint32)) + { + *dst++ = *src++; + } + limit = rptr->zero_size; + for (count = 0u; count != limit; count += sizeof (uint32)) + { + *dst++ = 0u; + } + } + + /* Invoke static objects constructors */ + __libc_init_array(); + (void) main(); + + while (1) + { + /* If main returns, make sure we don't return. */ + } +} + + +#elif defined (__ICCARM__) + +/******************************************************************************* +* Function Name: __low_level_init +******************************************************************************** +* +* Summary: +* This function perform early initializations for the IAR Embedded +* Workbench IDE. It is executed in the context of reset interrupt handler +* before the data sections are initialized. +* +* Parameters: +* None +* +* Return: +* The value that determines whether or not data sections should be initialized +* by the system startup code: +* 0 - skip data sections initialization; +* 1 - initialize data sections; +* +*******************************************************************************/ +int __low_level_init(void) +{ + #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) + + /* For PSoC 5LP, debugging is enabled by default */ + #if(CYDEV_DEBUGGING_ENABLE == 0) + *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK; + #endif /* (CYDEV_DEBUGGING_ENABLE) */ + + /* Reset Status Register has Read-to-clear SW access mode. + * Preserve current RESET_SR0 state to make it available for next reading. + */ + *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0); + + #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */ + + #if (CYDEV_BOOTLOADER_ENABLE) + CyBtldr_CheckLaunch(); + #endif /* CYDEV_BOOTLOADER_ENABLE */ + + /* Initialize data sections */ + __iar_data_init3(); + + initialize_psoc(); + + return 0; +} + +#endif /* __GNUC__ */ + + +/******************************************************************************* +* +* Default Rom Interrupt Vector table. +* +*******************************************************************************/ +#if defined(__ARMCC_VERSION) + /* Suppress diagnostic message 1296-D: extended constant initialiser used */ + #pragma diag_suppress 1296 +#endif /* defined(__ARMCC_VERSION) */ + +#if defined (__ICCARM__) + #pragma location=".romvectors" + const intvec_elem __vector_table[CY_NUM_ROM_VECTORS] = +#else + CY_SECTION(".romvectors") + const cyisraddress RomVectors[CY_NUM_ROM_VECTORS] = +#endif /* defined (__ICCARM__) */ +{ + INITIAL_STACK_POINTER, /* The initial stack pointer 0 */ + #if defined (__ICCARM__) /* The reset handler 1 */ + __iar_program_start, + #else + (cyisraddress)&Reset, + #endif /* defined (__ICCARM__) */ + &IntDefaultHandler, /* The NMI handler 2 */ + &IntDefaultHandler, /* The hard fault handler 3 */ +}; + +#if defined(__ARMCC_VERSION) + #pragma diag_default 1296 +#endif /* defined(__ARMCC_VERSION) */ + + +/******************************************************************************* +* Function Name: initialize_psoc +******************************************************************************** +* +* Summary: +* This function used to initialize the PSoC chip before calling main. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +#if (defined(__GNUC__) && !defined(__ARMCC_VERSION)) +__attribute__ ((constructor(101))) +#endif +void initialize_psoc(void) +{ + uint32 i; + + /* Set Priority group 5. */ + + /* Writes to NVIC_APINT register require the VECTKEY in the upper half */ + *CY_NVIC_APINT_PTR = CY_NVIC_APINT_VECTKEY | CY_NVIC_APINT_PRIGROUP_3_5; + *CY_NVIC_CFG_CTRL_PTR |= CY_NVIC_CFG_STACKALIGN; + + /* Set Ram interrupt vectors to default functions. */ + for (i = 0u; i < CY_NUM_VECTORS; i++) + { + #if defined (__ICCARM__) + CyRamVectors[i] = (i < CY_NUM_ROM_VECTORS) ? __vector_table[i].__fun : &IntDefaultHandler; + #else + CyRamVectors[i] = (i < CY_NUM_ROM_VECTORS) ? RomVectors[i] : &IntDefaultHandler; + #endif /* defined (__ICCARM__) */ + } + + /* Was stored in CFGMEM to avoid being cleared while SRAM gets cleared */ + CyResetStatus = CY_GET_REG8(CYREG_PHUB_CFGMEM23_CFG1); + + /* Point NVIC at the RAM vector table. */ + *CYINT_VECT_TABLE = CyRamVectors; + + /* Initialize the configuration registers. */ + cyfitter_cfg(); + + #if(0u != DMA_CHANNELS_USED__MASK0) + + /* Setup DMA - only necessary if the design contains a DMA component. */ + CyDmacConfigure(); + + #endif /* (0u != DMA_CHANNELS_USED__MASK0) */ + + #if !defined (__ICCARM__) + /* Actually, no need to clean this variable, just to make compiler happy. */ + cySysNoInitDataValid = 0u; + #endif /* !defined (__ICCARM__) */ +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s new file mode 100644 index 00000000..5ac6ba97 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s @@ -0,0 +1,174 @@ +/******************************************************************************* +* File Name: CyBootAsmGnu.s +* Version 4.0 +* +* Description: +* Assembly routines for GNU as. +* +******************************************************************************** +* Copyright 2010-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +.include "cyfittergnu.inc" + +.syntax unified +.text +.thumb + + +/******************************************************************************* +* Function Name: CyDelayCycles +******************************************************************************** +* +* Summary: +* Delays for the specified number of cycles. +* +* Parameters: +* uint32 cycles: number of cycles to delay. +* +* Return: +* None +* +*******************************************************************************/ +/* void CyDelayCycles(uint32 cycles) */ +.align 3 /* Align to 8 byte boundary (2^n) */ +.global CyDelayCycles +.func CyDelayCycles, CyDelayCycles +.type CyDelayCycles, %function +.thumb_func +CyDelayCycles: /* cycles bytes */ +/* If ICache is enabled */ +.ifeq CYDEV_INSTRUCT_CACHE_ENABLED - 1 + + ADDS r0, r0, #2 /* 1 2 Round to nearest multiple of 4 */ + LSRS r0, r0, #2 /* 1 2 Divide by 4 and set flags */ + BEQ CyDelayCycles_done /* 2 2 Skip if 0 */ + NOP /* 1 2 Loop alignment padding */ + +CyDelayCycles_loop: + SUBS r0, r0, #1 /* 1 2 */ + MOV r0, r0 /* 1 2 Pad loop to power of two cycles */ + BNE CyDelayCycles_loop /* 2 2 */ + +CyDelayCycles_done: + BX lr /* 3 2 */ + +.else + + CMP r0, #20 /* 1 2 If delay is short - jump to cycle */ + BLS CyDelayCycles_short /* 1 2 */ + PUSH {r1} /* 2 2 PUSH r1 to stack */ + MOVS r1, #1 /* 1 2 */ + + SUBS r0, r0, #20 /* 1 2 Subtract overhead */ + LDR r1,=CYREG_CACHE_CC_CTL/* 2 2 Load flash wait cycles value */ + LDRB r1, [r1, #0] /* 2 2 */ + ANDS r1, #0xC0 /* 1 2 */ + + LSRS r1, r1, #6 /* 1 2 */ + PUSH {r2} /* 1 2 PUSH r2 to stack */ + LDR r2, =cy_flash_cycles /* 2 2 */ + LDRB r1, [r2, r1] /* 2 2 */ + + POP {r2} /* 2 2 POP r2 from stack */ + NOP /* 1 2 Alignment padding */ + NOP /* 1 2 Alignment padding */ + NOP /* 1 2 Alignment padding */ + +CyDelayCycles_loop: + SBCS r0, r0, r1 /* 1 2 */ + BPL CyDelayCycles_loop /* 3 2 */ + NOP /* 1 2 Loop alignment padding */ + NOP /* 1 2 Loop alignment padding */ + + POP {r1} /* 2 2 POP r1 from stack */ +CyDelayCycles_done: + BX lr /* 3 2 */ + NOP /* 1 2 Alignment padding */ + NOP /* 1 2 Alignment padding */ + +CyDelayCycles_short: + SBCS r0, r0, #4 /* 1 2 */ + BPL CyDelayCycles_short /* 3 2 */ + BX lr /* 3 2 */ + +cy_flash_cycles: +.byte 0x0B +.byte 0x05 +.byte 0x07 +.byte 0x09 +.endif + +.endfunc + + +/******************************************************************************* +* Function Name: CyEnterCriticalSection +******************************************************************************** +* +* Summary: +* CyEnterCriticalSection disables interrupts and returns a value indicating +* whether interrupts were previously enabled (the actual value depends on +* whether the device is PSoC 3 or PSoC 5). +* +* Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit +* with interrupts still enabled. The test and set of the interrupt bits is not +* atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid +* corrupting processor state, it must be the policy that all interrupt routines +* restore the interrupt enable bits as they were found on entry. +* +* Parameters: +* None +* +* Return: +* uint8 +* Returns 0 if interrupts were previously enabled or 1 if interrupts +* were previously disabled. +* +*******************************************************************************/ +/* uint8 CyEnterCriticalSection(void) */ +.global CyEnterCriticalSection +.func CyEnterCriticalSection, CyEnterCriticalSection +.type CyEnterCriticalSection, %function +.thumb_func +CyEnterCriticalSection: + MRS r0, PRIMASK /* Save and return interrupt state */ + CPSID I /* Disable interrupts */ + BX lr +.endfunc + + +/******************************************************************************* +* Function Name: CyExitCriticalSection +******************************************************************************** +* +* Summary: +* CyExitCriticalSection re-enables interrupts if they were enabled before +* CyEnterCriticalSection was called. The argument should be the value returned +* from CyEnterCriticalSection. +* +* Parameters: +* uint8 savedIntrStatus: +* Saved interrupt status returned by the CyEnterCriticalSection function. +* +* Return: +* None +* +*******************************************************************************/ +/* void CyExitCriticalSection(uint8 savedIntrStatus) */ +.global CyExitCriticalSection +.func CyExitCriticalSection, CyExitCriticalSection +.type CyExitCriticalSection, %function +.thumb_func +CyExitCriticalSection: + MSR PRIMASK, r0 /* Restore interrupt state */ + BX lr +.endfunc + +.end + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s new file mode 100644 index 00000000..f2e8f940 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s @@ -0,0 +1,156 @@ +;------------------------------------------------------------------------------- +; FILENAME: CyBootAsmIar.s +; Version 4.0 +; +; DESCRIPTION: +; Assembly routines for IAR Embedded Workbench IDE. +; +;------------------------------------------------------------------------------- +; Copyright 2013, Cypress Semiconductor Corporation. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + + SECTION .text:CODE:ROOT(4) + PUBLIC CyDelayCycles + PUBLIC CyEnterCriticalSection + PUBLIC CyExitCriticalSection + INCLUDE cyfitteriar.inc + THUMB + + +;------------------------------------------------------------------------------- +; Function Name: CyEnterCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; CyEnterCriticalSection disables interrupts and returns a value indicating +; whether interrupts were previously enabled. +; +; Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit +; with interrupts still enabled. The test and set of the interrupt bits is not +; atomic. Therefore, to avoid corrupting processor state, it must be the policy +; that all interrupt routines restore the interrupt enable bits as they were +; found on entry. +; +; Parameters: +; None +; +; Return: +; uint8 +; Returns 0 if interrupts were previously enabled or 1 if interrupts +; were previously disabled. +; +;------------------------------------------------------------------------------- +; uint8 CyEnterCriticalSection(void) + +CyEnterCriticalSection: + MRS r0, PRIMASK ; Save and return interrupt state + CPSID I ; Disable interrupts + BX lr + + +;------------------------------------------------------------------------------- +; Function Name: CyExitCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; CyExitCriticalSection re-enables interrupts if they were enabled before +; CyEnterCriticalSection was called. The argument should be the value returned +; from CyEnterCriticalSection. +; +; Parameters: +; uint8 savedIntrStatus: +; Saved interrupt status returned by the CyEnterCriticalSection function. +; +; Return: +; None +; +;------------------------------------------------------------------------------- +; void CyExitCriticalSection(uint8 savedIntrStatus) + +CyExitCriticalSection: + MSR PRIMASK, r0 ; Restore interrupt state + BX lr + + +;------------------------------------------------------------------------------- +; Function Name: CyDelayCycles +;------------------------------------------------------------------------------- +; +; Summary: +; Delays for the specified number of cycles. +; +; Parameters: +; uint32 cycles: number of cycles to delay. +; +; Return: +; None +; +;------------------------------------------------------------------------------- +; void CyDelayCycles(uint32 cycles) + +CyDelayCycles: + IF CYDEV_INSTRUCT_CACHE_ENABLED == 1 + ; cycles bytes + ADDS r0, r0, #2 ; 1 2 Round to nearest multiple of 4 + LSRS r0, r0, #2 ; 1 2 Divide by 4 and set flags + BEQ CyDelayCycles_done ; 2 2 Skip if 0 + NOP ; 1 2 Loop alignment padding +CyDelayCycles_loop: + SUBS r0, r0, #1 ; 1 2 + MOV r0, r0 ; 1 2 Pad loop to power of two cycles + BNE CyDelayCycles_loop ; 2 2 +CyDelayCycles_done: + BX lr ; 3 2 + + ELSE + + CMP r0, #20 ; 1 2 If delay is short - jump to cycle + BLS CyDelayCycles_short ; 1 2 + PUSH {r1} ; 2 2 PUSH r1 to stack + MOVS r1, #1 ; 1 2 + + SUBS r0, r0, #20 ; 1 2 Subtract overhead + LDR r1,=CYREG_CACHE_CC_CTL; 2 2 Load flash wait cycles value + LDRB r1, [r1, #0] ; 2 2 + ANDS r1, r1, #0xC0 ; 1 2 + + LSRS r1, r1, #6 ; 1 2 + PUSH {r2} ; 1 2 PUSH r2 to stack + LDR r2, =cy_flash_cycles ; 2 2 + LDRB r1, [r2, r1] ; 2 2 + + POP {r2} ; 2 2 POP r2 from stack + NOP ; 1 2 Alignment padding + NOP ; 1 2 Alignment padding + NOP ; 1 2 Alignment padding + +CyDelayCycles_loop: + SBCS r0, r0, r1 ; 1 2 + BPL CyDelayCycles_loop ; 3 2 + NOP ; 1 2 Loop alignment padding + NOP ; 1 2 Loop alignment padding + + POP {r1} ; 2 2 POP r1 from stack +CyDelayCycles_done: + BX lr ; 3 2 + NOP ; 1 2 Alignment padding + NOP ; 1 2 Alignment padding +CyDelayCycles_short: + SBCS r0, r0, #4 ; 1 2 + BPL CyDelayCycles_short ; 3 2 + BX lr ; 3 2 + NOP ; 1 2 Loop alignment padding + + DATA +cy_flash_cycles: +byte_1 DCB 0x0B +byte_2 DCB 0x05 +byte_3 DCB 0x07 +byte_4 DCB 0x09 + + ENDIF + + END diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s new file mode 100644 index 00000000..c10181e7 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s @@ -0,0 +1,161 @@ +;------------------------------------------------------------------------------- +; FILENAME: CyBootAsmRv.s +; Version 4.0 +; +; DESCRIPTION: +; Assembly routines for RealView. +; +;------------------------------------------------------------------------------- +; Copyright 2010-2013, Cypress Semiconductor Corporation. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + + AREA |.text|,CODE,ALIGN=3 + THUMB + EXTERN Reset + + GET cyfitterrv.inc + +;------------------------------------------------------------------------------- +; Function Name: CyDelayCycles +;------------------------------------------------------------------------------- +; +; Summary: +; Delays for the specified number of cycles. +; +; Parameters: +; uint32 cycles: number of cycles to delay. +; +; Return: +; None +; +;------------------------------------------------------------------------------- +; void CyDelayCycles(uint32 cycles) + ALIGN 8 +CyDelayCycles FUNCTION + EXPORT CyDelayCycles + IF CYDEV_INSTRUCT_CACHE_ENABLED == 1 + ; cycles bytes + ADDS r0, r0, #2 ; 1 2 Round to nearest multiple of 4 + LSRS r0, r0, #2 ; 1 2 Divide by 4 and set flags + BEQ CyDelayCycles_done ; 2 2 Skip if 0 + NOP ; 1 2 Loop alignment padding +CyDelayCycles_loop + SUBS r0, r0, #1 ; 1 2 + MOV r0, r0 ; 1 2 Pad loop to power of two cycles + BNE CyDelayCycles_loop ; 2 2 + NOP ; 1 2 Loop alignment padding +CyDelayCycles_done + BX lr ; 3 2 + + ELSE + + CMP r0, #20 ; 1 2 If delay is short - jump to cycle + BLS CyDelayCycles_short ; 1 2 + PUSH {r1} ; 2 2 PUSH r1 to stack + MOVS r1, #1 ; 1 2 + + SUBS r0, r0, #20 ; 1 2 Subtract overhead + LDR r1,=CYREG_CACHE_CC_CTL; 2 2 Load flash wait cycles value + LDRB r1, [r1, #0] ; 2 2 + ANDS r1, #0xC0 ; 1 2 + + LSRS r1, r1, #6 ; 1 2 + PUSH {r2} ; 1 2 PUSH r2 to stack + LDR r2, =cy_flash_cycles ; 2 2 + LDRB r1, [r2, r1] ; 2 2 + + POP {r2} ; 2 2 POP r2 from stack + NOP ; 1 2 Alignment padding + NOP ; 1 2 Alignment padding + NOP ; 1 2 Alignment padding + +CyDelayCycles_loop + SBCS r0, r0, r1 ; 1 2 + BPL CyDelayCycles_loop ; 3 2 + NOP ; 1 2 Loop alignment padding + NOP ; 1 2 Loop alignment padding + + POP {r1} ; 2 2 POP r1 from stack +CyDelayCycles_done + BX lr ; 3 2 + NOP ; 1 2 Alignment padding + NOP ; 1 2 Alignment padding + +CyDelayCycles_short + SBCS r0, r0, #4 ; 1 2 + BPL CyDelayCycles_short ; 3 2 + BX lr ; 3 2 + +cy_flash_cycles +byte_1 DCB 0x0B +byte_2 DCB 0x05 +byte_3 DCB 0x07 +byte_4 DCB 0x09 + + ENDIF + ENDFUNC + + +;------------------------------------------------------------------------------- +; Function Name: CyEnterCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; CyEnterCriticalSection disables interrupts and returns a value indicating +; whether interrupts were previously enabled (the actual value depends on +; whether the device is PSoC 3 or PSoC 5). +; +; Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit +; with interrupts still enabled. The test and set of the interrupt bits is not +; atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid +; corrupting processor state, it must be the policy that all interrupt routines +; restore the interrupt enable bits as they were found on entry. +; +; Parameters: +; None +; +; Return: +; uint8 +; Returns 0 if interrupts were previously enabled or 1 if interrupts +; were previously disabled. +; +;------------------------------------------------------------------------------- +; uint8 CyEnterCriticalSection(void) +CyEnterCriticalSection FUNCTION + EXPORT CyEnterCriticalSection + MRS r0, PRIMASK ; Save and return interrupt state + CPSID I ; Disable interrupts + BX lr + ENDFUNC + + +;------------------------------------------------------------------------------- +; Function Name: CyExitCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; CyExitCriticalSection re-enables interrupts if they were enabled before +; CyEnterCriticalSection was called. The argument should be the value returned +; from CyEnterCriticalSection. +; +; Parameters: +; uint8 savedIntrStatus: +; Saved interrupt status returned by the CyEnterCriticalSection function. +; +; Return: +; None +; +;------------------------------------------------------------------------------- +; void CyExitCriticalSection(uint8 savedIntrStatus) +CyExitCriticalSection FUNCTION + EXPORT CyExitCriticalSection + MSR PRIMASK, r0 ; Restore interrupt state + BX lr + ENDFUNC + + END + +; [] END OF FILE diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyDmac.c b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyDmac.c new file mode 100644 index 00000000..e3858c62 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyDmac.c @@ -0,0 +1,1131 @@ +/******************************************************************************* +* File Name: CyDmac.c +* Version 4.0 +* +* Description: +* Provides an API for the DMAC component. The API includes functions for the +* DMA controller, DMA channels and Transfer Descriptors. +* +* This API is the library version not the auto generated code that gets +* generated when the user places a DMA component on the schematic. +* +* The auto generated code would use the APi's in this module. +* +* Note: +* This code is endian agnostic. +* +* The Transfer Descriptor memory can be used as regular memory if the TD's are +* not being used. +* +* This code uses the first byte of each TD to manage the free list of TD's. +* The user can over write this once the TD is allocated. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "CyDmac.h" + + +/******************************************************************************* +* The following variables are initialized from CyDmacConfigure() function that +* is executed from initialize_psoc() at the early initialization stage. +* In case of IAR EW IDE, initialize_psoc() is executed before the data sections +* are initialized. To avoid zeroing, these variables should be initialized +* properly during segments initialization as well. +*******************************************************************************/ +static uint8 CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS; /* Current Number of free elements in the list */ +static uint8 CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); /* Index of the first available TD */ +static uint32 CyDmaChannels = DMA_CHANNELS_USED__MASK0; /* Bit map of DMA channel ownership */ + + +/******************************************************************************* +* Function Name: CyDmacConfigure +******************************************************************************** +* +* Summary: +* Creates a linked list of all the TDs to be allocated. This function is called +* by the startup code; you do not normally need to call it. You could call this +* function if all of the DMA channels are inactive. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyDmacConfigure(void) +{ + uint8 dmaIndex; + + /* Set TD list variables. */ + CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); + CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS; + + /* Make TD free list. */ + for(dmaIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); dmaIndex != 0u; dmaIndex--) + { + CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = (uint8)(dmaIndex - 1u); + } + + /* Make the last one point to zero. */ + CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = 0u; +} + + +/******************************************************************************* +* Function Name: CyDmacError +******************************************************************************** +* +* Summary: +* Returns errors of the last failed DMA transaction. +* +* Parameters: +* None +* +* Return: +* Errors of the last failed DMA transaction. +* +* DMAC_PERIPH_ERR: +* Set to 1 when a peripheral responds to a bus transaction with an error +* response. +* +* DMAC_UNPOP_ACC: +* Set to 1 when an access is attempted to an invalid address. +* +* DMAC_BUS_TIMEOUT: +* Set to 1 when a bus timeout occurs. Cleared by writing a 1. Timeout values +* are determined by the BUS_TIMEOUT field in the PHUBCFG register. +* +* Theory: +* Once an error occurs the error bits are sticky and are only cleared by a +* write 1 to the error register. +* +*******************************************************************************/ +uint8 CyDmacError(void) +{ + return((uint8)(((uint32) 0x0Fu) & *CY_DMA_ERR_PTR)); +} + + +/******************************************************************************* +* Function Name: CyDmacClearError +******************************************************************************** +* +* Summary: +* Clears the error bits in the error register of the DMAC. +* +* Parameters: +* error: +* Clears the error bits in the DMAC error register. +* +* DMAC_PERIPH_ERR: +* Set to 1 when a peripheral responds to a bus transaction with an error +* response. +* +* DMAC_UNPOP_ACC: +* Set to 1 when an access is attempted to an invalid address. +* +* DMAC_BUS_TIMEOUT: +* Set to 1 when a bus timeout occurs. Cleared by writing a 1. Timeout values +* are determined by the BUS_TIMEOUT field in the PHUBCFG register. +* +* Return: +* None +* +* Theory: +* Once an error occurs the error bits are sticky and are only cleared by a +* write 1 to the error register. +* +*******************************************************************************/ +void CyDmacClearError(uint8 error) +{ + *CY_DMA_ERR_PTR = (((uint32)0x0Fu) & ((uint32)error)); +} + + +/******************************************************************************* +* Function Name: CyDmacErrorAddress +******************************************************************************** +* +* Summary: +* When an DMAC_BUS_TIMEOUT, DMAC_UNPOP_ACC and DMAC_PERIPH_ERR occurs the +* address of the error is written to the error address register and can be read +* with this function. +* +* If there are multiple errors, only the address of the first is saved. +* +* Parameters: +* None +* +* Return: +* The address that caused the error. +* +*******************************************************************************/ +uint32 CyDmacErrorAddress(void) +{ + return(CY_GET_REG32(CY_DMA_ERR_ADR_PTR)); +} + + +/******************************************************************************* +* Function Name: CyDmaChAlloc +******************************************************************************** +* +* Summary: +* Allocates a channel from the DMAC to be used in all functions that require a +* channel handle. +* +* Parameters: +* None +* +* Return: +* The allocated channel number. Zero is a valid channel number. +* DMA_INVALID_CHANNEL is returned if there are no channels available. +* +*******************************************************************************/ +uint8 CyDmaChAlloc(void) +{ + uint8 interruptState; + uint8 dmaIndex; + uint32 channel = 1u; + + + /* Enter critical section! */ + interruptState = CyEnterCriticalSection(); + + /* Look for a free channel. */ + for(dmaIndex = 0u; dmaIndex < CY_DMA_NUMBEROF_CHANNELS; dmaIndex++) + { + if(0uL == (CyDmaChannels & channel)) + { + /* Mark the channel as used. */ + CyDmaChannels |= channel; + break; + } + + channel <<= 1u; + } + + if(dmaIndex >= CY_DMA_NUMBEROF_CHANNELS) + { + dmaIndex = CY_DMA_INVALID_CHANNEL; + } + + /* Exit critical section! */ + CyExitCriticalSection(interruptState); + + return(dmaIndex); +} + + +/******************************************************************************* +* Function Name: CyDmaChFree +******************************************************************************** +* +* Summary: +* Frees a channel allocated by DmaChAlloc(). +* +* Parameters: +* uint8 chHandle: +* The handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChFree(uint8 chHandle) +{ + cystatus status = CYRET_BAD_PARAM; + uint8 interruptState; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + /* Enter critical section */ + interruptState = CyEnterCriticalSection(); + + /* Clear the bit mask that keeps track of ownership. */ + CyDmaChannels &= ~(((uint32) 1u) << chHandle); + + /* Exit critical section */ + CyExitCriticalSection(interruptState); + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChEnable +******************************************************************************** +* +* Summary: +* Enables the DMA channel. A software or hardware request still must happen +* before the channel is executed. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* +* uint8 preserveTds: +* Preserves the original TD state when the TD has completed. This parameter +* applies to all TDs in the channel. +* +* 0 - When a TD is completed, the DMAC leaves the TD configuration values in +* their current state, and does not restore them to their original state. +* +* 1 - When a TD is completed, the DMAC restores the original configuration +* values of the TD. +* +* When preserveTds is set, the TD slot that equals the channel number becomes +* RESERVED and that becomes where the working registers exist. So, for example, +* if you are using CH06 and preserveTds is set, you are not allowed to use TD +* slot 6. That is reclaimed by the DMA engine for its private use. +* +* Note Do not chain back to a completed TD if the preserveTds for the channel +* is set to 0. When a TD has completed preserveTds for the channel set to 0, +* the transfer count will be at 0. If a TD with a transfer count of 0 is +* started, the TD will transfer an indefinite amount of data. +* +* Take extra precautions when using the hardware request (DRQ) option when the +* preserveTds is set to 0, as you might be requesting the wrong data. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + if (0u != preserveTds) + { + /* Store the intermediate TD states separately in CHn_SEP_TD0/1 to + * preserve the original TD chain + */ + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= CY_DMA_CH_BASIC_CFG_WORK_SEP; + } + else + { + /* Store the intermediate and final TD states on top of the original TD chain */ + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_CH_BASIC_CFG_WORK_SEP); + } + + /* Enable channel */ + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= CY_DMA_CH_BASIC_CFG_EN; + + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChDisable +******************************************************************************** +* +* Summary: +* Disables the DMA channel. Once this function is called, CyDmaChStatus() may +* be called to determine when the channel is disabled and which TDs were being +* executed. +* +* If it is currently executing it will allow the current burst to finish +* naturally. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChDisable(uint8 chHandle) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + /*********************************************************************** + * Should not change configuration information of a DMA channel when it + * is active (or vulnerable to becoming active). + ***********************************************************************/ + + /* Disable channel */ + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_EN)); + + /* Store the intermediate and final TD states on top of the original TD chain */ + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_WORK_SEP)); + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaClearPendingDrq +******************************************************************************** +* +* Summary: +* Clears pending DMA data request. +* +* Parameters: +* uint8 chHandle: +* Handle to the dma channel. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaClearPendingDrq(uint8 chHandle) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + CY_DMA_CH_STRUCT_PTR[chHandle].action[0] |= CY_DMA_CPU_TERM_CHAIN; + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] |= 0x01u; + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChPriority +******************************************************************************** +* +* Summary: +* Sets the priority of a DMA channel. You can use this function when you want +* to change the priority at run time. If the priority remains the same for a +* DMA channel, then you can configure the priority in the .cydwr file. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* +* uint8 priority: +* Priority to set the channel to, 0 - 7. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChPriority(uint8 chHandle, uint8 priority) +{ + uint8 value; + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + value = CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] & ((uint8)(~(0x0Eu))); + + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] = value | ((uint8) ((priority & 0x7u) << 0x01u)); + + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChSetExtendedAddress +******************************************************************************** +* +* Summary: +* Sets the high 16 bits of the source and destination addresses for the DMA +* channel (valid for all TDs in the chain). +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* +* uint16 source: +* Upper 16 bit address of the DMA transfer source. +* +* uint16 destination: +* Upper 16 bit address of the DMA transfer destination. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destination) \ + +{ + cystatus status = CYRET_BAD_PARAM; + reg16 *convert; + + #if(CY_PSOC5) + + /* 0x1FFF8000-0x1FFFFFFF needs to use alias at 0x20008000-0x2000FFFF */ + if(source == 0x1FFFu) + { + source = 0x2000u; + } + + if(destination == 0x1FFFu) + { + destination = 0x2000u; + } + + #endif /* (CY_PSOC5) */ + + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + /* Set source address */ + convert = (reg16 *) &CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG1[0]; + CY_SET_REG16(convert, source); + + /* Set destination address */ + convert = (reg16 *) &CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG1[2u]; + CY_SET_REG16(convert, destination); + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChSetInitialTd +******************************************************************************** +* +* Summary: +* Sets the initial TD to be executed for the channel when the CyDmaChEnable() +* function is called. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize(). +* +* uint8 startTd: +* The index of TD to set as the first TD associated with the channel. Zero is +* a valid TD index. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChSetInitialTd(uint8 chHandle, uint8 startTd) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + CY_DMA_CH_STRUCT_PTR[chHandle].basic_status[1u] = startTd; + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChSetRequest +******************************************************************************** +* +* Summary: +* Allows the caller to terminate a chain of TDs, terminate one TD, or create a +* direct request to start the DMA channel. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* +* uint8 request: +* One of the following constants. Each of the constants is a three-bit value. +* +* CPU_REQ - Create a direct request to start the DMA channel +* CPU_TERM_TD - Terminate one TD +* CPU_TERM_CHAIN - Terminate a chain of TDs +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChSetRequest(uint8 chHandle, uint8 request) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + CY_DMA_CH_STRUCT_PTR[chHandle].action[0u] |= (request & (CPU_REQ | CPU_TERM_TD | CPU_TERM_CHAIN)); + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChGetRequest +******************************************************************************** +* +* Summary: +* This function allows the caller of CyDmaChSetRequest() to determine if the +* request was completed. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* +* Return: +* Returns a three-bit field, corresponding to the three bits of the request, +* which describes the state of the previously posted request. If the value is +* zero, the request was completed. CY_DMA_INVALID_CHANNEL if the handle is +* invalid. +* +*******************************************************************************/ +cystatus CyDmaChGetRequest(uint8 chHandle) +{ + cystatus status = CY_DMA_INVALID_CHANNEL; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + status = (cystatus) ((uint32)CY_DMA_CH_STRUCT_PTR[chHandle].action[0u] & + (uint32)(CY_DMA_CPU_REQ | CY_DMA_CPU_TERM_TD | CY_DMA_CPU_TERM_CHAIN)); + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChStatus +******************************************************************************** +* +* Summary: +* Determines the status of the DMA channel. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* +* uint8 * currentTd: +* The address to store the index of the current TD. Can be NULL if the value +* is not needed. +* +* uint8 * state: +* The address to store the state of the channel. Can be NULL if the value is +* not needed. +* +* STATUS_TD_ACTIVE +* 0: Channel is not currently being serviced by DMAC +* 1: Channel is currently being serviced by DMAC +* +* STATUS_CHAIN_ACTIVE +* 0: TD chain is inactive; either no DMA requests have triggered a new chain +* or the previous chain has completed. +* 1: TD chain has been triggered by a DMA request +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +* Theory: +* The caller can check on the activity of the Current TD and the Chain. +* +*******************************************************************************/ +cystatus CyDmaChStatus(uint8 chHandle, uint8 * currentTd, uint8 * state) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + if(NULL != currentTd) + { + *currentTd = CY_DMA_CH_STRUCT_PTR[chHandle].basic_status[1] & 0x7Fu; + } + + if(NULL != state) + { + *state= CY_DMA_CH_STRUCT_PTR[chHandle].basic_status[0]; + } + + status = CYRET_SUCCESS; + } + + return (status); +} + + +/******************************************************************************* +* Function Name: CyDmaChSetConfiguration +******************************************************************************** +* +* Summary: +* Sets configuration information of the channel. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize(). +* +* uint8 burstCount: +* Specifies the size of bursts (1 to 127) the data transfer should be divided +* into. If this value is zero then the whole transfer is done in one burst. +* +* uint8 requestPerBurst: +* The whole of the data can be split into multiple bursts, if this is +* required to complete the transaction: +* 0: All subsequent bursts after the first burst will be automatically +* requested and carried out +* 1: All subsequent bursts after the first burst must also be individually +* requested. +* +* uint8 tdDone0: +* Selects one of the TERMOUT0 interrupt lines to signal completion. The line +* connected to the nrq terminal will determine the TERMOUT0_SEL definition and +* should be used as supplied by cyfitter.h +* +* uint8 tdDone1: +* Selects one of the TERMOUT1 interrupt lines to signal completion. The line +* connected to the nrq terminal will determine the TERMOUT1_SEL definition and +* should be used as supplied by cyfitter.h +* +* uint8 tdStop: +* Selects one of the TERMIN interrupt lines to signal to the DMAC that the TD +* should terminate. The signal connected to the trq terminal will determine +* which TERMIN (termination request) is used. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChSetConfiguration(uint8 chHandle, uint8 burstCount, uint8 requestPerBurst, + uint8 tdDone0, uint8 tdDone1, uint8 tdStop) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[0] = (burstCount & 0x7Fu) | ((uint8)((requestPerBurst & 0x1u) << 7u)); + CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[1] = ((uint8)((tdDone1 & 0xFu) << 4u)) | (tdDone0 & 0xFu); + CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[2] = 0x0Fu & tdStop; + CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[3] = 0u; /* burstcount_remain. */ + + status = CYRET_SUCCESS; + } + + return (status); +} + + +/******************************************************************************* +* Function Name: CyDmaTdAllocate +******************************************************************************** +* +* Summary: +* Allocates a TD for use with an allocated DMA channel. +* +* Parameters: +* None +* +* Return: +* Zero-based index of the TD to be used by the caller. Since there are 128 TDs +* minus the reserved TDs (0 to 23), the value returned would range from 24 to +* 127 not 24 to 128. DMA_INVALID_TD is returned if there are no free TDs +* available. +* +*******************************************************************************/ +uint8 CyDmaTdAllocate(void) +{ + uint8 interruptState; + uint8 element = CY_DMA_INVALID_TD; + + /* Enter critical section! */ + interruptState = CyEnterCriticalSection(); + + if(CyDmaTdCurrentNumber > NUMBEROF_CHANNELS) + { + /* Get pointer to the Next available. */ + element = CyDmaTdFreeIndex; + + /* Decrement the count. */ + CyDmaTdCurrentNumber--; + + /* Update the next available pointer. */ + CyDmaTdFreeIndex = CY_DMA_TDMEM_STRUCT_PTR[element].TD0[0]; + } + + /* Exit critical section! */ + CyExitCriticalSection(interruptState); + + return(element); +} + + +/******************************************************************************* +* Function Name: CyDmaTdFree +******************************************************************************** +* +* Summary: +* Returns a TD to the free list. +* +* Parameters: +* uint8 tdHandle: +* The TD handle returned by the CyDmaTdAllocate(). +* +* Return: +* None +* +*******************************************************************************/ +void CyDmaTdFree(uint8 tdHandle) +{ + if(tdHandle < CY_DMA_NUMBEROF_TDS) + { + /* Enter critical section! */ + uint8 interruptState = CyEnterCriticalSection(); + + /* Get pointer to the Next available. */ + CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0u] = CyDmaTdFreeIndex; + + /* Set new Next Available. */ + CyDmaTdFreeIndex = tdHandle; + + /* Keep track of how many left. */ + CyDmaTdCurrentNumber++; + + /* Exit critical section! */ + CyExitCriticalSection(interruptState); + } +} + + +/******************************************************************************* +* Function Name: CyDmaTdFreeCount +******************************************************************************** +* +* Summary: +* Returns the number of free TDs available to be allocated. +* +* Parameters: +* None +* +* Return: +* The number of free TDs. +* +*******************************************************************************/ +uint8 CyDmaTdFreeCount(void) +{ + return(CyDmaTdCurrentNumber - CY_DMA_NUMBEROF_CHANNELS); +} + + +/******************************************************************************* +* Function Name: CyDmaTdSetConfiguration +******************************************************************************** +* +* Summary: +* Configures the TD. +* +* Parameters: +* uint8 tdHandle: +* A handle previously returned by CyDmaTdAlloc(). +* +* uint16 transferCount: +* The size of the data transfer (in bytes) for this TD. A size of zero will +* cause the transfer to continue indefinitely. This parameter is limited to +* 4095 bytes; the TD is not initialized at all when a higher value is passed. +* +* uint8 nextTd: +* Zero based index of the next Transfer Descriptor in the TD chain. Zero is a +* valid pointer to the next TD; DMA_END_CHAIN_TD is the end of the chain. +* DMA_DISABLE_TD indicates an end to the chain and the DMA is disabled. No +* further TDs are fetched. DMA_DISABLE_TD is only supported on PSoC3 and +* PSoC 5LP silicons. +* +* uint8 configuration: +* Stores the Bit field of configuration bits. +* +* CY_DMA_TD_SWAP_EN - Perform endian swap +* +* CY_DMA_TD_SWAP_SIZE4 - Swap size = 4 bytes +* +* CY_DMA_TD_AUTO_EXEC_NEXT - The next TD in the chain will trigger +* automatically when the current TD completes. +* +* CY_DMA_TD_TERMIN_EN - Terminate this TD if a positive edge on the trq +* input line occurs. The positive edge must occur +* during a burst. That is the only time the DMAC +* will listen for it. +* +* DMA__TD_TERMOUT_EN - When this TD completes, the TERMOUT signal will +* generate a pulse. Note that this option is +* instance specific with the instance name followed +* by two underscores. In this example, the instance +* name is DMA. +* +* CY_DMA_TD_INC_DST_ADR - Increment DST_ADR according to the size of each +* data transaction in the burst. +* +* CY_DMA_TD_INC_SRC_ADR - Increment SRC_ADR according to the size of each +* data transaction in the burst. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if tdHandle or transferCount is invalid. +* +*******************************************************************************/ +cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nextTd, uint8 configuration) \ + +{ + cystatus status = CYRET_BAD_PARAM; + + if((tdHandle < CY_DMA_NUMBEROF_TDS) && (0u == (0xF000u & transferCount))) + { + /* Set 12 bits transfer count. */ + reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0u]; + CY_SET_REG16(convert, transferCount); + + /* Set Next TD pointer. */ + CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[2u] = nextTd; + + /* Configure the TD */ + CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[3u] = configuration; + + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaTdGetConfiguration +******************************************************************************** +* +* Summary: +* Retrieves the configuration of the TD. If a NULL pointer is passed as a +* parameter, that parameter is skipped. You may request only the values you are +* interested in. +* +* Parameters: +* uint8 tdHandle: +* A handle previously returned by CyDmaTdAlloc(). +* +* uint16 * transferCount: +* The address to store the size of the data transfer (in bytes) for this TD. +* A size of zero could indicate that the TD has completed its transfer, or +* that the TD is doing an indefinite transfer. +* +* uint8 * nextTd: +* The address to store the index of the next TD in the TD chain. +* +* uint8 * configuration: +* The address to store the Bit field of configuration bits. +* See CyDmaTdSetConfiguration() function description. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if tdHandle is invalid. +* +* Side Effects: +* If a TD has a transfer count of N and is executed, the transfer count becomes +* 0. If it is reexecuted, the Transfer count of zero will be interpreted as a +* request for indefinite transfer. Be careful when requesting a TD with a +* transfer count of zero. +* +*******************************************************************************/ +cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 * nextTd, uint8 * configuration) \ + +{ + cystatus status = CYRET_BAD_PARAM; + + if(tdHandle < CY_DMA_NUMBEROF_TDS) + { + /* If we have a pointer */ + if(NULL != transferCount) + { + /* Get the 12 bits of the transfer count */ + reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0]; + *transferCount = 0x0FFFu & CY_GET_REG16(convert); + } + + /* If we have a pointer */ + if(NULL != nextTd) + { + /* Get the Next TD pointer */ + *nextTd = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[2u]; + } + + /* If we have a pointer */ + if(NULL != configuration) + { + /* Get the configuration the TD */ + *configuration = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[3u]; + } + + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaTdSetAddress +******************************************************************************** +* +* Summary: +* Sets the lower 16 bits of the source and destination addresses for this TD +* only. +* +* Parameters: +* uint8 tdHandle: +* A handle previously returned by CyDmaTdAlloc(). +* +* uint16 source: +* The lower 16 address bits of the source of the data transfer. +* +* uint16 destination: +* The lower 16 address bits of the destination of the data transfer. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if tdHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaTdSetAddress(uint8 tdHandle, uint16 source, uint16 destination) +{ + cystatus status = CYRET_BAD_PARAM; + reg16 *convert; + + if(tdHandle < CY_DMA_NUMBEROF_TDS) + { + /* Set source address */ + convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[0u]; + CY_SET_REG16(convert, source); + + /* Set destination address */ + convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[2u]; + CY_SET_REG16(convert, destination); + + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaTdGetAddress +******************************************************************************** +* +* Summary: +* Retrieves the lower 16 bits of the source and/or destination addresses for +* this TD only. If NULL is passed for a pointer parameter, that value is +* skipped. You may request only the values of interest. +* +* Parameters: +* uint8 tdHandle: +* A handle previously returned by CyDmaTdAlloc(). +* +* uint16 * source: +* The address to store the lower 16 address bits of the source of the data +* transfer. +* +* uint16 * destination: +* The address to store the lower 16 address bits of the destination of the +* data transfer. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if tdHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination) +{ + cystatus status = CYRET_BAD_PARAM; + reg16 *convert; + + if(tdHandle < CY_DMA_NUMBEROF_TDS) + { + /* If we have a pointer. */ + if(NULL != source) + { + /* Get source address */ + convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[0u]; + *source = CY_GET_REG16(convert); + } + + /* If we have a pointer. */ + if(NULL != destination) + { + /* Get Destination address. */ + convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[2u]; + *destination = CY_GET_REG16(convert); + } + + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChRoundRobin +******************************************************************************** +* +* Summary: +* Either enables or disables the Round-Robin scheduling enforcement algorithm. +* Within a priority level a Round-Robin fairness algorithm is enforced. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or Dma_DmaInitialize(). +* +* uint8 enableRR: +* 0: Disable Round-Robin fairness algorithm +* 1: Enable Round-Robin fairness algorithm +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChRoundRobin(uint8 chHandle, uint8 enableRR) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + if (0u != enableRR) + { + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= (uint8)CY_DMA_ROUND_ROBIN_ENABLE; + } + else + { + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_ROUND_ROBIN_ENABLE); + } + + status = CYRET_SUCCESS; + } + + return(status); +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h new file mode 100644 index 00000000..5dfac11a --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h @@ -0,0 +1,218 @@ +/******************************************************************************* +* File Name: CyDmac.h +* Version 4.0 +* +* Description: +* Provides the function definitions for the DMA Controller. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYDMAC_H) +#define CY_BOOT_CYDMAC_H + + +#include "cytypes.h" +#include "cyfitter.h" +#include "cydevice_trm.h" +#include "CyLib.h" + + +/*************************************** +* Function Prototypes +***************************************/ + +/* DMA Controller functions. */ +void CyDmacConfigure(void) ; +uint8 CyDmacError(void) ; +void CyDmacClearError(uint8 error) ; +uint32 CyDmacErrorAddress(void) ; + +/* Channel specific functions. */ +uint8 CyDmaChAlloc(void) ; +cystatus CyDmaChFree(uint8 chHandle) ; +cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds) ; +cystatus CyDmaChDisable(uint8 chHandle) ; +cystatus CyDmaClearPendingDrq(uint8 chHandle) ; +cystatus CyDmaChPriority(uint8 chHandle, uint8 priority) ; +cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destination)\ +; +cystatus CyDmaChSetInitialTd(uint8 chHandle, uint8 startTd) ; +cystatus CyDmaChSetRequest(uint8 chHandle, uint8 request) ; +cystatus CyDmaChGetRequest(uint8 chHandle) ; +cystatus CyDmaChStatus(uint8 chHandle, uint8 * currentTd, uint8 * state) ; +cystatus CyDmaChSetConfiguration(uint8 chHandle, uint8 burstCount, uint8 requestPerBurst, uint8 tdDone0, + uint8 tdDone1, uint8 tdStop) ; +cystatus CyDmaChRoundRobin(uint8 chHandle, uint8 enableRR) ; + +/* Transfer Descriptor functions. */ +uint8 CyDmaTdAllocate(void) ; +void CyDmaTdFree(uint8 tdHandle) ; +uint8 CyDmaTdFreeCount(void) ; +cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nextTd, uint8 configuration)\ +; +cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 * nextTd, uint8 * configuration)\ +; +cystatus CyDmaTdSetAddress(uint8 tdHandle, uint16 source, uint16 destination) ; +cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination) ; + + +/*************************************** +* Data Struct Definitions +***************************************/ + +typedef struct dmac_ch_struct +{ + volatile uint8 basic_cfg[4]; + volatile uint8 action[4]; + volatile uint8 basic_status[4]; + volatile uint8 reserved[4]; + +} dmac_ch; + + +typedef struct dmac_cfgmem_struct +{ + volatile uint8 CFG0[4]; + volatile uint8 CFG1[4]; + +} dmac_cfgmem; + + +typedef struct dmac_tdmem_struct +{ + volatile uint8 TD0[4]; + volatile uint8 TD1[4]; + +} dmac_tdmem; + + +typedef struct dmac_tdmem2_struct +{ + volatile uint16 xfercnt; + volatile uint8 next_td_ptr; + volatile uint8 flags; + volatile uint16 src_adr; + volatile uint16 dst_adr; +} dmac_tdmem2; + + +/*************************************** +* API Constants +***************************************/ + +#define CY_DMA_INVALID_CHANNEL 0xFFu /* Invalid Channel ID */ +#define CY_DMA_INVALID_TD 0xFFu /* Invalid TD */ +#define CY_DMA_END_CHAIN_TD 0xFFu /* End of chain TD */ +#define CY_DMA_DISABLE_TD 0xFEu + +#define CY_DMA_TD_SIZE 0x08u + +/* The "u" was removed as workaround for Keil compiler bug */ +#define CY_DMA_TD_SWAP_EN 0x80 +#define CY_DMA_TD_SWAP_SIZE4 0x40 +#define CY_DMA_TD_AUTO_EXEC_NEXT 0x20 +#define CY_DMA_TD_TERMIN_EN 0x10 +#define CY_DMA_TD_TERMOUT1_EN 0x08 +#define CY_DMA_TD_TERMOUT0_EN 0x04 +#define CY_DMA_TD_INC_DST_ADR 0x02 +#define CY_DMA_TD_INC_SRC_ADR 0x01 + +#define CY_DMA_NUMBEROF_TDS 128u +#define CY_DMA_NUMBEROF_CHANNELS ((uint8)(CYDEV_DMA_CHANNELS_AVAILABLE)) + +/* Action register bits */ +#define CY_DMA_CPU_REQ ((uint8)(1u << 0u)) +#define CY_DMA_CPU_TERM_TD ((uint8)(1u << 1u)) +#define CY_DMA_CPU_TERM_CHAIN ((uint8)(1u << 2u)) + +/* Basic Status register bits */ +#define CY_DMA_STATUS_CHAIN_ACTIVE ((uint8)(1u << 0u)) +#define CY_DMA_STATUS_TD_ACTIVE ((uint8)(1u << 1u)) + +/* DMA controller register error bits */ +#define CY_DMA_BUS_TIMEOUT (1u << 1u) +#define CY_DMA_UNPOP_ACC (1u << 2u) +#define CY_DMA_PERIPH_ERR (1u << 3u) + +/* Round robin bits */ +#define CY_DMA_ROUND_ROBIN_ENABLE ((uint8)(1u << 4u)) + + +/******************************************************************************* +* CyDmaChEnable() / CyDmaChDisable() API constants +*******************************************************************************/ +#define CY_DMA_CH_BASIC_CFG_EN (0x01u) +#define CY_DMA_CH_BASIC_CFG_WORK_SEP (0x20u) + + +/*************************************** +* Registers +***************************************/ + +#define CY_DMA_CFG_REG (*(reg32 *) CYREG_PHUB_CFG) +#define CY_DMA_CFG_PTR ( (reg32 *) CYREG_PHUB_CFG) + +#define CY_DMA_ERR_REG (*(reg32 *) CYREG_PHUB_ERR) +#define CY_DMA_ERR_PTR ( (reg32 *) CYREG_PHUB_ERR) + +#define CY_DMA_ERR_ADR_REG (*(reg32 *) CYREG_PHUB_ERR_ADR) +#define CY_DMA_ERR_ADR_PTR ( (reg32 *) CYREG_PHUB_ERR_ADR) + +#define CY_DMA_CH_STRUCT_REG (*(dmac_ch CYXDATA *) CYDEV_PHUB_CH0_BASE) +#define CY_DMA_CH_STRUCT_PTR ( (dmac_ch CYXDATA *) CYDEV_PHUB_CH0_BASE) + +#define CY_DMA_CFGMEM_STRUCT_REG (*(dmac_cfgmem CYXDATA *) CYDEV_PHUB_CFGMEM0_BASE) +#define CY_DMA_CFGMEM_STRUCT_PTR ( (dmac_cfgmem CYXDATA *) CYDEV_PHUB_CFGMEM0_BASE) + +#define CY_DMA_TDMEM_STRUCT_REG (*(dmac_tdmem CYXDATA *) CYDEV_PHUB_TDMEM0_BASE) +#define CY_DMA_TDMEM_STRUCT_PTR ( (dmac_tdmem CYXDATA *) CYDEV_PHUB_TDMEM0_BASE) + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from cy_boot 3.0 +*******************************************************************************/ +#define DMA_INVALID_CHANNEL (CY_DMA_INVALID_CHANNEL) +#define DMA_INVALID_TD (CY_DMA_INVALID_TD) +#define DMA_END_CHAIN_TD (CY_DMA_END_CHAIN_TD) +#define DMAC_TD_SIZE (CY_DMA_TD_SIZE) +#define TD_SWAP_EN (CY_DMA_TD_SWAP_EN) +#define TD_SWAP_SIZE4 (CY_DMA_TD_SWAP_SIZE4) +#define TD_AUTO_EXEC_NEXT (CY_DMA_TD_AUTO_EXEC_NEXT) +#define TD_TERMIN_EN (CY_DMA_TD_TERMIN_EN) +#define TD_TERMOUT1_EN (CY_DMA_TD_TERMOUT1_EN) +#define TD_TERMOUT0_EN (CY_DMA_TD_TERMOUT0_EN) +#define TD_INC_DST_ADR (CY_DMA_TD_INC_DST_ADR) +#define TD_INC_SRC_ADR (CY_DMA_TD_INC_SRC_ADR) +#define NUMBEROF_TDS (CY_DMA_NUMBEROF_TDS) +#define NUMBEROF_CHANNELS (CY_DMA_NUMBEROF_CHANNELS) +#define CPU_REQ (CY_DMA_CPU_REQ) +#define CPU_TERM_TD (CY_DMA_CPU_TERM_TD) +#define CPU_TERM_CHAIN (CY_DMA_CPU_TERM_CHAIN) +#define STATUS_CHAIN_ACTIVE (CY_DMA_STATUS_CHAIN_ACTIVE) +#define STATUS_TD_ACTIVE (CY_DMA_STATUS_TD_ACTIVE) +#define DMAC_BUS_TIMEOUT (CY_DMA_BUS_TIMEOUT) +#define DMAC_UNPOP_ACC (CY_DMA_UNPOP_ACC) +#define DMAC_PERIPH_ERR (CY_DMA_PERIPH_ERR) +#define ROUND_ROBIN_ENABLE (CY_DMA_ROUND_ROBIN_ENABLE) +#define DMA_DISABLE_TD (CY_DMA_DISABLE_TD) + +#define DMAC_CFG (CY_DMA_CFG_PTR) +#define DMAC_ERR (CY_DMA_ERR_PTR) +#define DMAC_ERR_ADR (CY_DMA_ERR_ADR_PTR) +#define DMAC_CH (CY_DMA_CH_STRUCT_PTR) +#define DMAC_CFGMEM (CY_DMA_CFGMEM_STRUCT_PTR) +#define DMAC_TDMEM (CY_DMA_TDMEM_STRUCT_PTR) + +#endif /* (CY_BOOT_CYDMAC_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyFlash.c b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyFlash.c new file mode 100644 index 00000000..6f27d8c0 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyFlash.c @@ -0,0 +1,694 @@ +/******************************************************************************* +* File Name: CyFlash.c +* Version 4.0 +* +* Description: +* Provides an API for the FLASH/EEPROM. +* +* Note: +* This code is endian agnostic. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "CyFlash.h" + + +/******************************************************************************* +* Holds die temperature, updated by CySetTemp(). Used for flash writting. +* The first byte is the sign of the temperature (0 = negative, 1 = positive). +* The second byte is the magnitude. +*******************************************************************************/ +uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE]; + +#if(CYDEV_ECC_ENABLE == 0) + static uint8 * rowBuffer = 0; +#endif /* (CYDEV_ECC_ENABLE == 0) */ + + +static cystatus CySetTempInt(void); + + +/******************************************************************************* +* Function Name: CyFlash_Start +******************************************************************************** +* +* Summary: +* Enable the Flash. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyFlash_Start(void) +{ + /* Active Power Mode */ + *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK; + + /* Standby Power Mode */ + *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK; + + CyDelayUs(CY_FLASH_EE_STARTUP_DELAY); +} + + +/******************************************************************************* +* Function Name: CyFlash_Stop +******************************************************************************** +* +* Summary: +* Disable the Flash. +* +* Parameters: +* None +* +* Return: +* None +* +* Side Effects: +* This setting is ignored as long as the CPU is currently running. This will +* only take effect when the CPU is later disabled. +* +*******************************************************************************/ +void CyFlash_Stop(void) +{ + /* Active Power Mode */ + *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK)); + + /* Standby Power Mode */ + *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK)); +} + + +/******************************************************************************* +* Function Name: CySetTempInt +******************************************************************************** +* +* Summary: +* Sends a command to the SPC to read the die temperature. Sets a global value +* used by the Write functions. This function must be called once before +* executing a series of Flash writing functions. +* +* Parameters: +* None +* +* Return: +* status: +* CYRET_SUCCESS - if successful +* CYRET_LOCKED - if Flash writing already in use +* CYRET_UNKNOWN - if there was an SPC error +* +*******************************************************************************/ +static cystatus CySetTempInt(void) +{ + cystatus status; + + /* Make sure SPC is powered */ + CySpcStart(); + + /* Plan for failure. */ + status = CYRET_UNKNOWN; + + if(CySpcLock() == CYRET_SUCCESS) + { + /* Write the command. */ + if(CYRET_STARTED == CySpcGetTemp(CY_TEMP_NUMBER_OF_SAMPLES)) + { + do + { + if(CySpcReadData(dieTemperature, CY_FLASH_DIE_TEMP_DATA_SIZE) == CY_FLASH_DIE_TEMP_DATA_SIZE) + { + status = CYRET_SUCCESS; + + while(CY_SPC_BUSY) + { + /* Spin until idle. */ + CyDelayUs(1u); + } + break; + } + + } while(CY_SPC_BUSY); + } + + CySpcUnlock(); + } + else + { + status = CYRET_LOCKED; + } + + return (status); +} + + +/******************************************************************************* +* Function Name: CySetTemp +******************************************************************************** +* +* Summary: +* This is a wraparound for CySetTempInt(). It is used to return second +* successful read of temperature value. +* +* Parameters: +* None +* +* Return: +* status: +* CYRET_SUCCESS if successful. +* CYRET_LOCKED if Flash writing already in use +* CYRET_UNKNOWN if there was an SPC error. +* +* uint8 dieTemperature[2]: +* Holds die temperature for the flash writting algorithm. The first byte is +* the sign of the temperature (0 = negative, 1 = positive). The second byte is +* the magnitude. +* +*******************************************************************************/ +cystatus CySetTemp(void) +{ + cystatus status = CySetTempInt(); + + if(status == CYRET_SUCCESS) + { + status = CySetTempInt(); + } + + return (status); +} + + +/******************************************************************************* +* Function Name: CySetFlashEEBuffer +******************************************************************************** +* +* Summary: +* Sets the user supplied temporary buffer to store SPC data while performing +* flash and EEPROM commands. This buffer is only necessary when Flash ECC is +* disabled. +* +* Parameters: +* buffer: +* Address of block of memory to store temporary memory. The size of the block +* of memory is CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE. +* +* Return: +* status: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if the buffer is NULL +* +*******************************************************************************/ +cystatus CySetFlashEEBuffer(uint8 * buffer) +{ + cystatus status = CYRET_SUCCESS; + + CySpcStart(); + + #if(CYDEV_ECC_ENABLE == 0) + + if(NULL == buffer) + { + status = CYRET_BAD_PARAM; + } + else if(CySpcLock() != CYRET_SUCCESS) + { + status = CYRET_LOCKED; + } + else + { + rowBuffer = buffer; + CySpcUnlock(); + } + + #else + + /* To supress the warning */ + buffer = buffer; + + #endif /* (CYDEV_ECC_ENABLE == 0u) */ + + return(status); +} + + +#if(CYDEV_ECC_ENABLE == 1) + + /******************************************************************************* + * Function Name: CyWriteRowData + ******************************************************************************** + * + * Summary: + * Sends a command to the SPC to load and program a row of data in + * Flash or EEPROM. + * + * Parameters: + * arrayID: ID of the array to write. + * The type of write, Flash or EEPROM, is determined from the array ID. + * The arrays in the part are sequential starting at the first ID for the + * specific memory type. The array ID for the Flash memory lasts from 0x00 to + * 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F. + * rowAddress: rowAddress of flash row to program. + * rowData: Array of bytes to write. + * + * Return: + * status: + * CYRET_SUCCESS if successful. + * CYRET_LOCKED if the SPC is already in use. + * CYRET_CANCELED if command not accepted + * CYRET_UNKNOWN if there was an SPC error. + * + *******************************************************************************/ + cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) + { + uint16 rowSize; + cystatus status; + + rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? CYDEV_EEPROM_ROW_SIZE : CYDEV_FLS_ROW_SIZE; + status = CyWriteRowFull(arrayId, rowAddress, rowData, rowSize); + + return(status); + } + +#else + + /******************************************************************************* + * Function Name: CyWriteRowData + ******************************************************************************** + * + * Summary: + * Sends a command to the SPC to load and program a row of data in + * Flash or EEPROM. + * + * Parameters: + * arrayID : ID of the array to write. + * The type of write, Flash or EEPROM, is determined from the array ID. + * The arrays in the part are sequential starting at the first ID for the + * specific memory type. The array ID for the Flash memory lasts from 0x00 to + * 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F. + * rowAddress : rowAddress of flash row to program. + * rowData : Array of bytes to write. + * + * Return: + * status: + * CYRET_SUCCESS if successful. + * CYRET_LOCKED if the SPC is already in use. + * CYRET_CANCELED if command not accepted + * CYRET_UNKNOWN if there was an SPC error. + * + *******************************************************************************/ + cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) + { + uint8 i; + uint32 offset; + uint16 rowSize; + cystatus status; + + /* Check whether rowBuffer pointer has been initialized by CySetFlashEEBuffer() */ + if(NULL != rowBuffer) + { + if(arrayId > CY_SPC_LAST_FLASH_ARRAYID) + { + rowSize = CYDEV_EEPROM_ROW_SIZE; + } + else + { + rowSize = CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE; + + /* Save the ECC area. */ + offset = CYDEV_ECC_BASE + + ((uint32)arrayId * CYDEV_ECC_SECTOR_SIZE) + + ((uint32)rowAddress * CYDEV_ECC_ROW_SIZE); + + for(i = 0u; i < CYDEV_ECC_ROW_SIZE; i++) + { + *(rowBuffer + CYDEV_FLS_ROW_SIZE + i) = CY_GET_XTND_REG8((void CYFAR *)(offset + i)); + } + } + + /* Copy the rowdata to the temporary buffer. */ + #if(CY_PSOC3) + (void) memcpy((void *) rowBuffer, (void *)((uint32) rowData), (int16) CYDEV_FLS_ROW_SIZE); + #else + (void) memcpy((void *) rowBuffer, (const void *) rowData, CYDEV_FLS_ROW_SIZE); + #endif /* (CY_PSOC3) */ + + status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, rowSize); + } + else + { + status = CYRET_UNKNOWN; + } + + return(status); + } + +#endif /* (CYDEV_ECC_ENABLE == 0u) */ + + +#if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) + + /******************************************************************************* + * Function Name: CyWriteRowConfig + ******************************************************************************** + * + * Summary: + * Sends a command to the SPC to load and program a row of config data in flash. + * This function is only valid for Flash array IDs (not for EEPROM). + * + * Parameters: + * arrayId: ID of the array to write + * The arrays in the part are sequential starting at the first ID for the + * specific memory type. The array ID for the Flash memory lasts + * from 0x00 to 0x3F. + * rowAddress: Address of the sector to erase. + * rowECC: Array of bytes to write. + * + * Return: + * status: + * CYRET_SUCCESS if successful. + * CYRET_LOCKED if the SPC is already in use. + * CYRET_CANCELED if command not accepted + * CYRET_UNKNOWN if there was an SPC error. + * + *******************************************************************************/ + cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC)\ + + { + uint32 offset; + uint16 i; + cystatus status; + + /* Check whether rowBuffer pointer has been initialized by CySetFlashEEBuffer() */ + if(NULL != rowBuffer) + { + /* Read the existing flash data. */ + offset = ((uint32)arrayId * CYDEV_FLS_SECTOR_SIZE) + + ((uint32)rowAddress * CYDEV_FLS_ROW_SIZE); + + #if (CYDEV_FLS_BASE != 0u) + offset += CYDEV_FLS_BASE; + #endif /* (CYDEV_FLS_BASE != 0u) */ + + for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++) + { + rowBuffer[i] = CY_GET_XTND_REG8((void CYFAR *)(offset + i)); + } + + #if(CY_PSOC3) + (void) memcpy((void *)&rowBuffer[CYDEV_FLS_ROW_SIZE], + (void *)(uint32)rowECC, + (int16)CYDEV_ECC_ROW_SIZE); + #else + (void) memcpy((void *)&rowBuffer[CYDEV_FLS_ROW_SIZE], + (const void *)rowECC, + CYDEV_ECC_ROW_SIZE); + #endif /* (CY_PSOC3) */ + + status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE); + } + else + { + status = CYRET_UNKNOWN; + } + + return (status); + } + +#endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */ + + + +/******************************************************************************* +* Function Name: CyWriteRowFull +******************************************************************************** +* Summary: +* Sends a command to the SPC to load and program a row of data in flash. +* rowData array is expected to contain Flash and ECC data if needed. +* +* Parameters: +* arrayId: FLASH or EEPROM array id. +* rowData: Pointer to a row of data to write. +* rowNumber: Zero based number of the row. +* rowSize: Size of the row. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_LOCKED if the SPC is already in use. +* CYRET_CANCELED if command not accepted +* CYRET_UNKNOWN if there was an SPC error. +* +*******************************************************************************/ +cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8* rowData, uint16 rowSize) \ + +{ + cystatus status; + + if(CySpcLock() == CYRET_SUCCESS) + { + /* Load row data into SPC internal latch */ + status = CySpcLoadRow(arrayId, rowData, rowSize); + + if(CYRET_STARTED == status) + { + while(CY_SPC_BUSY) + { + /* Wait for SPC to finish and get SPC status */ + CyDelayUs(1u); + } + + /* Hide SPC status */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + else + { + status = CYRET_UNKNOWN; + } + + if(CYRET_SUCCESS == status) + { + /* Erase and program flash with the data from SPC interval latch */ + status = CySpcWriteRow(arrayId, rowNumber, dieTemperature[0u], dieTemperature[1u]); + + if(CYRET_STARTED == status) + { + while(CY_SPC_BUSY) + { + /* Wait for SPC to finish and get SPC status */ + CyDelayUs(1u); + } + + /* Hide SPC status */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + else + { + status = CYRET_UNKNOWN; + } + } + } + + } + + CySpcUnlock(); + } + else + { + status = CYRET_LOCKED; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyFlash_SetWaitCycles +******************************************************************************** +* +* Summary: +* Sets the number of clock cycles the cache will wait before it samples data +* coming back from Flash. This function must be called before increasing CPU +* clock frequency. It can optionally be called after lowering CPU clock +* frequency in order to improve CPU performance. +* +* Parameters: +* uint8 freq: +* Frequency of operation in Megahertz. +* +* Return: +* None +* +*******************************************************************************/ +void CyFlash_SetWaitCycles(uint8 freq) +{ + uint8 interruptState; + + /* Save current global interrupt enable and disable it */ + interruptState = CyEnterCriticalSection(); + + /*************************************************************************** + * The number of clock cycles the cache will wait before it samples data + * coming back from Flash must be equal or greater to to the CPU frequency + * outlined in clock cycles. + ***************************************************************************/ + + #if (CY_PSOC3) + + if (freq <= 22u) + { + *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | + ((uint8)(CY_FLASH_LESSER_OR_EQUAL_22MHz << CY_FLASH_CYCLES_MASK_SHIFT))); + } + else if (freq <= 44u) + { + *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | + ((uint8)(CY_FLASH_LESSER_OR_EQUAL_44MHz << CY_FLASH_CYCLES_MASK_SHIFT))); + } + else + { + *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | + ((uint8)(CY_FLASH_GREATER_44MHz << CY_FLASH_CYCLES_MASK_SHIFT))); + } + + #endif /* (CY_PSOC3) */ + + + #if (CY_PSOC5) + + if (freq <= 16u) + { + *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | + ((uint8)(CY_FLASH_LESSER_OR_EQUAL_16MHz << CY_FLASH_CYCLES_MASK_SHIFT))); + } + else if (freq <= 33u) + { + *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | + ((uint8)(CY_FLASH_LESSER_OR_EQUAL_33MHz << CY_FLASH_CYCLES_MASK_SHIFT))); + } + else if (freq <= 50u) + { + *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | + ((uint8)(CY_FLASH_LESSER_OR_EQUAL_50MHz << CY_FLASH_CYCLES_MASK_SHIFT))); + } + else + { + *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | + ((uint8)(CY_FLASH_GREATER_51MHz << CY_FLASH_CYCLES_MASK_SHIFT))); + } + + #endif /* (CY_PSOC5) */ + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyEEPROM_Start +******************************************************************************** +* +* Summary: +* Enable the EEPROM. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyEEPROM_Start(void) +{ + /* Active Power Mode */ + *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK; + + /* Standby Power Mode */ + *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK; +} + + +/******************************************************************************* +* Function Name: CyEEPROM_Stop +******************************************************************************** +* +* Summary: +* Disable the EEPROM. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyEEPROM_Stop (void) +{ + /* Active Power Mode */ + *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK)); + + /* Standby Power Mode */ + *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK)); +} + + +/******************************************************************************* +* Function Name: CyEEPROM_ReadReserve +******************************************************************************** +* +* Summary: +* Request access to the EEPROM for reading and wait until access is available. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyEEPROM_ReadReserve(void) +{ + /* Make a request for PHUB to have access */ + *CY_FLASH_EE_SCR_PTR |= CY_FLASH_EE_SCR_AHB_EE_REQ; + + while (0u == (*CY_FLASH_EE_SCR_PTR & CY_FLASH_EE_SCR_AHB_EE_ACK)) + { + /* Wait for acknowledgement from PHUB */ + } +} + + +/******************************************************************************* +* Function Name: CyEEPROM_ReadRelease +******************************************************************************** +* +* Summary: +* Release the read reservation of the EEPROM. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyEEPROM_ReadRelease(void) +{ + *CY_FLASH_EE_SCR_PTR |= 0x00u; +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h new file mode 100644 index 00000000..002b2ebf --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h @@ -0,0 +1,239 @@ +/******************************************************************************* +* File Name: CyFlash.h +* Version 4.0 +* +* Description: +* Provides the function definitions for the FLASH/EEPROM. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYFLASH_H) +#define CY_BOOT_CYFLASH_H + +#include "cydevice_trm.h" +#include "cytypes.h" +#include "CyLib.h" +#include "CySpc.h" + +#define CY_FLASH_DIE_TEMP_DATA_SIZE (2u) /* Die temperature data size */ + +extern uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE]; + + +/*************************************** +* API Constants +***************************************/ + +#define CY_FLASH_BASE (CYDEV_FLASH_BASE) +#define CY_FLASH_SIZE (CYDEV_FLS_SIZE) +#define CY_FLASH_SIZEOF_ARRAY (CYDEV_FLS_SECTOR_SIZE) +#define CY_FLASH_SIZEOF_ROW (CYDEV_FLS_ROW_SIZE) +#define CY_FLASH_SIZEOF_ECC_ROW (CYDEV_ECC_ROW_SIZE) +#define CY_FLASH_NUMBER_ROWS (CYDEV_FLS_SIZE / CYDEV_FLS_ROW_SIZE) +#define CY_FLASH_NUMBER_ARRAYS (CYDEV_FLS_SIZE / CYDEV_FLS_SECTOR_SIZE) + +#define CY_EEPROM_BASE (CYDEV_EE_BASE) +#define CY_EEPROM_SIZE (CYDEV_EE_SIZE) +#define CY_EEPROM_SIZEOF_ARRAY (CYDEV_EEPROM_SECTOR_SIZE) +#define CY_EEPROM_SIZEOF_ROW (CYDEV_EEPROM_ROW_SIZE) +#define CY_EEPROM_NUMBER_ROWS (EEPROM_SIZE / CYDEV_EEPROM_ROW_SIZE) +#define CY_EEPROM_NUMBER_ARRAYS (CYDEV_EE_SIZE / CY_EEPROM_SIZEOF_ARRAY) + + +#if !defined(CYDEV_FLS_BASE) + #define CYDEV_FLS_BASE CYDEV_FLASH_BASE +#endif /* !defined(CYDEV_FLS_BASE) */ + + +/*************************************** +* Function Prototypes +***************************************/ + +/* Flash Functions */ +void CyFlash_Start(void); +void CyFlash_Stop(void); +cystatus CySetTemp(void); +cystatus CySetFlashEEBuffer(uint8 * buffer); +cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8 * rowData, uint16 rowSize) \ + ; +cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData); + +#if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) + cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC) \ + ; +#endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */ + +void CyFlash_SetWaitCycles(uint8 freq) ; + +/* EEPROM Functions */ +void CyEEPROM_Start(void) ; +void CyEEPROM_Stop(void) ; + +void CyEEPROM_ReadReserve(void) ; +void CyEEPROM_ReadRelease(void) ; + + +/*************************************** +* Registers +***************************************/ +/* Active Power Mode Configuration Register 12 */ +#define CY_FLASH_PM_ACT_EEFLASH_REG (* (reg8 *) CYREG_PM_ACT_CFG12) +#define CY_FLASH_PM_ACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_ACT_CFG12) + +/* Alternate Active Power Mode Configuration Register 12 */ +#define CY_FLASH_PM_ALTACT_EEFLASH_REG (* (reg8 *) CYREG_PM_STBY_CFG12) +#define CY_FLASH_PM_ALTACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_STBY_CFG12) + + +/* Cache Control Register */ +#if (CY_PSOC3) + + #define CY_FLASH_CONTROL_REG (* (reg8 *) CYREG_CACHE_CR ) + #define CY_FLASH_CONTROL_PTR ( (reg8 *) CYREG_CACHE_CR ) + +#else + + #define CY_FLASH_CONTROL_REG (* (reg8 *) CYREG_CACHE_CC_CTL ) + #define CY_FLASH_CONTROL_PTR ( (reg8 *) CYREG_CACHE_CC_CTL ) + +#endif /* (CY_PSOC3) */ + + +/* EEPROM Status & Control Register */ +#define CY_FLASH_EE_SCR_REG (* (reg8 *) CYREG_SPC_EE_SCR) +#define CY_FLASH_EE_SCR_PTR ( (reg8 *) CYREG_SPC_EE_SCR) + + + +/*************************************** +* Register Constants +***************************************/ + +/* Power Mode Masks */ +#define CY_FLASH_PM_EE_MASK (0x10u) +#define CY_FLASH_PM_FLASH_MASK (0x01u) + +/* Frequency Constants */ +#if (CY_PSOC3) + + #define CY_FLASH_LESSER_OR_EQUAL_22MHz (0x01u) + #define CY_FLASH_LESSER_OR_EQUAL_44MHz (0x02u) + #define CY_FLASH_GREATER_44MHz (0x03u) + +#endif /* (CY_PSOC3) */ + +#if (CY_PSOC5) + + #define CY_FLASH_LESSER_OR_EQUAL_16MHz (0x01u) + #define CY_FLASH_LESSER_OR_EQUAL_33MHz (0x02u) + #define CY_FLASH_LESSER_OR_EQUAL_50MHz (0x03u) + #define CY_FLASH_GREATER_51MHz (0x00u) + +#endif /* (CY_PSOC5) */ + +#define CY_FLASH_CYCLES_MASK_SHIFT (0x06u) +#define CY_FLASH_CYCLES_MASK ((uint8)(0x03u << (CY_FLASH_CYCLES_MASK_SHIFT))) +#define CY_FLASH_EE_STARTUP_DELAY (5u) + +#define CY_FLASH_EE_SCR_AHB_EE_REQ (0x01u) +#define CY_FLASH_EE_SCR_AHB_EE_ACK (0x02u) + + + +/* Default values for getting temperature. */ + +#define CY_TEMP_NUMBER_OF_SAMPLES (0x1u) +#define CY_TEMP_TIMER_PERIOD (0xFFFu) +#define CY_TEMP_CLK_DIV_SELECT (0x4u) +#define CY_TEMP_NUM_SAMPLES (1 << (CY_TEMP_NUMBER_OF_SAMPLES)) +#define CY_SPC_CLK_PERIOD (120u) /* nS */ +#define CY_SYS_ns_PER_TICK (1000u) +#define CY_FRM_EXEC_TIME (1000u) /* nS */ + +#define CY_GET_TEMP_TIME ((1 << (CY_TEMP_NUM_SAMPLES + 1)) * \ + (CY_SPC_CLK_PERIOD * CY_TEMP_CLK_DIV_SELECT) * \ + CY_TEMP_TIMER_PERIOD + CY_FRM_EXEC_TIME) + +#define CY_TEMP_MAX_WAIT ((CY_GET_TEMP_TIME) / CY_SYS_ns_PER_TICK) /* In system ticks. */ + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from cy_boot 3.0 +*******************************************************************************/ +#define FLASH_SIZE (CY_FLASH_SIZE) +#define FLASH_SIZEOF_SECTOR (CY_FLASH_SIZEOF_ARRAY) +#define FLASH_NUMBER_ROWS (CY_FLASH_NUMBER_ROWS) +#define FLASH_NUMBER_SECTORS (CY_FLASH_NUMBER_ARRAYS) +#define EEPROM_SIZE (CY_EEPROM_SIZE) +#define EEPROM_SIZEOF_SECTOR (CY_EEPROM_SIZEOF_ARRAY) +#define EEPROM_NUMBER_ROWS (CY_EEPROM_NUMBER_ROWS) +#define EEPROM_NUMBER_SECTORS (CY_EEPROM_NUMBER_ARRAYS) +#define CY_EEPROM_NUMBER_SECTORS (CY_EEPROM_NUMBER_ARRAYS) +#define CY_EEPROM_SIZEOF_SECTOR (CY_EEPROM_SIZEOF_ARRAY) + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from cy_boot 3.30 +*******************************************************************************/ +#define FLASH_CYCLES_PTR (CY_FLASH_CONTROL_PTR) + +#define TEMP_NUMBER_OF_SAMPLES (CY_TEMP_NUMBER_OF_SAMPLES) +#define TEMP_TIMER_PERIOD (CY_TEMP_TIMER_PERIOD) +#define TEMP_CLK_DIV_SELECT (CY_TEMP_CLK_DIV_SELECT) +#define NUM_SAMPLES (CY_TEMP_NUM_SAMPLES) +#define SPC_CLK_PERIOD (CY_SPC_CLK_PERIOD) +#define FRM_EXEC_TIME (CY_FRM_EXEC_TIME) +#define GET_TEMP_TIME (CY_GET_TEMP_TIME) +#define TEMP_MAX_WAIT (CY_TEMP_MAX_WAIT) + +#define ECC_ADDR (0x80u) + + +#define PM_ACT_EE_PTR (CY_FLASH_PM_ACT_EEFLASH_PTR) +#define PM_ACT_FLASH_PTR (CY_FLASH_PM_ACT_EEFLASH_PTR) + +#define PM_STBY_EE_PTR (CY_FLASH_PM_ALTACT_EEFLASH_PTR) +#define PM_STBY_FLASH_PTR (CY_FLASH_PM_ALTACT_EEFLASH_PTR) + +#define PM_EE_MASK (CY_FLASH_PM_EE_MASK) +#define PM_FLASH_MASK (CY_FLASH_PM_FLASH_MASK) + +#define FLASH_CYCLES_MASK_SHIFT (CY_FLASH_CYCLES_MASK_SHIFT) +#define FLASH_CYCLES_MASK (CY_FLASH_CYCLES_MASK) + + +#if (CY_PSOC3) + + #define LESSER_OR_EQUAL_22MHz (CY_FLASH_LESSER_OR_EQUAL_22MHz) + #define LESSER_OR_EQUAL_44MHz (CY_FLASH_LESSER_OR_EQUAL_44MHz) + #define GREATER_44MHz (CY_FLASH_GREATER_44MHz) + +#endif /* (CY_PSOC3) */ + +#if (CY_PSOC5) + + #define LESSER_OR_EQUAL_16MHz (CY_FLASH_LESSER_OR_EQUAL_16MHz) + #define LESSER_OR_EQUAL_33MHz (CY_FLASH_LESSER_OR_EQUAL_33MHz) + #define LESSER_OR_EQUAL_50MHz (CY_FLASH_LESSER_OR_EQUAL_50MHz) + #define LESSER_OR_EQUAL_67MHz (CY_FLASH_LESSER_OR_EQUAL_67MHz) + #define GREATER_67MHz (CY_FLASH_GREATER_67MHz) + #define GREATER_51MHz (CY_FLASH_GREATER_51MHz) + +#endif /* (CY_PSOC5) */ + +#define AHUB_EE_REQ_ACK_PTR (CY_FLASH_EE_SCR_PTR) + + +#endif /* (CY_BOOT_CYFLASH_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyLib.c b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyLib.c new file mode 100644 index 00000000..5278bdf1 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyLib.c @@ -0,0 +1,2710 @@ +/******************************************************************************* +* File Name: CyLib.c +* Version 4.0 +* +* Description: +* Provides system API for the clocking, interrupts and watchdog timer. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "CyLib.h" + + +/******************************************************************************* +* The CyResetStatus variable is used to obtain value of RESET_SR0 register after +* a device reset. It is set from initialize_psoc() at the early initialization +* stage. In case of IAR EW IDE, initialize_psoc() is executed before the data +* sections are initialized. To avoid zeroing, CyResetStatus should be placed +* to the .noinit section. +*******************************************************************************/ +CY_NOINIT uint8 CYXDATA CyResetStatus; + + +/* Variable Vdda */ +#if(CYDEV_VARIABLE_VDDA == 1) + + uint8 CyScPumpEnabled = (uint8)(CYDEV_VDDA_MV < 2700); + +#endif /* (CYDEV_VARIABLE_VDDA == 1) */ + + +/* Do not use these definitions directly in your application */ +uint32 cydelay_freq_hz = BCLK__BUS_CLK__HZ; +uint32 cydelay_freq_khz = (BCLK__BUS_CLK__HZ + 999u) / 1000u; +uint8 cydelay_freq_mhz = (uint8)((BCLK__BUS_CLK__HZ + 999999u) / 1000000u); +uint32 cydelay_32k_ms = 32768u * ((BCLK__BUS_CLK__HZ + 999u) / 1000u); + + +/* Function Prototypes */ +static uint8 CyUSB_PowerOnCheck(void) ; +static void CyIMO_SetTrimValue(uint8 freq) ; +static void CyBusClk_Internal_SetDivider(uint16 divider); + + +/******************************************************************************* +* Function Name: CyPLL_OUT_Start +******************************************************************************** +* +* Summary: +* Enables the PLL. Optionally waits for it to become stable. +* Waits at least 250 us or until it is detected that the PLL is stable. +* +* Parameters: +* wait: +* 0: Return immediately after configuration +* 1: Wait for PLL lock or timeout. +* +* Return: +* Status +* CYRET_SUCCESS - Completed successfully +* CYRET_TIMEOUT - Timeout occurred without detecting a stable clock. +* If the input source of the clock is jittery, then the lock indication +* may not occur. However, after the timeout has expired the generated PLL +* clock can still be used. +* +* Side Effects: +* If wait is enabled: This function wses the Fast Time Wheel to time the wait. +* Any other use of the Fast Time Wheel will be stopped during the period of +* this function and then restored. This function also uses the 100 KHz ILO. +* If not enabled, this function will enable the 100 KHz ILO for the period of +* this function. +* +* No changes to the setup of the ILO, Fast Time Wheel, Central Time Wheel or +* Once Per Second interrupt may be made by interrupt routines during the period +* of this function execution. The current operation of the ILO, Central Time +* Wheel and Once Per Second interrupt are maintained during the operation of +* this function provided the reading of the Power Manager Interrupt Status +* Register is only done using the CyPmReadStatus() function. +* +*******************************************************************************/ +cystatus CyPLL_OUT_Start(uint8 wait) +{ + cystatus status = CYRET_SUCCESS; + + uint8 iloEnableState; + uint8 pmTwCfg0State; + uint8 pmTwCfg2State; + + + /* Enables the PLL circuit */ + CY_CLK_PLL_CFG0_REG |= CY_CLK_PLL_ENABLE; + + if(wait != 0u) + { + /* Save 100 KHz ILO, FTW interval, enable and interrupt enable */ + iloEnableState = CY_LIB_SLOWCLK_ILO_CR0_REG & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ; + pmTwCfg0State = CY_LIB_PM_TW_CFG0_REG; + pmTwCfg2State = CY_LIB_PM_TW_CFG2_REG; + + CyPmFtwSetInterval(CY_CLK_PLL_FTW_INTERVAL); + + status = CYRET_TIMEOUT; + + while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT))) + { + /* Wait for the interrupt status */ + if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS)) + { + if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS)) + { + status = CYRET_SUCCESS; + break; + } + } + } + + /* Restore 100 KHz ILO, FTW interval, enable and interrupt enable */ + if(0u == iloEnableState) + { + CyILO_Stop100K(); + } + + CY_LIB_PM_TW_CFG0_REG = pmTwCfg0State; + CY_LIB_PM_TW_CFG2_REG = pmTwCfg2State; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyPLL_OUT_Stop +******************************************************************************** +* +* Summary: +* Disables the PLL. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyPLL_OUT_Stop(void) +{ + CY_CLK_PLL_CFG0_REG &= ((uint8)(~CY_CLK_PLL_ENABLE)); +} + + +/******************************************************************************* +* Function Name: CyPLL_OUT_SetPQ +******************************************************************************** +* +* Summary: +* Sets the P and Q dividers and the charge pump current. +* The Frequency Out will be P/Q * Frequency In. +* The PLL must be disabled before calling this function. +* +* Parameters: +* uint8 pDiv: +* Valid range [8 - 255]. +* +* uint8 qDiv: +* Valid range [1 - 16]. Input Frequency / Q must be in range of 1 to 3 MHz. + +* uint8 current: +* Valid range [1 - 7]. Charge pump current in uA. Refer to the device TRM and +* datasheet for more information. +* +* Return: +* None +* +* Side Effects: +* If as result of this function execution the CPU clock frequency is increased +* then the number of clock cycles the cache will wait before it samples data +* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() +* with appropriate parameter. It can be optionally called if CPU clock +* frequency is lowered in order to improve CPU performance. +* See CyFlash_SetWaitCycles() description for more information. +* +*******************************************************************************/ +void CyPLL_OUT_SetPQ(uint8 pDiv, uint8 qDiv, uint8 current) +{ + /* Halt CPU in debug mode if PLL is enabled */ + CYASSERT(0u == (CY_CLK_PLL_CFG0_REG & CY_CLK_PLL_ENABLE)); + + if((pDiv >= CY_CLK_PLL_MIN_P_VALUE ) && + (qDiv <= CY_CLK_PLL_MAX_Q_VALUE ) && (qDiv >= CY_CLK_PLL_MIN_Q_VALUE ) && + (current >= CY_CLK_PLL_MIN_CUR_VALUE) && (current <= CY_CLK_PLL_MAX_CUR_VALUE)) + { + /* Set new values */ + CY_CLK_PLL_P_REG = pDiv; + CY_CLK_PLL_Q_REG = ((uint8)(qDiv - 1u)); + CY_CLK_PLL_CFG1_REG = (CY_CLK_PLL_CFG1_REG & CY_CLK_PLL_CURRENT_MASK) | + ((uint8)(((uint8)(current - 1u)) << CY_CLK_PLL_CURRENT_POSITION)); + } + else + { + /*********************************************************************** + * Halt CPU in debug mode if: + * - P divider is less than required + * - Q divider is out of range + * - pump current is out of range + ***********************************************************************/ + CYASSERT(0u != 0u); + } + +} + + +/******************************************************************************* +* Function Name: CyPLL_OUT_SetSource +******************************************************************************** +* +* Summary: +* Sets the input clock source to the PLL. The PLL must be disabled before +* calling this function. +* +* Parameters: +* source: One of the three available PLL clock sources +* CY_PLL_SOURCE_IMO : IMO +* CY_PLL_SOURCE_XTAL : MHz Crystal +* CY_PLL_SOURCE_DSI : DSI +* +* Return: +* None +* +* Side Effects: +* If as result of this function execution the CPU clock frequency is increased +* then the number of clock cycles the cache will wait before it samples data +* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() +* with appropriate parameter. It can be optionally called if CPU clock +* frequency is lowered in order to improve CPU performance. +* See CyFlash_SetWaitCycles() description for more information. +* +*******************************************************************************/ +void CyPLL_OUT_SetSource(uint8 source) +{ + /* Halt CPU in debug mode if PLL is enabled */ + CYASSERT(0u == (CY_CLK_PLL_CFG0_REG & CY_CLK_PLL_ENABLE)); + + switch(source) + { + case CY_PLL_SOURCE_IMO: + case CY_PLL_SOURCE_XTAL: + case CY_PLL_SOURCE_DSI: + CY_LIB_CLKDIST_CR_REG = ((CY_LIB_CLKDIST_CR_REG & CY_LIB_CLKDIST_CR_PLL_SCR_MASK) | source); + break; + + default: + CYASSERT(0u != 0u); + break; + } +} + + +/******************************************************************************* +* Function Name: CyIMO_Start +******************************************************************************** +* +* Summary: +* Enables the IMO. Optionally waits at least 6 us for it to settle. +* +* Parameters: +* uint8 wait: +* 0: Return immediately after configuration +* 1: Wait for at least 6 us for the IMO to settle. +* +* Return: +* None +* +* Side Effects: +* If wait is enabled: This function wses the Fast Time Wheel to time the wait. +* Any other use of the Fast Time Wheel will be stopped during the period of +* this function and then restored. This function also uses the 100 KHz ILO. +* If not enabled, this function will enable the 100 KHz ILO for the period of +* this function. +* +* No changes to the setup of the ILO, Fast Time Wheel, Central Time Wheel or +* Once Per Second interrupt may be made by interrupt routines during the period +* of this function execution. The current operation of the ILO, Central Time +* Wheel and Once Per Second interrupt are maintained during the operation of +* this function provided the reading of the Power Manager Interrupt Status +* Register is only done using the CyPmReadStatus() function. +* +*******************************************************************************/ +void CyIMO_Start(uint8 wait) +{ + uint8 pmFtwCfg2Reg; + uint8 pmFtwCfg0Reg; + uint8 ilo100KhzEnable; + + + CY_LIB_PM_ACT_CFG0_REG |= CY_LIB_PM_ACT_CFG0_IMO_EN; + CY_LIB_PM_STBY_CFG0_REG |= CY_LIB_PM_STBY_CFG0_IMO_EN; + + if(0u != wait) + { + /* Need to turn on the 100KHz ILO if it happens to not already be running.*/ + ilo100KhzEnable = CY_LIB_SLOWCLK_ILO_CR0_REG & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ; + pmFtwCfg0Reg = CY_LIB_PM_TW_CFG0_REG; + pmFtwCfg2Reg = CY_LIB_PM_TW_CFG2_REG; + + CyPmFtwSetInterval(CY_LIB_CLK_IMO_FTW_TIMEOUT); + + while (0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT))) + { + /* Wait for the interrupt status */ + } + + if(0u == ilo100KhzEnable) + { + CyILO_Stop100K(); + } + + CY_LIB_PM_TW_CFG0_REG = pmFtwCfg0Reg; + CY_LIB_PM_TW_CFG2_REG = pmFtwCfg2Reg; + } +} + + +/******************************************************************************* +* Function Name: CyIMO_Stop +******************************************************************************** +* +* Summary: +* Disables the IMO. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyIMO_Stop(void) +{ + CY_LIB_PM_ACT_CFG0_REG &= ((uint8) (~CY_LIB_PM_ACT_CFG0_IMO_EN)); + CY_LIB_PM_STBY_CFG0_REG &= ((uint8) (~CY_LIB_PM_STBY_CFG0_IMO_EN)); +} + + +/******************************************************************************* +* Function Name: CyUSB_PowerOnCheck +******************************************************************************** +* +* Summary: +* Returns the USB power status value. A private function to cy_boot. +* +* Parameters: +* None +* +* Return: +* uint8: one if the USB is enabled, 0 if not enabled. +* +*******************************************************************************/ +static uint8 CyUSB_PowerOnCheck(void) +{ + uint8 poweredOn = 0u; + + /* Check whether device is in Active or AltActiv and if USB is powered on */ + if((((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ACTIVE ) && + (0u != (CY_LIB_PM_ACT_CFG5_REG & CY_ACT_USB_ENABLED ))) || + (((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ALT_ACT) && + (0u != (CY_LIB_PM_STBY_CFG5_REG & CY_ALT_ACT_USB_ENABLED)))) + { + poweredOn = 1u; + } + + return (poweredOn); +} + + +/******************************************************************************* +* Function Name: CyIMO_SetTrimValue +******************************************************************************** +* +* Summary: +* Sets the IMO factory trim values. +* +* Parameters: +* uint8 freq - frequency for which trims must be set +* +* Return: +* None +* +*******************************************************************************/ +static void CyIMO_SetTrimValue(uint8 freq) +{ + uint8 usbPowerOn = CyUSB_PowerOnCheck(); + + /* If USB is powered */ + if(usbPowerOn == 1u) + { + /* Unlock USB write */ + CY_LIB_USB_CR1_REG &= ((uint8)(~CY_LIB_USB_CLK_EN)); + } + switch(freq) + { + case CY_IMO_FREQ_3MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_3MHZ_PTR); + break; + + case CY_IMO_FREQ_6MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_6MHZ_PTR); + break; + + case CY_IMO_FREQ_12MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_12MHZ_PTR); + break; + + case CY_IMO_FREQ_24MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_24MHZ_PTR); + break; + + case CY_IMO_FREQ_48MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_TR1_PTR); + break; + + case CY_IMO_FREQ_62MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_67MHZ_PTR); + break; + +#if(CY_PSOC5) + case CY_IMO_FREQ_74MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_80MHZ_PTR); + break; +#endif /* (CY_PSOC5) */ + + case CY_IMO_FREQ_USB: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_USB_PTR); + + /* If USB is powered */ + if(usbPowerOn == 1u) + { + /* Lock the USB Oscillator */ + CY_LIB_USB_CR1_REG |= CY_LIB_USB_CLK_EN; + } + break; + + default: + CYASSERT(0u != 0u); + break; + } + +} + + +/******************************************************************************* +* Function Name: CyIMO_SetFreq +******************************************************************************** +* +* Summary: +* Sets the frequency of the IMO. Changes may be made while the IMO is running. +* +* Parameters: +* freq: Frequency of IMO operation +* CY_IMO_FREQ_3MHZ to set 3 MHz +* CY_IMO_FREQ_6MHZ to set 6 MHz +* CY_IMO_FREQ_12MHZ to set 12 MHz +* CY_IMO_FREQ_24MHZ to set 24 MHz +* CY_IMO_FREQ_48MHZ to set 48 MHz +* CY_IMO_FREQ_62MHZ to set 62.6 MHz +* CY_IMO_FREQ_74MHZ to set 74.7 MHz (not applicable for PSoC 3) +* CY_IMO_FREQ_USB to set 24 MHz (Trimmed for USB operation) +* +* Return: +* None +* +* Side Effects: +* If as result of this function execution the CPU clock frequency is increased +* then the number of clock cycles the cache will wait before it samples data +* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() +* with appropriate parameter. It can be optionally called if CPU clock +* frequency is lowered in order to improve CPU performance. +* See CyFlash_SetWaitCycles() description for more information. +* +* When the USB setting is chosen, the USB clock locking circuit is enabled. +* Otherwise this circuit is disabled. The USB block must be powered before +* selecting the USB setting. +* +*******************************************************************************/ +void CyIMO_SetFreq(uint8 freq) +{ + uint8 currentFreq; + uint8 nextFreq; + + /*************************************************************************** + * When changing the IMO frequency the Trim values must also be set + * accordingly.This requires reading the current frequency. If the new + * frequency is faster, then set the new trim and then change the frequency, + * otherwise change the frequency and then set the new trim values. + ***************************************************************************/ + + currentFreq = CY_LIB_FASTCLK_IMO_CR_REG & ((uint8)(~CY_LIB_FASTCLK_IMO_CR_RANGE_MASK)); + + /* Check if the requested frequency is USB. */ + nextFreq = (freq == CY_IMO_FREQ_USB) ? CY_IMO_FREQ_24MHZ : freq; + + switch (currentFreq) + { + case 0u: + currentFreq = CY_IMO_FREQ_12MHZ; + break; + + case 1u: + currentFreq = CY_IMO_FREQ_6MHZ; + break; + + case 2u: + currentFreq = CY_IMO_FREQ_24MHZ; + break; + + case 3u: + currentFreq = CY_IMO_FREQ_3MHZ; + break; + + case 4u: + currentFreq = CY_IMO_FREQ_48MHZ; + break; + + case 5u: + currentFreq = CY_IMO_FREQ_62MHZ; + break; + +#if(CY_PSOC5) + case 6u: + currentFreq = CY_IMO_FREQ_74MHZ; + break; +#endif /* (CY_PSOC5) */ + + default: + CYASSERT(0u != 0u); + break; + } + + if (nextFreq >= currentFreq) + { + /* Set the new trim first */ + CyIMO_SetTrimValue(freq); + } + + /* Set the usbclk_on bit when using CY_IMO_FREQ_USB, if not clear it */ + switch(freq) + { + case CY_IMO_FREQ_3MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_3MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; + + case CY_IMO_FREQ_6MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_6MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; + + case CY_IMO_FREQ_12MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_12MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; + + case CY_IMO_FREQ_24MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_24MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; + + case CY_IMO_FREQ_48MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_48MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; + + case CY_IMO_FREQ_62MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_62MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; + +#if(CY_PSOC5) + case CY_IMO_FREQ_74MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_74MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; +#endif /* (CY_PSOC5) */ + + case CY_IMO_FREQ_USB: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_24MHZ_VALUE) | CY_LIB_IMO_USBCLK_ON_SET; + break; + + default: + CYASSERT(0u != 0u); + break; + } + + /* Turn on the IMO Doubler, if switching to CY_IMO_FREQ_USB */ + if (freq == CY_IMO_FREQ_USB) + { + CyIMO_EnableDoubler(); + } + else + { + CyIMO_DisableDoubler(); + } + + if (nextFreq < currentFreq) + { + /* Set the new trim after setting the frequency */ + CyIMO_SetTrimValue(freq); + } +} + + +/******************************************************************************* +* Function Name: CyIMO_SetSource +******************************************************************************** +* +* Summary: +* Sets the source of the clock output from the IMO block. +* +* The output from the IMO is by default the IMO itself. Optionally the MHz +* Crystal or a DSI input can be the source of the IMO output instead. +* +* Parameters: +* source: CY_IMO_SOURCE_DSI to set the DSI as source. +* CY_IMO_SOURCE_XTAL to set the MHz as source. +* CY_IMO_SOURCE_IMO to set the IMO itself. +* +* Return: +* None +* +* Side Effects: +* If as result of this function execution the CPU clock frequency is increased +* then the number of clock cycles the cache will wait before it samples data +* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() +* with appropriate parameter. It can be optionally called if CPU clock +* frequency is lowered in order to improve CPU performance. +* See CyFlash_SetWaitCycles() description for more information. +* +*******************************************************************************/ +void CyIMO_SetSource(uint8 source) +{ + switch(source) + { + case CY_IMO_SOURCE_DSI: + CY_LIB_CLKDIST_CR_REG &= ((uint8)(~CY_LIB_CLKDIST_CR_IMO2X)); + CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_IMO; + break; + + case CY_IMO_SOURCE_XTAL: + CY_LIB_CLKDIST_CR_REG |= CY_LIB_CLKDIST_CR_IMO2X; + CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_IMO; + break; + + case CY_IMO_SOURCE_IMO: + CY_LIB_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_LIB_FASTCLK_IMO_IMO)); + break; + + default: + /* Incorrect source value */ + CYASSERT(0u != 0u); + break; + } +} + + +/******************************************************************************* +* Function Name: CyIMO_EnableDoubler +******************************************************************************** +* +* Summary: +* Enables the IMO doubler. The 2x frequency clock is used to convert a 24 MHz +* input to a 48 MHz output for use by the USB block. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyIMO_EnableDoubler(void) +{ + /* Set the FASTCLK_IMO_CR_PTR regigster's 4th bit */ + CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_DOUBLER; +} + + +/******************************************************************************* +* Function Name: CyIMO_DisableDoubler +******************************************************************************** +* +* Summary: +* Disables the IMO doubler. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyIMO_DisableDoubler(void) +{ + CY_LIB_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_LIB_FASTCLK_IMO_DOUBLER)); +} + + +/******************************************************************************* +* Function Name: CyMasterClk_SetSource +******************************************************************************** +* +* Summary: +* Sets the source of the master clock. +* +* Parameters: +* source: One of the four available Master clock sources. +* CY_MASTER_SOURCE_IMO +* CY_MASTER_SOURCE_PLL +* CY_MASTER_SOURCE_XTAL +* CY_MASTER_SOURCE_DSI +* +* Return: +* None +* +* Side Effects: +* The current source and the new source must both be running and stable before +* calling this function. +* +* If as result of this function execution the CPU clock frequency is increased +* then the number of clock cycles the cache will wait before it samples data +* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() +* with appropriate parameter. It can be optionally called if CPU clock +* frequency is lowered in order to improve CPU performance. +* See CyFlash_SetWaitCycles() description for more information. +* +*******************************************************************************/ +void CyMasterClk_SetSource(uint8 source) +{ + CY_LIB_CLKDIST_MSTR1_REG = (CY_LIB_CLKDIST_MSTR1_REG & MASTER_CLK_SRC_CLEAR) | + (source & ((uint8)(~MASTER_CLK_SRC_CLEAR))); +} + + +/******************************************************************************* +* Function Name: CyMasterClk_SetDivider +******************************************************************************** +* +* Summary: +* Sets the divider value used to generate Master Clock. +* +* Parameters: +* uint8 divider: +* Valid range [0-255]. The clock will be divided by this value + 1. +* For example to divide by 2 this parameter should be set to 1. +* +* Return: +* None +* +* Side Effects: +* If as result of this function execution the CPU clock frequency is increased +* then the number of clock cycles the cache will wait before it samples data +* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() +* with appropriate parameter. It can be optionally called if CPU clock +* frequency is lowered in order to improve CPU performance. +* See CyFlash_SetWaitCycles() description for more information. +* +* When changing the Master or Bus clock divider value from div-by-n to div-by-1 +* the first clock cycle output after the div-by-1 can be up to 4 ns shorter +* than the final/expected div-by-1 period. +* +*******************************************************************************/ +void CyMasterClk_SetDivider(uint8 divider) +{ + CY_LIB_CLKDIST_MSTR0_REG = divider; +} + + +/******************************************************************************* +* Function Name: CyBusClk_Internal_SetDivider +******************************************************************************** +* +* Summary: +* Function used by CyBusClk_SetDivider(). For internal use only. +* +* Parameters: +* divider: Valid range [0-65535]. +* The clock will be divided by this value + 1. +* For example to divide by 2 this parameter should be set to 1. +* +* Return: +* None +* +*******************************************************************************/ +static void CyBusClk_Internal_SetDivider(uint16 divider) +{ + /* Mask bits to enable shadow loads */ + CY_LIB_CLKDIST_AMASK_REG &= CY_LIB_CLKDIST_AMASK_MASK; + CY_LIB_CLKDIST_DMASK_REG = CY_LIB_CLKDIST_DMASK_MASK; + + /* Enable mask bits to enable shadow loads */ + CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_MASK; + + /* Update Shadow Divider Value Register with the new divider */ + CY_LIB_CLKDIST_WRK_LSB_REG = LO8(divider); + CY_LIB_CLKDIST_WRK_MSB_REG = HI8(divider); + + + /*************************************************************************** + * Copy shadow value defined in Shadow Divider Value Register + * (CY_LIB_CLKDIST_WRK_LSB_REG and CY_LIB_CLKDIST_WRK_MSB_REG) to all + * dividers selected in Analog and Digital Clock Mask Registers + * (CY_LIB_CLKDIST_AMASK_REG and CY_LIB_CLKDIST_DMASK_REG). + ***************************************************************************/ + CY_LIB_CLKDIST_LD_REG |= CY_LIB_CLKDIST_LD_LOAD; +} + + +/******************************************************************************* +* Function Name: CyBusClk_SetDivider +******************************************************************************** +* +* Summary: +* Sets the divider value used to generate Bus Clock. +* +* Parameters: +* divider: Valid range [0-65535]. The clock will be divided by this value + 1. +* For example to divide by 2 this parameter should be set to 1. +* +* Return: +* None +* +* Side Effects: +* If as result of this function execution the CPU clock frequency is increased +* then the number of clock cycles the cache will wait before it samples data +* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() +* with appropriate parameter. It can be optionally called if CPU clock +* frequency is lowered in order to improve CPU performance. +* See CyFlash_SetWaitCycles() description for more information. +* +*******************************************************************************/ +void CyBusClk_SetDivider(uint16 divider) +{ + uint8 masterClkDiv; + uint16 busClkDiv; + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + /* Work around to set the bus clock divider value */ + busClkDiv = (uint16)((uint16)CY_LIB_CLKDIST_BCFG_MSB_REG << 8u); + busClkDiv |= CY_LIB_CLKDIST_BCFG_LSB_REG; + + if ((divider == 0u) || (busClkDiv == 0u)) + { + /* Save away the master clock divider value */ + masterClkDiv = CY_LIB_CLKDIST_MSTR0_REG; + + if (masterClkDiv < CY_LIB_CLKDIST_MASTERCLK_DIV) + { + /* Set master clock divider to 7 */ + CyMasterClk_SetDivider(CY_LIB_CLKDIST_MASTERCLK_DIV); + } + + if (divider == 0u) + { + /* Set the SSS bit and the divider register desired value */ + CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_SSS; + CyBusClk_Internal_SetDivider(divider); + } + else + { + CyBusClk_Internal_SetDivider(divider); + CY_LIB_CLKDIST_BCFG2_REG &= ((uint8)(~CY_LIB_CLKDIST_BCFG2_SSS)); + } + + /* Restore the master clock */ + CyMasterClk_SetDivider(masterClkDiv); + } + else + { + CyBusClk_Internal_SetDivider(divider); + } + + CyExitCriticalSection(interruptState); +} + + +#if(CY_PSOC3) + + /******************************************************************************* + * Function Name: CyCpuClk_SetDivider + ******************************************************************************** + * + * Summary: + * Sets the divider value used to generate the CPU Clock. Only applicable for + * PSoC 3 parts. + * + * Parameters: + * divider: Valid range [0-15]. The clock will be divided by this value + 1. + * For example to divide by 2 this parameter should be set to 1. + * + * Return: + * None + * + * Side Effects: + * If as result of this function execution the CPU clock frequency is increased + * then the number of clock cycles the cache will wait before it samples data + * coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() + * with appropriate parameter. It can be optionally called if CPU clock + * frequency is lowered in order to improve CPU performance. + * See CyFlash_SetWaitCycles() description for more information. + * + *******************************************************************************/ + void CyCpuClk_SetDivider(uint8 divider) + { + CY_LIB_CLKDIST_MSTR1_REG = (CY_LIB_CLKDIST_MSTR1_REG & CY_LIB_CLKDIST_MSTR1_DIV_MASK) | + ((uint8)(divider << CY_LIB_CLKDIST_DIV_POSITION)); + } + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Function Name: CyUsbClk_SetSource +******************************************************************************** +* +* Summary: +* Sets the source of the USB clock. +* +* Parameters: +* source: One of the four available USB clock sources +* CY_LIB_USB_CLK_IMO2X - IMO 2x +* CY_LIB_USB_CLK_IMO - IMO +* CY_LIB_USB_CLK_PLL - PLL +* CY_LIB_USB_CLK_DSI - DSI +* +* Return: +* None +* +*******************************************************************************/ +void CyUsbClk_SetSource(uint8 source) +{ + CY_LIB_CLKDIST_UCFG_REG = (CY_LIB_CLKDIST_UCFG_REG & ((uint8)(~CY_LIB_CLKDIST_UCFG_SRC_SEL_MASK))) | + (CY_LIB_CLKDIST_UCFG_SRC_SEL_MASK & source); +} + + +/******************************************************************************* +* Function Name: CyILO_Start1K +******************************************************************************** +* +* Summary: +* Enables the ILO 1 KHz oscillator. +* +* Note The ILO 1 KHz oscillator is always enabled by default, regardless of the +* selection in the Clock Editor. Therefore, this API is only needed if the +* oscillator was turned off manually. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyILO_Start1K(void) +{ + /* Set the bit 1 of ILO RS */ + CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ; +} + + +/******************************************************************************* +* Function Name: CyILO_Stop1K +******************************************************************************** +* +* Summary: +* Disables the ILO 1 KHz oscillator. +* +* Note The ILO 1 KHz oscillator must be enabled if Sleep or Hibernate low power +* mode APIs are expected to be used. For more information, refer to the Power +* Management section of this document. +* +* Parameters: +* None +* +* Return: +* None +* +* Side Effects: +* PSoC5: Stopping the ILO 1 kHz could break the active WDT functionality. +* +*******************************************************************************/ +void CyILO_Stop1K(void) +{ + /* Clear the bit 1 of ILO RS */ + CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ)); +} + + +/******************************************************************************* +* Function Name: CyILO_Start100K +******************************************************************************** +* +* Summary: +* Enables the ILO 100 KHz oscillator. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyILO_Start100K(void) +{ + CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ; +} + + +/******************************************************************************* +* Function Name: CyILO_Stop100K +******************************************************************************** +* +* Summary: +* Disables the ILO 100 KHz oscillator. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyILO_Stop100K(void) +{ + CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ)); +} + + +/******************************************************************************* +* Function Name: CyILO_Enable33K +******************************************************************************** +* +* Summary: +* Enables the ILO 33 KHz divider. +* +* Note that the 33 KHz clock is generated from the 100 KHz oscillator, +* so it must also be running in order to generate the 33 KHz output. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyILO_Enable33K(void) +{ + /* Set the bit 5 of ILO RS */ + CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ; +} + + +/******************************************************************************* +* Function Name: CyILO_Disable33K +******************************************************************************** +* +* Summary: +* Disables the ILO 33 KHz divider. +* +* Note that the 33 KHz clock is generated from the 100 KHz oscillator, but this +* API does not disable the 100 KHz clock. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyILO_Disable33K(void) +{ + CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ)); +} + + +/******************************************************************************* +* Function Name: CyILO_SetSource +******************************************************************************** +* +* Summary: +* Sets the source of the clock output from the ILO block. +* +* Parameters: +* source: One of the three available ILO output sources +* Value Define Source +* 0 CY_ILO_SOURCE_100K ILO 100 KHz +* 1 CY_ILO_SOURCE_33K ILO 33 KHz +* 2 CY_ILO_SOURCE_1K ILO 1 KHz +* +* Return: +* None +* +*******************************************************************************/ +void CyILO_SetSource(uint8 source) +{ + CY_LIB_CLKDIST_CR_REG = (CY_LIB_CLKDIST_CR_REG & CY_ILO_SOURCE_BITS_CLEAR) | + (((uint8) (source << 2u)) & ((uint8)(~CY_ILO_SOURCE_BITS_CLEAR))); +} + + +/******************************************************************************* +* Function Name: CyILO_SetPowerMode +******************************************************************************** +* +* Summary: +* Sets the power mode used by the ILO during power down. Allows for lower power +* down power usage resulting in a slower startup time. +* +* Parameters: +* uint8 mode +* CY_ILO_FAST_START - Faster start-up, internal bias left on when powered down +* CY_ILO_SLOW_START - Slower start-up, internal bias off when powered down +* +* Return: +* Prevous power mode state. +* +*******************************************************************************/ +uint8 CyILO_SetPowerMode(uint8 mode) +{ + uint8 state; + + /* Get current state. */ + state = CY_LIB_SLOWCLK_ILO_CR0_REG; + + /* Set the the oscillator power mode. */ + if(mode != CY_ILO_FAST_START) + { + CY_LIB_SLOWCLK_ILO_CR0_REG = (state | CY_ILO_CONTROL_PD_MODE); + } + else + { + CY_LIB_SLOWCLK_ILO_CR0_REG = (state & ((uint8)(~CY_ILO_CONTROL_PD_MODE))); + } + + /* Return the old mode. */ + return ((state & CY_ILO_CONTROL_PD_MODE) >> CY_ILO_CONTROL_PD_POSITION); +} + + +/******************************************************************************* +* Function Name: CyXTAL_32KHZ_Start +******************************************************************************** +* +* Summary: +* Enables the 32 KHz Crystal Oscillator. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyXTAL_32KHZ_Start(void) +{ + volatile uint16 i; + + CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT; + CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_STARTUP; + CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | + CY_CLK_XTAL32_CFG_LP_DEFAULT; + + #if(CY_PSOC3) + CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_PDBEN; + #endif /* (CY_PSOC3) */ + + /* Enable operation of the 32K Crystal Oscillator */ + CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_EN; + + for (i = 1000u; i > 0u; i--) + { + if(0u != (CyXTAL_32KHZ_ReadStatus() & CY_XTAL32K_ANA_STAT)) + { + /* Ready - switch to the hign power mode */ + (void) CyXTAL_32KHZ_SetPowerMode(0u); + + break; + } + CyDelayUs(1u); + } +} + + +/******************************************************************************* +* Function Name: CyXTAL_32KHZ_Stop +******************************************************************************** +* +* Summary: +* Disables the 32KHz Crystal Oscillator. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyXTAL_32KHZ_Stop(void) +{ + CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT; + CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_POWERDOWN; + CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | + CY_CLK_XTAL32_CFG_LP_DEFAULT; + CY_CLK_XTAL32_CR_REG &= ((uint8)(~(CY_CLK_XTAL32_CR_EN | CY_CLK_XTAL32_CR_LPM))); + + #if(CY_PSOC3) + CY_CLK_XTAL32_CR_REG &= ((uint8)(~CY_CLK_XTAL32_CR_PDBEN)); + #endif /* (CY_PSOC3) */ +} + + +/******************************************************************************* +* Function Name: CyXTAL_32KHZ_ReadStatus +******************************************************************************** +* +* Summary: +* Returns status of the 32 KHz oscillator. +* +* Parameters: +* None +* +* Return: +* Value Define Source +* 20 CY_XTAL32K_ANA_STAT Analog measurement +* 1: Stable +* 0: Not stable +* +*******************************************************************************/ +uint8 CyXTAL_32KHZ_ReadStatus(void) +{ + return(CY_CLK_XTAL32_CR_REG & CY_XTAL32K_ANA_STAT); +} + + +/******************************************************************************* +* Function Name: CyXTAL_32KHZ_SetPowerMode +******************************************************************************** +* +* Summary: +* Sets the power mode for the 32 KHz oscillator used during sleep mode. +* Allows for lower power during sleep when there are fewer sources of noise. +* During active mode the oscillator is always run in high power mode. +* +* Parameters: +* uint8 mode +* 0: High power mode +* 1: Low power mode during sleep +* +* Return: +* Previous power mode. +* +*******************************************************************************/ +uint8 CyXTAL_32KHZ_SetPowerMode(uint8 mode) +{ + uint8 state = (0u != (CY_CLK_XTAL32_CR_REG & CY_CLK_XTAL32_CR_LPM)) ? 1u : 0u; + + CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT; + + if(1u == mode) + { + /* Low power mode during Sleep */ + CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_LOW_POWER; + CyDelayUs(10u); + CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | + CY_CLK_XTAL32_CFG_LP_LOWPOWER; + CyDelayUs(20u); + CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_LPM; + } + else + { + /* High power mode */ + CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_HIGH_POWER; + CyDelayUs(10u); + CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | + CY_CLK_XTAL32_CFG_LP_DEFAULT; + CY_CLK_XTAL32_CR_REG &= ((uint8)(~CY_CLK_XTAL32_CR_LPM)); + } + + return(state); +} + + +/******************************************************************************* +* Function Name: CyXTAL_Start +******************************************************************************** +* +* Summary: +* Enables the megahertz crystal. +* +* PSoC 3: +* Waits until the XERR bit is low (no error) for a millisecond or until the +* number of milliseconds specified by the wait parameter has expired. +* +* Parameters: +* wait: Valid range [0-255]. +* This is the timeout value in milliseconds. +* The appropriate value is crystal specific. +* +* Return: +* CYRET_SUCCESS - Completed successfully +* CYRET_TIMEOUT - Timeout occurred without detecting a low value on XERR. +* +* Side Effects and Restrictions: +* If wait is enabled (non-zero wait). Uses the Fast Timewheel to time the wait. +* Any other use of the Fast Timewheel (FTW) will be stopped during the period +* of this function and then restored. +* +* Uses the 100KHz ILO. If not enabled, this function will enable the 100KHz +* ILO for the period of this function. No changes to the setup of the ILO, +* Fast Timewheel, Central Timewheel or Once Per Second interrupt may be made +* by interrupt routines during the period of this function. +* +* The current operation of the ILO, Central Timewheel and Once Per Second +* interrupt are maintained during the operation of this function provided the +* reading of the Power Manager Interrupt Status Register is only done using the +* CyPmReadStatus() function. +* +*******************************************************************************/ +cystatus CyXTAL_Start(uint8 wait) +{ + cystatus status = CYRET_SUCCESS; + volatile uint8 timeout = wait; + volatile uint8 count; + uint8 iloEnableState; + uint8 pmTwCfg0Tmp; + uint8 pmTwCfg2Tmp; + + + /* Enables the MHz crystal oscillator circuit */ + CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_ENABLE; + + + if(wait > 0u) + { + /* Save 100 KHz ILO, FTW interval, enable and interrupt enable */ + iloEnableState = CY_LIB_SLOWCLK_ILO_CR0_REG; + pmTwCfg0Tmp = CY_LIB_PM_TW_CFG0_REG; + pmTwCfg2Tmp = CY_LIB_PM_TW_CFG2_REG; + + /* Set 250 us interval */ + CyPmFtwSetInterval(CY_CLK_XMHZ_FTW_INTERVAL); + status = CYRET_TIMEOUT; + + + for( ; timeout > 0u; timeout--) + { + /* Read XERR bit to clear it */ + (void) CY_CLK_XMHZ_CSR_REG; + + /* Wait for a millisecond - 4 x 250 us */ + for(count = 4u; count > 0u; count--) + { + while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT))) + { + /* Wait for the FTW interrupt event */ + } + } + + + /******************************************************************* + * High output indicates oscillator failure. + * Only can be used after start-up interval (1 ms) is completed. + *******************************************************************/ + if(0u == (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR)) + { + status = CYRET_SUCCESS; + break; + } + } + + + /* Restore 100 KHz ILO, FTW interval, enable and interrupt enable */ + if(0u == (iloEnableState & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ)) + { + CyILO_Stop100K(); + } + CY_LIB_PM_TW_CFG0_REG = pmTwCfg0Tmp; + CY_LIB_PM_TW_CFG2_REG = pmTwCfg2Tmp; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyXTAL_Stop +******************************************************************************** +* +* Summary: +* Disables the megahertz crystal oscillator. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyXTAL_Stop(void) +{ + /* Disable the the oscillator. */ + FASTCLK_XMHZ_CSR &= ((uint8)(~XMHZ_CONTROL_ENABLE)); +} + + +/******************************************************************************* +* Function Name: CyXTAL_EnableErrStatus +******************************************************************************** +* +* Summary: +* Enables the generation of the XERR status bit for the megahertz crystal. +* This function is not available for PSoC5. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyXTAL_EnableErrStatus(void) +{ + /* If oscillator has insufficient amplitude, XERR bit will be high. */ + CY_CLK_XMHZ_CSR_REG &= ((uint8)(~CY_CLK_XMHZ_CSR_XFB)); +} + + +/******************************************************************************* +* Function Name: CyXTAL_DisableErrStatus +******************************************************************************** +* +* Summary: +* Disables the generation of the XERR status bit for the megahertz crystal. +* This function is not available for PSoC5. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyXTAL_DisableErrStatus(void) +{ + /* If oscillator has insufficient amplitude, XERR bit will be high. */ + CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_XFB; +} + + +/******************************************************************************* +* Function Name: CyXTAL_ReadStatus +******************************************************************************** +* +* Summary: +* Reads the XERR status bit for the megahertz crystal. This status bit is a +* sticky clear on read value. This function is not available for PSoC5. +* +* Parameters: +* None +* +* Return: +* Status +* 0: No error +* 1: Error +* +*******************************************************************************/ +uint8 CyXTAL_ReadStatus(void) +{ + /*************************************************************************** + * High output indicates oscillator failure. Only use this after start-up + * interval is completed. This can be used for status and failure recovery. + ***************************************************************************/ + return((0u != (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR)) ? 1u : 0u); +} + + +/******************************************************************************* +* Function Name: CyXTAL_EnableFaultRecovery +******************************************************************************** +* +* Summary: +* Enables the fault recovery circuit which will switch to the IMO in the case +* of a fault in the megahertz crystal circuit. The crystal must be up and +* running with the XERR bit at 0, before calling this function to prevent +* immediate fault switchover. This function is not available for PSoC5. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyXTAL_EnableFaultRecovery(void) +{ + CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_XPROT; +} + + +/******************************************************************************* +* Function Name: CyXTAL_DisableFaultRecovery +******************************************************************************** +* +* Summary: +* Disables the fault recovery circuit which will switch to the IMO in the case +* of a fault in the megahertz crystal circuit. This function is not available +* for PSoC5. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyXTAL_DisableFaultRecovery(void) +{ + CY_CLK_XMHZ_CSR_REG &= ((uint8)(~CY_CLK_XMHZ_CSR_XPROT)); +} + + +/******************************************************************************* +* Function Name: CyXTAL_SetStartup +******************************************************************************** +* +* Summary: +* Sets the startup settings for the crystal. Logic model outputs a frequency +* (setting + 4) MHz when enabled. +* +* This is artificial as the actual frequency is determined by an attached +* external crystal. +* +* Parameters: +* setting: Valid range [0-31]. +* Value is dependent on the frequency and quality of the crystal being used. +* Refer to the device TRM and datasheet for more information. +* +* Return: +* None +* +*******************************************************************************/ +void CyXTAL_SetStartup(uint8 setting) +{ + CY_CLK_XMHZ_CFG0_REG = (CY_CLK_XMHZ_CFG0_REG & ((uint8)(~CY_CLK_XMHZ_CFG0_XCFG_MASK))) | + (setting & CY_CLK_XMHZ_CFG0_XCFG_MASK); +} + + + +/******************************************************************************* +* Function Name: CyXTAL_SetFbVoltage +******************************************************************************** +* +* Summary: +* Sets the feedback reference voltage to use for the crystal circuit. +* This function is only available for PSoC3 and PSoC 5LP. +* +* Parameters: +* setting: Valid range [0-15]. +* Refer to the device TRM and datasheet for more information. +* +* Return: +* None +* +*******************************************************************************/ +void CyXTAL_SetFbVoltage(uint8 setting) +{ + CY_CLK_XMHZ_CFG1_REG = ((CY_CLK_XMHZ_CFG1_REG & ((uint8)(~CY_CLK_XMHZ_CFG1_VREF_FB_MASK))) | + (setting & CY_CLK_XMHZ_CFG1_VREF_FB_MASK)); +} + + +/******************************************************************************* +* Function Name: CyXTAL_SetWdVoltage +******************************************************************************** +* +* Summary: +* Sets the reference voltage used by the watchdog to detect a failure in the +* crystal circuit. This function is only available for PSoC3 and PSoC 5LP. +* +* Parameters: +* setting: Valid range [0-7]. +* Refer to the device TRM and datasheet for more information. +* +* Return: +* None +* +*******************************************************************************/ +void CyXTAL_SetWdVoltage(uint8 setting) +{ + CY_CLK_XMHZ_CFG1_REG = ((CY_CLK_XMHZ_CFG1_REG & ((uint8)(~CY_CLK_XMHZ_CFG1_VREF_WD_MASK))) | + (((uint8)(setting << 4u)) & CY_CLK_XMHZ_CFG1_VREF_WD_MASK)); +} + + +/******************************************************************************* +* Function Name: CyHalt +******************************************************************************** +* +* Summary: +* Halts the CPU. +* +* Parameters: +* uint8 reason: Value to be used during debugging. +* +* Return: +* None +* +*******************************************************************************/ +void CyHalt(uint8 reason) CYREENTRANT +{ + if(0u != reason) + { + /* To remove unreferenced local variable warning */ + } + + #if defined (__ARMCC_VERSION) + __breakpoint(0x0); + #elif defined(__GNUC__) || defined (__ICCARM__) + __asm(" bkpt 1"); + #elif defined(__C51__) + CYDEV_HALT_CPU; + #endif /* (__ARMCC_VERSION) */ +} + + +/******************************************************************************* +* Function Name: CySoftwareReset +******************************************************************************** +* +* Summary: +* Forces a software reset of the device. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CySoftwareReset(void) +{ + CY_LIB_RESET_CR2_REG |= CY_LIB_RESET_CR2_RESET; +} + + +/******************************************************************************* +* Function Name: CyDelay +******************************************************************************** +* +* Summary: +* Blocks for milliseconds. +* +* Note: +* CyDelay has been implemented with the instruction cache assumed enabled. When +* instruction cache is disabled on PSoC5, CyDelay will be two times larger. For +* example, with instruction cache disabled CyDelay(100) would result in about +* 200 ms delay instead of 100 ms. +* +* Parameters: +* milliseconds: number of milliseconds to delay. +* +* Return: +* None +* +*******************************************************************************/ +void CyDelay(uint32 milliseconds) CYREENTRANT +{ + while (milliseconds > 32768u) + { + /*********************************************************************** + * This loop prevents overflow.At 100MHz, milliseconds * delay_freq_khz + * overflows at about 42 seconds. + ***********************************************************************/ + CyDelayCycles(cydelay_32k_ms); + milliseconds = ((uint32)(milliseconds - 32768u)); + } + + CyDelayCycles(milliseconds * cydelay_freq_khz); +} + + +#if(!CY_PSOC3) + + /* For PSoC3 devices function is defined in CyBootAsmKeil.a51 file */ + + /******************************************************************************* + * Function Name: CyDelayUs + ******************************************************************************** + * + * Summary: + * Blocks for microseconds. + * + * Note: + * CyDelay has been implemented with the instruction cache assumed enabled. + * When instruction cache is disabled on PSoC5, CyDelayUs will be two times + * larger. Ex: With instruction cache disabled CyDelayUs(100) would result + * in about 200us delay instead of 100us. + * + * Parameters: + * uint16 microseconds: number of microseconds to delay. + * + * Return: + * None + * + * Side Effects: + * CyDelayUS has been implemented with the instruction cache assumed enabled. + * When instruction cache is disabled on PSoC 5, CyDelayUs will be two times + * larger. For example, with instruction cache disabled CyDelayUs(100) would + * result in about 200 us delay instead of 100 us. + * + * If the bus clock frequency is a small non-integer number, the actual delay + * can be up to twice as long as the nominal value. The actual delay cannot be + * shorter than the nominal one. + *******************************************************************************/ + void CyDelayUs(uint16 microseconds) CYREENTRANT + { + CyDelayCycles((uint32)microseconds * cydelay_freq_mhz); + } + +#endif /* (!CY_PSOC3) */ + + +/******************************************************************************* +* Function Name: CyDelayFreq +******************************************************************************** +* +* Summary: +* Sets clock frequency for CyDelay. +* +* Parameters: +* freq: Frequency of bus clock in Hertz. +* +* Return: +* None +* +*******************************************************************************/ +void CyDelayFreq(uint32 freq) CYREENTRANT +{ + if (freq != 0u) + { + cydelay_freq_hz = freq; + } + else + { + cydelay_freq_hz = BCLK__BUS_CLK__HZ; + } + + cydelay_freq_mhz = (uint8)((cydelay_freq_hz + 999999u) / 1000000u); + cydelay_freq_khz = (cydelay_freq_hz + 999u) / 1000u; + cydelay_32k_ms = 32768u * cydelay_freq_khz; +} + + +/******************************************************************************* +* Function Name: CyWdtStart +******************************************************************************** +* +* Summary: +* Enables the watchdog timer. +* +* The timer is configured for the specified count interval, the central +* timewheel is cleared, the setting for low power mode is configured and the +* watchdog timer is enabled. +* +* Once enabled the watchdog cannot be disabled. The watchdog counts each time +* the Central Time Wheel (CTW) reaches the period specified. The watchdog must +* be cleared using the CyWdtClear() function before three ticks of the watchdog +* timer occur. The CTW is free running, so this will occur after between 2 and +* 3 timer periods elapse. +* +* PSoC5: The watchdog timer should not be used during sleep modes. Since the +* WDT cannot be disabled after it is enabled, the WDT timeout period can be +* set to be greater than the sleep wakeup period, then feed the dog on each +* wakeup from Sleep. +* +* Parameters: +* ticks: One of the four available timer periods. Once WDT enabled, the + interval cannot be changed. +* CYWDT_2_TICKS - 4 - 6 ms +* CYWDT_16_TICKS - 32 - 48 ms +* CYWDT_128_TICKS - 256 - 384 ms +* CYWDT_1024_TICKS - 2.048 - 3.072 s +* +* lpMode: Low power mode configuration. This parameter is ignored for PSoC 5. +* The WDT always acts as if CYWDT_LPMODE_NOCHANGE is passed. +* +* CYWDT_LPMODE_NOCHANGE - No Change +* CYWDT_LPMODE_MAXINTER - Switch to longest timer mode during low power +* mode +* CYWDT_LPMODE_DISABLED - Disable WDT during low power mode +* +* Return: +* None +* +* Side Effects: +* PSoC5: The ILO 1 KHz must be enabled for proper WDT operation. Stopping the +* ILO 1 kHz could break the active WDT functionality. +* +*******************************************************************************/ +void CyWdtStart(uint8 ticks, uint8 lpMode) +{ + /* Set WDT interval */ + CY_WDT_CFG_REG = (CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_INTERVAL_MASK))) | (ticks & CY_WDT_CFG_INTERVAL_MASK); + + /* Reset CTW to ensure that first watchdog period is full */ + CY_WDT_CFG_REG |= CY_WDT_CFG_CTW_RESET; + CY_WDT_CFG_REG &= ((uint8)(~CY_WDT_CFG_CTW_RESET)); + + /* Setting the low power mode */ + CY_WDT_CFG_REG = (((uint8)(lpMode << CY_WDT_CFG_LPMODE_SHIFT)) & CY_WDT_CFG_LPMODE_MASK) | + (CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_LPMODE_MASK))); + + /* Enables the watchdog reset */ + CY_WDT_CFG_REG |= CY_WDT_CFG_WDR_EN; +} + + +/******************************************************************************* +* Function Name: CyWdtClear +******************************************************************************** +* +* Summary: +* Clears (feeds) the watchdog timer. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyWdtClear(void) +{ + CY_WDT_CR_REG = CY_WDT_CR_FEED; +} + + + +/******************************************************************************* +* Function Name: CyVdLvDigitEnable +******************************************************************************** +* +* Summary: +* Enables the digital low voltage monitors to generate interrupt on Vddd +* archives specified threshold and optionally resets device. +* +* Parameters: +* reset: Option to reset device at a specified Vddd threshold: +* 0 - Device is not reset. +* 1 - Device is reset. +* +* threshold: Sets the trip level for the voltage monitor. +* Values from 1.70 V to 5.45 V are accepted with the approximately 250 mV +* interval. +* +* Return: +* None +* +*******************************************************************************/ +void CyVdLvDigitEnable(uint8 reset, uint8 threshold) +{ + *CY_INT_CLEAR_PTR = 0x01u; + + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN)); + + CY_VD_LVI_TRIP_REG = (threshold & CY_VD_LVI_TRIP_LVID_MASK) | + (CY_VD_LVI_TRIP_REG & ((uint8)(~CY_VD_LVI_TRIP_LVID_MASK))); + CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVID_EN; + + /* Timeout to eliminate glitches on the LVI/HVI when enabling */ + CyDelayUs(1u); + + (void)CY_VD_PERSISTENT_STATUS_REG; + + if(0u != reset) + { + CY_VD_PRES_CONTROL_REG |= CY_VD_PRESD_EN; + } + else + { + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN)); + } + + *CY_INT_CLR_PEND_PTR = 0x01u; + *CY_INT_ENABLE_PTR = 0x01u; +} + + +/******************************************************************************* +* Function Name: CyVdLvAnalogEnable +******************************************************************************** +* +* Summary: +* Enables the analog low voltage monitors to generate interrupt on Vdda +* archives specified threshold and optionally resets device. +* +* Parameters: +* reset: Option to reset device at a specified Vdda threshold: +* 0 - Device is not reset. +* 1 - Device is reset. +* +* threshold: Sets the trip level for the voltage monitor. +* Values from 1.70 V to 5.45 V are accepted with the approximately 250 mV +* interval. +* +* Return: +* None +* +*******************************************************************************/ +void CyVdLvAnalogEnable(uint8 reset, uint8 threshold) +{ + *CY_INT_CLEAR_PTR = 0x01u; + + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); + + CY_VD_LVI_TRIP_REG = ((uint8)(threshold << 4u)) | (CY_VD_LVI_TRIP_REG & 0x0Fu); + CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVIA_EN; + + /* Timeout to eliminate glitches on the LVI/HVI when enabling */ + CyDelayUs(1u); + + (void)CY_VD_PERSISTENT_STATUS_REG; + + if(0u != reset) + { + CY_VD_PRES_CONTROL_REG |= CY_VD_PRESA_EN; + } + else + { + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); + } + + *CY_INT_CLR_PEND_PTR = 0x01u; + *CY_INT_ENABLE_PTR = 0x01u; +} + + +/******************************************************************************* +* Function Name: CyVdLvDigitDisable +******************************************************************************** +* +* Summary: +* Disables the digital low voltage monitor (interrupt and device reset are +* disabled). +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyVdLvDigitDisable(void) +{ + CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_LVID_EN)); + + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN)); + + while(0u != (CY_VD_PERSISTENT_STATUS_REG & 0x07u)) + { + + } +} + + +/******************************************************************************* +* Function Name: CyVdLvAnalogDisable +******************************************************************************** +* +* Summary: +* Disables the analog low voltage monitor (interrupt and device reset are +* disabled). +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyVdLvAnalogDisable(void) +{ + CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_LVIA_EN)); + + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); + + while(0u != (CY_VD_PERSISTENT_STATUS_REG & 0x07u)) + { + + } +} + + +/******************************************************************************* +* Function Name: CyVdHvAnalogEnable +******************************************************************************** +* +* Summary: +* Enables the analog high voltage monitors to generate interrupt on +* Vdda archives 5.75 V threshold and optionally resets device. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyVdHvAnalogEnable(void) +{ + *CY_INT_CLEAR_PTR = 0x01u; + + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); + + CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_HVIA_EN; + + /* Timeout to eliminate glitches on the LVI/HVI when enabling */ + CyDelayUs(1u); + + (void) CY_VD_PERSISTENT_STATUS_REG; + + *CY_INT_CLR_PEND_PTR = 0x01u; + *CY_INT_ENABLE_PTR = 0x01u; +} + + +/******************************************************************************* +* Function Name: CyVdHvAnalogDisable +******************************************************************************** +* +* Summary: +* Disables the analog low voltage monitor +* (interrupt and device reset are disabled). +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyVdHvAnalogDisable(void) +{ + CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_HVIA_EN)); +} + + +/******************************************************************************* +* Function Name: CyVdStickyStatus +******************************************************************************** +* +* Summary: +* Manages the Reset and Voltage Detection Status Register 0. +* This register has the interrupt status for the HVIA, LVID and LVIA. +* This hardware register clears on read. +* +* Parameters: +* mask: Bits in the shadow register to clear. +* Define Definition +* CY_VD_LVID Persistent status of digital LVI. +* CY_VD_LVIA Persistent status of analog LVI. +* CY_VD_HVIA Persistent status of analog HVI. +* +* Return: +* Status. Same enumerated bit values as used for the mask parameter. +* +*******************************************************************************/ +uint8 CyVdStickyStatus(uint8 mask) +{ + uint8 status; + + status = CY_VD_PERSISTENT_STATUS_REG; + CY_VD_PERSISTENT_STATUS_REG &= ((uint8)(~mask)); + + return(status); +} + + +/******************************************************************************* +* Function Name: CyVdRealTimeStatus +******************************************************************************** +* +* Summary: +* Returns the real time voltage detection status. +* +* Parameters: +* None +* +* Return: +* Status: +* Define Definition +* CY_VD_LVID Persistent status of digital LVI. +* CY_VD_LVIA Persistent status of analog LVI. +* CY_VD_HVIA Persistent status of analog HVI. +* +*******************************************************************************/ +uint8 CyVdRealTimeStatus(void) +{ + uint8 interruptState; + uint8 vdFlagsState; + + interruptState = CyEnterCriticalSection(); + vdFlagsState = CY_VD_RT_STATUS_REG; + CyExitCriticalSection(interruptState); + + return(vdFlagsState); +} + + +/******************************************************************************* +* Function Name: CyDisableInts +******************************************************************************** +* +* Summary: +* Disables the interrupt enable for each interrupt. +* +* Parameters: +* None +* +* Return: +* 32 bit mask of previously enabled interrupts. +* +*******************************************************************************/ +uint32 CyDisableInts(void) +{ + uint32 intState; + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + #if(CY_PSOC3) + + /* Get the current interrupt state. */ + intState = ((uint32) CY_GET_REG8(CY_INT_CLR_EN0_PTR)); + intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN1_PTR)) << 8u)); + intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN2_PTR)) << 16u)); + intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN3_PTR)) << 24u)); + + + /* Disable all of the interrupts. */ + CY_SET_REG8(CY_INT_CLR_EN0_PTR, 0xFFu); + CY_SET_REG8(CY_INT_CLR_EN1_PTR, 0xFFu); + CY_SET_REG8(CY_INT_CLR_EN2_PTR, 0xFFu); + CY_SET_REG8(CY_INT_CLR_EN3_PTR, 0xFFu); + + #else + + /* Get the current interrupt state. */ + intState = CY_GET_REG32(CY_INT_CLEAR_PTR); + + /* Disable all of the interrupts. */ + CY_SET_REG32(CY_INT_CLEAR_PTR, 0xFFFFFFFFu); + + #endif /* (CY_PSOC3) */ + + CyExitCriticalSection(interruptState); + + return (intState); +} + + +/******************************************************************************* +* Function Name: CyEnableInts +******************************************************************************** +* +* Summary: +* Enables interrupts to a given state. +* +* Parameters: +* uint32 mask: 32 bit mask of interrupts to enable. +* +* Return: +* None +* +*******************************************************************************/ +void CyEnableInts(uint32 mask) +{ + + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + #if(CY_PSOC3) + + /* Set interrupts as enabled. */ + CY_SET_REG8(CY_INT_SET_EN3_PTR, ((uint8) (mask >> 24u))); + CY_SET_REG8(CY_INT_SET_EN2_PTR, ((uint8) (mask >> 16u))); + CY_SET_REG8(CY_INT_SET_EN1_PTR, ((uint8) (mask >> 8u ))); + CY_SET_REG8(CY_INT_SET_EN0_PTR, ((uint8) (mask ))); + + #else + + CY_SET_REG32(CY_INT_ENABLE_PTR, mask); + + #endif /* (CY_PSOC3) */ + + CyExitCriticalSection(interruptState); + +} + +#if(CY_PSOC5) + + /******************************************************************************* + * Function Name: CyFlushCache + ******************************************************************************** + * Summary: + * Flushes the PSoC 5/5LP cache by invalidating all entries. + * + * Parameters: + * None + * + * Return: + * None + * + *******************************************************************************/ + void CyFlushCache(void) + { + uint8 interruptState; + + /* Save current global interrupt enable and disable it */ + interruptState = CyEnterCriticalSection(); + + /* Fill instruction prefectch unit to insure data integrity */ + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + + /* All entries in the cache are invalidated on the next clock cycle. */ + CY_CACHE_CONTROL_REG |= CY_CACHE_CONTROL_FLUSH; + + + /*********************************************************************** + * The prefetch unit could/would be filled with the instructions that + * succeed the flush. Since a flush is desired then theoretically those + * instructions might be considered stale/invalid. + ***********************************************************************/ + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CyIntSetSysVector + ******************************************************************************** + * Summary: + * Sets the interrupt vector of the specified system interrupt number. System + * interrupts are present only for the ARM platform. These interrupts are for + * SysTick, PendSV and others. + * + * Parameters: + * number: Interrupt number, valid range [0-15]. + address: Pointer to an interrupt service routine. + * + * Return: + * The old ISR vector at this location. + * + *******************************************************************************/ + cyisraddress CyIntSetSysVector(uint8 number, cyisraddress address) + { + cyisraddress oldIsr; + cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE; + + CYASSERT(number <= CY_INT_SYS_NUMBER_MAX); + + /* Save old Interrupt service routine. */ + oldIsr = ramVectorTable[number & CY_INT_SYS_NUMBER_MASK]; + + /* Set new Interrupt service routine. */ + ramVectorTable[number & CY_INT_SYS_NUMBER_MASK] = address; + + return (oldIsr); + } + + + /******************************************************************************* + * Function Name: CyIntGetSysVector + ******************************************************************************** + * + * Summary: + * Gets the interrupt vector of the specified system interrupt number. System + * interrupts are present only for the ARM platform. These interrupts are for + * SysTick, PendSV and others. + * + * Parameters: + * number: The interrupt number, valid range [0-15]. + * + * Return: + * Address of the ISR in the interrupt vector table. + * + *******************************************************************************/ + cyisraddress CyIntGetSysVector(uint8 number) + { + cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE; + CYASSERT(number <= CY_INT_SYS_NUMBER_MAX); + + return ramVectorTable[number & CY_INT_SYS_NUMBER_MASK]; + } + + + /******************************************************************************* + * Function Name: CyIntSetVector + ******************************************************************************** + * + * Summary: + * Sets the interrupt vector of the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number + * address: Pointer to an interrupt service routine + * + * Return: + * Previous interrupt vector value. + * + *******************************************************************************/ + cyisraddress CyIntSetVector(uint8 number, cyisraddress address) + { + cyisraddress oldIsr; + cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + /* Save old Interrupt service routine. */ + oldIsr = ramVectorTable[CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK)]; + + /* Set new Interrupt service routine. */ + ramVectorTable[CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK)] = address; + + return (oldIsr); + } + + + /******************************************************************************* + * Function Name: CyIntGetVector + ******************************************************************************** + * + * Summary: + * Gets the interrupt vector of the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number + * + * Return: + * Address of the ISR in the interrupt vector table. + * + *******************************************************************************/ + cyisraddress CyIntGetVector(uint8 number) + { + cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE; + CYASSERT(number <= CY_INT_NUMBER_MAX); + + return (ramVectorTable[CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK)]); + } + + + /******************************************************************************* + * Function Name: CyIntSetPriority + ******************************************************************************** + * + * Summary: + * Sets the Priority of the Interrupt. + * + * Parameters: + * priority: Priority of the interrupt. 0 - 7, 0 being the highest. + * number: The number of the interrupt, 0 - 31. + * + * Return: + * None + * + *******************************************************************************/ + void CyIntSetPriority(uint8 number, uint8 priority) + { + CYASSERT(priority <= CY_INT_PRIORITY_MAX); + CYASSERT(number <= CY_INT_NUMBER_MAX); + CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] = (priority & CY_INT_PRIORITY_MASK)<< 5; + } + + + /******************************************************************************* + * Function Name: CyIntGetPriority + ******************************************************************************** + * + * Summary: + * Gets the Priority of the Interrupt. + * + * Parameters: + * number: The number of the interrupt, 0 - 31. + * + * Return: + * Priority of the interrupt. 0 - 7, 0 being the highest. + * + *******************************************************************************/ + uint8 CyIntGetPriority(uint8 number) + { + uint8 priority; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + priority = CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] >> 5; + + return (priority); + } + + + /******************************************************************************* + * Function Name: CyIntGetState + ******************************************************************************** + * + * Summary: + * Gets the enable state of the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number. + * + * Return: + * Enable status: 1 if enabled, 0 if disabled + * + *******************************************************************************/ + uint8 CyIntGetState(uint8 number) + { + reg32 * stateReg; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + /* Get a pointer to the Interrupt enable register. */ + stateReg = CY_INT_ENABLE_PTR; + + /* Get the state of the interrupt. */ + return (0u != (*stateReg & (((uint32) 1u) << (0x1Fu & number)))) ? ((uint8)(1u)) : ((uint8)(0u)); + } + + +#else /* PSoC3 */ + + + /******************************************************************************* + * Function Name: CyIntSetVector + ******************************************************************************** + * + * Summary: + * Sets the interrupt vector of the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number + * address: Pointer to an interrupt service routine + * + * Return: + * Previous interrupt vector value. + * + *******************************************************************************/ + cyisraddress CyIntSetVector(uint8 number, cyisraddress address) + { + cyisraddress oldIsr; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + /* Save old Interrupt service routine. */ + oldIsr = (cyisraddress) \ + CY_GET_REG16(&CY_INT_VECT_TABLE[number & CY_INT_NUMBER_MASK]); + + /* Set new Interrupt service routine. */ + CY_SET_REG16(&CY_INT_VECT_TABLE[number], (uint16) address); + + return (oldIsr); + } + + + /******************************************************************************* + * Function Name: CyIntGetVector + ******************************************************************************** + * + * Summary: + * Gets the interrupt vector of the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number + * + * Return: + * Address of the ISR in the interrupt vector table. + * + *******************************************************************************/ + cyisraddress CyIntGetVector(uint8 number) + { + CYASSERT(number <= CY_INT_NUMBER_MAX); + + return ((cyisraddress) \ + CY_GET_REG16(&CY_INT_VECT_TABLE[number & CY_INT_NUMBER_MASK])); + } + + + /******************************************************************************* + * Function Name: CyIntSetPriority + ******************************************************************************** + * + * Summary: + * Sets the Priority of the Interrupt. + * + * Parameters: + * priority: Priority of the interrupt. 0 - 7, 0 being the highest. + * number: The number of the interrupt, 0 - 31. + * + * Return: + * None + * + *******************************************************************************/ + void CyIntSetPriority(uint8 number, uint8 priority) + { + CYASSERT(priority <= CY_INT_PRIORITY_MAX); + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] = + (priority & CY_INT_PRIORITY_MASK) << 5; + } + + + /******************************************************************************* + * Function Name: CyIntGetPriority + ******************************************************************************** + * + * Summary: + * Gets the Priority of the Interrupt. + * + * Parameters: + * number: The number of the interrupt, 0 - 31. + * + * Return: + * Priority of the interrupt. 0 - 7, 0 being the highest. + * + *******************************************************************************/ + uint8 CyIntGetPriority(uint8 number) + { + uint8 priority; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + priority = CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] >> 5; + + return (priority); + } + + + /******************************************************************************* + * Function Name: CyIntGetState + ******************************************************************************** + * + * Summary: + * Gets the enable state of the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number. + * + * Return: + * Enable status: 1 if enabled, 0 if disabled + * + *******************************************************************************/ + uint8 CyIntGetState(uint8 number) + { + reg8 * stateReg; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + /* Get a pointer to the Interrupt enable register. */ + stateReg = CY_INT_ENABLE_PTR + ((number & CY_INT_NUMBER_MASK) >> 3u); + + /* Get the state of the interrupt. */ + return ((0u != (*stateReg & ((uint8)(1u << (0x07u & number))))) ? ((uint8)(1u)) : ((uint8)(0u))); + } + + +#endif /* (CY_PSOC5) */ + + +#if(CYDEV_VARIABLE_VDDA == 1) + + /******************************************************************************* + * Function Name: CySetScPumps + ******************************************************************************** + * + * Summary: + * If 1 is passed as a parameter: + * - if any of the SC blocks are used - enable pumps for the SC blocks and + * start boost clock. + * - For the each enabled SC block set boost clock index and enable boost + * clock. + * + * If non-1 value is passed as a parameter: + * - If all SC blocks are not used - disable pumps for the SC blocks and + * stop boost clock. + * - For the each enabled SC block clear boost clock index and disable boost + * clock. + * + * The global variable CyScPumpEnabled is updated to be equal to passed + * parameter. + * + * Parameters: + * uint8 enable: Enable/disable SC pumps and boost clock for enabled SC block. + * 1 - Enable + * 0 - Disable + * + * Return: + * None + * + *******************************************************************************/ + void CySetScPumps(uint8 enable) + { + if(1u == enable) + { + /* The SC pumps should be enabled */ + CyScPumpEnabled = 1u; + /* Enable pumps if any of SC blocks are used */ + if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAPS_MASK)) + { + CY_LIB_SC_MISC_REG |= CY_LIB_SC_MISC_PUMP_FORCE; + CyScBoostClk_Start(); + } + /* Set positive pump for each enabled SC block: set clock index and enable it */ + if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP0_EN)) + { + CY_LIB_SC0_BST_REG = (CY_LIB_SC0_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX; + CY_LIB_SC0_BST_REG |= CY_LIB_SC_BST_CLK_EN; + } + if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP1_EN)) + { + CY_LIB_SC1_BST_REG = (CY_LIB_SC1_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX; + CY_LIB_SC1_BST_REG |= CY_LIB_SC_BST_CLK_EN; + } + if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP2_EN)) + { + CY_LIB_SC2_BST_REG = (CY_LIB_SC2_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX; + CY_LIB_SC2_BST_REG |= CY_LIB_SC_BST_CLK_EN; + } + if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP3_EN)) + { + CY_LIB_SC3_BST_REG = (CY_LIB_SC3_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX; + CY_LIB_SC3_BST_REG |= CY_LIB_SC_BST_CLK_EN; + } + } + else + { + /* The SC pumps should be disabled */ + CyScPumpEnabled = 0u; + /* Disable pumps for all SC blocks and stop boost clock */ + CY_LIB_SC_MISC_REG &= ((uint8)(~CY_LIB_SC_MISC_PUMP_FORCE)); + CyScBoostClk_Stop(); + /* Disable boost clock and clear clock index for each SC block */ + CY_LIB_SC0_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN)); + CY_LIB_SC0_BST_REG = CY_LIB_SC0_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK; + CY_LIB_SC1_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN)); + CY_LIB_SC1_BST_REG = CY_LIB_SC1_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK; + CY_LIB_SC2_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN)); + CY_LIB_SC2_BST_REG = CY_LIB_SC2_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK; + CY_LIB_SC3_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN)); + CY_LIB_SC3_BST_REG = CY_LIB_SC3_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK; + } + } + +#endif /* (CYDEV_VARIABLE_VDDA == 1) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyLib.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyLib.h new file mode 100644 index 00000000..3bc638c7 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CyLib.h @@ -0,0 +1,1281 @@ +/******************************************************************************* +* File Name: CyLib.h +* Version 4.0 +* +* Description: +* Provides the function definitions for the system, clocking, interrupts and +* watchdog timer API. +* +* Note: +* Documentation of the API's in this file is located in the System Reference +* Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYLIB_H) +#define CY_BOOT_CYLIB_H + +#include +#include +#include + +#include "cytypes.h" +#include "cyfitter.h" +#include "cydevice_trm.h" +#include "cyPm.h" + +#if(CY_PSOC3) + #include +#endif /* (CY_PSOC3) */ + + +#if(CYDEV_VARIABLE_VDDA == 1) + + #include "CyScBoostClk.h" + +#endif /* (CYDEV_VARIABLE_VDDA == 1) */ + + +/* Global variable with preserved reset status */ +extern uint8 CYXDATA CyResetStatus; + + +/* Variable Vdda */ +#if(CYDEV_VARIABLE_VDDA == 1) + + extern uint8 CyScPumpEnabled; + +#endif /* (CYDEV_VARIABLE_VDDA == 1) */ + + +/* Do not use these definitions directly in your application */ +extern uint32 cydelay_freq_hz; +extern uint32 cydelay_freq_khz; +extern uint8 cydelay_freq_mhz; +extern uint32 cydelay_32k_ms; + + +/*************************************** +* Function Prototypes +***************************************/ +cystatus CyPLL_OUT_Start(uint8 wait) ; +void CyPLL_OUT_Stop(void) ; +void CyPLL_OUT_SetPQ(uint8 pDiv, uint8 qDiv, uint8 current) ; +void CyPLL_OUT_SetSource(uint8 source) ; + +void CyIMO_Start(uint8 wait) ; +void CyIMO_Stop(void) ; +void CyIMO_SetFreq(uint8 freq) ; +void CyIMO_SetSource(uint8 source) ; +void CyIMO_EnableDoubler(void) ; +void CyIMO_DisableDoubler(void) ; + +void CyMasterClk_SetSource(uint8 source) ; +void CyMasterClk_SetDivider(uint8 divider) ; +void CyBusClk_SetDivider(uint16 divider) ; + +#if(CY_PSOC3) + void CyCpuClk_SetDivider(uint8 divider) ; +#endif /* (CY_PSOC3) */ + +void CyUsbClk_SetSource(uint8 source) ; + +void CyILO_Start1K(void) ; +void CyILO_Stop1K(void) ; +void CyILO_Start100K(void) ; +void CyILO_Stop100K(void) ; +void CyILO_Enable33K(void) ; +void CyILO_Disable33K(void) ; +void CyILO_SetSource(uint8 source) ; +uint8 CyILO_SetPowerMode(uint8 mode) ; + +uint8 CyXTAL_32KHZ_ReadStatus(void) ; +uint8 CyXTAL_32KHZ_SetPowerMode(uint8 mode) ; +void CyXTAL_32KHZ_Start(void) ; +void CyXTAL_32KHZ_Stop(void) ; + +cystatus CyXTAL_Start(uint8 wait) ; +void CyXTAL_Stop(void) ; +void CyXTAL_SetStartup(uint8 setting) ; + +void CyXTAL_EnableErrStatus(void) ; +void CyXTAL_DisableErrStatus(void) ; +uint8 CyXTAL_ReadStatus(void) ; +void CyXTAL_EnableFaultRecovery(void) ; +void CyXTAL_DisableFaultRecovery(void) ; + +void CyXTAL_SetFbVoltage(uint8 setting) ; +void CyXTAL_SetWdVoltage(uint8 setting) ; + +void CyWdtStart(uint8 ticks, uint8 lpMode) ; +void CyWdtClear(void) ; + +/* System Function Prototypes */ +void CyDelay(uint32 milliseconds) CYREENTRANT; +void CyDelayUs(uint16 microseconds); +void CyDelayFreq(uint32 freq) CYREENTRANT; +void CyDelayCycles(uint32 cycles); + +void CySoftwareReset(void) ; + +uint8 CyEnterCriticalSection(void); +void CyExitCriticalSection(uint8 savedIntrStatus); +void CyHalt(uint8 reason) CYREENTRANT; + + +/* Interrupt Function Prototypes */ +#if(CY_PSOC5) + cyisraddress CyIntSetSysVector(uint8 number, cyisraddress address) ; + cyisraddress CyIntGetSysVector(uint8 number) ; +#endif /* (CY_PSOC5) */ + +cyisraddress CyIntSetVector(uint8 number, cyisraddress address) ; +cyisraddress CyIntGetVector(uint8 number) ; + +void CyIntSetPriority(uint8 number, uint8 priority) ; +uint8 CyIntGetPriority(uint8 number) ; + +uint8 CyIntGetState(uint8 number) ; + +uint32 CyDisableInts(void) ; +void CyEnableInts(uint32 mask) ; + + +#if(CY_PSOC5) + void CyFlushCache(void); +#endif /* (CY_PSOC5) */ + + +/* Voltage Detection Function Prototypes */ +void CyVdLvDigitEnable(uint8 reset, uint8 threshold) ; +void CyVdLvAnalogEnable(uint8 reset, uint8 threshold) ; +void CyVdLvDigitDisable(void) ; +void CyVdLvAnalogDisable(void) ; +void CyVdHvAnalogEnable(void) ; +void CyVdHvAnalogDisable(void) ; +uint8 CyVdStickyStatus(uint8 mask) ; +uint8 CyVdRealTimeStatus(void) ; + +void CySetScPumps(uint8 enable) ; + + +/*************************************** +* API Constants +***************************************/ + + +/******************************************************************************* +* PLL API Constants +*******************************************************************************/ +#define CY_CLK_PLL_ENABLE (0x01u) +#define CY_CLK_PLL_LOCK_STATUS (0x01u) + +#define CY_CLK_PLL_FTW_INTERVAL (24u) + +#define CY_CLK_PLL_MAX_Q_VALUE (16u) +#define CY_CLK_PLL_MIN_Q_VALUE (1u) +#define CY_CLK_PLL_MIN_P_VALUE (8u) +#define CY_CLK_PLL_MIN_CUR_VALUE (1u) +#define CY_CLK_PLL_MAX_CUR_VALUE (7u) + +#define CY_CLK_PLL_CURRENT_POSITION (4u) +#define CY_CLK_PLL_CURRENT_MASK (0x8Fu) + + +/******************************************************************************* +* External 32kHz Crystal Oscillator API Constants +*******************************************************************************/ +#define CY_XTAL32K_ANA_STAT (0x20u) + +#define CY_CLK_XTAL32_CR_LPM (0x02u) +#define CY_CLK_XTAL32_CR_EN (0x01u) +#if(CY_PSOC3) + #define CY_CLK_XTAL32_CR_PDBEN (0x04u) +#endif /* (CY_PSOC3) */ + +#define CY_CLK_XTAL32_TR_MASK (0x07u) +#define CY_CLK_XTAL32_TR_STARTUP (0x03u) +#define CY_CLK_XTAL32_TR_HIGH_POWER (0x06u) +#define CY_CLK_XTAL32_TR_LOW_POWER (0x01u) +#define CY_CLK_XTAL32_TR_POWERDOWN (0x00u) + +#define CY_CLK_XTAL32_TST_DEFAULT (0xF3u) + +#define CY_CLK_XTAL32_CFG_LP_DEFAULT (0x04u) +#define CY_CLK_XTAL32_CFG_LP_LOWPOWER (0x08u) +#define CY_CLK_XTAL32_CFG_LP_MASK (0x0Cu) + +#define CY_CLK_XTAL32_CFG_LP_ALLOW (0x80u) + + +/******************************************************************************* +* External MHz Crystal Oscillator API Constants +*******************************************************************************/ +#define CY_CLK_XMHZ_FTW_INTERVAL (24u) +#define CY_CLK_XMHZ_MIN_TIMEOUT (130u) + +#define CY_CLK_XMHZ_CSR_ENABLE (0x01u) +#define CY_CLK_XMHZ_CSR_XERR (0x80u) +#define CY_CLK_XMHZ_CSR_XFB (0x04u) +#define CY_CLK_XMHZ_CSR_XPROT (0x40u) + +#define CY_CLK_XMHZ_CFG0_XCFG_MASK (0x1Fu) +#define CY_CLK_XMHZ_CFG1_VREF_FB_MASK (0x0Fu) +#define CY_CLK_XMHZ_CFG1_VREF_WD_MASK (0x70u) + + +/******************************************************************************* +* Watchdog Timer API Constants +*******************************************************************************/ +#define CYWDT_2_TICKS (0x0u) /* 4 - 6 ms */ +#define CYWDT_16_TICKS (0x1u) /* 32 - 48 ms */ +#define CYWDT_128_TICKS (0x2u) /* 256 - 384 ms */ +#define CYWDT_1024_TICKS (0x3u) /* 2048 - 3072 ms */ + +#define CYWDT_LPMODE_NOCHANGE (0x00u) +#define CYWDT_LPMODE_MAXINTER (0x01u) +#define CYWDT_LPMODE_DISABLED (0x03u) + +#define CY_WDT_CFG_INTERVAL_MASK (0x03u) +#define CY_WDT_CFG_CTW_RESET (0x80u) +#define CY_WDT_CFG_LPMODE_SHIFT (5u) +#define CY_WDT_CFG_LPMODE_MASK (0x60u) +#define CY_WDT_CFG_WDR_EN (0x10u) +#define CY_WDT_CFG_CLEAR_ALL (0x00u) +#define CY_WDT_CR_FEED (0x01u) + + +/******************************************************************************* +* Voltage Detection API Constants +*******************************************************************************/ + +#define CY_VD_LVID_EN (0x01u) +#define CY_VD_LVIA_EN (0x02u) +#define CY_VD_HVIA_EN (0x04u) + +#define CY_VD_PRESD_EN (0x40u) +#define CY_VD_PRESA_EN (0x80u) + +#define CY_VD_LVID (0x01u) +#define CY_VD_LVIA (0x02u) +#define CY_VD_HVIA (0x04u) + +#define CY_VD_LVI_TRIP_LVID_MASK (0x0Fu) + + +/******************************************************************************* +* Variable VDDA API Constants +*******************************************************************************/ +#if(CYDEV_VARIABLE_VDDA == 1) + + /* Active Power Mode Configuration Register 9 */ + #define CY_LIB_ACT_CFG9_SWCAP0_EN (0x01u) + #define CY_LIB_ACT_CFG9_SWCAP1_EN (0x02u) + #define CY_LIB_ACT_CFG9_SWCAP2_EN (0x04u) + #define CY_LIB_ACT_CFG9_SWCAP3_EN (0x08u) + #define CY_LIB_ACT_CFG9_SWCAPS_MASK (0x0Fu) + + /* Switched Cap Miscellaneous Control Register */ + #define CY_LIB_SC_MISC_PUMP_FORCE (0x20u) + + /* Switched Capacitor 0 Boost Clock Selection Register */ + #define CY_LIB_SC_BST_CLK_EN (0x08u) + #define CY_LIB_SC_BST_CLK_INDEX_MASK (0xF8u) + +#endif /* (CYDEV_VARIABLE_VDDA == 1) */ + + +/******************************************************************************* +* Clock Distribution API Constants +*******************************************************************************/ +#define CY_LIB_CLKDIST_AMASK_MASK (0xF0u) +#define CY_LIB_CLKDIST_DMASK_MASK (0x00u) +#define CY_LIB_CLKDIST_LD_LOAD (0x01u) +#define CY_LIB_CLKDIST_BCFG2_MASK (0x80u) +#define CY_LIB_CLKDIST_MASTERCLK_DIV (7u) +#define CY_LIB_CLKDIST_BCFG2_SSS (0x40u) +#define CY_LIB_CLKDIST_MSTR1_SRC_MASK (0xFCu) +#define CY_LIB_FASTCLK_IMO_DOUBLER (0x10u) +#define CY_LIB_FASTCLK_IMO_IMO (0x20u) +#define CY_LIB_CLKDIST_CR_IMO2X (0x40u) +#define CY_LIB_FASTCLK_IMO_CR_RANGE_MASK (0xF8u) + +#define CY_LIB_CLKDIST_CR_PLL_SCR_MASK (0xFCu) + + +/* CyILO_SetPowerMode() */ +#define CY_ILO_CONTROL_PD_MODE (0x10u) +#define CY_ILO_CONTROL_PD_POSITION (4u) + +#define CY_ILO_SOURCE_100K (0u) +#define CY_ILO_SOURCE_33K (1u) +#define CY_ILO_SOURCE_1K (2u) + +#define CY_ILO_FAST_START (0u) +#define CY_ILO_SLOW_START (1u) + +#define CY_ILO_SOURCE_BITS_CLEAR (0xF3u) +#define CY_ILO_SOURCE_1K_SET (0x08u) +#define CY_ILO_SOURCE_33K_SET (0x04u) +#define CY_ILO_SOURCE_100K_SET (0x00u) + +#define CY_MASTER_SOURCE_IMO (0u) +#define CY_MASTER_SOURCE_PLL (1u) +#define CY_MASTER_SOURCE_XTAL (2u) +#define CY_MASTER_SOURCE_DSI (3u) + +#define CY_IMO_SOURCE_IMO (0u) +#define CY_IMO_SOURCE_XTAL (1u) +#define CY_IMO_SOURCE_DSI (2u) + + +/* CyIMO_Start() */ +#define CY_LIB_PM_ACT_CFG0_IMO_EN (0x10u) +#define CY_LIB_PM_STBY_CFG0_IMO_EN (0x10u) +#define CY_LIB_CLK_IMO_FTW_TIMEOUT (0x00u) + +#define CY_LIB_IMO_3MHZ_VALUE (0x03u) +#define CY_LIB_IMO_6MHZ_VALUE (0x01u) +#define CY_LIB_IMO_12MHZ_VALUE (0x00u) +#define CY_LIB_IMO_24MHZ_VALUE (0x02u) +#define CY_LIB_IMO_48MHZ_VALUE (0x04u) +#define CY_LIB_IMO_62MHZ_VALUE (0x05u) +#define CY_LIB_IMO_74MHZ_VALUE (0x06u) + + +/* CyIMO_SetFreq() */ +#define CY_IMO_FREQ_3MHZ (0u) +#define CY_IMO_FREQ_6MHZ (1u) +#define CY_IMO_FREQ_12MHZ (2u) +#define CY_IMO_FREQ_24MHZ (3u) +#define CY_IMO_FREQ_48MHZ (4u) +#define CY_IMO_FREQ_62MHZ (5u) +#if(CY_PSOC5) + #define CY_IMO_FREQ_74MHZ (6u) +#endif /* (CY_PSOC5) */ +#define CY_IMO_FREQ_USB (8u) + +#define CY_LIB_IMO_USBCLK_ON_SET (0x40u) + + +/* CyCpuClk_SetDivider() */ +#define CY_LIB_CLKDIST_DIV_POSITION (4u) +#define CY_LIB_CLKDIST_MSTR1_DIV_MASK (0x0Fu) + + +/* CyIMO_SetTrimValue() */ +#define CY_LIB_USB_CLK_EN (0x02u) + + +/* CyPLL_OUT_SetSource() - parameters */ +#define CY_PLL_SOURCE_IMO (0u) +#define CY_PLL_SOURCE_XTAL (1u) +#define CY_PLL_SOURCE_DSI (2u) + + +/* CyILO_[Start|Stop][1|100K](), CyILO_[Enable|Disable]33K() */ +#define CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ (0x02u) +#define CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ (0x20u) +#define CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ (0x04u) + + +/* CyUsbClk_SetSource() */ +#define CY_LIB_CLKDIST_UCFG_SRC_SEL_MASK (0x03u) + + +/* CyUsbClk_SetSource() - parameters */ +#define CY_LIB_USB_CLK_IMO2X (0x00u) +#define CY_LIB_USB_CLK_IMO (0x01u) +#define CY_LIB_USB_CLK_PLL (0x02u) +#define CY_LIB_USB_CLK_DSI (0x03u) + + +/* CyUSB_PowerOnCheck() */ +#define CY_ACT_USB_ENABLED (0x01u) +#define CY_ALT_ACT_USB_ENABLED (0x01u) + + +/*************************************** +* Registers +***************************************/ + + +/******************************************************************************* +* System Registers +*******************************************************************************/ + +/* Software Reset Control Register */ +#define CY_LIB_RESET_CR2_REG (* (reg8 *) CYREG_RESET_CR2) +#define CY_LIB_RESET_CR2_PTR ( (reg8 *) CYREG_RESET_CR2) + +/* Timewheel Configuration Register 0 */ +#define CY_LIB_PM_TW_CFG0_REG (*(reg8 *) CYREG_PM_TW_CFG0) +#define CY_LIB_PM_TW_CFG0_PTR ( (reg8 *) CYREG_PM_TW_CFG0) + +/* Timewheel Configuration Register 2 */ +#define CY_LIB_PM_TW_CFG2_REG (*(reg8 *) CYREG_PM_TW_CFG2) +#define CY_LIB_PM_TW_CFG2_PTR ( (reg8 *) CYREG_PM_TW_CFG2) + +/* USB Configuration Register */ +#define CY_LIB_CLKDIST_UCFG_REG (*(reg8 *) CYREG_CLKDIST_UCFG) +#define CY_LIB_CLKDIST_UCFG_PTR ( (reg8 *) CYREG_CLKDIST_UCFG) + +/* Internal Main Oscillator Trim Register 1 */ +#define CY_LIB_IMO_TR1_REG (*(reg8 *) CYREG_IMO_TR1) +#define CY_LIB_IMO_TR1_PTR ( (reg8 *) CYREG_IMO_TR1) + +/* USB control 1 Register */ +#define CY_LIB_USB_CR1_REG (*(reg8 *) CYREG_USB_CR1 ) +#define CY_LIB_USB_CR1_PTR ( (reg8 *) CYREG_USB_CR1 ) + +/* Active Power Mode Configuration Register 0 */ +#define CY_LIB_PM_ACT_CFG0_REG (*(reg8 *) CYREG_PM_ACT_CFG0) +#define CY_LIB_PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0) + +/* Standby Power Mode Configuration Register 0 */ +#define CY_LIB_PM_STBY_CFG0_REG (*(reg8 *) CYREG_PM_STBY_CFG0) +#define CY_LIB_PM_STBY_CFG0_PTR ( (reg8 *) CYREG_PM_STBY_CFG0) + +/* Active Power Mode Configuration Register 5 */ +#define CY_LIB_PM_ACT_CFG5_REG (* (reg8 *) CYREG_PM_ACT_CFG5 ) +#define CY_LIB_PM_ACT_CFG5_PTR ( (reg8 *) CYREG_PM_ACT_CFG5 ) + +/* Standby Power Mode Configuration Register 5 */ +#define CY_LIB_PM_STBY_CFG5_REG (* (reg8 *) CYREG_PM_STBY_CFG5 ) +#define CY_LIB_PM_STBY_CFG5_PTR ( (reg8 *) CYREG_PM_STBY_CFG5 ) + +/* CyIMO_SetTrimValue() */ +#if(CY_PSOC3) + #define CY_LIB_TRIM_IMO_3MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ) + #define CY_LIB_TRIM_IMO_6MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ) + #define CY_LIB_TRIM_IMO_12MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ) + #define CY_LIB_TRIM_IMO_24MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ) + #define CY_LIB_TRIM_IMO_67MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ) + #define CY_LIB_TRIM_IMO_80MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ) + #define CY_LIB_TRIM_IMO_USB_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_USB) + #define CY_LIB_TRIM_IMO_TR1_PTR ((void far *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u)) + #else + #define CY_LIB_TRIM_IMO_3MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ) + #define CY_LIB_TRIM_IMO_6MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ) + #define CY_LIB_TRIM_IMO_12MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ) + #define CY_LIB_TRIM_IMO_24MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ) + #define CY_LIB_TRIM_IMO_67MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ) + #define CY_LIB_TRIM_IMO_80MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ) + #define CY_LIB_TRIM_IMO_USB_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_USB) + #define CY_LIB_TRIM_IMO_TR1_PTR ((reg8 *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u)) +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* PLL Registers +*******************************************************************************/ + +/* PLL Configuration Register 0 */ +#define CY_CLK_PLL_CFG0_REG (*(reg8 *) CYREG_FASTCLK_PLL_CFG0) +#define CY_CLK_PLL_CFG0_PTR ( (reg8 *) CYREG_FASTCLK_PLL_CFG0) + +/* PLL Configuration Register 1 */ +#define CY_CLK_PLL_CFG1_REG (*(reg8 *) CYREG_FASTCLK_PLL_CFG1) +#define CY_CLK_PLL_CFG1_PTR ( (reg8 *) CYREG_FASTCLK_PLL_CFG1) + +/* PLL Status Register */ +#define CY_CLK_PLL_SR_REG (*(reg8 *) CYREG_FASTCLK_PLL_SR) +#define CY_CLK_PLL_SR_PTR ( (reg8 *) CYREG_FASTCLK_PLL_SR) + +/* PLL Q-Counter Configuration Register */ +#define CY_CLK_PLL_Q_REG (*(reg8 *) CYREG_FASTCLK_PLL_Q) +#define CY_CLK_PLL_Q_PTR ( (reg8 *) CYREG_FASTCLK_PLL_Q) + +/* PLL P-Counter Configuration Register */ +#define CY_CLK_PLL_P_REG (*(reg8 *) CYREG_FASTCLK_PLL_P) +#define CY_CLK_PLL_P_PTR ( (reg8 *) CYREG_FASTCLK_PLL_P) + + +/******************************************************************************* +* External MHz Crystal Oscillator Registers +*******************************************************************************/ + +/* External MHz Crystal Oscillator Status and Control Register */ +#define CY_CLK_XMHZ_CSR_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CSR) +#define CY_CLK_XMHZ_CSR_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CSR) + +/* External MHz Crystal Oscillator Configuration Register 0 */ +#define CY_CLK_XMHZ_CFG0_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CFG0) +#define CY_CLK_XMHZ_CFG0_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CFG0) + +/* External MHz Crystal Oscillator Configuration Register 1 */ +#define CY_CLK_XMHZ_CFG1_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CFG1) +#define CY_CLK_XMHZ_CFG1_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CFG1) + + +/******************************************************************************* +* External 32kHz Crystal Oscillator Registers +*******************************************************************************/ + +/* 32 kHz Watch Crystal Oscillator Trim Register */ +#define CY_CLK_XTAL32_TR_REG (*(reg8 *) CYREG_X32_TR) +#define CY_CLK_XTAL32_TR_PTR ( (reg8 *) CYREG_X32_TR) + +/* External 32kHz Crystal Oscillator Test Register */ +#define CY_CLK_XTAL32_TST_REG (*(reg8 *) CYREG_SLOWCLK_X32_TST) +#define CY_CLK_XTAL32_TST_PTR ( (reg8 *) CYREG_SLOWCLK_X32_TST) + +/* External 32kHz Crystal Oscillator Control Register */ +#define CY_CLK_XTAL32_CR_REG (*(reg8 *) CYREG_SLOWCLK_X32_CR) +#define CY_CLK_XTAL32_CR_PTR ( (reg8 *) CYREG_SLOWCLK_X32_CR) + +/* External 32kHz Crystal Oscillator Configuration Register */ +#define CY_CLK_XTAL32_CFG_REG (*(reg8 *) CYREG_SLOWCLK_X32_CFG) +#define CY_CLK_XTAL32_CFG_PTR ( (reg8 *) CYREG_SLOWCLK_X32_CFG) + + +/******************************************************************************* +* Watchdog Timer Registers +*******************************************************************************/ + +/* Watchdog Timer Configuration Register */ +#define CY_WDT_CFG_REG (*(reg8 *) CYREG_PM_WDT_CFG) +#define CY_WDT_CFG_PTR ( (reg8 *) CYREG_PM_WDT_CFG) + +/* Watchdog Timer Control Register */ +#define CY_WDT_CR_REG (*(reg8 *) CYREG_PM_WDT_CR) +#define CY_WDT_CR_PTR ( (reg8 *) CYREG_PM_WDT_CR) + + +/******************************************************************************* +* LVI/HVI Registers +*******************************************************************************/ + +#define CY_VD_LVI_TRIP_REG (* (reg8 *) CYREG_RESET_CR0) +#define CY_VD_LVI_TRIP_PTR ( (reg8 *) CYREG_RESET_CR0) + +#define CY_VD_LVI_HVI_CONTROL_REG (* (reg8 *) CYREG_RESET_CR1) +#define CY_VD_LVI_HVI_CONTROL_PTR ( (reg8 *) CYREG_RESET_CR1) + +#define CY_VD_PRES_CONTROL_REG (* (reg8 *) CYREG_RESET_CR3) +#define CY_VD_PRES_CONTROL_PTR ( (reg8 *) CYREG_RESET_CR3) + +#define CY_VD_PERSISTENT_STATUS_REG (* (reg8 *) CYREG_RESET_SR0) +#define CY_VD_PERSISTENT_STATUS_PTR ( (reg8 *) CYREG_RESET_SR0) + +#define CY_VD_RT_STATUS_REG (* (reg8 *) CYREG_RESET_SR2) +#define CY_VD_RT_STATUS_PTR ( (reg8 *) CYREG_RESET_SR2) + + +/******************************************************************************* +* Variable VDDA +*******************************************************************************/ +#if(CYDEV_VARIABLE_VDDA == 1) + + /* Active Power Mode Configuration Register 9 */ + #define CY_LIB_ACT_CFG9_REG (* (reg8 *) CYREG_PM_ACT_CFG9 ) + #define CY_LIB_ACT_CFG9_PTR ( (reg8 *) CYREG_PM_ACT_CFG9 ) + + /* Switched Capacitor 0 Boost Clock Selection Register */ + #define CY_LIB_SC0_BST_REG (* (reg8 *) CYREG_SC0_BST ) + #define CY_LIB_SC0_BST_PTR ( (reg8 *) CYREG_SC0_BST ) + + /* Switched Capacitor 1 Boost Clock Selection Register */ + #define CY_LIB_SC1_BST_REG (* (reg8 *) CYREG_SC1_BST ) + #define CY_LIB_SC1_BST_PTR ( (reg8 *) CYREG_SC1_BST ) + + /* Switched Capacitor 2 Boost Clock Selection Register */ + #define CY_LIB_SC2_BST_REG (* (reg8 *) CYREG_SC2_BST ) + #define CY_LIB_SC2_BST_PTR ( (reg8 *) CYREG_SC2_BST ) + + /* Switched Capacitor 3 Boost Clock Selection Register */ + #define CY_LIB_SC3_BST_REG (* (reg8 *) CYREG_SC3_BST ) + #define CY_LIB_SC3_BST_PTR ( (reg8 *) CYREG_SC3_BST ) + + /* Switched Cap Miscellaneous Control Register */ + #define CY_LIB_SC_MISC_REG (* (reg8 *) CYREG_SC_MISC ) + #define CY_LIB_SC_MISC_PTR ( (reg8 *) CYREG_SC_MISC ) + +#endif /* (CYDEV_VARIABLE_VDDA == 1) */ + + +/******************************************************************************* +* Clock Distribution Registers +*******************************************************************************/ + +/* Analog Clock Mask Register */ +#define CY_LIB_CLKDIST_AMASK_REG (* (reg8 *) CYREG_CLKDIST_AMASK ) +#define CY_LIB_CLKDIST_AMASK_PTR ( (reg8 *) CYREG_CLKDIST_AMASK ) + +/* Digital Clock Mask Register */ +#define CY_LIB_CLKDIST_DMASK_REG (*(reg8 *) CYREG_CLKDIST_DMASK) +#define CY_LIB_CLKDIST_DMASK_PTR ( (reg8 *) CYREG_CLKDIST_DMASK) + +/* CLK_BUS Configuration Register */ +#define CY_LIB_CLKDIST_BCFG2_REG (*(reg8 *) CYREG_CLKDIST_BCFG2) +#define CY_LIB_CLKDIST_BCFG2_PTR ( (reg8 *) CYREG_CLKDIST_BCFG2) + +/* LSB Shadow Divider Value Register */ +#define CY_LIB_CLKDIST_WRK_LSB_REG (*(reg8 *) CYREG_CLKDIST_WRK0) +#define CY_LIB_CLKDIST_WRK_LSB_PTR ( (reg8 *) CYREG_CLKDIST_WRK0) + +/* MSB Shadow Divider Value Register */ +#define CY_LIB_CLKDIST_WRK_MSB_REG (*(reg8 *) CYREG_CLKDIST_WRK1) +#define CY_LIB_CLKDIST_WRK_MSB_PTR ( (reg8 *) CYREG_CLKDIST_WRK1) + +/* LOAD Register */ +#define CY_LIB_CLKDIST_LD_REG (*(reg8 *) CYREG_CLKDIST_LD) +#define CY_LIB_CLKDIST_LD_PTR ( (reg8 *) CYREG_CLKDIST_LD) + +/* CLK_BUS LSB Divider Value Register */ +#define CY_LIB_CLKDIST_BCFG_LSB_REG (*(reg8 *) CYREG_CLKDIST_BCFG0) +#define CY_LIB_CLKDIST_BCFG_LSB_PTR ( (reg8 *) CYREG_CLKDIST_BCFG0) + +/* CLK_BUS MSB Divider Value Register */ +#define CY_LIB_CLKDIST_BCFG_MSB_REG (*(reg8 *) CYREG_CLKDIST_BCFG1) +#define CY_LIB_CLKDIST_BCFG_MSB_PTR ( (reg8 *) CYREG_CLKDIST_BCFG1) + +/* Master clock (clk_sync_d) Divider Value Register */ +#define CY_LIB_CLKDIST_MSTR0_REG (*(reg8 *) CYREG_CLKDIST_MSTR0) +#define CY_LIB_CLKDIST_MSTR0_PTR ( (reg8 *) CYREG_CLKDIST_MSTR0) + +/* Master (clk_sync_d) Configuration Register/CPU Divider Value */ +#define CY_LIB_CLKDIST_MSTR1_REG (*(reg8 *) CYREG_CLKDIST_MSTR1) +#define CY_LIB_CLKDIST_MSTR1_PTR ( (reg8 *) CYREG_CLKDIST_MSTR1) + +/* Internal Main Oscillator Control Register */ +#define CY_LIB_FASTCLK_IMO_CR_REG (*(reg8 *) CYREG_FASTCLK_IMO_CR) +#define CY_LIB_FASTCLK_IMO_CR_PTR ( (reg8 *) CYREG_FASTCLK_IMO_CR) + +/* Configuration Register CR */ +#define CY_LIB_CLKDIST_CR_REG (*(reg8 *) CYREG_CLKDIST_CR) +#define CY_LIB_CLKDIST_CR_PTR ( (reg8 *) CYREG_CLKDIST_CR) + +/* Internal Low-speed Oscillator Control Register 0 */ +#define CY_LIB_SLOWCLK_ILO_CR0_REG (*(reg8 *) CYREG_SLOWCLK_ILO_CR0) +#define CY_LIB_SLOWCLK_ILO_CR0_PTR ( (reg8 *) CYREG_SLOWCLK_ILO_CR0) + + +/******************************************************************************* +* Interrupt Registers +*******************************************************************************/ + +#if(CY_PSOC5) + + /* Interrupt Vector Table Offset */ + #define CY_INT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET) + + /* Interrupt Priority 0-31 */ + #define CY_INT_PRIORITY_REG (* (reg8 *) CYREG_NVIC_PRI_0) + #define CY_INT_PRIORITY_PTR ( (reg8 *) CYREG_NVIC_PRI_0) + + /* Interrupt Enable Set 0-31 */ + #define CY_INT_ENABLE_REG (* (reg32 *) CYREG_NVIC_SETENA0) + #define CY_INT_ENABLE_PTR ( (reg32 *) CYREG_NVIC_SETENA0) + + /* Interrupt Enable Clear 0-31 */ + #define CY_INT_CLEAR_REG (* (reg32 *) CYREG_NVIC_CLRENA0) + #define CY_INT_CLEAR_PTR ( (reg32 *) CYREG_NVIC_CLRENA0) + + /* Interrupt Pending Set 0-31 */ + #define CY_INT_SET_PEND_REG (* (reg32 *) CYREG_NVIC_SETPEND0) + #define CY_INT_SET_PEND_PTR ( (reg32 *) CYREG_NVIC_SETPEND0) + + /* Interrupt Pending Clear 0-31 */ + #define CY_INT_CLR_PEND_REG (* (reg32 *) CYREG_NVIC_CLRPEND0) + #define CY_INT_CLR_PEND_PTR ( (reg32 *) CYREG_NVIC_CLRPEND0) + + /* Cache Control Register */ + #define CY_CACHE_CONTROL_REG (* (reg16 *) CYREG_CACHE_CC_CTL ) + #define CY_CACHE_CONTROL_PTR ( (reg16 *) CYREG_CACHE_CC_CTL ) + +#elif (CY_PSOC3) + + /* Interrupt Address Vector registers */ + #define CY_INT_VECT_TABLE ((cyisraddress CYXDATA *) CYREG_INTC_VECT_MBASE) + + /* Interrrupt Controller Priority Registers */ + #define CY_INT_PRIORITY_REG (* (reg8 *) CYREG_INTC_PRIOR0) + #define CY_INT_PRIORITY_PTR ( (reg8 *) CYREG_INTC_PRIOR0) + + /* Interrrupt Controller Set Enable Registers */ + #define CY_INT_ENABLE_REG (* (reg8 *) CYREG_INTC_SET_EN0) + #define CY_INT_ENABLE_PTR ( (reg8 *) CYREG_INTC_SET_EN0) + + #define CY_INT_SET_EN0_REG (* (reg8 *) CYREG_INTC_SET_EN0) + #define CY_INT_SET_EN0_PTR ( (reg8 *) CYREG_INTC_SET_EN0) + + #define CY_INT_SET_EN1_REG (* (reg8 *) CYREG_INTC_SET_EN1) + #define CY_INT_SET_EN1_PTR ( (reg8 *) CYREG_INTC_SET_EN1) + + #define CY_INT_SET_EN2_REG (* (reg8 *) CYREG_INTC_SET_EN2) + #define CY_INT_SET_EN2_PTR ( (reg8 *) CYREG_INTC_SET_EN2) + + #define CY_INT_SET_EN3_REG (* (reg8 *) CYREG_INTC_SET_EN3) + #define CY_INT_SET_EN3_PTR ( (reg8 *) CYREG_INTC_SET_EN3) + + /* Interrrupt Controller Clear Enable Registers */ + #define CY_INT_CLEAR_REG (* (reg8 *) CYREG_INTC_CLR_EN0) + #define CY_INT_CLEAR_PTR ( (reg8 *) CYREG_INTC_CLR_EN0) + + #define CY_INT_CLR_EN0_REG (* (reg8 *) CYREG_INTC_CLR_EN0) + #define CY_INT_CLR_EN0_PTR ( (reg8 *) CYREG_INTC_CLR_EN0) + + #define CY_INT_CLR_EN1_REG (* (reg8 *) CYREG_INTC_CLR_EN1) + #define CY_INT_CLR_EN1_PTR ( (reg8 *) CYREG_INTC_CLR_EN1) + + #define CY_INT_CLR_EN2_REG (* (reg8 *) CYREG_INTC_CLR_EN2) + #define CY_INT_CLR_EN2_PTR ( (reg8 *) CYREG_INTC_CLR_EN2) + + #define CY_INT_CLR_EN3_REG (* (reg8 *) CYREG_INTC_CLR_EN3) + #define CY_INT_CLR_EN3_PTR ( (reg8 *) CYREG_INTC_CLR_EN3) + + + /* Interrrupt Controller Set Pend Registers */ + #define CY_INT_SET_PEND_REG (* (reg8 *) CYREG_INTC_SET_PD0) + #define CY_INT_SET_PEND_PTR ( (reg8 *) CYREG_INTC_SET_PD0) + + /* Interrrupt Controller Clear Pend Registers */ + #define CY_INT_CLR_PEND_REG (* (reg8 *) CYREG_INTC_CLR_PD0) + #define CY_INT_CLR_PEND_PTR ( (reg8 *) CYREG_INTC_CLR_PD0) + + + /* Access Interrupt Controller Registers based on interrupt number */ + #define CY_INT_SET_EN_INDX_PTR(number) ((reg8 *) (CYREG_INTC_SET_EN0 + (((number) & CY_INT_NUMBER_MASK) >> 3u))) + #define CY_INT_CLR_EN_INDX_PTR(number) ((reg8 *) (CYREG_INTC_CLR_EN0 + (((number) & CY_INT_NUMBER_MASK) >> 3u))) + #define CY_INT_CLR_PEND_INDX_PTR(number) ((reg8 *) (CYREG_INTC_CLR_PD0 + (((number) & CY_INT_NUMBER_MASK) >> 3u))) + #define CY_INT_SET_PEND_INDX_PTR(number) ((reg8 *) (CYREG_INTC_SET_PD0 + (((number) & CY_INT_NUMBER_MASK) >> 3u))) + +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* Macro Name: CyAssert +******************************************************************************** +* Summary: +* Macro that evaluates the expression and if it is false (evaluates to 0) then +* the processor is halted. +* +* This macro is evaluated unless NDEBUG is defined. +* +* If NDEBUG is defined, then no code is generated for this macro. NDEBUG is +* defined by default for a Release build setting and not defined for a Debug +* build setting. +* +* Parameters: +* expr: Logical expression. Asserts if false. +* +* Return: +* None +* +*******************************************************************************/ +#if !defined(NDEBUG) + #define CYASSERT(x) { \ + if(!(x)) \ + { \ + CyHalt((uint8) 0u); \ + } \ + } +#else + #define CYASSERT(x) +#endif /* !defined(NDEBUG) */ + + +/* Reset register fields of RESET_SR0 (CyResetStatus) */ +#define CY_RESET_LVID (0x01u) +#define CY_RESET_LVIA (0x02u) +#define CY_RESET_HVIA (0x04u) +#define CY_RESET_WD (0x08u) +#define CY_RESET_SW (0x20u) +#define CY_RESET_GPIO0 (0x40u) +#define CY_RESET_GPIO1 (0x80u) + + +/* Interrrupt Controller Configuration and Status Register */ +#if(CY_PSOC3) + #define INTERRUPT_CSR ((reg8 *) CYREG_INTC_CSR_EN) + #define DISABLE_IRQ_SET ((uint8)(0x01u << 1u)) /* INTC_CSR_EN */ + #define INTERRUPT_DISABLE_IRQ {*INTERRUPT_CSR |= DISABLE_IRQ_SET;} + #define INTERRUPT_ENABLE_IRQ {*INTERRUPT_CSR = (uint8)(~DISABLE_IRQ_SET);} +#endif /* (CY_PSOC3) */ + + +#if defined(__ARMCC_VERSION) + #define CyGlobalIntEnable {__enable_irq();} + #define CyGlobalIntDisable {__disable_irq();} +#elif defined(__GNUC__) || defined (__ICCARM__) + #define CyGlobalIntEnable {__asm("CPSIE i");} + #define CyGlobalIntDisable {__asm("CPSID i");} +#elif defined(__C51__) + #define CyGlobalIntEnable {\ + EA = 1u; \ + INTERRUPT_ENABLE_IRQ\ + } + + #define CyGlobalIntDisable {\ + INTERRUPT_DISABLE_IRQ; \ + CY_NOP; \ + EA = 0u;\ + } +#else + #error No compiler toolchain defined + #define CyGlobalIntEnable + #define CyGlobalIntDisable +#endif /* (__ARMCC_VERSION) */ + + +#ifdef CYREG_MLOGIC_CPU_SCR_CPU_SCR + #define CYDEV_HALT_CPU CY_SET_REG8(CYREG_MLOGIC_CPU_SCR_CPU_SCR, 0x01u) +#else + #define CYDEV_HALT_CPU CY_SET_REG8(CYREG_MLOGIC_CPU_SCR, 0x01u) +#endif /* (CYREG_MLOGIC_CPU_SCR_CPU_SCR) */ + + +#ifdef CYREG_MLOGIC_REV_ID_REV_ID + #define CYDEV_CHIP_REV_ACTUAL (CY_GET_REG8(CYREG_MLOGIC_REV_ID_REV_ID)) +#else + #define CYDEV_CHIP_REV_ACTUAL (CY_GET_REG8(CYREG_MLOGIC_REV_ID)) +#endif /* (CYREG_MLOGIC_REV_ID_REV_ID) */ + + +/******************************************************************************* +* System API constants +*******************************************************************************/ +#define CY_CACHE_CONTROL_FLUSH (0x0004u) +#define CY_LIB_RESET_CR2_RESET (0x01u) + + +/******************************************************************************* +* Interrupt API constants +*******************************************************************************/ +#if(CY_PSOC5) + + #define CY_INT_IRQ_BASE (16u) + +#elif (CY_PSOC3) + + #define CY_INT_IRQ_BASE (0u) + +#endif /* (CY_PSOC5) */ + +/* Valid range of interrupt 0-31 */ +#define CY_INT_NUMBER_MAX (31u) + +/* Valid range of system interrupt 0-15 */ +#define CY_INT_SYS_NUMBER_MAX (15u) + +/* Valid range of system priority 0-7 */ +#define CY_INT_PRIORITY_MAX (7u) + +/* Mask to get valid range of interrupt 0-31 */ +#define CY_INT_NUMBER_MASK (0x1Fu) + +/* Mask to get valid range of system priority 0-7 */ +#define CY_INT_PRIORITY_MASK (0x7u) + +/* Mask to get valid range of system interrupt 0-15 */ +#define CY_INT_SYS_NUMBER_MASK (0xFu) + + +/******************************************************************************* +* Interrupt Macros +*******************************************************************************/ + +#if(CY_PSOC5) + + /******************************************************************************* + * Macro Name: CyIntEnable + ******************************************************************************** + * + * Summary: + * Enables the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number + * + * Return: + * None + * + *******************************************************************************/ + #define CyIntEnable(number) CY_SET_REG32(CY_INT_ENABLE_PTR, ((uint32)((uint32)1u << (0x1Fu & (number))))) + + /******************************************************************************* + * Macro Name: CyIntDisable + ******************************************************************************** + * + * Summary: + * Disables the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number. + * + * Return: + * None + * + *******************************************************************************/ + #define CyIntDisable(number) CY_SET_REG32(CY_INT_CLEAR_PTR, ((uint32)((uint32)1u << (0x1Fu & (number))))) + + + /******************************************************************************* + * Macro Name: CyIntSetPending + ******************************************************************************** + * + * Summary: + * Forces the specified interrupt number to be pending. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number. + * + * Return: + * None + * + *******************************************************************************/ + #define CyIntSetPending(number) CY_SET_REG32(CY_INT_SET_PEND_PTR, ((uint32)((uint32)1u << (0x1Fu & (number))))) + + + /******************************************************************************* + * Macro Name: CyIntClearPending + ******************************************************************************** + * + * Summary: + * Clears any pending interrupt for the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number. + * + * Return: + * None + * + *******************************************************************************/ + #define CyIntClearPending(number) CY_SET_REG32(CY_INT_CLR_PEND_PTR, ((uint32)((uint32)1u << (0x1Fu & (number))))) + + +#else /* PSoC3 */ + + + /******************************************************************************* + * Macro Name: CyIntEnable + ******************************************************************************** + * + * Summary: + * Enables the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number + * + * Return: + * None + * + *******************************************************************************/ + #define CyIntEnable(number) CY_SET_REG8(CY_INT_SET_EN_INDX_PTR((number)), \ + ((uint8)(1u << (0x07u & (number))))) + + + /******************************************************************************* + * Macro Name: CyIntDisable + ******************************************************************************** + * + * Summary: + * Disables the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number. + * + * Return: + * None + * + *******************************************************************************/ + #define CyIntDisable(number) CY_SET_REG8(CY_INT_CLR_EN_INDX_PTR((number)), \ + ((uint8)(1u << (0x07u & (number))))) + + + /******************************************************************************* + * Macro Name: CyIntSetPending + ******************************************************************************** + * + * Summary: + * Forces the specified interrupt number to be pending. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number. + * + * Return: + * None + * + *******************************************************************************/ + #define CyIntSetPending(number) CY_SET_REG8(CY_INT_SET_PEND_INDX_PTR((number)), \ + ((uint8)(1u << (0x07u & (number))))) + + + /******************************************************************************* + * Macro Name: CyIntClearPending + ******************************************************************************** + * Summary: + * Clears any pending interrupt for the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number. + * + * Return: + * None + * + *******************************************************************************/ + #define CyIntClearPending(number) CY_SET_REG8(CY_INT_CLR_PEND_INDX_PTR((number)), \ + ((uint8)(1u << (0x07u & (number))))) + +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used. +*******************************************************************************/ +#define CYGlobalIntEnable CyGlobalIntEnable +#define CYGlobalIntDisable CyGlobalIntDisable + +#define cymemset(s,c,n) memset((s),(c),(n)) +#define cymemcpy(d,s,n) memcpy((d),(s),(n)) + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from cy_boot 3.0 +*******************************************************************************/ +#define MFGCFG_X32_TR_PTR (CY_CLK_XTAL32_TR_PTR) +#define MFGCFG_X32_TR (CY_CLK_XTAL32_TR_REG) +#define SLOWCLK_X32_TST_PTR (CY_CLK_XTAL32_TST_PTR) +#define SLOWCLK_X32_TST (CY_CLK_XTAL32_TST_REG) +#define SLOWCLK_X32_CR_PTR (CY_CLK_XTAL32_CR_PTR) +#define SLOWCLK_X32_CR (CY_CLK_XTAL32_CR_REG) +#define SLOWCLK_X32_CFG_PTR (CY_CLK_XTAL32_CFG_PTR) +#define SLOWCLK_X32_CFG (CY_CLK_XTAL32_CFG_REG) + +#define X32_CONTROL_ANA_STAT (CY_CLK_XTAL32_CR_ANA_STAT) +#define X32_CONTROL_DIG_STAT (0x10u) +#define X32_CONTROL_LPM (CY_CLK_XTAL32_CR_LPM) +#define X32_CONTROL_LPM_POSITION (1u) +#define X32_CONTROL_X32EN (CY_CLK_XTAL32_CR_EN) +#define X32_CONTROL_PDBEN (CY_CLK_XTAL32_CR_PDBEN) +#define X32_TR_DPMODE (CY_CLK_XTAL32_TR_STARTUP) +#define X32_TR_CLEAR (CY_CLK_XTAL32_TR_POWERDOWN) +#define X32_TR_HPMODE (CY_CLK_XTAL32_TR_HIGH_POWER) +#define X32_TR_LPMODE (CY_CLK_XTAL32_TR_LOW_POWER) +#define X32_TST_SETALL (CY_CLK_XTAL32_TST_DEFAULT) +#define X32_CFG_LP_BITS_MASK (CY_CLK_XTAL32_CFG_LP_MASK) +#define X32_CFG_LP_DEFAULT (CY_CLK_XTAL32_CFG_LP_DEFAULT) +#define X32_CFG_LOWPOWERMODE (0x80u) +#define X32_CFG_LP_LOWPOWER (0x8u) +#define CY_X32_HIGHPOWER_MODE (0u) +#define CY_X32_LOWPOWER_MODE (1u) +#define CY_XTAL32K_DIG_STAT (0x10u) +#define CY_XTAL32K_STAT_FIELDS (0x30u) +#define CY_XTAL32K_DIG_STAT_UNSTABLE (0u) +#define CY_XTAL32K_ANA_STAT_UNSTABLE (0x0u) +#define CY_XTAL32K_STATUS (0x20u) + +#define FASTCLK_XMHZ_CSR_PTR (CY_CLK_XMHZ_CSR_PTR) +#define FASTCLK_XMHZ_CSR (CY_CLK_XMHZ_CSR_REG) +#define FASTCLK_XMHZ_CFG0_PTR (CY_CLK_XMHZ_CFG0_PTR) +#define FASTCLK_XMHZ_CFG0 (CY_CLK_XMHZ_CFG0_REG) +#define FASTCLK_XMHZ_CFG1_PTR (CY_CLK_XMHZ_CFG1_PTR) +#define FASTCLK_XMHZ_CFG1 (CY_CLK_XMHZ_CFG1_REG) +#define FASTCLK_XMHZ_GAINMASK (CY_CLK_XMHZ_CFG0_XCFG_MASK) +#define FASTCLK_XMHZ_VREFMASK (CY_CLK_XMHZ_CFG1_VREF_FB_MASK) +#define FASTCLK_XMHZ_VREF_WD_MASK (CY_CLK_XMHZ_CFG1_VREF_WD_MASK) +#define XMHZ_CONTROL_ENABLE (CY_CLK_XMHZ_CSR_ENABLE) +#define X32_CONTROL_XERR_MASK (CY_CLK_XMHZ_CSR_XERR) +#define X32_CONTROL_XERR_DIS (CY_CLK_XMHZ_CSR_XFB) +#define X32_CONTROL_XERR_POSITION (7u) +#define X32_CONTROL_FAULT_RECOVER (CY_CLK_XMHZ_CSR_XPROT) + +#define CYWDT_CFG (CY_WDT_CFG_PTR) +#define CYWDT_CR (CY_WDT_CR_PTR) + +#define CYWDT_TICKS_MASK (CY_WDT_CFG_INTERVAL_MASK) +#define CYWDT_RESET (CY_WDT_CFG_CTW_RESET) +#define CYWDT_LPMODE_SHIFT (CY_WDT_CFG_LPMODE_SHIFT) +#define CYWDT_LPMODE_MASK (CY_WDT_CFG_LPMODE_MASK) +#define CYWDT_ENABLE_BIT (CY_WDT_CFG_WDR_EN) + +#define FASTCLK_PLL_CFG0_PTR (CY_CLK_PLL_CFG0_PTR) +#define FASTCLK_PLL_CFG0 (CY_CLK_PLL_CFG0_REG) +#define FASTCLK_PLL_SR_PTR (CY_CLK_PLL_SR_PTR) +#define FASTCLK_PLL_SR (CY_CLK_PLL_SR_REG) + +#define MAX_FASTCLK_PLL_Q_VALUE (CY_CLK_PLL_MAX_Q_VALUE) +#define MIN_FASTCLK_PLL_Q_VALUE (CY_CLK_PLL_MIN_Q_VALUE) +#define MIN_FASTCLK_PLL_P_VALUE (CY_CLK_PLL_MIN_P_VALUE) +#define MIN_FASTCLK_PLL_CUR_VALUE (CY_CLK_PLL_MIN_CUR_VALUE) +#define MAX_FASTCLK_PLL_CUR_VALUE (CY_CLK_PLL_MAX_CUR_VALUE) + +#define PLL_CONTROL_ENABLE (CY_CLK_PLL_ENABLE) +#define PLL_STATUS_LOCK (CY_CLK_PLL_LOCK_STATUS) +#define PLL_STATUS_ENABLED (CY_CLK_PLL_ENABLE) +#define PLL_CURRENT_POSITION (CY_CLK_PLL_CURRENT_POSITION) +#define PLL_VCO_GAIN_2 (2u) + +#define FASTCLK_PLL_Q_PTR (CY_CLK_PLL_Q_PTR) +#define FASTCLK_PLL_Q (CY_CLK_PLL_Q_REG) +#define FASTCLK_PLL_P_PTR (CY_CLK_PLL_P_PTR) +#define FASTCLK_PLL_P (CY_CLK_PLL_P_REG) +#define FASTCLK_PLL_CFG1_PTR (CY_CLK_PLL_CFG1_REG) +#define FASTCLK_PLL_CFG1 (CY_CLK_PLL_CFG1_REG) + +#define CY_VD_PRESISTENT_STATUS_REG (CY_VD_PERSISTENT_STATUS_REG) +#define CY_VD_PRESISTENT_STATUS_PTR (CY_VD_PERSISTENT_STATUS_PTR) + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from cy_boot 3.20 +*******************************************************************************/ + +#if(CY_PSOC5) + + #define CYINT_IRQ_BASE (CY_INT_IRQ_BASE) + + #define CYINT_VECT_TABLE (CY_INT_VECT_TABLE) + #define CYINT_PRIORITY (CY_INT_PRIORITY_PTR) + #define CYINT_ENABLE (CY_INT_ENABLE_PTR) + #define CYINT_CLEAR (CY_INT_CLEAR_PTR) + #define CYINT_SET_PEND (CY_INT_SET_PEND_PTR) + #define CYINT_CLR_PEND (CY_INT_CLR_PEND_PTR) + #define CACHE_CC_CTL (CY_CACHE_CONTROL_PTR) + +#elif (CY_PSOC3) + + #define CYINT_IRQ_BASE (CY_INT_IRQ_BASE) + + #define CYINT_VECT_TABLE (CY_INT_VECT_TABLE) + #define CYINT_PRIORITY (CY_INT_PRIORITY_PTR) + #define CYINT_ENABLE (CY_INT_ENABLE_PTR) + #define CYINT_CLEAR (CY_INT_CLEAR_PTR) + #define CYINT_SET_PEND (CY_INT_SET_PEND_PTR) + #define CYINT_CLR_PEND (CY_INT_CLR_PEND_PTR) + +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from cy_boot 3.30 +*******************************************************************************/ +#define BUS_AMASK_CLEAR (0xF0u) +#define BUS_DMASK_CLEAR (0x00u) +#define CLKDIST_LD_LOAD_SET (0x01u) +#define CLKDIST_WRK0_MASK_SET (0x80u) /* Enable shadow loads */ +#define MASTERCLK_DIVIDER_VALUE (7u) +#define CLKDIST_BCFG2_SSS_SET (0x40u) /* Sync source is same frequency */ +#define MASTER_CLK_SRC_CLEAR (0xFCu) +#define IMO_DOUBLER_ENABLE (0x10u) +#define CLOCK_IMO_IMO (0x20u) +#define CLOCK_IMO2X_XTAL (0x40u) +#define CLOCK_IMO_RANGE_CLEAR (0xF8u) +#define CLOCK_CONTROL_DIST_MASK (0xFCu) + + +#define CLKDIST_AMASK (*(reg8 *) CYREG_CLKDIST_AMASK) +#define CLKDIST_AMASK_PTR ( (reg8 *) CYREG_CLKDIST_AMASK) +#define CLKDIST_DMASK_PTR ( (reg8 *) CYREG_CLKDIST_DMASK) +#define CLKDIST_DMASK (*(reg8 *) CYREG_CLKDIST_DMASK) +#define CLKDIST_BCFG2_PTR ( (reg8 *) CYREG_CLKDIST_BCFG2) +#define CLKDIST_BCFG2 (*(reg8 *) CYREG_CLKDIST_BCFG2) +#define CLKDIST_WRK0_PTR ( (reg8 *) CYREG_CLKDIST_WRK0) +#define CLKDIST_WRK0 (*(reg8 *) CYREG_CLKDIST_WRK0) +#define CLKDIST_LD_PTR ( (reg8 *) CYREG_CLKDIST_LD) +#define CLKDIST_LD (*(reg8 *) CYREG_CLKDIST_LD) +#define CLKDIST_BCFG0_PTR ( (reg8 *) CYREG_CLKDIST_BCFG0) +#define CLKDIST_BCFG0 (*(reg8 *) CYREG_CLKDIST_BCFG0) +#define CLKDIST_MSTR0_PTR ( (reg8 *) CYREG_CLKDIST_MSTR0) +#define CLKDIST_MSTR0 (*(reg8 *) CYREG_CLKDIST_MSTR0) +#define FASTCLK_IMO_CR_PTR ( (reg8 *) CYREG_FASTCLK_IMO_CR) +#define FASTCLK_IMO_CR (*(reg8 *) CYREG_FASTCLK_IMO_CR) +#define CLKDIST_CR_PTR ( (reg8 *) CYREG_CLKDIST_CR) +#define CLKDIST_CR (*(reg8 *) CYREG_CLKDIST_CR) + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from cy_boot 3.50 +*******************************************************************************/ +#define IMO_PM_ENABLE (0x10u) +#define PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0) +#define PM_ACT_CFG0 (*(reg8 *) CYREG_PM_ACT_CFG0) +#define SLOWCLK_ILO_CR0_PTR ( (reg8 *) CYREG_SLOWCLK_ILO_CR0) +#define SLOWCLK_ILO_CR0 (*(reg8 *) CYREG_SLOWCLK_ILO_CR0) +#define ILO_CONTROL_PD_MODE (0x10u) +#define ILO_CONTROL_PD_POSITION (4u) +#define ILO_CONTROL_1KHZ_ON (0x02u) +#define ILO_CONTROL_100KHZ_ON (0x04u) +#define ILO_CONTROL_33KHZ_ON (0x20u) +#define PM_TW_CFG0_PTR ( (reg8 *) CYREG_PM_TW_CFG0) +#define PM_TW_CFG0 (*(reg8 *) CYREG_PM_TW_CFG0) +#define PM_TW_CFG2_PTR ( (reg8 *) CYREG_PM_TW_CFG2) +#define PM_TW_CFG2 (*(reg8 *) CYREG_PM_TW_CFG2) +#define RESET_CR2 ((reg8 *) CYREG_RESET_CR2) +#define FASTCLK_IMO_USBCLK_ON_SET (0x40u) +#define CLOCK_IMO_3MHZ_VALUE (0x03u) +#define CLOCK_IMO_6MHZ_VALUE (0x01u) +#define CLOCK_IMO_12MHZ_VALUE (0x00u) +#define CLOCK_IMO_24MHZ_VALUE (0x02u) +#define CLOCK_IMO_48MHZ_VALUE (0x04u) +#define CLOCK_IMO_62MHZ_VALUE (0x05u) +#define CLOCK_IMO_74MHZ_VALUE (0x06u) +#define CLKDIST_DIV_POSITION (4u) +#define CLKDIST_MSTR1_DIV_CLEAR (0x0Fu) +#define SFR_USER_CPUCLK_DIV_MASK (0x0Fu) +#define CLOCK_USB_ENABLE (0x02u) +#define CLOCK_IMO_OUT_X2 (0x10u) +#define CLOCK_IMO_OUT_X1 ((uint8)(~CLOCK_IMO_OUT_X2)) +#define CLOCK_IMO2X_ECO ((uint8)(~CLOCK_IMO2X_DSI)) +#define USB_CLKDIST_CONFIG_MASK (0x03u) +#define USB_CLK_IMO2X (0x00u) +#define USB_CLK_IMO (0x01u) +#define USB_CLK_PLL (0x02u) +#define USB_CLK_DSI (0x03u) +#define USB_CLK_DIV2_ON (0x04u) +#define USB_CLK_STOP_FLAG (0x00u) +#define USB_CLK_START_FLAG (0x01u) +#define FTW_CLEAR_ALL_BITS (0x00u) +#define FTW_CLEAR_FTW_BITS (0xFCu) +#define FTW_ENABLE (0x01u) +#define PM_STBY_CFG0_PTR ( (reg8 *) CYREG_PM_STBY_CFG0) +#define PM_STBY_CFG0 (*(reg8 *) CYREG_PM_STBY_CFG0) +#define PM_AVAIL_CR2_PTR ( (reg8 *) CYREG_PM_AVAIL_CR2) +#define PM_AVAIL_CR2 (*(reg8 *) CYREG_PM_AVAIL_CR2) +#define CLKDIST_UCFG_PTR ( (reg8 *) CYREG_CLKDIST_UCFG) +#define CLKDIST_UCFG (*(reg8 *) CYREG_CLKDIST_UCFG) +#define CLKDIST_MSTR1_PTR ( (reg8 *) CYREG_CLKDIST_MSTR1) +#define CLKDIST_MSTR1 (*(reg8 *) CYREG_CLKDIST_MSTR1) +#define SFR_USER_CPUCLK_DIV_PTR ((void far *) CYREG_SFR_USER_CPUCLK_DIV) +#define IMO_TR1_PTR ( (reg8 *) CYREG_IMO_TR1) +#define IMO_TR1 (*(reg8 *) CYREG_IMO_TR1) +#define CLOCK_CONTROL ( (reg8 *) CYREG_CLKDIST_CR) +#define CY_USB_CR1_PTR ( (reg8 *) CYREG_USB_CR1 ) +#define CY_USB_CR1 (*(reg8 *) CYREG_USB_CR1 ) +#define USB_CLKDIST_CONFIG_PTR ( (reg8 *) CYREG_CLKDIST_UCFG) +#define USB_CLKDIST_CONFIG (*(reg8 *) CYREG_CLKDIST_UCFG) +#define CY_PM_ACT_CFG5_REG (* (reg8 *) CYREG_PM_ACT_CFG5 ) +#define CY_PM_ACT_CFG5_PTR ( (reg8 *) CYREG_PM_ACT_CFG5 ) +#define CY_PM_STBY_CFG5_REG (* (reg8 *) CYREG_PM_STBY_CFG5 ) +#define CY_PM_STBY_CFG5_PTR ( (reg8 *) CYREG_PM_STBY_CFG5 ) +#if(CY_PSOC3) + #define FLSHID_CUST_TABLES_IMO_3MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ) + #define FLSHID_CUST_TABLES_IMO_6MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ) + #define FLSHID_CUST_TABLES_IMO_12MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ) + #define FLSHID_CUST_TABLES_IMO_24MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ) + #define FLSHID_CUST_TABLES_IMO_67MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ) + #define FLSHID_CUST_TABLES_IMO_80MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ) + #define FLSHID_CUST_TABLES_IMO_USB_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_USB) + #define FLSHID_MFG_CFG_IMO_TR1_PTR ((void far *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u)) + #else + #define FLSHID_CUST_TABLES_IMO_3MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ) + #define FLSHID_CUST_TABLES_IMO_6MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ) + #define FLSHID_CUST_TABLES_IMO_12MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ) + #define FLSHID_CUST_TABLES_IMO_24MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ) + #define FLSHID_CUST_TABLES_IMO_67MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ) + #define FLSHID_CUST_TABLES_IMO_80MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ) + #define FLSHID_CUST_TABLES_IMO_USB_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_USB) + #define FLSHID_MFG_CFG_IMO_TR1_PTR ((reg8 *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u)) +#endif /* (CY_PSOC3) */ + + +#endif /* (CY_BOOT_CYLIB_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CySpc.c b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CySpc.c new file mode 100644 index 00000000..8ea15809 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CySpc.c @@ -0,0 +1,554 @@ +/******************************************************************************* +* File Name: CySpc.c +* Version 4.0 +* +* Description: +* Provides an API for the System Performance Component. +* The SPC functions are not meant to be called directly by the user +* application. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "CySpc.h" + +#define CY_SPC_KEY_ONE (0xB6u) +#define CY_SPC_KEY_TWO(x) ((uint8) (((uint16) 0xD3u) + ((uint16) (x)))) + +/* Command Codes */ +#define CY_SPC_CMD_LD_BYTE (0x00u) +#define CY_SPC_CMD_LD_MULTI_BYTE (0x01u) +#define CY_SPC_CMD_LD_ROW (0x02u) +#define CY_SPC_CMD_RD_BYTE (0x03u) +#define CY_SPC_CMD_RD_MULTI_BYTE (0x04u) +#define CY_SPC_CMD_WR_ROW (0x05u) +#define CY_SPC_CMD_WR_USER_NVL (0x06u) +#define CY_SPC_CMD_PRG_ROW (0x07u) +#define CY_SPC_CMD_ER_SECTOR (0x08u) +#define CY_SPC_CMD_ER_ALL (0x09u) +#define CY_SPC_CMD_RD_HIDDEN (0x0Au) +#define CY_SPC_CMD_PRG_PROTECT (0x0Bu) +#define CY_SPC_CMD_CHECKSUM (0x0Cu) +#define CY_SPC_CMD_DWNLD_ALGORITHM (0x0Du) +#define CY_SPC_CMD_GET_TEMP (0x0Eu) +#define CY_SPC_CMD_GET_ADC (0x0Fu) +#define CY_SPC_CMD_RD_NVL_VOLATILE (0x10u) +#define CY_SPC_CMD_SETUP_TS (0x11u) +#define CY_SPC_CMD_DISABLE_TS (0x12u) +#define CY_SPC_CMD_ER_ROW (0x13u) + +/* Enable bit in Active and Alternate Active mode templates */ +#define PM_SPC_PM_EN (0x08u) + +/* Gate calls to the SPC. */ +uint8 SpcLockState = CY_SPC_UNLOCKED; + + +#if(CY_PSOC5) + + /*************************************************************************** + * The wait-state pipeline must be enabled prior to accessing the SPC + * register interface regardless of CPU frequency. The CySpcLock() saves + * current wait-state pipeline state and enables it. The CySpcUnlock() + * function, which must be called after SPC transaction, restores original + * state. + ***************************************************************************/ + static uint32 spcWaitPipeBypass = 0u; + +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* Function Name: CySpcStart +******************************************************************************** +* Summary: +* Starts the SPC. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CySpcStart(void) +{ + /* Save current global interrupt enable and disable it */ + uint8 interruptState = CyEnterCriticalSection(); + + CY_SPC_PM_ACT_REG |= PM_SPC_PM_EN; + CY_SPC_PM_STBY_REG |= PM_SPC_PM_EN; + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CySpcStop +******************************************************************************** +* Summary: +* Stops the SPC. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CySpcStop(void) +{ + /* Save current global interrupt enable and disable it */ + uint8 interruptState = CyEnterCriticalSection(); + + CY_SPC_PM_ACT_REG &= ((uint8)(~PM_SPC_PM_EN)); + CY_SPC_PM_STBY_REG &= ((uint8)(~PM_SPC_PM_EN)); + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CySpcReadData +******************************************************************************** +* Summary: +* Reads data from the SPC. +* +* Parameters: +* uint8 buffer: +* Address to store data read. +* +* uint8 size: +* Number of bytes to read from the SPC. +* +* Return: +* uint8: +* The number of bytes read from the SPC. +* +*******************************************************************************/ +uint8 CySpcReadData(uint8 buffer[], uint8 size) +{ + uint8 i; + + for(i = 0u; i < size; i++) + { + while(!CY_SPC_DATA_READY) + { + CyDelayUs(1u); + } + buffer[i] = CY_SPC_CPU_DATA_REG; + } + + return(i); +} + + +/******************************************************************************* +* Function Name: CySpcLoadMultiByte +******************************************************************************** +* Summary: +* Loads 1 to 32 bytes of data into the row latch of a Flash/EEPROM array. +* +* Parameters: +* uint8 array: +* Id of the array. +* +* uint16 address: +* Flash/eeprom addrress +* +* uint8* buffer: +* Data to load to the row latch +* +* uint16 number: +* Number bytes to load. +* +* Return: +* CYRET_STARTED +* CYRET_CANCELED +* CYRET_LOCKED +* CYRET_BAD_PARAM +* +*******************************************************************************/ +cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)\ + +{ + cystatus status = CYRET_STARTED; + uint8 i; + + /*************************************************************************** + * Check if number is correct for array. Number must be less than + * 32 for Flash or less than 16 for EEPROM. + ***************************************************************************/ + if(((array < CY_SPC_LAST_FLASH_ARRAYID) && (size < 32u)) || + ((array > CY_SPC_LAST_FLASH_ARRAYID) && (size < 16u))) + { + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_MULTI_BYTE); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_MULTI_BYTE; + + if(CY_SPC_BUSY) + { + CY_SPC_CPU_DATA_REG = array; + CY_SPC_CPU_DATA_REG = 1u & HI8(address); + CY_SPC_CPU_DATA_REG = LO8(address); + CY_SPC_CPU_DATA_REG = ((uint8)(size - 1u)); + + for(i = 0u; i < size; i++) + { + CY_SPC_CPU_DATA_REG = buffer[i]; + } + } + else + { + status = CYRET_CANCELED; + } + } + else + { + status = CYRET_LOCKED; + } + } + else + { + status = CYRET_BAD_PARAM; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcLoadRow +******************************************************************************** +* Summary: +* Loads a row of data into the row latch of a Flash/EEPROM array. +* +* Parameters: +* uint8 array: +* Id of the array. +* +* uint8* buffer: +* Data to be loaded to the row latch +* +* uint8 size: +* The number of data bytes that the SPC expects to be written. Depends on the +* type of the array and, if the array is Flash, whether ECC is being enabled +* or not. There are following values: flash row latch size with ECC enabled, +* flash row latch size with ECC disabled and EEPROM row latch size. +* +* Return: +* CYRET_STARTED +* CYRET_CANCELED +* CYRET_LOCKED +* +*******************************************************************************/ +cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size) +{ + cystatus status = CYRET_STARTED; + uint16 i; + + /* Make sure the SPC is ready to accept command */ + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_ROW); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_ROW; + + /* Make sure the command was accepted */ + if(CY_SPC_BUSY) + { + CY_SPC_CPU_DATA_REG = array; + + for(i = 0u; i < size; i++) + { + CY_SPC_CPU_DATA_REG = buffer[i]; + } + } + else + { + status = CYRET_CANCELED; + } + } + else + { + status = CYRET_LOCKED; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcWriteRow +******************************************************************************** +* Summary: +* Erases then programs a row in Flash/EEPROM with data in row latch. +* +* Parameters: +* uint8 array: +* Id of the array. +* +* uint16 address: +* flash/eeprom addrress +* +* uint8 tempPolarity: +* temperature polarity. +* 1: the Temp Magnitude is interpreted as a positive value +* 0: the Temp Magnitude is interpreted as a negative value +* +* uint8 tempMagnitude: +* temperature magnitude. +* +* Return: +* CYRET_STARTED +* CYRET_CANCELED +* CYRET_LOCKED +* +*******************************************************************************/ +cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\ + +{ + cystatus status = CYRET_STARTED; + + /* Make sure the SPC is ready to accept command */ + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_WR_ROW); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_WR_ROW; + + /* Make sure the command was accepted */ + if(CY_SPC_BUSY) + { + CY_SPC_CPU_DATA_REG = array; + CY_SPC_CPU_DATA_REG = HI8(address); + CY_SPC_CPU_DATA_REG = LO8(address); + CY_SPC_CPU_DATA_REG = tempPolarity; + CY_SPC_CPU_DATA_REG = tempMagnitude; + } + else + { + status = CYRET_CANCELED; + } + } + else + { + status = CYRET_LOCKED; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcEraseSector +******************************************************************************** +* Summary: +* Erases all data in the addressed sector (block of 64 rows). +* +* Parameters: +* uint8 array: +* Id of the array. +* +* uint8 sectorNumber: +* Zero based sector number within Flash/EEPROM array +* +* Return: +* CYRET_STARTED +* CYRET_CANCELED +* CYRET_LOCKED +* +*******************************************************************************/ +cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber) +{ + cystatus status = CYRET_STARTED; + + /* Make sure the SPC is ready to accept command */ + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_ER_SECTOR); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_ER_SECTOR; + + /* Make sure the command was accepted */ + if(CY_SPC_BUSY) + { + CY_SPC_CPU_DATA_REG = array; + CY_SPC_CPU_DATA_REG = sectorNumber; + } + else + { + status = CYRET_CANCELED; + } + } + else + { + status = CYRET_LOCKED; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcGetTemp +******************************************************************************** +* Summary: +* Returns the internal die temperature +* +* Parameters: +* uint8 numSamples: +* Number of samples. Valid values are 1-5, resulting in 2 - 32 samples +* respectively. +* +* uint16 timerPeriod: +* Number of ADC ACLK cycles. A valid 14 bit value is accepted, higher 2 bits +* of 16 bit values are ignored. +* +* uint8 clkDivSelect: +* ADC ACLK clock divide value. Valid values are 2 - 225. +* +* Return: +* CYRET_STARTED +* CYRET_CANCELED +* CYRET_LOCKED +* +*******************************************************************************/ +cystatus CySpcGetTemp(uint8 numSamples) +{ + cystatus status = CYRET_STARTED; + + /* Make sure the SPC is ready to accept command */ + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_GET_TEMP); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_GET_TEMP; + + /* Make sure the command was accepted */ + if(CY_SPC_BUSY) + { + CY_SPC_CPU_DATA_REG = numSamples; + } + else + { + status = CYRET_CANCELED; + } + } + else + { + status = CYRET_LOCKED; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcLock +******************************************************************************** +* Summary: +* Locks the SPC so it can not be used by someone else: +* - Saves wait-pipeline enable state and enable pipeline (PSoC5) +* +* Parameters: +* Note +* +* Return: +* CYRET_SUCCESS - if the resource was free. +* CYRET_LOCKED - if the SPC is in use. +* +*******************************************************************************/ +cystatus CySpcLock(void) +{ + cystatus status = CYRET_LOCKED; + uint8 interruptState; + + /* Enter critical section */ + interruptState = CyEnterCriticalSection(); + + if(CY_SPC_UNLOCKED == SpcLockState) + { + SpcLockState = CY_SPC_LOCKED; + status = CYRET_SUCCESS; + + #if(CY_PSOC5) + + if(0u != (CY_SPC_CPU_WAITPIPE_REG & CY_SPC_CPU_WAITPIPE_BYPASS)) + { + /* Enable pipeline registers */ + CY_SPC_CPU_WAITPIPE_REG &= ((uint32)(~CY_SPC_CPU_WAITPIPE_BYPASS)); + + /* At least 2 NOP instructions are recommended */ + CY_NOP; + CY_NOP; + CY_NOP; + + spcWaitPipeBypass = CY_SPC_CPU_WAITPIPE_BYPASS; + } + + #endif /* (CY_PSOC5) */ + } + + /* Exit critical section */ + CyExitCriticalSection(interruptState); + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcUnlock +******************************************************************************** +* Summary: +* Unlocks the SPC so it can be used by someone else: +* - Restores wait-pipeline enable state (PSoC5) +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CySpcUnlock(void) +{ + uint8 interruptState; + + /* Enter critical section */ + interruptState = CyEnterCriticalSection(); + + /* Release the SPC object */ + SpcLockState = CY_SPC_UNLOCKED; + + #if(CY_PSOC5) + + if(CY_SPC_CPU_WAITPIPE_BYPASS == spcWaitPipeBypass) + { + /* Force to bypass pipeline registers */ + CY_SPC_CPU_WAITPIPE_REG |= CY_SPC_CPU_WAITPIPE_BYPASS; + + /* At least 2 NOP instructions are recommended */ + CY_NOP; + CY_NOP; + CY_NOP; + + spcWaitPipeBypass = 0u; + } + + #endif /* (CY_PSOC5) */ + + /* Exit critical section */ + CyExitCriticalSection(interruptState); +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CySpc.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CySpc.h new file mode 100644 index 00000000..3757e132 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/CySpc.h @@ -0,0 +1,154 @@ +/******************************************************************************* +* File Name: CySpc.c +* Version 4.0 +* +* Description: +* Provides definitions for the System Performance Component API. +* The SPC functions are not meant to be called directly by the user +* application. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYSPC_H) +#define CY_BOOT_CYSPC_H + +#include "cytypes.h" +#include "CyLib.h" +#include "cydevice_trm.h" + + +/*************************************** +* Global Variables +***************************************/ +extern uint8 SpcLockState; + + +/*************************************** +* Function Prototypes +***************************************/ +void CySpcStart(void); +void CySpcStop(void); +uint8 CySpcReadData(uint8 buffer[], uint8 size); +cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)\ +; +cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size); +cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\ +; +cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber); +cystatus CySpcGetTemp(uint8 numSamples); +cystatus CySpcLock(void); +void CySpcUnlock(void); + + +/*************************************** +* API Constants +***************************************/ + +#define CY_SPC_LOCKED (0x01u) +#define CY_SPC_UNLOCKED (0x00u) + +/******************************************************************************* +* The Array ID indicates the unique ID of the SONOS array being accessed: +* - 0x00-0x3E : Flash Arrays +* - 0x3F : Selects all Flash arrays simultaneously +* - 0x40-0x7F : Embedded EEPROM Arrays +*******************************************************************************/ +#define CY_SPC_FIRST_FLASH_ARRAYID (0x00u) +#define CY_SPC_LAST_FLASH_ARRAYID (0x3Fu) +#define CY_SPC_FIRST_EE_ARRAYID (0x40u) +#define CY_SPC_LAST_EE_ARRAYID (0x7Fu) + + +#define CY_SPC_STATUS_DATA_READY_MASK (0x01u) +#define CY_SPC_STATUS_IDLE_MASK (0x02u) +#define CY_SPC_STATUS_CODE_MASK (0xFCu) +#define CY_SPC_STATUS_CODE_SHIFT (0x02u) + +/* Status codes for the SPC. */ +#define CY_SPC_STATUS_SUCCESS (0x00u) /* Operation Successful */ +#define CY_SPC_STATUS_INVALID_ARRAY_ID (0x01u) /* Invalid Array ID for given command */ +#define CY_SPC_STATUS_INVALID_2BYTEKEY (0x02u) /* Invalid 2-byte key */ +#define CY_SPC_STATUS_ARRAY_ASLEEP (0x03u) /* Addressed Array is Asleep */ +#define CY_SPC_STATUS_EXTERN_ACCESS (0x04u) /* External Access Failure (SPC is not in external access mode) */ +#define CY_SPC_STATUS_INVALID_NUMBER (0x05u) /* Invalid 'N' Value for given command */ +#define CY_SPC_STATUS_TEST_MODE (0x06u) /* Test Mode Failure (SPC is not in test mode) */ +#define CY_SPC_STATUS_ALG_CSUM (0x07u) /* Smart Write Algorithm Checksum Failure */ +#define CY_SPC_STATUS_PARAM_CSUM (0x08u) /* Smart Write Parameter Checksum Failure */ +#define CY_SPC_STATUS_PROTECTION (0x09u) /* Protection Check Failure */ +#define CY_SPC_STATUS_ADDRESS_PARAM (0x0Au) /* Invalid Address parameter for the given command */ +#define CY_SPC_STATUS_COMMAND_CODE (0x0Bu) /* Invalid Command Code */ +#define CY_SPC_STATUS_ROW_ID (0x0Cu) /* Invalid Row ID parameter for given command */ +#define CY_SPC_STATUS_TADC_INPUT (0x0Du) /* Invalid input value for Get Temp & Get ADC commands */ +#define CY_SPC_STATUS_BUSY (0xFFu) /* SPC is busy */ + +#if(CY_PSOC5) + + /* Wait-state pipeline */ + #define CY_SPC_CPU_WAITPIPE_BYPASS ((uint32)0x01u) + +#endif /* (CY_PSOC5) */ + + +/*************************************** +* Registers +***************************************/ + +/* SPC CPU Data Register */ +#define CY_SPC_CPU_DATA_REG (* (reg8 *) CYREG_SPC_CPU_DATA ) +#define CY_SPC_CPU_DATA_PTR ( (reg8 *) CYREG_SPC_CPU_DATA ) + +/* SPC Status Register */ +#define CY_SPC_STATUS_REG (* (reg8 *) CYREG_SPC_SR ) +#define CY_SPC_STATUS_PTR ( (reg8 *) CYREG_SPC_SR ) + +/* Active Power Mode Configuration Register 0 */ +#define CY_SPC_PM_ACT_REG (* (reg8 *) CYREG_PM_ACT_CFG0 ) +#define CY_SPC_PM_ACT_PTR ( (reg8 *) CYREG_PM_ACT_CFG0 ) + +/* Standby Power Mode Configuration Register 0 */ +#define CY_SPC_PM_STBY_REG (* (reg8 *) CYREG_PM_STBY_CFG0 ) +#define CY_SPC_PM_STBY_PTR ( (reg8 *) CYREG_PM_STBY_CFG0 ) + +#if(CY_PSOC5) + + /* Wait State Pipeline */ + #define CY_SPC_CPU_WAITPIPE_REG (* (reg32 *) CYREG_PANTHER_WAITPIPE ) + #define CY_SPC_CPU_WAITPIPE_PTR ( (reg32 *) CYREG_PANTHER_WAITPIPE ) + +#endif /* (CY_PSOC5) */ + + +/*************************************** +* Macros +***************************************/ +#define CY_SPC_IDLE (0u != (CY_SPC_STATUS_REG & CY_SPC_STATUS_IDLE_MASK)) +#define CY_SPC_BUSY (0u == (CY_SPC_STATUS_REG & CY_SPC_STATUS_IDLE_MASK)) +#define CY_SPC_DATA_READY (0u != (CY_SPC_STATUS_REG & CY_SPC_STATUS_DATA_READY_MASK)) + +/* SPC must be in idle state in order to obtain correct status */ +#define CY_SPC_READ_STATUS (CY_SPC_IDLE ? \ + ((uint8)(CY_SPC_STATUS_REG >> CY_SPC_STATUS_CODE_SHIFT)) : \ + ((uint8) CY_SPC_STATUS_BUSY)) + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from cy_boot 3.0 +*******************************************************************************/ +#define FIRST_FLASH_ARRAYID (CY_SPC_FIRST_FLASH_ARRAYID) +#define LAST_FLASH_ARRAYID (CY_SPC_LAST_FLASH_ARRAYID) +#define FIRST_EE_ARRAYID (CY_SPC_FIRST_EE_ARRAYID) +#define LAST_EE_ARRAYID (CY_SPC_LAST_EE_ARRAYID) +#define SIZEOF_ECC_ROW (CYDEV_ECC_ROW_SIZE) +#define SIZEOF_FLASH_ROW (CYDEV_FLS_ROW_SIZE) +#define SIZEOF_EEPROM_ROW (CYDEV_EEPROM_ROW_SIZE) + + +#endif /* (CY_BOOT_CYSPC_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/LED.c b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/LED.c new file mode 100755 index 00000000..3991486a --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/LED.c @@ -0,0 +1,137 @@ +/******************************************************************************* +* File Name: LED.c +* Version 1.90 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "LED.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + LED__PORT == 15 && ((LED__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: LED_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void LED_Write(uint8 value) +{ + uint8 staticBits = (LED_DR & (uint8)(~LED_MASK)); + LED_DR = staticBits | ((uint8)(value << LED_SHIFT) & LED_MASK); +} + + +/******************************************************************************* +* Function Name: LED_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to this drive mode. +* +* Return: +* None +* +*******************************************************************************/ +void LED_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(LED_0, mode); +} + + +/******************************************************************************* +* Function Name: LED_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro LED_ReadPS calls this function. +* +*******************************************************************************/ +uint8 LED_Read(void) +{ + return (LED_PS & LED_MASK) >> LED_SHIFT; +} + + +/******************************************************************************* +* Function Name: LED_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 LED_ReadDataReg(void) +{ + return (LED_DR & LED_MASK) >> LED_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(LED_INTSTAT) + + /******************************************************************************* + * Function Name: LED_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 LED_ClearInterrupt(void) + { + return (LED_INTSTAT & LED_MASK) >> LED_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/LED.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/LED.h new file mode 100755 index 00000000..103fc452 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/LED.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: LED.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_LED_H) /* Pins LED_H */ +#define CY_PINS_LED_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "LED_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + LED__PORT == 15 && ((LED__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void LED_Write(uint8 value) ; +void LED_SetDriveMode(uint8 mode) ; +uint8 LED_ReadDataReg(void) ; +uint8 LED_Read(void) ; +uint8 LED_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define LED_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define LED_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define LED_DM_RES_UP PIN_DM_RES_UP +#define LED_DM_RES_DWN PIN_DM_RES_DWN +#define LED_DM_OD_LO PIN_DM_OD_LO +#define LED_DM_OD_HI PIN_DM_OD_HI +#define LED_DM_STRONG PIN_DM_STRONG +#define LED_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define LED_MASK LED__MASK +#define LED_SHIFT LED__SHIFT +#define LED_WIDTH 1u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define LED_PS (* (reg8 *) LED__PS) +/* Data Register */ +#define LED_DR (* (reg8 *) LED__DR) +/* Port Number */ +#define LED_PRT_NUM (* (reg8 *) LED__PRT) +/* Connect to Analog Globals */ +#define LED_AG (* (reg8 *) LED__AG) +/* Analog MUX bux enable */ +#define LED_AMUX (* (reg8 *) LED__AMUX) +/* Bidirectional Enable */ +#define LED_BIE (* (reg8 *) LED__BIE) +/* Bit-mask for Aliased Register Access */ +#define LED_BIT_MASK (* (reg8 *) LED__BIT_MASK) +/* Bypass Enable */ +#define LED_BYP (* (reg8 *) LED__BYP) +/* Port wide control signals */ +#define LED_CTL (* (reg8 *) LED__CTL) +/* Drive Modes */ +#define LED_DM0 (* (reg8 *) LED__DM0) +#define LED_DM1 (* (reg8 *) LED__DM1) +#define LED_DM2 (* (reg8 *) LED__DM2) +/* Input Buffer Disable Override */ +#define LED_INP_DIS (* (reg8 *) LED__INP_DIS) +/* LCD Common or Segment Drive */ +#define LED_LCD_COM_SEG (* (reg8 *) LED__LCD_COM_SEG) +/* Enable Segment LCD */ +#define LED_LCD_EN (* (reg8 *) LED__LCD_EN) +/* Slew Rate Control */ +#define LED_SLW (* (reg8 *) LED__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define LED_PRTDSI__CAPS_SEL (* (reg8 *) LED__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define LED_PRTDSI__DBL_SYNC_IN (* (reg8 *) LED__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define LED_PRTDSI__OE_SEL0 (* (reg8 *) LED__PRTDSI__OE_SEL0) +#define LED_PRTDSI__OE_SEL1 (* (reg8 *) LED__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define LED_PRTDSI__OUT_SEL0 (* (reg8 *) LED__PRTDSI__OUT_SEL0) +#define LED_PRTDSI__OUT_SEL1 (* (reg8 *) LED__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define LED_PRTDSI__SYNC_OUT (* (reg8 *) LED__PRTDSI__SYNC_OUT) + + +#if defined(LED__INTSTAT) /* Interrupt Registers */ + + #define LED_INTSTAT (* (reg8 *) LED__INTSTAT) + #define LED_SNAP (* (reg8 *) LED__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_LED_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/LED_aliases.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/LED_aliases.h new file mode 100755 index 00000000..61edd82b --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/LED_aliases.h @@ -0,0 +1,32 @@ +/******************************************************************************* +* File Name: LED.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_LED_ALIASES_H) /* Pins LED_ALIASES_H */ +#define CY_PINS_LED_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define LED_0 LED__0__PC + +#endif /* End Pins LED_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h new file mode 100644 index 00000000..cab58f9f --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h @@ -0,0 +1,48 @@ +/******************************************************************************* +* File Name: SCSI_Out_DBx.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SCSI_Out_DBx_ALIASES_H) /* Pins SCSI_Out_DBx_ALIASES_H */ +#define CY_PINS_SCSI_Out_DBx_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SCSI_Out_DBx_0 SCSI_Out_DBx__0__PC +#define SCSI_Out_DBx_1 SCSI_Out_DBx__1__PC +#define SCSI_Out_DBx_2 SCSI_Out_DBx__2__PC +#define SCSI_Out_DBx_3 SCSI_Out_DBx__3__PC +#define SCSI_Out_DBx_4 SCSI_Out_DBx__4__PC +#define SCSI_Out_DBx_5 SCSI_Out_DBx__5__PC +#define SCSI_Out_DBx_6 SCSI_Out_DBx__6__PC +#define SCSI_Out_DBx_7 SCSI_Out_DBx__7__PC + +#define SCSI_Out_DBx_DB0 SCSI_Out_DBx__DB0__PC +#define SCSI_Out_DBx_DB1 SCSI_Out_DBx__DB1__PC +#define SCSI_Out_DBx_DB2 SCSI_Out_DBx__DB2__PC +#define SCSI_Out_DBx_DB3 SCSI_Out_DBx__DB3__PC +#define SCSI_Out_DBx_DB4 SCSI_Out_DBx__DB4__PC +#define SCSI_Out_DBx_DB5 SCSI_Out_DBx__DB5__PC +#define SCSI_Out_DBx_DB6 SCSI_Out_DBx__DB6__PC +#define SCSI_Out_DBx_DB7 SCSI_Out_DBx__DB7__PC + +#endif /* End Pins SCSI_Out_DBx_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h new file mode 100644 index 00000000..cd457bc8 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h @@ -0,0 +1,52 @@ +/******************************************************************************* +* File Name: SCSI_Out.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SCSI_Out_ALIASES_H) /* Pins SCSI_Out_ALIASES_H */ +#define CY_PINS_SCSI_Out_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SCSI_Out_0 SCSI_Out__0__PC +#define SCSI_Out_1 SCSI_Out__1__PC +#define SCSI_Out_2 SCSI_Out__2__PC +#define SCSI_Out_3 SCSI_Out__3__PC +#define SCSI_Out_4 SCSI_Out__4__PC +#define SCSI_Out_5 SCSI_Out__5__PC +#define SCSI_Out_6 SCSI_Out__6__PC +#define SCSI_Out_7 SCSI_Out__7__PC +#define SCSI_Out_8 SCSI_Out__8__PC +#define SCSI_Out_9 SCSI_Out__9__PC + +#define SCSI_Out_DBP_raw SCSI_Out__DBP_raw__PC +#define SCSI_Out_ATN SCSI_Out__ATN__PC +#define SCSI_Out_BSY SCSI_Out__BSY__PC +#define SCSI_Out_ACK SCSI_Out__ACK__PC +#define SCSI_Out_RST SCSI_Out__RST__PC +#define SCSI_Out_MSG SCSI_Out__MSG__PC +#define SCSI_Out_SEL SCSI_Out__SEL__PC +#define SCSI_Out_CD SCSI_Out__CD__PC +#define SCSI_Out_REQ SCSI_Out__REQ__PC +#define SCSI_Out_IO_raw SCSI_Out__IO_raw__PC + +#endif /* End Pins SCSI_Out_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.c b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.c new file mode 100755 index 00000000..a5aa27ee --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.c @@ -0,0 +1,141 @@ +/******************************************************************************* +* File Name: SD_PULLUP.c +* Version 1.90 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SD_PULLUP.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + SD_PULLUP__PORT == 15 && ((SD_PULLUP__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: SD_PULLUP_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void SD_PULLUP_Write(uint8 value) +{ + uint8 staticBits = (SD_PULLUP_DR & (uint8)(~SD_PULLUP_MASK)); + SD_PULLUP_DR = staticBits | ((uint8)(value << SD_PULLUP_SHIFT) & SD_PULLUP_MASK); +} + + +/******************************************************************************* +* Function Name: SD_PULLUP_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to this drive mode. +* +* Return: +* None +* +*******************************************************************************/ +void SD_PULLUP_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(SD_PULLUP_0, mode); + CyPins_SetPinDriveMode(SD_PULLUP_1, mode); + CyPins_SetPinDriveMode(SD_PULLUP_2, mode); + CyPins_SetPinDriveMode(SD_PULLUP_3, mode); + CyPins_SetPinDriveMode(SD_PULLUP_4, mode); +} + + +/******************************************************************************* +* Function Name: SD_PULLUP_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro SD_PULLUP_ReadPS calls this function. +* +*******************************************************************************/ +uint8 SD_PULLUP_Read(void) +{ + return (SD_PULLUP_PS & SD_PULLUP_MASK) >> SD_PULLUP_SHIFT; +} + + +/******************************************************************************* +* Function Name: SD_PULLUP_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 SD_PULLUP_ReadDataReg(void) +{ + return (SD_PULLUP_DR & SD_PULLUP_MASK) >> SD_PULLUP_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(SD_PULLUP_INTSTAT) + + /******************************************************************************* + * Function Name: SD_PULLUP_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 SD_PULLUP_ClearInterrupt(void) + { + return (SD_PULLUP_INTSTAT & SD_PULLUP_MASK) >> SD_PULLUP_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.h new file mode 100755 index 00000000..07394f01 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: SD_PULLUP.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_PULLUP_H) /* Pins SD_PULLUP_H */ +#define CY_PINS_SD_PULLUP_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SD_PULLUP_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SD_PULLUP__PORT == 15 && ((SD_PULLUP__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void SD_PULLUP_Write(uint8 value) ; +void SD_PULLUP_SetDriveMode(uint8 mode) ; +uint8 SD_PULLUP_ReadDataReg(void) ; +uint8 SD_PULLUP_Read(void) ; +uint8 SD_PULLUP_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define SD_PULLUP_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define SD_PULLUP_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define SD_PULLUP_DM_RES_UP PIN_DM_RES_UP +#define SD_PULLUP_DM_RES_DWN PIN_DM_RES_DWN +#define SD_PULLUP_DM_OD_LO PIN_DM_OD_LO +#define SD_PULLUP_DM_OD_HI PIN_DM_OD_HI +#define SD_PULLUP_DM_STRONG PIN_DM_STRONG +#define SD_PULLUP_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define SD_PULLUP_MASK SD_PULLUP__MASK +#define SD_PULLUP_SHIFT SD_PULLUP__SHIFT +#define SD_PULLUP_WIDTH 5u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SD_PULLUP_PS (* (reg8 *) SD_PULLUP__PS) +/* Data Register */ +#define SD_PULLUP_DR (* (reg8 *) SD_PULLUP__DR) +/* Port Number */ +#define SD_PULLUP_PRT_NUM (* (reg8 *) SD_PULLUP__PRT) +/* Connect to Analog Globals */ +#define SD_PULLUP_AG (* (reg8 *) SD_PULLUP__AG) +/* Analog MUX bux enable */ +#define SD_PULLUP_AMUX (* (reg8 *) SD_PULLUP__AMUX) +/* Bidirectional Enable */ +#define SD_PULLUP_BIE (* (reg8 *) SD_PULLUP__BIE) +/* Bit-mask for Aliased Register Access */ +#define SD_PULLUP_BIT_MASK (* (reg8 *) SD_PULLUP__BIT_MASK) +/* Bypass Enable */ +#define SD_PULLUP_BYP (* (reg8 *) SD_PULLUP__BYP) +/* Port wide control signals */ +#define SD_PULLUP_CTL (* (reg8 *) SD_PULLUP__CTL) +/* Drive Modes */ +#define SD_PULLUP_DM0 (* (reg8 *) SD_PULLUP__DM0) +#define SD_PULLUP_DM1 (* (reg8 *) SD_PULLUP__DM1) +#define SD_PULLUP_DM2 (* (reg8 *) SD_PULLUP__DM2) +/* Input Buffer Disable Override */ +#define SD_PULLUP_INP_DIS (* (reg8 *) SD_PULLUP__INP_DIS) +/* LCD Common or Segment Drive */ +#define SD_PULLUP_LCD_COM_SEG (* (reg8 *) SD_PULLUP__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SD_PULLUP_LCD_EN (* (reg8 *) SD_PULLUP__LCD_EN) +/* Slew Rate Control */ +#define SD_PULLUP_SLW (* (reg8 *) SD_PULLUP__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SD_PULLUP_PRTDSI__CAPS_SEL (* (reg8 *) SD_PULLUP__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SD_PULLUP_PRTDSI__DBL_SYNC_IN (* (reg8 *) SD_PULLUP__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SD_PULLUP_PRTDSI__OE_SEL0 (* (reg8 *) SD_PULLUP__PRTDSI__OE_SEL0) +#define SD_PULLUP_PRTDSI__OE_SEL1 (* (reg8 *) SD_PULLUP__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SD_PULLUP_PRTDSI__OUT_SEL0 (* (reg8 *) SD_PULLUP__PRTDSI__OUT_SEL0) +#define SD_PULLUP_PRTDSI__OUT_SEL1 (* (reg8 *) SD_PULLUP__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SD_PULLUP_PRTDSI__SYNC_OUT (* (reg8 *) SD_PULLUP__PRTDSI__SYNC_OUT) + + +#if defined(SD_PULLUP__INTSTAT) /* Interrupt Registers */ + + #define SD_PULLUP_INTSTAT (* (reg8 *) SD_PULLUP__INTSTAT) + #define SD_PULLUP_SNAP (* (reg8 *) SD_PULLUP__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SD_PULLUP_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP_aliases.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP_aliases.h new file mode 100755 index 00000000..bf8bd1df --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP_aliases.h @@ -0,0 +1,36 @@ +/******************************************************************************* +* File Name: SD_PULLUP.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_PULLUP_ALIASES_H) /* Pins SD_PULLUP_ALIASES_H */ +#define CY_PINS_SD_PULLUP_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SD_PULLUP_0 SD_PULLUP__0__PC +#define SD_PULLUP_1 SD_PULLUP__1__PC +#define SD_PULLUP_2 SD_PULLUP__2__PC +#define SD_PULLUP_3 SD_PULLUP__3__PC +#define SD_PULLUP_4 SD_PULLUP__4__PC + +#endif /* End Pins SD_PULLUP_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS.c b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS.c new file mode 100644 index 00000000..0750c413 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS.c @@ -0,0 +1,1335 @@ +/******************************************************************************* +* File Name: USBFS.c +* Version 2.60 +* +* Description: +* API for USBFS Component. +* +* Note: +* Many of the functions use endpoint number. RAM arrays are sized with 9 +* elements so they are indexed directly by epNumber. The SIE and ARB +* registers are indexed by variations of epNumber - 1. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "USBFS.h" +#include "USBFS_pvt.h" +#include "USBFS_hid.h" +#if(USBFS_DMA1_REMOVE == 0u) + #include "USBFS_ep1_dma.h" +#endif /* End USBFS_DMA1_REMOVE */ +#if(USBFS_DMA2_REMOVE == 0u) + #include "USBFS_ep2_dma.h" +#endif /* End USBFS_DMA2_REMOVE */ +#if(USBFS_DMA3_REMOVE == 0u) + #include "USBFS_ep3_dma.h" +#endif /* End USBFS_DMA3_REMOVE */ +#if(USBFS_DMA4_REMOVE == 0u) + #include "USBFS_ep4_dma.h" +#endif /* End USBFS_DMA4_REMOVE */ +#if(USBFS_DMA5_REMOVE == 0u) + #include "USBFS_ep5_dma.h" +#endif /* End USBFS_DMA5_REMOVE */ +#if(USBFS_DMA6_REMOVE == 0u) + #include "USBFS_ep6_dma.h" +#endif /* End USBFS_DMA6_REMOVE */ +#if(USBFS_DMA7_REMOVE == 0u) + #include "USBFS_ep7_dma.h" +#endif /* End USBFS_DMA7_REMOVE */ +#if(USBFS_DMA8_REMOVE == 0u) + #include "USBFS_ep8_dma.h" +#endif /* End USBFS_DMA8_REMOVE */ + + +/*************************************** +* Global data allocation +***************************************/ + +uint8 USBFS_initVar = 0u; +#if(USBFS_EP_MM != USBFS__EP_MANUAL) + uint8 USBFS_DmaChan[USBFS_MAX_EP]; + uint8 USBFS_DmaTd[USBFS_MAX_EP]; +#endif /* End USBFS_EP_MM */ + + +/******************************************************************************* +* Function Name: USBFS_Start +******************************************************************************** +* +* Summary: +* This function initialize the USB SIE, arbiter and the +* endpoint APIs, including setting the D+ Pullup +* +* Parameters: +* device: Contains the device number of the desired device descriptor. +* The device number can be found in the Device Descriptor Tab of +* "Configure" dialog, under the settings of desired Device Descriptor, +* in the "Device Number" field. +* mode: The operating voltage. This determines whether the voltage regulator +* is enabled for 5V operation or if pass through mode is used for 3.3V +* operation. Symbolic names and their associated values are given in the +* following table. +* USBFS_3V_OPERATION - Disable voltage regulator and pass-thru +* Vcc for pull-up +* USBFS_5V_OPERATION - Enable voltage regulator and use +* regulator for pull-up +* USBFS_DWR_VDDD_OPERATION - Enable or Disable voltage +* regulator depend on Vddd Voltage configuration in DWR. +* +* Return: +* None. +* +* Global variables: +* The USBFS_intiVar variable is used to indicate initial +* configuration of this component. The variable is initialized to zero (0u) +* and set to one (1u) the first time USBFS_Start() is called. +* This allows for component Re-Start without unnecessary re-initialization +* in all subsequent calls to the USBFS_Start() routine. +* If re-initialization of the component is required the variable should be set +* to zero before call of UART_Start() routine, or the user may call +* USBFS_Init() and USBFS_InitComponent() as done +* in the USBFS_Start() routine. +* +* Side Effects: +* This function will reset all communication states to default. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_Start(uint8 device, uint8 mode) +{ + /* If not Initialized then initialize all required hardware and software */ + if(USBFS_initVar == 0u) + { + USBFS_Init(); + USBFS_initVar = 1u; + } + USBFS_InitComponent(device, mode); +} + + +/******************************************************************************* +* Function Name: USBFS_Init +******************************************************************************** +* +* Summary: +* Initialize component's hardware. Usually called in USBFS_Start(). +* +* Parameters: +* None. +* +* Return: +* None. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_Init(void) +{ + uint8 enableInterrupts; + #if(USBFS_EP_MM != USBFS__EP_MANUAL) + uint16 i; + #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ + + enableInterrupts = CyEnterCriticalSection(); + + /* Enable USB block */ + USBFS_PM_ACT_CFG_REG |= USBFS_PM_ACT_EN_FSUSB; + /* Enable USB block for Standby Power Mode */ + USBFS_PM_STBY_CFG_REG |= USBFS_PM_STBY_EN_FSUSB; + + /* Enable core clock */ + USBFS_USB_CLK_EN_REG = USBFS_USB_CLK_ENABLE; + + USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK; + + /* ENABLING USBIO PADS IN USB MODE FROM I/O MODE */ + /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled */ + USBFS_USBIO_CR0_REG &= ((uint8)(~USBFS_USBIO_CR0_TEN)); + CyDelayUs(0u); /*~50ns delay */ + /* Disable the USBIO by asserting PM.USB_CR0.fsusbio_pd_n(Inverted) + * high. This will have been set low by the power manger out of reset. + * Also confirm USBIO pull-up disabled + */ + USBFS_PM_USB_CR0_REG &= ((uint8)(~(USBFS_PM_USB_CR0_PD_N | + USBFS_PM_USB_CR0_PD_PULLUP_N))); + + /* Select iomode to USB mode*/ + USBFS_USBIO_CR1_REG &= ((uint8)(~USBFS_USBIO_CR1_IOMODE)); + + /* Enable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/ + USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_REF_EN; + /* The reference will be available 1 us after the regulator is enabled */ + CyDelayUs(1u); + /* OR 40us after power restored */ + CyDelayUs(40u); + /* Ensure the single ended disable bits are low (PRT15.INP_DIS[7:6])(input receiver enabled). */ + USBFS_DM_INP_DIS_REG &= ((uint8)(~USBFS_DM_MASK)); + USBFS_DP_INP_DIS_REG &= ((uint8)(~USBFS_DP_MASK)); + + /* Enable USBIO */ + USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_N; + CyDelayUs(2u); + /* Set the USBIO pull-up enable */ + USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_PULLUP_N; + + /* Write WAx */ + CY_SET_REG8(USBFS_ARB_RW1_WA_PTR, 0u); + CY_SET_REG8(USBFS_ARB_RW1_WA_MSB_PTR, 0u); + + #if(USBFS_EP_MM != USBFS__EP_MANUAL) + /* Init transfer descriptor. This will be used to detect the DMA state - initialized or not. */ + for (i = 0u; i < USBFS_MAX_EP; i++) + { + USBFS_DmaTd[i] = DMA_INVALID_TD; + } + #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ + + CyExitCriticalSection(enableInterrupts); + + + /* Set the bus reset Interrupt. */ + (void) CyIntSetVector(USBFS_BUS_RESET_VECT_NUM, &USBFS_BUS_RESET_ISR); + CyIntSetPriority(USBFS_BUS_RESET_VECT_NUM, USBFS_BUS_RESET_PRIOR); + + /* Set the SOF Interrupt. */ + #if(USBFS_SOF_ISR_REMOVE == 0u) + (void) CyIntSetVector(USBFS_SOF_VECT_NUM, &USBFS_SOF_ISR); + CyIntSetPriority(USBFS_SOF_VECT_NUM, USBFS_SOF_PRIOR); + #endif /* End USBFS_SOF_ISR_REMOVE */ + + /* Set the Control Endpoint Interrupt. */ + (void) CyIntSetVector(USBFS_EP_0_VECT_NUM, &USBFS_EP_0_ISR); + CyIntSetPriority(USBFS_EP_0_VECT_NUM, USBFS_EP_0_PRIOR); + + /* Set the Data Endpoint 1 Interrupt. */ + #if(USBFS_EP1_ISR_REMOVE == 0u) + (void) CyIntSetVector(USBFS_EP_1_VECT_NUM, &USBFS_EP_1_ISR); + CyIntSetPriority(USBFS_EP_1_VECT_NUM, USBFS_EP_1_PRIOR); + #endif /* End USBFS_EP1_ISR_REMOVE */ + + /* Set the Data Endpoint 2 Interrupt. */ + #if(USBFS_EP2_ISR_REMOVE == 0u) + (void) CyIntSetVector(USBFS_EP_2_VECT_NUM, &USBFS_EP_2_ISR); + CyIntSetPriority(USBFS_EP_2_VECT_NUM, USBFS_EP_2_PRIOR); + #endif /* End USBFS_EP2_ISR_REMOVE */ + + /* Set the Data Endpoint 3 Interrupt. */ + #if(USBFS_EP3_ISR_REMOVE == 0u) + (void) CyIntSetVector(USBFS_EP_3_VECT_NUM, &USBFS_EP_3_ISR); + CyIntSetPriority(USBFS_EP_3_VECT_NUM, USBFS_EP_3_PRIOR); + #endif /* End USBFS_EP3_ISR_REMOVE */ + + /* Set the Data Endpoint 4 Interrupt. */ + #if(USBFS_EP4_ISR_REMOVE == 0u) + (void) CyIntSetVector(USBFS_EP_4_VECT_NUM, &USBFS_EP_4_ISR); + CyIntSetPriority(USBFS_EP_4_VECT_NUM, USBFS_EP_4_PRIOR); + #endif /* End USBFS_EP4_ISR_REMOVE */ + + /* Set the Data Endpoint 5 Interrupt. */ + #if(USBFS_EP5_ISR_REMOVE == 0u) + (void) CyIntSetVector(USBFS_EP_5_VECT_NUM, &USBFS_EP_5_ISR); + CyIntSetPriority(USBFS_EP_5_VECT_NUM, USBFS_EP_5_PRIOR); + #endif /* End USBFS_EP5_ISR_REMOVE */ + + /* Set the Data Endpoint 6 Interrupt. */ + #if(USBFS_EP6_ISR_REMOVE == 0u) + (void) CyIntSetVector(USBFS_EP_6_VECT_NUM, &USBFS_EP_6_ISR); + CyIntSetPriority(USBFS_EP_6_VECT_NUM, USBFS_EP_6_PRIOR); + #endif /* End USBFS_EP6_ISR_REMOVE */ + + /* Set the Data Endpoint 7 Interrupt. */ + #if(USBFS_EP7_ISR_REMOVE == 0u) + (void) CyIntSetVector(USBFS_EP_7_VECT_NUM, &USBFS_EP_7_ISR); + CyIntSetPriority(USBFS_EP_7_VECT_NUM, USBFS_EP_7_PRIOR); + #endif /* End USBFS_EP7_ISR_REMOVE */ + + /* Set the Data Endpoint 8 Interrupt. */ + #if(USBFS_EP8_ISR_REMOVE == 0u) + (void) CyIntSetVector(USBFS_EP_8_VECT_NUM, &USBFS_EP_8_ISR); + CyIntSetPriority(USBFS_EP_8_VECT_NUM, USBFS_EP_8_PRIOR); + #endif /* End USBFS_EP8_ISR_REMOVE */ + + #if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u)) + /* Set the ARB Interrupt. */ + (void) CyIntSetVector(USBFS_ARB_VECT_NUM, &USBFS_ARB_ISR); + CyIntSetPriority(USBFS_ARB_VECT_NUM, USBFS_ARB_PRIOR); + #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ + +} + + +/******************************************************************************* +* Function Name: USBFS_InitComponent +******************************************************************************** +* +* Summary: +* Initialize the component, except for the HW which is done one time in +* the Start function. This function pulls up D+. +* +* Parameters: +* device: Contains the device number of the desired device descriptor. +* The device number can be found in the Device Descriptor Tab of +* "Configure" dialog, under the settings of desired Device Descriptor, +* in the "Device Number" field. +* mode: The operating voltage. This determines whether the voltage regulator +* is enabled for 5V operation or if pass through mode is used for 3.3V +* operation. Symbolic names and their associated values are given in the +* following table. +* USBFS_3V_OPERATION - Disable voltage regulator and pass-thru +* Vcc for pull-up +* USBFS_5V_OPERATION - Enable voltage regulator and use +* regulator for pull-up +* USBFS_DWR_VDDD_OPERATION - Enable or Disable voltage +* regulator depend on Vddd Voltage configuration in DWR. +* +* Return: +* None. +* +* Global variables: +* USBFS_device: Contains the device number of the desired device +* descriptor. The device number can be found in the Device Descriptor Tab +* of "Configure" dialog, under the settings of desired Device Descriptor, +* in the "Device Number" field. +* USBFS_transferState: This variable used by the communication +* functions to handle current transfer state. Initialized to +* TRANS_STATE_IDLE in this API. +* USBFS_configuration: Contains current configuration number +* which is set by the Host using SET_CONFIGURATION request. +* Initialized to zero in this API. +* USBFS_deviceAddress: Contains current device address. This +* variable is initialized to zero in this API. Host starts to communicate +* to device with address 0 and then set it to whatever value using +* SET_ADDRESS request. +* USBFS_deviceStatus: initialized to 0. +* This is two bit variable which contain power status in first bit +* (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote +* wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit. +* USBFS_lastPacketSize initialized to 0; +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_InitComponent(uint8 device, uint8 mode) +{ + /* Initialize _hidProtocol variable to comply with + * HID 7.2.6 Set_Protocol Request: + * "When initialized, all devices default to report protocol." + */ + #if defined(USBFS_ENABLE_HID_CLASS) + uint8 i; + + for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++) + { + USBFS_hidProtocol[i] = USBFS_PROTOCOL_REPORT; + } + #endif /* USBFS_ENABLE_HID_CLASS */ + + /* Enable Interrupts. */ + CyIntEnable(USBFS_BUS_RESET_VECT_NUM); + CyIntEnable(USBFS_EP_0_VECT_NUM); + #if(USBFS_EP1_ISR_REMOVE == 0u) + CyIntEnable(USBFS_EP_1_VECT_NUM); + #endif /* End USBFS_EP1_ISR_REMOVE */ + #if(USBFS_EP2_ISR_REMOVE == 0u) + CyIntEnable(USBFS_EP_2_VECT_NUM); + #endif /* End USBFS_EP2_ISR_REMOVE */ + #if(USBFS_EP3_ISR_REMOVE == 0u) + CyIntEnable(USBFS_EP_3_VECT_NUM); + #endif /* End USBFS_EP3_ISR_REMOVE */ + #if(USBFS_EP4_ISR_REMOVE == 0u) + CyIntEnable(USBFS_EP_4_VECT_NUM); + #endif /* End USBFS_EP4_ISR_REMOVE */ + #if(USBFS_EP5_ISR_REMOVE == 0u) + CyIntEnable(USBFS_EP_5_VECT_NUM); + #endif /* End USBFS_EP5_ISR_REMOVE */ + #if(USBFS_EP6_ISR_REMOVE == 0u) + CyIntEnable(USBFS_EP_6_VECT_NUM); + #endif /* End USBFS_EP6_ISR_REMOVE */ + #if(USBFS_EP7_ISR_REMOVE == 0u) + CyIntEnable(USBFS_EP_7_VECT_NUM); + #endif /* End USBFS_EP7_ISR_REMOVE */ + #if(USBFS_EP8_ISR_REMOVE == 0u) + CyIntEnable(USBFS_EP_8_VECT_NUM); + #endif /* End USBFS_EP8_ISR_REMOVE */ + #if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u)) + /* usb arb interrupt enable */ + USBFS_ARB_INT_EN_REG = USBFS_ARB_INT_MASK; + CyIntEnable(USBFS_ARB_VECT_NUM); + #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ + + /* Arbiter configuration for DMA transfers */ + #if(USBFS_EP_MM != USBFS__EP_MANUAL) + + #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL) + USBFS_ARB_CFG_REG = USBFS_ARB_CFG_MANUAL_DMA; + #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */ + #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + /*Set cfg cmplt this rises DMA request when the full configuration is done */ + USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM; + #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ + #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ + + USBFS_transferState = USBFS_TRANS_STATE_IDLE; + + /* USB Locking: Enabled, VRegulator: depend on mode or DWR Voltage configuration*/ + switch(mode) + { + case USBFS_3V_OPERATION: + USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK; + break; + case USBFS_5V_OPERATION: + USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK | USBFS_CR1_REG_ENABLE; + break; + default: /*USBFS_DWR_VDDD_OPERATION */ + #if(USBFS_VDDD_MV < USBFS_3500MV) + USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK; + #else + USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK | USBFS_CR1_REG_ENABLE; + #endif /* End USBFS_VDDD_MV < USBFS_3500MV */ + break; + } + + /* Record the descriptor selection */ + USBFS_device = device; + + /* Clear all of the component data */ + USBFS_configuration = 0u; + USBFS_interfaceNumber = 0u; + USBFS_configurationChanged = 0u; + USBFS_deviceAddress = 0u; + USBFS_deviceStatus = 0u; + + USBFS_lastPacketSize = 0u; + + /* ACK Setup, Stall IN/OUT */ + CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT); + + /* Enable the SIE with an address 0 */ + CY_SET_REG8(USBFS_CR0_PTR, USBFS_CR0_ENABLE); + + /* Workaround for PSOC5LP */ + CyDelayCycles(1u); + + /* Finally, Enable d+ pullup and select iomode to USB mode*/ + CY_SET_REG8(USBFS_USBIO_CR1_PTR, USBFS_USBIO_CR1_USBPUEN); +} + + +/******************************************************************************* +* Function Name: USBFS_ReInitComponent +******************************************************************************** +* +* Summary: +* This function reinitialize the component configuration and is +* intend to be called from the Reset interrupt. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* USBFS_device: Contains the device number of the desired device +* descriptor. The device number can be found in the Device Descriptor Tab +* of "Configure" dialog, under the settings of desired Device Descriptor, +* in the "Device Number" field. +* USBFS_transferState: This variable used by the communication +* functions to handle current transfer state. Initialized to +* TRANS_STATE_IDLE in this API. +* USBFS_configuration: Contains current configuration number +* which is set by the Host using SET_CONFIGURATION request. +* Initialized to zero in this API. +* USBFS_deviceAddress: Contains current device address. This +* variable is initialized to zero in this API. Host starts to communicate +* to device with address 0 and then set it to whatever value using +* SET_ADDRESS request. +* USBFS_deviceStatus: initialized to 0. +* This is two bit variable which contain power status in first bit +* (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote +* wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit. +* USBFS_lastPacketSize initialized to 0; +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_ReInitComponent(void) +{ + /* Initialize _hidProtocol variable to comply with HID 7.2.6 Set_Protocol + * Request: "When initialized, all devices default to report protocol." + */ + #if defined(USBFS_ENABLE_HID_CLASS) + uint8 i; + + for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++) + { + USBFS_hidProtocol[i] = USBFS_PROTOCOL_REPORT; + } + #endif /* USBFS_ENABLE_HID_CLASS */ + + USBFS_transferState = USBFS_TRANS_STATE_IDLE; + + /* Clear all of the component data */ + USBFS_configuration = 0u; + USBFS_interfaceNumber = 0u; + USBFS_configurationChanged = 0u; + USBFS_deviceAddress = 0u; + USBFS_deviceStatus = 0u; + + USBFS_lastPacketSize = 0u; + + + /* ACK Setup, Stall IN/OUT */ + CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT); + + /* Enable the SIE with an address 0 */ + CY_SET_REG8(USBFS_CR0_PTR, USBFS_CR0_ENABLE); + +} + + +/******************************************************************************* +* Function Name: USBFS_Stop +******************************************************************************** +* +* Summary: +* This function shuts down the USB function including to release +* the D+ Pullup and disabling the SIE. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* USBFS_configuration: Contains current configuration number +* which is set by the Host using SET_CONFIGURATION request. +* Initialized to zero in this API. +* USBFS_deviceAddress: Contains current device address. This +* variable is initialized to zero in this API. Host starts to communicate +* to device with address 0 and then set it to whatever value using +* SET_ADDRESS request. +* USBFS_deviceStatus: initialized to 0. +* This is two bit variable which contain power status in first bit +* (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote +* wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit. +* USBFS_configurationChanged: This variable is set to one after +* SET_CONFIGURATION request and cleared in this function. +* USBFS_intiVar variable is set to zero +* +*******************************************************************************/ +void USBFS_Stop(void) +{ + + #if(USBFS_EP_MM != USBFS__EP_MANUAL) + USBFS_Stop_DMA(USBFS_MAX_EP); /* Stop all DMAs */ + #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ + + /* Disable the SIE */ + USBFS_CR0_REG &= (uint8)(~USBFS_CR0_ENABLE); + /* Disable the d+ pullup */ + USBFS_USBIO_CR1_REG &= (uint8)(~USBFS_USBIO_CR1_USBPUEN); + /* Disable USB in ACT PM */ + USBFS_PM_ACT_CFG_REG &= (uint8)(~USBFS_PM_ACT_EN_FSUSB); + /* Disable USB block for Standby Power Mode */ + USBFS_PM_STBY_CFG_REG &= (uint8)(~USBFS_PM_STBY_EN_FSUSB); + + /* Disable the reset and EP interrupts */ + CyIntDisable(USBFS_BUS_RESET_VECT_NUM); + CyIntDisable(USBFS_EP_0_VECT_NUM); + #if(USBFS_EP1_ISR_REMOVE == 0u) + CyIntDisable(USBFS_EP_1_VECT_NUM); + #endif /* End USBFS_EP1_ISR_REMOVE */ + #if(USBFS_EP2_ISR_REMOVE == 0u) + CyIntDisable(USBFS_EP_2_VECT_NUM); + #endif /* End USBFS_EP2_ISR_REMOVE */ + #if(USBFS_EP3_ISR_REMOVE == 0u) + CyIntDisable(USBFS_EP_3_VECT_NUM); + #endif /* End USBFS_EP3_ISR_REMOVE */ + #if(USBFS_EP4_ISR_REMOVE == 0u) + CyIntDisable(USBFS_EP_4_VECT_NUM); + #endif /* End USBFS_EP4_ISR_REMOVE */ + #if(USBFS_EP5_ISR_REMOVE == 0u) + CyIntDisable(USBFS_EP_5_VECT_NUM); + #endif /* End USBFS_EP5_ISR_REMOVE */ + #if(USBFS_EP6_ISR_REMOVE == 0u) + CyIntDisable(USBFS_EP_6_VECT_NUM); + #endif /* End USBFS_EP6_ISR_REMOVE */ + #if(USBFS_EP7_ISR_REMOVE == 0u) + CyIntDisable(USBFS_EP_7_VECT_NUM); + #endif /* End USBFS_EP7_ISR_REMOVE */ + #if(USBFS_EP8_ISR_REMOVE == 0u) + CyIntDisable(USBFS_EP_8_VECT_NUM); + #endif /* End USBFS_EP8_ISR_REMOVE */ + + /* Clear all of the component data */ + USBFS_configuration = 0u; + USBFS_interfaceNumber = 0u; + USBFS_configurationChanged = 0u; + USBFS_deviceAddress = 0u; + USBFS_deviceStatus = 0u; + USBFS_initVar = 0u; + +} + + +/******************************************************************************* +* Function Name: USBFS_CheckActivity +******************************************************************************** +* +* Summary: +* Returns the activity status of the bus. Clears the status hardware to +* provide fresh activity status on the next call of this routine. +* +* Parameters: +* None. +* +* Return: +* 1 - If bus activity was detected since the last call to this function +* 0 - If bus activity not was detected since the last call to this function +* +*******************************************************************************/ +uint8 USBFS_CheckActivity(void) +{ + uint8 r; + + r = CY_GET_REG8(USBFS_CR1_PTR); + CY_SET_REG8(USBFS_CR1_PTR, (r & ((uint8)(~USBFS_CR1_BUS_ACTIVITY)))); + + return((r & USBFS_CR1_BUS_ACTIVITY) >> USBFS_CR1_BUS_ACTIVITY_SHIFT); +} + + +/******************************************************************************* +* Function Name: USBFS_GetConfiguration +******************************************************************************** +* +* Summary: +* Returns the current configuration setting +* +* Parameters: +* None. +* +* Return: +* configuration. +* +*******************************************************************************/ +uint8 USBFS_GetConfiguration(void) +{ + return(USBFS_configuration); +} + + +/******************************************************************************* +* Function Name: USBFS_IsConfigurationChanged +******************************************************************************** +* +* Summary: +* Returns the clear on read configuration state. It is usefull when PC send +* double SET_CONFIGURATION request with same configuration number. +* +* Parameters: +* None. +* +* Return: +* Not zero value when new configuration has been changed, otherwise zero is +* returned. +* +* Global variables: +* USBFS_configurationChanged: This variable is set to one after +* SET_CONFIGURATION request and cleared in this function. +* +*******************************************************************************/ +uint8 USBFS_IsConfigurationChanged(void) +{ + uint8 res = 0u; + + if(USBFS_configurationChanged != 0u) + { + res = USBFS_configurationChanged; + USBFS_configurationChanged = 0u; + } + + return(res); +} + + +/******************************************************************************* +* Function Name: USBFS_GetInterfaceSetting +******************************************************************************** +* +* Summary: +* Returns the alternate setting from current interface +* +* Parameters: +* uint8 interfaceNumber, interface number +* +* Return: +* Alternate setting. +* +*******************************************************************************/ +uint8 USBFS_GetInterfaceSetting(uint8 interfaceNumber) + +{ + return(USBFS_interfaceSetting[interfaceNumber]); +} + + +/******************************************************************************* +* Function Name: USBFS_GetEPState +******************************************************************************** +* +* Summary: +* Returned the state of the requested endpoint. +* +* Parameters: +* epNumber: Endpoint Number +* +* Return: +* State of the requested endpoint. +* +*******************************************************************************/ +uint8 USBFS_GetEPState(uint8 epNumber) +{ + return(USBFS_EP[epNumber].apiEpState); +} + + +/******************************************************************************* +* Function Name: USBFS_GetEPCount +******************************************************************************** +* +* Summary: +* This function supports Data Endpoints only(EP1-EP8). +* Returns the transfer count for the requested endpoint. The value from +* the count registers includes 2 counts for the two byte checksum of the +* packet. This function subtracts the two counts. +* +* Parameters: +* epNumber: Data Endpoint Number. +* Valid values are between 1 and 8. +* +* Return: +* Returns the current byte count from the specified endpoint or 0 for an +* invalid endpoint. +* +*******************************************************************************/ +uint16 USBFS_GetEPCount(uint8 epNumber) +{ + uint8 ri; + uint16 result = 0u; + + if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); + + result = (uint8)(CY_GET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri)) & + USBFS_EPX_CNT0_MASK); + result = (result << 8u) | CY_GET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + ri)); + result -= USBFS_EPX_CNTX_CRC_COUNT; + } + return(result); +} + + +#if(USBFS_EP_MM != USBFS__EP_MANUAL) + + + /******************************************************************************* + * Function Name: USBFS_InitEP_DMA + ******************************************************************************** + * + * Summary: + * This function allocates and initializes a DMA channel to be used by the + * USBFS_LoadInEP() or USBFS_ReadOutEP() APIs for data + * transfer. + * + * Parameters: + * epNumber: Contains the data endpoint number. + * Valid values are between 1 and 8. + * *pData: Pointer to a data array that is related to the EP transfers. + * + * Return: + * None. + * + * Reentrant: + * No. + * + *******************************************************************************/ + void USBFS_InitEP_DMA(uint8 epNumber, const uint8 *pData) + + { + uint16 src; + uint16 dst; + #if (CY_PSOC3) /* PSoC 3 */ + src = HI16(CYDEV_SRAM_BASE); + dst = HI16(CYDEV_PERIPH_BASE); + pData = pData; + #else /* PSoC 5 */ + if((USBFS_EP[epNumber].addr & USBFS_DIR_IN) != 0u ) + { /* for the IN EP source is the SRAM memory buffer */ + src = HI16(pData); + dst = HI16(CYDEV_PERIPH_BASE); + } + else + { /* for the OUT EP source is the SIE register */ + src = HI16(CYDEV_PERIPH_BASE); + dst = HI16(pData); + } + #endif /* End C51 */ + switch(epNumber) + { + case USBFS_EP1: + #if(USBFS_DMA1_REMOVE == 0u) + USBFS_DmaChan[epNumber] = USBFS_ep1_DmaInitialize( + USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); + #endif /* End USBFS_DMA1_REMOVE */ + break; + case USBFS_EP2: + #if(USBFS_DMA2_REMOVE == 0u) + USBFS_DmaChan[epNumber] = USBFS_ep2_DmaInitialize( + USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); + #endif /* End USBFS_DMA2_REMOVE */ + break; + case USBFS_EP3: + #if(USBFS_DMA3_REMOVE == 0u) + USBFS_DmaChan[epNumber] = USBFS_ep3_DmaInitialize( + USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); + #endif /* End USBFS_DMA3_REMOVE */ + break; + case USBFS_EP4: + #if(USBFS_DMA4_REMOVE == 0u) + USBFS_DmaChan[epNumber] = USBFS_ep4_DmaInitialize( + USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); + #endif /* End USBFS_DMA4_REMOVE */ + break; + case USBFS_EP5: + #if(USBFS_DMA5_REMOVE == 0u) + USBFS_DmaChan[epNumber] = USBFS_ep5_DmaInitialize( + USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); + #endif /* End USBFS_DMA5_REMOVE */ + break; + case USBFS_EP6: + #if(USBFS_DMA6_REMOVE == 0u) + USBFS_DmaChan[epNumber] = USBFS_ep6_DmaInitialize( + USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); + #endif /* End USBFS_DMA6_REMOVE */ + break; + case USBFS_EP7: + #if(USBFS_DMA7_REMOVE == 0u) + USBFS_DmaChan[epNumber] = USBFS_ep7_DmaInitialize( + USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); + #endif /* End USBFS_DMA7_REMOVE */ + break; + case USBFS_EP8: + #if(USBFS_DMA8_REMOVE == 0u) + USBFS_DmaChan[epNumber] = USBFS_ep8_DmaInitialize( + USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); + #endif /* End USBFS_DMA8_REMOVE */ + break; + default: + /* Do not support EP0 DMA transfers */ + break; + } + if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + USBFS_DmaTd[epNumber] = CyDmaTdAllocate(); + } + } + + + /******************************************************************************* + * Function Name: USBFS_Stop_DMA + ******************************************************************************** + * + * Summary: Stops and free DMA + * + * Parameters: + * epNumber: Contains the data endpoint number or + * USBFS_MAX_EP to stop all DMAs + * + * Return: + * None. + * + * Reentrant: + * No. + * + *******************************************************************************/ + void USBFS_Stop_DMA(uint8 epNumber) + { + uint8 i; + i = (epNumber < USBFS_MAX_EP) ? epNumber : USBFS_EP1; + do + { + if(USBFS_DmaTd[i] != DMA_INVALID_TD) + { + (void) CyDmaChDisable(USBFS_DmaChan[i]); + CyDmaTdFree(USBFS_DmaTd[i]); + USBFS_DmaTd[i] = DMA_INVALID_TD; + } + i++; + }while((i < USBFS_MAX_EP) && (epNumber == USBFS_MAX_EP)); + } + +#endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ + + +/******************************************************************************* +* Function Name: USBFS_LoadInEP +******************************************************************************** +* +* Summary: +* Loads and enables the specified USB data endpoint for an IN interrupt or bulk +* transfer. +* +* Parameters: +* epNumber: Contains the data endpoint number. +* Valid values are between 1 and 8. +* *pData: A pointer to a data array from which the data for the endpoint space +* is loaded. +* length: The number of bytes to transfer from the array and then send as a +* result of an IN request. Valid values are between 0 and 512. +* +* Return: +* None. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length) + +{ + uint8 ri; + reg8 *p; + #if(USBFS_EP_MM == USBFS__EP_MANUAL) + uint16 i; + #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */ + + if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); + p = (reg8 *)(USBFS_ARB_RW1_DR_IND + ri); + + #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) + /* Limits length to available buffer space, auto MM could send packets up to 1024 bytes */ + if(length > (USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset)) + { + length = USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset; + } + #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */ + + /* Set the count and data toggle */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri), + (length >> 8u) | (USBFS_EP[epNumber].epToggle)); + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + ri), length & 0xFFu); + + #if(USBFS_EP_MM == USBFS__EP_MANUAL) + if(pData != NULL) + { + /* Copy the data using the arbiter data register */ + for (i = 0u; i < length; i++) + { + CY_SET_REG8(p, pData[i]); + } + } + USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; + /* Write the Mode register */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode); + #else + /* Init DMA if it was not initialized */ + if(USBFS_DmaTd[epNumber] == DMA_INVALID_TD) + { + USBFS_InitEP_DMA(epNumber, pData); + } + #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */ + + #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL) + USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; + if((pData != NULL) && (length > 0u)) + { + /* Enable DMA in mode2 for transferring data */ + (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); + (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, CY_DMA_DISABLE_TD, + TD_TERMIN_EN | TD_INC_SRC_ADR); + (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)pData), LO16((uint32)p)); + /* Enable the DMA */ + (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); + (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); + /* Generate DMA request */ + * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_DMA_REQ; + * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= ((uint8)(~USBFS_ARB_EPX_CFG_DMA_REQ)); + /* Mode register will be written in arb ISR after DMA transfer complete */ + } + else + { + /* When zero-length packet - write the Mode register directly */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode); + } + #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */ + + #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + if(pData != NULL) + { + /* Enable DMA in mode3 for transferring data */ + (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); + (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, + USBFS_DmaTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR); + (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)pData), LO16((uint32)p)); + /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */ + (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]); + /* Enable the DMA */ + (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); + (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); + } + else + { + USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; + if(length > 0u) + { + /* Set Data ready status, This will generate DMA request */ + * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY; + /* Mode register will be written in arb ISR(In Buffer Full) after first DMA transfer complete */ + } + else + { + /* When zero-length packet - write the Mode register directly */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode); + } + } + #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ + + } +} + + +/******************************************************************************* +* Function Name: USBFS_ReadOutEP +******************************************************************************** +* +* Summary: +* Read data from an endpoint. The application must call +* USBFS_GetEPState to see if an event is pending. +* +* Parameters: +* epNumber: Contains the data endpoint number. +* Valid values are between 1 and 8. +* pData: A pointer to a data array from which the data for the endpoint space +* is loaded. +* length: The number of bytes to transfer from the USB Out endpoint and loads +* it into data array. Valid values are between 0 and 1023. The function +* moves fewer than the requested number of bytes if the host sends +* fewer bytes than requested. +* +* Returns: +* Number of bytes received, 0 for an invalid endpoint. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length) + +{ + uint8 ri; + reg8 *p; + #if(USBFS_EP_MM == USBFS__EP_MANUAL) + uint16 i; + #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */ + #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) + uint16 xferCount; + #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */ + + if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP) && (pData != NULL)) + { + ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); + p = (reg8 *)(USBFS_ARB_RW1_DR_IND + ri); + + #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) + /* Determine which is smaller the requested data or the available data */ + xferCount = USBFS_GetEPCount(epNumber); + if (length > xferCount) + { + length = xferCount; + } + #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */ + + #if(USBFS_EP_MM == USBFS__EP_MANUAL) + /* Copy the data using the arbiter data register */ + for (i = 0u; i < length; i++) + { + pData[i] = CY_GET_REG8(p); + } + + /* (re)arming of OUT endpoint */ + USBFS_EnableOutEP(epNumber); + #else + /*Init DMA if it was not initialized */ + if(USBFS_DmaTd[epNumber] == DMA_INVALID_TD) + { + USBFS_InitEP_DMA(epNumber, pData); + } + #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */ + + #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL) + /* Enable DMA in mode2 for transferring data */ + (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); + (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, CY_DMA_DISABLE_TD, + TD_TERMIN_EN | TD_INC_DST_ADR); + (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)p), LO16((uint32)pData)); + /* Enable the DMA */ + (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); + (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); + + /* Generate DMA request */ + * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_DMA_REQ; + * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= ((uint8)(~USBFS_ARB_EPX_CFG_DMA_REQ)); + /* Out EP will be (re)armed in arb ISR after transfer complete */ + #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */ + + #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + /* Enable DMA in mode3 for transferring data */ + (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); + (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, USBFS_DmaTd[epNumber], + TD_TERMIN_EN | TD_INC_DST_ADR); + (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)p), LO16((uint32)pData)); + + /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */ + (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]); + /* Enable the DMA */ + (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); + (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); + /* Out EP will be (re)armed in arb ISR after transfer complete */ + #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ + + } + else + { + length = 0u; + } + + return(length); +} + + +/******************************************************************************* +* Function Name: USBFS_EnableOutEP +******************************************************************************** +* +* Summary: +* This function enables an OUT endpoint. It should not be +* called for an IN endpoint. +* +* Parameters: +* epNumber: Endpoint Number +* Valid values are between 1 and 8. +* +* Return: +* None. +* +* Global variables: +* USBFS_EP[epNumber].apiEpState - set to NO_EVENT_PENDING +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_EnableOutEP(uint8 epNumber) +{ + uint8 ri; + + if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); + USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; + /* Write the Mode register */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode); + } +} + + +/******************************************************************************* +* Function Name: USBFS_DisableOutEP +******************************************************************************** +* +* Summary: +* This function disables an OUT endpoint. It should not be +* called for an IN endpoint. +* +* Parameters: +* epNumber: Endpoint Number +* Valid values are between 1 and 8. +* +* Return: +* None. +* +*******************************************************************************/ +void USBFS_DisableOutEP(uint8 epNumber) +{ + uint8 ri ; + + if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); + /* Write the Mode register */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_OUT); + } +} + + +/******************************************************************************* +* Function Name: USBFS_Force +******************************************************************************** +* +* Summary: +* Forces the bus state +* +* Parameters: +* bState +* USBFS_FORCE_J +* USBFS_FORCE_K +* USBFS_FORCE_SE0 +* USBFS_FORCE_NONE +* +* Return: +* None. +* +*******************************************************************************/ +void USBFS_Force(uint8 bState) +{ + CY_SET_REG8(USBFS_USBIO_CR0_PTR, bState); +} + + +/******************************************************************************* +* Function Name: USBFS_GetEPAckState +******************************************************************************** +* +* Summary: +* Returns the ACK of the CR0 Register (ACKD) +* +* Parameters: +* epNumber: Endpoint Number +* Valid values are between 1 and 8. +* +* Returns +* 0 if nothing has been ACKD, non-=zero something has been ACKD +* +*******************************************************************************/ +uint8 USBFS_GetEPAckState(uint8 epNumber) +{ + uint8 ri; + uint8 cr = 0u; + + if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); + cr = CY_GET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri)) & USBFS_MODE_ACKD; + } + + return(cr); +} + + +/******************************************************************************* +* Function Name: USBFS_SetPowerStatus +******************************************************************************** +* +* Summary: +* Sets the device power status for reporting in the Get Device Status +* request +* +* Parameters: +* powerStatus: USBFS_DEVICE_STATUS_BUS_POWERED(0) - Bus Powered, +* USBFS_DEVICE_STATUS_SELF_POWERED(1) - Self Powered +* +* Return: +* None. +* +* Global variables: +* USBFS_deviceStatus - set power status +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_SetPowerStatus(uint8 powerStatus) +{ + if (powerStatus != USBFS_DEVICE_STATUS_BUS_POWERED) + { + USBFS_deviceStatus |= USBFS_DEVICE_STATUS_SELF_POWERED; + } + else + { + USBFS_deviceStatus &= ((uint8)(~USBFS_DEVICE_STATUS_SELF_POWERED)); + } +} + + +#if (USBFS_MON_VBUS == 1u) + + /******************************************************************************* + * Function Name: USBFS_VBusPresent + ******************************************************************************** + * + * Summary: + * Determines VBUS presence for Self Powered Devices. + * + * Parameters: + * None. + * + * Return: + * 1 if VBUS is present, otherwise 0. + * + *******************************************************************************/ + uint8 USBFS_VBusPresent(void) + { + return((0u != (CY_GET_REG8(USBFS_VBUS_PS_PTR) & USBFS_VBUS_MASK)) ? 1u : 0u); + } + +#endif /* USBFS_MON_VBUS */ + + +/******************************************************************************* +* Function Name: USBFS_RWUEnabled +******************************************************************************** +* +* Summary: +* Returns TRUE if Remote Wake Up is enabled, otherwise FALSE +* +* Parameters: +* None. +* +* Return: +* TRUE - Remote Wake Up Enabled +* FALSE - Remote Wake Up Disabled +* +* Global variables: +* USBFS_deviceStatus - checked to determine remote status +* +*******************************************************************************/ +uint8 USBFS_RWUEnabled(void) +{ + uint8 result = USBFS_FALSE; + if((USBFS_deviceStatus & USBFS_DEVICE_STATUS_REMOTE_WAKEUP) != 0u) + { + result = USBFS_TRUE; + } + + return(result); +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS.h new file mode 100644 index 00000000..41a8619d --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS.h @@ -0,0 +1,1189 @@ +/******************************************************************************* +* File Name: USBFS.h +* Version 2.60 +* +* Description: +* Header File for the USFS component. Contains prototypes and constant values. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_USBFS_USBFS_H) +#define CY_USBFS_USBFS_H + +#include "cytypes.h" +#include "cydevice_trm.h" +#include "cyfitter.h" +#include "CyLib.h" + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ + +/* Check to see if required defines such as CY_PSOC5LP are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5LP) + #error Component USBFS_v2_60 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5LP) */ + + +/*************************************** +* Memory Type Definitions +***************************************/ + +/* Renamed Type Definitions for backward compatibility. +* Should not be used in new designs. +*/ +#define USBFS_CODE CYCODE +#define USBFS_FAR CYFAR +#if defined(__C51__) || defined(__CX51__) + #define USBFS_DATA data + #define USBFS_XDATA xdata +#else + #define USBFS_DATA + #define USBFS_XDATA +#endif /* End __C51__ */ +#define USBFS_NULL NULL + + +/*************************************** +* Enumerated Types and Parameters +***************************************/ + +#define USBFS__EP_MANUAL 0 +#define USBFS__EP_DMAMANUAL 1 +#define USBFS__EP_DMAAUTO 2 + +#define USBFS__MA_STATIC 0 +#define USBFS__MA_DYNAMIC 1 + + + +/*************************************** +* Initial Parameter Constants +***************************************/ + +#define USBFS_NUM_DEVICES (1u) +#define USBFS_ENABLE_DESCRIPTOR_STRINGS +#define USBFS_ENABLE_SN_STRING +#define USBFS_ENABLE_STRINGS +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF_SIZE (65u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_NUM_IN_RPTS (1u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF_SIZE (65u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_NUM_OUT_RPTS (1u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_COUNT (1u) +#define USBFS_ENABLE_HID_CLASS +#define USBFS_HID_RPT_1_SIZE_LSB (0x24u) +#define USBFS_HID_RPT_1_SIZE_MSB (0x00u) +#define USBFS_MAX_REPORTID_NUMBER (0u) + +#define USBFS_MON_VBUS (0u) +#define USBFS_EXTERN_VBUS (0u) +#define USBFS_EXTERN_VND (0u) +#define USBFS_EXTERN_CLS (0u) +#define USBFS_MAX_INTERFACES_NUMBER (1u) +#define USBFS_EP0_ISR_REMOVE (0u) +#define USBFS_EP1_ISR_REMOVE (0u) +#define USBFS_EP2_ISR_REMOVE (0u) +#define USBFS_EP3_ISR_REMOVE (1u) +#define USBFS_EP4_ISR_REMOVE (1u) +#define USBFS_EP5_ISR_REMOVE (1u) +#define USBFS_EP6_ISR_REMOVE (1u) +#define USBFS_EP7_ISR_REMOVE (1u) +#define USBFS_EP8_ISR_REMOVE (1u) +#define USBFS_EP_MM (0u) +#define USBFS_EP_MA (0u) +#define USBFS_DMA1_REMOVE (1u) +#define USBFS_DMA2_REMOVE (1u) +#define USBFS_DMA3_REMOVE (1u) +#define USBFS_DMA4_REMOVE (1u) +#define USBFS_DMA5_REMOVE (1u) +#define USBFS_DMA6_REMOVE (1u) +#define USBFS_DMA7_REMOVE (1u) +#define USBFS_DMA8_REMOVE (1u) +#define USBFS_SOF_ISR_REMOVE (0u) +#define USBFS_ARB_ISR_REMOVE (0u) +#define USBFS_DP_ISR_REMOVE (0u) +#define USBFS_ENABLE_CDC_CLASS_API (1u) +#define USBFS_ENABLE_MIDI_API (1u) +#define USBFS_MIDI_EXT_MODE (0u) + + +/*************************************** +* Data Struct Definition +***************************************/ + +typedef struct +{ + uint8 attrib; + uint8 apiEpState; + uint8 hwEpState; + uint8 epToggle; + uint8 addr; + uint8 epMode; + uint16 buffOffset; + uint16 bufferSize; + uint8 interface; +} T_USBFS_EP_CTL_BLOCK; + +typedef struct +{ + uint8 interface; + uint8 altSetting; + uint8 addr; + uint8 attributes; + uint16 bufferSize; + uint8 bMisc; +} T_USBFS_EP_SETTINGS_BLOCK; + +typedef struct +{ + uint8 status; + uint16 length; +} T_USBFS_XFER_STATUS_BLOCK; + +typedef struct +{ + uint16 count; + volatile uint8 *pData; + T_USBFS_XFER_STATUS_BLOCK *pStatusBlock; +} T_USBFS_TD; + + +typedef struct +{ + uint8 c; + const void *p_list; +} T_USBFS_LUT; + +/* Resume/Suspend API Support */ +typedef struct +{ + uint8 enableState; + uint8 mode; +} USBFS_BACKUP_STRUCT; + + +/* Renamed structure fields for backward compatibility. +* Should not be used in new designs. +*/ +#define wBuffOffset buffOffset +#define wBufferSize bufferSize +#define bStatus status +#define wLength length +#define wCount count + +/* Renamed global variable for backward compatibility. +* Should not be used in new designs. +*/ +#define CurrentTD USBFS_currentTD + + +/*************************************** +* Function Prototypes +***************************************/ + +void USBFS_Start(uint8 device, uint8 mode) ; +void USBFS_Init(void) ; +void USBFS_InitComponent(uint8 device, uint8 mode) ; +void USBFS_Stop(void) ; +uint8 USBFS_CheckActivity(void) ; +uint8 USBFS_GetConfiguration(void) ; +uint8 USBFS_IsConfigurationChanged(void) ; +uint8 USBFS_GetInterfaceSetting(uint8 interfaceNumber) + ; +uint8 USBFS_GetEPState(uint8 epNumber) ; +uint16 USBFS_GetEPCount(uint8 epNumber) ; +void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length) + ; +uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length) + ; +void USBFS_EnableOutEP(uint8 epNumber) ; +void USBFS_DisableOutEP(uint8 epNumber) ; +void USBFS_Force(uint8 bState) ; +uint8 USBFS_GetEPAckState(uint8 epNumber) ; +void USBFS_SetPowerStatus(uint8 powerStatus) ; +uint8 USBFS_RWUEnabled(void) ; +void USBFS_TerminateEP(uint8 ep) ; + +void USBFS_Suspend(void) ; +void USBFS_Resume(void) ; + +#if defined(USBFS_ENABLE_FWSN_STRING) + void USBFS_SerialNumString(uint8 snString[]) ; +#endif /* USBFS_ENABLE_FWSN_STRING */ +#if (USBFS_MON_VBUS == 1u) + uint8 USBFS_VBusPresent(void) ; +#endif /* End USBFS_MON_VBUS */ + +#if defined(CYDEV_BOOTLOADER_IO_COMP) && ((CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) || \ + (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface)) + + void USBFS_CyBtldrCommStart(void) ; + void USBFS_CyBtldrCommStop(void) ; + void USBFS_CyBtldrCommReset(void) ; + cystatus USBFS_CyBtldrCommWrite(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL + ; + cystatus USBFS_CyBtldrCommRead( uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL + ; + + #define USBFS_BTLDR_SIZEOF_WRITE_BUFFER (64u) /* EP 1 OUT */ + #define USBFS_BTLDR_SIZEOF_READ_BUFFER (64u) /* EP 2 IN */ + #define USBFS_BTLDR_MAX_PACKET_SIZE USBFS_BTLDR_SIZEOF_WRITE_BUFFER + + /* These defines active if used USBFS interface as an + * IO Component for bootloading. When Custom_Interface selected + * in Bootloder configuration as the IO Component, user must + * provide these functions + */ + #if (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) + #define CyBtldrCommStart USBFS_CyBtldrCommStart + #define CyBtldrCommStop USBFS_CyBtldrCommStop + #define CyBtldrCommReset USBFS_CyBtldrCommReset + #define CyBtldrCommWrite USBFS_CyBtldrCommWrite + #define CyBtldrCommRead USBFS_CyBtldrCommRead + #endif /*End CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */ + +#endif /* End CYDEV_BOOTLOADER_IO_COMP */ + +#if(USBFS_EP_MM != USBFS__EP_MANUAL) + void USBFS_InitEP_DMA(uint8 epNumber, const uint8 *pData) + ; + void USBFS_Stop_DMA(uint8 epNumber) ; +#endif /* End USBFS_EP_MM != USBFS__EP_MANUAL) */ + +#if defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u) + void USBFS_MIDI_EP_Init(void) ; + + #if (USBFS_MIDI_IN_BUFF_SIZE > 0) + void USBFS_MIDI_IN_Service(void) ; + uint8 USBFS_PutUsbMidiIn(uint8 ic, const uint8 midiMsg[], uint8 cable) + ; + #endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */ + + #if (USBFS_MIDI_OUT_BUFF_SIZE > 0) + void USBFS_MIDI_OUT_EP_Service(void) ; + #endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */ + +#endif /* End USBFS_ENABLE_MIDI_API != 0u */ + +/* Renamed Functions for backward compatibility. +* Should not be used in new designs. +*/ + +#define USBFS_bCheckActivity USBFS_CheckActivity +#define USBFS_bGetConfiguration USBFS_GetConfiguration +#define USBFS_bGetInterfaceSetting USBFS_GetInterfaceSetting +#define USBFS_bGetEPState USBFS_GetEPState +#define USBFS_wGetEPCount USBFS_GetEPCount +#define USBFS_bGetEPAckState USBFS_GetEPAckState +#define USBFS_bRWUEnabled USBFS_RWUEnabled +#define USBFS_bVBusPresent USBFS_VBusPresent + +#define USBFS_bConfiguration USBFS_configuration +#define USBFS_bInterfaceSetting USBFS_interfaceSetting +#define USBFS_bDeviceAddress USBFS_deviceAddress +#define USBFS_bDeviceStatus USBFS_deviceStatus +#define USBFS_bDevice USBFS_device +#define USBFS_bTransferState USBFS_transferState +#define USBFS_bLastPacketSize USBFS_lastPacketSize + +#define USBFS_LoadEP USBFS_LoadInEP +#define USBFS_LoadInISOCEP USBFS_LoadInEP +#define USBFS_EnableOutISOCEP USBFS_EnableOutEP + +#define USBFS_SetVector CyIntSetVector +#define USBFS_SetPriority CyIntSetPriority +#define USBFS_EnableInt CyIntEnable + + +/*************************************** +* API Constants +***************************************/ + +#define USBFS_EP0 (0u) +#define USBFS_EP1 (1u) +#define USBFS_EP2 (2u) +#define USBFS_EP3 (3u) +#define USBFS_EP4 (4u) +#define USBFS_EP5 (5u) +#define USBFS_EP6 (6u) +#define USBFS_EP7 (7u) +#define USBFS_EP8 (8u) +#define USBFS_MAX_EP (9u) + +#define USBFS_TRUE (1u) +#define USBFS_FALSE (0u) + +#define USBFS_NO_EVENT_ALLOWED (2u) +#define USBFS_EVENT_PENDING (1u) +#define USBFS_NO_EVENT_PENDING (0u) + +#define USBFS_IN_BUFFER_FULL USBFS_NO_EVENT_PENDING +#define USBFS_IN_BUFFER_EMPTY USBFS_EVENT_PENDING +#define USBFS_OUT_BUFFER_FULL USBFS_EVENT_PENDING +#define USBFS_OUT_BUFFER_EMPTY USBFS_NO_EVENT_PENDING + +#define USBFS_FORCE_J (0xA0u) +#define USBFS_FORCE_K (0x80u) +#define USBFS_FORCE_SE0 (0xC0u) +#define USBFS_FORCE_NONE (0x00u) + +#define USBFS_IDLE_TIMER_RUNNING (0x02u) +#define USBFS_IDLE_TIMER_EXPIRED (0x01u) +#define USBFS_IDLE_TIMER_INDEFINITE (0x00u) + +#define USBFS_DEVICE_STATUS_BUS_POWERED (0x00u) +#define USBFS_DEVICE_STATUS_SELF_POWERED (0x01u) + +#define USBFS_3V_OPERATION (0x00u) +#define USBFS_5V_OPERATION (0x01u) +#define USBFS_DWR_VDDD_OPERATION (0x02u) + +#define USBFS_MODE_DISABLE (0x00u) +#define USBFS_MODE_NAK_IN_OUT (0x01u) +#define USBFS_MODE_STATUS_OUT_ONLY (0x02u) +#define USBFS_MODE_STALL_IN_OUT (0x03u) +#define USBFS_MODE_RESERVED_0100 (0x04u) +#define USBFS_MODE_ISO_OUT (0x05u) +#define USBFS_MODE_STATUS_IN_ONLY (0x06u) +#define USBFS_MODE_ISO_IN (0x07u) +#define USBFS_MODE_NAK_OUT (0x08u) +#define USBFS_MODE_ACK_OUT (0x09u) +#define USBFS_MODE_RESERVED_1010 (0x0Au) +#define USBFS_MODE_ACK_OUT_STATUS_IN (0x0Bu) +#define USBFS_MODE_NAK_IN (0x0Cu) +#define USBFS_MODE_ACK_IN (0x0Du) +#define USBFS_MODE_RESERVED_1110 (0x0Eu) +#define USBFS_MODE_ACK_IN_STATUS_OUT (0x0Fu) +#define USBFS_MODE_MASK (0x0Fu) +#define USBFS_MODE_STALL_DATA_EP (0x80u) + +#define USBFS_MODE_ACKD (0x10u) +#define USBFS_MODE_OUT_RCVD (0x20u) +#define USBFS_MODE_IN_RCVD (0x40u) +#define USBFS_MODE_SETUP_RCVD (0x80u) + +#define USBFS_RQST_TYPE_MASK (0x60u) +#define USBFS_RQST_TYPE_STD (0x00u) +#define USBFS_RQST_TYPE_CLS (0x20u) +#define USBFS_RQST_TYPE_VND (0x40u) +#define USBFS_RQST_DIR_MASK (0x80u) +#define USBFS_RQST_DIR_D2H (0x80u) +#define USBFS_RQST_DIR_H2D (0x00u) +#define USBFS_RQST_RCPT_MASK (0x03u) +#define USBFS_RQST_RCPT_DEV (0x00u) +#define USBFS_RQST_RCPT_IFC (0x01u) +#define USBFS_RQST_RCPT_EP (0x02u) +#define USBFS_RQST_RCPT_OTHER (0x03u) + +/* USB Class Codes */ +#define USBFS_CLASS_DEVICE (0x00u) /* Use class code info from Interface Descriptors */ +#define USBFS_CLASS_AUDIO (0x01u) /* Audio device */ +#define USBFS_CLASS_CDC (0x02u) /* Communication device class */ +#define USBFS_CLASS_HID (0x03u) /* Human Interface Device */ +#define USBFS_CLASS_PDC (0x05u) /* Physical device class */ +#define USBFS_CLASS_IMAGE (0x06u) /* Still Imaging device */ +#define USBFS_CLASS_PRINTER (0x07u) /* Printer device */ +#define USBFS_CLASS_MSD (0x08u) /* Mass Storage device */ +#define USBFS_CLASS_HUB (0x09u) /* Full/Hi speed Hub */ +#define USBFS_CLASS_CDC_DATA (0x0Au) /* CDC data device */ +#define USBFS_CLASS_SMART_CARD (0x0Bu) /* Smart Card device */ +#define USBFS_CLASS_CSD (0x0Du) /* Content Security device */ +#define USBFS_CLASS_VIDEO (0x0Eu) /* Video device */ +#define USBFS_CLASS_PHD (0x0Fu) /* Personal Healthcare device */ +#define USBFS_CLASS_WIRELESSD (0xDCu) /* Wireless Controller */ +#define USBFS_CLASS_MIS (0xE0u) /* Miscellaneous */ +#define USBFS_CLASS_APP (0xEFu) /* Application Specific */ +#define USBFS_CLASS_VENDOR (0xFFu) /* Vendor specific */ + + +/* Standard Request Types (Table 9-4) */ +#define USBFS_GET_STATUS (0x00u) +#define USBFS_CLEAR_FEATURE (0x01u) +#define USBFS_SET_FEATURE (0x03u) +#define USBFS_SET_ADDRESS (0x05u) +#define USBFS_GET_DESCRIPTOR (0x06u) +#define USBFS_SET_DESCRIPTOR (0x07u) +#define USBFS_GET_CONFIGURATION (0x08u) +#define USBFS_SET_CONFIGURATION (0x09u) +#define USBFS_GET_INTERFACE (0x0Au) +#define USBFS_SET_INTERFACE (0x0Bu) +#define USBFS_SYNCH_FRAME (0x0Cu) + +/* Vendor Specific Request Types */ +/* Request for Microsoft OS String Descriptor */ +#define USBFS_GET_EXTENDED_CONFIG_DESCRIPTOR (0x01u) + +/* Descriptor Types (Table 9-5) */ +#define USBFS_DESCR_DEVICE (1u) +#define USBFS_DESCR_CONFIG (2u) +#define USBFS_DESCR_STRING (3u) +#define USBFS_DESCR_INTERFACE (4u) +#define USBFS_DESCR_ENDPOINT (5u) +#define USBFS_DESCR_DEVICE_QUALIFIER (6u) +#define USBFS_DESCR_OTHER_SPEED (7u) +#define USBFS_DESCR_INTERFACE_POWER (8u) + +/* Device Descriptor Defines */ +#define USBFS_DEVICE_DESCR_LENGTH (18u) +#define USBFS_DEVICE_DESCR_SN_SHIFT (16u) + +/* Config Descriptor Shifts and Masks */ +#define USBFS_CONFIG_DESCR_LENGTH (0u) +#define USBFS_CONFIG_DESCR_TYPE (1u) +#define USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW (2u) +#define USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI (3u) +#define USBFS_CONFIG_DESCR_NUM_INTERFACES (4u) +#define USBFS_CONFIG_DESCR_CONFIG_VALUE (5u) +#define USBFS_CONFIG_DESCR_CONFIGURATION (6u) +#define USBFS_CONFIG_DESCR_ATTRIB (7u) +#define USBFS_CONFIG_DESCR_ATTRIB_SELF_POWERED (0x40u) +#define USBFS_CONFIG_DESCR_ATTRIB_RWU_EN (0x20u) + +/* Feature Selectors (Table 9-6) */ +#define USBFS_DEVICE_REMOTE_WAKEUP (0x01u) +#define USBFS_ENDPOINT_HALT (0x00u) +#define USBFS_TEST_MODE (0x02u) + +/* USB Device Status (Figure 9-4) */ +#define USBFS_DEVICE_STATUS_BUS_POWERED (0x00u) +#define USBFS_DEVICE_STATUS_SELF_POWERED (0x01u) +#define USBFS_DEVICE_STATUS_REMOTE_WAKEUP (0x02u) + +/* USB Endpoint Status (Figure 9-4) */ +#define USBFS_ENDPOINT_STATUS_HALT (0x01u) + +/* USB Endpoint Directions */ +#define USBFS_DIR_IN (0x80u) +#define USBFS_DIR_OUT (0x00u) +#define USBFS_DIR_UNUSED (0x7Fu) + +/* USB Endpoint Attributes */ +#define USBFS_EP_TYPE_CTRL (0x00u) +#define USBFS_EP_TYPE_ISOC (0x01u) +#define USBFS_EP_TYPE_BULK (0x02u) +#define USBFS_EP_TYPE_INT (0x03u) +#define USBFS_EP_TYPE_MASK (0x03u) + +#define USBFS_EP_SYNC_TYPE_NO_SYNC (0x00u) +#define USBFS_EP_SYNC_TYPE_ASYNC (0x04u) +#define USBFS_EP_SYNC_TYPE_ADAPTIVE (0x08u) +#define USBFS_EP_SYNC_TYPE_SYNCHRONOUS (0x0Cu) +#define USBFS_EP_SYNC_TYPE_MASK (0x0Cu) + +#define USBFS_EP_USAGE_TYPE_DATA (0x00u) +#define USBFS_EP_USAGE_TYPE_FEEDBACK (0x10u) +#define USBFS_EP_USAGE_TYPE_IMPLICIT (0x20u) +#define USBFS_EP_USAGE_TYPE_RESERVED (0x30u) +#define USBFS_EP_USAGE_TYPE_MASK (0x30u) + +/* Endpoint Status defines */ +#define USBFS_EP_STATUS_LENGTH (0x02u) + +/* Endpoint Device defines */ +#define USBFS_DEVICE_STATUS_LENGTH (0x02u) + +#define USBFS_STATUS_LENGTH_MAX \ + ( (USBFS_EP_STATUS_LENGTH > USBFS_DEVICE_STATUS_LENGTH) ? \ + USBFS_EP_STATUS_LENGTH : USBFS_DEVICE_STATUS_LENGTH ) +/* Transfer Completion Notification */ +#define USBFS_XFER_IDLE (0x00u) +#define USBFS_XFER_STATUS_ACK (0x01u) +#define USBFS_XFER_PREMATURE (0x02u) +#define USBFS_XFER_ERROR (0x03u) + +/* Driver State defines */ +#define USBFS_TRANS_STATE_IDLE (0x00u) +#define USBFS_TRANS_STATE_CONTROL_READ (0x02u) +#define USBFS_TRANS_STATE_CONTROL_WRITE (0x04u) +#define USBFS_TRANS_STATE_NO_DATA_CONTROL (0x06u) + +/* String Descriptor defines */ +#define USBFS_STRING_MSOS (0xEEu) +#define USBFS_MSOS_DESCRIPTOR_LENGTH (18u) +#define USBFS_MSOS_CONF_DESCR_LENGTH (40u) + +#if(USBFS_EP_MM == USBFS__EP_DMAMANUAL) + /* DMA manual mode defines */ + #define USBFS_DMA_BYTES_PER_BURST (0u) + #define USBFS_DMA_REQUEST_PER_BURST (0u) +#endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */ +#if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + /* DMA automatic mode defines */ + #define USBFS_DMA_BYTES_PER_BURST (32u) + /* BUF_SIZE-BYTES_PER_BURST examples: 55-32 bytes 44-16 bytes 33-8 bytes 22-4 bytes 11-2 bytes */ + #define USBFS_DMA_BUF_SIZE (0x55u) + #define USBFS_DMA_REQUEST_PER_BURST (1u) +#endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ + +/* DIE ID string descriptor defines */ +#if defined(USBFS_ENABLE_IDSN_STRING) + #define USBFS_IDSN_DESCR_LENGTH (0x22u) +#endif /* USBFS_ENABLE_IDSN_STRING */ + + +/*************************************** +* External data references +***************************************/ + +extern uint8 USBFS_initVar; +extern volatile uint8 USBFS_device; +extern volatile uint8 USBFS_transferState; +extern volatile uint8 USBFS_configuration; +extern volatile uint8 USBFS_configurationChanged; +extern volatile uint8 USBFS_deviceStatus; + +/* HID Variables */ +#if defined(USBFS_ENABLE_HID_CLASS) + extern volatile uint8 USBFS_hidProtocol[USBFS_MAX_INTERFACES_NUMBER]; + extern volatile uint8 USBFS_hidIdleRate[USBFS_MAX_INTERFACES_NUMBER]; + extern volatile uint8 USBFS_hidIdleTimer[USBFS_MAX_INTERFACES_NUMBER]; +#endif /* USBFS_ENABLE_HID_CLASS */ + + +/*************************************** +* Registers +***************************************/ + +#define USBFS_ARB_CFG_PTR ( (reg8 *) USBFS_USB__ARB_CFG) +#define USBFS_ARB_CFG_REG (* (reg8 *) USBFS_USB__ARB_CFG) + +#define USBFS_ARB_EP1_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP1_CFG) +#define USBFS_ARB_EP1_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP1_CFG) +#define USBFS_ARB_EP1_CFG_IND USBFS_USB__ARB_EP1_CFG +#define USBFS_ARB_EP1_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP1_INT_EN) +#define USBFS_ARB_EP1_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP1_INT_EN) +#define USBFS_ARB_EP1_INT_EN_IND USBFS_USB__ARB_EP1_INT_EN +#define USBFS_ARB_EP1_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP1_SR) +#define USBFS_ARB_EP1_SR_REG (* (reg8 *) USBFS_USB__ARB_EP1_SR) +#define USBFS_ARB_EP1_SR_IND USBFS_USB__ARB_EP1_SR + +#define USBFS_ARB_EP2_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP2_CFG) +#define USBFS_ARB_EP2_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP2_CFG) +#define USBFS_ARB_EP2_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP2_INT_EN) +#define USBFS_ARB_EP2_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP2_INT_EN) +#define USBFS_ARB_EP2_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP2_SR) +#define USBFS_ARB_EP2_SR_REG (* (reg8 *) USBFS_USB__ARB_EP2_SR) + +#define USBFS_ARB_EP3_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP3_CFG) +#define USBFS_ARB_EP3_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP3_CFG) +#define USBFS_ARB_EP3_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP3_INT_EN) +#define USBFS_ARB_EP3_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP3_INT_EN) +#define USBFS_ARB_EP3_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP3_SR) +#define USBFS_ARB_EP3_SR_REG (* (reg8 *) USBFS_USB__ARB_EP3_SR) + +#define USBFS_ARB_EP4_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP4_CFG) +#define USBFS_ARB_EP4_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP4_CFG) +#define USBFS_ARB_EP4_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP4_INT_EN) +#define USBFS_ARB_EP4_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP4_INT_EN) +#define USBFS_ARB_EP4_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP4_SR) +#define USBFS_ARB_EP4_SR_REG (* (reg8 *) USBFS_USB__ARB_EP4_SR) + +#define USBFS_ARB_EP5_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP5_CFG) +#define USBFS_ARB_EP5_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP5_CFG) +#define USBFS_ARB_EP5_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP5_INT_EN) +#define USBFS_ARB_EP5_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP5_INT_EN) +#define USBFS_ARB_EP5_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP5_SR) +#define USBFS_ARB_EP5_SR_REG (* (reg8 *) USBFS_USB__ARB_EP5_SR) + +#define USBFS_ARB_EP6_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP6_CFG) +#define USBFS_ARB_EP6_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP6_CFG) +#define USBFS_ARB_EP6_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP6_INT_EN) +#define USBFS_ARB_EP6_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP6_INT_EN) +#define USBFS_ARB_EP6_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP6_SR) +#define USBFS_ARB_EP6_SR_REG (* (reg8 *) USBFS_USB__ARB_EP6_SR) + +#define USBFS_ARB_EP7_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP7_CFG) +#define USBFS_ARB_EP7_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP7_CFG) +#define USBFS_ARB_EP7_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP7_INT_EN) +#define USBFS_ARB_EP7_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP7_INT_EN) +#define USBFS_ARB_EP7_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP7_SR) +#define USBFS_ARB_EP7_SR_REG (* (reg8 *) USBFS_USB__ARB_EP7_SR) + +#define USBFS_ARB_EP8_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP8_CFG) +#define USBFS_ARB_EP8_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP8_CFG) +#define USBFS_ARB_EP8_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP8_INT_EN) +#define USBFS_ARB_EP8_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP8_INT_EN) +#define USBFS_ARB_EP8_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP8_SR) +#define USBFS_ARB_EP8_SR_REG (* (reg8 *) USBFS_USB__ARB_EP8_SR) + +#define USBFS_ARB_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_INT_EN) +#define USBFS_ARB_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_INT_EN) +#define USBFS_ARB_INT_SR_PTR ( (reg8 *) USBFS_USB__ARB_INT_SR) +#define USBFS_ARB_INT_SR_REG (* (reg8 *) USBFS_USB__ARB_INT_SR) + +#define USBFS_ARB_RW1_DR_PTR ((reg8 *) USBFS_USB__ARB_RW1_DR) +#define USBFS_ARB_RW1_DR_IND USBFS_USB__ARB_RW1_DR +#define USBFS_ARB_RW1_RA_PTR ((reg8 *) USBFS_USB__ARB_RW1_RA) +#define USBFS_ARB_RW1_RA_IND USBFS_USB__ARB_RW1_RA +#define USBFS_ARB_RW1_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW1_RA_MSB) +#define USBFS_ARB_RW1_RA_MSB_IND USBFS_USB__ARB_RW1_RA_MSB +#define USBFS_ARB_RW1_WA_PTR ((reg8 *) USBFS_USB__ARB_RW1_WA) +#define USBFS_ARB_RW1_WA_IND USBFS_USB__ARB_RW1_WA +#define USBFS_ARB_RW1_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW1_WA_MSB) +#define USBFS_ARB_RW1_WA_MSB_IND USBFS_USB__ARB_RW1_WA_MSB + +#define USBFS_ARB_RW2_DR_PTR ((reg8 *) USBFS_USB__ARB_RW2_DR) +#define USBFS_ARB_RW2_RA_PTR ((reg8 *) USBFS_USB__ARB_RW2_RA) +#define USBFS_ARB_RW2_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW2_RA_MSB) +#define USBFS_ARB_RW2_WA_PTR ((reg8 *) USBFS_USB__ARB_RW2_WA) +#define USBFS_ARB_RW2_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW2_WA_MSB) + +#define USBFS_ARB_RW3_DR_PTR ((reg8 *) USBFS_USB__ARB_RW3_DR) +#define USBFS_ARB_RW3_RA_PTR ((reg8 *) USBFS_USB__ARB_RW3_RA) +#define USBFS_ARB_RW3_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW3_RA_MSB) +#define USBFS_ARB_RW3_WA_PTR ((reg8 *) USBFS_USB__ARB_RW3_WA) +#define USBFS_ARB_RW3_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW3_WA_MSB) + +#define USBFS_ARB_RW4_DR_PTR ((reg8 *) USBFS_USB__ARB_RW4_DR) +#define USBFS_ARB_RW4_RA_PTR ((reg8 *) USBFS_USB__ARB_RW4_RA) +#define USBFS_ARB_RW4_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW4_RA_MSB) +#define USBFS_ARB_RW4_WA_PTR ((reg8 *) USBFS_USB__ARB_RW4_WA) +#define USBFS_ARB_RW4_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW4_WA_MSB) + +#define USBFS_ARB_RW5_DR_PTR ((reg8 *) USBFS_USB__ARB_RW5_DR) +#define USBFS_ARB_RW5_RA_PTR ((reg8 *) USBFS_USB__ARB_RW5_RA) +#define USBFS_ARB_RW5_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW5_RA_MSB) +#define USBFS_ARB_RW5_WA_PTR ((reg8 *) USBFS_USB__ARB_RW5_WA) +#define USBFS_ARB_RW5_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW5_WA_MSB) + +#define USBFS_ARB_RW6_DR_PTR ((reg8 *) USBFS_USB__ARB_RW6_DR) +#define USBFS_ARB_RW6_RA_PTR ((reg8 *) USBFS_USB__ARB_RW6_RA) +#define USBFS_ARB_RW6_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW6_RA_MSB) +#define USBFS_ARB_RW6_WA_PTR ((reg8 *) USBFS_USB__ARB_RW6_WA) +#define USBFS_ARB_RW6_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW6_WA_MSB) + +#define USBFS_ARB_RW7_DR_PTR ((reg8 *) USBFS_USB__ARB_RW7_DR) +#define USBFS_ARB_RW7_RA_PTR ((reg8 *) USBFS_USB__ARB_RW7_RA) +#define USBFS_ARB_RW7_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW7_RA_MSB) +#define USBFS_ARB_RW7_WA_PTR ((reg8 *) USBFS_USB__ARB_RW7_WA) +#define USBFS_ARB_RW7_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW7_WA_MSB) + +#define USBFS_ARB_RW8_DR_PTR ((reg8 *) USBFS_USB__ARB_RW8_DR) +#define USBFS_ARB_RW8_RA_PTR ((reg8 *) USBFS_USB__ARB_RW8_RA) +#define USBFS_ARB_RW8_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW8_RA_MSB) +#define USBFS_ARB_RW8_WA_PTR ((reg8 *) USBFS_USB__ARB_RW8_WA) +#define USBFS_ARB_RW8_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW8_WA_MSB) + +#define USBFS_BUF_SIZE_PTR ( (reg8 *) USBFS_USB__BUF_SIZE) +#define USBFS_BUF_SIZE_REG (* (reg8 *) USBFS_USB__BUF_SIZE) +#define USBFS_BUS_RST_CNT_PTR ( (reg8 *) USBFS_USB__BUS_RST_CNT) +#define USBFS_BUS_RST_CNT_REG (* (reg8 *) USBFS_USB__BUS_RST_CNT) +#define USBFS_CWA_PTR ( (reg8 *) USBFS_USB__CWA) +#define USBFS_CWA_REG (* (reg8 *) USBFS_USB__CWA) +#define USBFS_CWA_MSB_PTR ( (reg8 *) USBFS_USB__CWA_MSB) +#define USBFS_CWA_MSB_REG (* (reg8 *) USBFS_USB__CWA_MSB) +#define USBFS_CR0_PTR ( (reg8 *) USBFS_USB__CR0) +#define USBFS_CR0_REG (* (reg8 *) USBFS_USB__CR0) +#define USBFS_CR1_PTR ( (reg8 *) USBFS_USB__CR1) +#define USBFS_CR1_REG (* (reg8 *) USBFS_USB__CR1) + +#define USBFS_DMA_THRES_PTR ( (reg8 *) USBFS_USB__DMA_THRES) +#define USBFS_DMA_THRES_REG (* (reg8 *) USBFS_USB__DMA_THRES) +#define USBFS_DMA_THRES_MSB_PTR ( (reg8 *) USBFS_USB__DMA_THRES_MSB) +#define USBFS_DMA_THRES_MSB_REG (* (reg8 *) USBFS_USB__DMA_THRES_MSB) + +#define USBFS_EP_ACTIVE_PTR ( (reg8 *) USBFS_USB__EP_ACTIVE) +#define USBFS_EP_ACTIVE_REG (* (reg8 *) USBFS_USB__EP_ACTIVE) +#define USBFS_EP_TYPE_PTR ( (reg8 *) USBFS_USB__EP_TYPE) +#define USBFS_EP_TYPE_REG (* (reg8 *) USBFS_USB__EP_TYPE) + +#define USBFS_EP0_CNT_PTR ( (reg8 *) USBFS_USB__EP0_CNT) +#define USBFS_EP0_CNT_REG (* (reg8 *) USBFS_USB__EP0_CNT) +#define USBFS_EP0_CR_PTR ( (reg8 *) USBFS_USB__EP0_CR) +#define USBFS_EP0_CR_REG (* (reg8 *) USBFS_USB__EP0_CR) +#define USBFS_EP0_DR0_PTR ( (reg8 *) USBFS_USB__EP0_DR0) +#define USBFS_EP0_DR0_REG (* (reg8 *) USBFS_USB__EP0_DR0) +#define USBFS_EP0_DR0_IND USBFS_USB__EP0_DR0 +#define USBFS_EP0_DR1_PTR ( (reg8 *) USBFS_USB__EP0_DR1) +#define USBFS_EP0_DR1_REG (* (reg8 *) USBFS_USB__EP0_DR1) +#define USBFS_EP0_DR2_PTR ( (reg8 *) USBFS_USB__EP0_DR2) +#define USBFS_EP0_DR2_REG (* (reg8 *) USBFS_USB__EP0_DR2) +#define USBFS_EP0_DR3_PTR ( (reg8 *) USBFS_USB__EP0_DR3) +#define USBFS_EP0_DR3_REG (* (reg8 *) USBFS_USB__EP0_DR3) +#define USBFS_EP0_DR4_PTR ( (reg8 *) USBFS_USB__EP0_DR4) +#define USBFS_EP0_DR4_REG (* (reg8 *) USBFS_USB__EP0_DR4) +#define USBFS_EP0_DR5_PTR ( (reg8 *) USBFS_USB__EP0_DR5) +#define USBFS_EP0_DR5_REG (* (reg8 *) USBFS_USB__EP0_DR5) +#define USBFS_EP0_DR6_PTR ( (reg8 *) USBFS_USB__EP0_DR6) +#define USBFS_EP0_DR6_REG (* (reg8 *) USBFS_USB__EP0_DR6) +#define USBFS_EP0_DR7_PTR ( (reg8 *) USBFS_USB__EP0_DR7) +#define USBFS_EP0_DR7_REG (* (reg8 *) USBFS_USB__EP0_DR7) + +#define USBFS_OSCLK_DR0_PTR ( (reg8 *) USBFS_USB__OSCLK_DR0) +#define USBFS_OSCLK_DR0_REG (* (reg8 *) USBFS_USB__OSCLK_DR0) +#define USBFS_OSCLK_DR1_PTR ( (reg8 *) USBFS_USB__OSCLK_DR1) +#define USBFS_OSCLK_DR1_REG (* (reg8 *) USBFS_USB__OSCLK_DR1) + +#define USBFS_PM_ACT_CFG_PTR ( (reg8 *) USBFS_USB__PM_ACT_CFG) +#define USBFS_PM_ACT_CFG_REG (* (reg8 *) USBFS_USB__PM_ACT_CFG) +#define USBFS_PM_STBY_CFG_PTR ( (reg8 *) USBFS_USB__PM_STBY_CFG) +#define USBFS_PM_STBY_CFG_REG (* (reg8 *) USBFS_USB__PM_STBY_CFG) + +#define USBFS_SIE_EP_INT_EN_PTR ( (reg8 *) USBFS_USB__SIE_EP_INT_EN) +#define USBFS_SIE_EP_INT_EN_REG (* (reg8 *) USBFS_USB__SIE_EP_INT_EN) +#define USBFS_SIE_EP_INT_SR_PTR ( (reg8 *) USBFS_USB__SIE_EP_INT_SR) +#define USBFS_SIE_EP_INT_SR_REG (* (reg8 *) USBFS_USB__SIE_EP_INT_SR) + +#define USBFS_SIE_EP1_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CNT0) +#define USBFS_SIE_EP1_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP1_CNT0) +#define USBFS_SIE_EP1_CNT0_IND USBFS_USB__SIE_EP1_CNT0 +#define USBFS_SIE_EP1_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CNT1) +#define USBFS_SIE_EP1_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP1_CNT1) +#define USBFS_SIE_EP1_CNT1_IND USBFS_USB__SIE_EP1_CNT1 +#define USBFS_SIE_EP1_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CR0) +#define USBFS_SIE_EP1_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP1_CR0) +#define USBFS_SIE_EP1_CR0_IND USBFS_USB__SIE_EP1_CR0 + +#define USBFS_SIE_EP2_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CNT0) +#define USBFS_SIE_EP2_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP2_CNT0) +#define USBFS_SIE_EP2_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CNT1) +#define USBFS_SIE_EP2_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP2_CNT1) +#define USBFS_SIE_EP2_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CR0) +#define USBFS_SIE_EP2_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP2_CR0) + +#define USBFS_SIE_EP3_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CNT0) +#define USBFS_SIE_EP3_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP3_CNT0) +#define USBFS_SIE_EP3_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CNT1) +#define USBFS_SIE_EP3_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP3_CNT1) +#define USBFS_SIE_EP3_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CR0) +#define USBFS_SIE_EP3_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP3_CR0) + +#define USBFS_SIE_EP4_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CNT0) +#define USBFS_SIE_EP4_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP4_CNT0) +#define USBFS_SIE_EP4_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CNT1) +#define USBFS_SIE_EP4_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP4_CNT1) +#define USBFS_SIE_EP4_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CR0) +#define USBFS_SIE_EP4_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP4_CR0) + +#define USBFS_SIE_EP5_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CNT0) +#define USBFS_SIE_EP5_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP5_CNT0) +#define USBFS_SIE_EP5_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CNT1) +#define USBFS_SIE_EP5_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP5_CNT1) +#define USBFS_SIE_EP5_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CR0) +#define USBFS_SIE_EP5_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP5_CR0) + +#define USBFS_SIE_EP6_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CNT0) +#define USBFS_SIE_EP6_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP6_CNT0) +#define USBFS_SIE_EP6_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CNT1) +#define USBFS_SIE_EP6_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP6_CNT1) +#define USBFS_SIE_EP6_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CR0) +#define USBFS_SIE_EP6_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP6_CR0) + +#define USBFS_SIE_EP7_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CNT0) +#define USBFS_SIE_EP7_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP7_CNT0) +#define USBFS_SIE_EP7_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CNT1) +#define USBFS_SIE_EP7_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP7_CNT1) +#define USBFS_SIE_EP7_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CR0) +#define USBFS_SIE_EP7_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP7_CR0) + +#define USBFS_SIE_EP8_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CNT0) +#define USBFS_SIE_EP8_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP8_CNT0) +#define USBFS_SIE_EP8_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CNT1) +#define USBFS_SIE_EP8_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP8_CNT1) +#define USBFS_SIE_EP8_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CR0) +#define USBFS_SIE_EP8_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP8_CR0) + +#define USBFS_SOF0_PTR ( (reg8 *) USBFS_USB__SOF0) +#define USBFS_SOF0_REG (* (reg8 *) USBFS_USB__SOF0) +#define USBFS_SOF1_PTR ( (reg8 *) USBFS_USB__SOF1) +#define USBFS_SOF1_REG (* (reg8 *) USBFS_USB__SOF1) + +#define USBFS_USB_CLK_EN_PTR ( (reg8 *) USBFS_USB__USB_CLK_EN) +#define USBFS_USB_CLK_EN_REG (* (reg8 *) USBFS_USB__USB_CLK_EN) + +#define USBFS_USBIO_CR0_PTR ( (reg8 *) USBFS_USB__USBIO_CR0) +#define USBFS_USBIO_CR0_REG (* (reg8 *) USBFS_USB__USBIO_CR0) +#define USBFS_USBIO_CR1_PTR ( (reg8 *) USBFS_USB__USBIO_CR1) +#define USBFS_USBIO_CR1_REG (* (reg8 *) USBFS_USB__USBIO_CR1) +#if(!CY_PSOC5LP) + #define USBFS_USBIO_CR2_PTR ( (reg8 *) USBFS_USB__USBIO_CR2) + #define USBFS_USBIO_CR2_REG (* (reg8 *) USBFS_USB__USBIO_CR2) +#endif /* End CY_PSOC5LP */ + +#define USBFS_DIE_ID CYDEV_FLSHID_CUST_TABLES_BASE + +#define USBFS_PM_USB_CR0_PTR ( (reg8 *) CYREG_PM_USB_CR0) +#define USBFS_PM_USB_CR0_REG (* (reg8 *) CYREG_PM_USB_CR0) +#define USBFS_DYN_RECONFIG_PTR ( (reg8 *) USBFS_USB__DYN_RECONFIG) +#define USBFS_DYN_RECONFIG_REG (* (reg8 *) USBFS_USB__DYN_RECONFIG) + +#define USBFS_DM_INP_DIS_PTR ( (reg8 *) USBFS_Dm__INP_DIS) +#define USBFS_DM_INP_DIS_REG (* (reg8 *) USBFS_Dm__INP_DIS) +#define USBFS_DP_INP_DIS_PTR ( (reg8 *) USBFS_Dp__INP_DIS) +#define USBFS_DP_INP_DIS_REG (* (reg8 *) USBFS_Dp__INP_DIS) +#define USBFS_DP_INTSTAT_PTR ( (reg8 *) USBFS_Dp__INTSTAT) +#define USBFS_DP_INTSTAT_REG (* (reg8 *) USBFS_Dp__INTSTAT) + +#if (USBFS_MON_VBUS == 1u) + #if (USBFS_EXTERN_VBUS == 0u) + #define USBFS_VBUS_DR_PTR ( (reg8 *) USBFS_VBUS__DR) + #define USBFS_VBUS_DR_REG (* (reg8 *) USBFS_VBUS__DR) + #define USBFS_VBUS_PS_PTR ( (reg8 *) USBFS_VBUS__PS) + #define USBFS_VBUS_PS_REG (* (reg8 *) USBFS_VBUS__PS) + #define USBFS_VBUS_MASK USBFS_VBUS__MASK + #else + #define USBFS_VBUS_PS_PTR ( (reg8 *) USBFS_Vbus_ps_sts_sts_reg__STATUS_REG ) + #define USBFS_VBUS_MASK (0x01u) + #endif /* End USBFS_EXTERN_VBUS == 0u */ +#endif /* End USBFS_MON_VBUS */ + +/* Renamed Registers for backward compatibility. +* Should not be used in new designs. +*/ +#define USBFS_ARB_CFG USBFS_ARB_CFG_PTR + +#define USBFS_ARB_EP1_CFG USBFS_ARB_EP1_CFG_PTR +#define USBFS_ARB_EP1_INT_EN USBFS_ARB_EP1_INT_EN_PTR +#define USBFS_ARB_EP1_SR USBFS_ARB_EP1_SR_PTR + +#define USBFS_ARB_EP2_CFG USBFS_ARB_EP2_CFG_PTR +#define USBFS_ARB_EP2_INT_EN USBFS_ARB_EP2_INT_EN_PTR +#define USBFS_ARB_EP2_SR USBFS_ARB_EP2_SR_PTR + +#define USBFS_ARB_EP3_CFG USBFS_ARB_EP3_CFG_PTR +#define USBFS_ARB_EP3_INT_EN USBFS_ARB_EP3_INT_EN_PTR +#define USBFS_ARB_EP3_SR USBFS_ARB_EP3_SR_PTR + +#define USBFS_ARB_EP4_CFG USBFS_ARB_EP4_CFG_PTR +#define USBFS_ARB_EP4_INT_EN USBFS_ARB_EP4_INT_EN_PTR +#define USBFS_ARB_EP4_SR USBFS_ARB_EP4_SR_PTR + +#define USBFS_ARB_EP5_CFG USBFS_ARB_EP5_CFG_PTR +#define USBFS_ARB_EP5_INT_EN USBFS_ARB_EP5_INT_EN_PTR +#define USBFS_ARB_EP5_SR USBFS_ARB_EP5_SR_PTR + +#define USBFS_ARB_EP6_CFG USBFS_ARB_EP6_CFG_PTR +#define USBFS_ARB_EP6_INT_EN USBFS_ARB_EP6_INT_EN_PTR +#define USBFS_ARB_EP6_SR USBFS_ARB_EP6_SR_PTR + +#define USBFS_ARB_EP7_CFG USBFS_ARB_EP7_CFG_PTR +#define USBFS_ARB_EP7_INT_EN USBFS_ARB_EP7_INT_EN_PTR +#define USBFS_ARB_EP7_SR USBFS_ARB_EP7_SR_PTR + +#define USBFS_ARB_EP8_CFG USBFS_ARB_EP8_CFG_PTR +#define USBFS_ARB_EP8_INT_EN USBFS_ARB_EP8_INT_EN_PTR +#define USBFS_ARB_EP8_SR USBFS_ARB_EP8_SR_PTR + +#define USBFS_ARB_INT_EN USBFS_ARB_INT_EN_PTR +#define USBFS_ARB_INT_SR USBFS_ARB_INT_SR_PTR + +#define USBFS_ARB_RW1_DR USBFS_ARB_RW1_DR_PTR +#define USBFS_ARB_RW1_RA USBFS_ARB_RW1_RA_PTR +#define USBFS_ARB_RW1_RA_MSB USBFS_ARB_RW1_RA_MSB_PTR +#define USBFS_ARB_RW1_WA USBFS_ARB_RW1_WA_PTR +#define USBFS_ARB_RW1_WA_MSB USBFS_ARB_RW1_WA_MSB_PTR + +#define USBFS_ARB_RW2_DR USBFS_ARB_RW2_DR_PTR +#define USBFS_ARB_RW2_RA USBFS_ARB_RW2_RA_PTR +#define USBFS_ARB_RW2_RA_MSB USBFS_ARB_RW2_RA_MSB_PTR +#define USBFS_ARB_RW2_WA USBFS_ARB_RW2_WA_PTR +#define USBFS_ARB_RW2_WA_MSB USBFS_ARB_RW2_WA_MSB_PTR + +#define USBFS_ARB_RW3_DR USBFS_ARB_RW3_DR_PTR +#define USBFS_ARB_RW3_RA USBFS_ARB_RW3_RA_PTR +#define USBFS_ARB_RW3_RA_MSB USBFS_ARB_RW3_RA_MSB_PTR +#define USBFS_ARB_RW3_WA USBFS_ARB_RW3_WA_PTR +#define USBFS_ARB_RW3_WA_MSB USBFS_ARB_RW3_WA_MSB_PTR + +#define USBFS_ARB_RW4_DR USBFS_ARB_RW4_DR_PTR +#define USBFS_ARB_RW4_RA USBFS_ARB_RW4_RA_PTR +#define USBFS_ARB_RW4_RA_MSB USBFS_ARB_RW4_RA_MSB_PTR +#define USBFS_ARB_RW4_WA USBFS_ARB_RW4_WA_PTR +#define USBFS_ARB_RW4_WA_MSB USBFS_ARB_RW4_WA_MSB_PTR + +#define USBFS_ARB_RW5_DR USBFS_ARB_RW5_DR_PTR +#define USBFS_ARB_RW5_RA USBFS_ARB_RW5_RA_PTR +#define USBFS_ARB_RW5_RA_MSB USBFS_ARB_RW5_RA_MSB_PTR +#define USBFS_ARB_RW5_WA USBFS_ARB_RW5_WA_PTR +#define USBFS_ARB_RW5_WA_MSB USBFS_ARB_RW5_WA_MSB_PTR + +#define USBFS_ARB_RW6_DR USBFS_ARB_RW6_DR_PTR +#define USBFS_ARB_RW6_RA USBFS_ARB_RW6_RA_PTR +#define USBFS_ARB_RW6_RA_MSB USBFS_ARB_RW6_RA_MSB_PTR +#define USBFS_ARB_RW6_WA USBFS_ARB_RW6_WA_PTR +#define USBFS_ARB_RW6_WA_MSB USBFS_ARB_RW6_WA_MSB_PTR + +#define USBFS_ARB_RW7_DR USBFS_ARB_RW7_DR_PTR +#define USBFS_ARB_RW7_RA USBFS_ARB_RW7_RA_PTR +#define USBFS_ARB_RW7_RA_MSB USBFS_ARB_RW7_RA_MSB_PTR +#define USBFS_ARB_RW7_WA USBFS_ARB_RW7_WA_PTR +#define USBFS_ARB_RW7_WA_MSB USBFS_ARB_RW7_WA_MSB_PTR + +#define USBFS_ARB_RW8_DR USBFS_ARB_RW8_DR_PTR +#define USBFS_ARB_RW8_RA USBFS_ARB_RW8_RA_PTR +#define USBFS_ARB_RW8_RA_MSB USBFS_ARB_RW8_RA_MSB_PTR +#define USBFS_ARB_RW8_WA USBFS_ARB_RW8_WA_PTR +#define USBFS_ARB_RW8_WA_MSB USBFS_ARB_RW8_WA_MSB_PTR + +#define USBFS_BUF_SIZE USBFS_BUF_SIZE_PTR +#define USBFS_BUS_RST_CNT USBFS_BUS_RST_CNT_PTR +#define USBFS_CR0 USBFS_CR0_PTR +#define USBFS_CR1 USBFS_CR1_PTR +#define USBFS_CWA USBFS_CWA_PTR +#define USBFS_CWA_MSB USBFS_CWA_MSB_PTR + +#define USBFS_DMA_THRES USBFS_DMA_THRES_PTR +#define USBFS_DMA_THRES_MSB USBFS_DMA_THRES_MSB_PTR + +#define USBFS_EP_ACTIVE USBFS_EP_ACTIVE_PTR +#define USBFS_EP_TYPE USBFS_EP_TYPE_PTR + +#define USBFS_EP0_CNT USBFS_EP0_CNT_PTR +#define USBFS_EP0_CR USBFS_EP0_CR_PTR +#define USBFS_EP0_DR0 USBFS_EP0_DR0_PTR +#define USBFS_EP0_DR1 USBFS_EP0_DR1_PTR +#define USBFS_EP0_DR2 USBFS_EP0_DR2_PTR +#define USBFS_EP0_DR3 USBFS_EP0_DR3_PTR +#define USBFS_EP0_DR4 USBFS_EP0_DR4_PTR +#define USBFS_EP0_DR5 USBFS_EP0_DR5_PTR +#define USBFS_EP0_DR6 USBFS_EP0_DR6_PTR +#define USBFS_EP0_DR7 USBFS_EP0_DR7_PTR + +#define USBFS_OSCLK_DR0 USBFS_OSCLK_DR0_PTR +#define USBFS_OSCLK_DR1 USBFS_OSCLK_DR1_PTR + +#define USBFS_PM_ACT_CFG USBFS_PM_ACT_CFG_PTR +#define USBFS_PM_STBY_CFG USBFS_PM_STBY_CFG_PTR + +#define USBFS_SIE_EP_INT_EN USBFS_SIE_EP_INT_EN_PTR +#define USBFS_SIE_EP_INT_SR USBFS_SIE_EP_INT_SR_PTR + +#define USBFS_SIE_EP1_CNT0 USBFS_SIE_EP1_CNT0_PTR +#define USBFS_SIE_EP1_CNT1 USBFS_SIE_EP1_CNT1_PTR +#define USBFS_SIE_EP1_CR0 USBFS_SIE_EP1_CR0_PTR + +#define USBFS_SIE_EP2_CNT0 USBFS_SIE_EP2_CNT0_PTR +#define USBFS_SIE_EP2_CNT1 USBFS_SIE_EP2_CNT1_PTR +#define USBFS_SIE_EP2_CR0 USBFS_SIE_EP2_CR0_PTR + +#define USBFS_SIE_EP3_CNT0 USBFS_SIE_EP3_CNT0_PTR +#define USBFS_SIE_EP3_CNT1 USBFS_SIE_EP3_CNT1_PTR +#define USBFS_SIE_EP3_CR0 USBFS_SIE_EP3_CR0_PTR + +#define USBFS_SIE_EP4_CNT0 USBFS_SIE_EP4_CNT0_PTR +#define USBFS_SIE_EP4_CNT1 USBFS_SIE_EP4_CNT1_PTR +#define USBFS_SIE_EP4_CR0 USBFS_SIE_EP4_CR0_PTR + +#define USBFS_SIE_EP5_CNT0 USBFS_SIE_EP5_CNT0_PTR +#define USBFS_SIE_EP5_CNT1 USBFS_SIE_EP5_CNT1_PTR +#define USBFS_SIE_EP5_CR0 USBFS_SIE_EP5_CR0_PTR + +#define USBFS_SIE_EP6_CNT0 USBFS_SIE_EP6_CNT0_PTR +#define USBFS_SIE_EP6_CNT1 USBFS_SIE_EP6_CNT1_PTR +#define USBFS_SIE_EP6_CR0 USBFS_SIE_EP6_CR0_PTR + +#define USBFS_SIE_EP7_CNT0 USBFS_SIE_EP7_CNT0_PTR +#define USBFS_SIE_EP7_CNT1 USBFS_SIE_EP7_CNT1_PTR +#define USBFS_SIE_EP7_CR0 USBFS_SIE_EP7_CR0_PTR + +#define USBFS_SIE_EP8_CNT0 USBFS_SIE_EP8_CNT0_PTR +#define USBFS_SIE_EP8_CNT1 USBFS_SIE_EP8_CNT1_PTR +#define USBFS_SIE_EP8_CR0 USBFS_SIE_EP8_CR0_PTR + +#define USBFS_SOF0 USBFS_SOF0_PTR +#define USBFS_SOF1 USBFS_SOF1_PTR + +#define USBFS_USB_CLK_EN USBFS_USB_CLK_EN_PTR + +#define USBFS_USBIO_CR0 USBFS_USBIO_CR0_PTR +#define USBFS_USBIO_CR1 USBFS_USBIO_CR1_PTR +#define USBFS_USBIO_CR2 USBFS_USBIO_CR2_PTR + +#define USBFS_USB_MEM ((reg8 *) CYDEV_USB_MEM_BASE) + +#if(CYDEV_CHIP_DIE_EXPECT == CYDEV_CHIP_DIE_LEOPARD) + /* PSoC3 interrupt registers*/ + #define USBFS_USB_ISR_PRIOR ((reg8 *) CYDEV_INTC_PRIOR0) + #define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_INTC_SET_EN0) + #define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_INTC_CLR_EN0) + #define USBFS_USB_ISR_VECT ((cyisraddress *) CYDEV_INTC_VECT_MBASE) +#elif(CYDEV_CHIP_DIE_EXPECT == CYDEV_CHIP_DIE_PANTHER) + /* PSoC5 interrupt registers*/ + #define USBFS_USB_ISR_PRIOR ((reg8 *) CYDEV_NVIC_PRI_0) + #define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_NVIC_SETENA0) + #define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_NVIC_CLRENA0) + #define USBFS_USB_ISR_VECT ((cyisraddress *) CYDEV_NVIC_VECT_OFFSET) +#endif /* End CYDEV_CHIP_DIE_EXPECT */ + + +/*************************************** +* Interrupt vectors, masks and priorities +***************************************/ + +#define USBFS_BUS_RESET_PRIOR USBFS_bus_reset__INTC_PRIOR_NUM +#define USBFS_BUS_RESET_MASK USBFS_bus_reset__INTC_MASK +#define USBFS_BUS_RESET_VECT_NUM USBFS_bus_reset__INTC_NUMBER + +#define USBFS_SOF_PRIOR USBFS_sof_int__INTC_PRIOR_NUM +#define USBFS_SOF_MASK USBFS_sof_int__INTC_MASK +#define USBFS_SOF_VECT_NUM USBFS_sof_int__INTC_NUMBER + +#define USBFS_EP_0_PRIOR USBFS_ep_0__INTC_PRIOR_NUM +#define USBFS_EP_0_MASK USBFS_ep_0__INTC_MASK +#define USBFS_EP_0_VECT_NUM USBFS_ep_0__INTC_NUMBER + +#define USBFS_EP_1_PRIOR USBFS_ep_1__INTC_PRIOR_NUM +#define USBFS_EP_1_MASK USBFS_ep_1__INTC_MASK +#define USBFS_EP_1_VECT_NUM USBFS_ep_1__INTC_NUMBER + +#define USBFS_EP_2_PRIOR USBFS_ep_2__INTC_PRIOR_NUM +#define USBFS_EP_2_MASK USBFS_ep_2__INTC_MASK +#define USBFS_EP_2_VECT_NUM USBFS_ep_2__INTC_NUMBER + +#define USBFS_EP_3_PRIOR USBFS_ep_3__INTC_PRIOR_NUM +#define USBFS_EP_3_MASK USBFS_ep_3__INTC_MASK +#define USBFS_EP_3_VECT_NUM USBFS_ep_3__INTC_NUMBER + +#define USBFS_EP_4_PRIOR USBFS_ep_4__INTC_PRIOR_NUM +#define USBFS_EP_4_MASK USBFS_ep_4__INTC_MASK +#define USBFS_EP_4_VECT_NUM USBFS_ep_4__INTC_NUMBER + +#define USBFS_EP_5_PRIOR USBFS_ep_5__INTC_PRIOR_NUM +#define USBFS_EP_5_MASK USBFS_ep_5__INTC_MASK +#define USBFS_EP_5_VECT_NUM USBFS_ep_5__INTC_NUMBER + +#define USBFS_EP_6_PRIOR USBFS_ep_6__INTC_PRIOR_NUM +#define USBFS_EP_6_MASK USBFS_ep_6__INTC_MASK +#define USBFS_EP_6_VECT_NUM USBFS_ep_6__INTC_NUMBER + +#define USBFS_EP_7_PRIOR USBFS_ep_7__INTC_PRIOR_NUM +#define USBFS_EP_7_MASK USBFS_ep_7__INTC_MASK +#define USBFS_EP_7_VECT_NUM USBFS_ep_7__INTC_NUMBER + +#define USBFS_EP_8_PRIOR USBFS_ep_8__INTC_PRIOR_NUM +#define USBFS_EP_8_MASK USBFS_ep_8__INTC_MASK +#define USBFS_EP_8_VECT_NUM USBFS_ep_8__INTC_NUMBER + +#define USBFS_DP_INTC_PRIOR USBFS_dp_int__INTC_PRIOR_NUM +#define USBFS_DP_INTC_MASK USBFS_dp_int__INTC_MASK +#define USBFS_DP_INTC_VECT_NUM USBFS_dp_int__INTC_NUMBER + +/* ARB ISR should have higher priority from EP_X ISR, therefore it is defined to highest (0) */ +#define USBFS_ARB_PRIOR (0u) +#define USBFS_ARB_MASK USBFS_arb_int__INTC_MASK +#define USBFS_ARB_VECT_NUM USBFS_arb_int__INTC_NUMBER + +/*************************************** + * Endpoint 0 offsets (Table 9-2) + **************************************/ + +#define USBFS_bmRequestType USBFS_EP0_DR0_PTR +#define USBFS_bRequest USBFS_EP0_DR1_PTR +#define USBFS_wValue USBFS_EP0_DR2_PTR +#define USBFS_wValueHi USBFS_EP0_DR3_PTR +#define USBFS_wValueLo USBFS_EP0_DR2_PTR +#define USBFS_wIndex USBFS_EP0_DR4_PTR +#define USBFS_wIndexHi USBFS_EP0_DR5_PTR +#define USBFS_wIndexLo USBFS_EP0_DR4_PTR +#define USBFS_length USBFS_EP0_DR6_PTR +#define USBFS_lengthHi USBFS_EP0_DR7_PTR +#define USBFS_lengthLo USBFS_EP0_DR6_PTR + + +/*************************************** +* Register Constants +***************************************/ +#define USBFS_VDDD_MV CYDEV_VDDD_MV +#define USBFS_3500MV (3500u) + +#define USBFS_CR1_REG_ENABLE (0x01u) +#define USBFS_CR1_ENABLE_LOCK (0x02u) +#define USBFS_CR1_BUS_ACTIVITY_SHIFT (0x02u) +#define USBFS_CR1_BUS_ACTIVITY ((uint8)(0x01u << USBFS_CR1_BUS_ACTIVITY_SHIFT)) +#define USBFS_CR1_TRIM_MSB_EN (0x08u) + +#define USBFS_EP0_CNT_DATA_TOGGLE (0x80u) +#define USBFS_EPX_CNT_DATA_TOGGLE (0x80u) +#define USBFS_EPX_CNT0_MASK (0x0Fu) +#define USBFS_EPX_CNTX_MSB_MASK (0x07u) +#define USBFS_EPX_CNTX_ADDR_SHIFT (0x04u) +#define USBFS_EPX_CNTX_ADDR_OFFSET (0x10u) +#define USBFS_EPX_CNTX_CRC_COUNT (0x02u) +#define USBFS_EPX_DATA_BUF_MAX (512u) + +#define USBFS_CR0_ENABLE (0x80u) + +/* A 100 KHz clock is used for BUS reset count. Recommended is to count 10 pulses */ +#define USBFS_BUS_RST_COUNT (0x0au) + +#define USBFS_USBIO_CR1_IOMODE (0x20u) +#define USBFS_USBIO_CR1_USBPUEN (0x04u) +#define USBFS_USBIO_CR1_DP0 (0x02u) +#define USBFS_USBIO_CR1_DM0 (0x01u) + +#define USBFS_USBIO_CR0_TEN (0x80u) +#define USBFS_USBIO_CR0_TSE0 (0x40u) +#define USBFS_USBIO_CR0_TD (0x20u) +#define USBFS_USBIO_CR0_RD (0x01u) + +#define USBFS_FASTCLK_IMO_CR_USBCLK_ON (0x40u) +#define USBFS_FASTCLK_IMO_CR_XCLKEN (0x20u) +#define USBFS_FASTCLK_IMO_CR_FX2ON (0x10u) + +#define USBFS_ARB_EPX_CFG_RESET (0x08u) +#define USBFS_ARB_EPX_CFG_CRC_BYPASS (0x04u) +#define USBFS_ARB_EPX_CFG_DMA_REQ (0x02u) +#define USBFS_ARB_EPX_CFG_IN_DATA_RDY (0x01u) + +#define USBFS_ARB_EPX_SR_IN_BUF_FULL (0x01u) +#define USBFS_ARB_EPX_SR_DMA_GNT (0x02u) +#define USBFS_ARB_EPX_SR_BUF_OVER (0x04u) +#define USBFS_ARB_EPX_SR_BUF_UNDER (0x08u) + +#define USBFS_ARB_CFG_AUTO_MEM (0x10u) +#define USBFS_ARB_CFG_MANUAL_DMA (0x20u) +#define USBFS_ARB_CFG_AUTO_DMA (0x40u) +#define USBFS_ARB_CFG_CFG_CPM (0x80u) + +#if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + #define USBFS_ARB_EPX_INT_MASK (0x1Du) +#else + #define USBFS_ARB_EPX_INT_MASK (0x1Fu) +#endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ +#define USBFS_ARB_INT_MASK (uint8)((USBFS_DMA1_REMOVE ^ 1u) | \ + (uint8)((USBFS_DMA2_REMOVE ^ 1u) << 1u) | \ + (uint8)((USBFS_DMA3_REMOVE ^ 1u) << 2u) | \ + (uint8)((USBFS_DMA4_REMOVE ^ 1u) << 3u) | \ + (uint8)((USBFS_DMA5_REMOVE ^ 1u) << 4u) | \ + (uint8)((USBFS_DMA6_REMOVE ^ 1u) << 5u) | \ + (uint8)((USBFS_DMA7_REMOVE ^ 1u) << 6u) | \ + (uint8)((USBFS_DMA8_REMOVE ^ 1u) << 7u) ) + +#define USBFS_SIE_EP_INT_EP1_MASK (0x01u) +#define USBFS_SIE_EP_INT_EP2_MASK (0x02u) +#define USBFS_SIE_EP_INT_EP3_MASK (0x04u) +#define USBFS_SIE_EP_INT_EP4_MASK (0x08u) +#define USBFS_SIE_EP_INT_EP5_MASK (0x10u) +#define USBFS_SIE_EP_INT_EP6_MASK (0x20u) +#define USBFS_SIE_EP_INT_EP7_MASK (0x40u) +#define USBFS_SIE_EP_INT_EP8_MASK (0x80u) + +#define USBFS_PM_ACT_EN_FSUSB USBFS_USB__PM_ACT_MSK +#define USBFS_PM_STBY_EN_FSUSB USBFS_USB__PM_STBY_MSK +#define USBFS_PM_AVAIL_EN_FSUSBIO (0x10u) + +#define USBFS_PM_USB_CR0_REF_EN (0x01u) +#define USBFS_PM_USB_CR0_PD_N (0x02u) +#define USBFS_PM_USB_CR0_PD_PULLUP_N (0x04u) + +#define USBFS_USB_CLK_ENABLE (0x01u) + +#define USBFS_DM_MASK USBFS_Dm__0__MASK +#define USBFS_DP_MASK USBFS_Dp__0__MASK + +#define USBFS_DYN_RECONFIG_ENABLE (0x01u) +#define USBFS_DYN_RECONFIG_EP_SHIFT (0x01u) +#define USBFS_DYN_RECONFIG_RDY_STS (0x10u) + + +#endif /* End CY_USBFS_USBFS_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.c b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.c new file mode 100644 index 00000000..e942a8f8 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.c @@ -0,0 +1,137 @@ +/******************************************************************************* +* File Name: USBFS_Dm.c +* Version 1.90 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "USBFS_Dm.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + USBFS_Dm__PORT == 15 && ((USBFS_Dm__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: USBFS_Dm_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void USBFS_Dm_Write(uint8 value) +{ + uint8 staticBits = (USBFS_Dm_DR & (uint8)(~USBFS_Dm_MASK)); + USBFS_Dm_DR = staticBits | ((uint8)(value << USBFS_Dm_SHIFT) & USBFS_Dm_MASK); +} + + +/******************************************************************************* +* Function Name: USBFS_Dm_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to this drive mode. +* +* Return: +* None +* +*******************************************************************************/ +void USBFS_Dm_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(USBFS_Dm_0, mode); +} + + +/******************************************************************************* +* Function Name: USBFS_Dm_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro USBFS_Dm_ReadPS calls this function. +* +*******************************************************************************/ +uint8 USBFS_Dm_Read(void) +{ + return (USBFS_Dm_PS & USBFS_Dm_MASK) >> USBFS_Dm_SHIFT; +} + + +/******************************************************************************* +* Function Name: USBFS_Dm_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 USBFS_Dm_ReadDataReg(void) +{ + return (USBFS_Dm_DR & USBFS_Dm_MASK) >> USBFS_Dm_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(USBFS_Dm_INTSTAT) + + /******************************************************************************* + * Function Name: USBFS_Dm_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 USBFS_Dm_ClearInterrupt(void) + { + return (USBFS_Dm_INTSTAT & USBFS_Dm_MASK) >> USBFS_Dm_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.h new file mode 100644 index 00000000..bbfcfee4 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: USBFS_Dm.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_USBFS_Dm_H) /* Pins USBFS_Dm_H */ +#define CY_PINS_USBFS_Dm_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "USBFS_Dm_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + USBFS_Dm__PORT == 15 && ((USBFS_Dm__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void USBFS_Dm_Write(uint8 value) ; +void USBFS_Dm_SetDriveMode(uint8 mode) ; +uint8 USBFS_Dm_ReadDataReg(void) ; +uint8 USBFS_Dm_Read(void) ; +uint8 USBFS_Dm_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define USBFS_Dm_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define USBFS_Dm_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define USBFS_Dm_DM_RES_UP PIN_DM_RES_UP +#define USBFS_Dm_DM_RES_DWN PIN_DM_RES_DWN +#define USBFS_Dm_DM_OD_LO PIN_DM_OD_LO +#define USBFS_Dm_DM_OD_HI PIN_DM_OD_HI +#define USBFS_Dm_DM_STRONG PIN_DM_STRONG +#define USBFS_Dm_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define USBFS_Dm_MASK USBFS_Dm__MASK +#define USBFS_Dm_SHIFT USBFS_Dm__SHIFT +#define USBFS_Dm_WIDTH 1u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define USBFS_Dm_PS (* (reg8 *) USBFS_Dm__PS) +/* Data Register */ +#define USBFS_Dm_DR (* (reg8 *) USBFS_Dm__DR) +/* Port Number */ +#define USBFS_Dm_PRT_NUM (* (reg8 *) USBFS_Dm__PRT) +/* Connect to Analog Globals */ +#define USBFS_Dm_AG (* (reg8 *) USBFS_Dm__AG) +/* Analog MUX bux enable */ +#define USBFS_Dm_AMUX (* (reg8 *) USBFS_Dm__AMUX) +/* Bidirectional Enable */ +#define USBFS_Dm_BIE (* (reg8 *) USBFS_Dm__BIE) +/* Bit-mask for Aliased Register Access */ +#define USBFS_Dm_BIT_MASK (* (reg8 *) USBFS_Dm__BIT_MASK) +/* Bypass Enable */ +#define USBFS_Dm_BYP (* (reg8 *) USBFS_Dm__BYP) +/* Port wide control signals */ +#define USBFS_Dm_CTL (* (reg8 *) USBFS_Dm__CTL) +/* Drive Modes */ +#define USBFS_Dm_DM0 (* (reg8 *) USBFS_Dm__DM0) +#define USBFS_Dm_DM1 (* (reg8 *) USBFS_Dm__DM1) +#define USBFS_Dm_DM2 (* (reg8 *) USBFS_Dm__DM2) +/* Input Buffer Disable Override */ +#define USBFS_Dm_INP_DIS (* (reg8 *) USBFS_Dm__INP_DIS) +/* LCD Common or Segment Drive */ +#define USBFS_Dm_LCD_COM_SEG (* (reg8 *) USBFS_Dm__LCD_COM_SEG) +/* Enable Segment LCD */ +#define USBFS_Dm_LCD_EN (* (reg8 *) USBFS_Dm__LCD_EN) +/* Slew Rate Control */ +#define USBFS_Dm_SLW (* (reg8 *) USBFS_Dm__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define USBFS_Dm_PRTDSI__CAPS_SEL (* (reg8 *) USBFS_Dm__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define USBFS_Dm_PRTDSI__DBL_SYNC_IN (* (reg8 *) USBFS_Dm__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define USBFS_Dm_PRTDSI__OE_SEL0 (* (reg8 *) USBFS_Dm__PRTDSI__OE_SEL0) +#define USBFS_Dm_PRTDSI__OE_SEL1 (* (reg8 *) USBFS_Dm__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define USBFS_Dm_PRTDSI__OUT_SEL0 (* (reg8 *) USBFS_Dm__PRTDSI__OUT_SEL0) +#define USBFS_Dm_PRTDSI__OUT_SEL1 (* (reg8 *) USBFS_Dm__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define USBFS_Dm_PRTDSI__SYNC_OUT (* (reg8 *) USBFS_Dm__PRTDSI__SYNC_OUT) + + +#if defined(USBFS_Dm__INTSTAT) /* Interrupt Registers */ + + #define USBFS_Dm_INTSTAT (* (reg8 *) USBFS_Dm__INTSTAT) + #define USBFS_Dm_SNAP (* (reg8 *) USBFS_Dm__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_USBFS_Dm_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h new file mode 100644 index 00000000..21242d52 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h @@ -0,0 +1,32 @@ +/******************************************************************************* +* File Name: USBFS_Dm.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_USBFS_Dm_ALIASES_H) /* Pins USBFS_Dm_ALIASES_H */ +#define CY_PINS_USBFS_Dm_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define USBFS_Dm_0 USBFS_Dm__0__PC + +#endif /* End Pins USBFS_Dm_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.c b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.c new file mode 100644 index 00000000..5904f4ae --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.c @@ -0,0 +1,137 @@ +/******************************************************************************* +* File Name: USBFS_Dp.c +* Version 1.90 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "USBFS_Dp.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + USBFS_Dp__PORT == 15 && ((USBFS_Dp__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: USBFS_Dp_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void USBFS_Dp_Write(uint8 value) +{ + uint8 staticBits = (USBFS_Dp_DR & (uint8)(~USBFS_Dp_MASK)); + USBFS_Dp_DR = staticBits | ((uint8)(value << USBFS_Dp_SHIFT) & USBFS_Dp_MASK); +} + + +/******************************************************************************* +* Function Name: USBFS_Dp_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to this drive mode. +* +* Return: +* None +* +*******************************************************************************/ +void USBFS_Dp_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(USBFS_Dp_0, mode); +} + + +/******************************************************************************* +* Function Name: USBFS_Dp_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro USBFS_Dp_ReadPS calls this function. +* +*******************************************************************************/ +uint8 USBFS_Dp_Read(void) +{ + return (USBFS_Dp_PS & USBFS_Dp_MASK) >> USBFS_Dp_SHIFT; +} + + +/******************************************************************************* +* Function Name: USBFS_Dp_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 USBFS_Dp_ReadDataReg(void) +{ + return (USBFS_Dp_DR & USBFS_Dp_MASK) >> USBFS_Dp_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(USBFS_Dp_INTSTAT) + + /******************************************************************************* + * Function Name: USBFS_Dp_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 USBFS_Dp_ClearInterrupt(void) + { + return (USBFS_Dp_INTSTAT & USBFS_Dp_MASK) >> USBFS_Dp_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.h new file mode 100644 index 00000000..217b6a3f --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: USBFS_Dp.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_USBFS_Dp_H) /* Pins USBFS_Dp_H */ +#define CY_PINS_USBFS_Dp_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "USBFS_Dp_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + USBFS_Dp__PORT == 15 && ((USBFS_Dp__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void USBFS_Dp_Write(uint8 value) ; +void USBFS_Dp_SetDriveMode(uint8 mode) ; +uint8 USBFS_Dp_ReadDataReg(void) ; +uint8 USBFS_Dp_Read(void) ; +uint8 USBFS_Dp_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define USBFS_Dp_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define USBFS_Dp_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define USBFS_Dp_DM_RES_UP PIN_DM_RES_UP +#define USBFS_Dp_DM_RES_DWN PIN_DM_RES_DWN +#define USBFS_Dp_DM_OD_LO PIN_DM_OD_LO +#define USBFS_Dp_DM_OD_HI PIN_DM_OD_HI +#define USBFS_Dp_DM_STRONG PIN_DM_STRONG +#define USBFS_Dp_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define USBFS_Dp_MASK USBFS_Dp__MASK +#define USBFS_Dp_SHIFT USBFS_Dp__SHIFT +#define USBFS_Dp_WIDTH 1u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define USBFS_Dp_PS (* (reg8 *) USBFS_Dp__PS) +/* Data Register */ +#define USBFS_Dp_DR (* (reg8 *) USBFS_Dp__DR) +/* Port Number */ +#define USBFS_Dp_PRT_NUM (* (reg8 *) USBFS_Dp__PRT) +/* Connect to Analog Globals */ +#define USBFS_Dp_AG (* (reg8 *) USBFS_Dp__AG) +/* Analog MUX bux enable */ +#define USBFS_Dp_AMUX (* (reg8 *) USBFS_Dp__AMUX) +/* Bidirectional Enable */ +#define USBFS_Dp_BIE (* (reg8 *) USBFS_Dp__BIE) +/* Bit-mask for Aliased Register Access */ +#define USBFS_Dp_BIT_MASK (* (reg8 *) USBFS_Dp__BIT_MASK) +/* Bypass Enable */ +#define USBFS_Dp_BYP (* (reg8 *) USBFS_Dp__BYP) +/* Port wide control signals */ +#define USBFS_Dp_CTL (* (reg8 *) USBFS_Dp__CTL) +/* Drive Modes */ +#define USBFS_Dp_DM0 (* (reg8 *) USBFS_Dp__DM0) +#define USBFS_Dp_DM1 (* (reg8 *) USBFS_Dp__DM1) +#define USBFS_Dp_DM2 (* (reg8 *) USBFS_Dp__DM2) +/* Input Buffer Disable Override */ +#define USBFS_Dp_INP_DIS (* (reg8 *) USBFS_Dp__INP_DIS) +/* LCD Common or Segment Drive */ +#define USBFS_Dp_LCD_COM_SEG (* (reg8 *) USBFS_Dp__LCD_COM_SEG) +/* Enable Segment LCD */ +#define USBFS_Dp_LCD_EN (* (reg8 *) USBFS_Dp__LCD_EN) +/* Slew Rate Control */ +#define USBFS_Dp_SLW (* (reg8 *) USBFS_Dp__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define USBFS_Dp_PRTDSI__CAPS_SEL (* (reg8 *) USBFS_Dp__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define USBFS_Dp_PRTDSI__DBL_SYNC_IN (* (reg8 *) USBFS_Dp__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define USBFS_Dp_PRTDSI__OE_SEL0 (* (reg8 *) USBFS_Dp__PRTDSI__OE_SEL0) +#define USBFS_Dp_PRTDSI__OE_SEL1 (* (reg8 *) USBFS_Dp__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define USBFS_Dp_PRTDSI__OUT_SEL0 (* (reg8 *) USBFS_Dp__PRTDSI__OUT_SEL0) +#define USBFS_Dp_PRTDSI__OUT_SEL1 (* (reg8 *) USBFS_Dp__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define USBFS_Dp_PRTDSI__SYNC_OUT (* (reg8 *) USBFS_Dp__PRTDSI__SYNC_OUT) + + +#if defined(USBFS_Dp__INTSTAT) /* Interrupt Registers */ + + #define USBFS_Dp_INTSTAT (* (reg8 *) USBFS_Dp__INTSTAT) + #define USBFS_Dp_SNAP (* (reg8 *) USBFS_Dp__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_USBFS_Dp_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h new file mode 100644 index 00000000..702fb7ed --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h @@ -0,0 +1,32 @@ +/******************************************************************************* +* File Name: USBFS_Dp.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_USBFS_Dp_ALIASES_H) /* Pins USBFS_Dp_ALIASES_H */ +#define CY_PINS_USBFS_Dp_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define USBFS_Dp_0 USBFS_Dp__0__PC + +#endif /* End Pins USBFS_Dp_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.c b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.c new file mode 100644 index 00000000..e837975c --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.c @@ -0,0 +1,318 @@ +/******************************************************************************* +* File Name: USBFS_audio.c +* Version 2.60 +* +* Description: +* USB AUDIO Class request handler. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS.h" + +#if defined(USBFS_ENABLE_AUDIO_CLASS) + +#include "USBFS_audio.h" +#include "USBFS_pvt.h" +#if defined(USBFS_ENABLE_MIDI_STREAMING) + #include "USBFS_midi.h" +#endif /* End USBFS_ENABLE_MIDI_STREAMING*/ + + +/*************************************** +* Custom Declarations +***************************************/ + +/* `#START CUSTOM_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +#if !defined(USER_SUPPLIED_AUDIO_HANDLER) + + +/*************************************** +* AUDIO Variables +***************************************/ + +#if defined(USBFS_ENABLE_AUDIO_STREAMING) + volatile uint8 USBFS_currentSampleFrequency[USBFS_MAX_EP][USBFS_SAMPLE_FREQ_LEN]; + volatile uint8 USBFS_frequencyChanged; + volatile uint8 USBFS_currentMute; + volatile uint8 USBFS_currentVolume[USBFS_VOLUME_LEN]; + volatile uint8 USBFS_minimumVolume[USBFS_VOLUME_LEN] = {USBFS_VOL_MIN_LSB, + USBFS_VOL_MIN_MSB}; + volatile uint8 USBFS_maximumVolume[USBFS_VOLUME_LEN] = {USBFS_VOL_MAX_LSB, + USBFS_VOL_MAX_MSB}; + volatile uint8 USBFS_resolutionVolume[USBFS_VOLUME_LEN] = {USBFS_VOL_RES_LSB, + USBFS_VOL_RES_MSB}; +#endif /* End USBFS_ENABLE_AUDIO_STREAMING */ + + +/******************************************************************************* +* Function Name: USBFS_DispatchAUDIOClassRqst +******************************************************************************** +* +* Summary: +* This routine dispatches class requests +* +* Parameters: +* None. +* +* Return: +* requestHandled +* +* Global variables: +* USBFS_currentSampleFrequency: Contains the current audio Sample +* Frequency. It is set by the Host using SET_CUR request to the endpoint. +* USBFS_frequencyChanged: This variable is used as a flag for the +* user code, to be aware that Host has been sent request for changing +* Sample Frequency. Sample frequency will be sent on the next OUT +* transaction. It is contains endpoint address when set. The following +* code is recommended for detecting new Sample Frequency in main code: +* if((USBFS_frequencyChanged != 0) && +* (USBFS_transferState == USBFS_TRANS_STATE_IDLE)) +* { +* USBFS_frequencyChanged = 0; +* } +* USBFS_transferState variable is checked to be sure that +* transfer completes. +* USBFS_currentMute: Contains mute configuration set by Host. +* USBFS_currentVolume: Contains volume level set by Host. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_DispatchAUDIOClassRqst(void) +{ + uint8 requestHandled = USBFS_FALSE; + + #if defined(USBFS_ENABLE_AUDIO_STREAMING) + uint8 epNumber; + epNumber = CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED; + #endif /* End USBFS_ENABLE_AUDIO_STREAMING */ + + if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H) + { + /* Control Read */ + if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \ + USBFS_RQST_RCPT_EP) + { + /* Endpoint */ + switch (CY_GET_REG8(USBFS_bRequest)) + { + case USBFS_GET_CUR: + #if defined(USBFS_ENABLE_AUDIO_STREAMING) + if(CY_GET_REG8(USBFS_wValueHi) == USBFS_SAMPLING_FREQ_CONTROL) + { + /* Endpoint Control Selector is Sampling Frequency */ + USBFS_currentTD.wCount = USBFS_SAMPLE_FREQ_LEN; + USBFS_currentTD.pData = USBFS_currentSampleFrequency[epNumber]; + requestHandled = USBFS_InitControlRead(); + } + #endif /* End USBFS_ENABLE_AUDIO_STREAMING */ + + /* `#START AUDIO_READ_REQUESTS` Place other request handler here */ + + /* `#END` */ + break; + default: + break; + } + } + else if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \ + USBFS_RQST_RCPT_IFC) + { + /* Interface or Entity ID */ + switch (CY_GET_REG8(USBFS_bRequest)) + { + case USBFS_GET_CUR: + #if defined(USBFS_ENABLE_AUDIO_STREAMING) + if(CY_GET_REG8(USBFS_wValueHi) == USBFS_MUTE_CONTROL) + { + /* `#START MUTE_CONTROL_GET_REQUEST` Place multi-channel handler here */ + + /* `#END` */ + + /* Entity ID Control Selector is MUTE */ + USBFS_currentTD.wCount = 1u; + USBFS_currentTD.pData = &USBFS_currentMute; + requestHandled = USBFS_InitControlRead(); + } + else if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL) + { + /* `#START VOLUME_CONTROL_GET_REQUEST` Place multi-channel handler here */ + + /* `#END` */ + + /* Entity ID Control Selector is VOLUME, */ + USBFS_currentTD.wCount = USBFS_VOLUME_LEN; + USBFS_currentTD.pData = USBFS_currentVolume; + requestHandled = USBFS_InitControlRead(); + } + else + { + /* `#START OTHER_GET_CUR_REQUESTS` Place other request handler here */ + + /* `#END` */ + } + break; + case USBFS_GET_MIN: /* GET_MIN */ + if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL) + { + /* Entity ID Control Selector is VOLUME, */ + USBFS_currentTD.wCount = USBFS_VOLUME_LEN; + USBFS_currentTD.pData = &USBFS_minimumVolume[0]; + requestHandled = USBFS_InitControlRead(); + } + break; + case USBFS_GET_MAX: /* GET_MAX */ + if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL) + { + /* Entity ID Control Selector is VOLUME, */ + USBFS_currentTD.wCount = USBFS_VOLUME_LEN; + USBFS_currentTD.pData = &USBFS_maximumVolume[0]; + requestHandled = USBFS_InitControlRead(); + } + break; + case USBFS_GET_RES: /* GET_RES */ + if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL) + { + /* Entity ID Control Selector is VOLUME, */ + USBFS_currentTD.wCount = USBFS_VOLUME_LEN; + USBFS_currentTD.pData = &USBFS_resolutionVolume[0]; + requestHandled = USBFS_InitControlRead(); + } + break; + /* The contents of the status message is reserved for future use. + * For the time being, a null packet should be returned in the data stage of the + * control transfer, and the received null packet should be ACKed. + */ + case USBFS_GET_STAT: + USBFS_currentTD.wCount = 0u; + requestHandled = USBFS_InitControlWrite(); + + #endif /* End USBFS_ENABLE_AUDIO_STREAMING */ + + /* `#START AUDIO_WRITE_REQUESTS` Place other request handler here */ + + /* `#END` */ + break; + default: + break; + } + } + else + { /* USBFS_RQST_RCPT_OTHER */ + } + } + else if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == \ + USBFS_RQST_DIR_H2D) + { + /* Control Write */ + if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \ + USBFS_RQST_RCPT_EP) + { + /* Endpoint */ + switch (CY_GET_REG8(USBFS_bRequest)) + { + case USBFS_SET_CUR: + #if defined(USBFS_ENABLE_AUDIO_STREAMING) + if(CY_GET_REG8(USBFS_wValueHi) == USBFS_SAMPLING_FREQ_CONTROL) + { + /* Endpoint Control Selector is Sampling Frequency */ + USBFS_currentTD.wCount = USBFS_SAMPLE_FREQ_LEN; + USBFS_currentTD.pData = USBFS_currentSampleFrequency[epNumber]; + requestHandled = USBFS_InitControlWrite(); + USBFS_frequencyChanged = epNumber; + } + #endif /* End USBFS_ENABLE_AUDIO_STREAMING */ + + /* `#START AUDIO_SAMPLING_FREQ_REQUESTS` Place other request handler here */ + + /* `#END` */ + break; + default: + break; + } + } + else if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \ + USBFS_RQST_RCPT_IFC) + { + /* Interface or Entity ID */ + switch (CY_GET_REG8(USBFS_bRequest)) + { + case USBFS_SET_CUR: + #if defined(USBFS_ENABLE_AUDIO_STREAMING) + if(CY_GET_REG8(USBFS_wValueHi) == USBFS_MUTE_CONTROL) + { + /* `#START MUTE_SET_REQUEST` Place multi-channel handler here */ + + /* `#END` */ + + /* Entity ID Control Selector is MUTE */ + USBFS_currentTD.wCount = 1u; + USBFS_currentTD.pData = &USBFS_currentMute; + requestHandled = USBFS_InitControlWrite(); + } + else if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL) + { + /* `#START VOLUME_CONTROL_SET_REQUEST` Place multi-channel handler here */ + + /* `#END` */ + + /* Entity ID Control Selector is VOLUME */ + USBFS_currentTD.wCount = USBFS_VOLUME_LEN; + USBFS_currentTD.pData = USBFS_currentVolume; + requestHandled = USBFS_InitControlWrite(); + } + else + { + /* `#START OTHER_SET_CUR_REQUESTS` Place other request handler here */ + + /* `#END` */ + } + #endif /* End USBFS_ENABLE_AUDIO_STREAMING */ + + /* `#START AUDIO_CONTROL_SEL_REQUESTS` Place other request handler here */ + + /* `#END` */ + break; + default: + break; + } + } + else + { /* USBFS_RQST_RCPT_OTHER */ + } + } + else + { /* requestHandled is initialized as FALSE by default */ + } + + return(requestHandled); +} + + +#endif /* USER_SUPPLIED_AUDIO_HANDLER */ + + +/******************************************************************************* +* Additional user functions supporting AUDIO Requests +********************************************************************************/ + +/* `#START AUDIO_FUNCTIONS` Place any additional functions here */ + +/* `#END` */ + +#endif /* End USBFS_ENABLE_AUDIO_CLASS*/ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.h new file mode 100644 index 00000000..0e0feb20 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.h @@ -0,0 +1,95 @@ +/******************************************************************************* +* File Name: USBFS_audio.h +* Version 2.60 +* +* Description: +* Header File for the USFS component. Contains prototypes and constant values. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_USBFS_USBFS_audio_H) +#define CY_USBFS_USBFS_audio_H + +#include "cytypes.h" + + +/*************************************** +* Custom Declarations +***************************************/ + +/* `#START CUSTOM_CONSTANTS` Place your declaration here */ + +/* `#END` */ + + +/*************************************** +* Constants for USBFS_audio API. +***************************************/ + +/* Audio Class-Specific Request Codes (AUDIO Table A-9) */ +#define USBFS_REQUEST_CODE_UNDEFINED (0x00u) +#define USBFS_SET_CUR (0x01u) +#define USBFS_GET_CUR (0x81u) +#define USBFS_SET_MIN (0x02u) +#define USBFS_GET_MIN (0x82u) +#define USBFS_SET_MAX (0x03u) +#define USBFS_GET_MAX (0x83u) +#define USBFS_SET_RES (0x04u) +#define USBFS_GET_RES (0x84u) +#define USBFS_SET_MEM (0x05u) +#define USBFS_GET_MEM (0x85u) +#define USBFS_GET_STAT (0xFFu) + +/* Endpoint Control Selectors (AUDIO Table A-19) */ +#define USBFS_EP_CONTROL_UNDEFINED (0x00u) +#define USBFS_SAMPLING_FREQ_CONTROL (0x01u) +#define USBFS_PITCH_CONTROL (0x02u) + +/* Feature Unit Control Selectors (AUDIO Table A-11) */ +#define USBFS_FU_CONTROL_UNDEFINED (0x00u) +#define USBFS_MUTE_CONTROL (0x01u) +#define USBFS_VOLUME_CONTROL (0x02u) +#define USBFS_BASS_CONTROL (0x03u) +#define USBFS_MID_CONTROL (0x04u) +#define USBFS_TREBLE_CONTROL (0x05u) +#define USBFS_GRAPHIC_EQUALIZER_CONTROL (0x06u) +#define USBFS_AUTOMATIC_GAIN_CONTROL (0x07u) +#define USBFS_DELAY_CONTROL (0x08u) +#define USBFS_BASS_BOOST_CONTROL (0x09u) +#define USBFS_LOUDNESS_CONTROL (0x0Au) + +#define USBFS_SAMPLE_FREQ_LEN (3u) +#define USBFS_VOLUME_LEN (2u) + +#if !defined(USER_SUPPLIED_DEFAULT_VOLUME_VALUE) + #define USBFS_VOL_MIN_MSB (0x80u) + #define USBFS_VOL_MIN_LSB (0x01u) + #define USBFS_VOL_MAX_MSB (0x7Fu) + #define USBFS_VOL_MAX_LSB (0xFFu) + #define USBFS_VOL_RES_MSB (0x00u) + #define USBFS_VOL_RES_LSB (0x01u) +#endif /* USER_SUPPLIED_DEFAULT_VOLUME_VALUE */ + + +/*************************************** +* External data references +***************************************/ + +extern volatile uint8 USBFS_currentSampleFrequency[USBFS_MAX_EP] + [USBFS_SAMPLE_FREQ_LEN]; +extern volatile uint8 USBFS_frequencyChanged; +extern volatile uint8 USBFS_currentMute; +extern volatile uint8 USBFS_currentVolume[USBFS_VOLUME_LEN]; +extern volatile uint8 USBFS_minimumVolume[USBFS_VOLUME_LEN]; +extern volatile uint8 USBFS_maximumVolume[USBFS_VOLUME_LEN]; +extern volatile uint8 USBFS_resolutionVolume[USBFS_VOLUME_LEN]; + +#endif /* End CY_USBFS_USBFS_audio_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_boot.c b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_boot.c new file mode 100644 index 00000000..3cbb2f9d --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_boot.c @@ -0,0 +1,262 @@ +/******************************************************************************* +* File Name: USBFS_boot.c +* Version 2.60 +* +* Description: +* Boot loader API for USBFS Component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS.h" + +#if defined(CYDEV_BOOTLOADER_IO_COMP) && ((CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) || \ + (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface)) + + +/*************************************** +* Bootloader defines +***************************************/ + +#define USBFS_CyBtLdrStarttimer(X, T) {USBFS_universalTime = T * 10; X = 0u;} +#define USBFS_CyBtLdrChecktimer(X) ((X++ < USBFS_universalTime) ? 1u : 0u) + +#define USBFS_BTLDR_OUT_EP (0x01u) +#define USBFS_BTLDR_IN_EP (0x02u) + + +/*************************************** +* Bootloader Variables +***************************************/ + +static uint16 USBFS_universalTime; +static uint8 USBFS_started = 0u; + + +/******************************************************************************* +* Function Name: USBFS_CyBtldrCommStart +******************************************************************************** +* +* Summary: +* Starts the component and enables the interrupt. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Side Effects: +* This function starts the USB with 3V or 5V operation. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_CyBtldrCommStart(void) +{ + CyGlobalIntEnable; /* Enable Global Interrupts */ + + /*Start USBFS Operation/device 0 and with 5V or 3V operation depend on Voltage Configuration in DWR */ + USBFS_Start(0u, USBFS_DWR_VDDD_OPERATION); + + /* USB component started, the correct enumeration will be checked in first Read operation */ + USBFS_started = 1u; + +} + + +/******************************************************************************* +* Function Name: USBFS_CyBtldrCommStop. +******************************************************************************** +* +* Summary: +* Disable the component and disable the interrupt. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void USBFS_CyBtldrCommStop(void) +{ + USBFS_Stop(); +} + + +/******************************************************************************* +* Function Name: USBFS_CyBtldrCommReset. +******************************************************************************** +* +* Summary: +* Resets the receive and transmit communication Buffers. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_CyBtldrCommReset(void) +{ + USBFS_EnableOutEP(USBFS_BTLDR_OUT_EP); /* Enable the OUT endpoint */ +} + + +/******************************************************************************* +* Function Name: USBFS_CyBtldrCommWrite. +******************************************************************************** +* +* Summary: +* Allows the caller to write data to the boot loader host. The function will +* handle polling to allow a block of data to be completely sent to the host +* device. +* +* Parameters: +* pData: A pointer to the block of data to send to the device +* size: The number of bytes to write. +* count: Pointer to an unsigned short variable to write the number of +* bytes actually written. +* timeOut: Number of units to wait before returning because of a timeout. +* +* Return: +* Returns the value that best describes the problem. +* +* Reentrant: +* No. +* +*******************************************************************************/ +cystatus USBFS_CyBtldrCommWrite(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL + +{ + uint16 time; + cystatus status; + + /* Enable IN transfer */ + USBFS_LoadInEP(USBFS_BTLDR_IN_EP, pData, USBFS_BTLDR_SIZEOF_READ_BUFFER); + + /* Start a timer to wait on. */ + USBFS_CyBtLdrStarttimer(time, timeOut); + + /* Wait for the master to read it. */ + while((USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL) && \ + USBFS_CyBtLdrChecktimer(time)) + { + CyDelay(1u); /* 1ms delay */ + } + + if (USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL) + { + status = CYRET_TIMEOUT; + } + else + { + *count = size; + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: USBFS_CyBtldrCommRead. +******************************************************************************** +* +* Summary: +* Allows the caller to read data from the boot loader host. The function will +* handle polling to allow a block of data to be completely received from the +* host device. +* +* Parameters: +* pData: A pointer to the area to store the block of data received +* from the device. +* size: The number of bytes to read. +* count: Pointer to an unsigned short variable to write the number +* of bytes actually read. +* timeOut: Number of units to wait before returning because of a timeOut. +* Timeout is measured in 10s of ms. +* +* Return: +* Returns the value that best describes the problem. +* +* Reentrant: +* No. +* +*******************************************************************************/ +cystatus USBFS_CyBtldrCommRead(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL + +{ + cystatus status; + uint16 time; + + if(size > USBFS_BTLDR_SIZEOF_WRITE_BUFFER) + { + size = USBFS_BTLDR_SIZEOF_WRITE_BUFFER; + } + /* Start a timer to wait on. */ + USBFS_CyBtLdrStarttimer(time, timeOut); + + /* Wait on enumeration in first time */ + if(USBFS_started) + { + /* Wait for Device to enumerate */ + while(!USBFS_GetConfiguration() && USBFS_CyBtLdrChecktimer(time)) + { + CyDelay(1u); /* 1ms delay */ + } + /* Enable first OUT, if enumeration complete */ + if(USBFS_GetConfiguration()) + { + USBFS_IsConfigurationChanged(); /* Clear configuration changes state status */ + USBFS_CyBtldrCommReset(); + USBFS_started = 0u; + } + } + else /* Check for configuration changes, has been done by Host */ + { + if(USBFS_IsConfigurationChanged() != 0u) /* Host could send double SET_INTERFACE request or RESET */ + { + if(USBFS_GetConfiguration() != 0u) /* Init OUT endpoints when device reconfigured */ + { + USBFS_CyBtldrCommReset(); + } + } + } + /* Wait on next packet */ + while((USBFS_GetEPState(USBFS_BTLDR_OUT_EP) != USBFS_OUT_BUFFER_FULL) && \ + USBFS_CyBtLdrChecktimer(time)) + { + CyDelay(1u); /* 1ms delay */ + } + + /* OUT EP has completed */ + if (USBFS_GetEPState(USBFS_BTLDR_OUT_EP) == USBFS_OUT_BUFFER_FULL) + { + *count = USBFS_ReadOutEP(USBFS_BTLDR_OUT_EP, pData, size); + status = CYRET_SUCCESS; + } + else + { + *count = 0u; + status = CYRET_TIMEOUT; + } + return(status); +} + +#endif /* End CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.c b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.c new file mode 100644 index 00000000..7d65d6b7 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.c @@ -0,0 +1,706 @@ +/******************************************************************************* +* File Name: USBFS_cdc.c +* Version 2.60 +* +* Description: +* USB HID Class request handler. +* +* Note: +* +******************************************************************************** +* Copyright 2012-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS.h" + +#if defined(USBFS_ENABLE_CDC_CLASS) + +#include "USBFS_cdc.h" +#include "USBFS_pvt.h" + + +/*************************************** +* CDC Variables +***************************************/ + +volatile uint8 USBFS_lineCoding[USBFS_LINE_CODING_SIZE]; +volatile uint8 USBFS_lineChanged; +volatile uint16 USBFS_lineControlBitmap; +volatile uint8 USBFS_cdc_data_in_ep; +volatile uint8 USBFS_cdc_data_out_ep; + + +/*************************************** +* Static Function Prototypes +***************************************/ +static uint16 USBFS_StrLen(const char8 string[]) ; + + +/*************************************** +* Custom Declarations +***************************************/ + +/* `#START CDC_CUSTOM_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +/******************************************************************************* +* Function Name: USBFS_DispatchCDCClassRqst +******************************************************************************** +* +* Summary: +* This routine dispatches CDC class requests. +* +* Parameters: +* None. +* +* Return: +* requestHandled +* +* Global variables: +* USBFS_lineCoding: Contains the current line coding structure. +* It is set by the Host using SET_LINE_CODING request and returned to the +* user code by the USBFS_GetDTERate(), USBFS_GetCharFormat(), +* USBFS_GetParityType(), USBFS_GetDataBits() APIs. +* USBFS_lineControlBitmap: Contains the current control signal +* bitmap. It is set by the Host using SET_CONTROL_LINE request and returned +* to the user code by the USBFS_GetLineControl() API. +* USBFS_lineChanged: This variable is used as a flag for the +* USBFS_IsLineChanged() API, to be aware that Host has been sent request +* for changing Line Coding or Control Bitmap. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_DispatchCDCClassRqst(void) +{ + uint8 requestHandled = USBFS_FALSE; + + if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H) + { /* Control Read */ + switch (CY_GET_REG8(USBFS_bRequest)) + { + case USBFS_CDC_GET_LINE_CODING: + USBFS_currentTD.count = USBFS_LINE_CODING_SIZE; + USBFS_currentTD.pData = USBFS_lineCoding; + requestHandled = USBFS_InitControlRead(); + break; + + /* `#START CDC_READ_REQUESTS` Place other request handler here */ + + /* `#END` */ + + default: /* requestHandled is initialized as FALSE by default */ + break; + } + } + else if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == \ + USBFS_RQST_DIR_H2D) + { /* Control Write */ + switch (CY_GET_REG8(USBFS_bRequest)) + { + case USBFS_CDC_SET_LINE_CODING: + USBFS_currentTD.count = USBFS_LINE_CODING_SIZE; + USBFS_currentTD.pData = USBFS_lineCoding; + USBFS_lineChanged |= USBFS_LINE_CODING_CHANGED; + requestHandled = USBFS_InitControlWrite(); + break; + + case USBFS_CDC_SET_CONTROL_LINE_STATE: + USBFS_lineControlBitmap = CY_GET_REG8(USBFS_wValueLo); + USBFS_lineChanged |= USBFS_LINE_CONTROL_CHANGED; + requestHandled = USBFS_InitNoDataControlTransfer(); + break; + + /* `#START CDC_WRITE_REQUESTS` Place other request handler here */ + + /* `#END` */ + + default: /* requestHandled is initialized as FALSE by default */ + break; + } + } + else + { /* requestHandled is initialized as FALSE by default */ + } + + return(requestHandled); +} + + +/*************************************** +* Optional CDC APIs +***************************************/ +#if (USBFS_ENABLE_CDC_CLASS_API != 0u) + + + /******************************************************************************* + * Function Name: USBFS_CDC_Init + ******************************************************************************** + * + * Summary: + * This function initialize the CDC interface to be ready for the receive data + * from the PC. + * + * Parameters: + * None. + * + * Return: + * None. + * + * Global variables: + * USBFS_lineChanged: Initialized to zero. + * USBFS_cdc_data_out_ep: Used as an OUT endpoint number. + * + * Reentrant: + * No. + * + *******************************************************************************/ + void USBFS_CDC_Init(void) + { + USBFS_lineChanged = 0u; + USBFS_EnableOutEP(USBFS_cdc_data_out_ep); + } + + + /******************************************************************************* + * Function Name: USBFS_PutData + ******************************************************************************** + * + * Summary: + * Sends a specified number of bytes from the location specified by a + * pointer to the PC. + * + * Parameters: + * pData: pointer to the buffer containing data to be sent. + * length: Specifies the number of bytes to send from the pData + * buffer. Maximum length will be limited by the maximum packet + * size for the endpoint. + * + * Return: + * None. + * + * Global variables: + * USBFS_cdc_data_in_ep: CDC IN endpoint number used for sending + * data. + * + * Reentrant: + * No. + * + *******************************************************************************/ + void USBFS_PutData(const uint8* pData, uint16 length) + { + /* Limits length to maximum packet size for the EP */ + if(length > USBFS_EP[USBFS_cdc_data_in_ep].bufferSize) + { + /* Caution: Data will be lost if length is greater than Max Packet Length */ + length = USBFS_EP[USBFS_cdc_data_in_ep].bufferSize; + /* Halt CPU in debug mode */ + CYASSERT(0u != 0u); + } + USBFS_LoadInEP(USBFS_cdc_data_in_ep, pData, length); + } + + + /******************************************************************************* + * Function Name: USBFS_StrLen + ******************************************************************************** + * + * Summary: + * Calculates length of a null terminated string. + * + * Parameters: + * string: pointer to the string. + * + * Return: + * Length of the string + * + *******************************************************************************/ + static uint16 USBFS_StrLen(const char8 string[]) + { + uint16 len = 0u; + + while (string[len] != (char8)0) + { + len++; + } + + return (len); + } + + + /******************************************************************************* + * Function Name: USBFS_PutString + ******************************************************************************** + * + * Summary: + * Sends a null terminated string to the PC. + * + * Parameters: + * string: pointer to the string to be sent to the PC + * + * Return: + * None. + * + * Global variables: + * USBFS_cdc_data_in_ep: CDC IN endpoint number used for sending + * data. + * + * Reentrant: + * No. + * + * Theory: + * This function will block if there is not enough memory to place the whole + * string, it will block until the entire string has been written to the + * transmit buffer. + * + *******************************************************************************/ + void USBFS_PutString(const char8 string[]) + { + uint16 str_length; + uint16 send_length; + uint16 buf_index = 0u; + + /* Get length of the null terminated string */ + str_length = USBFS_StrLen(string); + do + { + /* Limits length to maximum packet size for the EP */ + send_length = (str_length > USBFS_EP[USBFS_cdc_data_in_ep].bufferSize) ? + USBFS_EP[USBFS_cdc_data_in_ep].bufferSize : str_length; + /* Enable IN transfer */ + USBFS_LoadInEP(USBFS_cdc_data_in_ep, (const uint8 *)&string[buf_index], send_length); + str_length -= send_length; + + /* If more data are present to send */ + if(str_length > 0u) + { + buf_index += send_length; + /* Wait for the Host to read it. */ + while(USBFS_EP[USBFS_cdc_data_in_ep].apiEpState == + USBFS_IN_BUFFER_FULL) + { + ; + } + } + }while(str_length > 0u); + } + + + /******************************************************************************* + * Function Name: USBFS_PutChar + ******************************************************************************** + * + * Summary: + * Writes a single character to the PC. + * + * Parameters: + * txDataByte: Character to be sent to the PC. + * + * Return: + * None. + * + * Global variables: + * USBFS_cdc_data_in_ep: CDC IN endpoint number used for sending + * data. + * + * Reentrant: + * No. + * + *******************************************************************************/ + void USBFS_PutChar(char8 txDataByte) + { + uint8 dataByte; + dataByte = (uint8)txDataByte; + + USBFS_LoadInEP(USBFS_cdc_data_in_ep, &dataByte, 1u); + } + + + /******************************************************************************* + * Function Name: USBFS_PutCRLF + ******************************************************************************** + * + * Summary: + * Sends a carriage return (0x0D) and line feed (0x0A) to the PC + * + * Parameters: + * None. + * + * Return: + * None. + * + * Global variables: + * USBFS_cdc_data_in_ep: CDC IN endpoint number used for sending + * data. + * + * Reentrant: + * No. + * + *******************************************************************************/ + void USBFS_PutCRLF(void) + { + const uint8 CYCODE txData[] = {0x0Du, 0x0Au}; + + USBFS_LoadInEP(USBFS_cdc_data_in_ep, (const uint8 *)txData, 2u); + } + + + /******************************************************************************* + * Function Name: USBFS_GetCount + ******************************************************************************** + * + * Summary: + * This function returns the number of bytes that were received from the PC. + * + * Parameters: + * None. + * + * Return: + * Returns the number of received bytes. + * + * Global variables: + * USBFS_cdc_data_out_ep: CDC OUT endpoint number used. + * + *******************************************************************************/ + uint16 USBFS_GetCount(void) + { + uint16 bytesCount = 0u; + + if (USBFS_EP[USBFS_cdc_data_out_ep].apiEpState == USBFS_OUT_BUFFER_FULL) + { + bytesCount = USBFS_GetEPCount(USBFS_cdc_data_out_ep); + } + + return(bytesCount); + } + + + /******************************************************************************* + * Function Name: USBFS_DataIsReady + ******************************************************************************** + * + * Summary: + * Returns a nonzero value if the component received data or received + * zero-length packet. The GetAll() or GetData() API should be called to read + * data from the buffer and re-init OUT endpoint even when zero-length packet + * received. + * + * Parameters: + * None. + * + * Return: + * If the OUT packet received this function returns a nonzero value. + * Otherwise zero is returned. + * + * Global variables: + * USBFS_cdc_data_out_ep: CDC OUT endpoint number used. + * + *******************************************************************************/ + uint8 USBFS_DataIsReady(void) + { + return(USBFS_EP[USBFS_cdc_data_out_ep].apiEpState); + } + + + /******************************************************************************* + * Function Name: USBFS_CDCIsReady + ******************************************************************************** + * + * Summary: + * Returns a nonzero value if the component is ready to send more data to the + * PC. Otherwise returns zero. Should be called before sending new data to + * ensure the previous data has finished sending.This function returns the + * number of bytes that were received from the PC. + * + * Parameters: + * None. + * + * Return: + * If the buffer can accept new data then this function returns a nonzero value. + * Otherwise zero is returned. + * + * Global variables: + * USBFS_cdc_data_in_ep: CDC IN endpoint number used. + * + *******************************************************************************/ + uint8 USBFS_CDCIsReady(void) + { + return(USBFS_EP[USBFS_cdc_data_in_ep].apiEpState); + } + + + /******************************************************************************* + * Function Name: USBFS_GetData + ******************************************************************************** + * + * Summary: + * Gets a specified number of bytes from the input buffer and places it in a + * data array specified by the passed pointer. + * USBFS_DataIsReady() API should be called before, to be sure + * that data is received from the Host. + * + * Parameters: + * pData: Pointer to the data array where data will be placed. + * Length: Number of bytes to read into the data array from the RX buffer. + * Maximum length is limited by the the number of received bytes. + * + * Return: + * Number of bytes received. + * + * Global variables: + * USBFS_cdc_data_out_ep: CDC OUT endpoint number used. + * + * Reentrant: + * No. + * + *******************************************************************************/ + uint16 USBFS_GetData(uint8* pData, uint16 length) + { + return(USBFS_ReadOutEP(USBFS_cdc_data_out_ep, pData, length)); + } + + + /******************************************************************************* + * Function Name: USBFS_GetAll + ******************************************************************************** + * + * Summary: + * Gets all bytes of received data from the input buffer and places it into a + * specified data array. USBFS_DataIsReady() API should be called + * before, to be sure that data is received from the Host. + * + * Parameters: + * pData: Pointer to the data array where data will be placed. + * + * Return: + * Number of bytes received. + * + * Global variables: + * USBFS_cdc_data_out_ep: CDC OUT endpoint number used. + * USBFS_EP[].bufferSize: EP max packet size is used as a length + * to read all data from the EP buffer. + * + * Reentrant: + * No. + * + *******************************************************************************/ + uint16 USBFS_GetAll(uint8* pData) + { + return (USBFS_ReadOutEP(USBFS_cdc_data_out_ep, pData, + USBFS_EP[USBFS_cdc_data_out_ep].bufferSize)); + } + + + /******************************************************************************* + * Function Name: USBFS_GetChar + ******************************************************************************** + * + * Summary: + * Reads one byte of received data from the buffer. + * + * Parameters: + * None. + * + * Return: + * Received one character. + * + * Global variables: + * USBFS_cdc_data_out_ep: CDC OUT endpoint number used. + * + * Reentrant: + * No. + * + *******************************************************************************/ + uint8 USBFS_GetChar(void) + { + uint8 rxData; + + (void) USBFS_ReadOutEP(USBFS_cdc_data_out_ep, &rxData, 1u); + + return(rxData); + } + + /******************************************************************************* + * Function Name: USBFS_IsLineChanged + ******************************************************************************** + * + * Summary: + * This function returns clear on read status of the line. + * + * Parameters: + * None. + * + * Return: + * If SET_LINE_CODING or CDC_SET_CONTROL_LINE_STATE request received then not + * zero value returned. Otherwise zero is returned. + * + * Global variables: + * USBFS_transferState - it is checked to be sure then OUT data + * phase has been complete, and data written to the lineCoding or Control + * Bitmap buffer. + * USBFS_lineChanged: used as a flag to be aware that Host has been + * sent request for changing Line Coding or Control Bitmap. + * + *******************************************************************************/ + uint8 USBFS_IsLineChanged(void) + { + uint8 state = 0u; + + /* transferState is checked to be sure then OUT data phase has been complete */ + if(USBFS_transferState == USBFS_TRANS_STATE_IDLE) + { + if(USBFS_lineChanged != 0u) + { + state = USBFS_lineChanged; + USBFS_lineChanged = 0u; + } + } + + return(state); + } + + + /******************************************************************************* + * Function Name: USBFS_GetDTERate + ******************************************************************************** + * + * Summary: + * Returns the data terminal rate set for this port in bits per second. + * + * Parameters: + * None. + * + * Return: + * Returns a uint32 value of the data rate in bits per second. + * + * Global variables: + * USBFS_lineCoding: First four bytes converted to uint32 + * depend on compiler, and returned as a data rate. + * + *******************************************************************************/ + uint32 USBFS_GetDTERate(void) + { + uint32 rate; + + rate = USBFS_lineCoding[USBFS_LINE_CODING_RATE + 3u]; + rate = (rate << 8u) | USBFS_lineCoding[USBFS_LINE_CODING_RATE + 2u]; + rate = (rate << 8u) | USBFS_lineCoding[USBFS_LINE_CODING_RATE + 1u]; + rate = (rate << 8u) | USBFS_lineCoding[USBFS_LINE_CODING_RATE]; + + return(rate); + } + + + /******************************************************************************* + * Function Name: USBFS_GetCharFormat + ******************************************************************************** + * + * Summary: + * Returns the number of stop bits. + * + * Parameters: + * None. + * + * Return: + * Returns the number of stop bits. + * + * Global variables: + * USBFS_lineCoding: used to get a parameter. + * + *******************************************************************************/ + uint8 USBFS_GetCharFormat(void) + { + return(USBFS_lineCoding[USBFS_LINE_CODING_STOP_BITS]); + } + + + /******************************************************************************* + * Function Name: USBFS_GetParityType + ******************************************************************************** + * + * Summary: + * Returns the parity type for the CDC port. + * + * Parameters: + * None. + * + * Return: + * Returns the parity type. + * + * Global variables: + * USBFS_lineCoding: used to get a parameter. + * + *******************************************************************************/ + uint8 USBFS_GetParityType(void) + { + return(USBFS_lineCoding[USBFS_LINE_CODING_PARITY]); + } + + + /******************************************************************************* + * Function Name: USBFS_GetDataBits + ******************************************************************************** + * + * Summary: + * Returns the number of data bits for the CDC port. + * + * Parameters: + * None. + * + * Return: + * Returns the number of data bits. + * The number of data bits can be 5, 6, 7, 8 or 16. + * + * Global variables: + * USBFS_lineCoding: used to get a parameter. + * + *******************************************************************************/ + uint8 USBFS_GetDataBits(void) + { + return(USBFS_lineCoding[USBFS_LINE_CODING_DATA_BITS]); + } + + + /******************************************************************************* + * Function Name: USBFS_GetLineControl + ******************************************************************************** + * + * Summary: + * Returns Line control bitmap. + * + * Parameters: + * None. + * + * Return: + * Returns Line control bitmap. + * + * Global variables: + * USBFS_lineControlBitmap: used to get a parameter. + * + *******************************************************************************/ + uint16 USBFS_GetLineControl(void) + { + return(USBFS_lineControlBitmap); + } + +#endif /* End USBFS_ENABLE_CDC_CLASS_API*/ + + +/******************************************************************************* +* Additional user functions supporting CDC Requests +********************************************************************************/ + +/* `#START CDC_FUNCTIONS` Place any additional functions here */ + +/* `#END` */ + +#endif /* End USBFS_ENABLE_CDC_CLASS*/ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.h new file mode 100644 index 00000000..ca79f63e --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.h @@ -0,0 +1,92 @@ +/******************************************************************************* +* File Name: USBFS_cdc.h +* Version 2.60 +* +* Description: +* Header File for the USFS component. +* Contains CDC class prototypes and constant values. +* +******************************************************************************** +* Copyright 2012-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_USBFS_USBFS_cdc_H) +#define CY_USBFS_USBFS_cdc_H + +#include "cytypes.h" + + +/*************************************** +* Prototypes of the USBFS_cdc API. +***************************************/ + +#if (USBFS_ENABLE_CDC_CLASS_API != 0u) + void USBFS_CDC_Init(void) ; + void USBFS_PutData(const uint8* pData, uint16 length) ; + void USBFS_PutString(const char8 string[]) ; + void USBFS_PutChar(char8 txDataByte) ; + void USBFS_PutCRLF(void) ; + uint16 USBFS_GetCount(void) ; + uint8 USBFS_CDCIsReady(void) ; + uint8 USBFS_DataIsReady(void) ; + uint16 USBFS_GetData(uint8* pData, uint16 length) ; + uint16 USBFS_GetAll(uint8* pData) ; + uint8 USBFS_GetChar(void) ; + uint8 USBFS_IsLineChanged(void) ; + uint32 USBFS_GetDTERate(void) ; + uint8 USBFS_GetCharFormat(void) ; + uint8 USBFS_GetParityType(void) ; + uint8 USBFS_GetDataBits(void) ; + uint16 USBFS_GetLineControl(void) ; +#endif /* End USBFS_ENABLE_CDC_CLASS_API*/ + + +/*************************************** +* Constants for USBFS_cdc API. +***************************************/ + +/* CDC Class-Specific Request Codes (CDC ver 1.2 Table 19) */ +#define USBFS_CDC_SET_LINE_CODING (0x20u) +#define USBFS_CDC_GET_LINE_CODING (0x21u) +#define USBFS_CDC_SET_CONTROL_LINE_STATE (0x22u) + +#define USBFS_LINE_CODING_CHANGED (0x01u) +#define USBFS_LINE_CONTROL_CHANGED (0x02u) + +#define USBFS_1_STOPBIT (0x00u) +#define USBFS_1_5_STOPBITS (0x01u) +#define USBFS_2_STOPBITS (0x02u) + +#define USBFS_PARITY_NONE (0x00u) +#define USBFS_PARITY_ODD (0x01u) +#define USBFS_PARITY_EVEN (0x02u) +#define USBFS_PARITY_MARK (0x03u) +#define USBFS_PARITY_SPACE (0x04u) + +#define USBFS_LINE_CODING_SIZE (0x07u) +#define USBFS_LINE_CODING_RATE (0x00u) +#define USBFS_LINE_CODING_STOP_BITS (0x04u) +#define USBFS_LINE_CODING_PARITY (0x05u) +#define USBFS_LINE_CODING_DATA_BITS (0x06u) + +#define USBFS_LINE_CONTROL_DTR (0x01u) +#define USBFS_LINE_CONTROL_RTS (0x02u) + + +/*************************************** +* External data references +***************************************/ + +extern volatile uint8 USBFS_lineCoding[USBFS_LINE_CODING_SIZE]; +extern volatile uint8 USBFS_lineChanged; +extern volatile uint16 USBFS_lineControlBitmap; +extern volatile uint8 USBFS_cdc_data_in_ep; +extern volatile uint8 USBFS_cdc_data_out_ep; + +#endif /* End CY_USBFS_USBFS_cdc_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf new file mode 100644 index 00000000..8a8f5bea --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf @@ -0,0 +1,122 @@ +;****************************************************************************** +; File Name: USBFS_cdc.inf +; Version 2.60 +; +; Description: +; Windows USB CDC setup file for USBUART Device. +; +;****************************************************************************** +; Copyright 2007-2013, Cypress Semiconductor Corporation. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;****************************************************************************** + +[Version] +Signature="$Windows NT$" +Class=Ports +ClassGuid={4D36E978-E325-11CE-BFC1-08002BE10318} +Provider=%PROVIDER% +LayoutFile=layout.inf +DriverVer=03/05/2007,2.0.0000.0 + +[Manufacturer] +%MFGNAME%=DeviceList, NTx86, NTia64, NTamd64 + +[DestinationDirs] +DefaultDestDir=12 + +[SourceDisksFiles] + +[SourceDisksNames] + +[DeviceList.NTx86] +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232 + +[DeviceList.NTia64] +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232 + +[DeviceList.NTamd64] +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232 + + +;------------------------------------------------------------------------------ +; 32 bit section for Windows 2000/2003/XP/Vista +;------------------------------------------------------------------------------ + +[DriverInstall.NTx86] +include=mdmcpq.inf +CopyFiles=DriverCopyFiles +AddReg=DriverInstall.NTx86.AddReg + +[DriverCopyFiles] +usbser.sys,,,0x20 + +[DriverInstall.NTx86.AddReg] +HKR,,DevLoader,,*ntkern +HKR,,NTMPDriver,,usbser.sys +HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" + +[DriverInstall.NTx86.Services] +AddService=usbser, 0x00000002, DriverService + +;------------------------------------------------------------------------------ +; 64 bit section for Intel Itanium based systems +;------------------------------------------------------------------------------ + +[DriverInstall.NTia64] +include=mdmcpq.inf +CopyFiles=DriverCopyFiles +AddReg=DriverInstall.NTia64.AddReg + +[DriverCopyFiles] +usbser.sys,,,0x20 + +[DriverInstall.NTia64.AddReg] +HKR,,DevLoader,,*ntkern +HKR,,NTMPDriver,,usbser.sys +HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" + +[DriverInstall.NTia64.Services] +AddService=usbser, 0x00000002, DriverService + +;------------------------------------------------------------------------------ +; 64 bit section for AMD64 and Intel EM64T based systems +;------------------------------------------------------------------------------ + +[DriverInstall.NTamd64] +include=mdmcpq.inf +CopyFiles=DriverCopyFiles +AddReg=DriverInstall.NTamd64.AddReg + +[DriverCopyFiles] +usbser.sys,,,0x20 + +[DriverInstall.NTamd64.AddReg] +HKR,,DevLoader,,*ntkern +HKR,,NTMPDriver,,usbser.sys +HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" + +[DriverInstall.NTamd64.Services] +AddService=usbser, 0x00000002, DriverService + +;------------------------------------------------------------------------------ +; +;------------------------------------------------------------------------------ + +[DriverService] +DisplayName=%SERVICE% +ServiceType=1 +StartType=3 +ErrorControl=1 +ServiceBinary=%12%\usbser.sys + +;------------------------------------------------------------------------------ +; String Definitions +;------------------------------------------------------------------------------ + +[Strings] +PROVIDER="Cypress" +MFGNAME="Cypress Semiconductor Corporation" +DESCRIPTION="Cypress USB UART" +SERVICE="USB UART" diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_cls.c b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_cls.c new file mode 100644 index 00000000..7b5dc275 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_cls.c @@ -0,0 +1,107 @@ +/******************************************************************************* +* File Name: USBFS_cls.c +* Version 2.60 +* +* Description: +* USB Class request handler. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS.h" + +#if(USBFS_EXTERN_CLS == USBFS_FALSE) + +#include "USBFS_pvt.h" + + +/*************************************** +* User Implemented Class Driver Declarations. +***************************************/ +/* `#START USER_DEFINED_CLASS_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +/******************************************************************************* +* Function Name: USBFS_DispatchClassRqst +******************************************************************************** +* Summary: +* This routine dispatches class specific requests depend on interface class. +* +* Parameters: +* None. +* +* Return: +* requestHandled. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_DispatchClassRqst(void) +{ + uint8 requestHandled = USBFS_FALSE; + uint8 interfaceNumber = 0u; + + switch(CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) + { + case USBFS_RQST_RCPT_IFC: /* Class-specific request directed to an interface */ + interfaceNumber = CY_GET_REG8(USBFS_wIndexLo); /* wIndexLo contain Interface number */ + break; + case USBFS_RQST_RCPT_EP: /* Class-specific request directed to the endpoint */ + /* Find related interface to the endpoint, wIndexLo contain EP number */ + interfaceNumber = + USBFS_EP[CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED].interface; + break; + default: /* RequestHandled is initialized as FALSE by default */ + break; + } + /* Handle Class request depend on interface type */ + switch(USBFS_interfaceClass[interfaceNumber]) + { + case USBFS_CLASS_HID: + #if defined(USBFS_ENABLE_HID_CLASS) + requestHandled = USBFS_DispatchHIDClassRqst(); + #endif /* USBFS_ENABLE_HID_CLASS */ + break; + case USBFS_CLASS_AUDIO: + #if defined(USBFS_ENABLE_AUDIO_CLASS) + requestHandled = USBFS_DispatchAUDIOClassRqst(); + #endif /* USBFS_ENABLE_HID_CLASS */ + break; + case USBFS_CLASS_CDC: + #if defined(USBFS_ENABLE_CDC_CLASS) + requestHandled = USBFS_DispatchCDCClassRqst(); + #endif /* USBFS_ENABLE_CDC_CLASS */ + break; + default: /* requestHandled is initialized as FALSE by default */ + break; + } + + /* `#START USER_DEFINED_CLASS_CODE` Place your Class request here */ + + /* `#END` */ + + return(requestHandled); +} + + +/******************************************************************************* +* Additional user functions supporting Class Specific Requests +********************************************************************************/ + +/* `#START CLASS_SPECIFIC_FUNCTIONS` Place any additional functions here */ + +/* `#END` */ + +#endif /* USBFS_EXTERN_CLS */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_descr.c b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_descr.c new file mode 100755 index 00000000..094719e6 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_descr.c @@ -0,0 +1,323 @@ +/******************************************************************************* +* File Name: USBFS_descr.c +* Version 2.60 +* +* Description: +* USB descriptors and storage. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS.h" +#include "USBFS_pvt.h" + + +/***************************************************************************** +* User supplied descriptors. If you want to specify your own descriptors, +* remove the comments around the define USER_SUPPLIED_DESCRIPTORS below and +* add your descriptors. +*****************************************************************************/ +/* `#START USER_DESCRIPTORS_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +/*************************************** +* USB Customizer Generated Descriptors +***************************************/ + +#if !defined(USER_SUPPLIED_DESCRIPTORS) +/********************************************************************* +* Device Descriptors +*********************************************************************/ +const uint8 CYCODE USBFS_DEVICE0_DESCR[18u] = { +/* Descriptor Length */ 0x12u, +/* DescriptorType: DEVICE */ 0x01u, +/* bcdUSB (ver 2.0) */ 0x00u, 0x02u, +/* bDeviceClass */ 0x00u, +/* bDeviceSubClass */ 0x00u, +/* bDeviceProtocol */ 0x00u, +/* bMaxPacketSize0 */ 0x08u, +/* idVendor */ 0xB4u, 0x04u, +/* idProduct */ 0x1Du, 0xB7u, +/* bcdDevice */ 0x02u, 0x30u, +/* iManufacturer */ 0x01u, +/* iProduct */ 0x02u, +/* iSerialNumber */ 0x80u, +/* bNumConfigurations */ 0x01u +}; +/********************************************************************* +* Config Descriptor +*********************************************************************/ +const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_DESCR[41u] = { +/* Config Descriptor Length */ 0x09u, +/* DescriptorType: CONFIG */ 0x02u, +/* wTotalLength */ 0x29u, 0x00u, +/* bNumInterfaces */ 0x01u, +/* bConfigurationValue */ 0x01u, +/* iConfiguration */ 0x00u, +/* bmAttributes */ 0x80u, +/* bMaxPower */ 0x00u, +/********************************************************************* +* Interface Descriptor +*********************************************************************/ +/* Interface Descriptor Length */ 0x09u, +/* DescriptorType: INTERFACE */ 0x04u, +/* bInterfaceNumber */ 0x00u, +/* bAlternateSetting */ 0x00u, +/* bNumEndpoints */ 0x02u, +/* bInterfaceClass */ 0x03u, +/* bInterfaceSubClass */ 0x00u, +/* bInterfaceProtocol */ 0x00u, +/* iInterface */ 0x02u, +/********************************************************************* +* HID Class Descriptor +*********************************************************************/ +/* HID Class Descriptor Length */ 0x09u, +/* DescriptorType: HID_CLASS */ 0x21u, +/* bcdHID */ 0x11u, 0x01u, +/* bCountryCode */ 0x00u, +/* bNumDescriptors */ 0x01u, +/* bDescriptorType */ 0x22u, +/* wDescriptorLength (LSB) */ USBFS_HID_RPT_1_SIZE_LSB, +/* wDescriptorLength (MSB) */ USBFS_HID_RPT_1_SIZE_MSB, +/********************************************************************* +* Endpoint Descriptor +*********************************************************************/ +/* Endpoint Descriptor Length */ 0x07u, +/* DescriptorType: ENDPOINT */ 0x05u, +/* bEndpointAddress */ 0x01u, +/* bmAttributes */ 0x03u, +/* wMaxPacketSize */ 0x40u, 0x00u, +/* bInterval */ 0x01u, +/********************************************************************* +* Endpoint Descriptor +*********************************************************************/ +/* Endpoint Descriptor Length */ 0x07u, +/* DescriptorType: ENDPOINT */ 0x05u, +/* bEndpointAddress */ 0x82u, +/* bmAttributes */ 0x03u, +/* wMaxPacketSize */ 0x40u, 0x00u, +/* bInterval */ 0x01u +}; + +/********************************************************************* +* String Descriptor Table +*********************************************************************/ +const uint8 CYCODE USBFS_STRING_DESCRIPTORS[83u] = { +/********************************************************************* +* Language ID Descriptor +*********************************************************************/ +/* Descriptor Length */ 0x04u, +/* DescriptorType: STRING */ 0x03u, +/* Language Id */ 0x09u, 0x04u, +/********************************************************************* +* String Descriptor: "Cypress Semiconductor" +*********************************************************************/ +/* Descriptor Length */ 0x2Cu, +/* DescriptorType: STRING */ 0x03u, + (uint8)'C', 0u,(uint8)'y', 0u,(uint8)'p', 0u,(uint8)'r', 0u,(uint8)'e', 0u, + (uint8)'s', 0u,(uint8)'s', 0u,(uint8)' ', 0u,(uint8)'S', 0u,(uint8)'e', 0u, + (uint8)'m', 0u,(uint8)'i', 0u,(uint8)'c', 0u,(uint8)'o', 0u,(uint8)'n', 0u, + (uint8)'d', 0u,(uint8)'u', 0u,(uint8)'c', 0u,(uint8)'t', 0u,(uint8)'o', 0u, + (uint8)'r', 0u, +/********************************************************************* +* String Descriptor: "PSoC3 Bootloader" +*********************************************************************/ +/* Descriptor Length */ 0x22u, +/* DescriptorType: STRING */ 0x03u, + (uint8)'P', 0u,(uint8)'S', 0u,(uint8)'o', 0u,(uint8)'C', 0u,(uint8)'3', 0u, + (uint8)' ', 0u,(uint8)'B', 0u,(uint8)'o', 0u,(uint8)'o', 0u,(uint8)'t', 0u, + (uint8)'l', 0u,(uint8)'o', 0u,(uint8)'a', 0u,(uint8)'d', 0u,(uint8)'e', 0u, + (uint8)'r', 0u, +/*********************************************************************/ +/* Marks the end of the list. */ 0x00u}; +/*********************************************************************/ + +/********************************************************************* +* Serial Number String Descriptor +*********************************************************************/ +const uint8 CYCODE USBFS_SN_STRING_DESCRIPTOR[10] = { +/* Descriptor Length */ 0x0Au, +/* DescriptorType: STRING */ 0x03u, +(uint8)'0', 0u,(uint8)'0', 0u,(uint8)'0', 0u,(uint8)'1', 0u +}; + +/********************************************************************* +* HID Report Descriptor: Generic HID +*********************************************************************/ +const uint8 CYCODE USBFS_HIDREPORT_DESCRIPTOR1[40u] = { +/* Descriptor Size (Not part of descriptor)*/ USBFS_HID_RPT_1_SIZE_LSB, +USBFS_HID_RPT_1_SIZE_MSB, +/* USAGE_PAGE */ 0x05u, 0x01u, +/* USAGE */ 0x09u, 0x00u, +/* COLLECTION */ 0xA1u, 0x00u, +/* USAGE */ 0x09u, 0x00u, +/* COLLECTION */ 0xA1u, 0x00u, +/* USAGE */ 0x09u, 0x00u, +/* LOGICAL_MINIMUM */ 0x15u, 0x00u, +/* LOGICAL_MAXIMUM */ 0x25u, 0xFFu, +/* REPORT_SIZE */ 0x75u, 0x08u, +/* REPORT_COUNT */ 0x95u, 0x40u, +/* OUTPUT */ 0x91u, 0x02u, +/* USAGE */ 0x09u, 0x00u, +/* LOGICAL_MINIMUM */ 0x15u, 0x00u, +/* LOGICAL_MAXIMUM */ 0x25u, 0xFFu, +/* REPORT_SIZE */ 0x75u, 0x08u, +/* REPORT_COUNT */ 0x95u, 0x40u, +/* INPUT */ 0x81u, 0x02u, +/* END_COLLECTION */ 0xC0u, +/* END_COLLECTION */ 0xC0u, +/*********************************************************************/ +/* End of the HID Report Descriptor */ 0x00u, 0x00u}; +/*********************************************************************/ + +#if !defined(USER_DEFINE_USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_HID_RPT_STORAGE) +/********************************************************************* +* HID Input Report Storage +*********************************************************************/ +T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_RPT_SCB; +uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF[ + USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF_SIZE]; + +/********************************************************************* +* HID Input Report TD Table +*********************************************************************/ +const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_RPT_TABLE[1u] = { + {USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF_SIZE, + &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF[0u], + &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_RPT_SCB}, +}; +/********************************************************************* +* HID Output Report Storage +*********************************************************************/ +T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_RPT_SCB; +uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF[ + USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF_SIZE]; + +/********************************************************************* +* HID Output Report TD Table +*********************************************************************/ +const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_RPT_TABLE[1u] = { + {USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF_SIZE, + &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF[0u], + &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_RPT_SCB}, +}; +/********************************************************************* +* HID Report Look Up Table This table has four entries: +* IN Report Table +* OUT Report Table +* Feature Report Table +* HID Report Descriptor +* HID Class Descriptor +*********************************************************************/ +const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_TABLE[5u] = { + {0x00u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_RPT_TABLE}, + {0x00u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_RPT_TABLE}, + {0x00u, NULL}, + {0x01u, (const void *)&USBFS_HIDREPORT_DESCRIPTOR1[0]}, + {0x01u, (const void *)&USBFS_DEVICE0_CONFIGURATION0_DESCR[18]} +}; +#endif /* USER_DEFINE_USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_HID_RPT_STORAGE */ + +/********************************************************************* +* Interface Dispatch Table -- Points to the Class Dispatch Tables +*********************************************************************/ +const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_TABLE[1u] = { + {USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_COUNT, + &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_TABLE} +}; +/********************************************************************* +* Endpoint Setting Table -- This table contain the endpoint setting +* for each endpoint in the configuration. It +* contains the necessary information to +* configure the endpoint hardware for each +* interface and alternate setting. +*********************************************************************/ +const T_USBFS_EP_SETTINGS_BLOCK CYCODE USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE[2u] = { +/* IFC ALT EPAddr bmAttr MaxPktSize Class ********************/ +{0x00u, 0x00u, 0x01u, 0x03u, 0x0040u, 0x03u}, +{0x00u, 0x00u, 0x82u, 0x03u, 0x0040u, 0x03u} +}; +const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE_CLASS[1u] = { +0x03u +}; +/********************************************************************* +* Config Dispatch Table -- Points to the Config Descriptor and each of +* and endpoint setup table and to each +* interface table if it specifies a USB Class +*********************************************************************/ +const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_TABLE[4u] = { + {0x01u, &USBFS_DEVICE0_CONFIGURATION0_DESCR}, + {0x02u, &USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE}, + {0x01u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_TABLE}, + {0x00u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE_CLASS} +}; +/********************************************************************* +* Device Dispatch Table -- Points to the Device Descriptor and each of +* and Configuration Tables for this Device +*********************************************************************/ +const T_USBFS_LUT CYCODE USBFS_DEVICE0_TABLE[2u] = { + {0x01u, &USBFS_DEVICE0_DESCR}, + {0x01u, &USBFS_DEVICE0_CONFIGURATION0_TABLE} +}; +/********************************************************************* +* Device Table -- Indexed by the device number. +*********************************************************************/ +const T_USBFS_LUT CYCODE USBFS_TABLE[1u] = { + {0x01u, &USBFS_DEVICE0_TABLE} +}; + +#endif /* USER_SUPPLIED_DESCRIPTORS */ + +#if defined(USBFS_ENABLE_MSOS_STRING) + + /****************************************************************************** + * USB Microsoft OS String Descriptor + * "MSFT" identifies a Microsoft host + * "100" specifies version 1.00 + * USBFS_GET_EXTENDED_CONFIG_DESCRIPTOR becomes the bRequest value + * in a host vendor device/class request + ******************************************************************************/ + + const uint8 CYCODE USBFS_MSOS_DESCRIPTOR[USBFS_MSOS_DESCRIPTOR_LENGTH] = { + /* Descriptor Length */ 0x12u, + /* DescriptorType: STRING */ 0x03u, + /* qwSignature - "MSFT100" */ (uint8)'M', 0u, (uint8)'S', 0u, (uint8)'F', 0u, (uint8)'T', 0u, + (uint8)'1', 0u, (uint8)'0', 0u, (uint8)'0', 0u, + /* bMS_VendorCode: */ USBFS_GET_EXTENDED_CONFIG_DESCRIPTOR, + /* bPad */ 0x00u + }; + + /* Extended Configuration Descriptor */ + + const uint8 CYCODE USBFS_MSOS_CONFIGURATION_DESCR[USBFS_MSOS_CONF_DESCR_LENGTH] = { + /* Length of the descriptor 4 bytes */ 0x28u, 0x00u, 0x00u, 0x00u, + /* Version of the descriptor 2 bytes */ 0x00u, 0x01u, + /* wIndex - Fixed:INDEX_CONFIG_DESCRIPTOR */ 0x04u, 0x00u, + /* bCount - Count of device functions. */ 0x01u, + /* Reserved : 7 bytes */ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + /* bFirstInterfaceNumber */ 0x00u, + /* Reserved */ 0x01u, + /* compatibleID - "CYUSB\0\0" */ (uint8)'C', (uint8)'Y', (uint8)'U', (uint8)'S', (uint8)'B', + 0x00u, 0x00u, 0x00u, + /* subcompatibleID - "00001\0\0" */ (uint8)'0', (uint8)'0', (uint8)'0', (uint8)'0', (uint8)'1', + 0x00u, 0x00u, 0x00u, + /* Reserved : 6 bytes */ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u + }; + +#endif /* USBFS_ENABLE_MSOS_STRING */ + +/* DIE ID string descriptor for 8 bytes ID */ +#if defined(USBFS_ENABLE_IDSN_STRING) + uint8 USBFS_idSerialNumberStringDescriptor[USBFS_IDSN_DESCR_LENGTH]; +#endif /* USBFS_ENABLE_IDSN_STRING */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_drv.c b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_drv.c new file mode 100644 index 00000000..f4308eab --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_drv.c @@ -0,0 +1,781 @@ +/******************************************************************************* +* File Name: USBFS_drv.c +* Version 2.60 +* +* Description: +* Endpoint 0 Driver for the USBFS Component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS.h" +#include "USBFS_pvt.h" + + +/*************************************** +* Global data allocation +***************************************/ + +volatile T_USBFS_EP_CTL_BLOCK USBFS_EP[USBFS_MAX_EP]; +volatile uint8 USBFS_configuration; +volatile uint8 USBFS_interfaceNumber; +volatile uint8 USBFS_configurationChanged; +volatile uint8 USBFS_deviceAddress; +volatile uint8 USBFS_deviceStatus; +volatile uint8 USBFS_interfaceSetting[USBFS_MAX_INTERFACES_NUMBER]; +volatile uint8 USBFS_interfaceSetting_last[USBFS_MAX_INTERFACES_NUMBER]; +volatile uint8 USBFS_interfaceStatus[USBFS_MAX_INTERFACES_NUMBER]; +volatile uint8 USBFS_device; +const uint8 CYCODE *USBFS_interfaceClass; + + +/*************************************** +* Local data allocation +***************************************/ + +volatile uint8 USBFS_ep0Toggle; +volatile uint8 USBFS_lastPacketSize; +volatile uint8 USBFS_transferState; +volatile T_USBFS_TD USBFS_currentTD; +volatile uint8 USBFS_ep0Mode; +volatile uint8 USBFS_ep0Count; +volatile uint16 USBFS_transferByteCount; + + +/******************************************************************************* +* Function Name: USBFS_ep_0_Interrupt +******************************************************************************** +* +* Summary: +* This Interrupt Service Routine handles Endpoint 0 (Control Pipe) traffic. +* It dispatches setup requests and handles the data and status stages. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +CY_ISR(USBFS_EP_0_ISR) +{ + uint8 bRegTemp; + uint8 modifyReg; + + + bRegTemp = CY_GET_REG8(USBFS_EP0_CR_PTR); + if ((bRegTemp & USBFS_MODE_ACKD) != 0u) + { + modifyReg = 1u; + if ((bRegTemp & USBFS_MODE_SETUP_RCVD) != 0u) + { + if((bRegTemp & USBFS_MODE_MASK) != USBFS_MODE_NAK_IN_OUT) + { + modifyReg = 0u; /* When mode not NAK_IN_OUT => invalid setup */ + } + else + { + USBFS_HandleSetup(); + if((USBFS_ep0Mode & USBFS_MODE_SETUP_RCVD) != 0u) + { + modifyReg = 0u; /* if SETUP bit set -> exit without modifying the mode */ + } + + } + } + else if ((bRegTemp & USBFS_MODE_IN_RCVD) != 0u) + { + USBFS_HandleIN(); + } + else if ((bRegTemp & USBFS_MODE_OUT_RCVD) != 0u) + { + USBFS_HandleOUT(); + } + else + { + modifyReg = 0u; + } + if(modifyReg != 0u) + { + bRegTemp = CY_GET_REG8(USBFS_EP0_CR_PTR); /* unlock registers */ + if((bRegTemp & USBFS_MODE_SETUP_RCVD) == 0u) /* Check if SETUP bit is not set, otherwise exit */ + { + /* Update the count register */ + bRegTemp = USBFS_ep0Toggle | USBFS_ep0Count; + CY_SET_REG8(USBFS_EP0_CNT_PTR, bRegTemp); + if(bRegTemp == CY_GET_REG8(USBFS_EP0_CNT_PTR)) /* continue if writing was successful */ + { + do + { + modifyReg = USBFS_ep0Mode; /* Init temporary variable */ + /* Unlock registers */ + bRegTemp = CY_GET_REG8(USBFS_EP0_CR_PTR) & USBFS_MODE_SETUP_RCVD; + if(bRegTemp == 0u) /* Check if SETUP bit is not set */ + { + /* Set the Mode Register */ + CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_ep0Mode); + /* Writing check */ + modifyReg = CY_GET_REG8(USBFS_EP0_CR_PTR) & USBFS_MODE_MASK; + } + }while(modifyReg != USBFS_ep0Mode); /* Repeat if writing was not successful */ + } + } + } + } +} + + +/******************************************************************************* +* Function Name: USBFS_HandleSetup +******************************************************************************** +* +* Summary: +* This Routine dispatches requests for the four USB request types +* +* Parameters: +* None. +* +* Return: +* None. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_HandleSetup(void) +{ + uint8 requestHandled; + + requestHandled = CY_GET_REG8(USBFS_EP0_CR_PTR); /* unlock registers */ + CY_SET_REG8(USBFS_EP0_CR_PTR, requestHandled); /* clear setup bit */ + requestHandled = CY_GET_REG8(USBFS_EP0_CR_PTR); /* reread register */ + if((requestHandled & USBFS_MODE_SETUP_RCVD) != 0u) + { + USBFS_ep0Mode = requestHandled; /* if SETUP bit set -> exit without modifying the mode */ + } + else + { + /* In case the previous transfer did not complete, close it out */ + USBFS_UpdateStatusBlock(USBFS_XFER_PREMATURE); + + switch (CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_TYPE_MASK) + { + case USBFS_RQST_TYPE_STD: + requestHandled = USBFS_HandleStandardRqst(); + break; + case USBFS_RQST_TYPE_CLS: + requestHandled = USBFS_DispatchClassRqst(); + break; + case USBFS_RQST_TYPE_VND: + requestHandled = USBFS_HandleVendorRqst(); + break; + default: + requestHandled = USBFS_FALSE; + break; + } + if (requestHandled == USBFS_FALSE) + { + USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; + } + } +} + + +/******************************************************************************* +* Function Name: USBFS_HandleIN +******************************************************************************** +* +* Summary: +* This routine handles EP0 IN transfers. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_HandleIN(void) +{ + switch (USBFS_transferState) + { + case USBFS_TRANS_STATE_IDLE: + break; + case USBFS_TRANS_STATE_CONTROL_READ: + USBFS_ControlReadDataStage(); + break; + case USBFS_TRANS_STATE_CONTROL_WRITE: + USBFS_ControlWriteStatusStage(); + break; + case USBFS_TRANS_STATE_NO_DATA_CONTROL: + USBFS_NoDataControlStatusStage(); + break; + default: /* there are no more states */ + break; + } +} + + +/******************************************************************************* +* Function Name: USBFS_HandleOUT +******************************************************************************** +* +* Summary: +* This routine handles EP0 OUT transfers. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_HandleOUT(void) +{ + switch (USBFS_transferState) + { + case USBFS_TRANS_STATE_IDLE: + break; + case USBFS_TRANS_STATE_CONTROL_READ: + USBFS_ControlReadStatusStage(); + break; + case USBFS_TRANS_STATE_CONTROL_WRITE: + USBFS_ControlWriteDataStage(); + break; + case USBFS_TRANS_STATE_NO_DATA_CONTROL: + /* Update the completion block */ + USBFS_UpdateStatusBlock(USBFS_XFER_ERROR); + /* We expect no more data, so stall INs and OUTs */ + USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; + break; + default: /* There are no more states */ + break; + } +} + + +/******************************************************************************* +* Function Name: USBFS_LoadEP0 +******************************************************************************** +* +* Summary: +* This routine loads the EP0 data registers for OUT transfers. It uses the +* currentTD (previously initialized by the _InitControlWrite function and +* updated for each OUT transfer, and the bLastPacketSize) to determine how +* many uint8s to transfer on the current OUT. +* +* If the number of uint8s remaining is zero and the last transfer was full, +* we need to send a zero length packet. Otherwise we send the minimum +* of the control endpoint size (8) or remaining number of uint8s for the +* transaction. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* USBFS_transferByteCount - Update the transfer byte count from the +* last transaction. +* USBFS_ep0Count - counts the data loaded to the SIE memory in +* current packet. +* USBFS_lastPacketSize - remembers the USBFS_ep0Count value for the +* next packet. +* USBFS_transferByteCount - sum of the previous bytes transferred +* on previous packets(sum of USBFS_lastPacketSize) +* USBFS_ep0Toggle - inverted +* USBFS_ep0Mode - prepare for mode register content. +* USBFS_transferState - set to TRANS_STATE_CONTROL_READ +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_LoadEP0(void) +{ + uint8 ep0Count = 0u; + + /* Update the transfer byte count from the last transaction */ + USBFS_transferByteCount += USBFS_lastPacketSize; + /* Now load the next transaction */ + while ((USBFS_currentTD.count > 0u) && (ep0Count < 8u)) + { + CY_SET_REG8((reg8 *)(USBFS_EP0_DR0_IND + ep0Count), *USBFS_currentTD.pData); + USBFS_currentTD.pData = &USBFS_currentTD.pData[1u]; + ep0Count++; + USBFS_currentTD.count--; + } + /* Support zero-length packet*/ + if( (USBFS_lastPacketSize == 8u) || (ep0Count > 0u) ) + { + /* Update the data toggle */ + USBFS_ep0Toggle ^= USBFS_EP0_CNT_DATA_TOGGLE; + /* Set the Mode Register */ + USBFS_ep0Mode = USBFS_MODE_ACK_IN_STATUS_OUT; + /* Update the state (or stay the same) */ + USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ; + } + else + { + /* Expect Status Stage Out */ + USBFS_ep0Mode = USBFS_MODE_STATUS_OUT_ONLY; + /* Update the state (or stay the same) */ + USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ; + } + + /* Save the packet size for next time */ + USBFS_lastPacketSize = ep0Count; + USBFS_ep0Count = ep0Count; +} + + +/******************************************************************************* +* Function Name: USBFS_InitControlRead +******************************************************************************** +* +* Summary: +* Initialize a control read transaction, usable to send data to the host. +* The following global variables should be initialized before this function +* called. To send zero length packet use InitZeroLengthControlTransfer +* function. +* +* Parameters: +* None. +* +* Return: +* requestHandled state. +* +* Global variables: +* USBFS_currentTD.count - counts of data to be sent. +* USBFS_currentTD.pData - data pointer. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_InitControlRead(void) +{ + uint16 xferCount; + if(USBFS_currentTD.count == 0u) + { + (void) USBFS_InitZeroLengthControlTransfer(); + } + else + { + /* Set up the state machine */ + USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ; + /* Set the toggle, it gets updated in LoadEP */ + USBFS_ep0Toggle = 0u; + /* Initialize the Status Block */ + USBFS_InitializeStatusBlock(); + xferCount = (((uint16)CY_GET_REG8(USBFS_lengthHi) << 8u) | (CY_GET_REG8(USBFS_lengthLo))); + + if (USBFS_currentTD.count > xferCount) + { + USBFS_currentTD.count = xferCount; + } + USBFS_LoadEP0(); + } + + return(USBFS_TRUE); +} + + +/******************************************************************************* +* Function Name: USBFS_InitZeroLengthControlTransfer +******************************************************************************** +* +* Summary: +* Initialize a zero length data IN transfer. +* +* Parameters: +* None. +* +* Return: +* requestHandled state. +* +* Global variables: +* USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE +* USBFS_ep0Mode - prepare for mode register content. +* USBFS_transferState - set to TRANS_STATE_CONTROL_READ +* USBFS_ep0Count - cleared, means the zero-length packet. +* USBFS_lastPacketSize - cleared. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_InitZeroLengthControlTransfer(void) + +{ + /* Update the state */ + USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ; + /* Set the data toggle */ + USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE; + /* Set the Mode Register */ + USBFS_ep0Mode = USBFS_MODE_ACK_IN_STATUS_OUT; + /* Save the packet size for next time */ + USBFS_lastPacketSize = 0u; + USBFS_ep0Count = 0u; + + return(USBFS_TRUE); +} + + +/******************************************************************************* +* Function Name: USBFS_ControlReadDataStage +******************************************************************************** +* +* Summary: +* Handle the Data Stage of a control read transfer. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_ControlReadDataStage(void) + +{ + USBFS_LoadEP0(); +} + + +/******************************************************************************* +* Function Name: USBFS_ControlReadStatusStage +******************************************************************************** +* +* Summary: +* Handle the Status Stage of a control read transfer. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* USBFS_USBFS_transferByteCount - updated with last packet size. +* USBFS_transferState - set to TRANS_STATE_IDLE. +* USBFS_ep0Mode - set to MODE_STALL_IN_OUT. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_ControlReadStatusStage(void) +{ + /* Update the transfer byte count */ + USBFS_transferByteCount += USBFS_lastPacketSize; + /* Go Idle */ + USBFS_transferState = USBFS_TRANS_STATE_IDLE; + /* Update the completion block */ + USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK); + /* We expect no more data, so stall INs and OUTs */ + USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; +} + + +/******************************************************************************* +* Function Name: USBFS_InitControlWrite +******************************************************************************** +* +* Summary: +* Initialize a control write transaction +* +* Parameters: +* None. +* +* Return: +* requestHandled state. +* +* Global variables: +* USBFS_USBFS_transferState - set to TRANS_STATE_CONTROL_WRITE +* USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE +* USBFS_ep0Mode - set to MODE_ACK_OUT_STATUS_IN +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_InitControlWrite(void) +{ + uint16 xferCount; + + /* Set up the state machine */ + USBFS_transferState = USBFS_TRANS_STATE_CONTROL_WRITE; + /* This might not be necessary */ + USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE; + /* Initialize the Status Block */ + USBFS_InitializeStatusBlock(); + + xferCount = (((uint16)CY_GET_REG8(USBFS_lengthHi) << 8u) | (CY_GET_REG8(USBFS_lengthLo))); + + if (USBFS_currentTD.count > xferCount) + { + USBFS_currentTD.count = xferCount; + } + + /* Expect Data or Status Stage */ + USBFS_ep0Mode = USBFS_MODE_ACK_OUT_STATUS_IN; + + return(USBFS_TRUE); +} + + +/******************************************************************************* +* Function Name: USBFS_ControlWriteDataStage +******************************************************************************** +* +* Summary: +* Handle the Data Stage of a control write transfer +* 1. Get the data (We assume the destination was validated previously) +* 2. Update the count and data toggle +* 3. Update the mode register for the next transaction +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* USBFS_transferByteCount - Update the transfer byte count from the +* last transaction. +* USBFS_ep0Count - counts the data loaded from the SIE memory +* in current packet. +* USBFS_transferByteCount - sum of the previous bytes transferred +* on previous packets(sum of USBFS_lastPacketSize) +* USBFS_ep0Toggle - inverted +* USBFS_ep0Mode - set to MODE_ACK_OUT_STATUS_IN. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_ControlWriteDataStage(void) +{ + uint8 ep0Count; + uint8 regIndex = 0u; + + ep0Count = (CY_GET_REG8(USBFS_EP0_CNT_PTR) & USBFS_EPX_CNT0_MASK) - + USBFS_EPX_CNTX_CRC_COUNT; + + USBFS_transferByteCount += ep0Count; + + while ((USBFS_currentTD.count > 0u) && (ep0Count > 0u)) + { + *USBFS_currentTD.pData = CY_GET_REG8((reg8 *)(USBFS_EP0_DR0_IND + regIndex)); + USBFS_currentTD.pData = &USBFS_currentTD.pData[1u]; + regIndex++; + ep0Count--; + USBFS_currentTD.count--; + } + USBFS_ep0Count = ep0Count; + /* Update the data toggle */ + USBFS_ep0Toggle ^= USBFS_EP0_CNT_DATA_TOGGLE; + /* Expect Data or Status Stage */ + USBFS_ep0Mode = USBFS_MODE_ACK_OUT_STATUS_IN; +} + + +/******************************************************************************* +* Function Name: USBFS_ControlWriteStatusStage +******************************************************************************** +* +* Summary: +* Handle the Status Stage of a control write transfer +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* USBFS_transferState - set to TRANS_STATE_IDLE. +* USBFS_USBFS_ep0Mode - set to MODE_STALL_IN_OUT. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_ControlWriteStatusStage(void) +{ + /* Go Idle */ + USBFS_transferState = USBFS_TRANS_STATE_IDLE; + /* Update the completion block */ + USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK); + /* We expect no more data, so stall INs and OUTs */ + USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; +} + + +/******************************************************************************* +* Function Name: USBFS_InitNoDataControlTransfer +******************************************************************************** +* +* Summary: +* Initialize a no data control transfer +* +* Parameters: +* None. +* +* Return: +* requestHandled state. +* +* Global variables: +* USBFS_transferState - set to TRANS_STATE_NO_DATA_CONTROL. +* USBFS_ep0Mode - set to MODE_STATUS_IN_ONLY. +* USBFS_ep0Count - cleared. +* USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_InitNoDataControlTransfer(void) +{ + USBFS_transferState = USBFS_TRANS_STATE_NO_DATA_CONTROL; + USBFS_ep0Mode = USBFS_MODE_STATUS_IN_ONLY; + USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE; + USBFS_ep0Count = 0u; + + return(USBFS_TRUE); +} + + +/******************************************************************************* +* Function Name: USBFS_NoDataControlStatusStage +******************************************************************************** +* Summary: +* Handle the Status Stage of a no data control transfer. +* +* SET_ADDRESS is special, since we need to receive the status stage with +* the old address. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* USBFS_transferState - set to TRANS_STATE_IDLE. +* USBFS_ep0Mode - set to MODE_STALL_IN_OUT. +* USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE +* USBFS_deviceAddress - used to set new address and cleared +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_NoDataControlStatusStage(void) +{ + /* Change the USB address register if we got a SET_ADDRESS. */ + if (USBFS_deviceAddress != 0u) + { + CY_SET_REG8(USBFS_CR0_PTR, USBFS_deviceAddress | USBFS_CR0_ENABLE); + USBFS_deviceAddress = 0u; + } + /* Go Idle */ + USBFS_transferState = USBFS_TRANS_STATE_IDLE; + /* Update the completion block */ + USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK); + /* We expect no more data, so stall INs and OUTs */ + USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; +} + + +/******************************************************************************* +* Function Name: USBFS_UpdateStatusBlock +******************************************************************************** +* +* Summary: +* Update the Completion Status Block for a Request. The block is updated +* with the completion code the USBFS_transferByteCount. The +* StatusBlock Pointer is set to NULL. +* +* Parameters: +* completionCode - status. +* +* Return: +* None. +* +* Global variables: +* USBFS_currentTD.pStatusBlock->status - updated by the +* completionCode parameter. +* USBFS_currentTD.pStatusBlock->length - updated. +* USBFS_currentTD.pStatusBlock - cleared. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_UpdateStatusBlock(uint8 completionCode) +{ + if (USBFS_currentTD.pStatusBlock != NULL) + { + USBFS_currentTD.pStatusBlock->status = completionCode; + USBFS_currentTD.pStatusBlock->length = USBFS_transferByteCount; + USBFS_currentTD.pStatusBlock = NULL; + } +} + + +/******************************************************************************* +* Function Name: USBFS_InitializeStatusBlock +******************************************************************************** +* +* Summary: +* Initialize the Completion Status Block for a Request. The completion +* code is set to USB_XFER_IDLE. +* +* Also, initializes USBFS_transferByteCount. Save some space, +* this is the only consumer. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* USBFS_currentTD.pStatusBlock->status - set to XFER_IDLE. +* USBFS_currentTD.pStatusBlock->length - cleared. +* USBFS_transferByteCount - cleared. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_InitializeStatusBlock(void) +{ + USBFS_transferByteCount = 0u; + if(USBFS_currentTD.pStatusBlock != NULL) + { + USBFS_currentTD.pStatusBlock->status = USBFS_XFER_IDLE; + USBFS_currentTD.pStatusBlock->length = 0u; + } +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_episr.c b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_episr.c new file mode 100644 index 00000000..d758bf4d --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_episr.c @@ -0,0 +1,658 @@ +/******************************************************************************* +* File Name: USBFS_episr.c +* Version 2.60 +* +* Description: +* Data endpoint Interrupt Service Routines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS.h" +#include "USBFS_pvt.h" +#if defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u) + #include "USBFS_midi.h" +#endif /* End USBFS_ENABLE_MIDI_STREAMING*/ + + +/*************************************** +* Custom Declarations +***************************************/ +/* `#START CUSTOM_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +#if(USBFS_EP1_ISR_REMOVE == 0u) + + + /****************************************************************************** + * Function Name: USBFS_EP_1_ISR + ******************************************************************************* + * + * Summary: + * Endpoint 1 Interrupt Service Routine + * + * Parameters: + * None. + * + * Return: + * None. + * + ******************************************************************************/ + CY_ISR(USBFS_EP_1_ISR) + { + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + uint8 int_en; + #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ + + /* `#START EP1_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + int_en = EA; + CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ + #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ + + CY_GET_REG8(USBFS_SIE_EP1_CR0_PTR); /* Must read the mode reg */ + /* Do not toggle ISOC endpoint */ + if((USBFS_EP[USBFS_EP1].attrib & USBFS_EP_TYPE_MASK) != + USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP1].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + USBFS_EP[USBFS_EP1].apiEpState = USBFS_EVENT_PENDING; + CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) & + (uint8)~USBFS_SIE_EP_INT_EP1_MASK); + + #if( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT ) + if(USBFS_midi_out_ep == USBFS_EP1) + { + USBFS_MIDI_OUT_EP_Service(); + } + #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */ + + /* `#START EP1_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 ) + EA = int_en; + #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ + } + +#endif /* End USBFS_EP1_ISR_REMOVE */ + + +#if(USBFS_EP2_ISR_REMOVE == 0u) + + /******************************************************************************* + * Function Name: USBFS_EP_2_ISR + ******************************************************************************** + * + * Summary: + * Endpoint 2 Interrupt Service Routine + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + CY_ISR(USBFS_EP_2_ISR) + { + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + uint8 int_en; + #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ + + /* `#START EP2_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 ) + int_en = EA; + CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ + #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ + + CY_GET_REG8(USBFS_SIE_EP2_CR0_PTR); /* Must read the mode reg */ + /* Do not toggle ISOC endpoint */ + if((USBFS_EP[USBFS_EP2].attrib & USBFS_EP_TYPE_MASK) != + USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP2].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + USBFS_EP[USBFS_EP2].apiEpState = USBFS_EVENT_PENDING; + CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) + & (uint8)~USBFS_SIE_EP_INT_EP2_MASK); + + #if( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT ) + if(USBFS_midi_out_ep == USBFS_EP2) + { + USBFS_MIDI_OUT_EP_Service(); + } + #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */ + + /* `#START EP2_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + EA = int_en; + #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ + } + +#endif /* End USBFS_EP2_ISR_REMOVE */ + + +#if(USBFS_EP3_ISR_REMOVE == 0u) + + /******************************************************************************* + * Function Name: USBFS_EP_3_ISR + ******************************************************************************** + * + * Summary: + * Endpoint 3 Interrupt Service Routine + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + CY_ISR(USBFS_EP_3_ISR) + { + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + uint8 int_en; + #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ + + /* `#START EP3_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + int_en = EA; + CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + + CY_GET_REG8(USBFS_SIE_EP3_CR0_PTR); /* Must read the mode reg */ + /* Do not toggle ISOC endpoint */ + if((USBFS_EP[USBFS_EP3].attrib & USBFS_EP_TYPE_MASK) != + USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP3].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + USBFS_EP[USBFS_EP3].apiEpState = USBFS_EVENT_PENDING; + CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) + & (uint8)~USBFS_SIE_EP_INT_EP3_MASK); + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT) + if(USBFS_midi_out_ep == USBFS_EP3) + { + USBFS_MIDI_OUT_EP_Service(); + } + #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */ + + /* `#START EP3_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + EA = int_en; + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + } + +#endif /* End USBFS_EP3_ISR_REMOVE */ + + +#if(USBFS_EP4_ISR_REMOVE == 0u) + + /******************************************************************************* + * Function Name: USBFS_EP_4_ISR + ******************************************************************************** + * + * Summary: + * Endpoint 4 Interrupt Service Routine + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + CY_ISR(USBFS_EP_4_ISR) + { + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + uint8 int_en; + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + + /* `#START EP4_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + int_en = EA; + CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + + CY_GET_REG8(USBFS_SIE_EP4_CR0_PTR); /* Must read the mode reg */ + /* Do not toggle ISOC endpoint */ + if((USBFS_EP[USBFS_EP4].attrib & USBFS_EP_TYPE_MASK) != + USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP4].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + USBFS_EP[USBFS_EP4].apiEpState = USBFS_EVENT_PENDING; + CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) + & (uint8)~USBFS_SIE_EP_INT_EP4_MASK); + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT) + if(USBFS_midi_out_ep == USBFS_EP4) + { + USBFS_MIDI_OUT_EP_Service(); + } + #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */ + + /* `#START EP4_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + EA = int_en; + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + } + +#endif /* End USBFS_EP4_ISR_REMOVE */ + + +#if(USBFS_EP5_ISR_REMOVE == 0u) + + /******************************************************************************* + * Function Name: USBFS_EP_5_ISR + ******************************************************************************** + * + * Summary: + * Endpoint 5 Interrupt Service Routine + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + CY_ISR(USBFS_EP_5_ISR) + { + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + uint8 int_en; + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + + /* `#START EP5_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + int_en = EA; + CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + + CY_GET_REG8(USBFS_SIE_EP5_CR0_PTR); /* Must read the mode reg */ + /* Do not toggle ISOC endpoint */ + if((USBFS_EP[USBFS_EP5].attrib & USBFS_EP_TYPE_MASK) != + USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP5].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + USBFS_EP[USBFS_EP5].apiEpState = USBFS_EVENT_PENDING; + CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) + & (uint8)~USBFS_SIE_EP_INT_EP5_MASK); + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT) + if(USBFS_midi_out_ep == USBFS_EP5) + { + USBFS_MIDI_OUT_EP_Service(); + } + #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */ + + /* `#START EP5_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + EA = int_en; + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + } +#endif /* End USBFS_EP5_ISR_REMOVE */ + + +#if(USBFS_EP6_ISR_REMOVE == 0u) + + /******************************************************************************* + * Function Name: USBFS_EP_6_ISR + ******************************************************************************** + * + * Summary: + * Endpoint 6 Interrupt Service Routine + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + CY_ISR(USBFS_EP_6_ISR) + { + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + uint8 int_en; + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + + /* `#START EP6_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + int_en = EA; + CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + + CY_GET_REG8(USBFS_SIE_EP6_CR0_PTR); /* Must read the mode reg */ + /* Do not toggle ISOC endpoint */ + if((USBFS_EP[USBFS_EP6].attrib & USBFS_EP_TYPE_MASK) != + USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP6].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + USBFS_EP[USBFS_EP6].apiEpState = USBFS_EVENT_PENDING; + CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) + & (uint8)~USBFS_SIE_EP_INT_EP6_MASK); + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT) + if(USBFS_midi_out_ep == USBFS_EP6) + { + USBFS_MIDI_OUT_EP_Service(); + } + #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */ + + /* `#START EP6_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + EA = int_en; + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + } + +#endif /* End USBFS_EP6_ISR_REMOVE */ + + +#if(USBFS_EP7_ISR_REMOVE == 0u) + + /******************************************************************************* + * Function Name: USBFS_EP_7_ISR + ******************************************************************************** + * + * Summary: + * Endpoint 7 Interrupt Service Routine + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + CY_ISR(USBFS_EP_7_ISR) + { + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + uint8 int_en; + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + + /* `#START EP7_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + int_en = EA; + CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + + CY_GET_REG8(USBFS_SIE_EP7_CR0_PTR); /* Must read the mode reg */ + /* Do not toggle ISOC endpoint */ + if((USBFS_EP[USBFS_EP7].attrib & USBFS_EP_TYPE_MASK) != + USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP7].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + USBFS_EP[USBFS_EP7].apiEpState = USBFS_EVENT_PENDING; + CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) + & (uint8)~USBFS_SIE_EP_INT_EP7_MASK); + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT) + if(USBFS_midi_out_ep == USBFS_EP7) + { + USBFS_MIDI_OUT_EP_Service(); + } + #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */ + + /* `#START EP7_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + EA = int_en; + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + } + +#endif /* End USBFS_EP7_ISR_REMOVE */ + + +#if(USBFS_EP8_ISR_REMOVE == 0u) + + /******************************************************************************* + * Function Name: USBFS_EP_8_ISR + ******************************************************************************** + * + * Summary: + * Endpoint 8 Interrupt Service Routine + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + CY_ISR(USBFS_EP_8_ISR) + { + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + uint8 int_en; + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + + /* `#START EP8_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + int_en = EA; + CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + + CY_GET_REG8(USBFS_SIE_EP8_CR0_PTR); /* Must read the mode reg */ + /* Do not toggle ISOC endpoint */ + if((USBFS_EP[USBFS_EP8].attrib & USBFS_EP_TYPE_MASK) != + USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP8].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + USBFS_EP[USBFS_EP8].apiEpState = USBFS_EVENT_PENDING; + CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) + & (uint8)~USBFS_SIE_EP_INT_EP8_MASK); + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT) + if(USBFS_midi_out_ep == USBFS_EP8) + { + USBFS_MIDI_OUT_EP_Service(); + } + #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */ + + /* `#START EP8_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + EA = int_en; + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + } + +#endif /* End USBFS_EP8_ISR_REMOVE */ + + +/******************************************************************************* +* Function Name: USBFS_SOF_ISR +******************************************************************************** +* +* Summary: +* Start of Frame Interrupt Service Routine +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +CY_ISR(USBFS_SOF_ISR) +{ + /* `#START SOF_USER_CODE` Place your code here */ + + /* `#END` */ +} + + +/******************************************************************************* +* Function Name: USBFS_BUS_RESET_ISR +******************************************************************************** +* +* Summary: +* USB Bus Reset Interrupt Service Routine. Calls _Start with the same +* parameters as the last USER call to _Start +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +CY_ISR(USBFS_BUS_RESET_ISR) +{ + /* `#START BUS_RESET_USER_CODE` Place your code here */ + + /* `#END` */ + + USBFS_ReInitComponent(); +} + + +#if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u)) + + + /******************************************************************************* + * Function Name: USBFS_ARB_ISR + ******************************************************************************** + * + * Summary: + * Arbiter Interrupt Service Routine + * + * Parameters: + * None. + * + * Return: + * None. + * + * Side effect: + * Search for EP8 int_status will be much slower than search for EP1 int_status. + * + *******************************************************************************/ + CY_ISR(USBFS_ARB_ISR) + { + uint8 int_status; + uint8 ep_status; + uint8 ep = USBFS_EP1; + uint8 ptr = 0u; + + /* `#START ARB_BEGIN_USER_CODE` Place your code here */ + + /* `#END` */ + + int_status = USBFS_ARB_INT_SR_REG; /* read Arbiter Status Register */ + USBFS_ARB_INT_SR_REG = int_status; /* Clear Serviced Interrupts */ + + while(int_status != 0u) + { + if((int_status & 1u) != 0u) /* If EpX interrupt present */ + { /* read Endpoint Status Register */ + ep_status = CY_GET_REG8((reg8 *)(USBFS_ARB_EP1_SR_IND + ptr)); + /* If In Buffer Full */ + if((ep_status & USBFS_ARB_EPX_SR_IN_BUF_FULL) != 0u) + { + if((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u) + { + /* Clear Data ready status */ + *(reg8 *)(USBFS_ARB_EP1_CFG_IND + ptr) &= + (uint8)~USBFS_ARB_EPX_CFG_IN_DATA_RDY; + /* Write the Mode register */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ptr), USBFS_EP[ep].epMode); + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_IN) + if(ep == USBFS_midi_in_ep) + { /* Clear MIDI input pointer */ + USBFS_midiInPointer = 0u; + } + #endif /* End USBFS_ENABLE_MIDI_STREAMING*/ + } + } + /* (re)arm Out EP only for mode2 */ + #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) + /* If DMA Grant */ + if((ep_status & USBFS_ARB_EPX_SR_DMA_GNT) != 0u) + { + if((USBFS_EP[ep].addr & USBFS_DIR_IN) == 0u) + { + USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_PENDING; + /* Write the Mode register */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ptr), + USBFS_EP[ep].epMode); + } + } + #endif /* End USBFS_EP_MM */ + + /* `#START ARB_USER_CODE` Place your code here for handle Buffer Underflow/Overflow */ + + /* `#END` */ + + CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_SR_IND + ptr), ep_status); /* Clear Serviced events */ + } + ptr += USBFS_EPX_CNTX_ADDR_OFFSET; /* prepare pointer for next EP */ + ep++; + int_status >>= 1u; + } + + /* `#START ARB_END_USER_CODE` Place your code here */ + + /* `#END` */ + } + +#endif /* End USBFS_EP_MM */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.c b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.c new file mode 100644 index 00000000..cc1ea1e2 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.c @@ -0,0 +1,422 @@ +/******************************************************************************* +* File Name: USBFS_hid.c +* Version 2.60 +* +* Description: +* USB HID Class request handler. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS.h" + +#if defined(USBFS_ENABLE_HID_CLASS) + +#include "USBFS_pvt.h" +#include "USBFS_hid.h" + + +/*************************************** +* HID Variables +***************************************/ + +volatile uint8 USBFS_hidProtocol[USBFS_MAX_INTERFACES_NUMBER]; /* HID device protocol status */ +volatile uint8 USBFS_hidIdleRate[USBFS_MAX_INTERFACES_NUMBER]; /* HID device idle reload value */ +volatile uint8 USBFS_hidIdleTimer[USBFS_MAX_INTERFACES_NUMBER]; /* HID device idle rate value */ + + +/*************************************** +* Custom Declarations +***************************************/ + +/* `#START HID_CUSTOM_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +/******************************************************************************* +* Function Name: USBFS_UpdateHIDTimer +******************************************************************************** +* +* Summary: +* Updates the HID report timer and reloads it if expired +* +* Parameters: +* interface: Interface Number. +* +* Return: +* status. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_UpdateHIDTimer(uint8 interface) +{ + uint8 stat = USBFS_IDLE_TIMER_INDEFINITE; + + if(USBFS_hidIdleRate[interface] != 0u) + { + if(USBFS_hidIdleTimer[interface] > 0u) + { + USBFS_hidIdleTimer[interface]--; + stat = USBFS_IDLE_TIMER_RUNNING; + } + else + { + USBFS_hidIdleTimer[interface] = USBFS_hidIdleRate[interface]; + stat = USBFS_IDLE_TIMER_EXPIRED; + } + } + + return(stat); +} + + +/******************************************************************************* +* Function Name: USBFS_GetProtocol +******************************************************************************** +* +* Summary: +* Returns the selected protocol value to the application +* +* Parameters: +* interface: Interface Number. +* +* Return: +* Interface protocol. +* +*******************************************************************************/ +uint8 USBFS_GetProtocol(uint8 interface) +{ + return(USBFS_hidProtocol[interface]); +} + + +/******************************************************************************* +* Function Name: USBFS_DispatchHIDClassRqst +******************************************************************************** +* +* Summary: +* This routine dispatches class requests +* +* Parameters: +* None. +* +* Return: +* requestHandled +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_DispatchHIDClassRqst(void) +{ + uint8 requestHandled = USBFS_FALSE; + uint8 interfaceNumber; + + interfaceNumber = CY_GET_REG8(USBFS_wIndexLo); + if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H) + { /* Control Read */ + switch (CY_GET_REG8(USBFS_bRequest)) + { + case USBFS_GET_DESCRIPTOR: + if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_HID_CLASS) + { + USBFS_FindHidClassDecriptor(); + if (USBFS_currentTD.count != 0u) + { + requestHandled = USBFS_InitControlRead(); + } + } + else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_HID_REPORT) + { + USBFS_FindReportDescriptor(); + if (USBFS_currentTD.count != 0u) + { + requestHandled = USBFS_InitControlRead(); + } + } + else + { /* requestHandled is initialezed as FALSE by default */ + } + break; + case USBFS_HID_GET_REPORT: + USBFS_FindReport(); + if (USBFS_currentTD.count != 0u) + { + requestHandled = USBFS_InitControlRead(); + } + break; + + case USBFS_HID_GET_IDLE: + /* This function does not support multiple reports per interface*/ + /* Validate interfaceNumber and Report ID (should be 0) */ + if( (interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && + (CY_GET_REG8(USBFS_wValueLo) == 0u ) ) /* Do not support Idle per Report ID */ + { + USBFS_currentTD.count = 1u; + USBFS_currentTD.pData = &USBFS_hidIdleRate[interfaceNumber]; + requestHandled = USBFS_InitControlRead(); + } + break; + case USBFS_HID_GET_PROTOCOL: + /* Validate interfaceNumber */ + if( interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) + { + USBFS_currentTD.count = 1u; + USBFS_currentTD.pData = &USBFS_hidProtocol[interfaceNumber]; + requestHandled = USBFS_InitControlRead(); + } + break; + default: /* requestHandled is initialized as FALSE by default */ + break; + } + } + else if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == + USBFS_RQST_DIR_H2D) + { /* Control Write */ + switch (CY_GET_REG8(USBFS_bRequest)) + { + case USBFS_HID_SET_REPORT: + USBFS_FindReport(); + if (USBFS_currentTD.count != 0u) + { + requestHandled = USBFS_InitControlWrite(); + } + break; + case USBFS_HID_SET_IDLE: + /* This function does not support multiple reports per interface */ + /* Validate interfaceNumber and Report ID (should be 0) */ + if( (interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && + (CY_GET_REG8(USBFS_wValueLo) == 0u ) ) /* Do not support Idle per Report ID */ + { + USBFS_hidIdleRate[interfaceNumber] = CY_GET_REG8(USBFS_wValueHi); + /* With regards to HID spec: "7.2.4 Set_Idle Request" + * Latency. If the current period has gone past the + * newly proscribed time duration, then a report + * will be generated immediately. + */ + if(USBFS_hidIdleRate[interfaceNumber] < + USBFS_hidIdleTimer[interfaceNumber]) + { + /* Set the timer to zero and let the UpdateHIDTimer() API return IDLE_TIMER_EXPIRED status*/ + USBFS_hidIdleTimer[interfaceNumber] = 0u; + } + /* If the new request is received within 4 milliseconds + * (1 count) of the end of the current period, then the + * new request will have no effect until after the report. + */ + else if(USBFS_hidIdleTimer[interfaceNumber] <= 1u) + { + /* Do nothing. + * Let the UpdateHIDTimer() API continue to work and + * return IDLE_TIMER_EXPIRED status + */ + } + else + { /* Reload the timer*/ + USBFS_hidIdleTimer[interfaceNumber] = + USBFS_hidIdleRate[interfaceNumber]; + } + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + + case USBFS_HID_SET_PROTOCOL: + /* Validate interfaceNumber and protocol (must be 0 or 1) */ + if( (interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && + (CY_GET_REG8(USBFS_wValueLo) <= 1u) ) + { + USBFS_hidProtocol[interfaceNumber] = CY_GET_REG8(USBFS_wValueLo); + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + default: /* requestHandled is initialized as FALSE by default */ + break; + } + } + else + { /* requestHandled is initialized as FALSE by default */ + } + + return(requestHandled); +} + + +/******************************************************************************* +* Function Name: USB_FindHidClassDescriptor +******************************************************************************** +* +* Summary: +* This routine find Hid Class Descriptor pointer based on the Interface number +* and Alternate setting then loads the currentTD structure with the address of +* the buffer and the size. +* The HID Class Descriptor resides inside the config descriptor. +* +* Parameters: +* None. +* +* Return: +* currentTD +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_FindHidClassDecriptor(void) +{ + const T_USBFS_LUT CYCODE *pTmp; + volatile uint8 *pDescr; + uint8 interfaceN; + + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + interfaceN = CY_GET_REG8(USBFS_wIndexLo); + /* Third entry in the LUT starts the Interface Table pointers */ + /* Now use the request interface number*/ + pTmp = &pTmp[interfaceN + 2u]; + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE */ + pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + /* Now use Alternate setting number */ + pTmp = &pTmp[USBFS_interfaceSetting[interfaceN]]; + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_ALTERNATEi_HID_TABLE */ + pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + /* Fifth entry in the LUT points to Hid Class Descriptor in Configuration Descriptor */ + pTmp = &pTmp[4u]; + pDescr = (volatile uint8 *)pTmp->p_list; + /* The first byte contains the descriptor length */ + USBFS_currentTD.count = *pDescr; + USBFS_currentTD.pData = pDescr; +} + + +/******************************************************************************* +* Function Name: USB_FindReportDescriptor +******************************************************************************** +* +* Summary: +* This routine find Hid Report Descriptor pointer based on the Interface +* number, then loads the currentTD structure with the address of the buffer +* and the size. +* Hid Report Descriptor is located after IN/OUT/FEATURE reports. +* +* Parameters: +* void +* +* Return: +* currentTD +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_FindReportDescriptor(void) +{ + const T_USBFS_LUT CYCODE *pTmp; + volatile uint8 *pDescr; + uint8 interfaceN; + + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + interfaceN = CY_GET_REG8(USBFS_wIndexLo); + /* Third entry in the LUT starts the Interface Table pointers */ + /* Now use the request interface number */ + pTmp = &pTmp[interfaceN + 2u]; + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE */ + pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + /* Now use Alternate setting number */ + pTmp = &pTmp[USBFS_interfaceSetting[interfaceN]]; + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_ALTERNATEi_HID_TABLE */ + pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + /* Fourth entry in the LUT starts the Hid Report Descriptor */ + pTmp = &pTmp[3u]; + pDescr = (volatile uint8 *)pTmp->p_list; + /* The 1st and 2nd bytes of descriptor contain its length. LSB is 1st. */ + USBFS_currentTD.count = (((uint16)pDescr[1u] << 8u) | pDescr[0u]); + USBFS_currentTD.pData = &pDescr[2u]; +} + + +/******************************************************************************* +* Function Name: USBFS_FindReport +******************************************************************************** +* +* Summary: +* This routine sets up a transfer based on the Interface number, Report Type +* and Report ID, then loads the currentTD structure with the address of the +* buffer and the size. The caller has to decide if it is a control read or +* control write. +* +* Parameters: +* None. +* +* Return: +* currentTD +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_FindReport(void) +{ + const T_USBFS_LUT CYCODE *pTmp; + T_USBFS_TD *pTD; + uint8 interfaceN; + uint8 reportType; + + /* `#START HID_FINDREPORT` Place custom handling here */ + + /* `#END` */ + USBFS_currentTD.count = 0u; /* Init not supported condition */ + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + reportType = CY_GET_REG8(USBFS_wValueHi); + interfaceN = CY_GET_REG8(USBFS_wIndexLo); + /* Third entry in the LUT COnfiguration Table starts the Interface Table pointers */ + /* Now use the request interface number */ + pTmp = &pTmp[interfaceN + 2u]; + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE*/ + pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + if(interfaceN < USBFS_MAX_INTERFACES_NUMBER) + { + /* Now use Alternate setting number */ + pTmp = &pTmp[USBFS_interfaceSetting[interfaceN]]; + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_ALTERNATEi_HID_TABLE */ + pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + /* Validate reportType to comply with "7.2.1 Get_Report Request" */ + if((reportType >= USBFS_HID_GET_REPORT_INPUT) && + (reportType <= USBFS_HID_GET_REPORT_FEATURE)) + { + /* Get the entry proper TD (IN, OUT or Feature Report Table)*/ + pTmp = &pTmp[reportType - 1u]; + reportType = CY_GET_REG8(USBFS_wValueLo); /* Get reportID */ + /* Validate table support by the HID descriptor, compare table count with reportID */ + if(pTmp->c >= reportType) + { + pTD = (T_USBFS_TD *) pTmp->p_list; + pTD = &pTD[reportType]; /* select entry depend on report ID*/ + USBFS_currentTD.pData = pTD->pData; /* Buffer pointer */ + USBFS_currentTD.count = pTD->count; /* Buffer Size */ + USBFS_currentTD.pStatusBlock = pTD->pStatusBlock; + } + } + } +} + + +/******************************************************************************* +* Additional user functions supporting HID Requests +********************************************************************************/ + +/* `#START HID_FUNCTIONS` Place any additional functions here */ + +/* `#END` */ + +#endif /* End USBFS_ENABLE_HID_CLASS */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.h new file mode 100644 index 00000000..a34e4e73 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.h @@ -0,0 +1,64 @@ +/******************************************************************************* +* File Name: USBFS_hid.h +* Version 2.60 +* +* Description: +* Header File for the USFS component. Contains prototypes and constant values. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_USBFS_USBFS_hid_H) +#define CY_USBFS_USBFS_hid_H + +#include "cytypes.h" + + +/*************************************** +* Prototypes of the USBFS_hid API. +***************************************/ + +uint8 USBFS_UpdateHIDTimer(uint8 interface) ; +uint8 USBFS_GetProtocol(uint8 interface) ; + + +/*************************************** +*Renamed Functions for backward compatible +***************************************/ + +#define USBFS_bGetProtocol USBFS_GetProtocol + + +/*************************************** +* Constants for USBFS_hid API. +***************************************/ + +#define USBFS_PROTOCOL_BOOT (0x00u) +#define USBFS_PROTOCOL_REPORT (0x01u) + +/* Request Types (HID Chapter 7.2) */ +#define USBFS_HID_GET_REPORT (0x01u) +#define USBFS_HID_GET_IDLE (0x02u) +#define USBFS_HID_GET_PROTOCOL (0x03u) +#define USBFS_HID_SET_REPORT (0x09u) +#define USBFS_HID_SET_IDLE (0x0Au) +#define USBFS_HID_SET_PROTOCOL (0x0Bu) + +/* Descriptor Types (HID Chapter 7.1) */ +#define USBFS_DESCR_HID_CLASS (0x21u) +#define USBFS_DESCR_HID_REPORT (0x22u) +#define USBFS_DESCR_HID_PHYSICAL (0x23u) + +/* Report Request Types (HID Chapter 7.2.1) */ +#define USBFS_HID_GET_REPORT_INPUT (0x01u) +#define USBFS_HID_GET_REPORT_OUTPUT (0x02u) +#define USBFS_HID_GET_REPORT_FEATURE (0x03u) + +#endif /* End CY_USBFS_USBFS_hid_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.c b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.c new file mode 100644 index 00000000..0247caf2 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.c @@ -0,0 +1,1341 @@ +/******************************************************************************* +* File Name: USBFS_midi.c +* Version 2.60 +* +* Description: +* MIDI Streaming request handler. +* This file contains routines for sending and receiving MIDI +* messages, and handles running status in both directions. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS.h" + +#if defined(USBFS_ENABLE_MIDI_STREAMING) + +#include "USBFS_midi.h" +#include "USBFS_pvt.h" + + +/*************************************** +* MIDI Constants +***************************************/ + +#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + /* The Size of the MIDI messages (MIDI Table 4-1) */ + static const uint8 CYCODE USBFS_MIDI_SIZE[] = { + /* Miscellaneous function codes(Reserved) */ 0x03u, + /* Cable events (Reserved) */ 0x03u, + /* Two-byte System Common messages */ 0x02u, + /* Three-byte System Common messages */ 0x03u, + /* SysEx starts or continues */ 0x03u, + /* Single-byte System Common Message or + SysEx ends with following single byte */ 0x01u, + /* SysEx ends with following two bytes */ 0x02u, + /* SysEx ends with following three bytes */ 0x03u, + /* Note-off */ 0x03u, + /* Note-on */ 0x03u, + /* Poly-KeyPress */ 0x03u, + /* Control Change */ 0x03u, + /* Program Change */ 0x02u, + /* Channel Pressure */ 0x02u, + /* PitchBend Change */ 0x03u, + /* Single Byte */ 0x01u + }; +#endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ + + + +/*************************************** +* Global variables +***************************************/ + +#if (USBFS_MIDI_IN_BUFF_SIZE > 0) + #if (USBFS_MIDI_IN_BUFF_SIZE >= 256) + volatile uint16 USBFS_midiInPointer; /* Input endpoint buffer pointer */ + #else + volatile uint8 USBFS_midiInPointer; /* Input endpoint buffer pointer */ + #endif /* End USBFS_MIDI_IN_BUFF_SIZE >=256 */ + volatile uint8 USBFS_midi_in_ep; /* Input endpoint number */ + uint8 USBFS_midiInBuffer[USBFS_MIDI_IN_BUFF_SIZE]; /* Input endpoint buffer */ +#endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */ + +#if (USBFS_MIDI_OUT_BUFF_SIZE > 0) + volatile uint8 USBFS_midi_out_ep; /* Output endpoint number */ + uint8 USBFS_midiOutBuffer[USBFS_MIDI_OUT_BUFF_SIZE]; /* Output endpoint buffer */ +#endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */ + +#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + static USBFS_MIDI_RX_STATUS USBFS_MIDI1_Event; /* MIDI RX status structure */ + static volatile uint8 USBFS_MIDI1_TxRunStat; /* MIDI Output running status */ + volatile uint8 USBFS_MIDI1_InqFlags; /* Device inquiry flag */ + + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + static USBFS_MIDI_RX_STATUS USBFS_MIDI2_Event; /* MIDI RX status structure */ + static volatile uint8 USBFS_MIDI2_TxRunStat; /* MIDI Output running status */ + volatile uint8 USBFS_MIDI2_InqFlags; /* Device inquiry flag */ + #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ +#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ + + +/*************************************** +* Custom Declarations +***************************************/ + +/* `#START MIDI_CUSTOM_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +/*************************************** +* Optional MIDI APIs +***************************************/ +#if (USBFS_ENABLE_MIDI_API != 0u) + + +/******************************************************************************* +* Function Name: USBFS_MIDI_EP_Init +******************************************************************************** +* +* Summary: +* This function initializes the MIDI interface and UART(s) to be ready to +* receive data from the PC and MIDI ports. +* +* Parameters: +* None +* +* Return: +* None +* +* Global variables: +* USBFS_midiInBuffer: This buffer is used for saving and combining +* the received data from UART(s) and(or) generated internally by +* PutUsbMidiIn() function messages. USBFS_MIDI_IN_EP_Service() +* function transfers the data from this buffer to the PC. +* USBFS_midiOutBuffer: This buffer is used by the +* USBFS_MIDI_OUT_EP_Service() function for saving the received +* from the PC data, then the data are parsed and transferred to UART(s) +* buffer and to the internal processing by the +* USBFS_callbackLocalMidiEvent function. +* USBFS_midi_out_ep: Used as an OUT endpoint number. +* USBFS_midi_in_ep: Used as an IN endpoint number. +* USBFS_midiInPointer: Initialized to zero. +* +* Reentrant: +* No +* +*******************************************************************************/ +void USBFS_MIDI_EP_Init(void) +{ + #if (USBFS_MIDI_IN_BUFF_SIZE > 0) + USBFS_midiInPointer = 0u; + #endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */ + + #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + #if (USBFS_MIDI_IN_BUFF_SIZE > 0) + /* Init DMA configurations for IN EP*/ + USBFS_LoadInEP(USBFS_midi_in_ep, USBFS_midiInBuffer, + USBFS_MIDI_IN_BUFF_SIZE); + + #endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */ + #if (USBFS_MIDI_OUT_BUFF_SIZE > 0) + /* Init DMA configurations for OUT EP*/ + (void)USBFS_ReadOutEP(USBFS_midi_out_ep, USBFS_midiOutBuffer, + USBFS_MIDI_OUT_BUFF_SIZE); + #endif /*USBFS_MIDI_OUT_BUFF_SIZE > 0 */ + #endif /* End USBFS__EP_DMAAUTO */ + + #if (USBFS_MIDI_OUT_BUFF_SIZE > 0) + USBFS_EnableOutEP(USBFS_midi_out_ep); + #endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */ + + /* Initialize the MIDI port(s) */ + #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + USBFS_MIDI_Init(); + #endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ +} + +#if (USBFS_MIDI_OUT_BUFF_SIZE > 0) + + + /******************************************************************************* + * Function Name: USBFS_MIDI_OUT_EP_Service + ******************************************************************************** + * + * Summary: + * Services the USB MIDI OUT endpoints. + * This function is called from OUT EP ISR. It transfers the received from PC + * data to the external MIDI port(UART TX buffer) and calls the + * USBFS_callbackLocalMidiEvent() function to internal process + * of the MIDI data. + * This function is blocked by UART, if not enough space is available in UART + * TX buffer. Therefore it is recommended to use large UART TX buffer size. + * + * Parameters: + * None + * + * Return: + * None + * + * Global variables: + * USBFS_midiOutBuffer: Used as temporary buffer between USB internal + * memory and UART TX buffer. + * USBFS_midi_out_ep: Used as an OUT endpoint number. + * + * Reentrant: + * No + * + *******************************************************************************/ + void USBFS_MIDI_OUT_EP_Service(void) + { + #if USBFS_MIDI_OUT_BUFF_SIZE >= 256 + uint16 outLength; + uint16 outPointer; + #else + uint8 outLength; + uint8 outPointer; + #endif /* End USBFS_MIDI_OUT_BUFF_SIZE >=256 */ + + uint8 dmaState = 0u; + + /* Service the USB MIDI output endpoint */ + if (USBFS_GetEPState(USBFS_midi_out_ep) == USBFS_OUT_BUFFER_FULL) + { + #if USBFS_MIDI_OUT_BUFF_SIZE >= 256 + outLength = USBFS_GetEPCount(USBFS_midi_out_ep); + #else + outLength = (uint8)USBFS_GetEPCount(USBFS_midi_out_ep); + #endif /* End USBFS_MIDI_OUT_BUFF_SIZE >= 256 */ + #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) + #if USBFS_MIDI_OUT_BUFF_SIZE >= 256 + outLength = USBFS_ReadOutEP(USBFS_midi_out_ep, + USBFS_midiOutBuffer, outLength); + #else + outLength = (uint8)USBFS_ReadOutEP(USBFS_midi_out_ep, + USBFS_midiOutBuffer, (uint16)outLength); + #endif /* End USBFS_MIDI_OUT_BUFF_SIZE >= 256 */ + #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL) + do /* wait for DMA transfer complete */ + { + (void)CyDmaChStatus(USBFS_DmaChan[USBFS_midi_out_ep], NULL, &dmaState); + }while((dmaState & (STATUS_TD_ACTIVE | STATUS_CHAIN_ACTIVE)) != 0u); + #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */ + #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */ + if(dmaState != 0u) + { + /* Suppress compiler warning */ + } + if (outLength >= USBFS_EVENT_LENGTH) + { + outPointer = 0u; + while (outPointer < outLength) + { + /* In some OS OUT packet could be appended by nulls which could be skipped */ + if (USBFS_midiOutBuffer[outPointer] == 0u) + { + break; + } + /* Route USB MIDI to the External connection */ + #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + if ((USBFS_midiOutBuffer[outPointer] & USBFS_CABLE_MASK) == + USBFS_MIDI_CABLE_00) + { + USBFS_MIDI1_ProcessUsbOut(&USBFS_midiOutBuffer[outPointer]); + } + else if ((USBFS_midiOutBuffer[outPointer] & USBFS_CABLE_MASK) == + USBFS_MIDI_CABLE_01) + { + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + USBFS_MIDI2_ProcessUsbOut(&USBFS_midiOutBuffer[outPointer]); + #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ + } + else + { + /* `#START CUSTOM_MIDI_OUT_EP_SERV` Place your code here */ + + /* `#END` */ + } + #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ + + /* Process any local MIDI output functions */ + USBFS_callbackLocalMidiEvent( + USBFS_midiOutBuffer[outPointer] & USBFS_CABLE_MASK, + &USBFS_midiOutBuffer[outPointer + USBFS_EVENT_BYTE1]); + outPointer += USBFS_EVENT_LENGTH; + } + } + #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + /* Enable Out EP*/ + USBFS_EnableOutEP(USBFS_midi_out_ep); + #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ + } + } + +#endif /* #if (USBFS_MIDI_OUT_BUFF_SIZE > 0) */ + +#if (USBFS_MIDI_IN_BUFF_SIZE > 0) + + + /******************************************************************************* + * Function Name: USBFS_MIDI_IN_EP_Service + ******************************************************************************** + * + * Summary: + * Services the USB MIDI IN endpoint. Non-blocking. + * Checks that previous packet was processed by HOST, otherwise service the + * input endpoint on the subsequent call. It is called from the + * USBFS_MIDI_IN_Service() and from the + * USBFS_PutUsbMidiIn() function. + * + * Parameters: + * None + * + * Return: + * None + * + * Global variables: + * USBFS_midi_in_ep: Used as an IN endpoint number. + * USBFS_midiInBuffer: Function loads the data from this buffer to + * the USB IN endpoint. + * USBFS_midiInPointer: Cleared to zero when data are sent. + * + * Reentrant: + * No + * + *******************************************************************************/ + void USBFS_MIDI_IN_EP_Service(void) + { + /* Service the USB MIDI input endpoint */ + /* Check that previous packet was processed by HOST, otherwise service the USB later */ + if (USBFS_midiInPointer != 0u) + { + if(USBFS_GetEPState(USBFS_midi_in_ep) == USBFS_EVENT_PENDING) + { + #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) + USBFS_LoadInEP(USBFS_midi_in_ep, USBFS_midiInBuffer, + (uint16)USBFS_midiInPointer); + #else /* USBFS_EP_MM != USBFS__EP_DMAAUTO */ + /* rearm IN EP */ + USBFS_LoadInEP(USBFS_midi_in_ep, NULL, (uint16)USBFS_midiInPointer); + #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO*/ + + /* Clear the midiInPointer. For DMA mode, clear this pointer in the ARB ISR when data are moved by DMA */ + #if(USBFS_EP_MM == USBFS__EP_MANUAL) + USBFS_midiInPointer = 0u; + #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */ + } + } + } + + + /******************************************************************************* + * Function Name: USBFS_MIDI_IN_Service + ******************************************************************************** + * + * Summary: + * Services the traffic from the MIDI input ports (RX UART) and prepare data + * in USB MIDI IN endpoint buffer. + * Calls the USBFS_MIDI_IN_EP_Service() function to sent the + * data from buffer to PC. Non-blocking. Should be called from main foreground + * task. + * This function is not protected from the reentrant calls. When it is required + * to use this function in UART RX ISR to guaranty low latency, care should be + * taken to protect from reentrant calls. + * + * Parameters: + * None + * + * Return: + * None + * + * Global variables: + * USBFS_midiInPointer: Cleared to zero when data are sent. + * + * Reentrant: + * No + * + *******************************************************************************/ + void USBFS_MIDI_IN_Service(void) + { + /* Service the MIDI UART inputs until either both receivers have no more + * events or until the input endpoint buffer fills up. + */ + #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + uint8 m1 = 0u; + uint8 m2 = 0u; + do + { + if (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH)) + { + /* Check MIDI1 input port for a complete event */ + m1 = USBFS_MIDI1_GetEvent(); + if (m1 != 0u) + { + USBFS_PrepareInBuffer(m1, (uint8 *)&USBFS_MIDI1_Event.msgBuff[0], + USBFS_MIDI1_Event.size, USBFS_MIDI_CABLE_00); + } + } + + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + if (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH)) + { + /* Check MIDI2 input port for a complete event */ + m2 = USBFS_MIDI2_GetEvent(); + if (m2 != 0u) + { + USBFS_PrepareInBuffer(m2, (uint8 *)&USBFS_MIDI2_Event.msgBuff[0], + USBFS_MIDI2_Event.size, USBFS_MIDI_CABLE_01); + } + } + #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ + + }while( (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH)) + && ((m1 != 0u) || (m2 != 0u)) ); + #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ + + /* Service the USB MIDI input endpoint */ + USBFS_MIDI_IN_EP_Service(); + } + + + /******************************************************************************* + * Function Name: USBFS_PutUsbMidiIn + ******************************************************************************** + * + * Summary: + * Puts one MIDI messages into the USB MIDI In endpoint buffer. These are + * MIDI input messages to the host. This function is only used if the device + * has internal MIDI input functionality. USBMIDI_MIDI_IN_Service() function + * should additionally be called to send the message from local buffer to + * IN endpoint. + * + * Parameters: + * ic: 0 = No message (should never happen) + * 1 - 3 = Complete MIDI message in midiMsg + * 3 - IN EP LENGTH = Complete SySEx message(without EOSEX byte) in + * midiMsg. The length is limited by the max BULK EP size(64) + * MIDI_SYSEX = Start or continuation of SysEx message + * (put event bytes in midiMsg buffer) + * MIDI_EOSEX = End of SysEx message + * (put event bytes in midiMsg buffer) + * MIDI_TUNEREQ = Tune Request message (single byte system common msg) + * 0xf8 - 0xff = Single byte real-time message + * midiMsg: pointer to MIDI message. + * cable: cable number. + * + * Return: + * USBFS_TRUE if error. + * USBFS_FALSE if success. + * + * Global variables: + * USBFS_midi_in_ep: MIDI IN endpoint number used for sending data. + * USBFS_midiInPointer: Checked this variable to see if there is + * enough free space in the IN endpoint buffer. If buffer is full, initiate + * sending to PC. + * + * Reentrant: + * No + * + *******************************************************************************/ + uint8 USBFS_PutUsbMidiIn(uint8 ic, const uint8 midiMsg[], uint8 cable) + + { + uint8 retError = USBFS_FALSE; + uint8 msgIndex; + + /* Protect PrepareInBuffer() function from concurrent calls */ + #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + MIDI1_UART_DisableRxInt(); + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + MIDI2_UART_DisableRxInt(); + #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ + #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ + + if (USBFS_midiInPointer > + (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH)) + { + USBFS_MIDI_IN_EP_Service(); + } + if (USBFS_midiInPointer <= + (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH)) + { + if((ic < USBFS_EVENT_LENGTH) || (ic >= USBFS_MIDI_STATUS_MASK)) + { + USBFS_PrepareInBuffer(ic, midiMsg, ic, cable); + } + else + { /* Only SysEx message is greater than 4 bytes */ + msgIndex = 0u; + do + { + USBFS_PrepareInBuffer(USBFS_MIDI_SYSEX, &midiMsg[msgIndex], + USBFS_EVENT_BYTE3, cable); + ic -= USBFS_EVENT_BYTE3; + msgIndex += USBFS_EVENT_BYTE3; + if (USBFS_midiInPointer > + (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH)) + { + USBFS_MIDI_IN_EP_Service(); + if (USBFS_midiInPointer > + (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH)) + { + /* Error condition. HOST is not ready to receive this packet. */ + retError = USBFS_TRUE; + break; + } + } + }while(ic > USBFS_EVENT_BYTE3); + + if(retError == USBFS_FALSE) + { + USBFS_PrepareInBuffer(USBFS_MIDI_EOSEX, midiMsg, ic, cable); + } + } + } + else + { + /* Error condition. HOST is not ready to receive this packet. */ + retError = USBFS_TRUE; + } + + #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + MIDI1_UART_EnableRxInt(); + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + MIDI2_UART_EnableRxInt(); + #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ + #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ + + return (retError); + } + + + /******************************************************************************* + * Function Name: USBFS_PrepareInBuffer + ******************************************************************************** + * + * Summary: + * Builds a USB MIDI event in the input endpoint buffer at the current pointer. + * Puts one MIDI message into the USB MIDI In endpoint buffer. + * + * Parameters: + * ic: 0 = No message (should never happen) + * 1 - 3 = Complete MIDI message at pMdat[0] + * MIDI_SYSEX = Start or continuation of SysEx message + * (put eventLen bytes in buffer) + * MIDI_EOSEX = End of SysEx message + * (put eventLen bytes in buffer, + * and append MIDI_EOSEX) + * MIDI_TUNEREQ = Tune Request message (single byte system common msg) + * 0xf8 - 0xff = Single byte real-time message + * + * srcBuff: pointer to MIDI data + * eventLen: number of bytes in MIDI event + * cable: MIDI source port number + * + * Return: + * None + * + * Global variables: + * USBFS_midiInBuffer: This buffer is used for saving and combine the + * received from UART(s) and(or) generated internally by + * USBFS_PutUsbMidiIn() function messages. + * USBFS_midiInPointer: Used as an index for midiInBuffer to + * write data. + * + * Reentrant: + * No + * + *******************************************************************************/ + void USBFS_PrepareInBuffer(uint8 ic, const uint8 srcBuff[], uint8 eventLen, uint8 cable) + + { + uint8 srcBuffZero; + uint8 srcBuffOne; + + srcBuffZero = srcBuff[0u]; + srcBuffOne = srcBuff[1u]; + + if (ic >= (USBFS_MIDI_STATUS_MASK | USBFS_MIDI_SINGLE_BYTE_MASK)) + { + USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_SINGLE_BYTE | cable; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = ic; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = 0u; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = 0u; + USBFS_midiInPointer++; + } + else if((ic < USBFS_EVENT_LENGTH) || (ic == USBFS_MIDI_SYSEX)) + { + if(ic == USBFS_MIDI_SYSEX) + { + USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_SYSEX | cable; + USBFS_midiInPointer++; + } + else if (srcBuffZero < USBFS_MIDI_SYSEX) + { + USBFS_midiInBuffer[USBFS_midiInPointer] = (srcBuffZero >> 4u) | cable; + USBFS_midiInPointer++; + } + else if (srcBuffZero == USBFS_MIDI_TUNEREQ) + { + USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_1BYTE_COMMON | cable; + USBFS_midiInPointer++; + } + else if ((srcBuffZero == USBFS_MIDI_QFM) || (srcBuffZero == USBFS_MIDI_SONGSEL)) + { + USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_2BYTE_COMMON | cable; + USBFS_midiInPointer++; + } + else if (srcBuffZero == USBFS_MIDI_SPP) + { + USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_3BYTE_COMMON | cable; + USBFS_midiInPointer++; + } + else + { + } + + USBFS_midiInBuffer[USBFS_midiInPointer] = srcBuffZero; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = srcBuffOne; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = srcBuff[2u]; + USBFS_midiInPointer++; + } + else if (ic == USBFS_MIDI_EOSEX) + { + switch (eventLen) + { + case 0u: + USBFS_midiInBuffer[USBFS_midiInPointer] = + USBFS_SYSEX_ENDS_WITH1 | cable; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_MIDI_EOSEX; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = 0u; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = 0u; + USBFS_midiInPointer++; + break; + case 1u: + USBFS_midiInBuffer[USBFS_midiInPointer] = + USBFS_SYSEX_ENDS_WITH2 | cable; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = srcBuffZero; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_MIDI_EOSEX; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = 0u; + USBFS_midiInPointer++; + break; + case 2u: + USBFS_midiInBuffer[USBFS_midiInPointer] = + USBFS_SYSEX_ENDS_WITH3 | cable; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = srcBuffZero; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = srcBuffOne; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_MIDI_EOSEX; + USBFS_midiInPointer++; + break; + default: + break; + } + } + else + { + } + } + +#endif /* #if (USBFS_MIDI_IN_BUFF_SIZE > 0) */ + + +/* The implementation for external serial input and output connections +* to route USB MIDI data to and from those connections. +*/ +#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + + + /******************************************************************************* + * Function Name: USBFS_MIDI_Init + ******************************************************************************** + * + * Summary: + * Initializes MIDI variables and starts the UART(s) hardware block(s). + * + * Parameters: + * None + * + * Return: + * None + * + * Side Effects: + * Change the priority of the UART(s) TX interrupts to be higher than the + * default EP ISR priority. + * + * Global variables: + * USBFS_MIDI_Event: initialized to zero. + * USBFS_MIDI_TxRunStat: initialized to zero. + * + *******************************************************************************/ + void USBFS_MIDI_Init(void) + { + USBFS_MIDI1_Event.length = 0u; + USBFS_MIDI1_Event.count = 0u; + USBFS_MIDI1_Event.size = 0u; + USBFS_MIDI1_Event.runstat = 0u; + USBFS_MIDI1_TxRunStat = 0u; + USBFS_MIDI1_InqFlags = 0u; + /* Start UART block */ + MIDI1_UART_Start(); + /* Change the priority of the UART TX and RX interrupt */ + CyIntSetPriority(MIDI1_UART_TX_VECT_NUM, USBFS_CUSTOM_UART_TX_PRIOR_NUM); + CyIntSetPriority(MIDI1_UART_RX_VECT_NUM, USBFS_CUSTOM_UART_RX_PRIOR_NUM); + + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + USBFS_MIDI2_Event.length = 0u; + USBFS_MIDI2_Event.count = 0u; + USBFS_MIDI2_Event.size = 0u; + USBFS_MIDI2_Event.runstat = 0u; + USBFS_MIDI2_TxRunStat = 0u; + USBFS_MIDI2_InqFlags = 0u; + /* Start second UART block */ + MIDI2_UART_Start(); + /* Change the priority of the UART TX interrupt */ + CyIntSetPriority(MIDI2_UART_TX_VECT_NUM, USBFS_CUSTOM_UART_TX_PRIOR_NUM); + CyIntSetPriority(MIDI2_UART_RX_VECT_NUM, USBFS_CUSTOM_UART_RX_PRIOR_NUM); + #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF*/ + + /* `#START MIDI_INIT_CUSTOM` Init other extended UARTs here */ + + /* `#END` */ + + } + + + /******************************************************************************* + * Function Name: USBFS_ProcessMidiIn + ******************************************************************************** + * + * Summary: + * Processes one byte of incoming MIDI data. + * + * Parameters: + * mData = current MIDI input data byte + * *rxStat = pointer to a MIDI_RX_STATUS structure + * + * Return: + * 0, if no complete message + * 1 - 4, if message complete + * MIDI_SYSEX, if start or continuation of system exclusive + * MIDI_EOSEX, if end of system exclusive + * 0xf8 - 0xff, if single byte real time message + * + *******************************************************************************/ + uint8 USBFS_ProcessMidiIn(uint8 mData, USBFS_MIDI_RX_STATUS *rxStat) + + { + uint8 midiReturn = 0u; + + /* Check for a MIDI status byte. All status bytes, except real time messages, + * which are a single byte, force the start of a new buffer cycle. + */ + if ((mData & USBFS_MIDI_STATUS_BYTE_MASK) != 0u) + { + if ((mData & USBFS_MIDI_STATUS_MASK) == USBFS_MIDI_STATUS_MASK) + { + if ((mData & USBFS_MIDI_SINGLE_BYTE_MASK) != 0u) /* System Real-Time Messages(single byte) */ + { + midiReturn = mData; + } + else /* System Common Messages */ + { + switch (mData) + { + case USBFS_MIDI_SYSEX: + rxStat->msgBuff[0u] = USBFS_MIDI_SYSEX; + rxStat->runstat = USBFS_MIDI_SYSEX; + rxStat->count = 1u; + rxStat->length = 3u; + break; + case USBFS_MIDI_EOSEX: + rxStat->runstat = 0u; + rxStat->size = rxStat->count; + rxStat->count = 0u; + midiReturn = USBFS_MIDI_EOSEX; + break; + case USBFS_MIDI_SPP: + rxStat->msgBuff[0u] = USBFS_MIDI_SPP; + rxStat->runstat = 0u; + rxStat->count = 1u; + rxStat->length = 3u; + break; + case USBFS_MIDI_SONGSEL: + rxStat->msgBuff[0u] = USBFS_MIDI_SONGSEL; + rxStat->runstat = 0u; + rxStat->count = 1u; + rxStat->length = 2u; + break; + case USBFS_MIDI_QFM: + rxStat->msgBuff[0u] = USBFS_MIDI_QFM; + rxStat->runstat = 0u; + rxStat->count = 1u; + rxStat->length = 2u; + break; + case USBFS_MIDI_TUNEREQ: + rxStat->msgBuff[0u] = USBFS_MIDI_TUNEREQ; + rxStat->runstat = 0u; + rxStat->size = 1u; + rxStat->count = 0u; + midiReturn = rxStat->size; + break; + default: + break; + } + } + } + else /* Channel Messages */ + { + rxStat->msgBuff[0u] = mData; + rxStat->runstat = mData; + rxStat->count = 1u; + switch (mData & USBFS_MIDI_STATUS_MASK) + { + case USBFS_MIDI_NOTE_OFF: + case USBFS_MIDI_NOTE_ON: + case USBFS_MIDI_POLY_KEY_PRESSURE: + case USBFS_MIDI_CONTROL_CHANGE: + case USBFS_MIDI_PITCH_BEND_CHANGE: + rxStat->length = 3u; + break; + case USBFS_MIDI_PROGRAM_CHANGE: + case USBFS_MIDI_CHANNEL_PRESSURE: + rxStat->length = 2u; + break; + default: + rxStat->runstat = 0u; + rxStat->count = 0u; + break; + } + } + } + + /* Otherwise, it's a data byte */ + else + { + if (rxStat->runstat == USBFS_MIDI_SYSEX) + { + rxStat->msgBuff[rxStat->count] = mData; + rxStat->count++; + if (rxStat->count >= rxStat->length) + { + rxStat->size = rxStat->count; + rxStat->count = 0u; + midiReturn = USBFS_MIDI_SYSEX; + } + } + else if (rxStat->count > 0u) + { + rxStat->msgBuff[rxStat->count] = mData; + rxStat->count++; + if (rxStat->count >= rxStat->length) + { + rxStat->size = rxStat->count; + rxStat->count = 0u; + midiReturn = rxStat->size; + } + } + else if (rxStat->runstat != 0u) + { + rxStat->msgBuff[0u] = rxStat->runstat; + rxStat->msgBuff[1u] = mData; + rxStat->count = 2u; + switch (rxStat->runstat & USBFS_MIDI_STATUS_MASK) + { + case USBFS_MIDI_NOTE_OFF: + case USBFS_MIDI_NOTE_ON: + case USBFS_MIDI_POLY_KEY_PRESSURE: + case USBFS_MIDI_CONTROL_CHANGE: + case USBFS_MIDI_PITCH_BEND_CHANGE: + rxStat->length = 3u; + break; + case USBFS_MIDI_PROGRAM_CHANGE: + case USBFS_MIDI_CHANNEL_PRESSURE: + rxStat->size =rxStat->count; + rxStat->count = 0u; + midiReturn = rxStat->size; + break; + default: + rxStat->count = 0u; + break; + } + } + else + { + } + } + return (midiReturn); + } + + + /******************************************************************************* + * Function Name: USBFS_MIDI1_GetEvent + ******************************************************************************** + * + * Summary: + * Checks for incoming MIDI data, calls the MIDI event builder if so. + * Returns either empty or with a complete event. + * + * Parameters: + * None + * + * Return: + * 0, if no complete message + * 1 - 4, if message complete + * MIDI_SYSEX, if start or continuation of system exclusive + * MIDI_EOSEX, if end of system exclusive + * 0xf8 - 0xff, if single byte real time message + * + * Global variables: + * USBFS_MIDI1_Event: RX status structure used to parse received + * data. + * + *******************************************************************************/ + uint8 USBFS_MIDI1_GetEvent(void) + { + uint8 msgRtn = 0u; + uint8 rxData; + #if (MIDI1_UART_RXBUFFERSIZE >= 256u) + uint16 rxBufferRead; + #if CY_PSOC3 /* This local variable is required only for PSOC3 and large buffer */ + uint16 rxBufferWrite; + #endif /* end CY_PSOC3 */ + #else + uint8 rxBufferRead; + #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */ + uint8 rxBufferLoopDetect; + /* Read buffer loop condition to the local variable */ + rxBufferLoopDetect = MIDI1_UART_rxBufferLoopDetect; + + if ( (MIDI1_UART_rxBufferRead != MIDI1_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u) ) + { + /* Protect variables that could change on interrupt by disabling Rx interrupt.*/ + #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntDisable(MIDI1_UART_RX_VECT_NUM); + #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */ + rxBufferRead = MIDI1_UART_rxBufferRead; + #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + rxBufferWrite = MIDI1_UART_rxBufferWrite; + CyIntEnable(MIDI1_UART_RX_VECT_NUM); + #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */ + + /* Stay here until either the buffer is empty or we have a complete message + * in the message buffer. Note that we must use a temporary buffer pointer + * since it takes two instructions to increment with a wrap, and we can't + * risk doing that with the real pointer and getting an interrupt in between + * instructions. + */ + + #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + while ( ((rxBufferRead != rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) ) + #else + while ( ((rxBufferRead != MIDI1_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) ) + #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 && CY_PSOC3 */ + { + rxData = MIDI1_UART_rxBuffer[rxBufferRead]; + /* Increment pointer with a wrap */ + rxBufferRead++; + if(rxBufferRead >= MIDI1_UART_RXBUFFERSIZE) + { + rxBufferRead = 0u; + } + /* If loop condition was set - update real read buffer pointer + * to avoid overflow status + */ + if(rxBufferLoopDetect != 0u ) + { + MIDI1_UART_rxBufferLoopDetect = 0u; + #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntDisable(MIDI1_UART_RX_VECT_NUM); + #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */ + MIDI1_UART_rxBufferRead = rxBufferRead; + #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntEnable(MIDI1_UART_RX_VECT_NUM); + #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */ + } + + msgRtn = USBFS_ProcessMidiIn(rxData, + (USBFS_MIDI_RX_STATUS *)&USBFS_MIDI1_Event); + + /* Read buffer loop condition to the local variable */ + rxBufferLoopDetect = MIDI1_UART_rxBufferLoopDetect; + } + + /* Finally, update the real output pointer, then return with + * an indication as to whether there's a complete message in the buffer. + */ + #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntDisable(MIDI1_UART_RX_VECT_NUM); + #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */ + MIDI1_UART_rxBufferRead = rxBufferRead; + #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntEnable(MIDI1_UART_RX_VECT_NUM); + #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */ + } + + return (msgRtn); + } + + + /******************************************************************************* + * Function Name: USBFS_MIDI1_ProcessUsbOut + ******************************************************************************** + * + * Summary: + * Process a USB MIDI output event. + * Puts data into the MIDI TX output buffer. + * + * Parameters: + * *epBuf: pointer on MIDI event. + * + * Return: + * None + * + * Global variables: + * USBFS_MIDI1_TxRunStat: This variable used to save the MIDI + * status byte and skip to send the repeated status byte in subsequent event. + * USBFS_MIDI1_InqFlags: The following flags are set when SysEx + * message comes. + * USBFS_INQ_SYSEX_FLAG: Non-Real Time SySEx message received. + * USBFS_INQ_IDENTITY_REQ_FLAG: Identity Request received. + * This bit should be cleared by user when Identity Reply message generated. + * + *******************************************************************************/ + void USBFS_MIDI1_ProcessUsbOut(const uint8 epBuf[]) + + { + uint8 cmd; + uint8 len; + uint8 i; + + /* User code is required at the beginning of the procedure */ + /* `#START MIDI1_PROCESS_OUT_BEGIN` */ + + /* `#END` */ + + cmd = epBuf[USBFS_EVENT_BYTE0] & USBFS_CIN_MASK; + if((cmd != USBFS_RESERVED0) && (cmd != USBFS_RESERVED1)) + { + len = USBFS_MIDI_SIZE[cmd]; + i = USBFS_EVENT_BYTE1; + /* Universal System Exclusive message parsing */ + if(cmd == USBFS_SYSEX) + { + if((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX) && + (epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_NON_REAL_TIME)) + { /* Non-Real Time SySEx starts */ + USBFS_MIDI1_InqFlags |= USBFS_INQ_SYSEX_FLAG; + } + else + { + USBFS_MIDI1_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; + } + } + else if(cmd == USBFS_SYSEX_ENDS_WITH1) + { + USBFS_MIDI1_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; + } + else if(cmd == USBFS_SYSEX_ENDS_WITH2) + { + USBFS_MIDI1_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; + } + else if(cmd == USBFS_SYSEX_ENDS_WITH3) + { + /* Identify Request support */ + if((USBFS_MIDI1_InqFlags & USBFS_INQ_SYSEX_FLAG) != 0u) + { + USBFS_MIDI1_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; + if((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX_GEN_INFORMATION) && + (epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_IDENTITY_REQ)) + { /* Set the flag about received the Identity Request. + * The Identity Reply message may be send by user code. + */ + USBFS_MIDI1_InqFlags |= USBFS_INQ_IDENTITY_REQ_FLAG; + } + } + } + else /* Do nothing for other command */ + { + } + /* Running Status for Voice and Mode messages only. */ + if((cmd >= USBFS_NOTE_OFF) && ( cmd <= USBFS_PITCH_BEND_CHANGE)) + { + if(USBFS_MIDI1_TxRunStat == epBuf[USBFS_EVENT_BYTE1]) + { /* Skip the repeated Status byte */ + i++; + } + else + { /* Save Status byte for next event */ + USBFS_MIDI1_TxRunStat = epBuf[USBFS_EVENT_BYTE1]; + } + } + else + { /* Clear Running Status */ + USBFS_MIDI1_TxRunStat = 0u; + } + /* Puts data into the MIDI TX output buffer.*/ + do + { + MIDI1_UART_PutChar(epBuf[i]); + i++; + } while (i <= len); + } + + /* User code is required at the end of the procedure */ + /* `#START MIDI1_PROCESS_OUT_END` */ + + /* `#END` */ + } + +#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + + + /******************************************************************************* + * Function Name: USBFS_MIDI2_GetEvent + ******************************************************************************** + * + * Summary: + * Checks for incoming MIDI data, calls the MIDI event builder if so. + * Returns either empty or with a complete event. + * + * Parameters: + * None + * + * Return: + * 0, if no complete message + * 1 - 4, if message complete + * MIDI_SYSEX, if start or continuation of system exclusive + * MIDI_EOSEX, if end of system exclusive + * 0xf8 - 0xff, if single byte real time message + * + * Global variables: + * USBFS_MIDI2_Event: RX status structure used to parse received + * data. + * + *******************************************************************************/ + uint8 USBFS_MIDI2_GetEvent(void) + { + uint8 msgRtn = 0u; + uint8 rxData; + #if (MIDI2_UART_RXBUFFERSIZE >= 256u) + uint16 rxBufferRead; + #if CY_PSOC3 /* This local variable required only for PSOC3 and large buffer */ + uint16 rxBufferWrite; + #endif /* end CY_PSOC3 */ + #else + uint8 rxBufferRead; + #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */ + uint8 rxBufferLoopDetect; + /* Read buffer loop condition to the local variable */ + rxBufferLoopDetect = MIDI2_UART_rxBufferLoopDetect; + + if ( (MIDI2_UART_rxBufferRead != MIDI2_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u) ) + { + /* Protect variables that could change on interrupt by disabling Rx interrupt.*/ + #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntDisable(MIDI2_UART_RX_VECT_NUM); + #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */ + rxBufferRead = MIDI2_UART_rxBufferRead; + #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + rxBufferWrite = MIDI2_UART_rxBufferWrite; + CyIntEnable(MIDI2_UART_RX_VECT_NUM); + #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */ + + /* Stay here until either the buffer is empty or we have a complete message + * in the message buffer. Note that we must use a temporary output pointer to + * since it takes two instructions to increment with a wrap, and we can't + * risk doing that with the real pointer and getting an interrupt in between + * instructions. + */ + + #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + while ( ((rxBufferRead != rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) ) + #else + while ( ((rxBufferRead != MIDI2_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) ) + #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 && CY_PSOC3 */ + { + rxData = MIDI2_UART_rxBuffer[rxBufferRead]; + rxBufferRead++; + if(rxBufferRead >= MIDI2_UART_RXBUFFERSIZE) + { + rxBufferRead = 0u; + } + /* If loop condition was set - update real read buffer pointer + * to avoid overflow status + */ + if(rxBufferLoopDetect != 0u ) + { + MIDI2_UART_rxBufferLoopDetect = 0u; + #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntDisable(MIDI2_UART_RX_VECT_NUM); + #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */ + MIDI2_UART_rxBufferRead = rxBufferRead; + #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntEnable(MIDI2_UART_RX_VECT_NUM); + #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */ + } + + msgRtn = USBFS_ProcessMidiIn(rxData, + (USBFS_MIDI_RX_STATUS *)&USBFS_MIDI2_Event); + + /* Read buffer loop condition to the local variable */ + rxBufferLoopDetect = MIDI2_UART_rxBufferLoopDetect; + } + + /* Finally, update the real output pointer, then return with + * an indication as to whether there's a complete message in the buffer. + */ + #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntDisable(MIDI2_UART_RX_VECT_NUM); + #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */ + MIDI2_UART_rxBufferRead = rxBufferRead; + #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntEnable(MIDI2_UART_RX_VECT_NUM); + #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */ + } + + return (msgRtn); + } + + + /******************************************************************************* + * Function Name: USBFS_MIDI2_ProcessUsbOut + ******************************************************************************** + * + * Summary: + * Process a USB MIDI output event. + * Puts data into the MIDI TX output buffer. + * + * Parameters: + * *epBuf: pointer on MIDI event. + * + * Return: + * None + * + * Global variables: + * USBFS_MIDI2_TxRunStat: This variable used to save the MIDI + * status byte and skip to send the repeated status byte in subsequent event. + * USBFS_MIDI2_InqFlags: The following flags are set when SysEx + * message comes. + * USBFS_INQ_SYSEX_FLAG: Non-Real Time SySEx message received. + * USBFS_INQ_IDENTITY_REQ_FLAG: Identity Request received. + * This bit should be cleared by user when Identity Reply message generated. + * + *******************************************************************************/ + void USBFS_MIDI2_ProcessUsbOut(const uint8 epBuf[]) + + { + uint8 cmd; + uint8 len; + uint8 i; + + /* User code is required at the beginning of the procedure */ + /* `#START MIDI2_PROCESS_OUT_START` */ + + /* `#END` */ + + cmd = epBuf[USBFS_EVENT_BYTE0] & USBFS_CIN_MASK; + if((cmd != USBFS_RESERVED0) && (cmd != USBFS_RESERVED1)) + { + len = USBFS_MIDI_SIZE[cmd]; + i = USBFS_EVENT_BYTE1; + /* Universal System Exclusive message parsing */ + if(cmd == USBFS_SYSEX) + { + if((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX) && + (epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_NON_REAL_TIME)) + { /* SySEx starts */ + USBFS_MIDI2_InqFlags |= USBFS_INQ_SYSEX_FLAG; + } + else + { + USBFS_MIDI2_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; + } + } + else if(cmd == USBFS_SYSEX_ENDS_WITH1) + { + USBFS_MIDI2_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; + } + else if(cmd == USBFS_SYSEX_ENDS_WITH2) + { + USBFS_MIDI2_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; + } + else if(cmd == USBFS_SYSEX_ENDS_WITH3) + { + /* Identify Request support */ + if((USBFS_MIDI2_InqFlags & USBFS_INQ_SYSEX_FLAG) != 0u) + { + USBFS_MIDI2_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; + if((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX_GEN_INFORMATION) && + (epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_IDENTITY_REQ)) + { /* Set the flag about received the Identity Request. + * The Identity Reply message may be send by user code. + */ + USBFS_MIDI2_InqFlags |= USBFS_INQ_IDENTITY_REQ_FLAG; + } + } + } + else /* Do nothing for other command */ + { + } + /* Running Status for Voice and Mode messages only. */ + if((cmd >= USBFS_NOTE_OFF) && ( cmd <= USBFS_PITCH_BEND_CHANGE)) + { + if(USBFS_MIDI2_TxRunStat == epBuf[USBFS_EVENT_BYTE1]) + { /* Skip the repeated Status byte */ + i++; + } + else + { /* Save Status byte for next event */ + USBFS_MIDI2_TxRunStat = epBuf[USBFS_EVENT_BYTE1]; + } + } + else + { /* Clear Running Status */ + USBFS_MIDI2_TxRunStat = 0u; + } + /* Puts data into the MIDI TX output buffer.*/ + do + { + MIDI2_UART_PutChar(epBuf[i]); + i++; + } while (i <= len); + } + + /* User code is required at the end of the procedure */ + /* `#START MIDI2_PROCESS_OUT_END` */ + + /* `#END` */ + } +#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ +#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ + +#endif /* End (USBFS_ENABLE_MIDI_API != 0u) */ + + +/* `#START MIDI_FUNCTIONS` Place any additional functions here */ + +/* `#END` */ + +#endif /* End defined(USBFS_ENABLE_MIDI_STREAMING) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.h new file mode 100644 index 00000000..473cc26d --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.h @@ -0,0 +1,200 @@ +/******************************************************************************* +* File Name: USBFS_midi.h +* Version 2.60 +* +* Description: +* Header File for the USBFS MIDI module. +* Contains prototypes and constant values. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_USBFS_USBFS_midi_H) +#define CY_USBFS_USBFS_midi_H + +#include "cytypes.h" +#include "USBFS.h" + + +/*************************************** +* Data Struct Definition +***************************************/ + +/* The following structure is used to hold status information for + building and parsing incoming MIDI messages. */ +typedef struct +{ + uint8 length; /* expected length */ + uint8 count; /* current byte count */ + uint8 size; /* complete size */ + uint8 runstat; /* running status */ + uint8 msgBuff[4]; /* message buffer */ +} USBFS_MIDI_RX_STATUS; + + +/*************************************** +* MIDI Constants. +***************************************/ + +#define USBFS_ONE_EXT_INTRF (0x01u) +#define USBFS_TWO_EXT_INTRF (0x02u) + +/* Flag definitions for use with MIDI device inquiry */ +#define USBFS_INQ_SYSEX_FLAG (0x01u) +#define USBFS_INQ_IDENTITY_REQ_FLAG (0x02u) + +/* USB-MIDI Code Index Number Classifications (MIDI Table 4-1) */ +#define USBFS_CIN_MASK (0x0Fu) +#define USBFS_RESERVED0 (0x00u) +#define USBFS_RESERVED1 (0x01u) +#define USBFS_2BYTE_COMMON (0x02u) +#define USBFS_3BYTE_COMMON (0x03u) +#define USBFS_SYSEX (0x04u) +#define USBFS_1BYTE_COMMON (0x05u) +#define USBFS_SYSEX_ENDS_WITH1 (0x05u) +#define USBFS_SYSEX_ENDS_WITH2 (0x06u) +#define USBFS_SYSEX_ENDS_WITH3 (0x07u) +#define USBFS_NOTE_OFF (0x08u) +#define USBFS_NOTE_ON (0x09u) +#define USBFS_POLY_KEY_PRESSURE (0x0Au) +#define USBFS_CONTROL_CHANGE (0x0Bu) +#define USBFS_PROGRAM_CHANGE (0x0Cu) +#define USBFS_CHANNEL_PRESSURE (0x0Du) +#define USBFS_PITCH_BEND_CHANGE (0x0Eu) +#define USBFS_SINGLE_BYTE (0x0Fu) + +#define USBFS_CABLE_MASK (0xF0u) +#define USBFS_MIDI_CABLE_00 (0x00u) +#define USBFS_MIDI_CABLE_01 (0x10u) + +#define USBFS_EVENT_BYTE0 (0x00u) +#define USBFS_EVENT_BYTE1 (0x01u) +#define USBFS_EVENT_BYTE2 (0x02u) +#define USBFS_EVENT_BYTE3 (0x03u) +#define USBFS_EVENT_LENGTH (0x04u) + +#define USBFS_MIDI_STATUS_BYTE_MASK (0x80u) +#define USBFS_MIDI_STATUS_MASK (0xF0u) +#define USBFS_MIDI_SINGLE_BYTE_MASK (0x08u) +#define USBFS_MIDI_NOTE_OFF (0x80u) +#define USBFS_MIDI_NOTE_ON (0x90u) +#define USBFS_MIDI_POLY_KEY_PRESSURE (0xA0u) +#define USBFS_MIDI_CONTROL_CHANGE (0xB0u) +#define USBFS_MIDI_PROGRAM_CHANGE (0xC0u) +#define USBFS_MIDI_CHANNEL_PRESSURE (0xD0u) +#define USBFS_MIDI_PITCH_BEND_CHANGE (0xE0u) +#define USBFS_MIDI_SYSEX (0xF0u) +#define USBFS_MIDI_EOSEX (0xF7u) +#define USBFS_MIDI_QFM (0xF1u) +#define USBFS_MIDI_SPP (0xF2u) +#define USBFS_MIDI_SONGSEL (0xF3u) +#define USBFS_MIDI_TUNEREQ (0xF6u) +#define USBFS_MIDI_ACTIVESENSE (0xFEu) + +/* MIDI Universal System Exclusive defines */ +#define USBFS_MIDI_SYSEX_NON_REAL_TIME (0x7Eu) +#define USBFS_MIDI_SYSEX_REALTIME (0x7Fu) +/* ID of target device */ +#define USBFS_MIDI_SYSEX_ID_ALL (0x7Fu) +/* Sub-ID#1*/ +#define USBFS_MIDI_SYSEX_GEN_INFORMATION (0x06u) +#define USBFS_MIDI_SYSEX_GEN_MESSAGE (0x09u) +/* Sub-ID#2*/ +#define USBFS_MIDI_SYSEX_IDENTITY_REQ (0x01u) +#define USBFS_MIDI_SYSEX_IDENTITY_REPLY (0x02u) +#define USBFS_MIDI_SYSEX_SYSTEM_ON (0x01u) +#define USBFS_MIDI_SYSEX_SYSTEM_OFF (0x02u) + +#define USBFS_CUSTOM_UART_TX_PRIOR_NUM (0x04u) +#define USBFS_CUSTOM_UART_RX_PRIOR_NUM (0x02u) + +#define USBFS_ISR_SERVICE_MIDI_OUT \ + ( (USBFS_ENABLE_MIDI_API != 0u) && \ + (USBFS_MIDI_OUT_BUFF_SIZE > 0) && (USBFS_EP_MM == USBFS__EP_DMAAUTO) ) +#define USBFS_ISR_SERVICE_MIDI_IN \ + ( (USBFS_ENABLE_MIDI_API != 0u) && (USBFS_MIDI_IN_BUFF_SIZE > 0) ) + +/*************************************** +* External function references +***************************************/ + +void USBFS_callbackLocalMidiEvent(uint8 cable, uint8 *midiMsg) + ; + + +/*************************************** +* External references +***************************************/ + +#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + #include "MIDI1_UART.h" +#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ +#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + #include "MIDI2_UART.h" +#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ +#if(USBFS_EP_MM != USBFS__EP_MANUAL) + #include +#endif /* End USBFS_EP_MM */ + + +/*************************************** +* Private function prototypes +***************************************/ + +void USBFS_PrepareInBuffer(uint8 ic, const uint8 srcBuff[], uint8 eventLen, uint8 cable) + ; +#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + void USBFS_MIDI_Init(void) ; + uint8 USBFS_ProcessMidiIn(uint8 mData, USBFS_MIDI_RX_STATUS *rxStat) + ; + uint8 USBFS_MIDI1_GetEvent(void) ; + void USBFS_MIDI1_ProcessUsbOut(const uint8 epBuf[]) + ; + + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + uint8 USBFS_MIDI2_GetEvent(void) ; + void USBFS_MIDI2_ProcessUsbOut(const uint8 epBuf[]) + ; + #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ +#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ + + +/*************************************** +* External data references +***************************************/ + +#if defined(USBFS_ENABLE_MIDI_STREAMING) + +#if (USBFS_MIDI_IN_BUFF_SIZE > 0) + #if (USBFS_MIDI_IN_BUFF_SIZE >= 256) + extern volatile uint16 USBFS_midiInPointer; /* Input endpoint buffer pointer */ + #else + extern volatile uint8 USBFS_midiInPointer; /* Input endpoint buffer pointer */ + #endif /* End USBFS_MIDI_IN_BUFF_SIZE >=256 */ + extern volatile uint8 USBFS_midi_in_ep; /* Input endpoint number */ + extern uint8 USBFS_midiInBuffer[USBFS_MIDI_IN_BUFF_SIZE]; /* Input endpoint buffer */ +#endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */ + +#if (USBFS_MIDI_OUT_BUFF_SIZE > 0) + extern volatile uint8 USBFS_midi_out_ep; /* Output endpoint number */ + extern uint8 USBFS_midiOutBuffer[USBFS_MIDI_OUT_BUFF_SIZE]; /* Output endpoint buffer */ +#endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */ + +#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + extern volatile uint8 USBFS_MIDI1_InqFlags; /* Device inquiry flag */ + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + extern volatile uint8 USBFS_MIDI2_InqFlags; /* Device inquiry flag */ + #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ +#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ + +#endif /* USBFS_ENABLE_MIDI_STREAMING */ + + +#endif /* End CY_USBFS_USBFS_midi_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_pm.c b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_pm.c new file mode 100644 index 00000000..003d7f17 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_pm.c @@ -0,0 +1,277 @@ +/******************************************************************************* +* File Name: USBFS_pm.c +* Version 2.60 +* +* Description: +* This file provides Suspend/Resume APIs functionality. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "project.h" +#include "USBFS.h" +#include "USBFS_pvt.h" + + +/*************************************** +* Custom Declarations +***************************************/ +/* `#START PM_CUSTOM_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +/*************************************** +* Local data allocation +***************************************/ + +static USBFS_BACKUP_STRUCT USBFS_backup; + + +#if(USBFS_DP_ISR_REMOVE == 0u) + + + /******************************************************************************* + * Function Name: USBFS_DP_Interrupt + ******************************************************************************** + * + * Summary: + * This Interrupt Service Routine handles DP pin changes for wake-up from + * the sleep mode. + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + CY_ISR(USBFS_DP_ISR) + { + /* `#START DP_USER_CODE` Place your code here */ + + /* `#END` */ + + /* Clears active interrupt */ + CY_GET_REG8(USBFS_DP_INTSTAT_PTR); + } + +#endif /* (USBFS_DP_ISR_REMOVE == 0u) */ + + +/******************************************************************************* +* Function Name: USBFS_SaveConfig +******************************************************************************** +* +* Summary: +* Saves the current user configuration. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_SaveConfig(void) +{ + +} + + +/******************************************************************************* +* Function Name: USBFS_RestoreConfig +******************************************************************************** +* +* Summary: +* Restores the current user configuration. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_RestoreConfig(void) +{ + if(USBFS_configuration != 0u) + { + USBFS_ConfigReg(); + } +} + + +/******************************************************************************* +* Function Name: USBFS_Suspend +******************************************************************************** +* +* Summary: +* This function disables the USBFS block and prepares for power donwn mode. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* USBFS_backup.enable: modified. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_Suspend(void) +{ + uint8 enableInterrupts; + enableInterrupts = CyEnterCriticalSection(); + + if((CY_GET_REG8(USBFS_CR0_PTR) & USBFS_CR0_ENABLE) != 0u) + { /* USB block is enabled */ + USBFS_backup.enableState = 1u; + + #if(USBFS_EP_MM != USBFS__EP_MANUAL) + USBFS_Stop_DMA(USBFS_MAX_EP); /* Stop all DMAs */ + #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ + + /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled */ + USBFS_USBIO_CR0_REG &= (uint8)~USBFS_USBIO_CR0_TEN; + CyDelayUs(0u); /*~50ns delay */ + + /* Disable the USBIO by asserting PM.USB_CR0.fsusbio_pd_n(Inverted) and pd_pullup_hv(Inverted) high. */ + USBFS_PM_USB_CR0_REG &= + (uint8)~(USBFS_PM_USB_CR0_PD_N | USBFS_PM_USB_CR0_PD_PULLUP_N); + + /* Disable the SIE */ + USBFS_CR0_REG &= (uint8)~USBFS_CR0_ENABLE; + + CyDelayUs(0u); /*~50ns delay */ + /* Store mode and Disable VRegulator*/ + USBFS_backup.mode = USBFS_CR1_REG & USBFS_CR1_REG_ENABLE; + USBFS_CR1_REG &= (uint8)~USBFS_CR1_REG_ENABLE; + + CyDelayUs(1u); /* 0.5 us min delay */ + /* Disable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/ + USBFS_PM_USB_CR0_REG &= (uint8)~USBFS_PM_USB_CR0_REF_EN; + + /* Switch DP and DM terminals to GPIO mode and disconnect 1.5k pullup*/ + USBFS_USBIO_CR1_REG |= USBFS_USBIO_CR1_IOMODE; + + /* Disable USB in ACT PM */ + USBFS_PM_ACT_CFG_REG &= (uint8)~USBFS_PM_ACT_EN_FSUSB; + /* Disable USB block for Standby Power Mode */ + USBFS_PM_STBY_CFG_REG &= (uint8)~USBFS_PM_STBY_EN_FSUSB; + CyDelayUs(1u); /* min 0.5us delay required */ + + } + else + { + USBFS_backup.enableState = 0u; + } + CyExitCriticalSection(enableInterrupts); + + /* Set the DP Interrupt for wake-up from sleep mode. */ + #if(USBFS_DP_ISR_REMOVE == 0u) + (void) CyIntSetVector(USBFS_DP_INTC_VECT_NUM, &USBFS_DP_ISR); + CyIntSetPriority(USBFS_DP_INTC_VECT_NUM, USBFS_DP_INTC_PRIOR); + CyIntClearPending(USBFS_DP_INTC_VECT_NUM); + CyIntEnable(USBFS_DP_INTC_VECT_NUM); + #endif /* (USBFS_DP_ISR_REMOVE == 0u) */ + +} + + +/******************************************************************************* +* Function Name: USBFS_Resume +******************************************************************************** +* +* Summary: +* This function enables the USBFS block after power down mode. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* USBFS_backup - checked. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_Resume(void) +{ + uint8 enableInterrupts; + enableInterrupts = CyEnterCriticalSection(); + + if(USBFS_backup.enableState != 0u) + { + #if(USBFS_DP_ISR_REMOVE == 0u) + CyIntDisable(USBFS_DP_INTC_VECT_NUM); + #endif /* End USBFS_DP_ISR_REMOVE */ + + /* Enable USB block */ + USBFS_PM_ACT_CFG_REG |= USBFS_PM_ACT_EN_FSUSB; + /* Enable USB block for Standby Power Mode */ + USBFS_PM_STBY_CFG_REG |= USBFS_PM_STBY_EN_FSUSB; + /* Enable core clock */ + USBFS_USB_CLK_EN_REG |= USBFS_USB_CLK_ENABLE; + + /* Enable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/ + USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_REF_EN; + /* The reference will be available ~40us after power restored */ + CyDelayUs(40u); + /* Return VRegulator*/ + USBFS_CR1_REG |= USBFS_backup.mode; + CyDelayUs(0u); /*~50ns delay */ + /* Enable USBIO */ + USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_N; + CyDelayUs(2u); + /* Set the USBIO pull-up enable */ + USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_PULLUP_N; + + /* Reinit Arbiter configuration for DMA transfers */ + #if(USBFS_EP_MM != USBFS__EP_MANUAL) + /* usb arb interrupt enable */ + USBFS_ARB_INT_EN_REG = USBFS_ARB_INT_MASK; + #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL) + USBFS_ARB_CFG_REG = USBFS_ARB_CFG_MANUAL_DMA; + #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */ + #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + /*Set cfg cmplt this rises DMA request when the full configuration is done */ + USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM; + #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ + #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ + + /* STALL_IN_OUT */ + CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT); + /* Enable the SIE with a last address */ + USBFS_CR0_REG |= USBFS_CR0_ENABLE; + CyDelayCycles(1u); + /* Finally, Enable d+ pullup and select iomode to USB mode*/ + CY_SET_REG8(USBFS_USBIO_CR1_PTR, USBFS_USBIO_CR1_USBPUEN); + + /* Restore USB register settings */ + USBFS_RestoreConfig(); + + } + CyExitCriticalSection(enableInterrupts); +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h new file mode 100644 index 00000000..c98757f8 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h @@ -0,0 +1,203 @@ +/******************************************************************************* +* File Name: .h +* Version 2.60 +* +* Description: +* This private file provides constants and parameter values for the +* USBFS Component. +* Please do not use this file or its content in your project. +* +* Note: +* +******************************************************************************** +* Copyright 2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_USBFS_USBFS_pvt_H) +#define CY_USBFS_USBFS_pvt_H + + +/*************************************** +* Private Variables +***************************************/ + +/* Generated external references for descriptors*/ +extern const uint8 CYCODE USBFS_DEVICE0_DESCR[18u]; +extern const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_DESCR[41u]; +extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_TABLE[1u]; +extern const T_USBFS_EP_SETTINGS_BLOCK CYCODE USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE[2u]; +extern const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE_CLASS[1u]; +extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_TABLE[4u]; +extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_TABLE[2u]; +extern const T_USBFS_LUT CYCODE USBFS_TABLE[1u]; +extern const uint8 CYCODE USBFS_SN_STRING_DESCRIPTOR[10]; +extern const uint8 CYCODE USBFS_STRING_DESCRIPTORS[83u]; +extern T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_RPT_SCB; +extern uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF[ + USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF_SIZE]; +extern T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_RPT_SCB; +extern uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF[ + USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF_SIZE]; +extern const uint8 CYCODE USBFS_HIDREPORT_DESCRIPTOR1[40u]; +extern const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_RPT_TABLE[1u]; +extern const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_RPT_TABLE[1u]; +extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_TABLE[5u]; + + +extern const uint8 CYCODE USBFS_MSOS_DESCRIPTOR[USBFS_MSOS_DESCRIPTOR_LENGTH]; +extern const uint8 CYCODE USBFS_MSOS_CONFIGURATION_DESCR[USBFS_MSOS_CONF_DESCR_LENGTH]; +#if defined(USBFS_ENABLE_IDSN_STRING) + extern uint8 USBFS_idSerialNumberStringDescriptor[USBFS_IDSN_DESCR_LENGTH]; +#endif /* USBFS_ENABLE_IDSN_STRING */ + +extern volatile uint8 USBFS_interfaceNumber; +extern volatile uint8 USBFS_interfaceSetting[USBFS_MAX_INTERFACES_NUMBER]; +extern volatile uint8 USBFS_interfaceSetting_last[USBFS_MAX_INTERFACES_NUMBER]; +extern volatile uint8 USBFS_deviceAddress; +extern volatile uint8 USBFS_interfaceStatus[USBFS_MAX_INTERFACES_NUMBER]; +extern const uint8 CYCODE *USBFS_interfaceClass; + +extern volatile T_USBFS_EP_CTL_BLOCK USBFS_EP[USBFS_MAX_EP]; +extern volatile T_USBFS_TD USBFS_currentTD; + +#if(USBFS_EP_MM != USBFS__EP_MANUAL) + extern uint8 USBFS_DmaChan[USBFS_MAX_EP]; + extern uint8 USBFS_DmaTd[USBFS_MAX_EP]; +#endif /* End USBFS_EP_MM */ + +extern volatile uint8 USBFS_ep0Toggle; +extern volatile uint8 USBFS_lastPacketSize; +extern volatile uint8 USBFS_ep0Mode; +extern volatile uint8 USBFS_ep0Count; +extern volatile uint16 USBFS_transferByteCount; + + +/*************************************** +* Private Function Prototypes +***************************************/ +void USBFS_ReInitComponent(void) ; +void USBFS_HandleSetup(void) ; +void USBFS_HandleIN(void) ; +void USBFS_HandleOUT(void) ; +void USBFS_LoadEP0(void) ; +uint8 USBFS_InitControlRead(void) ; +uint8 USBFS_InitControlWrite(void) ; +void USBFS_ControlReadDataStage(void) ; +void USBFS_ControlReadStatusStage(void) ; +void USBFS_ControlReadPrematureStatus(void) + ; +uint8 USBFS_InitControlWrite(void) ; +uint8 USBFS_InitZeroLengthControlTransfer(void) + ; +void USBFS_ControlWriteDataStage(void) ; +void USBFS_ControlWriteStatusStage(void) ; +void USBFS_ControlWritePrematureStatus(void) + ; +uint8 USBFS_InitNoDataControlTransfer(void) ; +void USBFS_NoDataControlStatusStage(void) ; +void USBFS_InitializeStatusBlock(void) ; +void USBFS_UpdateStatusBlock(uint8 completionCode) ; +uint8 USBFS_DispatchClassRqst(void) ; + +void USBFS_Config(uint8 clearAltSetting) ; +void USBFS_ConfigAltChanged(void) ; +void USBFS_ConfigReg(void) ; + +const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 c) + ; +const T_USBFS_LUT CYCODE *USBFS_GetDeviceTablePtr(void) + ; +const uint8 CYCODE *USBFS_GetInterfaceClassTablePtr(void) + ; +uint8 USBFS_ClearEndpointHalt(void) ; +uint8 USBFS_SetEndpointHalt(void) ; +uint8 USBFS_ValidateAlternateSetting(void) ; + +void USBFS_SaveConfig(void) ; +void USBFS_RestoreConfig(void) ; + +#if defined(USBFS_ENABLE_IDSN_STRING) + void USBFS_ReadDieID(uint8 descr[]) ; +#endif /* USBFS_ENABLE_IDSN_STRING */ + +#if defined(USBFS_ENABLE_HID_CLASS) + uint8 USBFS_DispatchHIDClassRqst(void); +#endif /* End USBFS_ENABLE_HID_CLASS */ +#if defined(USBFS_ENABLE_AUDIO_CLASS) + uint8 USBFS_DispatchAUDIOClassRqst(void); +#endif /* End USBFS_ENABLE_HID_CLASS */ +#if defined(USBFS_ENABLE_CDC_CLASS) + uint8 USBFS_DispatchCDCClassRqst(void); +#endif /* End USBFS_ENABLE_CDC_CLASS */ + +CY_ISR_PROTO(USBFS_EP_0_ISR); +#if(USBFS_EP1_ISR_REMOVE == 0u) + CY_ISR_PROTO(USBFS_EP_1_ISR); +#endif /* End USBFS_EP1_ISR_REMOVE */ +#if(USBFS_EP2_ISR_REMOVE == 0u) + CY_ISR_PROTO(USBFS_EP_2_ISR); +#endif /* End USBFS_EP2_ISR_REMOVE */ +#if(USBFS_EP3_ISR_REMOVE == 0u) + CY_ISR_PROTO(USBFS_EP_3_ISR); +#endif /* End USBFS_EP3_ISR_REMOVE */ +#if(USBFS_EP4_ISR_REMOVE == 0u) + CY_ISR_PROTO(USBFS_EP_4_ISR); +#endif /* End USBFS_EP4_ISR_REMOVE */ +#if(USBFS_EP5_ISR_REMOVE == 0u) + CY_ISR_PROTO(USBFS_EP_5_ISR); +#endif /* End USBFS_EP5_ISR_REMOVE */ +#if(USBFS_EP6_ISR_REMOVE == 0u) + CY_ISR_PROTO(USBFS_EP_6_ISR); +#endif /* End USBFS_EP6_ISR_REMOVE */ +#if(USBFS_EP7_ISR_REMOVE == 0u) + CY_ISR_PROTO(USBFS_EP_7_ISR); +#endif /* End USBFS_EP7_ISR_REMOVE */ +#if(USBFS_EP8_ISR_REMOVE == 0u) + CY_ISR_PROTO(USBFS_EP_8_ISR); +#endif /* End USBFS_EP8_ISR_REMOVE */ +CY_ISR_PROTO(USBFS_BUS_RESET_ISR); +#if(USBFS_SOF_ISR_REMOVE == 0u) + CY_ISR_PROTO(USBFS_SOF_ISR); +#endif /* End USBFS_SOF_ISR_REMOVE */ +#if(USBFS_EP_MM != USBFS__EP_MANUAL) + CY_ISR_PROTO(USBFS_ARB_ISR); +#endif /* End USBFS_EP_MM */ +#if(USBFS_DP_ISR_REMOVE == 0u) + CY_ISR_PROTO(USBFS_DP_ISR); +#endif /* End USBFS_DP_ISR_REMOVE */ + + +/*************************************** +* Request Handlers +***************************************/ + +uint8 USBFS_HandleStandardRqst(void) ; +uint8 USBFS_DispatchClassRqst(void) ; +uint8 USBFS_HandleVendorRqst(void) ; + + +/*************************************** +* HID Internal references +***************************************/ +#if defined(USBFS_ENABLE_HID_CLASS) + void USBFS_FindReport(void) ; + void USBFS_FindReportDescriptor(void) ; + void USBFS_FindHidClassDecriptor(void) ; +#endif /* USBFS_ENABLE_HID_CLASS */ + + +/*************************************** +* MIDI Internal references +***************************************/ +#if defined(USBFS_ENABLE_MIDI_STREAMING) + void USBFS_MIDI_IN_EP_Service(void) ; +#endif /* USBFS_ENABLE_MIDI_STREAMING */ + + +#endif /* CY_USBFS_USBFS_pvt_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_std.c b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_std.c new file mode 100644 index 00000000..af2f201a --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_std.c @@ -0,0 +1,1134 @@ +/******************************************************************************* +* File Name: USBFS_std.c +* Version 2.60 +* +* Description: +* USB Standard request handler. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS.h" +#include "USBFS_cdc.h" +#include "USBFS_pvt.h" +#if defined(USBFS_ENABLE_MIDI_STREAMING) + #include "USBFS_midi.h" +#endif /* End USBFS_ENABLE_MIDI_STREAMING*/ + + +/*************************************** +* Static data allocation +***************************************/ + +#if defined(USBFS_ENABLE_FWSN_STRING) + static volatile uint8 *USBFS_fwSerialNumberStringDescriptor; + static volatile uint8 USBFS_snStringConfirm = USBFS_FALSE; +#endif /* USBFS_ENABLE_FWSN_STRING */ + +#if defined(USBFS_ENABLE_FWSN_STRING) + + + /******************************************************************************* + * Function Name: USBFS_SerialNumString + ******************************************************************************** + * + * Summary: + * Application firmware may supply the source of the USB device descriptors + * serial number string during runtime. + * + * Parameters: + * snString: pointer to string. + * + * Return: + * None. + * + * Reentrant: + * No. + * + *******************************************************************************/ + void USBFS_SerialNumString(uint8 snString[]) + { + USBFS_snStringConfirm = USBFS_FALSE; + if(snString != NULL) + { + USBFS_fwSerialNumberStringDescriptor = snString; + /* Check descriptor validation */ + if( (snString[0u] > 1u ) && (snString[1u] == USBFS_DESCR_STRING) ) + { + USBFS_snStringConfirm = USBFS_TRUE; + } + } + } + +#endif /* USBFS_ENABLE_FWSN_STRING */ + + +/******************************************************************************* +* Function Name: USBFS_HandleStandardRqst +******************************************************************************** +* +* Summary: +* This Routine dispatches standard requests +* +* Parameters: +* None. +* +* Return: +* TRUE if request handled. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_HandleStandardRqst(void) +{ + uint8 requestHandled = USBFS_FALSE; + uint8 interfaceNumber; + #if defined(USBFS_ENABLE_STRINGS) + volatile uint8 *pStr = 0u; + #if defined(USBFS_ENABLE_DESCRIPTOR_STRINGS) + uint8 nStr; + uint8 descrLength; + #endif /* USBFS_ENABLE_DESCRIPTOR_STRINGS */ + #endif /* USBFS_ENABLE_STRINGS */ + static volatile uint8 USBFS_tBuffer[USBFS_STATUS_LENGTH_MAX]; + const T_USBFS_LUT CYCODE *pTmp; + USBFS_currentTD.count = 0u; + + if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H) + { + /* Control Read */ + switch (CY_GET_REG8(USBFS_bRequest)) + { + case USBFS_GET_DESCRIPTOR: + if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_DEVICE) + { + pTmp = USBFS_GetDeviceTablePtr(); + USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list; + USBFS_currentTD.count = USBFS_DEVICE_DESCR_LENGTH; + requestHandled = USBFS_InitControlRead(); + } + else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_CONFIG) + { + pTmp = USBFS_GetConfigTablePtr(CY_GET_REG8(USBFS_wValueLo)); + USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list; + USBFS_currentTD.count = ((uint16)(USBFS_currentTD.pData)[ \ + USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI] << 8u) | \ + (USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW]; + requestHandled = USBFS_InitControlRead(); + } + #if defined(USBFS_ENABLE_STRINGS) + else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_STRING) + { + /* Descriptor Strings*/ + #if defined(USBFS_ENABLE_DESCRIPTOR_STRINGS) + nStr = 0u; + pStr = (volatile uint8 *)&USBFS_STRING_DESCRIPTORS[0u]; + while ( (CY_GET_REG8(USBFS_wValueLo) > nStr) && (*pStr != 0u) ) + { + /* Read descriptor length from 1st byte */ + descrLength = *pStr; + /* Move to next string descriptor */ + pStr = &pStr[descrLength]; + nStr++; + } + #endif /* End USBFS_ENABLE_DESCRIPTOR_STRINGS */ + /* Microsoft OS String*/ + #if defined(USBFS_ENABLE_MSOS_STRING) + if( CY_GET_REG8(USBFS_wValueLo) == USBFS_STRING_MSOS ) + { + pStr = (volatile uint8 *)&USBFS_MSOS_DESCRIPTOR[0u]; + } + #endif /* End USBFS_ENABLE_MSOS_STRING*/ + /* SN string */ + #if defined(USBFS_ENABLE_SN_STRING) + if( (CY_GET_REG8(USBFS_wValueLo) != 0u) && + (CY_GET_REG8(USBFS_wValueLo) == + USBFS_DEVICE0_DESCR[USBFS_DEVICE_DESCR_SN_SHIFT]) ) + { + pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u]; + #if defined(USBFS_ENABLE_FWSN_STRING) + if(USBFS_snStringConfirm != USBFS_FALSE) + { + pStr = USBFS_fwSerialNumberStringDescriptor; + } + #endif /* USBFS_ENABLE_FWSN_STRING */ + #if defined(USBFS_ENABLE_IDSN_STRING) + /* Read DIE ID and generate string descriptor in RAM */ + USBFS_ReadDieID(USBFS_idSerialNumberStringDescriptor); + pStr = USBFS_idSerialNumberStringDescriptor; + #endif /* End USBFS_ENABLE_IDSN_STRING */ + } + #endif /* End USBFS_ENABLE_SN_STRING */ + if (*pStr != 0u) + { + USBFS_currentTD.count = *pStr; + USBFS_currentTD.pData = pStr; + requestHandled = USBFS_InitControlRead(); + } + } + #endif /* End USBFS_ENABLE_STRINGS */ + else + { + requestHandled = USBFS_DispatchClassRqst(); + } + break; + case USBFS_GET_STATUS: + switch ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK)) + { + case USBFS_RQST_RCPT_EP: + USBFS_currentTD.count = USBFS_EP_STATUS_LENGTH; + USBFS_tBuffer[0u] = USBFS_EP[ \ + CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED].hwEpState; + USBFS_tBuffer[1u] = 0u; + USBFS_currentTD.pData = &USBFS_tBuffer[0u]; + requestHandled = USBFS_InitControlRead(); + break; + case USBFS_RQST_RCPT_DEV: + USBFS_currentTD.count = USBFS_DEVICE_STATUS_LENGTH; + USBFS_tBuffer[0u] = USBFS_deviceStatus; + USBFS_tBuffer[1u] = 0u; + USBFS_currentTD.pData = &USBFS_tBuffer[0u]; + requestHandled = USBFS_InitControlRead(); + break; + default: /* requestHandled is initialized as FALSE by default */ + break; + } + break; + case USBFS_GET_CONFIGURATION: + USBFS_currentTD.count = 1u; + USBFS_currentTD.pData = (volatile uint8 *)&USBFS_configuration; + requestHandled = USBFS_InitControlRead(); + break; + case USBFS_GET_INTERFACE: + USBFS_currentTD.count = 1u; + USBFS_currentTD.pData = (volatile uint8 *)&USBFS_interfaceSetting[ \ + CY_GET_REG8(USBFS_wIndexLo)]; + requestHandled = USBFS_InitControlRead(); + break; + default: /* requestHandled is initialized as FALSE by default */ + break; + } + } + else { + /* Control Write */ + switch (CY_GET_REG8(USBFS_bRequest)) + { + case USBFS_SET_ADDRESS: + USBFS_deviceAddress = CY_GET_REG8(USBFS_wValueLo); + requestHandled = USBFS_InitNoDataControlTransfer(); + break; + case USBFS_SET_CONFIGURATION: + USBFS_configuration = CY_GET_REG8(USBFS_wValueLo); + USBFS_configurationChanged = USBFS_TRUE; + USBFS_Config(USBFS_TRUE); + requestHandled = USBFS_InitNoDataControlTransfer(); + break; + case USBFS_SET_INTERFACE: + if (USBFS_ValidateAlternateSetting() != 0u) + { + interfaceNumber = CY_GET_REG8(USBFS_wIndexLo); + USBFS_interfaceNumber = interfaceNumber; + USBFS_configurationChanged = USBFS_TRUE; + #if ((USBFS_EP_MA == USBFS__MA_DYNAMIC) && \ + (USBFS_EP_MM == USBFS__EP_MANUAL) ) + USBFS_Config(USBFS_FALSE); + #else + USBFS_ConfigAltChanged(); + #endif /* End (USBFS_EP_MA == USBFS__MA_DYNAMIC) */ + /* Update handled Alt setting changes status */ + USBFS_interfaceSetting_last[interfaceNumber] = + USBFS_interfaceSetting[interfaceNumber]; + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + case USBFS_CLEAR_FEATURE: + switch (CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) + { + case USBFS_RQST_RCPT_EP: + if (CY_GET_REG8(USBFS_wValueLo) == USBFS_ENDPOINT_HALT) + { + requestHandled = USBFS_ClearEndpointHalt(); + } + break; + case USBFS_RQST_RCPT_DEV: + /* Clear device REMOTE_WAKEUP */ + if (CY_GET_REG8(USBFS_wValueLo) == USBFS_DEVICE_REMOTE_WAKEUP) + { + USBFS_deviceStatus &= (uint8)~USBFS_DEVICE_STATUS_REMOTE_WAKEUP; + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + case USBFS_RQST_RCPT_IFC: + /* Validate interfaceNumber */ + if (CY_GET_REG8(USBFS_wIndexLo) < USBFS_MAX_INTERFACES_NUMBER) + { + USBFS_interfaceStatus[CY_GET_REG8(USBFS_wIndexLo)] &= + (uint8)~(CY_GET_REG8(USBFS_wValueLo)); + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + default: /* requestHandled is initialized as FALSE by default */ + break; + } + break; + case USBFS_SET_FEATURE: + switch (CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) + { + case USBFS_RQST_RCPT_EP: + if (CY_GET_REG8(USBFS_wValueLo) == USBFS_ENDPOINT_HALT) + { + requestHandled = USBFS_SetEndpointHalt(); + } + break; + case USBFS_RQST_RCPT_DEV: + /* Set device REMOTE_WAKEUP */ + if (CY_GET_REG8(USBFS_wValueLo) == USBFS_DEVICE_REMOTE_WAKEUP) + { + USBFS_deviceStatus |= USBFS_DEVICE_STATUS_REMOTE_WAKEUP; + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + case USBFS_RQST_RCPT_IFC: + /* Validate interfaceNumber */ + if (CY_GET_REG8(USBFS_wIndexLo) < USBFS_MAX_INTERFACES_NUMBER) + { + USBFS_interfaceStatus[CY_GET_REG8(USBFS_wIndexLo)] &= + (uint8)~(CY_GET_REG8(USBFS_wValueLo)); + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + default: /* requestHandled is initialized as FALSE by default */ + break; + } + break; + default: /* requestHandled is initialized as FALSE by default */ + break; + } + } + return(requestHandled); +} + + +#if defined(USBFS_ENABLE_IDSN_STRING) + + /*************************************************************************** + * Function Name: USBFS_ReadDieID + **************************************************************************** + * + * Summary: + * This routine read Die ID and generate Serial Number string descriptor. + * + * Parameters: + * descr: pointer on string descriptor. + * + * Return: + * None. + * + * Reentrant: + * No. + * + ***************************************************************************/ + void USBFS_ReadDieID(uint8 descr[]) + { + uint8 i; + uint8 j = 0u; + uint8 value; + const char8 CYCODE hex[16u] = "0123456789ABCDEF"; + + + /* Check descriptor validation */ + if( descr != NULL) + { + descr[0u] = USBFS_IDSN_DESCR_LENGTH; + descr[1u] = USBFS_DESCR_STRING; + + /* fill descriptor */ + for(i = 2u; i < USBFS_IDSN_DESCR_LENGTH; i += 4u) + { + value = CY_GET_XTND_REG8((void CYFAR *)(USBFS_DIE_ID + j)); + j++; + descr[i] = (uint8)hex[value >> 4u]; + descr[i + 2u] = (uint8)hex[value & 0x0Fu]; + } + } + } + +#endif /* End USBFS_ENABLE_IDSN_STRING */ + + +/******************************************************************************* +* Function Name: USBFS_ConfigReg +******************************************************************************** +* +* Summary: +* This routine configures hardware registers from the variables. +* It is called from USBFS_Config() function and from RestoreConfig +* after Wakeup. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void USBFS_ConfigReg(void) +{ + uint8 ep; + uint8 i; + #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + uint8 ep_type = 0u; + #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ + + /* Set the endpoint buffer addresses */ + ep = USBFS_EP1; + for (i = 0u; i < 0x80u; i+= 0x10u) + { + CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_CFG_IND + i), USBFS_ARB_EPX_CFG_CRC_BYPASS | + USBFS_ARB_EPX_CFG_RESET); + + #if(USBFS_EP_MM != USBFS__EP_MANUAL) + /* Enable all Arbiter EP Interrupts : err, buf under, buf over, dma gnt(mode2 only), in buf full */ + CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_INT_EN_IND + i), USBFS_ARB_EPX_INT_MASK); + #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ + + if(USBFS_EP[ep].epMode != USBFS_MODE_DISABLE) + { + if((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u ) + { + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + i), USBFS_MODE_NAK_IN); + } + else + { + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + i), USBFS_MODE_NAK_OUT); + /* Prepare EP type mask for automatic memory allocation */ + #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + ep_type |= (uint8)(0x01u << (ep - USBFS_EP1)); + #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ + } + } + else + { + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + i), USBFS_MODE_STALL_DATA_EP); + } + + #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + i), USBFS_EP[ep].bufferSize >> 8u); + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + i), USBFS_EP[ep].bufferSize & 0xFFu); + + CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_IND + i), USBFS_EP[ep].buffOffset & 0xFFu); + CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u); + CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + i), USBFS_EP[ep].buffOffset & 0xFFu); + CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u); + #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */ + + ep++; + } + + #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + /* BUF_SIZE depend on DMA_THRESS value: 55-32 bytes 44-16 bytes 33-8 bytes 22-4 bytes 11-2 bytes */ + USBFS_BUF_SIZE_REG = USBFS_DMA_BUF_SIZE; + USBFS_DMA_THRES_REG = USBFS_DMA_BYTES_PER_BURST; /* DMA burst threshold */ + USBFS_DMA_THRES_MSB_REG = 0u; + USBFS_EP_ACTIVE_REG = USBFS_ARB_INT_MASK; + USBFS_EP_TYPE_REG = ep_type; + /* Cfg_cmp bit set to 1 once configuration is complete. */ + USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM | + USBFS_ARB_CFG_CFG_CPM; + /* Cfg_cmp bit set to 0 during configuration of PFSUSB Registers. */ + USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM; + #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ + + CY_SET_REG8(USBFS_SIE_EP_INT_EN_PTR, 0xFFu); +} + + +/******************************************************************************* +* Function Name: USBFS_Config +******************************************************************************** +* +* Summary: +* This routine configures endpoints for the entire configuration by scanning +* the configuration descriptor. +* +* Parameters: +* clearAltSetting: It configures the bAlternateSetting 0 for each interface. +* +* Return: +* None. +* +* USBFS_interfaceClass - Initialized class array for each interface. +* It is used for handling Class specific requests depend on interface class. +* Different classes in multiple Alternate settings does not supported. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_Config(uint8 clearAltSetting) +{ + uint8 ep; + uint8 cur_ep; + uint8 i; + uint8 ep_type; + const uint8 *pDescr; + #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) + uint16 buffCount = 0u; + #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */ + + const T_USBFS_LUT CYCODE *pTmp; + const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP; + + /* Clear all of the endpoints */ + for (ep = 0u; ep < USBFS_MAX_EP; ep++) + { + USBFS_EP[ep].attrib = 0u; + USBFS_EP[ep].hwEpState = 0u; + USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_PENDING; + USBFS_EP[ep].epToggle = 0u; + USBFS_EP[ep].epMode = USBFS_MODE_DISABLE; + USBFS_EP[ep].bufferSize = 0u; + USBFS_EP[ep].interface = 0u; + + } + + /* Clear Alternate settings for all interfaces */ + if(clearAltSetting != 0u) + { + for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++) + { + USBFS_interfaceSetting[i] = 0x00u; + USBFS_interfaceSetting_last[i] = 0x00u; + } + } + + /* Init Endpoints and Device Status if configured */ + if(USBFS_configuration > 0u) + { + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + /* Set Power status for current configuration */ + pDescr = (const uint8 *)pTmp->p_list; + if((pDescr[USBFS_CONFIG_DESCR_ATTRIB] & USBFS_CONFIG_DESCR_ATTRIB_SELF_POWERED) != 0u) + { + USBFS_deviceStatus |= USBFS_DEVICE_STATUS_SELF_POWERED; + } + else + { + USBFS_deviceStatus &= (uint8)~USBFS_DEVICE_STATUS_SELF_POWERED; + } + /* Move to next element */ + pTmp = &pTmp[1u]; + ep = pTmp->c; /* For this table, c is the number of endpoints configurations */ + + #if ((USBFS_EP_MA == USBFS__MA_DYNAMIC) && \ + (USBFS_EP_MM == USBFS__EP_MANUAL) ) + /* Configure for dynamic EP memory allocation */ + /* p_list points the endpoint setting table. */ + pEP = (T_USBFS_EP_SETTINGS_BLOCK *) pTmp->p_list; + for (i = 0u; i < ep; i++) + { + /* Compare current Alternate setting with EP Alt*/ + if(USBFS_interfaceSetting[pEP->interface] == pEP->altSetting) + { + cur_ep = pEP->addr & USBFS_DIR_UNUSED; + ep_type = pEP->attributes & USBFS_EP_TYPE_MASK; + if (pEP->addr & USBFS_DIR_IN) + { + /* IN Endpoint */ + USBFS_EP[cur_ep].apiEpState = USBFS_EVENT_PENDING; + USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ? + USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN; + #if defined(USBFS_ENABLE_CDC_CLASS) + if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) || + (pEP->bMisc == USBFS_CLASS_CDC)) && + (ep_type != USBFS_EP_TYPE_INT)) + { + USBFS_cdc_data_in_ep = cur_ep; + } + #endif /* End USBFS_ENABLE_CDC_CLASS*/ + #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \ + (USBFS_MIDI_IN_BUFF_SIZE > 0) ) + if((pEP->bMisc == USBFS_CLASS_AUDIO) && + (ep_type == USBFS_EP_TYPE_BULK)) + { + USBFS_midi_in_ep = cur_ep; + } + #endif /* End USBFS_ENABLE_MIDI_STREAMING*/ + } + else + { + /* OUT Endpoint */ + USBFS_EP[cur_ep].apiEpState = USBFS_NO_EVENT_PENDING; + USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ? + USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT; + #if defined(USBFS_ENABLE_CDC_CLASS) + if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) || + (pEP->bMisc == USBFS_CLASS_CDC)) && + (ep_type != USBFS_EP_TYPE_INT)) + { + USBFS_cdc_data_out_ep = cur_ep; + } + #endif /* End USBFS_ENABLE_CDC_CLASS*/ + #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \ + (USBFS_MIDI_OUT_BUFF_SIZE > 0) ) + if((pEP->bMisc == USBFS_CLASS_AUDIO) && + (ep_type == USBFS_EP_TYPE_BULK)) + { + USBFS_midi_out_ep = cur_ep; + } + #endif /* End USBFS_ENABLE_MIDI_STREAMING*/ + } + USBFS_EP[cur_ep].bufferSize = pEP->bufferSize; + USBFS_EP[cur_ep].addr = pEP->addr; + USBFS_EP[cur_ep].attrib = pEP->attributes; + } + pEP = &pEP[1u]; + } + #else /* Config for static EP memory allocation */ + for (i = USBFS_EP1; i < USBFS_MAX_EP; i++) + { + /* p_list points the endpoint setting table. */ + pEP = (const T_USBFS_EP_SETTINGS_BLOCK CYCODE *) pTmp->p_list; + /* Find max length for each EP and select it (length could be different in different Alt settings) */ + /* but other settings should be correct with regards to Interface alt Setting */ + for (cur_ep = 0u; cur_ep < ep; cur_ep++) + { + /* EP count is equal to EP # in table and we found larger EP length than have before*/ + if(i == (pEP->addr & USBFS_DIR_UNUSED)) + { + if(USBFS_EP[i].bufferSize < pEP->bufferSize) + { + USBFS_EP[i].bufferSize = pEP->bufferSize; + } + /* Compare current Alternate setting with EP Alt*/ + if(USBFS_interfaceSetting[pEP->interface] == pEP->altSetting) + { + ep_type = pEP->attributes & USBFS_EP_TYPE_MASK; + if ((pEP->addr & USBFS_DIR_IN) != 0u) + { + /* IN Endpoint */ + USBFS_EP[i].apiEpState = USBFS_EVENT_PENDING; + USBFS_EP[i].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ? + USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN; + /* Find and init CDC IN endpoint number */ + #if defined(USBFS_ENABLE_CDC_CLASS) + if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) || + (pEP->bMisc == USBFS_CLASS_CDC)) && + (ep_type != USBFS_EP_TYPE_INT)) + { + USBFS_cdc_data_in_ep = i; + } + #endif /* End USBFS_ENABLE_CDC_CLASS*/ + #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \ + (USBFS_MIDI_IN_BUFF_SIZE > 0) ) + if((pEP->bMisc == USBFS_CLASS_AUDIO) && + (ep_type == USBFS_EP_TYPE_BULK)) + { + USBFS_midi_in_ep = i; + } + #endif /* End USBFS_ENABLE_MIDI_STREAMING*/ + } + else + { + /* OUT Endpoint */ + USBFS_EP[i].apiEpState = USBFS_NO_EVENT_PENDING; + USBFS_EP[i].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ? + USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT; + /* Find and init CDC IN endpoint number */ + #if defined(USBFS_ENABLE_CDC_CLASS) + if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) || + (pEP->bMisc == USBFS_CLASS_CDC)) && + (ep_type != USBFS_EP_TYPE_INT)) + { + USBFS_cdc_data_out_ep = i; + } + #endif /* End USBFS_ENABLE_CDC_CLASS*/ + #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \ + (USBFS_MIDI_OUT_BUFF_SIZE > 0) ) + if((pEP->bMisc == USBFS_CLASS_AUDIO) && + (ep_type == USBFS_EP_TYPE_BULK)) + { + USBFS_midi_out_ep = i; + } + #endif /* End USBFS_ENABLE_MIDI_STREAMING*/ + } + USBFS_EP[i].addr = pEP->addr; + USBFS_EP[i].attrib = pEP->attributes; + + #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + break; /* use first EP setting in Auto memory managment */ + #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ + } + } + pEP = &pEP[1u]; + } + } + #endif /* End (USBFS_EP_MA == USBFS__MA_DYNAMIC) */ + + /* Init class array for each interface and interface number for each EP. + * It is used for handling Class specific requests directed to either an + * interface or the endpoint. + */ + /* p_list points the endpoint setting table. */ + pEP = (const T_USBFS_EP_SETTINGS_BLOCK CYCODE *) pTmp->p_list; + for (i = 0u; i < ep; i++) + { + /* Configure interface number for each EP*/ + USBFS_EP[pEP->addr & USBFS_DIR_UNUSED].interface = pEP->interface; + pEP = &pEP[1u]; + } + /* Init pointer on interface class table*/ + USBFS_interfaceClass = USBFS_GetInterfaceClassTablePtr(); + /* Set the endpoint buffer addresses */ + + #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) + for (ep = USBFS_EP1; ep < USBFS_MAX_EP; ep++) + { + USBFS_EP[ep].buffOffset = buffCount; + buffCount += USBFS_EP[ep].bufferSize; + } + #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */ + + /* Configure hardware registers */ + USBFS_ConfigReg(); + } /* USBFS_configuration > 0 */ +} + + +/******************************************************************************* +* Function Name: USBFS_ConfigAltChanged +******************************************************************************** +* +* Summary: +* This routine update configuration for the required endpoints only. +* It is called after SET_INTERFACE request when Static memory allocation used. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_ConfigAltChanged(void) +{ + uint8 ep; + uint8 cur_ep; + uint8 i; + uint8 ep_type; + uint8 ri; + + const T_USBFS_LUT CYCODE *pTmp; + const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP; + + + /* Init Endpoints and Device Status if configured */ + if(USBFS_configuration > 0u) + { + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + pTmp = &pTmp[1u]; + ep = pTmp->c; /* For this table, c is the number of endpoints configurations */ + + /* Do not touch EP which doesn't need reconfiguration */ + /* When Alt setting changed, the only required endpoints need to be reconfigured */ + /* p_list points the endpoint setting table. */ + pEP = (const T_USBFS_EP_SETTINGS_BLOCK CYCODE *) pTmp->p_list; + for (i = 0u; i < ep; i++) + { + /*If Alt setting changed and new is same with EP Alt */ + if((USBFS_interfaceSetting[pEP->interface] != + USBFS_interfaceSetting_last[pEP->interface] ) && + (USBFS_interfaceSetting[pEP->interface] == pEP->altSetting) && + (pEP->interface == CY_GET_REG8(USBFS_wIndexLo))) + { + cur_ep = pEP->addr & USBFS_DIR_UNUSED; + ri = ((cur_ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); + ep_type = pEP->attributes & USBFS_EP_TYPE_MASK; + if ((pEP->addr & USBFS_DIR_IN) != 0u) + { + /* IN Endpoint */ + USBFS_EP[cur_ep].apiEpState = USBFS_EVENT_PENDING; + USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ? + USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN; + } + else + { + /* OUT Endpoint */ + USBFS_EP[cur_ep].apiEpState = USBFS_NO_EVENT_PENDING; + USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ? + USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT; + } + /* Change the SIE mode for the selected EP to NAK ALL */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_IN_OUT); + USBFS_EP[cur_ep].bufferSize = pEP->bufferSize; + USBFS_EP[cur_ep].addr = pEP->addr; + USBFS_EP[cur_ep].attrib = pEP->attributes; + + /* Clear the data toggle */ + USBFS_EP[cur_ep].epToggle = 0u; + + /* Dynamic reconfiguration for mode 3 transfer */ + #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + /* In_data_rdy for selected EP should be set to 0 */ + * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= (uint8)~USBFS_ARB_EPX_CFG_IN_DATA_RDY; + + /* write the EP number for which reconfiguration is required */ + USBFS_DYN_RECONFIG_REG = (cur_ep - USBFS_EP1) << + USBFS_DYN_RECONFIG_EP_SHIFT; + /* Set the dyn_config_en bit in dynamic reconfiguration register */ + USBFS_DYN_RECONFIG_REG |= USBFS_DYN_RECONFIG_ENABLE; + /* wait for the dyn_config_rdy bit to set by the block, + * this bit will be set to 1 when block is ready for reconfiguration. + */ + while((USBFS_DYN_RECONFIG_REG & USBFS_DYN_RECONFIG_RDY_STS) == 0u) + { + ; + } + /* Once dyn_config_rdy bit is set, FW can change the EP configuration. */ + /* Change EP Type with new direction */ + if((pEP->addr & USBFS_DIR_IN) == 0u) + { + USBFS_EP_TYPE_REG |= (uint8)(0x01u << (cur_ep - USBFS_EP1)); + } + else + { + USBFS_EP_TYPE_REG &= (uint8)~(uint8)(0x01u << (cur_ep - USBFS_EP1)); + } + /* dynamic reconfiguration enable bit cleared, pointers and control/status + * signals for the selected EP is cleared/re-initialized on negative edge + * of dynamic reconfiguration enable bit). + */ + USBFS_DYN_RECONFIG_REG &= (uint8)~USBFS_DYN_RECONFIG_ENABLE; + /* The main loop has to re-enable DMA and OUT endpoint*/ + #else + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri), + USBFS_EP[cur_ep].bufferSize >> 8u); + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + ri), + USBFS_EP[cur_ep].bufferSize & 0xFFu); + CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_IND + ri), + USBFS_EP[cur_ep].buffOffset & 0xFFu); + CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_MSB_IND + ri), + USBFS_EP[cur_ep].buffOffset >> 8u); + CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + ri), + USBFS_EP[cur_ep].buffOffset & 0xFFu); + CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + ri), + USBFS_EP[cur_ep].buffOffset >> 8u); + #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ + } + /* Get next EP element */ + pEP = &pEP[1u]; + } + } /* USBFS_configuration > 0 */ +} + + +/******************************************************************************* +* Function Name: USBFS_GetConfigTablePtr +******************************************************************************** +* +* Summary: +* This routine returns a pointer a configuration table entry +* +* Parameters: +* c: Configuration Index +* +* Return: +* Device Descriptor pointer. +* +*******************************************************************************/ +const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 c) + +{ + /* Device Table */ + const T_USBFS_LUT CYCODE *pTmp; + + pTmp = (const T_USBFS_LUT CYCODE *) USBFS_TABLE[USBFS_device].p_list; + + /* The first entry points to the Device Descriptor, + * the rest configuration entries. + */ + return( (const T_USBFS_LUT CYCODE *) pTmp[c + 1u].p_list ); +} + + +/******************************************************************************* +* Function Name: USBFS_GetDeviceTablePtr +******************************************************************************** +* +* Summary: +* This routine returns a pointer to the Device table +* +* Parameters: +* None. +* +* Return: +* Device Table pointer +* +*******************************************************************************/ +const T_USBFS_LUT CYCODE *USBFS_GetDeviceTablePtr(void) + +{ + /* Device Table */ + return( (const T_USBFS_LUT CYCODE *) USBFS_TABLE[USBFS_device].p_list ); +} + + +/******************************************************************************* +* Function Name: USB_GetInterfaceClassTablePtr +******************************************************************************** +* +* Summary: +* This routine returns Interface Class table pointer, which contains +* the relation between interface number and interface class. +* +* Parameters: +* None. +* +* Return: +* Interface Class table pointer. +* +*******************************************************************************/ +const uint8 CYCODE *USBFS_GetInterfaceClassTablePtr(void) + +{ + const T_USBFS_LUT CYCODE *pTmp; + uint8 currentInterfacesNum; + + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + currentInterfacesNum = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES]; + /* Third entry in the LUT starts the Interface Table pointers */ + /* The INTERFACE_CLASS table is located after all interfaces */ + pTmp = &pTmp[currentInterfacesNum + 2u]; + return( (const uint8 CYCODE *) pTmp->p_list ); +} + + +/******************************************************************************* +* Function Name: USBFS_TerminateEP +******************************************************************************** +* +* Summary: +* This function terminates the specified USBFS endpoint. +* This function should be used before endpoint reconfiguration. +* +* Parameters: +* Endpoint number. +* +* Return: +* None. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_TerminateEP(uint8 ep) +{ + uint8 ri; + + ep &= USBFS_DIR_UNUSED; + ri = ((ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); + + if ((ep > USBFS_EP0) && (ep < USBFS_MAX_EP)) + { + /* Set the endpoint Halt */ + USBFS_EP[ep].hwEpState |= (USBFS_ENDPOINT_STATUS_HALT); + + /* Clear the data toggle */ + USBFS_EP[ep].epToggle = 0u; + USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_ALLOWED; + + if ((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u) + { + /* IN Endpoint */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_IN); + } + else + { + /* OUT Endpoint */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_OUT); + } + } +} + + +/******************************************************************************* +* Function Name: USBFS_SetEndpointHalt +******************************************************************************** +* +* Summary: +* This routine handles set endpoint halt. +* +* Parameters: +* None. +* +* Return: +* requestHandled. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_SetEndpointHalt(void) +{ + uint8 ep; + uint8 ri; + uint8 requestHandled = USBFS_FALSE; + + /* Set endpoint halt */ + ep = CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED; + ri = ((ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); + + if ((ep > USBFS_EP0) && (ep < USBFS_MAX_EP)) + { + /* Set the endpoint Halt */ + USBFS_EP[ep].hwEpState |= (USBFS_ENDPOINT_STATUS_HALT); + + /* Clear the data toggle */ + USBFS_EP[ep].epToggle = 0u; + USBFS_EP[ep].apiEpState |= USBFS_NO_EVENT_ALLOWED; + + if ((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u) + { + /* IN Endpoint */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_STALL_DATA_EP | + USBFS_MODE_ACK_IN); + } + else + { + /* OUT Endpoint */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_STALL_DATA_EP | + USBFS_MODE_ACK_OUT); + } + requestHandled = USBFS_InitNoDataControlTransfer(); + } + + return(requestHandled); +} + + +/******************************************************************************* +* Function Name: USBFS_ClearEndpointHalt +******************************************************************************** +* +* Summary: +* This routine handles clear endpoint halt. +* +* Parameters: +* None. +* +* Return: +* requestHandled. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_ClearEndpointHalt(void) +{ + uint8 ep; + uint8 ri; + uint8 requestHandled = USBFS_FALSE; + + /* Clear endpoint halt */ + ep = CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED; + ri = ((ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); + + if ((ep > USBFS_EP0) && (ep < USBFS_MAX_EP)) + { + /* Clear the endpoint Halt */ + USBFS_EP[ep].hwEpState &= (uint8)~(USBFS_ENDPOINT_STATUS_HALT); + + /* Clear the data toggle */ + USBFS_EP[ep].epToggle = 0u; + /* Clear toggle bit for already armed packet */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri), CY_GET_REG8( + (reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri)) & (uint8)~USBFS_EPX_CNT_DATA_TOGGLE); + /* Return API State as it was defined before */ + USBFS_EP[ep].apiEpState &= (uint8)~USBFS_NO_EVENT_ALLOWED; + + if ((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u) + { + /* IN Endpoint */ + if(USBFS_EP[ep].apiEpState == USBFS_IN_BUFFER_EMPTY) + { /* Wait for next packet from application */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_IN); + } + else /* Continue armed transfer */ + { + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_ACK_IN); + } + } + else + { + /* OUT Endpoint */ + if(USBFS_EP[ep].apiEpState == USBFS_OUT_BUFFER_FULL) + { /* Allow application to read full buffer */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_OUT); + } + else /* Mark endpoint as empty, so it will be reloaded */ + { + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_ACK_OUT); + } + } + requestHandled = USBFS_InitNoDataControlTransfer(); + } + + return(requestHandled); +} + + +/******************************************************************************* +* Function Name: USBFS_ValidateAlternateSetting +******************************************************************************** +* +* Summary: +* Validates (and records) a SET INTERFACE request. +* +* Parameters: +* None. +* +* Return: +* requestHandled. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_ValidateAlternateSetting(void) +{ + uint8 requestHandled = USBFS_TRUE; + uint8 interfaceNum; + const T_USBFS_LUT CYCODE *pTmp; + uint8 currentInterfacesNum; + + interfaceNum = CY_GET_REG8(USBFS_wIndexLo); + /* Validate interface setting, stall if invalid. */ + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + currentInterfacesNum = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES]; + + if((interfaceNum >= currentInterfacesNum) || (interfaceNum >= USBFS_MAX_INTERFACES_NUMBER)) + { /* Wrong interface number */ + requestHandled = USBFS_FALSE; + } + else + { + /* Save current Alt setting to find out the difference in Config() function */ + USBFS_interfaceSetting_last[interfaceNum] = USBFS_interfaceSetting[interfaceNum]; + USBFS_interfaceSetting[interfaceNum] = CY_GET_REG8(USBFS_wValueLo); + } + + return (requestHandled); +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_vnd.c b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_vnd.c new file mode 100644 index 00000000..6543a676 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/USBFS_vnd.c @@ -0,0 +1,96 @@ +/******************************************************************************* +* File Name: USBFS_vnd.c +* Version 2.60 +* +* Description: +* USB vendor request handler. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS.h" +#include "USBFS_pvt.h" + +#if(USBFS_EXTERN_VND == USBFS_FALSE) + + +/*************************************** +* Vendor Specific Declarations +***************************************/ + +/* `#START VENDOR_SPECIFIC_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +/******************************************************************************* +* Function Name: USBFS_HandleVendorRqst +******************************************************************************** +* +* Summary: +* This routine provide users with a method to implement vendor specifc +* requests. +* +* To implement vendor specific requests, add your code in this function to +* decode and disposition the request. If the request is handled, your code +* must set the variable "requestHandled" to TRUE, indicating that the +* request has been handled. +* +* Parameters: +* None. +* +* Return: +* requestHandled. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_HandleVendorRqst(void) +{ + uint8 requestHandled = USBFS_FALSE; + + if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H) + { + /* Control Read */ + switch (CY_GET_REG8(USBFS_bRequest)) + { + case USBFS_GET_EXTENDED_CONFIG_DESCRIPTOR: + #if defined(USBFS_ENABLE_MSOS_STRING) + USBFS_currentTD.pData = (volatile uint8 *)&USBFS_MSOS_CONFIGURATION_DESCR[0u]; + USBFS_currentTD.count = USBFS_MSOS_CONFIGURATION_DESCR[0u]; + requestHandled = USBFS_InitControlRead(); + #endif /* End USBFS_ENABLE_MSOS_STRING */ + break; + default: + break; + } + } + + /* `#START VENDOR_SPECIFIC_CODE` Place your vendor specific request here */ + + /* `#END` */ + + return(requestHandled); +} + + +/******************************************************************************* +* Additional user functions supporting Vendor Specific Requests +********************************************************************************/ + +/* `#START VENDOR_SPECIFIC_FUNCTIONS` Place any additional functions here */ + +/* `#END` */ + + +#endif /* USBFS_EXTERN_VND */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cm3gcc.ld b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cm3gcc.ld new file mode 100644 index 00000000..66ec5a45 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cm3gcc.ld @@ -0,0 +1,295 @@ +/* Linker script for ARM M-profile Simulator + * + * Version: Sourcery G++ Lite 2010q1-188 + * Support: https://support.codesourcery.com/GNUToolchain/ + * + * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc. + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +ENTRY(__cy_reset) +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) + + +MEMORY +{ + rom (rx) : ORIGIN = 0x0, LENGTH = 131072 + ram (rwx) : ORIGIN = 0x20000000 - (32768 / 2), LENGTH = 32768 +} + + +CY_APPL_ORIGIN = 0; +CY_FLASH_ROW_SIZE = 256; +CY_ECC_ROW_SIZE = 32; +CY_EE_IN_BTLDR = 0x0; +CY_APPL_LOADABLE = 0; +CY_EE_SIZE = 2048; +CY_APPL_NUM = 1; +CY_APPL_MAX = 1; +CY_METADATA_SIZE = 64; + + +/* These force the linker to search for particular symbols from + * the start of the link process and thus ensure the user's + * overrides are picked up + */ +EXTERN(Reset) + +/* Bring in the interrupt routines & vector */ +EXTERN(main) + +/* Bring in the meta data */ +EXTERN(cy_meta_loader cy_bootloader cy_meta_loadable cy_meta_bootloader) +EXTERN(cy_meta_custnvl cy_meta_wolatch cy_meta_flashprotect cy_metadata) + +/* Provide fall-back values */ +PROVIDE(__cy_heap_start = _end); +PROVIDE(__cy_region_num = (__cy_regions_end - __cy_regions) / 16); +PROVIDE(__cy_stack = ORIGIN(ram) + LENGTH(ram)); +PROVIDE(__cy_heap_end = __cy_stack - 0x2000); + + +SECTIONS +{ + /* The bootloader location */ + .cybootloader 0x0 : { KEEP(*(.cybootloader)) } >rom + + /* Calculate where the loadables should start */ + appl1_start = CY_APPL_ORIGIN ? CY_APPL_ORIGIN : ALIGN(CY_FLASH_ROW_SIZE); + appl2_start = appl1_start + ALIGN((LENGTH(rom) - appl1_start - 2 * CY_FLASH_ROW_SIZE) / 2, CY_FLASH_ROW_SIZE); + appl_start = (CY_APPL_NUM == 1) ? appl1_start : appl2_start; + ecc_offset = (appl_start / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE; + ee_offset = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? ((CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1)) : 0; + ee_size = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? (CY_EE_SIZE / CY_APPL_MAX) : CY_EE_SIZE; + PROVIDE(CY_ECC_OFFSET = ecc_offset); + + .text appl_start : + { + CREATE_OBJECT_SYMBOLS + PROVIDE(__cy_interrupt_vector = RomVectors); + + *(.romvectors) + + /* Make sure we pulled in an interrupt vector. */ + ASSERT (. != __cy_interrupt_vector, "No interrupt vector"); + + ASSERT (CY_APPL_ORIGIN ? (SIZEOF(.cybootloader) <= CY_APPL_ORIGIN) : 1, "Wrong image location"); + + PROVIDE(__cy_reset = Reset); + *(.text.Reset) + /* Make sure we pulled in some reset code. */ + ASSERT (. != __cy_reset, "No reset code"); + + /* Place the DMA initialization before text to ensure it gets placed in first 64K of flash */ + *(.dma_init) + ASSERT(appl_start + . <= 0x10000 || !0, "DMA Init must be within the first 64k of flash"); + + *(.text .text.* .gnu.linkonce.t.*) + *(.plt) + *(.gnu.warning) + *(.glue_7t) *(.glue_7) *(.vfp11_veneer) + + KEEP(*(.bootloader)) /* necessary for bootloader's, but doesn't impact non-bootloaders */ + + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.gcc_except_table) + } >rom + .eh_frame_hdr : ALIGN (4) + { + KEEP (*(.eh_frame_hdr)) + } >rom + .eh_frame : ALIGN (4) + { + KEEP (*(.eh_frame)) + } >rom + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >rom + __exidx_end = .; + .rodata : ALIGN (4) + { + *(.rodata .rodata.* .gnu.linkonce.r.*) + + . = ALIGN(4); + KEEP(*(.init)) + + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + __cy_regions = .; + LONG (__cy_region_init_ram) + LONG (__cy_region_start_data) + LONG (__cy_region_init_size_ram) + LONG (__cy_region_zero_size_ram) + __cy_regions_end = .; + + . = ALIGN (8); + _etext = .; + } >rom + + .ramvectors (NOLOAD) : ALIGN(8) + { + __cy_region_start_ram = .; + KEEP(*(.ramvectors)) + } + + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } + + .data : ALIGN(8) + { + __cy_region_start_data = .; + + KEEP(*(.jcr)) + *(.got.plt) *(.got) + *(.shdata) + *(.data .data.* .gnu.linkonce.d.*) + . = ALIGN (8); + *(.ram) + _edata = .; + } >ram AT>rom + .bss : ALIGN(8) + { + PROVIDE(__bss_start__ = .); + *(.shbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + *(.ram.b) + _end = .; + __end = .; + } >ram AT>rom + PROVIDE(end = .); + PROVIDE(__bss_end__ = .); + + __cy_region_init_ram = LOADADDR (.data); + __cy_region_init_size_ram = _edata - ADDR (.data); + __cy_region_zero_size_ram = _end - _edata; + + /* The .stack and .heap sections don't contain any symbols. + * They are only used for linker to calculate RAM utilization. + */ + .heap (NOLOAD) : + { + . = _end; + . += 0x0800; + __cy_heap_limit = .; + } >ram + + .stack (__cy_stack - 0x2000) (NOLOAD) : + { + __cy_stack_limit = .; + . += 0x2000; + } >ram + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__cy_stack_limit >= __cy_heap_limit, "region RAM overflowed with stack") + + .cyloadermeta ((appl_start == 0) ? (LENGTH(rom) - CY_METADATA_SIZE) : 0xF0000000) : + { + KEEP(*(.cyloadermeta)) + } :NONE + + .cyloadablemeta (LENGTH(rom) - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) : + { + KEEP(*(.cyloadablemeta)) + } >rom + + .cyconfigecc (0x80000000 + ecc_offset) : + { + KEEP(*(.cyconfigecc)) + } :NONE + + .cycustnvl 0x90000000 : { KEEP(*(.cycustnvl)) } :NONE + .cywolatch 0x90100000 : { KEEP(*(.cywolatch)) } :NONE + + .cyeeprom (0x90200000 + ee_offset) : + { + KEEP(*(.cyeeprom)) + ASSERT(. <= (0x90200000 + ee_offset + ee_size), ".cyeeprom data will not fit in EEPROM"); + } :NONE + + .cyflashprotect 0x90400000 : { KEEP(*(.cyflashprotect)) } :NONE + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE + + .stab 0 (NOLOAD) : { *(.stab) } + .stabstr 0 (NOLOAD) : { *(.stabstr) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. + */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* DWARF 2.1 */ + .debug_ranges 0 : { *(.debug_ranges) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) } + .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) } + /DISCARD/ : { *(.note.GNU-stack) } +} + diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/core_cm3.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/core_cm3.h new file mode 100644 index 00000000..122c9aa4 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/core_cm3.h @@ -0,0 +1,1627 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200 + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h new file mode 100644 index 00000000..cb5d1655 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h @@ -0,0 +1,54 @@ +/******************************************************************************* +* File Name: core_cm3_psoc5.h +* Version 4.0 +* +* Description: +* Provides important type information for the PSoC5. This includes types +* necessary for core_cm3.h. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + + +#if !defined(__CORE_CM3_PSOC5_H__) +#define __CORE_CM3_PSOC5_H__ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1 /*!< 15 Cortex-M3 System Tick Interrupt */ +/****** PSoC5 Peripheral Interrupt Numbers *******************************************************/ + /* Not relevant. All peripheral interrupts are defined by the user */ +} IRQn_Type; + +#include + +#define __CHECK_DEVICE_DEFINES + +#define __CM3_REV 0x0201 + +#define __MPU_PRESENT 0 +#define __NVIC_PRIO_BITS 3 +#define __Vendor_SysTickConfig 0 + +#include + + +#endif /* __CORE_CM3_PSOC5_H__ */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/core_cmFunc.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/core_cmFunc.h new file mode 100644 index 00000000..0a18fafc --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/core_cmFunc.h @@ -0,0 +1,636 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CORE_CMFUNC_H */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/core_cmInstr.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/core_cmInstr.h new file mode 100644 index 00000000..ab3a0109 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/core_cmInstr.h @@ -0,0 +1,688 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V3.20 + * @date 05. March 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + uint32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return(result); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return(result); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyPm.c b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyPm.c new file mode 100644 index 00000000..9906255c --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyPm.c @@ -0,0 +1,1819 @@ +/******************************************************************************* +* File Name: cyPm.c +* Version 4.0 +* +* Description: +* Provides an API for the power management. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cyPm.h" + + +/******************************************************************* +* Place your includes, defines and code here. Do not use merge +* region below unless any component datasheet suggest to do so. +*******************************************************************/ +/* `#START CY_PM_HEADER_INCLUDE` */ + +/* `#END` */ + + +static CY_PM_BACKUP_STRUCT cyPmBackup; +static CY_PM_CLOCK_BACKUP_STRUCT cyPmClockBackup; + +/* Convertion table between register's values and frequency in MHz */ +static const uint8 CYCODE cyPmImoFreqReg2Mhz[7u] = {12u, 6u, 24u, 3u, 48u, 62u, 74u}; + +/* Function Prototypes */ +static void CyPmHibSaveSet(void); +static void CyPmHibRestore(void) ; + +static void CyPmHibSlpSaveSet(void) ; +static void CyPmHibSlpRestore(void) ; + +static void CyPmHviLviSaveDisable(void) ; +static void CyPmHviLviRestore(void) ; + + +/******************************************************************************* +* Function Name: CyPmSaveClocks +******************************************************************************** +* +* Summary: +* This function is called in preparation for entering sleep or hibernate low +* power modes. Saves all state of the clocking system that does not persist +* during sleep/hibernate or that needs to be altered in preparation for +* sleep/hibernate. Shutdowns all the digital and analog clock dividers for the +* active power mode configuration. +* +* Switches the master clock over to the IMO and shuts down the PLL and MHz +* Crystal. The IMO frequency is set to either 12 MHz or 48 MHz to match the +* Design-Wide Resources System Editor "Enable Fast IMO During Startup" setting. +* The ILO and 32 KHz oscillators are not impacted. The current Flash wait state +* setting is saved and the Flash wait state setting is set for the current IMO +* speed. +* +* Note If the Master Clock source is routed through the DSI inputs, then it +* must be set manually to another source before using the +* CyPmSaveClocks()/CyPmRestoreClocks() functions. +* +* Parameters: +* None +* +* Return: +* None +* +* Side Effects: +* All peripheral clocks are going to be off after this API method call. +* +*******************************************************************************/ +void CyPmSaveClocks(void) +{ + /* Digital and analog clocks - save enable state and disable them all */ + cyPmClockBackup.enClkA = CY_PM_ACT_CFG1_REG & CY_PM_ACT_EN_CLK_A_MASK; + cyPmClockBackup.enClkD = CY_PM_ACT_CFG2_REG; + CY_PM_ACT_CFG1_REG &= ((uint8)(~CY_PM_ACT_EN_CLK_A_MASK)); + CY_PM_ACT_CFG2_REG &= ((uint8)(~CY_PM_ACT_EN_CLK_D_MASK)); + + /* Save current flash wait cycles and set the maximum value */ + cyPmClockBackup.flashWaitCycles = CY_PM_CACHE_CR_CYCLES_MASK & CY_PM_CACHE_CR_REG; + CyFlash_SetWaitCycles(CY_PM_MAX_FLASH_WAIT_CYCLES); + + /* IMO - save current IMO MHz OSC frequency and USB mode is on bit */ + cyPmClockBackup.imoFreq = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK; + cyPmClockBackup.imoUsbClk = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_USB; + + /* IMO doubler - save enable state */ + if(0u != (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_F2XON)) + { + /* IMO doubler enabled - save and disable */ + cyPmClockBackup.imo2x = CY_PM_ENABLED; + } + else + { + /* IMO doubler disabled */ + cyPmClockBackup.imo2x = CY_PM_DISABLED; + } + + /* IMO - set appropriate frequency for LPM */ + CyIMO_SetFreq(CY_PM_IMO_FREQ_LPM); + + /* IMO - save enable state and enable without wait to settle */ + if(0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG)) + { + /* IMO - save enabled state */ + cyPmClockBackup.imoEnable = CY_PM_ENABLED; + } + else + { + /* IMO - save disabled state */ + cyPmClockBackup.imoEnable = CY_PM_DISABLED; + + /* IMO - enable */ + CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE); + } + + /* IMO - save the current IMOCLK source and set to IMO if not yet */ + if(0u != (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_XCLKEN)) + { + /* DSI or XTAL CLK */ + cyPmClockBackup.imoClkSrc = + (0u == (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO2X_SRC)) ? CY_IMO_SOURCE_DSI : CY_IMO_SOURCE_XTAL; + + /* IMO - set IMOCLK source to MHz OSC */ + CyIMO_SetSource(CY_IMO_SOURCE_IMO); + } + else + { + /* IMO */ + cyPmClockBackup.imoClkSrc = CY_IMO_SOURCE_IMO; + } + + /* Save clk_imo source */ + cyPmClockBackup.clkImoSrc = CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO_OUT_MASK; + + /* If IMOCLK2X or SPC OSC is source for clk_imo, set it to IMOCLK */ + if(CY_PM_CLKDIST_IMO_OUT_IMO != cyPmClockBackup.clkImoSrc) + { + /* Set IMOCLK to source for clk_imo */ + CY_PM_CLKDIST_CR_REG = (CY_PM_CLKDIST_CR_REG & ((uint8)(~CY_PM_CLKDIST_IMO_OUT_MASK))) | + CY_PM_CLKDIST_IMO_OUT_IMO; + } /* Need to change nothing if IMOCLK is source clk_imo */ + + /* IMO doubler - disable it (saved above) */ + if(0u != (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_F2XON)) + { + CyIMO_DisableDoubler(); + } + + /* Master clock - save divider and set it to divide-by-one (if no yet) */ + cyPmClockBackup.clkSyncDiv = CY_PM_CLKDIST_MSTR0_REG; + if(CY_PM_DIV_BY_ONE != cyPmClockBackup.clkSyncDiv) + { + CyMasterClk_SetDivider(CY_PM_DIV_BY_ONE); + } /* Need to change nothing if master clock divider is 1 */ + + /* Master clock - save current source */ + cyPmClockBackup.masterClkSrc = CY_PM_CLKDIST_MSTR1_REG & CY_PM_MASTER_CLK_SRC_MASK; + + /* Master clock source - set it to IMO if not yet. */ + if(CY_MASTER_SOURCE_IMO != cyPmClockBackup.masterClkSrc) + { + CyMasterClk_SetSource(CY_MASTER_SOURCE_IMO); + } /* Need to change nothing if master clock source is IMO */ + + /* Bus clock - save divider and set it, if needed, to divide-by-one */ + cyPmClockBackup.clkBusDiv = (uint16) ((uint16) CY_PM_CLK_BUS_MSB_DIV_REG << 8u); + cyPmClockBackup.clkBusDiv |= CY_PM_CLK_BUS_LSB_DIV_REG; + if(CY_PM_BUS_CLK_DIV_BY_ONE != cyPmClockBackup.clkBusDiv) + { + CyBusClk_SetDivider(CY_PM_BUS_CLK_DIV_BY_ONE); + } /* Do nothing if saved and actual values are equal */ + + /* Set number of wait cycles for the flash according CPU frequency in MHz */ + CyFlash_SetWaitCycles((uint8)CY_PM_GET_CPU_FREQ_MHZ); + + /* PLL - check enable state, disable if needed */ + if(0u != (CY_PM_FASTCLK_PLL_CFG0_REG & CY_PM_PLL_CFG0_ENABLE)) + { + /* PLL is enabled - save state and disable */ + cyPmClockBackup.pllEnableState = CY_PM_ENABLED; + CyPLL_OUT_Stop(); + } + else + { + /* PLL is disabled - save state */ + cyPmClockBackup.pllEnableState = CY_PM_DISABLED; + } + + /* MHz ECO - check enable state and disable if needed */ + if(0u != (CY_PM_FASTCLK_XMHZ_CSR_REG & CY_PM_XMHZ_CSR_ENABLE)) + { + /* MHz ECO is enabled - save state and disable */ + cyPmClockBackup.xmhzEnableState = CY_PM_ENABLED; + CyXTAL_Stop(); + } + else + { + /* MHz ECO is disabled - save state */ + cyPmClockBackup.xmhzEnableState = CY_PM_DISABLED; + } + + + /*************************************************************************** + * Save enable state of delay between the system bus clock and each of the + * 4 individual analog clocks. This bit non-retention and it's value should + * be restored on wakeup. + ***************************************************************************/ + if(0u != (CY_PM_CLKDIST_DELAY_REG & CY_PM_CLKDIST_DELAY_EN)) + { + cyPmClockBackup.clkDistDelay = CY_PM_ENABLED; + } + else + { + cyPmClockBackup.clkDistDelay = CY_PM_DISABLED; + } +} + + +/******************************************************************************* +* Function Name: CyPmRestoreClocks +******************************************************************************** +* +* Summary: +* Restores any state that was preserved by the last call to CyPmSaveClocks(). +* The Flash wait state setting is also restored. +* +* Note If the Master Clock source is routed through the DSI inputs, then it +* must be set manually to another source before using the +* CyPmSaveClocks()/CyPmRestoreClocks() functions. +* +* PSoC 3 and PSoC 5LP: +* The merge region could be used to process state when the megahertz crystal is +* not ready after the hold-off timeout. +* +* PSoC 5: +* The 130 ms is given for the megahertz crystal to stabilize. It's readiness is +* not verified after the hold-off timeout. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyPmRestoreClocks(void) +{ + cystatus status = CYRET_TIMEOUT; + uint16 i; + uint16 clkBusDivTmp; + + + /* Convertion table between CyIMO_SetFreq() parameters and register's value */ + const uint8 CYCODE cyPmImoFreqMhz2Reg[7u] = { + CY_IMO_FREQ_12MHZ, CY_IMO_FREQ_6MHZ, CY_IMO_FREQ_24MHZ, CY_IMO_FREQ_3MHZ, + CY_IMO_FREQ_48MHZ, 5u, 6u}; + + /* Restore enable state of delay between the system bus clock and ACLKs. */ + if(CY_PM_ENABLED == cyPmClockBackup.clkDistDelay) + { + /* Delay for both the bandgap and the delay line to settle out */ + CyDelayCycles((uint32)(CY_PM_CLK_DELAY_BANDGAP_SETTLE_US + CY_PM_CLK_DELAY_BIAS_SETTLE_US) * + CY_PM_GET_CPU_FREQ_MHZ); + + CY_PM_CLKDIST_DELAY_REG |= CY_PM_CLKDIST_DELAY_EN; + } + + /* MHz ECO restore state */ + if(CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState) + { + /*********************************************************************** + * Enabling XMHZ XTAL. The actual CyXTAL_Start() with non zero wait + * period uses FTW for period measurement. This could cause a problem + * if CTW/FTW is used as a wake up time in the low power modes APIs. + * So, the XTAL wait procedure is implemented with a software delay. + ***********************************************************************/ + + /* Enable XMHZ XTAL with no wait */ + (void) CyXTAL_Start(CY_PM_XTAL_MHZ_NO_WAIT); + + /* Read XERR bit to clear it */ + (void) CY_PM_FASTCLK_XMHZ_CSR_REG; + + /* Wait */ + for(i = CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US; i > 0u; i--) + { + /* Make a 200 microseconds delay */ + CyDelayCycles((uint32)CY_PM_WAIT_200_US * CY_PM_GET_CPU_FREQ_MHZ); + + /* High output indicates oscillator failure */ + if(0u == (CY_PM_FASTCLK_XMHZ_CSR_REG & CY_PM_XMHZ_CSR_XERR)) + { + status = CYRET_SUCCESS; + break; + } + } + + if(CYRET_TIMEOUT == status) + { + /******************************************************************* + * Process the situation when megahertz crystal is not ready. + * Time to stabialize value is crystal specific. + *******************************************************************/ + /* `#START_MHZ_ECO_TIMEOUT` */ + + /* `#END` */ + } + } /* (CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState) */ + + + /* Temprorary set the maximum flash wait cycles */ + CyFlash_SetWaitCycles(CY_PM_MAX_FLASH_WAIT_CYCLES); + + /* The XTAL and DSI clocks are ready to be source for Master clock. */ + if((CY_PM_MASTER_CLK_SRC_XTAL == cyPmClockBackup.masterClkSrc) || + (CY_PM_MASTER_CLK_SRC_DSI == cyPmClockBackup.masterClkSrc)) + { + /* Restore Master clock's divider */ + if(CY_PM_CLKDIST_MSTR0_REG != cyPmClockBackup.clkSyncDiv) + { + /* Restore Master clock divider */ + CyMasterClk_SetDivider(cyPmClockBackup.clkSyncDiv); + } + + /* Restore Master clock source */ + CyMasterClk_SetSource(cyPmClockBackup.masterClkSrc); + } + + /* IMO - restore IMO frequency */ + if((0u != (cyPmClockBackup.imoUsbClk & CY_PM_FASTCLK_IMO_CR_USB)) && + (CY_IMO_FREQ_24MHZ == cyPmImoFreqMhz2Reg[cyPmClockBackup.imoFreq])) + { + /* Restore IMO frequency (24 MHz) and trim it for USB */ + CyIMO_SetFreq(CY_IMO_FREQ_USB); + } + else + { + /* Restore IMO frequency */ + CyIMO_SetFreq(cyPmImoFreqMhz2Reg[cyPmClockBackup.imoFreq]); + + if(0u != (cyPmClockBackup.imoUsbClk & CY_PM_FASTCLK_IMO_CR_USB)) + { + CY_PM_FASTCLK_IMO_CR_REG |= CY_PM_FASTCLK_IMO_CR_USB; + } + else + { + CY_PM_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_PM_FASTCLK_IMO_CR_USB)); + } + } + + /* IMO - restore enable state if needed */ + if((CY_PM_ENABLED == cyPmClockBackup.imoEnable) && + (0u == (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG))) + { + /* IMO - restore enabled state */ + CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE); + } + + /* IMO - restore disable state if needed */ + if((CY_PM_DISABLED == cyPmClockBackup.imoEnable) && + (0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG))) + { + CyIMO_Stop(); + } + + /* IMO - restore IMOCLK source */ + CyIMO_SetSource(cyPmClockBackup.imoClkSrc); + + /* Restore IMO doubler enable state (turned off by CyPmSaveClocks()) */ + if(CY_PM_ENABLED == cyPmClockBackup.imo2x) + { + CyIMO_EnableDoubler(); + } + + /* IMO - restore clk_imo source, if needed */ + if(cyPmClockBackup.clkImoSrc != (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO_OUT_MASK)) + { + CY_PM_CLKDIST_CR_REG = (CY_PM_CLKDIST_CR_REG & ((uint8)(~CY_PM_CLKDIST_IMO_OUT_MASK))) | + cyPmClockBackup.clkImoSrc; + } + + /* PLL restore state */ + if(CY_PM_ENABLED == cyPmClockBackup.pllEnableState) + { + /*********************************************************************** + * Enable PLL. The actual CyPLL_OUT_Start() without wait period uses FTW + * for period measurement. This could cause a problem if CTW/FTW is used + * as a wakeup time in the low power modes APIs. To omit this issue PLL + * wait procedure is implemented with a software delay. + ***********************************************************************/ + + /* Enable PLL */ + (void) CyPLL_OUT_Start(CY_PM_PLL_OUT_NO_WAIT); + + /* Make a 250 us delay */ + CyDelayCycles((uint32)CY_PM_WAIT_250_US * CY_PM_GET_CPU_FREQ_MHZ); + } /* (CY_PM_ENABLED == cyPmClockBackup.pllEnableState) */ + + + /* PLL and IMO is ready to be source for Master clock */ + if((CY_PM_MASTER_CLK_SRC_IMO == cyPmClockBackup.masterClkSrc) || + (CY_PM_MASTER_CLK_SRC_PLL == cyPmClockBackup.masterClkSrc)) + { + /* Restore Master clock divider */ + if(CY_PM_CLKDIST_MSTR0_REG != cyPmClockBackup.clkSyncDiv) + { + CyMasterClk_SetDivider(cyPmClockBackup.clkSyncDiv); + } + + /* Restore Master clock source */ + CyMasterClk_SetSource(cyPmClockBackup.masterClkSrc); + } + + /* Bus clock - restore divider, if needed */ + clkBusDivTmp = (uint16) ((uint16)CY_PM_CLK_BUS_MSB_DIV_REG << 8u); + clkBusDivTmp |= CY_PM_CLK_BUS_LSB_DIV_REG; + if(cyPmClockBackup.clkBusDiv != clkBusDivTmp) + { + CyBusClk_SetDivider(cyPmClockBackup.clkBusDiv); + } + + /* Restore flash wait cycles */ + CY_PM_CACHE_CR_REG = ((CY_PM_CACHE_CR_REG & ((uint8)(~CY_PM_CACHE_CR_CYCLES_MASK))) | + cyPmClockBackup.flashWaitCycles); + + /* Digital and analog clocks - restore state */ + CY_PM_ACT_CFG1_REG = cyPmClockBackup.enClkA; + CY_PM_ACT_CFG2_REG = cyPmClockBackup.enClkD; +} + + +/******************************************************************************* +* Function Name: CyPmAltAct +******************************************************************************** +* +* Summary: +* Puts the part into the Alternate Active (Standby) state. The Alternate Active +* state can allow for any of the capabilities of the device to be active, but +* the operation of this function is dependent on the CPU being disabled during +* the Alternate Active state. The configuration code and the component APIs +* will configure the template for the Alternate Active state to be the same as +* the Active state with the exception that the CPU will be disabled during +* Alternate Active. +* +* Note Before calling this function, you must manually configure the power mode +* of the source clocks for the timer that is used as the wakeup timer. +* +* PSoC 3: +* Before switching to Alternate Active, if a wakeupTime other than NONE is +* specified, then the appropriate timer state is configured as specified with +* the interrupt for that timer disabled. The wakeup source will be the +* combination of the values specified in the wakeupSource and any timer +* specified in the wakeupTime argument. Once the wakeup condition is +* satisfied, then all saved state is restored and the function returns in the +* Active state. +* +* Note that if the wakeupTime is made with a different value, the period before +* the wakeup occurs can be significantly shorter than the specified time. If +* the next call is made with the same wakeupTime value, then the wakeup will +* occur the specified period after the previous wakeup occurred. +* +* If a wakeupTime other than NONE is specified, then upon exit the state of the +* specified timer will be left as specified by wakeupTime with the timer +* enabled and the interrupt disabled. If the CTW, FTW or One PPS is already +* configured for wakeup, for example with the SleepTimer or RTC components, +* then specify NONE for the wakeupTime and include the appropriate source for +* wakeupSource. +* +* PSoC 5LP: +* This function is used to both enter the Alternate Active mode and halt the +* processor. For PSoC 3 these two actions must be paired together. With PSoC +* 5LP the processor can be halted independently with the __WFI() function from +* the CMSIS library that is included in Creator. This function should be used +* instead when the action required is just to halt the processor until an +* enabled interrupt occurs. +* +* The wakeupTime parameter is not used for this device. It must be set to zero +* (PM_ALT_ACT_TIME_NONE). The wake up time configuration can be done by a +* separate component: the CTW wakeup interval should be configured with the +* Sleep Timer component and one second interval should be configured with the +* RTC component. +* +* The wakeup behavior depends on wakeupSource parameter in the following +* manner: upon function execution the device will be switched from Active to +* Alternate Active mode and then the CPU will be halted. When an enabled wakeup +* event occurs the device will return to Active mode. Similarly when an +* enabled interrupt occurs the CPU will be started. These two actions will +* occur together provided that the event that occurs is an enabled wakeup +* source and also generates an interrupt. If just the wakeup event occurs then +* the device will be in Active mode, but the CPU will remain halted waiting for +* an interrupt. If an interrupt occurs from something other than a wakeup +* source, then the CPU will restart with the device in Alternate Active mode +* until a wakeup event occurs. +* +* For example, if CyPmAltAct(PM_ALT_ACT_TIME_NONE, PM_ALT_ACT_SRC_PICU) is +* called and PICU interrupt occurs, the CPU will be started and device will be +* switched into Active mode. And if CyPmAltAct(PM_ALT_ACT_TIME_NONE, +* PM_ALT_ACT_SRC_NONE) is called and PICU interrupt occurs, the CPU will be +* started while device remains in Alternate Active mode. +* +* Parameters: +* wakeupTime: Specifies a timer wakeup source and the frequency of that +* source. For PSoC 5LP this parameter is ignored. +* +* Define Time +* PM_ALT_ACT_TIME_NONE None +* PM_ALT_ACT_TIME_ONE_PPS One PPS: 1 second +* PM_ALT_ACT_TIME_CTW_2MS CTW: 2 ms +* PM_ALT_ACT_TIME_CTW_4MS CTW: 4 ms +* PM_ALT_ACT_TIME_CTW_8MS CTW: 8 ms +* PM_ALT_ACT_TIME_CTW_16MS CTW: 16 ms +* PM_ALT_ACT_TIME_CTW_32MS CTW: 32 ms +* PM_ALT_ACT_TIME_CTW_64MS CTW: 64 ms +* PM_ALT_ACT_TIME_CTW_128MS CTW: 128 ms +* PM_ALT_ACT_TIME_CTW_256MS CTW: 256 ms +* PM_ALT_ACT_TIME_CTW_512MS CTW: 512 ms +* PM_ALT_ACT_TIME_CTW_1024MS CTW: 1024 ms +* PM_ALT_ACT_TIME_CTW_2048MS CTW: 2048 ms +* PM_ALT_ACT_TIME_CTW_4096MS CTW: 4096 ms +* PM_ALT_ACT_TIME_FTW(1-256)* FTW: 10us to 2.56 ms +* +* *Note: PM_ALT_ACT_TIME_FTW() is a macro that takes an argument that +* specifies how many increments of 10 us to delay. + For PSoC 3 silicon the valid range of values is 1 to 256. +* +* wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if +* a wakeupTime has been specified the associated timer will be +* included as a wakeup source. +* +* Define Source +* PM_ALT_ACT_SRC_NONE None +* PM_ALT_ACT_SRC_COMPARATOR0 Comparator 0 +* PM_ALT_ACT_SRC_COMPARATOR1 Comparator 1 +* PM_ALT_ACT_SRC_COMPARATOR2 Comparator 2 +* PM_ALT_ACT_SRC_COMPARATOR3 Comparator 3 +* PM_ALT_ACT_SRC_INTERRUPT Interrupt +* PM_ALT_ACT_SRC_PICU PICU +* PM_ALT_ACT_SRC_I2C I2C +* PM_ALT_ACT_SRC_BOOSTCONVERTER Boost Converter +* PM_ALT_ACT_SRC_FTW Fast Timewheel* +* PM_ALT_ACT_SRC_VD High and Low Voltage Detection (HVI, LVI)* +* PM_ALT_ACT_SRC_CTW Central Timewheel** +* PM_ALT_ACT_SRC_ONE_PPS One PPS** +* PM_ALT_ACT_SRC_LCD LCD +* +* *Note : FTW and HVI/LVI wakeup signals are in the same mask bit. +* **Note: CTW and One PPS wakeup signals are in the same mask bit. +* +* When specifying a Comparator as the wakeupSource an instance specific define +* should be used that will track with the specific comparator that the instance +* is placed into. As an example, for a Comparator instance named MyComp the +* value to OR into the mask is: MyComp_ctComp__CMP_MASK. +* +* When CTW, FTW or One PPS is used as a wakeup source, the CyPmReadStatus() +* function must be called upon wakeup with corresponding parameter. Please +* refer to the CyPmReadStatus() API in the System Reference Guide for more +* information. +* +* Return: +* None +* +* Reentrant: +* No +* +* Side Effects: +* If a wakeupTime other than NONE is specified, then upon exit the state of the +* specified timer will be left as specified by wakeupTime with the timer +* enabled and the interrupt disabled. Also, the ILO 1 KHz (if CTW timer is +* used as wakeup time) or ILO 100 KHz (if FTW timer is used as wakeup time) +* will be left started. +* +*******************************************************************************/ +void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource) +{ + #if(CY_PSOC5) + + /* Arguments expected to be 0 */ + CYASSERT(PM_ALT_ACT_TIME_NONE == wakeupTime); + + if(0u != wakeupTime) + { + /* To remove unreferenced local variable warning */ + } + + #endif /* (CY_PSOC5) */ + + + #if(CY_PSOC3) + + /* FTW - save current and set new configuration */ + if((wakeupTime >= PM_ALT_ACT_TIME_FTW(1u)) && (wakeupTime <= PM_ALT_ACT_TIME_FTW(256u))) + { + CyPmFtwSetInterval(PM_ALT_ACT_FTW_INTERVAL(wakeupTime)); + + /* Include associated timer to the wakeupSource */ + wakeupSource |= PM_ALT_ACT_SRC_FTW; + } + + /* CTW - save current and set new configuration */ + if((wakeupTime >= PM_ALT_ACT_TIME_CTW_2MS) && (wakeupTime <= PM_ALT_ACT_TIME_CTW_4096MS)) + { + /* Save current CTW configuration and set new one */ + CyPmCtwSetInterval((uint8)(wakeupTime - 1u)); + + /* Include associated timer to the wakeupSource */ + wakeupSource |= PM_ALT_ACT_SRC_CTW; + } + + /* 1PPS - save current and set new configuration */ + if(PM_ALT_ACT_TIME_ONE_PPS == wakeupTime) + { + /* Save current 1PPS configuration and set new one */ + CyPmOppsSet(); + + /* Include associated timer to the wakeupSource */ + wakeupSource |= PM_ALT_ACT_SRC_ONE_PPS; + } + + #endif /* (CY_PSOC3) */ + + + /* Save and set new wake up configuration */ + + /* Interrupt, PICU, I2C, Boost converter, CTW/1PPS */ + cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG; + CY_PM_WAKEUP_CFG0_REG = (uint8) (wakeupSource >> 4u); + + /* Comparators */ + cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG; + CY_PM_WAKEUP_CFG1_REG = (((uint8) wakeupSource) & CY_PM_WAKEUP_SRC_CMPS_MASK); + + /* LCD */ + cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG; + CY_PM_WAKEUP_CFG2_REG = ((uint8) ((wakeupSource >> 12u) & 0x01u)); + + + /* Switch to the Alternate Active mode */ + CY_PM_MODE_CSR_REG = ((CY_PM_MODE_CSR_REG & ((uint8)(~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_ALT_ACT); + + /* Recommended readback. */ + (void) CY_PM_MODE_CSR_REG; + + /* Two recommended NOPs to get into the mode. */ + CY_NOP; + CY_NOP; + + /* Execute WFI instruction (for ARM-based devices only) */ + CY_PM_WFI; + + /* Point of return from Alternate Active Mode */ + + /* Restore wake up configuration */ + CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0; + CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1; + CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2; +} + + +/******************************************************************************* +* Function Name: CyPmSleep +******************************************************************************** +* +* Summary: +* Puts the part into the Sleep state. +* +* Note Before calling this function, you must manually configure the power +* mode of the source clocks for the timer that is used as wakeup timer. +* +* Note Before calling this function, you must prepare clock tree configuration +* for the low power mode by calling CyPmSaveClocks(). And restore clock +* configuration after CyPmSleep() execution by calling CyPmRestoreClocks(). See +* Power Management section, Clock Configuration subsection of the System +* Reference Guide for more information. +* +* PSoC 3: +* Before switching to Sleep, if a wakeupTime other than NONE is specified, +* then the appropriate timer state is configured as specified with the +* interrupt for that timer disabled. The wakeup source will be the combination +* of the values specified in the wakeupSource and any timer specified in the +* wakeupTime argument. Once the wakeup condition is satisfied, then all saved +* state is restored and the function returns in the Active state. +* +* Note that if the wakeupTime is made with a different value, the period before +* the wakeup occurs can be significantly shorter than the specified time. If +* the next call is made with the same wakeupTime value, then the wakeup will +* occur the specified period after the previous wakeup occurred. +* +* If a wakeupTime other than NONE is specified, then upon exit the state of the +* specified timer will be left as specified by wakeupTime with the timer +* enabled and the interrupt disabled. If the CTW or One PPS is already +* configured for wakeup, for example with the SleepTimer or RTC components, +* then specify NONE for the wakeupTime and include the appropriate source for +* wakeupSource. +* +* PSoC 5LP: +* The wakeupTime parameter is not used and the only NONE can be specified. +* The wakeup time must be configured with the component, SleepTimer for CTW +* intervals and RTC for 1PPS interval. The component must be configured to +* generate an interrrupt. +* +* Parameters: +* wakeupTime: Specifies a timer wakeup source and the frequency of that +* source. For PSoC 5LP, this parameter is ignored. +* +* Define Time +* PM_SLEEP_TIME_NONE None +* PM_SLEEP_TIME_ONE_PPS One PPS: 1 second +* PM_SLEEP_TIME_CTW_2MS CTW: 2 ms +* PM_SLEEP_TIME_CTW_4MS CTW: 4 ms +* PM_SLEEP_TIME_CTW_8MS CTW: 8 ms +* PM_SLEEP_TIME_CTW_16MS CTW: 16 ms +* PM_SLEEP_TIME_CTW_32MS CTW: 32 ms +* PM_SLEEP_TIME_CTW_64MS CTW: 64 ms +* PM_SLEEP_TIME_CTW_128MS CTW: 128 ms +* PM_SLEEP_TIME_CTW_256MS CTW: 256 ms +* PM_SLEEP_TIME_CTW_512MS CTW: 512 ms +* PM_SLEEP_TIME_CTW_1024MS CTW: 1024 ms +* PM_SLEEP_TIME_CTW_2048MS CTW: 2048 ms +* PM_SLEEP_TIME_CTW_4096MS CTW: 4096 ms +* +* wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if +* a wakeupTime has been specified the associated timer will be +* included as a wakeup source. +* +* Define Source +* PM_SLEEP_SRC_NONE None +* PM_SLEEP_SRC_COMPARATOR0 Comparator 0 +* PM_SLEEP_SRC_COMPARATOR1 Comparator 1 +* PM_SLEEP_SRC_COMPARATOR2 Comparator 2 +* PM_SLEEP_SRC_COMPARATOR3 Comparator 3 +* PM_SLEEP_SRC_PICU PICU +* PM_SLEEP_SRC_I2C I2C +* PM_SLEEP_SRC_BOOSTCONVERTER Boost Converter +* PM_SLEEP_SRC_VD High and Low Voltage Detection (HVI, LVI) +* PM_SLEEP_SRC_CTW Central Timewheel* +* PM_SLEEP_SRC_ONE_PPS One PPS* +* PM_SLEEP_SRC_LCD LCD +* +* *Note: CTW and One PPS wakeup signals are in the same mask bit. +* +* When specifying a Comparator as the wakeupSource an instance specific define +* should be used that will track with the specific comparator that the instance +* is placed into. As an example for a Comparator instance named MyComp the +* value to OR into the mask is: MyComp_ctComp__CMP_MASK. +* +* When CTW or One PPS is used as a wakeup source, the CyPmReadStatus() +* function must be called upon wakeup with corresponding parameter. Please +* refer to the CyPmReadStatus() API in the System Reference Guide for more +* information. +* +* Return: +* None +* +* Reentrant: +* No +* +* Side Effects and Restrictions: +* If a wakeupTime other than NONE is specified, then upon exit the state of the +* specified timer will be left as specified by wakeupTime with the timer +* enabled and the interrupt disabled. Also, the ILO 1 KHz (if CTW timer is +* used as wake up time) will be left started. +* +* The 1 kHz ILO clock is expected to be enabled for PSoC 3 and PSoC 5LP to +* measure Hibernate/Sleep regulator settling time after a reset. The holdoff +* delay is measured using rising edges of the 1 kHz ILO. +* +* For PSoC 3 silicon hardware buzz should be disabled before entering a sleep +* power mode. It is disabled by PSoC Creator during startup. +* If a Low Voltage Interrupt (LVI), High Voltage Interrupt (HVI) or Brown Out +* detect (power supply supervising capabilities) are required in a design +* during sleep, use the Central Time Wheel (CTW) to periodically wake the +* device, perform software buzz, and refresh the supervisory services. If LVI, +* HVI, or Brown Out is not required, then use of the CTW is not required. +* Refer to the device errata for more information. +* +*******************************************************************************/ +void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource) +{ + uint8 interruptState; + + /* Save current global interrupt enable and disable it */ + interruptState = CyEnterCriticalSection(); + + + /*********************************************************************** + * The Hibernate/Sleep regulator has a settling time after a reset. + * During this time, the system ignores requests to enter Sleep and + * Hibernate modes. The holdoff delay is measured using rising edges of + * the 1 kHz ILO. + ***********************************************************************/ + if(0u == (CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_PWRUP_PULSE_Q)) + { + /* Disable hold off - no action on restore */ + CY_PM_PWRSYS_SLP_TR_REG &= CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK; + } + else + { + /* Abort, device is not ready for low power mode entry */ + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); + + return; + } + + + /*********************************************************************** + * PSoC3 < TO6: + * - Hardware buzz must be disabled before sleep mode entry. + * - Voltage supervision (HVI/LVI) requires hardware buzz, so they must + * be aslo disabled. + * + * PSoC3 >= TO6: + * - Voltage supervision (HVI/LVI) requires hardware buzz, so hardware buzz must be + * enabled before sleep mode entry and restored on wakeup. + ***********************************************************************/ + #if(CY_PSOC3) + + /* Silicon Revision ID is below TO6 */ + if(CYDEV_CHIP_REV_ACTUAL < 5u) + { + /* Hardware buzz expected to be disabled in Sleep mode */ + CYASSERT(0u == (CY_PM_PWRSYS_WAKE_TR2_REG & CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ)); + } + + + if(0u != (CY_PM_RESET_CR1_REG & (CY_PM_RESET_CR1_HVIA_EN | + CY_PM_RESET_CR1_LVIA_EN | CY_PM_RESET_CR1_LVID_EN))) + { + if(CYDEV_CHIP_REV_ACTUAL < 5u) + { + /* LVI/HVI requires hardware buzz to be enabled */ + CYASSERT(0u != 0u); + } + else + { + if (0u == (CY_PM_PWRSYS_WAKE_TR2_REG & CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ)) + { + cyPmBackup.hardwareBuzz = CY_PM_DISABLED; + CY_PM_PWRSYS_WAKE_TR2_REG |= CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ; + } + else + { + cyPmBackup.hardwareBuzz = CY_PM_ENABLED; + } + } + } + + #endif /* (CY_PSOC3) */ + + + /******************************************************************************* + * For ARM-based devices, an interrupt is required for the CPU to wake up. The + * Power Management implementation assumes that wakeup time is configured with a + * separate component (component-based wakeup time configuration) for an + * interrupt to be issued on terminal count. For more information, refer to the + * Wakeup Time Configuration section of System Reference Guide. + *******************************************************************************/ + #if(CY_PSOC5) + + /* Arguments expected to be 0 */ + CYASSERT(PM_SLEEP_TIME_NONE == wakeupTime); + + if(0u != wakeupTime) + { + /* To remove unreferenced local variable warning */ + } + + #endif /* (CY_PSOC5) */ + + + CyPmHibSlpSaveSet(); + + + #if(CY_PSOC3) + + /* CTW - save current and set new configuration */ + if((wakeupTime >= PM_SLEEP_TIME_CTW_2MS) && (wakeupTime <= PM_SLEEP_TIME_CTW_4096MS)) + { + /* Save current and set new configuration of the CTW */ + CyPmCtwSetInterval((uint8)(wakeupTime - 1u)); + + /* Include associated timer to the wakeupSource */ + wakeupSource |= PM_SLEEP_SRC_CTW; + } + + /* 1PPS - save current and set new configuration */ + if(PM_SLEEP_TIME_ONE_PPS == wakeupTime) + { + /* Save current and set new configuration of the 1PPS */ + CyPmOppsSet(); + + /* Include associated timer to the wakeupSource */ + wakeupSource |= PM_SLEEP_SRC_ONE_PPS; + } + + #endif /* (CY_PSOC3) */ + + + /* Save and set new wake up configuration */ + + /* Interrupt, PICU, I2C, Boost converter, CTW/1PPS */ + cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG; + CY_PM_WAKEUP_CFG0_REG = (uint8) (wakeupSource >> 4u); + + /* Comparators */ + cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG; + CY_PM_WAKEUP_CFG1_REG = (((uint8) wakeupSource) & CY_PM_WAKEUP_SRC_CMPS_MASK); + + /* LCD */ + cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG; + CY_PM_WAKEUP_CFG2_REG = ((uint8) ((wakeupSource >> 12u) & 0x01u)); + + + /******************************************************************* + * Do not use merge region below unless any component datasheet + * suggest to do so. + *******************************************************************/ + /* `#START CY_PM_JUST_BEFORE_SLEEP` */ + + /* `#END` */ + + + /* Last moment IMO frequency change */ + if(0u == (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK)) + { + /* IMO frequency is 12 MHz */ + cyPmBackup.imoActFreq12Mhz = CY_PM_ENABLED; + } + else + { + /* IMO frequency is not 12 MHz */ + cyPmBackup.imoActFreq12Mhz = CY_PM_DISABLED; + + /* Save IMO frequency */ + cyPmBackup.imoActFreq = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK; + + /* Set IMO frequency to 12 MHz */ + CY_PM_FASTCLK_IMO_CR_REG &= ((uint8) (~CY_PM_FASTCLK_IMO_CR_FREQ_MASK)); + } + + /* Switch to the Sleep mode */ + CY_PM_MODE_CSR_REG = ((CY_PM_MODE_CSR_REG & ((uint8)(~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_SLEEP); + + /* Recommended readback. */ + (void) CY_PM_MODE_CSR_REG; + + /* Two recommended NOPs to get into the mode. */ + CY_NOP; + CY_NOP; + + /* Execute WFI instruction (for ARM-based devices only) */ + CY_PM_WFI; + + /* Point of return from Sleep Mode */ + + /* Restore last moment IMO frequency change */ + if(CY_PM_ENABLED != cyPmBackup.imoActFreq12Mhz) + { + CY_PM_FASTCLK_IMO_CR_REG = (CY_PM_FASTCLK_IMO_CR_REG & ((uint8)(~CY_PM_FASTCLK_IMO_CR_FREQ_MASK))) | + cyPmBackup.imoActFreq; + } + + + /******************************************************************* + * Do not use merge region below unless any component datasheet + * suggest to do so. + *******************************************************************/ + /* `#START CY_PM_JUST_AFTER_WAKEUP_FROM_SLEEP` */ + + /* `#END` */ + + + /* Restore hardware configuration */ + CyPmHibSlpRestore(); + + + /* Disable hardware buzz, if it was previously enabled */ + #if(CY_PSOC3) + + if(0u != (CY_PM_RESET_CR1_REG & (CY_PM_RESET_CR1_HVIA_EN | + CY_PM_RESET_CR1_LVIA_EN | CY_PM_RESET_CR1_LVID_EN))) + { + if(CYDEV_CHIP_REV_ACTUAL >= 5u) + { + if (CY_PM_DISABLED == cyPmBackup.hardwareBuzz) + { + CY_PM_PWRSYS_WAKE_TR2_REG &= (uint8)(~CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ); + } + } + } + + #endif /* (CY_PSOC3) */ + + + /* Restore current wake up configuration */ + CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0; + CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1; + CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2; + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyPmHibernate +******************************************************************************** +* +* Summary: +* Puts the part into the Hibernate state. +* +* PSoC 3 and PSoC 5LP: +* Before switching to Hibernate, the current status of the PICU wakeup source +* bit is saved and then set. This configures the device to wake up from the +* PICU. Make sure you have at least one pin configured to generate a PICU +* interrupt. For pin Px.y, the register "PICU_INTTYPE_PICUx_INTTYPEy" controls +* the PICU behavior. In the TRM, this register is "PICU[0..15]_INTTYPE[0..7]." +* In the Pins component datasheet, this register is referred to as the IRQ +* option. Once the wakeup occurs, the PICU wakeup source bit is restored and +* the PSoC returns to the Active state. +* +* Parameters: +* None +* +* Return: +* None +* +* Reentrant: +* No +* +* Side Effects: +* Applications must wait 20 us before re-entering hibernate or sleep after +* waking up from hibernate. The 20 us allows the sleep regulator time to +* stabilize before the next hibernate / sleep event occurs. The 20 us +* requirement begins when the device wakes up. There is no hardware check that +* this requirement is met. The specified delay should be done on ISR entry. +* +* After wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin is +* instance name of the Pins component) function must be called to clear the +* latched pin events to allow proper Hibernate mode entry andd to enable +* detection of future events. +* +* The 1 kHz ILO clock is expected to be enabled for PSoC 3 and PSoC 5LP to +* measure Hibernate/Sleep regulator settling time after a reset. The holdoff +* delay is measured using rising edges of the 1 kHz ILO. +* +*******************************************************************************/ +void CyPmHibernate(void) +{ + uint8 interruptState; + + /* Save current global interrupt enable and disable it */ + interruptState = CyEnterCriticalSection(); + + /*********************************************************************** + * The Hibernate/Sleep regulator has a settling time after a reset. + * During this time, the system ignores requests to enter Sleep and + * Hibernate modes. The holdoff delay is measured using rising edges of + * the 1 kHz ILO. + ***********************************************************************/ + if(0u == (CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_PWRUP_PULSE_Q)) + { + /* Disable hold off - no action on restore */ + CY_PM_PWRSYS_SLP_TR_REG &= CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK; + } + else + { + /* Abort, device is not ready for low power mode entry */ + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); + + return; + } + + CyPmHibSaveSet(); + + + /* Save and enable only wakeup on PICU */ + cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG; + CY_PM_WAKEUP_CFG0_REG = CY_PM_WAKEUP_PICU; + + cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG; + CY_PM_WAKEUP_CFG1_REG = 0x00u; + + cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG; + CY_PM_WAKEUP_CFG2_REG = 0x00u; + + + /* Last moment IMO frequency change */ + if(0u == (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK)) + { + /* IMO frequency is 12 MHz */ + cyPmBackup.imoActFreq12Mhz = CY_PM_ENABLED; + } + else + { + /* IMO frequency is not 12 MHz */ + cyPmBackup.imoActFreq12Mhz = CY_PM_DISABLED; + + /* Save IMO frequency */ + cyPmBackup.imoActFreq = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK; + + /* Set IMO frequency to 12 MHz */ + CY_PM_FASTCLK_IMO_CR_REG &= ((uint8) (~CY_PM_FASTCLK_IMO_CR_FREQ_MASK)); + } + + + /* Switch to Hibernate Mode */ + CY_PM_MODE_CSR_REG = (CY_PM_MODE_CSR_REG & ((uint8) (~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_HIBERNATE; + + /* Recommended readback. */ + (void) CY_PM_MODE_CSR_REG; + + /* Two recommended NOPs to get into the mode. */ + CY_NOP; + CY_NOP; + + /* Execute WFI instruction (for ARM-based devices only) */ + CY_PM_WFI; + + + /* Point of return from Hibernate mode */ + + + /* Restore last moment IMO frequency change */ + if(CY_PM_ENABLED != cyPmBackup.imoActFreq12Mhz) + { + CY_PM_FASTCLK_IMO_CR_REG = (CY_PM_FASTCLK_IMO_CR_REG & ((uint8)(~CY_PM_FASTCLK_IMO_CR_FREQ_MASK))) | + cyPmBackup.imoActFreq; + } + + + /* Restore device for proper Hibernate mode exit*/ + CyPmHibRestore(); + + /* Restore current wake up configuration */ + CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0; + CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1; + CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2; + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyPmReadStatus +******************************************************************************** +* +* Summary: +* Manages the Power Manager Interrupt Status Register. This register has the +* interrupt status for the one pulse per second, central timewheel and fast +* timewheel timers. This hardware register clears on read. To allow for only +* clearing the bits of interest and preserving the other bits, this function +* uses a shadow register that retains the state. This function reads the +* status register and ORs that value with the shadow register. That is the +* value that is returned. Then the bits in the mask that are set are cleared +* from this value and written back to the shadow register. +* +* Note You must call this function within 1 ms (1 clock cycle of the ILO) +* after a CTW event has occurred. +* +* Parameters: +* mask: Bits in the shadow register to clear. +* +* Define Source +* CY_PM_FTW_INT Fast Timewheel +* CY_PM_CTW_INT Central Timewheel +* CY_PM_ONEPPS_INT One Pulse Per Second +* +* Return: +* Status. Same bits values as the mask parameter. +* +*******************************************************************************/ +uint8 CyPmReadStatus(uint8 mask) +{ + static uint8 interruptStatus; + uint8 interruptState; + uint8 tmpStatus; + + /* Enter critical section */ + interruptState = CyEnterCriticalSection(); + + /* Save value of the register, copy it and clear desired bit */ + interruptStatus |= CY_PM_INT_SR_REG; + tmpStatus = interruptStatus; + interruptStatus &= ((uint8)(~mask)); + + /* Exit critical section */ + CyExitCriticalSection(interruptState); + + return(tmpStatus); +} + + +/******************************************************************************* +* Function Name: CyPmHibSaveSet +******************************************************************************** +* +* Summary: +* Prepare device for proper Hibernate low power mode entry: +* - Disables I2C backup regulator +* - Saves ILO power down mode state and enable it +* - Saves state of 1 kHz and 100 kHz ILO and disable them +* - Disables sleep regulator and shorts vccd to vpwrsleep +* - Save LVI/HVI configuration and disable them - CyPmHviLviSaveDisable() +* - CyPmHibSlpSaveSet() function is called +* +* Parameters: +* None +* +* Return: +* None +* +* Reentrant: +* No +* +*******************************************************************************/ +static void CyPmHibSaveSet(void) +{ + /* I2C backup reg must be off when the sleep regulator is unavailable */ + if(0u != (CY_PM_PWRSYS_CR1_REG & CY_PM_PWRSYS_CR1_I2CREG_BACKUP)) + { + /*********************************************************************** + * If I2C backup regulator is enabled, all the fixed-function registers + * store their values while device is in low power mode, otherwise their + * configuration is lost. The I2C API makes a decision to restore or not + * to restore I2C registers based on this. If this regulator will be + * disabled and then enabled, I2C API will suppose that I2C block + * registers preserved their values, while this is not true. So, the + * backup regulator is disabled. The I2C sleep APIs is responsible for + * restoration. + ***********************************************************************/ + + /* Disable I2C backup register */ + CY_PM_PWRSYS_CR1_REG &= ((uint8)(~CY_PM_PWRSYS_CR1_I2CREG_BACKUP)); + } + + + /* Save current ILO power mode and ensure low power mode */ + cyPmBackup.iloPowerMode = CyILO_SetPowerMode(CY_PM_POWERDOWN_MODE); + + /* Save current 1kHz ILO enable state. Disabled automatically. */ + cyPmBackup.ilo1kEnable = (0u == (CY_PM_SLOWCLK_ILO_CR0_REG & CY_PM_ILO_CR0_EN_1K)) ? + CY_PM_DISABLED : CY_PM_ENABLED; + + /* Save current 100kHz ILO enable state. Disabled automatically. */ + cyPmBackup.ilo100kEnable = (0u == (CY_PM_SLOWCLK_ILO_CR0_REG & CY_PM_ILO_CR0_EN_100K)) ? + CY_PM_DISABLED : CY_PM_ENABLED; + + + /* Disable the sleep regulator and shorts vccd to vpwrsleep */ + if(0u == (CY_PM_PWRSYS_SLP_TR_REG & CY_PM_PWRSYS_SLP_TR_BYPASS)) + { + /* Save current bypass state */ + cyPmBackup.slpTrBypass = CY_PM_DISABLED; + CY_PM_PWRSYS_SLP_TR_REG |= CY_PM_PWRSYS_SLP_TR_BYPASS; + } + else + { + cyPmBackup.slpTrBypass = CY_PM_ENABLED; + } + + /* LPCOMPs are always enabled (even when BOTH ext_vccd=1 and ext_vcca=1)*/ + + + /*************************************************************************** + * LVI/HVI must be disabled in Hibernate + ***************************************************************************/ + + /* Save LVI/HVI configuration and disable them */ + CyPmHviLviSaveDisable(); + + + /* Make the same preparations for Hibernate and Sleep modes */ + CyPmHibSlpSaveSet(); + + + /*************************************************************************** + * Save and set power mode wakeup trim registers + ***************************************************************************/ + cyPmBackup.wakeupTrim0 = CY_PM_PWRSYS_WAKE_TR0_REG; + cyPmBackup.wakeupTrim1 = CY_PM_PWRSYS_WAKE_TR1_REG; + + CY_PM_PWRSYS_WAKE_TR0_REG = CY_PM_PWRSYS_WAKE_TR0; + CY_PM_PWRSYS_WAKE_TR1_REG = CY_PM_PWRSYS_WAKE_TR1; +} + + +/******************************************************************************* +* Function Name: CyPmHibRestore +******************************************************************************** +* +* Summary: +* Restore device for proper Hibernate mode exit: +* - Restore LVI/HVI configuration - call CyPmHviLviRestore() +* - CyPmHibSlpSaveRestore() function is called +* - Restores ILO power down mode state and enable it +* - Restores state of 1 kHz and 100 kHz ILO and disable them +* - Restores sleep regulator settings +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +static void CyPmHibRestore(void) +{ + /* Restore LVI/HVI configuration */ + CyPmHviLviRestore(); + + /* Restore the same configuration for Hibernate and Sleep modes */ + CyPmHibSlpRestore(); + + /* Restore 1kHz ILO enable state */ + if(CY_PM_ENABLED == cyPmBackup.ilo1kEnable) + { + /* Enable 1kHz ILO */ + CyILO_Start1K(); + } + + /* Restore 100kHz ILO enable state */ + if(CY_PM_ENABLED == cyPmBackup.ilo100kEnable) + { + /* Enable 100kHz ILO */ + CyILO_Start100K(); + } + + /* Restore ILO power mode */ + (void) CyILO_SetPowerMode(cyPmBackup.iloPowerMode); + + + if(CY_PM_DISABLED == cyPmBackup.slpTrBypass) + { + /* Enable the sleep regulator */ + CY_PM_PWRSYS_SLP_TR_REG &= ((uint8)(~CY_PM_PWRSYS_SLP_TR_BYPASS)); + } + + + /*************************************************************************** + * Restore power mode wakeup trim registers + ***************************************************************************/ + CY_PM_PWRSYS_WAKE_TR0_REG = cyPmBackup.wakeupTrim0; + CY_PM_PWRSYS_WAKE_TR1_REG = cyPmBackup.wakeupTrim1; +} + + +/******************************************************************************* +* Function Name: CyPmCtwSetInterval +******************************************************************************** +* +* Summary: +* Performs CTW configuration: +* - Disables CTW interrupt +* - Enables 1 kHz ILO +* - Sets new CTW interval +* +* Parameters: +* ctwInterval: the CTW interval to be set. +* +* Return: +* None +* +* Side Effects: +* Enables ILO 1 KHz clock and leaves it enabled. +* +*******************************************************************************/ +void CyPmCtwSetInterval(uint8 ctwInterval) +{ + /* Disable CTW interrupt enable */ + CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_CTW_IE)); + + /* Enable 1kHz ILO (required for CTW operation) */ + CyILO_Start1K(); + + /* Interval could be set only while CTW is disabled */ + if(0u != (CY_PM_TW_CFG2_REG & CY_PM_CTW_EN)) + { + /* Set CTW interval if needed */ + if(CY_PM_TW_CFG1_REG != ctwInterval) + { + /* Disable the CTW, set new CTW interval and enable it again */ + CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_CTW_EN)); + CY_PM_TW_CFG1_REG = ctwInterval; + CY_PM_TW_CFG2_REG |= CY_PM_CTW_EN; + } /* Required interval is already set */ + } + else + { + /* Set CTW interval if needed */ + if(CY_PM_TW_CFG1_REG != ctwInterval) + { + /* Set the new CTW interval. Could be changed if CTW is disabled */ + CY_PM_TW_CFG1_REG = ctwInterval; + } /* Required interval is already set */ + + /* Enable the CTW */ + CY_PM_TW_CFG2_REG |= CY_PM_CTW_EN; + } +} + + +/******************************************************************************* +* Function Name: CyPmOppsSet +******************************************************************************** +* +* Summary: +* Performs 1PPS configuration: +* - Starts 32 KHz XTAL +* - Disables 1PPS interupts +* - Enables 1PPS +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyPmOppsSet(void) +{ + /* Enable 32kHz XTAL if needed */ + if(0u == (CY_PM_SLOWCLK_X32_CR_REG & CY_PM_X32_CR_X32EN)) + { + /* Enable 32kHz XTAL */ + CyXTAL_32KHZ_Start(); + } + + /* Disable 1PPS interrupt enable */ + CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_1PPS_IE)); + + /* Enable 1PPS operation */ + CY_PM_TW_CFG2_REG |= CY_PM_1PPS_EN; +} + + +/******************************************************************************* +* Function Name: CyPmFtwSetInterval +******************************************************************************** +* +* Summary: +* Performs FTW configuration: +* - Disables FTW interrupt +* - Enables 100 kHz ILO +* - Sets new FTW interval. +* +* Parameters: +* ftwInterval - FTW counter interval. +* +* Return: +* None +* +* Side Effects: +* Enables ILO 100 KHz clock and leaves it enabled. +* +*******************************************************************************/ +void CyPmFtwSetInterval(uint8 ftwInterval) +{ + /* Disable FTW interrupt enable */ + CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_FTW_IE)); + + /* Enable 100kHz ILO */ + CyILO_Start100K(); + + /* Iterval could be set only while FTW is disabled */ + if(0u != (CY_PM_TW_CFG2_REG & CY_PM_FTW_EN)) + { + /* Disable FTW, set new FTW interval if needed and enable it again */ + if(CY_PM_TW_CFG0_REG != ftwInterval) + { + /* Disable the CTW, set new CTW interval and enable it again */ + CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_FTW_EN)); + CY_PM_TW_CFG0_REG = ftwInterval; + CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN; + } /* Required interval is already set */ + } + else + { + /* Set new FTW counter interval if needed. FTW is disabled. */ + if(CY_PM_TW_CFG0_REG != ftwInterval) + { + /* Set the new CTW interval. Could be changed if CTW is disabled */ + CY_PM_TW_CFG0_REG = ftwInterval; + } /* Required interval is already set */ + + /* Enable the FTW */ + CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN; + } +} + + +/******************************************************************************* +* Function Name: CyPmHibSlpSaveSet +******************************************************************************** +* +* Summary: +* This API is used for preparing device for Sleep and Hibernate low power +* modes entry: +* - Saves COMP, VIDAC, DSM and SAR routing connections (PSoC 5) +* - Saves SC/CT routing connections (PSoC 3/5/5LP) +* - Disables Serial Wire Viewer (SWV) (PSoC 3) +* - Save boost reference selection and set it to internal +* +* Parameters: +* None +* +* Return: +* None +* +* Reentrant: +* No +* +*******************************************************************************/ +static void CyPmHibSlpSaveSet(void) +{ + /* Save SC/CT routing registers */ + cyPmBackup.scctData[0u] = CY_GET_REG8(CYREG_SC0_SW0 ); + cyPmBackup.scctData[1u] = CY_GET_REG8(CYREG_SC0_SW2 ); + cyPmBackup.scctData[2u] = CY_GET_REG8(CYREG_SC0_SW3 ); + cyPmBackup.scctData[3u] = CY_GET_REG8(CYREG_SC0_SW4 ); + cyPmBackup.scctData[4u] = CY_GET_REG8(CYREG_SC0_SW6 ); + cyPmBackup.scctData[5u] = CY_GET_REG8(CYREG_SC0_SW8 ); + cyPmBackup.scctData[6u] = CY_GET_REG8(CYREG_SC0_SW10); + + cyPmBackup.scctData[7u] = CY_GET_REG8(CYREG_SC1_SW0 ); + cyPmBackup.scctData[8u] = CY_GET_REG8(CYREG_SC1_SW2 ); + cyPmBackup.scctData[9u] = CY_GET_REG8(CYREG_SC1_SW3 ); + cyPmBackup.scctData[10u] = CY_GET_REG8(CYREG_SC1_SW4 ); + cyPmBackup.scctData[11u] = CY_GET_REG8(CYREG_SC1_SW6 ); + cyPmBackup.scctData[12u] = CY_GET_REG8(CYREG_SC1_SW8 ); + cyPmBackup.scctData[13u] = CY_GET_REG8(CYREG_SC1_SW10); + + cyPmBackup.scctData[14u] = CY_GET_REG8(CYREG_SC2_SW0 ); + cyPmBackup.scctData[15u] = CY_GET_REG8(CYREG_SC2_SW2 ); + cyPmBackup.scctData[16u] = CY_GET_REG8(CYREG_SC2_SW3 ); + cyPmBackup.scctData[17u] = CY_GET_REG8(CYREG_SC2_SW4 ); + cyPmBackup.scctData[18u] = CY_GET_REG8(CYREG_SC2_SW6 ); + cyPmBackup.scctData[19u] = CY_GET_REG8(CYREG_SC2_SW8 ); + cyPmBackup.scctData[20u] = CY_GET_REG8(CYREG_SC2_SW10); + + cyPmBackup.scctData[21u] = CY_GET_REG8(CYREG_SC3_SW0 ); + cyPmBackup.scctData[22u] = CY_GET_REG8(CYREG_SC3_SW2 ); + cyPmBackup.scctData[23u] = CY_GET_REG8(CYREG_SC3_SW3 ); + cyPmBackup.scctData[24u] = CY_GET_REG8(CYREG_SC3_SW4 ); + cyPmBackup.scctData[25u] = CY_GET_REG8(CYREG_SC3_SW6 ); + cyPmBackup.scctData[26u] = CY_GET_REG8(CYREG_SC3_SW8 ); + cyPmBackup.scctData[27u] = CY_GET_REG8(CYREG_SC3_SW10); + + CY_SET_REG8(CYREG_SC0_SW0 , 0u); + CY_SET_REG8(CYREG_SC0_SW2 , 0u); + CY_SET_REG8(CYREG_SC0_SW3 , 0u); + CY_SET_REG8(CYREG_SC0_SW4 , 0u); + CY_SET_REG8(CYREG_SC0_SW6 , 0u); + CY_SET_REG8(CYREG_SC0_SW8 , 0u); + CY_SET_REG8(CYREG_SC0_SW10, 0u); + + CY_SET_REG8(CYREG_SC1_SW0 , 0u); + CY_SET_REG8(CYREG_SC1_SW2 , 0u); + CY_SET_REG8(CYREG_SC1_SW3 , 0u); + CY_SET_REG8(CYREG_SC1_SW4 , 0u); + CY_SET_REG8(CYREG_SC1_SW6 , 0u); + CY_SET_REG8(CYREG_SC1_SW8 , 0u); + CY_SET_REG8(CYREG_SC1_SW10, 0u); + + CY_SET_REG8(CYREG_SC2_SW0 , 0u); + CY_SET_REG8(CYREG_SC2_SW2 , 0u); + CY_SET_REG8(CYREG_SC2_SW3 , 0u); + CY_SET_REG8(CYREG_SC2_SW4 , 0u); + CY_SET_REG8(CYREG_SC2_SW6 , 0u); + CY_SET_REG8(CYREG_SC2_SW8 , 0u); + CY_SET_REG8(CYREG_SC2_SW10, 0u); + + CY_SET_REG8(CYREG_SC3_SW0 , 0u); + CY_SET_REG8(CYREG_SC3_SW2 , 0u); + CY_SET_REG8(CYREG_SC3_SW3 , 0u); + CY_SET_REG8(CYREG_SC3_SW4 , 0u); + CY_SET_REG8(CYREG_SC3_SW6 , 0u); + CY_SET_REG8(CYREG_SC3_SW8 , 0u); + CY_SET_REG8(CYREG_SC3_SW10, 0u); + + + #if(CY_PSOC3) + + /* Serial Wire Viewer (SWV) workaround */ + + /* Disable SWV before entering low power mode */ + if(0u != (CY_PM_MLOGIC_DBG_REG & CY_PM_MLOGIC_DBG_SWV_CLK_EN)) + { + /* Save SWV clock enabled state */ + cyPmBackup.swvClkEnabled = CY_PM_ENABLED; + + /* Save current ports drive mode settings */ + cyPmBackup.prt1Dm = CY_PM_PRT1_PC3_REG & ((uint8)(~CY_PM_PRT1_PC3_DM_MASK)); + + /* Set drive mode to strong output */ + CY_PM_PRT1_PC3_REG = (CY_PM_PRT1_PC3_REG & CY_PM_PRT1_PC3_DM_MASK) | + CY_PM_PRT1_PC3_DM_STRONG; + + /* Disable SWV clocks */ + CY_PM_MLOGIC_DBG_REG &= ((uint8)(~CY_PM_MLOGIC_DBG_SWV_CLK_EN)); + } + else + { + /* Save SWV clock disabled state */ + cyPmBackup.swvClkEnabled = CY_PM_DISABLED; + } + + #endif /* (CY_PSOC3) */ + + + /*************************************************************************** + * Save boost reference and set it to boost's internal by clearing the bit. + * External (chip bandgap) reference is not available in Sleep and Hibernate. + ***************************************************************************/ + if(0u != (CY_PM_BOOST_CR2_REG & CY_PM_BOOST_CR2_EREFSEL_EXT)) + { + cyPmBackup.boostRefExt = CY_PM_ENABLED; + CY_PM_BOOST_CR2_REG &= ((uint8)(~CY_PM_BOOST_CR2_EREFSEL_EXT)); + } + else + { + cyPmBackup.boostRefExt = CY_PM_DISABLED; + } +} + + +/******************************************************************************* +* Function Name: CyPmHibSlpRestore +******************************************************************************** +* +* Summary: +* This API is used for restoring device configurations after wakeup from Sleep +* and Hibernate low power modes: +* - Restores SC/CT routing connections +* - Restores enable state of Serial Wire Viewer (SWV) (PSoC 3) +* - Restore boost reference selection +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +static void CyPmHibSlpRestore(void) +{ + /* Restore SC/CT routing registers */ + CY_SET_REG8(CYREG_SC0_SW0 , cyPmBackup.scctData[0u] ); + CY_SET_REG8(CYREG_SC0_SW2 , cyPmBackup.scctData[1u] ); + CY_SET_REG8(CYREG_SC0_SW3 , cyPmBackup.scctData[2u] ); + CY_SET_REG8(CYREG_SC0_SW4 , cyPmBackup.scctData[3u] ); + CY_SET_REG8(CYREG_SC0_SW6 , cyPmBackup.scctData[4u] ); + CY_SET_REG8(CYREG_SC0_SW8 , cyPmBackup.scctData[5u] ); + CY_SET_REG8(CYREG_SC0_SW10, cyPmBackup.scctData[6u] ); + + CY_SET_REG8(CYREG_SC1_SW0 , cyPmBackup.scctData[7u] ); + CY_SET_REG8(CYREG_SC1_SW2 , cyPmBackup.scctData[8u] ); + CY_SET_REG8(CYREG_SC1_SW3 , cyPmBackup.scctData[9u] ); + CY_SET_REG8(CYREG_SC1_SW4 , cyPmBackup.scctData[10u]); + CY_SET_REG8(CYREG_SC1_SW6 , cyPmBackup.scctData[11u]); + CY_SET_REG8(CYREG_SC1_SW8 , cyPmBackup.scctData[12u]); + CY_SET_REG8(CYREG_SC1_SW10, cyPmBackup.scctData[13u]); + + CY_SET_REG8(CYREG_SC2_SW0 , cyPmBackup.scctData[14u]); + CY_SET_REG8(CYREG_SC2_SW2 , cyPmBackup.scctData[15u]); + CY_SET_REG8(CYREG_SC2_SW3 , cyPmBackup.scctData[16u]); + CY_SET_REG8(CYREG_SC2_SW4 , cyPmBackup.scctData[17u]); + CY_SET_REG8(CYREG_SC2_SW6 , cyPmBackup.scctData[18u]); + CY_SET_REG8(CYREG_SC2_SW8 , cyPmBackup.scctData[19u]); + CY_SET_REG8(CYREG_SC2_SW10, cyPmBackup.scctData[20u]); + + CY_SET_REG8(CYREG_SC3_SW0 , cyPmBackup.scctData[21u]); + CY_SET_REG8(CYREG_SC3_SW2 , cyPmBackup.scctData[22u]); + CY_SET_REG8(CYREG_SC3_SW3 , cyPmBackup.scctData[23u]); + CY_SET_REG8(CYREG_SC3_SW4 , cyPmBackup.scctData[24u]); + CY_SET_REG8(CYREG_SC3_SW6 , cyPmBackup.scctData[25u]); + CY_SET_REG8(CYREG_SC3_SW8 , cyPmBackup.scctData[26u]); + CY_SET_REG8(CYREG_SC3_SW10, cyPmBackup.scctData[27u]); + + + #if(CY_PSOC3) + + /* Serial Wire Viewer (SWV) workaround */ + if(CY_PM_ENABLED == cyPmBackup.swvClkEnabled) + { + /* Restore ports drive mode */ + CY_PM_PRT1_PC3_REG = (CY_PM_PRT1_PC3_REG & CY_PM_PRT1_PC3_DM_MASK) | + cyPmBackup.prt1Dm; + + /* Enable SWV clocks */ + CY_PM_MLOGIC_DBG_REG |= CY_PM_MLOGIC_DBG_SWV_CLK_EN; + } + + #endif /* (CY_PSOC3) */ + + + /* Restore boost reference */ + if(CY_PM_ENABLED == cyPmBackup.boostRefExt) + { + CY_PM_BOOST_CR2_REG |= CY_PM_BOOST_CR2_EREFSEL_EXT; + } +} + + +/******************************************************************************* +* Function Name: CyPmHviLviSaveDisable +******************************************************************************** +* +* Summary: +* Saves analog and digital LVI and HVI configuration and disables them. +* +* Parameters: +* None +* +* Return: +* None +* +* Reentrant: +* No +* +*******************************************************************************/ +static void CyPmHviLviSaveDisable(void) +{ + if(0u != (CY_VD_LVI_HVI_CONTROL_REG & CY_VD_LVID_EN)) + { + cyPmBackup.lvidEn = CY_PM_ENABLED; + cyPmBackup.lvidTrip = CY_VD_LVI_TRIP_REG & CY_VD_LVI_TRIP_LVID_MASK; + + /* Save state of reset device at a specified Vddd threshold */ + cyPmBackup.lvidRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESD_EN)) ? \ + CY_PM_DISABLED : CY_PM_ENABLED; + + CyVdLvDigitDisable(); + } + else + { + cyPmBackup.lvidEn = CY_PM_DISABLED; + } + + if(0u != (CY_VD_LVI_HVI_CONTROL_REG & CY_VD_LVIA_EN)) + { + cyPmBackup.lviaEn = CY_PM_ENABLED; + cyPmBackup.lviaTrip = CY_VD_LVI_TRIP_REG >> 4u; + + /* Save state of reset device at a specified Vdda threshold */ + cyPmBackup.lviaRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESA_EN)) ? \ + CY_PM_DISABLED : CY_PM_ENABLED; + + CyVdLvAnalogDisable(); + } + else + { + cyPmBackup.lviaEn = CY_PM_DISABLED; + } + + if(0u != (CY_VD_LVI_HVI_CONTROL_REG & CY_VD_HVIA_EN)) + { + cyPmBackup.hviaEn = CY_PM_ENABLED; + CyVdHvAnalogDisable(); + } + else + { + cyPmBackup.hviaEn = CY_PM_DISABLED; + } +} + + +/******************************************************************************* +* Function Name: CyPmHviLviRestore +******************************************************************************** +* +* Summary: +* Restores analog and digital LVI and HVI configuration. +* +* Parameters: +* None +* +* Return: +* None +* +* Reentrant: +* No +* +*******************************************************************************/ +static void CyPmHviLviRestore(void) +{ + /* Restore LVI/HVI configuration */ + if(CY_PM_ENABLED == cyPmBackup.lvidEn) + { + CyVdLvDigitEnable(cyPmBackup.lvidRst, cyPmBackup.lvidTrip); + } + + if(CY_PM_ENABLED == cyPmBackup.lviaEn) + { + CyVdLvAnalogEnable(cyPmBackup.lviaRst, cyPmBackup.lviaTrip); + } + + if(CY_PM_ENABLED == cyPmBackup.hviaEn) + { + CyVdHvAnalogEnable(); + } +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyPm.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyPm.h new file mode 100644 index 00000000..327908be --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyPm.h @@ -0,0 +1,635 @@ +/******************************************************************************* +* File Name: cyPm.h +* Version 4.0 +* +* Description: +* Provides the function definitions for the power management API. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYPM_H) +#define CY_BOOT_CYPM_H + +#include "cytypes.h" /* Register access API */ +#include "cydevice_trm.h" /* Registers addresses */ +#include "cyfitter.h" /* Comparators placement */ +#include "CyLib.h" /* Clock API */ +#include "CyFlash.h" /* Flash API - CyFlash_SetWaitCycles() */ + + +/*************************************** +* Function Prototypes +***************************************/ +void CyPmSaveClocks(void) ; +void CyPmRestoreClocks(void) ; +void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource) ; +void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource) ; +void CyPmHibernate(void) ; + +uint8 CyPmReadStatus(uint8 mask) ; + +/* Internal APIs and are not meant to be called directly by the user */ +void CyPmCtwSetInterval(uint8 ctwInterval) ; +void CyPmFtwSetInterval(uint8 ftwInterval) ; +void CyPmOppsSet(void) ; + + +/*************************************** +* API Constants +***************************************/ + +#define PM_SLEEP_SRC_NONE (0x0000u) +#define PM_SLEEP_TIME_NONE (0x00u) +#define PM_ALT_ACT_SRC_NONE (0x0000u) +#define PM_ALT_ACT_TIME_NONE (0x0000u) + +#if(CY_PSOC3) + + /* Wake up time for the Sleep mode */ + #define PM_SLEEP_TIME_ONE_PPS (0x01u) + #define PM_SLEEP_TIME_CTW_2MS (0x02u) + #define PM_SLEEP_TIME_CTW_4MS (0x03u) + #define PM_SLEEP_TIME_CTW_8MS (0x04u) + #define PM_SLEEP_TIME_CTW_16MS (0x05u) + #define PM_SLEEP_TIME_CTW_32MS (0x06u) + #define PM_SLEEP_TIME_CTW_64MS (0x07u) + #define PM_SLEEP_TIME_CTW_128MS (0x08u) + #define PM_SLEEP_TIME_CTW_256MS (0x09u) + #define PM_SLEEP_TIME_CTW_512MS (0x0Au) + #define PM_SLEEP_TIME_CTW_1024MS (0x0Bu) + #define PM_SLEEP_TIME_CTW_2048MS (0x0Cu) + #define PM_SLEEP_TIME_CTW_4096MS (0x0Du) + + /* Difference between parameter's value and register's one */ + #define CY_PM_FTW_INTERVAL_SHIFT (0x000Eu) + + /* Wake up time for the Alternate Active mode */ + #define PM_ALT_ACT_TIME_ONE_PPS (0x0001u) + #define PM_ALT_ACT_TIME_CTW_2MS (0x0002u) + #define PM_ALT_ACT_TIME_CTW_4MS (0x0003u) + #define PM_ALT_ACT_TIME_CTW_8MS (0x0004u) + #define PM_ALT_ACT_TIME_CTW_16MS (0x0005u) + #define PM_ALT_ACT_TIME_CTW_32MS (0x0006u) + #define PM_ALT_ACT_TIME_CTW_64MS (0x0007u) + #define PM_ALT_ACT_TIME_CTW_128MS (0x0008u) + #define PM_ALT_ACT_TIME_CTW_256MS (0x0009u) + #define PM_ALT_ACT_TIME_CTW_512MS (0x000Au) + #define PM_ALT_ACT_TIME_CTW_1024MS (0x000Bu) + #define PM_ALT_ACT_TIME_CTW_2048MS (0x000Cu) + #define PM_ALT_ACT_TIME_CTW_4096MS (0x000Du) + #define PM_ALT_ACT_TIME_FTW(x) ((x) + CY_PM_FTW_INTERVAL_SHIFT) + +#endif /* (CY_PSOC3) */ + + +/* Wake up sources for the Sleep mode */ +#define PM_SLEEP_SRC_COMPARATOR0 (0x0001u) +#define PM_SLEEP_SRC_COMPARATOR1 (0x0002u) +#define PM_SLEEP_SRC_COMPARATOR2 (0x0004u) +#define PM_SLEEP_SRC_COMPARATOR3 (0x0008u) +#define PM_SLEEP_SRC_PICU (0x0040u) +#define PM_SLEEP_SRC_I2C (0x0080u) +#define PM_SLEEP_SRC_BOOSTCONVERTER (0x0200u) +#define PM_SLEEP_SRC_VD (0x0400u) +#define PM_SLEEP_SRC_CTW (0x0800u) +#define PM_SLEEP_SRC_ONE_PPS (0x0800u) +#define PM_SLEEP_SRC_LCD (0x1000u) + +/* Wake up sources for the Alternate Active mode */ +#define PM_ALT_ACT_SRC_COMPARATOR0 (0x0001u) +#define PM_ALT_ACT_SRC_COMPARATOR1 (0x0002u) +#define PM_ALT_ACT_SRC_COMPARATOR2 (0x0004u) +#define PM_ALT_ACT_SRC_COMPARATOR3 (0x0008u) +#define PM_ALT_ACT_SRC_INTERRUPT (0x0010u) +#define PM_ALT_ACT_SRC_PICU (0x0040u) +#define PM_ALT_ACT_SRC_I2C (0x0080u) +#define PM_ALT_ACT_SRC_BOOSTCONVERTER (0x0200u) +#define PM_ALT_ACT_SRC_FTW (0x0400u) +#define PM_ALT_ACT_SRC_VD (0x0400u) +#define PM_ALT_ACT_SRC_CTW (0x0800u) +#define PM_ALT_ACT_SRC_ONE_PPS (0x0800u) +#define PM_ALT_ACT_SRC_LCD (0x1000u) + + +#define CY_PM_WAKEUP_PICU (0x04u) +#define CY_PM_IMO_NO_WAIT_TO_SETTLE (0x00u) +#define CY_PM_POWERDOWN_MODE (0x01u) +#define CY_PM_HIGHPOWER_MODE (0x00u) /* Deprecated */ +#define CY_PM_ENABLED (0x01u) +#define CY_PM_DISABLED (0x00u) + +/* No wait for PLL to stabilize, used in CyPLL_OUT_Start() */ +#define CY_PM_PLL_OUT_NO_WAIT (0u) + +/* No wait for MHZ XTAL to stabilize, used in CyXTAL_Start() */ +#define CY_PM_XTAL_MHZ_NO_WAIT (0u) + +#define CY_PM_WAIT_200_US (200u) +#define CY_PM_WAIT_250_US (250u) +#define CY_PM_WAIT_20_US (20u) + +#define CY_PM_FREQ_3MHZ (3u) +#define CY_PM_FREQ_12MHZ (12u) +#define CY_PM_FREQ_48MHZ (48u) + + +#define CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US (5u) + + +/* Delay line bandgap current settling time starting from a wakeup event */ +#define CY_PM_CLK_DELAY_BANDGAP_SETTLE_US (50u) + +/* Delay line internal bias settling */ +#define CY_PM_CLK_DELAY_BIAS_SETTLE_US (25u) + + +/* Max flash wait cycles for each device */ +#if(CY_PSOC3) + #define CY_PM_MAX_FLASH_WAIT_CYCLES (45u) +#endif /* (CY_PSOC3) */ + +#if(CY_PSOC5) + #define CY_PM_MAX_FLASH_WAIT_CYCLES (55u) +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* This marco is used to obtain the CPU frequency in MHz. It should be only used +* when the clock distribution system is prepared for the low power mode entry. +* This macro is silicon dependent as PSoC 5 devices have no CPU clock divider +* and PSoC 3 devices have different placement of the CPU clock divider register +* bitfield. +*******************************************************************************/ +#if(CY_PSOC3) + #define CY_PM_GET_CPU_FREQ_MHZ \ + ((uint32)(cyPmImoFreqReg2Mhz[CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK]) / \ + ((uint8)(((CY_PM_CLKDIST_MSTR1_REG & CY_PM_CLKDIST_CPU_DIV_MASK) >> 4u) + 1u))) +#endif /* (CY_PSOC3) */ + +#if(CY_PSOC5) + + /* The CPU clock is directly derived from bus clock */ + #define CY_PM_GET_CPU_FREQ_MHZ (cyPmImoFreqReg2Mhz[CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK]) + +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* The low power mode entry is different for PSoC 3 and PSoC 5 devices. The low +* power modes in PSoC 5 devices are invoked by Wait-For-Interrupt (WFI) +* instruction. The ARM compilers has __wfi() instristic that inserts a WFI +* instruction into the instruction stream generated by the compiler. The GCC +* compiler has to execute assembly language instruction. +*******************************************************************************/ +#if(CY_PSOC5) + + #if defined(__ARMCC_VERSION) /* Instristic for Keil compilers */ + #define CY_PM_WFI __wfi() + #else /* ASM for GCC & IAR */ + #define CY_PM_WFI asm volatile ("WFI \n") + #endif /* (__ARMCC_VERSION) */ + +#else + + #define CY_PM_WFI CY_NOP + +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* Macro for the wakeupTime argument of the CyPmAltAct() function. The FTW should +* be programmed manually for non PSoC 3 devices. +*******************************************************************************/ +#if(CY_PSOC3) + + #define PM_ALT_ACT_FTW_INTERVAL(x) ((uint8)((x) - CY_PM_FTW_INTERVAL_SHIFT)) + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* This macro defines the IMO frequency that will be set by CyPmSaveClocks() +* function based on Enable Fast IMO during Startup option from the DWR file. +* The CyPmSleep()/CyPmHibernate() will set IMO 12 MHz just before entering +* low power mode and restore IMO back to the value set by CyPmSaveClocks() +* immediately on wakeup. +*******************************************************************************/ + +/* Enable Fast IMO during Startup - enabled */ +#if(1u == CYDEV_CONFIGURATION_IMOENABLED) + + /* IMO will be configured to 48 MHz */ + #define CY_PM_IMO_FREQ_LPM (CY_IMO_FREQ_48MHZ) + +#else + + /* IMO will be configured to 12 MHz */ + #define CY_PM_IMO_FREQ_LPM (CY_IMO_FREQ_12MHZ) + +#endif /* (1u == CYDEV_CONFIGURATION_IMOENABLED) */ + + +typedef struct cyPmClockBackupStruct +{ + /* CyPmSaveClocks()/CyPmRestoreClocks() */ + uint8 enClkA; /* Analog clocks enable */ + uint8 enClkD; /* Digital clocks enable */ + uint8 masterClkSrc; /* The Master clock source */ + uint8 imoFreq; /* IMO frequency (reg's value) */ + uint8 imoUsbClk; /* IMO USB CLK (reg's value) */ + uint8 flashWaitCycles; /* Flash wait cycles */ + uint8 imoEnable; /* IMO enable in Active mode */ + uint8 imoClkSrc; /* The IMO output */ + uint8 clkImoSrc; + uint8 imo2x; /* IMO doubler enable state */ + uint8 clkSyncDiv; /* Master clk divider */ + uint16 clkBusDiv; /* The clk_bus divider */ + uint8 pllEnableState; /* PLL enable state */ + uint8 xmhzEnableState; /* XM HZ enable state */ + uint8 clkDistDelay; /* Delay for clk_bus and ACLKs */ + +} CY_PM_CLOCK_BACKUP_STRUCT; + + +typedef struct cyPmBackupStruct +{ + uint8 iloPowerMode; /* ILO power mode */ + uint8 ilo1kEnable; /* ILO 1K enable state */ + uint8 ilo100kEnable; /* ILO 100K enable state */ + + uint8 slpTrBypass; /* Sleep Trim Bypass */ + + #if(CY_PSOC3) + + uint8 swvClkEnabled; /* SWV clock enable state */ + uint8 prt1Dm; /* Ports drive mode configuration */ + uint8 hardwareBuzz; + + #endif /* (CY_PSOC3) */ + + uint8 wakeupCfg0; /* Wake up configuration 0 */ + uint8 wakeupCfg1; /* Wake up configuration 1 */ + uint8 wakeupCfg2; /* Wake up configuration 2 */ + + uint8 wakeupTrim0; + uint8 wakeupTrim1; + + uint8 scctData[28u]; /* SC/CT routing registers */ + + /* CyPmHviLviSaveDisable()/CyPmHviLviRestore() */ + uint8 lvidEn; + uint8 lvidTrip; + uint8 lviaEn; + uint8 lviaTrip; + uint8 hviaEn; + uint8 lvidRst; + uint8 lviaRst; + + uint8 imoActFreq; /* Last moment IMO change */ + uint8 imoActFreq12Mhz; /* 12 MHz or not */ + + uint8 boostRefExt; /* Boost reference selection */ + +} CY_PM_BACKUP_STRUCT; + + +/*************************************** +* Registers +***************************************/ + +/* Power Mode Wakeup Trim Register 1 */ +#define CY_PM_PWRSYS_WAKE_TR1_REG (* (reg8 *) CYREG_PWRSYS_WAKE_TR1 ) +#define CY_PM_PWRSYS_WAKE_TR1_PTR ( (reg8 *) CYREG_PWRSYS_WAKE_TR1 ) + +/* Master clock Divider Value Register */ +#define CY_PM_CLKDIST_MSTR0_REG (* (reg8 *) CYREG_CLKDIST_MSTR0 ) +#define CY_PM_CLKDIST_MSTR0_PTR ( (reg8 *) CYREG_CLKDIST_MSTR0 ) + +/* Master Clock Configuration Register/CPU Divider Value */ +#define CY_PM_CLKDIST_MSTR1_REG (* (reg8 *) CYREG_CLKDIST_MSTR1 ) +#define CY_PM_CLKDIST_MSTR1_PTR ( (reg8 *) CYREG_CLKDIST_MSTR1 ) + +/* Clock distribution configuration Register */ +#define CY_PM_CLKDIST_CR_REG (* (reg8 *) CYREG_CLKDIST_CR ) +#define CY_PM_CLKDIST_CR_PTR ( (reg8 *) CYREG_CLKDIST_CR ) + +/* CLK_BUS LSB Divider Value Register */ +#define CY_PM_CLK_BUS_LSB_DIV_REG (* (reg8 *) CYREG_CLKDIST_BCFG0 ) +#define CY_PM_CLK_BUS_LSB_DIV_PTR ( (reg8 *) CYREG_CLKDIST_BCFG0 ) + +/* CLK_BUS MSB Divider Value Register */ +#define CY_PM_CLK_BUS_MSB_DIV_REG (* (reg8 *) CYREG_CLKDIST_BCFG1 ) +#define CY_PM_CLK_BUS_MSB_DIV_PTR ( (reg8 *) CYREG_CLKDIST_BCFG1 ) + +/* CLK_BUS Configuration Register */ +#define CLK_BUS_CFG_REG (* (reg8 *) CYREG_CLKDIST_BCFG2 ) +#define CLK_BUS_CFG_PTR ( (reg8 *) CYREG_CLKDIST_BCFG2 ) + +/* Power Mode Control/Status Register */ +#define CY_PM_MODE_CSR_REG (* (reg8 *) CYREG_PM_MODE_CSR ) +#define CY_PM_MODE_CSR_PTR ( (reg8 *) CYREG_PM_MODE_CSR ) + +/* Power System Control Register 1 */ +#define CY_PM_PWRSYS_CR1_REG (* (reg8 *) CYREG_PWRSYS_CR1 ) +#define CY_PM_PWRSYS_CR1_PTR ( (reg8 *) CYREG_PWRSYS_CR1 ) + +/* Power System Control Register 0 */ +#define CY_PM_PWRSYS_CR0_REG (* (reg8 *) CYREG_PWRSYS_CR0 ) +#define CY_PM_PWRSYS_CR0_PTR ( (reg8 *) CYREG_PWRSYS_CR0 ) + +/* Internal Low-speed Oscillator Control Register 0 */ +#define CY_PM_SLOWCLK_ILO_CR0_REG (* (reg8 *) CYREG_SLOWCLK_ILO_CR0 ) +#define CY_PM_SLOWCLK_ILO_CR0_PTR ( (reg8 *) CYREG_SLOWCLK_ILO_CR0 ) + +/* External 32kHz Crystal Oscillator Control Register */ +#define CY_PM_SLOWCLK_X32_CR_REG (* (reg8 *) CYREG_SLOWCLK_X32_CR ) +#define CY_PM_SLOWCLK_X32_CR_PTR ( (reg8 *) CYREG_SLOWCLK_X32_CR ) + +#if(CY_PSOC3) + + /* MLOGIC Debug Register */ + #define CY_PM_MLOGIC_DBG_REG (* (reg8 *) CYREG_MLOGIC_DEBUG ) + #define CY_PM_MLOGIC_DBG_PTR ( (reg8 *) CYREG_MLOGIC_DEBUG ) + + /* Port Pin Configuration Register */ + #define CY_PM_PRT1_PC3_REG (* (reg8 *) CYREG_PRT1_PC3 ) + #define CY_PM_PRT1_PC3_PTR ( (reg8 *) CYREG_PRT1_PC3 ) + +#endif /* (CY_PSOC3) */ + + +/* Sleep Regulator Trim Register */ +#define CY_PM_PWRSYS_SLP_TR_REG (* (reg8 *) CYREG_PWRSYS_SLP_TR ) +#define CY_PM_PWRSYS_SLP_TR_PTR ( (reg8 *) CYREG_PWRSYS_SLP_TR ) + + +/* Reset System Control Register */ +#define CY_PM_RESET_CR1_REG (* (reg8 *) CYREG_RESET_CR1 ) +#define CY_PM_RESET_CR1_PTR ( (reg8 *) CYREG_RESET_CR1 ) + +/* Power Mode Wakeup Trim Register 0 */ +#define CY_PM_PWRSYS_WAKE_TR0_REG (* (reg8 *) CYREG_PWRSYS_WAKE_TR0 ) +#define CY_PM_PWRSYS_WAKE_TR0_PTR ( (reg8 *) CYREG_PWRSYS_WAKE_TR0 ) + +#if(CY_PSOC3) + + /* Power Mode Wakeup Trim Register 2 */ + #define CY_PM_PWRSYS_WAKE_TR2_REG (* (reg8 *) CYREG_PWRSYS_WAKE_TR2 ) + #define CY_PM_PWRSYS_WAKE_TR2_PTR ( (reg8 *) CYREG_PWRSYS_WAKE_TR2 ) + +#endif /* (CY_PSOC3) */ + +/* Power Manager Interrupt Status Register */ +#define CY_PM_INT_SR_REG (* (reg8 *) CYREG_PM_INT_SR ) +#define CY_PM_INT_SR_PTR ( (reg8 *) CYREG_PM_INT_SR ) + +/* Active Power Mode Configuration Register 0 */ +#define CY_PM_ACT_CFG0_REG (* (reg8 *) CYREG_PM_ACT_CFG0 ) +#define CY_PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0 ) + +/* Active Power Mode Configuration Register 1 */ +#define CY_PM_ACT_CFG1_REG (* (reg8 *) CYREG_PM_ACT_CFG1 ) +#define CY_PM_ACT_CFG1_PTR ( (reg8 *) CYREG_PM_ACT_CFG1 ) + +/* Active Power Mode Configuration Register 2 */ +#define CY_PM_ACT_CFG2_REG (* (reg8 *) CYREG_PM_ACT_CFG2 ) +#define CY_PM_ACT_CFG2_PTR ( (reg8 *) CYREG_PM_ACT_CFG2 ) + +/* Boost Control 1 */ +#define CY_PM_BOOST_CR1_REG (* (reg8 *) CYREG_BOOST_CR1 ) +#define CY_PM_BOOST_CR1_PTR ( (reg8 *) CYREG_BOOST_CR1 ) + +/* Timewheel Configuration Register 0 */ +#define CY_PM_TW_CFG0_REG (* (reg8 *) CYREG_PM_TW_CFG0 ) +#define CY_PM_TW_CFG0_PTR ( (reg8 *) CYREG_PM_TW_CFG0 ) + +/* Timewheel Configuration Register 1 */ +#define CY_PM_TW_CFG1_REG (* (reg8 *) CYREG_PM_TW_CFG1 ) +#define CY_PM_TW_CFG1_PTR ( (reg8 *) CYREG_PM_TW_CFG1 ) + +/* Timewheel Configuration Register 2 */ +#define CY_PM_TW_CFG2_REG (* (reg8 *) CYREG_PM_TW_CFG2 ) +#define CY_PM_TW_CFG2_PTR ( (reg8 *) CYREG_PM_TW_CFG2 ) + +/* PLL Status Register */ +#define CY_PM_FASTCLK_PLL_SR_REG (*(reg8 *) CYREG_FASTCLK_PLL_SR ) +#define CY_PM_FASTCLK_PLL_SR_PTR ( (reg8 *) CYREG_FASTCLK_PLL_SR ) + +/* Internal Main Oscillator Control Register */ +#define CY_PM_FASTCLK_IMO_CR_REG (* (reg8 *) CYREG_FASTCLK_IMO_CR ) +#define CY_PM_FASTCLK_IMO_CR_PTR ( (reg8 *) CYREG_FASTCLK_IMO_CR ) + +/* PLL Configuration Register */ +#define CY_PM_FASTCLK_PLL_CFG0_REG (* (reg8 *) CYREG_FASTCLK_PLL_CFG0 ) +#define CY_PM_FASTCLK_PLL_CFG0_PTR ( (reg8 *) CYREG_FASTCLK_PLL_CFG0 ) + +/* External 4-33 MHz Crystal Oscillator Status and Control Register */ +#define CY_PM_FASTCLK_XMHZ_CSR_REG (* (reg8 *) CYREG_FASTCLK_XMHZ_CSR ) +#define CY_PM_FASTCLK_XMHZ_CSR_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CSR ) + +/* Delay block Configuration Register */ +#define CY_PM_CLKDIST_DELAY_REG (* (reg8 *) CYREG_CLKDIST_DLY1 ) +#define CY_PM_CLKDIST_DELAY_PTR ( (reg8 *) CYREG_CLKDIST_DLY1 ) + + +#if(CY_PSOC3) + + /* Cache Control Register */ + #define CY_PM_CACHE_CR_REG (* (reg8 *) CYREG_CACHE_CR ) + #define CY_PM_CACHE_CR_PTR ( (reg8 *) CYREG_CACHE_CR ) + +#else /* Device is PSoC 5 */ + + /* Cache Control Register */ + #define CY_PM_CACHE_CR_REG (* (reg8 *) CYREG_CACHE_CC_CTL ) + #define CY_PM_CACHE_CR_PTR ( (reg8 *) CYREG_CACHE_CC_CTL ) + +#endif /* (CY_PSOC3) */ + + +/* Power Mode Wakeup Mask Configuration Register 0 */ +#define CY_PM_WAKEUP_CFG0_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG0 ) +#define CY_PM_WAKEUP_CFG0_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG0 ) + +/* Power Mode Wakeup Mask Configuration Register 1 */ +#define CY_PM_WAKEUP_CFG1_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG1 ) +#define CY_PM_WAKEUP_CFG1_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG1 ) + +/* Power Mode Wakeup Mask Configuration Register 2 */ +#define CY_PM_WAKEUP_CFG2_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG2 ) +#define CY_PM_WAKEUP_CFG2_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG2 ) + +/* Boost Control 2 */ +#define CY_PM_BOOST_CR2_REG (* (reg8 *) CYREG_BOOST_CR2 ) +#define CY_PM_BOOST_CR2_PTR ( (reg8 *) CYREG_BOOST_CR2 ) + + +/*************************************** +* Register Constants +***************************************/ + +/* Internal Main Oscillator Control Register */ + +#define CY_PM_FASTCLK_IMO_CR_FREQ_MASK (0x07u) /* IMO frequency mask */ +#define CY_PM_FASTCLK_IMO_CR_FREQ_12MHZ (0x00u) /* IMO frequency 12 MHz */ +#define CY_PM_FASTCLK_IMO_CR_F2XON (0x10u) /* IMO doubler enable */ +#define CY_PM_FASTCLK_IMO_CR_USB (0x40u) /* IMO is in USB mode */ + +#define CY_PM_MASTER_CLK_SRC_IMO (0u) +#define CY_PM_MASTER_CLK_SRC_PLL (1u) +#define CY_PM_MASTER_CLK_SRC_XTAL (2u) +#define CY_PM_MASTER_CLK_SRC_DSI (3u) +#define CY_PM_MASTER_CLK_SRC_MASK (3u) + +#define CY_PM_PLL_CFG0_ENABLE (0x01u) /* PLL enable */ +#define CY_PM_PLL_STATUS_LOCK (0x01u) /* PLL Lock Status */ +#define CY_PM_XMHZ_CSR_ENABLE (0x01u) /* Enable X MHz OSC */ +#define CY_PM_XMHZ_CSR_XERR (0x80u) /* High indicates failure */ +#define CY_PM_BOOST_ENABLE (0x08u) /* Boost enable */ +#define CY_PM_ILO_CR0_EN_1K (0x02u) /* Enable 1kHz ILO */ +#define CY_PM_ILO_CR0_EN_100K (0x04u) /* Enable 100kHz ILO */ +#define CY_PM_ILO_CR0_PD_MODE (0x10u) /* Power down mode for ILO*/ +#define CY_PM_X32_CR_X32EN (0x01u) /* Enable 32kHz OSC */ + +#define CY_PM_CTW_IE (0x08u) /* CTW interrupt enable */ +#define CY_PM_CTW_EN (0x04u) /* CTW enable */ +#define CY_PM_FTW_IE (0x02u) /* FTW interrupt enable */ +#define CY_PM_FTW_EN (0x01u) /* FTW enable */ +#define CY_PM_1PPS_EN (0x10u) /* 1PPS enable */ +#define CY_PM_1PPS_IE (0x20u) /* 1PPS interrupt enable */ + + +#define CY_PM_ACT_EN_CLK_A_MASK (0x0Fu) +#define CY_PM_ACT_EN_CLK_D_MASK (0xFFu) + +#define CY_PM_DIV_BY_ONE (0x00u) + +/* Internal Main Oscillator Control Register */ +#define CY_PM_FASTCLK_IMO_CR_XCLKEN (0x20u) + +/* Clock distribution configuration Register */ +#define CY_PM_CLKDIST_IMO_OUT_MASK (0x30u) +#define CY_PM_CLKDIST_IMO_OUT_IMO (0x00u) +#define CY_PM_CLKDIST_IMO2X_SRC (0x40u) + +/* Waiting for the hibernate/sleep regulator to stabilize */ +#define CY_PM_MODE_CSR_PWRUP_PULSE_Q (0x08u) + +#define CY_PM_MODE_CSR_ACTIVE (0x00u) /* Active power mode */ +#define CY_PM_MODE_CSR_ALT_ACT (0x01u) /* Alternate Active power */ +#define CY_PM_MODE_CSR_SLEEP (0x03u) /* Sleep power mode */ +#define CY_PM_MODE_CSR_HIBERNATE (0x04u) /* Hibernate power mode */ +#define CY_PM_MODE_CSR_MASK (0x07u) + +/* I2C regulator backup enable */ +#define CY_PM_PWRSYS_CR1_I2CREG_BACKUP (0x04u) + +/* When set, prepares the system to disable the LDO-A */ +#define CY_PM_PWRSYS_CR1_LDOA_ISO (0x01u) + +/* When set, disables the analog LDO regulator */ +#define CY_PM_PWRSYS_CR1_LDOA_DIS (0x02u) + +#define CY_PM_PWRSYS_WAKE_TR2_VCCD_CLK_DET (0x04u) + +#define CY_PM_FTW_INT (0x01u) /* FTW event has occured */ +#define CY_PM_CTW_INT (0x02u) /* CTW event has occured */ +#define CY_PM_ONEPPS_INT (0x04u) /* 1PPS event has occured */ + +/* Active Power Mode Configuration Register 0 */ +#define CY_PM_ACT_CFG0_IMO (0x10u) /* IMO enable in Active */ + +/* Cache Control Register (same mask for all device revisions) */ +#define CY_PM_CACHE_CR_CYCLES_MASK (0xC0u) + +/* Bus Clock divider to divide-by-one */ +#define CY_PM_BUS_CLK_DIV_BY_ONE (0x00u) + +/* HVI/LVI feature on the external analog and digital supply mask */ +#define CY_PM_RESET_CR1_HVI_LVI_EN_MASK (0x07u) + +/* The high-voltage-interrupt feature on the external analog supply */ +#define CY_PM_RESET_CR1_HVIA_EN (0x04u) + +/* The low-voltage-interrupt feature on the external analog supply */ +#define CY_PM_RESET_CR1_LVIA_EN (0x02u) + +/* The low-voltage-interrupt feature on the external digital supply */ +#define CY_PM_RESET_CR1_LVID_EN (0x01u) + +/* Allows the system to program delays on clk_sync_d */ +#define CY_PM_CLKDIST_DELAY_EN (0x04u) + + +#define CY_PM_WAKEUP_SRC_CMPS_MASK (0x000Fu) + +/* Holdoff mask sleep trim */ +#define CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK (0x1Fu) + +#if(CY_PSOC3) + + /* CPU clock divider mask */ + #define CY_PM_CLKDIST_CPU_DIV_MASK (0xF0u) + + /* Serial Wire View (SWV) clock enable */ + #define CY_PM_MLOGIC_DBG_SWV_CLK_EN (0x04u) + + /* Port drive mode */ + #define CY_PM_PRT1_PC3_DM_MASK (0xf1u) + + /* Mode 6, stong pull-up, strong pull-down */ + #define CY_PM_PRT1_PC3_DM_STRONG (0x0Cu) + + /* When set, enables buzz wakeups */ + #define CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ (0x01u) + +#endif /* (CY_PSOC3) */ + + +/* Disable the sleep regulator and shorts vccd to vpwrsleep */ +#define CY_PM_PWRSYS_SLP_TR_BYPASS (0x10u) + +/* Boost Control 2: Select external precision reference */ +#define CY_PM_BOOST_CR2_EREFSEL_EXT (0x08u) + +#if(CY_PSOC3) + + #define CY_PM_PWRSYS_WAKE_TR0 (0xFFu) + #define CY_PM_PWRSYS_WAKE_TR1 (0x90u) + +#endif /* (CY_PSOC3) */ + +#if(CY_PSOC5) + + #define CY_PM_PWRSYS_WAKE_TR0 (0xFFu) + #define CY_PM_PWRSYS_WAKE_TR1 (0xB0u) + +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from cy_boot 3.30 +*******************************************************************************/ +#if(CY_PSOC3) + + /* Was removed as redundant */ + #define CY_PM_FTW_INTERVAL_MASK (0xFFu) + +#endif /* (CY_PSOC3) */ + +/* Was removed as redundant */ +#define CY_PM_CTW_INTERVAL_MASK (0x0Fu) + +#endif /* (CY_BOOT_CYPM_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydevice.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydevice.h new file mode 100755 index 00000000..2514d9aa --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydevice.h @@ -0,0 +1,5360 @@ +/******************************************************************************* +* FILENAME: cydevice.h +* OBSOLETE: Do not use this file. Use the _trm version instead. +* PSoC Creator 3.0 Component Pack 7 +* +* DESCRIPTION: +* This file provides all of the address values for the entire PSoC device. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#if !defined(CYDEVICE_H) +#define CYDEVICE_H +#define CYDEV_FLASH_BASE 0x00000000u +#define CYDEV_FLASH_SIZE 0x00020000u +#define CYDEV_FLASH_DATA_MBASE 0x00000000u +#define CYDEV_FLASH_DATA_MSIZE 0x00020000u +#define CYDEV_SRAM_BASE 0x1fffc000u +#define CYDEV_SRAM_SIZE 0x00008000u +#define CYDEV_SRAM_CODE64K_MBASE 0x1fff8000u +#define CYDEV_SRAM_CODE64K_MSIZE 0x00004000u +#define CYDEV_SRAM_CODE32K_MBASE 0x1fffc000u +#define CYDEV_SRAM_CODE32K_MSIZE 0x00002000u +#define CYDEV_SRAM_CODE16K_MBASE 0x1fffe000u +#define CYDEV_SRAM_CODE16K_MSIZE 0x00001000u +#define CYDEV_SRAM_CODE_MBASE 0x1fffc000u +#define CYDEV_SRAM_CODE_MSIZE 0x00004000u +#define CYDEV_SRAM_DATA_MBASE 0x20000000u +#define CYDEV_SRAM_DATA_MSIZE 0x00004000u +#define CYDEV_SRAM_DATA16K_MBASE 0x20001000u +#define CYDEV_SRAM_DATA16K_MSIZE 0x00001000u +#define CYDEV_SRAM_DATA32K_MBASE 0x20002000u +#define CYDEV_SRAM_DATA32K_MSIZE 0x00002000u +#define CYDEV_SRAM_DATA64K_MBASE 0x20004000u +#define CYDEV_SRAM_DATA64K_MSIZE 0x00004000u +#define CYDEV_DMA_BASE 0x20008000u +#define CYDEV_DMA_SIZE 0x00008000u +#define CYDEV_DMA_SRAM64K_MBASE 0x20008000u +#define CYDEV_DMA_SRAM64K_MSIZE 0x00004000u +#define CYDEV_DMA_SRAM32K_MBASE 0x2000c000u +#define CYDEV_DMA_SRAM32K_MSIZE 0x00002000u +#define CYDEV_DMA_SRAM16K_MBASE 0x2000e000u +#define CYDEV_DMA_SRAM16K_MSIZE 0x00001000u +#define CYDEV_DMA_SRAM_MBASE 0x2000f000u +#define CYDEV_DMA_SRAM_MSIZE 0x00001000u +#define CYDEV_CLKDIST_BASE 0x40004000u +#define CYDEV_CLKDIST_SIZE 0x00000110u +#define CYDEV_CLKDIST_CR 0x40004000u +#define CYDEV_CLKDIST_LD 0x40004001u +#define CYDEV_CLKDIST_WRK0 0x40004002u +#define CYDEV_CLKDIST_WRK1 0x40004003u +#define CYDEV_CLKDIST_MSTR0 0x40004004u +#define CYDEV_CLKDIST_MSTR1 0x40004005u +#define CYDEV_CLKDIST_BCFG0 0x40004006u +#define CYDEV_CLKDIST_BCFG1 0x40004007u +#define CYDEV_CLKDIST_BCFG2 0x40004008u +#define CYDEV_CLKDIST_UCFG 0x40004009u +#define CYDEV_CLKDIST_DLY0 0x4000400au +#define CYDEV_CLKDIST_DLY1 0x4000400bu +#define CYDEV_CLKDIST_DMASK 0x40004010u +#define CYDEV_CLKDIST_AMASK 0x40004014u +#define CYDEV_CLKDIST_DCFG0_BASE 0x40004080u +#define CYDEV_CLKDIST_DCFG0_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG0_CFG0 0x40004080u +#define CYDEV_CLKDIST_DCFG0_CFG1 0x40004081u +#define CYDEV_CLKDIST_DCFG0_CFG2 0x40004082u +#define CYDEV_CLKDIST_DCFG1_BASE 0x40004084u +#define CYDEV_CLKDIST_DCFG1_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG1_CFG0 0x40004084u +#define CYDEV_CLKDIST_DCFG1_CFG1 0x40004085u +#define CYDEV_CLKDIST_DCFG1_CFG2 0x40004086u +#define CYDEV_CLKDIST_DCFG2_BASE 0x40004088u +#define CYDEV_CLKDIST_DCFG2_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG2_CFG0 0x40004088u +#define CYDEV_CLKDIST_DCFG2_CFG1 0x40004089u +#define CYDEV_CLKDIST_DCFG2_CFG2 0x4000408au +#define CYDEV_CLKDIST_DCFG3_BASE 0x4000408cu +#define CYDEV_CLKDIST_DCFG3_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG3_CFG0 0x4000408cu +#define CYDEV_CLKDIST_DCFG3_CFG1 0x4000408du +#define CYDEV_CLKDIST_DCFG3_CFG2 0x4000408eu +#define CYDEV_CLKDIST_DCFG4_BASE 0x40004090u +#define CYDEV_CLKDIST_DCFG4_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG4_CFG0 0x40004090u +#define CYDEV_CLKDIST_DCFG4_CFG1 0x40004091u +#define CYDEV_CLKDIST_DCFG4_CFG2 0x40004092u +#define CYDEV_CLKDIST_DCFG5_BASE 0x40004094u +#define CYDEV_CLKDIST_DCFG5_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG5_CFG0 0x40004094u +#define CYDEV_CLKDIST_DCFG5_CFG1 0x40004095u +#define CYDEV_CLKDIST_DCFG5_CFG2 0x40004096u +#define CYDEV_CLKDIST_DCFG6_BASE 0x40004098u +#define CYDEV_CLKDIST_DCFG6_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG6_CFG0 0x40004098u +#define CYDEV_CLKDIST_DCFG6_CFG1 0x40004099u +#define CYDEV_CLKDIST_DCFG6_CFG2 0x4000409au +#define CYDEV_CLKDIST_DCFG7_BASE 0x4000409cu +#define CYDEV_CLKDIST_DCFG7_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG7_CFG0 0x4000409cu +#define CYDEV_CLKDIST_DCFG7_CFG1 0x4000409du +#define CYDEV_CLKDIST_DCFG7_CFG2 0x4000409eu +#define CYDEV_CLKDIST_ACFG0_BASE 0x40004100u +#define CYDEV_CLKDIST_ACFG0_SIZE 0x00000004u +#define CYDEV_CLKDIST_ACFG0_CFG0 0x40004100u +#define CYDEV_CLKDIST_ACFG0_CFG1 0x40004101u +#define CYDEV_CLKDIST_ACFG0_CFG2 0x40004102u +#define CYDEV_CLKDIST_ACFG0_CFG3 0x40004103u +#define CYDEV_CLKDIST_ACFG1_BASE 0x40004104u +#define CYDEV_CLKDIST_ACFG1_SIZE 0x00000004u +#define CYDEV_CLKDIST_ACFG1_CFG0 0x40004104u +#define CYDEV_CLKDIST_ACFG1_CFG1 0x40004105u +#define CYDEV_CLKDIST_ACFG1_CFG2 0x40004106u +#define CYDEV_CLKDIST_ACFG1_CFG3 0x40004107u +#define CYDEV_CLKDIST_ACFG2_BASE 0x40004108u +#define CYDEV_CLKDIST_ACFG2_SIZE 0x00000004u +#define CYDEV_CLKDIST_ACFG2_CFG0 0x40004108u +#define CYDEV_CLKDIST_ACFG2_CFG1 0x40004109u +#define CYDEV_CLKDIST_ACFG2_CFG2 0x4000410au +#define CYDEV_CLKDIST_ACFG2_CFG3 0x4000410bu +#define CYDEV_CLKDIST_ACFG3_BASE 0x4000410cu +#define CYDEV_CLKDIST_ACFG3_SIZE 0x00000004u +#define CYDEV_CLKDIST_ACFG3_CFG0 0x4000410cu +#define CYDEV_CLKDIST_ACFG3_CFG1 0x4000410du +#define CYDEV_CLKDIST_ACFG3_CFG2 0x4000410eu +#define CYDEV_CLKDIST_ACFG3_CFG3 0x4000410fu +#define CYDEV_FASTCLK_BASE 0x40004200u +#define CYDEV_FASTCLK_SIZE 0x00000026u +#define CYDEV_FASTCLK_IMO_BASE 0x40004200u +#define CYDEV_FASTCLK_IMO_SIZE 0x00000001u +#define CYDEV_FASTCLK_IMO_CR 0x40004200u +#define CYDEV_FASTCLK_XMHZ_BASE 0x40004210u +#define CYDEV_FASTCLK_XMHZ_SIZE 0x00000004u +#define CYDEV_FASTCLK_XMHZ_CSR 0x40004210u +#define CYDEV_FASTCLK_XMHZ_CFG0 0x40004212u +#define CYDEV_FASTCLK_XMHZ_CFG1 0x40004213u +#define CYDEV_FASTCLK_PLL_BASE 0x40004220u +#define CYDEV_FASTCLK_PLL_SIZE 0x00000006u +#define CYDEV_FASTCLK_PLL_CFG0 0x40004220u +#define CYDEV_FASTCLK_PLL_CFG1 0x40004221u +#define CYDEV_FASTCLK_PLL_P 0x40004222u +#define CYDEV_FASTCLK_PLL_Q 0x40004223u +#define CYDEV_FASTCLK_PLL_SR 0x40004225u +#define CYDEV_SLOWCLK_BASE 0x40004300u +#define CYDEV_SLOWCLK_SIZE 0x0000000bu +#define CYDEV_SLOWCLK_ILO_BASE 0x40004300u +#define CYDEV_SLOWCLK_ILO_SIZE 0x00000002u +#define CYDEV_SLOWCLK_ILO_CR0 0x40004300u +#define CYDEV_SLOWCLK_ILO_CR1 0x40004301u +#define CYDEV_SLOWCLK_X32_BASE 0x40004308u +#define CYDEV_SLOWCLK_X32_SIZE 0x00000003u +#define CYDEV_SLOWCLK_X32_CR 0x40004308u +#define CYDEV_SLOWCLK_X32_CFG 0x40004309u +#define CYDEV_SLOWCLK_X32_TST 0x4000430au +#define CYDEV_BOOST_BASE 0x40004320u +#define CYDEV_BOOST_SIZE 0x00000007u +#define CYDEV_BOOST_CR0 0x40004320u +#define CYDEV_BOOST_CR1 0x40004321u +#define CYDEV_BOOST_CR2 0x40004322u +#define CYDEV_BOOST_CR3 0x40004323u +#define CYDEV_BOOST_SR 0x40004324u +#define CYDEV_BOOST_CR4 0x40004325u +#define CYDEV_BOOST_SR2 0x40004326u +#define CYDEV_PWRSYS_BASE 0x40004330u +#define CYDEV_PWRSYS_SIZE 0x00000002u +#define CYDEV_PWRSYS_CR0 0x40004330u +#define CYDEV_PWRSYS_CR1 0x40004331u +#define CYDEV_PM_BASE 0x40004380u +#define CYDEV_PM_SIZE 0x00000057u +#define CYDEV_PM_TW_CFG0 0x40004380u +#define CYDEV_PM_TW_CFG1 0x40004381u +#define CYDEV_PM_TW_CFG2 0x40004382u +#define CYDEV_PM_WDT_CFG 0x40004383u +#define CYDEV_PM_WDT_CR 0x40004384u +#define CYDEV_PM_INT_SR 0x40004390u +#define CYDEV_PM_MODE_CFG0 0x40004391u +#define CYDEV_PM_MODE_CFG1 0x40004392u +#define CYDEV_PM_MODE_CSR 0x40004393u +#define CYDEV_PM_USB_CR0 0x40004394u +#define CYDEV_PM_WAKEUP_CFG0 0x40004398u +#define CYDEV_PM_WAKEUP_CFG1 0x40004399u +#define CYDEV_PM_WAKEUP_CFG2 0x4000439au +#define CYDEV_PM_ACT_BASE 0x400043a0u +#define CYDEV_PM_ACT_SIZE 0x0000000eu +#define CYDEV_PM_ACT_CFG0 0x400043a0u +#define CYDEV_PM_ACT_CFG1 0x400043a1u +#define CYDEV_PM_ACT_CFG2 0x400043a2u +#define CYDEV_PM_ACT_CFG3 0x400043a3u +#define CYDEV_PM_ACT_CFG4 0x400043a4u +#define CYDEV_PM_ACT_CFG5 0x400043a5u +#define CYDEV_PM_ACT_CFG6 0x400043a6u +#define CYDEV_PM_ACT_CFG7 0x400043a7u +#define CYDEV_PM_ACT_CFG8 0x400043a8u +#define CYDEV_PM_ACT_CFG9 0x400043a9u +#define CYDEV_PM_ACT_CFG10 0x400043aau +#define CYDEV_PM_ACT_CFG11 0x400043abu +#define CYDEV_PM_ACT_CFG12 0x400043acu +#define CYDEV_PM_ACT_CFG13 0x400043adu +#define CYDEV_PM_STBY_BASE 0x400043b0u +#define CYDEV_PM_STBY_SIZE 0x0000000eu +#define CYDEV_PM_STBY_CFG0 0x400043b0u +#define CYDEV_PM_STBY_CFG1 0x400043b1u +#define CYDEV_PM_STBY_CFG2 0x400043b2u +#define CYDEV_PM_STBY_CFG3 0x400043b3u +#define CYDEV_PM_STBY_CFG4 0x400043b4u +#define CYDEV_PM_STBY_CFG5 0x400043b5u +#define CYDEV_PM_STBY_CFG6 0x400043b6u +#define CYDEV_PM_STBY_CFG7 0x400043b7u +#define CYDEV_PM_STBY_CFG8 0x400043b8u +#define CYDEV_PM_STBY_CFG9 0x400043b9u +#define CYDEV_PM_STBY_CFG10 0x400043bau +#define CYDEV_PM_STBY_CFG11 0x400043bbu +#define CYDEV_PM_STBY_CFG12 0x400043bcu +#define CYDEV_PM_STBY_CFG13 0x400043bdu +#define CYDEV_PM_AVAIL_BASE 0x400043c0u +#define CYDEV_PM_AVAIL_SIZE 0x00000017u +#define CYDEV_PM_AVAIL_CR0 0x400043c0u +#define CYDEV_PM_AVAIL_CR1 0x400043c1u +#define CYDEV_PM_AVAIL_CR2 0x400043c2u +#define CYDEV_PM_AVAIL_CR3 0x400043c3u +#define CYDEV_PM_AVAIL_CR4 0x400043c4u +#define CYDEV_PM_AVAIL_CR5 0x400043c5u +#define CYDEV_PM_AVAIL_CR6 0x400043c6u +#define CYDEV_PM_AVAIL_SR0 0x400043d0u +#define CYDEV_PM_AVAIL_SR1 0x400043d1u +#define CYDEV_PM_AVAIL_SR2 0x400043d2u +#define CYDEV_PM_AVAIL_SR3 0x400043d3u +#define CYDEV_PM_AVAIL_SR4 0x400043d4u +#define CYDEV_PM_AVAIL_SR5 0x400043d5u +#define CYDEV_PM_AVAIL_SR6 0x400043d6u +#define CYDEV_PICU_BASE 0x40004500u +#define CYDEV_PICU_SIZE 0x000000b0u +#define CYDEV_PICU_INTTYPE_BASE 0x40004500u +#define CYDEV_PICU_INTTYPE_SIZE 0x00000080u +#define CYDEV_PICU_INTTYPE_PICU0_BASE 0x40004500u +#define CYDEV_PICU_INTTYPE_PICU0_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE0 0x40004500u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE1 0x40004501u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE2 0x40004502u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE3 0x40004503u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE4 0x40004504u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE5 0x40004505u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE6 0x40004506u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE7 0x40004507u +#define CYDEV_PICU_INTTYPE_PICU1_BASE 0x40004508u +#define CYDEV_PICU_INTTYPE_PICU1_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE0 0x40004508u +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE1 0x40004509u +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE2 0x4000450au +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE3 0x4000450bu +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE4 0x4000450cu +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE5 0x4000450du +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE6 0x4000450eu +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE7 0x4000450fu +#define CYDEV_PICU_INTTYPE_PICU2_BASE 0x40004510u +#define CYDEV_PICU_INTTYPE_PICU2_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE0 0x40004510u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE1 0x40004511u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE2 0x40004512u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE3 0x40004513u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE4 0x40004514u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE5 0x40004515u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE6 0x40004516u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE7 0x40004517u +#define CYDEV_PICU_INTTYPE_PICU3_BASE 0x40004518u +#define CYDEV_PICU_INTTYPE_PICU3_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE0 0x40004518u +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE1 0x40004519u +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE2 0x4000451au +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE3 0x4000451bu +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE4 0x4000451cu +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE5 0x4000451du +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE6 0x4000451eu +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE7 0x4000451fu +#define CYDEV_PICU_INTTYPE_PICU4_BASE 0x40004520u +#define CYDEV_PICU_INTTYPE_PICU4_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE0 0x40004520u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE1 0x40004521u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE2 0x40004522u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE3 0x40004523u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE4 0x40004524u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE5 0x40004525u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE6 0x40004526u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE7 0x40004527u +#define CYDEV_PICU_INTTYPE_PICU5_BASE 0x40004528u +#define CYDEV_PICU_INTTYPE_PICU5_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE0 0x40004528u +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE1 0x40004529u +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE2 0x4000452au +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE3 0x4000452bu +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE4 0x4000452cu +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE5 0x4000452du +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE6 0x4000452eu +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE7 0x4000452fu +#define CYDEV_PICU_INTTYPE_PICU6_BASE 0x40004530u +#define CYDEV_PICU_INTTYPE_PICU6_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE0 0x40004530u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE1 0x40004531u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE2 0x40004532u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE3 0x40004533u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE4 0x40004534u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE5 0x40004535u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE6 0x40004536u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE7 0x40004537u +#define CYDEV_PICU_INTTYPE_PICU12_BASE 0x40004560u +#define CYDEV_PICU_INTTYPE_PICU12_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE0 0x40004560u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE1 0x40004561u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE2 0x40004562u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE3 0x40004563u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE4 0x40004564u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE5 0x40004565u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE6 0x40004566u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE7 0x40004567u +#define CYDEV_PICU_INTTYPE_PICU15_BASE 0x40004578u +#define CYDEV_PICU_INTTYPE_PICU15_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE0 0x40004578u +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE1 0x40004579u +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE2 0x4000457au +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE3 0x4000457bu +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE4 0x4000457cu +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE5 0x4000457du +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE6 0x4000457eu +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE7 0x4000457fu +#define CYDEV_PICU_STAT_BASE 0x40004580u +#define CYDEV_PICU_STAT_SIZE 0x00000010u +#define CYDEV_PICU_STAT_PICU0_BASE 0x40004580u +#define CYDEV_PICU_STAT_PICU0_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU0_INTSTAT 0x40004580u +#define CYDEV_PICU_STAT_PICU1_BASE 0x40004581u +#define CYDEV_PICU_STAT_PICU1_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU1_INTSTAT 0x40004581u +#define CYDEV_PICU_STAT_PICU2_BASE 0x40004582u +#define CYDEV_PICU_STAT_PICU2_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU2_INTSTAT 0x40004582u +#define CYDEV_PICU_STAT_PICU3_BASE 0x40004583u +#define CYDEV_PICU_STAT_PICU3_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU3_INTSTAT 0x40004583u +#define CYDEV_PICU_STAT_PICU4_BASE 0x40004584u +#define CYDEV_PICU_STAT_PICU4_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU4_INTSTAT 0x40004584u +#define CYDEV_PICU_STAT_PICU5_BASE 0x40004585u +#define CYDEV_PICU_STAT_PICU5_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU5_INTSTAT 0x40004585u +#define CYDEV_PICU_STAT_PICU6_BASE 0x40004586u +#define CYDEV_PICU_STAT_PICU6_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU6_INTSTAT 0x40004586u +#define CYDEV_PICU_STAT_PICU12_BASE 0x4000458cu +#define CYDEV_PICU_STAT_PICU12_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU12_INTSTAT 0x4000458cu +#define CYDEV_PICU_STAT_PICU15_BASE 0x4000458fu +#define CYDEV_PICU_STAT_PICU15_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU15_INTSTAT 0x4000458fu +#define CYDEV_PICU_SNAP_BASE 0x40004590u +#define CYDEV_PICU_SNAP_SIZE 0x00000010u +#define CYDEV_PICU_SNAP_PICU0_BASE 0x40004590u +#define CYDEV_PICU_SNAP_PICU0_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU0_SNAP 0x40004590u +#define CYDEV_PICU_SNAP_PICU1_BASE 0x40004591u +#define CYDEV_PICU_SNAP_PICU1_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU1_SNAP 0x40004591u +#define CYDEV_PICU_SNAP_PICU2_BASE 0x40004592u +#define CYDEV_PICU_SNAP_PICU2_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU2_SNAP 0x40004592u +#define CYDEV_PICU_SNAP_PICU3_BASE 0x40004593u +#define CYDEV_PICU_SNAP_PICU3_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU3_SNAP 0x40004593u +#define CYDEV_PICU_SNAP_PICU4_BASE 0x40004594u +#define CYDEV_PICU_SNAP_PICU4_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU4_SNAP 0x40004594u +#define CYDEV_PICU_SNAP_PICU5_BASE 0x40004595u +#define CYDEV_PICU_SNAP_PICU5_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU5_SNAP 0x40004595u +#define CYDEV_PICU_SNAP_PICU6_BASE 0x40004596u +#define CYDEV_PICU_SNAP_PICU6_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU6_SNAP 0x40004596u +#define CYDEV_PICU_SNAP_PICU12_BASE 0x4000459cu +#define CYDEV_PICU_SNAP_PICU12_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU12_SNAP 0x4000459cu +#define CYDEV_PICU_SNAP_PICU_15_BASE 0x4000459fu +#define CYDEV_PICU_SNAP_PICU_15_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU_15_SNAP_15 0x4000459fu +#define CYDEV_PICU_DISABLE_COR_BASE 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_SIZE 0x00000010u +#define CYDEV_PICU_DISABLE_COR_PICU0_BASE 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_PICU0_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_PICU1_BASE 0x400045a1u +#define CYDEV_PICU_DISABLE_COR_PICU1_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR 0x400045a1u +#define CYDEV_PICU_DISABLE_COR_PICU2_BASE 0x400045a2u +#define CYDEV_PICU_DISABLE_COR_PICU2_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR 0x400045a2u +#define CYDEV_PICU_DISABLE_COR_PICU3_BASE 0x400045a3u +#define CYDEV_PICU_DISABLE_COR_PICU3_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR 0x400045a3u +#define CYDEV_PICU_DISABLE_COR_PICU4_BASE 0x400045a4u +#define CYDEV_PICU_DISABLE_COR_PICU4_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR 0x400045a4u +#define CYDEV_PICU_DISABLE_COR_PICU5_BASE 0x400045a5u +#define CYDEV_PICU_DISABLE_COR_PICU5_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR 0x400045a5u +#define CYDEV_PICU_DISABLE_COR_PICU6_BASE 0x400045a6u +#define CYDEV_PICU_DISABLE_COR_PICU6_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR 0x400045a6u +#define CYDEV_PICU_DISABLE_COR_PICU12_BASE 0x400045acu +#define CYDEV_PICU_DISABLE_COR_PICU12_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR 0x400045acu +#define CYDEV_PICU_DISABLE_COR_PICU15_BASE 0x400045afu +#define CYDEV_PICU_DISABLE_COR_PICU15_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR 0x400045afu +#define CYDEV_MFGCFG_BASE 0x40004600u +#define CYDEV_MFGCFG_SIZE 0x000000edu +#define CYDEV_MFGCFG_ANAIF_BASE 0x40004600u +#define CYDEV_MFGCFG_ANAIF_SIZE 0x00000038u +#define CYDEV_MFGCFG_ANAIF_DAC0_BASE 0x40004608u +#define CYDEV_MFGCFG_ANAIF_DAC0_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_DAC0_TR 0x40004608u +#define CYDEV_MFGCFG_ANAIF_DAC1_BASE 0x40004609u +#define CYDEV_MFGCFG_ANAIF_DAC1_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_DAC1_TR 0x40004609u +#define CYDEV_MFGCFG_ANAIF_DAC2_BASE 0x4000460au +#define CYDEV_MFGCFG_ANAIF_DAC2_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_DAC2_TR 0x4000460au +#define CYDEV_MFGCFG_ANAIF_DAC3_BASE 0x4000460bu +#define CYDEV_MFGCFG_ANAIF_DAC3_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_DAC3_TR 0x4000460bu +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE 0x40004610u +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0 0x40004610u +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE 0x40004611u +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0 0x40004611u +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE 0x40004612u +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0 0x40004612u +#define CYDEV_MFGCFG_ANAIF_SAR0_BASE 0x40004614u +#define CYDEV_MFGCFG_ANAIF_SAR0_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_SAR0_TR0 0x40004614u +#define CYDEV_MFGCFG_ANAIF_SAR1_BASE 0x40004616u +#define CYDEV_MFGCFG_ANAIF_SAR1_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_SAR1_TR0 0x40004616u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_BASE 0x40004620u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_TR0 0x40004620u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_TR1 0x40004621u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_BASE 0x40004622u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_TR0 0x40004622u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_TR1 0x40004623u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_BASE 0x40004624u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_TR0 0x40004624u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_TR1 0x40004625u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_BASE 0x40004626u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_TR0 0x40004626u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_TR1 0x40004627u +#define CYDEV_MFGCFG_ANAIF_CMP0_BASE 0x40004630u +#define CYDEV_MFGCFG_ANAIF_CMP0_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_CMP0_TR0 0x40004630u +#define CYDEV_MFGCFG_ANAIF_CMP0_TR1 0x40004631u +#define CYDEV_MFGCFG_ANAIF_CMP1_BASE 0x40004632u +#define CYDEV_MFGCFG_ANAIF_CMP1_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_CMP1_TR0 0x40004632u +#define CYDEV_MFGCFG_ANAIF_CMP1_TR1 0x40004633u +#define CYDEV_MFGCFG_ANAIF_CMP2_BASE 0x40004634u +#define CYDEV_MFGCFG_ANAIF_CMP2_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_CMP2_TR0 0x40004634u +#define CYDEV_MFGCFG_ANAIF_CMP2_TR1 0x40004635u +#define CYDEV_MFGCFG_ANAIF_CMP3_BASE 0x40004636u +#define CYDEV_MFGCFG_ANAIF_CMP3_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_CMP3_TR0 0x40004636u +#define CYDEV_MFGCFG_ANAIF_CMP3_TR1 0x40004637u +#define CYDEV_MFGCFG_PWRSYS_BASE 0x40004680u +#define CYDEV_MFGCFG_PWRSYS_SIZE 0x0000000bu +#define CYDEV_MFGCFG_PWRSYS_HIB_TR0 0x40004680u +#define CYDEV_MFGCFG_PWRSYS_HIB_TR1 0x40004681u +#define CYDEV_MFGCFG_PWRSYS_I2C_TR 0x40004682u +#define CYDEV_MFGCFG_PWRSYS_SLP_TR 0x40004683u +#define CYDEV_MFGCFG_PWRSYS_BUZZ_TR 0x40004684u +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR0 0x40004685u +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR1 0x40004686u +#define CYDEV_MFGCFG_PWRSYS_BREF_TR 0x40004687u +#define CYDEV_MFGCFG_PWRSYS_BG_TR 0x40004688u +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR2 0x40004689u +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR3 0x4000468au +#define CYDEV_MFGCFG_ILO_BASE 0x40004690u +#define CYDEV_MFGCFG_ILO_SIZE 0x00000002u +#define CYDEV_MFGCFG_ILO_TR0 0x40004690u +#define CYDEV_MFGCFG_ILO_TR1 0x40004691u +#define CYDEV_MFGCFG_X32_BASE 0x40004698u +#define CYDEV_MFGCFG_X32_SIZE 0x00000001u +#define CYDEV_MFGCFG_X32_TR 0x40004698u +#define CYDEV_MFGCFG_IMO_BASE 0x400046a0u +#define CYDEV_MFGCFG_IMO_SIZE 0x00000005u +#define CYDEV_MFGCFG_IMO_TR0 0x400046a0u +#define CYDEV_MFGCFG_IMO_TR1 0x400046a1u +#define CYDEV_MFGCFG_IMO_GAIN 0x400046a2u +#define CYDEV_MFGCFG_IMO_C36M 0x400046a3u +#define CYDEV_MFGCFG_IMO_TR2 0x400046a4u +#define CYDEV_MFGCFG_XMHZ_BASE 0x400046a8u +#define CYDEV_MFGCFG_XMHZ_SIZE 0x00000001u +#define CYDEV_MFGCFG_XMHZ_TR 0x400046a8u +#define CYDEV_MFGCFG_DLY 0x400046c0u +#define CYDEV_MFGCFG_MLOGIC_BASE 0x400046e0u +#define CYDEV_MFGCFG_MLOGIC_SIZE 0x0000000du +#define CYDEV_MFGCFG_MLOGIC_DMPSTR 0x400046e2u +#define CYDEV_MFGCFG_MLOGIC_SEG_BASE 0x400046e4u +#define CYDEV_MFGCFG_MLOGIC_SEG_SIZE 0x00000002u +#define CYDEV_MFGCFG_MLOGIC_SEG_CR 0x400046e4u +#define CYDEV_MFGCFG_MLOGIC_SEG_CFG0 0x400046e5u +#define CYDEV_MFGCFG_MLOGIC_DEBUG 0x400046e8u +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE 0x400046eau +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE 0x00000001u +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR 0x400046eau +#define CYDEV_MFGCFG_MLOGIC_REV_ID 0x400046ecu +#define CYDEV_RESET_BASE 0x400046f0u +#define CYDEV_RESET_SIZE 0x0000000fu +#define CYDEV_RESET_IPOR_CR0 0x400046f0u +#define CYDEV_RESET_IPOR_CR1 0x400046f1u +#define CYDEV_RESET_IPOR_CR2 0x400046f2u +#define CYDEV_RESET_IPOR_CR3 0x400046f3u +#define CYDEV_RESET_CR0 0x400046f4u +#define CYDEV_RESET_CR1 0x400046f5u +#define CYDEV_RESET_CR2 0x400046f6u +#define CYDEV_RESET_CR3 0x400046f7u +#define CYDEV_RESET_CR4 0x400046f8u +#define CYDEV_RESET_CR5 0x400046f9u +#define CYDEV_RESET_SR0 0x400046fau +#define CYDEV_RESET_SR1 0x400046fbu +#define CYDEV_RESET_SR2 0x400046fcu +#define CYDEV_RESET_SR3 0x400046fdu +#define CYDEV_RESET_TR 0x400046feu +#define CYDEV_SPC_BASE 0x40004700u +#define CYDEV_SPC_SIZE 0x00000100u +#define CYDEV_SPC_FM_EE_CR 0x40004700u +#define CYDEV_SPC_FM_EE_WAKE_CNT 0x40004701u +#define CYDEV_SPC_EE_SCR 0x40004702u +#define CYDEV_SPC_EE_ERR 0x40004703u +#define CYDEV_SPC_CPU_DATA 0x40004720u +#define CYDEV_SPC_DMA_DATA 0x40004721u +#define CYDEV_SPC_SR 0x40004722u +#define CYDEV_SPC_CR 0x40004723u +#define CYDEV_SPC_DMM_MAP_BASE 0x40004780u +#define CYDEV_SPC_DMM_MAP_SIZE 0x00000080u +#define CYDEV_SPC_DMM_MAP_SRAM_MBASE 0x40004780u +#define CYDEV_SPC_DMM_MAP_SRAM_MSIZE 0x00000080u +#define CYDEV_CACHE_BASE 0x40004800u +#define CYDEV_CACHE_SIZE 0x0000009cu +#define CYDEV_CACHE_CC_CTL 0x40004800u +#define CYDEV_CACHE_ECC_CORR 0x40004880u +#define CYDEV_CACHE_ECC_ERR 0x40004888u +#define CYDEV_CACHE_FLASH_ERR 0x40004890u +#define CYDEV_CACHE_HITMISS 0x40004898u +#define CYDEV_I2C_BASE 0x40004900u +#define CYDEV_I2C_SIZE 0x000000e1u +#define CYDEV_I2C_XCFG 0x400049c8u +#define CYDEV_I2C_ADR 0x400049cau +#define CYDEV_I2C_CFG 0x400049d6u +#define CYDEV_I2C_CSR 0x400049d7u +#define CYDEV_I2C_D 0x400049d8u +#define CYDEV_I2C_MCSR 0x400049d9u +#define CYDEV_I2C_CLK_DIV1 0x400049dbu +#define CYDEV_I2C_CLK_DIV2 0x400049dcu +#define CYDEV_I2C_TMOUT_CSR 0x400049ddu +#define CYDEV_I2C_TMOUT_SR 0x400049deu +#define CYDEV_I2C_TMOUT_CFG0 0x400049dfu +#define CYDEV_I2C_TMOUT_CFG1 0x400049e0u +#define CYDEV_DEC_BASE 0x40004e00u +#define CYDEV_DEC_SIZE 0x00000015u +#define CYDEV_DEC_CR 0x40004e00u +#define CYDEV_DEC_SR 0x40004e01u +#define CYDEV_DEC_SHIFT1 0x40004e02u +#define CYDEV_DEC_SHIFT2 0x40004e03u +#define CYDEV_DEC_DR2 0x40004e04u +#define CYDEV_DEC_DR2H 0x40004e05u +#define CYDEV_DEC_DR1 0x40004e06u +#define CYDEV_DEC_OCOR 0x40004e08u +#define CYDEV_DEC_OCORM 0x40004e09u +#define CYDEV_DEC_OCORH 0x40004e0au +#define CYDEV_DEC_GCOR 0x40004e0cu +#define CYDEV_DEC_GCORH 0x40004e0du +#define CYDEV_DEC_GVAL 0x40004e0eu +#define CYDEV_DEC_OUTSAMP 0x40004e10u +#define CYDEV_DEC_OUTSAMPM 0x40004e11u +#define CYDEV_DEC_OUTSAMPH 0x40004e12u +#define CYDEV_DEC_OUTSAMPS 0x40004e13u +#define CYDEV_DEC_COHER 0x40004e14u +#define CYDEV_TMR0_BASE 0x40004f00u +#define CYDEV_TMR0_SIZE 0x0000000cu +#define CYDEV_TMR0_CFG0 0x40004f00u +#define CYDEV_TMR0_CFG1 0x40004f01u +#define CYDEV_TMR0_CFG2 0x40004f02u +#define CYDEV_TMR0_SR0 0x40004f03u +#define CYDEV_TMR0_PER0 0x40004f04u +#define CYDEV_TMR0_PER1 0x40004f05u +#define CYDEV_TMR0_CNT_CMP0 0x40004f06u +#define CYDEV_TMR0_CNT_CMP1 0x40004f07u +#define CYDEV_TMR0_CAP0 0x40004f08u +#define CYDEV_TMR0_CAP1 0x40004f09u +#define CYDEV_TMR0_RT0 0x40004f0au +#define CYDEV_TMR0_RT1 0x40004f0bu +#define CYDEV_TMR1_BASE 0x40004f0cu +#define CYDEV_TMR1_SIZE 0x0000000cu +#define CYDEV_TMR1_CFG0 0x40004f0cu +#define CYDEV_TMR1_CFG1 0x40004f0du +#define CYDEV_TMR1_CFG2 0x40004f0eu +#define CYDEV_TMR1_SR0 0x40004f0fu +#define CYDEV_TMR1_PER0 0x40004f10u +#define CYDEV_TMR1_PER1 0x40004f11u +#define CYDEV_TMR1_CNT_CMP0 0x40004f12u +#define CYDEV_TMR1_CNT_CMP1 0x40004f13u +#define CYDEV_TMR1_CAP0 0x40004f14u +#define CYDEV_TMR1_CAP1 0x40004f15u +#define CYDEV_TMR1_RT0 0x40004f16u +#define CYDEV_TMR1_RT1 0x40004f17u +#define CYDEV_TMR2_BASE 0x40004f18u +#define CYDEV_TMR2_SIZE 0x0000000cu +#define CYDEV_TMR2_CFG0 0x40004f18u +#define CYDEV_TMR2_CFG1 0x40004f19u +#define CYDEV_TMR2_CFG2 0x40004f1au +#define CYDEV_TMR2_SR0 0x40004f1bu +#define CYDEV_TMR2_PER0 0x40004f1cu +#define CYDEV_TMR2_PER1 0x40004f1du +#define CYDEV_TMR2_CNT_CMP0 0x40004f1eu +#define CYDEV_TMR2_CNT_CMP1 0x40004f1fu +#define CYDEV_TMR2_CAP0 0x40004f20u +#define CYDEV_TMR2_CAP1 0x40004f21u +#define CYDEV_TMR2_RT0 0x40004f22u +#define CYDEV_TMR2_RT1 0x40004f23u +#define CYDEV_TMR3_BASE 0x40004f24u +#define CYDEV_TMR3_SIZE 0x0000000cu +#define CYDEV_TMR3_CFG0 0x40004f24u +#define CYDEV_TMR3_CFG1 0x40004f25u +#define CYDEV_TMR3_CFG2 0x40004f26u +#define CYDEV_TMR3_SR0 0x40004f27u +#define CYDEV_TMR3_PER0 0x40004f28u +#define CYDEV_TMR3_PER1 0x40004f29u +#define CYDEV_TMR3_CNT_CMP0 0x40004f2au +#define CYDEV_TMR3_CNT_CMP1 0x40004f2bu +#define CYDEV_TMR3_CAP0 0x40004f2cu +#define CYDEV_TMR3_CAP1 0x40004f2du +#define CYDEV_TMR3_RT0 0x40004f2eu +#define CYDEV_TMR3_RT1 0x40004f2fu +#define CYDEV_IO_BASE 0x40005000u +#define CYDEV_IO_SIZE 0x00000200u +#define CYDEV_IO_PC_BASE 0x40005000u +#define CYDEV_IO_PC_SIZE 0x00000080u +#define CYDEV_IO_PC_PRT0_BASE 0x40005000u +#define CYDEV_IO_PC_PRT0_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT0_PC0 0x40005000u +#define CYDEV_IO_PC_PRT0_PC1 0x40005001u +#define CYDEV_IO_PC_PRT0_PC2 0x40005002u +#define CYDEV_IO_PC_PRT0_PC3 0x40005003u +#define CYDEV_IO_PC_PRT0_PC4 0x40005004u +#define CYDEV_IO_PC_PRT0_PC5 0x40005005u +#define CYDEV_IO_PC_PRT0_PC6 0x40005006u +#define CYDEV_IO_PC_PRT0_PC7 0x40005007u +#define CYDEV_IO_PC_PRT1_BASE 0x40005008u +#define CYDEV_IO_PC_PRT1_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT1_PC0 0x40005008u +#define CYDEV_IO_PC_PRT1_PC1 0x40005009u +#define CYDEV_IO_PC_PRT1_PC2 0x4000500au +#define CYDEV_IO_PC_PRT1_PC3 0x4000500bu +#define CYDEV_IO_PC_PRT1_PC4 0x4000500cu +#define CYDEV_IO_PC_PRT1_PC5 0x4000500du +#define CYDEV_IO_PC_PRT1_PC6 0x4000500eu +#define CYDEV_IO_PC_PRT1_PC7 0x4000500fu +#define CYDEV_IO_PC_PRT2_BASE 0x40005010u +#define CYDEV_IO_PC_PRT2_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT2_PC0 0x40005010u +#define CYDEV_IO_PC_PRT2_PC1 0x40005011u +#define CYDEV_IO_PC_PRT2_PC2 0x40005012u +#define CYDEV_IO_PC_PRT2_PC3 0x40005013u +#define CYDEV_IO_PC_PRT2_PC4 0x40005014u +#define CYDEV_IO_PC_PRT2_PC5 0x40005015u +#define CYDEV_IO_PC_PRT2_PC6 0x40005016u +#define CYDEV_IO_PC_PRT2_PC7 0x40005017u +#define CYDEV_IO_PC_PRT3_BASE 0x40005018u +#define CYDEV_IO_PC_PRT3_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT3_PC0 0x40005018u +#define CYDEV_IO_PC_PRT3_PC1 0x40005019u +#define CYDEV_IO_PC_PRT3_PC2 0x4000501au +#define CYDEV_IO_PC_PRT3_PC3 0x4000501bu +#define CYDEV_IO_PC_PRT3_PC4 0x4000501cu +#define CYDEV_IO_PC_PRT3_PC5 0x4000501du +#define CYDEV_IO_PC_PRT3_PC6 0x4000501eu +#define CYDEV_IO_PC_PRT3_PC7 0x4000501fu +#define CYDEV_IO_PC_PRT4_BASE 0x40005020u +#define CYDEV_IO_PC_PRT4_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT4_PC0 0x40005020u +#define CYDEV_IO_PC_PRT4_PC1 0x40005021u +#define CYDEV_IO_PC_PRT4_PC2 0x40005022u +#define CYDEV_IO_PC_PRT4_PC3 0x40005023u +#define CYDEV_IO_PC_PRT4_PC4 0x40005024u +#define CYDEV_IO_PC_PRT4_PC5 0x40005025u +#define CYDEV_IO_PC_PRT4_PC6 0x40005026u +#define CYDEV_IO_PC_PRT4_PC7 0x40005027u +#define CYDEV_IO_PC_PRT5_BASE 0x40005028u +#define CYDEV_IO_PC_PRT5_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT5_PC0 0x40005028u +#define CYDEV_IO_PC_PRT5_PC1 0x40005029u +#define CYDEV_IO_PC_PRT5_PC2 0x4000502au +#define CYDEV_IO_PC_PRT5_PC3 0x4000502bu +#define CYDEV_IO_PC_PRT5_PC4 0x4000502cu +#define CYDEV_IO_PC_PRT5_PC5 0x4000502du +#define CYDEV_IO_PC_PRT5_PC6 0x4000502eu +#define CYDEV_IO_PC_PRT5_PC7 0x4000502fu +#define CYDEV_IO_PC_PRT6_BASE 0x40005030u +#define CYDEV_IO_PC_PRT6_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT6_PC0 0x40005030u +#define CYDEV_IO_PC_PRT6_PC1 0x40005031u +#define CYDEV_IO_PC_PRT6_PC2 0x40005032u +#define CYDEV_IO_PC_PRT6_PC3 0x40005033u +#define CYDEV_IO_PC_PRT6_PC4 0x40005034u +#define CYDEV_IO_PC_PRT6_PC5 0x40005035u +#define CYDEV_IO_PC_PRT6_PC6 0x40005036u +#define CYDEV_IO_PC_PRT6_PC7 0x40005037u +#define CYDEV_IO_PC_PRT12_BASE 0x40005060u +#define CYDEV_IO_PC_PRT12_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT12_PC0 0x40005060u +#define CYDEV_IO_PC_PRT12_PC1 0x40005061u +#define CYDEV_IO_PC_PRT12_PC2 0x40005062u +#define CYDEV_IO_PC_PRT12_PC3 0x40005063u +#define CYDEV_IO_PC_PRT12_PC4 0x40005064u +#define CYDEV_IO_PC_PRT12_PC5 0x40005065u +#define CYDEV_IO_PC_PRT12_PC6 0x40005066u +#define CYDEV_IO_PC_PRT12_PC7 0x40005067u +#define CYDEV_IO_PC_PRT15_BASE 0x40005078u +#define CYDEV_IO_PC_PRT15_SIZE 0x00000006u +#define CYDEV_IO_PC_PRT15_PC0 0x40005078u +#define CYDEV_IO_PC_PRT15_PC1 0x40005079u +#define CYDEV_IO_PC_PRT15_PC2 0x4000507au +#define CYDEV_IO_PC_PRT15_PC3 0x4000507bu +#define CYDEV_IO_PC_PRT15_PC4 0x4000507cu +#define CYDEV_IO_PC_PRT15_PC5 0x4000507du +#define CYDEV_IO_PC_PRT15_7_6_BASE 0x4000507eu +#define CYDEV_IO_PC_PRT15_7_6_SIZE 0x00000002u +#define CYDEV_IO_PC_PRT15_7_6_PC0 0x4000507eu +#define CYDEV_IO_PC_PRT15_7_6_PC1 0x4000507fu +#define CYDEV_IO_DR_BASE 0x40005080u +#define CYDEV_IO_DR_SIZE 0x00000010u +#define CYDEV_IO_DR_PRT0_BASE 0x40005080u +#define CYDEV_IO_DR_PRT0_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT0_DR_ALIAS 0x40005080u +#define CYDEV_IO_DR_PRT1_BASE 0x40005081u +#define CYDEV_IO_DR_PRT1_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT1_DR_ALIAS 0x40005081u +#define CYDEV_IO_DR_PRT2_BASE 0x40005082u +#define CYDEV_IO_DR_PRT2_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT2_DR_ALIAS 0x40005082u +#define CYDEV_IO_DR_PRT3_BASE 0x40005083u +#define CYDEV_IO_DR_PRT3_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT3_DR_ALIAS 0x40005083u +#define CYDEV_IO_DR_PRT4_BASE 0x40005084u +#define CYDEV_IO_DR_PRT4_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT4_DR_ALIAS 0x40005084u +#define CYDEV_IO_DR_PRT5_BASE 0x40005085u +#define CYDEV_IO_DR_PRT5_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT5_DR_ALIAS 0x40005085u +#define CYDEV_IO_DR_PRT6_BASE 0x40005086u +#define CYDEV_IO_DR_PRT6_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT6_DR_ALIAS 0x40005086u +#define CYDEV_IO_DR_PRT12_BASE 0x4000508cu +#define CYDEV_IO_DR_PRT12_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT12_DR_ALIAS 0x4000508cu +#define CYDEV_IO_DR_PRT15_BASE 0x4000508fu +#define CYDEV_IO_DR_PRT15_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT15_DR_15_ALIAS 0x4000508fu +#define CYDEV_IO_PS_BASE 0x40005090u +#define CYDEV_IO_PS_SIZE 0x00000010u +#define CYDEV_IO_PS_PRT0_BASE 0x40005090u +#define CYDEV_IO_PS_PRT0_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT0_PS_ALIAS 0x40005090u +#define CYDEV_IO_PS_PRT1_BASE 0x40005091u +#define CYDEV_IO_PS_PRT1_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT1_PS_ALIAS 0x40005091u +#define CYDEV_IO_PS_PRT2_BASE 0x40005092u +#define CYDEV_IO_PS_PRT2_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT2_PS_ALIAS 0x40005092u +#define CYDEV_IO_PS_PRT3_BASE 0x40005093u +#define CYDEV_IO_PS_PRT3_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT3_PS_ALIAS 0x40005093u +#define CYDEV_IO_PS_PRT4_BASE 0x40005094u +#define CYDEV_IO_PS_PRT4_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT4_PS_ALIAS 0x40005094u +#define CYDEV_IO_PS_PRT5_BASE 0x40005095u +#define CYDEV_IO_PS_PRT5_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT5_PS_ALIAS 0x40005095u +#define CYDEV_IO_PS_PRT6_BASE 0x40005096u +#define CYDEV_IO_PS_PRT6_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT6_PS_ALIAS 0x40005096u +#define CYDEV_IO_PS_PRT12_BASE 0x4000509cu +#define CYDEV_IO_PS_PRT12_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT12_PS_ALIAS 0x4000509cu +#define CYDEV_IO_PS_PRT15_BASE 0x4000509fu +#define CYDEV_IO_PS_PRT15_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT15_PS15_ALIAS 0x4000509fu +#define CYDEV_IO_PRT_BASE 0x40005100u +#define CYDEV_IO_PRT_SIZE 0x00000100u +#define CYDEV_IO_PRT_PRT0_BASE 0x40005100u +#define CYDEV_IO_PRT_PRT0_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT0_DR 0x40005100u +#define CYDEV_IO_PRT_PRT0_PS 0x40005101u +#define CYDEV_IO_PRT_PRT0_DM0 0x40005102u +#define CYDEV_IO_PRT_PRT0_DM1 0x40005103u +#define CYDEV_IO_PRT_PRT0_DM2 0x40005104u +#define CYDEV_IO_PRT_PRT0_SLW 0x40005105u +#define CYDEV_IO_PRT_PRT0_BYP 0x40005106u +#define CYDEV_IO_PRT_PRT0_BIE 0x40005107u +#define CYDEV_IO_PRT_PRT0_INP_DIS 0x40005108u +#define CYDEV_IO_PRT_PRT0_CTL 0x40005109u +#define CYDEV_IO_PRT_PRT0_PRT 0x4000510au +#define CYDEV_IO_PRT_PRT0_BIT_MASK 0x4000510bu +#define CYDEV_IO_PRT_PRT0_AMUX 0x4000510cu +#define CYDEV_IO_PRT_PRT0_AG 0x4000510du +#define CYDEV_IO_PRT_PRT0_LCD_COM_SEG 0x4000510eu +#define CYDEV_IO_PRT_PRT0_LCD_EN 0x4000510fu +#define CYDEV_IO_PRT_PRT1_BASE 0x40005110u +#define CYDEV_IO_PRT_PRT1_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT1_DR 0x40005110u +#define CYDEV_IO_PRT_PRT1_PS 0x40005111u +#define CYDEV_IO_PRT_PRT1_DM0 0x40005112u +#define CYDEV_IO_PRT_PRT1_DM1 0x40005113u +#define CYDEV_IO_PRT_PRT1_DM2 0x40005114u +#define CYDEV_IO_PRT_PRT1_SLW 0x40005115u +#define CYDEV_IO_PRT_PRT1_BYP 0x40005116u +#define CYDEV_IO_PRT_PRT1_BIE 0x40005117u +#define CYDEV_IO_PRT_PRT1_INP_DIS 0x40005118u +#define CYDEV_IO_PRT_PRT1_CTL 0x40005119u +#define CYDEV_IO_PRT_PRT1_PRT 0x4000511au +#define CYDEV_IO_PRT_PRT1_BIT_MASK 0x4000511bu +#define CYDEV_IO_PRT_PRT1_AMUX 0x4000511cu +#define CYDEV_IO_PRT_PRT1_AG 0x4000511du +#define CYDEV_IO_PRT_PRT1_LCD_COM_SEG 0x4000511eu +#define CYDEV_IO_PRT_PRT1_LCD_EN 0x4000511fu +#define CYDEV_IO_PRT_PRT2_BASE 0x40005120u +#define CYDEV_IO_PRT_PRT2_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT2_DR 0x40005120u +#define CYDEV_IO_PRT_PRT2_PS 0x40005121u +#define CYDEV_IO_PRT_PRT2_DM0 0x40005122u +#define CYDEV_IO_PRT_PRT2_DM1 0x40005123u +#define CYDEV_IO_PRT_PRT2_DM2 0x40005124u +#define CYDEV_IO_PRT_PRT2_SLW 0x40005125u +#define CYDEV_IO_PRT_PRT2_BYP 0x40005126u +#define CYDEV_IO_PRT_PRT2_BIE 0x40005127u +#define CYDEV_IO_PRT_PRT2_INP_DIS 0x40005128u +#define CYDEV_IO_PRT_PRT2_CTL 0x40005129u +#define CYDEV_IO_PRT_PRT2_PRT 0x4000512au +#define CYDEV_IO_PRT_PRT2_BIT_MASK 0x4000512bu +#define CYDEV_IO_PRT_PRT2_AMUX 0x4000512cu +#define CYDEV_IO_PRT_PRT2_AG 0x4000512du +#define CYDEV_IO_PRT_PRT2_LCD_COM_SEG 0x4000512eu +#define CYDEV_IO_PRT_PRT2_LCD_EN 0x4000512fu +#define CYDEV_IO_PRT_PRT3_BASE 0x40005130u +#define CYDEV_IO_PRT_PRT3_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT3_DR 0x40005130u +#define CYDEV_IO_PRT_PRT3_PS 0x40005131u +#define CYDEV_IO_PRT_PRT3_DM0 0x40005132u +#define CYDEV_IO_PRT_PRT3_DM1 0x40005133u +#define CYDEV_IO_PRT_PRT3_DM2 0x40005134u +#define CYDEV_IO_PRT_PRT3_SLW 0x40005135u +#define CYDEV_IO_PRT_PRT3_BYP 0x40005136u +#define CYDEV_IO_PRT_PRT3_BIE 0x40005137u +#define CYDEV_IO_PRT_PRT3_INP_DIS 0x40005138u +#define CYDEV_IO_PRT_PRT3_CTL 0x40005139u +#define CYDEV_IO_PRT_PRT3_PRT 0x4000513au +#define CYDEV_IO_PRT_PRT3_BIT_MASK 0x4000513bu +#define CYDEV_IO_PRT_PRT3_AMUX 0x4000513cu +#define CYDEV_IO_PRT_PRT3_AG 0x4000513du +#define CYDEV_IO_PRT_PRT3_LCD_COM_SEG 0x4000513eu +#define CYDEV_IO_PRT_PRT3_LCD_EN 0x4000513fu +#define CYDEV_IO_PRT_PRT4_BASE 0x40005140u +#define CYDEV_IO_PRT_PRT4_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT4_DR 0x40005140u +#define CYDEV_IO_PRT_PRT4_PS 0x40005141u +#define CYDEV_IO_PRT_PRT4_DM0 0x40005142u +#define CYDEV_IO_PRT_PRT4_DM1 0x40005143u +#define CYDEV_IO_PRT_PRT4_DM2 0x40005144u +#define CYDEV_IO_PRT_PRT4_SLW 0x40005145u +#define CYDEV_IO_PRT_PRT4_BYP 0x40005146u +#define CYDEV_IO_PRT_PRT4_BIE 0x40005147u +#define CYDEV_IO_PRT_PRT4_INP_DIS 0x40005148u +#define CYDEV_IO_PRT_PRT4_CTL 0x40005149u +#define CYDEV_IO_PRT_PRT4_PRT 0x4000514au +#define CYDEV_IO_PRT_PRT4_BIT_MASK 0x4000514bu +#define CYDEV_IO_PRT_PRT4_AMUX 0x4000514cu +#define CYDEV_IO_PRT_PRT4_AG 0x4000514du +#define CYDEV_IO_PRT_PRT4_LCD_COM_SEG 0x4000514eu +#define CYDEV_IO_PRT_PRT4_LCD_EN 0x4000514fu +#define CYDEV_IO_PRT_PRT5_BASE 0x40005150u +#define CYDEV_IO_PRT_PRT5_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT5_DR 0x40005150u +#define CYDEV_IO_PRT_PRT5_PS 0x40005151u +#define CYDEV_IO_PRT_PRT5_DM0 0x40005152u +#define CYDEV_IO_PRT_PRT5_DM1 0x40005153u +#define CYDEV_IO_PRT_PRT5_DM2 0x40005154u +#define CYDEV_IO_PRT_PRT5_SLW 0x40005155u +#define CYDEV_IO_PRT_PRT5_BYP 0x40005156u +#define CYDEV_IO_PRT_PRT5_BIE 0x40005157u +#define CYDEV_IO_PRT_PRT5_INP_DIS 0x40005158u +#define CYDEV_IO_PRT_PRT5_CTL 0x40005159u +#define CYDEV_IO_PRT_PRT5_PRT 0x4000515au +#define CYDEV_IO_PRT_PRT5_BIT_MASK 0x4000515bu +#define CYDEV_IO_PRT_PRT5_AMUX 0x4000515cu +#define CYDEV_IO_PRT_PRT5_AG 0x4000515du +#define CYDEV_IO_PRT_PRT5_LCD_COM_SEG 0x4000515eu +#define CYDEV_IO_PRT_PRT5_LCD_EN 0x4000515fu +#define CYDEV_IO_PRT_PRT6_BASE 0x40005160u +#define CYDEV_IO_PRT_PRT6_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT6_DR 0x40005160u +#define CYDEV_IO_PRT_PRT6_PS 0x40005161u +#define CYDEV_IO_PRT_PRT6_DM0 0x40005162u +#define CYDEV_IO_PRT_PRT6_DM1 0x40005163u +#define CYDEV_IO_PRT_PRT6_DM2 0x40005164u +#define CYDEV_IO_PRT_PRT6_SLW 0x40005165u +#define CYDEV_IO_PRT_PRT6_BYP 0x40005166u +#define CYDEV_IO_PRT_PRT6_BIE 0x40005167u +#define CYDEV_IO_PRT_PRT6_INP_DIS 0x40005168u +#define CYDEV_IO_PRT_PRT6_CTL 0x40005169u +#define CYDEV_IO_PRT_PRT6_PRT 0x4000516au +#define CYDEV_IO_PRT_PRT6_BIT_MASK 0x4000516bu +#define CYDEV_IO_PRT_PRT6_AMUX 0x4000516cu +#define CYDEV_IO_PRT_PRT6_AG 0x4000516du +#define CYDEV_IO_PRT_PRT6_LCD_COM_SEG 0x4000516eu +#define CYDEV_IO_PRT_PRT6_LCD_EN 0x4000516fu +#define CYDEV_IO_PRT_PRT12_BASE 0x400051c0u +#define CYDEV_IO_PRT_PRT12_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT12_DR 0x400051c0u +#define CYDEV_IO_PRT_PRT12_PS 0x400051c1u +#define CYDEV_IO_PRT_PRT12_DM0 0x400051c2u +#define CYDEV_IO_PRT_PRT12_DM1 0x400051c3u +#define CYDEV_IO_PRT_PRT12_DM2 0x400051c4u +#define CYDEV_IO_PRT_PRT12_SLW 0x400051c5u +#define CYDEV_IO_PRT_PRT12_BYP 0x400051c6u +#define CYDEV_IO_PRT_PRT12_BIE 0x400051c7u +#define CYDEV_IO_PRT_PRT12_INP_DIS 0x400051c8u +#define CYDEV_IO_PRT_PRT12_SIO_HYST_EN 0x400051c9u +#define CYDEV_IO_PRT_PRT12_PRT 0x400051cau +#define CYDEV_IO_PRT_PRT12_BIT_MASK 0x400051cbu +#define CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ 0x400051ccu +#define CYDEV_IO_PRT_PRT12_AG 0x400051cdu +#define CYDEV_IO_PRT_PRT12_SIO_CFG 0x400051ceu +#define CYDEV_IO_PRT_PRT12_SIO_DIFF 0x400051cfu +#define CYDEV_IO_PRT_PRT15_BASE 0x400051f0u +#define CYDEV_IO_PRT_PRT15_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT15_DR 0x400051f0u +#define CYDEV_IO_PRT_PRT15_PS 0x400051f1u +#define CYDEV_IO_PRT_PRT15_DM0 0x400051f2u +#define CYDEV_IO_PRT_PRT15_DM1 0x400051f3u +#define CYDEV_IO_PRT_PRT15_DM2 0x400051f4u +#define CYDEV_IO_PRT_PRT15_SLW 0x400051f5u +#define CYDEV_IO_PRT_PRT15_BYP 0x400051f6u +#define CYDEV_IO_PRT_PRT15_BIE 0x400051f7u +#define CYDEV_IO_PRT_PRT15_INP_DIS 0x400051f8u +#define CYDEV_IO_PRT_PRT15_CTL 0x400051f9u +#define CYDEV_IO_PRT_PRT15_PRT 0x400051fau +#define CYDEV_IO_PRT_PRT15_BIT_MASK 0x400051fbu +#define CYDEV_IO_PRT_PRT15_AMUX 0x400051fcu +#define CYDEV_IO_PRT_PRT15_AG 0x400051fdu +#define CYDEV_IO_PRT_PRT15_LCD_COM_SEG 0x400051feu +#define CYDEV_IO_PRT_PRT15_LCD_EN 0x400051ffu +#define CYDEV_PRTDSI_BASE 0x40005200u +#define CYDEV_PRTDSI_SIZE 0x0000007fu +#define CYDEV_PRTDSI_PRT0_BASE 0x40005200u +#define CYDEV_PRTDSI_PRT0_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT0_OUT_SEL0 0x40005200u +#define CYDEV_PRTDSI_PRT0_OUT_SEL1 0x40005201u +#define CYDEV_PRTDSI_PRT0_OE_SEL0 0x40005202u +#define CYDEV_PRTDSI_PRT0_OE_SEL1 0x40005203u +#define CYDEV_PRTDSI_PRT0_DBL_SYNC_IN 0x40005204u +#define CYDEV_PRTDSI_PRT0_SYNC_OUT 0x40005205u +#define CYDEV_PRTDSI_PRT0_CAPS_SEL 0x40005206u +#define CYDEV_PRTDSI_PRT1_BASE 0x40005208u +#define CYDEV_PRTDSI_PRT1_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT1_OUT_SEL0 0x40005208u +#define CYDEV_PRTDSI_PRT1_OUT_SEL1 0x40005209u +#define CYDEV_PRTDSI_PRT1_OE_SEL0 0x4000520au +#define CYDEV_PRTDSI_PRT1_OE_SEL1 0x4000520bu +#define CYDEV_PRTDSI_PRT1_DBL_SYNC_IN 0x4000520cu +#define CYDEV_PRTDSI_PRT1_SYNC_OUT 0x4000520du +#define CYDEV_PRTDSI_PRT1_CAPS_SEL 0x4000520eu +#define CYDEV_PRTDSI_PRT2_BASE 0x40005210u +#define CYDEV_PRTDSI_PRT2_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT2_OUT_SEL0 0x40005210u +#define CYDEV_PRTDSI_PRT2_OUT_SEL1 0x40005211u +#define CYDEV_PRTDSI_PRT2_OE_SEL0 0x40005212u +#define CYDEV_PRTDSI_PRT2_OE_SEL1 0x40005213u +#define CYDEV_PRTDSI_PRT2_DBL_SYNC_IN 0x40005214u +#define CYDEV_PRTDSI_PRT2_SYNC_OUT 0x40005215u +#define CYDEV_PRTDSI_PRT2_CAPS_SEL 0x40005216u +#define CYDEV_PRTDSI_PRT3_BASE 0x40005218u +#define CYDEV_PRTDSI_PRT3_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT3_OUT_SEL0 0x40005218u +#define CYDEV_PRTDSI_PRT3_OUT_SEL1 0x40005219u +#define CYDEV_PRTDSI_PRT3_OE_SEL0 0x4000521au +#define CYDEV_PRTDSI_PRT3_OE_SEL1 0x4000521bu +#define CYDEV_PRTDSI_PRT3_DBL_SYNC_IN 0x4000521cu +#define CYDEV_PRTDSI_PRT3_SYNC_OUT 0x4000521du +#define CYDEV_PRTDSI_PRT3_CAPS_SEL 0x4000521eu +#define CYDEV_PRTDSI_PRT4_BASE 0x40005220u +#define CYDEV_PRTDSI_PRT4_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT4_OUT_SEL0 0x40005220u +#define CYDEV_PRTDSI_PRT4_OUT_SEL1 0x40005221u +#define CYDEV_PRTDSI_PRT4_OE_SEL0 0x40005222u +#define CYDEV_PRTDSI_PRT4_OE_SEL1 0x40005223u +#define CYDEV_PRTDSI_PRT4_DBL_SYNC_IN 0x40005224u +#define CYDEV_PRTDSI_PRT4_SYNC_OUT 0x40005225u +#define CYDEV_PRTDSI_PRT4_CAPS_SEL 0x40005226u +#define CYDEV_PRTDSI_PRT5_BASE 0x40005228u +#define CYDEV_PRTDSI_PRT5_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT5_OUT_SEL0 0x40005228u +#define CYDEV_PRTDSI_PRT5_OUT_SEL1 0x40005229u +#define CYDEV_PRTDSI_PRT5_OE_SEL0 0x4000522au +#define CYDEV_PRTDSI_PRT5_OE_SEL1 0x4000522bu +#define CYDEV_PRTDSI_PRT5_DBL_SYNC_IN 0x4000522cu +#define CYDEV_PRTDSI_PRT5_SYNC_OUT 0x4000522du +#define CYDEV_PRTDSI_PRT5_CAPS_SEL 0x4000522eu +#define CYDEV_PRTDSI_PRT6_BASE 0x40005230u +#define CYDEV_PRTDSI_PRT6_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT6_OUT_SEL0 0x40005230u +#define CYDEV_PRTDSI_PRT6_OUT_SEL1 0x40005231u +#define CYDEV_PRTDSI_PRT6_OE_SEL0 0x40005232u +#define CYDEV_PRTDSI_PRT6_OE_SEL1 0x40005233u +#define CYDEV_PRTDSI_PRT6_DBL_SYNC_IN 0x40005234u +#define CYDEV_PRTDSI_PRT6_SYNC_OUT 0x40005235u +#define CYDEV_PRTDSI_PRT6_CAPS_SEL 0x40005236u +#define CYDEV_PRTDSI_PRT12_BASE 0x40005260u +#define CYDEV_PRTDSI_PRT12_SIZE 0x00000006u +#define CYDEV_PRTDSI_PRT12_OUT_SEL0 0x40005260u +#define CYDEV_PRTDSI_PRT12_OUT_SEL1 0x40005261u +#define CYDEV_PRTDSI_PRT12_OE_SEL0 0x40005262u +#define CYDEV_PRTDSI_PRT12_OE_SEL1 0x40005263u +#define CYDEV_PRTDSI_PRT12_DBL_SYNC_IN 0x40005264u +#define CYDEV_PRTDSI_PRT12_SYNC_OUT 0x40005265u +#define CYDEV_PRTDSI_PRT15_BASE 0x40005278u +#define CYDEV_PRTDSI_PRT15_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT15_OUT_SEL0 0x40005278u +#define CYDEV_PRTDSI_PRT15_OUT_SEL1 0x40005279u +#define CYDEV_PRTDSI_PRT15_OE_SEL0 0x4000527au +#define CYDEV_PRTDSI_PRT15_OE_SEL1 0x4000527bu +#define CYDEV_PRTDSI_PRT15_DBL_SYNC_IN 0x4000527cu +#define CYDEV_PRTDSI_PRT15_SYNC_OUT 0x4000527du +#define CYDEV_PRTDSI_PRT15_CAPS_SEL 0x4000527eu +#define CYDEV_EMIF_BASE 0x40005400u +#define CYDEV_EMIF_SIZE 0x00000007u +#define CYDEV_EMIF_NO_UDB 0x40005400u +#define CYDEV_EMIF_RP_WAIT_STATES 0x40005401u +#define CYDEV_EMIF_MEM_DWN 0x40005402u +#define CYDEV_EMIF_MEMCLK_DIV 0x40005403u +#define CYDEV_EMIF_CLOCK_EN 0x40005404u +#define CYDEV_EMIF_EM_TYPE 0x40005405u +#define CYDEV_EMIF_WP_WAIT_STATES 0x40005406u +#define CYDEV_ANAIF_BASE 0x40005800u +#define CYDEV_ANAIF_SIZE 0x000003a9u +#define CYDEV_ANAIF_CFG_BASE 0x40005800u +#define CYDEV_ANAIF_CFG_SIZE 0x0000010fu +#define CYDEV_ANAIF_CFG_SC0_BASE 0x40005800u +#define CYDEV_ANAIF_CFG_SC0_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_SC0_CR0 0x40005800u +#define CYDEV_ANAIF_CFG_SC0_CR1 0x40005801u +#define CYDEV_ANAIF_CFG_SC0_CR2 0x40005802u +#define CYDEV_ANAIF_CFG_SC1_BASE 0x40005804u +#define CYDEV_ANAIF_CFG_SC1_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_SC1_CR0 0x40005804u +#define CYDEV_ANAIF_CFG_SC1_CR1 0x40005805u +#define CYDEV_ANAIF_CFG_SC1_CR2 0x40005806u +#define CYDEV_ANAIF_CFG_SC2_BASE 0x40005808u +#define CYDEV_ANAIF_CFG_SC2_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_SC2_CR0 0x40005808u +#define CYDEV_ANAIF_CFG_SC2_CR1 0x40005809u +#define CYDEV_ANAIF_CFG_SC2_CR2 0x4000580au +#define CYDEV_ANAIF_CFG_SC3_BASE 0x4000580cu +#define CYDEV_ANAIF_CFG_SC3_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_SC3_CR0 0x4000580cu +#define CYDEV_ANAIF_CFG_SC3_CR1 0x4000580du +#define CYDEV_ANAIF_CFG_SC3_CR2 0x4000580eu +#define CYDEV_ANAIF_CFG_DAC0_BASE 0x40005820u +#define CYDEV_ANAIF_CFG_DAC0_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_DAC0_CR0 0x40005820u +#define CYDEV_ANAIF_CFG_DAC0_CR1 0x40005821u +#define CYDEV_ANAIF_CFG_DAC0_TST 0x40005822u +#define CYDEV_ANAIF_CFG_DAC1_BASE 0x40005824u +#define CYDEV_ANAIF_CFG_DAC1_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_DAC1_CR0 0x40005824u +#define CYDEV_ANAIF_CFG_DAC1_CR1 0x40005825u +#define CYDEV_ANAIF_CFG_DAC1_TST 0x40005826u +#define CYDEV_ANAIF_CFG_DAC2_BASE 0x40005828u +#define CYDEV_ANAIF_CFG_DAC2_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_DAC2_CR0 0x40005828u +#define CYDEV_ANAIF_CFG_DAC2_CR1 0x40005829u +#define CYDEV_ANAIF_CFG_DAC2_TST 0x4000582au +#define CYDEV_ANAIF_CFG_DAC3_BASE 0x4000582cu +#define CYDEV_ANAIF_CFG_DAC3_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_DAC3_CR0 0x4000582cu +#define CYDEV_ANAIF_CFG_DAC3_CR1 0x4000582du +#define CYDEV_ANAIF_CFG_DAC3_TST 0x4000582eu +#define CYDEV_ANAIF_CFG_CMP0_BASE 0x40005840u +#define CYDEV_ANAIF_CFG_CMP0_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_CMP0_CR 0x40005840u +#define CYDEV_ANAIF_CFG_CMP1_BASE 0x40005841u +#define CYDEV_ANAIF_CFG_CMP1_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_CMP1_CR 0x40005841u +#define CYDEV_ANAIF_CFG_CMP2_BASE 0x40005842u +#define CYDEV_ANAIF_CFG_CMP2_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_CMP2_CR 0x40005842u +#define CYDEV_ANAIF_CFG_CMP3_BASE 0x40005843u +#define CYDEV_ANAIF_CFG_CMP3_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_CMP3_CR 0x40005843u +#define CYDEV_ANAIF_CFG_LUT0_BASE 0x40005848u +#define CYDEV_ANAIF_CFG_LUT0_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LUT0_CR 0x40005848u +#define CYDEV_ANAIF_CFG_LUT0_MX 0x40005849u +#define CYDEV_ANAIF_CFG_LUT1_BASE 0x4000584au +#define CYDEV_ANAIF_CFG_LUT1_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LUT1_CR 0x4000584au +#define CYDEV_ANAIF_CFG_LUT1_MX 0x4000584bu +#define CYDEV_ANAIF_CFG_LUT2_BASE 0x4000584cu +#define CYDEV_ANAIF_CFG_LUT2_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LUT2_CR 0x4000584cu +#define CYDEV_ANAIF_CFG_LUT2_MX 0x4000584du +#define CYDEV_ANAIF_CFG_LUT3_BASE 0x4000584eu +#define CYDEV_ANAIF_CFG_LUT3_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LUT3_CR 0x4000584eu +#define CYDEV_ANAIF_CFG_LUT3_MX 0x4000584fu +#define CYDEV_ANAIF_CFG_OPAMP0_BASE 0x40005858u +#define CYDEV_ANAIF_CFG_OPAMP0_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_OPAMP0_CR 0x40005858u +#define CYDEV_ANAIF_CFG_OPAMP0_RSVD 0x40005859u +#define CYDEV_ANAIF_CFG_OPAMP1_BASE 0x4000585au +#define CYDEV_ANAIF_CFG_OPAMP1_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_OPAMP1_CR 0x4000585au +#define CYDEV_ANAIF_CFG_OPAMP1_RSVD 0x4000585bu +#define CYDEV_ANAIF_CFG_OPAMP2_BASE 0x4000585cu +#define CYDEV_ANAIF_CFG_OPAMP2_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_OPAMP2_CR 0x4000585cu +#define CYDEV_ANAIF_CFG_OPAMP2_RSVD 0x4000585du +#define CYDEV_ANAIF_CFG_OPAMP3_BASE 0x4000585eu +#define CYDEV_ANAIF_CFG_OPAMP3_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_OPAMP3_CR 0x4000585eu +#define CYDEV_ANAIF_CFG_OPAMP3_RSVD 0x4000585fu +#define CYDEV_ANAIF_CFG_LCDDAC_BASE 0x40005868u +#define CYDEV_ANAIF_CFG_LCDDAC_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LCDDAC_CR0 0x40005868u +#define CYDEV_ANAIF_CFG_LCDDAC_CR1 0x40005869u +#define CYDEV_ANAIF_CFG_LCDDRV_BASE 0x4000586au +#define CYDEV_ANAIF_CFG_LCDDRV_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_LCDDRV_CR 0x4000586au +#define CYDEV_ANAIF_CFG_LCDTMR_BASE 0x4000586bu +#define CYDEV_ANAIF_CFG_LCDTMR_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_LCDTMR_CFG 0x4000586bu +#define CYDEV_ANAIF_CFG_BG_BASE 0x4000586cu +#define CYDEV_ANAIF_CFG_BG_SIZE 0x00000004u +#define CYDEV_ANAIF_CFG_BG_CR0 0x4000586cu +#define CYDEV_ANAIF_CFG_BG_RSVD 0x4000586du +#define CYDEV_ANAIF_CFG_BG_DFT0 0x4000586eu +#define CYDEV_ANAIF_CFG_BG_DFT1 0x4000586fu +#define CYDEV_ANAIF_CFG_CAPSL_BASE 0x40005870u +#define CYDEV_ANAIF_CFG_CAPSL_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_CAPSL_CFG0 0x40005870u +#define CYDEV_ANAIF_CFG_CAPSL_CFG1 0x40005871u +#define CYDEV_ANAIF_CFG_CAPSR_BASE 0x40005872u +#define CYDEV_ANAIF_CFG_CAPSR_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_CAPSR_CFG0 0x40005872u +#define CYDEV_ANAIF_CFG_CAPSR_CFG1 0x40005873u +#define CYDEV_ANAIF_CFG_PUMP_BASE 0x40005876u +#define CYDEV_ANAIF_CFG_PUMP_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_PUMP_CR0 0x40005876u +#define CYDEV_ANAIF_CFG_PUMP_CR1 0x40005877u +#define CYDEV_ANAIF_CFG_LPF0_BASE 0x40005878u +#define CYDEV_ANAIF_CFG_LPF0_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LPF0_CR0 0x40005878u +#define CYDEV_ANAIF_CFG_LPF0_RSVD 0x40005879u +#define CYDEV_ANAIF_CFG_LPF1_BASE 0x4000587au +#define CYDEV_ANAIF_CFG_LPF1_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LPF1_CR0 0x4000587au +#define CYDEV_ANAIF_CFG_LPF1_RSVD 0x4000587bu +#define CYDEV_ANAIF_CFG_MISC_BASE 0x4000587cu +#define CYDEV_ANAIF_CFG_MISC_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_MISC_CR0 0x4000587cu +#define CYDEV_ANAIF_CFG_DSM0_BASE 0x40005880u +#define CYDEV_ANAIF_CFG_DSM0_SIZE 0x00000020u +#define CYDEV_ANAIF_CFG_DSM0_CR0 0x40005880u +#define CYDEV_ANAIF_CFG_DSM0_CR1 0x40005881u +#define CYDEV_ANAIF_CFG_DSM0_CR2 0x40005882u +#define CYDEV_ANAIF_CFG_DSM0_CR3 0x40005883u +#define CYDEV_ANAIF_CFG_DSM0_CR4 0x40005884u +#define CYDEV_ANAIF_CFG_DSM0_CR5 0x40005885u +#define CYDEV_ANAIF_CFG_DSM0_CR6 0x40005886u +#define CYDEV_ANAIF_CFG_DSM0_CR7 0x40005887u +#define CYDEV_ANAIF_CFG_DSM0_CR8 0x40005888u +#define CYDEV_ANAIF_CFG_DSM0_CR9 0x40005889u +#define CYDEV_ANAIF_CFG_DSM0_CR10 0x4000588au +#define CYDEV_ANAIF_CFG_DSM0_CR11 0x4000588bu +#define CYDEV_ANAIF_CFG_DSM0_CR12 0x4000588cu +#define CYDEV_ANAIF_CFG_DSM0_CR13 0x4000588du +#define CYDEV_ANAIF_CFG_DSM0_CR14 0x4000588eu +#define CYDEV_ANAIF_CFG_DSM0_CR15 0x4000588fu +#define CYDEV_ANAIF_CFG_DSM0_CR16 0x40005890u +#define CYDEV_ANAIF_CFG_DSM0_CR17 0x40005891u +#define CYDEV_ANAIF_CFG_DSM0_REF0 0x40005892u +#define CYDEV_ANAIF_CFG_DSM0_REF1 0x40005893u +#define CYDEV_ANAIF_CFG_DSM0_REF2 0x40005894u +#define CYDEV_ANAIF_CFG_DSM0_REF3 0x40005895u +#define CYDEV_ANAIF_CFG_DSM0_DEM0 0x40005896u +#define CYDEV_ANAIF_CFG_DSM0_DEM1 0x40005897u +#define CYDEV_ANAIF_CFG_DSM0_TST0 0x40005898u +#define CYDEV_ANAIF_CFG_DSM0_TST1 0x40005899u +#define CYDEV_ANAIF_CFG_DSM0_BUF0 0x4000589au +#define CYDEV_ANAIF_CFG_DSM0_BUF1 0x4000589bu +#define CYDEV_ANAIF_CFG_DSM0_BUF2 0x4000589cu +#define CYDEV_ANAIF_CFG_DSM0_BUF3 0x4000589du +#define CYDEV_ANAIF_CFG_DSM0_MISC 0x4000589eu +#define CYDEV_ANAIF_CFG_DSM0_RSVD1 0x4000589fu +#define CYDEV_ANAIF_CFG_SAR0_BASE 0x40005900u +#define CYDEV_ANAIF_CFG_SAR0_SIZE 0x00000007u +#define CYDEV_ANAIF_CFG_SAR0_CSR0 0x40005900u +#define CYDEV_ANAIF_CFG_SAR0_CSR1 0x40005901u +#define CYDEV_ANAIF_CFG_SAR0_CSR2 0x40005902u +#define CYDEV_ANAIF_CFG_SAR0_CSR3 0x40005903u +#define CYDEV_ANAIF_CFG_SAR0_CSR4 0x40005904u +#define CYDEV_ANAIF_CFG_SAR0_CSR5 0x40005905u +#define CYDEV_ANAIF_CFG_SAR0_CSR6 0x40005906u +#define CYDEV_ANAIF_CFG_SAR1_BASE 0x40005908u +#define CYDEV_ANAIF_CFG_SAR1_SIZE 0x00000007u +#define CYDEV_ANAIF_CFG_SAR1_CSR0 0x40005908u +#define CYDEV_ANAIF_CFG_SAR1_CSR1 0x40005909u +#define CYDEV_ANAIF_CFG_SAR1_CSR2 0x4000590au +#define CYDEV_ANAIF_CFG_SAR1_CSR3 0x4000590bu +#define CYDEV_ANAIF_CFG_SAR1_CSR4 0x4000590cu +#define CYDEV_ANAIF_CFG_SAR1_CSR5 0x4000590du +#define CYDEV_ANAIF_CFG_SAR1_CSR6 0x4000590eu +#define CYDEV_ANAIF_RT_BASE 0x40005a00u +#define CYDEV_ANAIF_RT_SIZE 0x00000162u +#define CYDEV_ANAIF_RT_SC0_BASE 0x40005a00u +#define CYDEV_ANAIF_RT_SC0_SIZE 0x0000000du +#define CYDEV_ANAIF_RT_SC0_SW0 0x40005a00u +#define CYDEV_ANAIF_RT_SC0_SW2 0x40005a02u +#define CYDEV_ANAIF_RT_SC0_SW3 0x40005a03u +#define CYDEV_ANAIF_RT_SC0_SW4 0x40005a04u +#define CYDEV_ANAIF_RT_SC0_SW6 0x40005a06u +#define CYDEV_ANAIF_RT_SC0_SW7 0x40005a07u +#define CYDEV_ANAIF_RT_SC0_SW8 0x40005a08u +#define CYDEV_ANAIF_RT_SC0_SW10 0x40005a0au +#define CYDEV_ANAIF_RT_SC0_CLK 0x40005a0bu +#define CYDEV_ANAIF_RT_SC0_BST 0x40005a0cu +#define CYDEV_ANAIF_RT_SC1_BASE 0x40005a10u +#define CYDEV_ANAIF_RT_SC1_SIZE 0x0000000du +#define CYDEV_ANAIF_RT_SC1_SW0 0x40005a10u +#define CYDEV_ANAIF_RT_SC1_SW2 0x40005a12u +#define CYDEV_ANAIF_RT_SC1_SW3 0x40005a13u +#define CYDEV_ANAIF_RT_SC1_SW4 0x40005a14u +#define CYDEV_ANAIF_RT_SC1_SW6 0x40005a16u +#define CYDEV_ANAIF_RT_SC1_SW7 0x40005a17u +#define CYDEV_ANAIF_RT_SC1_SW8 0x40005a18u +#define CYDEV_ANAIF_RT_SC1_SW10 0x40005a1au +#define CYDEV_ANAIF_RT_SC1_CLK 0x40005a1bu +#define CYDEV_ANAIF_RT_SC1_BST 0x40005a1cu +#define CYDEV_ANAIF_RT_SC2_BASE 0x40005a20u +#define CYDEV_ANAIF_RT_SC2_SIZE 0x0000000du +#define CYDEV_ANAIF_RT_SC2_SW0 0x40005a20u +#define CYDEV_ANAIF_RT_SC2_SW2 0x40005a22u +#define CYDEV_ANAIF_RT_SC2_SW3 0x40005a23u +#define CYDEV_ANAIF_RT_SC2_SW4 0x40005a24u +#define CYDEV_ANAIF_RT_SC2_SW6 0x40005a26u +#define CYDEV_ANAIF_RT_SC2_SW7 0x40005a27u +#define CYDEV_ANAIF_RT_SC2_SW8 0x40005a28u +#define CYDEV_ANAIF_RT_SC2_SW10 0x40005a2au +#define CYDEV_ANAIF_RT_SC2_CLK 0x40005a2bu +#define CYDEV_ANAIF_RT_SC2_BST 0x40005a2cu +#define CYDEV_ANAIF_RT_SC3_BASE 0x40005a30u +#define CYDEV_ANAIF_RT_SC3_SIZE 0x0000000du +#define CYDEV_ANAIF_RT_SC3_SW0 0x40005a30u +#define CYDEV_ANAIF_RT_SC3_SW2 0x40005a32u +#define CYDEV_ANAIF_RT_SC3_SW3 0x40005a33u +#define CYDEV_ANAIF_RT_SC3_SW4 0x40005a34u +#define CYDEV_ANAIF_RT_SC3_SW6 0x40005a36u +#define CYDEV_ANAIF_RT_SC3_SW7 0x40005a37u +#define CYDEV_ANAIF_RT_SC3_SW8 0x40005a38u +#define CYDEV_ANAIF_RT_SC3_SW10 0x40005a3au +#define CYDEV_ANAIF_RT_SC3_CLK 0x40005a3bu +#define CYDEV_ANAIF_RT_SC3_BST 0x40005a3cu +#define CYDEV_ANAIF_RT_DAC0_BASE 0x40005a80u +#define CYDEV_ANAIF_RT_DAC0_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_DAC0_SW0 0x40005a80u +#define CYDEV_ANAIF_RT_DAC0_SW2 0x40005a82u +#define CYDEV_ANAIF_RT_DAC0_SW3 0x40005a83u +#define CYDEV_ANAIF_RT_DAC0_SW4 0x40005a84u +#define CYDEV_ANAIF_RT_DAC0_STROBE 0x40005a87u +#define CYDEV_ANAIF_RT_DAC1_BASE 0x40005a88u +#define CYDEV_ANAIF_RT_DAC1_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_DAC1_SW0 0x40005a88u +#define CYDEV_ANAIF_RT_DAC1_SW2 0x40005a8au +#define CYDEV_ANAIF_RT_DAC1_SW3 0x40005a8bu +#define CYDEV_ANAIF_RT_DAC1_SW4 0x40005a8cu +#define CYDEV_ANAIF_RT_DAC1_STROBE 0x40005a8fu +#define CYDEV_ANAIF_RT_DAC2_BASE 0x40005a90u +#define CYDEV_ANAIF_RT_DAC2_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_DAC2_SW0 0x40005a90u +#define CYDEV_ANAIF_RT_DAC2_SW2 0x40005a92u +#define CYDEV_ANAIF_RT_DAC2_SW3 0x40005a93u +#define CYDEV_ANAIF_RT_DAC2_SW4 0x40005a94u +#define CYDEV_ANAIF_RT_DAC2_STROBE 0x40005a97u +#define CYDEV_ANAIF_RT_DAC3_BASE 0x40005a98u +#define CYDEV_ANAIF_RT_DAC3_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_DAC3_SW0 0x40005a98u +#define CYDEV_ANAIF_RT_DAC3_SW2 0x40005a9au +#define CYDEV_ANAIF_RT_DAC3_SW3 0x40005a9bu +#define CYDEV_ANAIF_RT_DAC3_SW4 0x40005a9cu +#define CYDEV_ANAIF_RT_DAC3_STROBE 0x40005a9fu +#define CYDEV_ANAIF_RT_CMP0_BASE 0x40005ac0u +#define CYDEV_ANAIF_RT_CMP0_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_CMP0_SW0 0x40005ac0u +#define CYDEV_ANAIF_RT_CMP0_SW2 0x40005ac2u +#define CYDEV_ANAIF_RT_CMP0_SW3 0x40005ac3u +#define CYDEV_ANAIF_RT_CMP0_SW4 0x40005ac4u +#define CYDEV_ANAIF_RT_CMP0_SW6 0x40005ac6u +#define CYDEV_ANAIF_RT_CMP0_CLK 0x40005ac7u +#define CYDEV_ANAIF_RT_CMP1_BASE 0x40005ac8u +#define CYDEV_ANAIF_RT_CMP1_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_CMP1_SW0 0x40005ac8u +#define CYDEV_ANAIF_RT_CMP1_SW2 0x40005acau +#define CYDEV_ANAIF_RT_CMP1_SW3 0x40005acbu +#define CYDEV_ANAIF_RT_CMP1_SW4 0x40005accu +#define CYDEV_ANAIF_RT_CMP1_SW6 0x40005aceu +#define CYDEV_ANAIF_RT_CMP1_CLK 0x40005acfu +#define CYDEV_ANAIF_RT_CMP2_BASE 0x40005ad0u +#define CYDEV_ANAIF_RT_CMP2_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_CMP2_SW0 0x40005ad0u +#define CYDEV_ANAIF_RT_CMP2_SW2 0x40005ad2u +#define CYDEV_ANAIF_RT_CMP2_SW3 0x40005ad3u +#define CYDEV_ANAIF_RT_CMP2_SW4 0x40005ad4u +#define CYDEV_ANAIF_RT_CMP2_SW6 0x40005ad6u +#define CYDEV_ANAIF_RT_CMP2_CLK 0x40005ad7u +#define CYDEV_ANAIF_RT_CMP3_BASE 0x40005ad8u +#define CYDEV_ANAIF_RT_CMP3_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_CMP3_SW0 0x40005ad8u +#define CYDEV_ANAIF_RT_CMP3_SW2 0x40005adau +#define CYDEV_ANAIF_RT_CMP3_SW3 0x40005adbu +#define CYDEV_ANAIF_RT_CMP3_SW4 0x40005adcu +#define CYDEV_ANAIF_RT_CMP3_SW6 0x40005adeu +#define CYDEV_ANAIF_RT_CMP3_CLK 0x40005adfu +#define CYDEV_ANAIF_RT_DSM0_BASE 0x40005b00u +#define CYDEV_ANAIF_RT_DSM0_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_DSM0_SW0 0x40005b00u +#define CYDEV_ANAIF_RT_DSM0_SW2 0x40005b02u +#define CYDEV_ANAIF_RT_DSM0_SW3 0x40005b03u +#define CYDEV_ANAIF_RT_DSM0_SW4 0x40005b04u +#define CYDEV_ANAIF_RT_DSM0_SW6 0x40005b06u +#define CYDEV_ANAIF_RT_DSM0_CLK 0x40005b07u +#define CYDEV_ANAIF_RT_SAR0_BASE 0x40005b20u +#define CYDEV_ANAIF_RT_SAR0_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_SAR0_SW0 0x40005b20u +#define CYDEV_ANAIF_RT_SAR0_SW2 0x40005b22u +#define CYDEV_ANAIF_RT_SAR0_SW3 0x40005b23u +#define CYDEV_ANAIF_RT_SAR0_SW4 0x40005b24u +#define CYDEV_ANAIF_RT_SAR0_SW6 0x40005b26u +#define CYDEV_ANAIF_RT_SAR0_CLK 0x40005b27u +#define CYDEV_ANAIF_RT_SAR1_BASE 0x40005b28u +#define CYDEV_ANAIF_RT_SAR1_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_SAR1_SW0 0x40005b28u +#define CYDEV_ANAIF_RT_SAR1_SW2 0x40005b2au +#define CYDEV_ANAIF_RT_SAR1_SW3 0x40005b2bu +#define CYDEV_ANAIF_RT_SAR1_SW4 0x40005b2cu +#define CYDEV_ANAIF_RT_SAR1_SW6 0x40005b2eu +#define CYDEV_ANAIF_RT_SAR1_CLK 0x40005b2fu +#define CYDEV_ANAIF_RT_OPAMP0_BASE 0x40005b40u +#define CYDEV_ANAIF_RT_OPAMP0_SIZE 0x00000002u +#define CYDEV_ANAIF_RT_OPAMP0_MX 0x40005b40u +#define CYDEV_ANAIF_RT_OPAMP0_SW 0x40005b41u +#define CYDEV_ANAIF_RT_OPAMP1_BASE 0x40005b42u +#define CYDEV_ANAIF_RT_OPAMP1_SIZE 0x00000002u +#define CYDEV_ANAIF_RT_OPAMP1_MX 0x40005b42u +#define CYDEV_ANAIF_RT_OPAMP1_SW 0x40005b43u +#define CYDEV_ANAIF_RT_OPAMP2_BASE 0x40005b44u +#define CYDEV_ANAIF_RT_OPAMP2_SIZE 0x00000002u +#define CYDEV_ANAIF_RT_OPAMP2_MX 0x40005b44u +#define CYDEV_ANAIF_RT_OPAMP2_SW 0x40005b45u +#define CYDEV_ANAIF_RT_OPAMP3_BASE 0x40005b46u +#define CYDEV_ANAIF_RT_OPAMP3_SIZE 0x00000002u +#define CYDEV_ANAIF_RT_OPAMP3_MX 0x40005b46u +#define CYDEV_ANAIF_RT_OPAMP3_SW 0x40005b47u +#define CYDEV_ANAIF_RT_LCDDAC_BASE 0x40005b50u +#define CYDEV_ANAIF_RT_LCDDAC_SIZE 0x00000005u +#define CYDEV_ANAIF_RT_LCDDAC_SW0 0x40005b50u +#define CYDEV_ANAIF_RT_LCDDAC_SW1 0x40005b51u +#define CYDEV_ANAIF_RT_LCDDAC_SW2 0x40005b52u +#define CYDEV_ANAIF_RT_LCDDAC_SW3 0x40005b53u +#define CYDEV_ANAIF_RT_LCDDAC_SW4 0x40005b54u +#define CYDEV_ANAIF_RT_SC_BASE 0x40005b56u +#define CYDEV_ANAIF_RT_SC_SIZE 0x00000001u +#define CYDEV_ANAIF_RT_SC_MISC 0x40005b56u +#define CYDEV_ANAIF_RT_BUS_BASE 0x40005b58u +#define CYDEV_ANAIF_RT_BUS_SIZE 0x00000004u +#define CYDEV_ANAIF_RT_BUS_SW0 0x40005b58u +#define CYDEV_ANAIF_RT_BUS_SW2 0x40005b5au +#define CYDEV_ANAIF_RT_BUS_SW3 0x40005b5bu +#define CYDEV_ANAIF_RT_DFT_BASE 0x40005b5cu +#define CYDEV_ANAIF_RT_DFT_SIZE 0x00000006u +#define CYDEV_ANAIF_RT_DFT_CR0 0x40005b5cu +#define CYDEV_ANAIF_RT_DFT_CR1 0x40005b5du +#define CYDEV_ANAIF_RT_DFT_CR2 0x40005b5eu +#define CYDEV_ANAIF_RT_DFT_CR3 0x40005b5fu +#define CYDEV_ANAIF_RT_DFT_CR4 0x40005b60u +#define CYDEV_ANAIF_RT_DFT_CR5 0x40005b61u +#define CYDEV_ANAIF_WRK_BASE 0x40005b80u +#define CYDEV_ANAIF_WRK_SIZE 0x00000029u +#define CYDEV_ANAIF_WRK_DAC0_BASE 0x40005b80u +#define CYDEV_ANAIF_WRK_DAC0_SIZE 0x00000001u +#define CYDEV_ANAIF_WRK_DAC0_D 0x40005b80u +#define CYDEV_ANAIF_WRK_DAC1_BASE 0x40005b81u +#define CYDEV_ANAIF_WRK_DAC1_SIZE 0x00000001u +#define CYDEV_ANAIF_WRK_DAC1_D 0x40005b81u +#define CYDEV_ANAIF_WRK_DAC2_BASE 0x40005b82u +#define CYDEV_ANAIF_WRK_DAC2_SIZE 0x00000001u +#define CYDEV_ANAIF_WRK_DAC2_D 0x40005b82u +#define CYDEV_ANAIF_WRK_DAC3_BASE 0x40005b83u +#define CYDEV_ANAIF_WRK_DAC3_SIZE 0x00000001u +#define CYDEV_ANAIF_WRK_DAC3_D 0x40005b83u +#define CYDEV_ANAIF_WRK_DSM0_BASE 0x40005b88u +#define CYDEV_ANAIF_WRK_DSM0_SIZE 0x00000002u +#define CYDEV_ANAIF_WRK_DSM0_OUT0 0x40005b88u +#define CYDEV_ANAIF_WRK_DSM0_OUT1 0x40005b89u +#define CYDEV_ANAIF_WRK_LUT_BASE 0x40005b90u +#define CYDEV_ANAIF_WRK_LUT_SIZE 0x00000005u +#define CYDEV_ANAIF_WRK_LUT_SR 0x40005b90u +#define CYDEV_ANAIF_WRK_LUT_WRK1 0x40005b91u +#define CYDEV_ANAIF_WRK_LUT_MSK 0x40005b92u +#define CYDEV_ANAIF_WRK_LUT_CLK 0x40005b93u +#define CYDEV_ANAIF_WRK_LUT_CPTR 0x40005b94u +#define CYDEV_ANAIF_WRK_CMP_BASE 0x40005b96u +#define CYDEV_ANAIF_WRK_CMP_SIZE 0x00000002u +#define CYDEV_ANAIF_WRK_CMP_WRK 0x40005b96u +#define CYDEV_ANAIF_WRK_CMP_TST 0x40005b97u +#define CYDEV_ANAIF_WRK_SC_BASE 0x40005b98u +#define CYDEV_ANAIF_WRK_SC_SIZE 0x00000005u +#define CYDEV_ANAIF_WRK_SC_SR 0x40005b98u +#define CYDEV_ANAIF_WRK_SC_WRK1 0x40005b99u +#define CYDEV_ANAIF_WRK_SC_MSK 0x40005b9au +#define CYDEV_ANAIF_WRK_SC_CMPINV 0x40005b9bu +#define CYDEV_ANAIF_WRK_SC_CPTR 0x40005b9cu +#define CYDEV_ANAIF_WRK_SAR0_BASE 0x40005ba0u +#define CYDEV_ANAIF_WRK_SAR0_SIZE 0x00000002u +#define CYDEV_ANAIF_WRK_SAR0_WRK0 0x40005ba0u +#define CYDEV_ANAIF_WRK_SAR0_WRK1 0x40005ba1u +#define CYDEV_ANAIF_WRK_SAR1_BASE 0x40005ba2u +#define CYDEV_ANAIF_WRK_SAR1_SIZE 0x00000002u +#define CYDEV_ANAIF_WRK_SAR1_WRK0 0x40005ba2u +#define CYDEV_ANAIF_WRK_SAR1_WRK1 0x40005ba3u +#define CYDEV_ANAIF_WRK_SARS_BASE 0x40005ba8u +#define CYDEV_ANAIF_WRK_SARS_SIZE 0x00000001u +#define CYDEV_ANAIF_WRK_SARS_SOF 0x40005ba8u +#define CYDEV_USB_BASE 0x40006000u +#define CYDEV_USB_SIZE 0x00000300u +#define CYDEV_USB_EP0_DR0 0x40006000u +#define CYDEV_USB_EP0_DR1 0x40006001u +#define CYDEV_USB_EP0_DR2 0x40006002u +#define CYDEV_USB_EP0_DR3 0x40006003u +#define CYDEV_USB_EP0_DR4 0x40006004u +#define CYDEV_USB_EP0_DR5 0x40006005u +#define CYDEV_USB_EP0_DR6 0x40006006u +#define CYDEV_USB_EP0_DR7 0x40006007u +#define CYDEV_USB_CR0 0x40006008u +#define CYDEV_USB_CR1 0x40006009u +#define CYDEV_USB_SIE_EP_INT_EN 0x4000600au +#define CYDEV_USB_SIE_EP_INT_SR 0x4000600bu +#define CYDEV_USB_SIE_EP1_BASE 0x4000600cu +#define CYDEV_USB_SIE_EP1_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP1_CNT0 0x4000600cu +#define CYDEV_USB_SIE_EP1_CNT1 0x4000600du +#define CYDEV_USB_SIE_EP1_CR0 0x4000600eu +#define CYDEV_USB_USBIO_CR0 0x40006010u +#define CYDEV_USB_USBIO_CR1 0x40006012u +#define CYDEV_USB_DYN_RECONFIG 0x40006014u +#define CYDEV_USB_SOF0 0x40006018u +#define CYDEV_USB_SOF1 0x40006019u +#define CYDEV_USB_SIE_EP2_BASE 0x4000601cu +#define CYDEV_USB_SIE_EP2_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP2_CNT0 0x4000601cu +#define CYDEV_USB_SIE_EP2_CNT1 0x4000601du +#define CYDEV_USB_SIE_EP2_CR0 0x4000601eu +#define CYDEV_USB_EP0_CR 0x40006028u +#define CYDEV_USB_EP0_CNT 0x40006029u +#define CYDEV_USB_SIE_EP3_BASE 0x4000602cu +#define CYDEV_USB_SIE_EP3_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP3_CNT0 0x4000602cu +#define CYDEV_USB_SIE_EP3_CNT1 0x4000602du +#define CYDEV_USB_SIE_EP3_CR0 0x4000602eu +#define CYDEV_USB_SIE_EP4_BASE 0x4000603cu +#define CYDEV_USB_SIE_EP4_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP4_CNT0 0x4000603cu +#define CYDEV_USB_SIE_EP4_CNT1 0x4000603du +#define CYDEV_USB_SIE_EP4_CR0 0x4000603eu +#define CYDEV_USB_SIE_EP5_BASE 0x4000604cu +#define CYDEV_USB_SIE_EP5_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP5_CNT0 0x4000604cu +#define CYDEV_USB_SIE_EP5_CNT1 0x4000604du +#define CYDEV_USB_SIE_EP5_CR0 0x4000604eu +#define CYDEV_USB_SIE_EP6_BASE 0x4000605cu +#define CYDEV_USB_SIE_EP6_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP6_CNT0 0x4000605cu +#define CYDEV_USB_SIE_EP6_CNT1 0x4000605du +#define CYDEV_USB_SIE_EP6_CR0 0x4000605eu +#define CYDEV_USB_SIE_EP7_BASE 0x4000606cu +#define CYDEV_USB_SIE_EP7_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP7_CNT0 0x4000606cu +#define CYDEV_USB_SIE_EP7_CNT1 0x4000606du +#define CYDEV_USB_SIE_EP7_CR0 0x4000606eu +#define CYDEV_USB_SIE_EP8_BASE 0x4000607cu +#define CYDEV_USB_SIE_EP8_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP8_CNT0 0x4000607cu +#define CYDEV_USB_SIE_EP8_CNT1 0x4000607du +#define CYDEV_USB_SIE_EP8_CR0 0x4000607eu +#define CYDEV_USB_ARB_EP1_BASE 0x40006080u +#define CYDEV_USB_ARB_EP1_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP1_CFG 0x40006080u +#define CYDEV_USB_ARB_EP1_INT_EN 0x40006081u +#define CYDEV_USB_ARB_EP1_SR 0x40006082u +#define CYDEV_USB_ARB_RW1_BASE 0x40006084u +#define CYDEV_USB_ARB_RW1_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW1_WA 0x40006084u +#define CYDEV_USB_ARB_RW1_WA_MSB 0x40006085u +#define CYDEV_USB_ARB_RW1_RA 0x40006086u +#define CYDEV_USB_ARB_RW1_RA_MSB 0x40006087u +#define CYDEV_USB_ARB_RW1_DR 0x40006088u +#define CYDEV_USB_BUF_SIZE 0x4000608cu +#define CYDEV_USB_EP_ACTIVE 0x4000608eu +#define CYDEV_USB_EP_TYPE 0x4000608fu +#define CYDEV_USB_ARB_EP2_BASE 0x40006090u +#define CYDEV_USB_ARB_EP2_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP2_CFG 0x40006090u +#define CYDEV_USB_ARB_EP2_INT_EN 0x40006091u +#define CYDEV_USB_ARB_EP2_SR 0x40006092u +#define CYDEV_USB_ARB_RW2_BASE 0x40006094u +#define CYDEV_USB_ARB_RW2_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW2_WA 0x40006094u +#define CYDEV_USB_ARB_RW2_WA_MSB 0x40006095u +#define CYDEV_USB_ARB_RW2_RA 0x40006096u +#define CYDEV_USB_ARB_RW2_RA_MSB 0x40006097u +#define CYDEV_USB_ARB_RW2_DR 0x40006098u +#define CYDEV_USB_ARB_CFG 0x4000609cu +#define CYDEV_USB_USB_CLK_EN 0x4000609du +#define CYDEV_USB_ARB_INT_EN 0x4000609eu +#define CYDEV_USB_ARB_INT_SR 0x4000609fu +#define CYDEV_USB_ARB_EP3_BASE 0x400060a0u +#define CYDEV_USB_ARB_EP3_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP3_CFG 0x400060a0u +#define CYDEV_USB_ARB_EP3_INT_EN 0x400060a1u +#define CYDEV_USB_ARB_EP3_SR 0x400060a2u +#define CYDEV_USB_ARB_RW3_BASE 0x400060a4u +#define CYDEV_USB_ARB_RW3_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW3_WA 0x400060a4u +#define CYDEV_USB_ARB_RW3_WA_MSB 0x400060a5u +#define CYDEV_USB_ARB_RW3_RA 0x400060a6u +#define CYDEV_USB_ARB_RW3_RA_MSB 0x400060a7u +#define CYDEV_USB_ARB_RW3_DR 0x400060a8u +#define CYDEV_USB_CWA 0x400060acu +#define CYDEV_USB_CWA_MSB 0x400060adu +#define CYDEV_USB_ARB_EP4_BASE 0x400060b0u +#define CYDEV_USB_ARB_EP4_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP4_CFG 0x400060b0u +#define CYDEV_USB_ARB_EP4_INT_EN 0x400060b1u +#define CYDEV_USB_ARB_EP4_SR 0x400060b2u +#define CYDEV_USB_ARB_RW4_BASE 0x400060b4u +#define CYDEV_USB_ARB_RW4_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW4_WA 0x400060b4u +#define CYDEV_USB_ARB_RW4_WA_MSB 0x400060b5u +#define CYDEV_USB_ARB_RW4_RA 0x400060b6u +#define CYDEV_USB_ARB_RW4_RA_MSB 0x400060b7u +#define CYDEV_USB_ARB_RW4_DR 0x400060b8u +#define CYDEV_USB_DMA_THRES 0x400060bcu +#define CYDEV_USB_DMA_THRES_MSB 0x400060bdu +#define CYDEV_USB_ARB_EP5_BASE 0x400060c0u +#define CYDEV_USB_ARB_EP5_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP5_CFG 0x400060c0u +#define CYDEV_USB_ARB_EP5_INT_EN 0x400060c1u +#define CYDEV_USB_ARB_EP5_SR 0x400060c2u +#define CYDEV_USB_ARB_RW5_BASE 0x400060c4u +#define CYDEV_USB_ARB_RW5_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW5_WA 0x400060c4u +#define CYDEV_USB_ARB_RW5_WA_MSB 0x400060c5u +#define CYDEV_USB_ARB_RW5_RA 0x400060c6u +#define CYDEV_USB_ARB_RW5_RA_MSB 0x400060c7u +#define CYDEV_USB_ARB_RW5_DR 0x400060c8u +#define CYDEV_USB_BUS_RST_CNT 0x400060ccu +#define CYDEV_USB_ARB_EP6_BASE 0x400060d0u +#define CYDEV_USB_ARB_EP6_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP6_CFG 0x400060d0u +#define CYDEV_USB_ARB_EP6_INT_EN 0x400060d1u +#define CYDEV_USB_ARB_EP6_SR 0x400060d2u +#define CYDEV_USB_ARB_RW6_BASE 0x400060d4u +#define CYDEV_USB_ARB_RW6_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW6_WA 0x400060d4u +#define CYDEV_USB_ARB_RW6_WA_MSB 0x400060d5u +#define CYDEV_USB_ARB_RW6_RA 0x400060d6u +#define CYDEV_USB_ARB_RW6_RA_MSB 0x400060d7u +#define CYDEV_USB_ARB_RW6_DR 0x400060d8u +#define CYDEV_USB_ARB_EP7_BASE 0x400060e0u +#define CYDEV_USB_ARB_EP7_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP7_CFG 0x400060e0u +#define CYDEV_USB_ARB_EP7_INT_EN 0x400060e1u +#define CYDEV_USB_ARB_EP7_SR 0x400060e2u +#define CYDEV_USB_ARB_RW7_BASE 0x400060e4u +#define CYDEV_USB_ARB_RW7_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW7_WA 0x400060e4u +#define CYDEV_USB_ARB_RW7_WA_MSB 0x400060e5u +#define CYDEV_USB_ARB_RW7_RA 0x400060e6u +#define CYDEV_USB_ARB_RW7_RA_MSB 0x400060e7u +#define CYDEV_USB_ARB_RW7_DR 0x400060e8u +#define CYDEV_USB_ARB_EP8_BASE 0x400060f0u +#define CYDEV_USB_ARB_EP8_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP8_CFG 0x400060f0u +#define CYDEV_USB_ARB_EP8_INT_EN 0x400060f1u +#define CYDEV_USB_ARB_EP8_SR 0x400060f2u +#define CYDEV_USB_ARB_RW8_BASE 0x400060f4u +#define CYDEV_USB_ARB_RW8_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW8_WA 0x400060f4u +#define CYDEV_USB_ARB_RW8_WA_MSB 0x400060f5u +#define CYDEV_USB_ARB_RW8_RA 0x400060f6u +#define CYDEV_USB_ARB_RW8_RA_MSB 0x400060f7u +#define CYDEV_USB_ARB_RW8_DR 0x400060f8u +#define CYDEV_USB_MEM_BASE 0x40006100u +#define CYDEV_USB_MEM_SIZE 0x00000200u +#define CYDEV_USB_MEM_DATA_MBASE 0x40006100u +#define CYDEV_USB_MEM_DATA_MSIZE 0x00000200u +#define CYDEV_UWRK_BASE 0x40006400u +#define CYDEV_UWRK_SIZE 0x00000b60u +#define CYDEV_UWRK_UWRK8_BASE 0x40006400u +#define CYDEV_UWRK_UWRK8_SIZE 0x000003b0u +#define CYDEV_UWRK_UWRK8_B0_BASE 0x40006400u +#define CYDEV_UWRK_UWRK8_B0_SIZE 0x000000b0u +#define CYDEV_UWRK_UWRK8_B0_UDB00_A0 0x40006400u +#define CYDEV_UWRK_UWRK8_B0_UDB01_A0 0x40006401u +#define CYDEV_UWRK_UWRK8_B0_UDB02_A0 0x40006402u +#define CYDEV_UWRK_UWRK8_B0_UDB03_A0 0x40006403u +#define CYDEV_UWRK_UWRK8_B0_UDB04_A0 0x40006404u +#define CYDEV_UWRK_UWRK8_B0_UDB05_A0 0x40006405u +#define CYDEV_UWRK_UWRK8_B0_UDB06_A0 0x40006406u +#define CYDEV_UWRK_UWRK8_B0_UDB07_A0 0x40006407u +#define CYDEV_UWRK_UWRK8_B0_UDB08_A0 0x40006408u +#define CYDEV_UWRK_UWRK8_B0_UDB09_A0 0x40006409u +#define CYDEV_UWRK_UWRK8_B0_UDB10_A0 0x4000640au +#define CYDEV_UWRK_UWRK8_B0_UDB11_A0 0x4000640bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_A0 0x4000640cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_A0 0x4000640du +#define CYDEV_UWRK_UWRK8_B0_UDB14_A0 0x4000640eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_A0 0x4000640fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_A1 0x40006410u +#define CYDEV_UWRK_UWRK8_B0_UDB01_A1 0x40006411u +#define CYDEV_UWRK_UWRK8_B0_UDB02_A1 0x40006412u +#define CYDEV_UWRK_UWRK8_B0_UDB03_A1 0x40006413u +#define CYDEV_UWRK_UWRK8_B0_UDB04_A1 0x40006414u +#define CYDEV_UWRK_UWRK8_B0_UDB05_A1 0x40006415u +#define CYDEV_UWRK_UWRK8_B0_UDB06_A1 0x40006416u +#define CYDEV_UWRK_UWRK8_B0_UDB07_A1 0x40006417u +#define CYDEV_UWRK_UWRK8_B0_UDB08_A1 0x40006418u +#define CYDEV_UWRK_UWRK8_B0_UDB09_A1 0x40006419u +#define CYDEV_UWRK_UWRK8_B0_UDB10_A1 0x4000641au +#define CYDEV_UWRK_UWRK8_B0_UDB11_A1 0x4000641bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_A1 0x4000641cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_A1 0x4000641du +#define CYDEV_UWRK_UWRK8_B0_UDB14_A1 0x4000641eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_A1 0x4000641fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_D0 0x40006420u +#define CYDEV_UWRK_UWRK8_B0_UDB01_D0 0x40006421u +#define CYDEV_UWRK_UWRK8_B0_UDB02_D0 0x40006422u +#define CYDEV_UWRK_UWRK8_B0_UDB03_D0 0x40006423u +#define CYDEV_UWRK_UWRK8_B0_UDB04_D0 0x40006424u +#define CYDEV_UWRK_UWRK8_B0_UDB05_D0 0x40006425u +#define CYDEV_UWRK_UWRK8_B0_UDB06_D0 0x40006426u +#define CYDEV_UWRK_UWRK8_B0_UDB07_D0 0x40006427u +#define CYDEV_UWRK_UWRK8_B0_UDB08_D0 0x40006428u +#define CYDEV_UWRK_UWRK8_B0_UDB09_D0 0x40006429u +#define CYDEV_UWRK_UWRK8_B0_UDB10_D0 0x4000642au +#define CYDEV_UWRK_UWRK8_B0_UDB11_D0 0x4000642bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_D0 0x4000642cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_D0 0x4000642du +#define CYDEV_UWRK_UWRK8_B0_UDB14_D0 0x4000642eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_D0 0x4000642fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_D1 0x40006430u +#define CYDEV_UWRK_UWRK8_B0_UDB01_D1 0x40006431u +#define CYDEV_UWRK_UWRK8_B0_UDB02_D1 0x40006432u +#define CYDEV_UWRK_UWRK8_B0_UDB03_D1 0x40006433u +#define CYDEV_UWRK_UWRK8_B0_UDB04_D1 0x40006434u +#define CYDEV_UWRK_UWRK8_B0_UDB05_D1 0x40006435u +#define CYDEV_UWRK_UWRK8_B0_UDB06_D1 0x40006436u +#define CYDEV_UWRK_UWRK8_B0_UDB07_D1 0x40006437u +#define CYDEV_UWRK_UWRK8_B0_UDB08_D1 0x40006438u +#define CYDEV_UWRK_UWRK8_B0_UDB09_D1 0x40006439u +#define CYDEV_UWRK_UWRK8_B0_UDB10_D1 0x4000643au +#define CYDEV_UWRK_UWRK8_B0_UDB11_D1 0x4000643bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_D1 0x4000643cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_D1 0x4000643du +#define CYDEV_UWRK_UWRK8_B0_UDB14_D1 0x4000643eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_D1 0x4000643fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_F0 0x40006440u +#define CYDEV_UWRK_UWRK8_B0_UDB01_F0 0x40006441u +#define CYDEV_UWRK_UWRK8_B0_UDB02_F0 0x40006442u +#define CYDEV_UWRK_UWRK8_B0_UDB03_F0 0x40006443u +#define CYDEV_UWRK_UWRK8_B0_UDB04_F0 0x40006444u +#define CYDEV_UWRK_UWRK8_B0_UDB05_F0 0x40006445u +#define CYDEV_UWRK_UWRK8_B0_UDB06_F0 0x40006446u +#define CYDEV_UWRK_UWRK8_B0_UDB07_F0 0x40006447u +#define CYDEV_UWRK_UWRK8_B0_UDB08_F0 0x40006448u +#define CYDEV_UWRK_UWRK8_B0_UDB09_F0 0x40006449u +#define CYDEV_UWRK_UWRK8_B0_UDB10_F0 0x4000644au +#define CYDEV_UWRK_UWRK8_B0_UDB11_F0 0x4000644bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_F0 0x4000644cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_F0 0x4000644du +#define CYDEV_UWRK_UWRK8_B0_UDB14_F0 0x4000644eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_F0 0x4000644fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_F1 0x40006450u +#define CYDEV_UWRK_UWRK8_B0_UDB01_F1 0x40006451u +#define CYDEV_UWRK_UWRK8_B0_UDB02_F1 0x40006452u +#define CYDEV_UWRK_UWRK8_B0_UDB03_F1 0x40006453u +#define CYDEV_UWRK_UWRK8_B0_UDB04_F1 0x40006454u +#define CYDEV_UWRK_UWRK8_B0_UDB05_F1 0x40006455u +#define CYDEV_UWRK_UWRK8_B0_UDB06_F1 0x40006456u +#define CYDEV_UWRK_UWRK8_B0_UDB07_F1 0x40006457u +#define CYDEV_UWRK_UWRK8_B0_UDB08_F1 0x40006458u +#define CYDEV_UWRK_UWRK8_B0_UDB09_F1 0x40006459u +#define CYDEV_UWRK_UWRK8_B0_UDB10_F1 0x4000645au +#define CYDEV_UWRK_UWRK8_B0_UDB11_F1 0x4000645bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_F1 0x4000645cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_F1 0x4000645du +#define CYDEV_UWRK_UWRK8_B0_UDB14_F1 0x4000645eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_F1 0x4000645fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_ST 0x40006460u +#define CYDEV_UWRK_UWRK8_B0_UDB01_ST 0x40006461u +#define CYDEV_UWRK_UWRK8_B0_UDB02_ST 0x40006462u +#define CYDEV_UWRK_UWRK8_B0_UDB03_ST 0x40006463u +#define CYDEV_UWRK_UWRK8_B0_UDB04_ST 0x40006464u +#define CYDEV_UWRK_UWRK8_B0_UDB05_ST 0x40006465u +#define CYDEV_UWRK_UWRK8_B0_UDB06_ST 0x40006466u +#define CYDEV_UWRK_UWRK8_B0_UDB07_ST 0x40006467u +#define CYDEV_UWRK_UWRK8_B0_UDB08_ST 0x40006468u +#define CYDEV_UWRK_UWRK8_B0_UDB09_ST 0x40006469u +#define CYDEV_UWRK_UWRK8_B0_UDB10_ST 0x4000646au +#define CYDEV_UWRK_UWRK8_B0_UDB11_ST 0x4000646bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_ST 0x4000646cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_ST 0x4000646du +#define CYDEV_UWRK_UWRK8_B0_UDB14_ST 0x4000646eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_ST 0x4000646fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_CTL 0x40006470u +#define CYDEV_UWRK_UWRK8_B0_UDB01_CTL 0x40006471u +#define CYDEV_UWRK_UWRK8_B0_UDB02_CTL 0x40006472u +#define CYDEV_UWRK_UWRK8_B0_UDB03_CTL 0x40006473u +#define CYDEV_UWRK_UWRK8_B0_UDB04_CTL 0x40006474u +#define CYDEV_UWRK_UWRK8_B0_UDB05_CTL 0x40006475u +#define CYDEV_UWRK_UWRK8_B0_UDB06_CTL 0x40006476u +#define CYDEV_UWRK_UWRK8_B0_UDB07_CTL 0x40006477u +#define CYDEV_UWRK_UWRK8_B0_UDB08_CTL 0x40006478u +#define CYDEV_UWRK_UWRK8_B0_UDB09_CTL 0x40006479u +#define CYDEV_UWRK_UWRK8_B0_UDB10_CTL 0x4000647au +#define CYDEV_UWRK_UWRK8_B0_UDB11_CTL 0x4000647bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_CTL 0x4000647cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_CTL 0x4000647du +#define CYDEV_UWRK_UWRK8_B0_UDB14_CTL 0x4000647eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_CTL 0x4000647fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_MSK 0x40006480u +#define CYDEV_UWRK_UWRK8_B0_UDB01_MSK 0x40006481u +#define CYDEV_UWRK_UWRK8_B0_UDB02_MSK 0x40006482u +#define CYDEV_UWRK_UWRK8_B0_UDB03_MSK 0x40006483u +#define CYDEV_UWRK_UWRK8_B0_UDB04_MSK 0x40006484u +#define CYDEV_UWRK_UWRK8_B0_UDB05_MSK 0x40006485u +#define CYDEV_UWRK_UWRK8_B0_UDB06_MSK 0x40006486u +#define CYDEV_UWRK_UWRK8_B0_UDB07_MSK 0x40006487u +#define CYDEV_UWRK_UWRK8_B0_UDB08_MSK 0x40006488u +#define CYDEV_UWRK_UWRK8_B0_UDB09_MSK 0x40006489u +#define CYDEV_UWRK_UWRK8_B0_UDB10_MSK 0x4000648au +#define CYDEV_UWRK_UWRK8_B0_UDB11_MSK 0x4000648bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_MSK 0x4000648cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_MSK 0x4000648du +#define CYDEV_UWRK_UWRK8_B0_UDB14_MSK 0x4000648eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_MSK 0x4000648fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_ACTL 0x40006490u +#define CYDEV_UWRK_UWRK8_B0_UDB01_ACTL 0x40006491u +#define CYDEV_UWRK_UWRK8_B0_UDB02_ACTL 0x40006492u +#define CYDEV_UWRK_UWRK8_B0_UDB03_ACTL 0x40006493u +#define CYDEV_UWRK_UWRK8_B0_UDB04_ACTL 0x40006494u +#define CYDEV_UWRK_UWRK8_B0_UDB05_ACTL 0x40006495u +#define CYDEV_UWRK_UWRK8_B0_UDB06_ACTL 0x40006496u +#define CYDEV_UWRK_UWRK8_B0_UDB07_ACTL 0x40006497u +#define CYDEV_UWRK_UWRK8_B0_UDB08_ACTL 0x40006498u +#define CYDEV_UWRK_UWRK8_B0_UDB09_ACTL 0x40006499u +#define CYDEV_UWRK_UWRK8_B0_UDB10_ACTL 0x4000649au +#define CYDEV_UWRK_UWRK8_B0_UDB11_ACTL 0x4000649bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_ACTL 0x4000649cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_ACTL 0x4000649du +#define CYDEV_UWRK_UWRK8_B0_UDB14_ACTL 0x4000649eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_ACTL 0x4000649fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_MC 0x400064a0u +#define CYDEV_UWRK_UWRK8_B0_UDB01_MC 0x400064a1u +#define CYDEV_UWRK_UWRK8_B0_UDB02_MC 0x400064a2u +#define CYDEV_UWRK_UWRK8_B0_UDB03_MC 0x400064a3u +#define CYDEV_UWRK_UWRK8_B0_UDB04_MC 0x400064a4u +#define CYDEV_UWRK_UWRK8_B0_UDB05_MC 0x400064a5u +#define CYDEV_UWRK_UWRK8_B0_UDB06_MC 0x400064a6u +#define CYDEV_UWRK_UWRK8_B0_UDB07_MC 0x400064a7u +#define CYDEV_UWRK_UWRK8_B0_UDB08_MC 0x400064a8u +#define CYDEV_UWRK_UWRK8_B0_UDB09_MC 0x400064a9u +#define CYDEV_UWRK_UWRK8_B0_UDB10_MC 0x400064aau +#define CYDEV_UWRK_UWRK8_B0_UDB11_MC 0x400064abu +#define CYDEV_UWRK_UWRK8_B0_UDB12_MC 0x400064acu +#define CYDEV_UWRK_UWRK8_B0_UDB13_MC 0x400064adu +#define CYDEV_UWRK_UWRK8_B0_UDB14_MC 0x400064aeu +#define CYDEV_UWRK_UWRK8_B0_UDB15_MC 0x400064afu +#define CYDEV_UWRK_UWRK8_B1_BASE 0x40006500u +#define CYDEV_UWRK_UWRK8_B1_SIZE 0x000000b0u +#define CYDEV_UWRK_UWRK8_B1_UDB04_A0 0x40006504u +#define CYDEV_UWRK_UWRK8_B1_UDB05_A0 0x40006505u +#define CYDEV_UWRK_UWRK8_B1_UDB06_A0 0x40006506u +#define CYDEV_UWRK_UWRK8_B1_UDB07_A0 0x40006507u +#define CYDEV_UWRK_UWRK8_B1_UDB08_A0 0x40006508u +#define CYDEV_UWRK_UWRK8_B1_UDB09_A0 0x40006509u +#define CYDEV_UWRK_UWRK8_B1_UDB10_A0 0x4000650au +#define CYDEV_UWRK_UWRK8_B1_UDB11_A0 0x4000650bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_A1 0x40006514u +#define CYDEV_UWRK_UWRK8_B1_UDB05_A1 0x40006515u +#define CYDEV_UWRK_UWRK8_B1_UDB06_A1 0x40006516u +#define CYDEV_UWRK_UWRK8_B1_UDB07_A1 0x40006517u +#define CYDEV_UWRK_UWRK8_B1_UDB08_A1 0x40006518u +#define CYDEV_UWRK_UWRK8_B1_UDB09_A1 0x40006519u +#define CYDEV_UWRK_UWRK8_B1_UDB10_A1 0x4000651au +#define CYDEV_UWRK_UWRK8_B1_UDB11_A1 0x4000651bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_D0 0x40006524u +#define CYDEV_UWRK_UWRK8_B1_UDB05_D0 0x40006525u +#define CYDEV_UWRK_UWRK8_B1_UDB06_D0 0x40006526u +#define CYDEV_UWRK_UWRK8_B1_UDB07_D0 0x40006527u +#define CYDEV_UWRK_UWRK8_B1_UDB08_D0 0x40006528u +#define CYDEV_UWRK_UWRK8_B1_UDB09_D0 0x40006529u +#define CYDEV_UWRK_UWRK8_B1_UDB10_D0 0x4000652au +#define CYDEV_UWRK_UWRK8_B1_UDB11_D0 0x4000652bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_D1 0x40006534u +#define CYDEV_UWRK_UWRK8_B1_UDB05_D1 0x40006535u +#define CYDEV_UWRK_UWRK8_B1_UDB06_D1 0x40006536u +#define CYDEV_UWRK_UWRK8_B1_UDB07_D1 0x40006537u +#define CYDEV_UWRK_UWRK8_B1_UDB08_D1 0x40006538u +#define CYDEV_UWRK_UWRK8_B1_UDB09_D1 0x40006539u +#define CYDEV_UWRK_UWRK8_B1_UDB10_D1 0x4000653au +#define CYDEV_UWRK_UWRK8_B1_UDB11_D1 0x4000653bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_F0 0x40006544u +#define CYDEV_UWRK_UWRK8_B1_UDB05_F0 0x40006545u +#define CYDEV_UWRK_UWRK8_B1_UDB06_F0 0x40006546u +#define CYDEV_UWRK_UWRK8_B1_UDB07_F0 0x40006547u +#define CYDEV_UWRK_UWRK8_B1_UDB08_F0 0x40006548u +#define CYDEV_UWRK_UWRK8_B1_UDB09_F0 0x40006549u +#define CYDEV_UWRK_UWRK8_B1_UDB10_F0 0x4000654au +#define CYDEV_UWRK_UWRK8_B1_UDB11_F0 0x4000654bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_F1 0x40006554u +#define CYDEV_UWRK_UWRK8_B1_UDB05_F1 0x40006555u +#define CYDEV_UWRK_UWRK8_B1_UDB06_F1 0x40006556u +#define CYDEV_UWRK_UWRK8_B1_UDB07_F1 0x40006557u +#define CYDEV_UWRK_UWRK8_B1_UDB08_F1 0x40006558u +#define CYDEV_UWRK_UWRK8_B1_UDB09_F1 0x40006559u +#define CYDEV_UWRK_UWRK8_B1_UDB10_F1 0x4000655au +#define CYDEV_UWRK_UWRK8_B1_UDB11_F1 0x4000655bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_ST 0x40006564u +#define CYDEV_UWRK_UWRK8_B1_UDB05_ST 0x40006565u +#define CYDEV_UWRK_UWRK8_B1_UDB06_ST 0x40006566u +#define CYDEV_UWRK_UWRK8_B1_UDB07_ST 0x40006567u +#define CYDEV_UWRK_UWRK8_B1_UDB08_ST 0x40006568u +#define CYDEV_UWRK_UWRK8_B1_UDB09_ST 0x40006569u +#define CYDEV_UWRK_UWRK8_B1_UDB10_ST 0x4000656au +#define CYDEV_UWRK_UWRK8_B1_UDB11_ST 0x4000656bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_CTL 0x40006574u +#define CYDEV_UWRK_UWRK8_B1_UDB05_CTL 0x40006575u +#define CYDEV_UWRK_UWRK8_B1_UDB06_CTL 0x40006576u +#define CYDEV_UWRK_UWRK8_B1_UDB07_CTL 0x40006577u +#define CYDEV_UWRK_UWRK8_B1_UDB08_CTL 0x40006578u +#define CYDEV_UWRK_UWRK8_B1_UDB09_CTL 0x40006579u +#define CYDEV_UWRK_UWRK8_B1_UDB10_CTL 0x4000657au +#define CYDEV_UWRK_UWRK8_B1_UDB11_CTL 0x4000657bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_MSK 0x40006584u +#define CYDEV_UWRK_UWRK8_B1_UDB05_MSK 0x40006585u +#define CYDEV_UWRK_UWRK8_B1_UDB06_MSK 0x40006586u +#define CYDEV_UWRK_UWRK8_B1_UDB07_MSK 0x40006587u +#define CYDEV_UWRK_UWRK8_B1_UDB08_MSK 0x40006588u +#define CYDEV_UWRK_UWRK8_B1_UDB09_MSK 0x40006589u +#define CYDEV_UWRK_UWRK8_B1_UDB10_MSK 0x4000658au +#define CYDEV_UWRK_UWRK8_B1_UDB11_MSK 0x4000658bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_ACTL 0x40006594u +#define CYDEV_UWRK_UWRK8_B1_UDB05_ACTL 0x40006595u +#define CYDEV_UWRK_UWRK8_B1_UDB06_ACTL 0x40006596u +#define CYDEV_UWRK_UWRK8_B1_UDB07_ACTL 0x40006597u +#define CYDEV_UWRK_UWRK8_B1_UDB08_ACTL 0x40006598u +#define CYDEV_UWRK_UWRK8_B1_UDB09_ACTL 0x40006599u +#define CYDEV_UWRK_UWRK8_B1_UDB10_ACTL 0x4000659au +#define CYDEV_UWRK_UWRK8_B1_UDB11_ACTL 0x4000659bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_MC 0x400065a4u +#define CYDEV_UWRK_UWRK8_B1_UDB05_MC 0x400065a5u +#define CYDEV_UWRK_UWRK8_B1_UDB06_MC 0x400065a6u +#define CYDEV_UWRK_UWRK8_B1_UDB07_MC 0x400065a7u +#define CYDEV_UWRK_UWRK8_B1_UDB08_MC 0x400065a8u +#define CYDEV_UWRK_UWRK8_B1_UDB09_MC 0x400065a9u +#define CYDEV_UWRK_UWRK8_B1_UDB10_MC 0x400065aau +#define CYDEV_UWRK_UWRK8_B1_UDB11_MC 0x400065abu +#define CYDEV_UWRK_UWRK16_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_SIZE 0x00000760u +#define CYDEV_UWRK_UWRK16_CAT_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_CAT_SIZE 0x00000760u +#define CYDEV_UWRK_UWRK16_CAT_B0_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_CAT_B0_SIZE 0x00000160u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1 0x40006800u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1 0x40006802u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1 0x40006804u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1 0x40006806u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1 0x40006808u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1 0x4000680au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1 0x4000680cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1 0x4000680eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1 0x40006810u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1 0x40006812u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1 0x40006814u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1 0x40006816u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1 0x40006818u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1 0x4000681au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1 0x4000681cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1 0x4000681eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1 0x40006840u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1 0x40006842u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1 0x40006844u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1 0x40006846u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1 0x40006848u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1 0x4000684au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1 0x4000684cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1 0x4000684eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1 0x40006850u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1 0x40006852u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1 0x40006854u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1 0x40006856u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1 0x40006858u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1 0x4000685au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1 0x4000685cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1 0x4000685eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1 0x40006880u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1 0x40006882u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1 0x40006884u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1 0x40006886u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1 0x40006888u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1 0x4000688au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1 0x4000688cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1 0x4000688eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1 0x40006890u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1 0x40006892u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1 0x40006894u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1 0x40006896u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1 0x40006898u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1 0x4000689au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1 0x4000689cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1 0x4000689eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL 0x400068c0u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL 0x400068c2u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL 0x400068c4u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL 0x400068c6u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL 0x400068c8u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL 0x400068cau +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL 0x400068ccu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL 0x400068ceu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL 0x400068d0u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL 0x400068d2u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL 0x400068d4u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL 0x400068d6u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL 0x400068d8u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL 0x400068dau +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL 0x400068dcu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL 0x400068deu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL 0x40006900u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL 0x40006902u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL 0x40006904u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL 0x40006906u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL 0x40006908u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL 0x4000690au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL 0x4000690cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL 0x4000690eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL 0x40006910u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL 0x40006912u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL 0x40006914u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL 0x40006916u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL 0x40006918u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL 0x4000691au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL 0x4000691cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL 0x4000691eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00 0x40006940u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00 0x40006942u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00 0x40006944u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00 0x40006946u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00 0x40006948u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00 0x4000694au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00 0x4000694cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00 0x4000694eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00 0x40006950u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00 0x40006952u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00 0x40006954u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00 0x40006956u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00 0x40006958u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00 0x4000695au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00 0x4000695cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00 0x4000695eu +#define CYDEV_UWRK_UWRK16_CAT_B1_BASE 0x40006a00u +#define CYDEV_UWRK_UWRK16_CAT_B1_SIZE 0x00000160u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1 0x40006a08u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1 0x40006a0au +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1 0x40006a0cu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1 0x40006a0eu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1 0x40006a10u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1 0x40006a12u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1 0x40006a14u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1 0x40006a16u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1 0x40006a48u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1 0x40006a4au +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1 0x40006a4cu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1 0x40006a4eu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1 0x40006a50u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1 0x40006a52u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1 0x40006a54u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1 0x40006a56u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1 0x40006a88u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1 0x40006a8au +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1 0x40006a8cu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1 0x40006a8eu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1 0x40006a90u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1 0x40006a92u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1 0x40006a94u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1 0x40006a96u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL 0x40006ac8u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL 0x40006acau +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL 0x40006accu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL 0x40006aceu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL 0x40006ad0u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL 0x40006ad2u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL 0x40006ad4u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL 0x40006ad6u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL 0x40006b08u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL 0x40006b0au +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL 0x40006b0cu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL 0x40006b0eu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL 0x40006b10u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL 0x40006b12u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL 0x40006b14u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL 0x40006b16u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00 0x40006b48u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00 0x40006b4au +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00 0x40006b4cu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00 0x40006b4eu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00 0x40006b50u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00 0x40006b52u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00 0x40006b54u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00 0x40006b56u +#define CYDEV_UWRK_UWRK16_DEF_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_DEF_SIZE 0x0000075eu +#define CYDEV_UWRK_UWRK16_DEF_B0_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_DEF_B0_SIZE 0x0000015eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0 0x40006800u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0 0x40006802u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0 0x40006804u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0 0x40006806u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0 0x40006808u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0 0x4000680au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0 0x4000680cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0 0x4000680eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0 0x40006810u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0 0x40006812u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0 0x40006814u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0 0x40006816u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0 0x40006818u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0 0x4000681au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0 0x4000681cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1 0x40006820u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1 0x40006822u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1 0x40006824u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1 0x40006826u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1 0x40006828u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1 0x4000682au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1 0x4000682cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1 0x4000682eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1 0x40006830u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1 0x40006832u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1 0x40006834u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1 0x40006836u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1 0x40006838u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1 0x4000683au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1 0x4000683cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0 0x40006840u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0 0x40006842u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0 0x40006844u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0 0x40006846u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0 0x40006848u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0 0x4000684au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0 0x4000684cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0 0x4000684eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0 0x40006850u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0 0x40006852u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0 0x40006854u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0 0x40006856u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0 0x40006858u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0 0x4000685au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0 0x4000685cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1 0x40006860u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1 0x40006862u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1 0x40006864u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1 0x40006866u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1 0x40006868u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1 0x4000686au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1 0x4000686cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1 0x4000686eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1 0x40006870u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1 0x40006872u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1 0x40006874u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1 0x40006876u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1 0x40006878u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1 0x4000687au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1 0x4000687cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0 0x40006880u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0 0x40006882u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0 0x40006884u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0 0x40006886u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0 0x40006888u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0 0x4000688au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0 0x4000688cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0 0x4000688eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0 0x40006890u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0 0x40006892u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0 0x40006894u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0 0x40006896u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0 0x40006898u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0 0x4000689au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0 0x4000689cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1 0x400068a0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1 0x400068a2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1 0x400068a4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1 0x400068a6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1 0x400068a8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1 0x400068aau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1 0x400068acu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1 0x400068aeu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1 0x400068b0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1 0x400068b2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1 0x400068b4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1 0x400068b6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1 0x400068b8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1 0x400068bau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1 0x400068bcu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST 0x400068c0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST 0x400068c2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST 0x400068c4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST 0x400068c6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST 0x400068c8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST 0x400068cau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST 0x400068ccu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST 0x400068ceu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST 0x400068d0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST 0x400068d2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST 0x400068d4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST 0x400068d6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST 0x400068d8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST 0x400068dau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST 0x400068dcu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL 0x400068e0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL 0x400068e2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL 0x400068e4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL 0x400068e6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL 0x400068e8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL 0x400068eau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL 0x400068ecu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL 0x400068eeu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL 0x400068f0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL 0x400068f2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL 0x400068f4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL 0x400068f6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL 0x400068f8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL 0x400068fau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL 0x400068fcu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK 0x40006900u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK 0x40006902u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK 0x40006904u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK 0x40006906u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK 0x40006908u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK 0x4000690au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK 0x4000690cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK 0x4000690eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK 0x40006910u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK 0x40006912u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK 0x40006914u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK 0x40006916u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK 0x40006918u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK 0x4000691au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK 0x4000691cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL 0x40006920u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL 0x40006922u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL 0x40006924u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL 0x40006926u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL 0x40006928u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL 0x4000692au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL 0x4000692cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL 0x4000692eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL 0x40006930u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL 0x40006932u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL 0x40006934u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL 0x40006936u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL 0x40006938u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL 0x4000693au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL 0x4000693cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC 0x40006940u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC 0x40006942u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC 0x40006944u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC 0x40006946u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC 0x40006948u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC 0x4000694au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC 0x4000694cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC 0x4000694eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC 0x40006950u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC 0x40006952u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC 0x40006954u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC 0x40006956u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC 0x40006958u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC 0x4000695au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC 0x4000695cu +#define CYDEV_UWRK_UWRK16_DEF_B1_BASE 0x40006a00u +#define CYDEV_UWRK_UWRK16_DEF_B1_SIZE 0x0000015eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0 0x40006a08u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0 0x40006a0au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0 0x40006a0cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0 0x40006a0eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0 0x40006a10u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0 0x40006a12u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0 0x40006a14u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0 0x40006a16u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1 0x40006a28u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1 0x40006a2au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1 0x40006a2cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1 0x40006a2eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1 0x40006a30u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1 0x40006a32u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1 0x40006a34u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1 0x40006a36u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0 0x40006a48u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0 0x40006a4au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0 0x40006a4cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0 0x40006a4eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0 0x40006a50u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0 0x40006a52u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0 0x40006a54u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0 0x40006a56u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1 0x40006a68u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1 0x40006a6au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1 0x40006a6cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1 0x40006a6eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1 0x40006a70u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1 0x40006a72u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1 0x40006a74u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1 0x40006a76u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0 0x40006a88u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0 0x40006a8au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0 0x40006a8cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0 0x40006a8eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0 0x40006a90u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0 0x40006a92u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0 0x40006a94u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0 0x40006a96u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1 0x40006aa8u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1 0x40006aaau +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1 0x40006aacu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1 0x40006aaeu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1 0x40006ab0u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1 0x40006ab2u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1 0x40006ab4u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1 0x40006ab6u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST 0x40006ac8u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST 0x40006acau +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST 0x40006accu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST 0x40006aceu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST 0x40006ad0u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST 0x40006ad2u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST 0x40006ad4u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST 0x40006ad6u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL 0x40006ae8u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL 0x40006aeau +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL 0x40006aecu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL 0x40006aeeu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL 0x40006af0u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL 0x40006af2u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL 0x40006af4u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL 0x40006af6u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK 0x40006b08u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK 0x40006b0au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK 0x40006b0cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK 0x40006b0eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK 0x40006b10u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK 0x40006b12u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK 0x40006b14u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK 0x40006b16u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL 0x40006b28u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL 0x40006b2au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL 0x40006b2cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL 0x40006b2eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL 0x40006b30u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL 0x40006b32u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL 0x40006b34u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL 0x40006b36u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC 0x40006b48u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC 0x40006b4au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC 0x40006b4cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC 0x40006b4eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC 0x40006b50u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC 0x40006b52u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC 0x40006b54u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC 0x40006b56u +#define CYDEV_PHUB_BASE 0x40007000u +#define CYDEV_PHUB_SIZE 0x00000c00u +#define CYDEV_PHUB_CFG 0x40007000u +#define CYDEV_PHUB_ERR 0x40007004u +#define CYDEV_PHUB_ERR_ADR 0x40007008u +#define CYDEV_PHUB_CH0_BASE 0x40007010u +#define CYDEV_PHUB_CH0_SIZE 0x0000000cu +#define CYDEV_PHUB_CH0_BASIC_CFG 0x40007010u +#define CYDEV_PHUB_CH0_ACTION 0x40007014u +#define CYDEV_PHUB_CH0_BASIC_STATUS 0x40007018u +#define CYDEV_PHUB_CH1_BASE 0x40007020u +#define CYDEV_PHUB_CH1_SIZE 0x0000000cu +#define CYDEV_PHUB_CH1_BASIC_CFG 0x40007020u +#define CYDEV_PHUB_CH1_ACTION 0x40007024u +#define CYDEV_PHUB_CH1_BASIC_STATUS 0x40007028u +#define CYDEV_PHUB_CH2_BASE 0x40007030u +#define CYDEV_PHUB_CH2_SIZE 0x0000000cu +#define CYDEV_PHUB_CH2_BASIC_CFG 0x40007030u +#define CYDEV_PHUB_CH2_ACTION 0x40007034u +#define CYDEV_PHUB_CH2_BASIC_STATUS 0x40007038u +#define CYDEV_PHUB_CH3_BASE 0x40007040u +#define CYDEV_PHUB_CH3_SIZE 0x0000000cu +#define CYDEV_PHUB_CH3_BASIC_CFG 0x40007040u +#define CYDEV_PHUB_CH3_ACTION 0x40007044u +#define CYDEV_PHUB_CH3_BASIC_STATUS 0x40007048u +#define CYDEV_PHUB_CH4_BASE 0x40007050u +#define CYDEV_PHUB_CH4_SIZE 0x0000000cu +#define CYDEV_PHUB_CH4_BASIC_CFG 0x40007050u +#define CYDEV_PHUB_CH4_ACTION 0x40007054u +#define CYDEV_PHUB_CH4_BASIC_STATUS 0x40007058u +#define CYDEV_PHUB_CH5_BASE 0x40007060u +#define CYDEV_PHUB_CH5_SIZE 0x0000000cu +#define CYDEV_PHUB_CH5_BASIC_CFG 0x40007060u +#define CYDEV_PHUB_CH5_ACTION 0x40007064u +#define CYDEV_PHUB_CH5_BASIC_STATUS 0x40007068u +#define CYDEV_PHUB_CH6_BASE 0x40007070u +#define CYDEV_PHUB_CH6_SIZE 0x0000000cu +#define CYDEV_PHUB_CH6_BASIC_CFG 0x40007070u +#define CYDEV_PHUB_CH6_ACTION 0x40007074u +#define CYDEV_PHUB_CH6_BASIC_STATUS 0x40007078u +#define CYDEV_PHUB_CH7_BASE 0x40007080u +#define CYDEV_PHUB_CH7_SIZE 0x0000000cu +#define CYDEV_PHUB_CH7_BASIC_CFG 0x40007080u +#define CYDEV_PHUB_CH7_ACTION 0x40007084u +#define CYDEV_PHUB_CH7_BASIC_STATUS 0x40007088u +#define CYDEV_PHUB_CH8_BASE 0x40007090u +#define CYDEV_PHUB_CH8_SIZE 0x0000000cu +#define CYDEV_PHUB_CH8_BASIC_CFG 0x40007090u +#define CYDEV_PHUB_CH8_ACTION 0x40007094u +#define CYDEV_PHUB_CH8_BASIC_STATUS 0x40007098u +#define CYDEV_PHUB_CH9_BASE 0x400070a0u +#define CYDEV_PHUB_CH9_SIZE 0x0000000cu +#define CYDEV_PHUB_CH9_BASIC_CFG 0x400070a0u +#define CYDEV_PHUB_CH9_ACTION 0x400070a4u +#define CYDEV_PHUB_CH9_BASIC_STATUS 0x400070a8u +#define CYDEV_PHUB_CH10_BASE 0x400070b0u +#define CYDEV_PHUB_CH10_SIZE 0x0000000cu +#define CYDEV_PHUB_CH10_BASIC_CFG 0x400070b0u +#define CYDEV_PHUB_CH10_ACTION 0x400070b4u +#define CYDEV_PHUB_CH10_BASIC_STATUS 0x400070b8u +#define CYDEV_PHUB_CH11_BASE 0x400070c0u +#define CYDEV_PHUB_CH11_SIZE 0x0000000cu +#define CYDEV_PHUB_CH11_BASIC_CFG 0x400070c0u +#define CYDEV_PHUB_CH11_ACTION 0x400070c4u +#define CYDEV_PHUB_CH11_BASIC_STATUS 0x400070c8u +#define CYDEV_PHUB_CH12_BASE 0x400070d0u +#define CYDEV_PHUB_CH12_SIZE 0x0000000cu +#define CYDEV_PHUB_CH12_BASIC_CFG 0x400070d0u +#define CYDEV_PHUB_CH12_ACTION 0x400070d4u +#define CYDEV_PHUB_CH12_BASIC_STATUS 0x400070d8u +#define CYDEV_PHUB_CH13_BASE 0x400070e0u +#define CYDEV_PHUB_CH13_SIZE 0x0000000cu +#define CYDEV_PHUB_CH13_BASIC_CFG 0x400070e0u +#define CYDEV_PHUB_CH13_ACTION 0x400070e4u +#define CYDEV_PHUB_CH13_BASIC_STATUS 0x400070e8u +#define CYDEV_PHUB_CH14_BASE 0x400070f0u +#define CYDEV_PHUB_CH14_SIZE 0x0000000cu +#define CYDEV_PHUB_CH14_BASIC_CFG 0x400070f0u +#define CYDEV_PHUB_CH14_ACTION 0x400070f4u +#define CYDEV_PHUB_CH14_BASIC_STATUS 0x400070f8u +#define CYDEV_PHUB_CH15_BASE 0x40007100u +#define CYDEV_PHUB_CH15_SIZE 0x0000000cu +#define CYDEV_PHUB_CH15_BASIC_CFG 0x40007100u +#define CYDEV_PHUB_CH15_ACTION 0x40007104u +#define CYDEV_PHUB_CH15_BASIC_STATUS 0x40007108u +#define CYDEV_PHUB_CH16_BASE 0x40007110u +#define CYDEV_PHUB_CH16_SIZE 0x0000000cu +#define CYDEV_PHUB_CH16_BASIC_CFG 0x40007110u +#define CYDEV_PHUB_CH16_ACTION 0x40007114u +#define CYDEV_PHUB_CH16_BASIC_STATUS 0x40007118u +#define CYDEV_PHUB_CH17_BASE 0x40007120u +#define CYDEV_PHUB_CH17_SIZE 0x0000000cu +#define CYDEV_PHUB_CH17_BASIC_CFG 0x40007120u +#define CYDEV_PHUB_CH17_ACTION 0x40007124u +#define CYDEV_PHUB_CH17_BASIC_STATUS 0x40007128u +#define CYDEV_PHUB_CH18_BASE 0x40007130u +#define CYDEV_PHUB_CH18_SIZE 0x0000000cu +#define CYDEV_PHUB_CH18_BASIC_CFG 0x40007130u +#define CYDEV_PHUB_CH18_ACTION 0x40007134u +#define CYDEV_PHUB_CH18_BASIC_STATUS 0x40007138u +#define CYDEV_PHUB_CH19_BASE 0x40007140u +#define CYDEV_PHUB_CH19_SIZE 0x0000000cu +#define CYDEV_PHUB_CH19_BASIC_CFG 0x40007140u +#define CYDEV_PHUB_CH19_ACTION 0x40007144u +#define CYDEV_PHUB_CH19_BASIC_STATUS 0x40007148u +#define CYDEV_PHUB_CH20_BASE 0x40007150u +#define CYDEV_PHUB_CH20_SIZE 0x0000000cu +#define CYDEV_PHUB_CH20_BASIC_CFG 0x40007150u +#define CYDEV_PHUB_CH20_ACTION 0x40007154u +#define CYDEV_PHUB_CH20_BASIC_STATUS 0x40007158u +#define CYDEV_PHUB_CH21_BASE 0x40007160u +#define CYDEV_PHUB_CH21_SIZE 0x0000000cu +#define CYDEV_PHUB_CH21_BASIC_CFG 0x40007160u +#define CYDEV_PHUB_CH21_ACTION 0x40007164u +#define CYDEV_PHUB_CH21_BASIC_STATUS 0x40007168u +#define CYDEV_PHUB_CH22_BASE 0x40007170u +#define CYDEV_PHUB_CH22_SIZE 0x0000000cu +#define CYDEV_PHUB_CH22_BASIC_CFG 0x40007170u +#define CYDEV_PHUB_CH22_ACTION 0x40007174u +#define CYDEV_PHUB_CH22_BASIC_STATUS 0x40007178u +#define CYDEV_PHUB_CH23_BASE 0x40007180u +#define CYDEV_PHUB_CH23_SIZE 0x0000000cu +#define CYDEV_PHUB_CH23_BASIC_CFG 0x40007180u +#define CYDEV_PHUB_CH23_ACTION 0x40007184u +#define CYDEV_PHUB_CH23_BASIC_STATUS 0x40007188u +#define CYDEV_PHUB_CFGMEM0_BASE 0x40007600u +#define CYDEV_PHUB_CFGMEM0_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM0_CFG0 0x40007600u +#define CYDEV_PHUB_CFGMEM0_CFG1 0x40007604u +#define CYDEV_PHUB_CFGMEM1_BASE 0x40007608u +#define CYDEV_PHUB_CFGMEM1_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM1_CFG0 0x40007608u +#define CYDEV_PHUB_CFGMEM1_CFG1 0x4000760cu +#define CYDEV_PHUB_CFGMEM2_BASE 0x40007610u +#define CYDEV_PHUB_CFGMEM2_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM2_CFG0 0x40007610u +#define CYDEV_PHUB_CFGMEM2_CFG1 0x40007614u +#define CYDEV_PHUB_CFGMEM3_BASE 0x40007618u +#define CYDEV_PHUB_CFGMEM3_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM3_CFG0 0x40007618u +#define CYDEV_PHUB_CFGMEM3_CFG1 0x4000761cu +#define CYDEV_PHUB_CFGMEM4_BASE 0x40007620u +#define CYDEV_PHUB_CFGMEM4_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM4_CFG0 0x40007620u +#define CYDEV_PHUB_CFGMEM4_CFG1 0x40007624u +#define CYDEV_PHUB_CFGMEM5_BASE 0x40007628u +#define CYDEV_PHUB_CFGMEM5_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM5_CFG0 0x40007628u +#define CYDEV_PHUB_CFGMEM5_CFG1 0x4000762cu +#define CYDEV_PHUB_CFGMEM6_BASE 0x40007630u +#define CYDEV_PHUB_CFGMEM6_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM6_CFG0 0x40007630u +#define CYDEV_PHUB_CFGMEM6_CFG1 0x40007634u +#define CYDEV_PHUB_CFGMEM7_BASE 0x40007638u +#define CYDEV_PHUB_CFGMEM7_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM7_CFG0 0x40007638u +#define CYDEV_PHUB_CFGMEM7_CFG1 0x4000763cu +#define CYDEV_PHUB_CFGMEM8_BASE 0x40007640u +#define CYDEV_PHUB_CFGMEM8_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM8_CFG0 0x40007640u +#define CYDEV_PHUB_CFGMEM8_CFG1 0x40007644u +#define CYDEV_PHUB_CFGMEM9_BASE 0x40007648u +#define CYDEV_PHUB_CFGMEM9_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM9_CFG0 0x40007648u +#define CYDEV_PHUB_CFGMEM9_CFG1 0x4000764cu +#define CYDEV_PHUB_CFGMEM10_BASE 0x40007650u +#define CYDEV_PHUB_CFGMEM10_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM10_CFG0 0x40007650u +#define CYDEV_PHUB_CFGMEM10_CFG1 0x40007654u +#define CYDEV_PHUB_CFGMEM11_BASE 0x40007658u +#define CYDEV_PHUB_CFGMEM11_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM11_CFG0 0x40007658u +#define CYDEV_PHUB_CFGMEM11_CFG1 0x4000765cu +#define CYDEV_PHUB_CFGMEM12_BASE 0x40007660u +#define CYDEV_PHUB_CFGMEM12_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM12_CFG0 0x40007660u +#define CYDEV_PHUB_CFGMEM12_CFG1 0x40007664u +#define CYDEV_PHUB_CFGMEM13_BASE 0x40007668u +#define CYDEV_PHUB_CFGMEM13_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM13_CFG0 0x40007668u +#define CYDEV_PHUB_CFGMEM13_CFG1 0x4000766cu +#define CYDEV_PHUB_CFGMEM14_BASE 0x40007670u +#define CYDEV_PHUB_CFGMEM14_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM14_CFG0 0x40007670u +#define CYDEV_PHUB_CFGMEM14_CFG1 0x40007674u +#define CYDEV_PHUB_CFGMEM15_BASE 0x40007678u +#define CYDEV_PHUB_CFGMEM15_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM15_CFG0 0x40007678u +#define CYDEV_PHUB_CFGMEM15_CFG1 0x4000767cu +#define CYDEV_PHUB_CFGMEM16_BASE 0x40007680u +#define CYDEV_PHUB_CFGMEM16_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM16_CFG0 0x40007680u +#define CYDEV_PHUB_CFGMEM16_CFG1 0x40007684u +#define CYDEV_PHUB_CFGMEM17_BASE 0x40007688u +#define CYDEV_PHUB_CFGMEM17_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM17_CFG0 0x40007688u +#define CYDEV_PHUB_CFGMEM17_CFG1 0x4000768cu +#define CYDEV_PHUB_CFGMEM18_BASE 0x40007690u +#define CYDEV_PHUB_CFGMEM18_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM18_CFG0 0x40007690u +#define CYDEV_PHUB_CFGMEM18_CFG1 0x40007694u +#define CYDEV_PHUB_CFGMEM19_BASE 0x40007698u +#define CYDEV_PHUB_CFGMEM19_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM19_CFG0 0x40007698u +#define CYDEV_PHUB_CFGMEM19_CFG1 0x4000769cu +#define CYDEV_PHUB_CFGMEM20_BASE 0x400076a0u +#define CYDEV_PHUB_CFGMEM20_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM20_CFG0 0x400076a0u +#define CYDEV_PHUB_CFGMEM20_CFG1 0x400076a4u +#define CYDEV_PHUB_CFGMEM21_BASE 0x400076a8u +#define CYDEV_PHUB_CFGMEM21_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM21_CFG0 0x400076a8u +#define CYDEV_PHUB_CFGMEM21_CFG1 0x400076acu +#define CYDEV_PHUB_CFGMEM22_BASE 0x400076b0u +#define CYDEV_PHUB_CFGMEM22_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM22_CFG0 0x400076b0u +#define CYDEV_PHUB_CFGMEM22_CFG1 0x400076b4u +#define CYDEV_PHUB_CFGMEM23_BASE 0x400076b8u +#define CYDEV_PHUB_CFGMEM23_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM23_CFG0 0x400076b8u +#define CYDEV_PHUB_CFGMEM23_CFG1 0x400076bcu +#define CYDEV_PHUB_TDMEM0_BASE 0x40007800u +#define CYDEV_PHUB_TDMEM0_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM0_ORIG_TD0 0x40007800u +#define CYDEV_PHUB_TDMEM0_ORIG_TD1 0x40007804u +#define CYDEV_PHUB_TDMEM1_BASE 0x40007808u +#define CYDEV_PHUB_TDMEM1_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM1_ORIG_TD0 0x40007808u +#define CYDEV_PHUB_TDMEM1_ORIG_TD1 0x4000780cu +#define CYDEV_PHUB_TDMEM2_BASE 0x40007810u +#define CYDEV_PHUB_TDMEM2_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM2_ORIG_TD0 0x40007810u +#define CYDEV_PHUB_TDMEM2_ORIG_TD1 0x40007814u +#define CYDEV_PHUB_TDMEM3_BASE 0x40007818u +#define CYDEV_PHUB_TDMEM3_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM3_ORIG_TD0 0x40007818u +#define CYDEV_PHUB_TDMEM3_ORIG_TD1 0x4000781cu +#define CYDEV_PHUB_TDMEM4_BASE 0x40007820u +#define CYDEV_PHUB_TDMEM4_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM4_ORIG_TD0 0x40007820u +#define CYDEV_PHUB_TDMEM4_ORIG_TD1 0x40007824u +#define CYDEV_PHUB_TDMEM5_BASE 0x40007828u +#define CYDEV_PHUB_TDMEM5_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM5_ORIG_TD0 0x40007828u +#define CYDEV_PHUB_TDMEM5_ORIG_TD1 0x4000782cu +#define CYDEV_PHUB_TDMEM6_BASE 0x40007830u +#define CYDEV_PHUB_TDMEM6_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM6_ORIG_TD0 0x40007830u +#define CYDEV_PHUB_TDMEM6_ORIG_TD1 0x40007834u +#define CYDEV_PHUB_TDMEM7_BASE 0x40007838u +#define CYDEV_PHUB_TDMEM7_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM7_ORIG_TD0 0x40007838u +#define CYDEV_PHUB_TDMEM7_ORIG_TD1 0x4000783cu +#define CYDEV_PHUB_TDMEM8_BASE 0x40007840u +#define CYDEV_PHUB_TDMEM8_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM8_ORIG_TD0 0x40007840u +#define CYDEV_PHUB_TDMEM8_ORIG_TD1 0x40007844u +#define CYDEV_PHUB_TDMEM9_BASE 0x40007848u +#define CYDEV_PHUB_TDMEM9_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM9_ORIG_TD0 0x40007848u +#define CYDEV_PHUB_TDMEM9_ORIG_TD1 0x4000784cu +#define CYDEV_PHUB_TDMEM10_BASE 0x40007850u +#define CYDEV_PHUB_TDMEM10_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM10_ORIG_TD0 0x40007850u +#define CYDEV_PHUB_TDMEM10_ORIG_TD1 0x40007854u +#define CYDEV_PHUB_TDMEM11_BASE 0x40007858u +#define CYDEV_PHUB_TDMEM11_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM11_ORIG_TD0 0x40007858u +#define CYDEV_PHUB_TDMEM11_ORIG_TD1 0x4000785cu +#define CYDEV_PHUB_TDMEM12_BASE 0x40007860u +#define CYDEV_PHUB_TDMEM12_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM12_ORIG_TD0 0x40007860u +#define CYDEV_PHUB_TDMEM12_ORIG_TD1 0x40007864u +#define CYDEV_PHUB_TDMEM13_BASE 0x40007868u +#define CYDEV_PHUB_TDMEM13_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM13_ORIG_TD0 0x40007868u +#define CYDEV_PHUB_TDMEM13_ORIG_TD1 0x4000786cu +#define CYDEV_PHUB_TDMEM14_BASE 0x40007870u +#define CYDEV_PHUB_TDMEM14_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM14_ORIG_TD0 0x40007870u +#define CYDEV_PHUB_TDMEM14_ORIG_TD1 0x40007874u +#define CYDEV_PHUB_TDMEM15_BASE 0x40007878u +#define CYDEV_PHUB_TDMEM15_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM15_ORIG_TD0 0x40007878u +#define CYDEV_PHUB_TDMEM15_ORIG_TD1 0x4000787cu +#define CYDEV_PHUB_TDMEM16_BASE 0x40007880u +#define CYDEV_PHUB_TDMEM16_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM16_ORIG_TD0 0x40007880u +#define CYDEV_PHUB_TDMEM16_ORIG_TD1 0x40007884u +#define CYDEV_PHUB_TDMEM17_BASE 0x40007888u +#define CYDEV_PHUB_TDMEM17_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM17_ORIG_TD0 0x40007888u +#define CYDEV_PHUB_TDMEM17_ORIG_TD1 0x4000788cu +#define CYDEV_PHUB_TDMEM18_BASE 0x40007890u +#define CYDEV_PHUB_TDMEM18_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM18_ORIG_TD0 0x40007890u +#define CYDEV_PHUB_TDMEM18_ORIG_TD1 0x40007894u +#define CYDEV_PHUB_TDMEM19_BASE 0x40007898u +#define CYDEV_PHUB_TDMEM19_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM19_ORIG_TD0 0x40007898u +#define CYDEV_PHUB_TDMEM19_ORIG_TD1 0x4000789cu +#define CYDEV_PHUB_TDMEM20_BASE 0x400078a0u +#define CYDEV_PHUB_TDMEM20_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM20_ORIG_TD0 0x400078a0u +#define CYDEV_PHUB_TDMEM20_ORIG_TD1 0x400078a4u +#define CYDEV_PHUB_TDMEM21_BASE 0x400078a8u +#define CYDEV_PHUB_TDMEM21_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM21_ORIG_TD0 0x400078a8u +#define CYDEV_PHUB_TDMEM21_ORIG_TD1 0x400078acu +#define CYDEV_PHUB_TDMEM22_BASE 0x400078b0u +#define CYDEV_PHUB_TDMEM22_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM22_ORIG_TD0 0x400078b0u +#define CYDEV_PHUB_TDMEM22_ORIG_TD1 0x400078b4u +#define CYDEV_PHUB_TDMEM23_BASE 0x400078b8u +#define CYDEV_PHUB_TDMEM23_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM23_ORIG_TD0 0x400078b8u +#define CYDEV_PHUB_TDMEM23_ORIG_TD1 0x400078bcu +#define CYDEV_PHUB_TDMEM24_BASE 0x400078c0u +#define CYDEV_PHUB_TDMEM24_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM24_ORIG_TD0 0x400078c0u +#define CYDEV_PHUB_TDMEM24_ORIG_TD1 0x400078c4u +#define CYDEV_PHUB_TDMEM25_BASE 0x400078c8u +#define CYDEV_PHUB_TDMEM25_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM25_ORIG_TD0 0x400078c8u +#define CYDEV_PHUB_TDMEM25_ORIG_TD1 0x400078ccu +#define CYDEV_PHUB_TDMEM26_BASE 0x400078d0u +#define CYDEV_PHUB_TDMEM26_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM26_ORIG_TD0 0x400078d0u +#define CYDEV_PHUB_TDMEM26_ORIG_TD1 0x400078d4u +#define CYDEV_PHUB_TDMEM27_BASE 0x400078d8u +#define CYDEV_PHUB_TDMEM27_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM27_ORIG_TD0 0x400078d8u +#define CYDEV_PHUB_TDMEM27_ORIG_TD1 0x400078dcu +#define CYDEV_PHUB_TDMEM28_BASE 0x400078e0u +#define CYDEV_PHUB_TDMEM28_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM28_ORIG_TD0 0x400078e0u +#define CYDEV_PHUB_TDMEM28_ORIG_TD1 0x400078e4u +#define CYDEV_PHUB_TDMEM29_BASE 0x400078e8u +#define CYDEV_PHUB_TDMEM29_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM29_ORIG_TD0 0x400078e8u +#define CYDEV_PHUB_TDMEM29_ORIG_TD1 0x400078ecu +#define CYDEV_PHUB_TDMEM30_BASE 0x400078f0u +#define CYDEV_PHUB_TDMEM30_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM30_ORIG_TD0 0x400078f0u +#define CYDEV_PHUB_TDMEM30_ORIG_TD1 0x400078f4u +#define CYDEV_PHUB_TDMEM31_BASE 0x400078f8u +#define CYDEV_PHUB_TDMEM31_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM31_ORIG_TD0 0x400078f8u +#define CYDEV_PHUB_TDMEM31_ORIG_TD1 0x400078fcu +#define CYDEV_PHUB_TDMEM32_BASE 0x40007900u +#define CYDEV_PHUB_TDMEM32_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM32_ORIG_TD0 0x40007900u +#define CYDEV_PHUB_TDMEM32_ORIG_TD1 0x40007904u +#define CYDEV_PHUB_TDMEM33_BASE 0x40007908u +#define CYDEV_PHUB_TDMEM33_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM33_ORIG_TD0 0x40007908u +#define CYDEV_PHUB_TDMEM33_ORIG_TD1 0x4000790cu +#define CYDEV_PHUB_TDMEM34_BASE 0x40007910u +#define CYDEV_PHUB_TDMEM34_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM34_ORIG_TD0 0x40007910u +#define CYDEV_PHUB_TDMEM34_ORIG_TD1 0x40007914u +#define CYDEV_PHUB_TDMEM35_BASE 0x40007918u +#define CYDEV_PHUB_TDMEM35_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM35_ORIG_TD0 0x40007918u +#define CYDEV_PHUB_TDMEM35_ORIG_TD1 0x4000791cu +#define CYDEV_PHUB_TDMEM36_BASE 0x40007920u +#define CYDEV_PHUB_TDMEM36_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM36_ORIG_TD0 0x40007920u +#define CYDEV_PHUB_TDMEM36_ORIG_TD1 0x40007924u +#define CYDEV_PHUB_TDMEM37_BASE 0x40007928u +#define CYDEV_PHUB_TDMEM37_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM37_ORIG_TD0 0x40007928u +#define CYDEV_PHUB_TDMEM37_ORIG_TD1 0x4000792cu +#define CYDEV_PHUB_TDMEM38_BASE 0x40007930u +#define CYDEV_PHUB_TDMEM38_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM38_ORIG_TD0 0x40007930u +#define CYDEV_PHUB_TDMEM38_ORIG_TD1 0x40007934u +#define CYDEV_PHUB_TDMEM39_BASE 0x40007938u +#define CYDEV_PHUB_TDMEM39_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM39_ORIG_TD0 0x40007938u +#define CYDEV_PHUB_TDMEM39_ORIG_TD1 0x4000793cu +#define CYDEV_PHUB_TDMEM40_BASE 0x40007940u +#define CYDEV_PHUB_TDMEM40_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM40_ORIG_TD0 0x40007940u +#define CYDEV_PHUB_TDMEM40_ORIG_TD1 0x40007944u +#define CYDEV_PHUB_TDMEM41_BASE 0x40007948u +#define CYDEV_PHUB_TDMEM41_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM41_ORIG_TD0 0x40007948u +#define CYDEV_PHUB_TDMEM41_ORIG_TD1 0x4000794cu +#define CYDEV_PHUB_TDMEM42_BASE 0x40007950u +#define CYDEV_PHUB_TDMEM42_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM42_ORIG_TD0 0x40007950u +#define CYDEV_PHUB_TDMEM42_ORIG_TD1 0x40007954u +#define CYDEV_PHUB_TDMEM43_BASE 0x40007958u +#define CYDEV_PHUB_TDMEM43_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM43_ORIG_TD0 0x40007958u +#define CYDEV_PHUB_TDMEM43_ORIG_TD1 0x4000795cu +#define CYDEV_PHUB_TDMEM44_BASE 0x40007960u +#define CYDEV_PHUB_TDMEM44_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM44_ORIG_TD0 0x40007960u +#define CYDEV_PHUB_TDMEM44_ORIG_TD1 0x40007964u +#define CYDEV_PHUB_TDMEM45_BASE 0x40007968u +#define CYDEV_PHUB_TDMEM45_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM45_ORIG_TD0 0x40007968u +#define CYDEV_PHUB_TDMEM45_ORIG_TD1 0x4000796cu +#define CYDEV_PHUB_TDMEM46_BASE 0x40007970u +#define CYDEV_PHUB_TDMEM46_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM46_ORIG_TD0 0x40007970u +#define CYDEV_PHUB_TDMEM46_ORIG_TD1 0x40007974u +#define CYDEV_PHUB_TDMEM47_BASE 0x40007978u +#define CYDEV_PHUB_TDMEM47_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM47_ORIG_TD0 0x40007978u +#define CYDEV_PHUB_TDMEM47_ORIG_TD1 0x4000797cu +#define CYDEV_PHUB_TDMEM48_BASE 0x40007980u +#define CYDEV_PHUB_TDMEM48_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM48_ORIG_TD0 0x40007980u +#define CYDEV_PHUB_TDMEM48_ORIG_TD1 0x40007984u +#define CYDEV_PHUB_TDMEM49_BASE 0x40007988u +#define CYDEV_PHUB_TDMEM49_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM49_ORIG_TD0 0x40007988u +#define CYDEV_PHUB_TDMEM49_ORIG_TD1 0x4000798cu +#define CYDEV_PHUB_TDMEM50_BASE 0x40007990u +#define CYDEV_PHUB_TDMEM50_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM50_ORIG_TD0 0x40007990u +#define CYDEV_PHUB_TDMEM50_ORIG_TD1 0x40007994u +#define CYDEV_PHUB_TDMEM51_BASE 0x40007998u +#define CYDEV_PHUB_TDMEM51_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM51_ORIG_TD0 0x40007998u +#define CYDEV_PHUB_TDMEM51_ORIG_TD1 0x4000799cu +#define CYDEV_PHUB_TDMEM52_BASE 0x400079a0u +#define CYDEV_PHUB_TDMEM52_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM52_ORIG_TD0 0x400079a0u +#define CYDEV_PHUB_TDMEM52_ORIG_TD1 0x400079a4u +#define CYDEV_PHUB_TDMEM53_BASE 0x400079a8u +#define CYDEV_PHUB_TDMEM53_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM53_ORIG_TD0 0x400079a8u +#define CYDEV_PHUB_TDMEM53_ORIG_TD1 0x400079acu +#define CYDEV_PHUB_TDMEM54_BASE 0x400079b0u +#define CYDEV_PHUB_TDMEM54_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM54_ORIG_TD0 0x400079b0u +#define CYDEV_PHUB_TDMEM54_ORIG_TD1 0x400079b4u +#define CYDEV_PHUB_TDMEM55_BASE 0x400079b8u +#define CYDEV_PHUB_TDMEM55_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM55_ORIG_TD0 0x400079b8u +#define CYDEV_PHUB_TDMEM55_ORIG_TD1 0x400079bcu +#define CYDEV_PHUB_TDMEM56_BASE 0x400079c0u +#define CYDEV_PHUB_TDMEM56_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM56_ORIG_TD0 0x400079c0u +#define CYDEV_PHUB_TDMEM56_ORIG_TD1 0x400079c4u +#define CYDEV_PHUB_TDMEM57_BASE 0x400079c8u +#define CYDEV_PHUB_TDMEM57_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM57_ORIG_TD0 0x400079c8u +#define CYDEV_PHUB_TDMEM57_ORIG_TD1 0x400079ccu +#define CYDEV_PHUB_TDMEM58_BASE 0x400079d0u +#define CYDEV_PHUB_TDMEM58_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM58_ORIG_TD0 0x400079d0u +#define CYDEV_PHUB_TDMEM58_ORIG_TD1 0x400079d4u +#define CYDEV_PHUB_TDMEM59_BASE 0x400079d8u +#define CYDEV_PHUB_TDMEM59_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM59_ORIG_TD0 0x400079d8u +#define CYDEV_PHUB_TDMEM59_ORIG_TD1 0x400079dcu +#define CYDEV_PHUB_TDMEM60_BASE 0x400079e0u +#define CYDEV_PHUB_TDMEM60_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM60_ORIG_TD0 0x400079e0u +#define CYDEV_PHUB_TDMEM60_ORIG_TD1 0x400079e4u +#define CYDEV_PHUB_TDMEM61_BASE 0x400079e8u +#define CYDEV_PHUB_TDMEM61_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM61_ORIG_TD0 0x400079e8u +#define CYDEV_PHUB_TDMEM61_ORIG_TD1 0x400079ecu +#define CYDEV_PHUB_TDMEM62_BASE 0x400079f0u +#define CYDEV_PHUB_TDMEM62_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM62_ORIG_TD0 0x400079f0u +#define CYDEV_PHUB_TDMEM62_ORIG_TD1 0x400079f4u +#define CYDEV_PHUB_TDMEM63_BASE 0x400079f8u +#define CYDEV_PHUB_TDMEM63_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM63_ORIG_TD0 0x400079f8u +#define CYDEV_PHUB_TDMEM63_ORIG_TD1 0x400079fcu +#define CYDEV_PHUB_TDMEM64_BASE 0x40007a00u +#define CYDEV_PHUB_TDMEM64_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM64_ORIG_TD0 0x40007a00u +#define CYDEV_PHUB_TDMEM64_ORIG_TD1 0x40007a04u +#define CYDEV_PHUB_TDMEM65_BASE 0x40007a08u +#define CYDEV_PHUB_TDMEM65_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM65_ORIG_TD0 0x40007a08u +#define CYDEV_PHUB_TDMEM65_ORIG_TD1 0x40007a0cu +#define CYDEV_PHUB_TDMEM66_BASE 0x40007a10u +#define CYDEV_PHUB_TDMEM66_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM66_ORIG_TD0 0x40007a10u +#define CYDEV_PHUB_TDMEM66_ORIG_TD1 0x40007a14u +#define CYDEV_PHUB_TDMEM67_BASE 0x40007a18u +#define CYDEV_PHUB_TDMEM67_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM67_ORIG_TD0 0x40007a18u +#define CYDEV_PHUB_TDMEM67_ORIG_TD1 0x40007a1cu +#define CYDEV_PHUB_TDMEM68_BASE 0x40007a20u +#define CYDEV_PHUB_TDMEM68_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM68_ORIG_TD0 0x40007a20u +#define CYDEV_PHUB_TDMEM68_ORIG_TD1 0x40007a24u +#define CYDEV_PHUB_TDMEM69_BASE 0x40007a28u +#define CYDEV_PHUB_TDMEM69_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM69_ORIG_TD0 0x40007a28u +#define CYDEV_PHUB_TDMEM69_ORIG_TD1 0x40007a2cu +#define CYDEV_PHUB_TDMEM70_BASE 0x40007a30u +#define CYDEV_PHUB_TDMEM70_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM70_ORIG_TD0 0x40007a30u +#define CYDEV_PHUB_TDMEM70_ORIG_TD1 0x40007a34u +#define CYDEV_PHUB_TDMEM71_BASE 0x40007a38u +#define CYDEV_PHUB_TDMEM71_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM71_ORIG_TD0 0x40007a38u +#define CYDEV_PHUB_TDMEM71_ORIG_TD1 0x40007a3cu +#define CYDEV_PHUB_TDMEM72_BASE 0x40007a40u +#define CYDEV_PHUB_TDMEM72_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM72_ORIG_TD0 0x40007a40u +#define CYDEV_PHUB_TDMEM72_ORIG_TD1 0x40007a44u +#define CYDEV_PHUB_TDMEM73_BASE 0x40007a48u +#define CYDEV_PHUB_TDMEM73_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM73_ORIG_TD0 0x40007a48u +#define CYDEV_PHUB_TDMEM73_ORIG_TD1 0x40007a4cu +#define CYDEV_PHUB_TDMEM74_BASE 0x40007a50u +#define CYDEV_PHUB_TDMEM74_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM74_ORIG_TD0 0x40007a50u +#define CYDEV_PHUB_TDMEM74_ORIG_TD1 0x40007a54u +#define CYDEV_PHUB_TDMEM75_BASE 0x40007a58u +#define CYDEV_PHUB_TDMEM75_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM75_ORIG_TD0 0x40007a58u +#define CYDEV_PHUB_TDMEM75_ORIG_TD1 0x40007a5cu +#define CYDEV_PHUB_TDMEM76_BASE 0x40007a60u +#define CYDEV_PHUB_TDMEM76_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM76_ORIG_TD0 0x40007a60u +#define CYDEV_PHUB_TDMEM76_ORIG_TD1 0x40007a64u +#define CYDEV_PHUB_TDMEM77_BASE 0x40007a68u +#define CYDEV_PHUB_TDMEM77_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM77_ORIG_TD0 0x40007a68u +#define CYDEV_PHUB_TDMEM77_ORIG_TD1 0x40007a6cu +#define CYDEV_PHUB_TDMEM78_BASE 0x40007a70u +#define CYDEV_PHUB_TDMEM78_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM78_ORIG_TD0 0x40007a70u +#define CYDEV_PHUB_TDMEM78_ORIG_TD1 0x40007a74u +#define CYDEV_PHUB_TDMEM79_BASE 0x40007a78u +#define CYDEV_PHUB_TDMEM79_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM79_ORIG_TD0 0x40007a78u +#define CYDEV_PHUB_TDMEM79_ORIG_TD1 0x40007a7cu +#define CYDEV_PHUB_TDMEM80_BASE 0x40007a80u +#define CYDEV_PHUB_TDMEM80_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM80_ORIG_TD0 0x40007a80u +#define CYDEV_PHUB_TDMEM80_ORIG_TD1 0x40007a84u +#define CYDEV_PHUB_TDMEM81_BASE 0x40007a88u +#define CYDEV_PHUB_TDMEM81_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM81_ORIG_TD0 0x40007a88u +#define CYDEV_PHUB_TDMEM81_ORIG_TD1 0x40007a8cu +#define CYDEV_PHUB_TDMEM82_BASE 0x40007a90u +#define CYDEV_PHUB_TDMEM82_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM82_ORIG_TD0 0x40007a90u +#define CYDEV_PHUB_TDMEM82_ORIG_TD1 0x40007a94u +#define CYDEV_PHUB_TDMEM83_BASE 0x40007a98u +#define CYDEV_PHUB_TDMEM83_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM83_ORIG_TD0 0x40007a98u +#define CYDEV_PHUB_TDMEM83_ORIG_TD1 0x40007a9cu +#define CYDEV_PHUB_TDMEM84_BASE 0x40007aa0u +#define CYDEV_PHUB_TDMEM84_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM84_ORIG_TD0 0x40007aa0u +#define CYDEV_PHUB_TDMEM84_ORIG_TD1 0x40007aa4u +#define CYDEV_PHUB_TDMEM85_BASE 0x40007aa8u +#define CYDEV_PHUB_TDMEM85_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM85_ORIG_TD0 0x40007aa8u +#define CYDEV_PHUB_TDMEM85_ORIG_TD1 0x40007aacu +#define CYDEV_PHUB_TDMEM86_BASE 0x40007ab0u +#define CYDEV_PHUB_TDMEM86_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM86_ORIG_TD0 0x40007ab0u +#define CYDEV_PHUB_TDMEM86_ORIG_TD1 0x40007ab4u +#define CYDEV_PHUB_TDMEM87_BASE 0x40007ab8u +#define CYDEV_PHUB_TDMEM87_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM87_ORIG_TD0 0x40007ab8u +#define CYDEV_PHUB_TDMEM87_ORIG_TD1 0x40007abcu +#define CYDEV_PHUB_TDMEM88_BASE 0x40007ac0u +#define CYDEV_PHUB_TDMEM88_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM88_ORIG_TD0 0x40007ac0u +#define CYDEV_PHUB_TDMEM88_ORIG_TD1 0x40007ac4u +#define CYDEV_PHUB_TDMEM89_BASE 0x40007ac8u +#define CYDEV_PHUB_TDMEM89_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM89_ORIG_TD0 0x40007ac8u +#define CYDEV_PHUB_TDMEM89_ORIG_TD1 0x40007accu +#define CYDEV_PHUB_TDMEM90_BASE 0x40007ad0u +#define CYDEV_PHUB_TDMEM90_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM90_ORIG_TD0 0x40007ad0u +#define CYDEV_PHUB_TDMEM90_ORIG_TD1 0x40007ad4u +#define CYDEV_PHUB_TDMEM91_BASE 0x40007ad8u +#define CYDEV_PHUB_TDMEM91_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM91_ORIG_TD0 0x40007ad8u +#define CYDEV_PHUB_TDMEM91_ORIG_TD1 0x40007adcu +#define CYDEV_PHUB_TDMEM92_BASE 0x40007ae0u +#define CYDEV_PHUB_TDMEM92_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM92_ORIG_TD0 0x40007ae0u +#define CYDEV_PHUB_TDMEM92_ORIG_TD1 0x40007ae4u +#define CYDEV_PHUB_TDMEM93_BASE 0x40007ae8u +#define CYDEV_PHUB_TDMEM93_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM93_ORIG_TD0 0x40007ae8u +#define CYDEV_PHUB_TDMEM93_ORIG_TD1 0x40007aecu +#define CYDEV_PHUB_TDMEM94_BASE 0x40007af0u +#define CYDEV_PHUB_TDMEM94_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM94_ORIG_TD0 0x40007af0u +#define CYDEV_PHUB_TDMEM94_ORIG_TD1 0x40007af4u +#define CYDEV_PHUB_TDMEM95_BASE 0x40007af8u +#define CYDEV_PHUB_TDMEM95_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM95_ORIG_TD0 0x40007af8u +#define CYDEV_PHUB_TDMEM95_ORIG_TD1 0x40007afcu +#define CYDEV_PHUB_TDMEM96_BASE 0x40007b00u +#define CYDEV_PHUB_TDMEM96_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM96_ORIG_TD0 0x40007b00u +#define CYDEV_PHUB_TDMEM96_ORIG_TD1 0x40007b04u +#define CYDEV_PHUB_TDMEM97_BASE 0x40007b08u +#define CYDEV_PHUB_TDMEM97_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM97_ORIG_TD0 0x40007b08u +#define CYDEV_PHUB_TDMEM97_ORIG_TD1 0x40007b0cu +#define CYDEV_PHUB_TDMEM98_BASE 0x40007b10u +#define CYDEV_PHUB_TDMEM98_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM98_ORIG_TD0 0x40007b10u +#define CYDEV_PHUB_TDMEM98_ORIG_TD1 0x40007b14u +#define CYDEV_PHUB_TDMEM99_BASE 0x40007b18u +#define CYDEV_PHUB_TDMEM99_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM99_ORIG_TD0 0x40007b18u +#define CYDEV_PHUB_TDMEM99_ORIG_TD1 0x40007b1cu +#define CYDEV_PHUB_TDMEM100_BASE 0x40007b20u +#define CYDEV_PHUB_TDMEM100_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM100_ORIG_TD0 0x40007b20u +#define CYDEV_PHUB_TDMEM100_ORIG_TD1 0x40007b24u +#define CYDEV_PHUB_TDMEM101_BASE 0x40007b28u +#define CYDEV_PHUB_TDMEM101_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM101_ORIG_TD0 0x40007b28u +#define CYDEV_PHUB_TDMEM101_ORIG_TD1 0x40007b2cu +#define CYDEV_PHUB_TDMEM102_BASE 0x40007b30u +#define CYDEV_PHUB_TDMEM102_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM102_ORIG_TD0 0x40007b30u +#define CYDEV_PHUB_TDMEM102_ORIG_TD1 0x40007b34u +#define CYDEV_PHUB_TDMEM103_BASE 0x40007b38u +#define CYDEV_PHUB_TDMEM103_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM103_ORIG_TD0 0x40007b38u +#define CYDEV_PHUB_TDMEM103_ORIG_TD1 0x40007b3cu +#define CYDEV_PHUB_TDMEM104_BASE 0x40007b40u +#define CYDEV_PHUB_TDMEM104_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM104_ORIG_TD0 0x40007b40u +#define CYDEV_PHUB_TDMEM104_ORIG_TD1 0x40007b44u +#define CYDEV_PHUB_TDMEM105_BASE 0x40007b48u +#define CYDEV_PHUB_TDMEM105_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM105_ORIG_TD0 0x40007b48u +#define CYDEV_PHUB_TDMEM105_ORIG_TD1 0x40007b4cu +#define CYDEV_PHUB_TDMEM106_BASE 0x40007b50u +#define CYDEV_PHUB_TDMEM106_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM106_ORIG_TD0 0x40007b50u +#define CYDEV_PHUB_TDMEM106_ORIG_TD1 0x40007b54u +#define CYDEV_PHUB_TDMEM107_BASE 0x40007b58u +#define CYDEV_PHUB_TDMEM107_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM107_ORIG_TD0 0x40007b58u +#define CYDEV_PHUB_TDMEM107_ORIG_TD1 0x40007b5cu +#define CYDEV_PHUB_TDMEM108_BASE 0x40007b60u +#define CYDEV_PHUB_TDMEM108_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM108_ORIG_TD0 0x40007b60u +#define CYDEV_PHUB_TDMEM108_ORIG_TD1 0x40007b64u +#define CYDEV_PHUB_TDMEM109_BASE 0x40007b68u +#define CYDEV_PHUB_TDMEM109_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM109_ORIG_TD0 0x40007b68u +#define CYDEV_PHUB_TDMEM109_ORIG_TD1 0x40007b6cu +#define CYDEV_PHUB_TDMEM110_BASE 0x40007b70u +#define CYDEV_PHUB_TDMEM110_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM110_ORIG_TD0 0x40007b70u +#define CYDEV_PHUB_TDMEM110_ORIG_TD1 0x40007b74u +#define CYDEV_PHUB_TDMEM111_BASE 0x40007b78u +#define CYDEV_PHUB_TDMEM111_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM111_ORIG_TD0 0x40007b78u +#define CYDEV_PHUB_TDMEM111_ORIG_TD1 0x40007b7cu +#define CYDEV_PHUB_TDMEM112_BASE 0x40007b80u +#define CYDEV_PHUB_TDMEM112_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM112_ORIG_TD0 0x40007b80u +#define CYDEV_PHUB_TDMEM112_ORIG_TD1 0x40007b84u +#define CYDEV_PHUB_TDMEM113_BASE 0x40007b88u +#define CYDEV_PHUB_TDMEM113_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM113_ORIG_TD0 0x40007b88u +#define CYDEV_PHUB_TDMEM113_ORIG_TD1 0x40007b8cu +#define CYDEV_PHUB_TDMEM114_BASE 0x40007b90u +#define CYDEV_PHUB_TDMEM114_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM114_ORIG_TD0 0x40007b90u +#define CYDEV_PHUB_TDMEM114_ORIG_TD1 0x40007b94u +#define CYDEV_PHUB_TDMEM115_BASE 0x40007b98u +#define CYDEV_PHUB_TDMEM115_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM115_ORIG_TD0 0x40007b98u +#define CYDEV_PHUB_TDMEM115_ORIG_TD1 0x40007b9cu +#define CYDEV_PHUB_TDMEM116_BASE 0x40007ba0u +#define CYDEV_PHUB_TDMEM116_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM116_ORIG_TD0 0x40007ba0u +#define CYDEV_PHUB_TDMEM116_ORIG_TD1 0x40007ba4u +#define CYDEV_PHUB_TDMEM117_BASE 0x40007ba8u +#define CYDEV_PHUB_TDMEM117_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM117_ORIG_TD0 0x40007ba8u +#define CYDEV_PHUB_TDMEM117_ORIG_TD1 0x40007bacu +#define CYDEV_PHUB_TDMEM118_BASE 0x40007bb0u +#define CYDEV_PHUB_TDMEM118_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM118_ORIG_TD0 0x40007bb0u +#define CYDEV_PHUB_TDMEM118_ORIG_TD1 0x40007bb4u +#define CYDEV_PHUB_TDMEM119_BASE 0x40007bb8u +#define CYDEV_PHUB_TDMEM119_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM119_ORIG_TD0 0x40007bb8u +#define CYDEV_PHUB_TDMEM119_ORIG_TD1 0x40007bbcu +#define CYDEV_PHUB_TDMEM120_BASE 0x40007bc0u +#define CYDEV_PHUB_TDMEM120_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM120_ORIG_TD0 0x40007bc0u +#define CYDEV_PHUB_TDMEM120_ORIG_TD1 0x40007bc4u +#define CYDEV_PHUB_TDMEM121_BASE 0x40007bc8u +#define CYDEV_PHUB_TDMEM121_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM121_ORIG_TD0 0x40007bc8u +#define CYDEV_PHUB_TDMEM121_ORIG_TD1 0x40007bccu +#define CYDEV_PHUB_TDMEM122_BASE 0x40007bd0u +#define CYDEV_PHUB_TDMEM122_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM122_ORIG_TD0 0x40007bd0u +#define CYDEV_PHUB_TDMEM122_ORIG_TD1 0x40007bd4u +#define CYDEV_PHUB_TDMEM123_BASE 0x40007bd8u +#define CYDEV_PHUB_TDMEM123_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM123_ORIG_TD0 0x40007bd8u +#define CYDEV_PHUB_TDMEM123_ORIG_TD1 0x40007bdcu +#define CYDEV_PHUB_TDMEM124_BASE 0x40007be0u +#define CYDEV_PHUB_TDMEM124_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM124_ORIG_TD0 0x40007be0u +#define CYDEV_PHUB_TDMEM124_ORIG_TD1 0x40007be4u +#define CYDEV_PHUB_TDMEM125_BASE 0x40007be8u +#define CYDEV_PHUB_TDMEM125_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM125_ORIG_TD0 0x40007be8u +#define CYDEV_PHUB_TDMEM125_ORIG_TD1 0x40007becu +#define CYDEV_PHUB_TDMEM126_BASE 0x40007bf0u +#define CYDEV_PHUB_TDMEM126_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM126_ORIG_TD0 0x40007bf0u +#define CYDEV_PHUB_TDMEM126_ORIG_TD1 0x40007bf4u +#define CYDEV_PHUB_TDMEM127_BASE 0x40007bf8u +#define CYDEV_PHUB_TDMEM127_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM127_ORIG_TD0 0x40007bf8u +#define CYDEV_PHUB_TDMEM127_ORIG_TD1 0x40007bfcu +#define CYDEV_EE_BASE 0x40008000u +#define CYDEV_EE_SIZE 0x00000800u +#define CYDEV_EE_DATA_MBASE 0x40008000u +#define CYDEV_EE_DATA_MSIZE 0x00000800u +#define CYDEV_CAN0_BASE 0x4000a000u +#define CYDEV_CAN0_SIZE 0x000002a0u +#define CYDEV_CAN0_CSR_BASE 0x4000a000u +#define CYDEV_CAN0_CSR_SIZE 0x00000018u +#define CYDEV_CAN0_CSR_INT_SR 0x4000a000u +#define CYDEV_CAN0_CSR_INT_EN 0x4000a004u +#define CYDEV_CAN0_CSR_BUF_SR 0x4000a008u +#define CYDEV_CAN0_CSR_ERR_SR 0x4000a00cu +#define CYDEV_CAN0_CSR_CMD 0x4000a010u +#define CYDEV_CAN0_CSR_CFG 0x4000a014u +#define CYDEV_CAN0_TX0_BASE 0x4000a020u +#define CYDEV_CAN0_TX0_SIZE 0x00000010u +#define CYDEV_CAN0_TX0_CMD 0x4000a020u +#define CYDEV_CAN0_TX0_ID 0x4000a024u +#define CYDEV_CAN0_TX0_DH 0x4000a028u +#define CYDEV_CAN0_TX0_DL 0x4000a02cu +#define CYDEV_CAN0_TX1_BASE 0x4000a030u +#define CYDEV_CAN0_TX1_SIZE 0x00000010u +#define CYDEV_CAN0_TX1_CMD 0x4000a030u +#define CYDEV_CAN0_TX1_ID 0x4000a034u +#define CYDEV_CAN0_TX1_DH 0x4000a038u +#define CYDEV_CAN0_TX1_DL 0x4000a03cu +#define CYDEV_CAN0_TX2_BASE 0x4000a040u +#define CYDEV_CAN0_TX2_SIZE 0x00000010u +#define CYDEV_CAN0_TX2_CMD 0x4000a040u +#define CYDEV_CAN0_TX2_ID 0x4000a044u +#define CYDEV_CAN0_TX2_DH 0x4000a048u +#define CYDEV_CAN0_TX2_DL 0x4000a04cu +#define CYDEV_CAN0_TX3_BASE 0x4000a050u +#define CYDEV_CAN0_TX3_SIZE 0x00000010u +#define CYDEV_CAN0_TX3_CMD 0x4000a050u +#define CYDEV_CAN0_TX3_ID 0x4000a054u +#define CYDEV_CAN0_TX3_DH 0x4000a058u +#define CYDEV_CAN0_TX3_DL 0x4000a05cu +#define CYDEV_CAN0_TX4_BASE 0x4000a060u +#define CYDEV_CAN0_TX4_SIZE 0x00000010u +#define CYDEV_CAN0_TX4_CMD 0x4000a060u +#define CYDEV_CAN0_TX4_ID 0x4000a064u +#define CYDEV_CAN0_TX4_DH 0x4000a068u +#define CYDEV_CAN0_TX4_DL 0x4000a06cu +#define CYDEV_CAN0_TX5_BASE 0x4000a070u +#define CYDEV_CAN0_TX5_SIZE 0x00000010u +#define CYDEV_CAN0_TX5_CMD 0x4000a070u +#define CYDEV_CAN0_TX5_ID 0x4000a074u +#define CYDEV_CAN0_TX5_DH 0x4000a078u +#define CYDEV_CAN0_TX5_DL 0x4000a07cu +#define CYDEV_CAN0_TX6_BASE 0x4000a080u +#define CYDEV_CAN0_TX6_SIZE 0x00000010u +#define CYDEV_CAN0_TX6_CMD 0x4000a080u +#define CYDEV_CAN0_TX6_ID 0x4000a084u +#define CYDEV_CAN0_TX6_DH 0x4000a088u +#define CYDEV_CAN0_TX6_DL 0x4000a08cu +#define CYDEV_CAN0_TX7_BASE 0x4000a090u +#define CYDEV_CAN0_TX7_SIZE 0x00000010u +#define CYDEV_CAN0_TX7_CMD 0x4000a090u +#define CYDEV_CAN0_TX7_ID 0x4000a094u +#define CYDEV_CAN0_TX7_DH 0x4000a098u +#define CYDEV_CAN0_TX7_DL 0x4000a09cu +#define CYDEV_CAN0_RX0_BASE 0x4000a0a0u +#define CYDEV_CAN0_RX0_SIZE 0x00000020u +#define CYDEV_CAN0_RX0_CMD 0x4000a0a0u +#define CYDEV_CAN0_RX0_ID 0x4000a0a4u +#define CYDEV_CAN0_RX0_DH 0x4000a0a8u +#define CYDEV_CAN0_RX0_DL 0x4000a0acu +#define CYDEV_CAN0_RX0_AMR 0x4000a0b0u +#define CYDEV_CAN0_RX0_ACR 0x4000a0b4u +#define CYDEV_CAN0_RX0_AMRD 0x4000a0b8u +#define CYDEV_CAN0_RX0_ACRD 0x4000a0bcu +#define CYDEV_CAN0_RX1_BASE 0x4000a0c0u +#define CYDEV_CAN0_RX1_SIZE 0x00000020u +#define CYDEV_CAN0_RX1_CMD 0x4000a0c0u +#define CYDEV_CAN0_RX1_ID 0x4000a0c4u +#define CYDEV_CAN0_RX1_DH 0x4000a0c8u +#define CYDEV_CAN0_RX1_DL 0x4000a0ccu +#define CYDEV_CAN0_RX1_AMR 0x4000a0d0u +#define CYDEV_CAN0_RX1_ACR 0x4000a0d4u +#define CYDEV_CAN0_RX1_AMRD 0x4000a0d8u +#define CYDEV_CAN0_RX1_ACRD 0x4000a0dcu +#define CYDEV_CAN0_RX2_BASE 0x4000a0e0u +#define CYDEV_CAN0_RX2_SIZE 0x00000020u +#define CYDEV_CAN0_RX2_CMD 0x4000a0e0u +#define CYDEV_CAN0_RX2_ID 0x4000a0e4u +#define CYDEV_CAN0_RX2_DH 0x4000a0e8u +#define CYDEV_CAN0_RX2_DL 0x4000a0ecu +#define CYDEV_CAN0_RX2_AMR 0x4000a0f0u +#define CYDEV_CAN0_RX2_ACR 0x4000a0f4u +#define CYDEV_CAN0_RX2_AMRD 0x4000a0f8u +#define CYDEV_CAN0_RX2_ACRD 0x4000a0fcu +#define CYDEV_CAN0_RX3_BASE 0x4000a100u +#define CYDEV_CAN0_RX3_SIZE 0x00000020u +#define CYDEV_CAN0_RX3_CMD 0x4000a100u +#define CYDEV_CAN0_RX3_ID 0x4000a104u +#define CYDEV_CAN0_RX3_DH 0x4000a108u +#define CYDEV_CAN0_RX3_DL 0x4000a10cu +#define CYDEV_CAN0_RX3_AMR 0x4000a110u +#define CYDEV_CAN0_RX3_ACR 0x4000a114u +#define CYDEV_CAN0_RX3_AMRD 0x4000a118u +#define CYDEV_CAN0_RX3_ACRD 0x4000a11cu +#define CYDEV_CAN0_RX4_BASE 0x4000a120u +#define CYDEV_CAN0_RX4_SIZE 0x00000020u +#define CYDEV_CAN0_RX4_CMD 0x4000a120u +#define CYDEV_CAN0_RX4_ID 0x4000a124u +#define CYDEV_CAN0_RX4_DH 0x4000a128u +#define CYDEV_CAN0_RX4_DL 0x4000a12cu +#define CYDEV_CAN0_RX4_AMR 0x4000a130u +#define CYDEV_CAN0_RX4_ACR 0x4000a134u +#define CYDEV_CAN0_RX4_AMRD 0x4000a138u +#define CYDEV_CAN0_RX4_ACRD 0x4000a13cu +#define CYDEV_CAN0_RX5_BASE 0x4000a140u +#define CYDEV_CAN0_RX5_SIZE 0x00000020u +#define CYDEV_CAN0_RX5_CMD 0x4000a140u +#define CYDEV_CAN0_RX5_ID 0x4000a144u +#define CYDEV_CAN0_RX5_DH 0x4000a148u +#define CYDEV_CAN0_RX5_DL 0x4000a14cu +#define CYDEV_CAN0_RX5_AMR 0x4000a150u +#define CYDEV_CAN0_RX5_ACR 0x4000a154u +#define CYDEV_CAN0_RX5_AMRD 0x4000a158u +#define CYDEV_CAN0_RX5_ACRD 0x4000a15cu +#define CYDEV_CAN0_RX6_BASE 0x4000a160u +#define CYDEV_CAN0_RX6_SIZE 0x00000020u +#define CYDEV_CAN0_RX6_CMD 0x4000a160u +#define CYDEV_CAN0_RX6_ID 0x4000a164u +#define CYDEV_CAN0_RX6_DH 0x4000a168u +#define CYDEV_CAN0_RX6_DL 0x4000a16cu +#define CYDEV_CAN0_RX6_AMR 0x4000a170u +#define CYDEV_CAN0_RX6_ACR 0x4000a174u +#define CYDEV_CAN0_RX6_AMRD 0x4000a178u +#define CYDEV_CAN0_RX6_ACRD 0x4000a17cu +#define CYDEV_CAN0_RX7_BASE 0x4000a180u +#define CYDEV_CAN0_RX7_SIZE 0x00000020u +#define CYDEV_CAN0_RX7_CMD 0x4000a180u +#define CYDEV_CAN0_RX7_ID 0x4000a184u +#define CYDEV_CAN0_RX7_DH 0x4000a188u +#define CYDEV_CAN0_RX7_DL 0x4000a18cu +#define CYDEV_CAN0_RX7_AMR 0x4000a190u +#define CYDEV_CAN0_RX7_ACR 0x4000a194u +#define CYDEV_CAN0_RX7_AMRD 0x4000a198u +#define CYDEV_CAN0_RX7_ACRD 0x4000a19cu +#define CYDEV_CAN0_RX8_BASE 0x4000a1a0u +#define CYDEV_CAN0_RX8_SIZE 0x00000020u +#define CYDEV_CAN0_RX8_CMD 0x4000a1a0u +#define CYDEV_CAN0_RX8_ID 0x4000a1a4u +#define CYDEV_CAN0_RX8_DH 0x4000a1a8u +#define CYDEV_CAN0_RX8_DL 0x4000a1acu +#define CYDEV_CAN0_RX8_AMR 0x4000a1b0u +#define CYDEV_CAN0_RX8_ACR 0x4000a1b4u +#define CYDEV_CAN0_RX8_AMRD 0x4000a1b8u +#define CYDEV_CAN0_RX8_ACRD 0x4000a1bcu +#define CYDEV_CAN0_RX9_BASE 0x4000a1c0u +#define CYDEV_CAN0_RX9_SIZE 0x00000020u +#define CYDEV_CAN0_RX9_CMD 0x4000a1c0u +#define CYDEV_CAN0_RX9_ID 0x4000a1c4u +#define CYDEV_CAN0_RX9_DH 0x4000a1c8u +#define CYDEV_CAN0_RX9_DL 0x4000a1ccu +#define CYDEV_CAN0_RX9_AMR 0x4000a1d0u +#define CYDEV_CAN0_RX9_ACR 0x4000a1d4u +#define CYDEV_CAN0_RX9_AMRD 0x4000a1d8u +#define CYDEV_CAN0_RX9_ACRD 0x4000a1dcu +#define CYDEV_CAN0_RX10_BASE 0x4000a1e0u +#define CYDEV_CAN0_RX10_SIZE 0x00000020u +#define CYDEV_CAN0_RX10_CMD 0x4000a1e0u +#define CYDEV_CAN0_RX10_ID 0x4000a1e4u +#define CYDEV_CAN0_RX10_DH 0x4000a1e8u +#define CYDEV_CAN0_RX10_DL 0x4000a1ecu +#define CYDEV_CAN0_RX10_AMR 0x4000a1f0u +#define CYDEV_CAN0_RX10_ACR 0x4000a1f4u +#define CYDEV_CAN0_RX10_AMRD 0x4000a1f8u +#define CYDEV_CAN0_RX10_ACRD 0x4000a1fcu +#define CYDEV_CAN0_RX11_BASE 0x4000a200u +#define CYDEV_CAN0_RX11_SIZE 0x00000020u +#define CYDEV_CAN0_RX11_CMD 0x4000a200u +#define CYDEV_CAN0_RX11_ID 0x4000a204u +#define CYDEV_CAN0_RX11_DH 0x4000a208u +#define CYDEV_CAN0_RX11_DL 0x4000a20cu +#define CYDEV_CAN0_RX11_AMR 0x4000a210u +#define CYDEV_CAN0_RX11_ACR 0x4000a214u +#define CYDEV_CAN0_RX11_AMRD 0x4000a218u +#define CYDEV_CAN0_RX11_ACRD 0x4000a21cu +#define CYDEV_CAN0_RX12_BASE 0x4000a220u +#define CYDEV_CAN0_RX12_SIZE 0x00000020u +#define CYDEV_CAN0_RX12_CMD 0x4000a220u +#define CYDEV_CAN0_RX12_ID 0x4000a224u +#define CYDEV_CAN0_RX12_DH 0x4000a228u +#define CYDEV_CAN0_RX12_DL 0x4000a22cu +#define CYDEV_CAN0_RX12_AMR 0x4000a230u +#define CYDEV_CAN0_RX12_ACR 0x4000a234u +#define CYDEV_CAN0_RX12_AMRD 0x4000a238u +#define CYDEV_CAN0_RX12_ACRD 0x4000a23cu +#define CYDEV_CAN0_RX13_BASE 0x4000a240u +#define CYDEV_CAN0_RX13_SIZE 0x00000020u +#define CYDEV_CAN0_RX13_CMD 0x4000a240u +#define CYDEV_CAN0_RX13_ID 0x4000a244u +#define CYDEV_CAN0_RX13_DH 0x4000a248u +#define CYDEV_CAN0_RX13_DL 0x4000a24cu +#define CYDEV_CAN0_RX13_AMR 0x4000a250u +#define CYDEV_CAN0_RX13_ACR 0x4000a254u +#define CYDEV_CAN0_RX13_AMRD 0x4000a258u +#define CYDEV_CAN0_RX13_ACRD 0x4000a25cu +#define CYDEV_CAN0_RX14_BASE 0x4000a260u +#define CYDEV_CAN0_RX14_SIZE 0x00000020u +#define CYDEV_CAN0_RX14_CMD 0x4000a260u +#define CYDEV_CAN0_RX14_ID 0x4000a264u +#define CYDEV_CAN0_RX14_DH 0x4000a268u +#define CYDEV_CAN0_RX14_DL 0x4000a26cu +#define CYDEV_CAN0_RX14_AMR 0x4000a270u +#define CYDEV_CAN0_RX14_ACR 0x4000a274u +#define CYDEV_CAN0_RX14_AMRD 0x4000a278u +#define CYDEV_CAN0_RX14_ACRD 0x4000a27cu +#define CYDEV_CAN0_RX15_BASE 0x4000a280u +#define CYDEV_CAN0_RX15_SIZE 0x00000020u +#define CYDEV_CAN0_RX15_CMD 0x4000a280u +#define CYDEV_CAN0_RX15_ID 0x4000a284u +#define CYDEV_CAN0_RX15_DH 0x4000a288u +#define CYDEV_CAN0_RX15_DL 0x4000a28cu +#define CYDEV_CAN0_RX15_AMR 0x4000a290u +#define CYDEV_CAN0_RX15_ACR 0x4000a294u +#define CYDEV_CAN0_RX15_AMRD 0x4000a298u +#define CYDEV_CAN0_RX15_ACRD 0x4000a29cu +#define CYDEV_DFB0_BASE 0x4000c000u +#define CYDEV_DFB0_SIZE 0x000007b5u +#define CYDEV_DFB0_DPA_SRAM_BASE 0x4000c000u +#define CYDEV_DFB0_DPA_SRAM_SIZE 0x00000200u +#define CYDEV_DFB0_DPA_SRAM_DATA_MBASE 0x4000c000u +#define CYDEV_DFB0_DPA_SRAM_DATA_MSIZE 0x00000200u +#define CYDEV_DFB0_DPB_SRAM_BASE 0x4000c200u +#define CYDEV_DFB0_DPB_SRAM_SIZE 0x00000200u +#define CYDEV_DFB0_DPB_SRAM_DATA_MBASE 0x4000c200u +#define CYDEV_DFB0_DPB_SRAM_DATA_MSIZE 0x00000200u +#define CYDEV_DFB0_CSA_SRAM_BASE 0x4000c400u +#define CYDEV_DFB0_CSA_SRAM_SIZE 0x00000100u +#define CYDEV_DFB0_CSA_SRAM_DATA_MBASE 0x4000c400u +#define CYDEV_DFB0_CSA_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_CSB_SRAM_BASE 0x4000c500u +#define CYDEV_DFB0_CSB_SRAM_SIZE 0x00000100u +#define CYDEV_DFB0_CSB_SRAM_DATA_MBASE 0x4000c500u +#define CYDEV_DFB0_CSB_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_FSM_SRAM_BASE 0x4000c600u +#define CYDEV_DFB0_FSM_SRAM_SIZE 0x00000100u +#define CYDEV_DFB0_FSM_SRAM_DATA_MBASE 0x4000c600u +#define CYDEV_DFB0_FSM_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_ACU_SRAM_BASE 0x4000c700u +#define CYDEV_DFB0_ACU_SRAM_SIZE 0x00000040u +#define CYDEV_DFB0_ACU_SRAM_DATA_MBASE 0x4000c700u +#define CYDEV_DFB0_ACU_SRAM_DATA_MSIZE 0x00000040u +#define CYDEV_DFB0_CR 0x4000c780u +#define CYDEV_DFB0_SR 0x4000c784u +#define CYDEV_DFB0_RAM_EN 0x4000c788u +#define CYDEV_DFB0_RAM_DIR 0x4000c78cu +#define CYDEV_DFB0_SEMA 0x4000c790u +#define CYDEV_DFB0_DSI_CTRL 0x4000c794u +#define CYDEV_DFB0_INT_CTRL 0x4000c798u +#define CYDEV_DFB0_DMA_CTRL 0x4000c79cu +#define CYDEV_DFB0_STAGEA 0x4000c7a0u +#define CYDEV_DFB0_STAGEAM 0x4000c7a1u +#define CYDEV_DFB0_STAGEAH 0x4000c7a2u +#define CYDEV_DFB0_STAGEB 0x4000c7a4u +#define CYDEV_DFB0_STAGEBM 0x4000c7a5u +#define CYDEV_DFB0_STAGEBH 0x4000c7a6u +#define CYDEV_DFB0_HOLDA 0x4000c7a8u +#define CYDEV_DFB0_HOLDAM 0x4000c7a9u +#define CYDEV_DFB0_HOLDAH 0x4000c7aau +#define CYDEV_DFB0_HOLDAS 0x4000c7abu +#define CYDEV_DFB0_HOLDB 0x4000c7acu +#define CYDEV_DFB0_HOLDBM 0x4000c7adu +#define CYDEV_DFB0_HOLDBH 0x4000c7aeu +#define CYDEV_DFB0_HOLDBS 0x4000c7afu +#define CYDEV_DFB0_COHER 0x4000c7b0u +#define CYDEV_DFB0_DALIGN 0x4000c7b4u +#define CYDEV_UCFG_BASE 0x40010000u +#define CYDEV_UCFG_SIZE 0x00005040u +#define CYDEV_UCFG_B0_BASE 0x40010000u +#define CYDEV_UCFG_B0_SIZE 0x00000fefu +#define CYDEV_UCFG_B0_P0_BASE 0x40010000u +#define CYDEV_UCFG_B0_P0_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P0_U0_BASE 0x40010000u +#define CYDEV_UCFG_B0_P0_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT0 0x40010000u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT1 0x40010004u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT2 0x40010008u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT3 0x4001000cu +#define CYDEV_UCFG_B0_P0_U0_PLD_IT4 0x40010010u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT5 0x40010014u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT6 0x40010018u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT7 0x4001001cu +#define CYDEV_UCFG_B0_P0_U0_PLD_IT8 0x40010020u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT9 0x40010024u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT10 0x40010028u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT11 0x4001002cu +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT0 0x40010030u +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT1 0x40010032u +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT2 0x40010034u +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT3 0x40010036u +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST 0x40010038u +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB 0x4001003au +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET 0x4001003cu +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS 0x4001003eu +#define CYDEV_UCFG_B0_P0_U0_CFG0 0x40010040u +#define CYDEV_UCFG_B0_P0_U0_CFG1 0x40010041u +#define CYDEV_UCFG_B0_P0_U0_CFG2 0x40010042u +#define CYDEV_UCFG_B0_P0_U0_CFG3 0x40010043u +#define CYDEV_UCFG_B0_P0_U0_CFG4 0x40010044u +#define CYDEV_UCFG_B0_P0_U0_CFG5 0x40010045u +#define CYDEV_UCFG_B0_P0_U0_CFG6 0x40010046u +#define CYDEV_UCFG_B0_P0_U0_CFG7 0x40010047u +#define CYDEV_UCFG_B0_P0_U0_CFG8 0x40010048u +#define CYDEV_UCFG_B0_P0_U0_CFG9 0x40010049u +#define CYDEV_UCFG_B0_P0_U0_CFG10 0x4001004au +#define CYDEV_UCFG_B0_P0_U0_CFG11 0x4001004bu +#define CYDEV_UCFG_B0_P0_U0_CFG12 0x4001004cu +#define CYDEV_UCFG_B0_P0_U0_CFG13 0x4001004du +#define CYDEV_UCFG_B0_P0_U0_CFG14 0x4001004eu +#define CYDEV_UCFG_B0_P0_U0_CFG15 0x4001004fu +#define CYDEV_UCFG_B0_P0_U0_CFG16 0x40010050u +#define CYDEV_UCFG_B0_P0_U0_CFG17 0x40010051u +#define CYDEV_UCFG_B0_P0_U0_CFG18 0x40010052u +#define CYDEV_UCFG_B0_P0_U0_CFG19 0x40010053u +#define CYDEV_UCFG_B0_P0_U0_CFG20 0x40010054u +#define CYDEV_UCFG_B0_P0_U0_CFG21 0x40010055u +#define CYDEV_UCFG_B0_P0_U0_CFG22 0x40010056u +#define CYDEV_UCFG_B0_P0_U0_CFG23 0x40010057u +#define CYDEV_UCFG_B0_P0_U0_CFG24 0x40010058u +#define CYDEV_UCFG_B0_P0_U0_CFG25 0x40010059u +#define CYDEV_UCFG_B0_P0_U0_CFG26 0x4001005au +#define CYDEV_UCFG_B0_P0_U0_CFG27 0x4001005bu +#define CYDEV_UCFG_B0_P0_U0_CFG28 0x4001005cu +#define CYDEV_UCFG_B0_P0_U0_CFG29 0x4001005du +#define CYDEV_UCFG_B0_P0_U0_CFG30 0x4001005eu +#define CYDEV_UCFG_B0_P0_U0_CFG31 0x4001005fu +#define CYDEV_UCFG_B0_P0_U0_DCFG0 0x40010060u +#define CYDEV_UCFG_B0_P0_U0_DCFG1 0x40010062u +#define CYDEV_UCFG_B0_P0_U0_DCFG2 0x40010064u +#define CYDEV_UCFG_B0_P0_U0_DCFG3 0x40010066u +#define CYDEV_UCFG_B0_P0_U0_DCFG4 0x40010068u +#define CYDEV_UCFG_B0_P0_U0_DCFG5 0x4001006au +#define CYDEV_UCFG_B0_P0_U0_DCFG6 0x4001006cu +#define CYDEV_UCFG_B0_P0_U0_DCFG7 0x4001006eu +#define CYDEV_UCFG_B0_P0_U1_BASE 0x40010080u +#define CYDEV_UCFG_B0_P0_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT0 0x40010080u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT1 0x40010084u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT2 0x40010088u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT3 0x4001008cu +#define CYDEV_UCFG_B0_P0_U1_PLD_IT4 0x40010090u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT5 0x40010094u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT6 0x40010098u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT7 0x4001009cu +#define CYDEV_UCFG_B0_P0_U1_PLD_IT8 0x400100a0u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT9 0x400100a4u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT10 0x400100a8u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT11 0x400100acu +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT0 0x400100b0u +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT1 0x400100b2u +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT2 0x400100b4u +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT3 0x400100b6u +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST 0x400100b8u +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB 0x400100bau +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET 0x400100bcu +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS 0x400100beu +#define CYDEV_UCFG_B0_P0_U1_CFG0 0x400100c0u +#define CYDEV_UCFG_B0_P0_U1_CFG1 0x400100c1u +#define CYDEV_UCFG_B0_P0_U1_CFG2 0x400100c2u +#define CYDEV_UCFG_B0_P0_U1_CFG3 0x400100c3u +#define CYDEV_UCFG_B0_P0_U1_CFG4 0x400100c4u +#define CYDEV_UCFG_B0_P0_U1_CFG5 0x400100c5u +#define CYDEV_UCFG_B0_P0_U1_CFG6 0x400100c6u +#define CYDEV_UCFG_B0_P0_U1_CFG7 0x400100c7u +#define CYDEV_UCFG_B0_P0_U1_CFG8 0x400100c8u +#define CYDEV_UCFG_B0_P0_U1_CFG9 0x400100c9u +#define CYDEV_UCFG_B0_P0_U1_CFG10 0x400100cau +#define CYDEV_UCFG_B0_P0_U1_CFG11 0x400100cbu +#define CYDEV_UCFG_B0_P0_U1_CFG12 0x400100ccu +#define CYDEV_UCFG_B0_P0_U1_CFG13 0x400100cdu +#define CYDEV_UCFG_B0_P0_U1_CFG14 0x400100ceu +#define CYDEV_UCFG_B0_P0_U1_CFG15 0x400100cfu +#define CYDEV_UCFG_B0_P0_U1_CFG16 0x400100d0u +#define CYDEV_UCFG_B0_P0_U1_CFG17 0x400100d1u +#define CYDEV_UCFG_B0_P0_U1_CFG18 0x400100d2u +#define CYDEV_UCFG_B0_P0_U1_CFG19 0x400100d3u +#define CYDEV_UCFG_B0_P0_U1_CFG20 0x400100d4u +#define CYDEV_UCFG_B0_P0_U1_CFG21 0x400100d5u +#define CYDEV_UCFG_B0_P0_U1_CFG22 0x400100d6u +#define CYDEV_UCFG_B0_P0_U1_CFG23 0x400100d7u +#define CYDEV_UCFG_B0_P0_U1_CFG24 0x400100d8u +#define CYDEV_UCFG_B0_P0_U1_CFG25 0x400100d9u +#define CYDEV_UCFG_B0_P0_U1_CFG26 0x400100dau +#define CYDEV_UCFG_B0_P0_U1_CFG27 0x400100dbu +#define CYDEV_UCFG_B0_P0_U1_CFG28 0x400100dcu +#define CYDEV_UCFG_B0_P0_U1_CFG29 0x400100ddu +#define CYDEV_UCFG_B0_P0_U1_CFG30 0x400100deu +#define CYDEV_UCFG_B0_P0_U1_CFG31 0x400100dfu +#define CYDEV_UCFG_B0_P0_U1_DCFG0 0x400100e0u +#define CYDEV_UCFG_B0_P0_U1_DCFG1 0x400100e2u +#define CYDEV_UCFG_B0_P0_U1_DCFG2 0x400100e4u +#define CYDEV_UCFG_B0_P0_U1_DCFG3 0x400100e6u +#define CYDEV_UCFG_B0_P0_U1_DCFG4 0x400100e8u +#define CYDEV_UCFG_B0_P0_U1_DCFG5 0x400100eau +#define CYDEV_UCFG_B0_P0_U1_DCFG6 0x400100ecu +#define CYDEV_UCFG_B0_P0_U1_DCFG7 0x400100eeu +#define CYDEV_UCFG_B0_P0_ROUTE_BASE 0x40010100u +#define CYDEV_UCFG_B0_P0_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P1_BASE 0x40010200u +#define CYDEV_UCFG_B0_P1_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P1_U0_BASE 0x40010200u +#define CYDEV_UCFG_B0_P1_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT0 0x40010200u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT1 0x40010204u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT2 0x40010208u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT3 0x4001020cu +#define CYDEV_UCFG_B0_P1_U0_PLD_IT4 0x40010210u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT5 0x40010214u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT6 0x40010218u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT7 0x4001021cu +#define CYDEV_UCFG_B0_P1_U0_PLD_IT8 0x40010220u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT9 0x40010224u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT10 0x40010228u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT11 0x4001022cu +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT0 0x40010230u +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT1 0x40010232u +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT2 0x40010234u +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT3 0x40010236u +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST 0x40010238u +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB 0x4001023au +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET 0x4001023cu +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS 0x4001023eu +#define CYDEV_UCFG_B0_P1_U0_CFG0 0x40010240u +#define CYDEV_UCFG_B0_P1_U0_CFG1 0x40010241u +#define CYDEV_UCFG_B0_P1_U0_CFG2 0x40010242u +#define CYDEV_UCFG_B0_P1_U0_CFG3 0x40010243u +#define CYDEV_UCFG_B0_P1_U0_CFG4 0x40010244u +#define CYDEV_UCFG_B0_P1_U0_CFG5 0x40010245u +#define CYDEV_UCFG_B0_P1_U0_CFG6 0x40010246u +#define CYDEV_UCFG_B0_P1_U0_CFG7 0x40010247u +#define CYDEV_UCFG_B0_P1_U0_CFG8 0x40010248u +#define CYDEV_UCFG_B0_P1_U0_CFG9 0x40010249u +#define CYDEV_UCFG_B0_P1_U0_CFG10 0x4001024au +#define CYDEV_UCFG_B0_P1_U0_CFG11 0x4001024bu +#define CYDEV_UCFG_B0_P1_U0_CFG12 0x4001024cu +#define CYDEV_UCFG_B0_P1_U0_CFG13 0x4001024du +#define CYDEV_UCFG_B0_P1_U0_CFG14 0x4001024eu +#define CYDEV_UCFG_B0_P1_U0_CFG15 0x4001024fu +#define CYDEV_UCFG_B0_P1_U0_CFG16 0x40010250u +#define CYDEV_UCFG_B0_P1_U0_CFG17 0x40010251u +#define CYDEV_UCFG_B0_P1_U0_CFG18 0x40010252u +#define CYDEV_UCFG_B0_P1_U0_CFG19 0x40010253u +#define CYDEV_UCFG_B0_P1_U0_CFG20 0x40010254u +#define CYDEV_UCFG_B0_P1_U0_CFG21 0x40010255u +#define CYDEV_UCFG_B0_P1_U0_CFG22 0x40010256u +#define CYDEV_UCFG_B0_P1_U0_CFG23 0x40010257u +#define CYDEV_UCFG_B0_P1_U0_CFG24 0x40010258u +#define CYDEV_UCFG_B0_P1_U0_CFG25 0x40010259u +#define CYDEV_UCFG_B0_P1_U0_CFG26 0x4001025au +#define CYDEV_UCFG_B0_P1_U0_CFG27 0x4001025bu +#define CYDEV_UCFG_B0_P1_U0_CFG28 0x4001025cu +#define CYDEV_UCFG_B0_P1_U0_CFG29 0x4001025du +#define CYDEV_UCFG_B0_P1_U0_CFG30 0x4001025eu +#define CYDEV_UCFG_B0_P1_U0_CFG31 0x4001025fu +#define CYDEV_UCFG_B0_P1_U0_DCFG0 0x40010260u +#define CYDEV_UCFG_B0_P1_U0_DCFG1 0x40010262u +#define CYDEV_UCFG_B0_P1_U0_DCFG2 0x40010264u +#define CYDEV_UCFG_B0_P1_U0_DCFG3 0x40010266u +#define CYDEV_UCFG_B0_P1_U0_DCFG4 0x40010268u +#define CYDEV_UCFG_B0_P1_U0_DCFG5 0x4001026au +#define CYDEV_UCFG_B0_P1_U0_DCFG6 0x4001026cu +#define CYDEV_UCFG_B0_P1_U0_DCFG7 0x4001026eu +#define CYDEV_UCFG_B0_P1_U1_BASE 0x40010280u +#define CYDEV_UCFG_B0_P1_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT0 0x40010280u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT1 0x40010284u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT2 0x40010288u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT3 0x4001028cu +#define CYDEV_UCFG_B0_P1_U1_PLD_IT4 0x40010290u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT5 0x40010294u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT6 0x40010298u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT7 0x4001029cu +#define CYDEV_UCFG_B0_P1_U1_PLD_IT8 0x400102a0u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT9 0x400102a4u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT10 0x400102a8u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT11 0x400102acu +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT0 0x400102b0u +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT1 0x400102b2u +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT2 0x400102b4u +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT3 0x400102b6u +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST 0x400102b8u +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB 0x400102bau +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET 0x400102bcu +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS 0x400102beu +#define CYDEV_UCFG_B0_P1_U1_CFG0 0x400102c0u +#define CYDEV_UCFG_B0_P1_U1_CFG1 0x400102c1u +#define CYDEV_UCFG_B0_P1_U1_CFG2 0x400102c2u +#define CYDEV_UCFG_B0_P1_U1_CFG3 0x400102c3u +#define CYDEV_UCFG_B0_P1_U1_CFG4 0x400102c4u +#define CYDEV_UCFG_B0_P1_U1_CFG5 0x400102c5u +#define CYDEV_UCFG_B0_P1_U1_CFG6 0x400102c6u +#define CYDEV_UCFG_B0_P1_U1_CFG7 0x400102c7u +#define CYDEV_UCFG_B0_P1_U1_CFG8 0x400102c8u +#define CYDEV_UCFG_B0_P1_U1_CFG9 0x400102c9u +#define CYDEV_UCFG_B0_P1_U1_CFG10 0x400102cau +#define CYDEV_UCFG_B0_P1_U1_CFG11 0x400102cbu +#define CYDEV_UCFG_B0_P1_U1_CFG12 0x400102ccu +#define CYDEV_UCFG_B0_P1_U1_CFG13 0x400102cdu +#define CYDEV_UCFG_B0_P1_U1_CFG14 0x400102ceu +#define CYDEV_UCFG_B0_P1_U1_CFG15 0x400102cfu +#define CYDEV_UCFG_B0_P1_U1_CFG16 0x400102d0u +#define CYDEV_UCFG_B0_P1_U1_CFG17 0x400102d1u +#define CYDEV_UCFG_B0_P1_U1_CFG18 0x400102d2u +#define CYDEV_UCFG_B0_P1_U1_CFG19 0x400102d3u +#define CYDEV_UCFG_B0_P1_U1_CFG20 0x400102d4u +#define CYDEV_UCFG_B0_P1_U1_CFG21 0x400102d5u +#define CYDEV_UCFG_B0_P1_U1_CFG22 0x400102d6u +#define CYDEV_UCFG_B0_P1_U1_CFG23 0x400102d7u +#define CYDEV_UCFG_B0_P1_U1_CFG24 0x400102d8u +#define CYDEV_UCFG_B0_P1_U1_CFG25 0x400102d9u +#define CYDEV_UCFG_B0_P1_U1_CFG26 0x400102dau +#define CYDEV_UCFG_B0_P1_U1_CFG27 0x400102dbu +#define CYDEV_UCFG_B0_P1_U1_CFG28 0x400102dcu +#define CYDEV_UCFG_B0_P1_U1_CFG29 0x400102ddu +#define CYDEV_UCFG_B0_P1_U1_CFG30 0x400102deu +#define CYDEV_UCFG_B0_P1_U1_CFG31 0x400102dfu +#define CYDEV_UCFG_B0_P1_U1_DCFG0 0x400102e0u +#define CYDEV_UCFG_B0_P1_U1_DCFG1 0x400102e2u +#define CYDEV_UCFG_B0_P1_U1_DCFG2 0x400102e4u +#define CYDEV_UCFG_B0_P1_U1_DCFG3 0x400102e6u +#define CYDEV_UCFG_B0_P1_U1_DCFG4 0x400102e8u +#define CYDEV_UCFG_B0_P1_U1_DCFG5 0x400102eau +#define CYDEV_UCFG_B0_P1_U1_DCFG6 0x400102ecu +#define CYDEV_UCFG_B0_P1_U1_DCFG7 0x400102eeu +#define CYDEV_UCFG_B0_P1_ROUTE_BASE 0x40010300u +#define CYDEV_UCFG_B0_P1_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P2_BASE 0x40010400u +#define CYDEV_UCFG_B0_P2_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P2_U0_BASE 0x40010400u +#define CYDEV_UCFG_B0_P2_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT0 0x40010400u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT1 0x40010404u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT2 0x40010408u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT3 0x4001040cu +#define CYDEV_UCFG_B0_P2_U0_PLD_IT4 0x40010410u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT5 0x40010414u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT6 0x40010418u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT7 0x4001041cu +#define CYDEV_UCFG_B0_P2_U0_PLD_IT8 0x40010420u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT9 0x40010424u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT10 0x40010428u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT11 0x4001042cu +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT0 0x40010430u +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT1 0x40010432u +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT2 0x40010434u +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT3 0x40010436u +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST 0x40010438u +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB 0x4001043au +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET 0x4001043cu +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS 0x4001043eu +#define CYDEV_UCFG_B0_P2_U0_CFG0 0x40010440u +#define CYDEV_UCFG_B0_P2_U0_CFG1 0x40010441u +#define CYDEV_UCFG_B0_P2_U0_CFG2 0x40010442u +#define CYDEV_UCFG_B0_P2_U0_CFG3 0x40010443u +#define CYDEV_UCFG_B0_P2_U0_CFG4 0x40010444u +#define CYDEV_UCFG_B0_P2_U0_CFG5 0x40010445u +#define CYDEV_UCFG_B0_P2_U0_CFG6 0x40010446u +#define CYDEV_UCFG_B0_P2_U0_CFG7 0x40010447u +#define CYDEV_UCFG_B0_P2_U0_CFG8 0x40010448u +#define CYDEV_UCFG_B0_P2_U0_CFG9 0x40010449u +#define CYDEV_UCFG_B0_P2_U0_CFG10 0x4001044au +#define CYDEV_UCFG_B0_P2_U0_CFG11 0x4001044bu +#define CYDEV_UCFG_B0_P2_U0_CFG12 0x4001044cu +#define CYDEV_UCFG_B0_P2_U0_CFG13 0x4001044du +#define CYDEV_UCFG_B0_P2_U0_CFG14 0x4001044eu +#define CYDEV_UCFG_B0_P2_U0_CFG15 0x4001044fu +#define CYDEV_UCFG_B0_P2_U0_CFG16 0x40010450u +#define CYDEV_UCFG_B0_P2_U0_CFG17 0x40010451u +#define CYDEV_UCFG_B0_P2_U0_CFG18 0x40010452u +#define CYDEV_UCFG_B0_P2_U0_CFG19 0x40010453u +#define CYDEV_UCFG_B0_P2_U0_CFG20 0x40010454u +#define CYDEV_UCFG_B0_P2_U0_CFG21 0x40010455u +#define CYDEV_UCFG_B0_P2_U0_CFG22 0x40010456u +#define CYDEV_UCFG_B0_P2_U0_CFG23 0x40010457u +#define CYDEV_UCFG_B0_P2_U0_CFG24 0x40010458u +#define CYDEV_UCFG_B0_P2_U0_CFG25 0x40010459u +#define CYDEV_UCFG_B0_P2_U0_CFG26 0x4001045au +#define CYDEV_UCFG_B0_P2_U0_CFG27 0x4001045bu +#define CYDEV_UCFG_B0_P2_U0_CFG28 0x4001045cu +#define CYDEV_UCFG_B0_P2_U0_CFG29 0x4001045du +#define CYDEV_UCFG_B0_P2_U0_CFG30 0x4001045eu +#define CYDEV_UCFG_B0_P2_U0_CFG31 0x4001045fu +#define CYDEV_UCFG_B0_P2_U0_DCFG0 0x40010460u +#define CYDEV_UCFG_B0_P2_U0_DCFG1 0x40010462u +#define CYDEV_UCFG_B0_P2_U0_DCFG2 0x40010464u +#define CYDEV_UCFG_B0_P2_U0_DCFG3 0x40010466u +#define CYDEV_UCFG_B0_P2_U0_DCFG4 0x40010468u +#define CYDEV_UCFG_B0_P2_U0_DCFG5 0x4001046au +#define CYDEV_UCFG_B0_P2_U0_DCFG6 0x4001046cu +#define CYDEV_UCFG_B0_P2_U0_DCFG7 0x4001046eu +#define CYDEV_UCFG_B0_P2_U1_BASE 0x40010480u +#define CYDEV_UCFG_B0_P2_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT0 0x40010480u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT1 0x40010484u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT2 0x40010488u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT3 0x4001048cu +#define CYDEV_UCFG_B0_P2_U1_PLD_IT4 0x40010490u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT5 0x40010494u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT6 0x40010498u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT7 0x4001049cu +#define CYDEV_UCFG_B0_P2_U1_PLD_IT8 0x400104a0u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT9 0x400104a4u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT10 0x400104a8u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT11 0x400104acu +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT0 0x400104b0u +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT1 0x400104b2u +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT2 0x400104b4u +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT3 0x400104b6u +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST 0x400104b8u +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB 0x400104bau +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET 0x400104bcu +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS 0x400104beu +#define CYDEV_UCFG_B0_P2_U1_CFG0 0x400104c0u +#define CYDEV_UCFG_B0_P2_U1_CFG1 0x400104c1u +#define CYDEV_UCFG_B0_P2_U1_CFG2 0x400104c2u +#define CYDEV_UCFG_B0_P2_U1_CFG3 0x400104c3u +#define CYDEV_UCFG_B0_P2_U1_CFG4 0x400104c4u +#define CYDEV_UCFG_B0_P2_U1_CFG5 0x400104c5u +#define CYDEV_UCFG_B0_P2_U1_CFG6 0x400104c6u +#define CYDEV_UCFG_B0_P2_U1_CFG7 0x400104c7u +#define CYDEV_UCFG_B0_P2_U1_CFG8 0x400104c8u +#define CYDEV_UCFG_B0_P2_U1_CFG9 0x400104c9u +#define CYDEV_UCFG_B0_P2_U1_CFG10 0x400104cau +#define CYDEV_UCFG_B0_P2_U1_CFG11 0x400104cbu +#define CYDEV_UCFG_B0_P2_U1_CFG12 0x400104ccu +#define CYDEV_UCFG_B0_P2_U1_CFG13 0x400104cdu +#define CYDEV_UCFG_B0_P2_U1_CFG14 0x400104ceu +#define CYDEV_UCFG_B0_P2_U1_CFG15 0x400104cfu +#define CYDEV_UCFG_B0_P2_U1_CFG16 0x400104d0u +#define CYDEV_UCFG_B0_P2_U1_CFG17 0x400104d1u +#define CYDEV_UCFG_B0_P2_U1_CFG18 0x400104d2u +#define CYDEV_UCFG_B0_P2_U1_CFG19 0x400104d3u +#define CYDEV_UCFG_B0_P2_U1_CFG20 0x400104d4u +#define CYDEV_UCFG_B0_P2_U1_CFG21 0x400104d5u +#define CYDEV_UCFG_B0_P2_U1_CFG22 0x400104d6u +#define CYDEV_UCFG_B0_P2_U1_CFG23 0x400104d7u +#define CYDEV_UCFG_B0_P2_U1_CFG24 0x400104d8u +#define CYDEV_UCFG_B0_P2_U1_CFG25 0x400104d9u +#define CYDEV_UCFG_B0_P2_U1_CFG26 0x400104dau +#define CYDEV_UCFG_B0_P2_U1_CFG27 0x400104dbu +#define CYDEV_UCFG_B0_P2_U1_CFG28 0x400104dcu +#define CYDEV_UCFG_B0_P2_U1_CFG29 0x400104ddu +#define CYDEV_UCFG_B0_P2_U1_CFG30 0x400104deu +#define CYDEV_UCFG_B0_P2_U1_CFG31 0x400104dfu +#define CYDEV_UCFG_B0_P2_U1_DCFG0 0x400104e0u +#define CYDEV_UCFG_B0_P2_U1_DCFG1 0x400104e2u +#define CYDEV_UCFG_B0_P2_U1_DCFG2 0x400104e4u +#define CYDEV_UCFG_B0_P2_U1_DCFG3 0x400104e6u +#define CYDEV_UCFG_B0_P2_U1_DCFG4 0x400104e8u +#define CYDEV_UCFG_B0_P2_U1_DCFG5 0x400104eau +#define CYDEV_UCFG_B0_P2_U1_DCFG6 0x400104ecu +#define CYDEV_UCFG_B0_P2_U1_DCFG7 0x400104eeu +#define CYDEV_UCFG_B0_P2_ROUTE_BASE 0x40010500u +#define CYDEV_UCFG_B0_P2_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P3_BASE 0x40010600u +#define CYDEV_UCFG_B0_P3_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P3_U0_BASE 0x40010600u +#define CYDEV_UCFG_B0_P3_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT0 0x40010600u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT1 0x40010604u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT2 0x40010608u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT3 0x4001060cu +#define CYDEV_UCFG_B0_P3_U0_PLD_IT4 0x40010610u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT5 0x40010614u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT6 0x40010618u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT7 0x4001061cu +#define CYDEV_UCFG_B0_P3_U0_PLD_IT8 0x40010620u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT9 0x40010624u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT10 0x40010628u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT11 0x4001062cu +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT0 0x40010630u +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT1 0x40010632u +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT2 0x40010634u +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT3 0x40010636u +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST 0x40010638u +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB 0x4001063au +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET 0x4001063cu +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS 0x4001063eu +#define CYDEV_UCFG_B0_P3_U0_CFG0 0x40010640u +#define CYDEV_UCFG_B0_P3_U0_CFG1 0x40010641u +#define CYDEV_UCFG_B0_P3_U0_CFG2 0x40010642u +#define CYDEV_UCFG_B0_P3_U0_CFG3 0x40010643u +#define CYDEV_UCFG_B0_P3_U0_CFG4 0x40010644u +#define CYDEV_UCFG_B0_P3_U0_CFG5 0x40010645u +#define CYDEV_UCFG_B0_P3_U0_CFG6 0x40010646u +#define CYDEV_UCFG_B0_P3_U0_CFG7 0x40010647u +#define CYDEV_UCFG_B0_P3_U0_CFG8 0x40010648u +#define CYDEV_UCFG_B0_P3_U0_CFG9 0x40010649u +#define CYDEV_UCFG_B0_P3_U0_CFG10 0x4001064au +#define CYDEV_UCFG_B0_P3_U0_CFG11 0x4001064bu +#define CYDEV_UCFG_B0_P3_U0_CFG12 0x4001064cu +#define CYDEV_UCFG_B0_P3_U0_CFG13 0x4001064du +#define CYDEV_UCFG_B0_P3_U0_CFG14 0x4001064eu +#define CYDEV_UCFG_B0_P3_U0_CFG15 0x4001064fu +#define CYDEV_UCFG_B0_P3_U0_CFG16 0x40010650u +#define CYDEV_UCFG_B0_P3_U0_CFG17 0x40010651u +#define CYDEV_UCFG_B0_P3_U0_CFG18 0x40010652u +#define CYDEV_UCFG_B0_P3_U0_CFG19 0x40010653u +#define CYDEV_UCFG_B0_P3_U0_CFG20 0x40010654u +#define CYDEV_UCFG_B0_P3_U0_CFG21 0x40010655u +#define CYDEV_UCFG_B0_P3_U0_CFG22 0x40010656u +#define CYDEV_UCFG_B0_P3_U0_CFG23 0x40010657u +#define CYDEV_UCFG_B0_P3_U0_CFG24 0x40010658u +#define CYDEV_UCFG_B0_P3_U0_CFG25 0x40010659u +#define CYDEV_UCFG_B0_P3_U0_CFG26 0x4001065au +#define CYDEV_UCFG_B0_P3_U0_CFG27 0x4001065bu +#define CYDEV_UCFG_B0_P3_U0_CFG28 0x4001065cu +#define CYDEV_UCFG_B0_P3_U0_CFG29 0x4001065du +#define CYDEV_UCFG_B0_P3_U0_CFG30 0x4001065eu +#define CYDEV_UCFG_B0_P3_U0_CFG31 0x4001065fu +#define CYDEV_UCFG_B0_P3_U0_DCFG0 0x40010660u +#define CYDEV_UCFG_B0_P3_U0_DCFG1 0x40010662u +#define CYDEV_UCFG_B0_P3_U0_DCFG2 0x40010664u +#define CYDEV_UCFG_B0_P3_U0_DCFG3 0x40010666u +#define CYDEV_UCFG_B0_P3_U0_DCFG4 0x40010668u +#define CYDEV_UCFG_B0_P3_U0_DCFG5 0x4001066au +#define CYDEV_UCFG_B0_P3_U0_DCFG6 0x4001066cu +#define CYDEV_UCFG_B0_P3_U0_DCFG7 0x4001066eu +#define CYDEV_UCFG_B0_P3_U1_BASE 0x40010680u +#define CYDEV_UCFG_B0_P3_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT0 0x40010680u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT1 0x40010684u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT2 0x40010688u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT3 0x4001068cu +#define CYDEV_UCFG_B0_P3_U1_PLD_IT4 0x40010690u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT5 0x40010694u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT6 0x40010698u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT7 0x4001069cu +#define CYDEV_UCFG_B0_P3_U1_PLD_IT8 0x400106a0u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT9 0x400106a4u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT10 0x400106a8u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT11 0x400106acu +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT0 0x400106b0u +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT1 0x400106b2u +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT2 0x400106b4u +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT3 0x400106b6u +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST 0x400106b8u +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB 0x400106bau +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET 0x400106bcu +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS 0x400106beu +#define CYDEV_UCFG_B0_P3_U1_CFG0 0x400106c0u +#define CYDEV_UCFG_B0_P3_U1_CFG1 0x400106c1u +#define CYDEV_UCFG_B0_P3_U1_CFG2 0x400106c2u +#define CYDEV_UCFG_B0_P3_U1_CFG3 0x400106c3u +#define CYDEV_UCFG_B0_P3_U1_CFG4 0x400106c4u +#define CYDEV_UCFG_B0_P3_U1_CFG5 0x400106c5u +#define CYDEV_UCFG_B0_P3_U1_CFG6 0x400106c6u +#define CYDEV_UCFG_B0_P3_U1_CFG7 0x400106c7u +#define CYDEV_UCFG_B0_P3_U1_CFG8 0x400106c8u +#define CYDEV_UCFG_B0_P3_U1_CFG9 0x400106c9u +#define CYDEV_UCFG_B0_P3_U1_CFG10 0x400106cau +#define CYDEV_UCFG_B0_P3_U1_CFG11 0x400106cbu +#define CYDEV_UCFG_B0_P3_U1_CFG12 0x400106ccu +#define CYDEV_UCFG_B0_P3_U1_CFG13 0x400106cdu +#define CYDEV_UCFG_B0_P3_U1_CFG14 0x400106ceu +#define CYDEV_UCFG_B0_P3_U1_CFG15 0x400106cfu +#define CYDEV_UCFG_B0_P3_U1_CFG16 0x400106d0u +#define CYDEV_UCFG_B0_P3_U1_CFG17 0x400106d1u +#define CYDEV_UCFG_B0_P3_U1_CFG18 0x400106d2u +#define CYDEV_UCFG_B0_P3_U1_CFG19 0x400106d3u +#define CYDEV_UCFG_B0_P3_U1_CFG20 0x400106d4u +#define CYDEV_UCFG_B0_P3_U1_CFG21 0x400106d5u +#define CYDEV_UCFG_B0_P3_U1_CFG22 0x400106d6u +#define CYDEV_UCFG_B0_P3_U1_CFG23 0x400106d7u +#define CYDEV_UCFG_B0_P3_U1_CFG24 0x400106d8u +#define CYDEV_UCFG_B0_P3_U1_CFG25 0x400106d9u +#define CYDEV_UCFG_B0_P3_U1_CFG26 0x400106dau +#define CYDEV_UCFG_B0_P3_U1_CFG27 0x400106dbu +#define CYDEV_UCFG_B0_P3_U1_CFG28 0x400106dcu +#define CYDEV_UCFG_B0_P3_U1_CFG29 0x400106ddu +#define CYDEV_UCFG_B0_P3_U1_CFG30 0x400106deu +#define CYDEV_UCFG_B0_P3_U1_CFG31 0x400106dfu +#define CYDEV_UCFG_B0_P3_U1_DCFG0 0x400106e0u +#define CYDEV_UCFG_B0_P3_U1_DCFG1 0x400106e2u +#define CYDEV_UCFG_B0_P3_U1_DCFG2 0x400106e4u +#define CYDEV_UCFG_B0_P3_U1_DCFG3 0x400106e6u +#define CYDEV_UCFG_B0_P3_U1_DCFG4 0x400106e8u +#define CYDEV_UCFG_B0_P3_U1_DCFG5 0x400106eau +#define CYDEV_UCFG_B0_P3_U1_DCFG6 0x400106ecu +#define CYDEV_UCFG_B0_P3_U1_DCFG7 0x400106eeu +#define CYDEV_UCFG_B0_P3_ROUTE_BASE 0x40010700u +#define CYDEV_UCFG_B0_P3_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P4_BASE 0x40010800u +#define CYDEV_UCFG_B0_P4_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P4_U0_BASE 0x40010800u +#define CYDEV_UCFG_B0_P4_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT0 0x40010800u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT1 0x40010804u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT2 0x40010808u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT3 0x4001080cu +#define CYDEV_UCFG_B0_P4_U0_PLD_IT4 0x40010810u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT5 0x40010814u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT6 0x40010818u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT7 0x4001081cu +#define CYDEV_UCFG_B0_P4_U0_PLD_IT8 0x40010820u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT9 0x40010824u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT10 0x40010828u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT11 0x4001082cu +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT0 0x40010830u +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT1 0x40010832u +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT2 0x40010834u +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT3 0x40010836u +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST 0x40010838u +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB 0x4001083au +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET 0x4001083cu +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS 0x4001083eu +#define CYDEV_UCFG_B0_P4_U0_CFG0 0x40010840u +#define CYDEV_UCFG_B0_P4_U0_CFG1 0x40010841u +#define CYDEV_UCFG_B0_P4_U0_CFG2 0x40010842u +#define CYDEV_UCFG_B0_P4_U0_CFG3 0x40010843u +#define CYDEV_UCFG_B0_P4_U0_CFG4 0x40010844u +#define CYDEV_UCFG_B0_P4_U0_CFG5 0x40010845u +#define CYDEV_UCFG_B0_P4_U0_CFG6 0x40010846u +#define CYDEV_UCFG_B0_P4_U0_CFG7 0x40010847u +#define CYDEV_UCFG_B0_P4_U0_CFG8 0x40010848u +#define CYDEV_UCFG_B0_P4_U0_CFG9 0x40010849u +#define CYDEV_UCFG_B0_P4_U0_CFG10 0x4001084au +#define CYDEV_UCFG_B0_P4_U0_CFG11 0x4001084bu +#define CYDEV_UCFG_B0_P4_U0_CFG12 0x4001084cu +#define CYDEV_UCFG_B0_P4_U0_CFG13 0x4001084du +#define CYDEV_UCFG_B0_P4_U0_CFG14 0x4001084eu +#define CYDEV_UCFG_B0_P4_U0_CFG15 0x4001084fu +#define CYDEV_UCFG_B0_P4_U0_CFG16 0x40010850u +#define CYDEV_UCFG_B0_P4_U0_CFG17 0x40010851u +#define CYDEV_UCFG_B0_P4_U0_CFG18 0x40010852u +#define CYDEV_UCFG_B0_P4_U0_CFG19 0x40010853u +#define CYDEV_UCFG_B0_P4_U0_CFG20 0x40010854u +#define CYDEV_UCFG_B0_P4_U0_CFG21 0x40010855u +#define CYDEV_UCFG_B0_P4_U0_CFG22 0x40010856u +#define CYDEV_UCFG_B0_P4_U0_CFG23 0x40010857u +#define CYDEV_UCFG_B0_P4_U0_CFG24 0x40010858u +#define CYDEV_UCFG_B0_P4_U0_CFG25 0x40010859u +#define CYDEV_UCFG_B0_P4_U0_CFG26 0x4001085au +#define CYDEV_UCFG_B0_P4_U0_CFG27 0x4001085bu +#define CYDEV_UCFG_B0_P4_U0_CFG28 0x4001085cu +#define CYDEV_UCFG_B0_P4_U0_CFG29 0x4001085du +#define CYDEV_UCFG_B0_P4_U0_CFG30 0x4001085eu +#define CYDEV_UCFG_B0_P4_U0_CFG31 0x4001085fu +#define CYDEV_UCFG_B0_P4_U0_DCFG0 0x40010860u +#define CYDEV_UCFG_B0_P4_U0_DCFG1 0x40010862u +#define CYDEV_UCFG_B0_P4_U0_DCFG2 0x40010864u +#define CYDEV_UCFG_B0_P4_U0_DCFG3 0x40010866u +#define CYDEV_UCFG_B0_P4_U0_DCFG4 0x40010868u +#define CYDEV_UCFG_B0_P4_U0_DCFG5 0x4001086au +#define CYDEV_UCFG_B0_P4_U0_DCFG6 0x4001086cu +#define CYDEV_UCFG_B0_P4_U0_DCFG7 0x4001086eu +#define CYDEV_UCFG_B0_P4_U1_BASE 0x40010880u +#define CYDEV_UCFG_B0_P4_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT0 0x40010880u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT1 0x40010884u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT2 0x40010888u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT3 0x4001088cu +#define CYDEV_UCFG_B0_P4_U1_PLD_IT4 0x40010890u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT5 0x40010894u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT6 0x40010898u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT7 0x4001089cu +#define CYDEV_UCFG_B0_P4_U1_PLD_IT8 0x400108a0u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT9 0x400108a4u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT10 0x400108a8u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT11 0x400108acu +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT0 0x400108b0u +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT1 0x400108b2u +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT2 0x400108b4u +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT3 0x400108b6u +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST 0x400108b8u +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB 0x400108bau +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET 0x400108bcu +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS 0x400108beu +#define CYDEV_UCFG_B0_P4_U1_CFG0 0x400108c0u +#define CYDEV_UCFG_B0_P4_U1_CFG1 0x400108c1u +#define CYDEV_UCFG_B0_P4_U1_CFG2 0x400108c2u +#define CYDEV_UCFG_B0_P4_U1_CFG3 0x400108c3u +#define CYDEV_UCFG_B0_P4_U1_CFG4 0x400108c4u +#define CYDEV_UCFG_B0_P4_U1_CFG5 0x400108c5u +#define CYDEV_UCFG_B0_P4_U1_CFG6 0x400108c6u +#define CYDEV_UCFG_B0_P4_U1_CFG7 0x400108c7u +#define CYDEV_UCFG_B0_P4_U1_CFG8 0x400108c8u +#define CYDEV_UCFG_B0_P4_U1_CFG9 0x400108c9u +#define CYDEV_UCFG_B0_P4_U1_CFG10 0x400108cau +#define CYDEV_UCFG_B0_P4_U1_CFG11 0x400108cbu +#define CYDEV_UCFG_B0_P4_U1_CFG12 0x400108ccu +#define CYDEV_UCFG_B0_P4_U1_CFG13 0x400108cdu +#define CYDEV_UCFG_B0_P4_U1_CFG14 0x400108ceu +#define CYDEV_UCFG_B0_P4_U1_CFG15 0x400108cfu +#define CYDEV_UCFG_B0_P4_U1_CFG16 0x400108d0u +#define CYDEV_UCFG_B0_P4_U1_CFG17 0x400108d1u +#define CYDEV_UCFG_B0_P4_U1_CFG18 0x400108d2u +#define CYDEV_UCFG_B0_P4_U1_CFG19 0x400108d3u +#define CYDEV_UCFG_B0_P4_U1_CFG20 0x400108d4u +#define CYDEV_UCFG_B0_P4_U1_CFG21 0x400108d5u +#define CYDEV_UCFG_B0_P4_U1_CFG22 0x400108d6u +#define CYDEV_UCFG_B0_P4_U1_CFG23 0x400108d7u +#define CYDEV_UCFG_B0_P4_U1_CFG24 0x400108d8u +#define CYDEV_UCFG_B0_P4_U1_CFG25 0x400108d9u +#define CYDEV_UCFG_B0_P4_U1_CFG26 0x400108dau +#define CYDEV_UCFG_B0_P4_U1_CFG27 0x400108dbu +#define CYDEV_UCFG_B0_P4_U1_CFG28 0x400108dcu +#define CYDEV_UCFG_B0_P4_U1_CFG29 0x400108ddu +#define CYDEV_UCFG_B0_P4_U1_CFG30 0x400108deu +#define CYDEV_UCFG_B0_P4_U1_CFG31 0x400108dfu +#define CYDEV_UCFG_B0_P4_U1_DCFG0 0x400108e0u +#define CYDEV_UCFG_B0_P4_U1_DCFG1 0x400108e2u +#define CYDEV_UCFG_B0_P4_U1_DCFG2 0x400108e4u +#define CYDEV_UCFG_B0_P4_U1_DCFG3 0x400108e6u +#define CYDEV_UCFG_B0_P4_U1_DCFG4 0x400108e8u +#define CYDEV_UCFG_B0_P4_U1_DCFG5 0x400108eau +#define CYDEV_UCFG_B0_P4_U1_DCFG6 0x400108ecu +#define CYDEV_UCFG_B0_P4_U1_DCFG7 0x400108eeu +#define CYDEV_UCFG_B0_P4_ROUTE_BASE 0x40010900u +#define CYDEV_UCFG_B0_P4_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P5_BASE 0x40010a00u +#define CYDEV_UCFG_B0_P5_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P5_U0_BASE 0x40010a00u +#define CYDEV_UCFG_B0_P5_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT0 0x40010a00u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT1 0x40010a04u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT2 0x40010a08u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT3 0x40010a0cu +#define CYDEV_UCFG_B0_P5_U0_PLD_IT4 0x40010a10u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT5 0x40010a14u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT6 0x40010a18u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT7 0x40010a1cu +#define CYDEV_UCFG_B0_P5_U0_PLD_IT8 0x40010a20u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT9 0x40010a24u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT10 0x40010a28u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT11 0x40010a2cu +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT0 0x40010a30u +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT1 0x40010a32u +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT2 0x40010a34u +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT3 0x40010a36u +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST 0x40010a38u +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB 0x40010a3au +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET 0x40010a3cu +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS 0x40010a3eu +#define CYDEV_UCFG_B0_P5_U0_CFG0 0x40010a40u +#define CYDEV_UCFG_B0_P5_U0_CFG1 0x40010a41u +#define CYDEV_UCFG_B0_P5_U0_CFG2 0x40010a42u +#define CYDEV_UCFG_B0_P5_U0_CFG3 0x40010a43u +#define CYDEV_UCFG_B0_P5_U0_CFG4 0x40010a44u +#define CYDEV_UCFG_B0_P5_U0_CFG5 0x40010a45u +#define CYDEV_UCFG_B0_P5_U0_CFG6 0x40010a46u +#define CYDEV_UCFG_B0_P5_U0_CFG7 0x40010a47u +#define CYDEV_UCFG_B0_P5_U0_CFG8 0x40010a48u +#define CYDEV_UCFG_B0_P5_U0_CFG9 0x40010a49u +#define CYDEV_UCFG_B0_P5_U0_CFG10 0x40010a4au +#define CYDEV_UCFG_B0_P5_U0_CFG11 0x40010a4bu +#define CYDEV_UCFG_B0_P5_U0_CFG12 0x40010a4cu +#define CYDEV_UCFG_B0_P5_U0_CFG13 0x40010a4du +#define CYDEV_UCFG_B0_P5_U0_CFG14 0x40010a4eu +#define CYDEV_UCFG_B0_P5_U0_CFG15 0x40010a4fu +#define CYDEV_UCFG_B0_P5_U0_CFG16 0x40010a50u +#define CYDEV_UCFG_B0_P5_U0_CFG17 0x40010a51u +#define CYDEV_UCFG_B0_P5_U0_CFG18 0x40010a52u +#define CYDEV_UCFG_B0_P5_U0_CFG19 0x40010a53u +#define CYDEV_UCFG_B0_P5_U0_CFG20 0x40010a54u +#define CYDEV_UCFG_B0_P5_U0_CFG21 0x40010a55u +#define CYDEV_UCFG_B0_P5_U0_CFG22 0x40010a56u +#define CYDEV_UCFG_B0_P5_U0_CFG23 0x40010a57u +#define CYDEV_UCFG_B0_P5_U0_CFG24 0x40010a58u +#define CYDEV_UCFG_B0_P5_U0_CFG25 0x40010a59u +#define CYDEV_UCFG_B0_P5_U0_CFG26 0x40010a5au +#define CYDEV_UCFG_B0_P5_U0_CFG27 0x40010a5bu +#define CYDEV_UCFG_B0_P5_U0_CFG28 0x40010a5cu +#define CYDEV_UCFG_B0_P5_U0_CFG29 0x40010a5du +#define CYDEV_UCFG_B0_P5_U0_CFG30 0x40010a5eu +#define CYDEV_UCFG_B0_P5_U0_CFG31 0x40010a5fu +#define CYDEV_UCFG_B0_P5_U0_DCFG0 0x40010a60u +#define CYDEV_UCFG_B0_P5_U0_DCFG1 0x40010a62u +#define CYDEV_UCFG_B0_P5_U0_DCFG2 0x40010a64u +#define CYDEV_UCFG_B0_P5_U0_DCFG3 0x40010a66u +#define CYDEV_UCFG_B0_P5_U0_DCFG4 0x40010a68u +#define CYDEV_UCFG_B0_P5_U0_DCFG5 0x40010a6au +#define CYDEV_UCFG_B0_P5_U0_DCFG6 0x40010a6cu +#define CYDEV_UCFG_B0_P5_U0_DCFG7 0x40010a6eu +#define CYDEV_UCFG_B0_P5_U1_BASE 0x40010a80u +#define CYDEV_UCFG_B0_P5_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT0 0x40010a80u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT1 0x40010a84u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT2 0x40010a88u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT3 0x40010a8cu +#define CYDEV_UCFG_B0_P5_U1_PLD_IT4 0x40010a90u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT5 0x40010a94u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT6 0x40010a98u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT7 0x40010a9cu +#define CYDEV_UCFG_B0_P5_U1_PLD_IT8 0x40010aa0u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT9 0x40010aa4u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT10 0x40010aa8u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT11 0x40010aacu +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT0 0x40010ab0u +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT1 0x40010ab2u +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT2 0x40010ab4u +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT3 0x40010ab6u +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST 0x40010ab8u +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB 0x40010abau +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET 0x40010abcu +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS 0x40010abeu +#define CYDEV_UCFG_B0_P5_U1_CFG0 0x40010ac0u +#define CYDEV_UCFG_B0_P5_U1_CFG1 0x40010ac1u +#define CYDEV_UCFG_B0_P5_U1_CFG2 0x40010ac2u +#define CYDEV_UCFG_B0_P5_U1_CFG3 0x40010ac3u +#define CYDEV_UCFG_B0_P5_U1_CFG4 0x40010ac4u +#define CYDEV_UCFG_B0_P5_U1_CFG5 0x40010ac5u +#define CYDEV_UCFG_B0_P5_U1_CFG6 0x40010ac6u +#define CYDEV_UCFG_B0_P5_U1_CFG7 0x40010ac7u +#define CYDEV_UCFG_B0_P5_U1_CFG8 0x40010ac8u +#define CYDEV_UCFG_B0_P5_U1_CFG9 0x40010ac9u +#define CYDEV_UCFG_B0_P5_U1_CFG10 0x40010acau +#define CYDEV_UCFG_B0_P5_U1_CFG11 0x40010acbu +#define CYDEV_UCFG_B0_P5_U1_CFG12 0x40010accu +#define CYDEV_UCFG_B0_P5_U1_CFG13 0x40010acdu +#define CYDEV_UCFG_B0_P5_U1_CFG14 0x40010aceu +#define CYDEV_UCFG_B0_P5_U1_CFG15 0x40010acfu +#define CYDEV_UCFG_B0_P5_U1_CFG16 0x40010ad0u +#define CYDEV_UCFG_B0_P5_U1_CFG17 0x40010ad1u +#define CYDEV_UCFG_B0_P5_U1_CFG18 0x40010ad2u +#define CYDEV_UCFG_B0_P5_U1_CFG19 0x40010ad3u +#define CYDEV_UCFG_B0_P5_U1_CFG20 0x40010ad4u +#define CYDEV_UCFG_B0_P5_U1_CFG21 0x40010ad5u +#define CYDEV_UCFG_B0_P5_U1_CFG22 0x40010ad6u +#define CYDEV_UCFG_B0_P5_U1_CFG23 0x40010ad7u +#define CYDEV_UCFG_B0_P5_U1_CFG24 0x40010ad8u +#define CYDEV_UCFG_B0_P5_U1_CFG25 0x40010ad9u +#define CYDEV_UCFG_B0_P5_U1_CFG26 0x40010adau +#define CYDEV_UCFG_B0_P5_U1_CFG27 0x40010adbu +#define CYDEV_UCFG_B0_P5_U1_CFG28 0x40010adcu +#define CYDEV_UCFG_B0_P5_U1_CFG29 0x40010addu +#define CYDEV_UCFG_B0_P5_U1_CFG30 0x40010adeu +#define CYDEV_UCFG_B0_P5_U1_CFG31 0x40010adfu +#define CYDEV_UCFG_B0_P5_U1_DCFG0 0x40010ae0u +#define CYDEV_UCFG_B0_P5_U1_DCFG1 0x40010ae2u +#define CYDEV_UCFG_B0_P5_U1_DCFG2 0x40010ae4u +#define CYDEV_UCFG_B0_P5_U1_DCFG3 0x40010ae6u +#define CYDEV_UCFG_B0_P5_U1_DCFG4 0x40010ae8u +#define CYDEV_UCFG_B0_P5_U1_DCFG5 0x40010aeau +#define CYDEV_UCFG_B0_P5_U1_DCFG6 0x40010aecu +#define CYDEV_UCFG_B0_P5_U1_DCFG7 0x40010aeeu +#define CYDEV_UCFG_B0_P5_ROUTE_BASE 0x40010b00u +#define CYDEV_UCFG_B0_P5_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P6_BASE 0x40010c00u +#define CYDEV_UCFG_B0_P6_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P6_U0_BASE 0x40010c00u +#define CYDEV_UCFG_B0_P6_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT0 0x40010c00u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT1 0x40010c04u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT2 0x40010c08u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT3 0x40010c0cu +#define CYDEV_UCFG_B0_P6_U0_PLD_IT4 0x40010c10u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT5 0x40010c14u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT6 0x40010c18u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT7 0x40010c1cu +#define CYDEV_UCFG_B0_P6_U0_PLD_IT8 0x40010c20u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT9 0x40010c24u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT10 0x40010c28u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT11 0x40010c2cu +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT0 0x40010c30u +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT1 0x40010c32u +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT2 0x40010c34u +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT3 0x40010c36u +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST 0x40010c38u +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB 0x40010c3au +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET 0x40010c3cu +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS 0x40010c3eu +#define CYDEV_UCFG_B0_P6_U0_CFG0 0x40010c40u +#define CYDEV_UCFG_B0_P6_U0_CFG1 0x40010c41u +#define CYDEV_UCFG_B0_P6_U0_CFG2 0x40010c42u +#define CYDEV_UCFG_B0_P6_U0_CFG3 0x40010c43u +#define CYDEV_UCFG_B0_P6_U0_CFG4 0x40010c44u +#define CYDEV_UCFG_B0_P6_U0_CFG5 0x40010c45u +#define CYDEV_UCFG_B0_P6_U0_CFG6 0x40010c46u +#define CYDEV_UCFG_B0_P6_U0_CFG7 0x40010c47u +#define CYDEV_UCFG_B0_P6_U0_CFG8 0x40010c48u +#define CYDEV_UCFG_B0_P6_U0_CFG9 0x40010c49u +#define CYDEV_UCFG_B0_P6_U0_CFG10 0x40010c4au +#define CYDEV_UCFG_B0_P6_U0_CFG11 0x40010c4bu +#define CYDEV_UCFG_B0_P6_U0_CFG12 0x40010c4cu +#define CYDEV_UCFG_B0_P6_U0_CFG13 0x40010c4du +#define CYDEV_UCFG_B0_P6_U0_CFG14 0x40010c4eu +#define CYDEV_UCFG_B0_P6_U0_CFG15 0x40010c4fu +#define CYDEV_UCFG_B0_P6_U0_CFG16 0x40010c50u +#define CYDEV_UCFG_B0_P6_U0_CFG17 0x40010c51u +#define CYDEV_UCFG_B0_P6_U0_CFG18 0x40010c52u +#define CYDEV_UCFG_B0_P6_U0_CFG19 0x40010c53u +#define CYDEV_UCFG_B0_P6_U0_CFG20 0x40010c54u +#define CYDEV_UCFG_B0_P6_U0_CFG21 0x40010c55u +#define CYDEV_UCFG_B0_P6_U0_CFG22 0x40010c56u +#define CYDEV_UCFG_B0_P6_U0_CFG23 0x40010c57u +#define CYDEV_UCFG_B0_P6_U0_CFG24 0x40010c58u +#define CYDEV_UCFG_B0_P6_U0_CFG25 0x40010c59u +#define CYDEV_UCFG_B0_P6_U0_CFG26 0x40010c5au +#define CYDEV_UCFG_B0_P6_U0_CFG27 0x40010c5bu +#define CYDEV_UCFG_B0_P6_U0_CFG28 0x40010c5cu +#define CYDEV_UCFG_B0_P6_U0_CFG29 0x40010c5du +#define CYDEV_UCFG_B0_P6_U0_CFG30 0x40010c5eu +#define CYDEV_UCFG_B0_P6_U0_CFG31 0x40010c5fu +#define CYDEV_UCFG_B0_P6_U0_DCFG0 0x40010c60u +#define CYDEV_UCFG_B0_P6_U0_DCFG1 0x40010c62u +#define CYDEV_UCFG_B0_P6_U0_DCFG2 0x40010c64u +#define CYDEV_UCFG_B0_P6_U0_DCFG3 0x40010c66u +#define CYDEV_UCFG_B0_P6_U0_DCFG4 0x40010c68u +#define CYDEV_UCFG_B0_P6_U0_DCFG5 0x40010c6au +#define CYDEV_UCFG_B0_P6_U0_DCFG6 0x40010c6cu +#define CYDEV_UCFG_B0_P6_U0_DCFG7 0x40010c6eu +#define CYDEV_UCFG_B0_P6_U1_BASE 0x40010c80u +#define CYDEV_UCFG_B0_P6_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT0 0x40010c80u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT1 0x40010c84u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT2 0x40010c88u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT3 0x40010c8cu +#define CYDEV_UCFG_B0_P6_U1_PLD_IT4 0x40010c90u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT5 0x40010c94u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT6 0x40010c98u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT7 0x40010c9cu +#define CYDEV_UCFG_B0_P6_U1_PLD_IT8 0x40010ca0u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT9 0x40010ca4u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT10 0x40010ca8u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT11 0x40010cacu +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT0 0x40010cb0u +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT1 0x40010cb2u +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT2 0x40010cb4u +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT3 0x40010cb6u +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST 0x40010cb8u +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB 0x40010cbau +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET 0x40010cbcu +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS 0x40010cbeu +#define CYDEV_UCFG_B0_P6_U1_CFG0 0x40010cc0u +#define CYDEV_UCFG_B0_P6_U1_CFG1 0x40010cc1u +#define CYDEV_UCFG_B0_P6_U1_CFG2 0x40010cc2u +#define CYDEV_UCFG_B0_P6_U1_CFG3 0x40010cc3u +#define CYDEV_UCFG_B0_P6_U1_CFG4 0x40010cc4u +#define CYDEV_UCFG_B0_P6_U1_CFG5 0x40010cc5u +#define CYDEV_UCFG_B0_P6_U1_CFG6 0x40010cc6u +#define CYDEV_UCFG_B0_P6_U1_CFG7 0x40010cc7u +#define CYDEV_UCFG_B0_P6_U1_CFG8 0x40010cc8u +#define CYDEV_UCFG_B0_P6_U1_CFG9 0x40010cc9u +#define CYDEV_UCFG_B0_P6_U1_CFG10 0x40010ccau +#define CYDEV_UCFG_B0_P6_U1_CFG11 0x40010ccbu +#define CYDEV_UCFG_B0_P6_U1_CFG12 0x40010cccu +#define CYDEV_UCFG_B0_P6_U1_CFG13 0x40010ccdu +#define CYDEV_UCFG_B0_P6_U1_CFG14 0x40010cceu +#define CYDEV_UCFG_B0_P6_U1_CFG15 0x40010ccfu +#define CYDEV_UCFG_B0_P6_U1_CFG16 0x40010cd0u +#define CYDEV_UCFG_B0_P6_U1_CFG17 0x40010cd1u +#define CYDEV_UCFG_B0_P6_U1_CFG18 0x40010cd2u +#define CYDEV_UCFG_B0_P6_U1_CFG19 0x40010cd3u +#define CYDEV_UCFG_B0_P6_U1_CFG20 0x40010cd4u +#define CYDEV_UCFG_B0_P6_U1_CFG21 0x40010cd5u +#define CYDEV_UCFG_B0_P6_U1_CFG22 0x40010cd6u +#define CYDEV_UCFG_B0_P6_U1_CFG23 0x40010cd7u +#define CYDEV_UCFG_B0_P6_U1_CFG24 0x40010cd8u +#define CYDEV_UCFG_B0_P6_U1_CFG25 0x40010cd9u +#define CYDEV_UCFG_B0_P6_U1_CFG26 0x40010cdau +#define CYDEV_UCFG_B0_P6_U1_CFG27 0x40010cdbu +#define CYDEV_UCFG_B0_P6_U1_CFG28 0x40010cdcu +#define CYDEV_UCFG_B0_P6_U1_CFG29 0x40010cddu +#define CYDEV_UCFG_B0_P6_U1_CFG30 0x40010cdeu +#define CYDEV_UCFG_B0_P6_U1_CFG31 0x40010cdfu +#define CYDEV_UCFG_B0_P6_U1_DCFG0 0x40010ce0u +#define CYDEV_UCFG_B0_P6_U1_DCFG1 0x40010ce2u +#define CYDEV_UCFG_B0_P6_U1_DCFG2 0x40010ce4u +#define CYDEV_UCFG_B0_P6_U1_DCFG3 0x40010ce6u +#define CYDEV_UCFG_B0_P6_U1_DCFG4 0x40010ce8u +#define CYDEV_UCFG_B0_P6_U1_DCFG5 0x40010ceau +#define CYDEV_UCFG_B0_P6_U1_DCFG6 0x40010cecu +#define CYDEV_UCFG_B0_P6_U1_DCFG7 0x40010ceeu +#define CYDEV_UCFG_B0_P6_ROUTE_BASE 0x40010d00u +#define CYDEV_UCFG_B0_P6_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P7_BASE 0x40010e00u +#define CYDEV_UCFG_B0_P7_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P7_U0_BASE 0x40010e00u +#define CYDEV_UCFG_B0_P7_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT0 0x40010e00u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT1 0x40010e04u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT2 0x40010e08u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT3 0x40010e0cu +#define CYDEV_UCFG_B0_P7_U0_PLD_IT4 0x40010e10u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT5 0x40010e14u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT6 0x40010e18u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT7 0x40010e1cu +#define CYDEV_UCFG_B0_P7_U0_PLD_IT8 0x40010e20u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT9 0x40010e24u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT10 0x40010e28u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT11 0x40010e2cu +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT0 0x40010e30u +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT1 0x40010e32u +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT2 0x40010e34u +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT3 0x40010e36u +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST 0x40010e38u +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB 0x40010e3au +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET 0x40010e3cu +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS 0x40010e3eu +#define CYDEV_UCFG_B0_P7_U0_CFG0 0x40010e40u +#define CYDEV_UCFG_B0_P7_U0_CFG1 0x40010e41u +#define CYDEV_UCFG_B0_P7_U0_CFG2 0x40010e42u +#define CYDEV_UCFG_B0_P7_U0_CFG3 0x40010e43u +#define CYDEV_UCFG_B0_P7_U0_CFG4 0x40010e44u +#define CYDEV_UCFG_B0_P7_U0_CFG5 0x40010e45u +#define CYDEV_UCFG_B0_P7_U0_CFG6 0x40010e46u +#define CYDEV_UCFG_B0_P7_U0_CFG7 0x40010e47u +#define CYDEV_UCFG_B0_P7_U0_CFG8 0x40010e48u +#define CYDEV_UCFG_B0_P7_U0_CFG9 0x40010e49u +#define CYDEV_UCFG_B0_P7_U0_CFG10 0x40010e4au +#define CYDEV_UCFG_B0_P7_U0_CFG11 0x40010e4bu +#define CYDEV_UCFG_B0_P7_U0_CFG12 0x40010e4cu +#define CYDEV_UCFG_B0_P7_U0_CFG13 0x40010e4du +#define CYDEV_UCFG_B0_P7_U0_CFG14 0x40010e4eu +#define CYDEV_UCFG_B0_P7_U0_CFG15 0x40010e4fu +#define CYDEV_UCFG_B0_P7_U0_CFG16 0x40010e50u +#define CYDEV_UCFG_B0_P7_U0_CFG17 0x40010e51u +#define CYDEV_UCFG_B0_P7_U0_CFG18 0x40010e52u +#define CYDEV_UCFG_B0_P7_U0_CFG19 0x40010e53u +#define CYDEV_UCFG_B0_P7_U0_CFG20 0x40010e54u +#define CYDEV_UCFG_B0_P7_U0_CFG21 0x40010e55u +#define CYDEV_UCFG_B0_P7_U0_CFG22 0x40010e56u +#define CYDEV_UCFG_B0_P7_U0_CFG23 0x40010e57u +#define CYDEV_UCFG_B0_P7_U0_CFG24 0x40010e58u +#define CYDEV_UCFG_B0_P7_U0_CFG25 0x40010e59u +#define CYDEV_UCFG_B0_P7_U0_CFG26 0x40010e5au +#define CYDEV_UCFG_B0_P7_U0_CFG27 0x40010e5bu +#define CYDEV_UCFG_B0_P7_U0_CFG28 0x40010e5cu +#define CYDEV_UCFG_B0_P7_U0_CFG29 0x40010e5du +#define CYDEV_UCFG_B0_P7_U0_CFG30 0x40010e5eu +#define CYDEV_UCFG_B0_P7_U0_CFG31 0x40010e5fu +#define CYDEV_UCFG_B0_P7_U0_DCFG0 0x40010e60u +#define CYDEV_UCFG_B0_P7_U0_DCFG1 0x40010e62u +#define CYDEV_UCFG_B0_P7_U0_DCFG2 0x40010e64u +#define CYDEV_UCFG_B0_P7_U0_DCFG3 0x40010e66u +#define CYDEV_UCFG_B0_P7_U0_DCFG4 0x40010e68u +#define CYDEV_UCFG_B0_P7_U0_DCFG5 0x40010e6au +#define CYDEV_UCFG_B0_P7_U0_DCFG6 0x40010e6cu +#define CYDEV_UCFG_B0_P7_U0_DCFG7 0x40010e6eu +#define CYDEV_UCFG_B0_P7_U1_BASE 0x40010e80u +#define CYDEV_UCFG_B0_P7_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT0 0x40010e80u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT1 0x40010e84u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT2 0x40010e88u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT3 0x40010e8cu +#define CYDEV_UCFG_B0_P7_U1_PLD_IT4 0x40010e90u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT5 0x40010e94u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT6 0x40010e98u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT7 0x40010e9cu +#define CYDEV_UCFG_B0_P7_U1_PLD_IT8 0x40010ea0u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT9 0x40010ea4u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT10 0x40010ea8u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT11 0x40010eacu +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT0 0x40010eb0u +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT1 0x40010eb2u +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT2 0x40010eb4u +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT3 0x40010eb6u +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST 0x40010eb8u +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB 0x40010ebau +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET 0x40010ebcu +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS 0x40010ebeu +#define CYDEV_UCFG_B0_P7_U1_CFG0 0x40010ec0u +#define CYDEV_UCFG_B0_P7_U1_CFG1 0x40010ec1u +#define CYDEV_UCFG_B0_P7_U1_CFG2 0x40010ec2u +#define CYDEV_UCFG_B0_P7_U1_CFG3 0x40010ec3u +#define CYDEV_UCFG_B0_P7_U1_CFG4 0x40010ec4u +#define CYDEV_UCFG_B0_P7_U1_CFG5 0x40010ec5u +#define CYDEV_UCFG_B0_P7_U1_CFG6 0x40010ec6u +#define CYDEV_UCFG_B0_P7_U1_CFG7 0x40010ec7u +#define CYDEV_UCFG_B0_P7_U1_CFG8 0x40010ec8u +#define CYDEV_UCFG_B0_P7_U1_CFG9 0x40010ec9u +#define CYDEV_UCFG_B0_P7_U1_CFG10 0x40010ecau +#define CYDEV_UCFG_B0_P7_U1_CFG11 0x40010ecbu +#define CYDEV_UCFG_B0_P7_U1_CFG12 0x40010eccu +#define CYDEV_UCFG_B0_P7_U1_CFG13 0x40010ecdu +#define CYDEV_UCFG_B0_P7_U1_CFG14 0x40010eceu +#define CYDEV_UCFG_B0_P7_U1_CFG15 0x40010ecfu +#define CYDEV_UCFG_B0_P7_U1_CFG16 0x40010ed0u +#define CYDEV_UCFG_B0_P7_U1_CFG17 0x40010ed1u +#define CYDEV_UCFG_B0_P7_U1_CFG18 0x40010ed2u +#define CYDEV_UCFG_B0_P7_U1_CFG19 0x40010ed3u +#define CYDEV_UCFG_B0_P7_U1_CFG20 0x40010ed4u +#define CYDEV_UCFG_B0_P7_U1_CFG21 0x40010ed5u +#define CYDEV_UCFG_B0_P7_U1_CFG22 0x40010ed6u +#define CYDEV_UCFG_B0_P7_U1_CFG23 0x40010ed7u +#define CYDEV_UCFG_B0_P7_U1_CFG24 0x40010ed8u +#define CYDEV_UCFG_B0_P7_U1_CFG25 0x40010ed9u +#define CYDEV_UCFG_B0_P7_U1_CFG26 0x40010edau +#define CYDEV_UCFG_B0_P7_U1_CFG27 0x40010edbu +#define CYDEV_UCFG_B0_P7_U1_CFG28 0x40010edcu +#define CYDEV_UCFG_B0_P7_U1_CFG29 0x40010eddu +#define CYDEV_UCFG_B0_P7_U1_CFG30 0x40010edeu +#define CYDEV_UCFG_B0_P7_U1_CFG31 0x40010edfu +#define CYDEV_UCFG_B0_P7_U1_DCFG0 0x40010ee0u +#define CYDEV_UCFG_B0_P7_U1_DCFG1 0x40010ee2u +#define CYDEV_UCFG_B0_P7_U1_DCFG2 0x40010ee4u +#define CYDEV_UCFG_B0_P7_U1_DCFG3 0x40010ee6u +#define CYDEV_UCFG_B0_P7_U1_DCFG4 0x40010ee8u +#define CYDEV_UCFG_B0_P7_U1_DCFG5 0x40010eeau +#define CYDEV_UCFG_B0_P7_U1_DCFG6 0x40010eecu +#define CYDEV_UCFG_B0_P7_U1_DCFG7 0x40010eeeu +#define CYDEV_UCFG_B0_P7_ROUTE_BASE 0x40010f00u +#define CYDEV_UCFG_B0_P7_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_BASE 0x40011000u +#define CYDEV_UCFG_B1_SIZE 0x00000fefu +#define CYDEV_UCFG_B1_P2_BASE 0x40011400u +#define CYDEV_UCFG_B1_P2_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P2_U0_BASE 0x40011400u +#define CYDEV_UCFG_B1_P2_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT0 0x40011400u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT1 0x40011404u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT2 0x40011408u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT3 0x4001140cu +#define CYDEV_UCFG_B1_P2_U0_PLD_IT4 0x40011410u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT5 0x40011414u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT6 0x40011418u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT7 0x4001141cu +#define CYDEV_UCFG_B1_P2_U0_PLD_IT8 0x40011420u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT9 0x40011424u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT10 0x40011428u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT11 0x4001142cu +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT0 0x40011430u +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT1 0x40011432u +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT2 0x40011434u +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT3 0x40011436u +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST 0x40011438u +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB 0x4001143au +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET 0x4001143cu +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS 0x4001143eu +#define CYDEV_UCFG_B1_P2_U0_CFG0 0x40011440u +#define CYDEV_UCFG_B1_P2_U0_CFG1 0x40011441u +#define CYDEV_UCFG_B1_P2_U0_CFG2 0x40011442u +#define CYDEV_UCFG_B1_P2_U0_CFG3 0x40011443u +#define CYDEV_UCFG_B1_P2_U0_CFG4 0x40011444u +#define CYDEV_UCFG_B1_P2_U0_CFG5 0x40011445u +#define CYDEV_UCFG_B1_P2_U0_CFG6 0x40011446u +#define CYDEV_UCFG_B1_P2_U0_CFG7 0x40011447u +#define CYDEV_UCFG_B1_P2_U0_CFG8 0x40011448u +#define CYDEV_UCFG_B1_P2_U0_CFG9 0x40011449u +#define CYDEV_UCFG_B1_P2_U0_CFG10 0x4001144au +#define CYDEV_UCFG_B1_P2_U0_CFG11 0x4001144bu +#define CYDEV_UCFG_B1_P2_U0_CFG12 0x4001144cu +#define CYDEV_UCFG_B1_P2_U0_CFG13 0x4001144du +#define CYDEV_UCFG_B1_P2_U0_CFG14 0x4001144eu +#define CYDEV_UCFG_B1_P2_U0_CFG15 0x4001144fu +#define CYDEV_UCFG_B1_P2_U0_CFG16 0x40011450u +#define CYDEV_UCFG_B1_P2_U0_CFG17 0x40011451u +#define CYDEV_UCFG_B1_P2_U0_CFG18 0x40011452u +#define CYDEV_UCFG_B1_P2_U0_CFG19 0x40011453u +#define CYDEV_UCFG_B1_P2_U0_CFG20 0x40011454u +#define CYDEV_UCFG_B1_P2_U0_CFG21 0x40011455u +#define CYDEV_UCFG_B1_P2_U0_CFG22 0x40011456u +#define CYDEV_UCFG_B1_P2_U0_CFG23 0x40011457u +#define CYDEV_UCFG_B1_P2_U0_CFG24 0x40011458u +#define CYDEV_UCFG_B1_P2_U0_CFG25 0x40011459u +#define CYDEV_UCFG_B1_P2_U0_CFG26 0x4001145au +#define CYDEV_UCFG_B1_P2_U0_CFG27 0x4001145bu +#define CYDEV_UCFG_B1_P2_U0_CFG28 0x4001145cu +#define CYDEV_UCFG_B1_P2_U0_CFG29 0x4001145du +#define CYDEV_UCFG_B1_P2_U0_CFG30 0x4001145eu +#define CYDEV_UCFG_B1_P2_U0_CFG31 0x4001145fu +#define CYDEV_UCFG_B1_P2_U0_DCFG0 0x40011460u +#define CYDEV_UCFG_B1_P2_U0_DCFG1 0x40011462u +#define CYDEV_UCFG_B1_P2_U0_DCFG2 0x40011464u +#define CYDEV_UCFG_B1_P2_U0_DCFG3 0x40011466u +#define CYDEV_UCFG_B1_P2_U0_DCFG4 0x40011468u +#define CYDEV_UCFG_B1_P2_U0_DCFG5 0x4001146au +#define CYDEV_UCFG_B1_P2_U0_DCFG6 0x4001146cu +#define CYDEV_UCFG_B1_P2_U0_DCFG7 0x4001146eu +#define CYDEV_UCFG_B1_P2_U1_BASE 0x40011480u +#define CYDEV_UCFG_B1_P2_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT0 0x40011480u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT1 0x40011484u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT2 0x40011488u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT3 0x4001148cu +#define CYDEV_UCFG_B1_P2_U1_PLD_IT4 0x40011490u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT5 0x40011494u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT6 0x40011498u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT7 0x4001149cu +#define CYDEV_UCFG_B1_P2_U1_PLD_IT8 0x400114a0u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT9 0x400114a4u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT10 0x400114a8u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT11 0x400114acu +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT0 0x400114b0u +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT1 0x400114b2u +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT2 0x400114b4u +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT3 0x400114b6u +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST 0x400114b8u +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB 0x400114bau +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET 0x400114bcu +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS 0x400114beu +#define CYDEV_UCFG_B1_P2_U1_CFG0 0x400114c0u +#define CYDEV_UCFG_B1_P2_U1_CFG1 0x400114c1u +#define CYDEV_UCFG_B1_P2_U1_CFG2 0x400114c2u +#define CYDEV_UCFG_B1_P2_U1_CFG3 0x400114c3u +#define CYDEV_UCFG_B1_P2_U1_CFG4 0x400114c4u +#define CYDEV_UCFG_B1_P2_U1_CFG5 0x400114c5u +#define CYDEV_UCFG_B1_P2_U1_CFG6 0x400114c6u +#define CYDEV_UCFG_B1_P2_U1_CFG7 0x400114c7u +#define CYDEV_UCFG_B1_P2_U1_CFG8 0x400114c8u +#define CYDEV_UCFG_B1_P2_U1_CFG9 0x400114c9u +#define CYDEV_UCFG_B1_P2_U1_CFG10 0x400114cau +#define CYDEV_UCFG_B1_P2_U1_CFG11 0x400114cbu +#define CYDEV_UCFG_B1_P2_U1_CFG12 0x400114ccu +#define CYDEV_UCFG_B1_P2_U1_CFG13 0x400114cdu +#define CYDEV_UCFG_B1_P2_U1_CFG14 0x400114ceu +#define CYDEV_UCFG_B1_P2_U1_CFG15 0x400114cfu +#define CYDEV_UCFG_B1_P2_U1_CFG16 0x400114d0u +#define CYDEV_UCFG_B1_P2_U1_CFG17 0x400114d1u +#define CYDEV_UCFG_B1_P2_U1_CFG18 0x400114d2u +#define CYDEV_UCFG_B1_P2_U1_CFG19 0x400114d3u +#define CYDEV_UCFG_B1_P2_U1_CFG20 0x400114d4u +#define CYDEV_UCFG_B1_P2_U1_CFG21 0x400114d5u +#define CYDEV_UCFG_B1_P2_U1_CFG22 0x400114d6u +#define CYDEV_UCFG_B1_P2_U1_CFG23 0x400114d7u +#define CYDEV_UCFG_B1_P2_U1_CFG24 0x400114d8u +#define CYDEV_UCFG_B1_P2_U1_CFG25 0x400114d9u +#define CYDEV_UCFG_B1_P2_U1_CFG26 0x400114dau +#define CYDEV_UCFG_B1_P2_U1_CFG27 0x400114dbu +#define CYDEV_UCFG_B1_P2_U1_CFG28 0x400114dcu +#define CYDEV_UCFG_B1_P2_U1_CFG29 0x400114ddu +#define CYDEV_UCFG_B1_P2_U1_CFG30 0x400114deu +#define CYDEV_UCFG_B1_P2_U1_CFG31 0x400114dfu +#define CYDEV_UCFG_B1_P2_U1_DCFG0 0x400114e0u +#define CYDEV_UCFG_B1_P2_U1_DCFG1 0x400114e2u +#define CYDEV_UCFG_B1_P2_U1_DCFG2 0x400114e4u +#define CYDEV_UCFG_B1_P2_U1_DCFG3 0x400114e6u +#define CYDEV_UCFG_B1_P2_U1_DCFG4 0x400114e8u +#define CYDEV_UCFG_B1_P2_U1_DCFG5 0x400114eau +#define CYDEV_UCFG_B1_P2_U1_DCFG6 0x400114ecu +#define CYDEV_UCFG_B1_P2_U1_DCFG7 0x400114eeu +#define CYDEV_UCFG_B1_P2_ROUTE_BASE 0x40011500u +#define CYDEV_UCFG_B1_P2_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P3_BASE 0x40011600u +#define CYDEV_UCFG_B1_P3_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P3_U0_BASE 0x40011600u +#define CYDEV_UCFG_B1_P3_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT0 0x40011600u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT1 0x40011604u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT2 0x40011608u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT3 0x4001160cu +#define CYDEV_UCFG_B1_P3_U0_PLD_IT4 0x40011610u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT5 0x40011614u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT6 0x40011618u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT7 0x4001161cu +#define CYDEV_UCFG_B1_P3_U0_PLD_IT8 0x40011620u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT9 0x40011624u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT10 0x40011628u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT11 0x4001162cu +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT0 0x40011630u +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT1 0x40011632u +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT2 0x40011634u +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT3 0x40011636u +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST 0x40011638u +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB 0x4001163au +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET 0x4001163cu +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS 0x4001163eu +#define CYDEV_UCFG_B1_P3_U0_CFG0 0x40011640u +#define CYDEV_UCFG_B1_P3_U0_CFG1 0x40011641u +#define CYDEV_UCFG_B1_P3_U0_CFG2 0x40011642u +#define CYDEV_UCFG_B1_P3_U0_CFG3 0x40011643u +#define CYDEV_UCFG_B1_P3_U0_CFG4 0x40011644u +#define CYDEV_UCFG_B1_P3_U0_CFG5 0x40011645u +#define CYDEV_UCFG_B1_P3_U0_CFG6 0x40011646u +#define CYDEV_UCFG_B1_P3_U0_CFG7 0x40011647u +#define CYDEV_UCFG_B1_P3_U0_CFG8 0x40011648u +#define CYDEV_UCFG_B1_P3_U0_CFG9 0x40011649u +#define CYDEV_UCFG_B1_P3_U0_CFG10 0x4001164au +#define CYDEV_UCFG_B1_P3_U0_CFG11 0x4001164bu +#define CYDEV_UCFG_B1_P3_U0_CFG12 0x4001164cu +#define CYDEV_UCFG_B1_P3_U0_CFG13 0x4001164du +#define CYDEV_UCFG_B1_P3_U0_CFG14 0x4001164eu +#define CYDEV_UCFG_B1_P3_U0_CFG15 0x4001164fu +#define CYDEV_UCFG_B1_P3_U0_CFG16 0x40011650u +#define CYDEV_UCFG_B1_P3_U0_CFG17 0x40011651u +#define CYDEV_UCFG_B1_P3_U0_CFG18 0x40011652u +#define CYDEV_UCFG_B1_P3_U0_CFG19 0x40011653u +#define CYDEV_UCFG_B1_P3_U0_CFG20 0x40011654u +#define CYDEV_UCFG_B1_P3_U0_CFG21 0x40011655u +#define CYDEV_UCFG_B1_P3_U0_CFG22 0x40011656u +#define CYDEV_UCFG_B1_P3_U0_CFG23 0x40011657u +#define CYDEV_UCFG_B1_P3_U0_CFG24 0x40011658u +#define CYDEV_UCFG_B1_P3_U0_CFG25 0x40011659u +#define CYDEV_UCFG_B1_P3_U0_CFG26 0x4001165au +#define CYDEV_UCFG_B1_P3_U0_CFG27 0x4001165bu +#define CYDEV_UCFG_B1_P3_U0_CFG28 0x4001165cu +#define CYDEV_UCFG_B1_P3_U0_CFG29 0x4001165du +#define CYDEV_UCFG_B1_P3_U0_CFG30 0x4001165eu +#define CYDEV_UCFG_B1_P3_U0_CFG31 0x4001165fu +#define CYDEV_UCFG_B1_P3_U0_DCFG0 0x40011660u +#define CYDEV_UCFG_B1_P3_U0_DCFG1 0x40011662u +#define CYDEV_UCFG_B1_P3_U0_DCFG2 0x40011664u +#define CYDEV_UCFG_B1_P3_U0_DCFG3 0x40011666u +#define CYDEV_UCFG_B1_P3_U0_DCFG4 0x40011668u +#define CYDEV_UCFG_B1_P3_U0_DCFG5 0x4001166au +#define CYDEV_UCFG_B1_P3_U0_DCFG6 0x4001166cu +#define CYDEV_UCFG_B1_P3_U0_DCFG7 0x4001166eu +#define CYDEV_UCFG_B1_P3_U1_BASE 0x40011680u +#define CYDEV_UCFG_B1_P3_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT0 0x40011680u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT1 0x40011684u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT2 0x40011688u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT3 0x4001168cu +#define CYDEV_UCFG_B1_P3_U1_PLD_IT4 0x40011690u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT5 0x40011694u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT6 0x40011698u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT7 0x4001169cu +#define CYDEV_UCFG_B1_P3_U1_PLD_IT8 0x400116a0u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT9 0x400116a4u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT10 0x400116a8u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT11 0x400116acu +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT0 0x400116b0u +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT1 0x400116b2u +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT2 0x400116b4u +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT3 0x400116b6u +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST 0x400116b8u +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB 0x400116bau +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET 0x400116bcu +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS 0x400116beu +#define CYDEV_UCFG_B1_P3_U1_CFG0 0x400116c0u +#define CYDEV_UCFG_B1_P3_U1_CFG1 0x400116c1u +#define CYDEV_UCFG_B1_P3_U1_CFG2 0x400116c2u +#define CYDEV_UCFG_B1_P3_U1_CFG3 0x400116c3u +#define CYDEV_UCFG_B1_P3_U1_CFG4 0x400116c4u +#define CYDEV_UCFG_B1_P3_U1_CFG5 0x400116c5u +#define CYDEV_UCFG_B1_P3_U1_CFG6 0x400116c6u +#define CYDEV_UCFG_B1_P3_U1_CFG7 0x400116c7u +#define CYDEV_UCFG_B1_P3_U1_CFG8 0x400116c8u +#define CYDEV_UCFG_B1_P3_U1_CFG9 0x400116c9u +#define CYDEV_UCFG_B1_P3_U1_CFG10 0x400116cau +#define CYDEV_UCFG_B1_P3_U1_CFG11 0x400116cbu +#define CYDEV_UCFG_B1_P3_U1_CFG12 0x400116ccu +#define CYDEV_UCFG_B1_P3_U1_CFG13 0x400116cdu +#define CYDEV_UCFG_B1_P3_U1_CFG14 0x400116ceu +#define CYDEV_UCFG_B1_P3_U1_CFG15 0x400116cfu +#define CYDEV_UCFG_B1_P3_U1_CFG16 0x400116d0u +#define CYDEV_UCFG_B1_P3_U1_CFG17 0x400116d1u +#define CYDEV_UCFG_B1_P3_U1_CFG18 0x400116d2u +#define CYDEV_UCFG_B1_P3_U1_CFG19 0x400116d3u +#define CYDEV_UCFG_B1_P3_U1_CFG20 0x400116d4u +#define CYDEV_UCFG_B1_P3_U1_CFG21 0x400116d5u +#define CYDEV_UCFG_B1_P3_U1_CFG22 0x400116d6u +#define CYDEV_UCFG_B1_P3_U1_CFG23 0x400116d7u +#define CYDEV_UCFG_B1_P3_U1_CFG24 0x400116d8u +#define CYDEV_UCFG_B1_P3_U1_CFG25 0x400116d9u +#define CYDEV_UCFG_B1_P3_U1_CFG26 0x400116dau +#define CYDEV_UCFG_B1_P3_U1_CFG27 0x400116dbu +#define CYDEV_UCFG_B1_P3_U1_CFG28 0x400116dcu +#define CYDEV_UCFG_B1_P3_U1_CFG29 0x400116ddu +#define CYDEV_UCFG_B1_P3_U1_CFG30 0x400116deu +#define CYDEV_UCFG_B1_P3_U1_CFG31 0x400116dfu +#define CYDEV_UCFG_B1_P3_U1_DCFG0 0x400116e0u +#define CYDEV_UCFG_B1_P3_U1_DCFG1 0x400116e2u +#define CYDEV_UCFG_B1_P3_U1_DCFG2 0x400116e4u +#define CYDEV_UCFG_B1_P3_U1_DCFG3 0x400116e6u +#define CYDEV_UCFG_B1_P3_U1_DCFG4 0x400116e8u +#define CYDEV_UCFG_B1_P3_U1_DCFG5 0x400116eau +#define CYDEV_UCFG_B1_P3_U1_DCFG6 0x400116ecu +#define CYDEV_UCFG_B1_P3_U1_DCFG7 0x400116eeu +#define CYDEV_UCFG_B1_P3_ROUTE_BASE 0x40011700u +#define CYDEV_UCFG_B1_P3_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P4_BASE 0x40011800u +#define CYDEV_UCFG_B1_P4_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P4_U0_BASE 0x40011800u +#define CYDEV_UCFG_B1_P4_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT0 0x40011800u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT1 0x40011804u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT2 0x40011808u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT3 0x4001180cu +#define CYDEV_UCFG_B1_P4_U0_PLD_IT4 0x40011810u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT5 0x40011814u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT6 0x40011818u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT7 0x4001181cu +#define CYDEV_UCFG_B1_P4_U0_PLD_IT8 0x40011820u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT9 0x40011824u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT10 0x40011828u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT11 0x4001182cu +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT0 0x40011830u +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT1 0x40011832u +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT2 0x40011834u +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT3 0x40011836u +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST 0x40011838u +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB 0x4001183au +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET 0x4001183cu +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS 0x4001183eu +#define CYDEV_UCFG_B1_P4_U0_CFG0 0x40011840u +#define CYDEV_UCFG_B1_P4_U0_CFG1 0x40011841u +#define CYDEV_UCFG_B1_P4_U0_CFG2 0x40011842u +#define CYDEV_UCFG_B1_P4_U0_CFG3 0x40011843u +#define CYDEV_UCFG_B1_P4_U0_CFG4 0x40011844u +#define CYDEV_UCFG_B1_P4_U0_CFG5 0x40011845u +#define CYDEV_UCFG_B1_P4_U0_CFG6 0x40011846u +#define CYDEV_UCFG_B1_P4_U0_CFG7 0x40011847u +#define CYDEV_UCFG_B1_P4_U0_CFG8 0x40011848u +#define CYDEV_UCFG_B1_P4_U0_CFG9 0x40011849u +#define CYDEV_UCFG_B1_P4_U0_CFG10 0x4001184au +#define CYDEV_UCFG_B1_P4_U0_CFG11 0x4001184bu +#define CYDEV_UCFG_B1_P4_U0_CFG12 0x4001184cu +#define CYDEV_UCFG_B1_P4_U0_CFG13 0x4001184du +#define CYDEV_UCFG_B1_P4_U0_CFG14 0x4001184eu +#define CYDEV_UCFG_B1_P4_U0_CFG15 0x4001184fu +#define CYDEV_UCFG_B1_P4_U0_CFG16 0x40011850u +#define CYDEV_UCFG_B1_P4_U0_CFG17 0x40011851u +#define CYDEV_UCFG_B1_P4_U0_CFG18 0x40011852u +#define CYDEV_UCFG_B1_P4_U0_CFG19 0x40011853u +#define CYDEV_UCFG_B1_P4_U0_CFG20 0x40011854u +#define CYDEV_UCFG_B1_P4_U0_CFG21 0x40011855u +#define CYDEV_UCFG_B1_P4_U0_CFG22 0x40011856u +#define CYDEV_UCFG_B1_P4_U0_CFG23 0x40011857u +#define CYDEV_UCFG_B1_P4_U0_CFG24 0x40011858u +#define CYDEV_UCFG_B1_P4_U0_CFG25 0x40011859u +#define CYDEV_UCFG_B1_P4_U0_CFG26 0x4001185au +#define CYDEV_UCFG_B1_P4_U0_CFG27 0x4001185bu +#define CYDEV_UCFG_B1_P4_U0_CFG28 0x4001185cu +#define CYDEV_UCFG_B1_P4_U0_CFG29 0x4001185du +#define CYDEV_UCFG_B1_P4_U0_CFG30 0x4001185eu +#define CYDEV_UCFG_B1_P4_U0_CFG31 0x4001185fu +#define CYDEV_UCFG_B1_P4_U0_DCFG0 0x40011860u +#define CYDEV_UCFG_B1_P4_U0_DCFG1 0x40011862u +#define CYDEV_UCFG_B1_P4_U0_DCFG2 0x40011864u +#define CYDEV_UCFG_B1_P4_U0_DCFG3 0x40011866u +#define CYDEV_UCFG_B1_P4_U0_DCFG4 0x40011868u +#define CYDEV_UCFG_B1_P4_U0_DCFG5 0x4001186au +#define CYDEV_UCFG_B1_P4_U0_DCFG6 0x4001186cu +#define CYDEV_UCFG_B1_P4_U0_DCFG7 0x4001186eu +#define CYDEV_UCFG_B1_P4_U1_BASE 0x40011880u +#define CYDEV_UCFG_B1_P4_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT0 0x40011880u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT1 0x40011884u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT2 0x40011888u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT3 0x4001188cu +#define CYDEV_UCFG_B1_P4_U1_PLD_IT4 0x40011890u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT5 0x40011894u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT6 0x40011898u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT7 0x4001189cu +#define CYDEV_UCFG_B1_P4_U1_PLD_IT8 0x400118a0u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT9 0x400118a4u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT10 0x400118a8u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT11 0x400118acu +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT0 0x400118b0u +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT1 0x400118b2u +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT2 0x400118b4u +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT3 0x400118b6u +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST 0x400118b8u +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB 0x400118bau +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET 0x400118bcu +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS 0x400118beu +#define CYDEV_UCFG_B1_P4_U1_CFG0 0x400118c0u +#define CYDEV_UCFG_B1_P4_U1_CFG1 0x400118c1u +#define CYDEV_UCFG_B1_P4_U1_CFG2 0x400118c2u +#define CYDEV_UCFG_B1_P4_U1_CFG3 0x400118c3u +#define CYDEV_UCFG_B1_P4_U1_CFG4 0x400118c4u +#define CYDEV_UCFG_B1_P4_U1_CFG5 0x400118c5u +#define CYDEV_UCFG_B1_P4_U1_CFG6 0x400118c6u +#define CYDEV_UCFG_B1_P4_U1_CFG7 0x400118c7u +#define CYDEV_UCFG_B1_P4_U1_CFG8 0x400118c8u +#define CYDEV_UCFG_B1_P4_U1_CFG9 0x400118c9u +#define CYDEV_UCFG_B1_P4_U1_CFG10 0x400118cau +#define CYDEV_UCFG_B1_P4_U1_CFG11 0x400118cbu +#define CYDEV_UCFG_B1_P4_U1_CFG12 0x400118ccu +#define CYDEV_UCFG_B1_P4_U1_CFG13 0x400118cdu +#define CYDEV_UCFG_B1_P4_U1_CFG14 0x400118ceu +#define CYDEV_UCFG_B1_P4_U1_CFG15 0x400118cfu +#define CYDEV_UCFG_B1_P4_U1_CFG16 0x400118d0u +#define CYDEV_UCFG_B1_P4_U1_CFG17 0x400118d1u +#define CYDEV_UCFG_B1_P4_U1_CFG18 0x400118d2u +#define CYDEV_UCFG_B1_P4_U1_CFG19 0x400118d3u +#define CYDEV_UCFG_B1_P4_U1_CFG20 0x400118d4u +#define CYDEV_UCFG_B1_P4_U1_CFG21 0x400118d5u +#define CYDEV_UCFG_B1_P4_U1_CFG22 0x400118d6u +#define CYDEV_UCFG_B1_P4_U1_CFG23 0x400118d7u +#define CYDEV_UCFG_B1_P4_U1_CFG24 0x400118d8u +#define CYDEV_UCFG_B1_P4_U1_CFG25 0x400118d9u +#define CYDEV_UCFG_B1_P4_U1_CFG26 0x400118dau +#define CYDEV_UCFG_B1_P4_U1_CFG27 0x400118dbu +#define CYDEV_UCFG_B1_P4_U1_CFG28 0x400118dcu +#define CYDEV_UCFG_B1_P4_U1_CFG29 0x400118ddu +#define CYDEV_UCFG_B1_P4_U1_CFG30 0x400118deu +#define CYDEV_UCFG_B1_P4_U1_CFG31 0x400118dfu +#define CYDEV_UCFG_B1_P4_U1_DCFG0 0x400118e0u +#define CYDEV_UCFG_B1_P4_U1_DCFG1 0x400118e2u +#define CYDEV_UCFG_B1_P4_U1_DCFG2 0x400118e4u +#define CYDEV_UCFG_B1_P4_U1_DCFG3 0x400118e6u +#define CYDEV_UCFG_B1_P4_U1_DCFG4 0x400118e8u +#define CYDEV_UCFG_B1_P4_U1_DCFG5 0x400118eau +#define CYDEV_UCFG_B1_P4_U1_DCFG6 0x400118ecu +#define CYDEV_UCFG_B1_P4_U1_DCFG7 0x400118eeu +#define CYDEV_UCFG_B1_P4_ROUTE_BASE 0x40011900u +#define CYDEV_UCFG_B1_P4_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P5_BASE 0x40011a00u +#define CYDEV_UCFG_B1_P5_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P5_U0_BASE 0x40011a00u +#define CYDEV_UCFG_B1_P5_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT0 0x40011a00u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT1 0x40011a04u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT2 0x40011a08u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT3 0x40011a0cu +#define CYDEV_UCFG_B1_P5_U0_PLD_IT4 0x40011a10u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT5 0x40011a14u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT6 0x40011a18u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT7 0x40011a1cu +#define CYDEV_UCFG_B1_P5_U0_PLD_IT8 0x40011a20u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT9 0x40011a24u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT10 0x40011a28u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT11 0x40011a2cu +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT0 0x40011a30u +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT1 0x40011a32u +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT2 0x40011a34u +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT3 0x40011a36u +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST 0x40011a38u +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB 0x40011a3au +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET 0x40011a3cu +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS 0x40011a3eu +#define CYDEV_UCFG_B1_P5_U0_CFG0 0x40011a40u +#define CYDEV_UCFG_B1_P5_U0_CFG1 0x40011a41u +#define CYDEV_UCFG_B1_P5_U0_CFG2 0x40011a42u +#define CYDEV_UCFG_B1_P5_U0_CFG3 0x40011a43u +#define CYDEV_UCFG_B1_P5_U0_CFG4 0x40011a44u +#define CYDEV_UCFG_B1_P5_U0_CFG5 0x40011a45u +#define CYDEV_UCFG_B1_P5_U0_CFG6 0x40011a46u +#define CYDEV_UCFG_B1_P5_U0_CFG7 0x40011a47u +#define CYDEV_UCFG_B1_P5_U0_CFG8 0x40011a48u +#define CYDEV_UCFG_B1_P5_U0_CFG9 0x40011a49u +#define CYDEV_UCFG_B1_P5_U0_CFG10 0x40011a4au +#define CYDEV_UCFG_B1_P5_U0_CFG11 0x40011a4bu +#define CYDEV_UCFG_B1_P5_U0_CFG12 0x40011a4cu +#define CYDEV_UCFG_B1_P5_U0_CFG13 0x40011a4du +#define CYDEV_UCFG_B1_P5_U0_CFG14 0x40011a4eu +#define CYDEV_UCFG_B1_P5_U0_CFG15 0x40011a4fu +#define CYDEV_UCFG_B1_P5_U0_CFG16 0x40011a50u +#define CYDEV_UCFG_B1_P5_U0_CFG17 0x40011a51u +#define CYDEV_UCFG_B1_P5_U0_CFG18 0x40011a52u +#define CYDEV_UCFG_B1_P5_U0_CFG19 0x40011a53u +#define CYDEV_UCFG_B1_P5_U0_CFG20 0x40011a54u +#define CYDEV_UCFG_B1_P5_U0_CFG21 0x40011a55u +#define CYDEV_UCFG_B1_P5_U0_CFG22 0x40011a56u +#define CYDEV_UCFG_B1_P5_U0_CFG23 0x40011a57u +#define CYDEV_UCFG_B1_P5_U0_CFG24 0x40011a58u +#define CYDEV_UCFG_B1_P5_U0_CFG25 0x40011a59u +#define CYDEV_UCFG_B1_P5_U0_CFG26 0x40011a5au +#define CYDEV_UCFG_B1_P5_U0_CFG27 0x40011a5bu +#define CYDEV_UCFG_B1_P5_U0_CFG28 0x40011a5cu +#define CYDEV_UCFG_B1_P5_U0_CFG29 0x40011a5du +#define CYDEV_UCFG_B1_P5_U0_CFG30 0x40011a5eu +#define CYDEV_UCFG_B1_P5_U0_CFG31 0x40011a5fu +#define CYDEV_UCFG_B1_P5_U0_DCFG0 0x40011a60u +#define CYDEV_UCFG_B1_P5_U0_DCFG1 0x40011a62u +#define CYDEV_UCFG_B1_P5_U0_DCFG2 0x40011a64u +#define CYDEV_UCFG_B1_P5_U0_DCFG3 0x40011a66u +#define CYDEV_UCFG_B1_P5_U0_DCFG4 0x40011a68u +#define CYDEV_UCFG_B1_P5_U0_DCFG5 0x40011a6au +#define CYDEV_UCFG_B1_P5_U0_DCFG6 0x40011a6cu +#define CYDEV_UCFG_B1_P5_U0_DCFG7 0x40011a6eu +#define CYDEV_UCFG_B1_P5_U1_BASE 0x40011a80u +#define CYDEV_UCFG_B1_P5_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT0 0x40011a80u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT1 0x40011a84u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT2 0x40011a88u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT3 0x40011a8cu +#define CYDEV_UCFG_B1_P5_U1_PLD_IT4 0x40011a90u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT5 0x40011a94u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT6 0x40011a98u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT7 0x40011a9cu +#define CYDEV_UCFG_B1_P5_U1_PLD_IT8 0x40011aa0u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT9 0x40011aa4u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT10 0x40011aa8u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT11 0x40011aacu +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT0 0x40011ab0u +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT1 0x40011ab2u +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT2 0x40011ab4u +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT3 0x40011ab6u +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST 0x40011ab8u +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB 0x40011abau +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET 0x40011abcu +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS 0x40011abeu +#define CYDEV_UCFG_B1_P5_U1_CFG0 0x40011ac0u +#define CYDEV_UCFG_B1_P5_U1_CFG1 0x40011ac1u +#define CYDEV_UCFG_B1_P5_U1_CFG2 0x40011ac2u +#define CYDEV_UCFG_B1_P5_U1_CFG3 0x40011ac3u +#define CYDEV_UCFG_B1_P5_U1_CFG4 0x40011ac4u +#define CYDEV_UCFG_B1_P5_U1_CFG5 0x40011ac5u +#define CYDEV_UCFG_B1_P5_U1_CFG6 0x40011ac6u +#define CYDEV_UCFG_B1_P5_U1_CFG7 0x40011ac7u +#define CYDEV_UCFG_B1_P5_U1_CFG8 0x40011ac8u +#define CYDEV_UCFG_B1_P5_U1_CFG9 0x40011ac9u +#define CYDEV_UCFG_B1_P5_U1_CFG10 0x40011acau +#define CYDEV_UCFG_B1_P5_U1_CFG11 0x40011acbu +#define CYDEV_UCFG_B1_P5_U1_CFG12 0x40011accu +#define CYDEV_UCFG_B1_P5_U1_CFG13 0x40011acdu +#define CYDEV_UCFG_B1_P5_U1_CFG14 0x40011aceu +#define CYDEV_UCFG_B1_P5_U1_CFG15 0x40011acfu +#define CYDEV_UCFG_B1_P5_U1_CFG16 0x40011ad0u +#define CYDEV_UCFG_B1_P5_U1_CFG17 0x40011ad1u +#define CYDEV_UCFG_B1_P5_U1_CFG18 0x40011ad2u +#define CYDEV_UCFG_B1_P5_U1_CFG19 0x40011ad3u +#define CYDEV_UCFG_B1_P5_U1_CFG20 0x40011ad4u +#define CYDEV_UCFG_B1_P5_U1_CFG21 0x40011ad5u +#define CYDEV_UCFG_B1_P5_U1_CFG22 0x40011ad6u +#define CYDEV_UCFG_B1_P5_U1_CFG23 0x40011ad7u +#define CYDEV_UCFG_B1_P5_U1_CFG24 0x40011ad8u +#define CYDEV_UCFG_B1_P5_U1_CFG25 0x40011ad9u +#define CYDEV_UCFG_B1_P5_U1_CFG26 0x40011adau +#define CYDEV_UCFG_B1_P5_U1_CFG27 0x40011adbu +#define CYDEV_UCFG_B1_P5_U1_CFG28 0x40011adcu +#define CYDEV_UCFG_B1_P5_U1_CFG29 0x40011addu +#define CYDEV_UCFG_B1_P5_U1_CFG30 0x40011adeu +#define CYDEV_UCFG_B1_P5_U1_CFG31 0x40011adfu +#define CYDEV_UCFG_B1_P5_U1_DCFG0 0x40011ae0u +#define CYDEV_UCFG_B1_P5_U1_DCFG1 0x40011ae2u +#define CYDEV_UCFG_B1_P5_U1_DCFG2 0x40011ae4u +#define CYDEV_UCFG_B1_P5_U1_DCFG3 0x40011ae6u +#define CYDEV_UCFG_B1_P5_U1_DCFG4 0x40011ae8u +#define CYDEV_UCFG_B1_P5_U1_DCFG5 0x40011aeau +#define CYDEV_UCFG_B1_P5_U1_DCFG6 0x40011aecu +#define CYDEV_UCFG_B1_P5_U1_DCFG7 0x40011aeeu +#define CYDEV_UCFG_B1_P5_ROUTE_BASE 0x40011b00u +#define CYDEV_UCFG_B1_P5_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_DSI0_BASE 0x40014000u +#define CYDEV_UCFG_DSI0_SIZE 0x000000efu +#define CYDEV_UCFG_DSI1_BASE 0x40014100u +#define CYDEV_UCFG_DSI1_SIZE 0x000000efu +#define CYDEV_UCFG_DSI2_BASE 0x40014200u +#define CYDEV_UCFG_DSI2_SIZE 0x000000efu +#define CYDEV_UCFG_DSI3_BASE 0x40014300u +#define CYDEV_UCFG_DSI3_SIZE 0x000000efu +#define CYDEV_UCFG_DSI4_BASE 0x40014400u +#define CYDEV_UCFG_DSI4_SIZE 0x000000efu +#define CYDEV_UCFG_DSI5_BASE 0x40014500u +#define CYDEV_UCFG_DSI5_SIZE 0x000000efu +#define CYDEV_UCFG_DSI6_BASE 0x40014600u +#define CYDEV_UCFG_DSI6_SIZE 0x000000efu +#define CYDEV_UCFG_DSI7_BASE 0x40014700u +#define CYDEV_UCFG_DSI7_SIZE 0x000000efu +#define CYDEV_UCFG_DSI8_BASE 0x40014800u +#define CYDEV_UCFG_DSI8_SIZE 0x000000efu +#define CYDEV_UCFG_DSI9_BASE 0x40014900u +#define CYDEV_UCFG_DSI9_SIZE 0x000000efu +#define CYDEV_UCFG_DSI12_BASE 0x40014c00u +#define CYDEV_UCFG_DSI12_SIZE 0x000000efu +#define CYDEV_UCFG_DSI13_BASE 0x40014d00u +#define CYDEV_UCFG_DSI13_SIZE 0x000000efu +#define CYDEV_UCFG_BCTL0_BASE 0x40015000u +#define CYDEV_UCFG_BCTL0_SIZE 0x00000010u +#define CYDEV_UCFG_BCTL0_MDCLK_EN 0x40015000u +#define CYDEV_UCFG_BCTL0_MBCLK_EN 0x40015001u +#define CYDEV_UCFG_BCTL0_WAIT_CFG 0x40015002u +#define CYDEV_UCFG_BCTL0_BANK_CTL 0x40015003u +#define CYDEV_UCFG_BCTL0_UDB_TEST_3 0x40015007u +#define CYDEV_UCFG_BCTL0_DCLK_EN0 0x40015008u +#define CYDEV_UCFG_BCTL0_BCLK_EN0 0x40015009u +#define CYDEV_UCFG_BCTL0_DCLK_EN1 0x4001500au +#define CYDEV_UCFG_BCTL0_BCLK_EN1 0x4001500bu +#define CYDEV_UCFG_BCTL0_DCLK_EN2 0x4001500cu +#define CYDEV_UCFG_BCTL0_BCLK_EN2 0x4001500du +#define CYDEV_UCFG_BCTL0_DCLK_EN3 0x4001500eu +#define CYDEV_UCFG_BCTL0_BCLK_EN3 0x4001500fu +#define CYDEV_UCFG_BCTL1_BASE 0x40015010u +#define CYDEV_UCFG_BCTL1_SIZE 0x00000010u +#define CYDEV_UCFG_BCTL1_MDCLK_EN 0x40015010u +#define CYDEV_UCFG_BCTL1_MBCLK_EN 0x40015011u +#define CYDEV_UCFG_BCTL1_WAIT_CFG 0x40015012u +#define CYDEV_UCFG_BCTL1_BANK_CTL 0x40015013u +#define CYDEV_UCFG_BCTL1_UDB_TEST_3 0x40015017u +#define CYDEV_UCFG_BCTL1_DCLK_EN0 0x40015018u +#define CYDEV_UCFG_BCTL1_BCLK_EN0 0x40015019u +#define CYDEV_UCFG_BCTL1_DCLK_EN1 0x4001501au +#define CYDEV_UCFG_BCTL1_BCLK_EN1 0x4001501bu +#define CYDEV_UCFG_BCTL1_DCLK_EN2 0x4001501cu +#define CYDEV_UCFG_BCTL1_BCLK_EN2 0x4001501du +#define CYDEV_UCFG_BCTL1_DCLK_EN3 0x4001501eu +#define CYDEV_UCFG_BCTL1_BCLK_EN3 0x4001501fu +#define CYDEV_IDMUX_BASE 0x40015100u +#define CYDEV_IDMUX_SIZE 0x00000016u +#define CYDEV_IDMUX_IRQ_CTL0 0x40015100u +#define CYDEV_IDMUX_IRQ_CTL1 0x40015101u +#define CYDEV_IDMUX_IRQ_CTL2 0x40015102u +#define CYDEV_IDMUX_IRQ_CTL3 0x40015103u +#define CYDEV_IDMUX_IRQ_CTL4 0x40015104u +#define CYDEV_IDMUX_IRQ_CTL5 0x40015105u +#define CYDEV_IDMUX_IRQ_CTL6 0x40015106u +#define CYDEV_IDMUX_IRQ_CTL7 0x40015107u +#define CYDEV_IDMUX_DRQ_CTL0 0x40015110u +#define CYDEV_IDMUX_DRQ_CTL1 0x40015111u +#define CYDEV_IDMUX_DRQ_CTL2 0x40015112u +#define CYDEV_IDMUX_DRQ_CTL3 0x40015113u +#define CYDEV_IDMUX_DRQ_CTL4 0x40015114u +#define CYDEV_IDMUX_DRQ_CTL5 0x40015115u +#define CYDEV_CACHERAM_BASE 0x40030000u +#define CYDEV_CACHERAM_SIZE 0x00000400u +#define CYDEV_CACHERAM_DATA_MBASE 0x40030000u +#define CYDEV_CACHERAM_DATA_MSIZE 0x00000400u +#define CYDEV_SFR_BASE 0x40050100u +#define CYDEV_SFR_SIZE 0x000000fbu +#define CYDEV_SFR_GPIO0 0x40050180u +#define CYDEV_SFR_GPIRD0 0x40050189u +#define CYDEV_SFR_GPIO0_SEL 0x4005018au +#define CYDEV_SFR_GPIO1 0x40050190u +#define CYDEV_SFR_GPIRD1 0x40050191u +#define CYDEV_SFR_GPIO2 0x40050198u +#define CYDEV_SFR_GPIRD2 0x40050199u +#define CYDEV_SFR_GPIO2_SEL 0x4005019au +#define CYDEV_SFR_GPIO1_SEL 0x400501a2u +#define CYDEV_SFR_GPIO3 0x400501b0u +#define CYDEV_SFR_GPIRD3 0x400501b1u +#define CYDEV_SFR_GPIO3_SEL 0x400501b2u +#define CYDEV_SFR_GPIO4 0x400501c0u +#define CYDEV_SFR_GPIRD4 0x400501c1u +#define CYDEV_SFR_GPIO4_SEL 0x400501c2u +#define CYDEV_SFR_GPIO5 0x400501c8u +#define CYDEV_SFR_GPIRD5 0x400501c9u +#define CYDEV_SFR_GPIO5_SEL 0x400501cau +#define CYDEV_SFR_GPIO6 0x400501d8u +#define CYDEV_SFR_GPIRD6 0x400501d9u +#define CYDEV_SFR_GPIO6_SEL 0x400501dau +#define CYDEV_SFR_GPIO12 0x400501e8u +#define CYDEV_SFR_GPIRD12 0x400501e9u +#define CYDEV_SFR_GPIO12_SEL 0x400501f2u +#define CYDEV_SFR_GPIO15 0x400501f8u +#define CYDEV_SFR_GPIRD15 0x400501f9u +#define CYDEV_SFR_GPIO15_SEL 0x400501fau +#define CYDEV_P3BA_BASE 0x40050300u +#define CYDEV_P3BA_SIZE 0x0000002bu +#define CYDEV_P3BA_Y_START 0x40050300u +#define CYDEV_P3BA_YROLL 0x40050301u +#define CYDEV_P3BA_YCFG 0x40050302u +#define CYDEV_P3BA_X_START1 0x40050303u +#define CYDEV_P3BA_X_START2 0x40050304u +#define CYDEV_P3BA_XROLL1 0x40050305u +#define CYDEV_P3BA_XROLL2 0x40050306u +#define CYDEV_P3BA_XINC 0x40050307u +#define CYDEV_P3BA_XCFG 0x40050308u +#define CYDEV_P3BA_OFFSETADDR1 0x40050309u +#define CYDEV_P3BA_OFFSETADDR2 0x4005030au +#define CYDEV_P3BA_OFFSETADDR3 0x4005030bu +#define CYDEV_P3BA_ABSADDR1 0x4005030cu +#define CYDEV_P3BA_ABSADDR2 0x4005030du +#define CYDEV_P3BA_ABSADDR3 0x4005030eu +#define CYDEV_P3BA_ABSADDR4 0x4005030fu +#define CYDEV_P3BA_DATCFG1 0x40050310u +#define CYDEV_P3BA_DATCFG2 0x40050311u +#define CYDEV_P3BA_CMP_RSLT1 0x40050314u +#define CYDEV_P3BA_CMP_RSLT2 0x40050315u +#define CYDEV_P3BA_CMP_RSLT3 0x40050316u +#define CYDEV_P3BA_CMP_RSLT4 0x40050317u +#define CYDEV_P3BA_DATA_REG1 0x40050318u +#define CYDEV_P3BA_DATA_REG2 0x40050319u +#define CYDEV_P3BA_DATA_REG3 0x4005031au +#define CYDEV_P3BA_DATA_REG4 0x4005031bu +#define CYDEV_P3BA_EXP_DATA1 0x4005031cu +#define CYDEV_P3BA_EXP_DATA2 0x4005031du +#define CYDEV_P3BA_EXP_DATA3 0x4005031eu +#define CYDEV_P3BA_EXP_DATA4 0x4005031fu +#define CYDEV_P3BA_MSTR_HRDATA1 0x40050320u +#define CYDEV_P3BA_MSTR_HRDATA2 0x40050321u +#define CYDEV_P3BA_MSTR_HRDATA3 0x40050322u +#define CYDEV_P3BA_MSTR_HRDATA4 0x40050323u +#define CYDEV_P3BA_BIST_EN 0x40050324u +#define CYDEV_P3BA_PHUB_MASTER_SSR 0x40050325u +#define CYDEV_P3BA_SEQCFG1 0x40050326u +#define CYDEV_P3BA_SEQCFG2 0x40050327u +#define CYDEV_P3BA_Y_CURR 0x40050328u +#define CYDEV_P3BA_X_CURR1 0x40050329u +#define CYDEV_P3BA_X_CURR2 0x4005032au +#define CYDEV_PANTHER_BASE 0x40080000u +#define CYDEV_PANTHER_SIZE 0x00000020u +#define CYDEV_PANTHER_STCALIB_CFG 0x40080000u +#define CYDEV_PANTHER_WAITPIPE 0x40080004u +#define CYDEV_PANTHER_TRACE_CFG 0x40080008u +#define CYDEV_PANTHER_DBG_CFG 0x4008000cu +#define CYDEV_PANTHER_CM3_LCKRST_STAT 0x40080018u +#define CYDEV_PANTHER_DEVICE_ID 0x4008001cu +#define CYDEV_FLSECC_BASE 0x48000000u +#define CYDEV_FLSECC_SIZE 0x00008000u +#define CYDEV_FLSECC_DATA_MBASE 0x48000000u +#define CYDEV_FLSECC_DATA_MSIZE 0x00008000u +#define CYDEV_FLSHID_BASE 0x49000000u +#define CYDEV_FLSHID_SIZE 0x00000200u +#define CYDEV_FLSHID_RSVD_MBASE 0x49000000u +#define CYDEV_FLSHID_RSVD_MSIZE 0x00000080u +#define CYDEV_FLSHID_CUST_MDATA_MBASE 0x49000080u +#define CYDEV_FLSHID_CUST_MDATA_MSIZE 0x00000080u +#define CYDEV_FLSHID_CUST_TABLES_BASE 0x49000100u +#define CYDEV_FLSHID_CUST_TABLES_SIZE 0x00000040u +#define CYDEV_FLSHID_CUST_TABLES_Y_LOC 0x49000100u +#define CYDEV_FLSHID_CUST_TABLES_X_LOC 0x49000101u +#define CYDEV_FLSHID_CUST_TABLES_WAFER_NUM 0x49000102u +#define CYDEV_FLSHID_CUST_TABLES_LOT_LSB 0x49000103u +#define CYDEV_FLSHID_CUST_TABLES_LOT_MSB 0x49000104u +#define CYDEV_FLSHID_CUST_TABLES_WRK_WK 0x49000105u +#define CYDEV_FLSHID_CUST_TABLES_FAB_YR 0x49000106u +#define CYDEV_FLSHID_CUST_TABLES_MINOR 0x49000107u +#define CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ 0x49000108u +#define CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ 0x49000109u +#define CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ 0x4900010au +#define CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ 0x4900010bu +#define CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ 0x4900010cu +#define CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ 0x4900010du +#define CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ 0x4900010eu +#define CYDEV_FLSHID_CUST_TABLES_IMO_USB 0x4900010fu +#define CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS 0x49000110u +#define CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS 0x49000111u +#define CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS 0x49000112u +#define CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS 0x49000113u +#define CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS 0x49000114u +#define CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS 0x49000115u +#define CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS 0x49000116u +#define CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS 0x49000117u +#define CYDEV_FLSHID_CUST_TABLES_DEC_M1 0x49000118u +#define CYDEV_FLSHID_CUST_TABLES_DEC_M2 0x49000119u +#define CYDEV_FLSHID_CUST_TABLES_DEC_M3 0x4900011au +#define CYDEV_FLSHID_CUST_TABLES_DEC_M4 0x4900011bu +#define CYDEV_FLSHID_CUST_TABLES_DEC_M5 0x4900011cu +#define CYDEV_FLSHID_CUST_TABLES_DEC_M6 0x4900011du +#define CYDEV_FLSHID_CUST_TABLES_DEC_M7 0x4900011eu +#define CYDEV_FLSHID_CUST_TABLES_DEC_M8 0x4900011fu +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M1 0x49000120u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M2 0x49000121u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M3 0x49000122u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M4 0x49000123u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M5 0x49000124u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M6 0x49000125u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M7 0x49000126u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M8 0x49000127u +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M1 0x49000128u +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M2 0x49000129u +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M3 0x4900012au +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M4 0x4900012bu +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M5 0x4900012cu +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M6 0x4900012du +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M7 0x4900012eu +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M8 0x4900012fu +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M1 0x49000130u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M2 0x49000131u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M3 0x49000132u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M4 0x49000133u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M5 0x49000134u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M6 0x49000135u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M7 0x49000136u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M8 0x49000137u +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M1 0x49000138u +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M2 0x49000139u +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M3 0x4900013au +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M4 0x4900013bu +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M5 0x4900013cu +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M6 0x4900013du +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M7 0x4900013eu +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M8 0x4900013fu +#define CYDEV_FLSHID_MFG_CFG_BASE 0x49000180u +#define CYDEV_FLSHID_MFG_CFG_SIZE 0x00000080u +#define CYDEV_FLSHID_MFG_CFG_IMO_TR1 0x49000188u +#define CYDEV_FLSHID_MFG_CFG_CMP0_TR0 0x490001acu +#define CYDEV_FLSHID_MFG_CFG_CMP1_TR0 0x490001aeu +#define CYDEV_FLSHID_MFG_CFG_CMP2_TR0 0x490001b0u +#define CYDEV_FLSHID_MFG_CFG_CMP3_TR0 0x490001b2u +#define CYDEV_FLSHID_MFG_CFG_CMP0_TR1 0x490001b4u +#define CYDEV_FLSHID_MFG_CFG_CMP1_TR1 0x490001b6u +#define CYDEV_FLSHID_MFG_CFG_CMP2_TR1 0x490001b8u +#define CYDEV_FLSHID_MFG_CFG_CMP3_TR1 0x490001bau +#define CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM 0x490001ceu +#define CYDEV_EXTMEM_BASE 0x60000000u +#define CYDEV_EXTMEM_SIZE 0x00800000u +#define CYDEV_EXTMEM_DATA_MBASE 0x60000000u +#define CYDEV_EXTMEM_DATA_MSIZE 0x00800000u +#define CYDEV_ITM_BASE 0xe0000000u +#define CYDEV_ITM_SIZE 0x00001000u +#define CYDEV_ITM_TRACE_EN 0xe0000e00u +#define CYDEV_ITM_TRACE_PRIVILEGE 0xe0000e40u +#define CYDEV_ITM_TRACE_CTRL 0xe0000e80u +#define CYDEV_ITM_LOCK_ACCESS 0xe0000fb0u +#define CYDEV_ITM_LOCK_STATUS 0xe0000fb4u +#define CYDEV_ITM_PID4 0xe0000fd0u +#define CYDEV_ITM_PID5 0xe0000fd4u +#define CYDEV_ITM_PID6 0xe0000fd8u +#define CYDEV_ITM_PID7 0xe0000fdcu +#define CYDEV_ITM_PID0 0xe0000fe0u +#define CYDEV_ITM_PID1 0xe0000fe4u +#define CYDEV_ITM_PID2 0xe0000fe8u +#define CYDEV_ITM_PID3 0xe0000fecu +#define CYDEV_ITM_CID0 0xe0000ff0u +#define CYDEV_ITM_CID1 0xe0000ff4u +#define CYDEV_ITM_CID2 0xe0000ff8u +#define CYDEV_ITM_CID3 0xe0000ffcu +#define CYDEV_DWT_BASE 0xe0001000u +#define CYDEV_DWT_SIZE 0x0000005cu +#define CYDEV_DWT_CTRL 0xe0001000u +#define CYDEV_DWT_CYCLE_COUNT 0xe0001004u +#define CYDEV_DWT_CPI_COUNT 0xe0001008u +#define CYDEV_DWT_EXC_OVHD_COUNT 0xe000100cu +#define CYDEV_DWT_SLEEP_COUNT 0xe0001010u +#define CYDEV_DWT_LSU_COUNT 0xe0001014u +#define CYDEV_DWT_FOLD_COUNT 0xe0001018u +#define CYDEV_DWT_PC_SAMPLE 0xe000101cu +#define CYDEV_DWT_COMP_0 0xe0001020u +#define CYDEV_DWT_MASK_0 0xe0001024u +#define CYDEV_DWT_FUNCTION_0 0xe0001028u +#define CYDEV_DWT_COMP_1 0xe0001030u +#define CYDEV_DWT_MASK_1 0xe0001034u +#define CYDEV_DWT_FUNCTION_1 0xe0001038u +#define CYDEV_DWT_COMP_2 0xe0001040u +#define CYDEV_DWT_MASK_2 0xe0001044u +#define CYDEV_DWT_FUNCTION_2 0xe0001048u +#define CYDEV_DWT_COMP_3 0xe0001050u +#define CYDEV_DWT_MASK_3 0xe0001054u +#define CYDEV_DWT_FUNCTION_3 0xe0001058u +#define CYDEV_FPB_BASE 0xe0002000u +#define CYDEV_FPB_SIZE 0x00001000u +#define CYDEV_FPB_CTRL 0xe0002000u +#define CYDEV_FPB_REMAP 0xe0002004u +#define CYDEV_FPB_FP_COMP_0 0xe0002008u +#define CYDEV_FPB_FP_COMP_1 0xe000200cu +#define CYDEV_FPB_FP_COMP_2 0xe0002010u +#define CYDEV_FPB_FP_COMP_3 0xe0002014u +#define CYDEV_FPB_FP_COMP_4 0xe0002018u +#define CYDEV_FPB_FP_COMP_5 0xe000201cu +#define CYDEV_FPB_FP_COMP_6 0xe0002020u +#define CYDEV_FPB_FP_COMP_7 0xe0002024u +#define CYDEV_FPB_PID4 0xe0002fd0u +#define CYDEV_FPB_PID5 0xe0002fd4u +#define CYDEV_FPB_PID6 0xe0002fd8u +#define CYDEV_FPB_PID7 0xe0002fdcu +#define CYDEV_FPB_PID0 0xe0002fe0u +#define CYDEV_FPB_PID1 0xe0002fe4u +#define CYDEV_FPB_PID2 0xe0002fe8u +#define CYDEV_FPB_PID3 0xe0002fecu +#define CYDEV_FPB_CID0 0xe0002ff0u +#define CYDEV_FPB_CID1 0xe0002ff4u +#define CYDEV_FPB_CID2 0xe0002ff8u +#define CYDEV_FPB_CID3 0xe0002ffcu +#define CYDEV_NVIC_BASE 0xe000e000u +#define CYDEV_NVIC_SIZE 0x00000d3cu +#define CYDEV_NVIC_INT_CTL_TYPE 0xe000e004u +#define CYDEV_NVIC_SYSTICK_CTL 0xe000e010u +#define CYDEV_NVIC_SYSTICK_RELOAD 0xe000e014u +#define CYDEV_NVIC_SYSTICK_CURRENT 0xe000e018u +#define CYDEV_NVIC_SYSTICK_CAL 0xe000e01cu +#define CYDEV_NVIC_SETENA0 0xe000e100u +#define CYDEV_NVIC_CLRENA0 0xe000e180u +#define CYDEV_NVIC_SETPEND0 0xe000e200u +#define CYDEV_NVIC_CLRPEND0 0xe000e280u +#define CYDEV_NVIC_ACTIVE0 0xe000e300u +#define CYDEV_NVIC_PRI_0 0xe000e400u +#define CYDEV_NVIC_PRI_1 0xe000e401u +#define CYDEV_NVIC_PRI_2 0xe000e402u +#define CYDEV_NVIC_PRI_3 0xe000e403u +#define CYDEV_NVIC_PRI_4 0xe000e404u +#define CYDEV_NVIC_PRI_5 0xe000e405u +#define CYDEV_NVIC_PRI_6 0xe000e406u +#define CYDEV_NVIC_PRI_7 0xe000e407u +#define CYDEV_NVIC_PRI_8 0xe000e408u +#define CYDEV_NVIC_PRI_9 0xe000e409u +#define CYDEV_NVIC_PRI_10 0xe000e40au +#define CYDEV_NVIC_PRI_11 0xe000e40bu +#define CYDEV_NVIC_PRI_12 0xe000e40cu +#define CYDEV_NVIC_PRI_13 0xe000e40du +#define CYDEV_NVIC_PRI_14 0xe000e40eu +#define CYDEV_NVIC_PRI_15 0xe000e40fu +#define CYDEV_NVIC_PRI_16 0xe000e410u +#define CYDEV_NVIC_PRI_17 0xe000e411u +#define CYDEV_NVIC_PRI_18 0xe000e412u +#define CYDEV_NVIC_PRI_19 0xe000e413u +#define CYDEV_NVIC_PRI_20 0xe000e414u +#define CYDEV_NVIC_PRI_21 0xe000e415u +#define CYDEV_NVIC_PRI_22 0xe000e416u +#define CYDEV_NVIC_PRI_23 0xe000e417u +#define CYDEV_NVIC_PRI_24 0xe000e418u +#define CYDEV_NVIC_PRI_25 0xe000e419u +#define CYDEV_NVIC_PRI_26 0xe000e41au +#define CYDEV_NVIC_PRI_27 0xe000e41bu +#define CYDEV_NVIC_PRI_28 0xe000e41cu +#define CYDEV_NVIC_PRI_29 0xe000e41du +#define CYDEV_NVIC_PRI_30 0xe000e41eu +#define CYDEV_NVIC_PRI_31 0xe000e41fu +#define CYDEV_NVIC_CPUID_BASE 0xe000ed00u +#define CYDEV_NVIC_INTR_CTRL_STATE 0xe000ed04u +#define CYDEV_NVIC_VECT_OFFSET 0xe000ed08u +#define CYDEV_NVIC_APPLN_INTR 0xe000ed0cu +#define CYDEV_NVIC_SYSTEM_CONTROL 0xe000ed10u +#define CYDEV_NVIC_CFG_CONTROL 0xe000ed14u +#define CYDEV_NVIC_SYS_PRIO_HANDLER_4_7 0xe000ed18u +#define CYDEV_NVIC_SYS_PRIO_HANDLER_8_11 0xe000ed1cu +#define CYDEV_NVIC_SYS_PRIO_HANDLER_12_15 0xe000ed20u +#define CYDEV_NVIC_SYS_HANDLER_CSR 0xe000ed24u +#define CYDEV_NVIC_MEMMAN_FAULT_STATUS 0xe000ed28u +#define CYDEV_NVIC_BUS_FAULT_STATUS 0xe000ed29u +#define CYDEV_NVIC_USAGE_FAULT_STATUS 0xe000ed2au +#define CYDEV_NVIC_HARD_FAULT_STATUS 0xe000ed2cu +#define CYDEV_NVIC_DEBUG_FAULT_STATUS 0xe000ed30u +#define CYDEV_NVIC_MEMMAN_FAULT_ADD 0xe000ed34u +#define CYDEV_NVIC_BUS_FAULT_ADD 0xe000ed38u +#define CYDEV_CORE_DBG_BASE 0xe000edf0u +#define CYDEV_CORE_DBG_SIZE 0x00000010u +#define CYDEV_CORE_DBG_DBG_HLT_CS 0xe000edf0u +#define CYDEV_CORE_DBG_DBG_REG_SEL 0xe000edf4u +#define CYDEV_CORE_DBG_DBG_REG_DATA 0xe000edf8u +#define CYDEV_CORE_DBG_EXC_MON_CTL 0xe000edfcu +#define CYDEV_TPIU_BASE 0xe0040000u +#define CYDEV_TPIU_SIZE 0x00001000u +#define CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ 0xe0040000u +#define CYDEV_TPIU_CURRENT_SYNC_PRT_SZ 0xe0040004u +#define CYDEV_TPIU_ASYNC_CLK_PRESCALER 0xe0040010u +#define CYDEV_TPIU_PROTOCOL 0xe00400f0u +#define CYDEV_TPIU_FORM_FLUSH_STAT 0xe0040300u +#define CYDEV_TPIU_FORM_FLUSH_CTRL 0xe0040304u +#define CYDEV_TPIU_TRIGGER 0xe0040ee8u +#define CYDEV_TPIU_ITETMDATA 0xe0040eecu +#define CYDEV_TPIU_ITATBCTR2 0xe0040ef0u +#define CYDEV_TPIU_ITATBCTR0 0xe0040ef8u +#define CYDEV_TPIU_ITITMDATA 0xe0040efcu +#define CYDEV_TPIU_ITCTRL 0xe0040f00u +#define CYDEV_TPIU_DEVID 0xe0040fc8u +#define CYDEV_TPIU_DEVTYPE 0xe0040fccu +#define CYDEV_TPIU_PID4 0xe0040fd0u +#define CYDEV_TPIU_PID5 0xe0040fd4u +#define CYDEV_TPIU_PID6 0xe0040fd8u +#define CYDEV_TPIU_PID7 0xe0040fdcu +#define CYDEV_TPIU_PID0 0xe0040fe0u +#define CYDEV_TPIU_PID1 0xe0040fe4u +#define CYDEV_TPIU_PID2 0xe0040fe8u +#define CYDEV_TPIU_PID3 0xe0040fecu +#define CYDEV_TPIU_CID0 0xe0040ff0u +#define CYDEV_TPIU_CID1 0xe0040ff4u +#define CYDEV_TPIU_CID2 0xe0040ff8u +#define CYDEV_TPIU_CID3 0xe0040ffcu +#define CYDEV_ETM_BASE 0xe0041000u +#define CYDEV_ETM_SIZE 0x00001000u +#define CYDEV_ETM_CTL 0xe0041000u +#define CYDEV_ETM_CFG_CODE 0xe0041004u +#define CYDEV_ETM_TRIG_EVENT 0xe0041008u +#define CYDEV_ETM_STATUS 0xe0041010u +#define CYDEV_ETM_SYS_CFG 0xe0041014u +#define CYDEV_ETM_TRACE_ENB_EVENT 0xe0041020u +#define CYDEV_ETM_TRACE_EN_CTRL1 0xe0041024u +#define CYDEV_ETM_FIFOFULL_LEVEL 0xe004102cu +#define CYDEV_ETM_SYNC_FREQ 0xe00411e0u +#define CYDEV_ETM_ETM_ID 0xe00411e4u +#define CYDEV_ETM_CFG_CODE_EXT 0xe00411e8u +#define CYDEV_ETM_TR_SS_EMBICE_CTRL 0xe00411f0u +#define CYDEV_ETM_CS_TRACE_ID 0xe0041200u +#define CYDEV_ETM_OS_LOCK_ACCESS 0xe0041300u +#define CYDEV_ETM_OS_LOCK_STATUS 0xe0041304u +#define CYDEV_ETM_PDSR 0xe0041314u +#define CYDEV_ETM_ITMISCIN 0xe0041ee0u +#define CYDEV_ETM_ITTRIGOUT 0xe0041ee8u +#define CYDEV_ETM_ITATBCTR2 0xe0041ef0u +#define CYDEV_ETM_ITATBCTR0 0xe0041ef8u +#define CYDEV_ETM_INT_MODE_CTRL 0xe0041f00u +#define CYDEV_ETM_CLM_TAG_SET 0xe0041fa0u +#define CYDEV_ETM_CLM_TAG_CLR 0xe0041fa4u +#define CYDEV_ETM_LOCK_ACCESS 0xe0041fb0u +#define CYDEV_ETM_LOCK_STATUS 0xe0041fb4u +#define CYDEV_ETM_AUTH_STATUS 0xe0041fb8u +#define CYDEV_ETM_DEV_TYPE 0xe0041fccu +#define CYDEV_ETM_PID4 0xe0041fd0u +#define CYDEV_ETM_PID5 0xe0041fd4u +#define CYDEV_ETM_PID6 0xe0041fd8u +#define CYDEV_ETM_PID7 0xe0041fdcu +#define CYDEV_ETM_PID0 0xe0041fe0u +#define CYDEV_ETM_PID1 0xe0041fe4u +#define CYDEV_ETM_PID2 0xe0041fe8u +#define CYDEV_ETM_PID3 0xe0041fecu +#define CYDEV_ETM_CID0 0xe0041ff0u +#define CYDEV_ETM_CID1 0xe0041ff4u +#define CYDEV_ETM_CID2 0xe0041ff8u +#define CYDEV_ETM_CID3 0xe0041ffcu +#define CYDEV_ROM_TABLE_BASE 0xe00ff000u +#define CYDEV_ROM_TABLE_SIZE 0x00001000u +#define CYDEV_ROM_TABLE_NVIC 0xe00ff000u +#define CYDEV_ROM_TABLE_DWT 0xe00ff004u +#define CYDEV_ROM_TABLE_FPB 0xe00ff008u +#define CYDEV_ROM_TABLE_ITM 0xe00ff00cu +#define CYDEV_ROM_TABLE_TPIU 0xe00ff010u +#define CYDEV_ROM_TABLE_ETM 0xe00ff014u +#define CYDEV_ROM_TABLE_END 0xe00ff018u +#define CYDEV_ROM_TABLE_MEMTYPE 0xe00fffccu +#define CYDEV_ROM_TABLE_PID4 0xe00fffd0u +#define CYDEV_ROM_TABLE_PID5 0xe00fffd4u +#define CYDEV_ROM_TABLE_PID6 0xe00fffd8u +#define CYDEV_ROM_TABLE_PID7 0xe00fffdcu +#define CYDEV_ROM_TABLE_PID0 0xe00fffe0u +#define CYDEV_ROM_TABLE_PID1 0xe00fffe4u +#define CYDEV_ROM_TABLE_PID2 0xe00fffe8u +#define CYDEV_ROM_TABLE_PID3 0xe00fffecu +#define CYDEV_ROM_TABLE_CID0 0xe00ffff0u +#define CYDEV_ROM_TABLE_CID1 0xe00ffff4u +#define CYDEV_ROM_TABLE_CID2 0xe00ffff8u +#define CYDEV_ROM_TABLE_CID3 0xe00ffffcu +#define CYDEV_FLS_SIZE CYDEV_FLASH_SIZE +#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE +#define CYDEV_FLS_SECTOR_SIZE 0x00010000u +#define CYDEV_FLS_ROW_SIZE 0x00000100u +#define CYDEV_ECC_SECTOR_SIZE 0x00002000u +#define CYDEV_ECC_ROW_SIZE 0x00000020u +#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400u +#define CYDEV_EEPROM_ROW_SIZE 0x00000010u +#define CYDEV_PERIPH_BASE CYDEV_CLKDIST_BASE +#define CYCLK_LD_DISABLE 0x00000004u +#define CYCLK_LD_SYNC_EN 0x00000002u +#define CYCLK_LD_LOAD 0x00000001u +#define CYCLK_PIPE 0x00000080u +#define CYCLK_SSS 0x00000040u +#define CYCLK_EARLY 0x00000020u +#define CYCLK_DUTY 0x00000010u +#define CYCLK_SYNC 0x00000008u +#define CYCLK_SRC_SEL_CLK_SYNC_D 0 +#define CYCLK_SRC_SEL_SYNC_DIG 0 +#define CYCLK_SRC_SEL_IMO 1 +#define CYCLK_SRC_SEL_XTAL_MHZ 2 +#define CYCLK_SRC_SEL_XTALM 2 +#define CYCLK_SRC_SEL_ILO 3 +#define CYCLK_SRC_SEL_PLL 4 +#define CYCLK_SRC_SEL_XTAL_KHZ 5 +#define CYCLK_SRC_SEL_XTALK 5 +#define CYCLK_SRC_SEL_DSI_G 6 +#define CYCLK_SRC_SEL_DSI_D 7 +#define CYCLK_SRC_SEL_CLK_SYNC_A 0 +#define CYCLK_SRC_SEL_DSI_A 7 +#endif /* CYDEVICE_H */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h new file mode 100755 index 00000000..27a4bffb --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h @@ -0,0 +1,5360 @@ +/******************************************************************************* +* FILENAME: cydevice_trm.h +* +* PSoC Creator 3.0 Component Pack 7 +* +* DESCRIPTION: +* This file provides all of the address values for the entire PSoC device. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#if !defined(CYDEVICE_TRM_H) +#define CYDEVICE_TRM_H +#define CYDEV_FLASH_BASE 0x00000000u +#define CYDEV_FLASH_SIZE 0x00020000u +#define CYREG_FLASH_DATA_MBASE 0x00000000u +#define CYREG_FLASH_DATA_MSIZE 0x00020000u +#define CYDEV_SRAM_BASE 0x1fffc000u +#define CYDEV_SRAM_SIZE 0x00008000u +#define CYREG_SRAM_CODE64K_MBASE 0x1fff8000u +#define CYREG_SRAM_CODE64K_MSIZE 0x00004000u +#define CYREG_SRAM_CODE32K_MBASE 0x1fffc000u +#define CYREG_SRAM_CODE32K_MSIZE 0x00002000u +#define CYREG_SRAM_CODE16K_MBASE 0x1fffe000u +#define CYREG_SRAM_CODE16K_MSIZE 0x00001000u +#define CYREG_SRAM_CODE_MBASE 0x1fffc000u +#define CYREG_SRAM_CODE_MSIZE 0x00004000u +#define CYREG_SRAM_DATA_MBASE 0x20000000u +#define CYREG_SRAM_DATA_MSIZE 0x00004000u +#define CYREG_SRAM_DATA16K_MBASE 0x20001000u +#define CYREG_SRAM_DATA16K_MSIZE 0x00001000u +#define CYREG_SRAM_DATA32K_MBASE 0x20002000u +#define CYREG_SRAM_DATA32K_MSIZE 0x00002000u +#define CYREG_SRAM_DATA64K_MBASE 0x20004000u +#define CYREG_SRAM_DATA64K_MSIZE 0x00004000u +#define CYDEV_DMA_BASE 0x20008000u +#define CYDEV_DMA_SIZE 0x00008000u +#define CYREG_DMA_SRAM64K_MBASE 0x20008000u +#define CYREG_DMA_SRAM64K_MSIZE 0x00004000u +#define CYREG_DMA_SRAM32K_MBASE 0x2000c000u +#define CYREG_DMA_SRAM32K_MSIZE 0x00002000u +#define CYREG_DMA_SRAM16K_MBASE 0x2000e000u +#define CYREG_DMA_SRAM16K_MSIZE 0x00001000u +#define CYREG_DMA_SRAM_MBASE 0x2000f000u +#define CYREG_DMA_SRAM_MSIZE 0x00001000u +#define CYDEV_CLKDIST_BASE 0x40004000u +#define CYDEV_CLKDIST_SIZE 0x00000110u +#define CYREG_CLKDIST_CR 0x40004000u +#define CYREG_CLKDIST_LD 0x40004001u +#define CYREG_CLKDIST_WRK0 0x40004002u +#define CYREG_CLKDIST_WRK1 0x40004003u +#define CYREG_CLKDIST_MSTR0 0x40004004u +#define CYREG_CLKDIST_MSTR1 0x40004005u +#define CYREG_CLKDIST_BCFG0 0x40004006u +#define CYREG_CLKDIST_BCFG1 0x40004007u +#define CYREG_CLKDIST_BCFG2 0x40004008u +#define CYREG_CLKDIST_UCFG 0x40004009u +#define CYREG_CLKDIST_DLY0 0x4000400au +#define CYREG_CLKDIST_DLY1 0x4000400bu +#define CYREG_CLKDIST_DMASK 0x40004010u +#define CYREG_CLKDIST_AMASK 0x40004014u +#define CYDEV_CLKDIST_DCFG0_BASE 0x40004080u +#define CYDEV_CLKDIST_DCFG0_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG0_CFG0 0x40004080u +#define CYREG_CLKDIST_DCFG0_CFG1 0x40004081u +#define CYREG_CLKDIST_DCFG0_CFG2 0x40004082u +#define CYDEV_CLKDIST_DCFG1_BASE 0x40004084u +#define CYDEV_CLKDIST_DCFG1_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG1_CFG0 0x40004084u +#define CYREG_CLKDIST_DCFG1_CFG1 0x40004085u +#define CYREG_CLKDIST_DCFG1_CFG2 0x40004086u +#define CYDEV_CLKDIST_DCFG2_BASE 0x40004088u +#define CYDEV_CLKDIST_DCFG2_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG2_CFG0 0x40004088u +#define CYREG_CLKDIST_DCFG2_CFG1 0x40004089u +#define CYREG_CLKDIST_DCFG2_CFG2 0x4000408au +#define CYDEV_CLKDIST_DCFG3_BASE 0x4000408cu +#define CYDEV_CLKDIST_DCFG3_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG3_CFG0 0x4000408cu +#define CYREG_CLKDIST_DCFG3_CFG1 0x4000408du +#define CYREG_CLKDIST_DCFG3_CFG2 0x4000408eu +#define CYDEV_CLKDIST_DCFG4_BASE 0x40004090u +#define CYDEV_CLKDIST_DCFG4_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG4_CFG0 0x40004090u +#define CYREG_CLKDIST_DCFG4_CFG1 0x40004091u +#define CYREG_CLKDIST_DCFG4_CFG2 0x40004092u +#define CYDEV_CLKDIST_DCFG5_BASE 0x40004094u +#define CYDEV_CLKDIST_DCFG5_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG5_CFG0 0x40004094u +#define CYREG_CLKDIST_DCFG5_CFG1 0x40004095u +#define CYREG_CLKDIST_DCFG5_CFG2 0x40004096u +#define CYDEV_CLKDIST_DCFG6_BASE 0x40004098u +#define CYDEV_CLKDIST_DCFG6_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG6_CFG0 0x40004098u +#define CYREG_CLKDIST_DCFG6_CFG1 0x40004099u +#define CYREG_CLKDIST_DCFG6_CFG2 0x4000409au +#define CYDEV_CLKDIST_DCFG7_BASE 0x4000409cu +#define CYDEV_CLKDIST_DCFG7_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG7_CFG0 0x4000409cu +#define CYREG_CLKDIST_DCFG7_CFG1 0x4000409du +#define CYREG_CLKDIST_DCFG7_CFG2 0x4000409eu +#define CYDEV_CLKDIST_ACFG0_BASE 0x40004100u +#define CYDEV_CLKDIST_ACFG0_SIZE 0x00000004u +#define CYREG_CLKDIST_ACFG0_CFG0 0x40004100u +#define CYREG_CLKDIST_ACFG0_CFG1 0x40004101u +#define CYREG_CLKDIST_ACFG0_CFG2 0x40004102u +#define CYREG_CLKDIST_ACFG0_CFG3 0x40004103u +#define CYDEV_CLKDIST_ACFG1_BASE 0x40004104u +#define CYDEV_CLKDIST_ACFG1_SIZE 0x00000004u +#define CYREG_CLKDIST_ACFG1_CFG0 0x40004104u +#define CYREG_CLKDIST_ACFG1_CFG1 0x40004105u +#define CYREG_CLKDIST_ACFG1_CFG2 0x40004106u +#define CYREG_CLKDIST_ACFG1_CFG3 0x40004107u +#define CYDEV_CLKDIST_ACFG2_BASE 0x40004108u +#define CYDEV_CLKDIST_ACFG2_SIZE 0x00000004u +#define CYREG_CLKDIST_ACFG2_CFG0 0x40004108u +#define CYREG_CLKDIST_ACFG2_CFG1 0x40004109u +#define CYREG_CLKDIST_ACFG2_CFG2 0x4000410au +#define CYREG_CLKDIST_ACFG2_CFG3 0x4000410bu +#define CYDEV_CLKDIST_ACFG3_BASE 0x4000410cu +#define CYDEV_CLKDIST_ACFG3_SIZE 0x00000004u +#define CYREG_CLKDIST_ACFG3_CFG0 0x4000410cu +#define CYREG_CLKDIST_ACFG3_CFG1 0x4000410du +#define CYREG_CLKDIST_ACFG3_CFG2 0x4000410eu +#define CYREG_CLKDIST_ACFG3_CFG3 0x4000410fu +#define CYDEV_FASTCLK_BASE 0x40004200u +#define CYDEV_FASTCLK_SIZE 0x00000026u +#define CYDEV_FASTCLK_IMO_BASE 0x40004200u +#define CYDEV_FASTCLK_IMO_SIZE 0x00000001u +#define CYREG_FASTCLK_IMO_CR 0x40004200u +#define CYDEV_FASTCLK_XMHZ_BASE 0x40004210u +#define CYDEV_FASTCLK_XMHZ_SIZE 0x00000004u +#define CYREG_FASTCLK_XMHZ_CSR 0x40004210u +#define CYREG_FASTCLK_XMHZ_CFG0 0x40004212u +#define CYREG_FASTCLK_XMHZ_CFG1 0x40004213u +#define CYDEV_FASTCLK_PLL_BASE 0x40004220u +#define CYDEV_FASTCLK_PLL_SIZE 0x00000006u +#define CYREG_FASTCLK_PLL_CFG0 0x40004220u +#define CYREG_FASTCLK_PLL_CFG1 0x40004221u +#define CYREG_FASTCLK_PLL_P 0x40004222u +#define CYREG_FASTCLK_PLL_Q 0x40004223u +#define CYREG_FASTCLK_PLL_SR 0x40004225u +#define CYDEV_SLOWCLK_BASE 0x40004300u +#define CYDEV_SLOWCLK_SIZE 0x0000000bu +#define CYDEV_SLOWCLK_ILO_BASE 0x40004300u +#define CYDEV_SLOWCLK_ILO_SIZE 0x00000002u +#define CYREG_SLOWCLK_ILO_CR0 0x40004300u +#define CYREG_SLOWCLK_ILO_CR1 0x40004301u +#define CYDEV_SLOWCLK_X32_BASE 0x40004308u +#define CYDEV_SLOWCLK_X32_SIZE 0x00000003u +#define CYREG_SLOWCLK_X32_CR 0x40004308u +#define CYREG_SLOWCLK_X32_CFG 0x40004309u +#define CYREG_SLOWCLK_X32_TST 0x4000430au +#define CYDEV_BOOST_BASE 0x40004320u +#define CYDEV_BOOST_SIZE 0x00000007u +#define CYREG_BOOST_CR0 0x40004320u +#define CYREG_BOOST_CR1 0x40004321u +#define CYREG_BOOST_CR2 0x40004322u +#define CYREG_BOOST_CR3 0x40004323u +#define CYREG_BOOST_SR 0x40004324u +#define CYREG_BOOST_CR4 0x40004325u +#define CYREG_BOOST_SR2 0x40004326u +#define CYDEV_PWRSYS_BASE 0x40004330u +#define CYDEV_PWRSYS_SIZE 0x00000002u +#define CYREG_PWRSYS_CR0 0x40004330u +#define CYREG_PWRSYS_CR1 0x40004331u +#define CYDEV_PM_BASE 0x40004380u +#define CYDEV_PM_SIZE 0x00000057u +#define CYREG_PM_TW_CFG0 0x40004380u +#define CYREG_PM_TW_CFG1 0x40004381u +#define CYREG_PM_TW_CFG2 0x40004382u +#define CYREG_PM_WDT_CFG 0x40004383u +#define CYREG_PM_WDT_CR 0x40004384u +#define CYREG_PM_INT_SR 0x40004390u +#define CYREG_PM_MODE_CFG0 0x40004391u +#define CYREG_PM_MODE_CFG1 0x40004392u +#define CYREG_PM_MODE_CSR 0x40004393u +#define CYREG_PM_USB_CR0 0x40004394u +#define CYREG_PM_WAKEUP_CFG0 0x40004398u +#define CYREG_PM_WAKEUP_CFG1 0x40004399u +#define CYREG_PM_WAKEUP_CFG2 0x4000439au +#define CYDEV_PM_ACT_BASE 0x400043a0u +#define CYDEV_PM_ACT_SIZE 0x0000000eu +#define CYREG_PM_ACT_CFG0 0x400043a0u +#define CYREG_PM_ACT_CFG1 0x400043a1u +#define CYREG_PM_ACT_CFG2 0x400043a2u +#define CYREG_PM_ACT_CFG3 0x400043a3u +#define CYREG_PM_ACT_CFG4 0x400043a4u +#define CYREG_PM_ACT_CFG5 0x400043a5u +#define CYREG_PM_ACT_CFG6 0x400043a6u +#define CYREG_PM_ACT_CFG7 0x400043a7u +#define CYREG_PM_ACT_CFG8 0x400043a8u +#define CYREG_PM_ACT_CFG9 0x400043a9u +#define CYREG_PM_ACT_CFG10 0x400043aau +#define CYREG_PM_ACT_CFG11 0x400043abu +#define CYREG_PM_ACT_CFG12 0x400043acu +#define CYREG_PM_ACT_CFG13 0x400043adu +#define CYDEV_PM_STBY_BASE 0x400043b0u +#define CYDEV_PM_STBY_SIZE 0x0000000eu +#define CYREG_PM_STBY_CFG0 0x400043b0u +#define CYREG_PM_STBY_CFG1 0x400043b1u +#define CYREG_PM_STBY_CFG2 0x400043b2u +#define CYREG_PM_STBY_CFG3 0x400043b3u +#define CYREG_PM_STBY_CFG4 0x400043b4u +#define CYREG_PM_STBY_CFG5 0x400043b5u +#define CYREG_PM_STBY_CFG6 0x400043b6u +#define CYREG_PM_STBY_CFG7 0x400043b7u +#define CYREG_PM_STBY_CFG8 0x400043b8u +#define CYREG_PM_STBY_CFG9 0x400043b9u +#define CYREG_PM_STBY_CFG10 0x400043bau +#define CYREG_PM_STBY_CFG11 0x400043bbu +#define CYREG_PM_STBY_CFG12 0x400043bcu +#define CYREG_PM_STBY_CFG13 0x400043bdu +#define CYDEV_PM_AVAIL_BASE 0x400043c0u +#define CYDEV_PM_AVAIL_SIZE 0x00000017u +#define CYREG_PM_AVAIL_CR0 0x400043c0u +#define CYREG_PM_AVAIL_CR1 0x400043c1u +#define CYREG_PM_AVAIL_CR2 0x400043c2u +#define CYREG_PM_AVAIL_CR3 0x400043c3u +#define CYREG_PM_AVAIL_CR4 0x400043c4u +#define CYREG_PM_AVAIL_CR5 0x400043c5u +#define CYREG_PM_AVAIL_CR6 0x400043c6u +#define CYREG_PM_AVAIL_SR0 0x400043d0u +#define CYREG_PM_AVAIL_SR1 0x400043d1u +#define CYREG_PM_AVAIL_SR2 0x400043d2u +#define CYREG_PM_AVAIL_SR3 0x400043d3u +#define CYREG_PM_AVAIL_SR4 0x400043d4u +#define CYREG_PM_AVAIL_SR5 0x400043d5u +#define CYREG_PM_AVAIL_SR6 0x400043d6u +#define CYDEV_PICU_BASE 0x40004500u +#define CYDEV_PICU_SIZE 0x000000b0u +#define CYDEV_PICU_INTTYPE_BASE 0x40004500u +#define CYDEV_PICU_INTTYPE_SIZE 0x00000080u +#define CYDEV_PICU_INTTYPE_PICU0_BASE 0x40004500u +#define CYDEV_PICU_INTTYPE_PICU0_SIZE 0x00000008u +#define CYREG_PICU0_INTTYPE0 0x40004500u +#define CYREG_PICU0_INTTYPE1 0x40004501u +#define CYREG_PICU0_INTTYPE2 0x40004502u +#define CYREG_PICU0_INTTYPE3 0x40004503u +#define CYREG_PICU0_INTTYPE4 0x40004504u +#define CYREG_PICU0_INTTYPE5 0x40004505u +#define CYREG_PICU0_INTTYPE6 0x40004506u +#define CYREG_PICU0_INTTYPE7 0x40004507u +#define CYDEV_PICU_INTTYPE_PICU1_BASE 0x40004508u +#define CYDEV_PICU_INTTYPE_PICU1_SIZE 0x00000008u +#define CYREG_PICU1_INTTYPE0 0x40004508u +#define CYREG_PICU1_INTTYPE1 0x40004509u +#define CYREG_PICU1_INTTYPE2 0x4000450au +#define CYREG_PICU1_INTTYPE3 0x4000450bu +#define CYREG_PICU1_INTTYPE4 0x4000450cu +#define CYREG_PICU1_INTTYPE5 0x4000450du +#define CYREG_PICU1_INTTYPE6 0x4000450eu +#define CYREG_PICU1_INTTYPE7 0x4000450fu +#define CYDEV_PICU_INTTYPE_PICU2_BASE 0x40004510u +#define CYDEV_PICU_INTTYPE_PICU2_SIZE 0x00000008u +#define CYREG_PICU2_INTTYPE0 0x40004510u +#define CYREG_PICU2_INTTYPE1 0x40004511u +#define CYREG_PICU2_INTTYPE2 0x40004512u +#define CYREG_PICU2_INTTYPE3 0x40004513u +#define CYREG_PICU2_INTTYPE4 0x40004514u +#define CYREG_PICU2_INTTYPE5 0x40004515u +#define CYREG_PICU2_INTTYPE6 0x40004516u +#define CYREG_PICU2_INTTYPE7 0x40004517u +#define CYDEV_PICU_INTTYPE_PICU3_BASE 0x40004518u +#define CYDEV_PICU_INTTYPE_PICU3_SIZE 0x00000008u +#define CYREG_PICU3_INTTYPE0 0x40004518u +#define CYREG_PICU3_INTTYPE1 0x40004519u +#define CYREG_PICU3_INTTYPE2 0x4000451au +#define CYREG_PICU3_INTTYPE3 0x4000451bu +#define CYREG_PICU3_INTTYPE4 0x4000451cu +#define CYREG_PICU3_INTTYPE5 0x4000451du +#define CYREG_PICU3_INTTYPE6 0x4000451eu +#define CYREG_PICU3_INTTYPE7 0x4000451fu +#define CYDEV_PICU_INTTYPE_PICU4_BASE 0x40004520u +#define CYDEV_PICU_INTTYPE_PICU4_SIZE 0x00000008u +#define CYREG_PICU4_INTTYPE0 0x40004520u +#define CYREG_PICU4_INTTYPE1 0x40004521u +#define CYREG_PICU4_INTTYPE2 0x40004522u +#define CYREG_PICU4_INTTYPE3 0x40004523u +#define CYREG_PICU4_INTTYPE4 0x40004524u +#define CYREG_PICU4_INTTYPE5 0x40004525u +#define CYREG_PICU4_INTTYPE6 0x40004526u +#define CYREG_PICU4_INTTYPE7 0x40004527u +#define CYDEV_PICU_INTTYPE_PICU5_BASE 0x40004528u +#define CYDEV_PICU_INTTYPE_PICU5_SIZE 0x00000008u +#define CYREG_PICU5_INTTYPE0 0x40004528u +#define CYREG_PICU5_INTTYPE1 0x40004529u +#define CYREG_PICU5_INTTYPE2 0x4000452au +#define CYREG_PICU5_INTTYPE3 0x4000452bu +#define CYREG_PICU5_INTTYPE4 0x4000452cu +#define CYREG_PICU5_INTTYPE5 0x4000452du +#define CYREG_PICU5_INTTYPE6 0x4000452eu +#define CYREG_PICU5_INTTYPE7 0x4000452fu +#define CYDEV_PICU_INTTYPE_PICU6_BASE 0x40004530u +#define CYDEV_PICU_INTTYPE_PICU6_SIZE 0x00000008u +#define CYREG_PICU6_INTTYPE0 0x40004530u +#define CYREG_PICU6_INTTYPE1 0x40004531u +#define CYREG_PICU6_INTTYPE2 0x40004532u +#define CYREG_PICU6_INTTYPE3 0x40004533u +#define CYREG_PICU6_INTTYPE4 0x40004534u +#define CYREG_PICU6_INTTYPE5 0x40004535u +#define CYREG_PICU6_INTTYPE6 0x40004536u +#define CYREG_PICU6_INTTYPE7 0x40004537u +#define CYDEV_PICU_INTTYPE_PICU12_BASE 0x40004560u +#define CYDEV_PICU_INTTYPE_PICU12_SIZE 0x00000008u +#define CYREG_PICU12_INTTYPE0 0x40004560u +#define CYREG_PICU12_INTTYPE1 0x40004561u +#define CYREG_PICU12_INTTYPE2 0x40004562u +#define CYREG_PICU12_INTTYPE3 0x40004563u +#define CYREG_PICU12_INTTYPE4 0x40004564u +#define CYREG_PICU12_INTTYPE5 0x40004565u +#define CYREG_PICU12_INTTYPE6 0x40004566u +#define CYREG_PICU12_INTTYPE7 0x40004567u +#define CYDEV_PICU_INTTYPE_PICU15_BASE 0x40004578u +#define CYDEV_PICU_INTTYPE_PICU15_SIZE 0x00000008u +#define CYREG_PICU15_INTTYPE0 0x40004578u +#define CYREG_PICU15_INTTYPE1 0x40004579u +#define CYREG_PICU15_INTTYPE2 0x4000457au +#define CYREG_PICU15_INTTYPE3 0x4000457bu +#define CYREG_PICU15_INTTYPE4 0x4000457cu +#define CYREG_PICU15_INTTYPE5 0x4000457du +#define CYREG_PICU15_INTTYPE6 0x4000457eu +#define CYREG_PICU15_INTTYPE7 0x4000457fu +#define CYDEV_PICU_STAT_BASE 0x40004580u +#define CYDEV_PICU_STAT_SIZE 0x00000010u +#define CYDEV_PICU_STAT_PICU0_BASE 0x40004580u +#define CYDEV_PICU_STAT_PICU0_SIZE 0x00000001u +#define CYREG_PICU0_INTSTAT 0x40004580u +#define CYDEV_PICU_STAT_PICU1_BASE 0x40004581u +#define CYDEV_PICU_STAT_PICU1_SIZE 0x00000001u +#define CYREG_PICU1_INTSTAT 0x40004581u +#define CYDEV_PICU_STAT_PICU2_BASE 0x40004582u +#define CYDEV_PICU_STAT_PICU2_SIZE 0x00000001u +#define CYREG_PICU2_INTSTAT 0x40004582u +#define CYDEV_PICU_STAT_PICU3_BASE 0x40004583u +#define CYDEV_PICU_STAT_PICU3_SIZE 0x00000001u +#define CYREG_PICU3_INTSTAT 0x40004583u +#define CYDEV_PICU_STAT_PICU4_BASE 0x40004584u +#define CYDEV_PICU_STAT_PICU4_SIZE 0x00000001u +#define CYREG_PICU4_INTSTAT 0x40004584u +#define CYDEV_PICU_STAT_PICU5_BASE 0x40004585u +#define CYDEV_PICU_STAT_PICU5_SIZE 0x00000001u +#define CYREG_PICU5_INTSTAT 0x40004585u +#define CYDEV_PICU_STAT_PICU6_BASE 0x40004586u +#define CYDEV_PICU_STAT_PICU6_SIZE 0x00000001u +#define CYREG_PICU6_INTSTAT 0x40004586u +#define CYDEV_PICU_STAT_PICU12_BASE 0x4000458cu +#define CYDEV_PICU_STAT_PICU12_SIZE 0x00000001u +#define CYREG_PICU12_INTSTAT 0x4000458cu +#define CYDEV_PICU_STAT_PICU15_BASE 0x4000458fu +#define CYDEV_PICU_STAT_PICU15_SIZE 0x00000001u +#define CYREG_PICU15_INTSTAT 0x4000458fu +#define CYDEV_PICU_SNAP_BASE 0x40004590u +#define CYDEV_PICU_SNAP_SIZE 0x00000010u +#define CYDEV_PICU_SNAP_PICU0_BASE 0x40004590u +#define CYDEV_PICU_SNAP_PICU0_SIZE 0x00000001u +#define CYREG_PICU0_SNAP 0x40004590u +#define CYDEV_PICU_SNAP_PICU1_BASE 0x40004591u +#define CYDEV_PICU_SNAP_PICU1_SIZE 0x00000001u +#define CYREG_PICU1_SNAP 0x40004591u +#define CYDEV_PICU_SNAP_PICU2_BASE 0x40004592u +#define CYDEV_PICU_SNAP_PICU2_SIZE 0x00000001u +#define CYREG_PICU2_SNAP 0x40004592u +#define CYDEV_PICU_SNAP_PICU3_BASE 0x40004593u +#define CYDEV_PICU_SNAP_PICU3_SIZE 0x00000001u +#define CYREG_PICU3_SNAP 0x40004593u +#define CYDEV_PICU_SNAP_PICU4_BASE 0x40004594u +#define CYDEV_PICU_SNAP_PICU4_SIZE 0x00000001u +#define CYREG_PICU4_SNAP 0x40004594u +#define CYDEV_PICU_SNAP_PICU5_BASE 0x40004595u +#define CYDEV_PICU_SNAP_PICU5_SIZE 0x00000001u +#define CYREG_PICU5_SNAP 0x40004595u +#define CYDEV_PICU_SNAP_PICU6_BASE 0x40004596u +#define CYDEV_PICU_SNAP_PICU6_SIZE 0x00000001u +#define CYREG_PICU6_SNAP 0x40004596u +#define CYDEV_PICU_SNAP_PICU12_BASE 0x4000459cu +#define CYDEV_PICU_SNAP_PICU12_SIZE 0x00000001u +#define CYREG_PICU12_SNAP 0x4000459cu +#define CYDEV_PICU_SNAP_PICU_15_BASE 0x4000459fu +#define CYDEV_PICU_SNAP_PICU_15_SIZE 0x00000001u +#define CYREG_PICU_15_SNAP_15 0x4000459fu +#define CYDEV_PICU_DISABLE_COR_BASE 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_SIZE 0x00000010u +#define CYDEV_PICU_DISABLE_COR_PICU0_BASE 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_PICU0_SIZE 0x00000001u +#define CYREG_PICU0_DISABLE_COR 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_PICU1_BASE 0x400045a1u +#define CYDEV_PICU_DISABLE_COR_PICU1_SIZE 0x00000001u +#define CYREG_PICU1_DISABLE_COR 0x400045a1u +#define CYDEV_PICU_DISABLE_COR_PICU2_BASE 0x400045a2u +#define CYDEV_PICU_DISABLE_COR_PICU2_SIZE 0x00000001u +#define CYREG_PICU2_DISABLE_COR 0x400045a2u +#define CYDEV_PICU_DISABLE_COR_PICU3_BASE 0x400045a3u +#define CYDEV_PICU_DISABLE_COR_PICU3_SIZE 0x00000001u +#define CYREG_PICU3_DISABLE_COR 0x400045a3u +#define CYDEV_PICU_DISABLE_COR_PICU4_BASE 0x400045a4u +#define CYDEV_PICU_DISABLE_COR_PICU4_SIZE 0x00000001u +#define CYREG_PICU4_DISABLE_COR 0x400045a4u +#define CYDEV_PICU_DISABLE_COR_PICU5_BASE 0x400045a5u +#define CYDEV_PICU_DISABLE_COR_PICU5_SIZE 0x00000001u +#define CYREG_PICU5_DISABLE_COR 0x400045a5u +#define CYDEV_PICU_DISABLE_COR_PICU6_BASE 0x400045a6u +#define CYDEV_PICU_DISABLE_COR_PICU6_SIZE 0x00000001u +#define CYREG_PICU6_DISABLE_COR 0x400045a6u +#define CYDEV_PICU_DISABLE_COR_PICU12_BASE 0x400045acu +#define CYDEV_PICU_DISABLE_COR_PICU12_SIZE 0x00000001u +#define CYREG_PICU12_DISABLE_COR 0x400045acu +#define CYDEV_PICU_DISABLE_COR_PICU15_BASE 0x400045afu +#define CYDEV_PICU_DISABLE_COR_PICU15_SIZE 0x00000001u +#define CYREG_PICU15_DISABLE_COR 0x400045afu +#define CYDEV_MFGCFG_BASE 0x40004600u +#define CYDEV_MFGCFG_SIZE 0x000000edu +#define CYDEV_MFGCFG_ANAIF_BASE 0x40004600u +#define CYDEV_MFGCFG_ANAIF_SIZE 0x00000038u +#define CYDEV_MFGCFG_ANAIF_DAC0_BASE 0x40004608u +#define CYDEV_MFGCFG_ANAIF_DAC0_SIZE 0x00000001u +#define CYREG_DAC0_TR 0x40004608u +#define CYDEV_MFGCFG_ANAIF_DAC1_BASE 0x40004609u +#define CYDEV_MFGCFG_ANAIF_DAC1_SIZE 0x00000001u +#define CYREG_DAC1_TR 0x40004609u +#define CYDEV_MFGCFG_ANAIF_DAC2_BASE 0x4000460au +#define CYDEV_MFGCFG_ANAIF_DAC2_SIZE 0x00000001u +#define CYREG_DAC2_TR 0x4000460au +#define CYDEV_MFGCFG_ANAIF_DAC3_BASE 0x4000460bu +#define CYDEV_MFGCFG_ANAIF_DAC3_SIZE 0x00000001u +#define CYREG_DAC3_TR 0x4000460bu +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE 0x40004610u +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE 0x00000001u +#define CYREG_NPUMP_DSM_TR0 0x40004610u +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE 0x40004611u +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE 0x00000001u +#define CYREG_NPUMP_SC_TR0 0x40004611u +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE 0x40004612u +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE 0x00000001u +#define CYREG_NPUMP_OPAMP_TR0 0x40004612u +#define CYDEV_MFGCFG_ANAIF_SAR0_BASE 0x40004614u +#define CYDEV_MFGCFG_ANAIF_SAR0_SIZE 0x00000001u +#define CYREG_SAR0_TR0 0x40004614u +#define CYDEV_MFGCFG_ANAIF_SAR1_BASE 0x40004616u +#define CYDEV_MFGCFG_ANAIF_SAR1_SIZE 0x00000001u +#define CYREG_SAR1_TR0 0x40004616u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_BASE 0x40004620u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE 0x00000002u +#define CYREG_OPAMP0_TR0 0x40004620u +#define CYREG_OPAMP0_TR1 0x40004621u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_BASE 0x40004622u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE 0x00000002u +#define CYREG_OPAMP1_TR0 0x40004622u +#define CYREG_OPAMP1_TR1 0x40004623u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_BASE 0x40004624u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE 0x00000002u +#define CYREG_OPAMP2_TR0 0x40004624u +#define CYREG_OPAMP2_TR1 0x40004625u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_BASE 0x40004626u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE 0x00000002u +#define CYREG_OPAMP3_TR0 0x40004626u +#define CYREG_OPAMP3_TR1 0x40004627u +#define CYDEV_MFGCFG_ANAIF_CMP0_BASE 0x40004630u +#define CYDEV_MFGCFG_ANAIF_CMP0_SIZE 0x00000002u +#define CYREG_CMP0_TR0 0x40004630u +#define CYREG_CMP0_TR1 0x40004631u +#define CYDEV_MFGCFG_ANAIF_CMP1_BASE 0x40004632u +#define CYDEV_MFGCFG_ANAIF_CMP1_SIZE 0x00000002u +#define CYREG_CMP1_TR0 0x40004632u +#define CYREG_CMP1_TR1 0x40004633u +#define CYDEV_MFGCFG_ANAIF_CMP2_BASE 0x40004634u +#define CYDEV_MFGCFG_ANAIF_CMP2_SIZE 0x00000002u +#define CYREG_CMP2_TR0 0x40004634u +#define CYREG_CMP2_TR1 0x40004635u +#define CYDEV_MFGCFG_ANAIF_CMP3_BASE 0x40004636u +#define CYDEV_MFGCFG_ANAIF_CMP3_SIZE 0x00000002u +#define CYREG_CMP3_TR0 0x40004636u +#define CYREG_CMP3_TR1 0x40004637u +#define CYDEV_MFGCFG_PWRSYS_BASE 0x40004680u +#define CYDEV_MFGCFG_PWRSYS_SIZE 0x0000000bu +#define CYREG_PWRSYS_HIB_TR0 0x40004680u +#define CYREG_PWRSYS_HIB_TR1 0x40004681u +#define CYREG_PWRSYS_I2C_TR 0x40004682u +#define CYREG_PWRSYS_SLP_TR 0x40004683u +#define CYREG_PWRSYS_BUZZ_TR 0x40004684u +#define CYREG_PWRSYS_WAKE_TR0 0x40004685u +#define CYREG_PWRSYS_WAKE_TR1 0x40004686u +#define CYREG_PWRSYS_BREF_TR 0x40004687u +#define CYREG_PWRSYS_BG_TR 0x40004688u +#define CYREG_PWRSYS_WAKE_TR2 0x40004689u +#define CYREG_PWRSYS_WAKE_TR3 0x4000468au +#define CYDEV_MFGCFG_ILO_BASE 0x40004690u +#define CYDEV_MFGCFG_ILO_SIZE 0x00000002u +#define CYREG_ILO_TR0 0x40004690u +#define CYREG_ILO_TR1 0x40004691u +#define CYDEV_MFGCFG_X32_BASE 0x40004698u +#define CYDEV_MFGCFG_X32_SIZE 0x00000001u +#define CYREG_X32_TR 0x40004698u +#define CYDEV_MFGCFG_IMO_BASE 0x400046a0u +#define CYDEV_MFGCFG_IMO_SIZE 0x00000005u +#define CYREG_IMO_TR0 0x400046a0u +#define CYREG_IMO_TR1 0x400046a1u +#define CYREG_IMO_GAIN 0x400046a2u +#define CYREG_IMO_C36M 0x400046a3u +#define CYREG_IMO_TR2 0x400046a4u +#define CYDEV_MFGCFG_XMHZ_BASE 0x400046a8u +#define CYDEV_MFGCFG_XMHZ_SIZE 0x00000001u +#define CYREG_XMHZ_TR 0x400046a8u +#define CYREG_MFGCFG_DLY 0x400046c0u +#define CYDEV_MFGCFG_MLOGIC_BASE 0x400046e0u +#define CYDEV_MFGCFG_MLOGIC_SIZE 0x0000000du +#define CYREG_MLOGIC_DMPSTR 0x400046e2u +#define CYDEV_MFGCFG_MLOGIC_SEG_BASE 0x400046e4u +#define CYDEV_MFGCFG_MLOGIC_SEG_SIZE 0x00000002u +#define CYREG_MLOGIC_SEG_CR 0x400046e4u +#define CYREG_MLOGIC_SEG_CFG0 0x400046e5u +#define CYREG_MLOGIC_DEBUG 0x400046e8u +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE 0x400046eau +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE 0x00000001u +#define CYREG_MLOGIC_CPU_SCR_CPU_SCR 0x400046eau +#define CYREG_MLOGIC_REV_ID 0x400046ecu +#define CYDEV_RESET_BASE 0x400046f0u +#define CYDEV_RESET_SIZE 0x0000000fu +#define CYREG_RESET_IPOR_CR0 0x400046f0u +#define CYREG_RESET_IPOR_CR1 0x400046f1u +#define CYREG_RESET_IPOR_CR2 0x400046f2u +#define CYREG_RESET_IPOR_CR3 0x400046f3u +#define CYREG_RESET_CR0 0x400046f4u +#define CYREG_RESET_CR1 0x400046f5u +#define CYREG_RESET_CR2 0x400046f6u +#define CYREG_RESET_CR3 0x400046f7u +#define CYREG_RESET_CR4 0x400046f8u +#define CYREG_RESET_CR5 0x400046f9u +#define CYREG_RESET_SR0 0x400046fau +#define CYREG_RESET_SR1 0x400046fbu +#define CYREG_RESET_SR2 0x400046fcu +#define CYREG_RESET_SR3 0x400046fdu +#define CYREG_RESET_TR 0x400046feu +#define CYDEV_SPC_BASE 0x40004700u +#define CYDEV_SPC_SIZE 0x00000100u +#define CYREG_SPC_FM_EE_CR 0x40004700u +#define CYREG_SPC_FM_EE_WAKE_CNT 0x40004701u +#define CYREG_SPC_EE_SCR 0x40004702u +#define CYREG_SPC_EE_ERR 0x40004703u +#define CYREG_SPC_CPU_DATA 0x40004720u +#define CYREG_SPC_DMA_DATA 0x40004721u +#define CYREG_SPC_SR 0x40004722u +#define CYREG_SPC_CR 0x40004723u +#define CYDEV_SPC_DMM_MAP_BASE 0x40004780u +#define CYDEV_SPC_DMM_MAP_SIZE 0x00000080u +#define CYREG_SPC_DMM_MAP_SRAM_MBASE 0x40004780u +#define CYREG_SPC_DMM_MAP_SRAM_MSIZE 0x00000080u +#define CYDEV_CACHE_BASE 0x40004800u +#define CYDEV_CACHE_SIZE 0x0000009cu +#define CYREG_CACHE_CC_CTL 0x40004800u +#define CYREG_CACHE_ECC_CORR 0x40004880u +#define CYREG_CACHE_ECC_ERR 0x40004888u +#define CYREG_CACHE_FLASH_ERR 0x40004890u +#define CYREG_CACHE_HITMISS 0x40004898u +#define CYDEV_I2C_BASE 0x40004900u +#define CYDEV_I2C_SIZE 0x000000e1u +#define CYREG_I2C_XCFG 0x400049c8u +#define CYREG_I2C_ADR 0x400049cau +#define CYREG_I2C_CFG 0x400049d6u +#define CYREG_I2C_CSR 0x400049d7u +#define CYREG_I2C_D 0x400049d8u +#define CYREG_I2C_MCSR 0x400049d9u +#define CYREG_I2C_CLK_DIV1 0x400049dbu +#define CYREG_I2C_CLK_DIV2 0x400049dcu +#define CYREG_I2C_TMOUT_CSR 0x400049ddu +#define CYREG_I2C_TMOUT_SR 0x400049deu +#define CYREG_I2C_TMOUT_CFG0 0x400049dfu +#define CYREG_I2C_TMOUT_CFG1 0x400049e0u +#define CYDEV_DEC_BASE 0x40004e00u +#define CYDEV_DEC_SIZE 0x00000015u +#define CYREG_DEC_CR 0x40004e00u +#define CYREG_DEC_SR 0x40004e01u +#define CYREG_DEC_SHIFT1 0x40004e02u +#define CYREG_DEC_SHIFT2 0x40004e03u +#define CYREG_DEC_DR2 0x40004e04u +#define CYREG_DEC_DR2H 0x40004e05u +#define CYREG_DEC_DR1 0x40004e06u +#define CYREG_DEC_OCOR 0x40004e08u +#define CYREG_DEC_OCORM 0x40004e09u +#define CYREG_DEC_OCORH 0x40004e0au +#define CYREG_DEC_GCOR 0x40004e0cu +#define CYREG_DEC_GCORH 0x40004e0du +#define CYREG_DEC_GVAL 0x40004e0eu +#define CYREG_DEC_OUTSAMP 0x40004e10u +#define CYREG_DEC_OUTSAMPM 0x40004e11u +#define CYREG_DEC_OUTSAMPH 0x40004e12u +#define CYREG_DEC_OUTSAMPS 0x40004e13u +#define CYREG_DEC_COHER 0x40004e14u +#define CYDEV_TMR0_BASE 0x40004f00u +#define CYDEV_TMR0_SIZE 0x0000000cu +#define CYREG_TMR0_CFG0 0x40004f00u +#define CYREG_TMR0_CFG1 0x40004f01u +#define CYREG_TMR0_CFG2 0x40004f02u +#define CYREG_TMR0_SR0 0x40004f03u +#define CYREG_TMR0_PER0 0x40004f04u +#define CYREG_TMR0_PER1 0x40004f05u +#define CYREG_TMR0_CNT_CMP0 0x40004f06u +#define CYREG_TMR0_CNT_CMP1 0x40004f07u +#define CYREG_TMR0_CAP0 0x40004f08u +#define CYREG_TMR0_CAP1 0x40004f09u +#define CYREG_TMR0_RT0 0x40004f0au +#define CYREG_TMR0_RT1 0x40004f0bu +#define CYDEV_TMR1_BASE 0x40004f0cu +#define CYDEV_TMR1_SIZE 0x0000000cu +#define CYREG_TMR1_CFG0 0x40004f0cu +#define CYREG_TMR1_CFG1 0x40004f0du +#define CYREG_TMR1_CFG2 0x40004f0eu +#define CYREG_TMR1_SR0 0x40004f0fu +#define CYREG_TMR1_PER0 0x40004f10u +#define CYREG_TMR1_PER1 0x40004f11u +#define CYREG_TMR1_CNT_CMP0 0x40004f12u +#define CYREG_TMR1_CNT_CMP1 0x40004f13u +#define CYREG_TMR1_CAP0 0x40004f14u +#define CYREG_TMR1_CAP1 0x40004f15u +#define CYREG_TMR1_RT0 0x40004f16u +#define CYREG_TMR1_RT1 0x40004f17u +#define CYDEV_TMR2_BASE 0x40004f18u +#define CYDEV_TMR2_SIZE 0x0000000cu +#define CYREG_TMR2_CFG0 0x40004f18u +#define CYREG_TMR2_CFG1 0x40004f19u +#define CYREG_TMR2_CFG2 0x40004f1au +#define CYREG_TMR2_SR0 0x40004f1bu +#define CYREG_TMR2_PER0 0x40004f1cu +#define CYREG_TMR2_PER1 0x40004f1du +#define CYREG_TMR2_CNT_CMP0 0x40004f1eu +#define CYREG_TMR2_CNT_CMP1 0x40004f1fu +#define CYREG_TMR2_CAP0 0x40004f20u +#define CYREG_TMR2_CAP1 0x40004f21u +#define CYREG_TMR2_RT0 0x40004f22u +#define CYREG_TMR2_RT1 0x40004f23u +#define CYDEV_TMR3_BASE 0x40004f24u +#define CYDEV_TMR3_SIZE 0x0000000cu +#define CYREG_TMR3_CFG0 0x40004f24u +#define CYREG_TMR3_CFG1 0x40004f25u +#define CYREG_TMR3_CFG2 0x40004f26u +#define CYREG_TMR3_SR0 0x40004f27u +#define CYREG_TMR3_PER0 0x40004f28u +#define CYREG_TMR3_PER1 0x40004f29u +#define CYREG_TMR3_CNT_CMP0 0x40004f2au +#define CYREG_TMR3_CNT_CMP1 0x40004f2bu +#define CYREG_TMR3_CAP0 0x40004f2cu +#define CYREG_TMR3_CAP1 0x40004f2du +#define CYREG_TMR3_RT0 0x40004f2eu +#define CYREG_TMR3_RT1 0x40004f2fu +#define CYDEV_IO_BASE 0x40005000u +#define CYDEV_IO_SIZE 0x00000200u +#define CYDEV_IO_PC_BASE 0x40005000u +#define CYDEV_IO_PC_SIZE 0x00000080u +#define CYDEV_IO_PC_PRT0_BASE 0x40005000u +#define CYDEV_IO_PC_PRT0_SIZE 0x00000008u +#define CYREG_PRT0_PC0 0x40005000u +#define CYREG_PRT0_PC1 0x40005001u +#define CYREG_PRT0_PC2 0x40005002u +#define CYREG_PRT0_PC3 0x40005003u +#define CYREG_PRT0_PC4 0x40005004u +#define CYREG_PRT0_PC5 0x40005005u +#define CYREG_PRT0_PC6 0x40005006u +#define CYREG_PRT0_PC7 0x40005007u +#define CYDEV_IO_PC_PRT1_BASE 0x40005008u +#define CYDEV_IO_PC_PRT1_SIZE 0x00000008u +#define CYREG_PRT1_PC0 0x40005008u +#define CYREG_PRT1_PC1 0x40005009u +#define CYREG_PRT1_PC2 0x4000500au +#define CYREG_PRT1_PC3 0x4000500bu +#define CYREG_PRT1_PC4 0x4000500cu +#define CYREG_PRT1_PC5 0x4000500du +#define CYREG_PRT1_PC6 0x4000500eu +#define CYREG_PRT1_PC7 0x4000500fu +#define CYDEV_IO_PC_PRT2_BASE 0x40005010u +#define CYDEV_IO_PC_PRT2_SIZE 0x00000008u +#define CYREG_PRT2_PC0 0x40005010u +#define CYREG_PRT2_PC1 0x40005011u +#define CYREG_PRT2_PC2 0x40005012u +#define CYREG_PRT2_PC3 0x40005013u +#define CYREG_PRT2_PC4 0x40005014u +#define CYREG_PRT2_PC5 0x40005015u +#define CYREG_PRT2_PC6 0x40005016u +#define CYREG_PRT2_PC7 0x40005017u +#define CYDEV_IO_PC_PRT3_BASE 0x40005018u +#define CYDEV_IO_PC_PRT3_SIZE 0x00000008u +#define CYREG_PRT3_PC0 0x40005018u +#define CYREG_PRT3_PC1 0x40005019u +#define CYREG_PRT3_PC2 0x4000501au +#define CYREG_PRT3_PC3 0x4000501bu +#define CYREG_PRT3_PC4 0x4000501cu +#define CYREG_PRT3_PC5 0x4000501du +#define CYREG_PRT3_PC6 0x4000501eu +#define CYREG_PRT3_PC7 0x4000501fu +#define CYDEV_IO_PC_PRT4_BASE 0x40005020u +#define CYDEV_IO_PC_PRT4_SIZE 0x00000008u +#define CYREG_PRT4_PC0 0x40005020u +#define CYREG_PRT4_PC1 0x40005021u +#define CYREG_PRT4_PC2 0x40005022u +#define CYREG_PRT4_PC3 0x40005023u +#define CYREG_PRT4_PC4 0x40005024u +#define CYREG_PRT4_PC5 0x40005025u +#define CYREG_PRT4_PC6 0x40005026u +#define CYREG_PRT4_PC7 0x40005027u +#define CYDEV_IO_PC_PRT5_BASE 0x40005028u +#define CYDEV_IO_PC_PRT5_SIZE 0x00000008u +#define CYREG_PRT5_PC0 0x40005028u +#define CYREG_PRT5_PC1 0x40005029u +#define CYREG_PRT5_PC2 0x4000502au +#define CYREG_PRT5_PC3 0x4000502bu +#define CYREG_PRT5_PC4 0x4000502cu +#define CYREG_PRT5_PC5 0x4000502du +#define CYREG_PRT5_PC6 0x4000502eu +#define CYREG_PRT5_PC7 0x4000502fu +#define CYDEV_IO_PC_PRT6_BASE 0x40005030u +#define CYDEV_IO_PC_PRT6_SIZE 0x00000008u +#define CYREG_PRT6_PC0 0x40005030u +#define CYREG_PRT6_PC1 0x40005031u +#define CYREG_PRT6_PC2 0x40005032u +#define CYREG_PRT6_PC3 0x40005033u +#define CYREG_PRT6_PC4 0x40005034u +#define CYREG_PRT6_PC5 0x40005035u +#define CYREG_PRT6_PC6 0x40005036u +#define CYREG_PRT6_PC7 0x40005037u +#define CYDEV_IO_PC_PRT12_BASE 0x40005060u +#define CYDEV_IO_PC_PRT12_SIZE 0x00000008u +#define CYREG_PRT12_PC0 0x40005060u +#define CYREG_PRT12_PC1 0x40005061u +#define CYREG_PRT12_PC2 0x40005062u +#define CYREG_PRT12_PC3 0x40005063u +#define CYREG_PRT12_PC4 0x40005064u +#define CYREG_PRT12_PC5 0x40005065u +#define CYREG_PRT12_PC6 0x40005066u +#define CYREG_PRT12_PC7 0x40005067u +#define CYDEV_IO_PC_PRT15_BASE 0x40005078u +#define CYDEV_IO_PC_PRT15_SIZE 0x00000006u +#define CYREG_IO_PC_PRT15_PC0 0x40005078u +#define CYREG_IO_PC_PRT15_PC1 0x40005079u +#define CYREG_IO_PC_PRT15_PC2 0x4000507au +#define CYREG_IO_PC_PRT15_PC3 0x4000507bu +#define CYREG_IO_PC_PRT15_PC4 0x4000507cu +#define CYREG_IO_PC_PRT15_PC5 0x4000507du +#define CYDEV_IO_PC_PRT15_7_6_BASE 0x4000507eu +#define CYDEV_IO_PC_PRT15_7_6_SIZE 0x00000002u +#define CYREG_IO_PC_PRT15_7_6_PC0 0x4000507eu +#define CYREG_IO_PC_PRT15_7_6_PC1 0x4000507fu +#define CYDEV_IO_DR_BASE 0x40005080u +#define CYDEV_IO_DR_SIZE 0x00000010u +#define CYDEV_IO_DR_PRT0_BASE 0x40005080u +#define CYDEV_IO_DR_PRT0_SIZE 0x00000001u +#define CYREG_PRT0_DR_ALIAS 0x40005080u +#define CYDEV_IO_DR_PRT1_BASE 0x40005081u +#define CYDEV_IO_DR_PRT1_SIZE 0x00000001u +#define CYREG_PRT1_DR_ALIAS 0x40005081u +#define CYDEV_IO_DR_PRT2_BASE 0x40005082u +#define CYDEV_IO_DR_PRT2_SIZE 0x00000001u +#define CYREG_PRT2_DR_ALIAS 0x40005082u +#define CYDEV_IO_DR_PRT3_BASE 0x40005083u +#define CYDEV_IO_DR_PRT3_SIZE 0x00000001u +#define CYREG_PRT3_DR_ALIAS 0x40005083u +#define CYDEV_IO_DR_PRT4_BASE 0x40005084u +#define CYDEV_IO_DR_PRT4_SIZE 0x00000001u +#define CYREG_PRT4_DR_ALIAS 0x40005084u +#define CYDEV_IO_DR_PRT5_BASE 0x40005085u +#define CYDEV_IO_DR_PRT5_SIZE 0x00000001u +#define CYREG_PRT5_DR_ALIAS 0x40005085u +#define CYDEV_IO_DR_PRT6_BASE 0x40005086u +#define CYDEV_IO_DR_PRT6_SIZE 0x00000001u +#define CYREG_PRT6_DR_ALIAS 0x40005086u +#define CYDEV_IO_DR_PRT12_BASE 0x4000508cu +#define CYDEV_IO_DR_PRT12_SIZE 0x00000001u +#define CYREG_PRT12_DR_ALIAS 0x4000508cu +#define CYDEV_IO_DR_PRT15_BASE 0x4000508fu +#define CYDEV_IO_DR_PRT15_SIZE 0x00000001u +#define CYREG_PRT15_DR_15_ALIAS 0x4000508fu +#define CYDEV_IO_PS_BASE 0x40005090u +#define CYDEV_IO_PS_SIZE 0x00000010u +#define CYDEV_IO_PS_PRT0_BASE 0x40005090u +#define CYDEV_IO_PS_PRT0_SIZE 0x00000001u +#define CYREG_PRT0_PS_ALIAS 0x40005090u +#define CYDEV_IO_PS_PRT1_BASE 0x40005091u +#define CYDEV_IO_PS_PRT1_SIZE 0x00000001u +#define CYREG_PRT1_PS_ALIAS 0x40005091u +#define CYDEV_IO_PS_PRT2_BASE 0x40005092u +#define CYDEV_IO_PS_PRT2_SIZE 0x00000001u +#define CYREG_PRT2_PS_ALIAS 0x40005092u +#define CYDEV_IO_PS_PRT3_BASE 0x40005093u +#define CYDEV_IO_PS_PRT3_SIZE 0x00000001u +#define CYREG_PRT3_PS_ALIAS 0x40005093u +#define CYDEV_IO_PS_PRT4_BASE 0x40005094u +#define CYDEV_IO_PS_PRT4_SIZE 0x00000001u +#define CYREG_PRT4_PS_ALIAS 0x40005094u +#define CYDEV_IO_PS_PRT5_BASE 0x40005095u +#define CYDEV_IO_PS_PRT5_SIZE 0x00000001u +#define CYREG_PRT5_PS_ALIAS 0x40005095u +#define CYDEV_IO_PS_PRT6_BASE 0x40005096u +#define CYDEV_IO_PS_PRT6_SIZE 0x00000001u +#define CYREG_PRT6_PS_ALIAS 0x40005096u +#define CYDEV_IO_PS_PRT12_BASE 0x4000509cu +#define CYDEV_IO_PS_PRT12_SIZE 0x00000001u +#define CYREG_PRT12_PS_ALIAS 0x4000509cu +#define CYDEV_IO_PS_PRT15_BASE 0x4000509fu +#define CYDEV_IO_PS_PRT15_SIZE 0x00000001u +#define CYREG_PRT15_PS15_ALIAS 0x4000509fu +#define CYDEV_IO_PRT_BASE 0x40005100u +#define CYDEV_IO_PRT_SIZE 0x00000100u +#define CYDEV_IO_PRT_PRT0_BASE 0x40005100u +#define CYDEV_IO_PRT_PRT0_SIZE 0x00000010u +#define CYREG_PRT0_DR 0x40005100u +#define CYREG_PRT0_PS 0x40005101u +#define CYREG_PRT0_DM0 0x40005102u +#define CYREG_PRT0_DM1 0x40005103u +#define CYREG_PRT0_DM2 0x40005104u +#define CYREG_PRT0_SLW 0x40005105u +#define CYREG_PRT0_BYP 0x40005106u +#define CYREG_PRT0_BIE 0x40005107u +#define CYREG_PRT0_INP_DIS 0x40005108u +#define CYREG_PRT0_CTL 0x40005109u +#define CYREG_PRT0_PRT 0x4000510au +#define CYREG_PRT0_BIT_MASK 0x4000510bu +#define CYREG_PRT0_AMUX 0x4000510cu +#define CYREG_PRT0_AG 0x4000510du +#define CYREG_PRT0_LCD_COM_SEG 0x4000510eu +#define CYREG_PRT0_LCD_EN 0x4000510fu +#define CYDEV_IO_PRT_PRT1_BASE 0x40005110u +#define CYDEV_IO_PRT_PRT1_SIZE 0x00000010u +#define CYREG_PRT1_DR 0x40005110u +#define CYREG_PRT1_PS 0x40005111u +#define CYREG_PRT1_DM0 0x40005112u +#define CYREG_PRT1_DM1 0x40005113u +#define CYREG_PRT1_DM2 0x40005114u +#define CYREG_PRT1_SLW 0x40005115u +#define CYREG_PRT1_BYP 0x40005116u +#define CYREG_PRT1_BIE 0x40005117u +#define CYREG_PRT1_INP_DIS 0x40005118u +#define CYREG_PRT1_CTL 0x40005119u +#define CYREG_PRT1_PRT 0x4000511au +#define CYREG_PRT1_BIT_MASK 0x4000511bu +#define CYREG_PRT1_AMUX 0x4000511cu +#define CYREG_PRT1_AG 0x4000511du +#define CYREG_PRT1_LCD_COM_SEG 0x4000511eu +#define CYREG_PRT1_LCD_EN 0x4000511fu +#define CYDEV_IO_PRT_PRT2_BASE 0x40005120u +#define CYDEV_IO_PRT_PRT2_SIZE 0x00000010u +#define CYREG_PRT2_DR 0x40005120u +#define CYREG_PRT2_PS 0x40005121u +#define CYREG_PRT2_DM0 0x40005122u +#define CYREG_PRT2_DM1 0x40005123u +#define CYREG_PRT2_DM2 0x40005124u +#define CYREG_PRT2_SLW 0x40005125u +#define CYREG_PRT2_BYP 0x40005126u +#define CYREG_PRT2_BIE 0x40005127u +#define CYREG_PRT2_INP_DIS 0x40005128u +#define CYREG_PRT2_CTL 0x40005129u +#define CYREG_PRT2_PRT 0x4000512au +#define CYREG_PRT2_BIT_MASK 0x4000512bu +#define CYREG_PRT2_AMUX 0x4000512cu +#define CYREG_PRT2_AG 0x4000512du +#define CYREG_PRT2_LCD_COM_SEG 0x4000512eu +#define CYREG_PRT2_LCD_EN 0x4000512fu +#define CYDEV_IO_PRT_PRT3_BASE 0x40005130u +#define CYDEV_IO_PRT_PRT3_SIZE 0x00000010u +#define CYREG_PRT3_DR 0x40005130u +#define CYREG_PRT3_PS 0x40005131u +#define CYREG_PRT3_DM0 0x40005132u +#define CYREG_PRT3_DM1 0x40005133u +#define CYREG_PRT3_DM2 0x40005134u +#define CYREG_PRT3_SLW 0x40005135u +#define CYREG_PRT3_BYP 0x40005136u +#define CYREG_PRT3_BIE 0x40005137u +#define CYREG_PRT3_INP_DIS 0x40005138u +#define CYREG_PRT3_CTL 0x40005139u +#define CYREG_PRT3_PRT 0x4000513au +#define CYREG_PRT3_BIT_MASK 0x4000513bu +#define CYREG_PRT3_AMUX 0x4000513cu +#define CYREG_PRT3_AG 0x4000513du +#define CYREG_PRT3_LCD_COM_SEG 0x4000513eu +#define CYREG_PRT3_LCD_EN 0x4000513fu +#define CYDEV_IO_PRT_PRT4_BASE 0x40005140u +#define CYDEV_IO_PRT_PRT4_SIZE 0x00000010u +#define CYREG_PRT4_DR 0x40005140u +#define CYREG_PRT4_PS 0x40005141u +#define CYREG_PRT4_DM0 0x40005142u +#define CYREG_PRT4_DM1 0x40005143u +#define CYREG_PRT4_DM2 0x40005144u +#define CYREG_PRT4_SLW 0x40005145u +#define CYREG_PRT4_BYP 0x40005146u +#define CYREG_PRT4_BIE 0x40005147u +#define CYREG_PRT4_INP_DIS 0x40005148u +#define CYREG_PRT4_CTL 0x40005149u +#define CYREG_PRT4_PRT 0x4000514au +#define CYREG_PRT4_BIT_MASK 0x4000514bu +#define CYREG_PRT4_AMUX 0x4000514cu +#define CYREG_PRT4_AG 0x4000514du +#define CYREG_PRT4_LCD_COM_SEG 0x4000514eu +#define CYREG_PRT4_LCD_EN 0x4000514fu +#define CYDEV_IO_PRT_PRT5_BASE 0x40005150u +#define CYDEV_IO_PRT_PRT5_SIZE 0x00000010u +#define CYREG_PRT5_DR 0x40005150u +#define CYREG_PRT5_PS 0x40005151u +#define CYREG_PRT5_DM0 0x40005152u +#define CYREG_PRT5_DM1 0x40005153u +#define CYREG_PRT5_DM2 0x40005154u +#define CYREG_PRT5_SLW 0x40005155u +#define CYREG_PRT5_BYP 0x40005156u +#define CYREG_PRT5_BIE 0x40005157u +#define CYREG_PRT5_INP_DIS 0x40005158u +#define CYREG_PRT5_CTL 0x40005159u +#define CYREG_PRT5_PRT 0x4000515au +#define CYREG_PRT5_BIT_MASK 0x4000515bu +#define CYREG_PRT5_AMUX 0x4000515cu +#define CYREG_PRT5_AG 0x4000515du +#define CYREG_PRT5_LCD_COM_SEG 0x4000515eu +#define CYREG_PRT5_LCD_EN 0x4000515fu +#define CYDEV_IO_PRT_PRT6_BASE 0x40005160u +#define CYDEV_IO_PRT_PRT6_SIZE 0x00000010u +#define CYREG_PRT6_DR 0x40005160u +#define CYREG_PRT6_PS 0x40005161u +#define CYREG_PRT6_DM0 0x40005162u +#define CYREG_PRT6_DM1 0x40005163u +#define CYREG_PRT6_DM2 0x40005164u +#define CYREG_PRT6_SLW 0x40005165u +#define CYREG_PRT6_BYP 0x40005166u +#define CYREG_PRT6_BIE 0x40005167u +#define CYREG_PRT6_INP_DIS 0x40005168u +#define CYREG_PRT6_CTL 0x40005169u +#define CYREG_PRT6_PRT 0x4000516au +#define CYREG_PRT6_BIT_MASK 0x4000516bu +#define CYREG_PRT6_AMUX 0x4000516cu +#define CYREG_PRT6_AG 0x4000516du +#define CYREG_PRT6_LCD_COM_SEG 0x4000516eu +#define CYREG_PRT6_LCD_EN 0x4000516fu +#define CYDEV_IO_PRT_PRT12_BASE 0x400051c0u +#define CYDEV_IO_PRT_PRT12_SIZE 0x00000010u +#define CYREG_PRT12_DR 0x400051c0u +#define CYREG_PRT12_PS 0x400051c1u +#define CYREG_PRT12_DM0 0x400051c2u +#define CYREG_PRT12_DM1 0x400051c3u +#define CYREG_PRT12_DM2 0x400051c4u +#define CYREG_PRT12_SLW 0x400051c5u +#define CYREG_PRT12_BYP 0x400051c6u +#define CYREG_PRT12_BIE 0x400051c7u +#define CYREG_PRT12_INP_DIS 0x400051c8u +#define CYREG_PRT12_SIO_HYST_EN 0x400051c9u +#define CYREG_PRT12_PRT 0x400051cau +#define CYREG_PRT12_BIT_MASK 0x400051cbu +#define CYREG_PRT12_SIO_REG_HIFREQ 0x400051ccu +#define CYREG_PRT12_AG 0x400051cdu +#define CYREG_PRT12_SIO_CFG 0x400051ceu +#define CYREG_PRT12_SIO_DIFF 0x400051cfu +#define CYDEV_IO_PRT_PRT15_BASE 0x400051f0u +#define CYDEV_IO_PRT_PRT15_SIZE 0x00000010u +#define CYREG_PRT15_DR 0x400051f0u +#define CYREG_PRT15_PS 0x400051f1u +#define CYREG_PRT15_DM0 0x400051f2u +#define CYREG_PRT15_DM1 0x400051f3u +#define CYREG_PRT15_DM2 0x400051f4u +#define CYREG_PRT15_SLW 0x400051f5u +#define CYREG_PRT15_BYP 0x400051f6u +#define CYREG_PRT15_BIE 0x400051f7u +#define CYREG_PRT15_INP_DIS 0x400051f8u +#define CYREG_PRT15_CTL 0x400051f9u +#define CYREG_PRT15_PRT 0x400051fau +#define CYREG_PRT15_BIT_MASK 0x400051fbu +#define CYREG_PRT15_AMUX 0x400051fcu +#define CYREG_PRT15_AG 0x400051fdu +#define CYREG_PRT15_LCD_COM_SEG 0x400051feu +#define CYREG_PRT15_LCD_EN 0x400051ffu +#define CYDEV_PRTDSI_BASE 0x40005200u +#define CYDEV_PRTDSI_SIZE 0x0000007fu +#define CYDEV_PRTDSI_PRT0_BASE 0x40005200u +#define CYDEV_PRTDSI_PRT0_SIZE 0x00000007u +#define CYREG_PRT0_OUT_SEL0 0x40005200u +#define CYREG_PRT0_OUT_SEL1 0x40005201u +#define CYREG_PRT0_OE_SEL0 0x40005202u +#define CYREG_PRT0_OE_SEL1 0x40005203u +#define CYREG_PRT0_DBL_SYNC_IN 0x40005204u +#define CYREG_PRT0_SYNC_OUT 0x40005205u +#define CYREG_PRT0_CAPS_SEL 0x40005206u +#define CYDEV_PRTDSI_PRT1_BASE 0x40005208u +#define CYDEV_PRTDSI_PRT1_SIZE 0x00000007u +#define CYREG_PRT1_OUT_SEL0 0x40005208u +#define CYREG_PRT1_OUT_SEL1 0x40005209u +#define CYREG_PRT1_OE_SEL0 0x4000520au +#define CYREG_PRT1_OE_SEL1 0x4000520bu +#define CYREG_PRT1_DBL_SYNC_IN 0x4000520cu +#define CYREG_PRT1_SYNC_OUT 0x4000520du +#define CYREG_PRT1_CAPS_SEL 0x4000520eu +#define CYDEV_PRTDSI_PRT2_BASE 0x40005210u +#define CYDEV_PRTDSI_PRT2_SIZE 0x00000007u +#define CYREG_PRT2_OUT_SEL0 0x40005210u +#define CYREG_PRT2_OUT_SEL1 0x40005211u +#define CYREG_PRT2_OE_SEL0 0x40005212u +#define CYREG_PRT2_OE_SEL1 0x40005213u +#define CYREG_PRT2_DBL_SYNC_IN 0x40005214u +#define CYREG_PRT2_SYNC_OUT 0x40005215u +#define CYREG_PRT2_CAPS_SEL 0x40005216u +#define CYDEV_PRTDSI_PRT3_BASE 0x40005218u +#define CYDEV_PRTDSI_PRT3_SIZE 0x00000007u +#define CYREG_PRT3_OUT_SEL0 0x40005218u +#define CYREG_PRT3_OUT_SEL1 0x40005219u +#define CYREG_PRT3_OE_SEL0 0x4000521au +#define CYREG_PRT3_OE_SEL1 0x4000521bu +#define CYREG_PRT3_DBL_SYNC_IN 0x4000521cu +#define CYREG_PRT3_SYNC_OUT 0x4000521du +#define CYREG_PRT3_CAPS_SEL 0x4000521eu +#define CYDEV_PRTDSI_PRT4_BASE 0x40005220u +#define CYDEV_PRTDSI_PRT4_SIZE 0x00000007u +#define CYREG_PRT4_OUT_SEL0 0x40005220u +#define CYREG_PRT4_OUT_SEL1 0x40005221u +#define CYREG_PRT4_OE_SEL0 0x40005222u +#define CYREG_PRT4_OE_SEL1 0x40005223u +#define CYREG_PRT4_DBL_SYNC_IN 0x40005224u +#define CYREG_PRT4_SYNC_OUT 0x40005225u +#define CYREG_PRT4_CAPS_SEL 0x40005226u +#define CYDEV_PRTDSI_PRT5_BASE 0x40005228u +#define CYDEV_PRTDSI_PRT5_SIZE 0x00000007u +#define CYREG_PRT5_OUT_SEL0 0x40005228u +#define CYREG_PRT5_OUT_SEL1 0x40005229u +#define CYREG_PRT5_OE_SEL0 0x4000522au +#define CYREG_PRT5_OE_SEL1 0x4000522bu +#define CYREG_PRT5_DBL_SYNC_IN 0x4000522cu +#define CYREG_PRT5_SYNC_OUT 0x4000522du +#define CYREG_PRT5_CAPS_SEL 0x4000522eu +#define CYDEV_PRTDSI_PRT6_BASE 0x40005230u +#define CYDEV_PRTDSI_PRT6_SIZE 0x00000007u +#define CYREG_PRT6_OUT_SEL0 0x40005230u +#define CYREG_PRT6_OUT_SEL1 0x40005231u +#define CYREG_PRT6_OE_SEL0 0x40005232u +#define CYREG_PRT6_OE_SEL1 0x40005233u +#define CYREG_PRT6_DBL_SYNC_IN 0x40005234u +#define CYREG_PRT6_SYNC_OUT 0x40005235u +#define CYREG_PRT6_CAPS_SEL 0x40005236u +#define CYDEV_PRTDSI_PRT12_BASE 0x40005260u +#define CYDEV_PRTDSI_PRT12_SIZE 0x00000006u +#define CYREG_PRT12_OUT_SEL0 0x40005260u +#define CYREG_PRT12_OUT_SEL1 0x40005261u +#define CYREG_PRT12_OE_SEL0 0x40005262u +#define CYREG_PRT12_OE_SEL1 0x40005263u +#define CYREG_PRT12_DBL_SYNC_IN 0x40005264u +#define CYREG_PRT12_SYNC_OUT 0x40005265u +#define CYDEV_PRTDSI_PRT15_BASE 0x40005278u +#define CYDEV_PRTDSI_PRT15_SIZE 0x00000007u +#define CYREG_PRT15_OUT_SEL0 0x40005278u +#define CYREG_PRT15_OUT_SEL1 0x40005279u +#define CYREG_PRT15_OE_SEL0 0x4000527au +#define CYREG_PRT15_OE_SEL1 0x4000527bu +#define CYREG_PRT15_DBL_SYNC_IN 0x4000527cu +#define CYREG_PRT15_SYNC_OUT 0x4000527du +#define CYREG_PRT15_CAPS_SEL 0x4000527eu +#define CYDEV_EMIF_BASE 0x40005400u +#define CYDEV_EMIF_SIZE 0x00000007u +#define CYREG_EMIF_NO_UDB 0x40005400u +#define CYREG_EMIF_RP_WAIT_STATES 0x40005401u +#define CYREG_EMIF_MEM_DWN 0x40005402u +#define CYREG_EMIF_MEMCLK_DIV 0x40005403u +#define CYREG_EMIF_CLOCK_EN 0x40005404u +#define CYREG_EMIF_EM_TYPE 0x40005405u +#define CYREG_EMIF_WP_WAIT_STATES 0x40005406u +#define CYDEV_ANAIF_BASE 0x40005800u +#define CYDEV_ANAIF_SIZE 0x000003a9u +#define CYDEV_ANAIF_CFG_BASE 0x40005800u +#define CYDEV_ANAIF_CFG_SIZE 0x0000010fu +#define CYDEV_ANAIF_CFG_SC0_BASE 0x40005800u +#define CYDEV_ANAIF_CFG_SC0_SIZE 0x00000003u +#define CYREG_SC0_CR0 0x40005800u +#define CYREG_SC0_CR1 0x40005801u +#define CYREG_SC0_CR2 0x40005802u +#define CYDEV_ANAIF_CFG_SC1_BASE 0x40005804u +#define CYDEV_ANAIF_CFG_SC1_SIZE 0x00000003u +#define CYREG_SC1_CR0 0x40005804u +#define CYREG_SC1_CR1 0x40005805u +#define CYREG_SC1_CR2 0x40005806u +#define CYDEV_ANAIF_CFG_SC2_BASE 0x40005808u +#define CYDEV_ANAIF_CFG_SC2_SIZE 0x00000003u +#define CYREG_SC2_CR0 0x40005808u +#define CYREG_SC2_CR1 0x40005809u +#define CYREG_SC2_CR2 0x4000580au +#define CYDEV_ANAIF_CFG_SC3_BASE 0x4000580cu +#define CYDEV_ANAIF_CFG_SC3_SIZE 0x00000003u +#define CYREG_SC3_CR0 0x4000580cu +#define CYREG_SC3_CR1 0x4000580du +#define CYREG_SC3_CR2 0x4000580eu +#define CYDEV_ANAIF_CFG_DAC0_BASE 0x40005820u +#define CYDEV_ANAIF_CFG_DAC0_SIZE 0x00000003u +#define CYREG_DAC0_CR0 0x40005820u +#define CYREG_DAC0_CR1 0x40005821u +#define CYREG_DAC0_TST 0x40005822u +#define CYDEV_ANAIF_CFG_DAC1_BASE 0x40005824u +#define CYDEV_ANAIF_CFG_DAC1_SIZE 0x00000003u +#define CYREG_DAC1_CR0 0x40005824u +#define CYREG_DAC1_CR1 0x40005825u +#define CYREG_DAC1_TST 0x40005826u +#define CYDEV_ANAIF_CFG_DAC2_BASE 0x40005828u +#define CYDEV_ANAIF_CFG_DAC2_SIZE 0x00000003u +#define CYREG_DAC2_CR0 0x40005828u +#define CYREG_DAC2_CR1 0x40005829u +#define CYREG_DAC2_TST 0x4000582au +#define CYDEV_ANAIF_CFG_DAC3_BASE 0x4000582cu +#define CYDEV_ANAIF_CFG_DAC3_SIZE 0x00000003u +#define CYREG_DAC3_CR0 0x4000582cu +#define CYREG_DAC3_CR1 0x4000582du +#define CYREG_DAC3_TST 0x4000582eu +#define CYDEV_ANAIF_CFG_CMP0_BASE 0x40005840u +#define CYDEV_ANAIF_CFG_CMP0_SIZE 0x00000001u +#define CYREG_CMP0_CR 0x40005840u +#define CYDEV_ANAIF_CFG_CMP1_BASE 0x40005841u +#define CYDEV_ANAIF_CFG_CMP1_SIZE 0x00000001u +#define CYREG_CMP1_CR 0x40005841u +#define CYDEV_ANAIF_CFG_CMP2_BASE 0x40005842u +#define CYDEV_ANAIF_CFG_CMP2_SIZE 0x00000001u +#define CYREG_CMP2_CR 0x40005842u +#define CYDEV_ANAIF_CFG_CMP3_BASE 0x40005843u +#define CYDEV_ANAIF_CFG_CMP3_SIZE 0x00000001u +#define CYREG_CMP3_CR 0x40005843u +#define CYDEV_ANAIF_CFG_LUT0_BASE 0x40005848u +#define CYDEV_ANAIF_CFG_LUT0_SIZE 0x00000002u +#define CYREG_LUT0_CR 0x40005848u +#define CYREG_LUT0_MX 0x40005849u +#define CYDEV_ANAIF_CFG_LUT1_BASE 0x4000584au +#define CYDEV_ANAIF_CFG_LUT1_SIZE 0x00000002u +#define CYREG_LUT1_CR 0x4000584au +#define CYREG_LUT1_MX 0x4000584bu +#define CYDEV_ANAIF_CFG_LUT2_BASE 0x4000584cu +#define CYDEV_ANAIF_CFG_LUT2_SIZE 0x00000002u +#define CYREG_LUT2_CR 0x4000584cu +#define CYREG_LUT2_MX 0x4000584du +#define CYDEV_ANAIF_CFG_LUT3_BASE 0x4000584eu +#define CYDEV_ANAIF_CFG_LUT3_SIZE 0x00000002u +#define CYREG_LUT3_CR 0x4000584eu +#define CYREG_LUT3_MX 0x4000584fu +#define CYDEV_ANAIF_CFG_OPAMP0_BASE 0x40005858u +#define CYDEV_ANAIF_CFG_OPAMP0_SIZE 0x00000002u +#define CYREG_OPAMP0_CR 0x40005858u +#define CYREG_OPAMP0_RSVD 0x40005859u +#define CYDEV_ANAIF_CFG_OPAMP1_BASE 0x4000585au +#define CYDEV_ANAIF_CFG_OPAMP1_SIZE 0x00000002u +#define CYREG_OPAMP1_CR 0x4000585au +#define CYREG_OPAMP1_RSVD 0x4000585bu +#define CYDEV_ANAIF_CFG_OPAMP2_BASE 0x4000585cu +#define CYDEV_ANAIF_CFG_OPAMP2_SIZE 0x00000002u +#define CYREG_OPAMP2_CR 0x4000585cu +#define CYREG_OPAMP2_RSVD 0x4000585du +#define CYDEV_ANAIF_CFG_OPAMP3_BASE 0x4000585eu +#define CYDEV_ANAIF_CFG_OPAMP3_SIZE 0x00000002u +#define CYREG_OPAMP3_CR 0x4000585eu +#define CYREG_OPAMP3_RSVD 0x4000585fu +#define CYDEV_ANAIF_CFG_LCDDAC_BASE 0x40005868u +#define CYDEV_ANAIF_CFG_LCDDAC_SIZE 0x00000002u +#define CYREG_LCDDAC_CR0 0x40005868u +#define CYREG_LCDDAC_CR1 0x40005869u +#define CYDEV_ANAIF_CFG_LCDDRV_BASE 0x4000586au +#define CYDEV_ANAIF_CFG_LCDDRV_SIZE 0x00000001u +#define CYREG_LCDDRV_CR 0x4000586au +#define CYDEV_ANAIF_CFG_LCDTMR_BASE 0x4000586bu +#define CYDEV_ANAIF_CFG_LCDTMR_SIZE 0x00000001u +#define CYREG_LCDTMR_CFG 0x4000586bu +#define CYDEV_ANAIF_CFG_BG_BASE 0x4000586cu +#define CYDEV_ANAIF_CFG_BG_SIZE 0x00000004u +#define CYREG_BG_CR0 0x4000586cu +#define CYREG_BG_RSVD 0x4000586du +#define CYREG_BG_DFT0 0x4000586eu +#define CYREG_BG_DFT1 0x4000586fu +#define CYDEV_ANAIF_CFG_CAPSL_BASE 0x40005870u +#define CYDEV_ANAIF_CFG_CAPSL_SIZE 0x00000002u +#define CYREG_CAPSL_CFG0 0x40005870u +#define CYREG_CAPSL_CFG1 0x40005871u +#define CYDEV_ANAIF_CFG_CAPSR_BASE 0x40005872u +#define CYDEV_ANAIF_CFG_CAPSR_SIZE 0x00000002u +#define CYREG_CAPSR_CFG0 0x40005872u +#define CYREG_CAPSR_CFG1 0x40005873u +#define CYDEV_ANAIF_CFG_PUMP_BASE 0x40005876u +#define CYDEV_ANAIF_CFG_PUMP_SIZE 0x00000002u +#define CYREG_PUMP_CR0 0x40005876u +#define CYREG_PUMP_CR1 0x40005877u +#define CYDEV_ANAIF_CFG_LPF0_BASE 0x40005878u +#define CYDEV_ANAIF_CFG_LPF0_SIZE 0x00000002u +#define CYREG_LPF0_CR0 0x40005878u +#define CYREG_LPF0_RSVD 0x40005879u +#define CYDEV_ANAIF_CFG_LPF1_BASE 0x4000587au +#define CYDEV_ANAIF_CFG_LPF1_SIZE 0x00000002u +#define CYREG_LPF1_CR0 0x4000587au +#define CYREG_LPF1_RSVD 0x4000587bu +#define CYDEV_ANAIF_CFG_MISC_BASE 0x4000587cu +#define CYDEV_ANAIF_CFG_MISC_SIZE 0x00000001u +#define CYREG_ANAIF_CFG_MISC_CR0 0x4000587cu +#define CYDEV_ANAIF_CFG_DSM0_BASE 0x40005880u +#define CYDEV_ANAIF_CFG_DSM0_SIZE 0x00000020u +#define CYREG_DSM0_CR0 0x40005880u +#define CYREG_DSM0_CR1 0x40005881u +#define CYREG_DSM0_CR2 0x40005882u +#define CYREG_DSM0_CR3 0x40005883u +#define CYREG_DSM0_CR4 0x40005884u +#define CYREG_DSM0_CR5 0x40005885u +#define CYREG_DSM0_CR6 0x40005886u +#define CYREG_DSM0_CR7 0x40005887u +#define CYREG_DSM0_CR8 0x40005888u +#define CYREG_DSM0_CR9 0x40005889u +#define CYREG_DSM0_CR10 0x4000588au +#define CYREG_DSM0_CR11 0x4000588bu +#define CYREG_DSM0_CR12 0x4000588cu +#define CYREG_DSM0_CR13 0x4000588du +#define CYREG_DSM0_CR14 0x4000588eu +#define CYREG_DSM0_CR15 0x4000588fu +#define CYREG_DSM0_CR16 0x40005890u +#define CYREG_DSM0_CR17 0x40005891u +#define CYREG_DSM0_REF0 0x40005892u +#define CYREG_DSM0_REF1 0x40005893u +#define CYREG_DSM0_REF2 0x40005894u +#define CYREG_DSM0_REF3 0x40005895u +#define CYREG_DSM0_DEM0 0x40005896u +#define CYREG_DSM0_DEM1 0x40005897u +#define CYREG_DSM0_TST0 0x40005898u +#define CYREG_DSM0_TST1 0x40005899u +#define CYREG_DSM0_BUF0 0x4000589au +#define CYREG_DSM0_BUF1 0x4000589bu +#define CYREG_DSM0_BUF2 0x4000589cu +#define CYREG_DSM0_BUF3 0x4000589du +#define CYREG_DSM0_MISC 0x4000589eu +#define CYREG_DSM0_RSVD1 0x4000589fu +#define CYDEV_ANAIF_CFG_SAR0_BASE 0x40005900u +#define CYDEV_ANAIF_CFG_SAR0_SIZE 0x00000007u +#define CYREG_SAR0_CSR0 0x40005900u +#define CYREG_SAR0_CSR1 0x40005901u +#define CYREG_SAR0_CSR2 0x40005902u +#define CYREG_SAR0_CSR3 0x40005903u +#define CYREG_SAR0_CSR4 0x40005904u +#define CYREG_SAR0_CSR5 0x40005905u +#define CYREG_SAR0_CSR6 0x40005906u +#define CYDEV_ANAIF_CFG_SAR1_BASE 0x40005908u +#define CYDEV_ANAIF_CFG_SAR1_SIZE 0x00000007u +#define CYREG_SAR1_CSR0 0x40005908u +#define CYREG_SAR1_CSR1 0x40005909u +#define CYREG_SAR1_CSR2 0x4000590au +#define CYREG_SAR1_CSR3 0x4000590bu +#define CYREG_SAR1_CSR4 0x4000590cu +#define CYREG_SAR1_CSR5 0x4000590du +#define CYREG_SAR1_CSR6 0x4000590eu +#define CYDEV_ANAIF_RT_BASE 0x40005a00u +#define CYDEV_ANAIF_RT_SIZE 0x00000162u +#define CYDEV_ANAIF_RT_SC0_BASE 0x40005a00u +#define CYDEV_ANAIF_RT_SC0_SIZE 0x0000000du +#define CYREG_SC0_SW0 0x40005a00u +#define CYREG_SC0_SW2 0x40005a02u +#define CYREG_SC0_SW3 0x40005a03u +#define CYREG_SC0_SW4 0x40005a04u +#define CYREG_SC0_SW6 0x40005a06u +#define CYREG_SC0_SW7 0x40005a07u +#define CYREG_SC0_SW8 0x40005a08u +#define CYREG_SC0_SW10 0x40005a0au +#define CYREG_SC0_CLK 0x40005a0bu +#define CYREG_SC0_BST 0x40005a0cu +#define CYDEV_ANAIF_RT_SC1_BASE 0x40005a10u +#define CYDEV_ANAIF_RT_SC1_SIZE 0x0000000du +#define CYREG_SC1_SW0 0x40005a10u +#define CYREG_SC1_SW2 0x40005a12u +#define CYREG_SC1_SW3 0x40005a13u +#define CYREG_SC1_SW4 0x40005a14u +#define CYREG_SC1_SW6 0x40005a16u +#define CYREG_SC1_SW7 0x40005a17u +#define CYREG_SC1_SW8 0x40005a18u +#define CYREG_SC1_SW10 0x40005a1au +#define CYREG_SC1_CLK 0x40005a1bu +#define CYREG_SC1_BST 0x40005a1cu +#define CYDEV_ANAIF_RT_SC2_BASE 0x40005a20u +#define CYDEV_ANAIF_RT_SC2_SIZE 0x0000000du +#define CYREG_SC2_SW0 0x40005a20u +#define CYREG_SC2_SW2 0x40005a22u +#define CYREG_SC2_SW3 0x40005a23u +#define CYREG_SC2_SW4 0x40005a24u +#define CYREG_SC2_SW6 0x40005a26u +#define CYREG_SC2_SW7 0x40005a27u +#define CYREG_SC2_SW8 0x40005a28u +#define CYREG_SC2_SW10 0x40005a2au +#define CYREG_SC2_CLK 0x40005a2bu +#define CYREG_SC2_BST 0x40005a2cu +#define CYDEV_ANAIF_RT_SC3_BASE 0x40005a30u +#define CYDEV_ANAIF_RT_SC3_SIZE 0x0000000du +#define CYREG_SC3_SW0 0x40005a30u +#define CYREG_SC3_SW2 0x40005a32u +#define CYREG_SC3_SW3 0x40005a33u +#define CYREG_SC3_SW4 0x40005a34u +#define CYREG_SC3_SW6 0x40005a36u +#define CYREG_SC3_SW7 0x40005a37u +#define CYREG_SC3_SW8 0x40005a38u +#define CYREG_SC3_SW10 0x40005a3au +#define CYREG_SC3_CLK 0x40005a3bu +#define CYREG_SC3_BST 0x40005a3cu +#define CYDEV_ANAIF_RT_DAC0_BASE 0x40005a80u +#define CYDEV_ANAIF_RT_DAC0_SIZE 0x00000008u +#define CYREG_DAC0_SW0 0x40005a80u +#define CYREG_DAC0_SW2 0x40005a82u +#define CYREG_DAC0_SW3 0x40005a83u +#define CYREG_DAC0_SW4 0x40005a84u +#define CYREG_DAC0_STROBE 0x40005a87u +#define CYDEV_ANAIF_RT_DAC1_BASE 0x40005a88u +#define CYDEV_ANAIF_RT_DAC1_SIZE 0x00000008u +#define CYREG_DAC1_SW0 0x40005a88u +#define CYREG_DAC1_SW2 0x40005a8au +#define CYREG_DAC1_SW3 0x40005a8bu +#define CYREG_DAC1_SW4 0x40005a8cu +#define CYREG_DAC1_STROBE 0x40005a8fu +#define CYDEV_ANAIF_RT_DAC2_BASE 0x40005a90u +#define CYDEV_ANAIF_RT_DAC2_SIZE 0x00000008u +#define CYREG_DAC2_SW0 0x40005a90u +#define CYREG_DAC2_SW2 0x40005a92u +#define CYREG_DAC2_SW3 0x40005a93u +#define CYREG_DAC2_SW4 0x40005a94u +#define CYREG_DAC2_STROBE 0x40005a97u +#define CYDEV_ANAIF_RT_DAC3_BASE 0x40005a98u +#define CYDEV_ANAIF_RT_DAC3_SIZE 0x00000008u +#define CYREG_DAC3_SW0 0x40005a98u +#define CYREG_DAC3_SW2 0x40005a9au +#define CYREG_DAC3_SW3 0x40005a9bu +#define CYREG_DAC3_SW4 0x40005a9cu +#define CYREG_DAC3_STROBE 0x40005a9fu +#define CYDEV_ANAIF_RT_CMP0_BASE 0x40005ac0u +#define CYDEV_ANAIF_RT_CMP0_SIZE 0x00000008u +#define CYREG_CMP0_SW0 0x40005ac0u +#define CYREG_CMP0_SW2 0x40005ac2u +#define CYREG_CMP0_SW3 0x40005ac3u +#define CYREG_CMP0_SW4 0x40005ac4u +#define CYREG_CMP0_SW6 0x40005ac6u +#define CYREG_CMP0_CLK 0x40005ac7u +#define CYDEV_ANAIF_RT_CMP1_BASE 0x40005ac8u +#define CYDEV_ANAIF_RT_CMP1_SIZE 0x00000008u +#define CYREG_CMP1_SW0 0x40005ac8u +#define CYREG_CMP1_SW2 0x40005acau +#define CYREG_CMP1_SW3 0x40005acbu +#define CYREG_CMP1_SW4 0x40005accu +#define CYREG_CMP1_SW6 0x40005aceu +#define CYREG_CMP1_CLK 0x40005acfu +#define CYDEV_ANAIF_RT_CMP2_BASE 0x40005ad0u +#define CYDEV_ANAIF_RT_CMP2_SIZE 0x00000008u +#define CYREG_CMP2_SW0 0x40005ad0u +#define CYREG_CMP2_SW2 0x40005ad2u +#define CYREG_CMP2_SW3 0x40005ad3u +#define CYREG_CMP2_SW4 0x40005ad4u +#define CYREG_CMP2_SW6 0x40005ad6u +#define CYREG_CMP2_CLK 0x40005ad7u +#define CYDEV_ANAIF_RT_CMP3_BASE 0x40005ad8u +#define CYDEV_ANAIF_RT_CMP3_SIZE 0x00000008u +#define CYREG_CMP3_SW0 0x40005ad8u +#define CYREG_CMP3_SW2 0x40005adau +#define CYREG_CMP3_SW3 0x40005adbu +#define CYREG_CMP3_SW4 0x40005adcu +#define CYREG_CMP3_SW6 0x40005adeu +#define CYREG_CMP3_CLK 0x40005adfu +#define CYDEV_ANAIF_RT_DSM0_BASE 0x40005b00u +#define CYDEV_ANAIF_RT_DSM0_SIZE 0x00000008u +#define CYREG_DSM0_SW0 0x40005b00u +#define CYREG_DSM0_SW2 0x40005b02u +#define CYREG_DSM0_SW3 0x40005b03u +#define CYREG_DSM0_SW4 0x40005b04u +#define CYREG_DSM0_SW6 0x40005b06u +#define CYREG_DSM0_CLK 0x40005b07u +#define CYDEV_ANAIF_RT_SAR0_BASE 0x40005b20u +#define CYDEV_ANAIF_RT_SAR0_SIZE 0x00000008u +#define CYREG_SAR0_SW0 0x40005b20u +#define CYREG_SAR0_SW2 0x40005b22u +#define CYREG_SAR0_SW3 0x40005b23u +#define CYREG_SAR0_SW4 0x40005b24u +#define CYREG_SAR0_SW6 0x40005b26u +#define CYREG_SAR0_CLK 0x40005b27u +#define CYDEV_ANAIF_RT_SAR1_BASE 0x40005b28u +#define CYDEV_ANAIF_RT_SAR1_SIZE 0x00000008u +#define CYREG_SAR1_SW0 0x40005b28u +#define CYREG_SAR1_SW2 0x40005b2au +#define CYREG_SAR1_SW3 0x40005b2bu +#define CYREG_SAR1_SW4 0x40005b2cu +#define CYREG_SAR1_SW6 0x40005b2eu +#define CYREG_SAR1_CLK 0x40005b2fu +#define CYDEV_ANAIF_RT_OPAMP0_BASE 0x40005b40u +#define CYDEV_ANAIF_RT_OPAMP0_SIZE 0x00000002u +#define CYREG_OPAMP0_MX 0x40005b40u +#define CYREG_OPAMP0_SW 0x40005b41u +#define CYDEV_ANAIF_RT_OPAMP1_BASE 0x40005b42u +#define CYDEV_ANAIF_RT_OPAMP1_SIZE 0x00000002u +#define CYREG_OPAMP1_MX 0x40005b42u +#define CYREG_OPAMP1_SW 0x40005b43u +#define CYDEV_ANAIF_RT_OPAMP2_BASE 0x40005b44u +#define CYDEV_ANAIF_RT_OPAMP2_SIZE 0x00000002u +#define CYREG_OPAMP2_MX 0x40005b44u +#define CYREG_OPAMP2_SW 0x40005b45u +#define CYDEV_ANAIF_RT_OPAMP3_BASE 0x40005b46u +#define CYDEV_ANAIF_RT_OPAMP3_SIZE 0x00000002u +#define CYREG_OPAMP3_MX 0x40005b46u +#define CYREG_OPAMP3_SW 0x40005b47u +#define CYDEV_ANAIF_RT_LCDDAC_BASE 0x40005b50u +#define CYDEV_ANAIF_RT_LCDDAC_SIZE 0x00000005u +#define CYREG_LCDDAC_SW0 0x40005b50u +#define CYREG_LCDDAC_SW1 0x40005b51u +#define CYREG_LCDDAC_SW2 0x40005b52u +#define CYREG_LCDDAC_SW3 0x40005b53u +#define CYREG_LCDDAC_SW4 0x40005b54u +#define CYDEV_ANAIF_RT_SC_BASE 0x40005b56u +#define CYDEV_ANAIF_RT_SC_SIZE 0x00000001u +#define CYREG_SC_MISC 0x40005b56u +#define CYDEV_ANAIF_RT_BUS_BASE 0x40005b58u +#define CYDEV_ANAIF_RT_BUS_SIZE 0x00000004u +#define CYREG_BUS_SW0 0x40005b58u +#define CYREG_BUS_SW2 0x40005b5au +#define CYREG_BUS_SW3 0x40005b5bu +#define CYDEV_ANAIF_RT_DFT_BASE 0x40005b5cu +#define CYDEV_ANAIF_RT_DFT_SIZE 0x00000006u +#define CYREG_DFT_CR0 0x40005b5cu +#define CYREG_DFT_CR1 0x40005b5du +#define CYREG_DFT_CR2 0x40005b5eu +#define CYREG_DFT_CR3 0x40005b5fu +#define CYREG_DFT_CR4 0x40005b60u +#define CYREG_DFT_CR5 0x40005b61u +#define CYDEV_ANAIF_WRK_BASE 0x40005b80u +#define CYDEV_ANAIF_WRK_SIZE 0x00000029u +#define CYDEV_ANAIF_WRK_DAC0_BASE 0x40005b80u +#define CYDEV_ANAIF_WRK_DAC0_SIZE 0x00000001u +#define CYREG_DAC0_D 0x40005b80u +#define CYDEV_ANAIF_WRK_DAC1_BASE 0x40005b81u +#define CYDEV_ANAIF_WRK_DAC1_SIZE 0x00000001u +#define CYREG_DAC1_D 0x40005b81u +#define CYDEV_ANAIF_WRK_DAC2_BASE 0x40005b82u +#define CYDEV_ANAIF_WRK_DAC2_SIZE 0x00000001u +#define CYREG_DAC2_D 0x40005b82u +#define CYDEV_ANAIF_WRK_DAC3_BASE 0x40005b83u +#define CYDEV_ANAIF_WRK_DAC3_SIZE 0x00000001u +#define CYREG_DAC3_D 0x40005b83u +#define CYDEV_ANAIF_WRK_DSM0_BASE 0x40005b88u +#define CYDEV_ANAIF_WRK_DSM0_SIZE 0x00000002u +#define CYREG_DSM0_OUT0 0x40005b88u +#define CYREG_DSM0_OUT1 0x40005b89u +#define CYDEV_ANAIF_WRK_LUT_BASE 0x40005b90u +#define CYDEV_ANAIF_WRK_LUT_SIZE 0x00000005u +#define CYREG_LUT_SR 0x40005b90u +#define CYREG_LUT_WRK1 0x40005b91u +#define CYREG_LUT_MSK 0x40005b92u +#define CYREG_LUT_CLK 0x40005b93u +#define CYREG_LUT_CPTR 0x40005b94u +#define CYDEV_ANAIF_WRK_CMP_BASE 0x40005b96u +#define CYDEV_ANAIF_WRK_CMP_SIZE 0x00000002u +#define CYREG_CMP_WRK 0x40005b96u +#define CYREG_CMP_TST 0x40005b97u +#define CYDEV_ANAIF_WRK_SC_BASE 0x40005b98u +#define CYDEV_ANAIF_WRK_SC_SIZE 0x00000005u +#define CYREG_SC_SR 0x40005b98u +#define CYREG_SC_WRK1 0x40005b99u +#define CYREG_SC_MSK 0x40005b9au +#define CYREG_SC_CMPINV 0x40005b9bu +#define CYREG_SC_CPTR 0x40005b9cu +#define CYDEV_ANAIF_WRK_SAR0_BASE 0x40005ba0u +#define CYDEV_ANAIF_WRK_SAR0_SIZE 0x00000002u +#define CYREG_SAR0_WRK0 0x40005ba0u +#define CYREG_SAR0_WRK1 0x40005ba1u +#define CYDEV_ANAIF_WRK_SAR1_BASE 0x40005ba2u +#define CYDEV_ANAIF_WRK_SAR1_SIZE 0x00000002u +#define CYREG_SAR1_WRK0 0x40005ba2u +#define CYREG_SAR1_WRK1 0x40005ba3u +#define CYDEV_ANAIF_WRK_SARS_BASE 0x40005ba8u +#define CYDEV_ANAIF_WRK_SARS_SIZE 0x00000001u +#define CYREG_ANAIF_WRK_SARS_SOF 0x40005ba8u +#define CYDEV_USB_BASE 0x40006000u +#define CYDEV_USB_SIZE 0x00000300u +#define CYREG_USB_EP0_DR0 0x40006000u +#define CYREG_USB_EP0_DR1 0x40006001u +#define CYREG_USB_EP0_DR2 0x40006002u +#define CYREG_USB_EP0_DR3 0x40006003u +#define CYREG_USB_EP0_DR4 0x40006004u +#define CYREG_USB_EP0_DR5 0x40006005u +#define CYREG_USB_EP0_DR6 0x40006006u +#define CYREG_USB_EP0_DR7 0x40006007u +#define CYREG_USB_CR0 0x40006008u +#define CYREG_USB_CR1 0x40006009u +#define CYREG_USB_SIE_EP_INT_EN 0x4000600au +#define CYREG_USB_SIE_EP_INT_SR 0x4000600bu +#define CYDEV_USB_SIE_EP1_BASE 0x4000600cu +#define CYDEV_USB_SIE_EP1_SIZE 0x00000003u +#define CYREG_USB_SIE_EP1_CNT0 0x4000600cu +#define CYREG_USB_SIE_EP1_CNT1 0x4000600du +#define CYREG_USB_SIE_EP1_CR0 0x4000600eu +#define CYREG_USB_USBIO_CR0 0x40006010u +#define CYREG_USB_USBIO_CR1 0x40006012u +#define CYREG_USB_DYN_RECONFIG 0x40006014u +#define CYREG_USB_SOF0 0x40006018u +#define CYREG_USB_SOF1 0x40006019u +#define CYDEV_USB_SIE_EP2_BASE 0x4000601cu +#define CYDEV_USB_SIE_EP2_SIZE 0x00000003u +#define CYREG_USB_SIE_EP2_CNT0 0x4000601cu +#define CYREG_USB_SIE_EP2_CNT1 0x4000601du +#define CYREG_USB_SIE_EP2_CR0 0x4000601eu +#define CYREG_USB_EP0_CR 0x40006028u +#define CYREG_USB_EP0_CNT 0x40006029u +#define CYDEV_USB_SIE_EP3_BASE 0x4000602cu +#define CYDEV_USB_SIE_EP3_SIZE 0x00000003u +#define CYREG_USB_SIE_EP3_CNT0 0x4000602cu +#define CYREG_USB_SIE_EP3_CNT1 0x4000602du +#define CYREG_USB_SIE_EP3_CR0 0x4000602eu +#define CYDEV_USB_SIE_EP4_BASE 0x4000603cu +#define CYDEV_USB_SIE_EP4_SIZE 0x00000003u +#define CYREG_USB_SIE_EP4_CNT0 0x4000603cu +#define CYREG_USB_SIE_EP4_CNT1 0x4000603du +#define CYREG_USB_SIE_EP4_CR0 0x4000603eu +#define CYDEV_USB_SIE_EP5_BASE 0x4000604cu +#define CYDEV_USB_SIE_EP5_SIZE 0x00000003u +#define CYREG_USB_SIE_EP5_CNT0 0x4000604cu +#define CYREG_USB_SIE_EP5_CNT1 0x4000604du +#define CYREG_USB_SIE_EP5_CR0 0x4000604eu +#define CYDEV_USB_SIE_EP6_BASE 0x4000605cu +#define CYDEV_USB_SIE_EP6_SIZE 0x00000003u +#define CYREG_USB_SIE_EP6_CNT0 0x4000605cu +#define CYREG_USB_SIE_EP6_CNT1 0x4000605du +#define CYREG_USB_SIE_EP6_CR0 0x4000605eu +#define CYDEV_USB_SIE_EP7_BASE 0x4000606cu +#define CYDEV_USB_SIE_EP7_SIZE 0x00000003u +#define CYREG_USB_SIE_EP7_CNT0 0x4000606cu +#define CYREG_USB_SIE_EP7_CNT1 0x4000606du +#define CYREG_USB_SIE_EP7_CR0 0x4000606eu +#define CYDEV_USB_SIE_EP8_BASE 0x4000607cu +#define CYDEV_USB_SIE_EP8_SIZE 0x00000003u +#define CYREG_USB_SIE_EP8_CNT0 0x4000607cu +#define CYREG_USB_SIE_EP8_CNT1 0x4000607du +#define CYREG_USB_SIE_EP8_CR0 0x4000607eu +#define CYDEV_USB_ARB_EP1_BASE 0x40006080u +#define CYDEV_USB_ARB_EP1_SIZE 0x00000003u +#define CYREG_USB_ARB_EP1_CFG 0x40006080u +#define CYREG_USB_ARB_EP1_INT_EN 0x40006081u +#define CYREG_USB_ARB_EP1_SR 0x40006082u +#define CYDEV_USB_ARB_RW1_BASE 0x40006084u +#define CYDEV_USB_ARB_RW1_SIZE 0x00000005u +#define CYREG_USB_ARB_RW1_WA 0x40006084u +#define CYREG_USB_ARB_RW1_WA_MSB 0x40006085u +#define CYREG_USB_ARB_RW1_RA 0x40006086u +#define CYREG_USB_ARB_RW1_RA_MSB 0x40006087u +#define CYREG_USB_ARB_RW1_DR 0x40006088u +#define CYREG_USB_BUF_SIZE 0x4000608cu +#define CYREG_USB_EP_ACTIVE 0x4000608eu +#define CYREG_USB_EP_TYPE 0x4000608fu +#define CYDEV_USB_ARB_EP2_BASE 0x40006090u +#define CYDEV_USB_ARB_EP2_SIZE 0x00000003u +#define CYREG_USB_ARB_EP2_CFG 0x40006090u +#define CYREG_USB_ARB_EP2_INT_EN 0x40006091u +#define CYREG_USB_ARB_EP2_SR 0x40006092u +#define CYDEV_USB_ARB_RW2_BASE 0x40006094u +#define CYDEV_USB_ARB_RW2_SIZE 0x00000005u +#define CYREG_USB_ARB_RW2_WA 0x40006094u +#define CYREG_USB_ARB_RW2_WA_MSB 0x40006095u +#define CYREG_USB_ARB_RW2_RA 0x40006096u +#define CYREG_USB_ARB_RW2_RA_MSB 0x40006097u +#define CYREG_USB_ARB_RW2_DR 0x40006098u +#define CYREG_USB_ARB_CFG 0x4000609cu +#define CYREG_USB_USB_CLK_EN 0x4000609du +#define CYREG_USB_ARB_INT_EN 0x4000609eu +#define CYREG_USB_ARB_INT_SR 0x4000609fu +#define CYDEV_USB_ARB_EP3_BASE 0x400060a0u +#define CYDEV_USB_ARB_EP3_SIZE 0x00000003u +#define CYREG_USB_ARB_EP3_CFG 0x400060a0u +#define CYREG_USB_ARB_EP3_INT_EN 0x400060a1u +#define CYREG_USB_ARB_EP3_SR 0x400060a2u +#define CYDEV_USB_ARB_RW3_BASE 0x400060a4u +#define CYDEV_USB_ARB_RW3_SIZE 0x00000005u +#define CYREG_USB_ARB_RW3_WA 0x400060a4u +#define CYREG_USB_ARB_RW3_WA_MSB 0x400060a5u +#define CYREG_USB_ARB_RW3_RA 0x400060a6u +#define CYREG_USB_ARB_RW3_RA_MSB 0x400060a7u +#define CYREG_USB_ARB_RW3_DR 0x400060a8u +#define CYREG_USB_CWA 0x400060acu +#define CYREG_USB_CWA_MSB 0x400060adu +#define CYDEV_USB_ARB_EP4_BASE 0x400060b0u +#define CYDEV_USB_ARB_EP4_SIZE 0x00000003u +#define CYREG_USB_ARB_EP4_CFG 0x400060b0u +#define CYREG_USB_ARB_EP4_INT_EN 0x400060b1u +#define CYREG_USB_ARB_EP4_SR 0x400060b2u +#define CYDEV_USB_ARB_RW4_BASE 0x400060b4u +#define CYDEV_USB_ARB_RW4_SIZE 0x00000005u +#define CYREG_USB_ARB_RW4_WA 0x400060b4u +#define CYREG_USB_ARB_RW4_WA_MSB 0x400060b5u +#define CYREG_USB_ARB_RW4_RA 0x400060b6u +#define CYREG_USB_ARB_RW4_RA_MSB 0x400060b7u +#define CYREG_USB_ARB_RW4_DR 0x400060b8u +#define CYREG_USB_DMA_THRES 0x400060bcu +#define CYREG_USB_DMA_THRES_MSB 0x400060bdu +#define CYDEV_USB_ARB_EP5_BASE 0x400060c0u +#define CYDEV_USB_ARB_EP5_SIZE 0x00000003u +#define CYREG_USB_ARB_EP5_CFG 0x400060c0u +#define CYREG_USB_ARB_EP5_INT_EN 0x400060c1u +#define CYREG_USB_ARB_EP5_SR 0x400060c2u +#define CYDEV_USB_ARB_RW5_BASE 0x400060c4u +#define CYDEV_USB_ARB_RW5_SIZE 0x00000005u +#define CYREG_USB_ARB_RW5_WA 0x400060c4u +#define CYREG_USB_ARB_RW5_WA_MSB 0x400060c5u +#define CYREG_USB_ARB_RW5_RA 0x400060c6u +#define CYREG_USB_ARB_RW5_RA_MSB 0x400060c7u +#define CYREG_USB_ARB_RW5_DR 0x400060c8u +#define CYREG_USB_BUS_RST_CNT 0x400060ccu +#define CYDEV_USB_ARB_EP6_BASE 0x400060d0u +#define CYDEV_USB_ARB_EP6_SIZE 0x00000003u +#define CYREG_USB_ARB_EP6_CFG 0x400060d0u +#define CYREG_USB_ARB_EP6_INT_EN 0x400060d1u +#define CYREG_USB_ARB_EP6_SR 0x400060d2u +#define CYDEV_USB_ARB_RW6_BASE 0x400060d4u +#define CYDEV_USB_ARB_RW6_SIZE 0x00000005u +#define CYREG_USB_ARB_RW6_WA 0x400060d4u +#define CYREG_USB_ARB_RW6_WA_MSB 0x400060d5u +#define CYREG_USB_ARB_RW6_RA 0x400060d6u +#define CYREG_USB_ARB_RW6_RA_MSB 0x400060d7u +#define CYREG_USB_ARB_RW6_DR 0x400060d8u +#define CYDEV_USB_ARB_EP7_BASE 0x400060e0u +#define CYDEV_USB_ARB_EP7_SIZE 0x00000003u +#define CYREG_USB_ARB_EP7_CFG 0x400060e0u +#define CYREG_USB_ARB_EP7_INT_EN 0x400060e1u +#define CYREG_USB_ARB_EP7_SR 0x400060e2u +#define CYDEV_USB_ARB_RW7_BASE 0x400060e4u +#define CYDEV_USB_ARB_RW7_SIZE 0x00000005u +#define CYREG_USB_ARB_RW7_WA 0x400060e4u +#define CYREG_USB_ARB_RW7_WA_MSB 0x400060e5u +#define CYREG_USB_ARB_RW7_RA 0x400060e6u +#define CYREG_USB_ARB_RW7_RA_MSB 0x400060e7u +#define CYREG_USB_ARB_RW7_DR 0x400060e8u +#define CYDEV_USB_ARB_EP8_BASE 0x400060f0u +#define CYDEV_USB_ARB_EP8_SIZE 0x00000003u +#define CYREG_USB_ARB_EP8_CFG 0x400060f0u +#define CYREG_USB_ARB_EP8_INT_EN 0x400060f1u +#define CYREG_USB_ARB_EP8_SR 0x400060f2u +#define CYDEV_USB_ARB_RW8_BASE 0x400060f4u +#define CYDEV_USB_ARB_RW8_SIZE 0x00000005u +#define CYREG_USB_ARB_RW8_WA 0x400060f4u +#define CYREG_USB_ARB_RW8_WA_MSB 0x400060f5u +#define CYREG_USB_ARB_RW8_RA 0x400060f6u +#define CYREG_USB_ARB_RW8_RA_MSB 0x400060f7u +#define CYREG_USB_ARB_RW8_DR 0x400060f8u +#define CYDEV_USB_MEM_BASE 0x40006100u +#define CYDEV_USB_MEM_SIZE 0x00000200u +#define CYREG_USB_MEM_DATA_MBASE 0x40006100u +#define CYREG_USB_MEM_DATA_MSIZE 0x00000200u +#define CYDEV_UWRK_BASE 0x40006400u +#define CYDEV_UWRK_SIZE 0x00000b60u +#define CYDEV_UWRK_UWRK8_BASE 0x40006400u +#define CYDEV_UWRK_UWRK8_SIZE 0x000003b0u +#define CYDEV_UWRK_UWRK8_B0_BASE 0x40006400u +#define CYDEV_UWRK_UWRK8_B0_SIZE 0x000000b0u +#define CYREG_B0_UDB00_A0 0x40006400u +#define CYREG_B0_UDB01_A0 0x40006401u +#define CYREG_B0_UDB02_A0 0x40006402u +#define CYREG_B0_UDB03_A0 0x40006403u +#define CYREG_B0_UDB04_A0 0x40006404u +#define CYREG_B0_UDB05_A0 0x40006405u +#define CYREG_B0_UDB06_A0 0x40006406u +#define CYREG_B0_UDB07_A0 0x40006407u +#define CYREG_B0_UDB08_A0 0x40006408u +#define CYREG_B0_UDB09_A0 0x40006409u +#define CYREG_B0_UDB10_A0 0x4000640au +#define CYREG_B0_UDB11_A0 0x4000640bu +#define CYREG_B0_UDB12_A0 0x4000640cu +#define CYREG_B0_UDB13_A0 0x4000640du +#define CYREG_B0_UDB14_A0 0x4000640eu +#define CYREG_B0_UDB15_A0 0x4000640fu +#define CYREG_B0_UDB00_A1 0x40006410u +#define CYREG_B0_UDB01_A1 0x40006411u +#define CYREG_B0_UDB02_A1 0x40006412u +#define CYREG_B0_UDB03_A1 0x40006413u +#define CYREG_B0_UDB04_A1 0x40006414u +#define CYREG_B0_UDB05_A1 0x40006415u +#define CYREG_B0_UDB06_A1 0x40006416u +#define CYREG_B0_UDB07_A1 0x40006417u +#define CYREG_B0_UDB08_A1 0x40006418u +#define CYREG_B0_UDB09_A1 0x40006419u +#define CYREG_B0_UDB10_A1 0x4000641au +#define CYREG_B0_UDB11_A1 0x4000641bu +#define CYREG_B0_UDB12_A1 0x4000641cu +#define CYREG_B0_UDB13_A1 0x4000641du +#define CYREG_B0_UDB14_A1 0x4000641eu +#define CYREG_B0_UDB15_A1 0x4000641fu +#define CYREG_B0_UDB00_D0 0x40006420u +#define CYREG_B0_UDB01_D0 0x40006421u +#define CYREG_B0_UDB02_D0 0x40006422u +#define CYREG_B0_UDB03_D0 0x40006423u +#define CYREG_B0_UDB04_D0 0x40006424u +#define CYREG_B0_UDB05_D0 0x40006425u +#define CYREG_B0_UDB06_D0 0x40006426u +#define CYREG_B0_UDB07_D0 0x40006427u +#define CYREG_B0_UDB08_D0 0x40006428u +#define CYREG_B0_UDB09_D0 0x40006429u +#define CYREG_B0_UDB10_D0 0x4000642au +#define CYREG_B0_UDB11_D0 0x4000642bu +#define CYREG_B0_UDB12_D0 0x4000642cu +#define CYREG_B0_UDB13_D0 0x4000642du +#define CYREG_B0_UDB14_D0 0x4000642eu +#define CYREG_B0_UDB15_D0 0x4000642fu +#define CYREG_B0_UDB00_D1 0x40006430u +#define CYREG_B0_UDB01_D1 0x40006431u +#define CYREG_B0_UDB02_D1 0x40006432u +#define CYREG_B0_UDB03_D1 0x40006433u +#define CYREG_B0_UDB04_D1 0x40006434u +#define CYREG_B0_UDB05_D1 0x40006435u +#define CYREG_B0_UDB06_D1 0x40006436u +#define CYREG_B0_UDB07_D1 0x40006437u +#define CYREG_B0_UDB08_D1 0x40006438u +#define CYREG_B0_UDB09_D1 0x40006439u +#define CYREG_B0_UDB10_D1 0x4000643au +#define CYREG_B0_UDB11_D1 0x4000643bu +#define CYREG_B0_UDB12_D1 0x4000643cu +#define CYREG_B0_UDB13_D1 0x4000643du +#define CYREG_B0_UDB14_D1 0x4000643eu +#define CYREG_B0_UDB15_D1 0x4000643fu +#define CYREG_B0_UDB00_F0 0x40006440u +#define CYREG_B0_UDB01_F0 0x40006441u +#define CYREG_B0_UDB02_F0 0x40006442u +#define CYREG_B0_UDB03_F0 0x40006443u +#define CYREG_B0_UDB04_F0 0x40006444u +#define CYREG_B0_UDB05_F0 0x40006445u +#define CYREG_B0_UDB06_F0 0x40006446u +#define CYREG_B0_UDB07_F0 0x40006447u +#define CYREG_B0_UDB08_F0 0x40006448u +#define CYREG_B0_UDB09_F0 0x40006449u +#define CYREG_B0_UDB10_F0 0x4000644au +#define CYREG_B0_UDB11_F0 0x4000644bu +#define CYREG_B0_UDB12_F0 0x4000644cu +#define CYREG_B0_UDB13_F0 0x4000644du +#define CYREG_B0_UDB14_F0 0x4000644eu +#define CYREG_B0_UDB15_F0 0x4000644fu +#define CYREG_B0_UDB00_F1 0x40006450u +#define CYREG_B0_UDB01_F1 0x40006451u +#define CYREG_B0_UDB02_F1 0x40006452u +#define CYREG_B0_UDB03_F1 0x40006453u +#define CYREG_B0_UDB04_F1 0x40006454u +#define CYREG_B0_UDB05_F1 0x40006455u +#define CYREG_B0_UDB06_F1 0x40006456u +#define CYREG_B0_UDB07_F1 0x40006457u +#define CYREG_B0_UDB08_F1 0x40006458u +#define CYREG_B0_UDB09_F1 0x40006459u +#define CYREG_B0_UDB10_F1 0x4000645au +#define CYREG_B0_UDB11_F1 0x4000645bu +#define CYREG_B0_UDB12_F1 0x4000645cu +#define CYREG_B0_UDB13_F1 0x4000645du +#define CYREG_B0_UDB14_F1 0x4000645eu +#define CYREG_B0_UDB15_F1 0x4000645fu +#define CYREG_B0_UDB00_ST 0x40006460u +#define CYREG_B0_UDB01_ST 0x40006461u +#define CYREG_B0_UDB02_ST 0x40006462u +#define CYREG_B0_UDB03_ST 0x40006463u +#define CYREG_B0_UDB04_ST 0x40006464u +#define CYREG_B0_UDB05_ST 0x40006465u +#define CYREG_B0_UDB06_ST 0x40006466u +#define CYREG_B0_UDB07_ST 0x40006467u +#define CYREG_B0_UDB08_ST 0x40006468u +#define CYREG_B0_UDB09_ST 0x40006469u +#define CYREG_B0_UDB10_ST 0x4000646au +#define CYREG_B0_UDB11_ST 0x4000646bu +#define CYREG_B0_UDB12_ST 0x4000646cu +#define CYREG_B0_UDB13_ST 0x4000646du +#define CYREG_B0_UDB14_ST 0x4000646eu +#define CYREG_B0_UDB15_ST 0x4000646fu +#define CYREG_B0_UDB00_CTL 0x40006470u +#define CYREG_B0_UDB01_CTL 0x40006471u +#define CYREG_B0_UDB02_CTL 0x40006472u +#define CYREG_B0_UDB03_CTL 0x40006473u +#define CYREG_B0_UDB04_CTL 0x40006474u +#define CYREG_B0_UDB05_CTL 0x40006475u +#define CYREG_B0_UDB06_CTL 0x40006476u +#define CYREG_B0_UDB07_CTL 0x40006477u +#define CYREG_B0_UDB08_CTL 0x40006478u +#define CYREG_B0_UDB09_CTL 0x40006479u +#define CYREG_B0_UDB10_CTL 0x4000647au +#define CYREG_B0_UDB11_CTL 0x4000647bu +#define CYREG_B0_UDB12_CTL 0x4000647cu +#define CYREG_B0_UDB13_CTL 0x4000647du +#define CYREG_B0_UDB14_CTL 0x4000647eu +#define CYREG_B0_UDB15_CTL 0x4000647fu +#define CYREG_B0_UDB00_MSK 0x40006480u +#define CYREG_B0_UDB01_MSK 0x40006481u +#define CYREG_B0_UDB02_MSK 0x40006482u +#define CYREG_B0_UDB03_MSK 0x40006483u +#define CYREG_B0_UDB04_MSK 0x40006484u +#define CYREG_B0_UDB05_MSK 0x40006485u +#define CYREG_B0_UDB06_MSK 0x40006486u +#define CYREG_B0_UDB07_MSK 0x40006487u +#define CYREG_B0_UDB08_MSK 0x40006488u +#define CYREG_B0_UDB09_MSK 0x40006489u +#define CYREG_B0_UDB10_MSK 0x4000648au +#define CYREG_B0_UDB11_MSK 0x4000648bu +#define CYREG_B0_UDB12_MSK 0x4000648cu +#define CYREG_B0_UDB13_MSK 0x4000648du +#define CYREG_B0_UDB14_MSK 0x4000648eu +#define CYREG_B0_UDB15_MSK 0x4000648fu +#define CYREG_B0_UDB00_ACTL 0x40006490u +#define CYREG_B0_UDB01_ACTL 0x40006491u +#define CYREG_B0_UDB02_ACTL 0x40006492u +#define CYREG_B0_UDB03_ACTL 0x40006493u +#define CYREG_B0_UDB04_ACTL 0x40006494u +#define CYREG_B0_UDB05_ACTL 0x40006495u +#define CYREG_B0_UDB06_ACTL 0x40006496u +#define CYREG_B0_UDB07_ACTL 0x40006497u +#define CYREG_B0_UDB08_ACTL 0x40006498u +#define CYREG_B0_UDB09_ACTL 0x40006499u +#define CYREG_B0_UDB10_ACTL 0x4000649au +#define CYREG_B0_UDB11_ACTL 0x4000649bu +#define CYREG_B0_UDB12_ACTL 0x4000649cu +#define CYREG_B0_UDB13_ACTL 0x4000649du +#define CYREG_B0_UDB14_ACTL 0x4000649eu +#define CYREG_B0_UDB15_ACTL 0x4000649fu +#define CYREG_B0_UDB00_MC 0x400064a0u +#define CYREG_B0_UDB01_MC 0x400064a1u +#define CYREG_B0_UDB02_MC 0x400064a2u +#define CYREG_B0_UDB03_MC 0x400064a3u +#define CYREG_B0_UDB04_MC 0x400064a4u +#define CYREG_B0_UDB05_MC 0x400064a5u +#define CYREG_B0_UDB06_MC 0x400064a6u +#define CYREG_B0_UDB07_MC 0x400064a7u +#define CYREG_B0_UDB08_MC 0x400064a8u +#define CYREG_B0_UDB09_MC 0x400064a9u +#define CYREG_B0_UDB10_MC 0x400064aau +#define CYREG_B0_UDB11_MC 0x400064abu +#define CYREG_B0_UDB12_MC 0x400064acu +#define CYREG_B0_UDB13_MC 0x400064adu +#define CYREG_B0_UDB14_MC 0x400064aeu +#define CYREG_B0_UDB15_MC 0x400064afu +#define CYDEV_UWRK_UWRK8_B1_BASE 0x40006500u +#define CYDEV_UWRK_UWRK8_B1_SIZE 0x000000b0u +#define CYREG_B1_UDB04_A0 0x40006504u +#define CYREG_B1_UDB05_A0 0x40006505u +#define CYREG_B1_UDB06_A0 0x40006506u +#define CYREG_B1_UDB07_A0 0x40006507u +#define CYREG_B1_UDB08_A0 0x40006508u +#define CYREG_B1_UDB09_A0 0x40006509u +#define CYREG_B1_UDB10_A0 0x4000650au +#define CYREG_B1_UDB11_A0 0x4000650bu +#define CYREG_B1_UDB04_A1 0x40006514u +#define CYREG_B1_UDB05_A1 0x40006515u +#define CYREG_B1_UDB06_A1 0x40006516u +#define CYREG_B1_UDB07_A1 0x40006517u +#define CYREG_B1_UDB08_A1 0x40006518u +#define CYREG_B1_UDB09_A1 0x40006519u +#define CYREG_B1_UDB10_A1 0x4000651au +#define CYREG_B1_UDB11_A1 0x4000651bu +#define CYREG_B1_UDB04_D0 0x40006524u +#define CYREG_B1_UDB05_D0 0x40006525u +#define CYREG_B1_UDB06_D0 0x40006526u +#define CYREG_B1_UDB07_D0 0x40006527u +#define CYREG_B1_UDB08_D0 0x40006528u +#define CYREG_B1_UDB09_D0 0x40006529u +#define CYREG_B1_UDB10_D0 0x4000652au +#define CYREG_B1_UDB11_D0 0x4000652bu +#define CYREG_B1_UDB04_D1 0x40006534u +#define CYREG_B1_UDB05_D1 0x40006535u +#define CYREG_B1_UDB06_D1 0x40006536u +#define CYREG_B1_UDB07_D1 0x40006537u +#define CYREG_B1_UDB08_D1 0x40006538u +#define CYREG_B1_UDB09_D1 0x40006539u +#define CYREG_B1_UDB10_D1 0x4000653au +#define CYREG_B1_UDB11_D1 0x4000653bu +#define CYREG_B1_UDB04_F0 0x40006544u +#define CYREG_B1_UDB05_F0 0x40006545u +#define CYREG_B1_UDB06_F0 0x40006546u +#define CYREG_B1_UDB07_F0 0x40006547u +#define CYREG_B1_UDB08_F0 0x40006548u +#define CYREG_B1_UDB09_F0 0x40006549u +#define CYREG_B1_UDB10_F0 0x4000654au +#define CYREG_B1_UDB11_F0 0x4000654bu +#define CYREG_B1_UDB04_F1 0x40006554u +#define CYREG_B1_UDB05_F1 0x40006555u +#define CYREG_B1_UDB06_F1 0x40006556u +#define CYREG_B1_UDB07_F1 0x40006557u +#define CYREG_B1_UDB08_F1 0x40006558u +#define CYREG_B1_UDB09_F1 0x40006559u +#define CYREG_B1_UDB10_F1 0x4000655au +#define CYREG_B1_UDB11_F1 0x4000655bu +#define CYREG_B1_UDB04_ST 0x40006564u +#define CYREG_B1_UDB05_ST 0x40006565u +#define CYREG_B1_UDB06_ST 0x40006566u +#define CYREG_B1_UDB07_ST 0x40006567u +#define CYREG_B1_UDB08_ST 0x40006568u +#define CYREG_B1_UDB09_ST 0x40006569u +#define CYREG_B1_UDB10_ST 0x4000656au +#define CYREG_B1_UDB11_ST 0x4000656bu +#define CYREG_B1_UDB04_CTL 0x40006574u +#define CYREG_B1_UDB05_CTL 0x40006575u +#define CYREG_B1_UDB06_CTL 0x40006576u +#define CYREG_B1_UDB07_CTL 0x40006577u +#define CYREG_B1_UDB08_CTL 0x40006578u +#define CYREG_B1_UDB09_CTL 0x40006579u +#define CYREG_B1_UDB10_CTL 0x4000657au +#define CYREG_B1_UDB11_CTL 0x4000657bu +#define CYREG_B1_UDB04_MSK 0x40006584u +#define CYREG_B1_UDB05_MSK 0x40006585u +#define CYREG_B1_UDB06_MSK 0x40006586u +#define CYREG_B1_UDB07_MSK 0x40006587u +#define CYREG_B1_UDB08_MSK 0x40006588u +#define CYREG_B1_UDB09_MSK 0x40006589u +#define CYREG_B1_UDB10_MSK 0x4000658au +#define CYREG_B1_UDB11_MSK 0x4000658bu +#define CYREG_B1_UDB04_ACTL 0x40006594u +#define CYREG_B1_UDB05_ACTL 0x40006595u +#define CYREG_B1_UDB06_ACTL 0x40006596u +#define CYREG_B1_UDB07_ACTL 0x40006597u +#define CYREG_B1_UDB08_ACTL 0x40006598u +#define CYREG_B1_UDB09_ACTL 0x40006599u +#define CYREG_B1_UDB10_ACTL 0x4000659au +#define CYREG_B1_UDB11_ACTL 0x4000659bu +#define CYREG_B1_UDB04_MC 0x400065a4u +#define CYREG_B1_UDB05_MC 0x400065a5u +#define CYREG_B1_UDB06_MC 0x400065a6u +#define CYREG_B1_UDB07_MC 0x400065a7u +#define CYREG_B1_UDB08_MC 0x400065a8u +#define CYREG_B1_UDB09_MC 0x400065a9u +#define CYREG_B1_UDB10_MC 0x400065aau +#define CYREG_B1_UDB11_MC 0x400065abu +#define CYDEV_UWRK_UWRK16_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_SIZE 0x00000760u +#define CYDEV_UWRK_UWRK16_CAT_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_CAT_SIZE 0x00000760u +#define CYDEV_UWRK_UWRK16_CAT_B0_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_CAT_B0_SIZE 0x00000160u +#define CYREG_B0_UDB00_A0_A1 0x40006800u +#define CYREG_B0_UDB01_A0_A1 0x40006802u +#define CYREG_B0_UDB02_A0_A1 0x40006804u +#define CYREG_B0_UDB03_A0_A1 0x40006806u +#define CYREG_B0_UDB04_A0_A1 0x40006808u +#define CYREG_B0_UDB05_A0_A1 0x4000680au +#define CYREG_B0_UDB06_A0_A1 0x4000680cu +#define CYREG_B0_UDB07_A0_A1 0x4000680eu +#define CYREG_B0_UDB08_A0_A1 0x40006810u +#define CYREG_B0_UDB09_A0_A1 0x40006812u +#define CYREG_B0_UDB10_A0_A1 0x40006814u +#define CYREG_B0_UDB11_A0_A1 0x40006816u +#define CYREG_B0_UDB12_A0_A1 0x40006818u +#define CYREG_B0_UDB13_A0_A1 0x4000681au +#define CYREG_B0_UDB14_A0_A1 0x4000681cu +#define CYREG_B0_UDB15_A0_A1 0x4000681eu +#define CYREG_B0_UDB00_D0_D1 0x40006840u +#define CYREG_B0_UDB01_D0_D1 0x40006842u +#define CYREG_B0_UDB02_D0_D1 0x40006844u +#define CYREG_B0_UDB03_D0_D1 0x40006846u +#define CYREG_B0_UDB04_D0_D1 0x40006848u +#define CYREG_B0_UDB05_D0_D1 0x4000684au +#define CYREG_B0_UDB06_D0_D1 0x4000684cu +#define CYREG_B0_UDB07_D0_D1 0x4000684eu +#define CYREG_B0_UDB08_D0_D1 0x40006850u +#define CYREG_B0_UDB09_D0_D1 0x40006852u +#define CYREG_B0_UDB10_D0_D1 0x40006854u +#define CYREG_B0_UDB11_D0_D1 0x40006856u +#define CYREG_B0_UDB12_D0_D1 0x40006858u +#define CYREG_B0_UDB13_D0_D1 0x4000685au +#define CYREG_B0_UDB14_D0_D1 0x4000685cu +#define CYREG_B0_UDB15_D0_D1 0x4000685eu +#define CYREG_B0_UDB00_F0_F1 0x40006880u +#define CYREG_B0_UDB01_F0_F1 0x40006882u +#define CYREG_B0_UDB02_F0_F1 0x40006884u +#define CYREG_B0_UDB03_F0_F1 0x40006886u +#define CYREG_B0_UDB04_F0_F1 0x40006888u +#define CYREG_B0_UDB05_F0_F1 0x4000688au +#define CYREG_B0_UDB06_F0_F1 0x4000688cu +#define CYREG_B0_UDB07_F0_F1 0x4000688eu +#define CYREG_B0_UDB08_F0_F1 0x40006890u +#define CYREG_B0_UDB09_F0_F1 0x40006892u +#define CYREG_B0_UDB10_F0_F1 0x40006894u +#define CYREG_B0_UDB11_F0_F1 0x40006896u +#define CYREG_B0_UDB12_F0_F1 0x40006898u +#define CYREG_B0_UDB13_F0_F1 0x4000689au +#define CYREG_B0_UDB14_F0_F1 0x4000689cu +#define CYREG_B0_UDB15_F0_F1 0x4000689eu +#define CYREG_B0_UDB00_ST_CTL 0x400068c0u +#define CYREG_B0_UDB01_ST_CTL 0x400068c2u +#define CYREG_B0_UDB02_ST_CTL 0x400068c4u +#define CYREG_B0_UDB03_ST_CTL 0x400068c6u +#define CYREG_B0_UDB04_ST_CTL 0x400068c8u +#define CYREG_B0_UDB05_ST_CTL 0x400068cau +#define CYREG_B0_UDB06_ST_CTL 0x400068ccu +#define CYREG_B0_UDB07_ST_CTL 0x400068ceu +#define CYREG_B0_UDB08_ST_CTL 0x400068d0u +#define CYREG_B0_UDB09_ST_CTL 0x400068d2u +#define CYREG_B0_UDB10_ST_CTL 0x400068d4u +#define CYREG_B0_UDB11_ST_CTL 0x400068d6u +#define CYREG_B0_UDB12_ST_CTL 0x400068d8u +#define CYREG_B0_UDB13_ST_CTL 0x400068dau +#define CYREG_B0_UDB14_ST_CTL 0x400068dcu +#define CYREG_B0_UDB15_ST_CTL 0x400068deu +#define CYREG_B0_UDB00_MSK_ACTL 0x40006900u +#define CYREG_B0_UDB01_MSK_ACTL 0x40006902u +#define CYREG_B0_UDB02_MSK_ACTL 0x40006904u +#define CYREG_B0_UDB03_MSK_ACTL 0x40006906u +#define CYREG_B0_UDB04_MSK_ACTL 0x40006908u +#define CYREG_B0_UDB05_MSK_ACTL 0x4000690au +#define CYREG_B0_UDB06_MSK_ACTL 0x4000690cu +#define CYREG_B0_UDB07_MSK_ACTL 0x4000690eu +#define CYREG_B0_UDB08_MSK_ACTL 0x40006910u +#define CYREG_B0_UDB09_MSK_ACTL 0x40006912u +#define CYREG_B0_UDB10_MSK_ACTL 0x40006914u +#define CYREG_B0_UDB11_MSK_ACTL 0x40006916u +#define CYREG_B0_UDB12_MSK_ACTL 0x40006918u +#define CYREG_B0_UDB13_MSK_ACTL 0x4000691au +#define CYREG_B0_UDB14_MSK_ACTL 0x4000691cu +#define CYREG_B0_UDB15_MSK_ACTL 0x4000691eu +#define CYREG_B0_UDB00_MC_00 0x40006940u +#define CYREG_B0_UDB01_MC_00 0x40006942u +#define CYREG_B0_UDB02_MC_00 0x40006944u +#define CYREG_B0_UDB03_MC_00 0x40006946u +#define CYREG_B0_UDB04_MC_00 0x40006948u +#define CYREG_B0_UDB05_MC_00 0x4000694au +#define CYREG_B0_UDB06_MC_00 0x4000694cu +#define CYREG_B0_UDB07_MC_00 0x4000694eu +#define CYREG_B0_UDB08_MC_00 0x40006950u +#define CYREG_B0_UDB09_MC_00 0x40006952u +#define CYREG_B0_UDB10_MC_00 0x40006954u +#define CYREG_B0_UDB11_MC_00 0x40006956u +#define CYREG_B0_UDB12_MC_00 0x40006958u +#define CYREG_B0_UDB13_MC_00 0x4000695au +#define CYREG_B0_UDB14_MC_00 0x4000695cu +#define CYREG_B0_UDB15_MC_00 0x4000695eu +#define CYDEV_UWRK_UWRK16_CAT_B1_BASE 0x40006a00u +#define CYDEV_UWRK_UWRK16_CAT_B1_SIZE 0x00000160u +#define CYREG_B1_UDB04_A0_A1 0x40006a08u +#define CYREG_B1_UDB05_A0_A1 0x40006a0au +#define CYREG_B1_UDB06_A0_A1 0x40006a0cu +#define CYREG_B1_UDB07_A0_A1 0x40006a0eu +#define CYREG_B1_UDB08_A0_A1 0x40006a10u +#define CYREG_B1_UDB09_A0_A1 0x40006a12u +#define CYREG_B1_UDB10_A0_A1 0x40006a14u +#define CYREG_B1_UDB11_A0_A1 0x40006a16u +#define CYREG_B1_UDB04_D0_D1 0x40006a48u +#define CYREG_B1_UDB05_D0_D1 0x40006a4au +#define CYREG_B1_UDB06_D0_D1 0x40006a4cu +#define CYREG_B1_UDB07_D0_D1 0x40006a4eu +#define CYREG_B1_UDB08_D0_D1 0x40006a50u +#define CYREG_B1_UDB09_D0_D1 0x40006a52u +#define CYREG_B1_UDB10_D0_D1 0x40006a54u +#define CYREG_B1_UDB11_D0_D1 0x40006a56u +#define CYREG_B1_UDB04_F0_F1 0x40006a88u +#define CYREG_B1_UDB05_F0_F1 0x40006a8au +#define CYREG_B1_UDB06_F0_F1 0x40006a8cu +#define CYREG_B1_UDB07_F0_F1 0x40006a8eu +#define CYREG_B1_UDB08_F0_F1 0x40006a90u +#define CYREG_B1_UDB09_F0_F1 0x40006a92u +#define CYREG_B1_UDB10_F0_F1 0x40006a94u +#define CYREG_B1_UDB11_F0_F1 0x40006a96u +#define CYREG_B1_UDB04_ST_CTL 0x40006ac8u +#define CYREG_B1_UDB05_ST_CTL 0x40006acau +#define CYREG_B1_UDB06_ST_CTL 0x40006accu +#define CYREG_B1_UDB07_ST_CTL 0x40006aceu +#define CYREG_B1_UDB08_ST_CTL 0x40006ad0u +#define CYREG_B1_UDB09_ST_CTL 0x40006ad2u +#define CYREG_B1_UDB10_ST_CTL 0x40006ad4u +#define CYREG_B1_UDB11_ST_CTL 0x40006ad6u +#define CYREG_B1_UDB04_MSK_ACTL 0x40006b08u +#define CYREG_B1_UDB05_MSK_ACTL 0x40006b0au +#define CYREG_B1_UDB06_MSK_ACTL 0x40006b0cu +#define CYREG_B1_UDB07_MSK_ACTL 0x40006b0eu +#define CYREG_B1_UDB08_MSK_ACTL 0x40006b10u +#define CYREG_B1_UDB09_MSK_ACTL 0x40006b12u +#define CYREG_B1_UDB10_MSK_ACTL 0x40006b14u +#define CYREG_B1_UDB11_MSK_ACTL 0x40006b16u +#define CYREG_B1_UDB04_MC_00 0x40006b48u +#define CYREG_B1_UDB05_MC_00 0x40006b4au +#define CYREG_B1_UDB06_MC_00 0x40006b4cu +#define CYREG_B1_UDB07_MC_00 0x40006b4eu +#define CYREG_B1_UDB08_MC_00 0x40006b50u +#define CYREG_B1_UDB09_MC_00 0x40006b52u +#define CYREG_B1_UDB10_MC_00 0x40006b54u +#define CYREG_B1_UDB11_MC_00 0x40006b56u +#define CYDEV_UWRK_UWRK16_DEF_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_DEF_SIZE 0x0000075eu +#define CYDEV_UWRK_UWRK16_DEF_B0_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_DEF_B0_SIZE 0x0000015eu +#define CYREG_B0_UDB00_01_A0 0x40006800u +#define CYREG_B0_UDB01_02_A0 0x40006802u +#define CYREG_B0_UDB02_03_A0 0x40006804u +#define CYREG_B0_UDB03_04_A0 0x40006806u +#define CYREG_B0_UDB04_05_A0 0x40006808u +#define CYREG_B0_UDB05_06_A0 0x4000680au +#define CYREG_B0_UDB06_07_A0 0x4000680cu +#define CYREG_B0_UDB07_08_A0 0x4000680eu +#define CYREG_B0_UDB08_09_A0 0x40006810u +#define CYREG_B0_UDB09_10_A0 0x40006812u +#define CYREG_B0_UDB10_11_A0 0x40006814u +#define CYREG_B0_UDB11_12_A0 0x40006816u +#define CYREG_B0_UDB12_13_A0 0x40006818u +#define CYREG_B0_UDB13_14_A0 0x4000681au +#define CYREG_B0_UDB14_15_A0 0x4000681cu +#define CYREG_B0_UDB00_01_A1 0x40006820u +#define CYREG_B0_UDB01_02_A1 0x40006822u +#define CYREG_B0_UDB02_03_A1 0x40006824u +#define CYREG_B0_UDB03_04_A1 0x40006826u +#define CYREG_B0_UDB04_05_A1 0x40006828u +#define CYREG_B0_UDB05_06_A1 0x4000682au +#define CYREG_B0_UDB06_07_A1 0x4000682cu +#define CYREG_B0_UDB07_08_A1 0x4000682eu +#define CYREG_B0_UDB08_09_A1 0x40006830u +#define CYREG_B0_UDB09_10_A1 0x40006832u +#define CYREG_B0_UDB10_11_A1 0x40006834u +#define CYREG_B0_UDB11_12_A1 0x40006836u +#define CYREG_B0_UDB12_13_A1 0x40006838u +#define CYREG_B0_UDB13_14_A1 0x4000683au +#define CYREG_B0_UDB14_15_A1 0x4000683cu +#define CYREG_B0_UDB00_01_D0 0x40006840u +#define CYREG_B0_UDB01_02_D0 0x40006842u +#define CYREG_B0_UDB02_03_D0 0x40006844u +#define CYREG_B0_UDB03_04_D0 0x40006846u +#define CYREG_B0_UDB04_05_D0 0x40006848u +#define CYREG_B0_UDB05_06_D0 0x4000684au +#define CYREG_B0_UDB06_07_D0 0x4000684cu +#define CYREG_B0_UDB07_08_D0 0x4000684eu +#define CYREG_B0_UDB08_09_D0 0x40006850u +#define CYREG_B0_UDB09_10_D0 0x40006852u +#define CYREG_B0_UDB10_11_D0 0x40006854u +#define CYREG_B0_UDB11_12_D0 0x40006856u +#define CYREG_B0_UDB12_13_D0 0x40006858u +#define CYREG_B0_UDB13_14_D0 0x4000685au +#define CYREG_B0_UDB14_15_D0 0x4000685cu +#define CYREG_B0_UDB00_01_D1 0x40006860u +#define CYREG_B0_UDB01_02_D1 0x40006862u +#define CYREG_B0_UDB02_03_D1 0x40006864u +#define CYREG_B0_UDB03_04_D1 0x40006866u +#define CYREG_B0_UDB04_05_D1 0x40006868u +#define CYREG_B0_UDB05_06_D1 0x4000686au +#define CYREG_B0_UDB06_07_D1 0x4000686cu +#define CYREG_B0_UDB07_08_D1 0x4000686eu +#define CYREG_B0_UDB08_09_D1 0x40006870u +#define CYREG_B0_UDB09_10_D1 0x40006872u +#define CYREG_B0_UDB10_11_D1 0x40006874u +#define CYREG_B0_UDB11_12_D1 0x40006876u +#define CYREG_B0_UDB12_13_D1 0x40006878u +#define CYREG_B0_UDB13_14_D1 0x4000687au +#define CYREG_B0_UDB14_15_D1 0x4000687cu +#define CYREG_B0_UDB00_01_F0 0x40006880u +#define CYREG_B0_UDB01_02_F0 0x40006882u +#define CYREG_B0_UDB02_03_F0 0x40006884u +#define CYREG_B0_UDB03_04_F0 0x40006886u +#define CYREG_B0_UDB04_05_F0 0x40006888u +#define CYREG_B0_UDB05_06_F0 0x4000688au +#define CYREG_B0_UDB06_07_F0 0x4000688cu +#define CYREG_B0_UDB07_08_F0 0x4000688eu +#define CYREG_B0_UDB08_09_F0 0x40006890u +#define CYREG_B0_UDB09_10_F0 0x40006892u +#define CYREG_B0_UDB10_11_F0 0x40006894u +#define CYREG_B0_UDB11_12_F0 0x40006896u +#define CYREG_B0_UDB12_13_F0 0x40006898u +#define CYREG_B0_UDB13_14_F0 0x4000689au +#define CYREG_B0_UDB14_15_F0 0x4000689cu +#define CYREG_B0_UDB00_01_F1 0x400068a0u +#define CYREG_B0_UDB01_02_F1 0x400068a2u +#define CYREG_B0_UDB02_03_F1 0x400068a4u +#define CYREG_B0_UDB03_04_F1 0x400068a6u +#define CYREG_B0_UDB04_05_F1 0x400068a8u +#define CYREG_B0_UDB05_06_F1 0x400068aau +#define CYREG_B0_UDB06_07_F1 0x400068acu +#define CYREG_B0_UDB07_08_F1 0x400068aeu +#define CYREG_B0_UDB08_09_F1 0x400068b0u +#define CYREG_B0_UDB09_10_F1 0x400068b2u +#define CYREG_B0_UDB10_11_F1 0x400068b4u +#define CYREG_B0_UDB11_12_F1 0x400068b6u +#define CYREG_B0_UDB12_13_F1 0x400068b8u +#define CYREG_B0_UDB13_14_F1 0x400068bau +#define CYREG_B0_UDB14_15_F1 0x400068bcu +#define CYREG_B0_UDB00_01_ST 0x400068c0u +#define CYREG_B0_UDB01_02_ST 0x400068c2u +#define CYREG_B0_UDB02_03_ST 0x400068c4u +#define CYREG_B0_UDB03_04_ST 0x400068c6u +#define CYREG_B0_UDB04_05_ST 0x400068c8u +#define CYREG_B0_UDB05_06_ST 0x400068cau +#define CYREG_B0_UDB06_07_ST 0x400068ccu +#define CYREG_B0_UDB07_08_ST 0x400068ceu +#define CYREG_B0_UDB08_09_ST 0x400068d0u +#define CYREG_B0_UDB09_10_ST 0x400068d2u +#define CYREG_B0_UDB10_11_ST 0x400068d4u +#define CYREG_B0_UDB11_12_ST 0x400068d6u +#define CYREG_B0_UDB12_13_ST 0x400068d8u +#define CYREG_B0_UDB13_14_ST 0x400068dau +#define CYREG_B0_UDB14_15_ST 0x400068dcu +#define CYREG_B0_UDB00_01_CTL 0x400068e0u +#define CYREG_B0_UDB01_02_CTL 0x400068e2u +#define CYREG_B0_UDB02_03_CTL 0x400068e4u +#define CYREG_B0_UDB03_04_CTL 0x400068e6u +#define CYREG_B0_UDB04_05_CTL 0x400068e8u +#define CYREG_B0_UDB05_06_CTL 0x400068eau +#define CYREG_B0_UDB06_07_CTL 0x400068ecu +#define CYREG_B0_UDB07_08_CTL 0x400068eeu +#define CYREG_B0_UDB08_09_CTL 0x400068f0u +#define CYREG_B0_UDB09_10_CTL 0x400068f2u +#define CYREG_B0_UDB10_11_CTL 0x400068f4u +#define CYREG_B0_UDB11_12_CTL 0x400068f6u +#define CYREG_B0_UDB12_13_CTL 0x400068f8u +#define CYREG_B0_UDB13_14_CTL 0x400068fau +#define CYREG_B0_UDB14_15_CTL 0x400068fcu +#define CYREG_B0_UDB00_01_MSK 0x40006900u +#define CYREG_B0_UDB01_02_MSK 0x40006902u +#define CYREG_B0_UDB02_03_MSK 0x40006904u +#define CYREG_B0_UDB03_04_MSK 0x40006906u +#define CYREG_B0_UDB04_05_MSK 0x40006908u +#define CYREG_B0_UDB05_06_MSK 0x4000690au +#define CYREG_B0_UDB06_07_MSK 0x4000690cu +#define CYREG_B0_UDB07_08_MSK 0x4000690eu +#define CYREG_B0_UDB08_09_MSK 0x40006910u +#define CYREG_B0_UDB09_10_MSK 0x40006912u +#define CYREG_B0_UDB10_11_MSK 0x40006914u +#define CYREG_B0_UDB11_12_MSK 0x40006916u +#define CYREG_B0_UDB12_13_MSK 0x40006918u +#define CYREG_B0_UDB13_14_MSK 0x4000691au +#define CYREG_B0_UDB14_15_MSK 0x4000691cu +#define CYREG_B0_UDB00_01_ACTL 0x40006920u +#define CYREG_B0_UDB01_02_ACTL 0x40006922u +#define CYREG_B0_UDB02_03_ACTL 0x40006924u +#define CYREG_B0_UDB03_04_ACTL 0x40006926u +#define CYREG_B0_UDB04_05_ACTL 0x40006928u +#define CYREG_B0_UDB05_06_ACTL 0x4000692au +#define CYREG_B0_UDB06_07_ACTL 0x4000692cu +#define CYREG_B0_UDB07_08_ACTL 0x4000692eu +#define CYREG_B0_UDB08_09_ACTL 0x40006930u +#define CYREG_B0_UDB09_10_ACTL 0x40006932u +#define CYREG_B0_UDB10_11_ACTL 0x40006934u +#define CYREG_B0_UDB11_12_ACTL 0x40006936u +#define CYREG_B0_UDB12_13_ACTL 0x40006938u +#define CYREG_B0_UDB13_14_ACTL 0x4000693au +#define CYREG_B0_UDB14_15_ACTL 0x4000693cu +#define CYREG_B0_UDB00_01_MC 0x40006940u +#define CYREG_B0_UDB01_02_MC 0x40006942u +#define CYREG_B0_UDB02_03_MC 0x40006944u +#define CYREG_B0_UDB03_04_MC 0x40006946u +#define CYREG_B0_UDB04_05_MC 0x40006948u +#define CYREG_B0_UDB05_06_MC 0x4000694au +#define CYREG_B0_UDB06_07_MC 0x4000694cu +#define CYREG_B0_UDB07_08_MC 0x4000694eu +#define CYREG_B0_UDB08_09_MC 0x40006950u +#define CYREG_B0_UDB09_10_MC 0x40006952u +#define CYREG_B0_UDB10_11_MC 0x40006954u +#define CYREG_B0_UDB11_12_MC 0x40006956u +#define CYREG_B0_UDB12_13_MC 0x40006958u +#define CYREG_B0_UDB13_14_MC 0x4000695au +#define CYREG_B0_UDB14_15_MC 0x4000695cu +#define CYDEV_UWRK_UWRK16_DEF_B1_BASE 0x40006a00u +#define CYDEV_UWRK_UWRK16_DEF_B1_SIZE 0x0000015eu +#define CYREG_B1_UDB04_05_A0 0x40006a08u +#define CYREG_B1_UDB05_06_A0 0x40006a0au +#define CYREG_B1_UDB06_07_A0 0x40006a0cu +#define CYREG_B1_UDB07_08_A0 0x40006a0eu +#define CYREG_B1_UDB08_09_A0 0x40006a10u +#define CYREG_B1_UDB09_10_A0 0x40006a12u +#define CYREG_B1_UDB10_11_A0 0x40006a14u +#define CYREG_B1_UDB11_12_A0 0x40006a16u +#define CYREG_B1_UDB04_05_A1 0x40006a28u +#define CYREG_B1_UDB05_06_A1 0x40006a2au +#define CYREG_B1_UDB06_07_A1 0x40006a2cu +#define CYREG_B1_UDB07_08_A1 0x40006a2eu +#define CYREG_B1_UDB08_09_A1 0x40006a30u +#define CYREG_B1_UDB09_10_A1 0x40006a32u +#define CYREG_B1_UDB10_11_A1 0x40006a34u +#define CYREG_B1_UDB11_12_A1 0x40006a36u +#define CYREG_B1_UDB04_05_D0 0x40006a48u +#define CYREG_B1_UDB05_06_D0 0x40006a4au +#define CYREG_B1_UDB06_07_D0 0x40006a4cu +#define CYREG_B1_UDB07_08_D0 0x40006a4eu +#define CYREG_B1_UDB08_09_D0 0x40006a50u +#define CYREG_B1_UDB09_10_D0 0x40006a52u +#define CYREG_B1_UDB10_11_D0 0x40006a54u +#define CYREG_B1_UDB11_12_D0 0x40006a56u +#define CYREG_B1_UDB04_05_D1 0x40006a68u +#define CYREG_B1_UDB05_06_D1 0x40006a6au +#define CYREG_B1_UDB06_07_D1 0x40006a6cu +#define CYREG_B1_UDB07_08_D1 0x40006a6eu +#define CYREG_B1_UDB08_09_D1 0x40006a70u +#define CYREG_B1_UDB09_10_D1 0x40006a72u +#define CYREG_B1_UDB10_11_D1 0x40006a74u +#define CYREG_B1_UDB11_12_D1 0x40006a76u +#define CYREG_B1_UDB04_05_F0 0x40006a88u +#define CYREG_B1_UDB05_06_F0 0x40006a8au +#define CYREG_B1_UDB06_07_F0 0x40006a8cu +#define CYREG_B1_UDB07_08_F0 0x40006a8eu +#define CYREG_B1_UDB08_09_F0 0x40006a90u +#define CYREG_B1_UDB09_10_F0 0x40006a92u +#define CYREG_B1_UDB10_11_F0 0x40006a94u +#define CYREG_B1_UDB11_12_F0 0x40006a96u +#define CYREG_B1_UDB04_05_F1 0x40006aa8u +#define CYREG_B1_UDB05_06_F1 0x40006aaau +#define CYREG_B1_UDB06_07_F1 0x40006aacu +#define CYREG_B1_UDB07_08_F1 0x40006aaeu +#define CYREG_B1_UDB08_09_F1 0x40006ab0u +#define CYREG_B1_UDB09_10_F1 0x40006ab2u +#define CYREG_B1_UDB10_11_F1 0x40006ab4u +#define CYREG_B1_UDB11_12_F1 0x40006ab6u +#define CYREG_B1_UDB04_05_ST 0x40006ac8u +#define CYREG_B1_UDB05_06_ST 0x40006acau +#define CYREG_B1_UDB06_07_ST 0x40006accu +#define CYREG_B1_UDB07_08_ST 0x40006aceu +#define CYREG_B1_UDB08_09_ST 0x40006ad0u +#define CYREG_B1_UDB09_10_ST 0x40006ad2u +#define CYREG_B1_UDB10_11_ST 0x40006ad4u +#define CYREG_B1_UDB11_12_ST 0x40006ad6u +#define CYREG_B1_UDB04_05_CTL 0x40006ae8u +#define CYREG_B1_UDB05_06_CTL 0x40006aeau +#define CYREG_B1_UDB06_07_CTL 0x40006aecu +#define CYREG_B1_UDB07_08_CTL 0x40006aeeu +#define CYREG_B1_UDB08_09_CTL 0x40006af0u +#define CYREG_B1_UDB09_10_CTL 0x40006af2u +#define CYREG_B1_UDB10_11_CTL 0x40006af4u +#define CYREG_B1_UDB11_12_CTL 0x40006af6u +#define CYREG_B1_UDB04_05_MSK 0x40006b08u +#define CYREG_B1_UDB05_06_MSK 0x40006b0au +#define CYREG_B1_UDB06_07_MSK 0x40006b0cu +#define CYREG_B1_UDB07_08_MSK 0x40006b0eu +#define CYREG_B1_UDB08_09_MSK 0x40006b10u +#define CYREG_B1_UDB09_10_MSK 0x40006b12u +#define CYREG_B1_UDB10_11_MSK 0x40006b14u +#define CYREG_B1_UDB11_12_MSK 0x40006b16u +#define CYREG_B1_UDB04_05_ACTL 0x40006b28u +#define CYREG_B1_UDB05_06_ACTL 0x40006b2au +#define CYREG_B1_UDB06_07_ACTL 0x40006b2cu +#define CYREG_B1_UDB07_08_ACTL 0x40006b2eu +#define CYREG_B1_UDB08_09_ACTL 0x40006b30u +#define CYREG_B1_UDB09_10_ACTL 0x40006b32u +#define CYREG_B1_UDB10_11_ACTL 0x40006b34u +#define CYREG_B1_UDB11_12_ACTL 0x40006b36u +#define CYREG_B1_UDB04_05_MC 0x40006b48u +#define CYREG_B1_UDB05_06_MC 0x40006b4au +#define CYREG_B1_UDB06_07_MC 0x40006b4cu +#define CYREG_B1_UDB07_08_MC 0x40006b4eu +#define CYREG_B1_UDB08_09_MC 0x40006b50u +#define CYREG_B1_UDB09_10_MC 0x40006b52u +#define CYREG_B1_UDB10_11_MC 0x40006b54u +#define CYREG_B1_UDB11_12_MC 0x40006b56u +#define CYDEV_PHUB_BASE 0x40007000u +#define CYDEV_PHUB_SIZE 0x00000c00u +#define CYREG_PHUB_CFG 0x40007000u +#define CYREG_PHUB_ERR 0x40007004u +#define CYREG_PHUB_ERR_ADR 0x40007008u +#define CYDEV_PHUB_CH0_BASE 0x40007010u +#define CYDEV_PHUB_CH0_SIZE 0x0000000cu +#define CYREG_PHUB_CH0_BASIC_CFG 0x40007010u +#define CYREG_PHUB_CH0_ACTION 0x40007014u +#define CYREG_PHUB_CH0_BASIC_STATUS 0x40007018u +#define CYDEV_PHUB_CH1_BASE 0x40007020u +#define CYDEV_PHUB_CH1_SIZE 0x0000000cu +#define CYREG_PHUB_CH1_BASIC_CFG 0x40007020u +#define CYREG_PHUB_CH1_ACTION 0x40007024u +#define CYREG_PHUB_CH1_BASIC_STATUS 0x40007028u +#define CYDEV_PHUB_CH2_BASE 0x40007030u +#define CYDEV_PHUB_CH2_SIZE 0x0000000cu +#define CYREG_PHUB_CH2_BASIC_CFG 0x40007030u +#define CYREG_PHUB_CH2_ACTION 0x40007034u +#define CYREG_PHUB_CH2_BASIC_STATUS 0x40007038u +#define CYDEV_PHUB_CH3_BASE 0x40007040u +#define CYDEV_PHUB_CH3_SIZE 0x0000000cu +#define CYREG_PHUB_CH3_BASIC_CFG 0x40007040u +#define CYREG_PHUB_CH3_ACTION 0x40007044u +#define CYREG_PHUB_CH3_BASIC_STATUS 0x40007048u +#define CYDEV_PHUB_CH4_BASE 0x40007050u +#define CYDEV_PHUB_CH4_SIZE 0x0000000cu +#define CYREG_PHUB_CH4_BASIC_CFG 0x40007050u +#define CYREG_PHUB_CH4_ACTION 0x40007054u +#define CYREG_PHUB_CH4_BASIC_STATUS 0x40007058u +#define CYDEV_PHUB_CH5_BASE 0x40007060u +#define CYDEV_PHUB_CH5_SIZE 0x0000000cu +#define CYREG_PHUB_CH5_BASIC_CFG 0x40007060u +#define CYREG_PHUB_CH5_ACTION 0x40007064u +#define CYREG_PHUB_CH5_BASIC_STATUS 0x40007068u +#define CYDEV_PHUB_CH6_BASE 0x40007070u +#define CYDEV_PHUB_CH6_SIZE 0x0000000cu +#define CYREG_PHUB_CH6_BASIC_CFG 0x40007070u +#define CYREG_PHUB_CH6_ACTION 0x40007074u +#define CYREG_PHUB_CH6_BASIC_STATUS 0x40007078u +#define CYDEV_PHUB_CH7_BASE 0x40007080u +#define CYDEV_PHUB_CH7_SIZE 0x0000000cu +#define CYREG_PHUB_CH7_BASIC_CFG 0x40007080u +#define CYREG_PHUB_CH7_ACTION 0x40007084u +#define CYREG_PHUB_CH7_BASIC_STATUS 0x40007088u +#define CYDEV_PHUB_CH8_BASE 0x40007090u +#define CYDEV_PHUB_CH8_SIZE 0x0000000cu +#define CYREG_PHUB_CH8_BASIC_CFG 0x40007090u +#define CYREG_PHUB_CH8_ACTION 0x40007094u +#define CYREG_PHUB_CH8_BASIC_STATUS 0x40007098u +#define CYDEV_PHUB_CH9_BASE 0x400070a0u +#define CYDEV_PHUB_CH9_SIZE 0x0000000cu +#define CYREG_PHUB_CH9_BASIC_CFG 0x400070a0u +#define CYREG_PHUB_CH9_ACTION 0x400070a4u +#define CYREG_PHUB_CH9_BASIC_STATUS 0x400070a8u +#define CYDEV_PHUB_CH10_BASE 0x400070b0u +#define CYDEV_PHUB_CH10_SIZE 0x0000000cu +#define CYREG_PHUB_CH10_BASIC_CFG 0x400070b0u +#define CYREG_PHUB_CH10_ACTION 0x400070b4u +#define CYREG_PHUB_CH10_BASIC_STATUS 0x400070b8u +#define CYDEV_PHUB_CH11_BASE 0x400070c0u +#define CYDEV_PHUB_CH11_SIZE 0x0000000cu +#define CYREG_PHUB_CH11_BASIC_CFG 0x400070c0u +#define CYREG_PHUB_CH11_ACTION 0x400070c4u +#define CYREG_PHUB_CH11_BASIC_STATUS 0x400070c8u +#define CYDEV_PHUB_CH12_BASE 0x400070d0u +#define CYDEV_PHUB_CH12_SIZE 0x0000000cu +#define CYREG_PHUB_CH12_BASIC_CFG 0x400070d0u +#define CYREG_PHUB_CH12_ACTION 0x400070d4u +#define CYREG_PHUB_CH12_BASIC_STATUS 0x400070d8u +#define CYDEV_PHUB_CH13_BASE 0x400070e0u +#define CYDEV_PHUB_CH13_SIZE 0x0000000cu +#define CYREG_PHUB_CH13_BASIC_CFG 0x400070e0u +#define CYREG_PHUB_CH13_ACTION 0x400070e4u +#define CYREG_PHUB_CH13_BASIC_STATUS 0x400070e8u +#define CYDEV_PHUB_CH14_BASE 0x400070f0u +#define CYDEV_PHUB_CH14_SIZE 0x0000000cu +#define CYREG_PHUB_CH14_BASIC_CFG 0x400070f0u +#define CYREG_PHUB_CH14_ACTION 0x400070f4u +#define CYREG_PHUB_CH14_BASIC_STATUS 0x400070f8u +#define CYDEV_PHUB_CH15_BASE 0x40007100u +#define CYDEV_PHUB_CH15_SIZE 0x0000000cu +#define CYREG_PHUB_CH15_BASIC_CFG 0x40007100u +#define CYREG_PHUB_CH15_ACTION 0x40007104u +#define CYREG_PHUB_CH15_BASIC_STATUS 0x40007108u +#define CYDEV_PHUB_CH16_BASE 0x40007110u +#define CYDEV_PHUB_CH16_SIZE 0x0000000cu +#define CYREG_PHUB_CH16_BASIC_CFG 0x40007110u +#define CYREG_PHUB_CH16_ACTION 0x40007114u +#define CYREG_PHUB_CH16_BASIC_STATUS 0x40007118u +#define CYDEV_PHUB_CH17_BASE 0x40007120u +#define CYDEV_PHUB_CH17_SIZE 0x0000000cu +#define CYREG_PHUB_CH17_BASIC_CFG 0x40007120u +#define CYREG_PHUB_CH17_ACTION 0x40007124u +#define CYREG_PHUB_CH17_BASIC_STATUS 0x40007128u +#define CYDEV_PHUB_CH18_BASE 0x40007130u +#define CYDEV_PHUB_CH18_SIZE 0x0000000cu +#define CYREG_PHUB_CH18_BASIC_CFG 0x40007130u +#define CYREG_PHUB_CH18_ACTION 0x40007134u +#define CYREG_PHUB_CH18_BASIC_STATUS 0x40007138u +#define CYDEV_PHUB_CH19_BASE 0x40007140u +#define CYDEV_PHUB_CH19_SIZE 0x0000000cu +#define CYREG_PHUB_CH19_BASIC_CFG 0x40007140u +#define CYREG_PHUB_CH19_ACTION 0x40007144u +#define CYREG_PHUB_CH19_BASIC_STATUS 0x40007148u +#define CYDEV_PHUB_CH20_BASE 0x40007150u +#define CYDEV_PHUB_CH20_SIZE 0x0000000cu +#define CYREG_PHUB_CH20_BASIC_CFG 0x40007150u +#define CYREG_PHUB_CH20_ACTION 0x40007154u +#define CYREG_PHUB_CH20_BASIC_STATUS 0x40007158u +#define CYDEV_PHUB_CH21_BASE 0x40007160u +#define CYDEV_PHUB_CH21_SIZE 0x0000000cu +#define CYREG_PHUB_CH21_BASIC_CFG 0x40007160u +#define CYREG_PHUB_CH21_ACTION 0x40007164u +#define CYREG_PHUB_CH21_BASIC_STATUS 0x40007168u +#define CYDEV_PHUB_CH22_BASE 0x40007170u +#define CYDEV_PHUB_CH22_SIZE 0x0000000cu +#define CYREG_PHUB_CH22_BASIC_CFG 0x40007170u +#define CYREG_PHUB_CH22_ACTION 0x40007174u +#define CYREG_PHUB_CH22_BASIC_STATUS 0x40007178u +#define CYDEV_PHUB_CH23_BASE 0x40007180u +#define CYDEV_PHUB_CH23_SIZE 0x0000000cu +#define CYREG_PHUB_CH23_BASIC_CFG 0x40007180u +#define CYREG_PHUB_CH23_ACTION 0x40007184u +#define CYREG_PHUB_CH23_BASIC_STATUS 0x40007188u +#define CYDEV_PHUB_CFGMEM0_BASE 0x40007600u +#define CYDEV_PHUB_CFGMEM0_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM0_CFG0 0x40007600u +#define CYREG_PHUB_CFGMEM0_CFG1 0x40007604u +#define CYDEV_PHUB_CFGMEM1_BASE 0x40007608u +#define CYDEV_PHUB_CFGMEM1_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM1_CFG0 0x40007608u +#define CYREG_PHUB_CFGMEM1_CFG1 0x4000760cu +#define CYDEV_PHUB_CFGMEM2_BASE 0x40007610u +#define CYDEV_PHUB_CFGMEM2_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM2_CFG0 0x40007610u +#define CYREG_PHUB_CFGMEM2_CFG1 0x40007614u +#define CYDEV_PHUB_CFGMEM3_BASE 0x40007618u +#define CYDEV_PHUB_CFGMEM3_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM3_CFG0 0x40007618u +#define CYREG_PHUB_CFGMEM3_CFG1 0x4000761cu +#define CYDEV_PHUB_CFGMEM4_BASE 0x40007620u +#define CYDEV_PHUB_CFGMEM4_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM4_CFG0 0x40007620u +#define CYREG_PHUB_CFGMEM4_CFG1 0x40007624u +#define CYDEV_PHUB_CFGMEM5_BASE 0x40007628u +#define CYDEV_PHUB_CFGMEM5_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM5_CFG0 0x40007628u +#define CYREG_PHUB_CFGMEM5_CFG1 0x4000762cu +#define CYDEV_PHUB_CFGMEM6_BASE 0x40007630u +#define CYDEV_PHUB_CFGMEM6_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM6_CFG0 0x40007630u +#define CYREG_PHUB_CFGMEM6_CFG1 0x40007634u +#define CYDEV_PHUB_CFGMEM7_BASE 0x40007638u +#define CYDEV_PHUB_CFGMEM7_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM7_CFG0 0x40007638u +#define CYREG_PHUB_CFGMEM7_CFG1 0x4000763cu +#define CYDEV_PHUB_CFGMEM8_BASE 0x40007640u +#define CYDEV_PHUB_CFGMEM8_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM8_CFG0 0x40007640u +#define CYREG_PHUB_CFGMEM8_CFG1 0x40007644u +#define CYDEV_PHUB_CFGMEM9_BASE 0x40007648u +#define CYDEV_PHUB_CFGMEM9_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM9_CFG0 0x40007648u +#define CYREG_PHUB_CFGMEM9_CFG1 0x4000764cu +#define CYDEV_PHUB_CFGMEM10_BASE 0x40007650u +#define CYDEV_PHUB_CFGMEM10_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM10_CFG0 0x40007650u +#define CYREG_PHUB_CFGMEM10_CFG1 0x40007654u +#define CYDEV_PHUB_CFGMEM11_BASE 0x40007658u +#define CYDEV_PHUB_CFGMEM11_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM11_CFG0 0x40007658u +#define CYREG_PHUB_CFGMEM11_CFG1 0x4000765cu +#define CYDEV_PHUB_CFGMEM12_BASE 0x40007660u +#define CYDEV_PHUB_CFGMEM12_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM12_CFG0 0x40007660u +#define CYREG_PHUB_CFGMEM12_CFG1 0x40007664u +#define CYDEV_PHUB_CFGMEM13_BASE 0x40007668u +#define CYDEV_PHUB_CFGMEM13_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM13_CFG0 0x40007668u +#define CYREG_PHUB_CFGMEM13_CFG1 0x4000766cu +#define CYDEV_PHUB_CFGMEM14_BASE 0x40007670u +#define CYDEV_PHUB_CFGMEM14_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM14_CFG0 0x40007670u +#define CYREG_PHUB_CFGMEM14_CFG1 0x40007674u +#define CYDEV_PHUB_CFGMEM15_BASE 0x40007678u +#define CYDEV_PHUB_CFGMEM15_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM15_CFG0 0x40007678u +#define CYREG_PHUB_CFGMEM15_CFG1 0x4000767cu +#define CYDEV_PHUB_CFGMEM16_BASE 0x40007680u +#define CYDEV_PHUB_CFGMEM16_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM16_CFG0 0x40007680u +#define CYREG_PHUB_CFGMEM16_CFG1 0x40007684u +#define CYDEV_PHUB_CFGMEM17_BASE 0x40007688u +#define CYDEV_PHUB_CFGMEM17_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM17_CFG0 0x40007688u +#define CYREG_PHUB_CFGMEM17_CFG1 0x4000768cu +#define CYDEV_PHUB_CFGMEM18_BASE 0x40007690u +#define CYDEV_PHUB_CFGMEM18_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM18_CFG0 0x40007690u +#define CYREG_PHUB_CFGMEM18_CFG1 0x40007694u +#define CYDEV_PHUB_CFGMEM19_BASE 0x40007698u +#define CYDEV_PHUB_CFGMEM19_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM19_CFG0 0x40007698u +#define CYREG_PHUB_CFGMEM19_CFG1 0x4000769cu +#define CYDEV_PHUB_CFGMEM20_BASE 0x400076a0u +#define CYDEV_PHUB_CFGMEM20_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM20_CFG0 0x400076a0u +#define CYREG_PHUB_CFGMEM20_CFG1 0x400076a4u +#define CYDEV_PHUB_CFGMEM21_BASE 0x400076a8u +#define CYDEV_PHUB_CFGMEM21_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM21_CFG0 0x400076a8u +#define CYREG_PHUB_CFGMEM21_CFG1 0x400076acu +#define CYDEV_PHUB_CFGMEM22_BASE 0x400076b0u +#define CYDEV_PHUB_CFGMEM22_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM22_CFG0 0x400076b0u +#define CYREG_PHUB_CFGMEM22_CFG1 0x400076b4u +#define CYDEV_PHUB_CFGMEM23_BASE 0x400076b8u +#define CYDEV_PHUB_CFGMEM23_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM23_CFG0 0x400076b8u +#define CYREG_PHUB_CFGMEM23_CFG1 0x400076bcu +#define CYDEV_PHUB_TDMEM0_BASE 0x40007800u +#define CYDEV_PHUB_TDMEM0_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM0_ORIG_TD0 0x40007800u +#define CYREG_PHUB_TDMEM0_ORIG_TD1 0x40007804u +#define CYDEV_PHUB_TDMEM1_BASE 0x40007808u +#define CYDEV_PHUB_TDMEM1_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM1_ORIG_TD0 0x40007808u +#define CYREG_PHUB_TDMEM1_ORIG_TD1 0x4000780cu +#define CYDEV_PHUB_TDMEM2_BASE 0x40007810u +#define CYDEV_PHUB_TDMEM2_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM2_ORIG_TD0 0x40007810u +#define CYREG_PHUB_TDMEM2_ORIG_TD1 0x40007814u +#define CYDEV_PHUB_TDMEM3_BASE 0x40007818u +#define CYDEV_PHUB_TDMEM3_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM3_ORIG_TD0 0x40007818u +#define CYREG_PHUB_TDMEM3_ORIG_TD1 0x4000781cu +#define CYDEV_PHUB_TDMEM4_BASE 0x40007820u +#define CYDEV_PHUB_TDMEM4_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM4_ORIG_TD0 0x40007820u +#define CYREG_PHUB_TDMEM4_ORIG_TD1 0x40007824u +#define CYDEV_PHUB_TDMEM5_BASE 0x40007828u +#define CYDEV_PHUB_TDMEM5_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM5_ORIG_TD0 0x40007828u +#define CYREG_PHUB_TDMEM5_ORIG_TD1 0x4000782cu +#define CYDEV_PHUB_TDMEM6_BASE 0x40007830u +#define CYDEV_PHUB_TDMEM6_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM6_ORIG_TD0 0x40007830u +#define CYREG_PHUB_TDMEM6_ORIG_TD1 0x40007834u +#define CYDEV_PHUB_TDMEM7_BASE 0x40007838u +#define CYDEV_PHUB_TDMEM7_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM7_ORIG_TD0 0x40007838u +#define CYREG_PHUB_TDMEM7_ORIG_TD1 0x4000783cu +#define CYDEV_PHUB_TDMEM8_BASE 0x40007840u +#define CYDEV_PHUB_TDMEM8_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM8_ORIG_TD0 0x40007840u +#define CYREG_PHUB_TDMEM8_ORIG_TD1 0x40007844u +#define CYDEV_PHUB_TDMEM9_BASE 0x40007848u +#define CYDEV_PHUB_TDMEM9_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM9_ORIG_TD0 0x40007848u +#define CYREG_PHUB_TDMEM9_ORIG_TD1 0x4000784cu +#define CYDEV_PHUB_TDMEM10_BASE 0x40007850u +#define CYDEV_PHUB_TDMEM10_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM10_ORIG_TD0 0x40007850u +#define CYREG_PHUB_TDMEM10_ORIG_TD1 0x40007854u +#define CYDEV_PHUB_TDMEM11_BASE 0x40007858u +#define CYDEV_PHUB_TDMEM11_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM11_ORIG_TD0 0x40007858u +#define CYREG_PHUB_TDMEM11_ORIG_TD1 0x4000785cu +#define CYDEV_PHUB_TDMEM12_BASE 0x40007860u +#define CYDEV_PHUB_TDMEM12_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM12_ORIG_TD0 0x40007860u +#define CYREG_PHUB_TDMEM12_ORIG_TD1 0x40007864u +#define CYDEV_PHUB_TDMEM13_BASE 0x40007868u +#define CYDEV_PHUB_TDMEM13_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM13_ORIG_TD0 0x40007868u +#define CYREG_PHUB_TDMEM13_ORIG_TD1 0x4000786cu +#define CYDEV_PHUB_TDMEM14_BASE 0x40007870u +#define CYDEV_PHUB_TDMEM14_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM14_ORIG_TD0 0x40007870u +#define CYREG_PHUB_TDMEM14_ORIG_TD1 0x40007874u +#define CYDEV_PHUB_TDMEM15_BASE 0x40007878u +#define CYDEV_PHUB_TDMEM15_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM15_ORIG_TD0 0x40007878u +#define CYREG_PHUB_TDMEM15_ORIG_TD1 0x4000787cu +#define CYDEV_PHUB_TDMEM16_BASE 0x40007880u +#define CYDEV_PHUB_TDMEM16_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM16_ORIG_TD0 0x40007880u +#define CYREG_PHUB_TDMEM16_ORIG_TD1 0x40007884u +#define CYDEV_PHUB_TDMEM17_BASE 0x40007888u +#define CYDEV_PHUB_TDMEM17_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM17_ORIG_TD0 0x40007888u +#define CYREG_PHUB_TDMEM17_ORIG_TD1 0x4000788cu +#define CYDEV_PHUB_TDMEM18_BASE 0x40007890u +#define CYDEV_PHUB_TDMEM18_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM18_ORIG_TD0 0x40007890u +#define CYREG_PHUB_TDMEM18_ORIG_TD1 0x40007894u +#define CYDEV_PHUB_TDMEM19_BASE 0x40007898u +#define CYDEV_PHUB_TDMEM19_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM19_ORIG_TD0 0x40007898u +#define CYREG_PHUB_TDMEM19_ORIG_TD1 0x4000789cu +#define CYDEV_PHUB_TDMEM20_BASE 0x400078a0u +#define CYDEV_PHUB_TDMEM20_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM20_ORIG_TD0 0x400078a0u +#define CYREG_PHUB_TDMEM20_ORIG_TD1 0x400078a4u +#define CYDEV_PHUB_TDMEM21_BASE 0x400078a8u +#define CYDEV_PHUB_TDMEM21_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM21_ORIG_TD0 0x400078a8u +#define CYREG_PHUB_TDMEM21_ORIG_TD1 0x400078acu +#define CYDEV_PHUB_TDMEM22_BASE 0x400078b0u +#define CYDEV_PHUB_TDMEM22_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM22_ORIG_TD0 0x400078b0u +#define CYREG_PHUB_TDMEM22_ORIG_TD1 0x400078b4u +#define CYDEV_PHUB_TDMEM23_BASE 0x400078b8u +#define CYDEV_PHUB_TDMEM23_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM23_ORIG_TD0 0x400078b8u +#define CYREG_PHUB_TDMEM23_ORIG_TD1 0x400078bcu +#define CYDEV_PHUB_TDMEM24_BASE 0x400078c0u +#define CYDEV_PHUB_TDMEM24_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM24_ORIG_TD0 0x400078c0u +#define CYREG_PHUB_TDMEM24_ORIG_TD1 0x400078c4u +#define CYDEV_PHUB_TDMEM25_BASE 0x400078c8u +#define CYDEV_PHUB_TDMEM25_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM25_ORIG_TD0 0x400078c8u +#define CYREG_PHUB_TDMEM25_ORIG_TD1 0x400078ccu +#define CYDEV_PHUB_TDMEM26_BASE 0x400078d0u +#define CYDEV_PHUB_TDMEM26_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM26_ORIG_TD0 0x400078d0u +#define CYREG_PHUB_TDMEM26_ORIG_TD1 0x400078d4u +#define CYDEV_PHUB_TDMEM27_BASE 0x400078d8u +#define CYDEV_PHUB_TDMEM27_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM27_ORIG_TD0 0x400078d8u +#define CYREG_PHUB_TDMEM27_ORIG_TD1 0x400078dcu +#define CYDEV_PHUB_TDMEM28_BASE 0x400078e0u +#define CYDEV_PHUB_TDMEM28_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM28_ORIG_TD0 0x400078e0u +#define CYREG_PHUB_TDMEM28_ORIG_TD1 0x400078e4u +#define CYDEV_PHUB_TDMEM29_BASE 0x400078e8u +#define CYDEV_PHUB_TDMEM29_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM29_ORIG_TD0 0x400078e8u +#define CYREG_PHUB_TDMEM29_ORIG_TD1 0x400078ecu +#define CYDEV_PHUB_TDMEM30_BASE 0x400078f0u +#define CYDEV_PHUB_TDMEM30_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM30_ORIG_TD0 0x400078f0u +#define CYREG_PHUB_TDMEM30_ORIG_TD1 0x400078f4u +#define CYDEV_PHUB_TDMEM31_BASE 0x400078f8u +#define CYDEV_PHUB_TDMEM31_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM31_ORIG_TD0 0x400078f8u +#define CYREG_PHUB_TDMEM31_ORIG_TD1 0x400078fcu +#define CYDEV_PHUB_TDMEM32_BASE 0x40007900u +#define CYDEV_PHUB_TDMEM32_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM32_ORIG_TD0 0x40007900u +#define CYREG_PHUB_TDMEM32_ORIG_TD1 0x40007904u +#define CYDEV_PHUB_TDMEM33_BASE 0x40007908u +#define CYDEV_PHUB_TDMEM33_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM33_ORIG_TD0 0x40007908u +#define CYREG_PHUB_TDMEM33_ORIG_TD1 0x4000790cu +#define CYDEV_PHUB_TDMEM34_BASE 0x40007910u +#define CYDEV_PHUB_TDMEM34_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM34_ORIG_TD0 0x40007910u +#define CYREG_PHUB_TDMEM34_ORIG_TD1 0x40007914u +#define CYDEV_PHUB_TDMEM35_BASE 0x40007918u +#define CYDEV_PHUB_TDMEM35_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM35_ORIG_TD0 0x40007918u +#define CYREG_PHUB_TDMEM35_ORIG_TD1 0x4000791cu +#define CYDEV_PHUB_TDMEM36_BASE 0x40007920u +#define CYDEV_PHUB_TDMEM36_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM36_ORIG_TD0 0x40007920u +#define CYREG_PHUB_TDMEM36_ORIG_TD1 0x40007924u +#define CYDEV_PHUB_TDMEM37_BASE 0x40007928u +#define CYDEV_PHUB_TDMEM37_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM37_ORIG_TD0 0x40007928u +#define CYREG_PHUB_TDMEM37_ORIG_TD1 0x4000792cu +#define CYDEV_PHUB_TDMEM38_BASE 0x40007930u +#define CYDEV_PHUB_TDMEM38_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM38_ORIG_TD0 0x40007930u +#define CYREG_PHUB_TDMEM38_ORIG_TD1 0x40007934u +#define CYDEV_PHUB_TDMEM39_BASE 0x40007938u +#define CYDEV_PHUB_TDMEM39_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM39_ORIG_TD0 0x40007938u +#define CYREG_PHUB_TDMEM39_ORIG_TD1 0x4000793cu +#define CYDEV_PHUB_TDMEM40_BASE 0x40007940u +#define CYDEV_PHUB_TDMEM40_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM40_ORIG_TD0 0x40007940u +#define CYREG_PHUB_TDMEM40_ORIG_TD1 0x40007944u +#define CYDEV_PHUB_TDMEM41_BASE 0x40007948u +#define CYDEV_PHUB_TDMEM41_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM41_ORIG_TD0 0x40007948u +#define CYREG_PHUB_TDMEM41_ORIG_TD1 0x4000794cu +#define CYDEV_PHUB_TDMEM42_BASE 0x40007950u +#define CYDEV_PHUB_TDMEM42_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM42_ORIG_TD0 0x40007950u +#define CYREG_PHUB_TDMEM42_ORIG_TD1 0x40007954u +#define CYDEV_PHUB_TDMEM43_BASE 0x40007958u +#define CYDEV_PHUB_TDMEM43_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM43_ORIG_TD0 0x40007958u +#define CYREG_PHUB_TDMEM43_ORIG_TD1 0x4000795cu +#define CYDEV_PHUB_TDMEM44_BASE 0x40007960u +#define CYDEV_PHUB_TDMEM44_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM44_ORIG_TD0 0x40007960u +#define CYREG_PHUB_TDMEM44_ORIG_TD1 0x40007964u +#define CYDEV_PHUB_TDMEM45_BASE 0x40007968u +#define CYDEV_PHUB_TDMEM45_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM45_ORIG_TD0 0x40007968u +#define CYREG_PHUB_TDMEM45_ORIG_TD1 0x4000796cu +#define CYDEV_PHUB_TDMEM46_BASE 0x40007970u +#define CYDEV_PHUB_TDMEM46_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM46_ORIG_TD0 0x40007970u +#define CYREG_PHUB_TDMEM46_ORIG_TD1 0x40007974u +#define CYDEV_PHUB_TDMEM47_BASE 0x40007978u +#define CYDEV_PHUB_TDMEM47_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM47_ORIG_TD0 0x40007978u +#define CYREG_PHUB_TDMEM47_ORIG_TD1 0x4000797cu +#define CYDEV_PHUB_TDMEM48_BASE 0x40007980u +#define CYDEV_PHUB_TDMEM48_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM48_ORIG_TD0 0x40007980u +#define CYREG_PHUB_TDMEM48_ORIG_TD1 0x40007984u +#define CYDEV_PHUB_TDMEM49_BASE 0x40007988u +#define CYDEV_PHUB_TDMEM49_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM49_ORIG_TD0 0x40007988u +#define CYREG_PHUB_TDMEM49_ORIG_TD1 0x4000798cu +#define CYDEV_PHUB_TDMEM50_BASE 0x40007990u +#define CYDEV_PHUB_TDMEM50_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM50_ORIG_TD0 0x40007990u +#define CYREG_PHUB_TDMEM50_ORIG_TD1 0x40007994u +#define CYDEV_PHUB_TDMEM51_BASE 0x40007998u +#define CYDEV_PHUB_TDMEM51_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM51_ORIG_TD0 0x40007998u +#define CYREG_PHUB_TDMEM51_ORIG_TD1 0x4000799cu +#define CYDEV_PHUB_TDMEM52_BASE 0x400079a0u +#define CYDEV_PHUB_TDMEM52_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM52_ORIG_TD0 0x400079a0u +#define CYREG_PHUB_TDMEM52_ORIG_TD1 0x400079a4u +#define CYDEV_PHUB_TDMEM53_BASE 0x400079a8u +#define CYDEV_PHUB_TDMEM53_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM53_ORIG_TD0 0x400079a8u +#define CYREG_PHUB_TDMEM53_ORIG_TD1 0x400079acu +#define CYDEV_PHUB_TDMEM54_BASE 0x400079b0u +#define CYDEV_PHUB_TDMEM54_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM54_ORIG_TD0 0x400079b0u +#define CYREG_PHUB_TDMEM54_ORIG_TD1 0x400079b4u +#define CYDEV_PHUB_TDMEM55_BASE 0x400079b8u +#define CYDEV_PHUB_TDMEM55_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM55_ORIG_TD0 0x400079b8u +#define CYREG_PHUB_TDMEM55_ORIG_TD1 0x400079bcu +#define CYDEV_PHUB_TDMEM56_BASE 0x400079c0u +#define CYDEV_PHUB_TDMEM56_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM56_ORIG_TD0 0x400079c0u +#define CYREG_PHUB_TDMEM56_ORIG_TD1 0x400079c4u +#define CYDEV_PHUB_TDMEM57_BASE 0x400079c8u +#define CYDEV_PHUB_TDMEM57_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM57_ORIG_TD0 0x400079c8u +#define CYREG_PHUB_TDMEM57_ORIG_TD1 0x400079ccu +#define CYDEV_PHUB_TDMEM58_BASE 0x400079d0u +#define CYDEV_PHUB_TDMEM58_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM58_ORIG_TD0 0x400079d0u +#define CYREG_PHUB_TDMEM58_ORIG_TD1 0x400079d4u +#define CYDEV_PHUB_TDMEM59_BASE 0x400079d8u +#define CYDEV_PHUB_TDMEM59_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM59_ORIG_TD0 0x400079d8u +#define CYREG_PHUB_TDMEM59_ORIG_TD1 0x400079dcu +#define CYDEV_PHUB_TDMEM60_BASE 0x400079e0u +#define CYDEV_PHUB_TDMEM60_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM60_ORIG_TD0 0x400079e0u +#define CYREG_PHUB_TDMEM60_ORIG_TD1 0x400079e4u +#define CYDEV_PHUB_TDMEM61_BASE 0x400079e8u +#define CYDEV_PHUB_TDMEM61_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM61_ORIG_TD0 0x400079e8u +#define CYREG_PHUB_TDMEM61_ORIG_TD1 0x400079ecu +#define CYDEV_PHUB_TDMEM62_BASE 0x400079f0u +#define CYDEV_PHUB_TDMEM62_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM62_ORIG_TD0 0x400079f0u +#define CYREG_PHUB_TDMEM62_ORIG_TD1 0x400079f4u +#define CYDEV_PHUB_TDMEM63_BASE 0x400079f8u +#define CYDEV_PHUB_TDMEM63_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM63_ORIG_TD0 0x400079f8u +#define CYREG_PHUB_TDMEM63_ORIG_TD1 0x400079fcu +#define CYDEV_PHUB_TDMEM64_BASE 0x40007a00u +#define CYDEV_PHUB_TDMEM64_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM64_ORIG_TD0 0x40007a00u +#define CYREG_PHUB_TDMEM64_ORIG_TD1 0x40007a04u +#define CYDEV_PHUB_TDMEM65_BASE 0x40007a08u +#define CYDEV_PHUB_TDMEM65_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM65_ORIG_TD0 0x40007a08u +#define CYREG_PHUB_TDMEM65_ORIG_TD1 0x40007a0cu +#define CYDEV_PHUB_TDMEM66_BASE 0x40007a10u +#define CYDEV_PHUB_TDMEM66_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM66_ORIG_TD0 0x40007a10u +#define CYREG_PHUB_TDMEM66_ORIG_TD1 0x40007a14u +#define CYDEV_PHUB_TDMEM67_BASE 0x40007a18u +#define CYDEV_PHUB_TDMEM67_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM67_ORIG_TD0 0x40007a18u +#define CYREG_PHUB_TDMEM67_ORIG_TD1 0x40007a1cu +#define CYDEV_PHUB_TDMEM68_BASE 0x40007a20u +#define CYDEV_PHUB_TDMEM68_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM68_ORIG_TD0 0x40007a20u +#define CYREG_PHUB_TDMEM68_ORIG_TD1 0x40007a24u +#define CYDEV_PHUB_TDMEM69_BASE 0x40007a28u +#define CYDEV_PHUB_TDMEM69_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM69_ORIG_TD0 0x40007a28u +#define CYREG_PHUB_TDMEM69_ORIG_TD1 0x40007a2cu +#define CYDEV_PHUB_TDMEM70_BASE 0x40007a30u +#define CYDEV_PHUB_TDMEM70_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM70_ORIG_TD0 0x40007a30u +#define CYREG_PHUB_TDMEM70_ORIG_TD1 0x40007a34u +#define CYDEV_PHUB_TDMEM71_BASE 0x40007a38u +#define CYDEV_PHUB_TDMEM71_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM71_ORIG_TD0 0x40007a38u +#define CYREG_PHUB_TDMEM71_ORIG_TD1 0x40007a3cu +#define CYDEV_PHUB_TDMEM72_BASE 0x40007a40u +#define CYDEV_PHUB_TDMEM72_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM72_ORIG_TD0 0x40007a40u +#define CYREG_PHUB_TDMEM72_ORIG_TD1 0x40007a44u +#define CYDEV_PHUB_TDMEM73_BASE 0x40007a48u +#define CYDEV_PHUB_TDMEM73_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM73_ORIG_TD0 0x40007a48u +#define CYREG_PHUB_TDMEM73_ORIG_TD1 0x40007a4cu +#define CYDEV_PHUB_TDMEM74_BASE 0x40007a50u +#define CYDEV_PHUB_TDMEM74_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM74_ORIG_TD0 0x40007a50u +#define CYREG_PHUB_TDMEM74_ORIG_TD1 0x40007a54u +#define CYDEV_PHUB_TDMEM75_BASE 0x40007a58u +#define CYDEV_PHUB_TDMEM75_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM75_ORIG_TD0 0x40007a58u +#define CYREG_PHUB_TDMEM75_ORIG_TD1 0x40007a5cu +#define CYDEV_PHUB_TDMEM76_BASE 0x40007a60u +#define CYDEV_PHUB_TDMEM76_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM76_ORIG_TD0 0x40007a60u +#define CYREG_PHUB_TDMEM76_ORIG_TD1 0x40007a64u +#define CYDEV_PHUB_TDMEM77_BASE 0x40007a68u +#define CYDEV_PHUB_TDMEM77_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM77_ORIG_TD0 0x40007a68u +#define CYREG_PHUB_TDMEM77_ORIG_TD1 0x40007a6cu +#define CYDEV_PHUB_TDMEM78_BASE 0x40007a70u +#define CYDEV_PHUB_TDMEM78_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM78_ORIG_TD0 0x40007a70u +#define CYREG_PHUB_TDMEM78_ORIG_TD1 0x40007a74u +#define CYDEV_PHUB_TDMEM79_BASE 0x40007a78u +#define CYDEV_PHUB_TDMEM79_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM79_ORIG_TD0 0x40007a78u +#define CYREG_PHUB_TDMEM79_ORIG_TD1 0x40007a7cu +#define CYDEV_PHUB_TDMEM80_BASE 0x40007a80u +#define CYDEV_PHUB_TDMEM80_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM80_ORIG_TD0 0x40007a80u +#define CYREG_PHUB_TDMEM80_ORIG_TD1 0x40007a84u +#define CYDEV_PHUB_TDMEM81_BASE 0x40007a88u +#define CYDEV_PHUB_TDMEM81_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM81_ORIG_TD0 0x40007a88u +#define CYREG_PHUB_TDMEM81_ORIG_TD1 0x40007a8cu +#define CYDEV_PHUB_TDMEM82_BASE 0x40007a90u +#define CYDEV_PHUB_TDMEM82_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM82_ORIG_TD0 0x40007a90u +#define CYREG_PHUB_TDMEM82_ORIG_TD1 0x40007a94u +#define CYDEV_PHUB_TDMEM83_BASE 0x40007a98u +#define CYDEV_PHUB_TDMEM83_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM83_ORIG_TD0 0x40007a98u +#define CYREG_PHUB_TDMEM83_ORIG_TD1 0x40007a9cu +#define CYDEV_PHUB_TDMEM84_BASE 0x40007aa0u +#define CYDEV_PHUB_TDMEM84_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM84_ORIG_TD0 0x40007aa0u +#define CYREG_PHUB_TDMEM84_ORIG_TD1 0x40007aa4u +#define CYDEV_PHUB_TDMEM85_BASE 0x40007aa8u +#define CYDEV_PHUB_TDMEM85_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM85_ORIG_TD0 0x40007aa8u +#define CYREG_PHUB_TDMEM85_ORIG_TD1 0x40007aacu +#define CYDEV_PHUB_TDMEM86_BASE 0x40007ab0u +#define CYDEV_PHUB_TDMEM86_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM86_ORIG_TD0 0x40007ab0u +#define CYREG_PHUB_TDMEM86_ORIG_TD1 0x40007ab4u +#define CYDEV_PHUB_TDMEM87_BASE 0x40007ab8u +#define CYDEV_PHUB_TDMEM87_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM87_ORIG_TD0 0x40007ab8u +#define CYREG_PHUB_TDMEM87_ORIG_TD1 0x40007abcu +#define CYDEV_PHUB_TDMEM88_BASE 0x40007ac0u +#define CYDEV_PHUB_TDMEM88_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM88_ORIG_TD0 0x40007ac0u +#define CYREG_PHUB_TDMEM88_ORIG_TD1 0x40007ac4u +#define CYDEV_PHUB_TDMEM89_BASE 0x40007ac8u +#define CYDEV_PHUB_TDMEM89_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM89_ORIG_TD0 0x40007ac8u +#define CYREG_PHUB_TDMEM89_ORIG_TD1 0x40007accu +#define CYDEV_PHUB_TDMEM90_BASE 0x40007ad0u +#define CYDEV_PHUB_TDMEM90_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM90_ORIG_TD0 0x40007ad0u +#define CYREG_PHUB_TDMEM90_ORIG_TD1 0x40007ad4u +#define CYDEV_PHUB_TDMEM91_BASE 0x40007ad8u +#define CYDEV_PHUB_TDMEM91_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM91_ORIG_TD0 0x40007ad8u +#define CYREG_PHUB_TDMEM91_ORIG_TD1 0x40007adcu +#define CYDEV_PHUB_TDMEM92_BASE 0x40007ae0u +#define CYDEV_PHUB_TDMEM92_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM92_ORIG_TD0 0x40007ae0u +#define CYREG_PHUB_TDMEM92_ORIG_TD1 0x40007ae4u +#define CYDEV_PHUB_TDMEM93_BASE 0x40007ae8u +#define CYDEV_PHUB_TDMEM93_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM93_ORIG_TD0 0x40007ae8u +#define CYREG_PHUB_TDMEM93_ORIG_TD1 0x40007aecu +#define CYDEV_PHUB_TDMEM94_BASE 0x40007af0u +#define CYDEV_PHUB_TDMEM94_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM94_ORIG_TD0 0x40007af0u +#define CYREG_PHUB_TDMEM94_ORIG_TD1 0x40007af4u +#define CYDEV_PHUB_TDMEM95_BASE 0x40007af8u +#define CYDEV_PHUB_TDMEM95_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM95_ORIG_TD0 0x40007af8u +#define CYREG_PHUB_TDMEM95_ORIG_TD1 0x40007afcu +#define CYDEV_PHUB_TDMEM96_BASE 0x40007b00u +#define CYDEV_PHUB_TDMEM96_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM96_ORIG_TD0 0x40007b00u +#define CYREG_PHUB_TDMEM96_ORIG_TD1 0x40007b04u +#define CYDEV_PHUB_TDMEM97_BASE 0x40007b08u +#define CYDEV_PHUB_TDMEM97_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM97_ORIG_TD0 0x40007b08u +#define CYREG_PHUB_TDMEM97_ORIG_TD1 0x40007b0cu +#define CYDEV_PHUB_TDMEM98_BASE 0x40007b10u +#define CYDEV_PHUB_TDMEM98_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM98_ORIG_TD0 0x40007b10u +#define CYREG_PHUB_TDMEM98_ORIG_TD1 0x40007b14u +#define CYDEV_PHUB_TDMEM99_BASE 0x40007b18u +#define CYDEV_PHUB_TDMEM99_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM99_ORIG_TD0 0x40007b18u +#define CYREG_PHUB_TDMEM99_ORIG_TD1 0x40007b1cu +#define CYDEV_PHUB_TDMEM100_BASE 0x40007b20u +#define CYDEV_PHUB_TDMEM100_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM100_ORIG_TD0 0x40007b20u +#define CYREG_PHUB_TDMEM100_ORIG_TD1 0x40007b24u +#define CYDEV_PHUB_TDMEM101_BASE 0x40007b28u +#define CYDEV_PHUB_TDMEM101_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM101_ORIG_TD0 0x40007b28u +#define CYREG_PHUB_TDMEM101_ORIG_TD1 0x40007b2cu +#define CYDEV_PHUB_TDMEM102_BASE 0x40007b30u +#define CYDEV_PHUB_TDMEM102_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM102_ORIG_TD0 0x40007b30u +#define CYREG_PHUB_TDMEM102_ORIG_TD1 0x40007b34u +#define CYDEV_PHUB_TDMEM103_BASE 0x40007b38u +#define CYDEV_PHUB_TDMEM103_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM103_ORIG_TD0 0x40007b38u +#define CYREG_PHUB_TDMEM103_ORIG_TD1 0x40007b3cu +#define CYDEV_PHUB_TDMEM104_BASE 0x40007b40u +#define CYDEV_PHUB_TDMEM104_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM104_ORIG_TD0 0x40007b40u +#define CYREG_PHUB_TDMEM104_ORIG_TD1 0x40007b44u +#define CYDEV_PHUB_TDMEM105_BASE 0x40007b48u +#define CYDEV_PHUB_TDMEM105_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM105_ORIG_TD0 0x40007b48u +#define CYREG_PHUB_TDMEM105_ORIG_TD1 0x40007b4cu +#define CYDEV_PHUB_TDMEM106_BASE 0x40007b50u +#define CYDEV_PHUB_TDMEM106_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM106_ORIG_TD0 0x40007b50u +#define CYREG_PHUB_TDMEM106_ORIG_TD1 0x40007b54u +#define CYDEV_PHUB_TDMEM107_BASE 0x40007b58u +#define CYDEV_PHUB_TDMEM107_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM107_ORIG_TD0 0x40007b58u +#define CYREG_PHUB_TDMEM107_ORIG_TD1 0x40007b5cu +#define CYDEV_PHUB_TDMEM108_BASE 0x40007b60u +#define CYDEV_PHUB_TDMEM108_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM108_ORIG_TD0 0x40007b60u +#define CYREG_PHUB_TDMEM108_ORIG_TD1 0x40007b64u +#define CYDEV_PHUB_TDMEM109_BASE 0x40007b68u +#define CYDEV_PHUB_TDMEM109_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM109_ORIG_TD0 0x40007b68u +#define CYREG_PHUB_TDMEM109_ORIG_TD1 0x40007b6cu +#define CYDEV_PHUB_TDMEM110_BASE 0x40007b70u +#define CYDEV_PHUB_TDMEM110_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM110_ORIG_TD0 0x40007b70u +#define CYREG_PHUB_TDMEM110_ORIG_TD1 0x40007b74u +#define CYDEV_PHUB_TDMEM111_BASE 0x40007b78u +#define CYDEV_PHUB_TDMEM111_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM111_ORIG_TD0 0x40007b78u +#define CYREG_PHUB_TDMEM111_ORIG_TD1 0x40007b7cu +#define CYDEV_PHUB_TDMEM112_BASE 0x40007b80u +#define CYDEV_PHUB_TDMEM112_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM112_ORIG_TD0 0x40007b80u +#define CYREG_PHUB_TDMEM112_ORIG_TD1 0x40007b84u +#define CYDEV_PHUB_TDMEM113_BASE 0x40007b88u +#define CYDEV_PHUB_TDMEM113_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM113_ORIG_TD0 0x40007b88u +#define CYREG_PHUB_TDMEM113_ORIG_TD1 0x40007b8cu +#define CYDEV_PHUB_TDMEM114_BASE 0x40007b90u +#define CYDEV_PHUB_TDMEM114_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM114_ORIG_TD0 0x40007b90u +#define CYREG_PHUB_TDMEM114_ORIG_TD1 0x40007b94u +#define CYDEV_PHUB_TDMEM115_BASE 0x40007b98u +#define CYDEV_PHUB_TDMEM115_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM115_ORIG_TD0 0x40007b98u +#define CYREG_PHUB_TDMEM115_ORIG_TD1 0x40007b9cu +#define CYDEV_PHUB_TDMEM116_BASE 0x40007ba0u +#define CYDEV_PHUB_TDMEM116_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM116_ORIG_TD0 0x40007ba0u +#define CYREG_PHUB_TDMEM116_ORIG_TD1 0x40007ba4u +#define CYDEV_PHUB_TDMEM117_BASE 0x40007ba8u +#define CYDEV_PHUB_TDMEM117_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM117_ORIG_TD0 0x40007ba8u +#define CYREG_PHUB_TDMEM117_ORIG_TD1 0x40007bacu +#define CYDEV_PHUB_TDMEM118_BASE 0x40007bb0u +#define CYDEV_PHUB_TDMEM118_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM118_ORIG_TD0 0x40007bb0u +#define CYREG_PHUB_TDMEM118_ORIG_TD1 0x40007bb4u +#define CYDEV_PHUB_TDMEM119_BASE 0x40007bb8u +#define CYDEV_PHUB_TDMEM119_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM119_ORIG_TD0 0x40007bb8u +#define CYREG_PHUB_TDMEM119_ORIG_TD1 0x40007bbcu +#define CYDEV_PHUB_TDMEM120_BASE 0x40007bc0u +#define CYDEV_PHUB_TDMEM120_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM120_ORIG_TD0 0x40007bc0u +#define CYREG_PHUB_TDMEM120_ORIG_TD1 0x40007bc4u +#define CYDEV_PHUB_TDMEM121_BASE 0x40007bc8u +#define CYDEV_PHUB_TDMEM121_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM121_ORIG_TD0 0x40007bc8u +#define CYREG_PHUB_TDMEM121_ORIG_TD1 0x40007bccu +#define CYDEV_PHUB_TDMEM122_BASE 0x40007bd0u +#define CYDEV_PHUB_TDMEM122_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM122_ORIG_TD0 0x40007bd0u +#define CYREG_PHUB_TDMEM122_ORIG_TD1 0x40007bd4u +#define CYDEV_PHUB_TDMEM123_BASE 0x40007bd8u +#define CYDEV_PHUB_TDMEM123_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM123_ORIG_TD0 0x40007bd8u +#define CYREG_PHUB_TDMEM123_ORIG_TD1 0x40007bdcu +#define CYDEV_PHUB_TDMEM124_BASE 0x40007be0u +#define CYDEV_PHUB_TDMEM124_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM124_ORIG_TD0 0x40007be0u +#define CYREG_PHUB_TDMEM124_ORIG_TD1 0x40007be4u +#define CYDEV_PHUB_TDMEM125_BASE 0x40007be8u +#define CYDEV_PHUB_TDMEM125_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM125_ORIG_TD0 0x40007be8u +#define CYREG_PHUB_TDMEM125_ORIG_TD1 0x40007becu +#define CYDEV_PHUB_TDMEM126_BASE 0x40007bf0u +#define CYDEV_PHUB_TDMEM126_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM126_ORIG_TD0 0x40007bf0u +#define CYREG_PHUB_TDMEM126_ORIG_TD1 0x40007bf4u +#define CYDEV_PHUB_TDMEM127_BASE 0x40007bf8u +#define CYDEV_PHUB_TDMEM127_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM127_ORIG_TD0 0x40007bf8u +#define CYREG_PHUB_TDMEM127_ORIG_TD1 0x40007bfcu +#define CYDEV_EE_BASE 0x40008000u +#define CYDEV_EE_SIZE 0x00000800u +#define CYREG_EE_DATA_MBASE 0x40008000u +#define CYREG_EE_DATA_MSIZE 0x00000800u +#define CYDEV_CAN0_BASE 0x4000a000u +#define CYDEV_CAN0_SIZE 0x000002a0u +#define CYDEV_CAN0_CSR_BASE 0x4000a000u +#define CYDEV_CAN0_CSR_SIZE 0x00000018u +#define CYREG_CAN0_CSR_INT_SR 0x4000a000u +#define CYREG_CAN0_CSR_INT_EN 0x4000a004u +#define CYREG_CAN0_CSR_BUF_SR 0x4000a008u +#define CYREG_CAN0_CSR_ERR_SR 0x4000a00cu +#define CYREG_CAN0_CSR_CMD 0x4000a010u +#define CYREG_CAN0_CSR_CFG 0x4000a014u +#define CYDEV_CAN0_TX0_BASE 0x4000a020u +#define CYDEV_CAN0_TX0_SIZE 0x00000010u +#define CYREG_CAN0_TX0_CMD 0x4000a020u +#define CYREG_CAN0_TX0_ID 0x4000a024u +#define CYREG_CAN0_TX0_DH 0x4000a028u +#define CYREG_CAN0_TX0_DL 0x4000a02cu +#define CYDEV_CAN0_TX1_BASE 0x4000a030u +#define CYDEV_CAN0_TX1_SIZE 0x00000010u +#define CYREG_CAN0_TX1_CMD 0x4000a030u +#define CYREG_CAN0_TX1_ID 0x4000a034u +#define CYREG_CAN0_TX1_DH 0x4000a038u +#define CYREG_CAN0_TX1_DL 0x4000a03cu +#define CYDEV_CAN0_TX2_BASE 0x4000a040u +#define CYDEV_CAN0_TX2_SIZE 0x00000010u +#define CYREG_CAN0_TX2_CMD 0x4000a040u +#define CYREG_CAN0_TX2_ID 0x4000a044u +#define CYREG_CAN0_TX2_DH 0x4000a048u +#define CYREG_CAN0_TX2_DL 0x4000a04cu +#define CYDEV_CAN0_TX3_BASE 0x4000a050u +#define CYDEV_CAN0_TX3_SIZE 0x00000010u +#define CYREG_CAN0_TX3_CMD 0x4000a050u +#define CYREG_CAN0_TX3_ID 0x4000a054u +#define CYREG_CAN0_TX3_DH 0x4000a058u +#define CYREG_CAN0_TX3_DL 0x4000a05cu +#define CYDEV_CAN0_TX4_BASE 0x4000a060u +#define CYDEV_CAN0_TX4_SIZE 0x00000010u +#define CYREG_CAN0_TX4_CMD 0x4000a060u +#define CYREG_CAN0_TX4_ID 0x4000a064u +#define CYREG_CAN0_TX4_DH 0x4000a068u +#define CYREG_CAN0_TX4_DL 0x4000a06cu +#define CYDEV_CAN0_TX5_BASE 0x4000a070u +#define CYDEV_CAN0_TX5_SIZE 0x00000010u +#define CYREG_CAN0_TX5_CMD 0x4000a070u +#define CYREG_CAN0_TX5_ID 0x4000a074u +#define CYREG_CAN0_TX5_DH 0x4000a078u +#define CYREG_CAN0_TX5_DL 0x4000a07cu +#define CYDEV_CAN0_TX6_BASE 0x4000a080u +#define CYDEV_CAN0_TX6_SIZE 0x00000010u +#define CYREG_CAN0_TX6_CMD 0x4000a080u +#define CYREG_CAN0_TX6_ID 0x4000a084u +#define CYREG_CAN0_TX6_DH 0x4000a088u +#define CYREG_CAN0_TX6_DL 0x4000a08cu +#define CYDEV_CAN0_TX7_BASE 0x4000a090u +#define CYDEV_CAN0_TX7_SIZE 0x00000010u +#define CYREG_CAN0_TX7_CMD 0x4000a090u +#define CYREG_CAN0_TX7_ID 0x4000a094u +#define CYREG_CAN0_TX7_DH 0x4000a098u +#define CYREG_CAN0_TX7_DL 0x4000a09cu +#define CYDEV_CAN0_RX0_BASE 0x4000a0a0u +#define CYDEV_CAN0_RX0_SIZE 0x00000020u +#define CYREG_CAN0_RX0_CMD 0x4000a0a0u +#define CYREG_CAN0_RX0_ID 0x4000a0a4u +#define CYREG_CAN0_RX0_DH 0x4000a0a8u +#define CYREG_CAN0_RX0_DL 0x4000a0acu +#define CYREG_CAN0_RX0_AMR 0x4000a0b0u +#define CYREG_CAN0_RX0_ACR 0x4000a0b4u +#define CYREG_CAN0_RX0_AMRD 0x4000a0b8u +#define CYREG_CAN0_RX0_ACRD 0x4000a0bcu +#define CYDEV_CAN0_RX1_BASE 0x4000a0c0u +#define CYDEV_CAN0_RX1_SIZE 0x00000020u +#define CYREG_CAN0_RX1_CMD 0x4000a0c0u +#define CYREG_CAN0_RX1_ID 0x4000a0c4u +#define CYREG_CAN0_RX1_DH 0x4000a0c8u +#define CYREG_CAN0_RX1_DL 0x4000a0ccu +#define CYREG_CAN0_RX1_AMR 0x4000a0d0u +#define CYREG_CAN0_RX1_ACR 0x4000a0d4u +#define CYREG_CAN0_RX1_AMRD 0x4000a0d8u +#define CYREG_CAN0_RX1_ACRD 0x4000a0dcu +#define CYDEV_CAN0_RX2_BASE 0x4000a0e0u +#define CYDEV_CAN0_RX2_SIZE 0x00000020u +#define CYREG_CAN0_RX2_CMD 0x4000a0e0u +#define CYREG_CAN0_RX2_ID 0x4000a0e4u +#define CYREG_CAN0_RX2_DH 0x4000a0e8u +#define CYREG_CAN0_RX2_DL 0x4000a0ecu +#define CYREG_CAN0_RX2_AMR 0x4000a0f0u +#define CYREG_CAN0_RX2_ACR 0x4000a0f4u +#define CYREG_CAN0_RX2_AMRD 0x4000a0f8u +#define CYREG_CAN0_RX2_ACRD 0x4000a0fcu +#define CYDEV_CAN0_RX3_BASE 0x4000a100u +#define CYDEV_CAN0_RX3_SIZE 0x00000020u +#define CYREG_CAN0_RX3_CMD 0x4000a100u +#define CYREG_CAN0_RX3_ID 0x4000a104u +#define CYREG_CAN0_RX3_DH 0x4000a108u +#define CYREG_CAN0_RX3_DL 0x4000a10cu +#define CYREG_CAN0_RX3_AMR 0x4000a110u +#define CYREG_CAN0_RX3_ACR 0x4000a114u +#define CYREG_CAN0_RX3_AMRD 0x4000a118u +#define CYREG_CAN0_RX3_ACRD 0x4000a11cu +#define CYDEV_CAN0_RX4_BASE 0x4000a120u +#define CYDEV_CAN0_RX4_SIZE 0x00000020u +#define CYREG_CAN0_RX4_CMD 0x4000a120u +#define CYREG_CAN0_RX4_ID 0x4000a124u +#define CYREG_CAN0_RX4_DH 0x4000a128u +#define CYREG_CAN0_RX4_DL 0x4000a12cu +#define CYREG_CAN0_RX4_AMR 0x4000a130u +#define CYREG_CAN0_RX4_ACR 0x4000a134u +#define CYREG_CAN0_RX4_AMRD 0x4000a138u +#define CYREG_CAN0_RX4_ACRD 0x4000a13cu +#define CYDEV_CAN0_RX5_BASE 0x4000a140u +#define CYDEV_CAN0_RX5_SIZE 0x00000020u +#define CYREG_CAN0_RX5_CMD 0x4000a140u +#define CYREG_CAN0_RX5_ID 0x4000a144u +#define CYREG_CAN0_RX5_DH 0x4000a148u +#define CYREG_CAN0_RX5_DL 0x4000a14cu +#define CYREG_CAN0_RX5_AMR 0x4000a150u +#define CYREG_CAN0_RX5_ACR 0x4000a154u +#define CYREG_CAN0_RX5_AMRD 0x4000a158u +#define CYREG_CAN0_RX5_ACRD 0x4000a15cu +#define CYDEV_CAN0_RX6_BASE 0x4000a160u +#define CYDEV_CAN0_RX6_SIZE 0x00000020u +#define CYREG_CAN0_RX6_CMD 0x4000a160u +#define CYREG_CAN0_RX6_ID 0x4000a164u +#define CYREG_CAN0_RX6_DH 0x4000a168u +#define CYREG_CAN0_RX6_DL 0x4000a16cu +#define CYREG_CAN0_RX6_AMR 0x4000a170u +#define CYREG_CAN0_RX6_ACR 0x4000a174u +#define CYREG_CAN0_RX6_AMRD 0x4000a178u +#define CYREG_CAN0_RX6_ACRD 0x4000a17cu +#define CYDEV_CAN0_RX7_BASE 0x4000a180u +#define CYDEV_CAN0_RX7_SIZE 0x00000020u +#define CYREG_CAN0_RX7_CMD 0x4000a180u +#define CYREG_CAN0_RX7_ID 0x4000a184u +#define CYREG_CAN0_RX7_DH 0x4000a188u +#define CYREG_CAN0_RX7_DL 0x4000a18cu +#define CYREG_CAN0_RX7_AMR 0x4000a190u +#define CYREG_CAN0_RX7_ACR 0x4000a194u +#define CYREG_CAN0_RX7_AMRD 0x4000a198u +#define CYREG_CAN0_RX7_ACRD 0x4000a19cu +#define CYDEV_CAN0_RX8_BASE 0x4000a1a0u +#define CYDEV_CAN0_RX8_SIZE 0x00000020u +#define CYREG_CAN0_RX8_CMD 0x4000a1a0u +#define CYREG_CAN0_RX8_ID 0x4000a1a4u +#define CYREG_CAN0_RX8_DH 0x4000a1a8u +#define CYREG_CAN0_RX8_DL 0x4000a1acu +#define CYREG_CAN0_RX8_AMR 0x4000a1b0u +#define CYREG_CAN0_RX8_ACR 0x4000a1b4u +#define CYREG_CAN0_RX8_AMRD 0x4000a1b8u +#define CYREG_CAN0_RX8_ACRD 0x4000a1bcu +#define CYDEV_CAN0_RX9_BASE 0x4000a1c0u +#define CYDEV_CAN0_RX9_SIZE 0x00000020u +#define CYREG_CAN0_RX9_CMD 0x4000a1c0u +#define CYREG_CAN0_RX9_ID 0x4000a1c4u +#define CYREG_CAN0_RX9_DH 0x4000a1c8u +#define CYREG_CAN0_RX9_DL 0x4000a1ccu +#define CYREG_CAN0_RX9_AMR 0x4000a1d0u +#define CYREG_CAN0_RX9_ACR 0x4000a1d4u +#define CYREG_CAN0_RX9_AMRD 0x4000a1d8u +#define CYREG_CAN0_RX9_ACRD 0x4000a1dcu +#define CYDEV_CAN0_RX10_BASE 0x4000a1e0u +#define CYDEV_CAN0_RX10_SIZE 0x00000020u +#define CYREG_CAN0_RX10_CMD 0x4000a1e0u +#define CYREG_CAN0_RX10_ID 0x4000a1e4u +#define CYREG_CAN0_RX10_DH 0x4000a1e8u +#define CYREG_CAN0_RX10_DL 0x4000a1ecu +#define CYREG_CAN0_RX10_AMR 0x4000a1f0u +#define CYREG_CAN0_RX10_ACR 0x4000a1f4u +#define CYREG_CAN0_RX10_AMRD 0x4000a1f8u +#define CYREG_CAN0_RX10_ACRD 0x4000a1fcu +#define CYDEV_CAN0_RX11_BASE 0x4000a200u +#define CYDEV_CAN0_RX11_SIZE 0x00000020u +#define CYREG_CAN0_RX11_CMD 0x4000a200u +#define CYREG_CAN0_RX11_ID 0x4000a204u +#define CYREG_CAN0_RX11_DH 0x4000a208u +#define CYREG_CAN0_RX11_DL 0x4000a20cu +#define CYREG_CAN0_RX11_AMR 0x4000a210u +#define CYREG_CAN0_RX11_ACR 0x4000a214u +#define CYREG_CAN0_RX11_AMRD 0x4000a218u +#define CYREG_CAN0_RX11_ACRD 0x4000a21cu +#define CYDEV_CAN0_RX12_BASE 0x4000a220u +#define CYDEV_CAN0_RX12_SIZE 0x00000020u +#define CYREG_CAN0_RX12_CMD 0x4000a220u +#define CYREG_CAN0_RX12_ID 0x4000a224u +#define CYREG_CAN0_RX12_DH 0x4000a228u +#define CYREG_CAN0_RX12_DL 0x4000a22cu +#define CYREG_CAN0_RX12_AMR 0x4000a230u +#define CYREG_CAN0_RX12_ACR 0x4000a234u +#define CYREG_CAN0_RX12_AMRD 0x4000a238u +#define CYREG_CAN0_RX12_ACRD 0x4000a23cu +#define CYDEV_CAN0_RX13_BASE 0x4000a240u +#define CYDEV_CAN0_RX13_SIZE 0x00000020u +#define CYREG_CAN0_RX13_CMD 0x4000a240u +#define CYREG_CAN0_RX13_ID 0x4000a244u +#define CYREG_CAN0_RX13_DH 0x4000a248u +#define CYREG_CAN0_RX13_DL 0x4000a24cu +#define CYREG_CAN0_RX13_AMR 0x4000a250u +#define CYREG_CAN0_RX13_ACR 0x4000a254u +#define CYREG_CAN0_RX13_AMRD 0x4000a258u +#define CYREG_CAN0_RX13_ACRD 0x4000a25cu +#define CYDEV_CAN0_RX14_BASE 0x4000a260u +#define CYDEV_CAN0_RX14_SIZE 0x00000020u +#define CYREG_CAN0_RX14_CMD 0x4000a260u +#define CYREG_CAN0_RX14_ID 0x4000a264u +#define CYREG_CAN0_RX14_DH 0x4000a268u +#define CYREG_CAN0_RX14_DL 0x4000a26cu +#define CYREG_CAN0_RX14_AMR 0x4000a270u +#define CYREG_CAN0_RX14_ACR 0x4000a274u +#define CYREG_CAN0_RX14_AMRD 0x4000a278u +#define CYREG_CAN0_RX14_ACRD 0x4000a27cu +#define CYDEV_CAN0_RX15_BASE 0x4000a280u +#define CYDEV_CAN0_RX15_SIZE 0x00000020u +#define CYREG_CAN0_RX15_CMD 0x4000a280u +#define CYREG_CAN0_RX15_ID 0x4000a284u +#define CYREG_CAN0_RX15_DH 0x4000a288u +#define CYREG_CAN0_RX15_DL 0x4000a28cu +#define CYREG_CAN0_RX15_AMR 0x4000a290u +#define CYREG_CAN0_RX15_ACR 0x4000a294u +#define CYREG_CAN0_RX15_AMRD 0x4000a298u +#define CYREG_CAN0_RX15_ACRD 0x4000a29cu +#define CYDEV_DFB0_BASE 0x4000c000u +#define CYDEV_DFB0_SIZE 0x000007b5u +#define CYDEV_DFB0_DPA_SRAM_BASE 0x4000c000u +#define CYDEV_DFB0_DPA_SRAM_SIZE 0x00000200u +#define CYREG_DFB0_DPA_SRAM_DATA_MBASE 0x4000c000u +#define CYREG_DFB0_DPA_SRAM_DATA_MSIZE 0x00000200u +#define CYDEV_DFB0_DPB_SRAM_BASE 0x4000c200u +#define CYDEV_DFB0_DPB_SRAM_SIZE 0x00000200u +#define CYREG_DFB0_DPB_SRAM_DATA_MBASE 0x4000c200u +#define CYREG_DFB0_DPB_SRAM_DATA_MSIZE 0x00000200u +#define CYDEV_DFB0_CSA_SRAM_BASE 0x4000c400u +#define CYDEV_DFB0_CSA_SRAM_SIZE 0x00000100u +#define CYREG_DFB0_CSA_SRAM_DATA_MBASE 0x4000c400u +#define CYREG_DFB0_CSA_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_CSB_SRAM_BASE 0x4000c500u +#define CYDEV_DFB0_CSB_SRAM_SIZE 0x00000100u +#define CYREG_DFB0_CSB_SRAM_DATA_MBASE 0x4000c500u +#define CYREG_DFB0_CSB_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_FSM_SRAM_BASE 0x4000c600u +#define CYDEV_DFB0_FSM_SRAM_SIZE 0x00000100u +#define CYREG_DFB0_FSM_SRAM_DATA_MBASE 0x4000c600u +#define CYREG_DFB0_FSM_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_ACU_SRAM_BASE 0x4000c700u +#define CYDEV_DFB0_ACU_SRAM_SIZE 0x00000040u +#define CYREG_DFB0_ACU_SRAM_DATA_MBASE 0x4000c700u +#define CYREG_DFB0_ACU_SRAM_DATA_MSIZE 0x00000040u +#define CYREG_DFB0_CR 0x4000c780u +#define CYREG_DFB0_SR 0x4000c784u +#define CYREG_DFB0_RAM_EN 0x4000c788u +#define CYREG_DFB0_RAM_DIR 0x4000c78cu +#define CYREG_DFB0_SEMA 0x4000c790u +#define CYREG_DFB0_DSI_CTRL 0x4000c794u +#define CYREG_DFB0_INT_CTRL 0x4000c798u +#define CYREG_DFB0_DMA_CTRL 0x4000c79cu +#define CYREG_DFB0_STAGEA 0x4000c7a0u +#define CYREG_DFB0_STAGEAM 0x4000c7a1u +#define CYREG_DFB0_STAGEAH 0x4000c7a2u +#define CYREG_DFB0_STAGEB 0x4000c7a4u +#define CYREG_DFB0_STAGEBM 0x4000c7a5u +#define CYREG_DFB0_STAGEBH 0x4000c7a6u +#define CYREG_DFB0_HOLDA 0x4000c7a8u +#define CYREG_DFB0_HOLDAM 0x4000c7a9u +#define CYREG_DFB0_HOLDAH 0x4000c7aau +#define CYREG_DFB0_HOLDAS 0x4000c7abu +#define CYREG_DFB0_HOLDB 0x4000c7acu +#define CYREG_DFB0_HOLDBM 0x4000c7adu +#define CYREG_DFB0_HOLDBH 0x4000c7aeu +#define CYREG_DFB0_HOLDBS 0x4000c7afu +#define CYREG_DFB0_COHER 0x4000c7b0u +#define CYREG_DFB0_DALIGN 0x4000c7b4u +#define CYDEV_UCFG_BASE 0x40010000u +#define CYDEV_UCFG_SIZE 0x00005040u +#define CYDEV_UCFG_B0_BASE 0x40010000u +#define CYDEV_UCFG_B0_SIZE 0x00000fefu +#define CYDEV_UCFG_B0_P0_BASE 0x40010000u +#define CYDEV_UCFG_B0_P0_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P0_U0_BASE 0x40010000u +#define CYDEV_UCFG_B0_P0_U0_SIZE 0x00000070u +#define CYREG_B0_P0_U0_PLD_IT0 0x40010000u +#define CYREG_B0_P0_U0_PLD_IT1 0x40010004u +#define CYREG_B0_P0_U0_PLD_IT2 0x40010008u +#define CYREG_B0_P0_U0_PLD_IT3 0x4001000cu +#define CYREG_B0_P0_U0_PLD_IT4 0x40010010u +#define CYREG_B0_P0_U0_PLD_IT5 0x40010014u +#define CYREG_B0_P0_U0_PLD_IT6 0x40010018u +#define CYREG_B0_P0_U0_PLD_IT7 0x4001001cu +#define CYREG_B0_P0_U0_PLD_IT8 0x40010020u +#define CYREG_B0_P0_U0_PLD_IT9 0x40010024u +#define CYREG_B0_P0_U0_PLD_IT10 0x40010028u +#define CYREG_B0_P0_U0_PLD_IT11 0x4001002cu +#define CYREG_B0_P0_U0_PLD_ORT0 0x40010030u +#define CYREG_B0_P0_U0_PLD_ORT1 0x40010032u +#define CYREG_B0_P0_U0_PLD_ORT2 0x40010034u +#define CYREG_B0_P0_U0_PLD_ORT3 0x40010036u +#define CYREG_B0_P0_U0_MC_CFG_CEN_CONST 0x40010038u +#define CYREG_B0_P0_U0_MC_CFG_XORFB 0x4001003au +#define CYREG_B0_P0_U0_MC_CFG_SET_RESET 0x4001003cu +#define CYREG_B0_P0_U0_MC_CFG_BYPASS 0x4001003eu +#define CYREG_B0_P0_U0_CFG0 0x40010040u +#define CYREG_B0_P0_U0_CFG1 0x40010041u +#define CYREG_B0_P0_U0_CFG2 0x40010042u +#define CYREG_B0_P0_U0_CFG3 0x40010043u +#define CYREG_B0_P0_U0_CFG4 0x40010044u +#define CYREG_B0_P0_U0_CFG5 0x40010045u +#define CYREG_B0_P0_U0_CFG6 0x40010046u +#define CYREG_B0_P0_U0_CFG7 0x40010047u +#define CYREG_B0_P0_U0_CFG8 0x40010048u +#define CYREG_B0_P0_U0_CFG9 0x40010049u +#define CYREG_B0_P0_U0_CFG10 0x4001004au +#define CYREG_B0_P0_U0_CFG11 0x4001004bu +#define CYREG_B0_P0_U0_CFG12 0x4001004cu +#define CYREG_B0_P0_U0_CFG13 0x4001004du +#define CYREG_B0_P0_U0_CFG14 0x4001004eu +#define CYREG_B0_P0_U0_CFG15 0x4001004fu +#define CYREG_B0_P0_U0_CFG16 0x40010050u +#define CYREG_B0_P0_U0_CFG17 0x40010051u +#define CYREG_B0_P0_U0_CFG18 0x40010052u +#define CYREG_B0_P0_U0_CFG19 0x40010053u +#define CYREG_B0_P0_U0_CFG20 0x40010054u +#define CYREG_B0_P0_U0_CFG21 0x40010055u +#define CYREG_B0_P0_U0_CFG22 0x40010056u +#define CYREG_B0_P0_U0_CFG23 0x40010057u +#define CYREG_B0_P0_U0_CFG24 0x40010058u +#define CYREG_B0_P0_U0_CFG25 0x40010059u +#define CYREG_B0_P0_U0_CFG26 0x4001005au +#define CYREG_B0_P0_U0_CFG27 0x4001005bu +#define CYREG_B0_P0_U0_CFG28 0x4001005cu +#define CYREG_B0_P0_U0_CFG29 0x4001005du +#define CYREG_B0_P0_U0_CFG30 0x4001005eu +#define CYREG_B0_P0_U0_CFG31 0x4001005fu +#define CYREG_B0_P0_U0_DCFG0 0x40010060u +#define CYREG_B0_P0_U0_DCFG1 0x40010062u +#define CYREG_B0_P0_U0_DCFG2 0x40010064u +#define CYREG_B0_P0_U0_DCFG3 0x40010066u +#define CYREG_B0_P0_U0_DCFG4 0x40010068u +#define CYREG_B0_P0_U0_DCFG5 0x4001006au +#define CYREG_B0_P0_U0_DCFG6 0x4001006cu +#define CYREG_B0_P0_U0_DCFG7 0x4001006eu +#define CYDEV_UCFG_B0_P0_U1_BASE 0x40010080u +#define CYDEV_UCFG_B0_P0_U1_SIZE 0x00000070u +#define CYREG_B0_P0_U1_PLD_IT0 0x40010080u +#define CYREG_B0_P0_U1_PLD_IT1 0x40010084u +#define CYREG_B0_P0_U1_PLD_IT2 0x40010088u +#define CYREG_B0_P0_U1_PLD_IT3 0x4001008cu +#define CYREG_B0_P0_U1_PLD_IT4 0x40010090u +#define CYREG_B0_P0_U1_PLD_IT5 0x40010094u +#define CYREG_B0_P0_U1_PLD_IT6 0x40010098u +#define CYREG_B0_P0_U1_PLD_IT7 0x4001009cu +#define CYREG_B0_P0_U1_PLD_IT8 0x400100a0u +#define CYREG_B0_P0_U1_PLD_IT9 0x400100a4u +#define CYREG_B0_P0_U1_PLD_IT10 0x400100a8u +#define CYREG_B0_P0_U1_PLD_IT11 0x400100acu +#define CYREG_B0_P0_U1_PLD_ORT0 0x400100b0u +#define CYREG_B0_P0_U1_PLD_ORT1 0x400100b2u +#define CYREG_B0_P0_U1_PLD_ORT2 0x400100b4u +#define CYREG_B0_P0_U1_PLD_ORT3 0x400100b6u +#define CYREG_B0_P0_U1_MC_CFG_CEN_CONST 0x400100b8u +#define CYREG_B0_P0_U1_MC_CFG_XORFB 0x400100bau +#define CYREG_B0_P0_U1_MC_CFG_SET_RESET 0x400100bcu +#define CYREG_B0_P0_U1_MC_CFG_BYPASS 0x400100beu +#define CYREG_B0_P0_U1_CFG0 0x400100c0u +#define CYREG_B0_P0_U1_CFG1 0x400100c1u +#define CYREG_B0_P0_U1_CFG2 0x400100c2u +#define CYREG_B0_P0_U1_CFG3 0x400100c3u +#define CYREG_B0_P0_U1_CFG4 0x400100c4u +#define CYREG_B0_P0_U1_CFG5 0x400100c5u +#define CYREG_B0_P0_U1_CFG6 0x400100c6u +#define CYREG_B0_P0_U1_CFG7 0x400100c7u +#define CYREG_B0_P0_U1_CFG8 0x400100c8u +#define CYREG_B0_P0_U1_CFG9 0x400100c9u +#define CYREG_B0_P0_U1_CFG10 0x400100cau +#define CYREG_B0_P0_U1_CFG11 0x400100cbu +#define CYREG_B0_P0_U1_CFG12 0x400100ccu +#define CYREG_B0_P0_U1_CFG13 0x400100cdu +#define CYREG_B0_P0_U1_CFG14 0x400100ceu +#define CYREG_B0_P0_U1_CFG15 0x400100cfu +#define CYREG_B0_P0_U1_CFG16 0x400100d0u +#define CYREG_B0_P0_U1_CFG17 0x400100d1u +#define CYREG_B0_P0_U1_CFG18 0x400100d2u +#define CYREG_B0_P0_U1_CFG19 0x400100d3u +#define CYREG_B0_P0_U1_CFG20 0x400100d4u +#define CYREG_B0_P0_U1_CFG21 0x400100d5u +#define CYREG_B0_P0_U1_CFG22 0x400100d6u +#define CYREG_B0_P0_U1_CFG23 0x400100d7u +#define CYREG_B0_P0_U1_CFG24 0x400100d8u +#define CYREG_B0_P0_U1_CFG25 0x400100d9u +#define CYREG_B0_P0_U1_CFG26 0x400100dau +#define CYREG_B0_P0_U1_CFG27 0x400100dbu +#define CYREG_B0_P0_U1_CFG28 0x400100dcu +#define CYREG_B0_P0_U1_CFG29 0x400100ddu +#define CYREG_B0_P0_U1_CFG30 0x400100deu +#define CYREG_B0_P0_U1_CFG31 0x400100dfu +#define CYREG_B0_P0_U1_DCFG0 0x400100e0u +#define CYREG_B0_P0_U1_DCFG1 0x400100e2u +#define CYREG_B0_P0_U1_DCFG2 0x400100e4u +#define CYREG_B0_P0_U1_DCFG3 0x400100e6u +#define CYREG_B0_P0_U1_DCFG4 0x400100e8u +#define CYREG_B0_P0_U1_DCFG5 0x400100eau +#define CYREG_B0_P0_U1_DCFG6 0x400100ecu +#define CYREG_B0_P0_U1_DCFG7 0x400100eeu +#define CYDEV_UCFG_B0_P0_ROUTE_BASE 0x40010100u +#define CYDEV_UCFG_B0_P0_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P1_BASE 0x40010200u +#define CYDEV_UCFG_B0_P1_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P1_U0_BASE 0x40010200u +#define CYDEV_UCFG_B0_P1_U0_SIZE 0x00000070u +#define CYREG_B0_P1_U0_PLD_IT0 0x40010200u +#define CYREG_B0_P1_U0_PLD_IT1 0x40010204u +#define CYREG_B0_P1_U0_PLD_IT2 0x40010208u +#define CYREG_B0_P1_U0_PLD_IT3 0x4001020cu +#define CYREG_B0_P1_U0_PLD_IT4 0x40010210u +#define CYREG_B0_P1_U0_PLD_IT5 0x40010214u +#define CYREG_B0_P1_U0_PLD_IT6 0x40010218u +#define CYREG_B0_P1_U0_PLD_IT7 0x4001021cu +#define CYREG_B0_P1_U0_PLD_IT8 0x40010220u +#define CYREG_B0_P1_U0_PLD_IT9 0x40010224u +#define CYREG_B0_P1_U0_PLD_IT10 0x40010228u +#define CYREG_B0_P1_U0_PLD_IT11 0x4001022cu +#define CYREG_B0_P1_U0_PLD_ORT0 0x40010230u +#define CYREG_B0_P1_U0_PLD_ORT1 0x40010232u +#define CYREG_B0_P1_U0_PLD_ORT2 0x40010234u +#define CYREG_B0_P1_U0_PLD_ORT3 0x40010236u +#define CYREG_B0_P1_U0_MC_CFG_CEN_CONST 0x40010238u +#define CYREG_B0_P1_U0_MC_CFG_XORFB 0x4001023au +#define CYREG_B0_P1_U0_MC_CFG_SET_RESET 0x4001023cu +#define CYREG_B0_P1_U0_MC_CFG_BYPASS 0x4001023eu +#define CYREG_B0_P1_U0_CFG0 0x40010240u +#define CYREG_B0_P1_U0_CFG1 0x40010241u +#define CYREG_B0_P1_U0_CFG2 0x40010242u +#define CYREG_B0_P1_U0_CFG3 0x40010243u +#define CYREG_B0_P1_U0_CFG4 0x40010244u +#define CYREG_B0_P1_U0_CFG5 0x40010245u +#define CYREG_B0_P1_U0_CFG6 0x40010246u +#define CYREG_B0_P1_U0_CFG7 0x40010247u +#define CYREG_B0_P1_U0_CFG8 0x40010248u +#define CYREG_B0_P1_U0_CFG9 0x40010249u +#define CYREG_B0_P1_U0_CFG10 0x4001024au +#define CYREG_B0_P1_U0_CFG11 0x4001024bu +#define CYREG_B0_P1_U0_CFG12 0x4001024cu +#define CYREG_B0_P1_U0_CFG13 0x4001024du +#define CYREG_B0_P1_U0_CFG14 0x4001024eu +#define CYREG_B0_P1_U0_CFG15 0x4001024fu +#define CYREG_B0_P1_U0_CFG16 0x40010250u +#define CYREG_B0_P1_U0_CFG17 0x40010251u +#define CYREG_B0_P1_U0_CFG18 0x40010252u +#define CYREG_B0_P1_U0_CFG19 0x40010253u +#define CYREG_B0_P1_U0_CFG20 0x40010254u +#define CYREG_B0_P1_U0_CFG21 0x40010255u +#define CYREG_B0_P1_U0_CFG22 0x40010256u +#define CYREG_B0_P1_U0_CFG23 0x40010257u +#define CYREG_B0_P1_U0_CFG24 0x40010258u +#define CYREG_B0_P1_U0_CFG25 0x40010259u +#define CYREG_B0_P1_U0_CFG26 0x4001025au +#define CYREG_B0_P1_U0_CFG27 0x4001025bu +#define CYREG_B0_P1_U0_CFG28 0x4001025cu +#define CYREG_B0_P1_U0_CFG29 0x4001025du +#define CYREG_B0_P1_U0_CFG30 0x4001025eu +#define CYREG_B0_P1_U0_CFG31 0x4001025fu +#define CYREG_B0_P1_U0_DCFG0 0x40010260u +#define CYREG_B0_P1_U0_DCFG1 0x40010262u +#define CYREG_B0_P1_U0_DCFG2 0x40010264u +#define CYREG_B0_P1_U0_DCFG3 0x40010266u +#define CYREG_B0_P1_U0_DCFG4 0x40010268u +#define CYREG_B0_P1_U0_DCFG5 0x4001026au +#define CYREG_B0_P1_U0_DCFG6 0x4001026cu +#define CYREG_B0_P1_U0_DCFG7 0x4001026eu +#define CYDEV_UCFG_B0_P1_U1_BASE 0x40010280u +#define CYDEV_UCFG_B0_P1_U1_SIZE 0x00000070u +#define CYREG_B0_P1_U1_PLD_IT0 0x40010280u +#define CYREG_B0_P1_U1_PLD_IT1 0x40010284u +#define CYREG_B0_P1_U1_PLD_IT2 0x40010288u +#define CYREG_B0_P1_U1_PLD_IT3 0x4001028cu +#define CYREG_B0_P1_U1_PLD_IT4 0x40010290u +#define CYREG_B0_P1_U1_PLD_IT5 0x40010294u +#define CYREG_B0_P1_U1_PLD_IT6 0x40010298u +#define CYREG_B0_P1_U1_PLD_IT7 0x4001029cu +#define CYREG_B0_P1_U1_PLD_IT8 0x400102a0u +#define CYREG_B0_P1_U1_PLD_IT9 0x400102a4u +#define CYREG_B0_P1_U1_PLD_IT10 0x400102a8u +#define CYREG_B0_P1_U1_PLD_IT11 0x400102acu +#define CYREG_B0_P1_U1_PLD_ORT0 0x400102b0u +#define CYREG_B0_P1_U1_PLD_ORT1 0x400102b2u +#define CYREG_B0_P1_U1_PLD_ORT2 0x400102b4u +#define CYREG_B0_P1_U1_PLD_ORT3 0x400102b6u +#define CYREG_B0_P1_U1_MC_CFG_CEN_CONST 0x400102b8u +#define CYREG_B0_P1_U1_MC_CFG_XORFB 0x400102bau +#define CYREG_B0_P1_U1_MC_CFG_SET_RESET 0x400102bcu +#define CYREG_B0_P1_U1_MC_CFG_BYPASS 0x400102beu +#define CYREG_B0_P1_U1_CFG0 0x400102c0u +#define CYREG_B0_P1_U1_CFG1 0x400102c1u +#define CYREG_B0_P1_U1_CFG2 0x400102c2u +#define CYREG_B0_P1_U1_CFG3 0x400102c3u +#define CYREG_B0_P1_U1_CFG4 0x400102c4u +#define CYREG_B0_P1_U1_CFG5 0x400102c5u +#define CYREG_B0_P1_U1_CFG6 0x400102c6u +#define CYREG_B0_P1_U1_CFG7 0x400102c7u +#define CYREG_B0_P1_U1_CFG8 0x400102c8u +#define CYREG_B0_P1_U1_CFG9 0x400102c9u +#define CYREG_B0_P1_U1_CFG10 0x400102cau +#define CYREG_B0_P1_U1_CFG11 0x400102cbu +#define CYREG_B0_P1_U1_CFG12 0x400102ccu +#define CYREG_B0_P1_U1_CFG13 0x400102cdu +#define CYREG_B0_P1_U1_CFG14 0x400102ceu +#define CYREG_B0_P1_U1_CFG15 0x400102cfu +#define CYREG_B0_P1_U1_CFG16 0x400102d0u +#define CYREG_B0_P1_U1_CFG17 0x400102d1u +#define CYREG_B0_P1_U1_CFG18 0x400102d2u +#define CYREG_B0_P1_U1_CFG19 0x400102d3u +#define CYREG_B0_P1_U1_CFG20 0x400102d4u +#define CYREG_B0_P1_U1_CFG21 0x400102d5u +#define CYREG_B0_P1_U1_CFG22 0x400102d6u +#define CYREG_B0_P1_U1_CFG23 0x400102d7u +#define CYREG_B0_P1_U1_CFG24 0x400102d8u +#define CYREG_B0_P1_U1_CFG25 0x400102d9u +#define CYREG_B0_P1_U1_CFG26 0x400102dau +#define CYREG_B0_P1_U1_CFG27 0x400102dbu +#define CYREG_B0_P1_U1_CFG28 0x400102dcu +#define CYREG_B0_P1_U1_CFG29 0x400102ddu +#define CYREG_B0_P1_U1_CFG30 0x400102deu +#define CYREG_B0_P1_U1_CFG31 0x400102dfu +#define CYREG_B0_P1_U1_DCFG0 0x400102e0u +#define CYREG_B0_P1_U1_DCFG1 0x400102e2u +#define CYREG_B0_P1_U1_DCFG2 0x400102e4u +#define CYREG_B0_P1_U1_DCFG3 0x400102e6u +#define CYREG_B0_P1_U1_DCFG4 0x400102e8u +#define CYREG_B0_P1_U1_DCFG5 0x400102eau +#define CYREG_B0_P1_U1_DCFG6 0x400102ecu +#define CYREG_B0_P1_U1_DCFG7 0x400102eeu +#define CYDEV_UCFG_B0_P1_ROUTE_BASE 0x40010300u +#define CYDEV_UCFG_B0_P1_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P2_BASE 0x40010400u +#define CYDEV_UCFG_B0_P2_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P2_U0_BASE 0x40010400u +#define CYDEV_UCFG_B0_P2_U0_SIZE 0x00000070u +#define CYREG_B0_P2_U0_PLD_IT0 0x40010400u +#define CYREG_B0_P2_U0_PLD_IT1 0x40010404u +#define CYREG_B0_P2_U0_PLD_IT2 0x40010408u +#define CYREG_B0_P2_U0_PLD_IT3 0x4001040cu +#define CYREG_B0_P2_U0_PLD_IT4 0x40010410u +#define CYREG_B0_P2_U0_PLD_IT5 0x40010414u +#define CYREG_B0_P2_U0_PLD_IT6 0x40010418u +#define CYREG_B0_P2_U0_PLD_IT7 0x4001041cu +#define CYREG_B0_P2_U0_PLD_IT8 0x40010420u +#define CYREG_B0_P2_U0_PLD_IT9 0x40010424u +#define CYREG_B0_P2_U0_PLD_IT10 0x40010428u +#define CYREG_B0_P2_U0_PLD_IT11 0x4001042cu +#define CYREG_B0_P2_U0_PLD_ORT0 0x40010430u +#define CYREG_B0_P2_U0_PLD_ORT1 0x40010432u +#define CYREG_B0_P2_U0_PLD_ORT2 0x40010434u +#define CYREG_B0_P2_U0_PLD_ORT3 0x40010436u +#define CYREG_B0_P2_U0_MC_CFG_CEN_CONST 0x40010438u +#define CYREG_B0_P2_U0_MC_CFG_XORFB 0x4001043au +#define CYREG_B0_P2_U0_MC_CFG_SET_RESET 0x4001043cu +#define CYREG_B0_P2_U0_MC_CFG_BYPASS 0x4001043eu +#define CYREG_B0_P2_U0_CFG0 0x40010440u +#define CYREG_B0_P2_U0_CFG1 0x40010441u +#define CYREG_B0_P2_U0_CFG2 0x40010442u +#define CYREG_B0_P2_U0_CFG3 0x40010443u +#define CYREG_B0_P2_U0_CFG4 0x40010444u +#define CYREG_B0_P2_U0_CFG5 0x40010445u +#define CYREG_B0_P2_U0_CFG6 0x40010446u +#define CYREG_B0_P2_U0_CFG7 0x40010447u +#define CYREG_B0_P2_U0_CFG8 0x40010448u +#define CYREG_B0_P2_U0_CFG9 0x40010449u +#define CYREG_B0_P2_U0_CFG10 0x4001044au +#define CYREG_B0_P2_U0_CFG11 0x4001044bu +#define CYREG_B0_P2_U0_CFG12 0x4001044cu +#define CYREG_B0_P2_U0_CFG13 0x4001044du +#define CYREG_B0_P2_U0_CFG14 0x4001044eu +#define CYREG_B0_P2_U0_CFG15 0x4001044fu +#define CYREG_B0_P2_U0_CFG16 0x40010450u +#define CYREG_B0_P2_U0_CFG17 0x40010451u +#define CYREG_B0_P2_U0_CFG18 0x40010452u +#define CYREG_B0_P2_U0_CFG19 0x40010453u +#define CYREG_B0_P2_U0_CFG20 0x40010454u +#define CYREG_B0_P2_U0_CFG21 0x40010455u +#define CYREG_B0_P2_U0_CFG22 0x40010456u +#define CYREG_B0_P2_U0_CFG23 0x40010457u +#define CYREG_B0_P2_U0_CFG24 0x40010458u +#define CYREG_B0_P2_U0_CFG25 0x40010459u +#define CYREG_B0_P2_U0_CFG26 0x4001045au +#define CYREG_B0_P2_U0_CFG27 0x4001045bu +#define CYREG_B0_P2_U0_CFG28 0x4001045cu +#define CYREG_B0_P2_U0_CFG29 0x4001045du +#define CYREG_B0_P2_U0_CFG30 0x4001045eu +#define CYREG_B0_P2_U0_CFG31 0x4001045fu +#define CYREG_B0_P2_U0_DCFG0 0x40010460u +#define CYREG_B0_P2_U0_DCFG1 0x40010462u +#define CYREG_B0_P2_U0_DCFG2 0x40010464u +#define CYREG_B0_P2_U0_DCFG3 0x40010466u +#define CYREG_B0_P2_U0_DCFG4 0x40010468u +#define CYREG_B0_P2_U0_DCFG5 0x4001046au +#define CYREG_B0_P2_U0_DCFG6 0x4001046cu +#define CYREG_B0_P2_U0_DCFG7 0x4001046eu +#define CYDEV_UCFG_B0_P2_U1_BASE 0x40010480u +#define CYDEV_UCFG_B0_P2_U1_SIZE 0x00000070u +#define CYREG_B0_P2_U1_PLD_IT0 0x40010480u +#define CYREG_B0_P2_U1_PLD_IT1 0x40010484u +#define CYREG_B0_P2_U1_PLD_IT2 0x40010488u +#define CYREG_B0_P2_U1_PLD_IT3 0x4001048cu +#define CYREG_B0_P2_U1_PLD_IT4 0x40010490u +#define CYREG_B0_P2_U1_PLD_IT5 0x40010494u +#define CYREG_B0_P2_U1_PLD_IT6 0x40010498u +#define CYREG_B0_P2_U1_PLD_IT7 0x4001049cu +#define CYREG_B0_P2_U1_PLD_IT8 0x400104a0u +#define CYREG_B0_P2_U1_PLD_IT9 0x400104a4u +#define CYREG_B0_P2_U1_PLD_IT10 0x400104a8u +#define CYREG_B0_P2_U1_PLD_IT11 0x400104acu +#define CYREG_B0_P2_U1_PLD_ORT0 0x400104b0u +#define CYREG_B0_P2_U1_PLD_ORT1 0x400104b2u +#define CYREG_B0_P2_U1_PLD_ORT2 0x400104b4u +#define CYREG_B0_P2_U1_PLD_ORT3 0x400104b6u +#define CYREG_B0_P2_U1_MC_CFG_CEN_CONST 0x400104b8u +#define CYREG_B0_P2_U1_MC_CFG_XORFB 0x400104bau +#define CYREG_B0_P2_U1_MC_CFG_SET_RESET 0x400104bcu +#define CYREG_B0_P2_U1_MC_CFG_BYPASS 0x400104beu +#define CYREG_B0_P2_U1_CFG0 0x400104c0u +#define CYREG_B0_P2_U1_CFG1 0x400104c1u +#define CYREG_B0_P2_U1_CFG2 0x400104c2u +#define CYREG_B0_P2_U1_CFG3 0x400104c3u +#define CYREG_B0_P2_U1_CFG4 0x400104c4u +#define CYREG_B0_P2_U1_CFG5 0x400104c5u +#define CYREG_B0_P2_U1_CFG6 0x400104c6u +#define CYREG_B0_P2_U1_CFG7 0x400104c7u +#define CYREG_B0_P2_U1_CFG8 0x400104c8u +#define CYREG_B0_P2_U1_CFG9 0x400104c9u +#define CYREG_B0_P2_U1_CFG10 0x400104cau +#define CYREG_B0_P2_U1_CFG11 0x400104cbu +#define CYREG_B0_P2_U1_CFG12 0x400104ccu +#define CYREG_B0_P2_U1_CFG13 0x400104cdu +#define CYREG_B0_P2_U1_CFG14 0x400104ceu +#define CYREG_B0_P2_U1_CFG15 0x400104cfu +#define CYREG_B0_P2_U1_CFG16 0x400104d0u +#define CYREG_B0_P2_U1_CFG17 0x400104d1u +#define CYREG_B0_P2_U1_CFG18 0x400104d2u +#define CYREG_B0_P2_U1_CFG19 0x400104d3u +#define CYREG_B0_P2_U1_CFG20 0x400104d4u +#define CYREG_B0_P2_U1_CFG21 0x400104d5u +#define CYREG_B0_P2_U1_CFG22 0x400104d6u +#define CYREG_B0_P2_U1_CFG23 0x400104d7u +#define CYREG_B0_P2_U1_CFG24 0x400104d8u +#define CYREG_B0_P2_U1_CFG25 0x400104d9u +#define CYREG_B0_P2_U1_CFG26 0x400104dau +#define CYREG_B0_P2_U1_CFG27 0x400104dbu +#define CYREG_B0_P2_U1_CFG28 0x400104dcu +#define CYREG_B0_P2_U1_CFG29 0x400104ddu +#define CYREG_B0_P2_U1_CFG30 0x400104deu +#define CYREG_B0_P2_U1_CFG31 0x400104dfu +#define CYREG_B0_P2_U1_DCFG0 0x400104e0u +#define CYREG_B0_P2_U1_DCFG1 0x400104e2u +#define CYREG_B0_P2_U1_DCFG2 0x400104e4u +#define CYREG_B0_P2_U1_DCFG3 0x400104e6u +#define CYREG_B0_P2_U1_DCFG4 0x400104e8u +#define CYREG_B0_P2_U1_DCFG5 0x400104eau +#define CYREG_B0_P2_U1_DCFG6 0x400104ecu +#define CYREG_B0_P2_U1_DCFG7 0x400104eeu +#define CYDEV_UCFG_B0_P2_ROUTE_BASE 0x40010500u +#define CYDEV_UCFG_B0_P2_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P3_BASE 0x40010600u +#define CYDEV_UCFG_B0_P3_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P3_U0_BASE 0x40010600u +#define CYDEV_UCFG_B0_P3_U0_SIZE 0x00000070u +#define CYREG_B0_P3_U0_PLD_IT0 0x40010600u +#define CYREG_B0_P3_U0_PLD_IT1 0x40010604u +#define CYREG_B0_P3_U0_PLD_IT2 0x40010608u +#define CYREG_B0_P3_U0_PLD_IT3 0x4001060cu +#define CYREG_B0_P3_U0_PLD_IT4 0x40010610u +#define CYREG_B0_P3_U0_PLD_IT5 0x40010614u +#define CYREG_B0_P3_U0_PLD_IT6 0x40010618u +#define CYREG_B0_P3_U0_PLD_IT7 0x4001061cu +#define CYREG_B0_P3_U0_PLD_IT8 0x40010620u +#define CYREG_B0_P3_U0_PLD_IT9 0x40010624u +#define CYREG_B0_P3_U0_PLD_IT10 0x40010628u +#define CYREG_B0_P3_U0_PLD_IT11 0x4001062cu +#define CYREG_B0_P3_U0_PLD_ORT0 0x40010630u +#define CYREG_B0_P3_U0_PLD_ORT1 0x40010632u +#define CYREG_B0_P3_U0_PLD_ORT2 0x40010634u +#define CYREG_B0_P3_U0_PLD_ORT3 0x40010636u +#define CYREG_B0_P3_U0_MC_CFG_CEN_CONST 0x40010638u +#define CYREG_B0_P3_U0_MC_CFG_XORFB 0x4001063au +#define CYREG_B0_P3_U0_MC_CFG_SET_RESET 0x4001063cu +#define CYREG_B0_P3_U0_MC_CFG_BYPASS 0x4001063eu +#define CYREG_B0_P3_U0_CFG0 0x40010640u +#define CYREG_B0_P3_U0_CFG1 0x40010641u +#define CYREG_B0_P3_U0_CFG2 0x40010642u +#define CYREG_B0_P3_U0_CFG3 0x40010643u +#define CYREG_B0_P3_U0_CFG4 0x40010644u +#define CYREG_B0_P3_U0_CFG5 0x40010645u +#define CYREG_B0_P3_U0_CFG6 0x40010646u +#define CYREG_B0_P3_U0_CFG7 0x40010647u +#define CYREG_B0_P3_U0_CFG8 0x40010648u +#define CYREG_B0_P3_U0_CFG9 0x40010649u +#define CYREG_B0_P3_U0_CFG10 0x4001064au +#define CYREG_B0_P3_U0_CFG11 0x4001064bu +#define CYREG_B0_P3_U0_CFG12 0x4001064cu +#define CYREG_B0_P3_U0_CFG13 0x4001064du +#define CYREG_B0_P3_U0_CFG14 0x4001064eu +#define CYREG_B0_P3_U0_CFG15 0x4001064fu +#define CYREG_B0_P3_U0_CFG16 0x40010650u +#define CYREG_B0_P3_U0_CFG17 0x40010651u +#define CYREG_B0_P3_U0_CFG18 0x40010652u +#define CYREG_B0_P3_U0_CFG19 0x40010653u +#define CYREG_B0_P3_U0_CFG20 0x40010654u +#define CYREG_B0_P3_U0_CFG21 0x40010655u +#define CYREG_B0_P3_U0_CFG22 0x40010656u +#define CYREG_B0_P3_U0_CFG23 0x40010657u +#define CYREG_B0_P3_U0_CFG24 0x40010658u +#define CYREG_B0_P3_U0_CFG25 0x40010659u +#define CYREG_B0_P3_U0_CFG26 0x4001065au +#define CYREG_B0_P3_U0_CFG27 0x4001065bu +#define CYREG_B0_P3_U0_CFG28 0x4001065cu +#define CYREG_B0_P3_U0_CFG29 0x4001065du +#define CYREG_B0_P3_U0_CFG30 0x4001065eu +#define CYREG_B0_P3_U0_CFG31 0x4001065fu +#define CYREG_B0_P3_U0_DCFG0 0x40010660u +#define CYREG_B0_P3_U0_DCFG1 0x40010662u +#define CYREG_B0_P3_U0_DCFG2 0x40010664u +#define CYREG_B0_P3_U0_DCFG3 0x40010666u +#define CYREG_B0_P3_U0_DCFG4 0x40010668u +#define CYREG_B0_P3_U0_DCFG5 0x4001066au +#define CYREG_B0_P3_U0_DCFG6 0x4001066cu +#define CYREG_B0_P3_U0_DCFG7 0x4001066eu +#define CYDEV_UCFG_B0_P3_U1_BASE 0x40010680u +#define CYDEV_UCFG_B0_P3_U1_SIZE 0x00000070u +#define CYREG_B0_P3_U1_PLD_IT0 0x40010680u +#define CYREG_B0_P3_U1_PLD_IT1 0x40010684u +#define CYREG_B0_P3_U1_PLD_IT2 0x40010688u +#define CYREG_B0_P3_U1_PLD_IT3 0x4001068cu +#define CYREG_B0_P3_U1_PLD_IT4 0x40010690u +#define CYREG_B0_P3_U1_PLD_IT5 0x40010694u +#define CYREG_B0_P3_U1_PLD_IT6 0x40010698u +#define CYREG_B0_P3_U1_PLD_IT7 0x4001069cu +#define CYREG_B0_P3_U1_PLD_IT8 0x400106a0u +#define CYREG_B0_P3_U1_PLD_IT9 0x400106a4u +#define CYREG_B0_P3_U1_PLD_IT10 0x400106a8u +#define CYREG_B0_P3_U1_PLD_IT11 0x400106acu +#define CYREG_B0_P3_U1_PLD_ORT0 0x400106b0u +#define CYREG_B0_P3_U1_PLD_ORT1 0x400106b2u +#define CYREG_B0_P3_U1_PLD_ORT2 0x400106b4u +#define CYREG_B0_P3_U1_PLD_ORT3 0x400106b6u +#define CYREG_B0_P3_U1_MC_CFG_CEN_CONST 0x400106b8u +#define CYREG_B0_P3_U1_MC_CFG_XORFB 0x400106bau +#define CYREG_B0_P3_U1_MC_CFG_SET_RESET 0x400106bcu +#define CYREG_B0_P3_U1_MC_CFG_BYPASS 0x400106beu +#define CYREG_B0_P3_U1_CFG0 0x400106c0u +#define CYREG_B0_P3_U1_CFG1 0x400106c1u +#define CYREG_B0_P3_U1_CFG2 0x400106c2u +#define CYREG_B0_P3_U1_CFG3 0x400106c3u +#define CYREG_B0_P3_U1_CFG4 0x400106c4u +#define CYREG_B0_P3_U1_CFG5 0x400106c5u +#define CYREG_B0_P3_U1_CFG6 0x400106c6u +#define CYREG_B0_P3_U1_CFG7 0x400106c7u +#define CYREG_B0_P3_U1_CFG8 0x400106c8u +#define CYREG_B0_P3_U1_CFG9 0x400106c9u +#define CYREG_B0_P3_U1_CFG10 0x400106cau +#define CYREG_B0_P3_U1_CFG11 0x400106cbu +#define CYREG_B0_P3_U1_CFG12 0x400106ccu +#define CYREG_B0_P3_U1_CFG13 0x400106cdu +#define CYREG_B0_P3_U1_CFG14 0x400106ceu +#define CYREG_B0_P3_U1_CFG15 0x400106cfu +#define CYREG_B0_P3_U1_CFG16 0x400106d0u +#define CYREG_B0_P3_U1_CFG17 0x400106d1u +#define CYREG_B0_P3_U1_CFG18 0x400106d2u +#define CYREG_B0_P3_U1_CFG19 0x400106d3u +#define CYREG_B0_P3_U1_CFG20 0x400106d4u +#define CYREG_B0_P3_U1_CFG21 0x400106d5u +#define CYREG_B0_P3_U1_CFG22 0x400106d6u +#define CYREG_B0_P3_U1_CFG23 0x400106d7u +#define CYREG_B0_P3_U1_CFG24 0x400106d8u +#define CYREG_B0_P3_U1_CFG25 0x400106d9u +#define CYREG_B0_P3_U1_CFG26 0x400106dau +#define CYREG_B0_P3_U1_CFG27 0x400106dbu +#define CYREG_B0_P3_U1_CFG28 0x400106dcu +#define CYREG_B0_P3_U1_CFG29 0x400106ddu +#define CYREG_B0_P3_U1_CFG30 0x400106deu +#define CYREG_B0_P3_U1_CFG31 0x400106dfu +#define CYREG_B0_P3_U1_DCFG0 0x400106e0u +#define CYREG_B0_P3_U1_DCFG1 0x400106e2u +#define CYREG_B0_P3_U1_DCFG2 0x400106e4u +#define CYREG_B0_P3_U1_DCFG3 0x400106e6u +#define CYREG_B0_P3_U1_DCFG4 0x400106e8u +#define CYREG_B0_P3_U1_DCFG5 0x400106eau +#define CYREG_B0_P3_U1_DCFG6 0x400106ecu +#define CYREG_B0_P3_U1_DCFG7 0x400106eeu +#define CYDEV_UCFG_B0_P3_ROUTE_BASE 0x40010700u +#define CYDEV_UCFG_B0_P3_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P4_BASE 0x40010800u +#define CYDEV_UCFG_B0_P4_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P4_U0_BASE 0x40010800u +#define CYDEV_UCFG_B0_P4_U0_SIZE 0x00000070u +#define CYREG_B0_P4_U0_PLD_IT0 0x40010800u +#define CYREG_B0_P4_U0_PLD_IT1 0x40010804u +#define CYREG_B0_P4_U0_PLD_IT2 0x40010808u +#define CYREG_B0_P4_U0_PLD_IT3 0x4001080cu +#define CYREG_B0_P4_U0_PLD_IT4 0x40010810u +#define CYREG_B0_P4_U0_PLD_IT5 0x40010814u +#define CYREG_B0_P4_U0_PLD_IT6 0x40010818u +#define CYREG_B0_P4_U0_PLD_IT7 0x4001081cu +#define CYREG_B0_P4_U0_PLD_IT8 0x40010820u +#define CYREG_B0_P4_U0_PLD_IT9 0x40010824u +#define CYREG_B0_P4_U0_PLD_IT10 0x40010828u +#define CYREG_B0_P4_U0_PLD_IT11 0x4001082cu +#define CYREG_B0_P4_U0_PLD_ORT0 0x40010830u +#define CYREG_B0_P4_U0_PLD_ORT1 0x40010832u +#define CYREG_B0_P4_U0_PLD_ORT2 0x40010834u +#define CYREG_B0_P4_U0_PLD_ORT3 0x40010836u +#define CYREG_B0_P4_U0_MC_CFG_CEN_CONST 0x40010838u +#define CYREG_B0_P4_U0_MC_CFG_XORFB 0x4001083au +#define CYREG_B0_P4_U0_MC_CFG_SET_RESET 0x4001083cu +#define CYREG_B0_P4_U0_MC_CFG_BYPASS 0x4001083eu +#define CYREG_B0_P4_U0_CFG0 0x40010840u +#define CYREG_B0_P4_U0_CFG1 0x40010841u +#define CYREG_B0_P4_U0_CFG2 0x40010842u +#define CYREG_B0_P4_U0_CFG3 0x40010843u +#define CYREG_B0_P4_U0_CFG4 0x40010844u +#define CYREG_B0_P4_U0_CFG5 0x40010845u +#define CYREG_B0_P4_U0_CFG6 0x40010846u +#define CYREG_B0_P4_U0_CFG7 0x40010847u +#define CYREG_B0_P4_U0_CFG8 0x40010848u +#define CYREG_B0_P4_U0_CFG9 0x40010849u +#define CYREG_B0_P4_U0_CFG10 0x4001084au +#define CYREG_B0_P4_U0_CFG11 0x4001084bu +#define CYREG_B0_P4_U0_CFG12 0x4001084cu +#define CYREG_B0_P4_U0_CFG13 0x4001084du +#define CYREG_B0_P4_U0_CFG14 0x4001084eu +#define CYREG_B0_P4_U0_CFG15 0x4001084fu +#define CYREG_B0_P4_U0_CFG16 0x40010850u +#define CYREG_B0_P4_U0_CFG17 0x40010851u +#define CYREG_B0_P4_U0_CFG18 0x40010852u +#define CYREG_B0_P4_U0_CFG19 0x40010853u +#define CYREG_B0_P4_U0_CFG20 0x40010854u +#define CYREG_B0_P4_U0_CFG21 0x40010855u +#define CYREG_B0_P4_U0_CFG22 0x40010856u +#define CYREG_B0_P4_U0_CFG23 0x40010857u +#define CYREG_B0_P4_U0_CFG24 0x40010858u +#define CYREG_B0_P4_U0_CFG25 0x40010859u +#define CYREG_B0_P4_U0_CFG26 0x4001085au +#define CYREG_B0_P4_U0_CFG27 0x4001085bu +#define CYREG_B0_P4_U0_CFG28 0x4001085cu +#define CYREG_B0_P4_U0_CFG29 0x4001085du +#define CYREG_B0_P4_U0_CFG30 0x4001085eu +#define CYREG_B0_P4_U0_CFG31 0x4001085fu +#define CYREG_B0_P4_U0_DCFG0 0x40010860u +#define CYREG_B0_P4_U0_DCFG1 0x40010862u +#define CYREG_B0_P4_U0_DCFG2 0x40010864u +#define CYREG_B0_P4_U0_DCFG3 0x40010866u +#define CYREG_B0_P4_U0_DCFG4 0x40010868u +#define CYREG_B0_P4_U0_DCFG5 0x4001086au +#define CYREG_B0_P4_U0_DCFG6 0x4001086cu +#define CYREG_B0_P4_U0_DCFG7 0x4001086eu +#define CYDEV_UCFG_B0_P4_U1_BASE 0x40010880u +#define CYDEV_UCFG_B0_P4_U1_SIZE 0x00000070u +#define CYREG_B0_P4_U1_PLD_IT0 0x40010880u +#define CYREG_B0_P4_U1_PLD_IT1 0x40010884u +#define CYREG_B0_P4_U1_PLD_IT2 0x40010888u +#define CYREG_B0_P4_U1_PLD_IT3 0x4001088cu +#define CYREG_B0_P4_U1_PLD_IT4 0x40010890u +#define CYREG_B0_P4_U1_PLD_IT5 0x40010894u +#define CYREG_B0_P4_U1_PLD_IT6 0x40010898u +#define CYREG_B0_P4_U1_PLD_IT7 0x4001089cu +#define CYREG_B0_P4_U1_PLD_IT8 0x400108a0u +#define CYREG_B0_P4_U1_PLD_IT9 0x400108a4u +#define CYREG_B0_P4_U1_PLD_IT10 0x400108a8u +#define CYREG_B0_P4_U1_PLD_IT11 0x400108acu +#define CYREG_B0_P4_U1_PLD_ORT0 0x400108b0u +#define CYREG_B0_P4_U1_PLD_ORT1 0x400108b2u +#define CYREG_B0_P4_U1_PLD_ORT2 0x400108b4u +#define CYREG_B0_P4_U1_PLD_ORT3 0x400108b6u +#define CYREG_B0_P4_U1_MC_CFG_CEN_CONST 0x400108b8u +#define CYREG_B0_P4_U1_MC_CFG_XORFB 0x400108bau +#define CYREG_B0_P4_U1_MC_CFG_SET_RESET 0x400108bcu +#define CYREG_B0_P4_U1_MC_CFG_BYPASS 0x400108beu +#define CYREG_B0_P4_U1_CFG0 0x400108c0u +#define CYREG_B0_P4_U1_CFG1 0x400108c1u +#define CYREG_B0_P4_U1_CFG2 0x400108c2u +#define CYREG_B0_P4_U1_CFG3 0x400108c3u +#define CYREG_B0_P4_U1_CFG4 0x400108c4u +#define CYREG_B0_P4_U1_CFG5 0x400108c5u +#define CYREG_B0_P4_U1_CFG6 0x400108c6u +#define CYREG_B0_P4_U1_CFG7 0x400108c7u +#define CYREG_B0_P4_U1_CFG8 0x400108c8u +#define CYREG_B0_P4_U1_CFG9 0x400108c9u +#define CYREG_B0_P4_U1_CFG10 0x400108cau +#define CYREG_B0_P4_U1_CFG11 0x400108cbu +#define CYREG_B0_P4_U1_CFG12 0x400108ccu +#define CYREG_B0_P4_U1_CFG13 0x400108cdu +#define CYREG_B0_P4_U1_CFG14 0x400108ceu +#define CYREG_B0_P4_U1_CFG15 0x400108cfu +#define CYREG_B0_P4_U1_CFG16 0x400108d0u +#define CYREG_B0_P4_U1_CFG17 0x400108d1u +#define CYREG_B0_P4_U1_CFG18 0x400108d2u +#define CYREG_B0_P4_U1_CFG19 0x400108d3u +#define CYREG_B0_P4_U1_CFG20 0x400108d4u +#define CYREG_B0_P4_U1_CFG21 0x400108d5u +#define CYREG_B0_P4_U1_CFG22 0x400108d6u +#define CYREG_B0_P4_U1_CFG23 0x400108d7u +#define CYREG_B0_P4_U1_CFG24 0x400108d8u +#define CYREG_B0_P4_U1_CFG25 0x400108d9u +#define CYREG_B0_P4_U1_CFG26 0x400108dau +#define CYREG_B0_P4_U1_CFG27 0x400108dbu +#define CYREG_B0_P4_U1_CFG28 0x400108dcu +#define CYREG_B0_P4_U1_CFG29 0x400108ddu +#define CYREG_B0_P4_U1_CFG30 0x400108deu +#define CYREG_B0_P4_U1_CFG31 0x400108dfu +#define CYREG_B0_P4_U1_DCFG0 0x400108e0u +#define CYREG_B0_P4_U1_DCFG1 0x400108e2u +#define CYREG_B0_P4_U1_DCFG2 0x400108e4u +#define CYREG_B0_P4_U1_DCFG3 0x400108e6u +#define CYREG_B0_P4_U1_DCFG4 0x400108e8u +#define CYREG_B0_P4_U1_DCFG5 0x400108eau +#define CYREG_B0_P4_U1_DCFG6 0x400108ecu +#define CYREG_B0_P4_U1_DCFG7 0x400108eeu +#define CYDEV_UCFG_B0_P4_ROUTE_BASE 0x40010900u +#define CYDEV_UCFG_B0_P4_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P5_BASE 0x40010a00u +#define CYDEV_UCFG_B0_P5_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P5_U0_BASE 0x40010a00u +#define CYDEV_UCFG_B0_P5_U0_SIZE 0x00000070u +#define CYREG_B0_P5_U0_PLD_IT0 0x40010a00u +#define CYREG_B0_P5_U0_PLD_IT1 0x40010a04u +#define CYREG_B0_P5_U0_PLD_IT2 0x40010a08u +#define CYREG_B0_P5_U0_PLD_IT3 0x40010a0cu +#define CYREG_B0_P5_U0_PLD_IT4 0x40010a10u +#define CYREG_B0_P5_U0_PLD_IT5 0x40010a14u +#define CYREG_B0_P5_U0_PLD_IT6 0x40010a18u +#define CYREG_B0_P5_U0_PLD_IT7 0x40010a1cu +#define CYREG_B0_P5_U0_PLD_IT8 0x40010a20u +#define CYREG_B0_P5_U0_PLD_IT9 0x40010a24u +#define CYREG_B0_P5_U0_PLD_IT10 0x40010a28u +#define CYREG_B0_P5_U0_PLD_IT11 0x40010a2cu +#define CYREG_B0_P5_U0_PLD_ORT0 0x40010a30u +#define CYREG_B0_P5_U0_PLD_ORT1 0x40010a32u +#define CYREG_B0_P5_U0_PLD_ORT2 0x40010a34u +#define CYREG_B0_P5_U0_PLD_ORT3 0x40010a36u +#define CYREG_B0_P5_U0_MC_CFG_CEN_CONST 0x40010a38u +#define CYREG_B0_P5_U0_MC_CFG_XORFB 0x40010a3au +#define CYREG_B0_P5_U0_MC_CFG_SET_RESET 0x40010a3cu +#define CYREG_B0_P5_U0_MC_CFG_BYPASS 0x40010a3eu +#define CYREG_B0_P5_U0_CFG0 0x40010a40u +#define CYREG_B0_P5_U0_CFG1 0x40010a41u +#define CYREG_B0_P5_U0_CFG2 0x40010a42u +#define CYREG_B0_P5_U0_CFG3 0x40010a43u +#define CYREG_B0_P5_U0_CFG4 0x40010a44u +#define CYREG_B0_P5_U0_CFG5 0x40010a45u +#define CYREG_B0_P5_U0_CFG6 0x40010a46u +#define CYREG_B0_P5_U0_CFG7 0x40010a47u +#define CYREG_B0_P5_U0_CFG8 0x40010a48u +#define CYREG_B0_P5_U0_CFG9 0x40010a49u +#define CYREG_B0_P5_U0_CFG10 0x40010a4au +#define CYREG_B0_P5_U0_CFG11 0x40010a4bu +#define CYREG_B0_P5_U0_CFG12 0x40010a4cu +#define CYREG_B0_P5_U0_CFG13 0x40010a4du +#define CYREG_B0_P5_U0_CFG14 0x40010a4eu +#define CYREG_B0_P5_U0_CFG15 0x40010a4fu +#define CYREG_B0_P5_U0_CFG16 0x40010a50u +#define CYREG_B0_P5_U0_CFG17 0x40010a51u +#define CYREG_B0_P5_U0_CFG18 0x40010a52u +#define CYREG_B0_P5_U0_CFG19 0x40010a53u +#define CYREG_B0_P5_U0_CFG20 0x40010a54u +#define CYREG_B0_P5_U0_CFG21 0x40010a55u +#define CYREG_B0_P5_U0_CFG22 0x40010a56u +#define CYREG_B0_P5_U0_CFG23 0x40010a57u +#define CYREG_B0_P5_U0_CFG24 0x40010a58u +#define CYREG_B0_P5_U0_CFG25 0x40010a59u +#define CYREG_B0_P5_U0_CFG26 0x40010a5au +#define CYREG_B0_P5_U0_CFG27 0x40010a5bu +#define CYREG_B0_P5_U0_CFG28 0x40010a5cu +#define CYREG_B0_P5_U0_CFG29 0x40010a5du +#define CYREG_B0_P5_U0_CFG30 0x40010a5eu +#define CYREG_B0_P5_U0_CFG31 0x40010a5fu +#define CYREG_B0_P5_U0_DCFG0 0x40010a60u +#define CYREG_B0_P5_U0_DCFG1 0x40010a62u +#define CYREG_B0_P5_U0_DCFG2 0x40010a64u +#define CYREG_B0_P5_U0_DCFG3 0x40010a66u +#define CYREG_B0_P5_U0_DCFG4 0x40010a68u +#define CYREG_B0_P5_U0_DCFG5 0x40010a6au +#define CYREG_B0_P5_U0_DCFG6 0x40010a6cu +#define CYREG_B0_P5_U0_DCFG7 0x40010a6eu +#define CYDEV_UCFG_B0_P5_U1_BASE 0x40010a80u +#define CYDEV_UCFG_B0_P5_U1_SIZE 0x00000070u +#define CYREG_B0_P5_U1_PLD_IT0 0x40010a80u +#define CYREG_B0_P5_U1_PLD_IT1 0x40010a84u +#define CYREG_B0_P5_U1_PLD_IT2 0x40010a88u +#define CYREG_B0_P5_U1_PLD_IT3 0x40010a8cu +#define CYREG_B0_P5_U1_PLD_IT4 0x40010a90u +#define CYREG_B0_P5_U1_PLD_IT5 0x40010a94u +#define CYREG_B0_P5_U1_PLD_IT6 0x40010a98u +#define CYREG_B0_P5_U1_PLD_IT7 0x40010a9cu +#define CYREG_B0_P5_U1_PLD_IT8 0x40010aa0u +#define CYREG_B0_P5_U1_PLD_IT9 0x40010aa4u +#define CYREG_B0_P5_U1_PLD_IT10 0x40010aa8u +#define CYREG_B0_P5_U1_PLD_IT11 0x40010aacu +#define CYREG_B0_P5_U1_PLD_ORT0 0x40010ab0u +#define CYREG_B0_P5_U1_PLD_ORT1 0x40010ab2u +#define CYREG_B0_P5_U1_PLD_ORT2 0x40010ab4u +#define CYREG_B0_P5_U1_PLD_ORT3 0x40010ab6u +#define CYREG_B0_P5_U1_MC_CFG_CEN_CONST 0x40010ab8u +#define CYREG_B0_P5_U1_MC_CFG_XORFB 0x40010abau +#define CYREG_B0_P5_U1_MC_CFG_SET_RESET 0x40010abcu +#define CYREG_B0_P5_U1_MC_CFG_BYPASS 0x40010abeu +#define CYREG_B0_P5_U1_CFG0 0x40010ac0u +#define CYREG_B0_P5_U1_CFG1 0x40010ac1u +#define CYREG_B0_P5_U1_CFG2 0x40010ac2u +#define CYREG_B0_P5_U1_CFG3 0x40010ac3u +#define CYREG_B0_P5_U1_CFG4 0x40010ac4u +#define CYREG_B0_P5_U1_CFG5 0x40010ac5u +#define CYREG_B0_P5_U1_CFG6 0x40010ac6u +#define CYREG_B0_P5_U1_CFG7 0x40010ac7u +#define CYREG_B0_P5_U1_CFG8 0x40010ac8u +#define CYREG_B0_P5_U1_CFG9 0x40010ac9u +#define CYREG_B0_P5_U1_CFG10 0x40010acau +#define CYREG_B0_P5_U1_CFG11 0x40010acbu +#define CYREG_B0_P5_U1_CFG12 0x40010accu +#define CYREG_B0_P5_U1_CFG13 0x40010acdu +#define CYREG_B0_P5_U1_CFG14 0x40010aceu +#define CYREG_B0_P5_U1_CFG15 0x40010acfu +#define CYREG_B0_P5_U1_CFG16 0x40010ad0u +#define CYREG_B0_P5_U1_CFG17 0x40010ad1u +#define CYREG_B0_P5_U1_CFG18 0x40010ad2u +#define CYREG_B0_P5_U1_CFG19 0x40010ad3u +#define CYREG_B0_P5_U1_CFG20 0x40010ad4u +#define CYREG_B0_P5_U1_CFG21 0x40010ad5u +#define CYREG_B0_P5_U1_CFG22 0x40010ad6u +#define CYREG_B0_P5_U1_CFG23 0x40010ad7u +#define CYREG_B0_P5_U1_CFG24 0x40010ad8u +#define CYREG_B0_P5_U1_CFG25 0x40010ad9u +#define CYREG_B0_P5_U1_CFG26 0x40010adau +#define CYREG_B0_P5_U1_CFG27 0x40010adbu +#define CYREG_B0_P5_U1_CFG28 0x40010adcu +#define CYREG_B0_P5_U1_CFG29 0x40010addu +#define CYREG_B0_P5_U1_CFG30 0x40010adeu +#define CYREG_B0_P5_U1_CFG31 0x40010adfu +#define CYREG_B0_P5_U1_DCFG0 0x40010ae0u +#define CYREG_B0_P5_U1_DCFG1 0x40010ae2u +#define CYREG_B0_P5_U1_DCFG2 0x40010ae4u +#define CYREG_B0_P5_U1_DCFG3 0x40010ae6u +#define CYREG_B0_P5_U1_DCFG4 0x40010ae8u +#define CYREG_B0_P5_U1_DCFG5 0x40010aeau +#define CYREG_B0_P5_U1_DCFG6 0x40010aecu +#define CYREG_B0_P5_U1_DCFG7 0x40010aeeu +#define CYDEV_UCFG_B0_P5_ROUTE_BASE 0x40010b00u +#define CYDEV_UCFG_B0_P5_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P6_BASE 0x40010c00u +#define CYDEV_UCFG_B0_P6_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P6_U0_BASE 0x40010c00u +#define CYDEV_UCFG_B0_P6_U0_SIZE 0x00000070u +#define CYREG_B0_P6_U0_PLD_IT0 0x40010c00u +#define CYREG_B0_P6_U0_PLD_IT1 0x40010c04u +#define CYREG_B0_P6_U0_PLD_IT2 0x40010c08u +#define CYREG_B0_P6_U0_PLD_IT3 0x40010c0cu +#define CYREG_B0_P6_U0_PLD_IT4 0x40010c10u +#define CYREG_B0_P6_U0_PLD_IT5 0x40010c14u +#define CYREG_B0_P6_U0_PLD_IT6 0x40010c18u +#define CYREG_B0_P6_U0_PLD_IT7 0x40010c1cu +#define CYREG_B0_P6_U0_PLD_IT8 0x40010c20u +#define CYREG_B0_P6_U0_PLD_IT9 0x40010c24u +#define CYREG_B0_P6_U0_PLD_IT10 0x40010c28u +#define CYREG_B0_P6_U0_PLD_IT11 0x40010c2cu +#define CYREG_B0_P6_U0_PLD_ORT0 0x40010c30u +#define CYREG_B0_P6_U0_PLD_ORT1 0x40010c32u +#define CYREG_B0_P6_U0_PLD_ORT2 0x40010c34u +#define CYREG_B0_P6_U0_PLD_ORT3 0x40010c36u +#define CYREG_B0_P6_U0_MC_CFG_CEN_CONST 0x40010c38u +#define CYREG_B0_P6_U0_MC_CFG_XORFB 0x40010c3au +#define CYREG_B0_P6_U0_MC_CFG_SET_RESET 0x40010c3cu +#define CYREG_B0_P6_U0_MC_CFG_BYPASS 0x40010c3eu +#define CYREG_B0_P6_U0_CFG0 0x40010c40u +#define CYREG_B0_P6_U0_CFG1 0x40010c41u +#define CYREG_B0_P6_U0_CFG2 0x40010c42u +#define CYREG_B0_P6_U0_CFG3 0x40010c43u +#define CYREG_B0_P6_U0_CFG4 0x40010c44u +#define CYREG_B0_P6_U0_CFG5 0x40010c45u +#define CYREG_B0_P6_U0_CFG6 0x40010c46u +#define CYREG_B0_P6_U0_CFG7 0x40010c47u +#define CYREG_B0_P6_U0_CFG8 0x40010c48u +#define CYREG_B0_P6_U0_CFG9 0x40010c49u +#define CYREG_B0_P6_U0_CFG10 0x40010c4au +#define CYREG_B0_P6_U0_CFG11 0x40010c4bu +#define CYREG_B0_P6_U0_CFG12 0x40010c4cu +#define CYREG_B0_P6_U0_CFG13 0x40010c4du +#define CYREG_B0_P6_U0_CFG14 0x40010c4eu +#define CYREG_B0_P6_U0_CFG15 0x40010c4fu +#define CYREG_B0_P6_U0_CFG16 0x40010c50u +#define CYREG_B0_P6_U0_CFG17 0x40010c51u +#define CYREG_B0_P6_U0_CFG18 0x40010c52u +#define CYREG_B0_P6_U0_CFG19 0x40010c53u +#define CYREG_B0_P6_U0_CFG20 0x40010c54u +#define CYREG_B0_P6_U0_CFG21 0x40010c55u +#define CYREG_B0_P6_U0_CFG22 0x40010c56u +#define CYREG_B0_P6_U0_CFG23 0x40010c57u +#define CYREG_B0_P6_U0_CFG24 0x40010c58u +#define CYREG_B0_P6_U0_CFG25 0x40010c59u +#define CYREG_B0_P6_U0_CFG26 0x40010c5au +#define CYREG_B0_P6_U0_CFG27 0x40010c5bu +#define CYREG_B0_P6_U0_CFG28 0x40010c5cu +#define CYREG_B0_P6_U0_CFG29 0x40010c5du +#define CYREG_B0_P6_U0_CFG30 0x40010c5eu +#define CYREG_B0_P6_U0_CFG31 0x40010c5fu +#define CYREG_B0_P6_U0_DCFG0 0x40010c60u +#define CYREG_B0_P6_U0_DCFG1 0x40010c62u +#define CYREG_B0_P6_U0_DCFG2 0x40010c64u +#define CYREG_B0_P6_U0_DCFG3 0x40010c66u +#define CYREG_B0_P6_U0_DCFG4 0x40010c68u +#define CYREG_B0_P6_U0_DCFG5 0x40010c6au +#define CYREG_B0_P6_U0_DCFG6 0x40010c6cu +#define CYREG_B0_P6_U0_DCFG7 0x40010c6eu +#define CYDEV_UCFG_B0_P6_U1_BASE 0x40010c80u +#define CYDEV_UCFG_B0_P6_U1_SIZE 0x00000070u +#define CYREG_B0_P6_U1_PLD_IT0 0x40010c80u +#define CYREG_B0_P6_U1_PLD_IT1 0x40010c84u +#define CYREG_B0_P6_U1_PLD_IT2 0x40010c88u +#define CYREG_B0_P6_U1_PLD_IT3 0x40010c8cu +#define CYREG_B0_P6_U1_PLD_IT4 0x40010c90u +#define CYREG_B0_P6_U1_PLD_IT5 0x40010c94u +#define CYREG_B0_P6_U1_PLD_IT6 0x40010c98u +#define CYREG_B0_P6_U1_PLD_IT7 0x40010c9cu +#define CYREG_B0_P6_U1_PLD_IT8 0x40010ca0u +#define CYREG_B0_P6_U1_PLD_IT9 0x40010ca4u +#define CYREG_B0_P6_U1_PLD_IT10 0x40010ca8u +#define CYREG_B0_P6_U1_PLD_IT11 0x40010cacu +#define CYREG_B0_P6_U1_PLD_ORT0 0x40010cb0u +#define CYREG_B0_P6_U1_PLD_ORT1 0x40010cb2u +#define CYREG_B0_P6_U1_PLD_ORT2 0x40010cb4u +#define CYREG_B0_P6_U1_PLD_ORT3 0x40010cb6u +#define CYREG_B0_P6_U1_MC_CFG_CEN_CONST 0x40010cb8u +#define CYREG_B0_P6_U1_MC_CFG_XORFB 0x40010cbau +#define CYREG_B0_P6_U1_MC_CFG_SET_RESET 0x40010cbcu +#define CYREG_B0_P6_U1_MC_CFG_BYPASS 0x40010cbeu +#define CYREG_B0_P6_U1_CFG0 0x40010cc0u +#define CYREG_B0_P6_U1_CFG1 0x40010cc1u +#define CYREG_B0_P6_U1_CFG2 0x40010cc2u +#define CYREG_B0_P6_U1_CFG3 0x40010cc3u +#define CYREG_B0_P6_U1_CFG4 0x40010cc4u +#define CYREG_B0_P6_U1_CFG5 0x40010cc5u +#define CYREG_B0_P6_U1_CFG6 0x40010cc6u +#define CYREG_B0_P6_U1_CFG7 0x40010cc7u +#define CYREG_B0_P6_U1_CFG8 0x40010cc8u +#define CYREG_B0_P6_U1_CFG9 0x40010cc9u +#define CYREG_B0_P6_U1_CFG10 0x40010ccau +#define CYREG_B0_P6_U1_CFG11 0x40010ccbu +#define CYREG_B0_P6_U1_CFG12 0x40010cccu +#define CYREG_B0_P6_U1_CFG13 0x40010ccdu +#define CYREG_B0_P6_U1_CFG14 0x40010cceu +#define CYREG_B0_P6_U1_CFG15 0x40010ccfu +#define CYREG_B0_P6_U1_CFG16 0x40010cd0u +#define CYREG_B0_P6_U1_CFG17 0x40010cd1u +#define CYREG_B0_P6_U1_CFG18 0x40010cd2u +#define CYREG_B0_P6_U1_CFG19 0x40010cd3u +#define CYREG_B0_P6_U1_CFG20 0x40010cd4u +#define CYREG_B0_P6_U1_CFG21 0x40010cd5u +#define CYREG_B0_P6_U1_CFG22 0x40010cd6u +#define CYREG_B0_P6_U1_CFG23 0x40010cd7u +#define CYREG_B0_P6_U1_CFG24 0x40010cd8u +#define CYREG_B0_P6_U1_CFG25 0x40010cd9u +#define CYREG_B0_P6_U1_CFG26 0x40010cdau +#define CYREG_B0_P6_U1_CFG27 0x40010cdbu +#define CYREG_B0_P6_U1_CFG28 0x40010cdcu +#define CYREG_B0_P6_U1_CFG29 0x40010cddu +#define CYREG_B0_P6_U1_CFG30 0x40010cdeu +#define CYREG_B0_P6_U1_CFG31 0x40010cdfu +#define CYREG_B0_P6_U1_DCFG0 0x40010ce0u +#define CYREG_B0_P6_U1_DCFG1 0x40010ce2u +#define CYREG_B0_P6_U1_DCFG2 0x40010ce4u +#define CYREG_B0_P6_U1_DCFG3 0x40010ce6u +#define CYREG_B0_P6_U1_DCFG4 0x40010ce8u +#define CYREG_B0_P6_U1_DCFG5 0x40010ceau +#define CYREG_B0_P6_U1_DCFG6 0x40010cecu +#define CYREG_B0_P6_U1_DCFG7 0x40010ceeu +#define CYDEV_UCFG_B0_P6_ROUTE_BASE 0x40010d00u +#define CYDEV_UCFG_B0_P6_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P7_BASE 0x40010e00u +#define CYDEV_UCFG_B0_P7_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P7_U0_BASE 0x40010e00u +#define CYDEV_UCFG_B0_P7_U0_SIZE 0x00000070u +#define CYREG_B0_P7_U0_PLD_IT0 0x40010e00u +#define CYREG_B0_P7_U0_PLD_IT1 0x40010e04u +#define CYREG_B0_P7_U0_PLD_IT2 0x40010e08u +#define CYREG_B0_P7_U0_PLD_IT3 0x40010e0cu +#define CYREG_B0_P7_U0_PLD_IT4 0x40010e10u +#define CYREG_B0_P7_U0_PLD_IT5 0x40010e14u +#define CYREG_B0_P7_U0_PLD_IT6 0x40010e18u +#define CYREG_B0_P7_U0_PLD_IT7 0x40010e1cu +#define CYREG_B0_P7_U0_PLD_IT8 0x40010e20u +#define CYREG_B0_P7_U0_PLD_IT9 0x40010e24u +#define CYREG_B0_P7_U0_PLD_IT10 0x40010e28u +#define CYREG_B0_P7_U0_PLD_IT11 0x40010e2cu +#define CYREG_B0_P7_U0_PLD_ORT0 0x40010e30u +#define CYREG_B0_P7_U0_PLD_ORT1 0x40010e32u +#define CYREG_B0_P7_U0_PLD_ORT2 0x40010e34u +#define CYREG_B0_P7_U0_PLD_ORT3 0x40010e36u +#define CYREG_B0_P7_U0_MC_CFG_CEN_CONST 0x40010e38u +#define CYREG_B0_P7_U0_MC_CFG_XORFB 0x40010e3au +#define CYREG_B0_P7_U0_MC_CFG_SET_RESET 0x40010e3cu +#define CYREG_B0_P7_U0_MC_CFG_BYPASS 0x40010e3eu +#define CYREG_B0_P7_U0_CFG0 0x40010e40u +#define CYREG_B0_P7_U0_CFG1 0x40010e41u +#define CYREG_B0_P7_U0_CFG2 0x40010e42u +#define CYREG_B0_P7_U0_CFG3 0x40010e43u +#define CYREG_B0_P7_U0_CFG4 0x40010e44u +#define CYREG_B0_P7_U0_CFG5 0x40010e45u +#define CYREG_B0_P7_U0_CFG6 0x40010e46u +#define CYREG_B0_P7_U0_CFG7 0x40010e47u +#define CYREG_B0_P7_U0_CFG8 0x40010e48u +#define CYREG_B0_P7_U0_CFG9 0x40010e49u +#define CYREG_B0_P7_U0_CFG10 0x40010e4au +#define CYREG_B0_P7_U0_CFG11 0x40010e4bu +#define CYREG_B0_P7_U0_CFG12 0x40010e4cu +#define CYREG_B0_P7_U0_CFG13 0x40010e4du +#define CYREG_B0_P7_U0_CFG14 0x40010e4eu +#define CYREG_B0_P7_U0_CFG15 0x40010e4fu +#define CYREG_B0_P7_U0_CFG16 0x40010e50u +#define CYREG_B0_P7_U0_CFG17 0x40010e51u +#define CYREG_B0_P7_U0_CFG18 0x40010e52u +#define CYREG_B0_P7_U0_CFG19 0x40010e53u +#define CYREG_B0_P7_U0_CFG20 0x40010e54u +#define CYREG_B0_P7_U0_CFG21 0x40010e55u +#define CYREG_B0_P7_U0_CFG22 0x40010e56u +#define CYREG_B0_P7_U0_CFG23 0x40010e57u +#define CYREG_B0_P7_U0_CFG24 0x40010e58u +#define CYREG_B0_P7_U0_CFG25 0x40010e59u +#define CYREG_B0_P7_U0_CFG26 0x40010e5au +#define CYREG_B0_P7_U0_CFG27 0x40010e5bu +#define CYREG_B0_P7_U0_CFG28 0x40010e5cu +#define CYREG_B0_P7_U0_CFG29 0x40010e5du +#define CYREG_B0_P7_U0_CFG30 0x40010e5eu +#define CYREG_B0_P7_U0_CFG31 0x40010e5fu +#define CYREG_B0_P7_U0_DCFG0 0x40010e60u +#define CYREG_B0_P7_U0_DCFG1 0x40010e62u +#define CYREG_B0_P7_U0_DCFG2 0x40010e64u +#define CYREG_B0_P7_U0_DCFG3 0x40010e66u +#define CYREG_B0_P7_U0_DCFG4 0x40010e68u +#define CYREG_B0_P7_U0_DCFG5 0x40010e6au +#define CYREG_B0_P7_U0_DCFG6 0x40010e6cu +#define CYREG_B0_P7_U0_DCFG7 0x40010e6eu +#define CYDEV_UCFG_B0_P7_U1_BASE 0x40010e80u +#define CYDEV_UCFG_B0_P7_U1_SIZE 0x00000070u +#define CYREG_B0_P7_U1_PLD_IT0 0x40010e80u +#define CYREG_B0_P7_U1_PLD_IT1 0x40010e84u +#define CYREG_B0_P7_U1_PLD_IT2 0x40010e88u +#define CYREG_B0_P7_U1_PLD_IT3 0x40010e8cu +#define CYREG_B0_P7_U1_PLD_IT4 0x40010e90u +#define CYREG_B0_P7_U1_PLD_IT5 0x40010e94u +#define CYREG_B0_P7_U1_PLD_IT6 0x40010e98u +#define CYREG_B0_P7_U1_PLD_IT7 0x40010e9cu +#define CYREG_B0_P7_U1_PLD_IT8 0x40010ea0u +#define CYREG_B0_P7_U1_PLD_IT9 0x40010ea4u +#define CYREG_B0_P7_U1_PLD_IT10 0x40010ea8u +#define CYREG_B0_P7_U1_PLD_IT11 0x40010eacu +#define CYREG_B0_P7_U1_PLD_ORT0 0x40010eb0u +#define CYREG_B0_P7_U1_PLD_ORT1 0x40010eb2u +#define CYREG_B0_P7_U1_PLD_ORT2 0x40010eb4u +#define CYREG_B0_P7_U1_PLD_ORT3 0x40010eb6u +#define CYREG_B0_P7_U1_MC_CFG_CEN_CONST 0x40010eb8u +#define CYREG_B0_P7_U1_MC_CFG_XORFB 0x40010ebau +#define CYREG_B0_P7_U1_MC_CFG_SET_RESET 0x40010ebcu +#define CYREG_B0_P7_U1_MC_CFG_BYPASS 0x40010ebeu +#define CYREG_B0_P7_U1_CFG0 0x40010ec0u +#define CYREG_B0_P7_U1_CFG1 0x40010ec1u +#define CYREG_B0_P7_U1_CFG2 0x40010ec2u +#define CYREG_B0_P7_U1_CFG3 0x40010ec3u +#define CYREG_B0_P7_U1_CFG4 0x40010ec4u +#define CYREG_B0_P7_U1_CFG5 0x40010ec5u +#define CYREG_B0_P7_U1_CFG6 0x40010ec6u +#define CYREG_B0_P7_U1_CFG7 0x40010ec7u +#define CYREG_B0_P7_U1_CFG8 0x40010ec8u +#define CYREG_B0_P7_U1_CFG9 0x40010ec9u +#define CYREG_B0_P7_U1_CFG10 0x40010ecau +#define CYREG_B0_P7_U1_CFG11 0x40010ecbu +#define CYREG_B0_P7_U1_CFG12 0x40010eccu +#define CYREG_B0_P7_U1_CFG13 0x40010ecdu +#define CYREG_B0_P7_U1_CFG14 0x40010eceu +#define CYREG_B0_P7_U1_CFG15 0x40010ecfu +#define CYREG_B0_P7_U1_CFG16 0x40010ed0u +#define CYREG_B0_P7_U1_CFG17 0x40010ed1u +#define CYREG_B0_P7_U1_CFG18 0x40010ed2u +#define CYREG_B0_P7_U1_CFG19 0x40010ed3u +#define CYREG_B0_P7_U1_CFG20 0x40010ed4u +#define CYREG_B0_P7_U1_CFG21 0x40010ed5u +#define CYREG_B0_P7_U1_CFG22 0x40010ed6u +#define CYREG_B0_P7_U1_CFG23 0x40010ed7u +#define CYREG_B0_P7_U1_CFG24 0x40010ed8u +#define CYREG_B0_P7_U1_CFG25 0x40010ed9u +#define CYREG_B0_P7_U1_CFG26 0x40010edau +#define CYREG_B0_P7_U1_CFG27 0x40010edbu +#define CYREG_B0_P7_U1_CFG28 0x40010edcu +#define CYREG_B0_P7_U1_CFG29 0x40010eddu +#define CYREG_B0_P7_U1_CFG30 0x40010edeu +#define CYREG_B0_P7_U1_CFG31 0x40010edfu +#define CYREG_B0_P7_U1_DCFG0 0x40010ee0u +#define CYREG_B0_P7_U1_DCFG1 0x40010ee2u +#define CYREG_B0_P7_U1_DCFG2 0x40010ee4u +#define CYREG_B0_P7_U1_DCFG3 0x40010ee6u +#define CYREG_B0_P7_U1_DCFG4 0x40010ee8u +#define CYREG_B0_P7_U1_DCFG5 0x40010eeau +#define CYREG_B0_P7_U1_DCFG6 0x40010eecu +#define CYREG_B0_P7_U1_DCFG7 0x40010eeeu +#define CYDEV_UCFG_B0_P7_ROUTE_BASE 0x40010f00u +#define CYDEV_UCFG_B0_P7_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_BASE 0x40011000u +#define CYDEV_UCFG_B1_SIZE 0x00000fefu +#define CYDEV_UCFG_B1_P2_BASE 0x40011400u +#define CYDEV_UCFG_B1_P2_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P2_U0_BASE 0x40011400u +#define CYDEV_UCFG_B1_P2_U0_SIZE 0x00000070u +#define CYREG_B1_P2_U0_PLD_IT0 0x40011400u +#define CYREG_B1_P2_U0_PLD_IT1 0x40011404u +#define CYREG_B1_P2_U0_PLD_IT2 0x40011408u +#define CYREG_B1_P2_U0_PLD_IT3 0x4001140cu +#define CYREG_B1_P2_U0_PLD_IT4 0x40011410u +#define CYREG_B1_P2_U0_PLD_IT5 0x40011414u +#define CYREG_B1_P2_U0_PLD_IT6 0x40011418u +#define CYREG_B1_P2_U0_PLD_IT7 0x4001141cu +#define CYREG_B1_P2_U0_PLD_IT8 0x40011420u +#define CYREG_B1_P2_U0_PLD_IT9 0x40011424u +#define CYREG_B1_P2_U0_PLD_IT10 0x40011428u +#define CYREG_B1_P2_U0_PLD_IT11 0x4001142cu +#define CYREG_B1_P2_U0_PLD_ORT0 0x40011430u +#define CYREG_B1_P2_U0_PLD_ORT1 0x40011432u +#define CYREG_B1_P2_U0_PLD_ORT2 0x40011434u +#define CYREG_B1_P2_U0_PLD_ORT3 0x40011436u +#define CYREG_B1_P2_U0_MC_CFG_CEN_CONST 0x40011438u +#define CYREG_B1_P2_U0_MC_CFG_XORFB 0x4001143au +#define CYREG_B1_P2_U0_MC_CFG_SET_RESET 0x4001143cu +#define CYREG_B1_P2_U0_MC_CFG_BYPASS 0x4001143eu +#define CYREG_B1_P2_U0_CFG0 0x40011440u +#define CYREG_B1_P2_U0_CFG1 0x40011441u +#define CYREG_B1_P2_U0_CFG2 0x40011442u +#define CYREG_B1_P2_U0_CFG3 0x40011443u +#define CYREG_B1_P2_U0_CFG4 0x40011444u +#define CYREG_B1_P2_U0_CFG5 0x40011445u +#define CYREG_B1_P2_U0_CFG6 0x40011446u +#define CYREG_B1_P2_U0_CFG7 0x40011447u +#define CYREG_B1_P2_U0_CFG8 0x40011448u +#define CYREG_B1_P2_U0_CFG9 0x40011449u +#define CYREG_B1_P2_U0_CFG10 0x4001144au +#define CYREG_B1_P2_U0_CFG11 0x4001144bu +#define CYREG_B1_P2_U0_CFG12 0x4001144cu +#define CYREG_B1_P2_U0_CFG13 0x4001144du +#define CYREG_B1_P2_U0_CFG14 0x4001144eu +#define CYREG_B1_P2_U0_CFG15 0x4001144fu +#define CYREG_B1_P2_U0_CFG16 0x40011450u +#define CYREG_B1_P2_U0_CFG17 0x40011451u +#define CYREG_B1_P2_U0_CFG18 0x40011452u +#define CYREG_B1_P2_U0_CFG19 0x40011453u +#define CYREG_B1_P2_U0_CFG20 0x40011454u +#define CYREG_B1_P2_U0_CFG21 0x40011455u +#define CYREG_B1_P2_U0_CFG22 0x40011456u +#define CYREG_B1_P2_U0_CFG23 0x40011457u +#define CYREG_B1_P2_U0_CFG24 0x40011458u +#define CYREG_B1_P2_U0_CFG25 0x40011459u +#define CYREG_B1_P2_U0_CFG26 0x4001145au +#define CYREG_B1_P2_U0_CFG27 0x4001145bu +#define CYREG_B1_P2_U0_CFG28 0x4001145cu +#define CYREG_B1_P2_U0_CFG29 0x4001145du +#define CYREG_B1_P2_U0_CFG30 0x4001145eu +#define CYREG_B1_P2_U0_CFG31 0x4001145fu +#define CYREG_B1_P2_U0_DCFG0 0x40011460u +#define CYREG_B1_P2_U0_DCFG1 0x40011462u +#define CYREG_B1_P2_U0_DCFG2 0x40011464u +#define CYREG_B1_P2_U0_DCFG3 0x40011466u +#define CYREG_B1_P2_U0_DCFG4 0x40011468u +#define CYREG_B1_P2_U0_DCFG5 0x4001146au +#define CYREG_B1_P2_U0_DCFG6 0x4001146cu +#define CYREG_B1_P2_U0_DCFG7 0x4001146eu +#define CYDEV_UCFG_B1_P2_U1_BASE 0x40011480u +#define CYDEV_UCFG_B1_P2_U1_SIZE 0x00000070u +#define CYREG_B1_P2_U1_PLD_IT0 0x40011480u +#define CYREG_B1_P2_U1_PLD_IT1 0x40011484u +#define CYREG_B1_P2_U1_PLD_IT2 0x40011488u +#define CYREG_B1_P2_U1_PLD_IT3 0x4001148cu +#define CYREG_B1_P2_U1_PLD_IT4 0x40011490u +#define CYREG_B1_P2_U1_PLD_IT5 0x40011494u +#define CYREG_B1_P2_U1_PLD_IT6 0x40011498u +#define CYREG_B1_P2_U1_PLD_IT7 0x4001149cu +#define CYREG_B1_P2_U1_PLD_IT8 0x400114a0u +#define CYREG_B1_P2_U1_PLD_IT9 0x400114a4u +#define CYREG_B1_P2_U1_PLD_IT10 0x400114a8u +#define CYREG_B1_P2_U1_PLD_IT11 0x400114acu +#define CYREG_B1_P2_U1_PLD_ORT0 0x400114b0u +#define CYREG_B1_P2_U1_PLD_ORT1 0x400114b2u +#define CYREG_B1_P2_U1_PLD_ORT2 0x400114b4u +#define CYREG_B1_P2_U1_PLD_ORT3 0x400114b6u +#define CYREG_B1_P2_U1_MC_CFG_CEN_CONST 0x400114b8u +#define CYREG_B1_P2_U1_MC_CFG_XORFB 0x400114bau +#define CYREG_B1_P2_U1_MC_CFG_SET_RESET 0x400114bcu +#define CYREG_B1_P2_U1_MC_CFG_BYPASS 0x400114beu +#define CYREG_B1_P2_U1_CFG0 0x400114c0u +#define CYREG_B1_P2_U1_CFG1 0x400114c1u +#define CYREG_B1_P2_U1_CFG2 0x400114c2u +#define CYREG_B1_P2_U1_CFG3 0x400114c3u +#define CYREG_B1_P2_U1_CFG4 0x400114c4u +#define CYREG_B1_P2_U1_CFG5 0x400114c5u +#define CYREG_B1_P2_U1_CFG6 0x400114c6u +#define CYREG_B1_P2_U1_CFG7 0x400114c7u +#define CYREG_B1_P2_U1_CFG8 0x400114c8u +#define CYREG_B1_P2_U1_CFG9 0x400114c9u +#define CYREG_B1_P2_U1_CFG10 0x400114cau +#define CYREG_B1_P2_U1_CFG11 0x400114cbu +#define CYREG_B1_P2_U1_CFG12 0x400114ccu +#define CYREG_B1_P2_U1_CFG13 0x400114cdu +#define CYREG_B1_P2_U1_CFG14 0x400114ceu +#define CYREG_B1_P2_U1_CFG15 0x400114cfu +#define CYREG_B1_P2_U1_CFG16 0x400114d0u +#define CYREG_B1_P2_U1_CFG17 0x400114d1u +#define CYREG_B1_P2_U1_CFG18 0x400114d2u +#define CYREG_B1_P2_U1_CFG19 0x400114d3u +#define CYREG_B1_P2_U1_CFG20 0x400114d4u +#define CYREG_B1_P2_U1_CFG21 0x400114d5u +#define CYREG_B1_P2_U1_CFG22 0x400114d6u +#define CYREG_B1_P2_U1_CFG23 0x400114d7u +#define CYREG_B1_P2_U1_CFG24 0x400114d8u +#define CYREG_B1_P2_U1_CFG25 0x400114d9u +#define CYREG_B1_P2_U1_CFG26 0x400114dau +#define CYREG_B1_P2_U1_CFG27 0x400114dbu +#define CYREG_B1_P2_U1_CFG28 0x400114dcu +#define CYREG_B1_P2_U1_CFG29 0x400114ddu +#define CYREG_B1_P2_U1_CFG30 0x400114deu +#define CYREG_B1_P2_U1_CFG31 0x400114dfu +#define CYREG_B1_P2_U1_DCFG0 0x400114e0u +#define CYREG_B1_P2_U1_DCFG1 0x400114e2u +#define CYREG_B1_P2_U1_DCFG2 0x400114e4u +#define CYREG_B1_P2_U1_DCFG3 0x400114e6u +#define CYREG_B1_P2_U1_DCFG4 0x400114e8u +#define CYREG_B1_P2_U1_DCFG5 0x400114eau +#define CYREG_B1_P2_U1_DCFG6 0x400114ecu +#define CYREG_B1_P2_U1_DCFG7 0x400114eeu +#define CYDEV_UCFG_B1_P2_ROUTE_BASE 0x40011500u +#define CYDEV_UCFG_B1_P2_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P3_BASE 0x40011600u +#define CYDEV_UCFG_B1_P3_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P3_U0_BASE 0x40011600u +#define CYDEV_UCFG_B1_P3_U0_SIZE 0x00000070u +#define CYREG_B1_P3_U0_PLD_IT0 0x40011600u +#define CYREG_B1_P3_U0_PLD_IT1 0x40011604u +#define CYREG_B1_P3_U0_PLD_IT2 0x40011608u +#define CYREG_B1_P3_U0_PLD_IT3 0x4001160cu +#define CYREG_B1_P3_U0_PLD_IT4 0x40011610u +#define CYREG_B1_P3_U0_PLD_IT5 0x40011614u +#define CYREG_B1_P3_U0_PLD_IT6 0x40011618u +#define CYREG_B1_P3_U0_PLD_IT7 0x4001161cu +#define CYREG_B1_P3_U0_PLD_IT8 0x40011620u +#define CYREG_B1_P3_U0_PLD_IT9 0x40011624u +#define CYREG_B1_P3_U0_PLD_IT10 0x40011628u +#define CYREG_B1_P3_U0_PLD_IT11 0x4001162cu +#define CYREG_B1_P3_U0_PLD_ORT0 0x40011630u +#define CYREG_B1_P3_U0_PLD_ORT1 0x40011632u +#define CYREG_B1_P3_U0_PLD_ORT2 0x40011634u +#define CYREG_B1_P3_U0_PLD_ORT3 0x40011636u +#define CYREG_B1_P3_U0_MC_CFG_CEN_CONST 0x40011638u +#define CYREG_B1_P3_U0_MC_CFG_XORFB 0x4001163au +#define CYREG_B1_P3_U0_MC_CFG_SET_RESET 0x4001163cu +#define CYREG_B1_P3_U0_MC_CFG_BYPASS 0x4001163eu +#define CYREG_B1_P3_U0_CFG0 0x40011640u +#define CYREG_B1_P3_U0_CFG1 0x40011641u +#define CYREG_B1_P3_U0_CFG2 0x40011642u +#define CYREG_B1_P3_U0_CFG3 0x40011643u +#define CYREG_B1_P3_U0_CFG4 0x40011644u +#define CYREG_B1_P3_U0_CFG5 0x40011645u +#define CYREG_B1_P3_U0_CFG6 0x40011646u +#define CYREG_B1_P3_U0_CFG7 0x40011647u +#define CYREG_B1_P3_U0_CFG8 0x40011648u +#define CYREG_B1_P3_U0_CFG9 0x40011649u +#define CYREG_B1_P3_U0_CFG10 0x4001164au +#define CYREG_B1_P3_U0_CFG11 0x4001164bu +#define CYREG_B1_P3_U0_CFG12 0x4001164cu +#define CYREG_B1_P3_U0_CFG13 0x4001164du +#define CYREG_B1_P3_U0_CFG14 0x4001164eu +#define CYREG_B1_P3_U0_CFG15 0x4001164fu +#define CYREG_B1_P3_U0_CFG16 0x40011650u +#define CYREG_B1_P3_U0_CFG17 0x40011651u +#define CYREG_B1_P3_U0_CFG18 0x40011652u +#define CYREG_B1_P3_U0_CFG19 0x40011653u +#define CYREG_B1_P3_U0_CFG20 0x40011654u +#define CYREG_B1_P3_U0_CFG21 0x40011655u +#define CYREG_B1_P3_U0_CFG22 0x40011656u +#define CYREG_B1_P3_U0_CFG23 0x40011657u +#define CYREG_B1_P3_U0_CFG24 0x40011658u +#define CYREG_B1_P3_U0_CFG25 0x40011659u +#define CYREG_B1_P3_U0_CFG26 0x4001165au +#define CYREG_B1_P3_U0_CFG27 0x4001165bu +#define CYREG_B1_P3_U0_CFG28 0x4001165cu +#define CYREG_B1_P3_U0_CFG29 0x4001165du +#define CYREG_B1_P3_U0_CFG30 0x4001165eu +#define CYREG_B1_P3_U0_CFG31 0x4001165fu +#define CYREG_B1_P3_U0_DCFG0 0x40011660u +#define CYREG_B1_P3_U0_DCFG1 0x40011662u +#define CYREG_B1_P3_U0_DCFG2 0x40011664u +#define CYREG_B1_P3_U0_DCFG3 0x40011666u +#define CYREG_B1_P3_U0_DCFG4 0x40011668u +#define CYREG_B1_P3_U0_DCFG5 0x4001166au +#define CYREG_B1_P3_U0_DCFG6 0x4001166cu +#define CYREG_B1_P3_U0_DCFG7 0x4001166eu +#define CYDEV_UCFG_B1_P3_U1_BASE 0x40011680u +#define CYDEV_UCFG_B1_P3_U1_SIZE 0x00000070u +#define CYREG_B1_P3_U1_PLD_IT0 0x40011680u +#define CYREG_B1_P3_U1_PLD_IT1 0x40011684u +#define CYREG_B1_P3_U1_PLD_IT2 0x40011688u +#define CYREG_B1_P3_U1_PLD_IT3 0x4001168cu +#define CYREG_B1_P3_U1_PLD_IT4 0x40011690u +#define CYREG_B1_P3_U1_PLD_IT5 0x40011694u +#define CYREG_B1_P3_U1_PLD_IT6 0x40011698u +#define CYREG_B1_P3_U1_PLD_IT7 0x4001169cu +#define CYREG_B1_P3_U1_PLD_IT8 0x400116a0u +#define CYREG_B1_P3_U1_PLD_IT9 0x400116a4u +#define CYREG_B1_P3_U1_PLD_IT10 0x400116a8u +#define CYREG_B1_P3_U1_PLD_IT11 0x400116acu +#define CYREG_B1_P3_U1_PLD_ORT0 0x400116b0u +#define CYREG_B1_P3_U1_PLD_ORT1 0x400116b2u +#define CYREG_B1_P3_U1_PLD_ORT2 0x400116b4u +#define CYREG_B1_P3_U1_PLD_ORT3 0x400116b6u +#define CYREG_B1_P3_U1_MC_CFG_CEN_CONST 0x400116b8u +#define CYREG_B1_P3_U1_MC_CFG_XORFB 0x400116bau +#define CYREG_B1_P3_U1_MC_CFG_SET_RESET 0x400116bcu +#define CYREG_B1_P3_U1_MC_CFG_BYPASS 0x400116beu +#define CYREG_B1_P3_U1_CFG0 0x400116c0u +#define CYREG_B1_P3_U1_CFG1 0x400116c1u +#define CYREG_B1_P3_U1_CFG2 0x400116c2u +#define CYREG_B1_P3_U1_CFG3 0x400116c3u +#define CYREG_B1_P3_U1_CFG4 0x400116c4u +#define CYREG_B1_P3_U1_CFG5 0x400116c5u +#define CYREG_B1_P3_U1_CFG6 0x400116c6u +#define CYREG_B1_P3_U1_CFG7 0x400116c7u +#define CYREG_B1_P3_U1_CFG8 0x400116c8u +#define CYREG_B1_P3_U1_CFG9 0x400116c9u +#define CYREG_B1_P3_U1_CFG10 0x400116cau +#define CYREG_B1_P3_U1_CFG11 0x400116cbu +#define CYREG_B1_P3_U1_CFG12 0x400116ccu +#define CYREG_B1_P3_U1_CFG13 0x400116cdu +#define CYREG_B1_P3_U1_CFG14 0x400116ceu +#define CYREG_B1_P3_U1_CFG15 0x400116cfu +#define CYREG_B1_P3_U1_CFG16 0x400116d0u +#define CYREG_B1_P3_U1_CFG17 0x400116d1u +#define CYREG_B1_P3_U1_CFG18 0x400116d2u +#define CYREG_B1_P3_U1_CFG19 0x400116d3u +#define CYREG_B1_P3_U1_CFG20 0x400116d4u +#define CYREG_B1_P3_U1_CFG21 0x400116d5u +#define CYREG_B1_P3_U1_CFG22 0x400116d6u +#define CYREG_B1_P3_U1_CFG23 0x400116d7u +#define CYREG_B1_P3_U1_CFG24 0x400116d8u +#define CYREG_B1_P3_U1_CFG25 0x400116d9u +#define CYREG_B1_P3_U1_CFG26 0x400116dau +#define CYREG_B1_P3_U1_CFG27 0x400116dbu +#define CYREG_B1_P3_U1_CFG28 0x400116dcu +#define CYREG_B1_P3_U1_CFG29 0x400116ddu +#define CYREG_B1_P3_U1_CFG30 0x400116deu +#define CYREG_B1_P3_U1_CFG31 0x400116dfu +#define CYREG_B1_P3_U1_DCFG0 0x400116e0u +#define CYREG_B1_P3_U1_DCFG1 0x400116e2u +#define CYREG_B1_P3_U1_DCFG2 0x400116e4u +#define CYREG_B1_P3_U1_DCFG3 0x400116e6u +#define CYREG_B1_P3_U1_DCFG4 0x400116e8u +#define CYREG_B1_P3_U1_DCFG5 0x400116eau +#define CYREG_B1_P3_U1_DCFG6 0x400116ecu +#define CYREG_B1_P3_U1_DCFG7 0x400116eeu +#define CYDEV_UCFG_B1_P3_ROUTE_BASE 0x40011700u +#define CYDEV_UCFG_B1_P3_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P4_BASE 0x40011800u +#define CYDEV_UCFG_B1_P4_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P4_U0_BASE 0x40011800u +#define CYDEV_UCFG_B1_P4_U0_SIZE 0x00000070u +#define CYREG_B1_P4_U0_PLD_IT0 0x40011800u +#define CYREG_B1_P4_U0_PLD_IT1 0x40011804u +#define CYREG_B1_P4_U0_PLD_IT2 0x40011808u +#define CYREG_B1_P4_U0_PLD_IT3 0x4001180cu +#define CYREG_B1_P4_U0_PLD_IT4 0x40011810u +#define CYREG_B1_P4_U0_PLD_IT5 0x40011814u +#define CYREG_B1_P4_U0_PLD_IT6 0x40011818u +#define CYREG_B1_P4_U0_PLD_IT7 0x4001181cu +#define CYREG_B1_P4_U0_PLD_IT8 0x40011820u +#define CYREG_B1_P4_U0_PLD_IT9 0x40011824u +#define CYREG_B1_P4_U0_PLD_IT10 0x40011828u +#define CYREG_B1_P4_U0_PLD_IT11 0x4001182cu +#define CYREG_B1_P4_U0_PLD_ORT0 0x40011830u +#define CYREG_B1_P4_U0_PLD_ORT1 0x40011832u +#define CYREG_B1_P4_U0_PLD_ORT2 0x40011834u +#define CYREG_B1_P4_U0_PLD_ORT3 0x40011836u +#define CYREG_B1_P4_U0_MC_CFG_CEN_CONST 0x40011838u +#define CYREG_B1_P4_U0_MC_CFG_XORFB 0x4001183au +#define CYREG_B1_P4_U0_MC_CFG_SET_RESET 0x4001183cu +#define CYREG_B1_P4_U0_MC_CFG_BYPASS 0x4001183eu +#define CYREG_B1_P4_U0_CFG0 0x40011840u +#define CYREG_B1_P4_U0_CFG1 0x40011841u +#define CYREG_B1_P4_U0_CFG2 0x40011842u +#define CYREG_B1_P4_U0_CFG3 0x40011843u +#define CYREG_B1_P4_U0_CFG4 0x40011844u +#define CYREG_B1_P4_U0_CFG5 0x40011845u +#define CYREG_B1_P4_U0_CFG6 0x40011846u +#define CYREG_B1_P4_U0_CFG7 0x40011847u +#define CYREG_B1_P4_U0_CFG8 0x40011848u +#define CYREG_B1_P4_U0_CFG9 0x40011849u +#define CYREG_B1_P4_U0_CFG10 0x4001184au +#define CYREG_B1_P4_U0_CFG11 0x4001184bu +#define CYREG_B1_P4_U0_CFG12 0x4001184cu +#define CYREG_B1_P4_U0_CFG13 0x4001184du +#define CYREG_B1_P4_U0_CFG14 0x4001184eu +#define CYREG_B1_P4_U0_CFG15 0x4001184fu +#define CYREG_B1_P4_U0_CFG16 0x40011850u +#define CYREG_B1_P4_U0_CFG17 0x40011851u +#define CYREG_B1_P4_U0_CFG18 0x40011852u +#define CYREG_B1_P4_U0_CFG19 0x40011853u +#define CYREG_B1_P4_U0_CFG20 0x40011854u +#define CYREG_B1_P4_U0_CFG21 0x40011855u +#define CYREG_B1_P4_U0_CFG22 0x40011856u +#define CYREG_B1_P4_U0_CFG23 0x40011857u +#define CYREG_B1_P4_U0_CFG24 0x40011858u +#define CYREG_B1_P4_U0_CFG25 0x40011859u +#define CYREG_B1_P4_U0_CFG26 0x4001185au +#define CYREG_B1_P4_U0_CFG27 0x4001185bu +#define CYREG_B1_P4_U0_CFG28 0x4001185cu +#define CYREG_B1_P4_U0_CFG29 0x4001185du +#define CYREG_B1_P4_U0_CFG30 0x4001185eu +#define CYREG_B1_P4_U0_CFG31 0x4001185fu +#define CYREG_B1_P4_U0_DCFG0 0x40011860u +#define CYREG_B1_P4_U0_DCFG1 0x40011862u +#define CYREG_B1_P4_U0_DCFG2 0x40011864u +#define CYREG_B1_P4_U0_DCFG3 0x40011866u +#define CYREG_B1_P4_U0_DCFG4 0x40011868u +#define CYREG_B1_P4_U0_DCFG5 0x4001186au +#define CYREG_B1_P4_U0_DCFG6 0x4001186cu +#define CYREG_B1_P4_U0_DCFG7 0x4001186eu +#define CYDEV_UCFG_B1_P4_U1_BASE 0x40011880u +#define CYDEV_UCFG_B1_P4_U1_SIZE 0x00000070u +#define CYREG_B1_P4_U1_PLD_IT0 0x40011880u +#define CYREG_B1_P4_U1_PLD_IT1 0x40011884u +#define CYREG_B1_P4_U1_PLD_IT2 0x40011888u +#define CYREG_B1_P4_U1_PLD_IT3 0x4001188cu +#define CYREG_B1_P4_U1_PLD_IT4 0x40011890u +#define CYREG_B1_P4_U1_PLD_IT5 0x40011894u +#define CYREG_B1_P4_U1_PLD_IT6 0x40011898u +#define CYREG_B1_P4_U1_PLD_IT7 0x4001189cu +#define CYREG_B1_P4_U1_PLD_IT8 0x400118a0u +#define CYREG_B1_P4_U1_PLD_IT9 0x400118a4u +#define CYREG_B1_P4_U1_PLD_IT10 0x400118a8u +#define CYREG_B1_P4_U1_PLD_IT11 0x400118acu +#define CYREG_B1_P4_U1_PLD_ORT0 0x400118b0u +#define CYREG_B1_P4_U1_PLD_ORT1 0x400118b2u +#define CYREG_B1_P4_U1_PLD_ORT2 0x400118b4u +#define CYREG_B1_P4_U1_PLD_ORT3 0x400118b6u +#define CYREG_B1_P4_U1_MC_CFG_CEN_CONST 0x400118b8u +#define CYREG_B1_P4_U1_MC_CFG_XORFB 0x400118bau +#define CYREG_B1_P4_U1_MC_CFG_SET_RESET 0x400118bcu +#define CYREG_B1_P4_U1_MC_CFG_BYPASS 0x400118beu +#define CYREG_B1_P4_U1_CFG0 0x400118c0u +#define CYREG_B1_P4_U1_CFG1 0x400118c1u +#define CYREG_B1_P4_U1_CFG2 0x400118c2u +#define CYREG_B1_P4_U1_CFG3 0x400118c3u +#define CYREG_B1_P4_U1_CFG4 0x400118c4u +#define CYREG_B1_P4_U1_CFG5 0x400118c5u +#define CYREG_B1_P4_U1_CFG6 0x400118c6u +#define CYREG_B1_P4_U1_CFG7 0x400118c7u +#define CYREG_B1_P4_U1_CFG8 0x400118c8u +#define CYREG_B1_P4_U1_CFG9 0x400118c9u +#define CYREG_B1_P4_U1_CFG10 0x400118cau +#define CYREG_B1_P4_U1_CFG11 0x400118cbu +#define CYREG_B1_P4_U1_CFG12 0x400118ccu +#define CYREG_B1_P4_U1_CFG13 0x400118cdu +#define CYREG_B1_P4_U1_CFG14 0x400118ceu +#define CYREG_B1_P4_U1_CFG15 0x400118cfu +#define CYREG_B1_P4_U1_CFG16 0x400118d0u +#define CYREG_B1_P4_U1_CFG17 0x400118d1u +#define CYREG_B1_P4_U1_CFG18 0x400118d2u +#define CYREG_B1_P4_U1_CFG19 0x400118d3u +#define CYREG_B1_P4_U1_CFG20 0x400118d4u +#define CYREG_B1_P4_U1_CFG21 0x400118d5u +#define CYREG_B1_P4_U1_CFG22 0x400118d6u +#define CYREG_B1_P4_U1_CFG23 0x400118d7u +#define CYREG_B1_P4_U1_CFG24 0x400118d8u +#define CYREG_B1_P4_U1_CFG25 0x400118d9u +#define CYREG_B1_P4_U1_CFG26 0x400118dau +#define CYREG_B1_P4_U1_CFG27 0x400118dbu +#define CYREG_B1_P4_U1_CFG28 0x400118dcu +#define CYREG_B1_P4_U1_CFG29 0x400118ddu +#define CYREG_B1_P4_U1_CFG30 0x400118deu +#define CYREG_B1_P4_U1_CFG31 0x400118dfu +#define CYREG_B1_P4_U1_DCFG0 0x400118e0u +#define CYREG_B1_P4_U1_DCFG1 0x400118e2u +#define CYREG_B1_P4_U1_DCFG2 0x400118e4u +#define CYREG_B1_P4_U1_DCFG3 0x400118e6u +#define CYREG_B1_P4_U1_DCFG4 0x400118e8u +#define CYREG_B1_P4_U1_DCFG5 0x400118eau +#define CYREG_B1_P4_U1_DCFG6 0x400118ecu +#define CYREG_B1_P4_U1_DCFG7 0x400118eeu +#define CYDEV_UCFG_B1_P4_ROUTE_BASE 0x40011900u +#define CYDEV_UCFG_B1_P4_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P5_BASE 0x40011a00u +#define CYDEV_UCFG_B1_P5_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P5_U0_BASE 0x40011a00u +#define CYDEV_UCFG_B1_P5_U0_SIZE 0x00000070u +#define CYREG_B1_P5_U0_PLD_IT0 0x40011a00u +#define CYREG_B1_P5_U0_PLD_IT1 0x40011a04u +#define CYREG_B1_P5_U0_PLD_IT2 0x40011a08u +#define CYREG_B1_P5_U0_PLD_IT3 0x40011a0cu +#define CYREG_B1_P5_U0_PLD_IT4 0x40011a10u +#define CYREG_B1_P5_U0_PLD_IT5 0x40011a14u +#define CYREG_B1_P5_U0_PLD_IT6 0x40011a18u +#define CYREG_B1_P5_U0_PLD_IT7 0x40011a1cu +#define CYREG_B1_P5_U0_PLD_IT8 0x40011a20u +#define CYREG_B1_P5_U0_PLD_IT9 0x40011a24u +#define CYREG_B1_P5_U0_PLD_IT10 0x40011a28u +#define CYREG_B1_P5_U0_PLD_IT11 0x40011a2cu +#define CYREG_B1_P5_U0_PLD_ORT0 0x40011a30u +#define CYREG_B1_P5_U0_PLD_ORT1 0x40011a32u +#define CYREG_B1_P5_U0_PLD_ORT2 0x40011a34u +#define CYREG_B1_P5_U0_PLD_ORT3 0x40011a36u +#define CYREG_B1_P5_U0_MC_CFG_CEN_CONST 0x40011a38u +#define CYREG_B1_P5_U0_MC_CFG_XORFB 0x40011a3au +#define CYREG_B1_P5_U0_MC_CFG_SET_RESET 0x40011a3cu +#define CYREG_B1_P5_U0_MC_CFG_BYPASS 0x40011a3eu +#define CYREG_B1_P5_U0_CFG0 0x40011a40u +#define CYREG_B1_P5_U0_CFG1 0x40011a41u +#define CYREG_B1_P5_U0_CFG2 0x40011a42u +#define CYREG_B1_P5_U0_CFG3 0x40011a43u +#define CYREG_B1_P5_U0_CFG4 0x40011a44u +#define CYREG_B1_P5_U0_CFG5 0x40011a45u +#define CYREG_B1_P5_U0_CFG6 0x40011a46u +#define CYREG_B1_P5_U0_CFG7 0x40011a47u +#define CYREG_B1_P5_U0_CFG8 0x40011a48u +#define CYREG_B1_P5_U0_CFG9 0x40011a49u +#define CYREG_B1_P5_U0_CFG10 0x40011a4au +#define CYREG_B1_P5_U0_CFG11 0x40011a4bu +#define CYREG_B1_P5_U0_CFG12 0x40011a4cu +#define CYREG_B1_P5_U0_CFG13 0x40011a4du +#define CYREG_B1_P5_U0_CFG14 0x40011a4eu +#define CYREG_B1_P5_U0_CFG15 0x40011a4fu +#define CYREG_B1_P5_U0_CFG16 0x40011a50u +#define CYREG_B1_P5_U0_CFG17 0x40011a51u +#define CYREG_B1_P5_U0_CFG18 0x40011a52u +#define CYREG_B1_P5_U0_CFG19 0x40011a53u +#define CYREG_B1_P5_U0_CFG20 0x40011a54u +#define CYREG_B1_P5_U0_CFG21 0x40011a55u +#define CYREG_B1_P5_U0_CFG22 0x40011a56u +#define CYREG_B1_P5_U0_CFG23 0x40011a57u +#define CYREG_B1_P5_U0_CFG24 0x40011a58u +#define CYREG_B1_P5_U0_CFG25 0x40011a59u +#define CYREG_B1_P5_U0_CFG26 0x40011a5au +#define CYREG_B1_P5_U0_CFG27 0x40011a5bu +#define CYREG_B1_P5_U0_CFG28 0x40011a5cu +#define CYREG_B1_P5_U0_CFG29 0x40011a5du +#define CYREG_B1_P5_U0_CFG30 0x40011a5eu +#define CYREG_B1_P5_U0_CFG31 0x40011a5fu +#define CYREG_B1_P5_U0_DCFG0 0x40011a60u +#define CYREG_B1_P5_U0_DCFG1 0x40011a62u +#define CYREG_B1_P5_U0_DCFG2 0x40011a64u +#define CYREG_B1_P5_U0_DCFG3 0x40011a66u +#define CYREG_B1_P5_U0_DCFG4 0x40011a68u +#define CYREG_B1_P5_U0_DCFG5 0x40011a6au +#define CYREG_B1_P5_U0_DCFG6 0x40011a6cu +#define CYREG_B1_P5_U0_DCFG7 0x40011a6eu +#define CYDEV_UCFG_B1_P5_U1_BASE 0x40011a80u +#define CYDEV_UCFG_B1_P5_U1_SIZE 0x00000070u +#define CYREG_B1_P5_U1_PLD_IT0 0x40011a80u +#define CYREG_B1_P5_U1_PLD_IT1 0x40011a84u +#define CYREG_B1_P5_U1_PLD_IT2 0x40011a88u +#define CYREG_B1_P5_U1_PLD_IT3 0x40011a8cu +#define CYREG_B1_P5_U1_PLD_IT4 0x40011a90u +#define CYREG_B1_P5_U1_PLD_IT5 0x40011a94u +#define CYREG_B1_P5_U1_PLD_IT6 0x40011a98u +#define CYREG_B1_P5_U1_PLD_IT7 0x40011a9cu +#define CYREG_B1_P5_U1_PLD_IT8 0x40011aa0u +#define CYREG_B1_P5_U1_PLD_IT9 0x40011aa4u +#define CYREG_B1_P5_U1_PLD_IT10 0x40011aa8u +#define CYREG_B1_P5_U1_PLD_IT11 0x40011aacu +#define CYREG_B1_P5_U1_PLD_ORT0 0x40011ab0u +#define CYREG_B1_P5_U1_PLD_ORT1 0x40011ab2u +#define CYREG_B1_P5_U1_PLD_ORT2 0x40011ab4u +#define CYREG_B1_P5_U1_PLD_ORT3 0x40011ab6u +#define CYREG_B1_P5_U1_MC_CFG_CEN_CONST 0x40011ab8u +#define CYREG_B1_P5_U1_MC_CFG_XORFB 0x40011abau +#define CYREG_B1_P5_U1_MC_CFG_SET_RESET 0x40011abcu +#define CYREG_B1_P5_U1_MC_CFG_BYPASS 0x40011abeu +#define CYREG_B1_P5_U1_CFG0 0x40011ac0u +#define CYREG_B1_P5_U1_CFG1 0x40011ac1u +#define CYREG_B1_P5_U1_CFG2 0x40011ac2u +#define CYREG_B1_P5_U1_CFG3 0x40011ac3u +#define CYREG_B1_P5_U1_CFG4 0x40011ac4u +#define CYREG_B1_P5_U1_CFG5 0x40011ac5u +#define CYREG_B1_P5_U1_CFG6 0x40011ac6u +#define CYREG_B1_P5_U1_CFG7 0x40011ac7u +#define CYREG_B1_P5_U1_CFG8 0x40011ac8u +#define CYREG_B1_P5_U1_CFG9 0x40011ac9u +#define CYREG_B1_P5_U1_CFG10 0x40011acau +#define CYREG_B1_P5_U1_CFG11 0x40011acbu +#define CYREG_B1_P5_U1_CFG12 0x40011accu +#define CYREG_B1_P5_U1_CFG13 0x40011acdu +#define CYREG_B1_P5_U1_CFG14 0x40011aceu +#define CYREG_B1_P5_U1_CFG15 0x40011acfu +#define CYREG_B1_P5_U1_CFG16 0x40011ad0u +#define CYREG_B1_P5_U1_CFG17 0x40011ad1u +#define CYREG_B1_P5_U1_CFG18 0x40011ad2u +#define CYREG_B1_P5_U1_CFG19 0x40011ad3u +#define CYREG_B1_P5_U1_CFG20 0x40011ad4u +#define CYREG_B1_P5_U1_CFG21 0x40011ad5u +#define CYREG_B1_P5_U1_CFG22 0x40011ad6u +#define CYREG_B1_P5_U1_CFG23 0x40011ad7u +#define CYREG_B1_P5_U1_CFG24 0x40011ad8u +#define CYREG_B1_P5_U1_CFG25 0x40011ad9u +#define CYREG_B1_P5_U1_CFG26 0x40011adau +#define CYREG_B1_P5_U1_CFG27 0x40011adbu +#define CYREG_B1_P5_U1_CFG28 0x40011adcu +#define CYREG_B1_P5_U1_CFG29 0x40011addu +#define CYREG_B1_P5_U1_CFG30 0x40011adeu +#define CYREG_B1_P5_U1_CFG31 0x40011adfu +#define CYREG_B1_P5_U1_DCFG0 0x40011ae0u +#define CYREG_B1_P5_U1_DCFG1 0x40011ae2u +#define CYREG_B1_P5_U1_DCFG2 0x40011ae4u +#define CYREG_B1_P5_U1_DCFG3 0x40011ae6u +#define CYREG_B1_P5_U1_DCFG4 0x40011ae8u +#define CYREG_B1_P5_U1_DCFG5 0x40011aeau +#define CYREG_B1_P5_U1_DCFG6 0x40011aecu +#define CYREG_B1_P5_U1_DCFG7 0x40011aeeu +#define CYDEV_UCFG_B1_P5_ROUTE_BASE 0x40011b00u +#define CYDEV_UCFG_B1_P5_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_DSI0_BASE 0x40014000u +#define CYDEV_UCFG_DSI0_SIZE 0x000000efu +#define CYDEV_UCFG_DSI1_BASE 0x40014100u +#define CYDEV_UCFG_DSI1_SIZE 0x000000efu +#define CYDEV_UCFG_DSI2_BASE 0x40014200u +#define CYDEV_UCFG_DSI2_SIZE 0x000000efu +#define CYDEV_UCFG_DSI3_BASE 0x40014300u +#define CYDEV_UCFG_DSI3_SIZE 0x000000efu +#define CYDEV_UCFG_DSI4_BASE 0x40014400u +#define CYDEV_UCFG_DSI4_SIZE 0x000000efu +#define CYDEV_UCFG_DSI5_BASE 0x40014500u +#define CYDEV_UCFG_DSI5_SIZE 0x000000efu +#define CYDEV_UCFG_DSI6_BASE 0x40014600u +#define CYDEV_UCFG_DSI6_SIZE 0x000000efu +#define CYDEV_UCFG_DSI7_BASE 0x40014700u +#define CYDEV_UCFG_DSI7_SIZE 0x000000efu +#define CYDEV_UCFG_DSI8_BASE 0x40014800u +#define CYDEV_UCFG_DSI8_SIZE 0x000000efu +#define CYDEV_UCFG_DSI9_BASE 0x40014900u +#define CYDEV_UCFG_DSI9_SIZE 0x000000efu +#define CYDEV_UCFG_DSI12_BASE 0x40014c00u +#define CYDEV_UCFG_DSI12_SIZE 0x000000efu +#define CYDEV_UCFG_DSI13_BASE 0x40014d00u +#define CYDEV_UCFG_DSI13_SIZE 0x000000efu +#define CYDEV_UCFG_BCTL0_BASE 0x40015000u +#define CYDEV_UCFG_BCTL0_SIZE 0x00000010u +#define CYREG_BCTL0_MDCLK_EN 0x40015000u +#define CYREG_BCTL0_MBCLK_EN 0x40015001u +#define CYREG_BCTL0_WAIT_CFG 0x40015002u +#define CYREG_BCTL0_BANK_CTL 0x40015003u +#define CYREG_BCTL0_UDB_TEST_3 0x40015007u +#define CYREG_BCTL0_DCLK_EN0 0x40015008u +#define CYREG_BCTL0_BCLK_EN0 0x40015009u +#define CYREG_BCTL0_DCLK_EN1 0x4001500au +#define CYREG_BCTL0_BCLK_EN1 0x4001500bu +#define CYREG_BCTL0_DCLK_EN2 0x4001500cu +#define CYREG_BCTL0_BCLK_EN2 0x4001500du +#define CYREG_BCTL0_DCLK_EN3 0x4001500eu +#define CYREG_BCTL0_BCLK_EN3 0x4001500fu +#define CYDEV_UCFG_BCTL1_BASE 0x40015010u +#define CYDEV_UCFG_BCTL1_SIZE 0x00000010u +#define CYREG_BCTL1_MDCLK_EN 0x40015010u +#define CYREG_BCTL1_MBCLK_EN 0x40015011u +#define CYREG_BCTL1_WAIT_CFG 0x40015012u +#define CYREG_BCTL1_BANK_CTL 0x40015013u +#define CYREG_BCTL1_UDB_TEST_3 0x40015017u +#define CYREG_BCTL1_DCLK_EN0 0x40015018u +#define CYREG_BCTL1_BCLK_EN0 0x40015019u +#define CYREG_BCTL1_DCLK_EN1 0x4001501au +#define CYREG_BCTL1_BCLK_EN1 0x4001501bu +#define CYREG_BCTL1_DCLK_EN2 0x4001501cu +#define CYREG_BCTL1_BCLK_EN2 0x4001501du +#define CYREG_BCTL1_DCLK_EN3 0x4001501eu +#define CYREG_BCTL1_BCLK_EN3 0x4001501fu +#define CYDEV_IDMUX_BASE 0x40015100u +#define CYDEV_IDMUX_SIZE 0x00000016u +#define CYREG_IDMUX_IRQ_CTL0 0x40015100u +#define CYREG_IDMUX_IRQ_CTL1 0x40015101u +#define CYREG_IDMUX_IRQ_CTL2 0x40015102u +#define CYREG_IDMUX_IRQ_CTL3 0x40015103u +#define CYREG_IDMUX_IRQ_CTL4 0x40015104u +#define CYREG_IDMUX_IRQ_CTL5 0x40015105u +#define CYREG_IDMUX_IRQ_CTL6 0x40015106u +#define CYREG_IDMUX_IRQ_CTL7 0x40015107u +#define CYREG_IDMUX_DRQ_CTL0 0x40015110u +#define CYREG_IDMUX_DRQ_CTL1 0x40015111u +#define CYREG_IDMUX_DRQ_CTL2 0x40015112u +#define CYREG_IDMUX_DRQ_CTL3 0x40015113u +#define CYREG_IDMUX_DRQ_CTL4 0x40015114u +#define CYREG_IDMUX_DRQ_CTL5 0x40015115u +#define CYDEV_CACHERAM_BASE 0x40030000u +#define CYDEV_CACHERAM_SIZE 0x00000400u +#define CYREG_CACHERAM_DATA_MBASE 0x40030000u +#define CYREG_CACHERAM_DATA_MSIZE 0x00000400u +#define CYDEV_SFR_BASE 0x40050100u +#define CYDEV_SFR_SIZE 0x000000fbu +#define CYREG_SFR_GPIO0 0x40050180u +#define CYREG_SFR_GPIRD0 0x40050189u +#define CYREG_SFR_GPIO0_SEL 0x4005018au +#define CYREG_SFR_GPIO1 0x40050190u +#define CYREG_SFR_GPIRD1 0x40050191u +#define CYREG_SFR_GPIO2 0x40050198u +#define CYREG_SFR_GPIRD2 0x40050199u +#define CYREG_SFR_GPIO2_SEL 0x4005019au +#define CYREG_SFR_GPIO1_SEL 0x400501a2u +#define CYREG_SFR_GPIO3 0x400501b0u +#define CYREG_SFR_GPIRD3 0x400501b1u +#define CYREG_SFR_GPIO3_SEL 0x400501b2u +#define CYREG_SFR_GPIO4 0x400501c0u +#define CYREG_SFR_GPIRD4 0x400501c1u +#define CYREG_SFR_GPIO4_SEL 0x400501c2u +#define CYREG_SFR_GPIO5 0x400501c8u +#define CYREG_SFR_GPIRD5 0x400501c9u +#define CYREG_SFR_GPIO5_SEL 0x400501cau +#define CYREG_SFR_GPIO6 0x400501d8u +#define CYREG_SFR_GPIRD6 0x400501d9u +#define CYREG_SFR_GPIO6_SEL 0x400501dau +#define CYREG_SFR_GPIO12 0x400501e8u +#define CYREG_SFR_GPIRD12 0x400501e9u +#define CYREG_SFR_GPIO12_SEL 0x400501f2u +#define CYREG_SFR_GPIO15 0x400501f8u +#define CYREG_SFR_GPIRD15 0x400501f9u +#define CYREG_SFR_GPIO15_SEL 0x400501fau +#define CYDEV_P3BA_BASE 0x40050300u +#define CYDEV_P3BA_SIZE 0x0000002bu +#define CYREG_P3BA_Y_START 0x40050300u +#define CYREG_P3BA_YROLL 0x40050301u +#define CYREG_P3BA_YCFG 0x40050302u +#define CYREG_P3BA_X_START1 0x40050303u +#define CYREG_P3BA_X_START2 0x40050304u +#define CYREG_P3BA_XROLL1 0x40050305u +#define CYREG_P3BA_XROLL2 0x40050306u +#define CYREG_P3BA_XINC 0x40050307u +#define CYREG_P3BA_XCFG 0x40050308u +#define CYREG_P3BA_OFFSETADDR1 0x40050309u +#define CYREG_P3BA_OFFSETADDR2 0x4005030au +#define CYREG_P3BA_OFFSETADDR3 0x4005030bu +#define CYREG_P3BA_ABSADDR1 0x4005030cu +#define CYREG_P3BA_ABSADDR2 0x4005030du +#define CYREG_P3BA_ABSADDR3 0x4005030eu +#define CYREG_P3BA_ABSADDR4 0x4005030fu +#define CYREG_P3BA_DATCFG1 0x40050310u +#define CYREG_P3BA_DATCFG2 0x40050311u +#define CYREG_P3BA_CMP_RSLT1 0x40050314u +#define CYREG_P3BA_CMP_RSLT2 0x40050315u +#define CYREG_P3BA_CMP_RSLT3 0x40050316u +#define CYREG_P3BA_CMP_RSLT4 0x40050317u +#define CYREG_P3BA_DATA_REG1 0x40050318u +#define CYREG_P3BA_DATA_REG2 0x40050319u +#define CYREG_P3BA_DATA_REG3 0x4005031au +#define CYREG_P3BA_DATA_REG4 0x4005031bu +#define CYREG_P3BA_EXP_DATA1 0x4005031cu +#define CYREG_P3BA_EXP_DATA2 0x4005031du +#define CYREG_P3BA_EXP_DATA3 0x4005031eu +#define CYREG_P3BA_EXP_DATA4 0x4005031fu +#define CYREG_P3BA_MSTR_HRDATA1 0x40050320u +#define CYREG_P3BA_MSTR_HRDATA2 0x40050321u +#define CYREG_P3BA_MSTR_HRDATA3 0x40050322u +#define CYREG_P3BA_MSTR_HRDATA4 0x40050323u +#define CYREG_P3BA_BIST_EN 0x40050324u +#define CYREG_P3BA_PHUB_MASTER_SSR 0x40050325u +#define CYREG_P3BA_SEQCFG1 0x40050326u +#define CYREG_P3BA_SEQCFG2 0x40050327u +#define CYREG_P3BA_Y_CURR 0x40050328u +#define CYREG_P3BA_X_CURR1 0x40050329u +#define CYREG_P3BA_X_CURR2 0x4005032au +#define CYDEV_PANTHER_BASE 0x40080000u +#define CYDEV_PANTHER_SIZE 0x00000020u +#define CYREG_PANTHER_STCALIB_CFG 0x40080000u +#define CYREG_PANTHER_WAITPIPE 0x40080004u +#define CYREG_PANTHER_TRACE_CFG 0x40080008u +#define CYREG_PANTHER_DBG_CFG 0x4008000cu +#define CYREG_PANTHER_CM3_LCKRST_STAT 0x40080018u +#define CYREG_PANTHER_DEVICE_ID 0x4008001cu +#define CYDEV_FLSECC_BASE 0x48000000u +#define CYDEV_FLSECC_SIZE 0x00008000u +#define CYREG_FLSECC_DATA_MBASE 0x48000000u +#define CYREG_FLSECC_DATA_MSIZE 0x00008000u +#define CYDEV_FLSHID_BASE 0x49000000u +#define CYDEV_FLSHID_SIZE 0x00000200u +#define CYREG_FLSHID_RSVD_MBASE 0x49000000u +#define CYREG_FLSHID_RSVD_MSIZE 0x00000080u +#define CYREG_FLSHID_CUST_MDATA_MBASE 0x49000080u +#define CYREG_FLSHID_CUST_MDATA_MSIZE 0x00000080u +#define CYDEV_FLSHID_CUST_TABLES_BASE 0x49000100u +#define CYDEV_FLSHID_CUST_TABLES_SIZE 0x00000040u +#define CYREG_FLSHID_CUST_TABLES_Y_LOC 0x49000100u +#define CYREG_FLSHID_CUST_TABLES_X_LOC 0x49000101u +#define CYREG_FLSHID_CUST_TABLES_WAFER_NUM 0x49000102u +#define CYREG_FLSHID_CUST_TABLES_LOT_LSB 0x49000103u +#define CYREG_FLSHID_CUST_TABLES_LOT_MSB 0x49000104u +#define CYREG_FLSHID_CUST_TABLES_WRK_WK 0x49000105u +#define CYREG_FLSHID_CUST_TABLES_FAB_YR 0x49000106u +#define CYREG_FLSHID_CUST_TABLES_MINOR 0x49000107u +#define CYREG_FLSHID_CUST_TABLES_IMO_3MHZ 0x49000108u +#define CYREG_FLSHID_CUST_TABLES_IMO_6MHZ 0x49000109u +#define CYREG_FLSHID_CUST_TABLES_IMO_12MHZ 0x4900010au +#define CYREG_FLSHID_CUST_TABLES_IMO_24MHZ 0x4900010bu +#define CYREG_FLSHID_CUST_TABLES_IMO_67MHZ 0x4900010cu +#define CYREG_FLSHID_CUST_TABLES_IMO_80MHZ 0x4900010du +#define CYREG_FLSHID_CUST_TABLES_IMO_92MHZ 0x4900010eu +#define CYREG_FLSHID_CUST_TABLES_IMO_USB 0x4900010fu +#define CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS 0x49000110u +#define CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS 0x49000111u +#define CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS 0x49000112u +#define CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS 0x49000113u +#define CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS 0x49000114u +#define CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS 0x49000115u +#define CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS 0x49000116u +#define CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS 0x49000117u +#define CYREG_FLSHID_CUST_TABLES_DEC_M1 0x49000118u +#define CYREG_FLSHID_CUST_TABLES_DEC_M2 0x49000119u +#define CYREG_FLSHID_CUST_TABLES_DEC_M3 0x4900011au +#define CYREG_FLSHID_CUST_TABLES_DEC_M4 0x4900011bu +#define CYREG_FLSHID_CUST_TABLES_DEC_M5 0x4900011cu +#define CYREG_FLSHID_CUST_TABLES_DEC_M6 0x4900011du +#define CYREG_FLSHID_CUST_TABLES_DEC_M7 0x4900011eu +#define CYREG_FLSHID_CUST_TABLES_DEC_M8 0x4900011fu +#define CYREG_FLSHID_CUST_TABLES_DAC0_M1 0x49000120u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M2 0x49000121u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M3 0x49000122u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M4 0x49000123u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M5 0x49000124u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M6 0x49000125u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M7 0x49000126u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M8 0x49000127u +#define CYREG_FLSHID_CUST_TABLES_DAC2_M1 0x49000128u +#define CYREG_FLSHID_CUST_TABLES_DAC2_M2 0x49000129u +#define CYREG_FLSHID_CUST_TABLES_DAC2_M3 0x4900012au +#define CYREG_FLSHID_CUST_TABLES_DAC2_M4 0x4900012bu +#define CYREG_FLSHID_CUST_TABLES_DAC2_M5 0x4900012cu +#define CYREG_FLSHID_CUST_TABLES_DAC2_M6 0x4900012du +#define CYREG_FLSHID_CUST_TABLES_DAC2_M7 0x4900012eu +#define CYREG_FLSHID_CUST_TABLES_DAC2_M8 0x4900012fu +#define CYREG_FLSHID_CUST_TABLES_DAC1_M1 0x49000130u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M2 0x49000131u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M3 0x49000132u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M4 0x49000133u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M5 0x49000134u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M6 0x49000135u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M7 0x49000136u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M8 0x49000137u +#define CYREG_FLSHID_CUST_TABLES_DAC3_M1 0x49000138u +#define CYREG_FLSHID_CUST_TABLES_DAC3_M2 0x49000139u +#define CYREG_FLSHID_CUST_TABLES_DAC3_M3 0x4900013au +#define CYREG_FLSHID_CUST_TABLES_DAC3_M4 0x4900013bu +#define CYREG_FLSHID_CUST_TABLES_DAC3_M5 0x4900013cu +#define CYREG_FLSHID_CUST_TABLES_DAC3_M6 0x4900013du +#define CYREG_FLSHID_CUST_TABLES_DAC3_M7 0x4900013eu +#define CYREG_FLSHID_CUST_TABLES_DAC3_M8 0x4900013fu +#define CYDEV_FLSHID_MFG_CFG_BASE 0x49000180u +#define CYDEV_FLSHID_MFG_CFG_SIZE 0x00000080u +#define CYREG_FLSHID_MFG_CFG_IMO_TR1 0x49000188u +#define CYREG_FLSHID_MFG_CFG_CMP0_TR0 0x490001acu +#define CYREG_FLSHID_MFG_CFG_CMP1_TR0 0x490001aeu +#define CYREG_FLSHID_MFG_CFG_CMP2_TR0 0x490001b0u +#define CYREG_FLSHID_MFG_CFG_CMP3_TR0 0x490001b2u +#define CYREG_FLSHID_MFG_CFG_CMP0_TR1 0x490001b4u +#define CYREG_FLSHID_MFG_CFG_CMP1_TR1 0x490001b6u +#define CYREG_FLSHID_MFG_CFG_CMP2_TR1 0x490001b8u +#define CYREG_FLSHID_MFG_CFG_CMP3_TR1 0x490001bau +#define CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM 0x490001ceu +#define CYDEV_EXTMEM_BASE 0x60000000u +#define CYDEV_EXTMEM_SIZE 0x00800000u +#define CYREG_EXTMEM_DATA_MBASE 0x60000000u +#define CYREG_EXTMEM_DATA_MSIZE 0x00800000u +#define CYDEV_ITM_BASE 0xe0000000u +#define CYDEV_ITM_SIZE 0x00001000u +#define CYREG_ITM_TRACE_EN 0xe0000e00u +#define CYREG_ITM_TRACE_PRIVILEGE 0xe0000e40u +#define CYREG_ITM_TRACE_CTRL 0xe0000e80u +#define CYREG_ITM_LOCK_ACCESS 0xe0000fb0u +#define CYREG_ITM_LOCK_STATUS 0xe0000fb4u +#define CYREG_ITM_PID4 0xe0000fd0u +#define CYREG_ITM_PID5 0xe0000fd4u +#define CYREG_ITM_PID6 0xe0000fd8u +#define CYREG_ITM_PID7 0xe0000fdcu +#define CYREG_ITM_PID0 0xe0000fe0u +#define CYREG_ITM_PID1 0xe0000fe4u +#define CYREG_ITM_PID2 0xe0000fe8u +#define CYREG_ITM_PID3 0xe0000fecu +#define CYREG_ITM_CID0 0xe0000ff0u +#define CYREG_ITM_CID1 0xe0000ff4u +#define CYREG_ITM_CID2 0xe0000ff8u +#define CYREG_ITM_CID3 0xe0000ffcu +#define CYDEV_DWT_BASE 0xe0001000u +#define CYDEV_DWT_SIZE 0x0000005cu +#define CYREG_DWT_CTRL 0xe0001000u +#define CYREG_DWT_CYCLE_COUNT 0xe0001004u +#define CYREG_DWT_CPI_COUNT 0xe0001008u +#define CYREG_DWT_EXC_OVHD_COUNT 0xe000100cu +#define CYREG_DWT_SLEEP_COUNT 0xe0001010u +#define CYREG_DWT_LSU_COUNT 0xe0001014u +#define CYREG_DWT_FOLD_COUNT 0xe0001018u +#define CYREG_DWT_PC_SAMPLE 0xe000101cu +#define CYREG_DWT_COMP_0 0xe0001020u +#define CYREG_DWT_MASK_0 0xe0001024u +#define CYREG_DWT_FUNCTION_0 0xe0001028u +#define CYREG_DWT_COMP_1 0xe0001030u +#define CYREG_DWT_MASK_1 0xe0001034u +#define CYREG_DWT_FUNCTION_1 0xe0001038u +#define CYREG_DWT_COMP_2 0xe0001040u +#define CYREG_DWT_MASK_2 0xe0001044u +#define CYREG_DWT_FUNCTION_2 0xe0001048u +#define CYREG_DWT_COMP_3 0xe0001050u +#define CYREG_DWT_MASK_3 0xe0001054u +#define CYREG_DWT_FUNCTION_3 0xe0001058u +#define CYDEV_FPB_BASE 0xe0002000u +#define CYDEV_FPB_SIZE 0x00001000u +#define CYREG_FPB_CTRL 0xe0002000u +#define CYREG_FPB_REMAP 0xe0002004u +#define CYREG_FPB_FP_COMP_0 0xe0002008u +#define CYREG_FPB_FP_COMP_1 0xe000200cu +#define CYREG_FPB_FP_COMP_2 0xe0002010u +#define CYREG_FPB_FP_COMP_3 0xe0002014u +#define CYREG_FPB_FP_COMP_4 0xe0002018u +#define CYREG_FPB_FP_COMP_5 0xe000201cu +#define CYREG_FPB_FP_COMP_6 0xe0002020u +#define CYREG_FPB_FP_COMP_7 0xe0002024u +#define CYREG_FPB_PID4 0xe0002fd0u +#define CYREG_FPB_PID5 0xe0002fd4u +#define CYREG_FPB_PID6 0xe0002fd8u +#define CYREG_FPB_PID7 0xe0002fdcu +#define CYREG_FPB_PID0 0xe0002fe0u +#define CYREG_FPB_PID1 0xe0002fe4u +#define CYREG_FPB_PID2 0xe0002fe8u +#define CYREG_FPB_PID3 0xe0002fecu +#define CYREG_FPB_CID0 0xe0002ff0u +#define CYREG_FPB_CID1 0xe0002ff4u +#define CYREG_FPB_CID2 0xe0002ff8u +#define CYREG_FPB_CID3 0xe0002ffcu +#define CYDEV_NVIC_BASE 0xe000e000u +#define CYDEV_NVIC_SIZE 0x00000d3cu +#define CYREG_NVIC_INT_CTL_TYPE 0xe000e004u +#define CYREG_NVIC_SYSTICK_CTL 0xe000e010u +#define CYREG_NVIC_SYSTICK_RELOAD 0xe000e014u +#define CYREG_NVIC_SYSTICK_CURRENT 0xe000e018u +#define CYREG_NVIC_SYSTICK_CAL 0xe000e01cu +#define CYREG_NVIC_SETENA0 0xe000e100u +#define CYREG_NVIC_CLRENA0 0xe000e180u +#define CYREG_NVIC_SETPEND0 0xe000e200u +#define CYREG_NVIC_CLRPEND0 0xe000e280u +#define CYREG_NVIC_ACTIVE0 0xe000e300u +#define CYREG_NVIC_PRI_0 0xe000e400u +#define CYREG_NVIC_PRI_1 0xe000e401u +#define CYREG_NVIC_PRI_2 0xe000e402u +#define CYREG_NVIC_PRI_3 0xe000e403u +#define CYREG_NVIC_PRI_4 0xe000e404u +#define CYREG_NVIC_PRI_5 0xe000e405u +#define CYREG_NVIC_PRI_6 0xe000e406u +#define CYREG_NVIC_PRI_7 0xe000e407u +#define CYREG_NVIC_PRI_8 0xe000e408u +#define CYREG_NVIC_PRI_9 0xe000e409u +#define CYREG_NVIC_PRI_10 0xe000e40au +#define CYREG_NVIC_PRI_11 0xe000e40bu +#define CYREG_NVIC_PRI_12 0xe000e40cu +#define CYREG_NVIC_PRI_13 0xe000e40du +#define CYREG_NVIC_PRI_14 0xe000e40eu +#define CYREG_NVIC_PRI_15 0xe000e40fu +#define CYREG_NVIC_PRI_16 0xe000e410u +#define CYREG_NVIC_PRI_17 0xe000e411u +#define CYREG_NVIC_PRI_18 0xe000e412u +#define CYREG_NVIC_PRI_19 0xe000e413u +#define CYREG_NVIC_PRI_20 0xe000e414u +#define CYREG_NVIC_PRI_21 0xe000e415u +#define CYREG_NVIC_PRI_22 0xe000e416u +#define CYREG_NVIC_PRI_23 0xe000e417u +#define CYREG_NVIC_PRI_24 0xe000e418u +#define CYREG_NVIC_PRI_25 0xe000e419u +#define CYREG_NVIC_PRI_26 0xe000e41au +#define CYREG_NVIC_PRI_27 0xe000e41bu +#define CYREG_NVIC_PRI_28 0xe000e41cu +#define CYREG_NVIC_PRI_29 0xe000e41du +#define CYREG_NVIC_PRI_30 0xe000e41eu +#define CYREG_NVIC_PRI_31 0xe000e41fu +#define CYREG_NVIC_CPUID_BASE 0xe000ed00u +#define CYREG_NVIC_INTR_CTRL_STATE 0xe000ed04u +#define CYREG_NVIC_VECT_OFFSET 0xe000ed08u +#define CYREG_NVIC_APPLN_INTR 0xe000ed0cu +#define CYREG_NVIC_SYSTEM_CONTROL 0xe000ed10u +#define CYREG_NVIC_CFG_CONTROL 0xe000ed14u +#define CYREG_NVIC_SYS_PRIO_HANDLER_4_7 0xe000ed18u +#define CYREG_NVIC_SYS_PRIO_HANDLER_8_11 0xe000ed1cu +#define CYREG_NVIC_SYS_PRIO_HANDLER_12_15 0xe000ed20u +#define CYREG_NVIC_SYS_HANDLER_CSR 0xe000ed24u +#define CYREG_NVIC_MEMMAN_FAULT_STATUS 0xe000ed28u +#define CYREG_NVIC_BUS_FAULT_STATUS 0xe000ed29u +#define CYREG_NVIC_USAGE_FAULT_STATUS 0xe000ed2au +#define CYREG_NVIC_HARD_FAULT_STATUS 0xe000ed2cu +#define CYREG_NVIC_DEBUG_FAULT_STATUS 0xe000ed30u +#define CYREG_NVIC_MEMMAN_FAULT_ADD 0xe000ed34u +#define CYREG_NVIC_BUS_FAULT_ADD 0xe000ed38u +#define CYDEV_CORE_DBG_BASE 0xe000edf0u +#define CYDEV_CORE_DBG_SIZE 0x00000010u +#define CYREG_CORE_DBG_DBG_HLT_CS 0xe000edf0u +#define CYREG_CORE_DBG_DBG_REG_SEL 0xe000edf4u +#define CYREG_CORE_DBG_DBG_REG_DATA 0xe000edf8u +#define CYREG_CORE_DBG_EXC_MON_CTL 0xe000edfcu +#define CYDEV_TPIU_BASE 0xe0040000u +#define CYDEV_TPIU_SIZE 0x00001000u +#define CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ 0xe0040000u +#define CYREG_TPIU_CURRENT_SYNC_PRT_SZ 0xe0040004u +#define CYREG_TPIU_ASYNC_CLK_PRESCALER 0xe0040010u +#define CYREG_TPIU_PROTOCOL 0xe00400f0u +#define CYREG_TPIU_FORM_FLUSH_STAT 0xe0040300u +#define CYREG_TPIU_FORM_FLUSH_CTRL 0xe0040304u +#define CYREG_TPIU_TRIGGER 0xe0040ee8u +#define CYREG_TPIU_ITETMDATA 0xe0040eecu +#define CYREG_TPIU_ITATBCTR2 0xe0040ef0u +#define CYREG_TPIU_ITATBCTR0 0xe0040ef8u +#define CYREG_TPIU_ITITMDATA 0xe0040efcu +#define CYREG_TPIU_ITCTRL 0xe0040f00u +#define CYREG_TPIU_DEVID 0xe0040fc8u +#define CYREG_TPIU_DEVTYPE 0xe0040fccu +#define CYREG_TPIU_PID4 0xe0040fd0u +#define CYREG_TPIU_PID5 0xe0040fd4u +#define CYREG_TPIU_PID6 0xe0040fd8u +#define CYREG_TPIU_PID7 0xe0040fdcu +#define CYREG_TPIU_PID0 0xe0040fe0u +#define CYREG_TPIU_PID1 0xe0040fe4u +#define CYREG_TPIU_PID2 0xe0040fe8u +#define CYREG_TPIU_PID3 0xe0040fecu +#define CYREG_TPIU_CID0 0xe0040ff0u +#define CYREG_TPIU_CID1 0xe0040ff4u +#define CYREG_TPIU_CID2 0xe0040ff8u +#define CYREG_TPIU_CID3 0xe0040ffcu +#define CYDEV_ETM_BASE 0xe0041000u +#define CYDEV_ETM_SIZE 0x00001000u +#define CYREG_ETM_CTL 0xe0041000u +#define CYREG_ETM_CFG_CODE 0xe0041004u +#define CYREG_ETM_TRIG_EVENT 0xe0041008u +#define CYREG_ETM_STATUS 0xe0041010u +#define CYREG_ETM_SYS_CFG 0xe0041014u +#define CYREG_ETM_TRACE_ENB_EVENT 0xe0041020u +#define CYREG_ETM_TRACE_EN_CTRL1 0xe0041024u +#define CYREG_ETM_FIFOFULL_LEVEL 0xe004102cu +#define CYREG_ETM_SYNC_FREQ 0xe00411e0u +#define CYREG_ETM_ETM_ID 0xe00411e4u +#define CYREG_ETM_CFG_CODE_EXT 0xe00411e8u +#define CYREG_ETM_TR_SS_EMBICE_CTRL 0xe00411f0u +#define CYREG_ETM_CS_TRACE_ID 0xe0041200u +#define CYREG_ETM_OS_LOCK_ACCESS 0xe0041300u +#define CYREG_ETM_OS_LOCK_STATUS 0xe0041304u +#define CYREG_ETM_PDSR 0xe0041314u +#define CYREG_ETM_ITMISCIN 0xe0041ee0u +#define CYREG_ETM_ITTRIGOUT 0xe0041ee8u +#define CYREG_ETM_ITATBCTR2 0xe0041ef0u +#define CYREG_ETM_ITATBCTR0 0xe0041ef8u +#define CYREG_ETM_INT_MODE_CTRL 0xe0041f00u +#define CYREG_ETM_CLM_TAG_SET 0xe0041fa0u +#define CYREG_ETM_CLM_TAG_CLR 0xe0041fa4u +#define CYREG_ETM_LOCK_ACCESS 0xe0041fb0u +#define CYREG_ETM_LOCK_STATUS 0xe0041fb4u +#define CYREG_ETM_AUTH_STATUS 0xe0041fb8u +#define CYREG_ETM_DEV_TYPE 0xe0041fccu +#define CYREG_ETM_PID4 0xe0041fd0u +#define CYREG_ETM_PID5 0xe0041fd4u +#define CYREG_ETM_PID6 0xe0041fd8u +#define CYREG_ETM_PID7 0xe0041fdcu +#define CYREG_ETM_PID0 0xe0041fe0u +#define CYREG_ETM_PID1 0xe0041fe4u +#define CYREG_ETM_PID2 0xe0041fe8u +#define CYREG_ETM_PID3 0xe0041fecu +#define CYREG_ETM_CID0 0xe0041ff0u +#define CYREG_ETM_CID1 0xe0041ff4u +#define CYREG_ETM_CID2 0xe0041ff8u +#define CYREG_ETM_CID3 0xe0041ffcu +#define CYDEV_ROM_TABLE_BASE 0xe00ff000u +#define CYDEV_ROM_TABLE_SIZE 0x00001000u +#define CYREG_ROM_TABLE_NVIC 0xe00ff000u +#define CYREG_ROM_TABLE_DWT 0xe00ff004u +#define CYREG_ROM_TABLE_FPB 0xe00ff008u +#define CYREG_ROM_TABLE_ITM 0xe00ff00cu +#define CYREG_ROM_TABLE_TPIU 0xe00ff010u +#define CYREG_ROM_TABLE_ETM 0xe00ff014u +#define CYREG_ROM_TABLE_END 0xe00ff018u +#define CYREG_ROM_TABLE_MEMTYPE 0xe00fffccu +#define CYREG_ROM_TABLE_PID4 0xe00fffd0u +#define CYREG_ROM_TABLE_PID5 0xe00fffd4u +#define CYREG_ROM_TABLE_PID6 0xe00fffd8u +#define CYREG_ROM_TABLE_PID7 0xe00fffdcu +#define CYREG_ROM_TABLE_PID0 0xe00fffe0u +#define CYREG_ROM_TABLE_PID1 0xe00fffe4u +#define CYREG_ROM_TABLE_PID2 0xe00fffe8u +#define CYREG_ROM_TABLE_PID3 0xe00fffecu +#define CYREG_ROM_TABLE_CID0 0xe00ffff0u +#define CYREG_ROM_TABLE_CID1 0xe00ffff4u +#define CYREG_ROM_TABLE_CID2 0xe00ffff8u +#define CYREG_ROM_TABLE_CID3 0xe00ffffcu +#define CYDEV_FLS_SIZE CYDEV_FLASH_SIZE +#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE +#define CYDEV_FLS_SECTOR_SIZE 0x00010000u +#define CYDEV_FLS_ROW_SIZE 0x00000100u +#define CYDEV_ECC_SECTOR_SIZE 0x00002000u +#define CYDEV_ECC_ROW_SIZE 0x00000020u +#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400u +#define CYDEV_EEPROM_ROW_SIZE 0x00000010u +#define CYDEV_PERIPH_BASE CYDEV_CLKDIST_BASE +#define CYCLK_LD_DISABLE 0x00000004u +#define CYCLK_LD_SYNC_EN 0x00000002u +#define CYCLK_LD_LOAD 0x00000001u +#define CYCLK_PIPE 0x00000080u +#define CYCLK_SSS 0x00000040u +#define CYCLK_EARLY 0x00000020u +#define CYCLK_DUTY 0x00000010u +#define CYCLK_SYNC 0x00000008u +#define CYCLK_SRC_SEL_CLK_SYNC_D 0 +#define CYCLK_SRC_SEL_SYNC_DIG 0 +#define CYCLK_SRC_SEL_IMO 1 +#define CYCLK_SRC_SEL_XTAL_MHZ 2 +#define CYCLK_SRC_SEL_XTALM 2 +#define CYCLK_SRC_SEL_ILO 3 +#define CYCLK_SRC_SEL_PLL 4 +#define CYCLK_SRC_SEL_XTAL_KHZ 5 +#define CYCLK_SRC_SEL_XTALK 5 +#define CYCLK_SRC_SEL_DSI_G 6 +#define CYCLK_SRC_SEL_DSI_D 7 +#define CYCLK_SRC_SEL_CLK_SYNC_A 0 +#define CYCLK_SRC_SEL_DSI_A 7 +#endif /* CYDEVICE_TRM_H */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu.inc b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu.inc new file mode 100755 index 00000000..dc11e6db --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu.inc @@ -0,0 +1,5357 @@ +/******************************************************************************* +* FILENAME: cydevicegnu.inc +* OBSOLETE: Do not use this file. Use the _trm version instead. +* PSoC Creator 3.0 Component Pack 7 +* +* DESCRIPTION: +* This file provides all of the address values for the entire PSoC device. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +.set CYDEV_FLASH_BASE, 0x00000000 +.set CYDEV_FLASH_SIZE, 0x00020000 +.set CYDEV_FLASH_DATA_MBASE, 0x00000000 +.set CYDEV_FLASH_DATA_MSIZE, 0x00020000 +.set CYDEV_SRAM_BASE, 0x1fffc000 +.set CYDEV_SRAM_SIZE, 0x00008000 +.set CYDEV_SRAM_CODE64K_MBASE, 0x1fff8000 +.set CYDEV_SRAM_CODE64K_MSIZE, 0x00004000 +.set CYDEV_SRAM_CODE32K_MBASE, 0x1fffc000 +.set CYDEV_SRAM_CODE32K_MSIZE, 0x00002000 +.set CYDEV_SRAM_CODE16K_MBASE, 0x1fffe000 +.set CYDEV_SRAM_CODE16K_MSIZE, 0x00001000 +.set CYDEV_SRAM_CODE_MBASE, 0x1fffc000 +.set CYDEV_SRAM_CODE_MSIZE, 0x00004000 +.set CYDEV_SRAM_DATA_MBASE, 0x20000000 +.set CYDEV_SRAM_DATA_MSIZE, 0x00004000 +.set CYDEV_SRAM_DATA16K_MBASE, 0x20001000 +.set CYDEV_SRAM_DATA16K_MSIZE, 0x00001000 +.set CYDEV_SRAM_DATA32K_MBASE, 0x20002000 +.set CYDEV_SRAM_DATA32K_MSIZE, 0x00002000 +.set CYDEV_SRAM_DATA64K_MBASE, 0x20004000 +.set CYDEV_SRAM_DATA64K_MSIZE, 0x00004000 +.set CYDEV_DMA_BASE, 0x20008000 +.set CYDEV_DMA_SIZE, 0x00008000 +.set CYDEV_DMA_SRAM64K_MBASE, 0x20008000 +.set CYDEV_DMA_SRAM64K_MSIZE, 0x00004000 +.set CYDEV_DMA_SRAM32K_MBASE, 0x2000c000 +.set CYDEV_DMA_SRAM32K_MSIZE, 0x00002000 +.set CYDEV_DMA_SRAM16K_MBASE, 0x2000e000 +.set CYDEV_DMA_SRAM16K_MSIZE, 0x00001000 +.set CYDEV_DMA_SRAM_MBASE, 0x2000f000 +.set CYDEV_DMA_SRAM_MSIZE, 0x00001000 +.set CYDEV_CLKDIST_BASE, 0x40004000 +.set CYDEV_CLKDIST_SIZE, 0x00000110 +.set CYDEV_CLKDIST_CR, 0x40004000 +.set CYDEV_CLKDIST_LD, 0x40004001 +.set CYDEV_CLKDIST_WRK0, 0x40004002 +.set CYDEV_CLKDIST_WRK1, 0x40004003 +.set CYDEV_CLKDIST_MSTR0, 0x40004004 +.set CYDEV_CLKDIST_MSTR1, 0x40004005 +.set CYDEV_CLKDIST_BCFG0, 0x40004006 +.set CYDEV_CLKDIST_BCFG1, 0x40004007 +.set CYDEV_CLKDIST_BCFG2, 0x40004008 +.set CYDEV_CLKDIST_UCFG, 0x40004009 +.set CYDEV_CLKDIST_DLY0, 0x4000400a +.set CYDEV_CLKDIST_DLY1, 0x4000400b +.set CYDEV_CLKDIST_DMASK, 0x40004010 +.set CYDEV_CLKDIST_AMASK, 0x40004014 +.set CYDEV_CLKDIST_DCFG0_BASE, 0x40004080 +.set CYDEV_CLKDIST_DCFG0_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG0_CFG0, 0x40004080 +.set CYDEV_CLKDIST_DCFG0_CFG1, 0x40004081 +.set CYDEV_CLKDIST_DCFG0_CFG2, 0x40004082 +.set CYDEV_CLKDIST_DCFG1_BASE, 0x40004084 +.set CYDEV_CLKDIST_DCFG1_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG1_CFG0, 0x40004084 +.set CYDEV_CLKDIST_DCFG1_CFG1, 0x40004085 +.set CYDEV_CLKDIST_DCFG1_CFG2, 0x40004086 +.set CYDEV_CLKDIST_DCFG2_BASE, 0x40004088 +.set CYDEV_CLKDIST_DCFG2_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG2_CFG0, 0x40004088 +.set CYDEV_CLKDIST_DCFG2_CFG1, 0x40004089 +.set CYDEV_CLKDIST_DCFG2_CFG2, 0x4000408a +.set CYDEV_CLKDIST_DCFG3_BASE, 0x4000408c +.set CYDEV_CLKDIST_DCFG3_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG3_CFG0, 0x4000408c +.set CYDEV_CLKDIST_DCFG3_CFG1, 0x4000408d +.set CYDEV_CLKDIST_DCFG3_CFG2, 0x4000408e +.set CYDEV_CLKDIST_DCFG4_BASE, 0x40004090 +.set CYDEV_CLKDIST_DCFG4_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG4_CFG0, 0x40004090 +.set CYDEV_CLKDIST_DCFG4_CFG1, 0x40004091 +.set CYDEV_CLKDIST_DCFG4_CFG2, 0x40004092 +.set CYDEV_CLKDIST_DCFG5_BASE, 0x40004094 +.set CYDEV_CLKDIST_DCFG5_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG5_CFG0, 0x40004094 +.set CYDEV_CLKDIST_DCFG5_CFG1, 0x40004095 +.set CYDEV_CLKDIST_DCFG5_CFG2, 0x40004096 +.set CYDEV_CLKDIST_DCFG6_BASE, 0x40004098 +.set CYDEV_CLKDIST_DCFG6_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG6_CFG0, 0x40004098 +.set CYDEV_CLKDIST_DCFG6_CFG1, 0x40004099 +.set CYDEV_CLKDIST_DCFG6_CFG2, 0x4000409a +.set CYDEV_CLKDIST_DCFG7_BASE, 0x4000409c +.set CYDEV_CLKDIST_DCFG7_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG7_CFG0, 0x4000409c +.set CYDEV_CLKDIST_DCFG7_CFG1, 0x4000409d +.set CYDEV_CLKDIST_DCFG7_CFG2, 0x4000409e +.set CYDEV_CLKDIST_ACFG0_BASE, 0x40004100 +.set CYDEV_CLKDIST_ACFG0_SIZE, 0x00000004 +.set CYDEV_CLKDIST_ACFG0_CFG0, 0x40004100 +.set CYDEV_CLKDIST_ACFG0_CFG1, 0x40004101 +.set CYDEV_CLKDIST_ACFG0_CFG2, 0x40004102 +.set CYDEV_CLKDIST_ACFG0_CFG3, 0x40004103 +.set CYDEV_CLKDIST_ACFG1_BASE, 0x40004104 +.set CYDEV_CLKDIST_ACFG1_SIZE, 0x00000004 +.set CYDEV_CLKDIST_ACFG1_CFG0, 0x40004104 +.set CYDEV_CLKDIST_ACFG1_CFG1, 0x40004105 +.set CYDEV_CLKDIST_ACFG1_CFG2, 0x40004106 +.set CYDEV_CLKDIST_ACFG1_CFG3, 0x40004107 +.set CYDEV_CLKDIST_ACFG2_BASE, 0x40004108 +.set CYDEV_CLKDIST_ACFG2_SIZE, 0x00000004 +.set CYDEV_CLKDIST_ACFG2_CFG0, 0x40004108 +.set CYDEV_CLKDIST_ACFG2_CFG1, 0x40004109 +.set CYDEV_CLKDIST_ACFG2_CFG2, 0x4000410a +.set CYDEV_CLKDIST_ACFG2_CFG3, 0x4000410b +.set CYDEV_CLKDIST_ACFG3_BASE, 0x4000410c +.set CYDEV_CLKDIST_ACFG3_SIZE, 0x00000004 +.set CYDEV_CLKDIST_ACFG3_CFG0, 0x4000410c +.set CYDEV_CLKDIST_ACFG3_CFG1, 0x4000410d +.set CYDEV_CLKDIST_ACFG3_CFG2, 0x4000410e +.set CYDEV_CLKDIST_ACFG3_CFG3, 0x4000410f +.set CYDEV_FASTCLK_BASE, 0x40004200 +.set CYDEV_FASTCLK_SIZE, 0x00000026 +.set CYDEV_FASTCLK_IMO_BASE, 0x40004200 +.set CYDEV_FASTCLK_IMO_SIZE, 0x00000001 +.set CYDEV_FASTCLK_IMO_CR, 0x40004200 +.set CYDEV_FASTCLK_XMHZ_BASE, 0x40004210 +.set CYDEV_FASTCLK_XMHZ_SIZE, 0x00000004 +.set CYDEV_FASTCLK_XMHZ_CSR, 0x40004210 +.set CYDEV_FASTCLK_XMHZ_CFG0, 0x40004212 +.set CYDEV_FASTCLK_XMHZ_CFG1, 0x40004213 +.set CYDEV_FASTCLK_PLL_BASE, 0x40004220 +.set CYDEV_FASTCLK_PLL_SIZE, 0x00000006 +.set CYDEV_FASTCLK_PLL_CFG0, 0x40004220 +.set CYDEV_FASTCLK_PLL_CFG1, 0x40004221 +.set CYDEV_FASTCLK_PLL_P, 0x40004222 +.set CYDEV_FASTCLK_PLL_Q, 0x40004223 +.set CYDEV_FASTCLK_PLL_SR, 0x40004225 +.set CYDEV_SLOWCLK_BASE, 0x40004300 +.set CYDEV_SLOWCLK_SIZE, 0x0000000b +.set CYDEV_SLOWCLK_ILO_BASE, 0x40004300 +.set CYDEV_SLOWCLK_ILO_SIZE, 0x00000002 +.set CYDEV_SLOWCLK_ILO_CR0, 0x40004300 +.set CYDEV_SLOWCLK_ILO_CR1, 0x40004301 +.set CYDEV_SLOWCLK_X32_BASE, 0x40004308 +.set CYDEV_SLOWCLK_X32_SIZE, 0x00000003 +.set CYDEV_SLOWCLK_X32_CR, 0x40004308 +.set CYDEV_SLOWCLK_X32_CFG, 0x40004309 +.set CYDEV_SLOWCLK_X32_TST, 0x4000430a +.set CYDEV_BOOST_BASE, 0x40004320 +.set CYDEV_BOOST_SIZE, 0x00000007 +.set CYDEV_BOOST_CR0, 0x40004320 +.set CYDEV_BOOST_CR1, 0x40004321 +.set CYDEV_BOOST_CR2, 0x40004322 +.set CYDEV_BOOST_CR3, 0x40004323 +.set CYDEV_BOOST_SR, 0x40004324 +.set CYDEV_BOOST_CR4, 0x40004325 +.set CYDEV_BOOST_SR2, 0x40004326 +.set CYDEV_PWRSYS_BASE, 0x40004330 +.set CYDEV_PWRSYS_SIZE, 0x00000002 +.set CYDEV_PWRSYS_CR0, 0x40004330 +.set CYDEV_PWRSYS_CR1, 0x40004331 +.set CYDEV_PM_BASE, 0x40004380 +.set CYDEV_PM_SIZE, 0x00000057 +.set CYDEV_PM_TW_CFG0, 0x40004380 +.set CYDEV_PM_TW_CFG1, 0x40004381 +.set CYDEV_PM_TW_CFG2, 0x40004382 +.set CYDEV_PM_WDT_CFG, 0x40004383 +.set CYDEV_PM_WDT_CR, 0x40004384 +.set CYDEV_PM_INT_SR, 0x40004390 +.set CYDEV_PM_MODE_CFG0, 0x40004391 +.set CYDEV_PM_MODE_CFG1, 0x40004392 +.set CYDEV_PM_MODE_CSR, 0x40004393 +.set CYDEV_PM_USB_CR0, 0x40004394 +.set CYDEV_PM_WAKEUP_CFG0, 0x40004398 +.set CYDEV_PM_WAKEUP_CFG1, 0x40004399 +.set CYDEV_PM_WAKEUP_CFG2, 0x4000439a +.set CYDEV_PM_ACT_BASE, 0x400043a0 +.set CYDEV_PM_ACT_SIZE, 0x0000000e +.set CYDEV_PM_ACT_CFG0, 0x400043a0 +.set CYDEV_PM_ACT_CFG1, 0x400043a1 +.set CYDEV_PM_ACT_CFG2, 0x400043a2 +.set CYDEV_PM_ACT_CFG3, 0x400043a3 +.set CYDEV_PM_ACT_CFG4, 0x400043a4 +.set CYDEV_PM_ACT_CFG5, 0x400043a5 +.set CYDEV_PM_ACT_CFG6, 0x400043a6 +.set CYDEV_PM_ACT_CFG7, 0x400043a7 +.set CYDEV_PM_ACT_CFG8, 0x400043a8 +.set CYDEV_PM_ACT_CFG9, 0x400043a9 +.set CYDEV_PM_ACT_CFG10, 0x400043aa +.set CYDEV_PM_ACT_CFG11, 0x400043ab +.set CYDEV_PM_ACT_CFG12, 0x400043ac +.set CYDEV_PM_ACT_CFG13, 0x400043ad +.set CYDEV_PM_STBY_BASE, 0x400043b0 +.set CYDEV_PM_STBY_SIZE, 0x0000000e +.set CYDEV_PM_STBY_CFG0, 0x400043b0 +.set CYDEV_PM_STBY_CFG1, 0x400043b1 +.set CYDEV_PM_STBY_CFG2, 0x400043b2 +.set CYDEV_PM_STBY_CFG3, 0x400043b3 +.set CYDEV_PM_STBY_CFG4, 0x400043b4 +.set CYDEV_PM_STBY_CFG5, 0x400043b5 +.set CYDEV_PM_STBY_CFG6, 0x400043b6 +.set CYDEV_PM_STBY_CFG7, 0x400043b7 +.set CYDEV_PM_STBY_CFG8, 0x400043b8 +.set CYDEV_PM_STBY_CFG9, 0x400043b9 +.set CYDEV_PM_STBY_CFG10, 0x400043ba +.set CYDEV_PM_STBY_CFG11, 0x400043bb +.set CYDEV_PM_STBY_CFG12, 0x400043bc +.set CYDEV_PM_STBY_CFG13, 0x400043bd +.set CYDEV_PM_AVAIL_BASE, 0x400043c0 +.set CYDEV_PM_AVAIL_SIZE, 0x00000017 +.set CYDEV_PM_AVAIL_CR0, 0x400043c0 +.set CYDEV_PM_AVAIL_CR1, 0x400043c1 +.set CYDEV_PM_AVAIL_CR2, 0x400043c2 +.set CYDEV_PM_AVAIL_CR3, 0x400043c3 +.set CYDEV_PM_AVAIL_CR4, 0x400043c4 +.set CYDEV_PM_AVAIL_CR5, 0x400043c5 +.set CYDEV_PM_AVAIL_CR6, 0x400043c6 +.set CYDEV_PM_AVAIL_SR0, 0x400043d0 +.set CYDEV_PM_AVAIL_SR1, 0x400043d1 +.set CYDEV_PM_AVAIL_SR2, 0x400043d2 +.set CYDEV_PM_AVAIL_SR3, 0x400043d3 +.set CYDEV_PM_AVAIL_SR4, 0x400043d4 +.set CYDEV_PM_AVAIL_SR5, 0x400043d5 +.set CYDEV_PM_AVAIL_SR6, 0x400043d6 +.set CYDEV_PICU_BASE, 0x40004500 +.set CYDEV_PICU_SIZE, 0x000000b0 +.set CYDEV_PICU_INTTYPE_BASE, 0x40004500 +.set CYDEV_PICU_INTTYPE_SIZE, 0x00000080 +.set CYDEV_PICU_INTTYPE_PICU0_BASE, 0x40004500 +.set CYDEV_PICU_INTTYPE_PICU0_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE0, 0x40004500 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE1, 0x40004501 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE2, 0x40004502 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE3, 0x40004503 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE4, 0x40004504 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE5, 0x40004505 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE6, 0x40004506 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE7, 0x40004507 +.set CYDEV_PICU_INTTYPE_PICU1_BASE, 0x40004508 +.set CYDEV_PICU_INTTYPE_PICU1_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE0, 0x40004508 +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE1, 0x40004509 +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE2, 0x4000450a +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE3, 0x4000450b +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE4, 0x4000450c +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE5, 0x4000450d +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE6, 0x4000450e +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE7, 0x4000450f +.set CYDEV_PICU_INTTYPE_PICU2_BASE, 0x40004510 +.set CYDEV_PICU_INTTYPE_PICU2_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE0, 0x40004510 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE1, 0x40004511 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE2, 0x40004512 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE3, 0x40004513 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE4, 0x40004514 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE5, 0x40004515 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE6, 0x40004516 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE7, 0x40004517 +.set CYDEV_PICU_INTTYPE_PICU3_BASE, 0x40004518 +.set CYDEV_PICU_INTTYPE_PICU3_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE0, 0x40004518 +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE1, 0x40004519 +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE2, 0x4000451a +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE3, 0x4000451b +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE4, 0x4000451c +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE5, 0x4000451d +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE6, 0x4000451e +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE7, 0x4000451f +.set CYDEV_PICU_INTTYPE_PICU4_BASE, 0x40004520 +.set CYDEV_PICU_INTTYPE_PICU4_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE0, 0x40004520 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE1, 0x40004521 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE2, 0x40004522 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE3, 0x40004523 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE4, 0x40004524 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE5, 0x40004525 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE6, 0x40004526 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE7, 0x40004527 +.set CYDEV_PICU_INTTYPE_PICU5_BASE, 0x40004528 +.set CYDEV_PICU_INTTYPE_PICU5_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE0, 0x40004528 +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE1, 0x40004529 +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE2, 0x4000452a +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE3, 0x4000452b +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE4, 0x4000452c +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE5, 0x4000452d +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE6, 0x4000452e +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE7, 0x4000452f +.set CYDEV_PICU_INTTYPE_PICU6_BASE, 0x40004530 +.set CYDEV_PICU_INTTYPE_PICU6_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE0, 0x40004530 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE1, 0x40004531 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE2, 0x40004532 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE3, 0x40004533 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE4, 0x40004534 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE5, 0x40004535 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE6, 0x40004536 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE7, 0x40004537 +.set CYDEV_PICU_INTTYPE_PICU12_BASE, 0x40004560 +.set CYDEV_PICU_INTTYPE_PICU12_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE0, 0x40004560 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE1, 0x40004561 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE2, 0x40004562 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE3, 0x40004563 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE4, 0x40004564 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE5, 0x40004565 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE6, 0x40004566 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE7, 0x40004567 +.set CYDEV_PICU_INTTYPE_PICU15_BASE, 0x40004578 +.set CYDEV_PICU_INTTYPE_PICU15_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE0, 0x40004578 +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE1, 0x40004579 +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE2, 0x4000457a +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE3, 0x4000457b +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE4, 0x4000457c +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE5, 0x4000457d +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE6, 0x4000457e +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE7, 0x4000457f +.set CYDEV_PICU_STAT_BASE, 0x40004580 +.set CYDEV_PICU_STAT_SIZE, 0x00000010 +.set CYDEV_PICU_STAT_PICU0_BASE, 0x40004580 +.set CYDEV_PICU_STAT_PICU0_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU0_INTSTAT, 0x40004580 +.set CYDEV_PICU_STAT_PICU1_BASE, 0x40004581 +.set CYDEV_PICU_STAT_PICU1_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU1_INTSTAT, 0x40004581 +.set CYDEV_PICU_STAT_PICU2_BASE, 0x40004582 +.set CYDEV_PICU_STAT_PICU2_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU2_INTSTAT, 0x40004582 +.set CYDEV_PICU_STAT_PICU3_BASE, 0x40004583 +.set CYDEV_PICU_STAT_PICU3_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU3_INTSTAT, 0x40004583 +.set CYDEV_PICU_STAT_PICU4_BASE, 0x40004584 +.set CYDEV_PICU_STAT_PICU4_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU4_INTSTAT, 0x40004584 +.set CYDEV_PICU_STAT_PICU5_BASE, 0x40004585 +.set CYDEV_PICU_STAT_PICU5_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU5_INTSTAT, 0x40004585 +.set CYDEV_PICU_STAT_PICU6_BASE, 0x40004586 +.set CYDEV_PICU_STAT_PICU6_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU6_INTSTAT, 0x40004586 +.set CYDEV_PICU_STAT_PICU12_BASE, 0x4000458c +.set CYDEV_PICU_STAT_PICU12_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU12_INTSTAT, 0x4000458c +.set CYDEV_PICU_STAT_PICU15_BASE, 0x4000458f +.set CYDEV_PICU_STAT_PICU15_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU15_INTSTAT, 0x4000458f +.set CYDEV_PICU_SNAP_BASE, 0x40004590 +.set CYDEV_PICU_SNAP_SIZE, 0x00000010 +.set CYDEV_PICU_SNAP_PICU0_BASE, 0x40004590 +.set CYDEV_PICU_SNAP_PICU0_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU0_SNAP, 0x40004590 +.set CYDEV_PICU_SNAP_PICU1_BASE, 0x40004591 +.set CYDEV_PICU_SNAP_PICU1_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU1_SNAP, 0x40004591 +.set CYDEV_PICU_SNAP_PICU2_BASE, 0x40004592 +.set CYDEV_PICU_SNAP_PICU2_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU2_SNAP, 0x40004592 +.set CYDEV_PICU_SNAP_PICU3_BASE, 0x40004593 +.set CYDEV_PICU_SNAP_PICU3_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU3_SNAP, 0x40004593 +.set CYDEV_PICU_SNAP_PICU4_BASE, 0x40004594 +.set CYDEV_PICU_SNAP_PICU4_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU4_SNAP, 0x40004594 +.set CYDEV_PICU_SNAP_PICU5_BASE, 0x40004595 +.set CYDEV_PICU_SNAP_PICU5_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU5_SNAP, 0x40004595 +.set CYDEV_PICU_SNAP_PICU6_BASE, 0x40004596 +.set CYDEV_PICU_SNAP_PICU6_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU6_SNAP, 0x40004596 +.set CYDEV_PICU_SNAP_PICU12_BASE, 0x4000459c +.set CYDEV_PICU_SNAP_PICU12_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU12_SNAP, 0x4000459c +.set CYDEV_PICU_SNAP_PICU_15_BASE, 0x4000459f +.set CYDEV_PICU_SNAP_PICU_15_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU_15_SNAP_15, 0x4000459f +.set CYDEV_PICU_DISABLE_COR_BASE, 0x400045a0 +.set CYDEV_PICU_DISABLE_COR_SIZE, 0x00000010 +.set CYDEV_PICU_DISABLE_COR_PICU0_BASE, 0x400045a0 +.set CYDEV_PICU_DISABLE_COR_PICU0_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR, 0x400045a0 +.set CYDEV_PICU_DISABLE_COR_PICU1_BASE, 0x400045a1 +.set CYDEV_PICU_DISABLE_COR_PICU1_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR, 0x400045a1 +.set CYDEV_PICU_DISABLE_COR_PICU2_BASE, 0x400045a2 +.set CYDEV_PICU_DISABLE_COR_PICU2_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR, 0x400045a2 +.set CYDEV_PICU_DISABLE_COR_PICU3_BASE, 0x400045a3 +.set CYDEV_PICU_DISABLE_COR_PICU3_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR, 0x400045a3 +.set CYDEV_PICU_DISABLE_COR_PICU4_BASE, 0x400045a4 +.set CYDEV_PICU_DISABLE_COR_PICU4_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR, 0x400045a4 +.set CYDEV_PICU_DISABLE_COR_PICU5_BASE, 0x400045a5 +.set CYDEV_PICU_DISABLE_COR_PICU5_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR, 0x400045a5 +.set CYDEV_PICU_DISABLE_COR_PICU6_BASE, 0x400045a6 +.set CYDEV_PICU_DISABLE_COR_PICU6_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR, 0x400045a6 +.set CYDEV_PICU_DISABLE_COR_PICU12_BASE, 0x400045ac +.set CYDEV_PICU_DISABLE_COR_PICU12_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR, 0x400045ac +.set CYDEV_PICU_DISABLE_COR_PICU15_BASE, 0x400045af +.set CYDEV_PICU_DISABLE_COR_PICU15_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR, 0x400045af +.set CYDEV_MFGCFG_BASE, 0x40004600 +.set CYDEV_MFGCFG_SIZE, 0x000000ed +.set CYDEV_MFGCFG_ANAIF_BASE, 0x40004600 +.set CYDEV_MFGCFG_ANAIF_SIZE, 0x00000038 +.set CYDEV_MFGCFG_ANAIF_DAC0_BASE, 0x40004608 +.set CYDEV_MFGCFG_ANAIF_DAC0_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_DAC0_TR, 0x40004608 +.set CYDEV_MFGCFG_ANAIF_DAC1_BASE, 0x40004609 +.set CYDEV_MFGCFG_ANAIF_DAC1_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_DAC1_TR, 0x40004609 +.set CYDEV_MFGCFG_ANAIF_DAC2_BASE, 0x4000460a +.set CYDEV_MFGCFG_ANAIF_DAC2_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_DAC2_TR, 0x4000460a +.set CYDEV_MFGCFG_ANAIF_DAC3_BASE, 0x4000460b +.set CYDEV_MFGCFG_ANAIF_DAC3_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_DAC3_TR, 0x4000460b +.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE, 0x40004610 +.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0, 0x40004610 +.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE, 0x40004611 +.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0, 0x40004611 +.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE, 0x40004612 +.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0, 0x40004612 +.set CYDEV_MFGCFG_ANAIF_SAR0_BASE, 0x40004614 +.set CYDEV_MFGCFG_ANAIF_SAR0_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_SAR0_TR0, 0x40004614 +.set CYDEV_MFGCFG_ANAIF_SAR1_BASE, 0x40004616 +.set CYDEV_MFGCFG_ANAIF_SAR1_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_SAR1_TR0, 0x40004616 +.set CYDEV_MFGCFG_ANAIF_OPAMP0_BASE, 0x40004620 +.set CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_OPAMP0_TR0, 0x40004620 +.set CYDEV_MFGCFG_ANAIF_OPAMP0_TR1, 0x40004621 +.set CYDEV_MFGCFG_ANAIF_OPAMP1_BASE, 0x40004622 +.set CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_OPAMP1_TR0, 0x40004622 +.set CYDEV_MFGCFG_ANAIF_OPAMP1_TR1, 0x40004623 +.set CYDEV_MFGCFG_ANAIF_OPAMP2_BASE, 0x40004624 +.set CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_OPAMP2_TR0, 0x40004624 +.set CYDEV_MFGCFG_ANAIF_OPAMP2_TR1, 0x40004625 +.set CYDEV_MFGCFG_ANAIF_OPAMP3_BASE, 0x40004626 +.set CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_OPAMP3_TR0, 0x40004626 +.set CYDEV_MFGCFG_ANAIF_OPAMP3_TR1, 0x40004627 +.set CYDEV_MFGCFG_ANAIF_CMP0_BASE, 0x40004630 +.set CYDEV_MFGCFG_ANAIF_CMP0_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_CMP0_TR0, 0x40004630 +.set CYDEV_MFGCFG_ANAIF_CMP0_TR1, 0x40004631 +.set CYDEV_MFGCFG_ANAIF_CMP1_BASE, 0x40004632 +.set CYDEV_MFGCFG_ANAIF_CMP1_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_CMP1_TR0, 0x40004632 +.set CYDEV_MFGCFG_ANAIF_CMP1_TR1, 0x40004633 +.set CYDEV_MFGCFG_ANAIF_CMP2_BASE, 0x40004634 +.set CYDEV_MFGCFG_ANAIF_CMP2_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_CMP2_TR0, 0x40004634 +.set CYDEV_MFGCFG_ANAIF_CMP2_TR1, 0x40004635 +.set CYDEV_MFGCFG_ANAIF_CMP3_BASE, 0x40004636 +.set CYDEV_MFGCFG_ANAIF_CMP3_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_CMP3_TR0, 0x40004636 +.set CYDEV_MFGCFG_ANAIF_CMP3_TR1, 0x40004637 +.set CYDEV_MFGCFG_PWRSYS_BASE, 0x40004680 +.set CYDEV_MFGCFG_PWRSYS_SIZE, 0x0000000b +.set CYDEV_MFGCFG_PWRSYS_HIB_TR0, 0x40004680 +.set CYDEV_MFGCFG_PWRSYS_HIB_TR1, 0x40004681 +.set CYDEV_MFGCFG_PWRSYS_I2C_TR, 0x40004682 +.set CYDEV_MFGCFG_PWRSYS_SLP_TR, 0x40004683 +.set CYDEV_MFGCFG_PWRSYS_BUZZ_TR, 0x40004684 +.set CYDEV_MFGCFG_PWRSYS_WAKE_TR0, 0x40004685 +.set CYDEV_MFGCFG_PWRSYS_WAKE_TR1, 0x40004686 +.set CYDEV_MFGCFG_PWRSYS_BREF_TR, 0x40004687 +.set CYDEV_MFGCFG_PWRSYS_BG_TR, 0x40004688 +.set CYDEV_MFGCFG_PWRSYS_WAKE_TR2, 0x40004689 +.set CYDEV_MFGCFG_PWRSYS_WAKE_TR3, 0x4000468a +.set CYDEV_MFGCFG_ILO_BASE, 0x40004690 +.set CYDEV_MFGCFG_ILO_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ILO_TR0, 0x40004690 +.set CYDEV_MFGCFG_ILO_TR1, 0x40004691 +.set CYDEV_MFGCFG_X32_BASE, 0x40004698 +.set CYDEV_MFGCFG_X32_SIZE, 0x00000001 +.set CYDEV_MFGCFG_X32_TR, 0x40004698 +.set CYDEV_MFGCFG_IMO_BASE, 0x400046a0 +.set CYDEV_MFGCFG_IMO_SIZE, 0x00000005 +.set CYDEV_MFGCFG_IMO_TR0, 0x400046a0 +.set CYDEV_MFGCFG_IMO_TR1, 0x400046a1 +.set CYDEV_MFGCFG_IMO_GAIN, 0x400046a2 +.set CYDEV_MFGCFG_IMO_C36M, 0x400046a3 +.set CYDEV_MFGCFG_IMO_TR2, 0x400046a4 +.set CYDEV_MFGCFG_XMHZ_BASE, 0x400046a8 +.set CYDEV_MFGCFG_XMHZ_SIZE, 0x00000001 +.set CYDEV_MFGCFG_XMHZ_TR, 0x400046a8 +.set CYDEV_MFGCFG_DLY, 0x400046c0 +.set CYDEV_MFGCFG_MLOGIC_BASE, 0x400046e0 +.set CYDEV_MFGCFG_MLOGIC_SIZE, 0x0000000d +.set CYDEV_MFGCFG_MLOGIC_DMPSTR, 0x400046e2 +.set CYDEV_MFGCFG_MLOGIC_SEG_BASE, 0x400046e4 +.set CYDEV_MFGCFG_MLOGIC_SEG_SIZE, 0x00000002 +.set CYDEV_MFGCFG_MLOGIC_SEG_CR, 0x400046e4 +.set CYDEV_MFGCFG_MLOGIC_SEG_CFG0, 0x400046e5 +.set CYDEV_MFGCFG_MLOGIC_DEBUG, 0x400046e8 +.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE, 0x400046ea +.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE, 0x00000001 +.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR, 0x400046ea +.set CYDEV_MFGCFG_MLOGIC_REV_ID, 0x400046ec +.set CYDEV_RESET_BASE, 0x400046f0 +.set CYDEV_RESET_SIZE, 0x0000000f +.set CYDEV_RESET_IPOR_CR0, 0x400046f0 +.set CYDEV_RESET_IPOR_CR1, 0x400046f1 +.set CYDEV_RESET_IPOR_CR2, 0x400046f2 +.set CYDEV_RESET_IPOR_CR3, 0x400046f3 +.set CYDEV_RESET_CR0, 0x400046f4 +.set CYDEV_RESET_CR1, 0x400046f5 +.set CYDEV_RESET_CR2, 0x400046f6 +.set CYDEV_RESET_CR3, 0x400046f7 +.set CYDEV_RESET_CR4, 0x400046f8 +.set CYDEV_RESET_CR5, 0x400046f9 +.set CYDEV_RESET_SR0, 0x400046fa +.set CYDEV_RESET_SR1, 0x400046fb +.set CYDEV_RESET_SR2, 0x400046fc +.set CYDEV_RESET_SR3, 0x400046fd +.set CYDEV_RESET_TR, 0x400046fe +.set CYDEV_SPC_BASE, 0x40004700 +.set CYDEV_SPC_SIZE, 0x00000100 +.set CYDEV_SPC_FM_EE_CR, 0x40004700 +.set CYDEV_SPC_FM_EE_WAKE_CNT, 0x40004701 +.set CYDEV_SPC_EE_SCR, 0x40004702 +.set CYDEV_SPC_EE_ERR, 0x40004703 +.set CYDEV_SPC_CPU_DATA, 0x40004720 +.set CYDEV_SPC_DMA_DATA, 0x40004721 +.set CYDEV_SPC_SR, 0x40004722 +.set CYDEV_SPC_CR, 0x40004723 +.set CYDEV_SPC_DMM_MAP_BASE, 0x40004780 +.set CYDEV_SPC_DMM_MAP_SIZE, 0x00000080 +.set CYDEV_SPC_DMM_MAP_SRAM_MBASE, 0x40004780 +.set CYDEV_SPC_DMM_MAP_SRAM_MSIZE, 0x00000080 +.set CYDEV_CACHE_BASE, 0x40004800 +.set CYDEV_CACHE_SIZE, 0x0000009c +.set CYDEV_CACHE_CC_CTL, 0x40004800 +.set CYDEV_CACHE_ECC_CORR, 0x40004880 +.set CYDEV_CACHE_ECC_ERR, 0x40004888 +.set CYDEV_CACHE_FLASH_ERR, 0x40004890 +.set CYDEV_CACHE_HITMISS, 0x40004898 +.set CYDEV_I2C_BASE, 0x40004900 +.set CYDEV_I2C_SIZE, 0x000000e1 +.set CYDEV_I2C_XCFG, 0x400049c8 +.set CYDEV_I2C_ADR, 0x400049ca +.set CYDEV_I2C_CFG, 0x400049d6 +.set CYDEV_I2C_CSR, 0x400049d7 +.set CYDEV_I2C_D, 0x400049d8 +.set CYDEV_I2C_MCSR, 0x400049d9 +.set CYDEV_I2C_CLK_DIV1, 0x400049db +.set CYDEV_I2C_CLK_DIV2, 0x400049dc +.set CYDEV_I2C_TMOUT_CSR, 0x400049dd +.set CYDEV_I2C_TMOUT_SR, 0x400049de +.set CYDEV_I2C_TMOUT_CFG0, 0x400049df +.set CYDEV_I2C_TMOUT_CFG1, 0x400049e0 +.set CYDEV_DEC_BASE, 0x40004e00 +.set CYDEV_DEC_SIZE, 0x00000015 +.set CYDEV_DEC_CR, 0x40004e00 +.set CYDEV_DEC_SR, 0x40004e01 +.set CYDEV_DEC_SHIFT1, 0x40004e02 +.set CYDEV_DEC_SHIFT2, 0x40004e03 +.set CYDEV_DEC_DR2, 0x40004e04 +.set CYDEV_DEC_DR2H, 0x40004e05 +.set CYDEV_DEC_DR1, 0x40004e06 +.set CYDEV_DEC_OCOR, 0x40004e08 +.set CYDEV_DEC_OCORM, 0x40004e09 +.set CYDEV_DEC_OCORH, 0x40004e0a +.set CYDEV_DEC_GCOR, 0x40004e0c +.set CYDEV_DEC_GCORH, 0x40004e0d +.set CYDEV_DEC_GVAL, 0x40004e0e +.set CYDEV_DEC_OUTSAMP, 0x40004e10 +.set CYDEV_DEC_OUTSAMPM, 0x40004e11 +.set CYDEV_DEC_OUTSAMPH, 0x40004e12 +.set CYDEV_DEC_OUTSAMPS, 0x40004e13 +.set CYDEV_DEC_COHER, 0x40004e14 +.set CYDEV_TMR0_BASE, 0x40004f00 +.set CYDEV_TMR0_SIZE, 0x0000000c +.set CYDEV_TMR0_CFG0, 0x40004f00 +.set CYDEV_TMR0_CFG1, 0x40004f01 +.set CYDEV_TMR0_CFG2, 0x40004f02 +.set CYDEV_TMR0_SR0, 0x40004f03 +.set CYDEV_TMR0_PER0, 0x40004f04 +.set CYDEV_TMR0_PER1, 0x40004f05 +.set CYDEV_TMR0_CNT_CMP0, 0x40004f06 +.set CYDEV_TMR0_CNT_CMP1, 0x40004f07 +.set CYDEV_TMR0_CAP0, 0x40004f08 +.set CYDEV_TMR0_CAP1, 0x40004f09 +.set CYDEV_TMR0_RT0, 0x40004f0a +.set CYDEV_TMR0_RT1, 0x40004f0b +.set CYDEV_TMR1_BASE, 0x40004f0c +.set CYDEV_TMR1_SIZE, 0x0000000c +.set CYDEV_TMR1_CFG0, 0x40004f0c +.set CYDEV_TMR1_CFG1, 0x40004f0d +.set CYDEV_TMR1_CFG2, 0x40004f0e +.set CYDEV_TMR1_SR0, 0x40004f0f +.set CYDEV_TMR1_PER0, 0x40004f10 +.set CYDEV_TMR1_PER1, 0x40004f11 +.set CYDEV_TMR1_CNT_CMP0, 0x40004f12 +.set CYDEV_TMR1_CNT_CMP1, 0x40004f13 +.set CYDEV_TMR1_CAP0, 0x40004f14 +.set CYDEV_TMR1_CAP1, 0x40004f15 +.set CYDEV_TMR1_RT0, 0x40004f16 +.set CYDEV_TMR1_RT1, 0x40004f17 +.set CYDEV_TMR2_BASE, 0x40004f18 +.set CYDEV_TMR2_SIZE, 0x0000000c +.set CYDEV_TMR2_CFG0, 0x40004f18 +.set CYDEV_TMR2_CFG1, 0x40004f19 +.set CYDEV_TMR2_CFG2, 0x40004f1a +.set CYDEV_TMR2_SR0, 0x40004f1b +.set CYDEV_TMR2_PER0, 0x40004f1c +.set CYDEV_TMR2_PER1, 0x40004f1d +.set CYDEV_TMR2_CNT_CMP0, 0x40004f1e +.set CYDEV_TMR2_CNT_CMP1, 0x40004f1f +.set CYDEV_TMR2_CAP0, 0x40004f20 +.set CYDEV_TMR2_CAP1, 0x40004f21 +.set CYDEV_TMR2_RT0, 0x40004f22 +.set CYDEV_TMR2_RT1, 0x40004f23 +.set CYDEV_TMR3_BASE, 0x40004f24 +.set CYDEV_TMR3_SIZE, 0x0000000c +.set CYDEV_TMR3_CFG0, 0x40004f24 +.set CYDEV_TMR3_CFG1, 0x40004f25 +.set CYDEV_TMR3_CFG2, 0x40004f26 +.set CYDEV_TMR3_SR0, 0x40004f27 +.set CYDEV_TMR3_PER0, 0x40004f28 +.set CYDEV_TMR3_PER1, 0x40004f29 +.set CYDEV_TMR3_CNT_CMP0, 0x40004f2a +.set CYDEV_TMR3_CNT_CMP1, 0x40004f2b +.set CYDEV_TMR3_CAP0, 0x40004f2c +.set CYDEV_TMR3_CAP1, 0x40004f2d +.set CYDEV_TMR3_RT0, 0x40004f2e +.set CYDEV_TMR3_RT1, 0x40004f2f +.set CYDEV_IO_BASE, 0x40005000 +.set CYDEV_IO_SIZE, 0x00000200 +.set CYDEV_IO_PC_BASE, 0x40005000 +.set CYDEV_IO_PC_SIZE, 0x00000080 +.set CYDEV_IO_PC_PRT0_BASE, 0x40005000 +.set CYDEV_IO_PC_PRT0_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT0_PC0, 0x40005000 +.set CYDEV_IO_PC_PRT0_PC1, 0x40005001 +.set CYDEV_IO_PC_PRT0_PC2, 0x40005002 +.set CYDEV_IO_PC_PRT0_PC3, 0x40005003 +.set CYDEV_IO_PC_PRT0_PC4, 0x40005004 +.set CYDEV_IO_PC_PRT0_PC5, 0x40005005 +.set CYDEV_IO_PC_PRT0_PC6, 0x40005006 +.set CYDEV_IO_PC_PRT0_PC7, 0x40005007 +.set CYDEV_IO_PC_PRT1_BASE, 0x40005008 +.set CYDEV_IO_PC_PRT1_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT1_PC0, 0x40005008 +.set CYDEV_IO_PC_PRT1_PC1, 0x40005009 +.set CYDEV_IO_PC_PRT1_PC2, 0x4000500a +.set CYDEV_IO_PC_PRT1_PC3, 0x4000500b +.set CYDEV_IO_PC_PRT1_PC4, 0x4000500c +.set CYDEV_IO_PC_PRT1_PC5, 0x4000500d +.set CYDEV_IO_PC_PRT1_PC6, 0x4000500e +.set CYDEV_IO_PC_PRT1_PC7, 0x4000500f +.set CYDEV_IO_PC_PRT2_BASE, 0x40005010 +.set CYDEV_IO_PC_PRT2_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT2_PC0, 0x40005010 +.set CYDEV_IO_PC_PRT2_PC1, 0x40005011 +.set CYDEV_IO_PC_PRT2_PC2, 0x40005012 +.set CYDEV_IO_PC_PRT2_PC3, 0x40005013 +.set CYDEV_IO_PC_PRT2_PC4, 0x40005014 +.set CYDEV_IO_PC_PRT2_PC5, 0x40005015 +.set CYDEV_IO_PC_PRT2_PC6, 0x40005016 +.set CYDEV_IO_PC_PRT2_PC7, 0x40005017 +.set CYDEV_IO_PC_PRT3_BASE, 0x40005018 +.set CYDEV_IO_PC_PRT3_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT3_PC0, 0x40005018 +.set CYDEV_IO_PC_PRT3_PC1, 0x40005019 +.set CYDEV_IO_PC_PRT3_PC2, 0x4000501a +.set CYDEV_IO_PC_PRT3_PC3, 0x4000501b +.set CYDEV_IO_PC_PRT3_PC4, 0x4000501c +.set CYDEV_IO_PC_PRT3_PC5, 0x4000501d +.set CYDEV_IO_PC_PRT3_PC6, 0x4000501e +.set CYDEV_IO_PC_PRT3_PC7, 0x4000501f +.set CYDEV_IO_PC_PRT4_BASE, 0x40005020 +.set CYDEV_IO_PC_PRT4_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT4_PC0, 0x40005020 +.set CYDEV_IO_PC_PRT4_PC1, 0x40005021 +.set CYDEV_IO_PC_PRT4_PC2, 0x40005022 +.set CYDEV_IO_PC_PRT4_PC3, 0x40005023 +.set CYDEV_IO_PC_PRT4_PC4, 0x40005024 +.set CYDEV_IO_PC_PRT4_PC5, 0x40005025 +.set CYDEV_IO_PC_PRT4_PC6, 0x40005026 +.set CYDEV_IO_PC_PRT4_PC7, 0x40005027 +.set CYDEV_IO_PC_PRT5_BASE, 0x40005028 +.set CYDEV_IO_PC_PRT5_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT5_PC0, 0x40005028 +.set CYDEV_IO_PC_PRT5_PC1, 0x40005029 +.set CYDEV_IO_PC_PRT5_PC2, 0x4000502a +.set CYDEV_IO_PC_PRT5_PC3, 0x4000502b +.set CYDEV_IO_PC_PRT5_PC4, 0x4000502c +.set CYDEV_IO_PC_PRT5_PC5, 0x4000502d +.set CYDEV_IO_PC_PRT5_PC6, 0x4000502e +.set CYDEV_IO_PC_PRT5_PC7, 0x4000502f +.set CYDEV_IO_PC_PRT6_BASE, 0x40005030 +.set CYDEV_IO_PC_PRT6_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT6_PC0, 0x40005030 +.set CYDEV_IO_PC_PRT6_PC1, 0x40005031 +.set CYDEV_IO_PC_PRT6_PC2, 0x40005032 +.set CYDEV_IO_PC_PRT6_PC3, 0x40005033 +.set CYDEV_IO_PC_PRT6_PC4, 0x40005034 +.set CYDEV_IO_PC_PRT6_PC5, 0x40005035 +.set CYDEV_IO_PC_PRT6_PC6, 0x40005036 +.set CYDEV_IO_PC_PRT6_PC7, 0x40005037 +.set CYDEV_IO_PC_PRT12_BASE, 0x40005060 +.set CYDEV_IO_PC_PRT12_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT12_PC0, 0x40005060 +.set CYDEV_IO_PC_PRT12_PC1, 0x40005061 +.set CYDEV_IO_PC_PRT12_PC2, 0x40005062 +.set CYDEV_IO_PC_PRT12_PC3, 0x40005063 +.set CYDEV_IO_PC_PRT12_PC4, 0x40005064 +.set CYDEV_IO_PC_PRT12_PC5, 0x40005065 +.set CYDEV_IO_PC_PRT12_PC6, 0x40005066 +.set CYDEV_IO_PC_PRT12_PC7, 0x40005067 +.set CYDEV_IO_PC_PRT15_BASE, 0x40005078 +.set CYDEV_IO_PC_PRT15_SIZE, 0x00000006 +.set CYDEV_IO_PC_PRT15_PC0, 0x40005078 +.set CYDEV_IO_PC_PRT15_PC1, 0x40005079 +.set CYDEV_IO_PC_PRT15_PC2, 0x4000507a +.set CYDEV_IO_PC_PRT15_PC3, 0x4000507b +.set CYDEV_IO_PC_PRT15_PC4, 0x4000507c +.set CYDEV_IO_PC_PRT15_PC5, 0x4000507d +.set CYDEV_IO_PC_PRT15_7_6_BASE, 0x4000507e +.set CYDEV_IO_PC_PRT15_7_6_SIZE, 0x00000002 +.set CYDEV_IO_PC_PRT15_7_6_PC0, 0x4000507e +.set CYDEV_IO_PC_PRT15_7_6_PC1, 0x4000507f +.set CYDEV_IO_DR_BASE, 0x40005080 +.set CYDEV_IO_DR_SIZE, 0x00000010 +.set CYDEV_IO_DR_PRT0_BASE, 0x40005080 +.set CYDEV_IO_DR_PRT0_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT0_DR_ALIAS, 0x40005080 +.set CYDEV_IO_DR_PRT1_BASE, 0x40005081 +.set CYDEV_IO_DR_PRT1_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT1_DR_ALIAS, 0x40005081 +.set CYDEV_IO_DR_PRT2_BASE, 0x40005082 +.set CYDEV_IO_DR_PRT2_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT2_DR_ALIAS, 0x40005082 +.set CYDEV_IO_DR_PRT3_BASE, 0x40005083 +.set CYDEV_IO_DR_PRT3_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT3_DR_ALIAS, 0x40005083 +.set CYDEV_IO_DR_PRT4_BASE, 0x40005084 +.set CYDEV_IO_DR_PRT4_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT4_DR_ALIAS, 0x40005084 +.set CYDEV_IO_DR_PRT5_BASE, 0x40005085 +.set CYDEV_IO_DR_PRT5_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT5_DR_ALIAS, 0x40005085 +.set CYDEV_IO_DR_PRT6_BASE, 0x40005086 +.set CYDEV_IO_DR_PRT6_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT6_DR_ALIAS, 0x40005086 +.set CYDEV_IO_DR_PRT12_BASE, 0x4000508c +.set CYDEV_IO_DR_PRT12_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT12_DR_ALIAS, 0x4000508c +.set CYDEV_IO_DR_PRT15_BASE, 0x4000508f +.set CYDEV_IO_DR_PRT15_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT15_DR_15_ALIAS, 0x4000508f +.set CYDEV_IO_PS_BASE, 0x40005090 +.set CYDEV_IO_PS_SIZE, 0x00000010 +.set CYDEV_IO_PS_PRT0_BASE, 0x40005090 +.set CYDEV_IO_PS_PRT0_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT0_PS_ALIAS, 0x40005090 +.set CYDEV_IO_PS_PRT1_BASE, 0x40005091 +.set CYDEV_IO_PS_PRT1_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT1_PS_ALIAS, 0x40005091 +.set CYDEV_IO_PS_PRT2_BASE, 0x40005092 +.set CYDEV_IO_PS_PRT2_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT2_PS_ALIAS, 0x40005092 +.set CYDEV_IO_PS_PRT3_BASE, 0x40005093 +.set CYDEV_IO_PS_PRT3_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT3_PS_ALIAS, 0x40005093 +.set CYDEV_IO_PS_PRT4_BASE, 0x40005094 +.set CYDEV_IO_PS_PRT4_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT4_PS_ALIAS, 0x40005094 +.set CYDEV_IO_PS_PRT5_BASE, 0x40005095 +.set CYDEV_IO_PS_PRT5_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT5_PS_ALIAS, 0x40005095 +.set CYDEV_IO_PS_PRT6_BASE, 0x40005096 +.set CYDEV_IO_PS_PRT6_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT6_PS_ALIAS, 0x40005096 +.set CYDEV_IO_PS_PRT12_BASE, 0x4000509c +.set CYDEV_IO_PS_PRT12_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT12_PS_ALIAS, 0x4000509c +.set CYDEV_IO_PS_PRT15_BASE, 0x4000509f +.set CYDEV_IO_PS_PRT15_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT15_PS15_ALIAS, 0x4000509f +.set CYDEV_IO_PRT_BASE, 0x40005100 +.set CYDEV_IO_PRT_SIZE, 0x00000100 +.set CYDEV_IO_PRT_PRT0_BASE, 0x40005100 +.set CYDEV_IO_PRT_PRT0_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT0_DR, 0x40005100 +.set CYDEV_IO_PRT_PRT0_PS, 0x40005101 +.set CYDEV_IO_PRT_PRT0_DM0, 0x40005102 +.set CYDEV_IO_PRT_PRT0_DM1, 0x40005103 +.set CYDEV_IO_PRT_PRT0_DM2, 0x40005104 +.set CYDEV_IO_PRT_PRT0_SLW, 0x40005105 +.set CYDEV_IO_PRT_PRT0_BYP, 0x40005106 +.set CYDEV_IO_PRT_PRT0_BIE, 0x40005107 +.set CYDEV_IO_PRT_PRT0_INP_DIS, 0x40005108 +.set CYDEV_IO_PRT_PRT0_CTL, 0x40005109 +.set CYDEV_IO_PRT_PRT0_PRT, 0x4000510a +.set CYDEV_IO_PRT_PRT0_BIT_MASK, 0x4000510b +.set CYDEV_IO_PRT_PRT0_AMUX, 0x4000510c +.set CYDEV_IO_PRT_PRT0_AG, 0x4000510d +.set CYDEV_IO_PRT_PRT0_LCD_COM_SEG, 0x4000510e +.set CYDEV_IO_PRT_PRT0_LCD_EN, 0x4000510f +.set CYDEV_IO_PRT_PRT1_BASE, 0x40005110 +.set CYDEV_IO_PRT_PRT1_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT1_DR, 0x40005110 +.set CYDEV_IO_PRT_PRT1_PS, 0x40005111 +.set CYDEV_IO_PRT_PRT1_DM0, 0x40005112 +.set CYDEV_IO_PRT_PRT1_DM1, 0x40005113 +.set CYDEV_IO_PRT_PRT1_DM2, 0x40005114 +.set CYDEV_IO_PRT_PRT1_SLW, 0x40005115 +.set CYDEV_IO_PRT_PRT1_BYP, 0x40005116 +.set CYDEV_IO_PRT_PRT1_BIE, 0x40005117 +.set CYDEV_IO_PRT_PRT1_INP_DIS, 0x40005118 +.set CYDEV_IO_PRT_PRT1_CTL, 0x40005119 +.set CYDEV_IO_PRT_PRT1_PRT, 0x4000511a +.set CYDEV_IO_PRT_PRT1_BIT_MASK, 0x4000511b +.set CYDEV_IO_PRT_PRT1_AMUX, 0x4000511c +.set CYDEV_IO_PRT_PRT1_AG, 0x4000511d +.set CYDEV_IO_PRT_PRT1_LCD_COM_SEG, 0x4000511e +.set CYDEV_IO_PRT_PRT1_LCD_EN, 0x4000511f +.set CYDEV_IO_PRT_PRT2_BASE, 0x40005120 +.set CYDEV_IO_PRT_PRT2_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT2_DR, 0x40005120 +.set CYDEV_IO_PRT_PRT2_PS, 0x40005121 +.set CYDEV_IO_PRT_PRT2_DM0, 0x40005122 +.set CYDEV_IO_PRT_PRT2_DM1, 0x40005123 +.set CYDEV_IO_PRT_PRT2_DM2, 0x40005124 +.set CYDEV_IO_PRT_PRT2_SLW, 0x40005125 +.set CYDEV_IO_PRT_PRT2_BYP, 0x40005126 +.set CYDEV_IO_PRT_PRT2_BIE, 0x40005127 +.set CYDEV_IO_PRT_PRT2_INP_DIS, 0x40005128 +.set CYDEV_IO_PRT_PRT2_CTL, 0x40005129 +.set CYDEV_IO_PRT_PRT2_PRT, 0x4000512a +.set CYDEV_IO_PRT_PRT2_BIT_MASK, 0x4000512b +.set CYDEV_IO_PRT_PRT2_AMUX, 0x4000512c +.set CYDEV_IO_PRT_PRT2_AG, 0x4000512d +.set CYDEV_IO_PRT_PRT2_LCD_COM_SEG, 0x4000512e +.set CYDEV_IO_PRT_PRT2_LCD_EN, 0x4000512f +.set CYDEV_IO_PRT_PRT3_BASE, 0x40005130 +.set CYDEV_IO_PRT_PRT3_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT3_DR, 0x40005130 +.set CYDEV_IO_PRT_PRT3_PS, 0x40005131 +.set CYDEV_IO_PRT_PRT3_DM0, 0x40005132 +.set CYDEV_IO_PRT_PRT3_DM1, 0x40005133 +.set CYDEV_IO_PRT_PRT3_DM2, 0x40005134 +.set CYDEV_IO_PRT_PRT3_SLW, 0x40005135 +.set CYDEV_IO_PRT_PRT3_BYP, 0x40005136 +.set CYDEV_IO_PRT_PRT3_BIE, 0x40005137 +.set CYDEV_IO_PRT_PRT3_INP_DIS, 0x40005138 +.set CYDEV_IO_PRT_PRT3_CTL, 0x40005139 +.set CYDEV_IO_PRT_PRT3_PRT, 0x4000513a +.set CYDEV_IO_PRT_PRT3_BIT_MASK, 0x4000513b +.set CYDEV_IO_PRT_PRT3_AMUX, 0x4000513c +.set CYDEV_IO_PRT_PRT3_AG, 0x4000513d +.set CYDEV_IO_PRT_PRT3_LCD_COM_SEG, 0x4000513e +.set CYDEV_IO_PRT_PRT3_LCD_EN, 0x4000513f +.set CYDEV_IO_PRT_PRT4_BASE, 0x40005140 +.set CYDEV_IO_PRT_PRT4_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT4_DR, 0x40005140 +.set CYDEV_IO_PRT_PRT4_PS, 0x40005141 +.set CYDEV_IO_PRT_PRT4_DM0, 0x40005142 +.set CYDEV_IO_PRT_PRT4_DM1, 0x40005143 +.set CYDEV_IO_PRT_PRT4_DM2, 0x40005144 +.set CYDEV_IO_PRT_PRT4_SLW, 0x40005145 +.set CYDEV_IO_PRT_PRT4_BYP, 0x40005146 +.set CYDEV_IO_PRT_PRT4_BIE, 0x40005147 +.set CYDEV_IO_PRT_PRT4_INP_DIS, 0x40005148 +.set CYDEV_IO_PRT_PRT4_CTL, 0x40005149 +.set CYDEV_IO_PRT_PRT4_PRT, 0x4000514a +.set CYDEV_IO_PRT_PRT4_BIT_MASK, 0x4000514b +.set CYDEV_IO_PRT_PRT4_AMUX, 0x4000514c +.set CYDEV_IO_PRT_PRT4_AG, 0x4000514d +.set CYDEV_IO_PRT_PRT4_LCD_COM_SEG, 0x4000514e +.set CYDEV_IO_PRT_PRT4_LCD_EN, 0x4000514f +.set CYDEV_IO_PRT_PRT5_BASE, 0x40005150 +.set CYDEV_IO_PRT_PRT5_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT5_DR, 0x40005150 +.set CYDEV_IO_PRT_PRT5_PS, 0x40005151 +.set CYDEV_IO_PRT_PRT5_DM0, 0x40005152 +.set CYDEV_IO_PRT_PRT5_DM1, 0x40005153 +.set CYDEV_IO_PRT_PRT5_DM2, 0x40005154 +.set CYDEV_IO_PRT_PRT5_SLW, 0x40005155 +.set CYDEV_IO_PRT_PRT5_BYP, 0x40005156 +.set CYDEV_IO_PRT_PRT5_BIE, 0x40005157 +.set CYDEV_IO_PRT_PRT5_INP_DIS, 0x40005158 +.set CYDEV_IO_PRT_PRT5_CTL, 0x40005159 +.set CYDEV_IO_PRT_PRT5_PRT, 0x4000515a +.set CYDEV_IO_PRT_PRT5_BIT_MASK, 0x4000515b +.set CYDEV_IO_PRT_PRT5_AMUX, 0x4000515c +.set CYDEV_IO_PRT_PRT5_AG, 0x4000515d +.set CYDEV_IO_PRT_PRT5_LCD_COM_SEG, 0x4000515e +.set CYDEV_IO_PRT_PRT5_LCD_EN, 0x4000515f +.set CYDEV_IO_PRT_PRT6_BASE, 0x40005160 +.set CYDEV_IO_PRT_PRT6_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT6_DR, 0x40005160 +.set CYDEV_IO_PRT_PRT6_PS, 0x40005161 +.set CYDEV_IO_PRT_PRT6_DM0, 0x40005162 +.set CYDEV_IO_PRT_PRT6_DM1, 0x40005163 +.set CYDEV_IO_PRT_PRT6_DM2, 0x40005164 +.set CYDEV_IO_PRT_PRT6_SLW, 0x40005165 +.set CYDEV_IO_PRT_PRT6_BYP, 0x40005166 +.set CYDEV_IO_PRT_PRT6_BIE, 0x40005167 +.set CYDEV_IO_PRT_PRT6_INP_DIS, 0x40005168 +.set CYDEV_IO_PRT_PRT6_CTL, 0x40005169 +.set CYDEV_IO_PRT_PRT6_PRT, 0x4000516a +.set CYDEV_IO_PRT_PRT6_BIT_MASK, 0x4000516b +.set CYDEV_IO_PRT_PRT6_AMUX, 0x4000516c +.set CYDEV_IO_PRT_PRT6_AG, 0x4000516d +.set CYDEV_IO_PRT_PRT6_LCD_COM_SEG, 0x4000516e +.set CYDEV_IO_PRT_PRT6_LCD_EN, 0x4000516f +.set CYDEV_IO_PRT_PRT12_BASE, 0x400051c0 +.set CYDEV_IO_PRT_PRT12_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT12_DR, 0x400051c0 +.set CYDEV_IO_PRT_PRT12_PS, 0x400051c1 +.set CYDEV_IO_PRT_PRT12_DM0, 0x400051c2 +.set CYDEV_IO_PRT_PRT12_DM1, 0x400051c3 +.set CYDEV_IO_PRT_PRT12_DM2, 0x400051c4 +.set CYDEV_IO_PRT_PRT12_SLW, 0x400051c5 +.set CYDEV_IO_PRT_PRT12_BYP, 0x400051c6 +.set CYDEV_IO_PRT_PRT12_BIE, 0x400051c7 +.set CYDEV_IO_PRT_PRT12_INP_DIS, 0x400051c8 +.set CYDEV_IO_PRT_PRT12_SIO_HYST_EN, 0x400051c9 +.set CYDEV_IO_PRT_PRT12_PRT, 0x400051ca +.set CYDEV_IO_PRT_PRT12_BIT_MASK, 0x400051cb +.set CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ, 0x400051cc +.set CYDEV_IO_PRT_PRT12_AG, 0x400051cd +.set CYDEV_IO_PRT_PRT12_SIO_CFG, 0x400051ce +.set CYDEV_IO_PRT_PRT12_SIO_DIFF, 0x400051cf +.set CYDEV_IO_PRT_PRT15_BASE, 0x400051f0 +.set CYDEV_IO_PRT_PRT15_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT15_DR, 0x400051f0 +.set CYDEV_IO_PRT_PRT15_PS, 0x400051f1 +.set CYDEV_IO_PRT_PRT15_DM0, 0x400051f2 +.set CYDEV_IO_PRT_PRT15_DM1, 0x400051f3 +.set CYDEV_IO_PRT_PRT15_DM2, 0x400051f4 +.set CYDEV_IO_PRT_PRT15_SLW, 0x400051f5 +.set CYDEV_IO_PRT_PRT15_BYP, 0x400051f6 +.set CYDEV_IO_PRT_PRT15_BIE, 0x400051f7 +.set CYDEV_IO_PRT_PRT15_INP_DIS, 0x400051f8 +.set CYDEV_IO_PRT_PRT15_CTL, 0x400051f9 +.set CYDEV_IO_PRT_PRT15_PRT, 0x400051fa +.set CYDEV_IO_PRT_PRT15_BIT_MASK, 0x400051fb +.set CYDEV_IO_PRT_PRT15_AMUX, 0x400051fc +.set CYDEV_IO_PRT_PRT15_AG, 0x400051fd +.set CYDEV_IO_PRT_PRT15_LCD_COM_SEG, 0x400051fe +.set CYDEV_IO_PRT_PRT15_LCD_EN, 0x400051ff +.set CYDEV_PRTDSI_BASE, 0x40005200 +.set CYDEV_PRTDSI_SIZE, 0x0000007f +.set CYDEV_PRTDSI_PRT0_BASE, 0x40005200 +.set CYDEV_PRTDSI_PRT0_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT0_OUT_SEL0, 0x40005200 +.set CYDEV_PRTDSI_PRT0_OUT_SEL1, 0x40005201 +.set CYDEV_PRTDSI_PRT0_OE_SEL0, 0x40005202 +.set CYDEV_PRTDSI_PRT0_OE_SEL1, 0x40005203 +.set CYDEV_PRTDSI_PRT0_DBL_SYNC_IN, 0x40005204 +.set CYDEV_PRTDSI_PRT0_SYNC_OUT, 0x40005205 +.set CYDEV_PRTDSI_PRT0_CAPS_SEL, 0x40005206 +.set CYDEV_PRTDSI_PRT1_BASE, 0x40005208 +.set CYDEV_PRTDSI_PRT1_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT1_OUT_SEL0, 0x40005208 +.set CYDEV_PRTDSI_PRT1_OUT_SEL1, 0x40005209 +.set CYDEV_PRTDSI_PRT1_OE_SEL0, 0x4000520a +.set CYDEV_PRTDSI_PRT1_OE_SEL1, 0x4000520b +.set CYDEV_PRTDSI_PRT1_DBL_SYNC_IN, 0x4000520c +.set CYDEV_PRTDSI_PRT1_SYNC_OUT, 0x4000520d +.set CYDEV_PRTDSI_PRT1_CAPS_SEL, 0x4000520e +.set CYDEV_PRTDSI_PRT2_BASE, 0x40005210 +.set CYDEV_PRTDSI_PRT2_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT2_OUT_SEL0, 0x40005210 +.set CYDEV_PRTDSI_PRT2_OUT_SEL1, 0x40005211 +.set CYDEV_PRTDSI_PRT2_OE_SEL0, 0x40005212 +.set CYDEV_PRTDSI_PRT2_OE_SEL1, 0x40005213 +.set CYDEV_PRTDSI_PRT2_DBL_SYNC_IN, 0x40005214 +.set CYDEV_PRTDSI_PRT2_SYNC_OUT, 0x40005215 +.set CYDEV_PRTDSI_PRT2_CAPS_SEL, 0x40005216 +.set CYDEV_PRTDSI_PRT3_BASE, 0x40005218 +.set CYDEV_PRTDSI_PRT3_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT3_OUT_SEL0, 0x40005218 +.set CYDEV_PRTDSI_PRT3_OUT_SEL1, 0x40005219 +.set CYDEV_PRTDSI_PRT3_OE_SEL0, 0x4000521a +.set CYDEV_PRTDSI_PRT3_OE_SEL1, 0x4000521b +.set CYDEV_PRTDSI_PRT3_DBL_SYNC_IN, 0x4000521c +.set CYDEV_PRTDSI_PRT3_SYNC_OUT, 0x4000521d +.set CYDEV_PRTDSI_PRT3_CAPS_SEL, 0x4000521e +.set CYDEV_PRTDSI_PRT4_BASE, 0x40005220 +.set CYDEV_PRTDSI_PRT4_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT4_OUT_SEL0, 0x40005220 +.set CYDEV_PRTDSI_PRT4_OUT_SEL1, 0x40005221 +.set CYDEV_PRTDSI_PRT4_OE_SEL0, 0x40005222 +.set CYDEV_PRTDSI_PRT4_OE_SEL1, 0x40005223 +.set CYDEV_PRTDSI_PRT4_DBL_SYNC_IN, 0x40005224 +.set CYDEV_PRTDSI_PRT4_SYNC_OUT, 0x40005225 +.set CYDEV_PRTDSI_PRT4_CAPS_SEL, 0x40005226 +.set CYDEV_PRTDSI_PRT5_BASE, 0x40005228 +.set CYDEV_PRTDSI_PRT5_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT5_OUT_SEL0, 0x40005228 +.set CYDEV_PRTDSI_PRT5_OUT_SEL1, 0x40005229 +.set CYDEV_PRTDSI_PRT5_OE_SEL0, 0x4000522a +.set CYDEV_PRTDSI_PRT5_OE_SEL1, 0x4000522b +.set CYDEV_PRTDSI_PRT5_DBL_SYNC_IN, 0x4000522c +.set CYDEV_PRTDSI_PRT5_SYNC_OUT, 0x4000522d +.set CYDEV_PRTDSI_PRT5_CAPS_SEL, 0x4000522e +.set CYDEV_PRTDSI_PRT6_BASE, 0x40005230 +.set CYDEV_PRTDSI_PRT6_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT6_OUT_SEL0, 0x40005230 +.set CYDEV_PRTDSI_PRT6_OUT_SEL1, 0x40005231 +.set CYDEV_PRTDSI_PRT6_OE_SEL0, 0x40005232 +.set CYDEV_PRTDSI_PRT6_OE_SEL1, 0x40005233 +.set CYDEV_PRTDSI_PRT6_DBL_SYNC_IN, 0x40005234 +.set CYDEV_PRTDSI_PRT6_SYNC_OUT, 0x40005235 +.set CYDEV_PRTDSI_PRT6_CAPS_SEL, 0x40005236 +.set CYDEV_PRTDSI_PRT12_BASE, 0x40005260 +.set CYDEV_PRTDSI_PRT12_SIZE, 0x00000006 +.set CYDEV_PRTDSI_PRT12_OUT_SEL0, 0x40005260 +.set CYDEV_PRTDSI_PRT12_OUT_SEL1, 0x40005261 +.set CYDEV_PRTDSI_PRT12_OE_SEL0, 0x40005262 +.set CYDEV_PRTDSI_PRT12_OE_SEL1, 0x40005263 +.set CYDEV_PRTDSI_PRT12_DBL_SYNC_IN, 0x40005264 +.set CYDEV_PRTDSI_PRT12_SYNC_OUT, 0x40005265 +.set CYDEV_PRTDSI_PRT15_BASE, 0x40005278 +.set CYDEV_PRTDSI_PRT15_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT15_OUT_SEL0, 0x40005278 +.set CYDEV_PRTDSI_PRT15_OUT_SEL1, 0x40005279 +.set CYDEV_PRTDSI_PRT15_OE_SEL0, 0x4000527a +.set CYDEV_PRTDSI_PRT15_OE_SEL1, 0x4000527b +.set CYDEV_PRTDSI_PRT15_DBL_SYNC_IN, 0x4000527c +.set CYDEV_PRTDSI_PRT15_SYNC_OUT, 0x4000527d +.set CYDEV_PRTDSI_PRT15_CAPS_SEL, 0x4000527e +.set CYDEV_EMIF_BASE, 0x40005400 +.set CYDEV_EMIF_SIZE, 0x00000007 +.set CYDEV_EMIF_NO_UDB, 0x40005400 +.set CYDEV_EMIF_RP_WAIT_STATES, 0x40005401 +.set CYDEV_EMIF_MEM_DWN, 0x40005402 +.set CYDEV_EMIF_MEMCLK_DIV, 0x40005403 +.set CYDEV_EMIF_CLOCK_EN, 0x40005404 +.set CYDEV_EMIF_EM_TYPE, 0x40005405 +.set CYDEV_EMIF_WP_WAIT_STATES, 0x40005406 +.set CYDEV_ANAIF_BASE, 0x40005800 +.set CYDEV_ANAIF_SIZE, 0x000003a9 +.set CYDEV_ANAIF_CFG_BASE, 0x40005800 +.set CYDEV_ANAIF_CFG_SIZE, 0x0000010f +.set CYDEV_ANAIF_CFG_SC0_BASE, 0x40005800 +.set CYDEV_ANAIF_CFG_SC0_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_SC0_CR0, 0x40005800 +.set CYDEV_ANAIF_CFG_SC0_CR1, 0x40005801 +.set CYDEV_ANAIF_CFG_SC0_CR2, 0x40005802 +.set CYDEV_ANAIF_CFG_SC1_BASE, 0x40005804 +.set CYDEV_ANAIF_CFG_SC1_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_SC1_CR0, 0x40005804 +.set CYDEV_ANAIF_CFG_SC1_CR1, 0x40005805 +.set CYDEV_ANAIF_CFG_SC1_CR2, 0x40005806 +.set CYDEV_ANAIF_CFG_SC2_BASE, 0x40005808 +.set CYDEV_ANAIF_CFG_SC2_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_SC2_CR0, 0x40005808 +.set CYDEV_ANAIF_CFG_SC2_CR1, 0x40005809 +.set CYDEV_ANAIF_CFG_SC2_CR2, 0x4000580a +.set CYDEV_ANAIF_CFG_SC3_BASE, 0x4000580c +.set CYDEV_ANAIF_CFG_SC3_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_SC3_CR0, 0x4000580c +.set CYDEV_ANAIF_CFG_SC3_CR1, 0x4000580d +.set CYDEV_ANAIF_CFG_SC3_CR2, 0x4000580e +.set CYDEV_ANAIF_CFG_DAC0_BASE, 0x40005820 +.set CYDEV_ANAIF_CFG_DAC0_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_DAC0_CR0, 0x40005820 +.set CYDEV_ANAIF_CFG_DAC0_CR1, 0x40005821 +.set CYDEV_ANAIF_CFG_DAC0_TST, 0x40005822 +.set CYDEV_ANAIF_CFG_DAC1_BASE, 0x40005824 +.set CYDEV_ANAIF_CFG_DAC1_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_DAC1_CR0, 0x40005824 +.set CYDEV_ANAIF_CFG_DAC1_CR1, 0x40005825 +.set CYDEV_ANAIF_CFG_DAC1_TST, 0x40005826 +.set CYDEV_ANAIF_CFG_DAC2_BASE, 0x40005828 +.set CYDEV_ANAIF_CFG_DAC2_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_DAC2_CR0, 0x40005828 +.set CYDEV_ANAIF_CFG_DAC2_CR1, 0x40005829 +.set CYDEV_ANAIF_CFG_DAC2_TST, 0x4000582a +.set CYDEV_ANAIF_CFG_DAC3_BASE, 0x4000582c +.set CYDEV_ANAIF_CFG_DAC3_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_DAC3_CR0, 0x4000582c +.set CYDEV_ANAIF_CFG_DAC3_CR1, 0x4000582d +.set CYDEV_ANAIF_CFG_DAC3_TST, 0x4000582e +.set CYDEV_ANAIF_CFG_CMP0_BASE, 0x40005840 +.set CYDEV_ANAIF_CFG_CMP0_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_CMP0_CR, 0x40005840 +.set CYDEV_ANAIF_CFG_CMP1_BASE, 0x40005841 +.set CYDEV_ANAIF_CFG_CMP1_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_CMP1_CR, 0x40005841 +.set CYDEV_ANAIF_CFG_CMP2_BASE, 0x40005842 +.set CYDEV_ANAIF_CFG_CMP2_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_CMP2_CR, 0x40005842 +.set CYDEV_ANAIF_CFG_CMP3_BASE, 0x40005843 +.set CYDEV_ANAIF_CFG_CMP3_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_CMP3_CR, 0x40005843 +.set CYDEV_ANAIF_CFG_LUT0_BASE, 0x40005848 +.set CYDEV_ANAIF_CFG_LUT0_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LUT0_CR, 0x40005848 +.set CYDEV_ANAIF_CFG_LUT0_MX, 0x40005849 +.set CYDEV_ANAIF_CFG_LUT1_BASE, 0x4000584a +.set CYDEV_ANAIF_CFG_LUT1_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LUT1_CR, 0x4000584a +.set CYDEV_ANAIF_CFG_LUT1_MX, 0x4000584b +.set CYDEV_ANAIF_CFG_LUT2_BASE, 0x4000584c +.set CYDEV_ANAIF_CFG_LUT2_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LUT2_CR, 0x4000584c +.set CYDEV_ANAIF_CFG_LUT2_MX, 0x4000584d +.set CYDEV_ANAIF_CFG_LUT3_BASE, 0x4000584e +.set CYDEV_ANAIF_CFG_LUT3_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LUT3_CR, 0x4000584e +.set CYDEV_ANAIF_CFG_LUT3_MX, 0x4000584f +.set CYDEV_ANAIF_CFG_OPAMP0_BASE, 0x40005858 +.set CYDEV_ANAIF_CFG_OPAMP0_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_OPAMP0_CR, 0x40005858 +.set CYDEV_ANAIF_CFG_OPAMP0_RSVD, 0x40005859 +.set CYDEV_ANAIF_CFG_OPAMP1_BASE, 0x4000585a +.set CYDEV_ANAIF_CFG_OPAMP1_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_OPAMP1_CR, 0x4000585a +.set CYDEV_ANAIF_CFG_OPAMP1_RSVD, 0x4000585b +.set CYDEV_ANAIF_CFG_OPAMP2_BASE, 0x4000585c +.set CYDEV_ANAIF_CFG_OPAMP2_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_OPAMP2_CR, 0x4000585c +.set CYDEV_ANAIF_CFG_OPAMP2_RSVD, 0x4000585d +.set CYDEV_ANAIF_CFG_OPAMP3_BASE, 0x4000585e +.set CYDEV_ANAIF_CFG_OPAMP3_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_OPAMP3_CR, 0x4000585e +.set CYDEV_ANAIF_CFG_OPAMP3_RSVD, 0x4000585f +.set CYDEV_ANAIF_CFG_LCDDAC_BASE, 0x40005868 +.set CYDEV_ANAIF_CFG_LCDDAC_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LCDDAC_CR0, 0x40005868 +.set CYDEV_ANAIF_CFG_LCDDAC_CR1, 0x40005869 +.set CYDEV_ANAIF_CFG_LCDDRV_BASE, 0x4000586a +.set CYDEV_ANAIF_CFG_LCDDRV_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_LCDDRV_CR, 0x4000586a +.set CYDEV_ANAIF_CFG_LCDTMR_BASE, 0x4000586b +.set CYDEV_ANAIF_CFG_LCDTMR_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_LCDTMR_CFG, 0x4000586b +.set CYDEV_ANAIF_CFG_BG_BASE, 0x4000586c +.set CYDEV_ANAIF_CFG_BG_SIZE, 0x00000004 +.set CYDEV_ANAIF_CFG_BG_CR0, 0x4000586c +.set CYDEV_ANAIF_CFG_BG_RSVD, 0x4000586d +.set CYDEV_ANAIF_CFG_BG_DFT0, 0x4000586e +.set CYDEV_ANAIF_CFG_BG_DFT1, 0x4000586f +.set CYDEV_ANAIF_CFG_CAPSL_BASE, 0x40005870 +.set CYDEV_ANAIF_CFG_CAPSL_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_CAPSL_CFG0, 0x40005870 +.set CYDEV_ANAIF_CFG_CAPSL_CFG1, 0x40005871 +.set CYDEV_ANAIF_CFG_CAPSR_BASE, 0x40005872 +.set CYDEV_ANAIF_CFG_CAPSR_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_CAPSR_CFG0, 0x40005872 +.set CYDEV_ANAIF_CFG_CAPSR_CFG1, 0x40005873 +.set CYDEV_ANAIF_CFG_PUMP_BASE, 0x40005876 +.set CYDEV_ANAIF_CFG_PUMP_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_PUMP_CR0, 0x40005876 +.set CYDEV_ANAIF_CFG_PUMP_CR1, 0x40005877 +.set CYDEV_ANAIF_CFG_LPF0_BASE, 0x40005878 +.set CYDEV_ANAIF_CFG_LPF0_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LPF0_CR0, 0x40005878 +.set CYDEV_ANAIF_CFG_LPF0_RSVD, 0x40005879 +.set CYDEV_ANAIF_CFG_LPF1_BASE, 0x4000587a +.set CYDEV_ANAIF_CFG_LPF1_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LPF1_CR0, 0x4000587a +.set CYDEV_ANAIF_CFG_LPF1_RSVD, 0x4000587b +.set CYDEV_ANAIF_CFG_MISC_BASE, 0x4000587c +.set CYDEV_ANAIF_CFG_MISC_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_MISC_CR0, 0x4000587c +.set CYDEV_ANAIF_CFG_DSM0_BASE, 0x40005880 +.set CYDEV_ANAIF_CFG_DSM0_SIZE, 0x00000020 +.set CYDEV_ANAIF_CFG_DSM0_CR0, 0x40005880 +.set CYDEV_ANAIF_CFG_DSM0_CR1, 0x40005881 +.set CYDEV_ANAIF_CFG_DSM0_CR2, 0x40005882 +.set CYDEV_ANAIF_CFG_DSM0_CR3, 0x40005883 +.set CYDEV_ANAIF_CFG_DSM0_CR4, 0x40005884 +.set CYDEV_ANAIF_CFG_DSM0_CR5, 0x40005885 +.set CYDEV_ANAIF_CFG_DSM0_CR6, 0x40005886 +.set CYDEV_ANAIF_CFG_DSM0_CR7, 0x40005887 +.set CYDEV_ANAIF_CFG_DSM0_CR8, 0x40005888 +.set CYDEV_ANAIF_CFG_DSM0_CR9, 0x40005889 +.set CYDEV_ANAIF_CFG_DSM0_CR10, 0x4000588a +.set CYDEV_ANAIF_CFG_DSM0_CR11, 0x4000588b +.set CYDEV_ANAIF_CFG_DSM0_CR12, 0x4000588c +.set CYDEV_ANAIF_CFG_DSM0_CR13, 0x4000588d +.set CYDEV_ANAIF_CFG_DSM0_CR14, 0x4000588e +.set CYDEV_ANAIF_CFG_DSM0_CR15, 0x4000588f +.set CYDEV_ANAIF_CFG_DSM0_CR16, 0x40005890 +.set CYDEV_ANAIF_CFG_DSM0_CR17, 0x40005891 +.set CYDEV_ANAIF_CFG_DSM0_REF0, 0x40005892 +.set CYDEV_ANAIF_CFG_DSM0_REF1, 0x40005893 +.set CYDEV_ANAIF_CFG_DSM0_REF2, 0x40005894 +.set CYDEV_ANAIF_CFG_DSM0_REF3, 0x40005895 +.set CYDEV_ANAIF_CFG_DSM0_DEM0, 0x40005896 +.set CYDEV_ANAIF_CFG_DSM0_DEM1, 0x40005897 +.set CYDEV_ANAIF_CFG_DSM0_TST0, 0x40005898 +.set CYDEV_ANAIF_CFG_DSM0_TST1, 0x40005899 +.set CYDEV_ANAIF_CFG_DSM0_BUF0, 0x4000589a +.set CYDEV_ANAIF_CFG_DSM0_BUF1, 0x4000589b +.set CYDEV_ANAIF_CFG_DSM0_BUF2, 0x4000589c +.set CYDEV_ANAIF_CFG_DSM0_BUF3, 0x4000589d +.set CYDEV_ANAIF_CFG_DSM0_MISC, 0x4000589e +.set CYDEV_ANAIF_CFG_DSM0_RSVD1, 0x4000589f +.set CYDEV_ANAIF_CFG_SAR0_BASE, 0x40005900 +.set CYDEV_ANAIF_CFG_SAR0_SIZE, 0x00000007 +.set CYDEV_ANAIF_CFG_SAR0_CSR0, 0x40005900 +.set CYDEV_ANAIF_CFG_SAR0_CSR1, 0x40005901 +.set CYDEV_ANAIF_CFG_SAR0_CSR2, 0x40005902 +.set CYDEV_ANAIF_CFG_SAR0_CSR3, 0x40005903 +.set CYDEV_ANAIF_CFG_SAR0_CSR4, 0x40005904 +.set CYDEV_ANAIF_CFG_SAR0_CSR5, 0x40005905 +.set CYDEV_ANAIF_CFG_SAR0_CSR6, 0x40005906 +.set CYDEV_ANAIF_CFG_SAR1_BASE, 0x40005908 +.set CYDEV_ANAIF_CFG_SAR1_SIZE, 0x00000007 +.set CYDEV_ANAIF_CFG_SAR1_CSR0, 0x40005908 +.set CYDEV_ANAIF_CFG_SAR1_CSR1, 0x40005909 +.set CYDEV_ANAIF_CFG_SAR1_CSR2, 0x4000590a +.set CYDEV_ANAIF_CFG_SAR1_CSR3, 0x4000590b +.set CYDEV_ANAIF_CFG_SAR1_CSR4, 0x4000590c +.set CYDEV_ANAIF_CFG_SAR1_CSR5, 0x4000590d +.set CYDEV_ANAIF_CFG_SAR1_CSR6, 0x4000590e +.set CYDEV_ANAIF_RT_BASE, 0x40005a00 +.set CYDEV_ANAIF_RT_SIZE, 0x00000162 +.set CYDEV_ANAIF_RT_SC0_BASE, 0x40005a00 +.set CYDEV_ANAIF_RT_SC0_SIZE, 0x0000000d +.set CYDEV_ANAIF_RT_SC0_SW0, 0x40005a00 +.set CYDEV_ANAIF_RT_SC0_SW2, 0x40005a02 +.set CYDEV_ANAIF_RT_SC0_SW3, 0x40005a03 +.set CYDEV_ANAIF_RT_SC0_SW4, 0x40005a04 +.set CYDEV_ANAIF_RT_SC0_SW6, 0x40005a06 +.set CYDEV_ANAIF_RT_SC0_SW7, 0x40005a07 +.set CYDEV_ANAIF_RT_SC0_SW8, 0x40005a08 +.set CYDEV_ANAIF_RT_SC0_SW10, 0x40005a0a +.set CYDEV_ANAIF_RT_SC0_CLK, 0x40005a0b +.set CYDEV_ANAIF_RT_SC0_BST, 0x40005a0c +.set CYDEV_ANAIF_RT_SC1_BASE, 0x40005a10 +.set CYDEV_ANAIF_RT_SC1_SIZE, 0x0000000d +.set CYDEV_ANAIF_RT_SC1_SW0, 0x40005a10 +.set CYDEV_ANAIF_RT_SC1_SW2, 0x40005a12 +.set CYDEV_ANAIF_RT_SC1_SW3, 0x40005a13 +.set CYDEV_ANAIF_RT_SC1_SW4, 0x40005a14 +.set CYDEV_ANAIF_RT_SC1_SW6, 0x40005a16 +.set CYDEV_ANAIF_RT_SC1_SW7, 0x40005a17 +.set CYDEV_ANAIF_RT_SC1_SW8, 0x40005a18 +.set CYDEV_ANAIF_RT_SC1_SW10, 0x40005a1a +.set CYDEV_ANAIF_RT_SC1_CLK, 0x40005a1b +.set CYDEV_ANAIF_RT_SC1_BST, 0x40005a1c +.set CYDEV_ANAIF_RT_SC2_BASE, 0x40005a20 +.set CYDEV_ANAIF_RT_SC2_SIZE, 0x0000000d +.set CYDEV_ANAIF_RT_SC2_SW0, 0x40005a20 +.set CYDEV_ANAIF_RT_SC2_SW2, 0x40005a22 +.set CYDEV_ANAIF_RT_SC2_SW3, 0x40005a23 +.set CYDEV_ANAIF_RT_SC2_SW4, 0x40005a24 +.set CYDEV_ANAIF_RT_SC2_SW6, 0x40005a26 +.set CYDEV_ANAIF_RT_SC2_SW7, 0x40005a27 +.set CYDEV_ANAIF_RT_SC2_SW8, 0x40005a28 +.set CYDEV_ANAIF_RT_SC2_SW10, 0x40005a2a +.set CYDEV_ANAIF_RT_SC2_CLK, 0x40005a2b +.set CYDEV_ANAIF_RT_SC2_BST, 0x40005a2c +.set CYDEV_ANAIF_RT_SC3_BASE, 0x40005a30 +.set CYDEV_ANAIF_RT_SC3_SIZE, 0x0000000d +.set CYDEV_ANAIF_RT_SC3_SW0, 0x40005a30 +.set CYDEV_ANAIF_RT_SC3_SW2, 0x40005a32 +.set CYDEV_ANAIF_RT_SC3_SW3, 0x40005a33 +.set CYDEV_ANAIF_RT_SC3_SW4, 0x40005a34 +.set CYDEV_ANAIF_RT_SC3_SW6, 0x40005a36 +.set CYDEV_ANAIF_RT_SC3_SW7, 0x40005a37 +.set CYDEV_ANAIF_RT_SC3_SW8, 0x40005a38 +.set CYDEV_ANAIF_RT_SC3_SW10, 0x40005a3a +.set CYDEV_ANAIF_RT_SC3_CLK, 0x40005a3b +.set CYDEV_ANAIF_RT_SC3_BST, 0x40005a3c +.set CYDEV_ANAIF_RT_DAC0_BASE, 0x40005a80 +.set CYDEV_ANAIF_RT_DAC0_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_DAC0_SW0, 0x40005a80 +.set CYDEV_ANAIF_RT_DAC0_SW2, 0x40005a82 +.set CYDEV_ANAIF_RT_DAC0_SW3, 0x40005a83 +.set CYDEV_ANAIF_RT_DAC0_SW4, 0x40005a84 +.set CYDEV_ANAIF_RT_DAC0_STROBE, 0x40005a87 +.set CYDEV_ANAIF_RT_DAC1_BASE, 0x40005a88 +.set CYDEV_ANAIF_RT_DAC1_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_DAC1_SW0, 0x40005a88 +.set CYDEV_ANAIF_RT_DAC1_SW2, 0x40005a8a +.set CYDEV_ANAIF_RT_DAC1_SW3, 0x40005a8b +.set CYDEV_ANAIF_RT_DAC1_SW4, 0x40005a8c +.set CYDEV_ANAIF_RT_DAC1_STROBE, 0x40005a8f +.set CYDEV_ANAIF_RT_DAC2_BASE, 0x40005a90 +.set CYDEV_ANAIF_RT_DAC2_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_DAC2_SW0, 0x40005a90 +.set CYDEV_ANAIF_RT_DAC2_SW2, 0x40005a92 +.set CYDEV_ANAIF_RT_DAC2_SW3, 0x40005a93 +.set CYDEV_ANAIF_RT_DAC2_SW4, 0x40005a94 +.set CYDEV_ANAIF_RT_DAC2_STROBE, 0x40005a97 +.set CYDEV_ANAIF_RT_DAC3_BASE, 0x40005a98 +.set CYDEV_ANAIF_RT_DAC3_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_DAC3_SW0, 0x40005a98 +.set CYDEV_ANAIF_RT_DAC3_SW2, 0x40005a9a +.set CYDEV_ANAIF_RT_DAC3_SW3, 0x40005a9b +.set CYDEV_ANAIF_RT_DAC3_SW4, 0x40005a9c +.set CYDEV_ANAIF_RT_DAC3_STROBE, 0x40005a9f +.set CYDEV_ANAIF_RT_CMP0_BASE, 0x40005ac0 +.set CYDEV_ANAIF_RT_CMP0_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_CMP0_SW0, 0x40005ac0 +.set CYDEV_ANAIF_RT_CMP0_SW2, 0x40005ac2 +.set CYDEV_ANAIF_RT_CMP0_SW3, 0x40005ac3 +.set CYDEV_ANAIF_RT_CMP0_SW4, 0x40005ac4 +.set CYDEV_ANAIF_RT_CMP0_SW6, 0x40005ac6 +.set CYDEV_ANAIF_RT_CMP0_CLK, 0x40005ac7 +.set CYDEV_ANAIF_RT_CMP1_BASE, 0x40005ac8 +.set CYDEV_ANAIF_RT_CMP1_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_CMP1_SW0, 0x40005ac8 +.set CYDEV_ANAIF_RT_CMP1_SW2, 0x40005aca +.set CYDEV_ANAIF_RT_CMP1_SW3, 0x40005acb +.set CYDEV_ANAIF_RT_CMP1_SW4, 0x40005acc +.set CYDEV_ANAIF_RT_CMP1_SW6, 0x40005ace +.set CYDEV_ANAIF_RT_CMP1_CLK, 0x40005acf +.set CYDEV_ANAIF_RT_CMP2_BASE, 0x40005ad0 +.set CYDEV_ANAIF_RT_CMP2_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_CMP2_SW0, 0x40005ad0 +.set CYDEV_ANAIF_RT_CMP2_SW2, 0x40005ad2 +.set CYDEV_ANAIF_RT_CMP2_SW3, 0x40005ad3 +.set CYDEV_ANAIF_RT_CMP2_SW4, 0x40005ad4 +.set CYDEV_ANAIF_RT_CMP2_SW6, 0x40005ad6 +.set CYDEV_ANAIF_RT_CMP2_CLK, 0x40005ad7 +.set CYDEV_ANAIF_RT_CMP3_BASE, 0x40005ad8 +.set CYDEV_ANAIF_RT_CMP3_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_CMP3_SW0, 0x40005ad8 +.set CYDEV_ANAIF_RT_CMP3_SW2, 0x40005ada +.set CYDEV_ANAIF_RT_CMP3_SW3, 0x40005adb +.set CYDEV_ANAIF_RT_CMP3_SW4, 0x40005adc +.set CYDEV_ANAIF_RT_CMP3_SW6, 0x40005ade +.set CYDEV_ANAIF_RT_CMP3_CLK, 0x40005adf +.set CYDEV_ANAIF_RT_DSM0_BASE, 0x40005b00 +.set CYDEV_ANAIF_RT_DSM0_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_DSM0_SW0, 0x40005b00 +.set CYDEV_ANAIF_RT_DSM0_SW2, 0x40005b02 +.set CYDEV_ANAIF_RT_DSM0_SW3, 0x40005b03 +.set CYDEV_ANAIF_RT_DSM0_SW4, 0x40005b04 +.set CYDEV_ANAIF_RT_DSM0_SW6, 0x40005b06 +.set CYDEV_ANAIF_RT_DSM0_CLK, 0x40005b07 +.set CYDEV_ANAIF_RT_SAR0_BASE, 0x40005b20 +.set CYDEV_ANAIF_RT_SAR0_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_SAR0_SW0, 0x40005b20 +.set CYDEV_ANAIF_RT_SAR0_SW2, 0x40005b22 +.set CYDEV_ANAIF_RT_SAR0_SW3, 0x40005b23 +.set CYDEV_ANAIF_RT_SAR0_SW4, 0x40005b24 +.set CYDEV_ANAIF_RT_SAR0_SW6, 0x40005b26 +.set CYDEV_ANAIF_RT_SAR0_CLK, 0x40005b27 +.set CYDEV_ANAIF_RT_SAR1_BASE, 0x40005b28 +.set CYDEV_ANAIF_RT_SAR1_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_SAR1_SW0, 0x40005b28 +.set CYDEV_ANAIF_RT_SAR1_SW2, 0x40005b2a +.set CYDEV_ANAIF_RT_SAR1_SW3, 0x40005b2b +.set CYDEV_ANAIF_RT_SAR1_SW4, 0x40005b2c +.set CYDEV_ANAIF_RT_SAR1_SW6, 0x40005b2e +.set CYDEV_ANAIF_RT_SAR1_CLK, 0x40005b2f +.set CYDEV_ANAIF_RT_OPAMP0_BASE, 0x40005b40 +.set CYDEV_ANAIF_RT_OPAMP0_SIZE, 0x00000002 +.set CYDEV_ANAIF_RT_OPAMP0_MX, 0x40005b40 +.set CYDEV_ANAIF_RT_OPAMP0_SW, 0x40005b41 +.set CYDEV_ANAIF_RT_OPAMP1_BASE, 0x40005b42 +.set CYDEV_ANAIF_RT_OPAMP1_SIZE, 0x00000002 +.set CYDEV_ANAIF_RT_OPAMP1_MX, 0x40005b42 +.set CYDEV_ANAIF_RT_OPAMP1_SW, 0x40005b43 +.set CYDEV_ANAIF_RT_OPAMP2_BASE, 0x40005b44 +.set CYDEV_ANAIF_RT_OPAMP2_SIZE, 0x00000002 +.set CYDEV_ANAIF_RT_OPAMP2_MX, 0x40005b44 +.set CYDEV_ANAIF_RT_OPAMP2_SW, 0x40005b45 +.set CYDEV_ANAIF_RT_OPAMP3_BASE, 0x40005b46 +.set CYDEV_ANAIF_RT_OPAMP3_SIZE, 0x00000002 +.set CYDEV_ANAIF_RT_OPAMP3_MX, 0x40005b46 +.set CYDEV_ANAIF_RT_OPAMP3_SW, 0x40005b47 +.set CYDEV_ANAIF_RT_LCDDAC_BASE, 0x40005b50 +.set CYDEV_ANAIF_RT_LCDDAC_SIZE, 0x00000005 +.set CYDEV_ANAIF_RT_LCDDAC_SW0, 0x40005b50 +.set CYDEV_ANAIF_RT_LCDDAC_SW1, 0x40005b51 +.set CYDEV_ANAIF_RT_LCDDAC_SW2, 0x40005b52 +.set CYDEV_ANAIF_RT_LCDDAC_SW3, 0x40005b53 +.set CYDEV_ANAIF_RT_LCDDAC_SW4, 0x40005b54 +.set CYDEV_ANAIF_RT_SC_BASE, 0x40005b56 +.set CYDEV_ANAIF_RT_SC_SIZE, 0x00000001 +.set CYDEV_ANAIF_RT_SC_MISC, 0x40005b56 +.set CYDEV_ANAIF_RT_BUS_BASE, 0x40005b58 +.set CYDEV_ANAIF_RT_BUS_SIZE, 0x00000004 +.set CYDEV_ANAIF_RT_BUS_SW0, 0x40005b58 +.set CYDEV_ANAIF_RT_BUS_SW2, 0x40005b5a +.set CYDEV_ANAIF_RT_BUS_SW3, 0x40005b5b +.set CYDEV_ANAIF_RT_DFT_BASE, 0x40005b5c +.set CYDEV_ANAIF_RT_DFT_SIZE, 0x00000006 +.set CYDEV_ANAIF_RT_DFT_CR0, 0x40005b5c +.set CYDEV_ANAIF_RT_DFT_CR1, 0x40005b5d +.set CYDEV_ANAIF_RT_DFT_CR2, 0x40005b5e +.set CYDEV_ANAIF_RT_DFT_CR3, 0x40005b5f +.set CYDEV_ANAIF_RT_DFT_CR4, 0x40005b60 +.set CYDEV_ANAIF_RT_DFT_CR5, 0x40005b61 +.set CYDEV_ANAIF_WRK_BASE, 0x40005b80 +.set CYDEV_ANAIF_WRK_SIZE, 0x00000029 +.set CYDEV_ANAIF_WRK_DAC0_BASE, 0x40005b80 +.set CYDEV_ANAIF_WRK_DAC0_SIZE, 0x00000001 +.set CYDEV_ANAIF_WRK_DAC0_D, 0x40005b80 +.set CYDEV_ANAIF_WRK_DAC1_BASE, 0x40005b81 +.set CYDEV_ANAIF_WRK_DAC1_SIZE, 0x00000001 +.set CYDEV_ANAIF_WRK_DAC1_D, 0x40005b81 +.set CYDEV_ANAIF_WRK_DAC2_BASE, 0x40005b82 +.set CYDEV_ANAIF_WRK_DAC2_SIZE, 0x00000001 +.set CYDEV_ANAIF_WRK_DAC2_D, 0x40005b82 +.set CYDEV_ANAIF_WRK_DAC3_BASE, 0x40005b83 +.set CYDEV_ANAIF_WRK_DAC3_SIZE, 0x00000001 +.set CYDEV_ANAIF_WRK_DAC3_D, 0x40005b83 +.set CYDEV_ANAIF_WRK_DSM0_BASE, 0x40005b88 +.set CYDEV_ANAIF_WRK_DSM0_SIZE, 0x00000002 +.set CYDEV_ANAIF_WRK_DSM0_OUT0, 0x40005b88 +.set CYDEV_ANAIF_WRK_DSM0_OUT1, 0x40005b89 +.set CYDEV_ANAIF_WRK_LUT_BASE, 0x40005b90 +.set CYDEV_ANAIF_WRK_LUT_SIZE, 0x00000005 +.set CYDEV_ANAIF_WRK_LUT_SR, 0x40005b90 +.set CYDEV_ANAIF_WRK_LUT_WRK1, 0x40005b91 +.set CYDEV_ANAIF_WRK_LUT_MSK, 0x40005b92 +.set CYDEV_ANAIF_WRK_LUT_CLK, 0x40005b93 +.set CYDEV_ANAIF_WRK_LUT_CPTR, 0x40005b94 +.set CYDEV_ANAIF_WRK_CMP_BASE, 0x40005b96 +.set CYDEV_ANAIF_WRK_CMP_SIZE, 0x00000002 +.set CYDEV_ANAIF_WRK_CMP_WRK, 0x40005b96 +.set CYDEV_ANAIF_WRK_CMP_TST, 0x40005b97 +.set CYDEV_ANAIF_WRK_SC_BASE, 0x40005b98 +.set CYDEV_ANAIF_WRK_SC_SIZE, 0x00000005 +.set CYDEV_ANAIF_WRK_SC_SR, 0x40005b98 +.set CYDEV_ANAIF_WRK_SC_WRK1, 0x40005b99 +.set CYDEV_ANAIF_WRK_SC_MSK, 0x40005b9a +.set CYDEV_ANAIF_WRK_SC_CMPINV, 0x40005b9b +.set CYDEV_ANAIF_WRK_SC_CPTR, 0x40005b9c +.set CYDEV_ANAIF_WRK_SAR0_BASE, 0x40005ba0 +.set CYDEV_ANAIF_WRK_SAR0_SIZE, 0x00000002 +.set CYDEV_ANAIF_WRK_SAR0_WRK0, 0x40005ba0 +.set CYDEV_ANAIF_WRK_SAR0_WRK1, 0x40005ba1 +.set CYDEV_ANAIF_WRK_SAR1_BASE, 0x40005ba2 +.set CYDEV_ANAIF_WRK_SAR1_SIZE, 0x00000002 +.set CYDEV_ANAIF_WRK_SAR1_WRK0, 0x40005ba2 +.set CYDEV_ANAIF_WRK_SAR1_WRK1, 0x40005ba3 +.set CYDEV_ANAIF_WRK_SARS_BASE, 0x40005ba8 +.set CYDEV_ANAIF_WRK_SARS_SIZE, 0x00000001 +.set CYDEV_ANAIF_WRK_SARS_SOF, 0x40005ba8 +.set CYDEV_USB_BASE, 0x40006000 +.set CYDEV_USB_SIZE, 0x00000300 +.set CYDEV_USB_EP0_DR0, 0x40006000 +.set CYDEV_USB_EP0_DR1, 0x40006001 +.set CYDEV_USB_EP0_DR2, 0x40006002 +.set CYDEV_USB_EP0_DR3, 0x40006003 +.set CYDEV_USB_EP0_DR4, 0x40006004 +.set CYDEV_USB_EP0_DR5, 0x40006005 +.set CYDEV_USB_EP0_DR6, 0x40006006 +.set CYDEV_USB_EP0_DR7, 0x40006007 +.set CYDEV_USB_CR0, 0x40006008 +.set CYDEV_USB_CR1, 0x40006009 +.set CYDEV_USB_SIE_EP_INT_EN, 0x4000600a +.set CYDEV_USB_SIE_EP_INT_SR, 0x4000600b +.set CYDEV_USB_SIE_EP1_BASE, 0x4000600c +.set CYDEV_USB_SIE_EP1_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP1_CNT0, 0x4000600c +.set CYDEV_USB_SIE_EP1_CNT1, 0x4000600d +.set CYDEV_USB_SIE_EP1_CR0, 0x4000600e +.set CYDEV_USB_USBIO_CR0, 0x40006010 +.set CYDEV_USB_USBIO_CR1, 0x40006012 +.set CYDEV_USB_DYN_RECONFIG, 0x40006014 +.set CYDEV_USB_SOF0, 0x40006018 +.set CYDEV_USB_SOF1, 0x40006019 +.set CYDEV_USB_SIE_EP2_BASE, 0x4000601c +.set CYDEV_USB_SIE_EP2_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP2_CNT0, 0x4000601c +.set CYDEV_USB_SIE_EP2_CNT1, 0x4000601d +.set CYDEV_USB_SIE_EP2_CR0, 0x4000601e +.set CYDEV_USB_EP0_CR, 0x40006028 +.set CYDEV_USB_EP0_CNT, 0x40006029 +.set CYDEV_USB_SIE_EP3_BASE, 0x4000602c +.set CYDEV_USB_SIE_EP3_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP3_CNT0, 0x4000602c +.set CYDEV_USB_SIE_EP3_CNT1, 0x4000602d +.set CYDEV_USB_SIE_EP3_CR0, 0x4000602e +.set CYDEV_USB_SIE_EP4_BASE, 0x4000603c +.set CYDEV_USB_SIE_EP4_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP4_CNT0, 0x4000603c +.set CYDEV_USB_SIE_EP4_CNT1, 0x4000603d +.set CYDEV_USB_SIE_EP4_CR0, 0x4000603e +.set CYDEV_USB_SIE_EP5_BASE, 0x4000604c +.set CYDEV_USB_SIE_EP5_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP5_CNT0, 0x4000604c +.set CYDEV_USB_SIE_EP5_CNT1, 0x4000604d +.set CYDEV_USB_SIE_EP5_CR0, 0x4000604e +.set CYDEV_USB_SIE_EP6_BASE, 0x4000605c +.set CYDEV_USB_SIE_EP6_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP6_CNT0, 0x4000605c +.set CYDEV_USB_SIE_EP6_CNT1, 0x4000605d +.set CYDEV_USB_SIE_EP6_CR0, 0x4000605e +.set CYDEV_USB_SIE_EP7_BASE, 0x4000606c +.set CYDEV_USB_SIE_EP7_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP7_CNT0, 0x4000606c +.set CYDEV_USB_SIE_EP7_CNT1, 0x4000606d +.set CYDEV_USB_SIE_EP7_CR0, 0x4000606e +.set CYDEV_USB_SIE_EP8_BASE, 0x4000607c +.set CYDEV_USB_SIE_EP8_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP8_CNT0, 0x4000607c +.set CYDEV_USB_SIE_EP8_CNT1, 0x4000607d +.set CYDEV_USB_SIE_EP8_CR0, 0x4000607e +.set CYDEV_USB_ARB_EP1_BASE, 0x40006080 +.set CYDEV_USB_ARB_EP1_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP1_CFG, 0x40006080 +.set CYDEV_USB_ARB_EP1_INT_EN, 0x40006081 +.set CYDEV_USB_ARB_EP1_SR, 0x40006082 +.set CYDEV_USB_ARB_RW1_BASE, 0x40006084 +.set CYDEV_USB_ARB_RW1_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW1_WA, 0x40006084 +.set CYDEV_USB_ARB_RW1_WA_MSB, 0x40006085 +.set CYDEV_USB_ARB_RW1_RA, 0x40006086 +.set CYDEV_USB_ARB_RW1_RA_MSB, 0x40006087 +.set CYDEV_USB_ARB_RW1_DR, 0x40006088 +.set CYDEV_USB_BUF_SIZE, 0x4000608c +.set CYDEV_USB_EP_ACTIVE, 0x4000608e +.set CYDEV_USB_EP_TYPE, 0x4000608f +.set CYDEV_USB_ARB_EP2_BASE, 0x40006090 +.set CYDEV_USB_ARB_EP2_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP2_CFG, 0x40006090 +.set CYDEV_USB_ARB_EP2_INT_EN, 0x40006091 +.set CYDEV_USB_ARB_EP2_SR, 0x40006092 +.set CYDEV_USB_ARB_RW2_BASE, 0x40006094 +.set CYDEV_USB_ARB_RW2_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW2_WA, 0x40006094 +.set CYDEV_USB_ARB_RW2_WA_MSB, 0x40006095 +.set CYDEV_USB_ARB_RW2_RA, 0x40006096 +.set CYDEV_USB_ARB_RW2_RA_MSB, 0x40006097 +.set CYDEV_USB_ARB_RW2_DR, 0x40006098 +.set CYDEV_USB_ARB_CFG, 0x4000609c +.set CYDEV_USB_USB_CLK_EN, 0x4000609d +.set CYDEV_USB_ARB_INT_EN, 0x4000609e +.set CYDEV_USB_ARB_INT_SR, 0x4000609f +.set CYDEV_USB_ARB_EP3_BASE, 0x400060a0 +.set CYDEV_USB_ARB_EP3_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP3_CFG, 0x400060a0 +.set CYDEV_USB_ARB_EP3_INT_EN, 0x400060a1 +.set CYDEV_USB_ARB_EP3_SR, 0x400060a2 +.set CYDEV_USB_ARB_RW3_BASE, 0x400060a4 +.set CYDEV_USB_ARB_RW3_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW3_WA, 0x400060a4 +.set CYDEV_USB_ARB_RW3_WA_MSB, 0x400060a5 +.set CYDEV_USB_ARB_RW3_RA, 0x400060a6 +.set CYDEV_USB_ARB_RW3_RA_MSB, 0x400060a7 +.set CYDEV_USB_ARB_RW3_DR, 0x400060a8 +.set CYDEV_USB_CWA, 0x400060ac +.set CYDEV_USB_CWA_MSB, 0x400060ad +.set CYDEV_USB_ARB_EP4_BASE, 0x400060b0 +.set CYDEV_USB_ARB_EP4_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP4_CFG, 0x400060b0 +.set CYDEV_USB_ARB_EP4_INT_EN, 0x400060b1 +.set CYDEV_USB_ARB_EP4_SR, 0x400060b2 +.set CYDEV_USB_ARB_RW4_BASE, 0x400060b4 +.set CYDEV_USB_ARB_RW4_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW4_WA, 0x400060b4 +.set CYDEV_USB_ARB_RW4_WA_MSB, 0x400060b5 +.set CYDEV_USB_ARB_RW4_RA, 0x400060b6 +.set CYDEV_USB_ARB_RW4_RA_MSB, 0x400060b7 +.set CYDEV_USB_ARB_RW4_DR, 0x400060b8 +.set CYDEV_USB_DMA_THRES, 0x400060bc +.set CYDEV_USB_DMA_THRES_MSB, 0x400060bd +.set CYDEV_USB_ARB_EP5_BASE, 0x400060c0 +.set CYDEV_USB_ARB_EP5_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP5_CFG, 0x400060c0 +.set CYDEV_USB_ARB_EP5_INT_EN, 0x400060c1 +.set CYDEV_USB_ARB_EP5_SR, 0x400060c2 +.set CYDEV_USB_ARB_RW5_BASE, 0x400060c4 +.set CYDEV_USB_ARB_RW5_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW5_WA, 0x400060c4 +.set CYDEV_USB_ARB_RW5_WA_MSB, 0x400060c5 +.set CYDEV_USB_ARB_RW5_RA, 0x400060c6 +.set CYDEV_USB_ARB_RW5_RA_MSB, 0x400060c7 +.set CYDEV_USB_ARB_RW5_DR, 0x400060c8 +.set CYDEV_USB_BUS_RST_CNT, 0x400060cc +.set CYDEV_USB_ARB_EP6_BASE, 0x400060d0 +.set CYDEV_USB_ARB_EP6_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP6_CFG, 0x400060d0 +.set CYDEV_USB_ARB_EP6_INT_EN, 0x400060d1 +.set CYDEV_USB_ARB_EP6_SR, 0x400060d2 +.set CYDEV_USB_ARB_RW6_BASE, 0x400060d4 +.set CYDEV_USB_ARB_RW6_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW6_WA, 0x400060d4 +.set CYDEV_USB_ARB_RW6_WA_MSB, 0x400060d5 +.set CYDEV_USB_ARB_RW6_RA, 0x400060d6 +.set CYDEV_USB_ARB_RW6_RA_MSB, 0x400060d7 +.set CYDEV_USB_ARB_RW6_DR, 0x400060d8 +.set CYDEV_USB_ARB_EP7_BASE, 0x400060e0 +.set CYDEV_USB_ARB_EP7_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP7_CFG, 0x400060e0 +.set CYDEV_USB_ARB_EP7_INT_EN, 0x400060e1 +.set CYDEV_USB_ARB_EP7_SR, 0x400060e2 +.set CYDEV_USB_ARB_RW7_BASE, 0x400060e4 +.set CYDEV_USB_ARB_RW7_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW7_WA, 0x400060e4 +.set CYDEV_USB_ARB_RW7_WA_MSB, 0x400060e5 +.set CYDEV_USB_ARB_RW7_RA, 0x400060e6 +.set CYDEV_USB_ARB_RW7_RA_MSB, 0x400060e7 +.set CYDEV_USB_ARB_RW7_DR, 0x400060e8 +.set CYDEV_USB_ARB_EP8_BASE, 0x400060f0 +.set CYDEV_USB_ARB_EP8_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP8_CFG, 0x400060f0 +.set CYDEV_USB_ARB_EP8_INT_EN, 0x400060f1 +.set CYDEV_USB_ARB_EP8_SR, 0x400060f2 +.set CYDEV_USB_ARB_RW8_BASE, 0x400060f4 +.set CYDEV_USB_ARB_RW8_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW8_WA, 0x400060f4 +.set CYDEV_USB_ARB_RW8_WA_MSB, 0x400060f5 +.set CYDEV_USB_ARB_RW8_RA, 0x400060f6 +.set CYDEV_USB_ARB_RW8_RA_MSB, 0x400060f7 +.set CYDEV_USB_ARB_RW8_DR, 0x400060f8 +.set CYDEV_USB_MEM_BASE, 0x40006100 +.set CYDEV_USB_MEM_SIZE, 0x00000200 +.set CYDEV_USB_MEM_DATA_MBASE, 0x40006100 +.set CYDEV_USB_MEM_DATA_MSIZE, 0x00000200 +.set CYDEV_UWRK_BASE, 0x40006400 +.set CYDEV_UWRK_SIZE, 0x00000b60 +.set CYDEV_UWRK_UWRK8_BASE, 0x40006400 +.set CYDEV_UWRK_UWRK8_SIZE, 0x000003b0 +.set CYDEV_UWRK_UWRK8_B0_BASE, 0x40006400 +.set CYDEV_UWRK_UWRK8_B0_SIZE, 0x000000b0 +.set CYDEV_UWRK_UWRK8_B0_UDB00_A0, 0x40006400 +.set CYDEV_UWRK_UWRK8_B0_UDB01_A0, 0x40006401 +.set CYDEV_UWRK_UWRK8_B0_UDB02_A0, 0x40006402 +.set CYDEV_UWRK_UWRK8_B0_UDB03_A0, 0x40006403 +.set CYDEV_UWRK_UWRK8_B0_UDB04_A0, 0x40006404 +.set CYDEV_UWRK_UWRK8_B0_UDB05_A0, 0x40006405 +.set CYDEV_UWRK_UWRK8_B0_UDB06_A0, 0x40006406 +.set CYDEV_UWRK_UWRK8_B0_UDB07_A0, 0x40006407 +.set CYDEV_UWRK_UWRK8_B0_UDB08_A0, 0x40006408 +.set CYDEV_UWRK_UWRK8_B0_UDB09_A0, 0x40006409 +.set CYDEV_UWRK_UWRK8_B0_UDB10_A0, 0x4000640a +.set CYDEV_UWRK_UWRK8_B0_UDB11_A0, 0x4000640b +.set CYDEV_UWRK_UWRK8_B0_UDB12_A0, 0x4000640c +.set CYDEV_UWRK_UWRK8_B0_UDB13_A0, 0x4000640d +.set CYDEV_UWRK_UWRK8_B0_UDB14_A0, 0x4000640e +.set CYDEV_UWRK_UWRK8_B0_UDB15_A0, 0x4000640f +.set CYDEV_UWRK_UWRK8_B0_UDB00_A1, 0x40006410 +.set CYDEV_UWRK_UWRK8_B0_UDB01_A1, 0x40006411 +.set CYDEV_UWRK_UWRK8_B0_UDB02_A1, 0x40006412 +.set CYDEV_UWRK_UWRK8_B0_UDB03_A1, 0x40006413 +.set CYDEV_UWRK_UWRK8_B0_UDB04_A1, 0x40006414 +.set CYDEV_UWRK_UWRK8_B0_UDB05_A1, 0x40006415 +.set CYDEV_UWRK_UWRK8_B0_UDB06_A1, 0x40006416 +.set CYDEV_UWRK_UWRK8_B0_UDB07_A1, 0x40006417 +.set CYDEV_UWRK_UWRK8_B0_UDB08_A1, 0x40006418 +.set CYDEV_UWRK_UWRK8_B0_UDB09_A1, 0x40006419 +.set CYDEV_UWRK_UWRK8_B0_UDB10_A1, 0x4000641a +.set CYDEV_UWRK_UWRK8_B0_UDB11_A1, 0x4000641b +.set CYDEV_UWRK_UWRK8_B0_UDB12_A1, 0x4000641c +.set CYDEV_UWRK_UWRK8_B0_UDB13_A1, 0x4000641d +.set CYDEV_UWRK_UWRK8_B0_UDB14_A1, 0x4000641e +.set CYDEV_UWRK_UWRK8_B0_UDB15_A1, 0x4000641f +.set CYDEV_UWRK_UWRK8_B0_UDB00_D0, 0x40006420 +.set CYDEV_UWRK_UWRK8_B0_UDB01_D0, 0x40006421 +.set CYDEV_UWRK_UWRK8_B0_UDB02_D0, 0x40006422 +.set CYDEV_UWRK_UWRK8_B0_UDB03_D0, 0x40006423 +.set CYDEV_UWRK_UWRK8_B0_UDB04_D0, 0x40006424 +.set CYDEV_UWRK_UWRK8_B0_UDB05_D0, 0x40006425 +.set CYDEV_UWRK_UWRK8_B0_UDB06_D0, 0x40006426 +.set CYDEV_UWRK_UWRK8_B0_UDB07_D0, 0x40006427 +.set CYDEV_UWRK_UWRK8_B0_UDB08_D0, 0x40006428 +.set CYDEV_UWRK_UWRK8_B0_UDB09_D0, 0x40006429 +.set CYDEV_UWRK_UWRK8_B0_UDB10_D0, 0x4000642a +.set CYDEV_UWRK_UWRK8_B0_UDB11_D0, 0x4000642b +.set CYDEV_UWRK_UWRK8_B0_UDB12_D0, 0x4000642c +.set CYDEV_UWRK_UWRK8_B0_UDB13_D0, 0x4000642d +.set CYDEV_UWRK_UWRK8_B0_UDB14_D0, 0x4000642e +.set CYDEV_UWRK_UWRK8_B0_UDB15_D0, 0x4000642f +.set CYDEV_UWRK_UWRK8_B0_UDB00_D1, 0x40006430 +.set CYDEV_UWRK_UWRK8_B0_UDB01_D1, 0x40006431 +.set CYDEV_UWRK_UWRK8_B0_UDB02_D1, 0x40006432 +.set CYDEV_UWRK_UWRK8_B0_UDB03_D1, 0x40006433 +.set CYDEV_UWRK_UWRK8_B0_UDB04_D1, 0x40006434 +.set CYDEV_UWRK_UWRK8_B0_UDB05_D1, 0x40006435 +.set CYDEV_UWRK_UWRK8_B0_UDB06_D1, 0x40006436 +.set CYDEV_UWRK_UWRK8_B0_UDB07_D1, 0x40006437 +.set CYDEV_UWRK_UWRK8_B0_UDB08_D1, 0x40006438 +.set CYDEV_UWRK_UWRK8_B0_UDB09_D1, 0x40006439 +.set CYDEV_UWRK_UWRK8_B0_UDB10_D1, 0x4000643a +.set CYDEV_UWRK_UWRK8_B0_UDB11_D1, 0x4000643b +.set CYDEV_UWRK_UWRK8_B0_UDB12_D1, 0x4000643c +.set CYDEV_UWRK_UWRK8_B0_UDB13_D1, 0x4000643d +.set CYDEV_UWRK_UWRK8_B0_UDB14_D1, 0x4000643e +.set CYDEV_UWRK_UWRK8_B0_UDB15_D1, 0x4000643f +.set CYDEV_UWRK_UWRK8_B0_UDB00_F0, 0x40006440 +.set CYDEV_UWRK_UWRK8_B0_UDB01_F0, 0x40006441 +.set CYDEV_UWRK_UWRK8_B0_UDB02_F0, 0x40006442 +.set CYDEV_UWRK_UWRK8_B0_UDB03_F0, 0x40006443 +.set CYDEV_UWRK_UWRK8_B0_UDB04_F0, 0x40006444 +.set CYDEV_UWRK_UWRK8_B0_UDB05_F0, 0x40006445 +.set CYDEV_UWRK_UWRK8_B0_UDB06_F0, 0x40006446 +.set CYDEV_UWRK_UWRK8_B0_UDB07_F0, 0x40006447 +.set CYDEV_UWRK_UWRK8_B0_UDB08_F0, 0x40006448 +.set CYDEV_UWRK_UWRK8_B0_UDB09_F0, 0x40006449 +.set CYDEV_UWRK_UWRK8_B0_UDB10_F0, 0x4000644a +.set CYDEV_UWRK_UWRK8_B0_UDB11_F0, 0x4000644b +.set CYDEV_UWRK_UWRK8_B0_UDB12_F0, 0x4000644c +.set CYDEV_UWRK_UWRK8_B0_UDB13_F0, 0x4000644d +.set CYDEV_UWRK_UWRK8_B0_UDB14_F0, 0x4000644e +.set CYDEV_UWRK_UWRK8_B0_UDB15_F0, 0x4000644f +.set CYDEV_UWRK_UWRK8_B0_UDB00_F1, 0x40006450 +.set CYDEV_UWRK_UWRK8_B0_UDB01_F1, 0x40006451 +.set CYDEV_UWRK_UWRK8_B0_UDB02_F1, 0x40006452 +.set CYDEV_UWRK_UWRK8_B0_UDB03_F1, 0x40006453 +.set CYDEV_UWRK_UWRK8_B0_UDB04_F1, 0x40006454 +.set CYDEV_UWRK_UWRK8_B0_UDB05_F1, 0x40006455 +.set CYDEV_UWRK_UWRK8_B0_UDB06_F1, 0x40006456 +.set CYDEV_UWRK_UWRK8_B0_UDB07_F1, 0x40006457 +.set CYDEV_UWRK_UWRK8_B0_UDB08_F1, 0x40006458 +.set CYDEV_UWRK_UWRK8_B0_UDB09_F1, 0x40006459 +.set CYDEV_UWRK_UWRK8_B0_UDB10_F1, 0x4000645a +.set CYDEV_UWRK_UWRK8_B0_UDB11_F1, 0x4000645b +.set CYDEV_UWRK_UWRK8_B0_UDB12_F1, 0x4000645c +.set CYDEV_UWRK_UWRK8_B0_UDB13_F1, 0x4000645d +.set CYDEV_UWRK_UWRK8_B0_UDB14_F1, 0x4000645e +.set CYDEV_UWRK_UWRK8_B0_UDB15_F1, 0x4000645f +.set CYDEV_UWRK_UWRK8_B0_UDB00_ST, 0x40006460 +.set CYDEV_UWRK_UWRK8_B0_UDB01_ST, 0x40006461 +.set CYDEV_UWRK_UWRK8_B0_UDB02_ST, 0x40006462 +.set CYDEV_UWRK_UWRK8_B0_UDB03_ST, 0x40006463 +.set CYDEV_UWRK_UWRK8_B0_UDB04_ST, 0x40006464 +.set CYDEV_UWRK_UWRK8_B0_UDB05_ST, 0x40006465 +.set CYDEV_UWRK_UWRK8_B0_UDB06_ST, 0x40006466 +.set CYDEV_UWRK_UWRK8_B0_UDB07_ST, 0x40006467 +.set CYDEV_UWRK_UWRK8_B0_UDB08_ST, 0x40006468 +.set CYDEV_UWRK_UWRK8_B0_UDB09_ST, 0x40006469 +.set CYDEV_UWRK_UWRK8_B0_UDB10_ST, 0x4000646a +.set CYDEV_UWRK_UWRK8_B0_UDB11_ST, 0x4000646b +.set CYDEV_UWRK_UWRK8_B0_UDB12_ST, 0x4000646c +.set CYDEV_UWRK_UWRK8_B0_UDB13_ST, 0x4000646d +.set CYDEV_UWRK_UWRK8_B0_UDB14_ST, 0x4000646e +.set CYDEV_UWRK_UWRK8_B0_UDB15_ST, 0x4000646f +.set CYDEV_UWRK_UWRK8_B0_UDB00_CTL, 0x40006470 +.set CYDEV_UWRK_UWRK8_B0_UDB01_CTL, 0x40006471 +.set CYDEV_UWRK_UWRK8_B0_UDB02_CTL, 0x40006472 +.set CYDEV_UWRK_UWRK8_B0_UDB03_CTL, 0x40006473 +.set CYDEV_UWRK_UWRK8_B0_UDB04_CTL, 0x40006474 +.set CYDEV_UWRK_UWRK8_B0_UDB05_CTL, 0x40006475 +.set CYDEV_UWRK_UWRK8_B0_UDB06_CTL, 0x40006476 +.set CYDEV_UWRK_UWRK8_B0_UDB07_CTL, 0x40006477 +.set CYDEV_UWRK_UWRK8_B0_UDB08_CTL, 0x40006478 +.set CYDEV_UWRK_UWRK8_B0_UDB09_CTL, 0x40006479 +.set CYDEV_UWRK_UWRK8_B0_UDB10_CTL, 0x4000647a +.set CYDEV_UWRK_UWRK8_B0_UDB11_CTL, 0x4000647b +.set CYDEV_UWRK_UWRK8_B0_UDB12_CTL, 0x4000647c +.set CYDEV_UWRK_UWRK8_B0_UDB13_CTL, 0x4000647d +.set CYDEV_UWRK_UWRK8_B0_UDB14_CTL, 0x4000647e +.set CYDEV_UWRK_UWRK8_B0_UDB15_CTL, 0x4000647f +.set CYDEV_UWRK_UWRK8_B0_UDB00_MSK, 0x40006480 +.set CYDEV_UWRK_UWRK8_B0_UDB01_MSK, 0x40006481 +.set CYDEV_UWRK_UWRK8_B0_UDB02_MSK, 0x40006482 +.set CYDEV_UWRK_UWRK8_B0_UDB03_MSK, 0x40006483 +.set CYDEV_UWRK_UWRK8_B0_UDB04_MSK, 0x40006484 +.set CYDEV_UWRK_UWRK8_B0_UDB05_MSK, 0x40006485 +.set CYDEV_UWRK_UWRK8_B0_UDB06_MSK, 0x40006486 +.set CYDEV_UWRK_UWRK8_B0_UDB07_MSK, 0x40006487 +.set CYDEV_UWRK_UWRK8_B0_UDB08_MSK, 0x40006488 +.set CYDEV_UWRK_UWRK8_B0_UDB09_MSK, 0x40006489 +.set CYDEV_UWRK_UWRK8_B0_UDB10_MSK, 0x4000648a +.set CYDEV_UWRK_UWRK8_B0_UDB11_MSK, 0x4000648b +.set CYDEV_UWRK_UWRK8_B0_UDB12_MSK, 0x4000648c +.set CYDEV_UWRK_UWRK8_B0_UDB13_MSK, 0x4000648d +.set CYDEV_UWRK_UWRK8_B0_UDB14_MSK, 0x4000648e +.set CYDEV_UWRK_UWRK8_B0_UDB15_MSK, 0x4000648f +.set CYDEV_UWRK_UWRK8_B0_UDB00_ACTL, 0x40006490 +.set CYDEV_UWRK_UWRK8_B0_UDB01_ACTL, 0x40006491 +.set CYDEV_UWRK_UWRK8_B0_UDB02_ACTL, 0x40006492 +.set CYDEV_UWRK_UWRK8_B0_UDB03_ACTL, 0x40006493 +.set CYDEV_UWRK_UWRK8_B0_UDB04_ACTL, 0x40006494 +.set CYDEV_UWRK_UWRK8_B0_UDB05_ACTL, 0x40006495 +.set CYDEV_UWRK_UWRK8_B0_UDB06_ACTL, 0x40006496 +.set CYDEV_UWRK_UWRK8_B0_UDB07_ACTL, 0x40006497 +.set CYDEV_UWRK_UWRK8_B0_UDB08_ACTL, 0x40006498 +.set CYDEV_UWRK_UWRK8_B0_UDB09_ACTL, 0x40006499 +.set CYDEV_UWRK_UWRK8_B0_UDB10_ACTL, 0x4000649a +.set CYDEV_UWRK_UWRK8_B0_UDB11_ACTL, 0x4000649b +.set CYDEV_UWRK_UWRK8_B0_UDB12_ACTL, 0x4000649c +.set CYDEV_UWRK_UWRK8_B0_UDB13_ACTL, 0x4000649d +.set CYDEV_UWRK_UWRK8_B0_UDB14_ACTL, 0x4000649e +.set CYDEV_UWRK_UWRK8_B0_UDB15_ACTL, 0x4000649f +.set CYDEV_UWRK_UWRK8_B0_UDB00_MC, 0x400064a0 +.set CYDEV_UWRK_UWRK8_B0_UDB01_MC, 0x400064a1 +.set CYDEV_UWRK_UWRK8_B0_UDB02_MC, 0x400064a2 +.set CYDEV_UWRK_UWRK8_B0_UDB03_MC, 0x400064a3 +.set CYDEV_UWRK_UWRK8_B0_UDB04_MC, 0x400064a4 +.set CYDEV_UWRK_UWRK8_B0_UDB05_MC, 0x400064a5 +.set CYDEV_UWRK_UWRK8_B0_UDB06_MC, 0x400064a6 +.set CYDEV_UWRK_UWRK8_B0_UDB07_MC, 0x400064a7 +.set CYDEV_UWRK_UWRK8_B0_UDB08_MC, 0x400064a8 +.set CYDEV_UWRK_UWRK8_B0_UDB09_MC, 0x400064a9 +.set CYDEV_UWRK_UWRK8_B0_UDB10_MC, 0x400064aa +.set CYDEV_UWRK_UWRK8_B0_UDB11_MC, 0x400064ab +.set CYDEV_UWRK_UWRK8_B0_UDB12_MC, 0x400064ac +.set CYDEV_UWRK_UWRK8_B0_UDB13_MC, 0x400064ad +.set CYDEV_UWRK_UWRK8_B0_UDB14_MC, 0x400064ae +.set CYDEV_UWRK_UWRK8_B0_UDB15_MC, 0x400064af +.set CYDEV_UWRK_UWRK8_B1_BASE, 0x40006500 +.set CYDEV_UWRK_UWRK8_B1_SIZE, 0x000000b0 +.set CYDEV_UWRK_UWRK8_B1_UDB04_A0, 0x40006504 +.set CYDEV_UWRK_UWRK8_B1_UDB05_A0, 0x40006505 +.set CYDEV_UWRK_UWRK8_B1_UDB06_A0, 0x40006506 +.set CYDEV_UWRK_UWRK8_B1_UDB07_A0, 0x40006507 +.set CYDEV_UWRK_UWRK8_B1_UDB08_A0, 0x40006508 +.set CYDEV_UWRK_UWRK8_B1_UDB09_A0, 0x40006509 +.set CYDEV_UWRK_UWRK8_B1_UDB10_A0, 0x4000650a +.set CYDEV_UWRK_UWRK8_B1_UDB11_A0, 0x4000650b +.set CYDEV_UWRK_UWRK8_B1_UDB04_A1, 0x40006514 +.set CYDEV_UWRK_UWRK8_B1_UDB05_A1, 0x40006515 +.set CYDEV_UWRK_UWRK8_B1_UDB06_A1, 0x40006516 +.set CYDEV_UWRK_UWRK8_B1_UDB07_A1, 0x40006517 +.set CYDEV_UWRK_UWRK8_B1_UDB08_A1, 0x40006518 +.set CYDEV_UWRK_UWRK8_B1_UDB09_A1, 0x40006519 +.set CYDEV_UWRK_UWRK8_B1_UDB10_A1, 0x4000651a +.set CYDEV_UWRK_UWRK8_B1_UDB11_A1, 0x4000651b +.set CYDEV_UWRK_UWRK8_B1_UDB04_D0, 0x40006524 +.set CYDEV_UWRK_UWRK8_B1_UDB05_D0, 0x40006525 +.set CYDEV_UWRK_UWRK8_B1_UDB06_D0, 0x40006526 +.set CYDEV_UWRK_UWRK8_B1_UDB07_D0, 0x40006527 +.set CYDEV_UWRK_UWRK8_B1_UDB08_D0, 0x40006528 +.set CYDEV_UWRK_UWRK8_B1_UDB09_D0, 0x40006529 +.set CYDEV_UWRK_UWRK8_B1_UDB10_D0, 0x4000652a +.set CYDEV_UWRK_UWRK8_B1_UDB11_D0, 0x4000652b +.set CYDEV_UWRK_UWRK8_B1_UDB04_D1, 0x40006534 +.set CYDEV_UWRK_UWRK8_B1_UDB05_D1, 0x40006535 +.set CYDEV_UWRK_UWRK8_B1_UDB06_D1, 0x40006536 +.set CYDEV_UWRK_UWRK8_B1_UDB07_D1, 0x40006537 +.set CYDEV_UWRK_UWRK8_B1_UDB08_D1, 0x40006538 +.set CYDEV_UWRK_UWRK8_B1_UDB09_D1, 0x40006539 +.set CYDEV_UWRK_UWRK8_B1_UDB10_D1, 0x4000653a +.set CYDEV_UWRK_UWRK8_B1_UDB11_D1, 0x4000653b +.set CYDEV_UWRK_UWRK8_B1_UDB04_F0, 0x40006544 +.set CYDEV_UWRK_UWRK8_B1_UDB05_F0, 0x40006545 +.set CYDEV_UWRK_UWRK8_B1_UDB06_F0, 0x40006546 +.set CYDEV_UWRK_UWRK8_B1_UDB07_F0, 0x40006547 +.set CYDEV_UWRK_UWRK8_B1_UDB08_F0, 0x40006548 +.set CYDEV_UWRK_UWRK8_B1_UDB09_F0, 0x40006549 +.set CYDEV_UWRK_UWRK8_B1_UDB10_F0, 0x4000654a +.set CYDEV_UWRK_UWRK8_B1_UDB11_F0, 0x4000654b +.set CYDEV_UWRK_UWRK8_B1_UDB04_F1, 0x40006554 +.set CYDEV_UWRK_UWRK8_B1_UDB05_F1, 0x40006555 +.set CYDEV_UWRK_UWRK8_B1_UDB06_F1, 0x40006556 +.set CYDEV_UWRK_UWRK8_B1_UDB07_F1, 0x40006557 +.set CYDEV_UWRK_UWRK8_B1_UDB08_F1, 0x40006558 +.set CYDEV_UWRK_UWRK8_B1_UDB09_F1, 0x40006559 +.set CYDEV_UWRK_UWRK8_B1_UDB10_F1, 0x4000655a +.set CYDEV_UWRK_UWRK8_B1_UDB11_F1, 0x4000655b +.set CYDEV_UWRK_UWRK8_B1_UDB04_ST, 0x40006564 +.set CYDEV_UWRK_UWRK8_B1_UDB05_ST, 0x40006565 +.set CYDEV_UWRK_UWRK8_B1_UDB06_ST, 0x40006566 +.set CYDEV_UWRK_UWRK8_B1_UDB07_ST, 0x40006567 +.set CYDEV_UWRK_UWRK8_B1_UDB08_ST, 0x40006568 +.set CYDEV_UWRK_UWRK8_B1_UDB09_ST, 0x40006569 +.set CYDEV_UWRK_UWRK8_B1_UDB10_ST, 0x4000656a +.set CYDEV_UWRK_UWRK8_B1_UDB11_ST, 0x4000656b +.set CYDEV_UWRK_UWRK8_B1_UDB04_CTL, 0x40006574 +.set CYDEV_UWRK_UWRK8_B1_UDB05_CTL, 0x40006575 +.set CYDEV_UWRK_UWRK8_B1_UDB06_CTL, 0x40006576 +.set CYDEV_UWRK_UWRK8_B1_UDB07_CTL, 0x40006577 +.set CYDEV_UWRK_UWRK8_B1_UDB08_CTL, 0x40006578 +.set CYDEV_UWRK_UWRK8_B1_UDB09_CTL, 0x40006579 +.set CYDEV_UWRK_UWRK8_B1_UDB10_CTL, 0x4000657a +.set CYDEV_UWRK_UWRK8_B1_UDB11_CTL, 0x4000657b +.set CYDEV_UWRK_UWRK8_B1_UDB04_MSK, 0x40006584 +.set CYDEV_UWRK_UWRK8_B1_UDB05_MSK, 0x40006585 +.set CYDEV_UWRK_UWRK8_B1_UDB06_MSK, 0x40006586 +.set CYDEV_UWRK_UWRK8_B1_UDB07_MSK, 0x40006587 +.set CYDEV_UWRK_UWRK8_B1_UDB08_MSK, 0x40006588 +.set CYDEV_UWRK_UWRK8_B1_UDB09_MSK, 0x40006589 +.set CYDEV_UWRK_UWRK8_B1_UDB10_MSK, 0x4000658a +.set CYDEV_UWRK_UWRK8_B1_UDB11_MSK, 0x4000658b +.set CYDEV_UWRK_UWRK8_B1_UDB04_ACTL, 0x40006594 +.set CYDEV_UWRK_UWRK8_B1_UDB05_ACTL, 0x40006595 +.set CYDEV_UWRK_UWRK8_B1_UDB06_ACTL, 0x40006596 +.set CYDEV_UWRK_UWRK8_B1_UDB07_ACTL, 0x40006597 +.set CYDEV_UWRK_UWRK8_B1_UDB08_ACTL, 0x40006598 +.set CYDEV_UWRK_UWRK8_B1_UDB09_ACTL, 0x40006599 +.set CYDEV_UWRK_UWRK8_B1_UDB10_ACTL, 0x4000659a +.set CYDEV_UWRK_UWRK8_B1_UDB11_ACTL, 0x4000659b +.set CYDEV_UWRK_UWRK8_B1_UDB04_MC, 0x400065a4 +.set CYDEV_UWRK_UWRK8_B1_UDB05_MC, 0x400065a5 +.set CYDEV_UWRK_UWRK8_B1_UDB06_MC, 0x400065a6 +.set CYDEV_UWRK_UWRK8_B1_UDB07_MC, 0x400065a7 +.set CYDEV_UWRK_UWRK8_B1_UDB08_MC, 0x400065a8 +.set CYDEV_UWRK_UWRK8_B1_UDB09_MC, 0x400065a9 +.set CYDEV_UWRK_UWRK8_B1_UDB10_MC, 0x400065aa +.set CYDEV_UWRK_UWRK8_B1_UDB11_MC, 0x400065ab +.set CYDEV_UWRK_UWRK16_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_SIZE, 0x00000760 +.set CYDEV_UWRK_UWRK16_CAT_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_CAT_SIZE, 0x00000760 +.set CYDEV_UWRK_UWRK16_CAT_B0_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_CAT_B0_SIZE, 0x00000160 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1, 0x40006800 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1, 0x40006802 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1, 0x40006804 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1, 0x40006806 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1, 0x40006808 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1, 0x4000680a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1, 0x4000680c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1, 0x4000680e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1, 0x40006810 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1, 0x40006812 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1, 0x40006814 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1, 0x40006816 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1, 0x40006818 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1, 0x4000681a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1, 0x4000681c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1, 0x4000681e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1, 0x40006840 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1, 0x40006842 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1, 0x40006844 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1, 0x40006846 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1, 0x40006848 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1, 0x4000684a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1, 0x4000684c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1, 0x4000684e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1, 0x40006850 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1, 0x40006852 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1, 0x40006854 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1, 0x40006856 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1, 0x40006858 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1, 0x4000685a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1, 0x4000685c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1, 0x4000685e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1, 0x40006880 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1, 0x40006882 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1, 0x40006884 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1, 0x40006886 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1, 0x40006888 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1, 0x4000688a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1, 0x4000688c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1, 0x4000688e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1, 0x40006890 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1, 0x40006892 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1, 0x40006894 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1, 0x40006896 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1, 0x40006898 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1, 0x4000689a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1, 0x4000689c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1, 0x4000689e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL, 0x400068c0 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL, 0x400068c2 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL, 0x400068c4 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL, 0x400068c6 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL, 0x400068c8 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL, 0x400068ca +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL, 0x400068cc +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL, 0x400068ce +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL, 0x400068d0 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL, 0x400068d2 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL, 0x400068d4 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL, 0x400068d6 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL, 0x400068d8 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL, 0x400068da +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL, 0x400068dc +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL, 0x400068de +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL, 0x40006900 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL, 0x40006902 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL, 0x40006904 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL, 0x40006906 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL, 0x40006908 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL, 0x4000690a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL, 0x4000690c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL, 0x4000690e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL, 0x40006910 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL, 0x40006912 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL, 0x40006914 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL, 0x40006916 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL, 0x40006918 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL, 0x4000691a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL, 0x4000691c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL, 0x4000691e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00, 0x40006940 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00, 0x40006942 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00, 0x40006944 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00, 0x40006946 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00, 0x40006948 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00, 0x4000694a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00, 0x4000694c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00, 0x4000694e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00, 0x40006950 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00, 0x40006952 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00, 0x40006954 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00, 0x40006956 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00, 0x40006958 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00, 0x4000695a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00, 0x4000695c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00, 0x4000695e +.set CYDEV_UWRK_UWRK16_CAT_B1_BASE, 0x40006a00 +.set CYDEV_UWRK_UWRK16_CAT_B1_SIZE, 0x00000160 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1, 0x40006a08 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1, 0x40006a0a +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1, 0x40006a0c +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1, 0x40006a0e +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1, 0x40006a10 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1, 0x40006a12 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1, 0x40006a14 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1, 0x40006a16 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1, 0x40006a48 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1, 0x40006a4a +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1, 0x40006a4c +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1, 0x40006a4e +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1, 0x40006a50 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1, 0x40006a52 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1, 0x40006a54 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1, 0x40006a56 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1, 0x40006a88 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1, 0x40006a8a +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1, 0x40006a8c +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1, 0x40006a8e +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1, 0x40006a90 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1, 0x40006a92 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1, 0x40006a94 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1, 0x40006a96 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL, 0x40006ac8 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL, 0x40006aca +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL, 0x40006acc +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL, 0x40006ace +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL, 0x40006ad0 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL, 0x40006ad2 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL, 0x40006ad4 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL, 0x40006ad6 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL, 0x40006b08 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL, 0x40006b0a +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL, 0x40006b0c +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL, 0x40006b0e +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL, 0x40006b10 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL, 0x40006b12 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL, 0x40006b14 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL, 0x40006b16 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00, 0x40006b48 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00, 0x40006b4a +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00, 0x40006b4c +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00, 0x40006b4e +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00, 0x40006b50 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00, 0x40006b52 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00, 0x40006b54 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00, 0x40006b56 +.set CYDEV_UWRK_UWRK16_DEF_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_DEF_SIZE, 0x0000075e +.set CYDEV_UWRK_UWRK16_DEF_B0_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_DEF_B0_SIZE, 0x0000015e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0, 0x40006800 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0, 0x40006802 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0, 0x40006804 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0, 0x40006806 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0, 0x40006808 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0, 0x4000680a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0, 0x4000680c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0, 0x4000680e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0, 0x40006810 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0, 0x40006812 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0, 0x40006814 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0, 0x40006816 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0, 0x40006818 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0, 0x4000681a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0, 0x4000681c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1, 0x40006820 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1, 0x40006822 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1, 0x40006824 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1, 0x40006826 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1, 0x40006828 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1, 0x4000682a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1, 0x4000682c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1, 0x4000682e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1, 0x40006830 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1, 0x40006832 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1, 0x40006834 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1, 0x40006836 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1, 0x40006838 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1, 0x4000683a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1, 0x4000683c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0, 0x40006840 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0, 0x40006842 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0, 0x40006844 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0, 0x40006846 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0, 0x40006848 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0, 0x4000684a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0, 0x4000684c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0, 0x4000684e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0, 0x40006850 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0, 0x40006852 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0, 0x40006854 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0, 0x40006856 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0, 0x40006858 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0, 0x4000685a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0, 0x4000685c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1, 0x40006860 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1, 0x40006862 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1, 0x40006864 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1, 0x40006866 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1, 0x40006868 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1, 0x4000686a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1, 0x4000686c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1, 0x4000686e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1, 0x40006870 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1, 0x40006872 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1, 0x40006874 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1, 0x40006876 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1, 0x40006878 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1, 0x4000687a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1, 0x4000687c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0, 0x40006880 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0, 0x40006882 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0, 0x40006884 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0, 0x40006886 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0, 0x40006888 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0, 0x4000688a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0, 0x4000688c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0, 0x4000688e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0, 0x40006890 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0, 0x40006892 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0, 0x40006894 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0, 0x40006896 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0, 0x40006898 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0, 0x4000689a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0, 0x4000689c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1, 0x400068a0 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1, 0x400068a2 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1, 0x400068a4 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1, 0x400068a6 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1, 0x400068a8 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1, 0x400068aa +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1, 0x400068ac +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1, 0x400068ae +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1, 0x400068b0 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1, 0x400068b2 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1, 0x400068b4 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1, 0x400068b6 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1, 0x400068b8 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1, 0x400068ba +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1, 0x400068bc +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST, 0x400068c0 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST, 0x400068c2 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST, 0x400068c4 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST, 0x400068c6 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST, 0x400068c8 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST, 0x400068ca +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST, 0x400068cc +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST, 0x400068ce +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST, 0x400068d0 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST, 0x400068d2 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST, 0x400068d4 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST, 0x400068d6 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST, 0x400068d8 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST, 0x400068da +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST, 0x400068dc +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL, 0x400068e0 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL, 0x400068e2 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL, 0x400068e4 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL, 0x400068e6 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL, 0x400068e8 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL, 0x400068ea +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL, 0x400068ec +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL, 0x400068ee +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL, 0x400068f0 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL, 0x400068f2 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL, 0x400068f4 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL, 0x400068f6 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL, 0x400068f8 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL, 0x400068fa +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL, 0x400068fc +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK, 0x40006900 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK, 0x40006902 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK, 0x40006904 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK, 0x40006906 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK, 0x40006908 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK, 0x4000690a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK, 0x4000690c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK, 0x4000690e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK, 0x40006910 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK, 0x40006912 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK, 0x40006914 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK, 0x40006916 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK, 0x40006918 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK, 0x4000691a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK, 0x4000691c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL, 0x40006920 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL, 0x40006922 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL, 0x40006924 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL, 0x40006926 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL, 0x40006928 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL, 0x4000692a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL, 0x4000692c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL, 0x4000692e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL, 0x40006930 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL, 0x40006932 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL, 0x40006934 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL, 0x40006936 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL, 0x40006938 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL, 0x4000693a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL, 0x4000693c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC, 0x40006940 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC, 0x40006942 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC, 0x40006944 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC, 0x40006946 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC, 0x40006948 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC, 0x4000694a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC, 0x4000694c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC, 0x4000694e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC, 0x40006950 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC, 0x40006952 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC, 0x40006954 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC, 0x40006956 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC, 0x40006958 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC, 0x4000695a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC, 0x4000695c +.set CYDEV_UWRK_UWRK16_DEF_B1_BASE, 0x40006a00 +.set CYDEV_UWRK_UWRK16_DEF_B1_SIZE, 0x0000015e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0, 0x40006a08 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0, 0x40006a0a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0, 0x40006a0c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0, 0x40006a0e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0, 0x40006a10 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0, 0x40006a12 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0, 0x40006a14 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0, 0x40006a16 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1, 0x40006a28 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1, 0x40006a2a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1, 0x40006a2c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1, 0x40006a2e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1, 0x40006a30 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1, 0x40006a32 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1, 0x40006a34 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1, 0x40006a36 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0, 0x40006a48 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0, 0x40006a4a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0, 0x40006a4c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0, 0x40006a4e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0, 0x40006a50 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0, 0x40006a52 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0, 0x40006a54 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0, 0x40006a56 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1, 0x40006a68 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1, 0x40006a6a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1, 0x40006a6c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1, 0x40006a6e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1, 0x40006a70 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1, 0x40006a72 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1, 0x40006a74 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1, 0x40006a76 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0, 0x40006a88 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0, 0x40006a8a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0, 0x40006a8c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0, 0x40006a8e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0, 0x40006a90 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0, 0x40006a92 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0, 0x40006a94 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0, 0x40006a96 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1, 0x40006aa8 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1, 0x40006aaa +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1, 0x40006aac +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1, 0x40006aae +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1, 0x40006ab0 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1, 0x40006ab2 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1, 0x40006ab4 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1, 0x40006ab6 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST, 0x40006ac8 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST, 0x40006aca +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST, 0x40006acc +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST, 0x40006ace +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST, 0x40006ad0 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST, 0x40006ad2 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST, 0x40006ad4 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST, 0x40006ad6 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL, 0x40006ae8 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL, 0x40006aea +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL, 0x40006aec +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL, 0x40006aee +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL, 0x40006af0 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL, 0x40006af2 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL, 0x40006af4 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL, 0x40006af6 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK, 0x40006b08 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK, 0x40006b0a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK, 0x40006b0c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK, 0x40006b0e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK, 0x40006b10 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK, 0x40006b12 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK, 0x40006b14 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK, 0x40006b16 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL, 0x40006b28 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL, 0x40006b2a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL, 0x40006b2c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL, 0x40006b2e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL, 0x40006b30 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL, 0x40006b32 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL, 0x40006b34 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL, 0x40006b36 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC, 0x40006b48 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC, 0x40006b4a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC, 0x40006b4c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC, 0x40006b4e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC, 0x40006b50 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC, 0x40006b52 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC, 0x40006b54 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC, 0x40006b56 +.set CYDEV_PHUB_BASE, 0x40007000 +.set CYDEV_PHUB_SIZE, 0x00000c00 +.set CYDEV_PHUB_CFG, 0x40007000 +.set CYDEV_PHUB_ERR, 0x40007004 +.set CYDEV_PHUB_ERR_ADR, 0x40007008 +.set CYDEV_PHUB_CH0_BASE, 0x40007010 +.set CYDEV_PHUB_CH0_SIZE, 0x0000000c +.set CYDEV_PHUB_CH0_BASIC_CFG, 0x40007010 +.set CYDEV_PHUB_CH0_ACTION, 0x40007014 +.set CYDEV_PHUB_CH0_BASIC_STATUS, 0x40007018 +.set CYDEV_PHUB_CH1_BASE, 0x40007020 +.set CYDEV_PHUB_CH1_SIZE, 0x0000000c +.set CYDEV_PHUB_CH1_BASIC_CFG, 0x40007020 +.set CYDEV_PHUB_CH1_ACTION, 0x40007024 +.set CYDEV_PHUB_CH1_BASIC_STATUS, 0x40007028 +.set CYDEV_PHUB_CH2_BASE, 0x40007030 +.set CYDEV_PHUB_CH2_SIZE, 0x0000000c +.set CYDEV_PHUB_CH2_BASIC_CFG, 0x40007030 +.set CYDEV_PHUB_CH2_ACTION, 0x40007034 +.set CYDEV_PHUB_CH2_BASIC_STATUS, 0x40007038 +.set CYDEV_PHUB_CH3_BASE, 0x40007040 +.set CYDEV_PHUB_CH3_SIZE, 0x0000000c +.set CYDEV_PHUB_CH3_BASIC_CFG, 0x40007040 +.set CYDEV_PHUB_CH3_ACTION, 0x40007044 +.set CYDEV_PHUB_CH3_BASIC_STATUS, 0x40007048 +.set CYDEV_PHUB_CH4_BASE, 0x40007050 +.set CYDEV_PHUB_CH4_SIZE, 0x0000000c +.set CYDEV_PHUB_CH4_BASIC_CFG, 0x40007050 +.set CYDEV_PHUB_CH4_ACTION, 0x40007054 +.set CYDEV_PHUB_CH4_BASIC_STATUS, 0x40007058 +.set CYDEV_PHUB_CH5_BASE, 0x40007060 +.set CYDEV_PHUB_CH5_SIZE, 0x0000000c +.set CYDEV_PHUB_CH5_BASIC_CFG, 0x40007060 +.set CYDEV_PHUB_CH5_ACTION, 0x40007064 +.set CYDEV_PHUB_CH5_BASIC_STATUS, 0x40007068 +.set CYDEV_PHUB_CH6_BASE, 0x40007070 +.set CYDEV_PHUB_CH6_SIZE, 0x0000000c +.set CYDEV_PHUB_CH6_BASIC_CFG, 0x40007070 +.set CYDEV_PHUB_CH6_ACTION, 0x40007074 +.set CYDEV_PHUB_CH6_BASIC_STATUS, 0x40007078 +.set CYDEV_PHUB_CH7_BASE, 0x40007080 +.set CYDEV_PHUB_CH7_SIZE, 0x0000000c +.set CYDEV_PHUB_CH7_BASIC_CFG, 0x40007080 +.set CYDEV_PHUB_CH7_ACTION, 0x40007084 +.set CYDEV_PHUB_CH7_BASIC_STATUS, 0x40007088 +.set CYDEV_PHUB_CH8_BASE, 0x40007090 +.set CYDEV_PHUB_CH8_SIZE, 0x0000000c +.set CYDEV_PHUB_CH8_BASIC_CFG, 0x40007090 +.set CYDEV_PHUB_CH8_ACTION, 0x40007094 +.set CYDEV_PHUB_CH8_BASIC_STATUS, 0x40007098 +.set CYDEV_PHUB_CH9_BASE, 0x400070a0 +.set CYDEV_PHUB_CH9_SIZE, 0x0000000c +.set CYDEV_PHUB_CH9_BASIC_CFG, 0x400070a0 +.set CYDEV_PHUB_CH9_ACTION, 0x400070a4 +.set CYDEV_PHUB_CH9_BASIC_STATUS, 0x400070a8 +.set CYDEV_PHUB_CH10_BASE, 0x400070b0 +.set CYDEV_PHUB_CH10_SIZE, 0x0000000c +.set CYDEV_PHUB_CH10_BASIC_CFG, 0x400070b0 +.set CYDEV_PHUB_CH10_ACTION, 0x400070b4 +.set CYDEV_PHUB_CH10_BASIC_STATUS, 0x400070b8 +.set CYDEV_PHUB_CH11_BASE, 0x400070c0 +.set CYDEV_PHUB_CH11_SIZE, 0x0000000c +.set CYDEV_PHUB_CH11_BASIC_CFG, 0x400070c0 +.set CYDEV_PHUB_CH11_ACTION, 0x400070c4 +.set CYDEV_PHUB_CH11_BASIC_STATUS, 0x400070c8 +.set CYDEV_PHUB_CH12_BASE, 0x400070d0 +.set CYDEV_PHUB_CH12_SIZE, 0x0000000c +.set CYDEV_PHUB_CH12_BASIC_CFG, 0x400070d0 +.set CYDEV_PHUB_CH12_ACTION, 0x400070d4 +.set CYDEV_PHUB_CH12_BASIC_STATUS, 0x400070d8 +.set CYDEV_PHUB_CH13_BASE, 0x400070e0 +.set CYDEV_PHUB_CH13_SIZE, 0x0000000c +.set CYDEV_PHUB_CH13_BASIC_CFG, 0x400070e0 +.set CYDEV_PHUB_CH13_ACTION, 0x400070e4 +.set CYDEV_PHUB_CH13_BASIC_STATUS, 0x400070e8 +.set CYDEV_PHUB_CH14_BASE, 0x400070f0 +.set CYDEV_PHUB_CH14_SIZE, 0x0000000c +.set CYDEV_PHUB_CH14_BASIC_CFG, 0x400070f0 +.set CYDEV_PHUB_CH14_ACTION, 0x400070f4 +.set CYDEV_PHUB_CH14_BASIC_STATUS, 0x400070f8 +.set CYDEV_PHUB_CH15_BASE, 0x40007100 +.set CYDEV_PHUB_CH15_SIZE, 0x0000000c +.set CYDEV_PHUB_CH15_BASIC_CFG, 0x40007100 +.set CYDEV_PHUB_CH15_ACTION, 0x40007104 +.set CYDEV_PHUB_CH15_BASIC_STATUS, 0x40007108 +.set CYDEV_PHUB_CH16_BASE, 0x40007110 +.set CYDEV_PHUB_CH16_SIZE, 0x0000000c +.set CYDEV_PHUB_CH16_BASIC_CFG, 0x40007110 +.set CYDEV_PHUB_CH16_ACTION, 0x40007114 +.set CYDEV_PHUB_CH16_BASIC_STATUS, 0x40007118 +.set CYDEV_PHUB_CH17_BASE, 0x40007120 +.set CYDEV_PHUB_CH17_SIZE, 0x0000000c +.set CYDEV_PHUB_CH17_BASIC_CFG, 0x40007120 +.set CYDEV_PHUB_CH17_ACTION, 0x40007124 +.set CYDEV_PHUB_CH17_BASIC_STATUS, 0x40007128 +.set CYDEV_PHUB_CH18_BASE, 0x40007130 +.set CYDEV_PHUB_CH18_SIZE, 0x0000000c +.set CYDEV_PHUB_CH18_BASIC_CFG, 0x40007130 +.set CYDEV_PHUB_CH18_ACTION, 0x40007134 +.set CYDEV_PHUB_CH18_BASIC_STATUS, 0x40007138 +.set CYDEV_PHUB_CH19_BASE, 0x40007140 +.set CYDEV_PHUB_CH19_SIZE, 0x0000000c +.set CYDEV_PHUB_CH19_BASIC_CFG, 0x40007140 +.set CYDEV_PHUB_CH19_ACTION, 0x40007144 +.set CYDEV_PHUB_CH19_BASIC_STATUS, 0x40007148 +.set CYDEV_PHUB_CH20_BASE, 0x40007150 +.set CYDEV_PHUB_CH20_SIZE, 0x0000000c +.set CYDEV_PHUB_CH20_BASIC_CFG, 0x40007150 +.set CYDEV_PHUB_CH20_ACTION, 0x40007154 +.set CYDEV_PHUB_CH20_BASIC_STATUS, 0x40007158 +.set CYDEV_PHUB_CH21_BASE, 0x40007160 +.set CYDEV_PHUB_CH21_SIZE, 0x0000000c +.set CYDEV_PHUB_CH21_BASIC_CFG, 0x40007160 +.set CYDEV_PHUB_CH21_ACTION, 0x40007164 +.set CYDEV_PHUB_CH21_BASIC_STATUS, 0x40007168 +.set CYDEV_PHUB_CH22_BASE, 0x40007170 +.set CYDEV_PHUB_CH22_SIZE, 0x0000000c +.set CYDEV_PHUB_CH22_BASIC_CFG, 0x40007170 +.set CYDEV_PHUB_CH22_ACTION, 0x40007174 +.set CYDEV_PHUB_CH22_BASIC_STATUS, 0x40007178 +.set CYDEV_PHUB_CH23_BASE, 0x40007180 +.set CYDEV_PHUB_CH23_SIZE, 0x0000000c +.set CYDEV_PHUB_CH23_BASIC_CFG, 0x40007180 +.set CYDEV_PHUB_CH23_ACTION, 0x40007184 +.set CYDEV_PHUB_CH23_BASIC_STATUS, 0x40007188 +.set CYDEV_PHUB_CFGMEM0_BASE, 0x40007600 +.set CYDEV_PHUB_CFGMEM0_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM0_CFG0, 0x40007600 +.set CYDEV_PHUB_CFGMEM0_CFG1, 0x40007604 +.set CYDEV_PHUB_CFGMEM1_BASE, 0x40007608 +.set CYDEV_PHUB_CFGMEM1_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM1_CFG0, 0x40007608 +.set CYDEV_PHUB_CFGMEM1_CFG1, 0x4000760c +.set CYDEV_PHUB_CFGMEM2_BASE, 0x40007610 +.set CYDEV_PHUB_CFGMEM2_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM2_CFG0, 0x40007610 +.set CYDEV_PHUB_CFGMEM2_CFG1, 0x40007614 +.set CYDEV_PHUB_CFGMEM3_BASE, 0x40007618 +.set CYDEV_PHUB_CFGMEM3_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM3_CFG0, 0x40007618 +.set CYDEV_PHUB_CFGMEM3_CFG1, 0x4000761c +.set CYDEV_PHUB_CFGMEM4_BASE, 0x40007620 +.set CYDEV_PHUB_CFGMEM4_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM4_CFG0, 0x40007620 +.set CYDEV_PHUB_CFGMEM4_CFG1, 0x40007624 +.set CYDEV_PHUB_CFGMEM5_BASE, 0x40007628 +.set CYDEV_PHUB_CFGMEM5_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM5_CFG0, 0x40007628 +.set CYDEV_PHUB_CFGMEM5_CFG1, 0x4000762c +.set CYDEV_PHUB_CFGMEM6_BASE, 0x40007630 +.set CYDEV_PHUB_CFGMEM6_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM6_CFG0, 0x40007630 +.set CYDEV_PHUB_CFGMEM6_CFG1, 0x40007634 +.set CYDEV_PHUB_CFGMEM7_BASE, 0x40007638 +.set CYDEV_PHUB_CFGMEM7_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM7_CFG0, 0x40007638 +.set CYDEV_PHUB_CFGMEM7_CFG1, 0x4000763c +.set CYDEV_PHUB_CFGMEM8_BASE, 0x40007640 +.set CYDEV_PHUB_CFGMEM8_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM8_CFG0, 0x40007640 +.set CYDEV_PHUB_CFGMEM8_CFG1, 0x40007644 +.set CYDEV_PHUB_CFGMEM9_BASE, 0x40007648 +.set CYDEV_PHUB_CFGMEM9_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM9_CFG0, 0x40007648 +.set CYDEV_PHUB_CFGMEM9_CFG1, 0x4000764c +.set CYDEV_PHUB_CFGMEM10_BASE, 0x40007650 +.set CYDEV_PHUB_CFGMEM10_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM10_CFG0, 0x40007650 +.set CYDEV_PHUB_CFGMEM10_CFG1, 0x40007654 +.set CYDEV_PHUB_CFGMEM11_BASE, 0x40007658 +.set CYDEV_PHUB_CFGMEM11_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM11_CFG0, 0x40007658 +.set CYDEV_PHUB_CFGMEM11_CFG1, 0x4000765c +.set CYDEV_PHUB_CFGMEM12_BASE, 0x40007660 +.set CYDEV_PHUB_CFGMEM12_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM12_CFG0, 0x40007660 +.set CYDEV_PHUB_CFGMEM12_CFG1, 0x40007664 +.set CYDEV_PHUB_CFGMEM13_BASE, 0x40007668 +.set CYDEV_PHUB_CFGMEM13_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM13_CFG0, 0x40007668 +.set CYDEV_PHUB_CFGMEM13_CFG1, 0x4000766c +.set CYDEV_PHUB_CFGMEM14_BASE, 0x40007670 +.set CYDEV_PHUB_CFGMEM14_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM14_CFG0, 0x40007670 +.set CYDEV_PHUB_CFGMEM14_CFG1, 0x40007674 +.set CYDEV_PHUB_CFGMEM15_BASE, 0x40007678 +.set CYDEV_PHUB_CFGMEM15_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM15_CFG0, 0x40007678 +.set CYDEV_PHUB_CFGMEM15_CFG1, 0x4000767c +.set CYDEV_PHUB_CFGMEM16_BASE, 0x40007680 +.set CYDEV_PHUB_CFGMEM16_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM16_CFG0, 0x40007680 +.set CYDEV_PHUB_CFGMEM16_CFG1, 0x40007684 +.set CYDEV_PHUB_CFGMEM17_BASE, 0x40007688 +.set CYDEV_PHUB_CFGMEM17_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM17_CFG0, 0x40007688 +.set CYDEV_PHUB_CFGMEM17_CFG1, 0x4000768c +.set CYDEV_PHUB_CFGMEM18_BASE, 0x40007690 +.set CYDEV_PHUB_CFGMEM18_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM18_CFG0, 0x40007690 +.set CYDEV_PHUB_CFGMEM18_CFG1, 0x40007694 +.set CYDEV_PHUB_CFGMEM19_BASE, 0x40007698 +.set CYDEV_PHUB_CFGMEM19_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM19_CFG0, 0x40007698 +.set CYDEV_PHUB_CFGMEM19_CFG1, 0x4000769c +.set CYDEV_PHUB_CFGMEM20_BASE, 0x400076a0 +.set CYDEV_PHUB_CFGMEM20_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM20_CFG0, 0x400076a0 +.set CYDEV_PHUB_CFGMEM20_CFG1, 0x400076a4 +.set CYDEV_PHUB_CFGMEM21_BASE, 0x400076a8 +.set CYDEV_PHUB_CFGMEM21_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM21_CFG0, 0x400076a8 +.set CYDEV_PHUB_CFGMEM21_CFG1, 0x400076ac +.set CYDEV_PHUB_CFGMEM22_BASE, 0x400076b0 +.set CYDEV_PHUB_CFGMEM22_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM22_CFG0, 0x400076b0 +.set CYDEV_PHUB_CFGMEM22_CFG1, 0x400076b4 +.set CYDEV_PHUB_CFGMEM23_BASE, 0x400076b8 +.set CYDEV_PHUB_CFGMEM23_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM23_CFG0, 0x400076b8 +.set CYDEV_PHUB_CFGMEM23_CFG1, 0x400076bc +.set CYDEV_PHUB_TDMEM0_BASE, 0x40007800 +.set CYDEV_PHUB_TDMEM0_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM0_ORIG_TD0, 0x40007800 +.set CYDEV_PHUB_TDMEM0_ORIG_TD1, 0x40007804 +.set CYDEV_PHUB_TDMEM1_BASE, 0x40007808 +.set CYDEV_PHUB_TDMEM1_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM1_ORIG_TD0, 0x40007808 +.set CYDEV_PHUB_TDMEM1_ORIG_TD1, 0x4000780c +.set CYDEV_PHUB_TDMEM2_BASE, 0x40007810 +.set CYDEV_PHUB_TDMEM2_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM2_ORIG_TD0, 0x40007810 +.set CYDEV_PHUB_TDMEM2_ORIG_TD1, 0x40007814 +.set CYDEV_PHUB_TDMEM3_BASE, 0x40007818 +.set CYDEV_PHUB_TDMEM3_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM3_ORIG_TD0, 0x40007818 +.set CYDEV_PHUB_TDMEM3_ORIG_TD1, 0x4000781c +.set CYDEV_PHUB_TDMEM4_BASE, 0x40007820 +.set CYDEV_PHUB_TDMEM4_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM4_ORIG_TD0, 0x40007820 +.set CYDEV_PHUB_TDMEM4_ORIG_TD1, 0x40007824 +.set CYDEV_PHUB_TDMEM5_BASE, 0x40007828 +.set CYDEV_PHUB_TDMEM5_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM5_ORIG_TD0, 0x40007828 +.set CYDEV_PHUB_TDMEM5_ORIG_TD1, 0x4000782c +.set CYDEV_PHUB_TDMEM6_BASE, 0x40007830 +.set CYDEV_PHUB_TDMEM6_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM6_ORIG_TD0, 0x40007830 +.set CYDEV_PHUB_TDMEM6_ORIG_TD1, 0x40007834 +.set CYDEV_PHUB_TDMEM7_BASE, 0x40007838 +.set CYDEV_PHUB_TDMEM7_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM7_ORIG_TD0, 0x40007838 +.set CYDEV_PHUB_TDMEM7_ORIG_TD1, 0x4000783c +.set CYDEV_PHUB_TDMEM8_BASE, 0x40007840 +.set CYDEV_PHUB_TDMEM8_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM8_ORIG_TD0, 0x40007840 +.set CYDEV_PHUB_TDMEM8_ORIG_TD1, 0x40007844 +.set CYDEV_PHUB_TDMEM9_BASE, 0x40007848 +.set CYDEV_PHUB_TDMEM9_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM9_ORIG_TD0, 0x40007848 +.set CYDEV_PHUB_TDMEM9_ORIG_TD1, 0x4000784c +.set CYDEV_PHUB_TDMEM10_BASE, 0x40007850 +.set CYDEV_PHUB_TDMEM10_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM10_ORIG_TD0, 0x40007850 +.set CYDEV_PHUB_TDMEM10_ORIG_TD1, 0x40007854 +.set CYDEV_PHUB_TDMEM11_BASE, 0x40007858 +.set CYDEV_PHUB_TDMEM11_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM11_ORIG_TD0, 0x40007858 +.set CYDEV_PHUB_TDMEM11_ORIG_TD1, 0x4000785c +.set CYDEV_PHUB_TDMEM12_BASE, 0x40007860 +.set CYDEV_PHUB_TDMEM12_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM12_ORIG_TD0, 0x40007860 +.set CYDEV_PHUB_TDMEM12_ORIG_TD1, 0x40007864 +.set CYDEV_PHUB_TDMEM13_BASE, 0x40007868 +.set CYDEV_PHUB_TDMEM13_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM13_ORIG_TD0, 0x40007868 +.set CYDEV_PHUB_TDMEM13_ORIG_TD1, 0x4000786c +.set CYDEV_PHUB_TDMEM14_BASE, 0x40007870 +.set CYDEV_PHUB_TDMEM14_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM14_ORIG_TD0, 0x40007870 +.set CYDEV_PHUB_TDMEM14_ORIG_TD1, 0x40007874 +.set CYDEV_PHUB_TDMEM15_BASE, 0x40007878 +.set CYDEV_PHUB_TDMEM15_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM15_ORIG_TD0, 0x40007878 +.set CYDEV_PHUB_TDMEM15_ORIG_TD1, 0x4000787c +.set CYDEV_PHUB_TDMEM16_BASE, 0x40007880 +.set CYDEV_PHUB_TDMEM16_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM16_ORIG_TD0, 0x40007880 +.set CYDEV_PHUB_TDMEM16_ORIG_TD1, 0x40007884 +.set CYDEV_PHUB_TDMEM17_BASE, 0x40007888 +.set CYDEV_PHUB_TDMEM17_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM17_ORIG_TD0, 0x40007888 +.set CYDEV_PHUB_TDMEM17_ORIG_TD1, 0x4000788c +.set CYDEV_PHUB_TDMEM18_BASE, 0x40007890 +.set CYDEV_PHUB_TDMEM18_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM18_ORIG_TD0, 0x40007890 +.set CYDEV_PHUB_TDMEM18_ORIG_TD1, 0x40007894 +.set CYDEV_PHUB_TDMEM19_BASE, 0x40007898 +.set CYDEV_PHUB_TDMEM19_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM19_ORIG_TD0, 0x40007898 +.set CYDEV_PHUB_TDMEM19_ORIG_TD1, 0x4000789c +.set CYDEV_PHUB_TDMEM20_BASE, 0x400078a0 +.set CYDEV_PHUB_TDMEM20_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM20_ORIG_TD0, 0x400078a0 +.set CYDEV_PHUB_TDMEM20_ORIG_TD1, 0x400078a4 +.set CYDEV_PHUB_TDMEM21_BASE, 0x400078a8 +.set CYDEV_PHUB_TDMEM21_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM21_ORIG_TD0, 0x400078a8 +.set CYDEV_PHUB_TDMEM21_ORIG_TD1, 0x400078ac +.set CYDEV_PHUB_TDMEM22_BASE, 0x400078b0 +.set CYDEV_PHUB_TDMEM22_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM22_ORIG_TD0, 0x400078b0 +.set CYDEV_PHUB_TDMEM22_ORIG_TD1, 0x400078b4 +.set CYDEV_PHUB_TDMEM23_BASE, 0x400078b8 +.set CYDEV_PHUB_TDMEM23_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM23_ORIG_TD0, 0x400078b8 +.set CYDEV_PHUB_TDMEM23_ORIG_TD1, 0x400078bc +.set CYDEV_PHUB_TDMEM24_BASE, 0x400078c0 +.set CYDEV_PHUB_TDMEM24_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM24_ORIG_TD0, 0x400078c0 +.set CYDEV_PHUB_TDMEM24_ORIG_TD1, 0x400078c4 +.set CYDEV_PHUB_TDMEM25_BASE, 0x400078c8 +.set CYDEV_PHUB_TDMEM25_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM25_ORIG_TD0, 0x400078c8 +.set CYDEV_PHUB_TDMEM25_ORIG_TD1, 0x400078cc +.set CYDEV_PHUB_TDMEM26_BASE, 0x400078d0 +.set CYDEV_PHUB_TDMEM26_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM26_ORIG_TD0, 0x400078d0 +.set CYDEV_PHUB_TDMEM26_ORIG_TD1, 0x400078d4 +.set CYDEV_PHUB_TDMEM27_BASE, 0x400078d8 +.set CYDEV_PHUB_TDMEM27_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM27_ORIG_TD0, 0x400078d8 +.set CYDEV_PHUB_TDMEM27_ORIG_TD1, 0x400078dc +.set CYDEV_PHUB_TDMEM28_BASE, 0x400078e0 +.set CYDEV_PHUB_TDMEM28_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM28_ORIG_TD0, 0x400078e0 +.set CYDEV_PHUB_TDMEM28_ORIG_TD1, 0x400078e4 +.set CYDEV_PHUB_TDMEM29_BASE, 0x400078e8 +.set CYDEV_PHUB_TDMEM29_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM29_ORIG_TD0, 0x400078e8 +.set CYDEV_PHUB_TDMEM29_ORIG_TD1, 0x400078ec +.set CYDEV_PHUB_TDMEM30_BASE, 0x400078f0 +.set CYDEV_PHUB_TDMEM30_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM30_ORIG_TD0, 0x400078f0 +.set CYDEV_PHUB_TDMEM30_ORIG_TD1, 0x400078f4 +.set CYDEV_PHUB_TDMEM31_BASE, 0x400078f8 +.set CYDEV_PHUB_TDMEM31_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM31_ORIG_TD0, 0x400078f8 +.set CYDEV_PHUB_TDMEM31_ORIG_TD1, 0x400078fc +.set CYDEV_PHUB_TDMEM32_BASE, 0x40007900 +.set CYDEV_PHUB_TDMEM32_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM32_ORIG_TD0, 0x40007900 +.set CYDEV_PHUB_TDMEM32_ORIG_TD1, 0x40007904 +.set CYDEV_PHUB_TDMEM33_BASE, 0x40007908 +.set CYDEV_PHUB_TDMEM33_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM33_ORIG_TD0, 0x40007908 +.set CYDEV_PHUB_TDMEM33_ORIG_TD1, 0x4000790c +.set CYDEV_PHUB_TDMEM34_BASE, 0x40007910 +.set CYDEV_PHUB_TDMEM34_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM34_ORIG_TD0, 0x40007910 +.set CYDEV_PHUB_TDMEM34_ORIG_TD1, 0x40007914 +.set CYDEV_PHUB_TDMEM35_BASE, 0x40007918 +.set CYDEV_PHUB_TDMEM35_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM35_ORIG_TD0, 0x40007918 +.set CYDEV_PHUB_TDMEM35_ORIG_TD1, 0x4000791c +.set CYDEV_PHUB_TDMEM36_BASE, 0x40007920 +.set CYDEV_PHUB_TDMEM36_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM36_ORIG_TD0, 0x40007920 +.set CYDEV_PHUB_TDMEM36_ORIG_TD1, 0x40007924 +.set CYDEV_PHUB_TDMEM37_BASE, 0x40007928 +.set CYDEV_PHUB_TDMEM37_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM37_ORIG_TD0, 0x40007928 +.set CYDEV_PHUB_TDMEM37_ORIG_TD1, 0x4000792c +.set CYDEV_PHUB_TDMEM38_BASE, 0x40007930 +.set CYDEV_PHUB_TDMEM38_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM38_ORIG_TD0, 0x40007930 +.set CYDEV_PHUB_TDMEM38_ORIG_TD1, 0x40007934 +.set CYDEV_PHUB_TDMEM39_BASE, 0x40007938 +.set CYDEV_PHUB_TDMEM39_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM39_ORIG_TD0, 0x40007938 +.set CYDEV_PHUB_TDMEM39_ORIG_TD1, 0x4000793c +.set CYDEV_PHUB_TDMEM40_BASE, 0x40007940 +.set CYDEV_PHUB_TDMEM40_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM40_ORIG_TD0, 0x40007940 +.set CYDEV_PHUB_TDMEM40_ORIG_TD1, 0x40007944 +.set CYDEV_PHUB_TDMEM41_BASE, 0x40007948 +.set CYDEV_PHUB_TDMEM41_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM41_ORIG_TD0, 0x40007948 +.set CYDEV_PHUB_TDMEM41_ORIG_TD1, 0x4000794c +.set CYDEV_PHUB_TDMEM42_BASE, 0x40007950 +.set CYDEV_PHUB_TDMEM42_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM42_ORIG_TD0, 0x40007950 +.set CYDEV_PHUB_TDMEM42_ORIG_TD1, 0x40007954 +.set CYDEV_PHUB_TDMEM43_BASE, 0x40007958 +.set CYDEV_PHUB_TDMEM43_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM43_ORIG_TD0, 0x40007958 +.set CYDEV_PHUB_TDMEM43_ORIG_TD1, 0x4000795c +.set CYDEV_PHUB_TDMEM44_BASE, 0x40007960 +.set CYDEV_PHUB_TDMEM44_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM44_ORIG_TD0, 0x40007960 +.set CYDEV_PHUB_TDMEM44_ORIG_TD1, 0x40007964 +.set CYDEV_PHUB_TDMEM45_BASE, 0x40007968 +.set CYDEV_PHUB_TDMEM45_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM45_ORIG_TD0, 0x40007968 +.set CYDEV_PHUB_TDMEM45_ORIG_TD1, 0x4000796c +.set CYDEV_PHUB_TDMEM46_BASE, 0x40007970 +.set CYDEV_PHUB_TDMEM46_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM46_ORIG_TD0, 0x40007970 +.set CYDEV_PHUB_TDMEM46_ORIG_TD1, 0x40007974 +.set CYDEV_PHUB_TDMEM47_BASE, 0x40007978 +.set CYDEV_PHUB_TDMEM47_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM47_ORIG_TD0, 0x40007978 +.set CYDEV_PHUB_TDMEM47_ORIG_TD1, 0x4000797c +.set CYDEV_PHUB_TDMEM48_BASE, 0x40007980 +.set CYDEV_PHUB_TDMEM48_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM48_ORIG_TD0, 0x40007980 +.set CYDEV_PHUB_TDMEM48_ORIG_TD1, 0x40007984 +.set CYDEV_PHUB_TDMEM49_BASE, 0x40007988 +.set CYDEV_PHUB_TDMEM49_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM49_ORIG_TD0, 0x40007988 +.set CYDEV_PHUB_TDMEM49_ORIG_TD1, 0x4000798c +.set CYDEV_PHUB_TDMEM50_BASE, 0x40007990 +.set CYDEV_PHUB_TDMEM50_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM50_ORIG_TD0, 0x40007990 +.set CYDEV_PHUB_TDMEM50_ORIG_TD1, 0x40007994 +.set CYDEV_PHUB_TDMEM51_BASE, 0x40007998 +.set CYDEV_PHUB_TDMEM51_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM51_ORIG_TD0, 0x40007998 +.set CYDEV_PHUB_TDMEM51_ORIG_TD1, 0x4000799c +.set CYDEV_PHUB_TDMEM52_BASE, 0x400079a0 +.set CYDEV_PHUB_TDMEM52_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM52_ORIG_TD0, 0x400079a0 +.set CYDEV_PHUB_TDMEM52_ORIG_TD1, 0x400079a4 +.set CYDEV_PHUB_TDMEM53_BASE, 0x400079a8 +.set CYDEV_PHUB_TDMEM53_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM53_ORIG_TD0, 0x400079a8 +.set CYDEV_PHUB_TDMEM53_ORIG_TD1, 0x400079ac +.set CYDEV_PHUB_TDMEM54_BASE, 0x400079b0 +.set CYDEV_PHUB_TDMEM54_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM54_ORIG_TD0, 0x400079b0 +.set CYDEV_PHUB_TDMEM54_ORIG_TD1, 0x400079b4 +.set CYDEV_PHUB_TDMEM55_BASE, 0x400079b8 +.set CYDEV_PHUB_TDMEM55_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM55_ORIG_TD0, 0x400079b8 +.set CYDEV_PHUB_TDMEM55_ORIG_TD1, 0x400079bc +.set CYDEV_PHUB_TDMEM56_BASE, 0x400079c0 +.set CYDEV_PHUB_TDMEM56_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM56_ORIG_TD0, 0x400079c0 +.set CYDEV_PHUB_TDMEM56_ORIG_TD1, 0x400079c4 +.set CYDEV_PHUB_TDMEM57_BASE, 0x400079c8 +.set CYDEV_PHUB_TDMEM57_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM57_ORIG_TD0, 0x400079c8 +.set CYDEV_PHUB_TDMEM57_ORIG_TD1, 0x400079cc +.set CYDEV_PHUB_TDMEM58_BASE, 0x400079d0 +.set CYDEV_PHUB_TDMEM58_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM58_ORIG_TD0, 0x400079d0 +.set CYDEV_PHUB_TDMEM58_ORIG_TD1, 0x400079d4 +.set CYDEV_PHUB_TDMEM59_BASE, 0x400079d8 +.set CYDEV_PHUB_TDMEM59_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM59_ORIG_TD0, 0x400079d8 +.set CYDEV_PHUB_TDMEM59_ORIG_TD1, 0x400079dc +.set CYDEV_PHUB_TDMEM60_BASE, 0x400079e0 +.set CYDEV_PHUB_TDMEM60_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM60_ORIG_TD0, 0x400079e0 +.set CYDEV_PHUB_TDMEM60_ORIG_TD1, 0x400079e4 +.set CYDEV_PHUB_TDMEM61_BASE, 0x400079e8 +.set CYDEV_PHUB_TDMEM61_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM61_ORIG_TD0, 0x400079e8 +.set CYDEV_PHUB_TDMEM61_ORIG_TD1, 0x400079ec +.set CYDEV_PHUB_TDMEM62_BASE, 0x400079f0 +.set CYDEV_PHUB_TDMEM62_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM62_ORIG_TD0, 0x400079f0 +.set CYDEV_PHUB_TDMEM62_ORIG_TD1, 0x400079f4 +.set CYDEV_PHUB_TDMEM63_BASE, 0x400079f8 +.set CYDEV_PHUB_TDMEM63_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM63_ORIG_TD0, 0x400079f8 +.set CYDEV_PHUB_TDMEM63_ORIG_TD1, 0x400079fc +.set CYDEV_PHUB_TDMEM64_BASE, 0x40007a00 +.set CYDEV_PHUB_TDMEM64_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM64_ORIG_TD0, 0x40007a00 +.set CYDEV_PHUB_TDMEM64_ORIG_TD1, 0x40007a04 +.set CYDEV_PHUB_TDMEM65_BASE, 0x40007a08 +.set CYDEV_PHUB_TDMEM65_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM65_ORIG_TD0, 0x40007a08 +.set CYDEV_PHUB_TDMEM65_ORIG_TD1, 0x40007a0c +.set CYDEV_PHUB_TDMEM66_BASE, 0x40007a10 +.set CYDEV_PHUB_TDMEM66_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM66_ORIG_TD0, 0x40007a10 +.set CYDEV_PHUB_TDMEM66_ORIG_TD1, 0x40007a14 +.set CYDEV_PHUB_TDMEM67_BASE, 0x40007a18 +.set CYDEV_PHUB_TDMEM67_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM67_ORIG_TD0, 0x40007a18 +.set CYDEV_PHUB_TDMEM67_ORIG_TD1, 0x40007a1c +.set CYDEV_PHUB_TDMEM68_BASE, 0x40007a20 +.set CYDEV_PHUB_TDMEM68_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM68_ORIG_TD0, 0x40007a20 +.set CYDEV_PHUB_TDMEM68_ORIG_TD1, 0x40007a24 +.set CYDEV_PHUB_TDMEM69_BASE, 0x40007a28 +.set CYDEV_PHUB_TDMEM69_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM69_ORIG_TD0, 0x40007a28 +.set CYDEV_PHUB_TDMEM69_ORIG_TD1, 0x40007a2c +.set CYDEV_PHUB_TDMEM70_BASE, 0x40007a30 +.set CYDEV_PHUB_TDMEM70_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM70_ORIG_TD0, 0x40007a30 +.set CYDEV_PHUB_TDMEM70_ORIG_TD1, 0x40007a34 +.set CYDEV_PHUB_TDMEM71_BASE, 0x40007a38 +.set CYDEV_PHUB_TDMEM71_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM71_ORIG_TD0, 0x40007a38 +.set CYDEV_PHUB_TDMEM71_ORIG_TD1, 0x40007a3c +.set CYDEV_PHUB_TDMEM72_BASE, 0x40007a40 +.set CYDEV_PHUB_TDMEM72_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM72_ORIG_TD0, 0x40007a40 +.set CYDEV_PHUB_TDMEM72_ORIG_TD1, 0x40007a44 +.set CYDEV_PHUB_TDMEM73_BASE, 0x40007a48 +.set CYDEV_PHUB_TDMEM73_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM73_ORIG_TD0, 0x40007a48 +.set CYDEV_PHUB_TDMEM73_ORIG_TD1, 0x40007a4c +.set CYDEV_PHUB_TDMEM74_BASE, 0x40007a50 +.set CYDEV_PHUB_TDMEM74_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM74_ORIG_TD0, 0x40007a50 +.set CYDEV_PHUB_TDMEM74_ORIG_TD1, 0x40007a54 +.set CYDEV_PHUB_TDMEM75_BASE, 0x40007a58 +.set CYDEV_PHUB_TDMEM75_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM75_ORIG_TD0, 0x40007a58 +.set CYDEV_PHUB_TDMEM75_ORIG_TD1, 0x40007a5c +.set CYDEV_PHUB_TDMEM76_BASE, 0x40007a60 +.set CYDEV_PHUB_TDMEM76_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM76_ORIG_TD0, 0x40007a60 +.set CYDEV_PHUB_TDMEM76_ORIG_TD1, 0x40007a64 +.set CYDEV_PHUB_TDMEM77_BASE, 0x40007a68 +.set CYDEV_PHUB_TDMEM77_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM77_ORIG_TD0, 0x40007a68 +.set CYDEV_PHUB_TDMEM77_ORIG_TD1, 0x40007a6c +.set CYDEV_PHUB_TDMEM78_BASE, 0x40007a70 +.set CYDEV_PHUB_TDMEM78_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM78_ORIG_TD0, 0x40007a70 +.set CYDEV_PHUB_TDMEM78_ORIG_TD1, 0x40007a74 +.set CYDEV_PHUB_TDMEM79_BASE, 0x40007a78 +.set CYDEV_PHUB_TDMEM79_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM79_ORIG_TD0, 0x40007a78 +.set CYDEV_PHUB_TDMEM79_ORIG_TD1, 0x40007a7c +.set CYDEV_PHUB_TDMEM80_BASE, 0x40007a80 +.set CYDEV_PHUB_TDMEM80_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM80_ORIG_TD0, 0x40007a80 +.set CYDEV_PHUB_TDMEM80_ORIG_TD1, 0x40007a84 +.set CYDEV_PHUB_TDMEM81_BASE, 0x40007a88 +.set CYDEV_PHUB_TDMEM81_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM81_ORIG_TD0, 0x40007a88 +.set CYDEV_PHUB_TDMEM81_ORIG_TD1, 0x40007a8c +.set CYDEV_PHUB_TDMEM82_BASE, 0x40007a90 +.set CYDEV_PHUB_TDMEM82_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM82_ORIG_TD0, 0x40007a90 +.set CYDEV_PHUB_TDMEM82_ORIG_TD1, 0x40007a94 +.set CYDEV_PHUB_TDMEM83_BASE, 0x40007a98 +.set CYDEV_PHUB_TDMEM83_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM83_ORIG_TD0, 0x40007a98 +.set CYDEV_PHUB_TDMEM83_ORIG_TD1, 0x40007a9c +.set CYDEV_PHUB_TDMEM84_BASE, 0x40007aa0 +.set CYDEV_PHUB_TDMEM84_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM84_ORIG_TD0, 0x40007aa0 +.set CYDEV_PHUB_TDMEM84_ORIG_TD1, 0x40007aa4 +.set CYDEV_PHUB_TDMEM85_BASE, 0x40007aa8 +.set CYDEV_PHUB_TDMEM85_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM85_ORIG_TD0, 0x40007aa8 +.set CYDEV_PHUB_TDMEM85_ORIG_TD1, 0x40007aac +.set CYDEV_PHUB_TDMEM86_BASE, 0x40007ab0 +.set CYDEV_PHUB_TDMEM86_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM86_ORIG_TD0, 0x40007ab0 +.set CYDEV_PHUB_TDMEM86_ORIG_TD1, 0x40007ab4 +.set CYDEV_PHUB_TDMEM87_BASE, 0x40007ab8 +.set CYDEV_PHUB_TDMEM87_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM87_ORIG_TD0, 0x40007ab8 +.set CYDEV_PHUB_TDMEM87_ORIG_TD1, 0x40007abc +.set CYDEV_PHUB_TDMEM88_BASE, 0x40007ac0 +.set CYDEV_PHUB_TDMEM88_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM88_ORIG_TD0, 0x40007ac0 +.set CYDEV_PHUB_TDMEM88_ORIG_TD1, 0x40007ac4 +.set CYDEV_PHUB_TDMEM89_BASE, 0x40007ac8 +.set CYDEV_PHUB_TDMEM89_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM89_ORIG_TD0, 0x40007ac8 +.set CYDEV_PHUB_TDMEM89_ORIG_TD1, 0x40007acc +.set CYDEV_PHUB_TDMEM90_BASE, 0x40007ad0 +.set CYDEV_PHUB_TDMEM90_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM90_ORIG_TD0, 0x40007ad0 +.set CYDEV_PHUB_TDMEM90_ORIG_TD1, 0x40007ad4 +.set CYDEV_PHUB_TDMEM91_BASE, 0x40007ad8 +.set CYDEV_PHUB_TDMEM91_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM91_ORIG_TD0, 0x40007ad8 +.set CYDEV_PHUB_TDMEM91_ORIG_TD1, 0x40007adc +.set CYDEV_PHUB_TDMEM92_BASE, 0x40007ae0 +.set CYDEV_PHUB_TDMEM92_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM92_ORIG_TD0, 0x40007ae0 +.set CYDEV_PHUB_TDMEM92_ORIG_TD1, 0x40007ae4 +.set CYDEV_PHUB_TDMEM93_BASE, 0x40007ae8 +.set CYDEV_PHUB_TDMEM93_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM93_ORIG_TD0, 0x40007ae8 +.set CYDEV_PHUB_TDMEM93_ORIG_TD1, 0x40007aec +.set CYDEV_PHUB_TDMEM94_BASE, 0x40007af0 +.set CYDEV_PHUB_TDMEM94_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM94_ORIG_TD0, 0x40007af0 +.set CYDEV_PHUB_TDMEM94_ORIG_TD1, 0x40007af4 +.set CYDEV_PHUB_TDMEM95_BASE, 0x40007af8 +.set CYDEV_PHUB_TDMEM95_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM95_ORIG_TD0, 0x40007af8 +.set CYDEV_PHUB_TDMEM95_ORIG_TD1, 0x40007afc +.set CYDEV_PHUB_TDMEM96_BASE, 0x40007b00 +.set CYDEV_PHUB_TDMEM96_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM96_ORIG_TD0, 0x40007b00 +.set CYDEV_PHUB_TDMEM96_ORIG_TD1, 0x40007b04 +.set CYDEV_PHUB_TDMEM97_BASE, 0x40007b08 +.set CYDEV_PHUB_TDMEM97_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM97_ORIG_TD0, 0x40007b08 +.set CYDEV_PHUB_TDMEM97_ORIG_TD1, 0x40007b0c +.set CYDEV_PHUB_TDMEM98_BASE, 0x40007b10 +.set CYDEV_PHUB_TDMEM98_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM98_ORIG_TD0, 0x40007b10 +.set CYDEV_PHUB_TDMEM98_ORIG_TD1, 0x40007b14 +.set CYDEV_PHUB_TDMEM99_BASE, 0x40007b18 +.set CYDEV_PHUB_TDMEM99_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM99_ORIG_TD0, 0x40007b18 +.set CYDEV_PHUB_TDMEM99_ORIG_TD1, 0x40007b1c +.set CYDEV_PHUB_TDMEM100_BASE, 0x40007b20 +.set CYDEV_PHUB_TDMEM100_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM100_ORIG_TD0, 0x40007b20 +.set CYDEV_PHUB_TDMEM100_ORIG_TD1, 0x40007b24 +.set CYDEV_PHUB_TDMEM101_BASE, 0x40007b28 +.set CYDEV_PHUB_TDMEM101_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM101_ORIG_TD0, 0x40007b28 +.set CYDEV_PHUB_TDMEM101_ORIG_TD1, 0x40007b2c +.set CYDEV_PHUB_TDMEM102_BASE, 0x40007b30 +.set CYDEV_PHUB_TDMEM102_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM102_ORIG_TD0, 0x40007b30 +.set CYDEV_PHUB_TDMEM102_ORIG_TD1, 0x40007b34 +.set CYDEV_PHUB_TDMEM103_BASE, 0x40007b38 +.set CYDEV_PHUB_TDMEM103_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM103_ORIG_TD0, 0x40007b38 +.set CYDEV_PHUB_TDMEM103_ORIG_TD1, 0x40007b3c +.set CYDEV_PHUB_TDMEM104_BASE, 0x40007b40 +.set CYDEV_PHUB_TDMEM104_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM104_ORIG_TD0, 0x40007b40 +.set CYDEV_PHUB_TDMEM104_ORIG_TD1, 0x40007b44 +.set CYDEV_PHUB_TDMEM105_BASE, 0x40007b48 +.set CYDEV_PHUB_TDMEM105_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM105_ORIG_TD0, 0x40007b48 +.set CYDEV_PHUB_TDMEM105_ORIG_TD1, 0x40007b4c +.set CYDEV_PHUB_TDMEM106_BASE, 0x40007b50 +.set CYDEV_PHUB_TDMEM106_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM106_ORIG_TD0, 0x40007b50 +.set CYDEV_PHUB_TDMEM106_ORIG_TD1, 0x40007b54 +.set CYDEV_PHUB_TDMEM107_BASE, 0x40007b58 +.set CYDEV_PHUB_TDMEM107_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM107_ORIG_TD0, 0x40007b58 +.set CYDEV_PHUB_TDMEM107_ORIG_TD1, 0x40007b5c +.set CYDEV_PHUB_TDMEM108_BASE, 0x40007b60 +.set CYDEV_PHUB_TDMEM108_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM108_ORIG_TD0, 0x40007b60 +.set CYDEV_PHUB_TDMEM108_ORIG_TD1, 0x40007b64 +.set CYDEV_PHUB_TDMEM109_BASE, 0x40007b68 +.set CYDEV_PHUB_TDMEM109_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM109_ORIG_TD0, 0x40007b68 +.set CYDEV_PHUB_TDMEM109_ORIG_TD1, 0x40007b6c +.set CYDEV_PHUB_TDMEM110_BASE, 0x40007b70 +.set CYDEV_PHUB_TDMEM110_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM110_ORIG_TD0, 0x40007b70 +.set CYDEV_PHUB_TDMEM110_ORIG_TD1, 0x40007b74 +.set CYDEV_PHUB_TDMEM111_BASE, 0x40007b78 +.set CYDEV_PHUB_TDMEM111_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM111_ORIG_TD0, 0x40007b78 +.set CYDEV_PHUB_TDMEM111_ORIG_TD1, 0x40007b7c +.set CYDEV_PHUB_TDMEM112_BASE, 0x40007b80 +.set CYDEV_PHUB_TDMEM112_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM112_ORIG_TD0, 0x40007b80 +.set CYDEV_PHUB_TDMEM112_ORIG_TD1, 0x40007b84 +.set CYDEV_PHUB_TDMEM113_BASE, 0x40007b88 +.set CYDEV_PHUB_TDMEM113_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM113_ORIG_TD0, 0x40007b88 +.set CYDEV_PHUB_TDMEM113_ORIG_TD1, 0x40007b8c +.set CYDEV_PHUB_TDMEM114_BASE, 0x40007b90 +.set CYDEV_PHUB_TDMEM114_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM114_ORIG_TD0, 0x40007b90 +.set CYDEV_PHUB_TDMEM114_ORIG_TD1, 0x40007b94 +.set CYDEV_PHUB_TDMEM115_BASE, 0x40007b98 +.set CYDEV_PHUB_TDMEM115_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM115_ORIG_TD0, 0x40007b98 +.set CYDEV_PHUB_TDMEM115_ORIG_TD1, 0x40007b9c +.set CYDEV_PHUB_TDMEM116_BASE, 0x40007ba0 +.set CYDEV_PHUB_TDMEM116_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM116_ORIG_TD0, 0x40007ba0 +.set CYDEV_PHUB_TDMEM116_ORIG_TD1, 0x40007ba4 +.set CYDEV_PHUB_TDMEM117_BASE, 0x40007ba8 +.set CYDEV_PHUB_TDMEM117_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM117_ORIG_TD0, 0x40007ba8 +.set CYDEV_PHUB_TDMEM117_ORIG_TD1, 0x40007bac +.set CYDEV_PHUB_TDMEM118_BASE, 0x40007bb0 +.set CYDEV_PHUB_TDMEM118_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM118_ORIG_TD0, 0x40007bb0 +.set CYDEV_PHUB_TDMEM118_ORIG_TD1, 0x40007bb4 +.set CYDEV_PHUB_TDMEM119_BASE, 0x40007bb8 +.set CYDEV_PHUB_TDMEM119_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM119_ORIG_TD0, 0x40007bb8 +.set CYDEV_PHUB_TDMEM119_ORIG_TD1, 0x40007bbc +.set CYDEV_PHUB_TDMEM120_BASE, 0x40007bc0 +.set CYDEV_PHUB_TDMEM120_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM120_ORIG_TD0, 0x40007bc0 +.set CYDEV_PHUB_TDMEM120_ORIG_TD1, 0x40007bc4 +.set CYDEV_PHUB_TDMEM121_BASE, 0x40007bc8 +.set CYDEV_PHUB_TDMEM121_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM121_ORIG_TD0, 0x40007bc8 +.set CYDEV_PHUB_TDMEM121_ORIG_TD1, 0x40007bcc +.set CYDEV_PHUB_TDMEM122_BASE, 0x40007bd0 +.set CYDEV_PHUB_TDMEM122_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM122_ORIG_TD0, 0x40007bd0 +.set CYDEV_PHUB_TDMEM122_ORIG_TD1, 0x40007bd4 +.set CYDEV_PHUB_TDMEM123_BASE, 0x40007bd8 +.set CYDEV_PHUB_TDMEM123_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM123_ORIG_TD0, 0x40007bd8 +.set CYDEV_PHUB_TDMEM123_ORIG_TD1, 0x40007bdc +.set CYDEV_PHUB_TDMEM124_BASE, 0x40007be0 +.set CYDEV_PHUB_TDMEM124_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM124_ORIG_TD0, 0x40007be0 +.set CYDEV_PHUB_TDMEM124_ORIG_TD1, 0x40007be4 +.set CYDEV_PHUB_TDMEM125_BASE, 0x40007be8 +.set CYDEV_PHUB_TDMEM125_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM125_ORIG_TD0, 0x40007be8 +.set CYDEV_PHUB_TDMEM125_ORIG_TD1, 0x40007bec +.set CYDEV_PHUB_TDMEM126_BASE, 0x40007bf0 +.set CYDEV_PHUB_TDMEM126_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM126_ORIG_TD0, 0x40007bf0 +.set CYDEV_PHUB_TDMEM126_ORIG_TD1, 0x40007bf4 +.set CYDEV_PHUB_TDMEM127_BASE, 0x40007bf8 +.set CYDEV_PHUB_TDMEM127_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM127_ORIG_TD0, 0x40007bf8 +.set CYDEV_PHUB_TDMEM127_ORIG_TD1, 0x40007bfc +.set CYDEV_EE_BASE, 0x40008000 +.set CYDEV_EE_SIZE, 0x00000800 +.set CYDEV_EE_DATA_MBASE, 0x40008000 +.set CYDEV_EE_DATA_MSIZE, 0x00000800 +.set CYDEV_CAN0_BASE, 0x4000a000 +.set CYDEV_CAN0_SIZE, 0x000002a0 +.set CYDEV_CAN0_CSR_BASE, 0x4000a000 +.set CYDEV_CAN0_CSR_SIZE, 0x00000018 +.set CYDEV_CAN0_CSR_INT_SR, 0x4000a000 +.set CYDEV_CAN0_CSR_INT_EN, 0x4000a004 +.set CYDEV_CAN0_CSR_BUF_SR, 0x4000a008 +.set CYDEV_CAN0_CSR_ERR_SR, 0x4000a00c +.set CYDEV_CAN0_CSR_CMD, 0x4000a010 +.set CYDEV_CAN0_CSR_CFG, 0x4000a014 +.set CYDEV_CAN0_TX0_BASE, 0x4000a020 +.set CYDEV_CAN0_TX0_SIZE, 0x00000010 +.set CYDEV_CAN0_TX0_CMD, 0x4000a020 +.set CYDEV_CAN0_TX0_ID, 0x4000a024 +.set CYDEV_CAN0_TX0_DH, 0x4000a028 +.set CYDEV_CAN0_TX0_DL, 0x4000a02c +.set CYDEV_CAN0_TX1_BASE, 0x4000a030 +.set CYDEV_CAN0_TX1_SIZE, 0x00000010 +.set CYDEV_CAN0_TX1_CMD, 0x4000a030 +.set CYDEV_CAN0_TX1_ID, 0x4000a034 +.set CYDEV_CAN0_TX1_DH, 0x4000a038 +.set CYDEV_CAN0_TX1_DL, 0x4000a03c +.set CYDEV_CAN0_TX2_BASE, 0x4000a040 +.set CYDEV_CAN0_TX2_SIZE, 0x00000010 +.set CYDEV_CAN0_TX2_CMD, 0x4000a040 +.set CYDEV_CAN0_TX2_ID, 0x4000a044 +.set CYDEV_CAN0_TX2_DH, 0x4000a048 +.set CYDEV_CAN0_TX2_DL, 0x4000a04c +.set CYDEV_CAN0_TX3_BASE, 0x4000a050 +.set CYDEV_CAN0_TX3_SIZE, 0x00000010 +.set CYDEV_CAN0_TX3_CMD, 0x4000a050 +.set CYDEV_CAN0_TX3_ID, 0x4000a054 +.set CYDEV_CAN0_TX3_DH, 0x4000a058 +.set CYDEV_CAN0_TX3_DL, 0x4000a05c +.set CYDEV_CAN0_TX4_BASE, 0x4000a060 +.set CYDEV_CAN0_TX4_SIZE, 0x00000010 +.set CYDEV_CAN0_TX4_CMD, 0x4000a060 +.set CYDEV_CAN0_TX4_ID, 0x4000a064 +.set CYDEV_CAN0_TX4_DH, 0x4000a068 +.set CYDEV_CAN0_TX4_DL, 0x4000a06c +.set CYDEV_CAN0_TX5_BASE, 0x4000a070 +.set CYDEV_CAN0_TX5_SIZE, 0x00000010 +.set CYDEV_CAN0_TX5_CMD, 0x4000a070 +.set CYDEV_CAN0_TX5_ID, 0x4000a074 +.set CYDEV_CAN0_TX5_DH, 0x4000a078 +.set CYDEV_CAN0_TX5_DL, 0x4000a07c +.set CYDEV_CAN0_TX6_BASE, 0x4000a080 +.set CYDEV_CAN0_TX6_SIZE, 0x00000010 +.set CYDEV_CAN0_TX6_CMD, 0x4000a080 +.set CYDEV_CAN0_TX6_ID, 0x4000a084 +.set CYDEV_CAN0_TX6_DH, 0x4000a088 +.set CYDEV_CAN0_TX6_DL, 0x4000a08c +.set CYDEV_CAN0_TX7_BASE, 0x4000a090 +.set CYDEV_CAN0_TX7_SIZE, 0x00000010 +.set CYDEV_CAN0_TX7_CMD, 0x4000a090 +.set CYDEV_CAN0_TX7_ID, 0x4000a094 +.set CYDEV_CAN0_TX7_DH, 0x4000a098 +.set CYDEV_CAN0_TX7_DL, 0x4000a09c +.set CYDEV_CAN0_RX0_BASE, 0x4000a0a0 +.set CYDEV_CAN0_RX0_SIZE, 0x00000020 +.set CYDEV_CAN0_RX0_CMD, 0x4000a0a0 +.set CYDEV_CAN0_RX0_ID, 0x4000a0a4 +.set CYDEV_CAN0_RX0_DH, 0x4000a0a8 +.set CYDEV_CAN0_RX0_DL, 0x4000a0ac +.set CYDEV_CAN0_RX0_AMR, 0x4000a0b0 +.set CYDEV_CAN0_RX0_ACR, 0x4000a0b4 +.set CYDEV_CAN0_RX0_AMRD, 0x4000a0b8 +.set CYDEV_CAN0_RX0_ACRD, 0x4000a0bc +.set CYDEV_CAN0_RX1_BASE, 0x4000a0c0 +.set CYDEV_CAN0_RX1_SIZE, 0x00000020 +.set CYDEV_CAN0_RX1_CMD, 0x4000a0c0 +.set CYDEV_CAN0_RX1_ID, 0x4000a0c4 +.set CYDEV_CAN0_RX1_DH, 0x4000a0c8 +.set CYDEV_CAN0_RX1_DL, 0x4000a0cc +.set CYDEV_CAN0_RX1_AMR, 0x4000a0d0 +.set CYDEV_CAN0_RX1_ACR, 0x4000a0d4 +.set CYDEV_CAN0_RX1_AMRD, 0x4000a0d8 +.set CYDEV_CAN0_RX1_ACRD, 0x4000a0dc +.set CYDEV_CAN0_RX2_BASE, 0x4000a0e0 +.set CYDEV_CAN0_RX2_SIZE, 0x00000020 +.set CYDEV_CAN0_RX2_CMD, 0x4000a0e0 +.set CYDEV_CAN0_RX2_ID, 0x4000a0e4 +.set CYDEV_CAN0_RX2_DH, 0x4000a0e8 +.set CYDEV_CAN0_RX2_DL, 0x4000a0ec +.set CYDEV_CAN0_RX2_AMR, 0x4000a0f0 +.set CYDEV_CAN0_RX2_ACR, 0x4000a0f4 +.set CYDEV_CAN0_RX2_AMRD, 0x4000a0f8 +.set CYDEV_CAN0_RX2_ACRD, 0x4000a0fc +.set CYDEV_CAN0_RX3_BASE, 0x4000a100 +.set CYDEV_CAN0_RX3_SIZE, 0x00000020 +.set CYDEV_CAN0_RX3_CMD, 0x4000a100 +.set CYDEV_CAN0_RX3_ID, 0x4000a104 +.set CYDEV_CAN0_RX3_DH, 0x4000a108 +.set CYDEV_CAN0_RX3_DL, 0x4000a10c +.set CYDEV_CAN0_RX3_AMR, 0x4000a110 +.set CYDEV_CAN0_RX3_ACR, 0x4000a114 +.set CYDEV_CAN0_RX3_AMRD, 0x4000a118 +.set CYDEV_CAN0_RX3_ACRD, 0x4000a11c +.set CYDEV_CAN0_RX4_BASE, 0x4000a120 +.set CYDEV_CAN0_RX4_SIZE, 0x00000020 +.set CYDEV_CAN0_RX4_CMD, 0x4000a120 +.set CYDEV_CAN0_RX4_ID, 0x4000a124 +.set CYDEV_CAN0_RX4_DH, 0x4000a128 +.set CYDEV_CAN0_RX4_DL, 0x4000a12c +.set CYDEV_CAN0_RX4_AMR, 0x4000a130 +.set CYDEV_CAN0_RX4_ACR, 0x4000a134 +.set CYDEV_CAN0_RX4_AMRD, 0x4000a138 +.set CYDEV_CAN0_RX4_ACRD, 0x4000a13c +.set CYDEV_CAN0_RX5_BASE, 0x4000a140 +.set CYDEV_CAN0_RX5_SIZE, 0x00000020 +.set CYDEV_CAN0_RX5_CMD, 0x4000a140 +.set CYDEV_CAN0_RX5_ID, 0x4000a144 +.set CYDEV_CAN0_RX5_DH, 0x4000a148 +.set CYDEV_CAN0_RX5_DL, 0x4000a14c +.set CYDEV_CAN0_RX5_AMR, 0x4000a150 +.set CYDEV_CAN0_RX5_ACR, 0x4000a154 +.set CYDEV_CAN0_RX5_AMRD, 0x4000a158 +.set CYDEV_CAN0_RX5_ACRD, 0x4000a15c +.set CYDEV_CAN0_RX6_BASE, 0x4000a160 +.set CYDEV_CAN0_RX6_SIZE, 0x00000020 +.set CYDEV_CAN0_RX6_CMD, 0x4000a160 +.set CYDEV_CAN0_RX6_ID, 0x4000a164 +.set CYDEV_CAN0_RX6_DH, 0x4000a168 +.set CYDEV_CAN0_RX6_DL, 0x4000a16c +.set CYDEV_CAN0_RX6_AMR, 0x4000a170 +.set CYDEV_CAN0_RX6_ACR, 0x4000a174 +.set CYDEV_CAN0_RX6_AMRD, 0x4000a178 +.set CYDEV_CAN0_RX6_ACRD, 0x4000a17c +.set CYDEV_CAN0_RX7_BASE, 0x4000a180 +.set CYDEV_CAN0_RX7_SIZE, 0x00000020 +.set CYDEV_CAN0_RX7_CMD, 0x4000a180 +.set CYDEV_CAN0_RX7_ID, 0x4000a184 +.set CYDEV_CAN0_RX7_DH, 0x4000a188 +.set CYDEV_CAN0_RX7_DL, 0x4000a18c +.set CYDEV_CAN0_RX7_AMR, 0x4000a190 +.set CYDEV_CAN0_RX7_ACR, 0x4000a194 +.set CYDEV_CAN0_RX7_AMRD, 0x4000a198 +.set CYDEV_CAN0_RX7_ACRD, 0x4000a19c +.set CYDEV_CAN0_RX8_BASE, 0x4000a1a0 +.set CYDEV_CAN0_RX8_SIZE, 0x00000020 +.set CYDEV_CAN0_RX8_CMD, 0x4000a1a0 +.set CYDEV_CAN0_RX8_ID, 0x4000a1a4 +.set CYDEV_CAN0_RX8_DH, 0x4000a1a8 +.set CYDEV_CAN0_RX8_DL, 0x4000a1ac +.set CYDEV_CAN0_RX8_AMR, 0x4000a1b0 +.set CYDEV_CAN0_RX8_ACR, 0x4000a1b4 +.set CYDEV_CAN0_RX8_AMRD, 0x4000a1b8 +.set CYDEV_CAN0_RX8_ACRD, 0x4000a1bc +.set CYDEV_CAN0_RX9_BASE, 0x4000a1c0 +.set CYDEV_CAN0_RX9_SIZE, 0x00000020 +.set CYDEV_CAN0_RX9_CMD, 0x4000a1c0 +.set CYDEV_CAN0_RX9_ID, 0x4000a1c4 +.set CYDEV_CAN0_RX9_DH, 0x4000a1c8 +.set CYDEV_CAN0_RX9_DL, 0x4000a1cc +.set CYDEV_CAN0_RX9_AMR, 0x4000a1d0 +.set CYDEV_CAN0_RX9_ACR, 0x4000a1d4 +.set CYDEV_CAN0_RX9_AMRD, 0x4000a1d8 +.set CYDEV_CAN0_RX9_ACRD, 0x4000a1dc +.set CYDEV_CAN0_RX10_BASE, 0x4000a1e0 +.set CYDEV_CAN0_RX10_SIZE, 0x00000020 +.set CYDEV_CAN0_RX10_CMD, 0x4000a1e0 +.set CYDEV_CAN0_RX10_ID, 0x4000a1e4 +.set CYDEV_CAN0_RX10_DH, 0x4000a1e8 +.set CYDEV_CAN0_RX10_DL, 0x4000a1ec +.set CYDEV_CAN0_RX10_AMR, 0x4000a1f0 +.set CYDEV_CAN0_RX10_ACR, 0x4000a1f4 +.set CYDEV_CAN0_RX10_AMRD, 0x4000a1f8 +.set CYDEV_CAN0_RX10_ACRD, 0x4000a1fc +.set CYDEV_CAN0_RX11_BASE, 0x4000a200 +.set CYDEV_CAN0_RX11_SIZE, 0x00000020 +.set CYDEV_CAN0_RX11_CMD, 0x4000a200 +.set CYDEV_CAN0_RX11_ID, 0x4000a204 +.set CYDEV_CAN0_RX11_DH, 0x4000a208 +.set CYDEV_CAN0_RX11_DL, 0x4000a20c +.set CYDEV_CAN0_RX11_AMR, 0x4000a210 +.set CYDEV_CAN0_RX11_ACR, 0x4000a214 +.set CYDEV_CAN0_RX11_AMRD, 0x4000a218 +.set CYDEV_CAN0_RX11_ACRD, 0x4000a21c +.set CYDEV_CAN0_RX12_BASE, 0x4000a220 +.set CYDEV_CAN0_RX12_SIZE, 0x00000020 +.set CYDEV_CAN0_RX12_CMD, 0x4000a220 +.set CYDEV_CAN0_RX12_ID, 0x4000a224 +.set CYDEV_CAN0_RX12_DH, 0x4000a228 +.set CYDEV_CAN0_RX12_DL, 0x4000a22c +.set CYDEV_CAN0_RX12_AMR, 0x4000a230 +.set CYDEV_CAN0_RX12_ACR, 0x4000a234 +.set CYDEV_CAN0_RX12_AMRD, 0x4000a238 +.set CYDEV_CAN0_RX12_ACRD, 0x4000a23c +.set CYDEV_CAN0_RX13_BASE, 0x4000a240 +.set CYDEV_CAN0_RX13_SIZE, 0x00000020 +.set CYDEV_CAN0_RX13_CMD, 0x4000a240 +.set CYDEV_CAN0_RX13_ID, 0x4000a244 +.set CYDEV_CAN0_RX13_DH, 0x4000a248 +.set CYDEV_CAN0_RX13_DL, 0x4000a24c +.set CYDEV_CAN0_RX13_AMR, 0x4000a250 +.set CYDEV_CAN0_RX13_ACR, 0x4000a254 +.set CYDEV_CAN0_RX13_AMRD, 0x4000a258 +.set CYDEV_CAN0_RX13_ACRD, 0x4000a25c +.set CYDEV_CAN0_RX14_BASE, 0x4000a260 +.set CYDEV_CAN0_RX14_SIZE, 0x00000020 +.set CYDEV_CAN0_RX14_CMD, 0x4000a260 +.set CYDEV_CAN0_RX14_ID, 0x4000a264 +.set CYDEV_CAN0_RX14_DH, 0x4000a268 +.set CYDEV_CAN0_RX14_DL, 0x4000a26c +.set CYDEV_CAN0_RX14_AMR, 0x4000a270 +.set CYDEV_CAN0_RX14_ACR, 0x4000a274 +.set CYDEV_CAN0_RX14_AMRD, 0x4000a278 +.set CYDEV_CAN0_RX14_ACRD, 0x4000a27c +.set CYDEV_CAN0_RX15_BASE, 0x4000a280 +.set CYDEV_CAN0_RX15_SIZE, 0x00000020 +.set CYDEV_CAN0_RX15_CMD, 0x4000a280 +.set CYDEV_CAN0_RX15_ID, 0x4000a284 +.set CYDEV_CAN0_RX15_DH, 0x4000a288 +.set CYDEV_CAN0_RX15_DL, 0x4000a28c +.set CYDEV_CAN0_RX15_AMR, 0x4000a290 +.set CYDEV_CAN0_RX15_ACR, 0x4000a294 +.set CYDEV_CAN0_RX15_AMRD, 0x4000a298 +.set CYDEV_CAN0_RX15_ACRD, 0x4000a29c +.set CYDEV_DFB0_BASE, 0x4000c000 +.set CYDEV_DFB0_SIZE, 0x000007b5 +.set CYDEV_DFB0_DPA_SRAM_BASE, 0x4000c000 +.set CYDEV_DFB0_DPA_SRAM_SIZE, 0x00000200 +.set CYDEV_DFB0_DPA_SRAM_DATA_MBASE, 0x4000c000 +.set CYDEV_DFB0_DPA_SRAM_DATA_MSIZE, 0x00000200 +.set CYDEV_DFB0_DPB_SRAM_BASE, 0x4000c200 +.set CYDEV_DFB0_DPB_SRAM_SIZE, 0x00000200 +.set CYDEV_DFB0_DPB_SRAM_DATA_MBASE, 0x4000c200 +.set CYDEV_DFB0_DPB_SRAM_DATA_MSIZE, 0x00000200 +.set CYDEV_DFB0_CSA_SRAM_BASE, 0x4000c400 +.set CYDEV_DFB0_CSA_SRAM_SIZE, 0x00000100 +.set CYDEV_DFB0_CSA_SRAM_DATA_MBASE, 0x4000c400 +.set CYDEV_DFB0_CSA_SRAM_DATA_MSIZE, 0x00000100 +.set CYDEV_DFB0_CSB_SRAM_BASE, 0x4000c500 +.set CYDEV_DFB0_CSB_SRAM_SIZE, 0x00000100 +.set CYDEV_DFB0_CSB_SRAM_DATA_MBASE, 0x4000c500 +.set CYDEV_DFB0_CSB_SRAM_DATA_MSIZE, 0x00000100 +.set CYDEV_DFB0_FSM_SRAM_BASE, 0x4000c600 +.set CYDEV_DFB0_FSM_SRAM_SIZE, 0x00000100 +.set CYDEV_DFB0_FSM_SRAM_DATA_MBASE, 0x4000c600 +.set CYDEV_DFB0_FSM_SRAM_DATA_MSIZE, 0x00000100 +.set CYDEV_DFB0_ACU_SRAM_BASE, 0x4000c700 +.set CYDEV_DFB0_ACU_SRAM_SIZE, 0x00000040 +.set CYDEV_DFB0_ACU_SRAM_DATA_MBASE, 0x4000c700 +.set CYDEV_DFB0_ACU_SRAM_DATA_MSIZE, 0x00000040 +.set CYDEV_DFB0_CR, 0x4000c780 +.set CYDEV_DFB0_SR, 0x4000c784 +.set CYDEV_DFB0_RAM_EN, 0x4000c788 +.set CYDEV_DFB0_RAM_DIR, 0x4000c78c +.set CYDEV_DFB0_SEMA, 0x4000c790 +.set CYDEV_DFB0_DSI_CTRL, 0x4000c794 +.set CYDEV_DFB0_INT_CTRL, 0x4000c798 +.set CYDEV_DFB0_DMA_CTRL, 0x4000c79c +.set CYDEV_DFB0_STAGEA, 0x4000c7a0 +.set CYDEV_DFB0_STAGEAM, 0x4000c7a1 +.set CYDEV_DFB0_STAGEAH, 0x4000c7a2 +.set CYDEV_DFB0_STAGEB, 0x4000c7a4 +.set CYDEV_DFB0_STAGEBM, 0x4000c7a5 +.set CYDEV_DFB0_STAGEBH, 0x4000c7a6 +.set CYDEV_DFB0_HOLDA, 0x4000c7a8 +.set CYDEV_DFB0_HOLDAM, 0x4000c7a9 +.set CYDEV_DFB0_HOLDAH, 0x4000c7aa +.set CYDEV_DFB0_HOLDAS, 0x4000c7ab +.set CYDEV_DFB0_HOLDB, 0x4000c7ac +.set CYDEV_DFB0_HOLDBM, 0x4000c7ad +.set CYDEV_DFB0_HOLDBH, 0x4000c7ae +.set CYDEV_DFB0_HOLDBS, 0x4000c7af +.set CYDEV_DFB0_COHER, 0x4000c7b0 +.set CYDEV_DFB0_DALIGN, 0x4000c7b4 +.set CYDEV_UCFG_BASE, 0x40010000 +.set CYDEV_UCFG_SIZE, 0x00005040 +.set CYDEV_UCFG_B0_BASE, 0x40010000 +.set CYDEV_UCFG_B0_SIZE, 0x00000fef +.set CYDEV_UCFG_B0_P0_BASE, 0x40010000 +.set CYDEV_UCFG_B0_P0_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P0_U0_BASE, 0x40010000 +.set CYDEV_UCFG_B0_P0_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT0, 0x40010000 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT1, 0x40010004 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT2, 0x40010008 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT3, 0x4001000c +.set CYDEV_UCFG_B0_P0_U0_PLD_IT4, 0x40010010 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT5, 0x40010014 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT6, 0x40010018 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT7, 0x4001001c +.set CYDEV_UCFG_B0_P0_U0_PLD_IT8, 0x40010020 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT9, 0x40010024 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT10, 0x40010028 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT11, 0x4001002c +.set CYDEV_UCFG_B0_P0_U0_PLD_ORT0, 0x40010030 +.set CYDEV_UCFG_B0_P0_U0_PLD_ORT1, 0x40010032 +.set CYDEV_UCFG_B0_P0_U0_PLD_ORT2, 0x40010034 +.set CYDEV_UCFG_B0_P0_U0_PLD_ORT3, 0x40010036 +.set CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST, 0x40010038 +.set CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB, 0x4001003a +.set CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET, 0x4001003c +.set CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS, 0x4001003e +.set CYDEV_UCFG_B0_P0_U0_CFG0, 0x40010040 +.set CYDEV_UCFG_B0_P0_U0_CFG1, 0x40010041 +.set CYDEV_UCFG_B0_P0_U0_CFG2, 0x40010042 +.set CYDEV_UCFG_B0_P0_U0_CFG3, 0x40010043 +.set CYDEV_UCFG_B0_P0_U0_CFG4, 0x40010044 +.set CYDEV_UCFG_B0_P0_U0_CFG5, 0x40010045 +.set CYDEV_UCFG_B0_P0_U0_CFG6, 0x40010046 +.set CYDEV_UCFG_B0_P0_U0_CFG7, 0x40010047 +.set CYDEV_UCFG_B0_P0_U0_CFG8, 0x40010048 +.set CYDEV_UCFG_B0_P0_U0_CFG9, 0x40010049 +.set CYDEV_UCFG_B0_P0_U0_CFG10, 0x4001004a +.set CYDEV_UCFG_B0_P0_U0_CFG11, 0x4001004b +.set CYDEV_UCFG_B0_P0_U0_CFG12, 0x4001004c +.set CYDEV_UCFG_B0_P0_U0_CFG13, 0x4001004d +.set CYDEV_UCFG_B0_P0_U0_CFG14, 0x4001004e +.set CYDEV_UCFG_B0_P0_U0_CFG15, 0x4001004f +.set CYDEV_UCFG_B0_P0_U0_CFG16, 0x40010050 +.set CYDEV_UCFG_B0_P0_U0_CFG17, 0x40010051 +.set CYDEV_UCFG_B0_P0_U0_CFG18, 0x40010052 +.set CYDEV_UCFG_B0_P0_U0_CFG19, 0x40010053 +.set CYDEV_UCFG_B0_P0_U0_CFG20, 0x40010054 +.set CYDEV_UCFG_B0_P0_U0_CFG21, 0x40010055 +.set CYDEV_UCFG_B0_P0_U0_CFG22, 0x40010056 +.set CYDEV_UCFG_B0_P0_U0_CFG23, 0x40010057 +.set CYDEV_UCFG_B0_P0_U0_CFG24, 0x40010058 +.set CYDEV_UCFG_B0_P0_U0_CFG25, 0x40010059 +.set CYDEV_UCFG_B0_P0_U0_CFG26, 0x4001005a +.set CYDEV_UCFG_B0_P0_U0_CFG27, 0x4001005b +.set CYDEV_UCFG_B0_P0_U0_CFG28, 0x4001005c +.set CYDEV_UCFG_B0_P0_U0_CFG29, 0x4001005d +.set CYDEV_UCFG_B0_P0_U0_CFG30, 0x4001005e +.set CYDEV_UCFG_B0_P0_U0_CFG31, 0x4001005f +.set CYDEV_UCFG_B0_P0_U0_DCFG0, 0x40010060 +.set CYDEV_UCFG_B0_P0_U0_DCFG1, 0x40010062 +.set CYDEV_UCFG_B0_P0_U0_DCFG2, 0x40010064 +.set CYDEV_UCFG_B0_P0_U0_DCFG3, 0x40010066 +.set CYDEV_UCFG_B0_P0_U0_DCFG4, 0x40010068 +.set CYDEV_UCFG_B0_P0_U0_DCFG5, 0x4001006a +.set CYDEV_UCFG_B0_P0_U0_DCFG6, 0x4001006c +.set CYDEV_UCFG_B0_P0_U0_DCFG7, 0x4001006e +.set CYDEV_UCFG_B0_P0_U1_BASE, 0x40010080 +.set CYDEV_UCFG_B0_P0_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT0, 0x40010080 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT1, 0x40010084 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT2, 0x40010088 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT3, 0x4001008c +.set CYDEV_UCFG_B0_P0_U1_PLD_IT4, 0x40010090 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT5, 0x40010094 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT6, 0x40010098 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT7, 0x4001009c +.set CYDEV_UCFG_B0_P0_U1_PLD_IT8, 0x400100a0 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT9, 0x400100a4 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT10, 0x400100a8 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT11, 0x400100ac +.set CYDEV_UCFG_B0_P0_U1_PLD_ORT0, 0x400100b0 +.set CYDEV_UCFG_B0_P0_U1_PLD_ORT1, 0x400100b2 +.set CYDEV_UCFG_B0_P0_U1_PLD_ORT2, 0x400100b4 +.set CYDEV_UCFG_B0_P0_U1_PLD_ORT3, 0x400100b6 +.set CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST, 0x400100b8 +.set CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB, 0x400100ba +.set CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET, 0x400100bc +.set CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS, 0x400100be +.set CYDEV_UCFG_B0_P0_U1_CFG0, 0x400100c0 +.set CYDEV_UCFG_B0_P0_U1_CFG1, 0x400100c1 +.set CYDEV_UCFG_B0_P0_U1_CFG2, 0x400100c2 +.set CYDEV_UCFG_B0_P0_U1_CFG3, 0x400100c3 +.set CYDEV_UCFG_B0_P0_U1_CFG4, 0x400100c4 +.set CYDEV_UCFG_B0_P0_U1_CFG5, 0x400100c5 +.set CYDEV_UCFG_B0_P0_U1_CFG6, 0x400100c6 +.set CYDEV_UCFG_B0_P0_U1_CFG7, 0x400100c7 +.set CYDEV_UCFG_B0_P0_U1_CFG8, 0x400100c8 +.set CYDEV_UCFG_B0_P0_U1_CFG9, 0x400100c9 +.set CYDEV_UCFG_B0_P0_U1_CFG10, 0x400100ca +.set CYDEV_UCFG_B0_P0_U1_CFG11, 0x400100cb +.set CYDEV_UCFG_B0_P0_U1_CFG12, 0x400100cc +.set CYDEV_UCFG_B0_P0_U1_CFG13, 0x400100cd +.set CYDEV_UCFG_B0_P0_U1_CFG14, 0x400100ce +.set CYDEV_UCFG_B0_P0_U1_CFG15, 0x400100cf +.set CYDEV_UCFG_B0_P0_U1_CFG16, 0x400100d0 +.set CYDEV_UCFG_B0_P0_U1_CFG17, 0x400100d1 +.set CYDEV_UCFG_B0_P0_U1_CFG18, 0x400100d2 +.set CYDEV_UCFG_B0_P0_U1_CFG19, 0x400100d3 +.set CYDEV_UCFG_B0_P0_U1_CFG20, 0x400100d4 +.set CYDEV_UCFG_B0_P0_U1_CFG21, 0x400100d5 +.set CYDEV_UCFG_B0_P0_U1_CFG22, 0x400100d6 +.set CYDEV_UCFG_B0_P0_U1_CFG23, 0x400100d7 +.set CYDEV_UCFG_B0_P0_U1_CFG24, 0x400100d8 +.set CYDEV_UCFG_B0_P0_U1_CFG25, 0x400100d9 +.set CYDEV_UCFG_B0_P0_U1_CFG26, 0x400100da +.set CYDEV_UCFG_B0_P0_U1_CFG27, 0x400100db +.set CYDEV_UCFG_B0_P0_U1_CFG28, 0x400100dc +.set CYDEV_UCFG_B0_P0_U1_CFG29, 0x400100dd +.set CYDEV_UCFG_B0_P0_U1_CFG30, 0x400100de +.set CYDEV_UCFG_B0_P0_U1_CFG31, 0x400100df +.set CYDEV_UCFG_B0_P0_U1_DCFG0, 0x400100e0 +.set CYDEV_UCFG_B0_P0_U1_DCFG1, 0x400100e2 +.set CYDEV_UCFG_B0_P0_U1_DCFG2, 0x400100e4 +.set CYDEV_UCFG_B0_P0_U1_DCFG3, 0x400100e6 +.set CYDEV_UCFG_B0_P0_U1_DCFG4, 0x400100e8 +.set CYDEV_UCFG_B0_P0_U1_DCFG5, 0x400100ea +.set CYDEV_UCFG_B0_P0_U1_DCFG6, 0x400100ec +.set CYDEV_UCFG_B0_P0_U1_DCFG7, 0x400100ee +.set CYDEV_UCFG_B0_P0_ROUTE_BASE, 0x40010100 +.set CYDEV_UCFG_B0_P0_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P1_BASE, 0x40010200 +.set CYDEV_UCFG_B0_P1_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P1_U0_BASE, 0x40010200 +.set CYDEV_UCFG_B0_P1_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT0, 0x40010200 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT1, 0x40010204 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT2, 0x40010208 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT3, 0x4001020c +.set CYDEV_UCFG_B0_P1_U0_PLD_IT4, 0x40010210 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT5, 0x40010214 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT6, 0x40010218 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT7, 0x4001021c +.set CYDEV_UCFG_B0_P1_U0_PLD_IT8, 0x40010220 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT9, 0x40010224 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT10, 0x40010228 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT11, 0x4001022c +.set CYDEV_UCFG_B0_P1_U0_PLD_ORT0, 0x40010230 +.set CYDEV_UCFG_B0_P1_U0_PLD_ORT1, 0x40010232 +.set CYDEV_UCFG_B0_P1_U0_PLD_ORT2, 0x40010234 +.set CYDEV_UCFG_B0_P1_U0_PLD_ORT3, 0x40010236 +.set CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST, 0x40010238 +.set CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB, 0x4001023a +.set CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET, 0x4001023c +.set CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS, 0x4001023e +.set CYDEV_UCFG_B0_P1_U0_CFG0, 0x40010240 +.set CYDEV_UCFG_B0_P1_U0_CFG1, 0x40010241 +.set CYDEV_UCFG_B0_P1_U0_CFG2, 0x40010242 +.set CYDEV_UCFG_B0_P1_U0_CFG3, 0x40010243 +.set CYDEV_UCFG_B0_P1_U0_CFG4, 0x40010244 +.set CYDEV_UCFG_B0_P1_U0_CFG5, 0x40010245 +.set CYDEV_UCFG_B0_P1_U0_CFG6, 0x40010246 +.set CYDEV_UCFG_B0_P1_U0_CFG7, 0x40010247 +.set CYDEV_UCFG_B0_P1_U0_CFG8, 0x40010248 +.set CYDEV_UCFG_B0_P1_U0_CFG9, 0x40010249 +.set CYDEV_UCFG_B0_P1_U0_CFG10, 0x4001024a +.set CYDEV_UCFG_B0_P1_U0_CFG11, 0x4001024b +.set CYDEV_UCFG_B0_P1_U0_CFG12, 0x4001024c +.set CYDEV_UCFG_B0_P1_U0_CFG13, 0x4001024d +.set CYDEV_UCFG_B0_P1_U0_CFG14, 0x4001024e +.set CYDEV_UCFG_B0_P1_U0_CFG15, 0x4001024f +.set CYDEV_UCFG_B0_P1_U0_CFG16, 0x40010250 +.set CYDEV_UCFG_B0_P1_U0_CFG17, 0x40010251 +.set CYDEV_UCFG_B0_P1_U0_CFG18, 0x40010252 +.set CYDEV_UCFG_B0_P1_U0_CFG19, 0x40010253 +.set CYDEV_UCFG_B0_P1_U0_CFG20, 0x40010254 +.set CYDEV_UCFG_B0_P1_U0_CFG21, 0x40010255 +.set CYDEV_UCFG_B0_P1_U0_CFG22, 0x40010256 +.set CYDEV_UCFG_B0_P1_U0_CFG23, 0x40010257 +.set CYDEV_UCFG_B0_P1_U0_CFG24, 0x40010258 +.set CYDEV_UCFG_B0_P1_U0_CFG25, 0x40010259 +.set CYDEV_UCFG_B0_P1_U0_CFG26, 0x4001025a +.set CYDEV_UCFG_B0_P1_U0_CFG27, 0x4001025b +.set CYDEV_UCFG_B0_P1_U0_CFG28, 0x4001025c +.set CYDEV_UCFG_B0_P1_U0_CFG29, 0x4001025d +.set CYDEV_UCFG_B0_P1_U0_CFG30, 0x4001025e +.set CYDEV_UCFG_B0_P1_U0_CFG31, 0x4001025f +.set CYDEV_UCFG_B0_P1_U0_DCFG0, 0x40010260 +.set CYDEV_UCFG_B0_P1_U0_DCFG1, 0x40010262 +.set CYDEV_UCFG_B0_P1_U0_DCFG2, 0x40010264 +.set CYDEV_UCFG_B0_P1_U0_DCFG3, 0x40010266 +.set CYDEV_UCFG_B0_P1_U0_DCFG4, 0x40010268 +.set CYDEV_UCFG_B0_P1_U0_DCFG5, 0x4001026a +.set CYDEV_UCFG_B0_P1_U0_DCFG6, 0x4001026c +.set CYDEV_UCFG_B0_P1_U0_DCFG7, 0x4001026e +.set CYDEV_UCFG_B0_P1_U1_BASE, 0x40010280 +.set CYDEV_UCFG_B0_P1_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT0, 0x40010280 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT1, 0x40010284 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT2, 0x40010288 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT3, 0x4001028c +.set CYDEV_UCFG_B0_P1_U1_PLD_IT4, 0x40010290 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT5, 0x40010294 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT6, 0x40010298 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT7, 0x4001029c +.set CYDEV_UCFG_B0_P1_U1_PLD_IT8, 0x400102a0 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT9, 0x400102a4 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT10, 0x400102a8 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT11, 0x400102ac +.set CYDEV_UCFG_B0_P1_U1_PLD_ORT0, 0x400102b0 +.set CYDEV_UCFG_B0_P1_U1_PLD_ORT1, 0x400102b2 +.set CYDEV_UCFG_B0_P1_U1_PLD_ORT2, 0x400102b4 +.set CYDEV_UCFG_B0_P1_U1_PLD_ORT3, 0x400102b6 +.set CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST, 0x400102b8 +.set CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB, 0x400102ba +.set CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET, 0x400102bc +.set CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS, 0x400102be +.set CYDEV_UCFG_B0_P1_U1_CFG0, 0x400102c0 +.set CYDEV_UCFG_B0_P1_U1_CFG1, 0x400102c1 +.set CYDEV_UCFG_B0_P1_U1_CFG2, 0x400102c2 +.set CYDEV_UCFG_B0_P1_U1_CFG3, 0x400102c3 +.set CYDEV_UCFG_B0_P1_U1_CFG4, 0x400102c4 +.set CYDEV_UCFG_B0_P1_U1_CFG5, 0x400102c5 +.set CYDEV_UCFG_B0_P1_U1_CFG6, 0x400102c6 +.set CYDEV_UCFG_B0_P1_U1_CFG7, 0x400102c7 +.set CYDEV_UCFG_B0_P1_U1_CFG8, 0x400102c8 +.set CYDEV_UCFG_B0_P1_U1_CFG9, 0x400102c9 +.set CYDEV_UCFG_B0_P1_U1_CFG10, 0x400102ca +.set CYDEV_UCFG_B0_P1_U1_CFG11, 0x400102cb +.set CYDEV_UCFG_B0_P1_U1_CFG12, 0x400102cc +.set CYDEV_UCFG_B0_P1_U1_CFG13, 0x400102cd +.set CYDEV_UCFG_B0_P1_U1_CFG14, 0x400102ce +.set CYDEV_UCFG_B0_P1_U1_CFG15, 0x400102cf +.set CYDEV_UCFG_B0_P1_U1_CFG16, 0x400102d0 +.set CYDEV_UCFG_B0_P1_U1_CFG17, 0x400102d1 +.set CYDEV_UCFG_B0_P1_U1_CFG18, 0x400102d2 +.set CYDEV_UCFG_B0_P1_U1_CFG19, 0x400102d3 +.set CYDEV_UCFG_B0_P1_U1_CFG20, 0x400102d4 +.set CYDEV_UCFG_B0_P1_U1_CFG21, 0x400102d5 +.set CYDEV_UCFG_B0_P1_U1_CFG22, 0x400102d6 +.set CYDEV_UCFG_B0_P1_U1_CFG23, 0x400102d7 +.set CYDEV_UCFG_B0_P1_U1_CFG24, 0x400102d8 +.set CYDEV_UCFG_B0_P1_U1_CFG25, 0x400102d9 +.set CYDEV_UCFG_B0_P1_U1_CFG26, 0x400102da +.set CYDEV_UCFG_B0_P1_U1_CFG27, 0x400102db +.set CYDEV_UCFG_B0_P1_U1_CFG28, 0x400102dc +.set CYDEV_UCFG_B0_P1_U1_CFG29, 0x400102dd +.set CYDEV_UCFG_B0_P1_U1_CFG30, 0x400102de +.set CYDEV_UCFG_B0_P1_U1_CFG31, 0x400102df +.set CYDEV_UCFG_B0_P1_U1_DCFG0, 0x400102e0 +.set CYDEV_UCFG_B0_P1_U1_DCFG1, 0x400102e2 +.set CYDEV_UCFG_B0_P1_U1_DCFG2, 0x400102e4 +.set CYDEV_UCFG_B0_P1_U1_DCFG3, 0x400102e6 +.set CYDEV_UCFG_B0_P1_U1_DCFG4, 0x400102e8 +.set CYDEV_UCFG_B0_P1_U1_DCFG5, 0x400102ea +.set CYDEV_UCFG_B0_P1_U1_DCFG6, 0x400102ec +.set CYDEV_UCFG_B0_P1_U1_DCFG7, 0x400102ee +.set CYDEV_UCFG_B0_P1_ROUTE_BASE, 0x40010300 +.set CYDEV_UCFG_B0_P1_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P2_BASE, 0x40010400 +.set CYDEV_UCFG_B0_P2_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P2_U0_BASE, 0x40010400 +.set CYDEV_UCFG_B0_P2_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT0, 0x40010400 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT1, 0x40010404 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT2, 0x40010408 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT3, 0x4001040c +.set CYDEV_UCFG_B0_P2_U0_PLD_IT4, 0x40010410 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT5, 0x40010414 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT6, 0x40010418 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT7, 0x4001041c +.set CYDEV_UCFG_B0_P2_U0_PLD_IT8, 0x40010420 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT9, 0x40010424 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT10, 0x40010428 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT11, 0x4001042c +.set CYDEV_UCFG_B0_P2_U0_PLD_ORT0, 0x40010430 +.set CYDEV_UCFG_B0_P2_U0_PLD_ORT1, 0x40010432 +.set CYDEV_UCFG_B0_P2_U0_PLD_ORT2, 0x40010434 +.set CYDEV_UCFG_B0_P2_U0_PLD_ORT3, 0x40010436 +.set CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST, 0x40010438 +.set CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB, 0x4001043a +.set CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET, 0x4001043c +.set CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS, 0x4001043e +.set CYDEV_UCFG_B0_P2_U0_CFG0, 0x40010440 +.set CYDEV_UCFG_B0_P2_U0_CFG1, 0x40010441 +.set CYDEV_UCFG_B0_P2_U0_CFG2, 0x40010442 +.set CYDEV_UCFG_B0_P2_U0_CFG3, 0x40010443 +.set CYDEV_UCFG_B0_P2_U0_CFG4, 0x40010444 +.set CYDEV_UCFG_B0_P2_U0_CFG5, 0x40010445 +.set CYDEV_UCFG_B0_P2_U0_CFG6, 0x40010446 +.set CYDEV_UCFG_B0_P2_U0_CFG7, 0x40010447 +.set CYDEV_UCFG_B0_P2_U0_CFG8, 0x40010448 +.set CYDEV_UCFG_B0_P2_U0_CFG9, 0x40010449 +.set CYDEV_UCFG_B0_P2_U0_CFG10, 0x4001044a +.set CYDEV_UCFG_B0_P2_U0_CFG11, 0x4001044b +.set CYDEV_UCFG_B0_P2_U0_CFG12, 0x4001044c +.set CYDEV_UCFG_B0_P2_U0_CFG13, 0x4001044d +.set CYDEV_UCFG_B0_P2_U0_CFG14, 0x4001044e +.set CYDEV_UCFG_B0_P2_U0_CFG15, 0x4001044f +.set CYDEV_UCFG_B0_P2_U0_CFG16, 0x40010450 +.set CYDEV_UCFG_B0_P2_U0_CFG17, 0x40010451 +.set CYDEV_UCFG_B0_P2_U0_CFG18, 0x40010452 +.set CYDEV_UCFG_B0_P2_U0_CFG19, 0x40010453 +.set CYDEV_UCFG_B0_P2_U0_CFG20, 0x40010454 +.set CYDEV_UCFG_B0_P2_U0_CFG21, 0x40010455 +.set CYDEV_UCFG_B0_P2_U0_CFG22, 0x40010456 +.set CYDEV_UCFG_B0_P2_U0_CFG23, 0x40010457 +.set CYDEV_UCFG_B0_P2_U0_CFG24, 0x40010458 +.set CYDEV_UCFG_B0_P2_U0_CFG25, 0x40010459 +.set CYDEV_UCFG_B0_P2_U0_CFG26, 0x4001045a +.set CYDEV_UCFG_B0_P2_U0_CFG27, 0x4001045b +.set CYDEV_UCFG_B0_P2_U0_CFG28, 0x4001045c +.set CYDEV_UCFG_B0_P2_U0_CFG29, 0x4001045d +.set CYDEV_UCFG_B0_P2_U0_CFG30, 0x4001045e +.set CYDEV_UCFG_B0_P2_U0_CFG31, 0x4001045f +.set CYDEV_UCFG_B0_P2_U0_DCFG0, 0x40010460 +.set CYDEV_UCFG_B0_P2_U0_DCFG1, 0x40010462 +.set CYDEV_UCFG_B0_P2_U0_DCFG2, 0x40010464 +.set CYDEV_UCFG_B0_P2_U0_DCFG3, 0x40010466 +.set CYDEV_UCFG_B0_P2_U0_DCFG4, 0x40010468 +.set CYDEV_UCFG_B0_P2_U0_DCFG5, 0x4001046a +.set CYDEV_UCFG_B0_P2_U0_DCFG6, 0x4001046c +.set CYDEV_UCFG_B0_P2_U0_DCFG7, 0x4001046e +.set CYDEV_UCFG_B0_P2_U1_BASE, 0x40010480 +.set CYDEV_UCFG_B0_P2_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT0, 0x40010480 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT1, 0x40010484 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT2, 0x40010488 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT3, 0x4001048c +.set CYDEV_UCFG_B0_P2_U1_PLD_IT4, 0x40010490 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT5, 0x40010494 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT6, 0x40010498 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT7, 0x4001049c +.set CYDEV_UCFG_B0_P2_U1_PLD_IT8, 0x400104a0 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT9, 0x400104a4 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT10, 0x400104a8 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT11, 0x400104ac +.set CYDEV_UCFG_B0_P2_U1_PLD_ORT0, 0x400104b0 +.set CYDEV_UCFG_B0_P2_U1_PLD_ORT1, 0x400104b2 +.set CYDEV_UCFG_B0_P2_U1_PLD_ORT2, 0x400104b4 +.set CYDEV_UCFG_B0_P2_U1_PLD_ORT3, 0x400104b6 +.set CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST, 0x400104b8 +.set CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB, 0x400104ba +.set CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET, 0x400104bc +.set CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS, 0x400104be +.set CYDEV_UCFG_B0_P2_U1_CFG0, 0x400104c0 +.set CYDEV_UCFG_B0_P2_U1_CFG1, 0x400104c1 +.set CYDEV_UCFG_B0_P2_U1_CFG2, 0x400104c2 +.set CYDEV_UCFG_B0_P2_U1_CFG3, 0x400104c3 +.set CYDEV_UCFG_B0_P2_U1_CFG4, 0x400104c4 +.set CYDEV_UCFG_B0_P2_U1_CFG5, 0x400104c5 +.set CYDEV_UCFG_B0_P2_U1_CFG6, 0x400104c6 +.set CYDEV_UCFG_B0_P2_U1_CFG7, 0x400104c7 +.set CYDEV_UCFG_B0_P2_U1_CFG8, 0x400104c8 +.set CYDEV_UCFG_B0_P2_U1_CFG9, 0x400104c9 +.set CYDEV_UCFG_B0_P2_U1_CFG10, 0x400104ca +.set CYDEV_UCFG_B0_P2_U1_CFG11, 0x400104cb +.set CYDEV_UCFG_B0_P2_U1_CFG12, 0x400104cc +.set CYDEV_UCFG_B0_P2_U1_CFG13, 0x400104cd +.set CYDEV_UCFG_B0_P2_U1_CFG14, 0x400104ce +.set CYDEV_UCFG_B0_P2_U1_CFG15, 0x400104cf +.set CYDEV_UCFG_B0_P2_U1_CFG16, 0x400104d0 +.set CYDEV_UCFG_B0_P2_U1_CFG17, 0x400104d1 +.set CYDEV_UCFG_B0_P2_U1_CFG18, 0x400104d2 +.set CYDEV_UCFG_B0_P2_U1_CFG19, 0x400104d3 +.set CYDEV_UCFG_B0_P2_U1_CFG20, 0x400104d4 +.set CYDEV_UCFG_B0_P2_U1_CFG21, 0x400104d5 +.set CYDEV_UCFG_B0_P2_U1_CFG22, 0x400104d6 +.set CYDEV_UCFG_B0_P2_U1_CFG23, 0x400104d7 +.set CYDEV_UCFG_B0_P2_U1_CFG24, 0x400104d8 +.set CYDEV_UCFG_B0_P2_U1_CFG25, 0x400104d9 +.set CYDEV_UCFG_B0_P2_U1_CFG26, 0x400104da +.set CYDEV_UCFG_B0_P2_U1_CFG27, 0x400104db +.set CYDEV_UCFG_B0_P2_U1_CFG28, 0x400104dc +.set CYDEV_UCFG_B0_P2_U1_CFG29, 0x400104dd +.set CYDEV_UCFG_B0_P2_U1_CFG30, 0x400104de +.set CYDEV_UCFG_B0_P2_U1_CFG31, 0x400104df +.set CYDEV_UCFG_B0_P2_U1_DCFG0, 0x400104e0 +.set CYDEV_UCFG_B0_P2_U1_DCFG1, 0x400104e2 +.set CYDEV_UCFG_B0_P2_U1_DCFG2, 0x400104e4 +.set CYDEV_UCFG_B0_P2_U1_DCFG3, 0x400104e6 +.set CYDEV_UCFG_B0_P2_U1_DCFG4, 0x400104e8 +.set CYDEV_UCFG_B0_P2_U1_DCFG5, 0x400104ea +.set CYDEV_UCFG_B0_P2_U1_DCFG6, 0x400104ec +.set CYDEV_UCFG_B0_P2_U1_DCFG7, 0x400104ee +.set CYDEV_UCFG_B0_P2_ROUTE_BASE, 0x40010500 +.set CYDEV_UCFG_B0_P2_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P3_BASE, 0x40010600 +.set CYDEV_UCFG_B0_P3_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P3_U0_BASE, 0x40010600 +.set CYDEV_UCFG_B0_P3_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT0, 0x40010600 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT1, 0x40010604 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT2, 0x40010608 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT3, 0x4001060c +.set CYDEV_UCFG_B0_P3_U0_PLD_IT4, 0x40010610 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT5, 0x40010614 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT6, 0x40010618 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT7, 0x4001061c +.set CYDEV_UCFG_B0_P3_U0_PLD_IT8, 0x40010620 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT9, 0x40010624 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT10, 0x40010628 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT11, 0x4001062c +.set CYDEV_UCFG_B0_P3_U0_PLD_ORT0, 0x40010630 +.set CYDEV_UCFG_B0_P3_U0_PLD_ORT1, 0x40010632 +.set CYDEV_UCFG_B0_P3_U0_PLD_ORT2, 0x40010634 +.set CYDEV_UCFG_B0_P3_U0_PLD_ORT3, 0x40010636 +.set CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST, 0x40010638 +.set CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB, 0x4001063a +.set CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET, 0x4001063c +.set CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS, 0x4001063e +.set CYDEV_UCFG_B0_P3_U0_CFG0, 0x40010640 +.set CYDEV_UCFG_B0_P3_U0_CFG1, 0x40010641 +.set CYDEV_UCFG_B0_P3_U0_CFG2, 0x40010642 +.set CYDEV_UCFG_B0_P3_U0_CFG3, 0x40010643 +.set CYDEV_UCFG_B0_P3_U0_CFG4, 0x40010644 +.set CYDEV_UCFG_B0_P3_U0_CFG5, 0x40010645 +.set CYDEV_UCFG_B0_P3_U0_CFG6, 0x40010646 +.set CYDEV_UCFG_B0_P3_U0_CFG7, 0x40010647 +.set CYDEV_UCFG_B0_P3_U0_CFG8, 0x40010648 +.set CYDEV_UCFG_B0_P3_U0_CFG9, 0x40010649 +.set CYDEV_UCFG_B0_P3_U0_CFG10, 0x4001064a +.set CYDEV_UCFG_B0_P3_U0_CFG11, 0x4001064b +.set CYDEV_UCFG_B0_P3_U0_CFG12, 0x4001064c +.set CYDEV_UCFG_B0_P3_U0_CFG13, 0x4001064d +.set CYDEV_UCFG_B0_P3_U0_CFG14, 0x4001064e +.set CYDEV_UCFG_B0_P3_U0_CFG15, 0x4001064f +.set CYDEV_UCFG_B0_P3_U0_CFG16, 0x40010650 +.set CYDEV_UCFG_B0_P3_U0_CFG17, 0x40010651 +.set CYDEV_UCFG_B0_P3_U0_CFG18, 0x40010652 +.set CYDEV_UCFG_B0_P3_U0_CFG19, 0x40010653 +.set CYDEV_UCFG_B0_P3_U0_CFG20, 0x40010654 +.set CYDEV_UCFG_B0_P3_U0_CFG21, 0x40010655 +.set CYDEV_UCFG_B0_P3_U0_CFG22, 0x40010656 +.set CYDEV_UCFG_B0_P3_U0_CFG23, 0x40010657 +.set CYDEV_UCFG_B0_P3_U0_CFG24, 0x40010658 +.set CYDEV_UCFG_B0_P3_U0_CFG25, 0x40010659 +.set CYDEV_UCFG_B0_P3_U0_CFG26, 0x4001065a +.set CYDEV_UCFG_B0_P3_U0_CFG27, 0x4001065b +.set CYDEV_UCFG_B0_P3_U0_CFG28, 0x4001065c +.set CYDEV_UCFG_B0_P3_U0_CFG29, 0x4001065d +.set CYDEV_UCFG_B0_P3_U0_CFG30, 0x4001065e +.set CYDEV_UCFG_B0_P3_U0_CFG31, 0x4001065f +.set CYDEV_UCFG_B0_P3_U0_DCFG0, 0x40010660 +.set CYDEV_UCFG_B0_P3_U0_DCFG1, 0x40010662 +.set CYDEV_UCFG_B0_P3_U0_DCFG2, 0x40010664 +.set CYDEV_UCFG_B0_P3_U0_DCFG3, 0x40010666 +.set CYDEV_UCFG_B0_P3_U0_DCFG4, 0x40010668 +.set CYDEV_UCFG_B0_P3_U0_DCFG5, 0x4001066a +.set CYDEV_UCFG_B0_P3_U0_DCFG6, 0x4001066c +.set CYDEV_UCFG_B0_P3_U0_DCFG7, 0x4001066e +.set CYDEV_UCFG_B0_P3_U1_BASE, 0x40010680 +.set CYDEV_UCFG_B0_P3_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT0, 0x40010680 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT1, 0x40010684 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT2, 0x40010688 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT3, 0x4001068c +.set CYDEV_UCFG_B0_P3_U1_PLD_IT4, 0x40010690 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT5, 0x40010694 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT6, 0x40010698 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT7, 0x4001069c +.set CYDEV_UCFG_B0_P3_U1_PLD_IT8, 0x400106a0 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT9, 0x400106a4 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT10, 0x400106a8 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT11, 0x400106ac +.set CYDEV_UCFG_B0_P3_U1_PLD_ORT0, 0x400106b0 +.set CYDEV_UCFG_B0_P3_U1_PLD_ORT1, 0x400106b2 +.set CYDEV_UCFG_B0_P3_U1_PLD_ORT2, 0x400106b4 +.set CYDEV_UCFG_B0_P3_U1_PLD_ORT3, 0x400106b6 +.set CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST, 0x400106b8 +.set CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB, 0x400106ba +.set CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET, 0x400106bc +.set CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS, 0x400106be +.set CYDEV_UCFG_B0_P3_U1_CFG0, 0x400106c0 +.set CYDEV_UCFG_B0_P3_U1_CFG1, 0x400106c1 +.set CYDEV_UCFG_B0_P3_U1_CFG2, 0x400106c2 +.set CYDEV_UCFG_B0_P3_U1_CFG3, 0x400106c3 +.set CYDEV_UCFG_B0_P3_U1_CFG4, 0x400106c4 +.set CYDEV_UCFG_B0_P3_U1_CFG5, 0x400106c5 +.set CYDEV_UCFG_B0_P3_U1_CFG6, 0x400106c6 +.set CYDEV_UCFG_B0_P3_U1_CFG7, 0x400106c7 +.set CYDEV_UCFG_B0_P3_U1_CFG8, 0x400106c8 +.set CYDEV_UCFG_B0_P3_U1_CFG9, 0x400106c9 +.set CYDEV_UCFG_B0_P3_U1_CFG10, 0x400106ca +.set CYDEV_UCFG_B0_P3_U1_CFG11, 0x400106cb +.set CYDEV_UCFG_B0_P3_U1_CFG12, 0x400106cc +.set CYDEV_UCFG_B0_P3_U1_CFG13, 0x400106cd +.set CYDEV_UCFG_B0_P3_U1_CFG14, 0x400106ce +.set CYDEV_UCFG_B0_P3_U1_CFG15, 0x400106cf +.set CYDEV_UCFG_B0_P3_U1_CFG16, 0x400106d0 +.set CYDEV_UCFG_B0_P3_U1_CFG17, 0x400106d1 +.set CYDEV_UCFG_B0_P3_U1_CFG18, 0x400106d2 +.set CYDEV_UCFG_B0_P3_U1_CFG19, 0x400106d3 +.set CYDEV_UCFG_B0_P3_U1_CFG20, 0x400106d4 +.set CYDEV_UCFG_B0_P3_U1_CFG21, 0x400106d5 +.set CYDEV_UCFG_B0_P3_U1_CFG22, 0x400106d6 +.set CYDEV_UCFG_B0_P3_U1_CFG23, 0x400106d7 +.set CYDEV_UCFG_B0_P3_U1_CFG24, 0x400106d8 +.set CYDEV_UCFG_B0_P3_U1_CFG25, 0x400106d9 +.set CYDEV_UCFG_B0_P3_U1_CFG26, 0x400106da +.set CYDEV_UCFG_B0_P3_U1_CFG27, 0x400106db +.set CYDEV_UCFG_B0_P3_U1_CFG28, 0x400106dc +.set CYDEV_UCFG_B0_P3_U1_CFG29, 0x400106dd +.set CYDEV_UCFG_B0_P3_U1_CFG30, 0x400106de +.set CYDEV_UCFG_B0_P3_U1_CFG31, 0x400106df +.set CYDEV_UCFG_B0_P3_U1_DCFG0, 0x400106e0 +.set CYDEV_UCFG_B0_P3_U1_DCFG1, 0x400106e2 +.set CYDEV_UCFG_B0_P3_U1_DCFG2, 0x400106e4 +.set CYDEV_UCFG_B0_P3_U1_DCFG3, 0x400106e6 +.set CYDEV_UCFG_B0_P3_U1_DCFG4, 0x400106e8 +.set CYDEV_UCFG_B0_P3_U1_DCFG5, 0x400106ea +.set CYDEV_UCFG_B0_P3_U1_DCFG6, 0x400106ec +.set CYDEV_UCFG_B0_P3_U1_DCFG7, 0x400106ee +.set CYDEV_UCFG_B0_P3_ROUTE_BASE, 0x40010700 +.set CYDEV_UCFG_B0_P3_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P4_BASE, 0x40010800 +.set CYDEV_UCFG_B0_P4_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P4_U0_BASE, 0x40010800 +.set CYDEV_UCFG_B0_P4_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT0, 0x40010800 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT1, 0x40010804 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT2, 0x40010808 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT3, 0x4001080c +.set CYDEV_UCFG_B0_P4_U0_PLD_IT4, 0x40010810 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT5, 0x40010814 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT6, 0x40010818 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT7, 0x4001081c +.set CYDEV_UCFG_B0_P4_U0_PLD_IT8, 0x40010820 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT9, 0x40010824 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT10, 0x40010828 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT11, 0x4001082c +.set CYDEV_UCFG_B0_P4_U0_PLD_ORT0, 0x40010830 +.set CYDEV_UCFG_B0_P4_U0_PLD_ORT1, 0x40010832 +.set CYDEV_UCFG_B0_P4_U0_PLD_ORT2, 0x40010834 +.set CYDEV_UCFG_B0_P4_U0_PLD_ORT3, 0x40010836 +.set CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST, 0x40010838 +.set CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB, 0x4001083a +.set CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET, 0x4001083c +.set CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS, 0x4001083e +.set CYDEV_UCFG_B0_P4_U0_CFG0, 0x40010840 +.set CYDEV_UCFG_B0_P4_U0_CFG1, 0x40010841 +.set CYDEV_UCFG_B0_P4_U0_CFG2, 0x40010842 +.set CYDEV_UCFG_B0_P4_U0_CFG3, 0x40010843 +.set CYDEV_UCFG_B0_P4_U0_CFG4, 0x40010844 +.set CYDEV_UCFG_B0_P4_U0_CFG5, 0x40010845 +.set CYDEV_UCFG_B0_P4_U0_CFG6, 0x40010846 +.set CYDEV_UCFG_B0_P4_U0_CFG7, 0x40010847 +.set CYDEV_UCFG_B0_P4_U0_CFG8, 0x40010848 +.set CYDEV_UCFG_B0_P4_U0_CFG9, 0x40010849 +.set CYDEV_UCFG_B0_P4_U0_CFG10, 0x4001084a +.set CYDEV_UCFG_B0_P4_U0_CFG11, 0x4001084b +.set CYDEV_UCFG_B0_P4_U0_CFG12, 0x4001084c +.set CYDEV_UCFG_B0_P4_U0_CFG13, 0x4001084d +.set CYDEV_UCFG_B0_P4_U0_CFG14, 0x4001084e +.set CYDEV_UCFG_B0_P4_U0_CFG15, 0x4001084f +.set CYDEV_UCFG_B0_P4_U0_CFG16, 0x40010850 +.set CYDEV_UCFG_B0_P4_U0_CFG17, 0x40010851 +.set CYDEV_UCFG_B0_P4_U0_CFG18, 0x40010852 +.set CYDEV_UCFG_B0_P4_U0_CFG19, 0x40010853 +.set CYDEV_UCFG_B0_P4_U0_CFG20, 0x40010854 +.set CYDEV_UCFG_B0_P4_U0_CFG21, 0x40010855 +.set CYDEV_UCFG_B0_P4_U0_CFG22, 0x40010856 +.set CYDEV_UCFG_B0_P4_U0_CFG23, 0x40010857 +.set CYDEV_UCFG_B0_P4_U0_CFG24, 0x40010858 +.set CYDEV_UCFG_B0_P4_U0_CFG25, 0x40010859 +.set CYDEV_UCFG_B0_P4_U0_CFG26, 0x4001085a +.set CYDEV_UCFG_B0_P4_U0_CFG27, 0x4001085b +.set CYDEV_UCFG_B0_P4_U0_CFG28, 0x4001085c +.set CYDEV_UCFG_B0_P4_U0_CFG29, 0x4001085d +.set CYDEV_UCFG_B0_P4_U0_CFG30, 0x4001085e +.set CYDEV_UCFG_B0_P4_U0_CFG31, 0x4001085f +.set CYDEV_UCFG_B0_P4_U0_DCFG0, 0x40010860 +.set CYDEV_UCFG_B0_P4_U0_DCFG1, 0x40010862 +.set CYDEV_UCFG_B0_P4_U0_DCFG2, 0x40010864 +.set CYDEV_UCFG_B0_P4_U0_DCFG3, 0x40010866 +.set CYDEV_UCFG_B0_P4_U0_DCFG4, 0x40010868 +.set CYDEV_UCFG_B0_P4_U0_DCFG5, 0x4001086a +.set CYDEV_UCFG_B0_P4_U0_DCFG6, 0x4001086c +.set CYDEV_UCFG_B0_P4_U0_DCFG7, 0x4001086e +.set CYDEV_UCFG_B0_P4_U1_BASE, 0x40010880 +.set CYDEV_UCFG_B0_P4_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT0, 0x40010880 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT1, 0x40010884 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT2, 0x40010888 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT3, 0x4001088c +.set CYDEV_UCFG_B0_P4_U1_PLD_IT4, 0x40010890 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT5, 0x40010894 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT6, 0x40010898 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT7, 0x4001089c +.set CYDEV_UCFG_B0_P4_U1_PLD_IT8, 0x400108a0 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT9, 0x400108a4 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT10, 0x400108a8 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT11, 0x400108ac +.set CYDEV_UCFG_B0_P4_U1_PLD_ORT0, 0x400108b0 +.set CYDEV_UCFG_B0_P4_U1_PLD_ORT1, 0x400108b2 +.set CYDEV_UCFG_B0_P4_U1_PLD_ORT2, 0x400108b4 +.set CYDEV_UCFG_B0_P4_U1_PLD_ORT3, 0x400108b6 +.set CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST, 0x400108b8 +.set CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB, 0x400108ba +.set CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET, 0x400108bc +.set CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS, 0x400108be +.set CYDEV_UCFG_B0_P4_U1_CFG0, 0x400108c0 +.set CYDEV_UCFG_B0_P4_U1_CFG1, 0x400108c1 +.set CYDEV_UCFG_B0_P4_U1_CFG2, 0x400108c2 +.set CYDEV_UCFG_B0_P4_U1_CFG3, 0x400108c3 +.set CYDEV_UCFG_B0_P4_U1_CFG4, 0x400108c4 +.set CYDEV_UCFG_B0_P4_U1_CFG5, 0x400108c5 +.set CYDEV_UCFG_B0_P4_U1_CFG6, 0x400108c6 +.set CYDEV_UCFG_B0_P4_U1_CFG7, 0x400108c7 +.set CYDEV_UCFG_B0_P4_U1_CFG8, 0x400108c8 +.set CYDEV_UCFG_B0_P4_U1_CFG9, 0x400108c9 +.set CYDEV_UCFG_B0_P4_U1_CFG10, 0x400108ca +.set CYDEV_UCFG_B0_P4_U1_CFG11, 0x400108cb +.set CYDEV_UCFG_B0_P4_U1_CFG12, 0x400108cc +.set CYDEV_UCFG_B0_P4_U1_CFG13, 0x400108cd +.set CYDEV_UCFG_B0_P4_U1_CFG14, 0x400108ce +.set CYDEV_UCFG_B0_P4_U1_CFG15, 0x400108cf +.set CYDEV_UCFG_B0_P4_U1_CFG16, 0x400108d0 +.set CYDEV_UCFG_B0_P4_U1_CFG17, 0x400108d1 +.set CYDEV_UCFG_B0_P4_U1_CFG18, 0x400108d2 +.set CYDEV_UCFG_B0_P4_U1_CFG19, 0x400108d3 +.set CYDEV_UCFG_B0_P4_U1_CFG20, 0x400108d4 +.set CYDEV_UCFG_B0_P4_U1_CFG21, 0x400108d5 +.set CYDEV_UCFG_B0_P4_U1_CFG22, 0x400108d6 +.set CYDEV_UCFG_B0_P4_U1_CFG23, 0x400108d7 +.set CYDEV_UCFG_B0_P4_U1_CFG24, 0x400108d8 +.set CYDEV_UCFG_B0_P4_U1_CFG25, 0x400108d9 +.set CYDEV_UCFG_B0_P4_U1_CFG26, 0x400108da +.set CYDEV_UCFG_B0_P4_U1_CFG27, 0x400108db +.set CYDEV_UCFG_B0_P4_U1_CFG28, 0x400108dc +.set CYDEV_UCFG_B0_P4_U1_CFG29, 0x400108dd +.set CYDEV_UCFG_B0_P4_U1_CFG30, 0x400108de +.set CYDEV_UCFG_B0_P4_U1_CFG31, 0x400108df +.set CYDEV_UCFG_B0_P4_U1_DCFG0, 0x400108e0 +.set CYDEV_UCFG_B0_P4_U1_DCFG1, 0x400108e2 +.set CYDEV_UCFG_B0_P4_U1_DCFG2, 0x400108e4 +.set CYDEV_UCFG_B0_P4_U1_DCFG3, 0x400108e6 +.set CYDEV_UCFG_B0_P4_U1_DCFG4, 0x400108e8 +.set CYDEV_UCFG_B0_P4_U1_DCFG5, 0x400108ea +.set CYDEV_UCFG_B0_P4_U1_DCFG6, 0x400108ec +.set CYDEV_UCFG_B0_P4_U1_DCFG7, 0x400108ee +.set CYDEV_UCFG_B0_P4_ROUTE_BASE, 0x40010900 +.set CYDEV_UCFG_B0_P4_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P5_BASE, 0x40010a00 +.set CYDEV_UCFG_B0_P5_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P5_U0_BASE, 0x40010a00 +.set CYDEV_UCFG_B0_P5_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT0, 0x40010a00 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT1, 0x40010a04 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT2, 0x40010a08 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT3, 0x40010a0c +.set CYDEV_UCFG_B0_P5_U0_PLD_IT4, 0x40010a10 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT5, 0x40010a14 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT6, 0x40010a18 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT7, 0x40010a1c +.set CYDEV_UCFG_B0_P5_U0_PLD_IT8, 0x40010a20 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT9, 0x40010a24 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT10, 0x40010a28 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT11, 0x40010a2c +.set CYDEV_UCFG_B0_P5_U0_PLD_ORT0, 0x40010a30 +.set CYDEV_UCFG_B0_P5_U0_PLD_ORT1, 0x40010a32 +.set CYDEV_UCFG_B0_P5_U0_PLD_ORT2, 0x40010a34 +.set CYDEV_UCFG_B0_P5_U0_PLD_ORT3, 0x40010a36 +.set CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST, 0x40010a38 +.set CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB, 0x40010a3a +.set CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET, 0x40010a3c +.set CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS, 0x40010a3e +.set CYDEV_UCFG_B0_P5_U0_CFG0, 0x40010a40 +.set CYDEV_UCFG_B0_P5_U0_CFG1, 0x40010a41 +.set CYDEV_UCFG_B0_P5_U0_CFG2, 0x40010a42 +.set CYDEV_UCFG_B0_P5_U0_CFG3, 0x40010a43 +.set CYDEV_UCFG_B0_P5_U0_CFG4, 0x40010a44 +.set CYDEV_UCFG_B0_P5_U0_CFG5, 0x40010a45 +.set CYDEV_UCFG_B0_P5_U0_CFG6, 0x40010a46 +.set CYDEV_UCFG_B0_P5_U0_CFG7, 0x40010a47 +.set CYDEV_UCFG_B0_P5_U0_CFG8, 0x40010a48 +.set CYDEV_UCFG_B0_P5_U0_CFG9, 0x40010a49 +.set CYDEV_UCFG_B0_P5_U0_CFG10, 0x40010a4a +.set CYDEV_UCFG_B0_P5_U0_CFG11, 0x40010a4b +.set CYDEV_UCFG_B0_P5_U0_CFG12, 0x40010a4c +.set CYDEV_UCFG_B0_P5_U0_CFG13, 0x40010a4d +.set CYDEV_UCFG_B0_P5_U0_CFG14, 0x40010a4e +.set CYDEV_UCFG_B0_P5_U0_CFG15, 0x40010a4f +.set CYDEV_UCFG_B0_P5_U0_CFG16, 0x40010a50 +.set CYDEV_UCFG_B0_P5_U0_CFG17, 0x40010a51 +.set CYDEV_UCFG_B0_P5_U0_CFG18, 0x40010a52 +.set CYDEV_UCFG_B0_P5_U0_CFG19, 0x40010a53 +.set CYDEV_UCFG_B0_P5_U0_CFG20, 0x40010a54 +.set CYDEV_UCFG_B0_P5_U0_CFG21, 0x40010a55 +.set CYDEV_UCFG_B0_P5_U0_CFG22, 0x40010a56 +.set CYDEV_UCFG_B0_P5_U0_CFG23, 0x40010a57 +.set CYDEV_UCFG_B0_P5_U0_CFG24, 0x40010a58 +.set CYDEV_UCFG_B0_P5_U0_CFG25, 0x40010a59 +.set CYDEV_UCFG_B0_P5_U0_CFG26, 0x40010a5a +.set CYDEV_UCFG_B0_P5_U0_CFG27, 0x40010a5b +.set CYDEV_UCFG_B0_P5_U0_CFG28, 0x40010a5c +.set CYDEV_UCFG_B0_P5_U0_CFG29, 0x40010a5d +.set CYDEV_UCFG_B0_P5_U0_CFG30, 0x40010a5e +.set CYDEV_UCFG_B0_P5_U0_CFG31, 0x40010a5f +.set CYDEV_UCFG_B0_P5_U0_DCFG0, 0x40010a60 +.set CYDEV_UCFG_B0_P5_U0_DCFG1, 0x40010a62 +.set CYDEV_UCFG_B0_P5_U0_DCFG2, 0x40010a64 +.set CYDEV_UCFG_B0_P5_U0_DCFG3, 0x40010a66 +.set CYDEV_UCFG_B0_P5_U0_DCFG4, 0x40010a68 +.set CYDEV_UCFG_B0_P5_U0_DCFG5, 0x40010a6a +.set CYDEV_UCFG_B0_P5_U0_DCFG6, 0x40010a6c +.set CYDEV_UCFG_B0_P5_U0_DCFG7, 0x40010a6e +.set CYDEV_UCFG_B0_P5_U1_BASE, 0x40010a80 +.set CYDEV_UCFG_B0_P5_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT0, 0x40010a80 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT1, 0x40010a84 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT2, 0x40010a88 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT3, 0x40010a8c +.set CYDEV_UCFG_B0_P5_U1_PLD_IT4, 0x40010a90 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT5, 0x40010a94 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT6, 0x40010a98 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT7, 0x40010a9c +.set CYDEV_UCFG_B0_P5_U1_PLD_IT8, 0x40010aa0 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT9, 0x40010aa4 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT10, 0x40010aa8 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT11, 0x40010aac +.set CYDEV_UCFG_B0_P5_U1_PLD_ORT0, 0x40010ab0 +.set CYDEV_UCFG_B0_P5_U1_PLD_ORT1, 0x40010ab2 +.set CYDEV_UCFG_B0_P5_U1_PLD_ORT2, 0x40010ab4 +.set CYDEV_UCFG_B0_P5_U1_PLD_ORT3, 0x40010ab6 +.set CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST, 0x40010ab8 +.set CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB, 0x40010aba +.set CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET, 0x40010abc +.set CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS, 0x40010abe +.set CYDEV_UCFG_B0_P5_U1_CFG0, 0x40010ac0 +.set CYDEV_UCFG_B0_P5_U1_CFG1, 0x40010ac1 +.set CYDEV_UCFG_B0_P5_U1_CFG2, 0x40010ac2 +.set CYDEV_UCFG_B0_P5_U1_CFG3, 0x40010ac3 +.set CYDEV_UCFG_B0_P5_U1_CFG4, 0x40010ac4 +.set CYDEV_UCFG_B0_P5_U1_CFG5, 0x40010ac5 +.set CYDEV_UCFG_B0_P5_U1_CFG6, 0x40010ac6 +.set CYDEV_UCFG_B0_P5_U1_CFG7, 0x40010ac7 +.set CYDEV_UCFG_B0_P5_U1_CFG8, 0x40010ac8 +.set CYDEV_UCFG_B0_P5_U1_CFG9, 0x40010ac9 +.set CYDEV_UCFG_B0_P5_U1_CFG10, 0x40010aca +.set CYDEV_UCFG_B0_P5_U1_CFG11, 0x40010acb +.set CYDEV_UCFG_B0_P5_U1_CFG12, 0x40010acc +.set CYDEV_UCFG_B0_P5_U1_CFG13, 0x40010acd +.set CYDEV_UCFG_B0_P5_U1_CFG14, 0x40010ace +.set CYDEV_UCFG_B0_P5_U1_CFG15, 0x40010acf +.set CYDEV_UCFG_B0_P5_U1_CFG16, 0x40010ad0 +.set CYDEV_UCFG_B0_P5_U1_CFG17, 0x40010ad1 +.set CYDEV_UCFG_B0_P5_U1_CFG18, 0x40010ad2 +.set CYDEV_UCFG_B0_P5_U1_CFG19, 0x40010ad3 +.set CYDEV_UCFG_B0_P5_U1_CFG20, 0x40010ad4 +.set CYDEV_UCFG_B0_P5_U1_CFG21, 0x40010ad5 +.set CYDEV_UCFG_B0_P5_U1_CFG22, 0x40010ad6 +.set CYDEV_UCFG_B0_P5_U1_CFG23, 0x40010ad7 +.set CYDEV_UCFG_B0_P5_U1_CFG24, 0x40010ad8 +.set CYDEV_UCFG_B0_P5_U1_CFG25, 0x40010ad9 +.set CYDEV_UCFG_B0_P5_U1_CFG26, 0x40010ada +.set CYDEV_UCFG_B0_P5_U1_CFG27, 0x40010adb +.set CYDEV_UCFG_B0_P5_U1_CFG28, 0x40010adc +.set CYDEV_UCFG_B0_P5_U1_CFG29, 0x40010add +.set CYDEV_UCFG_B0_P5_U1_CFG30, 0x40010ade +.set CYDEV_UCFG_B0_P5_U1_CFG31, 0x40010adf +.set CYDEV_UCFG_B0_P5_U1_DCFG0, 0x40010ae0 +.set CYDEV_UCFG_B0_P5_U1_DCFG1, 0x40010ae2 +.set CYDEV_UCFG_B0_P5_U1_DCFG2, 0x40010ae4 +.set CYDEV_UCFG_B0_P5_U1_DCFG3, 0x40010ae6 +.set CYDEV_UCFG_B0_P5_U1_DCFG4, 0x40010ae8 +.set CYDEV_UCFG_B0_P5_U1_DCFG5, 0x40010aea +.set CYDEV_UCFG_B0_P5_U1_DCFG6, 0x40010aec +.set CYDEV_UCFG_B0_P5_U1_DCFG7, 0x40010aee +.set CYDEV_UCFG_B0_P5_ROUTE_BASE, 0x40010b00 +.set CYDEV_UCFG_B0_P5_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P6_BASE, 0x40010c00 +.set CYDEV_UCFG_B0_P6_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P6_U0_BASE, 0x40010c00 +.set CYDEV_UCFG_B0_P6_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT0, 0x40010c00 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT1, 0x40010c04 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT2, 0x40010c08 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT3, 0x40010c0c +.set CYDEV_UCFG_B0_P6_U0_PLD_IT4, 0x40010c10 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT5, 0x40010c14 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT6, 0x40010c18 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT7, 0x40010c1c +.set CYDEV_UCFG_B0_P6_U0_PLD_IT8, 0x40010c20 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT9, 0x40010c24 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT10, 0x40010c28 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT11, 0x40010c2c +.set CYDEV_UCFG_B0_P6_U0_PLD_ORT0, 0x40010c30 +.set CYDEV_UCFG_B0_P6_U0_PLD_ORT1, 0x40010c32 +.set CYDEV_UCFG_B0_P6_U0_PLD_ORT2, 0x40010c34 +.set CYDEV_UCFG_B0_P6_U0_PLD_ORT3, 0x40010c36 +.set CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST, 0x40010c38 +.set CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB, 0x40010c3a +.set CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET, 0x40010c3c +.set CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS, 0x40010c3e +.set CYDEV_UCFG_B0_P6_U0_CFG0, 0x40010c40 +.set CYDEV_UCFG_B0_P6_U0_CFG1, 0x40010c41 +.set CYDEV_UCFG_B0_P6_U0_CFG2, 0x40010c42 +.set CYDEV_UCFG_B0_P6_U0_CFG3, 0x40010c43 +.set CYDEV_UCFG_B0_P6_U0_CFG4, 0x40010c44 +.set CYDEV_UCFG_B0_P6_U0_CFG5, 0x40010c45 +.set CYDEV_UCFG_B0_P6_U0_CFG6, 0x40010c46 +.set CYDEV_UCFG_B0_P6_U0_CFG7, 0x40010c47 +.set CYDEV_UCFG_B0_P6_U0_CFG8, 0x40010c48 +.set CYDEV_UCFG_B0_P6_U0_CFG9, 0x40010c49 +.set CYDEV_UCFG_B0_P6_U0_CFG10, 0x40010c4a +.set CYDEV_UCFG_B0_P6_U0_CFG11, 0x40010c4b +.set CYDEV_UCFG_B0_P6_U0_CFG12, 0x40010c4c +.set CYDEV_UCFG_B0_P6_U0_CFG13, 0x40010c4d +.set CYDEV_UCFG_B0_P6_U0_CFG14, 0x40010c4e +.set CYDEV_UCFG_B0_P6_U0_CFG15, 0x40010c4f +.set CYDEV_UCFG_B0_P6_U0_CFG16, 0x40010c50 +.set CYDEV_UCFG_B0_P6_U0_CFG17, 0x40010c51 +.set CYDEV_UCFG_B0_P6_U0_CFG18, 0x40010c52 +.set CYDEV_UCFG_B0_P6_U0_CFG19, 0x40010c53 +.set CYDEV_UCFG_B0_P6_U0_CFG20, 0x40010c54 +.set CYDEV_UCFG_B0_P6_U0_CFG21, 0x40010c55 +.set CYDEV_UCFG_B0_P6_U0_CFG22, 0x40010c56 +.set CYDEV_UCFG_B0_P6_U0_CFG23, 0x40010c57 +.set CYDEV_UCFG_B0_P6_U0_CFG24, 0x40010c58 +.set CYDEV_UCFG_B0_P6_U0_CFG25, 0x40010c59 +.set CYDEV_UCFG_B0_P6_U0_CFG26, 0x40010c5a +.set CYDEV_UCFG_B0_P6_U0_CFG27, 0x40010c5b +.set CYDEV_UCFG_B0_P6_U0_CFG28, 0x40010c5c +.set CYDEV_UCFG_B0_P6_U0_CFG29, 0x40010c5d +.set CYDEV_UCFG_B0_P6_U0_CFG30, 0x40010c5e +.set CYDEV_UCFG_B0_P6_U0_CFG31, 0x40010c5f +.set CYDEV_UCFG_B0_P6_U0_DCFG0, 0x40010c60 +.set CYDEV_UCFG_B0_P6_U0_DCFG1, 0x40010c62 +.set CYDEV_UCFG_B0_P6_U0_DCFG2, 0x40010c64 +.set CYDEV_UCFG_B0_P6_U0_DCFG3, 0x40010c66 +.set CYDEV_UCFG_B0_P6_U0_DCFG4, 0x40010c68 +.set CYDEV_UCFG_B0_P6_U0_DCFG5, 0x40010c6a +.set CYDEV_UCFG_B0_P6_U0_DCFG6, 0x40010c6c +.set CYDEV_UCFG_B0_P6_U0_DCFG7, 0x40010c6e +.set CYDEV_UCFG_B0_P6_U1_BASE, 0x40010c80 +.set CYDEV_UCFG_B0_P6_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT0, 0x40010c80 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT1, 0x40010c84 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT2, 0x40010c88 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT3, 0x40010c8c +.set CYDEV_UCFG_B0_P6_U1_PLD_IT4, 0x40010c90 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT5, 0x40010c94 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT6, 0x40010c98 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT7, 0x40010c9c +.set CYDEV_UCFG_B0_P6_U1_PLD_IT8, 0x40010ca0 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT9, 0x40010ca4 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT10, 0x40010ca8 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT11, 0x40010cac +.set CYDEV_UCFG_B0_P6_U1_PLD_ORT0, 0x40010cb0 +.set CYDEV_UCFG_B0_P6_U1_PLD_ORT1, 0x40010cb2 +.set CYDEV_UCFG_B0_P6_U1_PLD_ORT2, 0x40010cb4 +.set CYDEV_UCFG_B0_P6_U1_PLD_ORT3, 0x40010cb6 +.set CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST, 0x40010cb8 +.set CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB, 0x40010cba +.set CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET, 0x40010cbc +.set CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS, 0x40010cbe +.set CYDEV_UCFG_B0_P6_U1_CFG0, 0x40010cc0 +.set CYDEV_UCFG_B0_P6_U1_CFG1, 0x40010cc1 +.set CYDEV_UCFG_B0_P6_U1_CFG2, 0x40010cc2 +.set CYDEV_UCFG_B0_P6_U1_CFG3, 0x40010cc3 +.set CYDEV_UCFG_B0_P6_U1_CFG4, 0x40010cc4 +.set CYDEV_UCFG_B0_P6_U1_CFG5, 0x40010cc5 +.set CYDEV_UCFG_B0_P6_U1_CFG6, 0x40010cc6 +.set CYDEV_UCFG_B0_P6_U1_CFG7, 0x40010cc7 +.set CYDEV_UCFG_B0_P6_U1_CFG8, 0x40010cc8 +.set CYDEV_UCFG_B0_P6_U1_CFG9, 0x40010cc9 +.set CYDEV_UCFG_B0_P6_U1_CFG10, 0x40010cca +.set CYDEV_UCFG_B0_P6_U1_CFG11, 0x40010ccb +.set CYDEV_UCFG_B0_P6_U1_CFG12, 0x40010ccc +.set CYDEV_UCFG_B0_P6_U1_CFG13, 0x40010ccd +.set CYDEV_UCFG_B0_P6_U1_CFG14, 0x40010cce +.set CYDEV_UCFG_B0_P6_U1_CFG15, 0x40010ccf +.set CYDEV_UCFG_B0_P6_U1_CFG16, 0x40010cd0 +.set CYDEV_UCFG_B0_P6_U1_CFG17, 0x40010cd1 +.set CYDEV_UCFG_B0_P6_U1_CFG18, 0x40010cd2 +.set CYDEV_UCFG_B0_P6_U1_CFG19, 0x40010cd3 +.set CYDEV_UCFG_B0_P6_U1_CFG20, 0x40010cd4 +.set CYDEV_UCFG_B0_P6_U1_CFG21, 0x40010cd5 +.set CYDEV_UCFG_B0_P6_U1_CFG22, 0x40010cd6 +.set CYDEV_UCFG_B0_P6_U1_CFG23, 0x40010cd7 +.set CYDEV_UCFG_B0_P6_U1_CFG24, 0x40010cd8 +.set CYDEV_UCFG_B0_P6_U1_CFG25, 0x40010cd9 +.set CYDEV_UCFG_B0_P6_U1_CFG26, 0x40010cda +.set CYDEV_UCFG_B0_P6_U1_CFG27, 0x40010cdb +.set CYDEV_UCFG_B0_P6_U1_CFG28, 0x40010cdc +.set CYDEV_UCFG_B0_P6_U1_CFG29, 0x40010cdd +.set CYDEV_UCFG_B0_P6_U1_CFG30, 0x40010cde +.set CYDEV_UCFG_B0_P6_U1_CFG31, 0x40010cdf +.set CYDEV_UCFG_B0_P6_U1_DCFG0, 0x40010ce0 +.set CYDEV_UCFG_B0_P6_U1_DCFG1, 0x40010ce2 +.set CYDEV_UCFG_B0_P6_U1_DCFG2, 0x40010ce4 +.set CYDEV_UCFG_B0_P6_U1_DCFG3, 0x40010ce6 +.set CYDEV_UCFG_B0_P6_U1_DCFG4, 0x40010ce8 +.set CYDEV_UCFG_B0_P6_U1_DCFG5, 0x40010cea +.set CYDEV_UCFG_B0_P6_U1_DCFG6, 0x40010cec +.set CYDEV_UCFG_B0_P6_U1_DCFG7, 0x40010cee +.set CYDEV_UCFG_B0_P6_ROUTE_BASE, 0x40010d00 +.set CYDEV_UCFG_B0_P6_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P7_BASE, 0x40010e00 +.set CYDEV_UCFG_B0_P7_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P7_U0_BASE, 0x40010e00 +.set CYDEV_UCFG_B0_P7_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT0, 0x40010e00 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT1, 0x40010e04 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT2, 0x40010e08 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT3, 0x40010e0c +.set CYDEV_UCFG_B0_P7_U0_PLD_IT4, 0x40010e10 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT5, 0x40010e14 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT6, 0x40010e18 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT7, 0x40010e1c +.set CYDEV_UCFG_B0_P7_U0_PLD_IT8, 0x40010e20 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT9, 0x40010e24 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT10, 0x40010e28 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT11, 0x40010e2c +.set CYDEV_UCFG_B0_P7_U0_PLD_ORT0, 0x40010e30 +.set CYDEV_UCFG_B0_P7_U0_PLD_ORT1, 0x40010e32 +.set CYDEV_UCFG_B0_P7_U0_PLD_ORT2, 0x40010e34 +.set CYDEV_UCFG_B0_P7_U0_PLD_ORT3, 0x40010e36 +.set CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST, 0x40010e38 +.set CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB, 0x40010e3a +.set CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET, 0x40010e3c +.set CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS, 0x40010e3e +.set CYDEV_UCFG_B0_P7_U0_CFG0, 0x40010e40 +.set CYDEV_UCFG_B0_P7_U0_CFG1, 0x40010e41 +.set CYDEV_UCFG_B0_P7_U0_CFG2, 0x40010e42 +.set CYDEV_UCFG_B0_P7_U0_CFG3, 0x40010e43 +.set CYDEV_UCFG_B0_P7_U0_CFG4, 0x40010e44 +.set CYDEV_UCFG_B0_P7_U0_CFG5, 0x40010e45 +.set CYDEV_UCFG_B0_P7_U0_CFG6, 0x40010e46 +.set CYDEV_UCFG_B0_P7_U0_CFG7, 0x40010e47 +.set CYDEV_UCFG_B0_P7_U0_CFG8, 0x40010e48 +.set CYDEV_UCFG_B0_P7_U0_CFG9, 0x40010e49 +.set CYDEV_UCFG_B0_P7_U0_CFG10, 0x40010e4a +.set CYDEV_UCFG_B0_P7_U0_CFG11, 0x40010e4b +.set CYDEV_UCFG_B0_P7_U0_CFG12, 0x40010e4c +.set CYDEV_UCFG_B0_P7_U0_CFG13, 0x40010e4d +.set CYDEV_UCFG_B0_P7_U0_CFG14, 0x40010e4e +.set CYDEV_UCFG_B0_P7_U0_CFG15, 0x40010e4f +.set CYDEV_UCFG_B0_P7_U0_CFG16, 0x40010e50 +.set CYDEV_UCFG_B0_P7_U0_CFG17, 0x40010e51 +.set CYDEV_UCFG_B0_P7_U0_CFG18, 0x40010e52 +.set CYDEV_UCFG_B0_P7_U0_CFG19, 0x40010e53 +.set CYDEV_UCFG_B0_P7_U0_CFG20, 0x40010e54 +.set CYDEV_UCFG_B0_P7_U0_CFG21, 0x40010e55 +.set CYDEV_UCFG_B0_P7_U0_CFG22, 0x40010e56 +.set CYDEV_UCFG_B0_P7_U0_CFG23, 0x40010e57 +.set CYDEV_UCFG_B0_P7_U0_CFG24, 0x40010e58 +.set CYDEV_UCFG_B0_P7_U0_CFG25, 0x40010e59 +.set CYDEV_UCFG_B0_P7_U0_CFG26, 0x40010e5a +.set CYDEV_UCFG_B0_P7_U0_CFG27, 0x40010e5b +.set CYDEV_UCFG_B0_P7_U0_CFG28, 0x40010e5c +.set CYDEV_UCFG_B0_P7_U0_CFG29, 0x40010e5d +.set CYDEV_UCFG_B0_P7_U0_CFG30, 0x40010e5e +.set CYDEV_UCFG_B0_P7_U0_CFG31, 0x40010e5f +.set CYDEV_UCFG_B0_P7_U0_DCFG0, 0x40010e60 +.set CYDEV_UCFG_B0_P7_U0_DCFG1, 0x40010e62 +.set CYDEV_UCFG_B0_P7_U0_DCFG2, 0x40010e64 +.set CYDEV_UCFG_B0_P7_U0_DCFG3, 0x40010e66 +.set CYDEV_UCFG_B0_P7_U0_DCFG4, 0x40010e68 +.set CYDEV_UCFG_B0_P7_U0_DCFG5, 0x40010e6a +.set CYDEV_UCFG_B0_P7_U0_DCFG6, 0x40010e6c +.set CYDEV_UCFG_B0_P7_U0_DCFG7, 0x40010e6e +.set CYDEV_UCFG_B0_P7_U1_BASE, 0x40010e80 +.set CYDEV_UCFG_B0_P7_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT0, 0x40010e80 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT1, 0x40010e84 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT2, 0x40010e88 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT3, 0x40010e8c +.set CYDEV_UCFG_B0_P7_U1_PLD_IT4, 0x40010e90 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT5, 0x40010e94 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT6, 0x40010e98 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT7, 0x40010e9c +.set CYDEV_UCFG_B0_P7_U1_PLD_IT8, 0x40010ea0 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT9, 0x40010ea4 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT10, 0x40010ea8 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT11, 0x40010eac +.set CYDEV_UCFG_B0_P7_U1_PLD_ORT0, 0x40010eb0 +.set CYDEV_UCFG_B0_P7_U1_PLD_ORT1, 0x40010eb2 +.set CYDEV_UCFG_B0_P7_U1_PLD_ORT2, 0x40010eb4 +.set CYDEV_UCFG_B0_P7_U1_PLD_ORT3, 0x40010eb6 +.set CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST, 0x40010eb8 +.set CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB, 0x40010eba +.set CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET, 0x40010ebc +.set CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS, 0x40010ebe +.set CYDEV_UCFG_B0_P7_U1_CFG0, 0x40010ec0 +.set CYDEV_UCFG_B0_P7_U1_CFG1, 0x40010ec1 +.set CYDEV_UCFG_B0_P7_U1_CFG2, 0x40010ec2 +.set CYDEV_UCFG_B0_P7_U1_CFG3, 0x40010ec3 +.set CYDEV_UCFG_B0_P7_U1_CFG4, 0x40010ec4 +.set CYDEV_UCFG_B0_P7_U1_CFG5, 0x40010ec5 +.set CYDEV_UCFG_B0_P7_U1_CFG6, 0x40010ec6 +.set CYDEV_UCFG_B0_P7_U1_CFG7, 0x40010ec7 +.set CYDEV_UCFG_B0_P7_U1_CFG8, 0x40010ec8 +.set CYDEV_UCFG_B0_P7_U1_CFG9, 0x40010ec9 +.set CYDEV_UCFG_B0_P7_U1_CFG10, 0x40010eca +.set CYDEV_UCFG_B0_P7_U1_CFG11, 0x40010ecb +.set CYDEV_UCFG_B0_P7_U1_CFG12, 0x40010ecc +.set CYDEV_UCFG_B0_P7_U1_CFG13, 0x40010ecd +.set CYDEV_UCFG_B0_P7_U1_CFG14, 0x40010ece +.set CYDEV_UCFG_B0_P7_U1_CFG15, 0x40010ecf +.set CYDEV_UCFG_B0_P7_U1_CFG16, 0x40010ed0 +.set CYDEV_UCFG_B0_P7_U1_CFG17, 0x40010ed1 +.set CYDEV_UCFG_B0_P7_U1_CFG18, 0x40010ed2 +.set CYDEV_UCFG_B0_P7_U1_CFG19, 0x40010ed3 +.set CYDEV_UCFG_B0_P7_U1_CFG20, 0x40010ed4 +.set CYDEV_UCFG_B0_P7_U1_CFG21, 0x40010ed5 +.set CYDEV_UCFG_B0_P7_U1_CFG22, 0x40010ed6 +.set CYDEV_UCFG_B0_P7_U1_CFG23, 0x40010ed7 +.set CYDEV_UCFG_B0_P7_U1_CFG24, 0x40010ed8 +.set CYDEV_UCFG_B0_P7_U1_CFG25, 0x40010ed9 +.set CYDEV_UCFG_B0_P7_U1_CFG26, 0x40010eda +.set CYDEV_UCFG_B0_P7_U1_CFG27, 0x40010edb +.set CYDEV_UCFG_B0_P7_U1_CFG28, 0x40010edc +.set CYDEV_UCFG_B0_P7_U1_CFG29, 0x40010edd +.set CYDEV_UCFG_B0_P7_U1_CFG30, 0x40010ede +.set CYDEV_UCFG_B0_P7_U1_CFG31, 0x40010edf +.set CYDEV_UCFG_B0_P7_U1_DCFG0, 0x40010ee0 +.set CYDEV_UCFG_B0_P7_U1_DCFG1, 0x40010ee2 +.set CYDEV_UCFG_B0_P7_U1_DCFG2, 0x40010ee4 +.set CYDEV_UCFG_B0_P7_U1_DCFG3, 0x40010ee6 +.set CYDEV_UCFG_B0_P7_U1_DCFG4, 0x40010ee8 +.set CYDEV_UCFG_B0_P7_U1_DCFG5, 0x40010eea +.set CYDEV_UCFG_B0_P7_U1_DCFG6, 0x40010eec +.set CYDEV_UCFG_B0_P7_U1_DCFG7, 0x40010eee +.set CYDEV_UCFG_B0_P7_ROUTE_BASE, 0x40010f00 +.set CYDEV_UCFG_B0_P7_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_BASE, 0x40011000 +.set CYDEV_UCFG_B1_SIZE, 0x00000fef +.set CYDEV_UCFG_B1_P2_BASE, 0x40011400 +.set CYDEV_UCFG_B1_P2_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P2_U0_BASE, 0x40011400 +.set CYDEV_UCFG_B1_P2_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT0, 0x40011400 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT1, 0x40011404 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT2, 0x40011408 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT3, 0x4001140c +.set CYDEV_UCFG_B1_P2_U0_PLD_IT4, 0x40011410 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT5, 0x40011414 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT6, 0x40011418 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT7, 0x4001141c +.set CYDEV_UCFG_B1_P2_U0_PLD_IT8, 0x40011420 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT9, 0x40011424 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT10, 0x40011428 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT11, 0x4001142c +.set CYDEV_UCFG_B1_P2_U0_PLD_ORT0, 0x40011430 +.set CYDEV_UCFG_B1_P2_U0_PLD_ORT1, 0x40011432 +.set CYDEV_UCFG_B1_P2_U0_PLD_ORT2, 0x40011434 +.set CYDEV_UCFG_B1_P2_U0_PLD_ORT3, 0x40011436 +.set CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST, 0x40011438 +.set CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB, 0x4001143a +.set CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET, 0x4001143c +.set CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS, 0x4001143e +.set CYDEV_UCFG_B1_P2_U0_CFG0, 0x40011440 +.set CYDEV_UCFG_B1_P2_U0_CFG1, 0x40011441 +.set CYDEV_UCFG_B1_P2_U0_CFG2, 0x40011442 +.set CYDEV_UCFG_B1_P2_U0_CFG3, 0x40011443 +.set CYDEV_UCFG_B1_P2_U0_CFG4, 0x40011444 +.set CYDEV_UCFG_B1_P2_U0_CFG5, 0x40011445 +.set CYDEV_UCFG_B1_P2_U0_CFG6, 0x40011446 +.set CYDEV_UCFG_B1_P2_U0_CFG7, 0x40011447 +.set CYDEV_UCFG_B1_P2_U0_CFG8, 0x40011448 +.set CYDEV_UCFG_B1_P2_U0_CFG9, 0x40011449 +.set CYDEV_UCFG_B1_P2_U0_CFG10, 0x4001144a +.set CYDEV_UCFG_B1_P2_U0_CFG11, 0x4001144b +.set CYDEV_UCFG_B1_P2_U0_CFG12, 0x4001144c +.set CYDEV_UCFG_B1_P2_U0_CFG13, 0x4001144d +.set CYDEV_UCFG_B1_P2_U0_CFG14, 0x4001144e +.set CYDEV_UCFG_B1_P2_U0_CFG15, 0x4001144f +.set CYDEV_UCFG_B1_P2_U0_CFG16, 0x40011450 +.set CYDEV_UCFG_B1_P2_U0_CFG17, 0x40011451 +.set CYDEV_UCFG_B1_P2_U0_CFG18, 0x40011452 +.set CYDEV_UCFG_B1_P2_U0_CFG19, 0x40011453 +.set CYDEV_UCFG_B1_P2_U0_CFG20, 0x40011454 +.set CYDEV_UCFG_B1_P2_U0_CFG21, 0x40011455 +.set CYDEV_UCFG_B1_P2_U0_CFG22, 0x40011456 +.set CYDEV_UCFG_B1_P2_U0_CFG23, 0x40011457 +.set CYDEV_UCFG_B1_P2_U0_CFG24, 0x40011458 +.set CYDEV_UCFG_B1_P2_U0_CFG25, 0x40011459 +.set CYDEV_UCFG_B1_P2_U0_CFG26, 0x4001145a +.set CYDEV_UCFG_B1_P2_U0_CFG27, 0x4001145b +.set CYDEV_UCFG_B1_P2_U0_CFG28, 0x4001145c +.set CYDEV_UCFG_B1_P2_U0_CFG29, 0x4001145d +.set CYDEV_UCFG_B1_P2_U0_CFG30, 0x4001145e +.set CYDEV_UCFG_B1_P2_U0_CFG31, 0x4001145f +.set CYDEV_UCFG_B1_P2_U0_DCFG0, 0x40011460 +.set CYDEV_UCFG_B1_P2_U0_DCFG1, 0x40011462 +.set CYDEV_UCFG_B1_P2_U0_DCFG2, 0x40011464 +.set CYDEV_UCFG_B1_P2_U0_DCFG3, 0x40011466 +.set CYDEV_UCFG_B1_P2_U0_DCFG4, 0x40011468 +.set CYDEV_UCFG_B1_P2_U0_DCFG5, 0x4001146a +.set CYDEV_UCFG_B1_P2_U0_DCFG6, 0x4001146c +.set CYDEV_UCFG_B1_P2_U0_DCFG7, 0x4001146e +.set CYDEV_UCFG_B1_P2_U1_BASE, 0x40011480 +.set CYDEV_UCFG_B1_P2_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT0, 0x40011480 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT1, 0x40011484 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT2, 0x40011488 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT3, 0x4001148c +.set CYDEV_UCFG_B1_P2_U1_PLD_IT4, 0x40011490 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT5, 0x40011494 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT6, 0x40011498 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT7, 0x4001149c +.set CYDEV_UCFG_B1_P2_U1_PLD_IT8, 0x400114a0 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT9, 0x400114a4 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT10, 0x400114a8 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT11, 0x400114ac +.set CYDEV_UCFG_B1_P2_U1_PLD_ORT0, 0x400114b0 +.set CYDEV_UCFG_B1_P2_U1_PLD_ORT1, 0x400114b2 +.set CYDEV_UCFG_B1_P2_U1_PLD_ORT2, 0x400114b4 +.set CYDEV_UCFG_B1_P2_U1_PLD_ORT3, 0x400114b6 +.set CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST, 0x400114b8 +.set CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB, 0x400114ba +.set CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET, 0x400114bc +.set CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS, 0x400114be +.set CYDEV_UCFG_B1_P2_U1_CFG0, 0x400114c0 +.set CYDEV_UCFG_B1_P2_U1_CFG1, 0x400114c1 +.set CYDEV_UCFG_B1_P2_U1_CFG2, 0x400114c2 +.set CYDEV_UCFG_B1_P2_U1_CFG3, 0x400114c3 +.set CYDEV_UCFG_B1_P2_U1_CFG4, 0x400114c4 +.set CYDEV_UCFG_B1_P2_U1_CFG5, 0x400114c5 +.set CYDEV_UCFG_B1_P2_U1_CFG6, 0x400114c6 +.set CYDEV_UCFG_B1_P2_U1_CFG7, 0x400114c7 +.set CYDEV_UCFG_B1_P2_U1_CFG8, 0x400114c8 +.set CYDEV_UCFG_B1_P2_U1_CFG9, 0x400114c9 +.set CYDEV_UCFG_B1_P2_U1_CFG10, 0x400114ca +.set CYDEV_UCFG_B1_P2_U1_CFG11, 0x400114cb +.set CYDEV_UCFG_B1_P2_U1_CFG12, 0x400114cc +.set CYDEV_UCFG_B1_P2_U1_CFG13, 0x400114cd +.set CYDEV_UCFG_B1_P2_U1_CFG14, 0x400114ce +.set CYDEV_UCFG_B1_P2_U1_CFG15, 0x400114cf +.set CYDEV_UCFG_B1_P2_U1_CFG16, 0x400114d0 +.set CYDEV_UCFG_B1_P2_U1_CFG17, 0x400114d1 +.set CYDEV_UCFG_B1_P2_U1_CFG18, 0x400114d2 +.set CYDEV_UCFG_B1_P2_U1_CFG19, 0x400114d3 +.set CYDEV_UCFG_B1_P2_U1_CFG20, 0x400114d4 +.set CYDEV_UCFG_B1_P2_U1_CFG21, 0x400114d5 +.set CYDEV_UCFG_B1_P2_U1_CFG22, 0x400114d6 +.set CYDEV_UCFG_B1_P2_U1_CFG23, 0x400114d7 +.set CYDEV_UCFG_B1_P2_U1_CFG24, 0x400114d8 +.set CYDEV_UCFG_B1_P2_U1_CFG25, 0x400114d9 +.set CYDEV_UCFG_B1_P2_U1_CFG26, 0x400114da +.set CYDEV_UCFG_B1_P2_U1_CFG27, 0x400114db +.set CYDEV_UCFG_B1_P2_U1_CFG28, 0x400114dc +.set CYDEV_UCFG_B1_P2_U1_CFG29, 0x400114dd +.set CYDEV_UCFG_B1_P2_U1_CFG30, 0x400114de +.set CYDEV_UCFG_B1_P2_U1_CFG31, 0x400114df +.set CYDEV_UCFG_B1_P2_U1_DCFG0, 0x400114e0 +.set CYDEV_UCFG_B1_P2_U1_DCFG1, 0x400114e2 +.set CYDEV_UCFG_B1_P2_U1_DCFG2, 0x400114e4 +.set CYDEV_UCFG_B1_P2_U1_DCFG3, 0x400114e6 +.set CYDEV_UCFG_B1_P2_U1_DCFG4, 0x400114e8 +.set CYDEV_UCFG_B1_P2_U1_DCFG5, 0x400114ea +.set CYDEV_UCFG_B1_P2_U1_DCFG6, 0x400114ec +.set CYDEV_UCFG_B1_P2_U1_DCFG7, 0x400114ee +.set CYDEV_UCFG_B1_P2_ROUTE_BASE, 0x40011500 +.set CYDEV_UCFG_B1_P2_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_P3_BASE, 0x40011600 +.set CYDEV_UCFG_B1_P3_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P3_U0_BASE, 0x40011600 +.set CYDEV_UCFG_B1_P3_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT0, 0x40011600 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT1, 0x40011604 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT2, 0x40011608 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT3, 0x4001160c +.set CYDEV_UCFG_B1_P3_U0_PLD_IT4, 0x40011610 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT5, 0x40011614 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT6, 0x40011618 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT7, 0x4001161c +.set CYDEV_UCFG_B1_P3_U0_PLD_IT8, 0x40011620 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT9, 0x40011624 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT10, 0x40011628 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT11, 0x4001162c +.set CYDEV_UCFG_B1_P3_U0_PLD_ORT0, 0x40011630 +.set CYDEV_UCFG_B1_P3_U0_PLD_ORT1, 0x40011632 +.set CYDEV_UCFG_B1_P3_U0_PLD_ORT2, 0x40011634 +.set CYDEV_UCFG_B1_P3_U0_PLD_ORT3, 0x40011636 +.set CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST, 0x40011638 +.set CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB, 0x4001163a +.set CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET, 0x4001163c +.set CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS, 0x4001163e +.set CYDEV_UCFG_B1_P3_U0_CFG0, 0x40011640 +.set CYDEV_UCFG_B1_P3_U0_CFG1, 0x40011641 +.set CYDEV_UCFG_B1_P3_U0_CFG2, 0x40011642 +.set CYDEV_UCFG_B1_P3_U0_CFG3, 0x40011643 +.set CYDEV_UCFG_B1_P3_U0_CFG4, 0x40011644 +.set CYDEV_UCFG_B1_P3_U0_CFG5, 0x40011645 +.set CYDEV_UCFG_B1_P3_U0_CFG6, 0x40011646 +.set CYDEV_UCFG_B1_P3_U0_CFG7, 0x40011647 +.set CYDEV_UCFG_B1_P3_U0_CFG8, 0x40011648 +.set CYDEV_UCFG_B1_P3_U0_CFG9, 0x40011649 +.set CYDEV_UCFG_B1_P3_U0_CFG10, 0x4001164a +.set CYDEV_UCFG_B1_P3_U0_CFG11, 0x4001164b +.set CYDEV_UCFG_B1_P3_U0_CFG12, 0x4001164c +.set CYDEV_UCFG_B1_P3_U0_CFG13, 0x4001164d +.set CYDEV_UCFG_B1_P3_U0_CFG14, 0x4001164e +.set CYDEV_UCFG_B1_P3_U0_CFG15, 0x4001164f +.set CYDEV_UCFG_B1_P3_U0_CFG16, 0x40011650 +.set CYDEV_UCFG_B1_P3_U0_CFG17, 0x40011651 +.set CYDEV_UCFG_B1_P3_U0_CFG18, 0x40011652 +.set CYDEV_UCFG_B1_P3_U0_CFG19, 0x40011653 +.set CYDEV_UCFG_B1_P3_U0_CFG20, 0x40011654 +.set CYDEV_UCFG_B1_P3_U0_CFG21, 0x40011655 +.set CYDEV_UCFG_B1_P3_U0_CFG22, 0x40011656 +.set CYDEV_UCFG_B1_P3_U0_CFG23, 0x40011657 +.set CYDEV_UCFG_B1_P3_U0_CFG24, 0x40011658 +.set CYDEV_UCFG_B1_P3_U0_CFG25, 0x40011659 +.set CYDEV_UCFG_B1_P3_U0_CFG26, 0x4001165a +.set CYDEV_UCFG_B1_P3_U0_CFG27, 0x4001165b +.set CYDEV_UCFG_B1_P3_U0_CFG28, 0x4001165c +.set CYDEV_UCFG_B1_P3_U0_CFG29, 0x4001165d +.set CYDEV_UCFG_B1_P3_U0_CFG30, 0x4001165e +.set CYDEV_UCFG_B1_P3_U0_CFG31, 0x4001165f +.set CYDEV_UCFG_B1_P3_U0_DCFG0, 0x40011660 +.set CYDEV_UCFG_B1_P3_U0_DCFG1, 0x40011662 +.set CYDEV_UCFG_B1_P3_U0_DCFG2, 0x40011664 +.set CYDEV_UCFG_B1_P3_U0_DCFG3, 0x40011666 +.set CYDEV_UCFG_B1_P3_U0_DCFG4, 0x40011668 +.set CYDEV_UCFG_B1_P3_U0_DCFG5, 0x4001166a +.set CYDEV_UCFG_B1_P3_U0_DCFG6, 0x4001166c +.set CYDEV_UCFG_B1_P3_U0_DCFG7, 0x4001166e +.set CYDEV_UCFG_B1_P3_U1_BASE, 0x40011680 +.set CYDEV_UCFG_B1_P3_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT0, 0x40011680 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT1, 0x40011684 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT2, 0x40011688 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT3, 0x4001168c +.set CYDEV_UCFG_B1_P3_U1_PLD_IT4, 0x40011690 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT5, 0x40011694 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT6, 0x40011698 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT7, 0x4001169c +.set CYDEV_UCFG_B1_P3_U1_PLD_IT8, 0x400116a0 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT9, 0x400116a4 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT10, 0x400116a8 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT11, 0x400116ac +.set CYDEV_UCFG_B1_P3_U1_PLD_ORT0, 0x400116b0 +.set CYDEV_UCFG_B1_P3_U1_PLD_ORT1, 0x400116b2 +.set CYDEV_UCFG_B1_P3_U1_PLD_ORT2, 0x400116b4 +.set CYDEV_UCFG_B1_P3_U1_PLD_ORT3, 0x400116b6 +.set CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST, 0x400116b8 +.set CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB, 0x400116ba +.set CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET, 0x400116bc +.set CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS, 0x400116be +.set CYDEV_UCFG_B1_P3_U1_CFG0, 0x400116c0 +.set CYDEV_UCFG_B1_P3_U1_CFG1, 0x400116c1 +.set CYDEV_UCFG_B1_P3_U1_CFG2, 0x400116c2 +.set CYDEV_UCFG_B1_P3_U1_CFG3, 0x400116c3 +.set CYDEV_UCFG_B1_P3_U1_CFG4, 0x400116c4 +.set CYDEV_UCFG_B1_P3_U1_CFG5, 0x400116c5 +.set CYDEV_UCFG_B1_P3_U1_CFG6, 0x400116c6 +.set CYDEV_UCFG_B1_P3_U1_CFG7, 0x400116c7 +.set CYDEV_UCFG_B1_P3_U1_CFG8, 0x400116c8 +.set CYDEV_UCFG_B1_P3_U1_CFG9, 0x400116c9 +.set CYDEV_UCFG_B1_P3_U1_CFG10, 0x400116ca +.set CYDEV_UCFG_B1_P3_U1_CFG11, 0x400116cb +.set CYDEV_UCFG_B1_P3_U1_CFG12, 0x400116cc +.set CYDEV_UCFG_B1_P3_U1_CFG13, 0x400116cd +.set CYDEV_UCFG_B1_P3_U1_CFG14, 0x400116ce +.set CYDEV_UCFG_B1_P3_U1_CFG15, 0x400116cf +.set CYDEV_UCFG_B1_P3_U1_CFG16, 0x400116d0 +.set CYDEV_UCFG_B1_P3_U1_CFG17, 0x400116d1 +.set CYDEV_UCFG_B1_P3_U1_CFG18, 0x400116d2 +.set CYDEV_UCFG_B1_P3_U1_CFG19, 0x400116d3 +.set CYDEV_UCFG_B1_P3_U1_CFG20, 0x400116d4 +.set CYDEV_UCFG_B1_P3_U1_CFG21, 0x400116d5 +.set CYDEV_UCFG_B1_P3_U1_CFG22, 0x400116d6 +.set CYDEV_UCFG_B1_P3_U1_CFG23, 0x400116d7 +.set CYDEV_UCFG_B1_P3_U1_CFG24, 0x400116d8 +.set CYDEV_UCFG_B1_P3_U1_CFG25, 0x400116d9 +.set CYDEV_UCFG_B1_P3_U1_CFG26, 0x400116da +.set CYDEV_UCFG_B1_P3_U1_CFG27, 0x400116db +.set CYDEV_UCFG_B1_P3_U1_CFG28, 0x400116dc +.set CYDEV_UCFG_B1_P3_U1_CFG29, 0x400116dd +.set CYDEV_UCFG_B1_P3_U1_CFG30, 0x400116de +.set CYDEV_UCFG_B1_P3_U1_CFG31, 0x400116df +.set CYDEV_UCFG_B1_P3_U1_DCFG0, 0x400116e0 +.set CYDEV_UCFG_B1_P3_U1_DCFG1, 0x400116e2 +.set CYDEV_UCFG_B1_P3_U1_DCFG2, 0x400116e4 +.set CYDEV_UCFG_B1_P3_U1_DCFG3, 0x400116e6 +.set CYDEV_UCFG_B1_P3_U1_DCFG4, 0x400116e8 +.set CYDEV_UCFG_B1_P3_U1_DCFG5, 0x400116ea +.set CYDEV_UCFG_B1_P3_U1_DCFG6, 0x400116ec +.set CYDEV_UCFG_B1_P3_U1_DCFG7, 0x400116ee +.set CYDEV_UCFG_B1_P3_ROUTE_BASE, 0x40011700 +.set CYDEV_UCFG_B1_P3_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_P4_BASE, 0x40011800 +.set CYDEV_UCFG_B1_P4_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P4_U0_BASE, 0x40011800 +.set CYDEV_UCFG_B1_P4_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT0, 0x40011800 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT1, 0x40011804 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT2, 0x40011808 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT3, 0x4001180c +.set CYDEV_UCFG_B1_P4_U0_PLD_IT4, 0x40011810 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT5, 0x40011814 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT6, 0x40011818 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT7, 0x4001181c +.set CYDEV_UCFG_B1_P4_U0_PLD_IT8, 0x40011820 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT9, 0x40011824 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT10, 0x40011828 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT11, 0x4001182c +.set CYDEV_UCFG_B1_P4_U0_PLD_ORT0, 0x40011830 +.set CYDEV_UCFG_B1_P4_U0_PLD_ORT1, 0x40011832 +.set CYDEV_UCFG_B1_P4_U0_PLD_ORT2, 0x40011834 +.set CYDEV_UCFG_B1_P4_U0_PLD_ORT3, 0x40011836 +.set CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST, 0x40011838 +.set CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB, 0x4001183a +.set CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET, 0x4001183c +.set CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS, 0x4001183e +.set CYDEV_UCFG_B1_P4_U0_CFG0, 0x40011840 +.set CYDEV_UCFG_B1_P4_U0_CFG1, 0x40011841 +.set CYDEV_UCFG_B1_P4_U0_CFG2, 0x40011842 +.set CYDEV_UCFG_B1_P4_U0_CFG3, 0x40011843 +.set CYDEV_UCFG_B1_P4_U0_CFG4, 0x40011844 +.set CYDEV_UCFG_B1_P4_U0_CFG5, 0x40011845 +.set CYDEV_UCFG_B1_P4_U0_CFG6, 0x40011846 +.set CYDEV_UCFG_B1_P4_U0_CFG7, 0x40011847 +.set CYDEV_UCFG_B1_P4_U0_CFG8, 0x40011848 +.set CYDEV_UCFG_B1_P4_U0_CFG9, 0x40011849 +.set CYDEV_UCFG_B1_P4_U0_CFG10, 0x4001184a +.set CYDEV_UCFG_B1_P4_U0_CFG11, 0x4001184b +.set CYDEV_UCFG_B1_P4_U0_CFG12, 0x4001184c +.set CYDEV_UCFG_B1_P4_U0_CFG13, 0x4001184d +.set CYDEV_UCFG_B1_P4_U0_CFG14, 0x4001184e +.set CYDEV_UCFG_B1_P4_U0_CFG15, 0x4001184f +.set CYDEV_UCFG_B1_P4_U0_CFG16, 0x40011850 +.set CYDEV_UCFG_B1_P4_U0_CFG17, 0x40011851 +.set CYDEV_UCFG_B1_P4_U0_CFG18, 0x40011852 +.set CYDEV_UCFG_B1_P4_U0_CFG19, 0x40011853 +.set CYDEV_UCFG_B1_P4_U0_CFG20, 0x40011854 +.set CYDEV_UCFG_B1_P4_U0_CFG21, 0x40011855 +.set CYDEV_UCFG_B1_P4_U0_CFG22, 0x40011856 +.set CYDEV_UCFG_B1_P4_U0_CFG23, 0x40011857 +.set CYDEV_UCFG_B1_P4_U0_CFG24, 0x40011858 +.set CYDEV_UCFG_B1_P4_U0_CFG25, 0x40011859 +.set CYDEV_UCFG_B1_P4_U0_CFG26, 0x4001185a +.set CYDEV_UCFG_B1_P4_U0_CFG27, 0x4001185b +.set CYDEV_UCFG_B1_P4_U0_CFG28, 0x4001185c +.set CYDEV_UCFG_B1_P4_U0_CFG29, 0x4001185d +.set CYDEV_UCFG_B1_P4_U0_CFG30, 0x4001185e +.set CYDEV_UCFG_B1_P4_U0_CFG31, 0x4001185f +.set CYDEV_UCFG_B1_P4_U0_DCFG0, 0x40011860 +.set CYDEV_UCFG_B1_P4_U0_DCFG1, 0x40011862 +.set CYDEV_UCFG_B1_P4_U0_DCFG2, 0x40011864 +.set CYDEV_UCFG_B1_P4_U0_DCFG3, 0x40011866 +.set CYDEV_UCFG_B1_P4_U0_DCFG4, 0x40011868 +.set CYDEV_UCFG_B1_P4_U0_DCFG5, 0x4001186a +.set CYDEV_UCFG_B1_P4_U0_DCFG6, 0x4001186c +.set CYDEV_UCFG_B1_P4_U0_DCFG7, 0x4001186e +.set CYDEV_UCFG_B1_P4_U1_BASE, 0x40011880 +.set CYDEV_UCFG_B1_P4_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT0, 0x40011880 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT1, 0x40011884 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT2, 0x40011888 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT3, 0x4001188c +.set CYDEV_UCFG_B1_P4_U1_PLD_IT4, 0x40011890 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT5, 0x40011894 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT6, 0x40011898 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT7, 0x4001189c +.set CYDEV_UCFG_B1_P4_U1_PLD_IT8, 0x400118a0 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT9, 0x400118a4 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT10, 0x400118a8 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT11, 0x400118ac +.set CYDEV_UCFG_B1_P4_U1_PLD_ORT0, 0x400118b0 +.set CYDEV_UCFG_B1_P4_U1_PLD_ORT1, 0x400118b2 +.set CYDEV_UCFG_B1_P4_U1_PLD_ORT2, 0x400118b4 +.set CYDEV_UCFG_B1_P4_U1_PLD_ORT3, 0x400118b6 +.set CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST, 0x400118b8 +.set CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB, 0x400118ba +.set CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET, 0x400118bc +.set CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS, 0x400118be +.set CYDEV_UCFG_B1_P4_U1_CFG0, 0x400118c0 +.set CYDEV_UCFG_B1_P4_U1_CFG1, 0x400118c1 +.set CYDEV_UCFG_B1_P4_U1_CFG2, 0x400118c2 +.set CYDEV_UCFG_B1_P4_U1_CFG3, 0x400118c3 +.set CYDEV_UCFG_B1_P4_U1_CFG4, 0x400118c4 +.set CYDEV_UCFG_B1_P4_U1_CFG5, 0x400118c5 +.set CYDEV_UCFG_B1_P4_U1_CFG6, 0x400118c6 +.set CYDEV_UCFG_B1_P4_U1_CFG7, 0x400118c7 +.set CYDEV_UCFG_B1_P4_U1_CFG8, 0x400118c8 +.set CYDEV_UCFG_B1_P4_U1_CFG9, 0x400118c9 +.set CYDEV_UCFG_B1_P4_U1_CFG10, 0x400118ca +.set CYDEV_UCFG_B1_P4_U1_CFG11, 0x400118cb +.set CYDEV_UCFG_B1_P4_U1_CFG12, 0x400118cc +.set CYDEV_UCFG_B1_P4_U1_CFG13, 0x400118cd +.set CYDEV_UCFG_B1_P4_U1_CFG14, 0x400118ce +.set CYDEV_UCFG_B1_P4_U1_CFG15, 0x400118cf +.set CYDEV_UCFG_B1_P4_U1_CFG16, 0x400118d0 +.set CYDEV_UCFG_B1_P4_U1_CFG17, 0x400118d1 +.set CYDEV_UCFG_B1_P4_U1_CFG18, 0x400118d2 +.set CYDEV_UCFG_B1_P4_U1_CFG19, 0x400118d3 +.set CYDEV_UCFG_B1_P4_U1_CFG20, 0x400118d4 +.set CYDEV_UCFG_B1_P4_U1_CFG21, 0x400118d5 +.set CYDEV_UCFG_B1_P4_U1_CFG22, 0x400118d6 +.set CYDEV_UCFG_B1_P4_U1_CFG23, 0x400118d7 +.set CYDEV_UCFG_B1_P4_U1_CFG24, 0x400118d8 +.set CYDEV_UCFG_B1_P4_U1_CFG25, 0x400118d9 +.set CYDEV_UCFG_B1_P4_U1_CFG26, 0x400118da +.set CYDEV_UCFG_B1_P4_U1_CFG27, 0x400118db +.set CYDEV_UCFG_B1_P4_U1_CFG28, 0x400118dc +.set CYDEV_UCFG_B1_P4_U1_CFG29, 0x400118dd +.set CYDEV_UCFG_B1_P4_U1_CFG30, 0x400118de +.set CYDEV_UCFG_B1_P4_U1_CFG31, 0x400118df +.set CYDEV_UCFG_B1_P4_U1_DCFG0, 0x400118e0 +.set CYDEV_UCFG_B1_P4_U1_DCFG1, 0x400118e2 +.set CYDEV_UCFG_B1_P4_U1_DCFG2, 0x400118e4 +.set CYDEV_UCFG_B1_P4_U1_DCFG3, 0x400118e6 +.set CYDEV_UCFG_B1_P4_U1_DCFG4, 0x400118e8 +.set CYDEV_UCFG_B1_P4_U1_DCFG5, 0x400118ea +.set CYDEV_UCFG_B1_P4_U1_DCFG6, 0x400118ec +.set CYDEV_UCFG_B1_P4_U1_DCFG7, 0x400118ee +.set CYDEV_UCFG_B1_P4_ROUTE_BASE, 0x40011900 +.set CYDEV_UCFG_B1_P4_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_P5_BASE, 0x40011a00 +.set CYDEV_UCFG_B1_P5_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P5_U0_BASE, 0x40011a00 +.set CYDEV_UCFG_B1_P5_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT0, 0x40011a00 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT1, 0x40011a04 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT2, 0x40011a08 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT3, 0x40011a0c +.set CYDEV_UCFG_B1_P5_U0_PLD_IT4, 0x40011a10 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT5, 0x40011a14 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT6, 0x40011a18 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT7, 0x40011a1c +.set CYDEV_UCFG_B1_P5_U0_PLD_IT8, 0x40011a20 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT9, 0x40011a24 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT10, 0x40011a28 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT11, 0x40011a2c +.set CYDEV_UCFG_B1_P5_U0_PLD_ORT0, 0x40011a30 +.set CYDEV_UCFG_B1_P5_U0_PLD_ORT1, 0x40011a32 +.set CYDEV_UCFG_B1_P5_U0_PLD_ORT2, 0x40011a34 +.set CYDEV_UCFG_B1_P5_U0_PLD_ORT3, 0x40011a36 +.set CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST, 0x40011a38 +.set CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB, 0x40011a3a +.set CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET, 0x40011a3c +.set CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS, 0x40011a3e +.set CYDEV_UCFG_B1_P5_U0_CFG0, 0x40011a40 +.set CYDEV_UCFG_B1_P5_U0_CFG1, 0x40011a41 +.set CYDEV_UCFG_B1_P5_U0_CFG2, 0x40011a42 +.set CYDEV_UCFG_B1_P5_U0_CFG3, 0x40011a43 +.set CYDEV_UCFG_B1_P5_U0_CFG4, 0x40011a44 +.set CYDEV_UCFG_B1_P5_U0_CFG5, 0x40011a45 +.set CYDEV_UCFG_B1_P5_U0_CFG6, 0x40011a46 +.set CYDEV_UCFG_B1_P5_U0_CFG7, 0x40011a47 +.set CYDEV_UCFG_B1_P5_U0_CFG8, 0x40011a48 +.set CYDEV_UCFG_B1_P5_U0_CFG9, 0x40011a49 +.set CYDEV_UCFG_B1_P5_U0_CFG10, 0x40011a4a +.set CYDEV_UCFG_B1_P5_U0_CFG11, 0x40011a4b +.set CYDEV_UCFG_B1_P5_U0_CFG12, 0x40011a4c +.set CYDEV_UCFG_B1_P5_U0_CFG13, 0x40011a4d +.set CYDEV_UCFG_B1_P5_U0_CFG14, 0x40011a4e +.set CYDEV_UCFG_B1_P5_U0_CFG15, 0x40011a4f +.set CYDEV_UCFG_B1_P5_U0_CFG16, 0x40011a50 +.set CYDEV_UCFG_B1_P5_U0_CFG17, 0x40011a51 +.set CYDEV_UCFG_B1_P5_U0_CFG18, 0x40011a52 +.set CYDEV_UCFG_B1_P5_U0_CFG19, 0x40011a53 +.set CYDEV_UCFG_B1_P5_U0_CFG20, 0x40011a54 +.set CYDEV_UCFG_B1_P5_U0_CFG21, 0x40011a55 +.set CYDEV_UCFG_B1_P5_U0_CFG22, 0x40011a56 +.set CYDEV_UCFG_B1_P5_U0_CFG23, 0x40011a57 +.set CYDEV_UCFG_B1_P5_U0_CFG24, 0x40011a58 +.set CYDEV_UCFG_B1_P5_U0_CFG25, 0x40011a59 +.set CYDEV_UCFG_B1_P5_U0_CFG26, 0x40011a5a +.set CYDEV_UCFG_B1_P5_U0_CFG27, 0x40011a5b +.set CYDEV_UCFG_B1_P5_U0_CFG28, 0x40011a5c +.set CYDEV_UCFG_B1_P5_U0_CFG29, 0x40011a5d +.set CYDEV_UCFG_B1_P5_U0_CFG30, 0x40011a5e +.set CYDEV_UCFG_B1_P5_U0_CFG31, 0x40011a5f +.set CYDEV_UCFG_B1_P5_U0_DCFG0, 0x40011a60 +.set CYDEV_UCFG_B1_P5_U0_DCFG1, 0x40011a62 +.set CYDEV_UCFG_B1_P5_U0_DCFG2, 0x40011a64 +.set CYDEV_UCFG_B1_P5_U0_DCFG3, 0x40011a66 +.set CYDEV_UCFG_B1_P5_U0_DCFG4, 0x40011a68 +.set CYDEV_UCFG_B1_P5_U0_DCFG5, 0x40011a6a +.set CYDEV_UCFG_B1_P5_U0_DCFG6, 0x40011a6c +.set CYDEV_UCFG_B1_P5_U0_DCFG7, 0x40011a6e +.set CYDEV_UCFG_B1_P5_U1_BASE, 0x40011a80 +.set CYDEV_UCFG_B1_P5_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT0, 0x40011a80 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT1, 0x40011a84 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT2, 0x40011a88 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT3, 0x40011a8c +.set CYDEV_UCFG_B1_P5_U1_PLD_IT4, 0x40011a90 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT5, 0x40011a94 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT6, 0x40011a98 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT7, 0x40011a9c +.set CYDEV_UCFG_B1_P5_U1_PLD_IT8, 0x40011aa0 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT9, 0x40011aa4 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT10, 0x40011aa8 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT11, 0x40011aac +.set CYDEV_UCFG_B1_P5_U1_PLD_ORT0, 0x40011ab0 +.set CYDEV_UCFG_B1_P5_U1_PLD_ORT1, 0x40011ab2 +.set CYDEV_UCFG_B1_P5_U1_PLD_ORT2, 0x40011ab4 +.set CYDEV_UCFG_B1_P5_U1_PLD_ORT3, 0x40011ab6 +.set CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST, 0x40011ab8 +.set CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB, 0x40011aba +.set CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET, 0x40011abc +.set CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS, 0x40011abe +.set CYDEV_UCFG_B1_P5_U1_CFG0, 0x40011ac0 +.set CYDEV_UCFG_B1_P5_U1_CFG1, 0x40011ac1 +.set CYDEV_UCFG_B1_P5_U1_CFG2, 0x40011ac2 +.set CYDEV_UCFG_B1_P5_U1_CFG3, 0x40011ac3 +.set CYDEV_UCFG_B1_P5_U1_CFG4, 0x40011ac4 +.set CYDEV_UCFG_B1_P5_U1_CFG5, 0x40011ac5 +.set CYDEV_UCFG_B1_P5_U1_CFG6, 0x40011ac6 +.set CYDEV_UCFG_B1_P5_U1_CFG7, 0x40011ac7 +.set CYDEV_UCFG_B1_P5_U1_CFG8, 0x40011ac8 +.set CYDEV_UCFG_B1_P5_U1_CFG9, 0x40011ac9 +.set CYDEV_UCFG_B1_P5_U1_CFG10, 0x40011aca +.set CYDEV_UCFG_B1_P5_U1_CFG11, 0x40011acb +.set CYDEV_UCFG_B1_P5_U1_CFG12, 0x40011acc +.set CYDEV_UCFG_B1_P5_U1_CFG13, 0x40011acd +.set CYDEV_UCFG_B1_P5_U1_CFG14, 0x40011ace +.set CYDEV_UCFG_B1_P5_U1_CFG15, 0x40011acf +.set CYDEV_UCFG_B1_P5_U1_CFG16, 0x40011ad0 +.set CYDEV_UCFG_B1_P5_U1_CFG17, 0x40011ad1 +.set CYDEV_UCFG_B1_P5_U1_CFG18, 0x40011ad2 +.set CYDEV_UCFG_B1_P5_U1_CFG19, 0x40011ad3 +.set CYDEV_UCFG_B1_P5_U1_CFG20, 0x40011ad4 +.set CYDEV_UCFG_B1_P5_U1_CFG21, 0x40011ad5 +.set CYDEV_UCFG_B1_P5_U1_CFG22, 0x40011ad6 +.set CYDEV_UCFG_B1_P5_U1_CFG23, 0x40011ad7 +.set CYDEV_UCFG_B1_P5_U1_CFG24, 0x40011ad8 +.set CYDEV_UCFG_B1_P5_U1_CFG25, 0x40011ad9 +.set CYDEV_UCFG_B1_P5_U1_CFG26, 0x40011ada +.set CYDEV_UCFG_B1_P5_U1_CFG27, 0x40011adb +.set CYDEV_UCFG_B1_P5_U1_CFG28, 0x40011adc +.set CYDEV_UCFG_B1_P5_U1_CFG29, 0x40011add +.set CYDEV_UCFG_B1_P5_U1_CFG30, 0x40011ade +.set CYDEV_UCFG_B1_P5_U1_CFG31, 0x40011adf +.set CYDEV_UCFG_B1_P5_U1_DCFG0, 0x40011ae0 +.set CYDEV_UCFG_B1_P5_U1_DCFG1, 0x40011ae2 +.set CYDEV_UCFG_B1_P5_U1_DCFG2, 0x40011ae4 +.set CYDEV_UCFG_B1_P5_U1_DCFG3, 0x40011ae6 +.set CYDEV_UCFG_B1_P5_U1_DCFG4, 0x40011ae8 +.set CYDEV_UCFG_B1_P5_U1_DCFG5, 0x40011aea +.set CYDEV_UCFG_B1_P5_U1_DCFG6, 0x40011aec +.set CYDEV_UCFG_B1_P5_U1_DCFG7, 0x40011aee +.set CYDEV_UCFG_B1_P5_ROUTE_BASE, 0x40011b00 +.set CYDEV_UCFG_B1_P5_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI0_BASE, 0x40014000 +.set CYDEV_UCFG_DSI0_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI1_BASE, 0x40014100 +.set CYDEV_UCFG_DSI1_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI2_BASE, 0x40014200 +.set CYDEV_UCFG_DSI2_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI3_BASE, 0x40014300 +.set CYDEV_UCFG_DSI3_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI4_BASE, 0x40014400 +.set CYDEV_UCFG_DSI4_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI5_BASE, 0x40014500 +.set CYDEV_UCFG_DSI5_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI6_BASE, 0x40014600 +.set CYDEV_UCFG_DSI6_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI7_BASE, 0x40014700 +.set CYDEV_UCFG_DSI7_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI8_BASE, 0x40014800 +.set CYDEV_UCFG_DSI8_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI9_BASE, 0x40014900 +.set CYDEV_UCFG_DSI9_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI12_BASE, 0x40014c00 +.set CYDEV_UCFG_DSI12_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI13_BASE, 0x40014d00 +.set CYDEV_UCFG_DSI13_SIZE, 0x000000ef +.set CYDEV_UCFG_BCTL0_BASE, 0x40015000 +.set CYDEV_UCFG_BCTL0_SIZE, 0x00000010 +.set CYDEV_UCFG_BCTL0_MDCLK_EN, 0x40015000 +.set CYDEV_UCFG_BCTL0_MBCLK_EN, 0x40015001 +.set CYDEV_UCFG_BCTL0_WAIT_CFG, 0x40015002 +.set CYDEV_UCFG_BCTL0_BANK_CTL, 0x40015003 +.set CYDEV_UCFG_BCTL0_UDB_TEST_3, 0x40015007 +.set CYDEV_UCFG_BCTL0_DCLK_EN0, 0x40015008 +.set CYDEV_UCFG_BCTL0_BCLK_EN0, 0x40015009 +.set CYDEV_UCFG_BCTL0_DCLK_EN1, 0x4001500a +.set CYDEV_UCFG_BCTL0_BCLK_EN1, 0x4001500b +.set CYDEV_UCFG_BCTL0_DCLK_EN2, 0x4001500c +.set CYDEV_UCFG_BCTL0_BCLK_EN2, 0x4001500d +.set CYDEV_UCFG_BCTL0_DCLK_EN3, 0x4001500e +.set CYDEV_UCFG_BCTL0_BCLK_EN3, 0x4001500f +.set CYDEV_UCFG_BCTL1_BASE, 0x40015010 +.set CYDEV_UCFG_BCTL1_SIZE, 0x00000010 +.set CYDEV_UCFG_BCTL1_MDCLK_EN, 0x40015010 +.set CYDEV_UCFG_BCTL1_MBCLK_EN, 0x40015011 +.set CYDEV_UCFG_BCTL1_WAIT_CFG, 0x40015012 +.set CYDEV_UCFG_BCTL1_BANK_CTL, 0x40015013 +.set CYDEV_UCFG_BCTL1_UDB_TEST_3, 0x40015017 +.set CYDEV_UCFG_BCTL1_DCLK_EN0, 0x40015018 +.set CYDEV_UCFG_BCTL1_BCLK_EN0, 0x40015019 +.set CYDEV_UCFG_BCTL1_DCLK_EN1, 0x4001501a +.set CYDEV_UCFG_BCTL1_BCLK_EN1, 0x4001501b +.set CYDEV_UCFG_BCTL1_DCLK_EN2, 0x4001501c +.set CYDEV_UCFG_BCTL1_BCLK_EN2, 0x4001501d +.set CYDEV_UCFG_BCTL1_DCLK_EN3, 0x4001501e +.set CYDEV_UCFG_BCTL1_BCLK_EN3, 0x4001501f +.set CYDEV_IDMUX_BASE, 0x40015100 +.set CYDEV_IDMUX_SIZE, 0x00000016 +.set CYDEV_IDMUX_IRQ_CTL0, 0x40015100 +.set CYDEV_IDMUX_IRQ_CTL1, 0x40015101 +.set CYDEV_IDMUX_IRQ_CTL2, 0x40015102 +.set CYDEV_IDMUX_IRQ_CTL3, 0x40015103 +.set CYDEV_IDMUX_IRQ_CTL4, 0x40015104 +.set CYDEV_IDMUX_IRQ_CTL5, 0x40015105 +.set CYDEV_IDMUX_IRQ_CTL6, 0x40015106 +.set CYDEV_IDMUX_IRQ_CTL7, 0x40015107 +.set CYDEV_IDMUX_DRQ_CTL0, 0x40015110 +.set CYDEV_IDMUX_DRQ_CTL1, 0x40015111 +.set CYDEV_IDMUX_DRQ_CTL2, 0x40015112 +.set CYDEV_IDMUX_DRQ_CTL3, 0x40015113 +.set CYDEV_IDMUX_DRQ_CTL4, 0x40015114 +.set CYDEV_IDMUX_DRQ_CTL5, 0x40015115 +.set CYDEV_CACHERAM_BASE, 0x40030000 +.set CYDEV_CACHERAM_SIZE, 0x00000400 +.set CYDEV_CACHERAM_DATA_MBASE, 0x40030000 +.set CYDEV_CACHERAM_DATA_MSIZE, 0x00000400 +.set CYDEV_SFR_BASE, 0x40050100 +.set CYDEV_SFR_SIZE, 0x000000fb +.set CYDEV_SFR_GPIO0, 0x40050180 +.set CYDEV_SFR_GPIRD0, 0x40050189 +.set CYDEV_SFR_GPIO0_SEL, 0x4005018a +.set CYDEV_SFR_GPIO1, 0x40050190 +.set CYDEV_SFR_GPIRD1, 0x40050191 +.set CYDEV_SFR_GPIO2, 0x40050198 +.set CYDEV_SFR_GPIRD2, 0x40050199 +.set CYDEV_SFR_GPIO2_SEL, 0x4005019a +.set CYDEV_SFR_GPIO1_SEL, 0x400501a2 +.set CYDEV_SFR_GPIO3, 0x400501b0 +.set CYDEV_SFR_GPIRD3, 0x400501b1 +.set CYDEV_SFR_GPIO3_SEL, 0x400501b2 +.set CYDEV_SFR_GPIO4, 0x400501c0 +.set CYDEV_SFR_GPIRD4, 0x400501c1 +.set CYDEV_SFR_GPIO4_SEL, 0x400501c2 +.set CYDEV_SFR_GPIO5, 0x400501c8 +.set CYDEV_SFR_GPIRD5, 0x400501c9 +.set CYDEV_SFR_GPIO5_SEL, 0x400501ca +.set CYDEV_SFR_GPIO6, 0x400501d8 +.set CYDEV_SFR_GPIRD6, 0x400501d9 +.set CYDEV_SFR_GPIO6_SEL, 0x400501da +.set CYDEV_SFR_GPIO12, 0x400501e8 +.set CYDEV_SFR_GPIRD12, 0x400501e9 +.set CYDEV_SFR_GPIO12_SEL, 0x400501f2 +.set CYDEV_SFR_GPIO15, 0x400501f8 +.set CYDEV_SFR_GPIRD15, 0x400501f9 +.set CYDEV_SFR_GPIO15_SEL, 0x400501fa +.set CYDEV_P3BA_BASE, 0x40050300 +.set CYDEV_P3BA_SIZE, 0x0000002b +.set CYDEV_P3BA_Y_START, 0x40050300 +.set CYDEV_P3BA_YROLL, 0x40050301 +.set CYDEV_P3BA_YCFG, 0x40050302 +.set CYDEV_P3BA_X_START1, 0x40050303 +.set CYDEV_P3BA_X_START2, 0x40050304 +.set CYDEV_P3BA_XROLL1, 0x40050305 +.set CYDEV_P3BA_XROLL2, 0x40050306 +.set CYDEV_P3BA_XINC, 0x40050307 +.set CYDEV_P3BA_XCFG, 0x40050308 +.set CYDEV_P3BA_OFFSETADDR1, 0x40050309 +.set CYDEV_P3BA_OFFSETADDR2, 0x4005030a +.set CYDEV_P3BA_OFFSETADDR3, 0x4005030b +.set CYDEV_P3BA_ABSADDR1, 0x4005030c +.set CYDEV_P3BA_ABSADDR2, 0x4005030d +.set CYDEV_P3BA_ABSADDR3, 0x4005030e +.set CYDEV_P3BA_ABSADDR4, 0x4005030f +.set CYDEV_P3BA_DATCFG1, 0x40050310 +.set CYDEV_P3BA_DATCFG2, 0x40050311 +.set CYDEV_P3BA_CMP_RSLT1, 0x40050314 +.set CYDEV_P3BA_CMP_RSLT2, 0x40050315 +.set CYDEV_P3BA_CMP_RSLT3, 0x40050316 +.set CYDEV_P3BA_CMP_RSLT4, 0x40050317 +.set CYDEV_P3BA_DATA_REG1, 0x40050318 +.set CYDEV_P3BA_DATA_REG2, 0x40050319 +.set CYDEV_P3BA_DATA_REG3, 0x4005031a +.set CYDEV_P3BA_DATA_REG4, 0x4005031b +.set CYDEV_P3BA_EXP_DATA1, 0x4005031c +.set CYDEV_P3BA_EXP_DATA2, 0x4005031d +.set CYDEV_P3BA_EXP_DATA3, 0x4005031e +.set CYDEV_P3BA_EXP_DATA4, 0x4005031f +.set CYDEV_P3BA_MSTR_HRDATA1, 0x40050320 +.set CYDEV_P3BA_MSTR_HRDATA2, 0x40050321 +.set CYDEV_P3BA_MSTR_HRDATA3, 0x40050322 +.set CYDEV_P3BA_MSTR_HRDATA4, 0x40050323 +.set CYDEV_P3BA_BIST_EN, 0x40050324 +.set CYDEV_P3BA_PHUB_MASTER_SSR, 0x40050325 +.set CYDEV_P3BA_SEQCFG1, 0x40050326 +.set CYDEV_P3BA_SEQCFG2, 0x40050327 +.set CYDEV_P3BA_Y_CURR, 0x40050328 +.set CYDEV_P3BA_X_CURR1, 0x40050329 +.set CYDEV_P3BA_X_CURR2, 0x4005032a +.set CYDEV_PANTHER_BASE, 0x40080000 +.set CYDEV_PANTHER_SIZE, 0x00000020 +.set CYDEV_PANTHER_STCALIB_CFG, 0x40080000 +.set CYDEV_PANTHER_WAITPIPE, 0x40080004 +.set CYDEV_PANTHER_TRACE_CFG, 0x40080008 +.set CYDEV_PANTHER_DBG_CFG, 0x4008000c +.set CYDEV_PANTHER_CM3_LCKRST_STAT, 0x40080018 +.set CYDEV_PANTHER_DEVICE_ID, 0x4008001c +.set CYDEV_FLSECC_BASE, 0x48000000 +.set CYDEV_FLSECC_SIZE, 0x00008000 +.set CYDEV_FLSECC_DATA_MBASE, 0x48000000 +.set CYDEV_FLSECC_DATA_MSIZE, 0x00008000 +.set CYDEV_FLSHID_BASE, 0x49000000 +.set CYDEV_FLSHID_SIZE, 0x00000200 +.set CYDEV_FLSHID_RSVD_MBASE, 0x49000000 +.set CYDEV_FLSHID_RSVD_MSIZE, 0x00000080 +.set CYDEV_FLSHID_CUST_MDATA_MBASE, 0x49000080 +.set CYDEV_FLSHID_CUST_MDATA_MSIZE, 0x00000080 +.set CYDEV_FLSHID_CUST_TABLES_BASE, 0x49000100 +.set CYDEV_FLSHID_CUST_TABLES_SIZE, 0x00000040 +.set CYDEV_FLSHID_CUST_TABLES_Y_LOC, 0x49000100 +.set CYDEV_FLSHID_CUST_TABLES_X_LOC, 0x49000101 +.set CYDEV_FLSHID_CUST_TABLES_WAFER_NUM, 0x49000102 +.set CYDEV_FLSHID_CUST_TABLES_LOT_LSB, 0x49000103 +.set CYDEV_FLSHID_CUST_TABLES_LOT_MSB, 0x49000104 +.set CYDEV_FLSHID_CUST_TABLES_WRK_WK, 0x49000105 +.set CYDEV_FLSHID_CUST_TABLES_FAB_YR, 0x49000106 +.set CYDEV_FLSHID_CUST_TABLES_MINOR, 0x49000107 +.set CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ, 0x49000108 +.set CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ, 0x49000109 +.set CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ, 0x4900010a +.set CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ, 0x4900010b +.set CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ, 0x4900010c +.set CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ, 0x4900010d +.set CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ, 0x4900010e +.set CYDEV_FLSHID_CUST_TABLES_IMO_USB, 0x4900010f +.set CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS, 0x49000110 +.set CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS, 0x49000111 +.set CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS, 0x49000112 +.set CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS, 0x49000113 +.set CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS, 0x49000114 +.set CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS, 0x49000115 +.set CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS, 0x49000116 +.set CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS, 0x49000117 +.set CYDEV_FLSHID_CUST_TABLES_DEC_M1, 0x49000118 +.set CYDEV_FLSHID_CUST_TABLES_DEC_M2, 0x49000119 +.set CYDEV_FLSHID_CUST_TABLES_DEC_M3, 0x4900011a +.set CYDEV_FLSHID_CUST_TABLES_DEC_M4, 0x4900011b +.set CYDEV_FLSHID_CUST_TABLES_DEC_M5, 0x4900011c +.set CYDEV_FLSHID_CUST_TABLES_DEC_M6, 0x4900011d +.set CYDEV_FLSHID_CUST_TABLES_DEC_M7, 0x4900011e +.set CYDEV_FLSHID_CUST_TABLES_DEC_M8, 0x4900011f +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M1, 0x49000120 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M2, 0x49000121 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M3, 0x49000122 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M4, 0x49000123 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M5, 0x49000124 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M6, 0x49000125 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M7, 0x49000126 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M8, 0x49000127 +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M1, 0x49000128 +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M2, 0x49000129 +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M3, 0x4900012a +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M4, 0x4900012b +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M5, 0x4900012c +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M6, 0x4900012d +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M7, 0x4900012e +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M8, 0x4900012f +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M1, 0x49000130 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M2, 0x49000131 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M3, 0x49000132 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M4, 0x49000133 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M5, 0x49000134 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M6, 0x49000135 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M7, 0x49000136 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M8, 0x49000137 +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M1, 0x49000138 +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M2, 0x49000139 +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M3, 0x4900013a +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M4, 0x4900013b +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M5, 0x4900013c +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M6, 0x4900013d +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M7, 0x4900013e +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M8, 0x4900013f +.set CYDEV_FLSHID_MFG_CFG_BASE, 0x49000180 +.set CYDEV_FLSHID_MFG_CFG_SIZE, 0x00000080 +.set CYDEV_FLSHID_MFG_CFG_IMO_TR1, 0x49000188 +.set CYDEV_FLSHID_MFG_CFG_CMP0_TR0, 0x490001ac +.set CYDEV_FLSHID_MFG_CFG_CMP1_TR0, 0x490001ae +.set CYDEV_FLSHID_MFG_CFG_CMP2_TR0, 0x490001b0 +.set CYDEV_FLSHID_MFG_CFG_CMP3_TR0, 0x490001b2 +.set CYDEV_FLSHID_MFG_CFG_CMP0_TR1, 0x490001b4 +.set CYDEV_FLSHID_MFG_CFG_CMP1_TR1, 0x490001b6 +.set CYDEV_FLSHID_MFG_CFG_CMP2_TR1, 0x490001b8 +.set CYDEV_FLSHID_MFG_CFG_CMP3_TR1, 0x490001ba +.set CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM, 0x490001ce +.set CYDEV_EXTMEM_BASE, 0x60000000 +.set CYDEV_EXTMEM_SIZE, 0x00800000 +.set CYDEV_EXTMEM_DATA_MBASE, 0x60000000 +.set CYDEV_EXTMEM_DATA_MSIZE, 0x00800000 +.set CYDEV_ITM_BASE, 0xe0000000 +.set CYDEV_ITM_SIZE, 0x00001000 +.set CYDEV_ITM_TRACE_EN, 0xe0000e00 +.set CYDEV_ITM_TRACE_PRIVILEGE, 0xe0000e40 +.set CYDEV_ITM_TRACE_CTRL, 0xe0000e80 +.set CYDEV_ITM_LOCK_ACCESS, 0xe0000fb0 +.set CYDEV_ITM_LOCK_STATUS, 0xe0000fb4 +.set CYDEV_ITM_PID4, 0xe0000fd0 +.set CYDEV_ITM_PID5, 0xe0000fd4 +.set CYDEV_ITM_PID6, 0xe0000fd8 +.set CYDEV_ITM_PID7, 0xe0000fdc +.set CYDEV_ITM_PID0, 0xe0000fe0 +.set CYDEV_ITM_PID1, 0xe0000fe4 +.set CYDEV_ITM_PID2, 0xe0000fe8 +.set CYDEV_ITM_PID3, 0xe0000fec +.set CYDEV_ITM_CID0, 0xe0000ff0 +.set CYDEV_ITM_CID1, 0xe0000ff4 +.set CYDEV_ITM_CID2, 0xe0000ff8 +.set CYDEV_ITM_CID3, 0xe0000ffc +.set CYDEV_DWT_BASE, 0xe0001000 +.set CYDEV_DWT_SIZE, 0x0000005c +.set CYDEV_DWT_CTRL, 0xe0001000 +.set CYDEV_DWT_CYCLE_COUNT, 0xe0001004 +.set CYDEV_DWT_CPI_COUNT, 0xe0001008 +.set CYDEV_DWT_EXC_OVHD_COUNT, 0xe000100c +.set CYDEV_DWT_SLEEP_COUNT, 0xe0001010 +.set CYDEV_DWT_LSU_COUNT, 0xe0001014 +.set CYDEV_DWT_FOLD_COUNT, 0xe0001018 +.set CYDEV_DWT_PC_SAMPLE, 0xe000101c +.set CYDEV_DWT_COMP_0, 0xe0001020 +.set CYDEV_DWT_MASK_0, 0xe0001024 +.set CYDEV_DWT_FUNCTION_0, 0xe0001028 +.set CYDEV_DWT_COMP_1, 0xe0001030 +.set CYDEV_DWT_MASK_1, 0xe0001034 +.set CYDEV_DWT_FUNCTION_1, 0xe0001038 +.set CYDEV_DWT_COMP_2, 0xe0001040 +.set CYDEV_DWT_MASK_2, 0xe0001044 +.set CYDEV_DWT_FUNCTION_2, 0xe0001048 +.set CYDEV_DWT_COMP_3, 0xe0001050 +.set CYDEV_DWT_MASK_3, 0xe0001054 +.set CYDEV_DWT_FUNCTION_3, 0xe0001058 +.set CYDEV_FPB_BASE, 0xe0002000 +.set CYDEV_FPB_SIZE, 0x00001000 +.set CYDEV_FPB_CTRL, 0xe0002000 +.set CYDEV_FPB_REMAP, 0xe0002004 +.set CYDEV_FPB_FP_COMP_0, 0xe0002008 +.set CYDEV_FPB_FP_COMP_1, 0xe000200c +.set CYDEV_FPB_FP_COMP_2, 0xe0002010 +.set CYDEV_FPB_FP_COMP_3, 0xe0002014 +.set CYDEV_FPB_FP_COMP_4, 0xe0002018 +.set CYDEV_FPB_FP_COMP_5, 0xe000201c +.set CYDEV_FPB_FP_COMP_6, 0xe0002020 +.set CYDEV_FPB_FP_COMP_7, 0xe0002024 +.set CYDEV_FPB_PID4, 0xe0002fd0 +.set CYDEV_FPB_PID5, 0xe0002fd4 +.set CYDEV_FPB_PID6, 0xe0002fd8 +.set CYDEV_FPB_PID7, 0xe0002fdc +.set CYDEV_FPB_PID0, 0xe0002fe0 +.set CYDEV_FPB_PID1, 0xe0002fe4 +.set CYDEV_FPB_PID2, 0xe0002fe8 +.set CYDEV_FPB_PID3, 0xe0002fec +.set CYDEV_FPB_CID0, 0xe0002ff0 +.set CYDEV_FPB_CID1, 0xe0002ff4 +.set CYDEV_FPB_CID2, 0xe0002ff8 +.set CYDEV_FPB_CID3, 0xe0002ffc +.set CYDEV_NVIC_BASE, 0xe000e000 +.set CYDEV_NVIC_SIZE, 0x00000d3c +.set CYDEV_NVIC_INT_CTL_TYPE, 0xe000e004 +.set CYDEV_NVIC_SYSTICK_CTL, 0xe000e010 +.set CYDEV_NVIC_SYSTICK_RELOAD, 0xe000e014 +.set CYDEV_NVIC_SYSTICK_CURRENT, 0xe000e018 +.set CYDEV_NVIC_SYSTICK_CAL, 0xe000e01c +.set CYDEV_NVIC_SETENA0, 0xe000e100 +.set CYDEV_NVIC_CLRENA0, 0xe000e180 +.set CYDEV_NVIC_SETPEND0, 0xe000e200 +.set CYDEV_NVIC_CLRPEND0, 0xe000e280 +.set CYDEV_NVIC_ACTIVE0, 0xe000e300 +.set CYDEV_NVIC_PRI_0, 0xe000e400 +.set CYDEV_NVIC_PRI_1, 0xe000e401 +.set CYDEV_NVIC_PRI_2, 0xe000e402 +.set CYDEV_NVIC_PRI_3, 0xe000e403 +.set CYDEV_NVIC_PRI_4, 0xe000e404 +.set CYDEV_NVIC_PRI_5, 0xe000e405 +.set CYDEV_NVIC_PRI_6, 0xe000e406 +.set CYDEV_NVIC_PRI_7, 0xe000e407 +.set CYDEV_NVIC_PRI_8, 0xe000e408 +.set CYDEV_NVIC_PRI_9, 0xe000e409 +.set CYDEV_NVIC_PRI_10, 0xe000e40a +.set CYDEV_NVIC_PRI_11, 0xe000e40b +.set CYDEV_NVIC_PRI_12, 0xe000e40c +.set CYDEV_NVIC_PRI_13, 0xe000e40d +.set CYDEV_NVIC_PRI_14, 0xe000e40e +.set CYDEV_NVIC_PRI_15, 0xe000e40f +.set CYDEV_NVIC_PRI_16, 0xe000e410 +.set CYDEV_NVIC_PRI_17, 0xe000e411 +.set CYDEV_NVIC_PRI_18, 0xe000e412 +.set CYDEV_NVIC_PRI_19, 0xe000e413 +.set CYDEV_NVIC_PRI_20, 0xe000e414 +.set CYDEV_NVIC_PRI_21, 0xe000e415 +.set CYDEV_NVIC_PRI_22, 0xe000e416 +.set CYDEV_NVIC_PRI_23, 0xe000e417 +.set CYDEV_NVIC_PRI_24, 0xe000e418 +.set CYDEV_NVIC_PRI_25, 0xe000e419 +.set CYDEV_NVIC_PRI_26, 0xe000e41a +.set CYDEV_NVIC_PRI_27, 0xe000e41b +.set CYDEV_NVIC_PRI_28, 0xe000e41c +.set CYDEV_NVIC_PRI_29, 0xe000e41d +.set CYDEV_NVIC_PRI_30, 0xe000e41e +.set CYDEV_NVIC_PRI_31, 0xe000e41f +.set CYDEV_NVIC_CPUID_BASE, 0xe000ed00 +.set CYDEV_NVIC_INTR_CTRL_STATE, 0xe000ed04 +.set CYDEV_NVIC_VECT_OFFSET, 0xe000ed08 +.set CYDEV_NVIC_APPLN_INTR, 0xe000ed0c +.set CYDEV_NVIC_SYSTEM_CONTROL, 0xe000ed10 +.set CYDEV_NVIC_CFG_CONTROL, 0xe000ed14 +.set CYDEV_NVIC_SYS_PRIO_HANDLER_4_7, 0xe000ed18 +.set CYDEV_NVIC_SYS_PRIO_HANDLER_8_11, 0xe000ed1c +.set CYDEV_NVIC_SYS_PRIO_HANDLER_12_15, 0xe000ed20 +.set CYDEV_NVIC_SYS_HANDLER_CSR, 0xe000ed24 +.set CYDEV_NVIC_MEMMAN_FAULT_STATUS, 0xe000ed28 +.set CYDEV_NVIC_BUS_FAULT_STATUS, 0xe000ed29 +.set CYDEV_NVIC_USAGE_FAULT_STATUS, 0xe000ed2a +.set CYDEV_NVIC_HARD_FAULT_STATUS, 0xe000ed2c +.set CYDEV_NVIC_DEBUG_FAULT_STATUS, 0xe000ed30 +.set CYDEV_NVIC_MEMMAN_FAULT_ADD, 0xe000ed34 +.set CYDEV_NVIC_BUS_FAULT_ADD, 0xe000ed38 +.set CYDEV_CORE_DBG_BASE, 0xe000edf0 +.set CYDEV_CORE_DBG_SIZE, 0x00000010 +.set CYDEV_CORE_DBG_DBG_HLT_CS, 0xe000edf0 +.set CYDEV_CORE_DBG_DBG_REG_SEL, 0xe000edf4 +.set CYDEV_CORE_DBG_DBG_REG_DATA, 0xe000edf8 +.set CYDEV_CORE_DBG_EXC_MON_CTL, 0xe000edfc +.set CYDEV_TPIU_BASE, 0xe0040000 +.set CYDEV_TPIU_SIZE, 0x00001000 +.set CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ, 0xe0040000 +.set CYDEV_TPIU_CURRENT_SYNC_PRT_SZ, 0xe0040004 +.set CYDEV_TPIU_ASYNC_CLK_PRESCALER, 0xe0040010 +.set CYDEV_TPIU_PROTOCOL, 0xe00400f0 +.set CYDEV_TPIU_FORM_FLUSH_STAT, 0xe0040300 +.set CYDEV_TPIU_FORM_FLUSH_CTRL, 0xe0040304 +.set CYDEV_TPIU_TRIGGER, 0xe0040ee8 +.set CYDEV_TPIU_ITETMDATA, 0xe0040eec +.set CYDEV_TPIU_ITATBCTR2, 0xe0040ef0 +.set CYDEV_TPIU_ITATBCTR0, 0xe0040ef8 +.set CYDEV_TPIU_ITITMDATA, 0xe0040efc +.set CYDEV_TPIU_ITCTRL, 0xe0040f00 +.set CYDEV_TPIU_DEVID, 0xe0040fc8 +.set CYDEV_TPIU_DEVTYPE, 0xe0040fcc +.set CYDEV_TPIU_PID4, 0xe0040fd0 +.set CYDEV_TPIU_PID5, 0xe0040fd4 +.set CYDEV_TPIU_PID6, 0xe0040fd8 +.set CYDEV_TPIU_PID7, 0xe0040fdc +.set CYDEV_TPIU_PID0, 0xe0040fe0 +.set CYDEV_TPIU_PID1, 0xe0040fe4 +.set CYDEV_TPIU_PID2, 0xe0040fe8 +.set CYDEV_TPIU_PID3, 0xe0040fec +.set CYDEV_TPIU_CID0, 0xe0040ff0 +.set CYDEV_TPIU_CID1, 0xe0040ff4 +.set CYDEV_TPIU_CID2, 0xe0040ff8 +.set CYDEV_TPIU_CID3, 0xe0040ffc +.set CYDEV_ETM_BASE, 0xe0041000 +.set CYDEV_ETM_SIZE, 0x00001000 +.set CYDEV_ETM_CTL, 0xe0041000 +.set CYDEV_ETM_CFG_CODE, 0xe0041004 +.set CYDEV_ETM_TRIG_EVENT, 0xe0041008 +.set CYDEV_ETM_STATUS, 0xe0041010 +.set CYDEV_ETM_SYS_CFG, 0xe0041014 +.set CYDEV_ETM_TRACE_ENB_EVENT, 0xe0041020 +.set CYDEV_ETM_TRACE_EN_CTRL1, 0xe0041024 +.set CYDEV_ETM_FIFOFULL_LEVEL, 0xe004102c +.set CYDEV_ETM_SYNC_FREQ, 0xe00411e0 +.set CYDEV_ETM_ETM_ID, 0xe00411e4 +.set CYDEV_ETM_CFG_CODE_EXT, 0xe00411e8 +.set CYDEV_ETM_TR_SS_EMBICE_CTRL, 0xe00411f0 +.set CYDEV_ETM_CS_TRACE_ID, 0xe0041200 +.set CYDEV_ETM_OS_LOCK_ACCESS, 0xe0041300 +.set CYDEV_ETM_OS_LOCK_STATUS, 0xe0041304 +.set CYDEV_ETM_PDSR, 0xe0041314 +.set CYDEV_ETM_ITMISCIN, 0xe0041ee0 +.set CYDEV_ETM_ITTRIGOUT, 0xe0041ee8 +.set CYDEV_ETM_ITATBCTR2, 0xe0041ef0 +.set CYDEV_ETM_ITATBCTR0, 0xe0041ef8 +.set CYDEV_ETM_INT_MODE_CTRL, 0xe0041f00 +.set CYDEV_ETM_CLM_TAG_SET, 0xe0041fa0 +.set CYDEV_ETM_CLM_TAG_CLR, 0xe0041fa4 +.set CYDEV_ETM_LOCK_ACCESS, 0xe0041fb0 +.set CYDEV_ETM_LOCK_STATUS, 0xe0041fb4 +.set CYDEV_ETM_AUTH_STATUS, 0xe0041fb8 +.set CYDEV_ETM_DEV_TYPE, 0xe0041fcc +.set CYDEV_ETM_PID4, 0xe0041fd0 +.set CYDEV_ETM_PID5, 0xe0041fd4 +.set CYDEV_ETM_PID6, 0xe0041fd8 +.set CYDEV_ETM_PID7, 0xe0041fdc +.set CYDEV_ETM_PID0, 0xe0041fe0 +.set CYDEV_ETM_PID1, 0xe0041fe4 +.set CYDEV_ETM_PID2, 0xe0041fe8 +.set CYDEV_ETM_PID3, 0xe0041fec +.set CYDEV_ETM_CID0, 0xe0041ff0 +.set CYDEV_ETM_CID1, 0xe0041ff4 +.set CYDEV_ETM_CID2, 0xe0041ff8 +.set CYDEV_ETM_CID3, 0xe0041ffc +.set CYDEV_ROM_TABLE_BASE, 0xe00ff000 +.set CYDEV_ROM_TABLE_SIZE, 0x00001000 +.set CYDEV_ROM_TABLE_NVIC, 0xe00ff000 +.set CYDEV_ROM_TABLE_DWT, 0xe00ff004 +.set CYDEV_ROM_TABLE_FPB, 0xe00ff008 +.set CYDEV_ROM_TABLE_ITM, 0xe00ff00c +.set CYDEV_ROM_TABLE_TPIU, 0xe00ff010 +.set CYDEV_ROM_TABLE_ETM, 0xe00ff014 +.set CYDEV_ROM_TABLE_END, 0xe00ff018 +.set CYDEV_ROM_TABLE_MEMTYPE, 0xe00fffcc +.set CYDEV_ROM_TABLE_PID4, 0xe00fffd0 +.set CYDEV_ROM_TABLE_PID5, 0xe00fffd4 +.set CYDEV_ROM_TABLE_PID6, 0xe00fffd8 +.set CYDEV_ROM_TABLE_PID7, 0xe00fffdc +.set CYDEV_ROM_TABLE_PID0, 0xe00fffe0 +.set CYDEV_ROM_TABLE_PID1, 0xe00fffe4 +.set CYDEV_ROM_TABLE_PID2, 0xe00fffe8 +.set CYDEV_ROM_TABLE_PID3, 0xe00fffec +.set CYDEV_ROM_TABLE_CID0, 0xe00ffff0 +.set CYDEV_ROM_TABLE_CID1, 0xe00ffff4 +.set CYDEV_ROM_TABLE_CID2, 0xe00ffff8 +.set CYDEV_ROM_TABLE_CID3, 0xe00ffffc +.set CYDEV_FLS_SIZE, CYDEV_FLASH_SIZE +.set CYDEV_ECC_BASE, CYDEV_FLSECC_BASE +.set CYDEV_FLS_SECTOR_SIZE, 0x00010000 +.set CYDEV_FLS_ROW_SIZE, 0x00000100 +.set CYDEV_ECC_SECTOR_SIZE, 0x00002000 +.set CYDEV_ECC_ROW_SIZE, 0x00000020 +.set CYDEV_EEPROM_SECTOR_SIZE, 0x00000400 +.set CYDEV_EEPROM_ROW_SIZE, 0x00000010 +.set CYDEV_PERIPH_BASE, CYDEV_CLKDIST_BASE +.set CYCLK_LD_DISABLE, 0x00000004 +.set CYCLK_LD_SYNC_EN, 0x00000002 +.set CYCLK_LD_LOAD, 0x00000001 +.set CYCLK_PIPE, 0x00000080 +.set CYCLK_SSS, 0x00000040 +.set CYCLK_EARLY, 0x00000020 +.set CYCLK_DUTY, 0x00000010 +.set CYCLK_SYNC, 0x00000008 +.set CYCLK_SRC_SEL_CLK_SYNC_D, 0 +.set CYCLK_SRC_SEL_SYNC_DIG, 0 +.set CYCLK_SRC_SEL_IMO, 1 +.set CYCLK_SRC_SEL_XTAL_MHZ, 2 +.set CYCLK_SRC_SEL_XTALM, 2 +.set CYCLK_SRC_SEL_ILO, 3 +.set CYCLK_SRC_SEL_PLL, 4 +.set CYCLK_SRC_SEL_XTAL_KHZ, 5 +.set CYCLK_SRC_SEL_XTALK, 5 +.set CYCLK_SRC_SEL_DSI_G, 6 +.set CYCLK_SRC_SEL_DSI_D, 7 +.set CYCLK_SRC_SEL_CLK_SYNC_A, 0 +.set CYCLK_SRC_SEL_DSI_A, 7 diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc new file mode 100755 index 00000000..ede64b20 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc @@ -0,0 +1,5357 @@ +/******************************************************************************* +* FILENAME: cydevicegnu_trm.inc +* +* PSoC Creator 3.0 Component Pack 7 +* +* DESCRIPTION: +* This file provides all of the address values for the entire PSoC device. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +.set CYDEV_FLASH_BASE, 0x00000000 +.set CYDEV_FLASH_SIZE, 0x00020000 +.set CYREG_FLASH_DATA_MBASE, 0x00000000 +.set CYREG_FLASH_DATA_MSIZE, 0x00020000 +.set CYDEV_SRAM_BASE, 0x1fffc000 +.set CYDEV_SRAM_SIZE, 0x00008000 +.set CYREG_SRAM_CODE64K_MBASE, 0x1fff8000 +.set CYREG_SRAM_CODE64K_MSIZE, 0x00004000 +.set CYREG_SRAM_CODE32K_MBASE, 0x1fffc000 +.set CYREG_SRAM_CODE32K_MSIZE, 0x00002000 +.set CYREG_SRAM_CODE16K_MBASE, 0x1fffe000 +.set CYREG_SRAM_CODE16K_MSIZE, 0x00001000 +.set CYREG_SRAM_CODE_MBASE, 0x1fffc000 +.set CYREG_SRAM_CODE_MSIZE, 0x00004000 +.set CYREG_SRAM_DATA_MBASE, 0x20000000 +.set CYREG_SRAM_DATA_MSIZE, 0x00004000 +.set CYREG_SRAM_DATA16K_MBASE, 0x20001000 +.set CYREG_SRAM_DATA16K_MSIZE, 0x00001000 +.set CYREG_SRAM_DATA32K_MBASE, 0x20002000 +.set CYREG_SRAM_DATA32K_MSIZE, 0x00002000 +.set CYREG_SRAM_DATA64K_MBASE, 0x20004000 +.set CYREG_SRAM_DATA64K_MSIZE, 0x00004000 +.set CYDEV_DMA_BASE, 0x20008000 +.set CYDEV_DMA_SIZE, 0x00008000 +.set CYREG_DMA_SRAM64K_MBASE, 0x20008000 +.set CYREG_DMA_SRAM64K_MSIZE, 0x00004000 +.set CYREG_DMA_SRAM32K_MBASE, 0x2000c000 +.set CYREG_DMA_SRAM32K_MSIZE, 0x00002000 +.set CYREG_DMA_SRAM16K_MBASE, 0x2000e000 +.set CYREG_DMA_SRAM16K_MSIZE, 0x00001000 +.set CYREG_DMA_SRAM_MBASE, 0x2000f000 +.set CYREG_DMA_SRAM_MSIZE, 0x00001000 +.set CYDEV_CLKDIST_BASE, 0x40004000 +.set CYDEV_CLKDIST_SIZE, 0x00000110 +.set CYREG_CLKDIST_CR, 0x40004000 +.set CYREG_CLKDIST_LD, 0x40004001 +.set CYREG_CLKDIST_WRK0, 0x40004002 +.set CYREG_CLKDIST_WRK1, 0x40004003 +.set CYREG_CLKDIST_MSTR0, 0x40004004 +.set CYREG_CLKDIST_MSTR1, 0x40004005 +.set CYREG_CLKDIST_BCFG0, 0x40004006 +.set CYREG_CLKDIST_BCFG1, 0x40004007 +.set CYREG_CLKDIST_BCFG2, 0x40004008 +.set CYREG_CLKDIST_UCFG, 0x40004009 +.set CYREG_CLKDIST_DLY0, 0x4000400a +.set CYREG_CLKDIST_DLY1, 0x4000400b +.set CYREG_CLKDIST_DMASK, 0x40004010 +.set CYREG_CLKDIST_AMASK, 0x40004014 +.set CYDEV_CLKDIST_DCFG0_BASE, 0x40004080 +.set CYDEV_CLKDIST_DCFG0_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG0_CFG0, 0x40004080 +.set CYREG_CLKDIST_DCFG0_CFG1, 0x40004081 +.set CYREG_CLKDIST_DCFG0_CFG2, 0x40004082 +.set CYDEV_CLKDIST_DCFG1_BASE, 0x40004084 +.set CYDEV_CLKDIST_DCFG1_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG1_CFG0, 0x40004084 +.set CYREG_CLKDIST_DCFG1_CFG1, 0x40004085 +.set CYREG_CLKDIST_DCFG1_CFG2, 0x40004086 +.set CYDEV_CLKDIST_DCFG2_BASE, 0x40004088 +.set CYDEV_CLKDIST_DCFG2_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG2_CFG0, 0x40004088 +.set CYREG_CLKDIST_DCFG2_CFG1, 0x40004089 +.set CYREG_CLKDIST_DCFG2_CFG2, 0x4000408a +.set CYDEV_CLKDIST_DCFG3_BASE, 0x4000408c +.set CYDEV_CLKDIST_DCFG3_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG3_CFG0, 0x4000408c +.set CYREG_CLKDIST_DCFG3_CFG1, 0x4000408d +.set CYREG_CLKDIST_DCFG3_CFG2, 0x4000408e +.set CYDEV_CLKDIST_DCFG4_BASE, 0x40004090 +.set CYDEV_CLKDIST_DCFG4_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG4_CFG0, 0x40004090 +.set CYREG_CLKDIST_DCFG4_CFG1, 0x40004091 +.set CYREG_CLKDIST_DCFG4_CFG2, 0x40004092 +.set CYDEV_CLKDIST_DCFG5_BASE, 0x40004094 +.set CYDEV_CLKDIST_DCFG5_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG5_CFG0, 0x40004094 +.set CYREG_CLKDIST_DCFG5_CFG1, 0x40004095 +.set CYREG_CLKDIST_DCFG5_CFG2, 0x40004096 +.set CYDEV_CLKDIST_DCFG6_BASE, 0x40004098 +.set CYDEV_CLKDIST_DCFG6_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG6_CFG0, 0x40004098 +.set CYREG_CLKDIST_DCFG6_CFG1, 0x40004099 +.set CYREG_CLKDIST_DCFG6_CFG2, 0x4000409a +.set CYDEV_CLKDIST_DCFG7_BASE, 0x4000409c +.set CYDEV_CLKDIST_DCFG7_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG7_CFG0, 0x4000409c +.set CYREG_CLKDIST_DCFG7_CFG1, 0x4000409d +.set CYREG_CLKDIST_DCFG7_CFG2, 0x4000409e +.set CYDEV_CLKDIST_ACFG0_BASE, 0x40004100 +.set CYDEV_CLKDIST_ACFG0_SIZE, 0x00000004 +.set CYREG_CLKDIST_ACFG0_CFG0, 0x40004100 +.set CYREG_CLKDIST_ACFG0_CFG1, 0x40004101 +.set CYREG_CLKDIST_ACFG0_CFG2, 0x40004102 +.set CYREG_CLKDIST_ACFG0_CFG3, 0x40004103 +.set CYDEV_CLKDIST_ACFG1_BASE, 0x40004104 +.set CYDEV_CLKDIST_ACFG1_SIZE, 0x00000004 +.set CYREG_CLKDIST_ACFG1_CFG0, 0x40004104 +.set CYREG_CLKDIST_ACFG1_CFG1, 0x40004105 +.set CYREG_CLKDIST_ACFG1_CFG2, 0x40004106 +.set CYREG_CLKDIST_ACFG1_CFG3, 0x40004107 +.set CYDEV_CLKDIST_ACFG2_BASE, 0x40004108 +.set CYDEV_CLKDIST_ACFG2_SIZE, 0x00000004 +.set CYREG_CLKDIST_ACFG2_CFG0, 0x40004108 +.set CYREG_CLKDIST_ACFG2_CFG1, 0x40004109 +.set CYREG_CLKDIST_ACFG2_CFG2, 0x4000410a +.set CYREG_CLKDIST_ACFG2_CFG3, 0x4000410b +.set CYDEV_CLKDIST_ACFG3_BASE, 0x4000410c +.set CYDEV_CLKDIST_ACFG3_SIZE, 0x00000004 +.set CYREG_CLKDIST_ACFG3_CFG0, 0x4000410c +.set CYREG_CLKDIST_ACFG3_CFG1, 0x4000410d +.set CYREG_CLKDIST_ACFG3_CFG2, 0x4000410e +.set CYREG_CLKDIST_ACFG3_CFG3, 0x4000410f +.set CYDEV_FASTCLK_BASE, 0x40004200 +.set CYDEV_FASTCLK_SIZE, 0x00000026 +.set CYDEV_FASTCLK_IMO_BASE, 0x40004200 +.set CYDEV_FASTCLK_IMO_SIZE, 0x00000001 +.set CYREG_FASTCLK_IMO_CR, 0x40004200 +.set CYDEV_FASTCLK_XMHZ_BASE, 0x40004210 +.set CYDEV_FASTCLK_XMHZ_SIZE, 0x00000004 +.set CYREG_FASTCLK_XMHZ_CSR, 0x40004210 +.set CYREG_FASTCLK_XMHZ_CFG0, 0x40004212 +.set CYREG_FASTCLK_XMHZ_CFG1, 0x40004213 +.set CYDEV_FASTCLK_PLL_BASE, 0x40004220 +.set CYDEV_FASTCLK_PLL_SIZE, 0x00000006 +.set CYREG_FASTCLK_PLL_CFG0, 0x40004220 +.set CYREG_FASTCLK_PLL_CFG1, 0x40004221 +.set CYREG_FASTCLK_PLL_P, 0x40004222 +.set CYREG_FASTCLK_PLL_Q, 0x40004223 +.set CYREG_FASTCLK_PLL_SR, 0x40004225 +.set CYDEV_SLOWCLK_BASE, 0x40004300 +.set CYDEV_SLOWCLK_SIZE, 0x0000000b +.set CYDEV_SLOWCLK_ILO_BASE, 0x40004300 +.set CYDEV_SLOWCLK_ILO_SIZE, 0x00000002 +.set CYREG_SLOWCLK_ILO_CR0, 0x40004300 +.set CYREG_SLOWCLK_ILO_CR1, 0x40004301 +.set CYDEV_SLOWCLK_X32_BASE, 0x40004308 +.set CYDEV_SLOWCLK_X32_SIZE, 0x00000003 +.set CYREG_SLOWCLK_X32_CR, 0x40004308 +.set CYREG_SLOWCLK_X32_CFG, 0x40004309 +.set CYREG_SLOWCLK_X32_TST, 0x4000430a +.set CYDEV_BOOST_BASE, 0x40004320 +.set CYDEV_BOOST_SIZE, 0x00000007 +.set CYREG_BOOST_CR0, 0x40004320 +.set CYREG_BOOST_CR1, 0x40004321 +.set CYREG_BOOST_CR2, 0x40004322 +.set CYREG_BOOST_CR3, 0x40004323 +.set CYREG_BOOST_SR, 0x40004324 +.set CYREG_BOOST_CR4, 0x40004325 +.set CYREG_BOOST_SR2, 0x40004326 +.set CYDEV_PWRSYS_BASE, 0x40004330 +.set CYDEV_PWRSYS_SIZE, 0x00000002 +.set CYREG_PWRSYS_CR0, 0x40004330 +.set CYREG_PWRSYS_CR1, 0x40004331 +.set CYDEV_PM_BASE, 0x40004380 +.set CYDEV_PM_SIZE, 0x00000057 +.set CYREG_PM_TW_CFG0, 0x40004380 +.set CYREG_PM_TW_CFG1, 0x40004381 +.set CYREG_PM_TW_CFG2, 0x40004382 +.set CYREG_PM_WDT_CFG, 0x40004383 +.set CYREG_PM_WDT_CR, 0x40004384 +.set CYREG_PM_INT_SR, 0x40004390 +.set CYREG_PM_MODE_CFG0, 0x40004391 +.set CYREG_PM_MODE_CFG1, 0x40004392 +.set CYREG_PM_MODE_CSR, 0x40004393 +.set CYREG_PM_USB_CR0, 0x40004394 +.set CYREG_PM_WAKEUP_CFG0, 0x40004398 +.set CYREG_PM_WAKEUP_CFG1, 0x40004399 +.set CYREG_PM_WAKEUP_CFG2, 0x4000439a +.set CYDEV_PM_ACT_BASE, 0x400043a0 +.set CYDEV_PM_ACT_SIZE, 0x0000000e +.set CYREG_PM_ACT_CFG0, 0x400043a0 +.set CYREG_PM_ACT_CFG1, 0x400043a1 +.set CYREG_PM_ACT_CFG2, 0x400043a2 +.set CYREG_PM_ACT_CFG3, 0x400043a3 +.set CYREG_PM_ACT_CFG4, 0x400043a4 +.set CYREG_PM_ACT_CFG5, 0x400043a5 +.set CYREG_PM_ACT_CFG6, 0x400043a6 +.set CYREG_PM_ACT_CFG7, 0x400043a7 +.set CYREG_PM_ACT_CFG8, 0x400043a8 +.set CYREG_PM_ACT_CFG9, 0x400043a9 +.set CYREG_PM_ACT_CFG10, 0x400043aa +.set CYREG_PM_ACT_CFG11, 0x400043ab +.set CYREG_PM_ACT_CFG12, 0x400043ac +.set CYREG_PM_ACT_CFG13, 0x400043ad +.set CYDEV_PM_STBY_BASE, 0x400043b0 +.set CYDEV_PM_STBY_SIZE, 0x0000000e +.set CYREG_PM_STBY_CFG0, 0x400043b0 +.set CYREG_PM_STBY_CFG1, 0x400043b1 +.set CYREG_PM_STBY_CFG2, 0x400043b2 +.set CYREG_PM_STBY_CFG3, 0x400043b3 +.set CYREG_PM_STBY_CFG4, 0x400043b4 +.set CYREG_PM_STBY_CFG5, 0x400043b5 +.set CYREG_PM_STBY_CFG6, 0x400043b6 +.set CYREG_PM_STBY_CFG7, 0x400043b7 +.set CYREG_PM_STBY_CFG8, 0x400043b8 +.set CYREG_PM_STBY_CFG9, 0x400043b9 +.set CYREG_PM_STBY_CFG10, 0x400043ba +.set CYREG_PM_STBY_CFG11, 0x400043bb +.set CYREG_PM_STBY_CFG12, 0x400043bc +.set CYREG_PM_STBY_CFG13, 0x400043bd +.set CYDEV_PM_AVAIL_BASE, 0x400043c0 +.set CYDEV_PM_AVAIL_SIZE, 0x00000017 +.set CYREG_PM_AVAIL_CR0, 0x400043c0 +.set CYREG_PM_AVAIL_CR1, 0x400043c1 +.set CYREG_PM_AVAIL_CR2, 0x400043c2 +.set CYREG_PM_AVAIL_CR3, 0x400043c3 +.set CYREG_PM_AVAIL_CR4, 0x400043c4 +.set CYREG_PM_AVAIL_CR5, 0x400043c5 +.set CYREG_PM_AVAIL_CR6, 0x400043c6 +.set CYREG_PM_AVAIL_SR0, 0x400043d0 +.set CYREG_PM_AVAIL_SR1, 0x400043d1 +.set CYREG_PM_AVAIL_SR2, 0x400043d2 +.set CYREG_PM_AVAIL_SR3, 0x400043d3 +.set CYREG_PM_AVAIL_SR4, 0x400043d4 +.set CYREG_PM_AVAIL_SR5, 0x400043d5 +.set CYREG_PM_AVAIL_SR6, 0x400043d6 +.set CYDEV_PICU_BASE, 0x40004500 +.set CYDEV_PICU_SIZE, 0x000000b0 +.set CYDEV_PICU_INTTYPE_BASE, 0x40004500 +.set CYDEV_PICU_INTTYPE_SIZE, 0x00000080 +.set CYDEV_PICU_INTTYPE_PICU0_BASE, 0x40004500 +.set CYDEV_PICU_INTTYPE_PICU0_SIZE, 0x00000008 +.set CYREG_PICU0_INTTYPE0, 0x40004500 +.set CYREG_PICU0_INTTYPE1, 0x40004501 +.set CYREG_PICU0_INTTYPE2, 0x40004502 +.set CYREG_PICU0_INTTYPE3, 0x40004503 +.set CYREG_PICU0_INTTYPE4, 0x40004504 +.set CYREG_PICU0_INTTYPE5, 0x40004505 +.set CYREG_PICU0_INTTYPE6, 0x40004506 +.set CYREG_PICU0_INTTYPE7, 0x40004507 +.set CYDEV_PICU_INTTYPE_PICU1_BASE, 0x40004508 +.set CYDEV_PICU_INTTYPE_PICU1_SIZE, 0x00000008 +.set CYREG_PICU1_INTTYPE0, 0x40004508 +.set CYREG_PICU1_INTTYPE1, 0x40004509 +.set CYREG_PICU1_INTTYPE2, 0x4000450a +.set CYREG_PICU1_INTTYPE3, 0x4000450b +.set CYREG_PICU1_INTTYPE4, 0x4000450c +.set CYREG_PICU1_INTTYPE5, 0x4000450d +.set CYREG_PICU1_INTTYPE6, 0x4000450e +.set CYREG_PICU1_INTTYPE7, 0x4000450f +.set CYDEV_PICU_INTTYPE_PICU2_BASE, 0x40004510 +.set CYDEV_PICU_INTTYPE_PICU2_SIZE, 0x00000008 +.set CYREG_PICU2_INTTYPE0, 0x40004510 +.set CYREG_PICU2_INTTYPE1, 0x40004511 +.set CYREG_PICU2_INTTYPE2, 0x40004512 +.set CYREG_PICU2_INTTYPE3, 0x40004513 +.set CYREG_PICU2_INTTYPE4, 0x40004514 +.set CYREG_PICU2_INTTYPE5, 0x40004515 +.set CYREG_PICU2_INTTYPE6, 0x40004516 +.set CYREG_PICU2_INTTYPE7, 0x40004517 +.set CYDEV_PICU_INTTYPE_PICU3_BASE, 0x40004518 +.set CYDEV_PICU_INTTYPE_PICU3_SIZE, 0x00000008 +.set CYREG_PICU3_INTTYPE0, 0x40004518 +.set CYREG_PICU3_INTTYPE1, 0x40004519 +.set CYREG_PICU3_INTTYPE2, 0x4000451a +.set CYREG_PICU3_INTTYPE3, 0x4000451b +.set CYREG_PICU3_INTTYPE4, 0x4000451c +.set CYREG_PICU3_INTTYPE5, 0x4000451d +.set CYREG_PICU3_INTTYPE6, 0x4000451e +.set CYREG_PICU3_INTTYPE7, 0x4000451f +.set CYDEV_PICU_INTTYPE_PICU4_BASE, 0x40004520 +.set CYDEV_PICU_INTTYPE_PICU4_SIZE, 0x00000008 +.set CYREG_PICU4_INTTYPE0, 0x40004520 +.set CYREG_PICU4_INTTYPE1, 0x40004521 +.set CYREG_PICU4_INTTYPE2, 0x40004522 +.set CYREG_PICU4_INTTYPE3, 0x40004523 +.set CYREG_PICU4_INTTYPE4, 0x40004524 +.set CYREG_PICU4_INTTYPE5, 0x40004525 +.set CYREG_PICU4_INTTYPE6, 0x40004526 +.set CYREG_PICU4_INTTYPE7, 0x40004527 +.set CYDEV_PICU_INTTYPE_PICU5_BASE, 0x40004528 +.set CYDEV_PICU_INTTYPE_PICU5_SIZE, 0x00000008 +.set CYREG_PICU5_INTTYPE0, 0x40004528 +.set CYREG_PICU5_INTTYPE1, 0x40004529 +.set CYREG_PICU5_INTTYPE2, 0x4000452a +.set CYREG_PICU5_INTTYPE3, 0x4000452b +.set CYREG_PICU5_INTTYPE4, 0x4000452c +.set CYREG_PICU5_INTTYPE5, 0x4000452d +.set CYREG_PICU5_INTTYPE6, 0x4000452e +.set CYREG_PICU5_INTTYPE7, 0x4000452f +.set CYDEV_PICU_INTTYPE_PICU6_BASE, 0x40004530 +.set CYDEV_PICU_INTTYPE_PICU6_SIZE, 0x00000008 +.set CYREG_PICU6_INTTYPE0, 0x40004530 +.set CYREG_PICU6_INTTYPE1, 0x40004531 +.set CYREG_PICU6_INTTYPE2, 0x40004532 +.set CYREG_PICU6_INTTYPE3, 0x40004533 +.set CYREG_PICU6_INTTYPE4, 0x40004534 +.set CYREG_PICU6_INTTYPE5, 0x40004535 +.set CYREG_PICU6_INTTYPE6, 0x40004536 +.set CYREG_PICU6_INTTYPE7, 0x40004537 +.set CYDEV_PICU_INTTYPE_PICU12_BASE, 0x40004560 +.set CYDEV_PICU_INTTYPE_PICU12_SIZE, 0x00000008 +.set CYREG_PICU12_INTTYPE0, 0x40004560 +.set CYREG_PICU12_INTTYPE1, 0x40004561 +.set CYREG_PICU12_INTTYPE2, 0x40004562 +.set CYREG_PICU12_INTTYPE3, 0x40004563 +.set CYREG_PICU12_INTTYPE4, 0x40004564 +.set CYREG_PICU12_INTTYPE5, 0x40004565 +.set CYREG_PICU12_INTTYPE6, 0x40004566 +.set CYREG_PICU12_INTTYPE7, 0x40004567 +.set CYDEV_PICU_INTTYPE_PICU15_BASE, 0x40004578 +.set CYDEV_PICU_INTTYPE_PICU15_SIZE, 0x00000008 +.set CYREG_PICU15_INTTYPE0, 0x40004578 +.set CYREG_PICU15_INTTYPE1, 0x40004579 +.set CYREG_PICU15_INTTYPE2, 0x4000457a +.set CYREG_PICU15_INTTYPE3, 0x4000457b +.set CYREG_PICU15_INTTYPE4, 0x4000457c +.set CYREG_PICU15_INTTYPE5, 0x4000457d +.set CYREG_PICU15_INTTYPE6, 0x4000457e +.set CYREG_PICU15_INTTYPE7, 0x4000457f +.set CYDEV_PICU_STAT_BASE, 0x40004580 +.set CYDEV_PICU_STAT_SIZE, 0x00000010 +.set CYDEV_PICU_STAT_PICU0_BASE, 0x40004580 +.set CYDEV_PICU_STAT_PICU0_SIZE, 0x00000001 +.set CYREG_PICU0_INTSTAT, 0x40004580 +.set CYDEV_PICU_STAT_PICU1_BASE, 0x40004581 +.set CYDEV_PICU_STAT_PICU1_SIZE, 0x00000001 +.set CYREG_PICU1_INTSTAT, 0x40004581 +.set CYDEV_PICU_STAT_PICU2_BASE, 0x40004582 +.set CYDEV_PICU_STAT_PICU2_SIZE, 0x00000001 +.set CYREG_PICU2_INTSTAT, 0x40004582 +.set CYDEV_PICU_STAT_PICU3_BASE, 0x40004583 +.set CYDEV_PICU_STAT_PICU3_SIZE, 0x00000001 +.set CYREG_PICU3_INTSTAT, 0x40004583 +.set CYDEV_PICU_STAT_PICU4_BASE, 0x40004584 +.set CYDEV_PICU_STAT_PICU4_SIZE, 0x00000001 +.set CYREG_PICU4_INTSTAT, 0x40004584 +.set CYDEV_PICU_STAT_PICU5_BASE, 0x40004585 +.set CYDEV_PICU_STAT_PICU5_SIZE, 0x00000001 +.set CYREG_PICU5_INTSTAT, 0x40004585 +.set CYDEV_PICU_STAT_PICU6_BASE, 0x40004586 +.set CYDEV_PICU_STAT_PICU6_SIZE, 0x00000001 +.set CYREG_PICU6_INTSTAT, 0x40004586 +.set CYDEV_PICU_STAT_PICU12_BASE, 0x4000458c +.set CYDEV_PICU_STAT_PICU12_SIZE, 0x00000001 +.set CYREG_PICU12_INTSTAT, 0x4000458c +.set CYDEV_PICU_STAT_PICU15_BASE, 0x4000458f +.set CYDEV_PICU_STAT_PICU15_SIZE, 0x00000001 +.set CYREG_PICU15_INTSTAT, 0x4000458f +.set CYDEV_PICU_SNAP_BASE, 0x40004590 +.set CYDEV_PICU_SNAP_SIZE, 0x00000010 +.set CYDEV_PICU_SNAP_PICU0_BASE, 0x40004590 +.set CYDEV_PICU_SNAP_PICU0_SIZE, 0x00000001 +.set CYREG_PICU0_SNAP, 0x40004590 +.set CYDEV_PICU_SNAP_PICU1_BASE, 0x40004591 +.set CYDEV_PICU_SNAP_PICU1_SIZE, 0x00000001 +.set CYREG_PICU1_SNAP, 0x40004591 +.set CYDEV_PICU_SNAP_PICU2_BASE, 0x40004592 +.set CYDEV_PICU_SNAP_PICU2_SIZE, 0x00000001 +.set CYREG_PICU2_SNAP, 0x40004592 +.set CYDEV_PICU_SNAP_PICU3_BASE, 0x40004593 +.set CYDEV_PICU_SNAP_PICU3_SIZE, 0x00000001 +.set CYREG_PICU3_SNAP, 0x40004593 +.set CYDEV_PICU_SNAP_PICU4_BASE, 0x40004594 +.set CYDEV_PICU_SNAP_PICU4_SIZE, 0x00000001 +.set CYREG_PICU4_SNAP, 0x40004594 +.set CYDEV_PICU_SNAP_PICU5_BASE, 0x40004595 +.set CYDEV_PICU_SNAP_PICU5_SIZE, 0x00000001 +.set CYREG_PICU5_SNAP, 0x40004595 +.set CYDEV_PICU_SNAP_PICU6_BASE, 0x40004596 +.set CYDEV_PICU_SNAP_PICU6_SIZE, 0x00000001 +.set CYREG_PICU6_SNAP, 0x40004596 +.set CYDEV_PICU_SNAP_PICU12_BASE, 0x4000459c +.set CYDEV_PICU_SNAP_PICU12_SIZE, 0x00000001 +.set CYREG_PICU12_SNAP, 0x4000459c +.set CYDEV_PICU_SNAP_PICU_15_BASE, 0x4000459f +.set CYDEV_PICU_SNAP_PICU_15_SIZE, 0x00000001 +.set CYREG_PICU_15_SNAP_15, 0x4000459f +.set CYDEV_PICU_DISABLE_COR_BASE, 0x400045a0 +.set CYDEV_PICU_DISABLE_COR_SIZE, 0x00000010 +.set CYDEV_PICU_DISABLE_COR_PICU0_BASE, 0x400045a0 +.set CYDEV_PICU_DISABLE_COR_PICU0_SIZE, 0x00000001 +.set CYREG_PICU0_DISABLE_COR, 0x400045a0 +.set CYDEV_PICU_DISABLE_COR_PICU1_BASE, 0x400045a1 +.set CYDEV_PICU_DISABLE_COR_PICU1_SIZE, 0x00000001 +.set CYREG_PICU1_DISABLE_COR, 0x400045a1 +.set CYDEV_PICU_DISABLE_COR_PICU2_BASE, 0x400045a2 +.set CYDEV_PICU_DISABLE_COR_PICU2_SIZE, 0x00000001 +.set CYREG_PICU2_DISABLE_COR, 0x400045a2 +.set CYDEV_PICU_DISABLE_COR_PICU3_BASE, 0x400045a3 +.set CYDEV_PICU_DISABLE_COR_PICU3_SIZE, 0x00000001 +.set CYREG_PICU3_DISABLE_COR, 0x400045a3 +.set CYDEV_PICU_DISABLE_COR_PICU4_BASE, 0x400045a4 +.set CYDEV_PICU_DISABLE_COR_PICU4_SIZE, 0x00000001 +.set CYREG_PICU4_DISABLE_COR, 0x400045a4 +.set CYDEV_PICU_DISABLE_COR_PICU5_BASE, 0x400045a5 +.set CYDEV_PICU_DISABLE_COR_PICU5_SIZE, 0x00000001 +.set CYREG_PICU5_DISABLE_COR, 0x400045a5 +.set CYDEV_PICU_DISABLE_COR_PICU6_BASE, 0x400045a6 +.set CYDEV_PICU_DISABLE_COR_PICU6_SIZE, 0x00000001 +.set CYREG_PICU6_DISABLE_COR, 0x400045a6 +.set CYDEV_PICU_DISABLE_COR_PICU12_BASE, 0x400045ac +.set CYDEV_PICU_DISABLE_COR_PICU12_SIZE, 0x00000001 +.set CYREG_PICU12_DISABLE_COR, 0x400045ac +.set CYDEV_PICU_DISABLE_COR_PICU15_BASE, 0x400045af +.set CYDEV_PICU_DISABLE_COR_PICU15_SIZE, 0x00000001 +.set CYREG_PICU15_DISABLE_COR, 0x400045af +.set CYDEV_MFGCFG_BASE, 0x40004600 +.set CYDEV_MFGCFG_SIZE, 0x000000ed +.set CYDEV_MFGCFG_ANAIF_BASE, 0x40004600 +.set CYDEV_MFGCFG_ANAIF_SIZE, 0x00000038 +.set CYDEV_MFGCFG_ANAIF_DAC0_BASE, 0x40004608 +.set CYDEV_MFGCFG_ANAIF_DAC0_SIZE, 0x00000001 +.set CYREG_DAC0_TR, 0x40004608 +.set CYDEV_MFGCFG_ANAIF_DAC1_BASE, 0x40004609 +.set CYDEV_MFGCFG_ANAIF_DAC1_SIZE, 0x00000001 +.set CYREG_DAC1_TR, 0x40004609 +.set CYDEV_MFGCFG_ANAIF_DAC2_BASE, 0x4000460a +.set CYDEV_MFGCFG_ANAIF_DAC2_SIZE, 0x00000001 +.set CYREG_DAC2_TR, 0x4000460a +.set CYDEV_MFGCFG_ANAIF_DAC3_BASE, 0x4000460b +.set CYDEV_MFGCFG_ANAIF_DAC3_SIZE, 0x00000001 +.set CYREG_DAC3_TR, 0x4000460b +.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE, 0x40004610 +.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE, 0x00000001 +.set CYREG_NPUMP_DSM_TR0, 0x40004610 +.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE, 0x40004611 +.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE, 0x00000001 +.set CYREG_NPUMP_SC_TR0, 0x40004611 +.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE, 0x40004612 +.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE, 0x00000001 +.set CYREG_NPUMP_OPAMP_TR0, 0x40004612 +.set CYDEV_MFGCFG_ANAIF_SAR0_BASE, 0x40004614 +.set CYDEV_MFGCFG_ANAIF_SAR0_SIZE, 0x00000001 +.set CYREG_SAR0_TR0, 0x40004614 +.set CYDEV_MFGCFG_ANAIF_SAR1_BASE, 0x40004616 +.set CYDEV_MFGCFG_ANAIF_SAR1_SIZE, 0x00000001 +.set CYREG_SAR1_TR0, 0x40004616 +.set CYDEV_MFGCFG_ANAIF_OPAMP0_BASE, 0x40004620 +.set CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE, 0x00000002 +.set CYREG_OPAMP0_TR0, 0x40004620 +.set CYREG_OPAMP0_TR1, 0x40004621 +.set CYDEV_MFGCFG_ANAIF_OPAMP1_BASE, 0x40004622 +.set CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE, 0x00000002 +.set CYREG_OPAMP1_TR0, 0x40004622 +.set CYREG_OPAMP1_TR1, 0x40004623 +.set CYDEV_MFGCFG_ANAIF_OPAMP2_BASE, 0x40004624 +.set CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE, 0x00000002 +.set CYREG_OPAMP2_TR0, 0x40004624 +.set CYREG_OPAMP2_TR1, 0x40004625 +.set CYDEV_MFGCFG_ANAIF_OPAMP3_BASE, 0x40004626 +.set CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE, 0x00000002 +.set CYREG_OPAMP3_TR0, 0x40004626 +.set CYREG_OPAMP3_TR1, 0x40004627 +.set CYDEV_MFGCFG_ANAIF_CMP0_BASE, 0x40004630 +.set CYDEV_MFGCFG_ANAIF_CMP0_SIZE, 0x00000002 +.set CYREG_CMP0_TR0, 0x40004630 +.set CYREG_CMP0_TR1, 0x40004631 +.set CYDEV_MFGCFG_ANAIF_CMP1_BASE, 0x40004632 +.set CYDEV_MFGCFG_ANAIF_CMP1_SIZE, 0x00000002 +.set CYREG_CMP1_TR0, 0x40004632 +.set CYREG_CMP1_TR1, 0x40004633 +.set CYDEV_MFGCFG_ANAIF_CMP2_BASE, 0x40004634 +.set CYDEV_MFGCFG_ANAIF_CMP2_SIZE, 0x00000002 +.set CYREG_CMP2_TR0, 0x40004634 +.set CYREG_CMP2_TR1, 0x40004635 +.set CYDEV_MFGCFG_ANAIF_CMP3_BASE, 0x40004636 +.set CYDEV_MFGCFG_ANAIF_CMP3_SIZE, 0x00000002 +.set CYREG_CMP3_TR0, 0x40004636 +.set CYREG_CMP3_TR1, 0x40004637 +.set CYDEV_MFGCFG_PWRSYS_BASE, 0x40004680 +.set CYDEV_MFGCFG_PWRSYS_SIZE, 0x0000000b +.set CYREG_PWRSYS_HIB_TR0, 0x40004680 +.set CYREG_PWRSYS_HIB_TR1, 0x40004681 +.set CYREG_PWRSYS_I2C_TR, 0x40004682 +.set CYREG_PWRSYS_SLP_TR, 0x40004683 +.set CYREG_PWRSYS_BUZZ_TR, 0x40004684 +.set CYREG_PWRSYS_WAKE_TR0, 0x40004685 +.set CYREG_PWRSYS_WAKE_TR1, 0x40004686 +.set CYREG_PWRSYS_BREF_TR, 0x40004687 +.set CYREG_PWRSYS_BG_TR, 0x40004688 +.set CYREG_PWRSYS_WAKE_TR2, 0x40004689 +.set CYREG_PWRSYS_WAKE_TR3, 0x4000468a +.set CYDEV_MFGCFG_ILO_BASE, 0x40004690 +.set CYDEV_MFGCFG_ILO_SIZE, 0x00000002 +.set CYREG_ILO_TR0, 0x40004690 +.set CYREG_ILO_TR1, 0x40004691 +.set CYDEV_MFGCFG_X32_BASE, 0x40004698 +.set CYDEV_MFGCFG_X32_SIZE, 0x00000001 +.set CYREG_X32_TR, 0x40004698 +.set CYDEV_MFGCFG_IMO_BASE, 0x400046a0 +.set CYDEV_MFGCFG_IMO_SIZE, 0x00000005 +.set CYREG_IMO_TR0, 0x400046a0 +.set CYREG_IMO_TR1, 0x400046a1 +.set CYREG_IMO_GAIN, 0x400046a2 +.set CYREG_IMO_C36M, 0x400046a3 +.set CYREG_IMO_TR2, 0x400046a4 +.set CYDEV_MFGCFG_XMHZ_BASE, 0x400046a8 +.set CYDEV_MFGCFG_XMHZ_SIZE, 0x00000001 +.set CYREG_XMHZ_TR, 0x400046a8 +.set CYREG_MFGCFG_DLY, 0x400046c0 +.set CYDEV_MFGCFG_MLOGIC_BASE, 0x400046e0 +.set CYDEV_MFGCFG_MLOGIC_SIZE, 0x0000000d +.set CYREG_MLOGIC_DMPSTR, 0x400046e2 +.set CYDEV_MFGCFG_MLOGIC_SEG_BASE, 0x400046e4 +.set CYDEV_MFGCFG_MLOGIC_SEG_SIZE, 0x00000002 +.set CYREG_MLOGIC_SEG_CR, 0x400046e4 +.set CYREG_MLOGIC_SEG_CFG0, 0x400046e5 +.set CYREG_MLOGIC_DEBUG, 0x400046e8 +.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE, 0x400046ea +.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE, 0x00000001 +.set CYREG_MLOGIC_CPU_SCR_CPU_SCR, 0x400046ea +.set CYREG_MLOGIC_REV_ID, 0x400046ec +.set CYDEV_RESET_BASE, 0x400046f0 +.set CYDEV_RESET_SIZE, 0x0000000f +.set CYREG_RESET_IPOR_CR0, 0x400046f0 +.set CYREG_RESET_IPOR_CR1, 0x400046f1 +.set CYREG_RESET_IPOR_CR2, 0x400046f2 +.set CYREG_RESET_IPOR_CR3, 0x400046f3 +.set CYREG_RESET_CR0, 0x400046f4 +.set CYREG_RESET_CR1, 0x400046f5 +.set CYREG_RESET_CR2, 0x400046f6 +.set CYREG_RESET_CR3, 0x400046f7 +.set CYREG_RESET_CR4, 0x400046f8 +.set CYREG_RESET_CR5, 0x400046f9 +.set CYREG_RESET_SR0, 0x400046fa +.set CYREG_RESET_SR1, 0x400046fb +.set CYREG_RESET_SR2, 0x400046fc +.set CYREG_RESET_SR3, 0x400046fd +.set CYREG_RESET_TR, 0x400046fe +.set CYDEV_SPC_BASE, 0x40004700 +.set CYDEV_SPC_SIZE, 0x00000100 +.set CYREG_SPC_FM_EE_CR, 0x40004700 +.set CYREG_SPC_FM_EE_WAKE_CNT, 0x40004701 +.set CYREG_SPC_EE_SCR, 0x40004702 +.set CYREG_SPC_EE_ERR, 0x40004703 +.set CYREG_SPC_CPU_DATA, 0x40004720 +.set CYREG_SPC_DMA_DATA, 0x40004721 +.set CYREG_SPC_SR, 0x40004722 +.set CYREG_SPC_CR, 0x40004723 +.set CYDEV_SPC_DMM_MAP_BASE, 0x40004780 +.set CYDEV_SPC_DMM_MAP_SIZE, 0x00000080 +.set CYREG_SPC_DMM_MAP_SRAM_MBASE, 0x40004780 +.set CYREG_SPC_DMM_MAP_SRAM_MSIZE, 0x00000080 +.set CYDEV_CACHE_BASE, 0x40004800 +.set CYDEV_CACHE_SIZE, 0x0000009c +.set CYREG_CACHE_CC_CTL, 0x40004800 +.set CYREG_CACHE_ECC_CORR, 0x40004880 +.set CYREG_CACHE_ECC_ERR, 0x40004888 +.set CYREG_CACHE_FLASH_ERR, 0x40004890 +.set CYREG_CACHE_HITMISS, 0x40004898 +.set CYDEV_I2C_BASE, 0x40004900 +.set CYDEV_I2C_SIZE, 0x000000e1 +.set CYREG_I2C_XCFG, 0x400049c8 +.set CYREG_I2C_ADR, 0x400049ca +.set CYREG_I2C_CFG, 0x400049d6 +.set CYREG_I2C_CSR, 0x400049d7 +.set CYREG_I2C_D, 0x400049d8 +.set CYREG_I2C_MCSR, 0x400049d9 +.set CYREG_I2C_CLK_DIV1, 0x400049db +.set CYREG_I2C_CLK_DIV2, 0x400049dc +.set CYREG_I2C_TMOUT_CSR, 0x400049dd +.set CYREG_I2C_TMOUT_SR, 0x400049de +.set CYREG_I2C_TMOUT_CFG0, 0x400049df +.set CYREG_I2C_TMOUT_CFG1, 0x400049e0 +.set CYDEV_DEC_BASE, 0x40004e00 +.set CYDEV_DEC_SIZE, 0x00000015 +.set CYREG_DEC_CR, 0x40004e00 +.set CYREG_DEC_SR, 0x40004e01 +.set CYREG_DEC_SHIFT1, 0x40004e02 +.set CYREG_DEC_SHIFT2, 0x40004e03 +.set CYREG_DEC_DR2, 0x40004e04 +.set CYREG_DEC_DR2H, 0x40004e05 +.set CYREG_DEC_DR1, 0x40004e06 +.set CYREG_DEC_OCOR, 0x40004e08 +.set CYREG_DEC_OCORM, 0x40004e09 +.set CYREG_DEC_OCORH, 0x40004e0a +.set CYREG_DEC_GCOR, 0x40004e0c +.set CYREG_DEC_GCORH, 0x40004e0d +.set CYREG_DEC_GVAL, 0x40004e0e +.set CYREG_DEC_OUTSAMP, 0x40004e10 +.set CYREG_DEC_OUTSAMPM, 0x40004e11 +.set CYREG_DEC_OUTSAMPH, 0x40004e12 +.set CYREG_DEC_OUTSAMPS, 0x40004e13 +.set CYREG_DEC_COHER, 0x40004e14 +.set CYDEV_TMR0_BASE, 0x40004f00 +.set CYDEV_TMR0_SIZE, 0x0000000c +.set CYREG_TMR0_CFG0, 0x40004f00 +.set CYREG_TMR0_CFG1, 0x40004f01 +.set CYREG_TMR0_CFG2, 0x40004f02 +.set CYREG_TMR0_SR0, 0x40004f03 +.set CYREG_TMR0_PER0, 0x40004f04 +.set CYREG_TMR0_PER1, 0x40004f05 +.set CYREG_TMR0_CNT_CMP0, 0x40004f06 +.set CYREG_TMR0_CNT_CMP1, 0x40004f07 +.set CYREG_TMR0_CAP0, 0x40004f08 +.set CYREG_TMR0_CAP1, 0x40004f09 +.set CYREG_TMR0_RT0, 0x40004f0a +.set CYREG_TMR0_RT1, 0x40004f0b +.set CYDEV_TMR1_BASE, 0x40004f0c +.set CYDEV_TMR1_SIZE, 0x0000000c +.set CYREG_TMR1_CFG0, 0x40004f0c +.set CYREG_TMR1_CFG1, 0x40004f0d +.set CYREG_TMR1_CFG2, 0x40004f0e +.set CYREG_TMR1_SR0, 0x40004f0f +.set CYREG_TMR1_PER0, 0x40004f10 +.set CYREG_TMR1_PER1, 0x40004f11 +.set CYREG_TMR1_CNT_CMP0, 0x40004f12 +.set CYREG_TMR1_CNT_CMP1, 0x40004f13 +.set CYREG_TMR1_CAP0, 0x40004f14 +.set CYREG_TMR1_CAP1, 0x40004f15 +.set CYREG_TMR1_RT0, 0x40004f16 +.set CYREG_TMR1_RT1, 0x40004f17 +.set CYDEV_TMR2_BASE, 0x40004f18 +.set CYDEV_TMR2_SIZE, 0x0000000c +.set CYREG_TMR2_CFG0, 0x40004f18 +.set CYREG_TMR2_CFG1, 0x40004f19 +.set CYREG_TMR2_CFG2, 0x40004f1a +.set CYREG_TMR2_SR0, 0x40004f1b +.set CYREG_TMR2_PER0, 0x40004f1c +.set CYREG_TMR2_PER1, 0x40004f1d +.set CYREG_TMR2_CNT_CMP0, 0x40004f1e +.set CYREG_TMR2_CNT_CMP1, 0x40004f1f +.set CYREG_TMR2_CAP0, 0x40004f20 +.set CYREG_TMR2_CAP1, 0x40004f21 +.set CYREG_TMR2_RT0, 0x40004f22 +.set CYREG_TMR2_RT1, 0x40004f23 +.set CYDEV_TMR3_BASE, 0x40004f24 +.set CYDEV_TMR3_SIZE, 0x0000000c +.set CYREG_TMR3_CFG0, 0x40004f24 +.set CYREG_TMR3_CFG1, 0x40004f25 +.set CYREG_TMR3_CFG2, 0x40004f26 +.set CYREG_TMR3_SR0, 0x40004f27 +.set CYREG_TMR3_PER0, 0x40004f28 +.set CYREG_TMR3_PER1, 0x40004f29 +.set CYREG_TMR3_CNT_CMP0, 0x40004f2a +.set CYREG_TMR3_CNT_CMP1, 0x40004f2b +.set CYREG_TMR3_CAP0, 0x40004f2c +.set CYREG_TMR3_CAP1, 0x40004f2d +.set CYREG_TMR3_RT0, 0x40004f2e +.set CYREG_TMR3_RT1, 0x40004f2f +.set CYDEV_IO_BASE, 0x40005000 +.set CYDEV_IO_SIZE, 0x00000200 +.set CYDEV_IO_PC_BASE, 0x40005000 +.set CYDEV_IO_PC_SIZE, 0x00000080 +.set CYDEV_IO_PC_PRT0_BASE, 0x40005000 +.set CYDEV_IO_PC_PRT0_SIZE, 0x00000008 +.set CYREG_PRT0_PC0, 0x40005000 +.set CYREG_PRT0_PC1, 0x40005001 +.set CYREG_PRT0_PC2, 0x40005002 +.set CYREG_PRT0_PC3, 0x40005003 +.set CYREG_PRT0_PC4, 0x40005004 +.set CYREG_PRT0_PC5, 0x40005005 +.set CYREG_PRT0_PC6, 0x40005006 +.set CYREG_PRT0_PC7, 0x40005007 +.set CYDEV_IO_PC_PRT1_BASE, 0x40005008 +.set CYDEV_IO_PC_PRT1_SIZE, 0x00000008 +.set CYREG_PRT1_PC0, 0x40005008 +.set CYREG_PRT1_PC1, 0x40005009 +.set CYREG_PRT1_PC2, 0x4000500a +.set CYREG_PRT1_PC3, 0x4000500b +.set CYREG_PRT1_PC4, 0x4000500c +.set CYREG_PRT1_PC5, 0x4000500d +.set CYREG_PRT1_PC6, 0x4000500e +.set CYREG_PRT1_PC7, 0x4000500f +.set CYDEV_IO_PC_PRT2_BASE, 0x40005010 +.set CYDEV_IO_PC_PRT2_SIZE, 0x00000008 +.set CYREG_PRT2_PC0, 0x40005010 +.set CYREG_PRT2_PC1, 0x40005011 +.set CYREG_PRT2_PC2, 0x40005012 +.set CYREG_PRT2_PC3, 0x40005013 +.set CYREG_PRT2_PC4, 0x40005014 +.set CYREG_PRT2_PC5, 0x40005015 +.set CYREG_PRT2_PC6, 0x40005016 +.set CYREG_PRT2_PC7, 0x40005017 +.set CYDEV_IO_PC_PRT3_BASE, 0x40005018 +.set CYDEV_IO_PC_PRT3_SIZE, 0x00000008 +.set CYREG_PRT3_PC0, 0x40005018 +.set CYREG_PRT3_PC1, 0x40005019 +.set CYREG_PRT3_PC2, 0x4000501a +.set CYREG_PRT3_PC3, 0x4000501b +.set CYREG_PRT3_PC4, 0x4000501c +.set CYREG_PRT3_PC5, 0x4000501d +.set CYREG_PRT3_PC6, 0x4000501e +.set CYREG_PRT3_PC7, 0x4000501f +.set CYDEV_IO_PC_PRT4_BASE, 0x40005020 +.set CYDEV_IO_PC_PRT4_SIZE, 0x00000008 +.set CYREG_PRT4_PC0, 0x40005020 +.set CYREG_PRT4_PC1, 0x40005021 +.set CYREG_PRT4_PC2, 0x40005022 +.set CYREG_PRT4_PC3, 0x40005023 +.set CYREG_PRT4_PC4, 0x40005024 +.set CYREG_PRT4_PC5, 0x40005025 +.set CYREG_PRT4_PC6, 0x40005026 +.set CYREG_PRT4_PC7, 0x40005027 +.set CYDEV_IO_PC_PRT5_BASE, 0x40005028 +.set CYDEV_IO_PC_PRT5_SIZE, 0x00000008 +.set CYREG_PRT5_PC0, 0x40005028 +.set CYREG_PRT5_PC1, 0x40005029 +.set CYREG_PRT5_PC2, 0x4000502a +.set CYREG_PRT5_PC3, 0x4000502b +.set CYREG_PRT5_PC4, 0x4000502c +.set CYREG_PRT5_PC5, 0x4000502d +.set CYREG_PRT5_PC6, 0x4000502e +.set CYREG_PRT5_PC7, 0x4000502f +.set CYDEV_IO_PC_PRT6_BASE, 0x40005030 +.set CYDEV_IO_PC_PRT6_SIZE, 0x00000008 +.set CYREG_PRT6_PC0, 0x40005030 +.set CYREG_PRT6_PC1, 0x40005031 +.set CYREG_PRT6_PC2, 0x40005032 +.set CYREG_PRT6_PC3, 0x40005033 +.set CYREG_PRT6_PC4, 0x40005034 +.set CYREG_PRT6_PC5, 0x40005035 +.set CYREG_PRT6_PC6, 0x40005036 +.set CYREG_PRT6_PC7, 0x40005037 +.set CYDEV_IO_PC_PRT12_BASE, 0x40005060 +.set CYDEV_IO_PC_PRT12_SIZE, 0x00000008 +.set CYREG_PRT12_PC0, 0x40005060 +.set CYREG_PRT12_PC1, 0x40005061 +.set CYREG_PRT12_PC2, 0x40005062 +.set CYREG_PRT12_PC3, 0x40005063 +.set CYREG_PRT12_PC4, 0x40005064 +.set CYREG_PRT12_PC5, 0x40005065 +.set CYREG_PRT12_PC6, 0x40005066 +.set CYREG_PRT12_PC7, 0x40005067 +.set CYDEV_IO_PC_PRT15_BASE, 0x40005078 +.set CYDEV_IO_PC_PRT15_SIZE, 0x00000006 +.set CYREG_IO_PC_PRT15_PC0, 0x40005078 +.set CYREG_IO_PC_PRT15_PC1, 0x40005079 +.set CYREG_IO_PC_PRT15_PC2, 0x4000507a +.set CYREG_IO_PC_PRT15_PC3, 0x4000507b +.set CYREG_IO_PC_PRT15_PC4, 0x4000507c +.set CYREG_IO_PC_PRT15_PC5, 0x4000507d +.set CYDEV_IO_PC_PRT15_7_6_BASE, 0x4000507e +.set CYDEV_IO_PC_PRT15_7_6_SIZE, 0x00000002 +.set CYREG_IO_PC_PRT15_7_6_PC0, 0x4000507e +.set CYREG_IO_PC_PRT15_7_6_PC1, 0x4000507f +.set CYDEV_IO_DR_BASE, 0x40005080 +.set CYDEV_IO_DR_SIZE, 0x00000010 +.set CYDEV_IO_DR_PRT0_BASE, 0x40005080 +.set CYDEV_IO_DR_PRT0_SIZE, 0x00000001 +.set CYREG_PRT0_DR_ALIAS, 0x40005080 +.set CYDEV_IO_DR_PRT1_BASE, 0x40005081 +.set CYDEV_IO_DR_PRT1_SIZE, 0x00000001 +.set CYREG_PRT1_DR_ALIAS, 0x40005081 +.set CYDEV_IO_DR_PRT2_BASE, 0x40005082 +.set CYDEV_IO_DR_PRT2_SIZE, 0x00000001 +.set CYREG_PRT2_DR_ALIAS, 0x40005082 +.set CYDEV_IO_DR_PRT3_BASE, 0x40005083 +.set CYDEV_IO_DR_PRT3_SIZE, 0x00000001 +.set CYREG_PRT3_DR_ALIAS, 0x40005083 +.set CYDEV_IO_DR_PRT4_BASE, 0x40005084 +.set CYDEV_IO_DR_PRT4_SIZE, 0x00000001 +.set CYREG_PRT4_DR_ALIAS, 0x40005084 +.set CYDEV_IO_DR_PRT5_BASE, 0x40005085 +.set CYDEV_IO_DR_PRT5_SIZE, 0x00000001 +.set CYREG_PRT5_DR_ALIAS, 0x40005085 +.set CYDEV_IO_DR_PRT6_BASE, 0x40005086 +.set CYDEV_IO_DR_PRT6_SIZE, 0x00000001 +.set CYREG_PRT6_DR_ALIAS, 0x40005086 +.set CYDEV_IO_DR_PRT12_BASE, 0x4000508c +.set CYDEV_IO_DR_PRT12_SIZE, 0x00000001 +.set CYREG_PRT12_DR_ALIAS, 0x4000508c +.set CYDEV_IO_DR_PRT15_BASE, 0x4000508f +.set CYDEV_IO_DR_PRT15_SIZE, 0x00000001 +.set CYREG_PRT15_DR_15_ALIAS, 0x4000508f +.set CYDEV_IO_PS_BASE, 0x40005090 +.set CYDEV_IO_PS_SIZE, 0x00000010 +.set CYDEV_IO_PS_PRT0_BASE, 0x40005090 +.set CYDEV_IO_PS_PRT0_SIZE, 0x00000001 +.set CYREG_PRT0_PS_ALIAS, 0x40005090 +.set CYDEV_IO_PS_PRT1_BASE, 0x40005091 +.set CYDEV_IO_PS_PRT1_SIZE, 0x00000001 +.set CYREG_PRT1_PS_ALIAS, 0x40005091 +.set CYDEV_IO_PS_PRT2_BASE, 0x40005092 +.set CYDEV_IO_PS_PRT2_SIZE, 0x00000001 +.set CYREG_PRT2_PS_ALIAS, 0x40005092 +.set CYDEV_IO_PS_PRT3_BASE, 0x40005093 +.set CYDEV_IO_PS_PRT3_SIZE, 0x00000001 +.set CYREG_PRT3_PS_ALIAS, 0x40005093 +.set CYDEV_IO_PS_PRT4_BASE, 0x40005094 +.set CYDEV_IO_PS_PRT4_SIZE, 0x00000001 +.set CYREG_PRT4_PS_ALIAS, 0x40005094 +.set CYDEV_IO_PS_PRT5_BASE, 0x40005095 +.set CYDEV_IO_PS_PRT5_SIZE, 0x00000001 +.set CYREG_PRT5_PS_ALIAS, 0x40005095 +.set CYDEV_IO_PS_PRT6_BASE, 0x40005096 +.set CYDEV_IO_PS_PRT6_SIZE, 0x00000001 +.set CYREG_PRT6_PS_ALIAS, 0x40005096 +.set CYDEV_IO_PS_PRT12_BASE, 0x4000509c +.set CYDEV_IO_PS_PRT12_SIZE, 0x00000001 +.set CYREG_PRT12_PS_ALIAS, 0x4000509c +.set CYDEV_IO_PS_PRT15_BASE, 0x4000509f +.set CYDEV_IO_PS_PRT15_SIZE, 0x00000001 +.set CYREG_PRT15_PS15_ALIAS, 0x4000509f +.set CYDEV_IO_PRT_BASE, 0x40005100 +.set CYDEV_IO_PRT_SIZE, 0x00000100 +.set CYDEV_IO_PRT_PRT0_BASE, 0x40005100 +.set CYDEV_IO_PRT_PRT0_SIZE, 0x00000010 +.set CYREG_PRT0_DR, 0x40005100 +.set CYREG_PRT0_PS, 0x40005101 +.set CYREG_PRT0_DM0, 0x40005102 +.set CYREG_PRT0_DM1, 0x40005103 +.set CYREG_PRT0_DM2, 0x40005104 +.set CYREG_PRT0_SLW, 0x40005105 +.set CYREG_PRT0_BYP, 0x40005106 +.set CYREG_PRT0_BIE, 0x40005107 +.set CYREG_PRT0_INP_DIS, 0x40005108 +.set CYREG_PRT0_CTL, 0x40005109 +.set CYREG_PRT0_PRT, 0x4000510a +.set CYREG_PRT0_BIT_MASK, 0x4000510b +.set CYREG_PRT0_AMUX, 0x4000510c +.set CYREG_PRT0_AG, 0x4000510d +.set CYREG_PRT0_LCD_COM_SEG, 0x4000510e +.set CYREG_PRT0_LCD_EN, 0x4000510f +.set CYDEV_IO_PRT_PRT1_BASE, 0x40005110 +.set CYDEV_IO_PRT_PRT1_SIZE, 0x00000010 +.set CYREG_PRT1_DR, 0x40005110 +.set CYREG_PRT1_PS, 0x40005111 +.set CYREG_PRT1_DM0, 0x40005112 +.set CYREG_PRT1_DM1, 0x40005113 +.set CYREG_PRT1_DM2, 0x40005114 +.set CYREG_PRT1_SLW, 0x40005115 +.set CYREG_PRT1_BYP, 0x40005116 +.set CYREG_PRT1_BIE, 0x40005117 +.set CYREG_PRT1_INP_DIS, 0x40005118 +.set CYREG_PRT1_CTL, 0x40005119 +.set CYREG_PRT1_PRT, 0x4000511a +.set CYREG_PRT1_BIT_MASK, 0x4000511b +.set CYREG_PRT1_AMUX, 0x4000511c +.set CYREG_PRT1_AG, 0x4000511d +.set CYREG_PRT1_LCD_COM_SEG, 0x4000511e +.set CYREG_PRT1_LCD_EN, 0x4000511f +.set CYDEV_IO_PRT_PRT2_BASE, 0x40005120 +.set CYDEV_IO_PRT_PRT2_SIZE, 0x00000010 +.set CYREG_PRT2_DR, 0x40005120 +.set CYREG_PRT2_PS, 0x40005121 +.set CYREG_PRT2_DM0, 0x40005122 +.set CYREG_PRT2_DM1, 0x40005123 +.set CYREG_PRT2_DM2, 0x40005124 +.set CYREG_PRT2_SLW, 0x40005125 +.set CYREG_PRT2_BYP, 0x40005126 +.set CYREG_PRT2_BIE, 0x40005127 +.set CYREG_PRT2_INP_DIS, 0x40005128 +.set CYREG_PRT2_CTL, 0x40005129 +.set CYREG_PRT2_PRT, 0x4000512a +.set CYREG_PRT2_BIT_MASK, 0x4000512b +.set CYREG_PRT2_AMUX, 0x4000512c +.set CYREG_PRT2_AG, 0x4000512d +.set CYREG_PRT2_LCD_COM_SEG, 0x4000512e +.set CYREG_PRT2_LCD_EN, 0x4000512f +.set CYDEV_IO_PRT_PRT3_BASE, 0x40005130 +.set CYDEV_IO_PRT_PRT3_SIZE, 0x00000010 +.set CYREG_PRT3_DR, 0x40005130 +.set CYREG_PRT3_PS, 0x40005131 +.set CYREG_PRT3_DM0, 0x40005132 +.set CYREG_PRT3_DM1, 0x40005133 +.set CYREG_PRT3_DM2, 0x40005134 +.set CYREG_PRT3_SLW, 0x40005135 +.set CYREG_PRT3_BYP, 0x40005136 +.set CYREG_PRT3_BIE, 0x40005137 +.set CYREG_PRT3_INP_DIS, 0x40005138 +.set CYREG_PRT3_CTL, 0x40005139 +.set CYREG_PRT3_PRT, 0x4000513a +.set CYREG_PRT3_BIT_MASK, 0x4000513b +.set CYREG_PRT3_AMUX, 0x4000513c +.set CYREG_PRT3_AG, 0x4000513d +.set CYREG_PRT3_LCD_COM_SEG, 0x4000513e +.set CYREG_PRT3_LCD_EN, 0x4000513f +.set CYDEV_IO_PRT_PRT4_BASE, 0x40005140 +.set CYDEV_IO_PRT_PRT4_SIZE, 0x00000010 +.set CYREG_PRT4_DR, 0x40005140 +.set CYREG_PRT4_PS, 0x40005141 +.set CYREG_PRT4_DM0, 0x40005142 +.set CYREG_PRT4_DM1, 0x40005143 +.set CYREG_PRT4_DM2, 0x40005144 +.set CYREG_PRT4_SLW, 0x40005145 +.set CYREG_PRT4_BYP, 0x40005146 +.set CYREG_PRT4_BIE, 0x40005147 +.set CYREG_PRT4_INP_DIS, 0x40005148 +.set CYREG_PRT4_CTL, 0x40005149 +.set CYREG_PRT4_PRT, 0x4000514a +.set CYREG_PRT4_BIT_MASK, 0x4000514b +.set CYREG_PRT4_AMUX, 0x4000514c +.set CYREG_PRT4_AG, 0x4000514d +.set CYREG_PRT4_LCD_COM_SEG, 0x4000514e +.set CYREG_PRT4_LCD_EN, 0x4000514f +.set CYDEV_IO_PRT_PRT5_BASE, 0x40005150 +.set CYDEV_IO_PRT_PRT5_SIZE, 0x00000010 +.set CYREG_PRT5_DR, 0x40005150 +.set CYREG_PRT5_PS, 0x40005151 +.set CYREG_PRT5_DM0, 0x40005152 +.set CYREG_PRT5_DM1, 0x40005153 +.set CYREG_PRT5_DM2, 0x40005154 +.set CYREG_PRT5_SLW, 0x40005155 +.set CYREG_PRT5_BYP, 0x40005156 +.set CYREG_PRT5_BIE, 0x40005157 +.set CYREG_PRT5_INP_DIS, 0x40005158 +.set CYREG_PRT5_CTL, 0x40005159 +.set CYREG_PRT5_PRT, 0x4000515a +.set CYREG_PRT5_BIT_MASK, 0x4000515b +.set CYREG_PRT5_AMUX, 0x4000515c +.set CYREG_PRT5_AG, 0x4000515d +.set CYREG_PRT5_LCD_COM_SEG, 0x4000515e +.set CYREG_PRT5_LCD_EN, 0x4000515f +.set CYDEV_IO_PRT_PRT6_BASE, 0x40005160 +.set CYDEV_IO_PRT_PRT6_SIZE, 0x00000010 +.set CYREG_PRT6_DR, 0x40005160 +.set CYREG_PRT6_PS, 0x40005161 +.set CYREG_PRT6_DM0, 0x40005162 +.set CYREG_PRT6_DM1, 0x40005163 +.set CYREG_PRT6_DM2, 0x40005164 +.set CYREG_PRT6_SLW, 0x40005165 +.set CYREG_PRT6_BYP, 0x40005166 +.set CYREG_PRT6_BIE, 0x40005167 +.set CYREG_PRT6_INP_DIS, 0x40005168 +.set CYREG_PRT6_CTL, 0x40005169 +.set CYREG_PRT6_PRT, 0x4000516a +.set CYREG_PRT6_BIT_MASK, 0x4000516b +.set CYREG_PRT6_AMUX, 0x4000516c +.set CYREG_PRT6_AG, 0x4000516d +.set CYREG_PRT6_LCD_COM_SEG, 0x4000516e +.set CYREG_PRT6_LCD_EN, 0x4000516f +.set CYDEV_IO_PRT_PRT12_BASE, 0x400051c0 +.set CYDEV_IO_PRT_PRT12_SIZE, 0x00000010 +.set CYREG_PRT12_DR, 0x400051c0 +.set CYREG_PRT12_PS, 0x400051c1 +.set CYREG_PRT12_DM0, 0x400051c2 +.set CYREG_PRT12_DM1, 0x400051c3 +.set CYREG_PRT12_DM2, 0x400051c4 +.set CYREG_PRT12_SLW, 0x400051c5 +.set CYREG_PRT12_BYP, 0x400051c6 +.set CYREG_PRT12_BIE, 0x400051c7 +.set CYREG_PRT12_INP_DIS, 0x400051c8 +.set CYREG_PRT12_SIO_HYST_EN, 0x400051c9 +.set CYREG_PRT12_PRT, 0x400051ca +.set CYREG_PRT12_BIT_MASK, 0x400051cb +.set CYREG_PRT12_SIO_REG_HIFREQ, 0x400051cc +.set CYREG_PRT12_AG, 0x400051cd +.set CYREG_PRT12_SIO_CFG, 0x400051ce +.set CYREG_PRT12_SIO_DIFF, 0x400051cf +.set CYDEV_IO_PRT_PRT15_BASE, 0x400051f0 +.set CYDEV_IO_PRT_PRT15_SIZE, 0x00000010 +.set CYREG_PRT15_DR, 0x400051f0 +.set CYREG_PRT15_PS, 0x400051f1 +.set CYREG_PRT15_DM0, 0x400051f2 +.set CYREG_PRT15_DM1, 0x400051f3 +.set CYREG_PRT15_DM2, 0x400051f4 +.set CYREG_PRT15_SLW, 0x400051f5 +.set CYREG_PRT15_BYP, 0x400051f6 +.set CYREG_PRT15_BIE, 0x400051f7 +.set CYREG_PRT15_INP_DIS, 0x400051f8 +.set CYREG_PRT15_CTL, 0x400051f9 +.set CYREG_PRT15_PRT, 0x400051fa +.set CYREG_PRT15_BIT_MASK, 0x400051fb +.set CYREG_PRT15_AMUX, 0x400051fc +.set CYREG_PRT15_AG, 0x400051fd +.set CYREG_PRT15_LCD_COM_SEG, 0x400051fe +.set CYREG_PRT15_LCD_EN, 0x400051ff +.set CYDEV_PRTDSI_BASE, 0x40005200 +.set CYDEV_PRTDSI_SIZE, 0x0000007f +.set CYDEV_PRTDSI_PRT0_BASE, 0x40005200 +.set CYDEV_PRTDSI_PRT0_SIZE, 0x00000007 +.set CYREG_PRT0_OUT_SEL0, 0x40005200 +.set CYREG_PRT0_OUT_SEL1, 0x40005201 +.set CYREG_PRT0_OE_SEL0, 0x40005202 +.set CYREG_PRT0_OE_SEL1, 0x40005203 +.set CYREG_PRT0_DBL_SYNC_IN, 0x40005204 +.set CYREG_PRT0_SYNC_OUT, 0x40005205 +.set CYREG_PRT0_CAPS_SEL, 0x40005206 +.set CYDEV_PRTDSI_PRT1_BASE, 0x40005208 +.set CYDEV_PRTDSI_PRT1_SIZE, 0x00000007 +.set CYREG_PRT1_OUT_SEL0, 0x40005208 +.set CYREG_PRT1_OUT_SEL1, 0x40005209 +.set CYREG_PRT1_OE_SEL0, 0x4000520a +.set CYREG_PRT1_OE_SEL1, 0x4000520b +.set CYREG_PRT1_DBL_SYNC_IN, 0x4000520c +.set CYREG_PRT1_SYNC_OUT, 0x4000520d +.set CYREG_PRT1_CAPS_SEL, 0x4000520e +.set CYDEV_PRTDSI_PRT2_BASE, 0x40005210 +.set CYDEV_PRTDSI_PRT2_SIZE, 0x00000007 +.set CYREG_PRT2_OUT_SEL0, 0x40005210 +.set CYREG_PRT2_OUT_SEL1, 0x40005211 +.set CYREG_PRT2_OE_SEL0, 0x40005212 +.set CYREG_PRT2_OE_SEL1, 0x40005213 +.set CYREG_PRT2_DBL_SYNC_IN, 0x40005214 +.set CYREG_PRT2_SYNC_OUT, 0x40005215 +.set CYREG_PRT2_CAPS_SEL, 0x40005216 +.set CYDEV_PRTDSI_PRT3_BASE, 0x40005218 +.set CYDEV_PRTDSI_PRT3_SIZE, 0x00000007 +.set CYREG_PRT3_OUT_SEL0, 0x40005218 +.set CYREG_PRT3_OUT_SEL1, 0x40005219 +.set CYREG_PRT3_OE_SEL0, 0x4000521a +.set CYREG_PRT3_OE_SEL1, 0x4000521b +.set CYREG_PRT3_DBL_SYNC_IN, 0x4000521c +.set CYREG_PRT3_SYNC_OUT, 0x4000521d +.set CYREG_PRT3_CAPS_SEL, 0x4000521e +.set CYDEV_PRTDSI_PRT4_BASE, 0x40005220 +.set CYDEV_PRTDSI_PRT4_SIZE, 0x00000007 +.set CYREG_PRT4_OUT_SEL0, 0x40005220 +.set CYREG_PRT4_OUT_SEL1, 0x40005221 +.set CYREG_PRT4_OE_SEL0, 0x40005222 +.set CYREG_PRT4_OE_SEL1, 0x40005223 +.set CYREG_PRT4_DBL_SYNC_IN, 0x40005224 +.set CYREG_PRT4_SYNC_OUT, 0x40005225 +.set CYREG_PRT4_CAPS_SEL, 0x40005226 +.set CYDEV_PRTDSI_PRT5_BASE, 0x40005228 +.set CYDEV_PRTDSI_PRT5_SIZE, 0x00000007 +.set CYREG_PRT5_OUT_SEL0, 0x40005228 +.set CYREG_PRT5_OUT_SEL1, 0x40005229 +.set CYREG_PRT5_OE_SEL0, 0x4000522a +.set CYREG_PRT5_OE_SEL1, 0x4000522b +.set CYREG_PRT5_DBL_SYNC_IN, 0x4000522c +.set CYREG_PRT5_SYNC_OUT, 0x4000522d +.set CYREG_PRT5_CAPS_SEL, 0x4000522e +.set CYDEV_PRTDSI_PRT6_BASE, 0x40005230 +.set CYDEV_PRTDSI_PRT6_SIZE, 0x00000007 +.set CYREG_PRT6_OUT_SEL0, 0x40005230 +.set CYREG_PRT6_OUT_SEL1, 0x40005231 +.set CYREG_PRT6_OE_SEL0, 0x40005232 +.set CYREG_PRT6_OE_SEL1, 0x40005233 +.set CYREG_PRT6_DBL_SYNC_IN, 0x40005234 +.set CYREG_PRT6_SYNC_OUT, 0x40005235 +.set CYREG_PRT6_CAPS_SEL, 0x40005236 +.set CYDEV_PRTDSI_PRT12_BASE, 0x40005260 +.set CYDEV_PRTDSI_PRT12_SIZE, 0x00000006 +.set CYREG_PRT12_OUT_SEL0, 0x40005260 +.set CYREG_PRT12_OUT_SEL1, 0x40005261 +.set CYREG_PRT12_OE_SEL0, 0x40005262 +.set CYREG_PRT12_OE_SEL1, 0x40005263 +.set CYREG_PRT12_DBL_SYNC_IN, 0x40005264 +.set CYREG_PRT12_SYNC_OUT, 0x40005265 +.set CYDEV_PRTDSI_PRT15_BASE, 0x40005278 +.set CYDEV_PRTDSI_PRT15_SIZE, 0x00000007 +.set CYREG_PRT15_OUT_SEL0, 0x40005278 +.set CYREG_PRT15_OUT_SEL1, 0x40005279 +.set CYREG_PRT15_OE_SEL0, 0x4000527a +.set CYREG_PRT15_OE_SEL1, 0x4000527b +.set CYREG_PRT15_DBL_SYNC_IN, 0x4000527c +.set CYREG_PRT15_SYNC_OUT, 0x4000527d +.set CYREG_PRT15_CAPS_SEL, 0x4000527e +.set CYDEV_EMIF_BASE, 0x40005400 +.set CYDEV_EMIF_SIZE, 0x00000007 +.set CYREG_EMIF_NO_UDB, 0x40005400 +.set CYREG_EMIF_RP_WAIT_STATES, 0x40005401 +.set CYREG_EMIF_MEM_DWN, 0x40005402 +.set CYREG_EMIF_MEMCLK_DIV, 0x40005403 +.set CYREG_EMIF_CLOCK_EN, 0x40005404 +.set CYREG_EMIF_EM_TYPE, 0x40005405 +.set CYREG_EMIF_WP_WAIT_STATES, 0x40005406 +.set CYDEV_ANAIF_BASE, 0x40005800 +.set CYDEV_ANAIF_SIZE, 0x000003a9 +.set CYDEV_ANAIF_CFG_BASE, 0x40005800 +.set CYDEV_ANAIF_CFG_SIZE, 0x0000010f +.set CYDEV_ANAIF_CFG_SC0_BASE, 0x40005800 +.set CYDEV_ANAIF_CFG_SC0_SIZE, 0x00000003 +.set CYREG_SC0_CR0, 0x40005800 +.set CYREG_SC0_CR1, 0x40005801 +.set CYREG_SC0_CR2, 0x40005802 +.set CYDEV_ANAIF_CFG_SC1_BASE, 0x40005804 +.set CYDEV_ANAIF_CFG_SC1_SIZE, 0x00000003 +.set CYREG_SC1_CR0, 0x40005804 +.set CYREG_SC1_CR1, 0x40005805 +.set CYREG_SC1_CR2, 0x40005806 +.set CYDEV_ANAIF_CFG_SC2_BASE, 0x40005808 +.set CYDEV_ANAIF_CFG_SC2_SIZE, 0x00000003 +.set CYREG_SC2_CR0, 0x40005808 +.set CYREG_SC2_CR1, 0x40005809 +.set CYREG_SC2_CR2, 0x4000580a +.set CYDEV_ANAIF_CFG_SC3_BASE, 0x4000580c +.set CYDEV_ANAIF_CFG_SC3_SIZE, 0x00000003 +.set CYREG_SC3_CR0, 0x4000580c +.set CYREG_SC3_CR1, 0x4000580d +.set CYREG_SC3_CR2, 0x4000580e +.set CYDEV_ANAIF_CFG_DAC0_BASE, 0x40005820 +.set CYDEV_ANAIF_CFG_DAC0_SIZE, 0x00000003 +.set CYREG_DAC0_CR0, 0x40005820 +.set CYREG_DAC0_CR1, 0x40005821 +.set CYREG_DAC0_TST, 0x40005822 +.set CYDEV_ANAIF_CFG_DAC1_BASE, 0x40005824 +.set CYDEV_ANAIF_CFG_DAC1_SIZE, 0x00000003 +.set CYREG_DAC1_CR0, 0x40005824 +.set CYREG_DAC1_CR1, 0x40005825 +.set CYREG_DAC1_TST, 0x40005826 +.set CYDEV_ANAIF_CFG_DAC2_BASE, 0x40005828 +.set CYDEV_ANAIF_CFG_DAC2_SIZE, 0x00000003 +.set CYREG_DAC2_CR0, 0x40005828 +.set CYREG_DAC2_CR1, 0x40005829 +.set CYREG_DAC2_TST, 0x4000582a +.set CYDEV_ANAIF_CFG_DAC3_BASE, 0x4000582c +.set CYDEV_ANAIF_CFG_DAC3_SIZE, 0x00000003 +.set CYREG_DAC3_CR0, 0x4000582c +.set CYREG_DAC3_CR1, 0x4000582d +.set CYREG_DAC3_TST, 0x4000582e +.set CYDEV_ANAIF_CFG_CMP0_BASE, 0x40005840 +.set CYDEV_ANAIF_CFG_CMP0_SIZE, 0x00000001 +.set CYREG_CMP0_CR, 0x40005840 +.set CYDEV_ANAIF_CFG_CMP1_BASE, 0x40005841 +.set CYDEV_ANAIF_CFG_CMP1_SIZE, 0x00000001 +.set CYREG_CMP1_CR, 0x40005841 +.set CYDEV_ANAIF_CFG_CMP2_BASE, 0x40005842 +.set CYDEV_ANAIF_CFG_CMP2_SIZE, 0x00000001 +.set CYREG_CMP2_CR, 0x40005842 +.set CYDEV_ANAIF_CFG_CMP3_BASE, 0x40005843 +.set CYDEV_ANAIF_CFG_CMP3_SIZE, 0x00000001 +.set CYREG_CMP3_CR, 0x40005843 +.set CYDEV_ANAIF_CFG_LUT0_BASE, 0x40005848 +.set CYDEV_ANAIF_CFG_LUT0_SIZE, 0x00000002 +.set CYREG_LUT0_CR, 0x40005848 +.set CYREG_LUT0_MX, 0x40005849 +.set CYDEV_ANAIF_CFG_LUT1_BASE, 0x4000584a +.set CYDEV_ANAIF_CFG_LUT1_SIZE, 0x00000002 +.set CYREG_LUT1_CR, 0x4000584a +.set CYREG_LUT1_MX, 0x4000584b +.set CYDEV_ANAIF_CFG_LUT2_BASE, 0x4000584c +.set CYDEV_ANAIF_CFG_LUT2_SIZE, 0x00000002 +.set CYREG_LUT2_CR, 0x4000584c +.set CYREG_LUT2_MX, 0x4000584d +.set CYDEV_ANAIF_CFG_LUT3_BASE, 0x4000584e +.set CYDEV_ANAIF_CFG_LUT3_SIZE, 0x00000002 +.set CYREG_LUT3_CR, 0x4000584e +.set CYREG_LUT3_MX, 0x4000584f +.set CYDEV_ANAIF_CFG_OPAMP0_BASE, 0x40005858 +.set CYDEV_ANAIF_CFG_OPAMP0_SIZE, 0x00000002 +.set CYREG_OPAMP0_CR, 0x40005858 +.set CYREG_OPAMP0_RSVD, 0x40005859 +.set CYDEV_ANAIF_CFG_OPAMP1_BASE, 0x4000585a +.set CYDEV_ANAIF_CFG_OPAMP1_SIZE, 0x00000002 +.set CYREG_OPAMP1_CR, 0x4000585a +.set CYREG_OPAMP1_RSVD, 0x4000585b +.set CYDEV_ANAIF_CFG_OPAMP2_BASE, 0x4000585c +.set CYDEV_ANAIF_CFG_OPAMP2_SIZE, 0x00000002 +.set CYREG_OPAMP2_CR, 0x4000585c +.set CYREG_OPAMP2_RSVD, 0x4000585d +.set CYDEV_ANAIF_CFG_OPAMP3_BASE, 0x4000585e +.set CYDEV_ANAIF_CFG_OPAMP3_SIZE, 0x00000002 +.set CYREG_OPAMP3_CR, 0x4000585e +.set CYREG_OPAMP3_RSVD, 0x4000585f +.set CYDEV_ANAIF_CFG_LCDDAC_BASE, 0x40005868 +.set CYDEV_ANAIF_CFG_LCDDAC_SIZE, 0x00000002 +.set CYREG_LCDDAC_CR0, 0x40005868 +.set CYREG_LCDDAC_CR1, 0x40005869 +.set CYDEV_ANAIF_CFG_LCDDRV_BASE, 0x4000586a +.set CYDEV_ANAIF_CFG_LCDDRV_SIZE, 0x00000001 +.set CYREG_LCDDRV_CR, 0x4000586a +.set CYDEV_ANAIF_CFG_LCDTMR_BASE, 0x4000586b +.set CYDEV_ANAIF_CFG_LCDTMR_SIZE, 0x00000001 +.set CYREG_LCDTMR_CFG, 0x4000586b +.set CYDEV_ANAIF_CFG_BG_BASE, 0x4000586c +.set CYDEV_ANAIF_CFG_BG_SIZE, 0x00000004 +.set CYREG_BG_CR0, 0x4000586c +.set CYREG_BG_RSVD, 0x4000586d +.set CYREG_BG_DFT0, 0x4000586e +.set CYREG_BG_DFT1, 0x4000586f +.set CYDEV_ANAIF_CFG_CAPSL_BASE, 0x40005870 +.set CYDEV_ANAIF_CFG_CAPSL_SIZE, 0x00000002 +.set CYREG_CAPSL_CFG0, 0x40005870 +.set CYREG_CAPSL_CFG1, 0x40005871 +.set CYDEV_ANAIF_CFG_CAPSR_BASE, 0x40005872 +.set CYDEV_ANAIF_CFG_CAPSR_SIZE, 0x00000002 +.set CYREG_CAPSR_CFG0, 0x40005872 +.set CYREG_CAPSR_CFG1, 0x40005873 +.set CYDEV_ANAIF_CFG_PUMP_BASE, 0x40005876 +.set CYDEV_ANAIF_CFG_PUMP_SIZE, 0x00000002 +.set CYREG_PUMP_CR0, 0x40005876 +.set CYREG_PUMP_CR1, 0x40005877 +.set CYDEV_ANAIF_CFG_LPF0_BASE, 0x40005878 +.set CYDEV_ANAIF_CFG_LPF0_SIZE, 0x00000002 +.set CYREG_LPF0_CR0, 0x40005878 +.set CYREG_LPF0_RSVD, 0x40005879 +.set CYDEV_ANAIF_CFG_LPF1_BASE, 0x4000587a +.set CYDEV_ANAIF_CFG_LPF1_SIZE, 0x00000002 +.set CYREG_LPF1_CR0, 0x4000587a +.set CYREG_LPF1_RSVD, 0x4000587b +.set CYDEV_ANAIF_CFG_MISC_BASE, 0x4000587c +.set CYDEV_ANAIF_CFG_MISC_SIZE, 0x00000001 +.set CYREG_ANAIF_CFG_MISC_CR0, 0x4000587c +.set CYDEV_ANAIF_CFG_DSM0_BASE, 0x40005880 +.set CYDEV_ANAIF_CFG_DSM0_SIZE, 0x00000020 +.set CYREG_DSM0_CR0, 0x40005880 +.set CYREG_DSM0_CR1, 0x40005881 +.set CYREG_DSM0_CR2, 0x40005882 +.set CYREG_DSM0_CR3, 0x40005883 +.set CYREG_DSM0_CR4, 0x40005884 +.set CYREG_DSM0_CR5, 0x40005885 +.set CYREG_DSM0_CR6, 0x40005886 +.set CYREG_DSM0_CR7, 0x40005887 +.set CYREG_DSM0_CR8, 0x40005888 +.set CYREG_DSM0_CR9, 0x40005889 +.set CYREG_DSM0_CR10, 0x4000588a +.set CYREG_DSM0_CR11, 0x4000588b +.set CYREG_DSM0_CR12, 0x4000588c +.set CYREG_DSM0_CR13, 0x4000588d +.set CYREG_DSM0_CR14, 0x4000588e +.set CYREG_DSM0_CR15, 0x4000588f +.set CYREG_DSM0_CR16, 0x40005890 +.set CYREG_DSM0_CR17, 0x40005891 +.set CYREG_DSM0_REF0, 0x40005892 +.set CYREG_DSM0_REF1, 0x40005893 +.set CYREG_DSM0_REF2, 0x40005894 +.set CYREG_DSM0_REF3, 0x40005895 +.set CYREG_DSM0_DEM0, 0x40005896 +.set CYREG_DSM0_DEM1, 0x40005897 +.set CYREG_DSM0_TST0, 0x40005898 +.set CYREG_DSM0_TST1, 0x40005899 +.set CYREG_DSM0_BUF0, 0x4000589a +.set CYREG_DSM0_BUF1, 0x4000589b +.set CYREG_DSM0_BUF2, 0x4000589c +.set CYREG_DSM0_BUF3, 0x4000589d +.set CYREG_DSM0_MISC, 0x4000589e +.set CYREG_DSM0_RSVD1, 0x4000589f +.set CYDEV_ANAIF_CFG_SAR0_BASE, 0x40005900 +.set CYDEV_ANAIF_CFG_SAR0_SIZE, 0x00000007 +.set CYREG_SAR0_CSR0, 0x40005900 +.set CYREG_SAR0_CSR1, 0x40005901 +.set CYREG_SAR0_CSR2, 0x40005902 +.set CYREG_SAR0_CSR3, 0x40005903 +.set CYREG_SAR0_CSR4, 0x40005904 +.set CYREG_SAR0_CSR5, 0x40005905 +.set CYREG_SAR0_CSR6, 0x40005906 +.set CYDEV_ANAIF_CFG_SAR1_BASE, 0x40005908 +.set CYDEV_ANAIF_CFG_SAR1_SIZE, 0x00000007 +.set CYREG_SAR1_CSR0, 0x40005908 +.set CYREG_SAR1_CSR1, 0x40005909 +.set CYREG_SAR1_CSR2, 0x4000590a +.set CYREG_SAR1_CSR3, 0x4000590b +.set CYREG_SAR1_CSR4, 0x4000590c +.set CYREG_SAR1_CSR5, 0x4000590d +.set CYREG_SAR1_CSR6, 0x4000590e +.set CYDEV_ANAIF_RT_BASE, 0x40005a00 +.set CYDEV_ANAIF_RT_SIZE, 0x00000162 +.set CYDEV_ANAIF_RT_SC0_BASE, 0x40005a00 +.set CYDEV_ANAIF_RT_SC0_SIZE, 0x0000000d +.set CYREG_SC0_SW0, 0x40005a00 +.set CYREG_SC0_SW2, 0x40005a02 +.set CYREG_SC0_SW3, 0x40005a03 +.set CYREG_SC0_SW4, 0x40005a04 +.set CYREG_SC0_SW6, 0x40005a06 +.set CYREG_SC0_SW7, 0x40005a07 +.set CYREG_SC0_SW8, 0x40005a08 +.set CYREG_SC0_SW10, 0x40005a0a +.set CYREG_SC0_CLK, 0x40005a0b +.set CYREG_SC0_BST, 0x40005a0c +.set CYDEV_ANAIF_RT_SC1_BASE, 0x40005a10 +.set CYDEV_ANAIF_RT_SC1_SIZE, 0x0000000d +.set CYREG_SC1_SW0, 0x40005a10 +.set CYREG_SC1_SW2, 0x40005a12 +.set CYREG_SC1_SW3, 0x40005a13 +.set CYREG_SC1_SW4, 0x40005a14 +.set CYREG_SC1_SW6, 0x40005a16 +.set CYREG_SC1_SW7, 0x40005a17 +.set CYREG_SC1_SW8, 0x40005a18 +.set CYREG_SC1_SW10, 0x40005a1a +.set CYREG_SC1_CLK, 0x40005a1b +.set CYREG_SC1_BST, 0x40005a1c +.set CYDEV_ANAIF_RT_SC2_BASE, 0x40005a20 +.set CYDEV_ANAIF_RT_SC2_SIZE, 0x0000000d +.set CYREG_SC2_SW0, 0x40005a20 +.set CYREG_SC2_SW2, 0x40005a22 +.set CYREG_SC2_SW3, 0x40005a23 +.set CYREG_SC2_SW4, 0x40005a24 +.set CYREG_SC2_SW6, 0x40005a26 +.set CYREG_SC2_SW7, 0x40005a27 +.set CYREG_SC2_SW8, 0x40005a28 +.set CYREG_SC2_SW10, 0x40005a2a +.set CYREG_SC2_CLK, 0x40005a2b +.set CYREG_SC2_BST, 0x40005a2c +.set CYDEV_ANAIF_RT_SC3_BASE, 0x40005a30 +.set CYDEV_ANAIF_RT_SC3_SIZE, 0x0000000d +.set CYREG_SC3_SW0, 0x40005a30 +.set CYREG_SC3_SW2, 0x40005a32 +.set CYREG_SC3_SW3, 0x40005a33 +.set CYREG_SC3_SW4, 0x40005a34 +.set CYREG_SC3_SW6, 0x40005a36 +.set CYREG_SC3_SW7, 0x40005a37 +.set CYREG_SC3_SW8, 0x40005a38 +.set CYREG_SC3_SW10, 0x40005a3a +.set CYREG_SC3_CLK, 0x40005a3b +.set CYREG_SC3_BST, 0x40005a3c +.set CYDEV_ANAIF_RT_DAC0_BASE, 0x40005a80 +.set CYDEV_ANAIF_RT_DAC0_SIZE, 0x00000008 +.set CYREG_DAC0_SW0, 0x40005a80 +.set CYREG_DAC0_SW2, 0x40005a82 +.set CYREG_DAC0_SW3, 0x40005a83 +.set CYREG_DAC0_SW4, 0x40005a84 +.set CYREG_DAC0_STROBE, 0x40005a87 +.set CYDEV_ANAIF_RT_DAC1_BASE, 0x40005a88 +.set CYDEV_ANAIF_RT_DAC1_SIZE, 0x00000008 +.set CYREG_DAC1_SW0, 0x40005a88 +.set CYREG_DAC1_SW2, 0x40005a8a +.set CYREG_DAC1_SW3, 0x40005a8b +.set CYREG_DAC1_SW4, 0x40005a8c +.set CYREG_DAC1_STROBE, 0x40005a8f +.set CYDEV_ANAIF_RT_DAC2_BASE, 0x40005a90 +.set CYDEV_ANAIF_RT_DAC2_SIZE, 0x00000008 +.set CYREG_DAC2_SW0, 0x40005a90 +.set CYREG_DAC2_SW2, 0x40005a92 +.set CYREG_DAC2_SW3, 0x40005a93 +.set CYREG_DAC2_SW4, 0x40005a94 +.set CYREG_DAC2_STROBE, 0x40005a97 +.set CYDEV_ANAIF_RT_DAC3_BASE, 0x40005a98 +.set CYDEV_ANAIF_RT_DAC3_SIZE, 0x00000008 +.set CYREG_DAC3_SW0, 0x40005a98 +.set CYREG_DAC3_SW2, 0x40005a9a +.set CYREG_DAC3_SW3, 0x40005a9b +.set CYREG_DAC3_SW4, 0x40005a9c +.set CYREG_DAC3_STROBE, 0x40005a9f +.set CYDEV_ANAIF_RT_CMP0_BASE, 0x40005ac0 +.set CYDEV_ANAIF_RT_CMP0_SIZE, 0x00000008 +.set CYREG_CMP0_SW0, 0x40005ac0 +.set CYREG_CMP0_SW2, 0x40005ac2 +.set CYREG_CMP0_SW3, 0x40005ac3 +.set CYREG_CMP0_SW4, 0x40005ac4 +.set CYREG_CMP0_SW6, 0x40005ac6 +.set CYREG_CMP0_CLK, 0x40005ac7 +.set CYDEV_ANAIF_RT_CMP1_BASE, 0x40005ac8 +.set CYDEV_ANAIF_RT_CMP1_SIZE, 0x00000008 +.set CYREG_CMP1_SW0, 0x40005ac8 +.set CYREG_CMP1_SW2, 0x40005aca +.set CYREG_CMP1_SW3, 0x40005acb +.set CYREG_CMP1_SW4, 0x40005acc +.set CYREG_CMP1_SW6, 0x40005ace +.set CYREG_CMP1_CLK, 0x40005acf +.set CYDEV_ANAIF_RT_CMP2_BASE, 0x40005ad0 +.set CYDEV_ANAIF_RT_CMP2_SIZE, 0x00000008 +.set CYREG_CMP2_SW0, 0x40005ad0 +.set CYREG_CMP2_SW2, 0x40005ad2 +.set CYREG_CMP2_SW3, 0x40005ad3 +.set CYREG_CMP2_SW4, 0x40005ad4 +.set CYREG_CMP2_SW6, 0x40005ad6 +.set CYREG_CMP2_CLK, 0x40005ad7 +.set CYDEV_ANAIF_RT_CMP3_BASE, 0x40005ad8 +.set CYDEV_ANAIF_RT_CMP3_SIZE, 0x00000008 +.set CYREG_CMP3_SW0, 0x40005ad8 +.set CYREG_CMP3_SW2, 0x40005ada +.set CYREG_CMP3_SW3, 0x40005adb +.set CYREG_CMP3_SW4, 0x40005adc +.set CYREG_CMP3_SW6, 0x40005ade +.set CYREG_CMP3_CLK, 0x40005adf +.set CYDEV_ANAIF_RT_DSM0_BASE, 0x40005b00 +.set CYDEV_ANAIF_RT_DSM0_SIZE, 0x00000008 +.set CYREG_DSM0_SW0, 0x40005b00 +.set CYREG_DSM0_SW2, 0x40005b02 +.set CYREG_DSM0_SW3, 0x40005b03 +.set CYREG_DSM0_SW4, 0x40005b04 +.set CYREG_DSM0_SW6, 0x40005b06 +.set CYREG_DSM0_CLK, 0x40005b07 +.set CYDEV_ANAIF_RT_SAR0_BASE, 0x40005b20 +.set CYDEV_ANAIF_RT_SAR0_SIZE, 0x00000008 +.set CYREG_SAR0_SW0, 0x40005b20 +.set CYREG_SAR0_SW2, 0x40005b22 +.set CYREG_SAR0_SW3, 0x40005b23 +.set CYREG_SAR0_SW4, 0x40005b24 +.set CYREG_SAR0_SW6, 0x40005b26 +.set CYREG_SAR0_CLK, 0x40005b27 +.set CYDEV_ANAIF_RT_SAR1_BASE, 0x40005b28 +.set CYDEV_ANAIF_RT_SAR1_SIZE, 0x00000008 +.set CYREG_SAR1_SW0, 0x40005b28 +.set CYREG_SAR1_SW2, 0x40005b2a +.set CYREG_SAR1_SW3, 0x40005b2b +.set CYREG_SAR1_SW4, 0x40005b2c +.set CYREG_SAR1_SW6, 0x40005b2e +.set CYREG_SAR1_CLK, 0x40005b2f +.set CYDEV_ANAIF_RT_OPAMP0_BASE, 0x40005b40 +.set CYDEV_ANAIF_RT_OPAMP0_SIZE, 0x00000002 +.set CYREG_OPAMP0_MX, 0x40005b40 +.set CYREG_OPAMP0_SW, 0x40005b41 +.set CYDEV_ANAIF_RT_OPAMP1_BASE, 0x40005b42 +.set CYDEV_ANAIF_RT_OPAMP1_SIZE, 0x00000002 +.set CYREG_OPAMP1_MX, 0x40005b42 +.set CYREG_OPAMP1_SW, 0x40005b43 +.set CYDEV_ANAIF_RT_OPAMP2_BASE, 0x40005b44 +.set CYDEV_ANAIF_RT_OPAMP2_SIZE, 0x00000002 +.set CYREG_OPAMP2_MX, 0x40005b44 +.set CYREG_OPAMP2_SW, 0x40005b45 +.set CYDEV_ANAIF_RT_OPAMP3_BASE, 0x40005b46 +.set CYDEV_ANAIF_RT_OPAMP3_SIZE, 0x00000002 +.set CYREG_OPAMP3_MX, 0x40005b46 +.set CYREG_OPAMP3_SW, 0x40005b47 +.set CYDEV_ANAIF_RT_LCDDAC_BASE, 0x40005b50 +.set CYDEV_ANAIF_RT_LCDDAC_SIZE, 0x00000005 +.set CYREG_LCDDAC_SW0, 0x40005b50 +.set CYREG_LCDDAC_SW1, 0x40005b51 +.set CYREG_LCDDAC_SW2, 0x40005b52 +.set CYREG_LCDDAC_SW3, 0x40005b53 +.set CYREG_LCDDAC_SW4, 0x40005b54 +.set CYDEV_ANAIF_RT_SC_BASE, 0x40005b56 +.set CYDEV_ANAIF_RT_SC_SIZE, 0x00000001 +.set CYREG_SC_MISC, 0x40005b56 +.set CYDEV_ANAIF_RT_BUS_BASE, 0x40005b58 +.set CYDEV_ANAIF_RT_BUS_SIZE, 0x00000004 +.set CYREG_BUS_SW0, 0x40005b58 +.set CYREG_BUS_SW2, 0x40005b5a +.set CYREG_BUS_SW3, 0x40005b5b +.set CYDEV_ANAIF_RT_DFT_BASE, 0x40005b5c +.set CYDEV_ANAIF_RT_DFT_SIZE, 0x00000006 +.set CYREG_DFT_CR0, 0x40005b5c +.set CYREG_DFT_CR1, 0x40005b5d +.set CYREG_DFT_CR2, 0x40005b5e +.set CYREG_DFT_CR3, 0x40005b5f +.set CYREG_DFT_CR4, 0x40005b60 +.set CYREG_DFT_CR5, 0x40005b61 +.set CYDEV_ANAIF_WRK_BASE, 0x40005b80 +.set CYDEV_ANAIF_WRK_SIZE, 0x00000029 +.set CYDEV_ANAIF_WRK_DAC0_BASE, 0x40005b80 +.set CYDEV_ANAIF_WRK_DAC0_SIZE, 0x00000001 +.set CYREG_DAC0_D, 0x40005b80 +.set CYDEV_ANAIF_WRK_DAC1_BASE, 0x40005b81 +.set CYDEV_ANAIF_WRK_DAC1_SIZE, 0x00000001 +.set CYREG_DAC1_D, 0x40005b81 +.set CYDEV_ANAIF_WRK_DAC2_BASE, 0x40005b82 +.set CYDEV_ANAIF_WRK_DAC2_SIZE, 0x00000001 +.set CYREG_DAC2_D, 0x40005b82 +.set CYDEV_ANAIF_WRK_DAC3_BASE, 0x40005b83 +.set CYDEV_ANAIF_WRK_DAC3_SIZE, 0x00000001 +.set CYREG_DAC3_D, 0x40005b83 +.set CYDEV_ANAIF_WRK_DSM0_BASE, 0x40005b88 +.set CYDEV_ANAIF_WRK_DSM0_SIZE, 0x00000002 +.set CYREG_DSM0_OUT0, 0x40005b88 +.set CYREG_DSM0_OUT1, 0x40005b89 +.set CYDEV_ANAIF_WRK_LUT_BASE, 0x40005b90 +.set CYDEV_ANAIF_WRK_LUT_SIZE, 0x00000005 +.set CYREG_LUT_SR, 0x40005b90 +.set CYREG_LUT_WRK1, 0x40005b91 +.set CYREG_LUT_MSK, 0x40005b92 +.set CYREG_LUT_CLK, 0x40005b93 +.set CYREG_LUT_CPTR, 0x40005b94 +.set CYDEV_ANAIF_WRK_CMP_BASE, 0x40005b96 +.set CYDEV_ANAIF_WRK_CMP_SIZE, 0x00000002 +.set CYREG_CMP_WRK, 0x40005b96 +.set CYREG_CMP_TST, 0x40005b97 +.set CYDEV_ANAIF_WRK_SC_BASE, 0x40005b98 +.set CYDEV_ANAIF_WRK_SC_SIZE, 0x00000005 +.set CYREG_SC_SR, 0x40005b98 +.set CYREG_SC_WRK1, 0x40005b99 +.set CYREG_SC_MSK, 0x40005b9a +.set CYREG_SC_CMPINV, 0x40005b9b +.set CYREG_SC_CPTR, 0x40005b9c +.set CYDEV_ANAIF_WRK_SAR0_BASE, 0x40005ba0 +.set CYDEV_ANAIF_WRK_SAR0_SIZE, 0x00000002 +.set CYREG_SAR0_WRK0, 0x40005ba0 +.set CYREG_SAR0_WRK1, 0x40005ba1 +.set CYDEV_ANAIF_WRK_SAR1_BASE, 0x40005ba2 +.set CYDEV_ANAIF_WRK_SAR1_SIZE, 0x00000002 +.set CYREG_SAR1_WRK0, 0x40005ba2 +.set CYREG_SAR1_WRK1, 0x40005ba3 +.set CYDEV_ANAIF_WRK_SARS_BASE, 0x40005ba8 +.set CYDEV_ANAIF_WRK_SARS_SIZE, 0x00000001 +.set CYREG_ANAIF_WRK_SARS_SOF, 0x40005ba8 +.set CYDEV_USB_BASE, 0x40006000 +.set CYDEV_USB_SIZE, 0x00000300 +.set CYREG_USB_EP0_DR0, 0x40006000 +.set CYREG_USB_EP0_DR1, 0x40006001 +.set CYREG_USB_EP0_DR2, 0x40006002 +.set CYREG_USB_EP0_DR3, 0x40006003 +.set CYREG_USB_EP0_DR4, 0x40006004 +.set CYREG_USB_EP0_DR5, 0x40006005 +.set CYREG_USB_EP0_DR6, 0x40006006 +.set CYREG_USB_EP0_DR7, 0x40006007 +.set CYREG_USB_CR0, 0x40006008 +.set CYREG_USB_CR1, 0x40006009 +.set CYREG_USB_SIE_EP_INT_EN, 0x4000600a +.set CYREG_USB_SIE_EP_INT_SR, 0x4000600b +.set CYDEV_USB_SIE_EP1_BASE, 0x4000600c +.set CYDEV_USB_SIE_EP1_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP1_CNT0, 0x4000600c +.set CYREG_USB_SIE_EP1_CNT1, 0x4000600d +.set CYREG_USB_SIE_EP1_CR0, 0x4000600e +.set CYREG_USB_USBIO_CR0, 0x40006010 +.set CYREG_USB_USBIO_CR1, 0x40006012 +.set CYREG_USB_DYN_RECONFIG, 0x40006014 +.set CYREG_USB_SOF0, 0x40006018 +.set CYREG_USB_SOF1, 0x40006019 +.set CYDEV_USB_SIE_EP2_BASE, 0x4000601c +.set CYDEV_USB_SIE_EP2_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP2_CNT0, 0x4000601c +.set CYREG_USB_SIE_EP2_CNT1, 0x4000601d +.set CYREG_USB_SIE_EP2_CR0, 0x4000601e +.set CYREG_USB_EP0_CR, 0x40006028 +.set CYREG_USB_EP0_CNT, 0x40006029 +.set CYDEV_USB_SIE_EP3_BASE, 0x4000602c +.set CYDEV_USB_SIE_EP3_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP3_CNT0, 0x4000602c +.set CYREG_USB_SIE_EP3_CNT1, 0x4000602d +.set CYREG_USB_SIE_EP3_CR0, 0x4000602e +.set CYDEV_USB_SIE_EP4_BASE, 0x4000603c +.set CYDEV_USB_SIE_EP4_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP4_CNT0, 0x4000603c +.set CYREG_USB_SIE_EP4_CNT1, 0x4000603d +.set CYREG_USB_SIE_EP4_CR0, 0x4000603e +.set CYDEV_USB_SIE_EP5_BASE, 0x4000604c +.set CYDEV_USB_SIE_EP5_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP5_CNT0, 0x4000604c +.set CYREG_USB_SIE_EP5_CNT1, 0x4000604d +.set CYREG_USB_SIE_EP5_CR0, 0x4000604e +.set CYDEV_USB_SIE_EP6_BASE, 0x4000605c +.set CYDEV_USB_SIE_EP6_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP6_CNT0, 0x4000605c +.set CYREG_USB_SIE_EP6_CNT1, 0x4000605d +.set CYREG_USB_SIE_EP6_CR0, 0x4000605e +.set CYDEV_USB_SIE_EP7_BASE, 0x4000606c +.set CYDEV_USB_SIE_EP7_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP7_CNT0, 0x4000606c +.set CYREG_USB_SIE_EP7_CNT1, 0x4000606d +.set CYREG_USB_SIE_EP7_CR0, 0x4000606e +.set CYDEV_USB_SIE_EP8_BASE, 0x4000607c +.set CYDEV_USB_SIE_EP8_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP8_CNT0, 0x4000607c +.set CYREG_USB_SIE_EP8_CNT1, 0x4000607d +.set CYREG_USB_SIE_EP8_CR0, 0x4000607e +.set CYDEV_USB_ARB_EP1_BASE, 0x40006080 +.set CYDEV_USB_ARB_EP1_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP1_CFG, 0x40006080 +.set CYREG_USB_ARB_EP1_INT_EN, 0x40006081 +.set CYREG_USB_ARB_EP1_SR, 0x40006082 +.set CYDEV_USB_ARB_RW1_BASE, 0x40006084 +.set CYDEV_USB_ARB_RW1_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW1_WA, 0x40006084 +.set CYREG_USB_ARB_RW1_WA_MSB, 0x40006085 +.set CYREG_USB_ARB_RW1_RA, 0x40006086 +.set CYREG_USB_ARB_RW1_RA_MSB, 0x40006087 +.set CYREG_USB_ARB_RW1_DR, 0x40006088 +.set CYREG_USB_BUF_SIZE, 0x4000608c +.set CYREG_USB_EP_ACTIVE, 0x4000608e +.set CYREG_USB_EP_TYPE, 0x4000608f +.set CYDEV_USB_ARB_EP2_BASE, 0x40006090 +.set CYDEV_USB_ARB_EP2_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP2_CFG, 0x40006090 +.set CYREG_USB_ARB_EP2_INT_EN, 0x40006091 +.set CYREG_USB_ARB_EP2_SR, 0x40006092 +.set CYDEV_USB_ARB_RW2_BASE, 0x40006094 +.set CYDEV_USB_ARB_RW2_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW2_WA, 0x40006094 +.set CYREG_USB_ARB_RW2_WA_MSB, 0x40006095 +.set CYREG_USB_ARB_RW2_RA, 0x40006096 +.set CYREG_USB_ARB_RW2_RA_MSB, 0x40006097 +.set CYREG_USB_ARB_RW2_DR, 0x40006098 +.set CYREG_USB_ARB_CFG, 0x4000609c +.set CYREG_USB_USB_CLK_EN, 0x4000609d +.set CYREG_USB_ARB_INT_EN, 0x4000609e +.set CYREG_USB_ARB_INT_SR, 0x4000609f +.set CYDEV_USB_ARB_EP3_BASE, 0x400060a0 +.set CYDEV_USB_ARB_EP3_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP3_CFG, 0x400060a0 +.set CYREG_USB_ARB_EP3_INT_EN, 0x400060a1 +.set CYREG_USB_ARB_EP3_SR, 0x400060a2 +.set CYDEV_USB_ARB_RW3_BASE, 0x400060a4 +.set CYDEV_USB_ARB_RW3_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW3_WA, 0x400060a4 +.set CYREG_USB_ARB_RW3_WA_MSB, 0x400060a5 +.set CYREG_USB_ARB_RW3_RA, 0x400060a6 +.set CYREG_USB_ARB_RW3_RA_MSB, 0x400060a7 +.set CYREG_USB_ARB_RW3_DR, 0x400060a8 +.set CYREG_USB_CWA, 0x400060ac +.set CYREG_USB_CWA_MSB, 0x400060ad +.set CYDEV_USB_ARB_EP4_BASE, 0x400060b0 +.set CYDEV_USB_ARB_EP4_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP4_CFG, 0x400060b0 +.set CYREG_USB_ARB_EP4_INT_EN, 0x400060b1 +.set CYREG_USB_ARB_EP4_SR, 0x400060b2 +.set CYDEV_USB_ARB_RW4_BASE, 0x400060b4 +.set CYDEV_USB_ARB_RW4_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW4_WA, 0x400060b4 +.set CYREG_USB_ARB_RW4_WA_MSB, 0x400060b5 +.set CYREG_USB_ARB_RW4_RA, 0x400060b6 +.set CYREG_USB_ARB_RW4_RA_MSB, 0x400060b7 +.set CYREG_USB_ARB_RW4_DR, 0x400060b8 +.set CYREG_USB_DMA_THRES, 0x400060bc +.set CYREG_USB_DMA_THRES_MSB, 0x400060bd +.set CYDEV_USB_ARB_EP5_BASE, 0x400060c0 +.set CYDEV_USB_ARB_EP5_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP5_CFG, 0x400060c0 +.set CYREG_USB_ARB_EP5_INT_EN, 0x400060c1 +.set CYREG_USB_ARB_EP5_SR, 0x400060c2 +.set CYDEV_USB_ARB_RW5_BASE, 0x400060c4 +.set CYDEV_USB_ARB_RW5_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW5_WA, 0x400060c4 +.set CYREG_USB_ARB_RW5_WA_MSB, 0x400060c5 +.set CYREG_USB_ARB_RW5_RA, 0x400060c6 +.set CYREG_USB_ARB_RW5_RA_MSB, 0x400060c7 +.set CYREG_USB_ARB_RW5_DR, 0x400060c8 +.set CYREG_USB_BUS_RST_CNT, 0x400060cc +.set CYDEV_USB_ARB_EP6_BASE, 0x400060d0 +.set CYDEV_USB_ARB_EP6_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP6_CFG, 0x400060d0 +.set CYREG_USB_ARB_EP6_INT_EN, 0x400060d1 +.set CYREG_USB_ARB_EP6_SR, 0x400060d2 +.set CYDEV_USB_ARB_RW6_BASE, 0x400060d4 +.set CYDEV_USB_ARB_RW6_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW6_WA, 0x400060d4 +.set CYREG_USB_ARB_RW6_WA_MSB, 0x400060d5 +.set CYREG_USB_ARB_RW6_RA, 0x400060d6 +.set CYREG_USB_ARB_RW6_RA_MSB, 0x400060d7 +.set CYREG_USB_ARB_RW6_DR, 0x400060d8 +.set CYDEV_USB_ARB_EP7_BASE, 0x400060e0 +.set CYDEV_USB_ARB_EP7_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP7_CFG, 0x400060e0 +.set CYREG_USB_ARB_EP7_INT_EN, 0x400060e1 +.set CYREG_USB_ARB_EP7_SR, 0x400060e2 +.set CYDEV_USB_ARB_RW7_BASE, 0x400060e4 +.set CYDEV_USB_ARB_RW7_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW7_WA, 0x400060e4 +.set CYREG_USB_ARB_RW7_WA_MSB, 0x400060e5 +.set CYREG_USB_ARB_RW7_RA, 0x400060e6 +.set CYREG_USB_ARB_RW7_RA_MSB, 0x400060e7 +.set CYREG_USB_ARB_RW7_DR, 0x400060e8 +.set CYDEV_USB_ARB_EP8_BASE, 0x400060f0 +.set CYDEV_USB_ARB_EP8_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP8_CFG, 0x400060f0 +.set CYREG_USB_ARB_EP8_INT_EN, 0x400060f1 +.set CYREG_USB_ARB_EP8_SR, 0x400060f2 +.set CYDEV_USB_ARB_RW8_BASE, 0x400060f4 +.set CYDEV_USB_ARB_RW8_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW8_WA, 0x400060f4 +.set CYREG_USB_ARB_RW8_WA_MSB, 0x400060f5 +.set CYREG_USB_ARB_RW8_RA, 0x400060f6 +.set CYREG_USB_ARB_RW8_RA_MSB, 0x400060f7 +.set CYREG_USB_ARB_RW8_DR, 0x400060f8 +.set CYDEV_USB_MEM_BASE, 0x40006100 +.set CYDEV_USB_MEM_SIZE, 0x00000200 +.set CYREG_USB_MEM_DATA_MBASE, 0x40006100 +.set CYREG_USB_MEM_DATA_MSIZE, 0x00000200 +.set CYDEV_UWRK_BASE, 0x40006400 +.set CYDEV_UWRK_SIZE, 0x00000b60 +.set CYDEV_UWRK_UWRK8_BASE, 0x40006400 +.set CYDEV_UWRK_UWRK8_SIZE, 0x000003b0 +.set CYDEV_UWRK_UWRK8_B0_BASE, 0x40006400 +.set CYDEV_UWRK_UWRK8_B0_SIZE, 0x000000b0 +.set CYREG_B0_UDB00_A0, 0x40006400 +.set CYREG_B0_UDB01_A0, 0x40006401 +.set CYREG_B0_UDB02_A0, 0x40006402 +.set CYREG_B0_UDB03_A0, 0x40006403 +.set CYREG_B0_UDB04_A0, 0x40006404 +.set CYREG_B0_UDB05_A0, 0x40006405 +.set CYREG_B0_UDB06_A0, 0x40006406 +.set CYREG_B0_UDB07_A0, 0x40006407 +.set CYREG_B0_UDB08_A0, 0x40006408 +.set CYREG_B0_UDB09_A0, 0x40006409 +.set CYREG_B0_UDB10_A0, 0x4000640a +.set CYREG_B0_UDB11_A0, 0x4000640b +.set CYREG_B0_UDB12_A0, 0x4000640c +.set CYREG_B0_UDB13_A0, 0x4000640d +.set CYREG_B0_UDB14_A0, 0x4000640e +.set CYREG_B0_UDB15_A0, 0x4000640f +.set CYREG_B0_UDB00_A1, 0x40006410 +.set CYREG_B0_UDB01_A1, 0x40006411 +.set CYREG_B0_UDB02_A1, 0x40006412 +.set CYREG_B0_UDB03_A1, 0x40006413 +.set CYREG_B0_UDB04_A1, 0x40006414 +.set CYREG_B0_UDB05_A1, 0x40006415 +.set CYREG_B0_UDB06_A1, 0x40006416 +.set CYREG_B0_UDB07_A1, 0x40006417 +.set CYREG_B0_UDB08_A1, 0x40006418 +.set CYREG_B0_UDB09_A1, 0x40006419 +.set CYREG_B0_UDB10_A1, 0x4000641a +.set CYREG_B0_UDB11_A1, 0x4000641b +.set CYREG_B0_UDB12_A1, 0x4000641c +.set CYREG_B0_UDB13_A1, 0x4000641d +.set CYREG_B0_UDB14_A1, 0x4000641e +.set CYREG_B0_UDB15_A1, 0x4000641f +.set CYREG_B0_UDB00_D0, 0x40006420 +.set CYREG_B0_UDB01_D0, 0x40006421 +.set CYREG_B0_UDB02_D0, 0x40006422 +.set CYREG_B0_UDB03_D0, 0x40006423 +.set CYREG_B0_UDB04_D0, 0x40006424 +.set CYREG_B0_UDB05_D0, 0x40006425 +.set CYREG_B0_UDB06_D0, 0x40006426 +.set CYREG_B0_UDB07_D0, 0x40006427 +.set CYREG_B0_UDB08_D0, 0x40006428 +.set CYREG_B0_UDB09_D0, 0x40006429 +.set CYREG_B0_UDB10_D0, 0x4000642a +.set CYREG_B0_UDB11_D0, 0x4000642b +.set CYREG_B0_UDB12_D0, 0x4000642c +.set CYREG_B0_UDB13_D0, 0x4000642d +.set CYREG_B0_UDB14_D0, 0x4000642e +.set CYREG_B0_UDB15_D0, 0x4000642f +.set CYREG_B0_UDB00_D1, 0x40006430 +.set CYREG_B0_UDB01_D1, 0x40006431 +.set CYREG_B0_UDB02_D1, 0x40006432 +.set CYREG_B0_UDB03_D1, 0x40006433 +.set CYREG_B0_UDB04_D1, 0x40006434 +.set CYREG_B0_UDB05_D1, 0x40006435 +.set CYREG_B0_UDB06_D1, 0x40006436 +.set CYREG_B0_UDB07_D1, 0x40006437 +.set CYREG_B0_UDB08_D1, 0x40006438 +.set CYREG_B0_UDB09_D1, 0x40006439 +.set CYREG_B0_UDB10_D1, 0x4000643a +.set CYREG_B0_UDB11_D1, 0x4000643b +.set CYREG_B0_UDB12_D1, 0x4000643c +.set CYREG_B0_UDB13_D1, 0x4000643d +.set CYREG_B0_UDB14_D1, 0x4000643e +.set CYREG_B0_UDB15_D1, 0x4000643f +.set CYREG_B0_UDB00_F0, 0x40006440 +.set CYREG_B0_UDB01_F0, 0x40006441 +.set CYREG_B0_UDB02_F0, 0x40006442 +.set CYREG_B0_UDB03_F0, 0x40006443 +.set CYREG_B0_UDB04_F0, 0x40006444 +.set CYREG_B0_UDB05_F0, 0x40006445 +.set CYREG_B0_UDB06_F0, 0x40006446 +.set CYREG_B0_UDB07_F0, 0x40006447 +.set CYREG_B0_UDB08_F0, 0x40006448 +.set CYREG_B0_UDB09_F0, 0x40006449 +.set CYREG_B0_UDB10_F0, 0x4000644a +.set CYREG_B0_UDB11_F0, 0x4000644b +.set CYREG_B0_UDB12_F0, 0x4000644c +.set CYREG_B0_UDB13_F0, 0x4000644d +.set CYREG_B0_UDB14_F0, 0x4000644e +.set CYREG_B0_UDB15_F0, 0x4000644f +.set CYREG_B0_UDB00_F1, 0x40006450 +.set CYREG_B0_UDB01_F1, 0x40006451 +.set CYREG_B0_UDB02_F1, 0x40006452 +.set CYREG_B0_UDB03_F1, 0x40006453 +.set CYREG_B0_UDB04_F1, 0x40006454 +.set CYREG_B0_UDB05_F1, 0x40006455 +.set CYREG_B0_UDB06_F1, 0x40006456 +.set CYREG_B0_UDB07_F1, 0x40006457 +.set CYREG_B0_UDB08_F1, 0x40006458 +.set CYREG_B0_UDB09_F1, 0x40006459 +.set CYREG_B0_UDB10_F1, 0x4000645a +.set CYREG_B0_UDB11_F1, 0x4000645b +.set CYREG_B0_UDB12_F1, 0x4000645c +.set CYREG_B0_UDB13_F1, 0x4000645d +.set CYREG_B0_UDB14_F1, 0x4000645e +.set CYREG_B0_UDB15_F1, 0x4000645f +.set CYREG_B0_UDB00_ST, 0x40006460 +.set CYREG_B0_UDB01_ST, 0x40006461 +.set CYREG_B0_UDB02_ST, 0x40006462 +.set CYREG_B0_UDB03_ST, 0x40006463 +.set CYREG_B0_UDB04_ST, 0x40006464 +.set CYREG_B0_UDB05_ST, 0x40006465 +.set CYREG_B0_UDB06_ST, 0x40006466 +.set CYREG_B0_UDB07_ST, 0x40006467 +.set CYREG_B0_UDB08_ST, 0x40006468 +.set CYREG_B0_UDB09_ST, 0x40006469 +.set CYREG_B0_UDB10_ST, 0x4000646a +.set CYREG_B0_UDB11_ST, 0x4000646b +.set CYREG_B0_UDB12_ST, 0x4000646c +.set CYREG_B0_UDB13_ST, 0x4000646d +.set CYREG_B0_UDB14_ST, 0x4000646e +.set CYREG_B0_UDB15_ST, 0x4000646f +.set CYREG_B0_UDB00_CTL, 0x40006470 +.set CYREG_B0_UDB01_CTL, 0x40006471 +.set CYREG_B0_UDB02_CTL, 0x40006472 +.set CYREG_B0_UDB03_CTL, 0x40006473 +.set CYREG_B0_UDB04_CTL, 0x40006474 +.set CYREG_B0_UDB05_CTL, 0x40006475 +.set CYREG_B0_UDB06_CTL, 0x40006476 +.set CYREG_B0_UDB07_CTL, 0x40006477 +.set CYREG_B0_UDB08_CTL, 0x40006478 +.set CYREG_B0_UDB09_CTL, 0x40006479 +.set CYREG_B0_UDB10_CTL, 0x4000647a +.set CYREG_B0_UDB11_CTL, 0x4000647b +.set CYREG_B0_UDB12_CTL, 0x4000647c +.set CYREG_B0_UDB13_CTL, 0x4000647d +.set CYREG_B0_UDB14_CTL, 0x4000647e +.set CYREG_B0_UDB15_CTL, 0x4000647f +.set CYREG_B0_UDB00_MSK, 0x40006480 +.set CYREG_B0_UDB01_MSK, 0x40006481 +.set CYREG_B0_UDB02_MSK, 0x40006482 +.set CYREG_B0_UDB03_MSK, 0x40006483 +.set CYREG_B0_UDB04_MSK, 0x40006484 +.set CYREG_B0_UDB05_MSK, 0x40006485 +.set CYREG_B0_UDB06_MSK, 0x40006486 +.set CYREG_B0_UDB07_MSK, 0x40006487 +.set CYREG_B0_UDB08_MSK, 0x40006488 +.set CYREG_B0_UDB09_MSK, 0x40006489 +.set CYREG_B0_UDB10_MSK, 0x4000648a +.set CYREG_B0_UDB11_MSK, 0x4000648b +.set CYREG_B0_UDB12_MSK, 0x4000648c +.set CYREG_B0_UDB13_MSK, 0x4000648d +.set CYREG_B0_UDB14_MSK, 0x4000648e +.set CYREG_B0_UDB15_MSK, 0x4000648f +.set CYREG_B0_UDB00_ACTL, 0x40006490 +.set CYREG_B0_UDB01_ACTL, 0x40006491 +.set CYREG_B0_UDB02_ACTL, 0x40006492 +.set CYREG_B0_UDB03_ACTL, 0x40006493 +.set CYREG_B0_UDB04_ACTL, 0x40006494 +.set CYREG_B0_UDB05_ACTL, 0x40006495 +.set CYREG_B0_UDB06_ACTL, 0x40006496 +.set CYREG_B0_UDB07_ACTL, 0x40006497 +.set CYREG_B0_UDB08_ACTL, 0x40006498 +.set CYREG_B0_UDB09_ACTL, 0x40006499 +.set CYREG_B0_UDB10_ACTL, 0x4000649a +.set CYREG_B0_UDB11_ACTL, 0x4000649b +.set CYREG_B0_UDB12_ACTL, 0x4000649c +.set CYREG_B0_UDB13_ACTL, 0x4000649d +.set CYREG_B0_UDB14_ACTL, 0x4000649e +.set CYREG_B0_UDB15_ACTL, 0x4000649f +.set CYREG_B0_UDB00_MC, 0x400064a0 +.set CYREG_B0_UDB01_MC, 0x400064a1 +.set CYREG_B0_UDB02_MC, 0x400064a2 +.set CYREG_B0_UDB03_MC, 0x400064a3 +.set CYREG_B0_UDB04_MC, 0x400064a4 +.set CYREG_B0_UDB05_MC, 0x400064a5 +.set CYREG_B0_UDB06_MC, 0x400064a6 +.set CYREG_B0_UDB07_MC, 0x400064a7 +.set CYREG_B0_UDB08_MC, 0x400064a8 +.set CYREG_B0_UDB09_MC, 0x400064a9 +.set CYREG_B0_UDB10_MC, 0x400064aa +.set CYREG_B0_UDB11_MC, 0x400064ab +.set CYREG_B0_UDB12_MC, 0x400064ac +.set CYREG_B0_UDB13_MC, 0x400064ad +.set CYREG_B0_UDB14_MC, 0x400064ae +.set CYREG_B0_UDB15_MC, 0x400064af +.set CYDEV_UWRK_UWRK8_B1_BASE, 0x40006500 +.set CYDEV_UWRK_UWRK8_B1_SIZE, 0x000000b0 +.set CYREG_B1_UDB04_A0, 0x40006504 +.set CYREG_B1_UDB05_A0, 0x40006505 +.set CYREG_B1_UDB06_A0, 0x40006506 +.set CYREG_B1_UDB07_A0, 0x40006507 +.set CYREG_B1_UDB08_A0, 0x40006508 +.set CYREG_B1_UDB09_A0, 0x40006509 +.set CYREG_B1_UDB10_A0, 0x4000650a +.set CYREG_B1_UDB11_A0, 0x4000650b +.set CYREG_B1_UDB04_A1, 0x40006514 +.set CYREG_B1_UDB05_A1, 0x40006515 +.set CYREG_B1_UDB06_A1, 0x40006516 +.set CYREG_B1_UDB07_A1, 0x40006517 +.set CYREG_B1_UDB08_A1, 0x40006518 +.set CYREG_B1_UDB09_A1, 0x40006519 +.set CYREG_B1_UDB10_A1, 0x4000651a +.set CYREG_B1_UDB11_A1, 0x4000651b +.set CYREG_B1_UDB04_D0, 0x40006524 +.set CYREG_B1_UDB05_D0, 0x40006525 +.set CYREG_B1_UDB06_D0, 0x40006526 +.set CYREG_B1_UDB07_D0, 0x40006527 +.set CYREG_B1_UDB08_D0, 0x40006528 +.set CYREG_B1_UDB09_D0, 0x40006529 +.set CYREG_B1_UDB10_D0, 0x4000652a +.set CYREG_B1_UDB11_D0, 0x4000652b +.set CYREG_B1_UDB04_D1, 0x40006534 +.set CYREG_B1_UDB05_D1, 0x40006535 +.set CYREG_B1_UDB06_D1, 0x40006536 +.set CYREG_B1_UDB07_D1, 0x40006537 +.set CYREG_B1_UDB08_D1, 0x40006538 +.set CYREG_B1_UDB09_D1, 0x40006539 +.set CYREG_B1_UDB10_D1, 0x4000653a +.set CYREG_B1_UDB11_D1, 0x4000653b +.set CYREG_B1_UDB04_F0, 0x40006544 +.set CYREG_B1_UDB05_F0, 0x40006545 +.set CYREG_B1_UDB06_F0, 0x40006546 +.set CYREG_B1_UDB07_F0, 0x40006547 +.set CYREG_B1_UDB08_F0, 0x40006548 +.set CYREG_B1_UDB09_F0, 0x40006549 +.set CYREG_B1_UDB10_F0, 0x4000654a +.set CYREG_B1_UDB11_F0, 0x4000654b +.set CYREG_B1_UDB04_F1, 0x40006554 +.set CYREG_B1_UDB05_F1, 0x40006555 +.set CYREG_B1_UDB06_F1, 0x40006556 +.set CYREG_B1_UDB07_F1, 0x40006557 +.set CYREG_B1_UDB08_F1, 0x40006558 +.set CYREG_B1_UDB09_F1, 0x40006559 +.set CYREG_B1_UDB10_F1, 0x4000655a +.set CYREG_B1_UDB11_F1, 0x4000655b +.set CYREG_B1_UDB04_ST, 0x40006564 +.set CYREG_B1_UDB05_ST, 0x40006565 +.set CYREG_B1_UDB06_ST, 0x40006566 +.set CYREG_B1_UDB07_ST, 0x40006567 +.set CYREG_B1_UDB08_ST, 0x40006568 +.set CYREG_B1_UDB09_ST, 0x40006569 +.set CYREG_B1_UDB10_ST, 0x4000656a +.set CYREG_B1_UDB11_ST, 0x4000656b +.set CYREG_B1_UDB04_CTL, 0x40006574 +.set CYREG_B1_UDB05_CTL, 0x40006575 +.set CYREG_B1_UDB06_CTL, 0x40006576 +.set CYREG_B1_UDB07_CTL, 0x40006577 +.set CYREG_B1_UDB08_CTL, 0x40006578 +.set CYREG_B1_UDB09_CTL, 0x40006579 +.set CYREG_B1_UDB10_CTL, 0x4000657a +.set CYREG_B1_UDB11_CTL, 0x4000657b +.set CYREG_B1_UDB04_MSK, 0x40006584 +.set CYREG_B1_UDB05_MSK, 0x40006585 +.set CYREG_B1_UDB06_MSK, 0x40006586 +.set CYREG_B1_UDB07_MSK, 0x40006587 +.set CYREG_B1_UDB08_MSK, 0x40006588 +.set CYREG_B1_UDB09_MSK, 0x40006589 +.set CYREG_B1_UDB10_MSK, 0x4000658a +.set CYREG_B1_UDB11_MSK, 0x4000658b +.set CYREG_B1_UDB04_ACTL, 0x40006594 +.set CYREG_B1_UDB05_ACTL, 0x40006595 +.set CYREG_B1_UDB06_ACTL, 0x40006596 +.set CYREG_B1_UDB07_ACTL, 0x40006597 +.set CYREG_B1_UDB08_ACTL, 0x40006598 +.set CYREG_B1_UDB09_ACTL, 0x40006599 +.set CYREG_B1_UDB10_ACTL, 0x4000659a +.set CYREG_B1_UDB11_ACTL, 0x4000659b +.set CYREG_B1_UDB04_MC, 0x400065a4 +.set CYREG_B1_UDB05_MC, 0x400065a5 +.set CYREG_B1_UDB06_MC, 0x400065a6 +.set CYREG_B1_UDB07_MC, 0x400065a7 +.set CYREG_B1_UDB08_MC, 0x400065a8 +.set CYREG_B1_UDB09_MC, 0x400065a9 +.set CYREG_B1_UDB10_MC, 0x400065aa +.set CYREG_B1_UDB11_MC, 0x400065ab +.set CYDEV_UWRK_UWRK16_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_SIZE, 0x00000760 +.set CYDEV_UWRK_UWRK16_CAT_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_CAT_SIZE, 0x00000760 +.set CYDEV_UWRK_UWRK16_CAT_B0_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_CAT_B0_SIZE, 0x00000160 +.set CYREG_B0_UDB00_A0_A1, 0x40006800 +.set CYREG_B0_UDB01_A0_A1, 0x40006802 +.set CYREG_B0_UDB02_A0_A1, 0x40006804 +.set CYREG_B0_UDB03_A0_A1, 0x40006806 +.set CYREG_B0_UDB04_A0_A1, 0x40006808 +.set CYREG_B0_UDB05_A0_A1, 0x4000680a +.set CYREG_B0_UDB06_A0_A1, 0x4000680c +.set CYREG_B0_UDB07_A0_A1, 0x4000680e +.set CYREG_B0_UDB08_A0_A1, 0x40006810 +.set CYREG_B0_UDB09_A0_A1, 0x40006812 +.set CYREG_B0_UDB10_A0_A1, 0x40006814 +.set CYREG_B0_UDB11_A0_A1, 0x40006816 +.set CYREG_B0_UDB12_A0_A1, 0x40006818 +.set CYREG_B0_UDB13_A0_A1, 0x4000681a +.set CYREG_B0_UDB14_A0_A1, 0x4000681c +.set CYREG_B0_UDB15_A0_A1, 0x4000681e +.set CYREG_B0_UDB00_D0_D1, 0x40006840 +.set CYREG_B0_UDB01_D0_D1, 0x40006842 +.set CYREG_B0_UDB02_D0_D1, 0x40006844 +.set CYREG_B0_UDB03_D0_D1, 0x40006846 +.set CYREG_B0_UDB04_D0_D1, 0x40006848 +.set CYREG_B0_UDB05_D0_D1, 0x4000684a +.set CYREG_B0_UDB06_D0_D1, 0x4000684c +.set CYREG_B0_UDB07_D0_D1, 0x4000684e +.set CYREG_B0_UDB08_D0_D1, 0x40006850 +.set CYREG_B0_UDB09_D0_D1, 0x40006852 +.set CYREG_B0_UDB10_D0_D1, 0x40006854 +.set CYREG_B0_UDB11_D0_D1, 0x40006856 +.set CYREG_B0_UDB12_D0_D1, 0x40006858 +.set CYREG_B0_UDB13_D0_D1, 0x4000685a +.set CYREG_B0_UDB14_D0_D1, 0x4000685c +.set CYREG_B0_UDB15_D0_D1, 0x4000685e +.set CYREG_B0_UDB00_F0_F1, 0x40006880 +.set CYREG_B0_UDB01_F0_F1, 0x40006882 +.set CYREG_B0_UDB02_F0_F1, 0x40006884 +.set CYREG_B0_UDB03_F0_F1, 0x40006886 +.set CYREG_B0_UDB04_F0_F1, 0x40006888 +.set CYREG_B0_UDB05_F0_F1, 0x4000688a +.set CYREG_B0_UDB06_F0_F1, 0x4000688c +.set CYREG_B0_UDB07_F0_F1, 0x4000688e +.set CYREG_B0_UDB08_F0_F1, 0x40006890 +.set CYREG_B0_UDB09_F0_F1, 0x40006892 +.set CYREG_B0_UDB10_F0_F1, 0x40006894 +.set CYREG_B0_UDB11_F0_F1, 0x40006896 +.set CYREG_B0_UDB12_F0_F1, 0x40006898 +.set CYREG_B0_UDB13_F0_F1, 0x4000689a +.set CYREG_B0_UDB14_F0_F1, 0x4000689c +.set CYREG_B0_UDB15_F0_F1, 0x4000689e +.set CYREG_B0_UDB00_ST_CTL, 0x400068c0 +.set CYREG_B0_UDB01_ST_CTL, 0x400068c2 +.set CYREG_B0_UDB02_ST_CTL, 0x400068c4 +.set CYREG_B0_UDB03_ST_CTL, 0x400068c6 +.set CYREG_B0_UDB04_ST_CTL, 0x400068c8 +.set CYREG_B0_UDB05_ST_CTL, 0x400068ca +.set CYREG_B0_UDB06_ST_CTL, 0x400068cc +.set CYREG_B0_UDB07_ST_CTL, 0x400068ce +.set CYREG_B0_UDB08_ST_CTL, 0x400068d0 +.set CYREG_B0_UDB09_ST_CTL, 0x400068d2 +.set CYREG_B0_UDB10_ST_CTL, 0x400068d4 +.set CYREG_B0_UDB11_ST_CTL, 0x400068d6 +.set CYREG_B0_UDB12_ST_CTL, 0x400068d8 +.set CYREG_B0_UDB13_ST_CTL, 0x400068da +.set CYREG_B0_UDB14_ST_CTL, 0x400068dc +.set CYREG_B0_UDB15_ST_CTL, 0x400068de +.set CYREG_B0_UDB00_MSK_ACTL, 0x40006900 +.set CYREG_B0_UDB01_MSK_ACTL, 0x40006902 +.set CYREG_B0_UDB02_MSK_ACTL, 0x40006904 +.set CYREG_B0_UDB03_MSK_ACTL, 0x40006906 +.set CYREG_B0_UDB04_MSK_ACTL, 0x40006908 +.set CYREG_B0_UDB05_MSK_ACTL, 0x4000690a +.set CYREG_B0_UDB06_MSK_ACTL, 0x4000690c +.set CYREG_B0_UDB07_MSK_ACTL, 0x4000690e +.set CYREG_B0_UDB08_MSK_ACTL, 0x40006910 +.set CYREG_B0_UDB09_MSK_ACTL, 0x40006912 +.set CYREG_B0_UDB10_MSK_ACTL, 0x40006914 +.set CYREG_B0_UDB11_MSK_ACTL, 0x40006916 +.set CYREG_B0_UDB12_MSK_ACTL, 0x40006918 +.set CYREG_B0_UDB13_MSK_ACTL, 0x4000691a +.set CYREG_B0_UDB14_MSK_ACTL, 0x4000691c +.set CYREG_B0_UDB15_MSK_ACTL, 0x4000691e +.set CYREG_B0_UDB00_MC_00, 0x40006940 +.set CYREG_B0_UDB01_MC_00, 0x40006942 +.set CYREG_B0_UDB02_MC_00, 0x40006944 +.set CYREG_B0_UDB03_MC_00, 0x40006946 +.set CYREG_B0_UDB04_MC_00, 0x40006948 +.set CYREG_B0_UDB05_MC_00, 0x4000694a +.set CYREG_B0_UDB06_MC_00, 0x4000694c +.set CYREG_B0_UDB07_MC_00, 0x4000694e +.set CYREG_B0_UDB08_MC_00, 0x40006950 +.set CYREG_B0_UDB09_MC_00, 0x40006952 +.set CYREG_B0_UDB10_MC_00, 0x40006954 +.set CYREG_B0_UDB11_MC_00, 0x40006956 +.set CYREG_B0_UDB12_MC_00, 0x40006958 +.set CYREG_B0_UDB13_MC_00, 0x4000695a +.set CYREG_B0_UDB14_MC_00, 0x4000695c +.set CYREG_B0_UDB15_MC_00, 0x4000695e +.set CYDEV_UWRK_UWRK16_CAT_B1_BASE, 0x40006a00 +.set CYDEV_UWRK_UWRK16_CAT_B1_SIZE, 0x00000160 +.set CYREG_B1_UDB04_A0_A1, 0x40006a08 +.set CYREG_B1_UDB05_A0_A1, 0x40006a0a +.set CYREG_B1_UDB06_A0_A1, 0x40006a0c +.set CYREG_B1_UDB07_A0_A1, 0x40006a0e +.set CYREG_B1_UDB08_A0_A1, 0x40006a10 +.set CYREG_B1_UDB09_A0_A1, 0x40006a12 +.set CYREG_B1_UDB10_A0_A1, 0x40006a14 +.set CYREG_B1_UDB11_A0_A1, 0x40006a16 +.set CYREG_B1_UDB04_D0_D1, 0x40006a48 +.set CYREG_B1_UDB05_D0_D1, 0x40006a4a +.set CYREG_B1_UDB06_D0_D1, 0x40006a4c +.set CYREG_B1_UDB07_D0_D1, 0x40006a4e +.set CYREG_B1_UDB08_D0_D1, 0x40006a50 +.set CYREG_B1_UDB09_D0_D1, 0x40006a52 +.set CYREG_B1_UDB10_D0_D1, 0x40006a54 +.set CYREG_B1_UDB11_D0_D1, 0x40006a56 +.set CYREG_B1_UDB04_F0_F1, 0x40006a88 +.set CYREG_B1_UDB05_F0_F1, 0x40006a8a +.set CYREG_B1_UDB06_F0_F1, 0x40006a8c +.set CYREG_B1_UDB07_F0_F1, 0x40006a8e +.set CYREG_B1_UDB08_F0_F1, 0x40006a90 +.set CYREG_B1_UDB09_F0_F1, 0x40006a92 +.set CYREG_B1_UDB10_F0_F1, 0x40006a94 +.set CYREG_B1_UDB11_F0_F1, 0x40006a96 +.set CYREG_B1_UDB04_ST_CTL, 0x40006ac8 +.set CYREG_B1_UDB05_ST_CTL, 0x40006aca +.set CYREG_B1_UDB06_ST_CTL, 0x40006acc +.set CYREG_B1_UDB07_ST_CTL, 0x40006ace +.set CYREG_B1_UDB08_ST_CTL, 0x40006ad0 +.set CYREG_B1_UDB09_ST_CTL, 0x40006ad2 +.set CYREG_B1_UDB10_ST_CTL, 0x40006ad4 +.set CYREG_B1_UDB11_ST_CTL, 0x40006ad6 +.set CYREG_B1_UDB04_MSK_ACTL, 0x40006b08 +.set CYREG_B1_UDB05_MSK_ACTL, 0x40006b0a +.set CYREG_B1_UDB06_MSK_ACTL, 0x40006b0c +.set CYREG_B1_UDB07_MSK_ACTL, 0x40006b0e +.set CYREG_B1_UDB08_MSK_ACTL, 0x40006b10 +.set CYREG_B1_UDB09_MSK_ACTL, 0x40006b12 +.set CYREG_B1_UDB10_MSK_ACTL, 0x40006b14 +.set CYREG_B1_UDB11_MSK_ACTL, 0x40006b16 +.set CYREG_B1_UDB04_MC_00, 0x40006b48 +.set CYREG_B1_UDB05_MC_00, 0x40006b4a +.set CYREG_B1_UDB06_MC_00, 0x40006b4c +.set CYREG_B1_UDB07_MC_00, 0x40006b4e +.set CYREG_B1_UDB08_MC_00, 0x40006b50 +.set CYREG_B1_UDB09_MC_00, 0x40006b52 +.set CYREG_B1_UDB10_MC_00, 0x40006b54 +.set CYREG_B1_UDB11_MC_00, 0x40006b56 +.set CYDEV_UWRK_UWRK16_DEF_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_DEF_SIZE, 0x0000075e +.set CYDEV_UWRK_UWRK16_DEF_B0_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_DEF_B0_SIZE, 0x0000015e +.set CYREG_B0_UDB00_01_A0, 0x40006800 +.set CYREG_B0_UDB01_02_A0, 0x40006802 +.set CYREG_B0_UDB02_03_A0, 0x40006804 +.set CYREG_B0_UDB03_04_A0, 0x40006806 +.set CYREG_B0_UDB04_05_A0, 0x40006808 +.set CYREG_B0_UDB05_06_A0, 0x4000680a +.set CYREG_B0_UDB06_07_A0, 0x4000680c +.set CYREG_B0_UDB07_08_A0, 0x4000680e +.set CYREG_B0_UDB08_09_A0, 0x40006810 +.set CYREG_B0_UDB09_10_A0, 0x40006812 +.set CYREG_B0_UDB10_11_A0, 0x40006814 +.set CYREG_B0_UDB11_12_A0, 0x40006816 +.set CYREG_B0_UDB12_13_A0, 0x40006818 +.set CYREG_B0_UDB13_14_A0, 0x4000681a +.set CYREG_B0_UDB14_15_A0, 0x4000681c +.set CYREG_B0_UDB00_01_A1, 0x40006820 +.set CYREG_B0_UDB01_02_A1, 0x40006822 +.set CYREG_B0_UDB02_03_A1, 0x40006824 +.set CYREG_B0_UDB03_04_A1, 0x40006826 +.set CYREG_B0_UDB04_05_A1, 0x40006828 +.set CYREG_B0_UDB05_06_A1, 0x4000682a +.set CYREG_B0_UDB06_07_A1, 0x4000682c +.set CYREG_B0_UDB07_08_A1, 0x4000682e +.set CYREG_B0_UDB08_09_A1, 0x40006830 +.set CYREG_B0_UDB09_10_A1, 0x40006832 +.set CYREG_B0_UDB10_11_A1, 0x40006834 +.set CYREG_B0_UDB11_12_A1, 0x40006836 +.set CYREG_B0_UDB12_13_A1, 0x40006838 +.set CYREG_B0_UDB13_14_A1, 0x4000683a +.set CYREG_B0_UDB14_15_A1, 0x4000683c +.set CYREG_B0_UDB00_01_D0, 0x40006840 +.set CYREG_B0_UDB01_02_D0, 0x40006842 +.set CYREG_B0_UDB02_03_D0, 0x40006844 +.set CYREG_B0_UDB03_04_D0, 0x40006846 +.set CYREG_B0_UDB04_05_D0, 0x40006848 +.set CYREG_B0_UDB05_06_D0, 0x4000684a +.set CYREG_B0_UDB06_07_D0, 0x4000684c +.set CYREG_B0_UDB07_08_D0, 0x4000684e +.set CYREG_B0_UDB08_09_D0, 0x40006850 +.set CYREG_B0_UDB09_10_D0, 0x40006852 +.set CYREG_B0_UDB10_11_D0, 0x40006854 +.set CYREG_B0_UDB11_12_D0, 0x40006856 +.set CYREG_B0_UDB12_13_D0, 0x40006858 +.set CYREG_B0_UDB13_14_D0, 0x4000685a +.set CYREG_B0_UDB14_15_D0, 0x4000685c +.set CYREG_B0_UDB00_01_D1, 0x40006860 +.set CYREG_B0_UDB01_02_D1, 0x40006862 +.set CYREG_B0_UDB02_03_D1, 0x40006864 +.set CYREG_B0_UDB03_04_D1, 0x40006866 +.set CYREG_B0_UDB04_05_D1, 0x40006868 +.set CYREG_B0_UDB05_06_D1, 0x4000686a +.set CYREG_B0_UDB06_07_D1, 0x4000686c +.set CYREG_B0_UDB07_08_D1, 0x4000686e +.set CYREG_B0_UDB08_09_D1, 0x40006870 +.set CYREG_B0_UDB09_10_D1, 0x40006872 +.set CYREG_B0_UDB10_11_D1, 0x40006874 +.set CYREG_B0_UDB11_12_D1, 0x40006876 +.set CYREG_B0_UDB12_13_D1, 0x40006878 +.set CYREG_B0_UDB13_14_D1, 0x4000687a +.set CYREG_B0_UDB14_15_D1, 0x4000687c +.set CYREG_B0_UDB00_01_F0, 0x40006880 +.set CYREG_B0_UDB01_02_F0, 0x40006882 +.set CYREG_B0_UDB02_03_F0, 0x40006884 +.set CYREG_B0_UDB03_04_F0, 0x40006886 +.set CYREG_B0_UDB04_05_F0, 0x40006888 +.set CYREG_B0_UDB05_06_F0, 0x4000688a +.set CYREG_B0_UDB06_07_F0, 0x4000688c +.set CYREG_B0_UDB07_08_F0, 0x4000688e +.set CYREG_B0_UDB08_09_F0, 0x40006890 +.set CYREG_B0_UDB09_10_F0, 0x40006892 +.set CYREG_B0_UDB10_11_F0, 0x40006894 +.set CYREG_B0_UDB11_12_F0, 0x40006896 +.set CYREG_B0_UDB12_13_F0, 0x40006898 +.set CYREG_B0_UDB13_14_F0, 0x4000689a +.set CYREG_B0_UDB14_15_F0, 0x4000689c +.set CYREG_B0_UDB00_01_F1, 0x400068a0 +.set CYREG_B0_UDB01_02_F1, 0x400068a2 +.set CYREG_B0_UDB02_03_F1, 0x400068a4 +.set CYREG_B0_UDB03_04_F1, 0x400068a6 +.set CYREG_B0_UDB04_05_F1, 0x400068a8 +.set CYREG_B0_UDB05_06_F1, 0x400068aa +.set CYREG_B0_UDB06_07_F1, 0x400068ac +.set CYREG_B0_UDB07_08_F1, 0x400068ae +.set CYREG_B0_UDB08_09_F1, 0x400068b0 +.set CYREG_B0_UDB09_10_F1, 0x400068b2 +.set CYREG_B0_UDB10_11_F1, 0x400068b4 +.set CYREG_B0_UDB11_12_F1, 0x400068b6 +.set CYREG_B0_UDB12_13_F1, 0x400068b8 +.set CYREG_B0_UDB13_14_F1, 0x400068ba +.set CYREG_B0_UDB14_15_F1, 0x400068bc +.set CYREG_B0_UDB00_01_ST, 0x400068c0 +.set CYREG_B0_UDB01_02_ST, 0x400068c2 +.set CYREG_B0_UDB02_03_ST, 0x400068c4 +.set CYREG_B0_UDB03_04_ST, 0x400068c6 +.set CYREG_B0_UDB04_05_ST, 0x400068c8 +.set CYREG_B0_UDB05_06_ST, 0x400068ca +.set CYREG_B0_UDB06_07_ST, 0x400068cc +.set CYREG_B0_UDB07_08_ST, 0x400068ce +.set CYREG_B0_UDB08_09_ST, 0x400068d0 +.set CYREG_B0_UDB09_10_ST, 0x400068d2 +.set CYREG_B0_UDB10_11_ST, 0x400068d4 +.set CYREG_B0_UDB11_12_ST, 0x400068d6 +.set CYREG_B0_UDB12_13_ST, 0x400068d8 +.set CYREG_B0_UDB13_14_ST, 0x400068da +.set CYREG_B0_UDB14_15_ST, 0x400068dc +.set CYREG_B0_UDB00_01_CTL, 0x400068e0 +.set CYREG_B0_UDB01_02_CTL, 0x400068e2 +.set CYREG_B0_UDB02_03_CTL, 0x400068e4 +.set CYREG_B0_UDB03_04_CTL, 0x400068e6 +.set CYREG_B0_UDB04_05_CTL, 0x400068e8 +.set CYREG_B0_UDB05_06_CTL, 0x400068ea +.set CYREG_B0_UDB06_07_CTL, 0x400068ec +.set CYREG_B0_UDB07_08_CTL, 0x400068ee +.set CYREG_B0_UDB08_09_CTL, 0x400068f0 +.set CYREG_B0_UDB09_10_CTL, 0x400068f2 +.set CYREG_B0_UDB10_11_CTL, 0x400068f4 +.set CYREG_B0_UDB11_12_CTL, 0x400068f6 +.set CYREG_B0_UDB12_13_CTL, 0x400068f8 +.set CYREG_B0_UDB13_14_CTL, 0x400068fa +.set CYREG_B0_UDB14_15_CTL, 0x400068fc +.set CYREG_B0_UDB00_01_MSK, 0x40006900 +.set CYREG_B0_UDB01_02_MSK, 0x40006902 +.set CYREG_B0_UDB02_03_MSK, 0x40006904 +.set CYREG_B0_UDB03_04_MSK, 0x40006906 +.set CYREG_B0_UDB04_05_MSK, 0x40006908 +.set CYREG_B0_UDB05_06_MSK, 0x4000690a +.set CYREG_B0_UDB06_07_MSK, 0x4000690c +.set CYREG_B0_UDB07_08_MSK, 0x4000690e +.set CYREG_B0_UDB08_09_MSK, 0x40006910 +.set CYREG_B0_UDB09_10_MSK, 0x40006912 +.set CYREG_B0_UDB10_11_MSK, 0x40006914 +.set CYREG_B0_UDB11_12_MSK, 0x40006916 +.set CYREG_B0_UDB12_13_MSK, 0x40006918 +.set CYREG_B0_UDB13_14_MSK, 0x4000691a +.set CYREG_B0_UDB14_15_MSK, 0x4000691c +.set CYREG_B0_UDB00_01_ACTL, 0x40006920 +.set CYREG_B0_UDB01_02_ACTL, 0x40006922 +.set CYREG_B0_UDB02_03_ACTL, 0x40006924 +.set CYREG_B0_UDB03_04_ACTL, 0x40006926 +.set CYREG_B0_UDB04_05_ACTL, 0x40006928 +.set CYREG_B0_UDB05_06_ACTL, 0x4000692a +.set CYREG_B0_UDB06_07_ACTL, 0x4000692c +.set CYREG_B0_UDB07_08_ACTL, 0x4000692e +.set CYREG_B0_UDB08_09_ACTL, 0x40006930 +.set CYREG_B0_UDB09_10_ACTL, 0x40006932 +.set CYREG_B0_UDB10_11_ACTL, 0x40006934 +.set CYREG_B0_UDB11_12_ACTL, 0x40006936 +.set CYREG_B0_UDB12_13_ACTL, 0x40006938 +.set CYREG_B0_UDB13_14_ACTL, 0x4000693a +.set CYREG_B0_UDB14_15_ACTL, 0x4000693c +.set CYREG_B0_UDB00_01_MC, 0x40006940 +.set CYREG_B0_UDB01_02_MC, 0x40006942 +.set CYREG_B0_UDB02_03_MC, 0x40006944 +.set CYREG_B0_UDB03_04_MC, 0x40006946 +.set CYREG_B0_UDB04_05_MC, 0x40006948 +.set CYREG_B0_UDB05_06_MC, 0x4000694a +.set CYREG_B0_UDB06_07_MC, 0x4000694c +.set CYREG_B0_UDB07_08_MC, 0x4000694e +.set CYREG_B0_UDB08_09_MC, 0x40006950 +.set CYREG_B0_UDB09_10_MC, 0x40006952 +.set CYREG_B0_UDB10_11_MC, 0x40006954 +.set CYREG_B0_UDB11_12_MC, 0x40006956 +.set CYREG_B0_UDB12_13_MC, 0x40006958 +.set CYREG_B0_UDB13_14_MC, 0x4000695a +.set CYREG_B0_UDB14_15_MC, 0x4000695c +.set CYDEV_UWRK_UWRK16_DEF_B1_BASE, 0x40006a00 +.set CYDEV_UWRK_UWRK16_DEF_B1_SIZE, 0x0000015e +.set CYREG_B1_UDB04_05_A0, 0x40006a08 +.set CYREG_B1_UDB05_06_A0, 0x40006a0a +.set CYREG_B1_UDB06_07_A0, 0x40006a0c +.set CYREG_B1_UDB07_08_A0, 0x40006a0e +.set CYREG_B1_UDB08_09_A0, 0x40006a10 +.set CYREG_B1_UDB09_10_A0, 0x40006a12 +.set CYREG_B1_UDB10_11_A0, 0x40006a14 +.set CYREG_B1_UDB11_12_A0, 0x40006a16 +.set CYREG_B1_UDB04_05_A1, 0x40006a28 +.set CYREG_B1_UDB05_06_A1, 0x40006a2a +.set CYREG_B1_UDB06_07_A1, 0x40006a2c +.set CYREG_B1_UDB07_08_A1, 0x40006a2e +.set CYREG_B1_UDB08_09_A1, 0x40006a30 +.set CYREG_B1_UDB09_10_A1, 0x40006a32 +.set CYREG_B1_UDB10_11_A1, 0x40006a34 +.set CYREG_B1_UDB11_12_A1, 0x40006a36 +.set CYREG_B1_UDB04_05_D0, 0x40006a48 +.set CYREG_B1_UDB05_06_D0, 0x40006a4a +.set CYREG_B1_UDB06_07_D0, 0x40006a4c +.set CYREG_B1_UDB07_08_D0, 0x40006a4e +.set CYREG_B1_UDB08_09_D0, 0x40006a50 +.set CYREG_B1_UDB09_10_D0, 0x40006a52 +.set CYREG_B1_UDB10_11_D0, 0x40006a54 +.set CYREG_B1_UDB11_12_D0, 0x40006a56 +.set CYREG_B1_UDB04_05_D1, 0x40006a68 +.set CYREG_B1_UDB05_06_D1, 0x40006a6a +.set CYREG_B1_UDB06_07_D1, 0x40006a6c +.set CYREG_B1_UDB07_08_D1, 0x40006a6e +.set CYREG_B1_UDB08_09_D1, 0x40006a70 +.set CYREG_B1_UDB09_10_D1, 0x40006a72 +.set CYREG_B1_UDB10_11_D1, 0x40006a74 +.set CYREG_B1_UDB11_12_D1, 0x40006a76 +.set CYREG_B1_UDB04_05_F0, 0x40006a88 +.set CYREG_B1_UDB05_06_F0, 0x40006a8a +.set CYREG_B1_UDB06_07_F0, 0x40006a8c +.set CYREG_B1_UDB07_08_F0, 0x40006a8e +.set CYREG_B1_UDB08_09_F0, 0x40006a90 +.set CYREG_B1_UDB09_10_F0, 0x40006a92 +.set CYREG_B1_UDB10_11_F0, 0x40006a94 +.set CYREG_B1_UDB11_12_F0, 0x40006a96 +.set CYREG_B1_UDB04_05_F1, 0x40006aa8 +.set CYREG_B1_UDB05_06_F1, 0x40006aaa +.set CYREG_B1_UDB06_07_F1, 0x40006aac +.set CYREG_B1_UDB07_08_F1, 0x40006aae +.set CYREG_B1_UDB08_09_F1, 0x40006ab0 +.set CYREG_B1_UDB09_10_F1, 0x40006ab2 +.set CYREG_B1_UDB10_11_F1, 0x40006ab4 +.set CYREG_B1_UDB11_12_F1, 0x40006ab6 +.set CYREG_B1_UDB04_05_ST, 0x40006ac8 +.set CYREG_B1_UDB05_06_ST, 0x40006aca +.set CYREG_B1_UDB06_07_ST, 0x40006acc +.set CYREG_B1_UDB07_08_ST, 0x40006ace +.set CYREG_B1_UDB08_09_ST, 0x40006ad0 +.set CYREG_B1_UDB09_10_ST, 0x40006ad2 +.set CYREG_B1_UDB10_11_ST, 0x40006ad4 +.set CYREG_B1_UDB11_12_ST, 0x40006ad6 +.set CYREG_B1_UDB04_05_CTL, 0x40006ae8 +.set CYREG_B1_UDB05_06_CTL, 0x40006aea +.set CYREG_B1_UDB06_07_CTL, 0x40006aec +.set CYREG_B1_UDB07_08_CTL, 0x40006aee +.set CYREG_B1_UDB08_09_CTL, 0x40006af0 +.set CYREG_B1_UDB09_10_CTL, 0x40006af2 +.set CYREG_B1_UDB10_11_CTL, 0x40006af4 +.set CYREG_B1_UDB11_12_CTL, 0x40006af6 +.set CYREG_B1_UDB04_05_MSK, 0x40006b08 +.set CYREG_B1_UDB05_06_MSK, 0x40006b0a +.set CYREG_B1_UDB06_07_MSK, 0x40006b0c +.set CYREG_B1_UDB07_08_MSK, 0x40006b0e +.set CYREG_B1_UDB08_09_MSK, 0x40006b10 +.set CYREG_B1_UDB09_10_MSK, 0x40006b12 +.set CYREG_B1_UDB10_11_MSK, 0x40006b14 +.set CYREG_B1_UDB11_12_MSK, 0x40006b16 +.set CYREG_B1_UDB04_05_ACTL, 0x40006b28 +.set CYREG_B1_UDB05_06_ACTL, 0x40006b2a +.set CYREG_B1_UDB06_07_ACTL, 0x40006b2c +.set CYREG_B1_UDB07_08_ACTL, 0x40006b2e +.set CYREG_B1_UDB08_09_ACTL, 0x40006b30 +.set CYREG_B1_UDB09_10_ACTL, 0x40006b32 +.set CYREG_B1_UDB10_11_ACTL, 0x40006b34 +.set CYREG_B1_UDB11_12_ACTL, 0x40006b36 +.set CYREG_B1_UDB04_05_MC, 0x40006b48 +.set CYREG_B1_UDB05_06_MC, 0x40006b4a +.set CYREG_B1_UDB06_07_MC, 0x40006b4c +.set CYREG_B1_UDB07_08_MC, 0x40006b4e +.set CYREG_B1_UDB08_09_MC, 0x40006b50 +.set CYREG_B1_UDB09_10_MC, 0x40006b52 +.set CYREG_B1_UDB10_11_MC, 0x40006b54 +.set CYREG_B1_UDB11_12_MC, 0x40006b56 +.set CYDEV_PHUB_BASE, 0x40007000 +.set CYDEV_PHUB_SIZE, 0x00000c00 +.set CYREG_PHUB_CFG, 0x40007000 +.set CYREG_PHUB_ERR, 0x40007004 +.set CYREG_PHUB_ERR_ADR, 0x40007008 +.set CYDEV_PHUB_CH0_BASE, 0x40007010 +.set CYDEV_PHUB_CH0_SIZE, 0x0000000c +.set CYREG_PHUB_CH0_BASIC_CFG, 0x40007010 +.set CYREG_PHUB_CH0_ACTION, 0x40007014 +.set CYREG_PHUB_CH0_BASIC_STATUS, 0x40007018 +.set CYDEV_PHUB_CH1_BASE, 0x40007020 +.set CYDEV_PHUB_CH1_SIZE, 0x0000000c +.set CYREG_PHUB_CH1_BASIC_CFG, 0x40007020 +.set CYREG_PHUB_CH1_ACTION, 0x40007024 +.set CYREG_PHUB_CH1_BASIC_STATUS, 0x40007028 +.set CYDEV_PHUB_CH2_BASE, 0x40007030 +.set CYDEV_PHUB_CH2_SIZE, 0x0000000c +.set CYREG_PHUB_CH2_BASIC_CFG, 0x40007030 +.set CYREG_PHUB_CH2_ACTION, 0x40007034 +.set CYREG_PHUB_CH2_BASIC_STATUS, 0x40007038 +.set CYDEV_PHUB_CH3_BASE, 0x40007040 +.set CYDEV_PHUB_CH3_SIZE, 0x0000000c +.set CYREG_PHUB_CH3_BASIC_CFG, 0x40007040 +.set CYREG_PHUB_CH3_ACTION, 0x40007044 +.set CYREG_PHUB_CH3_BASIC_STATUS, 0x40007048 +.set CYDEV_PHUB_CH4_BASE, 0x40007050 +.set CYDEV_PHUB_CH4_SIZE, 0x0000000c +.set CYREG_PHUB_CH4_BASIC_CFG, 0x40007050 +.set CYREG_PHUB_CH4_ACTION, 0x40007054 +.set CYREG_PHUB_CH4_BASIC_STATUS, 0x40007058 +.set CYDEV_PHUB_CH5_BASE, 0x40007060 +.set CYDEV_PHUB_CH5_SIZE, 0x0000000c +.set CYREG_PHUB_CH5_BASIC_CFG, 0x40007060 +.set CYREG_PHUB_CH5_ACTION, 0x40007064 +.set CYREG_PHUB_CH5_BASIC_STATUS, 0x40007068 +.set CYDEV_PHUB_CH6_BASE, 0x40007070 +.set CYDEV_PHUB_CH6_SIZE, 0x0000000c +.set CYREG_PHUB_CH6_BASIC_CFG, 0x40007070 +.set CYREG_PHUB_CH6_ACTION, 0x40007074 +.set CYREG_PHUB_CH6_BASIC_STATUS, 0x40007078 +.set CYDEV_PHUB_CH7_BASE, 0x40007080 +.set CYDEV_PHUB_CH7_SIZE, 0x0000000c +.set CYREG_PHUB_CH7_BASIC_CFG, 0x40007080 +.set CYREG_PHUB_CH7_ACTION, 0x40007084 +.set CYREG_PHUB_CH7_BASIC_STATUS, 0x40007088 +.set CYDEV_PHUB_CH8_BASE, 0x40007090 +.set CYDEV_PHUB_CH8_SIZE, 0x0000000c +.set CYREG_PHUB_CH8_BASIC_CFG, 0x40007090 +.set CYREG_PHUB_CH8_ACTION, 0x40007094 +.set CYREG_PHUB_CH8_BASIC_STATUS, 0x40007098 +.set CYDEV_PHUB_CH9_BASE, 0x400070a0 +.set CYDEV_PHUB_CH9_SIZE, 0x0000000c +.set CYREG_PHUB_CH9_BASIC_CFG, 0x400070a0 +.set CYREG_PHUB_CH9_ACTION, 0x400070a4 +.set CYREG_PHUB_CH9_BASIC_STATUS, 0x400070a8 +.set CYDEV_PHUB_CH10_BASE, 0x400070b0 +.set CYDEV_PHUB_CH10_SIZE, 0x0000000c +.set CYREG_PHUB_CH10_BASIC_CFG, 0x400070b0 +.set CYREG_PHUB_CH10_ACTION, 0x400070b4 +.set CYREG_PHUB_CH10_BASIC_STATUS, 0x400070b8 +.set CYDEV_PHUB_CH11_BASE, 0x400070c0 +.set CYDEV_PHUB_CH11_SIZE, 0x0000000c +.set CYREG_PHUB_CH11_BASIC_CFG, 0x400070c0 +.set CYREG_PHUB_CH11_ACTION, 0x400070c4 +.set CYREG_PHUB_CH11_BASIC_STATUS, 0x400070c8 +.set CYDEV_PHUB_CH12_BASE, 0x400070d0 +.set CYDEV_PHUB_CH12_SIZE, 0x0000000c +.set CYREG_PHUB_CH12_BASIC_CFG, 0x400070d0 +.set CYREG_PHUB_CH12_ACTION, 0x400070d4 +.set CYREG_PHUB_CH12_BASIC_STATUS, 0x400070d8 +.set CYDEV_PHUB_CH13_BASE, 0x400070e0 +.set CYDEV_PHUB_CH13_SIZE, 0x0000000c +.set CYREG_PHUB_CH13_BASIC_CFG, 0x400070e0 +.set CYREG_PHUB_CH13_ACTION, 0x400070e4 +.set CYREG_PHUB_CH13_BASIC_STATUS, 0x400070e8 +.set CYDEV_PHUB_CH14_BASE, 0x400070f0 +.set CYDEV_PHUB_CH14_SIZE, 0x0000000c +.set CYREG_PHUB_CH14_BASIC_CFG, 0x400070f0 +.set CYREG_PHUB_CH14_ACTION, 0x400070f4 +.set CYREG_PHUB_CH14_BASIC_STATUS, 0x400070f8 +.set CYDEV_PHUB_CH15_BASE, 0x40007100 +.set CYDEV_PHUB_CH15_SIZE, 0x0000000c +.set CYREG_PHUB_CH15_BASIC_CFG, 0x40007100 +.set CYREG_PHUB_CH15_ACTION, 0x40007104 +.set CYREG_PHUB_CH15_BASIC_STATUS, 0x40007108 +.set CYDEV_PHUB_CH16_BASE, 0x40007110 +.set CYDEV_PHUB_CH16_SIZE, 0x0000000c +.set CYREG_PHUB_CH16_BASIC_CFG, 0x40007110 +.set CYREG_PHUB_CH16_ACTION, 0x40007114 +.set CYREG_PHUB_CH16_BASIC_STATUS, 0x40007118 +.set CYDEV_PHUB_CH17_BASE, 0x40007120 +.set CYDEV_PHUB_CH17_SIZE, 0x0000000c +.set CYREG_PHUB_CH17_BASIC_CFG, 0x40007120 +.set CYREG_PHUB_CH17_ACTION, 0x40007124 +.set CYREG_PHUB_CH17_BASIC_STATUS, 0x40007128 +.set CYDEV_PHUB_CH18_BASE, 0x40007130 +.set CYDEV_PHUB_CH18_SIZE, 0x0000000c +.set CYREG_PHUB_CH18_BASIC_CFG, 0x40007130 +.set CYREG_PHUB_CH18_ACTION, 0x40007134 +.set CYREG_PHUB_CH18_BASIC_STATUS, 0x40007138 +.set CYDEV_PHUB_CH19_BASE, 0x40007140 +.set CYDEV_PHUB_CH19_SIZE, 0x0000000c +.set CYREG_PHUB_CH19_BASIC_CFG, 0x40007140 +.set CYREG_PHUB_CH19_ACTION, 0x40007144 +.set CYREG_PHUB_CH19_BASIC_STATUS, 0x40007148 +.set CYDEV_PHUB_CH20_BASE, 0x40007150 +.set CYDEV_PHUB_CH20_SIZE, 0x0000000c +.set CYREG_PHUB_CH20_BASIC_CFG, 0x40007150 +.set CYREG_PHUB_CH20_ACTION, 0x40007154 +.set CYREG_PHUB_CH20_BASIC_STATUS, 0x40007158 +.set CYDEV_PHUB_CH21_BASE, 0x40007160 +.set CYDEV_PHUB_CH21_SIZE, 0x0000000c +.set CYREG_PHUB_CH21_BASIC_CFG, 0x40007160 +.set CYREG_PHUB_CH21_ACTION, 0x40007164 +.set CYREG_PHUB_CH21_BASIC_STATUS, 0x40007168 +.set CYDEV_PHUB_CH22_BASE, 0x40007170 +.set CYDEV_PHUB_CH22_SIZE, 0x0000000c +.set CYREG_PHUB_CH22_BASIC_CFG, 0x40007170 +.set CYREG_PHUB_CH22_ACTION, 0x40007174 +.set CYREG_PHUB_CH22_BASIC_STATUS, 0x40007178 +.set CYDEV_PHUB_CH23_BASE, 0x40007180 +.set CYDEV_PHUB_CH23_SIZE, 0x0000000c +.set CYREG_PHUB_CH23_BASIC_CFG, 0x40007180 +.set CYREG_PHUB_CH23_ACTION, 0x40007184 +.set CYREG_PHUB_CH23_BASIC_STATUS, 0x40007188 +.set CYDEV_PHUB_CFGMEM0_BASE, 0x40007600 +.set CYDEV_PHUB_CFGMEM0_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM0_CFG0, 0x40007600 +.set CYREG_PHUB_CFGMEM0_CFG1, 0x40007604 +.set CYDEV_PHUB_CFGMEM1_BASE, 0x40007608 +.set CYDEV_PHUB_CFGMEM1_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM1_CFG0, 0x40007608 +.set CYREG_PHUB_CFGMEM1_CFG1, 0x4000760c +.set CYDEV_PHUB_CFGMEM2_BASE, 0x40007610 +.set CYDEV_PHUB_CFGMEM2_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM2_CFG0, 0x40007610 +.set CYREG_PHUB_CFGMEM2_CFG1, 0x40007614 +.set CYDEV_PHUB_CFGMEM3_BASE, 0x40007618 +.set CYDEV_PHUB_CFGMEM3_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM3_CFG0, 0x40007618 +.set CYREG_PHUB_CFGMEM3_CFG1, 0x4000761c +.set CYDEV_PHUB_CFGMEM4_BASE, 0x40007620 +.set CYDEV_PHUB_CFGMEM4_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM4_CFG0, 0x40007620 +.set CYREG_PHUB_CFGMEM4_CFG1, 0x40007624 +.set CYDEV_PHUB_CFGMEM5_BASE, 0x40007628 +.set CYDEV_PHUB_CFGMEM5_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM5_CFG0, 0x40007628 +.set CYREG_PHUB_CFGMEM5_CFG1, 0x4000762c +.set CYDEV_PHUB_CFGMEM6_BASE, 0x40007630 +.set CYDEV_PHUB_CFGMEM6_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM6_CFG0, 0x40007630 +.set CYREG_PHUB_CFGMEM6_CFG1, 0x40007634 +.set CYDEV_PHUB_CFGMEM7_BASE, 0x40007638 +.set CYDEV_PHUB_CFGMEM7_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM7_CFG0, 0x40007638 +.set CYREG_PHUB_CFGMEM7_CFG1, 0x4000763c +.set CYDEV_PHUB_CFGMEM8_BASE, 0x40007640 +.set CYDEV_PHUB_CFGMEM8_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM8_CFG0, 0x40007640 +.set CYREG_PHUB_CFGMEM8_CFG1, 0x40007644 +.set CYDEV_PHUB_CFGMEM9_BASE, 0x40007648 +.set CYDEV_PHUB_CFGMEM9_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM9_CFG0, 0x40007648 +.set CYREG_PHUB_CFGMEM9_CFG1, 0x4000764c +.set CYDEV_PHUB_CFGMEM10_BASE, 0x40007650 +.set CYDEV_PHUB_CFGMEM10_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM10_CFG0, 0x40007650 +.set CYREG_PHUB_CFGMEM10_CFG1, 0x40007654 +.set CYDEV_PHUB_CFGMEM11_BASE, 0x40007658 +.set CYDEV_PHUB_CFGMEM11_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM11_CFG0, 0x40007658 +.set CYREG_PHUB_CFGMEM11_CFG1, 0x4000765c +.set CYDEV_PHUB_CFGMEM12_BASE, 0x40007660 +.set CYDEV_PHUB_CFGMEM12_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM12_CFG0, 0x40007660 +.set CYREG_PHUB_CFGMEM12_CFG1, 0x40007664 +.set CYDEV_PHUB_CFGMEM13_BASE, 0x40007668 +.set CYDEV_PHUB_CFGMEM13_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM13_CFG0, 0x40007668 +.set CYREG_PHUB_CFGMEM13_CFG1, 0x4000766c +.set CYDEV_PHUB_CFGMEM14_BASE, 0x40007670 +.set CYDEV_PHUB_CFGMEM14_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM14_CFG0, 0x40007670 +.set CYREG_PHUB_CFGMEM14_CFG1, 0x40007674 +.set CYDEV_PHUB_CFGMEM15_BASE, 0x40007678 +.set CYDEV_PHUB_CFGMEM15_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM15_CFG0, 0x40007678 +.set CYREG_PHUB_CFGMEM15_CFG1, 0x4000767c +.set CYDEV_PHUB_CFGMEM16_BASE, 0x40007680 +.set CYDEV_PHUB_CFGMEM16_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM16_CFG0, 0x40007680 +.set CYREG_PHUB_CFGMEM16_CFG1, 0x40007684 +.set CYDEV_PHUB_CFGMEM17_BASE, 0x40007688 +.set CYDEV_PHUB_CFGMEM17_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM17_CFG0, 0x40007688 +.set CYREG_PHUB_CFGMEM17_CFG1, 0x4000768c +.set CYDEV_PHUB_CFGMEM18_BASE, 0x40007690 +.set CYDEV_PHUB_CFGMEM18_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM18_CFG0, 0x40007690 +.set CYREG_PHUB_CFGMEM18_CFG1, 0x40007694 +.set CYDEV_PHUB_CFGMEM19_BASE, 0x40007698 +.set CYDEV_PHUB_CFGMEM19_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM19_CFG0, 0x40007698 +.set CYREG_PHUB_CFGMEM19_CFG1, 0x4000769c +.set CYDEV_PHUB_CFGMEM20_BASE, 0x400076a0 +.set CYDEV_PHUB_CFGMEM20_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM20_CFG0, 0x400076a0 +.set CYREG_PHUB_CFGMEM20_CFG1, 0x400076a4 +.set CYDEV_PHUB_CFGMEM21_BASE, 0x400076a8 +.set CYDEV_PHUB_CFGMEM21_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM21_CFG0, 0x400076a8 +.set CYREG_PHUB_CFGMEM21_CFG1, 0x400076ac +.set CYDEV_PHUB_CFGMEM22_BASE, 0x400076b0 +.set CYDEV_PHUB_CFGMEM22_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM22_CFG0, 0x400076b0 +.set CYREG_PHUB_CFGMEM22_CFG1, 0x400076b4 +.set CYDEV_PHUB_CFGMEM23_BASE, 0x400076b8 +.set CYDEV_PHUB_CFGMEM23_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM23_CFG0, 0x400076b8 +.set CYREG_PHUB_CFGMEM23_CFG1, 0x400076bc +.set CYDEV_PHUB_TDMEM0_BASE, 0x40007800 +.set CYDEV_PHUB_TDMEM0_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM0_ORIG_TD0, 0x40007800 +.set CYREG_PHUB_TDMEM0_ORIG_TD1, 0x40007804 +.set CYDEV_PHUB_TDMEM1_BASE, 0x40007808 +.set CYDEV_PHUB_TDMEM1_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM1_ORIG_TD0, 0x40007808 +.set CYREG_PHUB_TDMEM1_ORIG_TD1, 0x4000780c +.set CYDEV_PHUB_TDMEM2_BASE, 0x40007810 +.set CYDEV_PHUB_TDMEM2_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM2_ORIG_TD0, 0x40007810 +.set CYREG_PHUB_TDMEM2_ORIG_TD1, 0x40007814 +.set CYDEV_PHUB_TDMEM3_BASE, 0x40007818 +.set CYDEV_PHUB_TDMEM3_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM3_ORIG_TD0, 0x40007818 +.set CYREG_PHUB_TDMEM3_ORIG_TD1, 0x4000781c +.set CYDEV_PHUB_TDMEM4_BASE, 0x40007820 +.set CYDEV_PHUB_TDMEM4_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM4_ORIG_TD0, 0x40007820 +.set CYREG_PHUB_TDMEM4_ORIG_TD1, 0x40007824 +.set CYDEV_PHUB_TDMEM5_BASE, 0x40007828 +.set CYDEV_PHUB_TDMEM5_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM5_ORIG_TD0, 0x40007828 +.set CYREG_PHUB_TDMEM5_ORIG_TD1, 0x4000782c +.set CYDEV_PHUB_TDMEM6_BASE, 0x40007830 +.set CYDEV_PHUB_TDMEM6_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM6_ORIG_TD0, 0x40007830 +.set CYREG_PHUB_TDMEM6_ORIG_TD1, 0x40007834 +.set CYDEV_PHUB_TDMEM7_BASE, 0x40007838 +.set CYDEV_PHUB_TDMEM7_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM7_ORIG_TD0, 0x40007838 +.set CYREG_PHUB_TDMEM7_ORIG_TD1, 0x4000783c +.set CYDEV_PHUB_TDMEM8_BASE, 0x40007840 +.set CYDEV_PHUB_TDMEM8_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM8_ORIG_TD0, 0x40007840 +.set CYREG_PHUB_TDMEM8_ORIG_TD1, 0x40007844 +.set CYDEV_PHUB_TDMEM9_BASE, 0x40007848 +.set CYDEV_PHUB_TDMEM9_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM9_ORIG_TD0, 0x40007848 +.set CYREG_PHUB_TDMEM9_ORIG_TD1, 0x4000784c +.set CYDEV_PHUB_TDMEM10_BASE, 0x40007850 +.set CYDEV_PHUB_TDMEM10_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM10_ORIG_TD0, 0x40007850 +.set CYREG_PHUB_TDMEM10_ORIG_TD1, 0x40007854 +.set CYDEV_PHUB_TDMEM11_BASE, 0x40007858 +.set CYDEV_PHUB_TDMEM11_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM11_ORIG_TD0, 0x40007858 +.set CYREG_PHUB_TDMEM11_ORIG_TD1, 0x4000785c +.set CYDEV_PHUB_TDMEM12_BASE, 0x40007860 +.set CYDEV_PHUB_TDMEM12_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM12_ORIG_TD0, 0x40007860 +.set CYREG_PHUB_TDMEM12_ORIG_TD1, 0x40007864 +.set CYDEV_PHUB_TDMEM13_BASE, 0x40007868 +.set CYDEV_PHUB_TDMEM13_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM13_ORIG_TD0, 0x40007868 +.set CYREG_PHUB_TDMEM13_ORIG_TD1, 0x4000786c +.set CYDEV_PHUB_TDMEM14_BASE, 0x40007870 +.set CYDEV_PHUB_TDMEM14_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM14_ORIG_TD0, 0x40007870 +.set CYREG_PHUB_TDMEM14_ORIG_TD1, 0x40007874 +.set CYDEV_PHUB_TDMEM15_BASE, 0x40007878 +.set CYDEV_PHUB_TDMEM15_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM15_ORIG_TD0, 0x40007878 +.set CYREG_PHUB_TDMEM15_ORIG_TD1, 0x4000787c +.set CYDEV_PHUB_TDMEM16_BASE, 0x40007880 +.set CYDEV_PHUB_TDMEM16_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM16_ORIG_TD0, 0x40007880 +.set CYREG_PHUB_TDMEM16_ORIG_TD1, 0x40007884 +.set CYDEV_PHUB_TDMEM17_BASE, 0x40007888 +.set CYDEV_PHUB_TDMEM17_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM17_ORIG_TD0, 0x40007888 +.set CYREG_PHUB_TDMEM17_ORIG_TD1, 0x4000788c +.set CYDEV_PHUB_TDMEM18_BASE, 0x40007890 +.set CYDEV_PHUB_TDMEM18_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM18_ORIG_TD0, 0x40007890 +.set CYREG_PHUB_TDMEM18_ORIG_TD1, 0x40007894 +.set CYDEV_PHUB_TDMEM19_BASE, 0x40007898 +.set CYDEV_PHUB_TDMEM19_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM19_ORIG_TD0, 0x40007898 +.set CYREG_PHUB_TDMEM19_ORIG_TD1, 0x4000789c +.set CYDEV_PHUB_TDMEM20_BASE, 0x400078a0 +.set CYDEV_PHUB_TDMEM20_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM20_ORIG_TD0, 0x400078a0 +.set CYREG_PHUB_TDMEM20_ORIG_TD1, 0x400078a4 +.set CYDEV_PHUB_TDMEM21_BASE, 0x400078a8 +.set CYDEV_PHUB_TDMEM21_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM21_ORIG_TD0, 0x400078a8 +.set CYREG_PHUB_TDMEM21_ORIG_TD1, 0x400078ac +.set CYDEV_PHUB_TDMEM22_BASE, 0x400078b0 +.set CYDEV_PHUB_TDMEM22_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM22_ORIG_TD0, 0x400078b0 +.set CYREG_PHUB_TDMEM22_ORIG_TD1, 0x400078b4 +.set CYDEV_PHUB_TDMEM23_BASE, 0x400078b8 +.set CYDEV_PHUB_TDMEM23_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM23_ORIG_TD0, 0x400078b8 +.set CYREG_PHUB_TDMEM23_ORIG_TD1, 0x400078bc +.set CYDEV_PHUB_TDMEM24_BASE, 0x400078c0 +.set CYDEV_PHUB_TDMEM24_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM24_ORIG_TD0, 0x400078c0 +.set CYREG_PHUB_TDMEM24_ORIG_TD1, 0x400078c4 +.set CYDEV_PHUB_TDMEM25_BASE, 0x400078c8 +.set CYDEV_PHUB_TDMEM25_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM25_ORIG_TD0, 0x400078c8 +.set CYREG_PHUB_TDMEM25_ORIG_TD1, 0x400078cc +.set CYDEV_PHUB_TDMEM26_BASE, 0x400078d0 +.set CYDEV_PHUB_TDMEM26_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM26_ORIG_TD0, 0x400078d0 +.set CYREG_PHUB_TDMEM26_ORIG_TD1, 0x400078d4 +.set CYDEV_PHUB_TDMEM27_BASE, 0x400078d8 +.set CYDEV_PHUB_TDMEM27_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM27_ORIG_TD0, 0x400078d8 +.set CYREG_PHUB_TDMEM27_ORIG_TD1, 0x400078dc +.set CYDEV_PHUB_TDMEM28_BASE, 0x400078e0 +.set CYDEV_PHUB_TDMEM28_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM28_ORIG_TD0, 0x400078e0 +.set CYREG_PHUB_TDMEM28_ORIG_TD1, 0x400078e4 +.set CYDEV_PHUB_TDMEM29_BASE, 0x400078e8 +.set CYDEV_PHUB_TDMEM29_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM29_ORIG_TD0, 0x400078e8 +.set CYREG_PHUB_TDMEM29_ORIG_TD1, 0x400078ec +.set CYDEV_PHUB_TDMEM30_BASE, 0x400078f0 +.set CYDEV_PHUB_TDMEM30_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM30_ORIG_TD0, 0x400078f0 +.set CYREG_PHUB_TDMEM30_ORIG_TD1, 0x400078f4 +.set CYDEV_PHUB_TDMEM31_BASE, 0x400078f8 +.set CYDEV_PHUB_TDMEM31_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM31_ORIG_TD0, 0x400078f8 +.set CYREG_PHUB_TDMEM31_ORIG_TD1, 0x400078fc +.set CYDEV_PHUB_TDMEM32_BASE, 0x40007900 +.set CYDEV_PHUB_TDMEM32_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM32_ORIG_TD0, 0x40007900 +.set CYREG_PHUB_TDMEM32_ORIG_TD1, 0x40007904 +.set CYDEV_PHUB_TDMEM33_BASE, 0x40007908 +.set CYDEV_PHUB_TDMEM33_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM33_ORIG_TD0, 0x40007908 +.set CYREG_PHUB_TDMEM33_ORIG_TD1, 0x4000790c +.set CYDEV_PHUB_TDMEM34_BASE, 0x40007910 +.set CYDEV_PHUB_TDMEM34_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM34_ORIG_TD0, 0x40007910 +.set CYREG_PHUB_TDMEM34_ORIG_TD1, 0x40007914 +.set CYDEV_PHUB_TDMEM35_BASE, 0x40007918 +.set CYDEV_PHUB_TDMEM35_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM35_ORIG_TD0, 0x40007918 +.set CYREG_PHUB_TDMEM35_ORIG_TD1, 0x4000791c +.set CYDEV_PHUB_TDMEM36_BASE, 0x40007920 +.set CYDEV_PHUB_TDMEM36_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM36_ORIG_TD0, 0x40007920 +.set CYREG_PHUB_TDMEM36_ORIG_TD1, 0x40007924 +.set CYDEV_PHUB_TDMEM37_BASE, 0x40007928 +.set CYDEV_PHUB_TDMEM37_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM37_ORIG_TD0, 0x40007928 +.set CYREG_PHUB_TDMEM37_ORIG_TD1, 0x4000792c +.set CYDEV_PHUB_TDMEM38_BASE, 0x40007930 +.set CYDEV_PHUB_TDMEM38_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM38_ORIG_TD0, 0x40007930 +.set CYREG_PHUB_TDMEM38_ORIG_TD1, 0x40007934 +.set CYDEV_PHUB_TDMEM39_BASE, 0x40007938 +.set CYDEV_PHUB_TDMEM39_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM39_ORIG_TD0, 0x40007938 +.set CYREG_PHUB_TDMEM39_ORIG_TD1, 0x4000793c +.set CYDEV_PHUB_TDMEM40_BASE, 0x40007940 +.set CYDEV_PHUB_TDMEM40_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM40_ORIG_TD0, 0x40007940 +.set CYREG_PHUB_TDMEM40_ORIG_TD1, 0x40007944 +.set CYDEV_PHUB_TDMEM41_BASE, 0x40007948 +.set CYDEV_PHUB_TDMEM41_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM41_ORIG_TD0, 0x40007948 +.set CYREG_PHUB_TDMEM41_ORIG_TD1, 0x4000794c +.set CYDEV_PHUB_TDMEM42_BASE, 0x40007950 +.set CYDEV_PHUB_TDMEM42_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM42_ORIG_TD0, 0x40007950 +.set CYREG_PHUB_TDMEM42_ORIG_TD1, 0x40007954 +.set CYDEV_PHUB_TDMEM43_BASE, 0x40007958 +.set CYDEV_PHUB_TDMEM43_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM43_ORIG_TD0, 0x40007958 +.set CYREG_PHUB_TDMEM43_ORIG_TD1, 0x4000795c +.set CYDEV_PHUB_TDMEM44_BASE, 0x40007960 +.set CYDEV_PHUB_TDMEM44_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM44_ORIG_TD0, 0x40007960 +.set CYREG_PHUB_TDMEM44_ORIG_TD1, 0x40007964 +.set CYDEV_PHUB_TDMEM45_BASE, 0x40007968 +.set CYDEV_PHUB_TDMEM45_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM45_ORIG_TD0, 0x40007968 +.set CYREG_PHUB_TDMEM45_ORIG_TD1, 0x4000796c +.set CYDEV_PHUB_TDMEM46_BASE, 0x40007970 +.set CYDEV_PHUB_TDMEM46_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM46_ORIG_TD0, 0x40007970 +.set CYREG_PHUB_TDMEM46_ORIG_TD1, 0x40007974 +.set CYDEV_PHUB_TDMEM47_BASE, 0x40007978 +.set CYDEV_PHUB_TDMEM47_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM47_ORIG_TD0, 0x40007978 +.set CYREG_PHUB_TDMEM47_ORIG_TD1, 0x4000797c +.set CYDEV_PHUB_TDMEM48_BASE, 0x40007980 +.set CYDEV_PHUB_TDMEM48_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM48_ORIG_TD0, 0x40007980 +.set CYREG_PHUB_TDMEM48_ORIG_TD1, 0x40007984 +.set CYDEV_PHUB_TDMEM49_BASE, 0x40007988 +.set CYDEV_PHUB_TDMEM49_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM49_ORIG_TD0, 0x40007988 +.set CYREG_PHUB_TDMEM49_ORIG_TD1, 0x4000798c +.set CYDEV_PHUB_TDMEM50_BASE, 0x40007990 +.set CYDEV_PHUB_TDMEM50_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM50_ORIG_TD0, 0x40007990 +.set CYREG_PHUB_TDMEM50_ORIG_TD1, 0x40007994 +.set CYDEV_PHUB_TDMEM51_BASE, 0x40007998 +.set CYDEV_PHUB_TDMEM51_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM51_ORIG_TD0, 0x40007998 +.set CYREG_PHUB_TDMEM51_ORIG_TD1, 0x4000799c +.set CYDEV_PHUB_TDMEM52_BASE, 0x400079a0 +.set CYDEV_PHUB_TDMEM52_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM52_ORIG_TD0, 0x400079a0 +.set CYREG_PHUB_TDMEM52_ORIG_TD1, 0x400079a4 +.set CYDEV_PHUB_TDMEM53_BASE, 0x400079a8 +.set CYDEV_PHUB_TDMEM53_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM53_ORIG_TD0, 0x400079a8 +.set CYREG_PHUB_TDMEM53_ORIG_TD1, 0x400079ac +.set CYDEV_PHUB_TDMEM54_BASE, 0x400079b0 +.set CYDEV_PHUB_TDMEM54_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM54_ORIG_TD0, 0x400079b0 +.set CYREG_PHUB_TDMEM54_ORIG_TD1, 0x400079b4 +.set CYDEV_PHUB_TDMEM55_BASE, 0x400079b8 +.set CYDEV_PHUB_TDMEM55_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM55_ORIG_TD0, 0x400079b8 +.set CYREG_PHUB_TDMEM55_ORIG_TD1, 0x400079bc +.set CYDEV_PHUB_TDMEM56_BASE, 0x400079c0 +.set CYDEV_PHUB_TDMEM56_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM56_ORIG_TD0, 0x400079c0 +.set CYREG_PHUB_TDMEM56_ORIG_TD1, 0x400079c4 +.set CYDEV_PHUB_TDMEM57_BASE, 0x400079c8 +.set CYDEV_PHUB_TDMEM57_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM57_ORIG_TD0, 0x400079c8 +.set CYREG_PHUB_TDMEM57_ORIG_TD1, 0x400079cc +.set CYDEV_PHUB_TDMEM58_BASE, 0x400079d0 +.set CYDEV_PHUB_TDMEM58_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM58_ORIG_TD0, 0x400079d0 +.set CYREG_PHUB_TDMEM58_ORIG_TD1, 0x400079d4 +.set CYDEV_PHUB_TDMEM59_BASE, 0x400079d8 +.set CYDEV_PHUB_TDMEM59_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM59_ORIG_TD0, 0x400079d8 +.set CYREG_PHUB_TDMEM59_ORIG_TD1, 0x400079dc +.set CYDEV_PHUB_TDMEM60_BASE, 0x400079e0 +.set CYDEV_PHUB_TDMEM60_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM60_ORIG_TD0, 0x400079e0 +.set CYREG_PHUB_TDMEM60_ORIG_TD1, 0x400079e4 +.set CYDEV_PHUB_TDMEM61_BASE, 0x400079e8 +.set CYDEV_PHUB_TDMEM61_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM61_ORIG_TD0, 0x400079e8 +.set CYREG_PHUB_TDMEM61_ORIG_TD1, 0x400079ec +.set CYDEV_PHUB_TDMEM62_BASE, 0x400079f0 +.set CYDEV_PHUB_TDMEM62_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM62_ORIG_TD0, 0x400079f0 +.set CYREG_PHUB_TDMEM62_ORIG_TD1, 0x400079f4 +.set CYDEV_PHUB_TDMEM63_BASE, 0x400079f8 +.set CYDEV_PHUB_TDMEM63_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM63_ORIG_TD0, 0x400079f8 +.set CYREG_PHUB_TDMEM63_ORIG_TD1, 0x400079fc +.set CYDEV_PHUB_TDMEM64_BASE, 0x40007a00 +.set CYDEV_PHUB_TDMEM64_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM64_ORIG_TD0, 0x40007a00 +.set CYREG_PHUB_TDMEM64_ORIG_TD1, 0x40007a04 +.set CYDEV_PHUB_TDMEM65_BASE, 0x40007a08 +.set CYDEV_PHUB_TDMEM65_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM65_ORIG_TD0, 0x40007a08 +.set CYREG_PHUB_TDMEM65_ORIG_TD1, 0x40007a0c +.set CYDEV_PHUB_TDMEM66_BASE, 0x40007a10 +.set CYDEV_PHUB_TDMEM66_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM66_ORIG_TD0, 0x40007a10 +.set CYREG_PHUB_TDMEM66_ORIG_TD1, 0x40007a14 +.set CYDEV_PHUB_TDMEM67_BASE, 0x40007a18 +.set CYDEV_PHUB_TDMEM67_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM67_ORIG_TD0, 0x40007a18 +.set CYREG_PHUB_TDMEM67_ORIG_TD1, 0x40007a1c +.set CYDEV_PHUB_TDMEM68_BASE, 0x40007a20 +.set CYDEV_PHUB_TDMEM68_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM68_ORIG_TD0, 0x40007a20 +.set CYREG_PHUB_TDMEM68_ORIG_TD1, 0x40007a24 +.set CYDEV_PHUB_TDMEM69_BASE, 0x40007a28 +.set CYDEV_PHUB_TDMEM69_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM69_ORIG_TD0, 0x40007a28 +.set CYREG_PHUB_TDMEM69_ORIG_TD1, 0x40007a2c +.set CYDEV_PHUB_TDMEM70_BASE, 0x40007a30 +.set CYDEV_PHUB_TDMEM70_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM70_ORIG_TD0, 0x40007a30 +.set CYREG_PHUB_TDMEM70_ORIG_TD1, 0x40007a34 +.set CYDEV_PHUB_TDMEM71_BASE, 0x40007a38 +.set CYDEV_PHUB_TDMEM71_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM71_ORIG_TD0, 0x40007a38 +.set CYREG_PHUB_TDMEM71_ORIG_TD1, 0x40007a3c +.set CYDEV_PHUB_TDMEM72_BASE, 0x40007a40 +.set CYDEV_PHUB_TDMEM72_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM72_ORIG_TD0, 0x40007a40 +.set CYREG_PHUB_TDMEM72_ORIG_TD1, 0x40007a44 +.set CYDEV_PHUB_TDMEM73_BASE, 0x40007a48 +.set CYDEV_PHUB_TDMEM73_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM73_ORIG_TD0, 0x40007a48 +.set CYREG_PHUB_TDMEM73_ORIG_TD1, 0x40007a4c +.set CYDEV_PHUB_TDMEM74_BASE, 0x40007a50 +.set CYDEV_PHUB_TDMEM74_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM74_ORIG_TD0, 0x40007a50 +.set CYREG_PHUB_TDMEM74_ORIG_TD1, 0x40007a54 +.set CYDEV_PHUB_TDMEM75_BASE, 0x40007a58 +.set CYDEV_PHUB_TDMEM75_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM75_ORIG_TD0, 0x40007a58 +.set CYREG_PHUB_TDMEM75_ORIG_TD1, 0x40007a5c +.set CYDEV_PHUB_TDMEM76_BASE, 0x40007a60 +.set CYDEV_PHUB_TDMEM76_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM76_ORIG_TD0, 0x40007a60 +.set CYREG_PHUB_TDMEM76_ORIG_TD1, 0x40007a64 +.set CYDEV_PHUB_TDMEM77_BASE, 0x40007a68 +.set CYDEV_PHUB_TDMEM77_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM77_ORIG_TD0, 0x40007a68 +.set CYREG_PHUB_TDMEM77_ORIG_TD1, 0x40007a6c +.set CYDEV_PHUB_TDMEM78_BASE, 0x40007a70 +.set CYDEV_PHUB_TDMEM78_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM78_ORIG_TD0, 0x40007a70 +.set CYREG_PHUB_TDMEM78_ORIG_TD1, 0x40007a74 +.set CYDEV_PHUB_TDMEM79_BASE, 0x40007a78 +.set CYDEV_PHUB_TDMEM79_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM79_ORIG_TD0, 0x40007a78 +.set CYREG_PHUB_TDMEM79_ORIG_TD1, 0x40007a7c +.set CYDEV_PHUB_TDMEM80_BASE, 0x40007a80 +.set CYDEV_PHUB_TDMEM80_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM80_ORIG_TD0, 0x40007a80 +.set CYREG_PHUB_TDMEM80_ORIG_TD1, 0x40007a84 +.set CYDEV_PHUB_TDMEM81_BASE, 0x40007a88 +.set CYDEV_PHUB_TDMEM81_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM81_ORIG_TD0, 0x40007a88 +.set CYREG_PHUB_TDMEM81_ORIG_TD1, 0x40007a8c +.set CYDEV_PHUB_TDMEM82_BASE, 0x40007a90 +.set CYDEV_PHUB_TDMEM82_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM82_ORIG_TD0, 0x40007a90 +.set CYREG_PHUB_TDMEM82_ORIG_TD1, 0x40007a94 +.set CYDEV_PHUB_TDMEM83_BASE, 0x40007a98 +.set CYDEV_PHUB_TDMEM83_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM83_ORIG_TD0, 0x40007a98 +.set CYREG_PHUB_TDMEM83_ORIG_TD1, 0x40007a9c +.set CYDEV_PHUB_TDMEM84_BASE, 0x40007aa0 +.set CYDEV_PHUB_TDMEM84_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM84_ORIG_TD0, 0x40007aa0 +.set CYREG_PHUB_TDMEM84_ORIG_TD1, 0x40007aa4 +.set CYDEV_PHUB_TDMEM85_BASE, 0x40007aa8 +.set CYDEV_PHUB_TDMEM85_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM85_ORIG_TD0, 0x40007aa8 +.set CYREG_PHUB_TDMEM85_ORIG_TD1, 0x40007aac +.set CYDEV_PHUB_TDMEM86_BASE, 0x40007ab0 +.set CYDEV_PHUB_TDMEM86_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM86_ORIG_TD0, 0x40007ab0 +.set CYREG_PHUB_TDMEM86_ORIG_TD1, 0x40007ab4 +.set CYDEV_PHUB_TDMEM87_BASE, 0x40007ab8 +.set CYDEV_PHUB_TDMEM87_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM87_ORIG_TD0, 0x40007ab8 +.set CYREG_PHUB_TDMEM87_ORIG_TD1, 0x40007abc +.set CYDEV_PHUB_TDMEM88_BASE, 0x40007ac0 +.set CYDEV_PHUB_TDMEM88_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM88_ORIG_TD0, 0x40007ac0 +.set CYREG_PHUB_TDMEM88_ORIG_TD1, 0x40007ac4 +.set CYDEV_PHUB_TDMEM89_BASE, 0x40007ac8 +.set CYDEV_PHUB_TDMEM89_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM89_ORIG_TD0, 0x40007ac8 +.set CYREG_PHUB_TDMEM89_ORIG_TD1, 0x40007acc +.set CYDEV_PHUB_TDMEM90_BASE, 0x40007ad0 +.set CYDEV_PHUB_TDMEM90_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM90_ORIG_TD0, 0x40007ad0 +.set CYREG_PHUB_TDMEM90_ORIG_TD1, 0x40007ad4 +.set CYDEV_PHUB_TDMEM91_BASE, 0x40007ad8 +.set CYDEV_PHUB_TDMEM91_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM91_ORIG_TD0, 0x40007ad8 +.set CYREG_PHUB_TDMEM91_ORIG_TD1, 0x40007adc +.set CYDEV_PHUB_TDMEM92_BASE, 0x40007ae0 +.set CYDEV_PHUB_TDMEM92_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM92_ORIG_TD0, 0x40007ae0 +.set CYREG_PHUB_TDMEM92_ORIG_TD1, 0x40007ae4 +.set CYDEV_PHUB_TDMEM93_BASE, 0x40007ae8 +.set CYDEV_PHUB_TDMEM93_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM93_ORIG_TD0, 0x40007ae8 +.set CYREG_PHUB_TDMEM93_ORIG_TD1, 0x40007aec +.set CYDEV_PHUB_TDMEM94_BASE, 0x40007af0 +.set CYDEV_PHUB_TDMEM94_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM94_ORIG_TD0, 0x40007af0 +.set CYREG_PHUB_TDMEM94_ORIG_TD1, 0x40007af4 +.set CYDEV_PHUB_TDMEM95_BASE, 0x40007af8 +.set CYDEV_PHUB_TDMEM95_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM95_ORIG_TD0, 0x40007af8 +.set CYREG_PHUB_TDMEM95_ORIG_TD1, 0x40007afc +.set CYDEV_PHUB_TDMEM96_BASE, 0x40007b00 +.set CYDEV_PHUB_TDMEM96_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM96_ORIG_TD0, 0x40007b00 +.set CYREG_PHUB_TDMEM96_ORIG_TD1, 0x40007b04 +.set CYDEV_PHUB_TDMEM97_BASE, 0x40007b08 +.set CYDEV_PHUB_TDMEM97_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM97_ORIG_TD0, 0x40007b08 +.set CYREG_PHUB_TDMEM97_ORIG_TD1, 0x40007b0c +.set CYDEV_PHUB_TDMEM98_BASE, 0x40007b10 +.set CYDEV_PHUB_TDMEM98_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM98_ORIG_TD0, 0x40007b10 +.set CYREG_PHUB_TDMEM98_ORIG_TD1, 0x40007b14 +.set CYDEV_PHUB_TDMEM99_BASE, 0x40007b18 +.set CYDEV_PHUB_TDMEM99_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM99_ORIG_TD0, 0x40007b18 +.set CYREG_PHUB_TDMEM99_ORIG_TD1, 0x40007b1c +.set CYDEV_PHUB_TDMEM100_BASE, 0x40007b20 +.set CYDEV_PHUB_TDMEM100_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM100_ORIG_TD0, 0x40007b20 +.set CYREG_PHUB_TDMEM100_ORIG_TD1, 0x40007b24 +.set CYDEV_PHUB_TDMEM101_BASE, 0x40007b28 +.set CYDEV_PHUB_TDMEM101_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM101_ORIG_TD0, 0x40007b28 +.set CYREG_PHUB_TDMEM101_ORIG_TD1, 0x40007b2c +.set CYDEV_PHUB_TDMEM102_BASE, 0x40007b30 +.set CYDEV_PHUB_TDMEM102_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM102_ORIG_TD0, 0x40007b30 +.set CYREG_PHUB_TDMEM102_ORIG_TD1, 0x40007b34 +.set CYDEV_PHUB_TDMEM103_BASE, 0x40007b38 +.set CYDEV_PHUB_TDMEM103_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM103_ORIG_TD0, 0x40007b38 +.set CYREG_PHUB_TDMEM103_ORIG_TD1, 0x40007b3c +.set CYDEV_PHUB_TDMEM104_BASE, 0x40007b40 +.set CYDEV_PHUB_TDMEM104_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM104_ORIG_TD0, 0x40007b40 +.set CYREG_PHUB_TDMEM104_ORIG_TD1, 0x40007b44 +.set CYDEV_PHUB_TDMEM105_BASE, 0x40007b48 +.set CYDEV_PHUB_TDMEM105_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM105_ORIG_TD0, 0x40007b48 +.set CYREG_PHUB_TDMEM105_ORIG_TD1, 0x40007b4c +.set CYDEV_PHUB_TDMEM106_BASE, 0x40007b50 +.set CYDEV_PHUB_TDMEM106_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM106_ORIG_TD0, 0x40007b50 +.set CYREG_PHUB_TDMEM106_ORIG_TD1, 0x40007b54 +.set CYDEV_PHUB_TDMEM107_BASE, 0x40007b58 +.set CYDEV_PHUB_TDMEM107_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM107_ORIG_TD0, 0x40007b58 +.set CYREG_PHUB_TDMEM107_ORIG_TD1, 0x40007b5c +.set CYDEV_PHUB_TDMEM108_BASE, 0x40007b60 +.set CYDEV_PHUB_TDMEM108_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM108_ORIG_TD0, 0x40007b60 +.set CYREG_PHUB_TDMEM108_ORIG_TD1, 0x40007b64 +.set CYDEV_PHUB_TDMEM109_BASE, 0x40007b68 +.set CYDEV_PHUB_TDMEM109_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM109_ORIG_TD0, 0x40007b68 +.set CYREG_PHUB_TDMEM109_ORIG_TD1, 0x40007b6c +.set CYDEV_PHUB_TDMEM110_BASE, 0x40007b70 +.set CYDEV_PHUB_TDMEM110_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM110_ORIG_TD0, 0x40007b70 +.set CYREG_PHUB_TDMEM110_ORIG_TD1, 0x40007b74 +.set CYDEV_PHUB_TDMEM111_BASE, 0x40007b78 +.set CYDEV_PHUB_TDMEM111_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM111_ORIG_TD0, 0x40007b78 +.set CYREG_PHUB_TDMEM111_ORIG_TD1, 0x40007b7c +.set CYDEV_PHUB_TDMEM112_BASE, 0x40007b80 +.set CYDEV_PHUB_TDMEM112_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM112_ORIG_TD0, 0x40007b80 +.set CYREG_PHUB_TDMEM112_ORIG_TD1, 0x40007b84 +.set CYDEV_PHUB_TDMEM113_BASE, 0x40007b88 +.set CYDEV_PHUB_TDMEM113_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM113_ORIG_TD0, 0x40007b88 +.set CYREG_PHUB_TDMEM113_ORIG_TD1, 0x40007b8c +.set CYDEV_PHUB_TDMEM114_BASE, 0x40007b90 +.set CYDEV_PHUB_TDMEM114_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM114_ORIG_TD0, 0x40007b90 +.set CYREG_PHUB_TDMEM114_ORIG_TD1, 0x40007b94 +.set CYDEV_PHUB_TDMEM115_BASE, 0x40007b98 +.set CYDEV_PHUB_TDMEM115_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM115_ORIG_TD0, 0x40007b98 +.set CYREG_PHUB_TDMEM115_ORIG_TD1, 0x40007b9c +.set CYDEV_PHUB_TDMEM116_BASE, 0x40007ba0 +.set CYDEV_PHUB_TDMEM116_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM116_ORIG_TD0, 0x40007ba0 +.set CYREG_PHUB_TDMEM116_ORIG_TD1, 0x40007ba4 +.set CYDEV_PHUB_TDMEM117_BASE, 0x40007ba8 +.set CYDEV_PHUB_TDMEM117_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM117_ORIG_TD0, 0x40007ba8 +.set CYREG_PHUB_TDMEM117_ORIG_TD1, 0x40007bac +.set CYDEV_PHUB_TDMEM118_BASE, 0x40007bb0 +.set CYDEV_PHUB_TDMEM118_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM118_ORIG_TD0, 0x40007bb0 +.set CYREG_PHUB_TDMEM118_ORIG_TD1, 0x40007bb4 +.set CYDEV_PHUB_TDMEM119_BASE, 0x40007bb8 +.set CYDEV_PHUB_TDMEM119_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM119_ORIG_TD0, 0x40007bb8 +.set CYREG_PHUB_TDMEM119_ORIG_TD1, 0x40007bbc +.set CYDEV_PHUB_TDMEM120_BASE, 0x40007bc0 +.set CYDEV_PHUB_TDMEM120_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM120_ORIG_TD0, 0x40007bc0 +.set CYREG_PHUB_TDMEM120_ORIG_TD1, 0x40007bc4 +.set CYDEV_PHUB_TDMEM121_BASE, 0x40007bc8 +.set CYDEV_PHUB_TDMEM121_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM121_ORIG_TD0, 0x40007bc8 +.set CYREG_PHUB_TDMEM121_ORIG_TD1, 0x40007bcc +.set CYDEV_PHUB_TDMEM122_BASE, 0x40007bd0 +.set CYDEV_PHUB_TDMEM122_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM122_ORIG_TD0, 0x40007bd0 +.set CYREG_PHUB_TDMEM122_ORIG_TD1, 0x40007bd4 +.set CYDEV_PHUB_TDMEM123_BASE, 0x40007bd8 +.set CYDEV_PHUB_TDMEM123_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM123_ORIG_TD0, 0x40007bd8 +.set CYREG_PHUB_TDMEM123_ORIG_TD1, 0x40007bdc +.set CYDEV_PHUB_TDMEM124_BASE, 0x40007be0 +.set CYDEV_PHUB_TDMEM124_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM124_ORIG_TD0, 0x40007be0 +.set CYREG_PHUB_TDMEM124_ORIG_TD1, 0x40007be4 +.set CYDEV_PHUB_TDMEM125_BASE, 0x40007be8 +.set CYDEV_PHUB_TDMEM125_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM125_ORIG_TD0, 0x40007be8 +.set CYREG_PHUB_TDMEM125_ORIG_TD1, 0x40007bec +.set CYDEV_PHUB_TDMEM126_BASE, 0x40007bf0 +.set CYDEV_PHUB_TDMEM126_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM126_ORIG_TD0, 0x40007bf0 +.set CYREG_PHUB_TDMEM126_ORIG_TD1, 0x40007bf4 +.set CYDEV_PHUB_TDMEM127_BASE, 0x40007bf8 +.set CYDEV_PHUB_TDMEM127_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM127_ORIG_TD0, 0x40007bf8 +.set CYREG_PHUB_TDMEM127_ORIG_TD1, 0x40007bfc +.set CYDEV_EE_BASE, 0x40008000 +.set CYDEV_EE_SIZE, 0x00000800 +.set CYREG_EE_DATA_MBASE, 0x40008000 +.set CYREG_EE_DATA_MSIZE, 0x00000800 +.set CYDEV_CAN0_BASE, 0x4000a000 +.set CYDEV_CAN0_SIZE, 0x000002a0 +.set CYDEV_CAN0_CSR_BASE, 0x4000a000 +.set CYDEV_CAN0_CSR_SIZE, 0x00000018 +.set CYREG_CAN0_CSR_INT_SR, 0x4000a000 +.set CYREG_CAN0_CSR_INT_EN, 0x4000a004 +.set CYREG_CAN0_CSR_BUF_SR, 0x4000a008 +.set CYREG_CAN0_CSR_ERR_SR, 0x4000a00c +.set CYREG_CAN0_CSR_CMD, 0x4000a010 +.set CYREG_CAN0_CSR_CFG, 0x4000a014 +.set CYDEV_CAN0_TX0_BASE, 0x4000a020 +.set CYDEV_CAN0_TX0_SIZE, 0x00000010 +.set CYREG_CAN0_TX0_CMD, 0x4000a020 +.set CYREG_CAN0_TX0_ID, 0x4000a024 +.set CYREG_CAN0_TX0_DH, 0x4000a028 +.set CYREG_CAN0_TX0_DL, 0x4000a02c +.set CYDEV_CAN0_TX1_BASE, 0x4000a030 +.set CYDEV_CAN0_TX1_SIZE, 0x00000010 +.set CYREG_CAN0_TX1_CMD, 0x4000a030 +.set CYREG_CAN0_TX1_ID, 0x4000a034 +.set CYREG_CAN0_TX1_DH, 0x4000a038 +.set CYREG_CAN0_TX1_DL, 0x4000a03c +.set CYDEV_CAN0_TX2_BASE, 0x4000a040 +.set CYDEV_CAN0_TX2_SIZE, 0x00000010 +.set CYREG_CAN0_TX2_CMD, 0x4000a040 +.set CYREG_CAN0_TX2_ID, 0x4000a044 +.set CYREG_CAN0_TX2_DH, 0x4000a048 +.set CYREG_CAN0_TX2_DL, 0x4000a04c +.set CYDEV_CAN0_TX3_BASE, 0x4000a050 +.set CYDEV_CAN0_TX3_SIZE, 0x00000010 +.set CYREG_CAN0_TX3_CMD, 0x4000a050 +.set CYREG_CAN0_TX3_ID, 0x4000a054 +.set CYREG_CAN0_TX3_DH, 0x4000a058 +.set CYREG_CAN0_TX3_DL, 0x4000a05c +.set CYDEV_CAN0_TX4_BASE, 0x4000a060 +.set CYDEV_CAN0_TX4_SIZE, 0x00000010 +.set CYREG_CAN0_TX4_CMD, 0x4000a060 +.set CYREG_CAN0_TX4_ID, 0x4000a064 +.set CYREG_CAN0_TX4_DH, 0x4000a068 +.set CYREG_CAN0_TX4_DL, 0x4000a06c +.set CYDEV_CAN0_TX5_BASE, 0x4000a070 +.set CYDEV_CAN0_TX5_SIZE, 0x00000010 +.set CYREG_CAN0_TX5_CMD, 0x4000a070 +.set CYREG_CAN0_TX5_ID, 0x4000a074 +.set CYREG_CAN0_TX5_DH, 0x4000a078 +.set CYREG_CAN0_TX5_DL, 0x4000a07c +.set CYDEV_CAN0_TX6_BASE, 0x4000a080 +.set CYDEV_CAN0_TX6_SIZE, 0x00000010 +.set CYREG_CAN0_TX6_CMD, 0x4000a080 +.set CYREG_CAN0_TX6_ID, 0x4000a084 +.set CYREG_CAN0_TX6_DH, 0x4000a088 +.set CYREG_CAN0_TX6_DL, 0x4000a08c +.set CYDEV_CAN0_TX7_BASE, 0x4000a090 +.set CYDEV_CAN0_TX7_SIZE, 0x00000010 +.set CYREG_CAN0_TX7_CMD, 0x4000a090 +.set CYREG_CAN0_TX7_ID, 0x4000a094 +.set CYREG_CAN0_TX7_DH, 0x4000a098 +.set CYREG_CAN0_TX7_DL, 0x4000a09c +.set CYDEV_CAN0_RX0_BASE, 0x4000a0a0 +.set CYDEV_CAN0_RX0_SIZE, 0x00000020 +.set CYREG_CAN0_RX0_CMD, 0x4000a0a0 +.set CYREG_CAN0_RX0_ID, 0x4000a0a4 +.set CYREG_CAN0_RX0_DH, 0x4000a0a8 +.set CYREG_CAN0_RX0_DL, 0x4000a0ac +.set CYREG_CAN0_RX0_AMR, 0x4000a0b0 +.set CYREG_CAN0_RX0_ACR, 0x4000a0b4 +.set CYREG_CAN0_RX0_AMRD, 0x4000a0b8 +.set CYREG_CAN0_RX0_ACRD, 0x4000a0bc +.set CYDEV_CAN0_RX1_BASE, 0x4000a0c0 +.set CYDEV_CAN0_RX1_SIZE, 0x00000020 +.set CYREG_CAN0_RX1_CMD, 0x4000a0c0 +.set CYREG_CAN0_RX1_ID, 0x4000a0c4 +.set CYREG_CAN0_RX1_DH, 0x4000a0c8 +.set CYREG_CAN0_RX1_DL, 0x4000a0cc +.set CYREG_CAN0_RX1_AMR, 0x4000a0d0 +.set CYREG_CAN0_RX1_ACR, 0x4000a0d4 +.set CYREG_CAN0_RX1_AMRD, 0x4000a0d8 +.set CYREG_CAN0_RX1_ACRD, 0x4000a0dc +.set CYDEV_CAN0_RX2_BASE, 0x4000a0e0 +.set CYDEV_CAN0_RX2_SIZE, 0x00000020 +.set CYREG_CAN0_RX2_CMD, 0x4000a0e0 +.set CYREG_CAN0_RX2_ID, 0x4000a0e4 +.set CYREG_CAN0_RX2_DH, 0x4000a0e8 +.set CYREG_CAN0_RX2_DL, 0x4000a0ec +.set CYREG_CAN0_RX2_AMR, 0x4000a0f0 +.set CYREG_CAN0_RX2_ACR, 0x4000a0f4 +.set CYREG_CAN0_RX2_AMRD, 0x4000a0f8 +.set CYREG_CAN0_RX2_ACRD, 0x4000a0fc +.set CYDEV_CAN0_RX3_BASE, 0x4000a100 +.set CYDEV_CAN0_RX3_SIZE, 0x00000020 +.set CYREG_CAN0_RX3_CMD, 0x4000a100 +.set CYREG_CAN0_RX3_ID, 0x4000a104 +.set CYREG_CAN0_RX3_DH, 0x4000a108 +.set CYREG_CAN0_RX3_DL, 0x4000a10c +.set CYREG_CAN0_RX3_AMR, 0x4000a110 +.set CYREG_CAN0_RX3_ACR, 0x4000a114 +.set CYREG_CAN0_RX3_AMRD, 0x4000a118 +.set CYREG_CAN0_RX3_ACRD, 0x4000a11c +.set CYDEV_CAN0_RX4_BASE, 0x4000a120 +.set CYDEV_CAN0_RX4_SIZE, 0x00000020 +.set CYREG_CAN0_RX4_CMD, 0x4000a120 +.set CYREG_CAN0_RX4_ID, 0x4000a124 +.set CYREG_CAN0_RX4_DH, 0x4000a128 +.set CYREG_CAN0_RX4_DL, 0x4000a12c +.set CYREG_CAN0_RX4_AMR, 0x4000a130 +.set CYREG_CAN0_RX4_ACR, 0x4000a134 +.set CYREG_CAN0_RX4_AMRD, 0x4000a138 +.set CYREG_CAN0_RX4_ACRD, 0x4000a13c +.set CYDEV_CAN0_RX5_BASE, 0x4000a140 +.set CYDEV_CAN0_RX5_SIZE, 0x00000020 +.set CYREG_CAN0_RX5_CMD, 0x4000a140 +.set CYREG_CAN0_RX5_ID, 0x4000a144 +.set CYREG_CAN0_RX5_DH, 0x4000a148 +.set CYREG_CAN0_RX5_DL, 0x4000a14c +.set CYREG_CAN0_RX5_AMR, 0x4000a150 +.set CYREG_CAN0_RX5_ACR, 0x4000a154 +.set CYREG_CAN0_RX5_AMRD, 0x4000a158 +.set CYREG_CAN0_RX5_ACRD, 0x4000a15c +.set CYDEV_CAN0_RX6_BASE, 0x4000a160 +.set CYDEV_CAN0_RX6_SIZE, 0x00000020 +.set CYREG_CAN0_RX6_CMD, 0x4000a160 +.set CYREG_CAN0_RX6_ID, 0x4000a164 +.set CYREG_CAN0_RX6_DH, 0x4000a168 +.set CYREG_CAN0_RX6_DL, 0x4000a16c +.set CYREG_CAN0_RX6_AMR, 0x4000a170 +.set CYREG_CAN0_RX6_ACR, 0x4000a174 +.set CYREG_CAN0_RX6_AMRD, 0x4000a178 +.set CYREG_CAN0_RX6_ACRD, 0x4000a17c +.set CYDEV_CAN0_RX7_BASE, 0x4000a180 +.set CYDEV_CAN0_RX7_SIZE, 0x00000020 +.set CYREG_CAN0_RX7_CMD, 0x4000a180 +.set CYREG_CAN0_RX7_ID, 0x4000a184 +.set CYREG_CAN0_RX7_DH, 0x4000a188 +.set CYREG_CAN0_RX7_DL, 0x4000a18c +.set CYREG_CAN0_RX7_AMR, 0x4000a190 +.set CYREG_CAN0_RX7_ACR, 0x4000a194 +.set CYREG_CAN0_RX7_AMRD, 0x4000a198 +.set CYREG_CAN0_RX7_ACRD, 0x4000a19c +.set CYDEV_CAN0_RX8_BASE, 0x4000a1a0 +.set CYDEV_CAN0_RX8_SIZE, 0x00000020 +.set CYREG_CAN0_RX8_CMD, 0x4000a1a0 +.set CYREG_CAN0_RX8_ID, 0x4000a1a4 +.set CYREG_CAN0_RX8_DH, 0x4000a1a8 +.set CYREG_CAN0_RX8_DL, 0x4000a1ac +.set CYREG_CAN0_RX8_AMR, 0x4000a1b0 +.set CYREG_CAN0_RX8_ACR, 0x4000a1b4 +.set CYREG_CAN0_RX8_AMRD, 0x4000a1b8 +.set CYREG_CAN0_RX8_ACRD, 0x4000a1bc +.set CYDEV_CAN0_RX9_BASE, 0x4000a1c0 +.set CYDEV_CAN0_RX9_SIZE, 0x00000020 +.set CYREG_CAN0_RX9_CMD, 0x4000a1c0 +.set CYREG_CAN0_RX9_ID, 0x4000a1c4 +.set CYREG_CAN0_RX9_DH, 0x4000a1c8 +.set CYREG_CAN0_RX9_DL, 0x4000a1cc +.set CYREG_CAN0_RX9_AMR, 0x4000a1d0 +.set CYREG_CAN0_RX9_ACR, 0x4000a1d4 +.set CYREG_CAN0_RX9_AMRD, 0x4000a1d8 +.set CYREG_CAN0_RX9_ACRD, 0x4000a1dc +.set CYDEV_CAN0_RX10_BASE, 0x4000a1e0 +.set CYDEV_CAN0_RX10_SIZE, 0x00000020 +.set CYREG_CAN0_RX10_CMD, 0x4000a1e0 +.set CYREG_CAN0_RX10_ID, 0x4000a1e4 +.set CYREG_CAN0_RX10_DH, 0x4000a1e8 +.set CYREG_CAN0_RX10_DL, 0x4000a1ec +.set CYREG_CAN0_RX10_AMR, 0x4000a1f0 +.set CYREG_CAN0_RX10_ACR, 0x4000a1f4 +.set CYREG_CAN0_RX10_AMRD, 0x4000a1f8 +.set CYREG_CAN0_RX10_ACRD, 0x4000a1fc +.set CYDEV_CAN0_RX11_BASE, 0x4000a200 +.set CYDEV_CAN0_RX11_SIZE, 0x00000020 +.set CYREG_CAN0_RX11_CMD, 0x4000a200 +.set CYREG_CAN0_RX11_ID, 0x4000a204 +.set CYREG_CAN0_RX11_DH, 0x4000a208 +.set CYREG_CAN0_RX11_DL, 0x4000a20c +.set CYREG_CAN0_RX11_AMR, 0x4000a210 +.set CYREG_CAN0_RX11_ACR, 0x4000a214 +.set CYREG_CAN0_RX11_AMRD, 0x4000a218 +.set CYREG_CAN0_RX11_ACRD, 0x4000a21c +.set CYDEV_CAN0_RX12_BASE, 0x4000a220 +.set CYDEV_CAN0_RX12_SIZE, 0x00000020 +.set CYREG_CAN0_RX12_CMD, 0x4000a220 +.set CYREG_CAN0_RX12_ID, 0x4000a224 +.set CYREG_CAN0_RX12_DH, 0x4000a228 +.set CYREG_CAN0_RX12_DL, 0x4000a22c +.set CYREG_CAN0_RX12_AMR, 0x4000a230 +.set CYREG_CAN0_RX12_ACR, 0x4000a234 +.set CYREG_CAN0_RX12_AMRD, 0x4000a238 +.set CYREG_CAN0_RX12_ACRD, 0x4000a23c +.set CYDEV_CAN0_RX13_BASE, 0x4000a240 +.set CYDEV_CAN0_RX13_SIZE, 0x00000020 +.set CYREG_CAN0_RX13_CMD, 0x4000a240 +.set CYREG_CAN0_RX13_ID, 0x4000a244 +.set CYREG_CAN0_RX13_DH, 0x4000a248 +.set CYREG_CAN0_RX13_DL, 0x4000a24c +.set CYREG_CAN0_RX13_AMR, 0x4000a250 +.set CYREG_CAN0_RX13_ACR, 0x4000a254 +.set CYREG_CAN0_RX13_AMRD, 0x4000a258 +.set CYREG_CAN0_RX13_ACRD, 0x4000a25c +.set CYDEV_CAN0_RX14_BASE, 0x4000a260 +.set CYDEV_CAN0_RX14_SIZE, 0x00000020 +.set CYREG_CAN0_RX14_CMD, 0x4000a260 +.set CYREG_CAN0_RX14_ID, 0x4000a264 +.set CYREG_CAN0_RX14_DH, 0x4000a268 +.set CYREG_CAN0_RX14_DL, 0x4000a26c +.set CYREG_CAN0_RX14_AMR, 0x4000a270 +.set CYREG_CAN0_RX14_ACR, 0x4000a274 +.set CYREG_CAN0_RX14_AMRD, 0x4000a278 +.set CYREG_CAN0_RX14_ACRD, 0x4000a27c +.set CYDEV_CAN0_RX15_BASE, 0x4000a280 +.set CYDEV_CAN0_RX15_SIZE, 0x00000020 +.set CYREG_CAN0_RX15_CMD, 0x4000a280 +.set CYREG_CAN0_RX15_ID, 0x4000a284 +.set CYREG_CAN0_RX15_DH, 0x4000a288 +.set CYREG_CAN0_RX15_DL, 0x4000a28c +.set CYREG_CAN0_RX15_AMR, 0x4000a290 +.set CYREG_CAN0_RX15_ACR, 0x4000a294 +.set CYREG_CAN0_RX15_AMRD, 0x4000a298 +.set CYREG_CAN0_RX15_ACRD, 0x4000a29c +.set CYDEV_DFB0_BASE, 0x4000c000 +.set CYDEV_DFB0_SIZE, 0x000007b5 +.set CYDEV_DFB0_DPA_SRAM_BASE, 0x4000c000 +.set CYDEV_DFB0_DPA_SRAM_SIZE, 0x00000200 +.set CYREG_DFB0_DPA_SRAM_DATA_MBASE, 0x4000c000 +.set CYREG_DFB0_DPA_SRAM_DATA_MSIZE, 0x00000200 +.set CYDEV_DFB0_DPB_SRAM_BASE, 0x4000c200 +.set CYDEV_DFB0_DPB_SRAM_SIZE, 0x00000200 +.set CYREG_DFB0_DPB_SRAM_DATA_MBASE, 0x4000c200 +.set CYREG_DFB0_DPB_SRAM_DATA_MSIZE, 0x00000200 +.set CYDEV_DFB0_CSA_SRAM_BASE, 0x4000c400 +.set CYDEV_DFB0_CSA_SRAM_SIZE, 0x00000100 +.set CYREG_DFB0_CSA_SRAM_DATA_MBASE, 0x4000c400 +.set CYREG_DFB0_CSA_SRAM_DATA_MSIZE, 0x00000100 +.set CYDEV_DFB0_CSB_SRAM_BASE, 0x4000c500 +.set CYDEV_DFB0_CSB_SRAM_SIZE, 0x00000100 +.set CYREG_DFB0_CSB_SRAM_DATA_MBASE, 0x4000c500 +.set CYREG_DFB0_CSB_SRAM_DATA_MSIZE, 0x00000100 +.set CYDEV_DFB0_FSM_SRAM_BASE, 0x4000c600 +.set CYDEV_DFB0_FSM_SRAM_SIZE, 0x00000100 +.set CYREG_DFB0_FSM_SRAM_DATA_MBASE, 0x4000c600 +.set CYREG_DFB0_FSM_SRAM_DATA_MSIZE, 0x00000100 +.set CYDEV_DFB0_ACU_SRAM_BASE, 0x4000c700 +.set CYDEV_DFB0_ACU_SRAM_SIZE, 0x00000040 +.set CYREG_DFB0_ACU_SRAM_DATA_MBASE, 0x4000c700 +.set CYREG_DFB0_ACU_SRAM_DATA_MSIZE, 0x00000040 +.set CYREG_DFB0_CR, 0x4000c780 +.set CYREG_DFB0_SR, 0x4000c784 +.set CYREG_DFB0_RAM_EN, 0x4000c788 +.set CYREG_DFB0_RAM_DIR, 0x4000c78c +.set CYREG_DFB0_SEMA, 0x4000c790 +.set CYREG_DFB0_DSI_CTRL, 0x4000c794 +.set CYREG_DFB0_INT_CTRL, 0x4000c798 +.set CYREG_DFB0_DMA_CTRL, 0x4000c79c +.set CYREG_DFB0_STAGEA, 0x4000c7a0 +.set CYREG_DFB0_STAGEAM, 0x4000c7a1 +.set CYREG_DFB0_STAGEAH, 0x4000c7a2 +.set CYREG_DFB0_STAGEB, 0x4000c7a4 +.set CYREG_DFB0_STAGEBM, 0x4000c7a5 +.set CYREG_DFB0_STAGEBH, 0x4000c7a6 +.set CYREG_DFB0_HOLDA, 0x4000c7a8 +.set CYREG_DFB0_HOLDAM, 0x4000c7a9 +.set CYREG_DFB0_HOLDAH, 0x4000c7aa +.set CYREG_DFB0_HOLDAS, 0x4000c7ab +.set CYREG_DFB0_HOLDB, 0x4000c7ac +.set CYREG_DFB0_HOLDBM, 0x4000c7ad +.set CYREG_DFB0_HOLDBH, 0x4000c7ae +.set CYREG_DFB0_HOLDBS, 0x4000c7af +.set CYREG_DFB0_COHER, 0x4000c7b0 +.set CYREG_DFB0_DALIGN, 0x4000c7b4 +.set CYDEV_UCFG_BASE, 0x40010000 +.set CYDEV_UCFG_SIZE, 0x00005040 +.set CYDEV_UCFG_B0_BASE, 0x40010000 +.set CYDEV_UCFG_B0_SIZE, 0x00000fef +.set CYDEV_UCFG_B0_P0_BASE, 0x40010000 +.set CYDEV_UCFG_B0_P0_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P0_U0_BASE, 0x40010000 +.set CYDEV_UCFG_B0_P0_U0_SIZE, 0x00000070 +.set CYREG_B0_P0_U0_PLD_IT0, 0x40010000 +.set CYREG_B0_P0_U0_PLD_IT1, 0x40010004 +.set CYREG_B0_P0_U0_PLD_IT2, 0x40010008 +.set CYREG_B0_P0_U0_PLD_IT3, 0x4001000c +.set CYREG_B0_P0_U0_PLD_IT4, 0x40010010 +.set CYREG_B0_P0_U0_PLD_IT5, 0x40010014 +.set CYREG_B0_P0_U0_PLD_IT6, 0x40010018 +.set CYREG_B0_P0_U0_PLD_IT7, 0x4001001c +.set CYREG_B0_P0_U0_PLD_IT8, 0x40010020 +.set CYREG_B0_P0_U0_PLD_IT9, 0x40010024 +.set CYREG_B0_P0_U0_PLD_IT10, 0x40010028 +.set CYREG_B0_P0_U0_PLD_IT11, 0x4001002c +.set CYREG_B0_P0_U0_PLD_ORT0, 0x40010030 +.set CYREG_B0_P0_U0_PLD_ORT1, 0x40010032 +.set CYREG_B0_P0_U0_PLD_ORT2, 0x40010034 +.set CYREG_B0_P0_U0_PLD_ORT3, 0x40010036 +.set CYREG_B0_P0_U0_MC_CFG_CEN_CONST, 0x40010038 +.set CYREG_B0_P0_U0_MC_CFG_XORFB, 0x4001003a +.set CYREG_B0_P0_U0_MC_CFG_SET_RESET, 0x4001003c +.set CYREG_B0_P0_U0_MC_CFG_BYPASS, 0x4001003e +.set CYREG_B0_P0_U0_CFG0, 0x40010040 +.set CYREG_B0_P0_U0_CFG1, 0x40010041 +.set CYREG_B0_P0_U0_CFG2, 0x40010042 +.set CYREG_B0_P0_U0_CFG3, 0x40010043 +.set CYREG_B0_P0_U0_CFG4, 0x40010044 +.set CYREG_B0_P0_U0_CFG5, 0x40010045 +.set CYREG_B0_P0_U0_CFG6, 0x40010046 +.set CYREG_B0_P0_U0_CFG7, 0x40010047 +.set CYREG_B0_P0_U0_CFG8, 0x40010048 +.set CYREG_B0_P0_U0_CFG9, 0x40010049 +.set CYREG_B0_P0_U0_CFG10, 0x4001004a +.set CYREG_B0_P0_U0_CFG11, 0x4001004b +.set CYREG_B0_P0_U0_CFG12, 0x4001004c +.set CYREG_B0_P0_U0_CFG13, 0x4001004d +.set CYREG_B0_P0_U0_CFG14, 0x4001004e +.set CYREG_B0_P0_U0_CFG15, 0x4001004f +.set CYREG_B0_P0_U0_CFG16, 0x40010050 +.set CYREG_B0_P0_U0_CFG17, 0x40010051 +.set CYREG_B0_P0_U0_CFG18, 0x40010052 +.set CYREG_B0_P0_U0_CFG19, 0x40010053 +.set CYREG_B0_P0_U0_CFG20, 0x40010054 +.set CYREG_B0_P0_U0_CFG21, 0x40010055 +.set CYREG_B0_P0_U0_CFG22, 0x40010056 +.set CYREG_B0_P0_U0_CFG23, 0x40010057 +.set CYREG_B0_P0_U0_CFG24, 0x40010058 +.set CYREG_B0_P0_U0_CFG25, 0x40010059 +.set CYREG_B0_P0_U0_CFG26, 0x4001005a +.set CYREG_B0_P0_U0_CFG27, 0x4001005b +.set CYREG_B0_P0_U0_CFG28, 0x4001005c +.set CYREG_B0_P0_U0_CFG29, 0x4001005d +.set CYREG_B0_P0_U0_CFG30, 0x4001005e +.set CYREG_B0_P0_U0_CFG31, 0x4001005f +.set CYREG_B0_P0_U0_DCFG0, 0x40010060 +.set CYREG_B0_P0_U0_DCFG1, 0x40010062 +.set CYREG_B0_P0_U0_DCFG2, 0x40010064 +.set CYREG_B0_P0_U0_DCFG3, 0x40010066 +.set CYREG_B0_P0_U0_DCFG4, 0x40010068 +.set CYREG_B0_P0_U0_DCFG5, 0x4001006a +.set CYREG_B0_P0_U0_DCFG6, 0x4001006c +.set CYREG_B0_P0_U0_DCFG7, 0x4001006e +.set CYDEV_UCFG_B0_P0_U1_BASE, 0x40010080 +.set CYDEV_UCFG_B0_P0_U1_SIZE, 0x00000070 +.set CYREG_B0_P0_U1_PLD_IT0, 0x40010080 +.set CYREG_B0_P0_U1_PLD_IT1, 0x40010084 +.set CYREG_B0_P0_U1_PLD_IT2, 0x40010088 +.set CYREG_B0_P0_U1_PLD_IT3, 0x4001008c +.set CYREG_B0_P0_U1_PLD_IT4, 0x40010090 +.set CYREG_B0_P0_U1_PLD_IT5, 0x40010094 +.set CYREG_B0_P0_U1_PLD_IT6, 0x40010098 +.set CYREG_B0_P0_U1_PLD_IT7, 0x4001009c +.set CYREG_B0_P0_U1_PLD_IT8, 0x400100a0 +.set CYREG_B0_P0_U1_PLD_IT9, 0x400100a4 +.set CYREG_B0_P0_U1_PLD_IT10, 0x400100a8 +.set CYREG_B0_P0_U1_PLD_IT11, 0x400100ac +.set CYREG_B0_P0_U1_PLD_ORT0, 0x400100b0 +.set CYREG_B0_P0_U1_PLD_ORT1, 0x400100b2 +.set CYREG_B0_P0_U1_PLD_ORT2, 0x400100b4 +.set CYREG_B0_P0_U1_PLD_ORT3, 0x400100b6 +.set CYREG_B0_P0_U1_MC_CFG_CEN_CONST, 0x400100b8 +.set CYREG_B0_P0_U1_MC_CFG_XORFB, 0x400100ba +.set CYREG_B0_P0_U1_MC_CFG_SET_RESET, 0x400100bc +.set CYREG_B0_P0_U1_MC_CFG_BYPASS, 0x400100be +.set CYREG_B0_P0_U1_CFG0, 0x400100c0 +.set CYREG_B0_P0_U1_CFG1, 0x400100c1 +.set CYREG_B0_P0_U1_CFG2, 0x400100c2 +.set CYREG_B0_P0_U1_CFG3, 0x400100c3 +.set CYREG_B0_P0_U1_CFG4, 0x400100c4 +.set CYREG_B0_P0_U1_CFG5, 0x400100c5 +.set CYREG_B0_P0_U1_CFG6, 0x400100c6 +.set CYREG_B0_P0_U1_CFG7, 0x400100c7 +.set CYREG_B0_P0_U1_CFG8, 0x400100c8 +.set CYREG_B0_P0_U1_CFG9, 0x400100c9 +.set CYREG_B0_P0_U1_CFG10, 0x400100ca +.set CYREG_B0_P0_U1_CFG11, 0x400100cb +.set CYREG_B0_P0_U1_CFG12, 0x400100cc +.set CYREG_B0_P0_U1_CFG13, 0x400100cd +.set CYREG_B0_P0_U1_CFG14, 0x400100ce +.set CYREG_B0_P0_U1_CFG15, 0x400100cf +.set CYREG_B0_P0_U1_CFG16, 0x400100d0 +.set CYREG_B0_P0_U1_CFG17, 0x400100d1 +.set CYREG_B0_P0_U1_CFG18, 0x400100d2 +.set CYREG_B0_P0_U1_CFG19, 0x400100d3 +.set CYREG_B0_P0_U1_CFG20, 0x400100d4 +.set CYREG_B0_P0_U1_CFG21, 0x400100d5 +.set CYREG_B0_P0_U1_CFG22, 0x400100d6 +.set CYREG_B0_P0_U1_CFG23, 0x400100d7 +.set CYREG_B0_P0_U1_CFG24, 0x400100d8 +.set CYREG_B0_P0_U1_CFG25, 0x400100d9 +.set CYREG_B0_P0_U1_CFG26, 0x400100da +.set CYREG_B0_P0_U1_CFG27, 0x400100db +.set CYREG_B0_P0_U1_CFG28, 0x400100dc +.set CYREG_B0_P0_U1_CFG29, 0x400100dd +.set CYREG_B0_P0_U1_CFG30, 0x400100de +.set CYREG_B0_P0_U1_CFG31, 0x400100df +.set CYREG_B0_P0_U1_DCFG0, 0x400100e0 +.set CYREG_B0_P0_U1_DCFG1, 0x400100e2 +.set CYREG_B0_P0_U1_DCFG2, 0x400100e4 +.set CYREG_B0_P0_U1_DCFG3, 0x400100e6 +.set CYREG_B0_P0_U1_DCFG4, 0x400100e8 +.set CYREG_B0_P0_U1_DCFG5, 0x400100ea +.set CYREG_B0_P0_U1_DCFG6, 0x400100ec +.set CYREG_B0_P0_U1_DCFG7, 0x400100ee +.set CYDEV_UCFG_B0_P0_ROUTE_BASE, 0x40010100 +.set CYDEV_UCFG_B0_P0_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P1_BASE, 0x40010200 +.set CYDEV_UCFG_B0_P1_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P1_U0_BASE, 0x40010200 +.set CYDEV_UCFG_B0_P1_U0_SIZE, 0x00000070 +.set CYREG_B0_P1_U0_PLD_IT0, 0x40010200 +.set CYREG_B0_P1_U0_PLD_IT1, 0x40010204 +.set CYREG_B0_P1_U0_PLD_IT2, 0x40010208 +.set CYREG_B0_P1_U0_PLD_IT3, 0x4001020c +.set CYREG_B0_P1_U0_PLD_IT4, 0x40010210 +.set CYREG_B0_P1_U0_PLD_IT5, 0x40010214 +.set CYREG_B0_P1_U0_PLD_IT6, 0x40010218 +.set CYREG_B0_P1_U0_PLD_IT7, 0x4001021c +.set CYREG_B0_P1_U0_PLD_IT8, 0x40010220 +.set CYREG_B0_P1_U0_PLD_IT9, 0x40010224 +.set CYREG_B0_P1_U0_PLD_IT10, 0x40010228 +.set CYREG_B0_P1_U0_PLD_IT11, 0x4001022c +.set CYREG_B0_P1_U0_PLD_ORT0, 0x40010230 +.set CYREG_B0_P1_U0_PLD_ORT1, 0x40010232 +.set CYREG_B0_P1_U0_PLD_ORT2, 0x40010234 +.set CYREG_B0_P1_U0_PLD_ORT3, 0x40010236 +.set CYREG_B0_P1_U0_MC_CFG_CEN_CONST, 0x40010238 +.set CYREG_B0_P1_U0_MC_CFG_XORFB, 0x4001023a +.set CYREG_B0_P1_U0_MC_CFG_SET_RESET, 0x4001023c +.set CYREG_B0_P1_U0_MC_CFG_BYPASS, 0x4001023e +.set CYREG_B0_P1_U0_CFG0, 0x40010240 +.set CYREG_B0_P1_U0_CFG1, 0x40010241 +.set CYREG_B0_P1_U0_CFG2, 0x40010242 +.set CYREG_B0_P1_U0_CFG3, 0x40010243 +.set CYREG_B0_P1_U0_CFG4, 0x40010244 +.set CYREG_B0_P1_U0_CFG5, 0x40010245 +.set CYREG_B0_P1_U0_CFG6, 0x40010246 +.set CYREG_B0_P1_U0_CFG7, 0x40010247 +.set CYREG_B0_P1_U0_CFG8, 0x40010248 +.set CYREG_B0_P1_U0_CFG9, 0x40010249 +.set CYREG_B0_P1_U0_CFG10, 0x4001024a +.set CYREG_B0_P1_U0_CFG11, 0x4001024b +.set CYREG_B0_P1_U0_CFG12, 0x4001024c +.set CYREG_B0_P1_U0_CFG13, 0x4001024d +.set CYREG_B0_P1_U0_CFG14, 0x4001024e +.set CYREG_B0_P1_U0_CFG15, 0x4001024f +.set CYREG_B0_P1_U0_CFG16, 0x40010250 +.set CYREG_B0_P1_U0_CFG17, 0x40010251 +.set CYREG_B0_P1_U0_CFG18, 0x40010252 +.set CYREG_B0_P1_U0_CFG19, 0x40010253 +.set CYREG_B0_P1_U0_CFG20, 0x40010254 +.set CYREG_B0_P1_U0_CFG21, 0x40010255 +.set CYREG_B0_P1_U0_CFG22, 0x40010256 +.set CYREG_B0_P1_U0_CFG23, 0x40010257 +.set CYREG_B0_P1_U0_CFG24, 0x40010258 +.set CYREG_B0_P1_U0_CFG25, 0x40010259 +.set CYREG_B0_P1_U0_CFG26, 0x4001025a +.set CYREG_B0_P1_U0_CFG27, 0x4001025b +.set CYREG_B0_P1_U0_CFG28, 0x4001025c +.set CYREG_B0_P1_U0_CFG29, 0x4001025d +.set CYREG_B0_P1_U0_CFG30, 0x4001025e +.set CYREG_B0_P1_U0_CFG31, 0x4001025f +.set CYREG_B0_P1_U0_DCFG0, 0x40010260 +.set CYREG_B0_P1_U0_DCFG1, 0x40010262 +.set CYREG_B0_P1_U0_DCFG2, 0x40010264 +.set CYREG_B0_P1_U0_DCFG3, 0x40010266 +.set CYREG_B0_P1_U0_DCFG4, 0x40010268 +.set CYREG_B0_P1_U0_DCFG5, 0x4001026a +.set CYREG_B0_P1_U0_DCFG6, 0x4001026c +.set CYREG_B0_P1_U0_DCFG7, 0x4001026e +.set CYDEV_UCFG_B0_P1_U1_BASE, 0x40010280 +.set CYDEV_UCFG_B0_P1_U1_SIZE, 0x00000070 +.set CYREG_B0_P1_U1_PLD_IT0, 0x40010280 +.set CYREG_B0_P1_U1_PLD_IT1, 0x40010284 +.set CYREG_B0_P1_U1_PLD_IT2, 0x40010288 +.set CYREG_B0_P1_U1_PLD_IT3, 0x4001028c +.set CYREG_B0_P1_U1_PLD_IT4, 0x40010290 +.set CYREG_B0_P1_U1_PLD_IT5, 0x40010294 +.set CYREG_B0_P1_U1_PLD_IT6, 0x40010298 +.set CYREG_B0_P1_U1_PLD_IT7, 0x4001029c +.set CYREG_B0_P1_U1_PLD_IT8, 0x400102a0 +.set CYREG_B0_P1_U1_PLD_IT9, 0x400102a4 +.set CYREG_B0_P1_U1_PLD_IT10, 0x400102a8 +.set CYREG_B0_P1_U1_PLD_IT11, 0x400102ac +.set CYREG_B0_P1_U1_PLD_ORT0, 0x400102b0 +.set CYREG_B0_P1_U1_PLD_ORT1, 0x400102b2 +.set CYREG_B0_P1_U1_PLD_ORT2, 0x400102b4 +.set CYREG_B0_P1_U1_PLD_ORT3, 0x400102b6 +.set CYREG_B0_P1_U1_MC_CFG_CEN_CONST, 0x400102b8 +.set CYREG_B0_P1_U1_MC_CFG_XORFB, 0x400102ba +.set CYREG_B0_P1_U1_MC_CFG_SET_RESET, 0x400102bc +.set CYREG_B0_P1_U1_MC_CFG_BYPASS, 0x400102be +.set CYREG_B0_P1_U1_CFG0, 0x400102c0 +.set CYREG_B0_P1_U1_CFG1, 0x400102c1 +.set CYREG_B0_P1_U1_CFG2, 0x400102c2 +.set CYREG_B0_P1_U1_CFG3, 0x400102c3 +.set CYREG_B0_P1_U1_CFG4, 0x400102c4 +.set CYREG_B0_P1_U1_CFG5, 0x400102c5 +.set CYREG_B0_P1_U1_CFG6, 0x400102c6 +.set CYREG_B0_P1_U1_CFG7, 0x400102c7 +.set CYREG_B0_P1_U1_CFG8, 0x400102c8 +.set CYREG_B0_P1_U1_CFG9, 0x400102c9 +.set CYREG_B0_P1_U1_CFG10, 0x400102ca +.set CYREG_B0_P1_U1_CFG11, 0x400102cb +.set CYREG_B0_P1_U1_CFG12, 0x400102cc +.set CYREG_B0_P1_U1_CFG13, 0x400102cd +.set CYREG_B0_P1_U1_CFG14, 0x400102ce +.set CYREG_B0_P1_U1_CFG15, 0x400102cf +.set CYREG_B0_P1_U1_CFG16, 0x400102d0 +.set CYREG_B0_P1_U1_CFG17, 0x400102d1 +.set CYREG_B0_P1_U1_CFG18, 0x400102d2 +.set CYREG_B0_P1_U1_CFG19, 0x400102d3 +.set CYREG_B0_P1_U1_CFG20, 0x400102d4 +.set CYREG_B0_P1_U1_CFG21, 0x400102d5 +.set CYREG_B0_P1_U1_CFG22, 0x400102d6 +.set CYREG_B0_P1_U1_CFG23, 0x400102d7 +.set CYREG_B0_P1_U1_CFG24, 0x400102d8 +.set CYREG_B0_P1_U1_CFG25, 0x400102d9 +.set CYREG_B0_P1_U1_CFG26, 0x400102da +.set CYREG_B0_P1_U1_CFG27, 0x400102db +.set CYREG_B0_P1_U1_CFG28, 0x400102dc +.set CYREG_B0_P1_U1_CFG29, 0x400102dd +.set CYREG_B0_P1_U1_CFG30, 0x400102de +.set CYREG_B0_P1_U1_CFG31, 0x400102df +.set CYREG_B0_P1_U1_DCFG0, 0x400102e0 +.set CYREG_B0_P1_U1_DCFG1, 0x400102e2 +.set CYREG_B0_P1_U1_DCFG2, 0x400102e4 +.set CYREG_B0_P1_U1_DCFG3, 0x400102e6 +.set CYREG_B0_P1_U1_DCFG4, 0x400102e8 +.set CYREG_B0_P1_U1_DCFG5, 0x400102ea +.set CYREG_B0_P1_U1_DCFG6, 0x400102ec +.set CYREG_B0_P1_U1_DCFG7, 0x400102ee +.set CYDEV_UCFG_B0_P1_ROUTE_BASE, 0x40010300 +.set CYDEV_UCFG_B0_P1_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P2_BASE, 0x40010400 +.set CYDEV_UCFG_B0_P2_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P2_U0_BASE, 0x40010400 +.set CYDEV_UCFG_B0_P2_U0_SIZE, 0x00000070 +.set CYREG_B0_P2_U0_PLD_IT0, 0x40010400 +.set CYREG_B0_P2_U0_PLD_IT1, 0x40010404 +.set CYREG_B0_P2_U0_PLD_IT2, 0x40010408 +.set CYREG_B0_P2_U0_PLD_IT3, 0x4001040c +.set CYREG_B0_P2_U0_PLD_IT4, 0x40010410 +.set CYREG_B0_P2_U0_PLD_IT5, 0x40010414 +.set CYREG_B0_P2_U0_PLD_IT6, 0x40010418 +.set CYREG_B0_P2_U0_PLD_IT7, 0x4001041c +.set CYREG_B0_P2_U0_PLD_IT8, 0x40010420 +.set CYREG_B0_P2_U0_PLD_IT9, 0x40010424 +.set CYREG_B0_P2_U0_PLD_IT10, 0x40010428 +.set CYREG_B0_P2_U0_PLD_IT11, 0x4001042c +.set CYREG_B0_P2_U0_PLD_ORT0, 0x40010430 +.set CYREG_B0_P2_U0_PLD_ORT1, 0x40010432 +.set CYREG_B0_P2_U0_PLD_ORT2, 0x40010434 +.set CYREG_B0_P2_U0_PLD_ORT3, 0x40010436 +.set CYREG_B0_P2_U0_MC_CFG_CEN_CONST, 0x40010438 +.set CYREG_B0_P2_U0_MC_CFG_XORFB, 0x4001043a +.set CYREG_B0_P2_U0_MC_CFG_SET_RESET, 0x4001043c +.set CYREG_B0_P2_U0_MC_CFG_BYPASS, 0x4001043e +.set CYREG_B0_P2_U0_CFG0, 0x40010440 +.set CYREG_B0_P2_U0_CFG1, 0x40010441 +.set CYREG_B0_P2_U0_CFG2, 0x40010442 +.set CYREG_B0_P2_U0_CFG3, 0x40010443 +.set CYREG_B0_P2_U0_CFG4, 0x40010444 +.set CYREG_B0_P2_U0_CFG5, 0x40010445 +.set CYREG_B0_P2_U0_CFG6, 0x40010446 +.set CYREG_B0_P2_U0_CFG7, 0x40010447 +.set CYREG_B0_P2_U0_CFG8, 0x40010448 +.set CYREG_B0_P2_U0_CFG9, 0x40010449 +.set CYREG_B0_P2_U0_CFG10, 0x4001044a +.set CYREG_B0_P2_U0_CFG11, 0x4001044b +.set CYREG_B0_P2_U0_CFG12, 0x4001044c +.set CYREG_B0_P2_U0_CFG13, 0x4001044d +.set CYREG_B0_P2_U0_CFG14, 0x4001044e +.set CYREG_B0_P2_U0_CFG15, 0x4001044f +.set CYREG_B0_P2_U0_CFG16, 0x40010450 +.set CYREG_B0_P2_U0_CFG17, 0x40010451 +.set CYREG_B0_P2_U0_CFG18, 0x40010452 +.set CYREG_B0_P2_U0_CFG19, 0x40010453 +.set CYREG_B0_P2_U0_CFG20, 0x40010454 +.set CYREG_B0_P2_U0_CFG21, 0x40010455 +.set CYREG_B0_P2_U0_CFG22, 0x40010456 +.set CYREG_B0_P2_U0_CFG23, 0x40010457 +.set CYREG_B0_P2_U0_CFG24, 0x40010458 +.set CYREG_B0_P2_U0_CFG25, 0x40010459 +.set CYREG_B0_P2_U0_CFG26, 0x4001045a +.set CYREG_B0_P2_U0_CFG27, 0x4001045b +.set CYREG_B0_P2_U0_CFG28, 0x4001045c +.set CYREG_B0_P2_U0_CFG29, 0x4001045d +.set CYREG_B0_P2_U0_CFG30, 0x4001045e +.set CYREG_B0_P2_U0_CFG31, 0x4001045f +.set CYREG_B0_P2_U0_DCFG0, 0x40010460 +.set CYREG_B0_P2_U0_DCFG1, 0x40010462 +.set CYREG_B0_P2_U0_DCFG2, 0x40010464 +.set CYREG_B0_P2_U0_DCFG3, 0x40010466 +.set CYREG_B0_P2_U0_DCFG4, 0x40010468 +.set CYREG_B0_P2_U0_DCFG5, 0x4001046a +.set CYREG_B0_P2_U0_DCFG6, 0x4001046c +.set CYREG_B0_P2_U0_DCFG7, 0x4001046e +.set CYDEV_UCFG_B0_P2_U1_BASE, 0x40010480 +.set CYDEV_UCFG_B0_P2_U1_SIZE, 0x00000070 +.set CYREG_B0_P2_U1_PLD_IT0, 0x40010480 +.set CYREG_B0_P2_U1_PLD_IT1, 0x40010484 +.set CYREG_B0_P2_U1_PLD_IT2, 0x40010488 +.set CYREG_B0_P2_U1_PLD_IT3, 0x4001048c +.set CYREG_B0_P2_U1_PLD_IT4, 0x40010490 +.set CYREG_B0_P2_U1_PLD_IT5, 0x40010494 +.set CYREG_B0_P2_U1_PLD_IT6, 0x40010498 +.set CYREG_B0_P2_U1_PLD_IT7, 0x4001049c +.set CYREG_B0_P2_U1_PLD_IT8, 0x400104a0 +.set CYREG_B0_P2_U1_PLD_IT9, 0x400104a4 +.set CYREG_B0_P2_U1_PLD_IT10, 0x400104a8 +.set CYREG_B0_P2_U1_PLD_IT11, 0x400104ac +.set CYREG_B0_P2_U1_PLD_ORT0, 0x400104b0 +.set CYREG_B0_P2_U1_PLD_ORT1, 0x400104b2 +.set CYREG_B0_P2_U1_PLD_ORT2, 0x400104b4 +.set CYREG_B0_P2_U1_PLD_ORT3, 0x400104b6 +.set CYREG_B0_P2_U1_MC_CFG_CEN_CONST, 0x400104b8 +.set CYREG_B0_P2_U1_MC_CFG_XORFB, 0x400104ba +.set CYREG_B0_P2_U1_MC_CFG_SET_RESET, 0x400104bc +.set CYREG_B0_P2_U1_MC_CFG_BYPASS, 0x400104be +.set CYREG_B0_P2_U1_CFG0, 0x400104c0 +.set CYREG_B0_P2_U1_CFG1, 0x400104c1 +.set CYREG_B0_P2_U1_CFG2, 0x400104c2 +.set CYREG_B0_P2_U1_CFG3, 0x400104c3 +.set CYREG_B0_P2_U1_CFG4, 0x400104c4 +.set CYREG_B0_P2_U1_CFG5, 0x400104c5 +.set CYREG_B0_P2_U1_CFG6, 0x400104c6 +.set CYREG_B0_P2_U1_CFG7, 0x400104c7 +.set CYREG_B0_P2_U1_CFG8, 0x400104c8 +.set CYREG_B0_P2_U1_CFG9, 0x400104c9 +.set CYREG_B0_P2_U1_CFG10, 0x400104ca +.set CYREG_B0_P2_U1_CFG11, 0x400104cb +.set CYREG_B0_P2_U1_CFG12, 0x400104cc +.set CYREG_B0_P2_U1_CFG13, 0x400104cd +.set CYREG_B0_P2_U1_CFG14, 0x400104ce +.set CYREG_B0_P2_U1_CFG15, 0x400104cf +.set CYREG_B0_P2_U1_CFG16, 0x400104d0 +.set CYREG_B0_P2_U1_CFG17, 0x400104d1 +.set CYREG_B0_P2_U1_CFG18, 0x400104d2 +.set CYREG_B0_P2_U1_CFG19, 0x400104d3 +.set CYREG_B0_P2_U1_CFG20, 0x400104d4 +.set CYREG_B0_P2_U1_CFG21, 0x400104d5 +.set CYREG_B0_P2_U1_CFG22, 0x400104d6 +.set CYREG_B0_P2_U1_CFG23, 0x400104d7 +.set CYREG_B0_P2_U1_CFG24, 0x400104d8 +.set CYREG_B0_P2_U1_CFG25, 0x400104d9 +.set CYREG_B0_P2_U1_CFG26, 0x400104da +.set CYREG_B0_P2_U1_CFG27, 0x400104db +.set CYREG_B0_P2_U1_CFG28, 0x400104dc +.set CYREG_B0_P2_U1_CFG29, 0x400104dd +.set CYREG_B0_P2_U1_CFG30, 0x400104de +.set CYREG_B0_P2_U1_CFG31, 0x400104df +.set CYREG_B0_P2_U1_DCFG0, 0x400104e0 +.set CYREG_B0_P2_U1_DCFG1, 0x400104e2 +.set CYREG_B0_P2_U1_DCFG2, 0x400104e4 +.set CYREG_B0_P2_U1_DCFG3, 0x400104e6 +.set CYREG_B0_P2_U1_DCFG4, 0x400104e8 +.set CYREG_B0_P2_U1_DCFG5, 0x400104ea +.set CYREG_B0_P2_U1_DCFG6, 0x400104ec +.set CYREG_B0_P2_U1_DCFG7, 0x400104ee +.set CYDEV_UCFG_B0_P2_ROUTE_BASE, 0x40010500 +.set CYDEV_UCFG_B0_P2_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P3_BASE, 0x40010600 +.set CYDEV_UCFG_B0_P3_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P3_U0_BASE, 0x40010600 +.set CYDEV_UCFG_B0_P3_U0_SIZE, 0x00000070 +.set CYREG_B0_P3_U0_PLD_IT0, 0x40010600 +.set CYREG_B0_P3_U0_PLD_IT1, 0x40010604 +.set CYREG_B0_P3_U0_PLD_IT2, 0x40010608 +.set CYREG_B0_P3_U0_PLD_IT3, 0x4001060c +.set CYREG_B0_P3_U0_PLD_IT4, 0x40010610 +.set CYREG_B0_P3_U0_PLD_IT5, 0x40010614 +.set CYREG_B0_P3_U0_PLD_IT6, 0x40010618 +.set CYREG_B0_P3_U0_PLD_IT7, 0x4001061c +.set CYREG_B0_P3_U0_PLD_IT8, 0x40010620 +.set CYREG_B0_P3_U0_PLD_IT9, 0x40010624 +.set CYREG_B0_P3_U0_PLD_IT10, 0x40010628 +.set CYREG_B0_P3_U0_PLD_IT11, 0x4001062c +.set CYREG_B0_P3_U0_PLD_ORT0, 0x40010630 +.set CYREG_B0_P3_U0_PLD_ORT1, 0x40010632 +.set CYREG_B0_P3_U0_PLD_ORT2, 0x40010634 +.set CYREG_B0_P3_U0_PLD_ORT3, 0x40010636 +.set CYREG_B0_P3_U0_MC_CFG_CEN_CONST, 0x40010638 +.set CYREG_B0_P3_U0_MC_CFG_XORFB, 0x4001063a +.set CYREG_B0_P3_U0_MC_CFG_SET_RESET, 0x4001063c +.set CYREG_B0_P3_U0_MC_CFG_BYPASS, 0x4001063e +.set CYREG_B0_P3_U0_CFG0, 0x40010640 +.set CYREG_B0_P3_U0_CFG1, 0x40010641 +.set CYREG_B0_P3_U0_CFG2, 0x40010642 +.set CYREG_B0_P3_U0_CFG3, 0x40010643 +.set CYREG_B0_P3_U0_CFG4, 0x40010644 +.set CYREG_B0_P3_U0_CFG5, 0x40010645 +.set CYREG_B0_P3_U0_CFG6, 0x40010646 +.set CYREG_B0_P3_U0_CFG7, 0x40010647 +.set CYREG_B0_P3_U0_CFG8, 0x40010648 +.set CYREG_B0_P3_U0_CFG9, 0x40010649 +.set CYREG_B0_P3_U0_CFG10, 0x4001064a +.set CYREG_B0_P3_U0_CFG11, 0x4001064b +.set CYREG_B0_P3_U0_CFG12, 0x4001064c +.set CYREG_B0_P3_U0_CFG13, 0x4001064d +.set CYREG_B0_P3_U0_CFG14, 0x4001064e +.set CYREG_B0_P3_U0_CFG15, 0x4001064f +.set CYREG_B0_P3_U0_CFG16, 0x40010650 +.set CYREG_B0_P3_U0_CFG17, 0x40010651 +.set CYREG_B0_P3_U0_CFG18, 0x40010652 +.set CYREG_B0_P3_U0_CFG19, 0x40010653 +.set CYREG_B0_P3_U0_CFG20, 0x40010654 +.set CYREG_B0_P3_U0_CFG21, 0x40010655 +.set CYREG_B0_P3_U0_CFG22, 0x40010656 +.set CYREG_B0_P3_U0_CFG23, 0x40010657 +.set CYREG_B0_P3_U0_CFG24, 0x40010658 +.set CYREG_B0_P3_U0_CFG25, 0x40010659 +.set CYREG_B0_P3_U0_CFG26, 0x4001065a +.set CYREG_B0_P3_U0_CFG27, 0x4001065b +.set CYREG_B0_P3_U0_CFG28, 0x4001065c +.set CYREG_B0_P3_U0_CFG29, 0x4001065d +.set CYREG_B0_P3_U0_CFG30, 0x4001065e +.set CYREG_B0_P3_U0_CFG31, 0x4001065f +.set CYREG_B0_P3_U0_DCFG0, 0x40010660 +.set CYREG_B0_P3_U0_DCFG1, 0x40010662 +.set CYREG_B0_P3_U0_DCFG2, 0x40010664 +.set CYREG_B0_P3_U0_DCFG3, 0x40010666 +.set CYREG_B0_P3_U0_DCFG4, 0x40010668 +.set CYREG_B0_P3_U0_DCFG5, 0x4001066a +.set CYREG_B0_P3_U0_DCFG6, 0x4001066c +.set CYREG_B0_P3_U0_DCFG7, 0x4001066e +.set CYDEV_UCFG_B0_P3_U1_BASE, 0x40010680 +.set CYDEV_UCFG_B0_P3_U1_SIZE, 0x00000070 +.set CYREG_B0_P3_U1_PLD_IT0, 0x40010680 +.set CYREG_B0_P3_U1_PLD_IT1, 0x40010684 +.set CYREG_B0_P3_U1_PLD_IT2, 0x40010688 +.set CYREG_B0_P3_U1_PLD_IT3, 0x4001068c +.set CYREG_B0_P3_U1_PLD_IT4, 0x40010690 +.set CYREG_B0_P3_U1_PLD_IT5, 0x40010694 +.set CYREG_B0_P3_U1_PLD_IT6, 0x40010698 +.set CYREG_B0_P3_U1_PLD_IT7, 0x4001069c +.set CYREG_B0_P3_U1_PLD_IT8, 0x400106a0 +.set CYREG_B0_P3_U1_PLD_IT9, 0x400106a4 +.set CYREG_B0_P3_U1_PLD_IT10, 0x400106a8 +.set CYREG_B0_P3_U1_PLD_IT11, 0x400106ac +.set CYREG_B0_P3_U1_PLD_ORT0, 0x400106b0 +.set CYREG_B0_P3_U1_PLD_ORT1, 0x400106b2 +.set CYREG_B0_P3_U1_PLD_ORT2, 0x400106b4 +.set CYREG_B0_P3_U1_PLD_ORT3, 0x400106b6 +.set CYREG_B0_P3_U1_MC_CFG_CEN_CONST, 0x400106b8 +.set CYREG_B0_P3_U1_MC_CFG_XORFB, 0x400106ba +.set CYREG_B0_P3_U1_MC_CFG_SET_RESET, 0x400106bc +.set CYREG_B0_P3_U1_MC_CFG_BYPASS, 0x400106be +.set CYREG_B0_P3_U1_CFG0, 0x400106c0 +.set CYREG_B0_P3_U1_CFG1, 0x400106c1 +.set CYREG_B0_P3_U1_CFG2, 0x400106c2 +.set CYREG_B0_P3_U1_CFG3, 0x400106c3 +.set CYREG_B0_P3_U1_CFG4, 0x400106c4 +.set CYREG_B0_P3_U1_CFG5, 0x400106c5 +.set CYREG_B0_P3_U1_CFG6, 0x400106c6 +.set CYREG_B0_P3_U1_CFG7, 0x400106c7 +.set CYREG_B0_P3_U1_CFG8, 0x400106c8 +.set CYREG_B0_P3_U1_CFG9, 0x400106c9 +.set CYREG_B0_P3_U1_CFG10, 0x400106ca +.set CYREG_B0_P3_U1_CFG11, 0x400106cb +.set CYREG_B0_P3_U1_CFG12, 0x400106cc +.set CYREG_B0_P3_U1_CFG13, 0x400106cd +.set CYREG_B0_P3_U1_CFG14, 0x400106ce +.set CYREG_B0_P3_U1_CFG15, 0x400106cf +.set CYREG_B0_P3_U1_CFG16, 0x400106d0 +.set CYREG_B0_P3_U1_CFG17, 0x400106d1 +.set CYREG_B0_P3_U1_CFG18, 0x400106d2 +.set CYREG_B0_P3_U1_CFG19, 0x400106d3 +.set CYREG_B0_P3_U1_CFG20, 0x400106d4 +.set CYREG_B0_P3_U1_CFG21, 0x400106d5 +.set CYREG_B0_P3_U1_CFG22, 0x400106d6 +.set CYREG_B0_P3_U1_CFG23, 0x400106d7 +.set CYREG_B0_P3_U1_CFG24, 0x400106d8 +.set CYREG_B0_P3_U1_CFG25, 0x400106d9 +.set CYREG_B0_P3_U1_CFG26, 0x400106da +.set CYREG_B0_P3_U1_CFG27, 0x400106db +.set CYREG_B0_P3_U1_CFG28, 0x400106dc +.set CYREG_B0_P3_U1_CFG29, 0x400106dd +.set CYREG_B0_P3_U1_CFG30, 0x400106de +.set CYREG_B0_P3_U1_CFG31, 0x400106df +.set CYREG_B0_P3_U1_DCFG0, 0x400106e0 +.set CYREG_B0_P3_U1_DCFG1, 0x400106e2 +.set CYREG_B0_P3_U1_DCFG2, 0x400106e4 +.set CYREG_B0_P3_U1_DCFG3, 0x400106e6 +.set CYREG_B0_P3_U1_DCFG4, 0x400106e8 +.set CYREG_B0_P3_U1_DCFG5, 0x400106ea +.set CYREG_B0_P3_U1_DCFG6, 0x400106ec +.set CYREG_B0_P3_U1_DCFG7, 0x400106ee +.set CYDEV_UCFG_B0_P3_ROUTE_BASE, 0x40010700 +.set CYDEV_UCFG_B0_P3_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P4_BASE, 0x40010800 +.set CYDEV_UCFG_B0_P4_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P4_U0_BASE, 0x40010800 +.set CYDEV_UCFG_B0_P4_U0_SIZE, 0x00000070 +.set CYREG_B0_P4_U0_PLD_IT0, 0x40010800 +.set CYREG_B0_P4_U0_PLD_IT1, 0x40010804 +.set CYREG_B0_P4_U0_PLD_IT2, 0x40010808 +.set CYREG_B0_P4_U0_PLD_IT3, 0x4001080c +.set CYREG_B0_P4_U0_PLD_IT4, 0x40010810 +.set CYREG_B0_P4_U0_PLD_IT5, 0x40010814 +.set CYREG_B0_P4_U0_PLD_IT6, 0x40010818 +.set CYREG_B0_P4_U0_PLD_IT7, 0x4001081c +.set CYREG_B0_P4_U0_PLD_IT8, 0x40010820 +.set CYREG_B0_P4_U0_PLD_IT9, 0x40010824 +.set CYREG_B0_P4_U0_PLD_IT10, 0x40010828 +.set CYREG_B0_P4_U0_PLD_IT11, 0x4001082c +.set CYREG_B0_P4_U0_PLD_ORT0, 0x40010830 +.set CYREG_B0_P4_U0_PLD_ORT1, 0x40010832 +.set CYREG_B0_P4_U0_PLD_ORT2, 0x40010834 +.set CYREG_B0_P4_U0_PLD_ORT3, 0x40010836 +.set CYREG_B0_P4_U0_MC_CFG_CEN_CONST, 0x40010838 +.set CYREG_B0_P4_U0_MC_CFG_XORFB, 0x4001083a +.set CYREG_B0_P4_U0_MC_CFG_SET_RESET, 0x4001083c +.set CYREG_B0_P4_U0_MC_CFG_BYPASS, 0x4001083e +.set CYREG_B0_P4_U0_CFG0, 0x40010840 +.set CYREG_B0_P4_U0_CFG1, 0x40010841 +.set CYREG_B0_P4_U0_CFG2, 0x40010842 +.set CYREG_B0_P4_U0_CFG3, 0x40010843 +.set CYREG_B0_P4_U0_CFG4, 0x40010844 +.set CYREG_B0_P4_U0_CFG5, 0x40010845 +.set CYREG_B0_P4_U0_CFG6, 0x40010846 +.set CYREG_B0_P4_U0_CFG7, 0x40010847 +.set CYREG_B0_P4_U0_CFG8, 0x40010848 +.set CYREG_B0_P4_U0_CFG9, 0x40010849 +.set CYREG_B0_P4_U0_CFG10, 0x4001084a +.set CYREG_B0_P4_U0_CFG11, 0x4001084b +.set CYREG_B0_P4_U0_CFG12, 0x4001084c +.set CYREG_B0_P4_U0_CFG13, 0x4001084d +.set CYREG_B0_P4_U0_CFG14, 0x4001084e +.set CYREG_B0_P4_U0_CFG15, 0x4001084f +.set CYREG_B0_P4_U0_CFG16, 0x40010850 +.set CYREG_B0_P4_U0_CFG17, 0x40010851 +.set CYREG_B0_P4_U0_CFG18, 0x40010852 +.set CYREG_B0_P4_U0_CFG19, 0x40010853 +.set CYREG_B0_P4_U0_CFG20, 0x40010854 +.set CYREG_B0_P4_U0_CFG21, 0x40010855 +.set CYREG_B0_P4_U0_CFG22, 0x40010856 +.set CYREG_B0_P4_U0_CFG23, 0x40010857 +.set CYREG_B0_P4_U0_CFG24, 0x40010858 +.set CYREG_B0_P4_U0_CFG25, 0x40010859 +.set CYREG_B0_P4_U0_CFG26, 0x4001085a +.set CYREG_B0_P4_U0_CFG27, 0x4001085b +.set CYREG_B0_P4_U0_CFG28, 0x4001085c +.set CYREG_B0_P4_U0_CFG29, 0x4001085d +.set CYREG_B0_P4_U0_CFG30, 0x4001085e +.set CYREG_B0_P4_U0_CFG31, 0x4001085f +.set CYREG_B0_P4_U0_DCFG0, 0x40010860 +.set CYREG_B0_P4_U0_DCFG1, 0x40010862 +.set CYREG_B0_P4_U0_DCFG2, 0x40010864 +.set CYREG_B0_P4_U0_DCFG3, 0x40010866 +.set CYREG_B0_P4_U0_DCFG4, 0x40010868 +.set CYREG_B0_P4_U0_DCFG5, 0x4001086a +.set CYREG_B0_P4_U0_DCFG6, 0x4001086c +.set CYREG_B0_P4_U0_DCFG7, 0x4001086e +.set CYDEV_UCFG_B0_P4_U1_BASE, 0x40010880 +.set CYDEV_UCFG_B0_P4_U1_SIZE, 0x00000070 +.set CYREG_B0_P4_U1_PLD_IT0, 0x40010880 +.set CYREG_B0_P4_U1_PLD_IT1, 0x40010884 +.set CYREG_B0_P4_U1_PLD_IT2, 0x40010888 +.set CYREG_B0_P4_U1_PLD_IT3, 0x4001088c +.set CYREG_B0_P4_U1_PLD_IT4, 0x40010890 +.set CYREG_B0_P4_U1_PLD_IT5, 0x40010894 +.set CYREG_B0_P4_U1_PLD_IT6, 0x40010898 +.set CYREG_B0_P4_U1_PLD_IT7, 0x4001089c +.set CYREG_B0_P4_U1_PLD_IT8, 0x400108a0 +.set CYREG_B0_P4_U1_PLD_IT9, 0x400108a4 +.set CYREG_B0_P4_U1_PLD_IT10, 0x400108a8 +.set CYREG_B0_P4_U1_PLD_IT11, 0x400108ac +.set CYREG_B0_P4_U1_PLD_ORT0, 0x400108b0 +.set CYREG_B0_P4_U1_PLD_ORT1, 0x400108b2 +.set CYREG_B0_P4_U1_PLD_ORT2, 0x400108b4 +.set CYREG_B0_P4_U1_PLD_ORT3, 0x400108b6 +.set CYREG_B0_P4_U1_MC_CFG_CEN_CONST, 0x400108b8 +.set CYREG_B0_P4_U1_MC_CFG_XORFB, 0x400108ba +.set CYREG_B0_P4_U1_MC_CFG_SET_RESET, 0x400108bc +.set CYREG_B0_P4_U1_MC_CFG_BYPASS, 0x400108be +.set CYREG_B0_P4_U1_CFG0, 0x400108c0 +.set CYREG_B0_P4_U1_CFG1, 0x400108c1 +.set CYREG_B0_P4_U1_CFG2, 0x400108c2 +.set CYREG_B0_P4_U1_CFG3, 0x400108c3 +.set CYREG_B0_P4_U1_CFG4, 0x400108c4 +.set CYREG_B0_P4_U1_CFG5, 0x400108c5 +.set CYREG_B0_P4_U1_CFG6, 0x400108c6 +.set CYREG_B0_P4_U1_CFG7, 0x400108c7 +.set CYREG_B0_P4_U1_CFG8, 0x400108c8 +.set CYREG_B0_P4_U1_CFG9, 0x400108c9 +.set CYREG_B0_P4_U1_CFG10, 0x400108ca +.set CYREG_B0_P4_U1_CFG11, 0x400108cb +.set CYREG_B0_P4_U1_CFG12, 0x400108cc +.set CYREG_B0_P4_U1_CFG13, 0x400108cd +.set CYREG_B0_P4_U1_CFG14, 0x400108ce +.set CYREG_B0_P4_U1_CFG15, 0x400108cf +.set CYREG_B0_P4_U1_CFG16, 0x400108d0 +.set CYREG_B0_P4_U1_CFG17, 0x400108d1 +.set CYREG_B0_P4_U1_CFG18, 0x400108d2 +.set CYREG_B0_P4_U1_CFG19, 0x400108d3 +.set CYREG_B0_P4_U1_CFG20, 0x400108d4 +.set CYREG_B0_P4_U1_CFG21, 0x400108d5 +.set CYREG_B0_P4_U1_CFG22, 0x400108d6 +.set CYREG_B0_P4_U1_CFG23, 0x400108d7 +.set CYREG_B0_P4_U1_CFG24, 0x400108d8 +.set CYREG_B0_P4_U1_CFG25, 0x400108d9 +.set CYREG_B0_P4_U1_CFG26, 0x400108da +.set CYREG_B0_P4_U1_CFG27, 0x400108db +.set CYREG_B0_P4_U1_CFG28, 0x400108dc +.set CYREG_B0_P4_U1_CFG29, 0x400108dd +.set CYREG_B0_P4_U1_CFG30, 0x400108de +.set CYREG_B0_P4_U1_CFG31, 0x400108df +.set CYREG_B0_P4_U1_DCFG0, 0x400108e0 +.set CYREG_B0_P4_U1_DCFG1, 0x400108e2 +.set CYREG_B0_P4_U1_DCFG2, 0x400108e4 +.set CYREG_B0_P4_U1_DCFG3, 0x400108e6 +.set CYREG_B0_P4_U1_DCFG4, 0x400108e8 +.set CYREG_B0_P4_U1_DCFG5, 0x400108ea +.set CYREG_B0_P4_U1_DCFG6, 0x400108ec +.set CYREG_B0_P4_U1_DCFG7, 0x400108ee +.set CYDEV_UCFG_B0_P4_ROUTE_BASE, 0x40010900 +.set CYDEV_UCFG_B0_P4_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P5_BASE, 0x40010a00 +.set CYDEV_UCFG_B0_P5_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P5_U0_BASE, 0x40010a00 +.set CYDEV_UCFG_B0_P5_U0_SIZE, 0x00000070 +.set CYREG_B0_P5_U0_PLD_IT0, 0x40010a00 +.set CYREG_B0_P5_U0_PLD_IT1, 0x40010a04 +.set CYREG_B0_P5_U0_PLD_IT2, 0x40010a08 +.set CYREG_B0_P5_U0_PLD_IT3, 0x40010a0c +.set CYREG_B0_P5_U0_PLD_IT4, 0x40010a10 +.set CYREG_B0_P5_U0_PLD_IT5, 0x40010a14 +.set CYREG_B0_P5_U0_PLD_IT6, 0x40010a18 +.set CYREG_B0_P5_U0_PLD_IT7, 0x40010a1c +.set CYREG_B0_P5_U0_PLD_IT8, 0x40010a20 +.set CYREG_B0_P5_U0_PLD_IT9, 0x40010a24 +.set CYREG_B0_P5_U0_PLD_IT10, 0x40010a28 +.set CYREG_B0_P5_U0_PLD_IT11, 0x40010a2c +.set CYREG_B0_P5_U0_PLD_ORT0, 0x40010a30 +.set CYREG_B0_P5_U0_PLD_ORT1, 0x40010a32 +.set CYREG_B0_P5_U0_PLD_ORT2, 0x40010a34 +.set CYREG_B0_P5_U0_PLD_ORT3, 0x40010a36 +.set CYREG_B0_P5_U0_MC_CFG_CEN_CONST, 0x40010a38 +.set CYREG_B0_P5_U0_MC_CFG_XORFB, 0x40010a3a +.set CYREG_B0_P5_U0_MC_CFG_SET_RESET, 0x40010a3c +.set CYREG_B0_P5_U0_MC_CFG_BYPASS, 0x40010a3e +.set CYREG_B0_P5_U0_CFG0, 0x40010a40 +.set CYREG_B0_P5_U0_CFG1, 0x40010a41 +.set CYREG_B0_P5_U0_CFG2, 0x40010a42 +.set CYREG_B0_P5_U0_CFG3, 0x40010a43 +.set CYREG_B0_P5_U0_CFG4, 0x40010a44 +.set CYREG_B0_P5_U0_CFG5, 0x40010a45 +.set CYREG_B0_P5_U0_CFG6, 0x40010a46 +.set CYREG_B0_P5_U0_CFG7, 0x40010a47 +.set CYREG_B0_P5_U0_CFG8, 0x40010a48 +.set CYREG_B0_P5_U0_CFG9, 0x40010a49 +.set CYREG_B0_P5_U0_CFG10, 0x40010a4a +.set CYREG_B0_P5_U0_CFG11, 0x40010a4b +.set CYREG_B0_P5_U0_CFG12, 0x40010a4c +.set CYREG_B0_P5_U0_CFG13, 0x40010a4d +.set CYREG_B0_P5_U0_CFG14, 0x40010a4e +.set CYREG_B0_P5_U0_CFG15, 0x40010a4f +.set CYREG_B0_P5_U0_CFG16, 0x40010a50 +.set CYREG_B0_P5_U0_CFG17, 0x40010a51 +.set CYREG_B0_P5_U0_CFG18, 0x40010a52 +.set CYREG_B0_P5_U0_CFG19, 0x40010a53 +.set CYREG_B0_P5_U0_CFG20, 0x40010a54 +.set CYREG_B0_P5_U0_CFG21, 0x40010a55 +.set CYREG_B0_P5_U0_CFG22, 0x40010a56 +.set CYREG_B0_P5_U0_CFG23, 0x40010a57 +.set CYREG_B0_P5_U0_CFG24, 0x40010a58 +.set CYREG_B0_P5_U0_CFG25, 0x40010a59 +.set CYREG_B0_P5_U0_CFG26, 0x40010a5a +.set CYREG_B0_P5_U0_CFG27, 0x40010a5b +.set CYREG_B0_P5_U0_CFG28, 0x40010a5c +.set CYREG_B0_P5_U0_CFG29, 0x40010a5d +.set CYREG_B0_P5_U0_CFG30, 0x40010a5e +.set CYREG_B0_P5_U0_CFG31, 0x40010a5f +.set CYREG_B0_P5_U0_DCFG0, 0x40010a60 +.set CYREG_B0_P5_U0_DCFG1, 0x40010a62 +.set CYREG_B0_P5_U0_DCFG2, 0x40010a64 +.set CYREG_B0_P5_U0_DCFG3, 0x40010a66 +.set CYREG_B0_P5_U0_DCFG4, 0x40010a68 +.set CYREG_B0_P5_U0_DCFG5, 0x40010a6a +.set CYREG_B0_P5_U0_DCFG6, 0x40010a6c +.set CYREG_B0_P5_U0_DCFG7, 0x40010a6e +.set CYDEV_UCFG_B0_P5_U1_BASE, 0x40010a80 +.set CYDEV_UCFG_B0_P5_U1_SIZE, 0x00000070 +.set CYREG_B0_P5_U1_PLD_IT0, 0x40010a80 +.set CYREG_B0_P5_U1_PLD_IT1, 0x40010a84 +.set CYREG_B0_P5_U1_PLD_IT2, 0x40010a88 +.set CYREG_B0_P5_U1_PLD_IT3, 0x40010a8c +.set CYREG_B0_P5_U1_PLD_IT4, 0x40010a90 +.set CYREG_B0_P5_U1_PLD_IT5, 0x40010a94 +.set CYREG_B0_P5_U1_PLD_IT6, 0x40010a98 +.set CYREG_B0_P5_U1_PLD_IT7, 0x40010a9c +.set CYREG_B0_P5_U1_PLD_IT8, 0x40010aa0 +.set CYREG_B0_P5_U1_PLD_IT9, 0x40010aa4 +.set CYREG_B0_P5_U1_PLD_IT10, 0x40010aa8 +.set CYREG_B0_P5_U1_PLD_IT11, 0x40010aac +.set CYREG_B0_P5_U1_PLD_ORT0, 0x40010ab0 +.set CYREG_B0_P5_U1_PLD_ORT1, 0x40010ab2 +.set CYREG_B0_P5_U1_PLD_ORT2, 0x40010ab4 +.set CYREG_B0_P5_U1_PLD_ORT3, 0x40010ab6 +.set CYREG_B0_P5_U1_MC_CFG_CEN_CONST, 0x40010ab8 +.set CYREG_B0_P5_U1_MC_CFG_XORFB, 0x40010aba +.set CYREG_B0_P5_U1_MC_CFG_SET_RESET, 0x40010abc +.set CYREG_B0_P5_U1_MC_CFG_BYPASS, 0x40010abe +.set CYREG_B0_P5_U1_CFG0, 0x40010ac0 +.set CYREG_B0_P5_U1_CFG1, 0x40010ac1 +.set CYREG_B0_P5_U1_CFG2, 0x40010ac2 +.set CYREG_B0_P5_U1_CFG3, 0x40010ac3 +.set CYREG_B0_P5_U1_CFG4, 0x40010ac4 +.set CYREG_B0_P5_U1_CFG5, 0x40010ac5 +.set CYREG_B0_P5_U1_CFG6, 0x40010ac6 +.set CYREG_B0_P5_U1_CFG7, 0x40010ac7 +.set CYREG_B0_P5_U1_CFG8, 0x40010ac8 +.set CYREG_B0_P5_U1_CFG9, 0x40010ac9 +.set CYREG_B0_P5_U1_CFG10, 0x40010aca +.set CYREG_B0_P5_U1_CFG11, 0x40010acb +.set CYREG_B0_P5_U1_CFG12, 0x40010acc +.set CYREG_B0_P5_U1_CFG13, 0x40010acd +.set CYREG_B0_P5_U1_CFG14, 0x40010ace +.set CYREG_B0_P5_U1_CFG15, 0x40010acf +.set CYREG_B0_P5_U1_CFG16, 0x40010ad0 +.set CYREG_B0_P5_U1_CFG17, 0x40010ad1 +.set CYREG_B0_P5_U1_CFG18, 0x40010ad2 +.set CYREG_B0_P5_U1_CFG19, 0x40010ad3 +.set CYREG_B0_P5_U1_CFG20, 0x40010ad4 +.set CYREG_B0_P5_U1_CFG21, 0x40010ad5 +.set CYREG_B0_P5_U1_CFG22, 0x40010ad6 +.set CYREG_B0_P5_U1_CFG23, 0x40010ad7 +.set CYREG_B0_P5_U1_CFG24, 0x40010ad8 +.set CYREG_B0_P5_U1_CFG25, 0x40010ad9 +.set CYREG_B0_P5_U1_CFG26, 0x40010ada +.set CYREG_B0_P5_U1_CFG27, 0x40010adb +.set CYREG_B0_P5_U1_CFG28, 0x40010adc +.set CYREG_B0_P5_U1_CFG29, 0x40010add +.set CYREG_B0_P5_U1_CFG30, 0x40010ade +.set CYREG_B0_P5_U1_CFG31, 0x40010adf +.set CYREG_B0_P5_U1_DCFG0, 0x40010ae0 +.set CYREG_B0_P5_U1_DCFG1, 0x40010ae2 +.set CYREG_B0_P5_U1_DCFG2, 0x40010ae4 +.set CYREG_B0_P5_U1_DCFG3, 0x40010ae6 +.set CYREG_B0_P5_U1_DCFG4, 0x40010ae8 +.set CYREG_B0_P5_U1_DCFG5, 0x40010aea +.set CYREG_B0_P5_U1_DCFG6, 0x40010aec +.set CYREG_B0_P5_U1_DCFG7, 0x40010aee +.set CYDEV_UCFG_B0_P5_ROUTE_BASE, 0x40010b00 +.set CYDEV_UCFG_B0_P5_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P6_BASE, 0x40010c00 +.set CYDEV_UCFG_B0_P6_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P6_U0_BASE, 0x40010c00 +.set CYDEV_UCFG_B0_P6_U0_SIZE, 0x00000070 +.set CYREG_B0_P6_U0_PLD_IT0, 0x40010c00 +.set CYREG_B0_P6_U0_PLD_IT1, 0x40010c04 +.set CYREG_B0_P6_U0_PLD_IT2, 0x40010c08 +.set CYREG_B0_P6_U0_PLD_IT3, 0x40010c0c +.set CYREG_B0_P6_U0_PLD_IT4, 0x40010c10 +.set CYREG_B0_P6_U0_PLD_IT5, 0x40010c14 +.set CYREG_B0_P6_U0_PLD_IT6, 0x40010c18 +.set CYREG_B0_P6_U0_PLD_IT7, 0x40010c1c +.set CYREG_B0_P6_U0_PLD_IT8, 0x40010c20 +.set CYREG_B0_P6_U0_PLD_IT9, 0x40010c24 +.set CYREG_B0_P6_U0_PLD_IT10, 0x40010c28 +.set CYREG_B0_P6_U0_PLD_IT11, 0x40010c2c +.set CYREG_B0_P6_U0_PLD_ORT0, 0x40010c30 +.set CYREG_B0_P6_U0_PLD_ORT1, 0x40010c32 +.set CYREG_B0_P6_U0_PLD_ORT2, 0x40010c34 +.set CYREG_B0_P6_U0_PLD_ORT3, 0x40010c36 +.set CYREG_B0_P6_U0_MC_CFG_CEN_CONST, 0x40010c38 +.set CYREG_B0_P6_U0_MC_CFG_XORFB, 0x40010c3a +.set CYREG_B0_P6_U0_MC_CFG_SET_RESET, 0x40010c3c +.set CYREG_B0_P6_U0_MC_CFG_BYPASS, 0x40010c3e +.set CYREG_B0_P6_U0_CFG0, 0x40010c40 +.set CYREG_B0_P6_U0_CFG1, 0x40010c41 +.set CYREG_B0_P6_U0_CFG2, 0x40010c42 +.set CYREG_B0_P6_U0_CFG3, 0x40010c43 +.set CYREG_B0_P6_U0_CFG4, 0x40010c44 +.set CYREG_B0_P6_U0_CFG5, 0x40010c45 +.set CYREG_B0_P6_U0_CFG6, 0x40010c46 +.set CYREG_B0_P6_U0_CFG7, 0x40010c47 +.set CYREG_B0_P6_U0_CFG8, 0x40010c48 +.set CYREG_B0_P6_U0_CFG9, 0x40010c49 +.set CYREG_B0_P6_U0_CFG10, 0x40010c4a +.set CYREG_B0_P6_U0_CFG11, 0x40010c4b +.set CYREG_B0_P6_U0_CFG12, 0x40010c4c +.set CYREG_B0_P6_U0_CFG13, 0x40010c4d +.set CYREG_B0_P6_U0_CFG14, 0x40010c4e +.set CYREG_B0_P6_U0_CFG15, 0x40010c4f +.set CYREG_B0_P6_U0_CFG16, 0x40010c50 +.set CYREG_B0_P6_U0_CFG17, 0x40010c51 +.set CYREG_B0_P6_U0_CFG18, 0x40010c52 +.set CYREG_B0_P6_U0_CFG19, 0x40010c53 +.set CYREG_B0_P6_U0_CFG20, 0x40010c54 +.set CYREG_B0_P6_U0_CFG21, 0x40010c55 +.set CYREG_B0_P6_U0_CFG22, 0x40010c56 +.set CYREG_B0_P6_U0_CFG23, 0x40010c57 +.set CYREG_B0_P6_U0_CFG24, 0x40010c58 +.set CYREG_B0_P6_U0_CFG25, 0x40010c59 +.set CYREG_B0_P6_U0_CFG26, 0x40010c5a +.set CYREG_B0_P6_U0_CFG27, 0x40010c5b +.set CYREG_B0_P6_U0_CFG28, 0x40010c5c +.set CYREG_B0_P6_U0_CFG29, 0x40010c5d +.set CYREG_B0_P6_U0_CFG30, 0x40010c5e +.set CYREG_B0_P6_U0_CFG31, 0x40010c5f +.set CYREG_B0_P6_U0_DCFG0, 0x40010c60 +.set CYREG_B0_P6_U0_DCFG1, 0x40010c62 +.set CYREG_B0_P6_U0_DCFG2, 0x40010c64 +.set CYREG_B0_P6_U0_DCFG3, 0x40010c66 +.set CYREG_B0_P6_U0_DCFG4, 0x40010c68 +.set CYREG_B0_P6_U0_DCFG5, 0x40010c6a +.set CYREG_B0_P6_U0_DCFG6, 0x40010c6c +.set CYREG_B0_P6_U0_DCFG7, 0x40010c6e +.set CYDEV_UCFG_B0_P6_U1_BASE, 0x40010c80 +.set CYDEV_UCFG_B0_P6_U1_SIZE, 0x00000070 +.set CYREG_B0_P6_U1_PLD_IT0, 0x40010c80 +.set CYREG_B0_P6_U1_PLD_IT1, 0x40010c84 +.set CYREG_B0_P6_U1_PLD_IT2, 0x40010c88 +.set CYREG_B0_P6_U1_PLD_IT3, 0x40010c8c +.set CYREG_B0_P6_U1_PLD_IT4, 0x40010c90 +.set CYREG_B0_P6_U1_PLD_IT5, 0x40010c94 +.set CYREG_B0_P6_U1_PLD_IT6, 0x40010c98 +.set CYREG_B0_P6_U1_PLD_IT7, 0x40010c9c +.set CYREG_B0_P6_U1_PLD_IT8, 0x40010ca0 +.set CYREG_B0_P6_U1_PLD_IT9, 0x40010ca4 +.set CYREG_B0_P6_U1_PLD_IT10, 0x40010ca8 +.set CYREG_B0_P6_U1_PLD_IT11, 0x40010cac +.set CYREG_B0_P6_U1_PLD_ORT0, 0x40010cb0 +.set CYREG_B0_P6_U1_PLD_ORT1, 0x40010cb2 +.set CYREG_B0_P6_U1_PLD_ORT2, 0x40010cb4 +.set CYREG_B0_P6_U1_PLD_ORT3, 0x40010cb6 +.set CYREG_B0_P6_U1_MC_CFG_CEN_CONST, 0x40010cb8 +.set CYREG_B0_P6_U1_MC_CFG_XORFB, 0x40010cba +.set CYREG_B0_P6_U1_MC_CFG_SET_RESET, 0x40010cbc +.set CYREG_B0_P6_U1_MC_CFG_BYPASS, 0x40010cbe +.set CYREG_B0_P6_U1_CFG0, 0x40010cc0 +.set CYREG_B0_P6_U1_CFG1, 0x40010cc1 +.set CYREG_B0_P6_U1_CFG2, 0x40010cc2 +.set CYREG_B0_P6_U1_CFG3, 0x40010cc3 +.set CYREG_B0_P6_U1_CFG4, 0x40010cc4 +.set CYREG_B0_P6_U1_CFG5, 0x40010cc5 +.set CYREG_B0_P6_U1_CFG6, 0x40010cc6 +.set CYREG_B0_P6_U1_CFG7, 0x40010cc7 +.set CYREG_B0_P6_U1_CFG8, 0x40010cc8 +.set CYREG_B0_P6_U1_CFG9, 0x40010cc9 +.set CYREG_B0_P6_U1_CFG10, 0x40010cca +.set CYREG_B0_P6_U1_CFG11, 0x40010ccb +.set CYREG_B0_P6_U1_CFG12, 0x40010ccc +.set CYREG_B0_P6_U1_CFG13, 0x40010ccd +.set CYREG_B0_P6_U1_CFG14, 0x40010cce +.set CYREG_B0_P6_U1_CFG15, 0x40010ccf +.set CYREG_B0_P6_U1_CFG16, 0x40010cd0 +.set CYREG_B0_P6_U1_CFG17, 0x40010cd1 +.set CYREG_B0_P6_U1_CFG18, 0x40010cd2 +.set CYREG_B0_P6_U1_CFG19, 0x40010cd3 +.set CYREG_B0_P6_U1_CFG20, 0x40010cd4 +.set CYREG_B0_P6_U1_CFG21, 0x40010cd5 +.set CYREG_B0_P6_U1_CFG22, 0x40010cd6 +.set CYREG_B0_P6_U1_CFG23, 0x40010cd7 +.set CYREG_B0_P6_U1_CFG24, 0x40010cd8 +.set CYREG_B0_P6_U1_CFG25, 0x40010cd9 +.set CYREG_B0_P6_U1_CFG26, 0x40010cda +.set CYREG_B0_P6_U1_CFG27, 0x40010cdb +.set CYREG_B0_P6_U1_CFG28, 0x40010cdc +.set CYREG_B0_P6_U1_CFG29, 0x40010cdd +.set CYREG_B0_P6_U1_CFG30, 0x40010cde +.set CYREG_B0_P6_U1_CFG31, 0x40010cdf +.set CYREG_B0_P6_U1_DCFG0, 0x40010ce0 +.set CYREG_B0_P6_U1_DCFG1, 0x40010ce2 +.set CYREG_B0_P6_U1_DCFG2, 0x40010ce4 +.set CYREG_B0_P6_U1_DCFG3, 0x40010ce6 +.set CYREG_B0_P6_U1_DCFG4, 0x40010ce8 +.set CYREG_B0_P6_U1_DCFG5, 0x40010cea +.set CYREG_B0_P6_U1_DCFG6, 0x40010cec +.set CYREG_B0_P6_U1_DCFG7, 0x40010cee +.set CYDEV_UCFG_B0_P6_ROUTE_BASE, 0x40010d00 +.set CYDEV_UCFG_B0_P6_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P7_BASE, 0x40010e00 +.set CYDEV_UCFG_B0_P7_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P7_U0_BASE, 0x40010e00 +.set CYDEV_UCFG_B0_P7_U0_SIZE, 0x00000070 +.set CYREG_B0_P7_U0_PLD_IT0, 0x40010e00 +.set CYREG_B0_P7_U0_PLD_IT1, 0x40010e04 +.set CYREG_B0_P7_U0_PLD_IT2, 0x40010e08 +.set CYREG_B0_P7_U0_PLD_IT3, 0x40010e0c +.set CYREG_B0_P7_U0_PLD_IT4, 0x40010e10 +.set CYREG_B0_P7_U0_PLD_IT5, 0x40010e14 +.set CYREG_B0_P7_U0_PLD_IT6, 0x40010e18 +.set CYREG_B0_P7_U0_PLD_IT7, 0x40010e1c +.set CYREG_B0_P7_U0_PLD_IT8, 0x40010e20 +.set CYREG_B0_P7_U0_PLD_IT9, 0x40010e24 +.set CYREG_B0_P7_U0_PLD_IT10, 0x40010e28 +.set CYREG_B0_P7_U0_PLD_IT11, 0x40010e2c +.set CYREG_B0_P7_U0_PLD_ORT0, 0x40010e30 +.set CYREG_B0_P7_U0_PLD_ORT1, 0x40010e32 +.set CYREG_B0_P7_U0_PLD_ORT2, 0x40010e34 +.set CYREG_B0_P7_U0_PLD_ORT3, 0x40010e36 +.set CYREG_B0_P7_U0_MC_CFG_CEN_CONST, 0x40010e38 +.set CYREG_B0_P7_U0_MC_CFG_XORFB, 0x40010e3a +.set CYREG_B0_P7_U0_MC_CFG_SET_RESET, 0x40010e3c +.set CYREG_B0_P7_U0_MC_CFG_BYPASS, 0x40010e3e +.set CYREG_B0_P7_U0_CFG0, 0x40010e40 +.set CYREG_B0_P7_U0_CFG1, 0x40010e41 +.set CYREG_B0_P7_U0_CFG2, 0x40010e42 +.set CYREG_B0_P7_U0_CFG3, 0x40010e43 +.set CYREG_B0_P7_U0_CFG4, 0x40010e44 +.set CYREG_B0_P7_U0_CFG5, 0x40010e45 +.set CYREG_B0_P7_U0_CFG6, 0x40010e46 +.set CYREG_B0_P7_U0_CFG7, 0x40010e47 +.set CYREG_B0_P7_U0_CFG8, 0x40010e48 +.set CYREG_B0_P7_U0_CFG9, 0x40010e49 +.set CYREG_B0_P7_U0_CFG10, 0x40010e4a +.set CYREG_B0_P7_U0_CFG11, 0x40010e4b +.set CYREG_B0_P7_U0_CFG12, 0x40010e4c +.set CYREG_B0_P7_U0_CFG13, 0x40010e4d +.set CYREG_B0_P7_U0_CFG14, 0x40010e4e +.set CYREG_B0_P7_U0_CFG15, 0x40010e4f +.set CYREG_B0_P7_U0_CFG16, 0x40010e50 +.set CYREG_B0_P7_U0_CFG17, 0x40010e51 +.set CYREG_B0_P7_U0_CFG18, 0x40010e52 +.set CYREG_B0_P7_U0_CFG19, 0x40010e53 +.set CYREG_B0_P7_U0_CFG20, 0x40010e54 +.set CYREG_B0_P7_U0_CFG21, 0x40010e55 +.set CYREG_B0_P7_U0_CFG22, 0x40010e56 +.set CYREG_B0_P7_U0_CFG23, 0x40010e57 +.set CYREG_B0_P7_U0_CFG24, 0x40010e58 +.set CYREG_B0_P7_U0_CFG25, 0x40010e59 +.set CYREG_B0_P7_U0_CFG26, 0x40010e5a +.set CYREG_B0_P7_U0_CFG27, 0x40010e5b +.set CYREG_B0_P7_U0_CFG28, 0x40010e5c +.set CYREG_B0_P7_U0_CFG29, 0x40010e5d +.set CYREG_B0_P7_U0_CFG30, 0x40010e5e +.set CYREG_B0_P7_U0_CFG31, 0x40010e5f +.set CYREG_B0_P7_U0_DCFG0, 0x40010e60 +.set CYREG_B0_P7_U0_DCFG1, 0x40010e62 +.set CYREG_B0_P7_U0_DCFG2, 0x40010e64 +.set CYREG_B0_P7_U0_DCFG3, 0x40010e66 +.set CYREG_B0_P7_U0_DCFG4, 0x40010e68 +.set CYREG_B0_P7_U0_DCFG5, 0x40010e6a +.set CYREG_B0_P7_U0_DCFG6, 0x40010e6c +.set CYREG_B0_P7_U0_DCFG7, 0x40010e6e +.set CYDEV_UCFG_B0_P7_U1_BASE, 0x40010e80 +.set CYDEV_UCFG_B0_P7_U1_SIZE, 0x00000070 +.set CYREG_B0_P7_U1_PLD_IT0, 0x40010e80 +.set CYREG_B0_P7_U1_PLD_IT1, 0x40010e84 +.set CYREG_B0_P7_U1_PLD_IT2, 0x40010e88 +.set CYREG_B0_P7_U1_PLD_IT3, 0x40010e8c +.set CYREG_B0_P7_U1_PLD_IT4, 0x40010e90 +.set CYREG_B0_P7_U1_PLD_IT5, 0x40010e94 +.set CYREG_B0_P7_U1_PLD_IT6, 0x40010e98 +.set CYREG_B0_P7_U1_PLD_IT7, 0x40010e9c +.set CYREG_B0_P7_U1_PLD_IT8, 0x40010ea0 +.set CYREG_B0_P7_U1_PLD_IT9, 0x40010ea4 +.set CYREG_B0_P7_U1_PLD_IT10, 0x40010ea8 +.set CYREG_B0_P7_U1_PLD_IT11, 0x40010eac +.set CYREG_B0_P7_U1_PLD_ORT0, 0x40010eb0 +.set CYREG_B0_P7_U1_PLD_ORT1, 0x40010eb2 +.set CYREG_B0_P7_U1_PLD_ORT2, 0x40010eb4 +.set CYREG_B0_P7_U1_PLD_ORT3, 0x40010eb6 +.set CYREG_B0_P7_U1_MC_CFG_CEN_CONST, 0x40010eb8 +.set CYREG_B0_P7_U1_MC_CFG_XORFB, 0x40010eba +.set CYREG_B0_P7_U1_MC_CFG_SET_RESET, 0x40010ebc +.set CYREG_B0_P7_U1_MC_CFG_BYPASS, 0x40010ebe +.set CYREG_B0_P7_U1_CFG0, 0x40010ec0 +.set CYREG_B0_P7_U1_CFG1, 0x40010ec1 +.set CYREG_B0_P7_U1_CFG2, 0x40010ec2 +.set CYREG_B0_P7_U1_CFG3, 0x40010ec3 +.set CYREG_B0_P7_U1_CFG4, 0x40010ec4 +.set CYREG_B0_P7_U1_CFG5, 0x40010ec5 +.set CYREG_B0_P7_U1_CFG6, 0x40010ec6 +.set CYREG_B0_P7_U1_CFG7, 0x40010ec7 +.set CYREG_B0_P7_U1_CFG8, 0x40010ec8 +.set CYREG_B0_P7_U1_CFG9, 0x40010ec9 +.set CYREG_B0_P7_U1_CFG10, 0x40010eca +.set CYREG_B0_P7_U1_CFG11, 0x40010ecb +.set CYREG_B0_P7_U1_CFG12, 0x40010ecc +.set CYREG_B0_P7_U1_CFG13, 0x40010ecd +.set CYREG_B0_P7_U1_CFG14, 0x40010ece +.set CYREG_B0_P7_U1_CFG15, 0x40010ecf +.set CYREG_B0_P7_U1_CFG16, 0x40010ed0 +.set CYREG_B0_P7_U1_CFG17, 0x40010ed1 +.set CYREG_B0_P7_U1_CFG18, 0x40010ed2 +.set CYREG_B0_P7_U1_CFG19, 0x40010ed3 +.set CYREG_B0_P7_U1_CFG20, 0x40010ed4 +.set CYREG_B0_P7_U1_CFG21, 0x40010ed5 +.set CYREG_B0_P7_U1_CFG22, 0x40010ed6 +.set CYREG_B0_P7_U1_CFG23, 0x40010ed7 +.set CYREG_B0_P7_U1_CFG24, 0x40010ed8 +.set CYREG_B0_P7_U1_CFG25, 0x40010ed9 +.set CYREG_B0_P7_U1_CFG26, 0x40010eda +.set CYREG_B0_P7_U1_CFG27, 0x40010edb +.set CYREG_B0_P7_U1_CFG28, 0x40010edc +.set CYREG_B0_P7_U1_CFG29, 0x40010edd +.set CYREG_B0_P7_U1_CFG30, 0x40010ede +.set CYREG_B0_P7_U1_CFG31, 0x40010edf +.set CYREG_B0_P7_U1_DCFG0, 0x40010ee0 +.set CYREG_B0_P7_U1_DCFG1, 0x40010ee2 +.set CYREG_B0_P7_U1_DCFG2, 0x40010ee4 +.set CYREG_B0_P7_U1_DCFG3, 0x40010ee6 +.set CYREG_B0_P7_U1_DCFG4, 0x40010ee8 +.set CYREG_B0_P7_U1_DCFG5, 0x40010eea +.set CYREG_B0_P7_U1_DCFG6, 0x40010eec +.set CYREG_B0_P7_U1_DCFG7, 0x40010eee +.set CYDEV_UCFG_B0_P7_ROUTE_BASE, 0x40010f00 +.set CYDEV_UCFG_B0_P7_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_BASE, 0x40011000 +.set CYDEV_UCFG_B1_SIZE, 0x00000fef +.set CYDEV_UCFG_B1_P2_BASE, 0x40011400 +.set CYDEV_UCFG_B1_P2_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P2_U0_BASE, 0x40011400 +.set CYDEV_UCFG_B1_P2_U0_SIZE, 0x00000070 +.set CYREG_B1_P2_U0_PLD_IT0, 0x40011400 +.set CYREG_B1_P2_U0_PLD_IT1, 0x40011404 +.set CYREG_B1_P2_U0_PLD_IT2, 0x40011408 +.set CYREG_B1_P2_U0_PLD_IT3, 0x4001140c +.set CYREG_B1_P2_U0_PLD_IT4, 0x40011410 +.set CYREG_B1_P2_U0_PLD_IT5, 0x40011414 +.set CYREG_B1_P2_U0_PLD_IT6, 0x40011418 +.set CYREG_B1_P2_U0_PLD_IT7, 0x4001141c +.set CYREG_B1_P2_U0_PLD_IT8, 0x40011420 +.set CYREG_B1_P2_U0_PLD_IT9, 0x40011424 +.set CYREG_B1_P2_U0_PLD_IT10, 0x40011428 +.set CYREG_B1_P2_U0_PLD_IT11, 0x4001142c +.set CYREG_B1_P2_U0_PLD_ORT0, 0x40011430 +.set CYREG_B1_P2_U0_PLD_ORT1, 0x40011432 +.set CYREG_B1_P2_U0_PLD_ORT2, 0x40011434 +.set CYREG_B1_P2_U0_PLD_ORT3, 0x40011436 +.set CYREG_B1_P2_U0_MC_CFG_CEN_CONST, 0x40011438 +.set CYREG_B1_P2_U0_MC_CFG_XORFB, 0x4001143a +.set CYREG_B1_P2_U0_MC_CFG_SET_RESET, 0x4001143c +.set CYREG_B1_P2_U0_MC_CFG_BYPASS, 0x4001143e +.set CYREG_B1_P2_U0_CFG0, 0x40011440 +.set CYREG_B1_P2_U0_CFG1, 0x40011441 +.set CYREG_B1_P2_U0_CFG2, 0x40011442 +.set CYREG_B1_P2_U0_CFG3, 0x40011443 +.set CYREG_B1_P2_U0_CFG4, 0x40011444 +.set CYREG_B1_P2_U0_CFG5, 0x40011445 +.set CYREG_B1_P2_U0_CFG6, 0x40011446 +.set CYREG_B1_P2_U0_CFG7, 0x40011447 +.set CYREG_B1_P2_U0_CFG8, 0x40011448 +.set CYREG_B1_P2_U0_CFG9, 0x40011449 +.set CYREG_B1_P2_U0_CFG10, 0x4001144a +.set CYREG_B1_P2_U0_CFG11, 0x4001144b +.set CYREG_B1_P2_U0_CFG12, 0x4001144c +.set CYREG_B1_P2_U0_CFG13, 0x4001144d +.set CYREG_B1_P2_U0_CFG14, 0x4001144e +.set CYREG_B1_P2_U0_CFG15, 0x4001144f +.set CYREG_B1_P2_U0_CFG16, 0x40011450 +.set CYREG_B1_P2_U0_CFG17, 0x40011451 +.set CYREG_B1_P2_U0_CFG18, 0x40011452 +.set CYREG_B1_P2_U0_CFG19, 0x40011453 +.set CYREG_B1_P2_U0_CFG20, 0x40011454 +.set CYREG_B1_P2_U0_CFG21, 0x40011455 +.set CYREG_B1_P2_U0_CFG22, 0x40011456 +.set CYREG_B1_P2_U0_CFG23, 0x40011457 +.set CYREG_B1_P2_U0_CFG24, 0x40011458 +.set CYREG_B1_P2_U0_CFG25, 0x40011459 +.set CYREG_B1_P2_U0_CFG26, 0x4001145a +.set CYREG_B1_P2_U0_CFG27, 0x4001145b +.set CYREG_B1_P2_U0_CFG28, 0x4001145c +.set CYREG_B1_P2_U0_CFG29, 0x4001145d +.set CYREG_B1_P2_U0_CFG30, 0x4001145e +.set CYREG_B1_P2_U0_CFG31, 0x4001145f +.set CYREG_B1_P2_U0_DCFG0, 0x40011460 +.set CYREG_B1_P2_U0_DCFG1, 0x40011462 +.set CYREG_B1_P2_U0_DCFG2, 0x40011464 +.set CYREG_B1_P2_U0_DCFG3, 0x40011466 +.set CYREG_B1_P2_U0_DCFG4, 0x40011468 +.set CYREG_B1_P2_U0_DCFG5, 0x4001146a +.set CYREG_B1_P2_U0_DCFG6, 0x4001146c +.set CYREG_B1_P2_U0_DCFG7, 0x4001146e +.set CYDEV_UCFG_B1_P2_U1_BASE, 0x40011480 +.set CYDEV_UCFG_B1_P2_U1_SIZE, 0x00000070 +.set CYREG_B1_P2_U1_PLD_IT0, 0x40011480 +.set CYREG_B1_P2_U1_PLD_IT1, 0x40011484 +.set CYREG_B1_P2_U1_PLD_IT2, 0x40011488 +.set CYREG_B1_P2_U1_PLD_IT3, 0x4001148c +.set CYREG_B1_P2_U1_PLD_IT4, 0x40011490 +.set CYREG_B1_P2_U1_PLD_IT5, 0x40011494 +.set CYREG_B1_P2_U1_PLD_IT6, 0x40011498 +.set CYREG_B1_P2_U1_PLD_IT7, 0x4001149c +.set CYREG_B1_P2_U1_PLD_IT8, 0x400114a0 +.set CYREG_B1_P2_U1_PLD_IT9, 0x400114a4 +.set CYREG_B1_P2_U1_PLD_IT10, 0x400114a8 +.set CYREG_B1_P2_U1_PLD_IT11, 0x400114ac +.set CYREG_B1_P2_U1_PLD_ORT0, 0x400114b0 +.set CYREG_B1_P2_U1_PLD_ORT1, 0x400114b2 +.set CYREG_B1_P2_U1_PLD_ORT2, 0x400114b4 +.set CYREG_B1_P2_U1_PLD_ORT3, 0x400114b6 +.set CYREG_B1_P2_U1_MC_CFG_CEN_CONST, 0x400114b8 +.set CYREG_B1_P2_U1_MC_CFG_XORFB, 0x400114ba +.set CYREG_B1_P2_U1_MC_CFG_SET_RESET, 0x400114bc +.set CYREG_B1_P2_U1_MC_CFG_BYPASS, 0x400114be +.set CYREG_B1_P2_U1_CFG0, 0x400114c0 +.set CYREG_B1_P2_U1_CFG1, 0x400114c1 +.set CYREG_B1_P2_U1_CFG2, 0x400114c2 +.set CYREG_B1_P2_U1_CFG3, 0x400114c3 +.set CYREG_B1_P2_U1_CFG4, 0x400114c4 +.set CYREG_B1_P2_U1_CFG5, 0x400114c5 +.set CYREG_B1_P2_U1_CFG6, 0x400114c6 +.set CYREG_B1_P2_U1_CFG7, 0x400114c7 +.set CYREG_B1_P2_U1_CFG8, 0x400114c8 +.set CYREG_B1_P2_U1_CFG9, 0x400114c9 +.set CYREG_B1_P2_U1_CFG10, 0x400114ca +.set CYREG_B1_P2_U1_CFG11, 0x400114cb +.set CYREG_B1_P2_U1_CFG12, 0x400114cc +.set CYREG_B1_P2_U1_CFG13, 0x400114cd +.set CYREG_B1_P2_U1_CFG14, 0x400114ce +.set CYREG_B1_P2_U1_CFG15, 0x400114cf +.set CYREG_B1_P2_U1_CFG16, 0x400114d0 +.set CYREG_B1_P2_U1_CFG17, 0x400114d1 +.set CYREG_B1_P2_U1_CFG18, 0x400114d2 +.set CYREG_B1_P2_U1_CFG19, 0x400114d3 +.set CYREG_B1_P2_U1_CFG20, 0x400114d4 +.set CYREG_B1_P2_U1_CFG21, 0x400114d5 +.set CYREG_B1_P2_U1_CFG22, 0x400114d6 +.set CYREG_B1_P2_U1_CFG23, 0x400114d7 +.set CYREG_B1_P2_U1_CFG24, 0x400114d8 +.set CYREG_B1_P2_U1_CFG25, 0x400114d9 +.set CYREG_B1_P2_U1_CFG26, 0x400114da +.set CYREG_B1_P2_U1_CFG27, 0x400114db +.set CYREG_B1_P2_U1_CFG28, 0x400114dc +.set CYREG_B1_P2_U1_CFG29, 0x400114dd +.set CYREG_B1_P2_U1_CFG30, 0x400114de +.set CYREG_B1_P2_U1_CFG31, 0x400114df +.set CYREG_B1_P2_U1_DCFG0, 0x400114e0 +.set CYREG_B1_P2_U1_DCFG1, 0x400114e2 +.set CYREG_B1_P2_U1_DCFG2, 0x400114e4 +.set CYREG_B1_P2_U1_DCFG3, 0x400114e6 +.set CYREG_B1_P2_U1_DCFG4, 0x400114e8 +.set CYREG_B1_P2_U1_DCFG5, 0x400114ea +.set CYREG_B1_P2_U1_DCFG6, 0x400114ec +.set CYREG_B1_P2_U1_DCFG7, 0x400114ee +.set CYDEV_UCFG_B1_P2_ROUTE_BASE, 0x40011500 +.set CYDEV_UCFG_B1_P2_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_P3_BASE, 0x40011600 +.set CYDEV_UCFG_B1_P3_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P3_U0_BASE, 0x40011600 +.set CYDEV_UCFG_B1_P3_U0_SIZE, 0x00000070 +.set CYREG_B1_P3_U0_PLD_IT0, 0x40011600 +.set CYREG_B1_P3_U0_PLD_IT1, 0x40011604 +.set CYREG_B1_P3_U0_PLD_IT2, 0x40011608 +.set CYREG_B1_P3_U0_PLD_IT3, 0x4001160c +.set CYREG_B1_P3_U0_PLD_IT4, 0x40011610 +.set CYREG_B1_P3_U0_PLD_IT5, 0x40011614 +.set CYREG_B1_P3_U0_PLD_IT6, 0x40011618 +.set CYREG_B1_P3_U0_PLD_IT7, 0x4001161c +.set CYREG_B1_P3_U0_PLD_IT8, 0x40011620 +.set CYREG_B1_P3_U0_PLD_IT9, 0x40011624 +.set CYREG_B1_P3_U0_PLD_IT10, 0x40011628 +.set CYREG_B1_P3_U0_PLD_IT11, 0x4001162c +.set CYREG_B1_P3_U0_PLD_ORT0, 0x40011630 +.set CYREG_B1_P3_U0_PLD_ORT1, 0x40011632 +.set CYREG_B1_P3_U0_PLD_ORT2, 0x40011634 +.set CYREG_B1_P3_U0_PLD_ORT3, 0x40011636 +.set CYREG_B1_P3_U0_MC_CFG_CEN_CONST, 0x40011638 +.set CYREG_B1_P3_U0_MC_CFG_XORFB, 0x4001163a +.set CYREG_B1_P3_U0_MC_CFG_SET_RESET, 0x4001163c +.set CYREG_B1_P3_U0_MC_CFG_BYPASS, 0x4001163e +.set CYREG_B1_P3_U0_CFG0, 0x40011640 +.set CYREG_B1_P3_U0_CFG1, 0x40011641 +.set CYREG_B1_P3_U0_CFG2, 0x40011642 +.set CYREG_B1_P3_U0_CFG3, 0x40011643 +.set CYREG_B1_P3_U0_CFG4, 0x40011644 +.set CYREG_B1_P3_U0_CFG5, 0x40011645 +.set CYREG_B1_P3_U0_CFG6, 0x40011646 +.set CYREG_B1_P3_U0_CFG7, 0x40011647 +.set CYREG_B1_P3_U0_CFG8, 0x40011648 +.set CYREG_B1_P3_U0_CFG9, 0x40011649 +.set CYREG_B1_P3_U0_CFG10, 0x4001164a +.set CYREG_B1_P3_U0_CFG11, 0x4001164b +.set CYREG_B1_P3_U0_CFG12, 0x4001164c +.set CYREG_B1_P3_U0_CFG13, 0x4001164d +.set CYREG_B1_P3_U0_CFG14, 0x4001164e +.set CYREG_B1_P3_U0_CFG15, 0x4001164f +.set CYREG_B1_P3_U0_CFG16, 0x40011650 +.set CYREG_B1_P3_U0_CFG17, 0x40011651 +.set CYREG_B1_P3_U0_CFG18, 0x40011652 +.set CYREG_B1_P3_U0_CFG19, 0x40011653 +.set CYREG_B1_P3_U0_CFG20, 0x40011654 +.set CYREG_B1_P3_U0_CFG21, 0x40011655 +.set CYREG_B1_P3_U0_CFG22, 0x40011656 +.set CYREG_B1_P3_U0_CFG23, 0x40011657 +.set CYREG_B1_P3_U0_CFG24, 0x40011658 +.set CYREG_B1_P3_U0_CFG25, 0x40011659 +.set CYREG_B1_P3_U0_CFG26, 0x4001165a +.set CYREG_B1_P3_U0_CFG27, 0x4001165b +.set CYREG_B1_P3_U0_CFG28, 0x4001165c +.set CYREG_B1_P3_U0_CFG29, 0x4001165d +.set CYREG_B1_P3_U0_CFG30, 0x4001165e +.set CYREG_B1_P3_U0_CFG31, 0x4001165f +.set CYREG_B1_P3_U0_DCFG0, 0x40011660 +.set CYREG_B1_P3_U0_DCFG1, 0x40011662 +.set CYREG_B1_P3_U0_DCFG2, 0x40011664 +.set CYREG_B1_P3_U0_DCFG3, 0x40011666 +.set CYREG_B1_P3_U0_DCFG4, 0x40011668 +.set CYREG_B1_P3_U0_DCFG5, 0x4001166a +.set CYREG_B1_P3_U0_DCFG6, 0x4001166c +.set CYREG_B1_P3_U0_DCFG7, 0x4001166e +.set CYDEV_UCFG_B1_P3_U1_BASE, 0x40011680 +.set CYDEV_UCFG_B1_P3_U1_SIZE, 0x00000070 +.set CYREG_B1_P3_U1_PLD_IT0, 0x40011680 +.set CYREG_B1_P3_U1_PLD_IT1, 0x40011684 +.set CYREG_B1_P3_U1_PLD_IT2, 0x40011688 +.set CYREG_B1_P3_U1_PLD_IT3, 0x4001168c +.set CYREG_B1_P3_U1_PLD_IT4, 0x40011690 +.set CYREG_B1_P3_U1_PLD_IT5, 0x40011694 +.set CYREG_B1_P3_U1_PLD_IT6, 0x40011698 +.set CYREG_B1_P3_U1_PLD_IT7, 0x4001169c +.set CYREG_B1_P3_U1_PLD_IT8, 0x400116a0 +.set CYREG_B1_P3_U1_PLD_IT9, 0x400116a4 +.set CYREG_B1_P3_U1_PLD_IT10, 0x400116a8 +.set CYREG_B1_P3_U1_PLD_IT11, 0x400116ac +.set CYREG_B1_P3_U1_PLD_ORT0, 0x400116b0 +.set CYREG_B1_P3_U1_PLD_ORT1, 0x400116b2 +.set CYREG_B1_P3_U1_PLD_ORT2, 0x400116b4 +.set CYREG_B1_P3_U1_PLD_ORT3, 0x400116b6 +.set CYREG_B1_P3_U1_MC_CFG_CEN_CONST, 0x400116b8 +.set CYREG_B1_P3_U1_MC_CFG_XORFB, 0x400116ba +.set CYREG_B1_P3_U1_MC_CFG_SET_RESET, 0x400116bc +.set CYREG_B1_P3_U1_MC_CFG_BYPASS, 0x400116be +.set CYREG_B1_P3_U1_CFG0, 0x400116c0 +.set CYREG_B1_P3_U1_CFG1, 0x400116c1 +.set CYREG_B1_P3_U1_CFG2, 0x400116c2 +.set CYREG_B1_P3_U1_CFG3, 0x400116c3 +.set CYREG_B1_P3_U1_CFG4, 0x400116c4 +.set CYREG_B1_P3_U1_CFG5, 0x400116c5 +.set CYREG_B1_P3_U1_CFG6, 0x400116c6 +.set CYREG_B1_P3_U1_CFG7, 0x400116c7 +.set CYREG_B1_P3_U1_CFG8, 0x400116c8 +.set CYREG_B1_P3_U1_CFG9, 0x400116c9 +.set CYREG_B1_P3_U1_CFG10, 0x400116ca +.set CYREG_B1_P3_U1_CFG11, 0x400116cb +.set CYREG_B1_P3_U1_CFG12, 0x400116cc +.set CYREG_B1_P3_U1_CFG13, 0x400116cd +.set CYREG_B1_P3_U1_CFG14, 0x400116ce +.set CYREG_B1_P3_U1_CFG15, 0x400116cf +.set CYREG_B1_P3_U1_CFG16, 0x400116d0 +.set CYREG_B1_P3_U1_CFG17, 0x400116d1 +.set CYREG_B1_P3_U1_CFG18, 0x400116d2 +.set CYREG_B1_P3_U1_CFG19, 0x400116d3 +.set CYREG_B1_P3_U1_CFG20, 0x400116d4 +.set CYREG_B1_P3_U1_CFG21, 0x400116d5 +.set CYREG_B1_P3_U1_CFG22, 0x400116d6 +.set CYREG_B1_P3_U1_CFG23, 0x400116d7 +.set CYREG_B1_P3_U1_CFG24, 0x400116d8 +.set CYREG_B1_P3_U1_CFG25, 0x400116d9 +.set CYREG_B1_P3_U1_CFG26, 0x400116da +.set CYREG_B1_P3_U1_CFG27, 0x400116db +.set CYREG_B1_P3_U1_CFG28, 0x400116dc +.set CYREG_B1_P3_U1_CFG29, 0x400116dd +.set CYREG_B1_P3_U1_CFG30, 0x400116de +.set CYREG_B1_P3_U1_CFG31, 0x400116df +.set CYREG_B1_P3_U1_DCFG0, 0x400116e0 +.set CYREG_B1_P3_U1_DCFG1, 0x400116e2 +.set CYREG_B1_P3_U1_DCFG2, 0x400116e4 +.set CYREG_B1_P3_U1_DCFG3, 0x400116e6 +.set CYREG_B1_P3_U1_DCFG4, 0x400116e8 +.set CYREG_B1_P3_U1_DCFG5, 0x400116ea +.set CYREG_B1_P3_U1_DCFG6, 0x400116ec +.set CYREG_B1_P3_U1_DCFG7, 0x400116ee +.set CYDEV_UCFG_B1_P3_ROUTE_BASE, 0x40011700 +.set CYDEV_UCFG_B1_P3_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_P4_BASE, 0x40011800 +.set CYDEV_UCFG_B1_P4_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P4_U0_BASE, 0x40011800 +.set CYDEV_UCFG_B1_P4_U0_SIZE, 0x00000070 +.set CYREG_B1_P4_U0_PLD_IT0, 0x40011800 +.set CYREG_B1_P4_U0_PLD_IT1, 0x40011804 +.set CYREG_B1_P4_U0_PLD_IT2, 0x40011808 +.set CYREG_B1_P4_U0_PLD_IT3, 0x4001180c +.set CYREG_B1_P4_U0_PLD_IT4, 0x40011810 +.set CYREG_B1_P4_U0_PLD_IT5, 0x40011814 +.set CYREG_B1_P4_U0_PLD_IT6, 0x40011818 +.set CYREG_B1_P4_U0_PLD_IT7, 0x4001181c +.set CYREG_B1_P4_U0_PLD_IT8, 0x40011820 +.set CYREG_B1_P4_U0_PLD_IT9, 0x40011824 +.set CYREG_B1_P4_U0_PLD_IT10, 0x40011828 +.set CYREG_B1_P4_U0_PLD_IT11, 0x4001182c +.set CYREG_B1_P4_U0_PLD_ORT0, 0x40011830 +.set CYREG_B1_P4_U0_PLD_ORT1, 0x40011832 +.set CYREG_B1_P4_U0_PLD_ORT2, 0x40011834 +.set CYREG_B1_P4_U0_PLD_ORT3, 0x40011836 +.set CYREG_B1_P4_U0_MC_CFG_CEN_CONST, 0x40011838 +.set CYREG_B1_P4_U0_MC_CFG_XORFB, 0x4001183a +.set CYREG_B1_P4_U0_MC_CFG_SET_RESET, 0x4001183c +.set CYREG_B1_P4_U0_MC_CFG_BYPASS, 0x4001183e +.set CYREG_B1_P4_U0_CFG0, 0x40011840 +.set CYREG_B1_P4_U0_CFG1, 0x40011841 +.set CYREG_B1_P4_U0_CFG2, 0x40011842 +.set CYREG_B1_P4_U0_CFG3, 0x40011843 +.set CYREG_B1_P4_U0_CFG4, 0x40011844 +.set CYREG_B1_P4_U0_CFG5, 0x40011845 +.set CYREG_B1_P4_U0_CFG6, 0x40011846 +.set CYREG_B1_P4_U0_CFG7, 0x40011847 +.set CYREG_B1_P4_U0_CFG8, 0x40011848 +.set CYREG_B1_P4_U0_CFG9, 0x40011849 +.set CYREG_B1_P4_U0_CFG10, 0x4001184a +.set CYREG_B1_P4_U0_CFG11, 0x4001184b +.set CYREG_B1_P4_U0_CFG12, 0x4001184c +.set CYREG_B1_P4_U0_CFG13, 0x4001184d +.set CYREG_B1_P4_U0_CFG14, 0x4001184e +.set CYREG_B1_P4_U0_CFG15, 0x4001184f +.set CYREG_B1_P4_U0_CFG16, 0x40011850 +.set CYREG_B1_P4_U0_CFG17, 0x40011851 +.set CYREG_B1_P4_U0_CFG18, 0x40011852 +.set CYREG_B1_P4_U0_CFG19, 0x40011853 +.set CYREG_B1_P4_U0_CFG20, 0x40011854 +.set CYREG_B1_P4_U0_CFG21, 0x40011855 +.set CYREG_B1_P4_U0_CFG22, 0x40011856 +.set CYREG_B1_P4_U0_CFG23, 0x40011857 +.set CYREG_B1_P4_U0_CFG24, 0x40011858 +.set CYREG_B1_P4_U0_CFG25, 0x40011859 +.set CYREG_B1_P4_U0_CFG26, 0x4001185a +.set CYREG_B1_P4_U0_CFG27, 0x4001185b +.set CYREG_B1_P4_U0_CFG28, 0x4001185c +.set CYREG_B1_P4_U0_CFG29, 0x4001185d +.set CYREG_B1_P4_U0_CFG30, 0x4001185e +.set CYREG_B1_P4_U0_CFG31, 0x4001185f +.set CYREG_B1_P4_U0_DCFG0, 0x40011860 +.set CYREG_B1_P4_U0_DCFG1, 0x40011862 +.set CYREG_B1_P4_U0_DCFG2, 0x40011864 +.set CYREG_B1_P4_U0_DCFG3, 0x40011866 +.set CYREG_B1_P4_U0_DCFG4, 0x40011868 +.set CYREG_B1_P4_U0_DCFG5, 0x4001186a +.set CYREG_B1_P4_U0_DCFG6, 0x4001186c +.set CYREG_B1_P4_U0_DCFG7, 0x4001186e +.set CYDEV_UCFG_B1_P4_U1_BASE, 0x40011880 +.set CYDEV_UCFG_B1_P4_U1_SIZE, 0x00000070 +.set CYREG_B1_P4_U1_PLD_IT0, 0x40011880 +.set CYREG_B1_P4_U1_PLD_IT1, 0x40011884 +.set CYREG_B1_P4_U1_PLD_IT2, 0x40011888 +.set CYREG_B1_P4_U1_PLD_IT3, 0x4001188c +.set CYREG_B1_P4_U1_PLD_IT4, 0x40011890 +.set CYREG_B1_P4_U1_PLD_IT5, 0x40011894 +.set CYREG_B1_P4_U1_PLD_IT6, 0x40011898 +.set CYREG_B1_P4_U1_PLD_IT7, 0x4001189c +.set CYREG_B1_P4_U1_PLD_IT8, 0x400118a0 +.set CYREG_B1_P4_U1_PLD_IT9, 0x400118a4 +.set CYREG_B1_P4_U1_PLD_IT10, 0x400118a8 +.set CYREG_B1_P4_U1_PLD_IT11, 0x400118ac +.set CYREG_B1_P4_U1_PLD_ORT0, 0x400118b0 +.set CYREG_B1_P4_U1_PLD_ORT1, 0x400118b2 +.set CYREG_B1_P4_U1_PLD_ORT2, 0x400118b4 +.set CYREG_B1_P4_U1_PLD_ORT3, 0x400118b6 +.set CYREG_B1_P4_U1_MC_CFG_CEN_CONST, 0x400118b8 +.set CYREG_B1_P4_U1_MC_CFG_XORFB, 0x400118ba +.set CYREG_B1_P4_U1_MC_CFG_SET_RESET, 0x400118bc +.set CYREG_B1_P4_U1_MC_CFG_BYPASS, 0x400118be +.set CYREG_B1_P4_U1_CFG0, 0x400118c0 +.set CYREG_B1_P4_U1_CFG1, 0x400118c1 +.set CYREG_B1_P4_U1_CFG2, 0x400118c2 +.set CYREG_B1_P4_U1_CFG3, 0x400118c3 +.set CYREG_B1_P4_U1_CFG4, 0x400118c4 +.set CYREG_B1_P4_U1_CFG5, 0x400118c5 +.set CYREG_B1_P4_U1_CFG6, 0x400118c6 +.set CYREG_B1_P4_U1_CFG7, 0x400118c7 +.set CYREG_B1_P4_U1_CFG8, 0x400118c8 +.set CYREG_B1_P4_U1_CFG9, 0x400118c9 +.set CYREG_B1_P4_U1_CFG10, 0x400118ca +.set CYREG_B1_P4_U1_CFG11, 0x400118cb +.set CYREG_B1_P4_U1_CFG12, 0x400118cc +.set CYREG_B1_P4_U1_CFG13, 0x400118cd +.set CYREG_B1_P4_U1_CFG14, 0x400118ce +.set CYREG_B1_P4_U1_CFG15, 0x400118cf +.set CYREG_B1_P4_U1_CFG16, 0x400118d0 +.set CYREG_B1_P4_U1_CFG17, 0x400118d1 +.set CYREG_B1_P4_U1_CFG18, 0x400118d2 +.set CYREG_B1_P4_U1_CFG19, 0x400118d3 +.set CYREG_B1_P4_U1_CFG20, 0x400118d4 +.set CYREG_B1_P4_U1_CFG21, 0x400118d5 +.set CYREG_B1_P4_U1_CFG22, 0x400118d6 +.set CYREG_B1_P4_U1_CFG23, 0x400118d7 +.set CYREG_B1_P4_U1_CFG24, 0x400118d8 +.set CYREG_B1_P4_U1_CFG25, 0x400118d9 +.set CYREG_B1_P4_U1_CFG26, 0x400118da +.set CYREG_B1_P4_U1_CFG27, 0x400118db +.set CYREG_B1_P4_U1_CFG28, 0x400118dc +.set CYREG_B1_P4_U1_CFG29, 0x400118dd +.set CYREG_B1_P4_U1_CFG30, 0x400118de +.set CYREG_B1_P4_U1_CFG31, 0x400118df +.set CYREG_B1_P4_U1_DCFG0, 0x400118e0 +.set CYREG_B1_P4_U1_DCFG1, 0x400118e2 +.set CYREG_B1_P4_U1_DCFG2, 0x400118e4 +.set CYREG_B1_P4_U1_DCFG3, 0x400118e6 +.set CYREG_B1_P4_U1_DCFG4, 0x400118e8 +.set CYREG_B1_P4_U1_DCFG5, 0x400118ea +.set CYREG_B1_P4_U1_DCFG6, 0x400118ec +.set CYREG_B1_P4_U1_DCFG7, 0x400118ee +.set CYDEV_UCFG_B1_P4_ROUTE_BASE, 0x40011900 +.set CYDEV_UCFG_B1_P4_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_P5_BASE, 0x40011a00 +.set CYDEV_UCFG_B1_P5_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P5_U0_BASE, 0x40011a00 +.set CYDEV_UCFG_B1_P5_U0_SIZE, 0x00000070 +.set CYREG_B1_P5_U0_PLD_IT0, 0x40011a00 +.set CYREG_B1_P5_U0_PLD_IT1, 0x40011a04 +.set CYREG_B1_P5_U0_PLD_IT2, 0x40011a08 +.set CYREG_B1_P5_U0_PLD_IT3, 0x40011a0c +.set CYREG_B1_P5_U0_PLD_IT4, 0x40011a10 +.set CYREG_B1_P5_U0_PLD_IT5, 0x40011a14 +.set CYREG_B1_P5_U0_PLD_IT6, 0x40011a18 +.set CYREG_B1_P5_U0_PLD_IT7, 0x40011a1c +.set CYREG_B1_P5_U0_PLD_IT8, 0x40011a20 +.set CYREG_B1_P5_U0_PLD_IT9, 0x40011a24 +.set CYREG_B1_P5_U0_PLD_IT10, 0x40011a28 +.set CYREG_B1_P5_U0_PLD_IT11, 0x40011a2c +.set CYREG_B1_P5_U0_PLD_ORT0, 0x40011a30 +.set CYREG_B1_P5_U0_PLD_ORT1, 0x40011a32 +.set CYREG_B1_P5_U0_PLD_ORT2, 0x40011a34 +.set CYREG_B1_P5_U0_PLD_ORT3, 0x40011a36 +.set CYREG_B1_P5_U0_MC_CFG_CEN_CONST, 0x40011a38 +.set CYREG_B1_P5_U0_MC_CFG_XORFB, 0x40011a3a +.set CYREG_B1_P5_U0_MC_CFG_SET_RESET, 0x40011a3c +.set CYREG_B1_P5_U0_MC_CFG_BYPASS, 0x40011a3e +.set CYREG_B1_P5_U0_CFG0, 0x40011a40 +.set CYREG_B1_P5_U0_CFG1, 0x40011a41 +.set CYREG_B1_P5_U0_CFG2, 0x40011a42 +.set CYREG_B1_P5_U0_CFG3, 0x40011a43 +.set CYREG_B1_P5_U0_CFG4, 0x40011a44 +.set CYREG_B1_P5_U0_CFG5, 0x40011a45 +.set CYREG_B1_P5_U0_CFG6, 0x40011a46 +.set CYREG_B1_P5_U0_CFG7, 0x40011a47 +.set CYREG_B1_P5_U0_CFG8, 0x40011a48 +.set CYREG_B1_P5_U0_CFG9, 0x40011a49 +.set CYREG_B1_P5_U0_CFG10, 0x40011a4a +.set CYREG_B1_P5_U0_CFG11, 0x40011a4b +.set CYREG_B1_P5_U0_CFG12, 0x40011a4c +.set CYREG_B1_P5_U0_CFG13, 0x40011a4d +.set CYREG_B1_P5_U0_CFG14, 0x40011a4e +.set CYREG_B1_P5_U0_CFG15, 0x40011a4f +.set CYREG_B1_P5_U0_CFG16, 0x40011a50 +.set CYREG_B1_P5_U0_CFG17, 0x40011a51 +.set CYREG_B1_P5_U0_CFG18, 0x40011a52 +.set CYREG_B1_P5_U0_CFG19, 0x40011a53 +.set CYREG_B1_P5_U0_CFG20, 0x40011a54 +.set CYREG_B1_P5_U0_CFG21, 0x40011a55 +.set CYREG_B1_P5_U0_CFG22, 0x40011a56 +.set CYREG_B1_P5_U0_CFG23, 0x40011a57 +.set CYREG_B1_P5_U0_CFG24, 0x40011a58 +.set CYREG_B1_P5_U0_CFG25, 0x40011a59 +.set CYREG_B1_P5_U0_CFG26, 0x40011a5a +.set CYREG_B1_P5_U0_CFG27, 0x40011a5b +.set CYREG_B1_P5_U0_CFG28, 0x40011a5c +.set CYREG_B1_P5_U0_CFG29, 0x40011a5d +.set CYREG_B1_P5_U0_CFG30, 0x40011a5e +.set CYREG_B1_P5_U0_CFG31, 0x40011a5f +.set CYREG_B1_P5_U0_DCFG0, 0x40011a60 +.set CYREG_B1_P5_U0_DCFG1, 0x40011a62 +.set CYREG_B1_P5_U0_DCFG2, 0x40011a64 +.set CYREG_B1_P5_U0_DCFG3, 0x40011a66 +.set CYREG_B1_P5_U0_DCFG4, 0x40011a68 +.set CYREG_B1_P5_U0_DCFG5, 0x40011a6a +.set CYREG_B1_P5_U0_DCFG6, 0x40011a6c +.set CYREG_B1_P5_U0_DCFG7, 0x40011a6e +.set CYDEV_UCFG_B1_P5_U1_BASE, 0x40011a80 +.set CYDEV_UCFG_B1_P5_U1_SIZE, 0x00000070 +.set CYREG_B1_P5_U1_PLD_IT0, 0x40011a80 +.set CYREG_B1_P5_U1_PLD_IT1, 0x40011a84 +.set CYREG_B1_P5_U1_PLD_IT2, 0x40011a88 +.set CYREG_B1_P5_U1_PLD_IT3, 0x40011a8c +.set CYREG_B1_P5_U1_PLD_IT4, 0x40011a90 +.set CYREG_B1_P5_U1_PLD_IT5, 0x40011a94 +.set CYREG_B1_P5_U1_PLD_IT6, 0x40011a98 +.set CYREG_B1_P5_U1_PLD_IT7, 0x40011a9c +.set CYREG_B1_P5_U1_PLD_IT8, 0x40011aa0 +.set CYREG_B1_P5_U1_PLD_IT9, 0x40011aa4 +.set CYREG_B1_P5_U1_PLD_IT10, 0x40011aa8 +.set CYREG_B1_P5_U1_PLD_IT11, 0x40011aac +.set CYREG_B1_P5_U1_PLD_ORT0, 0x40011ab0 +.set CYREG_B1_P5_U1_PLD_ORT1, 0x40011ab2 +.set CYREG_B1_P5_U1_PLD_ORT2, 0x40011ab4 +.set CYREG_B1_P5_U1_PLD_ORT3, 0x40011ab6 +.set CYREG_B1_P5_U1_MC_CFG_CEN_CONST, 0x40011ab8 +.set CYREG_B1_P5_U1_MC_CFG_XORFB, 0x40011aba +.set CYREG_B1_P5_U1_MC_CFG_SET_RESET, 0x40011abc +.set CYREG_B1_P5_U1_MC_CFG_BYPASS, 0x40011abe +.set CYREG_B1_P5_U1_CFG0, 0x40011ac0 +.set CYREG_B1_P5_U1_CFG1, 0x40011ac1 +.set CYREG_B1_P5_U1_CFG2, 0x40011ac2 +.set CYREG_B1_P5_U1_CFG3, 0x40011ac3 +.set CYREG_B1_P5_U1_CFG4, 0x40011ac4 +.set CYREG_B1_P5_U1_CFG5, 0x40011ac5 +.set CYREG_B1_P5_U1_CFG6, 0x40011ac6 +.set CYREG_B1_P5_U1_CFG7, 0x40011ac7 +.set CYREG_B1_P5_U1_CFG8, 0x40011ac8 +.set CYREG_B1_P5_U1_CFG9, 0x40011ac9 +.set CYREG_B1_P5_U1_CFG10, 0x40011aca +.set CYREG_B1_P5_U1_CFG11, 0x40011acb +.set CYREG_B1_P5_U1_CFG12, 0x40011acc +.set CYREG_B1_P5_U1_CFG13, 0x40011acd +.set CYREG_B1_P5_U1_CFG14, 0x40011ace +.set CYREG_B1_P5_U1_CFG15, 0x40011acf +.set CYREG_B1_P5_U1_CFG16, 0x40011ad0 +.set CYREG_B1_P5_U1_CFG17, 0x40011ad1 +.set CYREG_B1_P5_U1_CFG18, 0x40011ad2 +.set CYREG_B1_P5_U1_CFG19, 0x40011ad3 +.set CYREG_B1_P5_U1_CFG20, 0x40011ad4 +.set CYREG_B1_P5_U1_CFG21, 0x40011ad5 +.set CYREG_B1_P5_U1_CFG22, 0x40011ad6 +.set CYREG_B1_P5_U1_CFG23, 0x40011ad7 +.set CYREG_B1_P5_U1_CFG24, 0x40011ad8 +.set CYREG_B1_P5_U1_CFG25, 0x40011ad9 +.set CYREG_B1_P5_U1_CFG26, 0x40011ada +.set CYREG_B1_P5_U1_CFG27, 0x40011adb +.set CYREG_B1_P5_U1_CFG28, 0x40011adc +.set CYREG_B1_P5_U1_CFG29, 0x40011add +.set CYREG_B1_P5_U1_CFG30, 0x40011ade +.set CYREG_B1_P5_U1_CFG31, 0x40011adf +.set CYREG_B1_P5_U1_DCFG0, 0x40011ae0 +.set CYREG_B1_P5_U1_DCFG1, 0x40011ae2 +.set CYREG_B1_P5_U1_DCFG2, 0x40011ae4 +.set CYREG_B1_P5_U1_DCFG3, 0x40011ae6 +.set CYREG_B1_P5_U1_DCFG4, 0x40011ae8 +.set CYREG_B1_P5_U1_DCFG5, 0x40011aea +.set CYREG_B1_P5_U1_DCFG6, 0x40011aec +.set CYREG_B1_P5_U1_DCFG7, 0x40011aee +.set CYDEV_UCFG_B1_P5_ROUTE_BASE, 0x40011b00 +.set CYDEV_UCFG_B1_P5_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI0_BASE, 0x40014000 +.set CYDEV_UCFG_DSI0_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI1_BASE, 0x40014100 +.set CYDEV_UCFG_DSI1_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI2_BASE, 0x40014200 +.set CYDEV_UCFG_DSI2_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI3_BASE, 0x40014300 +.set CYDEV_UCFG_DSI3_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI4_BASE, 0x40014400 +.set CYDEV_UCFG_DSI4_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI5_BASE, 0x40014500 +.set CYDEV_UCFG_DSI5_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI6_BASE, 0x40014600 +.set CYDEV_UCFG_DSI6_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI7_BASE, 0x40014700 +.set CYDEV_UCFG_DSI7_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI8_BASE, 0x40014800 +.set CYDEV_UCFG_DSI8_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI9_BASE, 0x40014900 +.set CYDEV_UCFG_DSI9_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI12_BASE, 0x40014c00 +.set CYDEV_UCFG_DSI12_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI13_BASE, 0x40014d00 +.set CYDEV_UCFG_DSI13_SIZE, 0x000000ef +.set CYDEV_UCFG_BCTL0_BASE, 0x40015000 +.set CYDEV_UCFG_BCTL0_SIZE, 0x00000010 +.set CYREG_BCTL0_MDCLK_EN, 0x40015000 +.set CYREG_BCTL0_MBCLK_EN, 0x40015001 +.set CYREG_BCTL0_WAIT_CFG, 0x40015002 +.set CYREG_BCTL0_BANK_CTL, 0x40015003 +.set CYREG_BCTL0_UDB_TEST_3, 0x40015007 +.set CYREG_BCTL0_DCLK_EN0, 0x40015008 +.set CYREG_BCTL0_BCLK_EN0, 0x40015009 +.set CYREG_BCTL0_DCLK_EN1, 0x4001500a +.set CYREG_BCTL0_BCLK_EN1, 0x4001500b +.set CYREG_BCTL0_DCLK_EN2, 0x4001500c +.set CYREG_BCTL0_BCLK_EN2, 0x4001500d +.set CYREG_BCTL0_DCLK_EN3, 0x4001500e +.set CYREG_BCTL0_BCLK_EN3, 0x4001500f +.set CYDEV_UCFG_BCTL1_BASE, 0x40015010 +.set CYDEV_UCFG_BCTL1_SIZE, 0x00000010 +.set CYREG_BCTL1_MDCLK_EN, 0x40015010 +.set CYREG_BCTL1_MBCLK_EN, 0x40015011 +.set CYREG_BCTL1_WAIT_CFG, 0x40015012 +.set CYREG_BCTL1_BANK_CTL, 0x40015013 +.set CYREG_BCTL1_UDB_TEST_3, 0x40015017 +.set CYREG_BCTL1_DCLK_EN0, 0x40015018 +.set CYREG_BCTL1_BCLK_EN0, 0x40015019 +.set CYREG_BCTL1_DCLK_EN1, 0x4001501a +.set CYREG_BCTL1_BCLK_EN1, 0x4001501b +.set CYREG_BCTL1_DCLK_EN2, 0x4001501c +.set CYREG_BCTL1_BCLK_EN2, 0x4001501d +.set CYREG_BCTL1_DCLK_EN3, 0x4001501e +.set CYREG_BCTL1_BCLK_EN3, 0x4001501f +.set CYDEV_IDMUX_BASE, 0x40015100 +.set CYDEV_IDMUX_SIZE, 0x00000016 +.set CYREG_IDMUX_IRQ_CTL0, 0x40015100 +.set CYREG_IDMUX_IRQ_CTL1, 0x40015101 +.set CYREG_IDMUX_IRQ_CTL2, 0x40015102 +.set CYREG_IDMUX_IRQ_CTL3, 0x40015103 +.set CYREG_IDMUX_IRQ_CTL4, 0x40015104 +.set CYREG_IDMUX_IRQ_CTL5, 0x40015105 +.set CYREG_IDMUX_IRQ_CTL6, 0x40015106 +.set CYREG_IDMUX_IRQ_CTL7, 0x40015107 +.set CYREG_IDMUX_DRQ_CTL0, 0x40015110 +.set CYREG_IDMUX_DRQ_CTL1, 0x40015111 +.set CYREG_IDMUX_DRQ_CTL2, 0x40015112 +.set CYREG_IDMUX_DRQ_CTL3, 0x40015113 +.set CYREG_IDMUX_DRQ_CTL4, 0x40015114 +.set CYREG_IDMUX_DRQ_CTL5, 0x40015115 +.set CYDEV_CACHERAM_BASE, 0x40030000 +.set CYDEV_CACHERAM_SIZE, 0x00000400 +.set CYREG_CACHERAM_DATA_MBASE, 0x40030000 +.set CYREG_CACHERAM_DATA_MSIZE, 0x00000400 +.set CYDEV_SFR_BASE, 0x40050100 +.set CYDEV_SFR_SIZE, 0x000000fb +.set CYREG_SFR_GPIO0, 0x40050180 +.set CYREG_SFR_GPIRD0, 0x40050189 +.set CYREG_SFR_GPIO0_SEL, 0x4005018a +.set CYREG_SFR_GPIO1, 0x40050190 +.set CYREG_SFR_GPIRD1, 0x40050191 +.set CYREG_SFR_GPIO2, 0x40050198 +.set CYREG_SFR_GPIRD2, 0x40050199 +.set CYREG_SFR_GPIO2_SEL, 0x4005019a +.set CYREG_SFR_GPIO1_SEL, 0x400501a2 +.set CYREG_SFR_GPIO3, 0x400501b0 +.set CYREG_SFR_GPIRD3, 0x400501b1 +.set CYREG_SFR_GPIO3_SEL, 0x400501b2 +.set CYREG_SFR_GPIO4, 0x400501c0 +.set CYREG_SFR_GPIRD4, 0x400501c1 +.set CYREG_SFR_GPIO4_SEL, 0x400501c2 +.set CYREG_SFR_GPIO5, 0x400501c8 +.set CYREG_SFR_GPIRD5, 0x400501c9 +.set CYREG_SFR_GPIO5_SEL, 0x400501ca +.set CYREG_SFR_GPIO6, 0x400501d8 +.set CYREG_SFR_GPIRD6, 0x400501d9 +.set CYREG_SFR_GPIO6_SEL, 0x400501da +.set CYREG_SFR_GPIO12, 0x400501e8 +.set CYREG_SFR_GPIRD12, 0x400501e9 +.set CYREG_SFR_GPIO12_SEL, 0x400501f2 +.set CYREG_SFR_GPIO15, 0x400501f8 +.set CYREG_SFR_GPIRD15, 0x400501f9 +.set CYREG_SFR_GPIO15_SEL, 0x400501fa +.set CYDEV_P3BA_BASE, 0x40050300 +.set CYDEV_P3BA_SIZE, 0x0000002b +.set CYREG_P3BA_Y_START, 0x40050300 +.set CYREG_P3BA_YROLL, 0x40050301 +.set CYREG_P3BA_YCFG, 0x40050302 +.set CYREG_P3BA_X_START1, 0x40050303 +.set CYREG_P3BA_X_START2, 0x40050304 +.set CYREG_P3BA_XROLL1, 0x40050305 +.set CYREG_P3BA_XROLL2, 0x40050306 +.set CYREG_P3BA_XINC, 0x40050307 +.set CYREG_P3BA_XCFG, 0x40050308 +.set CYREG_P3BA_OFFSETADDR1, 0x40050309 +.set CYREG_P3BA_OFFSETADDR2, 0x4005030a +.set CYREG_P3BA_OFFSETADDR3, 0x4005030b +.set CYREG_P3BA_ABSADDR1, 0x4005030c +.set CYREG_P3BA_ABSADDR2, 0x4005030d +.set CYREG_P3BA_ABSADDR3, 0x4005030e +.set CYREG_P3BA_ABSADDR4, 0x4005030f +.set CYREG_P3BA_DATCFG1, 0x40050310 +.set CYREG_P3BA_DATCFG2, 0x40050311 +.set CYREG_P3BA_CMP_RSLT1, 0x40050314 +.set CYREG_P3BA_CMP_RSLT2, 0x40050315 +.set CYREG_P3BA_CMP_RSLT3, 0x40050316 +.set CYREG_P3BA_CMP_RSLT4, 0x40050317 +.set CYREG_P3BA_DATA_REG1, 0x40050318 +.set CYREG_P3BA_DATA_REG2, 0x40050319 +.set CYREG_P3BA_DATA_REG3, 0x4005031a +.set CYREG_P3BA_DATA_REG4, 0x4005031b +.set CYREG_P3BA_EXP_DATA1, 0x4005031c +.set CYREG_P3BA_EXP_DATA2, 0x4005031d +.set CYREG_P3BA_EXP_DATA3, 0x4005031e +.set CYREG_P3BA_EXP_DATA4, 0x4005031f +.set CYREG_P3BA_MSTR_HRDATA1, 0x40050320 +.set CYREG_P3BA_MSTR_HRDATA2, 0x40050321 +.set CYREG_P3BA_MSTR_HRDATA3, 0x40050322 +.set CYREG_P3BA_MSTR_HRDATA4, 0x40050323 +.set CYREG_P3BA_BIST_EN, 0x40050324 +.set CYREG_P3BA_PHUB_MASTER_SSR, 0x40050325 +.set CYREG_P3BA_SEQCFG1, 0x40050326 +.set CYREG_P3BA_SEQCFG2, 0x40050327 +.set CYREG_P3BA_Y_CURR, 0x40050328 +.set CYREG_P3BA_X_CURR1, 0x40050329 +.set CYREG_P3BA_X_CURR2, 0x4005032a +.set CYDEV_PANTHER_BASE, 0x40080000 +.set CYDEV_PANTHER_SIZE, 0x00000020 +.set CYREG_PANTHER_STCALIB_CFG, 0x40080000 +.set CYREG_PANTHER_WAITPIPE, 0x40080004 +.set CYREG_PANTHER_TRACE_CFG, 0x40080008 +.set CYREG_PANTHER_DBG_CFG, 0x4008000c +.set CYREG_PANTHER_CM3_LCKRST_STAT, 0x40080018 +.set CYREG_PANTHER_DEVICE_ID, 0x4008001c +.set CYDEV_FLSECC_BASE, 0x48000000 +.set CYDEV_FLSECC_SIZE, 0x00008000 +.set CYREG_FLSECC_DATA_MBASE, 0x48000000 +.set CYREG_FLSECC_DATA_MSIZE, 0x00008000 +.set CYDEV_FLSHID_BASE, 0x49000000 +.set CYDEV_FLSHID_SIZE, 0x00000200 +.set CYREG_FLSHID_RSVD_MBASE, 0x49000000 +.set CYREG_FLSHID_RSVD_MSIZE, 0x00000080 +.set CYREG_FLSHID_CUST_MDATA_MBASE, 0x49000080 +.set CYREG_FLSHID_CUST_MDATA_MSIZE, 0x00000080 +.set CYDEV_FLSHID_CUST_TABLES_BASE, 0x49000100 +.set CYDEV_FLSHID_CUST_TABLES_SIZE, 0x00000040 +.set CYREG_FLSHID_CUST_TABLES_Y_LOC, 0x49000100 +.set CYREG_FLSHID_CUST_TABLES_X_LOC, 0x49000101 +.set CYREG_FLSHID_CUST_TABLES_WAFER_NUM, 0x49000102 +.set CYREG_FLSHID_CUST_TABLES_LOT_LSB, 0x49000103 +.set CYREG_FLSHID_CUST_TABLES_LOT_MSB, 0x49000104 +.set CYREG_FLSHID_CUST_TABLES_WRK_WK, 0x49000105 +.set CYREG_FLSHID_CUST_TABLES_FAB_YR, 0x49000106 +.set CYREG_FLSHID_CUST_TABLES_MINOR, 0x49000107 +.set CYREG_FLSHID_CUST_TABLES_IMO_3MHZ, 0x49000108 +.set CYREG_FLSHID_CUST_TABLES_IMO_6MHZ, 0x49000109 +.set CYREG_FLSHID_CUST_TABLES_IMO_12MHZ, 0x4900010a +.set CYREG_FLSHID_CUST_TABLES_IMO_24MHZ, 0x4900010b +.set CYREG_FLSHID_CUST_TABLES_IMO_67MHZ, 0x4900010c +.set CYREG_FLSHID_CUST_TABLES_IMO_80MHZ, 0x4900010d +.set CYREG_FLSHID_CUST_TABLES_IMO_92MHZ, 0x4900010e +.set CYREG_FLSHID_CUST_TABLES_IMO_USB, 0x4900010f +.set CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS, 0x49000110 +.set CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS, 0x49000111 +.set CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS, 0x49000112 +.set CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS, 0x49000113 +.set CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS, 0x49000114 +.set CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS, 0x49000115 +.set CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS, 0x49000116 +.set CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS, 0x49000117 +.set CYREG_FLSHID_CUST_TABLES_DEC_M1, 0x49000118 +.set CYREG_FLSHID_CUST_TABLES_DEC_M2, 0x49000119 +.set CYREG_FLSHID_CUST_TABLES_DEC_M3, 0x4900011a +.set CYREG_FLSHID_CUST_TABLES_DEC_M4, 0x4900011b +.set CYREG_FLSHID_CUST_TABLES_DEC_M5, 0x4900011c +.set CYREG_FLSHID_CUST_TABLES_DEC_M6, 0x4900011d +.set CYREG_FLSHID_CUST_TABLES_DEC_M7, 0x4900011e +.set CYREG_FLSHID_CUST_TABLES_DEC_M8, 0x4900011f +.set CYREG_FLSHID_CUST_TABLES_DAC0_M1, 0x49000120 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M2, 0x49000121 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M3, 0x49000122 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M4, 0x49000123 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M5, 0x49000124 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M6, 0x49000125 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M7, 0x49000126 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M8, 0x49000127 +.set CYREG_FLSHID_CUST_TABLES_DAC2_M1, 0x49000128 +.set CYREG_FLSHID_CUST_TABLES_DAC2_M2, 0x49000129 +.set CYREG_FLSHID_CUST_TABLES_DAC2_M3, 0x4900012a +.set CYREG_FLSHID_CUST_TABLES_DAC2_M4, 0x4900012b +.set CYREG_FLSHID_CUST_TABLES_DAC2_M5, 0x4900012c +.set CYREG_FLSHID_CUST_TABLES_DAC2_M6, 0x4900012d +.set CYREG_FLSHID_CUST_TABLES_DAC2_M7, 0x4900012e +.set CYREG_FLSHID_CUST_TABLES_DAC2_M8, 0x4900012f +.set CYREG_FLSHID_CUST_TABLES_DAC1_M1, 0x49000130 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M2, 0x49000131 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M3, 0x49000132 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M4, 0x49000133 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M5, 0x49000134 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M6, 0x49000135 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M7, 0x49000136 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M8, 0x49000137 +.set CYREG_FLSHID_CUST_TABLES_DAC3_M1, 0x49000138 +.set CYREG_FLSHID_CUST_TABLES_DAC3_M2, 0x49000139 +.set CYREG_FLSHID_CUST_TABLES_DAC3_M3, 0x4900013a +.set CYREG_FLSHID_CUST_TABLES_DAC3_M4, 0x4900013b +.set CYREG_FLSHID_CUST_TABLES_DAC3_M5, 0x4900013c +.set CYREG_FLSHID_CUST_TABLES_DAC3_M6, 0x4900013d +.set CYREG_FLSHID_CUST_TABLES_DAC3_M7, 0x4900013e +.set CYREG_FLSHID_CUST_TABLES_DAC3_M8, 0x4900013f +.set CYDEV_FLSHID_MFG_CFG_BASE, 0x49000180 +.set CYDEV_FLSHID_MFG_CFG_SIZE, 0x00000080 +.set CYREG_FLSHID_MFG_CFG_IMO_TR1, 0x49000188 +.set CYREG_FLSHID_MFG_CFG_CMP0_TR0, 0x490001ac +.set CYREG_FLSHID_MFG_CFG_CMP1_TR0, 0x490001ae +.set CYREG_FLSHID_MFG_CFG_CMP2_TR0, 0x490001b0 +.set CYREG_FLSHID_MFG_CFG_CMP3_TR0, 0x490001b2 +.set CYREG_FLSHID_MFG_CFG_CMP0_TR1, 0x490001b4 +.set CYREG_FLSHID_MFG_CFG_CMP1_TR1, 0x490001b6 +.set CYREG_FLSHID_MFG_CFG_CMP2_TR1, 0x490001b8 +.set CYREG_FLSHID_MFG_CFG_CMP3_TR1, 0x490001ba +.set CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM, 0x490001ce +.set CYDEV_EXTMEM_BASE, 0x60000000 +.set CYDEV_EXTMEM_SIZE, 0x00800000 +.set CYREG_EXTMEM_DATA_MBASE, 0x60000000 +.set CYREG_EXTMEM_DATA_MSIZE, 0x00800000 +.set CYDEV_ITM_BASE, 0xe0000000 +.set CYDEV_ITM_SIZE, 0x00001000 +.set CYREG_ITM_TRACE_EN, 0xe0000e00 +.set CYREG_ITM_TRACE_PRIVILEGE, 0xe0000e40 +.set CYREG_ITM_TRACE_CTRL, 0xe0000e80 +.set CYREG_ITM_LOCK_ACCESS, 0xe0000fb0 +.set CYREG_ITM_LOCK_STATUS, 0xe0000fb4 +.set CYREG_ITM_PID4, 0xe0000fd0 +.set CYREG_ITM_PID5, 0xe0000fd4 +.set CYREG_ITM_PID6, 0xe0000fd8 +.set CYREG_ITM_PID7, 0xe0000fdc +.set CYREG_ITM_PID0, 0xe0000fe0 +.set CYREG_ITM_PID1, 0xe0000fe4 +.set CYREG_ITM_PID2, 0xe0000fe8 +.set CYREG_ITM_PID3, 0xe0000fec +.set CYREG_ITM_CID0, 0xe0000ff0 +.set CYREG_ITM_CID1, 0xe0000ff4 +.set CYREG_ITM_CID2, 0xe0000ff8 +.set CYREG_ITM_CID3, 0xe0000ffc +.set CYDEV_DWT_BASE, 0xe0001000 +.set CYDEV_DWT_SIZE, 0x0000005c +.set CYREG_DWT_CTRL, 0xe0001000 +.set CYREG_DWT_CYCLE_COUNT, 0xe0001004 +.set CYREG_DWT_CPI_COUNT, 0xe0001008 +.set CYREG_DWT_EXC_OVHD_COUNT, 0xe000100c +.set CYREG_DWT_SLEEP_COUNT, 0xe0001010 +.set CYREG_DWT_LSU_COUNT, 0xe0001014 +.set CYREG_DWT_FOLD_COUNT, 0xe0001018 +.set CYREG_DWT_PC_SAMPLE, 0xe000101c +.set CYREG_DWT_COMP_0, 0xe0001020 +.set CYREG_DWT_MASK_0, 0xe0001024 +.set CYREG_DWT_FUNCTION_0, 0xe0001028 +.set CYREG_DWT_COMP_1, 0xe0001030 +.set CYREG_DWT_MASK_1, 0xe0001034 +.set CYREG_DWT_FUNCTION_1, 0xe0001038 +.set CYREG_DWT_COMP_2, 0xe0001040 +.set CYREG_DWT_MASK_2, 0xe0001044 +.set CYREG_DWT_FUNCTION_2, 0xe0001048 +.set CYREG_DWT_COMP_3, 0xe0001050 +.set CYREG_DWT_MASK_3, 0xe0001054 +.set CYREG_DWT_FUNCTION_3, 0xe0001058 +.set CYDEV_FPB_BASE, 0xe0002000 +.set CYDEV_FPB_SIZE, 0x00001000 +.set CYREG_FPB_CTRL, 0xe0002000 +.set CYREG_FPB_REMAP, 0xe0002004 +.set CYREG_FPB_FP_COMP_0, 0xe0002008 +.set CYREG_FPB_FP_COMP_1, 0xe000200c +.set CYREG_FPB_FP_COMP_2, 0xe0002010 +.set CYREG_FPB_FP_COMP_3, 0xe0002014 +.set CYREG_FPB_FP_COMP_4, 0xe0002018 +.set CYREG_FPB_FP_COMP_5, 0xe000201c +.set CYREG_FPB_FP_COMP_6, 0xe0002020 +.set CYREG_FPB_FP_COMP_7, 0xe0002024 +.set CYREG_FPB_PID4, 0xe0002fd0 +.set CYREG_FPB_PID5, 0xe0002fd4 +.set CYREG_FPB_PID6, 0xe0002fd8 +.set CYREG_FPB_PID7, 0xe0002fdc +.set CYREG_FPB_PID0, 0xe0002fe0 +.set CYREG_FPB_PID1, 0xe0002fe4 +.set CYREG_FPB_PID2, 0xe0002fe8 +.set CYREG_FPB_PID3, 0xe0002fec +.set CYREG_FPB_CID0, 0xe0002ff0 +.set CYREG_FPB_CID1, 0xe0002ff4 +.set CYREG_FPB_CID2, 0xe0002ff8 +.set CYREG_FPB_CID3, 0xe0002ffc +.set CYDEV_NVIC_BASE, 0xe000e000 +.set CYDEV_NVIC_SIZE, 0x00000d3c +.set CYREG_NVIC_INT_CTL_TYPE, 0xe000e004 +.set CYREG_NVIC_SYSTICK_CTL, 0xe000e010 +.set CYREG_NVIC_SYSTICK_RELOAD, 0xe000e014 +.set CYREG_NVIC_SYSTICK_CURRENT, 0xe000e018 +.set CYREG_NVIC_SYSTICK_CAL, 0xe000e01c +.set CYREG_NVIC_SETENA0, 0xe000e100 +.set CYREG_NVIC_CLRENA0, 0xe000e180 +.set CYREG_NVIC_SETPEND0, 0xe000e200 +.set CYREG_NVIC_CLRPEND0, 0xe000e280 +.set CYREG_NVIC_ACTIVE0, 0xe000e300 +.set CYREG_NVIC_PRI_0, 0xe000e400 +.set CYREG_NVIC_PRI_1, 0xe000e401 +.set CYREG_NVIC_PRI_2, 0xe000e402 +.set CYREG_NVIC_PRI_3, 0xe000e403 +.set CYREG_NVIC_PRI_4, 0xe000e404 +.set CYREG_NVIC_PRI_5, 0xe000e405 +.set CYREG_NVIC_PRI_6, 0xe000e406 +.set CYREG_NVIC_PRI_7, 0xe000e407 +.set CYREG_NVIC_PRI_8, 0xe000e408 +.set CYREG_NVIC_PRI_9, 0xe000e409 +.set CYREG_NVIC_PRI_10, 0xe000e40a +.set CYREG_NVIC_PRI_11, 0xe000e40b +.set CYREG_NVIC_PRI_12, 0xe000e40c +.set CYREG_NVIC_PRI_13, 0xe000e40d +.set CYREG_NVIC_PRI_14, 0xe000e40e +.set CYREG_NVIC_PRI_15, 0xe000e40f +.set CYREG_NVIC_PRI_16, 0xe000e410 +.set CYREG_NVIC_PRI_17, 0xe000e411 +.set CYREG_NVIC_PRI_18, 0xe000e412 +.set CYREG_NVIC_PRI_19, 0xe000e413 +.set CYREG_NVIC_PRI_20, 0xe000e414 +.set CYREG_NVIC_PRI_21, 0xe000e415 +.set CYREG_NVIC_PRI_22, 0xe000e416 +.set CYREG_NVIC_PRI_23, 0xe000e417 +.set CYREG_NVIC_PRI_24, 0xe000e418 +.set CYREG_NVIC_PRI_25, 0xe000e419 +.set CYREG_NVIC_PRI_26, 0xe000e41a +.set CYREG_NVIC_PRI_27, 0xe000e41b +.set CYREG_NVIC_PRI_28, 0xe000e41c +.set CYREG_NVIC_PRI_29, 0xe000e41d +.set CYREG_NVIC_PRI_30, 0xe000e41e +.set CYREG_NVIC_PRI_31, 0xe000e41f +.set CYREG_NVIC_CPUID_BASE, 0xe000ed00 +.set CYREG_NVIC_INTR_CTRL_STATE, 0xe000ed04 +.set CYREG_NVIC_VECT_OFFSET, 0xe000ed08 +.set CYREG_NVIC_APPLN_INTR, 0xe000ed0c +.set CYREG_NVIC_SYSTEM_CONTROL, 0xe000ed10 +.set CYREG_NVIC_CFG_CONTROL, 0xe000ed14 +.set CYREG_NVIC_SYS_PRIO_HANDLER_4_7, 0xe000ed18 +.set CYREG_NVIC_SYS_PRIO_HANDLER_8_11, 0xe000ed1c +.set CYREG_NVIC_SYS_PRIO_HANDLER_12_15, 0xe000ed20 +.set CYREG_NVIC_SYS_HANDLER_CSR, 0xe000ed24 +.set CYREG_NVIC_MEMMAN_FAULT_STATUS, 0xe000ed28 +.set CYREG_NVIC_BUS_FAULT_STATUS, 0xe000ed29 +.set CYREG_NVIC_USAGE_FAULT_STATUS, 0xe000ed2a +.set CYREG_NVIC_HARD_FAULT_STATUS, 0xe000ed2c +.set CYREG_NVIC_DEBUG_FAULT_STATUS, 0xe000ed30 +.set CYREG_NVIC_MEMMAN_FAULT_ADD, 0xe000ed34 +.set CYREG_NVIC_BUS_FAULT_ADD, 0xe000ed38 +.set CYDEV_CORE_DBG_BASE, 0xe000edf0 +.set CYDEV_CORE_DBG_SIZE, 0x00000010 +.set CYREG_CORE_DBG_DBG_HLT_CS, 0xe000edf0 +.set CYREG_CORE_DBG_DBG_REG_SEL, 0xe000edf4 +.set CYREG_CORE_DBG_DBG_REG_DATA, 0xe000edf8 +.set CYREG_CORE_DBG_EXC_MON_CTL, 0xe000edfc +.set CYDEV_TPIU_BASE, 0xe0040000 +.set CYDEV_TPIU_SIZE, 0x00001000 +.set CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ, 0xe0040000 +.set CYREG_TPIU_CURRENT_SYNC_PRT_SZ, 0xe0040004 +.set CYREG_TPIU_ASYNC_CLK_PRESCALER, 0xe0040010 +.set CYREG_TPIU_PROTOCOL, 0xe00400f0 +.set CYREG_TPIU_FORM_FLUSH_STAT, 0xe0040300 +.set CYREG_TPIU_FORM_FLUSH_CTRL, 0xe0040304 +.set CYREG_TPIU_TRIGGER, 0xe0040ee8 +.set CYREG_TPIU_ITETMDATA, 0xe0040eec +.set CYREG_TPIU_ITATBCTR2, 0xe0040ef0 +.set CYREG_TPIU_ITATBCTR0, 0xe0040ef8 +.set CYREG_TPIU_ITITMDATA, 0xe0040efc +.set CYREG_TPIU_ITCTRL, 0xe0040f00 +.set CYREG_TPIU_DEVID, 0xe0040fc8 +.set CYREG_TPIU_DEVTYPE, 0xe0040fcc +.set CYREG_TPIU_PID4, 0xe0040fd0 +.set CYREG_TPIU_PID5, 0xe0040fd4 +.set CYREG_TPIU_PID6, 0xe0040fd8 +.set CYREG_TPIU_PID7, 0xe0040fdc +.set CYREG_TPIU_PID0, 0xe0040fe0 +.set CYREG_TPIU_PID1, 0xe0040fe4 +.set CYREG_TPIU_PID2, 0xe0040fe8 +.set CYREG_TPIU_PID3, 0xe0040fec +.set CYREG_TPIU_CID0, 0xe0040ff0 +.set CYREG_TPIU_CID1, 0xe0040ff4 +.set CYREG_TPIU_CID2, 0xe0040ff8 +.set CYREG_TPIU_CID3, 0xe0040ffc +.set CYDEV_ETM_BASE, 0xe0041000 +.set CYDEV_ETM_SIZE, 0x00001000 +.set CYREG_ETM_CTL, 0xe0041000 +.set CYREG_ETM_CFG_CODE, 0xe0041004 +.set CYREG_ETM_TRIG_EVENT, 0xe0041008 +.set CYREG_ETM_STATUS, 0xe0041010 +.set CYREG_ETM_SYS_CFG, 0xe0041014 +.set CYREG_ETM_TRACE_ENB_EVENT, 0xe0041020 +.set CYREG_ETM_TRACE_EN_CTRL1, 0xe0041024 +.set CYREG_ETM_FIFOFULL_LEVEL, 0xe004102c +.set CYREG_ETM_SYNC_FREQ, 0xe00411e0 +.set CYREG_ETM_ETM_ID, 0xe00411e4 +.set CYREG_ETM_CFG_CODE_EXT, 0xe00411e8 +.set CYREG_ETM_TR_SS_EMBICE_CTRL, 0xe00411f0 +.set CYREG_ETM_CS_TRACE_ID, 0xe0041200 +.set CYREG_ETM_OS_LOCK_ACCESS, 0xe0041300 +.set CYREG_ETM_OS_LOCK_STATUS, 0xe0041304 +.set CYREG_ETM_PDSR, 0xe0041314 +.set CYREG_ETM_ITMISCIN, 0xe0041ee0 +.set CYREG_ETM_ITTRIGOUT, 0xe0041ee8 +.set CYREG_ETM_ITATBCTR2, 0xe0041ef0 +.set CYREG_ETM_ITATBCTR0, 0xe0041ef8 +.set CYREG_ETM_INT_MODE_CTRL, 0xe0041f00 +.set CYREG_ETM_CLM_TAG_SET, 0xe0041fa0 +.set CYREG_ETM_CLM_TAG_CLR, 0xe0041fa4 +.set CYREG_ETM_LOCK_ACCESS, 0xe0041fb0 +.set CYREG_ETM_LOCK_STATUS, 0xe0041fb4 +.set CYREG_ETM_AUTH_STATUS, 0xe0041fb8 +.set CYREG_ETM_DEV_TYPE, 0xe0041fcc +.set CYREG_ETM_PID4, 0xe0041fd0 +.set CYREG_ETM_PID5, 0xe0041fd4 +.set CYREG_ETM_PID6, 0xe0041fd8 +.set CYREG_ETM_PID7, 0xe0041fdc +.set CYREG_ETM_PID0, 0xe0041fe0 +.set CYREG_ETM_PID1, 0xe0041fe4 +.set CYREG_ETM_PID2, 0xe0041fe8 +.set CYREG_ETM_PID3, 0xe0041fec +.set CYREG_ETM_CID0, 0xe0041ff0 +.set CYREG_ETM_CID1, 0xe0041ff4 +.set CYREG_ETM_CID2, 0xe0041ff8 +.set CYREG_ETM_CID3, 0xe0041ffc +.set CYDEV_ROM_TABLE_BASE, 0xe00ff000 +.set CYDEV_ROM_TABLE_SIZE, 0x00001000 +.set CYREG_ROM_TABLE_NVIC, 0xe00ff000 +.set CYREG_ROM_TABLE_DWT, 0xe00ff004 +.set CYREG_ROM_TABLE_FPB, 0xe00ff008 +.set CYREG_ROM_TABLE_ITM, 0xe00ff00c +.set CYREG_ROM_TABLE_TPIU, 0xe00ff010 +.set CYREG_ROM_TABLE_ETM, 0xe00ff014 +.set CYREG_ROM_TABLE_END, 0xe00ff018 +.set CYREG_ROM_TABLE_MEMTYPE, 0xe00fffcc +.set CYREG_ROM_TABLE_PID4, 0xe00fffd0 +.set CYREG_ROM_TABLE_PID5, 0xe00fffd4 +.set CYREG_ROM_TABLE_PID6, 0xe00fffd8 +.set CYREG_ROM_TABLE_PID7, 0xe00fffdc +.set CYREG_ROM_TABLE_PID0, 0xe00fffe0 +.set CYREG_ROM_TABLE_PID1, 0xe00fffe4 +.set CYREG_ROM_TABLE_PID2, 0xe00fffe8 +.set CYREG_ROM_TABLE_PID3, 0xe00fffec +.set CYREG_ROM_TABLE_CID0, 0xe00ffff0 +.set CYREG_ROM_TABLE_CID1, 0xe00ffff4 +.set CYREG_ROM_TABLE_CID2, 0xe00ffff8 +.set CYREG_ROM_TABLE_CID3, 0xe00ffffc +.set CYDEV_FLS_SIZE, CYDEV_FLASH_SIZE +.set CYDEV_ECC_BASE, CYDEV_FLSECC_BASE +.set CYDEV_FLS_SECTOR_SIZE, 0x00010000 +.set CYDEV_FLS_ROW_SIZE, 0x00000100 +.set CYDEV_ECC_SECTOR_SIZE, 0x00002000 +.set CYDEV_ECC_ROW_SIZE, 0x00000020 +.set CYDEV_EEPROM_SECTOR_SIZE, 0x00000400 +.set CYDEV_EEPROM_ROW_SIZE, 0x00000010 +.set CYDEV_PERIPH_BASE, CYDEV_CLKDIST_BASE +.set CYCLK_LD_DISABLE, 0x00000004 +.set CYCLK_LD_SYNC_EN, 0x00000002 +.set CYCLK_LD_LOAD, 0x00000001 +.set CYCLK_PIPE, 0x00000080 +.set CYCLK_SSS, 0x00000040 +.set CYCLK_EARLY, 0x00000020 +.set CYCLK_DUTY, 0x00000010 +.set CYCLK_SYNC, 0x00000008 +.set CYCLK_SRC_SEL_CLK_SYNC_D, 0 +.set CYCLK_SRC_SEL_SYNC_DIG, 0 +.set CYCLK_SRC_SEL_IMO, 1 +.set CYCLK_SRC_SEL_XTAL_MHZ, 2 +.set CYCLK_SRC_SEL_XTALM, 2 +.set CYCLK_SRC_SEL_ILO, 3 +.set CYCLK_SRC_SEL_PLL, 4 +.set CYCLK_SRC_SEL_XTAL_KHZ, 5 +.set CYCLK_SRC_SEL_XTALK, 5 +.set CYCLK_SRC_SEL_DSI_G, 6 +.set CYCLK_SRC_SEL_DSI_D, 7 +.set CYCLK_SRC_SEL_CLK_SYNC_A, 0 +.set CYCLK_SRC_SEL_DSI_A, 7 diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar.inc b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar.inc new file mode 100755 index 00000000..8f6fcc72 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar.inc @@ -0,0 +1,5356 @@ +; +; FILENAME: cydeviceiar.inc +; OBSOLETE: Do not use this file. Use the _trm version instead. +; PSoC Creator 3.0 Component Pack 7 +; +; DESCRIPTION: +; This file provides all of the address values for the entire PSoC device. +; +;------------------------------------------------------------------------------- +; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + +#define CYDEV_FLASH_BASE 0x00000000 +#define CYDEV_FLASH_SIZE 0x00020000 +#define CYDEV_FLASH_DATA_MBASE 0x00000000 +#define CYDEV_FLASH_DATA_MSIZE 0x00020000 +#define CYDEV_SRAM_BASE 0x1fffc000 +#define CYDEV_SRAM_SIZE 0x00008000 +#define CYDEV_SRAM_CODE64K_MBASE 0x1fff8000 +#define CYDEV_SRAM_CODE64K_MSIZE 0x00004000 +#define CYDEV_SRAM_CODE32K_MBASE 0x1fffc000 +#define CYDEV_SRAM_CODE32K_MSIZE 0x00002000 +#define CYDEV_SRAM_CODE16K_MBASE 0x1fffe000 +#define CYDEV_SRAM_CODE16K_MSIZE 0x00001000 +#define CYDEV_SRAM_CODE_MBASE 0x1fffc000 +#define CYDEV_SRAM_CODE_MSIZE 0x00004000 +#define CYDEV_SRAM_DATA_MBASE 0x20000000 +#define CYDEV_SRAM_DATA_MSIZE 0x00004000 +#define CYDEV_SRAM_DATA16K_MBASE 0x20001000 +#define CYDEV_SRAM_DATA16K_MSIZE 0x00001000 +#define CYDEV_SRAM_DATA32K_MBASE 0x20002000 +#define CYDEV_SRAM_DATA32K_MSIZE 0x00002000 +#define CYDEV_SRAM_DATA64K_MBASE 0x20004000 +#define CYDEV_SRAM_DATA64K_MSIZE 0x00004000 +#define CYDEV_DMA_BASE 0x20008000 +#define CYDEV_DMA_SIZE 0x00008000 +#define CYDEV_DMA_SRAM64K_MBASE 0x20008000 +#define CYDEV_DMA_SRAM64K_MSIZE 0x00004000 +#define CYDEV_DMA_SRAM32K_MBASE 0x2000c000 +#define CYDEV_DMA_SRAM32K_MSIZE 0x00002000 +#define CYDEV_DMA_SRAM16K_MBASE 0x2000e000 +#define CYDEV_DMA_SRAM16K_MSIZE 0x00001000 +#define CYDEV_DMA_SRAM_MBASE 0x2000f000 +#define CYDEV_DMA_SRAM_MSIZE 0x00001000 +#define CYDEV_CLKDIST_BASE 0x40004000 +#define CYDEV_CLKDIST_SIZE 0x00000110 +#define CYDEV_CLKDIST_CR 0x40004000 +#define CYDEV_CLKDIST_LD 0x40004001 +#define CYDEV_CLKDIST_WRK0 0x40004002 +#define CYDEV_CLKDIST_WRK1 0x40004003 +#define CYDEV_CLKDIST_MSTR0 0x40004004 +#define CYDEV_CLKDIST_MSTR1 0x40004005 +#define CYDEV_CLKDIST_BCFG0 0x40004006 +#define CYDEV_CLKDIST_BCFG1 0x40004007 +#define CYDEV_CLKDIST_BCFG2 0x40004008 +#define CYDEV_CLKDIST_UCFG 0x40004009 +#define CYDEV_CLKDIST_DLY0 0x4000400a +#define CYDEV_CLKDIST_DLY1 0x4000400b +#define CYDEV_CLKDIST_DMASK 0x40004010 +#define CYDEV_CLKDIST_AMASK 0x40004014 +#define CYDEV_CLKDIST_DCFG0_BASE 0x40004080 +#define CYDEV_CLKDIST_DCFG0_SIZE 0x00000003 +#define CYDEV_CLKDIST_DCFG0_CFG0 0x40004080 +#define CYDEV_CLKDIST_DCFG0_CFG1 0x40004081 +#define CYDEV_CLKDIST_DCFG0_CFG2 0x40004082 +#define CYDEV_CLKDIST_DCFG1_BASE 0x40004084 +#define CYDEV_CLKDIST_DCFG1_SIZE 0x00000003 +#define CYDEV_CLKDIST_DCFG1_CFG0 0x40004084 +#define CYDEV_CLKDIST_DCFG1_CFG1 0x40004085 +#define CYDEV_CLKDIST_DCFG1_CFG2 0x40004086 +#define CYDEV_CLKDIST_DCFG2_BASE 0x40004088 +#define CYDEV_CLKDIST_DCFG2_SIZE 0x00000003 +#define CYDEV_CLKDIST_DCFG2_CFG0 0x40004088 +#define CYDEV_CLKDIST_DCFG2_CFG1 0x40004089 +#define CYDEV_CLKDIST_DCFG2_CFG2 0x4000408a +#define CYDEV_CLKDIST_DCFG3_BASE 0x4000408c +#define CYDEV_CLKDIST_DCFG3_SIZE 0x00000003 +#define CYDEV_CLKDIST_DCFG3_CFG0 0x4000408c +#define CYDEV_CLKDIST_DCFG3_CFG1 0x4000408d +#define CYDEV_CLKDIST_DCFG3_CFG2 0x4000408e +#define CYDEV_CLKDIST_DCFG4_BASE 0x40004090 +#define CYDEV_CLKDIST_DCFG4_SIZE 0x00000003 +#define CYDEV_CLKDIST_DCFG4_CFG0 0x40004090 +#define CYDEV_CLKDIST_DCFG4_CFG1 0x40004091 +#define CYDEV_CLKDIST_DCFG4_CFG2 0x40004092 +#define CYDEV_CLKDIST_DCFG5_BASE 0x40004094 +#define CYDEV_CLKDIST_DCFG5_SIZE 0x00000003 +#define CYDEV_CLKDIST_DCFG5_CFG0 0x40004094 +#define CYDEV_CLKDIST_DCFG5_CFG1 0x40004095 +#define CYDEV_CLKDIST_DCFG5_CFG2 0x40004096 +#define CYDEV_CLKDIST_DCFG6_BASE 0x40004098 +#define CYDEV_CLKDIST_DCFG6_SIZE 0x00000003 +#define CYDEV_CLKDIST_DCFG6_CFG0 0x40004098 +#define CYDEV_CLKDIST_DCFG6_CFG1 0x40004099 +#define CYDEV_CLKDIST_DCFG6_CFG2 0x4000409a +#define CYDEV_CLKDIST_DCFG7_BASE 0x4000409c +#define CYDEV_CLKDIST_DCFG7_SIZE 0x00000003 +#define CYDEV_CLKDIST_DCFG7_CFG0 0x4000409c +#define CYDEV_CLKDIST_DCFG7_CFG1 0x4000409d +#define CYDEV_CLKDIST_DCFG7_CFG2 0x4000409e +#define CYDEV_CLKDIST_ACFG0_BASE 0x40004100 +#define CYDEV_CLKDIST_ACFG0_SIZE 0x00000004 +#define CYDEV_CLKDIST_ACFG0_CFG0 0x40004100 +#define CYDEV_CLKDIST_ACFG0_CFG1 0x40004101 +#define CYDEV_CLKDIST_ACFG0_CFG2 0x40004102 +#define CYDEV_CLKDIST_ACFG0_CFG3 0x40004103 +#define CYDEV_CLKDIST_ACFG1_BASE 0x40004104 +#define CYDEV_CLKDIST_ACFG1_SIZE 0x00000004 +#define CYDEV_CLKDIST_ACFG1_CFG0 0x40004104 +#define CYDEV_CLKDIST_ACFG1_CFG1 0x40004105 +#define CYDEV_CLKDIST_ACFG1_CFG2 0x40004106 +#define CYDEV_CLKDIST_ACFG1_CFG3 0x40004107 +#define CYDEV_CLKDIST_ACFG2_BASE 0x40004108 +#define CYDEV_CLKDIST_ACFG2_SIZE 0x00000004 +#define CYDEV_CLKDIST_ACFG2_CFG0 0x40004108 +#define CYDEV_CLKDIST_ACFG2_CFG1 0x40004109 +#define CYDEV_CLKDIST_ACFG2_CFG2 0x4000410a +#define CYDEV_CLKDIST_ACFG2_CFG3 0x4000410b +#define CYDEV_CLKDIST_ACFG3_BASE 0x4000410c +#define CYDEV_CLKDIST_ACFG3_SIZE 0x00000004 +#define CYDEV_CLKDIST_ACFG3_CFG0 0x4000410c +#define CYDEV_CLKDIST_ACFG3_CFG1 0x4000410d +#define CYDEV_CLKDIST_ACFG3_CFG2 0x4000410e +#define CYDEV_CLKDIST_ACFG3_CFG3 0x4000410f +#define CYDEV_FASTCLK_BASE 0x40004200 +#define CYDEV_FASTCLK_SIZE 0x00000026 +#define CYDEV_FASTCLK_IMO_BASE 0x40004200 +#define CYDEV_FASTCLK_IMO_SIZE 0x00000001 +#define CYDEV_FASTCLK_IMO_CR 0x40004200 +#define CYDEV_FASTCLK_XMHZ_BASE 0x40004210 +#define CYDEV_FASTCLK_XMHZ_SIZE 0x00000004 +#define CYDEV_FASTCLK_XMHZ_CSR 0x40004210 +#define CYDEV_FASTCLK_XMHZ_CFG0 0x40004212 +#define CYDEV_FASTCLK_XMHZ_CFG1 0x40004213 +#define CYDEV_FASTCLK_PLL_BASE 0x40004220 +#define CYDEV_FASTCLK_PLL_SIZE 0x00000006 +#define CYDEV_FASTCLK_PLL_CFG0 0x40004220 +#define CYDEV_FASTCLK_PLL_CFG1 0x40004221 +#define CYDEV_FASTCLK_PLL_P 0x40004222 +#define CYDEV_FASTCLK_PLL_Q 0x40004223 +#define CYDEV_FASTCLK_PLL_SR 0x40004225 +#define CYDEV_SLOWCLK_BASE 0x40004300 +#define CYDEV_SLOWCLK_SIZE 0x0000000b +#define CYDEV_SLOWCLK_ILO_BASE 0x40004300 +#define CYDEV_SLOWCLK_ILO_SIZE 0x00000002 +#define CYDEV_SLOWCLK_ILO_CR0 0x40004300 +#define CYDEV_SLOWCLK_ILO_CR1 0x40004301 +#define CYDEV_SLOWCLK_X32_BASE 0x40004308 +#define CYDEV_SLOWCLK_X32_SIZE 0x00000003 +#define CYDEV_SLOWCLK_X32_CR 0x40004308 +#define CYDEV_SLOWCLK_X32_CFG 0x40004309 +#define CYDEV_SLOWCLK_X32_TST 0x4000430a +#define CYDEV_BOOST_BASE 0x40004320 +#define CYDEV_BOOST_SIZE 0x00000007 +#define CYDEV_BOOST_CR0 0x40004320 +#define CYDEV_BOOST_CR1 0x40004321 +#define CYDEV_BOOST_CR2 0x40004322 +#define CYDEV_BOOST_CR3 0x40004323 +#define CYDEV_BOOST_SR 0x40004324 +#define CYDEV_BOOST_CR4 0x40004325 +#define CYDEV_BOOST_SR2 0x40004326 +#define CYDEV_PWRSYS_BASE 0x40004330 +#define CYDEV_PWRSYS_SIZE 0x00000002 +#define CYDEV_PWRSYS_CR0 0x40004330 +#define CYDEV_PWRSYS_CR1 0x40004331 +#define CYDEV_PM_BASE 0x40004380 +#define CYDEV_PM_SIZE 0x00000057 +#define CYDEV_PM_TW_CFG0 0x40004380 +#define CYDEV_PM_TW_CFG1 0x40004381 +#define CYDEV_PM_TW_CFG2 0x40004382 +#define CYDEV_PM_WDT_CFG 0x40004383 +#define CYDEV_PM_WDT_CR 0x40004384 +#define CYDEV_PM_INT_SR 0x40004390 +#define CYDEV_PM_MODE_CFG0 0x40004391 +#define CYDEV_PM_MODE_CFG1 0x40004392 +#define CYDEV_PM_MODE_CSR 0x40004393 +#define CYDEV_PM_USB_CR0 0x40004394 +#define CYDEV_PM_WAKEUP_CFG0 0x40004398 +#define CYDEV_PM_WAKEUP_CFG1 0x40004399 +#define CYDEV_PM_WAKEUP_CFG2 0x4000439a +#define CYDEV_PM_ACT_BASE 0x400043a0 +#define CYDEV_PM_ACT_SIZE 0x0000000e +#define CYDEV_PM_ACT_CFG0 0x400043a0 +#define CYDEV_PM_ACT_CFG1 0x400043a1 +#define CYDEV_PM_ACT_CFG2 0x400043a2 +#define CYDEV_PM_ACT_CFG3 0x400043a3 +#define CYDEV_PM_ACT_CFG4 0x400043a4 +#define CYDEV_PM_ACT_CFG5 0x400043a5 +#define CYDEV_PM_ACT_CFG6 0x400043a6 +#define CYDEV_PM_ACT_CFG7 0x400043a7 +#define CYDEV_PM_ACT_CFG8 0x400043a8 +#define CYDEV_PM_ACT_CFG9 0x400043a9 +#define CYDEV_PM_ACT_CFG10 0x400043aa +#define CYDEV_PM_ACT_CFG11 0x400043ab +#define CYDEV_PM_ACT_CFG12 0x400043ac +#define CYDEV_PM_ACT_CFG13 0x400043ad +#define CYDEV_PM_STBY_BASE 0x400043b0 +#define CYDEV_PM_STBY_SIZE 0x0000000e +#define CYDEV_PM_STBY_CFG0 0x400043b0 +#define CYDEV_PM_STBY_CFG1 0x400043b1 +#define CYDEV_PM_STBY_CFG2 0x400043b2 +#define CYDEV_PM_STBY_CFG3 0x400043b3 +#define CYDEV_PM_STBY_CFG4 0x400043b4 +#define CYDEV_PM_STBY_CFG5 0x400043b5 +#define CYDEV_PM_STBY_CFG6 0x400043b6 +#define CYDEV_PM_STBY_CFG7 0x400043b7 +#define CYDEV_PM_STBY_CFG8 0x400043b8 +#define CYDEV_PM_STBY_CFG9 0x400043b9 +#define CYDEV_PM_STBY_CFG10 0x400043ba +#define CYDEV_PM_STBY_CFG11 0x400043bb +#define CYDEV_PM_STBY_CFG12 0x400043bc +#define CYDEV_PM_STBY_CFG13 0x400043bd +#define CYDEV_PM_AVAIL_BASE 0x400043c0 +#define CYDEV_PM_AVAIL_SIZE 0x00000017 +#define CYDEV_PM_AVAIL_CR0 0x400043c0 +#define CYDEV_PM_AVAIL_CR1 0x400043c1 +#define CYDEV_PM_AVAIL_CR2 0x400043c2 +#define CYDEV_PM_AVAIL_CR3 0x400043c3 +#define CYDEV_PM_AVAIL_CR4 0x400043c4 +#define CYDEV_PM_AVAIL_CR5 0x400043c5 +#define CYDEV_PM_AVAIL_CR6 0x400043c6 +#define CYDEV_PM_AVAIL_SR0 0x400043d0 +#define CYDEV_PM_AVAIL_SR1 0x400043d1 +#define CYDEV_PM_AVAIL_SR2 0x400043d2 +#define CYDEV_PM_AVAIL_SR3 0x400043d3 +#define CYDEV_PM_AVAIL_SR4 0x400043d4 +#define CYDEV_PM_AVAIL_SR5 0x400043d5 +#define CYDEV_PM_AVAIL_SR6 0x400043d6 +#define CYDEV_PICU_BASE 0x40004500 +#define CYDEV_PICU_SIZE 0x000000b0 +#define CYDEV_PICU_INTTYPE_BASE 0x40004500 +#define CYDEV_PICU_INTTYPE_SIZE 0x00000080 +#define CYDEV_PICU_INTTYPE_PICU0_BASE 0x40004500 +#define CYDEV_PICU_INTTYPE_PICU0_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE0 0x40004500 +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE1 0x40004501 +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE2 0x40004502 +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE3 0x40004503 +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE4 0x40004504 +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE5 0x40004505 +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE6 0x40004506 +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE7 0x40004507 +#define CYDEV_PICU_INTTYPE_PICU1_BASE 0x40004508 +#define CYDEV_PICU_INTTYPE_PICU1_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE0 0x40004508 +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE1 0x40004509 +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE2 0x4000450a +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE3 0x4000450b +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE4 0x4000450c +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE5 0x4000450d +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE6 0x4000450e +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE7 0x4000450f +#define CYDEV_PICU_INTTYPE_PICU2_BASE 0x40004510 +#define CYDEV_PICU_INTTYPE_PICU2_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE0 0x40004510 +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE1 0x40004511 +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE2 0x40004512 +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE3 0x40004513 +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE4 0x40004514 +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE5 0x40004515 +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE6 0x40004516 +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE7 0x40004517 +#define CYDEV_PICU_INTTYPE_PICU3_BASE 0x40004518 +#define CYDEV_PICU_INTTYPE_PICU3_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE0 0x40004518 +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE1 0x40004519 +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE2 0x4000451a +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE3 0x4000451b +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE4 0x4000451c +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE5 0x4000451d +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE6 0x4000451e +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE7 0x4000451f +#define CYDEV_PICU_INTTYPE_PICU4_BASE 0x40004520 +#define CYDEV_PICU_INTTYPE_PICU4_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE0 0x40004520 +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE1 0x40004521 +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE2 0x40004522 +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE3 0x40004523 +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE4 0x40004524 +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE5 0x40004525 +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE6 0x40004526 +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE7 0x40004527 +#define CYDEV_PICU_INTTYPE_PICU5_BASE 0x40004528 +#define CYDEV_PICU_INTTYPE_PICU5_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE0 0x40004528 +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE1 0x40004529 +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE2 0x4000452a +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE3 0x4000452b +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE4 0x4000452c +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE5 0x4000452d +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE6 0x4000452e +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE7 0x4000452f +#define CYDEV_PICU_INTTYPE_PICU6_BASE 0x40004530 +#define CYDEV_PICU_INTTYPE_PICU6_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE0 0x40004530 +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE1 0x40004531 +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE2 0x40004532 +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE3 0x40004533 +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE4 0x40004534 +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE5 0x40004535 +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE6 0x40004536 +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE7 0x40004537 +#define CYDEV_PICU_INTTYPE_PICU12_BASE 0x40004560 +#define CYDEV_PICU_INTTYPE_PICU12_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE0 0x40004560 +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE1 0x40004561 +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE2 0x40004562 +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE3 0x40004563 +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE4 0x40004564 +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE5 0x40004565 +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE6 0x40004566 +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE7 0x40004567 +#define CYDEV_PICU_INTTYPE_PICU15_BASE 0x40004578 +#define CYDEV_PICU_INTTYPE_PICU15_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE0 0x40004578 +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE1 0x40004579 +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE2 0x4000457a +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE3 0x4000457b +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE4 0x4000457c +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE5 0x4000457d +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE6 0x4000457e +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE7 0x4000457f +#define CYDEV_PICU_STAT_BASE 0x40004580 +#define CYDEV_PICU_STAT_SIZE 0x00000010 +#define CYDEV_PICU_STAT_PICU0_BASE 0x40004580 +#define CYDEV_PICU_STAT_PICU0_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU0_INTSTAT 0x40004580 +#define CYDEV_PICU_STAT_PICU1_BASE 0x40004581 +#define CYDEV_PICU_STAT_PICU1_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU1_INTSTAT 0x40004581 +#define CYDEV_PICU_STAT_PICU2_BASE 0x40004582 +#define CYDEV_PICU_STAT_PICU2_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU2_INTSTAT 0x40004582 +#define CYDEV_PICU_STAT_PICU3_BASE 0x40004583 +#define CYDEV_PICU_STAT_PICU3_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU3_INTSTAT 0x40004583 +#define CYDEV_PICU_STAT_PICU4_BASE 0x40004584 +#define CYDEV_PICU_STAT_PICU4_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU4_INTSTAT 0x40004584 +#define CYDEV_PICU_STAT_PICU5_BASE 0x40004585 +#define CYDEV_PICU_STAT_PICU5_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU5_INTSTAT 0x40004585 +#define CYDEV_PICU_STAT_PICU6_BASE 0x40004586 +#define CYDEV_PICU_STAT_PICU6_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU6_INTSTAT 0x40004586 +#define CYDEV_PICU_STAT_PICU12_BASE 0x4000458c +#define CYDEV_PICU_STAT_PICU12_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU12_INTSTAT 0x4000458c +#define CYDEV_PICU_STAT_PICU15_BASE 0x4000458f +#define CYDEV_PICU_STAT_PICU15_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU15_INTSTAT 0x4000458f +#define CYDEV_PICU_SNAP_BASE 0x40004590 +#define CYDEV_PICU_SNAP_SIZE 0x00000010 +#define CYDEV_PICU_SNAP_PICU0_BASE 0x40004590 +#define CYDEV_PICU_SNAP_PICU0_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU0_SNAP 0x40004590 +#define CYDEV_PICU_SNAP_PICU1_BASE 0x40004591 +#define CYDEV_PICU_SNAP_PICU1_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU1_SNAP 0x40004591 +#define CYDEV_PICU_SNAP_PICU2_BASE 0x40004592 +#define CYDEV_PICU_SNAP_PICU2_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU2_SNAP 0x40004592 +#define CYDEV_PICU_SNAP_PICU3_BASE 0x40004593 +#define CYDEV_PICU_SNAP_PICU3_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU3_SNAP 0x40004593 +#define CYDEV_PICU_SNAP_PICU4_BASE 0x40004594 +#define CYDEV_PICU_SNAP_PICU4_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU4_SNAP 0x40004594 +#define CYDEV_PICU_SNAP_PICU5_BASE 0x40004595 +#define CYDEV_PICU_SNAP_PICU5_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU5_SNAP 0x40004595 +#define CYDEV_PICU_SNAP_PICU6_BASE 0x40004596 +#define CYDEV_PICU_SNAP_PICU6_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU6_SNAP 0x40004596 +#define CYDEV_PICU_SNAP_PICU12_BASE 0x4000459c +#define CYDEV_PICU_SNAP_PICU12_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU12_SNAP 0x4000459c +#define CYDEV_PICU_SNAP_PICU_15_BASE 0x4000459f +#define CYDEV_PICU_SNAP_PICU_15_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU_15_SNAP_15 0x4000459f +#define CYDEV_PICU_DISABLE_COR_BASE 0x400045a0 +#define CYDEV_PICU_DISABLE_COR_SIZE 0x00000010 +#define CYDEV_PICU_DISABLE_COR_PICU0_BASE 0x400045a0 +#define CYDEV_PICU_DISABLE_COR_PICU0_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR 0x400045a0 +#define CYDEV_PICU_DISABLE_COR_PICU1_BASE 0x400045a1 +#define CYDEV_PICU_DISABLE_COR_PICU1_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR 0x400045a1 +#define CYDEV_PICU_DISABLE_COR_PICU2_BASE 0x400045a2 +#define CYDEV_PICU_DISABLE_COR_PICU2_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR 0x400045a2 +#define CYDEV_PICU_DISABLE_COR_PICU3_BASE 0x400045a3 +#define CYDEV_PICU_DISABLE_COR_PICU3_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR 0x400045a3 +#define CYDEV_PICU_DISABLE_COR_PICU4_BASE 0x400045a4 +#define CYDEV_PICU_DISABLE_COR_PICU4_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR 0x400045a4 +#define CYDEV_PICU_DISABLE_COR_PICU5_BASE 0x400045a5 +#define CYDEV_PICU_DISABLE_COR_PICU5_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR 0x400045a5 +#define CYDEV_PICU_DISABLE_COR_PICU6_BASE 0x400045a6 +#define CYDEV_PICU_DISABLE_COR_PICU6_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR 0x400045a6 +#define CYDEV_PICU_DISABLE_COR_PICU12_BASE 0x400045ac +#define CYDEV_PICU_DISABLE_COR_PICU12_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR 0x400045ac +#define CYDEV_PICU_DISABLE_COR_PICU15_BASE 0x400045af +#define CYDEV_PICU_DISABLE_COR_PICU15_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR 0x400045af +#define CYDEV_MFGCFG_BASE 0x40004600 +#define CYDEV_MFGCFG_SIZE 0x000000ed +#define CYDEV_MFGCFG_ANAIF_BASE 0x40004600 +#define CYDEV_MFGCFG_ANAIF_SIZE 0x00000038 +#define CYDEV_MFGCFG_ANAIF_DAC0_BASE 0x40004608 +#define CYDEV_MFGCFG_ANAIF_DAC0_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_DAC0_TR 0x40004608 +#define CYDEV_MFGCFG_ANAIF_DAC1_BASE 0x40004609 +#define CYDEV_MFGCFG_ANAIF_DAC1_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_DAC1_TR 0x40004609 +#define CYDEV_MFGCFG_ANAIF_DAC2_BASE 0x4000460a +#define CYDEV_MFGCFG_ANAIF_DAC2_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_DAC2_TR 0x4000460a +#define CYDEV_MFGCFG_ANAIF_DAC3_BASE 0x4000460b +#define CYDEV_MFGCFG_ANAIF_DAC3_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_DAC3_TR 0x4000460b +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE 0x40004610 +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0 0x40004610 +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE 0x40004611 +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0 0x40004611 +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE 0x40004612 +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0 0x40004612 +#define CYDEV_MFGCFG_ANAIF_SAR0_BASE 0x40004614 +#define CYDEV_MFGCFG_ANAIF_SAR0_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_SAR0_TR0 0x40004614 +#define CYDEV_MFGCFG_ANAIF_SAR1_BASE 0x40004616 +#define CYDEV_MFGCFG_ANAIF_SAR1_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_SAR1_TR0 0x40004616 +#define CYDEV_MFGCFG_ANAIF_OPAMP0_BASE 0x40004620 +#define CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE 0x00000002 +#define CYDEV_MFGCFG_ANAIF_OPAMP0_TR0 0x40004620 +#define CYDEV_MFGCFG_ANAIF_OPAMP0_TR1 0x40004621 +#define CYDEV_MFGCFG_ANAIF_OPAMP1_BASE 0x40004622 +#define CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE 0x00000002 +#define CYDEV_MFGCFG_ANAIF_OPAMP1_TR0 0x40004622 +#define CYDEV_MFGCFG_ANAIF_OPAMP1_TR1 0x40004623 +#define CYDEV_MFGCFG_ANAIF_OPAMP2_BASE 0x40004624 +#define CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE 0x00000002 +#define CYDEV_MFGCFG_ANAIF_OPAMP2_TR0 0x40004624 +#define CYDEV_MFGCFG_ANAIF_OPAMP2_TR1 0x40004625 +#define CYDEV_MFGCFG_ANAIF_OPAMP3_BASE 0x40004626 +#define CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE 0x00000002 +#define CYDEV_MFGCFG_ANAIF_OPAMP3_TR0 0x40004626 +#define CYDEV_MFGCFG_ANAIF_OPAMP3_TR1 0x40004627 +#define CYDEV_MFGCFG_ANAIF_CMP0_BASE 0x40004630 +#define CYDEV_MFGCFG_ANAIF_CMP0_SIZE 0x00000002 +#define CYDEV_MFGCFG_ANAIF_CMP0_TR0 0x40004630 +#define CYDEV_MFGCFG_ANAIF_CMP0_TR1 0x40004631 +#define CYDEV_MFGCFG_ANAIF_CMP1_BASE 0x40004632 +#define CYDEV_MFGCFG_ANAIF_CMP1_SIZE 0x00000002 +#define CYDEV_MFGCFG_ANAIF_CMP1_TR0 0x40004632 +#define CYDEV_MFGCFG_ANAIF_CMP1_TR1 0x40004633 +#define CYDEV_MFGCFG_ANAIF_CMP2_BASE 0x40004634 +#define CYDEV_MFGCFG_ANAIF_CMP2_SIZE 0x00000002 +#define CYDEV_MFGCFG_ANAIF_CMP2_TR0 0x40004634 +#define CYDEV_MFGCFG_ANAIF_CMP2_TR1 0x40004635 +#define CYDEV_MFGCFG_ANAIF_CMP3_BASE 0x40004636 +#define CYDEV_MFGCFG_ANAIF_CMP3_SIZE 0x00000002 +#define CYDEV_MFGCFG_ANAIF_CMP3_TR0 0x40004636 +#define CYDEV_MFGCFG_ANAIF_CMP3_TR1 0x40004637 +#define CYDEV_MFGCFG_PWRSYS_BASE 0x40004680 +#define CYDEV_MFGCFG_PWRSYS_SIZE 0x0000000b +#define CYDEV_MFGCFG_PWRSYS_HIB_TR0 0x40004680 +#define CYDEV_MFGCFG_PWRSYS_HIB_TR1 0x40004681 +#define CYDEV_MFGCFG_PWRSYS_I2C_TR 0x40004682 +#define CYDEV_MFGCFG_PWRSYS_SLP_TR 0x40004683 +#define CYDEV_MFGCFG_PWRSYS_BUZZ_TR 0x40004684 +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR0 0x40004685 +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR1 0x40004686 +#define CYDEV_MFGCFG_PWRSYS_BREF_TR 0x40004687 +#define CYDEV_MFGCFG_PWRSYS_BG_TR 0x40004688 +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR2 0x40004689 +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR3 0x4000468a +#define CYDEV_MFGCFG_ILO_BASE 0x40004690 +#define CYDEV_MFGCFG_ILO_SIZE 0x00000002 +#define CYDEV_MFGCFG_ILO_TR0 0x40004690 +#define CYDEV_MFGCFG_ILO_TR1 0x40004691 +#define CYDEV_MFGCFG_X32_BASE 0x40004698 +#define CYDEV_MFGCFG_X32_SIZE 0x00000001 +#define CYDEV_MFGCFG_X32_TR 0x40004698 +#define CYDEV_MFGCFG_IMO_BASE 0x400046a0 +#define CYDEV_MFGCFG_IMO_SIZE 0x00000005 +#define CYDEV_MFGCFG_IMO_TR0 0x400046a0 +#define CYDEV_MFGCFG_IMO_TR1 0x400046a1 +#define CYDEV_MFGCFG_IMO_GAIN 0x400046a2 +#define CYDEV_MFGCFG_IMO_C36M 0x400046a3 +#define CYDEV_MFGCFG_IMO_TR2 0x400046a4 +#define CYDEV_MFGCFG_XMHZ_BASE 0x400046a8 +#define CYDEV_MFGCFG_XMHZ_SIZE 0x00000001 +#define CYDEV_MFGCFG_XMHZ_TR 0x400046a8 +#define CYDEV_MFGCFG_DLY 0x400046c0 +#define CYDEV_MFGCFG_MLOGIC_BASE 0x400046e0 +#define CYDEV_MFGCFG_MLOGIC_SIZE 0x0000000d +#define CYDEV_MFGCFG_MLOGIC_DMPSTR 0x400046e2 +#define CYDEV_MFGCFG_MLOGIC_SEG_BASE 0x400046e4 +#define CYDEV_MFGCFG_MLOGIC_SEG_SIZE 0x00000002 +#define CYDEV_MFGCFG_MLOGIC_SEG_CR 0x400046e4 +#define CYDEV_MFGCFG_MLOGIC_SEG_CFG0 0x400046e5 +#define CYDEV_MFGCFG_MLOGIC_DEBUG 0x400046e8 +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE 0x400046ea +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE 0x00000001 +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR 0x400046ea +#define CYDEV_MFGCFG_MLOGIC_REV_ID 0x400046ec +#define CYDEV_RESET_BASE 0x400046f0 +#define CYDEV_RESET_SIZE 0x0000000f +#define CYDEV_RESET_IPOR_CR0 0x400046f0 +#define CYDEV_RESET_IPOR_CR1 0x400046f1 +#define CYDEV_RESET_IPOR_CR2 0x400046f2 +#define CYDEV_RESET_IPOR_CR3 0x400046f3 +#define CYDEV_RESET_CR0 0x400046f4 +#define CYDEV_RESET_CR1 0x400046f5 +#define CYDEV_RESET_CR2 0x400046f6 +#define CYDEV_RESET_CR3 0x400046f7 +#define CYDEV_RESET_CR4 0x400046f8 +#define CYDEV_RESET_CR5 0x400046f9 +#define CYDEV_RESET_SR0 0x400046fa +#define CYDEV_RESET_SR1 0x400046fb +#define CYDEV_RESET_SR2 0x400046fc +#define CYDEV_RESET_SR3 0x400046fd +#define CYDEV_RESET_TR 0x400046fe +#define CYDEV_SPC_BASE 0x40004700 +#define CYDEV_SPC_SIZE 0x00000100 +#define CYDEV_SPC_FM_EE_CR 0x40004700 +#define CYDEV_SPC_FM_EE_WAKE_CNT 0x40004701 +#define CYDEV_SPC_EE_SCR 0x40004702 +#define CYDEV_SPC_EE_ERR 0x40004703 +#define CYDEV_SPC_CPU_DATA 0x40004720 +#define CYDEV_SPC_DMA_DATA 0x40004721 +#define CYDEV_SPC_SR 0x40004722 +#define CYDEV_SPC_CR 0x40004723 +#define CYDEV_SPC_DMM_MAP_BASE 0x40004780 +#define CYDEV_SPC_DMM_MAP_SIZE 0x00000080 +#define CYDEV_SPC_DMM_MAP_SRAM_MBASE 0x40004780 +#define CYDEV_SPC_DMM_MAP_SRAM_MSIZE 0x00000080 +#define CYDEV_CACHE_BASE 0x40004800 +#define CYDEV_CACHE_SIZE 0x0000009c +#define CYDEV_CACHE_CC_CTL 0x40004800 +#define CYDEV_CACHE_ECC_CORR 0x40004880 +#define CYDEV_CACHE_ECC_ERR 0x40004888 +#define CYDEV_CACHE_FLASH_ERR 0x40004890 +#define CYDEV_CACHE_HITMISS 0x40004898 +#define CYDEV_I2C_BASE 0x40004900 +#define CYDEV_I2C_SIZE 0x000000e1 +#define CYDEV_I2C_XCFG 0x400049c8 +#define CYDEV_I2C_ADR 0x400049ca +#define CYDEV_I2C_CFG 0x400049d6 +#define CYDEV_I2C_CSR 0x400049d7 +#define CYDEV_I2C_D 0x400049d8 +#define CYDEV_I2C_MCSR 0x400049d9 +#define CYDEV_I2C_CLK_DIV1 0x400049db +#define CYDEV_I2C_CLK_DIV2 0x400049dc +#define CYDEV_I2C_TMOUT_CSR 0x400049dd +#define CYDEV_I2C_TMOUT_SR 0x400049de +#define CYDEV_I2C_TMOUT_CFG0 0x400049df +#define CYDEV_I2C_TMOUT_CFG1 0x400049e0 +#define CYDEV_DEC_BASE 0x40004e00 +#define CYDEV_DEC_SIZE 0x00000015 +#define CYDEV_DEC_CR 0x40004e00 +#define CYDEV_DEC_SR 0x40004e01 +#define CYDEV_DEC_SHIFT1 0x40004e02 +#define CYDEV_DEC_SHIFT2 0x40004e03 +#define CYDEV_DEC_DR2 0x40004e04 +#define CYDEV_DEC_DR2H 0x40004e05 +#define CYDEV_DEC_DR1 0x40004e06 +#define CYDEV_DEC_OCOR 0x40004e08 +#define CYDEV_DEC_OCORM 0x40004e09 +#define CYDEV_DEC_OCORH 0x40004e0a +#define CYDEV_DEC_GCOR 0x40004e0c +#define CYDEV_DEC_GCORH 0x40004e0d +#define CYDEV_DEC_GVAL 0x40004e0e +#define CYDEV_DEC_OUTSAMP 0x40004e10 +#define CYDEV_DEC_OUTSAMPM 0x40004e11 +#define CYDEV_DEC_OUTSAMPH 0x40004e12 +#define CYDEV_DEC_OUTSAMPS 0x40004e13 +#define CYDEV_DEC_COHER 0x40004e14 +#define CYDEV_TMR0_BASE 0x40004f00 +#define CYDEV_TMR0_SIZE 0x0000000c +#define CYDEV_TMR0_CFG0 0x40004f00 +#define CYDEV_TMR0_CFG1 0x40004f01 +#define CYDEV_TMR0_CFG2 0x40004f02 +#define CYDEV_TMR0_SR0 0x40004f03 +#define CYDEV_TMR0_PER0 0x40004f04 +#define CYDEV_TMR0_PER1 0x40004f05 +#define CYDEV_TMR0_CNT_CMP0 0x40004f06 +#define CYDEV_TMR0_CNT_CMP1 0x40004f07 +#define CYDEV_TMR0_CAP0 0x40004f08 +#define CYDEV_TMR0_CAP1 0x40004f09 +#define CYDEV_TMR0_RT0 0x40004f0a +#define CYDEV_TMR0_RT1 0x40004f0b +#define CYDEV_TMR1_BASE 0x40004f0c +#define CYDEV_TMR1_SIZE 0x0000000c +#define CYDEV_TMR1_CFG0 0x40004f0c +#define CYDEV_TMR1_CFG1 0x40004f0d +#define CYDEV_TMR1_CFG2 0x40004f0e +#define CYDEV_TMR1_SR0 0x40004f0f +#define CYDEV_TMR1_PER0 0x40004f10 +#define CYDEV_TMR1_PER1 0x40004f11 +#define CYDEV_TMR1_CNT_CMP0 0x40004f12 +#define CYDEV_TMR1_CNT_CMP1 0x40004f13 +#define CYDEV_TMR1_CAP0 0x40004f14 +#define CYDEV_TMR1_CAP1 0x40004f15 +#define CYDEV_TMR1_RT0 0x40004f16 +#define CYDEV_TMR1_RT1 0x40004f17 +#define CYDEV_TMR2_BASE 0x40004f18 +#define CYDEV_TMR2_SIZE 0x0000000c +#define CYDEV_TMR2_CFG0 0x40004f18 +#define CYDEV_TMR2_CFG1 0x40004f19 +#define CYDEV_TMR2_CFG2 0x40004f1a +#define CYDEV_TMR2_SR0 0x40004f1b +#define CYDEV_TMR2_PER0 0x40004f1c +#define CYDEV_TMR2_PER1 0x40004f1d +#define CYDEV_TMR2_CNT_CMP0 0x40004f1e +#define CYDEV_TMR2_CNT_CMP1 0x40004f1f +#define CYDEV_TMR2_CAP0 0x40004f20 +#define CYDEV_TMR2_CAP1 0x40004f21 +#define CYDEV_TMR2_RT0 0x40004f22 +#define CYDEV_TMR2_RT1 0x40004f23 +#define CYDEV_TMR3_BASE 0x40004f24 +#define CYDEV_TMR3_SIZE 0x0000000c +#define CYDEV_TMR3_CFG0 0x40004f24 +#define CYDEV_TMR3_CFG1 0x40004f25 +#define CYDEV_TMR3_CFG2 0x40004f26 +#define CYDEV_TMR3_SR0 0x40004f27 +#define CYDEV_TMR3_PER0 0x40004f28 +#define CYDEV_TMR3_PER1 0x40004f29 +#define CYDEV_TMR3_CNT_CMP0 0x40004f2a +#define CYDEV_TMR3_CNT_CMP1 0x40004f2b +#define CYDEV_TMR3_CAP0 0x40004f2c +#define CYDEV_TMR3_CAP1 0x40004f2d +#define CYDEV_TMR3_RT0 0x40004f2e +#define CYDEV_TMR3_RT1 0x40004f2f +#define CYDEV_IO_BASE 0x40005000 +#define CYDEV_IO_SIZE 0x00000200 +#define CYDEV_IO_PC_BASE 0x40005000 +#define CYDEV_IO_PC_SIZE 0x00000080 +#define CYDEV_IO_PC_PRT0_BASE 0x40005000 +#define CYDEV_IO_PC_PRT0_SIZE 0x00000008 +#define CYDEV_IO_PC_PRT0_PC0 0x40005000 +#define CYDEV_IO_PC_PRT0_PC1 0x40005001 +#define CYDEV_IO_PC_PRT0_PC2 0x40005002 +#define CYDEV_IO_PC_PRT0_PC3 0x40005003 +#define CYDEV_IO_PC_PRT0_PC4 0x40005004 +#define CYDEV_IO_PC_PRT0_PC5 0x40005005 +#define CYDEV_IO_PC_PRT0_PC6 0x40005006 +#define CYDEV_IO_PC_PRT0_PC7 0x40005007 +#define CYDEV_IO_PC_PRT1_BASE 0x40005008 +#define CYDEV_IO_PC_PRT1_SIZE 0x00000008 +#define CYDEV_IO_PC_PRT1_PC0 0x40005008 +#define CYDEV_IO_PC_PRT1_PC1 0x40005009 +#define CYDEV_IO_PC_PRT1_PC2 0x4000500a +#define CYDEV_IO_PC_PRT1_PC3 0x4000500b +#define CYDEV_IO_PC_PRT1_PC4 0x4000500c +#define CYDEV_IO_PC_PRT1_PC5 0x4000500d +#define CYDEV_IO_PC_PRT1_PC6 0x4000500e +#define CYDEV_IO_PC_PRT1_PC7 0x4000500f +#define CYDEV_IO_PC_PRT2_BASE 0x40005010 +#define CYDEV_IO_PC_PRT2_SIZE 0x00000008 +#define CYDEV_IO_PC_PRT2_PC0 0x40005010 +#define CYDEV_IO_PC_PRT2_PC1 0x40005011 +#define CYDEV_IO_PC_PRT2_PC2 0x40005012 +#define CYDEV_IO_PC_PRT2_PC3 0x40005013 +#define CYDEV_IO_PC_PRT2_PC4 0x40005014 +#define CYDEV_IO_PC_PRT2_PC5 0x40005015 +#define CYDEV_IO_PC_PRT2_PC6 0x40005016 +#define CYDEV_IO_PC_PRT2_PC7 0x40005017 +#define CYDEV_IO_PC_PRT3_BASE 0x40005018 +#define CYDEV_IO_PC_PRT3_SIZE 0x00000008 +#define CYDEV_IO_PC_PRT3_PC0 0x40005018 +#define CYDEV_IO_PC_PRT3_PC1 0x40005019 +#define CYDEV_IO_PC_PRT3_PC2 0x4000501a +#define CYDEV_IO_PC_PRT3_PC3 0x4000501b +#define CYDEV_IO_PC_PRT3_PC4 0x4000501c +#define CYDEV_IO_PC_PRT3_PC5 0x4000501d +#define CYDEV_IO_PC_PRT3_PC6 0x4000501e +#define CYDEV_IO_PC_PRT3_PC7 0x4000501f +#define CYDEV_IO_PC_PRT4_BASE 0x40005020 +#define CYDEV_IO_PC_PRT4_SIZE 0x00000008 +#define CYDEV_IO_PC_PRT4_PC0 0x40005020 +#define CYDEV_IO_PC_PRT4_PC1 0x40005021 +#define CYDEV_IO_PC_PRT4_PC2 0x40005022 +#define CYDEV_IO_PC_PRT4_PC3 0x40005023 +#define CYDEV_IO_PC_PRT4_PC4 0x40005024 +#define CYDEV_IO_PC_PRT4_PC5 0x40005025 +#define CYDEV_IO_PC_PRT4_PC6 0x40005026 +#define CYDEV_IO_PC_PRT4_PC7 0x40005027 +#define CYDEV_IO_PC_PRT5_BASE 0x40005028 +#define CYDEV_IO_PC_PRT5_SIZE 0x00000008 +#define CYDEV_IO_PC_PRT5_PC0 0x40005028 +#define CYDEV_IO_PC_PRT5_PC1 0x40005029 +#define CYDEV_IO_PC_PRT5_PC2 0x4000502a +#define CYDEV_IO_PC_PRT5_PC3 0x4000502b +#define CYDEV_IO_PC_PRT5_PC4 0x4000502c +#define CYDEV_IO_PC_PRT5_PC5 0x4000502d +#define CYDEV_IO_PC_PRT5_PC6 0x4000502e +#define CYDEV_IO_PC_PRT5_PC7 0x4000502f +#define CYDEV_IO_PC_PRT6_BASE 0x40005030 +#define CYDEV_IO_PC_PRT6_SIZE 0x00000008 +#define CYDEV_IO_PC_PRT6_PC0 0x40005030 +#define CYDEV_IO_PC_PRT6_PC1 0x40005031 +#define CYDEV_IO_PC_PRT6_PC2 0x40005032 +#define CYDEV_IO_PC_PRT6_PC3 0x40005033 +#define CYDEV_IO_PC_PRT6_PC4 0x40005034 +#define CYDEV_IO_PC_PRT6_PC5 0x40005035 +#define CYDEV_IO_PC_PRT6_PC6 0x40005036 +#define CYDEV_IO_PC_PRT6_PC7 0x40005037 +#define CYDEV_IO_PC_PRT12_BASE 0x40005060 +#define CYDEV_IO_PC_PRT12_SIZE 0x00000008 +#define CYDEV_IO_PC_PRT12_PC0 0x40005060 +#define CYDEV_IO_PC_PRT12_PC1 0x40005061 +#define CYDEV_IO_PC_PRT12_PC2 0x40005062 +#define CYDEV_IO_PC_PRT12_PC3 0x40005063 +#define CYDEV_IO_PC_PRT12_PC4 0x40005064 +#define CYDEV_IO_PC_PRT12_PC5 0x40005065 +#define CYDEV_IO_PC_PRT12_PC6 0x40005066 +#define CYDEV_IO_PC_PRT12_PC7 0x40005067 +#define CYDEV_IO_PC_PRT15_BASE 0x40005078 +#define CYDEV_IO_PC_PRT15_SIZE 0x00000006 +#define CYDEV_IO_PC_PRT15_PC0 0x40005078 +#define CYDEV_IO_PC_PRT15_PC1 0x40005079 +#define CYDEV_IO_PC_PRT15_PC2 0x4000507a +#define CYDEV_IO_PC_PRT15_PC3 0x4000507b +#define CYDEV_IO_PC_PRT15_PC4 0x4000507c +#define CYDEV_IO_PC_PRT15_PC5 0x4000507d +#define CYDEV_IO_PC_PRT15_7_6_BASE 0x4000507e +#define CYDEV_IO_PC_PRT15_7_6_SIZE 0x00000002 +#define CYDEV_IO_PC_PRT15_7_6_PC0 0x4000507e +#define CYDEV_IO_PC_PRT15_7_6_PC1 0x4000507f +#define CYDEV_IO_DR_BASE 0x40005080 +#define CYDEV_IO_DR_SIZE 0x00000010 +#define CYDEV_IO_DR_PRT0_BASE 0x40005080 +#define CYDEV_IO_DR_PRT0_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT0_DR_ALIAS 0x40005080 +#define CYDEV_IO_DR_PRT1_BASE 0x40005081 +#define CYDEV_IO_DR_PRT1_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT1_DR_ALIAS 0x40005081 +#define CYDEV_IO_DR_PRT2_BASE 0x40005082 +#define CYDEV_IO_DR_PRT2_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT2_DR_ALIAS 0x40005082 +#define CYDEV_IO_DR_PRT3_BASE 0x40005083 +#define CYDEV_IO_DR_PRT3_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT3_DR_ALIAS 0x40005083 +#define CYDEV_IO_DR_PRT4_BASE 0x40005084 +#define CYDEV_IO_DR_PRT4_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT4_DR_ALIAS 0x40005084 +#define CYDEV_IO_DR_PRT5_BASE 0x40005085 +#define CYDEV_IO_DR_PRT5_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT5_DR_ALIAS 0x40005085 +#define CYDEV_IO_DR_PRT6_BASE 0x40005086 +#define CYDEV_IO_DR_PRT6_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT6_DR_ALIAS 0x40005086 +#define CYDEV_IO_DR_PRT12_BASE 0x4000508c +#define CYDEV_IO_DR_PRT12_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT12_DR_ALIAS 0x4000508c +#define CYDEV_IO_DR_PRT15_BASE 0x4000508f +#define CYDEV_IO_DR_PRT15_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT15_DR_15_ALIAS 0x4000508f +#define CYDEV_IO_PS_BASE 0x40005090 +#define CYDEV_IO_PS_SIZE 0x00000010 +#define CYDEV_IO_PS_PRT0_BASE 0x40005090 +#define CYDEV_IO_PS_PRT0_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT0_PS_ALIAS 0x40005090 +#define CYDEV_IO_PS_PRT1_BASE 0x40005091 +#define CYDEV_IO_PS_PRT1_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT1_PS_ALIAS 0x40005091 +#define CYDEV_IO_PS_PRT2_BASE 0x40005092 +#define CYDEV_IO_PS_PRT2_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT2_PS_ALIAS 0x40005092 +#define CYDEV_IO_PS_PRT3_BASE 0x40005093 +#define CYDEV_IO_PS_PRT3_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT3_PS_ALIAS 0x40005093 +#define CYDEV_IO_PS_PRT4_BASE 0x40005094 +#define CYDEV_IO_PS_PRT4_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT4_PS_ALIAS 0x40005094 +#define CYDEV_IO_PS_PRT5_BASE 0x40005095 +#define CYDEV_IO_PS_PRT5_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT5_PS_ALIAS 0x40005095 +#define CYDEV_IO_PS_PRT6_BASE 0x40005096 +#define CYDEV_IO_PS_PRT6_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT6_PS_ALIAS 0x40005096 +#define CYDEV_IO_PS_PRT12_BASE 0x4000509c +#define CYDEV_IO_PS_PRT12_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT12_PS_ALIAS 0x4000509c +#define CYDEV_IO_PS_PRT15_BASE 0x4000509f +#define CYDEV_IO_PS_PRT15_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT15_PS15_ALIAS 0x4000509f +#define CYDEV_IO_PRT_BASE 0x40005100 +#define CYDEV_IO_PRT_SIZE 0x00000100 +#define CYDEV_IO_PRT_PRT0_BASE 0x40005100 +#define CYDEV_IO_PRT_PRT0_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT0_DR 0x40005100 +#define CYDEV_IO_PRT_PRT0_PS 0x40005101 +#define CYDEV_IO_PRT_PRT0_DM0 0x40005102 +#define CYDEV_IO_PRT_PRT0_DM1 0x40005103 +#define CYDEV_IO_PRT_PRT0_DM2 0x40005104 +#define CYDEV_IO_PRT_PRT0_SLW 0x40005105 +#define CYDEV_IO_PRT_PRT0_BYP 0x40005106 +#define CYDEV_IO_PRT_PRT0_BIE 0x40005107 +#define CYDEV_IO_PRT_PRT0_INP_DIS 0x40005108 +#define CYDEV_IO_PRT_PRT0_CTL 0x40005109 +#define CYDEV_IO_PRT_PRT0_PRT 0x4000510a +#define CYDEV_IO_PRT_PRT0_BIT_MASK 0x4000510b +#define CYDEV_IO_PRT_PRT0_AMUX 0x4000510c +#define CYDEV_IO_PRT_PRT0_AG 0x4000510d +#define CYDEV_IO_PRT_PRT0_LCD_COM_SEG 0x4000510e +#define CYDEV_IO_PRT_PRT0_LCD_EN 0x4000510f +#define CYDEV_IO_PRT_PRT1_BASE 0x40005110 +#define CYDEV_IO_PRT_PRT1_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT1_DR 0x40005110 +#define CYDEV_IO_PRT_PRT1_PS 0x40005111 +#define CYDEV_IO_PRT_PRT1_DM0 0x40005112 +#define CYDEV_IO_PRT_PRT1_DM1 0x40005113 +#define CYDEV_IO_PRT_PRT1_DM2 0x40005114 +#define CYDEV_IO_PRT_PRT1_SLW 0x40005115 +#define CYDEV_IO_PRT_PRT1_BYP 0x40005116 +#define CYDEV_IO_PRT_PRT1_BIE 0x40005117 +#define CYDEV_IO_PRT_PRT1_INP_DIS 0x40005118 +#define CYDEV_IO_PRT_PRT1_CTL 0x40005119 +#define CYDEV_IO_PRT_PRT1_PRT 0x4000511a +#define CYDEV_IO_PRT_PRT1_BIT_MASK 0x4000511b +#define CYDEV_IO_PRT_PRT1_AMUX 0x4000511c +#define CYDEV_IO_PRT_PRT1_AG 0x4000511d +#define CYDEV_IO_PRT_PRT1_LCD_COM_SEG 0x4000511e +#define CYDEV_IO_PRT_PRT1_LCD_EN 0x4000511f +#define CYDEV_IO_PRT_PRT2_BASE 0x40005120 +#define CYDEV_IO_PRT_PRT2_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT2_DR 0x40005120 +#define CYDEV_IO_PRT_PRT2_PS 0x40005121 +#define CYDEV_IO_PRT_PRT2_DM0 0x40005122 +#define CYDEV_IO_PRT_PRT2_DM1 0x40005123 +#define CYDEV_IO_PRT_PRT2_DM2 0x40005124 +#define CYDEV_IO_PRT_PRT2_SLW 0x40005125 +#define CYDEV_IO_PRT_PRT2_BYP 0x40005126 +#define CYDEV_IO_PRT_PRT2_BIE 0x40005127 +#define CYDEV_IO_PRT_PRT2_INP_DIS 0x40005128 +#define CYDEV_IO_PRT_PRT2_CTL 0x40005129 +#define CYDEV_IO_PRT_PRT2_PRT 0x4000512a +#define CYDEV_IO_PRT_PRT2_BIT_MASK 0x4000512b +#define CYDEV_IO_PRT_PRT2_AMUX 0x4000512c +#define CYDEV_IO_PRT_PRT2_AG 0x4000512d +#define CYDEV_IO_PRT_PRT2_LCD_COM_SEG 0x4000512e +#define CYDEV_IO_PRT_PRT2_LCD_EN 0x4000512f +#define CYDEV_IO_PRT_PRT3_BASE 0x40005130 +#define CYDEV_IO_PRT_PRT3_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT3_DR 0x40005130 +#define CYDEV_IO_PRT_PRT3_PS 0x40005131 +#define CYDEV_IO_PRT_PRT3_DM0 0x40005132 +#define CYDEV_IO_PRT_PRT3_DM1 0x40005133 +#define CYDEV_IO_PRT_PRT3_DM2 0x40005134 +#define CYDEV_IO_PRT_PRT3_SLW 0x40005135 +#define CYDEV_IO_PRT_PRT3_BYP 0x40005136 +#define CYDEV_IO_PRT_PRT3_BIE 0x40005137 +#define CYDEV_IO_PRT_PRT3_INP_DIS 0x40005138 +#define CYDEV_IO_PRT_PRT3_CTL 0x40005139 +#define CYDEV_IO_PRT_PRT3_PRT 0x4000513a +#define CYDEV_IO_PRT_PRT3_BIT_MASK 0x4000513b +#define CYDEV_IO_PRT_PRT3_AMUX 0x4000513c +#define CYDEV_IO_PRT_PRT3_AG 0x4000513d +#define CYDEV_IO_PRT_PRT3_LCD_COM_SEG 0x4000513e +#define CYDEV_IO_PRT_PRT3_LCD_EN 0x4000513f +#define CYDEV_IO_PRT_PRT4_BASE 0x40005140 +#define CYDEV_IO_PRT_PRT4_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT4_DR 0x40005140 +#define CYDEV_IO_PRT_PRT4_PS 0x40005141 +#define CYDEV_IO_PRT_PRT4_DM0 0x40005142 +#define CYDEV_IO_PRT_PRT4_DM1 0x40005143 +#define CYDEV_IO_PRT_PRT4_DM2 0x40005144 +#define CYDEV_IO_PRT_PRT4_SLW 0x40005145 +#define CYDEV_IO_PRT_PRT4_BYP 0x40005146 +#define CYDEV_IO_PRT_PRT4_BIE 0x40005147 +#define CYDEV_IO_PRT_PRT4_INP_DIS 0x40005148 +#define CYDEV_IO_PRT_PRT4_CTL 0x40005149 +#define CYDEV_IO_PRT_PRT4_PRT 0x4000514a +#define CYDEV_IO_PRT_PRT4_BIT_MASK 0x4000514b +#define CYDEV_IO_PRT_PRT4_AMUX 0x4000514c +#define CYDEV_IO_PRT_PRT4_AG 0x4000514d +#define CYDEV_IO_PRT_PRT4_LCD_COM_SEG 0x4000514e +#define CYDEV_IO_PRT_PRT4_LCD_EN 0x4000514f +#define CYDEV_IO_PRT_PRT5_BASE 0x40005150 +#define CYDEV_IO_PRT_PRT5_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT5_DR 0x40005150 +#define CYDEV_IO_PRT_PRT5_PS 0x40005151 +#define CYDEV_IO_PRT_PRT5_DM0 0x40005152 +#define CYDEV_IO_PRT_PRT5_DM1 0x40005153 +#define CYDEV_IO_PRT_PRT5_DM2 0x40005154 +#define CYDEV_IO_PRT_PRT5_SLW 0x40005155 +#define CYDEV_IO_PRT_PRT5_BYP 0x40005156 +#define CYDEV_IO_PRT_PRT5_BIE 0x40005157 +#define CYDEV_IO_PRT_PRT5_INP_DIS 0x40005158 +#define CYDEV_IO_PRT_PRT5_CTL 0x40005159 +#define CYDEV_IO_PRT_PRT5_PRT 0x4000515a +#define CYDEV_IO_PRT_PRT5_BIT_MASK 0x4000515b +#define CYDEV_IO_PRT_PRT5_AMUX 0x4000515c +#define CYDEV_IO_PRT_PRT5_AG 0x4000515d +#define CYDEV_IO_PRT_PRT5_LCD_COM_SEG 0x4000515e +#define CYDEV_IO_PRT_PRT5_LCD_EN 0x4000515f +#define CYDEV_IO_PRT_PRT6_BASE 0x40005160 +#define CYDEV_IO_PRT_PRT6_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT6_DR 0x40005160 +#define CYDEV_IO_PRT_PRT6_PS 0x40005161 +#define CYDEV_IO_PRT_PRT6_DM0 0x40005162 +#define CYDEV_IO_PRT_PRT6_DM1 0x40005163 +#define CYDEV_IO_PRT_PRT6_DM2 0x40005164 +#define CYDEV_IO_PRT_PRT6_SLW 0x40005165 +#define CYDEV_IO_PRT_PRT6_BYP 0x40005166 +#define CYDEV_IO_PRT_PRT6_BIE 0x40005167 +#define CYDEV_IO_PRT_PRT6_INP_DIS 0x40005168 +#define CYDEV_IO_PRT_PRT6_CTL 0x40005169 +#define CYDEV_IO_PRT_PRT6_PRT 0x4000516a +#define CYDEV_IO_PRT_PRT6_BIT_MASK 0x4000516b +#define CYDEV_IO_PRT_PRT6_AMUX 0x4000516c +#define CYDEV_IO_PRT_PRT6_AG 0x4000516d +#define CYDEV_IO_PRT_PRT6_LCD_COM_SEG 0x4000516e +#define CYDEV_IO_PRT_PRT6_LCD_EN 0x4000516f +#define CYDEV_IO_PRT_PRT12_BASE 0x400051c0 +#define CYDEV_IO_PRT_PRT12_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT12_DR 0x400051c0 +#define CYDEV_IO_PRT_PRT12_PS 0x400051c1 +#define CYDEV_IO_PRT_PRT12_DM0 0x400051c2 +#define CYDEV_IO_PRT_PRT12_DM1 0x400051c3 +#define CYDEV_IO_PRT_PRT12_DM2 0x400051c4 +#define CYDEV_IO_PRT_PRT12_SLW 0x400051c5 +#define CYDEV_IO_PRT_PRT12_BYP 0x400051c6 +#define CYDEV_IO_PRT_PRT12_BIE 0x400051c7 +#define CYDEV_IO_PRT_PRT12_INP_DIS 0x400051c8 +#define CYDEV_IO_PRT_PRT12_SIO_HYST_EN 0x400051c9 +#define CYDEV_IO_PRT_PRT12_PRT 0x400051ca +#define CYDEV_IO_PRT_PRT12_BIT_MASK 0x400051cb +#define CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ 0x400051cc +#define CYDEV_IO_PRT_PRT12_AG 0x400051cd +#define CYDEV_IO_PRT_PRT12_SIO_CFG 0x400051ce +#define CYDEV_IO_PRT_PRT12_SIO_DIFF 0x400051cf +#define CYDEV_IO_PRT_PRT15_BASE 0x400051f0 +#define CYDEV_IO_PRT_PRT15_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT15_DR 0x400051f0 +#define CYDEV_IO_PRT_PRT15_PS 0x400051f1 +#define CYDEV_IO_PRT_PRT15_DM0 0x400051f2 +#define CYDEV_IO_PRT_PRT15_DM1 0x400051f3 +#define CYDEV_IO_PRT_PRT15_DM2 0x400051f4 +#define CYDEV_IO_PRT_PRT15_SLW 0x400051f5 +#define CYDEV_IO_PRT_PRT15_BYP 0x400051f6 +#define CYDEV_IO_PRT_PRT15_BIE 0x400051f7 +#define CYDEV_IO_PRT_PRT15_INP_DIS 0x400051f8 +#define CYDEV_IO_PRT_PRT15_CTL 0x400051f9 +#define CYDEV_IO_PRT_PRT15_PRT 0x400051fa +#define CYDEV_IO_PRT_PRT15_BIT_MASK 0x400051fb +#define CYDEV_IO_PRT_PRT15_AMUX 0x400051fc +#define CYDEV_IO_PRT_PRT15_AG 0x400051fd +#define CYDEV_IO_PRT_PRT15_LCD_COM_SEG 0x400051fe +#define CYDEV_IO_PRT_PRT15_LCD_EN 0x400051ff +#define CYDEV_PRTDSI_BASE 0x40005200 +#define CYDEV_PRTDSI_SIZE 0x0000007f +#define CYDEV_PRTDSI_PRT0_BASE 0x40005200 +#define CYDEV_PRTDSI_PRT0_SIZE 0x00000007 +#define CYDEV_PRTDSI_PRT0_OUT_SEL0 0x40005200 +#define CYDEV_PRTDSI_PRT0_OUT_SEL1 0x40005201 +#define CYDEV_PRTDSI_PRT0_OE_SEL0 0x40005202 +#define CYDEV_PRTDSI_PRT0_OE_SEL1 0x40005203 +#define CYDEV_PRTDSI_PRT0_DBL_SYNC_IN 0x40005204 +#define CYDEV_PRTDSI_PRT0_SYNC_OUT 0x40005205 +#define CYDEV_PRTDSI_PRT0_CAPS_SEL 0x40005206 +#define CYDEV_PRTDSI_PRT1_BASE 0x40005208 +#define CYDEV_PRTDSI_PRT1_SIZE 0x00000007 +#define CYDEV_PRTDSI_PRT1_OUT_SEL0 0x40005208 +#define CYDEV_PRTDSI_PRT1_OUT_SEL1 0x40005209 +#define CYDEV_PRTDSI_PRT1_OE_SEL0 0x4000520a +#define CYDEV_PRTDSI_PRT1_OE_SEL1 0x4000520b +#define CYDEV_PRTDSI_PRT1_DBL_SYNC_IN 0x4000520c +#define CYDEV_PRTDSI_PRT1_SYNC_OUT 0x4000520d +#define CYDEV_PRTDSI_PRT1_CAPS_SEL 0x4000520e +#define CYDEV_PRTDSI_PRT2_BASE 0x40005210 +#define CYDEV_PRTDSI_PRT2_SIZE 0x00000007 +#define CYDEV_PRTDSI_PRT2_OUT_SEL0 0x40005210 +#define CYDEV_PRTDSI_PRT2_OUT_SEL1 0x40005211 +#define CYDEV_PRTDSI_PRT2_OE_SEL0 0x40005212 +#define CYDEV_PRTDSI_PRT2_OE_SEL1 0x40005213 +#define CYDEV_PRTDSI_PRT2_DBL_SYNC_IN 0x40005214 +#define CYDEV_PRTDSI_PRT2_SYNC_OUT 0x40005215 +#define CYDEV_PRTDSI_PRT2_CAPS_SEL 0x40005216 +#define CYDEV_PRTDSI_PRT3_BASE 0x40005218 +#define CYDEV_PRTDSI_PRT3_SIZE 0x00000007 +#define CYDEV_PRTDSI_PRT3_OUT_SEL0 0x40005218 +#define CYDEV_PRTDSI_PRT3_OUT_SEL1 0x40005219 +#define CYDEV_PRTDSI_PRT3_OE_SEL0 0x4000521a +#define CYDEV_PRTDSI_PRT3_OE_SEL1 0x4000521b +#define CYDEV_PRTDSI_PRT3_DBL_SYNC_IN 0x4000521c +#define CYDEV_PRTDSI_PRT3_SYNC_OUT 0x4000521d +#define CYDEV_PRTDSI_PRT3_CAPS_SEL 0x4000521e +#define CYDEV_PRTDSI_PRT4_BASE 0x40005220 +#define CYDEV_PRTDSI_PRT4_SIZE 0x00000007 +#define CYDEV_PRTDSI_PRT4_OUT_SEL0 0x40005220 +#define CYDEV_PRTDSI_PRT4_OUT_SEL1 0x40005221 +#define CYDEV_PRTDSI_PRT4_OE_SEL0 0x40005222 +#define CYDEV_PRTDSI_PRT4_OE_SEL1 0x40005223 +#define CYDEV_PRTDSI_PRT4_DBL_SYNC_IN 0x40005224 +#define CYDEV_PRTDSI_PRT4_SYNC_OUT 0x40005225 +#define CYDEV_PRTDSI_PRT4_CAPS_SEL 0x40005226 +#define CYDEV_PRTDSI_PRT5_BASE 0x40005228 +#define CYDEV_PRTDSI_PRT5_SIZE 0x00000007 +#define CYDEV_PRTDSI_PRT5_OUT_SEL0 0x40005228 +#define CYDEV_PRTDSI_PRT5_OUT_SEL1 0x40005229 +#define CYDEV_PRTDSI_PRT5_OE_SEL0 0x4000522a +#define CYDEV_PRTDSI_PRT5_OE_SEL1 0x4000522b +#define CYDEV_PRTDSI_PRT5_DBL_SYNC_IN 0x4000522c +#define CYDEV_PRTDSI_PRT5_SYNC_OUT 0x4000522d +#define CYDEV_PRTDSI_PRT5_CAPS_SEL 0x4000522e +#define CYDEV_PRTDSI_PRT6_BASE 0x40005230 +#define CYDEV_PRTDSI_PRT6_SIZE 0x00000007 +#define CYDEV_PRTDSI_PRT6_OUT_SEL0 0x40005230 +#define CYDEV_PRTDSI_PRT6_OUT_SEL1 0x40005231 +#define CYDEV_PRTDSI_PRT6_OE_SEL0 0x40005232 +#define CYDEV_PRTDSI_PRT6_OE_SEL1 0x40005233 +#define CYDEV_PRTDSI_PRT6_DBL_SYNC_IN 0x40005234 +#define CYDEV_PRTDSI_PRT6_SYNC_OUT 0x40005235 +#define CYDEV_PRTDSI_PRT6_CAPS_SEL 0x40005236 +#define CYDEV_PRTDSI_PRT12_BASE 0x40005260 +#define CYDEV_PRTDSI_PRT12_SIZE 0x00000006 +#define CYDEV_PRTDSI_PRT12_OUT_SEL0 0x40005260 +#define CYDEV_PRTDSI_PRT12_OUT_SEL1 0x40005261 +#define CYDEV_PRTDSI_PRT12_OE_SEL0 0x40005262 +#define CYDEV_PRTDSI_PRT12_OE_SEL1 0x40005263 +#define CYDEV_PRTDSI_PRT12_DBL_SYNC_IN 0x40005264 +#define CYDEV_PRTDSI_PRT12_SYNC_OUT 0x40005265 +#define CYDEV_PRTDSI_PRT15_BASE 0x40005278 +#define CYDEV_PRTDSI_PRT15_SIZE 0x00000007 +#define CYDEV_PRTDSI_PRT15_OUT_SEL0 0x40005278 +#define CYDEV_PRTDSI_PRT15_OUT_SEL1 0x40005279 +#define CYDEV_PRTDSI_PRT15_OE_SEL0 0x4000527a +#define CYDEV_PRTDSI_PRT15_OE_SEL1 0x4000527b +#define CYDEV_PRTDSI_PRT15_DBL_SYNC_IN 0x4000527c +#define CYDEV_PRTDSI_PRT15_SYNC_OUT 0x4000527d +#define CYDEV_PRTDSI_PRT15_CAPS_SEL 0x4000527e +#define CYDEV_EMIF_BASE 0x40005400 +#define CYDEV_EMIF_SIZE 0x00000007 +#define CYDEV_EMIF_NO_UDB 0x40005400 +#define CYDEV_EMIF_RP_WAIT_STATES 0x40005401 +#define CYDEV_EMIF_MEM_DWN 0x40005402 +#define CYDEV_EMIF_MEMCLK_DIV 0x40005403 +#define CYDEV_EMIF_CLOCK_EN 0x40005404 +#define CYDEV_EMIF_EM_TYPE 0x40005405 +#define CYDEV_EMIF_WP_WAIT_STATES 0x40005406 +#define CYDEV_ANAIF_BASE 0x40005800 +#define CYDEV_ANAIF_SIZE 0x000003a9 +#define CYDEV_ANAIF_CFG_BASE 0x40005800 +#define CYDEV_ANAIF_CFG_SIZE 0x0000010f +#define CYDEV_ANAIF_CFG_SC0_BASE 0x40005800 +#define CYDEV_ANAIF_CFG_SC0_SIZE 0x00000003 +#define CYDEV_ANAIF_CFG_SC0_CR0 0x40005800 +#define CYDEV_ANAIF_CFG_SC0_CR1 0x40005801 +#define CYDEV_ANAIF_CFG_SC0_CR2 0x40005802 +#define CYDEV_ANAIF_CFG_SC1_BASE 0x40005804 +#define CYDEV_ANAIF_CFG_SC1_SIZE 0x00000003 +#define CYDEV_ANAIF_CFG_SC1_CR0 0x40005804 +#define CYDEV_ANAIF_CFG_SC1_CR1 0x40005805 +#define CYDEV_ANAIF_CFG_SC1_CR2 0x40005806 +#define CYDEV_ANAIF_CFG_SC2_BASE 0x40005808 +#define CYDEV_ANAIF_CFG_SC2_SIZE 0x00000003 +#define CYDEV_ANAIF_CFG_SC2_CR0 0x40005808 +#define CYDEV_ANAIF_CFG_SC2_CR1 0x40005809 +#define CYDEV_ANAIF_CFG_SC2_CR2 0x4000580a +#define CYDEV_ANAIF_CFG_SC3_BASE 0x4000580c +#define CYDEV_ANAIF_CFG_SC3_SIZE 0x00000003 +#define CYDEV_ANAIF_CFG_SC3_CR0 0x4000580c +#define CYDEV_ANAIF_CFG_SC3_CR1 0x4000580d +#define CYDEV_ANAIF_CFG_SC3_CR2 0x4000580e +#define CYDEV_ANAIF_CFG_DAC0_BASE 0x40005820 +#define CYDEV_ANAIF_CFG_DAC0_SIZE 0x00000003 +#define CYDEV_ANAIF_CFG_DAC0_CR0 0x40005820 +#define CYDEV_ANAIF_CFG_DAC0_CR1 0x40005821 +#define CYDEV_ANAIF_CFG_DAC0_TST 0x40005822 +#define CYDEV_ANAIF_CFG_DAC1_BASE 0x40005824 +#define CYDEV_ANAIF_CFG_DAC1_SIZE 0x00000003 +#define CYDEV_ANAIF_CFG_DAC1_CR0 0x40005824 +#define CYDEV_ANAIF_CFG_DAC1_CR1 0x40005825 +#define CYDEV_ANAIF_CFG_DAC1_TST 0x40005826 +#define CYDEV_ANAIF_CFG_DAC2_BASE 0x40005828 +#define CYDEV_ANAIF_CFG_DAC2_SIZE 0x00000003 +#define CYDEV_ANAIF_CFG_DAC2_CR0 0x40005828 +#define CYDEV_ANAIF_CFG_DAC2_CR1 0x40005829 +#define CYDEV_ANAIF_CFG_DAC2_TST 0x4000582a +#define CYDEV_ANAIF_CFG_DAC3_BASE 0x4000582c +#define CYDEV_ANAIF_CFG_DAC3_SIZE 0x00000003 +#define CYDEV_ANAIF_CFG_DAC3_CR0 0x4000582c +#define CYDEV_ANAIF_CFG_DAC3_CR1 0x4000582d +#define CYDEV_ANAIF_CFG_DAC3_TST 0x4000582e +#define CYDEV_ANAIF_CFG_CMP0_BASE 0x40005840 +#define CYDEV_ANAIF_CFG_CMP0_SIZE 0x00000001 +#define CYDEV_ANAIF_CFG_CMP0_CR 0x40005840 +#define CYDEV_ANAIF_CFG_CMP1_BASE 0x40005841 +#define CYDEV_ANAIF_CFG_CMP1_SIZE 0x00000001 +#define CYDEV_ANAIF_CFG_CMP1_CR 0x40005841 +#define CYDEV_ANAIF_CFG_CMP2_BASE 0x40005842 +#define CYDEV_ANAIF_CFG_CMP2_SIZE 0x00000001 +#define CYDEV_ANAIF_CFG_CMP2_CR 0x40005842 +#define CYDEV_ANAIF_CFG_CMP3_BASE 0x40005843 +#define CYDEV_ANAIF_CFG_CMP3_SIZE 0x00000001 +#define CYDEV_ANAIF_CFG_CMP3_CR 0x40005843 +#define CYDEV_ANAIF_CFG_LUT0_BASE 0x40005848 +#define CYDEV_ANAIF_CFG_LUT0_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_LUT0_CR 0x40005848 +#define CYDEV_ANAIF_CFG_LUT0_MX 0x40005849 +#define CYDEV_ANAIF_CFG_LUT1_BASE 0x4000584a +#define CYDEV_ANAIF_CFG_LUT1_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_LUT1_CR 0x4000584a +#define CYDEV_ANAIF_CFG_LUT1_MX 0x4000584b +#define CYDEV_ANAIF_CFG_LUT2_BASE 0x4000584c +#define CYDEV_ANAIF_CFG_LUT2_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_LUT2_CR 0x4000584c +#define CYDEV_ANAIF_CFG_LUT2_MX 0x4000584d +#define CYDEV_ANAIF_CFG_LUT3_BASE 0x4000584e +#define CYDEV_ANAIF_CFG_LUT3_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_LUT3_CR 0x4000584e +#define CYDEV_ANAIF_CFG_LUT3_MX 0x4000584f +#define CYDEV_ANAIF_CFG_OPAMP0_BASE 0x40005858 +#define CYDEV_ANAIF_CFG_OPAMP0_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_OPAMP0_CR 0x40005858 +#define CYDEV_ANAIF_CFG_OPAMP0_RSVD 0x40005859 +#define CYDEV_ANAIF_CFG_OPAMP1_BASE 0x4000585a +#define CYDEV_ANAIF_CFG_OPAMP1_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_OPAMP1_CR 0x4000585a +#define CYDEV_ANAIF_CFG_OPAMP1_RSVD 0x4000585b +#define CYDEV_ANAIF_CFG_OPAMP2_BASE 0x4000585c +#define CYDEV_ANAIF_CFG_OPAMP2_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_OPAMP2_CR 0x4000585c +#define CYDEV_ANAIF_CFG_OPAMP2_RSVD 0x4000585d +#define CYDEV_ANAIF_CFG_OPAMP3_BASE 0x4000585e +#define CYDEV_ANAIF_CFG_OPAMP3_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_OPAMP3_CR 0x4000585e +#define CYDEV_ANAIF_CFG_OPAMP3_RSVD 0x4000585f +#define CYDEV_ANAIF_CFG_LCDDAC_BASE 0x40005868 +#define CYDEV_ANAIF_CFG_LCDDAC_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_LCDDAC_CR0 0x40005868 +#define CYDEV_ANAIF_CFG_LCDDAC_CR1 0x40005869 +#define CYDEV_ANAIF_CFG_LCDDRV_BASE 0x4000586a +#define CYDEV_ANAIF_CFG_LCDDRV_SIZE 0x00000001 +#define CYDEV_ANAIF_CFG_LCDDRV_CR 0x4000586a +#define CYDEV_ANAIF_CFG_LCDTMR_BASE 0x4000586b +#define CYDEV_ANAIF_CFG_LCDTMR_SIZE 0x00000001 +#define CYDEV_ANAIF_CFG_LCDTMR_CFG 0x4000586b +#define CYDEV_ANAIF_CFG_BG_BASE 0x4000586c +#define CYDEV_ANAIF_CFG_BG_SIZE 0x00000004 +#define CYDEV_ANAIF_CFG_BG_CR0 0x4000586c +#define CYDEV_ANAIF_CFG_BG_RSVD 0x4000586d +#define CYDEV_ANAIF_CFG_BG_DFT0 0x4000586e +#define CYDEV_ANAIF_CFG_BG_DFT1 0x4000586f +#define CYDEV_ANAIF_CFG_CAPSL_BASE 0x40005870 +#define CYDEV_ANAIF_CFG_CAPSL_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_CAPSL_CFG0 0x40005870 +#define CYDEV_ANAIF_CFG_CAPSL_CFG1 0x40005871 +#define CYDEV_ANAIF_CFG_CAPSR_BASE 0x40005872 +#define CYDEV_ANAIF_CFG_CAPSR_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_CAPSR_CFG0 0x40005872 +#define CYDEV_ANAIF_CFG_CAPSR_CFG1 0x40005873 +#define CYDEV_ANAIF_CFG_PUMP_BASE 0x40005876 +#define CYDEV_ANAIF_CFG_PUMP_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_PUMP_CR0 0x40005876 +#define CYDEV_ANAIF_CFG_PUMP_CR1 0x40005877 +#define CYDEV_ANAIF_CFG_LPF0_BASE 0x40005878 +#define CYDEV_ANAIF_CFG_LPF0_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_LPF0_CR0 0x40005878 +#define CYDEV_ANAIF_CFG_LPF0_RSVD 0x40005879 +#define CYDEV_ANAIF_CFG_LPF1_BASE 0x4000587a +#define CYDEV_ANAIF_CFG_LPF1_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_LPF1_CR0 0x4000587a +#define CYDEV_ANAIF_CFG_LPF1_RSVD 0x4000587b +#define CYDEV_ANAIF_CFG_MISC_BASE 0x4000587c +#define CYDEV_ANAIF_CFG_MISC_SIZE 0x00000001 +#define CYDEV_ANAIF_CFG_MISC_CR0 0x4000587c +#define CYDEV_ANAIF_CFG_DSM0_BASE 0x40005880 +#define CYDEV_ANAIF_CFG_DSM0_SIZE 0x00000020 +#define CYDEV_ANAIF_CFG_DSM0_CR0 0x40005880 +#define CYDEV_ANAIF_CFG_DSM0_CR1 0x40005881 +#define CYDEV_ANAIF_CFG_DSM0_CR2 0x40005882 +#define CYDEV_ANAIF_CFG_DSM0_CR3 0x40005883 +#define CYDEV_ANAIF_CFG_DSM0_CR4 0x40005884 +#define CYDEV_ANAIF_CFG_DSM0_CR5 0x40005885 +#define CYDEV_ANAIF_CFG_DSM0_CR6 0x40005886 +#define CYDEV_ANAIF_CFG_DSM0_CR7 0x40005887 +#define CYDEV_ANAIF_CFG_DSM0_CR8 0x40005888 +#define CYDEV_ANAIF_CFG_DSM0_CR9 0x40005889 +#define CYDEV_ANAIF_CFG_DSM0_CR10 0x4000588a +#define CYDEV_ANAIF_CFG_DSM0_CR11 0x4000588b +#define CYDEV_ANAIF_CFG_DSM0_CR12 0x4000588c +#define CYDEV_ANAIF_CFG_DSM0_CR13 0x4000588d +#define CYDEV_ANAIF_CFG_DSM0_CR14 0x4000588e +#define CYDEV_ANAIF_CFG_DSM0_CR15 0x4000588f +#define CYDEV_ANAIF_CFG_DSM0_CR16 0x40005890 +#define CYDEV_ANAIF_CFG_DSM0_CR17 0x40005891 +#define CYDEV_ANAIF_CFG_DSM0_REF0 0x40005892 +#define CYDEV_ANAIF_CFG_DSM0_REF1 0x40005893 +#define CYDEV_ANAIF_CFG_DSM0_REF2 0x40005894 +#define CYDEV_ANAIF_CFG_DSM0_REF3 0x40005895 +#define CYDEV_ANAIF_CFG_DSM0_DEM0 0x40005896 +#define CYDEV_ANAIF_CFG_DSM0_DEM1 0x40005897 +#define CYDEV_ANAIF_CFG_DSM0_TST0 0x40005898 +#define CYDEV_ANAIF_CFG_DSM0_TST1 0x40005899 +#define CYDEV_ANAIF_CFG_DSM0_BUF0 0x4000589a +#define CYDEV_ANAIF_CFG_DSM0_BUF1 0x4000589b +#define CYDEV_ANAIF_CFG_DSM0_BUF2 0x4000589c +#define CYDEV_ANAIF_CFG_DSM0_BUF3 0x4000589d +#define CYDEV_ANAIF_CFG_DSM0_MISC 0x4000589e +#define CYDEV_ANAIF_CFG_DSM0_RSVD1 0x4000589f +#define CYDEV_ANAIF_CFG_SAR0_BASE 0x40005900 +#define CYDEV_ANAIF_CFG_SAR0_SIZE 0x00000007 +#define CYDEV_ANAIF_CFG_SAR0_CSR0 0x40005900 +#define CYDEV_ANAIF_CFG_SAR0_CSR1 0x40005901 +#define CYDEV_ANAIF_CFG_SAR0_CSR2 0x40005902 +#define CYDEV_ANAIF_CFG_SAR0_CSR3 0x40005903 +#define CYDEV_ANAIF_CFG_SAR0_CSR4 0x40005904 +#define CYDEV_ANAIF_CFG_SAR0_CSR5 0x40005905 +#define CYDEV_ANAIF_CFG_SAR0_CSR6 0x40005906 +#define CYDEV_ANAIF_CFG_SAR1_BASE 0x40005908 +#define CYDEV_ANAIF_CFG_SAR1_SIZE 0x00000007 +#define CYDEV_ANAIF_CFG_SAR1_CSR0 0x40005908 +#define CYDEV_ANAIF_CFG_SAR1_CSR1 0x40005909 +#define CYDEV_ANAIF_CFG_SAR1_CSR2 0x4000590a +#define CYDEV_ANAIF_CFG_SAR1_CSR3 0x4000590b +#define CYDEV_ANAIF_CFG_SAR1_CSR4 0x4000590c +#define CYDEV_ANAIF_CFG_SAR1_CSR5 0x4000590d +#define CYDEV_ANAIF_CFG_SAR1_CSR6 0x4000590e +#define CYDEV_ANAIF_RT_BASE 0x40005a00 +#define CYDEV_ANAIF_RT_SIZE 0x00000162 +#define CYDEV_ANAIF_RT_SC0_BASE 0x40005a00 +#define CYDEV_ANAIF_RT_SC0_SIZE 0x0000000d +#define CYDEV_ANAIF_RT_SC0_SW0 0x40005a00 +#define CYDEV_ANAIF_RT_SC0_SW2 0x40005a02 +#define CYDEV_ANAIF_RT_SC0_SW3 0x40005a03 +#define CYDEV_ANAIF_RT_SC0_SW4 0x40005a04 +#define CYDEV_ANAIF_RT_SC0_SW6 0x40005a06 +#define CYDEV_ANAIF_RT_SC0_SW7 0x40005a07 +#define CYDEV_ANAIF_RT_SC0_SW8 0x40005a08 +#define CYDEV_ANAIF_RT_SC0_SW10 0x40005a0a +#define CYDEV_ANAIF_RT_SC0_CLK 0x40005a0b +#define CYDEV_ANAIF_RT_SC0_BST 0x40005a0c +#define CYDEV_ANAIF_RT_SC1_BASE 0x40005a10 +#define CYDEV_ANAIF_RT_SC1_SIZE 0x0000000d +#define CYDEV_ANAIF_RT_SC1_SW0 0x40005a10 +#define CYDEV_ANAIF_RT_SC1_SW2 0x40005a12 +#define CYDEV_ANAIF_RT_SC1_SW3 0x40005a13 +#define CYDEV_ANAIF_RT_SC1_SW4 0x40005a14 +#define CYDEV_ANAIF_RT_SC1_SW6 0x40005a16 +#define CYDEV_ANAIF_RT_SC1_SW7 0x40005a17 +#define CYDEV_ANAIF_RT_SC1_SW8 0x40005a18 +#define CYDEV_ANAIF_RT_SC1_SW10 0x40005a1a +#define CYDEV_ANAIF_RT_SC1_CLK 0x40005a1b +#define CYDEV_ANAIF_RT_SC1_BST 0x40005a1c +#define CYDEV_ANAIF_RT_SC2_BASE 0x40005a20 +#define CYDEV_ANAIF_RT_SC2_SIZE 0x0000000d +#define CYDEV_ANAIF_RT_SC2_SW0 0x40005a20 +#define CYDEV_ANAIF_RT_SC2_SW2 0x40005a22 +#define CYDEV_ANAIF_RT_SC2_SW3 0x40005a23 +#define CYDEV_ANAIF_RT_SC2_SW4 0x40005a24 +#define CYDEV_ANAIF_RT_SC2_SW6 0x40005a26 +#define CYDEV_ANAIF_RT_SC2_SW7 0x40005a27 +#define CYDEV_ANAIF_RT_SC2_SW8 0x40005a28 +#define CYDEV_ANAIF_RT_SC2_SW10 0x40005a2a +#define CYDEV_ANAIF_RT_SC2_CLK 0x40005a2b +#define CYDEV_ANAIF_RT_SC2_BST 0x40005a2c +#define CYDEV_ANAIF_RT_SC3_BASE 0x40005a30 +#define CYDEV_ANAIF_RT_SC3_SIZE 0x0000000d +#define CYDEV_ANAIF_RT_SC3_SW0 0x40005a30 +#define CYDEV_ANAIF_RT_SC3_SW2 0x40005a32 +#define CYDEV_ANAIF_RT_SC3_SW3 0x40005a33 +#define CYDEV_ANAIF_RT_SC3_SW4 0x40005a34 +#define CYDEV_ANAIF_RT_SC3_SW6 0x40005a36 +#define CYDEV_ANAIF_RT_SC3_SW7 0x40005a37 +#define CYDEV_ANAIF_RT_SC3_SW8 0x40005a38 +#define CYDEV_ANAIF_RT_SC3_SW10 0x40005a3a +#define CYDEV_ANAIF_RT_SC3_CLK 0x40005a3b +#define CYDEV_ANAIF_RT_SC3_BST 0x40005a3c +#define CYDEV_ANAIF_RT_DAC0_BASE 0x40005a80 +#define CYDEV_ANAIF_RT_DAC0_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_DAC0_SW0 0x40005a80 +#define CYDEV_ANAIF_RT_DAC0_SW2 0x40005a82 +#define CYDEV_ANAIF_RT_DAC0_SW3 0x40005a83 +#define CYDEV_ANAIF_RT_DAC0_SW4 0x40005a84 +#define CYDEV_ANAIF_RT_DAC0_STROBE 0x40005a87 +#define CYDEV_ANAIF_RT_DAC1_BASE 0x40005a88 +#define CYDEV_ANAIF_RT_DAC1_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_DAC1_SW0 0x40005a88 +#define CYDEV_ANAIF_RT_DAC1_SW2 0x40005a8a +#define CYDEV_ANAIF_RT_DAC1_SW3 0x40005a8b +#define CYDEV_ANAIF_RT_DAC1_SW4 0x40005a8c +#define CYDEV_ANAIF_RT_DAC1_STROBE 0x40005a8f +#define CYDEV_ANAIF_RT_DAC2_BASE 0x40005a90 +#define CYDEV_ANAIF_RT_DAC2_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_DAC2_SW0 0x40005a90 +#define CYDEV_ANAIF_RT_DAC2_SW2 0x40005a92 +#define CYDEV_ANAIF_RT_DAC2_SW3 0x40005a93 +#define CYDEV_ANAIF_RT_DAC2_SW4 0x40005a94 +#define CYDEV_ANAIF_RT_DAC2_STROBE 0x40005a97 +#define CYDEV_ANAIF_RT_DAC3_BASE 0x40005a98 +#define CYDEV_ANAIF_RT_DAC3_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_DAC3_SW0 0x40005a98 +#define CYDEV_ANAIF_RT_DAC3_SW2 0x40005a9a +#define CYDEV_ANAIF_RT_DAC3_SW3 0x40005a9b +#define CYDEV_ANAIF_RT_DAC3_SW4 0x40005a9c +#define CYDEV_ANAIF_RT_DAC3_STROBE 0x40005a9f +#define CYDEV_ANAIF_RT_CMP0_BASE 0x40005ac0 +#define CYDEV_ANAIF_RT_CMP0_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_CMP0_SW0 0x40005ac0 +#define CYDEV_ANAIF_RT_CMP0_SW2 0x40005ac2 +#define CYDEV_ANAIF_RT_CMP0_SW3 0x40005ac3 +#define CYDEV_ANAIF_RT_CMP0_SW4 0x40005ac4 +#define CYDEV_ANAIF_RT_CMP0_SW6 0x40005ac6 +#define CYDEV_ANAIF_RT_CMP0_CLK 0x40005ac7 +#define CYDEV_ANAIF_RT_CMP1_BASE 0x40005ac8 +#define CYDEV_ANAIF_RT_CMP1_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_CMP1_SW0 0x40005ac8 +#define CYDEV_ANAIF_RT_CMP1_SW2 0x40005aca +#define CYDEV_ANAIF_RT_CMP1_SW3 0x40005acb +#define CYDEV_ANAIF_RT_CMP1_SW4 0x40005acc +#define CYDEV_ANAIF_RT_CMP1_SW6 0x40005ace +#define CYDEV_ANAIF_RT_CMP1_CLK 0x40005acf +#define CYDEV_ANAIF_RT_CMP2_BASE 0x40005ad0 +#define CYDEV_ANAIF_RT_CMP2_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_CMP2_SW0 0x40005ad0 +#define CYDEV_ANAIF_RT_CMP2_SW2 0x40005ad2 +#define CYDEV_ANAIF_RT_CMP2_SW3 0x40005ad3 +#define CYDEV_ANAIF_RT_CMP2_SW4 0x40005ad4 +#define CYDEV_ANAIF_RT_CMP2_SW6 0x40005ad6 +#define CYDEV_ANAIF_RT_CMP2_CLK 0x40005ad7 +#define CYDEV_ANAIF_RT_CMP3_BASE 0x40005ad8 +#define CYDEV_ANAIF_RT_CMP3_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_CMP3_SW0 0x40005ad8 +#define CYDEV_ANAIF_RT_CMP3_SW2 0x40005ada +#define CYDEV_ANAIF_RT_CMP3_SW3 0x40005adb +#define CYDEV_ANAIF_RT_CMP3_SW4 0x40005adc +#define CYDEV_ANAIF_RT_CMP3_SW6 0x40005ade +#define CYDEV_ANAIF_RT_CMP3_CLK 0x40005adf +#define CYDEV_ANAIF_RT_DSM0_BASE 0x40005b00 +#define CYDEV_ANAIF_RT_DSM0_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_DSM0_SW0 0x40005b00 +#define CYDEV_ANAIF_RT_DSM0_SW2 0x40005b02 +#define CYDEV_ANAIF_RT_DSM0_SW3 0x40005b03 +#define CYDEV_ANAIF_RT_DSM0_SW4 0x40005b04 +#define CYDEV_ANAIF_RT_DSM0_SW6 0x40005b06 +#define CYDEV_ANAIF_RT_DSM0_CLK 0x40005b07 +#define CYDEV_ANAIF_RT_SAR0_BASE 0x40005b20 +#define CYDEV_ANAIF_RT_SAR0_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_SAR0_SW0 0x40005b20 +#define CYDEV_ANAIF_RT_SAR0_SW2 0x40005b22 +#define CYDEV_ANAIF_RT_SAR0_SW3 0x40005b23 +#define CYDEV_ANAIF_RT_SAR0_SW4 0x40005b24 +#define CYDEV_ANAIF_RT_SAR0_SW6 0x40005b26 +#define CYDEV_ANAIF_RT_SAR0_CLK 0x40005b27 +#define CYDEV_ANAIF_RT_SAR1_BASE 0x40005b28 +#define CYDEV_ANAIF_RT_SAR1_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_SAR1_SW0 0x40005b28 +#define CYDEV_ANAIF_RT_SAR1_SW2 0x40005b2a +#define CYDEV_ANAIF_RT_SAR1_SW3 0x40005b2b +#define CYDEV_ANAIF_RT_SAR1_SW4 0x40005b2c +#define CYDEV_ANAIF_RT_SAR1_SW6 0x40005b2e +#define CYDEV_ANAIF_RT_SAR1_CLK 0x40005b2f +#define CYDEV_ANAIF_RT_OPAMP0_BASE 0x40005b40 +#define CYDEV_ANAIF_RT_OPAMP0_SIZE 0x00000002 +#define CYDEV_ANAIF_RT_OPAMP0_MX 0x40005b40 +#define CYDEV_ANAIF_RT_OPAMP0_SW 0x40005b41 +#define CYDEV_ANAIF_RT_OPAMP1_BASE 0x40005b42 +#define CYDEV_ANAIF_RT_OPAMP1_SIZE 0x00000002 +#define CYDEV_ANAIF_RT_OPAMP1_MX 0x40005b42 +#define CYDEV_ANAIF_RT_OPAMP1_SW 0x40005b43 +#define CYDEV_ANAIF_RT_OPAMP2_BASE 0x40005b44 +#define CYDEV_ANAIF_RT_OPAMP2_SIZE 0x00000002 +#define CYDEV_ANAIF_RT_OPAMP2_MX 0x40005b44 +#define CYDEV_ANAIF_RT_OPAMP2_SW 0x40005b45 +#define CYDEV_ANAIF_RT_OPAMP3_BASE 0x40005b46 +#define CYDEV_ANAIF_RT_OPAMP3_SIZE 0x00000002 +#define CYDEV_ANAIF_RT_OPAMP3_MX 0x40005b46 +#define CYDEV_ANAIF_RT_OPAMP3_SW 0x40005b47 +#define CYDEV_ANAIF_RT_LCDDAC_BASE 0x40005b50 +#define CYDEV_ANAIF_RT_LCDDAC_SIZE 0x00000005 +#define CYDEV_ANAIF_RT_LCDDAC_SW0 0x40005b50 +#define CYDEV_ANAIF_RT_LCDDAC_SW1 0x40005b51 +#define CYDEV_ANAIF_RT_LCDDAC_SW2 0x40005b52 +#define CYDEV_ANAIF_RT_LCDDAC_SW3 0x40005b53 +#define CYDEV_ANAIF_RT_LCDDAC_SW4 0x40005b54 +#define CYDEV_ANAIF_RT_SC_BASE 0x40005b56 +#define CYDEV_ANAIF_RT_SC_SIZE 0x00000001 +#define CYDEV_ANAIF_RT_SC_MISC 0x40005b56 +#define CYDEV_ANAIF_RT_BUS_BASE 0x40005b58 +#define CYDEV_ANAIF_RT_BUS_SIZE 0x00000004 +#define CYDEV_ANAIF_RT_BUS_SW0 0x40005b58 +#define CYDEV_ANAIF_RT_BUS_SW2 0x40005b5a +#define CYDEV_ANAIF_RT_BUS_SW3 0x40005b5b +#define CYDEV_ANAIF_RT_DFT_BASE 0x40005b5c +#define CYDEV_ANAIF_RT_DFT_SIZE 0x00000006 +#define CYDEV_ANAIF_RT_DFT_CR0 0x40005b5c +#define CYDEV_ANAIF_RT_DFT_CR1 0x40005b5d +#define CYDEV_ANAIF_RT_DFT_CR2 0x40005b5e +#define CYDEV_ANAIF_RT_DFT_CR3 0x40005b5f +#define CYDEV_ANAIF_RT_DFT_CR4 0x40005b60 +#define CYDEV_ANAIF_RT_DFT_CR5 0x40005b61 +#define CYDEV_ANAIF_WRK_BASE 0x40005b80 +#define CYDEV_ANAIF_WRK_SIZE 0x00000029 +#define CYDEV_ANAIF_WRK_DAC0_BASE 0x40005b80 +#define CYDEV_ANAIF_WRK_DAC0_SIZE 0x00000001 +#define CYDEV_ANAIF_WRK_DAC0_D 0x40005b80 +#define CYDEV_ANAIF_WRK_DAC1_BASE 0x40005b81 +#define CYDEV_ANAIF_WRK_DAC1_SIZE 0x00000001 +#define CYDEV_ANAIF_WRK_DAC1_D 0x40005b81 +#define CYDEV_ANAIF_WRK_DAC2_BASE 0x40005b82 +#define CYDEV_ANAIF_WRK_DAC2_SIZE 0x00000001 +#define CYDEV_ANAIF_WRK_DAC2_D 0x40005b82 +#define CYDEV_ANAIF_WRK_DAC3_BASE 0x40005b83 +#define CYDEV_ANAIF_WRK_DAC3_SIZE 0x00000001 +#define CYDEV_ANAIF_WRK_DAC3_D 0x40005b83 +#define CYDEV_ANAIF_WRK_DSM0_BASE 0x40005b88 +#define CYDEV_ANAIF_WRK_DSM0_SIZE 0x00000002 +#define CYDEV_ANAIF_WRK_DSM0_OUT0 0x40005b88 +#define CYDEV_ANAIF_WRK_DSM0_OUT1 0x40005b89 +#define CYDEV_ANAIF_WRK_LUT_BASE 0x40005b90 +#define CYDEV_ANAIF_WRK_LUT_SIZE 0x00000005 +#define CYDEV_ANAIF_WRK_LUT_SR 0x40005b90 +#define CYDEV_ANAIF_WRK_LUT_WRK1 0x40005b91 +#define CYDEV_ANAIF_WRK_LUT_MSK 0x40005b92 +#define CYDEV_ANAIF_WRK_LUT_CLK 0x40005b93 +#define CYDEV_ANAIF_WRK_LUT_CPTR 0x40005b94 +#define CYDEV_ANAIF_WRK_CMP_BASE 0x40005b96 +#define CYDEV_ANAIF_WRK_CMP_SIZE 0x00000002 +#define CYDEV_ANAIF_WRK_CMP_WRK 0x40005b96 +#define CYDEV_ANAIF_WRK_CMP_TST 0x40005b97 +#define CYDEV_ANAIF_WRK_SC_BASE 0x40005b98 +#define CYDEV_ANAIF_WRK_SC_SIZE 0x00000005 +#define CYDEV_ANAIF_WRK_SC_SR 0x40005b98 +#define CYDEV_ANAIF_WRK_SC_WRK1 0x40005b99 +#define CYDEV_ANAIF_WRK_SC_MSK 0x40005b9a +#define CYDEV_ANAIF_WRK_SC_CMPINV 0x40005b9b +#define CYDEV_ANAIF_WRK_SC_CPTR 0x40005b9c +#define CYDEV_ANAIF_WRK_SAR0_BASE 0x40005ba0 +#define CYDEV_ANAIF_WRK_SAR0_SIZE 0x00000002 +#define CYDEV_ANAIF_WRK_SAR0_WRK0 0x40005ba0 +#define CYDEV_ANAIF_WRK_SAR0_WRK1 0x40005ba1 +#define CYDEV_ANAIF_WRK_SAR1_BASE 0x40005ba2 +#define CYDEV_ANAIF_WRK_SAR1_SIZE 0x00000002 +#define CYDEV_ANAIF_WRK_SAR1_WRK0 0x40005ba2 +#define CYDEV_ANAIF_WRK_SAR1_WRK1 0x40005ba3 +#define CYDEV_ANAIF_WRK_SARS_BASE 0x40005ba8 +#define CYDEV_ANAIF_WRK_SARS_SIZE 0x00000001 +#define CYDEV_ANAIF_WRK_SARS_SOF 0x40005ba8 +#define CYDEV_USB_BASE 0x40006000 +#define CYDEV_USB_SIZE 0x00000300 +#define CYDEV_USB_EP0_DR0 0x40006000 +#define CYDEV_USB_EP0_DR1 0x40006001 +#define CYDEV_USB_EP0_DR2 0x40006002 +#define CYDEV_USB_EP0_DR3 0x40006003 +#define CYDEV_USB_EP0_DR4 0x40006004 +#define CYDEV_USB_EP0_DR5 0x40006005 +#define CYDEV_USB_EP0_DR6 0x40006006 +#define CYDEV_USB_EP0_DR7 0x40006007 +#define CYDEV_USB_CR0 0x40006008 +#define CYDEV_USB_CR1 0x40006009 +#define CYDEV_USB_SIE_EP_INT_EN 0x4000600a +#define CYDEV_USB_SIE_EP_INT_SR 0x4000600b +#define CYDEV_USB_SIE_EP1_BASE 0x4000600c +#define CYDEV_USB_SIE_EP1_SIZE 0x00000003 +#define CYDEV_USB_SIE_EP1_CNT0 0x4000600c +#define CYDEV_USB_SIE_EP1_CNT1 0x4000600d +#define CYDEV_USB_SIE_EP1_CR0 0x4000600e +#define CYDEV_USB_USBIO_CR0 0x40006010 +#define CYDEV_USB_USBIO_CR1 0x40006012 +#define CYDEV_USB_DYN_RECONFIG 0x40006014 +#define CYDEV_USB_SOF0 0x40006018 +#define CYDEV_USB_SOF1 0x40006019 +#define CYDEV_USB_SIE_EP2_BASE 0x4000601c +#define CYDEV_USB_SIE_EP2_SIZE 0x00000003 +#define CYDEV_USB_SIE_EP2_CNT0 0x4000601c +#define CYDEV_USB_SIE_EP2_CNT1 0x4000601d +#define CYDEV_USB_SIE_EP2_CR0 0x4000601e +#define CYDEV_USB_EP0_CR 0x40006028 +#define CYDEV_USB_EP0_CNT 0x40006029 +#define CYDEV_USB_SIE_EP3_BASE 0x4000602c +#define CYDEV_USB_SIE_EP3_SIZE 0x00000003 +#define CYDEV_USB_SIE_EP3_CNT0 0x4000602c +#define CYDEV_USB_SIE_EP3_CNT1 0x4000602d +#define CYDEV_USB_SIE_EP3_CR0 0x4000602e +#define CYDEV_USB_SIE_EP4_BASE 0x4000603c +#define CYDEV_USB_SIE_EP4_SIZE 0x00000003 +#define CYDEV_USB_SIE_EP4_CNT0 0x4000603c +#define CYDEV_USB_SIE_EP4_CNT1 0x4000603d +#define CYDEV_USB_SIE_EP4_CR0 0x4000603e +#define CYDEV_USB_SIE_EP5_BASE 0x4000604c +#define CYDEV_USB_SIE_EP5_SIZE 0x00000003 +#define CYDEV_USB_SIE_EP5_CNT0 0x4000604c +#define CYDEV_USB_SIE_EP5_CNT1 0x4000604d +#define CYDEV_USB_SIE_EP5_CR0 0x4000604e +#define CYDEV_USB_SIE_EP6_BASE 0x4000605c +#define CYDEV_USB_SIE_EP6_SIZE 0x00000003 +#define CYDEV_USB_SIE_EP6_CNT0 0x4000605c +#define CYDEV_USB_SIE_EP6_CNT1 0x4000605d +#define CYDEV_USB_SIE_EP6_CR0 0x4000605e +#define CYDEV_USB_SIE_EP7_BASE 0x4000606c +#define CYDEV_USB_SIE_EP7_SIZE 0x00000003 +#define CYDEV_USB_SIE_EP7_CNT0 0x4000606c +#define CYDEV_USB_SIE_EP7_CNT1 0x4000606d +#define CYDEV_USB_SIE_EP7_CR0 0x4000606e +#define CYDEV_USB_SIE_EP8_BASE 0x4000607c +#define CYDEV_USB_SIE_EP8_SIZE 0x00000003 +#define CYDEV_USB_SIE_EP8_CNT0 0x4000607c +#define CYDEV_USB_SIE_EP8_CNT1 0x4000607d +#define CYDEV_USB_SIE_EP8_CR0 0x4000607e +#define CYDEV_USB_ARB_EP1_BASE 0x40006080 +#define CYDEV_USB_ARB_EP1_SIZE 0x00000003 +#define CYDEV_USB_ARB_EP1_CFG 0x40006080 +#define CYDEV_USB_ARB_EP1_INT_EN 0x40006081 +#define CYDEV_USB_ARB_EP1_SR 0x40006082 +#define CYDEV_USB_ARB_RW1_BASE 0x40006084 +#define CYDEV_USB_ARB_RW1_SIZE 0x00000005 +#define CYDEV_USB_ARB_RW1_WA 0x40006084 +#define CYDEV_USB_ARB_RW1_WA_MSB 0x40006085 +#define CYDEV_USB_ARB_RW1_RA 0x40006086 +#define CYDEV_USB_ARB_RW1_RA_MSB 0x40006087 +#define CYDEV_USB_ARB_RW1_DR 0x40006088 +#define CYDEV_USB_BUF_SIZE 0x4000608c +#define CYDEV_USB_EP_ACTIVE 0x4000608e +#define CYDEV_USB_EP_TYPE 0x4000608f +#define CYDEV_USB_ARB_EP2_BASE 0x40006090 +#define CYDEV_USB_ARB_EP2_SIZE 0x00000003 +#define CYDEV_USB_ARB_EP2_CFG 0x40006090 +#define CYDEV_USB_ARB_EP2_INT_EN 0x40006091 +#define CYDEV_USB_ARB_EP2_SR 0x40006092 +#define CYDEV_USB_ARB_RW2_BASE 0x40006094 +#define CYDEV_USB_ARB_RW2_SIZE 0x00000005 +#define CYDEV_USB_ARB_RW2_WA 0x40006094 +#define CYDEV_USB_ARB_RW2_WA_MSB 0x40006095 +#define CYDEV_USB_ARB_RW2_RA 0x40006096 +#define CYDEV_USB_ARB_RW2_RA_MSB 0x40006097 +#define CYDEV_USB_ARB_RW2_DR 0x40006098 +#define CYDEV_USB_ARB_CFG 0x4000609c +#define CYDEV_USB_USB_CLK_EN 0x4000609d +#define CYDEV_USB_ARB_INT_EN 0x4000609e +#define CYDEV_USB_ARB_INT_SR 0x4000609f +#define CYDEV_USB_ARB_EP3_BASE 0x400060a0 +#define CYDEV_USB_ARB_EP3_SIZE 0x00000003 +#define CYDEV_USB_ARB_EP3_CFG 0x400060a0 +#define CYDEV_USB_ARB_EP3_INT_EN 0x400060a1 +#define CYDEV_USB_ARB_EP3_SR 0x400060a2 +#define CYDEV_USB_ARB_RW3_BASE 0x400060a4 +#define CYDEV_USB_ARB_RW3_SIZE 0x00000005 +#define CYDEV_USB_ARB_RW3_WA 0x400060a4 +#define CYDEV_USB_ARB_RW3_WA_MSB 0x400060a5 +#define CYDEV_USB_ARB_RW3_RA 0x400060a6 +#define CYDEV_USB_ARB_RW3_RA_MSB 0x400060a7 +#define CYDEV_USB_ARB_RW3_DR 0x400060a8 +#define CYDEV_USB_CWA 0x400060ac +#define CYDEV_USB_CWA_MSB 0x400060ad +#define CYDEV_USB_ARB_EP4_BASE 0x400060b0 +#define CYDEV_USB_ARB_EP4_SIZE 0x00000003 +#define CYDEV_USB_ARB_EP4_CFG 0x400060b0 +#define CYDEV_USB_ARB_EP4_INT_EN 0x400060b1 +#define CYDEV_USB_ARB_EP4_SR 0x400060b2 +#define CYDEV_USB_ARB_RW4_BASE 0x400060b4 +#define CYDEV_USB_ARB_RW4_SIZE 0x00000005 +#define CYDEV_USB_ARB_RW4_WA 0x400060b4 +#define CYDEV_USB_ARB_RW4_WA_MSB 0x400060b5 +#define CYDEV_USB_ARB_RW4_RA 0x400060b6 +#define CYDEV_USB_ARB_RW4_RA_MSB 0x400060b7 +#define CYDEV_USB_ARB_RW4_DR 0x400060b8 +#define CYDEV_USB_DMA_THRES 0x400060bc +#define CYDEV_USB_DMA_THRES_MSB 0x400060bd +#define CYDEV_USB_ARB_EP5_BASE 0x400060c0 +#define CYDEV_USB_ARB_EP5_SIZE 0x00000003 +#define CYDEV_USB_ARB_EP5_CFG 0x400060c0 +#define CYDEV_USB_ARB_EP5_INT_EN 0x400060c1 +#define CYDEV_USB_ARB_EP5_SR 0x400060c2 +#define CYDEV_USB_ARB_RW5_BASE 0x400060c4 +#define CYDEV_USB_ARB_RW5_SIZE 0x00000005 +#define CYDEV_USB_ARB_RW5_WA 0x400060c4 +#define CYDEV_USB_ARB_RW5_WA_MSB 0x400060c5 +#define CYDEV_USB_ARB_RW5_RA 0x400060c6 +#define CYDEV_USB_ARB_RW5_RA_MSB 0x400060c7 +#define CYDEV_USB_ARB_RW5_DR 0x400060c8 +#define CYDEV_USB_BUS_RST_CNT 0x400060cc +#define CYDEV_USB_ARB_EP6_BASE 0x400060d0 +#define CYDEV_USB_ARB_EP6_SIZE 0x00000003 +#define CYDEV_USB_ARB_EP6_CFG 0x400060d0 +#define CYDEV_USB_ARB_EP6_INT_EN 0x400060d1 +#define CYDEV_USB_ARB_EP6_SR 0x400060d2 +#define CYDEV_USB_ARB_RW6_BASE 0x400060d4 +#define CYDEV_USB_ARB_RW6_SIZE 0x00000005 +#define CYDEV_USB_ARB_RW6_WA 0x400060d4 +#define CYDEV_USB_ARB_RW6_WA_MSB 0x400060d5 +#define CYDEV_USB_ARB_RW6_RA 0x400060d6 +#define CYDEV_USB_ARB_RW6_RA_MSB 0x400060d7 +#define CYDEV_USB_ARB_RW6_DR 0x400060d8 +#define CYDEV_USB_ARB_EP7_BASE 0x400060e0 +#define CYDEV_USB_ARB_EP7_SIZE 0x00000003 +#define CYDEV_USB_ARB_EP7_CFG 0x400060e0 +#define CYDEV_USB_ARB_EP7_INT_EN 0x400060e1 +#define CYDEV_USB_ARB_EP7_SR 0x400060e2 +#define CYDEV_USB_ARB_RW7_BASE 0x400060e4 +#define CYDEV_USB_ARB_RW7_SIZE 0x00000005 +#define CYDEV_USB_ARB_RW7_WA 0x400060e4 +#define CYDEV_USB_ARB_RW7_WA_MSB 0x400060e5 +#define CYDEV_USB_ARB_RW7_RA 0x400060e6 +#define CYDEV_USB_ARB_RW7_RA_MSB 0x400060e7 +#define CYDEV_USB_ARB_RW7_DR 0x400060e8 +#define CYDEV_USB_ARB_EP8_BASE 0x400060f0 +#define CYDEV_USB_ARB_EP8_SIZE 0x00000003 +#define CYDEV_USB_ARB_EP8_CFG 0x400060f0 +#define CYDEV_USB_ARB_EP8_INT_EN 0x400060f1 +#define CYDEV_USB_ARB_EP8_SR 0x400060f2 +#define CYDEV_USB_ARB_RW8_BASE 0x400060f4 +#define CYDEV_USB_ARB_RW8_SIZE 0x00000005 +#define CYDEV_USB_ARB_RW8_WA 0x400060f4 +#define CYDEV_USB_ARB_RW8_WA_MSB 0x400060f5 +#define CYDEV_USB_ARB_RW8_RA 0x400060f6 +#define CYDEV_USB_ARB_RW8_RA_MSB 0x400060f7 +#define CYDEV_USB_ARB_RW8_DR 0x400060f8 +#define CYDEV_USB_MEM_BASE 0x40006100 +#define CYDEV_USB_MEM_SIZE 0x00000200 +#define CYDEV_USB_MEM_DATA_MBASE 0x40006100 +#define CYDEV_USB_MEM_DATA_MSIZE 0x00000200 +#define CYDEV_UWRK_BASE 0x40006400 +#define CYDEV_UWRK_SIZE 0x00000b60 +#define CYDEV_UWRK_UWRK8_BASE 0x40006400 +#define CYDEV_UWRK_UWRK8_SIZE 0x000003b0 +#define CYDEV_UWRK_UWRK8_B0_BASE 0x40006400 +#define CYDEV_UWRK_UWRK8_B0_SIZE 0x000000b0 +#define CYDEV_UWRK_UWRK8_B0_UDB00_A0 0x40006400 +#define CYDEV_UWRK_UWRK8_B0_UDB01_A0 0x40006401 +#define CYDEV_UWRK_UWRK8_B0_UDB02_A0 0x40006402 +#define CYDEV_UWRK_UWRK8_B0_UDB03_A0 0x40006403 +#define CYDEV_UWRK_UWRK8_B0_UDB04_A0 0x40006404 +#define CYDEV_UWRK_UWRK8_B0_UDB05_A0 0x40006405 +#define CYDEV_UWRK_UWRK8_B0_UDB06_A0 0x40006406 +#define CYDEV_UWRK_UWRK8_B0_UDB07_A0 0x40006407 +#define CYDEV_UWRK_UWRK8_B0_UDB08_A0 0x40006408 +#define CYDEV_UWRK_UWRK8_B0_UDB09_A0 0x40006409 +#define CYDEV_UWRK_UWRK8_B0_UDB10_A0 0x4000640a +#define CYDEV_UWRK_UWRK8_B0_UDB11_A0 0x4000640b +#define CYDEV_UWRK_UWRK8_B0_UDB12_A0 0x4000640c +#define CYDEV_UWRK_UWRK8_B0_UDB13_A0 0x4000640d +#define CYDEV_UWRK_UWRK8_B0_UDB14_A0 0x4000640e +#define CYDEV_UWRK_UWRK8_B0_UDB15_A0 0x4000640f +#define CYDEV_UWRK_UWRK8_B0_UDB00_A1 0x40006410 +#define CYDEV_UWRK_UWRK8_B0_UDB01_A1 0x40006411 +#define CYDEV_UWRK_UWRK8_B0_UDB02_A1 0x40006412 +#define CYDEV_UWRK_UWRK8_B0_UDB03_A1 0x40006413 +#define CYDEV_UWRK_UWRK8_B0_UDB04_A1 0x40006414 +#define CYDEV_UWRK_UWRK8_B0_UDB05_A1 0x40006415 +#define CYDEV_UWRK_UWRK8_B0_UDB06_A1 0x40006416 +#define CYDEV_UWRK_UWRK8_B0_UDB07_A1 0x40006417 +#define CYDEV_UWRK_UWRK8_B0_UDB08_A1 0x40006418 +#define CYDEV_UWRK_UWRK8_B0_UDB09_A1 0x40006419 +#define CYDEV_UWRK_UWRK8_B0_UDB10_A1 0x4000641a +#define CYDEV_UWRK_UWRK8_B0_UDB11_A1 0x4000641b +#define CYDEV_UWRK_UWRK8_B0_UDB12_A1 0x4000641c +#define CYDEV_UWRK_UWRK8_B0_UDB13_A1 0x4000641d +#define CYDEV_UWRK_UWRK8_B0_UDB14_A1 0x4000641e +#define CYDEV_UWRK_UWRK8_B0_UDB15_A1 0x4000641f +#define CYDEV_UWRK_UWRK8_B0_UDB00_D0 0x40006420 +#define CYDEV_UWRK_UWRK8_B0_UDB01_D0 0x40006421 +#define CYDEV_UWRK_UWRK8_B0_UDB02_D0 0x40006422 +#define CYDEV_UWRK_UWRK8_B0_UDB03_D0 0x40006423 +#define CYDEV_UWRK_UWRK8_B0_UDB04_D0 0x40006424 +#define CYDEV_UWRK_UWRK8_B0_UDB05_D0 0x40006425 +#define CYDEV_UWRK_UWRK8_B0_UDB06_D0 0x40006426 +#define CYDEV_UWRK_UWRK8_B0_UDB07_D0 0x40006427 +#define CYDEV_UWRK_UWRK8_B0_UDB08_D0 0x40006428 +#define CYDEV_UWRK_UWRK8_B0_UDB09_D0 0x40006429 +#define CYDEV_UWRK_UWRK8_B0_UDB10_D0 0x4000642a +#define CYDEV_UWRK_UWRK8_B0_UDB11_D0 0x4000642b +#define CYDEV_UWRK_UWRK8_B0_UDB12_D0 0x4000642c +#define CYDEV_UWRK_UWRK8_B0_UDB13_D0 0x4000642d +#define CYDEV_UWRK_UWRK8_B0_UDB14_D0 0x4000642e +#define CYDEV_UWRK_UWRK8_B0_UDB15_D0 0x4000642f +#define CYDEV_UWRK_UWRK8_B0_UDB00_D1 0x40006430 +#define CYDEV_UWRK_UWRK8_B0_UDB01_D1 0x40006431 +#define CYDEV_UWRK_UWRK8_B0_UDB02_D1 0x40006432 +#define CYDEV_UWRK_UWRK8_B0_UDB03_D1 0x40006433 +#define CYDEV_UWRK_UWRK8_B0_UDB04_D1 0x40006434 +#define CYDEV_UWRK_UWRK8_B0_UDB05_D1 0x40006435 +#define CYDEV_UWRK_UWRK8_B0_UDB06_D1 0x40006436 +#define CYDEV_UWRK_UWRK8_B0_UDB07_D1 0x40006437 +#define CYDEV_UWRK_UWRK8_B0_UDB08_D1 0x40006438 +#define CYDEV_UWRK_UWRK8_B0_UDB09_D1 0x40006439 +#define CYDEV_UWRK_UWRK8_B0_UDB10_D1 0x4000643a +#define CYDEV_UWRK_UWRK8_B0_UDB11_D1 0x4000643b +#define CYDEV_UWRK_UWRK8_B0_UDB12_D1 0x4000643c +#define CYDEV_UWRK_UWRK8_B0_UDB13_D1 0x4000643d +#define CYDEV_UWRK_UWRK8_B0_UDB14_D1 0x4000643e +#define CYDEV_UWRK_UWRK8_B0_UDB15_D1 0x4000643f +#define CYDEV_UWRK_UWRK8_B0_UDB00_F0 0x40006440 +#define CYDEV_UWRK_UWRK8_B0_UDB01_F0 0x40006441 +#define CYDEV_UWRK_UWRK8_B0_UDB02_F0 0x40006442 +#define CYDEV_UWRK_UWRK8_B0_UDB03_F0 0x40006443 +#define CYDEV_UWRK_UWRK8_B0_UDB04_F0 0x40006444 +#define CYDEV_UWRK_UWRK8_B0_UDB05_F0 0x40006445 +#define CYDEV_UWRK_UWRK8_B0_UDB06_F0 0x40006446 +#define CYDEV_UWRK_UWRK8_B0_UDB07_F0 0x40006447 +#define CYDEV_UWRK_UWRK8_B0_UDB08_F0 0x40006448 +#define CYDEV_UWRK_UWRK8_B0_UDB09_F0 0x40006449 +#define CYDEV_UWRK_UWRK8_B0_UDB10_F0 0x4000644a +#define CYDEV_UWRK_UWRK8_B0_UDB11_F0 0x4000644b +#define CYDEV_UWRK_UWRK8_B0_UDB12_F0 0x4000644c +#define CYDEV_UWRK_UWRK8_B0_UDB13_F0 0x4000644d +#define CYDEV_UWRK_UWRK8_B0_UDB14_F0 0x4000644e +#define CYDEV_UWRK_UWRK8_B0_UDB15_F0 0x4000644f +#define CYDEV_UWRK_UWRK8_B0_UDB00_F1 0x40006450 +#define CYDEV_UWRK_UWRK8_B0_UDB01_F1 0x40006451 +#define CYDEV_UWRK_UWRK8_B0_UDB02_F1 0x40006452 +#define CYDEV_UWRK_UWRK8_B0_UDB03_F1 0x40006453 +#define CYDEV_UWRK_UWRK8_B0_UDB04_F1 0x40006454 +#define CYDEV_UWRK_UWRK8_B0_UDB05_F1 0x40006455 +#define CYDEV_UWRK_UWRK8_B0_UDB06_F1 0x40006456 +#define CYDEV_UWRK_UWRK8_B0_UDB07_F1 0x40006457 +#define CYDEV_UWRK_UWRK8_B0_UDB08_F1 0x40006458 +#define CYDEV_UWRK_UWRK8_B0_UDB09_F1 0x40006459 +#define CYDEV_UWRK_UWRK8_B0_UDB10_F1 0x4000645a +#define CYDEV_UWRK_UWRK8_B0_UDB11_F1 0x4000645b +#define CYDEV_UWRK_UWRK8_B0_UDB12_F1 0x4000645c +#define CYDEV_UWRK_UWRK8_B0_UDB13_F1 0x4000645d +#define CYDEV_UWRK_UWRK8_B0_UDB14_F1 0x4000645e +#define CYDEV_UWRK_UWRK8_B0_UDB15_F1 0x4000645f +#define CYDEV_UWRK_UWRK8_B0_UDB00_ST 0x40006460 +#define CYDEV_UWRK_UWRK8_B0_UDB01_ST 0x40006461 +#define CYDEV_UWRK_UWRK8_B0_UDB02_ST 0x40006462 +#define CYDEV_UWRK_UWRK8_B0_UDB03_ST 0x40006463 +#define CYDEV_UWRK_UWRK8_B0_UDB04_ST 0x40006464 +#define CYDEV_UWRK_UWRK8_B0_UDB05_ST 0x40006465 +#define CYDEV_UWRK_UWRK8_B0_UDB06_ST 0x40006466 +#define CYDEV_UWRK_UWRK8_B0_UDB07_ST 0x40006467 +#define CYDEV_UWRK_UWRK8_B0_UDB08_ST 0x40006468 +#define CYDEV_UWRK_UWRK8_B0_UDB09_ST 0x40006469 +#define CYDEV_UWRK_UWRK8_B0_UDB10_ST 0x4000646a +#define CYDEV_UWRK_UWRK8_B0_UDB11_ST 0x4000646b +#define CYDEV_UWRK_UWRK8_B0_UDB12_ST 0x4000646c +#define CYDEV_UWRK_UWRK8_B0_UDB13_ST 0x4000646d +#define CYDEV_UWRK_UWRK8_B0_UDB14_ST 0x4000646e +#define CYDEV_UWRK_UWRK8_B0_UDB15_ST 0x4000646f +#define CYDEV_UWRK_UWRK8_B0_UDB00_CTL 0x40006470 +#define CYDEV_UWRK_UWRK8_B0_UDB01_CTL 0x40006471 +#define CYDEV_UWRK_UWRK8_B0_UDB02_CTL 0x40006472 +#define CYDEV_UWRK_UWRK8_B0_UDB03_CTL 0x40006473 +#define CYDEV_UWRK_UWRK8_B0_UDB04_CTL 0x40006474 +#define CYDEV_UWRK_UWRK8_B0_UDB05_CTL 0x40006475 +#define CYDEV_UWRK_UWRK8_B0_UDB06_CTL 0x40006476 +#define CYDEV_UWRK_UWRK8_B0_UDB07_CTL 0x40006477 +#define CYDEV_UWRK_UWRK8_B0_UDB08_CTL 0x40006478 +#define CYDEV_UWRK_UWRK8_B0_UDB09_CTL 0x40006479 +#define CYDEV_UWRK_UWRK8_B0_UDB10_CTL 0x4000647a +#define CYDEV_UWRK_UWRK8_B0_UDB11_CTL 0x4000647b +#define CYDEV_UWRK_UWRK8_B0_UDB12_CTL 0x4000647c +#define CYDEV_UWRK_UWRK8_B0_UDB13_CTL 0x4000647d +#define CYDEV_UWRK_UWRK8_B0_UDB14_CTL 0x4000647e +#define CYDEV_UWRK_UWRK8_B0_UDB15_CTL 0x4000647f +#define CYDEV_UWRK_UWRK8_B0_UDB00_MSK 0x40006480 +#define CYDEV_UWRK_UWRK8_B0_UDB01_MSK 0x40006481 +#define CYDEV_UWRK_UWRK8_B0_UDB02_MSK 0x40006482 +#define CYDEV_UWRK_UWRK8_B0_UDB03_MSK 0x40006483 +#define CYDEV_UWRK_UWRK8_B0_UDB04_MSK 0x40006484 +#define CYDEV_UWRK_UWRK8_B0_UDB05_MSK 0x40006485 +#define CYDEV_UWRK_UWRK8_B0_UDB06_MSK 0x40006486 +#define CYDEV_UWRK_UWRK8_B0_UDB07_MSK 0x40006487 +#define CYDEV_UWRK_UWRK8_B0_UDB08_MSK 0x40006488 +#define CYDEV_UWRK_UWRK8_B0_UDB09_MSK 0x40006489 +#define CYDEV_UWRK_UWRK8_B0_UDB10_MSK 0x4000648a +#define CYDEV_UWRK_UWRK8_B0_UDB11_MSK 0x4000648b +#define CYDEV_UWRK_UWRK8_B0_UDB12_MSK 0x4000648c +#define CYDEV_UWRK_UWRK8_B0_UDB13_MSK 0x4000648d +#define CYDEV_UWRK_UWRK8_B0_UDB14_MSK 0x4000648e +#define CYDEV_UWRK_UWRK8_B0_UDB15_MSK 0x4000648f +#define CYDEV_UWRK_UWRK8_B0_UDB00_ACTL 0x40006490 +#define CYDEV_UWRK_UWRK8_B0_UDB01_ACTL 0x40006491 +#define CYDEV_UWRK_UWRK8_B0_UDB02_ACTL 0x40006492 +#define CYDEV_UWRK_UWRK8_B0_UDB03_ACTL 0x40006493 +#define CYDEV_UWRK_UWRK8_B0_UDB04_ACTL 0x40006494 +#define CYDEV_UWRK_UWRK8_B0_UDB05_ACTL 0x40006495 +#define CYDEV_UWRK_UWRK8_B0_UDB06_ACTL 0x40006496 +#define CYDEV_UWRK_UWRK8_B0_UDB07_ACTL 0x40006497 +#define CYDEV_UWRK_UWRK8_B0_UDB08_ACTL 0x40006498 +#define CYDEV_UWRK_UWRK8_B0_UDB09_ACTL 0x40006499 +#define CYDEV_UWRK_UWRK8_B0_UDB10_ACTL 0x4000649a +#define CYDEV_UWRK_UWRK8_B0_UDB11_ACTL 0x4000649b +#define CYDEV_UWRK_UWRK8_B0_UDB12_ACTL 0x4000649c +#define CYDEV_UWRK_UWRK8_B0_UDB13_ACTL 0x4000649d +#define CYDEV_UWRK_UWRK8_B0_UDB14_ACTL 0x4000649e +#define CYDEV_UWRK_UWRK8_B0_UDB15_ACTL 0x4000649f +#define CYDEV_UWRK_UWRK8_B0_UDB00_MC 0x400064a0 +#define CYDEV_UWRK_UWRK8_B0_UDB01_MC 0x400064a1 +#define CYDEV_UWRK_UWRK8_B0_UDB02_MC 0x400064a2 +#define CYDEV_UWRK_UWRK8_B0_UDB03_MC 0x400064a3 +#define CYDEV_UWRK_UWRK8_B0_UDB04_MC 0x400064a4 +#define CYDEV_UWRK_UWRK8_B0_UDB05_MC 0x400064a5 +#define CYDEV_UWRK_UWRK8_B0_UDB06_MC 0x400064a6 +#define CYDEV_UWRK_UWRK8_B0_UDB07_MC 0x400064a7 +#define CYDEV_UWRK_UWRK8_B0_UDB08_MC 0x400064a8 +#define CYDEV_UWRK_UWRK8_B0_UDB09_MC 0x400064a9 +#define CYDEV_UWRK_UWRK8_B0_UDB10_MC 0x400064aa +#define CYDEV_UWRK_UWRK8_B0_UDB11_MC 0x400064ab +#define CYDEV_UWRK_UWRK8_B0_UDB12_MC 0x400064ac +#define CYDEV_UWRK_UWRK8_B0_UDB13_MC 0x400064ad +#define CYDEV_UWRK_UWRK8_B0_UDB14_MC 0x400064ae +#define CYDEV_UWRK_UWRK8_B0_UDB15_MC 0x400064af +#define CYDEV_UWRK_UWRK8_B1_BASE 0x40006500 +#define CYDEV_UWRK_UWRK8_B1_SIZE 0x000000b0 +#define CYDEV_UWRK_UWRK8_B1_UDB04_A0 0x40006504 +#define CYDEV_UWRK_UWRK8_B1_UDB05_A0 0x40006505 +#define CYDEV_UWRK_UWRK8_B1_UDB06_A0 0x40006506 +#define CYDEV_UWRK_UWRK8_B1_UDB07_A0 0x40006507 +#define CYDEV_UWRK_UWRK8_B1_UDB08_A0 0x40006508 +#define CYDEV_UWRK_UWRK8_B1_UDB09_A0 0x40006509 +#define CYDEV_UWRK_UWRK8_B1_UDB10_A0 0x4000650a +#define CYDEV_UWRK_UWRK8_B1_UDB11_A0 0x4000650b +#define CYDEV_UWRK_UWRK8_B1_UDB04_A1 0x40006514 +#define CYDEV_UWRK_UWRK8_B1_UDB05_A1 0x40006515 +#define CYDEV_UWRK_UWRK8_B1_UDB06_A1 0x40006516 +#define CYDEV_UWRK_UWRK8_B1_UDB07_A1 0x40006517 +#define CYDEV_UWRK_UWRK8_B1_UDB08_A1 0x40006518 +#define CYDEV_UWRK_UWRK8_B1_UDB09_A1 0x40006519 +#define CYDEV_UWRK_UWRK8_B1_UDB10_A1 0x4000651a +#define CYDEV_UWRK_UWRK8_B1_UDB11_A1 0x4000651b +#define CYDEV_UWRK_UWRK8_B1_UDB04_D0 0x40006524 +#define CYDEV_UWRK_UWRK8_B1_UDB05_D0 0x40006525 +#define CYDEV_UWRK_UWRK8_B1_UDB06_D0 0x40006526 +#define CYDEV_UWRK_UWRK8_B1_UDB07_D0 0x40006527 +#define CYDEV_UWRK_UWRK8_B1_UDB08_D0 0x40006528 +#define CYDEV_UWRK_UWRK8_B1_UDB09_D0 0x40006529 +#define CYDEV_UWRK_UWRK8_B1_UDB10_D0 0x4000652a +#define CYDEV_UWRK_UWRK8_B1_UDB11_D0 0x4000652b +#define CYDEV_UWRK_UWRK8_B1_UDB04_D1 0x40006534 +#define CYDEV_UWRK_UWRK8_B1_UDB05_D1 0x40006535 +#define CYDEV_UWRK_UWRK8_B1_UDB06_D1 0x40006536 +#define CYDEV_UWRK_UWRK8_B1_UDB07_D1 0x40006537 +#define CYDEV_UWRK_UWRK8_B1_UDB08_D1 0x40006538 +#define CYDEV_UWRK_UWRK8_B1_UDB09_D1 0x40006539 +#define CYDEV_UWRK_UWRK8_B1_UDB10_D1 0x4000653a +#define CYDEV_UWRK_UWRK8_B1_UDB11_D1 0x4000653b +#define CYDEV_UWRK_UWRK8_B1_UDB04_F0 0x40006544 +#define CYDEV_UWRK_UWRK8_B1_UDB05_F0 0x40006545 +#define CYDEV_UWRK_UWRK8_B1_UDB06_F0 0x40006546 +#define CYDEV_UWRK_UWRK8_B1_UDB07_F0 0x40006547 +#define CYDEV_UWRK_UWRK8_B1_UDB08_F0 0x40006548 +#define CYDEV_UWRK_UWRK8_B1_UDB09_F0 0x40006549 +#define CYDEV_UWRK_UWRK8_B1_UDB10_F0 0x4000654a +#define CYDEV_UWRK_UWRK8_B1_UDB11_F0 0x4000654b +#define CYDEV_UWRK_UWRK8_B1_UDB04_F1 0x40006554 +#define CYDEV_UWRK_UWRK8_B1_UDB05_F1 0x40006555 +#define CYDEV_UWRK_UWRK8_B1_UDB06_F1 0x40006556 +#define CYDEV_UWRK_UWRK8_B1_UDB07_F1 0x40006557 +#define CYDEV_UWRK_UWRK8_B1_UDB08_F1 0x40006558 +#define CYDEV_UWRK_UWRK8_B1_UDB09_F1 0x40006559 +#define CYDEV_UWRK_UWRK8_B1_UDB10_F1 0x4000655a +#define CYDEV_UWRK_UWRK8_B1_UDB11_F1 0x4000655b +#define CYDEV_UWRK_UWRK8_B1_UDB04_ST 0x40006564 +#define CYDEV_UWRK_UWRK8_B1_UDB05_ST 0x40006565 +#define CYDEV_UWRK_UWRK8_B1_UDB06_ST 0x40006566 +#define CYDEV_UWRK_UWRK8_B1_UDB07_ST 0x40006567 +#define CYDEV_UWRK_UWRK8_B1_UDB08_ST 0x40006568 +#define CYDEV_UWRK_UWRK8_B1_UDB09_ST 0x40006569 +#define CYDEV_UWRK_UWRK8_B1_UDB10_ST 0x4000656a +#define CYDEV_UWRK_UWRK8_B1_UDB11_ST 0x4000656b +#define CYDEV_UWRK_UWRK8_B1_UDB04_CTL 0x40006574 +#define CYDEV_UWRK_UWRK8_B1_UDB05_CTL 0x40006575 +#define CYDEV_UWRK_UWRK8_B1_UDB06_CTL 0x40006576 +#define CYDEV_UWRK_UWRK8_B1_UDB07_CTL 0x40006577 +#define CYDEV_UWRK_UWRK8_B1_UDB08_CTL 0x40006578 +#define CYDEV_UWRK_UWRK8_B1_UDB09_CTL 0x40006579 +#define CYDEV_UWRK_UWRK8_B1_UDB10_CTL 0x4000657a +#define CYDEV_UWRK_UWRK8_B1_UDB11_CTL 0x4000657b +#define CYDEV_UWRK_UWRK8_B1_UDB04_MSK 0x40006584 +#define CYDEV_UWRK_UWRK8_B1_UDB05_MSK 0x40006585 +#define CYDEV_UWRK_UWRK8_B1_UDB06_MSK 0x40006586 +#define CYDEV_UWRK_UWRK8_B1_UDB07_MSK 0x40006587 +#define CYDEV_UWRK_UWRK8_B1_UDB08_MSK 0x40006588 +#define CYDEV_UWRK_UWRK8_B1_UDB09_MSK 0x40006589 +#define CYDEV_UWRK_UWRK8_B1_UDB10_MSK 0x4000658a +#define CYDEV_UWRK_UWRK8_B1_UDB11_MSK 0x4000658b +#define CYDEV_UWRK_UWRK8_B1_UDB04_ACTL 0x40006594 +#define CYDEV_UWRK_UWRK8_B1_UDB05_ACTL 0x40006595 +#define CYDEV_UWRK_UWRK8_B1_UDB06_ACTL 0x40006596 +#define CYDEV_UWRK_UWRK8_B1_UDB07_ACTL 0x40006597 +#define CYDEV_UWRK_UWRK8_B1_UDB08_ACTL 0x40006598 +#define CYDEV_UWRK_UWRK8_B1_UDB09_ACTL 0x40006599 +#define CYDEV_UWRK_UWRK8_B1_UDB10_ACTL 0x4000659a +#define CYDEV_UWRK_UWRK8_B1_UDB11_ACTL 0x4000659b +#define CYDEV_UWRK_UWRK8_B1_UDB04_MC 0x400065a4 +#define CYDEV_UWRK_UWRK8_B1_UDB05_MC 0x400065a5 +#define CYDEV_UWRK_UWRK8_B1_UDB06_MC 0x400065a6 +#define CYDEV_UWRK_UWRK8_B1_UDB07_MC 0x400065a7 +#define CYDEV_UWRK_UWRK8_B1_UDB08_MC 0x400065a8 +#define CYDEV_UWRK_UWRK8_B1_UDB09_MC 0x400065a9 +#define CYDEV_UWRK_UWRK8_B1_UDB10_MC 0x400065aa +#define CYDEV_UWRK_UWRK8_B1_UDB11_MC 0x400065ab +#define CYDEV_UWRK_UWRK16_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_SIZE 0x00000760 +#define CYDEV_UWRK_UWRK16_CAT_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_CAT_SIZE 0x00000760 +#define CYDEV_UWRK_UWRK16_CAT_B0_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_CAT_B0_SIZE 0x00000160 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1 0x40006800 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1 0x40006802 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1 0x40006804 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1 0x40006806 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1 0x40006808 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1 0x4000680a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1 0x4000680c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1 0x4000680e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1 0x40006810 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1 0x40006812 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1 0x40006814 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1 0x40006816 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1 0x40006818 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1 0x4000681a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1 0x4000681c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1 0x4000681e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1 0x40006840 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1 0x40006842 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1 0x40006844 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1 0x40006846 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1 0x40006848 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1 0x4000684a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1 0x4000684c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1 0x4000684e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1 0x40006850 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1 0x40006852 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1 0x40006854 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1 0x40006856 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1 0x40006858 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1 0x4000685a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1 0x4000685c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1 0x4000685e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1 0x40006880 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1 0x40006882 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1 0x40006884 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1 0x40006886 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1 0x40006888 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1 0x4000688a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1 0x4000688c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1 0x4000688e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1 0x40006890 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1 0x40006892 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1 0x40006894 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1 0x40006896 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1 0x40006898 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1 0x4000689a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1 0x4000689c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1 0x4000689e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL 0x400068c0 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL 0x400068c2 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL 0x400068c4 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL 0x400068c6 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL 0x400068c8 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL 0x400068ca +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL 0x400068cc +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL 0x400068ce +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL 0x400068d0 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL 0x400068d2 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL 0x400068d4 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL 0x400068d6 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL 0x400068d8 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL 0x400068da +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL 0x400068dc +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL 0x400068de +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL 0x40006900 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL 0x40006902 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL 0x40006904 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL 0x40006906 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL 0x40006908 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL 0x4000690a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL 0x4000690c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL 0x4000690e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL 0x40006910 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL 0x40006912 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL 0x40006914 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL 0x40006916 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL 0x40006918 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL 0x4000691a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL 0x4000691c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL 0x4000691e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00 0x40006940 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00 0x40006942 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00 0x40006944 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00 0x40006946 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00 0x40006948 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00 0x4000694a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00 0x4000694c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00 0x4000694e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00 0x40006950 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00 0x40006952 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00 0x40006954 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00 0x40006956 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00 0x40006958 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00 0x4000695a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00 0x4000695c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00 0x4000695e +#define CYDEV_UWRK_UWRK16_CAT_B1_BASE 0x40006a00 +#define CYDEV_UWRK_UWRK16_CAT_B1_SIZE 0x00000160 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1 0x40006a08 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1 0x40006a0a +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1 0x40006a0c +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1 0x40006a0e +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1 0x40006a10 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1 0x40006a12 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1 0x40006a14 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1 0x40006a16 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1 0x40006a48 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1 0x40006a4a +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1 0x40006a4c +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1 0x40006a4e +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1 0x40006a50 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1 0x40006a52 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1 0x40006a54 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1 0x40006a56 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1 0x40006a88 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1 0x40006a8a +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1 0x40006a8c +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1 0x40006a8e +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1 0x40006a90 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1 0x40006a92 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1 0x40006a94 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1 0x40006a96 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL 0x40006ac8 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL 0x40006aca +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL 0x40006acc +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL 0x40006ace +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL 0x40006ad0 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL 0x40006ad2 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL 0x40006ad4 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL 0x40006ad6 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL 0x40006b08 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL 0x40006b0a +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL 0x40006b0c +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL 0x40006b0e +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL 0x40006b10 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL 0x40006b12 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL 0x40006b14 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL 0x40006b16 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00 0x40006b48 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00 0x40006b4a +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00 0x40006b4c +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00 0x40006b4e +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00 0x40006b50 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00 0x40006b52 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00 0x40006b54 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00 0x40006b56 +#define CYDEV_UWRK_UWRK16_DEF_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_DEF_SIZE 0x0000075e +#define CYDEV_UWRK_UWRK16_DEF_B0_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_DEF_B0_SIZE 0x0000015e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0 0x40006800 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0 0x40006802 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0 0x40006804 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0 0x40006806 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0 0x40006808 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0 0x4000680a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0 0x4000680c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0 0x4000680e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0 0x40006810 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0 0x40006812 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0 0x40006814 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0 0x40006816 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0 0x40006818 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0 0x4000681a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0 0x4000681c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1 0x40006820 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1 0x40006822 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1 0x40006824 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1 0x40006826 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1 0x40006828 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1 0x4000682a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1 0x4000682c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1 0x4000682e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1 0x40006830 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1 0x40006832 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1 0x40006834 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1 0x40006836 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1 0x40006838 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1 0x4000683a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1 0x4000683c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0 0x40006840 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0 0x40006842 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0 0x40006844 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0 0x40006846 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0 0x40006848 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0 0x4000684a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0 0x4000684c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0 0x4000684e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0 0x40006850 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0 0x40006852 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0 0x40006854 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0 0x40006856 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0 0x40006858 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0 0x4000685a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0 0x4000685c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1 0x40006860 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1 0x40006862 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1 0x40006864 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1 0x40006866 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1 0x40006868 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1 0x4000686a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1 0x4000686c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1 0x4000686e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1 0x40006870 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1 0x40006872 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1 0x40006874 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1 0x40006876 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1 0x40006878 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1 0x4000687a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1 0x4000687c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0 0x40006880 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0 0x40006882 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0 0x40006884 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0 0x40006886 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0 0x40006888 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0 0x4000688a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0 0x4000688c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0 0x4000688e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0 0x40006890 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0 0x40006892 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0 0x40006894 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0 0x40006896 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0 0x40006898 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0 0x4000689a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0 0x4000689c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1 0x400068a0 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1 0x400068a2 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1 0x400068a4 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1 0x400068a6 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1 0x400068a8 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1 0x400068aa +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1 0x400068ac +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1 0x400068ae +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1 0x400068b0 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1 0x400068b2 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1 0x400068b4 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1 0x400068b6 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1 0x400068b8 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1 0x400068ba +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1 0x400068bc +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST 0x400068c0 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST 0x400068c2 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST 0x400068c4 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST 0x400068c6 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST 0x400068c8 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST 0x400068ca +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST 0x400068cc +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST 0x400068ce +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST 0x400068d0 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST 0x400068d2 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST 0x400068d4 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST 0x400068d6 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST 0x400068d8 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST 0x400068da +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST 0x400068dc +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL 0x400068e0 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL 0x400068e2 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL 0x400068e4 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL 0x400068e6 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL 0x400068e8 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL 0x400068ea +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL 0x400068ec +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL 0x400068ee +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL 0x400068f0 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL 0x400068f2 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL 0x400068f4 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL 0x400068f6 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL 0x400068f8 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL 0x400068fa +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL 0x400068fc +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK 0x40006900 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK 0x40006902 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK 0x40006904 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK 0x40006906 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK 0x40006908 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK 0x4000690a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK 0x4000690c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK 0x4000690e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK 0x40006910 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK 0x40006912 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK 0x40006914 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK 0x40006916 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK 0x40006918 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK 0x4000691a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK 0x4000691c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL 0x40006920 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL 0x40006922 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL 0x40006924 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL 0x40006926 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL 0x40006928 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL 0x4000692a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL 0x4000692c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL 0x4000692e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL 0x40006930 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL 0x40006932 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL 0x40006934 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL 0x40006936 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL 0x40006938 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL 0x4000693a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL 0x4000693c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC 0x40006940 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC 0x40006942 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC 0x40006944 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC 0x40006946 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC 0x40006948 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC 0x4000694a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC 0x4000694c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC 0x4000694e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC 0x40006950 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC 0x40006952 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC 0x40006954 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC 0x40006956 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC 0x40006958 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC 0x4000695a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC 0x4000695c +#define CYDEV_UWRK_UWRK16_DEF_B1_BASE 0x40006a00 +#define CYDEV_UWRK_UWRK16_DEF_B1_SIZE 0x0000015e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0 0x40006a08 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0 0x40006a0a +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0 0x40006a0c +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0 0x40006a0e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0 0x40006a10 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0 0x40006a12 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0 0x40006a14 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0 0x40006a16 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1 0x40006a28 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1 0x40006a2a +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1 0x40006a2c +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1 0x40006a2e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1 0x40006a30 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1 0x40006a32 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1 0x40006a34 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1 0x40006a36 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0 0x40006a48 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0 0x40006a4a +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0 0x40006a4c +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0 0x40006a4e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0 0x40006a50 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0 0x40006a52 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0 0x40006a54 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0 0x40006a56 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1 0x40006a68 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1 0x40006a6a +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1 0x40006a6c +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1 0x40006a6e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1 0x40006a70 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1 0x40006a72 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1 0x40006a74 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1 0x40006a76 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0 0x40006a88 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0 0x40006a8a +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0 0x40006a8c +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0 0x40006a8e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0 0x40006a90 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0 0x40006a92 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0 0x40006a94 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0 0x40006a96 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1 0x40006aa8 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1 0x40006aaa +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1 0x40006aac +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1 0x40006aae +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1 0x40006ab0 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1 0x40006ab2 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1 0x40006ab4 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1 0x40006ab6 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST 0x40006ac8 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST 0x40006aca +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST 0x40006acc +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST 0x40006ace +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST 0x40006ad0 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST 0x40006ad2 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST 0x40006ad4 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST 0x40006ad6 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL 0x40006ae8 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL 0x40006aea +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL 0x40006aec +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL 0x40006aee +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL 0x40006af0 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL 0x40006af2 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL 0x40006af4 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL 0x40006af6 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK 0x40006b08 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK 0x40006b0a +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK 0x40006b0c +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK 0x40006b0e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK 0x40006b10 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK 0x40006b12 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK 0x40006b14 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK 0x40006b16 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL 0x40006b28 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL 0x40006b2a +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL 0x40006b2c +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL 0x40006b2e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL 0x40006b30 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL 0x40006b32 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL 0x40006b34 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL 0x40006b36 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC 0x40006b48 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC 0x40006b4a +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC 0x40006b4c +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC 0x40006b4e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC 0x40006b50 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC 0x40006b52 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC 0x40006b54 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC 0x40006b56 +#define CYDEV_PHUB_BASE 0x40007000 +#define CYDEV_PHUB_SIZE 0x00000c00 +#define CYDEV_PHUB_CFG 0x40007000 +#define CYDEV_PHUB_ERR 0x40007004 +#define CYDEV_PHUB_ERR_ADR 0x40007008 +#define CYDEV_PHUB_CH0_BASE 0x40007010 +#define CYDEV_PHUB_CH0_SIZE 0x0000000c +#define CYDEV_PHUB_CH0_BASIC_CFG 0x40007010 +#define CYDEV_PHUB_CH0_ACTION 0x40007014 +#define CYDEV_PHUB_CH0_BASIC_STATUS 0x40007018 +#define CYDEV_PHUB_CH1_BASE 0x40007020 +#define CYDEV_PHUB_CH1_SIZE 0x0000000c +#define CYDEV_PHUB_CH1_BASIC_CFG 0x40007020 +#define CYDEV_PHUB_CH1_ACTION 0x40007024 +#define CYDEV_PHUB_CH1_BASIC_STATUS 0x40007028 +#define CYDEV_PHUB_CH2_BASE 0x40007030 +#define CYDEV_PHUB_CH2_SIZE 0x0000000c +#define CYDEV_PHUB_CH2_BASIC_CFG 0x40007030 +#define CYDEV_PHUB_CH2_ACTION 0x40007034 +#define CYDEV_PHUB_CH2_BASIC_STATUS 0x40007038 +#define CYDEV_PHUB_CH3_BASE 0x40007040 +#define CYDEV_PHUB_CH3_SIZE 0x0000000c +#define CYDEV_PHUB_CH3_BASIC_CFG 0x40007040 +#define CYDEV_PHUB_CH3_ACTION 0x40007044 +#define CYDEV_PHUB_CH3_BASIC_STATUS 0x40007048 +#define CYDEV_PHUB_CH4_BASE 0x40007050 +#define CYDEV_PHUB_CH4_SIZE 0x0000000c +#define CYDEV_PHUB_CH4_BASIC_CFG 0x40007050 +#define CYDEV_PHUB_CH4_ACTION 0x40007054 +#define CYDEV_PHUB_CH4_BASIC_STATUS 0x40007058 +#define CYDEV_PHUB_CH5_BASE 0x40007060 +#define CYDEV_PHUB_CH5_SIZE 0x0000000c +#define CYDEV_PHUB_CH5_BASIC_CFG 0x40007060 +#define CYDEV_PHUB_CH5_ACTION 0x40007064 +#define CYDEV_PHUB_CH5_BASIC_STATUS 0x40007068 +#define CYDEV_PHUB_CH6_BASE 0x40007070 +#define CYDEV_PHUB_CH6_SIZE 0x0000000c +#define CYDEV_PHUB_CH6_BASIC_CFG 0x40007070 +#define CYDEV_PHUB_CH6_ACTION 0x40007074 +#define CYDEV_PHUB_CH6_BASIC_STATUS 0x40007078 +#define CYDEV_PHUB_CH7_BASE 0x40007080 +#define CYDEV_PHUB_CH7_SIZE 0x0000000c +#define CYDEV_PHUB_CH7_BASIC_CFG 0x40007080 +#define CYDEV_PHUB_CH7_ACTION 0x40007084 +#define CYDEV_PHUB_CH7_BASIC_STATUS 0x40007088 +#define CYDEV_PHUB_CH8_BASE 0x40007090 +#define CYDEV_PHUB_CH8_SIZE 0x0000000c +#define CYDEV_PHUB_CH8_BASIC_CFG 0x40007090 +#define CYDEV_PHUB_CH8_ACTION 0x40007094 +#define CYDEV_PHUB_CH8_BASIC_STATUS 0x40007098 +#define CYDEV_PHUB_CH9_BASE 0x400070a0 +#define CYDEV_PHUB_CH9_SIZE 0x0000000c +#define CYDEV_PHUB_CH9_BASIC_CFG 0x400070a0 +#define CYDEV_PHUB_CH9_ACTION 0x400070a4 +#define CYDEV_PHUB_CH9_BASIC_STATUS 0x400070a8 +#define CYDEV_PHUB_CH10_BASE 0x400070b0 +#define CYDEV_PHUB_CH10_SIZE 0x0000000c +#define CYDEV_PHUB_CH10_BASIC_CFG 0x400070b0 +#define CYDEV_PHUB_CH10_ACTION 0x400070b4 +#define CYDEV_PHUB_CH10_BASIC_STATUS 0x400070b8 +#define CYDEV_PHUB_CH11_BASE 0x400070c0 +#define CYDEV_PHUB_CH11_SIZE 0x0000000c +#define CYDEV_PHUB_CH11_BASIC_CFG 0x400070c0 +#define CYDEV_PHUB_CH11_ACTION 0x400070c4 +#define CYDEV_PHUB_CH11_BASIC_STATUS 0x400070c8 +#define CYDEV_PHUB_CH12_BASE 0x400070d0 +#define CYDEV_PHUB_CH12_SIZE 0x0000000c +#define CYDEV_PHUB_CH12_BASIC_CFG 0x400070d0 +#define CYDEV_PHUB_CH12_ACTION 0x400070d4 +#define CYDEV_PHUB_CH12_BASIC_STATUS 0x400070d8 +#define CYDEV_PHUB_CH13_BASE 0x400070e0 +#define CYDEV_PHUB_CH13_SIZE 0x0000000c +#define CYDEV_PHUB_CH13_BASIC_CFG 0x400070e0 +#define CYDEV_PHUB_CH13_ACTION 0x400070e4 +#define CYDEV_PHUB_CH13_BASIC_STATUS 0x400070e8 +#define CYDEV_PHUB_CH14_BASE 0x400070f0 +#define CYDEV_PHUB_CH14_SIZE 0x0000000c +#define CYDEV_PHUB_CH14_BASIC_CFG 0x400070f0 +#define CYDEV_PHUB_CH14_ACTION 0x400070f4 +#define CYDEV_PHUB_CH14_BASIC_STATUS 0x400070f8 +#define CYDEV_PHUB_CH15_BASE 0x40007100 +#define CYDEV_PHUB_CH15_SIZE 0x0000000c +#define CYDEV_PHUB_CH15_BASIC_CFG 0x40007100 +#define CYDEV_PHUB_CH15_ACTION 0x40007104 +#define CYDEV_PHUB_CH15_BASIC_STATUS 0x40007108 +#define CYDEV_PHUB_CH16_BASE 0x40007110 +#define CYDEV_PHUB_CH16_SIZE 0x0000000c +#define CYDEV_PHUB_CH16_BASIC_CFG 0x40007110 +#define CYDEV_PHUB_CH16_ACTION 0x40007114 +#define CYDEV_PHUB_CH16_BASIC_STATUS 0x40007118 +#define CYDEV_PHUB_CH17_BASE 0x40007120 +#define CYDEV_PHUB_CH17_SIZE 0x0000000c +#define CYDEV_PHUB_CH17_BASIC_CFG 0x40007120 +#define CYDEV_PHUB_CH17_ACTION 0x40007124 +#define CYDEV_PHUB_CH17_BASIC_STATUS 0x40007128 +#define CYDEV_PHUB_CH18_BASE 0x40007130 +#define CYDEV_PHUB_CH18_SIZE 0x0000000c +#define CYDEV_PHUB_CH18_BASIC_CFG 0x40007130 +#define CYDEV_PHUB_CH18_ACTION 0x40007134 +#define CYDEV_PHUB_CH18_BASIC_STATUS 0x40007138 +#define CYDEV_PHUB_CH19_BASE 0x40007140 +#define CYDEV_PHUB_CH19_SIZE 0x0000000c +#define CYDEV_PHUB_CH19_BASIC_CFG 0x40007140 +#define CYDEV_PHUB_CH19_ACTION 0x40007144 +#define CYDEV_PHUB_CH19_BASIC_STATUS 0x40007148 +#define CYDEV_PHUB_CH20_BASE 0x40007150 +#define CYDEV_PHUB_CH20_SIZE 0x0000000c +#define CYDEV_PHUB_CH20_BASIC_CFG 0x40007150 +#define CYDEV_PHUB_CH20_ACTION 0x40007154 +#define CYDEV_PHUB_CH20_BASIC_STATUS 0x40007158 +#define CYDEV_PHUB_CH21_BASE 0x40007160 +#define CYDEV_PHUB_CH21_SIZE 0x0000000c +#define CYDEV_PHUB_CH21_BASIC_CFG 0x40007160 +#define CYDEV_PHUB_CH21_ACTION 0x40007164 +#define CYDEV_PHUB_CH21_BASIC_STATUS 0x40007168 +#define CYDEV_PHUB_CH22_BASE 0x40007170 +#define CYDEV_PHUB_CH22_SIZE 0x0000000c +#define CYDEV_PHUB_CH22_BASIC_CFG 0x40007170 +#define CYDEV_PHUB_CH22_ACTION 0x40007174 +#define CYDEV_PHUB_CH22_BASIC_STATUS 0x40007178 +#define CYDEV_PHUB_CH23_BASE 0x40007180 +#define CYDEV_PHUB_CH23_SIZE 0x0000000c +#define CYDEV_PHUB_CH23_BASIC_CFG 0x40007180 +#define CYDEV_PHUB_CH23_ACTION 0x40007184 +#define CYDEV_PHUB_CH23_BASIC_STATUS 0x40007188 +#define CYDEV_PHUB_CFGMEM0_BASE 0x40007600 +#define CYDEV_PHUB_CFGMEM0_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM0_CFG0 0x40007600 +#define CYDEV_PHUB_CFGMEM0_CFG1 0x40007604 +#define CYDEV_PHUB_CFGMEM1_BASE 0x40007608 +#define CYDEV_PHUB_CFGMEM1_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM1_CFG0 0x40007608 +#define CYDEV_PHUB_CFGMEM1_CFG1 0x4000760c +#define CYDEV_PHUB_CFGMEM2_BASE 0x40007610 +#define CYDEV_PHUB_CFGMEM2_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM2_CFG0 0x40007610 +#define CYDEV_PHUB_CFGMEM2_CFG1 0x40007614 +#define CYDEV_PHUB_CFGMEM3_BASE 0x40007618 +#define CYDEV_PHUB_CFGMEM3_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM3_CFG0 0x40007618 +#define CYDEV_PHUB_CFGMEM3_CFG1 0x4000761c +#define CYDEV_PHUB_CFGMEM4_BASE 0x40007620 +#define CYDEV_PHUB_CFGMEM4_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM4_CFG0 0x40007620 +#define CYDEV_PHUB_CFGMEM4_CFG1 0x40007624 +#define CYDEV_PHUB_CFGMEM5_BASE 0x40007628 +#define CYDEV_PHUB_CFGMEM5_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM5_CFG0 0x40007628 +#define CYDEV_PHUB_CFGMEM5_CFG1 0x4000762c +#define CYDEV_PHUB_CFGMEM6_BASE 0x40007630 +#define CYDEV_PHUB_CFGMEM6_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM6_CFG0 0x40007630 +#define CYDEV_PHUB_CFGMEM6_CFG1 0x40007634 +#define CYDEV_PHUB_CFGMEM7_BASE 0x40007638 +#define CYDEV_PHUB_CFGMEM7_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM7_CFG0 0x40007638 +#define CYDEV_PHUB_CFGMEM7_CFG1 0x4000763c +#define CYDEV_PHUB_CFGMEM8_BASE 0x40007640 +#define CYDEV_PHUB_CFGMEM8_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM8_CFG0 0x40007640 +#define CYDEV_PHUB_CFGMEM8_CFG1 0x40007644 +#define CYDEV_PHUB_CFGMEM9_BASE 0x40007648 +#define CYDEV_PHUB_CFGMEM9_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM9_CFG0 0x40007648 +#define CYDEV_PHUB_CFGMEM9_CFG1 0x4000764c +#define CYDEV_PHUB_CFGMEM10_BASE 0x40007650 +#define CYDEV_PHUB_CFGMEM10_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM10_CFG0 0x40007650 +#define CYDEV_PHUB_CFGMEM10_CFG1 0x40007654 +#define CYDEV_PHUB_CFGMEM11_BASE 0x40007658 +#define CYDEV_PHUB_CFGMEM11_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM11_CFG0 0x40007658 +#define CYDEV_PHUB_CFGMEM11_CFG1 0x4000765c +#define CYDEV_PHUB_CFGMEM12_BASE 0x40007660 +#define CYDEV_PHUB_CFGMEM12_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM12_CFG0 0x40007660 +#define CYDEV_PHUB_CFGMEM12_CFG1 0x40007664 +#define CYDEV_PHUB_CFGMEM13_BASE 0x40007668 +#define CYDEV_PHUB_CFGMEM13_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM13_CFG0 0x40007668 +#define CYDEV_PHUB_CFGMEM13_CFG1 0x4000766c +#define CYDEV_PHUB_CFGMEM14_BASE 0x40007670 +#define CYDEV_PHUB_CFGMEM14_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM14_CFG0 0x40007670 +#define CYDEV_PHUB_CFGMEM14_CFG1 0x40007674 +#define CYDEV_PHUB_CFGMEM15_BASE 0x40007678 +#define CYDEV_PHUB_CFGMEM15_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM15_CFG0 0x40007678 +#define CYDEV_PHUB_CFGMEM15_CFG1 0x4000767c +#define CYDEV_PHUB_CFGMEM16_BASE 0x40007680 +#define CYDEV_PHUB_CFGMEM16_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM16_CFG0 0x40007680 +#define CYDEV_PHUB_CFGMEM16_CFG1 0x40007684 +#define CYDEV_PHUB_CFGMEM17_BASE 0x40007688 +#define CYDEV_PHUB_CFGMEM17_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM17_CFG0 0x40007688 +#define CYDEV_PHUB_CFGMEM17_CFG1 0x4000768c +#define CYDEV_PHUB_CFGMEM18_BASE 0x40007690 +#define CYDEV_PHUB_CFGMEM18_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM18_CFG0 0x40007690 +#define CYDEV_PHUB_CFGMEM18_CFG1 0x40007694 +#define CYDEV_PHUB_CFGMEM19_BASE 0x40007698 +#define CYDEV_PHUB_CFGMEM19_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM19_CFG0 0x40007698 +#define CYDEV_PHUB_CFGMEM19_CFG1 0x4000769c +#define CYDEV_PHUB_CFGMEM20_BASE 0x400076a0 +#define CYDEV_PHUB_CFGMEM20_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM20_CFG0 0x400076a0 +#define CYDEV_PHUB_CFGMEM20_CFG1 0x400076a4 +#define CYDEV_PHUB_CFGMEM21_BASE 0x400076a8 +#define CYDEV_PHUB_CFGMEM21_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM21_CFG0 0x400076a8 +#define CYDEV_PHUB_CFGMEM21_CFG1 0x400076ac +#define CYDEV_PHUB_CFGMEM22_BASE 0x400076b0 +#define CYDEV_PHUB_CFGMEM22_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM22_CFG0 0x400076b0 +#define CYDEV_PHUB_CFGMEM22_CFG1 0x400076b4 +#define CYDEV_PHUB_CFGMEM23_BASE 0x400076b8 +#define CYDEV_PHUB_CFGMEM23_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM23_CFG0 0x400076b8 +#define CYDEV_PHUB_CFGMEM23_CFG1 0x400076bc +#define CYDEV_PHUB_TDMEM0_BASE 0x40007800 +#define CYDEV_PHUB_TDMEM0_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM0_ORIG_TD0 0x40007800 +#define CYDEV_PHUB_TDMEM0_ORIG_TD1 0x40007804 +#define CYDEV_PHUB_TDMEM1_BASE 0x40007808 +#define CYDEV_PHUB_TDMEM1_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM1_ORIG_TD0 0x40007808 +#define CYDEV_PHUB_TDMEM1_ORIG_TD1 0x4000780c +#define CYDEV_PHUB_TDMEM2_BASE 0x40007810 +#define CYDEV_PHUB_TDMEM2_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM2_ORIG_TD0 0x40007810 +#define CYDEV_PHUB_TDMEM2_ORIG_TD1 0x40007814 +#define CYDEV_PHUB_TDMEM3_BASE 0x40007818 +#define CYDEV_PHUB_TDMEM3_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM3_ORIG_TD0 0x40007818 +#define CYDEV_PHUB_TDMEM3_ORIG_TD1 0x4000781c +#define CYDEV_PHUB_TDMEM4_BASE 0x40007820 +#define CYDEV_PHUB_TDMEM4_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM4_ORIG_TD0 0x40007820 +#define CYDEV_PHUB_TDMEM4_ORIG_TD1 0x40007824 +#define CYDEV_PHUB_TDMEM5_BASE 0x40007828 +#define CYDEV_PHUB_TDMEM5_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM5_ORIG_TD0 0x40007828 +#define CYDEV_PHUB_TDMEM5_ORIG_TD1 0x4000782c +#define CYDEV_PHUB_TDMEM6_BASE 0x40007830 +#define CYDEV_PHUB_TDMEM6_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM6_ORIG_TD0 0x40007830 +#define CYDEV_PHUB_TDMEM6_ORIG_TD1 0x40007834 +#define CYDEV_PHUB_TDMEM7_BASE 0x40007838 +#define CYDEV_PHUB_TDMEM7_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM7_ORIG_TD0 0x40007838 +#define CYDEV_PHUB_TDMEM7_ORIG_TD1 0x4000783c +#define CYDEV_PHUB_TDMEM8_BASE 0x40007840 +#define CYDEV_PHUB_TDMEM8_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM8_ORIG_TD0 0x40007840 +#define CYDEV_PHUB_TDMEM8_ORIG_TD1 0x40007844 +#define CYDEV_PHUB_TDMEM9_BASE 0x40007848 +#define CYDEV_PHUB_TDMEM9_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM9_ORIG_TD0 0x40007848 +#define CYDEV_PHUB_TDMEM9_ORIG_TD1 0x4000784c +#define CYDEV_PHUB_TDMEM10_BASE 0x40007850 +#define CYDEV_PHUB_TDMEM10_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM10_ORIG_TD0 0x40007850 +#define CYDEV_PHUB_TDMEM10_ORIG_TD1 0x40007854 +#define CYDEV_PHUB_TDMEM11_BASE 0x40007858 +#define CYDEV_PHUB_TDMEM11_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM11_ORIG_TD0 0x40007858 +#define CYDEV_PHUB_TDMEM11_ORIG_TD1 0x4000785c +#define CYDEV_PHUB_TDMEM12_BASE 0x40007860 +#define CYDEV_PHUB_TDMEM12_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM12_ORIG_TD0 0x40007860 +#define CYDEV_PHUB_TDMEM12_ORIG_TD1 0x40007864 +#define CYDEV_PHUB_TDMEM13_BASE 0x40007868 +#define CYDEV_PHUB_TDMEM13_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM13_ORIG_TD0 0x40007868 +#define CYDEV_PHUB_TDMEM13_ORIG_TD1 0x4000786c +#define CYDEV_PHUB_TDMEM14_BASE 0x40007870 +#define CYDEV_PHUB_TDMEM14_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM14_ORIG_TD0 0x40007870 +#define CYDEV_PHUB_TDMEM14_ORIG_TD1 0x40007874 +#define CYDEV_PHUB_TDMEM15_BASE 0x40007878 +#define CYDEV_PHUB_TDMEM15_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM15_ORIG_TD0 0x40007878 +#define CYDEV_PHUB_TDMEM15_ORIG_TD1 0x4000787c +#define CYDEV_PHUB_TDMEM16_BASE 0x40007880 +#define CYDEV_PHUB_TDMEM16_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM16_ORIG_TD0 0x40007880 +#define CYDEV_PHUB_TDMEM16_ORIG_TD1 0x40007884 +#define CYDEV_PHUB_TDMEM17_BASE 0x40007888 +#define CYDEV_PHUB_TDMEM17_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM17_ORIG_TD0 0x40007888 +#define CYDEV_PHUB_TDMEM17_ORIG_TD1 0x4000788c +#define CYDEV_PHUB_TDMEM18_BASE 0x40007890 +#define CYDEV_PHUB_TDMEM18_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM18_ORIG_TD0 0x40007890 +#define CYDEV_PHUB_TDMEM18_ORIG_TD1 0x40007894 +#define CYDEV_PHUB_TDMEM19_BASE 0x40007898 +#define CYDEV_PHUB_TDMEM19_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM19_ORIG_TD0 0x40007898 +#define CYDEV_PHUB_TDMEM19_ORIG_TD1 0x4000789c +#define CYDEV_PHUB_TDMEM20_BASE 0x400078a0 +#define CYDEV_PHUB_TDMEM20_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM20_ORIG_TD0 0x400078a0 +#define CYDEV_PHUB_TDMEM20_ORIG_TD1 0x400078a4 +#define CYDEV_PHUB_TDMEM21_BASE 0x400078a8 +#define CYDEV_PHUB_TDMEM21_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM21_ORIG_TD0 0x400078a8 +#define CYDEV_PHUB_TDMEM21_ORIG_TD1 0x400078ac +#define CYDEV_PHUB_TDMEM22_BASE 0x400078b0 +#define CYDEV_PHUB_TDMEM22_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM22_ORIG_TD0 0x400078b0 +#define CYDEV_PHUB_TDMEM22_ORIG_TD1 0x400078b4 +#define CYDEV_PHUB_TDMEM23_BASE 0x400078b8 +#define CYDEV_PHUB_TDMEM23_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM23_ORIG_TD0 0x400078b8 +#define CYDEV_PHUB_TDMEM23_ORIG_TD1 0x400078bc +#define CYDEV_PHUB_TDMEM24_BASE 0x400078c0 +#define CYDEV_PHUB_TDMEM24_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM24_ORIG_TD0 0x400078c0 +#define CYDEV_PHUB_TDMEM24_ORIG_TD1 0x400078c4 +#define CYDEV_PHUB_TDMEM25_BASE 0x400078c8 +#define CYDEV_PHUB_TDMEM25_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM25_ORIG_TD0 0x400078c8 +#define CYDEV_PHUB_TDMEM25_ORIG_TD1 0x400078cc +#define CYDEV_PHUB_TDMEM26_BASE 0x400078d0 +#define CYDEV_PHUB_TDMEM26_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM26_ORIG_TD0 0x400078d0 +#define CYDEV_PHUB_TDMEM26_ORIG_TD1 0x400078d4 +#define CYDEV_PHUB_TDMEM27_BASE 0x400078d8 +#define CYDEV_PHUB_TDMEM27_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM27_ORIG_TD0 0x400078d8 +#define CYDEV_PHUB_TDMEM27_ORIG_TD1 0x400078dc +#define CYDEV_PHUB_TDMEM28_BASE 0x400078e0 +#define CYDEV_PHUB_TDMEM28_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM28_ORIG_TD0 0x400078e0 +#define CYDEV_PHUB_TDMEM28_ORIG_TD1 0x400078e4 +#define CYDEV_PHUB_TDMEM29_BASE 0x400078e8 +#define CYDEV_PHUB_TDMEM29_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM29_ORIG_TD0 0x400078e8 +#define CYDEV_PHUB_TDMEM29_ORIG_TD1 0x400078ec +#define CYDEV_PHUB_TDMEM30_BASE 0x400078f0 +#define CYDEV_PHUB_TDMEM30_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM30_ORIG_TD0 0x400078f0 +#define CYDEV_PHUB_TDMEM30_ORIG_TD1 0x400078f4 +#define CYDEV_PHUB_TDMEM31_BASE 0x400078f8 +#define CYDEV_PHUB_TDMEM31_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM31_ORIG_TD0 0x400078f8 +#define CYDEV_PHUB_TDMEM31_ORIG_TD1 0x400078fc +#define CYDEV_PHUB_TDMEM32_BASE 0x40007900 +#define CYDEV_PHUB_TDMEM32_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM32_ORIG_TD0 0x40007900 +#define CYDEV_PHUB_TDMEM32_ORIG_TD1 0x40007904 +#define CYDEV_PHUB_TDMEM33_BASE 0x40007908 +#define CYDEV_PHUB_TDMEM33_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM33_ORIG_TD0 0x40007908 +#define CYDEV_PHUB_TDMEM33_ORIG_TD1 0x4000790c +#define CYDEV_PHUB_TDMEM34_BASE 0x40007910 +#define CYDEV_PHUB_TDMEM34_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM34_ORIG_TD0 0x40007910 +#define CYDEV_PHUB_TDMEM34_ORIG_TD1 0x40007914 +#define CYDEV_PHUB_TDMEM35_BASE 0x40007918 +#define CYDEV_PHUB_TDMEM35_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM35_ORIG_TD0 0x40007918 +#define CYDEV_PHUB_TDMEM35_ORIG_TD1 0x4000791c +#define CYDEV_PHUB_TDMEM36_BASE 0x40007920 +#define CYDEV_PHUB_TDMEM36_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM36_ORIG_TD0 0x40007920 +#define CYDEV_PHUB_TDMEM36_ORIG_TD1 0x40007924 +#define CYDEV_PHUB_TDMEM37_BASE 0x40007928 +#define CYDEV_PHUB_TDMEM37_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM37_ORIG_TD0 0x40007928 +#define CYDEV_PHUB_TDMEM37_ORIG_TD1 0x4000792c +#define CYDEV_PHUB_TDMEM38_BASE 0x40007930 +#define CYDEV_PHUB_TDMEM38_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM38_ORIG_TD0 0x40007930 +#define CYDEV_PHUB_TDMEM38_ORIG_TD1 0x40007934 +#define CYDEV_PHUB_TDMEM39_BASE 0x40007938 +#define CYDEV_PHUB_TDMEM39_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM39_ORIG_TD0 0x40007938 +#define CYDEV_PHUB_TDMEM39_ORIG_TD1 0x4000793c +#define CYDEV_PHUB_TDMEM40_BASE 0x40007940 +#define CYDEV_PHUB_TDMEM40_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM40_ORIG_TD0 0x40007940 +#define CYDEV_PHUB_TDMEM40_ORIG_TD1 0x40007944 +#define CYDEV_PHUB_TDMEM41_BASE 0x40007948 +#define CYDEV_PHUB_TDMEM41_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM41_ORIG_TD0 0x40007948 +#define CYDEV_PHUB_TDMEM41_ORIG_TD1 0x4000794c +#define CYDEV_PHUB_TDMEM42_BASE 0x40007950 +#define CYDEV_PHUB_TDMEM42_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM42_ORIG_TD0 0x40007950 +#define CYDEV_PHUB_TDMEM42_ORIG_TD1 0x40007954 +#define CYDEV_PHUB_TDMEM43_BASE 0x40007958 +#define CYDEV_PHUB_TDMEM43_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM43_ORIG_TD0 0x40007958 +#define CYDEV_PHUB_TDMEM43_ORIG_TD1 0x4000795c +#define CYDEV_PHUB_TDMEM44_BASE 0x40007960 +#define CYDEV_PHUB_TDMEM44_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM44_ORIG_TD0 0x40007960 +#define CYDEV_PHUB_TDMEM44_ORIG_TD1 0x40007964 +#define CYDEV_PHUB_TDMEM45_BASE 0x40007968 +#define CYDEV_PHUB_TDMEM45_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM45_ORIG_TD0 0x40007968 +#define CYDEV_PHUB_TDMEM45_ORIG_TD1 0x4000796c +#define CYDEV_PHUB_TDMEM46_BASE 0x40007970 +#define CYDEV_PHUB_TDMEM46_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM46_ORIG_TD0 0x40007970 +#define CYDEV_PHUB_TDMEM46_ORIG_TD1 0x40007974 +#define CYDEV_PHUB_TDMEM47_BASE 0x40007978 +#define CYDEV_PHUB_TDMEM47_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM47_ORIG_TD0 0x40007978 +#define CYDEV_PHUB_TDMEM47_ORIG_TD1 0x4000797c +#define CYDEV_PHUB_TDMEM48_BASE 0x40007980 +#define CYDEV_PHUB_TDMEM48_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM48_ORIG_TD0 0x40007980 +#define CYDEV_PHUB_TDMEM48_ORIG_TD1 0x40007984 +#define CYDEV_PHUB_TDMEM49_BASE 0x40007988 +#define CYDEV_PHUB_TDMEM49_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM49_ORIG_TD0 0x40007988 +#define CYDEV_PHUB_TDMEM49_ORIG_TD1 0x4000798c +#define CYDEV_PHUB_TDMEM50_BASE 0x40007990 +#define CYDEV_PHUB_TDMEM50_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM50_ORIG_TD0 0x40007990 +#define CYDEV_PHUB_TDMEM50_ORIG_TD1 0x40007994 +#define CYDEV_PHUB_TDMEM51_BASE 0x40007998 +#define CYDEV_PHUB_TDMEM51_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM51_ORIG_TD0 0x40007998 +#define CYDEV_PHUB_TDMEM51_ORIG_TD1 0x4000799c +#define CYDEV_PHUB_TDMEM52_BASE 0x400079a0 +#define CYDEV_PHUB_TDMEM52_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM52_ORIG_TD0 0x400079a0 +#define CYDEV_PHUB_TDMEM52_ORIG_TD1 0x400079a4 +#define CYDEV_PHUB_TDMEM53_BASE 0x400079a8 +#define CYDEV_PHUB_TDMEM53_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM53_ORIG_TD0 0x400079a8 +#define CYDEV_PHUB_TDMEM53_ORIG_TD1 0x400079ac +#define CYDEV_PHUB_TDMEM54_BASE 0x400079b0 +#define CYDEV_PHUB_TDMEM54_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM54_ORIG_TD0 0x400079b0 +#define CYDEV_PHUB_TDMEM54_ORIG_TD1 0x400079b4 +#define CYDEV_PHUB_TDMEM55_BASE 0x400079b8 +#define CYDEV_PHUB_TDMEM55_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM55_ORIG_TD0 0x400079b8 +#define CYDEV_PHUB_TDMEM55_ORIG_TD1 0x400079bc +#define CYDEV_PHUB_TDMEM56_BASE 0x400079c0 +#define CYDEV_PHUB_TDMEM56_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM56_ORIG_TD0 0x400079c0 +#define CYDEV_PHUB_TDMEM56_ORIG_TD1 0x400079c4 +#define CYDEV_PHUB_TDMEM57_BASE 0x400079c8 +#define CYDEV_PHUB_TDMEM57_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM57_ORIG_TD0 0x400079c8 +#define CYDEV_PHUB_TDMEM57_ORIG_TD1 0x400079cc +#define CYDEV_PHUB_TDMEM58_BASE 0x400079d0 +#define CYDEV_PHUB_TDMEM58_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM58_ORIG_TD0 0x400079d0 +#define CYDEV_PHUB_TDMEM58_ORIG_TD1 0x400079d4 +#define CYDEV_PHUB_TDMEM59_BASE 0x400079d8 +#define CYDEV_PHUB_TDMEM59_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM59_ORIG_TD0 0x400079d8 +#define CYDEV_PHUB_TDMEM59_ORIG_TD1 0x400079dc +#define CYDEV_PHUB_TDMEM60_BASE 0x400079e0 +#define CYDEV_PHUB_TDMEM60_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM60_ORIG_TD0 0x400079e0 +#define CYDEV_PHUB_TDMEM60_ORIG_TD1 0x400079e4 +#define CYDEV_PHUB_TDMEM61_BASE 0x400079e8 +#define CYDEV_PHUB_TDMEM61_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM61_ORIG_TD0 0x400079e8 +#define CYDEV_PHUB_TDMEM61_ORIG_TD1 0x400079ec +#define CYDEV_PHUB_TDMEM62_BASE 0x400079f0 +#define CYDEV_PHUB_TDMEM62_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM62_ORIG_TD0 0x400079f0 +#define CYDEV_PHUB_TDMEM62_ORIG_TD1 0x400079f4 +#define CYDEV_PHUB_TDMEM63_BASE 0x400079f8 +#define CYDEV_PHUB_TDMEM63_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM63_ORIG_TD0 0x400079f8 +#define CYDEV_PHUB_TDMEM63_ORIG_TD1 0x400079fc +#define CYDEV_PHUB_TDMEM64_BASE 0x40007a00 +#define CYDEV_PHUB_TDMEM64_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM64_ORIG_TD0 0x40007a00 +#define CYDEV_PHUB_TDMEM64_ORIG_TD1 0x40007a04 +#define CYDEV_PHUB_TDMEM65_BASE 0x40007a08 +#define CYDEV_PHUB_TDMEM65_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM65_ORIG_TD0 0x40007a08 +#define CYDEV_PHUB_TDMEM65_ORIG_TD1 0x40007a0c +#define CYDEV_PHUB_TDMEM66_BASE 0x40007a10 +#define CYDEV_PHUB_TDMEM66_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM66_ORIG_TD0 0x40007a10 +#define CYDEV_PHUB_TDMEM66_ORIG_TD1 0x40007a14 +#define CYDEV_PHUB_TDMEM67_BASE 0x40007a18 +#define CYDEV_PHUB_TDMEM67_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM67_ORIG_TD0 0x40007a18 +#define CYDEV_PHUB_TDMEM67_ORIG_TD1 0x40007a1c +#define CYDEV_PHUB_TDMEM68_BASE 0x40007a20 +#define CYDEV_PHUB_TDMEM68_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM68_ORIG_TD0 0x40007a20 +#define CYDEV_PHUB_TDMEM68_ORIG_TD1 0x40007a24 +#define CYDEV_PHUB_TDMEM69_BASE 0x40007a28 +#define CYDEV_PHUB_TDMEM69_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM69_ORIG_TD0 0x40007a28 +#define CYDEV_PHUB_TDMEM69_ORIG_TD1 0x40007a2c +#define CYDEV_PHUB_TDMEM70_BASE 0x40007a30 +#define CYDEV_PHUB_TDMEM70_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM70_ORIG_TD0 0x40007a30 +#define CYDEV_PHUB_TDMEM70_ORIG_TD1 0x40007a34 +#define CYDEV_PHUB_TDMEM71_BASE 0x40007a38 +#define CYDEV_PHUB_TDMEM71_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM71_ORIG_TD0 0x40007a38 +#define CYDEV_PHUB_TDMEM71_ORIG_TD1 0x40007a3c +#define CYDEV_PHUB_TDMEM72_BASE 0x40007a40 +#define CYDEV_PHUB_TDMEM72_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM72_ORIG_TD0 0x40007a40 +#define CYDEV_PHUB_TDMEM72_ORIG_TD1 0x40007a44 +#define CYDEV_PHUB_TDMEM73_BASE 0x40007a48 +#define CYDEV_PHUB_TDMEM73_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM73_ORIG_TD0 0x40007a48 +#define CYDEV_PHUB_TDMEM73_ORIG_TD1 0x40007a4c +#define CYDEV_PHUB_TDMEM74_BASE 0x40007a50 +#define CYDEV_PHUB_TDMEM74_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM74_ORIG_TD0 0x40007a50 +#define CYDEV_PHUB_TDMEM74_ORIG_TD1 0x40007a54 +#define CYDEV_PHUB_TDMEM75_BASE 0x40007a58 +#define CYDEV_PHUB_TDMEM75_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM75_ORIG_TD0 0x40007a58 +#define CYDEV_PHUB_TDMEM75_ORIG_TD1 0x40007a5c +#define CYDEV_PHUB_TDMEM76_BASE 0x40007a60 +#define CYDEV_PHUB_TDMEM76_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM76_ORIG_TD0 0x40007a60 +#define CYDEV_PHUB_TDMEM76_ORIG_TD1 0x40007a64 +#define CYDEV_PHUB_TDMEM77_BASE 0x40007a68 +#define CYDEV_PHUB_TDMEM77_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM77_ORIG_TD0 0x40007a68 +#define CYDEV_PHUB_TDMEM77_ORIG_TD1 0x40007a6c +#define CYDEV_PHUB_TDMEM78_BASE 0x40007a70 +#define CYDEV_PHUB_TDMEM78_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM78_ORIG_TD0 0x40007a70 +#define CYDEV_PHUB_TDMEM78_ORIG_TD1 0x40007a74 +#define CYDEV_PHUB_TDMEM79_BASE 0x40007a78 +#define CYDEV_PHUB_TDMEM79_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM79_ORIG_TD0 0x40007a78 +#define CYDEV_PHUB_TDMEM79_ORIG_TD1 0x40007a7c +#define CYDEV_PHUB_TDMEM80_BASE 0x40007a80 +#define CYDEV_PHUB_TDMEM80_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM80_ORIG_TD0 0x40007a80 +#define CYDEV_PHUB_TDMEM80_ORIG_TD1 0x40007a84 +#define CYDEV_PHUB_TDMEM81_BASE 0x40007a88 +#define CYDEV_PHUB_TDMEM81_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM81_ORIG_TD0 0x40007a88 +#define CYDEV_PHUB_TDMEM81_ORIG_TD1 0x40007a8c +#define CYDEV_PHUB_TDMEM82_BASE 0x40007a90 +#define CYDEV_PHUB_TDMEM82_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM82_ORIG_TD0 0x40007a90 +#define CYDEV_PHUB_TDMEM82_ORIG_TD1 0x40007a94 +#define CYDEV_PHUB_TDMEM83_BASE 0x40007a98 +#define CYDEV_PHUB_TDMEM83_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM83_ORIG_TD0 0x40007a98 +#define CYDEV_PHUB_TDMEM83_ORIG_TD1 0x40007a9c +#define CYDEV_PHUB_TDMEM84_BASE 0x40007aa0 +#define CYDEV_PHUB_TDMEM84_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM84_ORIG_TD0 0x40007aa0 +#define CYDEV_PHUB_TDMEM84_ORIG_TD1 0x40007aa4 +#define CYDEV_PHUB_TDMEM85_BASE 0x40007aa8 +#define CYDEV_PHUB_TDMEM85_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM85_ORIG_TD0 0x40007aa8 +#define CYDEV_PHUB_TDMEM85_ORIG_TD1 0x40007aac +#define CYDEV_PHUB_TDMEM86_BASE 0x40007ab0 +#define CYDEV_PHUB_TDMEM86_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM86_ORIG_TD0 0x40007ab0 +#define CYDEV_PHUB_TDMEM86_ORIG_TD1 0x40007ab4 +#define CYDEV_PHUB_TDMEM87_BASE 0x40007ab8 +#define CYDEV_PHUB_TDMEM87_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM87_ORIG_TD0 0x40007ab8 +#define CYDEV_PHUB_TDMEM87_ORIG_TD1 0x40007abc +#define CYDEV_PHUB_TDMEM88_BASE 0x40007ac0 +#define CYDEV_PHUB_TDMEM88_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM88_ORIG_TD0 0x40007ac0 +#define CYDEV_PHUB_TDMEM88_ORIG_TD1 0x40007ac4 +#define CYDEV_PHUB_TDMEM89_BASE 0x40007ac8 +#define CYDEV_PHUB_TDMEM89_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM89_ORIG_TD0 0x40007ac8 +#define CYDEV_PHUB_TDMEM89_ORIG_TD1 0x40007acc +#define CYDEV_PHUB_TDMEM90_BASE 0x40007ad0 +#define CYDEV_PHUB_TDMEM90_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM90_ORIG_TD0 0x40007ad0 +#define CYDEV_PHUB_TDMEM90_ORIG_TD1 0x40007ad4 +#define CYDEV_PHUB_TDMEM91_BASE 0x40007ad8 +#define CYDEV_PHUB_TDMEM91_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM91_ORIG_TD0 0x40007ad8 +#define CYDEV_PHUB_TDMEM91_ORIG_TD1 0x40007adc +#define CYDEV_PHUB_TDMEM92_BASE 0x40007ae0 +#define CYDEV_PHUB_TDMEM92_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM92_ORIG_TD0 0x40007ae0 +#define CYDEV_PHUB_TDMEM92_ORIG_TD1 0x40007ae4 +#define CYDEV_PHUB_TDMEM93_BASE 0x40007ae8 +#define CYDEV_PHUB_TDMEM93_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM93_ORIG_TD0 0x40007ae8 +#define CYDEV_PHUB_TDMEM93_ORIG_TD1 0x40007aec +#define CYDEV_PHUB_TDMEM94_BASE 0x40007af0 +#define CYDEV_PHUB_TDMEM94_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM94_ORIG_TD0 0x40007af0 +#define CYDEV_PHUB_TDMEM94_ORIG_TD1 0x40007af4 +#define CYDEV_PHUB_TDMEM95_BASE 0x40007af8 +#define CYDEV_PHUB_TDMEM95_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM95_ORIG_TD0 0x40007af8 +#define CYDEV_PHUB_TDMEM95_ORIG_TD1 0x40007afc +#define CYDEV_PHUB_TDMEM96_BASE 0x40007b00 +#define CYDEV_PHUB_TDMEM96_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM96_ORIG_TD0 0x40007b00 +#define CYDEV_PHUB_TDMEM96_ORIG_TD1 0x40007b04 +#define CYDEV_PHUB_TDMEM97_BASE 0x40007b08 +#define CYDEV_PHUB_TDMEM97_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM97_ORIG_TD0 0x40007b08 +#define CYDEV_PHUB_TDMEM97_ORIG_TD1 0x40007b0c +#define CYDEV_PHUB_TDMEM98_BASE 0x40007b10 +#define CYDEV_PHUB_TDMEM98_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM98_ORIG_TD0 0x40007b10 +#define CYDEV_PHUB_TDMEM98_ORIG_TD1 0x40007b14 +#define CYDEV_PHUB_TDMEM99_BASE 0x40007b18 +#define CYDEV_PHUB_TDMEM99_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM99_ORIG_TD0 0x40007b18 +#define CYDEV_PHUB_TDMEM99_ORIG_TD1 0x40007b1c +#define CYDEV_PHUB_TDMEM100_BASE 0x40007b20 +#define CYDEV_PHUB_TDMEM100_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM100_ORIG_TD0 0x40007b20 +#define CYDEV_PHUB_TDMEM100_ORIG_TD1 0x40007b24 +#define CYDEV_PHUB_TDMEM101_BASE 0x40007b28 +#define CYDEV_PHUB_TDMEM101_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM101_ORIG_TD0 0x40007b28 +#define CYDEV_PHUB_TDMEM101_ORIG_TD1 0x40007b2c +#define CYDEV_PHUB_TDMEM102_BASE 0x40007b30 +#define CYDEV_PHUB_TDMEM102_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM102_ORIG_TD0 0x40007b30 +#define CYDEV_PHUB_TDMEM102_ORIG_TD1 0x40007b34 +#define CYDEV_PHUB_TDMEM103_BASE 0x40007b38 +#define CYDEV_PHUB_TDMEM103_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM103_ORIG_TD0 0x40007b38 +#define CYDEV_PHUB_TDMEM103_ORIG_TD1 0x40007b3c +#define CYDEV_PHUB_TDMEM104_BASE 0x40007b40 +#define CYDEV_PHUB_TDMEM104_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM104_ORIG_TD0 0x40007b40 +#define CYDEV_PHUB_TDMEM104_ORIG_TD1 0x40007b44 +#define CYDEV_PHUB_TDMEM105_BASE 0x40007b48 +#define CYDEV_PHUB_TDMEM105_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM105_ORIG_TD0 0x40007b48 +#define CYDEV_PHUB_TDMEM105_ORIG_TD1 0x40007b4c +#define CYDEV_PHUB_TDMEM106_BASE 0x40007b50 +#define CYDEV_PHUB_TDMEM106_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM106_ORIG_TD0 0x40007b50 +#define CYDEV_PHUB_TDMEM106_ORIG_TD1 0x40007b54 +#define CYDEV_PHUB_TDMEM107_BASE 0x40007b58 +#define CYDEV_PHUB_TDMEM107_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM107_ORIG_TD0 0x40007b58 +#define CYDEV_PHUB_TDMEM107_ORIG_TD1 0x40007b5c +#define CYDEV_PHUB_TDMEM108_BASE 0x40007b60 +#define CYDEV_PHUB_TDMEM108_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM108_ORIG_TD0 0x40007b60 +#define CYDEV_PHUB_TDMEM108_ORIG_TD1 0x40007b64 +#define CYDEV_PHUB_TDMEM109_BASE 0x40007b68 +#define CYDEV_PHUB_TDMEM109_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM109_ORIG_TD0 0x40007b68 +#define CYDEV_PHUB_TDMEM109_ORIG_TD1 0x40007b6c +#define CYDEV_PHUB_TDMEM110_BASE 0x40007b70 +#define CYDEV_PHUB_TDMEM110_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM110_ORIG_TD0 0x40007b70 +#define CYDEV_PHUB_TDMEM110_ORIG_TD1 0x40007b74 +#define CYDEV_PHUB_TDMEM111_BASE 0x40007b78 +#define CYDEV_PHUB_TDMEM111_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM111_ORIG_TD0 0x40007b78 +#define CYDEV_PHUB_TDMEM111_ORIG_TD1 0x40007b7c +#define CYDEV_PHUB_TDMEM112_BASE 0x40007b80 +#define CYDEV_PHUB_TDMEM112_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM112_ORIG_TD0 0x40007b80 +#define CYDEV_PHUB_TDMEM112_ORIG_TD1 0x40007b84 +#define CYDEV_PHUB_TDMEM113_BASE 0x40007b88 +#define CYDEV_PHUB_TDMEM113_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM113_ORIG_TD0 0x40007b88 +#define CYDEV_PHUB_TDMEM113_ORIG_TD1 0x40007b8c +#define CYDEV_PHUB_TDMEM114_BASE 0x40007b90 +#define CYDEV_PHUB_TDMEM114_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM114_ORIG_TD0 0x40007b90 +#define CYDEV_PHUB_TDMEM114_ORIG_TD1 0x40007b94 +#define CYDEV_PHUB_TDMEM115_BASE 0x40007b98 +#define CYDEV_PHUB_TDMEM115_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM115_ORIG_TD0 0x40007b98 +#define CYDEV_PHUB_TDMEM115_ORIG_TD1 0x40007b9c +#define CYDEV_PHUB_TDMEM116_BASE 0x40007ba0 +#define CYDEV_PHUB_TDMEM116_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM116_ORIG_TD0 0x40007ba0 +#define CYDEV_PHUB_TDMEM116_ORIG_TD1 0x40007ba4 +#define CYDEV_PHUB_TDMEM117_BASE 0x40007ba8 +#define CYDEV_PHUB_TDMEM117_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM117_ORIG_TD0 0x40007ba8 +#define CYDEV_PHUB_TDMEM117_ORIG_TD1 0x40007bac +#define CYDEV_PHUB_TDMEM118_BASE 0x40007bb0 +#define CYDEV_PHUB_TDMEM118_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM118_ORIG_TD0 0x40007bb0 +#define CYDEV_PHUB_TDMEM118_ORIG_TD1 0x40007bb4 +#define CYDEV_PHUB_TDMEM119_BASE 0x40007bb8 +#define CYDEV_PHUB_TDMEM119_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM119_ORIG_TD0 0x40007bb8 +#define CYDEV_PHUB_TDMEM119_ORIG_TD1 0x40007bbc +#define CYDEV_PHUB_TDMEM120_BASE 0x40007bc0 +#define CYDEV_PHUB_TDMEM120_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM120_ORIG_TD0 0x40007bc0 +#define CYDEV_PHUB_TDMEM120_ORIG_TD1 0x40007bc4 +#define CYDEV_PHUB_TDMEM121_BASE 0x40007bc8 +#define CYDEV_PHUB_TDMEM121_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM121_ORIG_TD0 0x40007bc8 +#define CYDEV_PHUB_TDMEM121_ORIG_TD1 0x40007bcc +#define CYDEV_PHUB_TDMEM122_BASE 0x40007bd0 +#define CYDEV_PHUB_TDMEM122_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM122_ORIG_TD0 0x40007bd0 +#define CYDEV_PHUB_TDMEM122_ORIG_TD1 0x40007bd4 +#define CYDEV_PHUB_TDMEM123_BASE 0x40007bd8 +#define CYDEV_PHUB_TDMEM123_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM123_ORIG_TD0 0x40007bd8 +#define CYDEV_PHUB_TDMEM123_ORIG_TD1 0x40007bdc +#define CYDEV_PHUB_TDMEM124_BASE 0x40007be0 +#define CYDEV_PHUB_TDMEM124_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM124_ORIG_TD0 0x40007be0 +#define CYDEV_PHUB_TDMEM124_ORIG_TD1 0x40007be4 +#define CYDEV_PHUB_TDMEM125_BASE 0x40007be8 +#define CYDEV_PHUB_TDMEM125_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM125_ORIG_TD0 0x40007be8 +#define CYDEV_PHUB_TDMEM125_ORIG_TD1 0x40007bec +#define CYDEV_PHUB_TDMEM126_BASE 0x40007bf0 +#define CYDEV_PHUB_TDMEM126_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM126_ORIG_TD0 0x40007bf0 +#define CYDEV_PHUB_TDMEM126_ORIG_TD1 0x40007bf4 +#define CYDEV_PHUB_TDMEM127_BASE 0x40007bf8 +#define CYDEV_PHUB_TDMEM127_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM127_ORIG_TD0 0x40007bf8 +#define CYDEV_PHUB_TDMEM127_ORIG_TD1 0x40007bfc +#define CYDEV_EE_BASE 0x40008000 +#define CYDEV_EE_SIZE 0x00000800 +#define CYDEV_EE_DATA_MBASE 0x40008000 +#define CYDEV_EE_DATA_MSIZE 0x00000800 +#define CYDEV_CAN0_BASE 0x4000a000 +#define CYDEV_CAN0_SIZE 0x000002a0 +#define CYDEV_CAN0_CSR_BASE 0x4000a000 +#define CYDEV_CAN0_CSR_SIZE 0x00000018 +#define CYDEV_CAN0_CSR_INT_SR 0x4000a000 +#define CYDEV_CAN0_CSR_INT_EN 0x4000a004 +#define CYDEV_CAN0_CSR_BUF_SR 0x4000a008 +#define CYDEV_CAN0_CSR_ERR_SR 0x4000a00c +#define CYDEV_CAN0_CSR_CMD 0x4000a010 +#define CYDEV_CAN0_CSR_CFG 0x4000a014 +#define CYDEV_CAN0_TX0_BASE 0x4000a020 +#define CYDEV_CAN0_TX0_SIZE 0x00000010 +#define CYDEV_CAN0_TX0_CMD 0x4000a020 +#define CYDEV_CAN0_TX0_ID 0x4000a024 +#define CYDEV_CAN0_TX0_DH 0x4000a028 +#define CYDEV_CAN0_TX0_DL 0x4000a02c +#define CYDEV_CAN0_TX1_BASE 0x4000a030 +#define CYDEV_CAN0_TX1_SIZE 0x00000010 +#define CYDEV_CAN0_TX1_CMD 0x4000a030 +#define CYDEV_CAN0_TX1_ID 0x4000a034 +#define CYDEV_CAN0_TX1_DH 0x4000a038 +#define CYDEV_CAN0_TX1_DL 0x4000a03c +#define CYDEV_CAN0_TX2_BASE 0x4000a040 +#define CYDEV_CAN0_TX2_SIZE 0x00000010 +#define CYDEV_CAN0_TX2_CMD 0x4000a040 +#define CYDEV_CAN0_TX2_ID 0x4000a044 +#define CYDEV_CAN0_TX2_DH 0x4000a048 +#define CYDEV_CAN0_TX2_DL 0x4000a04c +#define CYDEV_CAN0_TX3_BASE 0x4000a050 +#define CYDEV_CAN0_TX3_SIZE 0x00000010 +#define CYDEV_CAN0_TX3_CMD 0x4000a050 +#define CYDEV_CAN0_TX3_ID 0x4000a054 +#define CYDEV_CAN0_TX3_DH 0x4000a058 +#define CYDEV_CAN0_TX3_DL 0x4000a05c +#define CYDEV_CAN0_TX4_BASE 0x4000a060 +#define CYDEV_CAN0_TX4_SIZE 0x00000010 +#define CYDEV_CAN0_TX4_CMD 0x4000a060 +#define CYDEV_CAN0_TX4_ID 0x4000a064 +#define CYDEV_CAN0_TX4_DH 0x4000a068 +#define CYDEV_CAN0_TX4_DL 0x4000a06c +#define CYDEV_CAN0_TX5_BASE 0x4000a070 +#define CYDEV_CAN0_TX5_SIZE 0x00000010 +#define CYDEV_CAN0_TX5_CMD 0x4000a070 +#define CYDEV_CAN0_TX5_ID 0x4000a074 +#define CYDEV_CAN0_TX5_DH 0x4000a078 +#define CYDEV_CAN0_TX5_DL 0x4000a07c +#define CYDEV_CAN0_TX6_BASE 0x4000a080 +#define CYDEV_CAN0_TX6_SIZE 0x00000010 +#define CYDEV_CAN0_TX6_CMD 0x4000a080 +#define CYDEV_CAN0_TX6_ID 0x4000a084 +#define CYDEV_CAN0_TX6_DH 0x4000a088 +#define CYDEV_CAN0_TX6_DL 0x4000a08c +#define CYDEV_CAN0_TX7_BASE 0x4000a090 +#define CYDEV_CAN0_TX7_SIZE 0x00000010 +#define CYDEV_CAN0_TX7_CMD 0x4000a090 +#define CYDEV_CAN0_TX7_ID 0x4000a094 +#define CYDEV_CAN0_TX7_DH 0x4000a098 +#define CYDEV_CAN0_TX7_DL 0x4000a09c +#define CYDEV_CAN0_RX0_BASE 0x4000a0a0 +#define CYDEV_CAN0_RX0_SIZE 0x00000020 +#define CYDEV_CAN0_RX0_CMD 0x4000a0a0 +#define CYDEV_CAN0_RX0_ID 0x4000a0a4 +#define CYDEV_CAN0_RX0_DH 0x4000a0a8 +#define CYDEV_CAN0_RX0_DL 0x4000a0ac +#define CYDEV_CAN0_RX0_AMR 0x4000a0b0 +#define CYDEV_CAN0_RX0_ACR 0x4000a0b4 +#define CYDEV_CAN0_RX0_AMRD 0x4000a0b8 +#define CYDEV_CAN0_RX0_ACRD 0x4000a0bc +#define CYDEV_CAN0_RX1_BASE 0x4000a0c0 +#define CYDEV_CAN0_RX1_SIZE 0x00000020 +#define CYDEV_CAN0_RX1_CMD 0x4000a0c0 +#define CYDEV_CAN0_RX1_ID 0x4000a0c4 +#define CYDEV_CAN0_RX1_DH 0x4000a0c8 +#define CYDEV_CAN0_RX1_DL 0x4000a0cc +#define CYDEV_CAN0_RX1_AMR 0x4000a0d0 +#define CYDEV_CAN0_RX1_ACR 0x4000a0d4 +#define CYDEV_CAN0_RX1_AMRD 0x4000a0d8 +#define CYDEV_CAN0_RX1_ACRD 0x4000a0dc +#define CYDEV_CAN0_RX2_BASE 0x4000a0e0 +#define CYDEV_CAN0_RX2_SIZE 0x00000020 +#define CYDEV_CAN0_RX2_CMD 0x4000a0e0 +#define CYDEV_CAN0_RX2_ID 0x4000a0e4 +#define CYDEV_CAN0_RX2_DH 0x4000a0e8 +#define CYDEV_CAN0_RX2_DL 0x4000a0ec +#define CYDEV_CAN0_RX2_AMR 0x4000a0f0 +#define CYDEV_CAN0_RX2_ACR 0x4000a0f4 +#define CYDEV_CAN0_RX2_AMRD 0x4000a0f8 +#define CYDEV_CAN0_RX2_ACRD 0x4000a0fc +#define CYDEV_CAN0_RX3_BASE 0x4000a100 +#define CYDEV_CAN0_RX3_SIZE 0x00000020 +#define CYDEV_CAN0_RX3_CMD 0x4000a100 +#define CYDEV_CAN0_RX3_ID 0x4000a104 +#define CYDEV_CAN0_RX3_DH 0x4000a108 +#define CYDEV_CAN0_RX3_DL 0x4000a10c +#define CYDEV_CAN0_RX3_AMR 0x4000a110 +#define CYDEV_CAN0_RX3_ACR 0x4000a114 +#define CYDEV_CAN0_RX3_AMRD 0x4000a118 +#define CYDEV_CAN0_RX3_ACRD 0x4000a11c +#define CYDEV_CAN0_RX4_BASE 0x4000a120 +#define CYDEV_CAN0_RX4_SIZE 0x00000020 +#define CYDEV_CAN0_RX4_CMD 0x4000a120 +#define CYDEV_CAN0_RX4_ID 0x4000a124 +#define CYDEV_CAN0_RX4_DH 0x4000a128 +#define CYDEV_CAN0_RX4_DL 0x4000a12c +#define CYDEV_CAN0_RX4_AMR 0x4000a130 +#define CYDEV_CAN0_RX4_ACR 0x4000a134 +#define CYDEV_CAN0_RX4_AMRD 0x4000a138 +#define CYDEV_CAN0_RX4_ACRD 0x4000a13c +#define CYDEV_CAN0_RX5_BASE 0x4000a140 +#define CYDEV_CAN0_RX5_SIZE 0x00000020 +#define CYDEV_CAN0_RX5_CMD 0x4000a140 +#define CYDEV_CAN0_RX5_ID 0x4000a144 +#define CYDEV_CAN0_RX5_DH 0x4000a148 +#define CYDEV_CAN0_RX5_DL 0x4000a14c +#define CYDEV_CAN0_RX5_AMR 0x4000a150 +#define CYDEV_CAN0_RX5_ACR 0x4000a154 +#define CYDEV_CAN0_RX5_AMRD 0x4000a158 +#define CYDEV_CAN0_RX5_ACRD 0x4000a15c +#define CYDEV_CAN0_RX6_BASE 0x4000a160 +#define CYDEV_CAN0_RX6_SIZE 0x00000020 +#define CYDEV_CAN0_RX6_CMD 0x4000a160 +#define CYDEV_CAN0_RX6_ID 0x4000a164 +#define CYDEV_CAN0_RX6_DH 0x4000a168 +#define CYDEV_CAN0_RX6_DL 0x4000a16c +#define CYDEV_CAN0_RX6_AMR 0x4000a170 +#define CYDEV_CAN0_RX6_ACR 0x4000a174 +#define CYDEV_CAN0_RX6_AMRD 0x4000a178 +#define CYDEV_CAN0_RX6_ACRD 0x4000a17c +#define CYDEV_CAN0_RX7_BASE 0x4000a180 +#define CYDEV_CAN0_RX7_SIZE 0x00000020 +#define CYDEV_CAN0_RX7_CMD 0x4000a180 +#define CYDEV_CAN0_RX7_ID 0x4000a184 +#define CYDEV_CAN0_RX7_DH 0x4000a188 +#define CYDEV_CAN0_RX7_DL 0x4000a18c +#define CYDEV_CAN0_RX7_AMR 0x4000a190 +#define CYDEV_CAN0_RX7_ACR 0x4000a194 +#define CYDEV_CAN0_RX7_AMRD 0x4000a198 +#define CYDEV_CAN0_RX7_ACRD 0x4000a19c +#define CYDEV_CAN0_RX8_BASE 0x4000a1a0 +#define CYDEV_CAN0_RX8_SIZE 0x00000020 +#define CYDEV_CAN0_RX8_CMD 0x4000a1a0 +#define CYDEV_CAN0_RX8_ID 0x4000a1a4 +#define CYDEV_CAN0_RX8_DH 0x4000a1a8 +#define CYDEV_CAN0_RX8_DL 0x4000a1ac +#define CYDEV_CAN0_RX8_AMR 0x4000a1b0 +#define CYDEV_CAN0_RX8_ACR 0x4000a1b4 +#define CYDEV_CAN0_RX8_AMRD 0x4000a1b8 +#define CYDEV_CAN0_RX8_ACRD 0x4000a1bc +#define CYDEV_CAN0_RX9_BASE 0x4000a1c0 +#define CYDEV_CAN0_RX9_SIZE 0x00000020 +#define CYDEV_CAN0_RX9_CMD 0x4000a1c0 +#define CYDEV_CAN0_RX9_ID 0x4000a1c4 +#define CYDEV_CAN0_RX9_DH 0x4000a1c8 +#define CYDEV_CAN0_RX9_DL 0x4000a1cc +#define CYDEV_CAN0_RX9_AMR 0x4000a1d0 +#define CYDEV_CAN0_RX9_ACR 0x4000a1d4 +#define CYDEV_CAN0_RX9_AMRD 0x4000a1d8 +#define CYDEV_CAN0_RX9_ACRD 0x4000a1dc +#define CYDEV_CAN0_RX10_BASE 0x4000a1e0 +#define CYDEV_CAN0_RX10_SIZE 0x00000020 +#define CYDEV_CAN0_RX10_CMD 0x4000a1e0 +#define CYDEV_CAN0_RX10_ID 0x4000a1e4 +#define CYDEV_CAN0_RX10_DH 0x4000a1e8 +#define CYDEV_CAN0_RX10_DL 0x4000a1ec +#define CYDEV_CAN0_RX10_AMR 0x4000a1f0 +#define CYDEV_CAN0_RX10_ACR 0x4000a1f4 +#define CYDEV_CAN0_RX10_AMRD 0x4000a1f8 +#define CYDEV_CAN0_RX10_ACRD 0x4000a1fc +#define CYDEV_CAN0_RX11_BASE 0x4000a200 +#define CYDEV_CAN0_RX11_SIZE 0x00000020 +#define CYDEV_CAN0_RX11_CMD 0x4000a200 +#define CYDEV_CAN0_RX11_ID 0x4000a204 +#define CYDEV_CAN0_RX11_DH 0x4000a208 +#define CYDEV_CAN0_RX11_DL 0x4000a20c +#define CYDEV_CAN0_RX11_AMR 0x4000a210 +#define CYDEV_CAN0_RX11_ACR 0x4000a214 +#define CYDEV_CAN0_RX11_AMRD 0x4000a218 +#define CYDEV_CAN0_RX11_ACRD 0x4000a21c +#define CYDEV_CAN0_RX12_BASE 0x4000a220 +#define CYDEV_CAN0_RX12_SIZE 0x00000020 +#define CYDEV_CAN0_RX12_CMD 0x4000a220 +#define CYDEV_CAN0_RX12_ID 0x4000a224 +#define CYDEV_CAN0_RX12_DH 0x4000a228 +#define CYDEV_CAN0_RX12_DL 0x4000a22c +#define CYDEV_CAN0_RX12_AMR 0x4000a230 +#define CYDEV_CAN0_RX12_ACR 0x4000a234 +#define CYDEV_CAN0_RX12_AMRD 0x4000a238 +#define CYDEV_CAN0_RX12_ACRD 0x4000a23c +#define CYDEV_CAN0_RX13_BASE 0x4000a240 +#define CYDEV_CAN0_RX13_SIZE 0x00000020 +#define CYDEV_CAN0_RX13_CMD 0x4000a240 +#define CYDEV_CAN0_RX13_ID 0x4000a244 +#define CYDEV_CAN0_RX13_DH 0x4000a248 +#define CYDEV_CAN0_RX13_DL 0x4000a24c +#define CYDEV_CAN0_RX13_AMR 0x4000a250 +#define CYDEV_CAN0_RX13_ACR 0x4000a254 +#define CYDEV_CAN0_RX13_AMRD 0x4000a258 +#define CYDEV_CAN0_RX13_ACRD 0x4000a25c +#define CYDEV_CAN0_RX14_BASE 0x4000a260 +#define CYDEV_CAN0_RX14_SIZE 0x00000020 +#define CYDEV_CAN0_RX14_CMD 0x4000a260 +#define CYDEV_CAN0_RX14_ID 0x4000a264 +#define CYDEV_CAN0_RX14_DH 0x4000a268 +#define CYDEV_CAN0_RX14_DL 0x4000a26c +#define CYDEV_CAN0_RX14_AMR 0x4000a270 +#define CYDEV_CAN0_RX14_ACR 0x4000a274 +#define CYDEV_CAN0_RX14_AMRD 0x4000a278 +#define CYDEV_CAN0_RX14_ACRD 0x4000a27c +#define CYDEV_CAN0_RX15_BASE 0x4000a280 +#define CYDEV_CAN0_RX15_SIZE 0x00000020 +#define CYDEV_CAN0_RX15_CMD 0x4000a280 +#define CYDEV_CAN0_RX15_ID 0x4000a284 +#define CYDEV_CAN0_RX15_DH 0x4000a288 +#define CYDEV_CAN0_RX15_DL 0x4000a28c +#define CYDEV_CAN0_RX15_AMR 0x4000a290 +#define CYDEV_CAN0_RX15_ACR 0x4000a294 +#define CYDEV_CAN0_RX15_AMRD 0x4000a298 +#define CYDEV_CAN0_RX15_ACRD 0x4000a29c +#define CYDEV_DFB0_BASE 0x4000c000 +#define CYDEV_DFB0_SIZE 0x000007b5 +#define CYDEV_DFB0_DPA_SRAM_BASE 0x4000c000 +#define CYDEV_DFB0_DPA_SRAM_SIZE 0x00000200 +#define CYDEV_DFB0_DPA_SRAM_DATA_MBASE 0x4000c000 +#define CYDEV_DFB0_DPA_SRAM_DATA_MSIZE 0x00000200 +#define CYDEV_DFB0_DPB_SRAM_BASE 0x4000c200 +#define CYDEV_DFB0_DPB_SRAM_SIZE 0x00000200 +#define CYDEV_DFB0_DPB_SRAM_DATA_MBASE 0x4000c200 +#define CYDEV_DFB0_DPB_SRAM_DATA_MSIZE 0x00000200 +#define CYDEV_DFB0_CSA_SRAM_BASE 0x4000c400 +#define CYDEV_DFB0_CSA_SRAM_SIZE 0x00000100 +#define CYDEV_DFB0_CSA_SRAM_DATA_MBASE 0x4000c400 +#define CYDEV_DFB0_CSA_SRAM_DATA_MSIZE 0x00000100 +#define CYDEV_DFB0_CSB_SRAM_BASE 0x4000c500 +#define CYDEV_DFB0_CSB_SRAM_SIZE 0x00000100 +#define CYDEV_DFB0_CSB_SRAM_DATA_MBASE 0x4000c500 +#define CYDEV_DFB0_CSB_SRAM_DATA_MSIZE 0x00000100 +#define CYDEV_DFB0_FSM_SRAM_BASE 0x4000c600 +#define CYDEV_DFB0_FSM_SRAM_SIZE 0x00000100 +#define CYDEV_DFB0_FSM_SRAM_DATA_MBASE 0x4000c600 +#define CYDEV_DFB0_FSM_SRAM_DATA_MSIZE 0x00000100 +#define CYDEV_DFB0_ACU_SRAM_BASE 0x4000c700 +#define CYDEV_DFB0_ACU_SRAM_SIZE 0x00000040 +#define CYDEV_DFB0_ACU_SRAM_DATA_MBASE 0x4000c700 +#define CYDEV_DFB0_ACU_SRAM_DATA_MSIZE 0x00000040 +#define CYDEV_DFB0_CR 0x4000c780 +#define CYDEV_DFB0_SR 0x4000c784 +#define CYDEV_DFB0_RAM_EN 0x4000c788 +#define CYDEV_DFB0_RAM_DIR 0x4000c78c +#define CYDEV_DFB0_SEMA 0x4000c790 +#define CYDEV_DFB0_DSI_CTRL 0x4000c794 +#define CYDEV_DFB0_INT_CTRL 0x4000c798 +#define CYDEV_DFB0_DMA_CTRL 0x4000c79c +#define CYDEV_DFB0_STAGEA 0x4000c7a0 +#define CYDEV_DFB0_STAGEAM 0x4000c7a1 +#define CYDEV_DFB0_STAGEAH 0x4000c7a2 +#define CYDEV_DFB0_STAGEB 0x4000c7a4 +#define CYDEV_DFB0_STAGEBM 0x4000c7a5 +#define CYDEV_DFB0_STAGEBH 0x4000c7a6 +#define CYDEV_DFB0_HOLDA 0x4000c7a8 +#define CYDEV_DFB0_HOLDAM 0x4000c7a9 +#define CYDEV_DFB0_HOLDAH 0x4000c7aa +#define CYDEV_DFB0_HOLDAS 0x4000c7ab +#define CYDEV_DFB0_HOLDB 0x4000c7ac +#define CYDEV_DFB0_HOLDBM 0x4000c7ad +#define CYDEV_DFB0_HOLDBH 0x4000c7ae +#define CYDEV_DFB0_HOLDBS 0x4000c7af +#define CYDEV_DFB0_COHER 0x4000c7b0 +#define CYDEV_DFB0_DALIGN 0x4000c7b4 +#define CYDEV_UCFG_BASE 0x40010000 +#define CYDEV_UCFG_SIZE 0x00005040 +#define CYDEV_UCFG_B0_BASE 0x40010000 +#define CYDEV_UCFG_B0_SIZE 0x00000fef +#define CYDEV_UCFG_B0_P0_BASE 0x40010000 +#define CYDEV_UCFG_B0_P0_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P0_U0_BASE 0x40010000 +#define CYDEV_UCFG_B0_P0_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT0 0x40010000 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT1 0x40010004 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT2 0x40010008 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT3 0x4001000c +#define CYDEV_UCFG_B0_P0_U0_PLD_IT4 0x40010010 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT5 0x40010014 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT6 0x40010018 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT7 0x4001001c +#define CYDEV_UCFG_B0_P0_U0_PLD_IT8 0x40010020 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT9 0x40010024 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT10 0x40010028 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT11 0x4001002c +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT0 0x40010030 +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT1 0x40010032 +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT2 0x40010034 +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT3 0x40010036 +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST 0x40010038 +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB 0x4001003a +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET 0x4001003c +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS 0x4001003e +#define CYDEV_UCFG_B0_P0_U0_CFG0 0x40010040 +#define CYDEV_UCFG_B0_P0_U0_CFG1 0x40010041 +#define CYDEV_UCFG_B0_P0_U0_CFG2 0x40010042 +#define CYDEV_UCFG_B0_P0_U0_CFG3 0x40010043 +#define CYDEV_UCFG_B0_P0_U0_CFG4 0x40010044 +#define CYDEV_UCFG_B0_P0_U0_CFG5 0x40010045 +#define CYDEV_UCFG_B0_P0_U0_CFG6 0x40010046 +#define CYDEV_UCFG_B0_P0_U0_CFG7 0x40010047 +#define CYDEV_UCFG_B0_P0_U0_CFG8 0x40010048 +#define CYDEV_UCFG_B0_P0_U0_CFG9 0x40010049 +#define CYDEV_UCFG_B0_P0_U0_CFG10 0x4001004a +#define CYDEV_UCFG_B0_P0_U0_CFG11 0x4001004b +#define CYDEV_UCFG_B0_P0_U0_CFG12 0x4001004c +#define CYDEV_UCFG_B0_P0_U0_CFG13 0x4001004d +#define CYDEV_UCFG_B0_P0_U0_CFG14 0x4001004e +#define CYDEV_UCFG_B0_P0_U0_CFG15 0x4001004f +#define CYDEV_UCFG_B0_P0_U0_CFG16 0x40010050 +#define CYDEV_UCFG_B0_P0_U0_CFG17 0x40010051 +#define CYDEV_UCFG_B0_P0_U0_CFG18 0x40010052 +#define CYDEV_UCFG_B0_P0_U0_CFG19 0x40010053 +#define CYDEV_UCFG_B0_P0_U0_CFG20 0x40010054 +#define CYDEV_UCFG_B0_P0_U0_CFG21 0x40010055 +#define CYDEV_UCFG_B0_P0_U0_CFG22 0x40010056 +#define CYDEV_UCFG_B0_P0_U0_CFG23 0x40010057 +#define CYDEV_UCFG_B0_P0_U0_CFG24 0x40010058 +#define CYDEV_UCFG_B0_P0_U0_CFG25 0x40010059 +#define CYDEV_UCFG_B0_P0_U0_CFG26 0x4001005a +#define CYDEV_UCFG_B0_P0_U0_CFG27 0x4001005b +#define CYDEV_UCFG_B0_P0_U0_CFG28 0x4001005c +#define CYDEV_UCFG_B0_P0_U0_CFG29 0x4001005d +#define CYDEV_UCFG_B0_P0_U0_CFG30 0x4001005e +#define CYDEV_UCFG_B0_P0_U0_CFG31 0x4001005f +#define CYDEV_UCFG_B0_P0_U0_DCFG0 0x40010060 +#define CYDEV_UCFG_B0_P0_U0_DCFG1 0x40010062 +#define CYDEV_UCFG_B0_P0_U0_DCFG2 0x40010064 +#define CYDEV_UCFG_B0_P0_U0_DCFG3 0x40010066 +#define CYDEV_UCFG_B0_P0_U0_DCFG4 0x40010068 +#define CYDEV_UCFG_B0_P0_U0_DCFG5 0x4001006a +#define CYDEV_UCFG_B0_P0_U0_DCFG6 0x4001006c +#define CYDEV_UCFG_B0_P0_U0_DCFG7 0x4001006e +#define CYDEV_UCFG_B0_P0_U1_BASE 0x40010080 +#define CYDEV_UCFG_B0_P0_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT0 0x40010080 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT1 0x40010084 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT2 0x40010088 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT3 0x4001008c +#define CYDEV_UCFG_B0_P0_U1_PLD_IT4 0x40010090 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT5 0x40010094 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT6 0x40010098 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT7 0x4001009c +#define CYDEV_UCFG_B0_P0_U1_PLD_IT8 0x400100a0 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT9 0x400100a4 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT10 0x400100a8 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT11 0x400100ac +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT0 0x400100b0 +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT1 0x400100b2 +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT2 0x400100b4 +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT3 0x400100b6 +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST 0x400100b8 +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB 0x400100ba +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET 0x400100bc +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS 0x400100be +#define CYDEV_UCFG_B0_P0_U1_CFG0 0x400100c0 +#define CYDEV_UCFG_B0_P0_U1_CFG1 0x400100c1 +#define CYDEV_UCFG_B0_P0_U1_CFG2 0x400100c2 +#define CYDEV_UCFG_B0_P0_U1_CFG3 0x400100c3 +#define CYDEV_UCFG_B0_P0_U1_CFG4 0x400100c4 +#define CYDEV_UCFG_B0_P0_U1_CFG5 0x400100c5 +#define CYDEV_UCFG_B0_P0_U1_CFG6 0x400100c6 +#define CYDEV_UCFG_B0_P0_U1_CFG7 0x400100c7 +#define CYDEV_UCFG_B0_P0_U1_CFG8 0x400100c8 +#define CYDEV_UCFG_B0_P0_U1_CFG9 0x400100c9 +#define CYDEV_UCFG_B0_P0_U1_CFG10 0x400100ca +#define CYDEV_UCFG_B0_P0_U1_CFG11 0x400100cb +#define CYDEV_UCFG_B0_P0_U1_CFG12 0x400100cc +#define CYDEV_UCFG_B0_P0_U1_CFG13 0x400100cd +#define CYDEV_UCFG_B0_P0_U1_CFG14 0x400100ce +#define CYDEV_UCFG_B0_P0_U1_CFG15 0x400100cf +#define CYDEV_UCFG_B0_P0_U1_CFG16 0x400100d0 +#define CYDEV_UCFG_B0_P0_U1_CFG17 0x400100d1 +#define CYDEV_UCFG_B0_P0_U1_CFG18 0x400100d2 +#define CYDEV_UCFG_B0_P0_U1_CFG19 0x400100d3 +#define CYDEV_UCFG_B0_P0_U1_CFG20 0x400100d4 +#define CYDEV_UCFG_B0_P0_U1_CFG21 0x400100d5 +#define CYDEV_UCFG_B0_P0_U1_CFG22 0x400100d6 +#define CYDEV_UCFG_B0_P0_U1_CFG23 0x400100d7 +#define CYDEV_UCFG_B0_P0_U1_CFG24 0x400100d8 +#define CYDEV_UCFG_B0_P0_U1_CFG25 0x400100d9 +#define CYDEV_UCFG_B0_P0_U1_CFG26 0x400100da +#define CYDEV_UCFG_B0_P0_U1_CFG27 0x400100db +#define CYDEV_UCFG_B0_P0_U1_CFG28 0x400100dc +#define CYDEV_UCFG_B0_P0_U1_CFG29 0x400100dd +#define CYDEV_UCFG_B0_P0_U1_CFG30 0x400100de +#define CYDEV_UCFG_B0_P0_U1_CFG31 0x400100df +#define CYDEV_UCFG_B0_P0_U1_DCFG0 0x400100e0 +#define CYDEV_UCFG_B0_P0_U1_DCFG1 0x400100e2 +#define CYDEV_UCFG_B0_P0_U1_DCFG2 0x400100e4 +#define CYDEV_UCFG_B0_P0_U1_DCFG3 0x400100e6 +#define CYDEV_UCFG_B0_P0_U1_DCFG4 0x400100e8 +#define CYDEV_UCFG_B0_P0_U1_DCFG5 0x400100ea +#define CYDEV_UCFG_B0_P0_U1_DCFG6 0x400100ec +#define CYDEV_UCFG_B0_P0_U1_DCFG7 0x400100ee +#define CYDEV_UCFG_B0_P0_ROUTE_BASE 0x40010100 +#define CYDEV_UCFG_B0_P0_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P1_BASE 0x40010200 +#define CYDEV_UCFG_B0_P1_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P1_U0_BASE 0x40010200 +#define CYDEV_UCFG_B0_P1_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT0 0x40010200 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT1 0x40010204 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT2 0x40010208 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT3 0x4001020c +#define CYDEV_UCFG_B0_P1_U0_PLD_IT4 0x40010210 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT5 0x40010214 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT6 0x40010218 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT7 0x4001021c +#define CYDEV_UCFG_B0_P1_U0_PLD_IT8 0x40010220 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT9 0x40010224 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT10 0x40010228 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT11 0x4001022c +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT0 0x40010230 +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT1 0x40010232 +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT2 0x40010234 +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT3 0x40010236 +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST 0x40010238 +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB 0x4001023a +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET 0x4001023c +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS 0x4001023e +#define CYDEV_UCFG_B0_P1_U0_CFG0 0x40010240 +#define CYDEV_UCFG_B0_P1_U0_CFG1 0x40010241 +#define CYDEV_UCFG_B0_P1_U0_CFG2 0x40010242 +#define CYDEV_UCFG_B0_P1_U0_CFG3 0x40010243 +#define CYDEV_UCFG_B0_P1_U0_CFG4 0x40010244 +#define CYDEV_UCFG_B0_P1_U0_CFG5 0x40010245 +#define CYDEV_UCFG_B0_P1_U0_CFG6 0x40010246 +#define CYDEV_UCFG_B0_P1_U0_CFG7 0x40010247 +#define CYDEV_UCFG_B0_P1_U0_CFG8 0x40010248 +#define CYDEV_UCFG_B0_P1_U0_CFG9 0x40010249 +#define CYDEV_UCFG_B0_P1_U0_CFG10 0x4001024a +#define CYDEV_UCFG_B0_P1_U0_CFG11 0x4001024b +#define CYDEV_UCFG_B0_P1_U0_CFG12 0x4001024c +#define CYDEV_UCFG_B0_P1_U0_CFG13 0x4001024d +#define CYDEV_UCFG_B0_P1_U0_CFG14 0x4001024e +#define CYDEV_UCFG_B0_P1_U0_CFG15 0x4001024f +#define CYDEV_UCFG_B0_P1_U0_CFG16 0x40010250 +#define CYDEV_UCFG_B0_P1_U0_CFG17 0x40010251 +#define CYDEV_UCFG_B0_P1_U0_CFG18 0x40010252 +#define CYDEV_UCFG_B0_P1_U0_CFG19 0x40010253 +#define CYDEV_UCFG_B0_P1_U0_CFG20 0x40010254 +#define CYDEV_UCFG_B0_P1_U0_CFG21 0x40010255 +#define CYDEV_UCFG_B0_P1_U0_CFG22 0x40010256 +#define CYDEV_UCFG_B0_P1_U0_CFG23 0x40010257 +#define CYDEV_UCFG_B0_P1_U0_CFG24 0x40010258 +#define CYDEV_UCFG_B0_P1_U0_CFG25 0x40010259 +#define CYDEV_UCFG_B0_P1_U0_CFG26 0x4001025a +#define CYDEV_UCFG_B0_P1_U0_CFG27 0x4001025b +#define CYDEV_UCFG_B0_P1_U0_CFG28 0x4001025c +#define CYDEV_UCFG_B0_P1_U0_CFG29 0x4001025d +#define CYDEV_UCFG_B0_P1_U0_CFG30 0x4001025e +#define CYDEV_UCFG_B0_P1_U0_CFG31 0x4001025f +#define CYDEV_UCFG_B0_P1_U0_DCFG0 0x40010260 +#define CYDEV_UCFG_B0_P1_U0_DCFG1 0x40010262 +#define CYDEV_UCFG_B0_P1_U0_DCFG2 0x40010264 +#define CYDEV_UCFG_B0_P1_U0_DCFG3 0x40010266 +#define CYDEV_UCFG_B0_P1_U0_DCFG4 0x40010268 +#define CYDEV_UCFG_B0_P1_U0_DCFG5 0x4001026a +#define CYDEV_UCFG_B0_P1_U0_DCFG6 0x4001026c +#define CYDEV_UCFG_B0_P1_U0_DCFG7 0x4001026e +#define CYDEV_UCFG_B0_P1_U1_BASE 0x40010280 +#define CYDEV_UCFG_B0_P1_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT0 0x40010280 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT1 0x40010284 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT2 0x40010288 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT3 0x4001028c +#define CYDEV_UCFG_B0_P1_U1_PLD_IT4 0x40010290 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT5 0x40010294 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT6 0x40010298 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT7 0x4001029c +#define CYDEV_UCFG_B0_P1_U1_PLD_IT8 0x400102a0 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT9 0x400102a4 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT10 0x400102a8 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT11 0x400102ac +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT0 0x400102b0 +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT1 0x400102b2 +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT2 0x400102b4 +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT3 0x400102b6 +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST 0x400102b8 +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB 0x400102ba +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET 0x400102bc +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS 0x400102be +#define CYDEV_UCFG_B0_P1_U1_CFG0 0x400102c0 +#define CYDEV_UCFG_B0_P1_U1_CFG1 0x400102c1 +#define CYDEV_UCFG_B0_P1_U1_CFG2 0x400102c2 +#define CYDEV_UCFG_B0_P1_U1_CFG3 0x400102c3 +#define CYDEV_UCFG_B0_P1_U1_CFG4 0x400102c4 +#define CYDEV_UCFG_B0_P1_U1_CFG5 0x400102c5 +#define CYDEV_UCFG_B0_P1_U1_CFG6 0x400102c6 +#define CYDEV_UCFG_B0_P1_U1_CFG7 0x400102c7 +#define CYDEV_UCFG_B0_P1_U1_CFG8 0x400102c8 +#define CYDEV_UCFG_B0_P1_U1_CFG9 0x400102c9 +#define CYDEV_UCFG_B0_P1_U1_CFG10 0x400102ca +#define CYDEV_UCFG_B0_P1_U1_CFG11 0x400102cb +#define CYDEV_UCFG_B0_P1_U1_CFG12 0x400102cc +#define CYDEV_UCFG_B0_P1_U1_CFG13 0x400102cd +#define CYDEV_UCFG_B0_P1_U1_CFG14 0x400102ce +#define CYDEV_UCFG_B0_P1_U1_CFG15 0x400102cf +#define CYDEV_UCFG_B0_P1_U1_CFG16 0x400102d0 +#define CYDEV_UCFG_B0_P1_U1_CFG17 0x400102d1 +#define CYDEV_UCFG_B0_P1_U1_CFG18 0x400102d2 +#define CYDEV_UCFG_B0_P1_U1_CFG19 0x400102d3 +#define CYDEV_UCFG_B0_P1_U1_CFG20 0x400102d4 +#define CYDEV_UCFG_B0_P1_U1_CFG21 0x400102d5 +#define CYDEV_UCFG_B0_P1_U1_CFG22 0x400102d6 +#define CYDEV_UCFG_B0_P1_U1_CFG23 0x400102d7 +#define CYDEV_UCFG_B0_P1_U1_CFG24 0x400102d8 +#define CYDEV_UCFG_B0_P1_U1_CFG25 0x400102d9 +#define CYDEV_UCFG_B0_P1_U1_CFG26 0x400102da +#define CYDEV_UCFG_B0_P1_U1_CFG27 0x400102db +#define CYDEV_UCFG_B0_P1_U1_CFG28 0x400102dc +#define CYDEV_UCFG_B0_P1_U1_CFG29 0x400102dd +#define CYDEV_UCFG_B0_P1_U1_CFG30 0x400102de +#define CYDEV_UCFG_B0_P1_U1_CFG31 0x400102df +#define CYDEV_UCFG_B0_P1_U1_DCFG0 0x400102e0 +#define CYDEV_UCFG_B0_P1_U1_DCFG1 0x400102e2 +#define CYDEV_UCFG_B0_P1_U1_DCFG2 0x400102e4 +#define CYDEV_UCFG_B0_P1_U1_DCFG3 0x400102e6 +#define CYDEV_UCFG_B0_P1_U1_DCFG4 0x400102e8 +#define CYDEV_UCFG_B0_P1_U1_DCFG5 0x400102ea +#define CYDEV_UCFG_B0_P1_U1_DCFG6 0x400102ec +#define CYDEV_UCFG_B0_P1_U1_DCFG7 0x400102ee +#define CYDEV_UCFG_B0_P1_ROUTE_BASE 0x40010300 +#define CYDEV_UCFG_B0_P1_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P2_BASE 0x40010400 +#define CYDEV_UCFG_B0_P2_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P2_U0_BASE 0x40010400 +#define CYDEV_UCFG_B0_P2_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT0 0x40010400 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT1 0x40010404 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT2 0x40010408 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT3 0x4001040c +#define CYDEV_UCFG_B0_P2_U0_PLD_IT4 0x40010410 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT5 0x40010414 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT6 0x40010418 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT7 0x4001041c +#define CYDEV_UCFG_B0_P2_U0_PLD_IT8 0x40010420 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT9 0x40010424 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT10 0x40010428 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT11 0x4001042c +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT0 0x40010430 +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT1 0x40010432 +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT2 0x40010434 +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT3 0x40010436 +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST 0x40010438 +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB 0x4001043a +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET 0x4001043c +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS 0x4001043e +#define CYDEV_UCFG_B0_P2_U0_CFG0 0x40010440 +#define CYDEV_UCFG_B0_P2_U0_CFG1 0x40010441 +#define CYDEV_UCFG_B0_P2_U0_CFG2 0x40010442 +#define CYDEV_UCFG_B0_P2_U0_CFG3 0x40010443 +#define CYDEV_UCFG_B0_P2_U0_CFG4 0x40010444 +#define CYDEV_UCFG_B0_P2_U0_CFG5 0x40010445 +#define CYDEV_UCFG_B0_P2_U0_CFG6 0x40010446 +#define CYDEV_UCFG_B0_P2_U0_CFG7 0x40010447 +#define CYDEV_UCFG_B0_P2_U0_CFG8 0x40010448 +#define CYDEV_UCFG_B0_P2_U0_CFG9 0x40010449 +#define CYDEV_UCFG_B0_P2_U0_CFG10 0x4001044a +#define CYDEV_UCFG_B0_P2_U0_CFG11 0x4001044b +#define CYDEV_UCFG_B0_P2_U0_CFG12 0x4001044c +#define CYDEV_UCFG_B0_P2_U0_CFG13 0x4001044d +#define CYDEV_UCFG_B0_P2_U0_CFG14 0x4001044e +#define CYDEV_UCFG_B0_P2_U0_CFG15 0x4001044f +#define CYDEV_UCFG_B0_P2_U0_CFG16 0x40010450 +#define CYDEV_UCFG_B0_P2_U0_CFG17 0x40010451 +#define CYDEV_UCFG_B0_P2_U0_CFG18 0x40010452 +#define CYDEV_UCFG_B0_P2_U0_CFG19 0x40010453 +#define CYDEV_UCFG_B0_P2_U0_CFG20 0x40010454 +#define CYDEV_UCFG_B0_P2_U0_CFG21 0x40010455 +#define CYDEV_UCFG_B0_P2_U0_CFG22 0x40010456 +#define CYDEV_UCFG_B0_P2_U0_CFG23 0x40010457 +#define CYDEV_UCFG_B0_P2_U0_CFG24 0x40010458 +#define CYDEV_UCFG_B0_P2_U0_CFG25 0x40010459 +#define CYDEV_UCFG_B0_P2_U0_CFG26 0x4001045a +#define CYDEV_UCFG_B0_P2_U0_CFG27 0x4001045b +#define CYDEV_UCFG_B0_P2_U0_CFG28 0x4001045c +#define CYDEV_UCFG_B0_P2_U0_CFG29 0x4001045d +#define CYDEV_UCFG_B0_P2_U0_CFG30 0x4001045e +#define CYDEV_UCFG_B0_P2_U0_CFG31 0x4001045f +#define CYDEV_UCFG_B0_P2_U0_DCFG0 0x40010460 +#define CYDEV_UCFG_B0_P2_U0_DCFG1 0x40010462 +#define CYDEV_UCFG_B0_P2_U0_DCFG2 0x40010464 +#define CYDEV_UCFG_B0_P2_U0_DCFG3 0x40010466 +#define CYDEV_UCFG_B0_P2_U0_DCFG4 0x40010468 +#define CYDEV_UCFG_B0_P2_U0_DCFG5 0x4001046a +#define CYDEV_UCFG_B0_P2_U0_DCFG6 0x4001046c +#define CYDEV_UCFG_B0_P2_U0_DCFG7 0x4001046e +#define CYDEV_UCFG_B0_P2_U1_BASE 0x40010480 +#define CYDEV_UCFG_B0_P2_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT0 0x40010480 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT1 0x40010484 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT2 0x40010488 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT3 0x4001048c +#define CYDEV_UCFG_B0_P2_U1_PLD_IT4 0x40010490 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT5 0x40010494 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT6 0x40010498 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT7 0x4001049c +#define CYDEV_UCFG_B0_P2_U1_PLD_IT8 0x400104a0 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT9 0x400104a4 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT10 0x400104a8 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT11 0x400104ac +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT0 0x400104b0 +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT1 0x400104b2 +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT2 0x400104b4 +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT3 0x400104b6 +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST 0x400104b8 +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB 0x400104ba +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET 0x400104bc +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS 0x400104be +#define CYDEV_UCFG_B0_P2_U1_CFG0 0x400104c0 +#define CYDEV_UCFG_B0_P2_U1_CFG1 0x400104c1 +#define CYDEV_UCFG_B0_P2_U1_CFG2 0x400104c2 +#define CYDEV_UCFG_B0_P2_U1_CFG3 0x400104c3 +#define CYDEV_UCFG_B0_P2_U1_CFG4 0x400104c4 +#define CYDEV_UCFG_B0_P2_U1_CFG5 0x400104c5 +#define CYDEV_UCFG_B0_P2_U1_CFG6 0x400104c6 +#define CYDEV_UCFG_B0_P2_U1_CFG7 0x400104c7 +#define CYDEV_UCFG_B0_P2_U1_CFG8 0x400104c8 +#define CYDEV_UCFG_B0_P2_U1_CFG9 0x400104c9 +#define CYDEV_UCFG_B0_P2_U1_CFG10 0x400104ca +#define CYDEV_UCFG_B0_P2_U1_CFG11 0x400104cb +#define CYDEV_UCFG_B0_P2_U1_CFG12 0x400104cc +#define CYDEV_UCFG_B0_P2_U1_CFG13 0x400104cd +#define CYDEV_UCFG_B0_P2_U1_CFG14 0x400104ce +#define CYDEV_UCFG_B0_P2_U1_CFG15 0x400104cf +#define CYDEV_UCFG_B0_P2_U1_CFG16 0x400104d0 +#define CYDEV_UCFG_B0_P2_U1_CFG17 0x400104d1 +#define CYDEV_UCFG_B0_P2_U1_CFG18 0x400104d2 +#define CYDEV_UCFG_B0_P2_U1_CFG19 0x400104d3 +#define CYDEV_UCFG_B0_P2_U1_CFG20 0x400104d4 +#define CYDEV_UCFG_B0_P2_U1_CFG21 0x400104d5 +#define CYDEV_UCFG_B0_P2_U1_CFG22 0x400104d6 +#define CYDEV_UCFG_B0_P2_U1_CFG23 0x400104d7 +#define CYDEV_UCFG_B0_P2_U1_CFG24 0x400104d8 +#define CYDEV_UCFG_B0_P2_U1_CFG25 0x400104d9 +#define CYDEV_UCFG_B0_P2_U1_CFG26 0x400104da +#define CYDEV_UCFG_B0_P2_U1_CFG27 0x400104db +#define CYDEV_UCFG_B0_P2_U1_CFG28 0x400104dc +#define CYDEV_UCFG_B0_P2_U1_CFG29 0x400104dd +#define CYDEV_UCFG_B0_P2_U1_CFG30 0x400104de +#define CYDEV_UCFG_B0_P2_U1_CFG31 0x400104df +#define CYDEV_UCFG_B0_P2_U1_DCFG0 0x400104e0 +#define CYDEV_UCFG_B0_P2_U1_DCFG1 0x400104e2 +#define CYDEV_UCFG_B0_P2_U1_DCFG2 0x400104e4 +#define CYDEV_UCFG_B0_P2_U1_DCFG3 0x400104e6 +#define CYDEV_UCFG_B0_P2_U1_DCFG4 0x400104e8 +#define CYDEV_UCFG_B0_P2_U1_DCFG5 0x400104ea +#define CYDEV_UCFG_B0_P2_U1_DCFG6 0x400104ec +#define CYDEV_UCFG_B0_P2_U1_DCFG7 0x400104ee +#define CYDEV_UCFG_B0_P2_ROUTE_BASE 0x40010500 +#define CYDEV_UCFG_B0_P2_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P3_BASE 0x40010600 +#define CYDEV_UCFG_B0_P3_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P3_U0_BASE 0x40010600 +#define CYDEV_UCFG_B0_P3_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT0 0x40010600 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT1 0x40010604 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT2 0x40010608 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT3 0x4001060c +#define CYDEV_UCFG_B0_P3_U0_PLD_IT4 0x40010610 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT5 0x40010614 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT6 0x40010618 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT7 0x4001061c +#define CYDEV_UCFG_B0_P3_U0_PLD_IT8 0x40010620 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT9 0x40010624 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT10 0x40010628 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT11 0x4001062c +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT0 0x40010630 +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT1 0x40010632 +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT2 0x40010634 +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT3 0x40010636 +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST 0x40010638 +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB 0x4001063a +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET 0x4001063c +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS 0x4001063e +#define CYDEV_UCFG_B0_P3_U0_CFG0 0x40010640 +#define CYDEV_UCFG_B0_P3_U0_CFG1 0x40010641 +#define CYDEV_UCFG_B0_P3_U0_CFG2 0x40010642 +#define CYDEV_UCFG_B0_P3_U0_CFG3 0x40010643 +#define CYDEV_UCFG_B0_P3_U0_CFG4 0x40010644 +#define CYDEV_UCFG_B0_P3_U0_CFG5 0x40010645 +#define CYDEV_UCFG_B0_P3_U0_CFG6 0x40010646 +#define CYDEV_UCFG_B0_P3_U0_CFG7 0x40010647 +#define CYDEV_UCFG_B0_P3_U0_CFG8 0x40010648 +#define CYDEV_UCFG_B0_P3_U0_CFG9 0x40010649 +#define CYDEV_UCFG_B0_P3_U0_CFG10 0x4001064a +#define CYDEV_UCFG_B0_P3_U0_CFG11 0x4001064b +#define CYDEV_UCFG_B0_P3_U0_CFG12 0x4001064c +#define CYDEV_UCFG_B0_P3_U0_CFG13 0x4001064d +#define CYDEV_UCFG_B0_P3_U0_CFG14 0x4001064e +#define CYDEV_UCFG_B0_P3_U0_CFG15 0x4001064f +#define CYDEV_UCFG_B0_P3_U0_CFG16 0x40010650 +#define CYDEV_UCFG_B0_P3_U0_CFG17 0x40010651 +#define CYDEV_UCFG_B0_P3_U0_CFG18 0x40010652 +#define CYDEV_UCFG_B0_P3_U0_CFG19 0x40010653 +#define CYDEV_UCFG_B0_P3_U0_CFG20 0x40010654 +#define CYDEV_UCFG_B0_P3_U0_CFG21 0x40010655 +#define CYDEV_UCFG_B0_P3_U0_CFG22 0x40010656 +#define CYDEV_UCFG_B0_P3_U0_CFG23 0x40010657 +#define CYDEV_UCFG_B0_P3_U0_CFG24 0x40010658 +#define CYDEV_UCFG_B0_P3_U0_CFG25 0x40010659 +#define CYDEV_UCFG_B0_P3_U0_CFG26 0x4001065a +#define CYDEV_UCFG_B0_P3_U0_CFG27 0x4001065b +#define CYDEV_UCFG_B0_P3_U0_CFG28 0x4001065c +#define CYDEV_UCFG_B0_P3_U0_CFG29 0x4001065d +#define CYDEV_UCFG_B0_P3_U0_CFG30 0x4001065e +#define CYDEV_UCFG_B0_P3_U0_CFG31 0x4001065f +#define CYDEV_UCFG_B0_P3_U0_DCFG0 0x40010660 +#define CYDEV_UCFG_B0_P3_U0_DCFG1 0x40010662 +#define CYDEV_UCFG_B0_P3_U0_DCFG2 0x40010664 +#define CYDEV_UCFG_B0_P3_U0_DCFG3 0x40010666 +#define CYDEV_UCFG_B0_P3_U0_DCFG4 0x40010668 +#define CYDEV_UCFG_B0_P3_U0_DCFG5 0x4001066a +#define CYDEV_UCFG_B0_P3_U0_DCFG6 0x4001066c +#define CYDEV_UCFG_B0_P3_U0_DCFG7 0x4001066e +#define CYDEV_UCFG_B0_P3_U1_BASE 0x40010680 +#define CYDEV_UCFG_B0_P3_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT0 0x40010680 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT1 0x40010684 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT2 0x40010688 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT3 0x4001068c +#define CYDEV_UCFG_B0_P3_U1_PLD_IT4 0x40010690 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT5 0x40010694 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT6 0x40010698 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT7 0x4001069c +#define CYDEV_UCFG_B0_P3_U1_PLD_IT8 0x400106a0 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT9 0x400106a4 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT10 0x400106a8 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT11 0x400106ac +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT0 0x400106b0 +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT1 0x400106b2 +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT2 0x400106b4 +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT3 0x400106b6 +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST 0x400106b8 +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB 0x400106ba +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET 0x400106bc +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS 0x400106be +#define CYDEV_UCFG_B0_P3_U1_CFG0 0x400106c0 +#define CYDEV_UCFG_B0_P3_U1_CFG1 0x400106c1 +#define CYDEV_UCFG_B0_P3_U1_CFG2 0x400106c2 +#define CYDEV_UCFG_B0_P3_U1_CFG3 0x400106c3 +#define CYDEV_UCFG_B0_P3_U1_CFG4 0x400106c4 +#define CYDEV_UCFG_B0_P3_U1_CFG5 0x400106c5 +#define CYDEV_UCFG_B0_P3_U1_CFG6 0x400106c6 +#define CYDEV_UCFG_B0_P3_U1_CFG7 0x400106c7 +#define CYDEV_UCFG_B0_P3_U1_CFG8 0x400106c8 +#define CYDEV_UCFG_B0_P3_U1_CFG9 0x400106c9 +#define CYDEV_UCFG_B0_P3_U1_CFG10 0x400106ca +#define CYDEV_UCFG_B0_P3_U1_CFG11 0x400106cb +#define CYDEV_UCFG_B0_P3_U1_CFG12 0x400106cc +#define CYDEV_UCFG_B0_P3_U1_CFG13 0x400106cd +#define CYDEV_UCFG_B0_P3_U1_CFG14 0x400106ce +#define CYDEV_UCFG_B0_P3_U1_CFG15 0x400106cf +#define CYDEV_UCFG_B0_P3_U1_CFG16 0x400106d0 +#define CYDEV_UCFG_B0_P3_U1_CFG17 0x400106d1 +#define CYDEV_UCFG_B0_P3_U1_CFG18 0x400106d2 +#define CYDEV_UCFG_B0_P3_U1_CFG19 0x400106d3 +#define CYDEV_UCFG_B0_P3_U1_CFG20 0x400106d4 +#define CYDEV_UCFG_B0_P3_U1_CFG21 0x400106d5 +#define CYDEV_UCFG_B0_P3_U1_CFG22 0x400106d6 +#define CYDEV_UCFG_B0_P3_U1_CFG23 0x400106d7 +#define CYDEV_UCFG_B0_P3_U1_CFG24 0x400106d8 +#define CYDEV_UCFG_B0_P3_U1_CFG25 0x400106d9 +#define CYDEV_UCFG_B0_P3_U1_CFG26 0x400106da +#define CYDEV_UCFG_B0_P3_U1_CFG27 0x400106db +#define CYDEV_UCFG_B0_P3_U1_CFG28 0x400106dc +#define CYDEV_UCFG_B0_P3_U1_CFG29 0x400106dd +#define CYDEV_UCFG_B0_P3_U1_CFG30 0x400106de +#define CYDEV_UCFG_B0_P3_U1_CFG31 0x400106df +#define CYDEV_UCFG_B0_P3_U1_DCFG0 0x400106e0 +#define CYDEV_UCFG_B0_P3_U1_DCFG1 0x400106e2 +#define CYDEV_UCFG_B0_P3_U1_DCFG2 0x400106e4 +#define CYDEV_UCFG_B0_P3_U1_DCFG3 0x400106e6 +#define CYDEV_UCFG_B0_P3_U1_DCFG4 0x400106e8 +#define CYDEV_UCFG_B0_P3_U1_DCFG5 0x400106ea +#define CYDEV_UCFG_B0_P3_U1_DCFG6 0x400106ec +#define CYDEV_UCFG_B0_P3_U1_DCFG7 0x400106ee +#define CYDEV_UCFG_B0_P3_ROUTE_BASE 0x40010700 +#define CYDEV_UCFG_B0_P3_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P4_BASE 0x40010800 +#define CYDEV_UCFG_B0_P4_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P4_U0_BASE 0x40010800 +#define CYDEV_UCFG_B0_P4_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT0 0x40010800 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT1 0x40010804 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT2 0x40010808 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT3 0x4001080c +#define CYDEV_UCFG_B0_P4_U0_PLD_IT4 0x40010810 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT5 0x40010814 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT6 0x40010818 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT7 0x4001081c +#define CYDEV_UCFG_B0_P4_U0_PLD_IT8 0x40010820 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT9 0x40010824 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT10 0x40010828 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT11 0x4001082c +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT0 0x40010830 +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT1 0x40010832 +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT2 0x40010834 +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT3 0x40010836 +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST 0x40010838 +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB 0x4001083a +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET 0x4001083c +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS 0x4001083e +#define CYDEV_UCFG_B0_P4_U0_CFG0 0x40010840 +#define CYDEV_UCFG_B0_P4_U0_CFG1 0x40010841 +#define CYDEV_UCFG_B0_P4_U0_CFG2 0x40010842 +#define CYDEV_UCFG_B0_P4_U0_CFG3 0x40010843 +#define CYDEV_UCFG_B0_P4_U0_CFG4 0x40010844 +#define CYDEV_UCFG_B0_P4_U0_CFG5 0x40010845 +#define CYDEV_UCFG_B0_P4_U0_CFG6 0x40010846 +#define CYDEV_UCFG_B0_P4_U0_CFG7 0x40010847 +#define CYDEV_UCFG_B0_P4_U0_CFG8 0x40010848 +#define CYDEV_UCFG_B0_P4_U0_CFG9 0x40010849 +#define CYDEV_UCFG_B0_P4_U0_CFG10 0x4001084a +#define CYDEV_UCFG_B0_P4_U0_CFG11 0x4001084b +#define CYDEV_UCFG_B0_P4_U0_CFG12 0x4001084c +#define CYDEV_UCFG_B0_P4_U0_CFG13 0x4001084d +#define CYDEV_UCFG_B0_P4_U0_CFG14 0x4001084e +#define CYDEV_UCFG_B0_P4_U0_CFG15 0x4001084f +#define CYDEV_UCFG_B0_P4_U0_CFG16 0x40010850 +#define CYDEV_UCFG_B0_P4_U0_CFG17 0x40010851 +#define CYDEV_UCFG_B0_P4_U0_CFG18 0x40010852 +#define CYDEV_UCFG_B0_P4_U0_CFG19 0x40010853 +#define CYDEV_UCFG_B0_P4_U0_CFG20 0x40010854 +#define CYDEV_UCFG_B0_P4_U0_CFG21 0x40010855 +#define CYDEV_UCFG_B0_P4_U0_CFG22 0x40010856 +#define CYDEV_UCFG_B0_P4_U0_CFG23 0x40010857 +#define CYDEV_UCFG_B0_P4_U0_CFG24 0x40010858 +#define CYDEV_UCFG_B0_P4_U0_CFG25 0x40010859 +#define CYDEV_UCFG_B0_P4_U0_CFG26 0x4001085a +#define CYDEV_UCFG_B0_P4_U0_CFG27 0x4001085b +#define CYDEV_UCFG_B0_P4_U0_CFG28 0x4001085c +#define CYDEV_UCFG_B0_P4_U0_CFG29 0x4001085d +#define CYDEV_UCFG_B0_P4_U0_CFG30 0x4001085e +#define CYDEV_UCFG_B0_P4_U0_CFG31 0x4001085f +#define CYDEV_UCFG_B0_P4_U0_DCFG0 0x40010860 +#define CYDEV_UCFG_B0_P4_U0_DCFG1 0x40010862 +#define CYDEV_UCFG_B0_P4_U0_DCFG2 0x40010864 +#define CYDEV_UCFG_B0_P4_U0_DCFG3 0x40010866 +#define CYDEV_UCFG_B0_P4_U0_DCFG4 0x40010868 +#define CYDEV_UCFG_B0_P4_U0_DCFG5 0x4001086a +#define CYDEV_UCFG_B0_P4_U0_DCFG6 0x4001086c +#define CYDEV_UCFG_B0_P4_U0_DCFG7 0x4001086e +#define CYDEV_UCFG_B0_P4_U1_BASE 0x40010880 +#define CYDEV_UCFG_B0_P4_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT0 0x40010880 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT1 0x40010884 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT2 0x40010888 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT3 0x4001088c +#define CYDEV_UCFG_B0_P4_U1_PLD_IT4 0x40010890 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT5 0x40010894 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT6 0x40010898 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT7 0x4001089c +#define CYDEV_UCFG_B0_P4_U1_PLD_IT8 0x400108a0 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT9 0x400108a4 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT10 0x400108a8 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT11 0x400108ac +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT0 0x400108b0 +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT1 0x400108b2 +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT2 0x400108b4 +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT3 0x400108b6 +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST 0x400108b8 +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB 0x400108ba +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET 0x400108bc +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS 0x400108be +#define CYDEV_UCFG_B0_P4_U1_CFG0 0x400108c0 +#define CYDEV_UCFG_B0_P4_U1_CFG1 0x400108c1 +#define CYDEV_UCFG_B0_P4_U1_CFG2 0x400108c2 +#define CYDEV_UCFG_B0_P4_U1_CFG3 0x400108c3 +#define CYDEV_UCFG_B0_P4_U1_CFG4 0x400108c4 +#define CYDEV_UCFG_B0_P4_U1_CFG5 0x400108c5 +#define CYDEV_UCFG_B0_P4_U1_CFG6 0x400108c6 +#define CYDEV_UCFG_B0_P4_U1_CFG7 0x400108c7 +#define CYDEV_UCFG_B0_P4_U1_CFG8 0x400108c8 +#define CYDEV_UCFG_B0_P4_U1_CFG9 0x400108c9 +#define CYDEV_UCFG_B0_P4_U1_CFG10 0x400108ca +#define CYDEV_UCFG_B0_P4_U1_CFG11 0x400108cb +#define CYDEV_UCFG_B0_P4_U1_CFG12 0x400108cc +#define CYDEV_UCFG_B0_P4_U1_CFG13 0x400108cd +#define CYDEV_UCFG_B0_P4_U1_CFG14 0x400108ce +#define CYDEV_UCFG_B0_P4_U1_CFG15 0x400108cf +#define CYDEV_UCFG_B0_P4_U1_CFG16 0x400108d0 +#define CYDEV_UCFG_B0_P4_U1_CFG17 0x400108d1 +#define CYDEV_UCFG_B0_P4_U1_CFG18 0x400108d2 +#define CYDEV_UCFG_B0_P4_U1_CFG19 0x400108d3 +#define CYDEV_UCFG_B0_P4_U1_CFG20 0x400108d4 +#define CYDEV_UCFG_B0_P4_U1_CFG21 0x400108d5 +#define CYDEV_UCFG_B0_P4_U1_CFG22 0x400108d6 +#define CYDEV_UCFG_B0_P4_U1_CFG23 0x400108d7 +#define CYDEV_UCFG_B0_P4_U1_CFG24 0x400108d8 +#define CYDEV_UCFG_B0_P4_U1_CFG25 0x400108d9 +#define CYDEV_UCFG_B0_P4_U1_CFG26 0x400108da +#define CYDEV_UCFG_B0_P4_U1_CFG27 0x400108db +#define CYDEV_UCFG_B0_P4_U1_CFG28 0x400108dc +#define CYDEV_UCFG_B0_P4_U1_CFG29 0x400108dd +#define CYDEV_UCFG_B0_P4_U1_CFG30 0x400108de +#define CYDEV_UCFG_B0_P4_U1_CFG31 0x400108df +#define CYDEV_UCFG_B0_P4_U1_DCFG0 0x400108e0 +#define CYDEV_UCFG_B0_P4_U1_DCFG1 0x400108e2 +#define CYDEV_UCFG_B0_P4_U1_DCFG2 0x400108e4 +#define CYDEV_UCFG_B0_P4_U1_DCFG3 0x400108e6 +#define CYDEV_UCFG_B0_P4_U1_DCFG4 0x400108e8 +#define CYDEV_UCFG_B0_P4_U1_DCFG5 0x400108ea +#define CYDEV_UCFG_B0_P4_U1_DCFG6 0x400108ec +#define CYDEV_UCFG_B0_P4_U1_DCFG7 0x400108ee +#define CYDEV_UCFG_B0_P4_ROUTE_BASE 0x40010900 +#define CYDEV_UCFG_B0_P4_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P5_BASE 0x40010a00 +#define CYDEV_UCFG_B0_P5_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P5_U0_BASE 0x40010a00 +#define CYDEV_UCFG_B0_P5_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT0 0x40010a00 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT1 0x40010a04 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT2 0x40010a08 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT3 0x40010a0c +#define CYDEV_UCFG_B0_P5_U0_PLD_IT4 0x40010a10 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT5 0x40010a14 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT6 0x40010a18 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT7 0x40010a1c +#define CYDEV_UCFG_B0_P5_U0_PLD_IT8 0x40010a20 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT9 0x40010a24 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT10 0x40010a28 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT11 0x40010a2c +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT0 0x40010a30 +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT1 0x40010a32 +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT2 0x40010a34 +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT3 0x40010a36 +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST 0x40010a38 +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB 0x40010a3a +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET 0x40010a3c +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS 0x40010a3e +#define CYDEV_UCFG_B0_P5_U0_CFG0 0x40010a40 +#define CYDEV_UCFG_B0_P5_U0_CFG1 0x40010a41 +#define CYDEV_UCFG_B0_P5_U0_CFG2 0x40010a42 +#define CYDEV_UCFG_B0_P5_U0_CFG3 0x40010a43 +#define CYDEV_UCFG_B0_P5_U0_CFG4 0x40010a44 +#define CYDEV_UCFG_B0_P5_U0_CFG5 0x40010a45 +#define CYDEV_UCFG_B0_P5_U0_CFG6 0x40010a46 +#define CYDEV_UCFG_B0_P5_U0_CFG7 0x40010a47 +#define CYDEV_UCFG_B0_P5_U0_CFG8 0x40010a48 +#define CYDEV_UCFG_B0_P5_U0_CFG9 0x40010a49 +#define CYDEV_UCFG_B0_P5_U0_CFG10 0x40010a4a +#define CYDEV_UCFG_B0_P5_U0_CFG11 0x40010a4b +#define CYDEV_UCFG_B0_P5_U0_CFG12 0x40010a4c +#define CYDEV_UCFG_B0_P5_U0_CFG13 0x40010a4d +#define CYDEV_UCFG_B0_P5_U0_CFG14 0x40010a4e +#define CYDEV_UCFG_B0_P5_U0_CFG15 0x40010a4f +#define CYDEV_UCFG_B0_P5_U0_CFG16 0x40010a50 +#define CYDEV_UCFG_B0_P5_U0_CFG17 0x40010a51 +#define CYDEV_UCFG_B0_P5_U0_CFG18 0x40010a52 +#define CYDEV_UCFG_B0_P5_U0_CFG19 0x40010a53 +#define CYDEV_UCFG_B0_P5_U0_CFG20 0x40010a54 +#define CYDEV_UCFG_B0_P5_U0_CFG21 0x40010a55 +#define CYDEV_UCFG_B0_P5_U0_CFG22 0x40010a56 +#define CYDEV_UCFG_B0_P5_U0_CFG23 0x40010a57 +#define CYDEV_UCFG_B0_P5_U0_CFG24 0x40010a58 +#define CYDEV_UCFG_B0_P5_U0_CFG25 0x40010a59 +#define CYDEV_UCFG_B0_P5_U0_CFG26 0x40010a5a +#define CYDEV_UCFG_B0_P5_U0_CFG27 0x40010a5b +#define CYDEV_UCFG_B0_P5_U0_CFG28 0x40010a5c +#define CYDEV_UCFG_B0_P5_U0_CFG29 0x40010a5d +#define CYDEV_UCFG_B0_P5_U0_CFG30 0x40010a5e +#define CYDEV_UCFG_B0_P5_U0_CFG31 0x40010a5f +#define CYDEV_UCFG_B0_P5_U0_DCFG0 0x40010a60 +#define CYDEV_UCFG_B0_P5_U0_DCFG1 0x40010a62 +#define CYDEV_UCFG_B0_P5_U0_DCFG2 0x40010a64 +#define CYDEV_UCFG_B0_P5_U0_DCFG3 0x40010a66 +#define CYDEV_UCFG_B0_P5_U0_DCFG4 0x40010a68 +#define CYDEV_UCFG_B0_P5_U0_DCFG5 0x40010a6a +#define CYDEV_UCFG_B0_P5_U0_DCFG6 0x40010a6c +#define CYDEV_UCFG_B0_P5_U0_DCFG7 0x40010a6e +#define CYDEV_UCFG_B0_P5_U1_BASE 0x40010a80 +#define CYDEV_UCFG_B0_P5_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT0 0x40010a80 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT1 0x40010a84 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT2 0x40010a88 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT3 0x40010a8c +#define CYDEV_UCFG_B0_P5_U1_PLD_IT4 0x40010a90 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT5 0x40010a94 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT6 0x40010a98 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT7 0x40010a9c +#define CYDEV_UCFG_B0_P5_U1_PLD_IT8 0x40010aa0 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT9 0x40010aa4 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT10 0x40010aa8 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT11 0x40010aac +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT0 0x40010ab0 +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT1 0x40010ab2 +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT2 0x40010ab4 +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT3 0x40010ab6 +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST 0x40010ab8 +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB 0x40010aba +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET 0x40010abc +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS 0x40010abe +#define CYDEV_UCFG_B0_P5_U1_CFG0 0x40010ac0 +#define CYDEV_UCFG_B0_P5_U1_CFG1 0x40010ac1 +#define CYDEV_UCFG_B0_P5_U1_CFG2 0x40010ac2 +#define CYDEV_UCFG_B0_P5_U1_CFG3 0x40010ac3 +#define CYDEV_UCFG_B0_P5_U1_CFG4 0x40010ac4 +#define CYDEV_UCFG_B0_P5_U1_CFG5 0x40010ac5 +#define CYDEV_UCFG_B0_P5_U1_CFG6 0x40010ac6 +#define CYDEV_UCFG_B0_P5_U1_CFG7 0x40010ac7 +#define CYDEV_UCFG_B0_P5_U1_CFG8 0x40010ac8 +#define CYDEV_UCFG_B0_P5_U1_CFG9 0x40010ac9 +#define CYDEV_UCFG_B0_P5_U1_CFG10 0x40010aca +#define CYDEV_UCFG_B0_P5_U1_CFG11 0x40010acb +#define CYDEV_UCFG_B0_P5_U1_CFG12 0x40010acc +#define CYDEV_UCFG_B0_P5_U1_CFG13 0x40010acd +#define CYDEV_UCFG_B0_P5_U1_CFG14 0x40010ace +#define CYDEV_UCFG_B0_P5_U1_CFG15 0x40010acf +#define CYDEV_UCFG_B0_P5_U1_CFG16 0x40010ad0 +#define CYDEV_UCFG_B0_P5_U1_CFG17 0x40010ad1 +#define CYDEV_UCFG_B0_P5_U1_CFG18 0x40010ad2 +#define CYDEV_UCFG_B0_P5_U1_CFG19 0x40010ad3 +#define CYDEV_UCFG_B0_P5_U1_CFG20 0x40010ad4 +#define CYDEV_UCFG_B0_P5_U1_CFG21 0x40010ad5 +#define CYDEV_UCFG_B0_P5_U1_CFG22 0x40010ad6 +#define CYDEV_UCFG_B0_P5_U1_CFG23 0x40010ad7 +#define CYDEV_UCFG_B0_P5_U1_CFG24 0x40010ad8 +#define CYDEV_UCFG_B0_P5_U1_CFG25 0x40010ad9 +#define CYDEV_UCFG_B0_P5_U1_CFG26 0x40010ada +#define CYDEV_UCFG_B0_P5_U1_CFG27 0x40010adb +#define CYDEV_UCFG_B0_P5_U1_CFG28 0x40010adc +#define CYDEV_UCFG_B0_P5_U1_CFG29 0x40010add +#define CYDEV_UCFG_B0_P5_U1_CFG30 0x40010ade +#define CYDEV_UCFG_B0_P5_U1_CFG31 0x40010adf +#define CYDEV_UCFG_B0_P5_U1_DCFG0 0x40010ae0 +#define CYDEV_UCFG_B0_P5_U1_DCFG1 0x40010ae2 +#define CYDEV_UCFG_B0_P5_U1_DCFG2 0x40010ae4 +#define CYDEV_UCFG_B0_P5_U1_DCFG3 0x40010ae6 +#define CYDEV_UCFG_B0_P5_U1_DCFG4 0x40010ae8 +#define CYDEV_UCFG_B0_P5_U1_DCFG5 0x40010aea +#define CYDEV_UCFG_B0_P5_U1_DCFG6 0x40010aec +#define CYDEV_UCFG_B0_P5_U1_DCFG7 0x40010aee +#define CYDEV_UCFG_B0_P5_ROUTE_BASE 0x40010b00 +#define CYDEV_UCFG_B0_P5_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P6_BASE 0x40010c00 +#define CYDEV_UCFG_B0_P6_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P6_U0_BASE 0x40010c00 +#define CYDEV_UCFG_B0_P6_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT0 0x40010c00 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT1 0x40010c04 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT2 0x40010c08 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT3 0x40010c0c +#define CYDEV_UCFG_B0_P6_U0_PLD_IT4 0x40010c10 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT5 0x40010c14 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT6 0x40010c18 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT7 0x40010c1c +#define CYDEV_UCFG_B0_P6_U0_PLD_IT8 0x40010c20 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT9 0x40010c24 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT10 0x40010c28 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT11 0x40010c2c +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT0 0x40010c30 +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT1 0x40010c32 +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT2 0x40010c34 +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT3 0x40010c36 +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST 0x40010c38 +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB 0x40010c3a +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET 0x40010c3c +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS 0x40010c3e +#define CYDEV_UCFG_B0_P6_U0_CFG0 0x40010c40 +#define CYDEV_UCFG_B0_P6_U0_CFG1 0x40010c41 +#define CYDEV_UCFG_B0_P6_U0_CFG2 0x40010c42 +#define CYDEV_UCFG_B0_P6_U0_CFG3 0x40010c43 +#define CYDEV_UCFG_B0_P6_U0_CFG4 0x40010c44 +#define CYDEV_UCFG_B0_P6_U0_CFG5 0x40010c45 +#define CYDEV_UCFG_B0_P6_U0_CFG6 0x40010c46 +#define CYDEV_UCFG_B0_P6_U0_CFG7 0x40010c47 +#define CYDEV_UCFG_B0_P6_U0_CFG8 0x40010c48 +#define CYDEV_UCFG_B0_P6_U0_CFG9 0x40010c49 +#define CYDEV_UCFG_B0_P6_U0_CFG10 0x40010c4a +#define CYDEV_UCFG_B0_P6_U0_CFG11 0x40010c4b +#define CYDEV_UCFG_B0_P6_U0_CFG12 0x40010c4c +#define CYDEV_UCFG_B0_P6_U0_CFG13 0x40010c4d +#define CYDEV_UCFG_B0_P6_U0_CFG14 0x40010c4e +#define CYDEV_UCFG_B0_P6_U0_CFG15 0x40010c4f +#define CYDEV_UCFG_B0_P6_U0_CFG16 0x40010c50 +#define CYDEV_UCFG_B0_P6_U0_CFG17 0x40010c51 +#define CYDEV_UCFG_B0_P6_U0_CFG18 0x40010c52 +#define CYDEV_UCFG_B0_P6_U0_CFG19 0x40010c53 +#define CYDEV_UCFG_B0_P6_U0_CFG20 0x40010c54 +#define CYDEV_UCFG_B0_P6_U0_CFG21 0x40010c55 +#define CYDEV_UCFG_B0_P6_U0_CFG22 0x40010c56 +#define CYDEV_UCFG_B0_P6_U0_CFG23 0x40010c57 +#define CYDEV_UCFG_B0_P6_U0_CFG24 0x40010c58 +#define CYDEV_UCFG_B0_P6_U0_CFG25 0x40010c59 +#define CYDEV_UCFG_B0_P6_U0_CFG26 0x40010c5a +#define CYDEV_UCFG_B0_P6_U0_CFG27 0x40010c5b +#define CYDEV_UCFG_B0_P6_U0_CFG28 0x40010c5c +#define CYDEV_UCFG_B0_P6_U0_CFG29 0x40010c5d +#define CYDEV_UCFG_B0_P6_U0_CFG30 0x40010c5e +#define CYDEV_UCFG_B0_P6_U0_CFG31 0x40010c5f +#define CYDEV_UCFG_B0_P6_U0_DCFG0 0x40010c60 +#define CYDEV_UCFG_B0_P6_U0_DCFG1 0x40010c62 +#define CYDEV_UCFG_B0_P6_U0_DCFG2 0x40010c64 +#define CYDEV_UCFG_B0_P6_U0_DCFG3 0x40010c66 +#define CYDEV_UCFG_B0_P6_U0_DCFG4 0x40010c68 +#define CYDEV_UCFG_B0_P6_U0_DCFG5 0x40010c6a +#define CYDEV_UCFG_B0_P6_U0_DCFG6 0x40010c6c +#define CYDEV_UCFG_B0_P6_U0_DCFG7 0x40010c6e +#define CYDEV_UCFG_B0_P6_U1_BASE 0x40010c80 +#define CYDEV_UCFG_B0_P6_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT0 0x40010c80 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT1 0x40010c84 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT2 0x40010c88 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT3 0x40010c8c +#define CYDEV_UCFG_B0_P6_U1_PLD_IT4 0x40010c90 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT5 0x40010c94 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT6 0x40010c98 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT7 0x40010c9c +#define CYDEV_UCFG_B0_P6_U1_PLD_IT8 0x40010ca0 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT9 0x40010ca4 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT10 0x40010ca8 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT11 0x40010cac +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT0 0x40010cb0 +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT1 0x40010cb2 +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT2 0x40010cb4 +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT3 0x40010cb6 +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST 0x40010cb8 +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB 0x40010cba +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET 0x40010cbc +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS 0x40010cbe +#define CYDEV_UCFG_B0_P6_U1_CFG0 0x40010cc0 +#define CYDEV_UCFG_B0_P6_U1_CFG1 0x40010cc1 +#define CYDEV_UCFG_B0_P6_U1_CFG2 0x40010cc2 +#define CYDEV_UCFG_B0_P6_U1_CFG3 0x40010cc3 +#define CYDEV_UCFG_B0_P6_U1_CFG4 0x40010cc4 +#define CYDEV_UCFG_B0_P6_U1_CFG5 0x40010cc5 +#define CYDEV_UCFG_B0_P6_U1_CFG6 0x40010cc6 +#define CYDEV_UCFG_B0_P6_U1_CFG7 0x40010cc7 +#define CYDEV_UCFG_B0_P6_U1_CFG8 0x40010cc8 +#define CYDEV_UCFG_B0_P6_U1_CFG9 0x40010cc9 +#define CYDEV_UCFG_B0_P6_U1_CFG10 0x40010cca +#define CYDEV_UCFG_B0_P6_U1_CFG11 0x40010ccb +#define CYDEV_UCFG_B0_P6_U1_CFG12 0x40010ccc +#define CYDEV_UCFG_B0_P6_U1_CFG13 0x40010ccd +#define CYDEV_UCFG_B0_P6_U1_CFG14 0x40010cce +#define CYDEV_UCFG_B0_P6_U1_CFG15 0x40010ccf +#define CYDEV_UCFG_B0_P6_U1_CFG16 0x40010cd0 +#define CYDEV_UCFG_B0_P6_U1_CFG17 0x40010cd1 +#define CYDEV_UCFG_B0_P6_U1_CFG18 0x40010cd2 +#define CYDEV_UCFG_B0_P6_U1_CFG19 0x40010cd3 +#define CYDEV_UCFG_B0_P6_U1_CFG20 0x40010cd4 +#define CYDEV_UCFG_B0_P6_U1_CFG21 0x40010cd5 +#define CYDEV_UCFG_B0_P6_U1_CFG22 0x40010cd6 +#define CYDEV_UCFG_B0_P6_U1_CFG23 0x40010cd7 +#define CYDEV_UCFG_B0_P6_U1_CFG24 0x40010cd8 +#define CYDEV_UCFG_B0_P6_U1_CFG25 0x40010cd9 +#define CYDEV_UCFG_B0_P6_U1_CFG26 0x40010cda +#define CYDEV_UCFG_B0_P6_U1_CFG27 0x40010cdb +#define CYDEV_UCFG_B0_P6_U1_CFG28 0x40010cdc +#define CYDEV_UCFG_B0_P6_U1_CFG29 0x40010cdd +#define CYDEV_UCFG_B0_P6_U1_CFG30 0x40010cde +#define CYDEV_UCFG_B0_P6_U1_CFG31 0x40010cdf +#define CYDEV_UCFG_B0_P6_U1_DCFG0 0x40010ce0 +#define CYDEV_UCFG_B0_P6_U1_DCFG1 0x40010ce2 +#define CYDEV_UCFG_B0_P6_U1_DCFG2 0x40010ce4 +#define CYDEV_UCFG_B0_P6_U1_DCFG3 0x40010ce6 +#define CYDEV_UCFG_B0_P6_U1_DCFG4 0x40010ce8 +#define CYDEV_UCFG_B0_P6_U1_DCFG5 0x40010cea +#define CYDEV_UCFG_B0_P6_U1_DCFG6 0x40010cec +#define CYDEV_UCFG_B0_P6_U1_DCFG7 0x40010cee +#define CYDEV_UCFG_B0_P6_ROUTE_BASE 0x40010d00 +#define CYDEV_UCFG_B0_P6_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P7_BASE 0x40010e00 +#define CYDEV_UCFG_B0_P7_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P7_U0_BASE 0x40010e00 +#define CYDEV_UCFG_B0_P7_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT0 0x40010e00 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT1 0x40010e04 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT2 0x40010e08 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT3 0x40010e0c +#define CYDEV_UCFG_B0_P7_U0_PLD_IT4 0x40010e10 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT5 0x40010e14 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT6 0x40010e18 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT7 0x40010e1c +#define CYDEV_UCFG_B0_P7_U0_PLD_IT8 0x40010e20 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT9 0x40010e24 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT10 0x40010e28 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT11 0x40010e2c +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT0 0x40010e30 +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT1 0x40010e32 +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT2 0x40010e34 +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT3 0x40010e36 +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST 0x40010e38 +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB 0x40010e3a +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET 0x40010e3c +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS 0x40010e3e +#define CYDEV_UCFG_B0_P7_U0_CFG0 0x40010e40 +#define CYDEV_UCFG_B0_P7_U0_CFG1 0x40010e41 +#define CYDEV_UCFG_B0_P7_U0_CFG2 0x40010e42 +#define CYDEV_UCFG_B0_P7_U0_CFG3 0x40010e43 +#define CYDEV_UCFG_B0_P7_U0_CFG4 0x40010e44 +#define CYDEV_UCFG_B0_P7_U0_CFG5 0x40010e45 +#define CYDEV_UCFG_B0_P7_U0_CFG6 0x40010e46 +#define CYDEV_UCFG_B0_P7_U0_CFG7 0x40010e47 +#define CYDEV_UCFG_B0_P7_U0_CFG8 0x40010e48 +#define CYDEV_UCFG_B0_P7_U0_CFG9 0x40010e49 +#define CYDEV_UCFG_B0_P7_U0_CFG10 0x40010e4a +#define CYDEV_UCFG_B0_P7_U0_CFG11 0x40010e4b +#define CYDEV_UCFG_B0_P7_U0_CFG12 0x40010e4c +#define CYDEV_UCFG_B0_P7_U0_CFG13 0x40010e4d +#define CYDEV_UCFG_B0_P7_U0_CFG14 0x40010e4e +#define CYDEV_UCFG_B0_P7_U0_CFG15 0x40010e4f +#define CYDEV_UCFG_B0_P7_U0_CFG16 0x40010e50 +#define CYDEV_UCFG_B0_P7_U0_CFG17 0x40010e51 +#define CYDEV_UCFG_B0_P7_U0_CFG18 0x40010e52 +#define CYDEV_UCFG_B0_P7_U0_CFG19 0x40010e53 +#define CYDEV_UCFG_B0_P7_U0_CFG20 0x40010e54 +#define CYDEV_UCFG_B0_P7_U0_CFG21 0x40010e55 +#define CYDEV_UCFG_B0_P7_U0_CFG22 0x40010e56 +#define CYDEV_UCFG_B0_P7_U0_CFG23 0x40010e57 +#define CYDEV_UCFG_B0_P7_U0_CFG24 0x40010e58 +#define CYDEV_UCFG_B0_P7_U0_CFG25 0x40010e59 +#define CYDEV_UCFG_B0_P7_U0_CFG26 0x40010e5a +#define CYDEV_UCFG_B0_P7_U0_CFG27 0x40010e5b +#define CYDEV_UCFG_B0_P7_U0_CFG28 0x40010e5c +#define CYDEV_UCFG_B0_P7_U0_CFG29 0x40010e5d +#define CYDEV_UCFG_B0_P7_U0_CFG30 0x40010e5e +#define CYDEV_UCFG_B0_P7_U0_CFG31 0x40010e5f +#define CYDEV_UCFG_B0_P7_U0_DCFG0 0x40010e60 +#define CYDEV_UCFG_B0_P7_U0_DCFG1 0x40010e62 +#define CYDEV_UCFG_B0_P7_U0_DCFG2 0x40010e64 +#define CYDEV_UCFG_B0_P7_U0_DCFG3 0x40010e66 +#define CYDEV_UCFG_B0_P7_U0_DCFG4 0x40010e68 +#define CYDEV_UCFG_B0_P7_U0_DCFG5 0x40010e6a +#define CYDEV_UCFG_B0_P7_U0_DCFG6 0x40010e6c +#define CYDEV_UCFG_B0_P7_U0_DCFG7 0x40010e6e +#define CYDEV_UCFG_B0_P7_U1_BASE 0x40010e80 +#define CYDEV_UCFG_B0_P7_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT0 0x40010e80 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT1 0x40010e84 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT2 0x40010e88 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT3 0x40010e8c +#define CYDEV_UCFG_B0_P7_U1_PLD_IT4 0x40010e90 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT5 0x40010e94 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT6 0x40010e98 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT7 0x40010e9c +#define CYDEV_UCFG_B0_P7_U1_PLD_IT8 0x40010ea0 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT9 0x40010ea4 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT10 0x40010ea8 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT11 0x40010eac +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT0 0x40010eb0 +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT1 0x40010eb2 +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT2 0x40010eb4 +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT3 0x40010eb6 +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST 0x40010eb8 +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB 0x40010eba +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET 0x40010ebc +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS 0x40010ebe +#define CYDEV_UCFG_B0_P7_U1_CFG0 0x40010ec0 +#define CYDEV_UCFG_B0_P7_U1_CFG1 0x40010ec1 +#define CYDEV_UCFG_B0_P7_U1_CFG2 0x40010ec2 +#define CYDEV_UCFG_B0_P7_U1_CFG3 0x40010ec3 +#define CYDEV_UCFG_B0_P7_U1_CFG4 0x40010ec4 +#define CYDEV_UCFG_B0_P7_U1_CFG5 0x40010ec5 +#define CYDEV_UCFG_B0_P7_U1_CFG6 0x40010ec6 +#define CYDEV_UCFG_B0_P7_U1_CFG7 0x40010ec7 +#define CYDEV_UCFG_B0_P7_U1_CFG8 0x40010ec8 +#define CYDEV_UCFG_B0_P7_U1_CFG9 0x40010ec9 +#define CYDEV_UCFG_B0_P7_U1_CFG10 0x40010eca +#define CYDEV_UCFG_B0_P7_U1_CFG11 0x40010ecb +#define CYDEV_UCFG_B0_P7_U1_CFG12 0x40010ecc +#define CYDEV_UCFG_B0_P7_U1_CFG13 0x40010ecd +#define CYDEV_UCFG_B0_P7_U1_CFG14 0x40010ece +#define CYDEV_UCFG_B0_P7_U1_CFG15 0x40010ecf +#define CYDEV_UCFG_B0_P7_U1_CFG16 0x40010ed0 +#define CYDEV_UCFG_B0_P7_U1_CFG17 0x40010ed1 +#define CYDEV_UCFG_B0_P7_U1_CFG18 0x40010ed2 +#define CYDEV_UCFG_B0_P7_U1_CFG19 0x40010ed3 +#define CYDEV_UCFG_B0_P7_U1_CFG20 0x40010ed4 +#define CYDEV_UCFG_B0_P7_U1_CFG21 0x40010ed5 +#define CYDEV_UCFG_B0_P7_U1_CFG22 0x40010ed6 +#define CYDEV_UCFG_B0_P7_U1_CFG23 0x40010ed7 +#define CYDEV_UCFG_B0_P7_U1_CFG24 0x40010ed8 +#define CYDEV_UCFG_B0_P7_U1_CFG25 0x40010ed9 +#define CYDEV_UCFG_B0_P7_U1_CFG26 0x40010eda +#define CYDEV_UCFG_B0_P7_U1_CFG27 0x40010edb +#define CYDEV_UCFG_B0_P7_U1_CFG28 0x40010edc +#define CYDEV_UCFG_B0_P7_U1_CFG29 0x40010edd +#define CYDEV_UCFG_B0_P7_U1_CFG30 0x40010ede +#define CYDEV_UCFG_B0_P7_U1_CFG31 0x40010edf +#define CYDEV_UCFG_B0_P7_U1_DCFG0 0x40010ee0 +#define CYDEV_UCFG_B0_P7_U1_DCFG1 0x40010ee2 +#define CYDEV_UCFG_B0_P7_U1_DCFG2 0x40010ee4 +#define CYDEV_UCFG_B0_P7_U1_DCFG3 0x40010ee6 +#define CYDEV_UCFG_B0_P7_U1_DCFG4 0x40010ee8 +#define CYDEV_UCFG_B0_P7_U1_DCFG5 0x40010eea +#define CYDEV_UCFG_B0_P7_U1_DCFG6 0x40010eec +#define CYDEV_UCFG_B0_P7_U1_DCFG7 0x40010eee +#define CYDEV_UCFG_B0_P7_ROUTE_BASE 0x40010f00 +#define CYDEV_UCFG_B0_P7_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B1_BASE 0x40011000 +#define CYDEV_UCFG_B1_SIZE 0x00000fef +#define CYDEV_UCFG_B1_P2_BASE 0x40011400 +#define CYDEV_UCFG_B1_P2_SIZE 0x000001ef +#define CYDEV_UCFG_B1_P2_U0_BASE 0x40011400 +#define CYDEV_UCFG_B1_P2_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT0 0x40011400 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT1 0x40011404 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT2 0x40011408 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT3 0x4001140c +#define CYDEV_UCFG_B1_P2_U0_PLD_IT4 0x40011410 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT5 0x40011414 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT6 0x40011418 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT7 0x4001141c +#define CYDEV_UCFG_B1_P2_U0_PLD_IT8 0x40011420 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT9 0x40011424 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT10 0x40011428 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT11 0x4001142c +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT0 0x40011430 +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT1 0x40011432 +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT2 0x40011434 +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT3 0x40011436 +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST 0x40011438 +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB 0x4001143a +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET 0x4001143c +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS 0x4001143e +#define CYDEV_UCFG_B1_P2_U0_CFG0 0x40011440 +#define CYDEV_UCFG_B1_P2_U0_CFG1 0x40011441 +#define CYDEV_UCFG_B1_P2_U0_CFG2 0x40011442 +#define CYDEV_UCFG_B1_P2_U0_CFG3 0x40011443 +#define CYDEV_UCFG_B1_P2_U0_CFG4 0x40011444 +#define CYDEV_UCFG_B1_P2_U0_CFG5 0x40011445 +#define CYDEV_UCFG_B1_P2_U0_CFG6 0x40011446 +#define CYDEV_UCFG_B1_P2_U0_CFG7 0x40011447 +#define CYDEV_UCFG_B1_P2_U0_CFG8 0x40011448 +#define CYDEV_UCFG_B1_P2_U0_CFG9 0x40011449 +#define CYDEV_UCFG_B1_P2_U0_CFG10 0x4001144a +#define CYDEV_UCFG_B1_P2_U0_CFG11 0x4001144b +#define CYDEV_UCFG_B1_P2_U0_CFG12 0x4001144c +#define CYDEV_UCFG_B1_P2_U0_CFG13 0x4001144d +#define CYDEV_UCFG_B1_P2_U0_CFG14 0x4001144e +#define CYDEV_UCFG_B1_P2_U0_CFG15 0x4001144f +#define CYDEV_UCFG_B1_P2_U0_CFG16 0x40011450 +#define CYDEV_UCFG_B1_P2_U0_CFG17 0x40011451 +#define CYDEV_UCFG_B1_P2_U0_CFG18 0x40011452 +#define CYDEV_UCFG_B1_P2_U0_CFG19 0x40011453 +#define CYDEV_UCFG_B1_P2_U0_CFG20 0x40011454 +#define CYDEV_UCFG_B1_P2_U0_CFG21 0x40011455 +#define CYDEV_UCFG_B1_P2_U0_CFG22 0x40011456 +#define CYDEV_UCFG_B1_P2_U0_CFG23 0x40011457 +#define CYDEV_UCFG_B1_P2_U0_CFG24 0x40011458 +#define CYDEV_UCFG_B1_P2_U0_CFG25 0x40011459 +#define CYDEV_UCFG_B1_P2_U0_CFG26 0x4001145a +#define CYDEV_UCFG_B1_P2_U0_CFG27 0x4001145b +#define CYDEV_UCFG_B1_P2_U0_CFG28 0x4001145c +#define CYDEV_UCFG_B1_P2_U0_CFG29 0x4001145d +#define CYDEV_UCFG_B1_P2_U0_CFG30 0x4001145e +#define CYDEV_UCFG_B1_P2_U0_CFG31 0x4001145f +#define CYDEV_UCFG_B1_P2_U0_DCFG0 0x40011460 +#define CYDEV_UCFG_B1_P2_U0_DCFG1 0x40011462 +#define CYDEV_UCFG_B1_P2_U0_DCFG2 0x40011464 +#define CYDEV_UCFG_B1_P2_U0_DCFG3 0x40011466 +#define CYDEV_UCFG_B1_P2_U0_DCFG4 0x40011468 +#define CYDEV_UCFG_B1_P2_U0_DCFG5 0x4001146a +#define CYDEV_UCFG_B1_P2_U0_DCFG6 0x4001146c +#define CYDEV_UCFG_B1_P2_U0_DCFG7 0x4001146e +#define CYDEV_UCFG_B1_P2_U1_BASE 0x40011480 +#define CYDEV_UCFG_B1_P2_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT0 0x40011480 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT1 0x40011484 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT2 0x40011488 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT3 0x4001148c +#define CYDEV_UCFG_B1_P2_U1_PLD_IT4 0x40011490 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT5 0x40011494 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT6 0x40011498 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT7 0x4001149c +#define CYDEV_UCFG_B1_P2_U1_PLD_IT8 0x400114a0 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT9 0x400114a4 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT10 0x400114a8 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT11 0x400114ac +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT0 0x400114b0 +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT1 0x400114b2 +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT2 0x400114b4 +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT3 0x400114b6 +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST 0x400114b8 +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB 0x400114ba +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET 0x400114bc +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS 0x400114be +#define CYDEV_UCFG_B1_P2_U1_CFG0 0x400114c0 +#define CYDEV_UCFG_B1_P2_U1_CFG1 0x400114c1 +#define CYDEV_UCFG_B1_P2_U1_CFG2 0x400114c2 +#define CYDEV_UCFG_B1_P2_U1_CFG3 0x400114c3 +#define CYDEV_UCFG_B1_P2_U1_CFG4 0x400114c4 +#define CYDEV_UCFG_B1_P2_U1_CFG5 0x400114c5 +#define CYDEV_UCFG_B1_P2_U1_CFG6 0x400114c6 +#define CYDEV_UCFG_B1_P2_U1_CFG7 0x400114c7 +#define CYDEV_UCFG_B1_P2_U1_CFG8 0x400114c8 +#define CYDEV_UCFG_B1_P2_U1_CFG9 0x400114c9 +#define CYDEV_UCFG_B1_P2_U1_CFG10 0x400114ca +#define CYDEV_UCFG_B1_P2_U1_CFG11 0x400114cb +#define CYDEV_UCFG_B1_P2_U1_CFG12 0x400114cc +#define CYDEV_UCFG_B1_P2_U1_CFG13 0x400114cd +#define CYDEV_UCFG_B1_P2_U1_CFG14 0x400114ce +#define CYDEV_UCFG_B1_P2_U1_CFG15 0x400114cf +#define CYDEV_UCFG_B1_P2_U1_CFG16 0x400114d0 +#define CYDEV_UCFG_B1_P2_U1_CFG17 0x400114d1 +#define CYDEV_UCFG_B1_P2_U1_CFG18 0x400114d2 +#define CYDEV_UCFG_B1_P2_U1_CFG19 0x400114d3 +#define CYDEV_UCFG_B1_P2_U1_CFG20 0x400114d4 +#define CYDEV_UCFG_B1_P2_U1_CFG21 0x400114d5 +#define CYDEV_UCFG_B1_P2_U1_CFG22 0x400114d6 +#define CYDEV_UCFG_B1_P2_U1_CFG23 0x400114d7 +#define CYDEV_UCFG_B1_P2_U1_CFG24 0x400114d8 +#define CYDEV_UCFG_B1_P2_U1_CFG25 0x400114d9 +#define CYDEV_UCFG_B1_P2_U1_CFG26 0x400114da +#define CYDEV_UCFG_B1_P2_U1_CFG27 0x400114db +#define CYDEV_UCFG_B1_P2_U1_CFG28 0x400114dc +#define CYDEV_UCFG_B1_P2_U1_CFG29 0x400114dd +#define CYDEV_UCFG_B1_P2_U1_CFG30 0x400114de +#define CYDEV_UCFG_B1_P2_U1_CFG31 0x400114df +#define CYDEV_UCFG_B1_P2_U1_DCFG0 0x400114e0 +#define CYDEV_UCFG_B1_P2_U1_DCFG1 0x400114e2 +#define CYDEV_UCFG_B1_P2_U1_DCFG2 0x400114e4 +#define CYDEV_UCFG_B1_P2_U1_DCFG3 0x400114e6 +#define CYDEV_UCFG_B1_P2_U1_DCFG4 0x400114e8 +#define CYDEV_UCFG_B1_P2_U1_DCFG5 0x400114ea +#define CYDEV_UCFG_B1_P2_U1_DCFG6 0x400114ec +#define CYDEV_UCFG_B1_P2_U1_DCFG7 0x400114ee +#define CYDEV_UCFG_B1_P2_ROUTE_BASE 0x40011500 +#define CYDEV_UCFG_B1_P2_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B1_P3_BASE 0x40011600 +#define CYDEV_UCFG_B1_P3_SIZE 0x000001ef +#define CYDEV_UCFG_B1_P3_U0_BASE 0x40011600 +#define CYDEV_UCFG_B1_P3_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT0 0x40011600 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT1 0x40011604 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT2 0x40011608 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT3 0x4001160c +#define CYDEV_UCFG_B1_P3_U0_PLD_IT4 0x40011610 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT5 0x40011614 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT6 0x40011618 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT7 0x4001161c +#define CYDEV_UCFG_B1_P3_U0_PLD_IT8 0x40011620 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT9 0x40011624 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT10 0x40011628 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT11 0x4001162c +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT0 0x40011630 +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT1 0x40011632 +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT2 0x40011634 +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT3 0x40011636 +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST 0x40011638 +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB 0x4001163a +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET 0x4001163c +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS 0x4001163e +#define CYDEV_UCFG_B1_P3_U0_CFG0 0x40011640 +#define CYDEV_UCFG_B1_P3_U0_CFG1 0x40011641 +#define CYDEV_UCFG_B1_P3_U0_CFG2 0x40011642 +#define CYDEV_UCFG_B1_P3_U0_CFG3 0x40011643 +#define CYDEV_UCFG_B1_P3_U0_CFG4 0x40011644 +#define CYDEV_UCFG_B1_P3_U0_CFG5 0x40011645 +#define CYDEV_UCFG_B1_P3_U0_CFG6 0x40011646 +#define CYDEV_UCFG_B1_P3_U0_CFG7 0x40011647 +#define CYDEV_UCFG_B1_P3_U0_CFG8 0x40011648 +#define CYDEV_UCFG_B1_P3_U0_CFG9 0x40011649 +#define CYDEV_UCFG_B1_P3_U0_CFG10 0x4001164a +#define CYDEV_UCFG_B1_P3_U0_CFG11 0x4001164b +#define CYDEV_UCFG_B1_P3_U0_CFG12 0x4001164c +#define CYDEV_UCFG_B1_P3_U0_CFG13 0x4001164d +#define CYDEV_UCFG_B1_P3_U0_CFG14 0x4001164e +#define CYDEV_UCFG_B1_P3_U0_CFG15 0x4001164f +#define CYDEV_UCFG_B1_P3_U0_CFG16 0x40011650 +#define CYDEV_UCFG_B1_P3_U0_CFG17 0x40011651 +#define CYDEV_UCFG_B1_P3_U0_CFG18 0x40011652 +#define CYDEV_UCFG_B1_P3_U0_CFG19 0x40011653 +#define CYDEV_UCFG_B1_P3_U0_CFG20 0x40011654 +#define CYDEV_UCFG_B1_P3_U0_CFG21 0x40011655 +#define CYDEV_UCFG_B1_P3_U0_CFG22 0x40011656 +#define CYDEV_UCFG_B1_P3_U0_CFG23 0x40011657 +#define CYDEV_UCFG_B1_P3_U0_CFG24 0x40011658 +#define CYDEV_UCFG_B1_P3_U0_CFG25 0x40011659 +#define CYDEV_UCFG_B1_P3_U0_CFG26 0x4001165a +#define CYDEV_UCFG_B1_P3_U0_CFG27 0x4001165b +#define CYDEV_UCFG_B1_P3_U0_CFG28 0x4001165c +#define CYDEV_UCFG_B1_P3_U0_CFG29 0x4001165d +#define CYDEV_UCFG_B1_P3_U0_CFG30 0x4001165e +#define CYDEV_UCFG_B1_P3_U0_CFG31 0x4001165f +#define CYDEV_UCFG_B1_P3_U0_DCFG0 0x40011660 +#define CYDEV_UCFG_B1_P3_U0_DCFG1 0x40011662 +#define CYDEV_UCFG_B1_P3_U0_DCFG2 0x40011664 +#define CYDEV_UCFG_B1_P3_U0_DCFG3 0x40011666 +#define CYDEV_UCFG_B1_P3_U0_DCFG4 0x40011668 +#define CYDEV_UCFG_B1_P3_U0_DCFG5 0x4001166a +#define CYDEV_UCFG_B1_P3_U0_DCFG6 0x4001166c +#define CYDEV_UCFG_B1_P3_U0_DCFG7 0x4001166e +#define CYDEV_UCFG_B1_P3_U1_BASE 0x40011680 +#define CYDEV_UCFG_B1_P3_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT0 0x40011680 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT1 0x40011684 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT2 0x40011688 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT3 0x4001168c +#define CYDEV_UCFG_B1_P3_U1_PLD_IT4 0x40011690 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT5 0x40011694 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT6 0x40011698 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT7 0x4001169c +#define CYDEV_UCFG_B1_P3_U1_PLD_IT8 0x400116a0 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT9 0x400116a4 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT10 0x400116a8 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT11 0x400116ac +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT0 0x400116b0 +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT1 0x400116b2 +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT2 0x400116b4 +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT3 0x400116b6 +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST 0x400116b8 +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB 0x400116ba +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET 0x400116bc +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS 0x400116be +#define CYDEV_UCFG_B1_P3_U1_CFG0 0x400116c0 +#define CYDEV_UCFG_B1_P3_U1_CFG1 0x400116c1 +#define CYDEV_UCFG_B1_P3_U1_CFG2 0x400116c2 +#define CYDEV_UCFG_B1_P3_U1_CFG3 0x400116c3 +#define CYDEV_UCFG_B1_P3_U1_CFG4 0x400116c4 +#define CYDEV_UCFG_B1_P3_U1_CFG5 0x400116c5 +#define CYDEV_UCFG_B1_P3_U1_CFG6 0x400116c6 +#define CYDEV_UCFG_B1_P3_U1_CFG7 0x400116c7 +#define CYDEV_UCFG_B1_P3_U1_CFG8 0x400116c8 +#define CYDEV_UCFG_B1_P3_U1_CFG9 0x400116c9 +#define CYDEV_UCFG_B1_P3_U1_CFG10 0x400116ca +#define CYDEV_UCFG_B1_P3_U1_CFG11 0x400116cb +#define CYDEV_UCFG_B1_P3_U1_CFG12 0x400116cc +#define CYDEV_UCFG_B1_P3_U1_CFG13 0x400116cd +#define CYDEV_UCFG_B1_P3_U1_CFG14 0x400116ce +#define CYDEV_UCFG_B1_P3_U1_CFG15 0x400116cf +#define CYDEV_UCFG_B1_P3_U1_CFG16 0x400116d0 +#define CYDEV_UCFG_B1_P3_U1_CFG17 0x400116d1 +#define CYDEV_UCFG_B1_P3_U1_CFG18 0x400116d2 +#define CYDEV_UCFG_B1_P3_U1_CFG19 0x400116d3 +#define CYDEV_UCFG_B1_P3_U1_CFG20 0x400116d4 +#define CYDEV_UCFG_B1_P3_U1_CFG21 0x400116d5 +#define CYDEV_UCFG_B1_P3_U1_CFG22 0x400116d6 +#define CYDEV_UCFG_B1_P3_U1_CFG23 0x400116d7 +#define CYDEV_UCFG_B1_P3_U1_CFG24 0x400116d8 +#define CYDEV_UCFG_B1_P3_U1_CFG25 0x400116d9 +#define CYDEV_UCFG_B1_P3_U1_CFG26 0x400116da +#define CYDEV_UCFG_B1_P3_U1_CFG27 0x400116db +#define CYDEV_UCFG_B1_P3_U1_CFG28 0x400116dc +#define CYDEV_UCFG_B1_P3_U1_CFG29 0x400116dd +#define CYDEV_UCFG_B1_P3_U1_CFG30 0x400116de +#define CYDEV_UCFG_B1_P3_U1_CFG31 0x400116df +#define CYDEV_UCFG_B1_P3_U1_DCFG0 0x400116e0 +#define CYDEV_UCFG_B1_P3_U1_DCFG1 0x400116e2 +#define CYDEV_UCFG_B1_P3_U1_DCFG2 0x400116e4 +#define CYDEV_UCFG_B1_P3_U1_DCFG3 0x400116e6 +#define CYDEV_UCFG_B1_P3_U1_DCFG4 0x400116e8 +#define CYDEV_UCFG_B1_P3_U1_DCFG5 0x400116ea +#define CYDEV_UCFG_B1_P3_U1_DCFG6 0x400116ec +#define CYDEV_UCFG_B1_P3_U1_DCFG7 0x400116ee +#define CYDEV_UCFG_B1_P3_ROUTE_BASE 0x40011700 +#define CYDEV_UCFG_B1_P3_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B1_P4_BASE 0x40011800 +#define CYDEV_UCFG_B1_P4_SIZE 0x000001ef +#define CYDEV_UCFG_B1_P4_U0_BASE 0x40011800 +#define CYDEV_UCFG_B1_P4_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT0 0x40011800 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT1 0x40011804 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT2 0x40011808 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT3 0x4001180c +#define CYDEV_UCFG_B1_P4_U0_PLD_IT4 0x40011810 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT5 0x40011814 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT6 0x40011818 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT7 0x4001181c +#define CYDEV_UCFG_B1_P4_U0_PLD_IT8 0x40011820 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT9 0x40011824 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT10 0x40011828 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT11 0x4001182c +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT0 0x40011830 +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT1 0x40011832 +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT2 0x40011834 +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT3 0x40011836 +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST 0x40011838 +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB 0x4001183a +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET 0x4001183c +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS 0x4001183e +#define CYDEV_UCFG_B1_P4_U0_CFG0 0x40011840 +#define CYDEV_UCFG_B1_P4_U0_CFG1 0x40011841 +#define CYDEV_UCFG_B1_P4_U0_CFG2 0x40011842 +#define CYDEV_UCFG_B1_P4_U0_CFG3 0x40011843 +#define CYDEV_UCFG_B1_P4_U0_CFG4 0x40011844 +#define CYDEV_UCFG_B1_P4_U0_CFG5 0x40011845 +#define CYDEV_UCFG_B1_P4_U0_CFG6 0x40011846 +#define CYDEV_UCFG_B1_P4_U0_CFG7 0x40011847 +#define CYDEV_UCFG_B1_P4_U0_CFG8 0x40011848 +#define CYDEV_UCFG_B1_P4_U0_CFG9 0x40011849 +#define CYDEV_UCFG_B1_P4_U0_CFG10 0x4001184a +#define CYDEV_UCFG_B1_P4_U0_CFG11 0x4001184b +#define CYDEV_UCFG_B1_P4_U0_CFG12 0x4001184c +#define CYDEV_UCFG_B1_P4_U0_CFG13 0x4001184d +#define CYDEV_UCFG_B1_P4_U0_CFG14 0x4001184e +#define CYDEV_UCFG_B1_P4_U0_CFG15 0x4001184f +#define CYDEV_UCFG_B1_P4_U0_CFG16 0x40011850 +#define CYDEV_UCFG_B1_P4_U0_CFG17 0x40011851 +#define CYDEV_UCFG_B1_P4_U0_CFG18 0x40011852 +#define CYDEV_UCFG_B1_P4_U0_CFG19 0x40011853 +#define CYDEV_UCFG_B1_P4_U0_CFG20 0x40011854 +#define CYDEV_UCFG_B1_P4_U0_CFG21 0x40011855 +#define CYDEV_UCFG_B1_P4_U0_CFG22 0x40011856 +#define CYDEV_UCFG_B1_P4_U0_CFG23 0x40011857 +#define CYDEV_UCFG_B1_P4_U0_CFG24 0x40011858 +#define CYDEV_UCFG_B1_P4_U0_CFG25 0x40011859 +#define CYDEV_UCFG_B1_P4_U0_CFG26 0x4001185a +#define CYDEV_UCFG_B1_P4_U0_CFG27 0x4001185b +#define CYDEV_UCFG_B1_P4_U0_CFG28 0x4001185c +#define CYDEV_UCFG_B1_P4_U0_CFG29 0x4001185d +#define CYDEV_UCFG_B1_P4_U0_CFG30 0x4001185e +#define CYDEV_UCFG_B1_P4_U0_CFG31 0x4001185f +#define CYDEV_UCFG_B1_P4_U0_DCFG0 0x40011860 +#define CYDEV_UCFG_B1_P4_U0_DCFG1 0x40011862 +#define CYDEV_UCFG_B1_P4_U0_DCFG2 0x40011864 +#define CYDEV_UCFG_B1_P4_U0_DCFG3 0x40011866 +#define CYDEV_UCFG_B1_P4_U0_DCFG4 0x40011868 +#define CYDEV_UCFG_B1_P4_U0_DCFG5 0x4001186a +#define CYDEV_UCFG_B1_P4_U0_DCFG6 0x4001186c +#define CYDEV_UCFG_B1_P4_U0_DCFG7 0x4001186e +#define CYDEV_UCFG_B1_P4_U1_BASE 0x40011880 +#define CYDEV_UCFG_B1_P4_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT0 0x40011880 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT1 0x40011884 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT2 0x40011888 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT3 0x4001188c +#define CYDEV_UCFG_B1_P4_U1_PLD_IT4 0x40011890 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT5 0x40011894 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT6 0x40011898 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT7 0x4001189c +#define CYDEV_UCFG_B1_P4_U1_PLD_IT8 0x400118a0 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT9 0x400118a4 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT10 0x400118a8 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT11 0x400118ac +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT0 0x400118b0 +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT1 0x400118b2 +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT2 0x400118b4 +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT3 0x400118b6 +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST 0x400118b8 +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB 0x400118ba +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET 0x400118bc +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS 0x400118be +#define CYDEV_UCFG_B1_P4_U1_CFG0 0x400118c0 +#define CYDEV_UCFG_B1_P4_U1_CFG1 0x400118c1 +#define CYDEV_UCFG_B1_P4_U1_CFG2 0x400118c2 +#define CYDEV_UCFG_B1_P4_U1_CFG3 0x400118c3 +#define CYDEV_UCFG_B1_P4_U1_CFG4 0x400118c4 +#define CYDEV_UCFG_B1_P4_U1_CFG5 0x400118c5 +#define CYDEV_UCFG_B1_P4_U1_CFG6 0x400118c6 +#define CYDEV_UCFG_B1_P4_U1_CFG7 0x400118c7 +#define CYDEV_UCFG_B1_P4_U1_CFG8 0x400118c8 +#define CYDEV_UCFG_B1_P4_U1_CFG9 0x400118c9 +#define CYDEV_UCFG_B1_P4_U1_CFG10 0x400118ca +#define CYDEV_UCFG_B1_P4_U1_CFG11 0x400118cb +#define CYDEV_UCFG_B1_P4_U1_CFG12 0x400118cc +#define CYDEV_UCFG_B1_P4_U1_CFG13 0x400118cd +#define CYDEV_UCFG_B1_P4_U1_CFG14 0x400118ce +#define CYDEV_UCFG_B1_P4_U1_CFG15 0x400118cf +#define CYDEV_UCFG_B1_P4_U1_CFG16 0x400118d0 +#define CYDEV_UCFG_B1_P4_U1_CFG17 0x400118d1 +#define CYDEV_UCFG_B1_P4_U1_CFG18 0x400118d2 +#define CYDEV_UCFG_B1_P4_U1_CFG19 0x400118d3 +#define CYDEV_UCFG_B1_P4_U1_CFG20 0x400118d4 +#define CYDEV_UCFG_B1_P4_U1_CFG21 0x400118d5 +#define CYDEV_UCFG_B1_P4_U1_CFG22 0x400118d6 +#define CYDEV_UCFG_B1_P4_U1_CFG23 0x400118d7 +#define CYDEV_UCFG_B1_P4_U1_CFG24 0x400118d8 +#define CYDEV_UCFG_B1_P4_U1_CFG25 0x400118d9 +#define CYDEV_UCFG_B1_P4_U1_CFG26 0x400118da +#define CYDEV_UCFG_B1_P4_U1_CFG27 0x400118db +#define CYDEV_UCFG_B1_P4_U1_CFG28 0x400118dc +#define CYDEV_UCFG_B1_P4_U1_CFG29 0x400118dd +#define CYDEV_UCFG_B1_P4_U1_CFG30 0x400118de +#define CYDEV_UCFG_B1_P4_U1_CFG31 0x400118df +#define CYDEV_UCFG_B1_P4_U1_DCFG0 0x400118e0 +#define CYDEV_UCFG_B1_P4_U1_DCFG1 0x400118e2 +#define CYDEV_UCFG_B1_P4_U1_DCFG2 0x400118e4 +#define CYDEV_UCFG_B1_P4_U1_DCFG3 0x400118e6 +#define CYDEV_UCFG_B1_P4_U1_DCFG4 0x400118e8 +#define CYDEV_UCFG_B1_P4_U1_DCFG5 0x400118ea +#define CYDEV_UCFG_B1_P4_U1_DCFG6 0x400118ec +#define CYDEV_UCFG_B1_P4_U1_DCFG7 0x400118ee +#define CYDEV_UCFG_B1_P4_ROUTE_BASE 0x40011900 +#define CYDEV_UCFG_B1_P4_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B1_P5_BASE 0x40011a00 +#define CYDEV_UCFG_B1_P5_SIZE 0x000001ef +#define CYDEV_UCFG_B1_P5_U0_BASE 0x40011a00 +#define CYDEV_UCFG_B1_P5_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT0 0x40011a00 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT1 0x40011a04 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT2 0x40011a08 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT3 0x40011a0c +#define CYDEV_UCFG_B1_P5_U0_PLD_IT4 0x40011a10 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT5 0x40011a14 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT6 0x40011a18 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT7 0x40011a1c +#define CYDEV_UCFG_B1_P5_U0_PLD_IT8 0x40011a20 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT9 0x40011a24 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT10 0x40011a28 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT11 0x40011a2c +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT0 0x40011a30 +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT1 0x40011a32 +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT2 0x40011a34 +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT3 0x40011a36 +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST 0x40011a38 +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB 0x40011a3a +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET 0x40011a3c +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS 0x40011a3e +#define CYDEV_UCFG_B1_P5_U0_CFG0 0x40011a40 +#define CYDEV_UCFG_B1_P5_U0_CFG1 0x40011a41 +#define CYDEV_UCFG_B1_P5_U0_CFG2 0x40011a42 +#define CYDEV_UCFG_B1_P5_U0_CFG3 0x40011a43 +#define CYDEV_UCFG_B1_P5_U0_CFG4 0x40011a44 +#define CYDEV_UCFG_B1_P5_U0_CFG5 0x40011a45 +#define CYDEV_UCFG_B1_P5_U0_CFG6 0x40011a46 +#define CYDEV_UCFG_B1_P5_U0_CFG7 0x40011a47 +#define CYDEV_UCFG_B1_P5_U0_CFG8 0x40011a48 +#define CYDEV_UCFG_B1_P5_U0_CFG9 0x40011a49 +#define CYDEV_UCFG_B1_P5_U0_CFG10 0x40011a4a +#define CYDEV_UCFG_B1_P5_U0_CFG11 0x40011a4b +#define CYDEV_UCFG_B1_P5_U0_CFG12 0x40011a4c +#define CYDEV_UCFG_B1_P5_U0_CFG13 0x40011a4d +#define CYDEV_UCFG_B1_P5_U0_CFG14 0x40011a4e +#define CYDEV_UCFG_B1_P5_U0_CFG15 0x40011a4f +#define CYDEV_UCFG_B1_P5_U0_CFG16 0x40011a50 +#define CYDEV_UCFG_B1_P5_U0_CFG17 0x40011a51 +#define CYDEV_UCFG_B1_P5_U0_CFG18 0x40011a52 +#define CYDEV_UCFG_B1_P5_U0_CFG19 0x40011a53 +#define CYDEV_UCFG_B1_P5_U0_CFG20 0x40011a54 +#define CYDEV_UCFG_B1_P5_U0_CFG21 0x40011a55 +#define CYDEV_UCFG_B1_P5_U0_CFG22 0x40011a56 +#define CYDEV_UCFG_B1_P5_U0_CFG23 0x40011a57 +#define CYDEV_UCFG_B1_P5_U0_CFG24 0x40011a58 +#define CYDEV_UCFG_B1_P5_U0_CFG25 0x40011a59 +#define CYDEV_UCFG_B1_P5_U0_CFG26 0x40011a5a +#define CYDEV_UCFG_B1_P5_U0_CFG27 0x40011a5b +#define CYDEV_UCFG_B1_P5_U0_CFG28 0x40011a5c +#define CYDEV_UCFG_B1_P5_U0_CFG29 0x40011a5d +#define CYDEV_UCFG_B1_P5_U0_CFG30 0x40011a5e +#define CYDEV_UCFG_B1_P5_U0_CFG31 0x40011a5f +#define CYDEV_UCFG_B1_P5_U0_DCFG0 0x40011a60 +#define CYDEV_UCFG_B1_P5_U0_DCFG1 0x40011a62 +#define CYDEV_UCFG_B1_P5_U0_DCFG2 0x40011a64 +#define CYDEV_UCFG_B1_P5_U0_DCFG3 0x40011a66 +#define CYDEV_UCFG_B1_P5_U0_DCFG4 0x40011a68 +#define CYDEV_UCFG_B1_P5_U0_DCFG5 0x40011a6a +#define CYDEV_UCFG_B1_P5_U0_DCFG6 0x40011a6c +#define CYDEV_UCFG_B1_P5_U0_DCFG7 0x40011a6e +#define CYDEV_UCFG_B1_P5_U1_BASE 0x40011a80 +#define CYDEV_UCFG_B1_P5_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT0 0x40011a80 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT1 0x40011a84 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT2 0x40011a88 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT3 0x40011a8c +#define CYDEV_UCFG_B1_P5_U1_PLD_IT4 0x40011a90 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT5 0x40011a94 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT6 0x40011a98 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT7 0x40011a9c +#define CYDEV_UCFG_B1_P5_U1_PLD_IT8 0x40011aa0 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT9 0x40011aa4 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT10 0x40011aa8 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT11 0x40011aac +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT0 0x40011ab0 +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT1 0x40011ab2 +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT2 0x40011ab4 +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT3 0x40011ab6 +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST 0x40011ab8 +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB 0x40011aba +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET 0x40011abc +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS 0x40011abe +#define CYDEV_UCFG_B1_P5_U1_CFG0 0x40011ac0 +#define CYDEV_UCFG_B1_P5_U1_CFG1 0x40011ac1 +#define CYDEV_UCFG_B1_P5_U1_CFG2 0x40011ac2 +#define CYDEV_UCFG_B1_P5_U1_CFG3 0x40011ac3 +#define CYDEV_UCFG_B1_P5_U1_CFG4 0x40011ac4 +#define CYDEV_UCFG_B1_P5_U1_CFG5 0x40011ac5 +#define CYDEV_UCFG_B1_P5_U1_CFG6 0x40011ac6 +#define CYDEV_UCFG_B1_P5_U1_CFG7 0x40011ac7 +#define CYDEV_UCFG_B1_P5_U1_CFG8 0x40011ac8 +#define CYDEV_UCFG_B1_P5_U1_CFG9 0x40011ac9 +#define CYDEV_UCFG_B1_P5_U1_CFG10 0x40011aca +#define CYDEV_UCFG_B1_P5_U1_CFG11 0x40011acb +#define CYDEV_UCFG_B1_P5_U1_CFG12 0x40011acc +#define CYDEV_UCFG_B1_P5_U1_CFG13 0x40011acd +#define CYDEV_UCFG_B1_P5_U1_CFG14 0x40011ace +#define CYDEV_UCFG_B1_P5_U1_CFG15 0x40011acf +#define CYDEV_UCFG_B1_P5_U1_CFG16 0x40011ad0 +#define CYDEV_UCFG_B1_P5_U1_CFG17 0x40011ad1 +#define CYDEV_UCFG_B1_P5_U1_CFG18 0x40011ad2 +#define CYDEV_UCFG_B1_P5_U1_CFG19 0x40011ad3 +#define CYDEV_UCFG_B1_P5_U1_CFG20 0x40011ad4 +#define CYDEV_UCFG_B1_P5_U1_CFG21 0x40011ad5 +#define CYDEV_UCFG_B1_P5_U1_CFG22 0x40011ad6 +#define CYDEV_UCFG_B1_P5_U1_CFG23 0x40011ad7 +#define CYDEV_UCFG_B1_P5_U1_CFG24 0x40011ad8 +#define CYDEV_UCFG_B1_P5_U1_CFG25 0x40011ad9 +#define CYDEV_UCFG_B1_P5_U1_CFG26 0x40011ada +#define CYDEV_UCFG_B1_P5_U1_CFG27 0x40011adb +#define CYDEV_UCFG_B1_P5_U1_CFG28 0x40011adc +#define CYDEV_UCFG_B1_P5_U1_CFG29 0x40011add +#define CYDEV_UCFG_B1_P5_U1_CFG30 0x40011ade +#define CYDEV_UCFG_B1_P5_U1_CFG31 0x40011adf +#define CYDEV_UCFG_B1_P5_U1_DCFG0 0x40011ae0 +#define CYDEV_UCFG_B1_P5_U1_DCFG1 0x40011ae2 +#define CYDEV_UCFG_B1_P5_U1_DCFG2 0x40011ae4 +#define CYDEV_UCFG_B1_P5_U1_DCFG3 0x40011ae6 +#define CYDEV_UCFG_B1_P5_U1_DCFG4 0x40011ae8 +#define CYDEV_UCFG_B1_P5_U1_DCFG5 0x40011aea +#define CYDEV_UCFG_B1_P5_U1_DCFG6 0x40011aec +#define CYDEV_UCFG_B1_P5_U1_DCFG7 0x40011aee +#define CYDEV_UCFG_B1_P5_ROUTE_BASE 0x40011b00 +#define CYDEV_UCFG_B1_P5_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_DSI0_BASE 0x40014000 +#define CYDEV_UCFG_DSI0_SIZE 0x000000ef +#define CYDEV_UCFG_DSI1_BASE 0x40014100 +#define CYDEV_UCFG_DSI1_SIZE 0x000000ef +#define CYDEV_UCFG_DSI2_BASE 0x40014200 +#define CYDEV_UCFG_DSI2_SIZE 0x000000ef +#define CYDEV_UCFG_DSI3_BASE 0x40014300 +#define CYDEV_UCFG_DSI3_SIZE 0x000000ef +#define CYDEV_UCFG_DSI4_BASE 0x40014400 +#define CYDEV_UCFG_DSI4_SIZE 0x000000ef +#define CYDEV_UCFG_DSI5_BASE 0x40014500 +#define CYDEV_UCFG_DSI5_SIZE 0x000000ef +#define CYDEV_UCFG_DSI6_BASE 0x40014600 +#define CYDEV_UCFG_DSI6_SIZE 0x000000ef +#define CYDEV_UCFG_DSI7_BASE 0x40014700 +#define CYDEV_UCFG_DSI7_SIZE 0x000000ef +#define CYDEV_UCFG_DSI8_BASE 0x40014800 +#define CYDEV_UCFG_DSI8_SIZE 0x000000ef +#define CYDEV_UCFG_DSI9_BASE 0x40014900 +#define CYDEV_UCFG_DSI9_SIZE 0x000000ef +#define CYDEV_UCFG_DSI12_BASE 0x40014c00 +#define CYDEV_UCFG_DSI12_SIZE 0x000000ef +#define CYDEV_UCFG_DSI13_BASE 0x40014d00 +#define CYDEV_UCFG_DSI13_SIZE 0x000000ef +#define CYDEV_UCFG_BCTL0_BASE 0x40015000 +#define CYDEV_UCFG_BCTL0_SIZE 0x00000010 +#define CYDEV_UCFG_BCTL0_MDCLK_EN 0x40015000 +#define CYDEV_UCFG_BCTL0_MBCLK_EN 0x40015001 +#define CYDEV_UCFG_BCTL0_WAIT_CFG 0x40015002 +#define CYDEV_UCFG_BCTL0_BANK_CTL 0x40015003 +#define CYDEV_UCFG_BCTL0_UDB_TEST_3 0x40015007 +#define CYDEV_UCFG_BCTL0_DCLK_EN0 0x40015008 +#define CYDEV_UCFG_BCTL0_BCLK_EN0 0x40015009 +#define CYDEV_UCFG_BCTL0_DCLK_EN1 0x4001500a +#define CYDEV_UCFG_BCTL0_BCLK_EN1 0x4001500b +#define CYDEV_UCFG_BCTL0_DCLK_EN2 0x4001500c +#define CYDEV_UCFG_BCTL0_BCLK_EN2 0x4001500d +#define CYDEV_UCFG_BCTL0_DCLK_EN3 0x4001500e +#define CYDEV_UCFG_BCTL0_BCLK_EN3 0x4001500f +#define CYDEV_UCFG_BCTL1_BASE 0x40015010 +#define CYDEV_UCFG_BCTL1_SIZE 0x00000010 +#define CYDEV_UCFG_BCTL1_MDCLK_EN 0x40015010 +#define CYDEV_UCFG_BCTL1_MBCLK_EN 0x40015011 +#define CYDEV_UCFG_BCTL1_WAIT_CFG 0x40015012 +#define CYDEV_UCFG_BCTL1_BANK_CTL 0x40015013 +#define CYDEV_UCFG_BCTL1_UDB_TEST_3 0x40015017 +#define CYDEV_UCFG_BCTL1_DCLK_EN0 0x40015018 +#define CYDEV_UCFG_BCTL1_BCLK_EN0 0x40015019 +#define CYDEV_UCFG_BCTL1_DCLK_EN1 0x4001501a +#define CYDEV_UCFG_BCTL1_BCLK_EN1 0x4001501b +#define CYDEV_UCFG_BCTL1_DCLK_EN2 0x4001501c +#define CYDEV_UCFG_BCTL1_BCLK_EN2 0x4001501d +#define CYDEV_UCFG_BCTL1_DCLK_EN3 0x4001501e +#define CYDEV_UCFG_BCTL1_BCLK_EN3 0x4001501f +#define CYDEV_IDMUX_BASE 0x40015100 +#define CYDEV_IDMUX_SIZE 0x00000016 +#define CYDEV_IDMUX_IRQ_CTL0 0x40015100 +#define CYDEV_IDMUX_IRQ_CTL1 0x40015101 +#define CYDEV_IDMUX_IRQ_CTL2 0x40015102 +#define CYDEV_IDMUX_IRQ_CTL3 0x40015103 +#define CYDEV_IDMUX_IRQ_CTL4 0x40015104 +#define CYDEV_IDMUX_IRQ_CTL5 0x40015105 +#define CYDEV_IDMUX_IRQ_CTL6 0x40015106 +#define CYDEV_IDMUX_IRQ_CTL7 0x40015107 +#define CYDEV_IDMUX_DRQ_CTL0 0x40015110 +#define CYDEV_IDMUX_DRQ_CTL1 0x40015111 +#define CYDEV_IDMUX_DRQ_CTL2 0x40015112 +#define CYDEV_IDMUX_DRQ_CTL3 0x40015113 +#define CYDEV_IDMUX_DRQ_CTL4 0x40015114 +#define CYDEV_IDMUX_DRQ_CTL5 0x40015115 +#define CYDEV_CACHERAM_BASE 0x40030000 +#define CYDEV_CACHERAM_SIZE 0x00000400 +#define CYDEV_CACHERAM_DATA_MBASE 0x40030000 +#define CYDEV_CACHERAM_DATA_MSIZE 0x00000400 +#define CYDEV_SFR_BASE 0x40050100 +#define CYDEV_SFR_SIZE 0x000000fb +#define CYDEV_SFR_GPIO0 0x40050180 +#define CYDEV_SFR_GPIRD0 0x40050189 +#define CYDEV_SFR_GPIO0_SEL 0x4005018a +#define CYDEV_SFR_GPIO1 0x40050190 +#define CYDEV_SFR_GPIRD1 0x40050191 +#define CYDEV_SFR_GPIO2 0x40050198 +#define CYDEV_SFR_GPIRD2 0x40050199 +#define CYDEV_SFR_GPIO2_SEL 0x4005019a +#define CYDEV_SFR_GPIO1_SEL 0x400501a2 +#define CYDEV_SFR_GPIO3 0x400501b0 +#define CYDEV_SFR_GPIRD3 0x400501b1 +#define CYDEV_SFR_GPIO3_SEL 0x400501b2 +#define CYDEV_SFR_GPIO4 0x400501c0 +#define CYDEV_SFR_GPIRD4 0x400501c1 +#define CYDEV_SFR_GPIO4_SEL 0x400501c2 +#define CYDEV_SFR_GPIO5 0x400501c8 +#define CYDEV_SFR_GPIRD5 0x400501c9 +#define CYDEV_SFR_GPIO5_SEL 0x400501ca +#define CYDEV_SFR_GPIO6 0x400501d8 +#define CYDEV_SFR_GPIRD6 0x400501d9 +#define CYDEV_SFR_GPIO6_SEL 0x400501da +#define CYDEV_SFR_GPIO12 0x400501e8 +#define CYDEV_SFR_GPIRD12 0x400501e9 +#define CYDEV_SFR_GPIO12_SEL 0x400501f2 +#define CYDEV_SFR_GPIO15 0x400501f8 +#define CYDEV_SFR_GPIRD15 0x400501f9 +#define CYDEV_SFR_GPIO15_SEL 0x400501fa +#define CYDEV_P3BA_BASE 0x40050300 +#define CYDEV_P3BA_SIZE 0x0000002b +#define CYDEV_P3BA_Y_START 0x40050300 +#define CYDEV_P3BA_YROLL 0x40050301 +#define CYDEV_P3BA_YCFG 0x40050302 +#define CYDEV_P3BA_X_START1 0x40050303 +#define CYDEV_P3BA_X_START2 0x40050304 +#define CYDEV_P3BA_XROLL1 0x40050305 +#define CYDEV_P3BA_XROLL2 0x40050306 +#define CYDEV_P3BA_XINC 0x40050307 +#define CYDEV_P3BA_XCFG 0x40050308 +#define CYDEV_P3BA_OFFSETADDR1 0x40050309 +#define CYDEV_P3BA_OFFSETADDR2 0x4005030a +#define CYDEV_P3BA_OFFSETADDR3 0x4005030b +#define CYDEV_P3BA_ABSADDR1 0x4005030c +#define CYDEV_P3BA_ABSADDR2 0x4005030d +#define CYDEV_P3BA_ABSADDR3 0x4005030e +#define CYDEV_P3BA_ABSADDR4 0x4005030f +#define CYDEV_P3BA_DATCFG1 0x40050310 +#define CYDEV_P3BA_DATCFG2 0x40050311 +#define CYDEV_P3BA_CMP_RSLT1 0x40050314 +#define CYDEV_P3BA_CMP_RSLT2 0x40050315 +#define CYDEV_P3BA_CMP_RSLT3 0x40050316 +#define CYDEV_P3BA_CMP_RSLT4 0x40050317 +#define CYDEV_P3BA_DATA_REG1 0x40050318 +#define CYDEV_P3BA_DATA_REG2 0x40050319 +#define CYDEV_P3BA_DATA_REG3 0x4005031a +#define CYDEV_P3BA_DATA_REG4 0x4005031b +#define CYDEV_P3BA_EXP_DATA1 0x4005031c +#define CYDEV_P3BA_EXP_DATA2 0x4005031d +#define CYDEV_P3BA_EXP_DATA3 0x4005031e +#define CYDEV_P3BA_EXP_DATA4 0x4005031f +#define CYDEV_P3BA_MSTR_HRDATA1 0x40050320 +#define CYDEV_P3BA_MSTR_HRDATA2 0x40050321 +#define CYDEV_P3BA_MSTR_HRDATA3 0x40050322 +#define CYDEV_P3BA_MSTR_HRDATA4 0x40050323 +#define CYDEV_P3BA_BIST_EN 0x40050324 +#define CYDEV_P3BA_PHUB_MASTER_SSR 0x40050325 +#define CYDEV_P3BA_SEQCFG1 0x40050326 +#define CYDEV_P3BA_SEQCFG2 0x40050327 +#define CYDEV_P3BA_Y_CURR 0x40050328 +#define CYDEV_P3BA_X_CURR1 0x40050329 +#define CYDEV_P3BA_X_CURR2 0x4005032a +#define CYDEV_PANTHER_BASE 0x40080000 +#define CYDEV_PANTHER_SIZE 0x00000020 +#define CYDEV_PANTHER_STCALIB_CFG 0x40080000 +#define CYDEV_PANTHER_WAITPIPE 0x40080004 +#define CYDEV_PANTHER_TRACE_CFG 0x40080008 +#define CYDEV_PANTHER_DBG_CFG 0x4008000c +#define CYDEV_PANTHER_CM3_LCKRST_STAT 0x40080018 +#define CYDEV_PANTHER_DEVICE_ID 0x4008001c +#define CYDEV_FLSECC_BASE 0x48000000 +#define CYDEV_FLSECC_SIZE 0x00008000 +#define CYDEV_FLSECC_DATA_MBASE 0x48000000 +#define CYDEV_FLSECC_DATA_MSIZE 0x00008000 +#define CYDEV_FLSHID_BASE 0x49000000 +#define CYDEV_FLSHID_SIZE 0x00000200 +#define CYDEV_FLSHID_RSVD_MBASE 0x49000000 +#define CYDEV_FLSHID_RSVD_MSIZE 0x00000080 +#define CYDEV_FLSHID_CUST_MDATA_MBASE 0x49000080 +#define CYDEV_FLSHID_CUST_MDATA_MSIZE 0x00000080 +#define CYDEV_FLSHID_CUST_TABLES_BASE 0x49000100 +#define CYDEV_FLSHID_CUST_TABLES_SIZE 0x00000040 +#define CYDEV_FLSHID_CUST_TABLES_Y_LOC 0x49000100 +#define CYDEV_FLSHID_CUST_TABLES_X_LOC 0x49000101 +#define CYDEV_FLSHID_CUST_TABLES_WAFER_NUM 0x49000102 +#define CYDEV_FLSHID_CUST_TABLES_LOT_LSB 0x49000103 +#define CYDEV_FLSHID_CUST_TABLES_LOT_MSB 0x49000104 +#define CYDEV_FLSHID_CUST_TABLES_WRK_WK 0x49000105 +#define CYDEV_FLSHID_CUST_TABLES_FAB_YR 0x49000106 +#define CYDEV_FLSHID_CUST_TABLES_MINOR 0x49000107 +#define CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ 0x49000108 +#define CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ 0x49000109 +#define CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ 0x4900010a +#define CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ 0x4900010b +#define CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ 0x4900010c +#define CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ 0x4900010d +#define CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ 0x4900010e +#define CYDEV_FLSHID_CUST_TABLES_IMO_USB 0x4900010f +#define CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS 0x49000110 +#define CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS 0x49000111 +#define CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS 0x49000112 +#define CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS 0x49000113 +#define CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS 0x49000114 +#define CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS 0x49000115 +#define CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS 0x49000116 +#define CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS 0x49000117 +#define CYDEV_FLSHID_CUST_TABLES_DEC_M1 0x49000118 +#define CYDEV_FLSHID_CUST_TABLES_DEC_M2 0x49000119 +#define CYDEV_FLSHID_CUST_TABLES_DEC_M3 0x4900011a +#define CYDEV_FLSHID_CUST_TABLES_DEC_M4 0x4900011b +#define CYDEV_FLSHID_CUST_TABLES_DEC_M5 0x4900011c +#define CYDEV_FLSHID_CUST_TABLES_DEC_M6 0x4900011d +#define CYDEV_FLSHID_CUST_TABLES_DEC_M7 0x4900011e +#define CYDEV_FLSHID_CUST_TABLES_DEC_M8 0x4900011f +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M1 0x49000120 +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M2 0x49000121 +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M3 0x49000122 +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M4 0x49000123 +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M5 0x49000124 +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M6 0x49000125 +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M7 0x49000126 +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M8 0x49000127 +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M1 0x49000128 +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M2 0x49000129 +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M3 0x4900012a +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M4 0x4900012b +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M5 0x4900012c +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M6 0x4900012d +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M7 0x4900012e +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M8 0x4900012f +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M1 0x49000130 +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M2 0x49000131 +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M3 0x49000132 +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M4 0x49000133 +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M5 0x49000134 +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M6 0x49000135 +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M7 0x49000136 +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M8 0x49000137 +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M1 0x49000138 +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M2 0x49000139 +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M3 0x4900013a +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M4 0x4900013b +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M5 0x4900013c +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M6 0x4900013d +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M7 0x4900013e +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M8 0x4900013f +#define CYDEV_FLSHID_MFG_CFG_BASE 0x49000180 +#define CYDEV_FLSHID_MFG_CFG_SIZE 0x00000080 +#define CYDEV_FLSHID_MFG_CFG_IMO_TR1 0x49000188 +#define CYDEV_FLSHID_MFG_CFG_CMP0_TR0 0x490001ac +#define CYDEV_FLSHID_MFG_CFG_CMP1_TR0 0x490001ae +#define CYDEV_FLSHID_MFG_CFG_CMP2_TR0 0x490001b0 +#define CYDEV_FLSHID_MFG_CFG_CMP3_TR0 0x490001b2 +#define CYDEV_FLSHID_MFG_CFG_CMP0_TR1 0x490001b4 +#define CYDEV_FLSHID_MFG_CFG_CMP1_TR1 0x490001b6 +#define CYDEV_FLSHID_MFG_CFG_CMP2_TR1 0x490001b8 +#define CYDEV_FLSHID_MFG_CFG_CMP3_TR1 0x490001ba +#define CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM 0x490001ce +#define CYDEV_EXTMEM_BASE 0x60000000 +#define CYDEV_EXTMEM_SIZE 0x00800000 +#define CYDEV_EXTMEM_DATA_MBASE 0x60000000 +#define CYDEV_EXTMEM_DATA_MSIZE 0x00800000 +#define CYDEV_ITM_BASE 0xe0000000 +#define CYDEV_ITM_SIZE 0x00001000 +#define CYDEV_ITM_TRACE_EN 0xe0000e00 +#define CYDEV_ITM_TRACE_PRIVILEGE 0xe0000e40 +#define CYDEV_ITM_TRACE_CTRL 0xe0000e80 +#define CYDEV_ITM_LOCK_ACCESS 0xe0000fb0 +#define CYDEV_ITM_LOCK_STATUS 0xe0000fb4 +#define CYDEV_ITM_PID4 0xe0000fd0 +#define CYDEV_ITM_PID5 0xe0000fd4 +#define CYDEV_ITM_PID6 0xe0000fd8 +#define CYDEV_ITM_PID7 0xe0000fdc +#define CYDEV_ITM_PID0 0xe0000fe0 +#define CYDEV_ITM_PID1 0xe0000fe4 +#define CYDEV_ITM_PID2 0xe0000fe8 +#define CYDEV_ITM_PID3 0xe0000fec +#define CYDEV_ITM_CID0 0xe0000ff0 +#define CYDEV_ITM_CID1 0xe0000ff4 +#define CYDEV_ITM_CID2 0xe0000ff8 +#define CYDEV_ITM_CID3 0xe0000ffc +#define CYDEV_DWT_BASE 0xe0001000 +#define CYDEV_DWT_SIZE 0x0000005c +#define CYDEV_DWT_CTRL 0xe0001000 +#define CYDEV_DWT_CYCLE_COUNT 0xe0001004 +#define CYDEV_DWT_CPI_COUNT 0xe0001008 +#define CYDEV_DWT_EXC_OVHD_COUNT 0xe000100c +#define CYDEV_DWT_SLEEP_COUNT 0xe0001010 +#define CYDEV_DWT_LSU_COUNT 0xe0001014 +#define CYDEV_DWT_FOLD_COUNT 0xe0001018 +#define CYDEV_DWT_PC_SAMPLE 0xe000101c +#define CYDEV_DWT_COMP_0 0xe0001020 +#define CYDEV_DWT_MASK_0 0xe0001024 +#define CYDEV_DWT_FUNCTION_0 0xe0001028 +#define CYDEV_DWT_COMP_1 0xe0001030 +#define CYDEV_DWT_MASK_1 0xe0001034 +#define CYDEV_DWT_FUNCTION_1 0xe0001038 +#define CYDEV_DWT_COMP_2 0xe0001040 +#define CYDEV_DWT_MASK_2 0xe0001044 +#define CYDEV_DWT_FUNCTION_2 0xe0001048 +#define CYDEV_DWT_COMP_3 0xe0001050 +#define CYDEV_DWT_MASK_3 0xe0001054 +#define CYDEV_DWT_FUNCTION_3 0xe0001058 +#define CYDEV_FPB_BASE 0xe0002000 +#define CYDEV_FPB_SIZE 0x00001000 +#define CYDEV_FPB_CTRL 0xe0002000 +#define CYDEV_FPB_REMAP 0xe0002004 +#define CYDEV_FPB_FP_COMP_0 0xe0002008 +#define CYDEV_FPB_FP_COMP_1 0xe000200c +#define CYDEV_FPB_FP_COMP_2 0xe0002010 +#define CYDEV_FPB_FP_COMP_3 0xe0002014 +#define CYDEV_FPB_FP_COMP_4 0xe0002018 +#define CYDEV_FPB_FP_COMP_5 0xe000201c +#define CYDEV_FPB_FP_COMP_6 0xe0002020 +#define CYDEV_FPB_FP_COMP_7 0xe0002024 +#define CYDEV_FPB_PID4 0xe0002fd0 +#define CYDEV_FPB_PID5 0xe0002fd4 +#define CYDEV_FPB_PID6 0xe0002fd8 +#define CYDEV_FPB_PID7 0xe0002fdc +#define CYDEV_FPB_PID0 0xe0002fe0 +#define CYDEV_FPB_PID1 0xe0002fe4 +#define CYDEV_FPB_PID2 0xe0002fe8 +#define CYDEV_FPB_PID3 0xe0002fec +#define CYDEV_FPB_CID0 0xe0002ff0 +#define CYDEV_FPB_CID1 0xe0002ff4 +#define CYDEV_FPB_CID2 0xe0002ff8 +#define CYDEV_FPB_CID3 0xe0002ffc +#define CYDEV_NVIC_BASE 0xe000e000 +#define CYDEV_NVIC_SIZE 0x00000d3c +#define CYDEV_NVIC_INT_CTL_TYPE 0xe000e004 +#define CYDEV_NVIC_SYSTICK_CTL 0xe000e010 +#define CYDEV_NVIC_SYSTICK_RELOAD 0xe000e014 +#define CYDEV_NVIC_SYSTICK_CURRENT 0xe000e018 +#define CYDEV_NVIC_SYSTICK_CAL 0xe000e01c +#define CYDEV_NVIC_SETENA0 0xe000e100 +#define CYDEV_NVIC_CLRENA0 0xe000e180 +#define CYDEV_NVIC_SETPEND0 0xe000e200 +#define CYDEV_NVIC_CLRPEND0 0xe000e280 +#define CYDEV_NVIC_ACTIVE0 0xe000e300 +#define CYDEV_NVIC_PRI_0 0xe000e400 +#define CYDEV_NVIC_PRI_1 0xe000e401 +#define CYDEV_NVIC_PRI_2 0xe000e402 +#define CYDEV_NVIC_PRI_3 0xe000e403 +#define CYDEV_NVIC_PRI_4 0xe000e404 +#define CYDEV_NVIC_PRI_5 0xe000e405 +#define CYDEV_NVIC_PRI_6 0xe000e406 +#define CYDEV_NVIC_PRI_7 0xe000e407 +#define CYDEV_NVIC_PRI_8 0xe000e408 +#define CYDEV_NVIC_PRI_9 0xe000e409 +#define CYDEV_NVIC_PRI_10 0xe000e40a +#define CYDEV_NVIC_PRI_11 0xe000e40b +#define CYDEV_NVIC_PRI_12 0xe000e40c +#define CYDEV_NVIC_PRI_13 0xe000e40d +#define CYDEV_NVIC_PRI_14 0xe000e40e +#define CYDEV_NVIC_PRI_15 0xe000e40f +#define CYDEV_NVIC_PRI_16 0xe000e410 +#define CYDEV_NVIC_PRI_17 0xe000e411 +#define CYDEV_NVIC_PRI_18 0xe000e412 +#define CYDEV_NVIC_PRI_19 0xe000e413 +#define CYDEV_NVIC_PRI_20 0xe000e414 +#define CYDEV_NVIC_PRI_21 0xe000e415 +#define CYDEV_NVIC_PRI_22 0xe000e416 +#define CYDEV_NVIC_PRI_23 0xe000e417 +#define CYDEV_NVIC_PRI_24 0xe000e418 +#define CYDEV_NVIC_PRI_25 0xe000e419 +#define CYDEV_NVIC_PRI_26 0xe000e41a +#define CYDEV_NVIC_PRI_27 0xe000e41b +#define CYDEV_NVIC_PRI_28 0xe000e41c +#define CYDEV_NVIC_PRI_29 0xe000e41d +#define CYDEV_NVIC_PRI_30 0xe000e41e +#define CYDEV_NVIC_PRI_31 0xe000e41f +#define CYDEV_NVIC_CPUID_BASE 0xe000ed00 +#define CYDEV_NVIC_INTR_CTRL_STATE 0xe000ed04 +#define CYDEV_NVIC_VECT_OFFSET 0xe000ed08 +#define CYDEV_NVIC_APPLN_INTR 0xe000ed0c +#define CYDEV_NVIC_SYSTEM_CONTROL 0xe000ed10 +#define CYDEV_NVIC_CFG_CONTROL 0xe000ed14 +#define CYDEV_NVIC_SYS_PRIO_HANDLER_4_7 0xe000ed18 +#define CYDEV_NVIC_SYS_PRIO_HANDLER_8_11 0xe000ed1c +#define CYDEV_NVIC_SYS_PRIO_HANDLER_12_15 0xe000ed20 +#define CYDEV_NVIC_SYS_HANDLER_CSR 0xe000ed24 +#define CYDEV_NVIC_MEMMAN_FAULT_STATUS 0xe000ed28 +#define CYDEV_NVIC_BUS_FAULT_STATUS 0xe000ed29 +#define CYDEV_NVIC_USAGE_FAULT_STATUS 0xe000ed2a +#define CYDEV_NVIC_HARD_FAULT_STATUS 0xe000ed2c +#define CYDEV_NVIC_DEBUG_FAULT_STATUS 0xe000ed30 +#define CYDEV_NVIC_MEMMAN_FAULT_ADD 0xe000ed34 +#define CYDEV_NVIC_BUS_FAULT_ADD 0xe000ed38 +#define CYDEV_CORE_DBG_BASE 0xe000edf0 +#define CYDEV_CORE_DBG_SIZE 0x00000010 +#define CYDEV_CORE_DBG_DBG_HLT_CS 0xe000edf0 +#define CYDEV_CORE_DBG_DBG_REG_SEL 0xe000edf4 +#define CYDEV_CORE_DBG_DBG_REG_DATA 0xe000edf8 +#define CYDEV_CORE_DBG_EXC_MON_CTL 0xe000edfc +#define CYDEV_TPIU_BASE 0xe0040000 +#define CYDEV_TPIU_SIZE 0x00001000 +#define CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ 0xe0040000 +#define CYDEV_TPIU_CURRENT_SYNC_PRT_SZ 0xe0040004 +#define CYDEV_TPIU_ASYNC_CLK_PRESCALER 0xe0040010 +#define CYDEV_TPIU_PROTOCOL 0xe00400f0 +#define CYDEV_TPIU_FORM_FLUSH_STAT 0xe0040300 +#define CYDEV_TPIU_FORM_FLUSH_CTRL 0xe0040304 +#define CYDEV_TPIU_TRIGGER 0xe0040ee8 +#define CYDEV_TPIU_ITETMDATA 0xe0040eec +#define CYDEV_TPIU_ITATBCTR2 0xe0040ef0 +#define CYDEV_TPIU_ITATBCTR0 0xe0040ef8 +#define CYDEV_TPIU_ITITMDATA 0xe0040efc +#define CYDEV_TPIU_ITCTRL 0xe0040f00 +#define CYDEV_TPIU_DEVID 0xe0040fc8 +#define CYDEV_TPIU_DEVTYPE 0xe0040fcc +#define CYDEV_TPIU_PID4 0xe0040fd0 +#define CYDEV_TPIU_PID5 0xe0040fd4 +#define CYDEV_TPIU_PID6 0xe0040fd8 +#define CYDEV_TPIU_PID7 0xe0040fdc +#define CYDEV_TPIU_PID0 0xe0040fe0 +#define CYDEV_TPIU_PID1 0xe0040fe4 +#define CYDEV_TPIU_PID2 0xe0040fe8 +#define CYDEV_TPIU_PID3 0xe0040fec +#define CYDEV_TPIU_CID0 0xe0040ff0 +#define CYDEV_TPIU_CID1 0xe0040ff4 +#define CYDEV_TPIU_CID2 0xe0040ff8 +#define CYDEV_TPIU_CID3 0xe0040ffc +#define CYDEV_ETM_BASE 0xe0041000 +#define CYDEV_ETM_SIZE 0x00001000 +#define CYDEV_ETM_CTL 0xe0041000 +#define CYDEV_ETM_CFG_CODE 0xe0041004 +#define CYDEV_ETM_TRIG_EVENT 0xe0041008 +#define CYDEV_ETM_STATUS 0xe0041010 +#define CYDEV_ETM_SYS_CFG 0xe0041014 +#define CYDEV_ETM_TRACE_ENB_EVENT 0xe0041020 +#define CYDEV_ETM_TRACE_EN_CTRL1 0xe0041024 +#define CYDEV_ETM_FIFOFULL_LEVEL 0xe004102c +#define CYDEV_ETM_SYNC_FREQ 0xe00411e0 +#define CYDEV_ETM_ETM_ID 0xe00411e4 +#define CYDEV_ETM_CFG_CODE_EXT 0xe00411e8 +#define CYDEV_ETM_TR_SS_EMBICE_CTRL 0xe00411f0 +#define CYDEV_ETM_CS_TRACE_ID 0xe0041200 +#define CYDEV_ETM_OS_LOCK_ACCESS 0xe0041300 +#define CYDEV_ETM_OS_LOCK_STATUS 0xe0041304 +#define CYDEV_ETM_PDSR 0xe0041314 +#define CYDEV_ETM_ITMISCIN 0xe0041ee0 +#define CYDEV_ETM_ITTRIGOUT 0xe0041ee8 +#define CYDEV_ETM_ITATBCTR2 0xe0041ef0 +#define CYDEV_ETM_ITATBCTR0 0xe0041ef8 +#define CYDEV_ETM_INT_MODE_CTRL 0xe0041f00 +#define CYDEV_ETM_CLM_TAG_SET 0xe0041fa0 +#define CYDEV_ETM_CLM_TAG_CLR 0xe0041fa4 +#define CYDEV_ETM_LOCK_ACCESS 0xe0041fb0 +#define CYDEV_ETM_LOCK_STATUS 0xe0041fb4 +#define CYDEV_ETM_AUTH_STATUS 0xe0041fb8 +#define CYDEV_ETM_DEV_TYPE 0xe0041fcc +#define CYDEV_ETM_PID4 0xe0041fd0 +#define CYDEV_ETM_PID5 0xe0041fd4 +#define CYDEV_ETM_PID6 0xe0041fd8 +#define CYDEV_ETM_PID7 0xe0041fdc +#define CYDEV_ETM_PID0 0xe0041fe0 +#define CYDEV_ETM_PID1 0xe0041fe4 +#define CYDEV_ETM_PID2 0xe0041fe8 +#define CYDEV_ETM_PID3 0xe0041fec +#define CYDEV_ETM_CID0 0xe0041ff0 +#define CYDEV_ETM_CID1 0xe0041ff4 +#define CYDEV_ETM_CID2 0xe0041ff8 +#define CYDEV_ETM_CID3 0xe0041ffc +#define CYDEV_ROM_TABLE_BASE 0xe00ff000 +#define CYDEV_ROM_TABLE_SIZE 0x00001000 +#define CYDEV_ROM_TABLE_NVIC 0xe00ff000 +#define CYDEV_ROM_TABLE_DWT 0xe00ff004 +#define CYDEV_ROM_TABLE_FPB 0xe00ff008 +#define CYDEV_ROM_TABLE_ITM 0xe00ff00c +#define CYDEV_ROM_TABLE_TPIU 0xe00ff010 +#define CYDEV_ROM_TABLE_ETM 0xe00ff014 +#define CYDEV_ROM_TABLE_END 0xe00ff018 +#define CYDEV_ROM_TABLE_MEMTYPE 0xe00fffcc +#define CYDEV_ROM_TABLE_PID4 0xe00fffd0 +#define CYDEV_ROM_TABLE_PID5 0xe00fffd4 +#define CYDEV_ROM_TABLE_PID6 0xe00fffd8 +#define CYDEV_ROM_TABLE_PID7 0xe00fffdc +#define CYDEV_ROM_TABLE_PID0 0xe00fffe0 +#define CYDEV_ROM_TABLE_PID1 0xe00fffe4 +#define CYDEV_ROM_TABLE_PID2 0xe00fffe8 +#define CYDEV_ROM_TABLE_PID3 0xe00fffec +#define CYDEV_ROM_TABLE_CID0 0xe00ffff0 +#define CYDEV_ROM_TABLE_CID1 0xe00ffff4 +#define CYDEV_ROM_TABLE_CID2 0xe00ffff8 +#define CYDEV_ROM_TABLE_CID3 0xe00ffffc +#define CYDEV_FLS_SIZE CYDEV_FLASH_SIZE +#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE +#define CYDEV_FLS_SECTOR_SIZE 0x00010000 +#define CYDEV_FLS_ROW_SIZE 0x00000100 +#define CYDEV_ECC_SECTOR_SIZE 0x00002000 +#define CYDEV_ECC_ROW_SIZE 0x00000020 +#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400 +#define CYDEV_EEPROM_ROW_SIZE 0x00000010 +#define CYDEV_PERIPH_BASE CYDEV_CLKDIST_BASE +#define CYCLK_LD_DISABLE 0x00000004 +#define CYCLK_LD_SYNC_EN 0x00000002 +#define CYCLK_LD_LOAD 0x00000001 +#define CYCLK_PIPE 0x00000080 +#define CYCLK_SSS 0x00000040 +#define CYCLK_EARLY 0x00000020 +#define CYCLK_DUTY 0x00000010 +#define CYCLK_SYNC 0x00000008 +#define CYCLK_SRC_SEL_CLK_SYNC_D 0 +#define CYCLK_SRC_SEL_SYNC_DIG 0 +#define CYCLK_SRC_SEL_IMO 1 +#define CYCLK_SRC_SEL_XTAL_MHZ 2 +#define CYCLK_SRC_SEL_XTALM 2 +#define CYCLK_SRC_SEL_ILO 3 +#define CYCLK_SRC_SEL_PLL 4 +#define CYCLK_SRC_SEL_XTAL_KHZ 5 +#define CYCLK_SRC_SEL_XTALK 5 +#define CYCLK_SRC_SEL_DSI_G 6 +#define CYCLK_SRC_SEL_DSI_D 7 +#define CYCLK_SRC_SEL_CLK_SYNC_A 0 +#define CYCLK_SRC_SEL_DSI_A 7 diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc new file mode 100755 index 00000000..9ce82ff8 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc @@ -0,0 +1,5356 @@ +; +; FILENAME: cydeviceiar_trm.inc +; +; PSoC Creator 3.0 Component Pack 7 +; +; DESCRIPTION: +; This file provides all of the address values for the entire PSoC device. +; +;------------------------------------------------------------------------------- +; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + +#define CYDEV_FLASH_BASE 0x00000000 +#define CYDEV_FLASH_SIZE 0x00020000 +#define CYREG_FLASH_DATA_MBASE 0x00000000 +#define CYREG_FLASH_DATA_MSIZE 0x00020000 +#define CYDEV_SRAM_BASE 0x1fffc000 +#define CYDEV_SRAM_SIZE 0x00008000 +#define CYREG_SRAM_CODE64K_MBASE 0x1fff8000 +#define CYREG_SRAM_CODE64K_MSIZE 0x00004000 +#define CYREG_SRAM_CODE32K_MBASE 0x1fffc000 +#define CYREG_SRAM_CODE32K_MSIZE 0x00002000 +#define CYREG_SRAM_CODE16K_MBASE 0x1fffe000 +#define CYREG_SRAM_CODE16K_MSIZE 0x00001000 +#define CYREG_SRAM_CODE_MBASE 0x1fffc000 +#define CYREG_SRAM_CODE_MSIZE 0x00004000 +#define CYREG_SRAM_DATA_MBASE 0x20000000 +#define CYREG_SRAM_DATA_MSIZE 0x00004000 +#define CYREG_SRAM_DATA16K_MBASE 0x20001000 +#define CYREG_SRAM_DATA16K_MSIZE 0x00001000 +#define CYREG_SRAM_DATA32K_MBASE 0x20002000 +#define CYREG_SRAM_DATA32K_MSIZE 0x00002000 +#define CYREG_SRAM_DATA64K_MBASE 0x20004000 +#define CYREG_SRAM_DATA64K_MSIZE 0x00004000 +#define CYDEV_DMA_BASE 0x20008000 +#define CYDEV_DMA_SIZE 0x00008000 +#define CYREG_DMA_SRAM64K_MBASE 0x20008000 +#define CYREG_DMA_SRAM64K_MSIZE 0x00004000 +#define CYREG_DMA_SRAM32K_MBASE 0x2000c000 +#define CYREG_DMA_SRAM32K_MSIZE 0x00002000 +#define CYREG_DMA_SRAM16K_MBASE 0x2000e000 +#define CYREG_DMA_SRAM16K_MSIZE 0x00001000 +#define CYREG_DMA_SRAM_MBASE 0x2000f000 +#define CYREG_DMA_SRAM_MSIZE 0x00001000 +#define CYDEV_CLKDIST_BASE 0x40004000 +#define CYDEV_CLKDIST_SIZE 0x00000110 +#define CYREG_CLKDIST_CR 0x40004000 +#define CYREG_CLKDIST_LD 0x40004001 +#define CYREG_CLKDIST_WRK0 0x40004002 +#define CYREG_CLKDIST_WRK1 0x40004003 +#define CYREG_CLKDIST_MSTR0 0x40004004 +#define CYREG_CLKDIST_MSTR1 0x40004005 +#define CYREG_CLKDIST_BCFG0 0x40004006 +#define CYREG_CLKDIST_BCFG1 0x40004007 +#define CYREG_CLKDIST_BCFG2 0x40004008 +#define CYREG_CLKDIST_UCFG 0x40004009 +#define CYREG_CLKDIST_DLY0 0x4000400a +#define CYREG_CLKDIST_DLY1 0x4000400b +#define CYREG_CLKDIST_DMASK 0x40004010 +#define CYREG_CLKDIST_AMASK 0x40004014 +#define CYDEV_CLKDIST_DCFG0_BASE 0x40004080 +#define CYDEV_CLKDIST_DCFG0_SIZE 0x00000003 +#define CYREG_CLKDIST_DCFG0_CFG0 0x40004080 +#define CYREG_CLKDIST_DCFG0_CFG1 0x40004081 +#define CYREG_CLKDIST_DCFG0_CFG2 0x40004082 +#define CYDEV_CLKDIST_DCFG1_BASE 0x40004084 +#define CYDEV_CLKDIST_DCFG1_SIZE 0x00000003 +#define CYREG_CLKDIST_DCFG1_CFG0 0x40004084 +#define CYREG_CLKDIST_DCFG1_CFG1 0x40004085 +#define CYREG_CLKDIST_DCFG1_CFG2 0x40004086 +#define CYDEV_CLKDIST_DCFG2_BASE 0x40004088 +#define CYDEV_CLKDIST_DCFG2_SIZE 0x00000003 +#define CYREG_CLKDIST_DCFG2_CFG0 0x40004088 +#define CYREG_CLKDIST_DCFG2_CFG1 0x40004089 +#define CYREG_CLKDIST_DCFG2_CFG2 0x4000408a +#define CYDEV_CLKDIST_DCFG3_BASE 0x4000408c +#define CYDEV_CLKDIST_DCFG3_SIZE 0x00000003 +#define CYREG_CLKDIST_DCFG3_CFG0 0x4000408c +#define CYREG_CLKDIST_DCFG3_CFG1 0x4000408d +#define CYREG_CLKDIST_DCFG3_CFG2 0x4000408e +#define CYDEV_CLKDIST_DCFG4_BASE 0x40004090 +#define CYDEV_CLKDIST_DCFG4_SIZE 0x00000003 +#define CYREG_CLKDIST_DCFG4_CFG0 0x40004090 +#define CYREG_CLKDIST_DCFG4_CFG1 0x40004091 +#define CYREG_CLKDIST_DCFG4_CFG2 0x40004092 +#define CYDEV_CLKDIST_DCFG5_BASE 0x40004094 +#define CYDEV_CLKDIST_DCFG5_SIZE 0x00000003 +#define CYREG_CLKDIST_DCFG5_CFG0 0x40004094 +#define CYREG_CLKDIST_DCFG5_CFG1 0x40004095 +#define CYREG_CLKDIST_DCFG5_CFG2 0x40004096 +#define CYDEV_CLKDIST_DCFG6_BASE 0x40004098 +#define CYDEV_CLKDIST_DCFG6_SIZE 0x00000003 +#define CYREG_CLKDIST_DCFG6_CFG0 0x40004098 +#define CYREG_CLKDIST_DCFG6_CFG1 0x40004099 +#define CYREG_CLKDIST_DCFG6_CFG2 0x4000409a +#define CYDEV_CLKDIST_DCFG7_BASE 0x4000409c +#define CYDEV_CLKDIST_DCFG7_SIZE 0x00000003 +#define CYREG_CLKDIST_DCFG7_CFG0 0x4000409c +#define CYREG_CLKDIST_DCFG7_CFG1 0x4000409d +#define CYREG_CLKDIST_DCFG7_CFG2 0x4000409e +#define CYDEV_CLKDIST_ACFG0_BASE 0x40004100 +#define CYDEV_CLKDIST_ACFG0_SIZE 0x00000004 +#define CYREG_CLKDIST_ACFG0_CFG0 0x40004100 +#define CYREG_CLKDIST_ACFG0_CFG1 0x40004101 +#define CYREG_CLKDIST_ACFG0_CFG2 0x40004102 +#define CYREG_CLKDIST_ACFG0_CFG3 0x40004103 +#define CYDEV_CLKDIST_ACFG1_BASE 0x40004104 +#define CYDEV_CLKDIST_ACFG1_SIZE 0x00000004 +#define CYREG_CLKDIST_ACFG1_CFG0 0x40004104 +#define CYREG_CLKDIST_ACFG1_CFG1 0x40004105 +#define CYREG_CLKDIST_ACFG1_CFG2 0x40004106 +#define CYREG_CLKDIST_ACFG1_CFG3 0x40004107 +#define CYDEV_CLKDIST_ACFG2_BASE 0x40004108 +#define CYDEV_CLKDIST_ACFG2_SIZE 0x00000004 +#define CYREG_CLKDIST_ACFG2_CFG0 0x40004108 +#define CYREG_CLKDIST_ACFG2_CFG1 0x40004109 +#define CYREG_CLKDIST_ACFG2_CFG2 0x4000410a +#define CYREG_CLKDIST_ACFG2_CFG3 0x4000410b +#define CYDEV_CLKDIST_ACFG3_BASE 0x4000410c +#define CYDEV_CLKDIST_ACFG3_SIZE 0x00000004 +#define CYREG_CLKDIST_ACFG3_CFG0 0x4000410c +#define CYREG_CLKDIST_ACFG3_CFG1 0x4000410d +#define CYREG_CLKDIST_ACFG3_CFG2 0x4000410e +#define CYREG_CLKDIST_ACFG3_CFG3 0x4000410f +#define CYDEV_FASTCLK_BASE 0x40004200 +#define CYDEV_FASTCLK_SIZE 0x00000026 +#define CYDEV_FASTCLK_IMO_BASE 0x40004200 +#define CYDEV_FASTCLK_IMO_SIZE 0x00000001 +#define CYREG_FASTCLK_IMO_CR 0x40004200 +#define CYDEV_FASTCLK_XMHZ_BASE 0x40004210 +#define CYDEV_FASTCLK_XMHZ_SIZE 0x00000004 +#define CYREG_FASTCLK_XMHZ_CSR 0x40004210 +#define CYREG_FASTCLK_XMHZ_CFG0 0x40004212 +#define CYREG_FASTCLK_XMHZ_CFG1 0x40004213 +#define CYDEV_FASTCLK_PLL_BASE 0x40004220 +#define CYDEV_FASTCLK_PLL_SIZE 0x00000006 +#define CYREG_FASTCLK_PLL_CFG0 0x40004220 +#define CYREG_FASTCLK_PLL_CFG1 0x40004221 +#define CYREG_FASTCLK_PLL_P 0x40004222 +#define CYREG_FASTCLK_PLL_Q 0x40004223 +#define CYREG_FASTCLK_PLL_SR 0x40004225 +#define CYDEV_SLOWCLK_BASE 0x40004300 +#define CYDEV_SLOWCLK_SIZE 0x0000000b +#define CYDEV_SLOWCLK_ILO_BASE 0x40004300 +#define CYDEV_SLOWCLK_ILO_SIZE 0x00000002 +#define CYREG_SLOWCLK_ILO_CR0 0x40004300 +#define CYREG_SLOWCLK_ILO_CR1 0x40004301 +#define CYDEV_SLOWCLK_X32_BASE 0x40004308 +#define CYDEV_SLOWCLK_X32_SIZE 0x00000003 +#define CYREG_SLOWCLK_X32_CR 0x40004308 +#define CYREG_SLOWCLK_X32_CFG 0x40004309 +#define CYREG_SLOWCLK_X32_TST 0x4000430a +#define CYDEV_BOOST_BASE 0x40004320 +#define CYDEV_BOOST_SIZE 0x00000007 +#define CYREG_BOOST_CR0 0x40004320 +#define CYREG_BOOST_CR1 0x40004321 +#define CYREG_BOOST_CR2 0x40004322 +#define CYREG_BOOST_CR3 0x40004323 +#define CYREG_BOOST_SR 0x40004324 +#define CYREG_BOOST_CR4 0x40004325 +#define CYREG_BOOST_SR2 0x40004326 +#define CYDEV_PWRSYS_BASE 0x40004330 +#define CYDEV_PWRSYS_SIZE 0x00000002 +#define CYREG_PWRSYS_CR0 0x40004330 +#define CYREG_PWRSYS_CR1 0x40004331 +#define CYDEV_PM_BASE 0x40004380 +#define CYDEV_PM_SIZE 0x00000057 +#define CYREG_PM_TW_CFG0 0x40004380 +#define CYREG_PM_TW_CFG1 0x40004381 +#define CYREG_PM_TW_CFG2 0x40004382 +#define CYREG_PM_WDT_CFG 0x40004383 +#define CYREG_PM_WDT_CR 0x40004384 +#define CYREG_PM_INT_SR 0x40004390 +#define CYREG_PM_MODE_CFG0 0x40004391 +#define CYREG_PM_MODE_CFG1 0x40004392 +#define CYREG_PM_MODE_CSR 0x40004393 +#define CYREG_PM_USB_CR0 0x40004394 +#define CYREG_PM_WAKEUP_CFG0 0x40004398 +#define CYREG_PM_WAKEUP_CFG1 0x40004399 +#define CYREG_PM_WAKEUP_CFG2 0x4000439a +#define CYDEV_PM_ACT_BASE 0x400043a0 +#define CYDEV_PM_ACT_SIZE 0x0000000e +#define CYREG_PM_ACT_CFG0 0x400043a0 +#define CYREG_PM_ACT_CFG1 0x400043a1 +#define CYREG_PM_ACT_CFG2 0x400043a2 +#define CYREG_PM_ACT_CFG3 0x400043a3 +#define CYREG_PM_ACT_CFG4 0x400043a4 +#define CYREG_PM_ACT_CFG5 0x400043a5 +#define CYREG_PM_ACT_CFG6 0x400043a6 +#define CYREG_PM_ACT_CFG7 0x400043a7 +#define CYREG_PM_ACT_CFG8 0x400043a8 +#define CYREG_PM_ACT_CFG9 0x400043a9 +#define CYREG_PM_ACT_CFG10 0x400043aa +#define CYREG_PM_ACT_CFG11 0x400043ab +#define CYREG_PM_ACT_CFG12 0x400043ac +#define CYREG_PM_ACT_CFG13 0x400043ad +#define CYDEV_PM_STBY_BASE 0x400043b0 +#define CYDEV_PM_STBY_SIZE 0x0000000e +#define CYREG_PM_STBY_CFG0 0x400043b0 +#define CYREG_PM_STBY_CFG1 0x400043b1 +#define CYREG_PM_STBY_CFG2 0x400043b2 +#define CYREG_PM_STBY_CFG3 0x400043b3 +#define CYREG_PM_STBY_CFG4 0x400043b4 +#define CYREG_PM_STBY_CFG5 0x400043b5 +#define CYREG_PM_STBY_CFG6 0x400043b6 +#define CYREG_PM_STBY_CFG7 0x400043b7 +#define CYREG_PM_STBY_CFG8 0x400043b8 +#define CYREG_PM_STBY_CFG9 0x400043b9 +#define CYREG_PM_STBY_CFG10 0x400043ba +#define CYREG_PM_STBY_CFG11 0x400043bb +#define CYREG_PM_STBY_CFG12 0x400043bc +#define CYREG_PM_STBY_CFG13 0x400043bd +#define CYDEV_PM_AVAIL_BASE 0x400043c0 +#define CYDEV_PM_AVAIL_SIZE 0x00000017 +#define CYREG_PM_AVAIL_CR0 0x400043c0 +#define CYREG_PM_AVAIL_CR1 0x400043c1 +#define CYREG_PM_AVAIL_CR2 0x400043c2 +#define CYREG_PM_AVAIL_CR3 0x400043c3 +#define CYREG_PM_AVAIL_CR4 0x400043c4 +#define CYREG_PM_AVAIL_CR5 0x400043c5 +#define CYREG_PM_AVAIL_CR6 0x400043c6 +#define CYREG_PM_AVAIL_SR0 0x400043d0 +#define CYREG_PM_AVAIL_SR1 0x400043d1 +#define CYREG_PM_AVAIL_SR2 0x400043d2 +#define CYREG_PM_AVAIL_SR3 0x400043d3 +#define CYREG_PM_AVAIL_SR4 0x400043d4 +#define CYREG_PM_AVAIL_SR5 0x400043d5 +#define CYREG_PM_AVAIL_SR6 0x400043d6 +#define CYDEV_PICU_BASE 0x40004500 +#define CYDEV_PICU_SIZE 0x000000b0 +#define CYDEV_PICU_INTTYPE_BASE 0x40004500 +#define CYDEV_PICU_INTTYPE_SIZE 0x00000080 +#define CYDEV_PICU_INTTYPE_PICU0_BASE 0x40004500 +#define CYDEV_PICU_INTTYPE_PICU0_SIZE 0x00000008 +#define CYREG_PICU0_INTTYPE0 0x40004500 +#define CYREG_PICU0_INTTYPE1 0x40004501 +#define CYREG_PICU0_INTTYPE2 0x40004502 +#define CYREG_PICU0_INTTYPE3 0x40004503 +#define CYREG_PICU0_INTTYPE4 0x40004504 +#define CYREG_PICU0_INTTYPE5 0x40004505 +#define CYREG_PICU0_INTTYPE6 0x40004506 +#define CYREG_PICU0_INTTYPE7 0x40004507 +#define CYDEV_PICU_INTTYPE_PICU1_BASE 0x40004508 +#define CYDEV_PICU_INTTYPE_PICU1_SIZE 0x00000008 +#define CYREG_PICU1_INTTYPE0 0x40004508 +#define CYREG_PICU1_INTTYPE1 0x40004509 +#define CYREG_PICU1_INTTYPE2 0x4000450a +#define CYREG_PICU1_INTTYPE3 0x4000450b +#define CYREG_PICU1_INTTYPE4 0x4000450c +#define CYREG_PICU1_INTTYPE5 0x4000450d +#define CYREG_PICU1_INTTYPE6 0x4000450e +#define CYREG_PICU1_INTTYPE7 0x4000450f +#define CYDEV_PICU_INTTYPE_PICU2_BASE 0x40004510 +#define CYDEV_PICU_INTTYPE_PICU2_SIZE 0x00000008 +#define CYREG_PICU2_INTTYPE0 0x40004510 +#define CYREG_PICU2_INTTYPE1 0x40004511 +#define CYREG_PICU2_INTTYPE2 0x40004512 +#define CYREG_PICU2_INTTYPE3 0x40004513 +#define CYREG_PICU2_INTTYPE4 0x40004514 +#define CYREG_PICU2_INTTYPE5 0x40004515 +#define CYREG_PICU2_INTTYPE6 0x40004516 +#define CYREG_PICU2_INTTYPE7 0x40004517 +#define CYDEV_PICU_INTTYPE_PICU3_BASE 0x40004518 +#define CYDEV_PICU_INTTYPE_PICU3_SIZE 0x00000008 +#define CYREG_PICU3_INTTYPE0 0x40004518 +#define CYREG_PICU3_INTTYPE1 0x40004519 +#define CYREG_PICU3_INTTYPE2 0x4000451a +#define CYREG_PICU3_INTTYPE3 0x4000451b +#define CYREG_PICU3_INTTYPE4 0x4000451c +#define CYREG_PICU3_INTTYPE5 0x4000451d +#define CYREG_PICU3_INTTYPE6 0x4000451e +#define CYREG_PICU3_INTTYPE7 0x4000451f +#define CYDEV_PICU_INTTYPE_PICU4_BASE 0x40004520 +#define CYDEV_PICU_INTTYPE_PICU4_SIZE 0x00000008 +#define CYREG_PICU4_INTTYPE0 0x40004520 +#define CYREG_PICU4_INTTYPE1 0x40004521 +#define CYREG_PICU4_INTTYPE2 0x40004522 +#define CYREG_PICU4_INTTYPE3 0x40004523 +#define CYREG_PICU4_INTTYPE4 0x40004524 +#define CYREG_PICU4_INTTYPE5 0x40004525 +#define CYREG_PICU4_INTTYPE6 0x40004526 +#define CYREG_PICU4_INTTYPE7 0x40004527 +#define CYDEV_PICU_INTTYPE_PICU5_BASE 0x40004528 +#define CYDEV_PICU_INTTYPE_PICU5_SIZE 0x00000008 +#define CYREG_PICU5_INTTYPE0 0x40004528 +#define CYREG_PICU5_INTTYPE1 0x40004529 +#define CYREG_PICU5_INTTYPE2 0x4000452a +#define CYREG_PICU5_INTTYPE3 0x4000452b +#define CYREG_PICU5_INTTYPE4 0x4000452c +#define CYREG_PICU5_INTTYPE5 0x4000452d +#define CYREG_PICU5_INTTYPE6 0x4000452e +#define CYREG_PICU5_INTTYPE7 0x4000452f +#define CYDEV_PICU_INTTYPE_PICU6_BASE 0x40004530 +#define CYDEV_PICU_INTTYPE_PICU6_SIZE 0x00000008 +#define CYREG_PICU6_INTTYPE0 0x40004530 +#define CYREG_PICU6_INTTYPE1 0x40004531 +#define CYREG_PICU6_INTTYPE2 0x40004532 +#define CYREG_PICU6_INTTYPE3 0x40004533 +#define CYREG_PICU6_INTTYPE4 0x40004534 +#define CYREG_PICU6_INTTYPE5 0x40004535 +#define CYREG_PICU6_INTTYPE6 0x40004536 +#define CYREG_PICU6_INTTYPE7 0x40004537 +#define CYDEV_PICU_INTTYPE_PICU12_BASE 0x40004560 +#define CYDEV_PICU_INTTYPE_PICU12_SIZE 0x00000008 +#define CYREG_PICU12_INTTYPE0 0x40004560 +#define CYREG_PICU12_INTTYPE1 0x40004561 +#define CYREG_PICU12_INTTYPE2 0x40004562 +#define CYREG_PICU12_INTTYPE3 0x40004563 +#define CYREG_PICU12_INTTYPE4 0x40004564 +#define CYREG_PICU12_INTTYPE5 0x40004565 +#define CYREG_PICU12_INTTYPE6 0x40004566 +#define CYREG_PICU12_INTTYPE7 0x40004567 +#define CYDEV_PICU_INTTYPE_PICU15_BASE 0x40004578 +#define CYDEV_PICU_INTTYPE_PICU15_SIZE 0x00000008 +#define CYREG_PICU15_INTTYPE0 0x40004578 +#define CYREG_PICU15_INTTYPE1 0x40004579 +#define CYREG_PICU15_INTTYPE2 0x4000457a +#define CYREG_PICU15_INTTYPE3 0x4000457b +#define CYREG_PICU15_INTTYPE4 0x4000457c +#define CYREG_PICU15_INTTYPE5 0x4000457d +#define CYREG_PICU15_INTTYPE6 0x4000457e +#define CYREG_PICU15_INTTYPE7 0x4000457f +#define CYDEV_PICU_STAT_BASE 0x40004580 +#define CYDEV_PICU_STAT_SIZE 0x00000010 +#define CYDEV_PICU_STAT_PICU0_BASE 0x40004580 +#define CYDEV_PICU_STAT_PICU0_SIZE 0x00000001 +#define CYREG_PICU0_INTSTAT 0x40004580 +#define CYDEV_PICU_STAT_PICU1_BASE 0x40004581 +#define CYDEV_PICU_STAT_PICU1_SIZE 0x00000001 +#define CYREG_PICU1_INTSTAT 0x40004581 +#define CYDEV_PICU_STAT_PICU2_BASE 0x40004582 +#define CYDEV_PICU_STAT_PICU2_SIZE 0x00000001 +#define CYREG_PICU2_INTSTAT 0x40004582 +#define CYDEV_PICU_STAT_PICU3_BASE 0x40004583 +#define CYDEV_PICU_STAT_PICU3_SIZE 0x00000001 +#define CYREG_PICU3_INTSTAT 0x40004583 +#define CYDEV_PICU_STAT_PICU4_BASE 0x40004584 +#define CYDEV_PICU_STAT_PICU4_SIZE 0x00000001 +#define CYREG_PICU4_INTSTAT 0x40004584 +#define CYDEV_PICU_STAT_PICU5_BASE 0x40004585 +#define CYDEV_PICU_STAT_PICU5_SIZE 0x00000001 +#define CYREG_PICU5_INTSTAT 0x40004585 +#define CYDEV_PICU_STAT_PICU6_BASE 0x40004586 +#define CYDEV_PICU_STAT_PICU6_SIZE 0x00000001 +#define CYREG_PICU6_INTSTAT 0x40004586 +#define CYDEV_PICU_STAT_PICU12_BASE 0x4000458c +#define CYDEV_PICU_STAT_PICU12_SIZE 0x00000001 +#define CYREG_PICU12_INTSTAT 0x4000458c +#define CYDEV_PICU_STAT_PICU15_BASE 0x4000458f +#define CYDEV_PICU_STAT_PICU15_SIZE 0x00000001 +#define CYREG_PICU15_INTSTAT 0x4000458f +#define CYDEV_PICU_SNAP_BASE 0x40004590 +#define CYDEV_PICU_SNAP_SIZE 0x00000010 +#define CYDEV_PICU_SNAP_PICU0_BASE 0x40004590 +#define CYDEV_PICU_SNAP_PICU0_SIZE 0x00000001 +#define CYREG_PICU0_SNAP 0x40004590 +#define CYDEV_PICU_SNAP_PICU1_BASE 0x40004591 +#define CYDEV_PICU_SNAP_PICU1_SIZE 0x00000001 +#define CYREG_PICU1_SNAP 0x40004591 +#define CYDEV_PICU_SNAP_PICU2_BASE 0x40004592 +#define CYDEV_PICU_SNAP_PICU2_SIZE 0x00000001 +#define CYREG_PICU2_SNAP 0x40004592 +#define CYDEV_PICU_SNAP_PICU3_BASE 0x40004593 +#define CYDEV_PICU_SNAP_PICU3_SIZE 0x00000001 +#define CYREG_PICU3_SNAP 0x40004593 +#define CYDEV_PICU_SNAP_PICU4_BASE 0x40004594 +#define CYDEV_PICU_SNAP_PICU4_SIZE 0x00000001 +#define CYREG_PICU4_SNAP 0x40004594 +#define CYDEV_PICU_SNAP_PICU5_BASE 0x40004595 +#define CYDEV_PICU_SNAP_PICU5_SIZE 0x00000001 +#define CYREG_PICU5_SNAP 0x40004595 +#define CYDEV_PICU_SNAP_PICU6_BASE 0x40004596 +#define CYDEV_PICU_SNAP_PICU6_SIZE 0x00000001 +#define CYREG_PICU6_SNAP 0x40004596 +#define CYDEV_PICU_SNAP_PICU12_BASE 0x4000459c +#define CYDEV_PICU_SNAP_PICU12_SIZE 0x00000001 +#define CYREG_PICU12_SNAP 0x4000459c +#define CYDEV_PICU_SNAP_PICU_15_BASE 0x4000459f +#define CYDEV_PICU_SNAP_PICU_15_SIZE 0x00000001 +#define CYREG_PICU_15_SNAP_15 0x4000459f +#define CYDEV_PICU_DISABLE_COR_BASE 0x400045a0 +#define CYDEV_PICU_DISABLE_COR_SIZE 0x00000010 +#define CYDEV_PICU_DISABLE_COR_PICU0_BASE 0x400045a0 +#define CYDEV_PICU_DISABLE_COR_PICU0_SIZE 0x00000001 +#define CYREG_PICU0_DISABLE_COR 0x400045a0 +#define CYDEV_PICU_DISABLE_COR_PICU1_BASE 0x400045a1 +#define CYDEV_PICU_DISABLE_COR_PICU1_SIZE 0x00000001 +#define CYREG_PICU1_DISABLE_COR 0x400045a1 +#define CYDEV_PICU_DISABLE_COR_PICU2_BASE 0x400045a2 +#define CYDEV_PICU_DISABLE_COR_PICU2_SIZE 0x00000001 +#define CYREG_PICU2_DISABLE_COR 0x400045a2 +#define CYDEV_PICU_DISABLE_COR_PICU3_BASE 0x400045a3 +#define CYDEV_PICU_DISABLE_COR_PICU3_SIZE 0x00000001 +#define CYREG_PICU3_DISABLE_COR 0x400045a3 +#define CYDEV_PICU_DISABLE_COR_PICU4_BASE 0x400045a4 +#define CYDEV_PICU_DISABLE_COR_PICU4_SIZE 0x00000001 +#define CYREG_PICU4_DISABLE_COR 0x400045a4 +#define CYDEV_PICU_DISABLE_COR_PICU5_BASE 0x400045a5 +#define CYDEV_PICU_DISABLE_COR_PICU5_SIZE 0x00000001 +#define CYREG_PICU5_DISABLE_COR 0x400045a5 +#define CYDEV_PICU_DISABLE_COR_PICU6_BASE 0x400045a6 +#define CYDEV_PICU_DISABLE_COR_PICU6_SIZE 0x00000001 +#define CYREG_PICU6_DISABLE_COR 0x400045a6 +#define CYDEV_PICU_DISABLE_COR_PICU12_BASE 0x400045ac +#define CYDEV_PICU_DISABLE_COR_PICU12_SIZE 0x00000001 +#define CYREG_PICU12_DISABLE_COR 0x400045ac +#define CYDEV_PICU_DISABLE_COR_PICU15_BASE 0x400045af +#define CYDEV_PICU_DISABLE_COR_PICU15_SIZE 0x00000001 +#define CYREG_PICU15_DISABLE_COR 0x400045af +#define CYDEV_MFGCFG_BASE 0x40004600 +#define CYDEV_MFGCFG_SIZE 0x000000ed +#define CYDEV_MFGCFG_ANAIF_BASE 0x40004600 +#define CYDEV_MFGCFG_ANAIF_SIZE 0x00000038 +#define CYDEV_MFGCFG_ANAIF_DAC0_BASE 0x40004608 +#define CYDEV_MFGCFG_ANAIF_DAC0_SIZE 0x00000001 +#define CYREG_DAC0_TR 0x40004608 +#define CYDEV_MFGCFG_ANAIF_DAC1_BASE 0x40004609 +#define CYDEV_MFGCFG_ANAIF_DAC1_SIZE 0x00000001 +#define CYREG_DAC1_TR 0x40004609 +#define CYDEV_MFGCFG_ANAIF_DAC2_BASE 0x4000460a +#define CYDEV_MFGCFG_ANAIF_DAC2_SIZE 0x00000001 +#define CYREG_DAC2_TR 0x4000460a +#define CYDEV_MFGCFG_ANAIF_DAC3_BASE 0x4000460b +#define CYDEV_MFGCFG_ANAIF_DAC3_SIZE 0x00000001 +#define CYREG_DAC3_TR 0x4000460b +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE 0x40004610 +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE 0x00000001 +#define CYREG_NPUMP_DSM_TR0 0x40004610 +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE 0x40004611 +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE 0x00000001 +#define CYREG_NPUMP_SC_TR0 0x40004611 +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE 0x40004612 +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE 0x00000001 +#define CYREG_NPUMP_OPAMP_TR0 0x40004612 +#define CYDEV_MFGCFG_ANAIF_SAR0_BASE 0x40004614 +#define CYDEV_MFGCFG_ANAIF_SAR0_SIZE 0x00000001 +#define CYREG_SAR0_TR0 0x40004614 +#define CYDEV_MFGCFG_ANAIF_SAR1_BASE 0x40004616 +#define CYDEV_MFGCFG_ANAIF_SAR1_SIZE 0x00000001 +#define CYREG_SAR1_TR0 0x40004616 +#define CYDEV_MFGCFG_ANAIF_OPAMP0_BASE 0x40004620 +#define CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE 0x00000002 +#define CYREG_OPAMP0_TR0 0x40004620 +#define CYREG_OPAMP0_TR1 0x40004621 +#define CYDEV_MFGCFG_ANAIF_OPAMP1_BASE 0x40004622 +#define CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE 0x00000002 +#define CYREG_OPAMP1_TR0 0x40004622 +#define CYREG_OPAMP1_TR1 0x40004623 +#define CYDEV_MFGCFG_ANAIF_OPAMP2_BASE 0x40004624 +#define CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE 0x00000002 +#define CYREG_OPAMP2_TR0 0x40004624 +#define CYREG_OPAMP2_TR1 0x40004625 +#define CYDEV_MFGCFG_ANAIF_OPAMP3_BASE 0x40004626 +#define CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE 0x00000002 +#define CYREG_OPAMP3_TR0 0x40004626 +#define CYREG_OPAMP3_TR1 0x40004627 +#define CYDEV_MFGCFG_ANAIF_CMP0_BASE 0x40004630 +#define CYDEV_MFGCFG_ANAIF_CMP0_SIZE 0x00000002 +#define CYREG_CMP0_TR0 0x40004630 +#define CYREG_CMP0_TR1 0x40004631 +#define CYDEV_MFGCFG_ANAIF_CMP1_BASE 0x40004632 +#define CYDEV_MFGCFG_ANAIF_CMP1_SIZE 0x00000002 +#define CYREG_CMP1_TR0 0x40004632 +#define CYREG_CMP1_TR1 0x40004633 +#define CYDEV_MFGCFG_ANAIF_CMP2_BASE 0x40004634 +#define CYDEV_MFGCFG_ANAIF_CMP2_SIZE 0x00000002 +#define CYREG_CMP2_TR0 0x40004634 +#define CYREG_CMP2_TR1 0x40004635 +#define CYDEV_MFGCFG_ANAIF_CMP3_BASE 0x40004636 +#define CYDEV_MFGCFG_ANAIF_CMP3_SIZE 0x00000002 +#define CYREG_CMP3_TR0 0x40004636 +#define CYREG_CMP3_TR1 0x40004637 +#define CYDEV_MFGCFG_PWRSYS_BASE 0x40004680 +#define CYDEV_MFGCFG_PWRSYS_SIZE 0x0000000b +#define CYREG_PWRSYS_HIB_TR0 0x40004680 +#define CYREG_PWRSYS_HIB_TR1 0x40004681 +#define CYREG_PWRSYS_I2C_TR 0x40004682 +#define CYREG_PWRSYS_SLP_TR 0x40004683 +#define CYREG_PWRSYS_BUZZ_TR 0x40004684 +#define CYREG_PWRSYS_WAKE_TR0 0x40004685 +#define CYREG_PWRSYS_WAKE_TR1 0x40004686 +#define CYREG_PWRSYS_BREF_TR 0x40004687 +#define CYREG_PWRSYS_BG_TR 0x40004688 +#define CYREG_PWRSYS_WAKE_TR2 0x40004689 +#define CYREG_PWRSYS_WAKE_TR3 0x4000468a +#define CYDEV_MFGCFG_ILO_BASE 0x40004690 +#define CYDEV_MFGCFG_ILO_SIZE 0x00000002 +#define CYREG_ILO_TR0 0x40004690 +#define CYREG_ILO_TR1 0x40004691 +#define CYDEV_MFGCFG_X32_BASE 0x40004698 +#define CYDEV_MFGCFG_X32_SIZE 0x00000001 +#define CYREG_X32_TR 0x40004698 +#define CYDEV_MFGCFG_IMO_BASE 0x400046a0 +#define CYDEV_MFGCFG_IMO_SIZE 0x00000005 +#define CYREG_IMO_TR0 0x400046a0 +#define CYREG_IMO_TR1 0x400046a1 +#define CYREG_IMO_GAIN 0x400046a2 +#define CYREG_IMO_C36M 0x400046a3 +#define CYREG_IMO_TR2 0x400046a4 +#define CYDEV_MFGCFG_XMHZ_BASE 0x400046a8 +#define CYDEV_MFGCFG_XMHZ_SIZE 0x00000001 +#define CYREG_XMHZ_TR 0x400046a8 +#define CYREG_MFGCFG_DLY 0x400046c0 +#define CYDEV_MFGCFG_MLOGIC_BASE 0x400046e0 +#define CYDEV_MFGCFG_MLOGIC_SIZE 0x0000000d +#define CYREG_MLOGIC_DMPSTR 0x400046e2 +#define CYDEV_MFGCFG_MLOGIC_SEG_BASE 0x400046e4 +#define CYDEV_MFGCFG_MLOGIC_SEG_SIZE 0x00000002 +#define CYREG_MLOGIC_SEG_CR 0x400046e4 +#define CYREG_MLOGIC_SEG_CFG0 0x400046e5 +#define CYREG_MLOGIC_DEBUG 0x400046e8 +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE 0x400046ea +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE 0x00000001 +#define CYREG_MLOGIC_CPU_SCR_CPU_SCR 0x400046ea +#define CYREG_MLOGIC_REV_ID 0x400046ec +#define CYDEV_RESET_BASE 0x400046f0 +#define CYDEV_RESET_SIZE 0x0000000f +#define CYREG_RESET_IPOR_CR0 0x400046f0 +#define CYREG_RESET_IPOR_CR1 0x400046f1 +#define CYREG_RESET_IPOR_CR2 0x400046f2 +#define CYREG_RESET_IPOR_CR3 0x400046f3 +#define CYREG_RESET_CR0 0x400046f4 +#define CYREG_RESET_CR1 0x400046f5 +#define CYREG_RESET_CR2 0x400046f6 +#define CYREG_RESET_CR3 0x400046f7 +#define CYREG_RESET_CR4 0x400046f8 +#define CYREG_RESET_CR5 0x400046f9 +#define CYREG_RESET_SR0 0x400046fa +#define CYREG_RESET_SR1 0x400046fb +#define CYREG_RESET_SR2 0x400046fc +#define CYREG_RESET_SR3 0x400046fd +#define CYREG_RESET_TR 0x400046fe +#define CYDEV_SPC_BASE 0x40004700 +#define CYDEV_SPC_SIZE 0x00000100 +#define CYREG_SPC_FM_EE_CR 0x40004700 +#define CYREG_SPC_FM_EE_WAKE_CNT 0x40004701 +#define CYREG_SPC_EE_SCR 0x40004702 +#define CYREG_SPC_EE_ERR 0x40004703 +#define CYREG_SPC_CPU_DATA 0x40004720 +#define CYREG_SPC_DMA_DATA 0x40004721 +#define CYREG_SPC_SR 0x40004722 +#define CYREG_SPC_CR 0x40004723 +#define CYDEV_SPC_DMM_MAP_BASE 0x40004780 +#define CYDEV_SPC_DMM_MAP_SIZE 0x00000080 +#define CYREG_SPC_DMM_MAP_SRAM_MBASE 0x40004780 +#define CYREG_SPC_DMM_MAP_SRAM_MSIZE 0x00000080 +#define CYDEV_CACHE_BASE 0x40004800 +#define CYDEV_CACHE_SIZE 0x0000009c +#define CYREG_CACHE_CC_CTL 0x40004800 +#define CYREG_CACHE_ECC_CORR 0x40004880 +#define CYREG_CACHE_ECC_ERR 0x40004888 +#define CYREG_CACHE_FLASH_ERR 0x40004890 +#define CYREG_CACHE_HITMISS 0x40004898 +#define CYDEV_I2C_BASE 0x40004900 +#define CYDEV_I2C_SIZE 0x000000e1 +#define CYREG_I2C_XCFG 0x400049c8 +#define CYREG_I2C_ADR 0x400049ca +#define CYREG_I2C_CFG 0x400049d6 +#define CYREG_I2C_CSR 0x400049d7 +#define CYREG_I2C_D 0x400049d8 +#define CYREG_I2C_MCSR 0x400049d9 +#define CYREG_I2C_CLK_DIV1 0x400049db +#define CYREG_I2C_CLK_DIV2 0x400049dc +#define CYREG_I2C_TMOUT_CSR 0x400049dd +#define CYREG_I2C_TMOUT_SR 0x400049de +#define CYREG_I2C_TMOUT_CFG0 0x400049df +#define CYREG_I2C_TMOUT_CFG1 0x400049e0 +#define CYDEV_DEC_BASE 0x40004e00 +#define CYDEV_DEC_SIZE 0x00000015 +#define CYREG_DEC_CR 0x40004e00 +#define CYREG_DEC_SR 0x40004e01 +#define CYREG_DEC_SHIFT1 0x40004e02 +#define CYREG_DEC_SHIFT2 0x40004e03 +#define CYREG_DEC_DR2 0x40004e04 +#define CYREG_DEC_DR2H 0x40004e05 +#define CYREG_DEC_DR1 0x40004e06 +#define CYREG_DEC_OCOR 0x40004e08 +#define CYREG_DEC_OCORM 0x40004e09 +#define CYREG_DEC_OCORH 0x40004e0a +#define CYREG_DEC_GCOR 0x40004e0c +#define CYREG_DEC_GCORH 0x40004e0d +#define CYREG_DEC_GVAL 0x40004e0e +#define CYREG_DEC_OUTSAMP 0x40004e10 +#define CYREG_DEC_OUTSAMPM 0x40004e11 +#define CYREG_DEC_OUTSAMPH 0x40004e12 +#define CYREG_DEC_OUTSAMPS 0x40004e13 +#define CYREG_DEC_COHER 0x40004e14 +#define CYDEV_TMR0_BASE 0x40004f00 +#define CYDEV_TMR0_SIZE 0x0000000c +#define CYREG_TMR0_CFG0 0x40004f00 +#define CYREG_TMR0_CFG1 0x40004f01 +#define CYREG_TMR0_CFG2 0x40004f02 +#define CYREG_TMR0_SR0 0x40004f03 +#define CYREG_TMR0_PER0 0x40004f04 +#define CYREG_TMR0_PER1 0x40004f05 +#define CYREG_TMR0_CNT_CMP0 0x40004f06 +#define CYREG_TMR0_CNT_CMP1 0x40004f07 +#define CYREG_TMR0_CAP0 0x40004f08 +#define CYREG_TMR0_CAP1 0x40004f09 +#define CYREG_TMR0_RT0 0x40004f0a +#define CYREG_TMR0_RT1 0x40004f0b +#define CYDEV_TMR1_BASE 0x40004f0c +#define CYDEV_TMR1_SIZE 0x0000000c +#define CYREG_TMR1_CFG0 0x40004f0c +#define CYREG_TMR1_CFG1 0x40004f0d +#define CYREG_TMR1_CFG2 0x40004f0e +#define CYREG_TMR1_SR0 0x40004f0f +#define CYREG_TMR1_PER0 0x40004f10 +#define CYREG_TMR1_PER1 0x40004f11 +#define CYREG_TMR1_CNT_CMP0 0x40004f12 +#define CYREG_TMR1_CNT_CMP1 0x40004f13 +#define CYREG_TMR1_CAP0 0x40004f14 +#define CYREG_TMR1_CAP1 0x40004f15 +#define CYREG_TMR1_RT0 0x40004f16 +#define CYREG_TMR1_RT1 0x40004f17 +#define CYDEV_TMR2_BASE 0x40004f18 +#define CYDEV_TMR2_SIZE 0x0000000c +#define CYREG_TMR2_CFG0 0x40004f18 +#define CYREG_TMR2_CFG1 0x40004f19 +#define CYREG_TMR2_CFG2 0x40004f1a +#define CYREG_TMR2_SR0 0x40004f1b +#define CYREG_TMR2_PER0 0x40004f1c +#define CYREG_TMR2_PER1 0x40004f1d +#define CYREG_TMR2_CNT_CMP0 0x40004f1e +#define CYREG_TMR2_CNT_CMP1 0x40004f1f +#define CYREG_TMR2_CAP0 0x40004f20 +#define CYREG_TMR2_CAP1 0x40004f21 +#define CYREG_TMR2_RT0 0x40004f22 +#define CYREG_TMR2_RT1 0x40004f23 +#define CYDEV_TMR3_BASE 0x40004f24 +#define CYDEV_TMR3_SIZE 0x0000000c +#define CYREG_TMR3_CFG0 0x40004f24 +#define CYREG_TMR3_CFG1 0x40004f25 +#define CYREG_TMR3_CFG2 0x40004f26 +#define CYREG_TMR3_SR0 0x40004f27 +#define CYREG_TMR3_PER0 0x40004f28 +#define CYREG_TMR3_PER1 0x40004f29 +#define CYREG_TMR3_CNT_CMP0 0x40004f2a +#define CYREG_TMR3_CNT_CMP1 0x40004f2b +#define CYREG_TMR3_CAP0 0x40004f2c +#define CYREG_TMR3_CAP1 0x40004f2d +#define CYREG_TMR3_RT0 0x40004f2e +#define CYREG_TMR3_RT1 0x40004f2f +#define CYDEV_IO_BASE 0x40005000 +#define CYDEV_IO_SIZE 0x00000200 +#define CYDEV_IO_PC_BASE 0x40005000 +#define CYDEV_IO_PC_SIZE 0x00000080 +#define CYDEV_IO_PC_PRT0_BASE 0x40005000 +#define CYDEV_IO_PC_PRT0_SIZE 0x00000008 +#define CYREG_PRT0_PC0 0x40005000 +#define CYREG_PRT0_PC1 0x40005001 +#define CYREG_PRT0_PC2 0x40005002 +#define CYREG_PRT0_PC3 0x40005003 +#define CYREG_PRT0_PC4 0x40005004 +#define CYREG_PRT0_PC5 0x40005005 +#define CYREG_PRT0_PC6 0x40005006 +#define CYREG_PRT0_PC7 0x40005007 +#define CYDEV_IO_PC_PRT1_BASE 0x40005008 +#define CYDEV_IO_PC_PRT1_SIZE 0x00000008 +#define CYREG_PRT1_PC0 0x40005008 +#define CYREG_PRT1_PC1 0x40005009 +#define CYREG_PRT1_PC2 0x4000500a +#define CYREG_PRT1_PC3 0x4000500b +#define CYREG_PRT1_PC4 0x4000500c +#define CYREG_PRT1_PC5 0x4000500d +#define CYREG_PRT1_PC6 0x4000500e +#define CYREG_PRT1_PC7 0x4000500f +#define CYDEV_IO_PC_PRT2_BASE 0x40005010 +#define CYDEV_IO_PC_PRT2_SIZE 0x00000008 +#define CYREG_PRT2_PC0 0x40005010 +#define CYREG_PRT2_PC1 0x40005011 +#define CYREG_PRT2_PC2 0x40005012 +#define CYREG_PRT2_PC3 0x40005013 +#define CYREG_PRT2_PC4 0x40005014 +#define CYREG_PRT2_PC5 0x40005015 +#define CYREG_PRT2_PC6 0x40005016 +#define CYREG_PRT2_PC7 0x40005017 +#define CYDEV_IO_PC_PRT3_BASE 0x40005018 +#define CYDEV_IO_PC_PRT3_SIZE 0x00000008 +#define CYREG_PRT3_PC0 0x40005018 +#define CYREG_PRT3_PC1 0x40005019 +#define CYREG_PRT3_PC2 0x4000501a +#define CYREG_PRT3_PC3 0x4000501b +#define CYREG_PRT3_PC4 0x4000501c +#define CYREG_PRT3_PC5 0x4000501d +#define CYREG_PRT3_PC6 0x4000501e +#define CYREG_PRT3_PC7 0x4000501f +#define CYDEV_IO_PC_PRT4_BASE 0x40005020 +#define CYDEV_IO_PC_PRT4_SIZE 0x00000008 +#define CYREG_PRT4_PC0 0x40005020 +#define CYREG_PRT4_PC1 0x40005021 +#define CYREG_PRT4_PC2 0x40005022 +#define CYREG_PRT4_PC3 0x40005023 +#define CYREG_PRT4_PC4 0x40005024 +#define CYREG_PRT4_PC5 0x40005025 +#define CYREG_PRT4_PC6 0x40005026 +#define CYREG_PRT4_PC7 0x40005027 +#define CYDEV_IO_PC_PRT5_BASE 0x40005028 +#define CYDEV_IO_PC_PRT5_SIZE 0x00000008 +#define CYREG_PRT5_PC0 0x40005028 +#define CYREG_PRT5_PC1 0x40005029 +#define CYREG_PRT5_PC2 0x4000502a +#define CYREG_PRT5_PC3 0x4000502b +#define CYREG_PRT5_PC4 0x4000502c +#define CYREG_PRT5_PC5 0x4000502d +#define CYREG_PRT5_PC6 0x4000502e +#define CYREG_PRT5_PC7 0x4000502f +#define CYDEV_IO_PC_PRT6_BASE 0x40005030 +#define CYDEV_IO_PC_PRT6_SIZE 0x00000008 +#define CYREG_PRT6_PC0 0x40005030 +#define CYREG_PRT6_PC1 0x40005031 +#define CYREG_PRT6_PC2 0x40005032 +#define CYREG_PRT6_PC3 0x40005033 +#define CYREG_PRT6_PC4 0x40005034 +#define CYREG_PRT6_PC5 0x40005035 +#define CYREG_PRT6_PC6 0x40005036 +#define CYREG_PRT6_PC7 0x40005037 +#define CYDEV_IO_PC_PRT12_BASE 0x40005060 +#define CYDEV_IO_PC_PRT12_SIZE 0x00000008 +#define CYREG_PRT12_PC0 0x40005060 +#define CYREG_PRT12_PC1 0x40005061 +#define CYREG_PRT12_PC2 0x40005062 +#define CYREG_PRT12_PC3 0x40005063 +#define CYREG_PRT12_PC4 0x40005064 +#define CYREG_PRT12_PC5 0x40005065 +#define CYREG_PRT12_PC6 0x40005066 +#define CYREG_PRT12_PC7 0x40005067 +#define CYDEV_IO_PC_PRT15_BASE 0x40005078 +#define CYDEV_IO_PC_PRT15_SIZE 0x00000006 +#define CYREG_IO_PC_PRT15_PC0 0x40005078 +#define CYREG_IO_PC_PRT15_PC1 0x40005079 +#define CYREG_IO_PC_PRT15_PC2 0x4000507a +#define CYREG_IO_PC_PRT15_PC3 0x4000507b +#define CYREG_IO_PC_PRT15_PC4 0x4000507c +#define CYREG_IO_PC_PRT15_PC5 0x4000507d +#define CYDEV_IO_PC_PRT15_7_6_BASE 0x4000507e +#define CYDEV_IO_PC_PRT15_7_6_SIZE 0x00000002 +#define CYREG_IO_PC_PRT15_7_6_PC0 0x4000507e +#define CYREG_IO_PC_PRT15_7_6_PC1 0x4000507f +#define CYDEV_IO_DR_BASE 0x40005080 +#define CYDEV_IO_DR_SIZE 0x00000010 +#define CYDEV_IO_DR_PRT0_BASE 0x40005080 +#define CYDEV_IO_DR_PRT0_SIZE 0x00000001 +#define CYREG_PRT0_DR_ALIAS 0x40005080 +#define CYDEV_IO_DR_PRT1_BASE 0x40005081 +#define CYDEV_IO_DR_PRT1_SIZE 0x00000001 +#define CYREG_PRT1_DR_ALIAS 0x40005081 +#define CYDEV_IO_DR_PRT2_BASE 0x40005082 +#define CYDEV_IO_DR_PRT2_SIZE 0x00000001 +#define CYREG_PRT2_DR_ALIAS 0x40005082 +#define CYDEV_IO_DR_PRT3_BASE 0x40005083 +#define CYDEV_IO_DR_PRT3_SIZE 0x00000001 +#define CYREG_PRT3_DR_ALIAS 0x40005083 +#define CYDEV_IO_DR_PRT4_BASE 0x40005084 +#define CYDEV_IO_DR_PRT4_SIZE 0x00000001 +#define CYREG_PRT4_DR_ALIAS 0x40005084 +#define CYDEV_IO_DR_PRT5_BASE 0x40005085 +#define CYDEV_IO_DR_PRT5_SIZE 0x00000001 +#define CYREG_PRT5_DR_ALIAS 0x40005085 +#define CYDEV_IO_DR_PRT6_BASE 0x40005086 +#define CYDEV_IO_DR_PRT6_SIZE 0x00000001 +#define CYREG_PRT6_DR_ALIAS 0x40005086 +#define CYDEV_IO_DR_PRT12_BASE 0x4000508c +#define CYDEV_IO_DR_PRT12_SIZE 0x00000001 +#define CYREG_PRT12_DR_ALIAS 0x4000508c +#define CYDEV_IO_DR_PRT15_BASE 0x4000508f +#define CYDEV_IO_DR_PRT15_SIZE 0x00000001 +#define CYREG_PRT15_DR_15_ALIAS 0x4000508f +#define CYDEV_IO_PS_BASE 0x40005090 +#define CYDEV_IO_PS_SIZE 0x00000010 +#define CYDEV_IO_PS_PRT0_BASE 0x40005090 +#define CYDEV_IO_PS_PRT0_SIZE 0x00000001 +#define CYREG_PRT0_PS_ALIAS 0x40005090 +#define CYDEV_IO_PS_PRT1_BASE 0x40005091 +#define CYDEV_IO_PS_PRT1_SIZE 0x00000001 +#define CYREG_PRT1_PS_ALIAS 0x40005091 +#define CYDEV_IO_PS_PRT2_BASE 0x40005092 +#define CYDEV_IO_PS_PRT2_SIZE 0x00000001 +#define CYREG_PRT2_PS_ALIAS 0x40005092 +#define CYDEV_IO_PS_PRT3_BASE 0x40005093 +#define CYDEV_IO_PS_PRT3_SIZE 0x00000001 +#define CYREG_PRT3_PS_ALIAS 0x40005093 +#define CYDEV_IO_PS_PRT4_BASE 0x40005094 +#define CYDEV_IO_PS_PRT4_SIZE 0x00000001 +#define CYREG_PRT4_PS_ALIAS 0x40005094 +#define CYDEV_IO_PS_PRT5_BASE 0x40005095 +#define CYDEV_IO_PS_PRT5_SIZE 0x00000001 +#define CYREG_PRT5_PS_ALIAS 0x40005095 +#define CYDEV_IO_PS_PRT6_BASE 0x40005096 +#define CYDEV_IO_PS_PRT6_SIZE 0x00000001 +#define CYREG_PRT6_PS_ALIAS 0x40005096 +#define CYDEV_IO_PS_PRT12_BASE 0x4000509c +#define CYDEV_IO_PS_PRT12_SIZE 0x00000001 +#define CYREG_PRT12_PS_ALIAS 0x4000509c +#define CYDEV_IO_PS_PRT15_BASE 0x4000509f +#define CYDEV_IO_PS_PRT15_SIZE 0x00000001 +#define CYREG_PRT15_PS15_ALIAS 0x4000509f +#define CYDEV_IO_PRT_BASE 0x40005100 +#define CYDEV_IO_PRT_SIZE 0x00000100 +#define CYDEV_IO_PRT_PRT0_BASE 0x40005100 +#define CYDEV_IO_PRT_PRT0_SIZE 0x00000010 +#define CYREG_PRT0_DR 0x40005100 +#define CYREG_PRT0_PS 0x40005101 +#define CYREG_PRT0_DM0 0x40005102 +#define CYREG_PRT0_DM1 0x40005103 +#define CYREG_PRT0_DM2 0x40005104 +#define CYREG_PRT0_SLW 0x40005105 +#define CYREG_PRT0_BYP 0x40005106 +#define CYREG_PRT0_BIE 0x40005107 +#define CYREG_PRT0_INP_DIS 0x40005108 +#define CYREG_PRT0_CTL 0x40005109 +#define CYREG_PRT0_PRT 0x4000510a +#define CYREG_PRT0_BIT_MASK 0x4000510b +#define CYREG_PRT0_AMUX 0x4000510c +#define CYREG_PRT0_AG 0x4000510d +#define CYREG_PRT0_LCD_COM_SEG 0x4000510e +#define CYREG_PRT0_LCD_EN 0x4000510f +#define CYDEV_IO_PRT_PRT1_BASE 0x40005110 +#define CYDEV_IO_PRT_PRT1_SIZE 0x00000010 +#define CYREG_PRT1_DR 0x40005110 +#define CYREG_PRT1_PS 0x40005111 +#define CYREG_PRT1_DM0 0x40005112 +#define CYREG_PRT1_DM1 0x40005113 +#define CYREG_PRT1_DM2 0x40005114 +#define CYREG_PRT1_SLW 0x40005115 +#define CYREG_PRT1_BYP 0x40005116 +#define CYREG_PRT1_BIE 0x40005117 +#define CYREG_PRT1_INP_DIS 0x40005118 +#define CYREG_PRT1_CTL 0x40005119 +#define CYREG_PRT1_PRT 0x4000511a +#define CYREG_PRT1_BIT_MASK 0x4000511b +#define CYREG_PRT1_AMUX 0x4000511c +#define CYREG_PRT1_AG 0x4000511d +#define CYREG_PRT1_LCD_COM_SEG 0x4000511e +#define CYREG_PRT1_LCD_EN 0x4000511f +#define CYDEV_IO_PRT_PRT2_BASE 0x40005120 +#define CYDEV_IO_PRT_PRT2_SIZE 0x00000010 +#define CYREG_PRT2_DR 0x40005120 +#define CYREG_PRT2_PS 0x40005121 +#define CYREG_PRT2_DM0 0x40005122 +#define CYREG_PRT2_DM1 0x40005123 +#define CYREG_PRT2_DM2 0x40005124 +#define CYREG_PRT2_SLW 0x40005125 +#define CYREG_PRT2_BYP 0x40005126 +#define CYREG_PRT2_BIE 0x40005127 +#define CYREG_PRT2_INP_DIS 0x40005128 +#define CYREG_PRT2_CTL 0x40005129 +#define CYREG_PRT2_PRT 0x4000512a +#define CYREG_PRT2_BIT_MASK 0x4000512b +#define CYREG_PRT2_AMUX 0x4000512c +#define CYREG_PRT2_AG 0x4000512d +#define CYREG_PRT2_LCD_COM_SEG 0x4000512e +#define CYREG_PRT2_LCD_EN 0x4000512f +#define CYDEV_IO_PRT_PRT3_BASE 0x40005130 +#define CYDEV_IO_PRT_PRT3_SIZE 0x00000010 +#define CYREG_PRT3_DR 0x40005130 +#define CYREG_PRT3_PS 0x40005131 +#define CYREG_PRT3_DM0 0x40005132 +#define CYREG_PRT3_DM1 0x40005133 +#define CYREG_PRT3_DM2 0x40005134 +#define CYREG_PRT3_SLW 0x40005135 +#define CYREG_PRT3_BYP 0x40005136 +#define CYREG_PRT3_BIE 0x40005137 +#define CYREG_PRT3_INP_DIS 0x40005138 +#define CYREG_PRT3_CTL 0x40005139 +#define CYREG_PRT3_PRT 0x4000513a +#define CYREG_PRT3_BIT_MASK 0x4000513b +#define CYREG_PRT3_AMUX 0x4000513c +#define CYREG_PRT3_AG 0x4000513d +#define CYREG_PRT3_LCD_COM_SEG 0x4000513e +#define CYREG_PRT3_LCD_EN 0x4000513f +#define CYDEV_IO_PRT_PRT4_BASE 0x40005140 +#define CYDEV_IO_PRT_PRT4_SIZE 0x00000010 +#define CYREG_PRT4_DR 0x40005140 +#define CYREG_PRT4_PS 0x40005141 +#define CYREG_PRT4_DM0 0x40005142 +#define CYREG_PRT4_DM1 0x40005143 +#define CYREG_PRT4_DM2 0x40005144 +#define CYREG_PRT4_SLW 0x40005145 +#define CYREG_PRT4_BYP 0x40005146 +#define CYREG_PRT4_BIE 0x40005147 +#define CYREG_PRT4_INP_DIS 0x40005148 +#define CYREG_PRT4_CTL 0x40005149 +#define CYREG_PRT4_PRT 0x4000514a +#define CYREG_PRT4_BIT_MASK 0x4000514b +#define CYREG_PRT4_AMUX 0x4000514c +#define CYREG_PRT4_AG 0x4000514d +#define CYREG_PRT4_LCD_COM_SEG 0x4000514e +#define CYREG_PRT4_LCD_EN 0x4000514f +#define CYDEV_IO_PRT_PRT5_BASE 0x40005150 +#define CYDEV_IO_PRT_PRT5_SIZE 0x00000010 +#define CYREG_PRT5_DR 0x40005150 +#define CYREG_PRT5_PS 0x40005151 +#define CYREG_PRT5_DM0 0x40005152 +#define CYREG_PRT5_DM1 0x40005153 +#define CYREG_PRT5_DM2 0x40005154 +#define CYREG_PRT5_SLW 0x40005155 +#define CYREG_PRT5_BYP 0x40005156 +#define CYREG_PRT5_BIE 0x40005157 +#define CYREG_PRT5_INP_DIS 0x40005158 +#define CYREG_PRT5_CTL 0x40005159 +#define CYREG_PRT5_PRT 0x4000515a +#define CYREG_PRT5_BIT_MASK 0x4000515b +#define CYREG_PRT5_AMUX 0x4000515c +#define CYREG_PRT5_AG 0x4000515d +#define CYREG_PRT5_LCD_COM_SEG 0x4000515e +#define CYREG_PRT5_LCD_EN 0x4000515f +#define CYDEV_IO_PRT_PRT6_BASE 0x40005160 +#define CYDEV_IO_PRT_PRT6_SIZE 0x00000010 +#define CYREG_PRT6_DR 0x40005160 +#define CYREG_PRT6_PS 0x40005161 +#define CYREG_PRT6_DM0 0x40005162 +#define CYREG_PRT6_DM1 0x40005163 +#define CYREG_PRT6_DM2 0x40005164 +#define CYREG_PRT6_SLW 0x40005165 +#define CYREG_PRT6_BYP 0x40005166 +#define CYREG_PRT6_BIE 0x40005167 +#define CYREG_PRT6_INP_DIS 0x40005168 +#define CYREG_PRT6_CTL 0x40005169 +#define CYREG_PRT6_PRT 0x4000516a +#define CYREG_PRT6_BIT_MASK 0x4000516b +#define CYREG_PRT6_AMUX 0x4000516c +#define CYREG_PRT6_AG 0x4000516d +#define CYREG_PRT6_LCD_COM_SEG 0x4000516e +#define CYREG_PRT6_LCD_EN 0x4000516f +#define CYDEV_IO_PRT_PRT12_BASE 0x400051c0 +#define CYDEV_IO_PRT_PRT12_SIZE 0x00000010 +#define CYREG_PRT12_DR 0x400051c0 +#define CYREG_PRT12_PS 0x400051c1 +#define CYREG_PRT12_DM0 0x400051c2 +#define CYREG_PRT12_DM1 0x400051c3 +#define CYREG_PRT12_DM2 0x400051c4 +#define CYREG_PRT12_SLW 0x400051c5 +#define CYREG_PRT12_BYP 0x400051c6 +#define CYREG_PRT12_BIE 0x400051c7 +#define CYREG_PRT12_INP_DIS 0x400051c8 +#define CYREG_PRT12_SIO_HYST_EN 0x400051c9 +#define CYREG_PRT12_PRT 0x400051ca +#define CYREG_PRT12_BIT_MASK 0x400051cb +#define CYREG_PRT12_SIO_REG_HIFREQ 0x400051cc +#define CYREG_PRT12_AG 0x400051cd +#define CYREG_PRT12_SIO_CFG 0x400051ce +#define CYREG_PRT12_SIO_DIFF 0x400051cf +#define CYDEV_IO_PRT_PRT15_BASE 0x400051f0 +#define CYDEV_IO_PRT_PRT15_SIZE 0x00000010 +#define CYREG_PRT15_DR 0x400051f0 +#define CYREG_PRT15_PS 0x400051f1 +#define CYREG_PRT15_DM0 0x400051f2 +#define CYREG_PRT15_DM1 0x400051f3 +#define CYREG_PRT15_DM2 0x400051f4 +#define CYREG_PRT15_SLW 0x400051f5 +#define CYREG_PRT15_BYP 0x400051f6 +#define CYREG_PRT15_BIE 0x400051f7 +#define CYREG_PRT15_INP_DIS 0x400051f8 +#define CYREG_PRT15_CTL 0x400051f9 +#define CYREG_PRT15_PRT 0x400051fa +#define CYREG_PRT15_BIT_MASK 0x400051fb +#define CYREG_PRT15_AMUX 0x400051fc +#define CYREG_PRT15_AG 0x400051fd +#define CYREG_PRT15_LCD_COM_SEG 0x400051fe +#define CYREG_PRT15_LCD_EN 0x400051ff +#define CYDEV_PRTDSI_BASE 0x40005200 +#define CYDEV_PRTDSI_SIZE 0x0000007f +#define CYDEV_PRTDSI_PRT0_BASE 0x40005200 +#define CYDEV_PRTDSI_PRT0_SIZE 0x00000007 +#define CYREG_PRT0_OUT_SEL0 0x40005200 +#define CYREG_PRT0_OUT_SEL1 0x40005201 +#define CYREG_PRT0_OE_SEL0 0x40005202 +#define CYREG_PRT0_OE_SEL1 0x40005203 +#define CYREG_PRT0_DBL_SYNC_IN 0x40005204 +#define CYREG_PRT0_SYNC_OUT 0x40005205 +#define CYREG_PRT0_CAPS_SEL 0x40005206 +#define CYDEV_PRTDSI_PRT1_BASE 0x40005208 +#define CYDEV_PRTDSI_PRT1_SIZE 0x00000007 +#define CYREG_PRT1_OUT_SEL0 0x40005208 +#define CYREG_PRT1_OUT_SEL1 0x40005209 +#define CYREG_PRT1_OE_SEL0 0x4000520a +#define CYREG_PRT1_OE_SEL1 0x4000520b +#define CYREG_PRT1_DBL_SYNC_IN 0x4000520c +#define CYREG_PRT1_SYNC_OUT 0x4000520d +#define CYREG_PRT1_CAPS_SEL 0x4000520e +#define CYDEV_PRTDSI_PRT2_BASE 0x40005210 +#define CYDEV_PRTDSI_PRT2_SIZE 0x00000007 +#define CYREG_PRT2_OUT_SEL0 0x40005210 +#define CYREG_PRT2_OUT_SEL1 0x40005211 +#define CYREG_PRT2_OE_SEL0 0x40005212 +#define CYREG_PRT2_OE_SEL1 0x40005213 +#define CYREG_PRT2_DBL_SYNC_IN 0x40005214 +#define CYREG_PRT2_SYNC_OUT 0x40005215 +#define CYREG_PRT2_CAPS_SEL 0x40005216 +#define CYDEV_PRTDSI_PRT3_BASE 0x40005218 +#define CYDEV_PRTDSI_PRT3_SIZE 0x00000007 +#define CYREG_PRT3_OUT_SEL0 0x40005218 +#define CYREG_PRT3_OUT_SEL1 0x40005219 +#define CYREG_PRT3_OE_SEL0 0x4000521a +#define CYREG_PRT3_OE_SEL1 0x4000521b +#define CYREG_PRT3_DBL_SYNC_IN 0x4000521c +#define CYREG_PRT3_SYNC_OUT 0x4000521d +#define CYREG_PRT3_CAPS_SEL 0x4000521e +#define CYDEV_PRTDSI_PRT4_BASE 0x40005220 +#define CYDEV_PRTDSI_PRT4_SIZE 0x00000007 +#define CYREG_PRT4_OUT_SEL0 0x40005220 +#define CYREG_PRT4_OUT_SEL1 0x40005221 +#define CYREG_PRT4_OE_SEL0 0x40005222 +#define CYREG_PRT4_OE_SEL1 0x40005223 +#define CYREG_PRT4_DBL_SYNC_IN 0x40005224 +#define CYREG_PRT4_SYNC_OUT 0x40005225 +#define CYREG_PRT4_CAPS_SEL 0x40005226 +#define CYDEV_PRTDSI_PRT5_BASE 0x40005228 +#define CYDEV_PRTDSI_PRT5_SIZE 0x00000007 +#define CYREG_PRT5_OUT_SEL0 0x40005228 +#define CYREG_PRT5_OUT_SEL1 0x40005229 +#define CYREG_PRT5_OE_SEL0 0x4000522a +#define CYREG_PRT5_OE_SEL1 0x4000522b +#define CYREG_PRT5_DBL_SYNC_IN 0x4000522c +#define CYREG_PRT5_SYNC_OUT 0x4000522d +#define CYREG_PRT5_CAPS_SEL 0x4000522e +#define CYDEV_PRTDSI_PRT6_BASE 0x40005230 +#define CYDEV_PRTDSI_PRT6_SIZE 0x00000007 +#define CYREG_PRT6_OUT_SEL0 0x40005230 +#define CYREG_PRT6_OUT_SEL1 0x40005231 +#define CYREG_PRT6_OE_SEL0 0x40005232 +#define CYREG_PRT6_OE_SEL1 0x40005233 +#define CYREG_PRT6_DBL_SYNC_IN 0x40005234 +#define CYREG_PRT6_SYNC_OUT 0x40005235 +#define CYREG_PRT6_CAPS_SEL 0x40005236 +#define CYDEV_PRTDSI_PRT12_BASE 0x40005260 +#define CYDEV_PRTDSI_PRT12_SIZE 0x00000006 +#define CYREG_PRT12_OUT_SEL0 0x40005260 +#define CYREG_PRT12_OUT_SEL1 0x40005261 +#define CYREG_PRT12_OE_SEL0 0x40005262 +#define CYREG_PRT12_OE_SEL1 0x40005263 +#define CYREG_PRT12_DBL_SYNC_IN 0x40005264 +#define CYREG_PRT12_SYNC_OUT 0x40005265 +#define CYDEV_PRTDSI_PRT15_BASE 0x40005278 +#define CYDEV_PRTDSI_PRT15_SIZE 0x00000007 +#define CYREG_PRT15_OUT_SEL0 0x40005278 +#define CYREG_PRT15_OUT_SEL1 0x40005279 +#define CYREG_PRT15_OE_SEL0 0x4000527a +#define CYREG_PRT15_OE_SEL1 0x4000527b +#define CYREG_PRT15_DBL_SYNC_IN 0x4000527c +#define CYREG_PRT15_SYNC_OUT 0x4000527d +#define CYREG_PRT15_CAPS_SEL 0x4000527e +#define CYDEV_EMIF_BASE 0x40005400 +#define CYDEV_EMIF_SIZE 0x00000007 +#define CYREG_EMIF_NO_UDB 0x40005400 +#define CYREG_EMIF_RP_WAIT_STATES 0x40005401 +#define CYREG_EMIF_MEM_DWN 0x40005402 +#define CYREG_EMIF_MEMCLK_DIV 0x40005403 +#define CYREG_EMIF_CLOCK_EN 0x40005404 +#define CYREG_EMIF_EM_TYPE 0x40005405 +#define CYREG_EMIF_WP_WAIT_STATES 0x40005406 +#define CYDEV_ANAIF_BASE 0x40005800 +#define CYDEV_ANAIF_SIZE 0x000003a9 +#define CYDEV_ANAIF_CFG_BASE 0x40005800 +#define CYDEV_ANAIF_CFG_SIZE 0x0000010f +#define CYDEV_ANAIF_CFG_SC0_BASE 0x40005800 +#define CYDEV_ANAIF_CFG_SC0_SIZE 0x00000003 +#define CYREG_SC0_CR0 0x40005800 +#define CYREG_SC0_CR1 0x40005801 +#define CYREG_SC0_CR2 0x40005802 +#define CYDEV_ANAIF_CFG_SC1_BASE 0x40005804 +#define CYDEV_ANAIF_CFG_SC1_SIZE 0x00000003 +#define CYREG_SC1_CR0 0x40005804 +#define CYREG_SC1_CR1 0x40005805 +#define CYREG_SC1_CR2 0x40005806 +#define CYDEV_ANAIF_CFG_SC2_BASE 0x40005808 +#define CYDEV_ANAIF_CFG_SC2_SIZE 0x00000003 +#define CYREG_SC2_CR0 0x40005808 +#define CYREG_SC2_CR1 0x40005809 +#define CYREG_SC2_CR2 0x4000580a +#define CYDEV_ANAIF_CFG_SC3_BASE 0x4000580c +#define CYDEV_ANAIF_CFG_SC3_SIZE 0x00000003 +#define CYREG_SC3_CR0 0x4000580c +#define CYREG_SC3_CR1 0x4000580d +#define CYREG_SC3_CR2 0x4000580e +#define CYDEV_ANAIF_CFG_DAC0_BASE 0x40005820 +#define CYDEV_ANAIF_CFG_DAC0_SIZE 0x00000003 +#define CYREG_DAC0_CR0 0x40005820 +#define CYREG_DAC0_CR1 0x40005821 +#define CYREG_DAC0_TST 0x40005822 +#define CYDEV_ANAIF_CFG_DAC1_BASE 0x40005824 +#define CYDEV_ANAIF_CFG_DAC1_SIZE 0x00000003 +#define CYREG_DAC1_CR0 0x40005824 +#define CYREG_DAC1_CR1 0x40005825 +#define CYREG_DAC1_TST 0x40005826 +#define CYDEV_ANAIF_CFG_DAC2_BASE 0x40005828 +#define CYDEV_ANAIF_CFG_DAC2_SIZE 0x00000003 +#define CYREG_DAC2_CR0 0x40005828 +#define CYREG_DAC2_CR1 0x40005829 +#define CYREG_DAC2_TST 0x4000582a +#define CYDEV_ANAIF_CFG_DAC3_BASE 0x4000582c +#define CYDEV_ANAIF_CFG_DAC3_SIZE 0x00000003 +#define CYREG_DAC3_CR0 0x4000582c +#define CYREG_DAC3_CR1 0x4000582d +#define CYREG_DAC3_TST 0x4000582e +#define CYDEV_ANAIF_CFG_CMP0_BASE 0x40005840 +#define CYDEV_ANAIF_CFG_CMP0_SIZE 0x00000001 +#define CYREG_CMP0_CR 0x40005840 +#define CYDEV_ANAIF_CFG_CMP1_BASE 0x40005841 +#define CYDEV_ANAIF_CFG_CMP1_SIZE 0x00000001 +#define CYREG_CMP1_CR 0x40005841 +#define CYDEV_ANAIF_CFG_CMP2_BASE 0x40005842 +#define CYDEV_ANAIF_CFG_CMP2_SIZE 0x00000001 +#define CYREG_CMP2_CR 0x40005842 +#define CYDEV_ANAIF_CFG_CMP3_BASE 0x40005843 +#define CYDEV_ANAIF_CFG_CMP3_SIZE 0x00000001 +#define CYREG_CMP3_CR 0x40005843 +#define CYDEV_ANAIF_CFG_LUT0_BASE 0x40005848 +#define CYDEV_ANAIF_CFG_LUT0_SIZE 0x00000002 +#define CYREG_LUT0_CR 0x40005848 +#define CYREG_LUT0_MX 0x40005849 +#define CYDEV_ANAIF_CFG_LUT1_BASE 0x4000584a +#define CYDEV_ANAIF_CFG_LUT1_SIZE 0x00000002 +#define CYREG_LUT1_CR 0x4000584a +#define CYREG_LUT1_MX 0x4000584b +#define CYDEV_ANAIF_CFG_LUT2_BASE 0x4000584c +#define CYDEV_ANAIF_CFG_LUT2_SIZE 0x00000002 +#define CYREG_LUT2_CR 0x4000584c +#define CYREG_LUT2_MX 0x4000584d +#define CYDEV_ANAIF_CFG_LUT3_BASE 0x4000584e +#define CYDEV_ANAIF_CFG_LUT3_SIZE 0x00000002 +#define CYREG_LUT3_CR 0x4000584e +#define CYREG_LUT3_MX 0x4000584f +#define CYDEV_ANAIF_CFG_OPAMP0_BASE 0x40005858 +#define CYDEV_ANAIF_CFG_OPAMP0_SIZE 0x00000002 +#define CYREG_OPAMP0_CR 0x40005858 +#define CYREG_OPAMP0_RSVD 0x40005859 +#define CYDEV_ANAIF_CFG_OPAMP1_BASE 0x4000585a +#define CYDEV_ANAIF_CFG_OPAMP1_SIZE 0x00000002 +#define CYREG_OPAMP1_CR 0x4000585a +#define CYREG_OPAMP1_RSVD 0x4000585b +#define CYDEV_ANAIF_CFG_OPAMP2_BASE 0x4000585c +#define CYDEV_ANAIF_CFG_OPAMP2_SIZE 0x00000002 +#define CYREG_OPAMP2_CR 0x4000585c +#define CYREG_OPAMP2_RSVD 0x4000585d +#define CYDEV_ANAIF_CFG_OPAMP3_BASE 0x4000585e +#define CYDEV_ANAIF_CFG_OPAMP3_SIZE 0x00000002 +#define CYREG_OPAMP3_CR 0x4000585e +#define CYREG_OPAMP3_RSVD 0x4000585f +#define CYDEV_ANAIF_CFG_LCDDAC_BASE 0x40005868 +#define CYDEV_ANAIF_CFG_LCDDAC_SIZE 0x00000002 +#define CYREG_LCDDAC_CR0 0x40005868 +#define CYREG_LCDDAC_CR1 0x40005869 +#define CYDEV_ANAIF_CFG_LCDDRV_BASE 0x4000586a +#define CYDEV_ANAIF_CFG_LCDDRV_SIZE 0x00000001 +#define CYREG_LCDDRV_CR 0x4000586a +#define CYDEV_ANAIF_CFG_LCDTMR_BASE 0x4000586b +#define CYDEV_ANAIF_CFG_LCDTMR_SIZE 0x00000001 +#define CYREG_LCDTMR_CFG 0x4000586b +#define CYDEV_ANAIF_CFG_BG_BASE 0x4000586c +#define CYDEV_ANAIF_CFG_BG_SIZE 0x00000004 +#define CYREG_BG_CR0 0x4000586c +#define CYREG_BG_RSVD 0x4000586d +#define CYREG_BG_DFT0 0x4000586e +#define CYREG_BG_DFT1 0x4000586f +#define CYDEV_ANAIF_CFG_CAPSL_BASE 0x40005870 +#define CYDEV_ANAIF_CFG_CAPSL_SIZE 0x00000002 +#define CYREG_CAPSL_CFG0 0x40005870 +#define CYREG_CAPSL_CFG1 0x40005871 +#define CYDEV_ANAIF_CFG_CAPSR_BASE 0x40005872 +#define CYDEV_ANAIF_CFG_CAPSR_SIZE 0x00000002 +#define CYREG_CAPSR_CFG0 0x40005872 +#define CYREG_CAPSR_CFG1 0x40005873 +#define CYDEV_ANAIF_CFG_PUMP_BASE 0x40005876 +#define CYDEV_ANAIF_CFG_PUMP_SIZE 0x00000002 +#define CYREG_PUMP_CR0 0x40005876 +#define CYREG_PUMP_CR1 0x40005877 +#define CYDEV_ANAIF_CFG_LPF0_BASE 0x40005878 +#define CYDEV_ANAIF_CFG_LPF0_SIZE 0x00000002 +#define CYREG_LPF0_CR0 0x40005878 +#define CYREG_LPF0_RSVD 0x40005879 +#define CYDEV_ANAIF_CFG_LPF1_BASE 0x4000587a +#define CYDEV_ANAIF_CFG_LPF1_SIZE 0x00000002 +#define CYREG_LPF1_CR0 0x4000587a +#define CYREG_LPF1_RSVD 0x4000587b +#define CYDEV_ANAIF_CFG_MISC_BASE 0x4000587c +#define CYDEV_ANAIF_CFG_MISC_SIZE 0x00000001 +#define CYREG_ANAIF_CFG_MISC_CR0 0x4000587c +#define CYDEV_ANAIF_CFG_DSM0_BASE 0x40005880 +#define CYDEV_ANAIF_CFG_DSM0_SIZE 0x00000020 +#define CYREG_DSM0_CR0 0x40005880 +#define CYREG_DSM0_CR1 0x40005881 +#define CYREG_DSM0_CR2 0x40005882 +#define CYREG_DSM0_CR3 0x40005883 +#define CYREG_DSM0_CR4 0x40005884 +#define CYREG_DSM0_CR5 0x40005885 +#define CYREG_DSM0_CR6 0x40005886 +#define CYREG_DSM0_CR7 0x40005887 +#define CYREG_DSM0_CR8 0x40005888 +#define CYREG_DSM0_CR9 0x40005889 +#define CYREG_DSM0_CR10 0x4000588a +#define CYREG_DSM0_CR11 0x4000588b +#define CYREG_DSM0_CR12 0x4000588c +#define CYREG_DSM0_CR13 0x4000588d +#define CYREG_DSM0_CR14 0x4000588e +#define CYREG_DSM0_CR15 0x4000588f +#define CYREG_DSM0_CR16 0x40005890 +#define CYREG_DSM0_CR17 0x40005891 +#define CYREG_DSM0_REF0 0x40005892 +#define CYREG_DSM0_REF1 0x40005893 +#define CYREG_DSM0_REF2 0x40005894 +#define CYREG_DSM0_REF3 0x40005895 +#define CYREG_DSM0_DEM0 0x40005896 +#define CYREG_DSM0_DEM1 0x40005897 +#define CYREG_DSM0_TST0 0x40005898 +#define CYREG_DSM0_TST1 0x40005899 +#define CYREG_DSM0_BUF0 0x4000589a +#define CYREG_DSM0_BUF1 0x4000589b +#define CYREG_DSM0_BUF2 0x4000589c +#define CYREG_DSM0_BUF3 0x4000589d +#define CYREG_DSM0_MISC 0x4000589e +#define CYREG_DSM0_RSVD1 0x4000589f +#define CYDEV_ANAIF_CFG_SAR0_BASE 0x40005900 +#define CYDEV_ANAIF_CFG_SAR0_SIZE 0x00000007 +#define CYREG_SAR0_CSR0 0x40005900 +#define CYREG_SAR0_CSR1 0x40005901 +#define CYREG_SAR0_CSR2 0x40005902 +#define CYREG_SAR0_CSR3 0x40005903 +#define CYREG_SAR0_CSR4 0x40005904 +#define CYREG_SAR0_CSR5 0x40005905 +#define CYREG_SAR0_CSR6 0x40005906 +#define CYDEV_ANAIF_CFG_SAR1_BASE 0x40005908 +#define CYDEV_ANAIF_CFG_SAR1_SIZE 0x00000007 +#define CYREG_SAR1_CSR0 0x40005908 +#define CYREG_SAR1_CSR1 0x40005909 +#define CYREG_SAR1_CSR2 0x4000590a +#define CYREG_SAR1_CSR3 0x4000590b +#define CYREG_SAR1_CSR4 0x4000590c +#define CYREG_SAR1_CSR5 0x4000590d +#define CYREG_SAR1_CSR6 0x4000590e +#define CYDEV_ANAIF_RT_BASE 0x40005a00 +#define CYDEV_ANAIF_RT_SIZE 0x00000162 +#define CYDEV_ANAIF_RT_SC0_BASE 0x40005a00 +#define CYDEV_ANAIF_RT_SC0_SIZE 0x0000000d +#define CYREG_SC0_SW0 0x40005a00 +#define CYREG_SC0_SW2 0x40005a02 +#define CYREG_SC0_SW3 0x40005a03 +#define CYREG_SC0_SW4 0x40005a04 +#define CYREG_SC0_SW6 0x40005a06 +#define CYREG_SC0_SW7 0x40005a07 +#define CYREG_SC0_SW8 0x40005a08 +#define CYREG_SC0_SW10 0x40005a0a +#define CYREG_SC0_CLK 0x40005a0b +#define CYREG_SC0_BST 0x40005a0c +#define CYDEV_ANAIF_RT_SC1_BASE 0x40005a10 +#define CYDEV_ANAIF_RT_SC1_SIZE 0x0000000d +#define CYREG_SC1_SW0 0x40005a10 +#define CYREG_SC1_SW2 0x40005a12 +#define CYREG_SC1_SW3 0x40005a13 +#define CYREG_SC1_SW4 0x40005a14 +#define CYREG_SC1_SW6 0x40005a16 +#define CYREG_SC1_SW7 0x40005a17 +#define CYREG_SC1_SW8 0x40005a18 +#define CYREG_SC1_SW10 0x40005a1a +#define CYREG_SC1_CLK 0x40005a1b +#define CYREG_SC1_BST 0x40005a1c +#define CYDEV_ANAIF_RT_SC2_BASE 0x40005a20 +#define CYDEV_ANAIF_RT_SC2_SIZE 0x0000000d +#define CYREG_SC2_SW0 0x40005a20 +#define CYREG_SC2_SW2 0x40005a22 +#define CYREG_SC2_SW3 0x40005a23 +#define CYREG_SC2_SW4 0x40005a24 +#define CYREG_SC2_SW6 0x40005a26 +#define CYREG_SC2_SW7 0x40005a27 +#define CYREG_SC2_SW8 0x40005a28 +#define CYREG_SC2_SW10 0x40005a2a +#define CYREG_SC2_CLK 0x40005a2b +#define CYREG_SC2_BST 0x40005a2c +#define CYDEV_ANAIF_RT_SC3_BASE 0x40005a30 +#define CYDEV_ANAIF_RT_SC3_SIZE 0x0000000d +#define CYREG_SC3_SW0 0x40005a30 +#define CYREG_SC3_SW2 0x40005a32 +#define CYREG_SC3_SW3 0x40005a33 +#define CYREG_SC3_SW4 0x40005a34 +#define CYREG_SC3_SW6 0x40005a36 +#define CYREG_SC3_SW7 0x40005a37 +#define CYREG_SC3_SW8 0x40005a38 +#define CYREG_SC3_SW10 0x40005a3a +#define CYREG_SC3_CLK 0x40005a3b +#define CYREG_SC3_BST 0x40005a3c +#define CYDEV_ANAIF_RT_DAC0_BASE 0x40005a80 +#define CYDEV_ANAIF_RT_DAC0_SIZE 0x00000008 +#define CYREG_DAC0_SW0 0x40005a80 +#define CYREG_DAC0_SW2 0x40005a82 +#define CYREG_DAC0_SW3 0x40005a83 +#define CYREG_DAC0_SW4 0x40005a84 +#define CYREG_DAC0_STROBE 0x40005a87 +#define CYDEV_ANAIF_RT_DAC1_BASE 0x40005a88 +#define CYDEV_ANAIF_RT_DAC1_SIZE 0x00000008 +#define CYREG_DAC1_SW0 0x40005a88 +#define CYREG_DAC1_SW2 0x40005a8a +#define CYREG_DAC1_SW3 0x40005a8b +#define CYREG_DAC1_SW4 0x40005a8c +#define CYREG_DAC1_STROBE 0x40005a8f +#define CYDEV_ANAIF_RT_DAC2_BASE 0x40005a90 +#define CYDEV_ANAIF_RT_DAC2_SIZE 0x00000008 +#define CYREG_DAC2_SW0 0x40005a90 +#define CYREG_DAC2_SW2 0x40005a92 +#define CYREG_DAC2_SW3 0x40005a93 +#define CYREG_DAC2_SW4 0x40005a94 +#define CYREG_DAC2_STROBE 0x40005a97 +#define CYDEV_ANAIF_RT_DAC3_BASE 0x40005a98 +#define CYDEV_ANAIF_RT_DAC3_SIZE 0x00000008 +#define CYREG_DAC3_SW0 0x40005a98 +#define CYREG_DAC3_SW2 0x40005a9a +#define CYREG_DAC3_SW3 0x40005a9b +#define CYREG_DAC3_SW4 0x40005a9c +#define CYREG_DAC3_STROBE 0x40005a9f +#define CYDEV_ANAIF_RT_CMP0_BASE 0x40005ac0 +#define CYDEV_ANAIF_RT_CMP0_SIZE 0x00000008 +#define CYREG_CMP0_SW0 0x40005ac0 +#define CYREG_CMP0_SW2 0x40005ac2 +#define CYREG_CMP0_SW3 0x40005ac3 +#define CYREG_CMP0_SW4 0x40005ac4 +#define CYREG_CMP0_SW6 0x40005ac6 +#define CYREG_CMP0_CLK 0x40005ac7 +#define CYDEV_ANAIF_RT_CMP1_BASE 0x40005ac8 +#define CYDEV_ANAIF_RT_CMP1_SIZE 0x00000008 +#define CYREG_CMP1_SW0 0x40005ac8 +#define CYREG_CMP1_SW2 0x40005aca +#define CYREG_CMP1_SW3 0x40005acb +#define CYREG_CMP1_SW4 0x40005acc +#define CYREG_CMP1_SW6 0x40005ace +#define CYREG_CMP1_CLK 0x40005acf +#define CYDEV_ANAIF_RT_CMP2_BASE 0x40005ad0 +#define CYDEV_ANAIF_RT_CMP2_SIZE 0x00000008 +#define CYREG_CMP2_SW0 0x40005ad0 +#define CYREG_CMP2_SW2 0x40005ad2 +#define CYREG_CMP2_SW3 0x40005ad3 +#define CYREG_CMP2_SW4 0x40005ad4 +#define CYREG_CMP2_SW6 0x40005ad6 +#define CYREG_CMP2_CLK 0x40005ad7 +#define CYDEV_ANAIF_RT_CMP3_BASE 0x40005ad8 +#define CYDEV_ANAIF_RT_CMP3_SIZE 0x00000008 +#define CYREG_CMP3_SW0 0x40005ad8 +#define CYREG_CMP3_SW2 0x40005ada +#define CYREG_CMP3_SW3 0x40005adb +#define CYREG_CMP3_SW4 0x40005adc +#define CYREG_CMP3_SW6 0x40005ade +#define CYREG_CMP3_CLK 0x40005adf +#define CYDEV_ANAIF_RT_DSM0_BASE 0x40005b00 +#define CYDEV_ANAIF_RT_DSM0_SIZE 0x00000008 +#define CYREG_DSM0_SW0 0x40005b00 +#define CYREG_DSM0_SW2 0x40005b02 +#define CYREG_DSM0_SW3 0x40005b03 +#define CYREG_DSM0_SW4 0x40005b04 +#define CYREG_DSM0_SW6 0x40005b06 +#define CYREG_DSM0_CLK 0x40005b07 +#define CYDEV_ANAIF_RT_SAR0_BASE 0x40005b20 +#define CYDEV_ANAIF_RT_SAR0_SIZE 0x00000008 +#define CYREG_SAR0_SW0 0x40005b20 +#define CYREG_SAR0_SW2 0x40005b22 +#define CYREG_SAR0_SW3 0x40005b23 +#define CYREG_SAR0_SW4 0x40005b24 +#define CYREG_SAR0_SW6 0x40005b26 +#define CYREG_SAR0_CLK 0x40005b27 +#define CYDEV_ANAIF_RT_SAR1_BASE 0x40005b28 +#define CYDEV_ANAIF_RT_SAR1_SIZE 0x00000008 +#define CYREG_SAR1_SW0 0x40005b28 +#define CYREG_SAR1_SW2 0x40005b2a +#define CYREG_SAR1_SW3 0x40005b2b +#define CYREG_SAR1_SW4 0x40005b2c +#define CYREG_SAR1_SW6 0x40005b2e +#define CYREG_SAR1_CLK 0x40005b2f +#define CYDEV_ANAIF_RT_OPAMP0_BASE 0x40005b40 +#define CYDEV_ANAIF_RT_OPAMP0_SIZE 0x00000002 +#define CYREG_OPAMP0_MX 0x40005b40 +#define CYREG_OPAMP0_SW 0x40005b41 +#define CYDEV_ANAIF_RT_OPAMP1_BASE 0x40005b42 +#define CYDEV_ANAIF_RT_OPAMP1_SIZE 0x00000002 +#define CYREG_OPAMP1_MX 0x40005b42 +#define CYREG_OPAMP1_SW 0x40005b43 +#define CYDEV_ANAIF_RT_OPAMP2_BASE 0x40005b44 +#define CYDEV_ANAIF_RT_OPAMP2_SIZE 0x00000002 +#define CYREG_OPAMP2_MX 0x40005b44 +#define CYREG_OPAMP2_SW 0x40005b45 +#define CYDEV_ANAIF_RT_OPAMP3_BASE 0x40005b46 +#define CYDEV_ANAIF_RT_OPAMP3_SIZE 0x00000002 +#define CYREG_OPAMP3_MX 0x40005b46 +#define CYREG_OPAMP3_SW 0x40005b47 +#define CYDEV_ANAIF_RT_LCDDAC_BASE 0x40005b50 +#define CYDEV_ANAIF_RT_LCDDAC_SIZE 0x00000005 +#define CYREG_LCDDAC_SW0 0x40005b50 +#define CYREG_LCDDAC_SW1 0x40005b51 +#define CYREG_LCDDAC_SW2 0x40005b52 +#define CYREG_LCDDAC_SW3 0x40005b53 +#define CYREG_LCDDAC_SW4 0x40005b54 +#define CYDEV_ANAIF_RT_SC_BASE 0x40005b56 +#define CYDEV_ANAIF_RT_SC_SIZE 0x00000001 +#define CYREG_SC_MISC 0x40005b56 +#define CYDEV_ANAIF_RT_BUS_BASE 0x40005b58 +#define CYDEV_ANAIF_RT_BUS_SIZE 0x00000004 +#define CYREG_BUS_SW0 0x40005b58 +#define CYREG_BUS_SW2 0x40005b5a +#define CYREG_BUS_SW3 0x40005b5b +#define CYDEV_ANAIF_RT_DFT_BASE 0x40005b5c +#define CYDEV_ANAIF_RT_DFT_SIZE 0x00000006 +#define CYREG_DFT_CR0 0x40005b5c +#define CYREG_DFT_CR1 0x40005b5d +#define CYREG_DFT_CR2 0x40005b5e +#define CYREG_DFT_CR3 0x40005b5f +#define CYREG_DFT_CR4 0x40005b60 +#define CYREG_DFT_CR5 0x40005b61 +#define CYDEV_ANAIF_WRK_BASE 0x40005b80 +#define CYDEV_ANAIF_WRK_SIZE 0x00000029 +#define CYDEV_ANAIF_WRK_DAC0_BASE 0x40005b80 +#define CYDEV_ANAIF_WRK_DAC0_SIZE 0x00000001 +#define CYREG_DAC0_D 0x40005b80 +#define CYDEV_ANAIF_WRK_DAC1_BASE 0x40005b81 +#define CYDEV_ANAIF_WRK_DAC1_SIZE 0x00000001 +#define CYREG_DAC1_D 0x40005b81 +#define CYDEV_ANAIF_WRK_DAC2_BASE 0x40005b82 +#define CYDEV_ANAIF_WRK_DAC2_SIZE 0x00000001 +#define CYREG_DAC2_D 0x40005b82 +#define CYDEV_ANAIF_WRK_DAC3_BASE 0x40005b83 +#define CYDEV_ANAIF_WRK_DAC3_SIZE 0x00000001 +#define CYREG_DAC3_D 0x40005b83 +#define CYDEV_ANAIF_WRK_DSM0_BASE 0x40005b88 +#define CYDEV_ANAIF_WRK_DSM0_SIZE 0x00000002 +#define CYREG_DSM0_OUT0 0x40005b88 +#define CYREG_DSM0_OUT1 0x40005b89 +#define CYDEV_ANAIF_WRK_LUT_BASE 0x40005b90 +#define CYDEV_ANAIF_WRK_LUT_SIZE 0x00000005 +#define CYREG_LUT_SR 0x40005b90 +#define CYREG_LUT_WRK1 0x40005b91 +#define CYREG_LUT_MSK 0x40005b92 +#define CYREG_LUT_CLK 0x40005b93 +#define CYREG_LUT_CPTR 0x40005b94 +#define CYDEV_ANAIF_WRK_CMP_BASE 0x40005b96 +#define CYDEV_ANAIF_WRK_CMP_SIZE 0x00000002 +#define CYREG_CMP_WRK 0x40005b96 +#define CYREG_CMP_TST 0x40005b97 +#define CYDEV_ANAIF_WRK_SC_BASE 0x40005b98 +#define CYDEV_ANAIF_WRK_SC_SIZE 0x00000005 +#define CYREG_SC_SR 0x40005b98 +#define CYREG_SC_WRK1 0x40005b99 +#define CYREG_SC_MSK 0x40005b9a +#define CYREG_SC_CMPINV 0x40005b9b +#define CYREG_SC_CPTR 0x40005b9c +#define CYDEV_ANAIF_WRK_SAR0_BASE 0x40005ba0 +#define CYDEV_ANAIF_WRK_SAR0_SIZE 0x00000002 +#define CYREG_SAR0_WRK0 0x40005ba0 +#define CYREG_SAR0_WRK1 0x40005ba1 +#define CYDEV_ANAIF_WRK_SAR1_BASE 0x40005ba2 +#define CYDEV_ANAIF_WRK_SAR1_SIZE 0x00000002 +#define CYREG_SAR1_WRK0 0x40005ba2 +#define CYREG_SAR1_WRK1 0x40005ba3 +#define CYDEV_ANAIF_WRK_SARS_BASE 0x40005ba8 +#define CYDEV_ANAIF_WRK_SARS_SIZE 0x00000001 +#define CYREG_ANAIF_WRK_SARS_SOF 0x40005ba8 +#define CYDEV_USB_BASE 0x40006000 +#define CYDEV_USB_SIZE 0x00000300 +#define CYREG_USB_EP0_DR0 0x40006000 +#define CYREG_USB_EP0_DR1 0x40006001 +#define CYREG_USB_EP0_DR2 0x40006002 +#define CYREG_USB_EP0_DR3 0x40006003 +#define CYREG_USB_EP0_DR4 0x40006004 +#define CYREG_USB_EP0_DR5 0x40006005 +#define CYREG_USB_EP0_DR6 0x40006006 +#define CYREG_USB_EP0_DR7 0x40006007 +#define CYREG_USB_CR0 0x40006008 +#define CYREG_USB_CR1 0x40006009 +#define CYREG_USB_SIE_EP_INT_EN 0x4000600a +#define CYREG_USB_SIE_EP_INT_SR 0x4000600b +#define CYDEV_USB_SIE_EP1_BASE 0x4000600c +#define CYDEV_USB_SIE_EP1_SIZE 0x00000003 +#define CYREG_USB_SIE_EP1_CNT0 0x4000600c +#define CYREG_USB_SIE_EP1_CNT1 0x4000600d +#define CYREG_USB_SIE_EP1_CR0 0x4000600e +#define CYREG_USB_USBIO_CR0 0x40006010 +#define CYREG_USB_USBIO_CR1 0x40006012 +#define CYREG_USB_DYN_RECONFIG 0x40006014 +#define CYREG_USB_SOF0 0x40006018 +#define CYREG_USB_SOF1 0x40006019 +#define CYDEV_USB_SIE_EP2_BASE 0x4000601c +#define CYDEV_USB_SIE_EP2_SIZE 0x00000003 +#define CYREG_USB_SIE_EP2_CNT0 0x4000601c +#define CYREG_USB_SIE_EP2_CNT1 0x4000601d +#define CYREG_USB_SIE_EP2_CR0 0x4000601e +#define CYREG_USB_EP0_CR 0x40006028 +#define CYREG_USB_EP0_CNT 0x40006029 +#define CYDEV_USB_SIE_EP3_BASE 0x4000602c +#define CYDEV_USB_SIE_EP3_SIZE 0x00000003 +#define CYREG_USB_SIE_EP3_CNT0 0x4000602c +#define CYREG_USB_SIE_EP3_CNT1 0x4000602d +#define CYREG_USB_SIE_EP3_CR0 0x4000602e +#define CYDEV_USB_SIE_EP4_BASE 0x4000603c +#define CYDEV_USB_SIE_EP4_SIZE 0x00000003 +#define CYREG_USB_SIE_EP4_CNT0 0x4000603c +#define CYREG_USB_SIE_EP4_CNT1 0x4000603d +#define CYREG_USB_SIE_EP4_CR0 0x4000603e +#define CYDEV_USB_SIE_EP5_BASE 0x4000604c +#define CYDEV_USB_SIE_EP5_SIZE 0x00000003 +#define CYREG_USB_SIE_EP5_CNT0 0x4000604c +#define CYREG_USB_SIE_EP5_CNT1 0x4000604d +#define CYREG_USB_SIE_EP5_CR0 0x4000604e +#define CYDEV_USB_SIE_EP6_BASE 0x4000605c +#define CYDEV_USB_SIE_EP6_SIZE 0x00000003 +#define CYREG_USB_SIE_EP6_CNT0 0x4000605c +#define CYREG_USB_SIE_EP6_CNT1 0x4000605d +#define CYREG_USB_SIE_EP6_CR0 0x4000605e +#define CYDEV_USB_SIE_EP7_BASE 0x4000606c +#define CYDEV_USB_SIE_EP7_SIZE 0x00000003 +#define CYREG_USB_SIE_EP7_CNT0 0x4000606c +#define CYREG_USB_SIE_EP7_CNT1 0x4000606d +#define CYREG_USB_SIE_EP7_CR0 0x4000606e +#define CYDEV_USB_SIE_EP8_BASE 0x4000607c +#define CYDEV_USB_SIE_EP8_SIZE 0x00000003 +#define CYREG_USB_SIE_EP8_CNT0 0x4000607c +#define CYREG_USB_SIE_EP8_CNT1 0x4000607d +#define CYREG_USB_SIE_EP8_CR0 0x4000607e +#define CYDEV_USB_ARB_EP1_BASE 0x40006080 +#define CYDEV_USB_ARB_EP1_SIZE 0x00000003 +#define CYREG_USB_ARB_EP1_CFG 0x40006080 +#define CYREG_USB_ARB_EP1_INT_EN 0x40006081 +#define CYREG_USB_ARB_EP1_SR 0x40006082 +#define CYDEV_USB_ARB_RW1_BASE 0x40006084 +#define CYDEV_USB_ARB_RW1_SIZE 0x00000005 +#define CYREG_USB_ARB_RW1_WA 0x40006084 +#define CYREG_USB_ARB_RW1_WA_MSB 0x40006085 +#define CYREG_USB_ARB_RW1_RA 0x40006086 +#define CYREG_USB_ARB_RW1_RA_MSB 0x40006087 +#define CYREG_USB_ARB_RW1_DR 0x40006088 +#define CYREG_USB_BUF_SIZE 0x4000608c +#define CYREG_USB_EP_ACTIVE 0x4000608e +#define CYREG_USB_EP_TYPE 0x4000608f +#define CYDEV_USB_ARB_EP2_BASE 0x40006090 +#define CYDEV_USB_ARB_EP2_SIZE 0x00000003 +#define CYREG_USB_ARB_EP2_CFG 0x40006090 +#define CYREG_USB_ARB_EP2_INT_EN 0x40006091 +#define CYREG_USB_ARB_EP2_SR 0x40006092 +#define CYDEV_USB_ARB_RW2_BASE 0x40006094 +#define CYDEV_USB_ARB_RW2_SIZE 0x00000005 +#define CYREG_USB_ARB_RW2_WA 0x40006094 +#define CYREG_USB_ARB_RW2_WA_MSB 0x40006095 +#define CYREG_USB_ARB_RW2_RA 0x40006096 +#define CYREG_USB_ARB_RW2_RA_MSB 0x40006097 +#define CYREG_USB_ARB_RW2_DR 0x40006098 +#define CYREG_USB_ARB_CFG 0x4000609c +#define CYREG_USB_USB_CLK_EN 0x4000609d +#define CYREG_USB_ARB_INT_EN 0x4000609e +#define CYREG_USB_ARB_INT_SR 0x4000609f +#define CYDEV_USB_ARB_EP3_BASE 0x400060a0 +#define CYDEV_USB_ARB_EP3_SIZE 0x00000003 +#define CYREG_USB_ARB_EP3_CFG 0x400060a0 +#define CYREG_USB_ARB_EP3_INT_EN 0x400060a1 +#define CYREG_USB_ARB_EP3_SR 0x400060a2 +#define CYDEV_USB_ARB_RW3_BASE 0x400060a4 +#define CYDEV_USB_ARB_RW3_SIZE 0x00000005 +#define CYREG_USB_ARB_RW3_WA 0x400060a4 +#define CYREG_USB_ARB_RW3_WA_MSB 0x400060a5 +#define CYREG_USB_ARB_RW3_RA 0x400060a6 +#define CYREG_USB_ARB_RW3_RA_MSB 0x400060a7 +#define CYREG_USB_ARB_RW3_DR 0x400060a8 +#define CYREG_USB_CWA 0x400060ac +#define CYREG_USB_CWA_MSB 0x400060ad +#define CYDEV_USB_ARB_EP4_BASE 0x400060b0 +#define CYDEV_USB_ARB_EP4_SIZE 0x00000003 +#define CYREG_USB_ARB_EP4_CFG 0x400060b0 +#define CYREG_USB_ARB_EP4_INT_EN 0x400060b1 +#define CYREG_USB_ARB_EP4_SR 0x400060b2 +#define CYDEV_USB_ARB_RW4_BASE 0x400060b4 +#define CYDEV_USB_ARB_RW4_SIZE 0x00000005 +#define CYREG_USB_ARB_RW4_WA 0x400060b4 +#define CYREG_USB_ARB_RW4_WA_MSB 0x400060b5 +#define CYREG_USB_ARB_RW4_RA 0x400060b6 +#define CYREG_USB_ARB_RW4_RA_MSB 0x400060b7 +#define CYREG_USB_ARB_RW4_DR 0x400060b8 +#define CYREG_USB_DMA_THRES 0x400060bc +#define CYREG_USB_DMA_THRES_MSB 0x400060bd +#define CYDEV_USB_ARB_EP5_BASE 0x400060c0 +#define CYDEV_USB_ARB_EP5_SIZE 0x00000003 +#define CYREG_USB_ARB_EP5_CFG 0x400060c0 +#define CYREG_USB_ARB_EP5_INT_EN 0x400060c1 +#define CYREG_USB_ARB_EP5_SR 0x400060c2 +#define CYDEV_USB_ARB_RW5_BASE 0x400060c4 +#define CYDEV_USB_ARB_RW5_SIZE 0x00000005 +#define CYREG_USB_ARB_RW5_WA 0x400060c4 +#define CYREG_USB_ARB_RW5_WA_MSB 0x400060c5 +#define CYREG_USB_ARB_RW5_RA 0x400060c6 +#define CYREG_USB_ARB_RW5_RA_MSB 0x400060c7 +#define CYREG_USB_ARB_RW5_DR 0x400060c8 +#define CYREG_USB_BUS_RST_CNT 0x400060cc +#define CYDEV_USB_ARB_EP6_BASE 0x400060d0 +#define CYDEV_USB_ARB_EP6_SIZE 0x00000003 +#define CYREG_USB_ARB_EP6_CFG 0x400060d0 +#define CYREG_USB_ARB_EP6_INT_EN 0x400060d1 +#define CYREG_USB_ARB_EP6_SR 0x400060d2 +#define CYDEV_USB_ARB_RW6_BASE 0x400060d4 +#define CYDEV_USB_ARB_RW6_SIZE 0x00000005 +#define CYREG_USB_ARB_RW6_WA 0x400060d4 +#define CYREG_USB_ARB_RW6_WA_MSB 0x400060d5 +#define CYREG_USB_ARB_RW6_RA 0x400060d6 +#define CYREG_USB_ARB_RW6_RA_MSB 0x400060d7 +#define CYREG_USB_ARB_RW6_DR 0x400060d8 +#define CYDEV_USB_ARB_EP7_BASE 0x400060e0 +#define CYDEV_USB_ARB_EP7_SIZE 0x00000003 +#define CYREG_USB_ARB_EP7_CFG 0x400060e0 +#define CYREG_USB_ARB_EP7_INT_EN 0x400060e1 +#define CYREG_USB_ARB_EP7_SR 0x400060e2 +#define CYDEV_USB_ARB_RW7_BASE 0x400060e4 +#define CYDEV_USB_ARB_RW7_SIZE 0x00000005 +#define CYREG_USB_ARB_RW7_WA 0x400060e4 +#define CYREG_USB_ARB_RW7_WA_MSB 0x400060e5 +#define CYREG_USB_ARB_RW7_RA 0x400060e6 +#define CYREG_USB_ARB_RW7_RA_MSB 0x400060e7 +#define CYREG_USB_ARB_RW7_DR 0x400060e8 +#define CYDEV_USB_ARB_EP8_BASE 0x400060f0 +#define CYDEV_USB_ARB_EP8_SIZE 0x00000003 +#define CYREG_USB_ARB_EP8_CFG 0x400060f0 +#define CYREG_USB_ARB_EP8_INT_EN 0x400060f1 +#define CYREG_USB_ARB_EP8_SR 0x400060f2 +#define CYDEV_USB_ARB_RW8_BASE 0x400060f4 +#define CYDEV_USB_ARB_RW8_SIZE 0x00000005 +#define CYREG_USB_ARB_RW8_WA 0x400060f4 +#define CYREG_USB_ARB_RW8_WA_MSB 0x400060f5 +#define CYREG_USB_ARB_RW8_RA 0x400060f6 +#define CYREG_USB_ARB_RW8_RA_MSB 0x400060f7 +#define CYREG_USB_ARB_RW8_DR 0x400060f8 +#define CYDEV_USB_MEM_BASE 0x40006100 +#define CYDEV_USB_MEM_SIZE 0x00000200 +#define CYREG_USB_MEM_DATA_MBASE 0x40006100 +#define CYREG_USB_MEM_DATA_MSIZE 0x00000200 +#define CYDEV_UWRK_BASE 0x40006400 +#define CYDEV_UWRK_SIZE 0x00000b60 +#define CYDEV_UWRK_UWRK8_BASE 0x40006400 +#define CYDEV_UWRK_UWRK8_SIZE 0x000003b0 +#define CYDEV_UWRK_UWRK8_B0_BASE 0x40006400 +#define CYDEV_UWRK_UWRK8_B0_SIZE 0x000000b0 +#define CYREG_B0_UDB00_A0 0x40006400 +#define CYREG_B0_UDB01_A0 0x40006401 +#define CYREG_B0_UDB02_A0 0x40006402 +#define CYREG_B0_UDB03_A0 0x40006403 +#define CYREG_B0_UDB04_A0 0x40006404 +#define CYREG_B0_UDB05_A0 0x40006405 +#define CYREG_B0_UDB06_A0 0x40006406 +#define CYREG_B0_UDB07_A0 0x40006407 +#define CYREG_B0_UDB08_A0 0x40006408 +#define CYREG_B0_UDB09_A0 0x40006409 +#define CYREG_B0_UDB10_A0 0x4000640a +#define CYREG_B0_UDB11_A0 0x4000640b +#define CYREG_B0_UDB12_A0 0x4000640c +#define CYREG_B0_UDB13_A0 0x4000640d +#define CYREG_B0_UDB14_A0 0x4000640e +#define CYREG_B0_UDB15_A0 0x4000640f +#define CYREG_B0_UDB00_A1 0x40006410 +#define CYREG_B0_UDB01_A1 0x40006411 +#define CYREG_B0_UDB02_A1 0x40006412 +#define CYREG_B0_UDB03_A1 0x40006413 +#define CYREG_B0_UDB04_A1 0x40006414 +#define CYREG_B0_UDB05_A1 0x40006415 +#define CYREG_B0_UDB06_A1 0x40006416 +#define CYREG_B0_UDB07_A1 0x40006417 +#define CYREG_B0_UDB08_A1 0x40006418 +#define CYREG_B0_UDB09_A1 0x40006419 +#define CYREG_B0_UDB10_A1 0x4000641a +#define CYREG_B0_UDB11_A1 0x4000641b +#define CYREG_B0_UDB12_A1 0x4000641c +#define CYREG_B0_UDB13_A1 0x4000641d +#define CYREG_B0_UDB14_A1 0x4000641e +#define CYREG_B0_UDB15_A1 0x4000641f +#define CYREG_B0_UDB00_D0 0x40006420 +#define CYREG_B0_UDB01_D0 0x40006421 +#define CYREG_B0_UDB02_D0 0x40006422 +#define CYREG_B0_UDB03_D0 0x40006423 +#define CYREG_B0_UDB04_D0 0x40006424 +#define CYREG_B0_UDB05_D0 0x40006425 +#define CYREG_B0_UDB06_D0 0x40006426 +#define CYREG_B0_UDB07_D0 0x40006427 +#define CYREG_B0_UDB08_D0 0x40006428 +#define CYREG_B0_UDB09_D0 0x40006429 +#define CYREG_B0_UDB10_D0 0x4000642a +#define CYREG_B0_UDB11_D0 0x4000642b +#define CYREG_B0_UDB12_D0 0x4000642c +#define CYREG_B0_UDB13_D0 0x4000642d +#define CYREG_B0_UDB14_D0 0x4000642e +#define CYREG_B0_UDB15_D0 0x4000642f +#define CYREG_B0_UDB00_D1 0x40006430 +#define CYREG_B0_UDB01_D1 0x40006431 +#define CYREG_B0_UDB02_D1 0x40006432 +#define CYREG_B0_UDB03_D1 0x40006433 +#define CYREG_B0_UDB04_D1 0x40006434 +#define CYREG_B0_UDB05_D1 0x40006435 +#define CYREG_B0_UDB06_D1 0x40006436 +#define CYREG_B0_UDB07_D1 0x40006437 +#define CYREG_B0_UDB08_D1 0x40006438 +#define CYREG_B0_UDB09_D1 0x40006439 +#define CYREG_B0_UDB10_D1 0x4000643a +#define CYREG_B0_UDB11_D1 0x4000643b +#define CYREG_B0_UDB12_D1 0x4000643c +#define CYREG_B0_UDB13_D1 0x4000643d +#define CYREG_B0_UDB14_D1 0x4000643e +#define CYREG_B0_UDB15_D1 0x4000643f +#define CYREG_B0_UDB00_F0 0x40006440 +#define CYREG_B0_UDB01_F0 0x40006441 +#define CYREG_B0_UDB02_F0 0x40006442 +#define CYREG_B0_UDB03_F0 0x40006443 +#define CYREG_B0_UDB04_F0 0x40006444 +#define CYREG_B0_UDB05_F0 0x40006445 +#define CYREG_B0_UDB06_F0 0x40006446 +#define CYREG_B0_UDB07_F0 0x40006447 +#define CYREG_B0_UDB08_F0 0x40006448 +#define CYREG_B0_UDB09_F0 0x40006449 +#define CYREG_B0_UDB10_F0 0x4000644a +#define CYREG_B0_UDB11_F0 0x4000644b +#define CYREG_B0_UDB12_F0 0x4000644c +#define CYREG_B0_UDB13_F0 0x4000644d +#define CYREG_B0_UDB14_F0 0x4000644e +#define CYREG_B0_UDB15_F0 0x4000644f +#define CYREG_B0_UDB00_F1 0x40006450 +#define CYREG_B0_UDB01_F1 0x40006451 +#define CYREG_B0_UDB02_F1 0x40006452 +#define CYREG_B0_UDB03_F1 0x40006453 +#define CYREG_B0_UDB04_F1 0x40006454 +#define CYREG_B0_UDB05_F1 0x40006455 +#define CYREG_B0_UDB06_F1 0x40006456 +#define CYREG_B0_UDB07_F1 0x40006457 +#define CYREG_B0_UDB08_F1 0x40006458 +#define CYREG_B0_UDB09_F1 0x40006459 +#define CYREG_B0_UDB10_F1 0x4000645a +#define CYREG_B0_UDB11_F1 0x4000645b +#define CYREG_B0_UDB12_F1 0x4000645c +#define CYREG_B0_UDB13_F1 0x4000645d +#define CYREG_B0_UDB14_F1 0x4000645e +#define CYREG_B0_UDB15_F1 0x4000645f +#define CYREG_B0_UDB00_ST 0x40006460 +#define CYREG_B0_UDB01_ST 0x40006461 +#define CYREG_B0_UDB02_ST 0x40006462 +#define CYREG_B0_UDB03_ST 0x40006463 +#define CYREG_B0_UDB04_ST 0x40006464 +#define CYREG_B0_UDB05_ST 0x40006465 +#define CYREG_B0_UDB06_ST 0x40006466 +#define CYREG_B0_UDB07_ST 0x40006467 +#define CYREG_B0_UDB08_ST 0x40006468 +#define CYREG_B0_UDB09_ST 0x40006469 +#define CYREG_B0_UDB10_ST 0x4000646a +#define CYREG_B0_UDB11_ST 0x4000646b +#define CYREG_B0_UDB12_ST 0x4000646c +#define CYREG_B0_UDB13_ST 0x4000646d +#define CYREG_B0_UDB14_ST 0x4000646e +#define CYREG_B0_UDB15_ST 0x4000646f +#define CYREG_B0_UDB00_CTL 0x40006470 +#define CYREG_B0_UDB01_CTL 0x40006471 +#define CYREG_B0_UDB02_CTL 0x40006472 +#define CYREG_B0_UDB03_CTL 0x40006473 +#define CYREG_B0_UDB04_CTL 0x40006474 +#define CYREG_B0_UDB05_CTL 0x40006475 +#define CYREG_B0_UDB06_CTL 0x40006476 +#define CYREG_B0_UDB07_CTL 0x40006477 +#define CYREG_B0_UDB08_CTL 0x40006478 +#define CYREG_B0_UDB09_CTL 0x40006479 +#define CYREG_B0_UDB10_CTL 0x4000647a +#define CYREG_B0_UDB11_CTL 0x4000647b +#define CYREG_B0_UDB12_CTL 0x4000647c +#define CYREG_B0_UDB13_CTL 0x4000647d +#define CYREG_B0_UDB14_CTL 0x4000647e +#define CYREG_B0_UDB15_CTL 0x4000647f +#define CYREG_B0_UDB00_MSK 0x40006480 +#define CYREG_B0_UDB01_MSK 0x40006481 +#define CYREG_B0_UDB02_MSK 0x40006482 +#define CYREG_B0_UDB03_MSK 0x40006483 +#define CYREG_B0_UDB04_MSK 0x40006484 +#define CYREG_B0_UDB05_MSK 0x40006485 +#define CYREG_B0_UDB06_MSK 0x40006486 +#define CYREG_B0_UDB07_MSK 0x40006487 +#define CYREG_B0_UDB08_MSK 0x40006488 +#define CYREG_B0_UDB09_MSK 0x40006489 +#define CYREG_B0_UDB10_MSK 0x4000648a +#define CYREG_B0_UDB11_MSK 0x4000648b +#define CYREG_B0_UDB12_MSK 0x4000648c +#define CYREG_B0_UDB13_MSK 0x4000648d +#define CYREG_B0_UDB14_MSK 0x4000648e +#define CYREG_B0_UDB15_MSK 0x4000648f +#define CYREG_B0_UDB00_ACTL 0x40006490 +#define CYREG_B0_UDB01_ACTL 0x40006491 +#define CYREG_B0_UDB02_ACTL 0x40006492 +#define CYREG_B0_UDB03_ACTL 0x40006493 +#define CYREG_B0_UDB04_ACTL 0x40006494 +#define CYREG_B0_UDB05_ACTL 0x40006495 +#define CYREG_B0_UDB06_ACTL 0x40006496 +#define CYREG_B0_UDB07_ACTL 0x40006497 +#define CYREG_B0_UDB08_ACTL 0x40006498 +#define CYREG_B0_UDB09_ACTL 0x40006499 +#define CYREG_B0_UDB10_ACTL 0x4000649a +#define CYREG_B0_UDB11_ACTL 0x4000649b +#define CYREG_B0_UDB12_ACTL 0x4000649c +#define CYREG_B0_UDB13_ACTL 0x4000649d +#define CYREG_B0_UDB14_ACTL 0x4000649e +#define CYREG_B0_UDB15_ACTL 0x4000649f +#define CYREG_B0_UDB00_MC 0x400064a0 +#define CYREG_B0_UDB01_MC 0x400064a1 +#define CYREG_B0_UDB02_MC 0x400064a2 +#define CYREG_B0_UDB03_MC 0x400064a3 +#define CYREG_B0_UDB04_MC 0x400064a4 +#define CYREG_B0_UDB05_MC 0x400064a5 +#define CYREG_B0_UDB06_MC 0x400064a6 +#define CYREG_B0_UDB07_MC 0x400064a7 +#define CYREG_B0_UDB08_MC 0x400064a8 +#define CYREG_B0_UDB09_MC 0x400064a9 +#define CYREG_B0_UDB10_MC 0x400064aa +#define CYREG_B0_UDB11_MC 0x400064ab +#define CYREG_B0_UDB12_MC 0x400064ac +#define CYREG_B0_UDB13_MC 0x400064ad +#define CYREG_B0_UDB14_MC 0x400064ae +#define CYREG_B0_UDB15_MC 0x400064af +#define CYDEV_UWRK_UWRK8_B1_BASE 0x40006500 +#define CYDEV_UWRK_UWRK8_B1_SIZE 0x000000b0 +#define CYREG_B1_UDB04_A0 0x40006504 +#define CYREG_B1_UDB05_A0 0x40006505 +#define CYREG_B1_UDB06_A0 0x40006506 +#define CYREG_B1_UDB07_A0 0x40006507 +#define CYREG_B1_UDB08_A0 0x40006508 +#define CYREG_B1_UDB09_A0 0x40006509 +#define CYREG_B1_UDB10_A0 0x4000650a +#define CYREG_B1_UDB11_A0 0x4000650b +#define CYREG_B1_UDB04_A1 0x40006514 +#define CYREG_B1_UDB05_A1 0x40006515 +#define CYREG_B1_UDB06_A1 0x40006516 +#define CYREG_B1_UDB07_A1 0x40006517 +#define CYREG_B1_UDB08_A1 0x40006518 +#define CYREG_B1_UDB09_A1 0x40006519 +#define CYREG_B1_UDB10_A1 0x4000651a +#define CYREG_B1_UDB11_A1 0x4000651b +#define CYREG_B1_UDB04_D0 0x40006524 +#define CYREG_B1_UDB05_D0 0x40006525 +#define CYREG_B1_UDB06_D0 0x40006526 +#define CYREG_B1_UDB07_D0 0x40006527 +#define CYREG_B1_UDB08_D0 0x40006528 +#define CYREG_B1_UDB09_D0 0x40006529 +#define CYREG_B1_UDB10_D0 0x4000652a +#define CYREG_B1_UDB11_D0 0x4000652b +#define CYREG_B1_UDB04_D1 0x40006534 +#define CYREG_B1_UDB05_D1 0x40006535 +#define CYREG_B1_UDB06_D1 0x40006536 +#define CYREG_B1_UDB07_D1 0x40006537 +#define CYREG_B1_UDB08_D1 0x40006538 +#define CYREG_B1_UDB09_D1 0x40006539 +#define CYREG_B1_UDB10_D1 0x4000653a +#define CYREG_B1_UDB11_D1 0x4000653b +#define CYREG_B1_UDB04_F0 0x40006544 +#define CYREG_B1_UDB05_F0 0x40006545 +#define CYREG_B1_UDB06_F0 0x40006546 +#define CYREG_B1_UDB07_F0 0x40006547 +#define CYREG_B1_UDB08_F0 0x40006548 +#define CYREG_B1_UDB09_F0 0x40006549 +#define CYREG_B1_UDB10_F0 0x4000654a +#define CYREG_B1_UDB11_F0 0x4000654b +#define CYREG_B1_UDB04_F1 0x40006554 +#define CYREG_B1_UDB05_F1 0x40006555 +#define CYREG_B1_UDB06_F1 0x40006556 +#define CYREG_B1_UDB07_F1 0x40006557 +#define CYREG_B1_UDB08_F1 0x40006558 +#define CYREG_B1_UDB09_F1 0x40006559 +#define CYREG_B1_UDB10_F1 0x4000655a +#define CYREG_B1_UDB11_F1 0x4000655b +#define CYREG_B1_UDB04_ST 0x40006564 +#define CYREG_B1_UDB05_ST 0x40006565 +#define CYREG_B1_UDB06_ST 0x40006566 +#define CYREG_B1_UDB07_ST 0x40006567 +#define CYREG_B1_UDB08_ST 0x40006568 +#define CYREG_B1_UDB09_ST 0x40006569 +#define CYREG_B1_UDB10_ST 0x4000656a +#define CYREG_B1_UDB11_ST 0x4000656b +#define CYREG_B1_UDB04_CTL 0x40006574 +#define CYREG_B1_UDB05_CTL 0x40006575 +#define CYREG_B1_UDB06_CTL 0x40006576 +#define CYREG_B1_UDB07_CTL 0x40006577 +#define CYREG_B1_UDB08_CTL 0x40006578 +#define CYREG_B1_UDB09_CTL 0x40006579 +#define CYREG_B1_UDB10_CTL 0x4000657a +#define CYREG_B1_UDB11_CTL 0x4000657b +#define CYREG_B1_UDB04_MSK 0x40006584 +#define CYREG_B1_UDB05_MSK 0x40006585 +#define CYREG_B1_UDB06_MSK 0x40006586 +#define CYREG_B1_UDB07_MSK 0x40006587 +#define CYREG_B1_UDB08_MSK 0x40006588 +#define CYREG_B1_UDB09_MSK 0x40006589 +#define CYREG_B1_UDB10_MSK 0x4000658a +#define CYREG_B1_UDB11_MSK 0x4000658b +#define CYREG_B1_UDB04_ACTL 0x40006594 +#define CYREG_B1_UDB05_ACTL 0x40006595 +#define CYREG_B1_UDB06_ACTL 0x40006596 +#define CYREG_B1_UDB07_ACTL 0x40006597 +#define CYREG_B1_UDB08_ACTL 0x40006598 +#define CYREG_B1_UDB09_ACTL 0x40006599 +#define CYREG_B1_UDB10_ACTL 0x4000659a +#define CYREG_B1_UDB11_ACTL 0x4000659b +#define CYREG_B1_UDB04_MC 0x400065a4 +#define CYREG_B1_UDB05_MC 0x400065a5 +#define CYREG_B1_UDB06_MC 0x400065a6 +#define CYREG_B1_UDB07_MC 0x400065a7 +#define CYREG_B1_UDB08_MC 0x400065a8 +#define CYREG_B1_UDB09_MC 0x400065a9 +#define CYREG_B1_UDB10_MC 0x400065aa +#define CYREG_B1_UDB11_MC 0x400065ab +#define CYDEV_UWRK_UWRK16_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_SIZE 0x00000760 +#define CYDEV_UWRK_UWRK16_CAT_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_CAT_SIZE 0x00000760 +#define CYDEV_UWRK_UWRK16_CAT_B0_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_CAT_B0_SIZE 0x00000160 +#define CYREG_B0_UDB00_A0_A1 0x40006800 +#define CYREG_B0_UDB01_A0_A1 0x40006802 +#define CYREG_B0_UDB02_A0_A1 0x40006804 +#define CYREG_B0_UDB03_A0_A1 0x40006806 +#define CYREG_B0_UDB04_A0_A1 0x40006808 +#define CYREG_B0_UDB05_A0_A1 0x4000680a +#define CYREG_B0_UDB06_A0_A1 0x4000680c +#define CYREG_B0_UDB07_A0_A1 0x4000680e +#define CYREG_B0_UDB08_A0_A1 0x40006810 +#define CYREG_B0_UDB09_A0_A1 0x40006812 +#define CYREG_B0_UDB10_A0_A1 0x40006814 +#define CYREG_B0_UDB11_A0_A1 0x40006816 +#define CYREG_B0_UDB12_A0_A1 0x40006818 +#define CYREG_B0_UDB13_A0_A1 0x4000681a +#define CYREG_B0_UDB14_A0_A1 0x4000681c +#define CYREG_B0_UDB15_A0_A1 0x4000681e +#define CYREG_B0_UDB00_D0_D1 0x40006840 +#define CYREG_B0_UDB01_D0_D1 0x40006842 +#define CYREG_B0_UDB02_D0_D1 0x40006844 +#define CYREG_B0_UDB03_D0_D1 0x40006846 +#define CYREG_B0_UDB04_D0_D1 0x40006848 +#define CYREG_B0_UDB05_D0_D1 0x4000684a +#define CYREG_B0_UDB06_D0_D1 0x4000684c +#define CYREG_B0_UDB07_D0_D1 0x4000684e +#define CYREG_B0_UDB08_D0_D1 0x40006850 +#define CYREG_B0_UDB09_D0_D1 0x40006852 +#define CYREG_B0_UDB10_D0_D1 0x40006854 +#define CYREG_B0_UDB11_D0_D1 0x40006856 +#define CYREG_B0_UDB12_D0_D1 0x40006858 +#define CYREG_B0_UDB13_D0_D1 0x4000685a +#define CYREG_B0_UDB14_D0_D1 0x4000685c +#define CYREG_B0_UDB15_D0_D1 0x4000685e +#define CYREG_B0_UDB00_F0_F1 0x40006880 +#define CYREG_B0_UDB01_F0_F1 0x40006882 +#define CYREG_B0_UDB02_F0_F1 0x40006884 +#define CYREG_B0_UDB03_F0_F1 0x40006886 +#define CYREG_B0_UDB04_F0_F1 0x40006888 +#define CYREG_B0_UDB05_F0_F1 0x4000688a +#define CYREG_B0_UDB06_F0_F1 0x4000688c +#define CYREG_B0_UDB07_F0_F1 0x4000688e +#define CYREG_B0_UDB08_F0_F1 0x40006890 +#define CYREG_B0_UDB09_F0_F1 0x40006892 +#define CYREG_B0_UDB10_F0_F1 0x40006894 +#define CYREG_B0_UDB11_F0_F1 0x40006896 +#define CYREG_B0_UDB12_F0_F1 0x40006898 +#define CYREG_B0_UDB13_F0_F1 0x4000689a +#define CYREG_B0_UDB14_F0_F1 0x4000689c +#define CYREG_B0_UDB15_F0_F1 0x4000689e +#define CYREG_B0_UDB00_ST_CTL 0x400068c0 +#define CYREG_B0_UDB01_ST_CTL 0x400068c2 +#define CYREG_B0_UDB02_ST_CTL 0x400068c4 +#define CYREG_B0_UDB03_ST_CTL 0x400068c6 +#define CYREG_B0_UDB04_ST_CTL 0x400068c8 +#define CYREG_B0_UDB05_ST_CTL 0x400068ca +#define CYREG_B0_UDB06_ST_CTL 0x400068cc +#define CYREG_B0_UDB07_ST_CTL 0x400068ce +#define CYREG_B0_UDB08_ST_CTL 0x400068d0 +#define CYREG_B0_UDB09_ST_CTL 0x400068d2 +#define CYREG_B0_UDB10_ST_CTL 0x400068d4 +#define CYREG_B0_UDB11_ST_CTL 0x400068d6 +#define CYREG_B0_UDB12_ST_CTL 0x400068d8 +#define CYREG_B0_UDB13_ST_CTL 0x400068da +#define CYREG_B0_UDB14_ST_CTL 0x400068dc +#define CYREG_B0_UDB15_ST_CTL 0x400068de +#define CYREG_B0_UDB00_MSK_ACTL 0x40006900 +#define CYREG_B0_UDB01_MSK_ACTL 0x40006902 +#define CYREG_B0_UDB02_MSK_ACTL 0x40006904 +#define CYREG_B0_UDB03_MSK_ACTL 0x40006906 +#define CYREG_B0_UDB04_MSK_ACTL 0x40006908 +#define CYREG_B0_UDB05_MSK_ACTL 0x4000690a +#define CYREG_B0_UDB06_MSK_ACTL 0x4000690c +#define CYREG_B0_UDB07_MSK_ACTL 0x4000690e +#define CYREG_B0_UDB08_MSK_ACTL 0x40006910 +#define CYREG_B0_UDB09_MSK_ACTL 0x40006912 +#define CYREG_B0_UDB10_MSK_ACTL 0x40006914 +#define CYREG_B0_UDB11_MSK_ACTL 0x40006916 +#define CYREG_B0_UDB12_MSK_ACTL 0x40006918 +#define CYREG_B0_UDB13_MSK_ACTL 0x4000691a +#define CYREG_B0_UDB14_MSK_ACTL 0x4000691c +#define CYREG_B0_UDB15_MSK_ACTL 0x4000691e +#define CYREG_B0_UDB00_MC_00 0x40006940 +#define CYREG_B0_UDB01_MC_00 0x40006942 +#define CYREG_B0_UDB02_MC_00 0x40006944 +#define CYREG_B0_UDB03_MC_00 0x40006946 +#define CYREG_B0_UDB04_MC_00 0x40006948 +#define CYREG_B0_UDB05_MC_00 0x4000694a +#define CYREG_B0_UDB06_MC_00 0x4000694c +#define CYREG_B0_UDB07_MC_00 0x4000694e +#define CYREG_B0_UDB08_MC_00 0x40006950 +#define CYREG_B0_UDB09_MC_00 0x40006952 +#define CYREG_B0_UDB10_MC_00 0x40006954 +#define CYREG_B0_UDB11_MC_00 0x40006956 +#define CYREG_B0_UDB12_MC_00 0x40006958 +#define CYREG_B0_UDB13_MC_00 0x4000695a +#define CYREG_B0_UDB14_MC_00 0x4000695c +#define CYREG_B0_UDB15_MC_00 0x4000695e +#define CYDEV_UWRK_UWRK16_CAT_B1_BASE 0x40006a00 +#define CYDEV_UWRK_UWRK16_CAT_B1_SIZE 0x00000160 +#define CYREG_B1_UDB04_A0_A1 0x40006a08 +#define CYREG_B1_UDB05_A0_A1 0x40006a0a +#define CYREG_B1_UDB06_A0_A1 0x40006a0c +#define CYREG_B1_UDB07_A0_A1 0x40006a0e +#define CYREG_B1_UDB08_A0_A1 0x40006a10 +#define CYREG_B1_UDB09_A0_A1 0x40006a12 +#define CYREG_B1_UDB10_A0_A1 0x40006a14 +#define CYREG_B1_UDB11_A0_A1 0x40006a16 +#define CYREG_B1_UDB04_D0_D1 0x40006a48 +#define CYREG_B1_UDB05_D0_D1 0x40006a4a +#define CYREG_B1_UDB06_D0_D1 0x40006a4c +#define CYREG_B1_UDB07_D0_D1 0x40006a4e +#define CYREG_B1_UDB08_D0_D1 0x40006a50 +#define CYREG_B1_UDB09_D0_D1 0x40006a52 +#define CYREG_B1_UDB10_D0_D1 0x40006a54 +#define CYREG_B1_UDB11_D0_D1 0x40006a56 +#define CYREG_B1_UDB04_F0_F1 0x40006a88 +#define CYREG_B1_UDB05_F0_F1 0x40006a8a +#define CYREG_B1_UDB06_F0_F1 0x40006a8c +#define CYREG_B1_UDB07_F0_F1 0x40006a8e +#define CYREG_B1_UDB08_F0_F1 0x40006a90 +#define CYREG_B1_UDB09_F0_F1 0x40006a92 +#define CYREG_B1_UDB10_F0_F1 0x40006a94 +#define CYREG_B1_UDB11_F0_F1 0x40006a96 +#define CYREG_B1_UDB04_ST_CTL 0x40006ac8 +#define CYREG_B1_UDB05_ST_CTL 0x40006aca +#define CYREG_B1_UDB06_ST_CTL 0x40006acc +#define CYREG_B1_UDB07_ST_CTL 0x40006ace +#define CYREG_B1_UDB08_ST_CTL 0x40006ad0 +#define CYREG_B1_UDB09_ST_CTL 0x40006ad2 +#define CYREG_B1_UDB10_ST_CTL 0x40006ad4 +#define CYREG_B1_UDB11_ST_CTL 0x40006ad6 +#define CYREG_B1_UDB04_MSK_ACTL 0x40006b08 +#define CYREG_B1_UDB05_MSK_ACTL 0x40006b0a +#define CYREG_B1_UDB06_MSK_ACTL 0x40006b0c +#define CYREG_B1_UDB07_MSK_ACTL 0x40006b0e +#define CYREG_B1_UDB08_MSK_ACTL 0x40006b10 +#define CYREG_B1_UDB09_MSK_ACTL 0x40006b12 +#define CYREG_B1_UDB10_MSK_ACTL 0x40006b14 +#define CYREG_B1_UDB11_MSK_ACTL 0x40006b16 +#define CYREG_B1_UDB04_MC_00 0x40006b48 +#define CYREG_B1_UDB05_MC_00 0x40006b4a +#define CYREG_B1_UDB06_MC_00 0x40006b4c +#define CYREG_B1_UDB07_MC_00 0x40006b4e +#define CYREG_B1_UDB08_MC_00 0x40006b50 +#define CYREG_B1_UDB09_MC_00 0x40006b52 +#define CYREG_B1_UDB10_MC_00 0x40006b54 +#define CYREG_B1_UDB11_MC_00 0x40006b56 +#define CYDEV_UWRK_UWRK16_DEF_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_DEF_SIZE 0x0000075e +#define CYDEV_UWRK_UWRK16_DEF_B0_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_DEF_B0_SIZE 0x0000015e +#define CYREG_B0_UDB00_01_A0 0x40006800 +#define CYREG_B0_UDB01_02_A0 0x40006802 +#define CYREG_B0_UDB02_03_A0 0x40006804 +#define CYREG_B0_UDB03_04_A0 0x40006806 +#define CYREG_B0_UDB04_05_A0 0x40006808 +#define CYREG_B0_UDB05_06_A0 0x4000680a +#define CYREG_B0_UDB06_07_A0 0x4000680c +#define CYREG_B0_UDB07_08_A0 0x4000680e +#define CYREG_B0_UDB08_09_A0 0x40006810 +#define CYREG_B0_UDB09_10_A0 0x40006812 +#define CYREG_B0_UDB10_11_A0 0x40006814 +#define CYREG_B0_UDB11_12_A0 0x40006816 +#define CYREG_B0_UDB12_13_A0 0x40006818 +#define CYREG_B0_UDB13_14_A0 0x4000681a +#define CYREG_B0_UDB14_15_A0 0x4000681c +#define CYREG_B0_UDB00_01_A1 0x40006820 +#define CYREG_B0_UDB01_02_A1 0x40006822 +#define CYREG_B0_UDB02_03_A1 0x40006824 +#define CYREG_B0_UDB03_04_A1 0x40006826 +#define CYREG_B0_UDB04_05_A1 0x40006828 +#define CYREG_B0_UDB05_06_A1 0x4000682a +#define CYREG_B0_UDB06_07_A1 0x4000682c +#define CYREG_B0_UDB07_08_A1 0x4000682e +#define CYREG_B0_UDB08_09_A1 0x40006830 +#define CYREG_B0_UDB09_10_A1 0x40006832 +#define CYREG_B0_UDB10_11_A1 0x40006834 +#define CYREG_B0_UDB11_12_A1 0x40006836 +#define CYREG_B0_UDB12_13_A1 0x40006838 +#define CYREG_B0_UDB13_14_A1 0x4000683a +#define CYREG_B0_UDB14_15_A1 0x4000683c +#define CYREG_B0_UDB00_01_D0 0x40006840 +#define CYREG_B0_UDB01_02_D0 0x40006842 +#define CYREG_B0_UDB02_03_D0 0x40006844 +#define CYREG_B0_UDB03_04_D0 0x40006846 +#define CYREG_B0_UDB04_05_D0 0x40006848 +#define CYREG_B0_UDB05_06_D0 0x4000684a +#define CYREG_B0_UDB06_07_D0 0x4000684c +#define CYREG_B0_UDB07_08_D0 0x4000684e +#define CYREG_B0_UDB08_09_D0 0x40006850 +#define CYREG_B0_UDB09_10_D0 0x40006852 +#define CYREG_B0_UDB10_11_D0 0x40006854 +#define CYREG_B0_UDB11_12_D0 0x40006856 +#define CYREG_B0_UDB12_13_D0 0x40006858 +#define CYREG_B0_UDB13_14_D0 0x4000685a +#define CYREG_B0_UDB14_15_D0 0x4000685c +#define CYREG_B0_UDB00_01_D1 0x40006860 +#define CYREG_B0_UDB01_02_D1 0x40006862 +#define CYREG_B0_UDB02_03_D1 0x40006864 +#define CYREG_B0_UDB03_04_D1 0x40006866 +#define CYREG_B0_UDB04_05_D1 0x40006868 +#define CYREG_B0_UDB05_06_D1 0x4000686a +#define CYREG_B0_UDB06_07_D1 0x4000686c +#define CYREG_B0_UDB07_08_D1 0x4000686e +#define CYREG_B0_UDB08_09_D1 0x40006870 +#define CYREG_B0_UDB09_10_D1 0x40006872 +#define CYREG_B0_UDB10_11_D1 0x40006874 +#define CYREG_B0_UDB11_12_D1 0x40006876 +#define CYREG_B0_UDB12_13_D1 0x40006878 +#define CYREG_B0_UDB13_14_D1 0x4000687a +#define CYREG_B0_UDB14_15_D1 0x4000687c +#define CYREG_B0_UDB00_01_F0 0x40006880 +#define CYREG_B0_UDB01_02_F0 0x40006882 +#define CYREG_B0_UDB02_03_F0 0x40006884 +#define CYREG_B0_UDB03_04_F0 0x40006886 +#define CYREG_B0_UDB04_05_F0 0x40006888 +#define CYREG_B0_UDB05_06_F0 0x4000688a +#define CYREG_B0_UDB06_07_F0 0x4000688c +#define CYREG_B0_UDB07_08_F0 0x4000688e +#define CYREG_B0_UDB08_09_F0 0x40006890 +#define CYREG_B0_UDB09_10_F0 0x40006892 +#define CYREG_B0_UDB10_11_F0 0x40006894 +#define CYREG_B0_UDB11_12_F0 0x40006896 +#define CYREG_B0_UDB12_13_F0 0x40006898 +#define CYREG_B0_UDB13_14_F0 0x4000689a +#define CYREG_B0_UDB14_15_F0 0x4000689c +#define CYREG_B0_UDB00_01_F1 0x400068a0 +#define CYREG_B0_UDB01_02_F1 0x400068a2 +#define CYREG_B0_UDB02_03_F1 0x400068a4 +#define CYREG_B0_UDB03_04_F1 0x400068a6 +#define CYREG_B0_UDB04_05_F1 0x400068a8 +#define CYREG_B0_UDB05_06_F1 0x400068aa +#define CYREG_B0_UDB06_07_F1 0x400068ac +#define CYREG_B0_UDB07_08_F1 0x400068ae +#define CYREG_B0_UDB08_09_F1 0x400068b0 +#define CYREG_B0_UDB09_10_F1 0x400068b2 +#define CYREG_B0_UDB10_11_F1 0x400068b4 +#define CYREG_B0_UDB11_12_F1 0x400068b6 +#define CYREG_B0_UDB12_13_F1 0x400068b8 +#define CYREG_B0_UDB13_14_F1 0x400068ba +#define CYREG_B0_UDB14_15_F1 0x400068bc +#define CYREG_B0_UDB00_01_ST 0x400068c0 +#define CYREG_B0_UDB01_02_ST 0x400068c2 +#define CYREG_B0_UDB02_03_ST 0x400068c4 +#define CYREG_B0_UDB03_04_ST 0x400068c6 +#define CYREG_B0_UDB04_05_ST 0x400068c8 +#define CYREG_B0_UDB05_06_ST 0x400068ca +#define CYREG_B0_UDB06_07_ST 0x400068cc +#define CYREG_B0_UDB07_08_ST 0x400068ce +#define CYREG_B0_UDB08_09_ST 0x400068d0 +#define CYREG_B0_UDB09_10_ST 0x400068d2 +#define CYREG_B0_UDB10_11_ST 0x400068d4 +#define CYREG_B0_UDB11_12_ST 0x400068d6 +#define CYREG_B0_UDB12_13_ST 0x400068d8 +#define CYREG_B0_UDB13_14_ST 0x400068da +#define CYREG_B0_UDB14_15_ST 0x400068dc +#define CYREG_B0_UDB00_01_CTL 0x400068e0 +#define CYREG_B0_UDB01_02_CTL 0x400068e2 +#define CYREG_B0_UDB02_03_CTL 0x400068e4 +#define CYREG_B0_UDB03_04_CTL 0x400068e6 +#define CYREG_B0_UDB04_05_CTL 0x400068e8 +#define CYREG_B0_UDB05_06_CTL 0x400068ea +#define CYREG_B0_UDB06_07_CTL 0x400068ec +#define CYREG_B0_UDB07_08_CTL 0x400068ee +#define CYREG_B0_UDB08_09_CTL 0x400068f0 +#define CYREG_B0_UDB09_10_CTL 0x400068f2 +#define CYREG_B0_UDB10_11_CTL 0x400068f4 +#define CYREG_B0_UDB11_12_CTL 0x400068f6 +#define CYREG_B0_UDB12_13_CTL 0x400068f8 +#define CYREG_B0_UDB13_14_CTL 0x400068fa +#define CYREG_B0_UDB14_15_CTL 0x400068fc +#define CYREG_B0_UDB00_01_MSK 0x40006900 +#define CYREG_B0_UDB01_02_MSK 0x40006902 +#define CYREG_B0_UDB02_03_MSK 0x40006904 +#define CYREG_B0_UDB03_04_MSK 0x40006906 +#define CYREG_B0_UDB04_05_MSK 0x40006908 +#define CYREG_B0_UDB05_06_MSK 0x4000690a +#define CYREG_B0_UDB06_07_MSK 0x4000690c +#define CYREG_B0_UDB07_08_MSK 0x4000690e +#define CYREG_B0_UDB08_09_MSK 0x40006910 +#define CYREG_B0_UDB09_10_MSK 0x40006912 +#define CYREG_B0_UDB10_11_MSK 0x40006914 +#define CYREG_B0_UDB11_12_MSK 0x40006916 +#define CYREG_B0_UDB12_13_MSK 0x40006918 +#define CYREG_B0_UDB13_14_MSK 0x4000691a +#define CYREG_B0_UDB14_15_MSK 0x4000691c +#define CYREG_B0_UDB00_01_ACTL 0x40006920 +#define CYREG_B0_UDB01_02_ACTL 0x40006922 +#define CYREG_B0_UDB02_03_ACTL 0x40006924 +#define CYREG_B0_UDB03_04_ACTL 0x40006926 +#define CYREG_B0_UDB04_05_ACTL 0x40006928 +#define CYREG_B0_UDB05_06_ACTL 0x4000692a +#define CYREG_B0_UDB06_07_ACTL 0x4000692c +#define CYREG_B0_UDB07_08_ACTL 0x4000692e +#define CYREG_B0_UDB08_09_ACTL 0x40006930 +#define CYREG_B0_UDB09_10_ACTL 0x40006932 +#define CYREG_B0_UDB10_11_ACTL 0x40006934 +#define CYREG_B0_UDB11_12_ACTL 0x40006936 +#define CYREG_B0_UDB12_13_ACTL 0x40006938 +#define CYREG_B0_UDB13_14_ACTL 0x4000693a +#define CYREG_B0_UDB14_15_ACTL 0x4000693c +#define CYREG_B0_UDB00_01_MC 0x40006940 +#define CYREG_B0_UDB01_02_MC 0x40006942 +#define CYREG_B0_UDB02_03_MC 0x40006944 +#define CYREG_B0_UDB03_04_MC 0x40006946 +#define CYREG_B0_UDB04_05_MC 0x40006948 +#define CYREG_B0_UDB05_06_MC 0x4000694a +#define CYREG_B0_UDB06_07_MC 0x4000694c +#define CYREG_B0_UDB07_08_MC 0x4000694e +#define CYREG_B0_UDB08_09_MC 0x40006950 +#define CYREG_B0_UDB09_10_MC 0x40006952 +#define CYREG_B0_UDB10_11_MC 0x40006954 +#define CYREG_B0_UDB11_12_MC 0x40006956 +#define CYREG_B0_UDB12_13_MC 0x40006958 +#define CYREG_B0_UDB13_14_MC 0x4000695a +#define CYREG_B0_UDB14_15_MC 0x4000695c +#define CYDEV_UWRK_UWRK16_DEF_B1_BASE 0x40006a00 +#define CYDEV_UWRK_UWRK16_DEF_B1_SIZE 0x0000015e +#define CYREG_B1_UDB04_05_A0 0x40006a08 +#define CYREG_B1_UDB05_06_A0 0x40006a0a +#define CYREG_B1_UDB06_07_A0 0x40006a0c +#define CYREG_B1_UDB07_08_A0 0x40006a0e +#define CYREG_B1_UDB08_09_A0 0x40006a10 +#define CYREG_B1_UDB09_10_A0 0x40006a12 +#define CYREG_B1_UDB10_11_A0 0x40006a14 +#define CYREG_B1_UDB11_12_A0 0x40006a16 +#define CYREG_B1_UDB04_05_A1 0x40006a28 +#define CYREG_B1_UDB05_06_A1 0x40006a2a +#define CYREG_B1_UDB06_07_A1 0x40006a2c +#define CYREG_B1_UDB07_08_A1 0x40006a2e +#define CYREG_B1_UDB08_09_A1 0x40006a30 +#define CYREG_B1_UDB09_10_A1 0x40006a32 +#define CYREG_B1_UDB10_11_A1 0x40006a34 +#define CYREG_B1_UDB11_12_A1 0x40006a36 +#define CYREG_B1_UDB04_05_D0 0x40006a48 +#define CYREG_B1_UDB05_06_D0 0x40006a4a +#define CYREG_B1_UDB06_07_D0 0x40006a4c +#define CYREG_B1_UDB07_08_D0 0x40006a4e +#define CYREG_B1_UDB08_09_D0 0x40006a50 +#define CYREG_B1_UDB09_10_D0 0x40006a52 +#define CYREG_B1_UDB10_11_D0 0x40006a54 +#define CYREG_B1_UDB11_12_D0 0x40006a56 +#define CYREG_B1_UDB04_05_D1 0x40006a68 +#define CYREG_B1_UDB05_06_D1 0x40006a6a +#define CYREG_B1_UDB06_07_D1 0x40006a6c +#define CYREG_B1_UDB07_08_D1 0x40006a6e +#define CYREG_B1_UDB08_09_D1 0x40006a70 +#define CYREG_B1_UDB09_10_D1 0x40006a72 +#define CYREG_B1_UDB10_11_D1 0x40006a74 +#define CYREG_B1_UDB11_12_D1 0x40006a76 +#define CYREG_B1_UDB04_05_F0 0x40006a88 +#define CYREG_B1_UDB05_06_F0 0x40006a8a +#define CYREG_B1_UDB06_07_F0 0x40006a8c +#define CYREG_B1_UDB07_08_F0 0x40006a8e +#define CYREG_B1_UDB08_09_F0 0x40006a90 +#define CYREG_B1_UDB09_10_F0 0x40006a92 +#define CYREG_B1_UDB10_11_F0 0x40006a94 +#define CYREG_B1_UDB11_12_F0 0x40006a96 +#define CYREG_B1_UDB04_05_F1 0x40006aa8 +#define CYREG_B1_UDB05_06_F1 0x40006aaa +#define CYREG_B1_UDB06_07_F1 0x40006aac +#define CYREG_B1_UDB07_08_F1 0x40006aae +#define CYREG_B1_UDB08_09_F1 0x40006ab0 +#define CYREG_B1_UDB09_10_F1 0x40006ab2 +#define CYREG_B1_UDB10_11_F1 0x40006ab4 +#define CYREG_B1_UDB11_12_F1 0x40006ab6 +#define CYREG_B1_UDB04_05_ST 0x40006ac8 +#define CYREG_B1_UDB05_06_ST 0x40006aca +#define CYREG_B1_UDB06_07_ST 0x40006acc +#define CYREG_B1_UDB07_08_ST 0x40006ace +#define CYREG_B1_UDB08_09_ST 0x40006ad0 +#define CYREG_B1_UDB09_10_ST 0x40006ad2 +#define CYREG_B1_UDB10_11_ST 0x40006ad4 +#define CYREG_B1_UDB11_12_ST 0x40006ad6 +#define CYREG_B1_UDB04_05_CTL 0x40006ae8 +#define CYREG_B1_UDB05_06_CTL 0x40006aea +#define CYREG_B1_UDB06_07_CTL 0x40006aec +#define CYREG_B1_UDB07_08_CTL 0x40006aee +#define CYREG_B1_UDB08_09_CTL 0x40006af0 +#define CYREG_B1_UDB09_10_CTL 0x40006af2 +#define CYREG_B1_UDB10_11_CTL 0x40006af4 +#define CYREG_B1_UDB11_12_CTL 0x40006af6 +#define CYREG_B1_UDB04_05_MSK 0x40006b08 +#define CYREG_B1_UDB05_06_MSK 0x40006b0a +#define CYREG_B1_UDB06_07_MSK 0x40006b0c +#define CYREG_B1_UDB07_08_MSK 0x40006b0e +#define CYREG_B1_UDB08_09_MSK 0x40006b10 +#define CYREG_B1_UDB09_10_MSK 0x40006b12 +#define CYREG_B1_UDB10_11_MSK 0x40006b14 +#define CYREG_B1_UDB11_12_MSK 0x40006b16 +#define CYREG_B1_UDB04_05_ACTL 0x40006b28 +#define CYREG_B1_UDB05_06_ACTL 0x40006b2a +#define CYREG_B1_UDB06_07_ACTL 0x40006b2c +#define CYREG_B1_UDB07_08_ACTL 0x40006b2e +#define CYREG_B1_UDB08_09_ACTL 0x40006b30 +#define CYREG_B1_UDB09_10_ACTL 0x40006b32 +#define CYREG_B1_UDB10_11_ACTL 0x40006b34 +#define CYREG_B1_UDB11_12_ACTL 0x40006b36 +#define CYREG_B1_UDB04_05_MC 0x40006b48 +#define CYREG_B1_UDB05_06_MC 0x40006b4a +#define CYREG_B1_UDB06_07_MC 0x40006b4c +#define CYREG_B1_UDB07_08_MC 0x40006b4e +#define CYREG_B1_UDB08_09_MC 0x40006b50 +#define CYREG_B1_UDB09_10_MC 0x40006b52 +#define CYREG_B1_UDB10_11_MC 0x40006b54 +#define CYREG_B1_UDB11_12_MC 0x40006b56 +#define CYDEV_PHUB_BASE 0x40007000 +#define CYDEV_PHUB_SIZE 0x00000c00 +#define CYREG_PHUB_CFG 0x40007000 +#define CYREG_PHUB_ERR 0x40007004 +#define CYREG_PHUB_ERR_ADR 0x40007008 +#define CYDEV_PHUB_CH0_BASE 0x40007010 +#define CYDEV_PHUB_CH0_SIZE 0x0000000c +#define CYREG_PHUB_CH0_BASIC_CFG 0x40007010 +#define CYREG_PHUB_CH0_ACTION 0x40007014 +#define CYREG_PHUB_CH0_BASIC_STATUS 0x40007018 +#define CYDEV_PHUB_CH1_BASE 0x40007020 +#define CYDEV_PHUB_CH1_SIZE 0x0000000c +#define CYREG_PHUB_CH1_BASIC_CFG 0x40007020 +#define CYREG_PHUB_CH1_ACTION 0x40007024 +#define CYREG_PHUB_CH1_BASIC_STATUS 0x40007028 +#define CYDEV_PHUB_CH2_BASE 0x40007030 +#define CYDEV_PHUB_CH2_SIZE 0x0000000c +#define CYREG_PHUB_CH2_BASIC_CFG 0x40007030 +#define CYREG_PHUB_CH2_ACTION 0x40007034 +#define CYREG_PHUB_CH2_BASIC_STATUS 0x40007038 +#define CYDEV_PHUB_CH3_BASE 0x40007040 +#define CYDEV_PHUB_CH3_SIZE 0x0000000c +#define CYREG_PHUB_CH3_BASIC_CFG 0x40007040 +#define CYREG_PHUB_CH3_ACTION 0x40007044 +#define CYREG_PHUB_CH3_BASIC_STATUS 0x40007048 +#define CYDEV_PHUB_CH4_BASE 0x40007050 +#define CYDEV_PHUB_CH4_SIZE 0x0000000c +#define CYREG_PHUB_CH4_BASIC_CFG 0x40007050 +#define CYREG_PHUB_CH4_ACTION 0x40007054 +#define CYREG_PHUB_CH4_BASIC_STATUS 0x40007058 +#define CYDEV_PHUB_CH5_BASE 0x40007060 +#define CYDEV_PHUB_CH5_SIZE 0x0000000c +#define CYREG_PHUB_CH5_BASIC_CFG 0x40007060 +#define CYREG_PHUB_CH5_ACTION 0x40007064 +#define CYREG_PHUB_CH5_BASIC_STATUS 0x40007068 +#define CYDEV_PHUB_CH6_BASE 0x40007070 +#define CYDEV_PHUB_CH6_SIZE 0x0000000c +#define CYREG_PHUB_CH6_BASIC_CFG 0x40007070 +#define CYREG_PHUB_CH6_ACTION 0x40007074 +#define CYREG_PHUB_CH6_BASIC_STATUS 0x40007078 +#define CYDEV_PHUB_CH7_BASE 0x40007080 +#define CYDEV_PHUB_CH7_SIZE 0x0000000c +#define CYREG_PHUB_CH7_BASIC_CFG 0x40007080 +#define CYREG_PHUB_CH7_ACTION 0x40007084 +#define CYREG_PHUB_CH7_BASIC_STATUS 0x40007088 +#define CYDEV_PHUB_CH8_BASE 0x40007090 +#define CYDEV_PHUB_CH8_SIZE 0x0000000c +#define CYREG_PHUB_CH8_BASIC_CFG 0x40007090 +#define CYREG_PHUB_CH8_ACTION 0x40007094 +#define CYREG_PHUB_CH8_BASIC_STATUS 0x40007098 +#define CYDEV_PHUB_CH9_BASE 0x400070a0 +#define CYDEV_PHUB_CH9_SIZE 0x0000000c +#define CYREG_PHUB_CH9_BASIC_CFG 0x400070a0 +#define CYREG_PHUB_CH9_ACTION 0x400070a4 +#define CYREG_PHUB_CH9_BASIC_STATUS 0x400070a8 +#define CYDEV_PHUB_CH10_BASE 0x400070b0 +#define CYDEV_PHUB_CH10_SIZE 0x0000000c +#define CYREG_PHUB_CH10_BASIC_CFG 0x400070b0 +#define CYREG_PHUB_CH10_ACTION 0x400070b4 +#define CYREG_PHUB_CH10_BASIC_STATUS 0x400070b8 +#define CYDEV_PHUB_CH11_BASE 0x400070c0 +#define CYDEV_PHUB_CH11_SIZE 0x0000000c +#define CYREG_PHUB_CH11_BASIC_CFG 0x400070c0 +#define CYREG_PHUB_CH11_ACTION 0x400070c4 +#define CYREG_PHUB_CH11_BASIC_STATUS 0x400070c8 +#define CYDEV_PHUB_CH12_BASE 0x400070d0 +#define CYDEV_PHUB_CH12_SIZE 0x0000000c +#define CYREG_PHUB_CH12_BASIC_CFG 0x400070d0 +#define CYREG_PHUB_CH12_ACTION 0x400070d4 +#define CYREG_PHUB_CH12_BASIC_STATUS 0x400070d8 +#define CYDEV_PHUB_CH13_BASE 0x400070e0 +#define CYDEV_PHUB_CH13_SIZE 0x0000000c +#define CYREG_PHUB_CH13_BASIC_CFG 0x400070e0 +#define CYREG_PHUB_CH13_ACTION 0x400070e4 +#define CYREG_PHUB_CH13_BASIC_STATUS 0x400070e8 +#define CYDEV_PHUB_CH14_BASE 0x400070f0 +#define CYDEV_PHUB_CH14_SIZE 0x0000000c +#define CYREG_PHUB_CH14_BASIC_CFG 0x400070f0 +#define CYREG_PHUB_CH14_ACTION 0x400070f4 +#define CYREG_PHUB_CH14_BASIC_STATUS 0x400070f8 +#define CYDEV_PHUB_CH15_BASE 0x40007100 +#define CYDEV_PHUB_CH15_SIZE 0x0000000c +#define CYREG_PHUB_CH15_BASIC_CFG 0x40007100 +#define CYREG_PHUB_CH15_ACTION 0x40007104 +#define CYREG_PHUB_CH15_BASIC_STATUS 0x40007108 +#define CYDEV_PHUB_CH16_BASE 0x40007110 +#define CYDEV_PHUB_CH16_SIZE 0x0000000c +#define CYREG_PHUB_CH16_BASIC_CFG 0x40007110 +#define CYREG_PHUB_CH16_ACTION 0x40007114 +#define CYREG_PHUB_CH16_BASIC_STATUS 0x40007118 +#define CYDEV_PHUB_CH17_BASE 0x40007120 +#define CYDEV_PHUB_CH17_SIZE 0x0000000c +#define CYREG_PHUB_CH17_BASIC_CFG 0x40007120 +#define CYREG_PHUB_CH17_ACTION 0x40007124 +#define CYREG_PHUB_CH17_BASIC_STATUS 0x40007128 +#define CYDEV_PHUB_CH18_BASE 0x40007130 +#define CYDEV_PHUB_CH18_SIZE 0x0000000c +#define CYREG_PHUB_CH18_BASIC_CFG 0x40007130 +#define CYREG_PHUB_CH18_ACTION 0x40007134 +#define CYREG_PHUB_CH18_BASIC_STATUS 0x40007138 +#define CYDEV_PHUB_CH19_BASE 0x40007140 +#define CYDEV_PHUB_CH19_SIZE 0x0000000c +#define CYREG_PHUB_CH19_BASIC_CFG 0x40007140 +#define CYREG_PHUB_CH19_ACTION 0x40007144 +#define CYREG_PHUB_CH19_BASIC_STATUS 0x40007148 +#define CYDEV_PHUB_CH20_BASE 0x40007150 +#define CYDEV_PHUB_CH20_SIZE 0x0000000c +#define CYREG_PHUB_CH20_BASIC_CFG 0x40007150 +#define CYREG_PHUB_CH20_ACTION 0x40007154 +#define CYREG_PHUB_CH20_BASIC_STATUS 0x40007158 +#define CYDEV_PHUB_CH21_BASE 0x40007160 +#define CYDEV_PHUB_CH21_SIZE 0x0000000c +#define CYREG_PHUB_CH21_BASIC_CFG 0x40007160 +#define CYREG_PHUB_CH21_ACTION 0x40007164 +#define CYREG_PHUB_CH21_BASIC_STATUS 0x40007168 +#define CYDEV_PHUB_CH22_BASE 0x40007170 +#define CYDEV_PHUB_CH22_SIZE 0x0000000c +#define CYREG_PHUB_CH22_BASIC_CFG 0x40007170 +#define CYREG_PHUB_CH22_ACTION 0x40007174 +#define CYREG_PHUB_CH22_BASIC_STATUS 0x40007178 +#define CYDEV_PHUB_CH23_BASE 0x40007180 +#define CYDEV_PHUB_CH23_SIZE 0x0000000c +#define CYREG_PHUB_CH23_BASIC_CFG 0x40007180 +#define CYREG_PHUB_CH23_ACTION 0x40007184 +#define CYREG_PHUB_CH23_BASIC_STATUS 0x40007188 +#define CYDEV_PHUB_CFGMEM0_BASE 0x40007600 +#define CYDEV_PHUB_CFGMEM0_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM0_CFG0 0x40007600 +#define CYREG_PHUB_CFGMEM0_CFG1 0x40007604 +#define CYDEV_PHUB_CFGMEM1_BASE 0x40007608 +#define CYDEV_PHUB_CFGMEM1_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM1_CFG0 0x40007608 +#define CYREG_PHUB_CFGMEM1_CFG1 0x4000760c +#define CYDEV_PHUB_CFGMEM2_BASE 0x40007610 +#define CYDEV_PHUB_CFGMEM2_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM2_CFG0 0x40007610 +#define CYREG_PHUB_CFGMEM2_CFG1 0x40007614 +#define CYDEV_PHUB_CFGMEM3_BASE 0x40007618 +#define CYDEV_PHUB_CFGMEM3_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM3_CFG0 0x40007618 +#define CYREG_PHUB_CFGMEM3_CFG1 0x4000761c +#define CYDEV_PHUB_CFGMEM4_BASE 0x40007620 +#define CYDEV_PHUB_CFGMEM4_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM4_CFG0 0x40007620 +#define CYREG_PHUB_CFGMEM4_CFG1 0x40007624 +#define CYDEV_PHUB_CFGMEM5_BASE 0x40007628 +#define CYDEV_PHUB_CFGMEM5_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM5_CFG0 0x40007628 +#define CYREG_PHUB_CFGMEM5_CFG1 0x4000762c +#define CYDEV_PHUB_CFGMEM6_BASE 0x40007630 +#define CYDEV_PHUB_CFGMEM6_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM6_CFG0 0x40007630 +#define CYREG_PHUB_CFGMEM6_CFG1 0x40007634 +#define CYDEV_PHUB_CFGMEM7_BASE 0x40007638 +#define CYDEV_PHUB_CFGMEM7_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM7_CFG0 0x40007638 +#define CYREG_PHUB_CFGMEM7_CFG1 0x4000763c +#define CYDEV_PHUB_CFGMEM8_BASE 0x40007640 +#define CYDEV_PHUB_CFGMEM8_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM8_CFG0 0x40007640 +#define CYREG_PHUB_CFGMEM8_CFG1 0x40007644 +#define CYDEV_PHUB_CFGMEM9_BASE 0x40007648 +#define CYDEV_PHUB_CFGMEM9_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM9_CFG0 0x40007648 +#define CYREG_PHUB_CFGMEM9_CFG1 0x4000764c +#define CYDEV_PHUB_CFGMEM10_BASE 0x40007650 +#define CYDEV_PHUB_CFGMEM10_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM10_CFG0 0x40007650 +#define CYREG_PHUB_CFGMEM10_CFG1 0x40007654 +#define CYDEV_PHUB_CFGMEM11_BASE 0x40007658 +#define CYDEV_PHUB_CFGMEM11_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM11_CFG0 0x40007658 +#define CYREG_PHUB_CFGMEM11_CFG1 0x4000765c +#define CYDEV_PHUB_CFGMEM12_BASE 0x40007660 +#define CYDEV_PHUB_CFGMEM12_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM12_CFG0 0x40007660 +#define CYREG_PHUB_CFGMEM12_CFG1 0x40007664 +#define CYDEV_PHUB_CFGMEM13_BASE 0x40007668 +#define CYDEV_PHUB_CFGMEM13_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM13_CFG0 0x40007668 +#define CYREG_PHUB_CFGMEM13_CFG1 0x4000766c +#define CYDEV_PHUB_CFGMEM14_BASE 0x40007670 +#define CYDEV_PHUB_CFGMEM14_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM14_CFG0 0x40007670 +#define CYREG_PHUB_CFGMEM14_CFG1 0x40007674 +#define CYDEV_PHUB_CFGMEM15_BASE 0x40007678 +#define CYDEV_PHUB_CFGMEM15_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM15_CFG0 0x40007678 +#define CYREG_PHUB_CFGMEM15_CFG1 0x4000767c +#define CYDEV_PHUB_CFGMEM16_BASE 0x40007680 +#define CYDEV_PHUB_CFGMEM16_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM16_CFG0 0x40007680 +#define CYREG_PHUB_CFGMEM16_CFG1 0x40007684 +#define CYDEV_PHUB_CFGMEM17_BASE 0x40007688 +#define CYDEV_PHUB_CFGMEM17_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM17_CFG0 0x40007688 +#define CYREG_PHUB_CFGMEM17_CFG1 0x4000768c +#define CYDEV_PHUB_CFGMEM18_BASE 0x40007690 +#define CYDEV_PHUB_CFGMEM18_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM18_CFG0 0x40007690 +#define CYREG_PHUB_CFGMEM18_CFG1 0x40007694 +#define CYDEV_PHUB_CFGMEM19_BASE 0x40007698 +#define CYDEV_PHUB_CFGMEM19_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM19_CFG0 0x40007698 +#define CYREG_PHUB_CFGMEM19_CFG1 0x4000769c +#define CYDEV_PHUB_CFGMEM20_BASE 0x400076a0 +#define CYDEV_PHUB_CFGMEM20_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM20_CFG0 0x400076a0 +#define CYREG_PHUB_CFGMEM20_CFG1 0x400076a4 +#define CYDEV_PHUB_CFGMEM21_BASE 0x400076a8 +#define CYDEV_PHUB_CFGMEM21_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM21_CFG0 0x400076a8 +#define CYREG_PHUB_CFGMEM21_CFG1 0x400076ac +#define CYDEV_PHUB_CFGMEM22_BASE 0x400076b0 +#define CYDEV_PHUB_CFGMEM22_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM22_CFG0 0x400076b0 +#define CYREG_PHUB_CFGMEM22_CFG1 0x400076b4 +#define CYDEV_PHUB_CFGMEM23_BASE 0x400076b8 +#define CYDEV_PHUB_CFGMEM23_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM23_CFG0 0x400076b8 +#define CYREG_PHUB_CFGMEM23_CFG1 0x400076bc +#define CYDEV_PHUB_TDMEM0_BASE 0x40007800 +#define CYDEV_PHUB_TDMEM0_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM0_ORIG_TD0 0x40007800 +#define CYREG_PHUB_TDMEM0_ORIG_TD1 0x40007804 +#define CYDEV_PHUB_TDMEM1_BASE 0x40007808 +#define CYDEV_PHUB_TDMEM1_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM1_ORIG_TD0 0x40007808 +#define CYREG_PHUB_TDMEM1_ORIG_TD1 0x4000780c +#define CYDEV_PHUB_TDMEM2_BASE 0x40007810 +#define CYDEV_PHUB_TDMEM2_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM2_ORIG_TD0 0x40007810 +#define CYREG_PHUB_TDMEM2_ORIG_TD1 0x40007814 +#define CYDEV_PHUB_TDMEM3_BASE 0x40007818 +#define CYDEV_PHUB_TDMEM3_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM3_ORIG_TD0 0x40007818 +#define CYREG_PHUB_TDMEM3_ORIG_TD1 0x4000781c +#define CYDEV_PHUB_TDMEM4_BASE 0x40007820 +#define CYDEV_PHUB_TDMEM4_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM4_ORIG_TD0 0x40007820 +#define CYREG_PHUB_TDMEM4_ORIG_TD1 0x40007824 +#define CYDEV_PHUB_TDMEM5_BASE 0x40007828 +#define CYDEV_PHUB_TDMEM5_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM5_ORIG_TD0 0x40007828 +#define CYREG_PHUB_TDMEM5_ORIG_TD1 0x4000782c +#define CYDEV_PHUB_TDMEM6_BASE 0x40007830 +#define CYDEV_PHUB_TDMEM6_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM6_ORIG_TD0 0x40007830 +#define CYREG_PHUB_TDMEM6_ORIG_TD1 0x40007834 +#define CYDEV_PHUB_TDMEM7_BASE 0x40007838 +#define CYDEV_PHUB_TDMEM7_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM7_ORIG_TD0 0x40007838 +#define CYREG_PHUB_TDMEM7_ORIG_TD1 0x4000783c +#define CYDEV_PHUB_TDMEM8_BASE 0x40007840 +#define CYDEV_PHUB_TDMEM8_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM8_ORIG_TD0 0x40007840 +#define CYREG_PHUB_TDMEM8_ORIG_TD1 0x40007844 +#define CYDEV_PHUB_TDMEM9_BASE 0x40007848 +#define CYDEV_PHUB_TDMEM9_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM9_ORIG_TD0 0x40007848 +#define CYREG_PHUB_TDMEM9_ORIG_TD1 0x4000784c +#define CYDEV_PHUB_TDMEM10_BASE 0x40007850 +#define CYDEV_PHUB_TDMEM10_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM10_ORIG_TD0 0x40007850 +#define CYREG_PHUB_TDMEM10_ORIG_TD1 0x40007854 +#define CYDEV_PHUB_TDMEM11_BASE 0x40007858 +#define CYDEV_PHUB_TDMEM11_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM11_ORIG_TD0 0x40007858 +#define CYREG_PHUB_TDMEM11_ORIG_TD1 0x4000785c +#define CYDEV_PHUB_TDMEM12_BASE 0x40007860 +#define CYDEV_PHUB_TDMEM12_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM12_ORIG_TD0 0x40007860 +#define CYREG_PHUB_TDMEM12_ORIG_TD1 0x40007864 +#define CYDEV_PHUB_TDMEM13_BASE 0x40007868 +#define CYDEV_PHUB_TDMEM13_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM13_ORIG_TD0 0x40007868 +#define CYREG_PHUB_TDMEM13_ORIG_TD1 0x4000786c +#define CYDEV_PHUB_TDMEM14_BASE 0x40007870 +#define CYDEV_PHUB_TDMEM14_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM14_ORIG_TD0 0x40007870 +#define CYREG_PHUB_TDMEM14_ORIG_TD1 0x40007874 +#define CYDEV_PHUB_TDMEM15_BASE 0x40007878 +#define CYDEV_PHUB_TDMEM15_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM15_ORIG_TD0 0x40007878 +#define CYREG_PHUB_TDMEM15_ORIG_TD1 0x4000787c +#define CYDEV_PHUB_TDMEM16_BASE 0x40007880 +#define CYDEV_PHUB_TDMEM16_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM16_ORIG_TD0 0x40007880 +#define CYREG_PHUB_TDMEM16_ORIG_TD1 0x40007884 +#define CYDEV_PHUB_TDMEM17_BASE 0x40007888 +#define CYDEV_PHUB_TDMEM17_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM17_ORIG_TD0 0x40007888 +#define CYREG_PHUB_TDMEM17_ORIG_TD1 0x4000788c +#define CYDEV_PHUB_TDMEM18_BASE 0x40007890 +#define CYDEV_PHUB_TDMEM18_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM18_ORIG_TD0 0x40007890 +#define CYREG_PHUB_TDMEM18_ORIG_TD1 0x40007894 +#define CYDEV_PHUB_TDMEM19_BASE 0x40007898 +#define CYDEV_PHUB_TDMEM19_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM19_ORIG_TD0 0x40007898 +#define CYREG_PHUB_TDMEM19_ORIG_TD1 0x4000789c +#define CYDEV_PHUB_TDMEM20_BASE 0x400078a0 +#define CYDEV_PHUB_TDMEM20_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM20_ORIG_TD0 0x400078a0 +#define CYREG_PHUB_TDMEM20_ORIG_TD1 0x400078a4 +#define CYDEV_PHUB_TDMEM21_BASE 0x400078a8 +#define CYDEV_PHUB_TDMEM21_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM21_ORIG_TD0 0x400078a8 +#define CYREG_PHUB_TDMEM21_ORIG_TD1 0x400078ac +#define CYDEV_PHUB_TDMEM22_BASE 0x400078b0 +#define CYDEV_PHUB_TDMEM22_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM22_ORIG_TD0 0x400078b0 +#define CYREG_PHUB_TDMEM22_ORIG_TD1 0x400078b4 +#define CYDEV_PHUB_TDMEM23_BASE 0x400078b8 +#define CYDEV_PHUB_TDMEM23_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM23_ORIG_TD0 0x400078b8 +#define CYREG_PHUB_TDMEM23_ORIG_TD1 0x400078bc +#define CYDEV_PHUB_TDMEM24_BASE 0x400078c0 +#define CYDEV_PHUB_TDMEM24_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM24_ORIG_TD0 0x400078c0 +#define CYREG_PHUB_TDMEM24_ORIG_TD1 0x400078c4 +#define CYDEV_PHUB_TDMEM25_BASE 0x400078c8 +#define CYDEV_PHUB_TDMEM25_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM25_ORIG_TD0 0x400078c8 +#define CYREG_PHUB_TDMEM25_ORIG_TD1 0x400078cc +#define CYDEV_PHUB_TDMEM26_BASE 0x400078d0 +#define CYDEV_PHUB_TDMEM26_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM26_ORIG_TD0 0x400078d0 +#define CYREG_PHUB_TDMEM26_ORIG_TD1 0x400078d4 +#define CYDEV_PHUB_TDMEM27_BASE 0x400078d8 +#define CYDEV_PHUB_TDMEM27_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM27_ORIG_TD0 0x400078d8 +#define CYREG_PHUB_TDMEM27_ORIG_TD1 0x400078dc +#define CYDEV_PHUB_TDMEM28_BASE 0x400078e0 +#define CYDEV_PHUB_TDMEM28_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM28_ORIG_TD0 0x400078e0 +#define CYREG_PHUB_TDMEM28_ORIG_TD1 0x400078e4 +#define CYDEV_PHUB_TDMEM29_BASE 0x400078e8 +#define CYDEV_PHUB_TDMEM29_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM29_ORIG_TD0 0x400078e8 +#define CYREG_PHUB_TDMEM29_ORIG_TD1 0x400078ec +#define CYDEV_PHUB_TDMEM30_BASE 0x400078f0 +#define CYDEV_PHUB_TDMEM30_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM30_ORIG_TD0 0x400078f0 +#define CYREG_PHUB_TDMEM30_ORIG_TD1 0x400078f4 +#define CYDEV_PHUB_TDMEM31_BASE 0x400078f8 +#define CYDEV_PHUB_TDMEM31_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM31_ORIG_TD0 0x400078f8 +#define CYREG_PHUB_TDMEM31_ORIG_TD1 0x400078fc +#define CYDEV_PHUB_TDMEM32_BASE 0x40007900 +#define CYDEV_PHUB_TDMEM32_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM32_ORIG_TD0 0x40007900 +#define CYREG_PHUB_TDMEM32_ORIG_TD1 0x40007904 +#define CYDEV_PHUB_TDMEM33_BASE 0x40007908 +#define CYDEV_PHUB_TDMEM33_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM33_ORIG_TD0 0x40007908 +#define CYREG_PHUB_TDMEM33_ORIG_TD1 0x4000790c +#define CYDEV_PHUB_TDMEM34_BASE 0x40007910 +#define CYDEV_PHUB_TDMEM34_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM34_ORIG_TD0 0x40007910 +#define CYREG_PHUB_TDMEM34_ORIG_TD1 0x40007914 +#define CYDEV_PHUB_TDMEM35_BASE 0x40007918 +#define CYDEV_PHUB_TDMEM35_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM35_ORIG_TD0 0x40007918 +#define CYREG_PHUB_TDMEM35_ORIG_TD1 0x4000791c +#define CYDEV_PHUB_TDMEM36_BASE 0x40007920 +#define CYDEV_PHUB_TDMEM36_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM36_ORIG_TD0 0x40007920 +#define CYREG_PHUB_TDMEM36_ORIG_TD1 0x40007924 +#define CYDEV_PHUB_TDMEM37_BASE 0x40007928 +#define CYDEV_PHUB_TDMEM37_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM37_ORIG_TD0 0x40007928 +#define CYREG_PHUB_TDMEM37_ORIG_TD1 0x4000792c +#define CYDEV_PHUB_TDMEM38_BASE 0x40007930 +#define CYDEV_PHUB_TDMEM38_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM38_ORIG_TD0 0x40007930 +#define CYREG_PHUB_TDMEM38_ORIG_TD1 0x40007934 +#define CYDEV_PHUB_TDMEM39_BASE 0x40007938 +#define CYDEV_PHUB_TDMEM39_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM39_ORIG_TD0 0x40007938 +#define CYREG_PHUB_TDMEM39_ORIG_TD1 0x4000793c +#define CYDEV_PHUB_TDMEM40_BASE 0x40007940 +#define CYDEV_PHUB_TDMEM40_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM40_ORIG_TD0 0x40007940 +#define CYREG_PHUB_TDMEM40_ORIG_TD1 0x40007944 +#define CYDEV_PHUB_TDMEM41_BASE 0x40007948 +#define CYDEV_PHUB_TDMEM41_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM41_ORIG_TD0 0x40007948 +#define CYREG_PHUB_TDMEM41_ORIG_TD1 0x4000794c +#define CYDEV_PHUB_TDMEM42_BASE 0x40007950 +#define CYDEV_PHUB_TDMEM42_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM42_ORIG_TD0 0x40007950 +#define CYREG_PHUB_TDMEM42_ORIG_TD1 0x40007954 +#define CYDEV_PHUB_TDMEM43_BASE 0x40007958 +#define CYDEV_PHUB_TDMEM43_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM43_ORIG_TD0 0x40007958 +#define CYREG_PHUB_TDMEM43_ORIG_TD1 0x4000795c +#define CYDEV_PHUB_TDMEM44_BASE 0x40007960 +#define CYDEV_PHUB_TDMEM44_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM44_ORIG_TD0 0x40007960 +#define CYREG_PHUB_TDMEM44_ORIG_TD1 0x40007964 +#define CYDEV_PHUB_TDMEM45_BASE 0x40007968 +#define CYDEV_PHUB_TDMEM45_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM45_ORIG_TD0 0x40007968 +#define CYREG_PHUB_TDMEM45_ORIG_TD1 0x4000796c +#define CYDEV_PHUB_TDMEM46_BASE 0x40007970 +#define CYDEV_PHUB_TDMEM46_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM46_ORIG_TD0 0x40007970 +#define CYREG_PHUB_TDMEM46_ORIG_TD1 0x40007974 +#define CYDEV_PHUB_TDMEM47_BASE 0x40007978 +#define CYDEV_PHUB_TDMEM47_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM47_ORIG_TD0 0x40007978 +#define CYREG_PHUB_TDMEM47_ORIG_TD1 0x4000797c +#define CYDEV_PHUB_TDMEM48_BASE 0x40007980 +#define CYDEV_PHUB_TDMEM48_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM48_ORIG_TD0 0x40007980 +#define CYREG_PHUB_TDMEM48_ORIG_TD1 0x40007984 +#define CYDEV_PHUB_TDMEM49_BASE 0x40007988 +#define CYDEV_PHUB_TDMEM49_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM49_ORIG_TD0 0x40007988 +#define CYREG_PHUB_TDMEM49_ORIG_TD1 0x4000798c +#define CYDEV_PHUB_TDMEM50_BASE 0x40007990 +#define CYDEV_PHUB_TDMEM50_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM50_ORIG_TD0 0x40007990 +#define CYREG_PHUB_TDMEM50_ORIG_TD1 0x40007994 +#define CYDEV_PHUB_TDMEM51_BASE 0x40007998 +#define CYDEV_PHUB_TDMEM51_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM51_ORIG_TD0 0x40007998 +#define CYREG_PHUB_TDMEM51_ORIG_TD1 0x4000799c +#define CYDEV_PHUB_TDMEM52_BASE 0x400079a0 +#define CYDEV_PHUB_TDMEM52_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM52_ORIG_TD0 0x400079a0 +#define CYREG_PHUB_TDMEM52_ORIG_TD1 0x400079a4 +#define CYDEV_PHUB_TDMEM53_BASE 0x400079a8 +#define CYDEV_PHUB_TDMEM53_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM53_ORIG_TD0 0x400079a8 +#define CYREG_PHUB_TDMEM53_ORIG_TD1 0x400079ac +#define CYDEV_PHUB_TDMEM54_BASE 0x400079b0 +#define CYDEV_PHUB_TDMEM54_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM54_ORIG_TD0 0x400079b0 +#define CYREG_PHUB_TDMEM54_ORIG_TD1 0x400079b4 +#define CYDEV_PHUB_TDMEM55_BASE 0x400079b8 +#define CYDEV_PHUB_TDMEM55_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM55_ORIG_TD0 0x400079b8 +#define CYREG_PHUB_TDMEM55_ORIG_TD1 0x400079bc +#define CYDEV_PHUB_TDMEM56_BASE 0x400079c0 +#define CYDEV_PHUB_TDMEM56_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM56_ORIG_TD0 0x400079c0 +#define CYREG_PHUB_TDMEM56_ORIG_TD1 0x400079c4 +#define CYDEV_PHUB_TDMEM57_BASE 0x400079c8 +#define CYDEV_PHUB_TDMEM57_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM57_ORIG_TD0 0x400079c8 +#define CYREG_PHUB_TDMEM57_ORIG_TD1 0x400079cc +#define CYDEV_PHUB_TDMEM58_BASE 0x400079d0 +#define CYDEV_PHUB_TDMEM58_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM58_ORIG_TD0 0x400079d0 +#define CYREG_PHUB_TDMEM58_ORIG_TD1 0x400079d4 +#define CYDEV_PHUB_TDMEM59_BASE 0x400079d8 +#define CYDEV_PHUB_TDMEM59_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM59_ORIG_TD0 0x400079d8 +#define CYREG_PHUB_TDMEM59_ORIG_TD1 0x400079dc +#define CYDEV_PHUB_TDMEM60_BASE 0x400079e0 +#define CYDEV_PHUB_TDMEM60_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM60_ORIG_TD0 0x400079e0 +#define CYREG_PHUB_TDMEM60_ORIG_TD1 0x400079e4 +#define CYDEV_PHUB_TDMEM61_BASE 0x400079e8 +#define CYDEV_PHUB_TDMEM61_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM61_ORIG_TD0 0x400079e8 +#define CYREG_PHUB_TDMEM61_ORIG_TD1 0x400079ec +#define CYDEV_PHUB_TDMEM62_BASE 0x400079f0 +#define CYDEV_PHUB_TDMEM62_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM62_ORIG_TD0 0x400079f0 +#define CYREG_PHUB_TDMEM62_ORIG_TD1 0x400079f4 +#define CYDEV_PHUB_TDMEM63_BASE 0x400079f8 +#define CYDEV_PHUB_TDMEM63_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM63_ORIG_TD0 0x400079f8 +#define CYREG_PHUB_TDMEM63_ORIG_TD1 0x400079fc +#define CYDEV_PHUB_TDMEM64_BASE 0x40007a00 +#define CYDEV_PHUB_TDMEM64_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM64_ORIG_TD0 0x40007a00 +#define CYREG_PHUB_TDMEM64_ORIG_TD1 0x40007a04 +#define CYDEV_PHUB_TDMEM65_BASE 0x40007a08 +#define CYDEV_PHUB_TDMEM65_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM65_ORIG_TD0 0x40007a08 +#define CYREG_PHUB_TDMEM65_ORIG_TD1 0x40007a0c +#define CYDEV_PHUB_TDMEM66_BASE 0x40007a10 +#define CYDEV_PHUB_TDMEM66_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM66_ORIG_TD0 0x40007a10 +#define CYREG_PHUB_TDMEM66_ORIG_TD1 0x40007a14 +#define CYDEV_PHUB_TDMEM67_BASE 0x40007a18 +#define CYDEV_PHUB_TDMEM67_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM67_ORIG_TD0 0x40007a18 +#define CYREG_PHUB_TDMEM67_ORIG_TD1 0x40007a1c +#define CYDEV_PHUB_TDMEM68_BASE 0x40007a20 +#define CYDEV_PHUB_TDMEM68_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM68_ORIG_TD0 0x40007a20 +#define CYREG_PHUB_TDMEM68_ORIG_TD1 0x40007a24 +#define CYDEV_PHUB_TDMEM69_BASE 0x40007a28 +#define CYDEV_PHUB_TDMEM69_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM69_ORIG_TD0 0x40007a28 +#define CYREG_PHUB_TDMEM69_ORIG_TD1 0x40007a2c +#define CYDEV_PHUB_TDMEM70_BASE 0x40007a30 +#define CYDEV_PHUB_TDMEM70_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM70_ORIG_TD0 0x40007a30 +#define CYREG_PHUB_TDMEM70_ORIG_TD1 0x40007a34 +#define CYDEV_PHUB_TDMEM71_BASE 0x40007a38 +#define CYDEV_PHUB_TDMEM71_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM71_ORIG_TD0 0x40007a38 +#define CYREG_PHUB_TDMEM71_ORIG_TD1 0x40007a3c +#define CYDEV_PHUB_TDMEM72_BASE 0x40007a40 +#define CYDEV_PHUB_TDMEM72_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM72_ORIG_TD0 0x40007a40 +#define CYREG_PHUB_TDMEM72_ORIG_TD1 0x40007a44 +#define CYDEV_PHUB_TDMEM73_BASE 0x40007a48 +#define CYDEV_PHUB_TDMEM73_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM73_ORIG_TD0 0x40007a48 +#define CYREG_PHUB_TDMEM73_ORIG_TD1 0x40007a4c +#define CYDEV_PHUB_TDMEM74_BASE 0x40007a50 +#define CYDEV_PHUB_TDMEM74_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM74_ORIG_TD0 0x40007a50 +#define CYREG_PHUB_TDMEM74_ORIG_TD1 0x40007a54 +#define CYDEV_PHUB_TDMEM75_BASE 0x40007a58 +#define CYDEV_PHUB_TDMEM75_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM75_ORIG_TD0 0x40007a58 +#define CYREG_PHUB_TDMEM75_ORIG_TD1 0x40007a5c +#define CYDEV_PHUB_TDMEM76_BASE 0x40007a60 +#define CYDEV_PHUB_TDMEM76_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM76_ORIG_TD0 0x40007a60 +#define CYREG_PHUB_TDMEM76_ORIG_TD1 0x40007a64 +#define CYDEV_PHUB_TDMEM77_BASE 0x40007a68 +#define CYDEV_PHUB_TDMEM77_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM77_ORIG_TD0 0x40007a68 +#define CYREG_PHUB_TDMEM77_ORIG_TD1 0x40007a6c +#define CYDEV_PHUB_TDMEM78_BASE 0x40007a70 +#define CYDEV_PHUB_TDMEM78_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM78_ORIG_TD0 0x40007a70 +#define CYREG_PHUB_TDMEM78_ORIG_TD1 0x40007a74 +#define CYDEV_PHUB_TDMEM79_BASE 0x40007a78 +#define CYDEV_PHUB_TDMEM79_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM79_ORIG_TD0 0x40007a78 +#define CYREG_PHUB_TDMEM79_ORIG_TD1 0x40007a7c +#define CYDEV_PHUB_TDMEM80_BASE 0x40007a80 +#define CYDEV_PHUB_TDMEM80_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM80_ORIG_TD0 0x40007a80 +#define CYREG_PHUB_TDMEM80_ORIG_TD1 0x40007a84 +#define CYDEV_PHUB_TDMEM81_BASE 0x40007a88 +#define CYDEV_PHUB_TDMEM81_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM81_ORIG_TD0 0x40007a88 +#define CYREG_PHUB_TDMEM81_ORIG_TD1 0x40007a8c +#define CYDEV_PHUB_TDMEM82_BASE 0x40007a90 +#define CYDEV_PHUB_TDMEM82_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM82_ORIG_TD0 0x40007a90 +#define CYREG_PHUB_TDMEM82_ORIG_TD1 0x40007a94 +#define CYDEV_PHUB_TDMEM83_BASE 0x40007a98 +#define CYDEV_PHUB_TDMEM83_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM83_ORIG_TD0 0x40007a98 +#define CYREG_PHUB_TDMEM83_ORIG_TD1 0x40007a9c +#define CYDEV_PHUB_TDMEM84_BASE 0x40007aa0 +#define CYDEV_PHUB_TDMEM84_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM84_ORIG_TD0 0x40007aa0 +#define CYREG_PHUB_TDMEM84_ORIG_TD1 0x40007aa4 +#define CYDEV_PHUB_TDMEM85_BASE 0x40007aa8 +#define CYDEV_PHUB_TDMEM85_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM85_ORIG_TD0 0x40007aa8 +#define CYREG_PHUB_TDMEM85_ORIG_TD1 0x40007aac +#define CYDEV_PHUB_TDMEM86_BASE 0x40007ab0 +#define CYDEV_PHUB_TDMEM86_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM86_ORIG_TD0 0x40007ab0 +#define CYREG_PHUB_TDMEM86_ORIG_TD1 0x40007ab4 +#define CYDEV_PHUB_TDMEM87_BASE 0x40007ab8 +#define CYDEV_PHUB_TDMEM87_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM87_ORIG_TD0 0x40007ab8 +#define CYREG_PHUB_TDMEM87_ORIG_TD1 0x40007abc +#define CYDEV_PHUB_TDMEM88_BASE 0x40007ac0 +#define CYDEV_PHUB_TDMEM88_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM88_ORIG_TD0 0x40007ac0 +#define CYREG_PHUB_TDMEM88_ORIG_TD1 0x40007ac4 +#define CYDEV_PHUB_TDMEM89_BASE 0x40007ac8 +#define CYDEV_PHUB_TDMEM89_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM89_ORIG_TD0 0x40007ac8 +#define CYREG_PHUB_TDMEM89_ORIG_TD1 0x40007acc +#define CYDEV_PHUB_TDMEM90_BASE 0x40007ad0 +#define CYDEV_PHUB_TDMEM90_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM90_ORIG_TD0 0x40007ad0 +#define CYREG_PHUB_TDMEM90_ORIG_TD1 0x40007ad4 +#define CYDEV_PHUB_TDMEM91_BASE 0x40007ad8 +#define CYDEV_PHUB_TDMEM91_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM91_ORIG_TD0 0x40007ad8 +#define CYREG_PHUB_TDMEM91_ORIG_TD1 0x40007adc +#define CYDEV_PHUB_TDMEM92_BASE 0x40007ae0 +#define CYDEV_PHUB_TDMEM92_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM92_ORIG_TD0 0x40007ae0 +#define CYREG_PHUB_TDMEM92_ORIG_TD1 0x40007ae4 +#define CYDEV_PHUB_TDMEM93_BASE 0x40007ae8 +#define CYDEV_PHUB_TDMEM93_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM93_ORIG_TD0 0x40007ae8 +#define CYREG_PHUB_TDMEM93_ORIG_TD1 0x40007aec +#define CYDEV_PHUB_TDMEM94_BASE 0x40007af0 +#define CYDEV_PHUB_TDMEM94_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM94_ORIG_TD0 0x40007af0 +#define CYREG_PHUB_TDMEM94_ORIG_TD1 0x40007af4 +#define CYDEV_PHUB_TDMEM95_BASE 0x40007af8 +#define CYDEV_PHUB_TDMEM95_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM95_ORIG_TD0 0x40007af8 +#define CYREG_PHUB_TDMEM95_ORIG_TD1 0x40007afc +#define CYDEV_PHUB_TDMEM96_BASE 0x40007b00 +#define CYDEV_PHUB_TDMEM96_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM96_ORIG_TD0 0x40007b00 +#define CYREG_PHUB_TDMEM96_ORIG_TD1 0x40007b04 +#define CYDEV_PHUB_TDMEM97_BASE 0x40007b08 +#define CYDEV_PHUB_TDMEM97_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM97_ORIG_TD0 0x40007b08 +#define CYREG_PHUB_TDMEM97_ORIG_TD1 0x40007b0c +#define CYDEV_PHUB_TDMEM98_BASE 0x40007b10 +#define CYDEV_PHUB_TDMEM98_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM98_ORIG_TD0 0x40007b10 +#define CYREG_PHUB_TDMEM98_ORIG_TD1 0x40007b14 +#define CYDEV_PHUB_TDMEM99_BASE 0x40007b18 +#define CYDEV_PHUB_TDMEM99_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM99_ORIG_TD0 0x40007b18 +#define CYREG_PHUB_TDMEM99_ORIG_TD1 0x40007b1c +#define CYDEV_PHUB_TDMEM100_BASE 0x40007b20 +#define CYDEV_PHUB_TDMEM100_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM100_ORIG_TD0 0x40007b20 +#define CYREG_PHUB_TDMEM100_ORIG_TD1 0x40007b24 +#define CYDEV_PHUB_TDMEM101_BASE 0x40007b28 +#define CYDEV_PHUB_TDMEM101_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM101_ORIG_TD0 0x40007b28 +#define CYREG_PHUB_TDMEM101_ORIG_TD1 0x40007b2c +#define CYDEV_PHUB_TDMEM102_BASE 0x40007b30 +#define CYDEV_PHUB_TDMEM102_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM102_ORIG_TD0 0x40007b30 +#define CYREG_PHUB_TDMEM102_ORIG_TD1 0x40007b34 +#define CYDEV_PHUB_TDMEM103_BASE 0x40007b38 +#define CYDEV_PHUB_TDMEM103_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM103_ORIG_TD0 0x40007b38 +#define CYREG_PHUB_TDMEM103_ORIG_TD1 0x40007b3c +#define CYDEV_PHUB_TDMEM104_BASE 0x40007b40 +#define CYDEV_PHUB_TDMEM104_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM104_ORIG_TD0 0x40007b40 +#define CYREG_PHUB_TDMEM104_ORIG_TD1 0x40007b44 +#define CYDEV_PHUB_TDMEM105_BASE 0x40007b48 +#define CYDEV_PHUB_TDMEM105_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM105_ORIG_TD0 0x40007b48 +#define CYREG_PHUB_TDMEM105_ORIG_TD1 0x40007b4c +#define CYDEV_PHUB_TDMEM106_BASE 0x40007b50 +#define CYDEV_PHUB_TDMEM106_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM106_ORIG_TD0 0x40007b50 +#define CYREG_PHUB_TDMEM106_ORIG_TD1 0x40007b54 +#define CYDEV_PHUB_TDMEM107_BASE 0x40007b58 +#define CYDEV_PHUB_TDMEM107_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM107_ORIG_TD0 0x40007b58 +#define CYREG_PHUB_TDMEM107_ORIG_TD1 0x40007b5c +#define CYDEV_PHUB_TDMEM108_BASE 0x40007b60 +#define CYDEV_PHUB_TDMEM108_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM108_ORIG_TD0 0x40007b60 +#define CYREG_PHUB_TDMEM108_ORIG_TD1 0x40007b64 +#define CYDEV_PHUB_TDMEM109_BASE 0x40007b68 +#define CYDEV_PHUB_TDMEM109_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM109_ORIG_TD0 0x40007b68 +#define CYREG_PHUB_TDMEM109_ORIG_TD1 0x40007b6c +#define CYDEV_PHUB_TDMEM110_BASE 0x40007b70 +#define CYDEV_PHUB_TDMEM110_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM110_ORIG_TD0 0x40007b70 +#define CYREG_PHUB_TDMEM110_ORIG_TD1 0x40007b74 +#define CYDEV_PHUB_TDMEM111_BASE 0x40007b78 +#define CYDEV_PHUB_TDMEM111_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM111_ORIG_TD0 0x40007b78 +#define CYREG_PHUB_TDMEM111_ORIG_TD1 0x40007b7c +#define CYDEV_PHUB_TDMEM112_BASE 0x40007b80 +#define CYDEV_PHUB_TDMEM112_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM112_ORIG_TD0 0x40007b80 +#define CYREG_PHUB_TDMEM112_ORIG_TD1 0x40007b84 +#define CYDEV_PHUB_TDMEM113_BASE 0x40007b88 +#define CYDEV_PHUB_TDMEM113_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM113_ORIG_TD0 0x40007b88 +#define CYREG_PHUB_TDMEM113_ORIG_TD1 0x40007b8c +#define CYDEV_PHUB_TDMEM114_BASE 0x40007b90 +#define CYDEV_PHUB_TDMEM114_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM114_ORIG_TD0 0x40007b90 +#define CYREG_PHUB_TDMEM114_ORIG_TD1 0x40007b94 +#define CYDEV_PHUB_TDMEM115_BASE 0x40007b98 +#define CYDEV_PHUB_TDMEM115_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM115_ORIG_TD0 0x40007b98 +#define CYREG_PHUB_TDMEM115_ORIG_TD1 0x40007b9c +#define CYDEV_PHUB_TDMEM116_BASE 0x40007ba0 +#define CYDEV_PHUB_TDMEM116_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM116_ORIG_TD0 0x40007ba0 +#define CYREG_PHUB_TDMEM116_ORIG_TD1 0x40007ba4 +#define CYDEV_PHUB_TDMEM117_BASE 0x40007ba8 +#define CYDEV_PHUB_TDMEM117_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM117_ORIG_TD0 0x40007ba8 +#define CYREG_PHUB_TDMEM117_ORIG_TD1 0x40007bac +#define CYDEV_PHUB_TDMEM118_BASE 0x40007bb0 +#define CYDEV_PHUB_TDMEM118_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM118_ORIG_TD0 0x40007bb0 +#define CYREG_PHUB_TDMEM118_ORIG_TD1 0x40007bb4 +#define CYDEV_PHUB_TDMEM119_BASE 0x40007bb8 +#define CYDEV_PHUB_TDMEM119_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM119_ORIG_TD0 0x40007bb8 +#define CYREG_PHUB_TDMEM119_ORIG_TD1 0x40007bbc +#define CYDEV_PHUB_TDMEM120_BASE 0x40007bc0 +#define CYDEV_PHUB_TDMEM120_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM120_ORIG_TD0 0x40007bc0 +#define CYREG_PHUB_TDMEM120_ORIG_TD1 0x40007bc4 +#define CYDEV_PHUB_TDMEM121_BASE 0x40007bc8 +#define CYDEV_PHUB_TDMEM121_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM121_ORIG_TD0 0x40007bc8 +#define CYREG_PHUB_TDMEM121_ORIG_TD1 0x40007bcc +#define CYDEV_PHUB_TDMEM122_BASE 0x40007bd0 +#define CYDEV_PHUB_TDMEM122_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM122_ORIG_TD0 0x40007bd0 +#define CYREG_PHUB_TDMEM122_ORIG_TD1 0x40007bd4 +#define CYDEV_PHUB_TDMEM123_BASE 0x40007bd8 +#define CYDEV_PHUB_TDMEM123_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM123_ORIG_TD0 0x40007bd8 +#define CYREG_PHUB_TDMEM123_ORIG_TD1 0x40007bdc +#define CYDEV_PHUB_TDMEM124_BASE 0x40007be0 +#define CYDEV_PHUB_TDMEM124_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM124_ORIG_TD0 0x40007be0 +#define CYREG_PHUB_TDMEM124_ORIG_TD1 0x40007be4 +#define CYDEV_PHUB_TDMEM125_BASE 0x40007be8 +#define CYDEV_PHUB_TDMEM125_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM125_ORIG_TD0 0x40007be8 +#define CYREG_PHUB_TDMEM125_ORIG_TD1 0x40007bec +#define CYDEV_PHUB_TDMEM126_BASE 0x40007bf0 +#define CYDEV_PHUB_TDMEM126_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM126_ORIG_TD0 0x40007bf0 +#define CYREG_PHUB_TDMEM126_ORIG_TD1 0x40007bf4 +#define CYDEV_PHUB_TDMEM127_BASE 0x40007bf8 +#define CYDEV_PHUB_TDMEM127_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM127_ORIG_TD0 0x40007bf8 +#define CYREG_PHUB_TDMEM127_ORIG_TD1 0x40007bfc +#define CYDEV_EE_BASE 0x40008000 +#define CYDEV_EE_SIZE 0x00000800 +#define CYREG_EE_DATA_MBASE 0x40008000 +#define CYREG_EE_DATA_MSIZE 0x00000800 +#define CYDEV_CAN0_BASE 0x4000a000 +#define CYDEV_CAN0_SIZE 0x000002a0 +#define CYDEV_CAN0_CSR_BASE 0x4000a000 +#define CYDEV_CAN0_CSR_SIZE 0x00000018 +#define CYREG_CAN0_CSR_INT_SR 0x4000a000 +#define CYREG_CAN0_CSR_INT_EN 0x4000a004 +#define CYREG_CAN0_CSR_BUF_SR 0x4000a008 +#define CYREG_CAN0_CSR_ERR_SR 0x4000a00c +#define CYREG_CAN0_CSR_CMD 0x4000a010 +#define CYREG_CAN0_CSR_CFG 0x4000a014 +#define CYDEV_CAN0_TX0_BASE 0x4000a020 +#define CYDEV_CAN0_TX0_SIZE 0x00000010 +#define CYREG_CAN0_TX0_CMD 0x4000a020 +#define CYREG_CAN0_TX0_ID 0x4000a024 +#define CYREG_CAN0_TX0_DH 0x4000a028 +#define CYREG_CAN0_TX0_DL 0x4000a02c +#define CYDEV_CAN0_TX1_BASE 0x4000a030 +#define CYDEV_CAN0_TX1_SIZE 0x00000010 +#define CYREG_CAN0_TX1_CMD 0x4000a030 +#define CYREG_CAN0_TX1_ID 0x4000a034 +#define CYREG_CAN0_TX1_DH 0x4000a038 +#define CYREG_CAN0_TX1_DL 0x4000a03c +#define CYDEV_CAN0_TX2_BASE 0x4000a040 +#define CYDEV_CAN0_TX2_SIZE 0x00000010 +#define CYREG_CAN0_TX2_CMD 0x4000a040 +#define CYREG_CAN0_TX2_ID 0x4000a044 +#define CYREG_CAN0_TX2_DH 0x4000a048 +#define CYREG_CAN0_TX2_DL 0x4000a04c +#define CYDEV_CAN0_TX3_BASE 0x4000a050 +#define CYDEV_CAN0_TX3_SIZE 0x00000010 +#define CYREG_CAN0_TX3_CMD 0x4000a050 +#define CYREG_CAN0_TX3_ID 0x4000a054 +#define CYREG_CAN0_TX3_DH 0x4000a058 +#define CYREG_CAN0_TX3_DL 0x4000a05c +#define CYDEV_CAN0_TX4_BASE 0x4000a060 +#define CYDEV_CAN0_TX4_SIZE 0x00000010 +#define CYREG_CAN0_TX4_CMD 0x4000a060 +#define CYREG_CAN0_TX4_ID 0x4000a064 +#define CYREG_CAN0_TX4_DH 0x4000a068 +#define CYREG_CAN0_TX4_DL 0x4000a06c +#define CYDEV_CAN0_TX5_BASE 0x4000a070 +#define CYDEV_CAN0_TX5_SIZE 0x00000010 +#define CYREG_CAN0_TX5_CMD 0x4000a070 +#define CYREG_CAN0_TX5_ID 0x4000a074 +#define CYREG_CAN0_TX5_DH 0x4000a078 +#define CYREG_CAN0_TX5_DL 0x4000a07c +#define CYDEV_CAN0_TX6_BASE 0x4000a080 +#define CYDEV_CAN0_TX6_SIZE 0x00000010 +#define CYREG_CAN0_TX6_CMD 0x4000a080 +#define CYREG_CAN0_TX6_ID 0x4000a084 +#define CYREG_CAN0_TX6_DH 0x4000a088 +#define CYREG_CAN0_TX6_DL 0x4000a08c +#define CYDEV_CAN0_TX7_BASE 0x4000a090 +#define CYDEV_CAN0_TX7_SIZE 0x00000010 +#define CYREG_CAN0_TX7_CMD 0x4000a090 +#define CYREG_CAN0_TX7_ID 0x4000a094 +#define CYREG_CAN0_TX7_DH 0x4000a098 +#define CYREG_CAN0_TX7_DL 0x4000a09c +#define CYDEV_CAN0_RX0_BASE 0x4000a0a0 +#define CYDEV_CAN0_RX0_SIZE 0x00000020 +#define CYREG_CAN0_RX0_CMD 0x4000a0a0 +#define CYREG_CAN0_RX0_ID 0x4000a0a4 +#define CYREG_CAN0_RX0_DH 0x4000a0a8 +#define CYREG_CAN0_RX0_DL 0x4000a0ac +#define CYREG_CAN0_RX0_AMR 0x4000a0b0 +#define CYREG_CAN0_RX0_ACR 0x4000a0b4 +#define CYREG_CAN0_RX0_AMRD 0x4000a0b8 +#define CYREG_CAN0_RX0_ACRD 0x4000a0bc +#define CYDEV_CAN0_RX1_BASE 0x4000a0c0 +#define CYDEV_CAN0_RX1_SIZE 0x00000020 +#define CYREG_CAN0_RX1_CMD 0x4000a0c0 +#define CYREG_CAN0_RX1_ID 0x4000a0c4 +#define CYREG_CAN0_RX1_DH 0x4000a0c8 +#define CYREG_CAN0_RX1_DL 0x4000a0cc +#define CYREG_CAN0_RX1_AMR 0x4000a0d0 +#define CYREG_CAN0_RX1_ACR 0x4000a0d4 +#define CYREG_CAN0_RX1_AMRD 0x4000a0d8 +#define CYREG_CAN0_RX1_ACRD 0x4000a0dc +#define CYDEV_CAN0_RX2_BASE 0x4000a0e0 +#define CYDEV_CAN0_RX2_SIZE 0x00000020 +#define CYREG_CAN0_RX2_CMD 0x4000a0e0 +#define CYREG_CAN0_RX2_ID 0x4000a0e4 +#define CYREG_CAN0_RX2_DH 0x4000a0e8 +#define CYREG_CAN0_RX2_DL 0x4000a0ec +#define CYREG_CAN0_RX2_AMR 0x4000a0f0 +#define CYREG_CAN0_RX2_ACR 0x4000a0f4 +#define CYREG_CAN0_RX2_AMRD 0x4000a0f8 +#define CYREG_CAN0_RX2_ACRD 0x4000a0fc +#define CYDEV_CAN0_RX3_BASE 0x4000a100 +#define CYDEV_CAN0_RX3_SIZE 0x00000020 +#define CYREG_CAN0_RX3_CMD 0x4000a100 +#define CYREG_CAN0_RX3_ID 0x4000a104 +#define CYREG_CAN0_RX3_DH 0x4000a108 +#define CYREG_CAN0_RX3_DL 0x4000a10c +#define CYREG_CAN0_RX3_AMR 0x4000a110 +#define CYREG_CAN0_RX3_ACR 0x4000a114 +#define CYREG_CAN0_RX3_AMRD 0x4000a118 +#define CYREG_CAN0_RX3_ACRD 0x4000a11c +#define CYDEV_CAN0_RX4_BASE 0x4000a120 +#define CYDEV_CAN0_RX4_SIZE 0x00000020 +#define CYREG_CAN0_RX4_CMD 0x4000a120 +#define CYREG_CAN0_RX4_ID 0x4000a124 +#define CYREG_CAN0_RX4_DH 0x4000a128 +#define CYREG_CAN0_RX4_DL 0x4000a12c +#define CYREG_CAN0_RX4_AMR 0x4000a130 +#define CYREG_CAN0_RX4_ACR 0x4000a134 +#define CYREG_CAN0_RX4_AMRD 0x4000a138 +#define CYREG_CAN0_RX4_ACRD 0x4000a13c +#define CYDEV_CAN0_RX5_BASE 0x4000a140 +#define CYDEV_CAN0_RX5_SIZE 0x00000020 +#define CYREG_CAN0_RX5_CMD 0x4000a140 +#define CYREG_CAN0_RX5_ID 0x4000a144 +#define CYREG_CAN0_RX5_DH 0x4000a148 +#define CYREG_CAN0_RX5_DL 0x4000a14c +#define CYREG_CAN0_RX5_AMR 0x4000a150 +#define CYREG_CAN0_RX5_ACR 0x4000a154 +#define CYREG_CAN0_RX5_AMRD 0x4000a158 +#define CYREG_CAN0_RX5_ACRD 0x4000a15c +#define CYDEV_CAN0_RX6_BASE 0x4000a160 +#define CYDEV_CAN0_RX6_SIZE 0x00000020 +#define CYREG_CAN0_RX6_CMD 0x4000a160 +#define CYREG_CAN0_RX6_ID 0x4000a164 +#define CYREG_CAN0_RX6_DH 0x4000a168 +#define CYREG_CAN0_RX6_DL 0x4000a16c +#define CYREG_CAN0_RX6_AMR 0x4000a170 +#define CYREG_CAN0_RX6_ACR 0x4000a174 +#define CYREG_CAN0_RX6_AMRD 0x4000a178 +#define CYREG_CAN0_RX6_ACRD 0x4000a17c +#define CYDEV_CAN0_RX7_BASE 0x4000a180 +#define CYDEV_CAN0_RX7_SIZE 0x00000020 +#define CYREG_CAN0_RX7_CMD 0x4000a180 +#define CYREG_CAN0_RX7_ID 0x4000a184 +#define CYREG_CAN0_RX7_DH 0x4000a188 +#define CYREG_CAN0_RX7_DL 0x4000a18c +#define CYREG_CAN0_RX7_AMR 0x4000a190 +#define CYREG_CAN0_RX7_ACR 0x4000a194 +#define CYREG_CAN0_RX7_AMRD 0x4000a198 +#define CYREG_CAN0_RX7_ACRD 0x4000a19c +#define CYDEV_CAN0_RX8_BASE 0x4000a1a0 +#define CYDEV_CAN0_RX8_SIZE 0x00000020 +#define CYREG_CAN0_RX8_CMD 0x4000a1a0 +#define CYREG_CAN0_RX8_ID 0x4000a1a4 +#define CYREG_CAN0_RX8_DH 0x4000a1a8 +#define CYREG_CAN0_RX8_DL 0x4000a1ac +#define CYREG_CAN0_RX8_AMR 0x4000a1b0 +#define CYREG_CAN0_RX8_ACR 0x4000a1b4 +#define CYREG_CAN0_RX8_AMRD 0x4000a1b8 +#define CYREG_CAN0_RX8_ACRD 0x4000a1bc +#define CYDEV_CAN0_RX9_BASE 0x4000a1c0 +#define CYDEV_CAN0_RX9_SIZE 0x00000020 +#define CYREG_CAN0_RX9_CMD 0x4000a1c0 +#define CYREG_CAN0_RX9_ID 0x4000a1c4 +#define CYREG_CAN0_RX9_DH 0x4000a1c8 +#define CYREG_CAN0_RX9_DL 0x4000a1cc +#define CYREG_CAN0_RX9_AMR 0x4000a1d0 +#define CYREG_CAN0_RX9_ACR 0x4000a1d4 +#define CYREG_CAN0_RX9_AMRD 0x4000a1d8 +#define CYREG_CAN0_RX9_ACRD 0x4000a1dc +#define CYDEV_CAN0_RX10_BASE 0x4000a1e0 +#define CYDEV_CAN0_RX10_SIZE 0x00000020 +#define CYREG_CAN0_RX10_CMD 0x4000a1e0 +#define CYREG_CAN0_RX10_ID 0x4000a1e4 +#define CYREG_CAN0_RX10_DH 0x4000a1e8 +#define CYREG_CAN0_RX10_DL 0x4000a1ec +#define CYREG_CAN0_RX10_AMR 0x4000a1f0 +#define CYREG_CAN0_RX10_ACR 0x4000a1f4 +#define CYREG_CAN0_RX10_AMRD 0x4000a1f8 +#define CYREG_CAN0_RX10_ACRD 0x4000a1fc +#define CYDEV_CAN0_RX11_BASE 0x4000a200 +#define CYDEV_CAN0_RX11_SIZE 0x00000020 +#define CYREG_CAN0_RX11_CMD 0x4000a200 +#define CYREG_CAN0_RX11_ID 0x4000a204 +#define CYREG_CAN0_RX11_DH 0x4000a208 +#define CYREG_CAN0_RX11_DL 0x4000a20c +#define CYREG_CAN0_RX11_AMR 0x4000a210 +#define CYREG_CAN0_RX11_ACR 0x4000a214 +#define CYREG_CAN0_RX11_AMRD 0x4000a218 +#define CYREG_CAN0_RX11_ACRD 0x4000a21c +#define CYDEV_CAN0_RX12_BASE 0x4000a220 +#define CYDEV_CAN0_RX12_SIZE 0x00000020 +#define CYREG_CAN0_RX12_CMD 0x4000a220 +#define CYREG_CAN0_RX12_ID 0x4000a224 +#define CYREG_CAN0_RX12_DH 0x4000a228 +#define CYREG_CAN0_RX12_DL 0x4000a22c +#define CYREG_CAN0_RX12_AMR 0x4000a230 +#define CYREG_CAN0_RX12_ACR 0x4000a234 +#define CYREG_CAN0_RX12_AMRD 0x4000a238 +#define CYREG_CAN0_RX12_ACRD 0x4000a23c +#define CYDEV_CAN0_RX13_BASE 0x4000a240 +#define CYDEV_CAN0_RX13_SIZE 0x00000020 +#define CYREG_CAN0_RX13_CMD 0x4000a240 +#define CYREG_CAN0_RX13_ID 0x4000a244 +#define CYREG_CAN0_RX13_DH 0x4000a248 +#define CYREG_CAN0_RX13_DL 0x4000a24c +#define CYREG_CAN0_RX13_AMR 0x4000a250 +#define CYREG_CAN0_RX13_ACR 0x4000a254 +#define CYREG_CAN0_RX13_AMRD 0x4000a258 +#define CYREG_CAN0_RX13_ACRD 0x4000a25c +#define CYDEV_CAN0_RX14_BASE 0x4000a260 +#define CYDEV_CAN0_RX14_SIZE 0x00000020 +#define CYREG_CAN0_RX14_CMD 0x4000a260 +#define CYREG_CAN0_RX14_ID 0x4000a264 +#define CYREG_CAN0_RX14_DH 0x4000a268 +#define CYREG_CAN0_RX14_DL 0x4000a26c +#define CYREG_CAN0_RX14_AMR 0x4000a270 +#define CYREG_CAN0_RX14_ACR 0x4000a274 +#define CYREG_CAN0_RX14_AMRD 0x4000a278 +#define CYREG_CAN0_RX14_ACRD 0x4000a27c +#define CYDEV_CAN0_RX15_BASE 0x4000a280 +#define CYDEV_CAN0_RX15_SIZE 0x00000020 +#define CYREG_CAN0_RX15_CMD 0x4000a280 +#define CYREG_CAN0_RX15_ID 0x4000a284 +#define CYREG_CAN0_RX15_DH 0x4000a288 +#define CYREG_CAN0_RX15_DL 0x4000a28c +#define CYREG_CAN0_RX15_AMR 0x4000a290 +#define CYREG_CAN0_RX15_ACR 0x4000a294 +#define CYREG_CAN0_RX15_AMRD 0x4000a298 +#define CYREG_CAN0_RX15_ACRD 0x4000a29c +#define CYDEV_DFB0_BASE 0x4000c000 +#define CYDEV_DFB0_SIZE 0x000007b5 +#define CYDEV_DFB0_DPA_SRAM_BASE 0x4000c000 +#define CYDEV_DFB0_DPA_SRAM_SIZE 0x00000200 +#define CYREG_DFB0_DPA_SRAM_DATA_MBASE 0x4000c000 +#define CYREG_DFB0_DPA_SRAM_DATA_MSIZE 0x00000200 +#define CYDEV_DFB0_DPB_SRAM_BASE 0x4000c200 +#define CYDEV_DFB0_DPB_SRAM_SIZE 0x00000200 +#define CYREG_DFB0_DPB_SRAM_DATA_MBASE 0x4000c200 +#define CYREG_DFB0_DPB_SRAM_DATA_MSIZE 0x00000200 +#define CYDEV_DFB0_CSA_SRAM_BASE 0x4000c400 +#define CYDEV_DFB0_CSA_SRAM_SIZE 0x00000100 +#define CYREG_DFB0_CSA_SRAM_DATA_MBASE 0x4000c400 +#define CYREG_DFB0_CSA_SRAM_DATA_MSIZE 0x00000100 +#define CYDEV_DFB0_CSB_SRAM_BASE 0x4000c500 +#define CYDEV_DFB0_CSB_SRAM_SIZE 0x00000100 +#define CYREG_DFB0_CSB_SRAM_DATA_MBASE 0x4000c500 +#define CYREG_DFB0_CSB_SRAM_DATA_MSIZE 0x00000100 +#define CYDEV_DFB0_FSM_SRAM_BASE 0x4000c600 +#define CYDEV_DFB0_FSM_SRAM_SIZE 0x00000100 +#define CYREG_DFB0_FSM_SRAM_DATA_MBASE 0x4000c600 +#define CYREG_DFB0_FSM_SRAM_DATA_MSIZE 0x00000100 +#define CYDEV_DFB0_ACU_SRAM_BASE 0x4000c700 +#define CYDEV_DFB0_ACU_SRAM_SIZE 0x00000040 +#define CYREG_DFB0_ACU_SRAM_DATA_MBASE 0x4000c700 +#define CYREG_DFB0_ACU_SRAM_DATA_MSIZE 0x00000040 +#define CYREG_DFB0_CR 0x4000c780 +#define CYREG_DFB0_SR 0x4000c784 +#define CYREG_DFB0_RAM_EN 0x4000c788 +#define CYREG_DFB0_RAM_DIR 0x4000c78c +#define CYREG_DFB0_SEMA 0x4000c790 +#define CYREG_DFB0_DSI_CTRL 0x4000c794 +#define CYREG_DFB0_INT_CTRL 0x4000c798 +#define CYREG_DFB0_DMA_CTRL 0x4000c79c +#define CYREG_DFB0_STAGEA 0x4000c7a0 +#define CYREG_DFB0_STAGEAM 0x4000c7a1 +#define CYREG_DFB0_STAGEAH 0x4000c7a2 +#define CYREG_DFB0_STAGEB 0x4000c7a4 +#define CYREG_DFB0_STAGEBM 0x4000c7a5 +#define CYREG_DFB0_STAGEBH 0x4000c7a6 +#define CYREG_DFB0_HOLDA 0x4000c7a8 +#define CYREG_DFB0_HOLDAM 0x4000c7a9 +#define CYREG_DFB0_HOLDAH 0x4000c7aa +#define CYREG_DFB0_HOLDAS 0x4000c7ab +#define CYREG_DFB0_HOLDB 0x4000c7ac +#define CYREG_DFB0_HOLDBM 0x4000c7ad +#define CYREG_DFB0_HOLDBH 0x4000c7ae +#define CYREG_DFB0_HOLDBS 0x4000c7af +#define CYREG_DFB0_COHER 0x4000c7b0 +#define CYREG_DFB0_DALIGN 0x4000c7b4 +#define CYDEV_UCFG_BASE 0x40010000 +#define CYDEV_UCFG_SIZE 0x00005040 +#define CYDEV_UCFG_B0_BASE 0x40010000 +#define CYDEV_UCFG_B0_SIZE 0x00000fef +#define CYDEV_UCFG_B0_P0_BASE 0x40010000 +#define CYDEV_UCFG_B0_P0_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P0_U0_BASE 0x40010000 +#define CYDEV_UCFG_B0_P0_U0_SIZE 0x00000070 +#define CYREG_B0_P0_U0_PLD_IT0 0x40010000 +#define CYREG_B0_P0_U0_PLD_IT1 0x40010004 +#define CYREG_B0_P0_U0_PLD_IT2 0x40010008 +#define CYREG_B0_P0_U0_PLD_IT3 0x4001000c +#define CYREG_B0_P0_U0_PLD_IT4 0x40010010 +#define CYREG_B0_P0_U0_PLD_IT5 0x40010014 +#define CYREG_B0_P0_U0_PLD_IT6 0x40010018 +#define CYREG_B0_P0_U0_PLD_IT7 0x4001001c +#define CYREG_B0_P0_U0_PLD_IT8 0x40010020 +#define CYREG_B0_P0_U0_PLD_IT9 0x40010024 +#define CYREG_B0_P0_U0_PLD_IT10 0x40010028 +#define CYREG_B0_P0_U0_PLD_IT11 0x4001002c +#define CYREG_B0_P0_U0_PLD_ORT0 0x40010030 +#define CYREG_B0_P0_U0_PLD_ORT1 0x40010032 +#define CYREG_B0_P0_U0_PLD_ORT2 0x40010034 +#define CYREG_B0_P0_U0_PLD_ORT3 0x40010036 +#define CYREG_B0_P0_U0_MC_CFG_CEN_CONST 0x40010038 +#define CYREG_B0_P0_U0_MC_CFG_XORFB 0x4001003a +#define CYREG_B0_P0_U0_MC_CFG_SET_RESET 0x4001003c +#define CYREG_B0_P0_U0_MC_CFG_BYPASS 0x4001003e +#define CYREG_B0_P0_U0_CFG0 0x40010040 +#define CYREG_B0_P0_U0_CFG1 0x40010041 +#define CYREG_B0_P0_U0_CFG2 0x40010042 +#define CYREG_B0_P0_U0_CFG3 0x40010043 +#define CYREG_B0_P0_U0_CFG4 0x40010044 +#define CYREG_B0_P0_U0_CFG5 0x40010045 +#define CYREG_B0_P0_U0_CFG6 0x40010046 +#define CYREG_B0_P0_U0_CFG7 0x40010047 +#define CYREG_B0_P0_U0_CFG8 0x40010048 +#define CYREG_B0_P0_U0_CFG9 0x40010049 +#define CYREG_B0_P0_U0_CFG10 0x4001004a +#define CYREG_B0_P0_U0_CFG11 0x4001004b +#define CYREG_B0_P0_U0_CFG12 0x4001004c +#define CYREG_B0_P0_U0_CFG13 0x4001004d +#define CYREG_B0_P0_U0_CFG14 0x4001004e +#define CYREG_B0_P0_U0_CFG15 0x4001004f +#define CYREG_B0_P0_U0_CFG16 0x40010050 +#define CYREG_B0_P0_U0_CFG17 0x40010051 +#define CYREG_B0_P0_U0_CFG18 0x40010052 +#define CYREG_B0_P0_U0_CFG19 0x40010053 +#define CYREG_B0_P0_U0_CFG20 0x40010054 +#define CYREG_B0_P0_U0_CFG21 0x40010055 +#define CYREG_B0_P0_U0_CFG22 0x40010056 +#define CYREG_B0_P0_U0_CFG23 0x40010057 +#define CYREG_B0_P0_U0_CFG24 0x40010058 +#define CYREG_B0_P0_U0_CFG25 0x40010059 +#define CYREG_B0_P0_U0_CFG26 0x4001005a +#define CYREG_B0_P0_U0_CFG27 0x4001005b +#define CYREG_B0_P0_U0_CFG28 0x4001005c +#define CYREG_B0_P0_U0_CFG29 0x4001005d +#define CYREG_B0_P0_U0_CFG30 0x4001005e +#define CYREG_B0_P0_U0_CFG31 0x4001005f +#define CYREG_B0_P0_U0_DCFG0 0x40010060 +#define CYREG_B0_P0_U0_DCFG1 0x40010062 +#define CYREG_B0_P0_U0_DCFG2 0x40010064 +#define CYREG_B0_P0_U0_DCFG3 0x40010066 +#define CYREG_B0_P0_U0_DCFG4 0x40010068 +#define CYREG_B0_P0_U0_DCFG5 0x4001006a +#define CYREG_B0_P0_U0_DCFG6 0x4001006c +#define CYREG_B0_P0_U0_DCFG7 0x4001006e +#define CYDEV_UCFG_B0_P0_U1_BASE 0x40010080 +#define CYDEV_UCFG_B0_P0_U1_SIZE 0x00000070 +#define CYREG_B0_P0_U1_PLD_IT0 0x40010080 +#define CYREG_B0_P0_U1_PLD_IT1 0x40010084 +#define CYREG_B0_P0_U1_PLD_IT2 0x40010088 +#define CYREG_B0_P0_U1_PLD_IT3 0x4001008c +#define CYREG_B0_P0_U1_PLD_IT4 0x40010090 +#define CYREG_B0_P0_U1_PLD_IT5 0x40010094 +#define CYREG_B0_P0_U1_PLD_IT6 0x40010098 +#define CYREG_B0_P0_U1_PLD_IT7 0x4001009c +#define CYREG_B0_P0_U1_PLD_IT8 0x400100a0 +#define CYREG_B0_P0_U1_PLD_IT9 0x400100a4 +#define CYREG_B0_P0_U1_PLD_IT10 0x400100a8 +#define CYREG_B0_P0_U1_PLD_IT11 0x400100ac +#define CYREG_B0_P0_U1_PLD_ORT0 0x400100b0 +#define CYREG_B0_P0_U1_PLD_ORT1 0x400100b2 +#define CYREG_B0_P0_U1_PLD_ORT2 0x400100b4 +#define CYREG_B0_P0_U1_PLD_ORT3 0x400100b6 +#define CYREG_B0_P0_U1_MC_CFG_CEN_CONST 0x400100b8 +#define CYREG_B0_P0_U1_MC_CFG_XORFB 0x400100ba +#define CYREG_B0_P0_U1_MC_CFG_SET_RESET 0x400100bc +#define CYREG_B0_P0_U1_MC_CFG_BYPASS 0x400100be +#define CYREG_B0_P0_U1_CFG0 0x400100c0 +#define CYREG_B0_P0_U1_CFG1 0x400100c1 +#define CYREG_B0_P0_U1_CFG2 0x400100c2 +#define CYREG_B0_P0_U1_CFG3 0x400100c3 +#define CYREG_B0_P0_U1_CFG4 0x400100c4 +#define CYREG_B0_P0_U1_CFG5 0x400100c5 +#define CYREG_B0_P0_U1_CFG6 0x400100c6 +#define CYREG_B0_P0_U1_CFG7 0x400100c7 +#define CYREG_B0_P0_U1_CFG8 0x400100c8 +#define CYREG_B0_P0_U1_CFG9 0x400100c9 +#define CYREG_B0_P0_U1_CFG10 0x400100ca +#define CYREG_B0_P0_U1_CFG11 0x400100cb +#define CYREG_B0_P0_U1_CFG12 0x400100cc +#define CYREG_B0_P0_U1_CFG13 0x400100cd +#define CYREG_B0_P0_U1_CFG14 0x400100ce +#define CYREG_B0_P0_U1_CFG15 0x400100cf +#define CYREG_B0_P0_U1_CFG16 0x400100d0 +#define CYREG_B0_P0_U1_CFG17 0x400100d1 +#define CYREG_B0_P0_U1_CFG18 0x400100d2 +#define CYREG_B0_P0_U1_CFG19 0x400100d3 +#define CYREG_B0_P0_U1_CFG20 0x400100d4 +#define CYREG_B0_P0_U1_CFG21 0x400100d5 +#define CYREG_B0_P0_U1_CFG22 0x400100d6 +#define CYREG_B0_P0_U1_CFG23 0x400100d7 +#define CYREG_B0_P0_U1_CFG24 0x400100d8 +#define CYREG_B0_P0_U1_CFG25 0x400100d9 +#define CYREG_B0_P0_U1_CFG26 0x400100da +#define CYREG_B0_P0_U1_CFG27 0x400100db +#define CYREG_B0_P0_U1_CFG28 0x400100dc +#define CYREG_B0_P0_U1_CFG29 0x400100dd +#define CYREG_B0_P0_U1_CFG30 0x400100de +#define CYREG_B0_P0_U1_CFG31 0x400100df +#define CYREG_B0_P0_U1_DCFG0 0x400100e0 +#define CYREG_B0_P0_U1_DCFG1 0x400100e2 +#define CYREG_B0_P0_U1_DCFG2 0x400100e4 +#define CYREG_B0_P0_U1_DCFG3 0x400100e6 +#define CYREG_B0_P0_U1_DCFG4 0x400100e8 +#define CYREG_B0_P0_U1_DCFG5 0x400100ea +#define CYREG_B0_P0_U1_DCFG6 0x400100ec +#define CYREG_B0_P0_U1_DCFG7 0x400100ee +#define CYDEV_UCFG_B0_P0_ROUTE_BASE 0x40010100 +#define CYDEV_UCFG_B0_P0_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P1_BASE 0x40010200 +#define CYDEV_UCFG_B0_P1_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P1_U0_BASE 0x40010200 +#define CYDEV_UCFG_B0_P1_U0_SIZE 0x00000070 +#define CYREG_B0_P1_U0_PLD_IT0 0x40010200 +#define CYREG_B0_P1_U0_PLD_IT1 0x40010204 +#define CYREG_B0_P1_U0_PLD_IT2 0x40010208 +#define CYREG_B0_P1_U0_PLD_IT3 0x4001020c +#define CYREG_B0_P1_U0_PLD_IT4 0x40010210 +#define CYREG_B0_P1_U0_PLD_IT5 0x40010214 +#define CYREG_B0_P1_U0_PLD_IT6 0x40010218 +#define CYREG_B0_P1_U0_PLD_IT7 0x4001021c +#define CYREG_B0_P1_U0_PLD_IT8 0x40010220 +#define CYREG_B0_P1_U0_PLD_IT9 0x40010224 +#define CYREG_B0_P1_U0_PLD_IT10 0x40010228 +#define CYREG_B0_P1_U0_PLD_IT11 0x4001022c +#define CYREG_B0_P1_U0_PLD_ORT0 0x40010230 +#define CYREG_B0_P1_U0_PLD_ORT1 0x40010232 +#define CYREG_B0_P1_U0_PLD_ORT2 0x40010234 +#define CYREG_B0_P1_U0_PLD_ORT3 0x40010236 +#define CYREG_B0_P1_U0_MC_CFG_CEN_CONST 0x40010238 +#define CYREG_B0_P1_U0_MC_CFG_XORFB 0x4001023a +#define CYREG_B0_P1_U0_MC_CFG_SET_RESET 0x4001023c +#define CYREG_B0_P1_U0_MC_CFG_BYPASS 0x4001023e +#define CYREG_B0_P1_U0_CFG0 0x40010240 +#define CYREG_B0_P1_U0_CFG1 0x40010241 +#define CYREG_B0_P1_U0_CFG2 0x40010242 +#define CYREG_B0_P1_U0_CFG3 0x40010243 +#define CYREG_B0_P1_U0_CFG4 0x40010244 +#define CYREG_B0_P1_U0_CFG5 0x40010245 +#define CYREG_B0_P1_U0_CFG6 0x40010246 +#define CYREG_B0_P1_U0_CFG7 0x40010247 +#define CYREG_B0_P1_U0_CFG8 0x40010248 +#define CYREG_B0_P1_U0_CFG9 0x40010249 +#define CYREG_B0_P1_U0_CFG10 0x4001024a +#define CYREG_B0_P1_U0_CFG11 0x4001024b +#define CYREG_B0_P1_U0_CFG12 0x4001024c +#define CYREG_B0_P1_U0_CFG13 0x4001024d +#define CYREG_B0_P1_U0_CFG14 0x4001024e +#define CYREG_B0_P1_U0_CFG15 0x4001024f +#define CYREG_B0_P1_U0_CFG16 0x40010250 +#define CYREG_B0_P1_U0_CFG17 0x40010251 +#define CYREG_B0_P1_U0_CFG18 0x40010252 +#define CYREG_B0_P1_U0_CFG19 0x40010253 +#define CYREG_B0_P1_U0_CFG20 0x40010254 +#define CYREG_B0_P1_U0_CFG21 0x40010255 +#define CYREG_B0_P1_U0_CFG22 0x40010256 +#define CYREG_B0_P1_U0_CFG23 0x40010257 +#define CYREG_B0_P1_U0_CFG24 0x40010258 +#define CYREG_B0_P1_U0_CFG25 0x40010259 +#define CYREG_B0_P1_U0_CFG26 0x4001025a +#define CYREG_B0_P1_U0_CFG27 0x4001025b +#define CYREG_B0_P1_U0_CFG28 0x4001025c +#define CYREG_B0_P1_U0_CFG29 0x4001025d +#define CYREG_B0_P1_U0_CFG30 0x4001025e +#define CYREG_B0_P1_U0_CFG31 0x4001025f +#define CYREG_B0_P1_U0_DCFG0 0x40010260 +#define CYREG_B0_P1_U0_DCFG1 0x40010262 +#define CYREG_B0_P1_U0_DCFG2 0x40010264 +#define CYREG_B0_P1_U0_DCFG3 0x40010266 +#define CYREG_B0_P1_U0_DCFG4 0x40010268 +#define CYREG_B0_P1_U0_DCFG5 0x4001026a +#define CYREG_B0_P1_U0_DCFG6 0x4001026c +#define CYREG_B0_P1_U0_DCFG7 0x4001026e +#define CYDEV_UCFG_B0_P1_U1_BASE 0x40010280 +#define CYDEV_UCFG_B0_P1_U1_SIZE 0x00000070 +#define CYREG_B0_P1_U1_PLD_IT0 0x40010280 +#define CYREG_B0_P1_U1_PLD_IT1 0x40010284 +#define CYREG_B0_P1_U1_PLD_IT2 0x40010288 +#define CYREG_B0_P1_U1_PLD_IT3 0x4001028c +#define CYREG_B0_P1_U1_PLD_IT4 0x40010290 +#define CYREG_B0_P1_U1_PLD_IT5 0x40010294 +#define CYREG_B0_P1_U1_PLD_IT6 0x40010298 +#define CYREG_B0_P1_U1_PLD_IT7 0x4001029c +#define CYREG_B0_P1_U1_PLD_IT8 0x400102a0 +#define CYREG_B0_P1_U1_PLD_IT9 0x400102a4 +#define CYREG_B0_P1_U1_PLD_IT10 0x400102a8 +#define CYREG_B0_P1_U1_PLD_IT11 0x400102ac +#define CYREG_B0_P1_U1_PLD_ORT0 0x400102b0 +#define CYREG_B0_P1_U1_PLD_ORT1 0x400102b2 +#define CYREG_B0_P1_U1_PLD_ORT2 0x400102b4 +#define CYREG_B0_P1_U1_PLD_ORT3 0x400102b6 +#define CYREG_B0_P1_U1_MC_CFG_CEN_CONST 0x400102b8 +#define CYREG_B0_P1_U1_MC_CFG_XORFB 0x400102ba +#define CYREG_B0_P1_U1_MC_CFG_SET_RESET 0x400102bc +#define CYREG_B0_P1_U1_MC_CFG_BYPASS 0x400102be +#define CYREG_B0_P1_U1_CFG0 0x400102c0 +#define CYREG_B0_P1_U1_CFG1 0x400102c1 +#define CYREG_B0_P1_U1_CFG2 0x400102c2 +#define CYREG_B0_P1_U1_CFG3 0x400102c3 +#define CYREG_B0_P1_U1_CFG4 0x400102c4 +#define CYREG_B0_P1_U1_CFG5 0x400102c5 +#define CYREG_B0_P1_U1_CFG6 0x400102c6 +#define CYREG_B0_P1_U1_CFG7 0x400102c7 +#define CYREG_B0_P1_U1_CFG8 0x400102c8 +#define CYREG_B0_P1_U1_CFG9 0x400102c9 +#define CYREG_B0_P1_U1_CFG10 0x400102ca +#define CYREG_B0_P1_U1_CFG11 0x400102cb +#define CYREG_B0_P1_U1_CFG12 0x400102cc +#define CYREG_B0_P1_U1_CFG13 0x400102cd +#define CYREG_B0_P1_U1_CFG14 0x400102ce +#define CYREG_B0_P1_U1_CFG15 0x400102cf +#define CYREG_B0_P1_U1_CFG16 0x400102d0 +#define CYREG_B0_P1_U1_CFG17 0x400102d1 +#define CYREG_B0_P1_U1_CFG18 0x400102d2 +#define CYREG_B0_P1_U1_CFG19 0x400102d3 +#define CYREG_B0_P1_U1_CFG20 0x400102d4 +#define CYREG_B0_P1_U1_CFG21 0x400102d5 +#define CYREG_B0_P1_U1_CFG22 0x400102d6 +#define CYREG_B0_P1_U1_CFG23 0x400102d7 +#define CYREG_B0_P1_U1_CFG24 0x400102d8 +#define CYREG_B0_P1_U1_CFG25 0x400102d9 +#define CYREG_B0_P1_U1_CFG26 0x400102da +#define CYREG_B0_P1_U1_CFG27 0x400102db +#define CYREG_B0_P1_U1_CFG28 0x400102dc +#define CYREG_B0_P1_U1_CFG29 0x400102dd +#define CYREG_B0_P1_U1_CFG30 0x400102de +#define CYREG_B0_P1_U1_CFG31 0x400102df +#define CYREG_B0_P1_U1_DCFG0 0x400102e0 +#define CYREG_B0_P1_U1_DCFG1 0x400102e2 +#define CYREG_B0_P1_U1_DCFG2 0x400102e4 +#define CYREG_B0_P1_U1_DCFG3 0x400102e6 +#define CYREG_B0_P1_U1_DCFG4 0x400102e8 +#define CYREG_B0_P1_U1_DCFG5 0x400102ea +#define CYREG_B0_P1_U1_DCFG6 0x400102ec +#define CYREG_B0_P1_U1_DCFG7 0x400102ee +#define CYDEV_UCFG_B0_P1_ROUTE_BASE 0x40010300 +#define CYDEV_UCFG_B0_P1_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P2_BASE 0x40010400 +#define CYDEV_UCFG_B0_P2_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P2_U0_BASE 0x40010400 +#define CYDEV_UCFG_B0_P2_U0_SIZE 0x00000070 +#define CYREG_B0_P2_U0_PLD_IT0 0x40010400 +#define CYREG_B0_P2_U0_PLD_IT1 0x40010404 +#define CYREG_B0_P2_U0_PLD_IT2 0x40010408 +#define CYREG_B0_P2_U0_PLD_IT3 0x4001040c +#define CYREG_B0_P2_U0_PLD_IT4 0x40010410 +#define CYREG_B0_P2_U0_PLD_IT5 0x40010414 +#define CYREG_B0_P2_U0_PLD_IT6 0x40010418 +#define CYREG_B0_P2_U0_PLD_IT7 0x4001041c +#define CYREG_B0_P2_U0_PLD_IT8 0x40010420 +#define CYREG_B0_P2_U0_PLD_IT9 0x40010424 +#define CYREG_B0_P2_U0_PLD_IT10 0x40010428 +#define CYREG_B0_P2_U0_PLD_IT11 0x4001042c +#define CYREG_B0_P2_U0_PLD_ORT0 0x40010430 +#define CYREG_B0_P2_U0_PLD_ORT1 0x40010432 +#define CYREG_B0_P2_U0_PLD_ORT2 0x40010434 +#define CYREG_B0_P2_U0_PLD_ORT3 0x40010436 +#define CYREG_B0_P2_U0_MC_CFG_CEN_CONST 0x40010438 +#define CYREG_B0_P2_U0_MC_CFG_XORFB 0x4001043a +#define CYREG_B0_P2_U0_MC_CFG_SET_RESET 0x4001043c +#define CYREG_B0_P2_U0_MC_CFG_BYPASS 0x4001043e +#define CYREG_B0_P2_U0_CFG0 0x40010440 +#define CYREG_B0_P2_U0_CFG1 0x40010441 +#define CYREG_B0_P2_U0_CFG2 0x40010442 +#define CYREG_B0_P2_U0_CFG3 0x40010443 +#define CYREG_B0_P2_U0_CFG4 0x40010444 +#define CYREG_B0_P2_U0_CFG5 0x40010445 +#define CYREG_B0_P2_U0_CFG6 0x40010446 +#define CYREG_B0_P2_U0_CFG7 0x40010447 +#define CYREG_B0_P2_U0_CFG8 0x40010448 +#define CYREG_B0_P2_U0_CFG9 0x40010449 +#define CYREG_B0_P2_U0_CFG10 0x4001044a +#define CYREG_B0_P2_U0_CFG11 0x4001044b +#define CYREG_B0_P2_U0_CFG12 0x4001044c +#define CYREG_B0_P2_U0_CFG13 0x4001044d +#define CYREG_B0_P2_U0_CFG14 0x4001044e +#define CYREG_B0_P2_U0_CFG15 0x4001044f +#define CYREG_B0_P2_U0_CFG16 0x40010450 +#define CYREG_B0_P2_U0_CFG17 0x40010451 +#define CYREG_B0_P2_U0_CFG18 0x40010452 +#define CYREG_B0_P2_U0_CFG19 0x40010453 +#define CYREG_B0_P2_U0_CFG20 0x40010454 +#define CYREG_B0_P2_U0_CFG21 0x40010455 +#define CYREG_B0_P2_U0_CFG22 0x40010456 +#define CYREG_B0_P2_U0_CFG23 0x40010457 +#define CYREG_B0_P2_U0_CFG24 0x40010458 +#define CYREG_B0_P2_U0_CFG25 0x40010459 +#define CYREG_B0_P2_U0_CFG26 0x4001045a +#define CYREG_B0_P2_U0_CFG27 0x4001045b +#define CYREG_B0_P2_U0_CFG28 0x4001045c +#define CYREG_B0_P2_U0_CFG29 0x4001045d +#define CYREG_B0_P2_U0_CFG30 0x4001045e +#define CYREG_B0_P2_U0_CFG31 0x4001045f +#define CYREG_B0_P2_U0_DCFG0 0x40010460 +#define CYREG_B0_P2_U0_DCFG1 0x40010462 +#define CYREG_B0_P2_U0_DCFG2 0x40010464 +#define CYREG_B0_P2_U0_DCFG3 0x40010466 +#define CYREG_B0_P2_U0_DCFG4 0x40010468 +#define CYREG_B0_P2_U0_DCFG5 0x4001046a +#define CYREG_B0_P2_U0_DCFG6 0x4001046c +#define CYREG_B0_P2_U0_DCFG7 0x4001046e +#define CYDEV_UCFG_B0_P2_U1_BASE 0x40010480 +#define CYDEV_UCFG_B0_P2_U1_SIZE 0x00000070 +#define CYREG_B0_P2_U1_PLD_IT0 0x40010480 +#define CYREG_B0_P2_U1_PLD_IT1 0x40010484 +#define CYREG_B0_P2_U1_PLD_IT2 0x40010488 +#define CYREG_B0_P2_U1_PLD_IT3 0x4001048c +#define CYREG_B0_P2_U1_PLD_IT4 0x40010490 +#define CYREG_B0_P2_U1_PLD_IT5 0x40010494 +#define CYREG_B0_P2_U1_PLD_IT6 0x40010498 +#define CYREG_B0_P2_U1_PLD_IT7 0x4001049c +#define CYREG_B0_P2_U1_PLD_IT8 0x400104a0 +#define CYREG_B0_P2_U1_PLD_IT9 0x400104a4 +#define CYREG_B0_P2_U1_PLD_IT10 0x400104a8 +#define CYREG_B0_P2_U1_PLD_IT11 0x400104ac +#define CYREG_B0_P2_U1_PLD_ORT0 0x400104b0 +#define CYREG_B0_P2_U1_PLD_ORT1 0x400104b2 +#define CYREG_B0_P2_U1_PLD_ORT2 0x400104b4 +#define CYREG_B0_P2_U1_PLD_ORT3 0x400104b6 +#define CYREG_B0_P2_U1_MC_CFG_CEN_CONST 0x400104b8 +#define CYREG_B0_P2_U1_MC_CFG_XORFB 0x400104ba +#define CYREG_B0_P2_U1_MC_CFG_SET_RESET 0x400104bc +#define CYREG_B0_P2_U1_MC_CFG_BYPASS 0x400104be +#define CYREG_B0_P2_U1_CFG0 0x400104c0 +#define CYREG_B0_P2_U1_CFG1 0x400104c1 +#define CYREG_B0_P2_U1_CFG2 0x400104c2 +#define CYREG_B0_P2_U1_CFG3 0x400104c3 +#define CYREG_B0_P2_U1_CFG4 0x400104c4 +#define CYREG_B0_P2_U1_CFG5 0x400104c5 +#define CYREG_B0_P2_U1_CFG6 0x400104c6 +#define CYREG_B0_P2_U1_CFG7 0x400104c7 +#define CYREG_B0_P2_U1_CFG8 0x400104c8 +#define CYREG_B0_P2_U1_CFG9 0x400104c9 +#define CYREG_B0_P2_U1_CFG10 0x400104ca +#define CYREG_B0_P2_U1_CFG11 0x400104cb +#define CYREG_B0_P2_U1_CFG12 0x400104cc +#define CYREG_B0_P2_U1_CFG13 0x400104cd +#define CYREG_B0_P2_U1_CFG14 0x400104ce +#define CYREG_B0_P2_U1_CFG15 0x400104cf +#define CYREG_B0_P2_U1_CFG16 0x400104d0 +#define CYREG_B0_P2_U1_CFG17 0x400104d1 +#define CYREG_B0_P2_U1_CFG18 0x400104d2 +#define CYREG_B0_P2_U1_CFG19 0x400104d3 +#define CYREG_B0_P2_U1_CFG20 0x400104d4 +#define CYREG_B0_P2_U1_CFG21 0x400104d5 +#define CYREG_B0_P2_U1_CFG22 0x400104d6 +#define CYREG_B0_P2_U1_CFG23 0x400104d7 +#define CYREG_B0_P2_U1_CFG24 0x400104d8 +#define CYREG_B0_P2_U1_CFG25 0x400104d9 +#define CYREG_B0_P2_U1_CFG26 0x400104da +#define CYREG_B0_P2_U1_CFG27 0x400104db +#define CYREG_B0_P2_U1_CFG28 0x400104dc +#define CYREG_B0_P2_U1_CFG29 0x400104dd +#define CYREG_B0_P2_U1_CFG30 0x400104de +#define CYREG_B0_P2_U1_CFG31 0x400104df +#define CYREG_B0_P2_U1_DCFG0 0x400104e0 +#define CYREG_B0_P2_U1_DCFG1 0x400104e2 +#define CYREG_B0_P2_U1_DCFG2 0x400104e4 +#define CYREG_B0_P2_U1_DCFG3 0x400104e6 +#define CYREG_B0_P2_U1_DCFG4 0x400104e8 +#define CYREG_B0_P2_U1_DCFG5 0x400104ea +#define CYREG_B0_P2_U1_DCFG6 0x400104ec +#define CYREG_B0_P2_U1_DCFG7 0x400104ee +#define CYDEV_UCFG_B0_P2_ROUTE_BASE 0x40010500 +#define CYDEV_UCFG_B0_P2_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P3_BASE 0x40010600 +#define CYDEV_UCFG_B0_P3_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P3_U0_BASE 0x40010600 +#define CYDEV_UCFG_B0_P3_U0_SIZE 0x00000070 +#define CYREG_B0_P3_U0_PLD_IT0 0x40010600 +#define CYREG_B0_P3_U0_PLD_IT1 0x40010604 +#define CYREG_B0_P3_U0_PLD_IT2 0x40010608 +#define CYREG_B0_P3_U0_PLD_IT3 0x4001060c +#define CYREG_B0_P3_U0_PLD_IT4 0x40010610 +#define CYREG_B0_P3_U0_PLD_IT5 0x40010614 +#define CYREG_B0_P3_U0_PLD_IT6 0x40010618 +#define CYREG_B0_P3_U0_PLD_IT7 0x4001061c +#define CYREG_B0_P3_U0_PLD_IT8 0x40010620 +#define CYREG_B0_P3_U0_PLD_IT9 0x40010624 +#define CYREG_B0_P3_U0_PLD_IT10 0x40010628 +#define CYREG_B0_P3_U0_PLD_IT11 0x4001062c +#define CYREG_B0_P3_U0_PLD_ORT0 0x40010630 +#define CYREG_B0_P3_U0_PLD_ORT1 0x40010632 +#define CYREG_B0_P3_U0_PLD_ORT2 0x40010634 +#define CYREG_B0_P3_U0_PLD_ORT3 0x40010636 +#define CYREG_B0_P3_U0_MC_CFG_CEN_CONST 0x40010638 +#define CYREG_B0_P3_U0_MC_CFG_XORFB 0x4001063a +#define CYREG_B0_P3_U0_MC_CFG_SET_RESET 0x4001063c +#define CYREG_B0_P3_U0_MC_CFG_BYPASS 0x4001063e +#define CYREG_B0_P3_U0_CFG0 0x40010640 +#define CYREG_B0_P3_U0_CFG1 0x40010641 +#define CYREG_B0_P3_U0_CFG2 0x40010642 +#define CYREG_B0_P3_U0_CFG3 0x40010643 +#define CYREG_B0_P3_U0_CFG4 0x40010644 +#define CYREG_B0_P3_U0_CFG5 0x40010645 +#define CYREG_B0_P3_U0_CFG6 0x40010646 +#define CYREG_B0_P3_U0_CFG7 0x40010647 +#define CYREG_B0_P3_U0_CFG8 0x40010648 +#define CYREG_B0_P3_U0_CFG9 0x40010649 +#define CYREG_B0_P3_U0_CFG10 0x4001064a +#define CYREG_B0_P3_U0_CFG11 0x4001064b +#define CYREG_B0_P3_U0_CFG12 0x4001064c +#define CYREG_B0_P3_U0_CFG13 0x4001064d +#define CYREG_B0_P3_U0_CFG14 0x4001064e +#define CYREG_B0_P3_U0_CFG15 0x4001064f +#define CYREG_B0_P3_U0_CFG16 0x40010650 +#define CYREG_B0_P3_U0_CFG17 0x40010651 +#define CYREG_B0_P3_U0_CFG18 0x40010652 +#define CYREG_B0_P3_U0_CFG19 0x40010653 +#define CYREG_B0_P3_U0_CFG20 0x40010654 +#define CYREG_B0_P3_U0_CFG21 0x40010655 +#define CYREG_B0_P3_U0_CFG22 0x40010656 +#define CYREG_B0_P3_U0_CFG23 0x40010657 +#define CYREG_B0_P3_U0_CFG24 0x40010658 +#define CYREG_B0_P3_U0_CFG25 0x40010659 +#define CYREG_B0_P3_U0_CFG26 0x4001065a +#define CYREG_B0_P3_U0_CFG27 0x4001065b +#define CYREG_B0_P3_U0_CFG28 0x4001065c +#define CYREG_B0_P3_U0_CFG29 0x4001065d +#define CYREG_B0_P3_U0_CFG30 0x4001065e +#define CYREG_B0_P3_U0_CFG31 0x4001065f +#define CYREG_B0_P3_U0_DCFG0 0x40010660 +#define CYREG_B0_P3_U0_DCFG1 0x40010662 +#define CYREG_B0_P3_U0_DCFG2 0x40010664 +#define CYREG_B0_P3_U0_DCFG3 0x40010666 +#define CYREG_B0_P3_U0_DCFG4 0x40010668 +#define CYREG_B0_P3_U0_DCFG5 0x4001066a +#define CYREG_B0_P3_U0_DCFG6 0x4001066c +#define CYREG_B0_P3_U0_DCFG7 0x4001066e +#define CYDEV_UCFG_B0_P3_U1_BASE 0x40010680 +#define CYDEV_UCFG_B0_P3_U1_SIZE 0x00000070 +#define CYREG_B0_P3_U1_PLD_IT0 0x40010680 +#define CYREG_B0_P3_U1_PLD_IT1 0x40010684 +#define CYREG_B0_P3_U1_PLD_IT2 0x40010688 +#define CYREG_B0_P3_U1_PLD_IT3 0x4001068c +#define CYREG_B0_P3_U1_PLD_IT4 0x40010690 +#define CYREG_B0_P3_U1_PLD_IT5 0x40010694 +#define CYREG_B0_P3_U1_PLD_IT6 0x40010698 +#define CYREG_B0_P3_U1_PLD_IT7 0x4001069c +#define CYREG_B0_P3_U1_PLD_IT8 0x400106a0 +#define CYREG_B0_P3_U1_PLD_IT9 0x400106a4 +#define CYREG_B0_P3_U1_PLD_IT10 0x400106a8 +#define CYREG_B0_P3_U1_PLD_IT11 0x400106ac +#define CYREG_B0_P3_U1_PLD_ORT0 0x400106b0 +#define CYREG_B0_P3_U1_PLD_ORT1 0x400106b2 +#define CYREG_B0_P3_U1_PLD_ORT2 0x400106b4 +#define CYREG_B0_P3_U1_PLD_ORT3 0x400106b6 +#define CYREG_B0_P3_U1_MC_CFG_CEN_CONST 0x400106b8 +#define CYREG_B0_P3_U1_MC_CFG_XORFB 0x400106ba +#define CYREG_B0_P3_U1_MC_CFG_SET_RESET 0x400106bc +#define CYREG_B0_P3_U1_MC_CFG_BYPASS 0x400106be +#define CYREG_B0_P3_U1_CFG0 0x400106c0 +#define CYREG_B0_P3_U1_CFG1 0x400106c1 +#define CYREG_B0_P3_U1_CFG2 0x400106c2 +#define CYREG_B0_P3_U1_CFG3 0x400106c3 +#define CYREG_B0_P3_U1_CFG4 0x400106c4 +#define CYREG_B0_P3_U1_CFG5 0x400106c5 +#define CYREG_B0_P3_U1_CFG6 0x400106c6 +#define CYREG_B0_P3_U1_CFG7 0x400106c7 +#define CYREG_B0_P3_U1_CFG8 0x400106c8 +#define CYREG_B0_P3_U1_CFG9 0x400106c9 +#define CYREG_B0_P3_U1_CFG10 0x400106ca +#define CYREG_B0_P3_U1_CFG11 0x400106cb +#define CYREG_B0_P3_U1_CFG12 0x400106cc +#define CYREG_B0_P3_U1_CFG13 0x400106cd +#define CYREG_B0_P3_U1_CFG14 0x400106ce +#define CYREG_B0_P3_U1_CFG15 0x400106cf +#define CYREG_B0_P3_U1_CFG16 0x400106d0 +#define CYREG_B0_P3_U1_CFG17 0x400106d1 +#define CYREG_B0_P3_U1_CFG18 0x400106d2 +#define CYREG_B0_P3_U1_CFG19 0x400106d3 +#define CYREG_B0_P3_U1_CFG20 0x400106d4 +#define CYREG_B0_P3_U1_CFG21 0x400106d5 +#define CYREG_B0_P3_U1_CFG22 0x400106d6 +#define CYREG_B0_P3_U1_CFG23 0x400106d7 +#define CYREG_B0_P3_U1_CFG24 0x400106d8 +#define CYREG_B0_P3_U1_CFG25 0x400106d9 +#define CYREG_B0_P3_U1_CFG26 0x400106da +#define CYREG_B0_P3_U1_CFG27 0x400106db +#define CYREG_B0_P3_U1_CFG28 0x400106dc +#define CYREG_B0_P3_U1_CFG29 0x400106dd +#define CYREG_B0_P3_U1_CFG30 0x400106de +#define CYREG_B0_P3_U1_CFG31 0x400106df +#define CYREG_B0_P3_U1_DCFG0 0x400106e0 +#define CYREG_B0_P3_U1_DCFG1 0x400106e2 +#define CYREG_B0_P3_U1_DCFG2 0x400106e4 +#define CYREG_B0_P3_U1_DCFG3 0x400106e6 +#define CYREG_B0_P3_U1_DCFG4 0x400106e8 +#define CYREG_B0_P3_U1_DCFG5 0x400106ea +#define CYREG_B0_P3_U1_DCFG6 0x400106ec +#define CYREG_B0_P3_U1_DCFG7 0x400106ee +#define CYDEV_UCFG_B0_P3_ROUTE_BASE 0x40010700 +#define CYDEV_UCFG_B0_P3_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P4_BASE 0x40010800 +#define CYDEV_UCFG_B0_P4_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P4_U0_BASE 0x40010800 +#define CYDEV_UCFG_B0_P4_U0_SIZE 0x00000070 +#define CYREG_B0_P4_U0_PLD_IT0 0x40010800 +#define CYREG_B0_P4_U0_PLD_IT1 0x40010804 +#define CYREG_B0_P4_U0_PLD_IT2 0x40010808 +#define CYREG_B0_P4_U0_PLD_IT3 0x4001080c +#define CYREG_B0_P4_U0_PLD_IT4 0x40010810 +#define CYREG_B0_P4_U0_PLD_IT5 0x40010814 +#define CYREG_B0_P4_U0_PLD_IT6 0x40010818 +#define CYREG_B0_P4_U0_PLD_IT7 0x4001081c +#define CYREG_B0_P4_U0_PLD_IT8 0x40010820 +#define CYREG_B0_P4_U0_PLD_IT9 0x40010824 +#define CYREG_B0_P4_U0_PLD_IT10 0x40010828 +#define CYREG_B0_P4_U0_PLD_IT11 0x4001082c +#define CYREG_B0_P4_U0_PLD_ORT0 0x40010830 +#define CYREG_B0_P4_U0_PLD_ORT1 0x40010832 +#define CYREG_B0_P4_U0_PLD_ORT2 0x40010834 +#define CYREG_B0_P4_U0_PLD_ORT3 0x40010836 +#define CYREG_B0_P4_U0_MC_CFG_CEN_CONST 0x40010838 +#define CYREG_B0_P4_U0_MC_CFG_XORFB 0x4001083a +#define CYREG_B0_P4_U0_MC_CFG_SET_RESET 0x4001083c +#define CYREG_B0_P4_U0_MC_CFG_BYPASS 0x4001083e +#define CYREG_B0_P4_U0_CFG0 0x40010840 +#define CYREG_B0_P4_U0_CFG1 0x40010841 +#define CYREG_B0_P4_U0_CFG2 0x40010842 +#define CYREG_B0_P4_U0_CFG3 0x40010843 +#define CYREG_B0_P4_U0_CFG4 0x40010844 +#define CYREG_B0_P4_U0_CFG5 0x40010845 +#define CYREG_B0_P4_U0_CFG6 0x40010846 +#define CYREG_B0_P4_U0_CFG7 0x40010847 +#define CYREG_B0_P4_U0_CFG8 0x40010848 +#define CYREG_B0_P4_U0_CFG9 0x40010849 +#define CYREG_B0_P4_U0_CFG10 0x4001084a +#define CYREG_B0_P4_U0_CFG11 0x4001084b +#define CYREG_B0_P4_U0_CFG12 0x4001084c +#define CYREG_B0_P4_U0_CFG13 0x4001084d +#define CYREG_B0_P4_U0_CFG14 0x4001084e +#define CYREG_B0_P4_U0_CFG15 0x4001084f +#define CYREG_B0_P4_U0_CFG16 0x40010850 +#define CYREG_B0_P4_U0_CFG17 0x40010851 +#define CYREG_B0_P4_U0_CFG18 0x40010852 +#define CYREG_B0_P4_U0_CFG19 0x40010853 +#define CYREG_B0_P4_U0_CFG20 0x40010854 +#define CYREG_B0_P4_U0_CFG21 0x40010855 +#define CYREG_B0_P4_U0_CFG22 0x40010856 +#define CYREG_B0_P4_U0_CFG23 0x40010857 +#define CYREG_B0_P4_U0_CFG24 0x40010858 +#define CYREG_B0_P4_U0_CFG25 0x40010859 +#define CYREG_B0_P4_U0_CFG26 0x4001085a +#define CYREG_B0_P4_U0_CFG27 0x4001085b +#define CYREG_B0_P4_U0_CFG28 0x4001085c +#define CYREG_B0_P4_U0_CFG29 0x4001085d +#define CYREG_B0_P4_U0_CFG30 0x4001085e +#define CYREG_B0_P4_U0_CFG31 0x4001085f +#define CYREG_B0_P4_U0_DCFG0 0x40010860 +#define CYREG_B0_P4_U0_DCFG1 0x40010862 +#define CYREG_B0_P4_U0_DCFG2 0x40010864 +#define CYREG_B0_P4_U0_DCFG3 0x40010866 +#define CYREG_B0_P4_U0_DCFG4 0x40010868 +#define CYREG_B0_P4_U0_DCFG5 0x4001086a +#define CYREG_B0_P4_U0_DCFG6 0x4001086c +#define CYREG_B0_P4_U0_DCFG7 0x4001086e +#define CYDEV_UCFG_B0_P4_U1_BASE 0x40010880 +#define CYDEV_UCFG_B0_P4_U1_SIZE 0x00000070 +#define CYREG_B0_P4_U1_PLD_IT0 0x40010880 +#define CYREG_B0_P4_U1_PLD_IT1 0x40010884 +#define CYREG_B0_P4_U1_PLD_IT2 0x40010888 +#define CYREG_B0_P4_U1_PLD_IT3 0x4001088c +#define CYREG_B0_P4_U1_PLD_IT4 0x40010890 +#define CYREG_B0_P4_U1_PLD_IT5 0x40010894 +#define CYREG_B0_P4_U1_PLD_IT6 0x40010898 +#define CYREG_B0_P4_U1_PLD_IT7 0x4001089c +#define CYREG_B0_P4_U1_PLD_IT8 0x400108a0 +#define CYREG_B0_P4_U1_PLD_IT9 0x400108a4 +#define CYREG_B0_P4_U1_PLD_IT10 0x400108a8 +#define CYREG_B0_P4_U1_PLD_IT11 0x400108ac +#define CYREG_B0_P4_U1_PLD_ORT0 0x400108b0 +#define CYREG_B0_P4_U1_PLD_ORT1 0x400108b2 +#define CYREG_B0_P4_U1_PLD_ORT2 0x400108b4 +#define CYREG_B0_P4_U1_PLD_ORT3 0x400108b6 +#define CYREG_B0_P4_U1_MC_CFG_CEN_CONST 0x400108b8 +#define CYREG_B0_P4_U1_MC_CFG_XORFB 0x400108ba +#define CYREG_B0_P4_U1_MC_CFG_SET_RESET 0x400108bc +#define CYREG_B0_P4_U1_MC_CFG_BYPASS 0x400108be +#define CYREG_B0_P4_U1_CFG0 0x400108c0 +#define CYREG_B0_P4_U1_CFG1 0x400108c1 +#define CYREG_B0_P4_U1_CFG2 0x400108c2 +#define CYREG_B0_P4_U1_CFG3 0x400108c3 +#define CYREG_B0_P4_U1_CFG4 0x400108c4 +#define CYREG_B0_P4_U1_CFG5 0x400108c5 +#define CYREG_B0_P4_U1_CFG6 0x400108c6 +#define CYREG_B0_P4_U1_CFG7 0x400108c7 +#define CYREG_B0_P4_U1_CFG8 0x400108c8 +#define CYREG_B0_P4_U1_CFG9 0x400108c9 +#define CYREG_B0_P4_U1_CFG10 0x400108ca +#define CYREG_B0_P4_U1_CFG11 0x400108cb +#define CYREG_B0_P4_U1_CFG12 0x400108cc +#define CYREG_B0_P4_U1_CFG13 0x400108cd +#define CYREG_B0_P4_U1_CFG14 0x400108ce +#define CYREG_B0_P4_U1_CFG15 0x400108cf +#define CYREG_B0_P4_U1_CFG16 0x400108d0 +#define CYREG_B0_P4_U1_CFG17 0x400108d1 +#define CYREG_B0_P4_U1_CFG18 0x400108d2 +#define CYREG_B0_P4_U1_CFG19 0x400108d3 +#define CYREG_B0_P4_U1_CFG20 0x400108d4 +#define CYREG_B0_P4_U1_CFG21 0x400108d5 +#define CYREG_B0_P4_U1_CFG22 0x400108d6 +#define CYREG_B0_P4_U1_CFG23 0x400108d7 +#define CYREG_B0_P4_U1_CFG24 0x400108d8 +#define CYREG_B0_P4_U1_CFG25 0x400108d9 +#define CYREG_B0_P4_U1_CFG26 0x400108da +#define CYREG_B0_P4_U1_CFG27 0x400108db +#define CYREG_B0_P4_U1_CFG28 0x400108dc +#define CYREG_B0_P4_U1_CFG29 0x400108dd +#define CYREG_B0_P4_U1_CFG30 0x400108de +#define CYREG_B0_P4_U1_CFG31 0x400108df +#define CYREG_B0_P4_U1_DCFG0 0x400108e0 +#define CYREG_B0_P4_U1_DCFG1 0x400108e2 +#define CYREG_B0_P4_U1_DCFG2 0x400108e4 +#define CYREG_B0_P4_U1_DCFG3 0x400108e6 +#define CYREG_B0_P4_U1_DCFG4 0x400108e8 +#define CYREG_B0_P4_U1_DCFG5 0x400108ea +#define CYREG_B0_P4_U1_DCFG6 0x400108ec +#define CYREG_B0_P4_U1_DCFG7 0x400108ee +#define CYDEV_UCFG_B0_P4_ROUTE_BASE 0x40010900 +#define CYDEV_UCFG_B0_P4_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P5_BASE 0x40010a00 +#define CYDEV_UCFG_B0_P5_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P5_U0_BASE 0x40010a00 +#define CYDEV_UCFG_B0_P5_U0_SIZE 0x00000070 +#define CYREG_B0_P5_U0_PLD_IT0 0x40010a00 +#define CYREG_B0_P5_U0_PLD_IT1 0x40010a04 +#define CYREG_B0_P5_U0_PLD_IT2 0x40010a08 +#define CYREG_B0_P5_U0_PLD_IT3 0x40010a0c +#define CYREG_B0_P5_U0_PLD_IT4 0x40010a10 +#define CYREG_B0_P5_U0_PLD_IT5 0x40010a14 +#define CYREG_B0_P5_U0_PLD_IT6 0x40010a18 +#define CYREG_B0_P5_U0_PLD_IT7 0x40010a1c +#define CYREG_B0_P5_U0_PLD_IT8 0x40010a20 +#define CYREG_B0_P5_U0_PLD_IT9 0x40010a24 +#define CYREG_B0_P5_U0_PLD_IT10 0x40010a28 +#define CYREG_B0_P5_U0_PLD_IT11 0x40010a2c +#define CYREG_B0_P5_U0_PLD_ORT0 0x40010a30 +#define CYREG_B0_P5_U0_PLD_ORT1 0x40010a32 +#define CYREG_B0_P5_U0_PLD_ORT2 0x40010a34 +#define CYREG_B0_P5_U0_PLD_ORT3 0x40010a36 +#define CYREG_B0_P5_U0_MC_CFG_CEN_CONST 0x40010a38 +#define CYREG_B0_P5_U0_MC_CFG_XORFB 0x40010a3a +#define CYREG_B0_P5_U0_MC_CFG_SET_RESET 0x40010a3c +#define CYREG_B0_P5_U0_MC_CFG_BYPASS 0x40010a3e +#define CYREG_B0_P5_U0_CFG0 0x40010a40 +#define CYREG_B0_P5_U0_CFG1 0x40010a41 +#define CYREG_B0_P5_U0_CFG2 0x40010a42 +#define CYREG_B0_P5_U0_CFG3 0x40010a43 +#define CYREG_B0_P5_U0_CFG4 0x40010a44 +#define CYREG_B0_P5_U0_CFG5 0x40010a45 +#define CYREG_B0_P5_U0_CFG6 0x40010a46 +#define CYREG_B0_P5_U0_CFG7 0x40010a47 +#define CYREG_B0_P5_U0_CFG8 0x40010a48 +#define CYREG_B0_P5_U0_CFG9 0x40010a49 +#define CYREG_B0_P5_U0_CFG10 0x40010a4a +#define CYREG_B0_P5_U0_CFG11 0x40010a4b +#define CYREG_B0_P5_U0_CFG12 0x40010a4c +#define CYREG_B0_P5_U0_CFG13 0x40010a4d +#define CYREG_B0_P5_U0_CFG14 0x40010a4e +#define CYREG_B0_P5_U0_CFG15 0x40010a4f +#define CYREG_B0_P5_U0_CFG16 0x40010a50 +#define CYREG_B0_P5_U0_CFG17 0x40010a51 +#define CYREG_B0_P5_U0_CFG18 0x40010a52 +#define CYREG_B0_P5_U0_CFG19 0x40010a53 +#define CYREG_B0_P5_U0_CFG20 0x40010a54 +#define CYREG_B0_P5_U0_CFG21 0x40010a55 +#define CYREG_B0_P5_U0_CFG22 0x40010a56 +#define CYREG_B0_P5_U0_CFG23 0x40010a57 +#define CYREG_B0_P5_U0_CFG24 0x40010a58 +#define CYREG_B0_P5_U0_CFG25 0x40010a59 +#define CYREG_B0_P5_U0_CFG26 0x40010a5a +#define CYREG_B0_P5_U0_CFG27 0x40010a5b +#define CYREG_B0_P5_U0_CFG28 0x40010a5c +#define CYREG_B0_P5_U0_CFG29 0x40010a5d +#define CYREG_B0_P5_U0_CFG30 0x40010a5e +#define CYREG_B0_P5_U0_CFG31 0x40010a5f +#define CYREG_B0_P5_U0_DCFG0 0x40010a60 +#define CYREG_B0_P5_U0_DCFG1 0x40010a62 +#define CYREG_B0_P5_U0_DCFG2 0x40010a64 +#define CYREG_B0_P5_U0_DCFG3 0x40010a66 +#define CYREG_B0_P5_U0_DCFG4 0x40010a68 +#define CYREG_B0_P5_U0_DCFG5 0x40010a6a +#define CYREG_B0_P5_U0_DCFG6 0x40010a6c +#define CYREG_B0_P5_U0_DCFG7 0x40010a6e +#define CYDEV_UCFG_B0_P5_U1_BASE 0x40010a80 +#define CYDEV_UCFG_B0_P5_U1_SIZE 0x00000070 +#define CYREG_B0_P5_U1_PLD_IT0 0x40010a80 +#define CYREG_B0_P5_U1_PLD_IT1 0x40010a84 +#define CYREG_B0_P5_U1_PLD_IT2 0x40010a88 +#define CYREG_B0_P5_U1_PLD_IT3 0x40010a8c +#define CYREG_B0_P5_U1_PLD_IT4 0x40010a90 +#define CYREG_B0_P5_U1_PLD_IT5 0x40010a94 +#define CYREG_B0_P5_U1_PLD_IT6 0x40010a98 +#define CYREG_B0_P5_U1_PLD_IT7 0x40010a9c +#define CYREG_B0_P5_U1_PLD_IT8 0x40010aa0 +#define CYREG_B0_P5_U1_PLD_IT9 0x40010aa4 +#define CYREG_B0_P5_U1_PLD_IT10 0x40010aa8 +#define CYREG_B0_P5_U1_PLD_IT11 0x40010aac +#define CYREG_B0_P5_U1_PLD_ORT0 0x40010ab0 +#define CYREG_B0_P5_U1_PLD_ORT1 0x40010ab2 +#define CYREG_B0_P5_U1_PLD_ORT2 0x40010ab4 +#define CYREG_B0_P5_U1_PLD_ORT3 0x40010ab6 +#define CYREG_B0_P5_U1_MC_CFG_CEN_CONST 0x40010ab8 +#define CYREG_B0_P5_U1_MC_CFG_XORFB 0x40010aba +#define CYREG_B0_P5_U1_MC_CFG_SET_RESET 0x40010abc +#define CYREG_B0_P5_U1_MC_CFG_BYPASS 0x40010abe +#define CYREG_B0_P5_U1_CFG0 0x40010ac0 +#define CYREG_B0_P5_U1_CFG1 0x40010ac1 +#define CYREG_B0_P5_U1_CFG2 0x40010ac2 +#define CYREG_B0_P5_U1_CFG3 0x40010ac3 +#define CYREG_B0_P5_U1_CFG4 0x40010ac4 +#define CYREG_B0_P5_U1_CFG5 0x40010ac5 +#define CYREG_B0_P5_U1_CFG6 0x40010ac6 +#define CYREG_B0_P5_U1_CFG7 0x40010ac7 +#define CYREG_B0_P5_U1_CFG8 0x40010ac8 +#define CYREG_B0_P5_U1_CFG9 0x40010ac9 +#define CYREG_B0_P5_U1_CFG10 0x40010aca +#define CYREG_B0_P5_U1_CFG11 0x40010acb +#define CYREG_B0_P5_U1_CFG12 0x40010acc +#define CYREG_B0_P5_U1_CFG13 0x40010acd +#define CYREG_B0_P5_U1_CFG14 0x40010ace +#define CYREG_B0_P5_U1_CFG15 0x40010acf +#define CYREG_B0_P5_U1_CFG16 0x40010ad0 +#define CYREG_B0_P5_U1_CFG17 0x40010ad1 +#define CYREG_B0_P5_U1_CFG18 0x40010ad2 +#define CYREG_B0_P5_U1_CFG19 0x40010ad3 +#define CYREG_B0_P5_U1_CFG20 0x40010ad4 +#define CYREG_B0_P5_U1_CFG21 0x40010ad5 +#define CYREG_B0_P5_U1_CFG22 0x40010ad6 +#define CYREG_B0_P5_U1_CFG23 0x40010ad7 +#define CYREG_B0_P5_U1_CFG24 0x40010ad8 +#define CYREG_B0_P5_U1_CFG25 0x40010ad9 +#define CYREG_B0_P5_U1_CFG26 0x40010ada +#define CYREG_B0_P5_U1_CFG27 0x40010adb +#define CYREG_B0_P5_U1_CFG28 0x40010adc +#define CYREG_B0_P5_U1_CFG29 0x40010add +#define CYREG_B0_P5_U1_CFG30 0x40010ade +#define CYREG_B0_P5_U1_CFG31 0x40010adf +#define CYREG_B0_P5_U1_DCFG0 0x40010ae0 +#define CYREG_B0_P5_U1_DCFG1 0x40010ae2 +#define CYREG_B0_P5_U1_DCFG2 0x40010ae4 +#define CYREG_B0_P5_U1_DCFG3 0x40010ae6 +#define CYREG_B0_P5_U1_DCFG4 0x40010ae8 +#define CYREG_B0_P5_U1_DCFG5 0x40010aea +#define CYREG_B0_P5_U1_DCFG6 0x40010aec +#define CYREG_B0_P5_U1_DCFG7 0x40010aee +#define CYDEV_UCFG_B0_P5_ROUTE_BASE 0x40010b00 +#define CYDEV_UCFG_B0_P5_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P6_BASE 0x40010c00 +#define CYDEV_UCFG_B0_P6_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P6_U0_BASE 0x40010c00 +#define CYDEV_UCFG_B0_P6_U0_SIZE 0x00000070 +#define CYREG_B0_P6_U0_PLD_IT0 0x40010c00 +#define CYREG_B0_P6_U0_PLD_IT1 0x40010c04 +#define CYREG_B0_P6_U0_PLD_IT2 0x40010c08 +#define CYREG_B0_P6_U0_PLD_IT3 0x40010c0c +#define CYREG_B0_P6_U0_PLD_IT4 0x40010c10 +#define CYREG_B0_P6_U0_PLD_IT5 0x40010c14 +#define CYREG_B0_P6_U0_PLD_IT6 0x40010c18 +#define CYREG_B0_P6_U0_PLD_IT7 0x40010c1c +#define CYREG_B0_P6_U0_PLD_IT8 0x40010c20 +#define CYREG_B0_P6_U0_PLD_IT9 0x40010c24 +#define CYREG_B0_P6_U0_PLD_IT10 0x40010c28 +#define CYREG_B0_P6_U0_PLD_IT11 0x40010c2c +#define CYREG_B0_P6_U0_PLD_ORT0 0x40010c30 +#define CYREG_B0_P6_U0_PLD_ORT1 0x40010c32 +#define CYREG_B0_P6_U0_PLD_ORT2 0x40010c34 +#define CYREG_B0_P6_U0_PLD_ORT3 0x40010c36 +#define CYREG_B0_P6_U0_MC_CFG_CEN_CONST 0x40010c38 +#define CYREG_B0_P6_U0_MC_CFG_XORFB 0x40010c3a +#define CYREG_B0_P6_U0_MC_CFG_SET_RESET 0x40010c3c +#define CYREG_B0_P6_U0_MC_CFG_BYPASS 0x40010c3e +#define CYREG_B0_P6_U0_CFG0 0x40010c40 +#define CYREG_B0_P6_U0_CFG1 0x40010c41 +#define CYREG_B0_P6_U0_CFG2 0x40010c42 +#define CYREG_B0_P6_U0_CFG3 0x40010c43 +#define CYREG_B0_P6_U0_CFG4 0x40010c44 +#define CYREG_B0_P6_U0_CFG5 0x40010c45 +#define CYREG_B0_P6_U0_CFG6 0x40010c46 +#define CYREG_B0_P6_U0_CFG7 0x40010c47 +#define CYREG_B0_P6_U0_CFG8 0x40010c48 +#define CYREG_B0_P6_U0_CFG9 0x40010c49 +#define CYREG_B0_P6_U0_CFG10 0x40010c4a +#define CYREG_B0_P6_U0_CFG11 0x40010c4b +#define CYREG_B0_P6_U0_CFG12 0x40010c4c +#define CYREG_B0_P6_U0_CFG13 0x40010c4d +#define CYREG_B0_P6_U0_CFG14 0x40010c4e +#define CYREG_B0_P6_U0_CFG15 0x40010c4f +#define CYREG_B0_P6_U0_CFG16 0x40010c50 +#define CYREG_B0_P6_U0_CFG17 0x40010c51 +#define CYREG_B0_P6_U0_CFG18 0x40010c52 +#define CYREG_B0_P6_U0_CFG19 0x40010c53 +#define CYREG_B0_P6_U0_CFG20 0x40010c54 +#define CYREG_B0_P6_U0_CFG21 0x40010c55 +#define CYREG_B0_P6_U0_CFG22 0x40010c56 +#define CYREG_B0_P6_U0_CFG23 0x40010c57 +#define CYREG_B0_P6_U0_CFG24 0x40010c58 +#define CYREG_B0_P6_U0_CFG25 0x40010c59 +#define CYREG_B0_P6_U0_CFG26 0x40010c5a +#define CYREG_B0_P6_U0_CFG27 0x40010c5b +#define CYREG_B0_P6_U0_CFG28 0x40010c5c +#define CYREG_B0_P6_U0_CFG29 0x40010c5d +#define CYREG_B0_P6_U0_CFG30 0x40010c5e +#define CYREG_B0_P6_U0_CFG31 0x40010c5f +#define CYREG_B0_P6_U0_DCFG0 0x40010c60 +#define CYREG_B0_P6_U0_DCFG1 0x40010c62 +#define CYREG_B0_P6_U0_DCFG2 0x40010c64 +#define CYREG_B0_P6_U0_DCFG3 0x40010c66 +#define CYREG_B0_P6_U0_DCFG4 0x40010c68 +#define CYREG_B0_P6_U0_DCFG5 0x40010c6a +#define CYREG_B0_P6_U0_DCFG6 0x40010c6c +#define CYREG_B0_P6_U0_DCFG7 0x40010c6e +#define CYDEV_UCFG_B0_P6_U1_BASE 0x40010c80 +#define CYDEV_UCFG_B0_P6_U1_SIZE 0x00000070 +#define CYREG_B0_P6_U1_PLD_IT0 0x40010c80 +#define CYREG_B0_P6_U1_PLD_IT1 0x40010c84 +#define CYREG_B0_P6_U1_PLD_IT2 0x40010c88 +#define CYREG_B0_P6_U1_PLD_IT3 0x40010c8c +#define CYREG_B0_P6_U1_PLD_IT4 0x40010c90 +#define CYREG_B0_P6_U1_PLD_IT5 0x40010c94 +#define CYREG_B0_P6_U1_PLD_IT6 0x40010c98 +#define CYREG_B0_P6_U1_PLD_IT7 0x40010c9c +#define CYREG_B0_P6_U1_PLD_IT8 0x40010ca0 +#define CYREG_B0_P6_U1_PLD_IT9 0x40010ca4 +#define CYREG_B0_P6_U1_PLD_IT10 0x40010ca8 +#define CYREG_B0_P6_U1_PLD_IT11 0x40010cac +#define CYREG_B0_P6_U1_PLD_ORT0 0x40010cb0 +#define CYREG_B0_P6_U1_PLD_ORT1 0x40010cb2 +#define CYREG_B0_P6_U1_PLD_ORT2 0x40010cb4 +#define CYREG_B0_P6_U1_PLD_ORT3 0x40010cb6 +#define CYREG_B0_P6_U1_MC_CFG_CEN_CONST 0x40010cb8 +#define CYREG_B0_P6_U1_MC_CFG_XORFB 0x40010cba +#define CYREG_B0_P6_U1_MC_CFG_SET_RESET 0x40010cbc +#define CYREG_B0_P6_U1_MC_CFG_BYPASS 0x40010cbe +#define CYREG_B0_P6_U1_CFG0 0x40010cc0 +#define CYREG_B0_P6_U1_CFG1 0x40010cc1 +#define CYREG_B0_P6_U1_CFG2 0x40010cc2 +#define CYREG_B0_P6_U1_CFG3 0x40010cc3 +#define CYREG_B0_P6_U1_CFG4 0x40010cc4 +#define CYREG_B0_P6_U1_CFG5 0x40010cc5 +#define CYREG_B0_P6_U1_CFG6 0x40010cc6 +#define CYREG_B0_P6_U1_CFG7 0x40010cc7 +#define CYREG_B0_P6_U1_CFG8 0x40010cc8 +#define CYREG_B0_P6_U1_CFG9 0x40010cc9 +#define CYREG_B0_P6_U1_CFG10 0x40010cca +#define CYREG_B0_P6_U1_CFG11 0x40010ccb +#define CYREG_B0_P6_U1_CFG12 0x40010ccc +#define CYREG_B0_P6_U1_CFG13 0x40010ccd +#define CYREG_B0_P6_U1_CFG14 0x40010cce +#define CYREG_B0_P6_U1_CFG15 0x40010ccf +#define CYREG_B0_P6_U1_CFG16 0x40010cd0 +#define CYREG_B0_P6_U1_CFG17 0x40010cd1 +#define CYREG_B0_P6_U1_CFG18 0x40010cd2 +#define CYREG_B0_P6_U1_CFG19 0x40010cd3 +#define CYREG_B0_P6_U1_CFG20 0x40010cd4 +#define CYREG_B0_P6_U1_CFG21 0x40010cd5 +#define CYREG_B0_P6_U1_CFG22 0x40010cd6 +#define CYREG_B0_P6_U1_CFG23 0x40010cd7 +#define CYREG_B0_P6_U1_CFG24 0x40010cd8 +#define CYREG_B0_P6_U1_CFG25 0x40010cd9 +#define CYREG_B0_P6_U1_CFG26 0x40010cda +#define CYREG_B0_P6_U1_CFG27 0x40010cdb +#define CYREG_B0_P6_U1_CFG28 0x40010cdc +#define CYREG_B0_P6_U1_CFG29 0x40010cdd +#define CYREG_B0_P6_U1_CFG30 0x40010cde +#define CYREG_B0_P6_U1_CFG31 0x40010cdf +#define CYREG_B0_P6_U1_DCFG0 0x40010ce0 +#define CYREG_B0_P6_U1_DCFG1 0x40010ce2 +#define CYREG_B0_P6_U1_DCFG2 0x40010ce4 +#define CYREG_B0_P6_U1_DCFG3 0x40010ce6 +#define CYREG_B0_P6_U1_DCFG4 0x40010ce8 +#define CYREG_B0_P6_U1_DCFG5 0x40010cea +#define CYREG_B0_P6_U1_DCFG6 0x40010cec +#define CYREG_B0_P6_U1_DCFG7 0x40010cee +#define CYDEV_UCFG_B0_P6_ROUTE_BASE 0x40010d00 +#define CYDEV_UCFG_B0_P6_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P7_BASE 0x40010e00 +#define CYDEV_UCFG_B0_P7_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P7_U0_BASE 0x40010e00 +#define CYDEV_UCFG_B0_P7_U0_SIZE 0x00000070 +#define CYREG_B0_P7_U0_PLD_IT0 0x40010e00 +#define CYREG_B0_P7_U0_PLD_IT1 0x40010e04 +#define CYREG_B0_P7_U0_PLD_IT2 0x40010e08 +#define CYREG_B0_P7_U0_PLD_IT3 0x40010e0c +#define CYREG_B0_P7_U0_PLD_IT4 0x40010e10 +#define CYREG_B0_P7_U0_PLD_IT5 0x40010e14 +#define CYREG_B0_P7_U0_PLD_IT6 0x40010e18 +#define CYREG_B0_P7_U0_PLD_IT7 0x40010e1c +#define CYREG_B0_P7_U0_PLD_IT8 0x40010e20 +#define CYREG_B0_P7_U0_PLD_IT9 0x40010e24 +#define CYREG_B0_P7_U0_PLD_IT10 0x40010e28 +#define CYREG_B0_P7_U0_PLD_IT11 0x40010e2c +#define CYREG_B0_P7_U0_PLD_ORT0 0x40010e30 +#define CYREG_B0_P7_U0_PLD_ORT1 0x40010e32 +#define CYREG_B0_P7_U0_PLD_ORT2 0x40010e34 +#define CYREG_B0_P7_U0_PLD_ORT3 0x40010e36 +#define CYREG_B0_P7_U0_MC_CFG_CEN_CONST 0x40010e38 +#define CYREG_B0_P7_U0_MC_CFG_XORFB 0x40010e3a +#define CYREG_B0_P7_U0_MC_CFG_SET_RESET 0x40010e3c +#define CYREG_B0_P7_U0_MC_CFG_BYPASS 0x40010e3e +#define CYREG_B0_P7_U0_CFG0 0x40010e40 +#define CYREG_B0_P7_U0_CFG1 0x40010e41 +#define CYREG_B0_P7_U0_CFG2 0x40010e42 +#define CYREG_B0_P7_U0_CFG3 0x40010e43 +#define CYREG_B0_P7_U0_CFG4 0x40010e44 +#define CYREG_B0_P7_U0_CFG5 0x40010e45 +#define CYREG_B0_P7_U0_CFG6 0x40010e46 +#define CYREG_B0_P7_U0_CFG7 0x40010e47 +#define CYREG_B0_P7_U0_CFG8 0x40010e48 +#define CYREG_B0_P7_U0_CFG9 0x40010e49 +#define CYREG_B0_P7_U0_CFG10 0x40010e4a +#define CYREG_B0_P7_U0_CFG11 0x40010e4b +#define CYREG_B0_P7_U0_CFG12 0x40010e4c +#define CYREG_B0_P7_U0_CFG13 0x40010e4d +#define CYREG_B0_P7_U0_CFG14 0x40010e4e +#define CYREG_B0_P7_U0_CFG15 0x40010e4f +#define CYREG_B0_P7_U0_CFG16 0x40010e50 +#define CYREG_B0_P7_U0_CFG17 0x40010e51 +#define CYREG_B0_P7_U0_CFG18 0x40010e52 +#define CYREG_B0_P7_U0_CFG19 0x40010e53 +#define CYREG_B0_P7_U0_CFG20 0x40010e54 +#define CYREG_B0_P7_U0_CFG21 0x40010e55 +#define CYREG_B0_P7_U0_CFG22 0x40010e56 +#define CYREG_B0_P7_U0_CFG23 0x40010e57 +#define CYREG_B0_P7_U0_CFG24 0x40010e58 +#define CYREG_B0_P7_U0_CFG25 0x40010e59 +#define CYREG_B0_P7_U0_CFG26 0x40010e5a +#define CYREG_B0_P7_U0_CFG27 0x40010e5b +#define CYREG_B0_P7_U0_CFG28 0x40010e5c +#define CYREG_B0_P7_U0_CFG29 0x40010e5d +#define CYREG_B0_P7_U0_CFG30 0x40010e5e +#define CYREG_B0_P7_U0_CFG31 0x40010e5f +#define CYREG_B0_P7_U0_DCFG0 0x40010e60 +#define CYREG_B0_P7_U0_DCFG1 0x40010e62 +#define CYREG_B0_P7_U0_DCFG2 0x40010e64 +#define CYREG_B0_P7_U0_DCFG3 0x40010e66 +#define CYREG_B0_P7_U0_DCFG4 0x40010e68 +#define CYREG_B0_P7_U0_DCFG5 0x40010e6a +#define CYREG_B0_P7_U0_DCFG6 0x40010e6c +#define CYREG_B0_P7_U0_DCFG7 0x40010e6e +#define CYDEV_UCFG_B0_P7_U1_BASE 0x40010e80 +#define CYDEV_UCFG_B0_P7_U1_SIZE 0x00000070 +#define CYREG_B0_P7_U1_PLD_IT0 0x40010e80 +#define CYREG_B0_P7_U1_PLD_IT1 0x40010e84 +#define CYREG_B0_P7_U1_PLD_IT2 0x40010e88 +#define CYREG_B0_P7_U1_PLD_IT3 0x40010e8c +#define CYREG_B0_P7_U1_PLD_IT4 0x40010e90 +#define CYREG_B0_P7_U1_PLD_IT5 0x40010e94 +#define CYREG_B0_P7_U1_PLD_IT6 0x40010e98 +#define CYREG_B0_P7_U1_PLD_IT7 0x40010e9c +#define CYREG_B0_P7_U1_PLD_IT8 0x40010ea0 +#define CYREG_B0_P7_U1_PLD_IT9 0x40010ea4 +#define CYREG_B0_P7_U1_PLD_IT10 0x40010ea8 +#define CYREG_B0_P7_U1_PLD_IT11 0x40010eac +#define CYREG_B0_P7_U1_PLD_ORT0 0x40010eb0 +#define CYREG_B0_P7_U1_PLD_ORT1 0x40010eb2 +#define CYREG_B0_P7_U1_PLD_ORT2 0x40010eb4 +#define CYREG_B0_P7_U1_PLD_ORT3 0x40010eb6 +#define CYREG_B0_P7_U1_MC_CFG_CEN_CONST 0x40010eb8 +#define CYREG_B0_P7_U1_MC_CFG_XORFB 0x40010eba +#define CYREG_B0_P7_U1_MC_CFG_SET_RESET 0x40010ebc +#define CYREG_B0_P7_U1_MC_CFG_BYPASS 0x40010ebe +#define CYREG_B0_P7_U1_CFG0 0x40010ec0 +#define CYREG_B0_P7_U1_CFG1 0x40010ec1 +#define CYREG_B0_P7_U1_CFG2 0x40010ec2 +#define CYREG_B0_P7_U1_CFG3 0x40010ec3 +#define CYREG_B0_P7_U1_CFG4 0x40010ec4 +#define CYREG_B0_P7_U1_CFG5 0x40010ec5 +#define CYREG_B0_P7_U1_CFG6 0x40010ec6 +#define CYREG_B0_P7_U1_CFG7 0x40010ec7 +#define CYREG_B0_P7_U1_CFG8 0x40010ec8 +#define CYREG_B0_P7_U1_CFG9 0x40010ec9 +#define CYREG_B0_P7_U1_CFG10 0x40010eca +#define CYREG_B0_P7_U1_CFG11 0x40010ecb +#define CYREG_B0_P7_U1_CFG12 0x40010ecc +#define CYREG_B0_P7_U1_CFG13 0x40010ecd +#define CYREG_B0_P7_U1_CFG14 0x40010ece +#define CYREG_B0_P7_U1_CFG15 0x40010ecf +#define CYREG_B0_P7_U1_CFG16 0x40010ed0 +#define CYREG_B0_P7_U1_CFG17 0x40010ed1 +#define CYREG_B0_P7_U1_CFG18 0x40010ed2 +#define CYREG_B0_P7_U1_CFG19 0x40010ed3 +#define CYREG_B0_P7_U1_CFG20 0x40010ed4 +#define CYREG_B0_P7_U1_CFG21 0x40010ed5 +#define CYREG_B0_P7_U1_CFG22 0x40010ed6 +#define CYREG_B0_P7_U1_CFG23 0x40010ed7 +#define CYREG_B0_P7_U1_CFG24 0x40010ed8 +#define CYREG_B0_P7_U1_CFG25 0x40010ed9 +#define CYREG_B0_P7_U1_CFG26 0x40010eda +#define CYREG_B0_P7_U1_CFG27 0x40010edb +#define CYREG_B0_P7_U1_CFG28 0x40010edc +#define CYREG_B0_P7_U1_CFG29 0x40010edd +#define CYREG_B0_P7_U1_CFG30 0x40010ede +#define CYREG_B0_P7_U1_CFG31 0x40010edf +#define CYREG_B0_P7_U1_DCFG0 0x40010ee0 +#define CYREG_B0_P7_U1_DCFG1 0x40010ee2 +#define CYREG_B0_P7_U1_DCFG2 0x40010ee4 +#define CYREG_B0_P7_U1_DCFG3 0x40010ee6 +#define CYREG_B0_P7_U1_DCFG4 0x40010ee8 +#define CYREG_B0_P7_U1_DCFG5 0x40010eea +#define CYREG_B0_P7_U1_DCFG6 0x40010eec +#define CYREG_B0_P7_U1_DCFG7 0x40010eee +#define CYDEV_UCFG_B0_P7_ROUTE_BASE 0x40010f00 +#define CYDEV_UCFG_B0_P7_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B1_BASE 0x40011000 +#define CYDEV_UCFG_B1_SIZE 0x00000fef +#define CYDEV_UCFG_B1_P2_BASE 0x40011400 +#define CYDEV_UCFG_B1_P2_SIZE 0x000001ef +#define CYDEV_UCFG_B1_P2_U0_BASE 0x40011400 +#define CYDEV_UCFG_B1_P2_U0_SIZE 0x00000070 +#define CYREG_B1_P2_U0_PLD_IT0 0x40011400 +#define CYREG_B1_P2_U0_PLD_IT1 0x40011404 +#define CYREG_B1_P2_U0_PLD_IT2 0x40011408 +#define CYREG_B1_P2_U0_PLD_IT3 0x4001140c +#define CYREG_B1_P2_U0_PLD_IT4 0x40011410 +#define CYREG_B1_P2_U0_PLD_IT5 0x40011414 +#define CYREG_B1_P2_U0_PLD_IT6 0x40011418 +#define CYREG_B1_P2_U0_PLD_IT7 0x4001141c +#define CYREG_B1_P2_U0_PLD_IT8 0x40011420 +#define CYREG_B1_P2_U0_PLD_IT9 0x40011424 +#define CYREG_B1_P2_U0_PLD_IT10 0x40011428 +#define CYREG_B1_P2_U0_PLD_IT11 0x4001142c +#define CYREG_B1_P2_U0_PLD_ORT0 0x40011430 +#define CYREG_B1_P2_U0_PLD_ORT1 0x40011432 +#define CYREG_B1_P2_U0_PLD_ORT2 0x40011434 +#define CYREG_B1_P2_U0_PLD_ORT3 0x40011436 +#define CYREG_B1_P2_U0_MC_CFG_CEN_CONST 0x40011438 +#define CYREG_B1_P2_U0_MC_CFG_XORFB 0x4001143a +#define CYREG_B1_P2_U0_MC_CFG_SET_RESET 0x4001143c +#define CYREG_B1_P2_U0_MC_CFG_BYPASS 0x4001143e +#define CYREG_B1_P2_U0_CFG0 0x40011440 +#define CYREG_B1_P2_U0_CFG1 0x40011441 +#define CYREG_B1_P2_U0_CFG2 0x40011442 +#define CYREG_B1_P2_U0_CFG3 0x40011443 +#define CYREG_B1_P2_U0_CFG4 0x40011444 +#define CYREG_B1_P2_U0_CFG5 0x40011445 +#define CYREG_B1_P2_U0_CFG6 0x40011446 +#define CYREG_B1_P2_U0_CFG7 0x40011447 +#define CYREG_B1_P2_U0_CFG8 0x40011448 +#define CYREG_B1_P2_U0_CFG9 0x40011449 +#define CYREG_B1_P2_U0_CFG10 0x4001144a +#define CYREG_B1_P2_U0_CFG11 0x4001144b +#define CYREG_B1_P2_U0_CFG12 0x4001144c +#define CYREG_B1_P2_U0_CFG13 0x4001144d +#define CYREG_B1_P2_U0_CFG14 0x4001144e +#define CYREG_B1_P2_U0_CFG15 0x4001144f +#define CYREG_B1_P2_U0_CFG16 0x40011450 +#define CYREG_B1_P2_U0_CFG17 0x40011451 +#define CYREG_B1_P2_U0_CFG18 0x40011452 +#define CYREG_B1_P2_U0_CFG19 0x40011453 +#define CYREG_B1_P2_U0_CFG20 0x40011454 +#define CYREG_B1_P2_U0_CFG21 0x40011455 +#define CYREG_B1_P2_U0_CFG22 0x40011456 +#define CYREG_B1_P2_U0_CFG23 0x40011457 +#define CYREG_B1_P2_U0_CFG24 0x40011458 +#define CYREG_B1_P2_U0_CFG25 0x40011459 +#define CYREG_B1_P2_U0_CFG26 0x4001145a +#define CYREG_B1_P2_U0_CFG27 0x4001145b +#define CYREG_B1_P2_U0_CFG28 0x4001145c +#define CYREG_B1_P2_U0_CFG29 0x4001145d +#define CYREG_B1_P2_U0_CFG30 0x4001145e +#define CYREG_B1_P2_U0_CFG31 0x4001145f +#define CYREG_B1_P2_U0_DCFG0 0x40011460 +#define CYREG_B1_P2_U0_DCFG1 0x40011462 +#define CYREG_B1_P2_U0_DCFG2 0x40011464 +#define CYREG_B1_P2_U0_DCFG3 0x40011466 +#define CYREG_B1_P2_U0_DCFG4 0x40011468 +#define CYREG_B1_P2_U0_DCFG5 0x4001146a +#define CYREG_B1_P2_U0_DCFG6 0x4001146c +#define CYREG_B1_P2_U0_DCFG7 0x4001146e +#define CYDEV_UCFG_B1_P2_U1_BASE 0x40011480 +#define CYDEV_UCFG_B1_P2_U1_SIZE 0x00000070 +#define CYREG_B1_P2_U1_PLD_IT0 0x40011480 +#define CYREG_B1_P2_U1_PLD_IT1 0x40011484 +#define CYREG_B1_P2_U1_PLD_IT2 0x40011488 +#define CYREG_B1_P2_U1_PLD_IT3 0x4001148c +#define CYREG_B1_P2_U1_PLD_IT4 0x40011490 +#define CYREG_B1_P2_U1_PLD_IT5 0x40011494 +#define CYREG_B1_P2_U1_PLD_IT6 0x40011498 +#define CYREG_B1_P2_U1_PLD_IT7 0x4001149c +#define CYREG_B1_P2_U1_PLD_IT8 0x400114a0 +#define CYREG_B1_P2_U1_PLD_IT9 0x400114a4 +#define CYREG_B1_P2_U1_PLD_IT10 0x400114a8 +#define CYREG_B1_P2_U1_PLD_IT11 0x400114ac +#define CYREG_B1_P2_U1_PLD_ORT0 0x400114b0 +#define CYREG_B1_P2_U1_PLD_ORT1 0x400114b2 +#define CYREG_B1_P2_U1_PLD_ORT2 0x400114b4 +#define CYREG_B1_P2_U1_PLD_ORT3 0x400114b6 +#define CYREG_B1_P2_U1_MC_CFG_CEN_CONST 0x400114b8 +#define CYREG_B1_P2_U1_MC_CFG_XORFB 0x400114ba +#define CYREG_B1_P2_U1_MC_CFG_SET_RESET 0x400114bc +#define CYREG_B1_P2_U1_MC_CFG_BYPASS 0x400114be +#define CYREG_B1_P2_U1_CFG0 0x400114c0 +#define CYREG_B1_P2_U1_CFG1 0x400114c1 +#define CYREG_B1_P2_U1_CFG2 0x400114c2 +#define CYREG_B1_P2_U1_CFG3 0x400114c3 +#define CYREG_B1_P2_U1_CFG4 0x400114c4 +#define CYREG_B1_P2_U1_CFG5 0x400114c5 +#define CYREG_B1_P2_U1_CFG6 0x400114c6 +#define CYREG_B1_P2_U1_CFG7 0x400114c7 +#define CYREG_B1_P2_U1_CFG8 0x400114c8 +#define CYREG_B1_P2_U1_CFG9 0x400114c9 +#define CYREG_B1_P2_U1_CFG10 0x400114ca +#define CYREG_B1_P2_U1_CFG11 0x400114cb +#define CYREG_B1_P2_U1_CFG12 0x400114cc +#define CYREG_B1_P2_U1_CFG13 0x400114cd +#define CYREG_B1_P2_U1_CFG14 0x400114ce +#define CYREG_B1_P2_U1_CFG15 0x400114cf +#define CYREG_B1_P2_U1_CFG16 0x400114d0 +#define CYREG_B1_P2_U1_CFG17 0x400114d1 +#define CYREG_B1_P2_U1_CFG18 0x400114d2 +#define CYREG_B1_P2_U1_CFG19 0x400114d3 +#define CYREG_B1_P2_U1_CFG20 0x400114d4 +#define CYREG_B1_P2_U1_CFG21 0x400114d5 +#define CYREG_B1_P2_U1_CFG22 0x400114d6 +#define CYREG_B1_P2_U1_CFG23 0x400114d7 +#define CYREG_B1_P2_U1_CFG24 0x400114d8 +#define CYREG_B1_P2_U1_CFG25 0x400114d9 +#define CYREG_B1_P2_U1_CFG26 0x400114da +#define CYREG_B1_P2_U1_CFG27 0x400114db +#define CYREG_B1_P2_U1_CFG28 0x400114dc +#define CYREG_B1_P2_U1_CFG29 0x400114dd +#define CYREG_B1_P2_U1_CFG30 0x400114de +#define CYREG_B1_P2_U1_CFG31 0x400114df +#define CYREG_B1_P2_U1_DCFG0 0x400114e0 +#define CYREG_B1_P2_U1_DCFG1 0x400114e2 +#define CYREG_B1_P2_U1_DCFG2 0x400114e4 +#define CYREG_B1_P2_U1_DCFG3 0x400114e6 +#define CYREG_B1_P2_U1_DCFG4 0x400114e8 +#define CYREG_B1_P2_U1_DCFG5 0x400114ea +#define CYREG_B1_P2_U1_DCFG6 0x400114ec +#define CYREG_B1_P2_U1_DCFG7 0x400114ee +#define CYDEV_UCFG_B1_P2_ROUTE_BASE 0x40011500 +#define CYDEV_UCFG_B1_P2_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B1_P3_BASE 0x40011600 +#define CYDEV_UCFG_B1_P3_SIZE 0x000001ef +#define CYDEV_UCFG_B1_P3_U0_BASE 0x40011600 +#define CYDEV_UCFG_B1_P3_U0_SIZE 0x00000070 +#define CYREG_B1_P3_U0_PLD_IT0 0x40011600 +#define CYREG_B1_P3_U0_PLD_IT1 0x40011604 +#define CYREG_B1_P3_U0_PLD_IT2 0x40011608 +#define CYREG_B1_P3_U0_PLD_IT3 0x4001160c +#define CYREG_B1_P3_U0_PLD_IT4 0x40011610 +#define CYREG_B1_P3_U0_PLD_IT5 0x40011614 +#define CYREG_B1_P3_U0_PLD_IT6 0x40011618 +#define CYREG_B1_P3_U0_PLD_IT7 0x4001161c +#define CYREG_B1_P3_U0_PLD_IT8 0x40011620 +#define CYREG_B1_P3_U0_PLD_IT9 0x40011624 +#define CYREG_B1_P3_U0_PLD_IT10 0x40011628 +#define CYREG_B1_P3_U0_PLD_IT11 0x4001162c +#define CYREG_B1_P3_U0_PLD_ORT0 0x40011630 +#define CYREG_B1_P3_U0_PLD_ORT1 0x40011632 +#define CYREG_B1_P3_U0_PLD_ORT2 0x40011634 +#define CYREG_B1_P3_U0_PLD_ORT3 0x40011636 +#define CYREG_B1_P3_U0_MC_CFG_CEN_CONST 0x40011638 +#define CYREG_B1_P3_U0_MC_CFG_XORFB 0x4001163a +#define CYREG_B1_P3_U0_MC_CFG_SET_RESET 0x4001163c +#define CYREG_B1_P3_U0_MC_CFG_BYPASS 0x4001163e +#define CYREG_B1_P3_U0_CFG0 0x40011640 +#define CYREG_B1_P3_U0_CFG1 0x40011641 +#define CYREG_B1_P3_U0_CFG2 0x40011642 +#define CYREG_B1_P3_U0_CFG3 0x40011643 +#define CYREG_B1_P3_U0_CFG4 0x40011644 +#define CYREG_B1_P3_U0_CFG5 0x40011645 +#define CYREG_B1_P3_U0_CFG6 0x40011646 +#define CYREG_B1_P3_U0_CFG7 0x40011647 +#define CYREG_B1_P3_U0_CFG8 0x40011648 +#define CYREG_B1_P3_U0_CFG9 0x40011649 +#define CYREG_B1_P3_U0_CFG10 0x4001164a +#define CYREG_B1_P3_U0_CFG11 0x4001164b +#define CYREG_B1_P3_U0_CFG12 0x4001164c +#define CYREG_B1_P3_U0_CFG13 0x4001164d +#define CYREG_B1_P3_U0_CFG14 0x4001164e +#define CYREG_B1_P3_U0_CFG15 0x4001164f +#define CYREG_B1_P3_U0_CFG16 0x40011650 +#define CYREG_B1_P3_U0_CFG17 0x40011651 +#define CYREG_B1_P3_U0_CFG18 0x40011652 +#define CYREG_B1_P3_U0_CFG19 0x40011653 +#define CYREG_B1_P3_U0_CFG20 0x40011654 +#define CYREG_B1_P3_U0_CFG21 0x40011655 +#define CYREG_B1_P3_U0_CFG22 0x40011656 +#define CYREG_B1_P3_U0_CFG23 0x40011657 +#define CYREG_B1_P3_U0_CFG24 0x40011658 +#define CYREG_B1_P3_U0_CFG25 0x40011659 +#define CYREG_B1_P3_U0_CFG26 0x4001165a +#define CYREG_B1_P3_U0_CFG27 0x4001165b +#define CYREG_B1_P3_U0_CFG28 0x4001165c +#define CYREG_B1_P3_U0_CFG29 0x4001165d +#define CYREG_B1_P3_U0_CFG30 0x4001165e +#define CYREG_B1_P3_U0_CFG31 0x4001165f +#define CYREG_B1_P3_U0_DCFG0 0x40011660 +#define CYREG_B1_P3_U0_DCFG1 0x40011662 +#define CYREG_B1_P3_U0_DCFG2 0x40011664 +#define CYREG_B1_P3_U0_DCFG3 0x40011666 +#define CYREG_B1_P3_U0_DCFG4 0x40011668 +#define CYREG_B1_P3_U0_DCFG5 0x4001166a +#define CYREG_B1_P3_U0_DCFG6 0x4001166c +#define CYREG_B1_P3_U0_DCFG7 0x4001166e +#define CYDEV_UCFG_B1_P3_U1_BASE 0x40011680 +#define CYDEV_UCFG_B1_P3_U1_SIZE 0x00000070 +#define CYREG_B1_P3_U1_PLD_IT0 0x40011680 +#define CYREG_B1_P3_U1_PLD_IT1 0x40011684 +#define CYREG_B1_P3_U1_PLD_IT2 0x40011688 +#define CYREG_B1_P3_U1_PLD_IT3 0x4001168c +#define CYREG_B1_P3_U1_PLD_IT4 0x40011690 +#define CYREG_B1_P3_U1_PLD_IT5 0x40011694 +#define CYREG_B1_P3_U1_PLD_IT6 0x40011698 +#define CYREG_B1_P3_U1_PLD_IT7 0x4001169c +#define CYREG_B1_P3_U1_PLD_IT8 0x400116a0 +#define CYREG_B1_P3_U1_PLD_IT9 0x400116a4 +#define CYREG_B1_P3_U1_PLD_IT10 0x400116a8 +#define CYREG_B1_P3_U1_PLD_IT11 0x400116ac +#define CYREG_B1_P3_U1_PLD_ORT0 0x400116b0 +#define CYREG_B1_P3_U1_PLD_ORT1 0x400116b2 +#define CYREG_B1_P3_U1_PLD_ORT2 0x400116b4 +#define CYREG_B1_P3_U1_PLD_ORT3 0x400116b6 +#define CYREG_B1_P3_U1_MC_CFG_CEN_CONST 0x400116b8 +#define CYREG_B1_P3_U1_MC_CFG_XORFB 0x400116ba +#define CYREG_B1_P3_U1_MC_CFG_SET_RESET 0x400116bc +#define CYREG_B1_P3_U1_MC_CFG_BYPASS 0x400116be +#define CYREG_B1_P3_U1_CFG0 0x400116c0 +#define CYREG_B1_P3_U1_CFG1 0x400116c1 +#define CYREG_B1_P3_U1_CFG2 0x400116c2 +#define CYREG_B1_P3_U1_CFG3 0x400116c3 +#define CYREG_B1_P3_U1_CFG4 0x400116c4 +#define CYREG_B1_P3_U1_CFG5 0x400116c5 +#define CYREG_B1_P3_U1_CFG6 0x400116c6 +#define CYREG_B1_P3_U1_CFG7 0x400116c7 +#define CYREG_B1_P3_U1_CFG8 0x400116c8 +#define CYREG_B1_P3_U1_CFG9 0x400116c9 +#define CYREG_B1_P3_U1_CFG10 0x400116ca +#define CYREG_B1_P3_U1_CFG11 0x400116cb +#define CYREG_B1_P3_U1_CFG12 0x400116cc +#define CYREG_B1_P3_U1_CFG13 0x400116cd +#define CYREG_B1_P3_U1_CFG14 0x400116ce +#define CYREG_B1_P3_U1_CFG15 0x400116cf +#define CYREG_B1_P3_U1_CFG16 0x400116d0 +#define CYREG_B1_P3_U1_CFG17 0x400116d1 +#define CYREG_B1_P3_U1_CFG18 0x400116d2 +#define CYREG_B1_P3_U1_CFG19 0x400116d3 +#define CYREG_B1_P3_U1_CFG20 0x400116d4 +#define CYREG_B1_P3_U1_CFG21 0x400116d5 +#define CYREG_B1_P3_U1_CFG22 0x400116d6 +#define CYREG_B1_P3_U1_CFG23 0x400116d7 +#define CYREG_B1_P3_U1_CFG24 0x400116d8 +#define CYREG_B1_P3_U1_CFG25 0x400116d9 +#define CYREG_B1_P3_U1_CFG26 0x400116da +#define CYREG_B1_P3_U1_CFG27 0x400116db +#define CYREG_B1_P3_U1_CFG28 0x400116dc +#define CYREG_B1_P3_U1_CFG29 0x400116dd +#define CYREG_B1_P3_U1_CFG30 0x400116de +#define CYREG_B1_P3_U1_CFG31 0x400116df +#define CYREG_B1_P3_U1_DCFG0 0x400116e0 +#define CYREG_B1_P3_U1_DCFG1 0x400116e2 +#define CYREG_B1_P3_U1_DCFG2 0x400116e4 +#define CYREG_B1_P3_U1_DCFG3 0x400116e6 +#define CYREG_B1_P3_U1_DCFG4 0x400116e8 +#define CYREG_B1_P3_U1_DCFG5 0x400116ea +#define CYREG_B1_P3_U1_DCFG6 0x400116ec +#define CYREG_B1_P3_U1_DCFG7 0x400116ee +#define CYDEV_UCFG_B1_P3_ROUTE_BASE 0x40011700 +#define CYDEV_UCFG_B1_P3_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B1_P4_BASE 0x40011800 +#define CYDEV_UCFG_B1_P4_SIZE 0x000001ef +#define CYDEV_UCFG_B1_P4_U0_BASE 0x40011800 +#define CYDEV_UCFG_B1_P4_U0_SIZE 0x00000070 +#define CYREG_B1_P4_U0_PLD_IT0 0x40011800 +#define CYREG_B1_P4_U0_PLD_IT1 0x40011804 +#define CYREG_B1_P4_U0_PLD_IT2 0x40011808 +#define CYREG_B1_P4_U0_PLD_IT3 0x4001180c +#define CYREG_B1_P4_U0_PLD_IT4 0x40011810 +#define CYREG_B1_P4_U0_PLD_IT5 0x40011814 +#define CYREG_B1_P4_U0_PLD_IT6 0x40011818 +#define CYREG_B1_P4_U0_PLD_IT7 0x4001181c +#define CYREG_B1_P4_U0_PLD_IT8 0x40011820 +#define CYREG_B1_P4_U0_PLD_IT9 0x40011824 +#define CYREG_B1_P4_U0_PLD_IT10 0x40011828 +#define CYREG_B1_P4_U0_PLD_IT11 0x4001182c +#define CYREG_B1_P4_U0_PLD_ORT0 0x40011830 +#define CYREG_B1_P4_U0_PLD_ORT1 0x40011832 +#define CYREG_B1_P4_U0_PLD_ORT2 0x40011834 +#define CYREG_B1_P4_U0_PLD_ORT3 0x40011836 +#define CYREG_B1_P4_U0_MC_CFG_CEN_CONST 0x40011838 +#define CYREG_B1_P4_U0_MC_CFG_XORFB 0x4001183a +#define CYREG_B1_P4_U0_MC_CFG_SET_RESET 0x4001183c +#define CYREG_B1_P4_U0_MC_CFG_BYPASS 0x4001183e +#define CYREG_B1_P4_U0_CFG0 0x40011840 +#define CYREG_B1_P4_U0_CFG1 0x40011841 +#define CYREG_B1_P4_U0_CFG2 0x40011842 +#define CYREG_B1_P4_U0_CFG3 0x40011843 +#define CYREG_B1_P4_U0_CFG4 0x40011844 +#define CYREG_B1_P4_U0_CFG5 0x40011845 +#define CYREG_B1_P4_U0_CFG6 0x40011846 +#define CYREG_B1_P4_U0_CFG7 0x40011847 +#define CYREG_B1_P4_U0_CFG8 0x40011848 +#define CYREG_B1_P4_U0_CFG9 0x40011849 +#define CYREG_B1_P4_U0_CFG10 0x4001184a +#define CYREG_B1_P4_U0_CFG11 0x4001184b +#define CYREG_B1_P4_U0_CFG12 0x4001184c +#define CYREG_B1_P4_U0_CFG13 0x4001184d +#define CYREG_B1_P4_U0_CFG14 0x4001184e +#define CYREG_B1_P4_U0_CFG15 0x4001184f +#define CYREG_B1_P4_U0_CFG16 0x40011850 +#define CYREG_B1_P4_U0_CFG17 0x40011851 +#define CYREG_B1_P4_U0_CFG18 0x40011852 +#define CYREG_B1_P4_U0_CFG19 0x40011853 +#define CYREG_B1_P4_U0_CFG20 0x40011854 +#define CYREG_B1_P4_U0_CFG21 0x40011855 +#define CYREG_B1_P4_U0_CFG22 0x40011856 +#define CYREG_B1_P4_U0_CFG23 0x40011857 +#define CYREG_B1_P4_U0_CFG24 0x40011858 +#define CYREG_B1_P4_U0_CFG25 0x40011859 +#define CYREG_B1_P4_U0_CFG26 0x4001185a +#define CYREG_B1_P4_U0_CFG27 0x4001185b +#define CYREG_B1_P4_U0_CFG28 0x4001185c +#define CYREG_B1_P4_U0_CFG29 0x4001185d +#define CYREG_B1_P4_U0_CFG30 0x4001185e +#define CYREG_B1_P4_U0_CFG31 0x4001185f +#define CYREG_B1_P4_U0_DCFG0 0x40011860 +#define CYREG_B1_P4_U0_DCFG1 0x40011862 +#define CYREG_B1_P4_U0_DCFG2 0x40011864 +#define CYREG_B1_P4_U0_DCFG3 0x40011866 +#define CYREG_B1_P4_U0_DCFG4 0x40011868 +#define CYREG_B1_P4_U0_DCFG5 0x4001186a +#define CYREG_B1_P4_U0_DCFG6 0x4001186c +#define CYREG_B1_P4_U0_DCFG7 0x4001186e +#define CYDEV_UCFG_B1_P4_U1_BASE 0x40011880 +#define CYDEV_UCFG_B1_P4_U1_SIZE 0x00000070 +#define CYREG_B1_P4_U1_PLD_IT0 0x40011880 +#define CYREG_B1_P4_U1_PLD_IT1 0x40011884 +#define CYREG_B1_P4_U1_PLD_IT2 0x40011888 +#define CYREG_B1_P4_U1_PLD_IT3 0x4001188c +#define CYREG_B1_P4_U1_PLD_IT4 0x40011890 +#define CYREG_B1_P4_U1_PLD_IT5 0x40011894 +#define CYREG_B1_P4_U1_PLD_IT6 0x40011898 +#define CYREG_B1_P4_U1_PLD_IT7 0x4001189c +#define CYREG_B1_P4_U1_PLD_IT8 0x400118a0 +#define CYREG_B1_P4_U1_PLD_IT9 0x400118a4 +#define CYREG_B1_P4_U1_PLD_IT10 0x400118a8 +#define CYREG_B1_P4_U1_PLD_IT11 0x400118ac +#define CYREG_B1_P4_U1_PLD_ORT0 0x400118b0 +#define CYREG_B1_P4_U1_PLD_ORT1 0x400118b2 +#define CYREG_B1_P4_U1_PLD_ORT2 0x400118b4 +#define CYREG_B1_P4_U1_PLD_ORT3 0x400118b6 +#define CYREG_B1_P4_U1_MC_CFG_CEN_CONST 0x400118b8 +#define CYREG_B1_P4_U1_MC_CFG_XORFB 0x400118ba +#define CYREG_B1_P4_U1_MC_CFG_SET_RESET 0x400118bc +#define CYREG_B1_P4_U1_MC_CFG_BYPASS 0x400118be +#define CYREG_B1_P4_U1_CFG0 0x400118c0 +#define CYREG_B1_P4_U1_CFG1 0x400118c1 +#define CYREG_B1_P4_U1_CFG2 0x400118c2 +#define CYREG_B1_P4_U1_CFG3 0x400118c3 +#define CYREG_B1_P4_U1_CFG4 0x400118c4 +#define CYREG_B1_P4_U1_CFG5 0x400118c5 +#define CYREG_B1_P4_U1_CFG6 0x400118c6 +#define CYREG_B1_P4_U1_CFG7 0x400118c7 +#define CYREG_B1_P4_U1_CFG8 0x400118c8 +#define CYREG_B1_P4_U1_CFG9 0x400118c9 +#define CYREG_B1_P4_U1_CFG10 0x400118ca +#define CYREG_B1_P4_U1_CFG11 0x400118cb +#define CYREG_B1_P4_U1_CFG12 0x400118cc +#define CYREG_B1_P4_U1_CFG13 0x400118cd +#define CYREG_B1_P4_U1_CFG14 0x400118ce +#define CYREG_B1_P4_U1_CFG15 0x400118cf +#define CYREG_B1_P4_U1_CFG16 0x400118d0 +#define CYREG_B1_P4_U1_CFG17 0x400118d1 +#define CYREG_B1_P4_U1_CFG18 0x400118d2 +#define CYREG_B1_P4_U1_CFG19 0x400118d3 +#define CYREG_B1_P4_U1_CFG20 0x400118d4 +#define CYREG_B1_P4_U1_CFG21 0x400118d5 +#define CYREG_B1_P4_U1_CFG22 0x400118d6 +#define CYREG_B1_P4_U1_CFG23 0x400118d7 +#define CYREG_B1_P4_U1_CFG24 0x400118d8 +#define CYREG_B1_P4_U1_CFG25 0x400118d9 +#define CYREG_B1_P4_U1_CFG26 0x400118da +#define CYREG_B1_P4_U1_CFG27 0x400118db +#define CYREG_B1_P4_U1_CFG28 0x400118dc +#define CYREG_B1_P4_U1_CFG29 0x400118dd +#define CYREG_B1_P4_U1_CFG30 0x400118de +#define CYREG_B1_P4_U1_CFG31 0x400118df +#define CYREG_B1_P4_U1_DCFG0 0x400118e0 +#define CYREG_B1_P4_U1_DCFG1 0x400118e2 +#define CYREG_B1_P4_U1_DCFG2 0x400118e4 +#define CYREG_B1_P4_U1_DCFG3 0x400118e6 +#define CYREG_B1_P4_U1_DCFG4 0x400118e8 +#define CYREG_B1_P4_U1_DCFG5 0x400118ea +#define CYREG_B1_P4_U1_DCFG6 0x400118ec +#define CYREG_B1_P4_U1_DCFG7 0x400118ee +#define CYDEV_UCFG_B1_P4_ROUTE_BASE 0x40011900 +#define CYDEV_UCFG_B1_P4_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B1_P5_BASE 0x40011a00 +#define CYDEV_UCFG_B1_P5_SIZE 0x000001ef +#define CYDEV_UCFG_B1_P5_U0_BASE 0x40011a00 +#define CYDEV_UCFG_B1_P5_U0_SIZE 0x00000070 +#define CYREG_B1_P5_U0_PLD_IT0 0x40011a00 +#define CYREG_B1_P5_U0_PLD_IT1 0x40011a04 +#define CYREG_B1_P5_U0_PLD_IT2 0x40011a08 +#define CYREG_B1_P5_U0_PLD_IT3 0x40011a0c +#define CYREG_B1_P5_U0_PLD_IT4 0x40011a10 +#define CYREG_B1_P5_U0_PLD_IT5 0x40011a14 +#define CYREG_B1_P5_U0_PLD_IT6 0x40011a18 +#define CYREG_B1_P5_U0_PLD_IT7 0x40011a1c +#define CYREG_B1_P5_U0_PLD_IT8 0x40011a20 +#define CYREG_B1_P5_U0_PLD_IT9 0x40011a24 +#define CYREG_B1_P5_U0_PLD_IT10 0x40011a28 +#define CYREG_B1_P5_U0_PLD_IT11 0x40011a2c +#define CYREG_B1_P5_U0_PLD_ORT0 0x40011a30 +#define CYREG_B1_P5_U0_PLD_ORT1 0x40011a32 +#define CYREG_B1_P5_U0_PLD_ORT2 0x40011a34 +#define CYREG_B1_P5_U0_PLD_ORT3 0x40011a36 +#define CYREG_B1_P5_U0_MC_CFG_CEN_CONST 0x40011a38 +#define CYREG_B1_P5_U0_MC_CFG_XORFB 0x40011a3a +#define CYREG_B1_P5_U0_MC_CFG_SET_RESET 0x40011a3c +#define CYREG_B1_P5_U0_MC_CFG_BYPASS 0x40011a3e +#define CYREG_B1_P5_U0_CFG0 0x40011a40 +#define CYREG_B1_P5_U0_CFG1 0x40011a41 +#define CYREG_B1_P5_U0_CFG2 0x40011a42 +#define CYREG_B1_P5_U0_CFG3 0x40011a43 +#define CYREG_B1_P5_U0_CFG4 0x40011a44 +#define CYREG_B1_P5_U0_CFG5 0x40011a45 +#define CYREG_B1_P5_U0_CFG6 0x40011a46 +#define CYREG_B1_P5_U0_CFG7 0x40011a47 +#define CYREG_B1_P5_U0_CFG8 0x40011a48 +#define CYREG_B1_P5_U0_CFG9 0x40011a49 +#define CYREG_B1_P5_U0_CFG10 0x40011a4a +#define CYREG_B1_P5_U0_CFG11 0x40011a4b +#define CYREG_B1_P5_U0_CFG12 0x40011a4c +#define CYREG_B1_P5_U0_CFG13 0x40011a4d +#define CYREG_B1_P5_U0_CFG14 0x40011a4e +#define CYREG_B1_P5_U0_CFG15 0x40011a4f +#define CYREG_B1_P5_U0_CFG16 0x40011a50 +#define CYREG_B1_P5_U0_CFG17 0x40011a51 +#define CYREG_B1_P5_U0_CFG18 0x40011a52 +#define CYREG_B1_P5_U0_CFG19 0x40011a53 +#define CYREG_B1_P5_U0_CFG20 0x40011a54 +#define CYREG_B1_P5_U0_CFG21 0x40011a55 +#define CYREG_B1_P5_U0_CFG22 0x40011a56 +#define CYREG_B1_P5_U0_CFG23 0x40011a57 +#define CYREG_B1_P5_U0_CFG24 0x40011a58 +#define CYREG_B1_P5_U0_CFG25 0x40011a59 +#define CYREG_B1_P5_U0_CFG26 0x40011a5a +#define CYREG_B1_P5_U0_CFG27 0x40011a5b +#define CYREG_B1_P5_U0_CFG28 0x40011a5c +#define CYREG_B1_P5_U0_CFG29 0x40011a5d +#define CYREG_B1_P5_U0_CFG30 0x40011a5e +#define CYREG_B1_P5_U0_CFG31 0x40011a5f +#define CYREG_B1_P5_U0_DCFG0 0x40011a60 +#define CYREG_B1_P5_U0_DCFG1 0x40011a62 +#define CYREG_B1_P5_U0_DCFG2 0x40011a64 +#define CYREG_B1_P5_U0_DCFG3 0x40011a66 +#define CYREG_B1_P5_U0_DCFG4 0x40011a68 +#define CYREG_B1_P5_U0_DCFG5 0x40011a6a +#define CYREG_B1_P5_U0_DCFG6 0x40011a6c +#define CYREG_B1_P5_U0_DCFG7 0x40011a6e +#define CYDEV_UCFG_B1_P5_U1_BASE 0x40011a80 +#define CYDEV_UCFG_B1_P5_U1_SIZE 0x00000070 +#define CYREG_B1_P5_U1_PLD_IT0 0x40011a80 +#define CYREG_B1_P5_U1_PLD_IT1 0x40011a84 +#define CYREG_B1_P5_U1_PLD_IT2 0x40011a88 +#define CYREG_B1_P5_U1_PLD_IT3 0x40011a8c +#define CYREG_B1_P5_U1_PLD_IT4 0x40011a90 +#define CYREG_B1_P5_U1_PLD_IT5 0x40011a94 +#define CYREG_B1_P5_U1_PLD_IT6 0x40011a98 +#define CYREG_B1_P5_U1_PLD_IT7 0x40011a9c +#define CYREG_B1_P5_U1_PLD_IT8 0x40011aa0 +#define CYREG_B1_P5_U1_PLD_IT9 0x40011aa4 +#define CYREG_B1_P5_U1_PLD_IT10 0x40011aa8 +#define CYREG_B1_P5_U1_PLD_IT11 0x40011aac +#define CYREG_B1_P5_U1_PLD_ORT0 0x40011ab0 +#define CYREG_B1_P5_U1_PLD_ORT1 0x40011ab2 +#define CYREG_B1_P5_U1_PLD_ORT2 0x40011ab4 +#define CYREG_B1_P5_U1_PLD_ORT3 0x40011ab6 +#define CYREG_B1_P5_U1_MC_CFG_CEN_CONST 0x40011ab8 +#define CYREG_B1_P5_U1_MC_CFG_XORFB 0x40011aba +#define CYREG_B1_P5_U1_MC_CFG_SET_RESET 0x40011abc +#define CYREG_B1_P5_U1_MC_CFG_BYPASS 0x40011abe +#define CYREG_B1_P5_U1_CFG0 0x40011ac0 +#define CYREG_B1_P5_U1_CFG1 0x40011ac1 +#define CYREG_B1_P5_U1_CFG2 0x40011ac2 +#define CYREG_B1_P5_U1_CFG3 0x40011ac3 +#define CYREG_B1_P5_U1_CFG4 0x40011ac4 +#define CYREG_B1_P5_U1_CFG5 0x40011ac5 +#define CYREG_B1_P5_U1_CFG6 0x40011ac6 +#define CYREG_B1_P5_U1_CFG7 0x40011ac7 +#define CYREG_B1_P5_U1_CFG8 0x40011ac8 +#define CYREG_B1_P5_U1_CFG9 0x40011ac9 +#define CYREG_B1_P5_U1_CFG10 0x40011aca +#define CYREG_B1_P5_U1_CFG11 0x40011acb +#define CYREG_B1_P5_U1_CFG12 0x40011acc +#define CYREG_B1_P5_U1_CFG13 0x40011acd +#define CYREG_B1_P5_U1_CFG14 0x40011ace +#define CYREG_B1_P5_U1_CFG15 0x40011acf +#define CYREG_B1_P5_U1_CFG16 0x40011ad0 +#define CYREG_B1_P5_U1_CFG17 0x40011ad1 +#define CYREG_B1_P5_U1_CFG18 0x40011ad2 +#define CYREG_B1_P5_U1_CFG19 0x40011ad3 +#define CYREG_B1_P5_U1_CFG20 0x40011ad4 +#define CYREG_B1_P5_U1_CFG21 0x40011ad5 +#define CYREG_B1_P5_U1_CFG22 0x40011ad6 +#define CYREG_B1_P5_U1_CFG23 0x40011ad7 +#define CYREG_B1_P5_U1_CFG24 0x40011ad8 +#define CYREG_B1_P5_U1_CFG25 0x40011ad9 +#define CYREG_B1_P5_U1_CFG26 0x40011ada +#define CYREG_B1_P5_U1_CFG27 0x40011adb +#define CYREG_B1_P5_U1_CFG28 0x40011adc +#define CYREG_B1_P5_U1_CFG29 0x40011add +#define CYREG_B1_P5_U1_CFG30 0x40011ade +#define CYREG_B1_P5_U1_CFG31 0x40011adf +#define CYREG_B1_P5_U1_DCFG0 0x40011ae0 +#define CYREG_B1_P5_U1_DCFG1 0x40011ae2 +#define CYREG_B1_P5_U1_DCFG2 0x40011ae4 +#define CYREG_B1_P5_U1_DCFG3 0x40011ae6 +#define CYREG_B1_P5_U1_DCFG4 0x40011ae8 +#define CYREG_B1_P5_U1_DCFG5 0x40011aea +#define CYREG_B1_P5_U1_DCFG6 0x40011aec +#define CYREG_B1_P5_U1_DCFG7 0x40011aee +#define CYDEV_UCFG_B1_P5_ROUTE_BASE 0x40011b00 +#define CYDEV_UCFG_B1_P5_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_DSI0_BASE 0x40014000 +#define CYDEV_UCFG_DSI0_SIZE 0x000000ef +#define CYDEV_UCFG_DSI1_BASE 0x40014100 +#define CYDEV_UCFG_DSI1_SIZE 0x000000ef +#define CYDEV_UCFG_DSI2_BASE 0x40014200 +#define CYDEV_UCFG_DSI2_SIZE 0x000000ef +#define CYDEV_UCFG_DSI3_BASE 0x40014300 +#define CYDEV_UCFG_DSI3_SIZE 0x000000ef +#define CYDEV_UCFG_DSI4_BASE 0x40014400 +#define CYDEV_UCFG_DSI4_SIZE 0x000000ef +#define CYDEV_UCFG_DSI5_BASE 0x40014500 +#define CYDEV_UCFG_DSI5_SIZE 0x000000ef +#define CYDEV_UCFG_DSI6_BASE 0x40014600 +#define CYDEV_UCFG_DSI6_SIZE 0x000000ef +#define CYDEV_UCFG_DSI7_BASE 0x40014700 +#define CYDEV_UCFG_DSI7_SIZE 0x000000ef +#define CYDEV_UCFG_DSI8_BASE 0x40014800 +#define CYDEV_UCFG_DSI8_SIZE 0x000000ef +#define CYDEV_UCFG_DSI9_BASE 0x40014900 +#define CYDEV_UCFG_DSI9_SIZE 0x000000ef +#define CYDEV_UCFG_DSI12_BASE 0x40014c00 +#define CYDEV_UCFG_DSI12_SIZE 0x000000ef +#define CYDEV_UCFG_DSI13_BASE 0x40014d00 +#define CYDEV_UCFG_DSI13_SIZE 0x000000ef +#define CYDEV_UCFG_BCTL0_BASE 0x40015000 +#define CYDEV_UCFG_BCTL0_SIZE 0x00000010 +#define CYREG_BCTL0_MDCLK_EN 0x40015000 +#define CYREG_BCTL0_MBCLK_EN 0x40015001 +#define CYREG_BCTL0_WAIT_CFG 0x40015002 +#define CYREG_BCTL0_BANK_CTL 0x40015003 +#define CYREG_BCTL0_UDB_TEST_3 0x40015007 +#define CYREG_BCTL0_DCLK_EN0 0x40015008 +#define CYREG_BCTL0_BCLK_EN0 0x40015009 +#define CYREG_BCTL0_DCLK_EN1 0x4001500a +#define CYREG_BCTL0_BCLK_EN1 0x4001500b +#define CYREG_BCTL0_DCLK_EN2 0x4001500c +#define CYREG_BCTL0_BCLK_EN2 0x4001500d +#define CYREG_BCTL0_DCLK_EN3 0x4001500e +#define CYREG_BCTL0_BCLK_EN3 0x4001500f +#define CYDEV_UCFG_BCTL1_BASE 0x40015010 +#define CYDEV_UCFG_BCTL1_SIZE 0x00000010 +#define CYREG_BCTL1_MDCLK_EN 0x40015010 +#define CYREG_BCTL1_MBCLK_EN 0x40015011 +#define CYREG_BCTL1_WAIT_CFG 0x40015012 +#define CYREG_BCTL1_BANK_CTL 0x40015013 +#define CYREG_BCTL1_UDB_TEST_3 0x40015017 +#define CYREG_BCTL1_DCLK_EN0 0x40015018 +#define CYREG_BCTL1_BCLK_EN0 0x40015019 +#define CYREG_BCTL1_DCLK_EN1 0x4001501a +#define CYREG_BCTL1_BCLK_EN1 0x4001501b +#define CYREG_BCTL1_DCLK_EN2 0x4001501c +#define CYREG_BCTL1_BCLK_EN2 0x4001501d +#define CYREG_BCTL1_DCLK_EN3 0x4001501e +#define CYREG_BCTL1_BCLK_EN3 0x4001501f +#define CYDEV_IDMUX_BASE 0x40015100 +#define CYDEV_IDMUX_SIZE 0x00000016 +#define CYREG_IDMUX_IRQ_CTL0 0x40015100 +#define CYREG_IDMUX_IRQ_CTL1 0x40015101 +#define CYREG_IDMUX_IRQ_CTL2 0x40015102 +#define CYREG_IDMUX_IRQ_CTL3 0x40015103 +#define CYREG_IDMUX_IRQ_CTL4 0x40015104 +#define CYREG_IDMUX_IRQ_CTL5 0x40015105 +#define CYREG_IDMUX_IRQ_CTL6 0x40015106 +#define CYREG_IDMUX_IRQ_CTL7 0x40015107 +#define CYREG_IDMUX_DRQ_CTL0 0x40015110 +#define CYREG_IDMUX_DRQ_CTL1 0x40015111 +#define CYREG_IDMUX_DRQ_CTL2 0x40015112 +#define CYREG_IDMUX_DRQ_CTL3 0x40015113 +#define CYREG_IDMUX_DRQ_CTL4 0x40015114 +#define CYREG_IDMUX_DRQ_CTL5 0x40015115 +#define CYDEV_CACHERAM_BASE 0x40030000 +#define CYDEV_CACHERAM_SIZE 0x00000400 +#define CYREG_CACHERAM_DATA_MBASE 0x40030000 +#define CYREG_CACHERAM_DATA_MSIZE 0x00000400 +#define CYDEV_SFR_BASE 0x40050100 +#define CYDEV_SFR_SIZE 0x000000fb +#define CYREG_SFR_GPIO0 0x40050180 +#define CYREG_SFR_GPIRD0 0x40050189 +#define CYREG_SFR_GPIO0_SEL 0x4005018a +#define CYREG_SFR_GPIO1 0x40050190 +#define CYREG_SFR_GPIRD1 0x40050191 +#define CYREG_SFR_GPIO2 0x40050198 +#define CYREG_SFR_GPIRD2 0x40050199 +#define CYREG_SFR_GPIO2_SEL 0x4005019a +#define CYREG_SFR_GPIO1_SEL 0x400501a2 +#define CYREG_SFR_GPIO3 0x400501b0 +#define CYREG_SFR_GPIRD3 0x400501b1 +#define CYREG_SFR_GPIO3_SEL 0x400501b2 +#define CYREG_SFR_GPIO4 0x400501c0 +#define CYREG_SFR_GPIRD4 0x400501c1 +#define CYREG_SFR_GPIO4_SEL 0x400501c2 +#define CYREG_SFR_GPIO5 0x400501c8 +#define CYREG_SFR_GPIRD5 0x400501c9 +#define CYREG_SFR_GPIO5_SEL 0x400501ca +#define CYREG_SFR_GPIO6 0x400501d8 +#define CYREG_SFR_GPIRD6 0x400501d9 +#define CYREG_SFR_GPIO6_SEL 0x400501da +#define CYREG_SFR_GPIO12 0x400501e8 +#define CYREG_SFR_GPIRD12 0x400501e9 +#define CYREG_SFR_GPIO12_SEL 0x400501f2 +#define CYREG_SFR_GPIO15 0x400501f8 +#define CYREG_SFR_GPIRD15 0x400501f9 +#define CYREG_SFR_GPIO15_SEL 0x400501fa +#define CYDEV_P3BA_BASE 0x40050300 +#define CYDEV_P3BA_SIZE 0x0000002b +#define CYREG_P3BA_Y_START 0x40050300 +#define CYREG_P3BA_YROLL 0x40050301 +#define CYREG_P3BA_YCFG 0x40050302 +#define CYREG_P3BA_X_START1 0x40050303 +#define CYREG_P3BA_X_START2 0x40050304 +#define CYREG_P3BA_XROLL1 0x40050305 +#define CYREG_P3BA_XROLL2 0x40050306 +#define CYREG_P3BA_XINC 0x40050307 +#define CYREG_P3BA_XCFG 0x40050308 +#define CYREG_P3BA_OFFSETADDR1 0x40050309 +#define CYREG_P3BA_OFFSETADDR2 0x4005030a +#define CYREG_P3BA_OFFSETADDR3 0x4005030b +#define CYREG_P3BA_ABSADDR1 0x4005030c +#define CYREG_P3BA_ABSADDR2 0x4005030d +#define CYREG_P3BA_ABSADDR3 0x4005030e +#define CYREG_P3BA_ABSADDR4 0x4005030f +#define CYREG_P3BA_DATCFG1 0x40050310 +#define CYREG_P3BA_DATCFG2 0x40050311 +#define CYREG_P3BA_CMP_RSLT1 0x40050314 +#define CYREG_P3BA_CMP_RSLT2 0x40050315 +#define CYREG_P3BA_CMP_RSLT3 0x40050316 +#define CYREG_P3BA_CMP_RSLT4 0x40050317 +#define CYREG_P3BA_DATA_REG1 0x40050318 +#define CYREG_P3BA_DATA_REG2 0x40050319 +#define CYREG_P3BA_DATA_REG3 0x4005031a +#define CYREG_P3BA_DATA_REG4 0x4005031b +#define CYREG_P3BA_EXP_DATA1 0x4005031c +#define CYREG_P3BA_EXP_DATA2 0x4005031d +#define CYREG_P3BA_EXP_DATA3 0x4005031e +#define CYREG_P3BA_EXP_DATA4 0x4005031f +#define CYREG_P3BA_MSTR_HRDATA1 0x40050320 +#define CYREG_P3BA_MSTR_HRDATA2 0x40050321 +#define CYREG_P3BA_MSTR_HRDATA3 0x40050322 +#define CYREG_P3BA_MSTR_HRDATA4 0x40050323 +#define CYREG_P3BA_BIST_EN 0x40050324 +#define CYREG_P3BA_PHUB_MASTER_SSR 0x40050325 +#define CYREG_P3BA_SEQCFG1 0x40050326 +#define CYREG_P3BA_SEQCFG2 0x40050327 +#define CYREG_P3BA_Y_CURR 0x40050328 +#define CYREG_P3BA_X_CURR1 0x40050329 +#define CYREG_P3BA_X_CURR2 0x4005032a +#define CYDEV_PANTHER_BASE 0x40080000 +#define CYDEV_PANTHER_SIZE 0x00000020 +#define CYREG_PANTHER_STCALIB_CFG 0x40080000 +#define CYREG_PANTHER_WAITPIPE 0x40080004 +#define CYREG_PANTHER_TRACE_CFG 0x40080008 +#define CYREG_PANTHER_DBG_CFG 0x4008000c +#define CYREG_PANTHER_CM3_LCKRST_STAT 0x40080018 +#define CYREG_PANTHER_DEVICE_ID 0x4008001c +#define CYDEV_FLSECC_BASE 0x48000000 +#define CYDEV_FLSECC_SIZE 0x00008000 +#define CYREG_FLSECC_DATA_MBASE 0x48000000 +#define CYREG_FLSECC_DATA_MSIZE 0x00008000 +#define CYDEV_FLSHID_BASE 0x49000000 +#define CYDEV_FLSHID_SIZE 0x00000200 +#define CYREG_FLSHID_RSVD_MBASE 0x49000000 +#define CYREG_FLSHID_RSVD_MSIZE 0x00000080 +#define CYREG_FLSHID_CUST_MDATA_MBASE 0x49000080 +#define CYREG_FLSHID_CUST_MDATA_MSIZE 0x00000080 +#define CYDEV_FLSHID_CUST_TABLES_BASE 0x49000100 +#define CYDEV_FLSHID_CUST_TABLES_SIZE 0x00000040 +#define CYREG_FLSHID_CUST_TABLES_Y_LOC 0x49000100 +#define CYREG_FLSHID_CUST_TABLES_X_LOC 0x49000101 +#define CYREG_FLSHID_CUST_TABLES_WAFER_NUM 0x49000102 +#define CYREG_FLSHID_CUST_TABLES_LOT_LSB 0x49000103 +#define CYREG_FLSHID_CUST_TABLES_LOT_MSB 0x49000104 +#define CYREG_FLSHID_CUST_TABLES_WRK_WK 0x49000105 +#define CYREG_FLSHID_CUST_TABLES_FAB_YR 0x49000106 +#define CYREG_FLSHID_CUST_TABLES_MINOR 0x49000107 +#define CYREG_FLSHID_CUST_TABLES_IMO_3MHZ 0x49000108 +#define CYREG_FLSHID_CUST_TABLES_IMO_6MHZ 0x49000109 +#define CYREG_FLSHID_CUST_TABLES_IMO_12MHZ 0x4900010a +#define CYREG_FLSHID_CUST_TABLES_IMO_24MHZ 0x4900010b +#define CYREG_FLSHID_CUST_TABLES_IMO_67MHZ 0x4900010c +#define CYREG_FLSHID_CUST_TABLES_IMO_80MHZ 0x4900010d +#define CYREG_FLSHID_CUST_TABLES_IMO_92MHZ 0x4900010e +#define CYREG_FLSHID_CUST_TABLES_IMO_USB 0x4900010f +#define CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS 0x49000110 +#define CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS 0x49000111 +#define CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS 0x49000112 +#define CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS 0x49000113 +#define CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS 0x49000114 +#define CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS 0x49000115 +#define CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS 0x49000116 +#define CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS 0x49000117 +#define CYREG_FLSHID_CUST_TABLES_DEC_M1 0x49000118 +#define CYREG_FLSHID_CUST_TABLES_DEC_M2 0x49000119 +#define CYREG_FLSHID_CUST_TABLES_DEC_M3 0x4900011a +#define CYREG_FLSHID_CUST_TABLES_DEC_M4 0x4900011b +#define CYREG_FLSHID_CUST_TABLES_DEC_M5 0x4900011c +#define CYREG_FLSHID_CUST_TABLES_DEC_M6 0x4900011d +#define CYREG_FLSHID_CUST_TABLES_DEC_M7 0x4900011e +#define CYREG_FLSHID_CUST_TABLES_DEC_M8 0x4900011f +#define CYREG_FLSHID_CUST_TABLES_DAC0_M1 0x49000120 +#define CYREG_FLSHID_CUST_TABLES_DAC0_M2 0x49000121 +#define CYREG_FLSHID_CUST_TABLES_DAC0_M3 0x49000122 +#define CYREG_FLSHID_CUST_TABLES_DAC0_M4 0x49000123 +#define CYREG_FLSHID_CUST_TABLES_DAC0_M5 0x49000124 +#define CYREG_FLSHID_CUST_TABLES_DAC0_M6 0x49000125 +#define CYREG_FLSHID_CUST_TABLES_DAC0_M7 0x49000126 +#define CYREG_FLSHID_CUST_TABLES_DAC0_M8 0x49000127 +#define CYREG_FLSHID_CUST_TABLES_DAC2_M1 0x49000128 +#define CYREG_FLSHID_CUST_TABLES_DAC2_M2 0x49000129 +#define CYREG_FLSHID_CUST_TABLES_DAC2_M3 0x4900012a +#define CYREG_FLSHID_CUST_TABLES_DAC2_M4 0x4900012b +#define CYREG_FLSHID_CUST_TABLES_DAC2_M5 0x4900012c +#define CYREG_FLSHID_CUST_TABLES_DAC2_M6 0x4900012d +#define CYREG_FLSHID_CUST_TABLES_DAC2_M7 0x4900012e +#define CYREG_FLSHID_CUST_TABLES_DAC2_M8 0x4900012f +#define CYREG_FLSHID_CUST_TABLES_DAC1_M1 0x49000130 +#define CYREG_FLSHID_CUST_TABLES_DAC1_M2 0x49000131 +#define CYREG_FLSHID_CUST_TABLES_DAC1_M3 0x49000132 +#define CYREG_FLSHID_CUST_TABLES_DAC1_M4 0x49000133 +#define CYREG_FLSHID_CUST_TABLES_DAC1_M5 0x49000134 +#define CYREG_FLSHID_CUST_TABLES_DAC1_M6 0x49000135 +#define CYREG_FLSHID_CUST_TABLES_DAC1_M7 0x49000136 +#define CYREG_FLSHID_CUST_TABLES_DAC1_M8 0x49000137 +#define CYREG_FLSHID_CUST_TABLES_DAC3_M1 0x49000138 +#define CYREG_FLSHID_CUST_TABLES_DAC3_M2 0x49000139 +#define CYREG_FLSHID_CUST_TABLES_DAC3_M3 0x4900013a +#define CYREG_FLSHID_CUST_TABLES_DAC3_M4 0x4900013b +#define CYREG_FLSHID_CUST_TABLES_DAC3_M5 0x4900013c +#define CYREG_FLSHID_CUST_TABLES_DAC3_M6 0x4900013d +#define CYREG_FLSHID_CUST_TABLES_DAC3_M7 0x4900013e +#define CYREG_FLSHID_CUST_TABLES_DAC3_M8 0x4900013f +#define CYDEV_FLSHID_MFG_CFG_BASE 0x49000180 +#define CYDEV_FLSHID_MFG_CFG_SIZE 0x00000080 +#define CYREG_FLSHID_MFG_CFG_IMO_TR1 0x49000188 +#define CYREG_FLSHID_MFG_CFG_CMP0_TR0 0x490001ac +#define CYREG_FLSHID_MFG_CFG_CMP1_TR0 0x490001ae +#define CYREG_FLSHID_MFG_CFG_CMP2_TR0 0x490001b0 +#define CYREG_FLSHID_MFG_CFG_CMP3_TR0 0x490001b2 +#define CYREG_FLSHID_MFG_CFG_CMP0_TR1 0x490001b4 +#define CYREG_FLSHID_MFG_CFG_CMP1_TR1 0x490001b6 +#define CYREG_FLSHID_MFG_CFG_CMP2_TR1 0x490001b8 +#define CYREG_FLSHID_MFG_CFG_CMP3_TR1 0x490001ba +#define CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM 0x490001ce +#define CYDEV_EXTMEM_BASE 0x60000000 +#define CYDEV_EXTMEM_SIZE 0x00800000 +#define CYREG_EXTMEM_DATA_MBASE 0x60000000 +#define CYREG_EXTMEM_DATA_MSIZE 0x00800000 +#define CYDEV_ITM_BASE 0xe0000000 +#define CYDEV_ITM_SIZE 0x00001000 +#define CYREG_ITM_TRACE_EN 0xe0000e00 +#define CYREG_ITM_TRACE_PRIVILEGE 0xe0000e40 +#define CYREG_ITM_TRACE_CTRL 0xe0000e80 +#define CYREG_ITM_LOCK_ACCESS 0xe0000fb0 +#define CYREG_ITM_LOCK_STATUS 0xe0000fb4 +#define CYREG_ITM_PID4 0xe0000fd0 +#define CYREG_ITM_PID5 0xe0000fd4 +#define CYREG_ITM_PID6 0xe0000fd8 +#define CYREG_ITM_PID7 0xe0000fdc +#define CYREG_ITM_PID0 0xe0000fe0 +#define CYREG_ITM_PID1 0xe0000fe4 +#define CYREG_ITM_PID2 0xe0000fe8 +#define CYREG_ITM_PID3 0xe0000fec +#define CYREG_ITM_CID0 0xe0000ff0 +#define CYREG_ITM_CID1 0xe0000ff4 +#define CYREG_ITM_CID2 0xe0000ff8 +#define CYREG_ITM_CID3 0xe0000ffc +#define CYDEV_DWT_BASE 0xe0001000 +#define CYDEV_DWT_SIZE 0x0000005c +#define CYREG_DWT_CTRL 0xe0001000 +#define CYREG_DWT_CYCLE_COUNT 0xe0001004 +#define CYREG_DWT_CPI_COUNT 0xe0001008 +#define CYREG_DWT_EXC_OVHD_COUNT 0xe000100c +#define CYREG_DWT_SLEEP_COUNT 0xe0001010 +#define CYREG_DWT_LSU_COUNT 0xe0001014 +#define CYREG_DWT_FOLD_COUNT 0xe0001018 +#define CYREG_DWT_PC_SAMPLE 0xe000101c +#define CYREG_DWT_COMP_0 0xe0001020 +#define CYREG_DWT_MASK_0 0xe0001024 +#define CYREG_DWT_FUNCTION_0 0xe0001028 +#define CYREG_DWT_COMP_1 0xe0001030 +#define CYREG_DWT_MASK_1 0xe0001034 +#define CYREG_DWT_FUNCTION_1 0xe0001038 +#define CYREG_DWT_COMP_2 0xe0001040 +#define CYREG_DWT_MASK_2 0xe0001044 +#define CYREG_DWT_FUNCTION_2 0xe0001048 +#define CYREG_DWT_COMP_3 0xe0001050 +#define CYREG_DWT_MASK_3 0xe0001054 +#define CYREG_DWT_FUNCTION_3 0xe0001058 +#define CYDEV_FPB_BASE 0xe0002000 +#define CYDEV_FPB_SIZE 0x00001000 +#define CYREG_FPB_CTRL 0xe0002000 +#define CYREG_FPB_REMAP 0xe0002004 +#define CYREG_FPB_FP_COMP_0 0xe0002008 +#define CYREG_FPB_FP_COMP_1 0xe000200c +#define CYREG_FPB_FP_COMP_2 0xe0002010 +#define CYREG_FPB_FP_COMP_3 0xe0002014 +#define CYREG_FPB_FP_COMP_4 0xe0002018 +#define CYREG_FPB_FP_COMP_5 0xe000201c +#define CYREG_FPB_FP_COMP_6 0xe0002020 +#define CYREG_FPB_FP_COMP_7 0xe0002024 +#define CYREG_FPB_PID4 0xe0002fd0 +#define CYREG_FPB_PID5 0xe0002fd4 +#define CYREG_FPB_PID6 0xe0002fd8 +#define CYREG_FPB_PID7 0xe0002fdc +#define CYREG_FPB_PID0 0xe0002fe0 +#define CYREG_FPB_PID1 0xe0002fe4 +#define CYREG_FPB_PID2 0xe0002fe8 +#define CYREG_FPB_PID3 0xe0002fec +#define CYREG_FPB_CID0 0xe0002ff0 +#define CYREG_FPB_CID1 0xe0002ff4 +#define CYREG_FPB_CID2 0xe0002ff8 +#define CYREG_FPB_CID3 0xe0002ffc +#define CYDEV_NVIC_BASE 0xe000e000 +#define CYDEV_NVIC_SIZE 0x00000d3c +#define CYREG_NVIC_INT_CTL_TYPE 0xe000e004 +#define CYREG_NVIC_SYSTICK_CTL 0xe000e010 +#define CYREG_NVIC_SYSTICK_RELOAD 0xe000e014 +#define CYREG_NVIC_SYSTICK_CURRENT 0xe000e018 +#define CYREG_NVIC_SYSTICK_CAL 0xe000e01c +#define CYREG_NVIC_SETENA0 0xe000e100 +#define CYREG_NVIC_CLRENA0 0xe000e180 +#define CYREG_NVIC_SETPEND0 0xe000e200 +#define CYREG_NVIC_CLRPEND0 0xe000e280 +#define CYREG_NVIC_ACTIVE0 0xe000e300 +#define CYREG_NVIC_PRI_0 0xe000e400 +#define CYREG_NVIC_PRI_1 0xe000e401 +#define CYREG_NVIC_PRI_2 0xe000e402 +#define CYREG_NVIC_PRI_3 0xe000e403 +#define CYREG_NVIC_PRI_4 0xe000e404 +#define CYREG_NVIC_PRI_5 0xe000e405 +#define CYREG_NVIC_PRI_6 0xe000e406 +#define CYREG_NVIC_PRI_7 0xe000e407 +#define CYREG_NVIC_PRI_8 0xe000e408 +#define CYREG_NVIC_PRI_9 0xe000e409 +#define CYREG_NVIC_PRI_10 0xe000e40a +#define CYREG_NVIC_PRI_11 0xe000e40b +#define CYREG_NVIC_PRI_12 0xe000e40c +#define CYREG_NVIC_PRI_13 0xe000e40d +#define CYREG_NVIC_PRI_14 0xe000e40e +#define CYREG_NVIC_PRI_15 0xe000e40f +#define CYREG_NVIC_PRI_16 0xe000e410 +#define CYREG_NVIC_PRI_17 0xe000e411 +#define CYREG_NVIC_PRI_18 0xe000e412 +#define CYREG_NVIC_PRI_19 0xe000e413 +#define CYREG_NVIC_PRI_20 0xe000e414 +#define CYREG_NVIC_PRI_21 0xe000e415 +#define CYREG_NVIC_PRI_22 0xe000e416 +#define CYREG_NVIC_PRI_23 0xe000e417 +#define CYREG_NVIC_PRI_24 0xe000e418 +#define CYREG_NVIC_PRI_25 0xe000e419 +#define CYREG_NVIC_PRI_26 0xe000e41a +#define CYREG_NVIC_PRI_27 0xe000e41b +#define CYREG_NVIC_PRI_28 0xe000e41c +#define CYREG_NVIC_PRI_29 0xe000e41d +#define CYREG_NVIC_PRI_30 0xe000e41e +#define CYREG_NVIC_PRI_31 0xe000e41f +#define CYREG_NVIC_CPUID_BASE 0xe000ed00 +#define CYREG_NVIC_INTR_CTRL_STATE 0xe000ed04 +#define CYREG_NVIC_VECT_OFFSET 0xe000ed08 +#define CYREG_NVIC_APPLN_INTR 0xe000ed0c +#define CYREG_NVIC_SYSTEM_CONTROL 0xe000ed10 +#define CYREG_NVIC_CFG_CONTROL 0xe000ed14 +#define CYREG_NVIC_SYS_PRIO_HANDLER_4_7 0xe000ed18 +#define CYREG_NVIC_SYS_PRIO_HANDLER_8_11 0xe000ed1c +#define CYREG_NVIC_SYS_PRIO_HANDLER_12_15 0xe000ed20 +#define CYREG_NVIC_SYS_HANDLER_CSR 0xe000ed24 +#define CYREG_NVIC_MEMMAN_FAULT_STATUS 0xe000ed28 +#define CYREG_NVIC_BUS_FAULT_STATUS 0xe000ed29 +#define CYREG_NVIC_USAGE_FAULT_STATUS 0xe000ed2a +#define CYREG_NVIC_HARD_FAULT_STATUS 0xe000ed2c +#define CYREG_NVIC_DEBUG_FAULT_STATUS 0xe000ed30 +#define CYREG_NVIC_MEMMAN_FAULT_ADD 0xe000ed34 +#define CYREG_NVIC_BUS_FAULT_ADD 0xe000ed38 +#define CYDEV_CORE_DBG_BASE 0xe000edf0 +#define CYDEV_CORE_DBG_SIZE 0x00000010 +#define CYREG_CORE_DBG_DBG_HLT_CS 0xe000edf0 +#define CYREG_CORE_DBG_DBG_REG_SEL 0xe000edf4 +#define CYREG_CORE_DBG_DBG_REG_DATA 0xe000edf8 +#define CYREG_CORE_DBG_EXC_MON_CTL 0xe000edfc +#define CYDEV_TPIU_BASE 0xe0040000 +#define CYDEV_TPIU_SIZE 0x00001000 +#define CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ 0xe0040000 +#define CYREG_TPIU_CURRENT_SYNC_PRT_SZ 0xe0040004 +#define CYREG_TPIU_ASYNC_CLK_PRESCALER 0xe0040010 +#define CYREG_TPIU_PROTOCOL 0xe00400f0 +#define CYREG_TPIU_FORM_FLUSH_STAT 0xe0040300 +#define CYREG_TPIU_FORM_FLUSH_CTRL 0xe0040304 +#define CYREG_TPIU_TRIGGER 0xe0040ee8 +#define CYREG_TPIU_ITETMDATA 0xe0040eec +#define CYREG_TPIU_ITATBCTR2 0xe0040ef0 +#define CYREG_TPIU_ITATBCTR0 0xe0040ef8 +#define CYREG_TPIU_ITITMDATA 0xe0040efc +#define CYREG_TPIU_ITCTRL 0xe0040f00 +#define CYREG_TPIU_DEVID 0xe0040fc8 +#define CYREG_TPIU_DEVTYPE 0xe0040fcc +#define CYREG_TPIU_PID4 0xe0040fd0 +#define CYREG_TPIU_PID5 0xe0040fd4 +#define CYREG_TPIU_PID6 0xe0040fd8 +#define CYREG_TPIU_PID7 0xe0040fdc +#define CYREG_TPIU_PID0 0xe0040fe0 +#define CYREG_TPIU_PID1 0xe0040fe4 +#define CYREG_TPIU_PID2 0xe0040fe8 +#define CYREG_TPIU_PID3 0xe0040fec +#define CYREG_TPIU_CID0 0xe0040ff0 +#define CYREG_TPIU_CID1 0xe0040ff4 +#define CYREG_TPIU_CID2 0xe0040ff8 +#define CYREG_TPIU_CID3 0xe0040ffc +#define CYDEV_ETM_BASE 0xe0041000 +#define CYDEV_ETM_SIZE 0x00001000 +#define CYREG_ETM_CTL 0xe0041000 +#define CYREG_ETM_CFG_CODE 0xe0041004 +#define CYREG_ETM_TRIG_EVENT 0xe0041008 +#define CYREG_ETM_STATUS 0xe0041010 +#define CYREG_ETM_SYS_CFG 0xe0041014 +#define CYREG_ETM_TRACE_ENB_EVENT 0xe0041020 +#define CYREG_ETM_TRACE_EN_CTRL1 0xe0041024 +#define CYREG_ETM_FIFOFULL_LEVEL 0xe004102c +#define CYREG_ETM_SYNC_FREQ 0xe00411e0 +#define CYREG_ETM_ETM_ID 0xe00411e4 +#define CYREG_ETM_CFG_CODE_EXT 0xe00411e8 +#define CYREG_ETM_TR_SS_EMBICE_CTRL 0xe00411f0 +#define CYREG_ETM_CS_TRACE_ID 0xe0041200 +#define CYREG_ETM_OS_LOCK_ACCESS 0xe0041300 +#define CYREG_ETM_OS_LOCK_STATUS 0xe0041304 +#define CYREG_ETM_PDSR 0xe0041314 +#define CYREG_ETM_ITMISCIN 0xe0041ee0 +#define CYREG_ETM_ITTRIGOUT 0xe0041ee8 +#define CYREG_ETM_ITATBCTR2 0xe0041ef0 +#define CYREG_ETM_ITATBCTR0 0xe0041ef8 +#define CYREG_ETM_INT_MODE_CTRL 0xe0041f00 +#define CYREG_ETM_CLM_TAG_SET 0xe0041fa0 +#define CYREG_ETM_CLM_TAG_CLR 0xe0041fa4 +#define CYREG_ETM_LOCK_ACCESS 0xe0041fb0 +#define CYREG_ETM_LOCK_STATUS 0xe0041fb4 +#define CYREG_ETM_AUTH_STATUS 0xe0041fb8 +#define CYREG_ETM_DEV_TYPE 0xe0041fcc +#define CYREG_ETM_PID4 0xe0041fd0 +#define CYREG_ETM_PID5 0xe0041fd4 +#define CYREG_ETM_PID6 0xe0041fd8 +#define CYREG_ETM_PID7 0xe0041fdc +#define CYREG_ETM_PID0 0xe0041fe0 +#define CYREG_ETM_PID1 0xe0041fe4 +#define CYREG_ETM_PID2 0xe0041fe8 +#define CYREG_ETM_PID3 0xe0041fec +#define CYREG_ETM_CID0 0xe0041ff0 +#define CYREG_ETM_CID1 0xe0041ff4 +#define CYREG_ETM_CID2 0xe0041ff8 +#define CYREG_ETM_CID3 0xe0041ffc +#define CYDEV_ROM_TABLE_BASE 0xe00ff000 +#define CYDEV_ROM_TABLE_SIZE 0x00001000 +#define CYREG_ROM_TABLE_NVIC 0xe00ff000 +#define CYREG_ROM_TABLE_DWT 0xe00ff004 +#define CYREG_ROM_TABLE_FPB 0xe00ff008 +#define CYREG_ROM_TABLE_ITM 0xe00ff00c +#define CYREG_ROM_TABLE_TPIU 0xe00ff010 +#define CYREG_ROM_TABLE_ETM 0xe00ff014 +#define CYREG_ROM_TABLE_END 0xe00ff018 +#define CYREG_ROM_TABLE_MEMTYPE 0xe00fffcc +#define CYREG_ROM_TABLE_PID4 0xe00fffd0 +#define CYREG_ROM_TABLE_PID5 0xe00fffd4 +#define CYREG_ROM_TABLE_PID6 0xe00fffd8 +#define CYREG_ROM_TABLE_PID7 0xe00fffdc +#define CYREG_ROM_TABLE_PID0 0xe00fffe0 +#define CYREG_ROM_TABLE_PID1 0xe00fffe4 +#define CYREG_ROM_TABLE_PID2 0xe00fffe8 +#define CYREG_ROM_TABLE_PID3 0xe00fffec +#define CYREG_ROM_TABLE_CID0 0xe00ffff0 +#define CYREG_ROM_TABLE_CID1 0xe00ffff4 +#define CYREG_ROM_TABLE_CID2 0xe00ffff8 +#define CYREG_ROM_TABLE_CID3 0xe00ffffc +#define CYDEV_FLS_SIZE CYDEV_FLASH_SIZE +#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE +#define CYDEV_FLS_SECTOR_SIZE 0x00010000 +#define CYDEV_FLS_ROW_SIZE 0x00000100 +#define CYDEV_ECC_SECTOR_SIZE 0x00002000 +#define CYDEV_ECC_ROW_SIZE 0x00000020 +#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400 +#define CYDEV_EEPROM_ROW_SIZE 0x00000010 +#define CYDEV_PERIPH_BASE CYDEV_CLKDIST_BASE +#define CYCLK_LD_DISABLE 0x00000004 +#define CYCLK_LD_SYNC_EN 0x00000002 +#define CYCLK_LD_LOAD 0x00000001 +#define CYCLK_PIPE 0x00000080 +#define CYCLK_SSS 0x00000040 +#define CYCLK_EARLY 0x00000020 +#define CYCLK_DUTY 0x00000010 +#define CYCLK_SYNC 0x00000008 +#define CYCLK_SRC_SEL_CLK_SYNC_D 0 +#define CYCLK_SRC_SEL_SYNC_DIG 0 +#define CYCLK_SRC_SEL_IMO 1 +#define CYCLK_SRC_SEL_XTAL_MHZ 2 +#define CYCLK_SRC_SEL_XTALM 2 +#define CYCLK_SRC_SEL_ILO 3 +#define CYCLK_SRC_SEL_PLL 4 +#define CYCLK_SRC_SEL_XTAL_KHZ 5 +#define CYCLK_SRC_SEL_XTALK 5 +#define CYCLK_SRC_SEL_DSI_G 6 +#define CYCLK_SRC_SEL_DSI_D 7 +#define CYCLK_SRC_SEL_CLK_SYNC_A 0 +#define CYCLK_SRC_SEL_DSI_A 7 diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydevicerv.inc b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydevicerv.inc new file mode 100755 index 00000000..b5f7a51f --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydevicerv.inc @@ -0,0 +1,16039 @@ +; +; FILENAME: cydevicerv.inc +; OBSOLETE: Do not use this file. Use the _trm version instead. +; PSoC Creator 3.0 Component Pack 7 +; +; DESCRIPTION: +; This file provides all of the address values for the entire PSoC device. +; +;------------------------------------------------------------------------------- +; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + + IF :LNOT::DEF:CYDEV_FLASH_BASE +CYDEV_FLASH_BASE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLASH_SIZE +CYDEV_FLASH_SIZE EQU 0x00020000 + ENDIF + IF :LNOT::DEF:CYDEV_FLASH_DATA_MBASE +CYDEV_FLASH_DATA_MBASE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLASH_DATA_MSIZE +CYDEV_FLASH_DATA_MSIZE EQU 0x00020000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_BASE +CYDEV_SRAM_BASE EQU 0x1fffc000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_SIZE +CYDEV_SRAM_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE64K_MBASE +CYDEV_SRAM_CODE64K_MBASE EQU 0x1fff8000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE64K_MSIZE +CYDEV_SRAM_CODE64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE32K_MBASE +CYDEV_SRAM_CODE32K_MBASE EQU 0x1fffc000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE32K_MSIZE +CYDEV_SRAM_CODE32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE16K_MBASE +CYDEV_SRAM_CODE16K_MBASE EQU 0x1fffe000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE16K_MSIZE +CYDEV_SRAM_CODE16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE_MBASE +CYDEV_SRAM_CODE_MBASE EQU 0x1fffc000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE_MSIZE +CYDEV_SRAM_CODE_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA_MBASE +CYDEV_SRAM_DATA_MBASE EQU 0x20000000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA_MSIZE +CYDEV_SRAM_DATA_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA16K_MBASE +CYDEV_SRAM_DATA16K_MBASE EQU 0x20001000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA16K_MSIZE +CYDEV_SRAM_DATA16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA32K_MBASE +CYDEV_SRAM_DATA32K_MBASE EQU 0x20002000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA32K_MSIZE +CYDEV_SRAM_DATA32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA64K_MBASE +CYDEV_SRAM_DATA64K_MBASE EQU 0x20004000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA64K_MSIZE +CYDEV_SRAM_DATA64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_BASE +CYDEV_DMA_BASE EQU 0x20008000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SIZE +CYDEV_DMA_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM64K_MBASE +CYDEV_DMA_SRAM64K_MBASE EQU 0x20008000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM64K_MSIZE +CYDEV_DMA_SRAM64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM32K_MBASE +CYDEV_DMA_SRAM32K_MBASE EQU 0x2000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM32K_MSIZE +CYDEV_DMA_SRAM32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM16K_MBASE +CYDEV_DMA_SRAM16K_MBASE EQU 0x2000e000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM16K_MSIZE +CYDEV_DMA_SRAM16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM_MBASE +CYDEV_DMA_SRAM_MBASE EQU 0x2000f000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM_MSIZE +CYDEV_DMA_SRAM_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_BASE +CYDEV_CLKDIST_BASE EQU 0x40004000 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_SIZE +CYDEV_CLKDIST_SIZE EQU 0x00000110 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_CR +CYDEV_CLKDIST_CR EQU 0x40004000 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_LD +CYDEV_CLKDIST_LD EQU 0x40004001 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_WRK0 +CYDEV_CLKDIST_WRK0 EQU 0x40004002 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_WRK1 +CYDEV_CLKDIST_WRK1 EQU 0x40004003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_MSTR0 +CYDEV_CLKDIST_MSTR0 EQU 0x40004004 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_MSTR1 +CYDEV_CLKDIST_MSTR1 EQU 0x40004005 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_BCFG0 +CYDEV_CLKDIST_BCFG0 EQU 0x40004006 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_BCFG1 +CYDEV_CLKDIST_BCFG1 EQU 0x40004007 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_BCFG2 +CYDEV_CLKDIST_BCFG2 EQU 0x40004008 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_UCFG +CYDEV_CLKDIST_UCFG EQU 0x40004009 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DLY0 +CYDEV_CLKDIST_DLY0 EQU 0x4000400a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DLY1 +CYDEV_CLKDIST_DLY1 EQU 0x4000400b + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DMASK +CYDEV_CLKDIST_DMASK EQU 0x40004010 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_AMASK +CYDEV_CLKDIST_AMASK EQU 0x40004014 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_BASE +CYDEV_CLKDIST_DCFG0_BASE EQU 0x40004080 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_SIZE +CYDEV_CLKDIST_DCFG0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_CFG0 +CYDEV_CLKDIST_DCFG0_CFG0 EQU 0x40004080 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_CFG1 +CYDEV_CLKDIST_DCFG0_CFG1 EQU 0x40004081 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_CFG2 +CYDEV_CLKDIST_DCFG0_CFG2 EQU 0x40004082 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_BASE +CYDEV_CLKDIST_DCFG1_BASE EQU 0x40004084 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_SIZE +CYDEV_CLKDIST_DCFG1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_CFG0 +CYDEV_CLKDIST_DCFG1_CFG0 EQU 0x40004084 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_CFG1 +CYDEV_CLKDIST_DCFG1_CFG1 EQU 0x40004085 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_CFG2 +CYDEV_CLKDIST_DCFG1_CFG2 EQU 0x40004086 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_BASE +CYDEV_CLKDIST_DCFG2_BASE EQU 0x40004088 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_SIZE +CYDEV_CLKDIST_DCFG2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_CFG0 +CYDEV_CLKDIST_DCFG2_CFG0 EQU 0x40004088 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_CFG1 +CYDEV_CLKDIST_DCFG2_CFG1 EQU 0x40004089 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_CFG2 +CYDEV_CLKDIST_DCFG2_CFG2 EQU 0x4000408a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_BASE +CYDEV_CLKDIST_DCFG3_BASE EQU 0x4000408c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_SIZE +CYDEV_CLKDIST_DCFG3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_CFG0 +CYDEV_CLKDIST_DCFG3_CFG0 EQU 0x4000408c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_CFG1 +CYDEV_CLKDIST_DCFG3_CFG1 EQU 0x4000408d + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_CFG2 +CYDEV_CLKDIST_DCFG3_CFG2 EQU 0x4000408e + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_BASE +CYDEV_CLKDIST_DCFG4_BASE EQU 0x40004090 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_SIZE +CYDEV_CLKDIST_DCFG4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_CFG0 +CYDEV_CLKDIST_DCFG4_CFG0 EQU 0x40004090 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_CFG1 +CYDEV_CLKDIST_DCFG4_CFG1 EQU 0x40004091 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_CFG2 +CYDEV_CLKDIST_DCFG4_CFG2 EQU 0x40004092 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_BASE +CYDEV_CLKDIST_DCFG5_BASE EQU 0x40004094 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_SIZE +CYDEV_CLKDIST_DCFG5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_CFG0 +CYDEV_CLKDIST_DCFG5_CFG0 EQU 0x40004094 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_CFG1 +CYDEV_CLKDIST_DCFG5_CFG1 EQU 0x40004095 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_CFG2 +CYDEV_CLKDIST_DCFG5_CFG2 EQU 0x40004096 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_BASE +CYDEV_CLKDIST_DCFG6_BASE EQU 0x40004098 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_SIZE +CYDEV_CLKDIST_DCFG6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_CFG0 +CYDEV_CLKDIST_DCFG6_CFG0 EQU 0x40004098 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_CFG1 +CYDEV_CLKDIST_DCFG6_CFG1 EQU 0x40004099 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_CFG2 +CYDEV_CLKDIST_DCFG6_CFG2 EQU 0x4000409a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_BASE +CYDEV_CLKDIST_DCFG7_BASE EQU 0x4000409c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_SIZE +CYDEV_CLKDIST_DCFG7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_CFG0 +CYDEV_CLKDIST_DCFG7_CFG0 EQU 0x4000409c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_CFG1 +CYDEV_CLKDIST_DCFG7_CFG1 EQU 0x4000409d + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_CFG2 +CYDEV_CLKDIST_DCFG7_CFG2 EQU 0x4000409e + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_BASE +CYDEV_CLKDIST_ACFG0_BASE EQU 0x40004100 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_SIZE +CYDEV_CLKDIST_ACFG0_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_CFG0 +CYDEV_CLKDIST_ACFG0_CFG0 EQU 0x40004100 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_CFG1 +CYDEV_CLKDIST_ACFG0_CFG1 EQU 0x40004101 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_CFG2 +CYDEV_CLKDIST_ACFG0_CFG2 EQU 0x40004102 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_CFG3 +CYDEV_CLKDIST_ACFG0_CFG3 EQU 0x40004103 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_BASE +CYDEV_CLKDIST_ACFG1_BASE EQU 0x40004104 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_SIZE +CYDEV_CLKDIST_ACFG1_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_CFG0 +CYDEV_CLKDIST_ACFG1_CFG0 EQU 0x40004104 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_CFG1 +CYDEV_CLKDIST_ACFG1_CFG1 EQU 0x40004105 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_CFG2 +CYDEV_CLKDIST_ACFG1_CFG2 EQU 0x40004106 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_CFG3 +CYDEV_CLKDIST_ACFG1_CFG3 EQU 0x40004107 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_BASE +CYDEV_CLKDIST_ACFG2_BASE EQU 0x40004108 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_SIZE +CYDEV_CLKDIST_ACFG2_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_CFG0 +CYDEV_CLKDIST_ACFG2_CFG0 EQU 0x40004108 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_CFG1 +CYDEV_CLKDIST_ACFG2_CFG1 EQU 0x40004109 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_CFG2 +CYDEV_CLKDIST_ACFG2_CFG2 EQU 0x4000410a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_CFG3 +CYDEV_CLKDIST_ACFG2_CFG3 EQU 0x4000410b + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_BASE +CYDEV_CLKDIST_ACFG3_BASE EQU 0x4000410c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_SIZE +CYDEV_CLKDIST_ACFG3_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_CFG0 +CYDEV_CLKDIST_ACFG3_CFG0 EQU 0x4000410c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_CFG1 +CYDEV_CLKDIST_ACFG3_CFG1 EQU 0x4000410d + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_CFG2 +CYDEV_CLKDIST_ACFG3_CFG2 EQU 0x4000410e + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_CFG3 +CYDEV_CLKDIST_ACFG3_CFG3 EQU 0x4000410f + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_BASE +CYDEV_FASTCLK_BASE EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_SIZE +CYDEV_FASTCLK_SIZE EQU 0x00000026 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_IMO_BASE +CYDEV_FASTCLK_IMO_BASE EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_IMO_SIZE +CYDEV_FASTCLK_IMO_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_IMO_CR +CYDEV_FASTCLK_IMO_CR EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_BASE +CYDEV_FASTCLK_XMHZ_BASE EQU 0x40004210 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_SIZE +CYDEV_FASTCLK_XMHZ_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_CSR +CYDEV_FASTCLK_XMHZ_CSR EQU 0x40004210 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_CFG0 +CYDEV_FASTCLK_XMHZ_CFG0 EQU 0x40004212 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_CFG1 +CYDEV_FASTCLK_XMHZ_CFG1 EQU 0x40004213 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_BASE +CYDEV_FASTCLK_PLL_BASE EQU 0x40004220 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_SIZE +CYDEV_FASTCLK_PLL_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_CFG0 +CYDEV_FASTCLK_PLL_CFG0 EQU 0x40004220 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_CFG1 +CYDEV_FASTCLK_PLL_CFG1 EQU 0x40004221 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_P +CYDEV_FASTCLK_PLL_P EQU 0x40004222 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_Q +CYDEV_FASTCLK_PLL_Q EQU 0x40004223 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_SR +CYDEV_FASTCLK_PLL_SR EQU 0x40004225 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_BASE +CYDEV_SLOWCLK_BASE EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_SIZE +CYDEV_SLOWCLK_SIZE EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_BASE +CYDEV_SLOWCLK_ILO_BASE EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_SIZE +CYDEV_SLOWCLK_ILO_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_CR0 +CYDEV_SLOWCLK_ILO_CR0 EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_CR1 +CYDEV_SLOWCLK_ILO_CR1 EQU 0x40004301 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_BASE +CYDEV_SLOWCLK_X32_BASE EQU 0x40004308 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_SIZE +CYDEV_SLOWCLK_X32_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_CR +CYDEV_SLOWCLK_X32_CR EQU 0x40004308 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_CFG +CYDEV_SLOWCLK_X32_CFG EQU 0x40004309 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_TST +CYDEV_SLOWCLK_X32_TST EQU 0x4000430a + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_BASE +CYDEV_BOOST_BASE EQU 0x40004320 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_SIZE +CYDEV_BOOST_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_CR0 +CYDEV_BOOST_CR0 EQU 0x40004320 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_CR1 +CYDEV_BOOST_CR1 EQU 0x40004321 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_CR2 +CYDEV_BOOST_CR2 EQU 0x40004322 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_CR3 +CYDEV_BOOST_CR3 EQU 0x40004323 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_SR +CYDEV_BOOST_SR EQU 0x40004324 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_CR4 +CYDEV_BOOST_CR4 EQU 0x40004325 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_SR2 +CYDEV_BOOST_SR2 EQU 0x40004326 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_BASE +CYDEV_PWRSYS_BASE EQU 0x40004330 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_SIZE +CYDEV_PWRSYS_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_CR0 +CYDEV_PWRSYS_CR0 EQU 0x40004330 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_CR1 +CYDEV_PWRSYS_CR1 EQU 0x40004331 + ENDIF + IF :LNOT::DEF:CYDEV_PM_BASE +CYDEV_PM_BASE EQU 0x40004380 + ENDIF + IF :LNOT::DEF:CYDEV_PM_SIZE +CYDEV_PM_SIZE EQU 0x00000057 + ENDIF + IF :LNOT::DEF:CYDEV_PM_TW_CFG0 +CYDEV_PM_TW_CFG0 EQU 0x40004380 + ENDIF + IF :LNOT::DEF:CYDEV_PM_TW_CFG1 +CYDEV_PM_TW_CFG1 EQU 0x40004381 + ENDIF + IF :LNOT::DEF:CYDEV_PM_TW_CFG2 +CYDEV_PM_TW_CFG2 EQU 0x40004382 + ENDIF + IF :LNOT::DEF:CYDEV_PM_WDT_CFG +CYDEV_PM_WDT_CFG EQU 0x40004383 + ENDIF + IF :LNOT::DEF:CYDEV_PM_WDT_CR +CYDEV_PM_WDT_CR EQU 0x40004384 + ENDIF + IF :LNOT::DEF:CYDEV_PM_INT_SR +CYDEV_PM_INT_SR EQU 0x40004390 + ENDIF + IF :LNOT::DEF:CYDEV_PM_MODE_CFG0 +CYDEV_PM_MODE_CFG0 EQU 0x40004391 + ENDIF + IF :LNOT::DEF:CYDEV_PM_MODE_CFG1 +CYDEV_PM_MODE_CFG1 EQU 0x40004392 + ENDIF + IF :LNOT::DEF:CYDEV_PM_MODE_CSR +CYDEV_PM_MODE_CSR EQU 0x40004393 + ENDIF + IF :LNOT::DEF:CYDEV_PM_USB_CR0 +CYDEV_PM_USB_CR0 EQU 0x40004394 + ENDIF + IF :LNOT::DEF:CYDEV_PM_WAKEUP_CFG0 +CYDEV_PM_WAKEUP_CFG0 EQU 0x40004398 + ENDIF + IF :LNOT::DEF:CYDEV_PM_WAKEUP_CFG1 +CYDEV_PM_WAKEUP_CFG1 EQU 0x40004399 + ENDIF + IF :LNOT::DEF:CYDEV_PM_WAKEUP_CFG2 +CYDEV_PM_WAKEUP_CFG2 EQU 0x4000439a + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_BASE +CYDEV_PM_ACT_BASE EQU 0x400043a0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_SIZE +CYDEV_PM_ACT_SIZE EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG0 +CYDEV_PM_ACT_CFG0 EQU 0x400043a0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG1 +CYDEV_PM_ACT_CFG1 EQU 0x400043a1 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG2 +CYDEV_PM_ACT_CFG2 EQU 0x400043a2 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG3 +CYDEV_PM_ACT_CFG3 EQU 0x400043a3 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG4 +CYDEV_PM_ACT_CFG4 EQU 0x400043a4 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG5 +CYDEV_PM_ACT_CFG5 EQU 0x400043a5 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG6 +CYDEV_PM_ACT_CFG6 EQU 0x400043a6 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG7 +CYDEV_PM_ACT_CFG7 EQU 0x400043a7 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG8 +CYDEV_PM_ACT_CFG8 EQU 0x400043a8 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG9 +CYDEV_PM_ACT_CFG9 EQU 0x400043a9 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG10 +CYDEV_PM_ACT_CFG10 EQU 0x400043aa + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG11 +CYDEV_PM_ACT_CFG11 EQU 0x400043ab + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG12 +CYDEV_PM_ACT_CFG12 EQU 0x400043ac + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG13 +CYDEV_PM_ACT_CFG13 EQU 0x400043ad + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_BASE +CYDEV_PM_STBY_BASE EQU 0x400043b0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_SIZE +CYDEV_PM_STBY_SIZE EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG0 +CYDEV_PM_STBY_CFG0 EQU 0x400043b0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG1 +CYDEV_PM_STBY_CFG1 EQU 0x400043b1 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG2 +CYDEV_PM_STBY_CFG2 EQU 0x400043b2 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG3 +CYDEV_PM_STBY_CFG3 EQU 0x400043b3 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG4 +CYDEV_PM_STBY_CFG4 EQU 0x400043b4 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG5 +CYDEV_PM_STBY_CFG5 EQU 0x400043b5 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG6 +CYDEV_PM_STBY_CFG6 EQU 0x400043b6 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG7 +CYDEV_PM_STBY_CFG7 EQU 0x400043b7 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG8 +CYDEV_PM_STBY_CFG8 EQU 0x400043b8 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG9 +CYDEV_PM_STBY_CFG9 EQU 0x400043b9 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG10 +CYDEV_PM_STBY_CFG10 EQU 0x400043ba + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG11 +CYDEV_PM_STBY_CFG11 EQU 0x400043bb + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG12 +CYDEV_PM_STBY_CFG12 EQU 0x400043bc + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG13 +CYDEV_PM_STBY_CFG13 EQU 0x400043bd + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_BASE +CYDEV_PM_AVAIL_BASE EQU 0x400043c0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SIZE +CYDEV_PM_AVAIL_SIZE EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR0 +CYDEV_PM_AVAIL_CR0 EQU 0x400043c0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR1 +CYDEV_PM_AVAIL_CR1 EQU 0x400043c1 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR2 +CYDEV_PM_AVAIL_CR2 EQU 0x400043c2 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR3 +CYDEV_PM_AVAIL_CR3 EQU 0x400043c3 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR4 +CYDEV_PM_AVAIL_CR4 EQU 0x400043c4 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR5 +CYDEV_PM_AVAIL_CR5 EQU 0x400043c5 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR6 +CYDEV_PM_AVAIL_CR6 EQU 0x400043c6 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR0 +CYDEV_PM_AVAIL_SR0 EQU 0x400043d0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR1 +CYDEV_PM_AVAIL_SR1 EQU 0x400043d1 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR2 +CYDEV_PM_AVAIL_SR2 EQU 0x400043d2 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR3 +CYDEV_PM_AVAIL_SR3 EQU 0x400043d3 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR4 +CYDEV_PM_AVAIL_SR4 EQU 0x400043d4 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR5 +CYDEV_PM_AVAIL_SR5 EQU 0x400043d5 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR6 +CYDEV_PM_AVAIL_SR6 EQU 0x400043d6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_BASE +CYDEV_PICU_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SIZE +CYDEV_PICU_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_BASE +CYDEV_PICU_INTTYPE_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_SIZE +CYDEV_PICU_INTTYPE_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_BASE +CYDEV_PICU_INTTYPE_PICU0_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_SIZE +CYDEV_PICU_INTTYPE_PICU0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE0 EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE1 EQU 0x40004501 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE2 EQU 0x40004502 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE3 EQU 0x40004503 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE4 EQU 0x40004504 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE5 EQU 0x40004505 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE6 EQU 0x40004506 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE7 EQU 0x40004507 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_BASE +CYDEV_PICU_INTTYPE_PICU1_BASE EQU 0x40004508 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_SIZE +CYDEV_PICU_INTTYPE_PICU1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE0 EQU 0x40004508 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE1 EQU 0x40004509 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE2 EQU 0x4000450a + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE3 EQU 0x4000450b + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE4 EQU 0x4000450c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE5 EQU 0x4000450d + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE6 EQU 0x4000450e + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE7 EQU 0x4000450f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_BASE +CYDEV_PICU_INTTYPE_PICU2_BASE EQU 0x40004510 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_SIZE +CYDEV_PICU_INTTYPE_PICU2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE0 EQU 0x40004510 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE1 EQU 0x40004511 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE2 EQU 0x40004512 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE3 EQU 0x40004513 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE4 EQU 0x40004514 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE5 EQU 0x40004515 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE6 EQU 0x40004516 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE7 EQU 0x40004517 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_BASE +CYDEV_PICU_INTTYPE_PICU3_BASE EQU 0x40004518 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_SIZE +CYDEV_PICU_INTTYPE_PICU3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE0 EQU 0x40004518 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE1 EQU 0x40004519 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE2 EQU 0x4000451a + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE3 EQU 0x4000451b + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE4 EQU 0x4000451c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE5 EQU 0x4000451d + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE6 EQU 0x4000451e + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE7 EQU 0x4000451f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_BASE +CYDEV_PICU_INTTYPE_PICU4_BASE EQU 0x40004520 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_SIZE +CYDEV_PICU_INTTYPE_PICU4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE0 EQU 0x40004520 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE1 EQU 0x40004521 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE2 EQU 0x40004522 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE3 EQU 0x40004523 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE4 EQU 0x40004524 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE5 EQU 0x40004525 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE6 EQU 0x40004526 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE7 EQU 0x40004527 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_BASE +CYDEV_PICU_INTTYPE_PICU5_BASE EQU 0x40004528 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_SIZE +CYDEV_PICU_INTTYPE_PICU5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE0 EQU 0x40004528 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE1 EQU 0x40004529 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE2 EQU 0x4000452a + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE3 EQU 0x4000452b + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE4 EQU 0x4000452c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE5 EQU 0x4000452d + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE6 EQU 0x4000452e + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE7 EQU 0x4000452f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_BASE +CYDEV_PICU_INTTYPE_PICU6_BASE EQU 0x40004530 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_SIZE +CYDEV_PICU_INTTYPE_PICU6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE0 EQU 0x40004530 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE1 EQU 0x40004531 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE2 EQU 0x40004532 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE3 EQU 0x40004533 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE4 EQU 0x40004534 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE5 EQU 0x40004535 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE6 EQU 0x40004536 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE7 EQU 0x40004537 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_BASE +CYDEV_PICU_INTTYPE_PICU12_BASE EQU 0x40004560 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_SIZE +CYDEV_PICU_INTTYPE_PICU12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE0 EQU 0x40004560 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE1 EQU 0x40004561 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE2 EQU 0x40004562 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE3 EQU 0x40004563 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE4 EQU 0x40004564 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE5 EQU 0x40004565 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE6 EQU 0x40004566 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE7 EQU 0x40004567 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_BASE +CYDEV_PICU_INTTYPE_PICU15_BASE EQU 0x40004578 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_SIZE +CYDEV_PICU_INTTYPE_PICU15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE0 EQU 0x40004578 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE1 EQU 0x40004579 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE2 EQU 0x4000457a + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE3 EQU 0x4000457b + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE4 EQU 0x4000457c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE5 EQU 0x4000457d + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE6 EQU 0x4000457e + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE7 EQU 0x4000457f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_BASE +CYDEV_PICU_STAT_BASE EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_SIZE +CYDEV_PICU_STAT_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_BASE +CYDEV_PICU_STAT_PICU0_BASE EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_SIZE +CYDEV_PICU_STAT_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_INTSTAT +CYDEV_PICU_STAT_PICU0_INTSTAT EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_BASE +CYDEV_PICU_STAT_PICU1_BASE EQU 0x40004581 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_SIZE +CYDEV_PICU_STAT_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_INTSTAT +CYDEV_PICU_STAT_PICU1_INTSTAT EQU 0x40004581 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_BASE +CYDEV_PICU_STAT_PICU2_BASE EQU 0x40004582 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_SIZE +CYDEV_PICU_STAT_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_INTSTAT +CYDEV_PICU_STAT_PICU2_INTSTAT EQU 0x40004582 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_BASE +CYDEV_PICU_STAT_PICU3_BASE EQU 0x40004583 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_SIZE +CYDEV_PICU_STAT_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_INTSTAT +CYDEV_PICU_STAT_PICU3_INTSTAT EQU 0x40004583 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_BASE +CYDEV_PICU_STAT_PICU4_BASE EQU 0x40004584 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_SIZE +CYDEV_PICU_STAT_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_INTSTAT +CYDEV_PICU_STAT_PICU4_INTSTAT EQU 0x40004584 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_BASE +CYDEV_PICU_STAT_PICU5_BASE EQU 0x40004585 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_SIZE +CYDEV_PICU_STAT_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_INTSTAT +CYDEV_PICU_STAT_PICU5_INTSTAT EQU 0x40004585 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_BASE +CYDEV_PICU_STAT_PICU6_BASE EQU 0x40004586 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_SIZE +CYDEV_PICU_STAT_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_INTSTAT +CYDEV_PICU_STAT_PICU6_INTSTAT EQU 0x40004586 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_BASE +CYDEV_PICU_STAT_PICU12_BASE EQU 0x4000458c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_SIZE +CYDEV_PICU_STAT_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_INTSTAT +CYDEV_PICU_STAT_PICU12_INTSTAT EQU 0x4000458c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_BASE +CYDEV_PICU_STAT_PICU15_BASE EQU 0x4000458f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_SIZE +CYDEV_PICU_STAT_PICU15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_INTSTAT +CYDEV_PICU_STAT_PICU15_INTSTAT EQU 0x4000458f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_BASE +CYDEV_PICU_SNAP_BASE EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_SIZE +CYDEV_PICU_SNAP_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_BASE +CYDEV_PICU_SNAP_PICU0_BASE EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_SIZE +CYDEV_PICU_SNAP_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_SNAP +CYDEV_PICU_SNAP_PICU0_SNAP EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_BASE +CYDEV_PICU_SNAP_PICU1_BASE EQU 0x40004591 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_SIZE +CYDEV_PICU_SNAP_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_SNAP +CYDEV_PICU_SNAP_PICU1_SNAP EQU 0x40004591 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_BASE +CYDEV_PICU_SNAP_PICU2_BASE EQU 0x40004592 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_SIZE +CYDEV_PICU_SNAP_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_SNAP +CYDEV_PICU_SNAP_PICU2_SNAP EQU 0x40004592 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_BASE +CYDEV_PICU_SNAP_PICU3_BASE EQU 0x40004593 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_SIZE +CYDEV_PICU_SNAP_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_SNAP +CYDEV_PICU_SNAP_PICU3_SNAP EQU 0x40004593 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_BASE +CYDEV_PICU_SNAP_PICU4_BASE EQU 0x40004594 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_SIZE +CYDEV_PICU_SNAP_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_SNAP +CYDEV_PICU_SNAP_PICU4_SNAP EQU 0x40004594 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_BASE +CYDEV_PICU_SNAP_PICU5_BASE EQU 0x40004595 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_SIZE +CYDEV_PICU_SNAP_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_SNAP +CYDEV_PICU_SNAP_PICU5_SNAP EQU 0x40004595 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_BASE +CYDEV_PICU_SNAP_PICU6_BASE EQU 0x40004596 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_SIZE +CYDEV_PICU_SNAP_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_SNAP +CYDEV_PICU_SNAP_PICU6_SNAP EQU 0x40004596 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_BASE +CYDEV_PICU_SNAP_PICU12_BASE EQU 0x4000459c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_SIZE +CYDEV_PICU_SNAP_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_SNAP +CYDEV_PICU_SNAP_PICU12_SNAP EQU 0x4000459c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_BASE +CYDEV_PICU_SNAP_PICU_15_BASE EQU 0x4000459f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_SIZE +CYDEV_PICU_SNAP_PICU_15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_SNAP_15 +CYDEV_PICU_SNAP_PICU_15_SNAP_15 EQU 0x4000459f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_BASE +CYDEV_PICU_DISABLE_COR_BASE EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_SIZE +CYDEV_PICU_DISABLE_COR_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_BASE +CYDEV_PICU_DISABLE_COR_PICU0_BASE EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_SIZE +CYDEV_PICU_DISABLE_COR_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_BASE +CYDEV_PICU_DISABLE_COR_PICU1_BASE EQU 0x400045a1 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_SIZE +CYDEV_PICU_DISABLE_COR_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR EQU 0x400045a1 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_BASE +CYDEV_PICU_DISABLE_COR_PICU2_BASE EQU 0x400045a2 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_SIZE +CYDEV_PICU_DISABLE_COR_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR EQU 0x400045a2 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_BASE +CYDEV_PICU_DISABLE_COR_PICU3_BASE EQU 0x400045a3 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_SIZE +CYDEV_PICU_DISABLE_COR_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR EQU 0x400045a3 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_BASE +CYDEV_PICU_DISABLE_COR_PICU4_BASE EQU 0x400045a4 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_SIZE +CYDEV_PICU_DISABLE_COR_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR EQU 0x400045a4 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_BASE +CYDEV_PICU_DISABLE_COR_PICU5_BASE EQU 0x400045a5 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_SIZE +CYDEV_PICU_DISABLE_COR_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR EQU 0x400045a5 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_BASE +CYDEV_PICU_DISABLE_COR_PICU6_BASE EQU 0x400045a6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_SIZE +CYDEV_PICU_DISABLE_COR_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR EQU 0x400045a6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_BASE +CYDEV_PICU_DISABLE_COR_PICU12_BASE EQU 0x400045ac + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_SIZE +CYDEV_PICU_DISABLE_COR_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR EQU 0x400045ac + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_BASE +CYDEV_PICU_DISABLE_COR_PICU15_BASE EQU 0x400045af + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_SIZE +CYDEV_PICU_DISABLE_COR_PICU15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR EQU 0x400045af + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_BASE +CYDEV_MFGCFG_BASE EQU 0x40004600 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_SIZE +CYDEV_MFGCFG_SIZE EQU 0x000000ed + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_BASE +CYDEV_MFGCFG_ANAIF_BASE EQU 0x40004600 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SIZE +CYDEV_MFGCFG_ANAIF_SIZE EQU 0x00000038 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_BASE +CYDEV_MFGCFG_ANAIF_DAC0_BASE EQU 0x40004608 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_SIZE +CYDEV_MFGCFG_ANAIF_DAC0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_TR +CYDEV_MFGCFG_ANAIF_DAC0_TR EQU 0x40004608 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_BASE +CYDEV_MFGCFG_ANAIF_DAC1_BASE EQU 0x40004609 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_SIZE +CYDEV_MFGCFG_ANAIF_DAC1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_TR +CYDEV_MFGCFG_ANAIF_DAC1_TR EQU 0x40004609 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_BASE +CYDEV_MFGCFG_ANAIF_DAC2_BASE EQU 0x4000460a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_SIZE +CYDEV_MFGCFG_ANAIF_DAC2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_TR +CYDEV_MFGCFG_ANAIF_DAC2_TR EQU 0x4000460a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_BASE +CYDEV_MFGCFG_ANAIF_DAC3_BASE EQU 0x4000460b + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_SIZE +CYDEV_MFGCFG_ANAIF_DAC3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_TR +CYDEV_MFGCFG_ANAIF_DAC3_TR EQU 0x4000460b + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE EQU 0x40004610 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0 +CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0 EQU 0x40004610 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE EQU 0x40004611 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0 +CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0 EQU 0x40004611 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE EQU 0x40004612 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0 +CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0 EQU 0x40004612 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_BASE +CYDEV_MFGCFG_ANAIF_SAR0_BASE EQU 0x40004614 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_SIZE +CYDEV_MFGCFG_ANAIF_SAR0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_TR0 +CYDEV_MFGCFG_ANAIF_SAR0_TR0 EQU 0x40004614 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_BASE +CYDEV_MFGCFG_ANAIF_SAR1_BASE EQU 0x40004616 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_SIZE +CYDEV_MFGCFG_ANAIF_SAR1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_TR0 +CYDEV_MFGCFG_ANAIF_SAR1_TR0 EQU 0x40004616 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_BASE +CYDEV_MFGCFG_ANAIF_OPAMP0_BASE EQU 0x40004620 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_TR0 +CYDEV_MFGCFG_ANAIF_OPAMP0_TR0 EQU 0x40004620 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_TR1 +CYDEV_MFGCFG_ANAIF_OPAMP0_TR1 EQU 0x40004621 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_BASE +CYDEV_MFGCFG_ANAIF_OPAMP1_BASE EQU 0x40004622 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_TR0 +CYDEV_MFGCFG_ANAIF_OPAMP1_TR0 EQU 0x40004622 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_TR1 +CYDEV_MFGCFG_ANAIF_OPAMP1_TR1 EQU 0x40004623 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_BASE +CYDEV_MFGCFG_ANAIF_OPAMP2_BASE EQU 0x40004624 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_TR0 +CYDEV_MFGCFG_ANAIF_OPAMP2_TR0 EQU 0x40004624 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_TR1 +CYDEV_MFGCFG_ANAIF_OPAMP2_TR1 EQU 0x40004625 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_BASE +CYDEV_MFGCFG_ANAIF_OPAMP3_BASE EQU 0x40004626 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_TR0 +CYDEV_MFGCFG_ANAIF_OPAMP3_TR0 EQU 0x40004626 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_TR1 +CYDEV_MFGCFG_ANAIF_OPAMP3_TR1 EQU 0x40004627 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_BASE +CYDEV_MFGCFG_ANAIF_CMP0_BASE EQU 0x40004630 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_SIZE +CYDEV_MFGCFG_ANAIF_CMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_TR0 +CYDEV_MFGCFG_ANAIF_CMP0_TR0 EQU 0x40004630 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_TR1 +CYDEV_MFGCFG_ANAIF_CMP0_TR1 EQU 0x40004631 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_BASE +CYDEV_MFGCFG_ANAIF_CMP1_BASE EQU 0x40004632 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_SIZE +CYDEV_MFGCFG_ANAIF_CMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_TR0 +CYDEV_MFGCFG_ANAIF_CMP1_TR0 EQU 0x40004632 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_TR1 +CYDEV_MFGCFG_ANAIF_CMP1_TR1 EQU 0x40004633 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_BASE +CYDEV_MFGCFG_ANAIF_CMP2_BASE EQU 0x40004634 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_SIZE +CYDEV_MFGCFG_ANAIF_CMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_TR0 +CYDEV_MFGCFG_ANAIF_CMP2_TR0 EQU 0x40004634 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_TR1 +CYDEV_MFGCFG_ANAIF_CMP2_TR1 EQU 0x40004635 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_BASE +CYDEV_MFGCFG_ANAIF_CMP3_BASE EQU 0x40004636 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_SIZE +CYDEV_MFGCFG_ANAIF_CMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_TR0 +CYDEV_MFGCFG_ANAIF_CMP3_TR0 EQU 0x40004636 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_TR1 +CYDEV_MFGCFG_ANAIF_CMP3_TR1 EQU 0x40004637 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BASE +CYDEV_MFGCFG_PWRSYS_BASE EQU 0x40004680 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_SIZE +CYDEV_MFGCFG_PWRSYS_SIZE EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_HIB_TR0 +CYDEV_MFGCFG_PWRSYS_HIB_TR0 EQU 0x40004680 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_HIB_TR1 +CYDEV_MFGCFG_PWRSYS_HIB_TR1 EQU 0x40004681 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_I2C_TR +CYDEV_MFGCFG_PWRSYS_I2C_TR EQU 0x40004682 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_SLP_TR +CYDEV_MFGCFG_PWRSYS_SLP_TR EQU 0x40004683 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BUZZ_TR +CYDEV_MFGCFG_PWRSYS_BUZZ_TR EQU 0x40004684 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_WAKE_TR0 +CYDEV_MFGCFG_PWRSYS_WAKE_TR0 EQU 0x40004685 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_WAKE_TR1 +CYDEV_MFGCFG_PWRSYS_WAKE_TR1 EQU 0x40004686 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BREF_TR +CYDEV_MFGCFG_PWRSYS_BREF_TR EQU 0x40004687 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BG_TR +CYDEV_MFGCFG_PWRSYS_BG_TR EQU 0x40004688 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_WAKE_TR2 +CYDEV_MFGCFG_PWRSYS_WAKE_TR2 EQU 0x40004689 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_WAKE_TR3 +CYDEV_MFGCFG_PWRSYS_WAKE_TR3 EQU 0x4000468a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_BASE +CYDEV_MFGCFG_ILO_BASE EQU 0x40004690 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_SIZE +CYDEV_MFGCFG_ILO_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_TR0 +CYDEV_MFGCFG_ILO_TR0 EQU 0x40004690 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_TR1 +CYDEV_MFGCFG_ILO_TR1 EQU 0x40004691 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_X32_BASE +CYDEV_MFGCFG_X32_BASE EQU 0x40004698 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_X32_SIZE +CYDEV_MFGCFG_X32_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_X32_TR +CYDEV_MFGCFG_X32_TR EQU 0x40004698 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_BASE +CYDEV_MFGCFG_IMO_BASE EQU 0x400046a0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_SIZE +CYDEV_MFGCFG_IMO_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_TR0 +CYDEV_MFGCFG_IMO_TR0 EQU 0x400046a0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_TR1 +CYDEV_MFGCFG_IMO_TR1 EQU 0x400046a1 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_GAIN +CYDEV_MFGCFG_IMO_GAIN EQU 0x400046a2 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_C36M +CYDEV_MFGCFG_IMO_C36M EQU 0x400046a3 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_TR2 +CYDEV_MFGCFG_IMO_TR2 EQU 0x400046a4 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_BASE +CYDEV_MFGCFG_XMHZ_BASE EQU 0x400046a8 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_SIZE +CYDEV_MFGCFG_XMHZ_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_TR +CYDEV_MFGCFG_XMHZ_TR EQU 0x400046a8 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_DLY +CYDEV_MFGCFG_DLY EQU 0x400046c0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_BASE +CYDEV_MFGCFG_MLOGIC_BASE EQU 0x400046e0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SIZE +CYDEV_MFGCFG_MLOGIC_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_DMPSTR +CYDEV_MFGCFG_MLOGIC_DMPSTR EQU 0x400046e2 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_BASE +CYDEV_MFGCFG_MLOGIC_SEG_BASE EQU 0x400046e4 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_SIZE +CYDEV_MFGCFG_MLOGIC_SEG_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_CR +CYDEV_MFGCFG_MLOGIC_SEG_CR EQU 0x400046e4 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_CFG0 +CYDEV_MFGCFG_MLOGIC_SEG_CFG0 EQU 0x400046e5 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_DEBUG +CYDEV_MFGCFG_MLOGIC_DEBUG EQU 0x400046e8 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE +CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE EQU 0x400046ea + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE +CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR +CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR EQU 0x400046ea + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_REV_ID +CYDEV_MFGCFG_MLOGIC_REV_ID EQU 0x400046ec + ENDIF + IF :LNOT::DEF:CYDEV_RESET_BASE +CYDEV_RESET_BASE EQU 0x400046f0 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SIZE +CYDEV_RESET_SIZE EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYDEV_RESET_IPOR_CR0 +CYDEV_RESET_IPOR_CR0 EQU 0x400046f0 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_IPOR_CR1 +CYDEV_RESET_IPOR_CR1 EQU 0x400046f1 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_IPOR_CR2 +CYDEV_RESET_IPOR_CR2 EQU 0x400046f2 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_IPOR_CR3 +CYDEV_RESET_IPOR_CR3 EQU 0x400046f3 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR0 +CYDEV_RESET_CR0 EQU 0x400046f4 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR1 +CYDEV_RESET_CR1 EQU 0x400046f5 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR2 +CYDEV_RESET_CR2 EQU 0x400046f6 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR3 +CYDEV_RESET_CR3 EQU 0x400046f7 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR4 +CYDEV_RESET_CR4 EQU 0x400046f8 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR5 +CYDEV_RESET_CR5 EQU 0x400046f9 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SR0 +CYDEV_RESET_SR0 EQU 0x400046fa + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SR1 +CYDEV_RESET_SR1 EQU 0x400046fb + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SR2 +CYDEV_RESET_SR2 EQU 0x400046fc + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SR3 +CYDEV_RESET_SR3 EQU 0x400046fd + ENDIF + IF :LNOT::DEF:CYDEV_RESET_TR +CYDEV_RESET_TR EQU 0x400046fe + ENDIF + IF :LNOT::DEF:CYDEV_SPC_BASE +CYDEV_SPC_BASE EQU 0x40004700 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_SIZE +CYDEV_SPC_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_FM_EE_CR +CYDEV_SPC_FM_EE_CR EQU 0x40004700 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_FM_EE_WAKE_CNT +CYDEV_SPC_FM_EE_WAKE_CNT EQU 0x40004701 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_EE_SCR +CYDEV_SPC_EE_SCR EQU 0x40004702 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_EE_ERR +CYDEV_SPC_EE_ERR EQU 0x40004703 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_CPU_DATA +CYDEV_SPC_CPU_DATA EQU 0x40004720 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMA_DATA +CYDEV_SPC_DMA_DATA EQU 0x40004721 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_SR +CYDEV_SPC_SR EQU 0x40004722 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_CR +CYDEV_SPC_CR EQU 0x40004723 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_BASE +CYDEV_SPC_DMM_MAP_BASE EQU 0x40004780 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_SIZE +CYDEV_SPC_DMM_MAP_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_SRAM_MBASE +CYDEV_SPC_DMM_MAP_SRAM_MBASE EQU 0x40004780 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_SRAM_MSIZE +CYDEV_SPC_DMM_MAP_SRAM_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_BASE +CYDEV_CACHE_BASE EQU 0x40004800 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_SIZE +CYDEV_CACHE_SIZE EQU 0x0000009c + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_CC_CTL +CYDEV_CACHE_CC_CTL EQU 0x40004800 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_ECC_CORR +CYDEV_CACHE_ECC_CORR EQU 0x40004880 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_ECC_ERR +CYDEV_CACHE_ECC_ERR EQU 0x40004888 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_FLASH_ERR +CYDEV_CACHE_FLASH_ERR EQU 0x40004890 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_HITMISS +CYDEV_CACHE_HITMISS EQU 0x40004898 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_BASE +CYDEV_I2C_BASE EQU 0x40004900 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_SIZE +CYDEV_I2C_SIZE EQU 0x000000e1 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_XCFG +CYDEV_I2C_XCFG EQU 0x400049c8 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_ADR +CYDEV_I2C_ADR EQU 0x400049ca + ENDIF + IF :LNOT::DEF:CYDEV_I2C_CFG +CYDEV_I2C_CFG EQU 0x400049d6 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_CSR +CYDEV_I2C_CSR EQU 0x400049d7 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_D +CYDEV_I2C_D EQU 0x400049d8 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_MCSR +CYDEV_I2C_MCSR EQU 0x400049d9 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_CLK_DIV1 +CYDEV_I2C_CLK_DIV1 EQU 0x400049db + ENDIF + IF :LNOT::DEF:CYDEV_I2C_CLK_DIV2 +CYDEV_I2C_CLK_DIV2 EQU 0x400049dc + ENDIF + IF :LNOT::DEF:CYDEV_I2C_TMOUT_CSR +CYDEV_I2C_TMOUT_CSR EQU 0x400049dd + ENDIF + IF :LNOT::DEF:CYDEV_I2C_TMOUT_SR +CYDEV_I2C_TMOUT_SR EQU 0x400049de + ENDIF + IF :LNOT::DEF:CYDEV_I2C_TMOUT_CFG0 +CYDEV_I2C_TMOUT_CFG0 EQU 0x400049df + ENDIF + IF :LNOT::DEF:CYDEV_I2C_TMOUT_CFG1 +CYDEV_I2C_TMOUT_CFG1 EQU 0x400049e0 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_BASE +CYDEV_DEC_BASE EQU 0x40004e00 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_SIZE +CYDEV_DEC_SIZE EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_CR +CYDEV_DEC_CR EQU 0x40004e00 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_SR +CYDEV_DEC_SR EQU 0x40004e01 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_SHIFT1 +CYDEV_DEC_SHIFT1 EQU 0x40004e02 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_SHIFT2 +CYDEV_DEC_SHIFT2 EQU 0x40004e03 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_DR2 +CYDEV_DEC_DR2 EQU 0x40004e04 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_DR2H +CYDEV_DEC_DR2H EQU 0x40004e05 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_DR1 +CYDEV_DEC_DR1 EQU 0x40004e06 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OCOR +CYDEV_DEC_OCOR EQU 0x40004e08 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OCORM +CYDEV_DEC_OCORM EQU 0x40004e09 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OCORH +CYDEV_DEC_OCORH EQU 0x40004e0a + ENDIF + IF :LNOT::DEF:CYDEV_DEC_GCOR +CYDEV_DEC_GCOR EQU 0x40004e0c + ENDIF + IF :LNOT::DEF:CYDEV_DEC_GCORH +CYDEV_DEC_GCORH EQU 0x40004e0d + ENDIF + IF :LNOT::DEF:CYDEV_DEC_GVAL +CYDEV_DEC_GVAL EQU 0x40004e0e + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OUTSAMP +CYDEV_DEC_OUTSAMP EQU 0x40004e10 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OUTSAMPM +CYDEV_DEC_OUTSAMPM EQU 0x40004e11 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OUTSAMPH +CYDEV_DEC_OUTSAMPH EQU 0x40004e12 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OUTSAMPS +CYDEV_DEC_OUTSAMPS EQU 0x40004e13 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_COHER +CYDEV_DEC_COHER EQU 0x40004e14 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_BASE +CYDEV_TMR0_BASE EQU 0x40004f00 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_SIZE +CYDEV_TMR0_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CFG0 +CYDEV_TMR0_CFG0 EQU 0x40004f00 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CFG1 +CYDEV_TMR0_CFG1 EQU 0x40004f01 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CFG2 +CYDEV_TMR0_CFG2 EQU 0x40004f02 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_SR0 +CYDEV_TMR0_SR0 EQU 0x40004f03 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_PER0 +CYDEV_TMR0_PER0 EQU 0x40004f04 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_PER1 +CYDEV_TMR0_PER1 EQU 0x40004f05 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CNT_CMP0 +CYDEV_TMR0_CNT_CMP0 EQU 0x40004f06 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CNT_CMP1 +CYDEV_TMR0_CNT_CMP1 EQU 0x40004f07 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CAP0 +CYDEV_TMR0_CAP0 EQU 0x40004f08 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CAP1 +CYDEV_TMR0_CAP1 EQU 0x40004f09 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_RT0 +CYDEV_TMR0_RT0 EQU 0x40004f0a + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_RT1 +CYDEV_TMR0_RT1 EQU 0x40004f0b + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_BASE +CYDEV_TMR1_BASE EQU 0x40004f0c + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_SIZE +CYDEV_TMR1_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CFG0 +CYDEV_TMR1_CFG0 EQU 0x40004f0c + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CFG1 +CYDEV_TMR1_CFG1 EQU 0x40004f0d + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CFG2 +CYDEV_TMR1_CFG2 EQU 0x40004f0e + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_SR0 +CYDEV_TMR1_SR0 EQU 0x40004f0f + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_PER0 +CYDEV_TMR1_PER0 EQU 0x40004f10 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_PER1 +CYDEV_TMR1_PER1 EQU 0x40004f11 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CNT_CMP0 +CYDEV_TMR1_CNT_CMP0 EQU 0x40004f12 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CNT_CMP1 +CYDEV_TMR1_CNT_CMP1 EQU 0x40004f13 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CAP0 +CYDEV_TMR1_CAP0 EQU 0x40004f14 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CAP1 +CYDEV_TMR1_CAP1 EQU 0x40004f15 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_RT0 +CYDEV_TMR1_RT0 EQU 0x40004f16 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_RT1 +CYDEV_TMR1_RT1 EQU 0x40004f17 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_BASE +CYDEV_TMR2_BASE EQU 0x40004f18 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_SIZE +CYDEV_TMR2_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CFG0 +CYDEV_TMR2_CFG0 EQU 0x40004f18 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CFG1 +CYDEV_TMR2_CFG1 EQU 0x40004f19 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CFG2 +CYDEV_TMR2_CFG2 EQU 0x40004f1a + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_SR0 +CYDEV_TMR2_SR0 EQU 0x40004f1b + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_PER0 +CYDEV_TMR2_PER0 EQU 0x40004f1c + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_PER1 +CYDEV_TMR2_PER1 EQU 0x40004f1d + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CNT_CMP0 +CYDEV_TMR2_CNT_CMP0 EQU 0x40004f1e + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CNT_CMP1 +CYDEV_TMR2_CNT_CMP1 EQU 0x40004f1f + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CAP0 +CYDEV_TMR2_CAP0 EQU 0x40004f20 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CAP1 +CYDEV_TMR2_CAP1 EQU 0x40004f21 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_RT0 +CYDEV_TMR2_RT0 EQU 0x40004f22 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_RT1 +CYDEV_TMR2_RT1 EQU 0x40004f23 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_BASE +CYDEV_TMR3_BASE EQU 0x40004f24 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_SIZE +CYDEV_TMR3_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CFG0 +CYDEV_TMR3_CFG0 EQU 0x40004f24 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CFG1 +CYDEV_TMR3_CFG1 EQU 0x40004f25 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CFG2 +CYDEV_TMR3_CFG2 EQU 0x40004f26 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_SR0 +CYDEV_TMR3_SR0 EQU 0x40004f27 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_PER0 +CYDEV_TMR3_PER0 EQU 0x40004f28 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_PER1 +CYDEV_TMR3_PER1 EQU 0x40004f29 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CNT_CMP0 +CYDEV_TMR3_CNT_CMP0 EQU 0x40004f2a + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CNT_CMP1 +CYDEV_TMR3_CNT_CMP1 EQU 0x40004f2b + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CAP0 +CYDEV_TMR3_CAP0 EQU 0x40004f2c + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CAP1 +CYDEV_TMR3_CAP1 EQU 0x40004f2d + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_RT0 +CYDEV_TMR3_RT0 EQU 0x40004f2e + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_RT1 +CYDEV_TMR3_RT1 EQU 0x40004f2f + ENDIF + IF :LNOT::DEF:CYDEV_IO_BASE +CYDEV_IO_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_SIZE +CYDEV_IO_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_BASE +CYDEV_IO_PC_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_SIZE +CYDEV_IO_PC_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_BASE +CYDEV_IO_PC_PRT0_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_SIZE +CYDEV_IO_PC_PRT0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC0 +CYDEV_IO_PC_PRT0_PC0 EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC1 +CYDEV_IO_PC_PRT0_PC1 EQU 0x40005001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC2 +CYDEV_IO_PC_PRT0_PC2 EQU 0x40005002 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC3 +CYDEV_IO_PC_PRT0_PC3 EQU 0x40005003 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC4 +CYDEV_IO_PC_PRT0_PC4 EQU 0x40005004 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC5 +CYDEV_IO_PC_PRT0_PC5 EQU 0x40005005 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC6 +CYDEV_IO_PC_PRT0_PC6 EQU 0x40005006 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC7 +CYDEV_IO_PC_PRT0_PC7 EQU 0x40005007 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_BASE +CYDEV_IO_PC_PRT1_BASE EQU 0x40005008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_SIZE +CYDEV_IO_PC_PRT1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC0 +CYDEV_IO_PC_PRT1_PC0 EQU 0x40005008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC1 +CYDEV_IO_PC_PRT1_PC1 EQU 0x40005009 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC2 +CYDEV_IO_PC_PRT1_PC2 EQU 0x4000500a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC3 +CYDEV_IO_PC_PRT1_PC3 EQU 0x4000500b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC4 +CYDEV_IO_PC_PRT1_PC4 EQU 0x4000500c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC5 +CYDEV_IO_PC_PRT1_PC5 EQU 0x4000500d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC6 +CYDEV_IO_PC_PRT1_PC6 EQU 0x4000500e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC7 +CYDEV_IO_PC_PRT1_PC7 EQU 0x4000500f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_BASE +CYDEV_IO_PC_PRT2_BASE EQU 0x40005010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_SIZE +CYDEV_IO_PC_PRT2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC0 +CYDEV_IO_PC_PRT2_PC0 EQU 0x40005010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC1 +CYDEV_IO_PC_PRT2_PC1 EQU 0x40005011 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC2 +CYDEV_IO_PC_PRT2_PC2 EQU 0x40005012 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC3 +CYDEV_IO_PC_PRT2_PC3 EQU 0x40005013 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC4 +CYDEV_IO_PC_PRT2_PC4 EQU 0x40005014 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC5 +CYDEV_IO_PC_PRT2_PC5 EQU 0x40005015 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC6 +CYDEV_IO_PC_PRT2_PC6 EQU 0x40005016 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC7 +CYDEV_IO_PC_PRT2_PC7 EQU 0x40005017 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_BASE +CYDEV_IO_PC_PRT3_BASE EQU 0x40005018 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_SIZE +CYDEV_IO_PC_PRT3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC0 +CYDEV_IO_PC_PRT3_PC0 EQU 0x40005018 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC1 +CYDEV_IO_PC_PRT3_PC1 EQU 0x40005019 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC2 +CYDEV_IO_PC_PRT3_PC2 EQU 0x4000501a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC3 +CYDEV_IO_PC_PRT3_PC3 EQU 0x4000501b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC4 +CYDEV_IO_PC_PRT3_PC4 EQU 0x4000501c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC5 +CYDEV_IO_PC_PRT3_PC5 EQU 0x4000501d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC6 +CYDEV_IO_PC_PRT3_PC6 EQU 0x4000501e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC7 +CYDEV_IO_PC_PRT3_PC7 EQU 0x4000501f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_BASE +CYDEV_IO_PC_PRT4_BASE EQU 0x40005020 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_SIZE +CYDEV_IO_PC_PRT4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC0 +CYDEV_IO_PC_PRT4_PC0 EQU 0x40005020 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC1 +CYDEV_IO_PC_PRT4_PC1 EQU 0x40005021 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC2 +CYDEV_IO_PC_PRT4_PC2 EQU 0x40005022 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC3 +CYDEV_IO_PC_PRT4_PC3 EQU 0x40005023 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC4 +CYDEV_IO_PC_PRT4_PC4 EQU 0x40005024 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC5 +CYDEV_IO_PC_PRT4_PC5 EQU 0x40005025 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC6 +CYDEV_IO_PC_PRT4_PC6 EQU 0x40005026 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC7 +CYDEV_IO_PC_PRT4_PC7 EQU 0x40005027 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_BASE +CYDEV_IO_PC_PRT5_BASE EQU 0x40005028 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_SIZE +CYDEV_IO_PC_PRT5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC0 +CYDEV_IO_PC_PRT5_PC0 EQU 0x40005028 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC1 +CYDEV_IO_PC_PRT5_PC1 EQU 0x40005029 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC2 +CYDEV_IO_PC_PRT5_PC2 EQU 0x4000502a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC3 +CYDEV_IO_PC_PRT5_PC3 EQU 0x4000502b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC4 +CYDEV_IO_PC_PRT5_PC4 EQU 0x4000502c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC5 +CYDEV_IO_PC_PRT5_PC5 EQU 0x4000502d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC6 +CYDEV_IO_PC_PRT5_PC6 EQU 0x4000502e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC7 +CYDEV_IO_PC_PRT5_PC7 EQU 0x4000502f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_BASE +CYDEV_IO_PC_PRT6_BASE EQU 0x40005030 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_SIZE +CYDEV_IO_PC_PRT6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC0 +CYDEV_IO_PC_PRT6_PC0 EQU 0x40005030 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC1 +CYDEV_IO_PC_PRT6_PC1 EQU 0x40005031 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC2 +CYDEV_IO_PC_PRT6_PC2 EQU 0x40005032 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC3 +CYDEV_IO_PC_PRT6_PC3 EQU 0x40005033 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC4 +CYDEV_IO_PC_PRT6_PC4 EQU 0x40005034 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC5 +CYDEV_IO_PC_PRT6_PC5 EQU 0x40005035 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC6 +CYDEV_IO_PC_PRT6_PC6 EQU 0x40005036 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC7 +CYDEV_IO_PC_PRT6_PC7 EQU 0x40005037 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_BASE +CYDEV_IO_PC_PRT12_BASE EQU 0x40005060 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_SIZE +CYDEV_IO_PC_PRT12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC0 +CYDEV_IO_PC_PRT12_PC0 EQU 0x40005060 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC1 +CYDEV_IO_PC_PRT12_PC1 EQU 0x40005061 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC2 +CYDEV_IO_PC_PRT12_PC2 EQU 0x40005062 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC3 +CYDEV_IO_PC_PRT12_PC3 EQU 0x40005063 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC4 +CYDEV_IO_PC_PRT12_PC4 EQU 0x40005064 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC5 +CYDEV_IO_PC_PRT12_PC5 EQU 0x40005065 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC6 +CYDEV_IO_PC_PRT12_PC6 EQU 0x40005066 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC7 +CYDEV_IO_PC_PRT12_PC7 EQU 0x40005067 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_BASE +CYDEV_IO_PC_PRT15_BASE EQU 0x40005078 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_SIZE +CYDEV_IO_PC_PRT15_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC0 +CYDEV_IO_PC_PRT15_PC0 EQU 0x40005078 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC1 +CYDEV_IO_PC_PRT15_PC1 EQU 0x40005079 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC2 +CYDEV_IO_PC_PRT15_PC2 EQU 0x4000507a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC3 +CYDEV_IO_PC_PRT15_PC3 EQU 0x4000507b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC4 +CYDEV_IO_PC_PRT15_PC4 EQU 0x4000507c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC5 +CYDEV_IO_PC_PRT15_PC5 EQU 0x4000507d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_BASE +CYDEV_IO_PC_PRT15_7_6_BASE EQU 0x4000507e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_SIZE +CYDEV_IO_PC_PRT15_7_6_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_PC0 +CYDEV_IO_PC_PRT15_7_6_PC0 EQU 0x4000507e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_PC1 +CYDEV_IO_PC_PRT15_7_6_PC1 EQU 0x4000507f + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_BASE +CYDEV_IO_DR_BASE EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_SIZE +CYDEV_IO_DR_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT0_BASE +CYDEV_IO_DR_PRT0_BASE EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT0_SIZE +CYDEV_IO_DR_PRT0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT0_DR_ALIAS +CYDEV_IO_DR_PRT0_DR_ALIAS EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT1_BASE +CYDEV_IO_DR_PRT1_BASE EQU 0x40005081 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT1_SIZE +CYDEV_IO_DR_PRT1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT1_DR_ALIAS +CYDEV_IO_DR_PRT1_DR_ALIAS EQU 0x40005081 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT2_BASE +CYDEV_IO_DR_PRT2_BASE EQU 0x40005082 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT2_SIZE +CYDEV_IO_DR_PRT2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT2_DR_ALIAS +CYDEV_IO_DR_PRT2_DR_ALIAS EQU 0x40005082 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT3_BASE +CYDEV_IO_DR_PRT3_BASE EQU 0x40005083 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT3_SIZE +CYDEV_IO_DR_PRT3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT3_DR_ALIAS +CYDEV_IO_DR_PRT3_DR_ALIAS EQU 0x40005083 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT4_BASE +CYDEV_IO_DR_PRT4_BASE EQU 0x40005084 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT4_SIZE +CYDEV_IO_DR_PRT4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT4_DR_ALIAS +CYDEV_IO_DR_PRT4_DR_ALIAS EQU 0x40005084 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT5_BASE +CYDEV_IO_DR_PRT5_BASE EQU 0x40005085 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT5_SIZE +CYDEV_IO_DR_PRT5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT5_DR_ALIAS +CYDEV_IO_DR_PRT5_DR_ALIAS EQU 0x40005085 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT6_BASE +CYDEV_IO_DR_PRT6_BASE EQU 0x40005086 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT6_SIZE +CYDEV_IO_DR_PRT6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT6_DR_ALIAS +CYDEV_IO_DR_PRT6_DR_ALIAS EQU 0x40005086 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT12_BASE +CYDEV_IO_DR_PRT12_BASE EQU 0x4000508c + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT12_SIZE +CYDEV_IO_DR_PRT12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT12_DR_ALIAS +CYDEV_IO_DR_PRT12_DR_ALIAS EQU 0x4000508c + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT15_BASE +CYDEV_IO_DR_PRT15_BASE EQU 0x4000508f + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT15_SIZE +CYDEV_IO_DR_PRT15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT15_DR_15_ALIAS +CYDEV_IO_DR_PRT15_DR_15_ALIAS EQU 0x4000508f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_BASE +CYDEV_IO_PS_BASE EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_SIZE +CYDEV_IO_PS_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT0_BASE +CYDEV_IO_PS_PRT0_BASE EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT0_SIZE +CYDEV_IO_PS_PRT0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT0_PS_ALIAS +CYDEV_IO_PS_PRT0_PS_ALIAS EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT1_BASE +CYDEV_IO_PS_PRT1_BASE EQU 0x40005091 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT1_SIZE +CYDEV_IO_PS_PRT1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT1_PS_ALIAS +CYDEV_IO_PS_PRT1_PS_ALIAS EQU 0x40005091 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT2_BASE +CYDEV_IO_PS_PRT2_BASE EQU 0x40005092 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT2_SIZE +CYDEV_IO_PS_PRT2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT2_PS_ALIAS +CYDEV_IO_PS_PRT2_PS_ALIAS EQU 0x40005092 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT3_BASE +CYDEV_IO_PS_PRT3_BASE EQU 0x40005093 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT3_SIZE +CYDEV_IO_PS_PRT3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT3_PS_ALIAS +CYDEV_IO_PS_PRT3_PS_ALIAS EQU 0x40005093 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT4_BASE +CYDEV_IO_PS_PRT4_BASE EQU 0x40005094 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT4_SIZE +CYDEV_IO_PS_PRT4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT4_PS_ALIAS +CYDEV_IO_PS_PRT4_PS_ALIAS EQU 0x40005094 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT5_BASE +CYDEV_IO_PS_PRT5_BASE EQU 0x40005095 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT5_SIZE +CYDEV_IO_PS_PRT5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT5_PS_ALIAS +CYDEV_IO_PS_PRT5_PS_ALIAS EQU 0x40005095 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT6_BASE +CYDEV_IO_PS_PRT6_BASE EQU 0x40005096 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT6_SIZE +CYDEV_IO_PS_PRT6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT6_PS_ALIAS +CYDEV_IO_PS_PRT6_PS_ALIAS EQU 0x40005096 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT12_BASE +CYDEV_IO_PS_PRT12_BASE EQU 0x4000509c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT12_SIZE +CYDEV_IO_PS_PRT12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT12_PS_ALIAS +CYDEV_IO_PS_PRT12_PS_ALIAS EQU 0x4000509c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT15_BASE +CYDEV_IO_PS_PRT15_BASE EQU 0x4000509f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT15_SIZE +CYDEV_IO_PS_PRT15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT15_PS15_ALIAS +CYDEV_IO_PS_PRT15_PS15_ALIAS EQU 0x4000509f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_BASE +CYDEV_IO_PRT_BASE EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_SIZE +CYDEV_IO_PRT_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BASE +CYDEV_IO_PRT_PRT0_BASE EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_SIZE +CYDEV_IO_PRT_PRT0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_DR +CYDEV_IO_PRT_PRT0_DR EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_PS +CYDEV_IO_PRT_PRT0_PS EQU 0x40005101 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_DM0 +CYDEV_IO_PRT_PRT0_DM0 EQU 0x40005102 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_DM1 +CYDEV_IO_PRT_PRT0_DM1 EQU 0x40005103 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_DM2 +CYDEV_IO_PRT_PRT0_DM2 EQU 0x40005104 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_SLW +CYDEV_IO_PRT_PRT0_SLW EQU 0x40005105 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BYP +CYDEV_IO_PRT_PRT0_BYP EQU 0x40005106 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BIE +CYDEV_IO_PRT_PRT0_BIE EQU 0x40005107 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_INP_DIS +CYDEV_IO_PRT_PRT0_INP_DIS EQU 0x40005108 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_CTL +CYDEV_IO_PRT_PRT0_CTL EQU 0x40005109 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_PRT +CYDEV_IO_PRT_PRT0_PRT EQU 0x4000510a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BIT_MASK +CYDEV_IO_PRT_PRT0_BIT_MASK EQU 0x4000510b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_AMUX +CYDEV_IO_PRT_PRT0_AMUX EQU 0x4000510c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_AG +CYDEV_IO_PRT_PRT0_AG EQU 0x4000510d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_LCD_COM_SEG +CYDEV_IO_PRT_PRT0_LCD_COM_SEG EQU 0x4000510e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_LCD_EN +CYDEV_IO_PRT_PRT0_LCD_EN EQU 0x4000510f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BASE +CYDEV_IO_PRT_PRT1_BASE EQU 0x40005110 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_SIZE +CYDEV_IO_PRT_PRT1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_DR +CYDEV_IO_PRT_PRT1_DR EQU 0x40005110 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_PS +CYDEV_IO_PRT_PRT1_PS EQU 0x40005111 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_DM0 +CYDEV_IO_PRT_PRT1_DM0 EQU 0x40005112 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_DM1 +CYDEV_IO_PRT_PRT1_DM1 EQU 0x40005113 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_DM2 +CYDEV_IO_PRT_PRT1_DM2 EQU 0x40005114 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_SLW +CYDEV_IO_PRT_PRT1_SLW EQU 0x40005115 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BYP +CYDEV_IO_PRT_PRT1_BYP EQU 0x40005116 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BIE +CYDEV_IO_PRT_PRT1_BIE EQU 0x40005117 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_INP_DIS +CYDEV_IO_PRT_PRT1_INP_DIS EQU 0x40005118 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_CTL +CYDEV_IO_PRT_PRT1_CTL EQU 0x40005119 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_PRT +CYDEV_IO_PRT_PRT1_PRT EQU 0x4000511a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BIT_MASK +CYDEV_IO_PRT_PRT1_BIT_MASK EQU 0x4000511b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_AMUX +CYDEV_IO_PRT_PRT1_AMUX EQU 0x4000511c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_AG +CYDEV_IO_PRT_PRT1_AG EQU 0x4000511d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_LCD_COM_SEG +CYDEV_IO_PRT_PRT1_LCD_COM_SEG EQU 0x4000511e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_LCD_EN +CYDEV_IO_PRT_PRT1_LCD_EN EQU 0x4000511f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BASE +CYDEV_IO_PRT_PRT2_BASE EQU 0x40005120 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_SIZE +CYDEV_IO_PRT_PRT2_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_DR +CYDEV_IO_PRT_PRT2_DR EQU 0x40005120 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_PS +CYDEV_IO_PRT_PRT2_PS EQU 0x40005121 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_DM0 +CYDEV_IO_PRT_PRT2_DM0 EQU 0x40005122 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_DM1 +CYDEV_IO_PRT_PRT2_DM1 EQU 0x40005123 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_DM2 +CYDEV_IO_PRT_PRT2_DM2 EQU 0x40005124 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_SLW +CYDEV_IO_PRT_PRT2_SLW EQU 0x40005125 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BYP +CYDEV_IO_PRT_PRT2_BYP EQU 0x40005126 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BIE +CYDEV_IO_PRT_PRT2_BIE EQU 0x40005127 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_INP_DIS +CYDEV_IO_PRT_PRT2_INP_DIS EQU 0x40005128 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_CTL +CYDEV_IO_PRT_PRT2_CTL EQU 0x40005129 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_PRT +CYDEV_IO_PRT_PRT2_PRT EQU 0x4000512a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BIT_MASK +CYDEV_IO_PRT_PRT2_BIT_MASK EQU 0x4000512b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_AMUX +CYDEV_IO_PRT_PRT2_AMUX EQU 0x4000512c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_AG +CYDEV_IO_PRT_PRT2_AG EQU 0x4000512d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_LCD_COM_SEG +CYDEV_IO_PRT_PRT2_LCD_COM_SEG EQU 0x4000512e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_LCD_EN +CYDEV_IO_PRT_PRT2_LCD_EN EQU 0x4000512f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BASE +CYDEV_IO_PRT_PRT3_BASE EQU 0x40005130 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_SIZE +CYDEV_IO_PRT_PRT3_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_DR +CYDEV_IO_PRT_PRT3_DR EQU 0x40005130 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_PS +CYDEV_IO_PRT_PRT3_PS EQU 0x40005131 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_DM0 +CYDEV_IO_PRT_PRT3_DM0 EQU 0x40005132 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_DM1 +CYDEV_IO_PRT_PRT3_DM1 EQU 0x40005133 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_DM2 +CYDEV_IO_PRT_PRT3_DM2 EQU 0x40005134 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_SLW +CYDEV_IO_PRT_PRT3_SLW EQU 0x40005135 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BYP +CYDEV_IO_PRT_PRT3_BYP EQU 0x40005136 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BIE +CYDEV_IO_PRT_PRT3_BIE EQU 0x40005137 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_INP_DIS +CYDEV_IO_PRT_PRT3_INP_DIS EQU 0x40005138 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_CTL +CYDEV_IO_PRT_PRT3_CTL EQU 0x40005139 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_PRT +CYDEV_IO_PRT_PRT3_PRT EQU 0x4000513a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BIT_MASK +CYDEV_IO_PRT_PRT3_BIT_MASK EQU 0x4000513b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_AMUX +CYDEV_IO_PRT_PRT3_AMUX EQU 0x4000513c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_AG +CYDEV_IO_PRT_PRT3_AG EQU 0x4000513d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_LCD_COM_SEG +CYDEV_IO_PRT_PRT3_LCD_COM_SEG EQU 0x4000513e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_LCD_EN +CYDEV_IO_PRT_PRT3_LCD_EN EQU 0x4000513f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BASE +CYDEV_IO_PRT_PRT4_BASE EQU 0x40005140 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_SIZE +CYDEV_IO_PRT_PRT4_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_DR +CYDEV_IO_PRT_PRT4_DR EQU 0x40005140 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_PS +CYDEV_IO_PRT_PRT4_PS EQU 0x40005141 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_DM0 +CYDEV_IO_PRT_PRT4_DM0 EQU 0x40005142 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_DM1 +CYDEV_IO_PRT_PRT4_DM1 EQU 0x40005143 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_DM2 +CYDEV_IO_PRT_PRT4_DM2 EQU 0x40005144 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_SLW +CYDEV_IO_PRT_PRT4_SLW EQU 0x40005145 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BYP +CYDEV_IO_PRT_PRT4_BYP EQU 0x40005146 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BIE +CYDEV_IO_PRT_PRT4_BIE EQU 0x40005147 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_INP_DIS +CYDEV_IO_PRT_PRT4_INP_DIS EQU 0x40005148 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_CTL +CYDEV_IO_PRT_PRT4_CTL EQU 0x40005149 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_PRT +CYDEV_IO_PRT_PRT4_PRT EQU 0x4000514a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BIT_MASK +CYDEV_IO_PRT_PRT4_BIT_MASK EQU 0x4000514b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_AMUX +CYDEV_IO_PRT_PRT4_AMUX EQU 0x4000514c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_AG +CYDEV_IO_PRT_PRT4_AG EQU 0x4000514d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_LCD_COM_SEG +CYDEV_IO_PRT_PRT4_LCD_COM_SEG EQU 0x4000514e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_LCD_EN +CYDEV_IO_PRT_PRT4_LCD_EN EQU 0x4000514f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BASE +CYDEV_IO_PRT_PRT5_BASE EQU 0x40005150 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_SIZE +CYDEV_IO_PRT_PRT5_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_DR +CYDEV_IO_PRT_PRT5_DR EQU 0x40005150 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_PS +CYDEV_IO_PRT_PRT5_PS EQU 0x40005151 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_DM0 +CYDEV_IO_PRT_PRT5_DM0 EQU 0x40005152 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_DM1 +CYDEV_IO_PRT_PRT5_DM1 EQU 0x40005153 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_DM2 +CYDEV_IO_PRT_PRT5_DM2 EQU 0x40005154 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_SLW +CYDEV_IO_PRT_PRT5_SLW EQU 0x40005155 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BYP +CYDEV_IO_PRT_PRT5_BYP EQU 0x40005156 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BIE +CYDEV_IO_PRT_PRT5_BIE EQU 0x40005157 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_INP_DIS +CYDEV_IO_PRT_PRT5_INP_DIS EQU 0x40005158 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_CTL +CYDEV_IO_PRT_PRT5_CTL EQU 0x40005159 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_PRT +CYDEV_IO_PRT_PRT5_PRT EQU 0x4000515a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BIT_MASK +CYDEV_IO_PRT_PRT5_BIT_MASK EQU 0x4000515b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_AMUX +CYDEV_IO_PRT_PRT5_AMUX EQU 0x4000515c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_AG +CYDEV_IO_PRT_PRT5_AG EQU 0x4000515d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_LCD_COM_SEG +CYDEV_IO_PRT_PRT5_LCD_COM_SEG EQU 0x4000515e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_LCD_EN +CYDEV_IO_PRT_PRT5_LCD_EN EQU 0x4000515f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BASE +CYDEV_IO_PRT_PRT6_BASE EQU 0x40005160 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_SIZE +CYDEV_IO_PRT_PRT6_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_DR +CYDEV_IO_PRT_PRT6_DR EQU 0x40005160 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_PS +CYDEV_IO_PRT_PRT6_PS EQU 0x40005161 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_DM0 +CYDEV_IO_PRT_PRT6_DM0 EQU 0x40005162 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_DM1 +CYDEV_IO_PRT_PRT6_DM1 EQU 0x40005163 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_DM2 +CYDEV_IO_PRT_PRT6_DM2 EQU 0x40005164 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_SLW +CYDEV_IO_PRT_PRT6_SLW EQU 0x40005165 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BYP +CYDEV_IO_PRT_PRT6_BYP EQU 0x40005166 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BIE +CYDEV_IO_PRT_PRT6_BIE EQU 0x40005167 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_INP_DIS +CYDEV_IO_PRT_PRT6_INP_DIS EQU 0x40005168 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_CTL +CYDEV_IO_PRT_PRT6_CTL EQU 0x40005169 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_PRT +CYDEV_IO_PRT_PRT6_PRT EQU 0x4000516a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BIT_MASK +CYDEV_IO_PRT_PRT6_BIT_MASK EQU 0x4000516b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_AMUX +CYDEV_IO_PRT_PRT6_AMUX EQU 0x4000516c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_AG +CYDEV_IO_PRT_PRT6_AG EQU 0x4000516d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_LCD_COM_SEG +CYDEV_IO_PRT_PRT6_LCD_COM_SEG EQU 0x4000516e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_LCD_EN +CYDEV_IO_PRT_PRT6_LCD_EN EQU 0x4000516f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BASE +CYDEV_IO_PRT_PRT12_BASE EQU 0x400051c0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIZE +CYDEV_IO_PRT_PRT12_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_DR +CYDEV_IO_PRT_PRT12_DR EQU 0x400051c0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_PS +CYDEV_IO_PRT_PRT12_PS EQU 0x400051c1 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_DM0 +CYDEV_IO_PRT_PRT12_DM0 EQU 0x400051c2 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_DM1 +CYDEV_IO_PRT_PRT12_DM1 EQU 0x400051c3 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_DM2 +CYDEV_IO_PRT_PRT12_DM2 EQU 0x400051c4 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SLW +CYDEV_IO_PRT_PRT12_SLW EQU 0x400051c5 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BYP +CYDEV_IO_PRT_PRT12_BYP EQU 0x400051c6 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BIE +CYDEV_IO_PRT_PRT12_BIE EQU 0x400051c7 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_INP_DIS +CYDEV_IO_PRT_PRT12_INP_DIS EQU 0x400051c8 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIO_HYST_EN +CYDEV_IO_PRT_PRT12_SIO_HYST_EN EQU 0x400051c9 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_PRT +CYDEV_IO_PRT_PRT12_PRT EQU 0x400051ca + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BIT_MASK +CYDEV_IO_PRT_PRT12_BIT_MASK EQU 0x400051cb + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ +CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ EQU 0x400051cc + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_AG +CYDEV_IO_PRT_PRT12_AG EQU 0x400051cd + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIO_CFG +CYDEV_IO_PRT_PRT12_SIO_CFG EQU 0x400051ce + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIO_DIFF +CYDEV_IO_PRT_PRT12_SIO_DIFF EQU 0x400051cf + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BASE +CYDEV_IO_PRT_PRT15_BASE EQU 0x400051f0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_SIZE +CYDEV_IO_PRT_PRT15_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_DR +CYDEV_IO_PRT_PRT15_DR EQU 0x400051f0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_PS +CYDEV_IO_PRT_PRT15_PS EQU 0x400051f1 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_DM0 +CYDEV_IO_PRT_PRT15_DM0 EQU 0x400051f2 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_DM1 +CYDEV_IO_PRT_PRT15_DM1 EQU 0x400051f3 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_DM2 +CYDEV_IO_PRT_PRT15_DM2 EQU 0x400051f4 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_SLW +CYDEV_IO_PRT_PRT15_SLW EQU 0x400051f5 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BYP +CYDEV_IO_PRT_PRT15_BYP EQU 0x400051f6 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BIE +CYDEV_IO_PRT_PRT15_BIE EQU 0x400051f7 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_INP_DIS +CYDEV_IO_PRT_PRT15_INP_DIS EQU 0x400051f8 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_CTL +CYDEV_IO_PRT_PRT15_CTL EQU 0x400051f9 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_PRT +CYDEV_IO_PRT_PRT15_PRT EQU 0x400051fa + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BIT_MASK +CYDEV_IO_PRT_PRT15_BIT_MASK EQU 0x400051fb + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_AMUX +CYDEV_IO_PRT_PRT15_AMUX EQU 0x400051fc + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_AG +CYDEV_IO_PRT_PRT15_AG EQU 0x400051fd + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_LCD_COM_SEG +CYDEV_IO_PRT_PRT15_LCD_COM_SEG EQU 0x400051fe + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_LCD_EN +CYDEV_IO_PRT_PRT15_LCD_EN EQU 0x400051ff + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_BASE +CYDEV_PRTDSI_BASE EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_SIZE +CYDEV_PRTDSI_SIZE EQU 0x0000007f + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_BASE +CYDEV_PRTDSI_PRT0_BASE EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_SIZE +CYDEV_PRTDSI_PRT0_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_OUT_SEL0 +CYDEV_PRTDSI_PRT0_OUT_SEL0 EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_OUT_SEL1 +CYDEV_PRTDSI_PRT0_OUT_SEL1 EQU 0x40005201 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_OE_SEL0 +CYDEV_PRTDSI_PRT0_OE_SEL0 EQU 0x40005202 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_OE_SEL1 +CYDEV_PRTDSI_PRT0_OE_SEL1 EQU 0x40005203 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_DBL_SYNC_IN +CYDEV_PRTDSI_PRT0_DBL_SYNC_IN EQU 0x40005204 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_SYNC_OUT +CYDEV_PRTDSI_PRT0_SYNC_OUT EQU 0x40005205 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_CAPS_SEL +CYDEV_PRTDSI_PRT0_CAPS_SEL EQU 0x40005206 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_BASE +CYDEV_PRTDSI_PRT1_BASE EQU 0x40005208 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_SIZE +CYDEV_PRTDSI_PRT1_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_OUT_SEL0 +CYDEV_PRTDSI_PRT1_OUT_SEL0 EQU 0x40005208 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_OUT_SEL1 +CYDEV_PRTDSI_PRT1_OUT_SEL1 EQU 0x40005209 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_OE_SEL0 +CYDEV_PRTDSI_PRT1_OE_SEL0 EQU 0x4000520a + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_OE_SEL1 +CYDEV_PRTDSI_PRT1_OE_SEL1 EQU 0x4000520b + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_DBL_SYNC_IN +CYDEV_PRTDSI_PRT1_DBL_SYNC_IN EQU 0x4000520c + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_SYNC_OUT +CYDEV_PRTDSI_PRT1_SYNC_OUT EQU 0x4000520d + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_CAPS_SEL +CYDEV_PRTDSI_PRT1_CAPS_SEL EQU 0x4000520e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_BASE +CYDEV_PRTDSI_PRT2_BASE EQU 0x40005210 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_SIZE +CYDEV_PRTDSI_PRT2_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_OUT_SEL0 +CYDEV_PRTDSI_PRT2_OUT_SEL0 EQU 0x40005210 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_OUT_SEL1 +CYDEV_PRTDSI_PRT2_OUT_SEL1 EQU 0x40005211 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_OE_SEL0 +CYDEV_PRTDSI_PRT2_OE_SEL0 EQU 0x40005212 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_OE_SEL1 +CYDEV_PRTDSI_PRT2_OE_SEL1 EQU 0x40005213 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_DBL_SYNC_IN +CYDEV_PRTDSI_PRT2_DBL_SYNC_IN EQU 0x40005214 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_SYNC_OUT +CYDEV_PRTDSI_PRT2_SYNC_OUT EQU 0x40005215 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_CAPS_SEL +CYDEV_PRTDSI_PRT2_CAPS_SEL EQU 0x40005216 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_BASE +CYDEV_PRTDSI_PRT3_BASE EQU 0x40005218 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_SIZE +CYDEV_PRTDSI_PRT3_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_OUT_SEL0 +CYDEV_PRTDSI_PRT3_OUT_SEL0 EQU 0x40005218 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_OUT_SEL1 +CYDEV_PRTDSI_PRT3_OUT_SEL1 EQU 0x40005219 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_OE_SEL0 +CYDEV_PRTDSI_PRT3_OE_SEL0 EQU 0x4000521a + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_OE_SEL1 +CYDEV_PRTDSI_PRT3_OE_SEL1 EQU 0x4000521b + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_DBL_SYNC_IN +CYDEV_PRTDSI_PRT3_DBL_SYNC_IN EQU 0x4000521c + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_SYNC_OUT +CYDEV_PRTDSI_PRT3_SYNC_OUT EQU 0x4000521d + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_CAPS_SEL +CYDEV_PRTDSI_PRT3_CAPS_SEL EQU 0x4000521e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_BASE +CYDEV_PRTDSI_PRT4_BASE EQU 0x40005220 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_SIZE +CYDEV_PRTDSI_PRT4_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_OUT_SEL0 +CYDEV_PRTDSI_PRT4_OUT_SEL0 EQU 0x40005220 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_OUT_SEL1 +CYDEV_PRTDSI_PRT4_OUT_SEL1 EQU 0x40005221 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_OE_SEL0 +CYDEV_PRTDSI_PRT4_OE_SEL0 EQU 0x40005222 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_OE_SEL1 +CYDEV_PRTDSI_PRT4_OE_SEL1 EQU 0x40005223 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_DBL_SYNC_IN +CYDEV_PRTDSI_PRT4_DBL_SYNC_IN EQU 0x40005224 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_SYNC_OUT +CYDEV_PRTDSI_PRT4_SYNC_OUT EQU 0x40005225 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_CAPS_SEL +CYDEV_PRTDSI_PRT4_CAPS_SEL EQU 0x40005226 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_BASE +CYDEV_PRTDSI_PRT5_BASE EQU 0x40005228 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_SIZE +CYDEV_PRTDSI_PRT5_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_OUT_SEL0 +CYDEV_PRTDSI_PRT5_OUT_SEL0 EQU 0x40005228 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_OUT_SEL1 +CYDEV_PRTDSI_PRT5_OUT_SEL1 EQU 0x40005229 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_OE_SEL0 +CYDEV_PRTDSI_PRT5_OE_SEL0 EQU 0x4000522a + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_OE_SEL1 +CYDEV_PRTDSI_PRT5_OE_SEL1 EQU 0x4000522b + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_DBL_SYNC_IN +CYDEV_PRTDSI_PRT5_DBL_SYNC_IN EQU 0x4000522c + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_SYNC_OUT +CYDEV_PRTDSI_PRT5_SYNC_OUT EQU 0x4000522d + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_CAPS_SEL +CYDEV_PRTDSI_PRT5_CAPS_SEL EQU 0x4000522e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_BASE +CYDEV_PRTDSI_PRT6_BASE EQU 0x40005230 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_SIZE +CYDEV_PRTDSI_PRT6_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_OUT_SEL0 +CYDEV_PRTDSI_PRT6_OUT_SEL0 EQU 0x40005230 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_OUT_SEL1 +CYDEV_PRTDSI_PRT6_OUT_SEL1 EQU 0x40005231 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_OE_SEL0 +CYDEV_PRTDSI_PRT6_OE_SEL0 EQU 0x40005232 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_OE_SEL1 +CYDEV_PRTDSI_PRT6_OE_SEL1 EQU 0x40005233 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_DBL_SYNC_IN +CYDEV_PRTDSI_PRT6_DBL_SYNC_IN EQU 0x40005234 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_SYNC_OUT +CYDEV_PRTDSI_PRT6_SYNC_OUT EQU 0x40005235 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_CAPS_SEL +CYDEV_PRTDSI_PRT6_CAPS_SEL EQU 0x40005236 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_BASE +CYDEV_PRTDSI_PRT12_BASE EQU 0x40005260 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_SIZE +CYDEV_PRTDSI_PRT12_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_OUT_SEL0 +CYDEV_PRTDSI_PRT12_OUT_SEL0 EQU 0x40005260 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_OUT_SEL1 +CYDEV_PRTDSI_PRT12_OUT_SEL1 EQU 0x40005261 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_OE_SEL0 +CYDEV_PRTDSI_PRT12_OE_SEL0 EQU 0x40005262 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_OE_SEL1 +CYDEV_PRTDSI_PRT12_OE_SEL1 EQU 0x40005263 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_DBL_SYNC_IN +CYDEV_PRTDSI_PRT12_DBL_SYNC_IN EQU 0x40005264 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_SYNC_OUT +CYDEV_PRTDSI_PRT12_SYNC_OUT EQU 0x40005265 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_BASE +CYDEV_PRTDSI_PRT15_BASE EQU 0x40005278 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_SIZE +CYDEV_PRTDSI_PRT15_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_OUT_SEL0 +CYDEV_PRTDSI_PRT15_OUT_SEL0 EQU 0x40005278 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_OUT_SEL1 +CYDEV_PRTDSI_PRT15_OUT_SEL1 EQU 0x40005279 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_OE_SEL0 +CYDEV_PRTDSI_PRT15_OE_SEL0 EQU 0x4000527a + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_OE_SEL1 +CYDEV_PRTDSI_PRT15_OE_SEL1 EQU 0x4000527b + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_DBL_SYNC_IN +CYDEV_PRTDSI_PRT15_DBL_SYNC_IN EQU 0x4000527c + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_SYNC_OUT +CYDEV_PRTDSI_PRT15_SYNC_OUT EQU 0x4000527d + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_CAPS_SEL +CYDEV_PRTDSI_PRT15_CAPS_SEL EQU 0x4000527e + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_BASE +CYDEV_EMIF_BASE EQU 0x40005400 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_SIZE +CYDEV_EMIF_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_NO_UDB +CYDEV_EMIF_NO_UDB EQU 0x40005400 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_RP_WAIT_STATES +CYDEV_EMIF_RP_WAIT_STATES EQU 0x40005401 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_MEM_DWN +CYDEV_EMIF_MEM_DWN EQU 0x40005402 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_MEMCLK_DIV +CYDEV_EMIF_MEMCLK_DIV EQU 0x40005403 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_CLOCK_EN +CYDEV_EMIF_CLOCK_EN EQU 0x40005404 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_EM_TYPE +CYDEV_EMIF_EM_TYPE EQU 0x40005405 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_WP_WAIT_STATES +CYDEV_EMIF_WP_WAIT_STATES EQU 0x40005406 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_BASE +CYDEV_ANAIF_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_SIZE +CYDEV_ANAIF_SIZE EQU 0x000003a9 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BASE +CYDEV_ANAIF_CFG_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SIZE +CYDEV_ANAIF_CFG_SIZE EQU 0x0000010f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_BASE +CYDEV_ANAIF_CFG_SC0_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_SIZE +CYDEV_ANAIF_CFG_SC0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_CR0 +CYDEV_ANAIF_CFG_SC0_CR0 EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_CR1 +CYDEV_ANAIF_CFG_SC0_CR1 EQU 0x40005801 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_CR2 +CYDEV_ANAIF_CFG_SC0_CR2 EQU 0x40005802 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_BASE +CYDEV_ANAIF_CFG_SC1_BASE EQU 0x40005804 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_SIZE +CYDEV_ANAIF_CFG_SC1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_CR0 +CYDEV_ANAIF_CFG_SC1_CR0 EQU 0x40005804 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_CR1 +CYDEV_ANAIF_CFG_SC1_CR1 EQU 0x40005805 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_CR2 +CYDEV_ANAIF_CFG_SC1_CR2 EQU 0x40005806 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_BASE +CYDEV_ANAIF_CFG_SC2_BASE EQU 0x40005808 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_SIZE +CYDEV_ANAIF_CFG_SC2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_CR0 +CYDEV_ANAIF_CFG_SC2_CR0 EQU 0x40005808 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_CR1 +CYDEV_ANAIF_CFG_SC2_CR1 EQU 0x40005809 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_CR2 +CYDEV_ANAIF_CFG_SC2_CR2 EQU 0x4000580a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_BASE +CYDEV_ANAIF_CFG_SC3_BASE EQU 0x4000580c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_SIZE +CYDEV_ANAIF_CFG_SC3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_CR0 +CYDEV_ANAIF_CFG_SC3_CR0 EQU 0x4000580c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_CR1 +CYDEV_ANAIF_CFG_SC3_CR1 EQU 0x4000580d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_CR2 +CYDEV_ANAIF_CFG_SC3_CR2 EQU 0x4000580e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_BASE +CYDEV_ANAIF_CFG_DAC0_BASE EQU 0x40005820 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_SIZE +CYDEV_ANAIF_CFG_DAC0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_CR0 +CYDEV_ANAIF_CFG_DAC0_CR0 EQU 0x40005820 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_CR1 +CYDEV_ANAIF_CFG_DAC0_CR1 EQU 0x40005821 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_TST +CYDEV_ANAIF_CFG_DAC0_TST EQU 0x40005822 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_BASE +CYDEV_ANAIF_CFG_DAC1_BASE EQU 0x40005824 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_SIZE +CYDEV_ANAIF_CFG_DAC1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_CR0 +CYDEV_ANAIF_CFG_DAC1_CR0 EQU 0x40005824 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_CR1 +CYDEV_ANAIF_CFG_DAC1_CR1 EQU 0x40005825 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_TST +CYDEV_ANAIF_CFG_DAC1_TST EQU 0x40005826 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_BASE +CYDEV_ANAIF_CFG_DAC2_BASE EQU 0x40005828 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_SIZE +CYDEV_ANAIF_CFG_DAC2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_CR0 +CYDEV_ANAIF_CFG_DAC2_CR0 EQU 0x40005828 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_CR1 +CYDEV_ANAIF_CFG_DAC2_CR1 EQU 0x40005829 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_TST +CYDEV_ANAIF_CFG_DAC2_TST EQU 0x4000582a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_BASE +CYDEV_ANAIF_CFG_DAC3_BASE EQU 0x4000582c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_SIZE +CYDEV_ANAIF_CFG_DAC3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_CR0 +CYDEV_ANAIF_CFG_DAC3_CR0 EQU 0x4000582c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_CR1 +CYDEV_ANAIF_CFG_DAC3_CR1 EQU 0x4000582d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_TST +CYDEV_ANAIF_CFG_DAC3_TST EQU 0x4000582e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_BASE +CYDEV_ANAIF_CFG_CMP0_BASE EQU 0x40005840 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_SIZE +CYDEV_ANAIF_CFG_CMP0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_CR +CYDEV_ANAIF_CFG_CMP0_CR EQU 0x40005840 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_BASE +CYDEV_ANAIF_CFG_CMP1_BASE EQU 0x40005841 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_SIZE +CYDEV_ANAIF_CFG_CMP1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_CR +CYDEV_ANAIF_CFG_CMP1_CR EQU 0x40005841 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_BASE +CYDEV_ANAIF_CFG_CMP2_BASE EQU 0x40005842 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_SIZE +CYDEV_ANAIF_CFG_CMP2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_CR +CYDEV_ANAIF_CFG_CMP2_CR EQU 0x40005842 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_BASE +CYDEV_ANAIF_CFG_CMP3_BASE EQU 0x40005843 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_SIZE +CYDEV_ANAIF_CFG_CMP3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_CR +CYDEV_ANAIF_CFG_CMP3_CR EQU 0x40005843 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_BASE +CYDEV_ANAIF_CFG_LUT0_BASE EQU 0x40005848 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_SIZE +CYDEV_ANAIF_CFG_LUT0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_CR +CYDEV_ANAIF_CFG_LUT0_CR EQU 0x40005848 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_MX +CYDEV_ANAIF_CFG_LUT0_MX EQU 0x40005849 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_BASE +CYDEV_ANAIF_CFG_LUT1_BASE EQU 0x4000584a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_SIZE +CYDEV_ANAIF_CFG_LUT1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_CR +CYDEV_ANAIF_CFG_LUT1_CR EQU 0x4000584a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_MX +CYDEV_ANAIF_CFG_LUT1_MX EQU 0x4000584b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_BASE +CYDEV_ANAIF_CFG_LUT2_BASE EQU 0x4000584c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_SIZE +CYDEV_ANAIF_CFG_LUT2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_CR +CYDEV_ANAIF_CFG_LUT2_CR EQU 0x4000584c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_MX +CYDEV_ANAIF_CFG_LUT2_MX EQU 0x4000584d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_BASE +CYDEV_ANAIF_CFG_LUT3_BASE EQU 0x4000584e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_SIZE +CYDEV_ANAIF_CFG_LUT3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_CR +CYDEV_ANAIF_CFG_LUT3_CR EQU 0x4000584e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_MX +CYDEV_ANAIF_CFG_LUT3_MX EQU 0x4000584f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_BASE +CYDEV_ANAIF_CFG_OPAMP0_BASE EQU 0x40005858 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_SIZE +CYDEV_ANAIF_CFG_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_CR +CYDEV_ANAIF_CFG_OPAMP0_CR EQU 0x40005858 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_RSVD +CYDEV_ANAIF_CFG_OPAMP0_RSVD EQU 0x40005859 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_BASE +CYDEV_ANAIF_CFG_OPAMP1_BASE EQU 0x4000585a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_SIZE +CYDEV_ANAIF_CFG_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_CR +CYDEV_ANAIF_CFG_OPAMP1_CR EQU 0x4000585a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_RSVD +CYDEV_ANAIF_CFG_OPAMP1_RSVD EQU 0x4000585b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_BASE +CYDEV_ANAIF_CFG_OPAMP2_BASE EQU 0x4000585c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_SIZE +CYDEV_ANAIF_CFG_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_CR +CYDEV_ANAIF_CFG_OPAMP2_CR EQU 0x4000585c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_RSVD +CYDEV_ANAIF_CFG_OPAMP2_RSVD EQU 0x4000585d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_BASE +CYDEV_ANAIF_CFG_OPAMP3_BASE EQU 0x4000585e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_SIZE +CYDEV_ANAIF_CFG_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_CR +CYDEV_ANAIF_CFG_OPAMP3_CR EQU 0x4000585e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_RSVD +CYDEV_ANAIF_CFG_OPAMP3_RSVD EQU 0x4000585f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_BASE +CYDEV_ANAIF_CFG_LCDDAC_BASE EQU 0x40005868 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_SIZE +CYDEV_ANAIF_CFG_LCDDAC_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_CR0 +CYDEV_ANAIF_CFG_LCDDAC_CR0 EQU 0x40005868 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_CR1 +CYDEV_ANAIF_CFG_LCDDAC_CR1 EQU 0x40005869 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_BASE +CYDEV_ANAIF_CFG_LCDDRV_BASE EQU 0x4000586a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_SIZE +CYDEV_ANAIF_CFG_LCDDRV_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_CR +CYDEV_ANAIF_CFG_LCDDRV_CR EQU 0x4000586a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_BASE +CYDEV_ANAIF_CFG_LCDTMR_BASE EQU 0x4000586b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_SIZE +CYDEV_ANAIF_CFG_LCDTMR_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_CFG +CYDEV_ANAIF_CFG_LCDTMR_CFG EQU 0x4000586b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_BASE +CYDEV_ANAIF_CFG_BG_BASE EQU 0x4000586c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_SIZE +CYDEV_ANAIF_CFG_BG_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_CR0 +CYDEV_ANAIF_CFG_BG_CR0 EQU 0x4000586c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_RSVD +CYDEV_ANAIF_CFG_BG_RSVD EQU 0x4000586d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_DFT0 +CYDEV_ANAIF_CFG_BG_DFT0 EQU 0x4000586e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_DFT1 +CYDEV_ANAIF_CFG_BG_DFT1 EQU 0x4000586f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_BASE +CYDEV_ANAIF_CFG_CAPSL_BASE EQU 0x40005870 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_SIZE +CYDEV_ANAIF_CFG_CAPSL_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_CFG0 +CYDEV_ANAIF_CFG_CAPSL_CFG0 EQU 0x40005870 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_CFG1 +CYDEV_ANAIF_CFG_CAPSL_CFG1 EQU 0x40005871 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_BASE +CYDEV_ANAIF_CFG_CAPSR_BASE EQU 0x40005872 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_SIZE +CYDEV_ANAIF_CFG_CAPSR_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_CFG0 +CYDEV_ANAIF_CFG_CAPSR_CFG0 EQU 0x40005872 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_CFG1 +CYDEV_ANAIF_CFG_CAPSR_CFG1 EQU 0x40005873 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_BASE +CYDEV_ANAIF_CFG_PUMP_BASE EQU 0x40005876 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_SIZE +CYDEV_ANAIF_CFG_PUMP_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_CR0 +CYDEV_ANAIF_CFG_PUMP_CR0 EQU 0x40005876 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_CR1 +CYDEV_ANAIF_CFG_PUMP_CR1 EQU 0x40005877 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_BASE +CYDEV_ANAIF_CFG_LPF0_BASE EQU 0x40005878 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_SIZE +CYDEV_ANAIF_CFG_LPF0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_CR0 +CYDEV_ANAIF_CFG_LPF0_CR0 EQU 0x40005878 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_RSVD +CYDEV_ANAIF_CFG_LPF0_RSVD EQU 0x40005879 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_BASE +CYDEV_ANAIF_CFG_LPF1_BASE EQU 0x4000587a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_SIZE +CYDEV_ANAIF_CFG_LPF1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_CR0 +CYDEV_ANAIF_CFG_LPF1_CR0 EQU 0x4000587a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_RSVD +CYDEV_ANAIF_CFG_LPF1_RSVD EQU 0x4000587b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_BASE +CYDEV_ANAIF_CFG_MISC_BASE EQU 0x4000587c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_SIZE +CYDEV_ANAIF_CFG_MISC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_CR0 +CYDEV_ANAIF_CFG_MISC_CR0 EQU 0x4000587c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BASE +CYDEV_ANAIF_CFG_DSM0_BASE EQU 0x40005880 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_SIZE +CYDEV_ANAIF_CFG_DSM0_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR0 +CYDEV_ANAIF_CFG_DSM0_CR0 EQU 0x40005880 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR1 +CYDEV_ANAIF_CFG_DSM0_CR1 EQU 0x40005881 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR2 +CYDEV_ANAIF_CFG_DSM0_CR2 EQU 0x40005882 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR3 +CYDEV_ANAIF_CFG_DSM0_CR3 EQU 0x40005883 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR4 +CYDEV_ANAIF_CFG_DSM0_CR4 EQU 0x40005884 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR5 +CYDEV_ANAIF_CFG_DSM0_CR5 EQU 0x40005885 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR6 +CYDEV_ANAIF_CFG_DSM0_CR6 EQU 0x40005886 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR7 +CYDEV_ANAIF_CFG_DSM0_CR7 EQU 0x40005887 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR8 +CYDEV_ANAIF_CFG_DSM0_CR8 EQU 0x40005888 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR9 +CYDEV_ANAIF_CFG_DSM0_CR9 EQU 0x40005889 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR10 +CYDEV_ANAIF_CFG_DSM0_CR10 EQU 0x4000588a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR11 +CYDEV_ANAIF_CFG_DSM0_CR11 EQU 0x4000588b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR12 +CYDEV_ANAIF_CFG_DSM0_CR12 EQU 0x4000588c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR13 +CYDEV_ANAIF_CFG_DSM0_CR13 EQU 0x4000588d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR14 +CYDEV_ANAIF_CFG_DSM0_CR14 EQU 0x4000588e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR15 +CYDEV_ANAIF_CFG_DSM0_CR15 EQU 0x4000588f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR16 +CYDEV_ANAIF_CFG_DSM0_CR16 EQU 0x40005890 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR17 +CYDEV_ANAIF_CFG_DSM0_CR17 EQU 0x40005891 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_REF0 +CYDEV_ANAIF_CFG_DSM0_REF0 EQU 0x40005892 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_REF1 +CYDEV_ANAIF_CFG_DSM0_REF1 EQU 0x40005893 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_REF2 +CYDEV_ANAIF_CFG_DSM0_REF2 EQU 0x40005894 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_REF3 +CYDEV_ANAIF_CFG_DSM0_REF3 EQU 0x40005895 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_DEM0 +CYDEV_ANAIF_CFG_DSM0_DEM0 EQU 0x40005896 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_DEM1 +CYDEV_ANAIF_CFG_DSM0_DEM1 EQU 0x40005897 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_TST0 +CYDEV_ANAIF_CFG_DSM0_TST0 EQU 0x40005898 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_TST1 +CYDEV_ANAIF_CFG_DSM0_TST1 EQU 0x40005899 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BUF0 +CYDEV_ANAIF_CFG_DSM0_BUF0 EQU 0x4000589a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BUF1 +CYDEV_ANAIF_CFG_DSM0_BUF1 EQU 0x4000589b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BUF2 +CYDEV_ANAIF_CFG_DSM0_BUF2 EQU 0x4000589c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BUF3 +CYDEV_ANAIF_CFG_DSM0_BUF3 EQU 0x4000589d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_MISC +CYDEV_ANAIF_CFG_DSM0_MISC EQU 0x4000589e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_RSVD1 +CYDEV_ANAIF_CFG_DSM0_RSVD1 EQU 0x4000589f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_BASE +CYDEV_ANAIF_CFG_SAR0_BASE EQU 0x40005900 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_SIZE +CYDEV_ANAIF_CFG_SAR0_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR0 +CYDEV_ANAIF_CFG_SAR0_CSR0 EQU 0x40005900 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR1 +CYDEV_ANAIF_CFG_SAR0_CSR1 EQU 0x40005901 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR2 +CYDEV_ANAIF_CFG_SAR0_CSR2 EQU 0x40005902 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR3 +CYDEV_ANAIF_CFG_SAR0_CSR3 EQU 0x40005903 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR4 +CYDEV_ANAIF_CFG_SAR0_CSR4 EQU 0x40005904 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR5 +CYDEV_ANAIF_CFG_SAR0_CSR5 EQU 0x40005905 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR6 +CYDEV_ANAIF_CFG_SAR0_CSR6 EQU 0x40005906 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_BASE +CYDEV_ANAIF_CFG_SAR1_BASE EQU 0x40005908 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_SIZE +CYDEV_ANAIF_CFG_SAR1_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR0 +CYDEV_ANAIF_CFG_SAR1_CSR0 EQU 0x40005908 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR1 +CYDEV_ANAIF_CFG_SAR1_CSR1 EQU 0x40005909 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR2 +CYDEV_ANAIF_CFG_SAR1_CSR2 EQU 0x4000590a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR3 +CYDEV_ANAIF_CFG_SAR1_CSR3 EQU 0x4000590b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR4 +CYDEV_ANAIF_CFG_SAR1_CSR4 EQU 0x4000590c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR5 +CYDEV_ANAIF_CFG_SAR1_CSR5 EQU 0x4000590d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR6 +CYDEV_ANAIF_CFG_SAR1_CSR6 EQU 0x4000590e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BASE +CYDEV_ANAIF_RT_BASE EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SIZE +CYDEV_ANAIF_RT_SIZE EQU 0x00000162 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_BASE +CYDEV_ANAIF_RT_SC0_BASE EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SIZE +CYDEV_ANAIF_RT_SC0_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW0 +CYDEV_ANAIF_RT_SC0_SW0 EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW2 +CYDEV_ANAIF_RT_SC0_SW2 EQU 0x40005a02 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW3 +CYDEV_ANAIF_RT_SC0_SW3 EQU 0x40005a03 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW4 +CYDEV_ANAIF_RT_SC0_SW4 EQU 0x40005a04 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW6 +CYDEV_ANAIF_RT_SC0_SW6 EQU 0x40005a06 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW7 +CYDEV_ANAIF_RT_SC0_SW7 EQU 0x40005a07 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW8 +CYDEV_ANAIF_RT_SC0_SW8 EQU 0x40005a08 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW10 +CYDEV_ANAIF_RT_SC0_SW10 EQU 0x40005a0a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_CLK +CYDEV_ANAIF_RT_SC0_CLK EQU 0x40005a0b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_BST +CYDEV_ANAIF_RT_SC0_BST EQU 0x40005a0c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_BASE +CYDEV_ANAIF_RT_SC1_BASE EQU 0x40005a10 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SIZE +CYDEV_ANAIF_RT_SC1_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW0 +CYDEV_ANAIF_RT_SC1_SW0 EQU 0x40005a10 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW2 +CYDEV_ANAIF_RT_SC1_SW2 EQU 0x40005a12 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW3 +CYDEV_ANAIF_RT_SC1_SW3 EQU 0x40005a13 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW4 +CYDEV_ANAIF_RT_SC1_SW4 EQU 0x40005a14 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW6 +CYDEV_ANAIF_RT_SC1_SW6 EQU 0x40005a16 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW7 +CYDEV_ANAIF_RT_SC1_SW7 EQU 0x40005a17 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW8 +CYDEV_ANAIF_RT_SC1_SW8 EQU 0x40005a18 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW10 +CYDEV_ANAIF_RT_SC1_SW10 EQU 0x40005a1a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_CLK +CYDEV_ANAIF_RT_SC1_CLK EQU 0x40005a1b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_BST +CYDEV_ANAIF_RT_SC1_BST EQU 0x40005a1c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_BASE +CYDEV_ANAIF_RT_SC2_BASE EQU 0x40005a20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SIZE +CYDEV_ANAIF_RT_SC2_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW0 +CYDEV_ANAIF_RT_SC2_SW0 EQU 0x40005a20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW2 +CYDEV_ANAIF_RT_SC2_SW2 EQU 0x40005a22 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW3 +CYDEV_ANAIF_RT_SC2_SW3 EQU 0x40005a23 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW4 +CYDEV_ANAIF_RT_SC2_SW4 EQU 0x40005a24 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW6 +CYDEV_ANAIF_RT_SC2_SW6 EQU 0x40005a26 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW7 +CYDEV_ANAIF_RT_SC2_SW7 EQU 0x40005a27 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW8 +CYDEV_ANAIF_RT_SC2_SW8 EQU 0x40005a28 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW10 +CYDEV_ANAIF_RT_SC2_SW10 EQU 0x40005a2a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_CLK +CYDEV_ANAIF_RT_SC2_CLK EQU 0x40005a2b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_BST +CYDEV_ANAIF_RT_SC2_BST EQU 0x40005a2c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_BASE +CYDEV_ANAIF_RT_SC3_BASE EQU 0x40005a30 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SIZE +CYDEV_ANAIF_RT_SC3_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW0 +CYDEV_ANAIF_RT_SC3_SW0 EQU 0x40005a30 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW2 +CYDEV_ANAIF_RT_SC3_SW2 EQU 0x40005a32 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW3 +CYDEV_ANAIF_RT_SC3_SW3 EQU 0x40005a33 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW4 +CYDEV_ANAIF_RT_SC3_SW4 EQU 0x40005a34 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW6 +CYDEV_ANAIF_RT_SC3_SW6 EQU 0x40005a36 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW7 +CYDEV_ANAIF_RT_SC3_SW7 EQU 0x40005a37 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW8 +CYDEV_ANAIF_RT_SC3_SW8 EQU 0x40005a38 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW10 +CYDEV_ANAIF_RT_SC3_SW10 EQU 0x40005a3a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_CLK +CYDEV_ANAIF_RT_SC3_CLK EQU 0x40005a3b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_BST +CYDEV_ANAIF_RT_SC3_BST EQU 0x40005a3c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_BASE +CYDEV_ANAIF_RT_DAC0_BASE EQU 0x40005a80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SIZE +CYDEV_ANAIF_RT_DAC0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SW0 +CYDEV_ANAIF_RT_DAC0_SW0 EQU 0x40005a80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SW2 +CYDEV_ANAIF_RT_DAC0_SW2 EQU 0x40005a82 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SW3 +CYDEV_ANAIF_RT_DAC0_SW3 EQU 0x40005a83 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SW4 +CYDEV_ANAIF_RT_DAC0_SW4 EQU 0x40005a84 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_STROBE +CYDEV_ANAIF_RT_DAC0_STROBE EQU 0x40005a87 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_BASE +CYDEV_ANAIF_RT_DAC1_BASE EQU 0x40005a88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SIZE +CYDEV_ANAIF_RT_DAC1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SW0 +CYDEV_ANAIF_RT_DAC1_SW0 EQU 0x40005a88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SW2 +CYDEV_ANAIF_RT_DAC1_SW2 EQU 0x40005a8a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SW3 +CYDEV_ANAIF_RT_DAC1_SW3 EQU 0x40005a8b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SW4 +CYDEV_ANAIF_RT_DAC1_SW4 EQU 0x40005a8c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_STROBE +CYDEV_ANAIF_RT_DAC1_STROBE EQU 0x40005a8f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_BASE +CYDEV_ANAIF_RT_DAC2_BASE EQU 0x40005a90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SIZE +CYDEV_ANAIF_RT_DAC2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SW0 +CYDEV_ANAIF_RT_DAC2_SW0 EQU 0x40005a90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SW2 +CYDEV_ANAIF_RT_DAC2_SW2 EQU 0x40005a92 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SW3 +CYDEV_ANAIF_RT_DAC2_SW3 EQU 0x40005a93 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SW4 +CYDEV_ANAIF_RT_DAC2_SW4 EQU 0x40005a94 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_STROBE +CYDEV_ANAIF_RT_DAC2_STROBE EQU 0x40005a97 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_BASE +CYDEV_ANAIF_RT_DAC3_BASE EQU 0x40005a98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SIZE +CYDEV_ANAIF_RT_DAC3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SW0 +CYDEV_ANAIF_RT_DAC3_SW0 EQU 0x40005a98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SW2 +CYDEV_ANAIF_RT_DAC3_SW2 EQU 0x40005a9a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SW3 +CYDEV_ANAIF_RT_DAC3_SW3 EQU 0x40005a9b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SW4 +CYDEV_ANAIF_RT_DAC3_SW4 EQU 0x40005a9c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_STROBE +CYDEV_ANAIF_RT_DAC3_STROBE EQU 0x40005a9f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_BASE +CYDEV_ANAIF_RT_CMP0_BASE EQU 0x40005ac0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SIZE +CYDEV_ANAIF_RT_CMP0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW0 +CYDEV_ANAIF_RT_CMP0_SW0 EQU 0x40005ac0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW2 +CYDEV_ANAIF_RT_CMP0_SW2 EQU 0x40005ac2 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW3 +CYDEV_ANAIF_RT_CMP0_SW3 EQU 0x40005ac3 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW4 +CYDEV_ANAIF_RT_CMP0_SW4 EQU 0x40005ac4 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW6 +CYDEV_ANAIF_RT_CMP0_SW6 EQU 0x40005ac6 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_CLK +CYDEV_ANAIF_RT_CMP0_CLK EQU 0x40005ac7 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_BASE +CYDEV_ANAIF_RT_CMP1_BASE EQU 0x40005ac8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SIZE +CYDEV_ANAIF_RT_CMP1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW0 +CYDEV_ANAIF_RT_CMP1_SW0 EQU 0x40005ac8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW2 +CYDEV_ANAIF_RT_CMP1_SW2 EQU 0x40005aca + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW3 +CYDEV_ANAIF_RT_CMP1_SW3 EQU 0x40005acb + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW4 +CYDEV_ANAIF_RT_CMP1_SW4 EQU 0x40005acc + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW6 +CYDEV_ANAIF_RT_CMP1_SW6 EQU 0x40005ace + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_CLK +CYDEV_ANAIF_RT_CMP1_CLK EQU 0x40005acf + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_BASE +CYDEV_ANAIF_RT_CMP2_BASE EQU 0x40005ad0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SIZE +CYDEV_ANAIF_RT_CMP2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW0 +CYDEV_ANAIF_RT_CMP2_SW0 EQU 0x40005ad0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW2 +CYDEV_ANAIF_RT_CMP2_SW2 EQU 0x40005ad2 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW3 +CYDEV_ANAIF_RT_CMP2_SW3 EQU 0x40005ad3 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW4 +CYDEV_ANAIF_RT_CMP2_SW4 EQU 0x40005ad4 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW6 +CYDEV_ANAIF_RT_CMP2_SW6 EQU 0x40005ad6 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_CLK +CYDEV_ANAIF_RT_CMP2_CLK EQU 0x40005ad7 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_BASE +CYDEV_ANAIF_RT_CMP3_BASE EQU 0x40005ad8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SIZE +CYDEV_ANAIF_RT_CMP3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW0 +CYDEV_ANAIF_RT_CMP3_SW0 EQU 0x40005ad8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW2 +CYDEV_ANAIF_RT_CMP3_SW2 EQU 0x40005ada + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW3 +CYDEV_ANAIF_RT_CMP3_SW3 EQU 0x40005adb + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW4 +CYDEV_ANAIF_RT_CMP3_SW4 EQU 0x40005adc + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW6 +CYDEV_ANAIF_RT_CMP3_SW6 EQU 0x40005ade + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_CLK +CYDEV_ANAIF_RT_CMP3_CLK EQU 0x40005adf + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_BASE +CYDEV_ANAIF_RT_DSM0_BASE EQU 0x40005b00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SIZE +CYDEV_ANAIF_RT_DSM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW0 +CYDEV_ANAIF_RT_DSM0_SW0 EQU 0x40005b00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW2 +CYDEV_ANAIF_RT_DSM0_SW2 EQU 0x40005b02 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW3 +CYDEV_ANAIF_RT_DSM0_SW3 EQU 0x40005b03 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW4 +CYDEV_ANAIF_RT_DSM0_SW4 EQU 0x40005b04 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW6 +CYDEV_ANAIF_RT_DSM0_SW6 EQU 0x40005b06 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_CLK +CYDEV_ANAIF_RT_DSM0_CLK EQU 0x40005b07 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_BASE +CYDEV_ANAIF_RT_SAR0_BASE EQU 0x40005b20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SIZE +CYDEV_ANAIF_RT_SAR0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW0 +CYDEV_ANAIF_RT_SAR0_SW0 EQU 0x40005b20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW2 +CYDEV_ANAIF_RT_SAR0_SW2 EQU 0x40005b22 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW3 +CYDEV_ANAIF_RT_SAR0_SW3 EQU 0x40005b23 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW4 +CYDEV_ANAIF_RT_SAR0_SW4 EQU 0x40005b24 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW6 +CYDEV_ANAIF_RT_SAR0_SW6 EQU 0x40005b26 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_CLK +CYDEV_ANAIF_RT_SAR0_CLK EQU 0x40005b27 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_BASE +CYDEV_ANAIF_RT_SAR1_BASE EQU 0x40005b28 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SIZE +CYDEV_ANAIF_RT_SAR1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW0 +CYDEV_ANAIF_RT_SAR1_SW0 EQU 0x40005b28 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW2 +CYDEV_ANAIF_RT_SAR1_SW2 EQU 0x40005b2a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW3 +CYDEV_ANAIF_RT_SAR1_SW3 EQU 0x40005b2b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW4 +CYDEV_ANAIF_RT_SAR1_SW4 EQU 0x40005b2c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW6 +CYDEV_ANAIF_RT_SAR1_SW6 EQU 0x40005b2e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_CLK +CYDEV_ANAIF_RT_SAR1_CLK EQU 0x40005b2f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_BASE +CYDEV_ANAIF_RT_OPAMP0_BASE EQU 0x40005b40 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_SIZE +CYDEV_ANAIF_RT_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_MX +CYDEV_ANAIF_RT_OPAMP0_MX EQU 0x40005b40 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_SW +CYDEV_ANAIF_RT_OPAMP0_SW EQU 0x40005b41 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_BASE +CYDEV_ANAIF_RT_OPAMP1_BASE EQU 0x40005b42 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_SIZE +CYDEV_ANAIF_RT_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_MX +CYDEV_ANAIF_RT_OPAMP1_MX EQU 0x40005b42 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_SW +CYDEV_ANAIF_RT_OPAMP1_SW EQU 0x40005b43 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_BASE +CYDEV_ANAIF_RT_OPAMP2_BASE EQU 0x40005b44 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_SIZE +CYDEV_ANAIF_RT_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_MX +CYDEV_ANAIF_RT_OPAMP2_MX EQU 0x40005b44 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_SW +CYDEV_ANAIF_RT_OPAMP2_SW EQU 0x40005b45 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_BASE +CYDEV_ANAIF_RT_OPAMP3_BASE EQU 0x40005b46 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_SIZE +CYDEV_ANAIF_RT_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_MX +CYDEV_ANAIF_RT_OPAMP3_MX EQU 0x40005b46 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_SW +CYDEV_ANAIF_RT_OPAMP3_SW EQU 0x40005b47 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_BASE +CYDEV_ANAIF_RT_LCDDAC_BASE EQU 0x40005b50 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SIZE +CYDEV_ANAIF_RT_LCDDAC_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW0 +CYDEV_ANAIF_RT_LCDDAC_SW0 EQU 0x40005b50 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW1 +CYDEV_ANAIF_RT_LCDDAC_SW1 EQU 0x40005b51 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW2 +CYDEV_ANAIF_RT_LCDDAC_SW2 EQU 0x40005b52 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW3 +CYDEV_ANAIF_RT_LCDDAC_SW3 EQU 0x40005b53 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW4 +CYDEV_ANAIF_RT_LCDDAC_SW4 EQU 0x40005b54 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_BASE +CYDEV_ANAIF_RT_SC_BASE EQU 0x40005b56 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_SIZE +CYDEV_ANAIF_RT_SC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_MISC +CYDEV_ANAIF_RT_SC_MISC EQU 0x40005b56 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_BASE +CYDEV_ANAIF_RT_BUS_BASE EQU 0x40005b58 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SIZE +CYDEV_ANAIF_RT_BUS_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SW0 +CYDEV_ANAIF_RT_BUS_SW0 EQU 0x40005b58 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SW2 +CYDEV_ANAIF_RT_BUS_SW2 EQU 0x40005b5a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SW3 +CYDEV_ANAIF_RT_BUS_SW3 EQU 0x40005b5b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_BASE +CYDEV_ANAIF_RT_DFT_BASE EQU 0x40005b5c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_SIZE +CYDEV_ANAIF_RT_DFT_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR0 +CYDEV_ANAIF_RT_DFT_CR0 EQU 0x40005b5c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR1 +CYDEV_ANAIF_RT_DFT_CR1 EQU 0x40005b5d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR2 +CYDEV_ANAIF_RT_DFT_CR2 EQU 0x40005b5e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR3 +CYDEV_ANAIF_RT_DFT_CR3 EQU 0x40005b5f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR4 +CYDEV_ANAIF_RT_DFT_CR4 EQU 0x40005b60 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR5 +CYDEV_ANAIF_RT_DFT_CR5 EQU 0x40005b61 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_BASE +CYDEV_ANAIF_WRK_BASE EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SIZE +CYDEV_ANAIF_WRK_SIZE EQU 0x00000029 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_BASE +CYDEV_ANAIF_WRK_DAC0_BASE EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_SIZE +CYDEV_ANAIF_WRK_DAC0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_D +CYDEV_ANAIF_WRK_DAC0_D EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_BASE +CYDEV_ANAIF_WRK_DAC1_BASE EQU 0x40005b81 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_SIZE +CYDEV_ANAIF_WRK_DAC1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_D +CYDEV_ANAIF_WRK_DAC1_D EQU 0x40005b81 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_BASE +CYDEV_ANAIF_WRK_DAC2_BASE EQU 0x40005b82 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_SIZE +CYDEV_ANAIF_WRK_DAC2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_D +CYDEV_ANAIF_WRK_DAC2_D EQU 0x40005b82 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_BASE +CYDEV_ANAIF_WRK_DAC3_BASE EQU 0x40005b83 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_SIZE +CYDEV_ANAIF_WRK_DAC3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_D +CYDEV_ANAIF_WRK_DAC3_D EQU 0x40005b83 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_BASE +CYDEV_ANAIF_WRK_DSM0_BASE EQU 0x40005b88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_SIZE +CYDEV_ANAIF_WRK_DSM0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_OUT0 +CYDEV_ANAIF_WRK_DSM0_OUT0 EQU 0x40005b88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_OUT1 +CYDEV_ANAIF_WRK_DSM0_OUT1 EQU 0x40005b89 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_BASE +CYDEV_ANAIF_WRK_LUT_BASE EQU 0x40005b90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_SIZE +CYDEV_ANAIF_WRK_LUT_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_SR +CYDEV_ANAIF_WRK_LUT_SR EQU 0x40005b90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_WRK1 +CYDEV_ANAIF_WRK_LUT_WRK1 EQU 0x40005b91 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_MSK +CYDEV_ANAIF_WRK_LUT_MSK EQU 0x40005b92 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_CLK +CYDEV_ANAIF_WRK_LUT_CLK EQU 0x40005b93 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_CPTR +CYDEV_ANAIF_WRK_LUT_CPTR EQU 0x40005b94 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_BASE +CYDEV_ANAIF_WRK_CMP_BASE EQU 0x40005b96 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_SIZE +CYDEV_ANAIF_WRK_CMP_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_WRK +CYDEV_ANAIF_WRK_CMP_WRK EQU 0x40005b96 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_TST +CYDEV_ANAIF_WRK_CMP_TST EQU 0x40005b97 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_BASE +CYDEV_ANAIF_WRK_SC_BASE EQU 0x40005b98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_SIZE +CYDEV_ANAIF_WRK_SC_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_SR +CYDEV_ANAIF_WRK_SC_SR EQU 0x40005b98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_WRK1 +CYDEV_ANAIF_WRK_SC_WRK1 EQU 0x40005b99 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_MSK +CYDEV_ANAIF_WRK_SC_MSK EQU 0x40005b9a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_CMPINV +CYDEV_ANAIF_WRK_SC_CMPINV EQU 0x40005b9b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_CPTR +CYDEV_ANAIF_WRK_SC_CPTR EQU 0x40005b9c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_BASE +CYDEV_ANAIF_WRK_SAR0_BASE EQU 0x40005ba0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_SIZE +CYDEV_ANAIF_WRK_SAR0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_WRK0 +CYDEV_ANAIF_WRK_SAR0_WRK0 EQU 0x40005ba0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_WRK1 +CYDEV_ANAIF_WRK_SAR0_WRK1 EQU 0x40005ba1 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_BASE +CYDEV_ANAIF_WRK_SAR1_BASE EQU 0x40005ba2 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_SIZE +CYDEV_ANAIF_WRK_SAR1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_WRK0 +CYDEV_ANAIF_WRK_SAR1_WRK0 EQU 0x40005ba2 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_WRK1 +CYDEV_ANAIF_WRK_SAR1_WRK1 EQU 0x40005ba3 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_BASE +CYDEV_ANAIF_WRK_SARS_BASE EQU 0x40005ba8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_SIZE +CYDEV_ANAIF_WRK_SARS_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_SOF +CYDEV_ANAIF_WRK_SARS_SOF EQU 0x40005ba8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_BASE +CYDEV_USB_BASE EQU 0x40006000 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIZE +CYDEV_USB_SIZE EQU 0x00000300 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR0 +CYDEV_USB_EP0_DR0 EQU 0x40006000 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR1 +CYDEV_USB_EP0_DR1 EQU 0x40006001 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR2 +CYDEV_USB_EP0_DR2 EQU 0x40006002 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR3 +CYDEV_USB_EP0_DR3 EQU 0x40006003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR4 +CYDEV_USB_EP0_DR4 EQU 0x40006004 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR5 +CYDEV_USB_EP0_DR5 EQU 0x40006005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR6 +CYDEV_USB_EP0_DR6 EQU 0x40006006 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR7 +CYDEV_USB_EP0_DR7 EQU 0x40006007 + ENDIF + IF :LNOT::DEF:CYDEV_USB_CR0 +CYDEV_USB_CR0 EQU 0x40006008 + ENDIF + IF :LNOT::DEF:CYDEV_USB_CR1 +CYDEV_USB_CR1 EQU 0x40006009 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP_INT_EN +CYDEV_USB_SIE_EP_INT_EN EQU 0x4000600a + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP_INT_SR +CYDEV_USB_SIE_EP_INT_SR EQU 0x4000600b + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_BASE +CYDEV_USB_SIE_EP1_BASE EQU 0x4000600c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_SIZE +CYDEV_USB_SIE_EP1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_CNT0 +CYDEV_USB_SIE_EP1_CNT0 EQU 0x4000600c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_CNT1 +CYDEV_USB_SIE_EP1_CNT1 EQU 0x4000600d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_CR0 +CYDEV_USB_SIE_EP1_CR0 EQU 0x4000600e + ENDIF + IF :LNOT::DEF:CYDEV_USB_USBIO_CR0 +CYDEV_USB_USBIO_CR0 EQU 0x40006010 + ENDIF + IF :LNOT::DEF:CYDEV_USB_USBIO_CR1 +CYDEV_USB_USBIO_CR1 EQU 0x40006012 + ENDIF + IF :LNOT::DEF:CYDEV_USB_DYN_RECONFIG +CYDEV_USB_DYN_RECONFIG EQU 0x40006014 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SOF0 +CYDEV_USB_SOF0 EQU 0x40006018 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SOF1 +CYDEV_USB_SOF1 EQU 0x40006019 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_BASE +CYDEV_USB_SIE_EP2_BASE EQU 0x4000601c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_SIZE +CYDEV_USB_SIE_EP2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_CNT0 +CYDEV_USB_SIE_EP2_CNT0 EQU 0x4000601c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_CNT1 +CYDEV_USB_SIE_EP2_CNT1 EQU 0x4000601d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_CR0 +CYDEV_USB_SIE_EP2_CR0 EQU 0x4000601e + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_CR +CYDEV_USB_EP0_CR EQU 0x40006028 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_CNT +CYDEV_USB_EP0_CNT EQU 0x40006029 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_BASE +CYDEV_USB_SIE_EP3_BASE EQU 0x4000602c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_SIZE +CYDEV_USB_SIE_EP3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_CNT0 +CYDEV_USB_SIE_EP3_CNT0 EQU 0x4000602c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_CNT1 +CYDEV_USB_SIE_EP3_CNT1 EQU 0x4000602d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_CR0 +CYDEV_USB_SIE_EP3_CR0 EQU 0x4000602e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_BASE +CYDEV_USB_SIE_EP4_BASE EQU 0x4000603c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_SIZE +CYDEV_USB_SIE_EP4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_CNT0 +CYDEV_USB_SIE_EP4_CNT0 EQU 0x4000603c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_CNT1 +CYDEV_USB_SIE_EP4_CNT1 EQU 0x4000603d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_CR0 +CYDEV_USB_SIE_EP4_CR0 EQU 0x4000603e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_BASE +CYDEV_USB_SIE_EP5_BASE EQU 0x4000604c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_SIZE +CYDEV_USB_SIE_EP5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_CNT0 +CYDEV_USB_SIE_EP5_CNT0 EQU 0x4000604c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_CNT1 +CYDEV_USB_SIE_EP5_CNT1 EQU 0x4000604d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_CR0 +CYDEV_USB_SIE_EP5_CR0 EQU 0x4000604e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_BASE +CYDEV_USB_SIE_EP6_BASE EQU 0x4000605c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_SIZE +CYDEV_USB_SIE_EP6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_CNT0 +CYDEV_USB_SIE_EP6_CNT0 EQU 0x4000605c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_CNT1 +CYDEV_USB_SIE_EP6_CNT1 EQU 0x4000605d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_CR0 +CYDEV_USB_SIE_EP6_CR0 EQU 0x4000605e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_BASE +CYDEV_USB_SIE_EP7_BASE EQU 0x4000606c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_SIZE +CYDEV_USB_SIE_EP7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_CNT0 +CYDEV_USB_SIE_EP7_CNT0 EQU 0x4000606c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_CNT1 +CYDEV_USB_SIE_EP7_CNT1 EQU 0x4000606d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_CR0 +CYDEV_USB_SIE_EP7_CR0 EQU 0x4000606e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_BASE +CYDEV_USB_SIE_EP8_BASE EQU 0x4000607c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_SIZE +CYDEV_USB_SIE_EP8_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_CNT0 +CYDEV_USB_SIE_EP8_CNT0 EQU 0x4000607c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_CNT1 +CYDEV_USB_SIE_EP8_CNT1 EQU 0x4000607d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_CR0 +CYDEV_USB_SIE_EP8_CR0 EQU 0x4000607e + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_BASE +CYDEV_USB_ARB_EP1_BASE EQU 0x40006080 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_SIZE +CYDEV_USB_ARB_EP1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_CFG +CYDEV_USB_ARB_EP1_CFG EQU 0x40006080 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_INT_EN +CYDEV_USB_ARB_EP1_INT_EN EQU 0x40006081 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_SR +CYDEV_USB_ARB_EP1_SR EQU 0x40006082 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_BASE +CYDEV_USB_ARB_RW1_BASE EQU 0x40006084 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_SIZE +CYDEV_USB_ARB_RW1_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_WA +CYDEV_USB_ARB_RW1_WA EQU 0x40006084 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_WA_MSB +CYDEV_USB_ARB_RW1_WA_MSB EQU 0x40006085 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_RA +CYDEV_USB_ARB_RW1_RA EQU 0x40006086 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_RA_MSB +CYDEV_USB_ARB_RW1_RA_MSB EQU 0x40006087 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_DR +CYDEV_USB_ARB_RW1_DR EQU 0x40006088 + ENDIF + IF :LNOT::DEF:CYDEV_USB_BUF_SIZE +CYDEV_USB_BUF_SIZE EQU 0x4000608c + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP_ACTIVE +CYDEV_USB_EP_ACTIVE EQU 0x4000608e + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP_TYPE +CYDEV_USB_EP_TYPE EQU 0x4000608f + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_BASE +CYDEV_USB_ARB_EP2_BASE EQU 0x40006090 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_SIZE +CYDEV_USB_ARB_EP2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_CFG +CYDEV_USB_ARB_EP2_CFG EQU 0x40006090 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_INT_EN +CYDEV_USB_ARB_EP2_INT_EN EQU 0x40006091 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_SR +CYDEV_USB_ARB_EP2_SR EQU 0x40006092 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_BASE +CYDEV_USB_ARB_RW2_BASE EQU 0x40006094 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_SIZE +CYDEV_USB_ARB_RW2_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_WA +CYDEV_USB_ARB_RW2_WA EQU 0x40006094 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_WA_MSB +CYDEV_USB_ARB_RW2_WA_MSB EQU 0x40006095 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_RA +CYDEV_USB_ARB_RW2_RA EQU 0x40006096 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_RA_MSB +CYDEV_USB_ARB_RW2_RA_MSB EQU 0x40006097 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_DR +CYDEV_USB_ARB_RW2_DR EQU 0x40006098 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_CFG +CYDEV_USB_ARB_CFG EQU 0x4000609c + ENDIF + IF :LNOT::DEF:CYDEV_USB_USB_CLK_EN +CYDEV_USB_USB_CLK_EN EQU 0x4000609d + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_INT_EN +CYDEV_USB_ARB_INT_EN EQU 0x4000609e + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_INT_SR +CYDEV_USB_ARB_INT_SR EQU 0x4000609f + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_BASE +CYDEV_USB_ARB_EP3_BASE EQU 0x400060a0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_SIZE +CYDEV_USB_ARB_EP3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_CFG +CYDEV_USB_ARB_EP3_CFG EQU 0x400060a0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_INT_EN +CYDEV_USB_ARB_EP3_INT_EN EQU 0x400060a1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_SR +CYDEV_USB_ARB_EP3_SR EQU 0x400060a2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_BASE +CYDEV_USB_ARB_RW3_BASE EQU 0x400060a4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_SIZE +CYDEV_USB_ARB_RW3_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_WA +CYDEV_USB_ARB_RW3_WA EQU 0x400060a4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_WA_MSB +CYDEV_USB_ARB_RW3_WA_MSB EQU 0x400060a5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_RA +CYDEV_USB_ARB_RW3_RA EQU 0x400060a6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_RA_MSB +CYDEV_USB_ARB_RW3_RA_MSB EQU 0x400060a7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_DR +CYDEV_USB_ARB_RW3_DR EQU 0x400060a8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_CWA +CYDEV_USB_CWA EQU 0x400060ac + ENDIF + IF :LNOT::DEF:CYDEV_USB_CWA_MSB +CYDEV_USB_CWA_MSB EQU 0x400060ad + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_BASE +CYDEV_USB_ARB_EP4_BASE EQU 0x400060b0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_SIZE +CYDEV_USB_ARB_EP4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_CFG +CYDEV_USB_ARB_EP4_CFG EQU 0x400060b0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_INT_EN +CYDEV_USB_ARB_EP4_INT_EN EQU 0x400060b1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_SR +CYDEV_USB_ARB_EP4_SR EQU 0x400060b2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_BASE +CYDEV_USB_ARB_RW4_BASE EQU 0x400060b4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_SIZE +CYDEV_USB_ARB_RW4_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_WA +CYDEV_USB_ARB_RW4_WA EQU 0x400060b4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_WA_MSB +CYDEV_USB_ARB_RW4_WA_MSB EQU 0x400060b5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_RA +CYDEV_USB_ARB_RW4_RA EQU 0x400060b6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_RA_MSB +CYDEV_USB_ARB_RW4_RA_MSB EQU 0x400060b7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_DR +CYDEV_USB_ARB_RW4_DR EQU 0x400060b8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_DMA_THRES +CYDEV_USB_DMA_THRES EQU 0x400060bc + ENDIF + IF :LNOT::DEF:CYDEV_USB_DMA_THRES_MSB +CYDEV_USB_DMA_THRES_MSB EQU 0x400060bd + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_BASE +CYDEV_USB_ARB_EP5_BASE EQU 0x400060c0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_SIZE +CYDEV_USB_ARB_EP5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_CFG +CYDEV_USB_ARB_EP5_CFG EQU 0x400060c0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_INT_EN +CYDEV_USB_ARB_EP5_INT_EN EQU 0x400060c1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_SR +CYDEV_USB_ARB_EP5_SR EQU 0x400060c2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_BASE +CYDEV_USB_ARB_RW5_BASE EQU 0x400060c4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_SIZE +CYDEV_USB_ARB_RW5_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_WA +CYDEV_USB_ARB_RW5_WA EQU 0x400060c4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_WA_MSB +CYDEV_USB_ARB_RW5_WA_MSB EQU 0x400060c5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_RA +CYDEV_USB_ARB_RW5_RA EQU 0x400060c6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_RA_MSB +CYDEV_USB_ARB_RW5_RA_MSB EQU 0x400060c7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_DR +CYDEV_USB_ARB_RW5_DR EQU 0x400060c8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_BUS_RST_CNT +CYDEV_USB_BUS_RST_CNT EQU 0x400060cc + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_BASE +CYDEV_USB_ARB_EP6_BASE EQU 0x400060d0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_SIZE +CYDEV_USB_ARB_EP6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_CFG +CYDEV_USB_ARB_EP6_CFG EQU 0x400060d0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_INT_EN +CYDEV_USB_ARB_EP6_INT_EN EQU 0x400060d1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_SR +CYDEV_USB_ARB_EP6_SR EQU 0x400060d2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_BASE +CYDEV_USB_ARB_RW6_BASE EQU 0x400060d4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_SIZE +CYDEV_USB_ARB_RW6_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_WA +CYDEV_USB_ARB_RW6_WA EQU 0x400060d4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_WA_MSB +CYDEV_USB_ARB_RW6_WA_MSB EQU 0x400060d5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_RA +CYDEV_USB_ARB_RW6_RA EQU 0x400060d6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_RA_MSB +CYDEV_USB_ARB_RW6_RA_MSB EQU 0x400060d7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_DR +CYDEV_USB_ARB_RW6_DR EQU 0x400060d8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_BASE +CYDEV_USB_ARB_EP7_BASE EQU 0x400060e0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_SIZE +CYDEV_USB_ARB_EP7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_CFG +CYDEV_USB_ARB_EP7_CFG EQU 0x400060e0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_INT_EN +CYDEV_USB_ARB_EP7_INT_EN EQU 0x400060e1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_SR +CYDEV_USB_ARB_EP7_SR EQU 0x400060e2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_BASE +CYDEV_USB_ARB_RW7_BASE EQU 0x400060e4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_SIZE +CYDEV_USB_ARB_RW7_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_WA +CYDEV_USB_ARB_RW7_WA EQU 0x400060e4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_WA_MSB +CYDEV_USB_ARB_RW7_WA_MSB EQU 0x400060e5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_RA +CYDEV_USB_ARB_RW7_RA EQU 0x400060e6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_RA_MSB +CYDEV_USB_ARB_RW7_RA_MSB EQU 0x400060e7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_DR +CYDEV_USB_ARB_RW7_DR EQU 0x400060e8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_BASE +CYDEV_USB_ARB_EP8_BASE EQU 0x400060f0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_SIZE +CYDEV_USB_ARB_EP8_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_CFG +CYDEV_USB_ARB_EP8_CFG EQU 0x400060f0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_INT_EN +CYDEV_USB_ARB_EP8_INT_EN EQU 0x400060f1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_SR +CYDEV_USB_ARB_EP8_SR EQU 0x400060f2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_BASE +CYDEV_USB_ARB_RW8_BASE EQU 0x400060f4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_SIZE +CYDEV_USB_ARB_RW8_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_WA +CYDEV_USB_ARB_RW8_WA EQU 0x400060f4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_WA_MSB +CYDEV_USB_ARB_RW8_WA_MSB EQU 0x400060f5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_RA +CYDEV_USB_ARB_RW8_RA EQU 0x400060f6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_RA_MSB +CYDEV_USB_ARB_RW8_RA_MSB EQU 0x400060f7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_DR +CYDEV_USB_ARB_RW8_DR EQU 0x400060f8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_BASE +CYDEV_USB_MEM_BASE EQU 0x40006100 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_SIZE +CYDEV_USB_MEM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_DATA_MBASE +CYDEV_USB_MEM_DATA_MBASE EQU 0x40006100 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_DATA_MSIZE +CYDEV_USB_MEM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_BASE +CYDEV_UWRK_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_SIZE +CYDEV_UWRK_SIZE EQU 0x00000b60 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_BASE +CYDEV_UWRK_UWRK8_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_SIZE +CYDEV_UWRK_UWRK8_SIZE EQU 0x000003b0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_BASE +CYDEV_UWRK_UWRK8_B0_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_SIZE +CYDEV_UWRK_UWRK8_B0_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_A0 +CYDEV_UWRK_UWRK8_B0_UDB00_A0 EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_A0 +CYDEV_UWRK_UWRK8_B0_UDB01_A0 EQU 0x40006401 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_A0 +CYDEV_UWRK_UWRK8_B0_UDB02_A0 EQU 0x40006402 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_A0 +CYDEV_UWRK_UWRK8_B0_UDB03_A0 EQU 0x40006403 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_A0 +CYDEV_UWRK_UWRK8_B0_UDB04_A0 EQU 0x40006404 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_A0 +CYDEV_UWRK_UWRK8_B0_UDB05_A0 EQU 0x40006405 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_A0 +CYDEV_UWRK_UWRK8_B0_UDB06_A0 EQU 0x40006406 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_A0 +CYDEV_UWRK_UWRK8_B0_UDB07_A0 EQU 0x40006407 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_A0 +CYDEV_UWRK_UWRK8_B0_UDB08_A0 EQU 0x40006408 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_A0 +CYDEV_UWRK_UWRK8_B0_UDB09_A0 EQU 0x40006409 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_A0 +CYDEV_UWRK_UWRK8_B0_UDB10_A0 EQU 0x4000640a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_A0 +CYDEV_UWRK_UWRK8_B0_UDB11_A0 EQU 0x4000640b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_A0 +CYDEV_UWRK_UWRK8_B0_UDB12_A0 EQU 0x4000640c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_A0 +CYDEV_UWRK_UWRK8_B0_UDB13_A0 EQU 0x4000640d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_A0 +CYDEV_UWRK_UWRK8_B0_UDB14_A0 EQU 0x4000640e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_A0 +CYDEV_UWRK_UWRK8_B0_UDB15_A0 EQU 0x4000640f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_A1 +CYDEV_UWRK_UWRK8_B0_UDB00_A1 EQU 0x40006410 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_A1 +CYDEV_UWRK_UWRK8_B0_UDB01_A1 EQU 0x40006411 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_A1 +CYDEV_UWRK_UWRK8_B0_UDB02_A1 EQU 0x40006412 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_A1 +CYDEV_UWRK_UWRK8_B0_UDB03_A1 EQU 0x40006413 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_A1 +CYDEV_UWRK_UWRK8_B0_UDB04_A1 EQU 0x40006414 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_A1 +CYDEV_UWRK_UWRK8_B0_UDB05_A1 EQU 0x40006415 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_A1 +CYDEV_UWRK_UWRK8_B0_UDB06_A1 EQU 0x40006416 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_A1 +CYDEV_UWRK_UWRK8_B0_UDB07_A1 EQU 0x40006417 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_A1 +CYDEV_UWRK_UWRK8_B0_UDB08_A1 EQU 0x40006418 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_A1 +CYDEV_UWRK_UWRK8_B0_UDB09_A1 EQU 0x40006419 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_A1 +CYDEV_UWRK_UWRK8_B0_UDB10_A1 EQU 0x4000641a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_A1 +CYDEV_UWRK_UWRK8_B0_UDB11_A1 EQU 0x4000641b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_A1 +CYDEV_UWRK_UWRK8_B0_UDB12_A1 EQU 0x4000641c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_A1 +CYDEV_UWRK_UWRK8_B0_UDB13_A1 EQU 0x4000641d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_A1 +CYDEV_UWRK_UWRK8_B0_UDB14_A1 EQU 0x4000641e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_A1 +CYDEV_UWRK_UWRK8_B0_UDB15_A1 EQU 0x4000641f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_D0 +CYDEV_UWRK_UWRK8_B0_UDB00_D0 EQU 0x40006420 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_D0 +CYDEV_UWRK_UWRK8_B0_UDB01_D0 EQU 0x40006421 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_D0 +CYDEV_UWRK_UWRK8_B0_UDB02_D0 EQU 0x40006422 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_D0 +CYDEV_UWRK_UWRK8_B0_UDB03_D0 EQU 0x40006423 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_D0 +CYDEV_UWRK_UWRK8_B0_UDB04_D0 EQU 0x40006424 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_D0 +CYDEV_UWRK_UWRK8_B0_UDB05_D0 EQU 0x40006425 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_D0 +CYDEV_UWRK_UWRK8_B0_UDB06_D0 EQU 0x40006426 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_D0 +CYDEV_UWRK_UWRK8_B0_UDB07_D0 EQU 0x40006427 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_D0 +CYDEV_UWRK_UWRK8_B0_UDB08_D0 EQU 0x40006428 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_D0 +CYDEV_UWRK_UWRK8_B0_UDB09_D0 EQU 0x40006429 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_D0 +CYDEV_UWRK_UWRK8_B0_UDB10_D0 EQU 0x4000642a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_D0 +CYDEV_UWRK_UWRK8_B0_UDB11_D0 EQU 0x4000642b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_D0 +CYDEV_UWRK_UWRK8_B0_UDB12_D0 EQU 0x4000642c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_D0 +CYDEV_UWRK_UWRK8_B0_UDB13_D0 EQU 0x4000642d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_D0 +CYDEV_UWRK_UWRK8_B0_UDB14_D0 EQU 0x4000642e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_D0 +CYDEV_UWRK_UWRK8_B0_UDB15_D0 EQU 0x4000642f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_D1 +CYDEV_UWRK_UWRK8_B0_UDB00_D1 EQU 0x40006430 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_D1 +CYDEV_UWRK_UWRK8_B0_UDB01_D1 EQU 0x40006431 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_D1 +CYDEV_UWRK_UWRK8_B0_UDB02_D1 EQU 0x40006432 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_D1 +CYDEV_UWRK_UWRK8_B0_UDB03_D1 EQU 0x40006433 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_D1 +CYDEV_UWRK_UWRK8_B0_UDB04_D1 EQU 0x40006434 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_D1 +CYDEV_UWRK_UWRK8_B0_UDB05_D1 EQU 0x40006435 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_D1 +CYDEV_UWRK_UWRK8_B0_UDB06_D1 EQU 0x40006436 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_D1 +CYDEV_UWRK_UWRK8_B0_UDB07_D1 EQU 0x40006437 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_D1 +CYDEV_UWRK_UWRK8_B0_UDB08_D1 EQU 0x40006438 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_D1 +CYDEV_UWRK_UWRK8_B0_UDB09_D1 EQU 0x40006439 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_D1 +CYDEV_UWRK_UWRK8_B0_UDB10_D1 EQU 0x4000643a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_D1 +CYDEV_UWRK_UWRK8_B0_UDB11_D1 EQU 0x4000643b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_D1 +CYDEV_UWRK_UWRK8_B0_UDB12_D1 EQU 0x4000643c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_D1 +CYDEV_UWRK_UWRK8_B0_UDB13_D1 EQU 0x4000643d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_D1 +CYDEV_UWRK_UWRK8_B0_UDB14_D1 EQU 0x4000643e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_D1 +CYDEV_UWRK_UWRK8_B0_UDB15_D1 EQU 0x4000643f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_F0 +CYDEV_UWRK_UWRK8_B0_UDB00_F0 EQU 0x40006440 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_F0 +CYDEV_UWRK_UWRK8_B0_UDB01_F0 EQU 0x40006441 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_F0 +CYDEV_UWRK_UWRK8_B0_UDB02_F0 EQU 0x40006442 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_F0 +CYDEV_UWRK_UWRK8_B0_UDB03_F0 EQU 0x40006443 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_F0 +CYDEV_UWRK_UWRK8_B0_UDB04_F0 EQU 0x40006444 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_F0 +CYDEV_UWRK_UWRK8_B0_UDB05_F0 EQU 0x40006445 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_F0 +CYDEV_UWRK_UWRK8_B0_UDB06_F0 EQU 0x40006446 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_F0 +CYDEV_UWRK_UWRK8_B0_UDB07_F0 EQU 0x40006447 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_F0 +CYDEV_UWRK_UWRK8_B0_UDB08_F0 EQU 0x40006448 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_F0 +CYDEV_UWRK_UWRK8_B0_UDB09_F0 EQU 0x40006449 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_F0 +CYDEV_UWRK_UWRK8_B0_UDB10_F0 EQU 0x4000644a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_F0 +CYDEV_UWRK_UWRK8_B0_UDB11_F0 EQU 0x4000644b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_F0 +CYDEV_UWRK_UWRK8_B0_UDB12_F0 EQU 0x4000644c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_F0 +CYDEV_UWRK_UWRK8_B0_UDB13_F0 EQU 0x4000644d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_F0 +CYDEV_UWRK_UWRK8_B0_UDB14_F0 EQU 0x4000644e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_F0 +CYDEV_UWRK_UWRK8_B0_UDB15_F0 EQU 0x4000644f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_F1 +CYDEV_UWRK_UWRK8_B0_UDB00_F1 EQU 0x40006450 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_F1 +CYDEV_UWRK_UWRK8_B0_UDB01_F1 EQU 0x40006451 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_F1 +CYDEV_UWRK_UWRK8_B0_UDB02_F1 EQU 0x40006452 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_F1 +CYDEV_UWRK_UWRK8_B0_UDB03_F1 EQU 0x40006453 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_F1 +CYDEV_UWRK_UWRK8_B0_UDB04_F1 EQU 0x40006454 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_F1 +CYDEV_UWRK_UWRK8_B0_UDB05_F1 EQU 0x40006455 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_F1 +CYDEV_UWRK_UWRK8_B0_UDB06_F1 EQU 0x40006456 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_F1 +CYDEV_UWRK_UWRK8_B0_UDB07_F1 EQU 0x40006457 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_F1 +CYDEV_UWRK_UWRK8_B0_UDB08_F1 EQU 0x40006458 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_F1 +CYDEV_UWRK_UWRK8_B0_UDB09_F1 EQU 0x40006459 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_F1 +CYDEV_UWRK_UWRK8_B0_UDB10_F1 EQU 0x4000645a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_F1 +CYDEV_UWRK_UWRK8_B0_UDB11_F1 EQU 0x4000645b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_F1 +CYDEV_UWRK_UWRK8_B0_UDB12_F1 EQU 0x4000645c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_F1 +CYDEV_UWRK_UWRK8_B0_UDB13_F1 EQU 0x4000645d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_F1 +CYDEV_UWRK_UWRK8_B0_UDB14_F1 EQU 0x4000645e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_F1 +CYDEV_UWRK_UWRK8_B0_UDB15_F1 EQU 0x4000645f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_ST +CYDEV_UWRK_UWRK8_B0_UDB00_ST EQU 0x40006460 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_ST +CYDEV_UWRK_UWRK8_B0_UDB01_ST EQU 0x40006461 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_ST +CYDEV_UWRK_UWRK8_B0_UDB02_ST EQU 0x40006462 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_ST +CYDEV_UWRK_UWRK8_B0_UDB03_ST EQU 0x40006463 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_ST +CYDEV_UWRK_UWRK8_B0_UDB04_ST EQU 0x40006464 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_ST +CYDEV_UWRK_UWRK8_B0_UDB05_ST EQU 0x40006465 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_ST +CYDEV_UWRK_UWRK8_B0_UDB06_ST EQU 0x40006466 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_ST +CYDEV_UWRK_UWRK8_B0_UDB07_ST EQU 0x40006467 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_ST +CYDEV_UWRK_UWRK8_B0_UDB08_ST EQU 0x40006468 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_ST +CYDEV_UWRK_UWRK8_B0_UDB09_ST EQU 0x40006469 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_ST +CYDEV_UWRK_UWRK8_B0_UDB10_ST EQU 0x4000646a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_ST +CYDEV_UWRK_UWRK8_B0_UDB11_ST EQU 0x4000646b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_ST +CYDEV_UWRK_UWRK8_B0_UDB12_ST EQU 0x4000646c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_ST +CYDEV_UWRK_UWRK8_B0_UDB13_ST EQU 0x4000646d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_ST +CYDEV_UWRK_UWRK8_B0_UDB14_ST EQU 0x4000646e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_ST +CYDEV_UWRK_UWRK8_B0_UDB15_ST EQU 0x4000646f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_CTL +CYDEV_UWRK_UWRK8_B0_UDB00_CTL EQU 0x40006470 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_CTL +CYDEV_UWRK_UWRK8_B0_UDB01_CTL EQU 0x40006471 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_CTL +CYDEV_UWRK_UWRK8_B0_UDB02_CTL EQU 0x40006472 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_CTL +CYDEV_UWRK_UWRK8_B0_UDB03_CTL EQU 0x40006473 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_CTL +CYDEV_UWRK_UWRK8_B0_UDB04_CTL EQU 0x40006474 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_CTL +CYDEV_UWRK_UWRK8_B0_UDB05_CTL EQU 0x40006475 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_CTL +CYDEV_UWRK_UWRK8_B0_UDB06_CTL EQU 0x40006476 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_CTL +CYDEV_UWRK_UWRK8_B0_UDB07_CTL EQU 0x40006477 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_CTL +CYDEV_UWRK_UWRK8_B0_UDB08_CTL EQU 0x40006478 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_CTL +CYDEV_UWRK_UWRK8_B0_UDB09_CTL EQU 0x40006479 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_CTL +CYDEV_UWRK_UWRK8_B0_UDB10_CTL EQU 0x4000647a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_CTL +CYDEV_UWRK_UWRK8_B0_UDB11_CTL EQU 0x4000647b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_CTL +CYDEV_UWRK_UWRK8_B0_UDB12_CTL EQU 0x4000647c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_CTL +CYDEV_UWRK_UWRK8_B0_UDB13_CTL EQU 0x4000647d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_CTL +CYDEV_UWRK_UWRK8_B0_UDB14_CTL EQU 0x4000647e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_CTL +CYDEV_UWRK_UWRK8_B0_UDB15_CTL EQU 0x4000647f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_MSK +CYDEV_UWRK_UWRK8_B0_UDB00_MSK EQU 0x40006480 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_MSK +CYDEV_UWRK_UWRK8_B0_UDB01_MSK EQU 0x40006481 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_MSK +CYDEV_UWRK_UWRK8_B0_UDB02_MSK EQU 0x40006482 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_MSK +CYDEV_UWRK_UWRK8_B0_UDB03_MSK EQU 0x40006483 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_MSK +CYDEV_UWRK_UWRK8_B0_UDB04_MSK EQU 0x40006484 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_MSK +CYDEV_UWRK_UWRK8_B0_UDB05_MSK EQU 0x40006485 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_MSK +CYDEV_UWRK_UWRK8_B0_UDB06_MSK EQU 0x40006486 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_MSK +CYDEV_UWRK_UWRK8_B0_UDB07_MSK EQU 0x40006487 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_MSK +CYDEV_UWRK_UWRK8_B0_UDB08_MSK EQU 0x40006488 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_MSK +CYDEV_UWRK_UWRK8_B0_UDB09_MSK EQU 0x40006489 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_MSK +CYDEV_UWRK_UWRK8_B0_UDB10_MSK EQU 0x4000648a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_MSK +CYDEV_UWRK_UWRK8_B0_UDB11_MSK EQU 0x4000648b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_MSK +CYDEV_UWRK_UWRK8_B0_UDB12_MSK EQU 0x4000648c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_MSK +CYDEV_UWRK_UWRK8_B0_UDB13_MSK EQU 0x4000648d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_MSK +CYDEV_UWRK_UWRK8_B0_UDB14_MSK EQU 0x4000648e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_MSK +CYDEV_UWRK_UWRK8_B0_UDB15_MSK EQU 0x4000648f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_ACTL +CYDEV_UWRK_UWRK8_B0_UDB00_ACTL EQU 0x40006490 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_ACTL +CYDEV_UWRK_UWRK8_B0_UDB01_ACTL EQU 0x40006491 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_ACTL +CYDEV_UWRK_UWRK8_B0_UDB02_ACTL EQU 0x40006492 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_ACTL +CYDEV_UWRK_UWRK8_B0_UDB03_ACTL EQU 0x40006493 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_ACTL +CYDEV_UWRK_UWRK8_B0_UDB04_ACTL EQU 0x40006494 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_ACTL +CYDEV_UWRK_UWRK8_B0_UDB05_ACTL EQU 0x40006495 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_ACTL +CYDEV_UWRK_UWRK8_B0_UDB06_ACTL EQU 0x40006496 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_ACTL +CYDEV_UWRK_UWRK8_B0_UDB07_ACTL EQU 0x40006497 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_ACTL +CYDEV_UWRK_UWRK8_B0_UDB08_ACTL EQU 0x40006498 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_ACTL +CYDEV_UWRK_UWRK8_B0_UDB09_ACTL EQU 0x40006499 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_ACTL +CYDEV_UWRK_UWRK8_B0_UDB10_ACTL EQU 0x4000649a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_ACTL +CYDEV_UWRK_UWRK8_B0_UDB11_ACTL EQU 0x4000649b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_ACTL +CYDEV_UWRK_UWRK8_B0_UDB12_ACTL EQU 0x4000649c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_ACTL +CYDEV_UWRK_UWRK8_B0_UDB13_ACTL EQU 0x4000649d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_ACTL +CYDEV_UWRK_UWRK8_B0_UDB14_ACTL EQU 0x4000649e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_ACTL +CYDEV_UWRK_UWRK8_B0_UDB15_ACTL EQU 0x4000649f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_MC +CYDEV_UWRK_UWRK8_B0_UDB00_MC EQU 0x400064a0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_MC +CYDEV_UWRK_UWRK8_B0_UDB01_MC EQU 0x400064a1 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_MC +CYDEV_UWRK_UWRK8_B0_UDB02_MC EQU 0x400064a2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_MC +CYDEV_UWRK_UWRK8_B0_UDB03_MC EQU 0x400064a3 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_MC +CYDEV_UWRK_UWRK8_B0_UDB04_MC EQU 0x400064a4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_MC +CYDEV_UWRK_UWRK8_B0_UDB05_MC EQU 0x400064a5 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_MC +CYDEV_UWRK_UWRK8_B0_UDB06_MC EQU 0x400064a6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_MC +CYDEV_UWRK_UWRK8_B0_UDB07_MC EQU 0x400064a7 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_MC +CYDEV_UWRK_UWRK8_B0_UDB08_MC EQU 0x400064a8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_MC +CYDEV_UWRK_UWRK8_B0_UDB09_MC EQU 0x400064a9 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_MC +CYDEV_UWRK_UWRK8_B0_UDB10_MC EQU 0x400064aa + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_MC +CYDEV_UWRK_UWRK8_B0_UDB11_MC EQU 0x400064ab + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_MC +CYDEV_UWRK_UWRK8_B0_UDB12_MC EQU 0x400064ac + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_MC +CYDEV_UWRK_UWRK8_B0_UDB13_MC EQU 0x400064ad + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_MC +CYDEV_UWRK_UWRK8_B0_UDB14_MC EQU 0x400064ae + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_MC +CYDEV_UWRK_UWRK8_B0_UDB15_MC EQU 0x400064af + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_BASE +CYDEV_UWRK_UWRK8_B1_BASE EQU 0x40006500 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_SIZE +CYDEV_UWRK_UWRK8_B1_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_A0 +CYDEV_UWRK_UWRK8_B1_UDB04_A0 EQU 0x40006504 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_A0 +CYDEV_UWRK_UWRK8_B1_UDB05_A0 EQU 0x40006505 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_A0 +CYDEV_UWRK_UWRK8_B1_UDB06_A0 EQU 0x40006506 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_A0 +CYDEV_UWRK_UWRK8_B1_UDB07_A0 EQU 0x40006507 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_A0 +CYDEV_UWRK_UWRK8_B1_UDB08_A0 EQU 0x40006508 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_A0 +CYDEV_UWRK_UWRK8_B1_UDB09_A0 EQU 0x40006509 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_A0 +CYDEV_UWRK_UWRK8_B1_UDB10_A0 EQU 0x4000650a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_A0 +CYDEV_UWRK_UWRK8_B1_UDB11_A0 EQU 0x4000650b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_A1 +CYDEV_UWRK_UWRK8_B1_UDB04_A1 EQU 0x40006514 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_A1 +CYDEV_UWRK_UWRK8_B1_UDB05_A1 EQU 0x40006515 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_A1 +CYDEV_UWRK_UWRK8_B1_UDB06_A1 EQU 0x40006516 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_A1 +CYDEV_UWRK_UWRK8_B1_UDB07_A1 EQU 0x40006517 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_A1 +CYDEV_UWRK_UWRK8_B1_UDB08_A1 EQU 0x40006518 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_A1 +CYDEV_UWRK_UWRK8_B1_UDB09_A1 EQU 0x40006519 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_A1 +CYDEV_UWRK_UWRK8_B1_UDB10_A1 EQU 0x4000651a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_A1 +CYDEV_UWRK_UWRK8_B1_UDB11_A1 EQU 0x4000651b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_D0 +CYDEV_UWRK_UWRK8_B1_UDB04_D0 EQU 0x40006524 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_D0 +CYDEV_UWRK_UWRK8_B1_UDB05_D0 EQU 0x40006525 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_D0 +CYDEV_UWRK_UWRK8_B1_UDB06_D0 EQU 0x40006526 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_D0 +CYDEV_UWRK_UWRK8_B1_UDB07_D0 EQU 0x40006527 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_D0 +CYDEV_UWRK_UWRK8_B1_UDB08_D0 EQU 0x40006528 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_D0 +CYDEV_UWRK_UWRK8_B1_UDB09_D0 EQU 0x40006529 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_D0 +CYDEV_UWRK_UWRK8_B1_UDB10_D0 EQU 0x4000652a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_D0 +CYDEV_UWRK_UWRK8_B1_UDB11_D0 EQU 0x4000652b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_D1 +CYDEV_UWRK_UWRK8_B1_UDB04_D1 EQU 0x40006534 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_D1 +CYDEV_UWRK_UWRK8_B1_UDB05_D1 EQU 0x40006535 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_D1 +CYDEV_UWRK_UWRK8_B1_UDB06_D1 EQU 0x40006536 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_D1 +CYDEV_UWRK_UWRK8_B1_UDB07_D1 EQU 0x40006537 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_D1 +CYDEV_UWRK_UWRK8_B1_UDB08_D1 EQU 0x40006538 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_D1 +CYDEV_UWRK_UWRK8_B1_UDB09_D1 EQU 0x40006539 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_D1 +CYDEV_UWRK_UWRK8_B1_UDB10_D1 EQU 0x4000653a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_D1 +CYDEV_UWRK_UWRK8_B1_UDB11_D1 EQU 0x4000653b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_F0 +CYDEV_UWRK_UWRK8_B1_UDB04_F0 EQU 0x40006544 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_F0 +CYDEV_UWRK_UWRK8_B1_UDB05_F0 EQU 0x40006545 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_F0 +CYDEV_UWRK_UWRK8_B1_UDB06_F0 EQU 0x40006546 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_F0 +CYDEV_UWRK_UWRK8_B1_UDB07_F0 EQU 0x40006547 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_F0 +CYDEV_UWRK_UWRK8_B1_UDB08_F0 EQU 0x40006548 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_F0 +CYDEV_UWRK_UWRK8_B1_UDB09_F0 EQU 0x40006549 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_F0 +CYDEV_UWRK_UWRK8_B1_UDB10_F0 EQU 0x4000654a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_F0 +CYDEV_UWRK_UWRK8_B1_UDB11_F0 EQU 0x4000654b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_F1 +CYDEV_UWRK_UWRK8_B1_UDB04_F1 EQU 0x40006554 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_F1 +CYDEV_UWRK_UWRK8_B1_UDB05_F1 EQU 0x40006555 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_F1 +CYDEV_UWRK_UWRK8_B1_UDB06_F1 EQU 0x40006556 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_F1 +CYDEV_UWRK_UWRK8_B1_UDB07_F1 EQU 0x40006557 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_F1 +CYDEV_UWRK_UWRK8_B1_UDB08_F1 EQU 0x40006558 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_F1 +CYDEV_UWRK_UWRK8_B1_UDB09_F1 EQU 0x40006559 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_F1 +CYDEV_UWRK_UWRK8_B1_UDB10_F1 EQU 0x4000655a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_F1 +CYDEV_UWRK_UWRK8_B1_UDB11_F1 EQU 0x4000655b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_ST +CYDEV_UWRK_UWRK8_B1_UDB04_ST EQU 0x40006564 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_ST +CYDEV_UWRK_UWRK8_B1_UDB05_ST EQU 0x40006565 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_ST +CYDEV_UWRK_UWRK8_B1_UDB06_ST EQU 0x40006566 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_ST +CYDEV_UWRK_UWRK8_B1_UDB07_ST EQU 0x40006567 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_ST +CYDEV_UWRK_UWRK8_B1_UDB08_ST EQU 0x40006568 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_ST +CYDEV_UWRK_UWRK8_B1_UDB09_ST EQU 0x40006569 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_ST +CYDEV_UWRK_UWRK8_B1_UDB10_ST EQU 0x4000656a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_ST +CYDEV_UWRK_UWRK8_B1_UDB11_ST EQU 0x4000656b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_CTL +CYDEV_UWRK_UWRK8_B1_UDB04_CTL EQU 0x40006574 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_CTL +CYDEV_UWRK_UWRK8_B1_UDB05_CTL EQU 0x40006575 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_CTL +CYDEV_UWRK_UWRK8_B1_UDB06_CTL EQU 0x40006576 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_CTL +CYDEV_UWRK_UWRK8_B1_UDB07_CTL EQU 0x40006577 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_CTL +CYDEV_UWRK_UWRK8_B1_UDB08_CTL EQU 0x40006578 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_CTL +CYDEV_UWRK_UWRK8_B1_UDB09_CTL EQU 0x40006579 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_CTL +CYDEV_UWRK_UWRK8_B1_UDB10_CTL EQU 0x4000657a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_CTL +CYDEV_UWRK_UWRK8_B1_UDB11_CTL EQU 0x4000657b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_MSK +CYDEV_UWRK_UWRK8_B1_UDB04_MSK EQU 0x40006584 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_MSK +CYDEV_UWRK_UWRK8_B1_UDB05_MSK EQU 0x40006585 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_MSK +CYDEV_UWRK_UWRK8_B1_UDB06_MSK EQU 0x40006586 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_MSK +CYDEV_UWRK_UWRK8_B1_UDB07_MSK EQU 0x40006587 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_MSK +CYDEV_UWRK_UWRK8_B1_UDB08_MSK EQU 0x40006588 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_MSK +CYDEV_UWRK_UWRK8_B1_UDB09_MSK EQU 0x40006589 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_MSK +CYDEV_UWRK_UWRK8_B1_UDB10_MSK EQU 0x4000658a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_MSK +CYDEV_UWRK_UWRK8_B1_UDB11_MSK EQU 0x4000658b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_ACTL +CYDEV_UWRK_UWRK8_B1_UDB04_ACTL EQU 0x40006594 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_ACTL +CYDEV_UWRK_UWRK8_B1_UDB05_ACTL EQU 0x40006595 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_ACTL +CYDEV_UWRK_UWRK8_B1_UDB06_ACTL EQU 0x40006596 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_ACTL +CYDEV_UWRK_UWRK8_B1_UDB07_ACTL EQU 0x40006597 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_ACTL +CYDEV_UWRK_UWRK8_B1_UDB08_ACTL EQU 0x40006598 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_ACTL +CYDEV_UWRK_UWRK8_B1_UDB09_ACTL EQU 0x40006599 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_ACTL +CYDEV_UWRK_UWRK8_B1_UDB10_ACTL EQU 0x4000659a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_ACTL +CYDEV_UWRK_UWRK8_B1_UDB11_ACTL EQU 0x4000659b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_MC +CYDEV_UWRK_UWRK8_B1_UDB04_MC EQU 0x400065a4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_MC +CYDEV_UWRK_UWRK8_B1_UDB05_MC EQU 0x400065a5 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_MC +CYDEV_UWRK_UWRK8_B1_UDB06_MC EQU 0x400065a6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_MC +CYDEV_UWRK_UWRK8_B1_UDB07_MC EQU 0x400065a7 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_MC +CYDEV_UWRK_UWRK8_B1_UDB08_MC EQU 0x400065a8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_MC +CYDEV_UWRK_UWRK8_B1_UDB09_MC EQU 0x400065a9 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_MC +CYDEV_UWRK_UWRK8_B1_UDB10_MC EQU 0x400065aa + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_MC +CYDEV_UWRK_UWRK8_B1_UDB11_MC EQU 0x400065ab + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_BASE +CYDEV_UWRK_UWRK16_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_SIZE +CYDEV_UWRK_UWRK16_SIZE EQU 0x00000760 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_BASE +CYDEV_UWRK_UWRK16_CAT_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_SIZE +CYDEV_UWRK_UWRK16_CAT_SIZE EQU 0x00000760 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_BASE +CYDEV_UWRK_UWRK16_CAT_B0_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_SIZE +CYDEV_UWRK_UWRK16_CAT_B0_SIZE EQU 0x00000160 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1 EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1 EQU 0x40006802 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1 EQU 0x40006804 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1 EQU 0x40006806 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1 EQU 0x40006808 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1 EQU 0x4000680a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1 EQU 0x4000680c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1 EQU 0x4000680e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1 EQU 0x40006810 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1 EQU 0x40006812 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1 EQU 0x40006814 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1 EQU 0x40006816 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1 EQU 0x40006818 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1 EQU 0x4000681a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1 EQU 0x4000681c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1 EQU 0x4000681e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1 EQU 0x40006840 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1 EQU 0x40006842 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1 EQU 0x40006844 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1 EQU 0x40006846 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1 EQU 0x40006848 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1 EQU 0x4000684a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1 EQU 0x4000684c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1 EQU 0x4000684e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1 EQU 0x40006850 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1 EQU 0x40006852 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1 EQU 0x40006854 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1 EQU 0x40006856 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1 EQU 0x40006858 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1 EQU 0x4000685a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1 EQU 0x4000685c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1 EQU 0x4000685e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1 EQU 0x40006880 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1 EQU 0x40006882 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1 EQU 0x40006884 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1 EQU 0x40006886 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1 EQU 0x40006888 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1 EQU 0x4000688a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1 EQU 0x4000688c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1 EQU 0x4000688e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1 EQU 0x40006890 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1 EQU 0x40006892 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1 EQU 0x40006894 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1 EQU 0x40006896 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1 EQU 0x40006898 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1 EQU 0x4000689a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1 EQU 0x4000689c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1 EQU 0x4000689e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL EQU 0x400068c0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL EQU 0x400068c2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL EQU 0x400068c4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL EQU 0x400068c6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL EQU 0x400068c8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL EQU 0x400068ca + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL EQU 0x400068cc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL EQU 0x400068ce + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL EQU 0x400068d0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL EQU 0x400068d2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL EQU 0x400068d4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL EQU 0x400068d6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL EQU 0x400068d8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL EQU 0x400068da + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL EQU 0x400068dc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL EQU 0x400068de + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL EQU 0x40006900 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL EQU 0x40006902 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL EQU 0x40006904 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL EQU 0x40006906 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL EQU 0x40006908 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL EQU 0x4000690a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL EQU 0x4000690c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL EQU 0x4000690e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL EQU 0x40006910 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL EQU 0x40006912 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL EQU 0x40006914 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL EQU 0x40006916 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL EQU 0x40006918 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL EQU 0x4000691a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL EQU 0x4000691c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL EQU 0x4000691e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00 EQU 0x40006940 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00 EQU 0x40006942 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00 EQU 0x40006944 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00 EQU 0x40006946 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00 EQU 0x40006948 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00 EQU 0x4000694a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00 EQU 0x4000694c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00 EQU 0x4000694e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00 EQU 0x40006950 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00 EQU 0x40006952 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00 EQU 0x40006954 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00 EQU 0x40006956 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00 EQU 0x40006958 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00 EQU 0x4000695a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00 EQU 0x4000695c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00 EQU 0x4000695e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_BASE +CYDEV_UWRK_UWRK16_CAT_B1_BASE EQU 0x40006a00 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_SIZE +CYDEV_UWRK_UWRK16_CAT_B1_SIZE EQU 0x00000160 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1 EQU 0x40006a08 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1 EQU 0x40006a0a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1 EQU 0x40006a0c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1 EQU 0x40006a0e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1 EQU 0x40006a10 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1 EQU 0x40006a12 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1 EQU 0x40006a14 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1 EQU 0x40006a16 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1 EQU 0x40006a48 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1 EQU 0x40006a4a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1 EQU 0x40006a4c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1 EQU 0x40006a4e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1 EQU 0x40006a50 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1 EQU 0x40006a52 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1 EQU 0x40006a54 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1 EQU 0x40006a56 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1 EQU 0x40006a88 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1 EQU 0x40006a8a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1 EQU 0x40006a8c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1 EQU 0x40006a8e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1 EQU 0x40006a90 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1 EQU 0x40006a92 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1 EQU 0x40006a94 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1 EQU 0x40006a96 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL EQU 0x40006ac8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL EQU 0x40006aca + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL EQU 0x40006acc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL EQU 0x40006ace + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL EQU 0x40006ad0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL EQU 0x40006ad2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL EQU 0x40006ad4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL EQU 0x40006ad6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL EQU 0x40006b08 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL EQU 0x40006b0a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL EQU 0x40006b0c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL EQU 0x40006b0e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL EQU 0x40006b10 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL EQU 0x40006b12 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL EQU 0x40006b14 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL EQU 0x40006b16 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00 EQU 0x40006b48 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00 EQU 0x40006b4a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00 EQU 0x40006b4c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00 EQU 0x40006b4e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00 EQU 0x40006b50 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00 EQU 0x40006b52 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00 EQU 0x40006b54 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00 EQU 0x40006b56 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_BASE +CYDEV_UWRK_UWRK16_DEF_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_SIZE +CYDEV_UWRK_UWRK16_DEF_SIZE EQU 0x0000075e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_BASE +CYDEV_UWRK_UWRK16_DEF_B0_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_SIZE +CYDEV_UWRK_UWRK16_DEF_B0_SIZE EQU 0x0000015e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0 EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0 EQU 0x40006802 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0 EQU 0x40006804 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0 EQU 0x40006806 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0 EQU 0x40006808 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0 EQU 0x4000680a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0 EQU 0x4000680c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0 EQU 0x4000680e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0 EQU 0x40006810 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0 EQU 0x40006812 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0 EQU 0x40006814 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0 EQU 0x40006816 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0 EQU 0x40006818 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0 EQU 0x4000681a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0 EQU 0x4000681c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1 EQU 0x40006820 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1 EQU 0x40006822 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1 EQU 0x40006824 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1 EQU 0x40006826 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1 EQU 0x40006828 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1 EQU 0x4000682a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1 EQU 0x4000682c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1 EQU 0x4000682e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1 EQU 0x40006830 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1 EQU 0x40006832 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1 EQU 0x40006834 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1 EQU 0x40006836 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1 EQU 0x40006838 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1 EQU 0x4000683a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1 EQU 0x4000683c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0 EQU 0x40006840 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0 EQU 0x40006842 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0 EQU 0x40006844 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0 EQU 0x40006846 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0 EQU 0x40006848 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0 EQU 0x4000684a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0 EQU 0x4000684c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0 EQU 0x4000684e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0 EQU 0x40006850 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0 EQU 0x40006852 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0 EQU 0x40006854 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0 EQU 0x40006856 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0 EQU 0x40006858 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0 EQU 0x4000685a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0 EQU 0x4000685c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1 EQU 0x40006860 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1 EQU 0x40006862 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1 EQU 0x40006864 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1 EQU 0x40006866 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1 EQU 0x40006868 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1 EQU 0x4000686a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1 EQU 0x4000686c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1 EQU 0x4000686e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1 EQU 0x40006870 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1 EQU 0x40006872 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1 EQU 0x40006874 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1 EQU 0x40006876 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1 EQU 0x40006878 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1 EQU 0x4000687a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1 EQU 0x4000687c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0 EQU 0x40006880 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0 EQU 0x40006882 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0 EQU 0x40006884 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0 EQU 0x40006886 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0 EQU 0x40006888 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0 EQU 0x4000688a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0 EQU 0x4000688c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0 EQU 0x4000688e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0 EQU 0x40006890 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0 EQU 0x40006892 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0 EQU 0x40006894 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0 EQU 0x40006896 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0 EQU 0x40006898 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0 EQU 0x4000689a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0 EQU 0x4000689c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1 EQU 0x400068a0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1 EQU 0x400068a2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1 EQU 0x400068a4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1 EQU 0x400068a6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1 EQU 0x400068a8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1 EQU 0x400068aa + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1 EQU 0x400068ac + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1 EQU 0x400068ae + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1 EQU 0x400068b0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1 EQU 0x400068b2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1 EQU 0x400068b4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1 EQU 0x400068b6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1 EQU 0x400068b8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1 EQU 0x400068ba + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1 EQU 0x400068bc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST EQU 0x400068c0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST EQU 0x400068c2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST EQU 0x400068c4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST EQU 0x400068c6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST EQU 0x400068c8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST EQU 0x400068ca + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST EQU 0x400068cc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST EQU 0x400068ce + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST EQU 0x400068d0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST EQU 0x400068d2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST EQU 0x400068d4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST EQU 0x400068d6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST EQU 0x400068d8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST EQU 0x400068da + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST EQU 0x400068dc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL EQU 0x400068e0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL EQU 0x400068e2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL EQU 0x400068e4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL EQU 0x400068e6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL EQU 0x400068e8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL EQU 0x400068ea + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL EQU 0x400068ec + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL EQU 0x400068ee + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL EQU 0x400068f0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL EQU 0x400068f2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL EQU 0x400068f4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL EQU 0x400068f6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL EQU 0x400068f8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL EQU 0x400068fa + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL EQU 0x400068fc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK EQU 0x40006900 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK EQU 0x40006902 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK EQU 0x40006904 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK EQU 0x40006906 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK EQU 0x40006908 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK EQU 0x4000690a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK EQU 0x4000690c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK EQU 0x4000690e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK EQU 0x40006910 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK EQU 0x40006912 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK EQU 0x40006914 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK EQU 0x40006916 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK EQU 0x40006918 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK EQU 0x4000691a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK EQU 0x4000691c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL EQU 0x40006920 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL EQU 0x40006922 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL EQU 0x40006924 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL EQU 0x40006926 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL EQU 0x40006928 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL EQU 0x4000692a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL EQU 0x4000692c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL EQU 0x4000692e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL EQU 0x40006930 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL EQU 0x40006932 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL EQU 0x40006934 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL EQU 0x40006936 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL EQU 0x40006938 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL EQU 0x4000693a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL EQU 0x4000693c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC EQU 0x40006940 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC EQU 0x40006942 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC EQU 0x40006944 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC EQU 0x40006946 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC EQU 0x40006948 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC EQU 0x4000694a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC EQU 0x4000694c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC EQU 0x4000694e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC EQU 0x40006950 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC EQU 0x40006952 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC EQU 0x40006954 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC EQU 0x40006956 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC EQU 0x40006958 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC EQU 0x4000695a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC EQU 0x4000695c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_BASE +CYDEV_UWRK_UWRK16_DEF_B1_BASE EQU 0x40006a00 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_SIZE +CYDEV_UWRK_UWRK16_DEF_B1_SIZE EQU 0x0000015e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0 EQU 0x40006a08 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0 EQU 0x40006a0a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0 EQU 0x40006a0c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0 EQU 0x40006a0e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0 EQU 0x40006a10 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0 EQU 0x40006a12 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0 EQU 0x40006a14 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0 EQU 0x40006a16 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1 EQU 0x40006a28 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1 EQU 0x40006a2a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1 EQU 0x40006a2c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1 EQU 0x40006a2e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1 EQU 0x40006a30 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1 EQU 0x40006a32 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1 EQU 0x40006a34 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1 EQU 0x40006a36 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0 EQU 0x40006a48 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0 EQU 0x40006a4a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0 EQU 0x40006a4c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0 EQU 0x40006a4e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0 EQU 0x40006a50 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0 EQU 0x40006a52 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0 EQU 0x40006a54 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0 EQU 0x40006a56 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1 EQU 0x40006a68 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1 EQU 0x40006a6a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1 EQU 0x40006a6c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1 EQU 0x40006a6e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1 EQU 0x40006a70 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1 EQU 0x40006a72 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1 EQU 0x40006a74 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1 EQU 0x40006a76 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0 EQU 0x40006a88 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0 EQU 0x40006a8a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0 EQU 0x40006a8c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0 EQU 0x40006a8e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0 EQU 0x40006a90 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0 EQU 0x40006a92 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0 EQU 0x40006a94 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0 EQU 0x40006a96 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1 EQU 0x40006aa8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1 EQU 0x40006aaa + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1 EQU 0x40006aac + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1 EQU 0x40006aae + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1 EQU 0x40006ab0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1 EQU 0x40006ab2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1 EQU 0x40006ab4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1 EQU 0x40006ab6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST EQU 0x40006ac8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST EQU 0x40006aca + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST EQU 0x40006acc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST EQU 0x40006ace + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST EQU 0x40006ad0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST EQU 0x40006ad2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST EQU 0x40006ad4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST EQU 0x40006ad6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL EQU 0x40006ae8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL EQU 0x40006aea + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL EQU 0x40006aec + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL EQU 0x40006aee + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL EQU 0x40006af0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL EQU 0x40006af2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL EQU 0x40006af4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL EQU 0x40006af6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK EQU 0x40006b08 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK EQU 0x40006b0a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK EQU 0x40006b0c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK EQU 0x40006b0e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK EQU 0x40006b10 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK EQU 0x40006b12 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK EQU 0x40006b14 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK EQU 0x40006b16 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL EQU 0x40006b28 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL EQU 0x40006b2a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL EQU 0x40006b2c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL EQU 0x40006b2e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL EQU 0x40006b30 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL EQU 0x40006b32 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL EQU 0x40006b34 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL EQU 0x40006b36 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC EQU 0x40006b48 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC EQU 0x40006b4a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC EQU 0x40006b4c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC EQU 0x40006b4e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC EQU 0x40006b50 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC EQU 0x40006b52 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC EQU 0x40006b54 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC EQU 0x40006b56 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_BASE +CYDEV_PHUB_BASE EQU 0x40007000 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_SIZE +CYDEV_PHUB_SIZE EQU 0x00000c00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFG +CYDEV_PHUB_CFG EQU 0x40007000 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_ERR +CYDEV_PHUB_ERR EQU 0x40007004 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_ERR_ADR +CYDEV_PHUB_ERR_ADR EQU 0x40007008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_BASE +CYDEV_PHUB_CH0_BASE EQU 0x40007010 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_SIZE +CYDEV_PHUB_CH0_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_BASIC_CFG +CYDEV_PHUB_CH0_BASIC_CFG EQU 0x40007010 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_ACTION +CYDEV_PHUB_CH0_ACTION EQU 0x40007014 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_BASIC_STATUS +CYDEV_PHUB_CH0_BASIC_STATUS EQU 0x40007018 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_BASE +CYDEV_PHUB_CH1_BASE EQU 0x40007020 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_SIZE +CYDEV_PHUB_CH1_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_BASIC_CFG +CYDEV_PHUB_CH1_BASIC_CFG EQU 0x40007020 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_ACTION +CYDEV_PHUB_CH1_ACTION EQU 0x40007024 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_BASIC_STATUS +CYDEV_PHUB_CH1_BASIC_STATUS EQU 0x40007028 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_BASE +CYDEV_PHUB_CH2_BASE EQU 0x40007030 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_SIZE +CYDEV_PHUB_CH2_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_BASIC_CFG +CYDEV_PHUB_CH2_BASIC_CFG EQU 0x40007030 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_ACTION +CYDEV_PHUB_CH2_ACTION EQU 0x40007034 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_BASIC_STATUS +CYDEV_PHUB_CH2_BASIC_STATUS EQU 0x40007038 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_BASE +CYDEV_PHUB_CH3_BASE EQU 0x40007040 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_SIZE +CYDEV_PHUB_CH3_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_BASIC_CFG +CYDEV_PHUB_CH3_BASIC_CFG EQU 0x40007040 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_ACTION +CYDEV_PHUB_CH3_ACTION EQU 0x40007044 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_BASIC_STATUS +CYDEV_PHUB_CH3_BASIC_STATUS EQU 0x40007048 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_BASE +CYDEV_PHUB_CH4_BASE EQU 0x40007050 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_SIZE +CYDEV_PHUB_CH4_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_BASIC_CFG +CYDEV_PHUB_CH4_BASIC_CFG EQU 0x40007050 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_ACTION +CYDEV_PHUB_CH4_ACTION EQU 0x40007054 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_BASIC_STATUS +CYDEV_PHUB_CH4_BASIC_STATUS EQU 0x40007058 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_BASE +CYDEV_PHUB_CH5_BASE EQU 0x40007060 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_SIZE +CYDEV_PHUB_CH5_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_BASIC_CFG +CYDEV_PHUB_CH5_BASIC_CFG EQU 0x40007060 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_ACTION +CYDEV_PHUB_CH5_ACTION EQU 0x40007064 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_BASIC_STATUS +CYDEV_PHUB_CH5_BASIC_STATUS EQU 0x40007068 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_BASE +CYDEV_PHUB_CH6_BASE EQU 0x40007070 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_SIZE +CYDEV_PHUB_CH6_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_BASIC_CFG +CYDEV_PHUB_CH6_BASIC_CFG EQU 0x40007070 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_ACTION +CYDEV_PHUB_CH6_ACTION EQU 0x40007074 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_BASIC_STATUS +CYDEV_PHUB_CH6_BASIC_STATUS EQU 0x40007078 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_BASE +CYDEV_PHUB_CH7_BASE EQU 0x40007080 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_SIZE +CYDEV_PHUB_CH7_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_BASIC_CFG +CYDEV_PHUB_CH7_BASIC_CFG EQU 0x40007080 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_ACTION +CYDEV_PHUB_CH7_ACTION EQU 0x40007084 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_BASIC_STATUS +CYDEV_PHUB_CH7_BASIC_STATUS EQU 0x40007088 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_BASE +CYDEV_PHUB_CH8_BASE EQU 0x40007090 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_SIZE +CYDEV_PHUB_CH8_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_BASIC_CFG +CYDEV_PHUB_CH8_BASIC_CFG EQU 0x40007090 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_ACTION +CYDEV_PHUB_CH8_ACTION EQU 0x40007094 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_BASIC_STATUS +CYDEV_PHUB_CH8_BASIC_STATUS EQU 0x40007098 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_BASE +CYDEV_PHUB_CH9_BASE EQU 0x400070a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_SIZE +CYDEV_PHUB_CH9_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_BASIC_CFG +CYDEV_PHUB_CH9_BASIC_CFG EQU 0x400070a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_ACTION +CYDEV_PHUB_CH9_ACTION EQU 0x400070a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_BASIC_STATUS +CYDEV_PHUB_CH9_BASIC_STATUS EQU 0x400070a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_BASE +CYDEV_PHUB_CH10_BASE EQU 0x400070b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_SIZE +CYDEV_PHUB_CH10_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_BASIC_CFG +CYDEV_PHUB_CH10_BASIC_CFG EQU 0x400070b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_ACTION +CYDEV_PHUB_CH10_ACTION EQU 0x400070b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_BASIC_STATUS +CYDEV_PHUB_CH10_BASIC_STATUS EQU 0x400070b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_BASE +CYDEV_PHUB_CH11_BASE EQU 0x400070c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_SIZE +CYDEV_PHUB_CH11_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_BASIC_CFG +CYDEV_PHUB_CH11_BASIC_CFG EQU 0x400070c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_ACTION +CYDEV_PHUB_CH11_ACTION EQU 0x400070c4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_BASIC_STATUS +CYDEV_PHUB_CH11_BASIC_STATUS EQU 0x400070c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_BASE +CYDEV_PHUB_CH12_BASE EQU 0x400070d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_SIZE +CYDEV_PHUB_CH12_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_BASIC_CFG +CYDEV_PHUB_CH12_BASIC_CFG EQU 0x400070d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_ACTION +CYDEV_PHUB_CH12_ACTION EQU 0x400070d4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_BASIC_STATUS +CYDEV_PHUB_CH12_BASIC_STATUS EQU 0x400070d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_BASE +CYDEV_PHUB_CH13_BASE EQU 0x400070e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_SIZE +CYDEV_PHUB_CH13_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_BASIC_CFG +CYDEV_PHUB_CH13_BASIC_CFG EQU 0x400070e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_ACTION +CYDEV_PHUB_CH13_ACTION EQU 0x400070e4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_BASIC_STATUS +CYDEV_PHUB_CH13_BASIC_STATUS EQU 0x400070e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_BASE +CYDEV_PHUB_CH14_BASE EQU 0x400070f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_SIZE +CYDEV_PHUB_CH14_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_BASIC_CFG +CYDEV_PHUB_CH14_BASIC_CFG EQU 0x400070f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_ACTION +CYDEV_PHUB_CH14_ACTION EQU 0x400070f4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_BASIC_STATUS +CYDEV_PHUB_CH14_BASIC_STATUS EQU 0x400070f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_BASE +CYDEV_PHUB_CH15_BASE EQU 0x40007100 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_SIZE +CYDEV_PHUB_CH15_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_BASIC_CFG +CYDEV_PHUB_CH15_BASIC_CFG EQU 0x40007100 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_ACTION +CYDEV_PHUB_CH15_ACTION EQU 0x40007104 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_BASIC_STATUS +CYDEV_PHUB_CH15_BASIC_STATUS EQU 0x40007108 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_BASE +CYDEV_PHUB_CH16_BASE EQU 0x40007110 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_SIZE +CYDEV_PHUB_CH16_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_BASIC_CFG +CYDEV_PHUB_CH16_BASIC_CFG EQU 0x40007110 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_ACTION +CYDEV_PHUB_CH16_ACTION EQU 0x40007114 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_BASIC_STATUS +CYDEV_PHUB_CH16_BASIC_STATUS EQU 0x40007118 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_BASE +CYDEV_PHUB_CH17_BASE EQU 0x40007120 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_SIZE +CYDEV_PHUB_CH17_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_BASIC_CFG +CYDEV_PHUB_CH17_BASIC_CFG EQU 0x40007120 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_ACTION +CYDEV_PHUB_CH17_ACTION EQU 0x40007124 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_BASIC_STATUS +CYDEV_PHUB_CH17_BASIC_STATUS EQU 0x40007128 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_BASE +CYDEV_PHUB_CH18_BASE EQU 0x40007130 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_SIZE +CYDEV_PHUB_CH18_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_BASIC_CFG +CYDEV_PHUB_CH18_BASIC_CFG EQU 0x40007130 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_ACTION +CYDEV_PHUB_CH18_ACTION EQU 0x40007134 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_BASIC_STATUS +CYDEV_PHUB_CH18_BASIC_STATUS EQU 0x40007138 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_BASE +CYDEV_PHUB_CH19_BASE EQU 0x40007140 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_SIZE +CYDEV_PHUB_CH19_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_BASIC_CFG +CYDEV_PHUB_CH19_BASIC_CFG EQU 0x40007140 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_ACTION +CYDEV_PHUB_CH19_ACTION EQU 0x40007144 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_BASIC_STATUS +CYDEV_PHUB_CH19_BASIC_STATUS EQU 0x40007148 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_BASE +CYDEV_PHUB_CH20_BASE EQU 0x40007150 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_SIZE +CYDEV_PHUB_CH20_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_BASIC_CFG +CYDEV_PHUB_CH20_BASIC_CFG EQU 0x40007150 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_ACTION +CYDEV_PHUB_CH20_ACTION EQU 0x40007154 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_BASIC_STATUS +CYDEV_PHUB_CH20_BASIC_STATUS EQU 0x40007158 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_BASE +CYDEV_PHUB_CH21_BASE EQU 0x40007160 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_SIZE +CYDEV_PHUB_CH21_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_BASIC_CFG +CYDEV_PHUB_CH21_BASIC_CFG EQU 0x40007160 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_ACTION +CYDEV_PHUB_CH21_ACTION EQU 0x40007164 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_BASIC_STATUS +CYDEV_PHUB_CH21_BASIC_STATUS EQU 0x40007168 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_BASE +CYDEV_PHUB_CH22_BASE EQU 0x40007170 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_SIZE +CYDEV_PHUB_CH22_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_BASIC_CFG +CYDEV_PHUB_CH22_BASIC_CFG EQU 0x40007170 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_ACTION +CYDEV_PHUB_CH22_ACTION EQU 0x40007174 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_BASIC_STATUS +CYDEV_PHUB_CH22_BASIC_STATUS EQU 0x40007178 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_BASE +CYDEV_PHUB_CH23_BASE EQU 0x40007180 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_SIZE +CYDEV_PHUB_CH23_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_BASIC_CFG +CYDEV_PHUB_CH23_BASIC_CFG EQU 0x40007180 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_ACTION +CYDEV_PHUB_CH23_ACTION EQU 0x40007184 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_BASIC_STATUS +CYDEV_PHUB_CH23_BASIC_STATUS EQU 0x40007188 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_BASE +CYDEV_PHUB_CFGMEM0_BASE EQU 0x40007600 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_SIZE +CYDEV_PHUB_CFGMEM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_CFG0 +CYDEV_PHUB_CFGMEM0_CFG0 EQU 0x40007600 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_CFG1 +CYDEV_PHUB_CFGMEM0_CFG1 EQU 0x40007604 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_BASE +CYDEV_PHUB_CFGMEM1_BASE EQU 0x40007608 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_SIZE +CYDEV_PHUB_CFGMEM1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_CFG0 +CYDEV_PHUB_CFGMEM1_CFG0 EQU 0x40007608 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_CFG1 +CYDEV_PHUB_CFGMEM1_CFG1 EQU 0x4000760c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_BASE +CYDEV_PHUB_CFGMEM2_BASE EQU 0x40007610 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_SIZE +CYDEV_PHUB_CFGMEM2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_CFG0 +CYDEV_PHUB_CFGMEM2_CFG0 EQU 0x40007610 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_CFG1 +CYDEV_PHUB_CFGMEM2_CFG1 EQU 0x40007614 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_BASE +CYDEV_PHUB_CFGMEM3_BASE EQU 0x40007618 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_SIZE +CYDEV_PHUB_CFGMEM3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_CFG0 +CYDEV_PHUB_CFGMEM3_CFG0 EQU 0x40007618 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_CFG1 +CYDEV_PHUB_CFGMEM3_CFG1 EQU 0x4000761c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_BASE +CYDEV_PHUB_CFGMEM4_BASE EQU 0x40007620 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_SIZE +CYDEV_PHUB_CFGMEM4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_CFG0 +CYDEV_PHUB_CFGMEM4_CFG0 EQU 0x40007620 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_CFG1 +CYDEV_PHUB_CFGMEM4_CFG1 EQU 0x40007624 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_BASE +CYDEV_PHUB_CFGMEM5_BASE EQU 0x40007628 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_SIZE +CYDEV_PHUB_CFGMEM5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_CFG0 +CYDEV_PHUB_CFGMEM5_CFG0 EQU 0x40007628 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_CFG1 +CYDEV_PHUB_CFGMEM5_CFG1 EQU 0x4000762c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_BASE +CYDEV_PHUB_CFGMEM6_BASE EQU 0x40007630 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_SIZE +CYDEV_PHUB_CFGMEM6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_CFG0 +CYDEV_PHUB_CFGMEM6_CFG0 EQU 0x40007630 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_CFG1 +CYDEV_PHUB_CFGMEM6_CFG1 EQU 0x40007634 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_BASE +CYDEV_PHUB_CFGMEM7_BASE EQU 0x40007638 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_SIZE +CYDEV_PHUB_CFGMEM7_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_CFG0 +CYDEV_PHUB_CFGMEM7_CFG0 EQU 0x40007638 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_CFG1 +CYDEV_PHUB_CFGMEM7_CFG1 EQU 0x4000763c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_BASE +CYDEV_PHUB_CFGMEM8_BASE EQU 0x40007640 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_SIZE +CYDEV_PHUB_CFGMEM8_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_CFG0 +CYDEV_PHUB_CFGMEM8_CFG0 EQU 0x40007640 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_CFG1 +CYDEV_PHUB_CFGMEM8_CFG1 EQU 0x40007644 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_BASE +CYDEV_PHUB_CFGMEM9_BASE EQU 0x40007648 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_SIZE +CYDEV_PHUB_CFGMEM9_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_CFG0 +CYDEV_PHUB_CFGMEM9_CFG0 EQU 0x40007648 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_CFG1 +CYDEV_PHUB_CFGMEM9_CFG1 EQU 0x4000764c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_BASE +CYDEV_PHUB_CFGMEM10_BASE EQU 0x40007650 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_SIZE +CYDEV_PHUB_CFGMEM10_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_CFG0 +CYDEV_PHUB_CFGMEM10_CFG0 EQU 0x40007650 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_CFG1 +CYDEV_PHUB_CFGMEM10_CFG1 EQU 0x40007654 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_BASE +CYDEV_PHUB_CFGMEM11_BASE EQU 0x40007658 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_SIZE +CYDEV_PHUB_CFGMEM11_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_CFG0 +CYDEV_PHUB_CFGMEM11_CFG0 EQU 0x40007658 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_CFG1 +CYDEV_PHUB_CFGMEM11_CFG1 EQU 0x4000765c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_BASE +CYDEV_PHUB_CFGMEM12_BASE EQU 0x40007660 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_SIZE +CYDEV_PHUB_CFGMEM12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_CFG0 +CYDEV_PHUB_CFGMEM12_CFG0 EQU 0x40007660 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_CFG1 +CYDEV_PHUB_CFGMEM12_CFG1 EQU 0x40007664 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_BASE +CYDEV_PHUB_CFGMEM13_BASE EQU 0x40007668 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_SIZE +CYDEV_PHUB_CFGMEM13_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_CFG0 +CYDEV_PHUB_CFGMEM13_CFG0 EQU 0x40007668 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_CFG1 +CYDEV_PHUB_CFGMEM13_CFG1 EQU 0x4000766c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_BASE +CYDEV_PHUB_CFGMEM14_BASE EQU 0x40007670 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_SIZE +CYDEV_PHUB_CFGMEM14_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_CFG0 +CYDEV_PHUB_CFGMEM14_CFG0 EQU 0x40007670 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_CFG1 +CYDEV_PHUB_CFGMEM14_CFG1 EQU 0x40007674 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_BASE +CYDEV_PHUB_CFGMEM15_BASE EQU 0x40007678 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_SIZE +CYDEV_PHUB_CFGMEM15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_CFG0 +CYDEV_PHUB_CFGMEM15_CFG0 EQU 0x40007678 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_CFG1 +CYDEV_PHUB_CFGMEM15_CFG1 EQU 0x4000767c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_BASE +CYDEV_PHUB_CFGMEM16_BASE EQU 0x40007680 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_SIZE +CYDEV_PHUB_CFGMEM16_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_CFG0 +CYDEV_PHUB_CFGMEM16_CFG0 EQU 0x40007680 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_CFG1 +CYDEV_PHUB_CFGMEM16_CFG1 EQU 0x40007684 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_BASE +CYDEV_PHUB_CFGMEM17_BASE EQU 0x40007688 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_SIZE +CYDEV_PHUB_CFGMEM17_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_CFG0 +CYDEV_PHUB_CFGMEM17_CFG0 EQU 0x40007688 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_CFG1 +CYDEV_PHUB_CFGMEM17_CFG1 EQU 0x4000768c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_BASE +CYDEV_PHUB_CFGMEM18_BASE EQU 0x40007690 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_SIZE +CYDEV_PHUB_CFGMEM18_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_CFG0 +CYDEV_PHUB_CFGMEM18_CFG0 EQU 0x40007690 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_CFG1 +CYDEV_PHUB_CFGMEM18_CFG1 EQU 0x40007694 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_BASE +CYDEV_PHUB_CFGMEM19_BASE EQU 0x40007698 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_SIZE +CYDEV_PHUB_CFGMEM19_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_CFG0 +CYDEV_PHUB_CFGMEM19_CFG0 EQU 0x40007698 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_CFG1 +CYDEV_PHUB_CFGMEM19_CFG1 EQU 0x4000769c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_BASE +CYDEV_PHUB_CFGMEM20_BASE EQU 0x400076a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_SIZE +CYDEV_PHUB_CFGMEM20_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_CFG0 +CYDEV_PHUB_CFGMEM20_CFG0 EQU 0x400076a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_CFG1 +CYDEV_PHUB_CFGMEM20_CFG1 EQU 0x400076a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_BASE +CYDEV_PHUB_CFGMEM21_BASE EQU 0x400076a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_SIZE +CYDEV_PHUB_CFGMEM21_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_CFG0 +CYDEV_PHUB_CFGMEM21_CFG0 EQU 0x400076a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_CFG1 +CYDEV_PHUB_CFGMEM21_CFG1 EQU 0x400076ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_BASE +CYDEV_PHUB_CFGMEM22_BASE EQU 0x400076b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_SIZE +CYDEV_PHUB_CFGMEM22_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_CFG0 +CYDEV_PHUB_CFGMEM22_CFG0 EQU 0x400076b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_CFG1 +CYDEV_PHUB_CFGMEM22_CFG1 EQU 0x400076b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_BASE +CYDEV_PHUB_CFGMEM23_BASE EQU 0x400076b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_SIZE +CYDEV_PHUB_CFGMEM23_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_CFG0 +CYDEV_PHUB_CFGMEM23_CFG0 EQU 0x400076b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_CFG1 +CYDEV_PHUB_CFGMEM23_CFG1 EQU 0x400076bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_BASE +CYDEV_PHUB_TDMEM0_BASE EQU 0x40007800 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_SIZE +CYDEV_PHUB_TDMEM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_ORIG_TD0 +CYDEV_PHUB_TDMEM0_ORIG_TD0 EQU 0x40007800 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_ORIG_TD1 +CYDEV_PHUB_TDMEM0_ORIG_TD1 EQU 0x40007804 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_BASE +CYDEV_PHUB_TDMEM1_BASE EQU 0x40007808 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_SIZE +CYDEV_PHUB_TDMEM1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_ORIG_TD0 +CYDEV_PHUB_TDMEM1_ORIG_TD0 EQU 0x40007808 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_ORIG_TD1 +CYDEV_PHUB_TDMEM1_ORIG_TD1 EQU 0x4000780c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_BASE +CYDEV_PHUB_TDMEM2_BASE EQU 0x40007810 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_SIZE +CYDEV_PHUB_TDMEM2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_ORIG_TD0 +CYDEV_PHUB_TDMEM2_ORIG_TD0 EQU 0x40007810 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_ORIG_TD1 +CYDEV_PHUB_TDMEM2_ORIG_TD1 EQU 0x40007814 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_BASE +CYDEV_PHUB_TDMEM3_BASE EQU 0x40007818 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_SIZE +CYDEV_PHUB_TDMEM3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_ORIG_TD0 +CYDEV_PHUB_TDMEM3_ORIG_TD0 EQU 0x40007818 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_ORIG_TD1 +CYDEV_PHUB_TDMEM3_ORIG_TD1 EQU 0x4000781c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_BASE +CYDEV_PHUB_TDMEM4_BASE EQU 0x40007820 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_SIZE +CYDEV_PHUB_TDMEM4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_ORIG_TD0 +CYDEV_PHUB_TDMEM4_ORIG_TD0 EQU 0x40007820 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_ORIG_TD1 +CYDEV_PHUB_TDMEM4_ORIG_TD1 EQU 0x40007824 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_BASE +CYDEV_PHUB_TDMEM5_BASE EQU 0x40007828 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_SIZE +CYDEV_PHUB_TDMEM5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_ORIG_TD0 +CYDEV_PHUB_TDMEM5_ORIG_TD0 EQU 0x40007828 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_ORIG_TD1 +CYDEV_PHUB_TDMEM5_ORIG_TD1 EQU 0x4000782c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_BASE +CYDEV_PHUB_TDMEM6_BASE EQU 0x40007830 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_SIZE +CYDEV_PHUB_TDMEM6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_ORIG_TD0 +CYDEV_PHUB_TDMEM6_ORIG_TD0 EQU 0x40007830 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_ORIG_TD1 +CYDEV_PHUB_TDMEM6_ORIG_TD1 EQU 0x40007834 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_BASE +CYDEV_PHUB_TDMEM7_BASE EQU 0x40007838 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_SIZE +CYDEV_PHUB_TDMEM7_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_ORIG_TD0 +CYDEV_PHUB_TDMEM7_ORIG_TD0 EQU 0x40007838 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_ORIG_TD1 +CYDEV_PHUB_TDMEM7_ORIG_TD1 EQU 0x4000783c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_BASE +CYDEV_PHUB_TDMEM8_BASE EQU 0x40007840 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_SIZE +CYDEV_PHUB_TDMEM8_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_ORIG_TD0 +CYDEV_PHUB_TDMEM8_ORIG_TD0 EQU 0x40007840 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_ORIG_TD1 +CYDEV_PHUB_TDMEM8_ORIG_TD1 EQU 0x40007844 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_BASE +CYDEV_PHUB_TDMEM9_BASE EQU 0x40007848 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_SIZE +CYDEV_PHUB_TDMEM9_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_ORIG_TD0 +CYDEV_PHUB_TDMEM9_ORIG_TD0 EQU 0x40007848 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_ORIG_TD1 +CYDEV_PHUB_TDMEM9_ORIG_TD1 EQU 0x4000784c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_BASE +CYDEV_PHUB_TDMEM10_BASE EQU 0x40007850 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_SIZE +CYDEV_PHUB_TDMEM10_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_ORIG_TD0 +CYDEV_PHUB_TDMEM10_ORIG_TD0 EQU 0x40007850 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_ORIG_TD1 +CYDEV_PHUB_TDMEM10_ORIG_TD1 EQU 0x40007854 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_BASE +CYDEV_PHUB_TDMEM11_BASE EQU 0x40007858 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_SIZE +CYDEV_PHUB_TDMEM11_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_ORIG_TD0 +CYDEV_PHUB_TDMEM11_ORIG_TD0 EQU 0x40007858 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_ORIG_TD1 +CYDEV_PHUB_TDMEM11_ORIG_TD1 EQU 0x4000785c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_BASE +CYDEV_PHUB_TDMEM12_BASE EQU 0x40007860 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_SIZE +CYDEV_PHUB_TDMEM12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_ORIG_TD0 +CYDEV_PHUB_TDMEM12_ORIG_TD0 EQU 0x40007860 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_ORIG_TD1 +CYDEV_PHUB_TDMEM12_ORIG_TD1 EQU 0x40007864 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_BASE +CYDEV_PHUB_TDMEM13_BASE EQU 0x40007868 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_SIZE +CYDEV_PHUB_TDMEM13_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_ORIG_TD0 +CYDEV_PHUB_TDMEM13_ORIG_TD0 EQU 0x40007868 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_ORIG_TD1 +CYDEV_PHUB_TDMEM13_ORIG_TD1 EQU 0x4000786c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_BASE +CYDEV_PHUB_TDMEM14_BASE EQU 0x40007870 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_SIZE +CYDEV_PHUB_TDMEM14_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_ORIG_TD0 +CYDEV_PHUB_TDMEM14_ORIG_TD0 EQU 0x40007870 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_ORIG_TD1 +CYDEV_PHUB_TDMEM14_ORIG_TD1 EQU 0x40007874 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_BASE +CYDEV_PHUB_TDMEM15_BASE EQU 0x40007878 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_SIZE +CYDEV_PHUB_TDMEM15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_ORIG_TD0 +CYDEV_PHUB_TDMEM15_ORIG_TD0 EQU 0x40007878 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_ORIG_TD1 +CYDEV_PHUB_TDMEM15_ORIG_TD1 EQU 0x4000787c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_BASE +CYDEV_PHUB_TDMEM16_BASE EQU 0x40007880 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_SIZE +CYDEV_PHUB_TDMEM16_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_ORIG_TD0 +CYDEV_PHUB_TDMEM16_ORIG_TD0 EQU 0x40007880 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_ORIG_TD1 +CYDEV_PHUB_TDMEM16_ORIG_TD1 EQU 0x40007884 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_BASE +CYDEV_PHUB_TDMEM17_BASE EQU 0x40007888 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_SIZE +CYDEV_PHUB_TDMEM17_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_ORIG_TD0 +CYDEV_PHUB_TDMEM17_ORIG_TD0 EQU 0x40007888 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_ORIG_TD1 +CYDEV_PHUB_TDMEM17_ORIG_TD1 EQU 0x4000788c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_BASE +CYDEV_PHUB_TDMEM18_BASE EQU 0x40007890 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_SIZE +CYDEV_PHUB_TDMEM18_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_ORIG_TD0 +CYDEV_PHUB_TDMEM18_ORIG_TD0 EQU 0x40007890 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_ORIG_TD1 +CYDEV_PHUB_TDMEM18_ORIG_TD1 EQU 0x40007894 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_BASE +CYDEV_PHUB_TDMEM19_BASE EQU 0x40007898 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_SIZE +CYDEV_PHUB_TDMEM19_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_ORIG_TD0 +CYDEV_PHUB_TDMEM19_ORIG_TD0 EQU 0x40007898 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_ORIG_TD1 +CYDEV_PHUB_TDMEM19_ORIG_TD1 EQU 0x4000789c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_BASE +CYDEV_PHUB_TDMEM20_BASE EQU 0x400078a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_SIZE +CYDEV_PHUB_TDMEM20_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_ORIG_TD0 +CYDEV_PHUB_TDMEM20_ORIG_TD0 EQU 0x400078a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_ORIG_TD1 +CYDEV_PHUB_TDMEM20_ORIG_TD1 EQU 0x400078a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_BASE +CYDEV_PHUB_TDMEM21_BASE EQU 0x400078a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_SIZE +CYDEV_PHUB_TDMEM21_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_ORIG_TD0 +CYDEV_PHUB_TDMEM21_ORIG_TD0 EQU 0x400078a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_ORIG_TD1 +CYDEV_PHUB_TDMEM21_ORIG_TD1 EQU 0x400078ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_BASE +CYDEV_PHUB_TDMEM22_BASE EQU 0x400078b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_SIZE +CYDEV_PHUB_TDMEM22_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_ORIG_TD0 +CYDEV_PHUB_TDMEM22_ORIG_TD0 EQU 0x400078b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_ORIG_TD1 +CYDEV_PHUB_TDMEM22_ORIG_TD1 EQU 0x400078b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_BASE +CYDEV_PHUB_TDMEM23_BASE EQU 0x400078b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_SIZE +CYDEV_PHUB_TDMEM23_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_ORIG_TD0 +CYDEV_PHUB_TDMEM23_ORIG_TD0 EQU 0x400078b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_ORIG_TD1 +CYDEV_PHUB_TDMEM23_ORIG_TD1 EQU 0x400078bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_BASE +CYDEV_PHUB_TDMEM24_BASE EQU 0x400078c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_SIZE +CYDEV_PHUB_TDMEM24_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_ORIG_TD0 +CYDEV_PHUB_TDMEM24_ORIG_TD0 EQU 0x400078c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_ORIG_TD1 +CYDEV_PHUB_TDMEM24_ORIG_TD1 EQU 0x400078c4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_BASE +CYDEV_PHUB_TDMEM25_BASE EQU 0x400078c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_SIZE +CYDEV_PHUB_TDMEM25_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_ORIG_TD0 +CYDEV_PHUB_TDMEM25_ORIG_TD0 EQU 0x400078c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_ORIG_TD1 +CYDEV_PHUB_TDMEM25_ORIG_TD1 EQU 0x400078cc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_BASE +CYDEV_PHUB_TDMEM26_BASE EQU 0x400078d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_SIZE +CYDEV_PHUB_TDMEM26_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_ORIG_TD0 +CYDEV_PHUB_TDMEM26_ORIG_TD0 EQU 0x400078d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_ORIG_TD1 +CYDEV_PHUB_TDMEM26_ORIG_TD1 EQU 0x400078d4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_BASE +CYDEV_PHUB_TDMEM27_BASE EQU 0x400078d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_SIZE +CYDEV_PHUB_TDMEM27_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_ORIG_TD0 +CYDEV_PHUB_TDMEM27_ORIG_TD0 EQU 0x400078d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_ORIG_TD1 +CYDEV_PHUB_TDMEM27_ORIG_TD1 EQU 0x400078dc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_BASE +CYDEV_PHUB_TDMEM28_BASE EQU 0x400078e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_SIZE +CYDEV_PHUB_TDMEM28_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_ORIG_TD0 +CYDEV_PHUB_TDMEM28_ORIG_TD0 EQU 0x400078e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_ORIG_TD1 +CYDEV_PHUB_TDMEM28_ORIG_TD1 EQU 0x400078e4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_BASE +CYDEV_PHUB_TDMEM29_BASE EQU 0x400078e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_SIZE +CYDEV_PHUB_TDMEM29_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_ORIG_TD0 +CYDEV_PHUB_TDMEM29_ORIG_TD0 EQU 0x400078e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_ORIG_TD1 +CYDEV_PHUB_TDMEM29_ORIG_TD1 EQU 0x400078ec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_BASE +CYDEV_PHUB_TDMEM30_BASE EQU 0x400078f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_SIZE +CYDEV_PHUB_TDMEM30_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_ORIG_TD0 +CYDEV_PHUB_TDMEM30_ORIG_TD0 EQU 0x400078f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_ORIG_TD1 +CYDEV_PHUB_TDMEM30_ORIG_TD1 EQU 0x400078f4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_BASE +CYDEV_PHUB_TDMEM31_BASE EQU 0x400078f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_SIZE +CYDEV_PHUB_TDMEM31_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_ORIG_TD0 +CYDEV_PHUB_TDMEM31_ORIG_TD0 EQU 0x400078f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_ORIG_TD1 +CYDEV_PHUB_TDMEM31_ORIG_TD1 EQU 0x400078fc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_BASE +CYDEV_PHUB_TDMEM32_BASE EQU 0x40007900 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_SIZE +CYDEV_PHUB_TDMEM32_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_ORIG_TD0 +CYDEV_PHUB_TDMEM32_ORIG_TD0 EQU 0x40007900 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_ORIG_TD1 +CYDEV_PHUB_TDMEM32_ORIG_TD1 EQU 0x40007904 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_BASE +CYDEV_PHUB_TDMEM33_BASE EQU 0x40007908 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_SIZE +CYDEV_PHUB_TDMEM33_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_ORIG_TD0 +CYDEV_PHUB_TDMEM33_ORIG_TD0 EQU 0x40007908 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_ORIG_TD1 +CYDEV_PHUB_TDMEM33_ORIG_TD1 EQU 0x4000790c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_BASE +CYDEV_PHUB_TDMEM34_BASE EQU 0x40007910 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_SIZE +CYDEV_PHUB_TDMEM34_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_ORIG_TD0 +CYDEV_PHUB_TDMEM34_ORIG_TD0 EQU 0x40007910 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_ORIG_TD1 +CYDEV_PHUB_TDMEM34_ORIG_TD1 EQU 0x40007914 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_BASE +CYDEV_PHUB_TDMEM35_BASE EQU 0x40007918 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_SIZE +CYDEV_PHUB_TDMEM35_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_ORIG_TD0 +CYDEV_PHUB_TDMEM35_ORIG_TD0 EQU 0x40007918 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_ORIG_TD1 +CYDEV_PHUB_TDMEM35_ORIG_TD1 EQU 0x4000791c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_BASE +CYDEV_PHUB_TDMEM36_BASE EQU 0x40007920 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_SIZE +CYDEV_PHUB_TDMEM36_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_ORIG_TD0 +CYDEV_PHUB_TDMEM36_ORIG_TD0 EQU 0x40007920 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_ORIG_TD1 +CYDEV_PHUB_TDMEM36_ORIG_TD1 EQU 0x40007924 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_BASE +CYDEV_PHUB_TDMEM37_BASE EQU 0x40007928 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_SIZE +CYDEV_PHUB_TDMEM37_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_ORIG_TD0 +CYDEV_PHUB_TDMEM37_ORIG_TD0 EQU 0x40007928 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_ORIG_TD1 +CYDEV_PHUB_TDMEM37_ORIG_TD1 EQU 0x4000792c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_BASE +CYDEV_PHUB_TDMEM38_BASE EQU 0x40007930 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_SIZE +CYDEV_PHUB_TDMEM38_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_ORIG_TD0 +CYDEV_PHUB_TDMEM38_ORIG_TD0 EQU 0x40007930 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_ORIG_TD1 +CYDEV_PHUB_TDMEM38_ORIG_TD1 EQU 0x40007934 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_BASE +CYDEV_PHUB_TDMEM39_BASE EQU 0x40007938 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_SIZE +CYDEV_PHUB_TDMEM39_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_ORIG_TD0 +CYDEV_PHUB_TDMEM39_ORIG_TD0 EQU 0x40007938 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_ORIG_TD1 +CYDEV_PHUB_TDMEM39_ORIG_TD1 EQU 0x4000793c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_BASE +CYDEV_PHUB_TDMEM40_BASE EQU 0x40007940 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_SIZE +CYDEV_PHUB_TDMEM40_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_ORIG_TD0 +CYDEV_PHUB_TDMEM40_ORIG_TD0 EQU 0x40007940 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_ORIG_TD1 +CYDEV_PHUB_TDMEM40_ORIG_TD1 EQU 0x40007944 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_BASE +CYDEV_PHUB_TDMEM41_BASE EQU 0x40007948 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_SIZE +CYDEV_PHUB_TDMEM41_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_ORIG_TD0 +CYDEV_PHUB_TDMEM41_ORIG_TD0 EQU 0x40007948 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_ORIG_TD1 +CYDEV_PHUB_TDMEM41_ORIG_TD1 EQU 0x4000794c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_BASE +CYDEV_PHUB_TDMEM42_BASE EQU 0x40007950 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_SIZE +CYDEV_PHUB_TDMEM42_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_ORIG_TD0 +CYDEV_PHUB_TDMEM42_ORIG_TD0 EQU 0x40007950 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_ORIG_TD1 +CYDEV_PHUB_TDMEM42_ORIG_TD1 EQU 0x40007954 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_BASE +CYDEV_PHUB_TDMEM43_BASE EQU 0x40007958 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_SIZE +CYDEV_PHUB_TDMEM43_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_ORIG_TD0 +CYDEV_PHUB_TDMEM43_ORIG_TD0 EQU 0x40007958 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_ORIG_TD1 +CYDEV_PHUB_TDMEM43_ORIG_TD1 EQU 0x4000795c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_BASE +CYDEV_PHUB_TDMEM44_BASE EQU 0x40007960 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_SIZE +CYDEV_PHUB_TDMEM44_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_ORIG_TD0 +CYDEV_PHUB_TDMEM44_ORIG_TD0 EQU 0x40007960 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_ORIG_TD1 +CYDEV_PHUB_TDMEM44_ORIG_TD1 EQU 0x40007964 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_BASE +CYDEV_PHUB_TDMEM45_BASE EQU 0x40007968 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_SIZE +CYDEV_PHUB_TDMEM45_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_ORIG_TD0 +CYDEV_PHUB_TDMEM45_ORIG_TD0 EQU 0x40007968 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_ORIG_TD1 +CYDEV_PHUB_TDMEM45_ORIG_TD1 EQU 0x4000796c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_BASE +CYDEV_PHUB_TDMEM46_BASE EQU 0x40007970 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_SIZE +CYDEV_PHUB_TDMEM46_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_ORIG_TD0 +CYDEV_PHUB_TDMEM46_ORIG_TD0 EQU 0x40007970 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_ORIG_TD1 +CYDEV_PHUB_TDMEM46_ORIG_TD1 EQU 0x40007974 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_BASE +CYDEV_PHUB_TDMEM47_BASE EQU 0x40007978 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_SIZE +CYDEV_PHUB_TDMEM47_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_ORIG_TD0 +CYDEV_PHUB_TDMEM47_ORIG_TD0 EQU 0x40007978 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_ORIG_TD1 +CYDEV_PHUB_TDMEM47_ORIG_TD1 EQU 0x4000797c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_BASE +CYDEV_PHUB_TDMEM48_BASE EQU 0x40007980 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_SIZE +CYDEV_PHUB_TDMEM48_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_ORIG_TD0 +CYDEV_PHUB_TDMEM48_ORIG_TD0 EQU 0x40007980 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_ORIG_TD1 +CYDEV_PHUB_TDMEM48_ORIG_TD1 EQU 0x40007984 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_BASE +CYDEV_PHUB_TDMEM49_BASE EQU 0x40007988 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_SIZE +CYDEV_PHUB_TDMEM49_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_ORIG_TD0 +CYDEV_PHUB_TDMEM49_ORIG_TD0 EQU 0x40007988 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_ORIG_TD1 +CYDEV_PHUB_TDMEM49_ORIG_TD1 EQU 0x4000798c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_BASE +CYDEV_PHUB_TDMEM50_BASE EQU 0x40007990 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_SIZE +CYDEV_PHUB_TDMEM50_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_ORIG_TD0 +CYDEV_PHUB_TDMEM50_ORIG_TD0 EQU 0x40007990 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_ORIG_TD1 +CYDEV_PHUB_TDMEM50_ORIG_TD1 EQU 0x40007994 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_BASE +CYDEV_PHUB_TDMEM51_BASE EQU 0x40007998 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_SIZE +CYDEV_PHUB_TDMEM51_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_ORIG_TD0 +CYDEV_PHUB_TDMEM51_ORIG_TD0 EQU 0x40007998 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_ORIG_TD1 +CYDEV_PHUB_TDMEM51_ORIG_TD1 EQU 0x4000799c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_BASE +CYDEV_PHUB_TDMEM52_BASE EQU 0x400079a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_SIZE +CYDEV_PHUB_TDMEM52_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_ORIG_TD0 +CYDEV_PHUB_TDMEM52_ORIG_TD0 EQU 0x400079a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_ORIG_TD1 +CYDEV_PHUB_TDMEM52_ORIG_TD1 EQU 0x400079a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_BASE +CYDEV_PHUB_TDMEM53_BASE EQU 0x400079a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_SIZE +CYDEV_PHUB_TDMEM53_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_ORIG_TD0 +CYDEV_PHUB_TDMEM53_ORIG_TD0 EQU 0x400079a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_ORIG_TD1 +CYDEV_PHUB_TDMEM53_ORIG_TD1 EQU 0x400079ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_BASE +CYDEV_PHUB_TDMEM54_BASE EQU 0x400079b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_SIZE +CYDEV_PHUB_TDMEM54_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_ORIG_TD0 +CYDEV_PHUB_TDMEM54_ORIG_TD0 EQU 0x400079b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_ORIG_TD1 +CYDEV_PHUB_TDMEM54_ORIG_TD1 EQU 0x400079b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_BASE +CYDEV_PHUB_TDMEM55_BASE EQU 0x400079b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_SIZE +CYDEV_PHUB_TDMEM55_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_ORIG_TD0 +CYDEV_PHUB_TDMEM55_ORIG_TD0 EQU 0x400079b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_ORIG_TD1 +CYDEV_PHUB_TDMEM55_ORIG_TD1 EQU 0x400079bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_BASE +CYDEV_PHUB_TDMEM56_BASE EQU 0x400079c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_SIZE +CYDEV_PHUB_TDMEM56_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_ORIG_TD0 +CYDEV_PHUB_TDMEM56_ORIG_TD0 EQU 0x400079c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_ORIG_TD1 +CYDEV_PHUB_TDMEM56_ORIG_TD1 EQU 0x400079c4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_BASE +CYDEV_PHUB_TDMEM57_BASE EQU 0x400079c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_SIZE +CYDEV_PHUB_TDMEM57_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_ORIG_TD0 +CYDEV_PHUB_TDMEM57_ORIG_TD0 EQU 0x400079c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_ORIG_TD1 +CYDEV_PHUB_TDMEM57_ORIG_TD1 EQU 0x400079cc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_BASE +CYDEV_PHUB_TDMEM58_BASE EQU 0x400079d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_SIZE +CYDEV_PHUB_TDMEM58_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_ORIG_TD0 +CYDEV_PHUB_TDMEM58_ORIG_TD0 EQU 0x400079d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_ORIG_TD1 +CYDEV_PHUB_TDMEM58_ORIG_TD1 EQU 0x400079d4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_BASE +CYDEV_PHUB_TDMEM59_BASE EQU 0x400079d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_SIZE +CYDEV_PHUB_TDMEM59_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_ORIG_TD0 +CYDEV_PHUB_TDMEM59_ORIG_TD0 EQU 0x400079d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_ORIG_TD1 +CYDEV_PHUB_TDMEM59_ORIG_TD1 EQU 0x400079dc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_BASE +CYDEV_PHUB_TDMEM60_BASE EQU 0x400079e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_SIZE +CYDEV_PHUB_TDMEM60_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_ORIG_TD0 +CYDEV_PHUB_TDMEM60_ORIG_TD0 EQU 0x400079e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_ORIG_TD1 +CYDEV_PHUB_TDMEM60_ORIG_TD1 EQU 0x400079e4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_BASE +CYDEV_PHUB_TDMEM61_BASE EQU 0x400079e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_SIZE +CYDEV_PHUB_TDMEM61_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_ORIG_TD0 +CYDEV_PHUB_TDMEM61_ORIG_TD0 EQU 0x400079e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_ORIG_TD1 +CYDEV_PHUB_TDMEM61_ORIG_TD1 EQU 0x400079ec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_BASE +CYDEV_PHUB_TDMEM62_BASE EQU 0x400079f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_SIZE +CYDEV_PHUB_TDMEM62_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_ORIG_TD0 +CYDEV_PHUB_TDMEM62_ORIG_TD0 EQU 0x400079f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_ORIG_TD1 +CYDEV_PHUB_TDMEM62_ORIG_TD1 EQU 0x400079f4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_BASE +CYDEV_PHUB_TDMEM63_BASE EQU 0x400079f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_SIZE +CYDEV_PHUB_TDMEM63_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_ORIG_TD0 +CYDEV_PHUB_TDMEM63_ORIG_TD0 EQU 0x400079f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_ORIG_TD1 +CYDEV_PHUB_TDMEM63_ORIG_TD1 EQU 0x400079fc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_BASE +CYDEV_PHUB_TDMEM64_BASE EQU 0x40007a00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_SIZE +CYDEV_PHUB_TDMEM64_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_ORIG_TD0 +CYDEV_PHUB_TDMEM64_ORIG_TD0 EQU 0x40007a00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_ORIG_TD1 +CYDEV_PHUB_TDMEM64_ORIG_TD1 EQU 0x40007a04 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_BASE +CYDEV_PHUB_TDMEM65_BASE EQU 0x40007a08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_SIZE +CYDEV_PHUB_TDMEM65_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_ORIG_TD0 +CYDEV_PHUB_TDMEM65_ORIG_TD0 EQU 0x40007a08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_ORIG_TD1 +CYDEV_PHUB_TDMEM65_ORIG_TD1 EQU 0x40007a0c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_BASE +CYDEV_PHUB_TDMEM66_BASE EQU 0x40007a10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_SIZE +CYDEV_PHUB_TDMEM66_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_ORIG_TD0 +CYDEV_PHUB_TDMEM66_ORIG_TD0 EQU 0x40007a10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_ORIG_TD1 +CYDEV_PHUB_TDMEM66_ORIG_TD1 EQU 0x40007a14 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_BASE +CYDEV_PHUB_TDMEM67_BASE EQU 0x40007a18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_SIZE +CYDEV_PHUB_TDMEM67_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_ORIG_TD0 +CYDEV_PHUB_TDMEM67_ORIG_TD0 EQU 0x40007a18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_ORIG_TD1 +CYDEV_PHUB_TDMEM67_ORIG_TD1 EQU 0x40007a1c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_BASE +CYDEV_PHUB_TDMEM68_BASE EQU 0x40007a20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_SIZE +CYDEV_PHUB_TDMEM68_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_ORIG_TD0 +CYDEV_PHUB_TDMEM68_ORIG_TD0 EQU 0x40007a20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_ORIG_TD1 +CYDEV_PHUB_TDMEM68_ORIG_TD1 EQU 0x40007a24 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_BASE +CYDEV_PHUB_TDMEM69_BASE EQU 0x40007a28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_SIZE +CYDEV_PHUB_TDMEM69_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_ORIG_TD0 +CYDEV_PHUB_TDMEM69_ORIG_TD0 EQU 0x40007a28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_ORIG_TD1 +CYDEV_PHUB_TDMEM69_ORIG_TD1 EQU 0x40007a2c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_BASE +CYDEV_PHUB_TDMEM70_BASE EQU 0x40007a30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_SIZE +CYDEV_PHUB_TDMEM70_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_ORIG_TD0 +CYDEV_PHUB_TDMEM70_ORIG_TD0 EQU 0x40007a30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_ORIG_TD1 +CYDEV_PHUB_TDMEM70_ORIG_TD1 EQU 0x40007a34 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_BASE +CYDEV_PHUB_TDMEM71_BASE EQU 0x40007a38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_SIZE +CYDEV_PHUB_TDMEM71_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_ORIG_TD0 +CYDEV_PHUB_TDMEM71_ORIG_TD0 EQU 0x40007a38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_ORIG_TD1 +CYDEV_PHUB_TDMEM71_ORIG_TD1 EQU 0x40007a3c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_BASE +CYDEV_PHUB_TDMEM72_BASE EQU 0x40007a40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_SIZE +CYDEV_PHUB_TDMEM72_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_ORIG_TD0 +CYDEV_PHUB_TDMEM72_ORIG_TD0 EQU 0x40007a40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_ORIG_TD1 +CYDEV_PHUB_TDMEM72_ORIG_TD1 EQU 0x40007a44 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_BASE +CYDEV_PHUB_TDMEM73_BASE EQU 0x40007a48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_SIZE +CYDEV_PHUB_TDMEM73_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_ORIG_TD0 +CYDEV_PHUB_TDMEM73_ORIG_TD0 EQU 0x40007a48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_ORIG_TD1 +CYDEV_PHUB_TDMEM73_ORIG_TD1 EQU 0x40007a4c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_BASE +CYDEV_PHUB_TDMEM74_BASE EQU 0x40007a50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_SIZE +CYDEV_PHUB_TDMEM74_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_ORIG_TD0 +CYDEV_PHUB_TDMEM74_ORIG_TD0 EQU 0x40007a50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_ORIG_TD1 +CYDEV_PHUB_TDMEM74_ORIG_TD1 EQU 0x40007a54 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_BASE +CYDEV_PHUB_TDMEM75_BASE EQU 0x40007a58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_SIZE +CYDEV_PHUB_TDMEM75_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_ORIG_TD0 +CYDEV_PHUB_TDMEM75_ORIG_TD0 EQU 0x40007a58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_ORIG_TD1 +CYDEV_PHUB_TDMEM75_ORIG_TD1 EQU 0x40007a5c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_BASE +CYDEV_PHUB_TDMEM76_BASE EQU 0x40007a60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_SIZE +CYDEV_PHUB_TDMEM76_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_ORIG_TD0 +CYDEV_PHUB_TDMEM76_ORIG_TD0 EQU 0x40007a60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_ORIG_TD1 +CYDEV_PHUB_TDMEM76_ORIG_TD1 EQU 0x40007a64 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_BASE +CYDEV_PHUB_TDMEM77_BASE EQU 0x40007a68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_SIZE +CYDEV_PHUB_TDMEM77_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_ORIG_TD0 +CYDEV_PHUB_TDMEM77_ORIG_TD0 EQU 0x40007a68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_ORIG_TD1 +CYDEV_PHUB_TDMEM77_ORIG_TD1 EQU 0x40007a6c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_BASE +CYDEV_PHUB_TDMEM78_BASE EQU 0x40007a70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_SIZE +CYDEV_PHUB_TDMEM78_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_ORIG_TD0 +CYDEV_PHUB_TDMEM78_ORIG_TD0 EQU 0x40007a70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_ORIG_TD1 +CYDEV_PHUB_TDMEM78_ORIG_TD1 EQU 0x40007a74 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_BASE +CYDEV_PHUB_TDMEM79_BASE EQU 0x40007a78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_SIZE +CYDEV_PHUB_TDMEM79_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_ORIG_TD0 +CYDEV_PHUB_TDMEM79_ORIG_TD0 EQU 0x40007a78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_ORIG_TD1 +CYDEV_PHUB_TDMEM79_ORIG_TD1 EQU 0x40007a7c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_BASE +CYDEV_PHUB_TDMEM80_BASE EQU 0x40007a80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_SIZE +CYDEV_PHUB_TDMEM80_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_ORIG_TD0 +CYDEV_PHUB_TDMEM80_ORIG_TD0 EQU 0x40007a80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_ORIG_TD1 +CYDEV_PHUB_TDMEM80_ORIG_TD1 EQU 0x40007a84 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_BASE +CYDEV_PHUB_TDMEM81_BASE EQU 0x40007a88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_SIZE +CYDEV_PHUB_TDMEM81_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_ORIG_TD0 +CYDEV_PHUB_TDMEM81_ORIG_TD0 EQU 0x40007a88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_ORIG_TD1 +CYDEV_PHUB_TDMEM81_ORIG_TD1 EQU 0x40007a8c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_BASE +CYDEV_PHUB_TDMEM82_BASE EQU 0x40007a90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_SIZE +CYDEV_PHUB_TDMEM82_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_ORIG_TD0 +CYDEV_PHUB_TDMEM82_ORIG_TD0 EQU 0x40007a90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_ORIG_TD1 +CYDEV_PHUB_TDMEM82_ORIG_TD1 EQU 0x40007a94 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_BASE +CYDEV_PHUB_TDMEM83_BASE EQU 0x40007a98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_SIZE +CYDEV_PHUB_TDMEM83_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_ORIG_TD0 +CYDEV_PHUB_TDMEM83_ORIG_TD0 EQU 0x40007a98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_ORIG_TD1 +CYDEV_PHUB_TDMEM83_ORIG_TD1 EQU 0x40007a9c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_BASE +CYDEV_PHUB_TDMEM84_BASE EQU 0x40007aa0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_SIZE +CYDEV_PHUB_TDMEM84_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_ORIG_TD0 +CYDEV_PHUB_TDMEM84_ORIG_TD0 EQU 0x40007aa0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_ORIG_TD1 +CYDEV_PHUB_TDMEM84_ORIG_TD1 EQU 0x40007aa4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_BASE +CYDEV_PHUB_TDMEM85_BASE EQU 0x40007aa8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_SIZE +CYDEV_PHUB_TDMEM85_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_ORIG_TD0 +CYDEV_PHUB_TDMEM85_ORIG_TD0 EQU 0x40007aa8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_ORIG_TD1 +CYDEV_PHUB_TDMEM85_ORIG_TD1 EQU 0x40007aac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_BASE +CYDEV_PHUB_TDMEM86_BASE EQU 0x40007ab0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_SIZE +CYDEV_PHUB_TDMEM86_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_ORIG_TD0 +CYDEV_PHUB_TDMEM86_ORIG_TD0 EQU 0x40007ab0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_ORIG_TD1 +CYDEV_PHUB_TDMEM86_ORIG_TD1 EQU 0x40007ab4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_BASE +CYDEV_PHUB_TDMEM87_BASE EQU 0x40007ab8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_SIZE +CYDEV_PHUB_TDMEM87_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_ORIG_TD0 +CYDEV_PHUB_TDMEM87_ORIG_TD0 EQU 0x40007ab8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_ORIG_TD1 +CYDEV_PHUB_TDMEM87_ORIG_TD1 EQU 0x40007abc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_BASE +CYDEV_PHUB_TDMEM88_BASE EQU 0x40007ac0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_SIZE +CYDEV_PHUB_TDMEM88_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_ORIG_TD0 +CYDEV_PHUB_TDMEM88_ORIG_TD0 EQU 0x40007ac0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_ORIG_TD1 +CYDEV_PHUB_TDMEM88_ORIG_TD1 EQU 0x40007ac4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_BASE +CYDEV_PHUB_TDMEM89_BASE EQU 0x40007ac8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_SIZE +CYDEV_PHUB_TDMEM89_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_ORIG_TD0 +CYDEV_PHUB_TDMEM89_ORIG_TD0 EQU 0x40007ac8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_ORIG_TD1 +CYDEV_PHUB_TDMEM89_ORIG_TD1 EQU 0x40007acc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_BASE +CYDEV_PHUB_TDMEM90_BASE EQU 0x40007ad0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_SIZE +CYDEV_PHUB_TDMEM90_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_ORIG_TD0 +CYDEV_PHUB_TDMEM90_ORIG_TD0 EQU 0x40007ad0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_ORIG_TD1 +CYDEV_PHUB_TDMEM90_ORIG_TD1 EQU 0x40007ad4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_BASE +CYDEV_PHUB_TDMEM91_BASE EQU 0x40007ad8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_SIZE +CYDEV_PHUB_TDMEM91_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_ORIG_TD0 +CYDEV_PHUB_TDMEM91_ORIG_TD0 EQU 0x40007ad8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_ORIG_TD1 +CYDEV_PHUB_TDMEM91_ORIG_TD1 EQU 0x40007adc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_BASE +CYDEV_PHUB_TDMEM92_BASE EQU 0x40007ae0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_SIZE +CYDEV_PHUB_TDMEM92_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_ORIG_TD0 +CYDEV_PHUB_TDMEM92_ORIG_TD0 EQU 0x40007ae0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_ORIG_TD1 +CYDEV_PHUB_TDMEM92_ORIG_TD1 EQU 0x40007ae4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_BASE +CYDEV_PHUB_TDMEM93_BASE EQU 0x40007ae8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_SIZE +CYDEV_PHUB_TDMEM93_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_ORIG_TD0 +CYDEV_PHUB_TDMEM93_ORIG_TD0 EQU 0x40007ae8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_ORIG_TD1 +CYDEV_PHUB_TDMEM93_ORIG_TD1 EQU 0x40007aec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_BASE +CYDEV_PHUB_TDMEM94_BASE EQU 0x40007af0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_SIZE +CYDEV_PHUB_TDMEM94_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_ORIG_TD0 +CYDEV_PHUB_TDMEM94_ORIG_TD0 EQU 0x40007af0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_ORIG_TD1 +CYDEV_PHUB_TDMEM94_ORIG_TD1 EQU 0x40007af4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_BASE +CYDEV_PHUB_TDMEM95_BASE EQU 0x40007af8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_SIZE +CYDEV_PHUB_TDMEM95_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_ORIG_TD0 +CYDEV_PHUB_TDMEM95_ORIG_TD0 EQU 0x40007af8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_ORIG_TD1 +CYDEV_PHUB_TDMEM95_ORIG_TD1 EQU 0x40007afc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_BASE +CYDEV_PHUB_TDMEM96_BASE EQU 0x40007b00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_SIZE +CYDEV_PHUB_TDMEM96_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_ORIG_TD0 +CYDEV_PHUB_TDMEM96_ORIG_TD0 EQU 0x40007b00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_ORIG_TD1 +CYDEV_PHUB_TDMEM96_ORIG_TD1 EQU 0x40007b04 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_BASE +CYDEV_PHUB_TDMEM97_BASE EQU 0x40007b08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_SIZE +CYDEV_PHUB_TDMEM97_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_ORIG_TD0 +CYDEV_PHUB_TDMEM97_ORIG_TD0 EQU 0x40007b08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_ORIG_TD1 +CYDEV_PHUB_TDMEM97_ORIG_TD1 EQU 0x40007b0c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_BASE +CYDEV_PHUB_TDMEM98_BASE EQU 0x40007b10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_SIZE +CYDEV_PHUB_TDMEM98_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_ORIG_TD0 +CYDEV_PHUB_TDMEM98_ORIG_TD0 EQU 0x40007b10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_ORIG_TD1 +CYDEV_PHUB_TDMEM98_ORIG_TD1 EQU 0x40007b14 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_BASE +CYDEV_PHUB_TDMEM99_BASE EQU 0x40007b18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_SIZE +CYDEV_PHUB_TDMEM99_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_ORIG_TD0 +CYDEV_PHUB_TDMEM99_ORIG_TD0 EQU 0x40007b18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_ORIG_TD1 +CYDEV_PHUB_TDMEM99_ORIG_TD1 EQU 0x40007b1c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_BASE +CYDEV_PHUB_TDMEM100_BASE EQU 0x40007b20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_SIZE +CYDEV_PHUB_TDMEM100_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_ORIG_TD0 +CYDEV_PHUB_TDMEM100_ORIG_TD0 EQU 0x40007b20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_ORIG_TD1 +CYDEV_PHUB_TDMEM100_ORIG_TD1 EQU 0x40007b24 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_BASE +CYDEV_PHUB_TDMEM101_BASE EQU 0x40007b28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_SIZE +CYDEV_PHUB_TDMEM101_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_ORIG_TD0 +CYDEV_PHUB_TDMEM101_ORIG_TD0 EQU 0x40007b28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_ORIG_TD1 +CYDEV_PHUB_TDMEM101_ORIG_TD1 EQU 0x40007b2c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_BASE +CYDEV_PHUB_TDMEM102_BASE EQU 0x40007b30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_SIZE +CYDEV_PHUB_TDMEM102_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_ORIG_TD0 +CYDEV_PHUB_TDMEM102_ORIG_TD0 EQU 0x40007b30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_ORIG_TD1 +CYDEV_PHUB_TDMEM102_ORIG_TD1 EQU 0x40007b34 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_BASE +CYDEV_PHUB_TDMEM103_BASE EQU 0x40007b38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_SIZE +CYDEV_PHUB_TDMEM103_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_ORIG_TD0 +CYDEV_PHUB_TDMEM103_ORIG_TD0 EQU 0x40007b38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_ORIG_TD1 +CYDEV_PHUB_TDMEM103_ORIG_TD1 EQU 0x40007b3c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_BASE +CYDEV_PHUB_TDMEM104_BASE EQU 0x40007b40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_SIZE +CYDEV_PHUB_TDMEM104_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_ORIG_TD0 +CYDEV_PHUB_TDMEM104_ORIG_TD0 EQU 0x40007b40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_ORIG_TD1 +CYDEV_PHUB_TDMEM104_ORIG_TD1 EQU 0x40007b44 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_BASE +CYDEV_PHUB_TDMEM105_BASE EQU 0x40007b48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_SIZE +CYDEV_PHUB_TDMEM105_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_ORIG_TD0 +CYDEV_PHUB_TDMEM105_ORIG_TD0 EQU 0x40007b48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_ORIG_TD1 +CYDEV_PHUB_TDMEM105_ORIG_TD1 EQU 0x40007b4c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_BASE +CYDEV_PHUB_TDMEM106_BASE EQU 0x40007b50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_SIZE +CYDEV_PHUB_TDMEM106_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_ORIG_TD0 +CYDEV_PHUB_TDMEM106_ORIG_TD0 EQU 0x40007b50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_ORIG_TD1 +CYDEV_PHUB_TDMEM106_ORIG_TD1 EQU 0x40007b54 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_BASE +CYDEV_PHUB_TDMEM107_BASE EQU 0x40007b58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_SIZE +CYDEV_PHUB_TDMEM107_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_ORIG_TD0 +CYDEV_PHUB_TDMEM107_ORIG_TD0 EQU 0x40007b58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_ORIG_TD1 +CYDEV_PHUB_TDMEM107_ORIG_TD1 EQU 0x40007b5c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_BASE +CYDEV_PHUB_TDMEM108_BASE EQU 0x40007b60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_SIZE +CYDEV_PHUB_TDMEM108_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_ORIG_TD0 +CYDEV_PHUB_TDMEM108_ORIG_TD0 EQU 0x40007b60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_ORIG_TD1 +CYDEV_PHUB_TDMEM108_ORIG_TD1 EQU 0x40007b64 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_BASE +CYDEV_PHUB_TDMEM109_BASE EQU 0x40007b68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_SIZE +CYDEV_PHUB_TDMEM109_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_ORIG_TD0 +CYDEV_PHUB_TDMEM109_ORIG_TD0 EQU 0x40007b68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_ORIG_TD1 +CYDEV_PHUB_TDMEM109_ORIG_TD1 EQU 0x40007b6c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_BASE +CYDEV_PHUB_TDMEM110_BASE EQU 0x40007b70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_SIZE +CYDEV_PHUB_TDMEM110_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_ORIG_TD0 +CYDEV_PHUB_TDMEM110_ORIG_TD0 EQU 0x40007b70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_ORIG_TD1 +CYDEV_PHUB_TDMEM110_ORIG_TD1 EQU 0x40007b74 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_BASE +CYDEV_PHUB_TDMEM111_BASE EQU 0x40007b78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_SIZE +CYDEV_PHUB_TDMEM111_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_ORIG_TD0 +CYDEV_PHUB_TDMEM111_ORIG_TD0 EQU 0x40007b78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_ORIG_TD1 +CYDEV_PHUB_TDMEM111_ORIG_TD1 EQU 0x40007b7c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_BASE +CYDEV_PHUB_TDMEM112_BASE EQU 0x40007b80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_SIZE +CYDEV_PHUB_TDMEM112_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_ORIG_TD0 +CYDEV_PHUB_TDMEM112_ORIG_TD0 EQU 0x40007b80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_ORIG_TD1 +CYDEV_PHUB_TDMEM112_ORIG_TD1 EQU 0x40007b84 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_BASE +CYDEV_PHUB_TDMEM113_BASE EQU 0x40007b88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_SIZE +CYDEV_PHUB_TDMEM113_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_ORIG_TD0 +CYDEV_PHUB_TDMEM113_ORIG_TD0 EQU 0x40007b88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_ORIG_TD1 +CYDEV_PHUB_TDMEM113_ORIG_TD1 EQU 0x40007b8c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_BASE +CYDEV_PHUB_TDMEM114_BASE EQU 0x40007b90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_SIZE +CYDEV_PHUB_TDMEM114_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_ORIG_TD0 +CYDEV_PHUB_TDMEM114_ORIG_TD0 EQU 0x40007b90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_ORIG_TD1 +CYDEV_PHUB_TDMEM114_ORIG_TD1 EQU 0x40007b94 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_BASE +CYDEV_PHUB_TDMEM115_BASE EQU 0x40007b98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_SIZE +CYDEV_PHUB_TDMEM115_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_ORIG_TD0 +CYDEV_PHUB_TDMEM115_ORIG_TD0 EQU 0x40007b98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_ORIG_TD1 +CYDEV_PHUB_TDMEM115_ORIG_TD1 EQU 0x40007b9c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_BASE +CYDEV_PHUB_TDMEM116_BASE EQU 0x40007ba0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_SIZE +CYDEV_PHUB_TDMEM116_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_ORIG_TD0 +CYDEV_PHUB_TDMEM116_ORIG_TD0 EQU 0x40007ba0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_ORIG_TD1 +CYDEV_PHUB_TDMEM116_ORIG_TD1 EQU 0x40007ba4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_BASE +CYDEV_PHUB_TDMEM117_BASE EQU 0x40007ba8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_SIZE +CYDEV_PHUB_TDMEM117_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_ORIG_TD0 +CYDEV_PHUB_TDMEM117_ORIG_TD0 EQU 0x40007ba8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_ORIG_TD1 +CYDEV_PHUB_TDMEM117_ORIG_TD1 EQU 0x40007bac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_BASE +CYDEV_PHUB_TDMEM118_BASE EQU 0x40007bb0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_SIZE +CYDEV_PHUB_TDMEM118_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_ORIG_TD0 +CYDEV_PHUB_TDMEM118_ORIG_TD0 EQU 0x40007bb0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_ORIG_TD1 +CYDEV_PHUB_TDMEM118_ORIG_TD1 EQU 0x40007bb4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_BASE +CYDEV_PHUB_TDMEM119_BASE EQU 0x40007bb8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_SIZE +CYDEV_PHUB_TDMEM119_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_ORIG_TD0 +CYDEV_PHUB_TDMEM119_ORIG_TD0 EQU 0x40007bb8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_ORIG_TD1 +CYDEV_PHUB_TDMEM119_ORIG_TD1 EQU 0x40007bbc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_BASE +CYDEV_PHUB_TDMEM120_BASE EQU 0x40007bc0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_SIZE +CYDEV_PHUB_TDMEM120_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_ORIG_TD0 +CYDEV_PHUB_TDMEM120_ORIG_TD0 EQU 0x40007bc0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_ORIG_TD1 +CYDEV_PHUB_TDMEM120_ORIG_TD1 EQU 0x40007bc4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_BASE +CYDEV_PHUB_TDMEM121_BASE EQU 0x40007bc8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_SIZE +CYDEV_PHUB_TDMEM121_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_ORIG_TD0 +CYDEV_PHUB_TDMEM121_ORIG_TD0 EQU 0x40007bc8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_ORIG_TD1 +CYDEV_PHUB_TDMEM121_ORIG_TD1 EQU 0x40007bcc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_BASE +CYDEV_PHUB_TDMEM122_BASE EQU 0x40007bd0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_SIZE +CYDEV_PHUB_TDMEM122_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_ORIG_TD0 +CYDEV_PHUB_TDMEM122_ORIG_TD0 EQU 0x40007bd0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_ORIG_TD1 +CYDEV_PHUB_TDMEM122_ORIG_TD1 EQU 0x40007bd4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_BASE +CYDEV_PHUB_TDMEM123_BASE EQU 0x40007bd8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_SIZE +CYDEV_PHUB_TDMEM123_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_ORIG_TD0 +CYDEV_PHUB_TDMEM123_ORIG_TD0 EQU 0x40007bd8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_ORIG_TD1 +CYDEV_PHUB_TDMEM123_ORIG_TD1 EQU 0x40007bdc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_BASE +CYDEV_PHUB_TDMEM124_BASE EQU 0x40007be0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_SIZE +CYDEV_PHUB_TDMEM124_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_ORIG_TD0 +CYDEV_PHUB_TDMEM124_ORIG_TD0 EQU 0x40007be0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_ORIG_TD1 +CYDEV_PHUB_TDMEM124_ORIG_TD1 EQU 0x40007be4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_BASE +CYDEV_PHUB_TDMEM125_BASE EQU 0x40007be8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_SIZE +CYDEV_PHUB_TDMEM125_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_ORIG_TD0 +CYDEV_PHUB_TDMEM125_ORIG_TD0 EQU 0x40007be8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_ORIG_TD1 +CYDEV_PHUB_TDMEM125_ORIG_TD1 EQU 0x40007bec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_BASE +CYDEV_PHUB_TDMEM126_BASE EQU 0x40007bf0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_SIZE +CYDEV_PHUB_TDMEM126_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_ORIG_TD0 +CYDEV_PHUB_TDMEM126_ORIG_TD0 EQU 0x40007bf0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_ORIG_TD1 +CYDEV_PHUB_TDMEM126_ORIG_TD1 EQU 0x40007bf4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_BASE +CYDEV_PHUB_TDMEM127_BASE EQU 0x40007bf8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_SIZE +CYDEV_PHUB_TDMEM127_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_ORIG_TD0 +CYDEV_PHUB_TDMEM127_ORIG_TD0 EQU 0x40007bf8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_ORIG_TD1 +CYDEV_PHUB_TDMEM127_ORIG_TD1 EQU 0x40007bfc + ENDIF + IF :LNOT::DEF:CYDEV_EE_BASE +CYDEV_EE_BASE EQU 0x40008000 + ENDIF + IF :LNOT::DEF:CYDEV_EE_SIZE +CYDEV_EE_SIZE EQU 0x00000800 + ENDIF + IF :LNOT::DEF:CYDEV_EE_DATA_MBASE +CYDEV_EE_DATA_MBASE EQU 0x40008000 + ENDIF + IF :LNOT::DEF:CYDEV_EE_DATA_MSIZE +CYDEV_EE_DATA_MSIZE EQU 0x00000800 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_BASE +CYDEV_CAN0_BASE EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_SIZE +CYDEV_CAN0_SIZE EQU 0x000002a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_BASE +CYDEV_CAN0_CSR_BASE EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_SIZE +CYDEV_CAN0_CSR_SIZE EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_INT_SR +CYDEV_CAN0_CSR_INT_SR EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_INT_EN +CYDEV_CAN0_CSR_INT_EN EQU 0x4000a004 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_BUF_SR +CYDEV_CAN0_CSR_BUF_SR EQU 0x4000a008 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_ERR_SR +CYDEV_CAN0_CSR_ERR_SR EQU 0x4000a00c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_CMD +CYDEV_CAN0_CSR_CMD EQU 0x4000a010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_CFG +CYDEV_CAN0_CSR_CFG EQU 0x4000a014 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_BASE +CYDEV_CAN0_TX0_BASE EQU 0x4000a020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_SIZE +CYDEV_CAN0_TX0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_CMD +CYDEV_CAN0_TX0_CMD EQU 0x4000a020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_ID +CYDEV_CAN0_TX0_ID EQU 0x4000a024 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_DH +CYDEV_CAN0_TX0_DH EQU 0x4000a028 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_DL +CYDEV_CAN0_TX0_DL EQU 0x4000a02c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_BASE +CYDEV_CAN0_TX1_BASE EQU 0x4000a030 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_SIZE +CYDEV_CAN0_TX1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_CMD +CYDEV_CAN0_TX1_CMD EQU 0x4000a030 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_ID +CYDEV_CAN0_TX1_ID EQU 0x4000a034 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_DH +CYDEV_CAN0_TX1_DH EQU 0x4000a038 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_DL +CYDEV_CAN0_TX1_DL EQU 0x4000a03c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_BASE +CYDEV_CAN0_TX2_BASE EQU 0x4000a040 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_SIZE +CYDEV_CAN0_TX2_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_CMD +CYDEV_CAN0_TX2_CMD EQU 0x4000a040 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_ID +CYDEV_CAN0_TX2_ID EQU 0x4000a044 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_DH +CYDEV_CAN0_TX2_DH EQU 0x4000a048 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_DL +CYDEV_CAN0_TX2_DL EQU 0x4000a04c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_BASE +CYDEV_CAN0_TX3_BASE EQU 0x4000a050 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_SIZE +CYDEV_CAN0_TX3_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_CMD +CYDEV_CAN0_TX3_CMD EQU 0x4000a050 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_ID +CYDEV_CAN0_TX3_ID EQU 0x4000a054 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_DH +CYDEV_CAN0_TX3_DH EQU 0x4000a058 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_DL +CYDEV_CAN0_TX3_DL EQU 0x4000a05c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_BASE +CYDEV_CAN0_TX4_BASE EQU 0x4000a060 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_SIZE +CYDEV_CAN0_TX4_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_CMD +CYDEV_CAN0_TX4_CMD EQU 0x4000a060 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_ID +CYDEV_CAN0_TX4_ID EQU 0x4000a064 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_DH +CYDEV_CAN0_TX4_DH EQU 0x4000a068 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_DL +CYDEV_CAN0_TX4_DL EQU 0x4000a06c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_BASE +CYDEV_CAN0_TX5_BASE EQU 0x4000a070 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_SIZE +CYDEV_CAN0_TX5_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_CMD +CYDEV_CAN0_TX5_CMD EQU 0x4000a070 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_ID +CYDEV_CAN0_TX5_ID EQU 0x4000a074 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_DH +CYDEV_CAN0_TX5_DH EQU 0x4000a078 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_DL +CYDEV_CAN0_TX5_DL EQU 0x4000a07c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_BASE +CYDEV_CAN0_TX6_BASE EQU 0x4000a080 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_SIZE +CYDEV_CAN0_TX6_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_CMD +CYDEV_CAN0_TX6_CMD EQU 0x4000a080 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_ID +CYDEV_CAN0_TX6_ID EQU 0x4000a084 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_DH +CYDEV_CAN0_TX6_DH EQU 0x4000a088 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_DL +CYDEV_CAN0_TX6_DL EQU 0x4000a08c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_BASE +CYDEV_CAN0_TX7_BASE EQU 0x4000a090 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_SIZE +CYDEV_CAN0_TX7_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_CMD +CYDEV_CAN0_TX7_CMD EQU 0x4000a090 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_ID +CYDEV_CAN0_TX7_ID EQU 0x4000a094 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_DH +CYDEV_CAN0_TX7_DH EQU 0x4000a098 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_DL +CYDEV_CAN0_TX7_DL EQU 0x4000a09c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_BASE +CYDEV_CAN0_RX0_BASE EQU 0x4000a0a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_SIZE +CYDEV_CAN0_RX0_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_CMD +CYDEV_CAN0_RX0_CMD EQU 0x4000a0a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_ID +CYDEV_CAN0_RX0_ID EQU 0x4000a0a4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_DH +CYDEV_CAN0_RX0_DH EQU 0x4000a0a8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_DL +CYDEV_CAN0_RX0_DL EQU 0x4000a0ac + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_AMR +CYDEV_CAN0_RX0_AMR EQU 0x4000a0b0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_ACR +CYDEV_CAN0_RX0_ACR EQU 0x4000a0b4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_AMRD +CYDEV_CAN0_RX0_AMRD EQU 0x4000a0b8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_ACRD +CYDEV_CAN0_RX0_ACRD EQU 0x4000a0bc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_BASE +CYDEV_CAN0_RX1_BASE EQU 0x4000a0c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_SIZE +CYDEV_CAN0_RX1_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_CMD +CYDEV_CAN0_RX1_CMD EQU 0x4000a0c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_ID +CYDEV_CAN0_RX1_ID EQU 0x4000a0c4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_DH +CYDEV_CAN0_RX1_DH EQU 0x4000a0c8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_DL +CYDEV_CAN0_RX1_DL EQU 0x4000a0cc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_AMR +CYDEV_CAN0_RX1_AMR EQU 0x4000a0d0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_ACR +CYDEV_CAN0_RX1_ACR EQU 0x4000a0d4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_AMRD +CYDEV_CAN0_RX1_AMRD EQU 0x4000a0d8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_ACRD +CYDEV_CAN0_RX1_ACRD EQU 0x4000a0dc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_BASE +CYDEV_CAN0_RX2_BASE EQU 0x4000a0e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_SIZE +CYDEV_CAN0_RX2_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_CMD +CYDEV_CAN0_RX2_CMD EQU 0x4000a0e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_ID +CYDEV_CAN0_RX2_ID EQU 0x4000a0e4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_DH +CYDEV_CAN0_RX2_DH EQU 0x4000a0e8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_DL +CYDEV_CAN0_RX2_DL EQU 0x4000a0ec + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_AMR +CYDEV_CAN0_RX2_AMR EQU 0x4000a0f0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_ACR +CYDEV_CAN0_RX2_ACR EQU 0x4000a0f4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_AMRD +CYDEV_CAN0_RX2_AMRD EQU 0x4000a0f8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_ACRD +CYDEV_CAN0_RX2_ACRD EQU 0x4000a0fc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_BASE +CYDEV_CAN0_RX3_BASE EQU 0x4000a100 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_SIZE +CYDEV_CAN0_RX3_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_CMD +CYDEV_CAN0_RX3_CMD EQU 0x4000a100 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_ID +CYDEV_CAN0_RX3_ID EQU 0x4000a104 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_DH +CYDEV_CAN0_RX3_DH EQU 0x4000a108 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_DL +CYDEV_CAN0_RX3_DL EQU 0x4000a10c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_AMR +CYDEV_CAN0_RX3_AMR EQU 0x4000a110 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_ACR +CYDEV_CAN0_RX3_ACR EQU 0x4000a114 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_AMRD +CYDEV_CAN0_RX3_AMRD EQU 0x4000a118 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_ACRD +CYDEV_CAN0_RX3_ACRD EQU 0x4000a11c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_BASE +CYDEV_CAN0_RX4_BASE EQU 0x4000a120 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_SIZE +CYDEV_CAN0_RX4_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_CMD +CYDEV_CAN0_RX4_CMD EQU 0x4000a120 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_ID +CYDEV_CAN0_RX4_ID EQU 0x4000a124 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_DH +CYDEV_CAN0_RX4_DH EQU 0x4000a128 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_DL +CYDEV_CAN0_RX4_DL EQU 0x4000a12c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_AMR +CYDEV_CAN0_RX4_AMR EQU 0x4000a130 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_ACR +CYDEV_CAN0_RX4_ACR EQU 0x4000a134 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_AMRD +CYDEV_CAN0_RX4_AMRD EQU 0x4000a138 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_ACRD +CYDEV_CAN0_RX4_ACRD EQU 0x4000a13c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_BASE +CYDEV_CAN0_RX5_BASE EQU 0x4000a140 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_SIZE +CYDEV_CAN0_RX5_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_CMD +CYDEV_CAN0_RX5_CMD EQU 0x4000a140 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_ID +CYDEV_CAN0_RX5_ID EQU 0x4000a144 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_DH +CYDEV_CAN0_RX5_DH EQU 0x4000a148 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_DL +CYDEV_CAN0_RX5_DL EQU 0x4000a14c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_AMR +CYDEV_CAN0_RX5_AMR EQU 0x4000a150 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_ACR +CYDEV_CAN0_RX5_ACR EQU 0x4000a154 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_AMRD +CYDEV_CAN0_RX5_AMRD EQU 0x4000a158 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_ACRD +CYDEV_CAN0_RX5_ACRD EQU 0x4000a15c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_BASE +CYDEV_CAN0_RX6_BASE EQU 0x4000a160 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_SIZE +CYDEV_CAN0_RX6_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_CMD +CYDEV_CAN0_RX6_CMD EQU 0x4000a160 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_ID +CYDEV_CAN0_RX6_ID EQU 0x4000a164 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_DH +CYDEV_CAN0_RX6_DH EQU 0x4000a168 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_DL +CYDEV_CAN0_RX6_DL EQU 0x4000a16c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_AMR +CYDEV_CAN0_RX6_AMR EQU 0x4000a170 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_ACR +CYDEV_CAN0_RX6_ACR EQU 0x4000a174 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_AMRD +CYDEV_CAN0_RX6_AMRD EQU 0x4000a178 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_ACRD +CYDEV_CAN0_RX6_ACRD EQU 0x4000a17c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_BASE +CYDEV_CAN0_RX7_BASE EQU 0x4000a180 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_SIZE +CYDEV_CAN0_RX7_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_CMD +CYDEV_CAN0_RX7_CMD EQU 0x4000a180 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_ID +CYDEV_CAN0_RX7_ID EQU 0x4000a184 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_DH +CYDEV_CAN0_RX7_DH EQU 0x4000a188 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_DL +CYDEV_CAN0_RX7_DL EQU 0x4000a18c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_AMR +CYDEV_CAN0_RX7_AMR EQU 0x4000a190 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_ACR +CYDEV_CAN0_RX7_ACR EQU 0x4000a194 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_AMRD +CYDEV_CAN0_RX7_AMRD EQU 0x4000a198 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_ACRD +CYDEV_CAN0_RX7_ACRD EQU 0x4000a19c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_BASE +CYDEV_CAN0_RX8_BASE EQU 0x4000a1a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_SIZE +CYDEV_CAN0_RX8_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_CMD +CYDEV_CAN0_RX8_CMD EQU 0x4000a1a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_ID +CYDEV_CAN0_RX8_ID EQU 0x4000a1a4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_DH +CYDEV_CAN0_RX8_DH EQU 0x4000a1a8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_DL +CYDEV_CAN0_RX8_DL EQU 0x4000a1ac + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_AMR +CYDEV_CAN0_RX8_AMR EQU 0x4000a1b0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_ACR +CYDEV_CAN0_RX8_ACR EQU 0x4000a1b4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_AMRD +CYDEV_CAN0_RX8_AMRD EQU 0x4000a1b8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_ACRD +CYDEV_CAN0_RX8_ACRD EQU 0x4000a1bc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_BASE +CYDEV_CAN0_RX9_BASE EQU 0x4000a1c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_SIZE +CYDEV_CAN0_RX9_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_CMD +CYDEV_CAN0_RX9_CMD EQU 0x4000a1c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_ID +CYDEV_CAN0_RX9_ID EQU 0x4000a1c4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_DH +CYDEV_CAN0_RX9_DH EQU 0x4000a1c8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_DL +CYDEV_CAN0_RX9_DL EQU 0x4000a1cc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_AMR +CYDEV_CAN0_RX9_AMR EQU 0x4000a1d0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_ACR +CYDEV_CAN0_RX9_ACR EQU 0x4000a1d4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_AMRD +CYDEV_CAN0_RX9_AMRD EQU 0x4000a1d8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_ACRD +CYDEV_CAN0_RX9_ACRD EQU 0x4000a1dc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_BASE +CYDEV_CAN0_RX10_BASE EQU 0x4000a1e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_SIZE +CYDEV_CAN0_RX10_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_CMD +CYDEV_CAN0_RX10_CMD EQU 0x4000a1e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_ID +CYDEV_CAN0_RX10_ID EQU 0x4000a1e4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_DH +CYDEV_CAN0_RX10_DH EQU 0x4000a1e8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_DL +CYDEV_CAN0_RX10_DL EQU 0x4000a1ec + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_AMR +CYDEV_CAN0_RX10_AMR EQU 0x4000a1f0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_ACR +CYDEV_CAN0_RX10_ACR EQU 0x4000a1f4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_AMRD +CYDEV_CAN0_RX10_AMRD EQU 0x4000a1f8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_ACRD +CYDEV_CAN0_RX10_ACRD EQU 0x4000a1fc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_BASE +CYDEV_CAN0_RX11_BASE EQU 0x4000a200 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_SIZE +CYDEV_CAN0_RX11_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_CMD +CYDEV_CAN0_RX11_CMD EQU 0x4000a200 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_ID +CYDEV_CAN0_RX11_ID EQU 0x4000a204 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_DH +CYDEV_CAN0_RX11_DH EQU 0x4000a208 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_DL +CYDEV_CAN0_RX11_DL EQU 0x4000a20c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_AMR +CYDEV_CAN0_RX11_AMR EQU 0x4000a210 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_ACR +CYDEV_CAN0_RX11_ACR EQU 0x4000a214 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_AMRD +CYDEV_CAN0_RX11_AMRD EQU 0x4000a218 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_ACRD +CYDEV_CAN0_RX11_ACRD EQU 0x4000a21c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_BASE +CYDEV_CAN0_RX12_BASE EQU 0x4000a220 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_SIZE +CYDEV_CAN0_RX12_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_CMD +CYDEV_CAN0_RX12_CMD EQU 0x4000a220 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_ID +CYDEV_CAN0_RX12_ID EQU 0x4000a224 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_DH +CYDEV_CAN0_RX12_DH EQU 0x4000a228 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_DL +CYDEV_CAN0_RX12_DL EQU 0x4000a22c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_AMR +CYDEV_CAN0_RX12_AMR EQU 0x4000a230 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_ACR +CYDEV_CAN0_RX12_ACR EQU 0x4000a234 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_AMRD +CYDEV_CAN0_RX12_AMRD EQU 0x4000a238 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_ACRD +CYDEV_CAN0_RX12_ACRD EQU 0x4000a23c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_BASE +CYDEV_CAN0_RX13_BASE EQU 0x4000a240 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_SIZE +CYDEV_CAN0_RX13_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_CMD +CYDEV_CAN0_RX13_CMD EQU 0x4000a240 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_ID +CYDEV_CAN0_RX13_ID EQU 0x4000a244 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_DH +CYDEV_CAN0_RX13_DH EQU 0x4000a248 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_DL +CYDEV_CAN0_RX13_DL EQU 0x4000a24c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_AMR +CYDEV_CAN0_RX13_AMR EQU 0x4000a250 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_ACR +CYDEV_CAN0_RX13_ACR EQU 0x4000a254 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_AMRD +CYDEV_CAN0_RX13_AMRD EQU 0x4000a258 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_ACRD +CYDEV_CAN0_RX13_ACRD EQU 0x4000a25c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_BASE +CYDEV_CAN0_RX14_BASE EQU 0x4000a260 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_SIZE +CYDEV_CAN0_RX14_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_CMD +CYDEV_CAN0_RX14_CMD EQU 0x4000a260 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_ID +CYDEV_CAN0_RX14_ID EQU 0x4000a264 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_DH +CYDEV_CAN0_RX14_DH EQU 0x4000a268 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_DL +CYDEV_CAN0_RX14_DL EQU 0x4000a26c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_AMR +CYDEV_CAN0_RX14_AMR EQU 0x4000a270 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_ACR +CYDEV_CAN0_RX14_ACR EQU 0x4000a274 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_AMRD +CYDEV_CAN0_RX14_AMRD EQU 0x4000a278 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_ACRD +CYDEV_CAN0_RX14_ACRD EQU 0x4000a27c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_BASE +CYDEV_CAN0_RX15_BASE EQU 0x4000a280 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_SIZE +CYDEV_CAN0_RX15_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_CMD +CYDEV_CAN0_RX15_CMD EQU 0x4000a280 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_ID +CYDEV_CAN0_RX15_ID EQU 0x4000a284 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_DH +CYDEV_CAN0_RX15_DH EQU 0x4000a288 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_DL +CYDEV_CAN0_RX15_DL EQU 0x4000a28c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_AMR +CYDEV_CAN0_RX15_AMR EQU 0x4000a290 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_ACR +CYDEV_CAN0_RX15_ACR EQU 0x4000a294 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_AMRD +CYDEV_CAN0_RX15_AMRD EQU 0x4000a298 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_ACRD +CYDEV_CAN0_RX15_ACRD EQU 0x4000a29c + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_BASE +CYDEV_DFB0_BASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_SIZE +CYDEV_DFB0_SIZE EQU 0x000007b5 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_BASE +CYDEV_DFB0_DPA_SRAM_BASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_SIZE +CYDEV_DFB0_DPA_SRAM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_DATA_MBASE +CYDEV_DFB0_DPA_SRAM_DATA_MBASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_DATA_MSIZE +CYDEV_DFB0_DPA_SRAM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_BASE +CYDEV_DFB0_DPB_SRAM_BASE EQU 0x4000c200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_SIZE +CYDEV_DFB0_DPB_SRAM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_DATA_MBASE +CYDEV_DFB0_DPB_SRAM_DATA_MBASE EQU 0x4000c200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_DATA_MSIZE +CYDEV_DFB0_DPB_SRAM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_BASE +CYDEV_DFB0_CSA_SRAM_BASE EQU 0x4000c400 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_SIZE +CYDEV_DFB0_CSA_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_DATA_MBASE +CYDEV_DFB0_CSA_SRAM_DATA_MBASE EQU 0x4000c400 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_DATA_MSIZE +CYDEV_DFB0_CSA_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_BASE +CYDEV_DFB0_CSB_SRAM_BASE EQU 0x4000c500 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_SIZE +CYDEV_DFB0_CSB_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_DATA_MBASE +CYDEV_DFB0_CSB_SRAM_DATA_MBASE EQU 0x4000c500 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_DATA_MSIZE +CYDEV_DFB0_CSB_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_BASE +CYDEV_DFB0_FSM_SRAM_BASE EQU 0x4000c600 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_SIZE +CYDEV_DFB0_FSM_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_DATA_MBASE +CYDEV_DFB0_FSM_SRAM_DATA_MBASE EQU 0x4000c600 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_DATA_MSIZE +CYDEV_DFB0_FSM_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_BASE +CYDEV_DFB0_ACU_SRAM_BASE EQU 0x4000c700 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_SIZE +CYDEV_DFB0_ACU_SRAM_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_DATA_MBASE +CYDEV_DFB0_ACU_SRAM_DATA_MBASE EQU 0x4000c700 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_DATA_MSIZE +CYDEV_DFB0_ACU_SRAM_DATA_MSIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CR +CYDEV_DFB0_CR EQU 0x4000c780 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_SR +CYDEV_DFB0_SR EQU 0x4000c784 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_RAM_EN +CYDEV_DFB0_RAM_EN EQU 0x4000c788 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_RAM_DIR +CYDEV_DFB0_RAM_DIR EQU 0x4000c78c + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_SEMA +CYDEV_DFB0_SEMA EQU 0x4000c790 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DSI_CTRL +CYDEV_DFB0_DSI_CTRL EQU 0x4000c794 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_INT_CTRL +CYDEV_DFB0_INT_CTRL EQU 0x4000c798 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DMA_CTRL +CYDEV_DFB0_DMA_CTRL EQU 0x4000c79c + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEA +CYDEV_DFB0_STAGEA EQU 0x4000c7a0 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEAM +CYDEV_DFB0_STAGEAM EQU 0x4000c7a1 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEAH +CYDEV_DFB0_STAGEAH EQU 0x4000c7a2 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEB +CYDEV_DFB0_STAGEB EQU 0x4000c7a4 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEBM +CYDEV_DFB0_STAGEBM EQU 0x4000c7a5 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEBH +CYDEV_DFB0_STAGEBH EQU 0x4000c7a6 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDA +CYDEV_DFB0_HOLDA EQU 0x4000c7a8 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDAM +CYDEV_DFB0_HOLDAM EQU 0x4000c7a9 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDAH +CYDEV_DFB0_HOLDAH EQU 0x4000c7aa + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDAS +CYDEV_DFB0_HOLDAS EQU 0x4000c7ab + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDB +CYDEV_DFB0_HOLDB EQU 0x4000c7ac + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDBM +CYDEV_DFB0_HOLDBM EQU 0x4000c7ad + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDBH +CYDEV_DFB0_HOLDBH EQU 0x4000c7ae + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDBS +CYDEV_DFB0_HOLDBS EQU 0x4000c7af + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_COHER +CYDEV_DFB0_COHER EQU 0x4000c7b0 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DALIGN +CYDEV_DFB0_DALIGN EQU 0x4000c7b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BASE +CYDEV_UCFG_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_SIZE +CYDEV_UCFG_SIZE EQU 0x00005040 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_BASE +CYDEV_UCFG_B0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_SIZE +CYDEV_UCFG_B0_SIZE EQU 0x00000fef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_BASE +CYDEV_UCFG_B0_P0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_SIZE +CYDEV_UCFG_B0_P0_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_BASE +CYDEV_UCFG_B0_P0_U0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_SIZE +CYDEV_UCFG_B0_P0_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT0 +CYDEV_UCFG_B0_P0_U0_PLD_IT0 EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT1 +CYDEV_UCFG_B0_P0_U0_PLD_IT1 EQU 0x40010004 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT2 +CYDEV_UCFG_B0_P0_U0_PLD_IT2 EQU 0x40010008 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT3 +CYDEV_UCFG_B0_P0_U0_PLD_IT3 EQU 0x4001000c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT4 +CYDEV_UCFG_B0_P0_U0_PLD_IT4 EQU 0x40010010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT5 +CYDEV_UCFG_B0_P0_U0_PLD_IT5 EQU 0x40010014 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT6 +CYDEV_UCFG_B0_P0_U0_PLD_IT6 EQU 0x40010018 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT7 +CYDEV_UCFG_B0_P0_U0_PLD_IT7 EQU 0x4001001c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT8 +CYDEV_UCFG_B0_P0_U0_PLD_IT8 EQU 0x40010020 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT9 +CYDEV_UCFG_B0_P0_U0_PLD_IT9 EQU 0x40010024 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT10 +CYDEV_UCFG_B0_P0_U0_PLD_IT10 EQU 0x40010028 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT11 +CYDEV_UCFG_B0_P0_U0_PLD_IT11 EQU 0x4001002c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_ORT0 +CYDEV_UCFG_B0_P0_U0_PLD_ORT0 EQU 0x40010030 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_ORT1 +CYDEV_UCFG_B0_P0_U0_PLD_ORT1 EQU 0x40010032 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_ORT2 +CYDEV_UCFG_B0_P0_U0_PLD_ORT2 EQU 0x40010034 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_ORT3 +CYDEV_UCFG_B0_P0_U0_PLD_ORT3 EQU 0x40010036 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST EQU 0x40010038 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB EQU 0x4001003a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET EQU 0x4001003c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS EQU 0x4001003e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG0 +CYDEV_UCFG_B0_P0_U0_CFG0 EQU 0x40010040 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG1 +CYDEV_UCFG_B0_P0_U0_CFG1 EQU 0x40010041 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG2 +CYDEV_UCFG_B0_P0_U0_CFG2 EQU 0x40010042 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG3 +CYDEV_UCFG_B0_P0_U0_CFG3 EQU 0x40010043 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG4 +CYDEV_UCFG_B0_P0_U0_CFG4 EQU 0x40010044 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG5 +CYDEV_UCFG_B0_P0_U0_CFG5 EQU 0x40010045 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG6 +CYDEV_UCFG_B0_P0_U0_CFG6 EQU 0x40010046 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG7 +CYDEV_UCFG_B0_P0_U0_CFG7 EQU 0x40010047 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG8 +CYDEV_UCFG_B0_P0_U0_CFG8 EQU 0x40010048 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG9 +CYDEV_UCFG_B0_P0_U0_CFG9 EQU 0x40010049 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG10 +CYDEV_UCFG_B0_P0_U0_CFG10 EQU 0x4001004a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG11 +CYDEV_UCFG_B0_P0_U0_CFG11 EQU 0x4001004b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG12 +CYDEV_UCFG_B0_P0_U0_CFG12 EQU 0x4001004c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG13 +CYDEV_UCFG_B0_P0_U0_CFG13 EQU 0x4001004d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG14 +CYDEV_UCFG_B0_P0_U0_CFG14 EQU 0x4001004e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG15 +CYDEV_UCFG_B0_P0_U0_CFG15 EQU 0x4001004f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG16 +CYDEV_UCFG_B0_P0_U0_CFG16 EQU 0x40010050 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG17 +CYDEV_UCFG_B0_P0_U0_CFG17 EQU 0x40010051 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG18 +CYDEV_UCFG_B0_P0_U0_CFG18 EQU 0x40010052 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG19 +CYDEV_UCFG_B0_P0_U0_CFG19 EQU 0x40010053 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG20 +CYDEV_UCFG_B0_P0_U0_CFG20 EQU 0x40010054 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG21 +CYDEV_UCFG_B0_P0_U0_CFG21 EQU 0x40010055 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG22 +CYDEV_UCFG_B0_P0_U0_CFG22 EQU 0x40010056 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG23 +CYDEV_UCFG_B0_P0_U0_CFG23 EQU 0x40010057 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG24 +CYDEV_UCFG_B0_P0_U0_CFG24 EQU 0x40010058 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG25 +CYDEV_UCFG_B0_P0_U0_CFG25 EQU 0x40010059 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG26 +CYDEV_UCFG_B0_P0_U0_CFG26 EQU 0x4001005a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG27 +CYDEV_UCFG_B0_P0_U0_CFG27 EQU 0x4001005b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG28 +CYDEV_UCFG_B0_P0_U0_CFG28 EQU 0x4001005c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG29 +CYDEV_UCFG_B0_P0_U0_CFG29 EQU 0x4001005d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG30 +CYDEV_UCFG_B0_P0_U0_CFG30 EQU 0x4001005e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG31 +CYDEV_UCFG_B0_P0_U0_CFG31 EQU 0x4001005f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG0 +CYDEV_UCFG_B0_P0_U0_DCFG0 EQU 0x40010060 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG1 +CYDEV_UCFG_B0_P0_U0_DCFG1 EQU 0x40010062 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG2 +CYDEV_UCFG_B0_P0_U0_DCFG2 EQU 0x40010064 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG3 +CYDEV_UCFG_B0_P0_U0_DCFG3 EQU 0x40010066 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG4 +CYDEV_UCFG_B0_P0_U0_DCFG4 EQU 0x40010068 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG5 +CYDEV_UCFG_B0_P0_U0_DCFG5 EQU 0x4001006a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG6 +CYDEV_UCFG_B0_P0_U0_DCFG6 EQU 0x4001006c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG7 +CYDEV_UCFG_B0_P0_U0_DCFG7 EQU 0x4001006e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_BASE +CYDEV_UCFG_B0_P0_U1_BASE EQU 0x40010080 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_SIZE +CYDEV_UCFG_B0_P0_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT0 +CYDEV_UCFG_B0_P0_U1_PLD_IT0 EQU 0x40010080 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT1 +CYDEV_UCFG_B0_P0_U1_PLD_IT1 EQU 0x40010084 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT2 +CYDEV_UCFG_B0_P0_U1_PLD_IT2 EQU 0x40010088 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT3 +CYDEV_UCFG_B0_P0_U1_PLD_IT3 EQU 0x4001008c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT4 +CYDEV_UCFG_B0_P0_U1_PLD_IT4 EQU 0x40010090 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT5 +CYDEV_UCFG_B0_P0_U1_PLD_IT5 EQU 0x40010094 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT6 +CYDEV_UCFG_B0_P0_U1_PLD_IT6 EQU 0x40010098 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT7 +CYDEV_UCFG_B0_P0_U1_PLD_IT7 EQU 0x4001009c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT8 +CYDEV_UCFG_B0_P0_U1_PLD_IT8 EQU 0x400100a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT9 +CYDEV_UCFG_B0_P0_U1_PLD_IT9 EQU 0x400100a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT10 +CYDEV_UCFG_B0_P0_U1_PLD_IT10 EQU 0x400100a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT11 +CYDEV_UCFG_B0_P0_U1_PLD_IT11 EQU 0x400100ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_ORT0 +CYDEV_UCFG_B0_P0_U1_PLD_ORT0 EQU 0x400100b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_ORT1 +CYDEV_UCFG_B0_P0_U1_PLD_ORT1 EQU 0x400100b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_ORT2 +CYDEV_UCFG_B0_P0_U1_PLD_ORT2 EQU 0x400100b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_ORT3 +CYDEV_UCFG_B0_P0_U1_PLD_ORT3 EQU 0x400100b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST EQU 0x400100b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB EQU 0x400100ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET EQU 0x400100bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS EQU 0x400100be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG0 +CYDEV_UCFG_B0_P0_U1_CFG0 EQU 0x400100c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG1 +CYDEV_UCFG_B0_P0_U1_CFG1 EQU 0x400100c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG2 +CYDEV_UCFG_B0_P0_U1_CFG2 EQU 0x400100c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG3 +CYDEV_UCFG_B0_P0_U1_CFG3 EQU 0x400100c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG4 +CYDEV_UCFG_B0_P0_U1_CFG4 EQU 0x400100c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG5 +CYDEV_UCFG_B0_P0_U1_CFG5 EQU 0x400100c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG6 +CYDEV_UCFG_B0_P0_U1_CFG6 EQU 0x400100c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG7 +CYDEV_UCFG_B0_P0_U1_CFG7 EQU 0x400100c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG8 +CYDEV_UCFG_B0_P0_U1_CFG8 EQU 0x400100c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG9 +CYDEV_UCFG_B0_P0_U1_CFG9 EQU 0x400100c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG10 +CYDEV_UCFG_B0_P0_U1_CFG10 EQU 0x400100ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG11 +CYDEV_UCFG_B0_P0_U1_CFG11 EQU 0x400100cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG12 +CYDEV_UCFG_B0_P0_U1_CFG12 EQU 0x400100cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG13 +CYDEV_UCFG_B0_P0_U1_CFG13 EQU 0x400100cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG14 +CYDEV_UCFG_B0_P0_U1_CFG14 EQU 0x400100ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG15 +CYDEV_UCFG_B0_P0_U1_CFG15 EQU 0x400100cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG16 +CYDEV_UCFG_B0_P0_U1_CFG16 EQU 0x400100d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG17 +CYDEV_UCFG_B0_P0_U1_CFG17 EQU 0x400100d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG18 +CYDEV_UCFG_B0_P0_U1_CFG18 EQU 0x400100d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG19 +CYDEV_UCFG_B0_P0_U1_CFG19 EQU 0x400100d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG20 +CYDEV_UCFG_B0_P0_U1_CFG20 EQU 0x400100d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG21 +CYDEV_UCFG_B0_P0_U1_CFG21 EQU 0x400100d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG22 +CYDEV_UCFG_B0_P0_U1_CFG22 EQU 0x400100d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG23 +CYDEV_UCFG_B0_P0_U1_CFG23 EQU 0x400100d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG24 +CYDEV_UCFG_B0_P0_U1_CFG24 EQU 0x400100d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG25 +CYDEV_UCFG_B0_P0_U1_CFG25 EQU 0x400100d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG26 +CYDEV_UCFG_B0_P0_U1_CFG26 EQU 0x400100da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG27 +CYDEV_UCFG_B0_P0_U1_CFG27 EQU 0x400100db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG28 +CYDEV_UCFG_B0_P0_U1_CFG28 EQU 0x400100dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG29 +CYDEV_UCFG_B0_P0_U1_CFG29 EQU 0x400100dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG30 +CYDEV_UCFG_B0_P0_U1_CFG30 EQU 0x400100de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG31 +CYDEV_UCFG_B0_P0_U1_CFG31 EQU 0x400100df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG0 +CYDEV_UCFG_B0_P0_U1_DCFG0 EQU 0x400100e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG1 +CYDEV_UCFG_B0_P0_U1_DCFG1 EQU 0x400100e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG2 +CYDEV_UCFG_B0_P0_U1_DCFG2 EQU 0x400100e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG3 +CYDEV_UCFG_B0_P0_U1_DCFG3 EQU 0x400100e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG4 +CYDEV_UCFG_B0_P0_U1_DCFG4 EQU 0x400100e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG5 +CYDEV_UCFG_B0_P0_U1_DCFG5 EQU 0x400100ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG6 +CYDEV_UCFG_B0_P0_U1_DCFG6 EQU 0x400100ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG7 +CYDEV_UCFG_B0_P0_U1_DCFG7 EQU 0x400100ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_ROUTE_BASE +CYDEV_UCFG_B0_P0_ROUTE_BASE EQU 0x40010100 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_ROUTE_SIZE +CYDEV_UCFG_B0_P0_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_BASE +CYDEV_UCFG_B0_P1_BASE EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_SIZE +CYDEV_UCFG_B0_P1_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_BASE +CYDEV_UCFG_B0_P1_U0_BASE EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_SIZE +CYDEV_UCFG_B0_P1_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT0 +CYDEV_UCFG_B0_P1_U0_PLD_IT0 EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT1 +CYDEV_UCFG_B0_P1_U0_PLD_IT1 EQU 0x40010204 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT2 +CYDEV_UCFG_B0_P1_U0_PLD_IT2 EQU 0x40010208 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT3 +CYDEV_UCFG_B0_P1_U0_PLD_IT3 EQU 0x4001020c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT4 +CYDEV_UCFG_B0_P1_U0_PLD_IT4 EQU 0x40010210 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT5 +CYDEV_UCFG_B0_P1_U0_PLD_IT5 EQU 0x40010214 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT6 +CYDEV_UCFG_B0_P1_U0_PLD_IT6 EQU 0x40010218 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT7 +CYDEV_UCFG_B0_P1_U0_PLD_IT7 EQU 0x4001021c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT8 +CYDEV_UCFG_B0_P1_U0_PLD_IT8 EQU 0x40010220 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT9 +CYDEV_UCFG_B0_P1_U0_PLD_IT9 EQU 0x40010224 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT10 +CYDEV_UCFG_B0_P1_U0_PLD_IT10 EQU 0x40010228 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT11 +CYDEV_UCFG_B0_P1_U0_PLD_IT11 EQU 0x4001022c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_ORT0 +CYDEV_UCFG_B0_P1_U0_PLD_ORT0 EQU 0x40010230 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_ORT1 +CYDEV_UCFG_B0_P1_U0_PLD_ORT1 EQU 0x40010232 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_ORT2 +CYDEV_UCFG_B0_P1_U0_PLD_ORT2 EQU 0x40010234 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_ORT3 +CYDEV_UCFG_B0_P1_U0_PLD_ORT3 EQU 0x40010236 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST EQU 0x40010238 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB EQU 0x4001023a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET EQU 0x4001023c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS EQU 0x4001023e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG0 +CYDEV_UCFG_B0_P1_U0_CFG0 EQU 0x40010240 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG1 +CYDEV_UCFG_B0_P1_U0_CFG1 EQU 0x40010241 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG2 +CYDEV_UCFG_B0_P1_U0_CFG2 EQU 0x40010242 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG3 +CYDEV_UCFG_B0_P1_U0_CFG3 EQU 0x40010243 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG4 +CYDEV_UCFG_B0_P1_U0_CFG4 EQU 0x40010244 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG5 +CYDEV_UCFG_B0_P1_U0_CFG5 EQU 0x40010245 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG6 +CYDEV_UCFG_B0_P1_U0_CFG6 EQU 0x40010246 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG7 +CYDEV_UCFG_B0_P1_U0_CFG7 EQU 0x40010247 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG8 +CYDEV_UCFG_B0_P1_U0_CFG8 EQU 0x40010248 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG9 +CYDEV_UCFG_B0_P1_U0_CFG9 EQU 0x40010249 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG10 +CYDEV_UCFG_B0_P1_U0_CFG10 EQU 0x4001024a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG11 +CYDEV_UCFG_B0_P1_U0_CFG11 EQU 0x4001024b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG12 +CYDEV_UCFG_B0_P1_U0_CFG12 EQU 0x4001024c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG13 +CYDEV_UCFG_B0_P1_U0_CFG13 EQU 0x4001024d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG14 +CYDEV_UCFG_B0_P1_U0_CFG14 EQU 0x4001024e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG15 +CYDEV_UCFG_B0_P1_U0_CFG15 EQU 0x4001024f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG16 +CYDEV_UCFG_B0_P1_U0_CFG16 EQU 0x40010250 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG17 +CYDEV_UCFG_B0_P1_U0_CFG17 EQU 0x40010251 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG18 +CYDEV_UCFG_B0_P1_U0_CFG18 EQU 0x40010252 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG19 +CYDEV_UCFG_B0_P1_U0_CFG19 EQU 0x40010253 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG20 +CYDEV_UCFG_B0_P1_U0_CFG20 EQU 0x40010254 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG21 +CYDEV_UCFG_B0_P1_U0_CFG21 EQU 0x40010255 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG22 +CYDEV_UCFG_B0_P1_U0_CFG22 EQU 0x40010256 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG23 +CYDEV_UCFG_B0_P1_U0_CFG23 EQU 0x40010257 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG24 +CYDEV_UCFG_B0_P1_U0_CFG24 EQU 0x40010258 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG25 +CYDEV_UCFG_B0_P1_U0_CFG25 EQU 0x40010259 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG26 +CYDEV_UCFG_B0_P1_U0_CFG26 EQU 0x4001025a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG27 +CYDEV_UCFG_B0_P1_U0_CFG27 EQU 0x4001025b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG28 +CYDEV_UCFG_B0_P1_U0_CFG28 EQU 0x4001025c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG29 +CYDEV_UCFG_B0_P1_U0_CFG29 EQU 0x4001025d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG30 +CYDEV_UCFG_B0_P1_U0_CFG30 EQU 0x4001025e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG31 +CYDEV_UCFG_B0_P1_U0_CFG31 EQU 0x4001025f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG0 +CYDEV_UCFG_B0_P1_U0_DCFG0 EQU 0x40010260 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG1 +CYDEV_UCFG_B0_P1_U0_DCFG1 EQU 0x40010262 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG2 +CYDEV_UCFG_B0_P1_U0_DCFG2 EQU 0x40010264 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG3 +CYDEV_UCFG_B0_P1_U0_DCFG3 EQU 0x40010266 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG4 +CYDEV_UCFG_B0_P1_U0_DCFG4 EQU 0x40010268 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG5 +CYDEV_UCFG_B0_P1_U0_DCFG5 EQU 0x4001026a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG6 +CYDEV_UCFG_B0_P1_U0_DCFG6 EQU 0x4001026c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG7 +CYDEV_UCFG_B0_P1_U0_DCFG7 EQU 0x4001026e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_BASE +CYDEV_UCFG_B0_P1_U1_BASE EQU 0x40010280 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_SIZE +CYDEV_UCFG_B0_P1_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT0 +CYDEV_UCFG_B0_P1_U1_PLD_IT0 EQU 0x40010280 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT1 +CYDEV_UCFG_B0_P1_U1_PLD_IT1 EQU 0x40010284 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT2 +CYDEV_UCFG_B0_P1_U1_PLD_IT2 EQU 0x40010288 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT3 +CYDEV_UCFG_B0_P1_U1_PLD_IT3 EQU 0x4001028c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT4 +CYDEV_UCFG_B0_P1_U1_PLD_IT4 EQU 0x40010290 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT5 +CYDEV_UCFG_B0_P1_U1_PLD_IT5 EQU 0x40010294 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT6 +CYDEV_UCFG_B0_P1_U1_PLD_IT6 EQU 0x40010298 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT7 +CYDEV_UCFG_B0_P1_U1_PLD_IT7 EQU 0x4001029c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT8 +CYDEV_UCFG_B0_P1_U1_PLD_IT8 EQU 0x400102a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT9 +CYDEV_UCFG_B0_P1_U1_PLD_IT9 EQU 0x400102a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT10 +CYDEV_UCFG_B0_P1_U1_PLD_IT10 EQU 0x400102a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT11 +CYDEV_UCFG_B0_P1_U1_PLD_IT11 EQU 0x400102ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_ORT0 +CYDEV_UCFG_B0_P1_U1_PLD_ORT0 EQU 0x400102b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_ORT1 +CYDEV_UCFG_B0_P1_U1_PLD_ORT1 EQU 0x400102b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_ORT2 +CYDEV_UCFG_B0_P1_U1_PLD_ORT2 EQU 0x400102b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_ORT3 +CYDEV_UCFG_B0_P1_U1_PLD_ORT3 EQU 0x400102b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST EQU 0x400102b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB EQU 0x400102ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET EQU 0x400102bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS EQU 0x400102be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG0 +CYDEV_UCFG_B0_P1_U1_CFG0 EQU 0x400102c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG1 +CYDEV_UCFG_B0_P1_U1_CFG1 EQU 0x400102c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG2 +CYDEV_UCFG_B0_P1_U1_CFG2 EQU 0x400102c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG3 +CYDEV_UCFG_B0_P1_U1_CFG3 EQU 0x400102c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG4 +CYDEV_UCFG_B0_P1_U1_CFG4 EQU 0x400102c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG5 +CYDEV_UCFG_B0_P1_U1_CFG5 EQU 0x400102c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG6 +CYDEV_UCFG_B0_P1_U1_CFG6 EQU 0x400102c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG7 +CYDEV_UCFG_B0_P1_U1_CFG7 EQU 0x400102c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG8 +CYDEV_UCFG_B0_P1_U1_CFG8 EQU 0x400102c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG9 +CYDEV_UCFG_B0_P1_U1_CFG9 EQU 0x400102c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG10 +CYDEV_UCFG_B0_P1_U1_CFG10 EQU 0x400102ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG11 +CYDEV_UCFG_B0_P1_U1_CFG11 EQU 0x400102cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG12 +CYDEV_UCFG_B0_P1_U1_CFG12 EQU 0x400102cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG13 +CYDEV_UCFG_B0_P1_U1_CFG13 EQU 0x400102cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG14 +CYDEV_UCFG_B0_P1_U1_CFG14 EQU 0x400102ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG15 +CYDEV_UCFG_B0_P1_U1_CFG15 EQU 0x400102cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG16 +CYDEV_UCFG_B0_P1_U1_CFG16 EQU 0x400102d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG17 +CYDEV_UCFG_B0_P1_U1_CFG17 EQU 0x400102d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG18 +CYDEV_UCFG_B0_P1_U1_CFG18 EQU 0x400102d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG19 +CYDEV_UCFG_B0_P1_U1_CFG19 EQU 0x400102d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG20 +CYDEV_UCFG_B0_P1_U1_CFG20 EQU 0x400102d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG21 +CYDEV_UCFG_B0_P1_U1_CFG21 EQU 0x400102d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG22 +CYDEV_UCFG_B0_P1_U1_CFG22 EQU 0x400102d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG23 +CYDEV_UCFG_B0_P1_U1_CFG23 EQU 0x400102d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG24 +CYDEV_UCFG_B0_P1_U1_CFG24 EQU 0x400102d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG25 +CYDEV_UCFG_B0_P1_U1_CFG25 EQU 0x400102d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG26 +CYDEV_UCFG_B0_P1_U1_CFG26 EQU 0x400102da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG27 +CYDEV_UCFG_B0_P1_U1_CFG27 EQU 0x400102db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG28 +CYDEV_UCFG_B0_P1_U1_CFG28 EQU 0x400102dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG29 +CYDEV_UCFG_B0_P1_U1_CFG29 EQU 0x400102dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG30 +CYDEV_UCFG_B0_P1_U1_CFG30 EQU 0x400102de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG31 +CYDEV_UCFG_B0_P1_U1_CFG31 EQU 0x400102df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG0 +CYDEV_UCFG_B0_P1_U1_DCFG0 EQU 0x400102e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG1 +CYDEV_UCFG_B0_P1_U1_DCFG1 EQU 0x400102e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG2 +CYDEV_UCFG_B0_P1_U1_DCFG2 EQU 0x400102e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG3 +CYDEV_UCFG_B0_P1_U1_DCFG3 EQU 0x400102e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG4 +CYDEV_UCFG_B0_P1_U1_DCFG4 EQU 0x400102e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG5 +CYDEV_UCFG_B0_P1_U1_DCFG5 EQU 0x400102ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG6 +CYDEV_UCFG_B0_P1_U1_DCFG6 EQU 0x400102ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG7 +CYDEV_UCFG_B0_P1_U1_DCFG7 EQU 0x400102ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_ROUTE_BASE +CYDEV_UCFG_B0_P1_ROUTE_BASE EQU 0x40010300 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_ROUTE_SIZE +CYDEV_UCFG_B0_P1_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_BASE +CYDEV_UCFG_B0_P2_BASE EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_SIZE +CYDEV_UCFG_B0_P2_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_BASE +CYDEV_UCFG_B0_P2_U0_BASE EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_SIZE +CYDEV_UCFG_B0_P2_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT0 +CYDEV_UCFG_B0_P2_U0_PLD_IT0 EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT1 +CYDEV_UCFG_B0_P2_U0_PLD_IT1 EQU 0x40010404 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT2 +CYDEV_UCFG_B0_P2_U0_PLD_IT2 EQU 0x40010408 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT3 +CYDEV_UCFG_B0_P2_U0_PLD_IT3 EQU 0x4001040c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT4 +CYDEV_UCFG_B0_P2_U0_PLD_IT4 EQU 0x40010410 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT5 +CYDEV_UCFG_B0_P2_U0_PLD_IT5 EQU 0x40010414 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT6 +CYDEV_UCFG_B0_P2_U0_PLD_IT6 EQU 0x40010418 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT7 +CYDEV_UCFG_B0_P2_U0_PLD_IT7 EQU 0x4001041c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT8 +CYDEV_UCFG_B0_P2_U0_PLD_IT8 EQU 0x40010420 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT9 +CYDEV_UCFG_B0_P2_U0_PLD_IT9 EQU 0x40010424 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT10 +CYDEV_UCFG_B0_P2_U0_PLD_IT10 EQU 0x40010428 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT11 +CYDEV_UCFG_B0_P2_U0_PLD_IT11 EQU 0x4001042c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_ORT0 +CYDEV_UCFG_B0_P2_U0_PLD_ORT0 EQU 0x40010430 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_ORT1 +CYDEV_UCFG_B0_P2_U0_PLD_ORT1 EQU 0x40010432 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_ORT2 +CYDEV_UCFG_B0_P2_U0_PLD_ORT2 EQU 0x40010434 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_ORT3 +CYDEV_UCFG_B0_P2_U0_PLD_ORT3 EQU 0x40010436 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST EQU 0x40010438 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB EQU 0x4001043a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET EQU 0x4001043c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS EQU 0x4001043e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG0 +CYDEV_UCFG_B0_P2_U0_CFG0 EQU 0x40010440 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG1 +CYDEV_UCFG_B0_P2_U0_CFG1 EQU 0x40010441 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG2 +CYDEV_UCFG_B0_P2_U0_CFG2 EQU 0x40010442 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG3 +CYDEV_UCFG_B0_P2_U0_CFG3 EQU 0x40010443 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG4 +CYDEV_UCFG_B0_P2_U0_CFG4 EQU 0x40010444 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG5 +CYDEV_UCFG_B0_P2_U0_CFG5 EQU 0x40010445 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG6 +CYDEV_UCFG_B0_P2_U0_CFG6 EQU 0x40010446 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG7 +CYDEV_UCFG_B0_P2_U0_CFG7 EQU 0x40010447 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG8 +CYDEV_UCFG_B0_P2_U0_CFG8 EQU 0x40010448 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG9 +CYDEV_UCFG_B0_P2_U0_CFG9 EQU 0x40010449 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG10 +CYDEV_UCFG_B0_P2_U0_CFG10 EQU 0x4001044a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG11 +CYDEV_UCFG_B0_P2_U0_CFG11 EQU 0x4001044b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG12 +CYDEV_UCFG_B0_P2_U0_CFG12 EQU 0x4001044c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG13 +CYDEV_UCFG_B0_P2_U0_CFG13 EQU 0x4001044d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG14 +CYDEV_UCFG_B0_P2_U0_CFG14 EQU 0x4001044e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG15 +CYDEV_UCFG_B0_P2_U0_CFG15 EQU 0x4001044f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG16 +CYDEV_UCFG_B0_P2_U0_CFG16 EQU 0x40010450 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG17 +CYDEV_UCFG_B0_P2_U0_CFG17 EQU 0x40010451 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG18 +CYDEV_UCFG_B0_P2_U0_CFG18 EQU 0x40010452 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG19 +CYDEV_UCFG_B0_P2_U0_CFG19 EQU 0x40010453 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG20 +CYDEV_UCFG_B0_P2_U0_CFG20 EQU 0x40010454 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG21 +CYDEV_UCFG_B0_P2_U0_CFG21 EQU 0x40010455 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG22 +CYDEV_UCFG_B0_P2_U0_CFG22 EQU 0x40010456 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG23 +CYDEV_UCFG_B0_P2_U0_CFG23 EQU 0x40010457 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG24 +CYDEV_UCFG_B0_P2_U0_CFG24 EQU 0x40010458 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG25 +CYDEV_UCFG_B0_P2_U0_CFG25 EQU 0x40010459 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG26 +CYDEV_UCFG_B0_P2_U0_CFG26 EQU 0x4001045a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG27 +CYDEV_UCFG_B0_P2_U0_CFG27 EQU 0x4001045b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG28 +CYDEV_UCFG_B0_P2_U0_CFG28 EQU 0x4001045c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG29 +CYDEV_UCFG_B0_P2_U0_CFG29 EQU 0x4001045d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG30 +CYDEV_UCFG_B0_P2_U0_CFG30 EQU 0x4001045e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG31 +CYDEV_UCFG_B0_P2_U0_CFG31 EQU 0x4001045f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG0 +CYDEV_UCFG_B0_P2_U0_DCFG0 EQU 0x40010460 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG1 +CYDEV_UCFG_B0_P2_U0_DCFG1 EQU 0x40010462 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG2 +CYDEV_UCFG_B0_P2_U0_DCFG2 EQU 0x40010464 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG3 +CYDEV_UCFG_B0_P2_U0_DCFG3 EQU 0x40010466 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG4 +CYDEV_UCFG_B0_P2_U0_DCFG4 EQU 0x40010468 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG5 +CYDEV_UCFG_B0_P2_U0_DCFG5 EQU 0x4001046a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG6 +CYDEV_UCFG_B0_P2_U0_DCFG6 EQU 0x4001046c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG7 +CYDEV_UCFG_B0_P2_U0_DCFG7 EQU 0x4001046e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_BASE +CYDEV_UCFG_B0_P2_U1_BASE EQU 0x40010480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_SIZE +CYDEV_UCFG_B0_P2_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT0 +CYDEV_UCFG_B0_P2_U1_PLD_IT0 EQU 0x40010480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT1 +CYDEV_UCFG_B0_P2_U1_PLD_IT1 EQU 0x40010484 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT2 +CYDEV_UCFG_B0_P2_U1_PLD_IT2 EQU 0x40010488 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT3 +CYDEV_UCFG_B0_P2_U1_PLD_IT3 EQU 0x4001048c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT4 +CYDEV_UCFG_B0_P2_U1_PLD_IT4 EQU 0x40010490 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT5 +CYDEV_UCFG_B0_P2_U1_PLD_IT5 EQU 0x40010494 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT6 +CYDEV_UCFG_B0_P2_U1_PLD_IT6 EQU 0x40010498 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT7 +CYDEV_UCFG_B0_P2_U1_PLD_IT7 EQU 0x4001049c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT8 +CYDEV_UCFG_B0_P2_U1_PLD_IT8 EQU 0x400104a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT9 +CYDEV_UCFG_B0_P2_U1_PLD_IT9 EQU 0x400104a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT10 +CYDEV_UCFG_B0_P2_U1_PLD_IT10 EQU 0x400104a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT11 +CYDEV_UCFG_B0_P2_U1_PLD_IT11 EQU 0x400104ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_ORT0 +CYDEV_UCFG_B0_P2_U1_PLD_ORT0 EQU 0x400104b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_ORT1 +CYDEV_UCFG_B0_P2_U1_PLD_ORT1 EQU 0x400104b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_ORT2 +CYDEV_UCFG_B0_P2_U1_PLD_ORT2 EQU 0x400104b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_ORT3 +CYDEV_UCFG_B0_P2_U1_PLD_ORT3 EQU 0x400104b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST EQU 0x400104b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB EQU 0x400104ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET EQU 0x400104bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS EQU 0x400104be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG0 +CYDEV_UCFG_B0_P2_U1_CFG0 EQU 0x400104c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG1 +CYDEV_UCFG_B0_P2_U1_CFG1 EQU 0x400104c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG2 +CYDEV_UCFG_B0_P2_U1_CFG2 EQU 0x400104c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG3 +CYDEV_UCFG_B0_P2_U1_CFG3 EQU 0x400104c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG4 +CYDEV_UCFG_B0_P2_U1_CFG4 EQU 0x400104c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG5 +CYDEV_UCFG_B0_P2_U1_CFG5 EQU 0x400104c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG6 +CYDEV_UCFG_B0_P2_U1_CFG6 EQU 0x400104c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG7 +CYDEV_UCFG_B0_P2_U1_CFG7 EQU 0x400104c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG8 +CYDEV_UCFG_B0_P2_U1_CFG8 EQU 0x400104c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG9 +CYDEV_UCFG_B0_P2_U1_CFG9 EQU 0x400104c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG10 +CYDEV_UCFG_B0_P2_U1_CFG10 EQU 0x400104ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG11 +CYDEV_UCFG_B0_P2_U1_CFG11 EQU 0x400104cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG12 +CYDEV_UCFG_B0_P2_U1_CFG12 EQU 0x400104cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG13 +CYDEV_UCFG_B0_P2_U1_CFG13 EQU 0x400104cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG14 +CYDEV_UCFG_B0_P2_U1_CFG14 EQU 0x400104ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG15 +CYDEV_UCFG_B0_P2_U1_CFG15 EQU 0x400104cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG16 +CYDEV_UCFG_B0_P2_U1_CFG16 EQU 0x400104d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG17 +CYDEV_UCFG_B0_P2_U1_CFG17 EQU 0x400104d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG18 +CYDEV_UCFG_B0_P2_U1_CFG18 EQU 0x400104d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG19 +CYDEV_UCFG_B0_P2_U1_CFG19 EQU 0x400104d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG20 +CYDEV_UCFG_B0_P2_U1_CFG20 EQU 0x400104d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG21 +CYDEV_UCFG_B0_P2_U1_CFG21 EQU 0x400104d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG22 +CYDEV_UCFG_B0_P2_U1_CFG22 EQU 0x400104d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG23 +CYDEV_UCFG_B0_P2_U1_CFG23 EQU 0x400104d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG24 +CYDEV_UCFG_B0_P2_U1_CFG24 EQU 0x400104d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG25 +CYDEV_UCFG_B0_P2_U1_CFG25 EQU 0x400104d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG26 +CYDEV_UCFG_B0_P2_U1_CFG26 EQU 0x400104da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG27 +CYDEV_UCFG_B0_P2_U1_CFG27 EQU 0x400104db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG28 +CYDEV_UCFG_B0_P2_U1_CFG28 EQU 0x400104dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG29 +CYDEV_UCFG_B0_P2_U1_CFG29 EQU 0x400104dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG30 +CYDEV_UCFG_B0_P2_U1_CFG30 EQU 0x400104de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG31 +CYDEV_UCFG_B0_P2_U1_CFG31 EQU 0x400104df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG0 +CYDEV_UCFG_B0_P2_U1_DCFG0 EQU 0x400104e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG1 +CYDEV_UCFG_B0_P2_U1_DCFG1 EQU 0x400104e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG2 +CYDEV_UCFG_B0_P2_U1_DCFG2 EQU 0x400104e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG3 +CYDEV_UCFG_B0_P2_U1_DCFG3 EQU 0x400104e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG4 +CYDEV_UCFG_B0_P2_U1_DCFG4 EQU 0x400104e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG5 +CYDEV_UCFG_B0_P2_U1_DCFG5 EQU 0x400104ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG6 +CYDEV_UCFG_B0_P2_U1_DCFG6 EQU 0x400104ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG7 +CYDEV_UCFG_B0_P2_U1_DCFG7 EQU 0x400104ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_ROUTE_BASE +CYDEV_UCFG_B0_P2_ROUTE_BASE EQU 0x40010500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_ROUTE_SIZE +CYDEV_UCFG_B0_P2_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_BASE +CYDEV_UCFG_B0_P3_BASE EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_SIZE +CYDEV_UCFG_B0_P3_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_BASE +CYDEV_UCFG_B0_P3_U0_BASE EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_SIZE +CYDEV_UCFG_B0_P3_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT0 +CYDEV_UCFG_B0_P3_U0_PLD_IT0 EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT1 +CYDEV_UCFG_B0_P3_U0_PLD_IT1 EQU 0x40010604 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT2 +CYDEV_UCFG_B0_P3_U0_PLD_IT2 EQU 0x40010608 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT3 +CYDEV_UCFG_B0_P3_U0_PLD_IT3 EQU 0x4001060c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT4 +CYDEV_UCFG_B0_P3_U0_PLD_IT4 EQU 0x40010610 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT5 +CYDEV_UCFG_B0_P3_U0_PLD_IT5 EQU 0x40010614 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT6 +CYDEV_UCFG_B0_P3_U0_PLD_IT6 EQU 0x40010618 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT7 +CYDEV_UCFG_B0_P3_U0_PLD_IT7 EQU 0x4001061c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT8 +CYDEV_UCFG_B0_P3_U0_PLD_IT8 EQU 0x40010620 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT9 +CYDEV_UCFG_B0_P3_U0_PLD_IT9 EQU 0x40010624 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT10 +CYDEV_UCFG_B0_P3_U0_PLD_IT10 EQU 0x40010628 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT11 +CYDEV_UCFG_B0_P3_U0_PLD_IT11 EQU 0x4001062c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_ORT0 +CYDEV_UCFG_B0_P3_U0_PLD_ORT0 EQU 0x40010630 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_ORT1 +CYDEV_UCFG_B0_P3_U0_PLD_ORT1 EQU 0x40010632 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_ORT2 +CYDEV_UCFG_B0_P3_U0_PLD_ORT2 EQU 0x40010634 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_ORT3 +CYDEV_UCFG_B0_P3_U0_PLD_ORT3 EQU 0x40010636 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST EQU 0x40010638 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB EQU 0x4001063a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET EQU 0x4001063c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS EQU 0x4001063e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG0 +CYDEV_UCFG_B0_P3_U0_CFG0 EQU 0x40010640 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG1 +CYDEV_UCFG_B0_P3_U0_CFG1 EQU 0x40010641 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG2 +CYDEV_UCFG_B0_P3_U0_CFG2 EQU 0x40010642 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG3 +CYDEV_UCFG_B0_P3_U0_CFG3 EQU 0x40010643 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG4 +CYDEV_UCFG_B0_P3_U0_CFG4 EQU 0x40010644 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG5 +CYDEV_UCFG_B0_P3_U0_CFG5 EQU 0x40010645 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG6 +CYDEV_UCFG_B0_P3_U0_CFG6 EQU 0x40010646 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG7 +CYDEV_UCFG_B0_P3_U0_CFG7 EQU 0x40010647 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG8 +CYDEV_UCFG_B0_P3_U0_CFG8 EQU 0x40010648 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG9 +CYDEV_UCFG_B0_P3_U0_CFG9 EQU 0x40010649 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG10 +CYDEV_UCFG_B0_P3_U0_CFG10 EQU 0x4001064a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG11 +CYDEV_UCFG_B0_P3_U0_CFG11 EQU 0x4001064b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG12 +CYDEV_UCFG_B0_P3_U0_CFG12 EQU 0x4001064c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG13 +CYDEV_UCFG_B0_P3_U0_CFG13 EQU 0x4001064d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG14 +CYDEV_UCFG_B0_P3_U0_CFG14 EQU 0x4001064e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG15 +CYDEV_UCFG_B0_P3_U0_CFG15 EQU 0x4001064f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG16 +CYDEV_UCFG_B0_P3_U0_CFG16 EQU 0x40010650 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG17 +CYDEV_UCFG_B0_P3_U0_CFG17 EQU 0x40010651 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG18 +CYDEV_UCFG_B0_P3_U0_CFG18 EQU 0x40010652 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG19 +CYDEV_UCFG_B0_P3_U0_CFG19 EQU 0x40010653 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG20 +CYDEV_UCFG_B0_P3_U0_CFG20 EQU 0x40010654 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG21 +CYDEV_UCFG_B0_P3_U0_CFG21 EQU 0x40010655 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG22 +CYDEV_UCFG_B0_P3_U0_CFG22 EQU 0x40010656 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG23 +CYDEV_UCFG_B0_P3_U0_CFG23 EQU 0x40010657 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG24 +CYDEV_UCFG_B0_P3_U0_CFG24 EQU 0x40010658 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG25 +CYDEV_UCFG_B0_P3_U0_CFG25 EQU 0x40010659 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG26 +CYDEV_UCFG_B0_P3_U0_CFG26 EQU 0x4001065a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG27 +CYDEV_UCFG_B0_P3_U0_CFG27 EQU 0x4001065b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG28 +CYDEV_UCFG_B0_P3_U0_CFG28 EQU 0x4001065c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG29 +CYDEV_UCFG_B0_P3_U0_CFG29 EQU 0x4001065d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG30 +CYDEV_UCFG_B0_P3_U0_CFG30 EQU 0x4001065e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG31 +CYDEV_UCFG_B0_P3_U0_CFG31 EQU 0x4001065f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG0 +CYDEV_UCFG_B0_P3_U0_DCFG0 EQU 0x40010660 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG1 +CYDEV_UCFG_B0_P3_U0_DCFG1 EQU 0x40010662 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG2 +CYDEV_UCFG_B0_P3_U0_DCFG2 EQU 0x40010664 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG3 +CYDEV_UCFG_B0_P3_U0_DCFG3 EQU 0x40010666 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG4 +CYDEV_UCFG_B0_P3_U0_DCFG4 EQU 0x40010668 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG5 +CYDEV_UCFG_B0_P3_U0_DCFG5 EQU 0x4001066a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG6 +CYDEV_UCFG_B0_P3_U0_DCFG6 EQU 0x4001066c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG7 +CYDEV_UCFG_B0_P3_U0_DCFG7 EQU 0x4001066e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_BASE +CYDEV_UCFG_B0_P3_U1_BASE EQU 0x40010680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_SIZE +CYDEV_UCFG_B0_P3_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT0 +CYDEV_UCFG_B0_P3_U1_PLD_IT0 EQU 0x40010680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT1 +CYDEV_UCFG_B0_P3_U1_PLD_IT1 EQU 0x40010684 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT2 +CYDEV_UCFG_B0_P3_U1_PLD_IT2 EQU 0x40010688 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT3 +CYDEV_UCFG_B0_P3_U1_PLD_IT3 EQU 0x4001068c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT4 +CYDEV_UCFG_B0_P3_U1_PLD_IT4 EQU 0x40010690 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT5 +CYDEV_UCFG_B0_P3_U1_PLD_IT5 EQU 0x40010694 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT6 +CYDEV_UCFG_B0_P3_U1_PLD_IT6 EQU 0x40010698 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT7 +CYDEV_UCFG_B0_P3_U1_PLD_IT7 EQU 0x4001069c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT8 +CYDEV_UCFG_B0_P3_U1_PLD_IT8 EQU 0x400106a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT9 +CYDEV_UCFG_B0_P3_U1_PLD_IT9 EQU 0x400106a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT10 +CYDEV_UCFG_B0_P3_U1_PLD_IT10 EQU 0x400106a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT11 +CYDEV_UCFG_B0_P3_U1_PLD_IT11 EQU 0x400106ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_ORT0 +CYDEV_UCFG_B0_P3_U1_PLD_ORT0 EQU 0x400106b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_ORT1 +CYDEV_UCFG_B0_P3_U1_PLD_ORT1 EQU 0x400106b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_ORT2 +CYDEV_UCFG_B0_P3_U1_PLD_ORT2 EQU 0x400106b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_ORT3 +CYDEV_UCFG_B0_P3_U1_PLD_ORT3 EQU 0x400106b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST EQU 0x400106b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB EQU 0x400106ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET EQU 0x400106bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS EQU 0x400106be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG0 +CYDEV_UCFG_B0_P3_U1_CFG0 EQU 0x400106c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG1 +CYDEV_UCFG_B0_P3_U1_CFG1 EQU 0x400106c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG2 +CYDEV_UCFG_B0_P3_U1_CFG2 EQU 0x400106c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG3 +CYDEV_UCFG_B0_P3_U1_CFG3 EQU 0x400106c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG4 +CYDEV_UCFG_B0_P3_U1_CFG4 EQU 0x400106c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG5 +CYDEV_UCFG_B0_P3_U1_CFG5 EQU 0x400106c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG6 +CYDEV_UCFG_B0_P3_U1_CFG6 EQU 0x400106c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG7 +CYDEV_UCFG_B0_P3_U1_CFG7 EQU 0x400106c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG8 +CYDEV_UCFG_B0_P3_U1_CFG8 EQU 0x400106c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG9 +CYDEV_UCFG_B0_P3_U1_CFG9 EQU 0x400106c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG10 +CYDEV_UCFG_B0_P3_U1_CFG10 EQU 0x400106ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG11 +CYDEV_UCFG_B0_P3_U1_CFG11 EQU 0x400106cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG12 +CYDEV_UCFG_B0_P3_U1_CFG12 EQU 0x400106cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG13 +CYDEV_UCFG_B0_P3_U1_CFG13 EQU 0x400106cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG14 +CYDEV_UCFG_B0_P3_U1_CFG14 EQU 0x400106ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG15 +CYDEV_UCFG_B0_P3_U1_CFG15 EQU 0x400106cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG16 +CYDEV_UCFG_B0_P3_U1_CFG16 EQU 0x400106d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG17 +CYDEV_UCFG_B0_P3_U1_CFG17 EQU 0x400106d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG18 +CYDEV_UCFG_B0_P3_U1_CFG18 EQU 0x400106d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG19 +CYDEV_UCFG_B0_P3_U1_CFG19 EQU 0x400106d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG20 +CYDEV_UCFG_B0_P3_U1_CFG20 EQU 0x400106d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG21 +CYDEV_UCFG_B0_P3_U1_CFG21 EQU 0x400106d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG22 +CYDEV_UCFG_B0_P3_U1_CFG22 EQU 0x400106d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG23 +CYDEV_UCFG_B0_P3_U1_CFG23 EQU 0x400106d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG24 +CYDEV_UCFG_B0_P3_U1_CFG24 EQU 0x400106d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG25 +CYDEV_UCFG_B0_P3_U1_CFG25 EQU 0x400106d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG26 +CYDEV_UCFG_B0_P3_U1_CFG26 EQU 0x400106da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG27 +CYDEV_UCFG_B0_P3_U1_CFG27 EQU 0x400106db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG28 +CYDEV_UCFG_B0_P3_U1_CFG28 EQU 0x400106dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG29 +CYDEV_UCFG_B0_P3_U1_CFG29 EQU 0x400106dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG30 +CYDEV_UCFG_B0_P3_U1_CFG30 EQU 0x400106de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG31 +CYDEV_UCFG_B0_P3_U1_CFG31 EQU 0x400106df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG0 +CYDEV_UCFG_B0_P3_U1_DCFG0 EQU 0x400106e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG1 +CYDEV_UCFG_B0_P3_U1_DCFG1 EQU 0x400106e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG2 +CYDEV_UCFG_B0_P3_U1_DCFG2 EQU 0x400106e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG3 +CYDEV_UCFG_B0_P3_U1_DCFG3 EQU 0x400106e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG4 +CYDEV_UCFG_B0_P3_U1_DCFG4 EQU 0x400106e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG5 +CYDEV_UCFG_B0_P3_U1_DCFG5 EQU 0x400106ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG6 +CYDEV_UCFG_B0_P3_U1_DCFG6 EQU 0x400106ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG7 +CYDEV_UCFG_B0_P3_U1_DCFG7 EQU 0x400106ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_ROUTE_BASE +CYDEV_UCFG_B0_P3_ROUTE_BASE EQU 0x40010700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_ROUTE_SIZE +CYDEV_UCFG_B0_P3_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_BASE +CYDEV_UCFG_B0_P4_BASE EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_SIZE +CYDEV_UCFG_B0_P4_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_BASE +CYDEV_UCFG_B0_P4_U0_BASE EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_SIZE +CYDEV_UCFG_B0_P4_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT0 +CYDEV_UCFG_B0_P4_U0_PLD_IT0 EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT1 +CYDEV_UCFG_B0_P4_U0_PLD_IT1 EQU 0x40010804 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT2 +CYDEV_UCFG_B0_P4_U0_PLD_IT2 EQU 0x40010808 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT3 +CYDEV_UCFG_B0_P4_U0_PLD_IT3 EQU 0x4001080c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT4 +CYDEV_UCFG_B0_P4_U0_PLD_IT4 EQU 0x40010810 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT5 +CYDEV_UCFG_B0_P4_U0_PLD_IT5 EQU 0x40010814 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT6 +CYDEV_UCFG_B0_P4_U0_PLD_IT6 EQU 0x40010818 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT7 +CYDEV_UCFG_B0_P4_U0_PLD_IT7 EQU 0x4001081c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT8 +CYDEV_UCFG_B0_P4_U0_PLD_IT8 EQU 0x40010820 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT9 +CYDEV_UCFG_B0_P4_U0_PLD_IT9 EQU 0x40010824 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT10 +CYDEV_UCFG_B0_P4_U0_PLD_IT10 EQU 0x40010828 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT11 +CYDEV_UCFG_B0_P4_U0_PLD_IT11 EQU 0x4001082c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_ORT0 +CYDEV_UCFG_B0_P4_U0_PLD_ORT0 EQU 0x40010830 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_ORT1 +CYDEV_UCFG_B0_P4_U0_PLD_ORT1 EQU 0x40010832 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_ORT2 +CYDEV_UCFG_B0_P4_U0_PLD_ORT2 EQU 0x40010834 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_ORT3 +CYDEV_UCFG_B0_P4_U0_PLD_ORT3 EQU 0x40010836 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST EQU 0x40010838 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB EQU 0x4001083a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET EQU 0x4001083c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS EQU 0x4001083e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG0 +CYDEV_UCFG_B0_P4_U0_CFG0 EQU 0x40010840 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG1 +CYDEV_UCFG_B0_P4_U0_CFG1 EQU 0x40010841 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG2 +CYDEV_UCFG_B0_P4_U0_CFG2 EQU 0x40010842 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG3 +CYDEV_UCFG_B0_P4_U0_CFG3 EQU 0x40010843 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG4 +CYDEV_UCFG_B0_P4_U0_CFG4 EQU 0x40010844 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG5 +CYDEV_UCFG_B0_P4_U0_CFG5 EQU 0x40010845 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG6 +CYDEV_UCFG_B0_P4_U0_CFG6 EQU 0x40010846 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG7 +CYDEV_UCFG_B0_P4_U0_CFG7 EQU 0x40010847 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG8 +CYDEV_UCFG_B0_P4_U0_CFG8 EQU 0x40010848 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG9 +CYDEV_UCFG_B0_P4_U0_CFG9 EQU 0x40010849 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG10 +CYDEV_UCFG_B0_P4_U0_CFG10 EQU 0x4001084a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG11 +CYDEV_UCFG_B0_P4_U0_CFG11 EQU 0x4001084b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG12 +CYDEV_UCFG_B0_P4_U0_CFG12 EQU 0x4001084c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG13 +CYDEV_UCFG_B0_P4_U0_CFG13 EQU 0x4001084d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG14 +CYDEV_UCFG_B0_P4_U0_CFG14 EQU 0x4001084e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG15 +CYDEV_UCFG_B0_P4_U0_CFG15 EQU 0x4001084f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG16 +CYDEV_UCFG_B0_P4_U0_CFG16 EQU 0x40010850 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG17 +CYDEV_UCFG_B0_P4_U0_CFG17 EQU 0x40010851 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG18 +CYDEV_UCFG_B0_P4_U0_CFG18 EQU 0x40010852 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG19 +CYDEV_UCFG_B0_P4_U0_CFG19 EQU 0x40010853 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG20 +CYDEV_UCFG_B0_P4_U0_CFG20 EQU 0x40010854 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG21 +CYDEV_UCFG_B0_P4_U0_CFG21 EQU 0x40010855 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG22 +CYDEV_UCFG_B0_P4_U0_CFG22 EQU 0x40010856 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG23 +CYDEV_UCFG_B0_P4_U0_CFG23 EQU 0x40010857 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG24 +CYDEV_UCFG_B0_P4_U0_CFG24 EQU 0x40010858 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG25 +CYDEV_UCFG_B0_P4_U0_CFG25 EQU 0x40010859 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG26 +CYDEV_UCFG_B0_P4_U0_CFG26 EQU 0x4001085a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG27 +CYDEV_UCFG_B0_P4_U0_CFG27 EQU 0x4001085b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG28 +CYDEV_UCFG_B0_P4_U0_CFG28 EQU 0x4001085c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG29 +CYDEV_UCFG_B0_P4_U0_CFG29 EQU 0x4001085d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG30 +CYDEV_UCFG_B0_P4_U0_CFG30 EQU 0x4001085e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG31 +CYDEV_UCFG_B0_P4_U0_CFG31 EQU 0x4001085f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG0 +CYDEV_UCFG_B0_P4_U0_DCFG0 EQU 0x40010860 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG1 +CYDEV_UCFG_B0_P4_U0_DCFG1 EQU 0x40010862 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG2 +CYDEV_UCFG_B0_P4_U0_DCFG2 EQU 0x40010864 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG3 +CYDEV_UCFG_B0_P4_U0_DCFG3 EQU 0x40010866 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG4 +CYDEV_UCFG_B0_P4_U0_DCFG4 EQU 0x40010868 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG5 +CYDEV_UCFG_B0_P4_U0_DCFG5 EQU 0x4001086a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG6 +CYDEV_UCFG_B0_P4_U0_DCFG6 EQU 0x4001086c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG7 +CYDEV_UCFG_B0_P4_U0_DCFG7 EQU 0x4001086e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_BASE +CYDEV_UCFG_B0_P4_U1_BASE EQU 0x40010880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_SIZE +CYDEV_UCFG_B0_P4_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT0 +CYDEV_UCFG_B0_P4_U1_PLD_IT0 EQU 0x40010880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT1 +CYDEV_UCFG_B0_P4_U1_PLD_IT1 EQU 0x40010884 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT2 +CYDEV_UCFG_B0_P4_U1_PLD_IT2 EQU 0x40010888 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT3 +CYDEV_UCFG_B0_P4_U1_PLD_IT3 EQU 0x4001088c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT4 +CYDEV_UCFG_B0_P4_U1_PLD_IT4 EQU 0x40010890 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT5 +CYDEV_UCFG_B0_P4_U1_PLD_IT5 EQU 0x40010894 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT6 +CYDEV_UCFG_B0_P4_U1_PLD_IT6 EQU 0x40010898 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT7 +CYDEV_UCFG_B0_P4_U1_PLD_IT7 EQU 0x4001089c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT8 +CYDEV_UCFG_B0_P4_U1_PLD_IT8 EQU 0x400108a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT9 +CYDEV_UCFG_B0_P4_U1_PLD_IT9 EQU 0x400108a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT10 +CYDEV_UCFG_B0_P4_U1_PLD_IT10 EQU 0x400108a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT11 +CYDEV_UCFG_B0_P4_U1_PLD_IT11 EQU 0x400108ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_ORT0 +CYDEV_UCFG_B0_P4_U1_PLD_ORT0 EQU 0x400108b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_ORT1 +CYDEV_UCFG_B0_P4_U1_PLD_ORT1 EQU 0x400108b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_ORT2 +CYDEV_UCFG_B0_P4_U1_PLD_ORT2 EQU 0x400108b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_ORT3 +CYDEV_UCFG_B0_P4_U1_PLD_ORT3 EQU 0x400108b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST EQU 0x400108b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB EQU 0x400108ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET EQU 0x400108bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS EQU 0x400108be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG0 +CYDEV_UCFG_B0_P4_U1_CFG0 EQU 0x400108c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG1 +CYDEV_UCFG_B0_P4_U1_CFG1 EQU 0x400108c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG2 +CYDEV_UCFG_B0_P4_U1_CFG2 EQU 0x400108c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG3 +CYDEV_UCFG_B0_P4_U1_CFG3 EQU 0x400108c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG4 +CYDEV_UCFG_B0_P4_U1_CFG4 EQU 0x400108c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG5 +CYDEV_UCFG_B0_P4_U1_CFG5 EQU 0x400108c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG6 +CYDEV_UCFG_B0_P4_U1_CFG6 EQU 0x400108c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG7 +CYDEV_UCFG_B0_P4_U1_CFG7 EQU 0x400108c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG8 +CYDEV_UCFG_B0_P4_U1_CFG8 EQU 0x400108c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG9 +CYDEV_UCFG_B0_P4_U1_CFG9 EQU 0x400108c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG10 +CYDEV_UCFG_B0_P4_U1_CFG10 EQU 0x400108ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG11 +CYDEV_UCFG_B0_P4_U1_CFG11 EQU 0x400108cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG12 +CYDEV_UCFG_B0_P4_U1_CFG12 EQU 0x400108cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG13 +CYDEV_UCFG_B0_P4_U1_CFG13 EQU 0x400108cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG14 +CYDEV_UCFG_B0_P4_U1_CFG14 EQU 0x400108ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG15 +CYDEV_UCFG_B0_P4_U1_CFG15 EQU 0x400108cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG16 +CYDEV_UCFG_B0_P4_U1_CFG16 EQU 0x400108d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG17 +CYDEV_UCFG_B0_P4_U1_CFG17 EQU 0x400108d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG18 +CYDEV_UCFG_B0_P4_U1_CFG18 EQU 0x400108d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG19 +CYDEV_UCFG_B0_P4_U1_CFG19 EQU 0x400108d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG20 +CYDEV_UCFG_B0_P4_U1_CFG20 EQU 0x400108d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG21 +CYDEV_UCFG_B0_P4_U1_CFG21 EQU 0x400108d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG22 +CYDEV_UCFG_B0_P4_U1_CFG22 EQU 0x400108d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG23 +CYDEV_UCFG_B0_P4_U1_CFG23 EQU 0x400108d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG24 +CYDEV_UCFG_B0_P4_U1_CFG24 EQU 0x400108d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG25 +CYDEV_UCFG_B0_P4_U1_CFG25 EQU 0x400108d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG26 +CYDEV_UCFG_B0_P4_U1_CFG26 EQU 0x400108da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG27 +CYDEV_UCFG_B0_P4_U1_CFG27 EQU 0x400108db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG28 +CYDEV_UCFG_B0_P4_U1_CFG28 EQU 0x400108dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG29 +CYDEV_UCFG_B0_P4_U1_CFG29 EQU 0x400108dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG30 +CYDEV_UCFG_B0_P4_U1_CFG30 EQU 0x400108de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG31 +CYDEV_UCFG_B0_P4_U1_CFG31 EQU 0x400108df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG0 +CYDEV_UCFG_B0_P4_U1_DCFG0 EQU 0x400108e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG1 +CYDEV_UCFG_B0_P4_U1_DCFG1 EQU 0x400108e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG2 +CYDEV_UCFG_B0_P4_U1_DCFG2 EQU 0x400108e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG3 +CYDEV_UCFG_B0_P4_U1_DCFG3 EQU 0x400108e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG4 +CYDEV_UCFG_B0_P4_U1_DCFG4 EQU 0x400108e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG5 +CYDEV_UCFG_B0_P4_U1_DCFG5 EQU 0x400108ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG6 +CYDEV_UCFG_B0_P4_U1_DCFG6 EQU 0x400108ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG7 +CYDEV_UCFG_B0_P4_U1_DCFG7 EQU 0x400108ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_ROUTE_BASE +CYDEV_UCFG_B0_P4_ROUTE_BASE EQU 0x40010900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_ROUTE_SIZE +CYDEV_UCFG_B0_P4_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_BASE +CYDEV_UCFG_B0_P5_BASE EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_SIZE +CYDEV_UCFG_B0_P5_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_BASE +CYDEV_UCFG_B0_P5_U0_BASE EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_SIZE +CYDEV_UCFG_B0_P5_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT0 +CYDEV_UCFG_B0_P5_U0_PLD_IT0 EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT1 +CYDEV_UCFG_B0_P5_U0_PLD_IT1 EQU 0x40010a04 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT2 +CYDEV_UCFG_B0_P5_U0_PLD_IT2 EQU 0x40010a08 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT3 +CYDEV_UCFG_B0_P5_U0_PLD_IT3 EQU 0x40010a0c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT4 +CYDEV_UCFG_B0_P5_U0_PLD_IT4 EQU 0x40010a10 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT5 +CYDEV_UCFG_B0_P5_U0_PLD_IT5 EQU 0x40010a14 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT6 +CYDEV_UCFG_B0_P5_U0_PLD_IT6 EQU 0x40010a18 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT7 +CYDEV_UCFG_B0_P5_U0_PLD_IT7 EQU 0x40010a1c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT8 +CYDEV_UCFG_B0_P5_U0_PLD_IT8 EQU 0x40010a20 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT9 +CYDEV_UCFG_B0_P5_U0_PLD_IT9 EQU 0x40010a24 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT10 +CYDEV_UCFG_B0_P5_U0_PLD_IT10 EQU 0x40010a28 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT11 +CYDEV_UCFG_B0_P5_U0_PLD_IT11 EQU 0x40010a2c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_ORT0 +CYDEV_UCFG_B0_P5_U0_PLD_ORT0 EQU 0x40010a30 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_ORT1 +CYDEV_UCFG_B0_P5_U0_PLD_ORT1 EQU 0x40010a32 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_ORT2 +CYDEV_UCFG_B0_P5_U0_PLD_ORT2 EQU 0x40010a34 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_ORT3 +CYDEV_UCFG_B0_P5_U0_PLD_ORT3 EQU 0x40010a36 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST EQU 0x40010a38 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB EQU 0x40010a3a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET EQU 0x40010a3c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS EQU 0x40010a3e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG0 +CYDEV_UCFG_B0_P5_U0_CFG0 EQU 0x40010a40 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG1 +CYDEV_UCFG_B0_P5_U0_CFG1 EQU 0x40010a41 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG2 +CYDEV_UCFG_B0_P5_U0_CFG2 EQU 0x40010a42 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG3 +CYDEV_UCFG_B0_P5_U0_CFG3 EQU 0x40010a43 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG4 +CYDEV_UCFG_B0_P5_U0_CFG4 EQU 0x40010a44 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG5 +CYDEV_UCFG_B0_P5_U0_CFG5 EQU 0x40010a45 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG6 +CYDEV_UCFG_B0_P5_U0_CFG6 EQU 0x40010a46 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG7 +CYDEV_UCFG_B0_P5_U0_CFG7 EQU 0x40010a47 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG8 +CYDEV_UCFG_B0_P5_U0_CFG8 EQU 0x40010a48 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG9 +CYDEV_UCFG_B0_P5_U0_CFG9 EQU 0x40010a49 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG10 +CYDEV_UCFG_B0_P5_U0_CFG10 EQU 0x40010a4a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG11 +CYDEV_UCFG_B0_P5_U0_CFG11 EQU 0x40010a4b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG12 +CYDEV_UCFG_B0_P5_U0_CFG12 EQU 0x40010a4c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG13 +CYDEV_UCFG_B0_P5_U0_CFG13 EQU 0x40010a4d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG14 +CYDEV_UCFG_B0_P5_U0_CFG14 EQU 0x40010a4e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG15 +CYDEV_UCFG_B0_P5_U0_CFG15 EQU 0x40010a4f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG16 +CYDEV_UCFG_B0_P5_U0_CFG16 EQU 0x40010a50 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG17 +CYDEV_UCFG_B0_P5_U0_CFG17 EQU 0x40010a51 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG18 +CYDEV_UCFG_B0_P5_U0_CFG18 EQU 0x40010a52 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG19 +CYDEV_UCFG_B0_P5_U0_CFG19 EQU 0x40010a53 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG20 +CYDEV_UCFG_B0_P5_U0_CFG20 EQU 0x40010a54 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG21 +CYDEV_UCFG_B0_P5_U0_CFG21 EQU 0x40010a55 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG22 +CYDEV_UCFG_B0_P5_U0_CFG22 EQU 0x40010a56 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG23 +CYDEV_UCFG_B0_P5_U0_CFG23 EQU 0x40010a57 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG24 +CYDEV_UCFG_B0_P5_U0_CFG24 EQU 0x40010a58 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG25 +CYDEV_UCFG_B0_P5_U0_CFG25 EQU 0x40010a59 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG26 +CYDEV_UCFG_B0_P5_U0_CFG26 EQU 0x40010a5a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG27 +CYDEV_UCFG_B0_P5_U0_CFG27 EQU 0x40010a5b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG28 +CYDEV_UCFG_B0_P5_U0_CFG28 EQU 0x40010a5c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG29 +CYDEV_UCFG_B0_P5_U0_CFG29 EQU 0x40010a5d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG30 +CYDEV_UCFG_B0_P5_U0_CFG30 EQU 0x40010a5e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG31 +CYDEV_UCFG_B0_P5_U0_CFG31 EQU 0x40010a5f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG0 +CYDEV_UCFG_B0_P5_U0_DCFG0 EQU 0x40010a60 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG1 +CYDEV_UCFG_B0_P5_U0_DCFG1 EQU 0x40010a62 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG2 +CYDEV_UCFG_B0_P5_U0_DCFG2 EQU 0x40010a64 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG3 +CYDEV_UCFG_B0_P5_U0_DCFG3 EQU 0x40010a66 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG4 +CYDEV_UCFG_B0_P5_U0_DCFG4 EQU 0x40010a68 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG5 +CYDEV_UCFG_B0_P5_U0_DCFG5 EQU 0x40010a6a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG6 +CYDEV_UCFG_B0_P5_U0_DCFG6 EQU 0x40010a6c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG7 +CYDEV_UCFG_B0_P5_U0_DCFG7 EQU 0x40010a6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_BASE +CYDEV_UCFG_B0_P5_U1_BASE EQU 0x40010a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_SIZE +CYDEV_UCFG_B0_P5_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT0 +CYDEV_UCFG_B0_P5_U1_PLD_IT0 EQU 0x40010a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT1 +CYDEV_UCFG_B0_P5_U1_PLD_IT1 EQU 0x40010a84 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT2 +CYDEV_UCFG_B0_P5_U1_PLD_IT2 EQU 0x40010a88 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT3 +CYDEV_UCFG_B0_P5_U1_PLD_IT3 EQU 0x40010a8c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT4 +CYDEV_UCFG_B0_P5_U1_PLD_IT4 EQU 0x40010a90 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT5 +CYDEV_UCFG_B0_P5_U1_PLD_IT5 EQU 0x40010a94 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT6 +CYDEV_UCFG_B0_P5_U1_PLD_IT6 EQU 0x40010a98 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT7 +CYDEV_UCFG_B0_P5_U1_PLD_IT7 EQU 0x40010a9c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT8 +CYDEV_UCFG_B0_P5_U1_PLD_IT8 EQU 0x40010aa0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT9 +CYDEV_UCFG_B0_P5_U1_PLD_IT9 EQU 0x40010aa4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT10 +CYDEV_UCFG_B0_P5_U1_PLD_IT10 EQU 0x40010aa8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT11 +CYDEV_UCFG_B0_P5_U1_PLD_IT11 EQU 0x40010aac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_ORT0 +CYDEV_UCFG_B0_P5_U1_PLD_ORT0 EQU 0x40010ab0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_ORT1 +CYDEV_UCFG_B0_P5_U1_PLD_ORT1 EQU 0x40010ab2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_ORT2 +CYDEV_UCFG_B0_P5_U1_PLD_ORT2 EQU 0x40010ab4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_ORT3 +CYDEV_UCFG_B0_P5_U1_PLD_ORT3 EQU 0x40010ab6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST EQU 0x40010ab8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB EQU 0x40010aba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET EQU 0x40010abc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS EQU 0x40010abe + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG0 +CYDEV_UCFG_B0_P5_U1_CFG0 EQU 0x40010ac0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG1 +CYDEV_UCFG_B0_P5_U1_CFG1 EQU 0x40010ac1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG2 +CYDEV_UCFG_B0_P5_U1_CFG2 EQU 0x40010ac2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG3 +CYDEV_UCFG_B0_P5_U1_CFG3 EQU 0x40010ac3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG4 +CYDEV_UCFG_B0_P5_U1_CFG4 EQU 0x40010ac4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG5 +CYDEV_UCFG_B0_P5_U1_CFG5 EQU 0x40010ac5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG6 +CYDEV_UCFG_B0_P5_U1_CFG6 EQU 0x40010ac6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG7 +CYDEV_UCFG_B0_P5_U1_CFG7 EQU 0x40010ac7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG8 +CYDEV_UCFG_B0_P5_U1_CFG8 EQU 0x40010ac8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG9 +CYDEV_UCFG_B0_P5_U1_CFG9 EQU 0x40010ac9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG10 +CYDEV_UCFG_B0_P5_U1_CFG10 EQU 0x40010aca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG11 +CYDEV_UCFG_B0_P5_U1_CFG11 EQU 0x40010acb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG12 +CYDEV_UCFG_B0_P5_U1_CFG12 EQU 0x40010acc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG13 +CYDEV_UCFG_B0_P5_U1_CFG13 EQU 0x40010acd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG14 +CYDEV_UCFG_B0_P5_U1_CFG14 EQU 0x40010ace + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG15 +CYDEV_UCFG_B0_P5_U1_CFG15 EQU 0x40010acf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG16 +CYDEV_UCFG_B0_P5_U1_CFG16 EQU 0x40010ad0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG17 +CYDEV_UCFG_B0_P5_U1_CFG17 EQU 0x40010ad1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG18 +CYDEV_UCFG_B0_P5_U1_CFG18 EQU 0x40010ad2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG19 +CYDEV_UCFG_B0_P5_U1_CFG19 EQU 0x40010ad3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG20 +CYDEV_UCFG_B0_P5_U1_CFG20 EQU 0x40010ad4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG21 +CYDEV_UCFG_B0_P5_U1_CFG21 EQU 0x40010ad5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG22 +CYDEV_UCFG_B0_P5_U1_CFG22 EQU 0x40010ad6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG23 +CYDEV_UCFG_B0_P5_U1_CFG23 EQU 0x40010ad7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG24 +CYDEV_UCFG_B0_P5_U1_CFG24 EQU 0x40010ad8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG25 +CYDEV_UCFG_B0_P5_U1_CFG25 EQU 0x40010ad9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG26 +CYDEV_UCFG_B0_P5_U1_CFG26 EQU 0x40010ada + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG27 +CYDEV_UCFG_B0_P5_U1_CFG27 EQU 0x40010adb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG28 +CYDEV_UCFG_B0_P5_U1_CFG28 EQU 0x40010adc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG29 +CYDEV_UCFG_B0_P5_U1_CFG29 EQU 0x40010add + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG30 +CYDEV_UCFG_B0_P5_U1_CFG30 EQU 0x40010ade + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG31 +CYDEV_UCFG_B0_P5_U1_CFG31 EQU 0x40010adf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG0 +CYDEV_UCFG_B0_P5_U1_DCFG0 EQU 0x40010ae0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG1 +CYDEV_UCFG_B0_P5_U1_DCFG1 EQU 0x40010ae2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG2 +CYDEV_UCFG_B0_P5_U1_DCFG2 EQU 0x40010ae4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG3 +CYDEV_UCFG_B0_P5_U1_DCFG3 EQU 0x40010ae6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG4 +CYDEV_UCFG_B0_P5_U1_DCFG4 EQU 0x40010ae8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG5 +CYDEV_UCFG_B0_P5_U1_DCFG5 EQU 0x40010aea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG6 +CYDEV_UCFG_B0_P5_U1_DCFG6 EQU 0x40010aec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG7 +CYDEV_UCFG_B0_P5_U1_DCFG7 EQU 0x40010aee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_ROUTE_BASE +CYDEV_UCFG_B0_P5_ROUTE_BASE EQU 0x40010b00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_ROUTE_SIZE +CYDEV_UCFG_B0_P5_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_BASE +CYDEV_UCFG_B0_P6_BASE EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_SIZE +CYDEV_UCFG_B0_P6_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_BASE +CYDEV_UCFG_B0_P6_U0_BASE EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_SIZE +CYDEV_UCFG_B0_P6_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT0 +CYDEV_UCFG_B0_P6_U0_PLD_IT0 EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT1 +CYDEV_UCFG_B0_P6_U0_PLD_IT1 EQU 0x40010c04 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT2 +CYDEV_UCFG_B0_P6_U0_PLD_IT2 EQU 0x40010c08 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT3 +CYDEV_UCFG_B0_P6_U0_PLD_IT3 EQU 0x40010c0c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT4 +CYDEV_UCFG_B0_P6_U0_PLD_IT4 EQU 0x40010c10 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT5 +CYDEV_UCFG_B0_P6_U0_PLD_IT5 EQU 0x40010c14 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT6 +CYDEV_UCFG_B0_P6_U0_PLD_IT6 EQU 0x40010c18 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT7 +CYDEV_UCFG_B0_P6_U0_PLD_IT7 EQU 0x40010c1c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT8 +CYDEV_UCFG_B0_P6_U0_PLD_IT8 EQU 0x40010c20 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT9 +CYDEV_UCFG_B0_P6_U0_PLD_IT9 EQU 0x40010c24 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT10 +CYDEV_UCFG_B0_P6_U0_PLD_IT10 EQU 0x40010c28 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT11 +CYDEV_UCFG_B0_P6_U0_PLD_IT11 EQU 0x40010c2c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_ORT0 +CYDEV_UCFG_B0_P6_U0_PLD_ORT0 EQU 0x40010c30 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_ORT1 +CYDEV_UCFG_B0_P6_U0_PLD_ORT1 EQU 0x40010c32 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_ORT2 +CYDEV_UCFG_B0_P6_U0_PLD_ORT2 EQU 0x40010c34 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_ORT3 +CYDEV_UCFG_B0_P6_U0_PLD_ORT3 EQU 0x40010c36 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST EQU 0x40010c38 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB EQU 0x40010c3a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET EQU 0x40010c3c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS EQU 0x40010c3e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG0 +CYDEV_UCFG_B0_P6_U0_CFG0 EQU 0x40010c40 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG1 +CYDEV_UCFG_B0_P6_U0_CFG1 EQU 0x40010c41 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG2 +CYDEV_UCFG_B0_P6_U0_CFG2 EQU 0x40010c42 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG3 +CYDEV_UCFG_B0_P6_U0_CFG3 EQU 0x40010c43 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG4 +CYDEV_UCFG_B0_P6_U0_CFG4 EQU 0x40010c44 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG5 +CYDEV_UCFG_B0_P6_U0_CFG5 EQU 0x40010c45 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG6 +CYDEV_UCFG_B0_P6_U0_CFG6 EQU 0x40010c46 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG7 +CYDEV_UCFG_B0_P6_U0_CFG7 EQU 0x40010c47 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG8 +CYDEV_UCFG_B0_P6_U0_CFG8 EQU 0x40010c48 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG9 +CYDEV_UCFG_B0_P6_U0_CFG9 EQU 0x40010c49 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG10 +CYDEV_UCFG_B0_P6_U0_CFG10 EQU 0x40010c4a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG11 +CYDEV_UCFG_B0_P6_U0_CFG11 EQU 0x40010c4b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG12 +CYDEV_UCFG_B0_P6_U0_CFG12 EQU 0x40010c4c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG13 +CYDEV_UCFG_B0_P6_U0_CFG13 EQU 0x40010c4d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG14 +CYDEV_UCFG_B0_P6_U0_CFG14 EQU 0x40010c4e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG15 +CYDEV_UCFG_B0_P6_U0_CFG15 EQU 0x40010c4f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG16 +CYDEV_UCFG_B0_P6_U0_CFG16 EQU 0x40010c50 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG17 +CYDEV_UCFG_B0_P6_U0_CFG17 EQU 0x40010c51 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG18 +CYDEV_UCFG_B0_P6_U0_CFG18 EQU 0x40010c52 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG19 +CYDEV_UCFG_B0_P6_U0_CFG19 EQU 0x40010c53 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG20 +CYDEV_UCFG_B0_P6_U0_CFG20 EQU 0x40010c54 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG21 +CYDEV_UCFG_B0_P6_U0_CFG21 EQU 0x40010c55 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG22 +CYDEV_UCFG_B0_P6_U0_CFG22 EQU 0x40010c56 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG23 +CYDEV_UCFG_B0_P6_U0_CFG23 EQU 0x40010c57 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG24 +CYDEV_UCFG_B0_P6_U0_CFG24 EQU 0x40010c58 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG25 +CYDEV_UCFG_B0_P6_U0_CFG25 EQU 0x40010c59 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG26 +CYDEV_UCFG_B0_P6_U0_CFG26 EQU 0x40010c5a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG27 +CYDEV_UCFG_B0_P6_U0_CFG27 EQU 0x40010c5b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG28 +CYDEV_UCFG_B0_P6_U0_CFG28 EQU 0x40010c5c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG29 +CYDEV_UCFG_B0_P6_U0_CFG29 EQU 0x40010c5d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG30 +CYDEV_UCFG_B0_P6_U0_CFG30 EQU 0x40010c5e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG31 +CYDEV_UCFG_B0_P6_U0_CFG31 EQU 0x40010c5f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG0 +CYDEV_UCFG_B0_P6_U0_DCFG0 EQU 0x40010c60 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG1 +CYDEV_UCFG_B0_P6_U0_DCFG1 EQU 0x40010c62 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG2 +CYDEV_UCFG_B0_P6_U0_DCFG2 EQU 0x40010c64 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG3 +CYDEV_UCFG_B0_P6_U0_DCFG3 EQU 0x40010c66 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG4 +CYDEV_UCFG_B0_P6_U0_DCFG4 EQU 0x40010c68 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG5 +CYDEV_UCFG_B0_P6_U0_DCFG5 EQU 0x40010c6a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG6 +CYDEV_UCFG_B0_P6_U0_DCFG6 EQU 0x40010c6c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG7 +CYDEV_UCFG_B0_P6_U0_DCFG7 EQU 0x40010c6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_BASE +CYDEV_UCFG_B0_P6_U1_BASE EQU 0x40010c80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_SIZE +CYDEV_UCFG_B0_P6_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT0 +CYDEV_UCFG_B0_P6_U1_PLD_IT0 EQU 0x40010c80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT1 +CYDEV_UCFG_B0_P6_U1_PLD_IT1 EQU 0x40010c84 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT2 +CYDEV_UCFG_B0_P6_U1_PLD_IT2 EQU 0x40010c88 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT3 +CYDEV_UCFG_B0_P6_U1_PLD_IT3 EQU 0x40010c8c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT4 +CYDEV_UCFG_B0_P6_U1_PLD_IT4 EQU 0x40010c90 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT5 +CYDEV_UCFG_B0_P6_U1_PLD_IT5 EQU 0x40010c94 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT6 +CYDEV_UCFG_B0_P6_U1_PLD_IT6 EQU 0x40010c98 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT7 +CYDEV_UCFG_B0_P6_U1_PLD_IT7 EQU 0x40010c9c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT8 +CYDEV_UCFG_B0_P6_U1_PLD_IT8 EQU 0x40010ca0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT9 +CYDEV_UCFG_B0_P6_U1_PLD_IT9 EQU 0x40010ca4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT10 +CYDEV_UCFG_B0_P6_U1_PLD_IT10 EQU 0x40010ca8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT11 +CYDEV_UCFG_B0_P6_U1_PLD_IT11 EQU 0x40010cac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_ORT0 +CYDEV_UCFG_B0_P6_U1_PLD_ORT0 EQU 0x40010cb0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_ORT1 +CYDEV_UCFG_B0_P6_U1_PLD_ORT1 EQU 0x40010cb2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_ORT2 +CYDEV_UCFG_B0_P6_U1_PLD_ORT2 EQU 0x40010cb4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_ORT3 +CYDEV_UCFG_B0_P6_U1_PLD_ORT3 EQU 0x40010cb6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST EQU 0x40010cb8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB EQU 0x40010cba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET EQU 0x40010cbc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS EQU 0x40010cbe + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG0 +CYDEV_UCFG_B0_P6_U1_CFG0 EQU 0x40010cc0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG1 +CYDEV_UCFG_B0_P6_U1_CFG1 EQU 0x40010cc1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG2 +CYDEV_UCFG_B0_P6_U1_CFG2 EQU 0x40010cc2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG3 +CYDEV_UCFG_B0_P6_U1_CFG3 EQU 0x40010cc3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG4 +CYDEV_UCFG_B0_P6_U1_CFG4 EQU 0x40010cc4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG5 +CYDEV_UCFG_B0_P6_U1_CFG5 EQU 0x40010cc5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG6 +CYDEV_UCFG_B0_P6_U1_CFG6 EQU 0x40010cc6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG7 +CYDEV_UCFG_B0_P6_U1_CFG7 EQU 0x40010cc7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG8 +CYDEV_UCFG_B0_P6_U1_CFG8 EQU 0x40010cc8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG9 +CYDEV_UCFG_B0_P6_U1_CFG9 EQU 0x40010cc9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG10 +CYDEV_UCFG_B0_P6_U1_CFG10 EQU 0x40010cca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG11 +CYDEV_UCFG_B0_P6_U1_CFG11 EQU 0x40010ccb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG12 +CYDEV_UCFG_B0_P6_U1_CFG12 EQU 0x40010ccc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG13 +CYDEV_UCFG_B0_P6_U1_CFG13 EQU 0x40010ccd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG14 +CYDEV_UCFG_B0_P6_U1_CFG14 EQU 0x40010cce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG15 +CYDEV_UCFG_B0_P6_U1_CFG15 EQU 0x40010ccf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG16 +CYDEV_UCFG_B0_P6_U1_CFG16 EQU 0x40010cd0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG17 +CYDEV_UCFG_B0_P6_U1_CFG17 EQU 0x40010cd1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG18 +CYDEV_UCFG_B0_P6_U1_CFG18 EQU 0x40010cd2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG19 +CYDEV_UCFG_B0_P6_U1_CFG19 EQU 0x40010cd3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG20 +CYDEV_UCFG_B0_P6_U1_CFG20 EQU 0x40010cd4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG21 +CYDEV_UCFG_B0_P6_U1_CFG21 EQU 0x40010cd5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG22 +CYDEV_UCFG_B0_P6_U1_CFG22 EQU 0x40010cd6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG23 +CYDEV_UCFG_B0_P6_U1_CFG23 EQU 0x40010cd7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG24 +CYDEV_UCFG_B0_P6_U1_CFG24 EQU 0x40010cd8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG25 +CYDEV_UCFG_B0_P6_U1_CFG25 EQU 0x40010cd9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG26 +CYDEV_UCFG_B0_P6_U1_CFG26 EQU 0x40010cda + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG27 +CYDEV_UCFG_B0_P6_U1_CFG27 EQU 0x40010cdb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG28 +CYDEV_UCFG_B0_P6_U1_CFG28 EQU 0x40010cdc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG29 +CYDEV_UCFG_B0_P6_U1_CFG29 EQU 0x40010cdd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG30 +CYDEV_UCFG_B0_P6_U1_CFG30 EQU 0x40010cde + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG31 +CYDEV_UCFG_B0_P6_U1_CFG31 EQU 0x40010cdf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG0 +CYDEV_UCFG_B0_P6_U1_DCFG0 EQU 0x40010ce0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG1 +CYDEV_UCFG_B0_P6_U1_DCFG1 EQU 0x40010ce2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG2 +CYDEV_UCFG_B0_P6_U1_DCFG2 EQU 0x40010ce4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG3 +CYDEV_UCFG_B0_P6_U1_DCFG3 EQU 0x40010ce6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG4 +CYDEV_UCFG_B0_P6_U1_DCFG4 EQU 0x40010ce8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG5 +CYDEV_UCFG_B0_P6_U1_DCFG5 EQU 0x40010cea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG6 +CYDEV_UCFG_B0_P6_U1_DCFG6 EQU 0x40010cec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG7 +CYDEV_UCFG_B0_P6_U1_DCFG7 EQU 0x40010cee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_ROUTE_BASE +CYDEV_UCFG_B0_P6_ROUTE_BASE EQU 0x40010d00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_ROUTE_SIZE +CYDEV_UCFG_B0_P6_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_BASE +CYDEV_UCFG_B0_P7_BASE EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_SIZE +CYDEV_UCFG_B0_P7_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_BASE +CYDEV_UCFG_B0_P7_U0_BASE EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_SIZE +CYDEV_UCFG_B0_P7_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT0 +CYDEV_UCFG_B0_P7_U0_PLD_IT0 EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT1 +CYDEV_UCFG_B0_P7_U0_PLD_IT1 EQU 0x40010e04 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT2 +CYDEV_UCFG_B0_P7_U0_PLD_IT2 EQU 0x40010e08 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT3 +CYDEV_UCFG_B0_P7_U0_PLD_IT3 EQU 0x40010e0c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT4 +CYDEV_UCFG_B0_P7_U0_PLD_IT4 EQU 0x40010e10 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT5 +CYDEV_UCFG_B0_P7_U0_PLD_IT5 EQU 0x40010e14 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT6 +CYDEV_UCFG_B0_P7_U0_PLD_IT6 EQU 0x40010e18 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT7 +CYDEV_UCFG_B0_P7_U0_PLD_IT7 EQU 0x40010e1c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT8 +CYDEV_UCFG_B0_P7_U0_PLD_IT8 EQU 0x40010e20 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT9 +CYDEV_UCFG_B0_P7_U0_PLD_IT9 EQU 0x40010e24 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT10 +CYDEV_UCFG_B0_P7_U0_PLD_IT10 EQU 0x40010e28 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT11 +CYDEV_UCFG_B0_P7_U0_PLD_IT11 EQU 0x40010e2c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_ORT0 +CYDEV_UCFG_B0_P7_U0_PLD_ORT0 EQU 0x40010e30 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_ORT1 +CYDEV_UCFG_B0_P7_U0_PLD_ORT1 EQU 0x40010e32 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_ORT2 +CYDEV_UCFG_B0_P7_U0_PLD_ORT2 EQU 0x40010e34 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_ORT3 +CYDEV_UCFG_B0_P7_U0_PLD_ORT3 EQU 0x40010e36 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST EQU 0x40010e38 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB EQU 0x40010e3a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET EQU 0x40010e3c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS EQU 0x40010e3e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG0 +CYDEV_UCFG_B0_P7_U0_CFG0 EQU 0x40010e40 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG1 +CYDEV_UCFG_B0_P7_U0_CFG1 EQU 0x40010e41 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG2 +CYDEV_UCFG_B0_P7_U0_CFG2 EQU 0x40010e42 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG3 +CYDEV_UCFG_B0_P7_U0_CFG3 EQU 0x40010e43 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG4 +CYDEV_UCFG_B0_P7_U0_CFG4 EQU 0x40010e44 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG5 +CYDEV_UCFG_B0_P7_U0_CFG5 EQU 0x40010e45 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG6 +CYDEV_UCFG_B0_P7_U0_CFG6 EQU 0x40010e46 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG7 +CYDEV_UCFG_B0_P7_U0_CFG7 EQU 0x40010e47 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG8 +CYDEV_UCFG_B0_P7_U0_CFG8 EQU 0x40010e48 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG9 +CYDEV_UCFG_B0_P7_U0_CFG9 EQU 0x40010e49 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG10 +CYDEV_UCFG_B0_P7_U0_CFG10 EQU 0x40010e4a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG11 +CYDEV_UCFG_B0_P7_U0_CFG11 EQU 0x40010e4b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG12 +CYDEV_UCFG_B0_P7_U0_CFG12 EQU 0x40010e4c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG13 +CYDEV_UCFG_B0_P7_U0_CFG13 EQU 0x40010e4d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG14 +CYDEV_UCFG_B0_P7_U0_CFG14 EQU 0x40010e4e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG15 +CYDEV_UCFG_B0_P7_U0_CFG15 EQU 0x40010e4f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG16 +CYDEV_UCFG_B0_P7_U0_CFG16 EQU 0x40010e50 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG17 +CYDEV_UCFG_B0_P7_U0_CFG17 EQU 0x40010e51 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG18 +CYDEV_UCFG_B0_P7_U0_CFG18 EQU 0x40010e52 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG19 +CYDEV_UCFG_B0_P7_U0_CFG19 EQU 0x40010e53 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG20 +CYDEV_UCFG_B0_P7_U0_CFG20 EQU 0x40010e54 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG21 +CYDEV_UCFG_B0_P7_U0_CFG21 EQU 0x40010e55 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG22 +CYDEV_UCFG_B0_P7_U0_CFG22 EQU 0x40010e56 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG23 +CYDEV_UCFG_B0_P7_U0_CFG23 EQU 0x40010e57 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG24 +CYDEV_UCFG_B0_P7_U0_CFG24 EQU 0x40010e58 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG25 +CYDEV_UCFG_B0_P7_U0_CFG25 EQU 0x40010e59 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG26 +CYDEV_UCFG_B0_P7_U0_CFG26 EQU 0x40010e5a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG27 +CYDEV_UCFG_B0_P7_U0_CFG27 EQU 0x40010e5b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG28 +CYDEV_UCFG_B0_P7_U0_CFG28 EQU 0x40010e5c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG29 +CYDEV_UCFG_B0_P7_U0_CFG29 EQU 0x40010e5d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG30 +CYDEV_UCFG_B0_P7_U0_CFG30 EQU 0x40010e5e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG31 +CYDEV_UCFG_B0_P7_U0_CFG31 EQU 0x40010e5f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG0 +CYDEV_UCFG_B0_P7_U0_DCFG0 EQU 0x40010e60 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG1 +CYDEV_UCFG_B0_P7_U0_DCFG1 EQU 0x40010e62 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG2 +CYDEV_UCFG_B0_P7_U0_DCFG2 EQU 0x40010e64 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG3 +CYDEV_UCFG_B0_P7_U0_DCFG3 EQU 0x40010e66 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG4 +CYDEV_UCFG_B0_P7_U0_DCFG4 EQU 0x40010e68 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG5 +CYDEV_UCFG_B0_P7_U0_DCFG5 EQU 0x40010e6a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG6 +CYDEV_UCFG_B0_P7_U0_DCFG6 EQU 0x40010e6c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG7 +CYDEV_UCFG_B0_P7_U0_DCFG7 EQU 0x40010e6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_BASE +CYDEV_UCFG_B0_P7_U1_BASE EQU 0x40010e80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_SIZE +CYDEV_UCFG_B0_P7_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT0 +CYDEV_UCFG_B0_P7_U1_PLD_IT0 EQU 0x40010e80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT1 +CYDEV_UCFG_B0_P7_U1_PLD_IT1 EQU 0x40010e84 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT2 +CYDEV_UCFG_B0_P7_U1_PLD_IT2 EQU 0x40010e88 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT3 +CYDEV_UCFG_B0_P7_U1_PLD_IT3 EQU 0x40010e8c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT4 +CYDEV_UCFG_B0_P7_U1_PLD_IT4 EQU 0x40010e90 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT5 +CYDEV_UCFG_B0_P7_U1_PLD_IT5 EQU 0x40010e94 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT6 +CYDEV_UCFG_B0_P7_U1_PLD_IT6 EQU 0x40010e98 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT7 +CYDEV_UCFG_B0_P7_U1_PLD_IT7 EQU 0x40010e9c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT8 +CYDEV_UCFG_B0_P7_U1_PLD_IT8 EQU 0x40010ea0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT9 +CYDEV_UCFG_B0_P7_U1_PLD_IT9 EQU 0x40010ea4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT10 +CYDEV_UCFG_B0_P7_U1_PLD_IT10 EQU 0x40010ea8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT11 +CYDEV_UCFG_B0_P7_U1_PLD_IT11 EQU 0x40010eac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_ORT0 +CYDEV_UCFG_B0_P7_U1_PLD_ORT0 EQU 0x40010eb0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_ORT1 +CYDEV_UCFG_B0_P7_U1_PLD_ORT1 EQU 0x40010eb2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_ORT2 +CYDEV_UCFG_B0_P7_U1_PLD_ORT2 EQU 0x40010eb4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_ORT3 +CYDEV_UCFG_B0_P7_U1_PLD_ORT3 EQU 0x40010eb6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST EQU 0x40010eb8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB EQU 0x40010eba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET EQU 0x40010ebc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS EQU 0x40010ebe + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG0 +CYDEV_UCFG_B0_P7_U1_CFG0 EQU 0x40010ec0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG1 +CYDEV_UCFG_B0_P7_U1_CFG1 EQU 0x40010ec1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG2 +CYDEV_UCFG_B0_P7_U1_CFG2 EQU 0x40010ec2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG3 +CYDEV_UCFG_B0_P7_U1_CFG3 EQU 0x40010ec3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG4 +CYDEV_UCFG_B0_P7_U1_CFG4 EQU 0x40010ec4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG5 +CYDEV_UCFG_B0_P7_U1_CFG5 EQU 0x40010ec5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG6 +CYDEV_UCFG_B0_P7_U1_CFG6 EQU 0x40010ec6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG7 +CYDEV_UCFG_B0_P7_U1_CFG7 EQU 0x40010ec7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG8 +CYDEV_UCFG_B0_P7_U1_CFG8 EQU 0x40010ec8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG9 +CYDEV_UCFG_B0_P7_U1_CFG9 EQU 0x40010ec9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG10 +CYDEV_UCFG_B0_P7_U1_CFG10 EQU 0x40010eca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG11 +CYDEV_UCFG_B0_P7_U1_CFG11 EQU 0x40010ecb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG12 +CYDEV_UCFG_B0_P7_U1_CFG12 EQU 0x40010ecc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG13 +CYDEV_UCFG_B0_P7_U1_CFG13 EQU 0x40010ecd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG14 +CYDEV_UCFG_B0_P7_U1_CFG14 EQU 0x40010ece + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG15 +CYDEV_UCFG_B0_P7_U1_CFG15 EQU 0x40010ecf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG16 +CYDEV_UCFG_B0_P7_U1_CFG16 EQU 0x40010ed0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG17 +CYDEV_UCFG_B0_P7_U1_CFG17 EQU 0x40010ed1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG18 +CYDEV_UCFG_B0_P7_U1_CFG18 EQU 0x40010ed2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG19 +CYDEV_UCFG_B0_P7_U1_CFG19 EQU 0x40010ed3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG20 +CYDEV_UCFG_B0_P7_U1_CFG20 EQU 0x40010ed4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG21 +CYDEV_UCFG_B0_P7_U1_CFG21 EQU 0x40010ed5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG22 +CYDEV_UCFG_B0_P7_U1_CFG22 EQU 0x40010ed6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG23 +CYDEV_UCFG_B0_P7_U1_CFG23 EQU 0x40010ed7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG24 +CYDEV_UCFG_B0_P7_U1_CFG24 EQU 0x40010ed8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG25 +CYDEV_UCFG_B0_P7_U1_CFG25 EQU 0x40010ed9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG26 +CYDEV_UCFG_B0_P7_U1_CFG26 EQU 0x40010eda + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG27 +CYDEV_UCFG_B0_P7_U1_CFG27 EQU 0x40010edb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG28 +CYDEV_UCFG_B0_P7_U1_CFG28 EQU 0x40010edc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG29 +CYDEV_UCFG_B0_P7_U1_CFG29 EQU 0x40010edd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG30 +CYDEV_UCFG_B0_P7_U1_CFG30 EQU 0x40010ede + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG31 +CYDEV_UCFG_B0_P7_U1_CFG31 EQU 0x40010edf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG0 +CYDEV_UCFG_B0_P7_U1_DCFG0 EQU 0x40010ee0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG1 +CYDEV_UCFG_B0_P7_U1_DCFG1 EQU 0x40010ee2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG2 +CYDEV_UCFG_B0_P7_U1_DCFG2 EQU 0x40010ee4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG3 +CYDEV_UCFG_B0_P7_U1_DCFG3 EQU 0x40010ee6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG4 +CYDEV_UCFG_B0_P7_U1_DCFG4 EQU 0x40010ee8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG5 +CYDEV_UCFG_B0_P7_U1_DCFG5 EQU 0x40010eea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG6 +CYDEV_UCFG_B0_P7_U1_DCFG6 EQU 0x40010eec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG7 +CYDEV_UCFG_B0_P7_U1_DCFG7 EQU 0x40010eee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_ROUTE_BASE +CYDEV_UCFG_B0_P7_ROUTE_BASE EQU 0x40010f00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_ROUTE_SIZE +CYDEV_UCFG_B0_P7_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_BASE +CYDEV_UCFG_B1_BASE EQU 0x40011000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_SIZE +CYDEV_UCFG_B1_SIZE EQU 0x00000fef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_BASE +CYDEV_UCFG_B1_P2_BASE EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_SIZE +CYDEV_UCFG_B1_P2_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_BASE +CYDEV_UCFG_B1_P2_U0_BASE EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_SIZE +CYDEV_UCFG_B1_P2_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT0 +CYDEV_UCFG_B1_P2_U0_PLD_IT0 EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT1 +CYDEV_UCFG_B1_P2_U0_PLD_IT1 EQU 0x40011404 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT2 +CYDEV_UCFG_B1_P2_U0_PLD_IT2 EQU 0x40011408 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT3 +CYDEV_UCFG_B1_P2_U0_PLD_IT3 EQU 0x4001140c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT4 +CYDEV_UCFG_B1_P2_U0_PLD_IT4 EQU 0x40011410 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT5 +CYDEV_UCFG_B1_P2_U0_PLD_IT5 EQU 0x40011414 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT6 +CYDEV_UCFG_B1_P2_U0_PLD_IT6 EQU 0x40011418 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT7 +CYDEV_UCFG_B1_P2_U0_PLD_IT7 EQU 0x4001141c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT8 +CYDEV_UCFG_B1_P2_U0_PLD_IT8 EQU 0x40011420 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT9 +CYDEV_UCFG_B1_P2_U0_PLD_IT9 EQU 0x40011424 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT10 +CYDEV_UCFG_B1_P2_U0_PLD_IT10 EQU 0x40011428 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT11 +CYDEV_UCFG_B1_P2_U0_PLD_IT11 EQU 0x4001142c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_ORT0 +CYDEV_UCFG_B1_P2_U0_PLD_ORT0 EQU 0x40011430 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_ORT1 +CYDEV_UCFG_B1_P2_U0_PLD_ORT1 EQU 0x40011432 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_ORT2 +CYDEV_UCFG_B1_P2_U0_PLD_ORT2 EQU 0x40011434 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_ORT3 +CYDEV_UCFG_B1_P2_U0_PLD_ORT3 EQU 0x40011436 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST EQU 0x40011438 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB +CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB EQU 0x4001143a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET EQU 0x4001143c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS +CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS EQU 0x4001143e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG0 +CYDEV_UCFG_B1_P2_U0_CFG0 EQU 0x40011440 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG1 +CYDEV_UCFG_B1_P2_U0_CFG1 EQU 0x40011441 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG2 +CYDEV_UCFG_B1_P2_U0_CFG2 EQU 0x40011442 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG3 +CYDEV_UCFG_B1_P2_U0_CFG3 EQU 0x40011443 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG4 +CYDEV_UCFG_B1_P2_U0_CFG4 EQU 0x40011444 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG5 +CYDEV_UCFG_B1_P2_U0_CFG5 EQU 0x40011445 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG6 +CYDEV_UCFG_B1_P2_U0_CFG6 EQU 0x40011446 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG7 +CYDEV_UCFG_B1_P2_U0_CFG7 EQU 0x40011447 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG8 +CYDEV_UCFG_B1_P2_U0_CFG8 EQU 0x40011448 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG9 +CYDEV_UCFG_B1_P2_U0_CFG9 EQU 0x40011449 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG10 +CYDEV_UCFG_B1_P2_U0_CFG10 EQU 0x4001144a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG11 +CYDEV_UCFG_B1_P2_U0_CFG11 EQU 0x4001144b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG12 +CYDEV_UCFG_B1_P2_U0_CFG12 EQU 0x4001144c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG13 +CYDEV_UCFG_B1_P2_U0_CFG13 EQU 0x4001144d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG14 +CYDEV_UCFG_B1_P2_U0_CFG14 EQU 0x4001144e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG15 +CYDEV_UCFG_B1_P2_U0_CFG15 EQU 0x4001144f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG16 +CYDEV_UCFG_B1_P2_U0_CFG16 EQU 0x40011450 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG17 +CYDEV_UCFG_B1_P2_U0_CFG17 EQU 0x40011451 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG18 +CYDEV_UCFG_B1_P2_U0_CFG18 EQU 0x40011452 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG19 +CYDEV_UCFG_B1_P2_U0_CFG19 EQU 0x40011453 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG20 +CYDEV_UCFG_B1_P2_U0_CFG20 EQU 0x40011454 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG21 +CYDEV_UCFG_B1_P2_U0_CFG21 EQU 0x40011455 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG22 +CYDEV_UCFG_B1_P2_U0_CFG22 EQU 0x40011456 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG23 +CYDEV_UCFG_B1_P2_U0_CFG23 EQU 0x40011457 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG24 +CYDEV_UCFG_B1_P2_U0_CFG24 EQU 0x40011458 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG25 +CYDEV_UCFG_B1_P2_U0_CFG25 EQU 0x40011459 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG26 +CYDEV_UCFG_B1_P2_U0_CFG26 EQU 0x4001145a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG27 +CYDEV_UCFG_B1_P2_U0_CFG27 EQU 0x4001145b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG28 +CYDEV_UCFG_B1_P2_U0_CFG28 EQU 0x4001145c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG29 +CYDEV_UCFG_B1_P2_U0_CFG29 EQU 0x4001145d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG30 +CYDEV_UCFG_B1_P2_U0_CFG30 EQU 0x4001145e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG31 +CYDEV_UCFG_B1_P2_U0_CFG31 EQU 0x4001145f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG0 +CYDEV_UCFG_B1_P2_U0_DCFG0 EQU 0x40011460 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG1 +CYDEV_UCFG_B1_P2_U0_DCFG1 EQU 0x40011462 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG2 +CYDEV_UCFG_B1_P2_U0_DCFG2 EQU 0x40011464 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG3 +CYDEV_UCFG_B1_P2_U0_DCFG3 EQU 0x40011466 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG4 +CYDEV_UCFG_B1_P2_U0_DCFG4 EQU 0x40011468 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG5 +CYDEV_UCFG_B1_P2_U0_DCFG5 EQU 0x4001146a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG6 +CYDEV_UCFG_B1_P2_U0_DCFG6 EQU 0x4001146c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG7 +CYDEV_UCFG_B1_P2_U0_DCFG7 EQU 0x4001146e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_BASE +CYDEV_UCFG_B1_P2_U1_BASE EQU 0x40011480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_SIZE +CYDEV_UCFG_B1_P2_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT0 +CYDEV_UCFG_B1_P2_U1_PLD_IT0 EQU 0x40011480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT1 +CYDEV_UCFG_B1_P2_U1_PLD_IT1 EQU 0x40011484 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT2 +CYDEV_UCFG_B1_P2_U1_PLD_IT2 EQU 0x40011488 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT3 +CYDEV_UCFG_B1_P2_U1_PLD_IT3 EQU 0x4001148c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT4 +CYDEV_UCFG_B1_P2_U1_PLD_IT4 EQU 0x40011490 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT5 +CYDEV_UCFG_B1_P2_U1_PLD_IT5 EQU 0x40011494 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT6 +CYDEV_UCFG_B1_P2_U1_PLD_IT6 EQU 0x40011498 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT7 +CYDEV_UCFG_B1_P2_U1_PLD_IT7 EQU 0x4001149c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT8 +CYDEV_UCFG_B1_P2_U1_PLD_IT8 EQU 0x400114a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT9 +CYDEV_UCFG_B1_P2_U1_PLD_IT9 EQU 0x400114a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT10 +CYDEV_UCFG_B1_P2_U1_PLD_IT10 EQU 0x400114a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT11 +CYDEV_UCFG_B1_P2_U1_PLD_IT11 EQU 0x400114ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_ORT0 +CYDEV_UCFG_B1_P2_U1_PLD_ORT0 EQU 0x400114b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_ORT1 +CYDEV_UCFG_B1_P2_U1_PLD_ORT1 EQU 0x400114b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_ORT2 +CYDEV_UCFG_B1_P2_U1_PLD_ORT2 EQU 0x400114b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_ORT3 +CYDEV_UCFG_B1_P2_U1_PLD_ORT3 EQU 0x400114b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST EQU 0x400114b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB +CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB EQU 0x400114ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET EQU 0x400114bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS +CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS EQU 0x400114be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG0 +CYDEV_UCFG_B1_P2_U1_CFG0 EQU 0x400114c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG1 +CYDEV_UCFG_B1_P2_U1_CFG1 EQU 0x400114c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG2 +CYDEV_UCFG_B1_P2_U1_CFG2 EQU 0x400114c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG3 +CYDEV_UCFG_B1_P2_U1_CFG3 EQU 0x400114c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG4 +CYDEV_UCFG_B1_P2_U1_CFG4 EQU 0x400114c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG5 +CYDEV_UCFG_B1_P2_U1_CFG5 EQU 0x400114c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG6 +CYDEV_UCFG_B1_P2_U1_CFG6 EQU 0x400114c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG7 +CYDEV_UCFG_B1_P2_U1_CFG7 EQU 0x400114c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG8 +CYDEV_UCFG_B1_P2_U1_CFG8 EQU 0x400114c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG9 +CYDEV_UCFG_B1_P2_U1_CFG9 EQU 0x400114c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG10 +CYDEV_UCFG_B1_P2_U1_CFG10 EQU 0x400114ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG11 +CYDEV_UCFG_B1_P2_U1_CFG11 EQU 0x400114cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG12 +CYDEV_UCFG_B1_P2_U1_CFG12 EQU 0x400114cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG13 +CYDEV_UCFG_B1_P2_U1_CFG13 EQU 0x400114cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG14 +CYDEV_UCFG_B1_P2_U1_CFG14 EQU 0x400114ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG15 +CYDEV_UCFG_B1_P2_U1_CFG15 EQU 0x400114cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG16 +CYDEV_UCFG_B1_P2_U1_CFG16 EQU 0x400114d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG17 +CYDEV_UCFG_B1_P2_U1_CFG17 EQU 0x400114d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG18 +CYDEV_UCFG_B1_P2_U1_CFG18 EQU 0x400114d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG19 +CYDEV_UCFG_B1_P2_U1_CFG19 EQU 0x400114d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG20 +CYDEV_UCFG_B1_P2_U1_CFG20 EQU 0x400114d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG21 +CYDEV_UCFG_B1_P2_U1_CFG21 EQU 0x400114d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG22 +CYDEV_UCFG_B1_P2_U1_CFG22 EQU 0x400114d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG23 +CYDEV_UCFG_B1_P2_U1_CFG23 EQU 0x400114d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG24 +CYDEV_UCFG_B1_P2_U1_CFG24 EQU 0x400114d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG25 +CYDEV_UCFG_B1_P2_U1_CFG25 EQU 0x400114d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG26 +CYDEV_UCFG_B1_P2_U1_CFG26 EQU 0x400114da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG27 +CYDEV_UCFG_B1_P2_U1_CFG27 EQU 0x400114db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG28 +CYDEV_UCFG_B1_P2_U1_CFG28 EQU 0x400114dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG29 +CYDEV_UCFG_B1_P2_U1_CFG29 EQU 0x400114dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG30 +CYDEV_UCFG_B1_P2_U1_CFG30 EQU 0x400114de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG31 +CYDEV_UCFG_B1_P2_U1_CFG31 EQU 0x400114df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG0 +CYDEV_UCFG_B1_P2_U1_DCFG0 EQU 0x400114e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG1 +CYDEV_UCFG_B1_P2_U1_DCFG1 EQU 0x400114e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG2 +CYDEV_UCFG_B1_P2_U1_DCFG2 EQU 0x400114e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG3 +CYDEV_UCFG_B1_P2_U1_DCFG3 EQU 0x400114e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG4 +CYDEV_UCFG_B1_P2_U1_DCFG4 EQU 0x400114e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG5 +CYDEV_UCFG_B1_P2_U1_DCFG5 EQU 0x400114ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG6 +CYDEV_UCFG_B1_P2_U1_DCFG6 EQU 0x400114ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG7 +CYDEV_UCFG_B1_P2_U1_DCFG7 EQU 0x400114ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_ROUTE_BASE +CYDEV_UCFG_B1_P2_ROUTE_BASE EQU 0x40011500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_ROUTE_SIZE +CYDEV_UCFG_B1_P2_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_BASE +CYDEV_UCFG_B1_P3_BASE EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_SIZE +CYDEV_UCFG_B1_P3_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_BASE +CYDEV_UCFG_B1_P3_U0_BASE EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_SIZE +CYDEV_UCFG_B1_P3_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT0 +CYDEV_UCFG_B1_P3_U0_PLD_IT0 EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT1 +CYDEV_UCFG_B1_P3_U0_PLD_IT1 EQU 0x40011604 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT2 +CYDEV_UCFG_B1_P3_U0_PLD_IT2 EQU 0x40011608 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT3 +CYDEV_UCFG_B1_P3_U0_PLD_IT3 EQU 0x4001160c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT4 +CYDEV_UCFG_B1_P3_U0_PLD_IT4 EQU 0x40011610 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT5 +CYDEV_UCFG_B1_P3_U0_PLD_IT5 EQU 0x40011614 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT6 +CYDEV_UCFG_B1_P3_U0_PLD_IT6 EQU 0x40011618 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT7 +CYDEV_UCFG_B1_P3_U0_PLD_IT7 EQU 0x4001161c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT8 +CYDEV_UCFG_B1_P3_U0_PLD_IT8 EQU 0x40011620 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT9 +CYDEV_UCFG_B1_P3_U0_PLD_IT9 EQU 0x40011624 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT10 +CYDEV_UCFG_B1_P3_U0_PLD_IT10 EQU 0x40011628 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT11 +CYDEV_UCFG_B1_P3_U0_PLD_IT11 EQU 0x4001162c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_ORT0 +CYDEV_UCFG_B1_P3_U0_PLD_ORT0 EQU 0x40011630 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_ORT1 +CYDEV_UCFG_B1_P3_U0_PLD_ORT1 EQU 0x40011632 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_ORT2 +CYDEV_UCFG_B1_P3_U0_PLD_ORT2 EQU 0x40011634 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_ORT3 +CYDEV_UCFG_B1_P3_U0_PLD_ORT3 EQU 0x40011636 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST EQU 0x40011638 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB +CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB EQU 0x4001163a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET EQU 0x4001163c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS +CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS EQU 0x4001163e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG0 +CYDEV_UCFG_B1_P3_U0_CFG0 EQU 0x40011640 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG1 +CYDEV_UCFG_B1_P3_U0_CFG1 EQU 0x40011641 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG2 +CYDEV_UCFG_B1_P3_U0_CFG2 EQU 0x40011642 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG3 +CYDEV_UCFG_B1_P3_U0_CFG3 EQU 0x40011643 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG4 +CYDEV_UCFG_B1_P3_U0_CFG4 EQU 0x40011644 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG5 +CYDEV_UCFG_B1_P3_U0_CFG5 EQU 0x40011645 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG6 +CYDEV_UCFG_B1_P3_U0_CFG6 EQU 0x40011646 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG7 +CYDEV_UCFG_B1_P3_U0_CFG7 EQU 0x40011647 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG8 +CYDEV_UCFG_B1_P3_U0_CFG8 EQU 0x40011648 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG9 +CYDEV_UCFG_B1_P3_U0_CFG9 EQU 0x40011649 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG10 +CYDEV_UCFG_B1_P3_U0_CFG10 EQU 0x4001164a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG11 +CYDEV_UCFG_B1_P3_U0_CFG11 EQU 0x4001164b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG12 +CYDEV_UCFG_B1_P3_U0_CFG12 EQU 0x4001164c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG13 +CYDEV_UCFG_B1_P3_U0_CFG13 EQU 0x4001164d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG14 +CYDEV_UCFG_B1_P3_U0_CFG14 EQU 0x4001164e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG15 +CYDEV_UCFG_B1_P3_U0_CFG15 EQU 0x4001164f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG16 +CYDEV_UCFG_B1_P3_U0_CFG16 EQU 0x40011650 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG17 +CYDEV_UCFG_B1_P3_U0_CFG17 EQU 0x40011651 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG18 +CYDEV_UCFG_B1_P3_U0_CFG18 EQU 0x40011652 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG19 +CYDEV_UCFG_B1_P3_U0_CFG19 EQU 0x40011653 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG20 +CYDEV_UCFG_B1_P3_U0_CFG20 EQU 0x40011654 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG21 +CYDEV_UCFG_B1_P3_U0_CFG21 EQU 0x40011655 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG22 +CYDEV_UCFG_B1_P3_U0_CFG22 EQU 0x40011656 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG23 +CYDEV_UCFG_B1_P3_U0_CFG23 EQU 0x40011657 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG24 +CYDEV_UCFG_B1_P3_U0_CFG24 EQU 0x40011658 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG25 +CYDEV_UCFG_B1_P3_U0_CFG25 EQU 0x40011659 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG26 +CYDEV_UCFG_B1_P3_U0_CFG26 EQU 0x4001165a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG27 +CYDEV_UCFG_B1_P3_U0_CFG27 EQU 0x4001165b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG28 +CYDEV_UCFG_B1_P3_U0_CFG28 EQU 0x4001165c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG29 +CYDEV_UCFG_B1_P3_U0_CFG29 EQU 0x4001165d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG30 +CYDEV_UCFG_B1_P3_U0_CFG30 EQU 0x4001165e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG31 +CYDEV_UCFG_B1_P3_U0_CFG31 EQU 0x4001165f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG0 +CYDEV_UCFG_B1_P3_U0_DCFG0 EQU 0x40011660 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG1 +CYDEV_UCFG_B1_P3_U0_DCFG1 EQU 0x40011662 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG2 +CYDEV_UCFG_B1_P3_U0_DCFG2 EQU 0x40011664 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG3 +CYDEV_UCFG_B1_P3_U0_DCFG3 EQU 0x40011666 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG4 +CYDEV_UCFG_B1_P3_U0_DCFG4 EQU 0x40011668 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG5 +CYDEV_UCFG_B1_P3_U0_DCFG5 EQU 0x4001166a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG6 +CYDEV_UCFG_B1_P3_U0_DCFG6 EQU 0x4001166c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG7 +CYDEV_UCFG_B1_P3_U0_DCFG7 EQU 0x4001166e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_BASE +CYDEV_UCFG_B1_P3_U1_BASE EQU 0x40011680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_SIZE +CYDEV_UCFG_B1_P3_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT0 +CYDEV_UCFG_B1_P3_U1_PLD_IT0 EQU 0x40011680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT1 +CYDEV_UCFG_B1_P3_U1_PLD_IT1 EQU 0x40011684 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT2 +CYDEV_UCFG_B1_P3_U1_PLD_IT2 EQU 0x40011688 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT3 +CYDEV_UCFG_B1_P3_U1_PLD_IT3 EQU 0x4001168c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT4 +CYDEV_UCFG_B1_P3_U1_PLD_IT4 EQU 0x40011690 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT5 +CYDEV_UCFG_B1_P3_U1_PLD_IT5 EQU 0x40011694 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT6 +CYDEV_UCFG_B1_P3_U1_PLD_IT6 EQU 0x40011698 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT7 +CYDEV_UCFG_B1_P3_U1_PLD_IT7 EQU 0x4001169c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT8 +CYDEV_UCFG_B1_P3_U1_PLD_IT8 EQU 0x400116a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT9 +CYDEV_UCFG_B1_P3_U1_PLD_IT9 EQU 0x400116a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT10 +CYDEV_UCFG_B1_P3_U1_PLD_IT10 EQU 0x400116a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT11 +CYDEV_UCFG_B1_P3_U1_PLD_IT11 EQU 0x400116ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_ORT0 +CYDEV_UCFG_B1_P3_U1_PLD_ORT0 EQU 0x400116b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_ORT1 +CYDEV_UCFG_B1_P3_U1_PLD_ORT1 EQU 0x400116b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_ORT2 +CYDEV_UCFG_B1_P3_U1_PLD_ORT2 EQU 0x400116b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_ORT3 +CYDEV_UCFG_B1_P3_U1_PLD_ORT3 EQU 0x400116b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST EQU 0x400116b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB +CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB EQU 0x400116ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET EQU 0x400116bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS +CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS EQU 0x400116be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG0 +CYDEV_UCFG_B1_P3_U1_CFG0 EQU 0x400116c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG1 +CYDEV_UCFG_B1_P3_U1_CFG1 EQU 0x400116c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG2 +CYDEV_UCFG_B1_P3_U1_CFG2 EQU 0x400116c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG3 +CYDEV_UCFG_B1_P3_U1_CFG3 EQU 0x400116c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG4 +CYDEV_UCFG_B1_P3_U1_CFG4 EQU 0x400116c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG5 +CYDEV_UCFG_B1_P3_U1_CFG5 EQU 0x400116c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG6 +CYDEV_UCFG_B1_P3_U1_CFG6 EQU 0x400116c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG7 +CYDEV_UCFG_B1_P3_U1_CFG7 EQU 0x400116c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG8 +CYDEV_UCFG_B1_P3_U1_CFG8 EQU 0x400116c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG9 +CYDEV_UCFG_B1_P3_U1_CFG9 EQU 0x400116c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG10 +CYDEV_UCFG_B1_P3_U1_CFG10 EQU 0x400116ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG11 +CYDEV_UCFG_B1_P3_U1_CFG11 EQU 0x400116cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG12 +CYDEV_UCFG_B1_P3_U1_CFG12 EQU 0x400116cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG13 +CYDEV_UCFG_B1_P3_U1_CFG13 EQU 0x400116cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG14 +CYDEV_UCFG_B1_P3_U1_CFG14 EQU 0x400116ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG15 +CYDEV_UCFG_B1_P3_U1_CFG15 EQU 0x400116cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG16 +CYDEV_UCFG_B1_P3_U1_CFG16 EQU 0x400116d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG17 +CYDEV_UCFG_B1_P3_U1_CFG17 EQU 0x400116d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG18 +CYDEV_UCFG_B1_P3_U1_CFG18 EQU 0x400116d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG19 +CYDEV_UCFG_B1_P3_U1_CFG19 EQU 0x400116d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG20 +CYDEV_UCFG_B1_P3_U1_CFG20 EQU 0x400116d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG21 +CYDEV_UCFG_B1_P3_U1_CFG21 EQU 0x400116d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG22 +CYDEV_UCFG_B1_P3_U1_CFG22 EQU 0x400116d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG23 +CYDEV_UCFG_B1_P3_U1_CFG23 EQU 0x400116d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG24 +CYDEV_UCFG_B1_P3_U1_CFG24 EQU 0x400116d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG25 +CYDEV_UCFG_B1_P3_U1_CFG25 EQU 0x400116d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG26 +CYDEV_UCFG_B1_P3_U1_CFG26 EQU 0x400116da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG27 +CYDEV_UCFG_B1_P3_U1_CFG27 EQU 0x400116db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG28 +CYDEV_UCFG_B1_P3_U1_CFG28 EQU 0x400116dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG29 +CYDEV_UCFG_B1_P3_U1_CFG29 EQU 0x400116dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG30 +CYDEV_UCFG_B1_P3_U1_CFG30 EQU 0x400116de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG31 +CYDEV_UCFG_B1_P3_U1_CFG31 EQU 0x400116df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG0 +CYDEV_UCFG_B1_P3_U1_DCFG0 EQU 0x400116e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG1 +CYDEV_UCFG_B1_P3_U1_DCFG1 EQU 0x400116e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG2 +CYDEV_UCFG_B1_P3_U1_DCFG2 EQU 0x400116e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG3 +CYDEV_UCFG_B1_P3_U1_DCFG3 EQU 0x400116e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG4 +CYDEV_UCFG_B1_P3_U1_DCFG4 EQU 0x400116e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG5 +CYDEV_UCFG_B1_P3_U1_DCFG5 EQU 0x400116ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG6 +CYDEV_UCFG_B1_P3_U1_DCFG6 EQU 0x400116ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG7 +CYDEV_UCFG_B1_P3_U1_DCFG7 EQU 0x400116ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_ROUTE_BASE +CYDEV_UCFG_B1_P3_ROUTE_BASE EQU 0x40011700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_ROUTE_SIZE +CYDEV_UCFG_B1_P3_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_BASE +CYDEV_UCFG_B1_P4_BASE EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_SIZE +CYDEV_UCFG_B1_P4_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_BASE +CYDEV_UCFG_B1_P4_U0_BASE EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_SIZE +CYDEV_UCFG_B1_P4_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT0 +CYDEV_UCFG_B1_P4_U0_PLD_IT0 EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT1 +CYDEV_UCFG_B1_P4_U0_PLD_IT1 EQU 0x40011804 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT2 +CYDEV_UCFG_B1_P4_U0_PLD_IT2 EQU 0x40011808 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT3 +CYDEV_UCFG_B1_P4_U0_PLD_IT3 EQU 0x4001180c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT4 +CYDEV_UCFG_B1_P4_U0_PLD_IT4 EQU 0x40011810 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT5 +CYDEV_UCFG_B1_P4_U0_PLD_IT5 EQU 0x40011814 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT6 +CYDEV_UCFG_B1_P4_U0_PLD_IT6 EQU 0x40011818 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT7 +CYDEV_UCFG_B1_P4_U0_PLD_IT7 EQU 0x4001181c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT8 +CYDEV_UCFG_B1_P4_U0_PLD_IT8 EQU 0x40011820 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT9 +CYDEV_UCFG_B1_P4_U0_PLD_IT9 EQU 0x40011824 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT10 +CYDEV_UCFG_B1_P4_U0_PLD_IT10 EQU 0x40011828 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT11 +CYDEV_UCFG_B1_P4_U0_PLD_IT11 EQU 0x4001182c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_ORT0 +CYDEV_UCFG_B1_P4_U0_PLD_ORT0 EQU 0x40011830 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_ORT1 +CYDEV_UCFG_B1_P4_U0_PLD_ORT1 EQU 0x40011832 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_ORT2 +CYDEV_UCFG_B1_P4_U0_PLD_ORT2 EQU 0x40011834 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_ORT3 +CYDEV_UCFG_B1_P4_U0_PLD_ORT3 EQU 0x40011836 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST EQU 0x40011838 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB +CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB EQU 0x4001183a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET EQU 0x4001183c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS +CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS EQU 0x4001183e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG0 +CYDEV_UCFG_B1_P4_U0_CFG0 EQU 0x40011840 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG1 +CYDEV_UCFG_B1_P4_U0_CFG1 EQU 0x40011841 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG2 +CYDEV_UCFG_B1_P4_U0_CFG2 EQU 0x40011842 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG3 +CYDEV_UCFG_B1_P4_U0_CFG3 EQU 0x40011843 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG4 +CYDEV_UCFG_B1_P4_U0_CFG4 EQU 0x40011844 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG5 +CYDEV_UCFG_B1_P4_U0_CFG5 EQU 0x40011845 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG6 +CYDEV_UCFG_B1_P4_U0_CFG6 EQU 0x40011846 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG7 +CYDEV_UCFG_B1_P4_U0_CFG7 EQU 0x40011847 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG8 +CYDEV_UCFG_B1_P4_U0_CFG8 EQU 0x40011848 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG9 +CYDEV_UCFG_B1_P4_U0_CFG9 EQU 0x40011849 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG10 +CYDEV_UCFG_B1_P4_U0_CFG10 EQU 0x4001184a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG11 +CYDEV_UCFG_B1_P4_U0_CFG11 EQU 0x4001184b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG12 +CYDEV_UCFG_B1_P4_U0_CFG12 EQU 0x4001184c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG13 +CYDEV_UCFG_B1_P4_U0_CFG13 EQU 0x4001184d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG14 +CYDEV_UCFG_B1_P4_U0_CFG14 EQU 0x4001184e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG15 +CYDEV_UCFG_B1_P4_U0_CFG15 EQU 0x4001184f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG16 +CYDEV_UCFG_B1_P4_U0_CFG16 EQU 0x40011850 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG17 +CYDEV_UCFG_B1_P4_U0_CFG17 EQU 0x40011851 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG18 +CYDEV_UCFG_B1_P4_U0_CFG18 EQU 0x40011852 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG19 +CYDEV_UCFG_B1_P4_U0_CFG19 EQU 0x40011853 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG20 +CYDEV_UCFG_B1_P4_U0_CFG20 EQU 0x40011854 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG21 +CYDEV_UCFG_B1_P4_U0_CFG21 EQU 0x40011855 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG22 +CYDEV_UCFG_B1_P4_U0_CFG22 EQU 0x40011856 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG23 +CYDEV_UCFG_B1_P4_U0_CFG23 EQU 0x40011857 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG24 +CYDEV_UCFG_B1_P4_U0_CFG24 EQU 0x40011858 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG25 +CYDEV_UCFG_B1_P4_U0_CFG25 EQU 0x40011859 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG26 +CYDEV_UCFG_B1_P4_U0_CFG26 EQU 0x4001185a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG27 +CYDEV_UCFG_B1_P4_U0_CFG27 EQU 0x4001185b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG28 +CYDEV_UCFG_B1_P4_U0_CFG28 EQU 0x4001185c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG29 +CYDEV_UCFG_B1_P4_U0_CFG29 EQU 0x4001185d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG30 +CYDEV_UCFG_B1_P4_U0_CFG30 EQU 0x4001185e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG31 +CYDEV_UCFG_B1_P4_U0_CFG31 EQU 0x4001185f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG0 +CYDEV_UCFG_B1_P4_U0_DCFG0 EQU 0x40011860 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG1 +CYDEV_UCFG_B1_P4_U0_DCFG1 EQU 0x40011862 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG2 +CYDEV_UCFG_B1_P4_U0_DCFG2 EQU 0x40011864 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG3 +CYDEV_UCFG_B1_P4_U0_DCFG3 EQU 0x40011866 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG4 +CYDEV_UCFG_B1_P4_U0_DCFG4 EQU 0x40011868 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG5 +CYDEV_UCFG_B1_P4_U0_DCFG5 EQU 0x4001186a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG6 +CYDEV_UCFG_B1_P4_U0_DCFG6 EQU 0x4001186c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG7 +CYDEV_UCFG_B1_P4_U0_DCFG7 EQU 0x4001186e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_BASE +CYDEV_UCFG_B1_P4_U1_BASE EQU 0x40011880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_SIZE +CYDEV_UCFG_B1_P4_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT0 +CYDEV_UCFG_B1_P4_U1_PLD_IT0 EQU 0x40011880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT1 +CYDEV_UCFG_B1_P4_U1_PLD_IT1 EQU 0x40011884 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT2 +CYDEV_UCFG_B1_P4_U1_PLD_IT2 EQU 0x40011888 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT3 +CYDEV_UCFG_B1_P4_U1_PLD_IT3 EQU 0x4001188c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT4 +CYDEV_UCFG_B1_P4_U1_PLD_IT4 EQU 0x40011890 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT5 +CYDEV_UCFG_B1_P4_U1_PLD_IT5 EQU 0x40011894 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT6 +CYDEV_UCFG_B1_P4_U1_PLD_IT6 EQU 0x40011898 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT7 +CYDEV_UCFG_B1_P4_U1_PLD_IT7 EQU 0x4001189c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT8 +CYDEV_UCFG_B1_P4_U1_PLD_IT8 EQU 0x400118a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT9 +CYDEV_UCFG_B1_P4_U1_PLD_IT9 EQU 0x400118a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT10 +CYDEV_UCFG_B1_P4_U1_PLD_IT10 EQU 0x400118a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT11 +CYDEV_UCFG_B1_P4_U1_PLD_IT11 EQU 0x400118ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_ORT0 +CYDEV_UCFG_B1_P4_U1_PLD_ORT0 EQU 0x400118b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_ORT1 +CYDEV_UCFG_B1_P4_U1_PLD_ORT1 EQU 0x400118b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_ORT2 +CYDEV_UCFG_B1_P4_U1_PLD_ORT2 EQU 0x400118b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_ORT3 +CYDEV_UCFG_B1_P4_U1_PLD_ORT3 EQU 0x400118b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST EQU 0x400118b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB +CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB EQU 0x400118ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET EQU 0x400118bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS +CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS EQU 0x400118be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG0 +CYDEV_UCFG_B1_P4_U1_CFG0 EQU 0x400118c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG1 +CYDEV_UCFG_B1_P4_U1_CFG1 EQU 0x400118c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG2 +CYDEV_UCFG_B1_P4_U1_CFG2 EQU 0x400118c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG3 +CYDEV_UCFG_B1_P4_U1_CFG3 EQU 0x400118c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG4 +CYDEV_UCFG_B1_P4_U1_CFG4 EQU 0x400118c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG5 +CYDEV_UCFG_B1_P4_U1_CFG5 EQU 0x400118c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG6 +CYDEV_UCFG_B1_P4_U1_CFG6 EQU 0x400118c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG7 +CYDEV_UCFG_B1_P4_U1_CFG7 EQU 0x400118c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG8 +CYDEV_UCFG_B1_P4_U1_CFG8 EQU 0x400118c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG9 +CYDEV_UCFG_B1_P4_U1_CFG9 EQU 0x400118c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG10 +CYDEV_UCFG_B1_P4_U1_CFG10 EQU 0x400118ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG11 +CYDEV_UCFG_B1_P4_U1_CFG11 EQU 0x400118cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG12 +CYDEV_UCFG_B1_P4_U1_CFG12 EQU 0x400118cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG13 +CYDEV_UCFG_B1_P4_U1_CFG13 EQU 0x400118cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG14 +CYDEV_UCFG_B1_P4_U1_CFG14 EQU 0x400118ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG15 +CYDEV_UCFG_B1_P4_U1_CFG15 EQU 0x400118cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG16 +CYDEV_UCFG_B1_P4_U1_CFG16 EQU 0x400118d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG17 +CYDEV_UCFG_B1_P4_U1_CFG17 EQU 0x400118d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG18 +CYDEV_UCFG_B1_P4_U1_CFG18 EQU 0x400118d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG19 +CYDEV_UCFG_B1_P4_U1_CFG19 EQU 0x400118d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG20 +CYDEV_UCFG_B1_P4_U1_CFG20 EQU 0x400118d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG21 +CYDEV_UCFG_B1_P4_U1_CFG21 EQU 0x400118d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG22 +CYDEV_UCFG_B1_P4_U1_CFG22 EQU 0x400118d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG23 +CYDEV_UCFG_B1_P4_U1_CFG23 EQU 0x400118d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG24 +CYDEV_UCFG_B1_P4_U1_CFG24 EQU 0x400118d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG25 +CYDEV_UCFG_B1_P4_U1_CFG25 EQU 0x400118d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG26 +CYDEV_UCFG_B1_P4_U1_CFG26 EQU 0x400118da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG27 +CYDEV_UCFG_B1_P4_U1_CFG27 EQU 0x400118db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG28 +CYDEV_UCFG_B1_P4_U1_CFG28 EQU 0x400118dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG29 +CYDEV_UCFG_B1_P4_U1_CFG29 EQU 0x400118dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG30 +CYDEV_UCFG_B1_P4_U1_CFG30 EQU 0x400118de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG31 +CYDEV_UCFG_B1_P4_U1_CFG31 EQU 0x400118df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG0 +CYDEV_UCFG_B1_P4_U1_DCFG0 EQU 0x400118e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG1 +CYDEV_UCFG_B1_P4_U1_DCFG1 EQU 0x400118e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG2 +CYDEV_UCFG_B1_P4_U1_DCFG2 EQU 0x400118e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG3 +CYDEV_UCFG_B1_P4_U1_DCFG3 EQU 0x400118e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG4 +CYDEV_UCFG_B1_P4_U1_DCFG4 EQU 0x400118e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG5 +CYDEV_UCFG_B1_P4_U1_DCFG5 EQU 0x400118ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG6 +CYDEV_UCFG_B1_P4_U1_DCFG6 EQU 0x400118ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG7 +CYDEV_UCFG_B1_P4_U1_DCFG7 EQU 0x400118ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_ROUTE_BASE +CYDEV_UCFG_B1_P4_ROUTE_BASE EQU 0x40011900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_ROUTE_SIZE +CYDEV_UCFG_B1_P4_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_BASE +CYDEV_UCFG_B1_P5_BASE EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_SIZE +CYDEV_UCFG_B1_P5_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_BASE +CYDEV_UCFG_B1_P5_U0_BASE EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_SIZE +CYDEV_UCFG_B1_P5_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT0 +CYDEV_UCFG_B1_P5_U0_PLD_IT0 EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT1 +CYDEV_UCFG_B1_P5_U0_PLD_IT1 EQU 0x40011a04 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT2 +CYDEV_UCFG_B1_P5_U0_PLD_IT2 EQU 0x40011a08 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT3 +CYDEV_UCFG_B1_P5_U0_PLD_IT3 EQU 0x40011a0c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT4 +CYDEV_UCFG_B1_P5_U0_PLD_IT4 EQU 0x40011a10 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT5 +CYDEV_UCFG_B1_P5_U0_PLD_IT5 EQU 0x40011a14 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT6 +CYDEV_UCFG_B1_P5_U0_PLD_IT6 EQU 0x40011a18 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT7 +CYDEV_UCFG_B1_P5_U0_PLD_IT7 EQU 0x40011a1c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT8 +CYDEV_UCFG_B1_P5_U0_PLD_IT8 EQU 0x40011a20 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT9 +CYDEV_UCFG_B1_P5_U0_PLD_IT9 EQU 0x40011a24 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT10 +CYDEV_UCFG_B1_P5_U0_PLD_IT10 EQU 0x40011a28 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT11 +CYDEV_UCFG_B1_P5_U0_PLD_IT11 EQU 0x40011a2c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_ORT0 +CYDEV_UCFG_B1_P5_U0_PLD_ORT0 EQU 0x40011a30 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_ORT1 +CYDEV_UCFG_B1_P5_U0_PLD_ORT1 EQU 0x40011a32 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_ORT2 +CYDEV_UCFG_B1_P5_U0_PLD_ORT2 EQU 0x40011a34 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_ORT3 +CYDEV_UCFG_B1_P5_U0_PLD_ORT3 EQU 0x40011a36 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST EQU 0x40011a38 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB +CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB EQU 0x40011a3a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET EQU 0x40011a3c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS +CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS EQU 0x40011a3e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG0 +CYDEV_UCFG_B1_P5_U0_CFG0 EQU 0x40011a40 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG1 +CYDEV_UCFG_B1_P5_U0_CFG1 EQU 0x40011a41 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG2 +CYDEV_UCFG_B1_P5_U0_CFG2 EQU 0x40011a42 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG3 +CYDEV_UCFG_B1_P5_U0_CFG3 EQU 0x40011a43 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG4 +CYDEV_UCFG_B1_P5_U0_CFG4 EQU 0x40011a44 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG5 +CYDEV_UCFG_B1_P5_U0_CFG5 EQU 0x40011a45 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG6 +CYDEV_UCFG_B1_P5_U0_CFG6 EQU 0x40011a46 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG7 +CYDEV_UCFG_B1_P5_U0_CFG7 EQU 0x40011a47 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG8 +CYDEV_UCFG_B1_P5_U0_CFG8 EQU 0x40011a48 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG9 +CYDEV_UCFG_B1_P5_U0_CFG9 EQU 0x40011a49 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG10 +CYDEV_UCFG_B1_P5_U0_CFG10 EQU 0x40011a4a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG11 +CYDEV_UCFG_B1_P5_U0_CFG11 EQU 0x40011a4b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG12 +CYDEV_UCFG_B1_P5_U0_CFG12 EQU 0x40011a4c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG13 +CYDEV_UCFG_B1_P5_U0_CFG13 EQU 0x40011a4d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG14 +CYDEV_UCFG_B1_P5_U0_CFG14 EQU 0x40011a4e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG15 +CYDEV_UCFG_B1_P5_U0_CFG15 EQU 0x40011a4f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG16 +CYDEV_UCFG_B1_P5_U0_CFG16 EQU 0x40011a50 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG17 +CYDEV_UCFG_B1_P5_U0_CFG17 EQU 0x40011a51 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG18 +CYDEV_UCFG_B1_P5_U0_CFG18 EQU 0x40011a52 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG19 +CYDEV_UCFG_B1_P5_U0_CFG19 EQU 0x40011a53 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG20 +CYDEV_UCFG_B1_P5_U0_CFG20 EQU 0x40011a54 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG21 +CYDEV_UCFG_B1_P5_U0_CFG21 EQU 0x40011a55 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG22 +CYDEV_UCFG_B1_P5_U0_CFG22 EQU 0x40011a56 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG23 +CYDEV_UCFG_B1_P5_U0_CFG23 EQU 0x40011a57 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG24 +CYDEV_UCFG_B1_P5_U0_CFG24 EQU 0x40011a58 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG25 +CYDEV_UCFG_B1_P5_U0_CFG25 EQU 0x40011a59 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG26 +CYDEV_UCFG_B1_P5_U0_CFG26 EQU 0x40011a5a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG27 +CYDEV_UCFG_B1_P5_U0_CFG27 EQU 0x40011a5b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG28 +CYDEV_UCFG_B1_P5_U0_CFG28 EQU 0x40011a5c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG29 +CYDEV_UCFG_B1_P5_U0_CFG29 EQU 0x40011a5d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG30 +CYDEV_UCFG_B1_P5_U0_CFG30 EQU 0x40011a5e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG31 +CYDEV_UCFG_B1_P5_U0_CFG31 EQU 0x40011a5f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG0 +CYDEV_UCFG_B1_P5_U0_DCFG0 EQU 0x40011a60 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG1 +CYDEV_UCFG_B1_P5_U0_DCFG1 EQU 0x40011a62 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG2 +CYDEV_UCFG_B1_P5_U0_DCFG2 EQU 0x40011a64 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG3 +CYDEV_UCFG_B1_P5_U0_DCFG3 EQU 0x40011a66 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG4 +CYDEV_UCFG_B1_P5_U0_DCFG4 EQU 0x40011a68 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG5 +CYDEV_UCFG_B1_P5_U0_DCFG5 EQU 0x40011a6a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG6 +CYDEV_UCFG_B1_P5_U0_DCFG6 EQU 0x40011a6c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG7 +CYDEV_UCFG_B1_P5_U0_DCFG7 EQU 0x40011a6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_BASE +CYDEV_UCFG_B1_P5_U1_BASE EQU 0x40011a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_SIZE +CYDEV_UCFG_B1_P5_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT0 +CYDEV_UCFG_B1_P5_U1_PLD_IT0 EQU 0x40011a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT1 +CYDEV_UCFG_B1_P5_U1_PLD_IT1 EQU 0x40011a84 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT2 +CYDEV_UCFG_B1_P5_U1_PLD_IT2 EQU 0x40011a88 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT3 +CYDEV_UCFG_B1_P5_U1_PLD_IT3 EQU 0x40011a8c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT4 +CYDEV_UCFG_B1_P5_U1_PLD_IT4 EQU 0x40011a90 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT5 +CYDEV_UCFG_B1_P5_U1_PLD_IT5 EQU 0x40011a94 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT6 +CYDEV_UCFG_B1_P5_U1_PLD_IT6 EQU 0x40011a98 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT7 +CYDEV_UCFG_B1_P5_U1_PLD_IT7 EQU 0x40011a9c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT8 +CYDEV_UCFG_B1_P5_U1_PLD_IT8 EQU 0x40011aa0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT9 +CYDEV_UCFG_B1_P5_U1_PLD_IT9 EQU 0x40011aa4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT10 +CYDEV_UCFG_B1_P5_U1_PLD_IT10 EQU 0x40011aa8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT11 +CYDEV_UCFG_B1_P5_U1_PLD_IT11 EQU 0x40011aac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_ORT0 +CYDEV_UCFG_B1_P5_U1_PLD_ORT0 EQU 0x40011ab0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_ORT1 +CYDEV_UCFG_B1_P5_U1_PLD_ORT1 EQU 0x40011ab2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_ORT2 +CYDEV_UCFG_B1_P5_U1_PLD_ORT2 EQU 0x40011ab4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_ORT3 +CYDEV_UCFG_B1_P5_U1_PLD_ORT3 EQU 0x40011ab6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST EQU 0x40011ab8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB +CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB EQU 0x40011aba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET EQU 0x40011abc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS +CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS EQU 0x40011abe + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG0 +CYDEV_UCFG_B1_P5_U1_CFG0 EQU 0x40011ac0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG1 +CYDEV_UCFG_B1_P5_U1_CFG1 EQU 0x40011ac1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG2 +CYDEV_UCFG_B1_P5_U1_CFG2 EQU 0x40011ac2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG3 +CYDEV_UCFG_B1_P5_U1_CFG3 EQU 0x40011ac3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG4 +CYDEV_UCFG_B1_P5_U1_CFG4 EQU 0x40011ac4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG5 +CYDEV_UCFG_B1_P5_U1_CFG5 EQU 0x40011ac5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG6 +CYDEV_UCFG_B1_P5_U1_CFG6 EQU 0x40011ac6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG7 +CYDEV_UCFG_B1_P5_U1_CFG7 EQU 0x40011ac7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG8 +CYDEV_UCFG_B1_P5_U1_CFG8 EQU 0x40011ac8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG9 +CYDEV_UCFG_B1_P5_U1_CFG9 EQU 0x40011ac9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG10 +CYDEV_UCFG_B1_P5_U1_CFG10 EQU 0x40011aca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG11 +CYDEV_UCFG_B1_P5_U1_CFG11 EQU 0x40011acb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG12 +CYDEV_UCFG_B1_P5_U1_CFG12 EQU 0x40011acc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG13 +CYDEV_UCFG_B1_P5_U1_CFG13 EQU 0x40011acd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG14 +CYDEV_UCFG_B1_P5_U1_CFG14 EQU 0x40011ace + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG15 +CYDEV_UCFG_B1_P5_U1_CFG15 EQU 0x40011acf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG16 +CYDEV_UCFG_B1_P5_U1_CFG16 EQU 0x40011ad0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG17 +CYDEV_UCFG_B1_P5_U1_CFG17 EQU 0x40011ad1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG18 +CYDEV_UCFG_B1_P5_U1_CFG18 EQU 0x40011ad2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG19 +CYDEV_UCFG_B1_P5_U1_CFG19 EQU 0x40011ad3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG20 +CYDEV_UCFG_B1_P5_U1_CFG20 EQU 0x40011ad4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG21 +CYDEV_UCFG_B1_P5_U1_CFG21 EQU 0x40011ad5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG22 +CYDEV_UCFG_B1_P5_U1_CFG22 EQU 0x40011ad6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG23 +CYDEV_UCFG_B1_P5_U1_CFG23 EQU 0x40011ad7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG24 +CYDEV_UCFG_B1_P5_U1_CFG24 EQU 0x40011ad8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG25 +CYDEV_UCFG_B1_P5_U1_CFG25 EQU 0x40011ad9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG26 +CYDEV_UCFG_B1_P5_U1_CFG26 EQU 0x40011ada + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG27 +CYDEV_UCFG_B1_P5_U1_CFG27 EQU 0x40011adb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG28 +CYDEV_UCFG_B1_P5_U1_CFG28 EQU 0x40011adc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG29 +CYDEV_UCFG_B1_P5_U1_CFG29 EQU 0x40011add + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG30 +CYDEV_UCFG_B1_P5_U1_CFG30 EQU 0x40011ade + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG31 +CYDEV_UCFG_B1_P5_U1_CFG31 EQU 0x40011adf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG0 +CYDEV_UCFG_B1_P5_U1_DCFG0 EQU 0x40011ae0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG1 +CYDEV_UCFG_B1_P5_U1_DCFG1 EQU 0x40011ae2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG2 +CYDEV_UCFG_B1_P5_U1_DCFG2 EQU 0x40011ae4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG3 +CYDEV_UCFG_B1_P5_U1_DCFG3 EQU 0x40011ae6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG4 +CYDEV_UCFG_B1_P5_U1_DCFG4 EQU 0x40011ae8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG5 +CYDEV_UCFG_B1_P5_U1_DCFG5 EQU 0x40011aea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG6 +CYDEV_UCFG_B1_P5_U1_DCFG6 EQU 0x40011aec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG7 +CYDEV_UCFG_B1_P5_U1_DCFG7 EQU 0x40011aee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_ROUTE_BASE +CYDEV_UCFG_B1_P5_ROUTE_BASE EQU 0x40011b00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_ROUTE_SIZE +CYDEV_UCFG_B1_P5_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI0_BASE +CYDEV_UCFG_DSI0_BASE EQU 0x40014000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI0_SIZE +CYDEV_UCFG_DSI0_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI1_BASE +CYDEV_UCFG_DSI1_BASE EQU 0x40014100 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI1_SIZE +CYDEV_UCFG_DSI1_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI2_BASE +CYDEV_UCFG_DSI2_BASE EQU 0x40014200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI2_SIZE +CYDEV_UCFG_DSI2_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI3_BASE +CYDEV_UCFG_DSI3_BASE EQU 0x40014300 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI3_SIZE +CYDEV_UCFG_DSI3_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI4_BASE +CYDEV_UCFG_DSI4_BASE EQU 0x40014400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI4_SIZE +CYDEV_UCFG_DSI4_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI5_BASE +CYDEV_UCFG_DSI5_BASE EQU 0x40014500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI5_SIZE +CYDEV_UCFG_DSI5_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI6_BASE +CYDEV_UCFG_DSI6_BASE EQU 0x40014600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI6_SIZE +CYDEV_UCFG_DSI6_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI7_BASE +CYDEV_UCFG_DSI7_BASE EQU 0x40014700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI7_SIZE +CYDEV_UCFG_DSI7_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI8_BASE +CYDEV_UCFG_DSI8_BASE EQU 0x40014800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI8_SIZE +CYDEV_UCFG_DSI8_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI9_BASE +CYDEV_UCFG_DSI9_BASE EQU 0x40014900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI9_SIZE +CYDEV_UCFG_DSI9_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI12_BASE +CYDEV_UCFG_DSI12_BASE EQU 0x40014c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI12_SIZE +CYDEV_UCFG_DSI12_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI13_BASE +CYDEV_UCFG_DSI13_BASE EQU 0x40014d00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI13_SIZE +CYDEV_UCFG_DSI13_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BASE +CYDEV_UCFG_BCTL0_BASE EQU 0x40015000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_SIZE +CYDEV_UCFG_BCTL0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_MDCLK_EN +CYDEV_UCFG_BCTL0_MDCLK_EN EQU 0x40015000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_MBCLK_EN +CYDEV_UCFG_BCTL0_MBCLK_EN EQU 0x40015001 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_WAIT_CFG +CYDEV_UCFG_BCTL0_WAIT_CFG EQU 0x40015002 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BANK_CTL +CYDEV_UCFG_BCTL0_BANK_CTL EQU 0x40015003 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_UDB_TEST_3 +CYDEV_UCFG_BCTL0_UDB_TEST_3 EQU 0x40015007 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_DCLK_EN0 +CYDEV_UCFG_BCTL0_DCLK_EN0 EQU 0x40015008 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BCLK_EN0 +CYDEV_UCFG_BCTL0_BCLK_EN0 EQU 0x40015009 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_DCLK_EN1 +CYDEV_UCFG_BCTL0_DCLK_EN1 EQU 0x4001500a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BCLK_EN1 +CYDEV_UCFG_BCTL0_BCLK_EN1 EQU 0x4001500b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_DCLK_EN2 +CYDEV_UCFG_BCTL0_DCLK_EN2 EQU 0x4001500c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BCLK_EN2 +CYDEV_UCFG_BCTL0_BCLK_EN2 EQU 0x4001500d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_DCLK_EN3 +CYDEV_UCFG_BCTL0_DCLK_EN3 EQU 0x4001500e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BCLK_EN3 +CYDEV_UCFG_BCTL0_BCLK_EN3 EQU 0x4001500f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BASE +CYDEV_UCFG_BCTL1_BASE EQU 0x40015010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_SIZE +CYDEV_UCFG_BCTL1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_MDCLK_EN +CYDEV_UCFG_BCTL1_MDCLK_EN EQU 0x40015010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_MBCLK_EN +CYDEV_UCFG_BCTL1_MBCLK_EN EQU 0x40015011 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_WAIT_CFG +CYDEV_UCFG_BCTL1_WAIT_CFG EQU 0x40015012 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BANK_CTL +CYDEV_UCFG_BCTL1_BANK_CTL EQU 0x40015013 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_UDB_TEST_3 +CYDEV_UCFG_BCTL1_UDB_TEST_3 EQU 0x40015017 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_DCLK_EN0 +CYDEV_UCFG_BCTL1_DCLK_EN0 EQU 0x40015018 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BCLK_EN0 +CYDEV_UCFG_BCTL1_BCLK_EN0 EQU 0x40015019 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_DCLK_EN1 +CYDEV_UCFG_BCTL1_DCLK_EN1 EQU 0x4001501a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BCLK_EN1 +CYDEV_UCFG_BCTL1_BCLK_EN1 EQU 0x4001501b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_DCLK_EN2 +CYDEV_UCFG_BCTL1_DCLK_EN2 EQU 0x4001501c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BCLK_EN2 +CYDEV_UCFG_BCTL1_BCLK_EN2 EQU 0x4001501d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_DCLK_EN3 +CYDEV_UCFG_BCTL1_DCLK_EN3 EQU 0x4001501e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BCLK_EN3 +CYDEV_UCFG_BCTL1_BCLK_EN3 EQU 0x4001501f + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_BASE +CYDEV_IDMUX_BASE EQU 0x40015100 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_SIZE +CYDEV_IDMUX_SIZE EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL0 +CYDEV_IDMUX_IRQ_CTL0 EQU 0x40015100 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL1 +CYDEV_IDMUX_IRQ_CTL1 EQU 0x40015101 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL2 +CYDEV_IDMUX_IRQ_CTL2 EQU 0x40015102 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL3 +CYDEV_IDMUX_IRQ_CTL3 EQU 0x40015103 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL4 +CYDEV_IDMUX_IRQ_CTL4 EQU 0x40015104 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL5 +CYDEV_IDMUX_IRQ_CTL5 EQU 0x40015105 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL6 +CYDEV_IDMUX_IRQ_CTL6 EQU 0x40015106 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL7 +CYDEV_IDMUX_IRQ_CTL7 EQU 0x40015107 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL0 +CYDEV_IDMUX_DRQ_CTL0 EQU 0x40015110 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL1 +CYDEV_IDMUX_DRQ_CTL1 EQU 0x40015111 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL2 +CYDEV_IDMUX_DRQ_CTL2 EQU 0x40015112 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL3 +CYDEV_IDMUX_DRQ_CTL3 EQU 0x40015113 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL4 +CYDEV_IDMUX_DRQ_CTL4 EQU 0x40015114 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL5 +CYDEV_IDMUX_DRQ_CTL5 EQU 0x40015115 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_BASE +CYDEV_CACHERAM_BASE EQU 0x40030000 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_SIZE +CYDEV_CACHERAM_SIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_DATA_MBASE +CYDEV_CACHERAM_DATA_MBASE EQU 0x40030000 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_DATA_MSIZE +CYDEV_CACHERAM_DATA_MSIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_BASE +CYDEV_SFR_BASE EQU 0x40050100 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_SIZE +CYDEV_SFR_SIZE EQU 0x000000fb + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO0 +CYDEV_SFR_GPIO0 EQU 0x40050180 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD0 +CYDEV_SFR_GPIRD0 EQU 0x40050189 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO0_SEL +CYDEV_SFR_GPIO0_SEL EQU 0x4005018a + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO1 +CYDEV_SFR_GPIO1 EQU 0x40050190 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD1 +CYDEV_SFR_GPIRD1 EQU 0x40050191 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO2 +CYDEV_SFR_GPIO2 EQU 0x40050198 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD2 +CYDEV_SFR_GPIRD2 EQU 0x40050199 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO2_SEL +CYDEV_SFR_GPIO2_SEL EQU 0x4005019a + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO1_SEL +CYDEV_SFR_GPIO1_SEL EQU 0x400501a2 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO3 +CYDEV_SFR_GPIO3 EQU 0x400501b0 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD3 +CYDEV_SFR_GPIRD3 EQU 0x400501b1 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO3_SEL +CYDEV_SFR_GPIO3_SEL EQU 0x400501b2 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO4 +CYDEV_SFR_GPIO4 EQU 0x400501c0 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD4 +CYDEV_SFR_GPIRD4 EQU 0x400501c1 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO4_SEL +CYDEV_SFR_GPIO4_SEL EQU 0x400501c2 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO5 +CYDEV_SFR_GPIO5 EQU 0x400501c8 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD5 +CYDEV_SFR_GPIRD5 EQU 0x400501c9 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO5_SEL +CYDEV_SFR_GPIO5_SEL EQU 0x400501ca + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO6 +CYDEV_SFR_GPIO6 EQU 0x400501d8 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD6 +CYDEV_SFR_GPIRD6 EQU 0x400501d9 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO6_SEL +CYDEV_SFR_GPIO6_SEL EQU 0x400501da + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO12 +CYDEV_SFR_GPIO12 EQU 0x400501e8 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD12 +CYDEV_SFR_GPIRD12 EQU 0x400501e9 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO12_SEL +CYDEV_SFR_GPIO12_SEL EQU 0x400501f2 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO15 +CYDEV_SFR_GPIO15 EQU 0x400501f8 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD15 +CYDEV_SFR_GPIRD15 EQU 0x400501f9 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO15_SEL +CYDEV_SFR_GPIO15_SEL EQU 0x400501fa + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_BASE +CYDEV_P3BA_BASE EQU 0x40050300 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_SIZE +CYDEV_P3BA_SIZE EQU 0x0000002b + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_Y_START +CYDEV_P3BA_Y_START EQU 0x40050300 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_YROLL +CYDEV_P3BA_YROLL EQU 0x40050301 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_YCFG +CYDEV_P3BA_YCFG EQU 0x40050302 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_X_START1 +CYDEV_P3BA_X_START1 EQU 0x40050303 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_X_START2 +CYDEV_P3BA_X_START2 EQU 0x40050304 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_XROLL1 +CYDEV_P3BA_XROLL1 EQU 0x40050305 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_XROLL2 +CYDEV_P3BA_XROLL2 EQU 0x40050306 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_XINC +CYDEV_P3BA_XINC EQU 0x40050307 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_XCFG +CYDEV_P3BA_XCFG EQU 0x40050308 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_OFFSETADDR1 +CYDEV_P3BA_OFFSETADDR1 EQU 0x40050309 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_OFFSETADDR2 +CYDEV_P3BA_OFFSETADDR2 EQU 0x4005030a + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_OFFSETADDR3 +CYDEV_P3BA_OFFSETADDR3 EQU 0x4005030b + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_ABSADDR1 +CYDEV_P3BA_ABSADDR1 EQU 0x4005030c + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_ABSADDR2 +CYDEV_P3BA_ABSADDR2 EQU 0x4005030d + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_ABSADDR3 +CYDEV_P3BA_ABSADDR3 EQU 0x4005030e + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_ABSADDR4 +CYDEV_P3BA_ABSADDR4 EQU 0x4005030f + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATCFG1 +CYDEV_P3BA_DATCFG1 EQU 0x40050310 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATCFG2 +CYDEV_P3BA_DATCFG2 EQU 0x40050311 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_CMP_RSLT1 +CYDEV_P3BA_CMP_RSLT1 EQU 0x40050314 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_CMP_RSLT2 +CYDEV_P3BA_CMP_RSLT2 EQU 0x40050315 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_CMP_RSLT3 +CYDEV_P3BA_CMP_RSLT3 EQU 0x40050316 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_CMP_RSLT4 +CYDEV_P3BA_CMP_RSLT4 EQU 0x40050317 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATA_REG1 +CYDEV_P3BA_DATA_REG1 EQU 0x40050318 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATA_REG2 +CYDEV_P3BA_DATA_REG2 EQU 0x40050319 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATA_REG3 +CYDEV_P3BA_DATA_REG3 EQU 0x4005031a + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATA_REG4 +CYDEV_P3BA_DATA_REG4 EQU 0x4005031b + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_EXP_DATA1 +CYDEV_P3BA_EXP_DATA1 EQU 0x4005031c + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_EXP_DATA2 +CYDEV_P3BA_EXP_DATA2 EQU 0x4005031d + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_EXP_DATA3 +CYDEV_P3BA_EXP_DATA3 EQU 0x4005031e + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_EXP_DATA4 +CYDEV_P3BA_EXP_DATA4 EQU 0x4005031f + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_MSTR_HRDATA1 +CYDEV_P3BA_MSTR_HRDATA1 EQU 0x40050320 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_MSTR_HRDATA2 +CYDEV_P3BA_MSTR_HRDATA2 EQU 0x40050321 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_MSTR_HRDATA3 +CYDEV_P3BA_MSTR_HRDATA3 EQU 0x40050322 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_MSTR_HRDATA4 +CYDEV_P3BA_MSTR_HRDATA4 EQU 0x40050323 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_BIST_EN +CYDEV_P3BA_BIST_EN EQU 0x40050324 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_PHUB_MASTER_SSR +CYDEV_P3BA_PHUB_MASTER_SSR EQU 0x40050325 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_SEQCFG1 +CYDEV_P3BA_SEQCFG1 EQU 0x40050326 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_SEQCFG2 +CYDEV_P3BA_SEQCFG2 EQU 0x40050327 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_Y_CURR +CYDEV_P3BA_Y_CURR EQU 0x40050328 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_X_CURR1 +CYDEV_P3BA_X_CURR1 EQU 0x40050329 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_X_CURR2 +CYDEV_P3BA_X_CURR2 EQU 0x4005032a + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_BASE +CYDEV_PANTHER_BASE EQU 0x40080000 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_SIZE +CYDEV_PANTHER_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_STCALIB_CFG +CYDEV_PANTHER_STCALIB_CFG EQU 0x40080000 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_WAITPIPE +CYDEV_PANTHER_WAITPIPE EQU 0x40080004 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_TRACE_CFG +CYDEV_PANTHER_TRACE_CFG EQU 0x40080008 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_DBG_CFG +CYDEV_PANTHER_DBG_CFG EQU 0x4008000c + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_CM3_LCKRST_STAT +CYDEV_PANTHER_CM3_LCKRST_STAT EQU 0x40080018 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_DEVICE_ID +CYDEV_PANTHER_DEVICE_ID EQU 0x4008001c + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_BASE +CYDEV_FLSECC_BASE EQU 0x48000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_SIZE +CYDEV_FLSECC_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_DATA_MBASE +CYDEV_FLSECC_DATA_MBASE EQU 0x48000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_DATA_MSIZE +CYDEV_FLSECC_DATA_MSIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_BASE +CYDEV_FLSHID_BASE EQU 0x49000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_SIZE +CYDEV_FLSHID_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_RSVD_MBASE +CYDEV_FLSHID_RSVD_MBASE EQU 0x49000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_RSVD_MSIZE +CYDEV_FLSHID_RSVD_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_MDATA_MBASE +CYDEV_FLSHID_CUST_MDATA_MBASE EQU 0x49000080 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_MDATA_MSIZE +CYDEV_FLSHID_CUST_MDATA_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_BASE +CYDEV_FLSHID_CUST_TABLES_BASE EQU 0x49000100 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_SIZE +CYDEV_FLSHID_CUST_TABLES_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_Y_LOC +CYDEV_FLSHID_CUST_TABLES_Y_LOC EQU 0x49000100 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_X_LOC +CYDEV_FLSHID_CUST_TABLES_X_LOC EQU 0x49000101 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_WAFER_NUM +CYDEV_FLSHID_CUST_TABLES_WAFER_NUM EQU 0x49000102 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_LOT_LSB +CYDEV_FLSHID_CUST_TABLES_LOT_LSB EQU 0x49000103 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_LOT_MSB +CYDEV_FLSHID_CUST_TABLES_LOT_MSB EQU 0x49000104 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_WRK_WK +CYDEV_FLSHID_CUST_TABLES_WRK_WK EQU 0x49000105 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_FAB_YR +CYDEV_FLSHID_CUST_TABLES_FAB_YR EQU 0x49000106 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_MINOR +CYDEV_FLSHID_CUST_TABLES_MINOR EQU 0x49000107 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ EQU 0x49000108 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ EQU 0x49000109 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ EQU 0x4900010a + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ EQU 0x4900010b + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ EQU 0x4900010c + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ EQU 0x4900010d + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ EQU 0x4900010e + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_USB +CYDEV_FLSHID_CUST_TABLES_IMO_USB EQU 0x4900010f + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS +CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS EQU 0x49000110 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS +CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS EQU 0x49000111 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS +CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS EQU 0x49000112 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS +CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS EQU 0x49000113 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS +CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS EQU 0x49000114 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS +CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS EQU 0x49000115 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS +CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS EQU 0x49000116 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS +CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS EQU 0x49000117 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M1 +CYDEV_FLSHID_CUST_TABLES_DEC_M1 EQU 0x49000118 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M2 +CYDEV_FLSHID_CUST_TABLES_DEC_M2 EQU 0x49000119 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M3 +CYDEV_FLSHID_CUST_TABLES_DEC_M3 EQU 0x4900011a + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M4 +CYDEV_FLSHID_CUST_TABLES_DEC_M4 EQU 0x4900011b + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M5 +CYDEV_FLSHID_CUST_TABLES_DEC_M5 EQU 0x4900011c + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M6 +CYDEV_FLSHID_CUST_TABLES_DEC_M6 EQU 0x4900011d + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M7 +CYDEV_FLSHID_CUST_TABLES_DEC_M7 EQU 0x4900011e + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M8 +CYDEV_FLSHID_CUST_TABLES_DEC_M8 EQU 0x4900011f + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M1 +CYDEV_FLSHID_CUST_TABLES_DAC0_M1 EQU 0x49000120 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M2 +CYDEV_FLSHID_CUST_TABLES_DAC0_M2 EQU 0x49000121 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M3 +CYDEV_FLSHID_CUST_TABLES_DAC0_M3 EQU 0x49000122 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M4 +CYDEV_FLSHID_CUST_TABLES_DAC0_M4 EQU 0x49000123 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M5 +CYDEV_FLSHID_CUST_TABLES_DAC0_M5 EQU 0x49000124 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M6 +CYDEV_FLSHID_CUST_TABLES_DAC0_M6 EQU 0x49000125 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M7 +CYDEV_FLSHID_CUST_TABLES_DAC0_M7 EQU 0x49000126 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M8 +CYDEV_FLSHID_CUST_TABLES_DAC0_M8 EQU 0x49000127 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M1 +CYDEV_FLSHID_CUST_TABLES_DAC2_M1 EQU 0x49000128 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M2 +CYDEV_FLSHID_CUST_TABLES_DAC2_M2 EQU 0x49000129 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M3 +CYDEV_FLSHID_CUST_TABLES_DAC2_M3 EQU 0x4900012a + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M4 +CYDEV_FLSHID_CUST_TABLES_DAC2_M4 EQU 0x4900012b + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M5 +CYDEV_FLSHID_CUST_TABLES_DAC2_M5 EQU 0x4900012c + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M6 +CYDEV_FLSHID_CUST_TABLES_DAC2_M6 EQU 0x4900012d + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M7 +CYDEV_FLSHID_CUST_TABLES_DAC2_M7 EQU 0x4900012e + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M8 +CYDEV_FLSHID_CUST_TABLES_DAC2_M8 EQU 0x4900012f + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M1 +CYDEV_FLSHID_CUST_TABLES_DAC1_M1 EQU 0x49000130 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M2 +CYDEV_FLSHID_CUST_TABLES_DAC1_M2 EQU 0x49000131 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M3 +CYDEV_FLSHID_CUST_TABLES_DAC1_M3 EQU 0x49000132 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M4 +CYDEV_FLSHID_CUST_TABLES_DAC1_M4 EQU 0x49000133 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M5 +CYDEV_FLSHID_CUST_TABLES_DAC1_M5 EQU 0x49000134 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M6 +CYDEV_FLSHID_CUST_TABLES_DAC1_M6 EQU 0x49000135 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M7 +CYDEV_FLSHID_CUST_TABLES_DAC1_M7 EQU 0x49000136 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M8 +CYDEV_FLSHID_CUST_TABLES_DAC1_M8 EQU 0x49000137 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M1 +CYDEV_FLSHID_CUST_TABLES_DAC3_M1 EQU 0x49000138 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M2 +CYDEV_FLSHID_CUST_TABLES_DAC3_M2 EQU 0x49000139 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M3 +CYDEV_FLSHID_CUST_TABLES_DAC3_M3 EQU 0x4900013a + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M4 +CYDEV_FLSHID_CUST_TABLES_DAC3_M4 EQU 0x4900013b + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M5 +CYDEV_FLSHID_CUST_TABLES_DAC3_M5 EQU 0x4900013c + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M6 +CYDEV_FLSHID_CUST_TABLES_DAC3_M6 EQU 0x4900013d + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M7 +CYDEV_FLSHID_CUST_TABLES_DAC3_M7 EQU 0x4900013e + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M8 +CYDEV_FLSHID_CUST_TABLES_DAC3_M8 EQU 0x4900013f + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_BASE +CYDEV_FLSHID_MFG_CFG_BASE EQU 0x49000180 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_SIZE +CYDEV_FLSHID_MFG_CFG_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_IMO_TR1 +CYDEV_FLSHID_MFG_CFG_IMO_TR1 EQU 0x49000188 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP0_TR0 +CYDEV_FLSHID_MFG_CFG_CMP0_TR0 EQU 0x490001ac + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP1_TR0 +CYDEV_FLSHID_MFG_CFG_CMP1_TR0 EQU 0x490001ae + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP2_TR0 +CYDEV_FLSHID_MFG_CFG_CMP2_TR0 EQU 0x490001b0 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP3_TR0 +CYDEV_FLSHID_MFG_CFG_CMP3_TR0 EQU 0x490001b2 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP0_TR1 +CYDEV_FLSHID_MFG_CFG_CMP0_TR1 EQU 0x490001b4 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP1_TR1 +CYDEV_FLSHID_MFG_CFG_CMP1_TR1 EQU 0x490001b6 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP2_TR1 +CYDEV_FLSHID_MFG_CFG_CMP2_TR1 EQU 0x490001b8 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP3_TR1 +CYDEV_FLSHID_MFG_CFG_CMP3_TR1 EQU 0x490001ba + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM +CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM EQU 0x490001ce + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_BASE +CYDEV_EXTMEM_BASE EQU 0x60000000 + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_SIZE +CYDEV_EXTMEM_SIZE EQU 0x00800000 + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_DATA_MBASE +CYDEV_EXTMEM_DATA_MBASE EQU 0x60000000 + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_DATA_MSIZE +CYDEV_EXTMEM_DATA_MSIZE EQU 0x00800000 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_BASE +CYDEV_ITM_BASE EQU 0xe0000000 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_SIZE +CYDEV_ITM_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_TRACE_EN +CYDEV_ITM_TRACE_EN EQU 0xe0000e00 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_TRACE_PRIVILEGE +CYDEV_ITM_TRACE_PRIVILEGE EQU 0xe0000e40 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_TRACE_CTRL +CYDEV_ITM_TRACE_CTRL EQU 0xe0000e80 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_LOCK_ACCESS +CYDEV_ITM_LOCK_ACCESS EQU 0xe0000fb0 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_LOCK_STATUS +CYDEV_ITM_LOCK_STATUS EQU 0xe0000fb4 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID4 +CYDEV_ITM_PID4 EQU 0xe0000fd0 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID5 +CYDEV_ITM_PID5 EQU 0xe0000fd4 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID6 +CYDEV_ITM_PID6 EQU 0xe0000fd8 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID7 +CYDEV_ITM_PID7 EQU 0xe0000fdc + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID0 +CYDEV_ITM_PID0 EQU 0xe0000fe0 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID1 +CYDEV_ITM_PID1 EQU 0xe0000fe4 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID2 +CYDEV_ITM_PID2 EQU 0xe0000fe8 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID3 +CYDEV_ITM_PID3 EQU 0xe0000fec + ENDIF + IF :LNOT::DEF:CYDEV_ITM_CID0 +CYDEV_ITM_CID0 EQU 0xe0000ff0 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_CID1 +CYDEV_ITM_CID1 EQU 0xe0000ff4 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_CID2 +CYDEV_ITM_CID2 EQU 0xe0000ff8 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_CID3 +CYDEV_ITM_CID3 EQU 0xe0000ffc + ENDIF + IF :LNOT::DEF:CYDEV_DWT_BASE +CYDEV_DWT_BASE EQU 0xe0001000 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_SIZE +CYDEV_DWT_SIZE EQU 0x0000005c + ENDIF + IF :LNOT::DEF:CYDEV_DWT_CTRL +CYDEV_DWT_CTRL EQU 0xe0001000 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_CYCLE_COUNT +CYDEV_DWT_CYCLE_COUNT EQU 0xe0001004 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_CPI_COUNT +CYDEV_DWT_CPI_COUNT EQU 0xe0001008 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_EXC_OVHD_COUNT +CYDEV_DWT_EXC_OVHD_COUNT EQU 0xe000100c + ENDIF + IF :LNOT::DEF:CYDEV_DWT_SLEEP_COUNT +CYDEV_DWT_SLEEP_COUNT EQU 0xe0001010 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_LSU_COUNT +CYDEV_DWT_LSU_COUNT EQU 0xe0001014 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_FOLD_COUNT +CYDEV_DWT_FOLD_COUNT EQU 0xe0001018 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_PC_SAMPLE +CYDEV_DWT_PC_SAMPLE EQU 0xe000101c + ENDIF + IF :LNOT::DEF:CYDEV_DWT_COMP_0 +CYDEV_DWT_COMP_0 EQU 0xe0001020 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_MASK_0 +CYDEV_DWT_MASK_0 EQU 0xe0001024 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_FUNCTION_0 +CYDEV_DWT_FUNCTION_0 EQU 0xe0001028 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_COMP_1 +CYDEV_DWT_COMP_1 EQU 0xe0001030 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_MASK_1 +CYDEV_DWT_MASK_1 EQU 0xe0001034 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_FUNCTION_1 +CYDEV_DWT_FUNCTION_1 EQU 0xe0001038 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_COMP_2 +CYDEV_DWT_COMP_2 EQU 0xe0001040 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_MASK_2 +CYDEV_DWT_MASK_2 EQU 0xe0001044 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_FUNCTION_2 +CYDEV_DWT_FUNCTION_2 EQU 0xe0001048 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_COMP_3 +CYDEV_DWT_COMP_3 EQU 0xe0001050 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_MASK_3 +CYDEV_DWT_MASK_3 EQU 0xe0001054 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_FUNCTION_3 +CYDEV_DWT_FUNCTION_3 EQU 0xe0001058 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_BASE +CYDEV_FPB_BASE EQU 0xe0002000 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_SIZE +CYDEV_FPB_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_CTRL +CYDEV_FPB_CTRL EQU 0xe0002000 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_REMAP +CYDEV_FPB_REMAP EQU 0xe0002004 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_0 +CYDEV_FPB_FP_COMP_0 EQU 0xe0002008 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_1 +CYDEV_FPB_FP_COMP_1 EQU 0xe000200c + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_2 +CYDEV_FPB_FP_COMP_2 EQU 0xe0002010 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_3 +CYDEV_FPB_FP_COMP_3 EQU 0xe0002014 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_4 +CYDEV_FPB_FP_COMP_4 EQU 0xe0002018 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_5 +CYDEV_FPB_FP_COMP_5 EQU 0xe000201c + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_6 +CYDEV_FPB_FP_COMP_6 EQU 0xe0002020 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_7 +CYDEV_FPB_FP_COMP_7 EQU 0xe0002024 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID4 +CYDEV_FPB_PID4 EQU 0xe0002fd0 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID5 +CYDEV_FPB_PID5 EQU 0xe0002fd4 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID6 +CYDEV_FPB_PID6 EQU 0xe0002fd8 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID7 +CYDEV_FPB_PID7 EQU 0xe0002fdc + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID0 +CYDEV_FPB_PID0 EQU 0xe0002fe0 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID1 +CYDEV_FPB_PID1 EQU 0xe0002fe4 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID2 +CYDEV_FPB_PID2 EQU 0xe0002fe8 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID3 +CYDEV_FPB_PID3 EQU 0xe0002fec + ENDIF + IF :LNOT::DEF:CYDEV_FPB_CID0 +CYDEV_FPB_CID0 EQU 0xe0002ff0 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_CID1 +CYDEV_FPB_CID1 EQU 0xe0002ff4 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_CID2 +CYDEV_FPB_CID2 EQU 0xe0002ff8 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_CID3 +CYDEV_FPB_CID3 EQU 0xe0002ffc + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_BASE +CYDEV_NVIC_BASE EQU 0xe000e000 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SIZE +CYDEV_NVIC_SIZE EQU 0x00000d3c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_INT_CTL_TYPE +CYDEV_NVIC_INT_CTL_TYPE EQU 0xe000e004 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYSTICK_CTL +CYDEV_NVIC_SYSTICK_CTL EQU 0xe000e010 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYSTICK_RELOAD +CYDEV_NVIC_SYSTICK_RELOAD EQU 0xe000e014 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYSTICK_CURRENT +CYDEV_NVIC_SYSTICK_CURRENT EQU 0xe000e018 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYSTICK_CAL +CYDEV_NVIC_SYSTICK_CAL EQU 0xe000e01c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SETENA0 +CYDEV_NVIC_SETENA0 EQU 0xe000e100 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_CLRENA0 +CYDEV_NVIC_CLRENA0 EQU 0xe000e180 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SETPEND0 +CYDEV_NVIC_SETPEND0 EQU 0xe000e200 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_CLRPEND0 +CYDEV_NVIC_CLRPEND0 EQU 0xe000e280 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_ACTIVE0 +CYDEV_NVIC_ACTIVE0 EQU 0xe000e300 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_0 +CYDEV_NVIC_PRI_0 EQU 0xe000e400 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_1 +CYDEV_NVIC_PRI_1 EQU 0xe000e401 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_2 +CYDEV_NVIC_PRI_2 EQU 0xe000e402 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_3 +CYDEV_NVIC_PRI_3 EQU 0xe000e403 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_4 +CYDEV_NVIC_PRI_4 EQU 0xe000e404 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_5 +CYDEV_NVIC_PRI_5 EQU 0xe000e405 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_6 +CYDEV_NVIC_PRI_6 EQU 0xe000e406 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_7 +CYDEV_NVIC_PRI_7 EQU 0xe000e407 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_8 +CYDEV_NVIC_PRI_8 EQU 0xe000e408 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_9 +CYDEV_NVIC_PRI_9 EQU 0xe000e409 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_10 +CYDEV_NVIC_PRI_10 EQU 0xe000e40a + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_11 +CYDEV_NVIC_PRI_11 EQU 0xe000e40b + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_12 +CYDEV_NVIC_PRI_12 EQU 0xe000e40c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_13 +CYDEV_NVIC_PRI_13 EQU 0xe000e40d + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_14 +CYDEV_NVIC_PRI_14 EQU 0xe000e40e + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_15 +CYDEV_NVIC_PRI_15 EQU 0xe000e40f + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_16 +CYDEV_NVIC_PRI_16 EQU 0xe000e410 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_17 +CYDEV_NVIC_PRI_17 EQU 0xe000e411 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_18 +CYDEV_NVIC_PRI_18 EQU 0xe000e412 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_19 +CYDEV_NVIC_PRI_19 EQU 0xe000e413 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_20 +CYDEV_NVIC_PRI_20 EQU 0xe000e414 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_21 +CYDEV_NVIC_PRI_21 EQU 0xe000e415 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_22 +CYDEV_NVIC_PRI_22 EQU 0xe000e416 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_23 +CYDEV_NVIC_PRI_23 EQU 0xe000e417 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_24 +CYDEV_NVIC_PRI_24 EQU 0xe000e418 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_25 +CYDEV_NVIC_PRI_25 EQU 0xe000e419 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_26 +CYDEV_NVIC_PRI_26 EQU 0xe000e41a + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_27 +CYDEV_NVIC_PRI_27 EQU 0xe000e41b + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_28 +CYDEV_NVIC_PRI_28 EQU 0xe000e41c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_29 +CYDEV_NVIC_PRI_29 EQU 0xe000e41d + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_30 +CYDEV_NVIC_PRI_30 EQU 0xe000e41e + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_31 +CYDEV_NVIC_PRI_31 EQU 0xe000e41f + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_CPUID_BASE +CYDEV_NVIC_CPUID_BASE EQU 0xe000ed00 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_INTR_CTRL_STATE +CYDEV_NVIC_INTR_CTRL_STATE EQU 0xe000ed04 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_VECT_OFFSET +CYDEV_NVIC_VECT_OFFSET EQU 0xe000ed08 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_APPLN_INTR +CYDEV_NVIC_APPLN_INTR EQU 0xe000ed0c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYSTEM_CONTROL +CYDEV_NVIC_SYSTEM_CONTROL EQU 0xe000ed10 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_CFG_CONTROL +CYDEV_NVIC_CFG_CONTROL EQU 0xe000ed14 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYS_PRIO_HANDLER_4_7 +CYDEV_NVIC_SYS_PRIO_HANDLER_4_7 EQU 0xe000ed18 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYS_PRIO_HANDLER_8_11 +CYDEV_NVIC_SYS_PRIO_HANDLER_8_11 EQU 0xe000ed1c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYS_PRIO_HANDLER_12_15 +CYDEV_NVIC_SYS_PRIO_HANDLER_12_15 EQU 0xe000ed20 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYS_HANDLER_CSR +CYDEV_NVIC_SYS_HANDLER_CSR EQU 0xe000ed24 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_MEMMAN_FAULT_STATUS +CYDEV_NVIC_MEMMAN_FAULT_STATUS EQU 0xe000ed28 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_BUS_FAULT_STATUS +CYDEV_NVIC_BUS_FAULT_STATUS EQU 0xe000ed29 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_USAGE_FAULT_STATUS +CYDEV_NVIC_USAGE_FAULT_STATUS EQU 0xe000ed2a + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_HARD_FAULT_STATUS +CYDEV_NVIC_HARD_FAULT_STATUS EQU 0xe000ed2c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_DEBUG_FAULT_STATUS +CYDEV_NVIC_DEBUG_FAULT_STATUS EQU 0xe000ed30 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_MEMMAN_FAULT_ADD +CYDEV_NVIC_MEMMAN_FAULT_ADD EQU 0xe000ed34 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_BUS_FAULT_ADD +CYDEV_NVIC_BUS_FAULT_ADD EQU 0xe000ed38 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_BASE +CYDEV_CORE_DBG_BASE EQU 0xe000edf0 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_SIZE +CYDEV_CORE_DBG_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_DBG_HLT_CS +CYDEV_CORE_DBG_DBG_HLT_CS EQU 0xe000edf0 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_DBG_REG_SEL +CYDEV_CORE_DBG_DBG_REG_SEL EQU 0xe000edf4 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_DBG_REG_DATA +CYDEV_CORE_DBG_DBG_REG_DATA EQU 0xe000edf8 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_EXC_MON_CTL +CYDEV_CORE_DBG_EXC_MON_CTL EQU 0xe000edfc + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_BASE +CYDEV_TPIU_BASE EQU 0xe0040000 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_SIZE +CYDEV_TPIU_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ +CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ EQU 0xe0040000 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_CURRENT_SYNC_PRT_SZ +CYDEV_TPIU_CURRENT_SYNC_PRT_SZ EQU 0xe0040004 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ASYNC_CLK_PRESCALER +CYDEV_TPIU_ASYNC_CLK_PRESCALER EQU 0xe0040010 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PROTOCOL +CYDEV_TPIU_PROTOCOL EQU 0xe00400f0 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_FORM_FLUSH_STAT +CYDEV_TPIU_FORM_FLUSH_STAT EQU 0xe0040300 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_FORM_FLUSH_CTRL +CYDEV_TPIU_FORM_FLUSH_CTRL EQU 0xe0040304 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_TRIGGER +CYDEV_TPIU_TRIGGER EQU 0xe0040ee8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ITETMDATA +CYDEV_TPIU_ITETMDATA EQU 0xe0040eec + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ITATBCTR2 +CYDEV_TPIU_ITATBCTR2 EQU 0xe0040ef0 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ITATBCTR0 +CYDEV_TPIU_ITATBCTR0 EQU 0xe0040ef8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ITITMDATA +CYDEV_TPIU_ITITMDATA EQU 0xe0040efc + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ITCTRL +CYDEV_TPIU_ITCTRL EQU 0xe0040f00 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_DEVID +CYDEV_TPIU_DEVID EQU 0xe0040fc8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_DEVTYPE +CYDEV_TPIU_DEVTYPE EQU 0xe0040fcc + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID4 +CYDEV_TPIU_PID4 EQU 0xe0040fd0 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID5 +CYDEV_TPIU_PID5 EQU 0xe0040fd4 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID6 +CYDEV_TPIU_PID6 EQU 0xe0040fd8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID7 +CYDEV_TPIU_PID7 EQU 0xe0040fdc + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID0 +CYDEV_TPIU_PID0 EQU 0xe0040fe0 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID1 +CYDEV_TPIU_PID1 EQU 0xe0040fe4 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID2 +CYDEV_TPIU_PID2 EQU 0xe0040fe8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID3 +CYDEV_TPIU_PID3 EQU 0xe0040fec + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_CID0 +CYDEV_TPIU_CID0 EQU 0xe0040ff0 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_CID1 +CYDEV_TPIU_CID1 EQU 0xe0040ff4 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_CID2 +CYDEV_TPIU_CID2 EQU 0xe0040ff8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_CID3 +CYDEV_TPIU_CID3 EQU 0xe0040ffc + ENDIF + IF :LNOT::DEF:CYDEV_ETM_BASE +CYDEV_ETM_BASE EQU 0xe0041000 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_SIZE +CYDEV_ETM_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CTL +CYDEV_ETM_CTL EQU 0xe0041000 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CFG_CODE +CYDEV_ETM_CFG_CODE EQU 0xe0041004 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_TRIG_EVENT +CYDEV_ETM_TRIG_EVENT EQU 0xe0041008 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_STATUS +CYDEV_ETM_STATUS EQU 0xe0041010 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_SYS_CFG +CYDEV_ETM_SYS_CFG EQU 0xe0041014 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_TRACE_ENB_EVENT +CYDEV_ETM_TRACE_ENB_EVENT EQU 0xe0041020 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_TRACE_EN_CTRL1 +CYDEV_ETM_TRACE_EN_CTRL1 EQU 0xe0041024 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_FIFOFULL_LEVEL +CYDEV_ETM_FIFOFULL_LEVEL EQU 0xe004102c + ENDIF + IF :LNOT::DEF:CYDEV_ETM_SYNC_FREQ +CYDEV_ETM_SYNC_FREQ EQU 0xe00411e0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_ETM_ID +CYDEV_ETM_ETM_ID EQU 0xe00411e4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CFG_CODE_EXT +CYDEV_ETM_CFG_CODE_EXT EQU 0xe00411e8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_TR_SS_EMBICE_CTRL +CYDEV_ETM_TR_SS_EMBICE_CTRL EQU 0xe00411f0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CS_TRACE_ID +CYDEV_ETM_CS_TRACE_ID EQU 0xe0041200 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_OS_LOCK_ACCESS +CYDEV_ETM_OS_LOCK_ACCESS EQU 0xe0041300 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_OS_LOCK_STATUS +CYDEV_ETM_OS_LOCK_STATUS EQU 0xe0041304 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PDSR +CYDEV_ETM_PDSR EQU 0xe0041314 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_ITMISCIN +CYDEV_ETM_ITMISCIN EQU 0xe0041ee0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_ITTRIGOUT +CYDEV_ETM_ITTRIGOUT EQU 0xe0041ee8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_ITATBCTR2 +CYDEV_ETM_ITATBCTR2 EQU 0xe0041ef0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_ITATBCTR0 +CYDEV_ETM_ITATBCTR0 EQU 0xe0041ef8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_INT_MODE_CTRL +CYDEV_ETM_INT_MODE_CTRL EQU 0xe0041f00 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CLM_TAG_SET +CYDEV_ETM_CLM_TAG_SET EQU 0xe0041fa0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CLM_TAG_CLR +CYDEV_ETM_CLM_TAG_CLR EQU 0xe0041fa4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_LOCK_ACCESS +CYDEV_ETM_LOCK_ACCESS EQU 0xe0041fb0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_LOCK_STATUS +CYDEV_ETM_LOCK_STATUS EQU 0xe0041fb4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_AUTH_STATUS +CYDEV_ETM_AUTH_STATUS EQU 0xe0041fb8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_DEV_TYPE +CYDEV_ETM_DEV_TYPE EQU 0xe0041fcc + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID4 +CYDEV_ETM_PID4 EQU 0xe0041fd0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID5 +CYDEV_ETM_PID5 EQU 0xe0041fd4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID6 +CYDEV_ETM_PID6 EQU 0xe0041fd8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID7 +CYDEV_ETM_PID7 EQU 0xe0041fdc + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID0 +CYDEV_ETM_PID0 EQU 0xe0041fe0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID1 +CYDEV_ETM_PID1 EQU 0xe0041fe4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID2 +CYDEV_ETM_PID2 EQU 0xe0041fe8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID3 +CYDEV_ETM_PID3 EQU 0xe0041fec + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CID0 +CYDEV_ETM_CID0 EQU 0xe0041ff0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CID1 +CYDEV_ETM_CID1 EQU 0xe0041ff4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CID2 +CYDEV_ETM_CID2 EQU 0xe0041ff8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CID3 +CYDEV_ETM_CID3 EQU 0xe0041ffc + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_BASE +CYDEV_ROM_TABLE_BASE EQU 0xe00ff000 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_SIZE +CYDEV_ROM_TABLE_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_NVIC +CYDEV_ROM_TABLE_NVIC EQU 0xe00ff000 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_DWT +CYDEV_ROM_TABLE_DWT EQU 0xe00ff004 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_FPB +CYDEV_ROM_TABLE_FPB EQU 0xe00ff008 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_ITM +CYDEV_ROM_TABLE_ITM EQU 0xe00ff00c + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_TPIU +CYDEV_ROM_TABLE_TPIU EQU 0xe00ff010 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_ETM +CYDEV_ROM_TABLE_ETM EQU 0xe00ff014 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_END +CYDEV_ROM_TABLE_END EQU 0xe00ff018 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_MEMTYPE +CYDEV_ROM_TABLE_MEMTYPE EQU 0xe00fffcc + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID4 +CYDEV_ROM_TABLE_PID4 EQU 0xe00fffd0 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID5 +CYDEV_ROM_TABLE_PID5 EQU 0xe00fffd4 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID6 +CYDEV_ROM_TABLE_PID6 EQU 0xe00fffd8 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID7 +CYDEV_ROM_TABLE_PID7 EQU 0xe00fffdc + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID0 +CYDEV_ROM_TABLE_PID0 EQU 0xe00fffe0 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID1 +CYDEV_ROM_TABLE_PID1 EQU 0xe00fffe4 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID2 +CYDEV_ROM_TABLE_PID2 EQU 0xe00fffe8 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID3 +CYDEV_ROM_TABLE_PID3 EQU 0xe00fffec + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_CID0 +CYDEV_ROM_TABLE_CID0 EQU 0xe00ffff0 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_CID1 +CYDEV_ROM_TABLE_CID1 EQU 0xe00ffff4 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_CID2 +CYDEV_ROM_TABLE_CID2 EQU 0xe00ffff8 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_CID3 +CYDEV_ROM_TABLE_CID3 EQU 0xe00ffffc + ENDIF + IF :LNOT::DEF:CYDEV_FLS_SIZE +CYDEV_FLS_SIZE EQU CYDEV_FLASH_SIZE + ENDIF + IF :LNOT::DEF:CYDEV_ECC_BASE +CYDEV_ECC_BASE EQU CYDEV_FLSECC_BASE + ENDIF + IF :LNOT::DEF:CYDEV_FLS_SECTOR_SIZE +CYDEV_FLS_SECTOR_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYDEV_FLS_ROW_SIZE +CYDEV_FLS_ROW_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_ECC_SECTOR_SIZE +CYDEV_ECC_SECTOR_SIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYDEV_ECC_ROW_SIZE +CYDEV_ECC_ROW_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_EEPROM_SECTOR_SIZE +CYDEV_EEPROM_SECTOR_SIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYDEV_EEPROM_ROW_SIZE +CYDEV_EEPROM_ROW_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PERIPH_BASE +CYDEV_PERIPH_BASE EQU CYDEV_CLKDIST_BASE + ENDIF + IF :LNOT::DEF:CYCLK_LD_DISABLE +CYCLK_LD_DISABLE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYCLK_LD_SYNC_EN +CYCLK_LD_SYNC_EN EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYCLK_LD_LOAD +CYCLK_LD_LOAD EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYCLK_PIPE +CYCLK_PIPE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYCLK_SSS +CYCLK_SSS EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYCLK_EARLY +CYCLK_EARLY EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYCLK_DUTY +CYCLK_DUTY EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYCLK_SYNC +CYCLK_SYNC EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_CLK_SYNC_D +CYCLK_SRC_SEL_CLK_SYNC_D EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_SYNC_DIG +CYCLK_SRC_SEL_SYNC_DIG EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_IMO +CYCLK_SRC_SEL_IMO EQU 1 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTAL_MHZ +CYCLK_SRC_SEL_XTAL_MHZ EQU 2 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTALM +CYCLK_SRC_SEL_XTALM EQU 2 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_ILO +CYCLK_SRC_SEL_ILO EQU 3 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_PLL +CYCLK_SRC_SEL_PLL EQU 4 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTAL_KHZ +CYCLK_SRC_SEL_XTAL_KHZ EQU 5 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTALK +CYCLK_SRC_SEL_XTALK EQU 5 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_G +CYCLK_SRC_SEL_DSI_G EQU 6 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_D +CYCLK_SRC_SEL_DSI_D EQU 7 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_CLK_SYNC_A +CYCLK_SRC_SEL_CLK_SYNC_A EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_A +CYCLK_SRC_SEL_DSI_A EQU 7 + ENDIF + END diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc new file mode 100755 index 00000000..790c65b5 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc @@ -0,0 +1,16039 @@ +; +; FILENAME: cydevicerv_trm.inc +; +; PSoC Creator 3.0 Component Pack 7 +; +; DESCRIPTION: +; This file provides all of the address values for the entire PSoC device. +; +;------------------------------------------------------------------------------- +; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + + IF :LNOT::DEF:CYDEV_FLASH_BASE +CYDEV_FLASH_BASE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLASH_SIZE +CYDEV_FLASH_SIZE EQU 0x00020000 + ENDIF + IF :LNOT::DEF:CYREG_FLASH_DATA_MBASE +CYREG_FLASH_DATA_MBASE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYREG_FLASH_DATA_MSIZE +CYREG_FLASH_DATA_MSIZE EQU 0x00020000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_BASE +CYDEV_SRAM_BASE EQU 0x1fffc000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_SIZE +CYDEV_SRAM_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE64K_MBASE +CYREG_SRAM_CODE64K_MBASE EQU 0x1fff8000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE64K_MSIZE +CYREG_SRAM_CODE64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE32K_MBASE +CYREG_SRAM_CODE32K_MBASE EQU 0x1fffc000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE32K_MSIZE +CYREG_SRAM_CODE32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE16K_MBASE +CYREG_SRAM_CODE16K_MBASE EQU 0x1fffe000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE16K_MSIZE +CYREG_SRAM_CODE16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE_MBASE +CYREG_SRAM_CODE_MBASE EQU 0x1fffc000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE_MSIZE +CYREG_SRAM_CODE_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA_MBASE +CYREG_SRAM_DATA_MBASE EQU 0x20000000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA_MSIZE +CYREG_SRAM_DATA_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA16K_MBASE +CYREG_SRAM_DATA16K_MBASE EQU 0x20001000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA16K_MSIZE +CYREG_SRAM_DATA16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA32K_MBASE +CYREG_SRAM_DATA32K_MBASE EQU 0x20002000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA32K_MSIZE +CYREG_SRAM_DATA32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA64K_MBASE +CYREG_SRAM_DATA64K_MBASE EQU 0x20004000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA64K_MSIZE +CYREG_SRAM_DATA64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_BASE +CYDEV_DMA_BASE EQU 0x20008000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SIZE +CYDEV_DMA_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM64K_MBASE +CYREG_DMA_SRAM64K_MBASE EQU 0x20008000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM64K_MSIZE +CYREG_DMA_SRAM64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM32K_MBASE +CYREG_DMA_SRAM32K_MBASE EQU 0x2000c000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM32K_MSIZE +CYREG_DMA_SRAM32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM16K_MBASE +CYREG_DMA_SRAM16K_MBASE EQU 0x2000e000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM16K_MSIZE +CYREG_DMA_SRAM16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM_MBASE +CYREG_DMA_SRAM_MBASE EQU 0x2000f000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM_MSIZE +CYREG_DMA_SRAM_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_BASE +CYDEV_CLKDIST_BASE EQU 0x40004000 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_SIZE +CYDEV_CLKDIST_SIZE EQU 0x00000110 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_CR +CYREG_CLKDIST_CR EQU 0x40004000 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_LD +CYREG_CLKDIST_LD EQU 0x40004001 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_WRK0 +CYREG_CLKDIST_WRK0 EQU 0x40004002 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_WRK1 +CYREG_CLKDIST_WRK1 EQU 0x40004003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_MSTR0 +CYREG_CLKDIST_MSTR0 EQU 0x40004004 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_MSTR1 +CYREG_CLKDIST_MSTR1 EQU 0x40004005 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_BCFG0 +CYREG_CLKDIST_BCFG0 EQU 0x40004006 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_BCFG1 +CYREG_CLKDIST_BCFG1 EQU 0x40004007 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_BCFG2 +CYREG_CLKDIST_BCFG2 EQU 0x40004008 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_UCFG +CYREG_CLKDIST_UCFG EQU 0x40004009 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DLY0 +CYREG_CLKDIST_DLY0 EQU 0x4000400a + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DLY1 +CYREG_CLKDIST_DLY1 EQU 0x4000400b + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DMASK +CYREG_CLKDIST_DMASK EQU 0x40004010 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_AMASK +CYREG_CLKDIST_AMASK EQU 0x40004014 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_BASE +CYDEV_CLKDIST_DCFG0_BASE EQU 0x40004080 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_SIZE +CYDEV_CLKDIST_DCFG0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG0_CFG0 +CYREG_CLKDIST_DCFG0_CFG0 EQU 0x40004080 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG0_CFG1 +CYREG_CLKDIST_DCFG0_CFG1 EQU 0x40004081 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG0_CFG2 +CYREG_CLKDIST_DCFG0_CFG2 EQU 0x40004082 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_BASE +CYDEV_CLKDIST_DCFG1_BASE EQU 0x40004084 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_SIZE +CYDEV_CLKDIST_DCFG1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG1_CFG0 +CYREG_CLKDIST_DCFG1_CFG0 EQU 0x40004084 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG1_CFG1 +CYREG_CLKDIST_DCFG1_CFG1 EQU 0x40004085 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG1_CFG2 +CYREG_CLKDIST_DCFG1_CFG2 EQU 0x40004086 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_BASE +CYDEV_CLKDIST_DCFG2_BASE EQU 0x40004088 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_SIZE +CYDEV_CLKDIST_DCFG2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG2_CFG0 +CYREG_CLKDIST_DCFG2_CFG0 EQU 0x40004088 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG2_CFG1 +CYREG_CLKDIST_DCFG2_CFG1 EQU 0x40004089 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG2_CFG2 +CYREG_CLKDIST_DCFG2_CFG2 EQU 0x4000408a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_BASE +CYDEV_CLKDIST_DCFG3_BASE EQU 0x4000408c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_SIZE +CYDEV_CLKDIST_DCFG3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG3_CFG0 +CYREG_CLKDIST_DCFG3_CFG0 EQU 0x4000408c + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG3_CFG1 +CYREG_CLKDIST_DCFG3_CFG1 EQU 0x4000408d + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG3_CFG2 +CYREG_CLKDIST_DCFG3_CFG2 EQU 0x4000408e + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_BASE +CYDEV_CLKDIST_DCFG4_BASE EQU 0x40004090 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_SIZE +CYDEV_CLKDIST_DCFG4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG4_CFG0 +CYREG_CLKDIST_DCFG4_CFG0 EQU 0x40004090 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG4_CFG1 +CYREG_CLKDIST_DCFG4_CFG1 EQU 0x40004091 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG4_CFG2 +CYREG_CLKDIST_DCFG4_CFG2 EQU 0x40004092 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_BASE +CYDEV_CLKDIST_DCFG5_BASE EQU 0x40004094 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_SIZE +CYDEV_CLKDIST_DCFG5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG5_CFG0 +CYREG_CLKDIST_DCFG5_CFG0 EQU 0x40004094 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG5_CFG1 +CYREG_CLKDIST_DCFG5_CFG1 EQU 0x40004095 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG5_CFG2 +CYREG_CLKDIST_DCFG5_CFG2 EQU 0x40004096 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_BASE +CYDEV_CLKDIST_DCFG6_BASE EQU 0x40004098 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_SIZE +CYDEV_CLKDIST_DCFG6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG6_CFG0 +CYREG_CLKDIST_DCFG6_CFG0 EQU 0x40004098 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG6_CFG1 +CYREG_CLKDIST_DCFG6_CFG1 EQU 0x40004099 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG6_CFG2 +CYREG_CLKDIST_DCFG6_CFG2 EQU 0x4000409a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_BASE +CYDEV_CLKDIST_DCFG7_BASE EQU 0x4000409c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_SIZE +CYDEV_CLKDIST_DCFG7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG7_CFG0 +CYREG_CLKDIST_DCFG7_CFG0 EQU 0x4000409c + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG7_CFG1 +CYREG_CLKDIST_DCFG7_CFG1 EQU 0x4000409d + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG7_CFG2 +CYREG_CLKDIST_DCFG7_CFG2 EQU 0x4000409e + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_BASE +CYDEV_CLKDIST_ACFG0_BASE EQU 0x40004100 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_SIZE +CYDEV_CLKDIST_ACFG0_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG0_CFG0 +CYREG_CLKDIST_ACFG0_CFG0 EQU 0x40004100 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG0_CFG1 +CYREG_CLKDIST_ACFG0_CFG1 EQU 0x40004101 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG0_CFG2 +CYREG_CLKDIST_ACFG0_CFG2 EQU 0x40004102 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG0_CFG3 +CYREG_CLKDIST_ACFG0_CFG3 EQU 0x40004103 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_BASE +CYDEV_CLKDIST_ACFG1_BASE EQU 0x40004104 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_SIZE +CYDEV_CLKDIST_ACFG1_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG1_CFG0 +CYREG_CLKDIST_ACFG1_CFG0 EQU 0x40004104 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG1_CFG1 +CYREG_CLKDIST_ACFG1_CFG1 EQU 0x40004105 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG1_CFG2 +CYREG_CLKDIST_ACFG1_CFG2 EQU 0x40004106 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG1_CFG3 +CYREG_CLKDIST_ACFG1_CFG3 EQU 0x40004107 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_BASE +CYDEV_CLKDIST_ACFG2_BASE EQU 0x40004108 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_SIZE +CYDEV_CLKDIST_ACFG2_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG2_CFG0 +CYREG_CLKDIST_ACFG2_CFG0 EQU 0x40004108 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG2_CFG1 +CYREG_CLKDIST_ACFG2_CFG1 EQU 0x40004109 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG2_CFG2 +CYREG_CLKDIST_ACFG2_CFG2 EQU 0x4000410a + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG2_CFG3 +CYREG_CLKDIST_ACFG2_CFG3 EQU 0x4000410b + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_BASE +CYDEV_CLKDIST_ACFG3_BASE EQU 0x4000410c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_SIZE +CYDEV_CLKDIST_ACFG3_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG3_CFG0 +CYREG_CLKDIST_ACFG3_CFG0 EQU 0x4000410c + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG3_CFG1 +CYREG_CLKDIST_ACFG3_CFG1 EQU 0x4000410d + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG3_CFG2 +CYREG_CLKDIST_ACFG3_CFG2 EQU 0x4000410e + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG3_CFG3 +CYREG_CLKDIST_ACFG3_CFG3 EQU 0x4000410f + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_BASE +CYDEV_FASTCLK_BASE EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_SIZE +CYDEV_FASTCLK_SIZE EQU 0x00000026 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_IMO_BASE +CYDEV_FASTCLK_IMO_BASE EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_IMO_SIZE +CYDEV_FASTCLK_IMO_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_IMO_CR +CYREG_FASTCLK_IMO_CR EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_BASE +CYDEV_FASTCLK_XMHZ_BASE EQU 0x40004210 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_SIZE +CYDEV_FASTCLK_XMHZ_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_XMHZ_CSR +CYREG_FASTCLK_XMHZ_CSR EQU 0x40004210 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_XMHZ_CFG0 +CYREG_FASTCLK_XMHZ_CFG0 EQU 0x40004212 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_XMHZ_CFG1 +CYREG_FASTCLK_XMHZ_CFG1 EQU 0x40004213 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_BASE +CYDEV_FASTCLK_PLL_BASE EQU 0x40004220 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_SIZE +CYDEV_FASTCLK_PLL_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_PLL_CFG0 +CYREG_FASTCLK_PLL_CFG0 EQU 0x40004220 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_PLL_CFG1 +CYREG_FASTCLK_PLL_CFG1 EQU 0x40004221 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_PLL_P +CYREG_FASTCLK_PLL_P EQU 0x40004222 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_PLL_Q +CYREG_FASTCLK_PLL_Q EQU 0x40004223 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_PLL_SR +CYREG_FASTCLK_PLL_SR EQU 0x40004225 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_BASE +CYDEV_SLOWCLK_BASE EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_SIZE +CYDEV_SLOWCLK_SIZE EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_BASE +CYDEV_SLOWCLK_ILO_BASE EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_SIZE +CYDEV_SLOWCLK_ILO_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_SLOWCLK_ILO_CR0 +CYREG_SLOWCLK_ILO_CR0 EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYREG_SLOWCLK_ILO_CR1 +CYREG_SLOWCLK_ILO_CR1 EQU 0x40004301 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_BASE +CYDEV_SLOWCLK_X32_BASE EQU 0x40004308 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_SIZE +CYDEV_SLOWCLK_X32_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SLOWCLK_X32_CR +CYREG_SLOWCLK_X32_CR EQU 0x40004308 + ENDIF + IF :LNOT::DEF:CYREG_SLOWCLK_X32_CFG +CYREG_SLOWCLK_X32_CFG EQU 0x40004309 + ENDIF + IF :LNOT::DEF:CYREG_SLOWCLK_X32_TST +CYREG_SLOWCLK_X32_TST EQU 0x4000430a + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_BASE +CYDEV_BOOST_BASE EQU 0x40004320 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_SIZE +CYDEV_BOOST_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_CR0 +CYREG_BOOST_CR0 EQU 0x40004320 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_CR1 +CYREG_BOOST_CR1 EQU 0x40004321 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_CR2 +CYREG_BOOST_CR2 EQU 0x40004322 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_CR3 +CYREG_BOOST_CR3 EQU 0x40004323 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_SR +CYREG_BOOST_SR EQU 0x40004324 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_CR4 +CYREG_BOOST_CR4 EQU 0x40004325 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_SR2 +CYREG_BOOST_SR2 EQU 0x40004326 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_BASE +CYDEV_PWRSYS_BASE EQU 0x40004330 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_SIZE +CYDEV_PWRSYS_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_CR0 +CYREG_PWRSYS_CR0 EQU 0x40004330 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_CR1 +CYREG_PWRSYS_CR1 EQU 0x40004331 + ENDIF + IF :LNOT::DEF:CYDEV_PM_BASE +CYDEV_PM_BASE EQU 0x40004380 + ENDIF + IF :LNOT::DEF:CYDEV_PM_SIZE +CYDEV_PM_SIZE EQU 0x00000057 + ENDIF + IF :LNOT::DEF:CYREG_PM_TW_CFG0 +CYREG_PM_TW_CFG0 EQU 0x40004380 + ENDIF + IF :LNOT::DEF:CYREG_PM_TW_CFG1 +CYREG_PM_TW_CFG1 EQU 0x40004381 + ENDIF + IF :LNOT::DEF:CYREG_PM_TW_CFG2 +CYREG_PM_TW_CFG2 EQU 0x40004382 + ENDIF + IF :LNOT::DEF:CYREG_PM_WDT_CFG +CYREG_PM_WDT_CFG EQU 0x40004383 + ENDIF + IF :LNOT::DEF:CYREG_PM_WDT_CR +CYREG_PM_WDT_CR EQU 0x40004384 + ENDIF + IF :LNOT::DEF:CYREG_PM_INT_SR +CYREG_PM_INT_SR EQU 0x40004390 + ENDIF + IF :LNOT::DEF:CYREG_PM_MODE_CFG0 +CYREG_PM_MODE_CFG0 EQU 0x40004391 + ENDIF + IF :LNOT::DEF:CYREG_PM_MODE_CFG1 +CYREG_PM_MODE_CFG1 EQU 0x40004392 + ENDIF + IF :LNOT::DEF:CYREG_PM_MODE_CSR +CYREG_PM_MODE_CSR EQU 0x40004393 + ENDIF + IF :LNOT::DEF:CYREG_PM_USB_CR0 +CYREG_PM_USB_CR0 EQU 0x40004394 + ENDIF + IF :LNOT::DEF:CYREG_PM_WAKEUP_CFG0 +CYREG_PM_WAKEUP_CFG0 EQU 0x40004398 + ENDIF + IF :LNOT::DEF:CYREG_PM_WAKEUP_CFG1 +CYREG_PM_WAKEUP_CFG1 EQU 0x40004399 + ENDIF + IF :LNOT::DEF:CYREG_PM_WAKEUP_CFG2 +CYREG_PM_WAKEUP_CFG2 EQU 0x4000439a + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_BASE +CYDEV_PM_ACT_BASE EQU 0x400043a0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_SIZE +CYDEV_PM_ACT_SIZE EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG0 +CYREG_PM_ACT_CFG0 EQU 0x400043a0 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG1 +CYREG_PM_ACT_CFG1 EQU 0x400043a1 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG2 +CYREG_PM_ACT_CFG2 EQU 0x400043a2 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG3 +CYREG_PM_ACT_CFG3 EQU 0x400043a3 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG4 +CYREG_PM_ACT_CFG4 EQU 0x400043a4 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG5 +CYREG_PM_ACT_CFG5 EQU 0x400043a5 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG6 +CYREG_PM_ACT_CFG6 EQU 0x400043a6 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG7 +CYREG_PM_ACT_CFG7 EQU 0x400043a7 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG8 +CYREG_PM_ACT_CFG8 EQU 0x400043a8 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG9 +CYREG_PM_ACT_CFG9 EQU 0x400043a9 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG10 +CYREG_PM_ACT_CFG10 EQU 0x400043aa + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG11 +CYREG_PM_ACT_CFG11 EQU 0x400043ab + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG12 +CYREG_PM_ACT_CFG12 EQU 0x400043ac + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG13 +CYREG_PM_ACT_CFG13 EQU 0x400043ad + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_BASE +CYDEV_PM_STBY_BASE EQU 0x400043b0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_SIZE +CYDEV_PM_STBY_SIZE EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG0 +CYREG_PM_STBY_CFG0 EQU 0x400043b0 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG1 +CYREG_PM_STBY_CFG1 EQU 0x400043b1 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG2 +CYREG_PM_STBY_CFG2 EQU 0x400043b2 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG3 +CYREG_PM_STBY_CFG3 EQU 0x400043b3 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG4 +CYREG_PM_STBY_CFG4 EQU 0x400043b4 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG5 +CYREG_PM_STBY_CFG5 EQU 0x400043b5 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG6 +CYREG_PM_STBY_CFG6 EQU 0x400043b6 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG7 +CYREG_PM_STBY_CFG7 EQU 0x400043b7 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG8 +CYREG_PM_STBY_CFG8 EQU 0x400043b8 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG9 +CYREG_PM_STBY_CFG9 EQU 0x400043b9 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG10 +CYREG_PM_STBY_CFG10 EQU 0x400043ba + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG11 +CYREG_PM_STBY_CFG11 EQU 0x400043bb + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG12 +CYREG_PM_STBY_CFG12 EQU 0x400043bc + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG13 +CYREG_PM_STBY_CFG13 EQU 0x400043bd + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_BASE +CYDEV_PM_AVAIL_BASE EQU 0x400043c0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SIZE +CYDEV_PM_AVAIL_SIZE EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR0 +CYREG_PM_AVAIL_CR0 EQU 0x400043c0 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR1 +CYREG_PM_AVAIL_CR1 EQU 0x400043c1 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR2 +CYREG_PM_AVAIL_CR2 EQU 0x400043c2 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR3 +CYREG_PM_AVAIL_CR3 EQU 0x400043c3 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR4 +CYREG_PM_AVAIL_CR4 EQU 0x400043c4 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR5 +CYREG_PM_AVAIL_CR5 EQU 0x400043c5 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR6 +CYREG_PM_AVAIL_CR6 EQU 0x400043c6 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR0 +CYREG_PM_AVAIL_SR0 EQU 0x400043d0 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR1 +CYREG_PM_AVAIL_SR1 EQU 0x400043d1 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR2 +CYREG_PM_AVAIL_SR2 EQU 0x400043d2 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR3 +CYREG_PM_AVAIL_SR3 EQU 0x400043d3 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR4 +CYREG_PM_AVAIL_SR4 EQU 0x400043d4 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR5 +CYREG_PM_AVAIL_SR5 EQU 0x400043d5 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR6 +CYREG_PM_AVAIL_SR6 EQU 0x400043d6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_BASE +CYDEV_PICU_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SIZE +CYDEV_PICU_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_BASE +CYDEV_PICU_INTTYPE_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_SIZE +CYDEV_PICU_INTTYPE_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_BASE +CYDEV_PICU_INTTYPE_PICU0_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_SIZE +CYDEV_PICU_INTTYPE_PICU0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE0 +CYREG_PICU0_INTTYPE0 EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE1 +CYREG_PICU0_INTTYPE1 EQU 0x40004501 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE2 +CYREG_PICU0_INTTYPE2 EQU 0x40004502 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE3 +CYREG_PICU0_INTTYPE3 EQU 0x40004503 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE4 +CYREG_PICU0_INTTYPE4 EQU 0x40004504 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE5 +CYREG_PICU0_INTTYPE5 EQU 0x40004505 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE6 +CYREG_PICU0_INTTYPE6 EQU 0x40004506 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE7 +CYREG_PICU0_INTTYPE7 EQU 0x40004507 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_BASE +CYDEV_PICU_INTTYPE_PICU1_BASE EQU 0x40004508 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_SIZE +CYDEV_PICU_INTTYPE_PICU1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE0 +CYREG_PICU1_INTTYPE0 EQU 0x40004508 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE1 +CYREG_PICU1_INTTYPE1 EQU 0x40004509 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE2 +CYREG_PICU1_INTTYPE2 EQU 0x4000450a + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE3 +CYREG_PICU1_INTTYPE3 EQU 0x4000450b + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE4 +CYREG_PICU1_INTTYPE4 EQU 0x4000450c + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE5 +CYREG_PICU1_INTTYPE5 EQU 0x4000450d + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE6 +CYREG_PICU1_INTTYPE6 EQU 0x4000450e + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE7 +CYREG_PICU1_INTTYPE7 EQU 0x4000450f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_BASE +CYDEV_PICU_INTTYPE_PICU2_BASE EQU 0x40004510 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_SIZE +CYDEV_PICU_INTTYPE_PICU2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE0 +CYREG_PICU2_INTTYPE0 EQU 0x40004510 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE1 +CYREG_PICU2_INTTYPE1 EQU 0x40004511 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE2 +CYREG_PICU2_INTTYPE2 EQU 0x40004512 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE3 +CYREG_PICU2_INTTYPE3 EQU 0x40004513 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE4 +CYREG_PICU2_INTTYPE4 EQU 0x40004514 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE5 +CYREG_PICU2_INTTYPE5 EQU 0x40004515 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE6 +CYREG_PICU2_INTTYPE6 EQU 0x40004516 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE7 +CYREG_PICU2_INTTYPE7 EQU 0x40004517 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_BASE +CYDEV_PICU_INTTYPE_PICU3_BASE EQU 0x40004518 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_SIZE +CYDEV_PICU_INTTYPE_PICU3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE0 +CYREG_PICU3_INTTYPE0 EQU 0x40004518 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE1 +CYREG_PICU3_INTTYPE1 EQU 0x40004519 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE2 +CYREG_PICU3_INTTYPE2 EQU 0x4000451a + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE3 +CYREG_PICU3_INTTYPE3 EQU 0x4000451b + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE4 +CYREG_PICU3_INTTYPE4 EQU 0x4000451c + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE5 +CYREG_PICU3_INTTYPE5 EQU 0x4000451d + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE6 +CYREG_PICU3_INTTYPE6 EQU 0x4000451e + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE7 +CYREG_PICU3_INTTYPE7 EQU 0x4000451f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_BASE +CYDEV_PICU_INTTYPE_PICU4_BASE EQU 0x40004520 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_SIZE +CYDEV_PICU_INTTYPE_PICU4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE0 +CYREG_PICU4_INTTYPE0 EQU 0x40004520 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE1 +CYREG_PICU4_INTTYPE1 EQU 0x40004521 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE2 +CYREG_PICU4_INTTYPE2 EQU 0x40004522 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE3 +CYREG_PICU4_INTTYPE3 EQU 0x40004523 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE4 +CYREG_PICU4_INTTYPE4 EQU 0x40004524 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE5 +CYREG_PICU4_INTTYPE5 EQU 0x40004525 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE6 +CYREG_PICU4_INTTYPE6 EQU 0x40004526 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE7 +CYREG_PICU4_INTTYPE7 EQU 0x40004527 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_BASE +CYDEV_PICU_INTTYPE_PICU5_BASE EQU 0x40004528 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_SIZE +CYDEV_PICU_INTTYPE_PICU5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE0 +CYREG_PICU5_INTTYPE0 EQU 0x40004528 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE1 +CYREG_PICU5_INTTYPE1 EQU 0x40004529 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE2 +CYREG_PICU5_INTTYPE2 EQU 0x4000452a + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE3 +CYREG_PICU5_INTTYPE3 EQU 0x4000452b + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE4 +CYREG_PICU5_INTTYPE4 EQU 0x4000452c + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE5 +CYREG_PICU5_INTTYPE5 EQU 0x4000452d + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE6 +CYREG_PICU5_INTTYPE6 EQU 0x4000452e + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE7 +CYREG_PICU5_INTTYPE7 EQU 0x4000452f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_BASE +CYDEV_PICU_INTTYPE_PICU6_BASE EQU 0x40004530 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_SIZE +CYDEV_PICU_INTTYPE_PICU6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE0 +CYREG_PICU6_INTTYPE0 EQU 0x40004530 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE1 +CYREG_PICU6_INTTYPE1 EQU 0x40004531 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE2 +CYREG_PICU6_INTTYPE2 EQU 0x40004532 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE3 +CYREG_PICU6_INTTYPE3 EQU 0x40004533 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE4 +CYREG_PICU6_INTTYPE4 EQU 0x40004534 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE5 +CYREG_PICU6_INTTYPE5 EQU 0x40004535 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE6 +CYREG_PICU6_INTTYPE6 EQU 0x40004536 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE7 +CYREG_PICU6_INTTYPE7 EQU 0x40004537 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_BASE +CYDEV_PICU_INTTYPE_PICU12_BASE EQU 0x40004560 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_SIZE +CYDEV_PICU_INTTYPE_PICU12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE0 +CYREG_PICU12_INTTYPE0 EQU 0x40004560 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE1 +CYREG_PICU12_INTTYPE1 EQU 0x40004561 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE2 +CYREG_PICU12_INTTYPE2 EQU 0x40004562 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE3 +CYREG_PICU12_INTTYPE3 EQU 0x40004563 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE4 +CYREG_PICU12_INTTYPE4 EQU 0x40004564 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE5 +CYREG_PICU12_INTTYPE5 EQU 0x40004565 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE6 +CYREG_PICU12_INTTYPE6 EQU 0x40004566 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE7 +CYREG_PICU12_INTTYPE7 EQU 0x40004567 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_BASE +CYDEV_PICU_INTTYPE_PICU15_BASE EQU 0x40004578 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_SIZE +CYDEV_PICU_INTTYPE_PICU15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE0 +CYREG_PICU15_INTTYPE0 EQU 0x40004578 + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE1 +CYREG_PICU15_INTTYPE1 EQU 0x40004579 + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE2 +CYREG_PICU15_INTTYPE2 EQU 0x4000457a + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE3 +CYREG_PICU15_INTTYPE3 EQU 0x4000457b + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE4 +CYREG_PICU15_INTTYPE4 EQU 0x4000457c + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE5 +CYREG_PICU15_INTTYPE5 EQU 0x4000457d + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE6 +CYREG_PICU15_INTTYPE6 EQU 0x4000457e + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE7 +CYREG_PICU15_INTTYPE7 EQU 0x4000457f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_BASE +CYDEV_PICU_STAT_BASE EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_SIZE +CYDEV_PICU_STAT_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_BASE +CYDEV_PICU_STAT_PICU0_BASE EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_SIZE +CYDEV_PICU_STAT_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTSTAT +CYREG_PICU0_INTSTAT EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_BASE +CYDEV_PICU_STAT_PICU1_BASE EQU 0x40004581 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_SIZE +CYDEV_PICU_STAT_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTSTAT +CYREG_PICU1_INTSTAT EQU 0x40004581 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_BASE +CYDEV_PICU_STAT_PICU2_BASE EQU 0x40004582 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_SIZE +CYDEV_PICU_STAT_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTSTAT +CYREG_PICU2_INTSTAT EQU 0x40004582 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_BASE +CYDEV_PICU_STAT_PICU3_BASE EQU 0x40004583 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_SIZE +CYDEV_PICU_STAT_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTSTAT +CYREG_PICU3_INTSTAT EQU 0x40004583 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_BASE +CYDEV_PICU_STAT_PICU4_BASE EQU 0x40004584 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_SIZE +CYDEV_PICU_STAT_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTSTAT +CYREG_PICU4_INTSTAT EQU 0x40004584 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_BASE +CYDEV_PICU_STAT_PICU5_BASE EQU 0x40004585 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_SIZE +CYDEV_PICU_STAT_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTSTAT +CYREG_PICU5_INTSTAT EQU 0x40004585 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_BASE +CYDEV_PICU_STAT_PICU6_BASE EQU 0x40004586 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_SIZE +CYDEV_PICU_STAT_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTSTAT +CYREG_PICU6_INTSTAT EQU 0x40004586 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_BASE +CYDEV_PICU_STAT_PICU12_BASE EQU 0x4000458c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_SIZE +CYDEV_PICU_STAT_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTSTAT +CYREG_PICU12_INTSTAT EQU 0x4000458c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_BASE +CYDEV_PICU_STAT_PICU15_BASE EQU 0x4000458f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_SIZE +CYDEV_PICU_STAT_PICU15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTSTAT +CYREG_PICU15_INTSTAT EQU 0x4000458f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_BASE +CYDEV_PICU_SNAP_BASE EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_SIZE +CYDEV_PICU_SNAP_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_BASE +CYDEV_PICU_SNAP_PICU0_BASE EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_SIZE +CYDEV_PICU_SNAP_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_SNAP +CYREG_PICU0_SNAP EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_BASE +CYDEV_PICU_SNAP_PICU1_BASE EQU 0x40004591 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_SIZE +CYDEV_PICU_SNAP_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_SNAP +CYREG_PICU1_SNAP EQU 0x40004591 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_BASE +CYDEV_PICU_SNAP_PICU2_BASE EQU 0x40004592 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_SIZE +CYDEV_PICU_SNAP_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_SNAP +CYREG_PICU2_SNAP EQU 0x40004592 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_BASE +CYDEV_PICU_SNAP_PICU3_BASE EQU 0x40004593 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_SIZE +CYDEV_PICU_SNAP_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_SNAP +CYREG_PICU3_SNAP EQU 0x40004593 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_BASE +CYDEV_PICU_SNAP_PICU4_BASE EQU 0x40004594 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_SIZE +CYDEV_PICU_SNAP_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_SNAP +CYREG_PICU4_SNAP EQU 0x40004594 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_BASE +CYDEV_PICU_SNAP_PICU5_BASE EQU 0x40004595 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_SIZE +CYDEV_PICU_SNAP_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_SNAP +CYREG_PICU5_SNAP EQU 0x40004595 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_BASE +CYDEV_PICU_SNAP_PICU6_BASE EQU 0x40004596 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_SIZE +CYDEV_PICU_SNAP_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_SNAP +CYREG_PICU6_SNAP EQU 0x40004596 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_BASE +CYDEV_PICU_SNAP_PICU12_BASE EQU 0x4000459c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_SIZE +CYDEV_PICU_SNAP_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_SNAP +CYREG_PICU12_SNAP EQU 0x4000459c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_BASE +CYDEV_PICU_SNAP_PICU_15_BASE EQU 0x4000459f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_SIZE +CYDEV_PICU_SNAP_PICU_15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU_15_SNAP_15 +CYREG_PICU_15_SNAP_15 EQU 0x4000459f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_BASE +CYDEV_PICU_DISABLE_COR_BASE EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_SIZE +CYDEV_PICU_DISABLE_COR_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_BASE +CYDEV_PICU_DISABLE_COR_PICU0_BASE EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_SIZE +CYDEV_PICU_DISABLE_COR_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_DISABLE_COR +CYREG_PICU0_DISABLE_COR EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_BASE +CYDEV_PICU_DISABLE_COR_PICU1_BASE EQU 0x400045a1 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_SIZE +CYDEV_PICU_DISABLE_COR_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_DISABLE_COR +CYREG_PICU1_DISABLE_COR EQU 0x400045a1 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_BASE +CYDEV_PICU_DISABLE_COR_PICU2_BASE EQU 0x400045a2 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_SIZE +CYDEV_PICU_DISABLE_COR_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_DISABLE_COR +CYREG_PICU2_DISABLE_COR EQU 0x400045a2 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_BASE +CYDEV_PICU_DISABLE_COR_PICU3_BASE EQU 0x400045a3 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_SIZE +CYDEV_PICU_DISABLE_COR_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_DISABLE_COR +CYREG_PICU3_DISABLE_COR EQU 0x400045a3 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_BASE +CYDEV_PICU_DISABLE_COR_PICU4_BASE EQU 0x400045a4 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_SIZE +CYDEV_PICU_DISABLE_COR_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_DISABLE_COR +CYREG_PICU4_DISABLE_COR EQU 0x400045a4 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_BASE +CYDEV_PICU_DISABLE_COR_PICU5_BASE EQU 0x400045a5 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_SIZE +CYDEV_PICU_DISABLE_COR_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_DISABLE_COR +CYREG_PICU5_DISABLE_COR EQU 0x400045a5 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_BASE +CYDEV_PICU_DISABLE_COR_PICU6_BASE EQU 0x400045a6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_SIZE +CYDEV_PICU_DISABLE_COR_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_DISABLE_COR +CYREG_PICU6_DISABLE_COR EQU 0x400045a6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_BASE +CYDEV_PICU_DISABLE_COR_PICU12_BASE EQU 0x400045ac + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_SIZE +CYDEV_PICU_DISABLE_COR_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_DISABLE_COR +CYREG_PICU12_DISABLE_COR EQU 0x400045ac + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_BASE +CYDEV_PICU_DISABLE_COR_PICU15_BASE EQU 0x400045af + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_SIZE +CYDEV_PICU_DISABLE_COR_PICU15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU15_DISABLE_COR +CYREG_PICU15_DISABLE_COR EQU 0x400045af + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_BASE +CYDEV_MFGCFG_BASE EQU 0x40004600 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_SIZE +CYDEV_MFGCFG_SIZE EQU 0x000000ed + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_BASE +CYDEV_MFGCFG_ANAIF_BASE EQU 0x40004600 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SIZE +CYDEV_MFGCFG_ANAIF_SIZE EQU 0x00000038 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_BASE +CYDEV_MFGCFG_ANAIF_DAC0_BASE EQU 0x40004608 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_SIZE +CYDEV_MFGCFG_ANAIF_DAC0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_TR +CYREG_DAC0_TR EQU 0x40004608 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_BASE +CYDEV_MFGCFG_ANAIF_DAC1_BASE EQU 0x40004609 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_SIZE +CYDEV_MFGCFG_ANAIF_DAC1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_TR +CYREG_DAC1_TR EQU 0x40004609 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_BASE +CYDEV_MFGCFG_ANAIF_DAC2_BASE EQU 0x4000460a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_SIZE +CYDEV_MFGCFG_ANAIF_DAC2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_TR +CYREG_DAC2_TR EQU 0x4000460a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_BASE +CYDEV_MFGCFG_ANAIF_DAC3_BASE EQU 0x4000460b + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_SIZE +CYDEV_MFGCFG_ANAIF_DAC3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC3_TR +CYREG_DAC3_TR EQU 0x4000460b + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE EQU 0x40004610 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_NPUMP_DSM_TR0 +CYREG_NPUMP_DSM_TR0 EQU 0x40004610 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE EQU 0x40004611 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_NPUMP_SC_TR0 +CYREG_NPUMP_SC_TR0 EQU 0x40004611 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE EQU 0x40004612 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_NPUMP_OPAMP_TR0 +CYREG_NPUMP_OPAMP_TR0 EQU 0x40004612 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_BASE +CYDEV_MFGCFG_ANAIF_SAR0_BASE EQU 0x40004614 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_SIZE +CYDEV_MFGCFG_ANAIF_SAR0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_TR0 +CYREG_SAR0_TR0 EQU 0x40004614 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_BASE +CYDEV_MFGCFG_ANAIF_SAR1_BASE EQU 0x40004616 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_SIZE +CYDEV_MFGCFG_ANAIF_SAR1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_TR0 +CYREG_SAR1_TR0 EQU 0x40004616 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_BASE +CYDEV_MFGCFG_ANAIF_OPAMP0_BASE EQU 0x40004620 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_TR0 +CYREG_OPAMP0_TR0 EQU 0x40004620 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_TR1 +CYREG_OPAMP0_TR1 EQU 0x40004621 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_BASE +CYDEV_MFGCFG_ANAIF_OPAMP1_BASE EQU 0x40004622 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_TR0 +CYREG_OPAMP1_TR0 EQU 0x40004622 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_TR1 +CYREG_OPAMP1_TR1 EQU 0x40004623 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_BASE +CYDEV_MFGCFG_ANAIF_OPAMP2_BASE EQU 0x40004624 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_TR0 +CYREG_OPAMP2_TR0 EQU 0x40004624 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_TR1 +CYREG_OPAMP2_TR1 EQU 0x40004625 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_BASE +CYDEV_MFGCFG_ANAIF_OPAMP3_BASE EQU 0x40004626 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_TR0 +CYREG_OPAMP3_TR0 EQU 0x40004626 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_TR1 +CYREG_OPAMP3_TR1 EQU 0x40004627 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_BASE +CYDEV_MFGCFG_ANAIF_CMP0_BASE EQU 0x40004630 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_SIZE +CYDEV_MFGCFG_ANAIF_CMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_TR0 +CYREG_CMP0_TR0 EQU 0x40004630 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_TR1 +CYREG_CMP0_TR1 EQU 0x40004631 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_BASE +CYDEV_MFGCFG_ANAIF_CMP1_BASE EQU 0x40004632 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_SIZE +CYDEV_MFGCFG_ANAIF_CMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CMP1_TR0 +CYREG_CMP1_TR0 EQU 0x40004632 + ENDIF + IF :LNOT::DEF:CYREG_CMP1_TR1 +CYREG_CMP1_TR1 EQU 0x40004633 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_BASE +CYDEV_MFGCFG_ANAIF_CMP2_BASE EQU 0x40004634 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_SIZE +CYDEV_MFGCFG_ANAIF_CMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_TR0 +CYREG_CMP2_TR0 EQU 0x40004634 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_TR1 +CYREG_CMP2_TR1 EQU 0x40004635 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_BASE +CYDEV_MFGCFG_ANAIF_CMP3_BASE EQU 0x40004636 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_SIZE +CYDEV_MFGCFG_ANAIF_CMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CMP3_TR0 +CYREG_CMP3_TR0 EQU 0x40004636 + ENDIF + IF :LNOT::DEF:CYREG_CMP3_TR1 +CYREG_CMP3_TR1 EQU 0x40004637 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BASE +CYDEV_MFGCFG_PWRSYS_BASE EQU 0x40004680 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_SIZE +CYDEV_MFGCFG_PWRSYS_SIZE EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_HIB_TR0 +CYREG_PWRSYS_HIB_TR0 EQU 0x40004680 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_HIB_TR1 +CYREG_PWRSYS_HIB_TR1 EQU 0x40004681 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_I2C_TR +CYREG_PWRSYS_I2C_TR EQU 0x40004682 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_SLP_TR +CYREG_PWRSYS_SLP_TR EQU 0x40004683 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_BUZZ_TR +CYREG_PWRSYS_BUZZ_TR EQU 0x40004684 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_WAKE_TR0 +CYREG_PWRSYS_WAKE_TR0 EQU 0x40004685 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_WAKE_TR1 +CYREG_PWRSYS_WAKE_TR1 EQU 0x40004686 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_BREF_TR +CYREG_PWRSYS_BREF_TR EQU 0x40004687 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_BG_TR +CYREG_PWRSYS_BG_TR EQU 0x40004688 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_WAKE_TR2 +CYREG_PWRSYS_WAKE_TR2 EQU 0x40004689 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_WAKE_TR3 +CYREG_PWRSYS_WAKE_TR3 EQU 0x4000468a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_BASE +CYDEV_MFGCFG_ILO_BASE EQU 0x40004690 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_SIZE +CYDEV_MFGCFG_ILO_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_ILO_TR0 +CYREG_ILO_TR0 EQU 0x40004690 + ENDIF + IF :LNOT::DEF:CYREG_ILO_TR1 +CYREG_ILO_TR1 EQU 0x40004691 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_X32_BASE +CYDEV_MFGCFG_X32_BASE EQU 0x40004698 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_X32_SIZE +CYDEV_MFGCFG_X32_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_X32_TR +CYREG_X32_TR EQU 0x40004698 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_BASE +CYDEV_MFGCFG_IMO_BASE EQU 0x400046a0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_SIZE +CYDEV_MFGCFG_IMO_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_IMO_TR0 +CYREG_IMO_TR0 EQU 0x400046a0 + ENDIF + IF :LNOT::DEF:CYREG_IMO_TR1 +CYREG_IMO_TR1 EQU 0x400046a1 + ENDIF + IF :LNOT::DEF:CYREG_IMO_GAIN +CYREG_IMO_GAIN EQU 0x400046a2 + ENDIF + IF :LNOT::DEF:CYREG_IMO_C36M +CYREG_IMO_C36M EQU 0x400046a3 + ENDIF + IF :LNOT::DEF:CYREG_IMO_TR2 +CYREG_IMO_TR2 EQU 0x400046a4 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_BASE +CYDEV_MFGCFG_XMHZ_BASE EQU 0x400046a8 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_SIZE +CYDEV_MFGCFG_XMHZ_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_XMHZ_TR +CYREG_XMHZ_TR EQU 0x400046a8 + ENDIF + IF :LNOT::DEF:CYREG_MFGCFG_DLY +CYREG_MFGCFG_DLY EQU 0x400046c0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_BASE +CYDEV_MFGCFG_MLOGIC_BASE EQU 0x400046e0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SIZE +CYDEV_MFGCFG_MLOGIC_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_DMPSTR +CYREG_MLOGIC_DMPSTR EQU 0x400046e2 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_BASE +CYDEV_MFGCFG_MLOGIC_SEG_BASE EQU 0x400046e4 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_SIZE +CYDEV_MFGCFG_MLOGIC_SEG_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_SEG_CR +CYREG_MLOGIC_SEG_CR EQU 0x400046e4 + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_SEG_CFG0 +CYREG_MLOGIC_SEG_CFG0 EQU 0x400046e5 + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_DEBUG +CYREG_MLOGIC_DEBUG EQU 0x400046e8 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE +CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE EQU 0x400046ea + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE +CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_CPU_SCR_CPU_SCR +CYREG_MLOGIC_CPU_SCR_CPU_SCR EQU 0x400046ea + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_REV_ID +CYREG_MLOGIC_REV_ID EQU 0x400046ec + ENDIF + IF :LNOT::DEF:CYDEV_RESET_BASE +CYDEV_RESET_BASE EQU 0x400046f0 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SIZE +CYDEV_RESET_SIZE EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYREG_RESET_IPOR_CR0 +CYREG_RESET_IPOR_CR0 EQU 0x400046f0 + ENDIF + IF :LNOT::DEF:CYREG_RESET_IPOR_CR1 +CYREG_RESET_IPOR_CR1 EQU 0x400046f1 + ENDIF + IF :LNOT::DEF:CYREG_RESET_IPOR_CR2 +CYREG_RESET_IPOR_CR2 EQU 0x400046f2 + ENDIF + IF :LNOT::DEF:CYREG_RESET_IPOR_CR3 +CYREG_RESET_IPOR_CR3 EQU 0x400046f3 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR0 +CYREG_RESET_CR0 EQU 0x400046f4 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR1 +CYREG_RESET_CR1 EQU 0x400046f5 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR2 +CYREG_RESET_CR2 EQU 0x400046f6 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR3 +CYREG_RESET_CR3 EQU 0x400046f7 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR4 +CYREG_RESET_CR4 EQU 0x400046f8 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR5 +CYREG_RESET_CR5 EQU 0x400046f9 + ENDIF + IF :LNOT::DEF:CYREG_RESET_SR0 +CYREG_RESET_SR0 EQU 0x400046fa + ENDIF + IF :LNOT::DEF:CYREG_RESET_SR1 +CYREG_RESET_SR1 EQU 0x400046fb + ENDIF + IF :LNOT::DEF:CYREG_RESET_SR2 +CYREG_RESET_SR2 EQU 0x400046fc + ENDIF + IF :LNOT::DEF:CYREG_RESET_SR3 +CYREG_RESET_SR3 EQU 0x400046fd + ENDIF + IF :LNOT::DEF:CYREG_RESET_TR +CYREG_RESET_TR EQU 0x400046fe + ENDIF + IF :LNOT::DEF:CYDEV_SPC_BASE +CYDEV_SPC_BASE EQU 0x40004700 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_SIZE +CYDEV_SPC_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_SPC_FM_EE_CR +CYREG_SPC_FM_EE_CR EQU 0x40004700 + ENDIF + IF :LNOT::DEF:CYREG_SPC_FM_EE_WAKE_CNT +CYREG_SPC_FM_EE_WAKE_CNT EQU 0x40004701 + ENDIF + IF :LNOT::DEF:CYREG_SPC_EE_SCR +CYREG_SPC_EE_SCR EQU 0x40004702 + ENDIF + IF :LNOT::DEF:CYREG_SPC_EE_ERR +CYREG_SPC_EE_ERR EQU 0x40004703 + ENDIF + IF :LNOT::DEF:CYREG_SPC_CPU_DATA +CYREG_SPC_CPU_DATA EQU 0x40004720 + ENDIF + IF :LNOT::DEF:CYREG_SPC_DMA_DATA +CYREG_SPC_DMA_DATA EQU 0x40004721 + ENDIF + IF :LNOT::DEF:CYREG_SPC_SR +CYREG_SPC_SR EQU 0x40004722 + ENDIF + IF :LNOT::DEF:CYREG_SPC_CR +CYREG_SPC_CR EQU 0x40004723 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_BASE +CYDEV_SPC_DMM_MAP_BASE EQU 0x40004780 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_SIZE +CYDEV_SPC_DMM_MAP_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYREG_SPC_DMM_MAP_SRAM_MBASE +CYREG_SPC_DMM_MAP_SRAM_MBASE EQU 0x40004780 + ENDIF + IF :LNOT::DEF:CYREG_SPC_DMM_MAP_SRAM_MSIZE +CYREG_SPC_DMM_MAP_SRAM_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_BASE +CYDEV_CACHE_BASE EQU 0x40004800 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_SIZE +CYDEV_CACHE_SIZE EQU 0x0000009c + ENDIF + IF :LNOT::DEF:CYREG_CACHE_CC_CTL +CYREG_CACHE_CC_CTL EQU 0x40004800 + ENDIF + IF :LNOT::DEF:CYREG_CACHE_ECC_CORR +CYREG_CACHE_ECC_CORR EQU 0x40004880 + ENDIF + IF :LNOT::DEF:CYREG_CACHE_ECC_ERR +CYREG_CACHE_ECC_ERR EQU 0x40004888 + ENDIF + IF :LNOT::DEF:CYREG_CACHE_FLASH_ERR +CYREG_CACHE_FLASH_ERR EQU 0x40004890 + ENDIF + IF :LNOT::DEF:CYREG_CACHE_HITMISS +CYREG_CACHE_HITMISS EQU 0x40004898 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_BASE +CYDEV_I2C_BASE EQU 0x40004900 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_SIZE +CYDEV_I2C_SIZE EQU 0x000000e1 + ENDIF + IF :LNOT::DEF:CYREG_I2C_XCFG +CYREG_I2C_XCFG EQU 0x400049c8 + ENDIF + IF :LNOT::DEF:CYREG_I2C_ADR +CYREG_I2C_ADR EQU 0x400049ca + ENDIF + IF :LNOT::DEF:CYREG_I2C_CFG +CYREG_I2C_CFG EQU 0x400049d6 + ENDIF + IF :LNOT::DEF:CYREG_I2C_CSR +CYREG_I2C_CSR EQU 0x400049d7 + ENDIF + IF :LNOT::DEF:CYREG_I2C_D +CYREG_I2C_D EQU 0x400049d8 + ENDIF + IF :LNOT::DEF:CYREG_I2C_MCSR +CYREG_I2C_MCSR EQU 0x400049d9 + ENDIF + IF :LNOT::DEF:CYREG_I2C_CLK_DIV1 +CYREG_I2C_CLK_DIV1 EQU 0x400049db + ENDIF + IF :LNOT::DEF:CYREG_I2C_CLK_DIV2 +CYREG_I2C_CLK_DIV2 EQU 0x400049dc + ENDIF + IF :LNOT::DEF:CYREG_I2C_TMOUT_CSR +CYREG_I2C_TMOUT_CSR EQU 0x400049dd + ENDIF + IF :LNOT::DEF:CYREG_I2C_TMOUT_SR +CYREG_I2C_TMOUT_SR EQU 0x400049de + ENDIF + IF :LNOT::DEF:CYREG_I2C_TMOUT_CFG0 +CYREG_I2C_TMOUT_CFG0 EQU 0x400049df + ENDIF + IF :LNOT::DEF:CYREG_I2C_TMOUT_CFG1 +CYREG_I2C_TMOUT_CFG1 EQU 0x400049e0 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_BASE +CYDEV_DEC_BASE EQU 0x40004e00 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_SIZE +CYDEV_DEC_SIZE EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYREG_DEC_CR +CYREG_DEC_CR EQU 0x40004e00 + ENDIF + IF :LNOT::DEF:CYREG_DEC_SR +CYREG_DEC_SR EQU 0x40004e01 + ENDIF + IF :LNOT::DEF:CYREG_DEC_SHIFT1 +CYREG_DEC_SHIFT1 EQU 0x40004e02 + ENDIF + IF :LNOT::DEF:CYREG_DEC_SHIFT2 +CYREG_DEC_SHIFT2 EQU 0x40004e03 + ENDIF + IF :LNOT::DEF:CYREG_DEC_DR2 +CYREG_DEC_DR2 EQU 0x40004e04 + ENDIF + IF :LNOT::DEF:CYREG_DEC_DR2H +CYREG_DEC_DR2H EQU 0x40004e05 + ENDIF + IF :LNOT::DEF:CYREG_DEC_DR1 +CYREG_DEC_DR1 EQU 0x40004e06 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OCOR +CYREG_DEC_OCOR EQU 0x40004e08 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OCORM +CYREG_DEC_OCORM EQU 0x40004e09 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OCORH +CYREG_DEC_OCORH EQU 0x40004e0a + ENDIF + IF :LNOT::DEF:CYREG_DEC_GCOR +CYREG_DEC_GCOR EQU 0x40004e0c + ENDIF + IF :LNOT::DEF:CYREG_DEC_GCORH +CYREG_DEC_GCORH EQU 0x40004e0d + ENDIF + IF :LNOT::DEF:CYREG_DEC_GVAL +CYREG_DEC_GVAL EQU 0x40004e0e + ENDIF + IF :LNOT::DEF:CYREG_DEC_OUTSAMP +CYREG_DEC_OUTSAMP EQU 0x40004e10 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OUTSAMPM +CYREG_DEC_OUTSAMPM EQU 0x40004e11 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OUTSAMPH +CYREG_DEC_OUTSAMPH EQU 0x40004e12 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OUTSAMPS +CYREG_DEC_OUTSAMPS EQU 0x40004e13 + ENDIF + IF :LNOT::DEF:CYREG_DEC_COHER +CYREG_DEC_COHER EQU 0x40004e14 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_BASE +CYDEV_TMR0_BASE EQU 0x40004f00 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_SIZE +CYDEV_TMR0_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CFG0 +CYREG_TMR0_CFG0 EQU 0x40004f00 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CFG1 +CYREG_TMR0_CFG1 EQU 0x40004f01 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CFG2 +CYREG_TMR0_CFG2 EQU 0x40004f02 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_SR0 +CYREG_TMR0_SR0 EQU 0x40004f03 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_PER0 +CYREG_TMR0_PER0 EQU 0x40004f04 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_PER1 +CYREG_TMR0_PER1 EQU 0x40004f05 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CNT_CMP0 +CYREG_TMR0_CNT_CMP0 EQU 0x40004f06 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CNT_CMP1 +CYREG_TMR0_CNT_CMP1 EQU 0x40004f07 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CAP0 +CYREG_TMR0_CAP0 EQU 0x40004f08 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CAP1 +CYREG_TMR0_CAP1 EQU 0x40004f09 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_RT0 +CYREG_TMR0_RT0 EQU 0x40004f0a + ENDIF + IF :LNOT::DEF:CYREG_TMR0_RT1 +CYREG_TMR0_RT1 EQU 0x40004f0b + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_BASE +CYDEV_TMR1_BASE EQU 0x40004f0c + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_SIZE +CYDEV_TMR1_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CFG0 +CYREG_TMR1_CFG0 EQU 0x40004f0c + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CFG1 +CYREG_TMR1_CFG1 EQU 0x40004f0d + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CFG2 +CYREG_TMR1_CFG2 EQU 0x40004f0e + ENDIF + IF :LNOT::DEF:CYREG_TMR1_SR0 +CYREG_TMR1_SR0 EQU 0x40004f0f + ENDIF + IF :LNOT::DEF:CYREG_TMR1_PER0 +CYREG_TMR1_PER0 EQU 0x40004f10 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_PER1 +CYREG_TMR1_PER1 EQU 0x40004f11 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CNT_CMP0 +CYREG_TMR1_CNT_CMP0 EQU 0x40004f12 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CNT_CMP1 +CYREG_TMR1_CNT_CMP1 EQU 0x40004f13 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CAP0 +CYREG_TMR1_CAP0 EQU 0x40004f14 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CAP1 +CYREG_TMR1_CAP1 EQU 0x40004f15 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_RT0 +CYREG_TMR1_RT0 EQU 0x40004f16 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_RT1 +CYREG_TMR1_RT1 EQU 0x40004f17 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_BASE +CYDEV_TMR2_BASE EQU 0x40004f18 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_SIZE +CYDEV_TMR2_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CFG0 +CYREG_TMR2_CFG0 EQU 0x40004f18 + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CFG1 +CYREG_TMR2_CFG1 EQU 0x40004f19 + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CFG2 +CYREG_TMR2_CFG2 EQU 0x40004f1a + ENDIF + IF :LNOT::DEF:CYREG_TMR2_SR0 +CYREG_TMR2_SR0 EQU 0x40004f1b + ENDIF + IF :LNOT::DEF:CYREG_TMR2_PER0 +CYREG_TMR2_PER0 EQU 0x40004f1c + ENDIF + IF :LNOT::DEF:CYREG_TMR2_PER1 +CYREG_TMR2_PER1 EQU 0x40004f1d + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CNT_CMP0 +CYREG_TMR2_CNT_CMP0 EQU 0x40004f1e + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CNT_CMP1 +CYREG_TMR2_CNT_CMP1 EQU 0x40004f1f + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CAP0 +CYREG_TMR2_CAP0 EQU 0x40004f20 + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CAP1 +CYREG_TMR2_CAP1 EQU 0x40004f21 + ENDIF + IF :LNOT::DEF:CYREG_TMR2_RT0 +CYREG_TMR2_RT0 EQU 0x40004f22 + ENDIF + IF :LNOT::DEF:CYREG_TMR2_RT1 +CYREG_TMR2_RT1 EQU 0x40004f23 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_BASE +CYDEV_TMR3_BASE EQU 0x40004f24 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_SIZE +CYDEV_TMR3_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CFG0 +CYREG_TMR3_CFG0 EQU 0x40004f24 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CFG1 +CYREG_TMR3_CFG1 EQU 0x40004f25 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CFG2 +CYREG_TMR3_CFG2 EQU 0x40004f26 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_SR0 +CYREG_TMR3_SR0 EQU 0x40004f27 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_PER0 +CYREG_TMR3_PER0 EQU 0x40004f28 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_PER1 +CYREG_TMR3_PER1 EQU 0x40004f29 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CNT_CMP0 +CYREG_TMR3_CNT_CMP0 EQU 0x40004f2a + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CNT_CMP1 +CYREG_TMR3_CNT_CMP1 EQU 0x40004f2b + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CAP0 +CYREG_TMR3_CAP0 EQU 0x40004f2c + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CAP1 +CYREG_TMR3_CAP1 EQU 0x40004f2d + ENDIF + IF :LNOT::DEF:CYREG_TMR3_RT0 +CYREG_TMR3_RT0 EQU 0x40004f2e + ENDIF + IF :LNOT::DEF:CYREG_TMR3_RT1 +CYREG_TMR3_RT1 EQU 0x40004f2f + ENDIF + IF :LNOT::DEF:CYDEV_IO_BASE +CYDEV_IO_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_SIZE +CYDEV_IO_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_BASE +CYDEV_IO_PC_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_SIZE +CYDEV_IO_PC_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_BASE +CYDEV_IO_PC_PRT0_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_SIZE +CYDEV_IO_PC_PRT0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC0 +CYREG_PRT0_PC0 EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC1 +CYREG_PRT0_PC1 EQU 0x40005001 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC2 +CYREG_PRT0_PC2 EQU 0x40005002 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC3 +CYREG_PRT0_PC3 EQU 0x40005003 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC4 +CYREG_PRT0_PC4 EQU 0x40005004 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC5 +CYREG_PRT0_PC5 EQU 0x40005005 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC6 +CYREG_PRT0_PC6 EQU 0x40005006 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC7 +CYREG_PRT0_PC7 EQU 0x40005007 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_BASE +CYDEV_IO_PC_PRT1_BASE EQU 0x40005008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_SIZE +CYDEV_IO_PC_PRT1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC0 +CYREG_PRT1_PC0 EQU 0x40005008 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC1 +CYREG_PRT1_PC1 EQU 0x40005009 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC2 +CYREG_PRT1_PC2 EQU 0x4000500a + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC3 +CYREG_PRT1_PC3 EQU 0x4000500b + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC4 +CYREG_PRT1_PC4 EQU 0x4000500c + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC5 +CYREG_PRT1_PC5 EQU 0x4000500d + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC6 +CYREG_PRT1_PC6 EQU 0x4000500e + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC7 +CYREG_PRT1_PC7 EQU 0x4000500f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_BASE +CYDEV_IO_PC_PRT2_BASE EQU 0x40005010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_SIZE +CYDEV_IO_PC_PRT2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC0 +CYREG_PRT2_PC0 EQU 0x40005010 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC1 +CYREG_PRT2_PC1 EQU 0x40005011 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC2 +CYREG_PRT2_PC2 EQU 0x40005012 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC3 +CYREG_PRT2_PC3 EQU 0x40005013 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC4 +CYREG_PRT2_PC4 EQU 0x40005014 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC5 +CYREG_PRT2_PC5 EQU 0x40005015 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC6 +CYREG_PRT2_PC6 EQU 0x40005016 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC7 +CYREG_PRT2_PC7 EQU 0x40005017 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_BASE +CYDEV_IO_PC_PRT3_BASE EQU 0x40005018 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_SIZE +CYDEV_IO_PC_PRT3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC0 +CYREG_PRT3_PC0 EQU 0x40005018 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC1 +CYREG_PRT3_PC1 EQU 0x40005019 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC2 +CYREG_PRT3_PC2 EQU 0x4000501a + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC3 +CYREG_PRT3_PC3 EQU 0x4000501b + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC4 +CYREG_PRT3_PC4 EQU 0x4000501c + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC5 +CYREG_PRT3_PC5 EQU 0x4000501d + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC6 +CYREG_PRT3_PC6 EQU 0x4000501e + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC7 +CYREG_PRT3_PC7 EQU 0x4000501f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_BASE +CYDEV_IO_PC_PRT4_BASE EQU 0x40005020 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_SIZE +CYDEV_IO_PC_PRT4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC0 +CYREG_PRT4_PC0 EQU 0x40005020 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC1 +CYREG_PRT4_PC1 EQU 0x40005021 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC2 +CYREG_PRT4_PC2 EQU 0x40005022 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC3 +CYREG_PRT4_PC3 EQU 0x40005023 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC4 +CYREG_PRT4_PC4 EQU 0x40005024 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC5 +CYREG_PRT4_PC5 EQU 0x40005025 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC6 +CYREG_PRT4_PC6 EQU 0x40005026 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC7 +CYREG_PRT4_PC7 EQU 0x40005027 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_BASE +CYDEV_IO_PC_PRT5_BASE EQU 0x40005028 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_SIZE +CYDEV_IO_PC_PRT5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC0 +CYREG_PRT5_PC0 EQU 0x40005028 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC1 +CYREG_PRT5_PC1 EQU 0x40005029 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC2 +CYREG_PRT5_PC2 EQU 0x4000502a + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC3 +CYREG_PRT5_PC3 EQU 0x4000502b + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC4 +CYREG_PRT5_PC4 EQU 0x4000502c + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC5 +CYREG_PRT5_PC5 EQU 0x4000502d + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC6 +CYREG_PRT5_PC6 EQU 0x4000502e + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC7 +CYREG_PRT5_PC7 EQU 0x4000502f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_BASE +CYDEV_IO_PC_PRT6_BASE EQU 0x40005030 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_SIZE +CYDEV_IO_PC_PRT6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC0 +CYREG_PRT6_PC0 EQU 0x40005030 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC1 +CYREG_PRT6_PC1 EQU 0x40005031 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC2 +CYREG_PRT6_PC2 EQU 0x40005032 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC3 +CYREG_PRT6_PC3 EQU 0x40005033 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC4 +CYREG_PRT6_PC4 EQU 0x40005034 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC5 +CYREG_PRT6_PC5 EQU 0x40005035 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC6 +CYREG_PRT6_PC6 EQU 0x40005036 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC7 +CYREG_PRT6_PC7 EQU 0x40005037 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_BASE +CYDEV_IO_PC_PRT12_BASE EQU 0x40005060 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_SIZE +CYDEV_IO_PC_PRT12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC0 +CYREG_PRT12_PC0 EQU 0x40005060 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC1 +CYREG_PRT12_PC1 EQU 0x40005061 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC2 +CYREG_PRT12_PC2 EQU 0x40005062 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC3 +CYREG_PRT12_PC3 EQU 0x40005063 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC4 +CYREG_PRT12_PC4 EQU 0x40005064 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC5 +CYREG_PRT12_PC5 EQU 0x40005065 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC6 +CYREG_PRT12_PC6 EQU 0x40005066 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC7 +CYREG_PRT12_PC7 EQU 0x40005067 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_BASE +CYDEV_IO_PC_PRT15_BASE EQU 0x40005078 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_SIZE +CYDEV_IO_PC_PRT15_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC0 +CYREG_IO_PC_PRT15_PC0 EQU 0x40005078 + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC1 +CYREG_IO_PC_PRT15_PC1 EQU 0x40005079 + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC2 +CYREG_IO_PC_PRT15_PC2 EQU 0x4000507a + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC3 +CYREG_IO_PC_PRT15_PC3 EQU 0x4000507b + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC4 +CYREG_IO_PC_PRT15_PC4 EQU 0x4000507c + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC5 +CYREG_IO_PC_PRT15_PC5 EQU 0x4000507d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_BASE +CYDEV_IO_PC_PRT15_7_6_BASE EQU 0x4000507e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_SIZE +CYDEV_IO_PC_PRT15_7_6_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_7_6_PC0 +CYREG_IO_PC_PRT15_7_6_PC0 EQU 0x4000507e + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_7_6_PC1 +CYREG_IO_PC_PRT15_7_6_PC1 EQU 0x4000507f + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_BASE +CYDEV_IO_DR_BASE EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_SIZE +CYDEV_IO_DR_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT0_BASE +CYDEV_IO_DR_PRT0_BASE EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT0_SIZE +CYDEV_IO_DR_PRT0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DR_ALIAS +CYREG_PRT0_DR_ALIAS EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT1_BASE +CYDEV_IO_DR_PRT1_BASE EQU 0x40005081 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT1_SIZE +CYDEV_IO_DR_PRT1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DR_ALIAS +CYREG_PRT1_DR_ALIAS EQU 0x40005081 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT2_BASE +CYDEV_IO_DR_PRT2_BASE EQU 0x40005082 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT2_SIZE +CYDEV_IO_DR_PRT2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DR_ALIAS +CYREG_PRT2_DR_ALIAS EQU 0x40005082 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT3_BASE +CYDEV_IO_DR_PRT3_BASE EQU 0x40005083 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT3_SIZE +CYDEV_IO_DR_PRT3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DR_ALIAS +CYREG_PRT3_DR_ALIAS EQU 0x40005083 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT4_BASE +CYDEV_IO_DR_PRT4_BASE EQU 0x40005084 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT4_SIZE +CYDEV_IO_DR_PRT4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DR_ALIAS +CYREG_PRT4_DR_ALIAS EQU 0x40005084 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT5_BASE +CYDEV_IO_DR_PRT5_BASE EQU 0x40005085 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT5_SIZE +CYDEV_IO_DR_PRT5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DR_ALIAS +CYREG_PRT5_DR_ALIAS EQU 0x40005085 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT6_BASE +CYDEV_IO_DR_PRT6_BASE EQU 0x40005086 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT6_SIZE +CYDEV_IO_DR_PRT6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DR_ALIAS +CYREG_PRT6_DR_ALIAS EQU 0x40005086 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT12_BASE +CYDEV_IO_DR_PRT12_BASE EQU 0x4000508c + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT12_SIZE +CYDEV_IO_DR_PRT12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DR_ALIAS +CYREG_PRT12_DR_ALIAS EQU 0x4000508c + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT15_BASE +CYDEV_IO_DR_PRT15_BASE EQU 0x4000508f + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT15_SIZE +CYDEV_IO_DR_PRT15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DR_15_ALIAS +CYREG_PRT15_DR_15_ALIAS EQU 0x4000508f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_BASE +CYDEV_IO_PS_BASE EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_SIZE +CYDEV_IO_PS_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT0_BASE +CYDEV_IO_PS_PRT0_BASE EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT0_SIZE +CYDEV_IO_PS_PRT0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PS_ALIAS +CYREG_PRT0_PS_ALIAS EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT1_BASE +CYDEV_IO_PS_PRT1_BASE EQU 0x40005091 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT1_SIZE +CYDEV_IO_PS_PRT1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PS_ALIAS +CYREG_PRT1_PS_ALIAS EQU 0x40005091 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT2_BASE +CYDEV_IO_PS_PRT2_BASE EQU 0x40005092 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT2_SIZE +CYDEV_IO_PS_PRT2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PS_ALIAS +CYREG_PRT2_PS_ALIAS EQU 0x40005092 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT3_BASE +CYDEV_IO_PS_PRT3_BASE EQU 0x40005093 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT3_SIZE +CYDEV_IO_PS_PRT3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PS_ALIAS +CYREG_PRT3_PS_ALIAS EQU 0x40005093 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT4_BASE +CYDEV_IO_PS_PRT4_BASE EQU 0x40005094 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT4_SIZE +CYDEV_IO_PS_PRT4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PS_ALIAS +CYREG_PRT4_PS_ALIAS EQU 0x40005094 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT5_BASE +CYDEV_IO_PS_PRT5_BASE EQU 0x40005095 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT5_SIZE +CYDEV_IO_PS_PRT5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PS_ALIAS +CYREG_PRT5_PS_ALIAS EQU 0x40005095 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT6_BASE +CYDEV_IO_PS_PRT6_BASE EQU 0x40005096 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT6_SIZE +CYDEV_IO_PS_PRT6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PS_ALIAS +CYREG_PRT6_PS_ALIAS EQU 0x40005096 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT12_BASE +CYDEV_IO_PS_PRT12_BASE EQU 0x4000509c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT12_SIZE +CYDEV_IO_PS_PRT12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PS_ALIAS +CYREG_PRT12_PS_ALIAS EQU 0x4000509c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT15_BASE +CYDEV_IO_PS_PRT15_BASE EQU 0x4000509f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT15_SIZE +CYDEV_IO_PS_PRT15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_PS15_ALIAS +CYREG_PRT15_PS15_ALIAS EQU 0x4000509f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_BASE +CYDEV_IO_PRT_BASE EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_SIZE +CYDEV_IO_PRT_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BASE +CYDEV_IO_PRT_PRT0_BASE EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_SIZE +CYDEV_IO_PRT_PRT0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DR +CYREG_PRT0_DR EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PS +CYREG_PRT0_PS EQU 0x40005101 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DM0 +CYREG_PRT0_DM0 EQU 0x40005102 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DM1 +CYREG_PRT0_DM1 EQU 0x40005103 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DM2 +CYREG_PRT0_DM2 EQU 0x40005104 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_SLW +CYREG_PRT0_SLW EQU 0x40005105 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_BYP +CYREG_PRT0_BYP EQU 0x40005106 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_BIE +CYREG_PRT0_BIE EQU 0x40005107 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_INP_DIS +CYREG_PRT0_INP_DIS EQU 0x40005108 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_CTL +CYREG_PRT0_CTL EQU 0x40005109 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PRT +CYREG_PRT0_PRT EQU 0x4000510a + ENDIF + IF :LNOT::DEF:CYREG_PRT0_BIT_MASK +CYREG_PRT0_BIT_MASK EQU 0x4000510b + ENDIF + IF :LNOT::DEF:CYREG_PRT0_AMUX +CYREG_PRT0_AMUX EQU 0x4000510c + ENDIF + IF :LNOT::DEF:CYREG_PRT0_AG +CYREG_PRT0_AG EQU 0x4000510d + ENDIF + IF :LNOT::DEF:CYREG_PRT0_LCD_COM_SEG +CYREG_PRT0_LCD_COM_SEG EQU 0x4000510e + ENDIF + IF :LNOT::DEF:CYREG_PRT0_LCD_EN +CYREG_PRT0_LCD_EN EQU 0x4000510f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BASE +CYDEV_IO_PRT_PRT1_BASE EQU 0x40005110 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_SIZE +CYDEV_IO_PRT_PRT1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DR +CYREG_PRT1_DR EQU 0x40005110 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PS +CYREG_PRT1_PS EQU 0x40005111 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DM0 +CYREG_PRT1_DM0 EQU 0x40005112 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DM1 +CYREG_PRT1_DM1 EQU 0x40005113 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DM2 +CYREG_PRT1_DM2 EQU 0x40005114 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_SLW +CYREG_PRT1_SLW EQU 0x40005115 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_BYP +CYREG_PRT1_BYP EQU 0x40005116 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_BIE +CYREG_PRT1_BIE EQU 0x40005117 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_INP_DIS +CYREG_PRT1_INP_DIS EQU 0x40005118 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_CTL +CYREG_PRT1_CTL EQU 0x40005119 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PRT +CYREG_PRT1_PRT EQU 0x4000511a + ENDIF + IF :LNOT::DEF:CYREG_PRT1_BIT_MASK +CYREG_PRT1_BIT_MASK EQU 0x4000511b + ENDIF + IF :LNOT::DEF:CYREG_PRT1_AMUX +CYREG_PRT1_AMUX EQU 0x4000511c + ENDIF + IF :LNOT::DEF:CYREG_PRT1_AG +CYREG_PRT1_AG EQU 0x4000511d + ENDIF + IF :LNOT::DEF:CYREG_PRT1_LCD_COM_SEG +CYREG_PRT1_LCD_COM_SEG EQU 0x4000511e + ENDIF + IF :LNOT::DEF:CYREG_PRT1_LCD_EN +CYREG_PRT1_LCD_EN EQU 0x4000511f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BASE +CYDEV_IO_PRT_PRT2_BASE EQU 0x40005120 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_SIZE +CYDEV_IO_PRT_PRT2_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DR +CYREG_PRT2_DR EQU 0x40005120 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PS +CYREG_PRT2_PS EQU 0x40005121 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DM0 +CYREG_PRT2_DM0 EQU 0x40005122 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DM1 +CYREG_PRT2_DM1 EQU 0x40005123 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DM2 +CYREG_PRT2_DM2 EQU 0x40005124 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_SLW +CYREG_PRT2_SLW EQU 0x40005125 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_BYP +CYREG_PRT2_BYP EQU 0x40005126 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_BIE +CYREG_PRT2_BIE EQU 0x40005127 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_INP_DIS +CYREG_PRT2_INP_DIS EQU 0x40005128 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_CTL +CYREG_PRT2_CTL EQU 0x40005129 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PRT +CYREG_PRT2_PRT EQU 0x4000512a + ENDIF + IF :LNOT::DEF:CYREG_PRT2_BIT_MASK +CYREG_PRT2_BIT_MASK EQU 0x4000512b + ENDIF + IF :LNOT::DEF:CYREG_PRT2_AMUX +CYREG_PRT2_AMUX EQU 0x4000512c + ENDIF + IF :LNOT::DEF:CYREG_PRT2_AG +CYREG_PRT2_AG EQU 0x4000512d + ENDIF + IF :LNOT::DEF:CYREG_PRT2_LCD_COM_SEG +CYREG_PRT2_LCD_COM_SEG EQU 0x4000512e + ENDIF + IF :LNOT::DEF:CYREG_PRT2_LCD_EN +CYREG_PRT2_LCD_EN EQU 0x4000512f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BASE +CYDEV_IO_PRT_PRT3_BASE EQU 0x40005130 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_SIZE +CYDEV_IO_PRT_PRT3_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DR +CYREG_PRT3_DR EQU 0x40005130 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PS +CYREG_PRT3_PS EQU 0x40005131 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DM0 +CYREG_PRT3_DM0 EQU 0x40005132 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DM1 +CYREG_PRT3_DM1 EQU 0x40005133 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DM2 +CYREG_PRT3_DM2 EQU 0x40005134 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_SLW +CYREG_PRT3_SLW EQU 0x40005135 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_BYP +CYREG_PRT3_BYP EQU 0x40005136 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_BIE +CYREG_PRT3_BIE EQU 0x40005137 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_INP_DIS +CYREG_PRT3_INP_DIS EQU 0x40005138 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_CTL +CYREG_PRT3_CTL EQU 0x40005139 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PRT +CYREG_PRT3_PRT EQU 0x4000513a + ENDIF + IF :LNOT::DEF:CYREG_PRT3_BIT_MASK +CYREG_PRT3_BIT_MASK EQU 0x4000513b + ENDIF + IF :LNOT::DEF:CYREG_PRT3_AMUX +CYREG_PRT3_AMUX EQU 0x4000513c + ENDIF + IF :LNOT::DEF:CYREG_PRT3_AG +CYREG_PRT3_AG EQU 0x4000513d + ENDIF + IF :LNOT::DEF:CYREG_PRT3_LCD_COM_SEG +CYREG_PRT3_LCD_COM_SEG EQU 0x4000513e + ENDIF + IF :LNOT::DEF:CYREG_PRT3_LCD_EN +CYREG_PRT3_LCD_EN EQU 0x4000513f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BASE +CYDEV_IO_PRT_PRT4_BASE EQU 0x40005140 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_SIZE +CYDEV_IO_PRT_PRT4_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DR +CYREG_PRT4_DR EQU 0x40005140 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PS +CYREG_PRT4_PS EQU 0x40005141 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DM0 +CYREG_PRT4_DM0 EQU 0x40005142 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DM1 +CYREG_PRT4_DM1 EQU 0x40005143 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DM2 +CYREG_PRT4_DM2 EQU 0x40005144 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_SLW +CYREG_PRT4_SLW EQU 0x40005145 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_BYP +CYREG_PRT4_BYP EQU 0x40005146 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_BIE +CYREG_PRT4_BIE EQU 0x40005147 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_INP_DIS +CYREG_PRT4_INP_DIS EQU 0x40005148 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_CTL +CYREG_PRT4_CTL EQU 0x40005149 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PRT +CYREG_PRT4_PRT EQU 0x4000514a + ENDIF + IF :LNOT::DEF:CYREG_PRT4_BIT_MASK +CYREG_PRT4_BIT_MASK EQU 0x4000514b + ENDIF + IF :LNOT::DEF:CYREG_PRT4_AMUX +CYREG_PRT4_AMUX EQU 0x4000514c + ENDIF + IF :LNOT::DEF:CYREG_PRT4_AG +CYREG_PRT4_AG EQU 0x4000514d + ENDIF + IF :LNOT::DEF:CYREG_PRT4_LCD_COM_SEG +CYREG_PRT4_LCD_COM_SEG EQU 0x4000514e + ENDIF + IF :LNOT::DEF:CYREG_PRT4_LCD_EN +CYREG_PRT4_LCD_EN EQU 0x4000514f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BASE +CYDEV_IO_PRT_PRT5_BASE EQU 0x40005150 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_SIZE +CYDEV_IO_PRT_PRT5_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DR +CYREG_PRT5_DR EQU 0x40005150 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PS +CYREG_PRT5_PS EQU 0x40005151 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DM0 +CYREG_PRT5_DM0 EQU 0x40005152 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DM1 +CYREG_PRT5_DM1 EQU 0x40005153 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DM2 +CYREG_PRT5_DM2 EQU 0x40005154 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_SLW +CYREG_PRT5_SLW EQU 0x40005155 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_BYP +CYREG_PRT5_BYP EQU 0x40005156 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_BIE +CYREG_PRT5_BIE EQU 0x40005157 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_INP_DIS +CYREG_PRT5_INP_DIS EQU 0x40005158 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_CTL +CYREG_PRT5_CTL EQU 0x40005159 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PRT +CYREG_PRT5_PRT EQU 0x4000515a + ENDIF + IF :LNOT::DEF:CYREG_PRT5_BIT_MASK +CYREG_PRT5_BIT_MASK EQU 0x4000515b + ENDIF + IF :LNOT::DEF:CYREG_PRT5_AMUX +CYREG_PRT5_AMUX EQU 0x4000515c + ENDIF + IF :LNOT::DEF:CYREG_PRT5_AG +CYREG_PRT5_AG EQU 0x4000515d + ENDIF + IF :LNOT::DEF:CYREG_PRT5_LCD_COM_SEG +CYREG_PRT5_LCD_COM_SEG EQU 0x4000515e + ENDIF + IF :LNOT::DEF:CYREG_PRT5_LCD_EN +CYREG_PRT5_LCD_EN EQU 0x4000515f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BASE +CYDEV_IO_PRT_PRT6_BASE EQU 0x40005160 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_SIZE +CYDEV_IO_PRT_PRT6_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DR +CYREG_PRT6_DR EQU 0x40005160 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PS +CYREG_PRT6_PS EQU 0x40005161 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DM0 +CYREG_PRT6_DM0 EQU 0x40005162 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DM1 +CYREG_PRT6_DM1 EQU 0x40005163 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DM2 +CYREG_PRT6_DM2 EQU 0x40005164 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_SLW +CYREG_PRT6_SLW EQU 0x40005165 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_BYP +CYREG_PRT6_BYP EQU 0x40005166 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_BIE +CYREG_PRT6_BIE EQU 0x40005167 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_INP_DIS +CYREG_PRT6_INP_DIS EQU 0x40005168 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_CTL +CYREG_PRT6_CTL EQU 0x40005169 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PRT +CYREG_PRT6_PRT EQU 0x4000516a + ENDIF + IF :LNOT::DEF:CYREG_PRT6_BIT_MASK +CYREG_PRT6_BIT_MASK EQU 0x4000516b + ENDIF + IF :LNOT::DEF:CYREG_PRT6_AMUX +CYREG_PRT6_AMUX EQU 0x4000516c + ENDIF + IF :LNOT::DEF:CYREG_PRT6_AG +CYREG_PRT6_AG EQU 0x4000516d + ENDIF + IF :LNOT::DEF:CYREG_PRT6_LCD_COM_SEG +CYREG_PRT6_LCD_COM_SEG EQU 0x4000516e + ENDIF + IF :LNOT::DEF:CYREG_PRT6_LCD_EN +CYREG_PRT6_LCD_EN EQU 0x4000516f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BASE +CYDEV_IO_PRT_PRT12_BASE EQU 0x400051c0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIZE +CYDEV_IO_PRT_PRT12_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DR +CYREG_PRT12_DR EQU 0x400051c0 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PS +CYREG_PRT12_PS EQU 0x400051c1 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DM0 +CYREG_PRT12_DM0 EQU 0x400051c2 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DM1 +CYREG_PRT12_DM1 EQU 0x400051c3 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DM2 +CYREG_PRT12_DM2 EQU 0x400051c4 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SLW +CYREG_PRT12_SLW EQU 0x400051c5 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_BYP +CYREG_PRT12_BYP EQU 0x400051c6 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_BIE +CYREG_PRT12_BIE EQU 0x400051c7 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_INP_DIS +CYREG_PRT12_INP_DIS EQU 0x400051c8 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SIO_HYST_EN +CYREG_PRT12_SIO_HYST_EN EQU 0x400051c9 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PRT +CYREG_PRT12_PRT EQU 0x400051ca + ENDIF + IF :LNOT::DEF:CYREG_PRT12_BIT_MASK +CYREG_PRT12_BIT_MASK EQU 0x400051cb + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SIO_REG_HIFREQ +CYREG_PRT12_SIO_REG_HIFREQ EQU 0x400051cc + ENDIF + IF :LNOT::DEF:CYREG_PRT12_AG +CYREG_PRT12_AG EQU 0x400051cd + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SIO_CFG +CYREG_PRT12_SIO_CFG EQU 0x400051ce + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SIO_DIFF +CYREG_PRT12_SIO_DIFF EQU 0x400051cf + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BASE +CYDEV_IO_PRT_PRT15_BASE EQU 0x400051f0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_SIZE +CYDEV_IO_PRT_PRT15_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DR +CYREG_PRT15_DR EQU 0x400051f0 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_PS +CYREG_PRT15_PS EQU 0x400051f1 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DM0 +CYREG_PRT15_DM0 EQU 0x400051f2 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DM1 +CYREG_PRT15_DM1 EQU 0x400051f3 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DM2 +CYREG_PRT15_DM2 EQU 0x400051f4 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_SLW +CYREG_PRT15_SLW EQU 0x400051f5 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_BYP +CYREG_PRT15_BYP EQU 0x400051f6 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_BIE +CYREG_PRT15_BIE EQU 0x400051f7 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_INP_DIS +CYREG_PRT15_INP_DIS EQU 0x400051f8 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_CTL +CYREG_PRT15_CTL EQU 0x400051f9 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_PRT +CYREG_PRT15_PRT EQU 0x400051fa + ENDIF + IF :LNOT::DEF:CYREG_PRT15_BIT_MASK +CYREG_PRT15_BIT_MASK EQU 0x400051fb + ENDIF + IF :LNOT::DEF:CYREG_PRT15_AMUX +CYREG_PRT15_AMUX EQU 0x400051fc + ENDIF + IF :LNOT::DEF:CYREG_PRT15_AG +CYREG_PRT15_AG EQU 0x400051fd + ENDIF + IF :LNOT::DEF:CYREG_PRT15_LCD_COM_SEG +CYREG_PRT15_LCD_COM_SEG EQU 0x400051fe + ENDIF + IF :LNOT::DEF:CYREG_PRT15_LCD_EN +CYREG_PRT15_LCD_EN EQU 0x400051ff + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_BASE +CYDEV_PRTDSI_BASE EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_SIZE +CYDEV_PRTDSI_SIZE EQU 0x0000007f + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_BASE +CYDEV_PRTDSI_PRT0_BASE EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_SIZE +CYDEV_PRTDSI_PRT0_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_OUT_SEL0 +CYREG_PRT0_OUT_SEL0 EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_OUT_SEL1 +CYREG_PRT0_OUT_SEL1 EQU 0x40005201 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_OE_SEL0 +CYREG_PRT0_OE_SEL0 EQU 0x40005202 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_OE_SEL1 +CYREG_PRT0_OE_SEL1 EQU 0x40005203 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DBL_SYNC_IN +CYREG_PRT0_DBL_SYNC_IN EQU 0x40005204 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_SYNC_OUT +CYREG_PRT0_SYNC_OUT EQU 0x40005205 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_CAPS_SEL +CYREG_PRT0_CAPS_SEL EQU 0x40005206 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_BASE +CYDEV_PRTDSI_PRT1_BASE EQU 0x40005208 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_SIZE +CYDEV_PRTDSI_PRT1_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_OUT_SEL0 +CYREG_PRT1_OUT_SEL0 EQU 0x40005208 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_OUT_SEL1 +CYREG_PRT1_OUT_SEL1 EQU 0x40005209 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_OE_SEL0 +CYREG_PRT1_OE_SEL0 EQU 0x4000520a + ENDIF + IF :LNOT::DEF:CYREG_PRT1_OE_SEL1 +CYREG_PRT1_OE_SEL1 EQU 0x4000520b + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DBL_SYNC_IN +CYREG_PRT1_DBL_SYNC_IN EQU 0x4000520c + ENDIF + IF :LNOT::DEF:CYREG_PRT1_SYNC_OUT +CYREG_PRT1_SYNC_OUT EQU 0x4000520d + ENDIF + IF :LNOT::DEF:CYREG_PRT1_CAPS_SEL +CYREG_PRT1_CAPS_SEL EQU 0x4000520e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_BASE +CYDEV_PRTDSI_PRT2_BASE EQU 0x40005210 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_SIZE +CYDEV_PRTDSI_PRT2_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_OUT_SEL0 +CYREG_PRT2_OUT_SEL0 EQU 0x40005210 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_OUT_SEL1 +CYREG_PRT2_OUT_SEL1 EQU 0x40005211 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_OE_SEL0 +CYREG_PRT2_OE_SEL0 EQU 0x40005212 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_OE_SEL1 +CYREG_PRT2_OE_SEL1 EQU 0x40005213 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DBL_SYNC_IN +CYREG_PRT2_DBL_SYNC_IN EQU 0x40005214 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_SYNC_OUT +CYREG_PRT2_SYNC_OUT EQU 0x40005215 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_CAPS_SEL +CYREG_PRT2_CAPS_SEL EQU 0x40005216 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_BASE +CYDEV_PRTDSI_PRT3_BASE EQU 0x40005218 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_SIZE +CYDEV_PRTDSI_PRT3_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_OUT_SEL0 +CYREG_PRT3_OUT_SEL0 EQU 0x40005218 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_OUT_SEL1 +CYREG_PRT3_OUT_SEL1 EQU 0x40005219 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_OE_SEL0 +CYREG_PRT3_OE_SEL0 EQU 0x4000521a + ENDIF + IF :LNOT::DEF:CYREG_PRT3_OE_SEL1 +CYREG_PRT3_OE_SEL1 EQU 0x4000521b + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DBL_SYNC_IN +CYREG_PRT3_DBL_SYNC_IN EQU 0x4000521c + ENDIF + IF :LNOT::DEF:CYREG_PRT3_SYNC_OUT +CYREG_PRT3_SYNC_OUT EQU 0x4000521d + ENDIF + IF :LNOT::DEF:CYREG_PRT3_CAPS_SEL +CYREG_PRT3_CAPS_SEL EQU 0x4000521e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_BASE +CYDEV_PRTDSI_PRT4_BASE EQU 0x40005220 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_SIZE +CYDEV_PRTDSI_PRT4_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_OUT_SEL0 +CYREG_PRT4_OUT_SEL0 EQU 0x40005220 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_OUT_SEL1 +CYREG_PRT4_OUT_SEL1 EQU 0x40005221 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_OE_SEL0 +CYREG_PRT4_OE_SEL0 EQU 0x40005222 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_OE_SEL1 +CYREG_PRT4_OE_SEL1 EQU 0x40005223 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DBL_SYNC_IN +CYREG_PRT4_DBL_SYNC_IN EQU 0x40005224 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_SYNC_OUT +CYREG_PRT4_SYNC_OUT EQU 0x40005225 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_CAPS_SEL +CYREG_PRT4_CAPS_SEL EQU 0x40005226 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_BASE +CYDEV_PRTDSI_PRT5_BASE EQU 0x40005228 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_SIZE +CYDEV_PRTDSI_PRT5_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_OUT_SEL0 +CYREG_PRT5_OUT_SEL0 EQU 0x40005228 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_OUT_SEL1 +CYREG_PRT5_OUT_SEL1 EQU 0x40005229 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_OE_SEL0 +CYREG_PRT5_OE_SEL0 EQU 0x4000522a + ENDIF + IF :LNOT::DEF:CYREG_PRT5_OE_SEL1 +CYREG_PRT5_OE_SEL1 EQU 0x4000522b + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DBL_SYNC_IN +CYREG_PRT5_DBL_SYNC_IN EQU 0x4000522c + ENDIF + IF :LNOT::DEF:CYREG_PRT5_SYNC_OUT +CYREG_PRT5_SYNC_OUT EQU 0x4000522d + ENDIF + IF :LNOT::DEF:CYREG_PRT5_CAPS_SEL +CYREG_PRT5_CAPS_SEL EQU 0x4000522e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_BASE +CYDEV_PRTDSI_PRT6_BASE EQU 0x40005230 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_SIZE +CYDEV_PRTDSI_PRT6_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_OUT_SEL0 +CYREG_PRT6_OUT_SEL0 EQU 0x40005230 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_OUT_SEL1 +CYREG_PRT6_OUT_SEL1 EQU 0x40005231 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_OE_SEL0 +CYREG_PRT6_OE_SEL0 EQU 0x40005232 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_OE_SEL1 +CYREG_PRT6_OE_SEL1 EQU 0x40005233 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DBL_SYNC_IN +CYREG_PRT6_DBL_SYNC_IN EQU 0x40005234 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_SYNC_OUT +CYREG_PRT6_SYNC_OUT EQU 0x40005235 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_CAPS_SEL +CYREG_PRT6_CAPS_SEL EQU 0x40005236 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_BASE +CYDEV_PRTDSI_PRT12_BASE EQU 0x40005260 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_SIZE +CYDEV_PRTDSI_PRT12_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_OUT_SEL0 +CYREG_PRT12_OUT_SEL0 EQU 0x40005260 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_OUT_SEL1 +CYREG_PRT12_OUT_SEL1 EQU 0x40005261 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_OE_SEL0 +CYREG_PRT12_OE_SEL0 EQU 0x40005262 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_OE_SEL1 +CYREG_PRT12_OE_SEL1 EQU 0x40005263 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DBL_SYNC_IN +CYREG_PRT12_DBL_SYNC_IN EQU 0x40005264 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SYNC_OUT +CYREG_PRT12_SYNC_OUT EQU 0x40005265 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_BASE +CYDEV_PRTDSI_PRT15_BASE EQU 0x40005278 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_SIZE +CYDEV_PRTDSI_PRT15_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_OUT_SEL0 +CYREG_PRT15_OUT_SEL0 EQU 0x40005278 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_OUT_SEL1 +CYREG_PRT15_OUT_SEL1 EQU 0x40005279 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_OE_SEL0 +CYREG_PRT15_OE_SEL0 EQU 0x4000527a + ENDIF + IF :LNOT::DEF:CYREG_PRT15_OE_SEL1 +CYREG_PRT15_OE_SEL1 EQU 0x4000527b + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DBL_SYNC_IN +CYREG_PRT15_DBL_SYNC_IN EQU 0x4000527c + ENDIF + IF :LNOT::DEF:CYREG_PRT15_SYNC_OUT +CYREG_PRT15_SYNC_OUT EQU 0x4000527d + ENDIF + IF :LNOT::DEF:CYREG_PRT15_CAPS_SEL +CYREG_PRT15_CAPS_SEL EQU 0x4000527e + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_BASE +CYDEV_EMIF_BASE EQU 0x40005400 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_SIZE +CYDEV_EMIF_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_NO_UDB +CYREG_EMIF_NO_UDB EQU 0x40005400 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_RP_WAIT_STATES +CYREG_EMIF_RP_WAIT_STATES EQU 0x40005401 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_MEM_DWN +CYREG_EMIF_MEM_DWN EQU 0x40005402 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_MEMCLK_DIV +CYREG_EMIF_MEMCLK_DIV EQU 0x40005403 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_CLOCK_EN +CYREG_EMIF_CLOCK_EN EQU 0x40005404 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_EM_TYPE +CYREG_EMIF_EM_TYPE EQU 0x40005405 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_WP_WAIT_STATES +CYREG_EMIF_WP_WAIT_STATES EQU 0x40005406 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_BASE +CYDEV_ANAIF_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_SIZE +CYDEV_ANAIF_SIZE EQU 0x000003a9 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BASE +CYDEV_ANAIF_CFG_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SIZE +CYDEV_ANAIF_CFG_SIZE EQU 0x0000010f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_BASE +CYDEV_ANAIF_CFG_SC0_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_SIZE +CYDEV_ANAIF_CFG_SC0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SC0_CR0 +CYREG_SC0_CR0 EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYREG_SC0_CR1 +CYREG_SC0_CR1 EQU 0x40005801 + ENDIF + IF :LNOT::DEF:CYREG_SC0_CR2 +CYREG_SC0_CR2 EQU 0x40005802 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_BASE +CYDEV_ANAIF_CFG_SC1_BASE EQU 0x40005804 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_SIZE +CYDEV_ANAIF_CFG_SC1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SC1_CR0 +CYREG_SC1_CR0 EQU 0x40005804 + ENDIF + IF :LNOT::DEF:CYREG_SC1_CR1 +CYREG_SC1_CR1 EQU 0x40005805 + ENDIF + IF :LNOT::DEF:CYREG_SC1_CR2 +CYREG_SC1_CR2 EQU 0x40005806 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_BASE +CYDEV_ANAIF_CFG_SC2_BASE EQU 0x40005808 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_SIZE +CYDEV_ANAIF_CFG_SC2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SC2_CR0 +CYREG_SC2_CR0 EQU 0x40005808 + ENDIF + IF :LNOT::DEF:CYREG_SC2_CR1 +CYREG_SC2_CR1 EQU 0x40005809 + ENDIF + IF :LNOT::DEF:CYREG_SC2_CR2 +CYREG_SC2_CR2 EQU 0x4000580a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_BASE +CYDEV_ANAIF_CFG_SC3_BASE EQU 0x4000580c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_SIZE +CYDEV_ANAIF_CFG_SC3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SC3_CR0 +CYREG_SC3_CR0 EQU 0x4000580c + ENDIF + IF :LNOT::DEF:CYREG_SC3_CR1 +CYREG_SC3_CR1 EQU 0x4000580d + ENDIF + IF :LNOT::DEF:CYREG_SC3_CR2 +CYREG_SC3_CR2 EQU 0x4000580e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_BASE +CYDEV_ANAIF_CFG_DAC0_BASE EQU 0x40005820 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_SIZE +CYDEV_ANAIF_CFG_DAC0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_CR0 +CYREG_DAC0_CR0 EQU 0x40005820 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_CR1 +CYREG_DAC0_CR1 EQU 0x40005821 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_TST +CYREG_DAC0_TST EQU 0x40005822 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_BASE +CYDEV_ANAIF_CFG_DAC1_BASE EQU 0x40005824 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_SIZE +CYDEV_ANAIF_CFG_DAC1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_CR0 +CYREG_DAC1_CR0 EQU 0x40005824 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_CR1 +CYREG_DAC1_CR1 EQU 0x40005825 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_TST +CYREG_DAC1_TST EQU 0x40005826 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_BASE +CYDEV_ANAIF_CFG_DAC2_BASE EQU 0x40005828 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_SIZE +CYDEV_ANAIF_CFG_DAC2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_CR0 +CYREG_DAC2_CR0 EQU 0x40005828 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_CR1 +CYREG_DAC2_CR1 EQU 0x40005829 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_TST +CYREG_DAC2_TST EQU 0x4000582a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_BASE +CYDEV_ANAIF_CFG_DAC3_BASE EQU 0x4000582c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_SIZE +CYDEV_ANAIF_CFG_DAC3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_DAC3_CR0 +CYREG_DAC3_CR0 EQU 0x4000582c + ENDIF + IF :LNOT::DEF:CYREG_DAC3_CR1 +CYREG_DAC3_CR1 EQU 0x4000582d + ENDIF + IF :LNOT::DEF:CYREG_DAC3_TST +CYREG_DAC3_TST EQU 0x4000582e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_BASE +CYDEV_ANAIF_CFG_CMP0_BASE EQU 0x40005840 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_SIZE +CYDEV_ANAIF_CFG_CMP0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_CR +CYREG_CMP0_CR EQU 0x40005840 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_BASE +CYDEV_ANAIF_CFG_CMP1_BASE EQU 0x40005841 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_SIZE +CYDEV_ANAIF_CFG_CMP1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CMP1_CR +CYREG_CMP1_CR EQU 0x40005841 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_BASE +CYDEV_ANAIF_CFG_CMP2_BASE EQU 0x40005842 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_SIZE +CYDEV_ANAIF_CFG_CMP2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_CR +CYREG_CMP2_CR EQU 0x40005842 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_BASE +CYDEV_ANAIF_CFG_CMP3_BASE EQU 0x40005843 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_SIZE +CYDEV_ANAIF_CFG_CMP3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CMP3_CR +CYREG_CMP3_CR EQU 0x40005843 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_BASE +CYDEV_ANAIF_CFG_LUT0_BASE EQU 0x40005848 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_SIZE +CYDEV_ANAIF_CFG_LUT0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LUT0_CR +CYREG_LUT0_CR EQU 0x40005848 + ENDIF + IF :LNOT::DEF:CYREG_LUT0_MX +CYREG_LUT0_MX EQU 0x40005849 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_BASE +CYDEV_ANAIF_CFG_LUT1_BASE EQU 0x4000584a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_SIZE +CYDEV_ANAIF_CFG_LUT1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LUT1_CR +CYREG_LUT1_CR EQU 0x4000584a + ENDIF + IF :LNOT::DEF:CYREG_LUT1_MX +CYREG_LUT1_MX EQU 0x4000584b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_BASE +CYDEV_ANAIF_CFG_LUT2_BASE EQU 0x4000584c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_SIZE +CYDEV_ANAIF_CFG_LUT2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LUT2_CR +CYREG_LUT2_CR EQU 0x4000584c + ENDIF + IF :LNOT::DEF:CYREG_LUT2_MX +CYREG_LUT2_MX EQU 0x4000584d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_BASE +CYDEV_ANAIF_CFG_LUT3_BASE EQU 0x4000584e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_SIZE +CYDEV_ANAIF_CFG_LUT3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LUT3_CR +CYREG_LUT3_CR EQU 0x4000584e + ENDIF + IF :LNOT::DEF:CYREG_LUT3_MX +CYREG_LUT3_MX EQU 0x4000584f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_BASE +CYDEV_ANAIF_CFG_OPAMP0_BASE EQU 0x40005858 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_SIZE +CYDEV_ANAIF_CFG_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_CR +CYREG_OPAMP0_CR EQU 0x40005858 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_RSVD +CYREG_OPAMP0_RSVD EQU 0x40005859 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_BASE +CYDEV_ANAIF_CFG_OPAMP1_BASE EQU 0x4000585a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_SIZE +CYDEV_ANAIF_CFG_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_CR +CYREG_OPAMP1_CR EQU 0x4000585a + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_RSVD +CYREG_OPAMP1_RSVD EQU 0x4000585b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_BASE +CYDEV_ANAIF_CFG_OPAMP2_BASE EQU 0x4000585c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_SIZE +CYDEV_ANAIF_CFG_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_CR +CYREG_OPAMP2_CR EQU 0x4000585c + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_RSVD +CYREG_OPAMP2_RSVD EQU 0x4000585d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_BASE +CYDEV_ANAIF_CFG_OPAMP3_BASE EQU 0x4000585e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_SIZE +CYDEV_ANAIF_CFG_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_CR +CYREG_OPAMP3_CR EQU 0x4000585e + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_RSVD +CYREG_OPAMP3_RSVD EQU 0x4000585f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_BASE +CYDEV_ANAIF_CFG_LCDDAC_BASE EQU 0x40005868 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_SIZE +CYDEV_ANAIF_CFG_LCDDAC_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_CR0 +CYREG_LCDDAC_CR0 EQU 0x40005868 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_CR1 +CYREG_LCDDAC_CR1 EQU 0x40005869 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_BASE +CYDEV_ANAIF_CFG_LCDDRV_BASE EQU 0x4000586a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_SIZE +CYDEV_ANAIF_CFG_LCDDRV_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_LCDDRV_CR +CYREG_LCDDRV_CR EQU 0x4000586a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_BASE +CYDEV_ANAIF_CFG_LCDTMR_BASE EQU 0x4000586b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_SIZE +CYDEV_ANAIF_CFG_LCDTMR_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_LCDTMR_CFG +CYREG_LCDTMR_CFG EQU 0x4000586b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_BASE +CYDEV_ANAIF_CFG_BG_BASE EQU 0x4000586c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_SIZE +CYDEV_ANAIF_CFG_BG_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_BG_CR0 +CYREG_BG_CR0 EQU 0x4000586c + ENDIF + IF :LNOT::DEF:CYREG_BG_RSVD +CYREG_BG_RSVD EQU 0x4000586d + ENDIF + IF :LNOT::DEF:CYREG_BG_DFT0 +CYREG_BG_DFT0 EQU 0x4000586e + ENDIF + IF :LNOT::DEF:CYREG_BG_DFT1 +CYREG_BG_DFT1 EQU 0x4000586f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_BASE +CYDEV_ANAIF_CFG_CAPSL_BASE EQU 0x40005870 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_SIZE +CYDEV_ANAIF_CFG_CAPSL_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CAPSL_CFG0 +CYREG_CAPSL_CFG0 EQU 0x40005870 + ENDIF + IF :LNOT::DEF:CYREG_CAPSL_CFG1 +CYREG_CAPSL_CFG1 EQU 0x40005871 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_BASE +CYDEV_ANAIF_CFG_CAPSR_BASE EQU 0x40005872 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_SIZE +CYDEV_ANAIF_CFG_CAPSR_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CAPSR_CFG0 +CYREG_CAPSR_CFG0 EQU 0x40005872 + ENDIF + IF :LNOT::DEF:CYREG_CAPSR_CFG1 +CYREG_CAPSR_CFG1 EQU 0x40005873 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_BASE +CYDEV_ANAIF_CFG_PUMP_BASE EQU 0x40005876 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_SIZE +CYDEV_ANAIF_CFG_PUMP_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_PUMP_CR0 +CYREG_PUMP_CR0 EQU 0x40005876 + ENDIF + IF :LNOT::DEF:CYREG_PUMP_CR1 +CYREG_PUMP_CR1 EQU 0x40005877 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_BASE +CYDEV_ANAIF_CFG_LPF0_BASE EQU 0x40005878 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_SIZE +CYDEV_ANAIF_CFG_LPF0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LPF0_CR0 +CYREG_LPF0_CR0 EQU 0x40005878 + ENDIF + IF :LNOT::DEF:CYREG_LPF0_RSVD +CYREG_LPF0_RSVD EQU 0x40005879 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_BASE +CYDEV_ANAIF_CFG_LPF1_BASE EQU 0x4000587a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_SIZE +CYDEV_ANAIF_CFG_LPF1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LPF1_CR0 +CYREG_LPF1_CR0 EQU 0x4000587a + ENDIF + IF :LNOT::DEF:CYREG_LPF1_RSVD +CYREG_LPF1_RSVD EQU 0x4000587b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_BASE +CYDEV_ANAIF_CFG_MISC_BASE EQU 0x4000587c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_SIZE +CYDEV_ANAIF_CFG_MISC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_ANAIF_CFG_MISC_CR0 +CYREG_ANAIF_CFG_MISC_CR0 EQU 0x4000587c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BASE +CYDEV_ANAIF_CFG_DSM0_BASE EQU 0x40005880 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_SIZE +CYDEV_ANAIF_CFG_DSM0_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR0 +CYREG_DSM0_CR0 EQU 0x40005880 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR1 +CYREG_DSM0_CR1 EQU 0x40005881 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR2 +CYREG_DSM0_CR2 EQU 0x40005882 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR3 +CYREG_DSM0_CR3 EQU 0x40005883 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR4 +CYREG_DSM0_CR4 EQU 0x40005884 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR5 +CYREG_DSM0_CR5 EQU 0x40005885 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR6 +CYREG_DSM0_CR6 EQU 0x40005886 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR7 +CYREG_DSM0_CR7 EQU 0x40005887 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR8 +CYREG_DSM0_CR8 EQU 0x40005888 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR9 +CYREG_DSM0_CR9 EQU 0x40005889 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR10 +CYREG_DSM0_CR10 EQU 0x4000588a + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR11 +CYREG_DSM0_CR11 EQU 0x4000588b + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR12 +CYREG_DSM0_CR12 EQU 0x4000588c + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR13 +CYREG_DSM0_CR13 EQU 0x4000588d + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR14 +CYREG_DSM0_CR14 EQU 0x4000588e + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR15 +CYREG_DSM0_CR15 EQU 0x4000588f + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR16 +CYREG_DSM0_CR16 EQU 0x40005890 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR17 +CYREG_DSM0_CR17 EQU 0x40005891 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_REF0 +CYREG_DSM0_REF0 EQU 0x40005892 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_REF1 +CYREG_DSM0_REF1 EQU 0x40005893 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_REF2 +CYREG_DSM0_REF2 EQU 0x40005894 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_REF3 +CYREG_DSM0_REF3 EQU 0x40005895 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_DEM0 +CYREG_DSM0_DEM0 EQU 0x40005896 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_DEM1 +CYREG_DSM0_DEM1 EQU 0x40005897 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_TST0 +CYREG_DSM0_TST0 EQU 0x40005898 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_TST1 +CYREG_DSM0_TST1 EQU 0x40005899 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_BUF0 +CYREG_DSM0_BUF0 EQU 0x4000589a + ENDIF + IF :LNOT::DEF:CYREG_DSM0_BUF1 +CYREG_DSM0_BUF1 EQU 0x4000589b + ENDIF + IF :LNOT::DEF:CYREG_DSM0_BUF2 +CYREG_DSM0_BUF2 EQU 0x4000589c + ENDIF + IF :LNOT::DEF:CYREG_DSM0_BUF3 +CYREG_DSM0_BUF3 EQU 0x4000589d + ENDIF + IF :LNOT::DEF:CYREG_DSM0_MISC +CYREG_DSM0_MISC EQU 0x4000589e + ENDIF + IF :LNOT::DEF:CYREG_DSM0_RSVD1 +CYREG_DSM0_RSVD1 EQU 0x4000589f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_BASE +CYDEV_ANAIF_CFG_SAR0_BASE EQU 0x40005900 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_SIZE +CYDEV_ANAIF_CFG_SAR0_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR0 +CYREG_SAR0_CSR0 EQU 0x40005900 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR1 +CYREG_SAR0_CSR1 EQU 0x40005901 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR2 +CYREG_SAR0_CSR2 EQU 0x40005902 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR3 +CYREG_SAR0_CSR3 EQU 0x40005903 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR4 +CYREG_SAR0_CSR4 EQU 0x40005904 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR5 +CYREG_SAR0_CSR5 EQU 0x40005905 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR6 +CYREG_SAR0_CSR6 EQU 0x40005906 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_BASE +CYDEV_ANAIF_CFG_SAR1_BASE EQU 0x40005908 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_SIZE +CYDEV_ANAIF_CFG_SAR1_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR0 +CYREG_SAR1_CSR0 EQU 0x40005908 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR1 +CYREG_SAR1_CSR1 EQU 0x40005909 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR2 +CYREG_SAR1_CSR2 EQU 0x4000590a + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR3 +CYREG_SAR1_CSR3 EQU 0x4000590b + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR4 +CYREG_SAR1_CSR4 EQU 0x4000590c + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR5 +CYREG_SAR1_CSR5 EQU 0x4000590d + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR6 +CYREG_SAR1_CSR6 EQU 0x4000590e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BASE +CYDEV_ANAIF_RT_BASE EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SIZE +CYDEV_ANAIF_RT_SIZE EQU 0x00000162 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_BASE +CYDEV_ANAIF_RT_SC0_BASE EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SIZE +CYDEV_ANAIF_RT_SC0_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW0 +CYREG_SC0_SW0 EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW2 +CYREG_SC0_SW2 EQU 0x40005a02 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW3 +CYREG_SC0_SW3 EQU 0x40005a03 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW4 +CYREG_SC0_SW4 EQU 0x40005a04 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW6 +CYREG_SC0_SW6 EQU 0x40005a06 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW7 +CYREG_SC0_SW7 EQU 0x40005a07 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW8 +CYREG_SC0_SW8 EQU 0x40005a08 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW10 +CYREG_SC0_SW10 EQU 0x40005a0a + ENDIF + IF :LNOT::DEF:CYREG_SC0_CLK +CYREG_SC0_CLK EQU 0x40005a0b + ENDIF + IF :LNOT::DEF:CYREG_SC0_BST +CYREG_SC0_BST EQU 0x40005a0c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_BASE +CYDEV_ANAIF_RT_SC1_BASE EQU 0x40005a10 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SIZE +CYDEV_ANAIF_RT_SC1_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW0 +CYREG_SC1_SW0 EQU 0x40005a10 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW2 +CYREG_SC1_SW2 EQU 0x40005a12 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW3 +CYREG_SC1_SW3 EQU 0x40005a13 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW4 +CYREG_SC1_SW4 EQU 0x40005a14 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW6 +CYREG_SC1_SW6 EQU 0x40005a16 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW7 +CYREG_SC1_SW7 EQU 0x40005a17 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW8 +CYREG_SC1_SW8 EQU 0x40005a18 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW10 +CYREG_SC1_SW10 EQU 0x40005a1a + ENDIF + IF :LNOT::DEF:CYREG_SC1_CLK +CYREG_SC1_CLK EQU 0x40005a1b + ENDIF + IF :LNOT::DEF:CYREG_SC1_BST +CYREG_SC1_BST EQU 0x40005a1c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_BASE +CYDEV_ANAIF_RT_SC2_BASE EQU 0x40005a20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SIZE +CYDEV_ANAIF_RT_SC2_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW0 +CYREG_SC2_SW0 EQU 0x40005a20 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW2 +CYREG_SC2_SW2 EQU 0x40005a22 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW3 +CYREG_SC2_SW3 EQU 0x40005a23 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW4 +CYREG_SC2_SW4 EQU 0x40005a24 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW6 +CYREG_SC2_SW6 EQU 0x40005a26 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW7 +CYREG_SC2_SW7 EQU 0x40005a27 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW8 +CYREG_SC2_SW8 EQU 0x40005a28 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW10 +CYREG_SC2_SW10 EQU 0x40005a2a + ENDIF + IF :LNOT::DEF:CYREG_SC2_CLK +CYREG_SC2_CLK EQU 0x40005a2b + ENDIF + IF :LNOT::DEF:CYREG_SC2_BST +CYREG_SC2_BST EQU 0x40005a2c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_BASE +CYDEV_ANAIF_RT_SC3_BASE EQU 0x40005a30 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SIZE +CYDEV_ANAIF_RT_SC3_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW0 +CYREG_SC3_SW0 EQU 0x40005a30 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW2 +CYREG_SC3_SW2 EQU 0x40005a32 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW3 +CYREG_SC3_SW3 EQU 0x40005a33 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW4 +CYREG_SC3_SW4 EQU 0x40005a34 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW6 +CYREG_SC3_SW6 EQU 0x40005a36 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW7 +CYREG_SC3_SW7 EQU 0x40005a37 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW8 +CYREG_SC3_SW8 EQU 0x40005a38 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW10 +CYREG_SC3_SW10 EQU 0x40005a3a + ENDIF + IF :LNOT::DEF:CYREG_SC3_CLK +CYREG_SC3_CLK EQU 0x40005a3b + ENDIF + IF :LNOT::DEF:CYREG_SC3_BST +CYREG_SC3_BST EQU 0x40005a3c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_BASE +CYDEV_ANAIF_RT_DAC0_BASE EQU 0x40005a80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SIZE +CYDEV_ANAIF_RT_DAC0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_SW0 +CYREG_DAC0_SW0 EQU 0x40005a80 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_SW2 +CYREG_DAC0_SW2 EQU 0x40005a82 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_SW3 +CYREG_DAC0_SW3 EQU 0x40005a83 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_SW4 +CYREG_DAC0_SW4 EQU 0x40005a84 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_STROBE +CYREG_DAC0_STROBE EQU 0x40005a87 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_BASE +CYDEV_ANAIF_RT_DAC1_BASE EQU 0x40005a88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SIZE +CYDEV_ANAIF_RT_DAC1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_SW0 +CYREG_DAC1_SW0 EQU 0x40005a88 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_SW2 +CYREG_DAC1_SW2 EQU 0x40005a8a + ENDIF + IF :LNOT::DEF:CYREG_DAC1_SW3 +CYREG_DAC1_SW3 EQU 0x40005a8b + ENDIF + IF :LNOT::DEF:CYREG_DAC1_SW4 +CYREG_DAC1_SW4 EQU 0x40005a8c + ENDIF + IF :LNOT::DEF:CYREG_DAC1_STROBE +CYREG_DAC1_STROBE EQU 0x40005a8f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_BASE +CYDEV_ANAIF_RT_DAC2_BASE EQU 0x40005a90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SIZE +CYDEV_ANAIF_RT_DAC2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_SW0 +CYREG_DAC2_SW0 EQU 0x40005a90 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_SW2 +CYREG_DAC2_SW2 EQU 0x40005a92 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_SW3 +CYREG_DAC2_SW3 EQU 0x40005a93 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_SW4 +CYREG_DAC2_SW4 EQU 0x40005a94 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_STROBE +CYREG_DAC2_STROBE EQU 0x40005a97 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_BASE +CYDEV_ANAIF_RT_DAC3_BASE EQU 0x40005a98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SIZE +CYDEV_ANAIF_RT_DAC3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_DAC3_SW0 +CYREG_DAC3_SW0 EQU 0x40005a98 + ENDIF + IF :LNOT::DEF:CYREG_DAC3_SW2 +CYREG_DAC3_SW2 EQU 0x40005a9a + ENDIF + IF :LNOT::DEF:CYREG_DAC3_SW3 +CYREG_DAC3_SW3 EQU 0x40005a9b + ENDIF + IF :LNOT::DEF:CYREG_DAC3_SW4 +CYREG_DAC3_SW4 EQU 0x40005a9c + ENDIF + IF :LNOT::DEF:CYREG_DAC3_STROBE +CYREG_DAC3_STROBE EQU 0x40005a9f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_BASE +CYDEV_ANAIF_RT_CMP0_BASE EQU 0x40005ac0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SIZE +CYDEV_ANAIF_RT_CMP0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_SW0 +CYREG_CMP0_SW0 EQU 0x40005ac0 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_SW2 +CYREG_CMP0_SW2 EQU 0x40005ac2 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_SW3 +CYREG_CMP0_SW3 EQU 0x40005ac3 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_SW4 +CYREG_CMP0_SW4 EQU 0x40005ac4 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_SW6 +CYREG_CMP0_SW6 EQU 0x40005ac6 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_CLK +CYREG_CMP0_CLK EQU 0x40005ac7 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_BASE +CYDEV_ANAIF_RT_CMP1_BASE EQU 0x40005ac8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SIZE +CYDEV_ANAIF_RT_CMP1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CMP1_SW0 +CYREG_CMP1_SW0 EQU 0x40005ac8 + ENDIF + IF :LNOT::DEF:CYREG_CMP1_SW2 +CYREG_CMP1_SW2 EQU 0x40005aca + ENDIF + IF :LNOT::DEF:CYREG_CMP1_SW3 +CYREG_CMP1_SW3 EQU 0x40005acb + ENDIF + IF :LNOT::DEF:CYREG_CMP1_SW4 +CYREG_CMP1_SW4 EQU 0x40005acc + ENDIF + IF :LNOT::DEF:CYREG_CMP1_SW6 +CYREG_CMP1_SW6 EQU 0x40005ace + ENDIF + IF :LNOT::DEF:CYREG_CMP1_CLK +CYREG_CMP1_CLK EQU 0x40005acf + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_BASE +CYDEV_ANAIF_RT_CMP2_BASE EQU 0x40005ad0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SIZE +CYDEV_ANAIF_RT_CMP2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_SW0 +CYREG_CMP2_SW0 EQU 0x40005ad0 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_SW2 +CYREG_CMP2_SW2 EQU 0x40005ad2 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_SW3 +CYREG_CMP2_SW3 EQU 0x40005ad3 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_SW4 +CYREG_CMP2_SW4 EQU 0x40005ad4 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_SW6 +CYREG_CMP2_SW6 EQU 0x40005ad6 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_CLK +CYREG_CMP2_CLK EQU 0x40005ad7 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_BASE +CYDEV_ANAIF_RT_CMP3_BASE EQU 0x40005ad8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SIZE +CYDEV_ANAIF_RT_CMP3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CMP3_SW0 +CYREG_CMP3_SW0 EQU 0x40005ad8 + ENDIF + IF :LNOT::DEF:CYREG_CMP3_SW2 +CYREG_CMP3_SW2 EQU 0x40005ada + ENDIF + IF :LNOT::DEF:CYREG_CMP3_SW3 +CYREG_CMP3_SW3 EQU 0x40005adb + ENDIF + IF :LNOT::DEF:CYREG_CMP3_SW4 +CYREG_CMP3_SW4 EQU 0x40005adc + ENDIF + IF :LNOT::DEF:CYREG_CMP3_SW6 +CYREG_CMP3_SW6 EQU 0x40005ade + ENDIF + IF :LNOT::DEF:CYREG_CMP3_CLK +CYREG_CMP3_CLK EQU 0x40005adf + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_BASE +CYDEV_ANAIF_RT_DSM0_BASE EQU 0x40005b00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SIZE +CYDEV_ANAIF_RT_DSM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_SW0 +CYREG_DSM0_SW0 EQU 0x40005b00 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_SW2 +CYREG_DSM0_SW2 EQU 0x40005b02 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_SW3 +CYREG_DSM0_SW3 EQU 0x40005b03 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_SW4 +CYREG_DSM0_SW4 EQU 0x40005b04 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_SW6 +CYREG_DSM0_SW6 EQU 0x40005b06 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CLK +CYREG_DSM0_CLK EQU 0x40005b07 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_BASE +CYDEV_ANAIF_RT_SAR0_BASE EQU 0x40005b20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SIZE +CYDEV_ANAIF_RT_SAR0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_SW0 +CYREG_SAR0_SW0 EQU 0x40005b20 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_SW2 +CYREG_SAR0_SW2 EQU 0x40005b22 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_SW3 +CYREG_SAR0_SW3 EQU 0x40005b23 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_SW4 +CYREG_SAR0_SW4 EQU 0x40005b24 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_SW6 +CYREG_SAR0_SW6 EQU 0x40005b26 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CLK +CYREG_SAR0_CLK EQU 0x40005b27 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_BASE +CYDEV_ANAIF_RT_SAR1_BASE EQU 0x40005b28 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SIZE +CYDEV_ANAIF_RT_SAR1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_SW0 +CYREG_SAR1_SW0 EQU 0x40005b28 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_SW2 +CYREG_SAR1_SW2 EQU 0x40005b2a + ENDIF + IF :LNOT::DEF:CYREG_SAR1_SW3 +CYREG_SAR1_SW3 EQU 0x40005b2b + ENDIF + IF :LNOT::DEF:CYREG_SAR1_SW4 +CYREG_SAR1_SW4 EQU 0x40005b2c + ENDIF + IF :LNOT::DEF:CYREG_SAR1_SW6 +CYREG_SAR1_SW6 EQU 0x40005b2e + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CLK +CYREG_SAR1_CLK EQU 0x40005b2f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_BASE +CYDEV_ANAIF_RT_OPAMP0_BASE EQU 0x40005b40 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_SIZE +CYDEV_ANAIF_RT_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_MX +CYREG_OPAMP0_MX EQU 0x40005b40 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_SW +CYREG_OPAMP0_SW EQU 0x40005b41 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_BASE +CYDEV_ANAIF_RT_OPAMP1_BASE EQU 0x40005b42 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_SIZE +CYDEV_ANAIF_RT_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_MX +CYREG_OPAMP1_MX EQU 0x40005b42 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_SW +CYREG_OPAMP1_SW EQU 0x40005b43 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_BASE +CYDEV_ANAIF_RT_OPAMP2_BASE EQU 0x40005b44 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_SIZE +CYDEV_ANAIF_RT_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_MX +CYREG_OPAMP2_MX EQU 0x40005b44 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_SW +CYREG_OPAMP2_SW EQU 0x40005b45 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_BASE +CYDEV_ANAIF_RT_OPAMP3_BASE EQU 0x40005b46 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_SIZE +CYDEV_ANAIF_RT_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_MX +CYREG_OPAMP3_MX EQU 0x40005b46 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_SW +CYREG_OPAMP3_SW EQU 0x40005b47 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_BASE +CYDEV_ANAIF_RT_LCDDAC_BASE EQU 0x40005b50 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SIZE +CYDEV_ANAIF_RT_LCDDAC_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_SW0 +CYREG_LCDDAC_SW0 EQU 0x40005b50 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_SW1 +CYREG_LCDDAC_SW1 EQU 0x40005b51 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_SW2 +CYREG_LCDDAC_SW2 EQU 0x40005b52 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_SW3 +CYREG_LCDDAC_SW3 EQU 0x40005b53 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_SW4 +CYREG_LCDDAC_SW4 EQU 0x40005b54 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_BASE +CYDEV_ANAIF_RT_SC_BASE EQU 0x40005b56 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_SIZE +CYDEV_ANAIF_RT_SC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SC_MISC +CYREG_SC_MISC EQU 0x40005b56 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_BASE +CYDEV_ANAIF_RT_BUS_BASE EQU 0x40005b58 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SIZE +CYDEV_ANAIF_RT_BUS_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_BUS_SW0 +CYREG_BUS_SW0 EQU 0x40005b58 + ENDIF + IF :LNOT::DEF:CYREG_BUS_SW2 +CYREG_BUS_SW2 EQU 0x40005b5a + ENDIF + IF :LNOT::DEF:CYREG_BUS_SW3 +CYREG_BUS_SW3 EQU 0x40005b5b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_BASE +CYDEV_ANAIF_RT_DFT_BASE EQU 0x40005b5c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_SIZE +CYDEV_ANAIF_RT_DFT_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR0 +CYREG_DFT_CR0 EQU 0x40005b5c + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR1 +CYREG_DFT_CR1 EQU 0x40005b5d + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR2 +CYREG_DFT_CR2 EQU 0x40005b5e + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR3 +CYREG_DFT_CR3 EQU 0x40005b5f + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR4 +CYREG_DFT_CR4 EQU 0x40005b60 + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR5 +CYREG_DFT_CR5 EQU 0x40005b61 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_BASE +CYDEV_ANAIF_WRK_BASE EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SIZE +CYDEV_ANAIF_WRK_SIZE EQU 0x00000029 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_BASE +CYDEV_ANAIF_WRK_DAC0_BASE EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_SIZE +CYDEV_ANAIF_WRK_DAC0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_D +CYREG_DAC0_D EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_BASE +CYDEV_ANAIF_WRK_DAC1_BASE EQU 0x40005b81 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_SIZE +CYDEV_ANAIF_WRK_DAC1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_D +CYREG_DAC1_D EQU 0x40005b81 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_BASE +CYDEV_ANAIF_WRK_DAC2_BASE EQU 0x40005b82 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_SIZE +CYDEV_ANAIF_WRK_DAC2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_D +CYREG_DAC2_D EQU 0x40005b82 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_BASE +CYDEV_ANAIF_WRK_DAC3_BASE EQU 0x40005b83 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_SIZE +CYDEV_ANAIF_WRK_DAC3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC3_D +CYREG_DAC3_D EQU 0x40005b83 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_BASE +CYDEV_ANAIF_WRK_DSM0_BASE EQU 0x40005b88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_SIZE +CYDEV_ANAIF_WRK_DSM0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_OUT0 +CYREG_DSM0_OUT0 EQU 0x40005b88 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_OUT1 +CYREG_DSM0_OUT1 EQU 0x40005b89 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_BASE +CYDEV_ANAIF_WRK_LUT_BASE EQU 0x40005b90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_SIZE +CYDEV_ANAIF_WRK_LUT_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_LUT_SR +CYREG_LUT_SR EQU 0x40005b90 + ENDIF + IF :LNOT::DEF:CYREG_LUT_WRK1 +CYREG_LUT_WRK1 EQU 0x40005b91 + ENDIF + IF :LNOT::DEF:CYREG_LUT_MSK +CYREG_LUT_MSK EQU 0x40005b92 + ENDIF + IF :LNOT::DEF:CYREG_LUT_CLK +CYREG_LUT_CLK EQU 0x40005b93 + ENDIF + IF :LNOT::DEF:CYREG_LUT_CPTR +CYREG_LUT_CPTR EQU 0x40005b94 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_BASE +CYDEV_ANAIF_WRK_CMP_BASE EQU 0x40005b96 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_SIZE +CYDEV_ANAIF_WRK_CMP_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CMP_WRK +CYREG_CMP_WRK EQU 0x40005b96 + ENDIF + IF :LNOT::DEF:CYREG_CMP_TST +CYREG_CMP_TST EQU 0x40005b97 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_BASE +CYDEV_ANAIF_WRK_SC_BASE EQU 0x40005b98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_SIZE +CYDEV_ANAIF_WRK_SC_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_SC_SR +CYREG_SC_SR EQU 0x40005b98 + ENDIF + IF :LNOT::DEF:CYREG_SC_WRK1 +CYREG_SC_WRK1 EQU 0x40005b99 + ENDIF + IF :LNOT::DEF:CYREG_SC_MSK +CYREG_SC_MSK EQU 0x40005b9a + ENDIF + IF :LNOT::DEF:CYREG_SC_CMPINV +CYREG_SC_CMPINV EQU 0x40005b9b + ENDIF + IF :LNOT::DEF:CYREG_SC_CPTR +CYREG_SC_CPTR EQU 0x40005b9c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_BASE +CYDEV_ANAIF_WRK_SAR0_BASE EQU 0x40005ba0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_SIZE +CYDEV_ANAIF_WRK_SAR0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_WRK0 +CYREG_SAR0_WRK0 EQU 0x40005ba0 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_WRK1 +CYREG_SAR0_WRK1 EQU 0x40005ba1 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_BASE +CYDEV_ANAIF_WRK_SAR1_BASE EQU 0x40005ba2 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_SIZE +CYDEV_ANAIF_WRK_SAR1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_WRK0 +CYREG_SAR1_WRK0 EQU 0x40005ba2 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_WRK1 +CYREG_SAR1_WRK1 EQU 0x40005ba3 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_BASE +CYDEV_ANAIF_WRK_SARS_BASE EQU 0x40005ba8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_SIZE +CYDEV_ANAIF_WRK_SARS_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_ANAIF_WRK_SARS_SOF +CYREG_ANAIF_WRK_SARS_SOF EQU 0x40005ba8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_BASE +CYDEV_USB_BASE EQU 0x40006000 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIZE +CYDEV_USB_SIZE EQU 0x00000300 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR0 +CYREG_USB_EP0_DR0 EQU 0x40006000 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR1 +CYREG_USB_EP0_DR1 EQU 0x40006001 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR2 +CYREG_USB_EP0_DR2 EQU 0x40006002 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR3 +CYREG_USB_EP0_DR3 EQU 0x40006003 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR4 +CYREG_USB_EP0_DR4 EQU 0x40006004 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR5 +CYREG_USB_EP0_DR5 EQU 0x40006005 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR6 +CYREG_USB_EP0_DR6 EQU 0x40006006 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR7 +CYREG_USB_EP0_DR7 EQU 0x40006007 + ENDIF + IF :LNOT::DEF:CYREG_USB_CR0 +CYREG_USB_CR0 EQU 0x40006008 + ENDIF + IF :LNOT::DEF:CYREG_USB_CR1 +CYREG_USB_CR1 EQU 0x40006009 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP_INT_EN +CYREG_USB_SIE_EP_INT_EN EQU 0x4000600a + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP_INT_SR +CYREG_USB_SIE_EP_INT_SR EQU 0x4000600b + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_BASE +CYDEV_USB_SIE_EP1_BASE EQU 0x4000600c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_SIZE +CYDEV_USB_SIE_EP1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP1_CNT0 +CYREG_USB_SIE_EP1_CNT0 EQU 0x4000600c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP1_CNT1 +CYREG_USB_SIE_EP1_CNT1 EQU 0x4000600d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP1_CR0 +CYREG_USB_SIE_EP1_CR0 EQU 0x4000600e + ENDIF + IF :LNOT::DEF:CYREG_USB_USBIO_CR0 +CYREG_USB_USBIO_CR0 EQU 0x40006010 + ENDIF + IF :LNOT::DEF:CYREG_USB_USBIO_CR1 +CYREG_USB_USBIO_CR1 EQU 0x40006012 + ENDIF + IF :LNOT::DEF:CYREG_USB_DYN_RECONFIG +CYREG_USB_DYN_RECONFIG EQU 0x40006014 + ENDIF + IF :LNOT::DEF:CYREG_USB_SOF0 +CYREG_USB_SOF0 EQU 0x40006018 + ENDIF + IF :LNOT::DEF:CYREG_USB_SOF1 +CYREG_USB_SOF1 EQU 0x40006019 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_BASE +CYDEV_USB_SIE_EP2_BASE EQU 0x4000601c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_SIZE +CYDEV_USB_SIE_EP2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP2_CNT0 +CYREG_USB_SIE_EP2_CNT0 EQU 0x4000601c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP2_CNT1 +CYREG_USB_SIE_EP2_CNT1 EQU 0x4000601d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP2_CR0 +CYREG_USB_SIE_EP2_CR0 EQU 0x4000601e + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_CR +CYREG_USB_EP0_CR EQU 0x40006028 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_CNT +CYREG_USB_EP0_CNT EQU 0x40006029 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_BASE +CYDEV_USB_SIE_EP3_BASE EQU 0x4000602c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_SIZE +CYDEV_USB_SIE_EP3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP3_CNT0 +CYREG_USB_SIE_EP3_CNT0 EQU 0x4000602c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP3_CNT1 +CYREG_USB_SIE_EP3_CNT1 EQU 0x4000602d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP3_CR0 +CYREG_USB_SIE_EP3_CR0 EQU 0x4000602e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_BASE +CYDEV_USB_SIE_EP4_BASE EQU 0x4000603c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_SIZE +CYDEV_USB_SIE_EP4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP4_CNT0 +CYREG_USB_SIE_EP4_CNT0 EQU 0x4000603c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP4_CNT1 +CYREG_USB_SIE_EP4_CNT1 EQU 0x4000603d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP4_CR0 +CYREG_USB_SIE_EP4_CR0 EQU 0x4000603e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_BASE +CYDEV_USB_SIE_EP5_BASE EQU 0x4000604c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_SIZE +CYDEV_USB_SIE_EP5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP5_CNT0 +CYREG_USB_SIE_EP5_CNT0 EQU 0x4000604c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP5_CNT1 +CYREG_USB_SIE_EP5_CNT1 EQU 0x4000604d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP5_CR0 +CYREG_USB_SIE_EP5_CR0 EQU 0x4000604e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_BASE +CYDEV_USB_SIE_EP6_BASE EQU 0x4000605c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_SIZE +CYDEV_USB_SIE_EP6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP6_CNT0 +CYREG_USB_SIE_EP6_CNT0 EQU 0x4000605c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP6_CNT1 +CYREG_USB_SIE_EP6_CNT1 EQU 0x4000605d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP6_CR0 +CYREG_USB_SIE_EP6_CR0 EQU 0x4000605e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_BASE +CYDEV_USB_SIE_EP7_BASE EQU 0x4000606c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_SIZE +CYDEV_USB_SIE_EP7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP7_CNT0 +CYREG_USB_SIE_EP7_CNT0 EQU 0x4000606c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP7_CNT1 +CYREG_USB_SIE_EP7_CNT1 EQU 0x4000606d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP7_CR0 +CYREG_USB_SIE_EP7_CR0 EQU 0x4000606e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_BASE +CYDEV_USB_SIE_EP8_BASE EQU 0x4000607c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_SIZE +CYDEV_USB_SIE_EP8_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP8_CNT0 +CYREG_USB_SIE_EP8_CNT0 EQU 0x4000607c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP8_CNT1 +CYREG_USB_SIE_EP8_CNT1 EQU 0x4000607d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP8_CR0 +CYREG_USB_SIE_EP8_CR0 EQU 0x4000607e + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_BASE +CYDEV_USB_ARB_EP1_BASE EQU 0x40006080 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_SIZE +CYDEV_USB_ARB_EP1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP1_CFG +CYREG_USB_ARB_EP1_CFG EQU 0x40006080 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP1_INT_EN +CYREG_USB_ARB_EP1_INT_EN EQU 0x40006081 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP1_SR +CYREG_USB_ARB_EP1_SR EQU 0x40006082 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_BASE +CYDEV_USB_ARB_RW1_BASE EQU 0x40006084 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_SIZE +CYDEV_USB_ARB_RW1_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW1_WA +CYREG_USB_ARB_RW1_WA EQU 0x40006084 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW1_WA_MSB +CYREG_USB_ARB_RW1_WA_MSB EQU 0x40006085 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW1_RA +CYREG_USB_ARB_RW1_RA EQU 0x40006086 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW1_RA_MSB +CYREG_USB_ARB_RW1_RA_MSB EQU 0x40006087 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW1_DR +CYREG_USB_ARB_RW1_DR EQU 0x40006088 + ENDIF + IF :LNOT::DEF:CYREG_USB_BUF_SIZE +CYREG_USB_BUF_SIZE EQU 0x4000608c + ENDIF + IF :LNOT::DEF:CYREG_USB_EP_ACTIVE +CYREG_USB_EP_ACTIVE EQU 0x4000608e + ENDIF + IF :LNOT::DEF:CYREG_USB_EP_TYPE +CYREG_USB_EP_TYPE EQU 0x4000608f + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_BASE +CYDEV_USB_ARB_EP2_BASE EQU 0x40006090 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_SIZE +CYDEV_USB_ARB_EP2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP2_CFG +CYREG_USB_ARB_EP2_CFG EQU 0x40006090 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP2_INT_EN +CYREG_USB_ARB_EP2_INT_EN EQU 0x40006091 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP2_SR +CYREG_USB_ARB_EP2_SR EQU 0x40006092 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_BASE +CYDEV_USB_ARB_RW2_BASE EQU 0x40006094 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_SIZE +CYDEV_USB_ARB_RW2_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW2_WA +CYREG_USB_ARB_RW2_WA EQU 0x40006094 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW2_WA_MSB +CYREG_USB_ARB_RW2_WA_MSB EQU 0x40006095 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW2_RA +CYREG_USB_ARB_RW2_RA EQU 0x40006096 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW2_RA_MSB +CYREG_USB_ARB_RW2_RA_MSB EQU 0x40006097 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW2_DR +CYREG_USB_ARB_RW2_DR EQU 0x40006098 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_CFG +CYREG_USB_ARB_CFG EQU 0x4000609c + ENDIF + IF :LNOT::DEF:CYREG_USB_USB_CLK_EN +CYREG_USB_USB_CLK_EN EQU 0x4000609d + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_INT_EN +CYREG_USB_ARB_INT_EN EQU 0x4000609e + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_INT_SR +CYREG_USB_ARB_INT_SR EQU 0x4000609f + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_BASE +CYDEV_USB_ARB_EP3_BASE EQU 0x400060a0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_SIZE +CYDEV_USB_ARB_EP3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP3_CFG +CYREG_USB_ARB_EP3_CFG EQU 0x400060a0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP3_INT_EN +CYREG_USB_ARB_EP3_INT_EN EQU 0x400060a1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP3_SR +CYREG_USB_ARB_EP3_SR EQU 0x400060a2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_BASE +CYDEV_USB_ARB_RW3_BASE EQU 0x400060a4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_SIZE +CYDEV_USB_ARB_RW3_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW3_WA +CYREG_USB_ARB_RW3_WA EQU 0x400060a4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW3_WA_MSB +CYREG_USB_ARB_RW3_WA_MSB EQU 0x400060a5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW3_RA +CYREG_USB_ARB_RW3_RA EQU 0x400060a6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW3_RA_MSB +CYREG_USB_ARB_RW3_RA_MSB EQU 0x400060a7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW3_DR +CYREG_USB_ARB_RW3_DR EQU 0x400060a8 + ENDIF + IF :LNOT::DEF:CYREG_USB_CWA +CYREG_USB_CWA EQU 0x400060ac + ENDIF + IF :LNOT::DEF:CYREG_USB_CWA_MSB +CYREG_USB_CWA_MSB EQU 0x400060ad + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_BASE +CYDEV_USB_ARB_EP4_BASE EQU 0x400060b0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_SIZE +CYDEV_USB_ARB_EP4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP4_CFG +CYREG_USB_ARB_EP4_CFG EQU 0x400060b0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP4_INT_EN +CYREG_USB_ARB_EP4_INT_EN EQU 0x400060b1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP4_SR +CYREG_USB_ARB_EP4_SR EQU 0x400060b2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_BASE +CYDEV_USB_ARB_RW4_BASE EQU 0x400060b4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_SIZE +CYDEV_USB_ARB_RW4_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW4_WA +CYREG_USB_ARB_RW4_WA EQU 0x400060b4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW4_WA_MSB +CYREG_USB_ARB_RW4_WA_MSB EQU 0x400060b5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW4_RA +CYREG_USB_ARB_RW4_RA EQU 0x400060b6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW4_RA_MSB +CYREG_USB_ARB_RW4_RA_MSB EQU 0x400060b7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW4_DR +CYREG_USB_ARB_RW4_DR EQU 0x400060b8 + ENDIF + IF :LNOT::DEF:CYREG_USB_DMA_THRES +CYREG_USB_DMA_THRES EQU 0x400060bc + ENDIF + IF :LNOT::DEF:CYREG_USB_DMA_THRES_MSB +CYREG_USB_DMA_THRES_MSB EQU 0x400060bd + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_BASE +CYDEV_USB_ARB_EP5_BASE EQU 0x400060c0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_SIZE +CYDEV_USB_ARB_EP5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP5_CFG +CYREG_USB_ARB_EP5_CFG EQU 0x400060c0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP5_INT_EN +CYREG_USB_ARB_EP5_INT_EN EQU 0x400060c1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP5_SR +CYREG_USB_ARB_EP5_SR EQU 0x400060c2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_BASE +CYDEV_USB_ARB_RW5_BASE EQU 0x400060c4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_SIZE +CYDEV_USB_ARB_RW5_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW5_WA +CYREG_USB_ARB_RW5_WA EQU 0x400060c4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW5_WA_MSB +CYREG_USB_ARB_RW5_WA_MSB EQU 0x400060c5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW5_RA +CYREG_USB_ARB_RW5_RA EQU 0x400060c6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW5_RA_MSB +CYREG_USB_ARB_RW5_RA_MSB EQU 0x400060c7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW5_DR +CYREG_USB_ARB_RW5_DR EQU 0x400060c8 + ENDIF + IF :LNOT::DEF:CYREG_USB_BUS_RST_CNT +CYREG_USB_BUS_RST_CNT EQU 0x400060cc + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_BASE +CYDEV_USB_ARB_EP6_BASE EQU 0x400060d0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_SIZE +CYDEV_USB_ARB_EP6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP6_CFG +CYREG_USB_ARB_EP6_CFG EQU 0x400060d0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP6_INT_EN +CYREG_USB_ARB_EP6_INT_EN EQU 0x400060d1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP6_SR +CYREG_USB_ARB_EP6_SR EQU 0x400060d2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_BASE +CYDEV_USB_ARB_RW6_BASE EQU 0x400060d4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_SIZE +CYDEV_USB_ARB_RW6_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW6_WA +CYREG_USB_ARB_RW6_WA EQU 0x400060d4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW6_WA_MSB +CYREG_USB_ARB_RW6_WA_MSB EQU 0x400060d5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW6_RA +CYREG_USB_ARB_RW6_RA EQU 0x400060d6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW6_RA_MSB +CYREG_USB_ARB_RW6_RA_MSB EQU 0x400060d7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW6_DR +CYREG_USB_ARB_RW6_DR EQU 0x400060d8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_BASE +CYDEV_USB_ARB_EP7_BASE EQU 0x400060e0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_SIZE +CYDEV_USB_ARB_EP7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP7_CFG +CYREG_USB_ARB_EP7_CFG EQU 0x400060e0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP7_INT_EN +CYREG_USB_ARB_EP7_INT_EN EQU 0x400060e1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP7_SR +CYREG_USB_ARB_EP7_SR EQU 0x400060e2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_BASE +CYDEV_USB_ARB_RW7_BASE EQU 0x400060e4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_SIZE +CYDEV_USB_ARB_RW7_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW7_WA +CYREG_USB_ARB_RW7_WA EQU 0x400060e4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW7_WA_MSB +CYREG_USB_ARB_RW7_WA_MSB EQU 0x400060e5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW7_RA +CYREG_USB_ARB_RW7_RA EQU 0x400060e6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW7_RA_MSB +CYREG_USB_ARB_RW7_RA_MSB EQU 0x400060e7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW7_DR +CYREG_USB_ARB_RW7_DR EQU 0x400060e8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_BASE +CYDEV_USB_ARB_EP8_BASE EQU 0x400060f0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_SIZE +CYDEV_USB_ARB_EP8_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP8_CFG +CYREG_USB_ARB_EP8_CFG EQU 0x400060f0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP8_INT_EN +CYREG_USB_ARB_EP8_INT_EN EQU 0x400060f1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP8_SR +CYREG_USB_ARB_EP8_SR EQU 0x400060f2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_BASE +CYDEV_USB_ARB_RW8_BASE EQU 0x400060f4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_SIZE +CYDEV_USB_ARB_RW8_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW8_WA +CYREG_USB_ARB_RW8_WA EQU 0x400060f4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW8_WA_MSB +CYREG_USB_ARB_RW8_WA_MSB EQU 0x400060f5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW8_RA +CYREG_USB_ARB_RW8_RA EQU 0x400060f6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW8_RA_MSB +CYREG_USB_ARB_RW8_RA_MSB EQU 0x400060f7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW8_DR +CYREG_USB_ARB_RW8_DR EQU 0x400060f8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_BASE +CYDEV_USB_MEM_BASE EQU 0x40006100 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_SIZE +CYDEV_USB_MEM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYREG_USB_MEM_DATA_MBASE +CYREG_USB_MEM_DATA_MBASE EQU 0x40006100 + ENDIF + IF :LNOT::DEF:CYREG_USB_MEM_DATA_MSIZE +CYREG_USB_MEM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_BASE +CYDEV_UWRK_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_SIZE +CYDEV_UWRK_SIZE EQU 0x00000b60 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_BASE +CYDEV_UWRK_UWRK8_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_SIZE +CYDEV_UWRK_UWRK8_SIZE EQU 0x000003b0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_BASE +CYDEV_UWRK_UWRK8_B0_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_SIZE +CYDEV_UWRK_UWRK8_B0_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_A0 +CYREG_B0_UDB00_A0 EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_A0 +CYREG_B0_UDB01_A0 EQU 0x40006401 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_A0 +CYREG_B0_UDB02_A0 EQU 0x40006402 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_A0 +CYREG_B0_UDB03_A0 EQU 0x40006403 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_A0 +CYREG_B0_UDB04_A0 EQU 0x40006404 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_A0 +CYREG_B0_UDB05_A0 EQU 0x40006405 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_A0 +CYREG_B0_UDB06_A0 EQU 0x40006406 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_A0 +CYREG_B0_UDB07_A0 EQU 0x40006407 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_A0 +CYREG_B0_UDB08_A0 EQU 0x40006408 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_A0 +CYREG_B0_UDB09_A0 EQU 0x40006409 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_A0 +CYREG_B0_UDB10_A0 EQU 0x4000640a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_A0 +CYREG_B0_UDB11_A0 EQU 0x4000640b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_A0 +CYREG_B0_UDB12_A0 EQU 0x4000640c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_A0 +CYREG_B0_UDB13_A0 EQU 0x4000640d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_A0 +CYREG_B0_UDB14_A0 EQU 0x4000640e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_A0 +CYREG_B0_UDB15_A0 EQU 0x4000640f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_A1 +CYREG_B0_UDB00_A1 EQU 0x40006410 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_A1 +CYREG_B0_UDB01_A1 EQU 0x40006411 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_A1 +CYREG_B0_UDB02_A1 EQU 0x40006412 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_A1 +CYREG_B0_UDB03_A1 EQU 0x40006413 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_A1 +CYREG_B0_UDB04_A1 EQU 0x40006414 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_A1 +CYREG_B0_UDB05_A1 EQU 0x40006415 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_A1 +CYREG_B0_UDB06_A1 EQU 0x40006416 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_A1 +CYREG_B0_UDB07_A1 EQU 0x40006417 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_A1 +CYREG_B0_UDB08_A1 EQU 0x40006418 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_A1 +CYREG_B0_UDB09_A1 EQU 0x40006419 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_A1 +CYREG_B0_UDB10_A1 EQU 0x4000641a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_A1 +CYREG_B0_UDB11_A1 EQU 0x4000641b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_A1 +CYREG_B0_UDB12_A1 EQU 0x4000641c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_A1 +CYREG_B0_UDB13_A1 EQU 0x4000641d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_A1 +CYREG_B0_UDB14_A1 EQU 0x4000641e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_A1 +CYREG_B0_UDB15_A1 EQU 0x4000641f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_D0 +CYREG_B0_UDB00_D0 EQU 0x40006420 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_D0 +CYREG_B0_UDB01_D0 EQU 0x40006421 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_D0 +CYREG_B0_UDB02_D0 EQU 0x40006422 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_D0 +CYREG_B0_UDB03_D0 EQU 0x40006423 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_D0 +CYREG_B0_UDB04_D0 EQU 0x40006424 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_D0 +CYREG_B0_UDB05_D0 EQU 0x40006425 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_D0 +CYREG_B0_UDB06_D0 EQU 0x40006426 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_D0 +CYREG_B0_UDB07_D0 EQU 0x40006427 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_D0 +CYREG_B0_UDB08_D0 EQU 0x40006428 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_D0 +CYREG_B0_UDB09_D0 EQU 0x40006429 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_D0 +CYREG_B0_UDB10_D0 EQU 0x4000642a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_D0 +CYREG_B0_UDB11_D0 EQU 0x4000642b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_D0 +CYREG_B0_UDB12_D0 EQU 0x4000642c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_D0 +CYREG_B0_UDB13_D0 EQU 0x4000642d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_D0 +CYREG_B0_UDB14_D0 EQU 0x4000642e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_D0 +CYREG_B0_UDB15_D0 EQU 0x4000642f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_D1 +CYREG_B0_UDB00_D1 EQU 0x40006430 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_D1 +CYREG_B0_UDB01_D1 EQU 0x40006431 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_D1 +CYREG_B0_UDB02_D1 EQU 0x40006432 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_D1 +CYREG_B0_UDB03_D1 EQU 0x40006433 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_D1 +CYREG_B0_UDB04_D1 EQU 0x40006434 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_D1 +CYREG_B0_UDB05_D1 EQU 0x40006435 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_D1 +CYREG_B0_UDB06_D1 EQU 0x40006436 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_D1 +CYREG_B0_UDB07_D1 EQU 0x40006437 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_D1 +CYREG_B0_UDB08_D1 EQU 0x40006438 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_D1 +CYREG_B0_UDB09_D1 EQU 0x40006439 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_D1 +CYREG_B0_UDB10_D1 EQU 0x4000643a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_D1 +CYREG_B0_UDB11_D1 EQU 0x4000643b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_D1 +CYREG_B0_UDB12_D1 EQU 0x4000643c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_D1 +CYREG_B0_UDB13_D1 EQU 0x4000643d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_D1 +CYREG_B0_UDB14_D1 EQU 0x4000643e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_D1 +CYREG_B0_UDB15_D1 EQU 0x4000643f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_F0 +CYREG_B0_UDB00_F0 EQU 0x40006440 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_F0 +CYREG_B0_UDB01_F0 EQU 0x40006441 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_F0 +CYREG_B0_UDB02_F0 EQU 0x40006442 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_F0 +CYREG_B0_UDB03_F0 EQU 0x40006443 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_F0 +CYREG_B0_UDB04_F0 EQU 0x40006444 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_F0 +CYREG_B0_UDB05_F0 EQU 0x40006445 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_F0 +CYREG_B0_UDB06_F0 EQU 0x40006446 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_F0 +CYREG_B0_UDB07_F0 EQU 0x40006447 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_F0 +CYREG_B0_UDB08_F0 EQU 0x40006448 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_F0 +CYREG_B0_UDB09_F0 EQU 0x40006449 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_F0 +CYREG_B0_UDB10_F0 EQU 0x4000644a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_F0 +CYREG_B0_UDB11_F0 EQU 0x4000644b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_F0 +CYREG_B0_UDB12_F0 EQU 0x4000644c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_F0 +CYREG_B0_UDB13_F0 EQU 0x4000644d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_F0 +CYREG_B0_UDB14_F0 EQU 0x4000644e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_F0 +CYREG_B0_UDB15_F0 EQU 0x4000644f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_F1 +CYREG_B0_UDB00_F1 EQU 0x40006450 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_F1 +CYREG_B0_UDB01_F1 EQU 0x40006451 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_F1 +CYREG_B0_UDB02_F1 EQU 0x40006452 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_F1 +CYREG_B0_UDB03_F1 EQU 0x40006453 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_F1 +CYREG_B0_UDB04_F1 EQU 0x40006454 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_F1 +CYREG_B0_UDB05_F1 EQU 0x40006455 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_F1 +CYREG_B0_UDB06_F1 EQU 0x40006456 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_F1 +CYREG_B0_UDB07_F1 EQU 0x40006457 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_F1 +CYREG_B0_UDB08_F1 EQU 0x40006458 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_F1 +CYREG_B0_UDB09_F1 EQU 0x40006459 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_F1 +CYREG_B0_UDB10_F1 EQU 0x4000645a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_F1 +CYREG_B0_UDB11_F1 EQU 0x4000645b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_F1 +CYREG_B0_UDB12_F1 EQU 0x4000645c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_F1 +CYREG_B0_UDB13_F1 EQU 0x4000645d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_F1 +CYREG_B0_UDB14_F1 EQU 0x4000645e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_F1 +CYREG_B0_UDB15_F1 EQU 0x4000645f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_ST +CYREG_B0_UDB00_ST EQU 0x40006460 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_ST +CYREG_B0_UDB01_ST EQU 0x40006461 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_ST +CYREG_B0_UDB02_ST EQU 0x40006462 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_ST +CYREG_B0_UDB03_ST EQU 0x40006463 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_ST +CYREG_B0_UDB04_ST EQU 0x40006464 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_ST +CYREG_B0_UDB05_ST EQU 0x40006465 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_ST +CYREG_B0_UDB06_ST EQU 0x40006466 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_ST +CYREG_B0_UDB07_ST EQU 0x40006467 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_ST +CYREG_B0_UDB08_ST EQU 0x40006468 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_ST +CYREG_B0_UDB09_ST EQU 0x40006469 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_ST +CYREG_B0_UDB10_ST EQU 0x4000646a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_ST +CYREG_B0_UDB11_ST EQU 0x4000646b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_ST +CYREG_B0_UDB12_ST EQU 0x4000646c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_ST +CYREG_B0_UDB13_ST EQU 0x4000646d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_ST +CYREG_B0_UDB14_ST EQU 0x4000646e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_ST +CYREG_B0_UDB15_ST EQU 0x4000646f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_CTL +CYREG_B0_UDB00_CTL EQU 0x40006470 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_CTL +CYREG_B0_UDB01_CTL EQU 0x40006471 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_CTL +CYREG_B0_UDB02_CTL EQU 0x40006472 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_CTL +CYREG_B0_UDB03_CTL EQU 0x40006473 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_CTL +CYREG_B0_UDB04_CTL EQU 0x40006474 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_CTL +CYREG_B0_UDB05_CTL EQU 0x40006475 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_CTL +CYREG_B0_UDB06_CTL EQU 0x40006476 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_CTL +CYREG_B0_UDB07_CTL EQU 0x40006477 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_CTL +CYREG_B0_UDB08_CTL EQU 0x40006478 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_CTL +CYREG_B0_UDB09_CTL EQU 0x40006479 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_CTL +CYREG_B0_UDB10_CTL EQU 0x4000647a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_CTL +CYREG_B0_UDB11_CTL EQU 0x4000647b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_CTL +CYREG_B0_UDB12_CTL EQU 0x4000647c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_CTL +CYREG_B0_UDB13_CTL EQU 0x4000647d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_CTL +CYREG_B0_UDB14_CTL EQU 0x4000647e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_CTL +CYREG_B0_UDB15_CTL EQU 0x4000647f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_MSK +CYREG_B0_UDB00_MSK EQU 0x40006480 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_MSK +CYREG_B0_UDB01_MSK EQU 0x40006481 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_MSK +CYREG_B0_UDB02_MSK EQU 0x40006482 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_MSK +CYREG_B0_UDB03_MSK EQU 0x40006483 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_MSK +CYREG_B0_UDB04_MSK EQU 0x40006484 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_MSK +CYREG_B0_UDB05_MSK EQU 0x40006485 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_MSK +CYREG_B0_UDB06_MSK EQU 0x40006486 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_MSK +CYREG_B0_UDB07_MSK EQU 0x40006487 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_MSK +CYREG_B0_UDB08_MSK EQU 0x40006488 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_MSK +CYREG_B0_UDB09_MSK EQU 0x40006489 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_MSK +CYREG_B0_UDB10_MSK EQU 0x4000648a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_MSK +CYREG_B0_UDB11_MSK EQU 0x4000648b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_MSK +CYREG_B0_UDB12_MSK EQU 0x4000648c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_MSK +CYREG_B0_UDB13_MSK EQU 0x4000648d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_MSK +CYREG_B0_UDB14_MSK EQU 0x4000648e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_MSK +CYREG_B0_UDB15_MSK EQU 0x4000648f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_ACTL +CYREG_B0_UDB00_ACTL EQU 0x40006490 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_ACTL +CYREG_B0_UDB01_ACTL EQU 0x40006491 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_ACTL +CYREG_B0_UDB02_ACTL EQU 0x40006492 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_ACTL +CYREG_B0_UDB03_ACTL EQU 0x40006493 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_ACTL +CYREG_B0_UDB04_ACTL EQU 0x40006494 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_ACTL +CYREG_B0_UDB05_ACTL EQU 0x40006495 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_ACTL +CYREG_B0_UDB06_ACTL EQU 0x40006496 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_ACTL +CYREG_B0_UDB07_ACTL EQU 0x40006497 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_ACTL +CYREG_B0_UDB08_ACTL EQU 0x40006498 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_ACTL +CYREG_B0_UDB09_ACTL EQU 0x40006499 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_ACTL +CYREG_B0_UDB10_ACTL EQU 0x4000649a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_ACTL +CYREG_B0_UDB11_ACTL EQU 0x4000649b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_ACTL +CYREG_B0_UDB12_ACTL EQU 0x4000649c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_ACTL +CYREG_B0_UDB13_ACTL EQU 0x4000649d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_ACTL +CYREG_B0_UDB14_ACTL EQU 0x4000649e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_ACTL +CYREG_B0_UDB15_ACTL EQU 0x4000649f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_MC +CYREG_B0_UDB00_MC EQU 0x400064a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_MC +CYREG_B0_UDB01_MC EQU 0x400064a1 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_MC +CYREG_B0_UDB02_MC EQU 0x400064a2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_MC +CYREG_B0_UDB03_MC EQU 0x400064a3 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_MC +CYREG_B0_UDB04_MC EQU 0x400064a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_MC +CYREG_B0_UDB05_MC EQU 0x400064a5 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_MC +CYREG_B0_UDB06_MC EQU 0x400064a6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_MC +CYREG_B0_UDB07_MC EQU 0x400064a7 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_MC +CYREG_B0_UDB08_MC EQU 0x400064a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_MC +CYREG_B0_UDB09_MC EQU 0x400064a9 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_MC +CYREG_B0_UDB10_MC EQU 0x400064aa + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_MC +CYREG_B0_UDB11_MC EQU 0x400064ab + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_MC +CYREG_B0_UDB12_MC EQU 0x400064ac + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_MC +CYREG_B0_UDB13_MC EQU 0x400064ad + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_MC +CYREG_B0_UDB14_MC EQU 0x400064ae + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_MC +CYREG_B0_UDB15_MC EQU 0x400064af + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_BASE +CYDEV_UWRK_UWRK8_B1_BASE EQU 0x40006500 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_SIZE +CYDEV_UWRK_UWRK8_B1_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_A0 +CYREG_B1_UDB04_A0 EQU 0x40006504 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_A0 +CYREG_B1_UDB05_A0 EQU 0x40006505 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_A0 +CYREG_B1_UDB06_A0 EQU 0x40006506 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_A0 +CYREG_B1_UDB07_A0 EQU 0x40006507 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_A0 +CYREG_B1_UDB08_A0 EQU 0x40006508 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_A0 +CYREG_B1_UDB09_A0 EQU 0x40006509 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_A0 +CYREG_B1_UDB10_A0 EQU 0x4000650a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_A0 +CYREG_B1_UDB11_A0 EQU 0x4000650b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_A1 +CYREG_B1_UDB04_A1 EQU 0x40006514 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_A1 +CYREG_B1_UDB05_A1 EQU 0x40006515 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_A1 +CYREG_B1_UDB06_A1 EQU 0x40006516 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_A1 +CYREG_B1_UDB07_A1 EQU 0x40006517 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_A1 +CYREG_B1_UDB08_A1 EQU 0x40006518 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_A1 +CYREG_B1_UDB09_A1 EQU 0x40006519 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_A1 +CYREG_B1_UDB10_A1 EQU 0x4000651a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_A1 +CYREG_B1_UDB11_A1 EQU 0x4000651b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_D0 +CYREG_B1_UDB04_D0 EQU 0x40006524 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_D0 +CYREG_B1_UDB05_D0 EQU 0x40006525 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_D0 +CYREG_B1_UDB06_D0 EQU 0x40006526 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_D0 +CYREG_B1_UDB07_D0 EQU 0x40006527 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_D0 +CYREG_B1_UDB08_D0 EQU 0x40006528 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_D0 +CYREG_B1_UDB09_D0 EQU 0x40006529 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_D0 +CYREG_B1_UDB10_D0 EQU 0x4000652a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_D0 +CYREG_B1_UDB11_D0 EQU 0x4000652b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_D1 +CYREG_B1_UDB04_D1 EQU 0x40006534 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_D1 +CYREG_B1_UDB05_D1 EQU 0x40006535 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_D1 +CYREG_B1_UDB06_D1 EQU 0x40006536 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_D1 +CYREG_B1_UDB07_D1 EQU 0x40006537 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_D1 +CYREG_B1_UDB08_D1 EQU 0x40006538 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_D1 +CYREG_B1_UDB09_D1 EQU 0x40006539 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_D1 +CYREG_B1_UDB10_D1 EQU 0x4000653a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_D1 +CYREG_B1_UDB11_D1 EQU 0x4000653b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_F0 +CYREG_B1_UDB04_F0 EQU 0x40006544 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_F0 +CYREG_B1_UDB05_F0 EQU 0x40006545 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_F0 +CYREG_B1_UDB06_F0 EQU 0x40006546 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_F0 +CYREG_B1_UDB07_F0 EQU 0x40006547 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_F0 +CYREG_B1_UDB08_F0 EQU 0x40006548 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_F0 +CYREG_B1_UDB09_F0 EQU 0x40006549 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_F0 +CYREG_B1_UDB10_F0 EQU 0x4000654a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_F0 +CYREG_B1_UDB11_F0 EQU 0x4000654b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_F1 +CYREG_B1_UDB04_F1 EQU 0x40006554 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_F1 +CYREG_B1_UDB05_F1 EQU 0x40006555 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_F1 +CYREG_B1_UDB06_F1 EQU 0x40006556 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_F1 +CYREG_B1_UDB07_F1 EQU 0x40006557 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_F1 +CYREG_B1_UDB08_F1 EQU 0x40006558 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_F1 +CYREG_B1_UDB09_F1 EQU 0x40006559 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_F1 +CYREG_B1_UDB10_F1 EQU 0x4000655a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_F1 +CYREG_B1_UDB11_F1 EQU 0x4000655b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_ST +CYREG_B1_UDB04_ST EQU 0x40006564 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_ST +CYREG_B1_UDB05_ST EQU 0x40006565 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_ST +CYREG_B1_UDB06_ST EQU 0x40006566 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_ST +CYREG_B1_UDB07_ST EQU 0x40006567 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_ST +CYREG_B1_UDB08_ST EQU 0x40006568 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_ST +CYREG_B1_UDB09_ST EQU 0x40006569 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_ST +CYREG_B1_UDB10_ST EQU 0x4000656a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_ST +CYREG_B1_UDB11_ST EQU 0x4000656b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_CTL +CYREG_B1_UDB04_CTL EQU 0x40006574 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_CTL +CYREG_B1_UDB05_CTL EQU 0x40006575 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_CTL +CYREG_B1_UDB06_CTL EQU 0x40006576 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_CTL +CYREG_B1_UDB07_CTL EQU 0x40006577 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_CTL +CYREG_B1_UDB08_CTL EQU 0x40006578 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_CTL +CYREG_B1_UDB09_CTL EQU 0x40006579 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_CTL +CYREG_B1_UDB10_CTL EQU 0x4000657a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_CTL +CYREG_B1_UDB11_CTL EQU 0x4000657b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_MSK +CYREG_B1_UDB04_MSK EQU 0x40006584 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_MSK +CYREG_B1_UDB05_MSK EQU 0x40006585 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_MSK +CYREG_B1_UDB06_MSK EQU 0x40006586 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_MSK +CYREG_B1_UDB07_MSK EQU 0x40006587 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_MSK +CYREG_B1_UDB08_MSK EQU 0x40006588 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_MSK +CYREG_B1_UDB09_MSK EQU 0x40006589 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_MSK +CYREG_B1_UDB10_MSK EQU 0x4000658a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_MSK +CYREG_B1_UDB11_MSK EQU 0x4000658b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_ACTL +CYREG_B1_UDB04_ACTL EQU 0x40006594 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_ACTL +CYREG_B1_UDB05_ACTL EQU 0x40006595 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_ACTL +CYREG_B1_UDB06_ACTL EQU 0x40006596 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_ACTL +CYREG_B1_UDB07_ACTL EQU 0x40006597 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_ACTL +CYREG_B1_UDB08_ACTL EQU 0x40006598 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_ACTL +CYREG_B1_UDB09_ACTL EQU 0x40006599 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_ACTL +CYREG_B1_UDB10_ACTL EQU 0x4000659a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_ACTL +CYREG_B1_UDB11_ACTL EQU 0x4000659b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_MC +CYREG_B1_UDB04_MC EQU 0x400065a4 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_MC +CYREG_B1_UDB05_MC EQU 0x400065a5 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_MC +CYREG_B1_UDB06_MC EQU 0x400065a6 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_MC +CYREG_B1_UDB07_MC EQU 0x400065a7 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_MC +CYREG_B1_UDB08_MC EQU 0x400065a8 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_MC +CYREG_B1_UDB09_MC EQU 0x400065a9 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_MC +CYREG_B1_UDB10_MC EQU 0x400065aa + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_MC +CYREG_B1_UDB11_MC EQU 0x400065ab + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_BASE +CYDEV_UWRK_UWRK16_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_SIZE +CYDEV_UWRK_UWRK16_SIZE EQU 0x00000760 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_BASE +CYDEV_UWRK_UWRK16_CAT_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_SIZE +CYDEV_UWRK_UWRK16_CAT_SIZE EQU 0x00000760 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_BASE +CYDEV_UWRK_UWRK16_CAT_B0_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_SIZE +CYDEV_UWRK_UWRK16_CAT_B0_SIZE EQU 0x00000160 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_A0_A1 +CYREG_B0_UDB00_A0_A1 EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_A0_A1 +CYREG_B0_UDB01_A0_A1 EQU 0x40006802 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_A0_A1 +CYREG_B0_UDB02_A0_A1 EQU 0x40006804 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_A0_A1 +CYREG_B0_UDB03_A0_A1 EQU 0x40006806 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_A0_A1 +CYREG_B0_UDB04_A0_A1 EQU 0x40006808 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_A0_A1 +CYREG_B0_UDB05_A0_A1 EQU 0x4000680a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_A0_A1 +CYREG_B0_UDB06_A0_A1 EQU 0x4000680c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_A0_A1 +CYREG_B0_UDB07_A0_A1 EQU 0x4000680e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_A0_A1 +CYREG_B0_UDB08_A0_A1 EQU 0x40006810 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_A0_A1 +CYREG_B0_UDB09_A0_A1 EQU 0x40006812 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_A0_A1 +CYREG_B0_UDB10_A0_A1 EQU 0x40006814 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_A0_A1 +CYREG_B0_UDB11_A0_A1 EQU 0x40006816 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_A0_A1 +CYREG_B0_UDB12_A0_A1 EQU 0x40006818 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_A0_A1 +CYREG_B0_UDB13_A0_A1 EQU 0x4000681a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_A0_A1 +CYREG_B0_UDB14_A0_A1 EQU 0x4000681c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_A0_A1 +CYREG_B0_UDB15_A0_A1 EQU 0x4000681e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_D0_D1 +CYREG_B0_UDB00_D0_D1 EQU 0x40006840 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_D0_D1 +CYREG_B0_UDB01_D0_D1 EQU 0x40006842 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_D0_D1 +CYREG_B0_UDB02_D0_D1 EQU 0x40006844 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_D0_D1 +CYREG_B0_UDB03_D0_D1 EQU 0x40006846 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_D0_D1 +CYREG_B0_UDB04_D0_D1 EQU 0x40006848 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_D0_D1 +CYREG_B0_UDB05_D0_D1 EQU 0x4000684a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_D0_D1 +CYREG_B0_UDB06_D0_D1 EQU 0x4000684c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_D0_D1 +CYREG_B0_UDB07_D0_D1 EQU 0x4000684e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_D0_D1 +CYREG_B0_UDB08_D0_D1 EQU 0x40006850 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_D0_D1 +CYREG_B0_UDB09_D0_D1 EQU 0x40006852 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_D0_D1 +CYREG_B0_UDB10_D0_D1 EQU 0x40006854 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_D0_D1 +CYREG_B0_UDB11_D0_D1 EQU 0x40006856 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_D0_D1 +CYREG_B0_UDB12_D0_D1 EQU 0x40006858 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_D0_D1 +CYREG_B0_UDB13_D0_D1 EQU 0x4000685a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_D0_D1 +CYREG_B0_UDB14_D0_D1 EQU 0x4000685c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_D0_D1 +CYREG_B0_UDB15_D0_D1 EQU 0x4000685e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_F0_F1 +CYREG_B0_UDB00_F0_F1 EQU 0x40006880 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_F0_F1 +CYREG_B0_UDB01_F0_F1 EQU 0x40006882 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_F0_F1 +CYREG_B0_UDB02_F0_F1 EQU 0x40006884 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_F0_F1 +CYREG_B0_UDB03_F0_F1 EQU 0x40006886 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_F0_F1 +CYREG_B0_UDB04_F0_F1 EQU 0x40006888 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_F0_F1 +CYREG_B0_UDB05_F0_F1 EQU 0x4000688a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_F0_F1 +CYREG_B0_UDB06_F0_F1 EQU 0x4000688c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_F0_F1 +CYREG_B0_UDB07_F0_F1 EQU 0x4000688e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_F0_F1 +CYREG_B0_UDB08_F0_F1 EQU 0x40006890 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_F0_F1 +CYREG_B0_UDB09_F0_F1 EQU 0x40006892 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_F0_F1 +CYREG_B0_UDB10_F0_F1 EQU 0x40006894 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_F0_F1 +CYREG_B0_UDB11_F0_F1 EQU 0x40006896 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_F0_F1 +CYREG_B0_UDB12_F0_F1 EQU 0x40006898 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_F0_F1 +CYREG_B0_UDB13_F0_F1 EQU 0x4000689a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_F0_F1 +CYREG_B0_UDB14_F0_F1 EQU 0x4000689c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_F0_F1 +CYREG_B0_UDB15_F0_F1 EQU 0x4000689e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_ST_CTL +CYREG_B0_UDB00_ST_CTL EQU 0x400068c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_ST_CTL +CYREG_B0_UDB01_ST_CTL EQU 0x400068c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_ST_CTL +CYREG_B0_UDB02_ST_CTL EQU 0x400068c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_ST_CTL +CYREG_B0_UDB03_ST_CTL EQU 0x400068c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_ST_CTL +CYREG_B0_UDB04_ST_CTL EQU 0x400068c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_ST_CTL +CYREG_B0_UDB05_ST_CTL EQU 0x400068ca + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_ST_CTL +CYREG_B0_UDB06_ST_CTL EQU 0x400068cc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_ST_CTL +CYREG_B0_UDB07_ST_CTL EQU 0x400068ce + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_ST_CTL +CYREG_B0_UDB08_ST_CTL EQU 0x400068d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_ST_CTL +CYREG_B0_UDB09_ST_CTL EQU 0x400068d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_ST_CTL +CYREG_B0_UDB10_ST_CTL EQU 0x400068d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_ST_CTL +CYREG_B0_UDB11_ST_CTL EQU 0x400068d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_ST_CTL +CYREG_B0_UDB12_ST_CTL EQU 0x400068d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_ST_CTL +CYREG_B0_UDB13_ST_CTL EQU 0x400068da + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_ST_CTL +CYREG_B0_UDB14_ST_CTL EQU 0x400068dc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_ST_CTL +CYREG_B0_UDB15_ST_CTL EQU 0x400068de + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_MSK_ACTL +CYREG_B0_UDB00_MSK_ACTL EQU 0x40006900 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_MSK_ACTL +CYREG_B0_UDB01_MSK_ACTL EQU 0x40006902 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_MSK_ACTL +CYREG_B0_UDB02_MSK_ACTL EQU 0x40006904 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_MSK_ACTL +CYREG_B0_UDB03_MSK_ACTL EQU 0x40006906 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_MSK_ACTL +CYREG_B0_UDB04_MSK_ACTL EQU 0x40006908 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_MSK_ACTL +CYREG_B0_UDB05_MSK_ACTL EQU 0x4000690a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_MSK_ACTL +CYREG_B0_UDB06_MSK_ACTL EQU 0x4000690c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_MSK_ACTL +CYREG_B0_UDB07_MSK_ACTL EQU 0x4000690e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_MSK_ACTL +CYREG_B0_UDB08_MSK_ACTL EQU 0x40006910 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_MSK_ACTL +CYREG_B0_UDB09_MSK_ACTL EQU 0x40006912 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_MSK_ACTL +CYREG_B0_UDB10_MSK_ACTL EQU 0x40006914 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_MSK_ACTL +CYREG_B0_UDB11_MSK_ACTL EQU 0x40006916 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_MSK_ACTL +CYREG_B0_UDB12_MSK_ACTL EQU 0x40006918 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_MSK_ACTL +CYREG_B0_UDB13_MSK_ACTL EQU 0x4000691a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_MSK_ACTL +CYREG_B0_UDB14_MSK_ACTL EQU 0x4000691c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_MSK_ACTL +CYREG_B0_UDB15_MSK_ACTL EQU 0x4000691e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_MC_00 +CYREG_B0_UDB00_MC_00 EQU 0x40006940 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_MC_00 +CYREG_B0_UDB01_MC_00 EQU 0x40006942 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_MC_00 +CYREG_B0_UDB02_MC_00 EQU 0x40006944 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_MC_00 +CYREG_B0_UDB03_MC_00 EQU 0x40006946 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_MC_00 +CYREG_B0_UDB04_MC_00 EQU 0x40006948 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_MC_00 +CYREG_B0_UDB05_MC_00 EQU 0x4000694a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_MC_00 +CYREG_B0_UDB06_MC_00 EQU 0x4000694c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_MC_00 +CYREG_B0_UDB07_MC_00 EQU 0x4000694e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_MC_00 +CYREG_B0_UDB08_MC_00 EQU 0x40006950 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_MC_00 +CYREG_B0_UDB09_MC_00 EQU 0x40006952 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_MC_00 +CYREG_B0_UDB10_MC_00 EQU 0x40006954 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_MC_00 +CYREG_B0_UDB11_MC_00 EQU 0x40006956 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_MC_00 +CYREG_B0_UDB12_MC_00 EQU 0x40006958 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_MC_00 +CYREG_B0_UDB13_MC_00 EQU 0x4000695a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_MC_00 +CYREG_B0_UDB14_MC_00 EQU 0x4000695c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_MC_00 +CYREG_B0_UDB15_MC_00 EQU 0x4000695e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_BASE +CYDEV_UWRK_UWRK16_CAT_B1_BASE EQU 0x40006a00 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_SIZE +CYDEV_UWRK_UWRK16_CAT_B1_SIZE EQU 0x00000160 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_A0_A1 +CYREG_B1_UDB04_A0_A1 EQU 0x40006a08 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_A0_A1 +CYREG_B1_UDB05_A0_A1 EQU 0x40006a0a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_A0_A1 +CYREG_B1_UDB06_A0_A1 EQU 0x40006a0c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_A0_A1 +CYREG_B1_UDB07_A0_A1 EQU 0x40006a0e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_A0_A1 +CYREG_B1_UDB08_A0_A1 EQU 0x40006a10 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_A0_A1 +CYREG_B1_UDB09_A0_A1 EQU 0x40006a12 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_A0_A1 +CYREG_B1_UDB10_A0_A1 EQU 0x40006a14 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_A0_A1 +CYREG_B1_UDB11_A0_A1 EQU 0x40006a16 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_D0_D1 +CYREG_B1_UDB04_D0_D1 EQU 0x40006a48 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_D0_D1 +CYREG_B1_UDB05_D0_D1 EQU 0x40006a4a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_D0_D1 +CYREG_B1_UDB06_D0_D1 EQU 0x40006a4c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_D0_D1 +CYREG_B1_UDB07_D0_D1 EQU 0x40006a4e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_D0_D1 +CYREG_B1_UDB08_D0_D1 EQU 0x40006a50 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_D0_D1 +CYREG_B1_UDB09_D0_D1 EQU 0x40006a52 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_D0_D1 +CYREG_B1_UDB10_D0_D1 EQU 0x40006a54 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_D0_D1 +CYREG_B1_UDB11_D0_D1 EQU 0x40006a56 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_F0_F1 +CYREG_B1_UDB04_F0_F1 EQU 0x40006a88 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_F0_F1 +CYREG_B1_UDB05_F0_F1 EQU 0x40006a8a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_F0_F1 +CYREG_B1_UDB06_F0_F1 EQU 0x40006a8c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_F0_F1 +CYREG_B1_UDB07_F0_F1 EQU 0x40006a8e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_F0_F1 +CYREG_B1_UDB08_F0_F1 EQU 0x40006a90 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_F0_F1 +CYREG_B1_UDB09_F0_F1 EQU 0x40006a92 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_F0_F1 +CYREG_B1_UDB10_F0_F1 EQU 0x40006a94 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_F0_F1 +CYREG_B1_UDB11_F0_F1 EQU 0x40006a96 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_ST_CTL +CYREG_B1_UDB04_ST_CTL EQU 0x40006ac8 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_ST_CTL +CYREG_B1_UDB05_ST_CTL EQU 0x40006aca + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_ST_CTL +CYREG_B1_UDB06_ST_CTL EQU 0x40006acc + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_ST_CTL +CYREG_B1_UDB07_ST_CTL EQU 0x40006ace + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_ST_CTL +CYREG_B1_UDB08_ST_CTL EQU 0x40006ad0 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_ST_CTL +CYREG_B1_UDB09_ST_CTL EQU 0x40006ad2 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_ST_CTL +CYREG_B1_UDB10_ST_CTL EQU 0x40006ad4 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_ST_CTL +CYREG_B1_UDB11_ST_CTL EQU 0x40006ad6 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_MSK_ACTL +CYREG_B1_UDB04_MSK_ACTL EQU 0x40006b08 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_MSK_ACTL +CYREG_B1_UDB05_MSK_ACTL EQU 0x40006b0a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_MSK_ACTL +CYREG_B1_UDB06_MSK_ACTL EQU 0x40006b0c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_MSK_ACTL +CYREG_B1_UDB07_MSK_ACTL EQU 0x40006b0e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_MSK_ACTL +CYREG_B1_UDB08_MSK_ACTL EQU 0x40006b10 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_MSK_ACTL +CYREG_B1_UDB09_MSK_ACTL EQU 0x40006b12 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_MSK_ACTL +CYREG_B1_UDB10_MSK_ACTL EQU 0x40006b14 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_MSK_ACTL +CYREG_B1_UDB11_MSK_ACTL EQU 0x40006b16 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_MC_00 +CYREG_B1_UDB04_MC_00 EQU 0x40006b48 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_MC_00 +CYREG_B1_UDB05_MC_00 EQU 0x40006b4a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_MC_00 +CYREG_B1_UDB06_MC_00 EQU 0x40006b4c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_MC_00 +CYREG_B1_UDB07_MC_00 EQU 0x40006b4e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_MC_00 +CYREG_B1_UDB08_MC_00 EQU 0x40006b50 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_MC_00 +CYREG_B1_UDB09_MC_00 EQU 0x40006b52 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_MC_00 +CYREG_B1_UDB10_MC_00 EQU 0x40006b54 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_MC_00 +CYREG_B1_UDB11_MC_00 EQU 0x40006b56 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_BASE +CYDEV_UWRK_UWRK16_DEF_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_SIZE +CYDEV_UWRK_UWRK16_DEF_SIZE EQU 0x0000075e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_BASE +CYDEV_UWRK_UWRK16_DEF_B0_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_SIZE +CYDEV_UWRK_UWRK16_DEF_B0_SIZE EQU 0x0000015e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_A0 +CYREG_B0_UDB00_01_A0 EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_A0 +CYREG_B0_UDB01_02_A0 EQU 0x40006802 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_A0 +CYREG_B0_UDB02_03_A0 EQU 0x40006804 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_A0 +CYREG_B0_UDB03_04_A0 EQU 0x40006806 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_A0 +CYREG_B0_UDB04_05_A0 EQU 0x40006808 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_A0 +CYREG_B0_UDB05_06_A0 EQU 0x4000680a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_A0 +CYREG_B0_UDB06_07_A0 EQU 0x4000680c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_A0 +CYREG_B0_UDB07_08_A0 EQU 0x4000680e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_A0 +CYREG_B0_UDB08_09_A0 EQU 0x40006810 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_A0 +CYREG_B0_UDB09_10_A0 EQU 0x40006812 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_A0 +CYREG_B0_UDB10_11_A0 EQU 0x40006814 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_A0 +CYREG_B0_UDB11_12_A0 EQU 0x40006816 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_A0 +CYREG_B0_UDB12_13_A0 EQU 0x40006818 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_A0 +CYREG_B0_UDB13_14_A0 EQU 0x4000681a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_A0 +CYREG_B0_UDB14_15_A0 EQU 0x4000681c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_A1 +CYREG_B0_UDB00_01_A1 EQU 0x40006820 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_A1 +CYREG_B0_UDB01_02_A1 EQU 0x40006822 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_A1 +CYREG_B0_UDB02_03_A1 EQU 0x40006824 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_A1 +CYREG_B0_UDB03_04_A1 EQU 0x40006826 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_A1 +CYREG_B0_UDB04_05_A1 EQU 0x40006828 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_A1 +CYREG_B0_UDB05_06_A1 EQU 0x4000682a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_A1 +CYREG_B0_UDB06_07_A1 EQU 0x4000682c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_A1 +CYREG_B0_UDB07_08_A1 EQU 0x4000682e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_A1 +CYREG_B0_UDB08_09_A1 EQU 0x40006830 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_A1 +CYREG_B0_UDB09_10_A1 EQU 0x40006832 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_A1 +CYREG_B0_UDB10_11_A1 EQU 0x40006834 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_A1 +CYREG_B0_UDB11_12_A1 EQU 0x40006836 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_A1 +CYREG_B0_UDB12_13_A1 EQU 0x40006838 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_A1 +CYREG_B0_UDB13_14_A1 EQU 0x4000683a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_A1 +CYREG_B0_UDB14_15_A1 EQU 0x4000683c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_D0 +CYREG_B0_UDB00_01_D0 EQU 0x40006840 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_D0 +CYREG_B0_UDB01_02_D0 EQU 0x40006842 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_D0 +CYREG_B0_UDB02_03_D0 EQU 0x40006844 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_D0 +CYREG_B0_UDB03_04_D0 EQU 0x40006846 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_D0 +CYREG_B0_UDB04_05_D0 EQU 0x40006848 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_D0 +CYREG_B0_UDB05_06_D0 EQU 0x4000684a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_D0 +CYREG_B0_UDB06_07_D0 EQU 0x4000684c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_D0 +CYREG_B0_UDB07_08_D0 EQU 0x4000684e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_D0 +CYREG_B0_UDB08_09_D0 EQU 0x40006850 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_D0 +CYREG_B0_UDB09_10_D0 EQU 0x40006852 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_D0 +CYREG_B0_UDB10_11_D0 EQU 0x40006854 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_D0 +CYREG_B0_UDB11_12_D0 EQU 0x40006856 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_D0 +CYREG_B0_UDB12_13_D0 EQU 0x40006858 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_D0 +CYREG_B0_UDB13_14_D0 EQU 0x4000685a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_D0 +CYREG_B0_UDB14_15_D0 EQU 0x4000685c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_D1 +CYREG_B0_UDB00_01_D1 EQU 0x40006860 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_D1 +CYREG_B0_UDB01_02_D1 EQU 0x40006862 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_D1 +CYREG_B0_UDB02_03_D1 EQU 0x40006864 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_D1 +CYREG_B0_UDB03_04_D1 EQU 0x40006866 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_D1 +CYREG_B0_UDB04_05_D1 EQU 0x40006868 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_D1 +CYREG_B0_UDB05_06_D1 EQU 0x4000686a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_D1 +CYREG_B0_UDB06_07_D1 EQU 0x4000686c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_D1 +CYREG_B0_UDB07_08_D1 EQU 0x4000686e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_D1 +CYREG_B0_UDB08_09_D1 EQU 0x40006870 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_D1 +CYREG_B0_UDB09_10_D1 EQU 0x40006872 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_D1 +CYREG_B0_UDB10_11_D1 EQU 0x40006874 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_D1 +CYREG_B0_UDB11_12_D1 EQU 0x40006876 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_D1 +CYREG_B0_UDB12_13_D1 EQU 0x40006878 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_D1 +CYREG_B0_UDB13_14_D1 EQU 0x4000687a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_D1 +CYREG_B0_UDB14_15_D1 EQU 0x4000687c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_F0 +CYREG_B0_UDB00_01_F0 EQU 0x40006880 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_F0 +CYREG_B0_UDB01_02_F0 EQU 0x40006882 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_F0 +CYREG_B0_UDB02_03_F0 EQU 0x40006884 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_F0 +CYREG_B0_UDB03_04_F0 EQU 0x40006886 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_F0 +CYREG_B0_UDB04_05_F0 EQU 0x40006888 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_F0 +CYREG_B0_UDB05_06_F0 EQU 0x4000688a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_F0 +CYREG_B0_UDB06_07_F0 EQU 0x4000688c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_F0 +CYREG_B0_UDB07_08_F0 EQU 0x4000688e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_F0 +CYREG_B0_UDB08_09_F0 EQU 0x40006890 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_F0 +CYREG_B0_UDB09_10_F0 EQU 0x40006892 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_F0 +CYREG_B0_UDB10_11_F0 EQU 0x40006894 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_F0 +CYREG_B0_UDB11_12_F0 EQU 0x40006896 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_F0 +CYREG_B0_UDB12_13_F0 EQU 0x40006898 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_F0 +CYREG_B0_UDB13_14_F0 EQU 0x4000689a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_F0 +CYREG_B0_UDB14_15_F0 EQU 0x4000689c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_F1 +CYREG_B0_UDB00_01_F1 EQU 0x400068a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_F1 +CYREG_B0_UDB01_02_F1 EQU 0x400068a2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_F1 +CYREG_B0_UDB02_03_F1 EQU 0x400068a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_F1 +CYREG_B0_UDB03_04_F1 EQU 0x400068a6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_F1 +CYREG_B0_UDB04_05_F1 EQU 0x400068a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_F1 +CYREG_B0_UDB05_06_F1 EQU 0x400068aa + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_F1 +CYREG_B0_UDB06_07_F1 EQU 0x400068ac + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_F1 +CYREG_B0_UDB07_08_F1 EQU 0x400068ae + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_F1 +CYREG_B0_UDB08_09_F1 EQU 0x400068b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_F1 +CYREG_B0_UDB09_10_F1 EQU 0x400068b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_F1 +CYREG_B0_UDB10_11_F1 EQU 0x400068b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_F1 +CYREG_B0_UDB11_12_F1 EQU 0x400068b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_F1 +CYREG_B0_UDB12_13_F1 EQU 0x400068b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_F1 +CYREG_B0_UDB13_14_F1 EQU 0x400068ba + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_F1 +CYREG_B0_UDB14_15_F1 EQU 0x400068bc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_ST +CYREG_B0_UDB00_01_ST EQU 0x400068c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_ST +CYREG_B0_UDB01_02_ST EQU 0x400068c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_ST +CYREG_B0_UDB02_03_ST EQU 0x400068c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_ST +CYREG_B0_UDB03_04_ST EQU 0x400068c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_ST +CYREG_B0_UDB04_05_ST EQU 0x400068c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_ST +CYREG_B0_UDB05_06_ST EQU 0x400068ca + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_ST +CYREG_B0_UDB06_07_ST EQU 0x400068cc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_ST +CYREG_B0_UDB07_08_ST EQU 0x400068ce + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_ST +CYREG_B0_UDB08_09_ST EQU 0x400068d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_ST +CYREG_B0_UDB09_10_ST EQU 0x400068d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_ST +CYREG_B0_UDB10_11_ST EQU 0x400068d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_ST +CYREG_B0_UDB11_12_ST EQU 0x400068d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_ST +CYREG_B0_UDB12_13_ST EQU 0x400068d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_ST +CYREG_B0_UDB13_14_ST EQU 0x400068da + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_ST +CYREG_B0_UDB14_15_ST EQU 0x400068dc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_CTL +CYREG_B0_UDB00_01_CTL EQU 0x400068e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_CTL +CYREG_B0_UDB01_02_CTL EQU 0x400068e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_CTL +CYREG_B0_UDB02_03_CTL EQU 0x400068e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_CTL +CYREG_B0_UDB03_04_CTL EQU 0x400068e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_CTL +CYREG_B0_UDB04_05_CTL EQU 0x400068e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_CTL +CYREG_B0_UDB05_06_CTL EQU 0x400068ea + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_CTL +CYREG_B0_UDB06_07_CTL EQU 0x400068ec + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_CTL +CYREG_B0_UDB07_08_CTL EQU 0x400068ee + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_CTL +CYREG_B0_UDB08_09_CTL EQU 0x400068f0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_CTL +CYREG_B0_UDB09_10_CTL EQU 0x400068f2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_CTL +CYREG_B0_UDB10_11_CTL EQU 0x400068f4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_CTL +CYREG_B0_UDB11_12_CTL EQU 0x400068f6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_CTL +CYREG_B0_UDB12_13_CTL EQU 0x400068f8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_CTL +CYREG_B0_UDB13_14_CTL EQU 0x400068fa + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_CTL +CYREG_B0_UDB14_15_CTL EQU 0x400068fc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_MSK +CYREG_B0_UDB00_01_MSK EQU 0x40006900 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_MSK +CYREG_B0_UDB01_02_MSK EQU 0x40006902 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_MSK +CYREG_B0_UDB02_03_MSK EQU 0x40006904 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_MSK +CYREG_B0_UDB03_04_MSK EQU 0x40006906 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_MSK +CYREG_B0_UDB04_05_MSK EQU 0x40006908 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_MSK +CYREG_B0_UDB05_06_MSK EQU 0x4000690a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_MSK +CYREG_B0_UDB06_07_MSK EQU 0x4000690c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_MSK +CYREG_B0_UDB07_08_MSK EQU 0x4000690e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_MSK +CYREG_B0_UDB08_09_MSK EQU 0x40006910 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_MSK +CYREG_B0_UDB09_10_MSK EQU 0x40006912 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_MSK +CYREG_B0_UDB10_11_MSK EQU 0x40006914 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_MSK +CYREG_B0_UDB11_12_MSK EQU 0x40006916 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_MSK +CYREG_B0_UDB12_13_MSK EQU 0x40006918 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_MSK +CYREG_B0_UDB13_14_MSK EQU 0x4000691a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_MSK +CYREG_B0_UDB14_15_MSK EQU 0x4000691c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_ACTL +CYREG_B0_UDB00_01_ACTL EQU 0x40006920 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_ACTL +CYREG_B0_UDB01_02_ACTL EQU 0x40006922 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_ACTL +CYREG_B0_UDB02_03_ACTL EQU 0x40006924 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_ACTL +CYREG_B0_UDB03_04_ACTL EQU 0x40006926 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_ACTL +CYREG_B0_UDB04_05_ACTL EQU 0x40006928 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_ACTL +CYREG_B0_UDB05_06_ACTL EQU 0x4000692a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_ACTL +CYREG_B0_UDB06_07_ACTL EQU 0x4000692c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_ACTL +CYREG_B0_UDB07_08_ACTL EQU 0x4000692e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_ACTL +CYREG_B0_UDB08_09_ACTL EQU 0x40006930 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_ACTL +CYREG_B0_UDB09_10_ACTL EQU 0x40006932 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_ACTL +CYREG_B0_UDB10_11_ACTL EQU 0x40006934 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_ACTL +CYREG_B0_UDB11_12_ACTL EQU 0x40006936 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_ACTL +CYREG_B0_UDB12_13_ACTL EQU 0x40006938 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_ACTL +CYREG_B0_UDB13_14_ACTL EQU 0x4000693a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_ACTL +CYREG_B0_UDB14_15_ACTL EQU 0x4000693c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_MC +CYREG_B0_UDB00_01_MC EQU 0x40006940 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_MC +CYREG_B0_UDB01_02_MC EQU 0x40006942 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_MC +CYREG_B0_UDB02_03_MC EQU 0x40006944 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_MC +CYREG_B0_UDB03_04_MC EQU 0x40006946 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_MC +CYREG_B0_UDB04_05_MC EQU 0x40006948 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_MC +CYREG_B0_UDB05_06_MC EQU 0x4000694a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_MC +CYREG_B0_UDB06_07_MC EQU 0x4000694c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_MC +CYREG_B0_UDB07_08_MC EQU 0x4000694e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_MC +CYREG_B0_UDB08_09_MC EQU 0x40006950 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_MC +CYREG_B0_UDB09_10_MC EQU 0x40006952 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_MC +CYREG_B0_UDB10_11_MC EQU 0x40006954 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_MC +CYREG_B0_UDB11_12_MC EQU 0x40006956 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_MC +CYREG_B0_UDB12_13_MC EQU 0x40006958 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_MC +CYREG_B0_UDB13_14_MC EQU 0x4000695a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_MC +CYREG_B0_UDB14_15_MC EQU 0x4000695c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_BASE +CYDEV_UWRK_UWRK16_DEF_B1_BASE EQU 0x40006a00 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_SIZE +CYDEV_UWRK_UWRK16_DEF_B1_SIZE EQU 0x0000015e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_A0 +CYREG_B1_UDB04_05_A0 EQU 0x40006a08 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_A0 +CYREG_B1_UDB05_06_A0 EQU 0x40006a0a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_A0 +CYREG_B1_UDB06_07_A0 EQU 0x40006a0c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_A0 +CYREG_B1_UDB07_08_A0 EQU 0x40006a0e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_A0 +CYREG_B1_UDB08_09_A0 EQU 0x40006a10 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_A0 +CYREG_B1_UDB09_10_A0 EQU 0x40006a12 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_A0 +CYREG_B1_UDB10_11_A0 EQU 0x40006a14 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_A0 +CYREG_B1_UDB11_12_A0 EQU 0x40006a16 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_A1 +CYREG_B1_UDB04_05_A1 EQU 0x40006a28 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_A1 +CYREG_B1_UDB05_06_A1 EQU 0x40006a2a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_A1 +CYREG_B1_UDB06_07_A1 EQU 0x40006a2c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_A1 +CYREG_B1_UDB07_08_A1 EQU 0x40006a2e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_A1 +CYREG_B1_UDB08_09_A1 EQU 0x40006a30 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_A1 +CYREG_B1_UDB09_10_A1 EQU 0x40006a32 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_A1 +CYREG_B1_UDB10_11_A1 EQU 0x40006a34 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_A1 +CYREG_B1_UDB11_12_A1 EQU 0x40006a36 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_D0 +CYREG_B1_UDB04_05_D0 EQU 0x40006a48 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_D0 +CYREG_B1_UDB05_06_D0 EQU 0x40006a4a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_D0 +CYREG_B1_UDB06_07_D0 EQU 0x40006a4c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_D0 +CYREG_B1_UDB07_08_D0 EQU 0x40006a4e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_D0 +CYREG_B1_UDB08_09_D0 EQU 0x40006a50 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_D0 +CYREG_B1_UDB09_10_D0 EQU 0x40006a52 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_D0 +CYREG_B1_UDB10_11_D0 EQU 0x40006a54 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_D0 +CYREG_B1_UDB11_12_D0 EQU 0x40006a56 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_D1 +CYREG_B1_UDB04_05_D1 EQU 0x40006a68 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_D1 +CYREG_B1_UDB05_06_D1 EQU 0x40006a6a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_D1 +CYREG_B1_UDB06_07_D1 EQU 0x40006a6c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_D1 +CYREG_B1_UDB07_08_D1 EQU 0x40006a6e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_D1 +CYREG_B1_UDB08_09_D1 EQU 0x40006a70 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_D1 +CYREG_B1_UDB09_10_D1 EQU 0x40006a72 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_D1 +CYREG_B1_UDB10_11_D1 EQU 0x40006a74 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_D1 +CYREG_B1_UDB11_12_D1 EQU 0x40006a76 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_F0 +CYREG_B1_UDB04_05_F0 EQU 0x40006a88 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_F0 +CYREG_B1_UDB05_06_F0 EQU 0x40006a8a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_F0 +CYREG_B1_UDB06_07_F0 EQU 0x40006a8c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_F0 +CYREG_B1_UDB07_08_F0 EQU 0x40006a8e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_F0 +CYREG_B1_UDB08_09_F0 EQU 0x40006a90 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_F0 +CYREG_B1_UDB09_10_F0 EQU 0x40006a92 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_F0 +CYREG_B1_UDB10_11_F0 EQU 0x40006a94 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_F0 +CYREG_B1_UDB11_12_F0 EQU 0x40006a96 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_F1 +CYREG_B1_UDB04_05_F1 EQU 0x40006aa8 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_F1 +CYREG_B1_UDB05_06_F1 EQU 0x40006aaa + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_F1 +CYREG_B1_UDB06_07_F1 EQU 0x40006aac + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_F1 +CYREG_B1_UDB07_08_F1 EQU 0x40006aae + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_F1 +CYREG_B1_UDB08_09_F1 EQU 0x40006ab0 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_F1 +CYREG_B1_UDB09_10_F1 EQU 0x40006ab2 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_F1 +CYREG_B1_UDB10_11_F1 EQU 0x40006ab4 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_F1 +CYREG_B1_UDB11_12_F1 EQU 0x40006ab6 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_ST +CYREG_B1_UDB04_05_ST EQU 0x40006ac8 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_ST +CYREG_B1_UDB05_06_ST EQU 0x40006aca + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_ST +CYREG_B1_UDB06_07_ST EQU 0x40006acc + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_ST +CYREG_B1_UDB07_08_ST EQU 0x40006ace + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_ST +CYREG_B1_UDB08_09_ST EQU 0x40006ad0 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_ST +CYREG_B1_UDB09_10_ST EQU 0x40006ad2 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_ST +CYREG_B1_UDB10_11_ST EQU 0x40006ad4 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_ST +CYREG_B1_UDB11_12_ST EQU 0x40006ad6 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_CTL +CYREG_B1_UDB04_05_CTL EQU 0x40006ae8 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_CTL +CYREG_B1_UDB05_06_CTL EQU 0x40006aea + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_CTL +CYREG_B1_UDB06_07_CTL EQU 0x40006aec + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_CTL +CYREG_B1_UDB07_08_CTL EQU 0x40006aee + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_CTL +CYREG_B1_UDB08_09_CTL EQU 0x40006af0 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_CTL +CYREG_B1_UDB09_10_CTL EQU 0x40006af2 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_CTL +CYREG_B1_UDB10_11_CTL EQU 0x40006af4 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_CTL +CYREG_B1_UDB11_12_CTL EQU 0x40006af6 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_MSK +CYREG_B1_UDB04_05_MSK EQU 0x40006b08 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_MSK +CYREG_B1_UDB05_06_MSK EQU 0x40006b0a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_MSK +CYREG_B1_UDB06_07_MSK EQU 0x40006b0c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_MSK +CYREG_B1_UDB07_08_MSK EQU 0x40006b0e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_MSK +CYREG_B1_UDB08_09_MSK EQU 0x40006b10 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_MSK +CYREG_B1_UDB09_10_MSK EQU 0x40006b12 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_MSK +CYREG_B1_UDB10_11_MSK EQU 0x40006b14 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_MSK +CYREG_B1_UDB11_12_MSK EQU 0x40006b16 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_ACTL +CYREG_B1_UDB04_05_ACTL EQU 0x40006b28 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_ACTL +CYREG_B1_UDB05_06_ACTL EQU 0x40006b2a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_ACTL +CYREG_B1_UDB06_07_ACTL EQU 0x40006b2c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_ACTL +CYREG_B1_UDB07_08_ACTL EQU 0x40006b2e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_ACTL +CYREG_B1_UDB08_09_ACTL EQU 0x40006b30 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_ACTL +CYREG_B1_UDB09_10_ACTL EQU 0x40006b32 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_ACTL +CYREG_B1_UDB10_11_ACTL EQU 0x40006b34 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_ACTL +CYREG_B1_UDB11_12_ACTL EQU 0x40006b36 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_MC +CYREG_B1_UDB04_05_MC EQU 0x40006b48 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_MC +CYREG_B1_UDB05_06_MC EQU 0x40006b4a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_MC +CYREG_B1_UDB06_07_MC EQU 0x40006b4c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_MC +CYREG_B1_UDB07_08_MC EQU 0x40006b4e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_MC +CYREG_B1_UDB08_09_MC EQU 0x40006b50 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_MC +CYREG_B1_UDB09_10_MC EQU 0x40006b52 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_MC +CYREG_B1_UDB10_11_MC EQU 0x40006b54 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_MC +CYREG_B1_UDB11_12_MC EQU 0x40006b56 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_BASE +CYDEV_PHUB_BASE EQU 0x40007000 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_SIZE +CYDEV_PHUB_SIZE EQU 0x00000c00 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFG +CYREG_PHUB_CFG EQU 0x40007000 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_ERR +CYREG_PHUB_ERR EQU 0x40007004 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_ERR_ADR +CYREG_PHUB_ERR_ADR EQU 0x40007008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_BASE +CYDEV_PHUB_CH0_BASE EQU 0x40007010 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_SIZE +CYDEV_PHUB_CH0_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH0_BASIC_CFG +CYREG_PHUB_CH0_BASIC_CFG EQU 0x40007010 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH0_ACTION +CYREG_PHUB_CH0_ACTION EQU 0x40007014 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH0_BASIC_STATUS +CYREG_PHUB_CH0_BASIC_STATUS EQU 0x40007018 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_BASE +CYDEV_PHUB_CH1_BASE EQU 0x40007020 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_SIZE +CYDEV_PHUB_CH1_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH1_BASIC_CFG +CYREG_PHUB_CH1_BASIC_CFG EQU 0x40007020 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH1_ACTION +CYREG_PHUB_CH1_ACTION EQU 0x40007024 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH1_BASIC_STATUS +CYREG_PHUB_CH1_BASIC_STATUS EQU 0x40007028 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_BASE +CYDEV_PHUB_CH2_BASE EQU 0x40007030 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_SIZE +CYDEV_PHUB_CH2_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH2_BASIC_CFG +CYREG_PHUB_CH2_BASIC_CFG EQU 0x40007030 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH2_ACTION +CYREG_PHUB_CH2_ACTION EQU 0x40007034 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH2_BASIC_STATUS +CYREG_PHUB_CH2_BASIC_STATUS EQU 0x40007038 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_BASE +CYDEV_PHUB_CH3_BASE EQU 0x40007040 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_SIZE +CYDEV_PHUB_CH3_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH3_BASIC_CFG +CYREG_PHUB_CH3_BASIC_CFG EQU 0x40007040 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH3_ACTION +CYREG_PHUB_CH3_ACTION EQU 0x40007044 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH3_BASIC_STATUS +CYREG_PHUB_CH3_BASIC_STATUS EQU 0x40007048 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_BASE +CYDEV_PHUB_CH4_BASE EQU 0x40007050 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_SIZE +CYDEV_PHUB_CH4_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH4_BASIC_CFG +CYREG_PHUB_CH4_BASIC_CFG EQU 0x40007050 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH4_ACTION +CYREG_PHUB_CH4_ACTION EQU 0x40007054 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH4_BASIC_STATUS +CYREG_PHUB_CH4_BASIC_STATUS EQU 0x40007058 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_BASE +CYDEV_PHUB_CH5_BASE EQU 0x40007060 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_SIZE +CYDEV_PHUB_CH5_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH5_BASIC_CFG +CYREG_PHUB_CH5_BASIC_CFG EQU 0x40007060 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH5_ACTION +CYREG_PHUB_CH5_ACTION EQU 0x40007064 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH5_BASIC_STATUS +CYREG_PHUB_CH5_BASIC_STATUS EQU 0x40007068 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_BASE +CYDEV_PHUB_CH6_BASE EQU 0x40007070 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_SIZE +CYDEV_PHUB_CH6_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH6_BASIC_CFG +CYREG_PHUB_CH6_BASIC_CFG EQU 0x40007070 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH6_ACTION +CYREG_PHUB_CH6_ACTION EQU 0x40007074 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH6_BASIC_STATUS +CYREG_PHUB_CH6_BASIC_STATUS EQU 0x40007078 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_BASE +CYDEV_PHUB_CH7_BASE EQU 0x40007080 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_SIZE +CYDEV_PHUB_CH7_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH7_BASIC_CFG +CYREG_PHUB_CH7_BASIC_CFG EQU 0x40007080 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH7_ACTION +CYREG_PHUB_CH7_ACTION EQU 0x40007084 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH7_BASIC_STATUS +CYREG_PHUB_CH7_BASIC_STATUS EQU 0x40007088 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_BASE +CYDEV_PHUB_CH8_BASE EQU 0x40007090 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_SIZE +CYDEV_PHUB_CH8_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH8_BASIC_CFG +CYREG_PHUB_CH8_BASIC_CFG EQU 0x40007090 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH8_ACTION +CYREG_PHUB_CH8_ACTION EQU 0x40007094 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH8_BASIC_STATUS +CYREG_PHUB_CH8_BASIC_STATUS EQU 0x40007098 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_BASE +CYDEV_PHUB_CH9_BASE EQU 0x400070a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_SIZE +CYDEV_PHUB_CH9_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH9_BASIC_CFG +CYREG_PHUB_CH9_BASIC_CFG EQU 0x400070a0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH9_ACTION +CYREG_PHUB_CH9_ACTION EQU 0x400070a4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH9_BASIC_STATUS +CYREG_PHUB_CH9_BASIC_STATUS EQU 0x400070a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_BASE +CYDEV_PHUB_CH10_BASE EQU 0x400070b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_SIZE +CYDEV_PHUB_CH10_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH10_BASIC_CFG +CYREG_PHUB_CH10_BASIC_CFG EQU 0x400070b0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH10_ACTION +CYREG_PHUB_CH10_ACTION EQU 0x400070b4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH10_BASIC_STATUS +CYREG_PHUB_CH10_BASIC_STATUS EQU 0x400070b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_BASE +CYDEV_PHUB_CH11_BASE EQU 0x400070c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_SIZE +CYDEV_PHUB_CH11_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH11_BASIC_CFG +CYREG_PHUB_CH11_BASIC_CFG EQU 0x400070c0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH11_ACTION +CYREG_PHUB_CH11_ACTION EQU 0x400070c4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH11_BASIC_STATUS +CYREG_PHUB_CH11_BASIC_STATUS EQU 0x400070c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_BASE +CYDEV_PHUB_CH12_BASE EQU 0x400070d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_SIZE +CYDEV_PHUB_CH12_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH12_BASIC_CFG +CYREG_PHUB_CH12_BASIC_CFG EQU 0x400070d0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH12_ACTION +CYREG_PHUB_CH12_ACTION EQU 0x400070d4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH12_BASIC_STATUS +CYREG_PHUB_CH12_BASIC_STATUS EQU 0x400070d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_BASE +CYDEV_PHUB_CH13_BASE EQU 0x400070e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_SIZE +CYDEV_PHUB_CH13_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH13_BASIC_CFG +CYREG_PHUB_CH13_BASIC_CFG EQU 0x400070e0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH13_ACTION +CYREG_PHUB_CH13_ACTION EQU 0x400070e4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH13_BASIC_STATUS +CYREG_PHUB_CH13_BASIC_STATUS EQU 0x400070e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_BASE +CYDEV_PHUB_CH14_BASE EQU 0x400070f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_SIZE +CYDEV_PHUB_CH14_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH14_BASIC_CFG +CYREG_PHUB_CH14_BASIC_CFG EQU 0x400070f0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH14_ACTION +CYREG_PHUB_CH14_ACTION EQU 0x400070f4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH14_BASIC_STATUS +CYREG_PHUB_CH14_BASIC_STATUS EQU 0x400070f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_BASE +CYDEV_PHUB_CH15_BASE EQU 0x40007100 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_SIZE +CYDEV_PHUB_CH15_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH15_BASIC_CFG +CYREG_PHUB_CH15_BASIC_CFG EQU 0x40007100 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH15_ACTION +CYREG_PHUB_CH15_ACTION EQU 0x40007104 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH15_BASIC_STATUS +CYREG_PHUB_CH15_BASIC_STATUS EQU 0x40007108 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_BASE +CYDEV_PHUB_CH16_BASE EQU 0x40007110 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_SIZE +CYDEV_PHUB_CH16_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH16_BASIC_CFG +CYREG_PHUB_CH16_BASIC_CFG EQU 0x40007110 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH16_ACTION +CYREG_PHUB_CH16_ACTION EQU 0x40007114 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH16_BASIC_STATUS +CYREG_PHUB_CH16_BASIC_STATUS EQU 0x40007118 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_BASE +CYDEV_PHUB_CH17_BASE EQU 0x40007120 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_SIZE +CYDEV_PHUB_CH17_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH17_BASIC_CFG +CYREG_PHUB_CH17_BASIC_CFG EQU 0x40007120 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH17_ACTION +CYREG_PHUB_CH17_ACTION EQU 0x40007124 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH17_BASIC_STATUS +CYREG_PHUB_CH17_BASIC_STATUS EQU 0x40007128 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_BASE +CYDEV_PHUB_CH18_BASE EQU 0x40007130 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_SIZE +CYDEV_PHUB_CH18_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH18_BASIC_CFG +CYREG_PHUB_CH18_BASIC_CFG EQU 0x40007130 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH18_ACTION +CYREG_PHUB_CH18_ACTION EQU 0x40007134 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH18_BASIC_STATUS +CYREG_PHUB_CH18_BASIC_STATUS EQU 0x40007138 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_BASE +CYDEV_PHUB_CH19_BASE EQU 0x40007140 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_SIZE +CYDEV_PHUB_CH19_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH19_BASIC_CFG +CYREG_PHUB_CH19_BASIC_CFG EQU 0x40007140 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH19_ACTION +CYREG_PHUB_CH19_ACTION EQU 0x40007144 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH19_BASIC_STATUS +CYREG_PHUB_CH19_BASIC_STATUS EQU 0x40007148 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_BASE +CYDEV_PHUB_CH20_BASE EQU 0x40007150 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_SIZE +CYDEV_PHUB_CH20_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH20_BASIC_CFG +CYREG_PHUB_CH20_BASIC_CFG EQU 0x40007150 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH20_ACTION +CYREG_PHUB_CH20_ACTION EQU 0x40007154 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH20_BASIC_STATUS +CYREG_PHUB_CH20_BASIC_STATUS EQU 0x40007158 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_BASE +CYDEV_PHUB_CH21_BASE EQU 0x40007160 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_SIZE +CYDEV_PHUB_CH21_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH21_BASIC_CFG +CYREG_PHUB_CH21_BASIC_CFG EQU 0x40007160 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH21_ACTION +CYREG_PHUB_CH21_ACTION EQU 0x40007164 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH21_BASIC_STATUS +CYREG_PHUB_CH21_BASIC_STATUS EQU 0x40007168 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_BASE +CYDEV_PHUB_CH22_BASE EQU 0x40007170 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_SIZE +CYDEV_PHUB_CH22_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH22_BASIC_CFG +CYREG_PHUB_CH22_BASIC_CFG EQU 0x40007170 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH22_ACTION +CYREG_PHUB_CH22_ACTION EQU 0x40007174 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH22_BASIC_STATUS +CYREG_PHUB_CH22_BASIC_STATUS EQU 0x40007178 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_BASE +CYDEV_PHUB_CH23_BASE EQU 0x40007180 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_SIZE +CYDEV_PHUB_CH23_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH23_BASIC_CFG +CYREG_PHUB_CH23_BASIC_CFG EQU 0x40007180 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH23_ACTION +CYREG_PHUB_CH23_ACTION EQU 0x40007184 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH23_BASIC_STATUS +CYREG_PHUB_CH23_BASIC_STATUS EQU 0x40007188 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_BASE +CYDEV_PHUB_CFGMEM0_BASE EQU 0x40007600 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_SIZE +CYDEV_PHUB_CFGMEM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM0_CFG0 +CYREG_PHUB_CFGMEM0_CFG0 EQU 0x40007600 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM0_CFG1 +CYREG_PHUB_CFGMEM0_CFG1 EQU 0x40007604 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_BASE +CYDEV_PHUB_CFGMEM1_BASE EQU 0x40007608 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_SIZE +CYDEV_PHUB_CFGMEM1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM1_CFG0 +CYREG_PHUB_CFGMEM1_CFG0 EQU 0x40007608 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM1_CFG1 +CYREG_PHUB_CFGMEM1_CFG1 EQU 0x4000760c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_BASE +CYDEV_PHUB_CFGMEM2_BASE EQU 0x40007610 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_SIZE +CYDEV_PHUB_CFGMEM2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM2_CFG0 +CYREG_PHUB_CFGMEM2_CFG0 EQU 0x40007610 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM2_CFG1 +CYREG_PHUB_CFGMEM2_CFG1 EQU 0x40007614 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_BASE +CYDEV_PHUB_CFGMEM3_BASE EQU 0x40007618 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_SIZE +CYDEV_PHUB_CFGMEM3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM3_CFG0 +CYREG_PHUB_CFGMEM3_CFG0 EQU 0x40007618 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM3_CFG1 +CYREG_PHUB_CFGMEM3_CFG1 EQU 0x4000761c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_BASE +CYDEV_PHUB_CFGMEM4_BASE EQU 0x40007620 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_SIZE +CYDEV_PHUB_CFGMEM4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM4_CFG0 +CYREG_PHUB_CFGMEM4_CFG0 EQU 0x40007620 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM4_CFG1 +CYREG_PHUB_CFGMEM4_CFG1 EQU 0x40007624 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_BASE +CYDEV_PHUB_CFGMEM5_BASE EQU 0x40007628 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_SIZE +CYDEV_PHUB_CFGMEM5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM5_CFG0 +CYREG_PHUB_CFGMEM5_CFG0 EQU 0x40007628 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM5_CFG1 +CYREG_PHUB_CFGMEM5_CFG1 EQU 0x4000762c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_BASE +CYDEV_PHUB_CFGMEM6_BASE EQU 0x40007630 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_SIZE +CYDEV_PHUB_CFGMEM6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM6_CFG0 +CYREG_PHUB_CFGMEM6_CFG0 EQU 0x40007630 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM6_CFG1 +CYREG_PHUB_CFGMEM6_CFG1 EQU 0x40007634 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_BASE +CYDEV_PHUB_CFGMEM7_BASE EQU 0x40007638 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_SIZE +CYDEV_PHUB_CFGMEM7_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM7_CFG0 +CYREG_PHUB_CFGMEM7_CFG0 EQU 0x40007638 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM7_CFG1 +CYREG_PHUB_CFGMEM7_CFG1 EQU 0x4000763c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_BASE +CYDEV_PHUB_CFGMEM8_BASE EQU 0x40007640 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_SIZE +CYDEV_PHUB_CFGMEM8_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM8_CFG0 +CYREG_PHUB_CFGMEM8_CFG0 EQU 0x40007640 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM8_CFG1 +CYREG_PHUB_CFGMEM8_CFG1 EQU 0x40007644 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_BASE +CYDEV_PHUB_CFGMEM9_BASE EQU 0x40007648 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_SIZE +CYDEV_PHUB_CFGMEM9_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM9_CFG0 +CYREG_PHUB_CFGMEM9_CFG0 EQU 0x40007648 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM9_CFG1 +CYREG_PHUB_CFGMEM9_CFG1 EQU 0x4000764c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_BASE +CYDEV_PHUB_CFGMEM10_BASE EQU 0x40007650 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_SIZE +CYDEV_PHUB_CFGMEM10_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM10_CFG0 +CYREG_PHUB_CFGMEM10_CFG0 EQU 0x40007650 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM10_CFG1 +CYREG_PHUB_CFGMEM10_CFG1 EQU 0x40007654 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_BASE +CYDEV_PHUB_CFGMEM11_BASE EQU 0x40007658 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_SIZE +CYDEV_PHUB_CFGMEM11_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM11_CFG0 +CYREG_PHUB_CFGMEM11_CFG0 EQU 0x40007658 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM11_CFG1 +CYREG_PHUB_CFGMEM11_CFG1 EQU 0x4000765c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_BASE +CYDEV_PHUB_CFGMEM12_BASE EQU 0x40007660 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_SIZE +CYDEV_PHUB_CFGMEM12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM12_CFG0 +CYREG_PHUB_CFGMEM12_CFG0 EQU 0x40007660 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM12_CFG1 +CYREG_PHUB_CFGMEM12_CFG1 EQU 0x40007664 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_BASE +CYDEV_PHUB_CFGMEM13_BASE EQU 0x40007668 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_SIZE +CYDEV_PHUB_CFGMEM13_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM13_CFG0 +CYREG_PHUB_CFGMEM13_CFG0 EQU 0x40007668 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM13_CFG1 +CYREG_PHUB_CFGMEM13_CFG1 EQU 0x4000766c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_BASE +CYDEV_PHUB_CFGMEM14_BASE EQU 0x40007670 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_SIZE +CYDEV_PHUB_CFGMEM14_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM14_CFG0 +CYREG_PHUB_CFGMEM14_CFG0 EQU 0x40007670 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM14_CFG1 +CYREG_PHUB_CFGMEM14_CFG1 EQU 0x40007674 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_BASE +CYDEV_PHUB_CFGMEM15_BASE EQU 0x40007678 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_SIZE +CYDEV_PHUB_CFGMEM15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM15_CFG0 +CYREG_PHUB_CFGMEM15_CFG0 EQU 0x40007678 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM15_CFG1 +CYREG_PHUB_CFGMEM15_CFG1 EQU 0x4000767c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_BASE +CYDEV_PHUB_CFGMEM16_BASE EQU 0x40007680 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_SIZE +CYDEV_PHUB_CFGMEM16_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM16_CFG0 +CYREG_PHUB_CFGMEM16_CFG0 EQU 0x40007680 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM16_CFG1 +CYREG_PHUB_CFGMEM16_CFG1 EQU 0x40007684 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_BASE +CYDEV_PHUB_CFGMEM17_BASE EQU 0x40007688 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_SIZE +CYDEV_PHUB_CFGMEM17_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM17_CFG0 +CYREG_PHUB_CFGMEM17_CFG0 EQU 0x40007688 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM17_CFG1 +CYREG_PHUB_CFGMEM17_CFG1 EQU 0x4000768c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_BASE +CYDEV_PHUB_CFGMEM18_BASE EQU 0x40007690 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_SIZE +CYDEV_PHUB_CFGMEM18_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM18_CFG0 +CYREG_PHUB_CFGMEM18_CFG0 EQU 0x40007690 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM18_CFG1 +CYREG_PHUB_CFGMEM18_CFG1 EQU 0x40007694 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_BASE +CYDEV_PHUB_CFGMEM19_BASE EQU 0x40007698 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_SIZE +CYDEV_PHUB_CFGMEM19_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM19_CFG0 +CYREG_PHUB_CFGMEM19_CFG0 EQU 0x40007698 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM19_CFG1 +CYREG_PHUB_CFGMEM19_CFG1 EQU 0x4000769c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_BASE +CYDEV_PHUB_CFGMEM20_BASE EQU 0x400076a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_SIZE +CYDEV_PHUB_CFGMEM20_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM20_CFG0 +CYREG_PHUB_CFGMEM20_CFG0 EQU 0x400076a0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM20_CFG1 +CYREG_PHUB_CFGMEM20_CFG1 EQU 0x400076a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_BASE +CYDEV_PHUB_CFGMEM21_BASE EQU 0x400076a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_SIZE +CYDEV_PHUB_CFGMEM21_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM21_CFG0 +CYREG_PHUB_CFGMEM21_CFG0 EQU 0x400076a8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM21_CFG1 +CYREG_PHUB_CFGMEM21_CFG1 EQU 0x400076ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_BASE +CYDEV_PHUB_CFGMEM22_BASE EQU 0x400076b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_SIZE +CYDEV_PHUB_CFGMEM22_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM22_CFG0 +CYREG_PHUB_CFGMEM22_CFG0 EQU 0x400076b0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM22_CFG1 +CYREG_PHUB_CFGMEM22_CFG1 EQU 0x400076b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_BASE +CYDEV_PHUB_CFGMEM23_BASE EQU 0x400076b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_SIZE +CYDEV_PHUB_CFGMEM23_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM23_CFG0 +CYREG_PHUB_CFGMEM23_CFG0 EQU 0x400076b8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM23_CFG1 +CYREG_PHUB_CFGMEM23_CFG1 EQU 0x400076bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_BASE +CYDEV_PHUB_TDMEM0_BASE EQU 0x40007800 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_SIZE +CYDEV_PHUB_TDMEM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM0_ORIG_TD0 +CYREG_PHUB_TDMEM0_ORIG_TD0 EQU 0x40007800 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM0_ORIG_TD1 +CYREG_PHUB_TDMEM0_ORIG_TD1 EQU 0x40007804 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_BASE +CYDEV_PHUB_TDMEM1_BASE EQU 0x40007808 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_SIZE +CYDEV_PHUB_TDMEM1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM1_ORIG_TD0 +CYREG_PHUB_TDMEM1_ORIG_TD0 EQU 0x40007808 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM1_ORIG_TD1 +CYREG_PHUB_TDMEM1_ORIG_TD1 EQU 0x4000780c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_BASE +CYDEV_PHUB_TDMEM2_BASE EQU 0x40007810 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_SIZE +CYDEV_PHUB_TDMEM2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM2_ORIG_TD0 +CYREG_PHUB_TDMEM2_ORIG_TD0 EQU 0x40007810 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM2_ORIG_TD1 +CYREG_PHUB_TDMEM2_ORIG_TD1 EQU 0x40007814 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_BASE +CYDEV_PHUB_TDMEM3_BASE EQU 0x40007818 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_SIZE +CYDEV_PHUB_TDMEM3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM3_ORIG_TD0 +CYREG_PHUB_TDMEM3_ORIG_TD0 EQU 0x40007818 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM3_ORIG_TD1 +CYREG_PHUB_TDMEM3_ORIG_TD1 EQU 0x4000781c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_BASE +CYDEV_PHUB_TDMEM4_BASE EQU 0x40007820 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_SIZE +CYDEV_PHUB_TDMEM4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM4_ORIG_TD0 +CYREG_PHUB_TDMEM4_ORIG_TD0 EQU 0x40007820 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM4_ORIG_TD1 +CYREG_PHUB_TDMEM4_ORIG_TD1 EQU 0x40007824 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_BASE +CYDEV_PHUB_TDMEM5_BASE EQU 0x40007828 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_SIZE +CYDEV_PHUB_TDMEM5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM5_ORIG_TD0 +CYREG_PHUB_TDMEM5_ORIG_TD0 EQU 0x40007828 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM5_ORIG_TD1 +CYREG_PHUB_TDMEM5_ORIG_TD1 EQU 0x4000782c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_BASE +CYDEV_PHUB_TDMEM6_BASE EQU 0x40007830 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_SIZE +CYDEV_PHUB_TDMEM6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM6_ORIG_TD0 +CYREG_PHUB_TDMEM6_ORIG_TD0 EQU 0x40007830 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM6_ORIG_TD1 +CYREG_PHUB_TDMEM6_ORIG_TD1 EQU 0x40007834 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_BASE +CYDEV_PHUB_TDMEM7_BASE EQU 0x40007838 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_SIZE +CYDEV_PHUB_TDMEM7_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM7_ORIG_TD0 +CYREG_PHUB_TDMEM7_ORIG_TD0 EQU 0x40007838 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM7_ORIG_TD1 +CYREG_PHUB_TDMEM7_ORIG_TD1 EQU 0x4000783c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_BASE +CYDEV_PHUB_TDMEM8_BASE EQU 0x40007840 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_SIZE +CYDEV_PHUB_TDMEM8_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM8_ORIG_TD0 +CYREG_PHUB_TDMEM8_ORIG_TD0 EQU 0x40007840 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM8_ORIG_TD1 +CYREG_PHUB_TDMEM8_ORIG_TD1 EQU 0x40007844 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_BASE +CYDEV_PHUB_TDMEM9_BASE EQU 0x40007848 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_SIZE +CYDEV_PHUB_TDMEM9_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM9_ORIG_TD0 +CYREG_PHUB_TDMEM9_ORIG_TD0 EQU 0x40007848 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM9_ORIG_TD1 +CYREG_PHUB_TDMEM9_ORIG_TD1 EQU 0x4000784c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_BASE +CYDEV_PHUB_TDMEM10_BASE EQU 0x40007850 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_SIZE +CYDEV_PHUB_TDMEM10_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM10_ORIG_TD0 +CYREG_PHUB_TDMEM10_ORIG_TD0 EQU 0x40007850 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM10_ORIG_TD1 +CYREG_PHUB_TDMEM10_ORIG_TD1 EQU 0x40007854 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_BASE +CYDEV_PHUB_TDMEM11_BASE EQU 0x40007858 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_SIZE +CYDEV_PHUB_TDMEM11_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM11_ORIG_TD0 +CYREG_PHUB_TDMEM11_ORIG_TD0 EQU 0x40007858 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM11_ORIG_TD1 +CYREG_PHUB_TDMEM11_ORIG_TD1 EQU 0x4000785c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_BASE +CYDEV_PHUB_TDMEM12_BASE EQU 0x40007860 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_SIZE +CYDEV_PHUB_TDMEM12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM12_ORIG_TD0 +CYREG_PHUB_TDMEM12_ORIG_TD0 EQU 0x40007860 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM12_ORIG_TD1 +CYREG_PHUB_TDMEM12_ORIG_TD1 EQU 0x40007864 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_BASE +CYDEV_PHUB_TDMEM13_BASE EQU 0x40007868 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_SIZE +CYDEV_PHUB_TDMEM13_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM13_ORIG_TD0 +CYREG_PHUB_TDMEM13_ORIG_TD0 EQU 0x40007868 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM13_ORIG_TD1 +CYREG_PHUB_TDMEM13_ORIG_TD1 EQU 0x4000786c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_BASE +CYDEV_PHUB_TDMEM14_BASE EQU 0x40007870 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_SIZE +CYDEV_PHUB_TDMEM14_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM14_ORIG_TD0 +CYREG_PHUB_TDMEM14_ORIG_TD0 EQU 0x40007870 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM14_ORIG_TD1 +CYREG_PHUB_TDMEM14_ORIG_TD1 EQU 0x40007874 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_BASE +CYDEV_PHUB_TDMEM15_BASE EQU 0x40007878 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_SIZE +CYDEV_PHUB_TDMEM15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM15_ORIG_TD0 +CYREG_PHUB_TDMEM15_ORIG_TD0 EQU 0x40007878 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM15_ORIG_TD1 +CYREG_PHUB_TDMEM15_ORIG_TD1 EQU 0x4000787c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_BASE +CYDEV_PHUB_TDMEM16_BASE EQU 0x40007880 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_SIZE +CYDEV_PHUB_TDMEM16_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM16_ORIG_TD0 +CYREG_PHUB_TDMEM16_ORIG_TD0 EQU 0x40007880 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM16_ORIG_TD1 +CYREG_PHUB_TDMEM16_ORIG_TD1 EQU 0x40007884 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_BASE +CYDEV_PHUB_TDMEM17_BASE EQU 0x40007888 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_SIZE +CYDEV_PHUB_TDMEM17_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM17_ORIG_TD0 +CYREG_PHUB_TDMEM17_ORIG_TD0 EQU 0x40007888 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM17_ORIG_TD1 +CYREG_PHUB_TDMEM17_ORIG_TD1 EQU 0x4000788c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_BASE +CYDEV_PHUB_TDMEM18_BASE EQU 0x40007890 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_SIZE +CYDEV_PHUB_TDMEM18_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM18_ORIG_TD0 +CYREG_PHUB_TDMEM18_ORIG_TD0 EQU 0x40007890 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM18_ORIG_TD1 +CYREG_PHUB_TDMEM18_ORIG_TD1 EQU 0x40007894 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_BASE +CYDEV_PHUB_TDMEM19_BASE EQU 0x40007898 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_SIZE +CYDEV_PHUB_TDMEM19_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM19_ORIG_TD0 +CYREG_PHUB_TDMEM19_ORIG_TD0 EQU 0x40007898 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM19_ORIG_TD1 +CYREG_PHUB_TDMEM19_ORIG_TD1 EQU 0x4000789c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_BASE +CYDEV_PHUB_TDMEM20_BASE EQU 0x400078a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_SIZE +CYDEV_PHUB_TDMEM20_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM20_ORIG_TD0 +CYREG_PHUB_TDMEM20_ORIG_TD0 EQU 0x400078a0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM20_ORIG_TD1 +CYREG_PHUB_TDMEM20_ORIG_TD1 EQU 0x400078a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_BASE +CYDEV_PHUB_TDMEM21_BASE EQU 0x400078a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_SIZE +CYDEV_PHUB_TDMEM21_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM21_ORIG_TD0 +CYREG_PHUB_TDMEM21_ORIG_TD0 EQU 0x400078a8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM21_ORIG_TD1 +CYREG_PHUB_TDMEM21_ORIG_TD1 EQU 0x400078ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_BASE +CYDEV_PHUB_TDMEM22_BASE EQU 0x400078b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_SIZE +CYDEV_PHUB_TDMEM22_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM22_ORIG_TD0 +CYREG_PHUB_TDMEM22_ORIG_TD0 EQU 0x400078b0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM22_ORIG_TD1 +CYREG_PHUB_TDMEM22_ORIG_TD1 EQU 0x400078b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_BASE +CYDEV_PHUB_TDMEM23_BASE EQU 0x400078b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_SIZE +CYDEV_PHUB_TDMEM23_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM23_ORIG_TD0 +CYREG_PHUB_TDMEM23_ORIG_TD0 EQU 0x400078b8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM23_ORIG_TD1 +CYREG_PHUB_TDMEM23_ORIG_TD1 EQU 0x400078bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_BASE +CYDEV_PHUB_TDMEM24_BASE EQU 0x400078c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_SIZE +CYDEV_PHUB_TDMEM24_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM24_ORIG_TD0 +CYREG_PHUB_TDMEM24_ORIG_TD0 EQU 0x400078c0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM24_ORIG_TD1 +CYREG_PHUB_TDMEM24_ORIG_TD1 EQU 0x400078c4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_BASE +CYDEV_PHUB_TDMEM25_BASE EQU 0x400078c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_SIZE +CYDEV_PHUB_TDMEM25_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM25_ORIG_TD0 +CYREG_PHUB_TDMEM25_ORIG_TD0 EQU 0x400078c8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM25_ORIG_TD1 +CYREG_PHUB_TDMEM25_ORIG_TD1 EQU 0x400078cc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_BASE +CYDEV_PHUB_TDMEM26_BASE EQU 0x400078d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_SIZE +CYDEV_PHUB_TDMEM26_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM26_ORIG_TD0 +CYREG_PHUB_TDMEM26_ORIG_TD0 EQU 0x400078d0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM26_ORIG_TD1 +CYREG_PHUB_TDMEM26_ORIG_TD1 EQU 0x400078d4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_BASE +CYDEV_PHUB_TDMEM27_BASE EQU 0x400078d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_SIZE +CYDEV_PHUB_TDMEM27_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM27_ORIG_TD0 +CYREG_PHUB_TDMEM27_ORIG_TD0 EQU 0x400078d8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM27_ORIG_TD1 +CYREG_PHUB_TDMEM27_ORIG_TD1 EQU 0x400078dc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_BASE +CYDEV_PHUB_TDMEM28_BASE EQU 0x400078e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_SIZE +CYDEV_PHUB_TDMEM28_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM28_ORIG_TD0 +CYREG_PHUB_TDMEM28_ORIG_TD0 EQU 0x400078e0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM28_ORIG_TD1 +CYREG_PHUB_TDMEM28_ORIG_TD1 EQU 0x400078e4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_BASE +CYDEV_PHUB_TDMEM29_BASE EQU 0x400078e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_SIZE +CYDEV_PHUB_TDMEM29_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM29_ORIG_TD0 +CYREG_PHUB_TDMEM29_ORIG_TD0 EQU 0x400078e8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM29_ORIG_TD1 +CYREG_PHUB_TDMEM29_ORIG_TD1 EQU 0x400078ec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_BASE +CYDEV_PHUB_TDMEM30_BASE EQU 0x400078f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_SIZE +CYDEV_PHUB_TDMEM30_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM30_ORIG_TD0 +CYREG_PHUB_TDMEM30_ORIG_TD0 EQU 0x400078f0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM30_ORIG_TD1 +CYREG_PHUB_TDMEM30_ORIG_TD1 EQU 0x400078f4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_BASE +CYDEV_PHUB_TDMEM31_BASE EQU 0x400078f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_SIZE +CYDEV_PHUB_TDMEM31_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM31_ORIG_TD0 +CYREG_PHUB_TDMEM31_ORIG_TD0 EQU 0x400078f8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM31_ORIG_TD1 +CYREG_PHUB_TDMEM31_ORIG_TD1 EQU 0x400078fc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_BASE +CYDEV_PHUB_TDMEM32_BASE EQU 0x40007900 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_SIZE +CYDEV_PHUB_TDMEM32_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM32_ORIG_TD0 +CYREG_PHUB_TDMEM32_ORIG_TD0 EQU 0x40007900 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM32_ORIG_TD1 +CYREG_PHUB_TDMEM32_ORIG_TD1 EQU 0x40007904 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_BASE +CYDEV_PHUB_TDMEM33_BASE EQU 0x40007908 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_SIZE +CYDEV_PHUB_TDMEM33_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM33_ORIG_TD0 +CYREG_PHUB_TDMEM33_ORIG_TD0 EQU 0x40007908 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM33_ORIG_TD1 +CYREG_PHUB_TDMEM33_ORIG_TD1 EQU 0x4000790c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_BASE +CYDEV_PHUB_TDMEM34_BASE EQU 0x40007910 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_SIZE +CYDEV_PHUB_TDMEM34_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM34_ORIG_TD0 +CYREG_PHUB_TDMEM34_ORIG_TD0 EQU 0x40007910 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM34_ORIG_TD1 +CYREG_PHUB_TDMEM34_ORIG_TD1 EQU 0x40007914 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_BASE +CYDEV_PHUB_TDMEM35_BASE EQU 0x40007918 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_SIZE +CYDEV_PHUB_TDMEM35_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM35_ORIG_TD0 +CYREG_PHUB_TDMEM35_ORIG_TD0 EQU 0x40007918 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM35_ORIG_TD1 +CYREG_PHUB_TDMEM35_ORIG_TD1 EQU 0x4000791c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_BASE +CYDEV_PHUB_TDMEM36_BASE EQU 0x40007920 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_SIZE +CYDEV_PHUB_TDMEM36_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM36_ORIG_TD0 +CYREG_PHUB_TDMEM36_ORIG_TD0 EQU 0x40007920 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM36_ORIG_TD1 +CYREG_PHUB_TDMEM36_ORIG_TD1 EQU 0x40007924 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_BASE +CYDEV_PHUB_TDMEM37_BASE EQU 0x40007928 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_SIZE +CYDEV_PHUB_TDMEM37_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM37_ORIG_TD0 +CYREG_PHUB_TDMEM37_ORIG_TD0 EQU 0x40007928 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM37_ORIG_TD1 +CYREG_PHUB_TDMEM37_ORIG_TD1 EQU 0x4000792c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_BASE +CYDEV_PHUB_TDMEM38_BASE EQU 0x40007930 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_SIZE +CYDEV_PHUB_TDMEM38_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM38_ORIG_TD0 +CYREG_PHUB_TDMEM38_ORIG_TD0 EQU 0x40007930 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM38_ORIG_TD1 +CYREG_PHUB_TDMEM38_ORIG_TD1 EQU 0x40007934 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_BASE +CYDEV_PHUB_TDMEM39_BASE EQU 0x40007938 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_SIZE +CYDEV_PHUB_TDMEM39_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM39_ORIG_TD0 +CYREG_PHUB_TDMEM39_ORIG_TD0 EQU 0x40007938 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM39_ORIG_TD1 +CYREG_PHUB_TDMEM39_ORIG_TD1 EQU 0x4000793c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_BASE +CYDEV_PHUB_TDMEM40_BASE EQU 0x40007940 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_SIZE +CYDEV_PHUB_TDMEM40_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM40_ORIG_TD0 +CYREG_PHUB_TDMEM40_ORIG_TD0 EQU 0x40007940 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM40_ORIG_TD1 +CYREG_PHUB_TDMEM40_ORIG_TD1 EQU 0x40007944 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_BASE +CYDEV_PHUB_TDMEM41_BASE EQU 0x40007948 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_SIZE +CYDEV_PHUB_TDMEM41_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM41_ORIG_TD0 +CYREG_PHUB_TDMEM41_ORIG_TD0 EQU 0x40007948 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM41_ORIG_TD1 +CYREG_PHUB_TDMEM41_ORIG_TD1 EQU 0x4000794c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_BASE +CYDEV_PHUB_TDMEM42_BASE EQU 0x40007950 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_SIZE +CYDEV_PHUB_TDMEM42_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM42_ORIG_TD0 +CYREG_PHUB_TDMEM42_ORIG_TD0 EQU 0x40007950 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM42_ORIG_TD1 +CYREG_PHUB_TDMEM42_ORIG_TD1 EQU 0x40007954 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_BASE +CYDEV_PHUB_TDMEM43_BASE EQU 0x40007958 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_SIZE +CYDEV_PHUB_TDMEM43_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM43_ORIG_TD0 +CYREG_PHUB_TDMEM43_ORIG_TD0 EQU 0x40007958 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM43_ORIG_TD1 +CYREG_PHUB_TDMEM43_ORIG_TD1 EQU 0x4000795c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_BASE +CYDEV_PHUB_TDMEM44_BASE EQU 0x40007960 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_SIZE +CYDEV_PHUB_TDMEM44_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM44_ORIG_TD0 +CYREG_PHUB_TDMEM44_ORIG_TD0 EQU 0x40007960 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM44_ORIG_TD1 +CYREG_PHUB_TDMEM44_ORIG_TD1 EQU 0x40007964 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_BASE +CYDEV_PHUB_TDMEM45_BASE EQU 0x40007968 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_SIZE +CYDEV_PHUB_TDMEM45_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM45_ORIG_TD0 +CYREG_PHUB_TDMEM45_ORIG_TD0 EQU 0x40007968 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM45_ORIG_TD1 +CYREG_PHUB_TDMEM45_ORIG_TD1 EQU 0x4000796c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_BASE +CYDEV_PHUB_TDMEM46_BASE EQU 0x40007970 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_SIZE +CYDEV_PHUB_TDMEM46_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM46_ORIG_TD0 +CYREG_PHUB_TDMEM46_ORIG_TD0 EQU 0x40007970 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM46_ORIG_TD1 +CYREG_PHUB_TDMEM46_ORIG_TD1 EQU 0x40007974 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_BASE +CYDEV_PHUB_TDMEM47_BASE EQU 0x40007978 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_SIZE +CYDEV_PHUB_TDMEM47_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM47_ORIG_TD0 +CYREG_PHUB_TDMEM47_ORIG_TD0 EQU 0x40007978 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM47_ORIG_TD1 +CYREG_PHUB_TDMEM47_ORIG_TD1 EQU 0x4000797c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_BASE +CYDEV_PHUB_TDMEM48_BASE EQU 0x40007980 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_SIZE +CYDEV_PHUB_TDMEM48_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM48_ORIG_TD0 +CYREG_PHUB_TDMEM48_ORIG_TD0 EQU 0x40007980 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM48_ORIG_TD1 +CYREG_PHUB_TDMEM48_ORIG_TD1 EQU 0x40007984 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_BASE +CYDEV_PHUB_TDMEM49_BASE EQU 0x40007988 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_SIZE +CYDEV_PHUB_TDMEM49_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM49_ORIG_TD0 +CYREG_PHUB_TDMEM49_ORIG_TD0 EQU 0x40007988 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM49_ORIG_TD1 +CYREG_PHUB_TDMEM49_ORIG_TD1 EQU 0x4000798c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_BASE +CYDEV_PHUB_TDMEM50_BASE EQU 0x40007990 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_SIZE +CYDEV_PHUB_TDMEM50_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM50_ORIG_TD0 +CYREG_PHUB_TDMEM50_ORIG_TD0 EQU 0x40007990 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM50_ORIG_TD1 +CYREG_PHUB_TDMEM50_ORIG_TD1 EQU 0x40007994 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_BASE +CYDEV_PHUB_TDMEM51_BASE EQU 0x40007998 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_SIZE +CYDEV_PHUB_TDMEM51_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM51_ORIG_TD0 +CYREG_PHUB_TDMEM51_ORIG_TD0 EQU 0x40007998 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM51_ORIG_TD1 +CYREG_PHUB_TDMEM51_ORIG_TD1 EQU 0x4000799c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_BASE +CYDEV_PHUB_TDMEM52_BASE EQU 0x400079a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_SIZE +CYDEV_PHUB_TDMEM52_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM52_ORIG_TD0 +CYREG_PHUB_TDMEM52_ORIG_TD0 EQU 0x400079a0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM52_ORIG_TD1 +CYREG_PHUB_TDMEM52_ORIG_TD1 EQU 0x400079a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_BASE +CYDEV_PHUB_TDMEM53_BASE EQU 0x400079a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_SIZE +CYDEV_PHUB_TDMEM53_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM53_ORIG_TD0 +CYREG_PHUB_TDMEM53_ORIG_TD0 EQU 0x400079a8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM53_ORIG_TD1 +CYREG_PHUB_TDMEM53_ORIG_TD1 EQU 0x400079ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_BASE +CYDEV_PHUB_TDMEM54_BASE EQU 0x400079b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_SIZE +CYDEV_PHUB_TDMEM54_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM54_ORIG_TD0 +CYREG_PHUB_TDMEM54_ORIG_TD0 EQU 0x400079b0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM54_ORIG_TD1 +CYREG_PHUB_TDMEM54_ORIG_TD1 EQU 0x400079b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_BASE +CYDEV_PHUB_TDMEM55_BASE EQU 0x400079b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_SIZE +CYDEV_PHUB_TDMEM55_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM55_ORIG_TD0 +CYREG_PHUB_TDMEM55_ORIG_TD0 EQU 0x400079b8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM55_ORIG_TD1 +CYREG_PHUB_TDMEM55_ORIG_TD1 EQU 0x400079bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_BASE +CYDEV_PHUB_TDMEM56_BASE EQU 0x400079c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_SIZE +CYDEV_PHUB_TDMEM56_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM56_ORIG_TD0 +CYREG_PHUB_TDMEM56_ORIG_TD0 EQU 0x400079c0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM56_ORIG_TD1 +CYREG_PHUB_TDMEM56_ORIG_TD1 EQU 0x400079c4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_BASE +CYDEV_PHUB_TDMEM57_BASE EQU 0x400079c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_SIZE +CYDEV_PHUB_TDMEM57_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM57_ORIG_TD0 +CYREG_PHUB_TDMEM57_ORIG_TD0 EQU 0x400079c8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM57_ORIG_TD1 +CYREG_PHUB_TDMEM57_ORIG_TD1 EQU 0x400079cc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_BASE +CYDEV_PHUB_TDMEM58_BASE EQU 0x400079d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_SIZE +CYDEV_PHUB_TDMEM58_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM58_ORIG_TD0 +CYREG_PHUB_TDMEM58_ORIG_TD0 EQU 0x400079d0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM58_ORIG_TD1 +CYREG_PHUB_TDMEM58_ORIG_TD1 EQU 0x400079d4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_BASE +CYDEV_PHUB_TDMEM59_BASE EQU 0x400079d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_SIZE +CYDEV_PHUB_TDMEM59_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM59_ORIG_TD0 +CYREG_PHUB_TDMEM59_ORIG_TD0 EQU 0x400079d8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM59_ORIG_TD1 +CYREG_PHUB_TDMEM59_ORIG_TD1 EQU 0x400079dc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_BASE +CYDEV_PHUB_TDMEM60_BASE EQU 0x400079e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_SIZE +CYDEV_PHUB_TDMEM60_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM60_ORIG_TD0 +CYREG_PHUB_TDMEM60_ORIG_TD0 EQU 0x400079e0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM60_ORIG_TD1 +CYREG_PHUB_TDMEM60_ORIG_TD1 EQU 0x400079e4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_BASE +CYDEV_PHUB_TDMEM61_BASE EQU 0x400079e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_SIZE +CYDEV_PHUB_TDMEM61_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM61_ORIG_TD0 +CYREG_PHUB_TDMEM61_ORIG_TD0 EQU 0x400079e8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM61_ORIG_TD1 +CYREG_PHUB_TDMEM61_ORIG_TD1 EQU 0x400079ec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_BASE +CYDEV_PHUB_TDMEM62_BASE EQU 0x400079f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_SIZE +CYDEV_PHUB_TDMEM62_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM62_ORIG_TD0 +CYREG_PHUB_TDMEM62_ORIG_TD0 EQU 0x400079f0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM62_ORIG_TD1 +CYREG_PHUB_TDMEM62_ORIG_TD1 EQU 0x400079f4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_BASE +CYDEV_PHUB_TDMEM63_BASE EQU 0x400079f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_SIZE +CYDEV_PHUB_TDMEM63_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM63_ORIG_TD0 +CYREG_PHUB_TDMEM63_ORIG_TD0 EQU 0x400079f8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM63_ORIG_TD1 +CYREG_PHUB_TDMEM63_ORIG_TD1 EQU 0x400079fc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_BASE +CYDEV_PHUB_TDMEM64_BASE EQU 0x40007a00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_SIZE +CYDEV_PHUB_TDMEM64_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM64_ORIG_TD0 +CYREG_PHUB_TDMEM64_ORIG_TD0 EQU 0x40007a00 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM64_ORIG_TD1 +CYREG_PHUB_TDMEM64_ORIG_TD1 EQU 0x40007a04 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_BASE +CYDEV_PHUB_TDMEM65_BASE EQU 0x40007a08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_SIZE +CYDEV_PHUB_TDMEM65_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM65_ORIG_TD0 +CYREG_PHUB_TDMEM65_ORIG_TD0 EQU 0x40007a08 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM65_ORIG_TD1 +CYREG_PHUB_TDMEM65_ORIG_TD1 EQU 0x40007a0c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_BASE +CYDEV_PHUB_TDMEM66_BASE EQU 0x40007a10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_SIZE +CYDEV_PHUB_TDMEM66_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM66_ORIG_TD0 +CYREG_PHUB_TDMEM66_ORIG_TD0 EQU 0x40007a10 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM66_ORIG_TD1 +CYREG_PHUB_TDMEM66_ORIG_TD1 EQU 0x40007a14 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_BASE +CYDEV_PHUB_TDMEM67_BASE EQU 0x40007a18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_SIZE +CYDEV_PHUB_TDMEM67_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM67_ORIG_TD0 +CYREG_PHUB_TDMEM67_ORIG_TD0 EQU 0x40007a18 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM67_ORIG_TD1 +CYREG_PHUB_TDMEM67_ORIG_TD1 EQU 0x40007a1c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_BASE +CYDEV_PHUB_TDMEM68_BASE EQU 0x40007a20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_SIZE +CYDEV_PHUB_TDMEM68_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM68_ORIG_TD0 +CYREG_PHUB_TDMEM68_ORIG_TD0 EQU 0x40007a20 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM68_ORIG_TD1 +CYREG_PHUB_TDMEM68_ORIG_TD1 EQU 0x40007a24 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_BASE +CYDEV_PHUB_TDMEM69_BASE EQU 0x40007a28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_SIZE +CYDEV_PHUB_TDMEM69_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM69_ORIG_TD0 +CYREG_PHUB_TDMEM69_ORIG_TD0 EQU 0x40007a28 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM69_ORIG_TD1 +CYREG_PHUB_TDMEM69_ORIG_TD1 EQU 0x40007a2c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_BASE +CYDEV_PHUB_TDMEM70_BASE EQU 0x40007a30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_SIZE +CYDEV_PHUB_TDMEM70_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM70_ORIG_TD0 +CYREG_PHUB_TDMEM70_ORIG_TD0 EQU 0x40007a30 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM70_ORIG_TD1 +CYREG_PHUB_TDMEM70_ORIG_TD1 EQU 0x40007a34 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_BASE +CYDEV_PHUB_TDMEM71_BASE EQU 0x40007a38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_SIZE +CYDEV_PHUB_TDMEM71_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM71_ORIG_TD0 +CYREG_PHUB_TDMEM71_ORIG_TD0 EQU 0x40007a38 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM71_ORIG_TD1 +CYREG_PHUB_TDMEM71_ORIG_TD1 EQU 0x40007a3c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_BASE +CYDEV_PHUB_TDMEM72_BASE EQU 0x40007a40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_SIZE +CYDEV_PHUB_TDMEM72_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM72_ORIG_TD0 +CYREG_PHUB_TDMEM72_ORIG_TD0 EQU 0x40007a40 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM72_ORIG_TD1 +CYREG_PHUB_TDMEM72_ORIG_TD1 EQU 0x40007a44 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_BASE +CYDEV_PHUB_TDMEM73_BASE EQU 0x40007a48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_SIZE +CYDEV_PHUB_TDMEM73_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM73_ORIG_TD0 +CYREG_PHUB_TDMEM73_ORIG_TD0 EQU 0x40007a48 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM73_ORIG_TD1 +CYREG_PHUB_TDMEM73_ORIG_TD1 EQU 0x40007a4c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_BASE +CYDEV_PHUB_TDMEM74_BASE EQU 0x40007a50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_SIZE +CYDEV_PHUB_TDMEM74_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM74_ORIG_TD0 +CYREG_PHUB_TDMEM74_ORIG_TD0 EQU 0x40007a50 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM74_ORIG_TD1 +CYREG_PHUB_TDMEM74_ORIG_TD1 EQU 0x40007a54 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_BASE +CYDEV_PHUB_TDMEM75_BASE EQU 0x40007a58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_SIZE +CYDEV_PHUB_TDMEM75_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM75_ORIG_TD0 +CYREG_PHUB_TDMEM75_ORIG_TD0 EQU 0x40007a58 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM75_ORIG_TD1 +CYREG_PHUB_TDMEM75_ORIG_TD1 EQU 0x40007a5c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_BASE +CYDEV_PHUB_TDMEM76_BASE EQU 0x40007a60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_SIZE +CYDEV_PHUB_TDMEM76_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM76_ORIG_TD0 +CYREG_PHUB_TDMEM76_ORIG_TD0 EQU 0x40007a60 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM76_ORIG_TD1 +CYREG_PHUB_TDMEM76_ORIG_TD1 EQU 0x40007a64 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_BASE +CYDEV_PHUB_TDMEM77_BASE EQU 0x40007a68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_SIZE +CYDEV_PHUB_TDMEM77_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM77_ORIG_TD0 +CYREG_PHUB_TDMEM77_ORIG_TD0 EQU 0x40007a68 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM77_ORIG_TD1 +CYREG_PHUB_TDMEM77_ORIG_TD1 EQU 0x40007a6c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_BASE +CYDEV_PHUB_TDMEM78_BASE EQU 0x40007a70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_SIZE +CYDEV_PHUB_TDMEM78_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM78_ORIG_TD0 +CYREG_PHUB_TDMEM78_ORIG_TD0 EQU 0x40007a70 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM78_ORIG_TD1 +CYREG_PHUB_TDMEM78_ORIG_TD1 EQU 0x40007a74 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_BASE +CYDEV_PHUB_TDMEM79_BASE EQU 0x40007a78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_SIZE +CYDEV_PHUB_TDMEM79_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM79_ORIG_TD0 +CYREG_PHUB_TDMEM79_ORIG_TD0 EQU 0x40007a78 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM79_ORIG_TD1 +CYREG_PHUB_TDMEM79_ORIG_TD1 EQU 0x40007a7c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_BASE +CYDEV_PHUB_TDMEM80_BASE EQU 0x40007a80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_SIZE +CYDEV_PHUB_TDMEM80_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM80_ORIG_TD0 +CYREG_PHUB_TDMEM80_ORIG_TD0 EQU 0x40007a80 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM80_ORIG_TD1 +CYREG_PHUB_TDMEM80_ORIG_TD1 EQU 0x40007a84 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_BASE +CYDEV_PHUB_TDMEM81_BASE EQU 0x40007a88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_SIZE +CYDEV_PHUB_TDMEM81_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM81_ORIG_TD0 +CYREG_PHUB_TDMEM81_ORIG_TD0 EQU 0x40007a88 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM81_ORIG_TD1 +CYREG_PHUB_TDMEM81_ORIG_TD1 EQU 0x40007a8c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_BASE +CYDEV_PHUB_TDMEM82_BASE EQU 0x40007a90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_SIZE +CYDEV_PHUB_TDMEM82_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM82_ORIG_TD0 +CYREG_PHUB_TDMEM82_ORIG_TD0 EQU 0x40007a90 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM82_ORIG_TD1 +CYREG_PHUB_TDMEM82_ORIG_TD1 EQU 0x40007a94 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_BASE +CYDEV_PHUB_TDMEM83_BASE EQU 0x40007a98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_SIZE +CYDEV_PHUB_TDMEM83_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM83_ORIG_TD0 +CYREG_PHUB_TDMEM83_ORIG_TD0 EQU 0x40007a98 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM83_ORIG_TD1 +CYREG_PHUB_TDMEM83_ORIG_TD1 EQU 0x40007a9c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_BASE +CYDEV_PHUB_TDMEM84_BASE EQU 0x40007aa0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_SIZE +CYDEV_PHUB_TDMEM84_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM84_ORIG_TD0 +CYREG_PHUB_TDMEM84_ORIG_TD0 EQU 0x40007aa0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM84_ORIG_TD1 +CYREG_PHUB_TDMEM84_ORIG_TD1 EQU 0x40007aa4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_BASE +CYDEV_PHUB_TDMEM85_BASE EQU 0x40007aa8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_SIZE +CYDEV_PHUB_TDMEM85_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM85_ORIG_TD0 +CYREG_PHUB_TDMEM85_ORIG_TD0 EQU 0x40007aa8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM85_ORIG_TD1 +CYREG_PHUB_TDMEM85_ORIG_TD1 EQU 0x40007aac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_BASE +CYDEV_PHUB_TDMEM86_BASE EQU 0x40007ab0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_SIZE +CYDEV_PHUB_TDMEM86_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM86_ORIG_TD0 +CYREG_PHUB_TDMEM86_ORIG_TD0 EQU 0x40007ab0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM86_ORIG_TD1 +CYREG_PHUB_TDMEM86_ORIG_TD1 EQU 0x40007ab4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_BASE +CYDEV_PHUB_TDMEM87_BASE EQU 0x40007ab8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_SIZE +CYDEV_PHUB_TDMEM87_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM87_ORIG_TD0 +CYREG_PHUB_TDMEM87_ORIG_TD0 EQU 0x40007ab8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM87_ORIG_TD1 +CYREG_PHUB_TDMEM87_ORIG_TD1 EQU 0x40007abc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_BASE +CYDEV_PHUB_TDMEM88_BASE EQU 0x40007ac0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_SIZE +CYDEV_PHUB_TDMEM88_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM88_ORIG_TD0 +CYREG_PHUB_TDMEM88_ORIG_TD0 EQU 0x40007ac0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM88_ORIG_TD1 +CYREG_PHUB_TDMEM88_ORIG_TD1 EQU 0x40007ac4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_BASE +CYDEV_PHUB_TDMEM89_BASE EQU 0x40007ac8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_SIZE +CYDEV_PHUB_TDMEM89_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM89_ORIG_TD0 +CYREG_PHUB_TDMEM89_ORIG_TD0 EQU 0x40007ac8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM89_ORIG_TD1 +CYREG_PHUB_TDMEM89_ORIG_TD1 EQU 0x40007acc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_BASE +CYDEV_PHUB_TDMEM90_BASE EQU 0x40007ad0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_SIZE +CYDEV_PHUB_TDMEM90_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM90_ORIG_TD0 +CYREG_PHUB_TDMEM90_ORIG_TD0 EQU 0x40007ad0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM90_ORIG_TD1 +CYREG_PHUB_TDMEM90_ORIG_TD1 EQU 0x40007ad4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_BASE +CYDEV_PHUB_TDMEM91_BASE EQU 0x40007ad8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_SIZE +CYDEV_PHUB_TDMEM91_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM91_ORIG_TD0 +CYREG_PHUB_TDMEM91_ORIG_TD0 EQU 0x40007ad8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM91_ORIG_TD1 +CYREG_PHUB_TDMEM91_ORIG_TD1 EQU 0x40007adc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_BASE +CYDEV_PHUB_TDMEM92_BASE EQU 0x40007ae0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_SIZE +CYDEV_PHUB_TDMEM92_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM92_ORIG_TD0 +CYREG_PHUB_TDMEM92_ORIG_TD0 EQU 0x40007ae0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM92_ORIG_TD1 +CYREG_PHUB_TDMEM92_ORIG_TD1 EQU 0x40007ae4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_BASE +CYDEV_PHUB_TDMEM93_BASE EQU 0x40007ae8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_SIZE +CYDEV_PHUB_TDMEM93_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM93_ORIG_TD0 +CYREG_PHUB_TDMEM93_ORIG_TD0 EQU 0x40007ae8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM93_ORIG_TD1 +CYREG_PHUB_TDMEM93_ORIG_TD1 EQU 0x40007aec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_BASE +CYDEV_PHUB_TDMEM94_BASE EQU 0x40007af0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_SIZE +CYDEV_PHUB_TDMEM94_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM94_ORIG_TD0 +CYREG_PHUB_TDMEM94_ORIG_TD0 EQU 0x40007af0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM94_ORIG_TD1 +CYREG_PHUB_TDMEM94_ORIG_TD1 EQU 0x40007af4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_BASE +CYDEV_PHUB_TDMEM95_BASE EQU 0x40007af8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_SIZE +CYDEV_PHUB_TDMEM95_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM95_ORIG_TD0 +CYREG_PHUB_TDMEM95_ORIG_TD0 EQU 0x40007af8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM95_ORIG_TD1 +CYREG_PHUB_TDMEM95_ORIG_TD1 EQU 0x40007afc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_BASE +CYDEV_PHUB_TDMEM96_BASE EQU 0x40007b00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_SIZE +CYDEV_PHUB_TDMEM96_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM96_ORIG_TD0 +CYREG_PHUB_TDMEM96_ORIG_TD0 EQU 0x40007b00 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM96_ORIG_TD1 +CYREG_PHUB_TDMEM96_ORIG_TD1 EQU 0x40007b04 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_BASE +CYDEV_PHUB_TDMEM97_BASE EQU 0x40007b08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_SIZE +CYDEV_PHUB_TDMEM97_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM97_ORIG_TD0 +CYREG_PHUB_TDMEM97_ORIG_TD0 EQU 0x40007b08 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM97_ORIG_TD1 +CYREG_PHUB_TDMEM97_ORIG_TD1 EQU 0x40007b0c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_BASE +CYDEV_PHUB_TDMEM98_BASE EQU 0x40007b10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_SIZE +CYDEV_PHUB_TDMEM98_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM98_ORIG_TD0 +CYREG_PHUB_TDMEM98_ORIG_TD0 EQU 0x40007b10 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM98_ORIG_TD1 +CYREG_PHUB_TDMEM98_ORIG_TD1 EQU 0x40007b14 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_BASE +CYDEV_PHUB_TDMEM99_BASE EQU 0x40007b18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_SIZE +CYDEV_PHUB_TDMEM99_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM99_ORIG_TD0 +CYREG_PHUB_TDMEM99_ORIG_TD0 EQU 0x40007b18 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM99_ORIG_TD1 +CYREG_PHUB_TDMEM99_ORIG_TD1 EQU 0x40007b1c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_BASE +CYDEV_PHUB_TDMEM100_BASE EQU 0x40007b20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_SIZE +CYDEV_PHUB_TDMEM100_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM100_ORIG_TD0 +CYREG_PHUB_TDMEM100_ORIG_TD0 EQU 0x40007b20 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM100_ORIG_TD1 +CYREG_PHUB_TDMEM100_ORIG_TD1 EQU 0x40007b24 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_BASE +CYDEV_PHUB_TDMEM101_BASE EQU 0x40007b28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_SIZE +CYDEV_PHUB_TDMEM101_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM101_ORIG_TD0 +CYREG_PHUB_TDMEM101_ORIG_TD0 EQU 0x40007b28 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM101_ORIG_TD1 +CYREG_PHUB_TDMEM101_ORIG_TD1 EQU 0x40007b2c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_BASE +CYDEV_PHUB_TDMEM102_BASE EQU 0x40007b30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_SIZE +CYDEV_PHUB_TDMEM102_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM102_ORIG_TD0 +CYREG_PHUB_TDMEM102_ORIG_TD0 EQU 0x40007b30 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM102_ORIG_TD1 +CYREG_PHUB_TDMEM102_ORIG_TD1 EQU 0x40007b34 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_BASE +CYDEV_PHUB_TDMEM103_BASE EQU 0x40007b38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_SIZE +CYDEV_PHUB_TDMEM103_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM103_ORIG_TD0 +CYREG_PHUB_TDMEM103_ORIG_TD0 EQU 0x40007b38 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM103_ORIG_TD1 +CYREG_PHUB_TDMEM103_ORIG_TD1 EQU 0x40007b3c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_BASE +CYDEV_PHUB_TDMEM104_BASE EQU 0x40007b40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_SIZE +CYDEV_PHUB_TDMEM104_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM104_ORIG_TD0 +CYREG_PHUB_TDMEM104_ORIG_TD0 EQU 0x40007b40 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM104_ORIG_TD1 +CYREG_PHUB_TDMEM104_ORIG_TD1 EQU 0x40007b44 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_BASE +CYDEV_PHUB_TDMEM105_BASE EQU 0x40007b48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_SIZE +CYDEV_PHUB_TDMEM105_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM105_ORIG_TD0 +CYREG_PHUB_TDMEM105_ORIG_TD0 EQU 0x40007b48 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM105_ORIG_TD1 +CYREG_PHUB_TDMEM105_ORIG_TD1 EQU 0x40007b4c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_BASE +CYDEV_PHUB_TDMEM106_BASE EQU 0x40007b50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_SIZE +CYDEV_PHUB_TDMEM106_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM106_ORIG_TD0 +CYREG_PHUB_TDMEM106_ORIG_TD0 EQU 0x40007b50 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM106_ORIG_TD1 +CYREG_PHUB_TDMEM106_ORIG_TD1 EQU 0x40007b54 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_BASE +CYDEV_PHUB_TDMEM107_BASE EQU 0x40007b58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_SIZE +CYDEV_PHUB_TDMEM107_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM107_ORIG_TD0 +CYREG_PHUB_TDMEM107_ORIG_TD0 EQU 0x40007b58 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM107_ORIG_TD1 +CYREG_PHUB_TDMEM107_ORIG_TD1 EQU 0x40007b5c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_BASE +CYDEV_PHUB_TDMEM108_BASE EQU 0x40007b60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_SIZE +CYDEV_PHUB_TDMEM108_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM108_ORIG_TD0 +CYREG_PHUB_TDMEM108_ORIG_TD0 EQU 0x40007b60 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM108_ORIG_TD1 +CYREG_PHUB_TDMEM108_ORIG_TD1 EQU 0x40007b64 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_BASE +CYDEV_PHUB_TDMEM109_BASE EQU 0x40007b68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_SIZE +CYDEV_PHUB_TDMEM109_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM109_ORIG_TD0 +CYREG_PHUB_TDMEM109_ORIG_TD0 EQU 0x40007b68 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM109_ORIG_TD1 +CYREG_PHUB_TDMEM109_ORIG_TD1 EQU 0x40007b6c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_BASE +CYDEV_PHUB_TDMEM110_BASE EQU 0x40007b70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_SIZE +CYDEV_PHUB_TDMEM110_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM110_ORIG_TD0 +CYREG_PHUB_TDMEM110_ORIG_TD0 EQU 0x40007b70 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM110_ORIG_TD1 +CYREG_PHUB_TDMEM110_ORIG_TD1 EQU 0x40007b74 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_BASE +CYDEV_PHUB_TDMEM111_BASE EQU 0x40007b78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_SIZE +CYDEV_PHUB_TDMEM111_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM111_ORIG_TD0 +CYREG_PHUB_TDMEM111_ORIG_TD0 EQU 0x40007b78 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM111_ORIG_TD1 +CYREG_PHUB_TDMEM111_ORIG_TD1 EQU 0x40007b7c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_BASE +CYDEV_PHUB_TDMEM112_BASE EQU 0x40007b80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_SIZE +CYDEV_PHUB_TDMEM112_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM112_ORIG_TD0 +CYREG_PHUB_TDMEM112_ORIG_TD0 EQU 0x40007b80 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM112_ORIG_TD1 +CYREG_PHUB_TDMEM112_ORIG_TD1 EQU 0x40007b84 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_BASE +CYDEV_PHUB_TDMEM113_BASE EQU 0x40007b88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_SIZE +CYDEV_PHUB_TDMEM113_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM113_ORIG_TD0 +CYREG_PHUB_TDMEM113_ORIG_TD0 EQU 0x40007b88 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM113_ORIG_TD1 +CYREG_PHUB_TDMEM113_ORIG_TD1 EQU 0x40007b8c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_BASE +CYDEV_PHUB_TDMEM114_BASE EQU 0x40007b90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_SIZE +CYDEV_PHUB_TDMEM114_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM114_ORIG_TD0 +CYREG_PHUB_TDMEM114_ORIG_TD0 EQU 0x40007b90 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM114_ORIG_TD1 +CYREG_PHUB_TDMEM114_ORIG_TD1 EQU 0x40007b94 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_BASE +CYDEV_PHUB_TDMEM115_BASE EQU 0x40007b98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_SIZE +CYDEV_PHUB_TDMEM115_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM115_ORIG_TD0 +CYREG_PHUB_TDMEM115_ORIG_TD0 EQU 0x40007b98 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM115_ORIG_TD1 +CYREG_PHUB_TDMEM115_ORIG_TD1 EQU 0x40007b9c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_BASE +CYDEV_PHUB_TDMEM116_BASE EQU 0x40007ba0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_SIZE +CYDEV_PHUB_TDMEM116_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM116_ORIG_TD0 +CYREG_PHUB_TDMEM116_ORIG_TD0 EQU 0x40007ba0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM116_ORIG_TD1 +CYREG_PHUB_TDMEM116_ORIG_TD1 EQU 0x40007ba4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_BASE +CYDEV_PHUB_TDMEM117_BASE EQU 0x40007ba8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_SIZE +CYDEV_PHUB_TDMEM117_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM117_ORIG_TD0 +CYREG_PHUB_TDMEM117_ORIG_TD0 EQU 0x40007ba8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM117_ORIG_TD1 +CYREG_PHUB_TDMEM117_ORIG_TD1 EQU 0x40007bac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_BASE +CYDEV_PHUB_TDMEM118_BASE EQU 0x40007bb0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_SIZE +CYDEV_PHUB_TDMEM118_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM118_ORIG_TD0 +CYREG_PHUB_TDMEM118_ORIG_TD0 EQU 0x40007bb0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM118_ORIG_TD1 +CYREG_PHUB_TDMEM118_ORIG_TD1 EQU 0x40007bb4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_BASE +CYDEV_PHUB_TDMEM119_BASE EQU 0x40007bb8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_SIZE +CYDEV_PHUB_TDMEM119_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM119_ORIG_TD0 +CYREG_PHUB_TDMEM119_ORIG_TD0 EQU 0x40007bb8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM119_ORIG_TD1 +CYREG_PHUB_TDMEM119_ORIG_TD1 EQU 0x40007bbc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_BASE +CYDEV_PHUB_TDMEM120_BASE EQU 0x40007bc0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_SIZE +CYDEV_PHUB_TDMEM120_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM120_ORIG_TD0 +CYREG_PHUB_TDMEM120_ORIG_TD0 EQU 0x40007bc0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM120_ORIG_TD1 +CYREG_PHUB_TDMEM120_ORIG_TD1 EQU 0x40007bc4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_BASE +CYDEV_PHUB_TDMEM121_BASE EQU 0x40007bc8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_SIZE +CYDEV_PHUB_TDMEM121_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM121_ORIG_TD0 +CYREG_PHUB_TDMEM121_ORIG_TD0 EQU 0x40007bc8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM121_ORIG_TD1 +CYREG_PHUB_TDMEM121_ORIG_TD1 EQU 0x40007bcc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_BASE +CYDEV_PHUB_TDMEM122_BASE EQU 0x40007bd0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_SIZE +CYDEV_PHUB_TDMEM122_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM122_ORIG_TD0 +CYREG_PHUB_TDMEM122_ORIG_TD0 EQU 0x40007bd0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM122_ORIG_TD1 +CYREG_PHUB_TDMEM122_ORIG_TD1 EQU 0x40007bd4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_BASE +CYDEV_PHUB_TDMEM123_BASE EQU 0x40007bd8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_SIZE +CYDEV_PHUB_TDMEM123_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM123_ORIG_TD0 +CYREG_PHUB_TDMEM123_ORIG_TD0 EQU 0x40007bd8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM123_ORIG_TD1 +CYREG_PHUB_TDMEM123_ORIG_TD1 EQU 0x40007bdc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_BASE +CYDEV_PHUB_TDMEM124_BASE EQU 0x40007be0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_SIZE +CYDEV_PHUB_TDMEM124_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM124_ORIG_TD0 +CYREG_PHUB_TDMEM124_ORIG_TD0 EQU 0x40007be0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM124_ORIG_TD1 +CYREG_PHUB_TDMEM124_ORIG_TD1 EQU 0x40007be4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_BASE +CYDEV_PHUB_TDMEM125_BASE EQU 0x40007be8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_SIZE +CYDEV_PHUB_TDMEM125_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM125_ORIG_TD0 +CYREG_PHUB_TDMEM125_ORIG_TD0 EQU 0x40007be8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM125_ORIG_TD1 +CYREG_PHUB_TDMEM125_ORIG_TD1 EQU 0x40007bec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_BASE +CYDEV_PHUB_TDMEM126_BASE EQU 0x40007bf0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_SIZE +CYDEV_PHUB_TDMEM126_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM126_ORIG_TD0 +CYREG_PHUB_TDMEM126_ORIG_TD0 EQU 0x40007bf0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM126_ORIG_TD1 +CYREG_PHUB_TDMEM126_ORIG_TD1 EQU 0x40007bf4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_BASE +CYDEV_PHUB_TDMEM127_BASE EQU 0x40007bf8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_SIZE +CYDEV_PHUB_TDMEM127_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM127_ORIG_TD0 +CYREG_PHUB_TDMEM127_ORIG_TD0 EQU 0x40007bf8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM127_ORIG_TD1 +CYREG_PHUB_TDMEM127_ORIG_TD1 EQU 0x40007bfc + ENDIF + IF :LNOT::DEF:CYDEV_EE_BASE +CYDEV_EE_BASE EQU 0x40008000 + ENDIF + IF :LNOT::DEF:CYDEV_EE_SIZE +CYDEV_EE_SIZE EQU 0x00000800 + ENDIF + IF :LNOT::DEF:CYREG_EE_DATA_MBASE +CYREG_EE_DATA_MBASE EQU 0x40008000 + ENDIF + IF :LNOT::DEF:CYREG_EE_DATA_MSIZE +CYREG_EE_DATA_MSIZE EQU 0x00000800 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_BASE +CYDEV_CAN0_BASE EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_SIZE +CYDEV_CAN0_SIZE EQU 0x000002a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_BASE +CYDEV_CAN0_CSR_BASE EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_SIZE +CYDEV_CAN0_CSR_SIZE EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_INT_SR +CYREG_CAN0_CSR_INT_SR EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_INT_EN +CYREG_CAN0_CSR_INT_EN EQU 0x4000a004 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_BUF_SR +CYREG_CAN0_CSR_BUF_SR EQU 0x4000a008 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_ERR_SR +CYREG_CAN0_CSR_ERR_SR EQU 0x4000a00c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_CMD +CYREG_CAN0_CSR_CMD EQU 0x4000a010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_CFG +CYREG_CAN0_CSR_CFG EQU 0x4000a014 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_BASE +CYDEV_CAN0_TX0_BASE EQU 0x4000a020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_SIZE +CYDEV_CAN0_TX0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX0_CMD +CYREG_CAN0_TX0_CMD EQU 0x4000a020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX0_ID +CYREG_CAN0_TX0_ID EQU 0x4000a024 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX0_DH +CYREG_CAN0_TX0_DH EQU 0x4000a028 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX0_DL +CYREG_CAN0_TX0_DL EQU 0x4000a02c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_BASE +CYDEV_CAN0_TX1_BASE EQU 0x4000a030 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_SIZE +CYDEV_CAN0_TX1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX1_CMD +CYREG_CAN0_TX1_CMD EQU 0x4000a030 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX1_ID +CYREG_CAN0_TX1_ID EQU 0x4000a034 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX1_DH +CYREG_CAN0_TX1_DH EQU 0x4000a038 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX1_DL +CYREG_CAN0_TX1_DL EQU 0x4000a03c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_BASE +CYDEV_CAN0_TX2_BASE EQU 0x4000a040 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_SIZE +CYDEV_CAN0_TX2_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX2_CMD +CYREG_CAN0_TX2_CMD EQU 0x4000a040 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX2_ID +CYREG_CAN0_TX2_ID EQU 0x4000a044 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX2_DH +CYREG_CAN0_TX2_DH EQU 0x4000a048 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX2_DL +CYREG_CAN0_TX2_DL EQU 0x4000a04c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_BASE +CYDEV_CAN0_TX3_BASE EQU 0x4000a050 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_SIZE +CYDEV_CAN0_TX3_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX3_CMD +CYREG_CAN0_TX3_CMD EQU 0x4000a050 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX3_ID +CYREG_CAN0_TX3_ID EQU 0x4000a054 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX3_DH +CYREG_CAN0_TX3_DH EQU 0x4000a058 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX3_DL +CYREG_CAN0_TX3_DL EQU 0x4000a05c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_BASE +CYDEV_CAN0_TX4_BASE EQU 0x4000a060 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_SIZE +CYDEV_CAN0_TX4_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX4_CMD +CYREG_CAN0_TX4_CMD EQU 0x4000a060 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX4_ID +CYREG_CAN0_TX4_ID EQU 0x4000a064 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX4_DH +CYREG_CAN0_TX4_DH EQU 0x4000a068 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX4_DL +CYREG_CAN0_TX4_DL EQU 0x4000a06c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_BASE +CYDEV_CAN0_TX5_BASE EQU 0x4000a070 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_SIZE +CYDEV_CAN0_TX5_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX5_CMD +CYREG_CAN0_TX5_CMD EQU 0x4000a070 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX5_ID +CYREG_CAN0_TX5_ID EQU 0x4000a074 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX5_DH +CYREG_CAN0_TX5_DH EQU 0x4000a078 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX5_DL +CYREG_CAN0_TX5_DL EQU 0x4000a07c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_BASE +CYDEV_CAN0_TX6_BASE EQU 0x4000a080 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_SIZE +CYDEV_CAN0_TX6_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX6_CMD +CYREG_CAN0_TX6_CMD EQU 0x4000a080 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX6_ID +CYREG_CAN0_TX6_ID EQU 0x4000a084 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX6_DH +CYREG_CAN0_TX6_DH EQU 0x4000a088 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX6_DL +CYREG_CAN0_TX6_DL EQU 0x4000a08c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_BASE +CYDEV_CAN0_TX7_BASE EQU 0x4000a090 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_SIZE +CYDEV_CAN0_TX7_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX7_CMD +CYREG_CAN0_TX7_CMD EQU 0x4000a090 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX7_ID +CYREG_CAN0_TX7_ID EQU 0x4000a094 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX7_DH +CYREG_CAN0_TX7_DH EQU 0x4000a098 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX7_DL +CYREG_CAN0_TX7_DL EQU 0x4000a09c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_BASE +CYDEV_CAN0_RX0_BASE EQU 0x4000a0a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_SIZE +CYDEV_CAN0_RX0_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_CMD +CYREG_CAN0_RX0_CMD EQU 0x4000a0a0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_ID +CYREG_CAN0_RX0_ID EQU 0x4000a0a4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_DH +CYREG_CAN0_RX0_DH EQU 0x4000a0a8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_DL +CYREG_CAN0_RX0_DL EQU 0x4000a0ac + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_AMR +CYREG_CAN0_RX0_AMR EQU 0x4000a0b0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_ACR +CYREG_CAN0_RX0_ACR EQU 0x4000a0b4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_AMRD +CYREG_CAN0_RX0_AMRD EQU 0x4000a0b8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_ACRD +CYREG_CAN0_RX0_ACRD EQU 0x4000a0bc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_BASE +CYDEV_CAN0_RX1_BASE EQU 0x4000a0c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_SIZE +CYDEV_CAN0_RX1_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_CMD +CYREG_CAN0_RX1_CMD EQU 0x4000a0c0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_ID +CYREG_CAN0_RX1_ID EQU 0x4000a0c4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_DH +CYREG_CAN0_RX1_DH EQU 0x4000a0c8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_DL +CYREG_CAN0_RX1_DL EQU 0x4000a0cc + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_AMR +CYREG_CAN0_RX1_AMR EQU 0x4000a0d0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_ACR +CYREG_CAN0_RX1_ACR EQU 0x4000a0d4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_AMRD +CYREG_CAN0_RX1_AMRD EQU 0x4000a0d8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_ACRD +CYREG_CAN0_RX1_ACRD EQU 0x4000a0dc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_BASE +CYDEV_CAN0_RX2_BASE EQU 0x4000a0e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_SIZE +CYDEV_CAN0_RX2_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_CMD +CYREG_CAN0_RX2_CMD EQU 0x4000a0e0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_ID +CYREG_CAN0_RX2_ID EQU 0x4000a0e4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_DH +CYREG_CAN0_RX2_DH EQU 0x4000a0e8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_DL +CYREG_CAN0_RX2_DL EQU 0x4000a0ec + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_AMR +CYREG_CAN0_RX2_AMR EQU 0x4000a0f0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_ACR +CYREG_CAN0_RX2_ACR EQU 0x4000a0f4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_AMRD +CYREG_CAN0_RX2_AMRD EQU 0x4000a0f8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_ACRD +CYREG_CAN0_RX2_ACRD EQU 0x4000a0fc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_BASE +CYDEV_CAN0_RX3_BASE EQU 0x4000a100 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_SIZE +CYDEV_CAN0_RX3_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_CMD +CYREG_CAN0_RX3_CMD EQU 0x4000a100 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_ID +CYREG_CAN0_RX3_ID EQU 0x4000a104 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_DH +CYREG_CAN0_RX3_DH EQU 0x4000a108 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_DL +CYREG_CAN0_RX3_DL EQU 0x4000a10c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_AMR +CYREG_CAN0_RX3_AMR EQU 0x4000a110 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_ACR +CYREG_CAN0_RX3_ACR EQU 0x4000a114 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_AMRD +CYREG_CAN0_RX3_AMRD EQU 0x4000a118 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_ACRD +CYREG_CAN0_RX3_ACRD EQU 0x4000a11c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_BASE +CYDEV_CAN0_RX4_BASE EQU 0x4000a120 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_SIZE +CYDEV_CAN0_RX4_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_CMD +CYREG_CAN0_RX4_CMD EQU 0x4000a120 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_ID +CYREG_CAN0_RX4_ID EQU 0x4000a124 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_DH +CYREG_CAN0_RX4_DH EQU 0x4000a128 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_DL +CYREG_CAN0_RX4_DL EQU 0x4000a12c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_AMR +CYREG_CAN0_RX4_AMR EQU 0x4000a130 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_ACR +CYREG_CAN0_RX4_ACR EQU 0x4000a134 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_AMRD +CYREG_CAN0_RX4_AMRD EQU 0x4000a138 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_ACRD +CYREG_CAN0_RX4_ACRD EQU 0x4000a13c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_BASE +CYDEV_CAN0_RX5_BASE EQU 0x4000a140 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_SIZE +CYDEV_CAN0_RX5_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_CMD +CYREG_CAN0_RX5_CMD EQU 0x4000a140 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_ID +CYREG_CAN0_RX5_ID EQU 0x4000a144 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_DH +CYREG_CAN0_RX5_DH EQU 0x4000a148 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_DL +CYREG_CAN0_RX5_DL EQU 0x4000a14c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_AMR +CYREG_CAN0_RX5_AMR EQU 0x4000a150 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_ACR +CYREG_CAN0_RX5_ACR EQU 0x4000a154 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_AMRD +CYREG_CAN0_RX5_AMRD EQU 0x4000a158 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_ACRD +CYREG_CAN0_RX5_ACRD EQU 0x4000a15c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_BASE +CYDEV_CAN0_RX6_BASE EQU 0x4000a160 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_SIZE +CYDEV_CAN0_RX6_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_CMD +CYREG_CAN0_RX6_CMD EQU 0x4000a160 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_ID +CYREG_CAN0_RX6_ID EQU 0x4000a164 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_DH +CYREG_CAN0_RX6_DH EQU 0x4000a168 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_DL +CYREG_CAN0_RX6_DL EQU 0x4000a16c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_AMR +CYREG_CAN0_RX6_AMR EQU 0x4000a170 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_ACR +CYREG_CAN0_RX6_ACR EQU 0x4000a174 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_AMRD +CYREG_CAN0_RX6_AMRD EQU 0x4000a178 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_ACRD +CYREG_CAN0_RX6_ACRD EQU 0x4000a17c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_BASE +CYDEV_CAN0_RX7_BASE EQU 0x4000a180 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_SIZE +CYDEV_CAN0_RX7_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_CMD +CYREG_CAN0_RX7_CMD EQU 0x4000a180 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_ID +CYREG_CAN0_RX7_ID EQU 0x4000a184 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_DH +CYREG_CAN0_RX7_DH EQU 0x4000a188 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_DL +CYREG_CAN0_RX7_DL EQU 0x4000a18c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_AMR +CYREG_CAN0_RX7_AMR EQU 0x4000a190 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_ACR +CYREG_CAN0_RX7_ACR EQU 0x4000a194 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_AMRD +CYREG_CAN0_RX7_AMRD EQU 0x4000a198 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_ACRD +CYREG_CAN0_RX7_ACRD EQU 0x4000a19c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_BASE +CYDEV_CAN0_RX8_BASE EQU 0x4000a1a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_SIZE +CYDEV_CAN0_RX8_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_CMD +CYREG_CAN0_RX8_CMD EQU 0x4000a1a0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_ID +CYREG_CAN0_RX8_ID EQU 0x4000a1a4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_DH +CYREG_CAN0_RX8_DH EQU 0x4000a1a8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_DL +CYREG_CAN0_RX8_DL EQU 0x4000a1ac + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_AMR +CYREG_CAN0_RX8_AMR EQU 0x4000a1b0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_ACR +CYREG_CAN0_RX8_ACR EQU 0x4000a1b4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_AMRD +CYREG_CAN0_RX8_AMRD EQU 0x4000a1b8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_ACRD +CYREG_CAN0_RX8_ACRD EQU 0x4000a1bc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_BASE +CYDEV_CAN0_RX9_BASE EQU 0x4000a1c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_SIZE +CYDEV_CAN0_RX9_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_CMD +CYREG_CAN0_RX9_CMD EQU 0x4000a1c0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_ID +CYREG_CAN0_RX9_ID EQU 0x4000a1c4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_DH +CYREG_CAN0_RX9_DH EQU 0x4000a1c8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_DL +CYREG_CAN0_RX9_DL EQU 0x4000a1cc + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_AMR +CYREG_CAN0_RX9_AMR EQU 0x4000a1d0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_ACR +CYREG_CAN0_RX9_ACR EQU 0x4000a1d4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_AMRD +CYREG_CAN0_RX9_AMRD EQU 0x4000a1d8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_ACRD +CYREG_CAN0_RX9_ACRD EQU 0x4000a1dc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_BASE +CYDEV_CAN0_RX10_BASE EQU 0x4000a1e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_SIZE +CYDEV_CAN0_RX10_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_CMD +CYREG_CAN0_RX10_CMD EQU 0x4000a1e0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_ID +CYREG_CAN0_RX10_ID EQU 0x4000a1e4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_DH +CYREG_CAN0_RX10_DH EQU 0x4000a1e8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_DL +CYREG_CAN0_RX10_DL EQU 0x4000a1ec + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_AMR +CYREG_CAN0_RX10_AMR EQU 0x4000a1f0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_ACR +CYREG_CAN0_RX10_ACR EQU 0x4000a1f4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_AMRD +CYREG_CAN0_RX10_AMRD EQU 0x4000a1f8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_ACRD +CYREG_CAN0_RX10_ACRD EQU 0x4000a1fc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_BASE +CYDEV_CAN0_RX11_BASE EQU 0x4000a200 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_SIZE +CYDEV_CAN0_RX11_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_CMD +CYREG_CAN0_RX11_CMD EQU 0x4000a200 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_ID +CYREG_CAN0_RX11_ID EQU 0x4000a204 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_DH +CYREG_CAN0_RX11_DH EQU 0x4000a208 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_DL +CYREG_CAN0_RX11_DL EQU 0x4000a20c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_AMR +CYREG_CAN0_RX11_AMR EQU 0x4000a210 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_ACR +CYREG_CAN0_RX11_ACR EQU 0x4000a214 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_AMRD +CYREG_CAN0_RX11_AMRD EQU 0x4000a218 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_ACRD +CYREG_CAN0_RX11_ACRD EQU 0x4000a21c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_BASE +CYDEV_CAN0_RX12_BASE EQU 0x4000a220 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_SIZE +CYDEV_CAN0_RX12_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_CMD +CYREG_CAN0_RX12_CMD EQU 0x4000a220 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_ID +CYREG_CAN0_RX12_ID EQU 0x4000a224 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_DH +CYREG_CAN0_RX12_DH EQU 0x4000a228 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_DL +CYREG_CAN0_RX12_DL EQU 0x4000a22c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_AMR +CYREG_CAN0_RX12_AMR EQU 0x4000a230 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_ACR +CYREG_CAN0_RX12_ACR EQU 0x4000a234 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_AMRD +CYREG_CAN0_RX12_AMRD EQU 0x4000a238 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_ACRD +CYREG_CAN0_RX12_ACRD EQU 0x4000a23c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_BASE +CYDEV_CAN0_RX13_BASE EQU 0x4000a240 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_SIZE +CYDEV_CAN0_RX13_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_CMD +CYREG_CAN0_RX13_CMD EQU 0x4000a240 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_ID +CYREG_CAN0_RX13_ID EQU 0x4000a244 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_DH +CYREG_CAN0_RX13_DH EQU 0x4000a248 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_DL +CYREG_CAN0_RX13_DL EQU 0x4000a24c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_AMR +CYREG_CAN0_RX13_AMR EQU 0x4000a250 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_ACR +CYREG_CAN0_RX13_ACR EQU 0x4000a254 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_AMRD +CYREG_CAN0_RX13_AMRD EQU 0x4000a258 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_ACRD +CYREG_CAN0_RX13_ACRD EQU 0x4000a25c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_BASE +CYDEV_CAN0_RX14_BASE EQU 0x4000a260 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_SIZE +CYDEV_CAN0_RX14_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_CMD +CYREG_CAN0_RX14_CMD EQU 0x4000a260 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_ID +CYREG_CAN0_RX14_ID EQU 0x4000a264 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_DH +CYREG_CAN0_RX14_DH EQU 0x4000a268 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_DL +CYREG_CAN0_RX14_DL EQU 0x4000a26c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_AMR +CYREG_CAN0_RX14_AMR EQU 0x4000a270 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_ACR +CYREG_CAN0_RX14_ACR EQU 0x4000a274 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_AMRD +CYREG_CAN0_RX14_AMRD EQU 0x4000a278 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_ACRD +CYREG_CAN0_RX14_ACRD EQU 0x4000a27c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_BASE +CYDEV_CAN0_RX15_BASE EQU 0x4000a280 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_SIZE +CYDEV_CAN0_RX15_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_CMD +CYREG_CAN0_RX15_CMD EQU 0x4000a280 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_ID +CYREG_CAN0_RX15_ID EQU 0x4000a284 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_DH +CYREG_CAN0_RX15_DH EQU 0x4000a288 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_DL +CYREG_CAN0_RX15_DL EQU 0x4000a28c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_AMR +CYREG_CAN0_RX15_AMR EQU 0x4000a290 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_ACR +CYREG_CAN0_RX15_ACR EQU 0x4000a294 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_AMRD +CYREG_CAN0_RX15_AMRD EQU 0x4000a298 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_ACRD +CYREG_CAN0_RX15_ACRD EQU 0x4000a29c + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_BASE +CYDEV_DFB0_BASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_SIZE +CYDEV_DFB0_SIZE EQU 0x000007b5 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_BASE +CYDEV_DFB0_DPA_SRAM_BASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_SIZE +CYDEV_DFB0_DPA_SRAM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DPA_SRAM_DATA_MBASE +CYREG_DFB0_DPA_SRAM_DATA_MBASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DPA_SRAM_DATA_MSIZE +CYREG_DFB0_DPA_SRAM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_BASE +CYDEV_DFB0_DPB_SRAM_BASE EQU 0x4000c200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_SIZE +CYDEV_DFB0_DPB_SRAM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DPB_SRAM_DATA_MBASE +CYREG_DFB0_DPB_SRAM_DATA_MBASE EQU 0x4000c200 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DPB_SRAM_DATA_MSIZE +CYREG_DFB0_DPB_SRAM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_BASE +CYDEV_DFB0_CSA_SRAM_BASE EQU 0x4000c400 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_SIZE +CYDEV_DFB0_CSA_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_CSA_SRAM_DATA_MBASE +CYREG_DFB0_CSA_SRAM_DATA_MBASE EQU 0x4000c400 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_CSA_SRAM_DATA_MSIZE +CYREG_DFB0_CSA_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_BASE +CYDEV_DFB0_CSB_SRAM_BASE EQU 0x4000c500 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_SIZE +CYDEV_DFB0_CSB_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_CSB_SRAM_DATA_MBASE +CYREG_DFB0_CSB_SRAM_DATA_MBASE EQU 0x4000c500 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_CSB_SRAM_DATA_MSIZE +CYREG_DFB0_CSB_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_BASE +CYDEV_DFB0_FSM_SRAM_BASE EQU 0x4000c600 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_SIZE +CYDEV_DFB0_FSM_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_FSM_SRAM_DATA_MBASE +CYREG_DFB0_FSM_SRAM_DATA_MBASE EQU 0x4000c600 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_FSM_SRAM_DATA_MSIZE +CYREG_DFB0_FSM_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_BASE +CYDEV_DFB0_ACU_SRAM_BASE EQU 0x4000c700 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_SIZE +CYDEV_DFB0_ACU_SRAM_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_ACU_SRAM_DATA_MBASE +CYREG_DFB0_ACU_SRAM_DATA_MBASE EQU 0x4000c700 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_ACU_SRAM_DATA_MSIZE +CYREG_DFB0_ACU_SRAM_DATA_MSIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_CR +CYREG_DFB0_CR EQU 0x4000c780 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_SR +CYREG_DFB0_SR EQU 0x4000c784 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_RAM_EN +CYREG_DFB0_RAM_EN EQU 0x4000c788 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_RAM_DIR +CYREG_DFB0_RAM_DIR EQU 0x4000c78c + ENDIF + IF :LNOT::DEF:CYREG_DFB0_SEMA +CYREG_DFB0_SEMA EQU 0x4000c790 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DSI_CTRL +CYREG_DFB0_DSI_CTRL EQU 0x4000c794 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_INT_CTRL +CYREG_DFB0_INT_CTRL EQU 0x4000c798 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DMA_CTRL +CYREG_DFB0_DMA_CTRL EQU 0x4000c79c + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEA +CYREG_DFB0_STAGEA EQU 0x4000c7a0 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEAM +CYREG_DFB0_STAGEAM EQU 0x4000c7a1 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEAH +CYREG_DFB0_STAGEAH EQU 0x4000c7a2 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEB +CYREG_DFB0_STAGEB EQU 0x4000c7a4 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEBM +CYREG_DFB0_STAGEBM EQU 0x4000c7a5 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEBH +CYREG_DFB0_STAGEBH EQU 0x4000c7a6 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDA +CYREG_DFB0_HOLDA EQU 0x4000c7a8 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDAM +CYREG_DFB0_HOLDAM EQU 0x4000c7a9 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDAH +CYREG_DFB0_HOLDAH EQU 0x4000c7aa + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDAS +CYREG_DFB0_HOLDAS EQU 0x4000c7ab + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDB +CYREG_DFB0_HOLDB EQU 0x4000c7ac + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDBM +CYREG_DFB0_HOLDBM EQU 0x4000c7ad + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDBH +CYREG_DFB0_HOLDBH EQU 0x4000c7ae + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDBS +CYREG_DFB0_HOLDBS EQU 0x4000c7af + ENDIF + IF :LNOT::DEF:CYREG_DFB0_COHER +CYREG_DFB0_COHER EQU 0x4000c7b0 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DALIGN +CYREG_DFB0_DALIGN EQU 0x4000c7b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BASE +CYDEV_UCFG_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_SIZE +CYDEV_UCFG_SIZE EQU 0x00005040 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_BASE +CYDEV_UCFG_B0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_SIZE +CYDEV_UCFG_B0_SIZE EQU 0x00000fef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_BASE +CYDEV_UCFG_B0_P0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_SIZE +CYDEV_UCFG_B0_P0_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_BASE +CYDEV_UCFG_B0_P0_U0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_SIZE +CYDEV_UCFG_B0_P0_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT0 +CYREG_B0_P0_U0_PLD_IT0 EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT1 +CYREG_B0_P0_U0_PLD_IT1 EQU 0x40010004 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT2 +CYREG_B0_P0_U0_PLD_IT2 EQU 0x40010008 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT3 +CYREG_B0_P0_U0_PLD_IT3 EQU 0x4001000c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT4 +CYREG_B0_P0_U0_PLD_IT4 EQU 0x40010010 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT5 +CYREG_B0_P0_U0_PLD_IT5 EQU 0x40010014 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT6 +CYREG_B0_P0_U0_PLD_IT6 EQU 0x40010018 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT7 +CYREG_B0_P0_U0_PLD_IT7 EQU 0x4001001c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT8 +CYREG_B0_P0_U0_PLD_IT8 EQU 0x40010020 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT9 +CYREG_B0_P0_U0_PLD_IT9 EQU 0x40010024 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT10 +CYREG_B0_P0_U0_PLD_IT10 EQU 0x40010028 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT11 +CYREG_B0_P0_U0_PLD_IT11 EQU 0x4001002c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_ORT0 +CYREG_B0_P0_U0_PLD_ORT0 EQU 0x40010030 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_ORT1 +CYREG_B0_P0_U0_PLD_ORT1 EQU 0x40010032 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_ORT2 +CYREG_B0_P0_U0_PLD_ORT2 EQU 0x40010034 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_ORT3 +CYREG_B0_P0_U0_PLD_ORT3 EQU 0x40010036 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_MC_CFG_CEN_CONST +CYREG_B0_P0_U0_MC_CFG_CEN_CONST EQU 0x40010038 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_MC_CFG_XORFB +CYREG_B0_P0_U0_MC_CFG_XORFB EQU 0x4001003a + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_MC_CFG_SET_RESET +CYREG_B0_P0_U0_MC_CFG_SET_RESET EQU 0x4001003c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_MC_CFG_BYPASS +CYREG_B0_P0_U0_MC_CFG_BYPASS EQU 0x4001003e + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG0 +CYREG_B0_P0_U0_CFG0 EQU 0x40010040 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG1 +CYREG_B0_P0_U0_CFG1 EQU 0x40010041 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG2 +CYREG_B0_P0_U0_CFG2 EQU 0x40010042 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG3 +CYREG_B0_P0_U0_CFG3 EQU 0x40010043 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG4 +CYREG_B0_P0_U0_CFG4 EQU 0x40010044 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG5 +CYREG_B0_P0_U0_CFG5 EQU 0x40010045 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG6 +CYREG_B0_P0_U0_CFG6 EQU 0x40010046 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG7 +CYREG_B0_P0_U0_CFG7 EQU 0x40010047 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG8 +CYREG_B0_P0_U0_CFG8 EQU 0x40010048 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG9 +CYREG_B0_P0_U0_CFG9 EQU 0x40010049 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG10 +CYREG_B0_P0_U0_CFG10 EQU 0x4001004a + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG11 +CYREG_B0_P0_U0_CFG11 EQU 0x4001004b + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG12 +CYREG_B0_P0_U0_CFG12 EQU 0x4001004c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG13 +CYREG_B0_P0_U0_CFG13 EQU 0x4001004d + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG14 +CYREG_B0_P0_U0_CFG14 EQU 0x4001004e + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG15 +CYREG_B0_P0_U0_CFG15 EQU 0x4001004f + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG16 +CYREG_B0_P0_U0_CFG16 EQU 0x40010050 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG17 +CYREG_B0_P0_U0_CFG17 EQU 0x40010051 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG18 +CYREG_B0_P0_U0_CFG18 EQU 0x40010052 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG19 +CYREG_B0_P0_U0_CFG19 EQU 0x40010053 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG20 +CYREG_B0_P0_U0_CFG20 EQU 0x40010054 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG21 +CYREG_B0_P0_U0_CFG21 EQU 0x40010055 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG22 +CYREG_B0_P0_U0_CFG22 EQU 0x40010056 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG23 +CYREG_B0_P0_U0_CFG23 EQU 0x40010057 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG24 +CYREG_B0_P0_U0_CFG24 EQU 0x40010058 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG25 +CYREG_B0_P0_U0_CFG25 EQU 0x40010059 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG26 +CYREG_B0_P0_U0_CFG26 EQU 0x4001005a + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG27 +CYREG_B0_P0_U0_CFG27 EQU 0x4001005b + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG28 +CYREG_B0_P0_U0_CFG28 EQU 0x4001005c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG29 +CYREG_B0_P0_U0_CFG29 EQU 0x4001005d + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG30 +CYREG_B0_P0_U0_CFG30 EQU 0x4001005e + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG31 +CYREG_B0_P0_U0_CFG31 EQU 0x4001005f + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG0 +CYREG_B0_P0_U0_DCFG0 EQU 0x40010060 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG1 +CYREG_B0_P0_U0_DCFG1 EQU 0x40010062 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG2 +CYREG_B0_P0_U0_DCFG2 EQU 0x40010064 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG3 +CYREG_B0_P0_U0_DCFG3 EQU 0x40010066 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG4 +CYREG_B0_P0_U0_DCFG4 EQU 0x40010068 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG5 +CYREG_B0_P0_U0_DCFG5 EQU 0x4001006a + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG6 +CYREG_B0_P0_U0_DCFG6 EQU 0x4001006c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG7 +CYREG_B0_P0_U0_DCFG7 EQU 0x4001006e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_BASE +CYDEV_UCFG_B0_P0_U1_BASE EQU 0x40010080 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_SIZE +CYDEV_UCFG_B0_P0_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT0 +CYREG_B0_P0_U1_PLD_IT0 EQU 0x40010080 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT1 +CYREG_B0_P0_U1_PLD_IT1 EQU 0x40010084 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT2 +CYREG_B0_P0_U1_PLD_IT2 EQU 0x40010088 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT3 +CYREG_B0_P0_U1_PLD_IT3 EQU 0x4001008c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT4 +CYREG_B0_P0_U1_PLD_IT4 EQU 0x40010090 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT5 +CYREG_B0_P0_U1_PLD_IT5 EQU 0x40010094 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT6 +CYREG_B0_P0_U1_PLD_IT6 EQU 0x40010098 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT7 +CYREG_B0_P0_U1_PLD_IT7 EQU 0x4001009c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT8 +CYREG_B0_P0_U1_PLD_IT8 EQU 0x400100a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT9 +CYREG_B0_P0_U1_PLD_IT9 EQU 0x400100a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT10 +CYREG_B0_P0_U1_PLD_IT10 EQU 0x400100a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT11 +CYREG_B0_P0_U1_PLD_IT11 EQU 0x400100ac + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_ORT0 +CYREG_B0_P0_U1_PLD_ORT0 EQU 0x400100b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_ORT1 +CYREG_B0_P0_U1_PLD_ORT1 EQU 0x400100b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_ORT2 +CYREG_B0_P0_U1_PLD_ORT2 EQU 0x400100b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_ORT3 +CYREG_B0_P0_U1_PLD_ORT3 EQU 0x400100b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_MC_CFG_CEN_CONST +CYREG_B0_P0_U1_MC_CFG_CEN_CONST EQU 0x400100b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_MC_CFG_XORFB +CYREG_B0_P0_U1_MC_CFG_XORFB EQU 0x400100ba + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_MC_CFG_SET_RESET +CYREG_B0_P0_U1_MC_CFG_SET_RESET EQU 0x400100bc + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_MC_CFG_BYPASS +CYREG_B0_P0_U1_MC_CFG_BYPASS EQU 0x400100be + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG0 +CYREG_B0_P0_U1_CFG0 EQU 0x400100c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG1 +CYREG_B0_P0_U1_CFG1 EQU 0x400100c1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG2 +CYREG_B0_P0_U1_CFG2 EQU 0x400100c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG3 +CYREG_B0_P0_U1_CFG3 EQU 0x400100c3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG4 +CYREG_B0_P0_U1_CFG4 EQU 0x400100c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG5 +CYREG_B0_P0_U1_CFG5 EQU 0x400100c5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG6 +CYREG_B0_P0_U1_CFG6 EQU 0x400100c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG7 +CYREG_B0_P0_U1_CFG7 EQU 0x400100c7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG8 +CYREG_B0_P0_U1_CFG8 EQU 0x400100c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG9 +CYREG_B0_P0_U1_CFG9 EQU 0x400100c9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG10 +CYREG_B0_P0_U1_CFG10 EQU 0x400100ca + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG11 +CYREG_B0_P0_U1_CFG11 EQU 0x400100cb + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG12 +CYREG_B0_P0_U1_CFG12 EQU 0x400100cc + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG13 +CYREG_B0_P0_U1_CFG13 EQU 0x400100cd + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG14 +CYREG_B0_P0_U1_CFG14 EQU 0x400100ce + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG15 +CYREG_B0_P0_U1_CFG15 EQU 0x400100cf + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG16 +CYREG_B0_P0_U1_CFG16 EQU 0x400100d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG17 +CYREG_B0_P0_U1_CFG17 EQU 0x400100d1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG18 +CYREG_B0_P0_U1_CFG18 EQU 0x400100d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG19 +CYREG_B0_P0_U1_CFG19 EQU 0x400100d3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG20 +CYREG_B0_P0_U1_CFG20 EQU 0x400100d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG21 +CYREG_B0_P0_U1_CFG21 EQU 0x400100d5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG22 +CYREG_B0_P0_U1_CFG22 EQU 0x400100d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG23 +CYREG_B0_P0_U1_CFG23 EQU 0x400100d7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG24 +CYREG_B0_P0_U1_CFG24 EQU 0x400100d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG25 +CYREG_B0_P0_U1_CFG25 EQU 0x400100d9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG26 +CYREG_B0_P0_U1_CFG26 EQU 0x400100da + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG27 +CYREG_B0_P0_U1_CFG27 EQU 0x400100db + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG28 +CYREG_B0_P0_U1_CFG28 EQU 0x400100dc + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG29 +CYREG_B0_P0_U1_CFG29 EQU 0x400100dd + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG30 +CYREG_B0_P0_U1_CFG30 EQU 0x400100de + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG31 +CYREG_B0_P0_U1_CFG31 EQU 0x400100df + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG0 +CYREG_B0_P0_U1_DCFG0 EQU 0x400100e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG1 +CYREG_B0_P0_U1_DCFG1 EQU 0x400100e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG2 +CYREG_B0_P0_U1_DCFG2 EQU 0x400100e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG3 +CYREG_B0_P0_U1_DCFG3 EQU 0x400100e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG4 +CYREG_B0_P0_U1_DCFG4 EQU 0x400100e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG5 +CYREG_B0_P0_U1_DCFG5 EQU 0x400100ea + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG6 +CYREG_B0_P0_U1_DCFG6 EQU 0x400100ec + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG7 +CYREG_B0_P0_U1_DCFG7 EQU 0x400100ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_ROUTE_BASE +CYDEV_UCFG_B0_P0_ROUTE_BASE EQU 0x40010100 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_ROUTE_SIZE +CYDEV_UCFG_B0_P0_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_BASE +CYDEV_UCFG_B0_P1_BASE EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_SIZE +CYDEV_UCFG_B0_P1_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_BASE +CYDEV_UCFG_B0_P1_U0_BASE EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_SIZE +CYDEV_UCFG_B0_P1_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT0 +CYREG_B0_P1_U0_PLD_IT0 EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT1 +CYREG_B0_P1_U0_PLD_IT1 EQU 0x40010204 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT2 +CYREG_B0_P1_U0_PLD_IT2 EQU 0x40010208 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT3 +CYREG_B0_P1_U0_PLD_IT3 EQU 0x4001020c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT4 +CYREG_B0_P1_U0_PLD_IT4 EQU 0x40010210 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT5 +CYREG_B0_P1_U0_PLD_IT5 EQU 0x40010214 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT6 +CYREG_B0_P1_U0_PLD_IT6 EQU 0x40010218 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT7 +CYREG_B0_P1_U0_PLD_IT7 EQU 0x4001021c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT8 +CYREG_B0_P1_U0_PLD_IT8 EQU 0x40010220 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT9 +CYREG_B0_P1_U0_PLD_IT9 EQU 0x40010224 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT10 +CYREG_B0_P1_U0_PLD_IT10 EQU 0x40010228 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT11 +CYREG_B0_P1_U0_PLD_IT11 EQU 0x4001022c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_ORT0 +CYREG_B0_P1_U0_PLD_ORT0 EQU 0x40010230 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_ORT1 +CYREG_B0_P1_U0_PLD_ORT1 EQU 0x40010232 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_ORT2 +CYREG_B0_P1_U0_PLD_ORT2 EQU 0x40010234 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_ORT3 +CYREG_B0_P1_U0_PLD_ORT3 EQU 0x40010236 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_MC_CFG_CEN_CONST +CYREG_B0_P1_U0_MC_CFG_CEN_CONST EQU 0x40010238 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_MC_CFG_XORFB +CYREG_B0_P1_U0_MC_CFG_XORFB EQU 0x4001023a + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_MC_CFG_SET_RESET +CYREG_B0_P1_U0_MC_CFG_SET_RESET EQU 0x4001023c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_MC_CFG_BYPASS +CYREG_B0_P1_U0_MC_CFG_BYPASS EQU 0x4001023e + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG0 +CYREG_B0_P1_U0_CFG0 EQU 0x40010240 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG1 +CYREG_B0_P1_U0_CFG1 EQU 0x40010241 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG2 +CYREG_B0_P1_U0_CFG2 EQU 0x40010242 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG3 +CYREG_B0_P1_U0_CFG3 EQU 0x40010243 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG4 +CYREG_B0_P1_U0_CFG4 EQU 0x40010244 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG5 +CYREG_B0_P1_U0_CFG5 EQU 0x40010245 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG6 +CYREG_B0_P1_U0_CFG6 EQU 0x40010246 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG7 +CYREG_B0_P1_U0_CFG7 EQU 0x40010247 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG8 +CYREG_B0_P1_U0_CFG8 EQU 0x40010248 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG9 +CYREG_B0_P1_U0_CFG9 EQU 0x40010249 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG10 +CYREG_B0_P1_U0_CFG10 EQU 0x4001024a + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG11 +CYREG_B0_P1_U0_CFG11 EQU 0x4001024b + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG12 +CYREG_B0_P1_U0_CFG12 EQU 0x4001024c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG13 +CYREG_B0_P1_U0_CFG13 EQU 0x4001024d + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG14 +CYREG_B0_P1_U0_CFG14 EQU 0x4001024e + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG15 +CYREG_B0_P1_U0_CFG15 EQU 0x4001024f + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG16 +CYREG_B0_P1_U0_CFG16 EQU 0x40010250 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG17 +CYREG_B0_P1_U0_CFG17 EQU 0x40010251 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG18 +CYREG_B0_P1_U0_CFG18 EQU 0x40010252 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG19 +CYREG_B0_P1_U0_CFG19 EQU 0x40010253 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG20 +CYREG_B0_P1_U0_CFG20 EQU 0x40010254 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG21 +CYREG_B0_P1_U0_CFG21 EQU 0x40010255 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG22 +CYREG_B0_P1_U0_CFG22 EQU 0x40010256 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG23 +CYREG_B0_P1_U0_CFG23 EQU 0x40010257 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG24 +CYREG_B0_P1_U0_CFG24 EQU 0x40010258 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG25 +CYREG_B0_P1_U0_CFG25 EQU 0x40010259 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG26 +CYREG_B0_P1_U0_CFG26 EQU 0x4001025a + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG27 +CYREG_B0_P1_U0_CFG27 EQU 0x4001025b + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG28 +CYREG_B0_P1_U0_CFG28 EQU 0x4001025c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG29 +CYREG_B0_P1_U0_CFG29 EQU 0x4001025d + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG30 +CYREG_B0_P1_U0_CFG30 EQU 0x4001025e + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG31 +CYREG_B0_P1_U0_CFG31 EQU 0x4001025f + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG0 +CYREG_B0_P1_U0_DCFG0 EQU 0x40010260 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG1 +CYREG_B0_P1_U0_DCFG1 EQU 0x40010262 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG2 +CYREG_B0_P1_U0_DCFG2 EQU 0x40010264 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG3 +CYREG_B0_P1_U0_DCFG3 EQU 0x40010266 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG4 +CYREG_B0_P1_U0_DCFG4 EQU 0x40010268 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG5 +CYREG_B0_P1_U0_DCFG5 EQU 0x4001026a + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG6 +CYREG_B0_P1_U0_DCFG6 EQU 0x4001026c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG7 +CYREG_B0_P1_U0_DCFG7 EQU 0x4001026e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_BASE +CYDEV_UCFG_B0_P1_U1_BASE EQU 0x40010280 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_SIZE +CYDEV_UCFG_B0_P1_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT0 +CYREG_B0_P1_U1_PLD_IT0 EQU 0x40010280 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT1 +CYREG_B0_P1_U1_PLD_IT1 EQU 0x40010284 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT2 +CYREG_B0_P1_U1_PLD_IT2 EQU 0x40010288 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT3 +CYREG_B0_P1_U1_PLD_IT3 EQU 0x4001028c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT4 +CYREG_B0_P1_U1_PLD_IT4 EQU 0x40010290 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT5 +CYREG_B0_P1_U1_PLD_IT5 EQU 0x40010294 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT6 +CYREG_B0_P1_U1_PLD_IT6 EQU 0x40010298 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT7 +CYREG_B0_P1_U1_PLD_IT7 EQU 0x4001029c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT8 +CYREG_B0_P1_U1_PLD_IT8 EQU 0x400102a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT9 +CYREG_B0_P1_U1_PLD_IT9 EQU 0x400102a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT10 +CYREG_B0_P1_U1_PLD_IT10 EQU 0x400102a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT11 +CYREG_B0_P1_U1_PLD_IT11 EQU 0x400102ac + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_ORT0 +CYREG_B0_P1_U1_PLD_ORT0 EQU 0x400102b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_ORT1 +CYREG_B0_P1_U1_PLD_ORT1 EQU 0x400102b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_ORT2 +CYREG_B0_P1_U1_PLD_ORT2 EQU 0x400102b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_ORT3 +CYREG_B0_P1_U1_PLD_ORT3 EQU 0x400102b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_MC_CFG_CEN_CONST +CYREG_B0_P1_U1_MC_CFG_CEN_CONST EQU 0x400102b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_MC_CFG_XORFB +CYREG_B0_P1_U1_MC_CFG_XORFB EQU 0x400102ba + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_MC_CFG_SET_RESET +CYREG_B0_P1_U1_MC_CFG_SET_RESET EQU 0x400102bc + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_MC_CFG_BYPASS +CYREG_B0_P1_U1_MC_CFG_BYPASS EQU 0x400102be + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG0 +CYREG_B0_P1_U1_CFG0 EQU 0x400102c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG1 +CYREG_B0_P1_U1_CFG1 EQU 0x400102c1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG2 +CYREG_B0_P1_U1_CFG2 EQU 0x400102c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG3 +CYREG_B0_P1_U1_CFG3 EQU 0x400102c3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG4 +CYREG_B0_P1_U1_CFG4 EQU 0x400102c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG5 +CYREG_B0_P1_U1_CFG5 EQU 0x400102c5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG6 +CYREG_B0_P1_U1_CFG6 EQU 0x400102c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG7 +CYREG_B0_P1_U1_CFG7 EQU 0x400102c7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG8 +CYREG_B0_P1_U1_CFG8 EQU 0x400102c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG9 +CYREG_B0_P1_U1_CFG9 EQU 0x400102c9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG10 +CYREG_B0_P1_U1_CFG10 EQU 0x400102ca + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG11 +CYREG_B0_P1_U1_CFG11 EQU 0x400102cb + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG12 +CYREG_B0_P1_U1_CFG12 EQU 0x400102cc + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG13 +CYREG_B0_P1_U1_CFG13 EQU 0x400102cd + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG14 +CYREG_B0_P1_U1_CFG14 EQU 0x400102ce + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG15 +CYREG_B0_P1_U1_CFG15 EQU 0x400102cf + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG16 +CYREG_B0_P1_U1_CFG16 EQU 0x400102d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG17 +CYREG_B0_P1_U1_CFG17 EQU 0x400102d1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG18 +CYREG_B0_P1_U1_CFG18 EQU 0x400102d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG19 +CYREG_B0_P1_U1_CFG19 EQU 0x400102d3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG20 +CYREG_B0_P1_U1_CFG20 EQU 0x400102d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG21 +CYREG_B0_P1_U1_CFG21 EQU 0x400102d5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG22 +CYREG_B0_P1_U1_CFG22 EQU 0x400102d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG23 +CYREG_B0_P1_U1_CFG23 EQU 0x400102d7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG24 +CYREG_B0_P1_U1_CFG24 EQU 0x400102d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG25 +CYREG_B0_P1_U1_CFG25 EQU 0x400102d9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG26 +CYREG_B0_P1_U1_CFG26 EQU 0x400102da + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG27 +CYREG_B0_P1_U1_CFG27 EQU 0x400102db + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG28 +CYREG_B0_P1_U1_CFG28 EQU 0x400102dc + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG29 +CYREG_B0_P1_U1_CFG29 EQU 0x400102dd + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG30 +CYREG_B0_P1_U1_CFG30 EQU 0x400102de + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG31 +CYREG_B0_P1_U1_CFG31 EQU 0x400102df + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG0 +CYREG_B0_P1_U1_DCFG0 EQU 0x400102e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG1 +CYREG_B0_P1_U1_DCFG1 EQU 0x400102e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG2 +CYREG_B0_P1_U1_DCFG2 EQU 0x400102e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG3 +CYREG_B0_P1_U1_DCFG3 EQU 0x400102e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG4 +CYREG_B0_P1_U1_DCFG4 EQU 0x400102e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG5 +CYREG_B0_P1_U1_DCFG5 EQU 0x400102ea + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG6 +CYREG_B0_P1_U1_DCFG6 EQU 0x400102ec + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG7 +CYREG_B0_P1_U1_DCFG7 EQU 0x400102ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_ROUTE_BASE +CYDEV_UCFG_B0_P1_ROUTE_BASE EQU 0x40010300 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_ROUTE_SIZE +CYDEV_UCFG_B0_P1_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_BASE +CYDEV_UCFG_B0_P2_BASE EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_SIZE +CYDEV_UCFG_B0_P2_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_BASE +CYDEV_UCFG_B0_P2_U0_BASE EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_SIZE +CYDEV_UCFG_B0_P2_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT0 +CYREG_B0_P2_U0_PLD_IT0 EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT1 +CYREG_B0_P2_U0_PLD_IT1 EQU 0x40010404 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT2 +CYREG_B0_P2_U0_PLD_IT2 EQU 0x40010408 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT3 +CYREG_B0_P2_U0_PLD_IT3 EQU 0x4001040c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT4 +CYREG_B0_P2_U0_PLD_IT4 EQU 0x40010410 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT5 +CYREG_B0_P2_U0_PLD_IT5 EQU 0x40010414 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT6 +CYREG_B0_P2_U0_PLD_IT6 EQU 0x40010418 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT7 +CYREG_B0_P2_U0_PLD_IT7 EQU 0x4001041c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT8 +CYREG_B0_P2_U0_PLD_IT8 EQU 0x40010420 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT9 +CYREG_B0_P2_U0_PLD_IT9 EQU 0x40010424 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT10 +CYREG_B0_P2_U0_PLD_IT10 EQU 0x40010428 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT11 +CYREG_B0_P2_U0_PLD_IT11 EQU 0x4001042c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_ORT0 +CYREG_B0_P2_U0_PLD_ORT0 EQU 0x40010430 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_ORT1 +CYREG_B0_P2_U0_PLD_ORT1 EQU 0x40010432 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_ORT2 +CYREG_B0_P2_U0_PLD_ORT2 EQU 0x40010434 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_ORT3 +CYREG_B0_P2_U0_PLD_ORT3 EQU 0x40010436 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_MC_CFG_CEN_CONST +CYREG_B0_P2_U0_MC_CFG_CEN_CONST EQU 0x40010438 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_MC_CFG_XORFB +CYREG_B0_P2_U0_MC_CFG_XORFB EQU 0x4001043a + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_MC_CFG_SET_RESET +CYREG_B0_P2_U0_MC_CFG_SET_RESET EQU 0x4001043c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_MC_CFG_BYPASS +CYREG_B0_P2_U0_MC_CFG_BYPASS EQU 0x4001043e + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG0 +CYREG_B0_P2_U0_CFG0 EQU 0x40010440 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG1 +CYREG_B0_P2_U0_CFG1 EQU 0x40010441 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG2 +CYREG_B0_P2_U0_CFG2 EQU 0x40010442 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG3 +CYREG_B0_P2_U0_CFG3 EQU 0x40010443 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG4 +CYREG_B0_P2_U0_CFG4 EQU 0x40010444 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG5 +CYREG_B0_P2_U0_CFG5 EQU 0x40010445 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG6 +CYREG_B0_P2_U0_CFG6 EQU 0x40010446 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG7 +CYREG_B0_P2_U0_CFG7 EQU 0x40010447 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG8 +CYREG_B0_P2_U0_CFG8 EQU 0x40010448 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG9 +CYREG_B0_P2_U0_CFG9 EQU 0x40010449 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG10 +CYREG_B0_P2_U0_CFG10 EQU 0x4001044a + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG11 +CYREG_B0_P2_U0_CFG11 EQU 0x4001044b + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG12 +CYREG_B0_P2_U0_CFG12 EQU 0x4001044c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG13 +CYREG_B0_P2_U0_CFG13 EQU 0x4001044d + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG14 +CYREG_B0_P2_U0_CFG14 EQU 0x4001044e + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG15 +CYREG_B0_P2_U0_CFG15 EQU 0x4001044f + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG16 +CYREG_B0_P2_U0_CFG16 EQU 0x40010450 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG17 +CYREG_B0_P2_U0_CFG17 EQU 0x40010451 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG18 +CYREG_B0_P2_U0_CFG18 EQU 0x40010452 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG19 +CYREG_B0_P2_U0_CFG19 EQU 0x40010453 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG20 +CYREG_B0_P2_U0_CFG20 EQU 0x40010454 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG21 +CYREG_B0_P2_U0_CFG21 EQU 0x40010455 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG22 +CYREG_B0_P2_U0_CFG22 EQU 0x40010456 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG23 +CYREG_B0_P2_U0_CFG23 EQU 0x40010457 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG24 +CYREG_B0_P2_U0_CFG24 EQU 0x40010458 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG25 +CYREG_B0_P2_U0_CFG25 EQU 0x40010459 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG26 +CYREG_B0_P2_U0_CFG26 EQU 0x4001045a + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG27 +CYREG_B0_P2_U0_CFG27 EQU 0x4001045b + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG28 +CYREG_B0_P2_U0_CFG28 EQU 0x4001045c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG29 +CYREG_B0_P2_U0_CFG29 EQU 0x4001045d + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG30 +CYREG_B0_P2_U0_CFG30 EQU 0x4001045e + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG31 +CYREG_B0_P2_U0_CFG31 EQU 0x4001045f + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG0 +CYREG_B0_P2_U0_DCFG0 EQU 0x40010460 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG1 +CYREG_B0_P2_U0_DCFG1 EQU 0x40010462 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG2 +CYREG_B0_P2_U0_DCFG2 EQU 0x40010464 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG3 +CYREG_B0_P2_U0_DCFG3 EQU 0x40010466 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG4 +CYREG_B0_P2_U0_DCFG4 EQU 0x40010468 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG5 +CYREG_B0_P2_U0_DCFG5 EQU 0x4001046a + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG6 +CYREG_B0_P2_U0_DCFG6 EQU 0x4001046c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG7 +CYREG_B0_P2_U0_DCFG7 EQU 0x4001046e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_BASE +CYDEV_UCFG_B0_P2_U1_BASE EQU 0x40010480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_SIZE +CYDEV_UCFG_B0_P2_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT0 +CYREG_B0_P2_U1_PLD_IT0 EQU 0x40010480 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT1 +CYREG_B0_P2_U1_PLD_IT1 EQU 0x40010484 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT2 +CYREG_B0_P2_U1_PLD_IT2 EQU 0x40010488 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT3 +CYREG_B0_P2_U1_PLD_IT3 EQU 0x4001048c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT4 +CYREG_B0_P2_U1_PLD_IT4 EQU 0x40010490 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT5 +CYREG_B0_P2_U1_PLD_IT5 EQU 0x40010494 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT6 +CYREG_B0_P2_U1_PLD_IT6 EQU 0x40010498 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT7 +CYREG_B0_P2_U1_PLD_IT7 EQU 0x4001049c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT8 +CYREG_B0_P2_U1_PLD_IT8 EQU 0x400104a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT9 +CYREG_B0_P2_U1_PLD_IT9 EQU 0x400104a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT10 +CYREG_B0_P2_U1_PLD_IT10 EQU 0x400104a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT11 +CYREG_B0_P2_U1_PLD_IT11 EQU 0x400104ac + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_ORT0 +CYREG_B0_P2_U1_PLD_ORT0 EQU 0x400104b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_ORT1 +CYREG_B0_P2_U1_PLD_ORT1 EQU 0x400104b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_ORT2 +CYREG_B0_P2_U1_PLD_ORT2 EQU 0x400104b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_ORT3 +CYREG_B0_P2_U1_PLD_ORT3 EQU 0x400104b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_MC_CFG_CEN_CONST +CYREG_B0_P2_U1_MC_CFG_CEN_CONST EQU 0x400104b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_MC_CFG_XORFB +CYREG_B0_P2_U1_MC_CFG_XORFB EQU 0x400104ba + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_MC_CFG_SET_RESET +CYREG_B0_P2_U1_MC_CFG_SET_RESET EQU 0x400104bc + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_MC_CFG_BYPASS +CYREG_B0_P2_U1_MC_CFG_BYPASS EQU 0x400104be + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG0 +CYREG_B0_P2_U1_CFG0 EQU 0x400104c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG1 +CYREG_B0_P2_U1_CFG1 EQU 0x400104c1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG2 +CYREG_B0_P2_U1_CFG2 EQU 0x400104c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG3 +CYREG_B0_P2_U1_CFG3 EQU 0x400104c3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG4 +CYREG_B0_P2_U1_CFG4 EQU 0x400104c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG5 +CYREG_B0_P2_U1_CFG5 EQU 0x400104c5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG6 +CYREG_B0_P2_U1_CFG6 EQU 0x400104c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG7 +CYREG_B0_P2_U1_CFG7 EQU 0x400104c7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG8 +CYREG_B0_P2_U1_CFG8 EQU 0x400104c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG9 +CYREG_B0_P2_U1_CFG9 EQU 0x400104c9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG10 +CYREG_B0_P2_U1_CFG10 EQU 0x400104ca + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG11 +CYREG_B0_P2_U1_CFG11 EQU 0x400104cb + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG12 +CYREG_B0_P2_U1_CFG12 EQU 0x400104cc + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG13 +CYREG_B0_P2_U1_CFG13 EQU 0x400104cd + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG14 +CYREG_B0_P2_U1_CFG14 EQU 0x400104ce + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG15 +CYREG_B0_P2_U1_CFG15 EQU 0x400104cf + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG16 +CYREG_B0_P2_U1_CFG16 EQU 0x400104d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG17 +CYREG_B0_P2_U1_CFG17 EQU 0x400104d1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG18 +CYREG_B0_P2_U1_CFG18 EQU 0x400104d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG19 +CYREG_B0_P2_U1_CFG19 EQU 0x400104d3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG20 +CYREG_B0_P2_U1_CFG20 EQU 0x400104d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG21 +CYREG_B0_P2_U1_CFG21 EQU 0x400104d5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG22 +CYREG_B0_P2_U1_CFG22 EQU 0x400104d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG23 +CYREG_B0_P2_U1_CFG23 EQU 0x400104d7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG24 +CYREG_B0_P2_U1_CFG24 EQU 0x400104d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG25 +CYREG_B0_P2_U1_CFG25 EQU 0x400104d9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG26 +CYREG_B0_P2_U1_CFG26 EQU 0x400104da + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG27 +CYREG_B0_P2_U1_CFG27 EQU 0x400104db + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG28 +CYREG_B0_P2_U1_CFG28 EQU 0x400104dc + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG29 +CYREG_B0_P2_U1_CFG29 EQU 0x400104dd + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG30 +CYREG_B0_P2_U1_CFG30 EQU 0x400104de + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG31 +CYREG_B0_P2_U1_CFG31 EQU 0x400104df + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG0 +CYREG_B0_P2_U1_DCFG0 EQU 0x400104e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG1 +CYREG_B0_P2_U1_DCFG1 EQU 0x400104e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG2 +CYREG_B0_P2_U1_DCFG2 EQU 0x400104e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG3 +CYREG_B0_P2_U1_DCFG3 EQU 0x400104e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG4 +CYREG_B0_P2_U1_DCFG4 EQU 0x400104e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG5 +CYREG_B0_P2_U1_DCFG5 EQU 0x400104ea + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG6 +CYREG_B0_P2_U1_DCFG6 EQU 0x400104ec + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG7 +CYREG_B0_P2_U1_DCFG7 EQU 0x400104ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_ROUTE_BASE +CYDEV_UCFG_B0_P2_ROUTE_BASE EQU 0x40010500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_ROUTE_SIZE +CYDEV_UCFG_B0_P2_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_BASE +CYDEV_UCFG_B0_P3_BASE EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_SIZE +CYDEV_UCFG_B0_P3_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_BASE +CYDEV_UCFG_B0_P3_U0_BASE EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_SIZE +CYDEV_UCFG_B0_P3_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT0 +CYREG_B0_P3_U0_PLD_IT0 EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT1 +CYREG_B0_P3_U0_PLD_IT1 EQU 0x40010604 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT2 +CYREG_B0_P3_U0_PLD_IT2 EQU 0x40010608 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT3 +CYREG_B0_P3_U0_PLD_IT3 EQU 0x4001060c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT4 +CYREG_B0_P3_U0_PLD_IT4 EQU 0x40010610 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT5 +CYREG_B0_P3_U0_PLD_IT5 EQU 0x40010614 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT6 +CYREG_B0_P3_U0_PLD_IT6 EQU 0x40010618 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT7 +CYREG_B0_P3_U0_PLD_IT7 EQU 0x4001061c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT8 +CYREG_B0_P3_U0_PLD_IT8 EQU 0x40010620 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT9 +CYREG_B0_P3_U0_PLD_IT9 EQU 0x40010624 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT10 +CYREG_B0_P3_U0_PLD_IT10 EQU 0x40010628 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT11 +CYREG_B0_P3_U0_PLD_IT11 EQU 0x4001062c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_ORT0 +CYREG_B0_P3_U0_PLD_ORT0 EQU 0x40010630 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_ORT1 +CYREG_B0_P3_U0_PLD_ORT1 EQU 0x40010632 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_ORT2 +CYREG_B0_P3_U0_PLD_ORT2 EQU 0x40010634 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_ORT3 +CYREG_B0_P3_U0_PLD_ORT3 EQU 0x40010636 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_MC_CFG_CEN_CONST +CYREG_B0_P3_U0_MC_CFG_CEN_CONST EQU 0x40010638 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_MC_CFG_XORFB +CYREG_B0_P3_U0_MC_CFG_XORFB EQU 0x4001063a + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_MC_CFG_SET_RESET +CYREG_B0_P3_U0_MC_CFG_SET_RESET EQU 0x4001063c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_MC_CFG_BYPASS +CYREG_B0_P3_U0_MC_CFG_BYPASS EQU 0x4001063e + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG0 +CYREG_B0_P3_U0_CFG0 EQU 0x40010640 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG1 +CYREG_B0_P3_U0_CFG1 EQU 0x40010641 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG2 +CYREG_B0_P3_U0_CFG2 EQU 0x40010642 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG3 +CYREG_B0_P3_U0_CFG3 EQU 0x40010643 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG4 +CYREG_B0_P3_U0_CFG4 EQU 0x40010644 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG5 +CYREG_B0_P3_U0_CFG5 EQU 0x40010645 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG6 +CYREG_B0_P3_U0_CFG6 EQU 0x40010646 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG7 +CYREG_B0_P3_U0_CFG7 EQU 0x40010647 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG8 +CYREG_B0_P3_U0_CFG8 EQU 0x40010648 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG9 +CYREG_B0_P3_U0_CFG9 EQU 0x40010649 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG10 +CYREG_B0_P3_U0_CFG10 EQU 0x4001064a + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG11 +CYREG_B0_P3_U0_CFG11 EQU 0x4001064b + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG12 +CYREG_B0_P3_U0_CFG12 EQU 0x4001064c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG13 +CYREG_B0_P3_U0_CFG13 EQU 0x4001064d + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG14 +CYREG_B0_P3_U0_CFG14 EQU 0x4001064e + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG15 +CYREG_B0_P3_U0_CFG15 EQU 0x4001064f + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG16 +CYREG_B0_P3_U0_CFG16 EQU 0x40010650 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG17 +CYREG_B0_P3_U0_CFG17 EQU 0x40010651 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG18 +CYREG_B0_P3_U0_CFG18 EQU 0x40010652 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG19 +CYREG_B0_P3_U0_CFG19 EQU 0x40010653 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG20 +CYREG_B0_P3_U0_CFG20 EQU 0x40010654 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG21 +CYREG_B0_P3_U0_CFG21 EQU 0x40010655 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG22 +CYREG_B0_P3_U0_CFG22 EQU 0x40010656 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG23 +CYREG_B0_P3_U0_CFG23 EQU 0x40010657 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG24 +CYREG_B0_P3_U0_CFG24 EQU 0x40010658 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG25 +CYREG_B0_P3_U0_CFG25 EQU 0x40010659 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG26 +CYREG_B0_P3_U0_CFG26 EQU 0x4001065a + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG27 +CYREG_B0_P3_U0_CFG27 EQU 0x4001065b + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG28 +CYREG_B0_P3_U0_CFG28 EQU 0x4001065c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG29 +CYREG_B0_P3_U0_CFG29 EQU 0x4001065d + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG30 +CYREG_B0_P3_U0_CFG30 EQU 0x4001065e + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG31 +CYREG_B0_P3_U0_CFG31 EQU 0x4001065f + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG0 +CYREG_B0_P3_U0_DCFG0 EQU 0x40010660 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG1 +CYREG_B0_P3_U0_DCFG1 EQU 0x40010662 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG2 +CYREG_B0_P3_U0_DCFG2 EQU 0x40010664 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG3 +CYREG_B0_P3_U0_DCFG3 EQU 0x40010666 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG4 +CYREG_B0_P3_U0_DCFG4 EQU 0x40010668 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG5 +CYREG_B0_P3_U0_DCFG5 EQU 0x4001066a + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG6 +CYREG_B0_P3_U0_DCFG6 EQU 0x4001066c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG7 +CYREG_B0_P3_U0_DCFG7 EQU 0x4001066e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_BASE +CYDEV_UCFG_B0_P3_U1_BASE EQU 0x40010680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_SIZE +CYDEV_UCFG_B0_P3_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT0 +CYREG_B0_P3_U1_PLD_IT0 EQU 0x40010680 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT1 +CYREG_B0_P3_U1_PLD_IT1 EQU 0x40010684 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT2 +CYREG_B0_P3_U1_PLD_IT2 EQU 0x40010688 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT3 +CYREG_B0_P3_U1_PLD_IT3 EQU 0x4001068c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT4 +CYREG_B0_P3_U1_PLD_IT4 EQU 0x40010690 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT5 +CYREG_B0_P3_U1_PLD_IT5 EQU 0x40010694 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT6 +CYREG_B0_P3_U1_PLD_IT6 EQU 0x40010698 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT7 +CYREG_B0_P3_U1_PLD_IT7 EQU 0x4001069c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT8 +CYREG_B0_P3_U1_PLD_IT8 EQU 0x400106a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT9 +CYREG_B0_P3_U1_PLD_IT9 EQU 0x400106a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT10 +CYREG_B0_P3_U1_PLD_IT10 EQU 0x400106a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT11 +CYREG_B0_P3_U1_PLD_IT11 EQU 0x400106ac + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_ORT0 +CYREG_B0_P3_U1_PLD_ORT0 EQU 0x400106b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_ORT1 +CYREG_B0_P3_U1_PLD_ORT1 EQU 0x400106b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_ORT2 +CYREG_B0_P3_U1_PLD_ORT2 EQU 0x400106b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_ORT3 +CYREG_B0_P3_U1_PLD_ORT3 EQU 0x400106b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_MC_CFG_CEN_CONST +CYREG_B0_P3_U1_MC_CFG_CEN_CONST EQU 0x400106b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_MC_CFG_XORFB +CYREG_B0_P3_U1_MC_CFG_XORFB EQU 0x400106ba + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_MC_CFG_SET_RESET +CYREG_B0_P3_U1_MC_CFG_SET_RESET EQU 0x400106bc + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_MC_CFG_BYPASS +CYREG_B0_P3_U1_MC_CFG_BYPASS EQU 0x400106be + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG0 +CYREG_B0_P3_U1_CFG0 EQU 0x400106c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG1 +CYREG_B0_P3_U1_CFG1 EQU 0x400106c1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG2 +CYREG_B0_P3_U1_CFG2 EQU 0x400106c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG3 +CYREG_B0_P3_U1_CFG3 EQU 0x400106c3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG4 +CYREG_B0_P3_U1_CFG4 EQU 0x400106c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG5 +CYREG_B0_P3_U1_CFG5 EQU 0x400106c5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG6 +CYREG_B0_P3_U1_CFG6 EQU 0x400106c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG7 +CYREG_B0_P3_U1_CFG7 EQU 0x400106c7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG8 +CYREG_B0_P3_U1_CFG8 EQU 0x400106c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG9 +CYREG_B0_P3_U1_CFG9 EQU 0x400106c9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG10 +CYREG_B0_P3_U1_CFG10 EQU 0x400106ca + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG11 +CYREG_B0_P3_U1_CFG11 EQU 0x400106cb + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG12 +CYREG_B0_P3_U1_CFG12 EQU 0x400106cc + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG13 +CYREG_B0_P3_U1_CFG13 EQU 0x400106cd + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG14 +CYREG_B0_P3_U1_CFG14 EQU 0x400106ce + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG15 +CYREG_B0_P3_U1_CFG15 EQU 0x400106cf + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG16 +CYREG_B0_P3_U1_CFG16 EQU 0x400106d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG17 +CYREG_B0_P3_U1_CFG17 EQU 0x400106d1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG18 +CYREG_B0_P3_U1_CFG18 EQU 0x400106d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG19 +CYREG_B0_P3_U1_CFG19 EQU 0x400106d3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG20 +CYREG_B0_P3_U1_CFG20 EQU 0x400106d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG21 +CYREG_B0_P3_U1_CFG21 EQU 0x400106d5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG22 +CYREG_B0_P3_U1_CFG22 EQU 0x400106d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG23 +CYREG_B0_P3_U1_CFG23 EQU 0x400106d7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG24 +CYREG_B0_P3_U1_CFG24 EQU 0x400106d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG25 +CYREG_B0_P3_U1_CFG25 EQU 0x400106d9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG26 +CYREG_B0_P3_U1_CFG26 EQU 0x400106da + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG27 +CYREG_B0_P3_U1_CFG27 EQU 0x400106db + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG28 +CYREG_B0_P3_U1_CFG28 EQU 0x400106dc + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG29 +CYREG_B0_P3_U1_CFG29 EQU 0x400106dd + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG30 +CYREG_B0_P3_U1_CFG30 EQU 0x400106de + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG31 +CYREG_B0_P3_U1_CFG31 EQU 0x400106df + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG0 +CYREG_B0_P3_U1_DCFG0 EQU 0x400106e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG1 +CYREG_B0_P3_U1_DCFG1 EQU 0x400106e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG2 +CYREG_B0_P3_U1_DCFG2 EQU 0x400106e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG3 +CYREG_B0_P3_U1_DCFG3 EQU 0x400106e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG4 +CYREG_B0_P3_U1_DCFG4 EQU 0x400106e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG5 +CYREG_B0_P3_U1_DCFG5 EQU 0x400106ea + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG6 +CYREG_B0_P3_U1_DCFG6 EQU 0x400106ec + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG7 +CYREG_B0_P3_U1_DCFG7 EQU 0x400106ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_ROUTE_BASE +CYDEV_UCFG_B0_P3_ROUTE_BASE EQU 0x40010700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_ROUTE_SIZE +CYDEV_UCFG_B0_P3_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_BASE +CYDEV_UCFG_B0_P4_BASE EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_SIZE +CYDEV_UCFG_B0_P4_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_BASE +CYDEV_UCFG_B0_P4_U0_BASE EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_SIZE +CYDEV_UCFG_B0_P4_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT0 +CYREG_B0_P4_U0_PLD_IT0 EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT1 +CYREG_B0_P4_U0_PLD_IT1 EQU 0x40010804 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT2 +CYREG_B0_P4_U0_PLD_IT2 EQU 0x40010808 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT3 +CYREG_B0_P4_U0_PLD_IT3 EQU 0x4001080c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT4 +CYREG_B0_P4_U0_PLD_IT4 EQU 0x40010810 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT5 +CYREG_B0_P4_U0_PLD_IT5 EQU 0x40010814 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT6 +CYREG_B0_P4_U0_PLD_IT6 EQU 0x40010818 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT7 +CYREG_B0_P4_U0_PLD_IT7 EQU 0x4001081c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT8 +CYREG_B0_P4_U0_PLD_IT8 EQU 0x40010820 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT9 +CYREG_B0_P4_U0_PLD_IT9 EQU 0x40010824 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT10 +CYREG_B0_P4_U0_PLD_IT10 EQU 0x40010828 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT11 +CYREG_B0_P4_U0_PLD_IT11 EQU 0x4001082c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_ORT0 +CYREG_B0_P4_U0_PLD_ORT0 EQU 0x40010830 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_ORT1 +CYREG_B0_P4_U0_PLD_ORT1 EQU 0x40010832 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_ORT2 +CYREG_B0_P4_U0_PLD_ORT2 EQU 0x40010834 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_ORT3 +CYREG_B0_P4_U0_PLD_ORT3 EQU 0x40010836 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_MC_CFG_CEN_CONST +CYREG_B0_P4_U0_MC_CFG_CEN_CONST EQU 0x40010838 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_MC_CFG_XORFB +CYREG_B0_P4_U0_MC_CFG_XORFB EQU 0x4001083a + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_MC_CFG_SET_RESET +CYREG_B0_P4_U0_MC_CFG_SET_RESET EQU 0x4001083c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_MC_CFG_BYPASS +CYREG_B0_P4_U0_MC_CFG_BYPASS EQU 0x4001083e + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG0 +CYREG_B0_P4_U0_CFG0 EQU 0x40010840 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG1 +CYREG_B0_P4_U0_CFG1 EQU 0x40010841 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG2 +CYREG_B0_P4_U0_CFG2 EQU 0x40010842 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG3 +CYREG_B0_P4_U0_CFG3 EQU 0x40010843 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG4 +CYREG_B0_P4_U0_CFG4 EQU 0x40010844 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG5 +CYREG_B0_P4_U0_CFG5 EQU 0x40010845 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG6 +CYREG_B0_P4_U0_CFG6 EQU 0x40010846 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG7 +CYREG_B0_P4_U0_CFG7 EQU 0x40010847 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG8 +CYREG_B0_P4_U0_CFG8 EQU 0x40010848 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG9 +CYREG_B0_P4_U0_CFG9 EQU 0x40010849 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG10 +CYREG_B0_P4_U0_CFG10 EQU 0x4001084a + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG11 +CYREG_B0_P4_U0_CFG11 EQU 0x4001084b + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG12 +CYREG_B0_P4_U0_CFG12 EQU 0x4001084c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG13 +CYREG_B0_P4_U0_CFG13 EQU 0x4001084d + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG14 +CYREG_B0_P4_U0_CFG14 EQU 0x4001084e + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG15 +CYREG_B0_P4_U0_CFG15 EQU 0x4001084f + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG16 +CYREG_B0_P4_U0_CFG16 EQU 0x40010850 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG17 +CYREG_B0_P4_U0_CFG17 EQU 0x40010851 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG18 +CYREG_B0_P4_U0_CFG18 EQU 0x40010852 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG19 +CYREG_B0_P4_U0_CFG19 EQU 0x40010853 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG20 +CYREG_B0_P4_U0_CFG20 EQU 0x40010854 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG21 +CYREG_B0_P4_U0_CFG21 EQU 0x40010855 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG22 +CYREG_B0_P4_U0_CFG22 EQU 0x40010856 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG23 +CYREG_B0_P4_U0_CFG23 EQU 0x40010857 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG24 +CYREG_B0_P4_U0_CFG24 EQU 0x40010858 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG25 +CYREG_B0_P4_U0_CFG25 EQU 0x40010859 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG26 +CYREG_B0_P4_U0_CFG26 EQU 0x4001085a + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG27 +CYREG_B0_P4_U0_CFG27 EQU 0x4001085b + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG28 +CYREG_B0_P4_U0_CFG28 EQU 0x4001085c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG29 +CYREG_B0_P4_U0_CFG29 EQU 0x4001085d + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG30 +CYREG_B0_P4_U0_CFG30 EQU 0x4001085e + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG31 +CYREG_B0_P4_U0_CFG31 EQU 0x4001085f + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG0 +CYREG_B0_P4_U0_DCFG0 EQU 0x40010860 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG1 +CYREG_B0_P4_U0_DCFG1 EQU 0x40010862 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG2 +CYREG_B0_P4_U0_DCFG2 EQU 0x40010864 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG3 +CYREG_B0_P4_U0_DCFG3 EQU 0x40010866 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG4 +CYREG_B0_P4_U0_DCFG4 EQU 0x40010868 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG5 +CYREG_B0_P4_U0_DCFG5 EQU 0x4001086a + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG6 +CYREG_B0_P4_U0_DCFG6 EQU 0x4001086c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG7 +CYREG_B0_P4_U0_DCFG7 EQU 0x4001086e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_BASE +CYDEV_UCFG_B0_P4_U1_BASE EQU 0x40010880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_SIZE +CYDEV_UCFG_B0_P4_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT0 +CYREG_B0_P4_U1_PLD_IT0 EQU 0x40010880 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT1 +CYREG_B0_P4_U1_PLD_IT1 EQU 0x40010884 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT2 +CYREG_B0_P4_U1_PLD_IT2 EQU 0x40010888 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT3 +CYREG_B0_P4_U1_PLD_IT3 EQU 0x4001088c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT4 +CYREG_B0_P4_U1_PLD_IT4 EQU 0x40010890 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT5 +CYREG_B0_P4_U1_PLD_IT5 EQU 0x40010894 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT6 +CYREG_B0_P4_U1_PLD_IT6 EQU 0x40010898 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT7 +CYREG_B0_P4_U1_PLD_IT7 EQU 0x4001089c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT8 +CYREG_B0_P4_U1_PLD_IT8 EQU 0x400108a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT9 +CYREG_B0_P4_U1_PLD_IT9 EQU 0x400108a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT10 +CYREG_B0_P4_U1_PLD_IT10 EQU 0x400108a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT11 +CYREG_B0_P4_U1_PLD_IT11 EQU 0x400108ac + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_ORT0 +CYREG_B0_P4_U1_PLD_ORT0 EQU 0x400108b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_ORT1 +CYREG_B0_P4_U1_PLD_ORT1 EQU 0x400108b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_ORT2 +CYREG_B0_P4_U1_PLD_ORT2 EQU 0x400108b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_ORT3 +CYREG_B0_P4_U1_PLD_ORT3 EQU 0x400108b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_MC_CFG_CEN_CONST +CYREG_B0_P4_U1_MC_CFG_CEN_CONST EQU 0x400108b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_MC_CFG_XORFB +CYREG_B0_P4_U1_MC_CFG_XORFB EQU 0x400108ba + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_MC_CFG_SET_RESET +CYREG_B0_P4_U1_MC_CFG_SET_RESET EQU 0x400108bc + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_MC_CFG_BYPASS +CYREG_B0_P4_U1_MC_CFG_BYPASS EQU 0x400108be + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG0 +CYREG_B0_P4_U1_CFG0 EQU 0x400108c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG1 +CYREG_B0_P4_U1_CFG1 EQU 0x400108c1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG2 +CYREG_B0_P4_U1_CFG2 EQU 0x400108c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG3 +CYREG_B0_P4_U1_CFG3 EQU 0x400108c3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG4 +CYREG_B0_P4_U1_CFG4 EQU 0x400108c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG5 +CYREG_B0_P4_U1_CFG5 EQU 0x400108c5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG6 +CYREG_B0_P4_U1_CFG6 EQU 0x400108c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG7 +CYREG_B0_P4_U1_CFG7 EQU 0x400108c7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG8 +CYREG_B0_P4_U1_CFG8 EQU 0x400108c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG9 +CYREG_B0_P4_U1_CFG9 EQU 0x400108c9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG10 +CYREG_B0_P4_U1_CFG10 EQU 0x400108ca + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG11 +CYREG_B0_P4_U1_CFG11 EQU 0x400108cb + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG12 +CYREG_B0_P4_U1_CFG12 EQU 0x400108cc + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG13 +CYREG_B0_P4_U1_CFG13 EQU 0x400108cd + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG14 +CYREG_B0_P4_U1_CFG14 EQU 0x400108ce + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG15 +CYREG_B0_P4_U1_CFG15 EQU 0x400108cf + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG16 +CYREG_B0_P4_U1_CFG16 EQU 0x400108d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG17 +CYREG_B0_P4_U1_CFG17 EQU 0x400108d1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG18 +CYREG_B0_P4_U1_CFG18 EQU 0x400108d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG19 +CYREG_B0_P4_U1_CFG19 EQU 0x400108d3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG20 +CYREG_B0_P4_U1_CFG20 EQU 0x400108d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG21 +CYREG_B0_P4_U1_CFG21 EQU 0x400108d5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG22 +CYREG_B0_P4_U1_CFG22 EQU 0x400108d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG23 +CYREG_B0_P4_U1_CFG23 EQU 0x400108d7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG24 +CYREG_B0_P4_U1_CFG24 EQU 0x400108d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG25 +CYREG_B0_P4_U1_CFG25 EQU 0x400108d9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG26 +CYREG_B0_P4_U1_CFG26 EQU 0x400108da + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG27 +CYREG_B0_P4_U1_CFG27 EQU 0x400108db + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG28 +CYREG_B0_P4_U1_CFG28 EQU 0x400108dc + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG29 +CYREG_B0_P4_U1_CFG29 EQU 0x400108dd + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG30 +CYREG_B0_P4_U1_CFG30 EQU 0x400108de + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG31 +CYREG_B0_P4_U1_CFG31 EQU 0x400108df + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG0 +CYREG_B0_P4_U1_DCFG0 EQU 0x400108e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG1 +CYREG_B0_P4_U1_DCFG1 EQU 0x400108e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG2 +CYREG_B0_P4_U1_DCFG2 EQU 0x400108e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG3 +CYREG_B0_P4_U1_DCFG3 EQU 0x400108e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG4 +CYREG_B0_P4_U1_DCFG4 EQU 0x400108e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG5 +CYREG_B0_P4_U1_DCFG5 EQU 0x400108ea + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG6 +CYREG_B0_P4_U1_DCFG6 EQU 0x400108ec + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG7 +CYREG_B0_P4_U1_DCFG7 EQU 0x400108ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_ROUTE_BASE +CYDEV_UCFG_B0_P4_ROUTE_BASE EQU 0x40010900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_ROUTE_SIZE +CYDEV_UCFG_B0_P4_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_BASE +CYDEV_UCFG_B0_P5_BASE EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_SIZE +CYDEV_UCFG_B0_P5_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_BASE +CYDEV_UCFG_B0_P5_U0_BASE EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_SIZE +CYDEV_UCFG_B0_P5_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT0 +CYREG_B0_P5_U0_PLD_IT0 EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT1 +CYREG_B0_P5_U0_PLD_IT1 EQU 0x40010a04 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT2 +CYREG_B0_P5_U0_PLD_IT2 EQU 0x40010a08 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT3 +CYREG_B0_P5_U0_PLD_IT3 EQU 0x40010a0c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT4 +CYREG_B0_P5_U0_PLD_IT4 EQU 0x40010a10 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT5 +CYREG_B0_P5_U0_PLD_IT5 EQU 0x40010a14 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT6 +CYREG_B0_P5_U0_PLD_IT6 EQU 0x40010a18 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT7 +CYREG_B0_P5_U0_PLD_IT7 EQU 0x40010a1c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT8 +CYREG_B0_P5_U0_PLD_IT8 EQU 0x40010a20 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT9 +CYREG_B0_P5_U0_PLD_IT9 EQU 0x40010a24 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT10 +CYREG_B0_P5_U0_PLD_IT10 EQU 0x40010a28 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT11 +CYREG_B0_P5_U0_PLD_IT11 EQU 0x40010a2c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_ORT0 +CYREG_B0_P5_U0_PLD_ORT0 EQU 0x40010a30 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_ORT1 +CYREG_B0_P5_U0_PLD_ORT1 EQU 0x40010a32 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_ORT2 +CYREG_B0_P5_U0_PLD_ORT2 EQU 0x40010a34 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_ORT3 +CYREG_B0_P5_U0_PLD_ORT3 EQU 0x40010a36 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_MC_CFG_CEN_CONST +CYREG_B0_P5_U0_MC_CFG_CEN_CONST EQU 0x40010a38 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_MC_CFG_XORFB +CYREG_B0_P5_U0_MC_CFG_XORFB EQU 0x40010a3a + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_MC_CFG_SET_RESET +CYREG_B0_P5_U0_MC_CFG_SET_RESET EQU 0x40010a3c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_MC_CFG_BYPASS +CYREG_B0_P5_U0_MC_CFG_BYPASS EQU 0x40010a3e + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG0 +CYREG_B0_P5_U0_CFG0 EQU 0x40010a40 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG1 +CYREG_B0_P5_U0_CFG1 EQU 0x40010a41 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG2 +CYREG_B0_P5_U0_CFG2 EQU 0x40010a42 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG3 +CYREG_B0_P5_U0_CFG3 EQU 0x40010a43 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG4 +CYREG_B0_P5_U0_CFG4 EQU 0x40010a44 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG5 +CYREG_B0_P5_U0_CFG5 EQU 0x40010a45 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG6 +CYREG_B0_P5_U0_CFG6 EQU 0x40010a46 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG7 +CYREG_B0_P5_U0_CFG7 EQU 0x40010a47 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG8 +CYREG_B0_P5_U0_CFG8 EQU 0x40010a48 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG9 +CYREG_B0_P5_U0_CFG9 EQU 0x40010a49 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG10 +CYREG_B0_P5_U0_CFG10 EQU 0x40010a4a + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG11 +CYREG_B0_P5_U0_CFG11 EQU 0x40010a4b + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG12 +CYREG_B0_P5_U0_CFG12 EQU 0x40010a4c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG13 +CYREG_B0_P5_U0_CFG13 EQU 0x40010a4d + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG14 +CYREG_B0_P5_U0_CFG14 EQU 0x40010a4e + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG15 +CYREG_B0_P5_U0_CFG15 EQU 0x40010a4f + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG16 +CYREG_B0_P5_U0_CFG16 EQU 0x40010a50 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG17 +CYREG_B0_P5_U0_CFG17 EQU 0x40010a51 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG18 +CYREG_B0_P5_U0_CFG18 EQU 0x40010a52 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG19 +CYREG_B0_P5_U0_CFG19 EQU 0x40010a53 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG20 +CYREG_B0_P5_U0_CFG20 EQU 0x40010a54 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG21 +CYREG_B0_P5_U0_CFG21 EQU 0x40010a55 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG22 +CYREG_B0_P5_U0_CFG22 EQU 0x40010a56 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG23 +CYREG_B0_P5_U0_CFG23 EQU 0x40010a57 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG24 +CYREG_B0_P5_U0_CFG24 EQU 0x40010a58 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG25 +CYREG_B0_P5_U0_CFG25 EQU 0x40010a59 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG26 +CYREG_B0_P5_U0_CFG26 EQU 0x40010a5a + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG27 +CYREG_B0_P5_U0_CFG27 EQU 0x40010a5b + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG28 +CYREG_B0_P5_U0_CFG28 EQU 0x40010a5c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG29 +CYREG_B0_P5_U0_CFG29 EQU 0x40010a5d + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG30 +CYREG_B0_P5_U0_CFG30 EQU 0x40010a5e + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG31 +CYREG_B0_P5_U0_CFG31 EQU 0x40010a5f + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG0 +CYREG_B0_P5_U0_DCFG0 EQU 0x40010a60 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG1 +CYREG_B0_P5_U0_DCFG1 EQU 0x40010a62 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG2 +CYREG_B0_P5_U0_DCFG2 EQU 0x40010a64 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG3 +CYREG_B0_P5_U0_DCFG3 EQU 0x40010a66 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG4 +CYREG_B0_P5_U0_DCFG4 EQU 0x40010a68 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG5 +CYREG_B0_P5_U0_DCFG5 EQU 0x40010a6a + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG6 +CYREG_B0_P5_U0_DCFG6 EQU 0x40010a6c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG7 +CYREG_B0_P5_U0_DCFG7 EQU 0x40010a6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_BASE +CYDEV_UCFG_B0_P5_U1_BASE EQU 0x40010a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_SIZE +CYDEV_UCFG_B0_P5_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT0 +CYREG_B0_P5_U1_PLD_IT0 EQU 0x40010a80 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT1 +CYREG_B0_P5_U1_PLD_IT1 EQU 0x40010a84 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT2 +CYREG_B0_P5_U1_PLD_IT2 EQU 0x40010a88 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT3 +CYREG_B0_P5_U1_PLD_IT3 EQU 0x40010a8c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT4 +CYREG_B0_P5_U1_PLD_IT4 EQU 0x40010a90 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT5 +CYREG_B0_P5_U1_PLD_IT5 EQU 0x40010a94 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT6 +CYREG_B0_P5_U1_PLD_IT6 EQU 0x40010a98 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT7 +CYREG_B0_P5_U1_PLD_IT7 EQU 0x40010a9c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT8 +CYREG_B0_P5_U1_PLD_IT8 EQU 0x40010aa0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT9 +CYREG_B0_P5_U1_PLD_IT9 EQU 0x40010aa4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT10 +CYREG_B0_P5_U1_PLD_IT10 EQU 0x40010aa8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT11 +CYREG_B0_P5_U1_PLD_IT11 EQU 0x40010aac + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_ORT0 +CYREG_B0_P5_U1_PLD_ORT0 EQU 0x40010ab0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_ORT1 +CYREG_B0_P5_U1_PLD_ORT1 EQU 0x40010ab2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_ORT2 +CYREG_B0_P5_U1_PLD_ORT2 EQU 0x40010ab4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_ORT3 +CYREG_B0_P5_U1_PLD_ORT3 EQU 0x40010ab6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_MC_CFG_CEN_CONST +CYREG_B0_P5_U1_MC_CFG_CEN_CONST EQU 0x40010ab8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_MC_CFG_XORFB +CYREG_B0_P5_U1_MC_CFG_XORFB EQU 0x40010aba + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_MC_CFG_SET_RESET +CYREG_B0_P5_U1_MC_CFG_SET_RESET EQU 0x40010abc + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_MC_CFG_BYPASS +CYREG_B0_P5_U1_MC_CFG_BYPASS EQU 0x40010abe + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG0 +CYREG_B0_P5_U1_CFG0 EQU 0x40010ac0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG1 +CYREG_B0_P5_U1_CFG1 EQU 0x40010ac1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG2 +CYREG_B0_P5_U1_CFG2 EQU 0x40010ac2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG3 +CYREG_B0_P5_U1_CFG3 EQU 0x40010ac3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG4 +CYREG_B0_P5_U1_CFG4 EQU 0x40010ac4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG5 +CYREG_B0_P5_U1_CFG5 EQU 0x40010ac5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG6 +CYREG_B0_P5_U1_CFG6 EQU 0x40010ac6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG7 +CYREG_B0_P5_U1_CFG7 EQU 0x40010ac7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG8 +CYREG_B0_P5_U1_CFG8 EQU 0x40010ac8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG9 +CYREG_B0_P5_U1_CFG9 EQU 0x40010ac9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG10 +CYREG_B0_P5_U1_CFG10 EQU 0x40010aca + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG11 +CYREG_B0_P5_U1_CFG11 EQU 0x40010acb + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG12 +CYREG_B0_P5_U1_CFG12 EQU 0x40010acc + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG13 +CYREG_B0_P5_U1_CFG13 EQU 0x40010acd + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG14 +CYREG_B0_P5_U1_CFG14 EQU 0x40010ace + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG15 +CYREG_B0_P5_U1_CFG15 EQU 0x40010acf + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG16 +CYREG_B0_P5_U1_CFG16 EQU 0x40010ad0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG17 +CYREG_B0_P5_U1_CFG17 EQU 0x40010ad1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG18 +CYREG_B0_P5_U1_CFG18 EQU 0x40010ad2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG19 +CYREG_B0_P5_U1_CFG19 EQU 0x40010ad3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG20 +CYREG_B0_P5_U1_CFG20 EQU 0x40010ad4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG21 +CYREG_B0_P5_U1_CFG21 EQU 0x40010ad5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG22 +CYREG_B0_P5_U1_CFG22 EQU 0x40010ad6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG23 +CYREG_B0_P5_U1_CFG23 EQU 0x40010ad7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG24 +CYREG_B0_P5_U1_CFG24 EQU 0x40010ad8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG25 +CYREG_B0_P5_U1_CFG25 EQU 0x40010ad9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG26 +CYREG_B0_P5_U1_CFG26 EQU 0x40010ada + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG27 +CYREG_B0_P5_U1_CFG27 EQU 0x40010adb + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG28 +CYREG_B0_P5_U1_CFG28 EQU 0x40010adc + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG29 +CYREG_B0_P5_U1_CFG29 EQU 0x40010add + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG30 +CYREG_B0_P5_U1_CFG30 EQU 0x40010ade + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG31 +CYREG_B0_P5_U1_CFG31 EQU 0x40010adf + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG0 +CYREG_B0_P5_U1_DCFG0 EQU 0x40010ae0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG1 +CYREG_B0_P5_U1_DCFG1 EQU 0x40010ae2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG2 +CYREG_B0_P5_U1_DCFG2 EQU 0x40010ae4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG3 +CYREG_B0_P5_U1_DCFG3 EQU 0x40010ae6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG4 +CYREG_B0_P5_U1_DCFG4 EQU 0x40010ae8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG5 +CYREG_B0_P5_U1_DCFG5 EQU 0x40010aea + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG6 +CYREG_B0_P5_U1_DCFG6 EQU 0x40010aec + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG7 +CYREG_B0_P5_U1_DCFG7 EQU 0x40010aee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_ROUTE_BASE +CYDEV_UCFG_B0_P5_ROUTE_BASE EQU 0x40010b00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_ROUTE_SIZE +CYDEV_UCFG_B0_P5_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_BASE +CYDEV_UCFG_B0_P6_BASE EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_SIZE +CYDEV_UCFG_B0_P6_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_BASE +CYDEV_UCFG_B0_P6_U0_BASE EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_SIZE +CYDEV_UCFG_B0_P6_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT0 +CYREG_B0_P6_U0_PLD_IT0 EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT1 +CYREG_B0_P6_U0_PLD_IT1 EQU 0x40010c04 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT2 +CYREG_B0_P6_U0_PLD_IT2 EQU 0x40010c08 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT3 +CYREG_B0_P6_U0_PLD_IT3 EQU 0x40010c0c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT4 +CYREG_B0_P6_U0_PLD_IT4 EQU 0x40010c10 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT5 +CYREG_B0_P6_U0_PLD_IT5 EQU 0x40010c14 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT6 +CYREG_B0_P6_U0_PLD_IT6 EQU 0x40010c18 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT7 +CYREG_B0_P6_U0_PLD_IT7 EQU 0x40010c1c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT8 +CYREG_B0_P6_U0_PLD_IT8 EQU 0x40010c20 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT9 +CYREG_B0_P6_U0_PLD_IT9 EQU 0x40010c24 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT10 +CYREG_B0_P6_U0_PLD_IT10 EQU 0x40010c28 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT11 +CYREG_B0_P6_U0_PLD_IT11 EQU 0x40010c2c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_ORT0 +CYREG_B0_P6_U0_PLD_ORT0 EQU 0x40010c30 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_ORT1 +CYREG_B0_P6_U0_PLD_ORT1 EQU 0x40010c32 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_ORT2 +CYREG_B0_P6_U0_PLD_ORT2 EQU 0x40010c34 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_ORT3 +CYREG_B0_P6_U0_PLD_ORT3 EQU 0x40010c36 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_MC_CFG_CEN_CONST +CYREG_B0_P6_U0_MC_CFG_CEN_CONST EQU 0x40010c38 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_MC_CFG_XORFB +CYREG_B0_P6_U0_MC_CFG_XORFB EQU 0x40010c3a + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_MC_CFG_SET_RESET +CYREG_B0_P6_U0_MC_CFG_SET_RESET EQU 0x40010c3c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_MC_CFG_BYPASS +CYREG_B0_P6_U0_MC_CFG_BYPASS EQU 0x40010c3e + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG0 +CYREG_B0_P6_U0_CFG0 EQU 0x40010c40 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG1 +CYREG_B0_P6_U0_CFG1 EQU 0x40010c41 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG2 +CYREG_B0_P6_U0_CFG2 EQU 0x40010c42 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG3 +CYREG_B0_P6_U0_CFG3 EQU 0x40010c43 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG4 +CYREG_B0_P6_U0_CFG4 EQU 0x40010c44 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG5 +CYREG_B0_P6_U0_CFG5 EQU 0x40010c45 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG6 +CYREG_B0_P6_U0_CFG6 EQU 0x40010c46 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG7 +CYREG_B0_P6_U0_CFG7 EQU 0x40010c47 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG8 +CYREG_B0_P6_U0_CFG8 EQU 0x40010c48 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG9 +CYREG_B0_P6_U0_CFG9 EQU 0x40010c49 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG10 +CYREG_B0_P6_U0_CFG10 EQU 0x40010c4a + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG11 +CYREG_B0_P6_U0_CFG11 EQU 0x40010c4b + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG12 +CYREG_B0_P6_U0_CFG12 EQU 0x40010c4c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG13 +CYREG_B0_P6_U0_CFG13 EQU 0x40010c4d + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG14 +CYREG_B0_P6_U0_CFG14 EQU 0x40010c4e + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG15 +CYREG_B0_P6_U0_CFG15 EQU 0x40010c4f + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG16 +CYREG_B0_P6_U0_CFG16 EQU 0x40010c50 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG17 +CYREG_B0_P6_U0_CFG17 EQU 0x40010c51 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG18 +CYREG_B0_P6_U0_CFG18 EQU 0x40010c52 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG19 +CYREG_B0_P6_U0_CFG19 EQU 0x40010c53 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG20 +CYREG_B0_P6_U0_CFG20 EQU 0x40010c54 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG21 +CYREG_B0_P6_U0_CFG21 EQU 0x40010c55 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG22 +CYREG_B0_P6_U0_CFG22 EQU 0x40010c56 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG23 +CYREG_B0_P6_U0_CFG23 EQU 0x40010c57 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG24 +CYREG_B0_P6_U0_CFG24 EQU 0x40010c58 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG25 +CYREG_B0_P6_U0_CFG25 EQU 0x40010c59 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG26 +CYREG_B0_P6_U0_CFG26 EQU 0x40010c5a + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG27 +CYREG_B0_P6_U0_CFG27 EQU 0x40010c5b + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG28 +CYREG_B0_P6_U0_CFG28 EQU 0x40010c5c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG29 +CYREG_B0_P6_U0_CFG29 EQU 0x40010c5d + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG30 +CYREG_B0_P6_U0_CFG30 EQU 0x40010c5e + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG31 +CYREG_B0_P6_U0_CFG31 EQU 0x40010c5f + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG0 +CYREG_B0_P6_U0_DCFG0 EQU 0x40010c60 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG1 +CYREG_B0_P6_U0_DCFG1 EQU 0x40010c62 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG2 +CYREG_B0_P6_U0_DCFG2 EQU 0x40010c64 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG3 +CYREG_B0_P6_U0_DCFG3 EQU 0x40010c66 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG4 +CYREG_B0_P6_U0_DCFG4 EQU 0x40010c68 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG5 +CYREG_B0_P6_U0_DCFG5 EQU 0x40010c6a + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG6 +CYREG_B0_P6_U0_DCFG6 EQU 0x40010c6c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG7 +CYREG_B0_P6_U0_DCFG7 EQU 0x40010c6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_BASE +CYDEV_UCFG_B0_P6_U1_BASE EQU 0x40010c80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_SIZE +CYDEV_UCFG_B0_P6_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT0 +CYREG_B0_P6_U1_PLD_IT0 EQU 0x40010c80 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT1 +CYREG_B0_P6_U1_PLD_IT1 EQU 0x40010c84 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT2 +CYREG_B0_P6_U1_PLD_IT2 EQU 0x40010c88 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT3 +CYREG_B0_P6_U1_PLD_IT3 EQU 0x40010c8c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT4 +CYREG_B0_P6_U1_PLD_IT4 EQU 0x40010c90 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT5 +CYREG_B0_P6_U1_PLD_IT5 EQU 0x40010c94 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT6 +CYREG_B0_P6_U1_PLD_IT6 EQU 0x40010c98 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT7 +CYREG_B0_P6_U1_PLD_IT7 EQU 0x40010c9c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT8 +CYREG_B0_P6_U1_PLD_IT8 EQU 0x40010ca0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT9 +CYREG_B0_P6_U1_PLD_IT9 EQU 0x40010ca4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT10 +CYREG_B0_P6_U1_PLD_IT10 EQU 0x40010ca8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT11 +CYREG_B0_P6_U1_PLD_IT11 EQU 0x40010cac + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_ORT0 +CYREG_B0_P6_U1_PLD_ORT0 EQU 0x40010cb0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_ORT1 +CYREG_B0_P6_U1_PLD_ORT1 EQU 0x40010cb2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_ORT2 +CYREG_B0_P6_U1_PLD_ORT2 EQU 0x40010cb4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_ORT3 +CYREG_B0_P6_U1_PLD_ORT3 EQU 0x40010cb6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_MC_CFG_CEN_CONST +CYREG_B0_P6_U1_MC_CFG_CEN_CONST EQU 0x40010cb8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_MC_CFG_XORFB +CYREG_B0_P6_U1_MC_CFG_XORFB EQU 0x40010cba + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_MC_CFG_SET_RESET +CYREG_B0_P6_U1_MC_CFG_SET_RESET EQU 0x40010cbc + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_MC_CFG_BYPASS +CYREG_B0_P6_U1_MC_CFG_BYPASS EQU 0x40010cbe + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG0 +CYREG_B0_P6_U1_CFG0 EQU 0x40010cc0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG1 +CYREG_B0_P6_U1_CFG1 EQU 0x40010cc1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG2 +CYREG_B0_P6_U1_CFG2 EQU 0x40010cc2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG3 +CYREG_B0_P6_U1_CFG3 EQU 0x40010cc3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG4 +CYREG_B0_P6_U1_CFG4 EQU 0x40010cc4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG5 +CYREG_B0_P6_U1_CFG5 EQU 0x40010cc5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG6 +CYREG_B0_P6_U1_CFG6 EQU 0x40010cc6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG7 +CYREG_B0_P6_U1_CFG7 EQU 0x40010cc7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG8 +CYREG_B0_P6_U1_CFG8 EQU 0x40010cc8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG9 +CYREG_B0_P6_U1_CFG9 EQU 0x40010cc9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG10 +CYREG_B0_P6_U1_CFG10 EQU 0x40010cca + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG11 +CYREG_B0_P6_U1_CFG11 EQU 0x40010ccb + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG12 +CYREG_B0_P6_U1_CFG12 EQU 0x40010ccc + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG13 +CYREG_B0_P6_U1_CFG13 EQU 0x40010ccd + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG14 +CYREG_B0_P6_U1_CFG14 EQU 0x40010cce + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG15 +CYREG_B0_P6_U1_CFG15 EQU 0x40010ccf + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG16 +CYREG_B0_P6_U1_CFG16 EQU 0x40010cd0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG17 +CYREG_B0_P6_U1_CFG17 EQU 0x40010cd1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG18 +CYREG_B0_P6_U1_CFG18 EQU 0x40010cd2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG19 +CYREG_B0_P6_U1_CFG19 EQU 0x40010cd3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG20 +CYREG_B0_P6_U1_CFG20 EQU 0x40010cd4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG21 +CYREG_B0_P6_U1_CFG21 EQU 0x40010cd5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG22 +CYREG_B0_P6_U1_CFG22 EQU 0x40010cd6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG23 +CYREG_B0_P6_U1_CFG23 EQU 0x40010cd7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG24 +CYREG_B0_P6_U1_CFG24 EQU 0x40010cd8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG25 +CYREG_B0_P6_U1_CFG25 EQU 0x40010cd9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG26 +CYREG_B0_P6_U1_CFG26 EQU 0x40010cda + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG27 +CYREG_B0_P6_U1_CFG27 EQU 0x40010cdb + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG28 +CYREG_B0_P6_U1_CFG28 EQU 0x40010cdc + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG29 +CYREG_B0_P6_U1_CFG29 EQU 0x40010cdd + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG30 +CYREG_B0_P6_U1_CFG30 EQU 0x40010cde + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG31 +CYREG_B0_P6_U1_CFG31 EQU 0x40010cdf + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG0 +CYREG_B0_P6_U1_DCFG0 EQU 0x40010ce0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG1 +CYREG_B0_P6_U1_DCFG1 EQU 0x40010ce2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG2 +CYREG_B0_P6_U1_DCFG2 EQU 0x40010ce4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG3 +CYREG_B0_P6_U1_DCFG3 EQU 0x40010ce6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG4 +CYREG_B0_P6_U1_DCFG4 EQU 0x40010ce8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG5 +CYREG_B0_P6_U1_DCFG5 EQU 0x40010cea + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG6 +CYREG_B0_P6_U1_DCFG6 EQU 0x40010cec + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG7 +CYREG_B0_P6_U1_DCFG7 EQU 0x40010cee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_ROUTE_BASE +CYDEV_UCFG_B0_P6_ROUTE_BASE EQU 0x40010d00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_ROUTE_SIZE +CYDEV_UCFG_B0_P6_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_BASE +CYDEV_UCFG_B0_P7_BASE EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_SIZE +CYDEV_UCFG_B0_P7_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_BASE +CYDEV_UCFG_B0_P7_U0_BASE EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_SIZE +CYDEV_UCFG_B0_P7_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT0 +CYREG_B0_P7_U0_PLD_IT0 EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT1 +CYREG_B0_P7_U0_PLD_IT1 EQU 0x40010e04 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT2 +CYREG_B0_P7_U0_PLD_IT2 EQU 0x40010e08 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT3 +CYREG_B0_P7_U0_PLD_IT3 EQU 0x40010e0c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT4 +CYREG_B0_P7_U0_PLD_IT4 EQU 0x40010e10 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT5 +CYREG_B0_P7_U0_PLD_IT5 EQU 0x40010e14 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT6 +CYREG_B0_P7_U0_PLD_IT6 EQU 0x40010e18 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT7 +CYREG_B0_P7_U0_PLD_IT7 EQU 0x40010e1c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT8 +CYREG_B0_P7_U0_PLD_IT8 EQU 0x40010e20 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT9 +CYREG_B0_P7_U0_PLD_IT9 EQU 0x40010e24 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT10 +CYREG_B0_P7_U0_PLD_IT10 EQU 0x40010e28 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT11 +CYREG_B0_P7_U0_PLD_IT11 EQU 0x40010e2c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_ORT0 +CYREG_B0_P7_U0_PLD_ORT0 EQU 0x40010e30 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_ORT1 +CYREG_B0_P7_U0_PLD_ORT1 EQU 0x40010e32 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_ORT2 +CYREG_B0_P7_U0_PLD_ORT2 EQU 0x40010e34 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_ORT3 +CYREG_B0_P7_U0_PLD_ORT3 EQU 0x40010e36 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_MC_CFG_CEN_CONST +CYREG_B0_P7_U0_MC_CFG_CEN_CONST EQU 0x40010e38 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_MC_CFG_XORFB +CYREG_B0_P7_U0_MC_CFG_XORFB EQU 0x40010e3a + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_MC_CFG_SET_RESET +CYREG_B0_P7_U0_MC_CFG_SET_RESET EQU 0x40010e3c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_MC_CFG_BYPASS +CYREG_B0_P7_U0_MC_CFG_BYPASS EQU 0x40010e3e + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG0 +CYREG_B0_P7_U0_CFG0 EQU 0x40010e40 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG1 +CYREG_B0_P7_U0_CFG1 EQU 0x40010e41 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG2 +CYREG_B0_P7_U0_CFG2 EQU 0x40010e42 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG3 +CYREG_B0_P7_U0_CFG3 EQU 0x40010e43 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG4 +CYREG_B0_P7_U0_CFG4 EQU 0x40010e44 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG5 +CYREG_B0_P7_U0_CFG5 EQU 0x40010e45 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG6 +CYREG_B0_P7_U0_CFG6 EQU 0x40010e46 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG7 +CYREG_B0_P7_U0_CFG7 EQU 0x40010e47 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG8 +CYREG_B0_P7_U0_CFG8 EQU 0x40010e48 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG9 +CYREG_B0_P7_U0_CFG9 EQU 0x40010e49 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG10 +CYREG_B0_P7_U0_CFG10 EQU 0x40010e4a + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG11 +CYREG_B0_P7_U0_CFG11 EQU 0x40010e4b + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG12 +CYREG_B0_P7_U0_CFG12 EQU 0x40010e4c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG13 +CYREG_B0_P7_U0_CFG13 EQU 0x40010e4d + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG14 +CYREG_B0_P7_U0_CFG14 EQU 0x40010e4e + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG15 +CYREG_B0_P7_U0_CFG15 EQU 0x40010e4f + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG16 +CYREG_B0_P7_U0_CFG16 EQU 0x40010e50 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG17 +CYREG_B0_P7_U0_CFG17 EQU 0x40010e51 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG18 +CYREG_B0_P7_U0_CFG18 EQU 0x40010e52 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG19 +CYREG_B0_P7_U0_CFG19 EQU 0x40010e53 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG20 +CYREG_B0_P7_U0_CFG20 EQU 0x40010e54 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG21 +CYREG_B0_P7_U0_CFG21 EQU 0x40010e55 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG22 +CYREG_B0_P7_U0_CFG22 EQU 0x40010e56 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG23 +CYREG_B0_P7_U0_CFG23 EQU 0x40010e57 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG24 +CYREG_B0_P7_U0_CFG24 EQU 0x40010e58 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG25 +CYREG_B0_P7_U0_CFG25 EQU 0x40010e59 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG26 +CYREG_B0_P7_U0_CFG26 EQU 0x40010e5a + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG27 +CYREG_B0_P7_U0_CFG27 EQU 0x40010e5b + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG28 +CYREG_B0_P7_U0_CFG28 EQU 0x40010e5c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG29 +CYREG_B0_P7_U0_CFG29 EQU 0x40010e5d + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG30 +CYREG_B0_P7_U0_CFG30 EQU 0x40010e5e + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG31 +CYREG_B0_P7_U0_CFG31 EQU 0x40010e5f + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG0 +CYREG_B0_P7_U0_DCFG0 EQU 0x40010e60 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG1 +CYREG_B0_P7_U0_DCFG1 EQU 0x40010e62 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG2 +CYREG_B0_P7_U0_DCFG2 EQU 0x40010e64 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG3 +CYREG_B0_P7_U0_DCFG3 EQU 0x40010e66 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG4 +CYREG_B0_P7_U0_DCFG4 EQU 0x40010e68 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG5 +CYREG_B0_P7_U0_DCFG5 EQU 0x40010e6a + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG6 +CYREG_B0_P7_U0_DCFG6 EQU 0x40010e6c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG7 +CYREG_B0_P7_U0_DCFG7 EQU 0x40010e6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_BASE +CYDEV_UCFG_B0_P7_U1_BASE EQU 0x40010e80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_SIZE +CYDEV_UCFG_B0_P7_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT0 +CYREG_B0_P7_U1_PLD_IT0 EQU 0x40010e80 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT1 +CYREG_B0_P7_U1_PLD_IT1 EQU 0x40010e84 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT2 +CYREG_B0_P7_U1_PLD_IT2 EQU 0x40010e88 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT3 +CYREG_B0_P7_U1_PLD_IT3 EQU 0x40010e8c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT4 +CYREG_B0_P7_U1_PLD_IT4 EQU 0x40010e90 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT5 +CYREG_B0_P7_U1_PLD_IT5 EQU 0x40010e94 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT6 +CYREG_B0_P7_U1_PLD_IT6 EQU 0x40010e98 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT7 +CYREG_B0_P7_U1_PLD_IT7 EQU 0x40010e9c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT8 +CYREG_B0_P7_U1_PLD_IT8 EQU 0x40010ea0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT9 +CYREG_B0_P7_U1_PLD_IT9 EQU 0x40010ea4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT10 +CYREG_B0_P7_U1_PLD_IT10 EQU 0x40010ea8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT11 +CYREG_B0_P7_U1_PLD_IT11 EQU 0x40010eac + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_ORT0 +CYREG_B0_P7_U1_PLD_ORT0 EQU 0x40010eb0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_ORT1 +CYREG_B0_P7_U1_PLD_ORT1 EQU 0x40010eb2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_ORT2 +CYREG_B0_P7_U1_PLD_ORT2 EQU 0x40010eb4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_ORT3 +CYREG_B0_P7_U1_PLD_ORT3 EQU 0x40010eb6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_MC_CFG_CEN_CONST +CYREG_B0_P7_U1_MC_CFG_CEN_CONST EQU 0x40010eb8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_MC_CFG_XORFB +CYREG_B0_P7_U1_MC_CFG_XORFB EQU 0x40010eba + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_MC_CFG_SET_RESET +CYREG_B0_P7_U1_MC_CFG_SET_RESET EQU 0x40010ebc + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_MC_CFG_BYPASS +CYREG_B0_P7_U1_MC_CFG_BYPASS EQU 0x40010ebe + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG0 +CYREG_B0_P7_U1_CFG0 EQU 0x40010ec0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG1 +CYREG_B0_P7_U1_CFG1 EQU 0x40010ec1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG2 +CYREG_B0_P7_U1_CFG2 EQU 0x40010ec2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG3 +CYREG_B0_P7_U1_CFG3 EQU 0x40010ec3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG4 +CYREG_B0_P7_U1_CFG4 EQU 0x40010ec4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG5 +CYREG_B0_P7_U1_CFG5 EQU 0x40010ec5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG6 +CYREG_B0_P7_U1_CFG6 EQU 0x40010ec6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG7 +CYREG_B0_P7_U1_CFG7 EQU 0x40010ec7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG8 +CYREG_B0_P7_U1_CFG8 EQU 0x40010ec8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG9 +CYREG_B0_P7_U1_CFG9 EQU 0x40010ec9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG10 +CYREG_B0_P7_U1_CFG10 EQU 0x40010eca + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG11 +CYREG_B0_P7_U1_CFG11 EQU 0x40010ecb + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG12 +CYREG_B0_P7_U1_CFG12 EQU 0x40010ecc + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG13 +CYREG_B0_P7_U1_CFG13 EQU 0x40010ecd + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG14 +CYREG_B0_P7_U1_CFG14 EQU 0x40010ece + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG15 +CYREG_B0_P7_U1_CFG15 EQU 0x40010ecf + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG16 +CYREG_B0_P7_U1_CFG16 EQU 0x40010ed0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG17 +CYREG_B0_P7_U1_CFG17 EQU 0x40010ed1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG18 +CYREG_B0_P7_U1_CFG18 EQU 0x40010ed2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG19 +CYREG_B0_P7_U1_CFG19 EQU 0x40010ed3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG20 +CYREG_B0_P7_U1_CFG20 EQU 0x40010ed4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG21 +CYREG_B0_P7_U1_CFG21 EQU 0x40010ed5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG22 +CYREG_B0_P7_U1_CFG22 EQU 0x40010ed6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG23 +CYREG_B0_P7_U1_CFG23 EQU 0x40010ed7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG24 +CYREG_B0_P7_U1_CFG24 EQU 0x40010ed8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG25 +CYREG_B0_P7_U1_CFG25 EQU 0x40010ed9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG26 +CYREG_B0_P7_U1_CFG26 EQU 0x40010eda + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG27 +CYREG_B0_P7_U1_CFG27 EQU 0x40010edb + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG28 +CYREG_B0_P7_U1_CFG28 EQU 0x40010edc + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG29 +CYREG_B0_P7_U1_CFG29 EQU 0x40010edd + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG30 +CYREG_B0_P7_U1_CFG30 EQU 0x40010ede + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG31 +CYREG_B0_P7_U1_CFG31 EQU 0x40010edf + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG0 +CYREG_B0_P7_U1_DCFG0 EQU 0x40010ee0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG1 +CYREG_B0_P7_U1_DCFG1 EQU 0x40010ee2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG2 +CYREG_B0_P7_U1_DCFG2 EQU 0x40010ee4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG3 +CYREG_B0_P7_U1_DCFG3 EQU 0x40010ee6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG4 +CYREG_B0_P7_U1_DCFG4 EQU 0x40010ee8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG5 +CYREG_B0_P7_U1_DCFG5 EQU 0x40010eea + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG6 +CYREG_B0_P7_U1_DCFG6 EQU 0x40010eec + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG7 +CYREG_B0_P7_U1_DCFG7 EQU 0x40010eee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_ROUTE_BASE +CYDEV_UCFG_B0_P7_ROUTE_BASE EQU 0x40010f00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_ROUTE_SIZE +CYDEV_UCFG_B0_P7_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_BASE +CYDEV_UCFG_B1_BASE EQU 0x40011000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_SIZE +CYDEV_UCFG_B1_SIZE EQU 0x00000fef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_BASE +CYDEV_UCFG_B1_P2_BASE EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_SIZE +CYDEV_UCFG_B1_P2_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_BASE +CYDEV_UCFG_B1_P2_U0_BASE EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_SIZE +CYDEV_UCFG_B1_P2_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT0 +CYREG_B1_P2_U0_PLD_IT0 EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT1 +CYREG_B1_P2_U0_PLD_IT1 EQU 0x40011404 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT2 +CYREG_B1_P2_U0_PLD_IT2 EQU 0x40011408 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT3 +CYREG_B1_P2_U0_PLD_IT3 EQU 0x4001140c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT4 +CYREG_B1_P2_U0_PLD_IT4 EQU 0x40011410 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT5 +CYREG_B1_P2_U0_PLD_IT5 EQU 0x40011414 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT6 +CYREG_B1_P2_U0_PLD_IT6 EQU 0x40011418 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT7 +CYREG_B1_P2_U0_PLD_IT7 EQU 0x4001141c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT8 +CYREG_B1_P2_U0_PLD_IT8 EQU 0x40011420 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT9 +CYREG_B1_P2_U0_PLD_IT9 EQU 0x40011424 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT10 +CYREG_B1_P2_U0_PLD_IT10 EQU 0x40011428 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT11 +CYREG_B1_P2_U0_PLD_IT11 EQU 0x4001142c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_ORT0 +CYREG_B1_P2_U0_PLD_ORT0 EQU 0x40011430 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_ORT1 +CYREG_B1_P2_U0_PLD_ORT1 EQU 0x40011432 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_ORT2 +CYREG_B1_P2_U0_PLD_ORT2 EQU 0x40011434 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_ORT3 +CYREG_B1_P2_U0_PLD_ORT3 EQU 0x40011436 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_MC_CFG_CEN_CONST +CYREG_B1_P2_U0_MC_CFG_CEN_CONST EQU 0x40011438 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_MC_CFG_XORFB +CYREG_B1_P2_U0_MC_CFG_XORFB EQU 0x4001143a + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_MC_CFG_SET_RESET +CYREG_B1_P2_U0_MC_CFG_SET_RESET EQU 0x4001143c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_MC_CFG_BYPASS +CYREG_B1_P2_U0_MC_CFG_BYPASS EQU 0x4001143e + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG0 +CYREG_B1_P2_U0_CFG0 EQU 0x40011440 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG1 +CYREG_B1_P2_U0_CFG1 EQU 0x40011441 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG2 +CYREG_B1_P2_U0_CFG2 EQU 0x40011442 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG3 +CYREG_B1_P2_U0_CFG3 EQU 0x40011443 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG4 +CYREG_B1_P2_U0_CFG4 EQU 0x40011444 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG5 +CYREG_B1_P2_U0_CFG5 EQU 0x40011445 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG6 +CYREG_B1_P2_U0_CFG6 EQU 0x40011446 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG7 +CYREG_B1_P2_U0_CFG7 EQU 0x40011447 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG8 +CYREG_B1_P2_U0_CFG8 EQU 0x40011448 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG9 +CYREG_B1_P2_U0_CFG9 EQU 0x40011449 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG10 +CYREG_B1_P2_U0_CFG10 EQU 0x4001144a + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG11 +CYREG_B1_P2_U0_CFG11 EQU 0x4001144b + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG12 +CYREG_B1_P2_U0_CFG12 EQU 0x4001144c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG13 +CYREG_B1_P2_U0_CFG13 EQU 0x4001144d + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG14 +CYREG_B1_P2_U0_CFG14 EQU 0x4001144e + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG15 +CYREG_B1_P2_U0_CFG15 EQU 0x4001144f + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG16 +CYREG_B1_P2_U0_CFG16 EQU 0x40011450 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG17 +CYREG_B1_P2_U0_CFG17 EQU 0x40011451 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG18 +CYREG_B1_P2_U0_CFG18 EQU 0x40011452 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG19 +CYREG_B1_P2_U0_CFG19 EQU 0x40011453 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG20 +CYREG_B1_P2_U0_CFG20 EQU 0x40011454 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG21 +CYREG_B1_P2_U0_CFG21 EQU 0x40011455 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG22 +CYREG_B1_P2_U0_CFG22 EQU 0x40011456 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG23 +CYREG_B1_P2_U0_CFG23 EQU 0x40011457 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG24 +CYREG_B1_P2_U0_CFG24 EQU 0x40011458 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG25 +CYREG_B1_P2_U0_CFG25 EQU 0x40011459 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG26 +CYREG_B1_P2_U0_CFG26 EQU 0x4001145a + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG27 +CYREG_B1_P2_U0_CFG27 EQU 0x4001145b + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG28 +CYREG_B1_P2_U0_CFG28 EQU 0x4001145c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG29 +CYREG_B1_P2_U0_CFG29 EQU 0x4001145d + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG30 +CYREG_B1_P2_U0_CFG30 EQU 0x4001145e + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG31 +CYREG_B1_P2_U0_CFG31 EQU 0x4001145f + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG0 +CYREG_B1_P2_U0_DCFG0 EQU 0x40011460 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG1 +CYREG_B1_P2_U0_DCFG1 EQU 0x40011462 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG2 +CYREG_B1_P2_U0_DCFG2 EQU 0x40011464 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG3 +CYREG_B1_P2_U0_DCFG3 EQU 0x40011466 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG4 +CYREG_B1_P2_U0_DCFG4 EQU 0x40011468 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG5 +CYREG_B1_P2_U0_DCFG5 EQU 0x4001146a + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG6 +CYREG_B1_P2_U0_DCFG6 EQU 0x4001146c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG7 +CYREG_B1_P2_U0_DCFG7 EQU 0x4001146e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_BASE +CYDEV_UCFG_B1_P2_U1_BASE EQU 0x40011480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_SIZE +CYDEV_UCFG_B1_P2_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT0 +CYREG_B1_P2_U1_PLD_IT0 EQU 0x40011480 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT1 +CYREG_B1_P2_U1_PLD_IT1 EQU 0x40011484 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT2 +CYREG_B1_P2_U1_PLD_IT2 EQU 0x40011488 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT3 +CYREG_B1_P2_U1_PLD_IT3 EQU 0x4001148c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT4 +CYREG_B1_P2_U1_PLD_IT4 EQU 0x40011490 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT5 +CYREG_B1_P2_U1_PLD_IT5 EQU 0x40011494 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT6 +CYREG_B1_P2_U1_PLD_IT6 EQU 0x40011498 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT7 +CYREG_B1_P2_U1_PLD_IT7 EQU 0x4001149c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT8 +CYREG_B1_P2_U1_PLD_IT8 EQU 0x400114a0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT9 +CYREG_B1_P2_U1_PLD_IT9 EQU 0x400114a4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT10 +CYREG_B1_P2_U1_PLD_IT10 EQU 0x400114a8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT11 +CYREG_B1_P2_U1_PLD_IT11 EQU 0x400114ac + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_ORT0 +CYREG_B1_P2_U1_PLD_ORT0 EQU 0x400114b0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_ORT1 +CYREG_B1_P2_U1_PLD_ORT1 EQU 0x400114b2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_ORT2 +CYREG_B1_P2_U1_PLD_ORT2 EQU 0x400114b4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_ORT3 +CYREG_B1_P2_U1_PLD_ORT3 EQU 0x400114b6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_MC_CFG_CEN_CONST +CYREG_B1_P2_U1_MC_CFG_CEN_CONST EQU 0x400114b8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_MC_CFG_XORFB +CYREG_B1_P2_U1_MC_CFG_XORFB EQU 0x400114ba + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_MC_CFG_SET_RESET +CYREG_B1_P2_U1_MC_CFG_SET_RESET EQU 0x400114bc + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_MC_CFG_BYPASS +CYREG_B1_P2_U1_MC_CFG_BYPASS EQU 0x400114be + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG0 +CYREG_B1_P2_U1_CFG0 EQU 0x400114c0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG1 +CYREG_B1_P2_U1_CFG1 EQU 0x400114c1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG2 +CYREG_B1_P2_U1_CFG2 EQU 0x400114c2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG3 +CYREG_B1_P2_U1_CFG3 EQU 0x400114c3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG4 +CYREG_B1_P2_U1_CFG4 EQU 0x400114c4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG5 +CYREG_B1_P2_U1_CFG5 EQU 0x400114c5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG6 +CYREG_B1_P2_U1_CFG6 EQU 0x400114c6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG7 +CYREG_B1_P2_U1_CFG7 EQU 0x400114c7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG8 +CYREG_B1_P2_U1_CFG8 EQU 0x400114c8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG9 +CYREG_B1_P2_U1_CFG9 EQU 0x400114c9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG10 +CYREG_B1_P2_U1_CFG10 EQU 0x400114ca + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG11 +CYREG_B1_P2_U1_CFG11 EQU 0x400114cb + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG12 +CYREG_B1_P2_U1_CFG12 EQU 0x400114cc + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG13 +CYREG_B1_P2_U1_CFG13 EQU 0x400114cd + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG14 +CYREG_B1_P2_U1_CFG14 EQU 0x400114ce + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG15 +CYREG_B1_P2_U1_CFG15 EQU 0x400114cf + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG16 +CYREG_B1_P2_U1_CFG16 EQU 0x400114d0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG17 +CYREG_B1_P2_U1_CFG17 EQU 0x400114d1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG18 +CYREG_B1_P2_U1_CFG18 EQU 0x400114d2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG19 +CYREG_B1_P2_U1_CFG19 EQU 0x400114d3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG20 +CYREG_B1_P2_U1_CFG20 EQU 0x400114d4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG21 +CYREG_B1_P2_U1_CFG21 EQU 0x400114d5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG22 +CYREG_B1_P2_U1_CFG22 EQU 0x400114d6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG23 +CYREG_B1_P2_U1_CFG23 EQU 0x400114d7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG24 +CYREG_B1_P2_U1_CFG24 EQU 0x400114d8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG25 +CYREG_B1_P2_U1_CFG25 EQU 0x400114d9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG26 +CYREG_B1_P2_U1_CFG26 EQU 0x400114da + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG27 +CYREG_B1_P2_U1_CFG27 EQU 0x400114db + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG28 +CYREG_B1_P2_U1_CFG28 EQU 0x400114dc + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG29 +CYREG_B1_P2_U1_CFG29 EQU 0x400114dd + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG30 +CYREG_B1_P2_U1_CFG30 EQU 0x400114de + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG31 +CYREG_B1_P2_U1_CFG31 EQU 0x400114df + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG0 +CYREG_B1_P2_U1_DCFG0 EQU 0x400114e0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG1 +CYREG_B1_P2_U1_DCFG1 EQU 0x400114e2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG2 +CYREG_B1_P2_U1_DCFG2 EQU 0x400114e4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG3 +CYREG_B1_P2_U1_DCFG3 EQU 0x400114e6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG4 +CYREG_B1_P2_U1_DCFG4 EQU 0x400114e8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG5 +CYREG_B1_P2_U1_DCFG5 EQU 0x400114ea + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG6 +CYREG_B1_P2_U1_DCFG6 EQU 0x400114ec + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG7 +CYREG_B1_P2_U1_DCFG7 EQU 0x400114ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_ROUTE_BASE +CYDEV_UCFG_B1_P2_ROUTE_BASE EQU 0x40011500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_ROUTE_SIZE +CYDEV_UCFG_B1_P2_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_BASE +CYDEV_UCFG_B1_P3_BASE EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_SIZE +CYDEV_UCFG_B1_P3_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_BASE +CYDEV_UCFG_B1_P3_U0_BASE EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_SIZE +CYDEV_UCFG_B1_P3_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT0 +CYREG_B1_P3_U0_PLD_IT0 EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT1 +CYREG_B1_P3_U0_PLD_IT1 EQU 0x40011604 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT2 +CYREG_B1_P3_U0_PLD_IT2 EQU 0x40011608 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT3 +CYREG_B1_P3_U0_PLD_IT3 EQU 0x4001160c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT4 +CYREG_B1_P3_U0_PLD_IT4 EQU 0x40011610 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT5 +CYREG_B1_P3_U0_PLD_IT5 EQU 0x40011614 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT6 +CYREG_B1_P3_U0_PLD_IT6 EQU 0x40011618 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT7 +CYREG_B1_P3_U0_PLD_IT7 EQU 0x4001161c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT8 +CYREG_B1_P3_U0_PLD_IT8 EQU 0x40011620 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT9 +CYREG_B1_P3_U0_PLD_IT9 EQU 0x40011624 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT10 +CYREG_B1_P3_U0_PLD_IT10 EQU 0x40011628 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT11 +CYREG_B1_P3_U0_PLD_IT11 EQU 0x4001162c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_ORT0 +CYREG_B1_P3_U0_PLD_ORT0 EQU 0x40011630 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_ORT1 +CYREG_B1_P3_U0_PLD_ORT1 EQU 0x40011632 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_ORT2 +CYREG_B1_P3_U0_PLD_ORT2 EQU 0x40011634 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_ORT3 +CYREG_B1_P3_U0_PLD_ORT3 EQU 0x40011636 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_MC_CFG_CEN_CONST +CYREG_B1_P3_U0_MC_CFG_CEN_CONST EQU 0x40011638 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_MC_CFG_XORFB +CYREG_B1_P3_U0_MC_CFG_XORFB EQU 0x4001163a + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_MC_CFG_SET_RESET +CYREG_B1_P3_U0_MC_CFG_SET_RESET EQU 0x4001163c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_MC_CFG_BYPASS +CYREG_B1_P3_U0_MC_CFG_BYPASS EQU 0x4001163e + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG0 +CYREG_B1_P3_U0_CFG0 EQU 0x40011640 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG1 +CYREG_B1_P3_U0_CFG1 EQU 0x40011641 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG2 +CYREG_B1_P3_U0_CFG2 EQU 0x40011642 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG3 +CYREG_B1_P3_U0_CFG3 EQU 0x40011643 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG4 +CYREG_B1_P3_U0_CFG4 EQU 0x40011644 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG5 +CYREG_B1_P3_U0_CFG5 EQU 0x40011645 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG6 +CYREG_B1_P3_U0_CFG6 EQU 0x40011646 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG7 +CYREG_B1_P3_U0_CFG7 EQU 0x40011647 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG8 +CYREG_B1_P3_U0_CFG8 EQU 0x40011648 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG9 +CYREG_B1_P3_U0_CFG9 EQU 0x40011649 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG10 +CYREG_B1_P3_U0_CFG10 EQU 0x4001164a + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG11 +CYREG_B1_P3_U0_CFG11 EQU 0x4001164b + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG12 +CYREG_B1_P3_U0_CFG12 EQU 0x4001164c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG13 +CYREG_B1_P3_U0_CFG13 EQU 0x4001164d + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG14 +CYREG_B1_P3_U0_CFG14 EQU 0x4001164e + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG15 +CYREG_B1_P3_U0_CFG15 EQU 0x4001164f + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG16 +CYREG_B1_P3_U0_CFG16 EQU 0x40011650 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG17 +CYREG_B1_P3_U0_CFG17 EQU 0x40011651 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG18 +CYREG_B1_P3_U0_CFG18 EQU 0x40011652 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG19 +CYREG_B1_P3_U0_CFG19 EQU 0x40011653 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG20 +CYREG_B1_P3_U0_CFG20 EQU 0x40011654 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG21 +CYREG_B1_P3_U0_CFG21 EQU 0x40011655 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG22 +CYREG_B1_P3_U0_CFG22 EQU 0x40011656 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG23 +CYREG_B1_P3_U0_CFG23 EQU 0x40011657 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG24 +CYREG_B1_P3_U0_CFG24 EQU 0x40011658 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG25 +CYREG_B1_P3_U0_CFG25 EQU 0x40011659 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG26 +CYREG_B1_P3_U0_CFG26 EQU 0x4001165a + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG27 +CYREG_B1_P3_U0_CFG27 EQU 0x4001165b + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG28 +CYREG_B1_P3_U0_CFG28 EQU 0x4001165c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG29 +CYREG_B1_P3_U0_CFG29 EQU 0x4001165d + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG30 +CYREG_B1_P3_U0_CFG30 EQU 0x4001165e + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG31 +CYREG_B1_P3_U0_CFG31 EQU 0x4001165f + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG0 +CYREG_B1_P3_U0_DCFG0 EQU 0x40011660 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG1 +CYREG_B1_P3_U0_DCFG1 EQU 0x40011662 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG2 +CYREG_B1_P3_U0_DCFG2 EQU 0x40011664 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG3 +CYREG_B1_P3_U0_DCFG3 EQU 0x40011666 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG4 +CYREG_B1_P3_U0_DCFG4 EQU 0x40011668 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG5 +CYREG_B1_P3_U0_DCFG5 EQU 0x4001166a + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG6 +CYREG_B1_P3_U0_DCFG6 EQU 0x4001166c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG7 +CYREG_B1_P3_U0_DCFG7 EQU 0x4001166e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_BASE +CYDEV_UCFG_B1_P3_U1_BASE EQU 0x40011680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_SIZE +CYDEV_UCFG_B1_P3_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT0 +CYREG_B1_P3_U1_PLD_IT0 EQU 0x40011680 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT1 +CYREG_B1_P3_U1_PLD_IT1 EQU 0x40011684 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT2 +CYREG_B1_P3_U1_PLD_IT2 EQU 0x40011688 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT3 +CYREG_B1_P3_U1_PLD_IT3 EQU 0x4001168c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT4 +CYREG_B1_P3_U1_PLD_IT4 EQU 0x40011690 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT5 +CYREG_B1_P3_U1_PLD_IT5 EQU 0x40011694 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT6 +CYREG_B1_P3_U1_PLD_IT6 EQU 0x40011698 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT7 +CYREG_B1_P3_U1_PLD_IT7 EQU 0x4001169c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT8 +CYREG_B1_P3_U1_PLD_IT8 EQU 0x400116a0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT9 +CYREG_B1_P3_U1_PLD_IT9 EQU 0x400116a4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT10 +CYREG_B1_P3_U1_PLD_IT10 EQU 0x400116a8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT11 +CYREG_B1_P3_U1_PLD_IT11 EQU 0x400116ac + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_ORT0 +CYREG_B1_P3_U1_PLD_ORT0 EQU 0x400116b0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_ORT1 +CYREG_B1_P3_U1_PLD_ORT1 EQU 0x400116b2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_ORT2 +CYREG_B1_P3_U1_PLD_ORT2 EQU 0x400116b4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_ORT3 +CYREG_B1_P3_U1_PLD_ORT3 EQU 0x400116b6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_MC_CFG_CEN_CONST +CYREG_B1_P3_U1_MC_CFG_CEN_CONST EQU 0x400116b8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_MC_CFG_XORFB +CYREG_B1_P3_U1_MC_CFG_XORFB EQU 0x400116ba + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_MC_CFG_SET_RESET +CYREG_B1_P3_U1_MC_CFG_SET_RESET EQU 0x400116bc + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_MC_CFG_BYPASS +CYREG_B1_P3_U1_MC_CFG_BYPASS EQU 0x400116be + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG0 +CYREG_B1_P3_U1_CFG0 EQU 0x400116c0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG1 +CYREG_B1_P3_U1_CFG1 EQU 0x400116c1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG2 +CYREG_B1_P3_U1_CFG2 EQU 0x400116c2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG3 +CYREG_B1_P3_U1_CFG3 EQU 0x400116c3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG4 +CYREG_B1_P3_U1_CFG4 EQU 0x400116c4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG5 +CYREG_B1_P3_U1_CFG5 EQU 0x400116c5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG6 +CYREG_B1_P3_U1_CFG6 EQU 0x400116c6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG7 +CYREG_B1_P3_U1_CFG7 EQU 0x400116c7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG8 +CYREG_B1_P3_U1_CFG8 EQU 0x400116c8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG9 +CYREG_B1_P3_U1_CFG9 EQU 0x400116c9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG10 +CYREG_B1_P3_U1_CFG10 EQU 0x400116ca + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG11 +CYREG_B1_P3_U1_CFG11 EQU 0x400116cb + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG12 +CYREG_B1_P3_U1_CFG12 EQU 0x400116cc + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG13 +CYREG_B1_P3_U1_CFG13 EQU 0x400116cd + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG14 +CYREG_B1_P3_U1_CFG14 EQU 0x400116ce + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG15 +CYREG_B1_P3_U1_CFG15 EQU 0x400116cf + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG16 +CYREG_B1_P3_U1_CFG16 EQU 0x400116d0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG17 +CYREG_B1_P3_U1_CFG17 EQU 0x400116d1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG18 +CYREG_B1_P3_U1_CFG18 EQU 0x400116d2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG19 +CYREG_B1_P3_U1_CFG19 EQU 0x400116d3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG20 +CYREG_B1_P3_U1_CFG20 EQU 0x400116d4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG21 +CYREG_B1_P3_U1_CFG21 EQU 0x400116d5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG22 +CYREG_B1_P3_U1_CFG22 EQU 0x400116d6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG23 +CYREG_B1_P3_U1_CFG23 EQU 0x400116d7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG24 +CYREG_B1_P3_U1_CFG24 EQU 0x400116d8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG25 +CYREG_B1_P3_U1_CFG25 EQU 0x400116d9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG26 +CYREG_B1_P3_U1_CFG26 EQU 0x400116da + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG27 +CYREG_B1_P3_U1_CFG27 EQU 0x400116db + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG28 +CYREG_B1_P3_U1_CFG28 EQU 0x400116dc + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG29 +CYREG_B1_P3_U1_CFG29 EQU 0x400116dd + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG30 +CYREG_B1_P3_U1_CFG30 EQU 0x400116de + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG31 +CYREG_B1_P3_U1_CFG31 EQU 0x400116df + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG0 +CYREG_B1_P3_U1_DCFG0 EQU 0x400116e0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG1 +CYREG_B1_P3_U1_DCFG1 EQU 0x400116e2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG2 +CYREG_B1_P3_U1_DCFG2 EQU 0x400116e4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG3 +CYREG_B1_P3_U1_DCFG3 EQU 0x400116e6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG4 +CYREG_B1_P3_U1_DCFG4 EQU 0x400116e8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG5 +CYREG_B1_P3_U1_DCFG5 EQU 0x400116ea + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG6 +CYREG_B1_P3_U1_DCFG6 EQU 0x400116ec + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG7 +CYREG_B1_P3_U1_DCFG7 EQU 0x400116ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_ROUTE_BASE +CYDEV_UCFG_B1_P3_ROUTE_BASE EQU 0x40011700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_ROUTE_SIZE +CYDEV_UCFG_B1_P3_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_BASE +CYDEV_UCFG_B1_P4_BASE EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_SIZE +CYDEV_UCFG_B1_P4_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_BASE +CYDEV_UCFG_B1_P4_U0_BASE EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_SIZE +CYDEV_UCFG_B1_P4_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT0 +CYREG_B1_P4_U0_PLD_IT0 EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT1 +CYREG_B1_P4_U0_PLD_IT1 EQU 0x40011804 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT2 +CYREG_B1_P4_U0_PLD_IT2 EQU 0x40011808 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT3 +CYREG_B1_P4_U0_PLD_IT3 EQU 0x4001180c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT4 +CYREG_B1_P4_U0_PLD_IT4 EQU 0x40011810 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT5 +CYREG_B1_P4_U0_PLD_IT5 EQU 0x40011814 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT6 +CYREG_B1_P4_U0_PLD_IT6 EQU 0x40011818 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT7 +CYREG_B1_P4_U0_PLD_IT7 EQU 0x4001181c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT8 +CYREG_B1_P4_U0_PLD_IT8 EQU 0x40011820 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT9 +CYREG_B1_P4_U0_PLD_IT9 EQU 0x40011824 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT10 +CYREG_B1_P4_U0_PLD_IT10 EQU 0x40011828 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT11 +CYREG_B1_P4_U0_PLD_IT11 EQU 0x4001182c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_ORT0 +CYREG_B1_P4_U0_PLD_ORT0 EQU 0x40011830 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_ORT1 +CYREG_B1_P4_U0_PLD_ORT1 EQU 0x40011832 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_ORT2 +CYREG_B1_P4_U0_PLD_ORT2 EQU 0x40011834 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_ORT3 +CYREG_B1_P4_U0_PLD_ORT3 EQU 0x40011836 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_MC_CFG_CEN_CONST +CYREG_B1_P4_U0_MC_CFG_CEN_CONST EQU 0x40011838 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_MC_CFG_XORFB +CYREG_B1_P4_U0_MC_CFG_XORFB EQU 0x4001183a + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_MC_CFG_SET_RESET +CYREG_B1_P4_U0_MC_CFG_SET_RESET EQU 0x4001183c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_MC_CFG_BYPASS +CYREG_B1_P4_U0_MC_CFG_BYPASS EQU 0x4001183e + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG0 +CYREG_B1_P4_U0_CFG0 EQU 0x40011840 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG1 +CYREG_B1_P4_U0_CFG1 EQU 0x40011841 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG2 +CYREG_B1_P4_U0_CFG2 EQU 0x40011842 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG3 +CYREG_B1_P4_U0_CFG3 EQU 0x40011843 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG4 +CYREG_B1_P4_U0_CFG4 EQU 0x40011844 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG5 +CYREG_B1_P4_U0_CFG5 EQU 0x40011845 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG6 +CYREG_B1_P4_U0_CFG6 EQU 0x40011846 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG7 +CYREG_B1_P4_U0_CFG7 EQU 0x40011847 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG8 +CYREG_B1_P4_U0_CFG8 EQU 0x40011848 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG9 +CYREG_B1_P4_U0_CFG9 EQU 0x40011849 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG10 +CYREG_B1_P4_U0_CFG10 EQU 0x4001184a + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG11 +CYREG_B1_P4_U0_CFG11 EQU 0x4001184b + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG12 +CYREG_B1_P4_U0_CFG12 EQU 0x4001184c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG13 +CYREG_B1_P4_U0_CFG13 EQU 0x4001184d + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG14 +CYREG_B1_P4_U0_CFG14 EQU 0x4001184e + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG15 +CYREG_B1_P4_U0_CFG15 EQU 0x4001184f + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG16 +CYREG_B1_P4_U0_CFG16 EQU 0x40011850 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG17 +CYREG_B1_P4_U0_CFG17 EQU 0x40011851 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG18 +CYREG_B1_P4_U0_CFG18 EQU 0x40011852 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG19 +CYREG_B1_P4_U0_CFG19 EQU 0x40011853 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG20 +CYREG_B1_P4_U0_CFG20 EQU 0x40011854 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG21 +CYREG_B1_P4_U0_CFG21 EQU 0x40011855 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG22 +CYREG_B1_P4_U0_CFG22 EQU 0x40011856 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG23 +CYREG_B1_P4_U0_CFG23 EQU 0x40011857 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG24 +CYREG_B1_P4_U0_CFG24 EQU 0x40011858 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG25 +CYREG_B1_P4_U0_CFG25 EQU 0x40011859 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG26 +CYREG_B1_P4_U0_CFG26 EQU 0x4001185a + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG27 +CYREG_B1_P4_U0_CFG27 EQU 0x4001185b + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG28 +CYREG_B1_P4_U0_CFG28 EQU 0x4001185c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG29 +CYREG_B1_P4_U0_CFG29 EQU 0x4001185d + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG30 +CYREG_B1_P4_U0_CFG30 EQU 0x4001185e + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG31 +CYREG_B1_P4_U0_CFG31 EQU 0x4001185f + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG0 +CYREG_B1_P4_U0_DCFG0 EQU 0x40011860 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG1 +CYREG_B1_P4_U0_DCFG1 EQU 0x40011862 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG2 +CYREG_B1_P4_U0_DCFG2 EQU 0x40011864 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG3 +CYREG_B1_P4_U0_DCFG3 EQU 0x40011866 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG4 +CYREG_B1_P4_U0_DCFG4 EQU 0x40011868 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG5 +CYREG_B1_P4_U0_DCFG5 EQU 0x4001186a + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG6 +CYREG_B1_P4_U0_DCFG6 EQU 0x4001186c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG7 +CYREG_B1_P4_U0_DCFG7 EQU 0x4001186e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_BASE +CYDEV_UCFG_B1_P4_U1_BASE EQU 0x40011880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_SIZE +CYDEV_UCFG_B1_P4_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT0 +CYREG_B1_P4_U1_PLD_IT0 EQU 0x40011880 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT1 +CYREG_B1_P4_U1_PLD_IT1 EQU 0x40011884 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT2 +CYREG_B1_P4_U1_PLD_IT2 EQU 0x40011888 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT3 +CYREG_B1_P4_U1_PLD_IT3 EQU 0x4001188c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT4 +CYREG_B1_P4_U1_PLD_IT4 EQU 0x40011890 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT5 +CYREG_B1_P4_U1_PLD_IT5 EQU 0x40011894 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT6 +CYREG_B1_P4_U1_PLD_IT6 EQU 0x40011898 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT7 +CYREG_B1_P4_U1_PLD_IT7 EQU 0x4001189c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT8 +CYREG_B1_P4_U1_PLD_IT8 EQU 0x400118a0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT9 +CYREG_B1_P4_U1_PLD_IT9 EQU 0x400118a4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT10 +CYREG_B1_P4_U1_PLD_IT10 EQU 0x400118a8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT11 +CYREG_B1_P4_U1_PLD_IT11 EQU 0x400118ac + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_ORT0 +CYREG_B1_P4_U1_PLD_ORT0 EQU 0x400118b0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_ORT1 +CYREG_B1_P4_U1_PLD_ORT1 EQU 0x400118b2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_ORT2 +CYREG_B1_P4_U1_PLD_ORT2 EQU 0x400118b4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_ORT3 +CYREG_B1_P4_U1_PLD_ORT3 EQU 0x400118b6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_MC_CFG_CEN_CONST +CYREG_B1_P4_U1_MC_CFG_CEN_CONST EQU 0x400118b8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_MC_CFG_XORFB +CYREG_B1_P4_U1_MC_CFG_XORFB EQU 0x400118ba + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_MC_CFG_SET_RESET +CYREG_B1_P4_U1_MC_CFG_SET_RESET EQU 0x400118bc + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_MC_CFG_BYPASS +CYREG_B1_P4_U1_MC_CFG_BYPASS EQU 0x400118be + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG0 +CYREG_B1_P4_U1_CFG0 EQU 0x400118c0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG1 +CYREG_B1_P4_U1_CFG1 EQU 0x400118c1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG2 +CYREG_B1_P4_U1_CFG2 EQU 0x400118c2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG3 +CYREG_B1_P4_U1_CFG3 EQU 0x400118c3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG4 +CYREG_B1_P4_U1_CFG4 EQU 0x400118c4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG5 +CYREG_B1_P4_U1_CFG5 EQU 0x400118c5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG6 +CYREG_B1_P4_U1_CFG6 EQU 0x400118c6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG7 +CYREG_B1_P4_U1_CFG7 EQU 0x400118c7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG8 +CYREG_B1_P4_U1_CFG8 EQU 0x400118c8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG9 +CYREG_B1_P4_U1_CFG9 EQU 0x400118c9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG10 +CYREG_B1_P4_U1_CFG10 EQU 0x400118ca + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG11 +CYREG_B1_P4_U1_CFG11 EQU 0x400118cb + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG12 +CYREG_B1_P4_U1_CFG12 EQU 0x400118cc + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG13 +CYREG_B1_P4_U1_CFG13 EQU 0x400118cd + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG14 +CYREG_B1_P4_U1_CFG14 EQU 0x400118ce + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG15 +CYREG_B1_P4_U1_CFG15 EQU 0x400118cf + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG16 +CYREG_B1_P4_U1_CFG16 EQU 0x400118d0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG17 +CYREG_B1_P4_U1_CFG17 EQU 0x400118d1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG18 +CYREG_B1_P4_U1_CFG18 EQU 0x400118d2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG19 +CYREG_B1_P4_U1_CFG19 EQU 0x400118d3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG20 +CYREG_B1_P4_U1_CFG20 EQU 0x400118d4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG21 +CYREG_B1_P4_U1_CFG21 EQU 0x400118d5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG22 +CYREG_B1_P4_U1_CFG22 EQU 0x400118d6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG23 +CYREG_B1_P4_U1_CFG23 EQU 0x400118d7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG24 +CYREG_B1_P4_U1_CFG24 EQU 0x400118d8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG25 +CYREG_B1_P4_U1_CFG25 EQU 0x400118d9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG26 +CYREG_B1_P4_U1_CFG26 EQU 0x400118da + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG27 +CYREG_B1_P4_U1_CFG27 EQU 0x400118db + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG28 +CYREG_B1_P4_U1_CFG28 EQU 0x400118dc + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG29 +CYREG_B1_P4_U1_CFG29 EQU 0x400118dd + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG30 +CYREG_B1_P4_U1_CFG30 EQU 0x400118de + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG31 +CYREG_B1_P4_U1_CFG31 EQU 0x400118df + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG0 +CYREG_B1_P4_U1_DCFG0 EQU 0x400118e0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG1 +CYREG_B1_P4_U1_DCFG1 EQU 0x400118e2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG2 +CYREG_B1_P4_U1_DCFG2 EQU 0x400118e4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG3 +CYREG_B1_P4_U1_DCFG3 EQU 0x400118e6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG4 +CYREG_B1_P4_U1_DCFG4 EQU 0x400118e8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG5 +CYREG_B1_P4_U1_DCFG5 EQU 0x400118ea + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG6 +CYREG_B1_P4_U1_DCFG6 EQU 0x400118ec + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG7 +CYREG_B1_P4_U1_DCFG7 EQU 0x400118ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_ROUTE_BASE +CYDEV_UCFG_B1_P4_ROUTE_BASE EQU 0x40011900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_ROUTE_SIZE +CYDEV_UCFG_B1_P4_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_BASE +CYDEV_UCFG_B1_P5_BASE EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_SIZE +CYDEV_UCFG_B1_P5_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_BASE +CYDEV_UCFG_B1_P5_U0_BASE EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_SIZE +CYDEV_UCFG_B1_P5_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT0 +CYREG_B1_P5_U0_PLD_IT0 EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT1 +CYREG_B1_P5_U0_PLD_IT1 EQU 0x40011a04 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT2 +CYREG_B1_P5_U0_PLD_IT2 EQU 0x40011a08 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT3 +CYREG_B1_P5_U0_PLD_IT3 EQU 0x40011a0c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT4 +CYREG_B1_P5_U0_PLD_IT4 EQU 0x40011a10 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT5 +CYREG_B1_P5_U0_PLD_IT5 EQU 0x40011a14 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT6 +CYREG_B1_P5_U0_PLD_IT6 EQU 0x40011a18 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT7 +CYREG_B1_P5_U0_PLD_IT7 EQU 0x40011a1c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT8 +CYREG_B1_P5_U0_PLD_IT8 EQU 0x40011a20 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT9 +CYREG_B1_P5_U0_PLD_IT9 EQU 0x40011a24 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT10 +CYREG_B1_P5_U0_PLD_IT10 EQU 0x40011a28 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT11 +CYREG_B1_P5_U0_PLD_IT11 EQU 0x40011a2c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_ORT0 +CYREG_B1_P5_U0_PLD_ORT0 EQU 0x40011a30 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_ORT1 +CYREG_B1_P5_U0_PLD_ORT1 EQU 0x40011a32 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_ORT2 +CYREG_B1_P5_U0_PLD_ORT2 EQU 0x40011a34 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_ORT3 +CYREG_B1_P5_U0_PLD_ORT3 EQU 0x40011a36 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_MC_CFG_CEN_CONST +CYREG_B1_P5_U0_MC_CFG_CEN_CONST EQU 0x40011a38 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_MC_CFG_XORFB +CYREG_B1_P5_U0_MC_CFG_XORFB EQU 0x40011a3a + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_MC_CFG_SET_RESET +CYREG_B1_P5_U0_MC_CFG_SET_RESET EQU 0x40011a3c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_MC_CFG_BYPASS +CYREG_B1_P5_U0_MC_CFG_BYPASS EQU 0x40011a3e + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG0 +CYREG_B1_P5_U0_CFG0 EQU 0x40011a40 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG1 +CYREG_B1_P5_U0_CFG1 EQU 0x40011a41 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG2 +CYREG_B1_P5_U0_CFG2 EQU 0x40011a42 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG3 +CYREG_B1_P5_U0_CFG3 EQU 0x40011a43 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG4 +CYREG_B1_P5_U0_CFG4 EQU 0x40011a44 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG5 +CYREG_B1_P5_U0_CFG5 EQU 0x40011a45 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG6 +CYREG_B1_P5_U0_CFG6 EQU 0x40011a46 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG7 +CYREG_B1_P5_U0_CFG7 EQU 0x40011a47 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG8 +CYREG_B1_P5_U0_CFG8 EQU 0x40011a48 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG9 +CYREG_B1_P5_U0_CFG9 EQU 0x40011a49 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG10 +CYREG_B1_P5_U0_CFG10 EQU 0x40011a4a + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG11 +CYREG_B1_P5_U0_CFG11 EQU 0x40011a4b + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG12 +CYREG_B1_P5_U0_CFG12 EQU 0x40011a4c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG13 +CYREG_B1_P5_U0_CFG13 EQU 0x40011a4d + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG14 +CYREG_B1_P5_U0_CFG14 EQU 0x40011a4e + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG15 +CYREG_B1_P5_U0_CFG15 EQU 0x40011a4f + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG16 +CYREG_B1_P5_U0_CFG16 EQU 0x40011a50 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG17 +CYREG_B1_P5_U0_CFG17 EQU 0x40011a51 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG18 +CYREG_B1_P5_U0_CFG18 EQU 0x40011a52 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG19 +CYREG_B1_P5_U0_CFG19 EQU 0x40011a53 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG20 +CYREG_B1_P5_U0_CFG20 EQU 0x40011a54 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG21 +CYREG_B1_P5_U0_CFG21 EQU 0x40011a55 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG22 +CYREG_B1_P5_U0_CFG22 EQU 0x40011a56 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG23 +CYREG_B1_P5_U0_CFG23 EQU 0x40011a57 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG24 +CYREG_B1_P5_U0_CFG24 EQU 0x40011a58 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG25 +CYREG_B1_P5_U0_CFG25 EQU 0x40011a59 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG26 +CYREG_B1_P5_U0_CFG26 EQU 0x40011a5a + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG27 +CYREG_B1_P5_U0_CFG27 EQU 0x40011a5b + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG28 +CYREG_B1_P5_U0_CFG28 EQU 0x40011a5c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG29 +CYREG_B1_P5_U0_CFG29 EQU 0x40011a5d + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG30 +CYREG_B1_P5_U0_CFG30 EQU 0x40011a5e + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG31 +CYREG_B1_P5_U0_CFG31 EQU 0x40011a5f + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG0 +CYREG_B1_P5_U0_DCFG0 EQU 0x40011a60 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG1 +CYREG_B1_P5_U0_DCFG1 EQU 0x40011a62 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG2 +CYREG_B1_P5_U0_DCFG2 EQU 0x40011a64 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG3 +CYREG_B1_P5_U0_DCFG3 EQU 0x40011a66 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG4 +CYREG_B1_P5_U0_DCFG4 EQU 0x40011a68 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG5 +CYREG_B1_P5_U0_DCFG5 EQU 0x40011a6a + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG6 +CYREG_B1_P5_U0_DCFG6 EQU 0x40011a6c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG7 +CYREG_B1_P5_U0_DCFG7 EQU 0x40011a6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_BASE +CYDEV_UCFG_B1_P5_U1_BASE EQU 0x40011a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_SIZE +CYDEV_UCFG_B1_P5_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT0 +CYREG_B1_P5_U1_PLD_IT0 EQU 0x40011a80 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT1 +CYREG_B1_P5_U1_PLD_IT1 EQU 0x40011a84 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT2 +CYREG_B1_P5_U1_PLD_IT2 EQU 0x40011a88 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT3 +CYREG_B1_P5_U1_PLD_IT3 EQU 0x40011a8c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT4 +CYREG_B1_P5_U1_PLD_IT4 EQU 0x40011a90 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT5 +CYREG_B1_P5_U1_PLD_IT5 EQU 0x40011a94 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT6 +CYREG_B1_P5_U1_PLD_IT6 EQU 0x40011a98 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT7 +CYREG_B1_P5_U1_PLD_IT7 EQU 0x40011a9c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT8 +CYREG_B1_P5_U1_PLD_IT8 EQU 0x40011aa0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT9 +CYREG_B1_P5_U1_PLD_IT9 EQU 0x40011aa4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT10 +CYREG_B1_P5_U1_PLD_IT10 EQU 0x40011aa8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT11 +CYREG_B1_P5_U1_PLD_IT11 EQU 0x40011aac + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_ORT0 +CYREG_B1_P5_U1_PLD_ORT0 EQU 0x40011ab0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_ORT1 +CYREG_B1_P5_U1_PLD_ORT1 EQU 0x40011ab2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_ORT2 +CYREG_B1_P5_U1_PLD_ORT2 EQU 0x40011ab4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_ORT3 +CYREG_B1_P5_U1_PLD_ORT3 EQU 0x40011ab6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_MC_CFG_CEN_CONST +CYREG_B1_P5_U1_MC_CFG_CEN_CONST EQU 0x40011ab8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_MC_CFG_XORFB +CYREG_B1_P5_U1_MC_CFG_XORFB EQU 0x40011aba + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_MC_CFG_SET_RESET +CYREG_B1_P5_U1_MC_CFG_SET_RESET EQU 0x40011abc + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_MC_CFG_BYPASS +CYREG_B1_P5_U1_MC_CFG_BYPASS EQU 0x40011abe + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG0 +CYREG_B1_P5_U1_CFG0 EQU 0x40011ac0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG1 +CYREG_B1_P5_U1_CFG1 EQU 0x40011ac1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG2 +CYREG_B1_P5_U1_CFG2 EQU 0x40011ac2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG3 +CYREG_B1_P5_U1_CFG3 EQU 0x40011ac3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG4 +CYREG_B1_P5_U1_CFG4 EQU 0x40011ac4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG5 +CYREG_B1_P5_U1_CFG5 EQU 0x40011ac5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG6 +CYREG_B1_P5_U1_CFG6 EQU 0x40011ac6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG7 +CYREG_B1_P5_U1_CFG7 EQU 0x40011ac7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG8 +CYREG_B1_P5_U1_CFG8 EQU 0x40011ac8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG9 +CYREG_B1_P5_U1_CFG9 EQU 0x40011ac9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG10 +CYREG_B1_P5_U1_CFG10 EQU 0x40011aca + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG11 +CYREG_B1_P5_U1_CFG11 EQU 0x40011acb + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG12 +CYREG_B1_P5_U1_CFG12 EQU 0x40011acc + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG13 +CYREG_B1_P5_U1_CFG13 EQU 0x40011acd + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG14 +CYREG_B1_P5_U1_CFG14 EQU 0x40011ace + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG15 +CYREG_B1_P5_U1_CFG15 EQU 0x40011acf + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG16 +CYREG_B1_P5_U1_CFG16 EQU 0x40011ad0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG17 +CYREG_B1_P5_U1_CFG17 EQU 0x40011ad1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG18 +CYREG_B1_P5_U1_CFG18 EQU 0x40011ad2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG19 +CYREG_B1_P5_U1_CFG19 EQU 0x40011ad3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG20 +CYREG_B1_P5_U1_CFG20 EQU 0x40011ad4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG21 +CYREG_B1_P5_U1_CFG21 EQU 0x40011ad5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG22 +CYREG_B1_P5_U1_CFG22 EQU 0x40011ad6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG23 +CYREG_B1_P5_U1_CFG23 EQU 0x40011ad7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG24 +CYREG_B1_P5_U1_CFG24 EQU 0x40011ad8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG25 +CYREG_B1_P5_U1_CFG25 EQU 0x40011ad9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG26 +CYREG_B1_P5_U1_CFG26 EQU 0x40011ada + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG27 +CYREG_B1_P5_U1_CFG27 EQU 0x40011adb + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG28 +CYREG_B1_P5_U1_CFG28 EQU 0x40011adc + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG29 +CYREG_B1_P5_U1_CFG29 EQU 0x40011add + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG30 +CYREG_B1_P5_U1_CFG30 EQU 0x40011ade + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG31 +CYREG_B1_P5_U1_CFG31 EQU 0x40011adf + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG0 +CYREG_B1_P5_U1_DCFG0 EQU 0x40011ae0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG1 +CYREG_B1_P5_U1_DCFG1 EQU 0x40011ae2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG2 +CYREG_B1_P5_U1_DCFG2 EQU 0x40011ae4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG3 +CYREG_B1_P5_U1_DCFG3 EQU 0x40011ae6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG4 +CYREG_B1_P5_U1_DCFG4 EQU 0x40011ae8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG5 +CYREG_B1_P5_U1_DCFG5 EQU 0x40011aea + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG6 +CYREG_B1_P5_U1_DCFG6 EQU 0x40011aec + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG7 +CYREG_B1_P5_U1_DCFG7 EQU 0x40011aee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_ROUTE_BASE +CYDEV_UCFG_B1_P5_ROUTE_BASE EQU 0x40011b00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_ROUTE_SIZE +CYDEV_UCFG_B1_P5_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI0_BASE +CYDEV_UCFG_DSI0_BASE EQU 0x40014000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI0_SIZE +CYDEV_UCFG_DSI0_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI1_BASE +CYDEV_UCFG_DSI1_BASE EQU 0x40014100 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI1_SIZE +CYDEV_UCFG_DSI1_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI2_BASE +CYDEV_UCFG_DSI2_BASE EQU 0x40014200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI2_SIZE +CYDEV_UCFG_DSI2_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI3_BASE +CYDEV_UCFG_DSI3_BASE EQU 0x40014300 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI3_SIZE +CYDEV_UCFG_DSI3_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI4_BASE +CYDEV_UCFG_DSI4_BASE EQU 0x40014400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI4_SIZE +CYDEV_UCFG_DSI4_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI5_BASE +CYDEV_UCFG_DSI5_BASE EQU 0x40014500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI5_SIZE +CYDEV_UCFG_DSI5_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI6_BASE +CYDEV_UCFG_DSI6_BASE EQU 0x40014600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI6_SIZE +CYDEV_UCFG_DSI6_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI7_BASE +CYDEV_UCFG_DSI7_BASE EQU 0x40014700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI7_SIZE +CYDEV_UCFG_DSI7_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI8_BASE +CYDEV_UCFG_DSI8_BASE EQU 0x40014800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI8_SIZE +CYDEV_UCFG_DSI8_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI9_BASE +CYDEV_UCFG_DSI9_BASE EQU 0x40014900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI9_SIZE +CYDEV_UCFG_DSI9_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI12_BASE +CYDEV_UCFG_DSI12_BASE EQU 0x40014c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI12_SIZE +CYDEV_UCFG_DSI12_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI13_BASE +CYDEV_UCFG_DSI13_BASE EQU 0x40014d00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI13_SIZE +CYDEV_UCFG_DSI13_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BASE +CYDEV_UCFG_BCTL0_BASE EQU 0x40015000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_SIZE +CYDEV_UCFG_BCTL0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_MDCLK_EN +CYREG_BCTL0_MDCLK_EN EQU 0x40015000 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_MBCLK_EN +CYREG_BCTL0_MBCLK_EN EQU 0x40015001 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_WAIT_CFG +CYREG_BCTL0_WAIT_CFG EQU 0x40015002 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_BANK_CTL +CYREG_BCTL0_BANK_CTL EQU 0x40015003 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_UDB_TEST_3 +CYREG_BCTL0_UDB_TEST_3 EQU 0x40015007 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_DCLK_EN0 +CYREG_BCTL0_DCLK_EN0 EQU 0x40015008 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_BCLK_EN0 +CYREG_BCTL0_BCLK_EN0 EQU 0x40015009 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_DCLK_EN1 +CYREG_BCTL0_DCLK_EN1 EQU 0x4001500a + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_BCLK_EN1 +CYREG_BCTL0_BCLK_EN1 EQU 0x4001500b + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_DCLK_EN2 +CYREG_BCTL0_DCLK_EN2 EQU 0x4001500c + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_BCLK_EN2 +CYREG_BCTL0_BCLK_EN2 EQU 0x4001500d + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_DCLK_EN3 +CYREG_BCTL0_DCLK_EN3 EQU 0x4001500e + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_BCLK_EN3 +CYREG_BCTL0_BCLK_EN3 EQU 0x4001500f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BASE +CYDEV_UCFG_BCTL1_BASE EQU 0x40015010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_SIZE +CYDEV_UCFG_BCTL1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_MDCLK_EN +CYREG_BCTL1_MDCLK_EN EQU 0x40015010 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_MBCLK_EN +CYREG_BCTL1_MBCLK_EN EQU 0x40015011 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_WAIT_CFG +CYREG_BCTL1_WAIT_CFG EQU 0x40015012 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_BANK_CTL +CYREG_BCTL1_BANK_CTL EQU 0x40015013 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_UDB_TEST_3 +CYREG_BCTL1_UDB_TEST_3 EQU 0x40015017 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_DCLK_EN0 +CYREG_BCTL1_DCLK_EN0 EQU 0x40015018 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_BCLK_EN0 +CYREG_BCTL1_BCLK_EN0 EQU 0x40015019 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_DCLK_EN1 +CYREG_BCTL1_DCLK_EN1 EQU 0x4001501a + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_BCLK_EN1 +CYREG_BCTL1_BCLK_EN1 EQU 0x4001501b + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_DCLK_EN2 +CYREG_BCTL1_DCLK_EN2 EQU 0x4001501c + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_BCLK_EN2 +CYREG_BCTL1_BCLK_EN2 EQU 0x4001501d + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_DCLK_EN3 +CYREG_BCTL1_DCLK_EN3 EQU 0x4001501e + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_BCLK_EN3 +CYREG_BCTL1_BCLK_EN3 EQU 0x4001501f + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_BASE +CYDEV_IDMUX_BASE EQU 0x40015100 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_SIZE +CYDEV_IDMUX_SIZE EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL0 +CYREG_IDMUX_IRQ_CTL0 EQU 0x40015100 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL1 +CYREG_IDMUX_IRQ_CTL1 EQU 0x40015101 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL2 +CYREG_IDMUX_IRQ_CTL2 EQU 0x40015102 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL3 +CYREG_IDMUX_IRQ_CTL3 EQU 0x40015103 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL4 +CYREG_IDMUX_IRQ_CTL4 EQU 0x40015104 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL5 +CYREG_IDMUX_IRQ_CTL5 EQU 0x40015105 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL6 +CYREG_IDMUX_IRQ_CTL6 EQU 0x40015106 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL7 +CYREG_IDMUX_IRQ_CTL7 EQU 0x40015107 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL0 +CYREG_IDMUX_DRQ_CTL0 EQU 0x40015110 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL1 +CYREG_IDMUX_DRQ_CTL1 EQU 0x40015111 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL2 +CYREG_IDMUX_DRQ_CTL2 EQU 0x40015112 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL3 +CYREG_IDMUX_DRQ_CTL3 EQU 0x40015113 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL4 +CYREG_IDMUX_DRQ_CTL4 EQU 0x40015114 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL5 +CYREG_IDMUX_DRQ_CTL5 EQU 0x40015115 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_BASE +CYDEV_CACHERAM_BASE EQU 0x40030000 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_SIZE +CYDEV_CACHERAM_SIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYREG_CACHERAM_DATA_MBASE +CYREG_CACHERAM_DATA_MBASE EQU 0x40030000 + ENDIF + IF :LNOT::DEF:CYREG_CACHERAM_DATA_MSIZE +CYREG_CACHERAM_DATA_MSIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_BASE +CYDEV_SFR_BASE EQU 0x40050100 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_SIZE +CYDEV_SFR_SIZE EQU 0x000000fb + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO0 +CYREG_SFR_GPIO0 EQU 0x40050180 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD0 +CYREG_SFR_GPIRD0 EQU 0x40050189 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO0_SEL +CYREG_SFR_GPIO0_SEL EQU 0x4005018a + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO1 +CYREG_SFR_GPIO1 EQU 0x40050190 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD1 +CYREG_SFR_GPIRD1 EQU 0x40050191 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO2 +CYREG_SFR_GPIO2 EQU 0x40050198 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD2 +CYREG_SFR_GPIRD2 EQU 0x40050199 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO2_SEL +CYREG_SFR_GPIO2_SEL EQU 0x4005019a + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO1_SEL +CYREG_SFR_GPIO1_SEL EQU 0x400501a2 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO3 +CYREG_SFR_GPIO3 EQU 0x400501b0 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD3 +CYREG_SFR_GPIRD3 EQU 0x400501b1 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO3_SEL +CYREG_SFR_GPIO3_SEL EQU 0x400501b2 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO4 +CYREG_SFR_GPIO4 EQU 0x400501c0 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD4 +CYREG_SFR_GPIRD4 EQU 0x400501c1 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO4_SEL +CYREG_SFR_GPIO4_SEL EQU 0x400501c2 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO5 +CYREG_SFR_GPIO5 EQU 0x400501c8 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD5 +CYREG_SFR_GPIRD5 EQU 0x400501c9 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO5_SEL +CYREG_SFR_GPIO5_SEL EQU 0x400501ca + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO6 +CYREG_SFR_GPIO6 EQU 0x400501d8 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD6 +CYREG_SFR_GPIRD6 EQU 0x400501d9 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO6_SEL +CYREG_SFR_GPIO6_SEL EQU 0x400501da + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO12 +CYREG_SFR_GPIO12 EQU 0x400501e8 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD12 +CYREG_SFR_GPIRD12 EQU 0x400501e9 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO12_SEL +CYREG_SFR_GPIO12_SEL EQU 0x400501f2 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO15 +CYREG_SFR_GPIO15 EQU 0x400501f8 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD15 +CYREG_SFR_GPIRD15 EQU 0x400501f9 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO15_SEL +CYREG_SFR_GPIO15_SEL EQU 0x400501fa + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_BASE +CYDEV_P3BA_BASE EQU 0x40050300 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_SIZE +CYDEV_P3BA_SIZE EQU 0x0000002b + ENDIF + IF :LNOT::DEF:CYREG_P3BA_Y_START +CYREG_P3BA_Y_START EQU 0x40050300 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_YROLL +CYREG_P3BA_YROLL EQU 0x40050301 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_YCFG +CYREG_P3BA_YCFG EQU 0x40050302 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_X_START1 +CYREG_P3BA_X_START1 EQU 0x40050303 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_X_START2 +CYREG_P3BA_X_START2 EQU 0x40050304 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_XROLL1 +CYREG_P3BA_XROLL1 EQU 0x40050305 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_XROLL2 +CYREG_P3BA_XROLL2 EQU 0x40050306 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_XINC +CYREG_P3BA_XINC EQU 0x40050307 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_XCFG +CYREG_P3BA_XCFG EQU 0x40050308 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_OFFSETADDR1 +CYREG_P3BA_OFFSETADDR1 EQU 0x40050309 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_OFFSETADDR2 +CYREG_P3BA_OFFSETADDR2 EQU 0x4005030a + ENDIF + IF :LNOT::DEF:CYREG_P3BA_OFFSETADDR3 +CYREG_P3BA_OFFSETADDR3 EQU 0x4005030b + ENDIF + IF :LNOT::DEF:CYREG_P3BA_ABSADDR1 +CYREG_P3BA_ABSADDR1 EQU 0x4005030c + ENDIF + IF :LNOT::DEF:CYREG_P3BA_ABSADDR2 +CYREG_P3BA_ABSADDR2 EQU 0x4005030d + ENDIF + IF :LNOT::DEF:CYREG_P3BA_ABSADDR3 +CYREG_P3BA_ABSADDR3 EQU 0x4005030e + ENDIF + IF :LNOT::DEF:CYREG_P3BA_ABSADDR4 +CYREG_P3BA_ABSADDR4 EQU 0x4005030f + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATCFG1 +CYREG_P3BA_DATCFG1 EQU 0x40050310 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATCFG2 +CYREG_P3BA_DATCFG2 EQU 0x40050311 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_CMP_RSLT1 +CYREG_P3BA_CMP_RSLT1 EQU 0x40050314 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_CMP_RSLT2 +CYREG_P3BA_CMP_RSLT2 EQU 0x40050315 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_CMP_RSLT3 +CYREG_P3BA_CMP_RSLT3 EQU 0x40050316 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_CMP_RSLT4 +CYREG_P3BA_CMP_RSLT4 EQU 0x40050317 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATA_REG1 +CYREG_P3BA_DATA_REG1 EQU 0x40050318 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATA_REG2 +CYREG_P3BA_DATA_REG2 EQU 0x40050319 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATA_REG3 +CYREG_P3BA_DATA_REG3 EQU 0x4005031a + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATA_REG4 +CYREG_P3BA_DATA_REG4 EQU 0x4005031b + ENDIF + IF :LNOT::DEF:CYREG_P3BA_EXP_DATA1 +CYREG_P3BA_EXP_DATA1 EQU 0x4005031c + ENDIF + IF :LNOT::DEF:CYREG_P3BA_EXP_DATA2 +CYREG_P3BA_EXP_DATA2 EQU 0x4005031d + ENDIF + IF :LNOT::DEF:CYREG_P3BA_EXP_DATA3 +CYREG_P3BA_EXP_DATA3 EQU 0x4005031e + ENDIF + IF :LNOT::DEF:CYREG_P3BA_EXP_DATA4 +CYREG_P3BA_EXP_DATA4 EQU 0x4005031f + ENDIF + IF :LNOT::DEF:CYREG_P3BA_MSTR_HRDATA1 +CYREG_P3BA_MSTR_HRDATA1 EQU 0x40050320 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_MSTR_HRDATA2 +CYREG_P3BA_MSTR_HRDATA2 EQU 0x40050321 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_MSTR_HRDATA3 +CYREG_P3BA_MSTR_HRDATA3 EQU 0x40050322 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_MSTR_HRDATA4 +CYREG_P3BA_MSTR_HRDATA4 EQU 0x40050323 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_BIST_EN +CYREG_P3BA_BIST_EN EQU 0x40050324 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_PHUB_MASTER_SSR +CYREG_P3BA_PHUB_MASTER_SSR EQU 0x40050325 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_SEQCFG1 +CYREG_P3BA_SEQCFG1 EQU 0x40050326 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_SEQCFG2 +CYREG_P3BA_SEQCFG2 EQU 0x40050327 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_Y_CURR +CYREG_P3BA_Y_CURR EQU 0x40050328 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_X_CURR1 +CYREG_P3BA_X_CURR1 EQU 0x40050329 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_X_CURR2 +CYREG_P3BA_X_CURR2 EQU 0x4005032a + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_BASE +CYDEV_PANTHER_BASE EQU 0x40080000 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_SIZE +CYDEV_PANTHER_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_STCALIB_CFG +CYREG_PANTHER_STCALIB_CFG EQU 0x40080000 + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_WAITPIPE +CYREG_PANTHER_WAITPIPE EQU 0x40080004 + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_TRACE_CFG +CYREG_PANTHER_TRACE_CFG EQU 0x40080008 + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_DBG_CFG +CYREG_PANTHER_DBG_CFG EQU 0x4008000c + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_CM3_LCKRST_STAT +CYREG_PANTHER_CM3_LCKRST_STAT EQU 0x40080018 + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_DEVICE_ID +CYREG_PANTHER_DEVICE_ID EQU 0x4008001c + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_BASE +CYDEV_FLSECC_BASE EQU 0x48000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_SIZE +CYDEV_FLSECC_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYREG_FLSECC_DATA_MBASE +CYREG_FLSECC_DATA_MBASE EQU 0x48000000 + ENDIF + IF :LNOT::DEF:CYREG_FLSECC_DATA_MSIZE +CYREG_FLSECC_DATA_MSIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_BASE +CYDEV_FLSHID_BASE EQU 0x49000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_SIZE +CYDEV_FLSHID_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_RSVD_MBASE +CYREG_FLSHID_RSVD_MBASE EQU 0x49000000 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_RSVD_MSIZE +CYREG_FLSHID_RSVD_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_MDATA_MBASE +CYREG_FLSHID_CUST_MDATA_MBASE EQU 0x49000080 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_MDATA_MSIZE +CYREG_FLSHID_CUST_MDATA_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_BASE +CYDEV_FLSHID_CUST_TABLES_BASE EQU 0x49000100 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_SIZE +CYDEV_FLSHID_CUST_TABLES_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_Y_LOC +CYREG_FLSHID_CUST_TABLES_Y_LOC EQU 0x49000100 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_X_LOC +CYREG_FLSHID_CUST_TABLES_X_LOC EQU 0x49000101 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_WAFER_NUM +CYREG_FLSHID_CUST_TABLES_WAFER_NUM EQU 0x49000102 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_LOT_LSB +CYREG_FLSHID_CUST_TABLES_LOT_LSB EQU 0x49000103 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_LOT_MSB +CYREG_FLSHID_CUST_TABLES_LOT_MSB EQU 0x49000104 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_WRK_WK +CYREG_FLSHID_CUST_TABLES_WRK_WK EQU 0x49000105 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_FAB_YR +CYREG_FLSHID_CUST_TABLES_FAB_YR EQU 0x49000106 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_MINOR +CYREG_FLSHID_CUST_TABLES_MINOR EQU 0x49000107 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_3MHZ +CYREG_FLSHID_CUST_TABLES_IMO_3MHZ EQU 0x49000108 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_6MHZ +CYREG_FLSHID_CUST_TABLES_IMO_6MHZ EQU 0x49000109 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_12MHZ +CYREG_FLSHID_CUST_TABLES_IMO_12MHZ EQU 0x4900010a + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_24MHZ +CYREG_FLSHID_CUST_TABLES_IMO_24MHZ EQU 0x4900010b + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_67MHZ +CYREG_FLSHID_CUST_TABLES_IMO_67MHZ EQU 0x4900010c + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_80MHZ +CYREG_FLSHID_CUST_TABLES_IMO_80MHZ EQU 0x4900010d + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_92MHZ +CYREG_FLSHID_CUST_TABLES_IMO_92MHZ EQU 0x4900010e + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_USB +CYREG_FLSHID_CUST_TABLES_IMO_USB EQU 0x4900010f + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS +CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS EQU 0x49000110 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS +CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS EQU 0x49000111 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS +CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS EQU 0x49000112 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS +CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS EQU 0x49000113 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS +CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS EQU 0x49000114 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS +CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS EQU 0x49000115 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS +CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS EQU 0x49000116 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS +CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS EQU 0x49000117 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M1 +CYREG_FLSHID_CUST_TABLES_DEC_M1 EQU 0x49000118 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M2 +CYREG_FLSHID_CUST_TABLES_DEC_M2 EQU 0x49000119 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M3 +CYREG_FLSHID_CUST_TABLES_DEC_M3 EQU 0x4900011a + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M4 +CYREG_FLSHID_CUST_TABLES_DEC_M4 EQU 0x4900011b + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M5 +CYREG_FLSHID_CUST_TABLES_DEC_M5 EQU 0x4900011c + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M6 +CYREG_FLSHID_CUST_TABLES_DEC_M6 EQU 0x4900011d + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M7 +CYREG_FLSHID_CUST_TABLES_DEC_M7 EQU 0x4900011e + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M8 +CYREG_FLSHID_CUST_TABLES_DEC_M8 EQU 0x4900011f + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M1 +CYREG_FLSHID_CUST_TABLES_DAC0_M1 EQU 0x49000120 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M2 +CYREG_FLSHID_CUST_TABLES_DAC0_M2 EQU 0x49000121 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M3 +CYREG_FLSHID_CUST_TABLES_DAC0_M3 EQU 0x49000122 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M4 +CYREG_FLSHID_CUST_TABLES_DAC0_M4 EQU 0x49000123 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M5 +CYREG_FLSHID_CUST_TABLES_DAC0_M5 EQU 0x49000124 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M6 +CYREG_FLSHID_CUST_TABLES_DAC0_M6 EQU 0x49000125 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M7 +CYREG_FLSHID_CUST_TABLES_DAC0_M7 EQU 0x49000126 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M8 +CYREG_FLSHID_CUST_TABLES_DAC0_M8 EQU 0x49000127 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M1 +CYREG_FLSHID_CUST_TABLES_DAC2_M1 EQU 0x49000128 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M2 +CYREG_FLSHID_CUST_TABLES_DAC2_M2 EQU 0x49000129 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M3 +CYREG_FLSHID_CUST_TABLES_DAC2_M3 EQU 0x4900012a + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M4 +CYREG_FLSHID_CUST_TABLES_DAC2_M4 EQU 0x4900012b + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M5 +CYREG_FLSHID_CUST_TABLES_DAC2_M5 EQU 0x4900012c + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M6 +CYREG_FLSHID_CUST_TABLES_DAC2_M6 EQU 0x4900012d + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M7 +CYREG_FLSHID_CUST_TABLES_DAC2_M7 EQU 0x4900012e + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M8 +CYREG_FLSHID_CUST_TABLES_DAC2_M8 EQU 0x4900012f + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M1 +CYREG_FLSHID_CUST_TABLES_DAC1_M1 EQU 0x49000130 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M2 +CYREG_FLSHID_CUST_TABLES_DAC1_M2 EQU 0x49000131 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M3 +CYREG_FLSHID_CUST_TABLES_DAC1_M3 EQU 0x49000132 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M4 +CYREG_FLSHID_CUST_TABLES_DAC1_M4 EQU 0x49000133 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M5 +CYREG_FLSHID_CUST_TABLES_DAC1_M5 EQU 0x49000134 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M6 +CYREG_FLSHID_CUST_TABLES_DAC1_M6 EQU 0x49000135 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M7 +CYREG_FLSHID_CUST_TABLES_DAC1_M7 EQU 0x49000136 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M8 +CYREG_FLSHID_CUST_TABLES_DAC1_M8 EQU 0x49000137 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M1 +CYREG_FLSHID_CUST_TABLES_DAC3_M1 EQU 0x49000138 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M2 +CYREG_FLSHID_CUST_TABLES_DAC3_M2 EQU 0x49000139 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M3 +CYREG_FLSHID_CUST_TABLES_DAC3_M3 EQU 0x4900013a + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M4 +CYREG_FLSHID_CUST_TABLES_DAC3_M4 EQU 0x4900013b + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M5 +CYREG_FLSHID_CUST_TABLES_DAC3_M5 EQU 0x4900013c + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M6 +CYREG_FLSHID_CUST_TABLES_DAC3_M6 EQU 0x4900013d + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M7 +CYREG_FLSHID_CUST_TABLES_DAC3_M7 EQU 0x4900013e + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M8 +CYREG_FLSHID_CUST_TABLES_DAC3_M8 EQU 0x4900013f + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_BASE +CYDEV_FLSHID_MFG_CFG_BASE EQU 0x49000180 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_SIZE +CYDEV_FLSHID_MFG_CFG_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_IMO_TR1 +CYREG_FLSHID_MFG_CFG_IMO_TR1 EQU 0x49000188 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP0_TR0 +CYREG_FLSHID_MFG_CFG_CMP0_TR0 EQU 0x490001ac + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP1_TR0 +CYREG_FLSHID_MFG_CFG_CMP1_TR0 EQU 0x490001ae + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP2_TR0 +CYREG_FLSHID_MFG_CFG_CMP2_TR0 EQU 0x490001b0 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP3_TR0 +CYREG_FLSHID_MFG_CFG_CMP3_TR0 EQU 0x490001b2 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP0_TR1 +CYREG_FLSHID_MFG_CFG_CMP0_TR1 EQU 0x490001b4 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP1_TR1 +CYREG_FLSHID_MFG_CFG_CMP1_TR1 EQU 0x490001b6 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP2_TR1 +CYREG_FLSHID_MFG_CFG_CMP2_TR1 EQU 0x490001b8 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP3_TR1 +CYREG_FLSHID_MFG_CFG_CMP3_TR1 EQU 0x490001ba + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM +CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM EQU 0x490001ce + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_BASE +CYDEV_EXTMEM_BASE EQU 0x60000000 + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_SIZE +CYDEV_EXTMEM_SIZE EQU 0x00800000 + ENDIF + IF :LNOT::DEF:CYREG_EXTMEM_DATA_MBASE +CYREG_EXTMEM_DATA_MBASE EQU 0x60000000 + ENDIF + IF :LNOT::DEF:CYREG_EXTMEM_DATA_MSIZE +CYREG_EXTMEM_DATA_MSIZE EQU 0x00800000 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_BASE +CYDEV_ITM_BASE EQU 0xe0000000 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_SIZE +CYDEV_ITM_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_ITM_TRACE_EN +CYREG_ITM_TRACE_EN EQU 0xe0000e00 + ENDIF + IF :LNOT::DEF:CYREG_ITM_TRACE_PRIVILEGE +CYREG_ITM_TRACE_PRIVILEGE EQU 0xe0000e40 + ENDIF + IF :LNOT::DEF:CYREG_ITM_TRACE_CTRL +CYREG_ITM_TRACE_CTRL EQU 0xe0000e80 + ENDIF + IF :LNOT::DEF:CYREG_ITM_LOCK_ACCESS +CYREG_ITM_LOCK_ACCESS EQU 0xe0000fb0 + ENDIF + IF :LNOT::DEF:CYREG_ITM_LOCK_STATUS +CYREG_ITM_LOCK_STATUS EQU 0xe0000fb4 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID4 +CYREG_ITM_PID4 EQU 0xe0000fd0 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID5 +CYREG_ITM_PID5 EQU 0xe0000fd4 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID6 +CYREG_ITM_PID6 EQU 0xe0000fd8 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID7 +CYREG_ITM_PID7 EQU 0xe0000fdc + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID0 +CYREG_ITM_PID0 EQU 0xe0000fe0 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID1 +CYREG_ITM_PID1 EQU 0xe0000fe4 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID2 +CYREG_ITM_PID2 EQU 0xe0000fe8 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID3 +CYREG_ITM_PID3 EQU 0xe0000fec + ENDIF + IF :LNOT::DEF:CYREG_ITM_CID0 +CYREG_ITM_CID0 EQU 0xe0000ff0 + ENDIF + IF :LNOT::DEF:CYREG_ITM_CID1 +CYREG_ITM_CID1 EQU 0xe0000ff4 + ENDIF + IF :LNOT::DEF:CYREG_ITM_CID2 +CYREG_ITM_CID2 EQU 0xe0000ff8 + ENDIF + IF :LNOT::DEF:CYREG_ITM_CID3 +CYREG_ITM_CID3 EQU 0xe0000ffc + ENDIF + IF :LNOT::DEF:CYDEV_DWT_BASE +CYDEV_DWT_BASE EQU 0xe0001000 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_SIZE +CYDEV_DWT_SIZE EQU 0x0000005c + ENDIF + IF :LNOT::DEF:CYREG_DWT_CTRL +CYREG_DWT_CTRL EQU 0xe0001000 + ENDIF + IF :LNOT::DEF:CYREG_DWT_CYCLE_COUNT +CYREG_DWT_CYCLE_COUNT EQU 0xe0001004 + ENDIF + IF :LNOT::DEF:CYREG_DWT_CPI_COUNT +CYREG_DWT_CPI_COUNT EQU 0xe0001008 + ENDIF + IF :LNOT::DEF:CYREG_DWT_EXC_OVHD_COUNT +CYREG_DWT_EXC_OVHD_COUNT EQU 0xe000100c + ENDIF + IF :LNOT::DEF:CYREG_DWT_SLEEP_COUNT +CYREG_DWT_SLEEP_COUNT EQU 0xe0001010 + ENDIF + IF :LNOT::DEF:CYREG_DWT_LSU_COUNT +CYREG_DWT_LSU_COUNT EQU 0xe0001014 + ENDIF + IF :LNOT::DEF:CYREG_DWT_FOLD_COUNT +CYREG_DWT_FOLD_COUNT EQU 0xe0001018 + ENDIF + IF :LNOT::DEF:CYREG_DWT_PC_SAMPLE +CYREG_DWT_PC_SAMPLE EQU 0xe000101c + ENDIF + IF :LNOT::DEF:CYREG_DWT_COMP_0 +CYREG_DWT_COMP_0 EQU 0xe0001020 + ENDIF + IF :LNOT::DEF:CYREG_DWT_MASK_0 +CYREG_DWT_MASK_0 EQU 0xe0001024 + ENDIF + IF :LNOT::DEF:CYREG_DWT_FUNCTION_0 +CYREG_DWT_FUNCTION_0 EQU 0xe0001028 + ENDIF + IF :LNOT::DEF:CYREG_DWT_COMP_1 +CYREG_DWT_COMP_1 EQU 0xe0001030 + ENDIF + IF :LNOT::DEF:CYREG_DWT_MASK_1 +CYREG_DWT_MASK_1 EQU 0xe0001034 + ENDIF + IF :LNOT::DEF:CYREG_DWT_FUNCTION_1 +CYREG_DWT_FUNCTION_1 EQU 0xe0001038 + ENDIF + IF :LNOT::DEF:CYREG_DWT_COMP_2 +CYREG_DWT_COMP_2 EQU 0xe0001040 + ENDIF + IF :LNOT::DEF:CYREG_DWT_MASK_2 +CYREG_DWT_MASK_2 EQU 0xe0001044 + ENDIF + IF :LNOT::DEF:CYREG_DWT_FUNCTION_2 +CYREG_DWT_FUNCTION_2 EQU 0xe0001048 + ENDIF + IF :LNOT::DEF:CYREG_DWT_COMP_3 +CYREG_DWT_COMP_3 EQU 0xe0001050 + ENDIF + IF :LNOT::DEF:CYREG_DWT_MASK_3 +CYREG_DWT_MASK_3 EQU 0xe0001054 + ENDIF + IF :LNOT::DEF:CYREG_DWT_FUNCTION_3 +CYREG_DWT_FUNCTION_3 EQU 0xe0001058 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_BASE +CYDEV_FPB_BASE EQU 0xe0002000 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_SIZE +CYDEV_FPB_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_FPB_CTRL +CYREG_FPB_CTRL EQU 0xe0002000 + ENDIF + IF :LNOT::DEF:CYREG_FPB_REMAP +CYREG_FPB_REMAP EQU 0xe0002004 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_0 +CYREG_FPB_FP_COMP_0 EQU 0xe0002008 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_1 +CYREG_FPB_FP_COMP_1 EQU 0xe000200c + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_2 +CYREG_FPB_FP_COMP_2 EQU 0xe0002010 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_3 +CYREG_FPB_FP_COMP_3 EQU 0xe0002014 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_4 +CYREG_FPB_FP_COMP_4 EQU 0xe0002018 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_5 +CYREG_FPB_FP_COMP_5 EQU 0xe000201c + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_6 +CYREG_FPB_FP_COMP_6 EQU 0xe0002020 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_7 +CYREG_FPB_FP_COMP_7 EQU 0xe0002024 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID4 +CYREG_FPB_PID4 EQU 0xe0002fd0 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID5 +CYREG_FPB_PID5 EQU 0xe0002fd4 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID6 +CYREG_FPB_PID6 EQU 0xe0002fd8 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID7 +CYREG_FPB_PID7 EQU 0xe0002fdc + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID0 +CYREG_FPB_PID0 EQU 0xe0002fe0 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID1 +CYREG_FPB_PID1 EQU 0xe0002fe4 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID2 +CYREG_FPB_PID2 EQU 0xe0002fe8 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID3 +CYREG_FPB_PID3 EQU 0xe0002fec + ENDIF + IF :LNOT::DEF:CYREG_FPB_CID0 +CYREG_FPB_CID0 EQU 0xe0002ff0 + ENDIF + IF :LNOT::DEF:CYREG_FPB_CID1 +CYREG_FPB_CID1 EQU 0xe0002ff4 + ENDIF + IF :LNOT::DEF:CYREG_FPB_CID2 +CYREG_FPB_CID2 EQU 0xe0002ff8 + ENDIF + IF :LNOT::DEF:CYREG_FPB_CID3 +CYREG_FPB_CID3 EQU 0xe0002ffc + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_BASE +CYDEV_NVIC_BASE EQU 0xe000e000 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SIZE +CYDEV_NVIC_SIZE EQU 0x00000d3c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_INT_CTL_TYPE +CYREG_NVIC_INT_CTL_TYPE EQU 0xe000e004 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYSTICK_CTL +CYREG_NVIC_SYSTICK_CTL EQU 0xe000e010 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYSTICK_RELOAD +CYREG_NVIC_SYSTICK_RELOAD EQU 0xe000e014 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYSTICK_CURRENT +CYREG_NVIC_SYSTICK_CURRENT EQU 0xe000e018 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYSTICK_CAL +CYREG_NVIC_SYSTICK_CAL EQU 0xe000e01c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SETENA0 +CYREG_NVIC_SETENA0 EQU 0xe000e100 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_CLRENA0 +CYREG_NVIC_CLRENA0 EQU 0xe000e180 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SETPEND0 +CYREG_NVIC_SETPEND0 EQU 0xe000e200 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_CLRPEND0 +CYREG_NVIC_CLRPEND0 EQU 0xe000e280 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_ACTIVE0 +CYREG_NVIC_ACTIVE0 EQU 0xe000e300 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_0 +CYREG_NVIC_PRI_0 EQU 0xe000e400 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_1 +CYREG_NVIC_PRI_1 EQU 0xe000e401 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_2 +CYREG_NVIC_PRI_2 EQU 0xe000e402 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_3 +CYREG_NVIC_PRI_3 EQU 0xe000e403 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_4 +CYREG_NVIC_PRI_4 EQU 0xe000e404 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_5 +CYREG_NVIC_PRI_5 EQU 0xe000e405 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_6 +CYREG_NVIC_PRI_6 EQU 0xe000e406 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_7 +CYREG_NVIC_PRI_7 EQU 0xe000e407 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_8 +CYREG_NVIC_PRI_8 EQU 0xe000e408 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_9 +CYREG_NVIC_PRI_9 EQU 0xe000e409 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_10 +CYREG_NVIC_PRI_10 EQU 0xe000e40a + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_11 +CYREG_NVIC_PRI_11 EQU 0xe000e40b + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_12 +CYREG_NVIC_PRI_12 EQU 0xe000e40c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_13 +CYREG_NVIC_PRI_13 EQU 0xe000e40d + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_14 +CYREG_NVIC_PRI_14 EQU 0xe000e40e + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_15 +CYREG_NVIC_PRI_15 EQU 0xe000e40f + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_16 +CYREG_NVIC_PRI_16 EQU 0xe000e410 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_17 +CYREG_NVIC_PRI_17 EQU 0xe000e411 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_18 +CYREG_NVIC_PRI_18 EQU 0xe000e412 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_19 +CYREG_NVIC_PRI_19 EQU 0xe000e413 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_20 +CYREG_NVIC_PRI_20 EQU 0xe000e414 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_21 +CYREG_NVIC_PRI_21 EQU 0xe000e415 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_22 +CYREG_NVIC_PRI_22 EQU 0xe000e416 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_23 +CYREG_NVIC_PRI_23 EQU 0xe000e417 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_24 +CYREG_NVIC_PRI_24 EQU 0xe000e418 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_25 +CYREG_NVIC_PRI_25 EQU 0xe000e419 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_26 +CYREG_NVIC_PRI_26 EQU 0xe000e41a + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_27 +CYREG_NVIC_PRI_27 EQU 0xe000e41b + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_28 +CYREG_NVIC_PRI_28 EQU 0xe000e41c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_29 +CYREG_NVIC_PRI_29 EQU 0xe000e41d + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_30 +CYREG_NVIC_PRI_30 EQU 0xe000e41e + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_31 +CYREG_NVIC_PRI_31 EQU 0xe000e41f + ENDIF + IF :LNOT::DEF:CYREG_NVIC_CPUID_BASE +CYREG_NVIC_CPUID_BASE EQU 0xe000ed00 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_INTR_CTRL_STATE +CYREG_NVIC_INTR_CTRL_STATE EQU 0xe000ed04 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_VECT_OFFSET +CYREG_NVIC_VECT_OFFSET EQU 0xe000ed08 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_APPLN_INTR +CYREG_NVIC_APPLN_INTR EQU 0xe000ed0c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYSTEM_CONTROL +CYREG_NVIC_SYSTEM_CONTROL EQU 0xe000ed10 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_CFG_CONTROL +CYREG_NVIC_CFG_CONTROL EQU 0xe000ed14 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYS_PRIO_HANDLER_4_7 +CYREG_NVIC_SYS_PRIO_HANDLER_4_7 EQU 0xe000ed18 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYS_PRIO_HANDLER_8_11 +CYREG_NVIC_SYS_PRIO_HANDLER_8_11 EQU 0xe000ed1c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYS_PRIO_HANDLER_12_15 +CYREG_NVIC_SYS_PRIO_HANDLER_12_15 EQU 0xe000ed20 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYS_HANDLER_CSR +CYREG_NVIC_SYS_HANDLER_CSR EQU 0xe000ed24 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_MEMMAN_FAULT_STATUS +CYREG_NVIC_MEMMAN_FAULT_STATUS EQU 0xe000ed28 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_BUS_FAULT_STATUS +CYREG_NVIC_BUS_FAULT_STATUS EQU 0xe000ed29 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_USAGE_FAULT_STATUS +CYREG_NVIC_USAGE_FAULT_STATUS EQU 0xe000ed2a + ENDIF + IF :LNOT::DEF:CYREG_NVIC_HARD_FAULT_STATUS +CYREG_NVIC_HARD_FAULT_STATUS EQU 0xe000ed2c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_DEBUG_FAULT_STATUS +CYREG_NVIC_DEBUG_FAULT_STATUS EQU 0xe000ed30 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_MEMMAN_FAULT_ADD +CYREG_NVIC_MEMMAN_FAULT_ADD EQU 0xe000ed34 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_BUS_FAULT_ADD +CYREG_NVIC_BUS_FAULT_ADD EQU 0xe000ed38 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_BASE +CYDEV_CORE_DBG_BASE EQU 0xe000edf0 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_SIZE +CYDEV_CORE_DBG_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CORE_DBG_DBG_HLT_CS +CYREG_CORE_DBG_DBG_HLT_CS EQU 0xe000edf0 + ENDIF + IF :LNOT::DEF:CYREG_CORE_DBG_DBG_REG_SEL +CYREG_CORE_DBG_DBG_REG_SEL EQU 0xe000edf4 + ENDIF + IF :LNOT::DEF:CYREG_CORE_DBG_DBG_REG_DATA +CYREG_CORE_DBG_DBG_REG_DATA EQU 0xe000edf8 + ENDIF + IF :LNOT::DEF:CYREG_CORE_DBG_EXC_MON_CTL +CYREG_CORE_DBG_EXC_MON_CTL EQU 0xe000edfc + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_BASE +CYDEV_TPIU_BASE EQU 0xe0040000 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_SIZE +CYDEV_TPIU_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ +CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ EQU 0xe0040000 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_CURRENT_SYNC_PRT_SZ +CYREG_TPIU_CURRENT_SYNC_PRT_SZ EQU 0xe0040004 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ASYNC_CLK_PRESCALER +CYREG_TPIU_ASYNC_CLK_PRESCALER EQU 0xe0040010 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PROTOCOL +CYREG_TPIU_PROTOCOL EQU 0xe00400f0 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_FORM_FLUSH_STAT +CYREG_TPIU_FORM_FLUSH_STAT EQU 0xe0040300 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_FORM_FLUSH_CTRL +CYREG_TPIU_FORM_FLUSH_CTRL EQU 0xe0040304 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_TRIGGER +CYREG_TPIU_TRIGGER EQU 0xe0040ee8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ITETMDATA +CYREG_TPIU_ITETMDATA EQU 0xe0040eec + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ITATBCTR2 +CYREG_TPIU_ITATBCTR2 EQU 0xe0040ef0 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ITATBCTR0 +CYREG_TPIU_ITATBCTR0 EQU 0xe0040ef8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ITITMDATA +CYREG_TPIU_ITITMDATA EQU 0xe0040efc + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ITCTRL +CYREG_TPIU_ITCTRL EQU 0xe0040f00 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_DEVID +CYREG_TPIU_DEVID EQU 0xe0040fc8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_DEVTYPE +CYREG_TPIU_DEVTYPE EQU 0xe0040fcc + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID4 +CYREG_TPIU_PID4 EQU 0xe0040fd0 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID5 +CYREG_TPIU_PID5 EQU 0xe0040fd4 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID6 +CYREG_TPIU_PID6 EQU 0xe0040fd8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID7 +CYREG_TPIU_PID7 EQU 0xe0040fdc + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID0 +CYREG_TPIU_PID0 EQU 0xe0040fe0 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID1 +CYREG_TPIU_PID1 EQU 0xe0040fe4 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID2 +CYREG_TPIU_PID2 EQU 0xe0040fe8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID3 +CYREG_TPIU_PID3 EQU 0xe0040fec + ENDIF + IF :LNOT::DEF:CYREG_TPIU_CID0 +CYREG_TPIU_CID0 EQU 0xe0040ff0 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_CID1 +CYREG_TPIU_CID1 EQU 0xe0040ff4 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_CID2 +CYREG_TPIU_CID2 EQU 0xe0040ff8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_CID3 +CYREG_TPIU_CID3 EQU 0xe0040ffc + ENDIF + IF :LNOT::DEF:CYDEV_ETM_BASE +CYDEV_ETM_BASE EQU 0xe0041000 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_SIZE +CYDEV_ETM_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CTL +CYREG_ETM_CTL EQU 0xe0041000 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CFG_CODE +CYREG_ETM_CFG_CODE EQU 0xe0041004 + ENDIF + IF :LNOT::DEF:CYREG_ETM_TRIG_EVENT +CYREG_ETM_TRIG_EVENT EQU 0xe0041008 + ENDIF + IF :LNOT::DEF:CYREG_ETM_STATUS +CYREG_ETM_STATUS EQU 0xe0041010 + ENDIF + IF :LNOT::DEF:CYREG_ETM_SYS_CFG +CYREG_ETM_SYS_CFG EQU 0xe0041014 + ENDIF + IF :LNOT::DEF:CYREG_ETM_TRACE_ENB_EVENT +CYREG_ETM_TRACE_ENB_EVENT EQU 0xe0041020 + ENDIF + IF :LNOT::DEF:CYREG_ETM_TRACE_EN_CTRL1 +CYREG_ETM_TRACE_EN_CTRL1 EQU 0xe0041024 + ENDIF + IF :LNOT::DEF:CYREG_ETM_FIFOFULL_LEVEL +CYREG_ETM_FIFOFULL_LEVEL EQU 0xe004102c + ENDIF + IF :LNOT::DEF:CYREG_ETM_SYNC_FREQ +CYREG_ETM_SYNC_FREQ EQU 0xe00411e0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_ETM_ID +CYREG_ETM_ETM_ID EQU 0xe00411e4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CFG_CODE_EXT +CYREG_ETM_CFG_CODE_EXT EQU 0xe00411e8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_TR_SS_EMBICE_CTRL +CYREG_ETM_TR_SS_EMBICE_CTRL EQU 0xe00411f0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CS_TRACE_ID +CYREG_ETM_CS_TRACE_ID EQU 0xe0041200 + ENDIF + IF :LNOT::DEF:CYREG_ETM_OS_LOCK_ACCESS +CYREG_ETM_OS_LOCK_ACCESS EQU 0xe0041300 + ENDIF + IF :LNOT::DEF:CYREG_ETM_OS_LOCK_STATUS +CYREG_ETM_OS_LOCK_STATUS EQU 0xe0041304 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PDSR +CYREG_ETM_PDSR EQU 0xe0041314 + ENDIF + IF :LNOT::DEF:CYREG_ETM_ITMISCIN +CYREG_ETM_ITMISCIN EQU 0xe0041ee0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_ITTRIGOUT +CYREG_ETM_ITTRIGOUT EQU 0xe0041ee8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_ITATBCTR2 +CYREG_ETM_ITATBCTR2 EQU 0xe0041ef0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_ITATBCTR0 +CYREG_ETM_ITATBCTR0 EQU 0xe0041ef8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_INT_MODE_CTRL +CYREG_ETM_INT_MODE_CTRL EQU 0xe0041f00 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CLM_TAG_SET +CYREG_ETM_CLM_TAG_SET EQU 0xe0041fa0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CLM_TAG_CLR +CYREG_ETM_CLM_TAG_CLR EQU 0xe0041fa4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_LOCK_ACCESS +CYREG_ETM_LOCK_ACCESS EQU 0xe0041fb0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_LOCK_STATUS +CYREG_ETM_LOCK_STATUS EQU 0xe0041fb4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_AUTH_STATUS +CYREG_ETM_AUTH_STATUS EQU 0xe0041fb8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_DEV_TYPE +CYREG_ETM_DEV_TYPE EQU 0xe0041fcc + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID4 +CYREG_ETM_PID4 EQU 0xe0041fd0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID5 +CYREG_ETM_PID5 EQU 0xe0041fd4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID6 +CYREG_ETM_PID6 EQU 0xe0041fd8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID7 +CYREG_ETM_PID7 EQU 0xe0041fdc + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID0 +CYREG_ETM_PID0 EQU 0xe0041fe0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID1 +CYREG_ETM_PID1 EQU 0xe0041fe4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID2 +CYREG_ETM_PID2 EQU 0xe0041fe8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID3 +CYREG_ETM_PID3 EQU 0xe0041fec + ENDIF + IF :LNOT::DEF:CYREG_ETM_CID0 +CYREG_ETM_CID0 EQU 0xe0041ff0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CID1 +CYREG_ETM_CID1 EQU 0xe0041ff4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CID2 +CYREG_ETM_CID2 EQU 0xe0041ff8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CID3 +CYREG_ETM_CID3 EQU 0xe0041ffc + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_BASE +CYDEV_ROM_TABLE_BASE EQU 0xe00ff000 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_SIZE +CYDEV_ROM_TABLE_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_NVIC +CYREG_ROM_TABLE_NVIC EQU 0xe00ff000 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_DWT +CYREG_ROM_TABLE_DWT EQU 0xe00ff004 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_FPB +CYREG_ROM_TABLE_FPB EQU 0xe00ff008 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_ITM +CYREG_ROM_TABLE_ITM EQU 0xe00ff00c + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_TPIU +CYREG_ROM_TABLE_TPIU EQU 0xe00ff010 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_ETM +CYREG_ROM_TABLE_ETM EQU 0xe00ff014 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_END +CYREG_ROM_TABLE_END EQU 0xe00ff018 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_MEMTYPE +CYREG_ROM_TABLE_MEMTYPE EQU 0xe00fffcc + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID4 +CYREG_ROM_TABLE_PID4 EQU 0xe00fffd0 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID5 +CYREG_ROM_TABLE_PID5 EQU 0xe00fffd4 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID6 +CYREG_ROM_TABLE_PID6 EQU 0xe00fffd8 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID7 +CYREG_ROM_TABLE_PID7 EQU 0xe00fffdc + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID0 +CYREG_ROM_TABLE_PID0 EQU 0xe00fffe0 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID1 +CYREG_ROM_TABLE_PID1 EQU 0xe00fffe4 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID2 +CYREG_ROM_TABLE_PID2 EQU 0xe00fffe8 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID3 +CYREG_ROM_TABLE_PID3 EQU 0xe00fffec + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_CID0 +CYREG_ROM_TABLE_CID0 EQU 0xe00ffff0 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_CID1 +CYREG_ROM_TABLE_CID1 EQU 0xe00ffff4 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_CID2 +CYREG_ROM_TABLE_CID2 EQU 0xe00ffff8 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_CID3 +CYREG_ROM_TABLE_CID3 EQU 0xe00ffffc + ENDIF + IF :LNOT::DEF:CYDEV_FLS_SIZE +CYDEV_FLS_SIZE EQU CYDEV_FLASH_SIZE + ENDIF + IF :LNOT::DEF:CYDEV_ECC_BASE +CYDEV_ECC_BASE EQU CYDEV_FLSECC_BASE + ENDIF + IF :LNOT::DEF:CYDEV_FLS_SECTOR_SIZE +CYDEV_FLS_SECTOR_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYDEV_FLS_ROW_SIZE +CYDEV_FLS_ROW_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_ECC_SECTOR_SIZE +CYDEV_ECC_SECTOR_SIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYDEV_ECC_ROW_SIZE +CYDEV_ECC_ROW_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_EEPROM_SECTOR_SIZE +CYDEV_EEPROM_SECTOR_SIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYDEV_EEPROM_ROW_SIZE +CYDEV_EEPROM_ROW_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PERIPH_BASE +CYDEV_PERIPH_BASE EQU CYDEV_CLKDIST_BASE + ENDIF + IF :LNOT::DEF:CYCLK_LD_DISABLE +CYCLK_LD_DISABLE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYCLK_LD_SYNC_EN +CYCLK_LD_SYNC_EN EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYCLK_LD_LOAD +CYCLK_LD_LOAD EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYCLK_PIPE +CYCLK_PIPE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYCLK_SSS +CYCLK_SSS EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYCLK_EARLY +CYCLK_EARLY EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYCLK_DUTY +CYCLK_DUTY EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYCLK_SYNC +CYCLK_SYNC EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_CLK_SYNC_D +CYCLK_SRC_SEL_CLK_SYNC_D EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_SYNC_DIG +CYCLK_SRC_SEL_SYNC_DIG EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_IMO +CYCLK_SRC_SEL_IMO EQU 1 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTAL_MHZ +CYCLK_SRC_SEL_XTAL_MHZ EQU 2 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTALM +CYCLK_SRC_SEL_XTALM EQU 2 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_ILO +CYCLK_SRC_SEL_ILO EQU 3 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_PLL +CYCLK_SRC_SEL_PLL EQU 4 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTAL_KHZ +CYCLK_SRC_SEL_XTAL_KHZ EQU 5 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTALK +CYCLK_SRC_SEL_XTALK EQU 5 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_G +CYCLK_SRC_SEL_DSI_G EQU 6 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_D +CYCLK_SRC_SEL_DSI_D EQU 7 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_CLK_SYNC_A +CYCLK_SRC_SEL_CLK_SYNC_A EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_A +CYCLK_SRC_SEL_DSI_A EQU 7 + ENDIF + END diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydisabledsheets.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydisabledsheets.h new file mode 100644 index 00000000..81788739 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cydisabledsheets.h @@ -0,0 +1,5 @@ +#ifndef INCLUDED_CYDISABLEDSHEETS_H +#define INCLUDED_CYDISABLEDSHEETS_H + + +#endif /* INCLUDED_CYDISABLEDSHEETS_H */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h new file mode 100755 index 00000000..dac33841 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -0,0 +1,1441 @@ +#ifndef INCLUDED_CYFITTER_H +#define INCLUDED_CYFITTER_H +#include +#include + +/* USBFS_bus_reset */ +#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_bus_reset__INTC_MASK 0x800000u +#define USBFS_bus_reset__INTC_NUMBER 23u +#define USBFS_bus_reset__INTC_PRIOR_NUM 7u +#define USBFS_bus_reset__INTC_PRIOR_REG CYREG_NVIC_PRI_23 +#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* USBFS_arb_int */ +#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_arb_int__INTC_MASK 0x400000u +#define USBFS_arb_int__INTC_NUMBER 22u +#define USBFS_arb_int__INTC_PRIOR_NUM 7u +#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22 +#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* USBFS_sof_int */ +#define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_sof_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_sof_int__INTC_MASK 0x200000u +#define USBFS_sof_int__INTC_NUMBER 21u +#define USBFS_sof_int__INTC_PRIOR_NUM 7u +#define USBFS_sof_int__INTC_PRIOR_REG CYREG_NVIC_PRI_21 +#define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SCSI_Out_DBx */ +#define SCSI_Out_DBx__0__AG CYREG_PRT5_AG +#define SCSI_Out_DBx__0__AMUX CYREG_PRT5_AMUX +#define SCSI_Out_DBx__0__BIE CYREG_PRT5_BIE +#define SCSI_Out_DBx__0__BIT_MASK CYREG_PRT5_BIT_MASK +#define SCSI_Out_DBx__0__BYP CYREG_PRT5_BYP +#define SCSI_Out_DBx__0__CTL CYREG_PRT5_CTL +#define SCSI_Out_DBx__0__DM0 CYREG_PRT5_DM0 +#define SCSI_Out_DBx__0__DM1 CYREG_PRT5_DM1 +#define SCSI_Out_DBx__0__DM2 CYREG_PRT5_DM2 +#define SCSI_Out_DBx__0__DR CYREG_PRT5_DR +#define SCSI_Out_DBx__0__INP_DIS CYREG_PRT5_INP_DIS +#define SCSI_Out_DBx__0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG +#define SCSI_Out_DBx__0__LCD_EN CYREG_PRT5_LCD_EN +#define SCSI_Out_DBx__0__MASK 0x02u +#define SCSI_Out_DBx__0__PC CYREG_PRT5_PC1 +#define SCSI_Out_DBx__0__PORT 5u +#define SCSI_Out_DBx__0__PRT CYREG_PRT5_PRT +#define SCSI_Out_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL +#define SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN +#define SCSI_Out_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 +#define SCSI_Out_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 +#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 +#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 +#define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT +#define SCSI_Out_DBx__0__PS CYREG_PRT5_PS +#define SCSI_Out_DBx__0__SHIFT 1 +#define SCSI_Out_DBx__0__SLW CYREG_PRT5_SLW +#define SCSI_Out_DBx__1__AG CYREG_PRT5_AG +#define SCSI_Out_DBx__1__AMUX CYREG_PRT5_AMUX +#define SCSI_Out_DBx__1__BIE CYREG_PRT5_BIE +#define SCSI_Out_DBx__1__BIT_MASK CYREG_PRT5_BIT_MASK +#define SCSI_Out_DBx__1__BYP CYREG_PRT5_BYP +#define SCSI_Out_DBx__1__CTL CYREG_PRT5_CTL +#define SCSI_Out_DBx__1__DM0 CYREG_PRT5_DM0 +#define SCSI_Out_DBx__1__DM1 CYREG_PRT5_DM1 +#define SCSI_Out_DBx__1__DM2 CYREG_PRT5_DM2 +#define SCSI_Out_DBx__1__DR CYREG_PRT5_DR +#define SCSI_Out_DBx__1__INP_DIS CYREG_PRT5_INP_DIS +#define SCSI_Out_DBx__1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG +#define SCSI_Out_DBx__1__LCD_EN CYREG_PRT5_LCD_EN +#define SCSI_Out_DBx__1__MASK 0x01u +#define SCSI_Out_DBx__1__PC CYREG_PRT5_PC0 +#define SCSI_Out_DBx__1__PORT 5u +#define SCSI_Out_DBx__1__PRT CYREG_PRT5_PRT +#define SCSI_Out_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL +#define SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN +#define SCSI_Out_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 +#define SCSI_Out_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 +#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 +#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 +#define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT +#define SCSI_Out_DBx__1__PS CYREG_PRT5_PS +#define SCSI_Out_DBx__1__SHIFT 0 +#define SCSI_Out_DBx__1__SLW CYREG_PRT5_SLW +#define SCSI_Out_DBx__2__AG CYREG_PRT6_AG +#define SCSI_Out_DBx__2__AMUX CYREG_PRT6_AMUX +#define SCSI_Out_DBx__2__BIE CYREG_PRT6_BIE +#define SCSI_Out_DBx__2__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out_DBx__2__BYP CYREG_PRT6_BYP +#define SCSI_Out_DBx__2__CTL CYREG_PRT6_CTL +#define SCSI_Out_DBx__2__DM0 CYREG_PRT6_DM0 +#define SCSI_Out_DBx__2__DM1 CYREG_PRT6_DM1 +#define SCSI_Out_DBx__2__DM2 CYREG_PRT6_DM2 +#define SCSI_Out_DBx__2__DR CYREG_PRT6_DR +#define SCSI_Out_DBx__2__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out_DBx__2__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out_DBx__2__MASK 0x20u +#define SCSI_Out_DBx__2__PC CYREG_PRT6_PC5 +#define SCSI_Out_DBx__2__PORT 6u +#define SCSI_Out_DBx__2__PRT CYREG_PRT6_PRT +#define SCSI_Out_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out_DBx__2__PS CYREG_PRT6_PS +#define SCSI_Out_DBx__2__SHIFT 5 +#define SCSI_Out_DBx__2__SLW CYREG_PRT6_SLW +#define SCSI_Out_DBx__3__AG CYREG_PRT6_AG +#define SCSI_Out_DBx__3__AMUX CYREG_PRT6_AMUX +#define SCSI_Out_DBx__3__BIE CYREG_PRT6_BIE +#define SCSI_Out_DBx__3__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out_DBx__3__BYP CYREG_PRT6_BYP +#define SCSI_Out_DBx__3__CTL CYREG_PRT6_CTL +#define SCSI_Out_DBx__3__DM0 CYREG_PRT6_DM0 +#define SCSI_Out_DBx__3__DM1 CYREG_PRT6_DM1 +#define SCSI_Out_DBx__3__DM2 CYREG_PRT6_DM2 +#define SCSI_Out_DBx__3__DR CYREG_PRT6_DR +#define SCSI_Out_DBx__3__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out_DBx__3__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out_DBx__3__MASK 0x10u +#define SCSI_Out_DBx__3__PC CYREG_PRT6_PC4 +#define SCSI_Out_DBx__3__PORT 6u +#define SCSI_Out_DBx__3__PRT CYREG_PRT6_PRT +#define SCSI_Out_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out_DBx__3__PS CYREG_PRT6_PS +#define SCSI_Out_DBx__3__SHIFT 4 +#define SCSI_Out_DBx__3__SLW CYREG_PRT6_SLW +#define SCSI_Out_DBx__4__AG CYREG_PRT2_AG +#define SCSI_Out_DBx__4__AMUX CYREG_PRT2_AMUX +#define SCSI_Out_DBx__4__BIE CYREG_PRT2_BIE +#define SCSI_Out_DBx__4__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Out_DBx__4__BYP CYREG_PRT2_BYP +#define SCSI_Out_DBx__4__CTL CYREG_PRT2_CTL +#define SCSI_Out_DBx__4__DM0 CYREG_PRT2_DM0 +#define SCSI_Out_DBx__4__DM1 CYREG_PRT2_DM1 +#define SCSI_Out_DBx__4__DM2 CYREG_PRT2_DM2 +#define SCSI_Out_DBx__4__DR CYREG_PRT2_DR +#define SCSI_Out_DBx__4__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Out_DBx__4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Out_DBx__4__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Out_DBx__4__MASK 0x80u +#define SCSI_Out_DBx__4__PC CYREG_PRT2_PC7 +#define SCSI_Out_DBx__4__PORT 2u +#define SCSI_Out_DBx__4__PRT CYREG_PRT2_PRT +#define SCSI_Out_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Out_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Out_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Out_DBx__4__PS CYREG_PRT2_PS +#define SCSI_Out_DBx__4__SHIFT 7 +#define SCSI_Out_DBx__4__SLW CYREG_PRT2_SLW +#define SCSI_Out_DBx__5__AG CYREG_PRT2_AG +#define SCSI_Out_DBx__5__AMUX CYREG_PRT2_AMUX +#define SCSI_Out_DBx__5__BIE CYREG_PRT2_BIE +#define SCSI_Out_DBx__5__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Out_DBx__5__BYP CYREG_PRT2_BYP +#define SCSI_Out_DBx__5__CTL CYREG_PRT2_CTL +#define SCSI_Out_DBx__5__DM0 CYREG_PRT2_DM0 +#define SCSI_Out_DBx__5__DM1 CYREG_PRT2_DM1 +#define SCSI_Out_DBx__5__DM2 CYREG_PRT2_DM2 +#define SCSI_Out_DBx__5__DR CYREG_PRT2_DR +#define SCSI_Out_DBx__5__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Out_DBx__5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Out_DBx__5__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Out_DBx__5__MASK 0x40u +#define SCSI_Out_DBx__5__PC CYREG_PRT2_PC6 +#define SCSI_Out_DBx__5__PORT 2u +#define SCSI_Out_DBx__5__PRT CYREG_PRT2_PRT +#define SCSI_Out_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Out_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Out_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Out_DBx__5__PS CYREG_PRT2_PS +#define SCSI_Out_DBx__5__SHIFT 6 +#define SCSI_Out_DBx__5__SLW CYREG_PRT2_SLW +#define SCSI_Out_DBx__6__AG CYREG_PRT2_AG +#define SCSI_Out_DBx__6__AMUX CYREG_PRT2_AMUX +#define SCSI_Out_DBx__6__BIE CYREG_PRT2_BIE +#define SCSI_Out_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Out_DBx__6__BYP CYREG_PRT2_BYP +#define SCSI_Out_DBx__6__CTL CYREG_PRT2_CTL +#define SCSI_Out_DBx__6__DM0 CYREG_PRT2_DM0 +#define SCSI_Out_DBx__6__DM1 CYREG_PRT2_DM1 +#define SCSI_Out_DBx__6__DM2 CYREG_PRT2_DM2 +#define SCSI_Out_DBx__6__DR CYREG_PRT2_DR +#define SCSI_Out_DBx__6__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Out_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Out_DBx__6__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Out_DBx__6__MASK 0x08u +#define SCSI_Out_DBx__6__PC CYREG_PRT2_PC3 +#define SCSI_Out_DBx__6__PORT 2u +#define SCSI_Out_DBx__6__PRT CYREG_PRT2_PRT +#define SCSI_Out_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Out_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Out_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Out_DBx__6__PS CYREG_PRT2_PS +#define SCSI_Out_DBx__6__SHIFT 3 +#define SCSI_Out_DBx__6__SLW CYREG_PRT2_SLW +#define SCSI_Out_DBx__7__AG CYREG_PRT2_AG +#define SCSI_Out_DBx__7__AMUX CYREG_PRT2_AMUX +#define SCSI_Out_DBx__7__BIE CYREG_PRT2_BIE +#define SCSI_Out_DBx__7__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Out_DBx__7__BYP CYREG_PRT2_BYP +#define SCSI_Out_DBx__7__CTL CYREG_PRT2_CTL +#define SCSI_Out_DBx__7__DM0 CYREG_PRT2_DM0 +#define SCSI_Out_DBx__7__DM1 CYREG_PRT2_DM1 +#define SCSI_Out_DBx__7__DM2 CYREG_PRT2_DM2 +#define SCSI_Out_DBx__7__DR CYREG_PRT2_DR +#define SCSI_Out_DBx__7__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Out_DBx__7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Out_DBx__7__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Out_DBx__7__MASK 0x04u +#define SCSI_Out_DBx__7__PC CYREG_PRT2_PC2 +#define SCSI_Out_DBx__7__PORT 2u +#define SCSI_Out_DBx__7__PRT CYREG_PRT2_PRT +#define SCSI_Out_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Out_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Out_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Out_DBx__7__PS CYREG_PRT2_PS +#define SCSI_Out_DBx__7__SHIFT 2 +#define SCSI_Out_DBx__7__SLW CYREG_PRT2_SLW +#define SCSI_Out_DBx__DB0__AG CYREG_PRT5_AG +#define SCSI_Out_DBx__DB0__AMUX CYREG_PRT5_AMUX +#define SCSI_Out_DBx__DB0__BIE CYREG_PRT5_BIE +#define SCSI_Out_DBx__DB0__BIT_MASK CYREG_PRT5_BIT_MASK +#define SCSI_Out_DBx__DB0__BYP CYREG_PRT5_BYP +#define SCSI_Out_DBx__DB0__CTL CYREG_PRT5_CTL +#define SCSI_Out_DBx__DB0__DM0 CYREG_PRT5_DM0 +#define SCSI_Out_DBx__DB0__DM1 CYREG_PRT5_DM1 +#define SCSI_Out_DBx__DB0__DM2 CYREG_PRT5_DM2 +#define SCSI_Out_DBx__DB0__DR CYREG_PRT5_DR +#define SCSI_Out_DBx__DB0__INP_DIS CYREG_PRT5_INP_DIS +#define SCSI_Out_DBx__DB0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG +#define SCSI_Out_DBx__DB0__LCD_EN CYREG_PRT5_LCD_EN +#define SCSI_Out_DBx__DB0__MASK 0x02u +#define SCSI_Out_DBx__DB0__PC CYREG_PRT5_PC1 +#define SCSI_Out_DBx__DB0__PORT 5u +#define SCSI_Out_DBx__DB0__PRT CYREG_PRT5_PRT +#define SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL +#define SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN +#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 +#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 +#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 +#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 +#define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT +#define SCSI_Out_DBx__DB0__PS CYREG_PRT5_PS +#define SCSI_Out_DBx__DB0__SHIFT 1 +#define SCSI_Out_DBx__DB0__SLW CYREG_PRT5_SLW +#define SCSI_Out_DBx__DB1__AG CYREG_PRT5_AG +#define SCSI_Out_DBx__DB1__AMUX CYREG_PRT5_AMUX +#define SCSI_Out_DBx__DB1__BIE CYREG_PRT5_BIE +#define SCSI_Out_DBx__DB1__BIT_MASK CYREG_PRT5_BIT_MASK +#define SCSI_Out_DBx__DB1__BYP CYREG_PRT5_BYP +#define SCSI_Out_DBx__DB1__CTL CYREG_PRT5_CTL +#define SCSI_Out_DBx__DB1__DM0 CYREG_PRT5_DM0 +#define SCSI_Out_DBx__DB1__DM1 CYREG_PRT5_DM1 +#define SCSI_Out_DBx__DB1__DM2 CYREG_PRT5_DM2 +#define SCSI_Out_DBx__DB1__DR CYREG_PRT5_DR +#define SCSI_Out_DBx__DB1__INP_DIS CYREG_PRT5_INP_DIS +#define SCSI_Out_DBx__DB1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG +#define SCSI_Out_DBx__DB1__LCD_EN CYREG_PRT5_LCD_EN +#define SCSI_Out_DBx__DB1__MASK 0x01u +#define SCSI_Out_DBx__DB1__PC CYREG_PRT5_PC0 +#define SCSI_Out_DBx__DB1__PORT 5u +#define SCSI_Out_DBx__DB1__PRT CYREG_PRT5_PRT +#define SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL +#define SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN +#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 +#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 +#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 +#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 +#define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT +#define SCSI_Out_DBx__DB1__PS CYREG_PRT5_PS +#define SCSI_Out_DBx__DB1__SHIFT 0 +#define SCSI_Out_DBx__DB1__SLW CYREG_PRT5_SLW +#define SCSI_Out_DBx__DB2__AG CYREG_PRT6_AG +#define SCSI_Out_DBx__DB2__AMUX CYREG_PRT6_AMUX +#define SCSI_Out_DBx__DB2__BIE CYREG_PRT6_BIE +#define SCSI_Out_DBx__DB2__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out_DBx__DB2__BYP CYREG_PRT6_BYP +#define SCSI_Out_DBx__DB2__CTL CYREG_PRT6_CTL +#define SCSI_Out_DBx__DB2__DM0 CYREG_PRT6_DM0 +#define SCSI_Out_DBx__DB2__DM1 CYREG_PRT6_DM1 +#define SCSI_Out_DBx__DB2__DM2 CYREG_PRT6_DM2 +#define SCSI_Out_DBx__DB2__DR CYREG_PRT6_DR +#define SCSI_Out_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out_DBx__DB2__MASK 0x20u +#define SCSI_Out_DBx__DB2__PC CYREG_PRT6_PC5 +#define SCSI_Out_DBx__DB2__PORT 6u +#define SCSI_Out_DBx__DB2__PRT CYREG_PRT6_PRT +#define SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out_DBx__DB2__PS CYREG_PRT6_PS +#define SCSI_Out_DBx__DB2__SHIFT 5 +#define SCSI_Out_DBx__DB2__SLW CYREG_PRT6_SLW +#define SCSI_Out_DBx__DB3__AG CYREG_PRT6_AG +#define SCSI_Out_DBx__DB3__AMUX CYREG_PRT6_AMUX +#define SCSI_Out_DBx__DB3__BIE CYREG_PRT6_BIE +#define SCSI_Out_DBx__DB3__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out_DBx__DB3__BYP CYREG_PRT6_BYP +#define SCSI_Out_DBx__DB3__CTL CYREG_PRT6_CTL +#define SCSI_Out_DBx__DB3__DM0 CYREG_PRT6_DM0 +#define SCSI_Out_DBx__DB3__DM1 CYREG_PRT6_DM1 +#define SCSI_Out_DBx__DB3__DM2 CYREG_PRT6_DM2 +#define SCSI_Out_DBx__DB3__DR CYREG_PRT6_DR +#define SCSI_Out_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out_DBx__DB3__MASK 0x10u +#define SCSI_Out_DBx__DB3__PC CYREG_PRT6_PC4 +#define SCSI_Out_DBx__DB3__PORT 6u +#define SCSI_Out_DBx__DB3__PRT CYREG_PRT6_PRT +#define SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out_DBx__DB3__PS CYREG_PRT6_PS +#define SCSI_Out_DBx__DB3__SHIFT 4 +#define SCSI_Out_DBx__DB3__SLW CYREG_PRT6_SLW +#define SCSI_Out_DBx__DB4__AG CYREG_PRT2_AG +#define SCSI_Out_DBx__DB4__AMUX CYREG_PRT2_AMUX +#define SCSI_Out_DBx__DB4__BIE CYREG_PRT2_BIE +#define SCSI_Out_DBx__DB4__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Out_DBx__DB4__BYP CYREG_PRT2_BYP +#define SCSI_Out_DBx__DB4__CTL CYREG_PRT2_CTL +#define SCSI_Out_DBx__DB4__DM0 CYREG_PRT2_DM0 +#define SCSI_Out_DBx__DB4__DM1 CYREG_PRT2_DM1 +#define SCSI_Out_DBx__DB4__DM2 CYREG_PRT2_DM2 +#define SCSI_Out_DBx__DB4__DR CYREG_PRT2_DR +#define SCSI_Out_DBx__DB4__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Out_DBx__DB4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Out_DBx__DB4__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Out_DBx__DB4__MASK 0x80u +#define SCSI_Out_DBx__DB4__PC CYREG_PRT2_PC7 +#define SCSI_Out_DBx__DB4__PORT 2u +#define SCSI_Out_DBx__DB4__PRT CYREG_PRT2_PRT +#define SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Out_DBx__DB4__PS CYREG_PRT2_PS +#define SCSI_Out_DBx__DB4__SHIFT 7 +#define SCSI_Out_DBx__DB4__SLW CYREG_PRT2_SLW +#define SCSI_Out_DBx__DB5__AG CYREG_PRT2_AG +#define SCSI_Out_DBx__DB5__AMUX CYREG_PRT2_AMUX +#define SCSI_Out_DBx__DB5__BIE CYREG_PRT2_BIE +#define SCSI_Out_DBx__DB5__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Out_DBx__DB5__BYP CYREG_PRT2_BYP +#define SCSI_Out_DBx__DB5__CTL CYREG_PRT2_CTL +#define SCSI_Out_DBx__DB5__DM0 CYREG_PRT2_DM0 +#define SCSI_Out_DBx__DB5__DM1 CYREG_PRT2_DM1 +#define SCSI_Out_DBx__DB5__DM2 CYREG_PRT2_DM2 +#define SCSI_Out_DBx__DB5__DR CYREG_PRT2_DR +#define SCSI_Out_DBx__DB5__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Out_DBx__DB5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Out_DBx__DB5__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Out_DBx__DB5__MASK 0x40u +#define SCSI_Out_DBx__DB5__PC CYREG_PRT2_PC6 +#define SCSI_Out_DBx__DB5__PORT 2u +#define SCSI_Out_DBx__DB5__PRT CYREG_PRT2_PRT +#define SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Out_DBx__DB5__PS CYREG_PRT2_PS +#define SCSI_Out_DBx__DB5__SHIFT 6 +#define SCSI_Out_DBx__DB5__SLW CYREG_PRT2_SLW +#define SCSI_Out_DBx__DB6__AG CYREG_PRT2_AG +#define SCSI_Out_DBx__DB6__AMUX CYREG_PRT2_AMUX +#define SCSI_Out_DBx__DB6__BIE CYREG_PRT2_BIE +#define SCSI_Out_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Out_DBx__DB6__BYP CYREG_PRT2_BYP +#define SCSI_Out_DBx__DB6__CTL CYREG_PRT2_CTL +#define SCSI_Out_DBx__DB6__DM0 CYREG_PRT2_DM0 +#define SCSI_Out_DBx__DB6__DM1 CYREG_PRT2_DM1 +#define SCSI_Out_DBx__DB6__DM2 CYREG_PRT2_DM2 +#define SCSI_Out_DBx__DB6__DR CYREG_PRT2_DR +#define SCSI_Out_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Out_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Out_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Out_DBx__DB6__MASK 0x08u +#define SCSI_Out_DBx__DB6__PC CYREG_PRT2_PC3 +#define SCSI_Out_DBx__DB6__PORT 2u +#define SCSI_Out_DBx__DB6__PRT CYREG_PRT2_PRT +#define SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Out_DBx__DB6__PS CYREG_PRT2_PS +#define SCSI_Out_DBx__DB6__SHIFT 3 +#define SCSI_Out_DBx__DB6__SLW CYREG_PRT2_SLW +#define SCSI_Out_DBx__DB7__AG CYREG_PRT2_AG +#define SCSI_Out_DBx__DB7__AMUX CYREG_PRT2_AMUX +#define SCSI_Out_DBx__DB7__BIE CYREG_PRT2_BIE +#define SCSI_Out_DBx__DB7__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Out_DBx__DB7__BYP CYREG_PRT2_BYP +#define SCSI_Out_DBx__DB7__CTL CYREG_PRT2_CTL +#define SCSI_Out_DBx__DB7__DM0 CYREG_PRT2_DM0 +#define SCSI_Out_DBx__DB7__DM1 CYREG_PRT2_DM1 +#define SCSI_Out_DBx__DB7__DM2 CYREG_PRT2_DM2 +#define SCSI_Out_DBx__DB7__DR CYREG_PRT2_DR +#define SCSI_Out_DBx__DB7__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Out_DBx__DB7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Out_DBx__DB7__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Out_DBx__DB7__MASK 0x04u +#define SCSI_Out_DBx__DB7__PC CYREG_PRT2_PC2 +#define SCSI_Out_DBx__DB7__PORT 2u +#define SCSI_Out_DBx__DB7__PRT CYREG_PRT2_PRT +#define SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Out_DBx__DB7__PS CYREG_PRT2_PS +#define SCSI_Out_DBx__DB7__SHIFT 2 +#define SCSI_Out_DBx__DB7__SLW CYREG_PRT2_SLW + +/* USBFS_dp_int */ +#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_dp_int__INTC_MASK 0x1000u +#define USBFS_dp_int__INTC_NUMBER 12u +#define USBFS_dp_int__INTC_PRIOR_NUM 7u +#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12 +#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* USBFS_ep_0 */ +#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_0__INTC_MASK 0x1000000u +#define USBFS_ep_0__INTC_NUMBER 24u +#define USBFS_ep_0__INTC_PRIOR_NUM 7u +#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24 +#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* USBFS_ep_1 */ +#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_1__INTC_MASK 0x01u +#define USBFS_ep_1__INTC_NUMBER 0u +#define USBFS_ep_1__INTC_PRIOR_NUM 7u +#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_0 +#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* USBFS_ep_2 */ +#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_2__INTC_MASK 0x02u +#define USBFS_ep_2__INTC_NUMBER 1u +#define USBFS_ep_2__INTC_PRIOR_NUM 7u +#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_1 +#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SD_PULLUP */ +#define SD_PULLUP__0__MASK 0x02u +#define SD_PULLUP__0__PC CYREG_PRT3_PC1 +#define SD_PULLUP__0__PORT 3u +#define SD_PULLUP__0__SHIFT 1 +#define SD_PULLUP__1__MASK 0x04u +#define SD_PULLUP__1__PC CYREG_PRT3_PC2 +#define SD_PULLUP__1__PORT 3u +#define SD_PULLUP__1__SHIFT 2 +#define SD_PULLUP__2__MASK 0x08u +#define SD_PULLUP__2__PC CYREG_PRT3_PC3 +#define SD_PULLUP__2__PORT 3u +#define SD_PULLUP__2__SHIFT 3 +#define SD_PULLUP__3__MASK 0x10u +#define SD_PULLUP__3__PC CYREG_PRT3_PC4 +#define SD_PULLUP__3__PORT 3u +#define SD_PULLUP__3__SHIFT 4 +#define SD_PULLUP__4__MASK 0x20u +#define SD_PULLUP__4__PC CYREG_PRT3_PC5 +#define SD_PULLUP__4__PORT 3u +#define SD_PULLUP__4__SHIFT 5 +#define SD_PULLUP__AG CYREG_PRT3_AG +#define SD_PULLUP__AMUX CYREG_PRT3_AMUX +#define SD_PULLUP__BIE CYREG_PRT3_BIE +#define SD_PULLUP__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_PULLUP__BYP CYREG_PRT3_BYP +#define SD_PULLUP__CTL CYREG_PRT3_CTL +#define SD_PULLUP__DM0 CYREG_PRT3_DM0 +#define SD_PULLUP__DM1 CYREG_PRT3_DM1 +#define SD_PULLUP__DM2 CYREG_PRT3_DM2 +#define SD_PULLUP__DR CYREG_PRT3_DR +#define SD_PULLUP__INP_DIS CYREG_PRT3_INP_DIS +#define SD_PULLUP__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_PULLUP__LCD_EN CYREG_PRT3_LCD_EN +#define SD_PULLUP__MASK 0x3Eu +#define SD_PULLUP__PORT 3u +#define SD_PULLUP__PRT CYREG_PRT3_PRT +#define SD_PULLUP__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_PULLUP__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_PULLUP__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_PULLUP__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_PULLUP__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_PULLUP__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_PULLUP__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_PULLUP__PS CYREG_PRT3_PS +#define SD_PULLUP__SHIFT 1 +#define SD_PULLUP__SLW CYREG_PRT3_SLW + +/* USBFS_USB */ +#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG +#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG +#define USBFS_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN +#define USBFS_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR +#define USBFS_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG +#define USBFS_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN +#define USBFS_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR +#define USBFS_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG +#define USBFS_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN +#define USBFS_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR +#define USBFS_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG +#define USBFS_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN +#define USBFS_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR +#define USBFS_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG +#define USBFS_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN +#define USBFS_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR +#define USBFS_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG +#define USBFS_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN +#define USBFS_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR +#define USBFS_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG +#define USBFS_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN +#define USBFS_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR +#define USBFS_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG +#define USBFS_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN +#define USBFS_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR +#define USBFS_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN +#define USBFS_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR +#define USBFS_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR +#define USBFS_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA +#define USBFS_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB +#define USBFS_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA +#define USBFS_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB +#define USBFS_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR +#define USBFS_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA +#define USBFS_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB +#define USBFS_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA +#define USBFS_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB +#define USBFS_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR +#define USBFS_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA +#define USBFS_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB +#define USBFS_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA +#define USBFS_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB +#define USBFS_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR +#define USBFS_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA +#define USBFS_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB +#define USBFS_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA +#define USBFS_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB +#define USBFS_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR +#define USBFS_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA +#define USBFS_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB +#define USBFS_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA +#define USBFS_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB +#define USBFS_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR +#define USBFS_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA +#define USBFS_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB +#define USBFS_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA +#define USBFS_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB +#define USBFS_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR +#define USBFS_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA +#define USBFS_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB +#define USBFS_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA +#define USBFS_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB +#define USBFS_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR +#define USBFS_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA +#define USBFS_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB +#define USBFS_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA +#define USBFS_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB +#define USBFS_USB__BUF_SIZE CYREG_USB_BUF_SIZE +#define USBFS_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT +#define USBFS_USB__CR0 CYREG_USB_CR0 +#define USBFS_USB__CR1 CYREG_USB_CR1 +#define USBFS_USB__CWA CYREG_USB_CWA +#define USBFS_USB__CWA_MSB CYREG_USB_CWA_MSB +#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES +#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB +#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG +#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT +#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR +#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0 +#define USBFS_USB__EP0_DR1 CYREG_USB_EP0_DR1 +#define USBFS_USB__EP0_DR2 CYREG_USB_EP0_DR2 +#define USBFS_USB__EP0_DR3 CYREG_USB_EP0_DR3 +#define USBFS_USB__EP0_DR4 CYREG_USB_EP0_DR4 +#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5 +#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6 +#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7 +#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE +#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE +#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE +#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5 +#define USBFS_USB__PM_ACT_MSK 0x01u +#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5 +#define USBFS_USB__PM_STBY_MSK 0x01u +#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0 +#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1 +#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0 +#define USBFS_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0 +#define USBFS_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1 +#define USBFS_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0 +#define USBFS_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0 +#define USBFS_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1 +#define USBFS_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0 +#define USBFS_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0 +#define USBFS_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1 +#define USBFS_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0 +#define USBFS_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0 +#define USBFS_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1 +#define USBFS_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0 +#define USBFS_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0 +#define USBFS_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1 +#define USBFS_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0 +#define USBFS_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0 +#define USBFS_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1 +#define USBFS_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0 +#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0 +#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1 +#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0 +#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN +#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR +#define USBFS_USB__SOF0 CYREG_USB_SOF0 +#define USBFS_USB__SOF1 CYREG_USB_SOF1 +#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0 +#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1 +#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN + +/* SCSI_Out */ +#define SCSI_Out__0__AG CYREG_PRT15_AG +#define SCSI_Out__0__AMUX CYREG_PRT15_AMUX +#define SCSI_Out__0__BIE CYREG_PRT15_BIE +#define SCSI_Out__0__BIT_MASK CYREG_PRT15_BIT_MASK +#define SCSI_Out__0__BYP CYREG_PRT15_BYP +#define SCSI_Out__0__CTL CYREG_PRT15_CTL +#define SCSI_Out__0__DM0 CYREG_PRT15_DM0 +#define SCSI_Out__0__DM1 CYREG_PRT15_DM1 +#define SCSI_Out__0__DM2 CYREG_PRT15_DM2 +#define SCSI_Out__0__DR CYREG_PRT15_DR +#define SCSI_Out__0__INP_DIS CYREG_PRT15_INP_DIS +#define SCSI_Out__0__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define SCSI_Out__0__LCD_EN CYREG_PRT15_LCD_EN +#define SCSI_Out__0__MASK 0x20u +#define SCSI_Out__0__PC CYREG_IO_PC_PRT15_PC5 +#define SCSI_Out__0__PORT 15u +#define SCSI_Out__0__PRT CYREG_PRT15_PRT +#define SCSI_Out__0__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define SCSI_Out__0__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define SCSI_Out__0__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define SCSI_Out__0__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define SCSI_Out__0__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define SCSI_Out__0__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define SCSI_Out__0__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define SCSI_Out__0__PS CYREG_PRT15_PS +#define SCSI_Out__0__SHIFT 5 +#define SCSI_Out__0__SLW CYREG_PRT15_SLW +#define SCSI_Out__1__AG CYREG_PRT15_AG +#define SCSI_Out__1__AMUX CYREG_PRT15_AMUX +#define SCSI_Out__1__BIE CYREG_PRT15_BIE +#define SCSI_Out__1__BIT_MASK CYREG_PRT15_BIT_MASK +#define SCSI_Out__1__BYP CYREG_PRT15_BYP +#define SCSI_Out__1__CTL CYREG_PRT15_CTL +#define SCSI_Out__1__DM0 CYREG_PRT15_DM0 +#define SCSI_Out__1__DM1 CYREG_PRT15_DM1 +#define SCSI_Out__1__DM2 CYREG_PRT15_DM2 +#define SCSI_Out__1__DR CYREG_PRT15_DR +#define SCSI_Out__1__INP_DIS CYREG_PRT15_INP_DIS +#define SCSI_Out__1__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define SCSI_Out__1__LCD_EN CYREG_PRT15_LCD_EN +#define SCSI_Out__1__MASK 0x10u +#define SCSI_Out__1__PC CYREG_IO_PC_PRT15_PC4 +#define SCSI_Out__1__PORT 15u +#define SCSI_Out__1__PRT CYREG_PRT15_PRT +#define SCSI_Out__1__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define SCSI_Out__1__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define SCSI_Out__1__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define SCSI_Out__1__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define SCSI_Out__1__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define SCSI_Out__1__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define SCSI_Out__1__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define SCSI_Out__1__PS CYREG_PRT15_PS +#define SCSI_Out__1__SHIFT 4 +#define SCSI_Out__1__SLW CYREG_PRT15_SLW +#define SCSI_Out__2__AG CYREG_PRT6_AG +#define SCSI_Out__2__AMUX CYREG_PRT6_AMUX +#define SCSI_Out__2__BIE CYREG_PRT6_BIE +#define SCSI_Out__2__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out__2__BYP CYREG_PRT6_BYP +#define SCSI_Out__2__CTL CYREG_PRT6_CTL +#define SCSI_Out__2__DM0 CYREG_PRT6_DM0 +#define SCSI_Out__2__DM1 CYREG_PRT6_DM1 +#define SCSI_Out__2__DM2 CYREG_PRT6_DM2 +#define SCSI_Out__2__DR CYREG_PRT6_DR +#define SCSI_Out__2__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out__2__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out__2__MASK 0x02u +#define SCSI_Out__2__PC CYREG_PRT6_PC1 +#define SCSI_Out__2__PORT 6u +#define SCSI_Out__2__PRT CYREG_PRT6_PRT +#define SCSI_Out__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out__2__PS CYREG_PRT6_PS +#define SCSI_Out__2__SHIFT 1 +#define SCSI_Out__2__SLW CYREG_PRT6_SLW +#define SCSI_Out__3__AG CYREG_PRT6_AG +#define SCSI_Out__3__AMUX CYREG_PRT6_AMUX +#define SCSI_Out__3__BIE CYREG_PRT6_BIE +#define SCSI_Out__3__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out__3__BYP CYREG_PRT6_BYP +#define SCSI_Out__3__CTL CYREG_PRT6_CTL +#define SCSI_Out__3__DM0 CYREG_PRT6_DM0 +#define SCSI_Out__3__DM1 CYREG_PRT6_DM1 +#define SCSI_Out__3__DM2 CYREG_PRT6_DM2 +#define SCSI_Out__3__DR CYREG_PRT6_DR +#define SCSI_Out__3__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out__3__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out__3__MASK 0x01u +#define SCSI_Out__3__PC CYREG_PRT6_PC0 +#define SCSI_Out__3__PORT 6u +#define SCSI_Out__3__PRT CYREG_PRT6_PRT +#define SCSI_Out__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out__3__PS CYREG_PRT6_PS +#define SCSI_Out__3__SHIFT 0 +#define SCSI_Out__3__SLW CYREG_PRT6_SLW +#define SCSI_Out__4__AG CYREG_PRT4_AG +#define SCSI_Out__4__AMUX CYREG_PRT4_AMUX +#define SCSI_Out__4__BIE CYREG_PRT4_BIE +#define SCSI_Out__4__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Out__4__BYP CYREG_PRT4_BYP +#define SCSI_Out__4__CTL CYREG_PRT4_CTL +#define SCSI_Out__4__DM0 CYREG_PRT4_DM0 +#define SCSI_Out__4__DM1 CYREG_PRT4_DM1 +#define SCSI_Out__4__DM2 CYREG_PRT4_DM2 +#define SCSI_Out__4__DR CYREG_PRT4_DR +#define SCSI_Out__4__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Out__4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Out__4__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Out__4__MASK 0x20u +#define SCSI_Out__4__PC CYREG_PRT4_PC5 +#define SCSI_Out__4__PORT 4u +#define SCSI_Out__4__PRT CYREG_PRT4_PRT +#define SCSI_Out__4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Out__4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Out__4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Out__4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Out__4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Out__4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Out__4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Out__4__PS CYREG_PRT4_PS +#define SCSI_Out__4__SHIFT 5 +#define SCSI_Out__4__SLW CYREG_PRT4_SLW +#define SCSI_Out__5__AG CYREG_PRT4_AG +#define SCSI_Out__5__AMUX CYREG_PRT4_AMUX +#define SCSI_Out__5__BIE CYREG_PRT4_BIE +#define SCSI_Out__5__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Out__5__BYP CYREG_PRT4_BYP +#define SCSI_Out__5__CTL CYREG_PRT4_CTL +#define SCSI_Out__5__DM0 CYREG_PRT4_DM0 +#define SCSI_Out__5__DM1 CYREG_PRT4_DM1 +#define SCSI_Out__5__DM2 CYREG_PRT4_DM2 +#define SCSI_Out__5__DR CYREG_PRT4_DR +#define SCSI_Out__5__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Out__5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Out__5__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Out__5__MASK 0x10u +#define SCSI_Out__5__PC CYREG_PRT4_PC4 +#define SCSI_Out__5__PORT 4u +#define SCSI_Out__5__PRT CYREG_PRT4_PRT +#define SCSI_Out__5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Out__5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Out__5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Out__5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Out__5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Out__5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Out__5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Out__5__PS CYREG_PRT4_PS +#define SCSI_Out__5__SHIFT 4 +#define SCSI_Out__5__SLW CYREG_PRT4_SLW +#define SCSI_Out__6__AG CYREG_PRT0_AG +#define SCSI_Out__6__AMUX CYREG_PRT0_AMUX +#define SCSI_Out__6__BIE CYREG_PRT0_BIE +#define SCSI_Out__6__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Out__6__BYP CYREG_PRT0_BYP +#define SCSI_Out__6__CTL CYREG_PRT0_CTL +#define SCSI_Out__6__DM0 CYREG_PRT0_DM0 +#define SCSI_Out__6__DM1 CYREG_PRT0_DM1 +#define SCSI_Out__6__DM2 CYREG_PRT0_DM2 +#define SCSI_Out__6__DR CYREG_PRT0_DR +#define SCSI_Out__6__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Out__6__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Out__6__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Out__6__MASK 0x80u +#define SCSI_Out__6__PC CYREG_PRT0_PC7 +#define SCSI_Out__6__PORT 0u +#define SCSI_Out__6__PRT CYREG_PRT0_PRT +#define SCSI_Out__6__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Out__6__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Out__6__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Out__6__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Out__6__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Out__6__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Out__6__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Out__6__PS CYREG_PRT0_PS +#define SCSI_Out__6__SHIFT 7 +#define SCSI_Out__6__SLW CYREG_PRT0_SLW +#define SCSI_Out__7__AG CYREG_PRT0_AG +#define SCSI_Out__7__AMUX CYREG_PRT0_AMUX +#define SCSI_Out__7__BIE CYREG_PRT0_BIE +#define SCSI_Out__7__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Out__7__BYP CYREG_PRT0_BYP +#define SCSI_Out__7__CTL CYREG_PRT0_CTL +#define SCSI_Out__7__DM0 CYREG_PRT0_DM0 +#define SCSI_Out__7__DM1 CYREG_PRT0_DM1 +#define SCSI_Out__7__DM2 CYREG_PRT0_DM2 +#define SCSI_Out__7__DR CYREG_PRT0_DR +#define SCSI_Out__7__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Out__7__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Out__7__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Out__7__MASK 0x40u +#define SCSI_Out__7__PC CYREG_PRT0_PC6 +#define SCSI_Out__7__PORT 0u +#define SCSI_Out__7__PRT CYREG_PRT0_PRT +#define SCSI_Out__7__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Out__7__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Out__7__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Out__7__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Out__7__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Out__7__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Out__7__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Out__7__PS CYREG_PRT0_PS +#define SCSI_Out__7__SHIFT 6 +#define SCSI_Out__7__SLW CYREG_PRT0_SLW +#define SCSI_Out__8__AG CYREG_PRT0_AG +#define SCSI_Out__8__AMUX CYREG_PRT0_AMUX +#define SCSI_Out__8__BIE CYREG_PRT0_BIE +#define SCSI_Out__8__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Out__8__BYP CYREG_PRT0_BYP +#define SCSI_Out__8__CTL CYREG_PRT0_CTL +#define SCSI_Out__8__DM0 CYREG_PRT0_DM0 +#define SCSI_Out__8__DM1 CYREG_PRT0_DM1 +#define SCSI_Out__8__DM2 CYREG_PRT0_DM2 +#define SCSI_Out__8__DR CYREG_PRT0_DR +#define SCSI_Out__8__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Out__8__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Out__8__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Out__8__MASK 0x08u +#define SCSI_Out__8__PC CYREG_PRT0_PC3 +#define SCSI_Out__8__PORT 0u +#define SCSI_Out__8__PRT CYREG_PRT0_PRT +#define SCSI_Out__8__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Out__8__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Out__8__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Out__8__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Out__8__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Out__8__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Out__8__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Out__8__PS CYREG_PRT0_PS +#define SCSI_Out__8__SHIFT 3 +#define SCSI_Out__8__SLW CYREG_PRT0_SLW +#define SCSI_Out__9__AG CYREG_PRT0_AG +#define SCSI_Out__9__AMUX CYREG_PRT0_AMUX +#define SCSI_Out__9__BIE CYREG_PRT0_BIE +#define SCSI_Out__9__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Out__9__BYP CYREG_PRT0_BYP +#define SCSI_Out__9__CTL CYREG_PRT0_CTL +#define SCSI_Out__9__DM0 CYREG_PRT0_DM0 +#define SCSI_Out__9__DM1 CYREG_PRT0_DM1 +#define SCSI_Out__9__DM2 CYREG_PRT0_DM2 +#define SCSI_Out__9__DR CYREG_PRT0_DR +#define SCSI_Out__9__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Out__9__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Out__9__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Out__9__MASK 0x04u +#define SCSI_Out__9__PC CYREG_PRT0_PC2 +#define SCSI_Out__9__PORT 0u +#define SCSI_Out__9__PRT CYREG_PRT0_PRT +#define SCSI_Out__9__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Out__9__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Out__9__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Out__9__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Out__9__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Out__9__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Out__9__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Out__9__PS CYREG_PRT0_PS +#define SCSI_Out__9__SHIFT 2 +#define SCSI_Out__9__SLW CYREG_PRT0_SLW +#define SCSI_Out__ACK__AG CYREG_PRT6_AG +#define SCSI_Out__ACK__AMUX CYREG_PRT6_AMUX +#define SCSI_Out__ACK__BIE CYREG_PRT6_BIE +#define SCSI_Out__ACK__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out__ACK__BYP CYREG_PRT6_BYP +#define SCSI_Out__ACK__CTL CYREG_PRT6_CTL +#define SCSI_Out__ACK__DM0 CYREG_PRT6_DM0 +#define SCSI_Out__ACK__DM1 CYREG_PRT6_DM1 +#define SCSI_Out__ACK__DM2 CYREG_PRT6_DM2 +#define SCSI_Out__ACK__DR CYREG_PRT6_DR +#define SCSI_Out__ACK__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out__ACK__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out__ACK__MASK 0x01u +#define SCSI_Out__ACK__PC CYREG_PRT6_PC0 +#define SCSI_Out__ACK__PORT 6u +#define SCSI_Out__ACK__PRT CYREG_PRT6_PRT +#define SCSI_Out__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out__ACK__PS CYREG_PRT6_PS +#define SCSI_Out__ACK__SHIFT 0 +#define SCSI_Out__ACK__SLW CYREG_PRT6_SLW +#define SCSI_Out__ATN__AG CYREG_PRT15_AG +#define SCSI_Out__ATN__AMUX CYREG_PRT15_AMUX +#define SCSI_Out__ATN__BIE CYREG_PRT15_BIE +#define SCSI_Out__ATN__BIT_MASK CYREG_PRT15_BIT_MASK +#define SCSI_Out__ATN__BYP CYREG_PRT15_BYP +#define SCSI_Out__ATN__CTL CYREG_PRT15_CTL +#define SCSI_Out__ATN__DM0 CYREG_PRT15_DM0 +#define SCSI_Out__ATN__DM1 CYREG_PRT15_DM1 +#define SCSI_Out__ATN__DM2 CYREG_PRT15_DM2 +#define SCSI_Out__ATN__DR CYREG_PRT15_DR +#define SCSI_Out__ATN__INP_DIS CYREG_PRT15_INP_DIS +#define SCSI_Out__ATN__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define SCSI_Out__ATN__LCD_EN CYREG_PRT15_LCD_EN +#define SCSI_Out__ATN__MASK 0x10u +#define SCSI_Out__ATN__PC CYREG_IO_PC_PRT15_PC4 +#define SCSI_Out__ATN__PORT 15u +#define SCSI_Out__ATN__PRT CYREG_PRT15_PRT +#define SCSI_Out__ATN__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define SCSI_Out__ATN__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define SCSI_Out__ATN__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define SCSI_Out__ATN__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define SCSI_Out__ATN__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define SCSI_Out__ATN__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define SCSI_Out__ATN__PS CYREG_PRT15_PS +#define SCSI_Out__ATN__SHIFT 4 +#define SCSI_Out__ATN__SLW CYREG_PRT15_SLW +#define SCSI_Out__BSY__AG CYREG_PRT6_AG +#define SCSI_Out__BSY__AMUX CYREG_PRT6_AMUX +#define SCSI_Out__BSY__BIE CYREG_PRT6_BIE +#define SCSI_Out__BSY__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out__BSY__BYP CYREG_PRT6_BYP +#define SCSI_Out__BSY__CTL CYREG_PRT6_CTL +#define SCSI_Out__BSY__DM0 CYREG_PRT6_DM0 +#define SCSI_Out__BSY__DM1 CYREG_PRT6_DM1 +#define SCSI_Out__BSY__DM2 CYREG_PRT6_DM2 +#define SCSI_Out__BSY__DR CYREG_PRT6_DR +#define SCSI_Out__BSY__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out__BSY__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out__BSY__MASK 0x02u +#define SCSI_Out__BSY__PC CYREG_PRT6_PC1 +#define SCSI_Out__BSY__PORT 6u +#define SCSI_Out__BSY__PRT CYREG_PRT6_PRT +#define SCSI_Out__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out__BSY__PS CYREG_PRT6_PS +#define SCSI_Out__BSY__SHIFT 1 +#define SCSI_Out__BSY__SLW CYREG_PRT6_SLW +#define SCSI_Out__CD__AG CYREG_PRT0_AG +#define SCSI_Out__CD__AMUX CYREG_PRT0_AMUX +#define SCSI_Out__CD__BIE CYREG_PRT0_BIE +#define SCSI_Out__CD__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Out__CD__BYP CYREG_PRT0_BYP +#define SCSI_Out__CD__CTL CYREG_PRT0_CTL +#define SCSI_Out__CD__DM0 CYREG_PRT0_DM0 +#define SCSI_Out__CD__DM1 CYREG_PRT0_DM1 +#define SCSI_Out__CD__DM2 CYREG_PRT0_DM2 +#define SCSI_Out__CD__DR CYREG_PRT0_DR +#define SCSI_Out__CD__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Out__CD__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Out__CD__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Out__CD__MASK 0x40u +#define SCSI_Out__CD__PC CYREG_PRT0_PC6 +#define SCSI_Out__CD__PORT 0u +#define SCSI_Out__CD__PRT CYREG_PRT0_PRT +#define SCSI_Out__CD__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Out__CD__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Out__CD__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Out__CD__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Out__CD__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Out__CD__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Out__CD__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Out__CD__PS CYREG_PRT0_PS +#define SCSI_Out__CD__SHIFT 6 +#define SCSI_Out__CD__SLW CYREG_PRT0_SLW +#define SCSI_Out__DBP_raw__AG CYREG_PRT15_AG +#define SCSI_Out__DBP_raw__AMUX CYREG_PRT15_AMUX +#define SCSI_Out__DBP_raw__BIE CYREG_PRT15_BIE +#define SCSI_Out__DBP_raw__BIT_MASK CYREG_PRT15_BIT_MASK +#define SCSI_Out__DBP_raw__BYP CYREG_PRT15_BYP +#define SCSI_Out__DBP_raw__CTL CYREG_PRT15_CTL +#define SCSI_Out__DBP_raw__DM0 CYREG_PRT15_DM0 +#define SCSI_Out__DBP_raw__DM1 CYREG_PRT15_DM1 +#define SCSI_Out__DBP_raw__DM2 CYREG_PRT15_DM2 +#define SCSI_Out__DBP_raw__DR CYREG_PRT15_DR +#define SCSI_Out__DBP_raw__INP_DIS CYREG_PRT15_INP_DIS +#define SCSI_Out__DBP_raw__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define SCSI_Out__DBP_raw__LCD_EN CYREG_PRT15_LCD_EN +#define SCSI_Out__DBP_raw__MASK 0x20u +#define SCSI_Out__DBP_raw__PC CYREG_IO_PC_PRT15_PC5 +#define SCSI_Out__DBP_raw__PORT 15u +#define SCSI_Out__DBP_raw__PRT CYREG_PRT15_PRT +#define SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define SCSI_Out__DBP_raw__PS CYREG_PRT15_PS +#define SCSI_Out__DBP_raw__SHIFT 5 +#define SCSI_Out__DBP_raw__SLW CYREG_PRT15_SLW +#define SCSI_Out__IO_raw__AG CYREG_PRT0_AG +#define SCSI_Out__IO_raw__AMUX CYREG_PRT0_AMUX +#define SCSI_Out__IO_raw__BIE CYREG_PRT0_BIE +#define SCSI_Out__IO_raw__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Out__IO_raw__BYP CYREG_PRT0_BYP +#define SCSI_Out__IO_raw__CTL CYREG_PRT0_CTL +#define SCSI_Out__IO_raw__DM0 CYREG_PRT0_DM0 +#define SCSI_Out__IO_raw__DM1 CYREG_PRT0_DM1 +#define SCSI_Out__IO_raw__DM2 CYREG_PRT0_DM2 +#define SCSI_Out__IO_raw__DR CYREG_PRT0_DR +#define SCSI_Out__IO_raw__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Out__IO_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Out__IO_raw__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Out__IO_raw__MASK 0x04u +#define SCSI_Out__IO_raw__PC CYREG_PRT0_PC2 +#define SCSI_Out__IO_raw__PORT 0u +#define SCSI_Out__IO_raw__PRT CYREG_PRT0_PRT +#define SCSI_Out__IO_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Out__IO_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Out__IO_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Out__IO_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Out__IO_raw__PS CYREG_PRT0_PS +#define SCSI_Out__IO_raw__SHIFT 2 +#define SCSI_Out__IO_raw__SLW CYREG_PRT0_SLW +#define SCSI_Out__MSG__AG CYREG_PRT4_AG +#define SCSI_Out__MSG__AMUX CYREG_PRT4_AMUX +#define SCSI_Out__MSG__BIE CYREG_PRT4_BIE +#define SCSI_Out__MSG__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Out__MSG__BYP CYREG_PRT4_BYP +#define SCSI_Out__MSG__CTL CYREG_PRT4_CTL +#define SCSI_Out__MSG__DM0 CYREG_PRT4_DM0 +#define SCSI_Out__MSG__DM1 CYREG_PRT4_DM1 +#define SCSI_Out__MSG__DM2 CYREG_PRT4_DM2 +#define SCSI_Out__MSG__DR CYREG_PRT4_DR +#define SCSI_Out__MSG__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Out__MSG__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Out__MSG__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Out__MSG__MASK 0x10u +#define SCSI_Out__MSG__PC CYREG_PRT4_PC4 +#define SCSI_Out__MSG__PORT 4u +#define SCSI_Out__MSG__PRT CYREG_PRT4_PRT +#define SCSI_Out__MSG__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Out__MSG__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Out__MSG__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Out__MSG__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Out__MSG__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Out__MSG__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Out__MSG__PS CYREG_PRT4_PS +#define SCSI_Out__MSG__SHIFT 4 +#define SCSI_Out__MSG__SLW CYREG_PRT4_SLW +#define SCSI_Out__REQ__AG CYREG_PRT0_AG +#define SCSI_Out__REQ__AMUX CYREG_PRT0_AMUX +#define SCSI_Out__REQ__BIE CYREG_PRT0_BIE +#define SCSI_Out__REQ__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Out__REQ__BYP CYREG_PRT0_BYP +#define SCSI_Out__REQ__CTL CYREG_PRT0_CTL +#define SCSI_Out__REQ__DM0 CYREG_PRT0_DM0 +#define SCSI_Out__REQ__DM1 CYREG_PRT0_DM1 +#define SCSI_Out__REQ__DM2 CYREG_PRT0_DM2 +#define SCSI_Out__REQ__DR CYREG_PRT0_DR +#define SCSI_Out__REQ__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Out__REQ__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Out__REQ__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Out__REQ__MASK 0x08u +#define SCSI_Out__REQ__PC CYREG_PRT0_PC3 +#define SCSI_Out__REQ__PORT 0u +#define SCSI_Out__REQ__PRT CYREG_PRT0_PRT +#define SCSI_Out__REQ__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Out__REQ__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Out__REQ__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Out__REQ__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Out__REQ__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Out__REQ__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Out__REQ__PS CYREG_PRT0_PS +#define SCSI_Out__REQ__SHIFT 3 +#define SCSI_Out__REQ__SLW CYREG_PRT0_SLW +#define SCSI_Out__RST__AG CYREG_PRT4_AG +#define SCSI_Out__RST__AMUX CYREG_PRT4_AMUX +#define SCSI_Out__RST__BIE CYREG_PRT4_BIE +#define SCSI_Out__RST__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Out__RST__BYP CYREG_PRT4_BYP +#define SCSI_Out__RST__CTL CYREG_PRT4_CTL +#define SCSI_Out__RST__DM0 CYREG_PRT4_DM0 +#define SCSI_Out__RST__DM1 CYREG_PRT4_DM1 +#define SCSI_Out__RST__DM2 CYREG_PRT4_DM2 +#define SCSI_Out__RST__DR CYREG_PRT4_DR +#define SCSI_Out__RST__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Out__RST__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Out__RST__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Out__RST__MASK 0x20u +#define SCSI_Out__RST__PC CYREG_PRT4_PC5 +#define SCSI_Out__RST__PORT 4u +#define SCSI_Out__RST__PRT CYREG_PRT4_PRT +#define SCSI_Out__RST__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Out__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Out__RST__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Out__RST__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Out__RST__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Out__RST__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Out__RST__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Out__RST__PS CYREG_PRT4_PS +#define SCSI_Out__RST__SHIFT 5 +#define SCSI_Out__RST__SLW CYREG_PRT4_SLW +#define SCSI_Out__SEL__AG CYREG_PRT0_AG +#define SCSI_Out__SEL__AMUX CYREG_PRT0_AMUX +#define SCSI_Out__SEL__BIE CYREG_PRT0_BIE +#define SCSI_Out__SEL__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Out__SEL__BYP CYREG_PRT0_BYP +#define SCSI_Out__SEL__CTL CYREG_PRT0_CTL +#define SCSI_Out__SEL__DM0 CYREG_PRT0_DM0 +#define SCSI_Out__SEL__DM1 CYREG_PRT0_DM1 +#define SCSI_Out__SEL__DM2 CYREG_PRT0_DM2 +#define SCSI_Out__SEL__DR CYREG_PRT0_DR +#define SCSI_Out__SEL__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Out__SEL__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Out__SEL__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Out__SEL__MASK 0x80u +#define SCSI_Out__SEL__PC CYREG_PRT0_PC7 +#define SCSI_Out__SEL__PORT 0u +#define SCSI_Out__SEL__PRT CYREG_PRT0_PRT +#define SCSI_Out__SEL__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Out__SEL__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Out__SEL__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Out__SEL__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Out__SEL__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Out__SEL__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Out__SEL__PS CYREG_PRT0_PS +#define SCSI_Out__SEL__SHIFT 7 +#define SCSI_Out__SEL__SLW CYREG_PRT0_SLW + +/* USBFS_Dm */ +#define USBFS_Dm__0__MASK 0x80u +#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1 +#define USBFS_Dm__0__PORT 15u +#define USBFS_Dm__0__SHIFT 7 +#define USBFS_Dm__AG CYREG_PRT15_AG +#define USBFS_Dm__AMUX CYREG_PRT15_AMUX +#define USBFS_Dm__BIE CYREG_PRT15_BIE +#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK +#define USBFS_Dm__BYP CYREG_PRT15_BYP +#define USBFS_Dm__CTL CYREG_PRT15_CTL +#define USBFS_Dm__DM0 CYREG_PRT15_DM0 +#define USBFS_Dm__DM1 CYREG_PRT15_DM1 +#define USBFS_Dm__DM2 CYREG_PRT15_DM2 +#define USBFS_Dm__DR CYREG_PRT15_DR +#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS +#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN +#define USBFS_Dm__MASK 0x80u +#define USBFS_Dm__PORT 15u +#define USBFS_Dm__PRT CYREG_PRT15_PRT +#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define USBFS_Dm__PS CYREG_PRT15_PS +#define USBFS_Dm__SHIFT 7 +#define USBFS_Dm__SLW CYREG_PRT15_SLW + +/* USBFS_Dp */ +#define USBFS_Dp__0__MASK 0x40u +#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0 +#define USBFS_Dp__0__PORT 15u +#define USBFS_Dp__0__SHIFT 6 +#define USBFS_Dp__AG CYREG_PRT15_AG +#define USBFS_Dp__AMUX CYREG_PRT15_AMUX +#define USBFS_Dp__BIE CYREG_PRT15_BIE +#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK +#define USBFS_Dp__BYP CYREG_PRT15_BYP +#define USBFS_Dp__CTL CYREG_PRT15_CTL +#define USBFS_Dp__DM0 CYREG_PRT15_DM0 +#define USBFS_Dp__DM1 CYREG_PRT15_DM1 +#define USBFS_Dp__DM2 CYREG_PRT15_DM2 +#define USBFS_Dp__DR CYREG_PRT15_DR +#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS +#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT +#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN +#define USBFS_Dp__MASK 0x40u +#define USBFS_Dp__PORT 15u +#define USBFS_Dp__PRT CYREG_PRT15_PRT +#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define USBFS_Dp__PS CYREG_PRT15_PS +#define USBFS_Dp__SHIFT 6 +#define USBFS_Dp__SLW CYREG_PRT15_SLW +#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15 + +/* LED */ +#define LED__0__MASK 0x02u +#define LED__0__PC CYREG_PRT0_PC1 +#define LED__0__PORT 0u +#define LED__0__SHIFT 1 +#define LED__AG CYREG_PRT0_AG +#define LED__AMUX CYREG_PRT0_AMUX +#define LED__BIE CYREG_PRT0_BIE +#define LED__BIT_MASK CYREG_PRT0_BIT_MASK +#define LED__BYP CYREG_PRT0_BYP +#define LED__CTL CYREG_PRT0_CTL +#define LED__DM0 CYREG_PRT0_DM0 +#define LED__DM1 CYREG_PRT0_DM1 +#define LED__DM2 CYREG_PRT0_DM2 +#define LED__DR CYREG_PRT0_DR +#define LED__INP_DIS CYREG_PRT0_INP_DIS +#define LED__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define LED__LCD_EN CYREG_PRT0_LCD_EN +#define LED__MASK 0x02u +#define LED__PORT 0u +#define LED__PRT CYREG_PRT0_PRT +#define LED__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define LED__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define LED__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define LED__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define LED__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define LED__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define LED__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define LED__PS CYREG_PRT0_PS +#define LED__SHIFT 1 +#define LED__SLW CYREG_PRT0_SLW + +/* Miscellaneous */ +/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */ +#define CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO 0 +#define CYDEV_DEBUGGING_DPS_SWD_SWV 6 +#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0 +#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0 +#define CYDEV_CONFIG_FASTBOOT_ENABLED 1 +#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u +#define CYDEV_CHIP_MEMBER_5B 4u +#define CYDEV_CHIP_FAMILY_PSOC5 3u +#define CYDEV_CHIP_DIE_PSOC5LP 4u +#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_DIE_PSOC5LP +#define CYDEV_BOOTLOADER_IO_COMP_USBFS 1 +#define BCLK__BUS_CLK__HZ 64000000U +#define BCLK__BUS_CLK__KHZ 64000U +#define BCLK__BUS_CLK__MHZ 64U +#define CYDEV_BOOTLOADER_APPLICATIONS 1u +#define CYDEV_BOOTLOADER_CHECKSUM_BASIC 0 +#define CYDEV_BOOTLOADER_CHECKSUM_CRC 1 +#define CYDEV_BOOTLOADER_IO_COMP CYDEV_BOOTLOADER_IO_COMP_USBFS +#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT +#define CYDEV_CHIP_DIE_LEOPARD 1u +#define CYDEV_CHIP_DIE_PANTHER 3u +#define CYDEV_CHIP_DIE_PSOC4A 2u +#define CYDEV_CHIP_DIE_UNKNOWN 0u +#define CYDEV_CHIP_FAMILY_PSOC3 1u +#define CYDEV_CHIP_FAMILY_PSOC4 2u +#define CYDEV_CHIP_FAMILY_UNKNOWN 0u +#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5 +#define CYDEV_CHIP_JTAG_ID 0x2E133069u +#define CYDEV_CHIP_MEMBER_3A 1u +#define CYDEV_CHIP_MEMBER_4A 2u +#define CYDEV_CHIP_MEMBER_5A 3u +#define CYDEV_CHIP_MEMBER_UNKNOWN 0u +#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B +#define CYDEV_CHIP_REVISION_3A_ES1 0u +#define CYDEV_CHIP_REVISION_3A_ES2 1u +#define CYDEV_CHIP_REVISION_3A_ES3 3u +#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u +#define CYDEV_CHIP_REVISION_4A_ES0 17u +#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u +#define CYDEV_CHIP_REVISION_5A_ES0 0u +#define CYDEV_CHIP_REVISION_5A_ES1 1u +#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u +#define CYDEV_CHIP_REVISION_5B_ES0 0u +#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_5B_PRODUCTION +#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REV_PSOC5LP_PRODUCTION +#define CYDEV_CHIP_REV_LEOPARD_ES1 0u +#define CYDEV_CHIP_REV_LEOPARD_ES2 1u +#define CYDEV_CHIP_REV_LEOPARD_ES3 3u +#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u +#define CYDEV_CHIP_REV_PANTHER_ES0 0u +#define CYDEV_CHIP_REV_PANTHER_ES1 1u +#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u +#define CYDEV_CHIP_REV_PSOC4A_ES0 17u +#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u +#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u +#define CYDEV_CONFIGURATION_COMPRESSED 1 +#define CYDEV_CONFIGURATION_DMA 0 +#define CYDEV_CONFIGURATION_ECC 0 +#define CYDEV_CONFIGURATION_IMOENABLED CYDEV_CONFIG_FASTBOOT_ENABLED +#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED +#define CYDEV_CONFIGURATION_MODE_DMA 2 +#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1 +#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn +#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1 +#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2 +#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD_SWV +#define CYDEV_DEBUGGING_DPS_Disable 3 +#define CYDEV_DEBUGGING_DPS_JTAG_4 1 +#define CYDEV_DEBUGGING_DPS_JTAG_5 0 +#define CYDEV_DEBUGGING_DPS_SWD 2 +#define CYDEV_DEBUGGING_ENABLE 1 +#define CYDEV_DEBUGGING_XRES 0 +#define CYDEV_DEBUG_ENABLE_MASK 0x20u +#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG +#define CYDEV_DMA_CHANNELS_AVAILABLE 24u +#define CYDEV_ECC_ENABLE 0 +#define CYDEV_HEAP_SIZE 0x0800 +#define CYDEV_INSTRUCT_CACHE_ENABLED 1 +#define CYDEV_INTR_RISING 0x00000000u +#define CYDEV_PROJ_TYPE 1 +#define CYDEV_PROJ_TYPE_BOOTLOADER 1 +#define CYDEV_PROJ_TYPE_LOADABLE 2 +#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3 +#define CYDEV_PROJ_TYPE_STANDARD 0 +#define CYDEV_PROTECTION_ENABLE 0 +#define CYDEV_STACK_SIZE 0x2000 +#define CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP +#define CYDEV_USE_BUNDLED_CMSIS 1 +#define CYDEV_VARIABLE_VDDA 0 +#define CYDEV_VDDA 5.0 +#define CYDEV_VDDA_MV 5000 +#define CYDEV_VDDD 5.0 +#define CYDEV_VDDD_MV 5000 +#define CYDEV_VDDIO0 5.0 +#define CYDEV_VDDIO0_MV 5000 +#define CYDEV_VDDIO1 5.0 +#define CYDEV_VDDIO1_MV 5000 +#define CYDEV_VDDIO2 5.0 +#define CYDEV_VDDIO2_MV 5000 +#define CYDEV_VDDIO3 5.0 +#define CYDEV_VDDIO3_MV 5000 +#define CYDEV_VIO0 5 +#define CYDEV_VIO0_MV 5000 +#define CYDEV_VIO1 5 +#define CYDEV_VIO1_MV 5000 +#define CYDEV_VIO2 5 +#define CYDEV_VIO2_MV 5000 +#define CYDEV_VIO3 5 +#define CYDEV_VIO3_MV 5000 +#define CyBtldr_Custom_Interface CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO +#define CyBtldr_USBFS CYDEV_BOOTLOADER_IO_COMP_USBFS +#define DMA_CHANNELS_USED__MASK0 0x00000000u +#define CYDEV_BOOTLOADER_ENABLE 1 + +#endif /* INCLUDED_CYFITTER_H */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c new file mode 100755 index 00000000..88469572 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -0,0 +1,444 @@ +/******************************************************************************* +* FILENAME: cyfitter_cfg.c +* PSoC Creator 3.0 Component Pack 7 +* +* Description: +* This file is automatically generated by PSoC Creator with device +* initialization code. Except for the user defined sections in +* CyClockStartupError(), this file should not be modified. +* +******************************************************************************** +* Copyright 2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#define CY_NEED_CYCLOCKSTARTUPERROR 1 + + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) + #define CYPACKED + #define CYPACKED_ATTR __attribute__ ((packed)) + #define CYALIGNED __attribute__ ((aligned)) + #define CY_CFG_UNUSED __attribute__ ((unused)) + #define CY_CFG_SECTION __attribute__ ((section(".psocinit"))) + + #if defined(__ARMCC_VERSION) + #define CY_CFG_MEMORY_BARRIER() __memory_changed() + #else + #define CY_CFG_MEMORY_BARRIER() __sync_synchronize() + #endif + +#elif defined(__ICCARM__) + #include + + #define CYPACKED __packed + #define CYPACKED_ATTR + #define CYALIGNED _Pragma("data_alignment=4") + #define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177") + #define CY_CFG_SECTION _Pragma("location=\".psocinit\"") + + #define CY_CFG_MEMORY_BARRIER() __DMB() + +#else + #error Unsupported toolchain +#endif + + +CY_CFG_UNUSED +static void CYMEMZERO(void *s, size_t n); +CY_CFG_UNUSED +static void CYMEMZERO(void *s, size_t n) +{ + (void)memset(s, 0, n); +} +CY_CFG_UNUSED +static void CYCONFIGCPY(void *dest, const void *src, size_t n); +CY_CFG_UNUSED +static void CYCONFIGCPY(void *dest, const void *src, size_t n) +{ + (void)memcpy(dest, src, n); +} +CY_CFG_UNUSED +static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n); +CY_CFG_UNUSED +static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n) +{ + (void)memcpy(dest, src, n); +} + + + +/* Clock startup error codes */ +#define CYCLOCKSTART_NO_ERROR 0u +#define CYCLOCKSTART_XTAL_ERROR 1u +#define CYCLOCKSTART_32KHZ_ERROR 2u +#define CYCLOCKSTART_PLL_ERROR 3u + +#ifdef CY_NEED_CYCLOCKSTARTUPERROR +/******************************************************************************* +* Function Name: CyClockStartupError +******************************************************************************** +* Summary: +* If an error is encountered during clock configuration (crystal startup error, +* PLL lock error, etc.), the system will end up here. Unless reimplemented by +* the customer, this function will stop in an infinite loop. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +CY_CFG_UNUSED +static void CyClockStartupError(uint8 errorCode); +CY_CFG_UNUSED +static void CyClockStartupError(uint8 errorCode) +{ + /* To remove the compiler warning if errorCode not used. */ + errorCode = errorCode; + + /* `#START CyClockStartupError` */ + + /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */ + /* we will end up here to allow the customer to implement something to */ + /* deal with the clock condition. */ + + /* `#END` */ + + /* If nothing else, stop here since the clocks have not started */ + /* correctly. */ + while(1) {} +} +#endif + +#define CY_CFG_BASE_ADDR_COUNT 12u +CYPACKED typedef struct +{ + uint8 offset; + uint8 value; +} CYPACKED_ATTR cy_cfg_addrvalue_t; + + + +/******************************************************************************* +* Function Name: cfg_write_bytes32 +******************************************************************************** +* Summary: +* This function is used for setting up the chip configuration areas that +* contain relatively sparse data. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]); +static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]) +{ + /* For 32-bit little-endian architectures */ + uint32 i, j = 0u; + for (i = 0u; i < CY_CFG_BASE_ADDR_COUNT; i++) + { + uint32 baseAddr = addr_table[i]; + uint8 count = (uint8)baseAddr; + baseAddr &= 0xFFFFFF00u; + while (count != 0u) + { + CY_SET_XTND_REG8((void CYFAR *)(baseAddr + data_table[j].offset), data_table[j].value); + j++; + count--; + } + } +} + +/******************************************************************************* +* Function Name: ClockSetup +******************************************************************************** +* +* Summary: +* Performs the initialization of all of the clocks in the device based on the +* settings in the Clock tab of the DWR. This includes enabling the requested +* clocks and setting the necessary dividers to produce the desired frequency. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +static void ClockSetup(void); +static void ClockSetup(void) +{ + uint32 timeout; + uint8 pllLock; + + + /* Configure ILO based on settings from Clock DWR */ + CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u); + + /* Configure IMO based on settings from Clock DWR */ + CY_SET_XTND_REG8((void CYFAR *)(CYREG_FASTCLK_IMO_CR), 0x52u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_TABLES_IMO_USB))); + + /* Configure PLL based on settings from Clock DWR */ + CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0818u); + CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1251u); + /* Wait up to 250us for the PLL to lock */ + pllLock = 0u; + for (timeout = 250u / 10u; (timeout > 0u) && (pllLock != 0x03u); timeout--) + { + pllLock = 0x03u & ((uint8)((uint8)pllLock << 1) | ((CY_GET_XTND_REG8((void CYFAR *)CYREG_FASTCLK_PLL_SR) & 0x01u) >> 0)); + CyDelayCycles(10u * 48u); /* Delay 10us based on 48MHz clock */ + } + /* If we ran out of time the PLL didn't lock so go to the error function */ + if (timeout == 0u) + { + CyClockStartupError(CYCLOCKSTART_PLL_ERROR); + } + + /* Configure Bus/Master Clock based on settings from Clock DWR */ + CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x0100u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x07u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG0), 0x00u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG2), 0x48u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x00u); + + /* Configure USB Clock based on settings from Clock DWR */ + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_UCFG), 0x00u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u); +} + + +/* Analog API Functions */ + + +/******************************************************************************* +* Function Name: AnalogSetDefault +******************************************************************************** +* +* Summary: +* Sets up the analog portions of the chip to default values based on chip +* configuration options from the project. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +static void AnalogSetDefault(void); +static void AnalogSetDefault(void) +{ + uint8 bg_xover_inl_trim = CY_GET_XTND_REG8((void CYFAR *)(CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM + 1u)); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT0), (bg_xover_inl_trim & 0x07u)); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT1), ((bg_xover_inl_trim >> 4) & 0x0Fu)); + CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, 0x44u); +} + + +/******************************************************************************* +* Function Name: SetAnalogRoutingPumps +******************************************************************************** +* +* Summary: +* Enables or disables the analog pumps feeding analog routing switches. +* Intended to be called at startup, based on the Vdda system configuration; +* may be called during operation when the user informs us that the Vdda voltage +* crossed the pump threshold. +* +* Parameters: +* enabled - 1 to enable the pumps, 0 to disable the pumps +* +* Return: +* void +* +*******************************************************************************/ +void SetAnalogRoutingPumps(uint8 enabled) +{ + uint8 regValue = CY_GET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0); + if (enabled != 0u) + { + regValue |= 0x00u; + } + else + { + regValue &= (uint8)~0x00u; + } + CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, regValue); +} + +#define CY_AMUX_UNUSED CYREG_BOOST_SR + + +/******************************************************************************* +* Function Name: cyfitter_cfg +******************************************************************************** +* Summary: +* This function is called by the start-up code for the selected device. It +* performs all of the necessary device configuration based on the design +* settings. This includes settings from the Design Wide Resources (DWR) such +* as Clocks and Pins as well as any component configuration that is necessary. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ + +void cyfitter_cfg(void) +{ + /* IOPINS0_0 Address: CYREG_PRT0_DR Size (bytes): 10 */ + static const uint8 CYCODE BS_IOPINS0_0_VAL[] = { + 0x02u, 0x00u, 0x00u, 0xCEu, 0xCCu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + + /* IOPINS0_8 Address: CYREG_PRT15_DR Size (bytes): 10 */ + static const uint8 CYCODE BS_IOPINS0_8_VAL[] = { + 0x00u, 0x00u, 0x00u, 0x30u, 0x30u, 0x00u, 0x00u, 0x00u, 0xC0u, 0x00u}; + + /* IOPINS0_2 Address: CYREG_PRT2_DM0 Size (bytes): 8 */ + static const uint8 CYCODE BS_IOPINS0_2_VAL[] = { + 0x00u, 0xCCu, 0xCCu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + + /* IOPINS0_3 Address: CYREG_PRT3_DM0 Size (bytes): 8 */ + static const uint8 CYCODE BS_IOPINS0_3_VAL[] = { + 0x00u, 0x3Eu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + + /* IOPINS0_4 Address: CYREG_PRT4_DM0 Size (bytes): 8 */ + static const uint8 CYCODE BS_IOPINS0_4_VAL[] = { + 0x00u, 0x30u, 0x30u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + + /* IOPINS0_5 Address: CYREG_PRT5_DM0 Size (bytes): 8 */ + static const uint8 CYCODE BS_IOPINS0_5_VAL[] = { + 0x00u, 0x03u, 0x03u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + + /* IOPINS0_6 Address: CYREG_PRT6_DM0 Size (bytes): 8 */ + static const uint8 CYCODE BS_IOPINS0_6_VAL[] = { + 0x00u, 0x33u, 0x33u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + +#ifdef CYGlobalIntDisable + /* Disable interrupts by default. Let user enable if/when they want. */ + CYGlobalIntDisable +#endif + + + /* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */ + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x01u : 0x00u)); + /* Setup clocks based on selections from Clock DWR */ + ClockSetup(); + /* Enable/Disable Debug functionality based on settings from System DWR */ + CY_SET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG, (CY_GET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG) | 0x04u)); + + { + static const uint32 CYCODE cy_cfg_addr_table[] = { + 0x40004501u, /* Base address: 0x40004500 Count: 1 */ + 0x40005202u, /* Base address: 0x40005200 Count: 2 */ + 0x40011701u, /* Base address: 0x40011700 Count: 1 */ + 0x40011901u, /* Base address: 0x40011900 Count: 1 */ + 0x40014003u, /* Base address: 0x40014000 Count: 3 */ + 0x40014102u, /* Base address: 0x40014100 Count: 2 */ + 0x40014202u, /* Base address: 0x40014200 Count: 2 */ + 0x40014302u, /* Base address: 0x40014300 Count: 2 */ + 0x40014703u, /* Base address: 0x40014700 Count: 3 */ + 0x40014803u, /* Base address: 0x40014800 Count: 3 */ + 0x40014C02u, /* Base address: 0x40014C00 Count: 2 */ + 0x40015101u, /* Base address: 0x40015100 Count: 1 */ + }; + + static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { + {0x7Eu, 0x02u}, + {0x1Cu, 0x3Eu}, + {0x7Cu, 0x40u}, + {0xEEu, 0x0Au}, + {0xEEu, 0x0Au}, + {0x33u, 0x80u}, + {0x36u, 0x40u}, + {0xCCu, 0x30u}, + {0xA6u, 0x40u}, + {0xA7u, 0x80u}, + {0xA6u, 0x40u}, + {0xA7u, 0x80u}, + {0xA6u, 0x40u}, + {0xA7u, 0x80u}, + {0x08u, 0x08u}, + {0x0Fu, 0x40u}, + {0xC2u, 0x0Cu}, + {0xAEu, 0x40u}, + {0xAFu, 0x80u}, + {0xEEu, 0x50u}, + {0xACu, 0x08u}, + {0xAFu, 0x40u}, + {0x00u, 0x0Au}, + }; + + + + CYPACKED typedef struct { + void CYFAR *address; + uint16 size; + } CYPACKED_ATTR cfg_memset_t; + + static const cfg_memset_t CYCODE cfg_memset_list [] = { + /* address, size */ + {(void CYFAR *)(CYREG_PRT1_DR), 16u}, + {(void CYFAR *)(CYREG_PRT12_DR), 16u}, + {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u}, + {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u}, + {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u}, + {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u}, + {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u}, + }; + + uint8 CYDATA i; + + /* Zero out critical memory blocks before beginning configuration */ + for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) + { + const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; + CYMEMZERO(ms->address, (uint32)(ms->size)); + } + + cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); + + /* Enable digital routing */ + CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL) | 0x02u); + CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL) | 0x02u); + + /* Enable UDB array */ + CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0) | 0x40u); + CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2) | 0x10u); + } + + /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT0_DR), (const void CYCODE *)(BS_IOPINS0_0_VAL), 10u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT15_DR), (const void CYCODE *)(BS_IOPINS0_8_VAL), 10u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT2_DM0), (const void CYCODE *)(BS_IOPINS0_2_VAL), 8u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT3_DM0), (const void CYCODE *)(BS_IOPINS0_3_VAL), 8u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT4_DM0), (const void CYCODE *)(BS_IOPINS0_4_VAL), 8u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT5_DM0), (const void CYCODE *)(BS_IOPINS0_5_VAL), 8u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT6_DM0), (const void CYCODE *)(BS_IOPINS0_6_VAL), 8u); + + /* Switch Boost to the precision bandgap reference from its internal reference */ + CY_SET_REG8((void CYXDATA *)CYREG_BOOST_CR2, (CY_GET_REG8((void CYXDATA *)CYREG_BOOST_CR2) | 0x08u)); + + /* Perform basic analog initialization to defaults */ + AnalogSetDefault(); + + /* Configure alternate active mode */ + CYCONFIGCPY((void CYFAR *)CYDEV_PM_STBY_BASE, (const void CYFAR *)CYDEV_PM_ACT_BASE, 14u); +} diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h new file mode 100755 index 00000000..191ee788 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h @@ -0,0 +1,28 @@ +/******************************************************************************* +* FILENAME: cyfitter_cfg.h +* PSoC Creator 3.0 Component Pack 7 +* +* Description: +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright 2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#ifndef CYFITTER_CFG_H +#define CYFITTER_CFG_H + +#include + +extern void cyfitter_cfg(void); + +/* Analog Set/Unset methods */ +extern void SetAnalogRoutingPumps(uint8 enabled); + + +#endif /* CYFITTER_CFG_H */ + +/*[]*/ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyfittergnu.inc new file mode 100755 index 00000000..461a6778 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -0,0 +1,1434 @@ +.ifndef INCLUDED_CYFITTERGNU_INC +.set INCLUDED_CYFITTERGNU_INC, 1 +.include "cydevicegnu.inc" +.include "cydevicegnu_trm.inc" + +/* USBFS_bus_reset */ +.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_bus_reset__INTC_MASK, 0x800000 +.set USBFS_bus_reset__INTC_NUMBER, 23 +.set USBFS_bus_reset__INTC_PRIOR_NUM, 7 +.set USBFS_bus_reset__INTC_PRIOR_REG, CYREG_NVIC_PRI_23 +.set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* USBFS_arb_int */ +.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_arb_int__INTC_MASK, 0x400000 +.set USBFS_arb_int__INTC_NUMBER, 22 +.set USBFS_arb_int__INTC_PRIOR_NUM, 7 +.set USBFS_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22 +.set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* USBFS_sof_int */ +.set USBFS_sof_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_sof_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_sof_int__INTC_MASK, 0x200000 +.set USBFS_sof_int__INTC_NUMBER, 21 +.set USBFS_sof_int__INTC_PRIOR_NUM, 7 +.set USBFS_sof_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_21 +.set USBFS_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SCSI_Out_DBx */ +.set SCSI_Out_DBx__0__AG, CYREG_PRT5_AG +.set SCSI_Out_DBx__0__AMUX, CYREG_PRT5_AMUX +.set SCSI_Out_DBx__0__BIE, CYREG_PRT5_BIE +.set SCSI_Out_DBx__0__BIT_MASK, CYREG_PRT5_BIT_MASK +.set SCSI_Out_DBx__0__BYP, CYREG_PRT5_BYP +.set SCSI_Out_DBx__0__CTL, CYREG_PRT5_CTL +.set SCSI_Out_DBx__0__DM0, CYREG_PRT5_DM0 +.set SCSI_Out_DBx__0__DM1, CYREG_PRT5_DM1 +.set SCSI_Out_DBx__0__DM2, CYREG_PRT5_DM2 +.set SCSI_Out_DBx__0__DR, CYREG_PRT5_DR +.set SCSI_Out_DBx__0__INP_DIS, CYREG_PRT5_INP_DIS +.set SCSI_Out_DBx__0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG +.set SCSI_Out_DBx__0__LCD_EN, CYREG_PRT5_LCD_EN +.set SCSI_Out_DBx__0__MASK, 0x02 +.set SCSI_Out_DBx__0__PC, CYREG_PRT5_PC1 +.set SCSI_Out_DBx__0__PORT, 5 +.set SCSI_Out_DBx__0__PRT, CYREG_PRT5_PRT +.set SCSI_Out_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL +.set SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN +.set SCSI_Out_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 +.set SCSI_Out_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 +.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 +.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 +.set SCSI_Out_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT +.set SCSI_Out_DBx__0__PS, CYREG_PRT5_PS +.set SCSI_Out_DBx__0__SHIFT, 1 +.set SCSI_Out_DBx__0__SLW, CYREG_PRT5_SLW +.set SCSI_Out_DBx__1__AG, CYREG_PRT5_AG +.set SCSI_Out_DBx__1__AMUX, CYREG_PRT5_AMUX +.set SCSI_Out_DBx__1__BIE, CYREG_PRT5_BIE +.set SCSI_Out_DBx__1__BIT_MASK, CYREG_PRT5_BIT_MASK +.set SCSI_Out_DBx__1__BYP, CYREG_PRT5_BYP +.set SCSI_Out_DBx__1__CTL, CYREG_PRT5_CTL +.set SCSI_Out_DBx__1__DM0, CYREG_PRT5_DM0 +.set SCSI_Out_DBx__1__DM1, CYREG_PRT5_DM1 +.set SCSI_Out_DBx__1__DM2, CYREG_PRT5_DM2 +.set SCSI_Out_DBx__1__DR, CYREG_PRT5_DR +.set SCSI_Out_DBx__1__INP_DIS, CYREG_PRT5_INP_DIS +.set SCSI_Out_DBx__1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG +.set SCSI_Out_DBx__1__LCD_EN, CYREG_PRT5_LCD_EN +.set SCSI_Out_DBx__1__MASK, 0x01 +.set SCSI_Out_DBx__1__PC, CYREG_PRT5_PC0 +.set SCSI_Out_DBx__1__PORT, 5 +.set SCSI_Out_DBx__1__PRT, CYREG_PRT5_PRT +.set SCSI_Out_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL +.set SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN +.set SCSI_Out_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 +.set SCSI_Out_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 +.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 +.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 +.set SCSI_Out_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT +.set SCSI_Out_DBx__1__PS, CYREG_PRT5_PS +.set SCSI_Out_DBx__1__SHIFT, 0 +.set SCSI_Out_DBx__1__SLW, CYREG_PRT5_SLW +.set SCSI_Out_DBx__2__AG, CYREG_PRT6_AG +.set SCSI_Out_DBx__2__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out_DBx__2__BIE, CYREG_PRT6_BIE +.set SCSI_Out_DBx__2__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out_DBx__2__BYP, CYREG_PRT6_BYP +.set SCSI_Out_DBx__2__CTL, CYREG_PRT6_CTL +.set SCSI_Out_DBx__2__DM0, CYREG_PRT6_DM0 +.set SCSI_Out_DBx__2__DM1, CYREG_PRT6_DM1 +.set SCSI_Out_DBx__2__DM2, CYREG_PRT6_DM2 +.set SCSI_Out_DBx__2__DR, CYREG_PRT6_DR +.set SCSI_Out_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out_DBx__2__MASK, 0x20 +.set SCSI_Out_DBx__2__PC, CYREG_PRT6_PC5 +.set SCSI_Out_DBx__2__PORT, 6 +.set SCSI_Out_DBx__2__PRT, CYREG_PRT6_PRT +.set SCSI_Out_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out_DBx__2__PS, CYREG_PRT6_PS +.set SCSI_Out_DBx__2__SHIFT, 5 +.set SCSI_Out_DBx__2__SLW, CYREG_PRT6_SLW +.set SCSI_Out_DBx__3__AG, CYREG_PRT6_AG +.set SCSI_Out_DBx__3__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out_DBx__3__BIE, CYREG_PRT6_BIE +.set SCSI_Out_DBx__3__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out_DBx__3__BYP, CYREG_PRT6_BYP +.set SCSI_Out_DBx__3__CTL, CYREG_PRT6_CTL +.set SCSI_Out_DBx__3__DM0, CYREG_PRT6_DM0 +.set SCSI_Out_DBx__3__DM1, CYREG_PRT6_DM1 +.set SCSI_Out_DBx__3__DM2, CYREG_PRT6_DM2 +.set SCSI_Out_DBx__3__DR, CYREG_PRT6_DR +.set SCSI_Out_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out_DBx__3__MASK, 0x10 +.set SCSI_Out_DBx__3__PC, CYREG_PRT6_PC4 +.set SCSI_Out_DBx__3__PORT, 6 +.set SCSI_Out_DBx__3__PRT, CYREG_PRT6_PRT +.set SCSI_Out_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out_DBx__3__PS, CYREG_PRT6_PS +.set SCSI_Out_DBx__3__SHIFT, 4 +.set SCSI_Out_DBx__3__SLW, CYREG_PRT6_SLW +.set SCSI_Out_DBx__4__AG, CYREG_PRT2_AG +.set SCSI_Out_DBx__4__AMUX, CYREG_PRT2_AMUX +.set SCSI_Out_DBx__4__BIE, CYREG_PRT2_BIE +.set SCSI_Out_DBx__4__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Out_DBx__4__BYP, CYREG_PRT2_BYP +.set SCSI_Out_DBx__4__CTL, CYREG_PRT2_CTL +.set SCSI_Out_DBx__4__DM0, CYREG_PRT2_DM0 +.set SCSI_Out_DBx__4__DM1, CYREG_PRT2_DM1 +.set SCSI_Out_DBx__4__DM2, CYREG_PRT2_DM2 +.set SCSI_Out_DBx__4__DR, CYREG_PRT2_DR +.set SCSI_Out_DBx__4__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Out_DBx__4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Out_DBx__4__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Out_DBx__4__MASK, 0x80 +.set SCSI_Out_DBx__4__PC, CYREG_PRT2_PC7 +.set SCSI_Out_DBx__4__PORT, 2 +.set SCSI_Out_DBx__4__PRT, CYREG_PRT2_PRT +.set SCSI_Out_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Out_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Out_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Out_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Out_DBx__4__PS, CYREG_PRT2_PS +.set SCSI_Out_DBx__4__SHIFT, 7 +.set SCSI_Out_DBx__4__SLW, CYREG_PRT2_SLW +.set SCSI_Out_DBx__5__AG, CYREG_PRT2_AG +.set SCSI_Out_DBx__5__AMUX, CYREG_PRT2_AMUX +.set SCSI_Out_DBx__5__BIE, CYREG_PRT2_BIE +.set SCSI_Out_DBx__5__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Out_DBx__5__BYP, CYREG_PRT2_BYP +.set SCSI_Out_DBx__5__CTL, CYREG_PRT2_CTL +.set SCSI_Out_DBx__5__DM0, CYREG_PRT2_DM0 +.set SCSI_Out_DBx__5__DM1, CYREG_PRT2_DM1 +.set SCSI_Out_DBx__5__DM2, CYREG_PRT2_DM2 +.set SCSI_Out_DBx__5__DR, CYREG_PRT2_DR +.set SCSI_Out_DBx__5__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Out_DBx__5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Out_DBx__5__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Out_DBx__5__MASK, 0x40 +.set SCSI_Out_DBx__5__PC, CYREG_PRT2_PC6 +.set SCSI_Out_DBx__5__PORT, 2 +.set SCSI_Out_DBx__5__PRT, CYREG_PRT2_PRT +.set SCSI_Out_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Out_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Out_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Out_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Out_DBx__5__PS, CYREG_PRT2_PS +.set SCSI_Out_DBx__5__SHIFT, 6 +.set SCSI_Out_DBx__5__SLW, CYREG_PRT2_SLW +.set SCSI_Out_DBx__6__AG, CYREG_PRT2_AG +.set SCSI_Out_DBx__6__AMUX, CYREG_PRT2_AMUX +.set SCSI_Out_DBx__6__BIE, CYREG_PRT2_BIE +.set SCSI_Out_DBx__6__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Out_DBx__6__BYP, CYREG_PRT2_BYP +.set SCSI_Out_DBx__6__CTL, CYREG_PRT2_CTL +.set SCSI_Out_DBx__6__DM0, CYREG_PRT2_DM0 +.set SCSI_Out_DBx__6__DM1, CYREG_PRT2_DM1 +.set SCSI_Out_DBx__6__DM2, CYREG_PRT2_DM2 +.set SCSI_Out_DBx__6__DR, CYREG_PRT2_DR +.set SCSI_Out_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Out_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Out_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Out_DBx__6__MASK, 0x08 +.set SCSI_Out_DBx__6__PC, CYREG_PRT2_PC3 +.set SCSI_Out_DBx__6__PORT, 2 +.set SCSI_Out_DBx__6__PRT, CYREG_PRT2_PRT +.set SCSI_Out_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Out_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Out_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Out_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Out_DBx__6__PS, CYREG_PRT2_PS +.set SCSI_Out_DBx__6__SHIFT, 3 +.set SCSI_Out_DBx__6__SLW, CYREG_PRT2_SLW +.set SCSI_Out_DBx__7__AG, CYREG_PRT2_AG +.set SCSI_Out_DBx__7__AMUX, CYREG_PRT2_AMUX +.set SCSI_Out_DBx__7__BIE, CYREG_PRT2_BIE +.set SCSI_Out_DBx__7__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Out_DBx__7__BYP, CYREG_PRT2_BYP +.set SCSI_Out_DBx__7__CTL, CYREG_PRT2_CTL +.set SCSI_Out_DBx__7__DM0, CYREG_PRT2_DM0 +.set SCSI_Out_DBx__7__DM1, CYREG_PRT2_DM1 +.set SCSI_Out_DBx__7__DM2, CYREG_PRT2_DM2 +.set SCSI_Out_DBx__7__DR, CYREG_PRT2_DR +.set SCSI_Out_DBx__7__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Out_DBx__7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Out_DBx__7__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Out_DBx__7__MASK, 0x04 +.set SCSI_Out_DBx__7__PC, CYREG_PRT2_PC2 +.set SCSI_Out_DBx__7__PORT, 2 +.set SCSI_Out_DBx__7__PRT, CYREG_PRT2_PRT +.set SCSI_Out_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Out_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Out_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Out_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Out_DBx__7__PS, CYREG_PRT2_PS +.set SCSI_Out_DBx__7__SHIFT, 2 +.set SCSI_Out_DBx__7__SLW, CYREG_PRT2_SLW +.set SCSI_Out_DBx__DB0__AG, CYREG_PRT5_AG +.set SCSI_Out_DBx__DB0__AMUX, CYREG_PRT5_AMUX +.set SCSI_Out_DBx__DB0__BIE, CYREG_PRT5_BIE +.set SCSI_Out_DBx__DB0__BIT_MASK, CYREG_PRT5_BIT_MASK +.set SCSI_Out_DBx__DB0__BYP, CYREG_PRT5_BYP +.set SCSI_Out_DBx__DB0__CTL, CYREG_PRT5_CTL +.set SCSI_Out_DBx__DB0__DM0, CYREG_PRT5_DM0 +.set SCSI_Out_DBx__DB0__DM1, CYREG_PRT5_DM1 +.set SCSI_Out_DBx__DB0__DM2, CYREG_PRT5_DM2 +.set SCSI_Out_DBx__DB0__DR, CYREG_PRT5_DR +.set SCSI_Out_DBx__DB0__INP_DIS, CYREG_PRT5_INP_DIS +.set SCSI_Out_DBx__DB0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG +.set SCSI_Out_DBx__DB0__LCD_EN, CYREG_PRT5_LCD_EN +.set SCSI_Out_DBx__DB0__MASK, 0x02 +.set SCSI_Out_DBx__DB0__PC, CYREG_PRT5_PC1 +.set SCSI_Out_DBx__DB0__PORT, 5 +.set SCSI_Out_DBx__DB0__PRT, CYREG_PRT5_PRT +.set SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL +.set SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN +.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 +.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 +.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 +.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 +.set SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT +.set SCSI_Out_DBx__DB0__PS, CYREG_PRT5_PS +.set SCSI_Out_DBx__DB0__SHIFT, 1 +.set SCSI_Out_DBx__DB0__SLW, CYREG_PRT5_SLW +.set SCSI_Out_DBx__DB1__AG, CYREG_PRT5_AG +.set SCSI_Out_DBx__DB1__AMUX, CYREG_PRT5_AMUX +.set SCSI_Out_DBx__DB1__BIE, CYREG_PRT5_BIE +.set SCSI_Out_DBx__DB1__BIT_MASK, CYREG_PRT5_BIT_MASK +.set SCSI_Out_DBx__DB1__BYP, CYREG_PRT5_BYP +.set SCSI_Out_DBx__DB1__CTL, CYREG_PRT5_CTL +.set SCSI_Out_DBx__DB1__DM0, CYREG_PRT5_DM0 +.set SCSI_Out_DBx__DB1__DM1, CYREG_PRT5_DM1 +.set SCSI_Out_DBx__DB1__DM2, CYREG_PRT5_DM2 +.set SCSI_Out_DBx__DB1__DR, CYREG_PRT5_DR +.set SCSI_Out_DBx__DB1__INP_DIS, CYREG_PRT5_INP_DIS +.set SCSI_Out_DBx__DB1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG +.set SCSI_Out_DBx__DB1__LCD_EN, CYREG_PRT5_LCD_EN +.set SCSI_Out_DBx__DB1__MASK, 0x01 +.set SCSI_Out_DBx__DB1__PC, CYREG_PRT5_PC0 +.set SCSI_Out_DBx__DB1__PORT, 5 +.set SCSI_Out_DBx__DB1__PRT, CYREG_PRT5_PRT +.set SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL +.set SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN +.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 +.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 +.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 +.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 +.set SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT +.set SCSI_Out_DBx__DB1__PS, CYREG_PRT5_PS +.set SCSI_Out_DBx__DB1__SHIFT, 0 +.set SCSI_Out_DBx__DB1__SLW, CYREG_PRT5_SLW +.set SCSI_Out_DBx__DB2__AG, CYREG_PRT6_AG +.set SCSI_Out_DBx__DB2__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out_DBx__DB2__BIE, CYREG_PRT6_BIE +.set SCSI_Out_DBx__DB2__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out_DBx__DB2__BYP, CYREG_PRT6_BYP +.set SCSI_Out_DBx__DB2__CTL, CYREG_PRT6_CTL +.set SCSI_Out_DBx__DB2__DM0, CYREG_PRT6_DM0 +.set SCSI_Out_DBx__DB2__DM1, CYREG_PRT6_DM1 +.set SCSI_Out_DBx__DB2__DM2, CYREG_PRT6_DM2 +.set SCSI_Out_DBx__DB2__DR, CYREG_PRT6_DR +.set SCSI_Out_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out_DBx__DB2__MASK, 0x20 +.set SCSI_Out_DBx__DB2__PC, CYREG_PRT6_PC5 +.set SCSI_Out_DBx__DB2__PORT, 6 +.set SCSI_Out_DBx__DB2__PRT, CYREG_PRT6_PRT +.set SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out_DBx__DB2__PS, CYREG_PRT6_PS +.set SCSI_Out_DBx__DB2__SHIFT, 5 +.set SCSI_Out_DBx__DB2__SLW, CYREG_PRT6_SLW +.set SCSI_Out_DBx__DB3__AG, CYREG_PRT6_AG +.set SCSI_Out_DBx__DB3__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out_DBx__DB3__BIE, CYREG_PRT6_BIE +.set SCSI_Out_DBx__DB3__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out_DBx__DB3__BYP, CYREG_PRT6_BYP +.set SCSI_Out_DBx__DB3__CTL, CYREG_PRT6_CTL +.set SCSI_Out_DBx__DB3__DM0, CYREG_PRT6_DM0 +.set SCSI_Out_DBx__DB3__DM1, CYREG_PRT6_DM1 +.set SCSI_Out_DBx__DB3__DM2, CYREG_PRT6_DM2 +.set SCSI_Out_DBx__DB3__DR, CYREG_PRT6_DR +.set SCSI_Out_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out_DBx__DB3__MASK, 0x10 +.set SCSI_Out_DBx__DB3__PC, CYREG_PRT6_PC4 +.set SCSI_Out_DBx__DB3__PORT, 6 +.set SCSI_Out_DBx__DB3__PRT, CYREG_PRT6_PRT +.set SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out_DBx__DB3__PS, CYREG_PRT6_PS +.set SCSI_Out_DBx__DB3__SHIFT, 4 +.set SCSI_Out_DBx__DB3__SLW, CYREG_PRT6_SLW +.set SCSI_Out_DBx__DB4__AG, CYREG_PRT2_AG +.set SCSI_Out_DBx__DB4__AMUX, CYREG_PRT2_AMUX +.set SCSI_Out_DBx__DB4__BIE, CYREG_PRT2_BIE +.set SCSI_Out_DBx__DB4__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Out_DBx__DB4__BYP, CYREG_PRT2_BYP +.set SCSI_Out_DBx__DB4__CTL, CYREG_PRT2_CTL +.set SCSI_Out_DBx__DB4__DM0, CYREG_PRT2_DM0 +.set SCSI_Out_DBx__DB4__DM1, CYREG_PRT2_DM1 +.set SCSI_Out_DBx__DB4__DM2, CYREG_PRT2_DM2 +.set SCSI_Out_DBx__DB4__DR, CYREG_PRT2_DR +.set SCSI_Out_DBx__DB4__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Out_DBx__DB4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Out_DBx__DB4__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Out_DBx__DB4__MASK, 0x80 +.set SCSI_Out_DBx__DB4__PC, CYREG_PRT2_PC7 +.set SCSI_Out_DBx__DB4__PORT, 2 +.set SCSI_Out_DBx__DB4__PRT, CYREG_PRT2_PRT +.set SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Out_DBx__DB4__PS, CYREG_PRT2_PS +.set SCSI_Out_DBx__DB4__SHIFT, 7 +.set SCSI_Out_DBx__DB4__SLW, CYREG_PRT2_SLW +.set SCSI_Out_DBx__DB5__AG, CYREG_PRT2_AG +.set SCSI_Out_DBx__DB5__AMUX, CYREG_PRT2_AMUX +.set SCSI_Out_DBx__DB5__BIE, CYREG_PRT2_BIE +.set SCSI_Out_DBx__DB5__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Out_DBx__DB5__BYP, CYREG_PRT2_BYP +.set SCSI_Out_DBx__DB5__CTL, CYREG_PRT2_CTL +.set SCSI_Out_DBx__DB5__DM0, CYREG_PRT2_DM0 +.set SCSI_Out_DBx__DB5__DM1, CYREG_PRT2_DM1 +.set SCSI_Out_DBx__DB5__DM2, CYREG_PRT2_DM2 +.set SCSI_Out_DBx__DB5__DR, CYREG_PRT2_DR +.set SCSI_Out_DBx__DB5__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Out_DBx__DB5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Out_DBx__DB5__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Out_DBx__DB5__MASK, 0x40 +.set SCSI_Out_DBx__DB5__PC, CYREG_PRT2_PC6 +.set SCSI_Out_DBx__DB5__PORT, 2 +.set SCSI_Out_DBx__DB5__PRT, CYREG_PRT2_PRT +.set SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Out_DBx__DB5__PS, CYREG_PRT2_PS +.set SCSI_Out_DBx__DB5__SHIFT, 6 +.set SCSI_Out_DBx__DB5__SLW, CYREG_PRT2_SLW +.set SCSI_Out_DBx__DB6__AG, CYREG_PRT2_AG +.set SCSI_Out_DBx__DB6__AMUX, CYREG_PRT2_AMUX +.set SCSI_Out_DBx__DB6__BIE, CYREG_PRT2_BIE +.set SCSI_Out_DBx__DB6__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Out_DBx__DB6__BYP, CYREG_PRT2_BYP +.set SCSI_Out_DBx__DB6__CTL, CYREG_PRT2_CTL +.set SCSI_Out_DBx__DB6__DM0, CYREG_PRT2_DM0 +.set SCSI_Out_DBx__DB6__DM1, CYREG_PRT2_DM1 +.set SCSI_Out_DBx__DB6__DM2, CYREG_PRT2_DM2 +.set SCSI_Out_DBx__DB6__DR, CYREG_PRT2_DR +.set SCSI_Out_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Out_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Out_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Out_DBx__DB6__MASK, 0x08 +.set SCSI_Out_DBx__DB6__PC, CYREG_PRT2_PC3 +.set SCSI_Out_DBx__DB6__PORT, 2 +.set SCSI_Out_DBx__DB6__PRT, CYREG_PRT2_PRT +.set SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Out_DBx__DB6__PS, CYREG_PRT2_PS +.set SCSI_Out_DBx__DB6__SHIFT, 3 +.set SCSI_Out_DBx__DB6__SLW, CYREG_PRT2_SLW +.set SCSI_Out_DBx__DB7__AG, CYREG_PRT2_AG +.set SCSI_Out_DBx__DB7__AMUX, CYREG_PRT2_AMUX +.set SCSI_Out_DBx__DB7__BIE, CYREG_PRT2_BIE +.set SCSI_Out_DBx__DB7__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Out_DBx__DB7__BYP, CYREG_PRT2_BYP +.set SCSI_Out_DBx__DB7__CTL, CYREG_PRT2_CTL +.set SCSI_Out_DBx__DB7__DM0, CYREG_PRT2_DM0 +.set SCSI_Out_DBx__DB7__DM1, CYREG_PRT2_DM1 +.set SCSI_Out_DBx__DB7__DM2, CYREG_PRT2_DM2 +.set SCSI_Out_DBx__DB7__DR, CYREG_PRT2_DR +.set SCSI_Out_DBx__DB7__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Out_DBx__DB7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Out_DBx__DB7__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Out_DBx__DB7__MASK, 0x04 +.set SCSI_Out_DBx__DB7__PC, CYREG_PRT2_PC2 +.set SCSI_Out_DBx__DB7__PORT, 2 +.set SCSI_Out_DBx__DB7__PRT, CYREG_PRT2_PRT +.set SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Out_DBx__DB7__PS, CYREG_PRT2_PS +.set SCSI_Out_DBx__DB7__SHIFT, 2 +.set SCSI_Out_DBx__DB7__SLW, CYREG_PRT2_SLW + +/* USBFS_dp_int */ +.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_dp_int__INTC_MASK, 0x1000 +.set USBFS_dp_int__INTC_NUMBER, 12 +.set USBFS_dp_int__INTC_PRIOR_NUM, 7 +.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12 +.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* USBFS_ep_0 */ +.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_0__INTC_MASK, 0x1000000 +.set USBFS_ep_0__INTC_NUMBER, 24 +.set USBFS_ep_0__INTC_PRIOR_NUM, 7 +.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24 +.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* USBFS_ep_1 */ +.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_1__INTC_MASK, 0x01 +.set USBFS_ep_1__INTC_NUMBER, 0 +.set USBFS_ep_1__INTC_PRIOR_NUM, 7 +.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_0 +.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* USBFS_ep_2 */ +.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_2__INTC_MASK, 0x02 +.set USBFS_ep_2__INTC_NUMBER, 1 +.set USBFS_ep_2__INTC_PRIOR_NUM, 7 +.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_1 +.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SD_PULLUP */ +.set SD_PULLUP__0__MASK, 0x02 +.set SD_PULLUP__0__PC, CYREG_PRT3_PC1 +.set SD_PULLUP__0__PORT, 3 +.set SD_PULLUP__0__SHIFT, 1 +.set SD_PULLUP__1__MASK, 0x04 +.set SD_PULLUP__1__PC, CYREG_PRT3_PC2 +.set SD_PULLUP__1__PORT, 3 +.set SD_PULLUP__1__SHIFT, 2 +.set SD_PULLUP__2__MASK, 0x08 +.set SD_PULLUP__2__PC, CYREG_PRT3_PC3 +.set SD_PULLUP__2__PORT, 3 +.set SD_PULLUP__2__SHIFT, 3 +.set SD_PULLUP__3__MASK, 0x10 +.set SD_PULLUP__3__PC, CYREG_PRT3_PC4 +.set SD_PULLUP__3__PORT, 3 +.set SD_PULLUP__3__SHIFT, 4 +.set SD_PULLUP__4__MASK, 0x20 +.set SD_PULLUP__4__PC, CYREG_PRT3_PC5 +.set SD_PULLUP__4__PORT, 3 +.set SD_PULLUP__4__SHIFT, 5 +.set SD_PULLUP__AG, CYREG_PRT3_AG +.set SD_PULLUP__AMUX, CYREG_PRT3_AMUX +.set SD_PULLUP__BIE, CYREG_PRT3_BIE +.set SD_PULLUP__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_PULLUP__BYP, CYREG_PRT3_BYP +.set SD_PULLUP__CTL, CYREG_PRT3_CTL +.set SD_PULLUP__DM0, CYREG_PRT3_DM0 +.set SD_PULLUP__DM1, CYREG_PRT3_DM1 +.set SD_PULLUP__DM2, CYREG_PRT3_DM2 +.set SD_PULLUP__DR, CYREG_PRT3_DR +.set SD_PULLUP__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_PULLUP__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_PULLUP__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_PULLUP__MASK, 0x3E +.set SD_PULLUP__PORT, 3 +.set SD_PULLUP__PRT, CYREG_PRT3_PRT +.set SD_PULLUP__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_PULLUP__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_PULLUP__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_PULLUP__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_PULLUP__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_PULLUP__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_PULLUP__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_PULLUP__PS, CYREG_PRT3_PS +.set SD_PULLUP__SHIFT, 1 +.set SD_PULLUP__SLW, CYREG_PRT3_SLW + +/* USBFS_USB */ +.set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG +.set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG +.set USBFS_USB__ARB_EP1_INT_EN, CYREG_USB_ARB_EP1_INT_EN +.set USBFS_USB__ARB_EP1_SR, CYREG_USB_ARB_EP1_SR +.set USBFS_USB__ARB_EP2_CFG, CYREG_USB_ARB_EP2_CFG +.set USBFS_USB__ARB_EP2_INT_EN, CYREG_USB_ARB_EP2_INT_EN +.set USBFS_USB__ARB_EP2_SR, CYREG_USB_ARB_EP2_SR +.set USBFS_USB__ARB_EP3_CFG, CYREG_USB_ARB_EP3_CFG +.set USBFS_USB__ARB_EP3_INT_EN, CYREG_USB_ARB_EP3_INT_EN +.set USBFS_USB__ARB_EP3_SR, CYREG_USB_ARB_EP3_SR +.set USBFS_USB__ARB_EP4_CFG, CYREG_USB_ARB_EP4_CFG +.set USBFS_USB__ARB_EP4_INT_EN, CYREG_USB_ARB_EP4_INT_EN +.set USBFS_USB__ARB_EP4_SR, CYREG_USB_ARB_EP4_SR +.set USBFS_USB__ARB_EP5_CFG, CYREG_USB_ARB_EP5_CFG +.set USBFS_USB__ARB_EP5_INT_EN, CYREG_USB_ARB_EP5_INT_EN +.set USBFS_USB__ARB_EP5_SR, CYREG_USB_ARB_EP5_SR +.set USBFS_USB__ARB_EP6_CFG, CYREG_USB_ARB_EP6_CFG +.set USBFS_USB__ARB_EP6_INT_EN, CYREG_USB_ARB_EP6_INT_EN +.set USBFS_USB__ARB_EP6_SR, CYREG_USB_ARB_EP6_SR +.set USBFS_USB__ARB_EP7_CFG, CYREG_USB_ARB_EP7_CFG +.set USBFS_USB__ARB_EP7_INT_EN, CYREG_USB_ARB_EP7_INT_EN +.set USBFS_USB__ARB_EP7_SR, CYREG_USB_ARB_EP7_SR +.set USBFS_USB__ARB_EP8_CFG, CYREG_USB_ARB_EP8_CFG +.set USBFS_USB__ARB_EP8_INT_EN, CYREG_USB_ARB_EP8_INT_EN +.set USBFS_USB__ARB_EP8_SR, CYREG_USB_ARB_EP8_SR +.set USBFS_USB__ARB_INT_EN, CYREG_USB_ARB_INT_EN +.set USBFS_USB__ARB_INT_SR, CYREG_USB_ARB_INT_SR +.set USBFS_USB__ARB_RW1_DR, CYREG_USB_ARB_RW1_DR +.set USBFS_USB__ARB_RW1_RA, CYREG_USB_ARB_RW1_RA +.set USBFS_USB__ARB_RW1_RA_MSB, CYREG_USB_ARB_RW1_RA_MSB +.set USBFS_USB__ARB_RW1_WA, CYREG_USB_ARB_RW1_WA +.set USBFS_USB__ARB_RW1_WA_MSB, CYREG_USB_ARB_RW1_WA_MSB +.set USBFS_USB__ARB_RW2_DR, CYREG_USB_ARB_RW2_DR +.set USBFS_USB__ARB_RW2_RA, CYREG_USB_ARB_RW2_RA +.set USBFS_USB__ARB_RW2_RA_MSB, CYREG_USB_ARB_RW2_RA_MSB +.set USBFS_USB__ARB_RW2_WA, CYREG_USB_ARB_RW2_WA +.set USBFS_USB__ARB_RW2_WA_MSB, CYREG_USB_ARB_RW2_WA_MSB +.set USBFS_USB__ARB_RW3_DR, CYREG_USB_ARB_RW3_DR +.set USBFS_USB__ARB_RW3_RA, CYREG_USB_ARB_RW3_RA +.set USBFS_USB__ARB_RW3_RA_MSB, CYREG_USB_ARB_RW3_RA_MSB +.set USBFS_USB__ARB_RW3_WA, CYREG_USB_ARB_RW3_WA +.set USBFS_USB__ARB_RW3_WA_MSB, CYREG_USB_ARB_RW3_WA_MSB +.set USBFS_USB__ARB_RW4_DR, CYREG_USB_ARB_RW4_DR +.set USBFS_USB__ARB_RW4_RA, CYREG_USB_ARB_RW4_RA +.set USBFS_USB__ARB_RW4_RA_MSB, CYREG_USB_ARB_RW4_RA_MSB +.set USBFS_USB__ARB_RW4_WA, CYREG_USB_ARB_RW4_WA +.set USBFS_USB__ARB_RW4_WA_MSB, CYREG_USB_ARB_RW4_WA_MSB +.set USBFS_USB__ARB_RW5_DR, CYREG_USB_ARB_RW5_DR +.set USBFS_USB__ARB_RW5_RA, CYREG_USB_ARB_RW5_RA +.set USBFS_USB__ARB_RW5_RA_MSB, CYREG_USB_ARB_RW5_RA_MSB +.set USBFS_USB__ARB_RW5_WA, CYREG_USB_ARB_RW5_WA +.set USBFS_USB__ARB_RW5_WA_MSB, CYREG_USB_ARB_RW5_WA_MSB +.set USBFS_USB__ARB_RW6_DR, CYREG_USB_ARB_RW6_DR +.set USBFS_USB__ARB_RW6_RA, CYREG_USB_ARB_RW6_RA +.set USBFS_USB__ARB_RW6_RA_MSB, CYREG_USB_ARB_RW6_RA_MSB +.set USBFS_USB__ARB_RW6_WA, CYREG_USB_ARB_RW6_WA +.set USBFS_USB__ARB_RW6_WA_MSB, CYREG_USB_ARB_RW6_WA_MSB +.set USBFS_USB__ARB_RW7_DR, CYREG_USB_ARB_RW7_DR +.set USBFS_USB__ARB_RW7_RA, CYREG_USB_ARB_RW7_RA +.set USBFS_USB__ARB_RW7_RA_MSB, CYREG_USB_ARB_RW7_RA_MSB +.set USBFS_USB__ARB_RW7_WA, CYREG_USB_ARB_RW7_WA +.set USBFS_USB__ARB_RW7_WA_MSB, CYREG_USB_ARB_RW7_WA_MSB +.set USBFS_USB__ARB_RW8_DR, CYREG_USB_ARB_RW8_DR +.set USBFS_USB__ARB_RW8_RA, CYREG_USB_ARB_RW8_RA +.set USBFS_USB__ARB_RW8_RA_MSB, CYREG_USB_ARB_RW8_RA_MSB +.set USBFS_USB__ARB_RW8_WA, CYREG_USB_ARB_RW8_WA +.set USBFS_USB__ARB_RW8_WA_MSB, CYREG_USB_ARB_RW8_WA_MSB +.set USBFS_USB__BUF_SIZE, CYREG_USB_BUF_SIZE +.set USBFS_USB__BUS_RST_CNT, CYREG_USB_BUS_RST_CNT +.set USBFS_USB__CR0, CYREG_USB_CR0 +.set USBFS_USB__CR1, CYREG_USB_CR1 +.set USBFS_USB__CWA, CYREG_USB_CWA +.set USBFS_USB__CWA_MSB, CYREG_USB_CWA_MSB +.set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES +.set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB +.set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG +.set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT +.set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR +.set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0 +.set USBFS_USB__EP0_DR1, CYREG_USB_EP0_DR1 +.set USBFS_USB__EP0_DR2, CYREG_USB_EP0_DR2 +.set USBFS_USB__EP0_DR3, CYREG_USB_EP0_DR3 +.set USBFS_USB__EP0_DR4, CYREG_USB_EP0_DR4 +.set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5 +.set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6 +.set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7 +.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE +.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE +.set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE +.set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5 +.set USBFS_USB__PM_ACT_MSK, 0x01 +.set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5 +.set USBFS_USB__PM_STBY_MSK, 0x01 +.set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0 +.set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1 +.set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0 +.set USBFS_USB__SIE_EP2_CNT0, CYREG_USB_SIE_EP2_CNT0 +.set USBFS_USB__SIE_EP2_CNT1, CYREG_USB_SIE_EP2_CNT1 +.set USBFS_USB__SIE_EP2_CR0, CYREG_USB_SIE_EP2_CR0 +.set USBFS_USB__SIE_EP3_CNT0, CYREG_USB_SIE_EP3_CNT0 +.set USBFS_USB__SIE_EP3_CNT1, CYREG_USB_SIE_EP3_CNT1 +.set USBFS_USB__SIE_EP3_CR0, CYREG_USB_SIE_EP3_CR0 +.set USBFS_USB__SIE_EP4_CNT0, CYREG_USB_SIE_EP4_CNT0 +.set USBFS_USB__SIE_EP4_CNT1, CYREG_USB_SIE_EP4_CNT1 +.set USBFS_USB__SIE_EP4_CR0, CYREG_USB_SIE_EP4_CR0 +.set USBFS_USB__SIE_EP5_CNT0, CYREG_USB_SIE_EP5_CNT0 +.set USBFS_USB__SIE_EP5_CNT1, CYREG_USB_SIE_EP5_CNT1 +.set USBFS_USB__SIE_EP5_CR0, CYREG_USB_SIE_EP5_CR0 +.set USBFS_USB__SIE_EP6_CNT0, CYREG_USB_SIE_EP6_CNT0 +.set USBFS_USB__SIE_EP6_CNT1, CYREG_USB_SIE_EP6_CNT1 +.set USBFS_USB__SIE_EP6_CR0, CYREG_USB_SIE_EP6_CR0 +.set USBFS_USB__SIE_EP7_CNT0, CYREG_USB_SIE_EP7_CNT0 +.set USBFS_USB__SIE_EP7_CNT1, CYREG_USB_SIE_EP7_CNT1 +.set USBFS_USB__SIE_EP7_CR0, CYREG_USB_SIE_EP7_CR0 +.set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0 +.set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1 +.set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0 +.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN +.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR +.set USBFS_USB__SOF0, CYREG_USB_SOF0 +.set USBFS_USB__SOF1, CYREG_USB_SOF1 +.set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0 +.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1 +.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN + +/* SCSI_Out */ +.set SCSI_Out__0__AG, CYREG_PRT15_AG +.set SCSI_Out__0__AMUX, CYREG_PRT15_AMUX +.set SCSI_Out__0__BIE, CYREG_PRT15_BIE +.set SCSI_Out__0__BIT_MASK, CYREG_PRT15_BIT_MASK +.set SCSI_Out__0__BYP, CYREG_PRT15_BYP +.set SCSI_Out__0__CTL, CYREG_PRT15_CTL +.set SCSI_Out__0__DM0, CYREG_PRT15_DM0 +.set SCSI_Out__0__DM1, CYREG_PRT15_DM1 +.set SCSI_Out__0__DM2, CYREG_PRT15_DM2 +.set SCSI_Out__0__DR, CYREG_PRT15_DR +.set SCSI_Out__0__INP_DIS, CYREG_PRT15_INP_DIS +.set SCSI_Out__0__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG +.set SCSI_Out__0__LCD_EN, CYREG_PRT15_LCD_EN +.set SCSI_Out__0__MASK, 0x20 +.set SCSI_Out__0__PC, CYREG_IO_PC_PRT15_PC5 +.set SCSI_Out__0__PORT, 15 +.set SCSI_Out__0__PRT, CYREG_PRT15_PRT +.set SCSI_Out__0__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL +.set SCSI_Out__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN +.set SCSI_Out__0__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 +.set SCSI_Out__0__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 +.set SCSI_Out__0__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 +.set SCSI_Out__0__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 +.set SCSI_Out__0__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT +.set SCSI_Out__0__PS, CYREG_PRT15_PS +.set SCSI_Out__0__SHIFT, 5 +.set SCSI_Out__0__SLW, CYREG_PRT15_SLW +.set SCSI_Out__1__AG, CYREG_PRT15_AG +.set SCSI_Out__1__AMUX, CYREG_PRT15_AMUX +.set SCSI_Out__1__BIE, CYREG_PRT15_BIE +.set SCSI_Out__1__BIT_MASK, CYREG_PRT15_BIT_MASK +.set SCSI_Out__1__BYP, CYREG_PRT15_BYP +.set SCSI_Out__1__CTL, CYREG_PRT15_CTL +.set SCSI_Out__1__DM0, CYREG_PRT15_DM0 +.set SCSI_Out__1__DM1, CYREG_PRT15_DM1 +.set SCSI_Out__1__DM2, CYREG_PRT15_DM2 +.set SCSI_Out__1__DR, CYREG_PRT15_DR +.set SCSI_Out__1__INP_DIS, CYREG_PRT15_INP_DIS +.set SCSI_Out__1__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG +.set SCSI_Out__1__LCD_EN, CYREG_PRT15_LCD_EN +.set SCSI_Out__1__MASK, 0x10 +.set SCSI_Out__1__PC, CYREG_IO_PC_PRT15_PC4 +.set SCSI_Out__1__PORT, 15 +.set SCSI_Out__1__PRT, CYREG_PRT15_PRT +.set SCSI_Out__1__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL +.set SCSI_Out__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN +.set SCSI_Out__1__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 +.set SCSI_Out__1__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 +.set SCSI_Out__1__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 +.set SCSI_Out__1__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 +.set SCSI_Out__1__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT +.set SCSI_Out__1__PS, CYREG_PRT15_PS +.set SCSI_Out__1__SHIFT, 4 +.set SCSI_Out__1__SLW, CYREG_PRT15_SLW +.set SCSI_Out__2__AG, CYREG_PRT6_AG +.set SCSI_Out__2__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out__2__BIE, CYREG_PRT6_BIE +.set SCSI_Out__2__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out__2__BYP, CYREG_PRT6_BYP +.set SCSI_Out__2__CTL, CYREG_PRT6_CTL +.set SCSI_Out__2__DM0, CYREG_PRT6_DM0 +.set SCSI_Out__2__DM1, CYREG_PRT6_DM1 +.set SCSI_Out__2__DM2, CYREG_PRT6_DM2 +.set SCSI_Out__2__DR, CYREG_PRT6_DR +.set SCSI_Out__2__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out__2__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out__2__MASK, 0x02 +.set SCSI_Out__2__PC, CYREG_PRT6_PC1 +.set SCSI_Out__2__PORT, 6 +.set SCSI_Out__2__PRT, CYREG_PRT6_PRT +.set SCSI_Out__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out__2__PS, CYREG_PRT6_PS +.set SCSI_Out__2__SHIFT, 1 +.set SCSI_Out__2__SLW, CYREG_PRT6_SLW +.set SCSI_Out__3__AG, CYREG_PRT6_AG +.set SCSI_Out__3__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out__3__BIE, CYREG_PRT6_BIE +.set SCSI_Out__3__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out__3__BYP, CYREG_PRT6_BYP +.set SCSI_Out__3__CTL, CYREG_PRT6_CTL +.set SCSI_Out__3__DM0, CYREG_PRT6_DM0 +.set SCSI_Out__3__DM1, CYREG_PRT6_DM1 +.set SCSI_Out__3__DM2, CYREG_PRT6_DM2 +.set SCSI_Out__3__DR, CYREG_PRT6_DR +.set SCSI_Out__3__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out__3__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out__3__MASK, 0x01 +.set SCSI_Out__3__PC, CYREG_PRT6_PC0 +.set SCSI_Out__3__PORT, 6 +.set SCSI_Out__3__PRT, CYREG_PRT6_PRT +.set SCSI_Out__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out__3__PS, CYREG_PRT6_PS +.set SCSI_Out__3__SHIFT, 0 +.set SCSI_Out__3__SLW, CYREG_PRT6_SLW +.set SCSI_Out__4__AG, CYREG_PRT4_AG +.set SCSI_Out__4__AMUX, CYREG_PRT4_AMUX +.set SCSI_Out__4__BIE, CYREG_PRT4_BIE +.set SCSI_Out__4__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Out__4__BYP, CYREG_PRT4_BYP +.set SCSI_Out__4__CTL, CYREG_PRT4_CTL +.set SCSI_Out__4__DM0, CYREG_PRT4_DM0 +.set SCSI_Out__4__DM1, CYREG_PRT4_DM1 +.set SCSI_Out__4__DM2, CYREG_PRT4_DM2 +.set SCSI_Out__4__DR, CYREG_PRT4_DR +.set SCSI_Out__4__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Out__4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Out__4__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Out__4__MASK, 0x20 +.set SCSI_Out__4__PC, CYREG_PRT4_PC5 +.set SCSI_Out__4__PORT, 4 +.set SCSI_Out__4__PRT, CYREG_PRT4_PRT +.set SCSI_Out__4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Out__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Out__4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Out__4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Out__4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Out__4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Out__4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Out__4__PS, CYREG_PRT4_PS +.set SCSI_Out__4__SHIFT, 5 +.set SCSI_Out__4__SLW, CYREG_PRT4_SLW +.set SCSI_Out__5__AG, CYREG_PRT4_AG +.set SCSI_Out__5__AMUX, CYREG_PRT4_AMUX +.set SCSI_Out__5__BIE, CYREG_PRT4_BIE +.set SCSI_Out__5__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Out__5__BYP, CYREG_PRT4_BYP +.set SCSI_Out__5__CTL, CYREG_PRT4_CTL +.set SCSI_Out__5__DM0, CYREG_PRT4_DM0 +.set SCSI_Out__5__DM1, CYREG_PRT4_DM1 +.set SCSI_Out__5__DM2, CYREG_PRT4_DM2 +.set SCSI_Out__5__DR, CYREG_PRT4_DR +.set SCSI_Out__5__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Out__5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Out__5__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Out__5__MASK, 0x10 +.set SCSI_Out__5__PC, CYREG_PRT4_PC4 +.set SCSI_Out__5__PORT, 4 +.set SCSI_Out__5__PRT, CYREG_PRT4_PRT +.set SCSI_Out__5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Out__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Out__5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Out__5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Out__5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Out__5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Out__5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Out__5__PS, CYREG_PRT4_PS +.set SCSI_Out__5__SHIFT, 4 +.set SCSI_Out__5__SLW, CYREG_PRT4_SLW +.set SCSI_Out__6__AG, CYREG_PRT0_AG +.set SCSI_Out__6__AMUX, CYREG_PRT0_AMUX +.set SCSI_Out__6__BIE, CYREG_PRT0_BIE +.set SCSI_Out__6__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Out__6__BYP, CYREG_PRT0_BYP +.set SCSI_Out__6__CTL, CYREG_PRT0_CTL +.set SCSI_Out__6__DM0, CYREG_PRT0_DM0 +.set SCSI_Out__6__DM1, CYREG_PRT0_DM1 +.set SCSI_Out__6__DM2, CYREG_PRT0_DM2 +.set SCSI_Out__6__DR, CYREG_PRT0_DR +.set SCSI_Out__6__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Out__6__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Out__6__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Out__6__MASK, 0x80 +.set SCSI_Out__6__PC, CYREG_PRT0_PC7 +.set SCSI_Out__6__PORT, 0 +.set SCSI_Out__6__PRT, CYREG_PRT0_PRT +.set SCSI_Out__6__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Out__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Out__6__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Out__6__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Out__6__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Out__6__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Out__6__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Out__6__PS, CYREG_PRT0_PS +.set SCSI_Out__6__SHIFT, 7 +.set SCSI_Out__6__SLW, CYREG_PRT0_SLW +.set SCSI_Out__7__AG, CYREG_PRT0_AG +.set SCSI_Out__7__AMUX, CYREG_PRT0_AMUX +.set SCSI_Out__7__BIE, CYREG_PRT0_BIE +.set SCSI_Out__7__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Out__7__BYP, CYREG_PRT0_BYP +.set SCSI_Out__7__CTL, CYREG_PRT0_CTL +.set SCSI_Out__7__DM0, CYREG_PRT0_DM0 +.set SCSI_Out__7__DM1, CYREG_PRT0_DM1 +.set SCSI_Out__7__DM2, CYREG_PRT0_DM2 +.set SCSI_Out__7__DR, CYREG_PRT0_DR +.set SCSI_Out__7__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Out__7__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Out__7__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Out__7__MASK, 0x40 +.set SCSI_Out__7__PC, CYREG_PRT0_PC6 +.set SCSI_Out__7__PORT, 0 +.set SCSI_Out__7__PRT, CYREG_PRT0_PRT +.set SCSI_Out__7__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Out__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Out__7__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Out__7__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Out__7__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Out__7__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Out__7__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Out__7__PS, CYREG_PRT0_PS +.set SCSI_Out__7__SHIFT, 6 +.set SCSI_Out__7__SLW, CYREG_PRT0_SLW +.set SCSI_Out__8__AG, CYREG_PRT0_AG +.set SCSI_Out__8__AMUX, CYREG_PRT0_AMUX +.set SCSI_Out__8__BIE, CYREG_PRT0_BIE +.set SCSI_Out__8__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Out__8__BYP, CYREG_PRT0_BYP +.set SCSI_Out__8__CTL, CYREG_PRT0_CTL +.set SCSI_Out__8__DM0, CYREG_PRT0_DM0 +.set SCSI_Out__8__DM1, CYREG_PRT0_DM1 +.set SCSI_Out__8__DM2, CYREG_PRT0_DM2 +.set SCSI_Out__8__DR, CYREG_PRT0_DR +.set SCSI_Out__8__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Out__8__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Out__8__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Out__8__MASK, 0x08 +.set SCSI_Out__8__PC, CYREG_PRT0_PC3 +.set SCSI_Out__8__PORT, 0 +.set SCSI_Out__8__PRT, CYREG_PRT0_PRT +.set SCSI_Out__8__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Out__8__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Out__8__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Out__8__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Out__8__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Out__8__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Out__8__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Out__8__PS, CYREG_PRT0_PS +.set SCSI_Out__8__SHIFT, 3 +.set SCSI_Out__8__SLW, CYREG_PRT0_SLW +.set SCSI_Out__9__AG, CYREG_PRT0_AG +.set SCSI_Out__9__AMUX, CYREG_PRT0_AMUX +.set SCSI_Out__9__BIE, CYREG_PRT0_BIE +.set SCSI_Out__9__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Out__9__BYP, CYREG_PRT0_BYP +.set SCSI_Out__9__CTL, CYREG_PRT0_CTL +.set SCSI_Out__9__DM0, CYREG_PRT0_DM0 +.set SCSI_Out__9__DM1, CYREG_PRT0_DM1 +.set SCSI_Out__9__DM2, CYREG_PRT0_DM2 +.set SCSI_Out__9__DR, CYREG_PRT0_DR +.set SCSI_Out__9__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Out__9__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Out__9__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Out__9__MASK, 0x04 +.set SCSI_Out__9__PC, CYREG_PRT0_PC2 +.set SCSI_Out__9__PORT, 0 +.set SCSI_Out__9__PRT, CYREG_PRT0_PRT +.set SCSI_Out__9__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Out__9__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Out__9__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Out__9__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Out__9__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Out__9__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Out__9__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Out__9__PS, CYREG_PRT0_PS +.set SCSI_Out__9__SHIFT, 2 +.set SCSI_Out__9__SLW, CYREG_PRT0_SLW +.set SCSI_Out__ACK__AG, CYREG_PRT6_AG +.set SCSI_Out__ACK__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out__ACK__BIE, CYREG_PRT6_BIE +.set SCSI_Out__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out__ACK__BYP, CYREG_PRT6_BYP +.set SCSI_Out__ACK__CTL, CYREG_PRT6_CTL +.set SCSI_Out__ACK__DM0, CYREG_PRT6_DM0 +.set SCSI_Out__ACK__DM1, CYREG_PRT6_DM1 +.set SCSI_Out__ACK__DM2, CYREG_PRT6_DM2 +.set SCSI_Out__ACK__DR, CYREG_PRT6_DR +.set SCSI_Out__ACK__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out__ACK__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out__ACK__MASK, 0x01 +.set SCSI_Out__ACK__PC, CYREG_PRT6_PC0 +.set SCSI_Out__ACK__PORT, 6 +.set SCSI_Out__ACK__PRT, CYREG_PRT6_PRT +.set SCSI_Out__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out__ACK__PS, CYREG_PRT6_PS +.set SCSI_Out__ACK__SHIFT, 0 +.set SCSI_Out__ACK__SLW, CYREG_PRT6_SLW +.set SCSI_Out__ATN__AG, CYREG_PRT15_AG +.set SCSI_Out__ATN__AMUX, CYREG_PRT15_AMUX +.set SCSI_Out__ATN__BIE, CYREG_PRT15_BIE +.set SCSI_Out__ATN__BIT_MASK, CYREG_PRT15_BIT_MASK +.set SCSI_Out__ATN__BYP, CYREG_PRT15_BYP +.set SCSI_Out__ATN__CTL, CYREG_PRT15_CTL +.set SCSI_Out__ATN__DM0, CYREG_PRT15_DM0 +.set SCSI_Out__ATN__DM1, CYREG_PRT15_DM1 +.set SCSI_Out__ATN__DM2, CYREG_PRT15_DM2 +.set SCSI_Out__ATN__DR, CYREG_PRT15_DR +.set SCSI_Out__ATN__INP_DIS, CYREG_PRT15_INP_DIS +.set SCSI_Out__ATN__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG +.set SCSI_Out__ATN__LCD_EN, CYREG_PRT15_LCD_EN +.set SCSI_Out__ATN__MASK, 0x10 +.set SCSI_Out__ATN__PC, CYREG_IO_PC_PRT15_PC4 +.set SCSI_Out__ATN__PORT, 15 +.set SCSI_Out__ATN__PRT, CYREG_PRT15_PRT +.set SCSI_Out__ATN__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL +.set SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN +.set SCSI_Out__ATN__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 +.set SCSI_Out__ATN__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 +.set SCSI_Out__ATN__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 +.set SCSI_Out__ATN__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 +.set SCSI_Out__ATN__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT +.set SCSI_Out__ATN__PS, CYREG_PRT15_PS +.set SCSI_Out__ATN__SHIFT, 4 +.set SCSI_Out__ATN__SLW, CYREG_PRT15_SLW +.set SCSI_Out__BSY__AG, CYREG_PRT6_AG +.set SCSI_Out__BSY__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out__BSY__BIE, CYREG_PRT6_BIE +.set SCSI_Out__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out__BSY__BYP, CYREG_PRT6_BYP +.set SCSI_Out__BSY__CTL, CYREG_PRT6_CTL +.set SCSI_Out__BSY__DM0, CYREG_PRT6_DM0 +.set SCSI_Out__BSY__DM1, CYREG_PRT6_DM1 +.set SCSI_Out__BSY__DM2, CYREG_PRT6_DM2 +.set SCSI_Out__BSY__DR, CYREG_PRT6_DR +.set SCSI_Out__BSY__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out__BSY__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out__BSY__MASK, 0x02 +.set SCSI_Out__BSY__PC, CYREG_PRT6_PC1 +.set SCSI_Out__BSY__PORT, 6 +.set SCSI_Out__BSY__PRT, CYREG_PRT6_PRT +.set SCSI_Out__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out__BSY__PS, CYREG_PRT6_PS +.set SCSI_Out__BSY__SHIFT, 1 +.set SCSI_Out__BSY__SLW, CYREG_PRT6_SLW +.set SCSI_Out__CD__AG, CYREG_PRT0_AG +.set SCSI_Out__CD__AMUX, CYREG_PRT0_AMUX +.set SCSI_Out__CD__BIE, CYREG_PRT0_BIE +.set SCSI_Out__CD__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Out__CD__BYP, CYREG_PRT0_BYP +.set SCSI_Out__CD__CTL, CYREG_PRT0_CTL +.set SCSI_Out__CD__DM0, CYREG_PRT0_DM0 +.set SCSI_Out__CD__DM1, CYREG_PRT0_DM1 +.set SCSI_Out__CD__DM2, CYREG_PRT0_DM2 +.set SCSI_Out__CD__DR, CYREG_PRT0_DR +.set SCSI_Out__CD__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Out__CD__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Out__CD__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Out__CD__MASK, 0x40 +.set SCSI_Out__CD__PC, CYREG_PRT0_PC6 +.set SCSI_Out__CD__PORT, 0 +.set SCSI_Out__CD__PRT, CYREG_PRT0_PRT +.set SCSI_Out__CD__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Out__CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Out__CD__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Out__CD__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Out__CD__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Out__CD__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Out__CD__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Out__CD__PS, CYREG_PRT0_PS +.set SCSI_Out__CD__SHIFT, 6 +.set SCSI_Out__CD__SLW, CYREG_PRT0_SLW +.set SCSI_Out__DBP_raw__AG, CYREG_PRT15_AG +.set SCSI_Out__DBP_raw__AMUX, CYREG_PRT15_AMUX +.set SCSI_Out__DBP_raw__BIE, CYREG_PRT15_BIE +.set SCSI_Out__DBP_raw__BIT_MASK, CYREG_PRT15_BIT_MASK +.set SCSI_Out__DBP_raw__BYP, CYREG_PRT15_BYP +.set SCSI_Out__DBP_raw__CTL, CYREG_PRT15_CTL +.set SCSI_Out__DBP_raw__DM0, CYREG_PRT15_DM0 +.set SCSI_Out__DBP_raw__DM1, CYREG_PRT15_DM1 +.set SCSI_Out__DBP_raw__DM2, CYREG_PRT15_DM2 +.set SCSI_Out__DBP_raw__DR, CYREG_PRT15_DR +.set SCSI_Out__DBP_raw__INP_DIS, CYREG_PRT15_INP_DIS +.set SCSI_Out__DBP_raw__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG +.set SCSI_Out__DBP_raw__LCD_EN, CYREG_PRT15_LCD_EN +.set SCSI_Out__DBP_raw__MASK, 0x20 +.set SCSI_Out__DBP_raw__PC, CYREG_IO_PC_PRT15_PC5 +.set SCSI_Out__DBP_raw__PORT, 15 +.set SCSI_Out__DBP_raw__PRT, CYREG_PRT15_PRT +.set SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL +.set SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN +.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 +.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 +.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 +.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 +.set SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT +.set SCSI_Out__DBP_raw__PS, CYREG_PRT15_PS +.set SCSI_Out__DBP_raw__SHIFT, 5 +.set SCSI_Out__DBP_raw__SLW, CYREG_PRT15_SLW +.set SCSI_Out__IO_raw__AG, CYREG_PRT0_AG +.set SCSI_Out__IO_raw__AMUX, CYREG_PRT0_AMUX +.set SCSI_Out__IO_raw__BIE, CYREG_PRT0_BIE +.set SCSI_Out__IO_raw__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Out__IO_raw__BYP, CYREG_PRT0_BYP +.set SCSI_Out__IO_raw__CTL, CYREG_PRT0_CTL +.set SCSI_Out__IO_raw__DM0, CYREG_PRT0_DM0 +.set SCSI_Out__IO_raw__DM1, CYREG_PRT0_DM1 +.set SCSI_Out__IO_raw__DM2, CYREG_PRT0_DM2 +.set SCSI_Out__IO_raw__DR, CYREG_PRT0_DR +.set SCSI_Out__IO_raw__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Out__IO_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Out__IO_raw__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Out__IO_raw__MASK, 0x04 +.set SCSI_Out__IO_raw__PC, CYREG_PRT0_PC2 +.set SCSI_Out__IO_raw__PORT, 0 +.set SCSI_Out__IO_raw__PRT, CYREG_PRT0_PRT +.set SCSI_Out__IO_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Out__IO_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Out__IO_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Out__IO_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Out__IO_raw__PS, CYREG_PRT0_PS +.set SCSI_Out__IO_raw__SHIFT, 2 +.set SCSI_Out__IO_raw__SLW, CYREG_PRT0_SLW +.set SCSI_Out__MSG__AG, CYREG_PRT4_AG +.set SCSI_Out__MSG__AMUX, CYREG_PRT4_AMUX +.set SCSI_Out__MSG__BIE, CYREG_PRT4_BIE +.set SCSI_Out__MSG__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Out__MSG__BYP, CYREG_PRT4_BYP +.set SCSI_Out__MSG__CTL, CYREG_PRT4_CTL +.set SCSI_Out__MSG__DM0, CYREG_PRT4_DM0 +.set SCSI_Out__MSG__DM1, CYREG_PRT4_DM1 +.set SCSI_Out__MSG__DM2, CYREG_PRT4_DM2 +.set SCSI_Out__MSG__DR, CYREG_PRT4_DR +.set SCSI_Out__MSG__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Out__MSG__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Out__MSG__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Out__MSG__MASK, 0x10 +.set SCSI_Out__MSG__PC, CYREG_PRT4_PC4 +.set SCSI_Out__MSG__PORT, 4 +.set SCSI_Out__MSG__PRT, CYREG_PRT4_PRT +.set SCSI_Out__MSG__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Out__MSG__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Out__MSG__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Out__MSG__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Out__MSG__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Out__MSG__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Out__MSG__PS, CYREG_PRT4_PS +.set SCSI_Out__MSG__SHIFT, 4 +.set SCSI_Out__MSG__SLW, CYREG_PRT4_SLW +.set SCSI_Out__REQ__AG, CYREG_PRT0_AG +.set SCSI_Out__REQ__AMUX, CYREG_PRT0_AMUX +.set SCSI_Out__REQ__BIE, CYREG_PRT0_BIE +.set SCSI_Out__REQ__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Out__REQ__BYP, CYREG_PRT0_BYP +.set SCSI_Out__REQ__CTL, CYREG_PRT0_CTL +.set SCSI_Out__REQ__DM0, CYREG_PRT0_DM0 +.set SCSI_Out__REQ__DM1, CYREG_PRT0_DM1 +.set SCSI_Out__REQ__DM2, CYREG_PRT0_DM2 +.set SCSI_Out__REQ__DR, CYREG_PRT0_DR +.set SCSI_Out__REQ__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Out__REQ__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Out__REQ__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Out__REQ__MASK, 0x08 +.set SCSI_Out__REQ__PC, CYREG_PRT0_PC3 +.set SCSI_Out__REQ__PORT, 0 +.set SCSI_Out__REQ__PRT, CYREG_PRT0_PRT +.set SCSI_Out__REQ__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Out__REQ__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Out__REQ__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Out__REQ__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Out__REQ__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Out__REQ__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Out__REQ__PS, CYREG_PRT0_PS +.set SCSI_Out__REQ__SHIFT, 3 +.set SCSI_Out__REQ__SLW, CYREG_PRT0_SLW +.set SCSI_Out__RST__AG, CYREG_PRT4_AG +.set SCSI_Out__RST__AMUX, CYREG_PRT4_AMUX +.set SCSI_Out__RST__BIE, CYREG_PRT4_BIE +.set SCSI_Out__RST__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Out__RST__BYP, CYREG_PRT4_BYP +.set SCSI_Out__RST__CTL, CYREG_PRT4_CTL +.set SCSI_Out__RST__DM0, CYREG_PRT4_DM0 +.set SCSI_Out__RST__DM1, CYREG_PRT4_DM1 +.set SCSI_Out__RST__DM2, CYREG_PRT4_DM2 +.set SCSI_Out__RST__DR, CYREG_PRT4_DR +.set SCSI_Out__RST__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Out__RST__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Out__RST__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Out__RST__MASK, 0x20 +.set SCSI_Out__RST__PC, CYREG_PRT4_PC5 +.set SCSI_Out__RST__PORT, 4 +.set SCSI_Out__RST__PRT, CYREG_PRT4_PRT +.set SCSI_Out__RST__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Out__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Out__RST__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Out__RST__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Out__RST__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Out__RST__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Out__RST__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Out__RST__PS, CYREG_PRT4_PS +.set SCSI_Out__RST__SHIFT, 5 +.set SCSI_Out__RST__SLW, CYREG_PRT4_SLW +.set SCSI_Out__SEL__AG, CYREG_PRT0_AG +.set SCSI_Out__SEL__AMUX, CYREG_PRT0_AMUX +.set SCSI_Out__SEL__BIE, CYREG_PRT0_BIE +.set SCSI_Out__SEL__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Out__SEL__BYP, CYREG_PRT0_BYP +.set SCSI_Out__SEL__CTL, CYREG_PRT0_CTL +.set SCSI_Out__SEL__DM0, CYREG_PRT0_DM0 +.set SCSI_Out__SEL__DM1, CYREG_PRT0_DM1 +.set SCSI_Out__SEL__DM2, CYREG_PRT0_DM2 +.set SCSI_Out__SEL__DR, CYREG_PRT0_DR +.set SCSI_Out__SEL__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Out__SEL__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Out__SEL__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Out__SEL__MASK, 0x80 +.set SCSI_Out__SEL__PC, CYREG_PRT0_PC7 +.set SCSI_Out__SEL__PORT, 0 +.set SCSI_Out__SEL__PRT, CYREG_PRT0_PRT +.set SCSI_Out__SEL__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Out__SEL__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Out__SEL__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Out__SEL__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Out__SEL__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Out__SEL__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Out__SEL__PS, CYREG_PRT0_PS +.set SCSI_Out__SEL__SHIFT, 7 +.set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW + +/* USBFS_Dm */ +.set USBFS_Dm__0__MASK, 0x80 +.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1 +.set USBFS_Dm__0__PORT, 15 +.set USBFS_Dm__0__SHIFT, 7 +.set USBFS_Dm__AG, CYREG_PRT15_AG +.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX +.set USBFS_Dm__BIE, CYREG_PRT15_BIE +.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK +.set USBFS_Dm__BYP, CYREG_PRT15_BYP +.set USBFS_Dm__CTL, CYREG_PRT15_CTL +.set USBFS_Dm__DM0, CYREG_PRT15_DM0 +.set USBFS_Dm__DM1, CYREG_PRT15_DM1 +.set USBFS_Dm__DM2, CYREG_PRT15_DM2 +.set USBFS_Dm__DR, CYREG_PRT15_DR +.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS +.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG +.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN +.set USBFS_Dm__MASK, 0x80 +.set USBFS_Dm__PORT, 15 +.set USBFS_Dm__PRT, CYREG_PRT15_PRT +.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL +.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN +.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 +.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 +.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 +.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 +.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT +.set USBFS_Dm__PS, CYREG_PRT15_PS +.set USBFS_Dm__SHIFT, 7 +.set USBFS_Dm__SLW, CYREG_PRT15_SLW + +/* USBFS_Dp */ +.set USBFS_Dp__0__MASK, 0x40 +.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0 +.set USBFS_Dp__0__PORT, 15 +.set USBFS_Dp__0__SHIFT, 6 +.set USBFS_Dp__AG, CYREG_PRT15_AG +.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX +.set USBFS_Dp__BIE, CYREG_PRT15_BIE +.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK +.set USBFS_Dp__BYP, CYREG_PRT15_BYP +.set USBFS_Dp__CTL, CYREG_PRT15_CTL +.set USBFS_Dp__DM0, CYREG_PRT15_DM0 +.set USBFS_Dp__DM1, CYREG_PRT15_DM1 +.set USBFS_Dp__DM2, CYREG_PRT15_DM2 +.set USBFS_Dp__DR, CYREG_PRT15_DR +.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS +.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT +.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG +.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN +.set USBFS_Dp__MASK, 0x40 +.set USBFS_Dp__PORT, 15 +.set USBFS_Dp__PRT, CYREG_PRT15_PRT +.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL +.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN +.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 +.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 +.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 +.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 +.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT +.set USBFS_Dp__PS, CYREG_PRT15_PS +.set USBFS_Dp__SHIFT, 6 +.set USBFS_Dp__SLW, CYREG_PRT15_SLW +.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15 + +/* LED */ +.set LED__0__MASK, 0x02 +.set LED__0__PC, CYREG_PRT0_PC1 +.set LED__0__PORT, 0 +.set LED__0__SHIFT, 1 +.set LED__AG, CYREG_PRT0_AG +.set LED__AMUX, CYREG_PRT0_AMUX +.set LED__BIE, CYREG_PRT0_BIE +.set LED__BIT_MASK, CYREG_PRT0_BIT_MASK +.set LED__BYP, CYREG_PRT0_BYP +.set LED__CTL, CYREG_PRT0_CTL +.set LED__DM0, CYREG_PRT0_DM0 +.set LED__DM1, CYREG_PRT0_DM1 +.set LED__DM2, CYREG_PRT0_DM2 +.set LED__DR, CYREG_PRT0_DR +.set LED__INP_DIS, CYREG_PRT0_INP_DIS +.set LED__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set LED__LCD_EN, CYREG_PRT0_LCD_EN +.set LED__MASK, 0x02 +.set LED__PORT, 0 +.set LED__PRT, CYREG_PRT0_PRT +.set LED__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set LED__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set LED__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set LED__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set LED__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set LED__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set LED__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set LED__PS, CYREG_PRT0_PS +.set LED__SHIFT, 1 +.set LED__SLW, CYREG_PRT0_SLW + +/* Miscellaneous */ +/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */ +.set CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO, 0 +.set CYDEV_DEBUGGING_DPS_SWD_SWV, 6 +.set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0 +.set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0 +.set CYDEV_CONFIG_FASTBOOT_ENABLED, 1 +.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0 +.set CYDEV_CHIP_MEMBER_5B, 4 +.set CYDEV_CHIP_FAMILY_PSOC5, 3 +.set CYDEV_CHIP_DIE_PSOC5LP, 4 +.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_DIE_PSOC5LP +.set CYDEV_BOOTLOADER_IO_COMP_USBFS, 1 +.set BCLK__BUS_CLK__HZ, 64000000 +.set BCLK__BUS_CLK__KHZ, 64000 +.set BCLK__BUS_CLK__MHZ, 64 +.set CYDEV_BOOTLOADER_APPLICATIONS, 1 +.set CYDEV_BOOTLOADER_CHECKSUM_BASIC, 0 +.set CYDEV_BOOTLOADER_CHECKSUM_CRC, 1 +.set CYDEV_BOOTLOADER_IO_COMP, CYDEV_BOOTLOADER_IO_COMP_USBFS +.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT +.set CYDEV_CHIP_DIE_LEOPARD, 1 +.set CYDEV_CHIP_DIE_PANTHER, 3 +.set CYDEV_CHIP_DIE_PSOC4A, 2 +.set CYDEV_CHIP_DIE_UNKNOWN, 0 +.set CYDEV_CHIP_FAMILY_PSOC3, 1 +.set CYDEV_CHIP_FAMILY_PSOC4, 2 +.set CYDEV_CHIP_FAMILY_UNKNOWN, 0 +.set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5 +.set CYDEV_CHIP_JTAG_ID, 0x2E133069 +.set CYDEV_CHIP_MEMBER_3A, 1 +.set CYDEV_CHIP_MEMBER_4A, 2 +.set CYDEV_CHIP_MEMBER_5A, 3 +.set CYDEV_CHIP_MEMBER_UNKNOWN, 0 +.set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B +.set CYDEV_CHIP_REVISION_3A_ES1, 0 +.set CYDEV_CHIP_REVISION_3A_ES2, 1 +.set CYDEV_CHIP_REVISION_3A_ES3, 3 +.set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3 +.set CYDEV_CHIP_REVISION_4A_ES0, 17 +.set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17 +.set CYDEV_CHIP_REVISION_5A_ES0, 0 +.set CYDEV_CHIP_REVISION_5A_ES1, 1 +.set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1 +.set CYDEV_CHIP_REVISION_5B_ES0, 0 +.set CYDEV_CHIP_REVISION_USED, CYDEV_CHIP_REVISION_5B_PRODUCTION +.set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REV_PSOC5LP_PRODUCTION +.set CYDEV_CHIP_REV_LEOPARD_ES1, 0 +.set CYDEV_CHIP_REV_LEOPARD_ES2, 1 +.set CYDEV_CHIP_REV_LEOPARD_ES3, 3 +.set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3 +.set CYDEV_CHIP_REV_PANTHER_ES0, 0 +.set CYDEV_CHIP_REV_PANTHER_ES1, 1 +.set CYDEV_CHIP_REV_PANTHER_PRODUCTION, 1 +.set CYDEV_CHIP_REV_PSOC4A_ES0, 17 +.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17 +.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0 +.set CYDEV_CONFIGURATION_COMPRESSED, 1 +.set CYDEV_CONFIGURATION_DMA, 0 +.set CYDEV_CONFIGURATION_ECC, 0 +.set CYDEV_CONFIGURATION_IMOENABLED, CYDEV_CONFIG_FASTBOOT_ENABLED +.set CYDEV_CONFIGURATION_MODE, CYDEV_CONFIGURATION_MODE_COMPRESSED +.set CYDEV_CONFIGURATION_MODE_DMA, 2 +.set CYDEV_CONFIGURATION_MODE_UNCOMPRESSED, 1 +.set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_AllowButWarn +.set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1 +.set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2 +.set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD_SWV +.set CYDEV_DEBUGGING_DPS_Disable, 3 +.set CYDEV_DEBUGGING_DPS_JTAG_4, 1 +.set CYDEV_DEBUGGING_DPS_JTAG_5, 0 +.set CYDEV_DEBUGGING_DPS_SWD, 2 +.set CYDEV_DEBUGGING_ENABLE, 1 +.set CYDEV_DEBUGGING_XRES, 0 +.set CYDEV_DEBUG_ENABLE_MASK, 0x20 +.set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG +.set CYDEV_DMA_CHANNELS_AVAILABLE, 24 +.set CYDEV_ECC_ENABLE, 0 +.set CYDEV_HEAP_SIZE, 0x0800 +.set CYDEV_INSTRUCT_CACHE_ENABLED, 1 +.set CYDEV_INTR_RISING, 0x00000000 +.set CYDEV_PROJ_TYPE, 1 +.set CYDEV_PROJ_TYPE_BOOTLOADER, 1 +.set CYDEV_PROJ_TYPE_LOADABLE, 2 +.set CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER, 3 +.set CYDEV_PROJ_TYPE_STANDARD, 0 +.set CYDEV_PROTECTION_ENABLE, 0 +.set CYDEV_STACK_SIZE, 0x2000 +.set CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP, 1 +.set CYDEV_USE_BUNDLED_CMSIS, 1 +.set CYDEV_VARIABLE_VDDA, 0 +.set CYDEV_VDDA_MV, 5000 +.set CYDEV_VDDD_MV, 5000 +.set CYDEV_VDDIO0_MV, 5000 +.set CYDEV_VDDIO1_MV, 5000 +.set CYDEV_VDDIO2_MV, 5000 +.set CYDEV_VDDIO3_MV, 5000 +.set CYDEV_VIO0, 5 +.set CYDEV_VIO0_MV, 5000 +.set CYDEV_VIO1, 5 +.set CYDEV_VIO1_MV, 5000 +.set CYDEV_VIO2, 5 +.set CYDEV_VIO2_MV, 5000 +.set CYDEV_VIO3, 5 +.set CYDEV_VIO3_MV, 5000 +.set CyBtldr_Custom_Interface, CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO +.set CyBtldr_USBFS, CYDEV_BOOTLOADER_IO_COMP_USBFS +.set DMA_CHANNELS_USED__MASK0, 0x00000000 +.set CYDEV_BOOTLOADER_ENABLE, 1 +.endif diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyfitteriar.inc new file mode 100755 index 00000000..a84954a5 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyfitteriar.inc @@ -0,0 +1,1435 @@ +#ifndef INCLUDED_CYFITTERIAR_INC +#define INCLUDED_CYFITTERIAR_INC + INCLUDE cydeviceiar.inc + INCLUDE cydeviceiar_trm.inc + +/* USBFS_bus_reset */ +USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_bus_reset__INTC_MASK EQU 0x800000 +USBFS_bus_reset__INTC_NUMBER EQU 23 +USBFS_bus_reset__INTC_PRIOR_NUM EQU 7 +USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23 +USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* USBFS_arb_int */ +USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_arb_int__INTC_MASK EQU 0x400000 +USBFS_arb_int__INTC_NUMBER EQU 22 +USBFS_arb_int__INTC_PRIOR_NUM EQU 7 +USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22 +USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* USBFS_sof_int */ +USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_sof_int__INTC_MASK EQU 0x200000 +USBFS_sof_int__INTC_NUMBER EQU 21 +USBFS_sof_int__INTC_PRIOR_NUM EQU 7 +USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21 +USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* SCSI_Out_DBx */ +SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG +SCSI_Out_DBx__0__AMUX EQU CYREG_PRT5_AMUX +SCSI_Out_DBx__0__BIE EQU CYREG_PRT5_BIE +SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_Out_DBx__0__BYP EQU CYREG_PRT5_BYP +SCSI_Out_DBx__0__CTL EQU CYREG_PRT5_CTL +SCSI_Out_DBx__0__DM0 EQU CYREG_PRT5_DM0 +SCSI_Out_DBx__0__DM1 EQU CYREG_PRT5_DM1 +SCSI_Out_DBx__0__DM2 EQU CYREG_PRT5_DM2 +SCSI_Out_DBx__0__DR EQU CYREG_PRT5_DR +SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_Out_DBx__0__MASK EQU 0x02 +SCSI_Out_DBx__0__PC EQU CYREG_PRT5_PC1 +SCSI_Out_DBx__0__PORT EQU 5 +SCSI_Out_DBx__0__PRT EQU CYREG_PRT5_PRT +SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_Out_DBx__0__PS EQU CYREG_PRT5_PS +SCSI_Out_DBx__0__SHIFT EQU 1 +SCSI_Out_DBx__0__SLW EQU CYREG_PRT5_SLW +SCSI_Out_DBx__1__AG EQU CYREG_PRT5_AG +SCSI_Out_DBx__1__AMUX EQU CYREG_PRT5_AMUX +SCSI_Out_DBx__1__BIE EQU CYREG_PRT5_BIE +SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_Out_DBx__1__BYP EQU CYREG_PRT5_BYP +SCSI_Out_DBx__1__CTL EQU CYREG_PRT5_CTL +SCSI_Out_DBx__1__DM0 EQU CYREG_PRT5_DM0 +SCSI_Out_DBx__1__DM1 EQU CYREG_PRT5_DM1 +SCSI_Out_DBx__1__DM2 EQU CYREG_PRT5_DM2 +SCSI_Out_DBx__1__DR EQU CYREG_PRT5_DR +SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_Out_DBx__1__MASK EQU 0x01 +SCSI_Out_DBx__1__PC EQU CYREG_PRT5_PC0 +SCSI_Out_DBx__1__PORT EQU 5 +SCSI_Out_DBx__1__PRT EQU CYREG_PRT5_PRT +SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_Out_DBx__1__PS EQU CYREG_PRT5_PS +SCSI_Out_DBx__1__SHIFT EQU 0 +SCSI_Out_DBx__1__SLW EQU CYREG_PRT5_SLW +SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG +SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE +SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP +SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL +SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR +SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out_DBx__2__MASK EQU 0x20 +SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC5 +SCSI_Out_DBx__2__PORT EQU 6 +SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT +SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS +SCSI_Out_DBx__2__SHIFT EQU 5 +SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW +SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG +SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE +SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP +SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL +SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR +SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out_DBx__3__MASK EQU 0x10 +SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC4 +SCSI_Out_DBx__3__PORT EQU 6 +SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT +SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS +SCSI_Out_DBx__3__SHIFT EQU 4 +SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW +SCSI_Out_DBx__4__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__4__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__4__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__4__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__4__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__4__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__4__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__4__MASK EQU 0x80 +SCSI_Out_DBx__4__PC EQU CYREG_PRT2_PC7 +SCSI_Out_DBx__4__PORT EQU 2 +SCSI_Out_DBx__4__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__4__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__4__SHIFT EQU 7 +SCSI_Out_DBx__4__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__5__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__5__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__5__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__5__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__5__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__5__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__5__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__5__MASK EQU 0x40 +SCSI_Out_DBx__5__PC EQU CYREG_PRT2_PC6 +SCSI_Out_DBx__5__PORT EQU 2 +SCSI_Out_DBx__5__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__5__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__5__SHIFT EQU 6 +SCSI_Out_DBx__5__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__6__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__6__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__6__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__6__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__6__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__6__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__6__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__6__MASK EQU 0x08 +SCSI_Out_DBx__6__PC EQU CYREG_PRT2_PC3 +SCSI_Out_DBx__6__PORT EQU 2 +SCSI_Out_DBx__6__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__6__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__6__SHIFT EQU 3 +SCSI_Out_DBx__6__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__7__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__7__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__7__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__7__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__7__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__7__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__7__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__7__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__7__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__7__MASK EQU 0x04 +SCSI_Out_DBx__7__PC EQU CYREG_PRT2_PC2 +SCSI_Out_DBx__7__PORT EQU 2 +SCSI_Out_DBx__7__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__7__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__7__SHIFT EQU 2 +SCSI_Out_DBx__7__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__DB0__AG EQU CYREG_PRT5_AG +SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX +SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT5_BIE +SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT5_BYP +SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT5_CTL +SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT5_DM0 +SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT5_DM1 +SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT5_DM2 +SCSI_Out_DBx__DB0__DR EQU CYREG_PRT5_DR +SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_Out_DBx__DB0__MASK EQU 0x02 +SCSI_Out_DBx__DB0__PC EQU CYREG_PRT5_PC1 +SCSI_Out_DBx__DB0__PORT EQU 5 +SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT5_PRT +SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_Out_DBx__DB0__PS EQU CYREG_PRT5_PS +SCSI_Out_DBx__DB0__SHIFT EQU 1 +SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT5_SLW +SCSI_Out_DBx__DB1__AG EQU CYREG_PRT5_AG +SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX +SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT5_BIE +SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT5_BYP +SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT5_CTL +SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT5_DM0 +SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT5_DM1 +SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT5_DM2 +SCSI_Out_DBx__DB1__DR EQU CYREG_PRT5_DR +SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_Out_DBx__DB1__MASK EQU 0x01 +SCSI_Out_DBx__DB1__PC EQU CYREG_PRT5_PC0 +SCSI_Out_DBx__DB1__PORT EQU 5 +SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT5_PRT +SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_Out_DBx__DB1__PS EQU CYREG_PRT5_PS +SCSI_Out_DBx__DB1__SHIFT EQU 0 +SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT5_SLW +SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG +SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE +SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP +SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL +SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR +SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out_DBx__DB2__MASK EQU 0x20 +SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC5 +SCSI_Out_DBx__DB2__PORT EQU 6 +SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT +SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS +SCSI_Out_DBx__DB2__SHIFT EQU 5 +SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW +SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG +SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE +SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP +SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL +SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR +SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out_DBx__DB3__MASK EQU 0x10 +SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC4 +SCSI_Out_DBx__DB3__PORT EQU 6 +SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT +SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS +SCSI_Out_DBx__DB3__SHIFT EQU 4 +SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW +SCSI_Out_DBx__DB4__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__DB4__MASK EQU 0x80 +SCSI_Out_DBx__DB4__PC EQU CYREG_PRT2_PC7 +SCSI_Out_DBx__DB4__PORT EQU 2 +SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__DB4__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__DB4__SHIFT EQU 7 +SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__DB5__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__DB5__MASK EQU 0x40 +SCSI_Out_DBx__DB5__PC EQU CYREG_PRT2_PC6 +SCSI_Out_DBx__DB5__PORT EQU 2 +SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__DB5__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__DB5__SHIFT EQU 6 +SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__DB6__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__DB6__MASK EQU 0x08 +SCSI_Out_DBx__DB6__PC EQU CYREG_PRT2_PC3 +SCSI_Out_DBx__DB6__PORT EQU 2 +SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__DB6__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__DB6__SHIFT EQU 3 +SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__DB7__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__DB7__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__DB7__MASK EQU 0x04 +SCSI_Out_DBx__DB7__PC EQU CYREG_PRT2_PC2 +SCSI_Out_DBx__DB7__PORT EQU 2 +SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__DB7__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__DB7__SHIFT EQU 2 +SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT2_SLW + +/* USBFS_dp_int */ +USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_dp_int__INTC_MASK EQU 0x1000 +USBFS_dp_int__INTC_NUMBER EQU 12 +USBFS_dp_int__INTC_PRIOR_NUM EQU 7 +USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12 +USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* USBFS_ep_0 */ +USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_0__INTC_MASK EQU 0x1000000 +USBFS_ep_0__INTC_NUMBER EQU 24 +USBFS_ep_0__INTC_PRIOR_NUM EQU 7 +USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24 +USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* USBFS_ep_1 */ +USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_1__INTC_MASK EQU 0x01 +USBFS_ep_1__INTC_NUMBER EQU 0 +USBFS_ep_1__INTC_PRIOR_NUM EQU 7 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 +USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* USBFS_ep_2 */ +USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_2__INTC_MASK EQU 0x02 +USBFS_ep_2__INTC_NUMBER EQU 1 +USBFS_ep_2__INTC_PRIOR_NUM EQU 7 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 +USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* SD_PULLUP */ +SD_PULLUP__0__MASK EQU 0x02 +SD_PULLUP__0__PC EQU CYREG_PRT3_PC1 +SD_PULLUP__0__PORT EQU 3 +SD_PULLUP__0__SHIFT EQU 1 +SD_PULLUP__1__MASK EQU 0x04 +SD_PULLUP__1__PC EQU CYREG_PRT3_PC2 +SD_PULLUP__1__PORT EQU 3 +SD_PULLUP__1__SHIFT EQU 2 +SD_PULLUP__2__MASK EQU 0x08 +SD_PULLUP__2__PC EQU CYREG_PRT3_PC3 +SD_PULLUP__2__PORT EQU 3 +SD_PULLUP__2__SHIFT EQU 3 +SD_PULLUP__3__MASK EQU 0x10 +SD_PULLUP__3__PC EQU CYREG_PRT3_PC4 +SD_PULLUP__3__PORT EQU 3 +SD_PULLUP__3__SHIFT EQU 4 +SD_PULLUP__4__MASK EQU 0x20 +SD_PULLUP__4__PC EQU CYREG_PRT3_PC5 +SD_PULLUP__4__PORT EQU 3 +SD_PULLUP__4__SHIFT EQU 5 +SD_PULLUP__AG EQU CYREG_PRT3_AG +SD_PULLUP__AMUX EQU CYREG_PRT3_AMUX +SD_PULLUP__BIE EQU CYREG_PRT3_BIE +SD_PULLUP__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_PULLUP__BYP EQU CYREG_PRT3_BYP +SD_PULLUP__CTL EQU CYREG_PRT3_CTL +SD_PULLUP__DM0 EQU CYREG_PRT3_DM0 +SD_PULLUP__DM1 EQU CYREG_PRT3_DM1 +SD_PULLUP__DM2 EQU CYREG_PRT3_DM2 +SD_PULLUP__DR EQU CYREG_PRT3_DR +SD_PULLUP__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_PULLUP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_PULLUP__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_PULLUP__MASK EQU 0x3E +SD_PULLUP__PORT EQU 3 +SD_PULLUP__PRT EQU CYREG_PRT3_PRT +SD_PULLUP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_PULLUP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_PULLUP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_PULLUP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_PULLUP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_PULLUP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_PULLUP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_PULLUP__PS EQU CYREG_PRT3_PS +SD_PULLUP__SHIFT EQU 1 +SD_PULLUP__SLW EQU CYREG_PRT3_SLW + +/* USBFS_USB */ +USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG +USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG +USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN +USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR +USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG +USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN +USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR +USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG +USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN +USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR +USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG +USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN +USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR +USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG +USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN +USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR +USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG +USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN +USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR +USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG +USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN +USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR +USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG +USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN +USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR +USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN +USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR +USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR +USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA +USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB +USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA +USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB +USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR +USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA +USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB +USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA +USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB +USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR +USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA +USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB +USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA +USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB +USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR +USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA +USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB +USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA +USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB +USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR +USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA +USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB +USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA +USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB +USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR +USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA +USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB +USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA +USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB +USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR +USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA +USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB +USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA +USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB +USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR +USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA +USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB +USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA +USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB +USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE +USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT +USBFS_USB__CR0 EQU CYREG_USB_CR0 +USBFS_USB__CR1 EQU CYREG_USB_CR1 +USBFS_USB__CWA EQU CYREG_USB_CWA +USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB +USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES +USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB +USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG +USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT +USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR +USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0 +USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1 +USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2 +USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3 +USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4 +USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5 +USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6 +USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7 +USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE +USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE +USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE +USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5 +USBFS_USB__PM_ACT_MSK EQU 0x01 +USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5 +USBFS_USB__PM_STBY_MSK EQU 0x01 +USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0 +USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1 +USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0 +USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0 +USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1 +USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0 +USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0 +USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1 +USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0 +USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0 +USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1 +USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0 +USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0 +USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1 +USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0 +USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0 +USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1 +USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0 +USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0 +USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1 +USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0 +USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0 +USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1 +USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0 +USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN +USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR +USBFS_USB__SOF0 EQU CYREG_USB_SOF0 +USBFS_USB__SOF1 EQU CYREG_USB_SOF1 +USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 +USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 +USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN + +/* SCSI_Out */ +SCSI_Out__0__AG EQU CYREG_PRT15_AG +SCSI_Out__0__AMUX EQU CYREG_PRT15_AMUX +SCSI_Out__0__BIE EQU CYREG_PRT15_BIE +SCSI_Out__0__BIT_MASK EQU CYREG_PRT15_BIT_MASK +SCSI_Out__0__BYP EQU CYREG_PRT15_BYP +SCSI_Out__0__CTL EQU CYREG_PRT15_CTL +SCSI_Out__0__DM0 EQU CYREG_PRT15_DM0 +SCSI_Out__0__DM1 EQU CYREG_PRT15_DM1 +SCSI_Out__0__DM2 EQU CYREG_PRT15_DM2 +SCSI_Out__0__DR EQU CYREG_PRT15_DR +SCSI_Out__0__INP_DIS EQU CYREG_PRT15_INP_DIS +SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +SCSI_Out__0__LCD_EN EQU CYREG_PRT15_LCD_EN +SCSI_Out__0__MASK EQU 0x20 +SCSI_Out__0__PC EQU CYREG_IO_PC_PRT15_PC5 +SCSI_Out__0__PORT EQU 15 +SCSI_Out__0__PRT EQU CYREG_PRT15_PRT +SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +SCSI_Out__0__PS EQU CYREG_PRT15_PS +SCSI_Out__0__SHIFT EQU 5 +SCSI_Out__0__SLW EQU CYREG_PRT15_SLW +SCSI_Out__1__AG EQU CYREG_PRT15_AG +SCSI_Out__1__AMUX EQU CYREG_PRT15_AMUX +SCSI_Out__1__BIE EQU CYREG_PRT15_BIE +SCSI_Out__1__BIT_MASK EQU CYREG_PRT15_BIT_MASK +SCSI_Out__1__BYP EQU CYREG_PRT15_BYP +SCSI_Out__1__CTL EQU CYREG_PRT15_CTL +SCSI_Out__1__DM0 EQU CYREG_PRT15_DM0 +SCSI_Out__1__DM1 EQU CYREG_PRT15_DM1 +SCSI_Out__1__DM2 EQU CYREG_PRT15_DM2 +SCSI_Out__1__DR EQU CYREG_PRT15_DR +SCSI_Out__1__INP_DIS EQU CYREG_PRT15_INP_DIS +SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +SCSI_Out__1__LCD_EN EQU CYREG_PRT15_LCD_EN +SCSI_Out__1__MASK EQU 0x10 +SCSI_Out__1__PC EQU CYREG_IO_PC_PRT15_PC4 +SCSI_Out__1__PORT EQU 15 +SCSI_Out__1__PRT EQU CYREG_PRT15_PRT +SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +SCSI_Out__1__PS EQU CYREG_PRT15_PS +SCSI_Out__1__SHIFT EQU 4 +SCSI_Out__1__SLW EQU CYREG_PRT15_SLW +SCSI_Out__2__AG EQU CYREG_PRT6_AG +SCSI_Out__2__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out__2__BIE EQU CYREG_PRT6_BIE +SCSI_Out__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out__2__BYP EQU CYREG_PRT6_BYP +SCSI_Out__2__CTL EQU CYREG_PRT6_CTL +SCSI_Out__2__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out__2__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out__2__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out__2__DR EQU CYREG_PRT6_DR +SCSI_Out__2__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out__2__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out__2__MASK EQU 0x02 +SCSI_Out__2__PC EQU CYREG_PRT6_PC1 +SCSI_Out__2__PORT EQU 6 +SCSI_Out__2__PRT EQU CYREG_PRT6_PRT +SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out__2__PS EQU CYREG_PRT6_PS +SCSI_Out__2__SHIFT EQU 1 +SCSI_Out__2__SLW EQU CYREG_PRT6_SLW +SCSI_Out__3__AG EQU CYREG_PRT6_AG +SCSI_Out__3__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out__3__BIE EQU CYREG_PRT6_BIE +SCSI_Out__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out__3__BYP EQU CYREG_PRT6_BYP +SCSI_Out__3__CTL EQU CYREG_PRT6_CTL +SCSI_Out__3__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out__3__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out__3__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out__3__DR EQU CYREG_PRT6_DR +SCSI_Out__3__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out__3__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out__3__MASK EQU 0x01 +SCSI_Out__3__PC EQU CYREG_PRT6_PC0 +SCSI_Out__3__PORT EQU 6 +SCSI_Out__3__PRT EQU CYREG_PRT6_PRT +SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out__3__PS EQU CYREG_PRT6_PS +SCSI_Out__3__SHIFT EQU 0 +SCSI_Out__3__SLW EQU CYREG_PRT6_SLW +SCSI_Out__4__AG EQU CYREG_PRT4_AG +SCSI_Out__4__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__4__BIE EQU CYREG_PRT4_BIE +SCSI_Out__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__4__BYP EQU CYREG_PRT4_BYP +SCSI_Out__4__CTL EQU CYREG_PRT4_CTL +SCSI_Out__4__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__4__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__4__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__4__DR EQU CYREG_PRT4_DR +SCSI_Out__4__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__4__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__4__MASK EQU 0x20 +SCSI_Out__4__PC EQU CYREG_PRT4_PC5 +SCSI_Out__4__PORT EQU 4 +SCSI_Out__4__PRT EQU CYREG_PRT4_PRT +SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__4__PS EQU CYREG_PRT4_PS +SCSI_Out__4__SHIFT EQU 5 +SCSI_Out__4__SLW EQU CYREG_PRT4_SLW +SCSI_Out__5__AG EQU CYREG_PRT4_AG +SCSI_Out__5__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__5__BIE EQU CYREG_PRT4_BIE +SCSI_Out__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__5__BYP EQU CYREG_PRT4_BYP +SCSI_Out__5__CTL EQU CYREG_PRT4_CTL +SCSI_Out__5__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__5__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__5__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__5__DR EQU CYREG_PRT4_DR +SCSI_Out__5__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__5__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__5__MASK EQU 0x10 +SCSI_Out__5__PC EQU CYREG_PRT4_PC4 +SCSI_Out__5__PORT EQU 4 +SCSI_Out__5__PRT EQU CYREG_PRT4_PRT +SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__5__PS EQU CYREG_PRT4_PS +SCSI_Out__5__SHIFT EQU 4 +SCSI_Out__5__SLW EQU CYREG_PRT4_SLW +SCSI_Out__6__AG EQU CYREG_PRT0_AG +SCSI_Out__6__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__6__BIE EQU CYREG_PRT0_BIE +SCSI_Out__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__6__BYP EQU CYREG_PRT0_BYP +SCSI_Out__6__CTL EQU CYREG_PRT0_CTL +SCSI_Out__6__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__6__DR EQU CYREG_PRT0_DR +SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__6__MASK EQU 0x80 +SCSI_Out__6__PC EQU CYREG_PRT0_PC7 +SCSI_Out__6__PORT EQU 0 +SCSI_Out__6__PRT EQU CYREG_PRT0_PRT +SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__6__PS EQU CYREG_PRT0_PS +SCSI_Out__6__SHIFT EQU 7 +SCSI_Out__6__SLW EQU CYREG_PRT0_SLW +SCSI_Out__7__AG EQU CYREG_PRT0_AG +SCSI_Out__7__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__7__BIE EQU CYREG_PRT0_BIE +SCSI_Out__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__7__BYP EQU CYREG_PRT0_BYP +SCSI_Out__7__CTL EQU CYREG_PRT0_CTL +SCSI_Out__7__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__7__DR EQU CYREG_PRT0_DR +SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__7__MASK EQU 0x40 +SCSI_Out__7__PC EQU CYREG_PRT0_PC6 +SCSI_Out__7__PORT EQU 0 +SCSI_Out__7__PRT EQU CYREG_PRT0_PRT +SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__7__PS EQU CYREG_PRT0_PS +SCSI_Out__7__SHIFT EQU 6 +SCSI_Out__7__SLW EQU CYREG_PRT0_SLW +SCSI_Out__8__AG EQU CYREG_PRT0_AG +SCSI_Out__8__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__8__BIE EQU CYREG_PRT0_BIE +SCSI_Out__8__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__8__BYP EQU CYREG_PRT0_BYP +SCSI_Out__8__CTL EQU CYREG_PRT0_CTL +SCSI_Out__8__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__8__DR EQU CYREG_PRT0_DR +SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__8__MASK EQU 0x08 +SCSI_Out__8__PC EQU CYREG_PRT0_PC3 +SCSI_Out__8__PORT EQU 0 +SCSI_Out__8__PRT EQU CYREG_PRT0_PRT +SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__8__PS EQU CYREG_PRT0_PS +SCSI_Out__8__SHIFT EQU 3 +SCSI_Out__8__SLW EQU CYREG_PRT0_SLW +SCSI_Out__9__AG EQU CYREG_PRT0_AG +SCSI_Out__9__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__9__BIE EQU CYREG_PRT0_BIE +SCSI_Out__9__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__9__BYP EQU CYREG_PRT0_BYP +SCSI_Out__9__CTL EQU CYREG_PRT0_CTL +SCSI_Out__9__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__9__DR EQU CYREG_PRT0_DR +SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__9__MASK EQU 0x04 +SCSI_Out__9__PC EQU CYREG_PRT0_PC2 +SCSI_Out__9__PORT EQU 0 +SCSI_Out__9__PRT EQU CYREG_PRT0_PRT +SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__9__PS EQU CYREG_PRT0_PS +SCSI_Out__9__SHIFT EQU 2 +SCSI_Out__9__SLW EQU CYREG_PRT0_SLW +SCSI_Out__ACK__AG EQU CYREG_PRT6_AG +SCSI_Out__ACK__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out__ACK__BIE EQU CYREG_PRT6_BIE +SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out__ACK__BYP EQU CYREG_PRT6_BYP +SCSI_Out__ACK__CTL EQU CYREG_PRT6_CTL +SCSI_Out__ACK__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out__ACK__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out__ACK__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out__ACK__DR EQU CYREG_PRT6_DR +SCSI_Out__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out__ACK__MASK EQU 0x01 +SCSI_Out__ACK__PC EQU CYREG_PRT6_PC0 +SCSI_Out__ACK__PORT EQU 6 +SCSI_Out__ACK__PRT EQU CYREG_PRT6_PRT +SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out__ACK__PS EQU CYREG_PRT6_PS +SCSI_Out__ACK__SHIFT EQU 0 +SCSI_Out__ACK__SLW EQU CYREG_PRT6_SLW +SCSI_Out__ATN__AG EQU CYREG_PRT15_AG +SCSI_Out__ATN__AMUX EQU CYREG_PRT15_AMUX +SCSI_Out__ATN__BIE EQU CYREG_PRT15_BIE +SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT15_BIT_MASK +SCSI_Out__ATN__BYP EQU CYREG_PRT15_BYP +SCSI_Out__ATN__CTL EQU CYREG_PRT15_CTL +SCSI_Out__ATN__DM0 EQU CYREG_PRT15_DM0 +SCSI_Out__ATN__DM1 EQU CYREG_PRT15_DM1 +SCSI_Out__ATN__DM2 EQU CYREG_PRT15_DM2 +SCSI_Out__ATN__DR EQU CYREG_PRT15_DR +SCSI_Out__ATN__INP_DIS EQU CYREG_PRT15_INP_DIS +SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +SCSI_Out__ATN__LCD_EN EQU CYREG_PRT15_LCD_EN +SCSI_Out__ATN__MASK EQU 0x10 +SCSI_Out__ATN__PC EQU CYREG_IO_PC_PRT15_PC4 +SCSI_Out__ATN__PORT EQU 15 +SCSI_Out__ATN__PRT EQU CYREG_PRT15_PRT +SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +SCSI_Out__ATN__PS EQU CYREG_PRT15_PS +SCSI_Out__ATN__SHIFT EQU 4 +SCSI_Out__ATN__SLW EQU CYREG_PRT15_SLW +SCSI_Out__BSY__AG EQU CYREG_PRT6_AG +SCSI_Out__BSY__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out__BSY__BIE EQU CYREG_PRT6_BIE +SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out__BSY__BYP EQU CYREG_PRT6_BYP +SCSI_Out__BSY__CTL EQU CYREG_PRT6_CTL +SCSI_Out__BSY__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out__BSY__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out__BSY__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out__BSY__DR EQU CYREG_PRT6_DR +SCSI_Out__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out__BSY__MASK EQU 0x02 +SCSI_Out__BSY__PC EQU CYREG_PRT6_PC1 +SCSI_Out__BSY__PORT EQU 6 +SCSI_Out__BSY__PRT EQU CYREG_PRT6_PRT +SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out__BSY__PS EQU CYREG_PRT6_PS +SCSI_Out__BSY__SHIFT EQU 1 +SCSI_Out__BSY__SLW EQU CYREG_PRT6_SLW +SCSI_Out__CD__AG EQU CYREG_PRT0_AG +SCSI_Out__CD__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__CD__BIE EQU CYREG_PRT0_BIE +SCSI_Out__CD__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__CD__BYP EQU CYREG_PRT0_BYP +SCSI_Out__CD__CTL EQU CYREG_PRT0_CTL +SCSI_Out__CD__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__CD__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__CD__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__CD__DR EQU CYREG_PRT0_DR +SCSI_Out__CD__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__CD__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__CD__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__CD__MASK EQU 0x40 +SCSI_Out__CD__PC EQU CYREG_PRT0_PC6 +SCSI_Out__CD__PORT EQU 0 +SCSI_Out__CD__PRT EQU CYREG_PRT0_PRT +SCSI_Out__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__CD__PS EQU CYREG_PRT0_PS +SCSI_Out__CD__SHIFT EQU 6 +SCSI_Out__CD__SLW EQU CYREG_PRT0_SLW +SCSI_Out__DBP_raw__AG EQU CYREG_PRT15_AG +SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT15_AMUX +SCSI_Out__DBP_raw__BIE EQU CYREG_PRT15_BIE +SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT15_BIT_MASK +SCSI_Out__DBP_raw__BYP EQU CYREG_PRT15_BYP +SCSI_Out__DBP_raw__CTL EQU CYREG_PRT15_CTL +SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT15_DM0 +SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT15_DM1 +SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT15_DM2 +SCSI_Out__DBP_raw__DR EQU CYREG_PRT15_DR +SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT15_INP_DIS +SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT15_LCD_EN +SCSI_Out__DBP_raw__MASK EQU 0x20 +SCSI_Out__DBP_raw__PC EQU CYREG_IO_PC_PRT15_PC5 +SCSI_Out__DBP_raw__PORT EQU 15 +SCSI_Out__DBP_raw__PRT EQU CYREG_PRT15_PRT +SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +SCSI_Out__DBP_raw__PS EQU CYREG_PRT15_PS +SCSI_Out__DBP_raw__SHIFT EQU 5 +SCSI_Out__DBP_raw__SLW EQU CYREG_PRT15_SLW +SCSI_Out__IO_raw__AG EQU CYREG_PRT0_AG +SCSI_Out__IO_raw__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__IO_raw__BIE EQU CYREG_PRT0_BIE +SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__IO_raw__BYP EQU CYREG_PRT0_BYP +SCSI_Out__IO_raw__CTL EQU CYREG_PRT0_CTL +SCSI_Out__IO_raw__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR +SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__IO_raw__MASK EQU 0x04 +SCSI_Out__IO_raw__PC EQU CYREG_PRT0_PC2 +SCSI_Out__IO_raw__PORT EQU 0 +SCSI_Out__IO_raw__PRT EQU CYREG_PRT0_PRT +SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS +SCSI_Out__IO_raw__SHIFT EQU 2 +SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW +SCSI_Out__MSG__AG EQU CYREG_PRT4_AG +SCSI_Out__MSG__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__MSG__BIE EQU CYREG_PRT4_BIE +SCSI_Out__MSG__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__MSG__BYP EQU CYREG_PRT4_BYP +SCSI_Out__MSG__CTL EQU CYREG_PRT4_CTL +SCSI_Out__MSG__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__MSG__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__MSG__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__MSG__DR EQU CYREG_PRT4_DR +SCSI_Out__MSG__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__MSG__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__MSG__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__MSG__MASK EQU 0x10 +SCSI_Out__MSG__PC EQU CYREG_PRT4_PC4 +SCSI_Out__MSG__PORT EQU 4 +SCSI_Out__MSG__PRT EQU CYREG_PRT4_PRT +SCSI_Out__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__MSG__PS EQU CYREG_PRT4_PS +SCSI_Out__MSG__SHIFT EQU 4 +SCSI_Out__MSG__SLW EQU CYREG_PRT4_SLW +SCSI_Out__REQ__AG EQU CYREG_PRT0_AG +SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE +SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__REQ__BYP EQU CYREG_PRT0_BYP +SCSI_Out__REQ__CTL EQU CYREG_PRT0_CTL +SCSI_Out__REQ__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__REQ__DR EQU CYREG_PRT0_DR +SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__REQ__MASK EQU 0x08 +SCSI_Out__REQ__PC EQU CYREG_PRT0_PC3 +SCSI_Out__REQ__PORT EQU 0 +SCSI_Out__REQ__PRT EQU CYREG_PRT0_PRT +SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__REQ__PS EQU CYREG_PRT0_PS +SCSI_Out__REQ__SHIFT EQU 3 +SCSI_Out__REQ__SLW EQU CYREG_PRT0_SLW +SCSI_Out__RST__AG EQU CYREG_PRT4_AG +SCSI_Out__RST__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__RST__BIE EQU CYREG_PRT4_BIE +SCSI_Out__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__RST__BYP EQU CYREG_PRT4_BYP +SCSI_Out__RST__CTL EQU CYREG_PRT4_CTL +SCSI_Out__RST__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__RST__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__RST__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__RST__DR EQU CYREG_PRT4_DR +SCSI_Out__RST__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__RST__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__RST__MASK EQU 0x20 +SCSI_Out__RST__PC EQU CYREG_PRT4_PC5 +SCSI_Out__RST__PORT EQU 4 +SCSI_Out__RST__PRT EQU CYREG_PRT4_PRT +SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__RST__PS EQU CYREG_PRT4_PS +SCSI_Out__RST__SHIFT EQU 5 +SCSI_Out__RST__SLW EQU CYREG_PRT4_SLW +SCSI_Out__SEL__AG EQU CYREG_PRT0_AG +SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE +SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP +SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL +SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__SEL__DR EQU CYREG_PRT0_DR +SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__SEL__MASK EQU 0x80 +SCSI_Out__SEL__PC EQU CYREG_PRT0_PC7 +SCSI_Out__SEL__PORT EQU 0 +SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT +SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__SEL__PS EQU CYREG_PRT0_PS +SCSI_Out__SEL__SHIFT EQU 7 +SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW + +/* USBFS_Dm */ +USBFS_Dm__0__MASK EQU 0x80 +USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 +USBFS_Dm__0__PORT EQU 15 +USBFS_Dm__0__SHIFT EQU 7 +USBFS_Dm__AG EQU CYREG_PRT15_AG +USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dm__BIE EQU CYREG_PRT15_BIE +USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dm__BYP EQU CYREG_PRT15_BYP +USBFS_Dm__CTL EQU CYREG_PRT15_CTL +USBFS_Dm__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dm__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dm__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dm__DR EQU CYREG_PRT15_DR +USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dm__MASK EQU 0x80 +USBFS_Dm__PORT EQU 15 +USBFS_Dm__PRT EQU CYREG_PRT15_PRT +USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dm__PS EQU CYREG_PRT15_PS +USBFS_Dm__SHIFT EQU 7 +USBFS_Dm__SLW EQU CYREG_PRT15_SLW + +/* USBFS_Dp */ +USBFS_Dp__0__MASK EQU 0x40 +USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0 +USBFS_Dp__0__PORT EQU 15 +USBFS_Dp__0__SHIFT EQU 6 +USBFS_Dp__AG EQU CYREG_PRT15_AG +USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dp__BIE EQU CYREG_PRT15_BIE +USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dp__BYP EQU CYREG_PRT15_BYP +USBFS_Dp__CTL EQU CYREG_PRT15_CTL +USBFS_Dp__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dp__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dp__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dp__DR EQU CYREG_PRT15_DR +USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT +USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dp__MASK EQU 0x40 +USBFS_Dp__PORT EQU 15 +USBFS_Dp__PRT EQU CYREG_PRT15_PRT +USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dp__PS EQU CYREG_PRT15_PS +USBFS_Dp__SHIFT EQU 6 +USBFS_Dp__SLW EQU CYREG_PRT15_SLW +USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15 + +/* LED */ +LED__0__MASK EQU 0x02 +LED__0__PC EQU CYREG_PRT0_PC1 +LED__0__PORT EQU 0 +LED__0__SHIFT EQU 1 +LED__AG EQU CYREG_PRT0_AG +LED__AMUX EQU CYREG_PRT0_AMUX +LED__BIE EQU CYREG_PRT0_BIE +LED__BIT_MASK EQU CYREG_PRT0_BIT_MASK +LED__BYP EQU CYREG_PRT0_BYP +LED__CTL EQU CYREG_PRT0_CTL +LED__DM0 EQU CYREG_PRT0_DM0 +LED__DM1 EQU CYREG_PRT0_DM1 +LED__DM2 EQU CYREG_PRT0_DM2 +LED__DR EQU CYREG_PRT0_DR +LED__INP_DIS EQU CYREG_PRT0_INP_DIS +LED__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +LED__LCD_EN EQU CYREG_PRT0_LCD_EN +LED__MASK EQU 0x02 +LED__PORT EQU 0 +LED__PRT EQU CYREG_PRT0_PRT +LED__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +LED__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +LED__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +LED__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +LED__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +LED__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +LED__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +LED__PS EQU CYREG_PRT0_PS +LED__SHIFT EQU 1 +LED__SLW EQU CYREG_PRT0_SLW + +/* Miscellaneous */ +/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */ +CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO EQU 0 +CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6 +CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0 +CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0 +CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1 +CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0 +CYDEV_CHIP_MEMBER_5B EQU 4 +CYDEV_CHIP_FAMILY_PSOC5 EQU 3 +CYDEV_CHIP_DIE_PSOC5LP EQU 4 +CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP +CYDEV_BOOTLOADER_IO_COMP_USBFS EQU 1 +BCLK__BUS_CLK__HZ EQU 64000000 +BCLK__BUS_CLK__KHZ EQU 64000 +BCLK__BUS_CLK__MHZ EQU 64 +CYDEV_BOOTLOADER_APPLICATIONS EQU 1 +CYDEV_BOOTLOADER_CHECKSUM_BASIC EQU 0 +CYDEV_BOOTLOADER_CHECKSUM_CRC EQU 1 +CYDEV_BOOTLOADER_IO_COMP EQU CYDEV_BOOTLOADER_IO_COMP_USBFS +CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT +CYDEV_CHIP_DIE_LEOPARD EQU 1 +CYDEV_CHIP_DIE_PANTHER EQU 3 +CYDEV_CHIP_DIE_PSOC4A EQU 2 +CYDEV_CHIP_DIE_UNKNOWN EQU 0 +CYDEV_CHIP_FAMILY_PSOC3 EQU 1 +CYDEV_CHIP_FAMILY_PSOC4 EQU 2 +CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 +CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5 +CYDEV_CHIP_JTAG_ID EQU 0x2E133069 +CYDEV_CHIP_MEMBER_3A EQU 1 +CYDEV_CHIP_MEMBER_4A EQU 2 +CYDEV_CHIP_MEMBER_5A EQU 3 +CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 +CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B +CYDEV_CHIP_REVISION_3A_ES1 EQU 0 +CYDEV_CHIP_REVISION_3A_ES2 EQU 1 +CYDEV_CHIP_REVISION_3A_ES3 EQU 3 +CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3 +CYDEV_CHIP_REVISION_4A_ES0 EQU 17 +CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_5A_ES0 EQU 0 +CYDEV_CHIP_REVISION_5A_ES1 EQU 1 +CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 +CYDEV_CHIP_REVISION_5B_ES0 EQU 0 +CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION +CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REV_PSOC5LP_PRODUCTION +CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0 +CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1 +CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3 +CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3 +CYDEV_CHIP_REV_PANTHER_ES0 EQU 0 +CYDEV_CHIP_REV_PANTHER_ES1 EQU 1 +CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1 +CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17 +CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17 +CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0 +CYDEV_CONFIGURATION_COMPRESSED EQU 1 +CYDEV_CONFIGURATION_DMA EQU 0 +CYDEV_CONFIGURATION_ECC EQU 0 +CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED +CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED +CYDEV_CONFIGURATION_MODE_DMA EQU 2 +CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1 +CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn +CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1 +CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2 +CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV +CYDEV_DEBUGGING_DPS_Disable EQU 3 +CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1 +CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0 +CYDEV_DEBUGGING_DPS_SWD EQU 2 +CYDEV_DEBUGGING_ENABLE EQU 1 +CYDEV_DEBUGGING_XRES EQU 0 +CYDEV_DEBUG_ENABLE_MASK EQU 0x20 +CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG +CYDEV_DMA_CHANNELS_AVAILABLE EQU 24 +CYDEV_ECC_ENABLE EQU 0 +CYDEV_HEAP_SIZE EQU 0x0800 +CYDEV_INSTRUCT_CACHE_ENABLED EQU 1 +CYDEV_INTR_RISING EQU 0x00000000 +CYDEV_PROJ_TYPE EQU 1 +CYDEV_PROJ_TYPE_BOOTLOADER EQU 1 +CYDEV_PROJ_TYPE_LOADABLE EQU 2 +CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3 +CYDEV_PROJ_TYPE_STANDARD EQU 0 +CYDEV_PROTECTION_ENABLE EQU 0 +CYDEV_STACK_SIZE EQU 0x2000 +CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP EQU 1 +CYDEV_USE_BUNDLED_CMSIS EQU 1 +CYDEV_VARIABLE_VDDA EQU 0 +CYDEV_VDDA_MV EQU 5000 +CYDEV_VDDD_MV EQU 5000 +CYDEV_VDDIO0_MV EQU 5000 +CYDEV_VDDIO1_MV EQU 5000 +CYDEV_VDDIO2_MV EQU 5000 +CYDEV_VDDIO3_MV EQU 5000 +CYDEV_VIO0 EQU 5 +CYDEV_VIO0_MV EQU 5000 +CYDEV_VIO1 EQU 5 +CYDEV_VIO1_MV EQU 5000 +CYDEV_VIO2 EQU 5 +CYDEV_VIO2_MV EQU 5000 +CYDEV_VIO3 EQU 5 +CYDEV_VIO3_MV EQU 5000 +CyBtldr_Custom_Interface EQU CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO +CyBtldr_USBFS EQU CYDEV_BOOTLOADER_IO_COMP_USBFS +DMA_CHANNELS_USED__MASK0 EQU 0x00000000 +CYDEV_BOOTLOADER_ENABLE EQU 1 + +#endif /* INCLUDED_CYFITTERIAR_INC */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyfitterrv.inc new file mode 100755 index 00000000..e03927f0 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -0,0 +1,1435 @@ + IF :LNOT::DEF:INCLUDED_CYFITTERRV_INC +INCLUDED_CYFITTERRV_INC EQU 1 + GET cydevicerv.inc + GET cydevicerv_trm.inc + +; USBFS_bus_reset +USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_bus_reset__INTC_MASK EQU 0x800000 +USBFS_bus_reset__INTC_NUMBER EQU 23 +USBFS_bus_reset__INTC_PRIOR_NUM EQU 7 +USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23 +USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; USBFS_arb_int +USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_arb_int__INTC_MASK EQU 0x400000 +USBFS_arb_int__INTC_NUMBER EQU 22 +USBFS_arb_int__INTC_PRIOR_NUM EQU 7 +USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22 +USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; USBFS_sof_int +USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_sof_int__INTC_MASK EQU 0x200000 +USBFS_sof_int__INTC_NUMBER EQU 21 +USBFS_sof_int__INTC_PRIOR_NUM EQU 7 +USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21 +USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SCSI_Out_DBx +SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG +SCSI_Out_DBx__0__AMUX EQU CYREG_PRT5_AMUX +SCSI_Out_DBx__0__BIE EQU CYREG_PRT5_BIE +SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_Out_DBx__0__BYP EQU CYREG_PRT5_BYP +SCSI_Out_DBx__0__CTL EQU CYREG_PRT5_CTL +SCSI_Out_DBx__0__DM0 EQU CYREG_PRT5_DM0 +SCSI_Out_DBx__0__DM1 EQU CYREG_PRT5_DM1 +SCSI_Out_DBx__0__DM2 EQU CYREG_PRT5_DM2 +SCSI_Out_DBx__0__DR EQU CYREG_PRT5_DR +SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_Out_DBx__0__MASK EQU 0x02 +SCSI_Out_DBx__0__PC EQU CYREG_PRT5_PC1 +SCSI_Out_DBx__0__PORT EQU 5 +SCSI_Out_DBx__0__PRT EQU CYREG_PRT5_PRT +SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_Out_DBx__0__PS EQU CYREG_PRT5_PS +SCSI_Out_DBx__0__SHIFT EQU 1 +SCSI_Out_DBx__0__SLW EQU CYREG_PRT5_SLW +SCSI_Out_DBx__1__AG EQU CYREG_PRT5_AG +SCSI_Out_DBx__1__AMUX EQU CYREG_PRT5_AMUX +SCSI_Out_DBx__1__BIE EQU CYREG_PRT5_BIE +SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_Out_DBx__1__BYP EQU CYREG_PRT5_BYP +SCSI_Out_DBx__1__CTL EQU CYREG_PRT5_CTL +SCSI_Out_DBx__1__DM0 EQU CYREG_PRT5_DM0 +SCSI_Out_DBx__1__DM1 EQU CYREG_PRT5_DM1 +SCSI_Out_DBx__1__DM2 EQU CYREG_PRT5_DM2 +SCSI_Out_DBx__1__DR EQU CYREG_PRT5_DR +SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_Out_DBx__1__MASK EQU 0x01 +SCSI_Out_DBx__1__PC EQU CYREG_PRT5_PC0 +SCSI_Out_DBx__1__PORT EQU 5 +SCSI_Out_DBx__1__PRT EQU CYREG_PRT5_PRT +SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_Out_DBx__1__PS EQU CYREG_PRT5_PS +SCSI_Out_DBx__1__SHIFT EQU 0 +SCSI_Out_DBx__1__SLW EQU CYREG_PRT5_SLW +SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG +SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE +SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP +SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL +SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR +SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out_DBx__2__MASK EQU 0x20 +SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC5 +SCSI_Out_DBx__2__PORT EQU 6 +SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT +SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS +SCSI_Out_DBx__2__SHIFT EQU 5 +SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW +SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG +SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE +SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP +SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL +SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR +SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out_DBx__3__MASK EQU 0x10 +SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC4 +SCSI_Out_DBx__3__PORT EQU 6 +SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT +SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS +SCSI_Out_DBx__3__SHIFT EQU 4 +SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW +SCSI_Out_DBx__4__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__4__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__4__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__4__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__4__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__4__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__4__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__4__MASK EQU 0x80 +SCSI_Out_DBx__4__PC EQU CYREG_PRT2_PC7 +SCSI_Out_DBx__4__PORT EQU 2 +SCSI_Out_DBx__4__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__4__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__4__SHIFT EQU 7 +SCSI_Out_DBx__4__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__5__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__5__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__5__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__5__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__5__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__5__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__5__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__5__MASK EQU 0x40 +SCSI_Out_DBx__5__PC EQU CYREG_PRT2_PC6 +SCSI_Out_DBx__5__PORT EQU 2 +SCSI_Out_DBx__5__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__5__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__5__SHIFT EQU 6 +SCSI_Out_DBx__5__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__6__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__6__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__6__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__6__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__6__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__6__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__6__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__6__MASK EQU 0x08 +SCSI_Out_DBx__6__PC EQU CYREG_PRT2_PC3 +SCSI_Out_DBx__6__PORT EQU 2 +SCSI_Out_DBx__6__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__6__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__6__SHIFT EQU 3 +SCSI_Out_DBx__6__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__7__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__7__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__7__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__7__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__7__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__7__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__7__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__7__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__7__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__7__MASK EQU 0x04 +SCSI_Out_DBx__7__PC EQU CYREG_PRT2_PC2 +SCSI_Out_DBx__7__PORT EQU 2 +SCSI_Out_DBx__7__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__7__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__7__SHIFT EQU 2 +SCSI_Out_DBx__7__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__DB0__AG EQU CYREG_PRT5_AG +SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX +SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT5_BIE +SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT5_BYP +SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT5_CTL +SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT5_DM0 +SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT5_DM1 +SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT5_DM2 +SCSI_Out_DBx__DB0__DR EQU CYREG_PRT5_DR +SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_Out_DBx__DB0__MASK EQU 0x02 +SCSI_Out_DBx__DB0__PC EQU CYREG_PRT5_PC1 +SCSI_Out_DBx__DB0__PORT EQU 5 +SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT5_PRT +SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_Out_DBx__DB0__PS EQU CYREG_PRT5_PS +SCSI_Out_DBx__DB0__SHIFT EQU 1 +SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT5_SLW +SCSI_Out_DBx__DB1__AG EQU CYREG_PRT5_AG +SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX +SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT5_BIE +SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT5_BYP +SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT5_CTL +SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT5_DM0 +SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT5_DM1 +SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT5_DM2 +SCSI_Out_DBx__DB1__DR EQU CYREG_PRT5_DR +SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_Out_DBx__DB1__MASK EQU 0x01 +SCSI_Out_DBx__DB1__PC EQU CYREG_PRT5_PC0 +SCSI_Out_DBx__DB1__PORT EQU 5 +SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT5_PRT +SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_Out_DBx__DB1__PS EQU CYREG_PRT5_PS +SCSI_Out_DBx__DB1__SHIFT EQU 0 +SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT5_SLW +SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG +SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE +SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP +SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL +SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR +SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out_DBx__DB2__MASK EQU 0x20 +SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC5 +SCSI_Out_DBx__DB2__PORT EQU 6 +SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT +SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS +SCSI_Out_DBx__DB2__SHIFT EQU 5 +SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW +SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG +SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE +SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP +SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL +SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR +SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out_DBx__DB3__MASK EQU 0x10 +SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC4 +SCSI_Out_DBx__DB3__PORT EQU 6 +SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT +SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS +SCSI_Out_DBx__DB3__SHIFT EQU 4 +SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW +SCSI_Out_DBx__DB4__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__DB4__MASK EQU 0x80 +SCSI_Out_DBx__DB4__PC EQU CYREG_PRT2_PC7 +SCSI_Out_DBx__DB4__PORT EQU 2 +SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__DB4__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__DB4__SHIFT EQU 7 +SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__DB5__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__DB5__MASK EQU 0x40 +SCSI_Out_DBx__DB5__PC EQU CYREG_PRT2_PC6 +SCSI_Out_DBx__DB5__PORT EQU 2 +SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__DB5__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__DB5__SHIFT EQU 6 +SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__DB6__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__DB6__MASK EQU 0x08 +SCSI_Out_DBx__DB6__PC EQU CYREG_PRT2_PC3 +SCSI_Out_DBx__DB6__PORT EQU 2 +SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__DB6__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__DB6__SHIFT EQU 3 +SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__DB7__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__DB7__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__DB7__MASK EQU 0x04 +SCSI_Out_DBx__DB7__PC EQU CYREG_PRT2_PC2 +SCSI_Out_DBx__DB7__PORT EQU 2 +SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__DB7__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__DB7__SHIFT EQU 2 +SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT2_SLW + +; USBFS_dp_int +USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_dp_int__INTC_MASK EQU 0x1000 +USBFS_dp_int__INTC_NUMBER EQU 12 +USBFS_dp_int__INTC_PRIOR_NUM EQU 7 +USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12 +USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; USBFS_ep_0 +USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_0__INTC_MASK EQU 0x1000000 +USBFS_ep_0__INTC_NUMBER EQU 24 +USBFS_ep_0__INTC_PRIOR_NUM EQU 7 +USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24 +USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; USBFS_ep_1 +USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_1__INTC_MASK EQU 0x01 +USBFS_ep_1__INTC_NUMBER EQU 0 +USBFS_ep_1__INTC_PRIOR_NUM EQU 7 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 +USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; USBFS_ep_2 +USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_2__INTC_MASK EQU 0x02 +USBFS_ep_2__INTC_NUMBER EQU 1 +USBFS_ep_2__INTC_PRIOR_NUM EQU 7 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 +USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SD_PULLUP +SD_PULLUP__0__MASK EQU 0x02 +SD_PULLUP__0__PC EQU CYREG_PRT3_PC1 +SD_PULLUP__0__PORT EQU 3 +SD_PULLUP__0__SHIFT EQU 1 +SD_PULLUP__1__MASK EQU 0x04 +SD_PULLUP__1__PC EQU CYREG_PRT3_PC2 +SD_PULLUP__1__PORT EQU 3 +SD_PULLUP__1__SHIFT EQU 2 +SD_PULLUP__2__MASK EQU 0x08 +SD_PULLUP__2__PC EQU CYREG_PRT3_PC3 +SD_PULLUP__2__PORT EQU 3 +SD_PULLUP__2__SHIFT EQU 3 +SD_PULLUP__3__MASK EQU 0x10 +SD_PULLUP__3__PC EQU CYREG_PRT3_PC4 +SD_PULLUP__3__PORT EQU 3 +SD_PULLUP__3__SHIFT EQU 4 +SD_PULLUP__4__MASK EQU 0x20 +SD_PULLUP__4__PC EQU CYREG_PRT3_PC5 +SD_PULLUP__4__PORT EQU 3 +SD_PULLUP__4__SHIFT EQU 5 +SD_PULLUP__AG EQU CYREG_PRT3_AG +SD_PULLUP__AMUX EQU CYREG_PRT3_AMUX +SD_PULLUP__BIE EQU CYREG_PRT3_BIE +SD_PULLUP__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_PULLUP__BYP EQU CYREG_PRT3_BYP +SD_PULLUP__CTL EQU CYREG_PRT3_CTL +SD_PULLUP__DM0 EQU CYREG_PRT3_DM0 +SD_PULLUP__DM1 EQU CYREG_PRT3_DM1 +SD_PULLUP__DM2 EQU CYREG_PRT3_DM2 +SD_PULLUP__DR EQU CYREG_PRT3_DR +SD_PULLUP__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_PULLUP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_PULLUP__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_PULLUP__MASK EQU 0x3E +SD_PULLUP__PORT EQU 3 +SD_PULLUP__PRT EQU CYREG_PRT3_PRT +SD_PULLUP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_PULLUP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_PULLUP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_PULLUP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_PULLUP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_PULLUP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_PULLUP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_PULLUP__PS EQU CYREG_PRT3_PS +SD_PULLUP__SHIFT EQU 1 +SD_PULLUP__SLW EQU CYREG_PRT3_SLW + +; USBFS_USB +USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG +USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG +USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN +USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR +USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG +USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN +USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR +USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG +USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN +USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR +USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG +USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN +USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR +USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG +USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN +USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR +USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG +USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN +USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR +USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG +USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN +USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR +USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG +USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN +USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR +USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN +USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR +USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR +USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA +USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB +USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA +USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB +USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR +USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA +USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB +USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA +USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB +USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR +USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA +USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB +USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA +USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB +USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR +USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA +USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB +USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA +USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB +USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR +USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA +USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB +USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA +USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB +USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR +USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA +USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB +USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA +USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB +USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR +USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA +USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB +USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA +USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB +USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR +USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA +USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB +USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA +USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB +USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE +USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT +USBFS_USB__CR0 EQU CYREG_USB_CR0 +USBFS_USB__CR1 EQU CYREG_USB_CR1 +USBFS_USB__CWA EQU CYREG_USB_CWA +USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB +USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES +USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB +USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG +USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT +USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR +USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0 +USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1 +USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2 +USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3 +USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4 +USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5 +USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6 +USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7 +USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE +USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE +USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE +USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5 +USBFS_USB__PM_ACT_MSK EQU 0x01 +USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5 +USBFS_USB__PM_STBY_MSK EQU 0x01 +USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0 +USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1 +USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0 +USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0 +USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1 +USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0 +USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0 +USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1 +USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0 +USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0 +USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1 +USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0 +USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0 +USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1 +USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0 +USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0 +USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1 +USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0 +USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0 +USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1 +USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0 +USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0 +USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1 +USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0 +USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN +USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR +USBFS_USB__SOF0 EQU CYREG_USB_SOF0 +USBFS_USB__SOF1 EQU CYREG_USB_SOF1 +USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 +USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 +USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN + +; SCSI_Out +SCSI_Out__0__AG EQU CYREG_PRT15_AG +SCSI_Out__0__AMUX EQU CYREG_PRT15_AMUX +SCSI_Out__0__BIE EQU CYREG_PRT15_BIE +SCSI_Out__0__BIT_MASK EQU CYREG_PRT15_BIT_MASK +SCSI_Out__0__BYP EQU CYREG_PRT15_BYP +SCSI_Out__0__CTL EQU CYREG_PRT15_CTL +SCSI_Out__0__DM0 EQU CYREG_PRT15_DM0 +SCSI_Out__0__DM1 EQU CYREG_PRT15_DM1 +SCSI_Out__0__DM2 EQU CYREG_PRT15_DM2 +SCSI_Out__0__DR EQU CYREG_PRT15_DR +SCSI_Out__0__INP_DIS EQU CYREG_PRT15_INP_DIS +SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +SCSI_Out__0__LCD_EN EQU CYREG_PRT15_LCD_EN +SCSI_Out__0__MASK EQU 0x20 +SCSI_Out__0__PC EQU CYREG_IO_PC_PRT15_PC5 +SCSI_Out__0__PORT EQU 15 +SCSI_Out__0__PRT EQU CYREG_PRT15_PRT +SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +SCSI_Out__0__PS EQU CYREG_PRT15_PS +SCSI_Out__0__SHIFT EQU 5 +SCSI_Out__0__SLW EQU CYREG_PRT15_SLW +SCSI_Out__1__AG EQU CYREG_PRT15_AG +SCSI_Out__1__AMUX EQU CYREG_PRT15_AMUX +SCSI_Out__1__BIE EQU CYREG_PRT15_BIE +SCSI_Out__1__BIT_MASK EQU CYREG_PRT15_BIT_MASK +SCSI_Out__1__BYP EQU CYREG_PRT15_BYP +SCSI_Out__1__CTL EQU CYREG_PRT15_CTL +SCSI_Out__1__DM0 EQU CYREG_PRT15_DM0 +SCSI_Out__1__DM1 EQU CYREG_PRT15_DM1 +SCSI_Out__1__DM2 EQU CYREG_PRT15_DM2 +SCSI_Out__1__DR EQU CYREG_PRT15_DR +SCSI_Out__1__INP_DIS EQU CYREG_PRT15_INP_DIS +SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +SCSI_Out__1__LCD_EN EQU CYREG_PRT15_LCD_EN +SCSI_Out__1__MASK EQU 0x10 +SCSI_Out__1__PC EQU CYREG_IO_PC_PRT15_PC4 +SCSI_Out__1__PORT EQU 15 +SCSI_Out__1__PRT EQU CYREG_PRT15_PRT +SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +SCSI_Out__1__PS EQU CYREG_PRT15_PS +SCSI_Out__1__SHIFT EQU 4 +SCSI_Out__1__SLW EQU CYREG_PRT15_SLW +SCSI_Out__2__AG EQU CYREG_PRT6_AG +SCSI_Out__2__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out__2__BIE EQU CYREG_PRT6_BIE +SCSI_Out__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out__2__BYP EQU CYREG_PRT6_BYP +SCSI_Out__2__CTL EQU CYREG_PRT6_CTL +SCSI_Out__2__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out__2__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out__2__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out__2__DR EQU CYREG_PRT6_DR +SCSI_Out__2__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out__2__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out__2__MASK EQU 0x02 +SCSI_Out__2__PC EQU CYREG_PRT6_PC1 +SCSI_Out__2__PORT EQU 6 +SCSI_Out__2__PRT EQU CYREG_PRT6_PRT +SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out__2__PS EQU CYREG_PRT6_PS +SCSI_Out__2__SHIFT EQU 1 +SCSI_Out__2__SLW EQU CYREG_PRT6_SLW +SCSI_Out__3__AG EQU CYREG_PRT6_AG +SCSI_Out__3__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out__3__BIE EQU CYREG_PRT6_BIE +SCSI_Out__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out__3__BYP EQU CYREG_PRT6_BYP +SCSI_Out__3__CTL EQU CYREG_PRT6_CTL +SCSI_Out__3__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out__3__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out__3__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out__3__DR EQU CYREG_PRT6_DR +SCSI_Out__3__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out__3__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out__3__MASK EQU 0x01 +SCSI_Out__3__PC EQU CYREG_PRT6_PC0 +SCSI_Out__3__PORT EQU 6 +SCSI_Out__3__PRT EQU CYREG_PRT6_PRT +SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out__3__PS EQU CYREG_PRT6_PS +SCSI_Out__3__SHIFT EQU 0 +SCSI_Out__3__SLW EQU CYREG_PRT6_SLW +SCSI_Out__4__AG EQU CYREG_PRT4_AG +SCSI_Out__4__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__4__BIE EQU CYREG_PRT4_BIE +SCSI_Out__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__4__BYP EQU CYREG_PRT4_BYP +SCSI_Out__4__CTL EQU CYREG_PRT4_CTL +SCSI_Out__4__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__4__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__4__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__4__DR EQU CYREG_PRT4_DR +SCSI_Out__4__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__4__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__4__MASK EQU 0x20 +SCSI_Out__4__PC EQU CYREG_PRT4_PC5 +SCSI_Out__4__PORT EQU 4 +SCSI_Out__4__PRT EQU CYREG_PRT4_PRT +SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__4__PS EQU CYREG_PRT4_PS +SCSI_Out__4__SHIFT EQU 5 +SCSI_Out__4__SLW EQU CYREG_PRT4_SLW +SCSI_Out__5__AG EQU CYREG_PRT4_AG +SCSI_Out__5__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__5__BIE EQU CYREG_PRT4_BIE +SCSI_Out__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__5__BYP EQU CYREG_PRT4_BYP +SCSI_Out__5__CTL EQU CYREG_PRT4_CTL +SCSI_Out__5__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__5__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__5__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__5__DR EQU CYREG_PRT4_DR +SCSI_Out__5__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__5__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__5__MASK EQU 0x10 +SCSI_Out__5__PC EQU CYREG_PRT4_PC4 +SCSI_Out__5__PORT EQU 4 +SCSI_Out__5__PRT EQU CYREG_PRT4_PRT +SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__5__PS EQU CYREG_PRT4_PS +SCSI_Out__5__SHIFT EQU 4 +SCSI_Out__5__SLW EQU CYREG_PRT4_SLW +SCSI_Out__6__AG EQU CYREG_PRT0_AG +SCSI_Out__6__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__6__BIE EQU CYREG_PRT0_BIE +SCSI_Out__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__6__BYP EQU CYREG_PRT0_BYP +SCSI_Out__6__CTL EQU CYREG_PRT0_CTL +SCSI_Out__6__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__6__DR EQU CYREG_PRT0_DR +SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__6__MASK EQU 0x80 +SCSI_Out__6__PC EQU CYREG_PRT0_PC7 +SCSI_Out__6__PORT EQU 0 +SCSI_Out__6__PRT EQU CYREG_PRT0_PRT +SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__6__PS EQU CYREG_PRT0_PS +SCSI_Out__6__SHIFT EQU 7 +SCSI_Out__6__SLW EQU CYREG_PRT0_SLW +SCSI_Out__7__AG EQU CYREG_PRT0_AG +SCSI_Out__7__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__7__BIE EQU CYREG_PRT0_BIE +SCSI_Out__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__7__BYP EQU CYREG_PRT0_BYP +SCSI_Out__7__CTL EQU CYREG_PRT0_CTL +SCSI_Out__7__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__7__DR EQU CYREG_PRT0_DR +SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__7__MASK EQU 0x40 +SCSI_Out__7__PC EQU CYREG_PRT0_PC6 +SCSI_Out__7__PORT EQU 0 +SCSI_Out__7__PRT EQU CYREG_PRT0_PRT +SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__7__PS EQU CYREG_PRT0_PS +SCSI_Out__7__SHIFT EQU 6 +SCSI_Out__7__SLW EQU CYREG_PRT0_SLW +SCSI_Out__8__AG EQU CYREG_PRT0_AG +SCSI_Out__8__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__8__BIE EQU CYREG_PRT0_BIE +SCSI_Out__8__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__8__BYP EQU CYREG_PRT0_BYP +SCSI_Out__8__CTL EQU CYREG_PRT0_CTL +SCSI_Out__8__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__8__DR EQU CYREG_PRT0_DR +SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__8__MASK EQU 0x08 +SCSI_Out__8__PC EQU CYREG_PRT0_PC3 +SCSI_Out__8__PORT EQU 0 +SCSI_Out__8__PRT EQU CYREG_PRT0_PRT +SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__8__PS EQU CYREG_PRT0_PS +SCSI_Out__8__SHIFT EQU 3 +SCSI_Out__8__SLW EQU CYREG_PRT0_SLW +SCSI_Out__9__AG EQU CYREG_PRT0_AG +SCSI_Out__9__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__9__BIE EQU CYREG_PRT0_BIE +SCSI_Out__9__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__9__BYP EQU CYREG_PRT0_BYP +SCSI_Out__9__CTL EQU CYREG_PRT0_CTL +SCSI_Out__9__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__9__DR EQU CYREG_PRT0_DR +SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__9__MASK EQU 0x04 +SCSI_Out__9__PC EQU CYREG_PRT0_PC2 +SCSI_Out__9__PORT EQU 0 +SCSI_Out__9__PRT EQU CYREG_PRT0_PRT +SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__9__PS EQU CYREG_PRT0_PS +SCSI_Out__9__SHIFT EQU 2 +SCSI_Out__9__SLW EQU CYREG_PRT0_SLW +SCSI_Out__ACK__AG EQU CYREG_PRT6_AG +SCSI_Out__ACK__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out__ACK__BIE EQU CYREG_PRT6_BIE +SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out__ACK__BYP EQU CYREG_PRT6_BYP +SCSI_Out__ACK__CTL EQU CYREG_PRT6_CTL +SCSI_Out__ACK__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out__ACK__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out__ACK__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out__ACK__DR EQU CYREG_PRT6_DR +SCSI_Out__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out__ACK__MASK EQU 0x01 +SCSI_Out__ACK__PC EQU CYREG_PRT6_PC0 +SCSI_Out__ACK__PORT EQU 6 +SCSI_Out__ACK__PRT EQU CYREG_PRT6_PRT +SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out__ACK__PS EQU CYREG_PRT6_PS +SCSI_Out__ACK__SHIFT EQU 0 +SCSI_Out__ACK__SLW EQU CYREG_PRT6_SLW +SCSI_Out__ATN__AG EQU CYREG_PRT15_AG +SCSI_Out__ATN__AMUX EQU CYREG_PRT15_AMUX +SCSI_Out__ATN__BIE EQU CYREG_PRT15_BIE +SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT15_BIT_MASK +SCSI_Out__ATN__BYP EQU CYREG_PRT15_BYP +SCSI_Out__ATN__CTL EQU CYREG_PRT15_CTL +SCSI_Out__ATN__DM0 EQU CYREG_PRT15_DM0 +SCSI_Out__ATN__DM1 EQU CYREG_PRT15_DM1 +SCSI_Out__ATN__DM2 EQU CYREG_PRT15_DM2 +SCSI_Out__ATN__DR EQU CYREG_PRT15_DR +SCSI_Out__ATN__INP_DIS EQU CYREG_PRT15_INP_DIS +SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +SCSI_Out__ATN__LCD_EN EQU CYREG_PRT15_LCD_EN +SCSI_Out__ATN__MASK EQU 0x10 +SCSI_Out__ATN__PC EQU CYREG_IO_PC_PRT15_PC4 +SCSI_Out__ATN__PORT EQU 15 +SCSI_Out__ATN__PRT EQU CYREG_PRT15_PRT +SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +SCSI_Out__ATN__PS EQU CYREG_PRT15_PS +SCSI_Out__ATN__SHIFT EQU 4 +SCSI_Out__ATN__SLW EQU CYREG_PRT15_SLW +SCSI_Out__BSY__AG EQU CYREG_PRT6_AG +SCSI_Out__BSY__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out__BSY__BIE EQU CYREG_PRT6_BIE +SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out__BSY__BYP EQU CYREG_PRT6_BYP +SCSI_Out__BSY__CTL EQU CYREG_PRT6_CTL +SCSI_Out__BSY__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out__BSY__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out__BSY__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out__BSY__DR EQU CYREG_PRT6_DR +SCSI_Out__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out__BSY__MASK EQU 0x02 +SCSI_Out__BSY__PC EQU CYREG_PRT6_PC1 +SCSI_Out__BSY__PORT EQU 6 +SCSI_Out__BSY__PRT EQU CYREG_PRT6_PRT +SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out__BSY__PS EQU CYREG_PRT6_PS +SCSI_Out__BSY__SHIFT EQU 1 +SCSI_Out__BSY__SLW EQU CYREG_PRT6_SLW +SCSI_Out__CD__AG EQU CYREG_PRT0_AG +SCSI_Out__CD__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__CD__BIE EQU CYREG_PRT0_BIE +SCSI_Out__CD__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__CD__BYP EQU CYREG_PRT0_BYP +SCSI_Out__CD__CTL EQU CYREG_PRT0_CTL +SCSI_Out__CD__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__CD__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__CD__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__CD__DR EQU CYREG_PRT0_DR +SCSI_Out__CD__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__CD__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__CD__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__CD__MASK EQU 0x40 +SCSI_Out__CD__PC EQU CYREG_PRT0_PC6 +SCSI_Out__CD__PORT EQU 0 +SCSI_Out__CD__PRT EQU CYREG_PRT0_PRT +SCSI_Out__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__CD__PS EQU CYREG_PRT0_PS +SCSI_Out__CD__SHIFT EQU 6 +SCSI_Out__CD__SLW EQU CYREG_PRT0_SLW +SCSI_Out__DBP_raw__AG EQU CYREG_PRT15_AG +SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT15_AMUX +SCSI_Out__DBP_raw__BIE EQU CYREG_PRT15_BIE +SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT15_BIT_MASK +SCSI_Out__DBP_raw__BYP EQU CYREG_PRT15_BYP +SCSI_Out__DBP_raw__CTL EQU CYREG_PRT15_CTL +SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT15_DM0 +SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT15_DM1 +SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT15_DM2 +SCSI_Out__DBP_raw__DR EQU CYREG_PRT15_DR +SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT15_INP_DIS +SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT15_LCD_EN +SCSI_Out__DBP_raw__MASK EQU 0x20 +SCSI_Out__DBP_raw__PC EQU CYREG_IO_PC_PRT15_PC5 +SCSI_Out__DBP_raw__PORT EQU 15 +SCSI_Out__DBP_raw__PRT EQU CYREG_PRT15_PRT +SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +SCSI_Out__DBP_raw__PS EQU CYREG_PRT15_PS +SCSI_Out__DBP_raw__SHIFT EQU 5 +SCSI_Out__DBP_raw__SLW EQU CYREG_PRT15_SLW +SCSI_Out__IO_raw__AG EQU CYREG_PRT0_AG +SCSI_Out__IO_raw__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__IO_raw__BIE EQU CYREG_PRT0_BIE +SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__IO_raw__BYP EQU CYREG_PRT0_BYP +SCSI_Out__IO_raw__CTL EQU CYREG_PRT0_CTL +SCSI_Out__IO_raw__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR +SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__IO_raw__MASK EQU 0x04 +SCSI_Out__IO_raw__PC EQU CYREG_PRT0_PC2 +SCSI_Out__IO_raw__PORT EQU 0 +SCSI_Out__IO_raw__PRT EQU CYREG_PRT0_PRT +SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS +SCSI_Out__IO_raw__SHIFT EQU 2 +SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW +SCSI_Out__MSG__AG EQU CYREG_PRT4_AG +SCSI_Out__MSG__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__MSG__BIE EQU CYREG_PRT4_BIE +SCSI_Out__MSG__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__MSG__BYP EQU CYREG_PRT4_BYP +SCSI_Out__MSG__CTL EQU CYREG_PRT4_CTL +SCSI_Out__MSG__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__MSG__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__MSG__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__MSG__DR EQU CYREG_PRT4_DR +SCSI_Out__MSG__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__MSG__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__MSG__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__MSG__MASK EQU 0x10 +SCSI_Out__MSG__PC EQU CYREG_PRT4_PC4 +SCSI_Out__MSG__PORT EQU 4 +SCSI_Out__MSG__PRT EQU CYREG_PRT4_PRT +SCSI_Out__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__MSG__PS EQU CYREG_PRT4_PS +SCSI_Out__MSG__SHIFT EQU 4 +SCSI_Out__MSG__SLW EQU CYREG_PRT4_SLW +SCSI_Out__REQ__AG EQU CYREG_PRT0_AG +SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE +SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__REQ__BYP EQU CYREG_PRT0_BYP +SCSI_Out__REQ__CTL EQU CYREG_PRT0_CTL +SCSI_Out__REQ__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__REQ__DR EQU CYREG_PRT0_DR +SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__REQ__MASK EQU 0x08 +SCSI_Out__REQ__PC EQU CYREG_PRT0_PC3 +SCSI_Out__REQ__PORT EQU 0 +SCSI_Out__REQ__PRT EQU CYREG_PRT0_PRT +SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__REQ__PS EQU CYREG_PRT0_PS +SCSI_Out__REQ__SHIFT EQU 3 +SCSI_Out__REQ__SLW EQU CYREG_PRT0_SLW +SCSI_Out__RST__AG EQU CYREG_PRT4_AG +SCSI_Out__RST__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__RST__BIE EQU CYREG_PRT4_BIE +SCSI_Out__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__RST__BYP EQU CYREG_PRT4_BYP +SCSI_Out__RST__CTL EQU CYREG_PRT4_CTL +SCSI_Out__RST__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__RST__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__RST__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__RST__DR EQU CYREG_PRT4_DR +SCSI_Out__RST__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__RST__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__RST__MASK EQU 0x20 +SCSI_Out__RST__PC EQU CYREG_PRT4_PC5 +SCSI_Out__RST__PORT EQU 4 +SCSI_Out__RST__PRT EQU CYREG_PRT4_PRT +SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__RST__PS EQU CYREG_PRT4_PS +SCSI_Out__RST__SHIFT EQU 5 +SCSI_Out__RST__SLW EQU CYREG_PRT4_SLW +SCSI_Out__SEL__AG EQU CYREG_PRT0_AG +SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE +SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP +SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL +SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__SEL__DR EQU CYREG_PRT0_DR +SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__SEL__MASK EQU 0x80 +SCSI_Out__SEL__PC EQU CYREG_PRT0_PC7 +SCSI_Out__SEL__PORT EQU 0 +SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT +SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__SEL__PS EQU CYREG_PRT0_PS +SCSI_Out__SEL__SHIFT EQU 7 +SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW + +; USBFS_Dm +USBFS_Dm__0__MASK EQU 0x80 +USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 +USBFS_Dm__0__PORT EQU 15 +USBFS_Dm__0__SHIFT EQU 7 +USBFS_Dm__AG EQU CYREG_PRT15_AG +USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dm__BIE EQU CYREG_PRT15_BIE +USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dm__BYP EQU CYREG_PRT15_BYP +USBFS_Dm__CTL EQU CYREG_PRT15_CTL +USBFS_Dm__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dm__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dm__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dm__DR EQU CYREG_PRT15_DR +USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dm__MASK EQU 0x80 +USBFS_Dm__PORT EQU 15 +USBFS_Dm__PRT EQU CYREG_PRT15_PRT +USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dm__PS EQU CYREG_PRT15_PS +USBFS_Dm__SHIFT EQU 7 +USBFS_Dm__SLW EQU CYREG_PRT15_SLW + +; USBFS_Dp +USBFS_Dp__0__MASK EQU 0x40 +USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0 +USBFS_Dp__0__PORT EQU 15 +USBFS_Dp__0__SHIFT EQU 6 +USBFS_Dp__AG EQU CYREG_PRT15_AG +USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dp__BIE EQU CYREG_PRT15_BIE +USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dp__BYP EQU CYREG_PRT15_BYP +USBFS_Dp__CTL EQU CYREG_PRT15_CTL +USBFS_Dp__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dp__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dp__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dp__DR EQU CYREG_PRT15_DR +USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT +USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dp__MASK EQU 0x40 +USBFS_Dp__PORT EQU 15 +USBFS_Dp__PRT EQU CYREG_PRT15_PRT +USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dp__PS EQU CYREG_PRT15_PS +USBFS_Dp__SHIFT EQU 6 +USBFS_Dp__SLW EQU CYREG_PRT15_SLW +USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15 + +; LED +LED__0__MASK EQU 0x02 +LED__0__PC EQU CYREG_PRT0_PC1 +LED__0__PORT EQU 0 +LED__0__SHIFT EQU 1 +LED__AG EQU CYREG_PRT0_AG +LED__AMUX EQU CYREG_PRT0_AMUX +LED__BIE EQU CYREG_PRT0_BIE +LED__BIT_MASK EQU CYREG_PRT0_BIT_MASK +LED__BYP EQU CYREG_PRT0_BYP +LED__CTL EQU CYREG_PRT0_CTL +LED__DM0 EQU CYREG_PRT0_DM0 +LED__DM1 EQU CYREG_PRT0_DM1 +LED__DM2 EQU CYREG_PRT0_DM2 +LED__DR EQU CYREG_PRT0_DR +LED__INP_DIS EQU CYREG_PRT0_INP_DIS +LED__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +LED__LCD_EN EQU CYREG_PRT0_LCD_EN +LED__MASK EQU 0x02 +LED__PORT EQU 0 +LED__PRT EQU CYREG_PRT0_PRT +LED__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +LED__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +LED__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +LED__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +LED__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +LED__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +LED__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +LED__PS EQU CYREG_PRT0_PS +LED__SHIFT EQU 1 +LED__SLW EQU CYREG_PRT0_SLW + +; Miscellaneous +; -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release +CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO EQU 0 +CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6 +CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0 +CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0 +CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1 +CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0 +CYDEV_CHIP_MEMBER_5B EQU 4 +CYDEV_CHIP_FAMILY_PSOC5 EQU 3 +CYDEV_CHIP_DIE_PSOC5LP EQU 4 +CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP +CYDEV_BOOTLOADER_IO_COMP_USBFS EQU 1 +BCLK__BUS_CLK__HZ EQU 64000000 +BCLK__BUS_CLK__KHZ EQU 64000 +BCLK__BUS_CLK__MHZ EQU 64 +CYDEV_BOOTLOADER_APPLICATIONS EQU 1 +CYDEV_BOOTLOADER_CHECKSUM_BASIC EQU 0 +CYDEV_BOOTLOADER_CHECKSUM_CRC EQU 1 +CYDEV_BOOTLOADER_IO_COMP EQU CYDEV_BOOTLOADER_IO_COMP_USBFS +CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT +CYDEV_CHIP_DIE_LEOPARD EQU 1 +CYDEV_CHIP_DIE_PANTHER EQU 3 +CYDEV_CHIP_DIE_PSOC4A EQU 2 +CYDEV_CHIP_DIE_UNKNOWN EQU 0 +CYDEV_CHIP_FAMILY_PSOC3 EQU 1 +CYDEV_CHIP_FAMILY_PSOC4 EQU 2 +CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 +CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5 +CYDEV_CHIP_JTAG_ID EQU 0x2E133069 +CYDEV_CHIP_MEMBER_3A EQU 1 +CYDEV_CHIP_MEMBER_4A EQU 2 +CYDEV_CHIP_MEMBER_5A EQU 3 +CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 +CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B +CYDEV_CHIP_REVISION_3A_ES1 EQU 0 +CYDEV_CHIP_REVISION_3A_ES2 EQU 1 +CYDEV_CHIP_REVISION_3A_ES3 EQU 3 +CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3 +CYDEV_CHIP_REVISION_4A_ES0 EQU 17 +CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_5A_ES0 EQU 0 +CYDEV_CHIP_REVISION_5A_ES1 EQU 1 +CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 +CYDEV_CHIP_REVISION_5B_ES0 EQU 0 +CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION +CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REV_PSOC5LP_PRODUCTION +CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0 +CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1 +CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3 +CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3 +CYDEV_CHIP_REV_PANTHER_ES0 EQU 0 +CYDEV_CHIP_REV_PANTHER_ES1 EQU 1 +CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1 +CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17 +CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17 +CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0 +CYDEV_CONFIGURATION_COMPRESSED EQU 1 +CYDEV_CONFIGURATION_DMA EQU 0 +CYDEV_CONFIGURATION_ECC EQU 0 +CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED +CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED +CYDEV_CONFIGURATION_MODE_DMA EQU 2 +CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1 +CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn +CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1 +CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2 +CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV +CYDEV_DEBUGGING_DPS_Disable EQU 3 +CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1 +CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0 +CYDEV_DEBUGGING_DPS_SWD EQU 2 +CYDEV_DEBUGGING_ENABLE EQU 1 +CYDEV_DEBUGGING_XRES EQU 0 +CYDEV_DEBUG_ENABLE_MASK EQU 0x20 +CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG +CYDEV_DMA_CHANNELS_AVAILABLE EQU 24 +CYDEV_ECC_ENABLE EQU 0 +CYDEV_HEAP_SIZE EQU 0x0800 +CYDEV_INSTRUCT_CACHE_ENABLED EQU 1 +CYDEV_INTR_RISING EQU 0x00000000 +CYDEV_PROJ_TYPE EQU 1 +CYDEV_PROJ_TYPE_BOOTLOADER EQU 1 +CYDEV_PROJ_TYPE_LOADABLE EQU 2 +CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3 +CYDEV_PROJ_TYPE_STANDARD EQU 0 +CYDEV_PROTECTION_ENABLE EQU 0 +CYDEV_STACK_SIZE EQU 0x2000 +CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP EQU 1 +CYDEV_USE_BUNDLED_CMSIS EQU 1 +CYDEV_VARIABLE_VDDA EQU 0 +CYDEV_VDDA_MV EQU 5000 +CYDEV_VDDD_MV EQU 5000 +CYDEV_VDDIO0_MV EQU 5000 +CYDEV_VDDIO1_MV EQU 5000 +CYDEV_VDDIO2_MV EQU 5000 +CYDEV_VDDIO3_MV EQU 5000 +CYDEV_VIO0 EQU 5 +CYDEV_VIO0_MV EQU 5000 +CYDEV_VIO1 EQU 5 +CYDEV_VIO1_MV EQU 5000 +CYDEV_VIO2 EQU 5 +CYDEV_VIO2_MV EQU 5000 +CYDEV_VIO3 EQU 5 +CYDEV_VIO3_MV EQU 5000 +CyBtldr_Custom_Interface EQU CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO +CyBtldr_USBFS EQU CYDEV_BOOTLOADER_IO_COMP_USBFS +DMA_CHANNELS_USED__MASK0 EQU 0x00000000 +CYDEV_BOOTLOADER_ENABLE EQU 1 + ENDIF + END diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c new file mode 100755 index 00000000..38cbe3ae --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c @@ -0,0 +1,108 @@ +/******************************************************************************* +* FILENAME: cymetadata.c +* +* PSoC Creator 3.0 Component Pack 7 +* +* DESCRIPTION: +* This file defines all extra memory spaces that need to be included. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + + +#include "cytypes.h" + + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +__attribute__ ((__section__(".cyloadermeta"), used)) +#elif defined(__ICCARM__) +#pragma location=".cyloadermeta" +#else +#error "Unsupported toolchain" +#endif +const uint8 cy_meta_loader[] = { + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x01u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u +}; + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +__attribute__ ((__section__(".cyconfigecc"), used)) +#elif defined(__ICCARM__) +#pragma location=".cyconfigecc" +#else +#error "Unsupported toolchain" +#endif +const uint8 cy_meta_configecc[] = { + 0x00u +}; + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +__attribute__ ((__section__(".cycustnvl"), used)) +#elif defined(__ICCARM__) +#pragma location=".cycustnvl" +#else +#error "Unsupported toolchain" +#endif +const uint8 cy_meta_custnvl[] = { + 0x80u, 0x00u, 0x40u, 0x05u +}; + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +__attribute__ ((__section__(".cywolatch"), used)) +#elif defined(__ICCARM__) +#pragma location=".cywolatch" +#else +#error "Unsupported toolchain" +#endif +const uint8 cy_meta_wonvl[] = { + 0xBCu, 0x90u, 0xACu, 0xAFu +}; + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +__attribute__ ((__section__(".cyflashprotect"), used)) +#elif defined(__ICCARM__) +#pragma location=".cyflashprotect" +#else +#error "Unsupported toolchain" +#endif +const uint8 cy_meta_flashprotect[] = { + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u +}; + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +__attribute__ ((__section__(".cymeta"), used)) +#elif defined(__ICCARM__) +#pragma location=".cymeta" +#else +#error "Unsupported toolchain" +#endif +const uint8 cy_metadata[] = { + 0x00u, 0x01u, 0x2Eu, 0x13u, 0x30u, 0x69u, 0x00u, 0x01u, + 0x00u, 0x00u, 0x00u, 0x00u +}; diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cypins.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cypins.h new file mode 100644 index 00000000..6caced2f --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cypins.h @@ -0,0 +1,295 @@ +/******************************************************************************* +* File Name: cypins.h +* Version 4.0 +* +* Description: +* This file contains the function prototypes and constants used for port/pin +* in access and control. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYPINS_H) +#define CY_BOOT_CYPINS_H + +#include "cyfitter.h" +#include "cytypes.h" + + +/************************************** +* API Parameter Constants +**************************************/ + +#define CY_PINS_PC_DRIVE_MODE_SHIFT (0x01u) +#define CY_PINS_PC_DRIVE_MODE_MASK ((uint8)(0x07u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_0 ((uint8)(0x00u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_1 ((uint8)(0x01u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_2 ((uint8)(0x02u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_3 ((uint8)(0x03u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_4 ((uint8)(0x04u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_5 ((uint8)(0x05u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_6 ((uint8)(0x06u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_7 ((uint8)(0x07u << CY_PINS_PC_DRIVE_MODE_SHIFT)) + + +/* SetPinDriveMode */ +#define CY_PINS_DM_ALG_HIZ (CY_PINS_PC_DRIVE_MODE_0) +#define CY_PINS_DM_DIG_HIZ (CY_PINS_PC_DRIVE_MODE_1) +#define CY_PINS_DM_RES_UP (CY_PINS_PC_DRIVE_MODE_2) +#define CY_PINS_DM_RES_DWN (CY_PINS_PC_DRIVE_MODE_3) +#define CY_PINS_DM_OD_LO (CY_PINS_PC_DRIVE_MODE_4) +#define CY_PINS_DM_OD_HI (CY_PINS_PC_DRIVE_MODE_5) +#define CY_PINS_DM_STRONG (CY_PINS_PC_DRIVE_MODE_6) +#define CY_PINS_DM_RES_UPDWN (CY_PINS_PC_DRIVE_MODE_7) + + +/************************************** +* Register Constants +**************************************/ + +/* Port Pin Configuration Register */ +#define CY_PINS_PC_DATAOUT (0x01u) +#define CY_PINS_PC_PIN_FASTSLEW (0xBFu) +#define CY_PINS_PC_PIN_SLOWSLEW (0x40u) +#define CY_PINS_PC_PIN_STATE (0x10u) +#define CY_PINS_PC_BIDIR_EN (0x20u) +#define CY_PINS_PC_SLEW (0x40u) +#define CY_PINS_PC_BYPASS (0x80u) + + +/************************************** +* Pin API Macros +**************************************/ + +/******************************************************************************* +* Macro Name: CyPins_ReadPin +******************************************************************************** +* +* Summary: +* Reads the current value on the pin (pin state, PS). +* +* Parameters: +* pinPC: Port pin configuration register (uint16). +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* Return: +* Pin state +* 0: Logic low value +* Non-0: Logic high value +* +*******************************************************************************/ +#define CyPins_ReadPin(pinPC) ( *(reg8 *)(pinPC) & CY_PINS_PC_PIN_STATE ) + + +/******************************************************************************* +* Macro Name: CyPins_SetPin +******************************************************************************** +* +* Summary: +* Set the output value for the pin (data register, DR) to a logic high. +* +* Note that this only has an effect for pins configured as software pins that +* are not driven by hardware. +* +* Parameters: +* pinPC: Port pin configuration register (uint16). +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* Return: +* None +* +*******************************************************************************/ +#define CyPins_SetPin(pinPC) ( *(reg8 *)(pinPC) |= CY_PINS_PC_DATAOUT) + + +/******************************************************************************* +* Macro Name: CyPins_ClearPin +******************************************************************************** +* +* Summary: +* This macro sets the state of the specified pin to 0 +* +* Parameters: +* pinPC: address of a Pin Configuration register. +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* Return: +* None +* +*******************************************************************************/ +#define CyPins_ClearPin(pinPC) ( *(reg8 *)(pinPC) &= ((uint8)(~CY_PINS_PC_DATAOUT))) + + +/******************************************************************************* +* Macro Name: CyPins_SetPinDriveMode +******************************************************************************** +* +* Summary: +* Sets the drive mode for the pin (DM). +* +* Parameters: +* pinPC: Port pin configuration register (uint16) +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* mode: Desired drive mode +* +* Define Source +* PIN_DM_ALG_HIZ Analog HiZ +* PIN_DM_DIG_HIZ Digital HiZ +* PIN_DM_RES_UP Resistive pull up +* PIN_DM_RES_DWN Resistive pull down +* PIN_DM_OD_LO Open drain - drive low +* PIN_DM_OD_HI Open drain - drive high +* PIN_DM_STRONG Strong CMOS Output +* PIN_DM_RES_UPDWN Resistive pull up/down +* +* Return: +* None +* +*******************************************************************************/ +#define CyPins_SetPinDriveMode(pinPC, mode) \ + ( *(reg8 *)(pinPC) = (*(reg8 *)(pinPC) & ((uint8)(~CY_PINS_PC_DRIVE_MODE_MASK))) | \ + ((mode) & CY_PINS_PC_DRIVE_MODE_MASK)) + + +/******************************************************************************* +* Macro Name: CyPins_ReadPinDriveMode +******************************************************************************** +* +* Summary: +* Reads the drive mode for the pin (DM). +* +* Parameters: +* pinPC: Port pin configuration register (uint16) +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* +* Return: +* mode: Current drive mode for the pin +* +* Define Source +* PIN_DM_ALG_HIZ Analog HiZ +* PIN_DM_DIG_HIZ Digital HiZ +* PIN_DM_RES_UP Resistive pull up +* PIN_DM_RES_DWN Resistive pull down +* PIN_DM_OD_LO Open drain - drive low +* PIN_DM_OD_HI Open drain - drive high +* PIN_DM_STRONG Strong CMOS Output +* PIN_DM_RES_UPDWN Resistive pull up/down +* +*******************************************************************************/ +#define CyPins_ReadPinDriveMode(pinPC) (*(reg8 *)(pinPC) & CY_PINS_PC_DRIVE_MODE_MASK) + + +/******************************************************************************* +* Macro Name: CyPins_FastSlew +******************************************************************************** +* +* Summary: +* Set the slew rate for the pin to fast edge rate. +* Note that this only applies for pins in strong output drive modes, +* not to resistive drive modes. +* +* Parameters: +* pinPC: address of a Pin Configuration register. +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* +* Return: +* None +* +*******************************************************************************/ +#define CyPins_FastSlew(pinPC) (*(reg8 *)(pinPC) = (*(reg8 *)(pinPC) & CY_PINS_PC_PIN_FASTSLEW)) + + +/******************************************************************************* +* Macro Name: CyPins_SlowSlew +******************************************************************************** +* +* Summary: +* Set the slew rate for the pin to slow edge rate. +* Note that this only applies for pins in strong output drive modes, +* not to resistive drive modes. +* +* Parameters: +* pinPC: address of a Pin Configuration register. +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* Return: +* None +* +*******************************************************************************/ +#define CyPins_SlowSlew(pinPC) (*(reg8 *)(pinPC) = (*(reg8 *)(pinPC) | CY_PINS_PC_PIN_SLOWSLEW)) + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from cy_boot 3.30 +*******************************************************************************/ +#define PC_DRIVE_MODE_SHIFT (CY_PINS_PC_DRIVE_MODE_SHIFT) +#define PC_DRIVE_MODE_MASK (CY_PINS_PC_DRIVE_MODE_MASK) +#define PC_DRIVE_MODE_0 (CY_PINS_PC_DRIVE_MODE_0) +#define PC_DRIVE_MODE_1 (CY_PINS_PC_DRIVE_MODE_1) +#define PC_DRIVE_MODE_2 (CY_PINS_PC_DRIVE_MODE_2) +#define PC_DRIVE_MODE_3 (CY_PINS_PC_DRIVE_MODE_3) +#define PC_DRIVE_MODE_4 (CY_PINS_PC_DRIVE_MODE_4) +#define PC_DRIVE_MODE_5 (CY_PINS_PC_DRIVE_MODE_5) +#define PC_DRIVE_MODE_6 (CY_PINS_PC_DRIVE_MODE_6) +#define PC_DRIVE_MODE_7 (CY_PINS_PC_DRIVE_MODE_7) + +#define PIN_DM_ALG_HIZ (CY_PINS_DM_ALG_HIZ) +#define PIN_DM_DIG_HIZ (CY_PINS_DM_DIG_HIZ) +#define PIN_DM_RES_UP (CY_PINS_DM_RES_UP) +#define PIN_DM_RES_DWN (CY_PINS_DM_RES_DWN) +#define PIN_DM_OD_LO (CY_PINS_DM_OD_LO) +#define PIN_DM_OD_HI (CY_PINS_DM_OD_HI) +#define PIN_DM_STRONG (CY_PINS_DM_STRONG) +#define PIN_DM_RES_UPDWN (CY_PINS_DM_RES_UPDWN) + +#define PC_DATAOUT (CY_PINS_PC_DATAOUT) +#define PC_PIN_FASTSLEW (CY_PINS_PC_PIN_FASTSLEW) +#define PC_PIN_SLOWSLEW (CY_PINS_PC_PIN_SLOWSLEW) +#define PC_PIN_STATE (CY_PINS_PC_PIN_STATE) +#define PC_BIDIR_EN (CY_PINS_PC_BIDIR_EN) +#define PC_SLEW (CY_PINS_PC_SLEW) +#define PC_BYPASS (CY_PINS_PC_BYPASS) + +#endif /* (CY_BOOT_CYPINS_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cytypes.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cytypes.h new file mode 100644 index 00000000..24db0621 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cytypes.h @@ -0,0 +1,438 @@ +/******************************************************************************* +* FILENAME: cytypes.h +* Version 4.0 +* +* Description: +* CyTypes provides register access macros and approved types for use in +* firmware. +* +* Note: +* Due to endiannesses of the hardware and some compilers, the register +* access macros for big endian compilers use some library calls to arrange +* data the correct way. +* +* Register Access macros and functions perform their operations on an +* input of type pointer to void. The arguments passed to it should be +* pointers to the type associated with the register size. +* (i.e. a "uint8 *" shouldn't be passed to obtain a 16-bit register value) +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYTYPES_H) +#define CY_BOOT_CYTYPES_H + +#if defined(__C51__) + #include +#endif /* (__C51__) */ + +/* ARM and C99 or later */ +#if defined(__GNUC__) || defined(__ARMCC_VERSION) || (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) + #include +#endif /* (__GNUC__) || defined(__ARMCC_VERSION) || (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) */ + +#include "cyfitter.h" + + +#if defined( __ICCARM__ ) + /* Suppress warning for multiple volatile variables in an expression. */ + /* This is common in component code and the usage is not order dependent. */ + #pragma diag_suppress=Pa082 +#endif /* defined( __ICCARM__ ) */ + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ + + +/******************************************************************************* +* FAMILY encodes the overall architectural family +*******************************************************************************/ +#define CY_PSOC3 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) +#define CY_PSOC4 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) +#define CY_PSOC5 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5) + + +/******************************************************************************* +* MEMBER encodes both the family and the detailed architecture +*******************************************************************************/ +#define CY_PSOC4A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A) +#ifdef CYDEV_CHIP_MEMBER_4D + #define CY_PSOC4D (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D) + #define CY_PSOC4SF (CY_PSOC4D) +#else + #define CY_PSOC4D (0u != 0u) + #define CY_PSOC4SF (CY_PSOC4D) +#endif /* CYDEV_CHIP_MEMBER_4D */ + +#define CY_PSOC5A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A) +#ifdef CYDEV_CHIP_MEMBER_5B + #define CY_PSOC5LP (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5B) +#else + #define CY_PSOC5LP (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_5B */ + + +/******************************************************************************* +* UDB revisions +*******************************************************************************/ +#define CY_UDB_V0 (CY_PSOC5A) +#define CY_UDB_V1 (!CY_UDB_V0) + + +/******************************************************************************* +* Base Types. Acceptable types from MISRA-C specifying signedness and size. +*******************************************************************************/ +typedef unsigned char uint8; +typedef unsigned short uint16; +typedef unsigned long uint32; +typedef signed char int8; +typedef signed short int16; +typedef signed long int32; +typedef float float32; + +#if(!CY_PSOC3) + + typedef double float64; + typedef long long int64; + typedef unsigned long long uint64; + +#endif /* (!CY_PSOC3) */ + +/* Signed or unsigned depending on the compiler selection */ +typedef char char8; + + +/******************************************************************************* +* Memory address functions prototypes +*******************************************************************************/ +#if(CY_PSOC3) + + /*************************************************************************** + * Prototypes for absolute memory address functions (cymem.a51) with built-in + * endian conversion. These functions should be called through the + * CY_GET_XTND_REGxx and CY_SET_XTND_REGxx macros. + ***************************************************************************/ + extern uint8 cyread8 (const volatile void far *addr); + extern void cywrite8 (volatile void far *addr, uint8 value); + + extern uint16 cyread16 (const volatile void far *addr); + extern uint16 cyread16_nodpx(const volatile void far *addr); + + extern void cywrite16 (volatile void far *addr, uint16 value); + extern void cywrite16_nodpx(volatile void far *addr, uint16 value); + + extern uint32 cyread24 (const volatile void far *addr); + extern uint32 cyread24_nodpx(const volatile void far *addr); + + extern void cywrite24 (volatile void far *addr, uint32 value); + extern void cywrite24_nodpx(volatile void far *addr, uint32 value); + + extern uint32 cyread32 (const volatile void far *addr); + extern uint32 cyread32_nodpx(const volatile void far *addr); + + extern void cywrite32 (volatile void far *addr, uint32 value); + extern void cywrite32_nodpx(volatile void far *addr, uint32 value); + + + /*************************************************************************** + * Memory access routines from cymem.a51 for the generated device + * configuration code. These functions may be subject to change in future + * revisions of the cy_boot component and they are not available for all + * devices. Most code should use memset or memcpy instead. + ***************************************************************************/ + void cymemzero(void far *addr, uint16 size); + void cyconfigcpy(uint16 size, const void far *src, void far *dest) large; + void cyconfigcpycode(uint16 size, const void code *src, void far *dest); + + #define CYCONFIGCPY_DECLARED (1) + +#else + + /* Prototype for function to set a 24-bit register. Located at cyutils.c */ + extern void CySetReg24(uint32 volatile * addr, uint32 value); + + #if(CY_PSOC4) + + extern uint32 CyGetReg24(uint32 const volatile * addr); + + #endif /* (CY_PSOC4) */ + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Memory model definitions. To allow code to be 8051-ARM agnostic. +*******************************************************************************/ +#if(CY_PSOC3) + + #define CYBDATA bdata + #define CYBIT bit + #define CYCODE code + #define CYCOMPACT compact + #define CYDATA data + #define CYFAR far + #define CYIDATA idata + #define CYLARGE large + #define CYPDATA pdata + #define CYREENTRANT reentrant + #define CYSMALL small + #define CYXDATA xdata + #define XDATA xdata + + #define CY_NOINIT + +#else + + #define CYBDATA + #define CYBIT uint8 + #define CYCODE + #define CYCOMPACT + #define CYDATA + #define CYFAR + #define CYIDATA + #define CYLARGE + #define CYPDATA + #define CYREENTRANT + #define CYSMALL + #define CYXDATA + #define XDATA + + #if defined(__ARMCC_VERSION) + #define CY_NOINIT __attribute__ ((section(".noinit"), zero_init)) + #define CY_NORETURN __attribute__ ((noreturn)) + #define CY_SECTION(name) __attribute__ ((section(name))) + #define CY_ALIGN(align) __align(align) + #elif defined (__GNUC__) + #define CY_NOINIT __attribute__ ((section(".noinit"))) + #define CY_NORETURN __attribute__ ((noreturn)) + #define CY_SECTION(name) __attribute__ ((section(name))) + #define CY_ALIGN(align) __attribute__ ((aligned(align))) + #elif defined (__ICCARM__) + #define CY_NOINIT __no_init + #define CY_NORETURN __noreturn + #endif /* (__ARMCC_VERSION) */ + +#endif /* (CY_PSOC3) */ + + +#if(CY_PSOC3) + + /* 8051 naturally returns an 8 bit value. */ + typedef unsigned char cystatus; + +#else + + /* ARM naturally returns a 32 bit value. */ + typedef unsigned long cystatus; + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Hardware Register Types. +*******************************************************************************/ +typedef volatile uint8 CYXDATA reg8; +typedef volatile uint16 CYXDATA reg16; +typedef volatile uint32 CYXDATA reg32; + + +/******************************************************************************* +* Interrupt Types and Macros +*******************************************************************************/ +#if(CY_PSOC3) + + #define CY_ISR(FuncName) void FuncName (void) interrupt 0 + #define CY_ISR_PROTO(FuncName) void FuncName (void) + typedef void (CYCODE * cyisraddress)(void); + +#else + + #define CY_ISR(FuncName) void FuncName (void) + #define CY_ISR_PROTO(FuncName) void FuncName (void) + typedef void (* cyisraddress)(void); + + #if defined (__ICCARM__) + typedef union { cyisraddress __fun; void * __ptr; } intvec_elem; + #endif /* defined (__ICCARM__) */ + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Register Access +*******************************************************************************/ +#if(CY_PSOC3) + + + /******************************************************************************* + * KEIL for the 8051 is a big endian compiler This causes problems as the on chip + * registers are little endian. Byte swapping for two and four byte registers is + * implemented in the functions below. This will require conditional compilation + * of function prototypes in code. + *******************************************************************************/ + + /* Access macros for 8, 16, 24 and 32-bit registers, IN THE FIRST 64K OF XDATA */ + + #define CY_GET_REG8(addr) (*((const reg8 *)(addr))) + #define CY_SET_REG8(addr, value) (*((reg8 *)(addr)) = (uint8)(value)) + + #define CY_GET_REG16(addr) cyread16_nodpx ((const volatile void far *)(const reg16 *)(addr)) + #define CY_SET_REG16(addr, value) cywrite16_nodpx((volatile void far *)(reg16 *)(addr), value) + + #define CY_GET_REG24(addr) cyread24_nodpx ((const volatile void far *)(const reg32 *)(addr)) + #define CY_SET_REG24(addr, value) cywrite24_nodpx((volatile void far *)(reg32 *)(addr),value) + + #define CY_GET_REG32(addr) cyread32_nodpx ((const volatile void far *)(const reg32 *)(addr)) + #define CY_SET_REG32(addr, value) cywrite32_nodpx((volatile void far *)(reg32 *)(addr), value) + + /* Access 8, 16, 24 and 32-bit registers, ABOVE THE FIRST 64K OF XDATA */ + #define CY_GET_XTND_REG8(addr) cyread8((const volatile void far *)(addr)) + #define CY_SET_XTND_REG8(addr, value) cywrite8((volatile void far *)(addr), value) + + #define CY_GET_XTND_REG16(addr) cyread16((const volatile void far *)(addr)) + #define CY_SET_XTND_REG16(addr, value) cywrite16((volatile void far *)(addr), value) + + #define CY_GET_XTND_REG24(addr) cyread24((const volatile void far *)(addr)) + #define CY_SET_XTND_REG24(addr, value) cywrite24((volatile void far *)(addr), value) + + #define CY_GET_XTND_REG32(addr) cyread32((const volatile void far *)(addr)) + #define CY_SET_XTND_REG32(addr, value) cywrite32((volatile void far *)(addr), value) + +#else + + /* 8, 16, 24 and 32-bit register access macros */ + #define CY_GET_REG8(addr) (*((const reg8 *)(addr))) + #define CY_SET_REG8(addr, value) (*((reg8 *)(addr)) = (uint8)(value)) + + #define CY_GET_REG16(addr) (*((const reg16 *)(addr))) + #define CY_SET_REG16(addr, value) (*((reg16 *)(addr)) = (uint16)(value)) + + + #define CY_SET_REG24(addr, value) CySetReg24((reg32 *) (addr), (value)) + #if(CY_PSOC4) + #define CY_GET_REG24(addr) CyGetReg24((const reg32 *) (addr)) + #else + #define CY_GET_REG24(addr) (*((const reg32 *)(addr)) & 0x00FFFFFFu) + #endif /* (CY_PSOC4) */ + + + #define CY_GET_REG32(addr) (*((const reg32 *)(addr))) + #define CY_SET_REG32(addr, value) (*((reg32 *)(addr)) = (uint32)(value)) + + + /* To allow code to be 8051-ARM agnostic. */ + #define CY_GET_XTND_REG8(addr) CY_GET_REG8(addr) + #define CY_SET_XTND_REG8(addr, value) CY_SET_REG8(addr, value) + + #define CY_GET_XTND_REG16(addr) CY_GET_REG16(addr) + #define CY_SET_XTND_REG16(addr, value) CY_SET_REG16(addr, value) + + #define CY_GET_XTND_REG24(addr) CY_GET_REG24(addr) + #define CY_SET_XTND_REG24(addr, value) CY_SET_REG24(addr, value) + + #define CY_GET_XTND_REG32(addr) CY_GET_REG32(addr) + #define CY_SET_XTND_REG32(addr, value) CY_SET_REG32(addr, value) + +#endif /* (CY_PSOC3) */ + + + +/******************************************************************************* +* Data manipulation defines +*******************************************************************************/ + +/* Get 8 bits of a 16 bit value. */ +#define LO8(x) ((uint8) ((x) & 0xFFu)) +#define HI8(x) ((uint8) ((uint16)(x) >> 8)) + +/* Get 16 bits of a 32 bit value. */ +#define LO16(x) ((uint16) ((x) & 0xFFFFu)) +#define HI16(x) ((uint16) ((uint32)(x) >> 16)) + +/* Swap the byte ordering of a 32 bit value */ +#define CYSWAP_ENDIAN32(x) \ + ((uint32)(((x) >> 24) | (((x) & 0x00FF0000u) >> 8) | (((x) & 0x0000FF00u) << 8) | ((x) << 24))) + +/* Swap the byte ordering of a 16 bit value */ +#define CYSWAP_ENDIAN16(x) ((uint16)(((x) << 8) | ((x) >> 8))) + + +/******************************************************************************* +* Defines the standard return values used PSoC content. A function is +* not limited to these return values but can use them when returning standard +* error values. Return values can be overloaded if documented in the function +* header. On the 8051 a function can use a larger return type but still use the +* defined return codes. +* +* Zero is successful, all other values indicate some form of failure. 1 - 0x7F - +* standard defined values; 0x80 - ... - user or content defined values. +*******************************************************************************/ +#define CYRET_SUCCESS (0x00u) /* Successful */ +#define CYRET_BAD_PARAM (0x01u) /* One or more invalid parameters */ +#define CYRET_INVALID_OBJECT (0x02u) /* Invalid object specified */ +#define CYRET_MEMORY (0x03u) /* Memory related failure */ +#define CYRET_LOCKED (0x04u) /* Resource lock failure */ +#define CYRET_EMPTY (0x05u) /* No more objects available */ +#define CYRET_BAD_DATA (0x06u) /* Bad data received (CRC or other error check) */ +#define CYRET_STARTED (0x07u) /* Operation started, but not necessarily completed yet */ +#define CYRET_FINISHED (0x08u) /* Operation completed */ +#define CYRET_CANCELED (0x09u) /* Operation canceled */ +#define CYRET_TIMEOUT (0x10u) /* Operation timed out */ +#define CYRET_INVALID_STATE (0x11u) /* Operation not setup or is in an improper state */ +#define CYRET_UNKNOWN ((cystatus) 0xFFFFFFFFu) /* Unknown failure */ + + +/******************************************************************************* +* Intrinsic Defines: Processor NOP instruction +*******************************************************************************/ +#if(CY_PSOC3) + + #define CY_NOP _nop_() + +#else + + #if defined(__ARMCC_VERSION) + + /* RealView */ + #define CY_NOP __nop() + + #else + + /* GCC */ + #define CY_NOP __asm("NOP\n") + + #endif /* defined(__ARMCC_VERSION) */ + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from cy_boot 3.10 +*******************************************************************************/ + +/* Device is PSoC 3 and the revision is ES2 or earlier */ +#define CY_PSOC3_ES2 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \ + (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_3A_ES2)) + +/* Device is PSoC 3 and the revision is ES3 or later */ +#define CY_PSOC3_ES3 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \ + (CYDEV_CHIP_REVISION_USED >= CYDEV_CHIP_REVISION_3A_ES3)) + +/* Device is PSoC 5 and the revision is ES1 or earlier */ +#define CY_PSOC5_ES1 (CY_PSOC5A && \ + (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_5A_ES1)) + +/* Device is PSoC 5 and the revision is ES2 or later */ +#define CY_PSOC5_ES2 (CY_PSOC5A && \ + (CYDEV_CHIP_REVISION_USED > CYDEV_CHIP_REVISION_5A_ES1)) + +#endif /* CY_BOOT_CYTYPES_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyutils.c b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyutils.c new file mode 100644 index 00000000..6d42579a --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/cyutils.c @@ -0,0 +1,87 @@ +/******************************************************************************* +* FILENAME: cyutils.c +* Version 4.0 +* +* Description: +* CyUtils provides function to handle 24-bit value writes. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" + +#if (!CY_PSOC3) + + /*************************************************************************** + * Function Name: CySetReg24 + **************************************************************************** + * + * Summary: + * Writes the 24-bit value to the specified register. + * + * Parameters: + * addr : adress where data must be written + * value: data that must be written + * + * Return: + * None + * + * Reentrant: + * No + * + ***************************************************************************/ + void CySetReg24(uint32 volatile * addr, uint32 value) + { + uint8 volatile *tmpAddr; + + tmpAddr = (uint8 volatile *) addr; + + tmpAddr[0u] = (uint8) value; + tmpAddr[1u] = (uint8) (value >> 8u); + tmpAddr[2u] = (uint8) (value >> 16u); + } + + + #if(CY_PSOC4) + + /*************************************************************************** + * Function Name: CyGetReg24 + **************************************************************************** + * + * Summary: + * Reads the 24-bit value from the specified register. + * + * Parameters: + * addr : adress where data must be read + * + * Return: + * None + * + * Reentrant: + * No + * + ***************************************************************************/ + uint32 CyGetReg24(uint32 const volatile * addr) + { + uint8 const volatile *tmpAddr; + uint32 value; + + tmpAddr = (uint8 const volatile *) addr; + + value = (uint32) tmpAddr[0u]; + value |= ((uint32) tmpAddr[1u] << 8u ); + value |= ((uint32) tmpAddr[2u] << 16u); + + return(value); + } + + #endif /*(CY_PSOC4)*/ + +#endif /* (!CY_PSOC3) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/eeprom.hex b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/eeprom.hex new file mode 100644 index 00000000..e69de29b diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/project.h new file mode 100755 index 00000000..d3473436 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/project.h @@ -0,0 +1,53 @@ +/******************************************************************************* + * File Name: project.h + * PSoC Creator 3.0 Component Pack 7 + * + * Description: + * This file is automatically generated by PSoC Creator and should not + * be edited by hand. + * + * + ******************************************************************************** + * Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. + * You may use this file only in accordance with the license, terms, conditions, + * disclaimers, and limitations in the end user license agreement accompanying + * the software package with which this file was provided. + ********************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/*[]*/ + diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/protect.hex b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/protect.hex new file mode 100644 index 00000000..deab42f1 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/Generated_Source/PSoC5/protect.hex @@ -0,0 +1,3 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p7E1pc{Qn6o{{uR6gMs|F+)_~n66&A*D8N@ea0qqmfu|+N{{h^sroI3G literal 0 HcmV?d00001 diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/bootloader.cyprj b/software/SCSI2SD/pbook/bootloader.cydsn/bootloader.cyprj new file mode 100755 index 00000000..ff4af5c1 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/bootloader.cyprj @@ -0,0 +1,1139 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/bootloader.svd b/software/SCSI2SD/pbook/bootloader.cydsn/bootloader.svd new file mode 100755 index 00000000..97ec4d4a --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/bootloader.svd @@ -0,0 +1,494 @@ + + + CY8C5267AXI_LP051 + 0.1 + CY8C52LP + 8 + 32 + + + USBFS + USBFS + 0x40004394 + + 0 + 0x1D0A + registers + + + + USBFS_PM_USB_CR0 + USB Power Mode Control Register 0 + 0x0 + 8 + read-write + 0 + 0 + + + fsusbio_ref_en + No description available + 0 + 0 + read-write + + + fsusbio_pd_n + No description available + 1 + 1 + read-write + + + fsusbio_pd_pullup_n + No description available + 2 + 2 + read-write + + + + + USBFS_PM_ACT_CFG + Active Power Mode Configuration Register + 0x11 + 8 + read-write + 0 + 0 + + + USBFS_PM_STBY_CFG + Standby Power Mode Configuration Register + 0x21 + 8 + read-write + 0 + 0 + + + USBFS_PRT_PS + Port Pin State Register + 0xE5D + 8 + read-write + 0 + 0 + + + PinState_DP + No description available + 6 + 6 + read-only + + + PinState_DM + No description available + 7 + 7 + read-only + + + + + USBFS_PRT_DM0 + Port Drive Mode Register + 0xE5E + 8 + read-write + 0 + 0 + + + DriveMode_DP + No description available + 6 + 6 + read-write + + + DriveMode_DM + No description available + 7 + 7 + read-write + + + + + USBFS_PRT_DM1 + Port Drive Mode Register + 0xE5F + 8 + read-write + 0 + 0 + + + PullUp_en_DP + No description available + 6 + 6 + read-write + + + PullUp_en_DM + No description available + 7 + 7 + read-write + + + + + USBFS_PRT_INP_DIS + Input buffer disable override + 0xE64 + 8 + read-write + 0 + 0 + + + seinput_dis_dp + No description available + 6 + 6 + read-write + + + seinput_dis_dm + No description available + 7 + 7 + read-write + + + + + USBFS_EP0_DR0 + bmRequestType + 0x1C6C + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR1 + bRequest + 0x1C6D + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR2 + wValueLo + 0x1C6E + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR3 + wValueHi + 0x1C6F + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR4 + wIndexLo + 0x1C70 + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR5 + wIndexHi + 0x1C71 + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR6 + lengthLo + 0x1C72 + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR7 + lengthHi + 0x1C73 + 8 + read-write + 0 + 0 + + + USBFS_CR0 + USB Control Register 0 + 0x1C74 + 8 + read-write + 0 + 0 + + + device_address + No description available + 6 + 0 + read-only + + + usb_enable + No description available + 7 + 7 + read-write + + + + + USBFS_CR1 + USB Control Register 1 + 0x1C75 + 8 + read-write + 0 + 0 + + + reg_enable + No description available + 0 + 0 + read-write + + + enable_lock + No description available + 1 + 1 + read-write + + + bus_activity + No description available + 2 + 2 + read-write + + + trim_offset_msb + No description available + 3 + 3 + read-write + + + + + USBFS_SIE_EP1_CR0 + The Endpoint1 Control Register + 0x1C7A + 8 + read-write + 0 + 0 + + + USBFS_USBIO_CR0 + USBIO Control Register 0 + 0x1C7C + 8 + read-write + 0 + 0 + + + rd + No description available + 0 + 0 + read-only + + + td + No description available + 5 + 5 + read-write + + + tse0 + No description available + 6 + 6 + read-write + + + ten + No description available + 7 + 7 + read-write + + + + + USBFS_USBIO_CR1 + USBIO Control Register 1 + 0x1C7E + 8 + read-write + 0 + 0 + + + dmo + No description available + 0 + 0 + read-only + + + dpo + No description available + 1 + 1 + read-only + + + usbpuen + No description available + 2 + 2 + read-write + + + iomode + No description available + 5 + 5 + read-write + + + + + USBFS_SIE_EP2_CR0 + The Endpoint2 Control Register + 0x1C8A + 8 + read-write + 0 + 0 + + + USBFS_SIE_EP3_CR0 + The Endpoint3 Control Register + 0x1C9A + 8 + read-write + 0 + 0 + + + USBFS_SIE_EP4_CR0 + The Endpoint4 Control Register + 0x1CAA + 8 + read-write + 0 + 0 + + + USBFS_SIE_EP5_CR0 + The Endpoint5 Control Register + 0x1CBA + 8 + read-write + 0 + 0 + + + USBFS_SIE_EP6_CR0 + The Endpoint6 Control Register + 0x1CCA + 8 + read-write + 0 + 0 + + + USBFS_SIE_EP7_CR0 + The Endpoint7 Control Register + 0x1CDA + 8 + read-write + 0 + 0 + + + USBFS_SIE_EP8_CR0 + The Endpoint8 Control Register + 0x1CEA + 8 + read-write + 0 + 0 + + + USBFS_BUF_SIZE + Dedicated Endpoint Buffer Size Register + 0x1CF8 + 8 + read-write + 0 + 0 + + + USBFS_EP_ACTIVE + Endpoint Active Indication Register + 0x1CFA + 8 + read-write + 0 + 0 + + + USBFS_EP_TYPE + Endpoint Type (IN/OUT) Indication + 0x1CFB + 8 + read-write + 0 + 0 + + + USBFS_USB_CLK_EN + USB Block Clock Enable Register + 0x1D09 + 8 + read-write + 0 + 0 + + + + + \ No newline at end of file diff --git a/software/SCSI2SD/pbook/bootloader.cydsn/main.c b/software/SCSI2SD/pbook/bootloader.cydsn/main.c new file mode 100755 index 00000000..2c2d41d6 --- /dev/null +++ b/software/SCSI2SD/pbook/bootloader.cydsn/main.c @@ -0,0 +1,54 @@ +// Copyright (C) 2013 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . +#include + +static void resetSCSI() +{ + CyPins_ClearPin(SCSI_Out_IO_raw); + CyPins_ClearPin(SCSI_Out_ATN); + CyPins_ClearPin(SCSI_Out_BSY); + CyPins_ClearPin(SCSI_Out_ACK); + CyPins_ClearPin(SCSI_Out_RST); + CyPins_ClearPin(SCSI_Out_SEL); + CyPins_ClearPin(SCSI_Out_REQ); + CyPins_ClearPin(SCSI_Out_MSG); + CyPins_ClearPin(SCSI_Out_CD); + CyPins_ClearPin(SCSI_Out_DBx_DB0); + CyPins_ClearPin(SCSI_Out_DBx_DB1); + CyPins_ClearPin(SCSI_Out_DBx_DB2); + CyPins_ClearPin(SCSI_Out_DBx_DB3); + CyPins_ClearPin(SCSI_Out_DBx_DB4); + CyPins_ClearPin(SCSI_Out_DBx_DB5); + CyPins_ClearPin(SCSI_Out_DBx_DB6); + CyPins_ClearPin(SCSI_Out_DBx_DB7); + CyPins_ClearPin(SCSI_Out_DBP_raw); +} + +void main() +{ + resetSCSI(); + + // The call to the bootloader should not return + CyBtldr_Start(); + + /* CyGlobalIntEnable; */ /* Uncomment this line to enable global interrupts. */ + for(;;) + { + /* Place your application code here. */ + } +} + diff --git a/software/SCSI2SD/pbook/pbook.cydsn/.gitignore b/software/SCSI2SD/pbook/pbook.cydsn/.gitignore new file mode 100644 index 00000000..0cf205ed --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/.gitignore @@ -0,0 +1,7 @@ +codegentemp +CortexM3 +*.Micha_000 +*.rpt +*.pdf +*.html + diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/Bootloadable_1.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/Bootloadable_1.c new file mode 100755 index 00000000..c5058bc0 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/Bootloadable_1.c @@ -0,0 +1,84 @@ +/******************************************************************************* +* File Name: Bootloadable_1.c +* Version 1.20 +* +* Description: +* Provides an API for the Bootloadable application. The API includes a +* single function for starting bootloader. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "Bootloadable_1.h" + + +/******************************************************************************* +* Function Name: Bootloadable_1_Load +******************************************************************************** +* Summary: +* Begins the bootloading algorithm, downloading a new ACD image from the host. +* +* Parameters: +* None +* +* Returns: +* This method will never return. It will load a new application and reset +* the device. +* +*******************************************************************************/ +void Bootloadable_1_Load(void) +{ + /* Schedule Bootloader to start after reset */ + Bootloadable_1_SET_RUN_TYPE(Bootloadable_1_START_BTLDR); + + CySoftwareReset(); +} + + +/******************************************************************************* +* Function Name: Bootloadable_1_SetFlashByte +******************************************************************************** +* Summary: +* Sets byte at specified address in Flash. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void Bootloadable_1_SetFlashByte(uint32 address, uint8 runType) +{ + uint32 flsAddr = address - CYDEV_FLASH_BASE; + uint8 rowData[CYDEV_FLS_ROW_SIZE]; + + #if !(CY_PSOC4) + uint8 arrayId = (uint8)(flsAddr / CYDEV_FLS_SECTOR_SIZE); + #endif /* !(CY_PSOC4) */ + + uint16 rowNum = (uint16)((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE); + uint32 baseAddr = address - (address % CYDEV_FLS_ROW_SIZE); + uint16 idx; + + + for (idx = 0u; idx < CYDEV_FLS_ROW_SIZE; idx++) + { + rowData[idx] = Bootloadable_1_GET_CODE_DATA(baseAddr + idx); + } + rowData[address % CYDEV_FLS_ROW_SIZE] = runType; + + + #if(CY_PSOC4) + (void) CySysFlashWriteRow((uint32)rowNum, rowData); + #else + (void) CyWriteRowData(arrayId, rowNum, rowData); + #endif /* (CY_PSOC4) */ +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/Bootloadable_1.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/Bootloadable_1.h new file mode 100755 index 00000000..437dec25 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/Bootloadable_1.h @@ -0,0 +1,155 @@ +/******************************************************************************* +* File Name: Bootloadable_1.h +* Version 1.20 +* +* Description: +* Provides an API for the Bootloadable application. The API includes a +* single function for starting bootloader. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + + +#ifndef CY_BOOTLOADABLE_Bootloadable_1_H +#define CY_BOOTLOADABLE_Bootloadable_1_H + +#include "cydevice_trm.h" +#include "CyFlash.h" + + +/* Check to see if required defines such as CY_PSOC5LP are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5LP) + #error Component Bootloadable_v1_20 requires cy_boot v3.0 or later +#endif /* !defined (CY_PSOC5LP) */ + + +#ifndef CYDEV_FLASH_BASE + #define CYDEV_FLASH_BASE CYDEV_FLS_BASE + #define CYDEV_FLASH_SIZE CYDEV_FLS_SIZE +#endif /* CYDEV_FLASH_BASE */ + +#if(CY_PSOC3) + #define Bootloadable_1_GET_CODE_DATA(idx) (*((uint8 CYCODE *) (idx))) +#else + #define Bootloadable_1_GET_CODE_DATA(idx) (*((uint8 *)(CYDEV_FLASH_BASE + (idx)))) +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* This variable is used by Bootloader/Bootloadable components to schedule what +* application will be started after software reset. +*******************************************************************************/ +#if (CY_PSOC4) + #if defined(__ARMCC_VERSION) + __attribute__ ((section(".bootloaderruntype"), zero_init)) + #elif defined (__GNUC__) + __attribute__ ((section(".bootloaderruntype"))) + #elif defined (__ICCARM__) + #pragma location=".bootloaderruntype" + #endif /* defined(__ARMCC_VERSION) */ + extern volatile uint32 cyBtldrRunType; +#endif /* (CY_PSOC4) */ + + +/******************************************************************************* +* Get the reason of the device reset +*******************************************************************************/ +#if(CY_PSOC4) + #define Bootloadable_1_RES_CAUSE_RESET_SOFT (0x10u) + #define Bootloadable_1_GET_RUN_TYPE \ + (((CY_GET_REG32(CYREG_RES_CAUSE) & Bootloadable_1_RES_CAUSE_RESET_SOFT) > 0u) \ + ? (cyBtldrRunType) \ + : 0u) +#else + #define Bootloadable_1_GET_RUN_TYPE (CY_GET_REG8(CYREG_RESET_SR0) & \ + (Bootloadable_1_START_BTLDR | Bootloadable_1_START_APP)) +#endif /* (CY_PSOC4) */ + + +/******************************************************************************* +* Schedule Bootloader/Bootloadable to be run after software reset +*******************************************************************************/ +#if(CY_PSOC4) + #define Bootloadable_1_SET_RUN_TYPE(x) (cyBtldrRunType = (x)) +#else + #define Bootloadable_1_SET_RUN_TYPE(x) CY_SET_REG8(CYREG_RESET_SR0, (x)) +#endif /* (CY_PSOC4) */ + + + +/*************************************** +* Function Prototypes +***************************************/ +extern void Bootloadable_1_Load(void) ; + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from version 1.10 +*******************************************************************************/ +#define CYBTDLR_SET_RUN_TYPE(x) Bootloadable_1_SET_RUN_TYPE(x) + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from version 1.20 +*******************************************************************************/ +#define Bootloadable_1_START_APP (0x80u) +#define Bootloadable_1_START_BTLDR (0x40u) +#define Bootloadable_1_META_DATA_SIZE (64u) +#define Bootloadable_1_META_APP_CHECKSUM_OFFSET (0u) + +#if(CY_PSOC3) + + #define Bootloadable_1_APP_ADDRESS uint16 + #define Bootloadable_1_GET_CODE_WORD(idx) (*((uint32 CYCODE *) (idx))) + + /* Offset by 2 from 32 bit start because only need 16 bits */ + #define Bootloadable_1_META_APP_ADDR_OFFSET (3u) + #define Bootloadable_1_META_APP_BL_LAST_ROW_OFFSET (7u) + #define Bootloadable_1_META_APP_BYTE_LEN_OFFSET (11u) + #define Bootloadable_1_META_APP_RUN_TYPE_OFFSET (15u) + +#else + + #define Bootloadable_1_APP_ADDRESS uint32 + #define Bootloadable_1_GET_CODE_WORD(idx) (*((uint32 *)(CYDEV_FLASH_BASE + (idx)))) + + #define Bootloadable_1_META_APP_ADDR_OFFSET (1u) + #define Bootloadable_1_META_APP_BL_LAST_ROW_OFFSET (5u) + #define Bootloadable_1_META_APP_BYTE_LEN_OFFSET (9u) + #define Bootloadable_1_META_APP_RUN_TYPE_OFFSET (13u) + +#endif /* (CY_PSOC3) */ + +#define Bootloadable_1_META_APP_ACTIVE_OFFSET (16u) +#define Bootloadable_1_META_APP_VERIFIED_OFFSET (17u) + +#define Bootloadable_1_META_APP_BL_BUILD_VER_OFFSET (18u) +#define Bootloadable_1_META_APP_ID_OFFSET (20u) +#define Bootloadable_1_META_APP_VER_OFFSET (22u) +#define Bootloadable_1_META_APP_CUST_ID_OFFSET (24u) + +#define Bootloadable_1_SetFlashRunType(runType) \ + Bootloadable_1_SetFlashByte(Bootloadable_1_MD_APP_RUN_ADDR(0), (runType)) + +void Bootloadable_1_SetFlashByte(uint32 address, uint8 runType) ; + +#if(CY_PSOC4) + #define Bootloadable_1_SOFTWARE_RESET CY_SET_REG32(CYREG_CM0_AIRCR, 0x05FA0004u) +#else + #define Bootloadable_1_SOFTWARE_RESET CY_SET_REG8(CYREG_RESET_CR2, 0x01u) +#endif /* (CY_PSOC4) */ + +#if(CY_PSOC4) + extern uint8 appRunType; +#endif /* (CY_PSOC4) */ + + +#endif /* CY_BOOTLOADABLE_Bootloadable_1_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CFG_EEPROM.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CFG_EEPROM.c new file mode 100755 index 00000000..56974822 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CFG_EEPROM.c @@ -0,0 +1,511 @@ +/******************************************************************************* +* File Name: CFG_EEPROM.c +* Version 2.10 +* +* Description: +* Provides the source code to the API for the EEPROM component. +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "CFG_EEPROM.h" + + +#if (CY_PSOC3 || CY_PSOC5LP) + + /******************************************************************************* + * Function Name: CFG_EEPROM_Enable + ******************************************************************************** + * + * Summary: + * Enable the EEPROM. + * + * Parameters: + * None + * + * Return: + * None + * + *******************************************************************************/ + void CFG_EEPROM_Enable(void) + { + CyEEPROM_Start(); + } + + + /******************************************************************************* + * Function Name: CFG_EEPROM_Start + ******************************************************************************** + * + * Summary: + * Starts EEPROM. + * + * Parameters: + * None + * + * Return: + * None + * + *******************************************************************************/ + void CFG_EEPROM_Start(void) + { + /* Enable the EEPROM */ + CFG_EEPROM_Enable(); + } + + + /******************************************************************************* + * Function Name: CFG_EEPROM_Stop + ******************************************************************************** + * + * Summary: + * Stops and powers down EEPROM. + * + * Parameters: + * None + * + * Return: + * None + * + *******************************************************************************/ + void CFG_EEPROM_Stop (void) + { + /* Disable EEPROM */ + CyEEPROM_Stop(); + } + +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + +/******************************************************************************* +* Function Name: CFG_EEPROM_EraseSector +******************************************************************************** +* +* Summary: +* Erases a sector of memory. This function blocks until the operation is +* complete. +* +* Parameters: +* sectorNumber: Sector number to erase. +* +* Return: +* CYRET_SUCCESS, if the operation was successful. +* CYRET_BAD_PARAM, if the parameter sectorNumber out of range. +* CYRET_LOCKED, if the spc is being used. +* CYRET_UNKNOWN, if there was an SPC error. +* +*******************************************************************************/ +cystatus CFG_EEPROM_EraseSector(uint8 sectorNumber) +{ + cystatus status; + + /* Start the SPC */ + CySpcStart(); + + if(sectorNumber < (uint8) CY_EEPROM_NUMBER_ARRAYS) + { + /* See if we can get the SPC. */ + if(CySpcLock() == CYRET_SUCCESS) + { + #if(CY_PSOC5A) + + /* Plan for failure */ + status = CYRET_UNKNOWN; + + /* Command to load a row of data */ + if(CySpcLoadRow(CY_SPC_FIRST_EE_ARRAYID, 0, CYDEV_EEPROM_ROW_SIZE) == CYRET_STARTED) + { + while(CY_SPC_BUSY) + { + /* Wait until SPC becomes idle */ + } + + /* SPC is idle now */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + } + + /* Command to erase a sector */ + if(status == CYRET_SUCCESS) + { + + #endif /* (CY_PSOC5A) */ + + if(CySpcEraseSector(CY_SPC_FIRST_EE_ARRAYID, sectorNumber) == CYRET_STARTED) + { + /* Plan for failure */ + status = CYRET_UNKNOWN; + + while(CY_SPC_BUSY) + { + /* Wait until SPC becomes idle */ + } + + /* SPC is idle now */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + } + else + { + status = CYRET_UNKNOWN; + } + + #if(CY_PSOC5A) + + } + else + { + status = CYRET_UNKNOWN; + } + + #endif /* (CY_PSOC5A) */ + + /* Unlock the SPC so someone else can use it. */ + CySpcUnlock(); + } + else + { + status = CYRET_LOCKED; + } + } + else + { + status = CYRET_BAD_PARAM; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CFG_EEPROM_Write +******************************************************************************** +* +* Summary: +* Writes a row, CYDEV_EEPROM_ROW_SIZE of data to the EEPROM. This is +* a blocking call. It will not return until the function succeeds or fails. +* +* Parameters: +* rowData: Address of the data to write to the EEPROM. +* rowNumber: EEPROM row number to program. +* +* Return: +* CYRET_SUCCESS, if the operation was successful. +* CYRET_BAD_PARAM, if the parameter rowNumber out of range. +* CYRET_LOCKED, if the spc is being used. +* CYRET_UNKNOWN, if there was an SPC error. +* +*******************************************************************************/ +cystatus CFG_EEPROM_Write(const uint8 * rowData, uint8 rowNumber) +{ + cystatus status; + + /* Start the SPC */ + CySpcStart(); + + if(rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS) + { + /* See if we can get the SPC. */ + if(CySpcLock() == CYRET_SUCCESS) + { + /* Plan for failure */ + status = CYRET_UNKNOWN; + + /* Command to load a row of data */ + if(CySpcLoadRow(CY_SPC_FIRST_EE_ARRAYID, rowData, CYDEV_EEPROM_ROW_SIZE) == CYRET_STARTED) + { + while(CY_SPC_BUSY) + { + /* Wait until SPC becomes idle */ + } + + /* SPC is idle now */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + + /* Command to erase and program the row. */ + if(status == CYRET_SUCCESS) + { + if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0], + dieTemperature[1]) == CYRET_STARTED) + { + /* Plan for failure */ + status = CYRET_UNKNOWN; + + while(CY_SPC_BUSY) + { + /* Wait until SPC becomes idle */ + } + + /* SPC is idle now */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + } + else + { + status = CYRET_UNKNOWN; + } + } + else + { + status = CYRET_UNKNOWN; + } + } + + /* Unlock the SPC so someone else can use it. */ + CySpcUnlock(); + } + else + { + status = CYRET_LOCKED; + } + } + else + { + status = CYRET_BAD_PARAM; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CFG_EEPROM_StartWrite +******************************************************************************** +* +* Summary: +* Starts the SPC write function. This function does not block, it returns +* once the command has begun the SPC write function. This function must be used +* in combination with CFG_EEPROM_QueryWrite(). Once this function has +* been called the SPC will be locked until CFG_EEPROM_QueryWrite() +* returns CYRET_SUCCESS. +* +* Parameters: +* rowData: Address of buffer containing a row of data to write to the EEPROM. +* rowNumber: EEPROM row number to program. +* +* Return: +* CYRET_STARTED, if the spc command to write was successfuly started. +* CYRET_BAD_PARAM, if the parameter rowNumber out of range. +* CYRET_LOCKED, if the spc is being used. +* CYRET_UNKNOWN, if there was an SPC error. +* +*******************************************************************************/ +cystatus CFG_EEPROM_StartWrite(const uint8 * rowData, uint8 rowNumber) \ + +{ + cystatus status; + + if(rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS) + { + /* See if we can get the SPC. */ + if(CySpcLock() == CYRET_SUCCESS) + { + /* Plan for failure */ + status = CYRET_UNKNOWN; + + /* Command to load a row of data */ + if(CySpcLoadRow(CY_SPC_FIRST_EE_ARRAYID, rowData, CYDEV_EEPROM_ROW_SIZE) == CYRET_STARTED) + { + while(CY_SPC_BUSY) + { + /* Wait until SPC becomes idle */ + } + + /* SPC is idle now */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + + /* Command to erase and program the row. */ + if(status == CYRET_SUCCESS) + { + if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0], + dieTemperature[1]) == CYRET_STARTED) + { + status = CYRET_STARTED; + } + else + { + status = CYRET_UNKNOWN; + } + } + else + { + status = CYRET_UNKNOWN; + } + } + } + else + { + status = CYRET_LOCKED; + } + } + else + { + status = CYRET_BAD_PARAM; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CFG_EEPROM_QueryWrite +******************************************************************************** +* +* Summary: +* Checks the state of write to EEPROM. This function must be called until +* the return value is not CYRET_STARTED. +* +* Parameters: +* None +* +* Return: +* CYRET_STARTED, if the spc command is still processing. +* CYRET_SUCCESS, if the operation was successful. +* CYRET_UNKNOWN, if there was an SPC error. +* +*******************************************************************************/ +cystatus CFG_EEPROM_QueryWrite(void) +{ + cystatus status; + + /* Check if SPC is idle */ + if(CY_SPC_IDLE) + { + /* SPC is idle now */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + else + { + status = CYRET_UNKNOWN; + } + + /* Unlock the SPC so someone else can use it. */ + CySpcUnlock(); + } + else + { + status = CYRET_STARTED; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CFG_EEPROM_ByteWrite +******************************************************************************** +* +* Summary: +* Writes a byte of data to the EEPROM. This is a blocking call. It will not +* return until the function succeeds or fails. +* +* Parameters: +* dataByte: Byte of data to write to the EEPROM. +* rowNumber: EEPROM row number to program. +* byteNumber: Byte number within the row to program. +* +* Return: +* CYRET_SUCCESS, if the operation was successful. +* CYRET_BAD_PARAM, if the parameter rowNumber or byteNumber out of range. +* CYRET_LOCKED, if the spc is being used. +* CYRET_UNKNOWN, if there was an SPC error. +* +*******************************************************************************/ +cystatus CFG_EEPROM_ByteWrite(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \ + +{ + cystatus status; + + /* Start the SPC */ + CySpcStart(); + + if((rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS) && (byteNumber < (uint8) SIZEOF_EEPROM_ROW)) + { + /* See if we can get the SPC. */ + if(CySpcLock() == CYRET_SUCCESS) + { + /* Plan for failure */ + status = CYRET_UNKNOWN; + + /* Command to load a byte of data */ + if(CySpcLoadMultiByte(CY_SPC_FIRST_EE_ARRAYID, (uint16)byteNumber, &dataByte,\ + CFG_EEPROM_SPC_BYTE_WRITE_SIZE) == CYRET_STARTED) + { + while(CY_SPC_BUSY) + { + /* Wait until SPC becomes idle */ + } + + /* SPC is idle now */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + + /* Command to erase and program the row. */ + if(status == CYRET_SUCCESS) + { + if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0], + dieTemperature[1]) == CYRET_STARTED) + { + /* Plan for failure */ + status = CYRET_UNKNOWN; + + while(CY_SPC_BUSY) + { + /* Wait until SPC becomes idle */ + } + + /* SPC is idle now */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + } + else + { + status = CYRET_UNKNOWN; + } + } + else + { + status = CYRET_UNKNOWN; + } + } + + /* Unlock the SPC so someone else can use it. */ + CySpcUnlock(); + } + else + { + status = CYRET_LOCKED; + } + } + else + { + status = CYRET_BAD_PARAM; + } + + return(status); +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CFG_EEPROM.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CFG_EEPROM.h new file mode 100755 index 00000000..836b8e6d --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CFG_EEPROM.h @@ -0,0 +1,60 @@ +/******************************************************************************* +* File Name: CFG_EEPROM.h +* Version 2.10 +* +* Description: +* Provides the function definitions for the EEPROM APIs. +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_EEPROM_CFG_EEPROM_H) +#define CY_EEPROM_CFG_EEPROM_H + +#include "cydevice_trm.h" +#include "CyFlash.h" + +#if !defined(CY_PSOC5LP) + #error Component EEPROM_v2_10 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5LP) */ + + +/*************************************** +* Function Prototypes +***************************************/ + +#if (CY_PSOC3 || CY_PSOC5LP) + void CFG_EEPROM_Enable(void) ; + void CFG_EEPROM_Start(void); + void CFG_EEPROM_Stop(void) ; +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + +cystatus CFG_EEPROM_EraseSector(uint8 sectorNumber) ; +cystatus CFG_EEPROM_Write(const uint8 * rowData, uint8 rowNumber) ; +cystatus CFG_EEPROM_StartWrite(const uint8 * rowData, uint8 rowNumber) \ + ; +cystatus CFG_EEPROM_QueryWrite(void) ; +cystatus CFG_EEPROM_ByteWrite(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \ + ; + + +/**************************************** +* API Constants +****************************************/ + +#define CFG_EEPROM_EEPROM_SIZE CYDEV_EE_SIZE +#define CFG_EEPROM_SPC_BYTE_WRITE_SIZE (0x01u) + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from EEPROM 2.10 +*******************************************************************************/ +#define SPC_BYTE_WRITE_SIZE (CFG_EEPROM_SPC_BYTE_WRITE_SIZE) + +#endif /* CY_EEPROM_CFG_EEPROM_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/Cm3Iar.icf b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/Cm3Iar.icf new file mode 100755 index 00000000..061f4f45 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/Cm3Iar.icf @@ -0,0 +1,113 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x0; +define symbol __ICFEDIT_region_ROM_end__ = 131072 - 1; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000 - (32768 / 2); +define symbol __ICFEDIT_region_RAM_end__ = 0x20000000 + (32768 / 2) - 1; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x4000; +define symbol __ICFEDIT_size_heap__ = 0x1000; +/**** End of ICF editor section. ###ICF###*/ + + +/******** Definitions ********/ +define symbol CY_APPL_LOADABLE = 1; +define symbol CY_APPL_LOADER = 0; +define symbol CY_APPL_NUM = 1; +define symbol CY_APPL_MAX = 1; +define symbol CY_METADATA_SIZE = 64; +define symbol CY_EE_IN_BTLDR = 0x00; +define symbol CY_EE_SIZE = 2048; +include "cybootloader.icf"; +if (!CY_APPL_LOADABLE) { + define symbol CYDEV_BTLDR_SIZE = 0; +} + +define symbol CY_FLASH_SIZE = 131072; +define symbol CY_APPL_ORIGIN = 0; +define symbol CY_FLASH_ROW_SIZE = 256; +define symbol CY_ECC_ROW_SIZE = 32; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, last block CSTACK}; + +define block LOADER { readonly section .cybootloader }; +define block APPL with fixed order {readonly section .romvectors, readonly}; + +/* The address of Flash row next after Bootloader image */ +define symbol CY_BTLDR_END = CYDEV_BTLDR_SIZE + + ((CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE) ? + (CY_FLASH_ROW_SIZE - (CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE)) : 0); + +/* The start address of Standard/Loader/Loadable#1 image */ +define symbol CY_APPL1_START = CY_APPL_ORIGIN ? CY_APPL_ORIGIN : CY_BTLDR_END; + +/* The number of metadata records located at the end of Flash */ +define symbol CY_METADATA_CNT = (CY_APPL_NUM == 2) ? 2 : ((CY_APPL_LOADER || CY_APPL_LOADABLE) ? 1 : 0); + +/* The application area size measured in rows */ +define symbol CY_APPL_ROW_CNT = ((CY_FLASH_SIZE - CY_APPL1_START) / CY_FLASH_ROW_SIZE) - CY_METADATA_CNT; + +/* The start address of Loadable#2 image if any */ +define symbol CY_APPL2_START = CY_APPL1_START + (CY_APPL_ROW_CNT / 2 + CY_APPL_ROW_CNT % 2) * CY_FLASH_ROW_SIZE; + +/* The current image (Standard/Loader/Loadable) start address */ +define symbol CY_APPL_START = (CY_APPL_NUM == 1) ? CY_APPL1_START : CY_APPL2_START; + +/* The ECC data placement address */ +define exported symbol CY_ECC_OFFSET = (CY_APPL_START / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE; + +/* The EEPROM offset and size that can be used by current application (Standard/Loader/Loadable) */ +define symbol CY_EE_OFFSET = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? ((CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1)) : 0; +define symbol CY_EE_IN_USE = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? (CY_EE_SIZE / CY_APPL_MAX) : CY_EE_SIZE; + +/* Define EEPROM region */ +define region EEPROM_region = mem:[from (0x90200000 + CY_EE_OFFSET) size CY_EE_IN_USE]; + +/* Define APPL region that will limit application size */ +define region APPL_region = mem:[from CY_APPL_START size CY_APPL_ROW_CNT * CY_FLASH_ROW_SIZE]; + + +/****** Initializations ******/ +initialize by copy { readwrite }; +do not initialize { section .noinit }; +do not initialize { readwrite section .ramvectors }; + +/******** Placements *********/ +".cybootloader" : place at start of ROM_region {block LOADER}; +"APPL" : place at start of APPL_region {block APPL}; + +"RAMVEC" : place at start of RAM_region { readwrite section .ramvectors }; +"readwrite" : place in RAM_region { readwrite }; +"HSTACK" : place at end of RAM_region { block HSTACK}; + +keep { section .cybootloader, + section .cyloadermeta, + section .cyloadablemeta, + section .cyconfigecc, + section .cycustnvl, + section .cywolatch, + section .cyeeprom, + section .cyflashprotect, + section .cymeta }; + +".cyloadermeta" : place at address mem : (CY_APPL_LOADER ? (CY_FLASH_SIZE - CY_METADATA_SIZE) : 0xF0000000) { readonly section .cyloadermeta }; +".cyloadablemeta" : place at address mem : (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) { readonly section .cyloadablemeta }; +".cyconfigecc" : place at address mem : (0x80000000 + CY_ECC_OFFSET) { readonly section .cyconfigecc }; +".cycustnvl" : place at address mem : 0x90000000 { readonly section .cycustnvl }; +".cywolatch" : place at address mem : 0x90100000 { readonly section .cywolatch }; +".cyeeprom" : place in EEPROM_region { readonly section .cyeeprom }; +".cyflashprotect" : place at address mem : 0x90400000 { readonly section .cyflashprotect }; +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +/* EOF */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/Cm3RealView.scat b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/Cm3RealView.scat new file mode 100755 index 00000000..65833c8b --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/Cm3RealView.scat @@ -0,0 +1,190 @@ +#! armcc -E +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************** +;* File Name: Cm3RealView.scat +;* Version 4.0 +;* +;* Description: +;* This Linker Descriptor file describes the memory layout of the PSoC5 +;* device. The memory layout of the final binary and hex images as well as +;* the placement in PSoC5 memory is described. +;* +;* +;* Note: +;* +;* romvectors: Cypress default Interrupt sevice routine vector table. +;* +;* This is the ISR vector table at bootup. Used only for the reset vector. +;* +;* +;* ramvectors: Cypress ram interrupt service routine vector table. +;* +;* This is the ISR vector table used by the application. +;* +;* +;******************************************************************************** +;* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +;* You may use this file only in accordance with the license, terms, conditions, +;* disclaimers, and limitations in the end user license agreement accompanying +;* the software package with which this file was provided. +;********************************************************************************/ +#include "cyfitter.h" + +#define CY_FLASH_SIZE 131072 +#define CY_APPL_ORIGIN 0 +#define CY_FLASH_ROW_SIZE 256 +#define CY_ECC_ROW_SIZE 32 +#define CY_EE_SIZE 2048 +#define CY_METADATA_SIZE 64 + + +; Define application base address +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) + #define CY_APPL_NUM 1 + #define CY_APPL_MAX 1 + #define CY_EE_IN_BTLDR 0 + + #if CY_APPL_ORIGIN + #define APPL1_START CY_APPL_ORIGIN + #else + #define APPL1_START AlignExpr(ImageLimit(CYBOOTLOADER), CY_FLASH_ROW_SIZE) + #endif + + #define APPL_START (APPL1_START + AlignExpr(((CY_FLASH_SIZE - APPL1_START - 2 * CY_FLASH_ROW_SIZE) / 2 ) * (CY_APPL_NUM - 1), CY_FLASH_ROW_SIZE)) + #define ECC_OFFSET ((APPL_START / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE) + #define EE_OFFSET (CY_EE_IN_BTLDR ? 0 : (CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1)) + #define EE_SIZE (CY_EE_IN_BTLDR ? CY_EE_SIZE : (CY_EE_SIZE / CY_APPL_MAX)) + +#else + + #define APPL_START 0 + #define ECC_OFFSET 0 + #define EE_OFFSET 0 + #define EE_SIZE CY_EE_SIZE + +#endif + + +; Place Bootloader at the beginning of Flash +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) + + CYBOOTLOADER 0 + { + .cybootloader +0 + { + * (.cybootloader) + } + } + + #if CY_APPL_ORIGIN + ScatterAssert(APPL_START > LoadLimit(CYBOOTLOADER)) + #endif + +#endif + + +APPLICATION APPL_START (CY_FLASH_SIZE - APPL_START) +{ + VECTORS +0 + { + * (.romvectors) + } + + CODE +0 + { + * (+RO) + } + + ISRVECTORS (0x20000000 - (32768 / 2)) UNINIT + { + * (.ramvectors) + } + + NOINIT_DATA +0 UNINIT + { + * (.noinit) + } + + DATA +0 + { + .ANY (+RW, +ZI) + } + + ARM_LIB_HEAP (0x20000000 + (32768 / 2) - 0x1000 - 0x4000) EMPTY 0x1000 + { + } + + ARM_LIB_STACK (0x20000000 + (32768 / 2)) EMPTY -0x4000 + { + } +} + + +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_BOOTLOADER || CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER) + + CYLOADERMETA (CY_FLASH_SIZE - CY_METADATA_SIZE) + { + .cyloadermeta +0 { * (.cyloadermeta) } + } + +#else + + #if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) + + CYLOADABLEMETA (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) + { + .cyloadablemeta +0 { * (.cyloadablemeta) } + } + + #endif + +#endif + +#if (CYDEV_ECC_ENABLE == 0) + + CYCONFIGECC (0x80000000 + ECC_OFFSET) + { + .cyconfigecc +0 { * (.cyconfigecc) } + } + +#endif + +CYCUSTNVL 0x90000000 +{ + .cycustnvl +0 { * (.cycustnvl) } +} + +CYWOLATCH 0x90100000 +{ + .cywolatch +0 { * (.cywolatch) } +} + +#if defined(CYDEV_ALLOCATE_EEPROM) + + CYEEPROM 0x90200000 + EE_OFFSET (EE_SIZE) + { + .cyeeprom +0 { * (.cyeeprom) } + } + +#endif + +CYFLASHPROTECT 0x90400000 +{ + .cyflashprotect +0 { * (.cyflashprotect) } +} + +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) + + CYLOADERMETA +0 + { + .cyloadermeta +0 { * (.cyloadermeta) } + } + +#endif diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/Cm3Start.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/Cm3Start.c new file mode 100755 index 00000000..14bcbf8d --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/Cm3Start.c @@ -0,0 +1,461 @@ +/******************************************************************************* +* File Name: Cm3Start.c +* Version 4.0 +* +* Description: +* Startup code for the ARM CM3. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "cydevice_trm.h" +#include "cytypes.h" +#include "cyfitter_cfg.h" +#include "CyLib.h" +#include "CyDmac.h" +#include "cyfitter.h" + +#define CY_NUM_INTERRUPTS (32u) +#define CY_NUM_VECTORS (CYINT_IRQ_BASE + CY_NUM_INTERRUPTS) +#define CY_NUM_ROM_VECTORS (4u) +#define CY_NVIC_APINT_PTR ((reg32 *) CYREG_NVIC_APPLN_INTR) +#define CY_NVIC_CFG_CTRL_PTR ((reg32 *) CYREG_NVIC_CFG_CONTROL) +#define CY_NVIC_APINT_PRIGROUP_3_5 (0x00000400u) /* Priority group 3.5 split */ +#define CY_NVIC_APINT_VECTKEY (0x05FA0000u) /* This key is required in order to write the NVIC_APINT register */ +#define CY_NVIC_CFG_STACKALIGN (0x00000200u) /* This specifies that the exception stack must be 8 byte aligned */ + + +/* Extern functions */ +extern void CyBtldr_CheckLaunch(void); + +/* Function prototypes */ +void initialize_psoc(void); +CY_ISR(IntDefaultHandler); +void Reset(void); +CY_ISR(IntDefaultHandler); + +#if defined(__ARMCC_VERSION) + #define INITIAL_STACK_POINTER ((cyisraddress)(uint32)&Image$$ARM_LIB_STACK$$ZI$$Limit) +#elif defined (__GNUC__) + #define INITIAL_STACK_POINTER (&__cy_stack) +#elif defined (__ICCARM__) + #pragma language=extended + #pragma segment="CSTACK" + #define INITIAL_STACK_POINTER { .__ptr = __sfe( "CSTACK" ) } + + extern void __iar_program_start( void ); + extern void __iar_data_init3 (void); +#endif /* (__ARMCC_VERSION) */ + +/* Global variables */ +#if !defined (__ICCARM__) + CY_NOINIT static uint32 cySysNoInitDataValid; +#endif /* !defined (__ICCARM__) */ + + +/******************************************************************************* +* Default Ram Interrupt Vector table storage area. Must be 256-byte aligned. +*******************************************************************************/ +#if defined (__ICCARM__) + #pragma location=".ramvectors" + #pragma data_alignment=256 +#else + CY_SECTION(".ramvectors") + CY_ALIGN(256) +#endif /* defined (__ICCARM__) */ +cyisraddress CyRamVectors[CY_NUM_VECTORS]; + + +/******************************************************************************* +* Function Name: IntDefaultHandler +******************************************************************************** +* +* Summary: +* This function is called for all interrupts, other than reset, that get +* called before the system is setup. +* +* Parameters: +* None +* +* Return: +* None +* +* Theory: +* Any value other than zero is acceptable. +* +*******************************************************************************/ +CY_ISR(IntDefaultHandler) +{ + + while(1) + { + /*********************************************************************** + * We should never get here. If we do, a serious problem occured, so go + * into an infinite loop. + ***********************************************************************/ + } +} + + +#if defined(__ARMCC_VERSION) + +/* Local function for the device reset. */ +extern void Reset(void); + +/* Application entry point. */ +extern void $Super$$main(void); + +/* Linker-generated Stack Base addresses, Two Region and One Region */ +extern uint32 Image$$ARM_LIB_STACK$$ZI$$Limit; + +/* RealView C Library initialization. */ +extern int __main(void); + + +/******************************************************************************* +* Function Name: Reset +******************************************************************************** +* +* Summary: +* This function handles the reset interrupt for the RVDS/MDK toolchains. +* This is the first bit of code that is executed at startup. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void Reset(void) +{ + #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) + + /* For PSoC 5LP, debugging is enabled by default */ + #if(CYDEV_DEBUGGING_ENABLE == 0) + *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK; + #endif /* (CYDEV_DEBUGGING_ENABLE) */ + + /* Reset Status Register has Read-to-clear SW access mode. + * Preserve current RESET_SR0 state to make it available for next reading. + */ + *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0); + + #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */ + + #if(CYDEV_BOOTLOADER_ENABLE) + CyBtldr_CheckLaunch(); + #endif /* (CYDEV_BOOTLOADER_ENABLE) */ + + __main(); +} + + +/******************************************************************************* +* Function Name: $Sub$$main +******************************************************************************** +* +* Summary: +* This function is called imediatly before the users main +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void $Sub$$main(void) +{ + initialize_psoc(); + + /* Call original main */ + $Super$$main(); + + while (1) + { + /* If main returns it is undefined what we should do. */ + } +} + +#elif defined(__GNUC__) + +void Start_c(void); + +/* Stack Base address */ +extern void __cy_stack(void); + +/* Application entry point. */ +extern int main(void); + +/* The static objects constructors initializer */ +extern void __libc_init_array(void); + +typedef unsigned char __cy_byte_align8 __attribute ((aligned (8))); + +struct __cy_region +{ + __cy_byte_align8 *init; /* Initial contents of this region. */ + __cy_byte_align8 *data; /* Start address of region. */ + size_t init_size; /* Size of initial data. */ + size_t zero_size; /* Additional size to be zeroed. */ +}; + +extern const struct __cy_region __cy_regions[]; +extern const char __cy_region_num __attribute__((weak)); +#define __cy_region_num ((size_t)&__cy_region_num) + + +/******************************************************************************* +* Function Name: Reset +******************************************************************************** +* +* Summary: +* This function handles the reset interrupt for the GCC toolchain. This is the +* first bit of code that is executed at startup. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void Reset(void) +{ + #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) + + /* For PSoC 5LP, debugging is enabled by default */ + #if(CYDEV_DEBUGGING_ENABLE == 0) + *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK; + #endif /* (CYDEV_DEBUGGING_ENABLE) */ + + /* Reset Status Register has Read-to-clear SW access mode. + * Preserve current RESET_SR0 state to make it available for next reading. + */ + *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0); + + #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */ + + #if(CYDEV_BOOTLOADER_ENABLE) + CyBtldr_CheckLaunch(); + #endif /* (CYDEV_BOOTLOADER_ENABLE) */ + + Start_c(); +} + +__attribute__((weak)) +void _exit(int status) +{ + /* Cause a divide by 0 exception */ + int x = status / INT_MAX; + x = 4 / x; + + while(1) + { + } +} + +/******************************************************************************* +* Function Name: Start_c +******************************************************************************** +* +* Summary: +* This function handles initializing the .data and .bss sections in +* preperation for running standard C code. Once initialization is complete +* it will call main(). This function will never return. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void Start_c(void) __attribute__ ((noreturn)); +void Start_c(void) +{ + unsigned regions = __cy_region_num; + const struct __cy_region *rptr = __cy_regions; + + /* Initialize memory */ + for (regions = __cy_region_num, rptr = __cy_regions; regions--; rptr++) + { + uint32 *src = (uint32 *)rptr->init; + uint32 *dst = (uint32 *)rptr->data; + unsigned limit = rptr->init_size; + unsigned count; + + for (count = 0u; count != limit; count += sizeof (uint32)) + { + *dst++ = *src++; + } + limit = rptr->zero_size; + for (count = 0u; count != limit; count += sizeof (uint32)) + { + *dst++ = 0u; + } + } + + /* Invoke static objects constructors */ + __libc_init_array(); + (void) main(); + + while (1) + { + /* If main returns, make sure we don't return. */ + } +} + + +#elif defined (__ICCARM__) + +/******************************************************************************* +* Function Name: __low_level_init +******************************************************************************** +* +* Summary: +* This function perform early initializations for the IAR Embedded +* Workbench IDE. It is executed in the context of reset interrupt handler +* before the data sections are initialized. +* +* Parameters: +* None +* +* Return: +* The value that determines whether or not data sections should be initialized +* by the system startup code: +* 0 - skip data sections initialization; +* 1 - initialize data sections; +* +*******************************************************************************/ +int __low_level_init(void) +{ + #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) + + /* For PSoC 5LP, debugging is enabled by default */ + #if(CYDEV_DEBUGGING_ENABLE == 0) + *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK; + #endif /* (CYDEV_DEBUGGING_ENABLE) */ + + /* Reset Status Register has Read-to-clear SW access mode. + * Preserve current RESET_SR0 state to make it available for next reading. + */ + *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0); + + #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */ + + #if (CYDEV_BOOTLOADER_ENABLE) + CyBtldr_CheckLaunch(); + #endif /* CYDEV_BOOTLOADER_ENABLE */ + + /* Initialize data sections */ + __iar_data_init3(); + + initialize_psoc(); + + return 0; +} + +#endif /* __GNUC__ */ + + +/******************************************************************************* +* +* Default Rom Interrupt Vector table. +* +*******************************************************************************/ +#if defined(__ARMCC_VERSION) + /* Suppress diagnostic message 1296-D: extended constant initialiser used */ + #pragma diag_suppress 1296 +#endif /* defined(__ARMCC_VERSION) */ + +#if defined (__ICCARM__) + #pragma location=".romvectors" + const intvec_elem __vector_table[CY_NUM_ROM_VECTORS] = +#else + CY_SECTION(".romvectors") + const cyisraddress RomVectors[CY_NUM_ROM_VECTORS] = +#endif /* defined (__ICCARM__) */ +{ + INITIAL_STACK_POINTER, /* The initial stack pointer 0 */ + #if defined (__ICCARM__) /* The reset handler 1 */ + __iar_program_start, + #else + (cyisraddress)&Reset, + #endif /* defined (__ICCARM__) */ + &IntDefaultHandler, /* The NMI handler 2 */ + &IntDefaultHandler, /* The hard fault handler 3 */ +}; + +#if defined(__ARMCC_VERSION) + #pragma diag_default 1296 +#endif /* defined(__ARMCC_VERSION) */ + + +/******************************************************************************* +* Function Name: initialize_psoc +******************************************************************************** +* +* Summary: +* This function used to initialize the PSoC chip before calling main. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +#if (defined(__GNUC__) && !defined(__ARMCC_VERSION)) +__attribute__ ((constructor(101))) +#endif +void initialize_psoc(void) +{ + uint32 i; + + /* Set Priority group 5. */ + + /* Writes to NVIC_APINT register require the VECTKEY in the upper half */ + *CY_NVIC_APINT_PTR = CY_NVIC_APINT_VECTKEY | CY_NVIC_APINT_PRIGROUP_3_5; + *CY_NVIC_CFG_CTRL_PTR |= CY_NVIC_CFG_STACKALIGN; + + /* Set Ram interrupt vectors to default functions. */ + for (i = 0u; i < CY_NUM_VECTORS; i++) + { + #if defined (__ICCARM__) + CyRamVectors[i] = (i < CY_NUM_ROM_VECTORS) ? __vector_table[i].__fun : &IntDefaultHandler; + #else + CyRamVectors[i] = (i < CY_NUM_ROM_VECTORS) ? RomVectors[i] : &IntDefaultHandler; + #endif /* defined (__ICCARM__) */ + } + + /* Was stored in CFGMEM to avoid being cleared while SRAM gets cleared */ + CyResetStatus = CY_GET_REG8(CYREG_PHUB_CFGMEM23_CFG1); + + /* Point NVIC at the RAM vector table. */ + *CYINT_VECT_TABLE = CyRamVectors; + + /* Initialize the configuration registers. */ + cyfitter_cfg(); + + #if(0u != DMA_CHANNELS_USED__MASK0) + + /* Setup DMA - only necessary if the design contains a DMA component. */ + CyDmacConfigure(); + + #endif /* (0u != DMA_CHANNELS_USED__MASK0) */ + + #if !defined (__ICCARM__) + /* Actually, no need to clean this variable, just to make compiler happy. */ + cySysNoInitDataValid = 0u; + #endif /* !defined (__ICCARM__) */ +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s new file mode 100755 index 00000000..5ac6ba97 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s @@ -0,0 +1,174 @@ +/******************************************************************************* +* File Name: CyBootAsmGnu.s +* Version 4.0 +* +* Description: +* Assembly routines for GNU as. +* +******************************************************************************** +* Copyright 2010-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +.include "cyfittergnu.inc" + +.syntax unified +.text +.thumb + + +/******************************************************************************* +* Function Name: CyDelayCycles +******************************************************************************** +* +* Summary: +* Delays for the specified number of cycles. +* +* Parameters: +* uint32 cycles: number of cycles to delay. +* +* Return: +* None +* +*******************************************************************************/ +/* void CyDelayCycles(uint32 cycles) */ +.align 3 /* Align to 8 byte boundary (2^n) */ +.global CyDelayCycles +.func CyDelayCycles, CyDelayCycles +.type CyDelayCycles, %function +.thumb_func +CyDelayCycles: /* cycles bytes */ +/* If ICache is enabled */ +.ifeq CYDEV_INSTRUCT_CACHE_ENABLED - 1 + + ADDS r0, r0, #2 /* 1 2 Round to nearest multiple of 4 */ + LSRS r0, r0, #2 /* 1 2 Divide by 4 and set flags */ + BEQ CyDelayCycles_done /* 2 2 Skip if 0 */ + NOP /* 1 2 Loop alignment padding */ + +CyDelayCycles_loop: + SUBS r0, r0, #1 /* 1 2 */ + MOV r0, r0 /* 1 2 Pad loop to power of two cycles */ + BNE CyDelayCycles_loop /* 2 2 */ + +CyDelayCycles_done: + BX lr /* 3 2 */ + +.else + + CMP r0, #20 /* 1 2 If delay is short - jump to cycle */ + BLS CyDelayCycles_short /* 1 2 */ + PUSH {r1} /* 2 2 PUSH r1 to stack */ + MOVS r1, #1 /* 1 2 */ + + SUBS r0, r0, #20 /* 1 2 Subtract overhead */ + LDR r1,=CYREG_CACHE_CC_CTL/* 2 2 Load flash wait cycles value */ + LDRB r1, [r1, #0] /* 2 2 */ + ANDS r1, #0xC0 /* 1 2 */ + + LSRS r1, r1, #6 /* 1 2 */ + PUSH {r2} /* 1 2 PUSH r2 to stack */ + LDR r2, =cy_flash_cycles /* 2 2 */ + LDRB r1, [r2, r1] /* 2 2 */ + + POP {r2} /* 2 2 POP r2 from stack */ + NOP /* 1 2 Alignment padding */ + NOP /* 1 2 Alignment padding */ + NOP /* 1 2 Alignment padding */ + +CyDelayCycles_loop: + SBCS r0, r0, r1 /* 1 2 */ + BPL CyDelayCycles_loop /* 3 2 */ + NOP /* 1 2 Loop alignment padding */ + NOP /* 1 2 Loop alignment padding */ + + POP {r1} /* 2 2 POP r1 from stack */ +CyDelayCycles_done: + BX lr /* 3 2 */ + NOP /* 1 2 Alignment padding */ + NOP /* 1 2 Alignment padding */ + +CyDelayCycles_short: + SBCS r0, r0, #4 /* 1 2 */ + BPL CyDelayCycles_short /* 3 2 */ + BX lr /* 3 2 */ + +cy_flash_cycles: +.byte 0x0B +.byte 0x05 +.byte 0x07 +.byte 0x09 +.endif + +.endfunc + + +/******************************************************************************* +* Function Name: CyEnterCriticalSection +******************************************************************************** +* +* Summary: +* CyEnterCriticalSection disables interrupts and returns a value indicating +* whether interrupts were previously enabled (the actual value depends on +* whether the device is PSoC 3 or PSoC 5). +* +* Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit +* with interrupts still enabled. The test and set of the interrupt bits is not +* atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid +* corrupting processor state, it must be the policy that all interrupt routines +* restore the interrupt enable bits as they were found on entry. +* +* Parameters: +* None +* +* Return: +* uint8 +* Returns 0 if interrupts were previously enabled or 1 if interrupts +* were previously disabled. +* +*******************************************************************************/ +/* uint8 CyEnterCriticalSection(void) */ +.global CyEnterCriticalSection +.func CyEnterCriticalSection, CyEnterCriticalSection +.type CyEnterCriticalSection, %function +.thumb_func +CyEnterCriticalSection: + MRS r0, PRIMASK /* Save and return interrupt state */ + CPSID I /* Disable interrupts */ + BX lr +.endfunc + + +/******************************************************************************* +* Function Name: CyExitCriticalSection +******************************************************************************** +* +* Summary: +* CyExitCriticalSection re-enables interrupts if they were enabled before +* CyEnterCriticalSection was called. The argument should be the value returned +* from CyEnterCriticalSection. +* +* Parameters: +* uint8 savedIntrStatus: +* Saved interrupt status returned by the CyEnterCriticalSection function. +* +* Return: +* None +* +*******************************************************************************/ +/* void CyExitCriticalSection(uint8 savedIntrStatus) */ +.global CyExitCriticalSection +.func CyExitCriticalSection, CyExitCriticalSection +.type CyExitCriticalSection, %function +.thumb_func +CyExitCriticalSection: + MSR PRIMASK, r0 /* Restore interrupt state */ + BX lr +.endfunc + +.end + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s new file mode 100755 index 00000000..f2e8f940 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s @@ -0,0 +1,156 @@ +;------------------------------------------------------------------------------- +; FILENAME: CyBootAsmIar.s +; Version 4.0 +; +; DESCRIPTION: +; Assembly routines for IAR Embedded Workbench IDE. +; +;------------------------------------------------------------------------------- +; Copyright 2013, Cypress Semiconductor Corporation. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + + SECTION .text:CODE:ROOT(4) + PUBLIC CyDelayCycles + PUBLIC CyEnterCriticalSection + PUBLIC CyExitCriticalSection + INCLUDE cyfitteriar.inc + THUMB + + +;------------------------------------------------------------------------------- +; Function Name: CyEnterCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; CyEnterCriticalSection disables interrupts and returns a value indicating +; whether interrupts were previously enabled. +; +; Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit +; with interrupts still enabled. The test and set of the interrupt bits is not +; atomic. Therefore, to avoid corrupting processor state, it must be the policy +; that all interrupt routines restore the interrupt enable bits as they were +; found on entry. +; +; Parameters: +; None +; +; Return: +; uint8 +; Returns 0 if interrupts were previously enabled or 1 if interrupts +; were previously disabled. +; +;------------------------------------------------------------------------------- +; uint8 CyEnterCriticalSection(void) + +CyEnterCriticalSection: + MRS r0, PRIMASK ; Save and return interrupt state + CPSID I ; Disable interrupts + BX lr + + +;------------------------------------------------------------------------------- +; Function Name: CyExitCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; CyExitCriticalSection re-enables interrupts if they were enabled before +; CyEnterCriticalSection was called. The argument should be the value returned +; from CyEnterCriticalSection. +; +; Parameters: +; uint8 savedIntrStatus: +; Saved interrupt status returned by the CyEnterCriticalSection function. +; +; Return: +; None +; +;------------------------------------------------------------------------------- +; void CyExitCriticalSection(uint8 savedIntrStatus) + +CyExitCriticalSection: + MSR PRIMASK, r0 ; Restore interrupt state + BX lr + + +;------------------------------------------------------------------------------- +; Function Name: CyDelayCycles +;------------------------------------------------------------------------------- +; +; Summary: +; Delays for the specified number of cycles. +; +; Parameters: +; uint32 cycles: number of cycles to delay. +; +; Return: +; None +; +;------------------------------------------------------------------------------- +; void CyDelayCycles(uint32 cycles) + +CyDelayCycles: + IF CYDEV_INSTRUCT_CACHE_ENABLED == 1 + ; cycles bytes + ADDS r0, r0, #2 ; 1 2 Round to nearest multiple of 4 + LSRS r0, r0, #2 ; 1 2 Divide by 4 and set flags + BEQ CyDelayCycles_done ; 2 2 Skip if 0 + NOP ; 1 2 Loop alignment padding +CyDelayCycles_loop: + SUBS r0, r0, #1 ; 1 2 + MOV r0, r0 ; 1 2 Pad loop to power of two cycles + BNE CyDelayCycles_loop ; 2 2 +CyDelayCycles_done: + BX lr ; 3 2 + + ELSE + + CMP r0, #20 ; 1 2 If delay is short - jump to cycle + BLS CyDelayCycles_short ; 1 2 + PUSH {r1} ; 2 2 PUSH r1 to stack + MOVS r1, #1 ; 1 2 + + SUBS r0, r0, #20 ; 1 2 Subtract overhead + LDR r1,=CYREG_CACHE_CC_CTL; 2 2 Load flash wait cycles value + LDRB r1, [r1, #0] ; 2 2 + ANDS r1, r1, #0xC0 ; 1 2 + + LSRS r1, r1, #6 ; 1 2 + PUSH {r2} ; 1 2 PUSH r2 to stack + LDR r2, =cy_flash_cycles ; 2 2 + LDRB r1, [r2, r1] ; 2 2 + + POP {r2} ; 2 2 POP r2 from stack + NOP ; 1 2 Alignment padding + NOP ; 1 2 Alignment padding + NOP ; 1 2 Alignment padding + +CyDelayCycles_loop: + SBCS r0, r0, r1 ; 1 2 + BPL CyDelayCycles_loop ; 3 2 + NOP ; 1 2 Loop alignment padding + NOP ; 1 2 Loop alignment padding + + POP {r1} ; 2 2 POP r1 from stack +CyDelayCycles_done: + BX lr ; 3 2 + NOP ; 1 2 Alignment padding + NOP ; 1 2 Alignment padding +CyDelayCycles_short: + SBCS r0, r0, #4 ; 1 2 + BPL CyDelayCycles_short ; 3 2 + BX lr ; 3 2 + NOP ; 1 2 Loop alignment padding + + DATA +cy_flash_cycles: +byte_1 DCB 0x0B +byte_2 DCB 0x05 +byte_3 DCB 0x07 +byte_4 DCB 0x09 + + ENDIF + + END diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s new file mode 100755 index 00000000..c10181e7 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s @@ -0,0 +1,161 @@ +;------------------------------------------------------------------------------- +; FILENAME: CyBootAsmRv.s +; Version 4.0 +; +; DESCRIPTION: +; Assembly routines for RealView. +; +;------------------------------------------------------------------------------- +; Copyright 2010-2013, Cypress Semiconductor Corporation. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + + AREA |.text|,CODE,ALIGN=3 + THUMB + EXTERN Reset + + GET cyfitterrv.inc + +;------------------------------------------------------------------------------- +; Function Name: CyDelayCycles +;------------------------------------------------------------------------------- +; +; Summary: +; Delays for the specified number of cycles. +; +; Parameters: +; uint32 cycles: number of cycles to delay. +; +; Return: +; None +; +;------------------------------------------------------------------------------- +; void CyDelayCycles(uint32 cycles) + ALIGN 8 +CyDelayCycles FUNCTION + EXPORT CyDelayCycles + IF CYDEV_INSTRUCT_CACHE_ENABLED == 1 + ; cycles bytes + ADDS r0, r0, #2 ; 1 2 Round to nearest multiple of 4 + LSRS r0, r0, #2 ; 1 2 Divide by 4 and set flags + BEQ CyDelayCycles_done ; 2 2 Skip if 0 + NOP ; 1 2 Loop alignment padding +CyDelayCycles_loop + SUBS r0, r0, #1 ; 1 2 + MOV r0, r0 ; 1 2 Pad loop to power of two cycles + BNE CyDelayCycles_loop ; 2 2 + NOP ; 1 2 Loop alignment padding +CyDelayCycles_done + BX lr ; 3 2 + + ELSE + + CMP r0, #20 ; 1 2 If delay is short - jump to cycle + BLS CyDelayCycles_short ; 1 2 + PUSH {r1} ; 2 2 PUSH r1 to stack + MOVS r1, #1 ; 1 2 + + SUBS r0, r0, #20 ; 1 2 Subtract overhead + LDR r1,=CYREG_CACHE_CC_CTL; 2 2 Load flash wait cycles value + LDRB r1, [r1, #0] ; 2 2 + ANDS r1, #0xC0 ; 1 2 + + LSRS r1, r1, #6 ; 1 2 + PUSH {r2} ; 1 2 PUSH r2 to stack + LDR r2, =cy_flash_cycles ; 2 2 + LDRB r1, [r2, r1] ; 2 2 + + POP {r2} ; 2 2 POP r2 from stack + NOP ; 1 2 Alignment padding + NOP ; 1 2 Alignment padding + NOP ; 1 2 Alignment padding + +CyDelayCycles_loop + SBCS r0, r0, r1 ; 1 2 + BPL CyDelayCycles_loop ; 3 2 + NOP ; 1 2 Loop alignment padding + NOP ; 1 2 Loop alignment padding + + POP {r1} ; 2 2 POP r1 from stack +CyDelayCycles_done + BX lr ; 3 2 + NOP ; 1 2 Alignment padding + NOP ; 1 2 Alignment padding + +CyDelayCycles_short + SBCS r0, r0, #4 ; 1 2 + BPL CyDelayCycles_short ; 3 2 + BX lr ; 3 2 + +cy_flash_cycles +byte_1 DCB 0x0B +byte_2 DCB 0x05 +byte_3 DCB 0x07 +byte_4 DCB 0x09 + + ENDIF + ENDFUNC + + +;------------------------------------------------------------------------------- +; Function Name: CyEnterCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; CyEnterCriticalSection disables interrupts and returns a value indicating +; whether interrupts were previously enabled (the actual value depends on +; whether the device is PSoC 3 or PSoC 5). +; +; Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit +; with interrupts still enabled. The test and set of the interrupt bits is not +; atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid +; corrupting processor state, it must be the policy that all interrupt routines +; restore the interrupt enable bits as they were found on entry. +; +; Parameters: +; None +; +; Return: +; uint8 +; Returns 0 if interrupts were previously enabled or 1 if interrupts +; were previously disabled. +; +;------------------------------------------------------------------------------- +; uint8 CyEnterCriticalSection(void) +CyEnterCriticalSection FUNCTION + EXPORT CyEnterCriticalSection + MRS r0, PRIMASK ; Save and return interrupt state + CPSID I ; Disable interrupts + BX lr + ENDFUNC + + +;------------------------------------------------------------------------------- +; Function Name: CyExitCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; CyExitCriticalSection re-enables interrupts if they were enabled before +; CyEnterCriticalSection was called. The argument should be the value returned +; from CyEnterCriticalSection. +; +; Parameters: +; uint8 savedIntrStatus: +; Saved interrupt status returned by the CyEnterCriticalSection function. +; +; Return: +; None +; +;------------------------------------------------------------------------------- +; void CyExitCriticalSection(uint8 savedIntrStatus) +CyExitCriticalSection FUNCTION + EXPORT CyExitCriticalSection + MSR PRIMASK, r0 ; Restore interrupt state + BX lr + ENDFUNC + + END + +; [] END OF FILE diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyDmac.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyDmac.c new file mode 100755 index 00000000..e3858c62 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyDmac.c @@ -0,0 +1,1131 @@ +/******************************************************************************* +* File Name: CyDmac.c +* Version 4.0 +* +* Description: +* Provides an API for the DMAC component. The API includes functions for the +* DMA controller, DMA channels and Transfer Descriptors. +* +* This API is the library version not the auto generated code that gets +* generated when the user places a DMA component on the schematic. +* +* The auto generated code would use the APi's in this module. +* +* Note: +* This code is endian agnostic. +* +* The Transfer Descriptor memory can be used as regular memory if the TD's are +* not being used. +* +* This code uses the first byte of each TD to manage the free list of TD's. +* The user can over write this once the TD is allocated. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "CyDmac.h" + + +/******************************************************************************* +* The following variables are initialized from CyDmacConfigure() function that +* is executed from initialize_psoc() at the early initialization stage. +* In case of IAR EW IDE, initialize_psoc() is executed before the data sections +* are initialized. To avoid zeroing, these variables should be initialized +* properly during segments initialization as well. +*******************************************************************************/ +static uint8 CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS; /* Current Number of free elements in the list */ +static uint8 CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); /* Index of the first available TD */ +static uint32 CyDmaChannels = DMA_CHANNELS_USED__MASK0; /* Bit map of DMA channel ownership */ + + +/******************************************************************************* +* Function Name: CyDmacConfigure +******************************************************************************** +* +* Summary: +* Creates a linked list of all the TDs to be allocated. This function is called +* by the startup code; you do not normally need to call it. You could call this +* function if all of the DMA channels are inactive. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyDmacConfigure(void) +{ + uint8 dmaIndex; + + /* Set TD list variables. */ + CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); + CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS; + + /* Make TD free list. */ + for(dmaIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); dmaIndex != 0u; dmaIndex--) + { + CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = (uint8)(dmaIndex - 1u); + } + + /* Make the last one point to zero. */ + CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = 0u; +} + + +/******************************************************************************* +* Function Name: CyDmacError +******************************************************************************** +* +* Summary: +* Returns errors of the last failed DMA transaction. +* +* Parameters: +* None +* +* Return: +* Errors of the last failed DMA transaction. +* +* DMAC_PERIPH_ERR: +* Set to 1 when a peripheral responds to a bus transaction with an error +* response. +* +* DMAC_UNPOP_ACC: +* Set to 1 when an access is attempted to an invalid address. +* +* DMAC_BUS_TIMEOUT: +* Set to 1 when a bus timeout occurs. Cleared by writing a 1. Timeout values +* are determined by the BUS_TIMEOUT field in the PHUBCFG register. +* +* Theory: +* Once an error occurs the error bits are sticky and are only cleared by a +* write 1 to the error register. +* +*******************************************************************************/ +uint8 CyDmacError(void) +{ + return((uint8)(((uint32) 0x0Fu) & *CY_DMA_ERR_PTR)); +} + + +/******************************************************************************* +* Function Name: CyDmacClearError +******************************************************************************** +* +* Summary: +* Clears the error bits in the error register of the DMAC. +* +* Parameters: +* error: +* Clears the error bits in the DMAC error register. +* +* DMAC_PERIPH_ERR: +* Set to 1 when a peripheral responds to a bus transaction with an error +* response. +* +* DMAC_UNPOP_ACC: +* Set to 1 when an access is attempted to an invalid address. +* +* DMAC_BUS_TIMEOUT: +* Set to 1 when a bus timeout occurs. Cleared by writing a 1. Timeout values +* are determined by the BUS_TIMEOUT field in the PHUBCFG register. +* +* Return: +* None +* +* Theory: +* Once an error occurs the error bits are sticky and are only cleared by a +* write 1 to the error register. +* +*******************************************************************************/ +void CyDmacClearError(uint8 error) +{ + *CY_DMA_ERR_PTR = (((uint32)0x0Fu) & ((uint32)error)); +} + + +/******************************************************************************* +* Function Name: CyDmacErrorAddress +******************************************************************************** +* +* Summary: +* When an DMAC_BUS_TIMEOUT, DMAC_UNPOP_ACC and DMAC_PERIPH_ERR occurs the +* address of the error is written to the error address register and can be read +* with this function. +* +* If there are multiple errors, only the address of the first is saved. +* +* Parameters: +* None +* +* Return: +* The address that caused the error. +* +*******************************************************************************/ +uint32 CyDmacErrorAddress(void) +{ + return(CY_GET_REG32(CY_DMA_ERR_ADR_PTR)); +} + + +/******************************************************************************* +* Function Name: CyDmaChAlloc +******************************************************************************** +* +* Summary: +* Allocates a channel from the DMAC to be used in all functions that require a +* channel handle. +* +* Parameters: +* None +* +* Return: +* The allocated channel number. Zero is a valid channel number. +* DMA_INVALID_CHANNEL is returned if there are no channels available. +* +*******************************************************************************/ +uint8 CyDmaChAlloc(void) +{ + uint8 interruptState; + uint8 dmaIndex; + uint32 channel = 1u; + + + /* Enter critical section! */ + interruptState = CyEnterCriticalSection(); + + /* Look for a free channel. */ + for(dmaIndex = 0u; dmaIndex < CY_DMA_NUMBEROF_CHANNELS; dmaIndex++) + { + if(0uL == (CyDmaChannels & channel)) + { + /* Mark the channel as used. */ + CyDmaChannels |= channel; + break; + } + + channel <<= 1u; + } + + if(dmaIndex >= CY_DMA_NUMBEROF_CHANNELS) + { + dmaIndex = CY_DMA_INVALID_CHANNEL; + } + + /* Exit critical section! */ + CyExitCriticalSection(interruptState); + + return(dmaIndex); +} + + +/******************************************************************************* +* Function Name: CyDmaChFree +******************************************************************************** +* +* Summary: +* Frees a channel allocated by DmaChAlloc(). +* +* Parameters: +* uint8 chHandle: +* The handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChFree(uint8 chHandle) +{ + cystatus status = CYRET_BAD_PARAM; + uint8 interruptState; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + /* Enter critical section */ + interruptState = CyEnterCriticalSection(); + + /* Clear the bit mask that keeps track of ownership. */ + CyDmaChannels &= ~(((uint32) 1u) << chHandle); + + /* Exit critical section */ + CyExitCriticalSection(interruptState); + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChEnable +******************************************************************************** +* +* Summary: +* Enables the DMA channel. A software or hardware request still must happen +* before the channel is executed. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* +* uint8 preserveTds: +* Preserves the original TD state when the TD has completed. This parameter +* applies to all TDs in the channel. +* +* 0 - When a TD is completed, the DMAC leaves the TD configuration values in +* their current state, and does not restore them to their original state. +* +* 1 - When a TD is completed, the DMAC restores the original configuration +* values of the TD. +* +* When preserveTds is set, the TD slot that equals the channel number becomes +* RESERVED and that becomes where the working registers exist. So, for example, +* if you are using CH06 and preserveTds is set, you are not allowed to use TD +* slot 6. That is reclaimed by the DMA engine for its private use. +* +* Note Do not chain back to a completed TD if the preserveTds for the channel +* is set to 0. When a TD has completed preserveTds for the channel set to 0, +* the transfer count will be at 0. If a TD with a transfer count of 0 is +* started, the TD will transfer an indefinite amount of data. +* +* Take extra precautions when using the hardware request (DRQ) option when the +* preserveTds is set to 0, as you might be requesting the wrong data. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + if (0u != preserveTds) + { + /* Store the intermediate TD states separately in CHn_SEP_TD0/1 to + * preserve the original TD chain + */ + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= CY_DMA_CH_BASIC_CFG_WORK_SEP; + } + else + { + /* Store the intermediate and final TD states on top of the original TD chain */ + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_CH_BASIC_CFG_WORK_SEP); + } + + /* Enable channel */ + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= CY_DMA_CH_BASIC_CFG_EN; + + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChDisable +******************************************************************************** +* +* Summary: +* Disables the DMA channel. Once this function is called, CyDmaChStatus() may +* be called to determine when the channel is disabled and which TDs were being +* executed. +* +* If it is currently executing it will allow the current burst to finish +* naturally. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChDisable(uint8 chHandle) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + /*********************************************************************** + * Should not change configuration information of a DMA channel when it + * is active (or vulnerable to becoming active). + ***********************************************************************/ + + /* Disable channel */ + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_EN)); + + /* Store the intermediate and final TD states on top of the original TD chain */ + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_WORK_SEP)); + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaClearPendingDrq +******************************************************************************** +* +* Summary: +* Clears pending DMA data request. +* +* Parameters: +* uint8 chHandle: +* Handle to the dma channel. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaClearPendingDrq(uint8 chHandle) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + CY_DMA_CH_STRUCT_PTR[chHandle].action[0] |= CY_DMA_CPU_TERM_CHAIN; + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] |= 0x01u; + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChPriority +******************************************************************************** +* +* Summary: +* Sets the priority of a DMA channel. You can use this function when you want +* to change the priority at run time. If the priority remains the same for a +* DMA channel, then you can configure the priority in the .cydwr file. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* +* uint8 priority: +* Priority to set the channel to, 0 - 7. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChPriority(uint8 chHandle, uint8 priority) +{ + uint8 value; + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + value = CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] & ((uint8)(~(0x0Eu))); + + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] = value | ((uint8) ((priority & 0x7u) << 0x01u)); + + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChSetExtendedAddress +******************************************************************************** +* +* Summary: +* Sets the high 16 bits of the source and destination addresses for the DMA +* channel (valid for all TDs in the chain). +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* +* uint16 source: +* Upper 16 bit address of the DMA transfer source. +* +* uint16 destination: +* Upper 16 bit address of the DMA transfer destination. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destination) \ + +{ + cystatus status = CYRET_BAD_PARAM; + reg16 *convert; + + #if(CY_PSOC5) + + /* 0x1FFF8000-0x1FFFFFFF needs to use alias at 0x20008000-0x2000FFFF */ + if(source == 0x1FFFu) + { + source = 0x2000u; + } + + if(destination == 0x1FFFu) + { + destination = 0x2000u; + } + + #endif /* (CY_PSOC5) */ + + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + /* Set source address */ + convert = (reg16 *) &CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG1[0]; + CY_SET_REG16(convert, source); + + /* Set destination address */ + convert = (reg16 *) &CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG1[2u]; + CY_SET_REG16(convert, destination); + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChSetInitialTd +******************************************************************************** +* +* Summary: +* Sets the initial TD to be executed for the channel when the CyDmaChEnable() +* function is called. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize(). +* +* uint8 startTd: +* The index of TD to set as the first TD associated with the channel. Zero is +* a valid TD index. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChSetInitialTd(uint8 chHandle, uint8 startTd) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + CY_DMA_CH_STRUCT_PTR[chHandle].basic_status[1u] = startTd; + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChSetRequest +******************************************************************************** +* +* Summary: +* Allows the caller to terminate a chain of TDs, terminate one TD, or create a +* direct request to start the DMA channel. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* +* uint8 request: +* One of the following constants. Each of the constants is a three-bit value. +* +* CPU_REQ - Create a direct request to start the DMA channel +* CPU_TERM_TD - Terminate one TD +* CPU_TERM_CHAIN - Terminate a chain of TDs +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChSetRequest(uint8 chHandle, uint8 request) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + CY_DMA_CH_STRUCT_PTR[chHandle].action[0u] |= (request & (CPU_REQ | CPU_TERM_TD | CPU_TERM_CHAIN)); + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChGetRequest +******************************************************************************** +* +* Summary: +* This function allows the caller of CyDmaChSetRequest() to determine if the +* request was completed. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* +* Return: +* Returns a three-bit field, corresponding to the three bits of the request, +* which describes the state of the previously posted request. If the value is +* zero, the request was completed. CY_DMA_INVALID_CHANNEL if the handle is +* invalid. +* +*******************************************************************************/ +cystatus CyDmaChGetRequest(uint8 chHandle) +{ + cystatus status = CY_DMA_INVALID_CHANNEL; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + status = (cystatus) ((uint32)CY_DMA_CH_STRUCT_PTR[chHandle].action[0u] & + (uint32)(CY_DMA_CPU_REQ | CY_DMA_CPU_TERM_TD | CY_DMA_CPU_TERM_CHAIN)); + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChStatus +******************************************************************************** +* +* Summary: +* Determines the status of the DMA channel. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* +* uint8 * currentTd: +* The address to store the index of the current TD. Can be NULL if the value +* is not needed. +* +* uint8 * state: +* The address to store the state of the channel. Can be NULL if the value is +* not needed. +* +* STATUS_TD_ACTIVE +* 0: Channel is not currently being serviced by DMAC +* 1: Channel is currently being serviced by DMAC +* +* STATUS_CHAIN_ACTIVE +* 0: TD chain is inactive; either no DMA requests have triggered a new chain +* or the previous chain has completed. +* 1: TD chain has been triggered by a DMA request +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +* Theory: +* The caller can check on the activity of the Current TD and the Chain. +* +*******************************************************************************/ +cystatus CyDmaChStatus(uint8 chHandle, uint8 * currentTd, uint8 * state) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + if(NULL != currentTd) + { + *currentTd = CY_DMA_CH_STRUCT_PTR[chHandle].basic_status[1] & 0x7Fu; + } + + if(NULL != state) + { + *state= CY_DMA_CH_STRUCT_PTR[chHandle].basic_status[0]; + } + + status = CYRET_SUCCESS; + } + + return (status); +} + + +/******************************************************************************* +* Function Name: CyDmaChSetConfiguration +******************************************************************************** +* +* Summary: +* Sets configuration information of the channel. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize(). +* +* uint8 burstCount: +* Specifies the size of bursts (1 to 127) the data transfer should be divided +* into. If this value is zero then the whole transfer is done in one burst. +* +* uint8 requestPerBurst: +* The whole of the data can be split into multiple bursts, if this is +* required to complete the transaction: +* 0: All subsequent bursts after the first burst will be automatically +* requested and carried out +* 1: All subsequent bursts after the first burst must also be individually +* requested. +* +* uint8 tdDone0: +* Selects one of the TERMOUT0 interrupt lines to signal completion. The line +* connected to the nrq terminal will determine the TERMOUT0_SEL definition and +* should be used as supplied by cyfitter.h +* +* uint8 tdDone1: +* Selects one of the TERMOUT1 interrupt lines to signal completion. The line +* connected to the nrq terminal will determine the TERMOUT1_SEL definition and +* should be used as supplied by cyfitter.h +* +* uint8 tdStop: +* Selects one of the TERMIN interrupt lines to signal to the DMAC that the TD +* should terminate. The signal connected to the trq terminal will determine +* which TERMIN (termination request) is used. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChSetConfiguration(uint8 chHandle, uint8 burstCount, uint8 requestPerBurst, + uint8 tdDone0, uint8 tdDone1, uint8 tdStop) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[0] = (burstCount & 0x7Fu) | ((uint8)((requestPerBurst & 0x1u) << 7u)); + CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[1] = ((uint8)((tdDone1 & 0xFu) << 4u)) | (tdDone0 & 0xFu); + CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[2] = 0x0Fu & tdStop; + CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[3] = 0u; /* burstcount_remain. */ + + status = CYRET_SUCCESS; + } + + return (status); +} + + +/******************************************************************************* +* Function Name: CyDmaTdAllocate +******************************************************************************** +* +* Summary: +* Allocates a TD for use with an allocated DMA channel. +* +* Parameters: +* None +* +* Return: +* Zero-based index of the TD to be used by the caller. Since there are 128 TDs +* minus the reserved TDs (0 to 23), the value returned would range from 24 to +* 127 not 24 to 128. DMA_INVALID_TD is returned if there are no free TDs +* available. +* +*******************************************************************************/ +uint8 CyDmaTdAllocate(void) +{ + uint8 interruptState; + uint8 element = CY_DMA_INVALID_TD; + + /* Enter critical section! */ + interruptState = CyEnterCriticalSection(); + + if(CyDmaTdCurrentNumber > NUMBEROF_CHANNELS) + { + /* Get pointer to the Next available. */ + element = CyDmaTdFreeIndex; + + /* Decrement the count. */ + CyDmaTdCurrentNumber--; + + /* Update the next available pointer. */ + CyDmaTdFreeIndex = CY_DMA_TDMEM_STRUCT_PTR[element].TD0[0]; + } + + /* Exit critical section! */ + CyExitCriticalSection(interruptState); + + return(element); +} + + +/******************************************************************************* +* Function Name: CyDmaTdFree +******************************************************************************** +* +* Summary: +* Returns a TD to the free list. +* +* Parameters: +* uint8 tdHandle: +* The TD handle returned by the CyDmaTdAllocate(). +* +* Return: +* None +* +*******************************************************************************/ +void CyDmaTdFree(uint8 tdHandle) +{ + if(tdHandle < CY_DMA_NUMBEROF_TDS) + { + /* Enter critical section! */ + uint8 interruptState = CyEnterCriticalSection(); + + /* Get pointer to the Next available. */ + CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0u] = CyDmaTdFreeIndex; + + /* Set new Next Available. */ + CyDmaTdFreeIndex = tdHandle; + + /* Keep track of how many left. */ + CyDmaTdCurrentNumber++; + + /* Exit critical section! */ + CyExitCriticalSection(interruptState); + } +} + + +/******************************************************************************* +* Function Name: CyDmaTdFreeCount +******************************************************************************** +* +* Summary: +* Returns the number of free TDs available to be allocated. +* +* Parameters: +* None +* +* Return: +* The number of free TDs. +* +*******************************************************************************/ +uint8 CyDmaTdFreeCount(void) +{ + return(CyDmaTdCurrentNumber - CY_DMA_NUMBEROF_CHANNELS); +} + + +/******************************************************************************* +* Function Name: CyDmaTdSetConfiguration +******************************************************************************** +* +* Summary: +* Configures the TD. +* +* Parameters: +* uint8 tdHandle: +* A handle previously returned by CyDmaTdAlloc(). +* +* uint16 transferCount: +* The size of the data transfer (in bytes) for this TD. A size of zero will +* cause the transfer to continue indefinitely. This parameter is limited to +* 4095 bytes; the TD is not initialized at all when a higher value is passed. +* +* uint8 nextTd: +* Zero based index of the next Transfer Descriptor in the TD chain. Zero is a +* valid pointer to the next TD; DMA_END_CHAIN_TD is the end of the chain. +* DMA_DISABLE_TD indicates an end to the chain and the DMA is disabled. No +* further TDs are fetched. DMA_DISABLE_TD is only supported on PSoC3 and +* PSoC 5LP silicons. +* +* uint8 configuration: +* Stores the Bit field of configuration bits. +* +* CY_DMA_TD_SWAP_EN - Perform endian swap +* +* CY_DMA_TD_SWAP_SIZE4 - Swap size = 4 bytes +* +* CY_DMA_TD_AUTO_EXEC_NEXT - The next TD in the chain will trigger +* automatically when the current TD completes. +* +* CY_DMA_TD_TERMIN_EN - Terminate this TD if a positive edge on the trq +* input line occurs. The positive edge must occur +* during a burst. That is the only time the DMAC +* will listen for it. +* +* DMA__TD_TERMOUT_EN - When this TD completes, the TERMOUT signal will +* generate a pulse. Note that this option is +* instance specific with the instance name followed +* by two underscores. In this example, the instance +* name is DMA. +* +* CY_DMA_TD_INC_DST_ADR - Increment DST_ADR according to the size of each +* data transaction in the burst. +* +* CY_DMA_TD_INC_SRC_ADR - Increment SRC_ADR according to the size of each +* data transaction in the burst. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if tdHandle or transferCount is invalid. +* +*******************************************************************************/ +cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nextTd, uint8 configuration) \ + +{ + cystatus status = CYRET_BAD_PARAM; + + if((tdHandle < CY_DMA_NUMBEROF_TDS) && (0u == (0xF000u & transferCount))) + { + /* Set 12 bits transfer count. */ + reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0u]; + CY_SET_REG16(convert, transferCount); + + /* Set Next TD pointer. */ + CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[2u] = nextTd; + + /* Configure the TD */ + CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[3u] = configuration; + + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaTdGetConfiguration +******************************************************************************** +* +* Summary: +* Retrieves the configuration of the TD. If a NULL pointer is passed as a +* parameter, that parameter is skipped. You may request only the values you are +* interested in. +* +* Parameters: +* uint8 tdHandle: +* A handle previously returned by CyDmaTdAlloc(). +* +* uint16 * transferCount: +* The address to store the size of the data transfer (in bytes) for this TD. +* A size of zero could indicate that the TD has completed its transfer, or +* that the TD is doing an indefinite transfer. +* +* uint8 * nextTd: +* The address to store the index of the next TD in the TD chain. +* +* uint8 * configuration: +* The address to store the Bit field of configuration bits. +* See CyDmaTdSetConfiguration() function description. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if tdHandle is invalid. +* +* Side Effects: +* If a TD has a transfer count of N and is executed, the transfer count becomes +* 0. If it is reexecuted, the Transfer count of zero will be interpreted as a +* request for indefinite transfer. Be careful when requesting a TD with a +* transfer count of zero. +* +*******************************************************************************/ +cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 * nextTd, uint8 * configuration) \ + +{ + cystatus status = CYRET_BAD_PARAM; + + if(tdHandle < CY_DMA_NUMBEROF_TDS) + { + /* If we have a pointer */ + if(NULL != transferCount) + { + /* Get the 12 bits of the transfer count */ + reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0]; + *transferCount = 0x0FFFu & CY_GET_REG16(convert); + } + + /* If we have a pointer */ + if(NULL != nextTd) + { + /* Get the Next TD pointer */ + *nextTd = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[2u]; + } + + /* If we have a pointer */ + if(NULL != configuration) + { + /* Get the configuration the TD */ + *configuration = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[3u]; + } + + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaTdSetAddress +******************************************************************************** +* +* Summary: +* Sets the lower 16 bits of the source and destination addresses for this TD +* only. +* +* Parameters: +* uint8 tdHandle: +* A handle previously returned by CyDmaTdAlloc(). +* +* uint16 source: +* The lower 16 address bits of the source of the data transfer. +* +* uint16 destination: +* The lower 16 address bits of the destination of the data transfer. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if tdHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaTdSetAddress(uint8 tdHandle, uint16 source, uint16 destination) +{ + cystatus status = CYRET_BAD_PARAM; + reg16 *convert; + + if(tdHandle < CY_DMA_NUMBEROF_TDS) + { + /* Set source address */ + convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[0u]; + CY_SET_REG16(convert, source); + + /* Set destination address */ + convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[2u]; + CY_SET_REG16(convert, destination); + + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaTdGetAddress +******************************************************************************** +* +* Summary: +* Retrieves the lower 16 bits of the source and/or destination addresses for +* this TD only. If NULL is passed for a pointer parameter, that value is +* skipped. You may request only the values of interest. +* +* Parameters: +* uint8 tdHandle: +* A handle previously returned by CyDmaTdAlloc(). +* +* uint16 * source: +* The address to store the lower 16 address bits of the source of the data +* transfer. +* +* uint16 * destination: +* The address to store the lower 16 address bits of the destination of the +* data transfer. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if tdHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination) +{ + cystatus status = CYRET_BAD_PARAM; + reg16 *convert; + + if(tdHandle < CY_DMA_NUMBEROF_TDS) + { + /* If we have a pointer. */ + if(NULL != source) + { + /* Get source address */ + convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[0u]; + *source = CY_GET_REG16(convert); + } + + /* If we have a pointer. */ + if(NULL != destination) + { + /* Get Destination address. */ + convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[2u]; + *destination = CY_GET_REG16(convert); + } + + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChRoundRobin +******************************************************************************** +* +* Summary: +* Either enables or disables the Round-Robin scheduling enforcement algorithm. +* Within a priority level a Round-Robin fairness algorithm is enforced. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or Dma_DmaInitialize(). +* +* uint8 enableRR: +* 0: Disable Round-Robin fairness algorithm +* 1: Enable Round-Robin fairness algorithm +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChRoundRobin(uint8 chHandle, uint8 enableRR) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + if (0u != enableRR) + { + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= (uint8)CY_DMA_ROUND_ROBIN_ENABLE; + } + else + { + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_ROUND_ROBIN_ENABLE); + } + + status = CYRET_SUCCESS; + } + + return(status); +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyDmac.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyDmac.h new file mode 100755 index 00000000..5dfac11a --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyDmac.h @@ -0,0 +1,218 @@ +/******************************************************************************* +* File Name: CyDmac.h +* Version 4.0 +* +* Description: +* Provides the function definitions for the DMA Controller. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYDMAC_H) +#define CY_BOOT_CYDMAC_H + + +#include "cytypes.h" +#include "cyfitter.h" +#include "cydevice_trm.h" +#include "CyLib.h" + + +/*************************************** +* Function Prototypes +***************************************/ + +/* DMA Controller functions. */ +void CyDmacConfigure(void) ; +uint8 CyDmacError(void) ; +void CyDmacClearError(uint8 error) ; +uint32 CyDmacErrorAddress(void) ; + +/* Channel specific functions. */ +uint8 CyDmaChAlloc(void) ; +cystatus CyDmaChFree(uint8 chHandle) ; +cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds) ; +cystatus CyDmaChDisable(uint8 chHandle) ; +cystatus CyDmaClearPendingDrq(uint8 chHandle) ; +cystatus CyDmaChPriority(uint8 chHandle, uint8 priority) ; +cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destination)\ +; +cystatus CyDmaChSetInitialTd(uint8 chHandle, uint8 startTd) ; +cystatus CyDmaChSetRequest(uint8 chHandle, uint8 request) ; +cystatus CyDmaChGetRequest(uint8 chHandle) ; +cystatus CyDmaChStatus(uint8 chHandle, uint8 * currentTd, uint8 * state) ; +cystatus CyDmaChSetConfiguration(uint8 chHandle, uint8 burstCount, uint8 requestPerBurst, uint8 tdDone0, + uint8 tdDone1, uint8 tdStop) ; +cystatus CyDmaChRoundRobin(uint8 chHandle, uint8 enableRR) ; + +/* Transfer Descriptor functions. */ +uint8 CyDmaTdAllocate(void) ; +void CyDmaTdFree(uint8 tdHandle) ; +uint8 CyDmaTdFreeCount(void) ; +cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nextTd, uint8 configuration)\ +; +cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 * nextTd, uint8 * configuration)\ +; +cystatus CyDmaTdSetAddress(uint8 tdHandle, uint16 source, uint16 destination) ; +cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination) ; + + +/*************************************** +* Data Struct Definitions +***************************************/ + +typedef struct dmac_ch_struct +{ + volatile uint8 basic_cfg[4]; + volatile uint8 action[4]; + volatile uint8 basic_status[4]; + volatile uint8 reserved[4]; + +} dmac_ch; + + +typedef struct dmac_cfgmem_struct +{ + volatile uint8 CFG0[4]; + volatile uint8 CFG1[4]; + +} dmac_cfgmem; + + +typedef struct dmac_tdmem_struct +{ + volatile uint8 TD0[4]; + volatile uint8 TD1[4]; + +} dmac_tdmem; + + +typedef struct dmac_tdmem2_struct +{ + volatile uint16 xfercnt; + volatile uint8 next_td_ptr; + volatile uint8 flags; + volatile uint16 src_adr; + volatile uint16 dst_adr; +} dmac_tdmem2; + + +/*************************************** +* API Constants +***************************************/ + +#define CY_DMA_INVALID_CHANNEL 0xFFu /* Invalid Channel ID */ +#define CY_DMA_INVALID_TD 0xFFu /* Invalid TD */ +#define CY_DMA_END_CHAIN_TD 0xFFu /* End of chain TD */ +#define CY_DMA_DISABLE_TD 0xFEu + +#define CY_DMA_TD_SIZE 0x08u + +/* The "u" was removed as workaround for Keil compiler bug */ +#define CY_DMA_TD_SWAP_EN 0x80 +#define CY_DMA_TD_SWAP_SIZE4 0x40 +#define CY_DMA_TD_AUTO_EXEC_NEXT 0x20 +#define CY_DMA_TD_TERMIN_EN 0x10 +#define CY_DMA_TD_TERMOUT1_EN 0x08 +#define CY_DMA_TD_TERMOUT0_EN 0x04 +#define CY_DMA_TD_INC_DST_ADR 0x02 +#define CY_DMA_TD_INC_SRC_ADR 0x01 + +#define CY_DMA_NUMBEROF_TDS 128u +#define CY_DMA_NUMBEROF_CHANNELS ((uint8)(CYDEV_DMA_CHANNELS_AVAILABLE)) + +/* Action register bits */ +#define CY_DMA_CPU_REQ ((uint8)(1u << 0u)) +#define CY_DMA_CPU_TERM_TD ((uint8)(1u << 1u)) +#define CY_DMA_CPU_TERM_CHAIN ((uint8)(1u << 2u)) + +/* Basic Status register bits */ +#define CY_DMA_STATUS_CHAIN_ACTIVE ((uint8)(1u << 0u)) +#define CY_DMA_STATUS_TD_ACTIVE ((uint8)(1u << 1u)) + +/* DMA controller register error bits */ +#define CY_DMA_BUS_TIMEOUT (1u << 1u) +#define CY_DMA_UNPOP_ACC (1u << 2u) +#define CY_DMA_PERIPH_ERR (1u << 3u) + +/* Round robin bits */ +#define CY_DMA_ROUND_ROBIN_ENABLE ((uint8)(1u << 4u)) + + +/******************************************************************************* +* CyDmaChEnable() / CyDmaChDisable() API constants +*******************************************************************************/ +#define CY_DMA_CH_BASIC_CFG_EN (0x01u) +#define CY_DMA_CH_BASIC_CFG_WORK_SEP (0x20u) + + +/*************************************** +* Registers +***************************************/ + +#define CY_DMA_CFG_REG (*(reg32 *) CYREG_PHUB_CFG) +#define CY_DMA_CFG_PTR ( (reg32 *) CYREG_PHUB_CFG) + +#define CY_DMA_ERR_REG (*(reg32 *) CYREG_PHUB_ERR) +#define CY_DMA_ERR_PTR ( (reg32 *) CYREG_PHUB_ERR) + +#define CY_DMA_ERR_ADR_REG (*(reg32 *) CYREG_PHUB_ERR_ADR) +#define CY_DMA_ERR_ADR_PTR ( (reg32 *) CYREG_PHUB_ERR_ADR) + +#define CY_DMA_CH_STRUCT_REG (*(dmac_ch CYXDATA *) CYDEV_PHUB_CH0_BASE) +#define CY_DMA_CH_STRUCT_PTR ( (dmac_ch CYXDATA *) CYDEV_PHUB_CH0_BASE) + +#define CY_DMA_CFGMEM_STRUCT_REG (*(dmac_cfgmem CYXDATA *) CYDEV_PHUB_CFGMEM0_BASE) +#define CY_DMA_CFGMEM_STRUCT_PTR ( (dmac_cfgmem CYXDATA *) CYDEV_PHUB_CFGMEM0_BASE) + +#define CY_DMA_TDMEM_STRUCT_REG (*(dmac_tdmem CYXDATA *) CYDEV_PHUB_TDMEM0_BASE) +#define CY_DMA_TDMEM_STRUCT_PTR ( (dmac_tdmem CYXDATA *) CYDEV_PHUB_TDMEM0_BASE) + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from cy_boot 3.0 +*******************************************************************************/ +#define DMA_INVALID_CHANNEL (CY_DMA_INVALID_CHANNEL) +#define DMA_INVALID_TD (CY_DMA_INVALID_TD) +#define DMA_END_CHAIN_TD (CY_DMA_END_CHAIN_TD) +#define DMAC_TD_SIZE (CY_DMA_TD_SIZE) +#define TD_SWAP_EN (CY_DMA_TD_SWAP_EN) +#define TD_SWAP_SIZE4 (CY_DMA_TD_SWAP_SIZE4) +#define TD_AUTO_EXEC_NEXT (CY_DMA_TD_AUTO_EXEC_NEXT) +#define TD_TERMIN_EN (CY_DMA_TD_TERMIN_EN) +#define TD_TERMOUT1_EN (CY_DMA_TD_TERMOUT1_EN) +#define TD_TERMOUT0_EN (CY_DMA_TD_TERMOUT0_EN) +#define TD_INC_DST_ADR (CY_DMA_TD_INC_DST_ADR) +#define TD_INC_SRC_ADR (CY_DMA_TD_INC_SRC_ADR) +#define NUMBEROF_TDS (CY_DMA_NUMBEROF_TDS) +#define NUMBEROF_CHANNELS (CY_DMA_NUMBEROF_CHANNELS) +#define CPU_REQ (CY_DMA_CPU_REQ) +#define CPU_TERM_TD (CY_DMA_CPU_TERM_TD) +#define CPU_TERM_CHAIN (CY_DMA_CPU_TERM_CHAIN) +#define STATUS_CHAIN_ACTIVE (CY_DMA_STATUS_CHAIN_ACTIVE) +#define STATUS_TD_ACTIVE (CY_DMA_STATUS_TD_ACTIVE) +#define DMAC_BUS_TIMEOUT (CY_DMA_BUS_TIMEOUT) +#define DMAC_UNPOP_ACC (CY_DMA_UNPOP_ACC) +#define DMAC_PERIPH_ERR (CY_DMA_PERIPH_ERR) +#define ROUND_ROBIN_ENABLE (CY_DMA_ROUND_ROBIN_ENABLE) +#define DMA_DISABLE_TD (CY_DMA_DISABLE_TD) + +#define DMAC_CFG (CY_DMA_CFG_PTR) +#define DMAC_ERR (CY_DMA_ERR_PTR) +#define DMAC_ERR_ADR (CY_DMA_ERR_ADR_PTR) +#define DMAC_CH (CY_DMA_CH_STRUCT_PTR) +#define DMAC_CFGMEM (CY_DMA_CFGMEM_STRUCT_PTR) +#define DMAC_TDMEM (CY_DMA_TDMEM_STRUCT_PTR) + +#endif /* (CY_BOOT_CYDMAC_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyFlash.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyFlash.c new file mode 100755 index 00000000..6f27d8c0 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyFlash.c @@ -0,0 +1,694 @@ +/******************************************************************************* +* File Name: CyFlash.c +* Version 4.0 +* +* Description: +* Provides an API for the FLASH/EEPROM. +* +* Note: +* This code is endian agnostic. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "CyFlash.h" + + +/******************************************************************************* +* Holds die temperature, updated by CySetTemp(). Used for flash writting. +* The first byte is the sign of the temperature (0 = negative, 1 = positive). +* The second byte is the magnitude. +*******************************************************************************/ +uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE]; + +#if(CYDEV_ECC_ENABLE == 0) + static uint8 * rowBuffer = 0; +#endif /* (CYDEV_ECC_ENABLE == 0) */ + + +static cystatus CySetTempInt(void); + + +/******************************************************************************* +* Function Name: CyFlash_Start +******************************************************************************** +* +* Summary: +* Enable the Flash. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyFlash_Start(void) +{ + /* Active Power Mode */ + *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK; + + /* Standby Power Mode */ + *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK; + + CyDelayUs(CY_FLASH_EE_STARTUP_DELAY); +} + + +/******************************************************************************* +* Function Name: CyFlash_Stop +******************************************************************************** +* +* Summary: +* Disable the Flash. +* +* Parameters: +* None +* +* Return: +* None +* +* Side Effects: +* This setting is ignored as long as the CPU is currently running. This will +* only take effect when the CPU is later disabled. +* +*******************************************************************************/ +void CyFlash_Stop(void) +{ + /* Active Power Mode */ + *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK)); + + /* Standby Power Mode */ + *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK)); +} + + +/******************************************************************************* +* Function Name: CySetTempInt +******************************************************************************** +* +* Summary: +* Sends a command to the SPC to read the die temperature. Sets a global value +* used by the Write functions. This function must be called once before +* executing a series of Flash writing functions. +* +* Parameters: +* None +* +* Return: +* status: +* CYRET_SUCCESS - if successful +* CYRET_LOCKED - if Flash writing already in use +* CYRET_UNKNOWN - if there was an SPC error +* +*******************************************************************************/ +static cystatus CySetTempInt(void) +{ + cystatus status; + + /* Make sure SPC is powered */ + CySpcStart(); + + /* Plan for failure. */ + status = CYRET_UNKNOWN; + + if(CySpcLock() == CYRET_SUCCESS) + { + /* Write the command. */ + if(CYRET_STARTED == CySpcGetTemp(CY_TEMP_NUMBER_OF_SAMPLES)) + { + do + { + if(CySpcReadData(dieTemperature, CY_FLASH_DIE_TEMP_DATA_SIZE) == CY_FLASH_DIE_TEMP_DATA_SIZE) + { + status = CYRET_SUCCESS; + + while(CY_SPC_BUSY) + { + /* Spin until idle. */ + CyDelayUs(1u); + } + break; + } + + } while(CY_SPC_BUSY); + } + + CySpcUnlock(); + } + else + { + status = CYRET_LOCKED; + } + + return (status); +} + + +/******************************************************************************* +* Function Name: CySetTemp +******************************************************************************** +* +* Summary: +* This is a wraparound for CySetTempInt(). It is used to return second +* successful read of temperature value. +* +* Parameters: +* None +* +* Return: +* status: +* CYRET_SUCCESS if successful. +* CYRET_LOCKED if Flash writing already in use +* CYRET_UNKNOWN if there was an SPC error. +* +* uint8 dieTemperature[2]: +* Holds die temperature for the flash writting algorithm. The first byte is +* the sign of the temperature (0 = negative, 1 = positive). The second byte is +* the magnitude. +* +*******************************************************************************/ +cystatus CySetTemp(void) +{ + cystatus status = CySetTempInt(); + + if(status == CYRET_SUCCESS) + { + status = CySetTempInt(); + } + + return (status); +} + + +/******************************************************************************* +* Function Name: CySetFlashEEBuffer +******************************************************************************** +* +* Summary: +* Sets the user supplied temporary buffer to store SPC data while performing +* flash and EEPROM commands. This buffer is only necessary when Flash ECC is +* disabled. +* +* Parameters: +* buffer: +* Address of block of memory to store temporary memory. The size of the block +* of memory is CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE. +* +* Return: +* status: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if the buffer is NULL +* +*******************************************************************************/ +cystatus CySetFlashEEBuffer(uint8 * buffer) +{ + cystatus status = CYRET_SUCCESS; + + CySpcStart(); + + #if(CYDEV_ECC_ENABLE == 0) + + if(NULL == buffer) + { + status = CYRET_BAD_PARAM; + } + else if(CySpcLock() != CYRET_SUCCESS) + { + status = CYRET_LOCKED; + } + else + { + rowBuffer = buffer; + CySpcUnlock(); + } + + #else + + /* To supress the warning */ + buffer = buffer; + + #endif /* (CYDEV_ECC_ENABLE == 0u) */ + + return(status); +} + + +#if(CYDEV_ECC_ENABLE == 1) + + /******************************************************************************* + * Function Name: CyWriteRowData + ******************************************************************************** + * + * Summary: + * Sends a command to the SPC to load and program a row of data in + * Flash or EEPROM. + * + * Parameters: + * arrayID: ID of the array to write. + * The type of write, Flash or EEPROM, is determined from the array ID. + * The arrays in the part are sequential starting at the first ID for the + * specific memory type. The array ID for the Flash memory lasts from 0x00 to + * 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F. + * rowAddress: rowAddress of flash row to program. + * rowData: Array of bytes to write. + * + * Return: + * status: + * CYRET_SUCCESS if successful. + * CYRET_LOCKED if the SPC is already in use. + * CYRET_CANCELED if command not accepted + * CYRET_UNKNOWN if there was an SPC error. + * + *******************************************************************************/ + cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) + { + uint16 rowSize; + cystatus status; + + rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? CYDEV_EEPROM_ROW_SIZE : CYDEV_FLS_ROW_SIZE; + status = CyWriteRowFull(arrayId, rowAddress, rowData, rowSize); + + return(status); + } + +#else + + /******************************************************************************* + * Function Name: CyWriteRowData + ******************************************************************************** + * + * Summary: + * Sends a command to the SPC to load and program a row of data in + * Flash or EEPROM. + * + * Parameters: + * arrayID : ID of the array to write. + * The type of write, Flash or EEPROM, is determined from the array ID. + * The arrays in the part are sequential starting at the first ID for the + * specific memory type. The array ID for the Flash memory lasts from 0x00 to + * 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F. + * rowAddress : rowAddress of flash row to program. + * rowData : Array of bytes to write. + * + * Return: + * status: + * CYRET_SUCCESS if successful. + * CYRET_LOCKED if the SPC is already in use. + * CYRET_CANCELED if command not accepted + * CYRET_UNKNOWN if there was an SPC error. + * + *******************************************************************************/ + cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) + { + uint8 i; + uint32 offset; + uint16 rowSize; + cystatus status; + + /* Check whether rowBuffer pointer has been initialized by CySetFlashEEBuffer() */ + if(NULL != rowBuffer) + { + if(arrayId > CY_SPC_LAST_FLASH_ARRAYID) + { + rowSize = CYDEV_EEPROM_ROW_SIZE; + } + else + { + rowSize = CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE; + + /* Save the ECC area. */ + offset = CYDEV_ECC_BASE + + ((uint32)arrayId * CYDEV_ECC_SECTOR_SIZE) + + ((uint32)rowAddress * CYDEV_ECC_ROW_SIZE); + + for(i = 0u; i < CYDEV_ECC_ROW_SIZE; i++) + { + *(rowBuffer + CYDEV_FLS_ROW_SIZE + i) = CY_GET_XTND_REG8((void CYFAR *)(offset + i)); + } + } + + /* Copy the rowdata to the temporary buffer. */ + #if(CY_PSOC3) + (void) memcpy((void *) rowBuffer, (void *)((uint32) rowData), (int16) CYDEV_FLS_ROW_SIZE); + #else + (void) memcpy((void *) rowBuffer, (const void *) rowData, CYDEV_FLS_ROW_SIZE); + #endif /* (CY_PSOC3) */ + + status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, rowSize); + } + else + { + status = CYRET_UNKNOWN; + } + + return(status); + } + +#endif /* (CYDEV_ECC_ENABLE == 0u) */ + + +#if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) + + /******************************************************************************* + * Function Name: CyWriteRowConfig + ******************************************************************************** + * + * Summary: + * Sends a command to the SPC to load and program a row of config data in flash. + * This function is only valid for Flash array IDs (not for EEPROM). + * + * Parameters: + * arrayId: ID of the array to write + * The arrays in the part are sequential starting at the first ID for the + * specific memory type. The array ID for the Flash memory lasts + * from 0x00 to 0x3F. + * rowAddress: Address of the sector to erase. + * rowECC: Array of bytes to write. + * + * Return: + * status: + * CYRET_SUCCESS if successful. + * CYRET_LOCKED if the SPC is already in use. + * CYRET_CANCELED if command not accepted + * CYRET_UNKNOWN if there was an SPC error. + * + *******************************************************************************/ + cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC)\ + + { + uint32 offset; + uint16 i; + cystatus status; + + /* Check whether rowBuffer pointer has been initialized by CySetFlashEEBuffer() */ + if(NULL != rowBuffer) + { + /* Read the existing flash data. */ + offset = ((uint32)arrayId * CYDEV_FLS_SECTOR_SIZE) + + ((uint32)rowAddress * CYDEV_FLS_ROW_SIZE); + + #if (CYDEV_FLS_BASE != 0u) + offset += CYDEV_FLS_BASE; + #endif /* (CYDEV_FLS_BASE != 0u) */ + + for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++) + { + rowBuffer[i] = CY_GET_XTND_REG8((void CYFAR *)(offset + i)); + } + + #if(CY_PSOC3) + (void) memcpy((void *)&rowBuffer[CYDEV_FLS_ROW_SIZE], + (void *)(uint32)rowECC, + (int16)CYDEV_ECC_ROW_SIZE); + #else + (void) memcpy((void *)&rowBuffer[CYDEV_FLS_ROW_SIZE], + (const void *)rowECC, + CYDEV_ECC_ROW_SIZE); + #endif /* (CY_PSOC3) */ + + status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE); + } + else + { + status = CYRET_UNKNOWN; + } + + return (status); + } + +#endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */ + + + +/******************************************************************************* +* Function Name: CyWriteRowFull +******************************************************************************** +* Summary: +* Sends a command to the SPC to load and program a row of data in flash. +* rowData array is expected to contain Flash and ECC data if needed. +* +* Parameters: +* arrayId: FLASH or EEPROM array id. +* rowData: Pointer to a row of data to write. +* rowNumber: Zero based number of the row. +* rowSize: Size of the row. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_LOCKED if the SPC is already in use. +* CYRET_CANCELED if command not accepted +* CYRET_UNKNOWN if there was an SPC error. +* +*******************************************************************************/ +cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8* rowData, uint16 rowSize) \ + +{ + cystatus status; + + if(CySpcLock() == CYRET_SUCCESS) + { + /* Load row data into SPC internal latch */ + status = CySpcLoadRow(arrayId, rowData, rowSize); + + if(CYRET_STARTED == status) + { + while(CY_SPC_BUSY) + { + /* Wait for SPC to finish and get SPC status */ + CyDelayUs(1u); + } + + /* Hide SPC status */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + else + { + status = CYRET_UNKNOWN; + } + + if(CYRET_SUCCESS == status) + { + /* Erase and program flash with the data from SPC interval latch */ + status = CySpcWriteRow(arrayId, rowNumber, dieTemperature[0u], dieTemperature[1u]); + + if(CYRET_STARTED == status) + { + while(CY_SPC_BUSY) + { + /* Wait for SPC to finish and get SPC status */ + CyDelayUs(1u); + } + + /* Hide SPC status */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + else + { + status = CYRET_UNKNOWN; + } + } + } + + } + + CySpcUnlock(); + } + else + { + status = CYRET_LOCKED; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyFlash_SetWaitCycles +******************************************************************************** +* +* Summary: +* Sets the number of clock cycles the cache will wait before it samples data +* coming back from Flash. This function must be called before increasing CPU +* clock frequency. It can optionally be called after lowering CPU clock +* frequency in order to improve CPU performance. +* +* Parameters: +* uint8 freq: +* Frequency of operation in Megahertz. +* +* Return: +* None +* +*******************************************************************************/ +void CyFlash_SetWaitCycles(uint8 freq) +{ + uint8 interruptState; + + /* Save current global interrupt enable and disable it */ + interruptState = CyEnterCriticalSection(); + + /*************************************************************************** + * The number of clock cycles the cache will wait before it samples data + * coming back from Flash must be equal or greater to to the CPU frequency + * outlined in clock cycles. + ***************************************************************************/ + + #if (CY_PSOC3) + + if (freq <= 22u) + { + *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | + ((uint8)(CY_FLASH_LESSER_OR_EQUAL_22MHz << CY_FLASH_CYCLES_MASK_SHIFT))); + } + else if (freq <= 44u) + { + *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | + ((uint8)(CY_FLASH_LESSER_OR_EQUAL_44MHz << CY_FLASH_CYCLES_MASK_SHIFT))); + } + else + { + *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | + ((uint8)(CY_FLASH_GREATER_44MHz << CY_FLASH_CYCLES_MASK_SHIFT))); + } + + #endif /* (CY_PSOC3) */ + + + #if (CY_PSOC5) + + if (freq <= 16u) + { + *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | + ((uint8)(CY_FLASH_LESSER_OR_EQUAL_16MHz << CY_FLASH_CYCLES_MASK_SHIFT))); + } + else if (freq <= 33u) + { + *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | + ((uint8)(CY_FLASH_LESSER_OR_EQUAL_33MHz << CY_FLASH_CYCLES_MASK_SHIFT))); + } + else if (freq <= 50u) + { + *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | + ((uint8)(CY_FLASH_LESSER_OR_EQUAL_50MHz << CY_FLASH_CYCLES_MASK_SHIFT))); + } + else + { + *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | + ((uint8)(CY_FLASH_GREATER_51MHz << CY_FLASH_CYCLES_MASK_SHIFT))); + } + + #endif /* (CY_PSOC5) */ + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyEEPROM_Start +******************************************************************************** +* +* Summary: +* Enable the EEPROM. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyEEPROM_Start(void) +{ + /* Active Power Mode */ + *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK; + + /* Standby Power Mode */ + *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK; +} + + +/******************************************************************************* +* Function Name: CyEEPROM_Stop +******************************************************************************** +* +* Summary: +* Disable the EEPROM. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyEEPROM_Stop (void) +{ + /* Active Power Mode */ + *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK)); + + /* Standby Power Mode */ + *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK)); +} + + +/******************************************************************************* +* Function Name: CyEEPROM_ReadReserve +******************************************************************************** +* +* Summary: +* Request access to the EEPROM for reading and wait until access is available. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyEEPROM_ReadReserve(void) +{ + /* Make a request for PHUB to have access */ + *CY_FLASH_EE_SCR_PTR |= CY_FLASH_EE_SCR_AHB_EE_REQ; + + while (0u == (*CY_FLASH_EE_SCR_PTR & CY_FLASH_EE_SCR_AHB_EE_ACK)) + { + /* Wait for acknowledgement from PHUB */ + } +} + + +/******************************************************************************* +* Function Name: CyEEPROM_ReadRelease +******************************************************************************** +* +* Summary: +* Release the read reservation of the EEPROM. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyEEPROM_ReadRelease(void) +{ + *CY_FLASH_EE_SCR_PTR |= 0x00u; +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyFlash.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyFlash.h new file mode 100755 index 00000000..002b2ebf --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyFlash.h @@ -0,0 +1,239 @@ +/******************************************************************************* +* File Name: CyFlash.h +* Version 4.0 +* +* Description: +* Provides the function definitions for the FLASH/EEPROM. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYFLASH_H) +#define CY_BOOT_CYFLASH_H + +#include "cydevice_trm.h" +#include "cytypes.h" +#include "CyLib.h" +#include "CySpc.h" + +#define CY_FLASH_DIE_TEMP_DATA_SIZE (2u) /* Die temperature data size */ + +extern uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE]; + + +/*************************************** +* API Constants +***************************************/ + +#define CY_FLASH_BASE (CYDEV_FLASH_BASE) +#define CY_FLASH_SIZE (CYDEV_FLS_SIZE) +#define CY_FLASH_SIZEOF_ARRAY (CYDEV_FLS_SECTOR_SIZE) +#define CY_FLASH_SIZEOF_ROW (CYDEV_FLS_ROW_SIZE) +#define CY_FLASH_SIZEOF_ECC_ROW (CYDEV_ECC_ROW_SIZE) +#define CY_FLASH_NUMBER_ROWS (CYDEV_FLS_SIZE / CYDEV_FLS_ROW_SIZE) +#define CY_FLASH_NUMBER_ARRAYS (CYDEV_FLS_SIZE / CYDEV_FLS_SECTOR_SIZE) + +#define CY_EEPROM_BASE (CYDEV_EE_BASE) +#define CY_EEPROM_SIZE (CYDEV_EE_SIZE) +#define CY_EEPROM_SIZEOF_ARRAY (CYDEV_EEPROM_SECTOR_SIZE) +#define CY_EEPROM_SIZEOF_ROW (CYDEV_EEPROM_ROW_SIZE) +#define CY_EEPROM_NUMBER_ROWS (EEPROM_SIZE / CYDEV_EEPROM_ROW_SIZE) +#define CY_EEPROM_NUMBER_ARRAYS (CYDEV_EE_SIZE / CY_EEPROM_SIZEOF_ARRAY) + + +#if !defined(CYDEV_FLS_BASE) + #define CYDEV_FLS_BASE CYDEV_FLASH_BASE +#endif /* !defined(CYDEV_FLS_BASE) */ + + +/*************************************** +* Function Prototypes +***************************************/ + +/* Flash Functions */ +void CyFlash_Start(void); +void CyFlash_Stop(void); +cystatus CySetTemp(void); +cystatus CySetFlashEEBuffer(uint8 * buffer); +cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8 * rowData, uint16 rowSize) \ + ; +cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData); + +#if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) + cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC) \ + ; +#endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */ + +void CyFlash_SetWaitCycles(uint8 freq) ; + +/* EEPROM Functions */ +void CyEEPROM_Start(void) ; +void CyEEPROM_Stop(void) ; + +void CyEEPROM_ReadReserve(void) ; +void CyEEPROM_ReadRelease(void) ; + + +/*************************************** +* Registers +***************************************/ +/* Active Power Mode Configuration Register 12 */ +#define CY_FLASH_PM_ACT_EEFLASH_REG (* (reg8 *) CYREG_PM_ACT_CFG12) +#define CY_FLASH_PM_ACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_ACT_CFG12) + +/* Alternate Active Power Mode Configuration Register 12 */ +#define CY_FLASH_PM_ALTACT_EEFLASH_REG (* (reg8 *) CYREG_PM_STBY_CFG12) +#define CY_FLASH_PM_ALTACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_STBY_CFG12) + + +/* Cache Control Register */ +#if (CY_PSOC3) + + #define CY_FLASH_CONTROL_REG (* (reg8 *) CYREG_CACHE_CR ) + #define CY_FLASH_CONTROL_PTR ( (reg8 *) CYREG_CACHE_CR ) + +#else + + #define CY_FLASH_CONTROL_REG (* (reg8 *) CYREG_CACHE_CC_CTL ) + #define CY_FLASH_CONTROL_PTR ( (reg8 *) CYREG_CACHE_CC_CTL ) + +#endif /* (CY_PSOC3) */ + + +/* EEPROM Status & Control Register */ +#define CY_FLASH_EE_SCR_REG (* (reg8 *) CYREG_SPC_EE_SCR) +#define CY_FLASH_EE_SCR_PTR ( (reg8 *) CYREG_SPC_EE_SCR) + + + +/*************************************** +* Register Constants +***************************************/ + +/* Power Mode Masks */ +#define CY_FLASH_PM_EE_MASK (0x10u) +#define CY_FLASH_PM_FLASH_MASK (0x01u) + +/* Frequency Constants */ +#if (CY_PSOC3) + + #define CY_FLASH_LESSER_OR_EQUAL_22MHz (0x01u) + #define CY_FLASH_LESSER_OR_EQUAL_44MHz (0x02u) + #define CY_FLASH_GREATER_44MHz (0x03u) + +#endif /* (CY_PSOC3) */ + +#if (CY_PSOC5) + + #define CY_FLASH_LESSER_OR_EQUAL_16MHz (0x01u) + #define CY_FLASH_LESSER_OR_EQUAL_33MHz (0x02u) + #define CY_FLASH_LESSER_OR_EQUAL_50MHz (0x03u) + #define CY_FLASH_GREATER_51MHz (0x00u) + +#endif /* (CY_PSOC5) */ + +#define CY_FLASH_CYCLES_MASK_SHIFT (0x06u) +#define CY_FLASH_CYCLES_MASK ((uint8)(0x03u << (CY_FLASH_CYCLES_MASK_SHIFT))) +#define CY_FLASH_EE_STARTUP_DELAY (5u) + +#define CY_FLASH_EE_SCR_AHB_EE_REQ (0x01u) +#define CY_FLASH_EE_SCR_AHB_EE_ACK (0x02u) + + + +/* Default values for getting temperature. */ + +#define CY_TEMP_NUMBER_OF_SAMPLES (0x1u) +#define CY_TEMP_TIMER_PERIOD (0xFFFu) +#define CY_TEMP_CLK_DIV_SELECT (0x4u) +#define CY_TEMP_NUM_SAMPLES (1 << (CY_TEMP_NUMBER_OF_SAMPLES)) +#define CY_SPC_CLK_PERIOD (120u) /* nS */ +#define CY_SYS_ns_PER_TICK (1000u) +#define CY_FRM_EXEC_TIME (1000u) /* nS */ + +#define CY_GET_TEMP_TIME ((1 << (CY_TEMP_NUM_SAMPLES + 1)) * \ + (CY_SPC_CLK_PERIOD * CY_TEMP_CLK_DIV_SELECT) * \ + CY_TEMP_TIMER_PERIOD + CY_FRM_EXEC_TIME) + +#define CY_TEMP_MAX_WAIT ((CY_GET_TEMP_TIME) / CY_SYS_ns_PER_TICK) /* In system ticks. */ + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from cy_boot 3.0 +*******************************************************************************/ +#define FLASH_SIZE (CY_FLASH_SIZE) +#define FLASH_SIZEOF_SECTOR (CY_FLASH_SIZEOF_ARRAY) +#define FLASH_NUMBER_ROWS (CY_FLASH_NUMBER_ROWS) +#define FLASH_NUMBER_SECTORS (CY_FLASH_NUMBER_ARRAYS) +#define EEPROM_SIZE (CY_EEPROM_SIZE) +#define EEPROM_SIZEOF_SECTOR (CY_EEPROM_SIZEOF_ARRAY) +#define EEPROM_NUMBER_ROWS (CY_EEPROM_NUMBER_ROWS) +#define EEPROM_NUMBER_SECTORS (CY_EEPROM_NUMBER_ARRAYS) +#define CY_EEPROM_NUMBER_SECTORS (CY_EEPROM_NUMBER_ARRAYS) +#define CY_EEPROM_SIZEOF_SECTOR (CY_EEPROM_SIZEOF_ARRAY) + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from cy_boot 3.30 +*******************************************************************************/ +#define FLASH_CYCLES_PTR (CY_FLASH_CONTROL_PTR) + +#define TEMP_NUMBER_OF_SAMPLES (CY_TEMP_NUMBER_OF_SAMPLES) +#define TEMP_TIMER_PERIOD (CY_TEMP_TIMER_PERIOD) +#define TEMP_CLK_DIV_SELECT (CY_TEMP_CLK_DIV_SELECT) +#define NUM_SAMPLES (CY_TEMP_NUM_SAMPLES) +#define SPC_CLK_PERIOD (CY_SPC_CLK_PERIOD) +#define FRM_EXEC_TIME (CY_FRM_EXEC_TIME) +#define GET_TEMP_TIME (CY_GET_TEMP_TIME) +#define TEMP_MAX_WAIT (CY_TEMP_MAX_WAIT) + +#define ECC_ADDR (0x80u) + + +#define PM_ACT_EE_PTR (CY_FLASH_PM_ACT_EEFLASH_PTR) +#define PM_ACT_FLASH_PTR (CY_FLASH_PM_ACT_EEFLASH_PTR) + +#define PM_STBY_EE_PTR (CY_FLASH_PM_ALTACT_EEFLASH_PTR) +#define PM_STBY_FLASH_PTR (CY_FLASH_PM_ALTACT_EEFLASH_PTR) + +#define PM_EE_MASK (CY_FLASH_PM_EE_MASK) +#define PM_FLASH_MASK (CY_FLASH_PM_FLASH_MASK) + +#define FLASH_CYCLES_MASK_SHIFT (CY_FLASH_CYCLES_MASK_SHIFT) +#define FLASH_CYCLES_MASK (CY_FLASH_CYCLES_MASK) + + +#if (CY_PSOC3) + + #define LESSER_OR_EQUAL_22MHz (CY_FLASH_LESSER_OR_EQUAL_22MHz) + #define LESSER_OR_EQUAL_44MHz (CY_FLASH_LESSER_OR_EQUAL_44MHz) + #define GREATER_44MHz (CY_FLASH_GREATER_44MHz) + +#endif /* (CY_PSOC3) */ + +#if (CY_PSOC5) + + #define LESSER_OR_EQUAL_16MHz (CY_FLASH_LESSER_OR_EQUAL_16MHz) + #define LESSER_OR_EQUAL_33MHz (CY_FLASH_LESSER_OR_EQUAL_33MHz) + #define LESSER_OR_EQUAL_50MHz (CY_FLASH_LESSER_OR_EQUAL_50MHz) + #define LESSER_OR_EQUAL_67MHz (CY_FLASH_LESSER_OR_EQUAL_67MHz) + #define GREATER_67MHz (CY_FLASH_GREATER_67MHz) + #define GREATER_51MHz (CY_FLASH_GREATER_51MHz) + +#endif /* (CY_PSOC5) */ + +#define AHUB_EE_REQ_ACK_PTR (CY_FLASH_EE_SCR_PTR) + + +#endif /* (CY_BOOT_CYFLASH_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyLib.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyLib.c new file mode 100755 index 00000000..5278bdf1 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyLib.c @@ -0,0 +1,2710 @@ +/******************************************************************************* +* File Name: CyLib.c +* Version 4.0 +* +* Description: +* Provides system API for the clocking, interrupts and watchdog timer. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "CyLib.h" + + +/******************************************************************************* +* The CyResetStatus variable is used to obtain value of RESET_SR0 register after +* a device reset. It is set from initialize_psoc() at the early initialization +* stage. In case of IAR EW IDE, initialize_psoc() is executed before the data +* sections are initialized. To avoid zeroing, CyResetStatus should be placed +* to the .noinit section. +*******************************************************************************/ +CY_NOINIT uint8 CYXDATA CyResetStatus; + + +/* Variable Vdda */ +#if(CYDEV_VARIABLE_VDDA == 1) + + uint8 CyScPumpEnabled = (uint8)(CYDEV_VDDA_MV < 2700); + +#endif /* (CYDEV_VARIABLE_VDDA == 1) */ + + +/* Do not use these definitions directly in your application */ +uint32 cydelay_freq_hz = BCLK__BUS_CLK__HZ; +uint32 cydelay_freq_khz = (BCLK__BUS_CLK__HZ + 999u) / 1000u; +uint8 cydelay_freq_mhz = (uint8)((BCLK__BUS_CLK__HZ + 999999u) / 1000000u); +uint32 cydelay_32k_ms = 32768u * ((BCLK__BUS_CLK__HZ + 999u) / 1000u); + + +/* Function Prototypes */ +static uint8 CyUSB_PowerOnCheck(void) ; +static void CyIMO_SetTrimValue(uint8 freq) ; +static void CyBusClk_Internal_SetDivider(uint16 divider); + + +/******************************************************************************* +* Function Name: CyPLL_OUT_Start +******************************************************************************** +* +* Summary: +* Enables the PLL. Optionally waits for it to become stable. +* Waits at least 250 us or until it is detected that the PLL is stable. +* +* Parameters: +* wait: +* 0: Return immediately after configuration +* 1: Wait for PLL lock or timeout. +* +* Return: +* Status +* CYRET_SUCCESS - Completed successfully +* CYRET_TIMEOUT - Timeout occurred without detecting a stable clock. +* If the input source of the clock is jittery, then the lock indication +* may not occur. However, after the timeout has expired the generated PLL +* clock can still be used. +* +* Side Effects: +* If wait is enabled: This function wses the Fast Time Wheel to time the wait. +* Any other use of the Fast Time Wheel will be stopped during the period of +* this function and then restored. This function also uses the 100 KHz ILO. +* If not enabled, this function will enable the 100 KHz ILO for the period of +* this function. +* +* No changes to the setup of the ILO, Fast Time Wheel, Central Time Wheel or +* Once Per Second interrupt may be made by interrupt routines during the period +* of this function execution. The current operation of the ILO, Central Time +* Wheel and Once Per Second interrupt are maintained during the operation of +* this function provided the reading of the Power Manager Interrupt Status +* Register is only done using the CyPmReadStatus() function. +* +*******************************************************************************/ +cystatus CyPLL_OUT_Start(uint8 wait) +{ + cystatus status = CYRET_SUCCESS; + + uint8 iloEnableState; + uint8 pmTwCfg0State; + uint8 pmTwCfg2State; + + + /* Enables the PLL circuit */ + CY_CLK_PLL_CFG0_REG |= CY_CLK_PLL_ENABLE; + + if(wait != 0u) + { + /* Save 100 KHz ILO, FTW interval, enable and interrupt enable */ + iloEnableState = CY_LIB_SLOWCLK_ILO_CR0_REG & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ; + pmTwCfg0State = CY_LIB_PM_TW_CFG0_REG; + pmTwCfg2State = CY_LIB_PM_TW_CFG2_REG; + + CyPmFtwSetInterval(CY_CLK_PLL_FTW_INTERVAL); + + status = CYRET_TIMEOUT; + + while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT))) + { + /* Wait for the interrupt status */ + if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS)) + { + if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS)) + { + status = CYRET_SUCCESS; + break; + } + } + } + + /* Restore 100 KHz ILO, FTW interval, enable and interrupt enable */ + if(0u == iloEnableState) + { + CyILO_Stop100K(); + } + + CY_LIB_PM_TW_CFG0_REG = pmTwCfg0State; + CY_LIB_PM_TW_CFG2_REG = pmTwCfg2State; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyPLL_OUT_Stop +******************************************************************************** +* +* Summary: +* Disables the PLL. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyPLL_OUT_Stop(void) +{ + CY_CLK_PLL_CFG0_REG &= ((uint8)(~CY_CLK_PLL_ENABLE)); +} + + +/******************************************************************************* +* Function Name: CyPLL_OUT_SetPQ +******************************************************************************** +* +* Summary: +* Sets the P and Q dividers and the charge pump current. +* The Frequency Out will be P/Q * Frequency In. +* The PLL must be disabled before calling this function. +* +* Parameters: +* uint8 pDiv: +* Valid range [8 - 255]. +* +* uint8 qDiv: +* Valid range [1 - 16]. Input Frequency / Q must be in range of 1 to 3 MHz. + +* uint8 current: +* Valid range [1 - 7]. Charge pump current in uA. Refer to the device TRM and +* datasheet for more information. +* +* Return: +* None +* +* Side Effects: +* If as result of this function execution the CPU clock frequency is increased +* then the number of clock cycles the cache will wait before it samples data +* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() +* with appropriate parameter. It can be optionally called if CPU clock +* frequency is lowered in order to improve CPU performance. +* See CyFlash_SetWaitCycles() description for more information. +* +*******************************************************************************/ +void CyPLL_OUT_SetPQ(uint8 pDiv, uint8 qDiv, uint8 current) +{ + /* Halt CPU in debug mode if PLL is enabled */ + CYASSERT(0u == (CY_CLK_PLL_CFG0_REG & CY_CLK_PLL_ENABLE)); + + if((pDiv >= CY_CLK_PLL_MIN_P_VALUE ) && + (qDiv <= CY_CLK_PLL_MAX_Q_VALUE ) && (qDiv >= CY_CLK_PLL_MIN_Q_VALUE ) && + (current >= CY_CLK_PLL_MIN_CUR_VALUE) && (current <= CY_CLK_PLL_MAX_CUR_VALUE)) + { + /* Set new values */ + CY_CLK_PLL_P_REG = pDiv; + CY_CLK_PLL_Q_REG = ((uint8)(qDiv - 1u)); + CY_CLK_PLL_CFG1_REG = (CY_CLK_PLL_CFG1_REG & CY_CLK_PLL_CURRENT_MASK) | + ((uint8)(((uint8)(current - 1u)) << CY_CLK_PLL_CURRENT_POSITION)); + } + else + { + /*********************************************************************** + * Halt CPU in debug mode if: + * - P divider is less than required + * - Q divider is out of range + * - pump current is out of range + ***********************************************************************/ + CYASSERT(0u != 0u); + } + +} + + +/******************************************************************************* +* Function Name: CyPLL_OUT_SetSource +******************************************************************************** +* +* Summary: +* Sets the input clock source to the PLL. The PLL must be disabled before +* calling this function. +* +* Parameters: +* source: One of the three available PLL clock sources +* CY_PLL_SOURCE_IMO : IMO +* CY_PLL_SOURCE_XTAL : MHz Crystal +* CY_PLL_SOURCE_DSI : DSI +* +* Return: +* None +* +* Side Effects: +* If as result of this function execution the CPU clock frequency is increased +* then the number of clock cycles the cache will wait before it samples data +* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() +* with appropriate parameter. It can be optionally called if CPU clock +* frequency is lowered in order to improve CPU performance. +* See CyFlash_SetWaitCycles() description for more information. +* +*******************************************************************************/ +void CyPLL_OUT_SetSource(uint8 source) +{ + /* Halt CPU in debug mode if PLL is enabled */ + CYASSERT(0u == (CY_CLK_PLL_CFG0_REG & CY_CLK_PLL_ENABLE)); + + switch(source) + { + case CY_PLL_SOURCE_IMO: + case CY_PLL_SOURCE_XTAL: + case CY_PLL_SOURCE_DSI: + CY_LIB_CLKDIST_CR_REG = ((CY_LIB_CLKDIST_CR_REG & CY_LIB_CLKDIST_CR_PLL_SCR_MASK) | source); + break; + + default: + CYASSERT(0u != 0u); + break; + } +} + + +/******************************************************************************* +* Function Name: CyIMO_Start +******************************************************************************** +* +* Summary: +* Enables the IMO. Optionally waits at least 6 us for it to settle. +* +* Parameters: +* uint8 wait: +* 0: Return immediately after configuration +* 1: Wait for at least 6 us for the IMO to settle. +* +* Return: +* None +* +* Side Effects: +* If wait is enabled: This function wses the Fast Time Wheel to time the wait. +* Any other use of the Fast Time Wheel will be stopped during the period of +* this function and then restored. This function also uses the 100 KHz ILO. +* If not enabled, this function will enable the 100 KHz ILO for the period of +* this function. +* +* No changes to the setup of the ILO, Fast Time Wheel, Central Time Wheel or +* Once Per Second interrupt may be made by interrupt routines during the period +* of this function execution. The current operation of the ILO, Central Time +* Wheel and Once Per Second interrupt are maintained during the operation of +* this function provided the reading of the Power Manager Interrupt Status +* Register is only done using the CyPmReadStatus() function. +* +*******************************************************************************/ +void CyIMO_Start(uint8 wait) +{ + uint8 pmFtwCfg2Reg; + uint8 pmFtwCfg0Reg; + uint8 ilo100KhzEnable; + + + CY_LIB_PM_ACT_CFG0_REG |= CY_LIB_PM_ACT_CFG0_IMO_EN; + CY_LIB_PM_STBY_CFG0_REG |= CY_LIB_PM_STBY_CFG0_IMO_EN; + + if(0u != wait) + { + /* Need to turn on the 100KHz ILO if it happens to not already be running.*/ + ilo100KhzEnable = CY_LIB_SLOWCLK_ILO_CR0_REG & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ; + pmFtwCfg0Reg = CY_LIB_PM_TW_CFG0_REG; + pmFtwCfg2Reg = CY_LIB_PM_TW_CFG2_REG; + + CyPmFtwSetInterval(CY_LIB_CLK_IMO_FTW_TIMEOUT); + + while (0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT))) + { + /* Wait for the interrupt status */ + } + + if(0u == ilo100KhzEnable) + { + CyILO_Stop100K(); + } + + CY_LIB_PM_TW_CFG0_REG = pmFtwCfg0Reg; + CY_LIB_PM_TW_CFG2_REG = pmFtwCfg2Reg; + } +} + + +/******************************************************************************* +* Function Name: CyIMO_Stop +******************************************************************************** +* +* Summary: +* Disables the IMO. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyIMO_Stop(void) +{ + CY_LIB_PM_ACT_CFG0_REG &= ((uint8) (~CY_LIB_PM_ACT_CFG0_IMO_EN)); + CY_LIB_PM_STBY_CFG0_REG &= ((uint8) (~CY_LIB_PM_STBY_CFG0_IMO_EN)); +} + + +/******************************************************************************* +* Function Name: CyUSB_PowerOnCheck +******************************************************************************** +* +* Summary: +* Returns the USB power status value. A private function to cy_boot. +* +* Parameters: +* None +* +* Return: +* uint8: one if the USB is enabled, 0 if not enabled. +* +*******************************************************************************/ +static uint8 CyUSB_PowerOnCheck(void) +{ + uint8 poweredOn = 0u; + + /* Check whether device is in Active or AltActiv and if USB is powered on */ + if((((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ACTIVE ) && + (0u != (CY_LIB_PM_ACT_CFG5_REG & CY_ACT_USB_ENABLED ))) || + (((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ALT_ACT) && + (0u != (CY_LIB_PM_STBY_CFG5_REG & CY_ALT_ACT_USB_ENABLED)))) + { + poweredOn = 1u; + } + + return (poweredOn); +} + + +/******************************************************************************* +* Function Name: CyIMO_SetTrimValue +******************************************************************************** +* +* Summary: +* Sets the IMO factory trim values. +* +* Parameters: +* uint8 freq - frequency for which trims must be set +* +* Return: +* None +* +*******************************************************************************/ +static void CyIMO_SetTrimValue(uint8 freq) +{ + uint8 usbPowerOn = CyUSB_PowerOnCheck(); + + /* If USB is powered */ + if(usbPowerOn == 1u) + { + /* Unlock USB write */ + CY_LIB_USB_CR1_REG &= ((uint8)(~CY_LIB_USB_CLK_EN)); + } + switch(freq) + { + case CY_IMO_FREQ_3MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_3MHZ_PTR); + break; + + case CY_IMO_FREQ_6MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_6MHZ_PTR); + break; + + case CY_IMO_FREQ_12MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_12MHZ_PTR); + break; + + case CY_IMO_FREQ_24MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_24MHZ_PTR); + break; + + case CY_IMO_FREQ_48MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_TR1_PTR); + break; + + case CY_IMO_FREQ_62MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_67MHZ_PTR); + break; + +#if(CY_PSOC5) + case CY_IMO_FREQ_74MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_80MHZ_PTR); + break; +#endif /* (CY_PSOC5) */ + + case CY_IMO_FREQ_USB: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_USB_PTR); + + /* If USB is powered */ + if(usbPowerOn == 1u) + { + /* Lock the USB Oscillator */ + CY_LIB_USB_CR1_REG |= CY_LIB_USB_CLK_EN; + } + break; + + default: + CYASSERT(0u != 0u); + break; + } + +} + + +/******************************************************************************* +* Function Name: CyIMO_SetFreq +******************************************************************************** +* +* Summary: +* Sets the frequency of the IMO. Changes may be made while the IMO is running. +* +* Parameters: +* freq: Frequency of IMO operation +* CY_IMO_FREQ_3MHZ to set 3 MHz +* CY_IMO_FREQ_6MHZ to set 6 MHz +* CY_IMO_FREQ_12MHZ to set 12 MHz +* CY_IMO_FREQ_24MHZ to set 24 MHz +* CY_IMO_FREQ_48MHZ to set 48 MHz +* CY_IMO_FREQ_62MHZ to set 62.6 MHz +* CY_IMO_FREQ_74MHZ to set 74.7 MHz (not applicable for PSoC 3) +* CY_IMO_FREQ_USB to set 24 MHz (Trimmed for USB operation) +* +* Return: +* None +* +* Side Effects: +* If as result of this function execution the CPU clock frequency is increased +* then the number of clock cycles the cache will wait before it samples data +* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() +* with appropriate parameter. It can be optionally called if CPU clock +* frequency is lowered in order to improve CPU performance. +* See CyFlash_SetWaitCycles() description for more information. +* +* When the USB setting is chosen, the USB clock locking circuit is enabled. +* Otherwise this circuit is disabled. The USB block must be powered before +* selecting the USB setting. +* +*******************************************************************************/ +void CyIMO_SetFreq(uint8 freq) +{ + uint8 currentFreq; + uint8 nextFreq; + + /*************************************************************************** + * When changing the IMO frequency the Trim values must also be set + * accordingly.This requires reading the current frequency. If the new + * frequency is faster, then set the new trim and then change the frequency, + * otherwise change the frequency and then set the new trim values. + ***************************************************************************/ + + currentFreq = CY_LIB_FASTCLK_IMO_CR_REG & ((uint8)(~CY_LIB_FASTCLK_IMO_CR_RANGE_MASK)); + + /* Check if the requested frequency is USB. */ + nextFreq = (freq == CY_IMO_FREQ_USB) ? CY_IMO_FREQ_24MHZ : freq; + + switch (currentFreq) + { + case 0u: + currentFreq = CY_IMO_FREQ_12MHZ; + break; + + case 1u: + currentFreq = CY_IMO_FREQ_6MHZ; + break; + + case 2u: + currentFreq = CY_IMO_FREQ_24MHZ; + break; + + case 3u: + currentFreq = CY_IMO_FREQ_3MHZ; + break; + + case 4u: + currentFreq = CY_IMO_FREQ_48MHZ; + break; + + case 5u: + currentFreq = CY_IMO_FREQ_62MHZ; + break; + +#if(CY_PSOC5) + case 6u: + currentFreq = CY_IMO_FREQ_74MHZ; + break; +#endif /* (CY_PSOC5) */ + + default: + CYASSERT(0u != 0u); + break; + } + + if (nextFreq >= currentFreq) + { + /* Set the new trim first */ + CyIMO_SetTrimValue(freq); + } + + /* Set the usbclk_on bit when using CY_IMO_FREQ_USB, if not clear it */ + switch(freq) + { + case CY_IMO_FREQ_3MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_3MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; + + case CY_IMO_FREQ_6MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_6MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; + + case CY_IMO_FREQ_12MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_12MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; + + case CY_IMO_FREQ_24MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_24MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; + + case CY_IMO_FREQ_48MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_48MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; + + case CY_IMO_FREQ_62MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_62MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; + +#if(CY_PSOC5) + case CY_IMO_FREQ_74MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_74MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; +#endif /* (CY_PSOC5) */ + + case CY_IMO_FREQ_USB: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_24MHZ_VALUE) | CY_LIB_IMO_USBCLK_ON_SET; + break; + + default: + CYASSERT(0u != 0u); + break; + } + + /* Turn on the IMO Doubler, if switching to CY_IMO_FREQ_USB */ + if (freq == CY_IMO_FREQ_USB) + { + CyIMO_EnableDoubler(); + } + else + { + CyIMO_DisableDoubler(); + } + + if (nextFreq < currentFreq) + { + /* Set the new trim after setting the frequency */ + CyIMO_SetTrimValue(freq); + } +} + + +/******************************************************************************* +* Function Name: CyIMO_SetSource +******************************************************************************** +* +* Summary: +* Sets the source of the clock output from the IMO block. +* +* The output from the IMO is by default the IMO itself. Optionally the MHz +* Crystal or a DSI input can be the source of the IMO output instead. +* +* Parameters: +* source: CY_IMO_SOURCE_DSI to set the DSI as source. +* CY_IMO_SOURCE_XTAL to set the MHz as source. +* CY_IMO_SOURCE_IMO to set the IMO itself. +* +* Return: +* None +* +* Side Effects: +* If as result of this function execution the CPU clock frequency is increased +* then the number of clock cycles the cache will wait before it samples data +* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() +* with appropriate parameter. It can be optionally called if CPU clock +* frequency is lowered in order to improve CPU performance. +* See CyFlash_SetWaitCycles() description for more information. +* +*******************************************************************************/ +void CyIMO_SetSource(uint8 source) +{ + switch(source) + { + case CY_IMO_SOURCE_DSI: + CY_LIB_CLKDIST_CR_REG &= ((uint8)(~CY_LIB_CLKDIST_CR_IMO2X)); + CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_IMO; + break; + + case CY_IMO_SOURCE_XTAL: + CY_LIB_CLKDIST_CR_REG |= CY_LIB_CLKDIST_CR_IMO2X; + CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_IMO; + break; + + case CY_IMO_SOURCE_IMO: + CY_LIB_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_LIB_FASTCLK_IMO_IMO)); + break; + + default: + /* Incorrect source value */ + CYASSERT(0u != 0u); + break; + } +} + + +/******************************************************************************* +* Function Name: CyIMO_EnableDoubler +******************************************************************************** +* +* Summary: +* Enables the IMO doubler. The 2x frequency clock is used to convert a 24 MHz +* input to a 48 MHz output for use by the USB block. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyIMO_EnableDoubler(void) +{ + /* Set the FASTCLK_IMO_CR_PTR regigster's 4th bit */ + CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_DOUBLER; +} + + +/******************************************************************************* +* Function Name: CyIMO_DisableDoubler +******************************************************************************** +* +* Summary: +* Disables the IMO doubler. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyIMO_DisableDoubler(void) +{ + CY_LIB_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_LIB_FASTCLK_IMO_DOUBLER)); +} + + +/******************************************************************************* +* Function Name: CyMasterClk_SetSource +******************************************************************************** +* +* Summary: +* Sets the source of the master clock. +* +* Parameters: +* source: One of the four available Master clock sources. +* CY_MASTER_SOURCE_IMO +* CY_MASTER_SOURCE_PLL +* CY_MASTER_SOURCE_XTAL +* CY_MASTER_SOURCE_DSI +* +* Return: +* None +* +* Side Effects: +* The current source and the new source must both be running and stable before +* calling this function. +* +* If as result of this function execution the CPU clock frequency is increased +* then the number of clock cycles the cache will wait before it samples data +* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() +* with appropriate parameter. It can be optionally called if CPU clock +* frequency is lowered in order to improve CPU performance. +* See CyFlash_SetWaitCycles() description for more information. +* +*******************************************************************************/ +void CyMasterClk_SetSource(uint8 source) +{ + CY_LIB_CLKDIST_MSTR1_REG = (CY_LIB_CLKDIST_MSTR1_REG & MASTER_CLK_SRC_CLEAR) | + (source & ((uint8)(~MASTER_CLK_SRC_CLEAR))); +} + + +/******************************************************************************* +* Function Name: CyMasterClk_SetDivider +******************************************************************************** +* +* Summary: +* Sets the divider value used to generate Master Clock. +* +* Parameters: +* uint8 divider: +* Valid range [0-255]. The clock will be divided by this value + 1. +* For example to divide by 2 this parameter should be set to 1. +* +* Return: +* None +* +* Side Effects: +* If as result of this function execution the CPU clock frequency is increased +* then the number of clock cycles the cache will wait before it samples data +* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() +* with appropriate parameter. It can be optionally called if CPU clock +* frequency is lowered in order to improve CPU performance. +* See CyFlash_SetWaitCycles() description for more information. +* +* When changing the Master or Bus clock divider value from div-by-n to div-by-1 +* the first clock cycle output after the div-by-1 can be up to 4 ns shorter +* than the final/expected div-by-1 period. +* +*******************************************************************************/ +void CyMasterClk_SetDivider(uint8 divider) +{ + CY_LIB_CLKDIST_MSTR0_REG = divider; +} + + +/******************************************************************************* +* Function Name: CyBusClk_Internal_SetDivider +******************************************************************************** +* +* Summary: +* Function used by CyBusClk_SetDivider(). For internal use only. +* +* Parameters: +* divider: Valid range [0-65535]. +* The clock will be divided by this value + 1. +* For example to divide by 2 this parameter should be set to 1. +* +* Return: +* None +* +*******************************************************************************/ +static void CyBusClk_Internal_SetDivider(uint16 divider) +{ + /* Mask bits to enable shadow loads */ + CY_LIB_CLKDIST_AMASK_REG &= CY_LIB_CLKDIST_AMASK_MASK; + CY_LIB_CLKDIST_DMASK_REG = CY_LIB_CLKDIST_DMASK_MASK; + + /* Enable mask bits to enable shadow loads */ + CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_MASK; + + /* Update Shadow Divider Value Register with the new divider */ + CY_LIB_CLKDIST_WRK_LSB_REG = LO8(divider); + CY_LIB_CLKDIST_WRK_MSB_REG = HI8(divider); + + + /*************************************************************************** + * Copy shadow value defined in Shadow Divider Value Register + * (CY_LIB_CLKDIST_WRK_LSB_REG and CY_LIB_CLKDIST_WRK_MSB_REG) to all + * dividers selected in Analog and Digital Clock Mask Registers + * (CY_LIB_CLKDIST_AMASK_REG and CY_LIB_CLKDIST_DMASK_REG). + ***************************************************************************/ + CY_LIB_CLKDIST_LD_REG |= CY_LIB_CLKDIST_LD_LOAD; +} + + +/******************************************************************************* +* Function Name: CyBusClk_SetDivider +******************************************************************************** +* +* Summary: +* Sets the divider value used to generate Bus Clock. +* +* Parameters: +* divider: Valid range [0-65535]. The clock will be divided by this value + 1. +* For example to divide by 2 this parameter should be set to 1. +* +* Return: +* None +* +* Side Effects: +* If as result of this function execution the CPU clock frequency is increased +* then the number of clock cycles the cache will wait before it samples data +* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() +* with appropriate parameter. It can be optionally called if CPU clock +* frequency is lowered in order to improve CPU performance. +* See CyFlash_SetWaitCycles() description for more information. +* +*******************************************************************************/ +void CyBusClk_SetDivider(uint16 divider) +{ + uint8 masterClkDiv; + uint16 busClkDiv; + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + /* Work around to set the bus clock divider value */ + busClkDiv = (uint16)((uint16)CY_LIB_CLKDIST_BCFG_MSB_REG << 8u); + busClkDiv |= CY_LIB_CLKDIST_BCFG_LSB_REG; + + if ((divider == 0u) || (busClkDiv == 0u)) + { + /* Save away the master clock divider value */ + masterClkDiv = CY_LIB_CLKDIST_MSTR0_REG; + + if (masterClkDiv < CY_LIB_CLKDIST_MASTERCLK_DIV) + { + /* Set master clock divider to 7 */ + CyMasterClk_SetDivider(CY_LIB_CLKDIST_MASTERCLK_DIV); + } + + if (divider == 0u) + { + /* Set the SSS bit and the divider register desired value */ + CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_SSS; + CyBusClk_Internal_SetDivider(divider); + } + else + { + CyBusClk_Internal_SetDivider(divider); + CY_LIB_CLKDIST_BCFG2_REG &= ((uint8)(~CY_LIB_CLKDIST_BCFG2_SSS)); + } + + /* Restore the master clock */ + CyMasterClk_SetDivider(masterClkDiv); + } + else + { + CyBusClk_Internal_SetDivider(divider); + } + + CyExitCriticalSection(interruptState); +} + + +#if(CY_PSOC3) + + /******************************************************************************* + * Function Name: CyCpuClk_SetDivider + ******************************************************************************** + * + * Summary: + * Sets the divider value used to generate the CPU Clock. Only applicable for + * PSoC 3 parts. + * + * Parameters: + * divider: Valid range [0-15]. The clock will be divided by this value + 1. + * For example to divide by 2 this parameter should be set to 1. + * + * Return: + * None + * + * Side Effects: + * If as result of this function execution the CPU clock frequency is increased + * then the number of clock cycles the cache will wait before it samples data + * coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() + * with appropriate parameter. It can be optionally called if CPU clock + * frequency is lowered in order to improve CPU performance. + * See CyFlash_SetWaitCycles() description for more information. + * + *******************************************************************************/ + void CyCpuClk_SetDivider(uint8 divider) + { + CY_LIB_CLKDIST_MSTR1_REG = (CY_LIB_CLKDIST_MSTR1_REG & CY_LIB_CLKDIST_MSTR1_DIV_MASK) | + ((uint8)(divider << CY_LIB_CLKDIST_DIV_POSITION)); + } + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Function Name: CyUsbClk_SetSource +******************************************************************************** +* +* Summary: +* Sets the source of the USB clock. +* +* Parameters: +* source: One of the four available USB clock sources +* CY_LIB_USB_CLK_IMO2X - IMO 2x +* CY_LIB_USB_CLK_IMO - IMO +* CY_LIB_USB_CLK_PLL - PLL +* CY_LIB_USB_CLK_DSI - DSI +* +* Return: +* None +* +*******************************************************************************/ +void CyUsbClk_SetSource(uint8 source) +{ + CY_LIB_CLKDIST_UCFG_REG = (CY_LIB_CLKDIST_UCFG_REG & ((uint8)(~CY_LIB_CLKDIST_UCFG_SRC_SEL_MASK))) | + (CY_LIB_CLKDIST_UCFG_SRC_SEL_MASK & source); +} + + +/******************************************************************************* +* Function Name: CyILO_Start1K +******************************************************************************** +* +* Summary: +* Enables the ILO 1 KHz oscillator. +* +* Note The ILO 1 KHz oscillator is always enabled by default, regardless of the +* selection in the Clock Editor. Therefore, this API is only needed if the +* oscillator was turned off manually. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyILO_Start1K(void) +{ + /* Set the bit 1 of ILO RS */ + CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ; +} + + +/******************************************************************************* +* Function Name: CyILO_Stop1K +******************************************************************************** +* +* Summary: +* Disables the ILO 1 KHz oscillator. +* +* Note The ILO 1 KHz oscillator must be enabled if Sleep or Hibernate low power +* mode APIs are expected to be used. For more information, refer to the Power +* Management section of this document. +* +* Parameters: +* None +* +* Return: +* None +* +* Side Effects: +* PSoC5: Stopping the ILO 1 kHz could break the active WDT functionality. +* +*******************************************************************************/ +void CyILO_Stop1K(void) +{ + /* Clear the bit 1 of ILO RS */ + CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ)); +} + + +/******************************************************************************* +* Function Name: CyILO_Start100K +******************************************************************************** +* +* Summary: +* Enables the ILO 100 KHz oscillator. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyILO_Start100K(void) +{ + CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ; +} + + +/******************************************************************************* +* Function Name: CyILO_Stop100K +******************************************************************************** +* +* Summary: +* Disables the ILO 100 KHz oscillator. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyILO_Stop100K(void) +{ + CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ)); +} + + +/******************************************************************************* +* Function Name: CyILO_Enable33K +******************************************************************************** +* +* Summary: +* Enables the ILO 33 KHz divider. +* +* Note that the 33 KHz clock is generated from the 100 KHz oscillator, +* so it must also be running in order to generate the 33 KHz output. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyILO_Enable33K(void) +{ + /* Set the bit 5 of ILO RS */ + CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ; +} + + +/******************************************************************************* +* Function Name: CyILO_Disable33K +******************************************************************************** +* +* Summary: +* Disables the ILO 33 KHz divider. +* +* Note that the 33 KHz clock is generated from the 100 KHz oscillator, but this +* API does not disable the 100 KHz clock. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyILO_Disable33K(void) +{ + CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ)); +} + + +/******************************************************************************* +* Function Name: CyILO_SetSource +******************************************************************************** +* +* Summary: +* Sets the source of the clock output from the ILO block. +* +* Parameters: +* source: One of the three available ILO output sources +* Value Define Source +* 0 CY_ILO_SOURCE_100K ILO 100 KHz +* 1 CY_ILO_SOURCE_33K ILO 33 KHz +* 2 CY_ILO_SOURCE_1K ILO 1 KHz +* +* Return: +* None +* +*******************************************************************************/ +void CyILO_SetSource(uint8 source) +{ + CY_LIB_CLKDIST_CR_REG = (CY_LIB_CLKDIST_CR_REG & CY_ILO_SOURCE_BITS_CLEAR) | + (((uint8) (source << 2u)) & ((uint8)(~CY_ILO_SOURCE_BITS_CLEAR))); +} + + +/******************************************************************************* +* Function Name: CyILO_SetPowerMode +******************************************************************************** +* +* Summary: +* Sets the power mode used by the ILO during power down. Allows for lower power +* down power usage resulting in a slower startup time. +* +* Parameters: +* uint8 mode +* CY_ILO_FAST_START - Faster start-up, internal bias left on when powered down +* CY_ILO_SLOW_START - Slower start-up, internal bias off when powered down +* +* Return: +* Prevous power mode state. +* +*******************************************************************************/ +uint8 CyILO_SetPowerMode(uint8 mode) +{ + uint8 state; + + /* Get current state. */ + state = CY_LIB_SLOWCLK_ILO_CR0_REG; + + /* Set the the oscillator power mode. */ + if(mode != CY_ILO_FAST_START) + { + CY_LIB_SLOWCLK_ILO_CR0_REG = (state | CY_ILO_CONTROL_PD_MODE); + } + else + { + CY_LIB_SLOWCLK_ILO_CR0_REG = (state & ((uint8)(~CY_ILO_CONTROL_PD_MODE))); + } + + /* Return the old mode. */ + return ((state & CY_ILO_CONTROL_PD_MODE) >> CY_ILO_CONTROL_PD_POSITION); +} + + +/******************************************************************************* +* Function Name: CyXTAL_32KHZ_Start +******************************************************************************** +* +* Summary: +* Enables the 32 KHz Crystal Oscillator. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyXTAL_32KHZ_Start(void) +{ + volatile uint16 i; + + CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT; + CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_STARTUP; + CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | + CY_CLK_XTAL32_CFG_LP_DEFAULT; + + #if(CY_PSOC3) + CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_PDBEN; + #endif /* (CY_PSOC3) */ + + /* Enable operation of the 32K Crystal Oscillator */ + CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_EN; + + for (i = 1000u; i > 0u; i--) + { + if(0u != (CyXTAL_32KHZ_ReadStatus() & CY_XTAL32K_ANA_STAT)) + { + /* Ready - switch to the hign power mode */ + (void) CyXTAL_32KHZ_SetPowerMode(0u); + + break; + } + CyDelayUs(1u); + } +} + + +/******************************************************************************* +* Function Name: CyXTAL_32KHZ_Stop +******************************************************************************** +* +* Summary: +* Disables the 32KHz Crystal Oscillator. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyXTAL_32KHZ_Stop(void) +{ + CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT; + CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_POWERDOWN; + CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | + CY_CLK_XTAL32_CFG_LP_DEFAULT; + CY_CLK_XTAL32_CR_REG &= ((uint8)(~(CY_CLK_XTAL32_CR_EN | CY_CLK_XTAL32_CR_LPM))); + + #if(CY_PSOC3) + CY_CLK_XTAL32_CR_REG &= ((uint8)(~CY_CLK_XTAL32_CR_PDBEN)); + #endif /* (CY_PSOC3) */ +} + + +/******************************************************************************* +* Function Name: CyXTAL_32KHZ_ReadStatus +******************************************************************************** +* +* Summary: +* Returns status of the 32 KHz oscillator. +* +* Parameters: +* None +* +* Return: +* Value Define Source +* 20 CY_XTAL32K_ANA_STAT Analog measurement +* 1: Stable +* 0: Not stable +* +*******************************************************************************/ +uint8 CyXTAL_32KHZ_ReadStatus(void) +{ + return(CY_CLK_XTAL32_CR_REG & CY_XTAL32K_ANA_STAT); +} + + +/******************************************************************************* +* Function Name: CyXTAL_32KHZ_SetPowerMode +******************************************************************************** +* +* Summary: +* Sets the power mode for the 32 KHz oscillator used during sleep mode. +* Allows for lower power during sleep when there are fewer sources of noise. +* During active mode the oscillator is always run in high power mode. +* +* Parameters: +* uint8 mode +* 0: High power mode +* 1: Low power mode during sleep +* +* Return: +* Previous power mode. +* +*******************************************************************************/ +uint8 CyXTAL_32KHZ_SetPowerMode(uint8 mode) +{ + uint8 state = (0u != (CY_CLK_XTAL32_CR_REG & CY_CLK_XTAL32_CR_LPM)) ? 1u : 0u; + + CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT; + + if(1u == mode) + { + /* Low power mode during Sleep */ + CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_LOW_POWER; + CyDelayUs(10u); + CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | + CY_CLK_XTAL32_CFG_LP_LOWPOWER; + CyDelayUs(20u); + CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_LPM; + } + else + { + /* High power mode */ + CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_HIGH_POWER; + CyDelayUs(10u); + CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | + CY_CLK_XTAL32_CFG_LP_DEFAULT; + CY_CLK_XTAL32_CR_REG &= ((uint8)(~CY_CLK_XTAL32_CR_LPM)); + } + + return(state); +} + + +/******************************************************************************* +* Function Name: CyXTAL_Start +******************************************************************************** +* +* Summary: +* Enables the megahertz crystal. +* +* PSoC 3: +* Waits until the XERR bit is low (no error) for a millisecond or until the +* number of milliseconds specified by the wait parameter has expired. +* +* Parameters: +* wait: Valid range [0-255]. +* This is the timeout value in milliseconds. +* The appropriate value is crystal specific. +* +* Return: +* CYRET_SUCCESS - Completed successfully +* CYRET_TIMEOUT - Timeout occurred without detecting a low value on XERR. +* +* Side Effects and Restrictions: +* If wait is enabled (non-zero wait). Uses the Fast Timewheel to time the wait. +* Any other use of the Fast Timewheel (FTW) will be stopped during the period +* of this function and then restored. +* +* Uses the 100KHz ILO. If not enabled, this function will enable the 100KHz +* ILO for the period of this function. No changes to the setup of the ILO, +* Fast Timewheel, Central Timewheel or Once Per Second interrupt may be made +* by interrupt routines during the period of this function. +* +* The current operation of the ILO, Central Timewheel and Once Per Second +* interrupt are maintained during the operation of this function provided the +* reading of the Power Manager Interrupt Status Register is only done using the +* CyPmReadStatus() function. +* +*******************************************************************************/ +cystatus CyXTAL_Start(uint8 wait) +{ + cystatus status = CYRET_SUCCESS; + volatile uint8 timeout = wait; + volatile uint8 count; + uint8 iloEnableState; + uint8 pmTwCfg0Tmp; + uint8 pmTwCfg2Tmp; + + + /* Enables the MHz crystal oscillator circuit */ + CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_ENABLE; + + + if(wait > 0u) + { + /* Save 100 KHz ILO, FTW interval, enable and interrupt enable */ + iloEnableState = CY_LIB_SLOWCLK_ILO_CR0_REG; + pmTwCfg0Tmp = CY_LIB_PM_TW_CFG0_REG; + pmTwCfg2Tmp = CY_LIB_PM_TW_CFG2_REG; + + /* Set 250 us interval */ + CyPmFtwSetInterval(CY_CLK_XMHZ_FTW_INTERVAL); + status = CYRET_TIMEOUT; + + + for( ; timeout > 0u; timeout--) + { + /* Read XERR bit to clear it */ + (void) CY_CLK_XMHZ_CSR_REG; + + /* Wait for a millisecond - 4 x 250 us */ + for(count = 4u; count > 0u; count--) + { + while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT))) + { + /* Wait for the FTW interrupt event */ + } + } + + + /******************************************************************* + * High output indicates oscillator failure. + * Only can be used after start-up interval (1 ms) is completed. + *******************************************************************/ + if(0u == (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR)) + { + status = CYRET_SUCCESS; + break; + } + } + + + /* Restore 100 KHz ILO, FTW interval, enable and interrupt enable */ + if(0u == (iloEnableState & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ)) + { + CyILO_Stop100K(); + } + CY_LIB_PM_TW_CFG0_REG = pmTwCfg0Tmp; + CY_LIB_PM_TW_CFG2_REG = pmTwCfg2Tmp; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyXTAL_Stop +******************************************************************************** +* +* Summary: +* Disables the megahertz crystal oscillator. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyXTAL_Stop(void) +{ + /* Disable the the oscillator. */ + FASTCLK_XMHZ_CSR &= ((uint8)(~XMHZ_CONTROL_ENABLE)); +} + + +/******************************************************************************* +* Function Name: CyXTAL_EnableErrStatus +******************************************************************************** +* +* Summary: +* Enables the generation of the XERR status bit for the megahertz crystal. +* This function is not available for PSoC5. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyXTAL_EnableErrStatus(void) +{ + /* If oscillator has insufficient amplitude, XERR bit will be high. */ + CY_CLK_XMHZ_CSR_REG &= ((uint8)(~CY_CLK_XMHZ_CSR_XFB)); +} + + +/******************************************************************************* +* Function Name: CyXTAL_DisableErrStatus +******************************************************************************** +* +* Summary: +* Disables the generation of the XERR status bit for the megahertz crystal. +* This function is not available for PSoC5. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyXTAL_DisableErrStatus(void) +{ + /* If oscillator has insufficient amplitude, XERR bit will be high. */ + CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_XFB; +} + + +/******************************************************************************* +* Function Name: CyXTAL_ReadStatus +******************************************************************************** +* +* Summary: +* Reads the XERR status bit for the megahertz crystal. This status bit is a +* sticky clear on read value. This function is not available for PSoC5. +* +* Parameters: +* None +* +* Return: +* Status +* 0: No error +* 1: Error +* +*******************************************************************************/ +uint8 CyXTAL_ReadStatus(void) +{ + /*************************************************************************** + * High output indicates oscillator failure. Only use this after start-up + * interval is completed. This can be used for status and failure recovery. + ***************************************************************************/ + return((0u != (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR)) ? 1u : 0u); +} + + +/******************************************************************************* +* Function Name: CyXTAL_EnableFaultRecovery +******************************************************************************** +* +* Summary: +* Enables the fault recovery circuit which will switch to the IMO in the case +* of a fault in the megahertz crystal circuit. The crystal must be up and +* running with the XERR bit at 0, before calling this function to prevent +* immediate fault switchover. This function is not available for PSoC5. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyXTAL_EnableFaultRecovery(void) +{ + CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_XPROT; +} + + +/******************************************************************************* +* Function Name: CyXTAL_DisableFaultRecovery +******************************************************************************** +* +* Summary: +* Disables the fault recovery circuit which will switch to the IMO in the case +* of a fault in the megahertz crystal circuit. This function is not available +* for PSoC5. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyXTAL_DisableFaultRecovery(void) +{ + CY_CLK_XMHZ_CSR_REG &= ((uint8)(~CY_CLK_XMHZ_CSR_XPROT)); +} + + +/******************************************************************************* +* Function Name: CyXTAL_SetStartup +******************************************************************************** +* +* Summary: +* Sets the startup settings for the crystal. Logic model outputs a frequency +* (setting + 4) MHz when enabled. +* +* This is artificial as the actual frequency is determined by an attached +* external crystal. +* +* Parameters: +* setting: Valid range [0-31]. +* Value is dependent on the frequency and quality of the crystal being used. +* Refer to the device TRM and datasheet for more information. +* +* Return: +* None +* +*******************************************************************************/ +void CyXTAL_SetStartup(uint8 setting) +{ + CY_CLK_XMHZ_CFG0_REG = (CY_CLK_XMHZ_CFG0_REG & ((uint8)(~CY_CLK_XMHZ_CFG0_XCFG_MASK))) | + (setting & CY_CLK_XMHZ_CFG0_XCFG_MASK); +} + + + +/******************************************************************************* +* Function Name: CyXTAL_SetFbVoltage +******************************************************************************** +* +* Summary: +* Sets the feedback reference voltage to use for the crystal circuit. +* This function is only available for PSoC3 and PSoC 5LP. +* +* Parameters: +* setting: Valid range [0-15]. +* Refer to the device TRM and datasheet for more information. +* +* Return: +* None +* +*******************************************************************************/ +void CyXTAL_SetFbVoltage(uint8 setting) +{ + CY_CLK_XMHZ_CFG1_REG = ((CY_CLK_XMHZ_CFG1_REG & ((uint8)(~CY_CLK_XMHZ_CFG1_VREF_FB_MASK))) | + (setting & CY_CLK_XMHZ_CFG1_VREF_FB_MASK)); +} + + +/******************************************************************************* +* Function Name: CyXTAL_SetWdVoltage +******************************************************************************** +* +* Summary: +* Sets the reference voltage used by the watchdog to detect a failure in the +* crystal circuit. This function is only available for PSoC3 and PSoC 5LP. +* +* Parameters: +* setting: Valid range [0-7]. +* Refer to the device TRM and datasheet for more information. +* +* Return: +* None +* +*******************************************************************************/ +void CyXTAL_SetWdVoltage(uint8 setting) +{ + CY_CLK_XMHZ_CFG1_REG = ((CY_CLK_XMHZ_CFG1_REG & ((uint8)(~CY_CLK_XMHZ_CFG1_VREF_WD_MASK))) | + (((uint8)(setting << 4u)) & CY_CLK_XMHZ_CFG1_VREF_WD_MASK)); +} + + +/******************************************************************************* +* Function Name: CyHalt +******************************************************************************** +* +* Summary: +* Halts the CPU. +* +* Parameters: +* uint8 reason: Value to be used during debugging. +* +* Return: +* None +* +*******************************************************************************/ +void CyHalt(uint8 reason) CYREENTRANT +{ + if(0u != reason) + { + /* To remove unreferenced local variable warning */ + } + + #if defined (__ARMCC_VERSION) + __breakpoint(0x0); + #elif defined(__GNUC__) || defined (__ICCARM__) + __asm(" bkpt 1"); + #elif defined(__C51__) + CYDEV_HALT_CPU; + #endif /* (__ARMCC_VERSION) */ +} + + +/******************************************************************************* +* Function Name: CySoftwareReset +******************************************************************************** +* +* Summary: +* Forces a software reset of the device. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CySoftwareReset(void) +{ + CY_LIB_RESET_CR2_REG |= CY_LIB_RESET_CR2_RESET; +} + + +/******************************************************************************* +* Function Name: CyDelay +******************************************************************************** +* +* Summary: +* Blocks for milliseconds. +* +* Note: +* CyDelay has been implemented with the instruction cache assumed enabled. When +* instruction cache is disabled on PSoC5, CyDelay will be two times larger. For +* example, with instruction cache disabled CyDelay(100) would result in about +* 200 ms delay instead of 100 ms. +* +* Parameters: +* milliseconds: number of milliseconds to delay. +* +* Return: +* None +* +*******************************************************************************/ +void CyDelay(uint32 milliseconds) CYREENTRANT +{ + while (milliseconds > 32768u) + { + /*********************************************************************** + * This loop prevents overflow.At 100MHz, milliseconds * delay_freq_khz + * overflows at about 42 seconds. + ***********************************************************************/ + CyDelayCycles(cydelay_32k_ms); + milliseconds = ((uint32)(milliseconds - 32768u)); + } + + CyDelayCycles(milliseconds * cydelay_freq_khz); +} + + +#if(!CY_PSOC3) + + /* For PSoC3 devices function is defined in CyBootAsmKeil.a51 file */ + + /******************************************************************************* + * Function Name: CyDelayUs + ******************************************************************************** + * + * Summary: + * Blocks for microseconds. + * + * Note: + * CyDelay has been implemented with the instruction cache assumed enabled. + * When instruction cache is disabled on PSoC5, CyDelayUs will be two times + * larger. Ex: With instruction cache disabled CyDelayUs(100) would result + * in about 200us delay instead of 100us. + * + * Parameters: + * uint16 microseconds: number of microseconds to delay. + * + * Return: + * None + * + * Side Effects: + * CyDelayUS has been implemented with the instruction cache assumed enabled. + * When instruction cache is disabled on PSoC 5, CyDelayUs will be two times + * larger. For example, with instruction cache disabled CyDelayUs(100) would + * result in about 200 us delay instead of 100 us. + * + * If the bus clock frequency is a small non-integer number, the actual delay + * can be up to twice as long as the nominal value. The actual delay cannot be + * shorter than the nominal one. + *******************************************************************************/ + void CyDelayUs(uint16 microseconds) CYREENTRANT + { + CyDelayCycles((uint32)microseconds * cydelay_freq_mhz); + } + +#endif /* (!CY_PSOC3) */ + + +/******************************************************************************* +* Function Name: CyDelayFreq +******************************************************************************** +* +* Summary: +* Sets clock frequency for CyDelay. +* +* Parameters: +* freq: Frequency of bus clock in Hertz. +* +* Return: +* None +* +*******************************************************************************/ +void CyDelayFreq(uint32 freq) CYREENTRANT +{ + if (freq != 0u) + { + cydelay_freq_hz = freq; + } + else + { + cydelay_freq_hz = BCLK__BUS_CLK__HZ; + } + + cydelay_freq_mhz = (uint8)((cydelay_freq_hz + 999999u) / 1000000u); + cydelay_freq_khz = (cydelay_freq_hz + 999u) / 1000u; + cydelay_32k_ms = 32768u * cydelay_freq_khz; +} + + +/******************************************************************************* +* Function Name: CyWdtStart +******************************************************************************** +* +* Summary: +* Enables the watchdog timer. +* +* The timer is configured for the specified count interval, the central +* timewheel is cleared, the setting for low power mode is configured and the +* watchdog timer is enabled. +* +* Once enabled the watchdog cannot be disabled. The watchdog counts each time +* the Central Time Wheel (CTW) reaches the period specified. The watchdog must +* be cleared using the CyWdtClear() function before three ticks of the watchdog +* timer occur. The CTW is free running, so this will occur after between 2 and +* 3 timer periods elapse. +* +* PSoC5: The watchdog timer should not be used during sleep modes. Since the +* WDT cannot be disabled after it is enabled, the WDT timeout period can be +* set to be greater than the sleep wakeup period, then feed the dog on each +* wakeup from Sleep. +* +* Parameters: +* ticks: One of the four available timer periods. Once WDT enabled, the + interval cannot be changed. +* CYWDT_2_TICKS - 4 - 6 ms +* CYWDT_16_TICKS - 32 - 48 ms +* CYWDT_128_TICKS - 256 - 384 ms +* CYWDT_1024_TICKS - 2.048 - 3.072 s +* +* lpMode: Low power mode configuration. This parameter is ignored for PSoC 5. +* The WDT always acts as if CYWDT_LPMODE_NOCHANGE is passed. +* +* CYWDT_LPMODE_NOCHANGE - No Change +* CYWDT_LPMODE_MAXINTER - Switch to longest timer mode during low power +* mode +* CYWDT_LPMODE_DISABLED - Disable WDT during low power mode +* +* Return: +* None +* +* Side Effects: +* PSoC5: The ILO 1 KHz must be enabled for proper WDT operation. Stopping the +* ILO 1 kHz could break the active WDT functionality. +* +*******************************************************************************/ +void CyWdtStart(uint8 ticks, uint8 lpMode) +{ + /* Set WDT interval */ + CY_WDT_CFG_REG = (CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_INTERVAL_MASK))) | (ticks & CY_WDT_CFG_INTERVAL_MASK); + + /* Reset CTW to ensure that first watchdog period is full */ + CY_WDT_CFG_REG |= CY_WDT_CFG_CTW_RESET; + CY_WDT_CFG_REG &= ((uint8)(~CY_WDT_CFG_CTW_RESET)); + + /* Setting the low power mode */ + CY_WDT_CFG_REG = (((uint8)(lpMode << CY_WDT_CFG_LPMODE_SHIFT)) & CY_WDT_CFG_LPMODE_MASK) | + (CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_LPMODE_MASK))); + + /* Enables the watchdog reset */ + CY_WDT_CFG_REG |= CY_WDT_CFG_WDR_EN; +} + + +/******************************************************************************* +* Function Name: CyWdtClear +******************************************************************************** +* +* Summary: +* Clears (feeds) the watchdog timer. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyWdtClear(void) +{ + CY_WDT_CR_REG = CY_WDT_CR_FEED; +} + + + +/******************************************************************************* +* Function Name: CyVdLvDigitEnable +******************************************************************************** +* +* Summary: +* Enables the digital low voltage monitors to generate interrupt on Vddd +* archives specified threshold and optionally resets device. +* +* Parameters: +* reset: Option to reset device at a specified Vddd threshold: +* 0 - Device is not reset. +* 1 - Device is reset. +* +* threshold: Sets the trip level for the voltage monitor. +* Values from 1.70 V to 5.45 V are accepted with the approximately 250 mV +* interval. +* +* Return: +* None +* +*******************************************************************************/ +void CyVdLvDigitEnable(uint8 reset, uint8 threshold) +{ + *CY_INT_CLEAR_PTR = 0x01u; + + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN)); + + CY_VD_LVI_TRIP_REG = (threshold & CY_VD_LVI_TRIP_LVID_MASK) | + (CY_VD_LVI_TRIP_REG & ((uint8)(~CY_VD_LVI_TRIP_LVID_MASK))); + CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVID_EN; + + /* Timeout to eliminate glitches on the LVI/HVI when enabling */ + CyDelayUs(1u); + + (void)CY_VD_PERSISTENT_STATUS_REG; + + if(0u != reset) + { + CY_VD_PRES_CONTROL_REG |= CY_VD_PRESD_EN; + } + else + { + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN)); + } + + *CY_INT_CLR_PEND_PTR = 0x01u; + *CY_INT_ENABLE_PTR = 0x01u; +} + + +/******************************************************************************* +* Function Name: CyVdLvAnalogEnable +******************************************************************************** +* +* Summary: +* Enables the analog low voltage monitors to generate interrupt on Vdda +* archives specified threshold and optionally resets device. +* +* Parameters: +* reset: Option to reset device at a specified Vdda threshold: +* 0 - Device is not reset. +* 1 - Device is reset. +* +* threshold: Sets the trip level for the voltage monitor. +* Values from 1.70 V to 5.45 V are accepted with the approximately 250 mV +* interval. +* +* Return: +* None +* +*******************************************************************************/ +void CyVdLvAnalogEnable(uint8 reset, uint8 threshold) +{ + *CY_INT_CLEAR_PTR = 0x01u; + + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); + + CY_VD_LVI_TRIP_REG = ((uint8)(threshold << 4u)) | (CY_VD_LVI_TRIP_REG & 0x0Fu); + CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVIA_EN; + + /* Timeout to eliminate glitches on the LVI/HVI when enabling */ + CyDelayUs(1u); + + (void)CY_VD_PERSISTENT_STATUS_REG; + + if(0u != reset) + { + CY_VD_PRES_CONTROL_REG |= CY_VD_PRESA_EN; + } + else + { + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); + } + + *CY_INT_CLR_PEND_PTR = 0x01u; + *CY_INT_ENABLE_PTR = 0x01u; +} + + +/******************************************************************************* +* Function Name: CyVdLvDigitDisable +******************************************************************************** +* +* Summary: +* Disables the digital low voltage monitor (interrupt and device reset are +* disabled). +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyVdLvDigitDisable(void) +{ + CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_LVID_EN)); + + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN)); + + while(0u != (CY_VD_PERSISTENT_STATUS_REG & 0x07u)) + { + + } +} + + +/******************************************************************************* +* Function Name: CyVdLvAnalogDisable +******************************************************************************** +* +* Summary: +* Disables the analog low voltage monitor (interrupt and device reset are +* disabled). +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyVdLvAnalogDisable(void) +{ + CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_LVIA_EN)); + + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); + + while(0u != (CY_VD_PERSISTENT_STATUS_REG & 0x07u)) + { + + } +} + + +/******************************************************************************* +* Function Name: CyVdHvAnalogEnable +******************************************************************************** +* +* Summary: +* Enables the analog high voltage monitors to generate interrupt on +* Vdda archives 5.75 V threshold and optionally resets device. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyVdHvAnalogEnable(void) +{ + *CY_INT_CLEAR_PTR = 0x01u; + + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); + + CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_HVIA_EN; + + /* Timeout to eliminate glitches on the LVI/HVI when enabling */ + CyDelayUs(1u); + + (void) CY_VD_PERSISTENT_STATUS_REG; + + *CY_INT_CLR_PEND_PTR = 0x01u; + *CY_INT_ENABLE_PTR = 0x01u; +} + + +/******************************************************************************* +* Function Name: CyVdHvAnalogDisable +******************************************************************************** +* +* Summary: +* Disables the analog low voltage monitor +* (interrupt and device reset are disabled). +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyVdHvAnalogDisable(void) +{ + CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_HVIA_EN)); +} + + +/******************************************************************************* +* Function Name: CyVdStickyStatus +******************************************************************************** +* +* Summary: +* Manages the Reset and Voltage Detection Status Register 0. +* This register has the interrupt status for the HVIA, LVID and LVIA. +* This hardware register clears on read. +* +* Parameters: +* mask: Bits in the shadow register to clear. +* Define Definition +* CY_VD_LVID Persistent status of digital LVI. +* CY_VD_LVIA Persistent status of analog LVI. +* CY_VD_HVIA Persistent status of analog HVI. +* +* Return: +* Status. Same enumerated bit values as used for the mask parameter. +* +*******************************************************************************/ +uint8 CyVdStickyStatus(uint8 mask) +{ + uint8 status; + + status = CY_VD_PERSISTENT_STATUS_REG; + CY_VD_PERSISTENT_STATUS_REG &= ((uint8)(~mask)); + + return(status); +} + + +/******************************************************************************* +* Function Name: CyVdRealTimeStatus +******************************************************************************** +* +* Summary: +* Returns the real time voltage detection status. +* +* Parameters: +* None +* +* Return: +* Status: +* Define Definition +* CY_VD_LVID Persistent status of digital LVI. +* CY_VD_LVIA Persistent status of analog LVI. +* CY_VD_HVIA Persistent status of analog HVI. +* +*******************************************************************************/ +uint8 CyVdRealTimeStatus(void) +{ + uint8 interruptState; + uint8 vdFlagsState; + + interruptState = CyEnterCriticalSection(); + vdFlagsState = CY_VD_RT_STATUS_REG; + CyExitCriticalSection(interruptState); + + return(vdFlagsState); +} + + +/******************************************************************************* +* Function Name: CyDisableInts +******************************************************************************** +* +* Summary: +* Disables the interrupt enable for each interrupt. +* +* Parameters: +* None +* +* Return: +* 32 bit mask of previously enabled interrupts. +* +*******************************************************************************/ +uint32 CyDisableInts(void) +{ + uint32 intState; + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + #if(CY_PSOC3) + + /* Get the current interrupt state. */ + intState = ((uint32) CY_GET_REG8(CY_INT_CLR_EN0_PTR)); + intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN1_PTR)) << 8u)); + intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN2_PTR)) << 16u)); + intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN3_PTR)) << 24u)); + + + /* Disable all of the interrupts. */ + CY_SET_REG8(CY_INT_CLR_EN0_PTR, 0xFFu); + CY_SET_REG8(CY_INT_CLR_EN1_PTR, 0xFFu); + CY_SET_REG8(CY_INT_CLR_EN2_PTR, 0xFFu); + CY_SET_REG8(CY_INT_CLR_EN3_PTR, 0xFFu); + + #else + + /* Get the current interrupt state. */ + intState = CY_GET_REG32(CY_INT_CLEAR_PTR); + + /* Disable all of the interrupts. */ + CY_SET_REG32(CY_INT_CLEAR_PTR, 0xFFFFFFFFu); + + #endif /* (CY_PSOC3) */ + + CyExitCriticalSection(interruptState); + + return (intState); +} + + +/******************************************************************************* +* Function Name: CyEnableInts +******************************************************************************** +* +* Summary: +* Enables interrupts to a given state. +* +* Parameters: +* uint32 mask: 32 bit mask of interrupts to enable. +* +* Return: +* None +* +*******************************************************************************/ +void CyEnableInts(uint32 mask) +{ + + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + #if(CY_PSOC3) + + /* Set interrupts as enabled. */ + CY_SET_REG8(CY_INT_SET_EN3_PTR, ((uint8) (mask >> 24u))); + CY_SET_REG8(CY_INT_SET_EN2_PTR, ((uint8) (mask >> 16u))); + CY_SET_REG8(CY_INT_SET_EN1_PTR, ((uint8) (mask >> 8u ))); + CY_SET_REG8(CY_INT_SET_EN0_PTR, ((uint8) (mask ))); + + #else + + CY_SET_REG32(CY_INT_ENABLE_PTR, mask); + + #endif /* (CY_PSOC3) */ + + CyExitCriticalSection(interruptState); + +} + +#if(CY_PSOC5) + + /******************************************************************************* + * Function Name: CyFlushCache + ******************************************************************************** + * Summary: + * Flushes the PSoC 5/5LP cache by invalidating all entries. + * + * Parameters: + * None + * + * Return: + * None + * + *******************************************************************************/ + void CyFlushCache(void) + { + uint8 interruptState; + + /* Save current global interrupt enable and disable it */ + interruptState = CyEnterCriticalSection(); + + /* Fill instruction prefectch unit to insure data integrity */ + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + + /* All entries in the cache are invalidated on the next clock cycle. */ + CY_CACHE_CONTROL_REG |= CY_CACHE_CONTROL_FLUSH; + + + /*********************************************************************** + * The prefetch unit could/would be filled with the instructions that + * succeed the flush. Since a flush is desired then theoretically those + * instructions might be considered stale/invalid. + ***********************************************************************/ + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CyIntSetSysVector + ******************************************************************************** + * Summary: + * Sets the interrupt vector of the specified system interrupt number. System + * interrupts are present only for the ARM platform. These interrupts are for + * SysTick, PendSV and others. + * + * Parameters: + * number: Interrupt number, valid range [0-15]. + address: Pointer to an interrupt service routine. + * + * Return: + * The old ISR vector at this location. + * + *******************************************************************************/ + cyisraddress CyIntSetSysVector(uint8 number, cyisraddress address) + { + cyisraddress oldIsr; + cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE; + + CYASSERT(number <= CY_INT_SYS_NUMBER_MAX); + + /* Save old Interrupt service routine. */ + oldIsr = ramVectorTable[number & CY_INT_SYS_NUMBER_MASK]; + + /* Set new Interrupt service routine. */ + ramVectorTable[number & CY_INT_SYS_NUMBER_MASK] = address; + + return (oldIsr); + } + + + /******************************************************************************* + * Function Name: CyIntGetSysVector + ******************************************************************************** + * + * Summary: + * Gets the interrupt vector of the specified system interrupt number. System + * interrupts are present only for the ARM platform. These interrupts are for + * SysTick, PendSV and others. + * + * Parameters: + * number: The interrupt number, valid range [0-15]. + * + * Return: + * Address of the ISR in the interrupt vector table. + * + *******************************************************************************/ + cyisraddress CyIntGetSysVector(uint8 number) + { + cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE; + CYASSERT(number <= CY_INT_SYS_NUMBER_MAX); + + return ramVectorTable[number & CY_INT_SYS_NUMBER_MASK]; + } + + + /******************************************************************************* + * Function Name: CyIntSetVector + ******************************************************************************** + * + * Summary: + * Sets the interrupt vector of the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number + * address: Pointer to an interrupt service routine + * + * Return: + * Previous interrupt vector value. + * + *******************************************************************************/ + cyisraddress CyIntSetVector(uint8 number, cyisraddress address) + { + cyisraddress oldIsr; + cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + /* Save old Interrupt service routine. */ + oldIsr = ramVectorTable[CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK)]; + + /* Set new Interrupt service routine. */ + ramVectorTable[CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK)] = address; + + return (oldIsr); + } + + + /******************************************************************************* + * Function Name: CyIntGetVector + ******************************************************************************** + * + * Summary: + * Gets the interrupt vector of the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number + * + * Return: + * Address of the ISR in the interrupt vector table. + * + *******************************************************************************/ + cyisraddress CyIntGetVector(uint8 number) + { + cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE; + CYASSERT(number <= CY_INT_NUMBER_MAX); + + return (ramVectorTable[CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK)]); + } + + + /******************************************************************************* + * Function Name: CyIntSetPriority + ******************************************************************************** + * + * Summary: + * Sets the Priority of the Interrupt. + * + * Parameters: + * priority: Priority of the interrupt. 0 - 7, 0 being the highest. + * number: The number of the interrupt, 0 - 31. + * + * Return: + * None + * + *******************************************************************************/ + void CyIntSetPriority(uint8 number, uint8 priority) + { + CYASSERT(priority <= CY_INT_PRIORITY_MAX); + CYASSERT(number <= CY_INT_NUMBER_MAX); + CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] = (priority & CY_INT_PRIORITY_MASK)<< 5; + } + + + /******************************************************************************* + * Function Name: CyIntGetPriority + ******************************************************************************** + * + * Summary: + * Gets the Priority of the Interrupt. + * + * Parameters: + * number: The number of the interrupt, 0 - 31. + * + * Return: + * Priority of the interrupt. 0 - 7, 0 being the highest. + * + *******************************************************************************/ + uint8 CyIntGetPriority(uint8 number) + { + uint8 priority; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + priority = CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] >> 5; + + return (priority); + } + + + /******************************************************************************* + * Function Name: CyIntGetState + ******************************************************************************** + * + * Summary: + * Gets the enable state of the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number. + * + * Return: + * Enable status: 1 if enabled, 0 if disabled + * + *******************************************************************************/ + uint8 CyIntGetState(uint8 number) + { + reg32 * stateReg; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + /* Get a pointer to the Interrupt enable register. */ + stateReg = CY_INT_ENABLE_PTR; + + /* Get the state of the interrupt. */ + return (0u != (*stateReg & (((uint32) 1u) << (0x1Fu & number)))) ? ((uint8)(1u)) : ((uint8)(0u)); + } + + +#else /* PSoC3 */ + + + /******************************************************************************* + * Function Name: CyIntSetVector + ******************************************************************************** + * + * Summary: + * Sets the interrupt vector of the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number + * address: Pointer to an interrupt service routine + * + * Return: + * Previous interrupt vector value. + * + *******************************************************************************/ + cyisraddress CyIntSetVector(uint8 number, cyisraddress address) + { + cyisraddress oldIsr; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + /* Save old Interrupt service routine. */ + oldIsr = (cyisraddress) \ + CY_GET_REG16(&CY_INT_VECT_TABLE[number & CY_INT_NUMBER_MASK]); + + /* Set new Interrupt service routine. */ + CY_SET_REG16(&CY_INT_VECT_TABLE[number], (uint16) address); + + return (oldIsr); + } + + + /******************************************************************************* + * Function Name: CyIntGetVector + ******************************************************************************** + * + * Summary: + * Gets the interrupt vector of the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number + * + * Return: + * Address of the ISR in the interrupt vector table. + * + *******************************************************************************/ + cyisraddress CyIntGetVector(uint8 number) + { + CYASSERT(number <= CY_INT_NUMBER_MAX); + + return ((cyisraddress) \ + CY_GET_REG16(&CY_INT_VECT_TABLE[number & CY_INT_NUMBER_MASK])); + } + + + /******************************************************************************* + * Function Name: CyIntSetPriority + ******************************************************************************** + * + * Summary: + * Sets the Priority of the Interrupt. + * + * Parameters: + * priority: Priority of the interrupt. 0 - 7, 0 being the highest. + * number: The number of the interrupt, 0 - 31. + * + * Return: + * None + * + *******************************************************************************/ + void CyIntSetPriority(uint8 number, uint8 priority) + { + CYASSERT(priority <= CY_INT_PRIORITY_MAX); + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] = + (priority & CY_INT_PRIORITY_MASK) << 5; + } + + + /******************************************************************************* + * Function Name: CyIntGetPriority + ******************************************************************************** + * + * Summary: + * Gets the Priority of the Interrupt. + * + * Parameters: + * number: The number of the interrupt, 0 - 31. + * + * Return: + * Priority of the interrupt. 0 - 7, 0 being the highest. + * + *******************************************************************************/ + uint8 CyIntGetPriority(uint8 number) + { + uint8 priority; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + priority = CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] >> 5; + + return (priority); + } + + + /******************************************************************************* + * Function Name: CyIntGetState + ******************************************************************************** + * + * Summary: + * Gets the enable state of the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number. + * + * Return: + * Enable status: 1 if enabled, 0 if disabled + * + *******************************************************************************/ + uint8 CyIntGetState(uint8 number) + { + reg8 * stateReg; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + /* Get a pointer to the Interrupt enable register. */ + stateReg = CY_INT_ENABLE_PTR + ((number & CY_INT_NUMBER_MASK) >> 3u); + + /* Get the state of the interrupt. */ + return ((0u != (*stateReg & ((uint8)(1u << (0x07u & number))))) ? ((uint8)(1u)) : ((uint8)(0u))); + } + + +#endif /* (CY_PSOC5) */ + + +#if(CYDEV_VARIABLE_VDDA == 1) + + /******************************************************************************* + * Function Name: CySetScPumps + ******************************************************************************** + * + * Summary: + * If 1 is passed as a parameter: + * - if any of the SC blocks are used - enable pumps for the SC blocks and + * start boost clock. + * - For the each enabled SC block set boost clock index and enable boost + * clock. + * + * If non-1 value is passed as a parameter: + * - If all SC blocks are not used - disable pumps for the SC blocks and + * stop boost clock. + * - For the each enabled SC block clear boost clock index and disable boost + * clock. + * + * The global variable CyScPumpEnabled is updated to be equal to passed + * parameter. + * + * Parameters: + * uint8 enable: Enable/disable SC pumps and boost clock for enabled SC block. + * 1 - Enable + * 0 - Disable + * + * Return: + * None + * + *******************************************************************************/ + void CySetScPumps(uint8 enable) + { + if(1u == enable) + { + /* The SC pumps should be enabled */ + CyScPumpEnabled = 1u; + /* Enable pumps if any of SC blocks are used */ + if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAPS_MASK)) + { + CY_LIB_SC_MISC_REG |= CY_LIB_SC_MISC_PUMP_FORCE; + CyScBoostClk_Start(); + } + /* Set positive pump for each enabled SC block: set clock index and enable it */ + if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP0_EN)) + { + CY_LIB_SC0_BST_REG = (CY_LIB_SC0_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX; + CY_LIB_SC0_BST_REG |= CY_LIB_SC_BST_CLK_EN; + } + if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP1_EN)) + { + CY_LIB_SC1_BST_REG = (CY_LIB_SC1_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX; + CY_LIB_SC1_BST_REG |= CY_LIB_SC_BST_CLK_EN; + } + if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP2_EN)) + { + CY_LIB_SC2_BST_REG = (CY_LIB_SC2_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX; + CY_LIB_SC2_BST_REG |= CY_LIB_SC_BST_CLK_EN; + } + if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP3_EN)) + { + CY_LIB_SC3_BST_REG = (CY_LIB_SC3_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX; + CY_LIB_SC3_BST_REG |= CY_LIB_SC_BST_CLK_EN; + } + } + else + { + /* The SC pumps should be disabled */ + CyScPumpEnabled = 0u; + /* Disable pumps for all SC blocks and stop boost clock */ + CY_LIB_SC_MISC_REG &= ((uint8)(~CY_LIB_SC_MISC_PUMP_FORCE)); + CyScBoostClk_Stop(); + /* Disable boost clock and clear clock index for each SC block */ + CY_LIB_SC0_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN)); + CY_LIB_SC0_BST_REG = CY_LIB_SC0_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK; + CY_LIB_SC1_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN)); + CY_LIB_SC1_BST_REG = CY_LIB_SC1_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK; + CY_LIB_SC2_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN)); + CY_LIB_SC2_BST_REG = CY_LIB_SC2_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK; + CY_LIB_SC3_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN)); + CY_LIB_SC3_BST_REG = CY_LIB_SC3_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK; + } + } + +#endif /* (CYDEV_VARIABLE_VDDA == 1) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyLib.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyLib.h new file mode 100755 index 00000000..3bc638c7 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CyLib.h @@ -0,0 +1,1281 @@ +/******************************************************************************* +* File Name: CyLib.h +* Version 4.0 +* +* Description: +* Provides the function definitions for the system, clocking, interrupts and +* watchdog timer API. +* +* Note: +* Documentation of the API's in this file is located in the System Reference +* Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYLIB_H) +#define CY_BOOT_CYLIB_H + +#include +#include +#include + +#include "cytypes.h" +#include "cyfitter.h" +#include "cydevice_trm.h" +#include "cyPm.h" + +#if(CY_PSOC3) + #include +#endif /* (CY_PSOC3) */ + + +#if(CYDEV_VARIABLE_VDDA == 1) + + #include "CyScBoostClk.h" + +#endif /* (CYDEV_VARIABLE_VDDA == 1) */ + + +/* Global variable with preserved reset status */ +extern uint8 CYXDATA CyResetStatus; + + +/* Variable Vdda */ +#if(CYDEV_VARIABLE_VDDA == 1) + + extern uint8 CyScPumpEnabled; + +#endif /* (CYDEV_VARIABLE_VDDA == 1) */ + + +/* Do not use these definitions directly in your application */ +extern uint32 cydelay_freq_hz; +extern uint32 cydelay_freq_khz; +extern uint8 cydelay_freq_mhz; +extern uint32 cydelay_32k_ms; + + +/*************************************** +* Function Prototypes +***************************************/ +cystatus CyPLL_OUT_Start(uint8 wait) ; +void CyPLL_OUT_Stop(void) ; +void CyPLL_OUT_SetPQ(uint8 pDiv, uint8 qDiv, uint8 current) ; +void CyPLL_OUT_SetSource(uint8 source) ; + +void CyIMO_Start(uint8 wait) ; +void CyIMO_Stop(void) ; +void CyIMO_SetFreq(uint8 freq) ; +void CyIMO_SetSource(uint8 source) ; +void CyIMO_EnableDoubler(void) ; +void CyIMO_DisableDoubler(void) ; + +void CyMasterClk_SetSource(uint8 source) ; +void CyMasterClk_SetDivider(uint8 divider) ; +void CyBusClk_SetDivider(uint16 divider) ; + +#if(CY_PSOC3) + void CyCpuClk_SetDivider(uint8 divider) ; +#endif /* (CY_PSOC3) */ + +void CyUsbClk_SetSource(uint8 source) ; + +void CyILO_Start1K(void) ; +void CyILO_Stop1K(void) ; +void CyILO_Start100K(void) ; +void CyILO_Stop100K(void) ; +void CyILO_Enable33K(void) ; +void CyILO_Disable33K(void) ; +void CyILO_SetSource(uint8 source) ; +uint8 CyILO_SetPowerMode(uint8 mode) ; + +uint8 CyXTAL_32KHZ_ReadStatus(void) ; +uint8 CyXTAL_32KHZ_SetPowerMode(uint8 mode) ; +void CyXTAL_32KHZ_Start(void) ; +void CyXTAL_32KHZ_Stop(void) ; + +cystatus CyXTAL_Start(uint8 wait) ; +void CyXTAL_Stop(void) ; +void CyXTAL_SetStartup(uint8 setting) ; + +void CyXTAL_EnableErrStatus(void) ; +void CyXTAL_DisableErrStatus(void) ; +uint8 CyXTAL_ReadStatus(void) ; +void CyXTAL_EnableFaultRecovery(void) ; +void CyXTAL_DisableFaultRecovery(void) ; + +void CyXTAL_SetFbVoltage(uint8 setting) ; +void CyXTAL_SetWdVoltage(uint8 setting) ; + +void CyWdtStart(uint8 ticks, uint8 lpMode) ; +void CyWdtClear(void) ; + +/* System Function Prototypes */ +void CyDelay(uint32 milliseconds) CYREENTRANT; +void CyDelayUs(uint16 microseconds); +void CyDelayFreq(uint32 freq) CYREENTRANT; +void CyDelayCycles(uint32 cycles); + +void CySoftwareReset(void) ; + +uint8 CyEnterCriticalSection(void); +void CyExitCriticalSection(uint8 savedIntrStatus); +void CyHalt(uint8 reason) CYREENTRANT; + + +/* Interrupt Function Prototypes */ +#if(CY_PSOC5) + cyisraddress CyIntSetSysVector(uint8 number, cyisraddress address) ; + cyisraddress CyIntGetSysVector(uint8 number) ; +#endif /* (CY_PSOC5) */ + +cyisraddress CyIntSetVector(uint8 number, cyisraddress address) ; +cyisraddress CyIntGetVector(uint8 number) ; + +void CyIntSetPriority(uint8 number, uint8 priority) ; +uint8 CyIntGetPriority(uint8 number) ; + +uint8 CyIntGetState(uint8 number) ; + +uint32 CyDisableInts(void) ; +void CyEnableInts(uint32 mask) ; + + +#if(CY_PSOC5) + void CyFlushCache(void); +#endif /* (CY_PSOC5) */ + + +/* Voltage Detection Function Prototypes */ +void CyVdLvDigitEnable(uint8 reset, uint8 threshold) ; +void CyVdLvAnalogEnable(uint8 reset, uint8 threshold) ; +void CyVdLvDigitDisable(void) ; +void CyVdLvAnalogDisable(void) ; +void CyVdHvAnalogEnable(void) ; +void CyVdHvAnalogDisable(void) ; +uint8 CyVdStickyStatus(uint8 mask) ; +uint8 CyVdRealTimeStatus(void) ; + +void CySetScPumps(uint8 enable) ; + + +/*************************************** +* API Constants +***************************************/ + + +/******************************************************************************* +* PLL API Constants +*******************************************************************************/ +#define CY_CLK_PLL_ENABLE (0x01u) +#define CY_CLK_PLL_LOCK_STATUS (0x01u) + +#define CY_CLK_PLL_FTW_INTERVAL (24u) + +#define CY_CLK_PLL_MAX_Q_VALUE (16u) +#define CY_CLK_PLL_MIN_Q_VALUE (1u) +#define CY_CLK_PLL_MIN_P_VALUE (8u) +#define CY_CLK_PLL_MIN_CUR_VALUE (1u) +#define CY_CLK_PLL_MAX_CUR_VALUE (7u) + +#define CY_CLK_PLL_CURRENT_POSITION (4u) +#define CY_CLK_PLL_CURRENT_MASK (0x8Fu) + + +/******************************************************************************* +* External 32kHz Crystal Oscillator API Constants +*******************************************************************************/ +#define CY_XTAL32K_ANA_STAT (0x20u) + +#define CY_CLK_XTAL32_CR_LPM (0x02u) +#define CY_CLK_XTAL32_CR_EN (0x01u) +#if(CY_PSOC3) + #define CY_CLK_XTAL32_CR_PDBEN (0x04u) +#endif /* (CY_PSOC3) */ + +#define CY_CLK_XTAL32_TR_MASK (0x07u) +#define CY_CLK_XTAL32_TR_STARTUP (0x03u) +#define CY_CLK_XTAL32_TR_HIGH_POWER (0x06u) +#define CY_CLK_XTAL32_TR_LOW_POWER (0x01u) +#define CY_CLK_XTAL32_TR_POWERDOWN (0x00u) + +#define CY_CLK_XTAL32_TST_DEFAULT (0xF3u) + +#define CY_CLK_XTAL32_CFG_LP_DEFAULT (0x04u) +#define CY_CLK_XTAL32_CFG_LP_LOWPOWER (0x08u) +#define CY_CLK_XTAL32_CFG_LP_MASK (0x0Cu) + +#define CY_CLK_XTAL32_CFG_LP_ALLOW (0x80u) + + +/******************************************************************************* +* External MHz Crystal Oscillator API Constants +*******************************************************************************/ +#define CY_CLK_XMHZ_FTW_INTERVAL (24u) +#define CY_CLK_XMHZ_MIN_TIMEOUT (130u) + +#define CY_CLK_XMHZ_CSR_ENABLE (0x01u) +#define CY_CLK_XMHZ_CSR_XERR (0x80u) +#define CY_CLK_XMHZ_CSR_XFB (0x04u) +#define CY_CLK_XMHZ_CSR_XPROT (0x40u) + +#define CY_CLK_XMHZ_CFG0_XCFG_MASK (0x1Fu) +#define CY_CLK_XMHZ_CFG1_VREF_FB_MASK (0x0Fu) +#define CY_CLK_XMHZ_CFG1_VREF_WD_MASK (0x70u) + + +/******************************************************************************* +* Watchdog Timer API Constants +*******************************************************************************/ +#define CYWDT_2_TICKS (0x0u) /* 4 - 6 ms */ +#define CYWDT_16_TICKS (0x1u) /* 32 - 48 ms */ +#define CYWDT_128_TICKS (0x2u) /* 256 - 384 ms */ +#define CYWDT_1024_TICKS (0x3u) /* 2048 - 3072 ms */ + +#define CYWDT_LPMODE_NOCHANGE (0x00u) +#define CYWDT_LPMODE_MAXINTER (0x01u) +#define CYWDT_LPMODE_DISABLED (0x03u) + +#define CY_WDT_CFG_INTERVAL_MASK (0x03u) +#define CY_WDT_CFG_CTW_RESET (0x80u) +#define CY_WDT_CFG_LPMODE_SHIFT (5u) +#define CY_WDT_CFG_LPMODE_MASK (0x60u) +#define CY_WDT_CFG_WDR_EN (0x10u) +#define CY_WDT_CFG_CLEAR_ALL (0x00u) +#define CY_WDT_CR_FEED (0x01u) + + +/******************************************************************************* +* Voltage Detection API Constants +*******************************************************************************/ + +#define CY_VD_LVID_EN (0x01u) +#define CY_VD_LVIA_EN (0x02u) +#define CY_VD_HVIA_EN (0x04u) + +#define CY_VD_PRESD_EN (0x40u) +#define CY_VD_PRESA_EN (0x80u) + +#define CY_VD_LVID (0x01u) +#define CY_VD_LVIA (0x02u) +#define CY_VD_HVIA (0x04u) + +#define CY_VD_LVI_TRIP_LVID_MASK (0x0Fu) + + +/******************************************************************************* +* Variable VDDA API Constants +*******************************************************************************/ +#if(CYDEV_VARIABLE_VDDA == 1) + + /* Active Power Mode Configuration Register 9 */ + #define CY_LIB_ACT_CFG9_SWCAP0_EN (0x01u) + #define CY_LIB_ACT_CFG9_SWCAP1_EN (0x02u) + #define CY_LIB_ACT_CFG9_SWCAP2_EN (0x04u) + #define CY_LIB_ACT_CFG9_SWCAP3_EN (0x08u) + #define CY_LIB_ACT_CFG9_SWCAPS_MASK (0x0Fu) + + /* Switched Cap Miscellaneous Control Register */ + #define CY_LIB_SC_MISC_PUMP_FORCE (0x20u) + + /* Switched Capacitor 0 Boost Clock Selection Register */ + #define CY_LIB_SC_BST_CLK_EN (0x08u) + #define CY_LIB_SC_BST_CLK_INDEX_MASK (0xF8u) + +#endif /* (CYDEV_VARIABLE_VDDA == 1) */ + + +/******************************************************************************* +* Clock Distribution API Constants +*******************************************************************************/ +#define CY_LIB_CLKDIST_AMASK_MASK (0xF0u) +#define CY_LIB_CLKDIST_DMASK_MASK (0x00u) +#define CY_LIB_CLKDIST_LD_LOAD (0x01u) +#define CY_LIB_CLKDIST_BCFG2_MASK (0x80u) +#define CY_LIB_CLKDIST_MASTERCLK_DIV (7u) +#define CY_LIB_CLKDIST_BCFG2_SSS (0x40u) +#define CY_LIB_CLKDIST_MSTR1_SRC_MASK (0xFCu) +#define CY_LIB_FASTCLK_IMO_DOUBLER (0x10u) +#define CY_LIB_FASTCLK_IMO_IMO (0x20u) +#define CY_LIB_CLKDIST_CR_IMO2X (0x40u) +#define CY_LIB_FASTCLK_IMO_CR_RANGE_MASK (0xF8u) + +#define CY_LIB_CLKDIST_CR_PLL_SCR_MASK (0xFCu) + + +/* CyILO_SetPowerMode() */ +#define CY_ILO_CONTROL_PD_MODE (0x10u) +#define CY_ILO_CONTROL_PD_POSITION (4u) + +#define CY_ILO_SOURCE_100K (0u) +#define CY_ILO_SOURCE_33K (1u) +#define CY_ILO_SOURCE_1K (2u) + +#define CY_ILO_FAST_START (0u) +#define CY_ILO_SLOW_START (1u) + +#define CY_ILO_SOURCE_BITS_CLEAR (0xF3u) +#define CY_ILO_SOURCE_1K_SET (0x08u) +#define CY_ILO_SOURCE_33K_SET (0x04u) +#define CY_ILO_SOURCE_100K_SET (0x00u) + +#define CY_MASTER_SOURCE_IMO (0u) +#define CY_MASTER_SOURCE_PLL (1u) +#define CY_MASTER_SOURCE_XTAL (2u) +#define CY_MASTER_SOURCE_DSI (3u) + +#define CY_IMO_SOURCE_IMO (0u) +#define CY_IMO_SOURCE_XTAL (1u) +#define CY_IMO_SOURCE_DSI (2u) + + +/* CyIMO_Start() */ +#define CY_LIB_PM_ACT_CFG0_IMO_EN (0x10u) +#define CY_LIB_PM_STBY_CFG0_IMO_EN (0x10u) +#define CY_LIB_CLK_IMO_FTW_TIMEOUT (0x00u) + +#define CY_LIB_IMO_3MHZ_VALUE (0x03u) +#define CY_LIB_IMO_6MHZ_VALUE (0x01u) +#define CY_LIB_IMO_12MHZ_VALUE (0x00u) +#define CY_LIB_IMO_24MHZ_VALUE (0x02u) +#define CY_LIB_IMO_48MHZ_VALUE (0x04u) +#define CY_LIB_IMO_62MHZ_VALUE (0x05u) +#define CY_LIB_IMO_74MHZ_VALUE (0x06u) + + +/* CyIMO_SetFreq() */ +#define CY_IMO_FREQ_3MHZ (0u) +#define CY_IMO_FREQ_6MHZ (1u) +#define CY_IMO_FREQ_12MHZ (2u) +#define CY_IMO_FREQ_24MHZ (3u) +#define CY_IMO_FREQ_48MHZ (4u) +#define CY_IMO_FREQ_62MHZ (5u) +#if(CY_PSOC5) + #define CY_IMO_FREQ_74MHZ (6u) +#endif /* (CY_PSOC5) */ +#define CY_IMO_FREQ_USB (8u) + +#define CY_LIB_IMO_USBCLK_ON_SET (0x40u) + + +/* CyCpuClk_SetDivider() */ +#define CY_LIB_CLKDIST_DIV_POSITION (4u) +#define CY_LIB_CLKDIST_MSTR1_DIV_MASK (0x0Fu) + + +/* CyIMO_SetTrimValue() */ +#define CY_LIB_USB_CLK_EN (0x02u) + + +/* CyPLL_OUT_SetSource() - parameters */ +#define CY_PLL_SOURCE_IMO (0u) +#define CY_PLL_SOURCE_XTAL (1u) +#define CY_PLL_SOURCE_DSI (2u) + + +/* CyILO_[Start|Stop][1|100K](), CyILO_[Enable|Disable]33K() */ +#define CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ (0x02u) +#define CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ (0x20u) +#define CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ (0x04u) + + +/* CyUsbClk_SetSource() */ +#define CY_LIB_CLKDIST_UCFG_SRC_SEL_MASK (0x03u) + + +/* CyUsbClk_SetSource() - parameters */ +#define CY_LIB_USB_CLK_IMO2X (0x00u) +#define CY_LIB_USB_CLK_IMO (0x01u) +#define CY_LIB_USB_CLK_PLL (0x02u) +#define CY_LIB_USB_CLK_DSI (0x03u) + + +/* CyUSB_PowerOnCheck() */ +#define CY_ACT_USB_ENABLED (0x01u) +#define CY_ALT_ACT_USB_ENABLED (0x01u) + + +/*************************************** +* Registers +***************************************/ + + +/******************************************************************************* +* System Registers +*******************************************************************************/ + +/* Software Reset Control Register */ +#define CY_LIB_RESET_CR2_REG (* (reg8 *) CYREG_RESET_CR2) +#define CY_LIB_RESET_CR2_PTR ( (reg8 *) CYREG_RESET_CR2) + +/* Timewheel Configuration Register 0 */ +#define CY_LIB_PM_TW_CFG0_REG (*(reg8 *) CYREG_PM_TW_CFG0) +#define CY_LIB_PM_TW_CFG0_PTR ( (reg8 *) CYREG_PM_TW_CFG0) + +/* Timewheel Configuration Register 2 */ +#define CY_LIB_PM_TW_CFG2_REG (*(reg8 *) CYREG_PM_TW_CFG2) +#define CY_LIB_PM_TW_CFG2_PTR ( (reg8 *) CYREG_PM_TW_CFG2) + +/* USB Configuration Register */ +#define CY_LIB_CLKDIST_UCFG_REG (*(reg8 *) CYREG_CLKDIST_UCFG) +#define CY_LIB_CLKDIST_UCFG_PTR ( (reg8 *) CYREG_CLKDIST_UCFG) + +/* Internal Main Oscillator Trim Register 1 */ +#define CY_LIB_IMO_TR1_REG (*(reg8 *) CYREG_IMO_TR1) +#define CY_LIB_IMO_TR1_PTR ( (reg8 *) CYREG_IMO_TR1) + +/* USB control 1 Register */ +#define CY_LIB_USB_CR1_REG (*(reg8 *) CYREG_USB_CR1 ) +#define CY_LIB_USB_CR1_PTR ( (reg8 *) CYREG_USB_CR1 ) + +/* Active Power Mode Configuration Register 0 */ +#define CY_LIB_PM_ACT_CFG0_REG (*(reg8 *) CYREG_PM_ACT_CFG0) +#define CY_LIB_PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0) + +/* Standby Power Mode Configuration Register 0 */ +#define CY_LIB_PM_STBY_CFG0_REG (*(reg8 *) CYREG_PM_STBY_CFG0) +#define CY_LIB_PM_STBY_CFG0_PTR ( (reg8 *) CYREG_PM_STBY_CFG0) + +/* Active Power Mode Configuration Register 5 */ +#define CY_LIB_PM_ACT_CFG5_REG (* (reg8 *) CYREG_PM_ACT_CFG5 ) +#define CY_LIB_PM_ACT_CFG5_PTR ( (reg8 *) CYREG_PM_ACT_CFG5 ) + +/* Standby Power Mode Configuration Register 5 */ +#define CY_LIB_PM_STBY_CFG5_REG (* (reg8 *) CYREG_PM_STBY_CFG5 ) +#define CY_LIB_PM_STBY_CFG5_PTR ( (reg8 *) CYREG_PM_STBY_CFG5 ) + +/* CyIMO_SetTrimValue() */ +#if(CY_PSOC3) + #define CY_LIB_TRIM_IMO_3MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ) + #define CY_LIB_TRIM_IMO_6MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ) + #define CY_LIB_TRIM_IMO_12MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ) + #define CY_LIB_TRIM_IMO_24MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ) + #define CY_LIB_TRIM_IMO_67MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ) + #define CY_LIB_TRIM_IMO_80MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ) + #define CY_LIB_TRIM_IMO_USB_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_USB) + #define CY_LIB_TRIM_IMO_TR1_PTR ((void far *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u)) + #else + #define CY_LIB_TRIM_IMO_3MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ) + #define CY_LIB_TRIM_IMO_6MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ) + #define CY_LIB_TRIM_IMO_12MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ) + #define CY_LIB_TRIM_IMO_24MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ) + #define CY_LIB_TRIM_IMO_67MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ) + #define CY_LIB_TRIM_IMO_80MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ) + #define CY_LIB_TRIM_IMO_USB_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_USB) + #define CY_LIB_TRIM_IMO_TR1_PTR ((reg8 *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u)) +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* PLL Registers +*******************************************************************************/ + +/* PLL Configuration Register 0 */ +#define CY_CLK_PLL_CFG0_REG (*(reg8 *) CYREG_FASTCLK_PLL_CFG0) +#define CY_CLK_PLL_CFG0_PTR ( (reg8 *) CYREG_FASTCLK_PLL_CFG0) + +/* PLL Configuration Register 1 */ +#define CY_CLK_PLL_CFG1_REG (*(reg8 *) CYREG_FASTCLK_PLL_CFG1) +#define CY_CLK_PLL_CFG1_PTR ( (reg8 *) CYREG_FASTCLK_PLL_CFG1) + +/* PLL Status Register */ +#define CY_CLK_PLL_SR_REG (*(reg8 *) CYREG_FASTCLK_PLL_SR) +#define CY_CLK_PLL_SR_PTR ( (reg8 *) CYREG_FASTCLK_PLL_SR) + +/* PLL Q-Counter Configuration Register */ +#define CY_CLK_PLL_Q_REG (*(reg8 *) CYREG_FASTCLK_PLL_Q) +#define CY_CLK_PLL_Q_PTR ( (reg8 *) CYREG_FASTCLK_PLL_Q) + +/* PLL P-Counter Configuration Register */ +#define CY_CLK_PLL_P_REG (*(reg8 *) CYREG_FASTCLK_PLL_P) +#define CY_CLK_PLL_P_PTR ( (reg8 *) CYREG_FASTCLK_PLL_P) + + +/******************************************************************************* +* External MHz Crystal Oscillator Registers +*******************************************************************************/ + +/* External MHz Crystal Oscillator Status and Control Register */ +#define CY_CLK_XMHZ_CSR_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CSR) +#define CY_CLK_XMHZ_CSR_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CSR) + +/* External MHz Crystal Oscillator Configuration Register 0 */ +#define CY_CLK_XMHZ_CFG0_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CFG0) +#define CY_CLK_XMHZ_CFG0_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CFG0) + +/* External MHz Crystal Oscillator Configuration Register 1 */ +#define CY_CLK_XMHZ_CFG1_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CFG1) +#define CY_CLK_XMHZ_CFG1_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CFG1) + + +/******************************************************************************* +* External 32kHz Crystal Oscillator Registers +*******************************************************************************/ + +/* 32 kHz Watch Crystal Oscillator Trim Register */ +#define CY_CLK_XTAL32_TR_REG (*(reg8 *) CYREG_X32_TR) +#define CY_CLK_XTAL32_TR_PTR ( (reg8 *) CYREG_X32_TR) + +/* External 32kHz Crystal Oscillator Test Register */ +#define CY_CLK_XTAL32_TST_REG (*(reg8 *) CYREG_SLOWCLK_X32_TST) +#define CY_CLK_XTAL32_TST_PTR ( (reg8 *) CYREG_SLOWCLK_X32_TST) + +/* External 32kHz Crystal Oscillator Control Register */ +#define CY_CLK_XTAL32_CR_REG (*(reg8 *) CYREG_SLOWCLK_X32_CR) +#define CY_CLK_XTAL32_CR_PTR ( (reg8 *) CYREG_SLOWCLK_X32_CR) + +/* External 32kHz Crystal Oscillator Configuration Register */ +#define CY_CLK_XTAL32_CFG_REG (*(reg8 *) CYREG_SLOWCLK_X32_CFG) +#define CY_CLK_XTAL32_CFG_PTR ( (reg8 *) CYREG_SLOWCLK_X32_CFG) + + +/******************************************************************************* +* Watchdog Timer Registers +*******************************************************************************/ + +/* Watchdog Timer Configuration Register */ +#define CY_WDT_CFG_REG (*(reg8 *) CYREG_PM_WDT_CFG) +#define CY_WDT_CFG_PTR ( (reg8 *) CYREG_PM_WDT_CFG) + +/* Watchdog Timer Control Register */ +#define CY_WDT_CR_REG (*(reg8 *) CYREG_PM_WDT_CR) +#define CY_WDT_CR_PTR ( (reg8 *) CYREG_PM_WDT_CR) + + +/******************************************************************************* +* LVI/HVI Registers +*******************************************************************************/ + +#define CY_VD_LVI_TRIP_REG (* (reg8 *) CYREG_RESET_CR0) +#define CY_VD_LVI_TRIP_PTR ( (reg8 *) CYREG_RESET_CR0) + +#define CY_VD_LVI_HVI_CONTROL_REG (* (reg8 *) CYREG_RESET_CR1) +#define CY_VD_LVI_HVI_CONTROL_PTR ( (reg8 *) CYREG_RESET_CR1) + +#define CY_VD_PRES_CONTROL_REG (* (reg8 *) CYREG_RESET_CR3) +#define CY_VD_PRES_CONTROL_PTR ( (reg8 *) CYREG_RESET_CR3) + +#define CY_VD_PERSISTENT_STATUS_REG (* (reg8 *) CYREG_RESET_SR0) +#define CY_VD_PERSISTENT_STATUS_PTR ( (reg8 *) CYREG_RESET_SR0) + +#define CY_VD_RT_STATUS_REG (* (reg8 *) CYREG_RESET_SR2) +#define CY_VD_RT_STATUS_PTR ( (reg8 *) CYREG_RESET_SR2) + + +/******************************************************************************* +* Variable VDDA +*******************************************************************************/ +#if(CYDEV_VARIABLE_VDDA == 1) + + /* Active Power Mode Configuration Register 9 */ + #define CY_LIB_ACT_CFG9_REG (* (reg8 *) CYREG_PM_ACT_CFG9 ) + #define CY_LIB_ACT_CFG9_PTR ( (reg8 *) CYREG_PM_ACT_CFG9 ) + + /* Switched Capacitor 0 Boost Clock Selection Register */ + #define CY_LIB_SC0_BST_REG (* (reg8 *) CYREG_SC0_BST ) + #define CY_LIB_SC0_BST_PTR ( (reg8 *) CYREG_SC0_BST ) + + /* Switched Capacitor 1 Boost Clock Selection Register */ + #define CY_LIB_SC1_BST_REG (* (reg8 *) CYREG_SC1_BST ) + #define CY_LIB_SC1_BST_PTR ( (reg8 *) CYREG_SC1_BST ) + + /* Switched Capacitor 2 Boost Clock Selection Register */ + #define CY_LIB_SC2_BST_REG (* (reg8 *) CYREG_SC2_BST ) + #define CY_LIB_SC2_BST_PTR ( (reg8 *) CYREG_SC2_BST ) + + /* Switched Capacitor 3 Boost Clock Selection Register */ + #define CY_LIB_SC3_BST_REG (* (reg8 *) CYREG_SC3_BST ) + #define CY_LIB_SC3_BST_PTR ( (reg8 *) CYREG_SC3_BST ) + + /* Switched Cap Miscellaneous Control Register */ + #define CY_LIB_SC_MISC_REG (* (reg8 *) CYREG_SC_MISC ) + #define CY_LIB_SC_MISC_PTR ( (reg8 *) CYREG_SC_MISC ) + +#endif /* (CYDEV_VARIABLE_VDDA == 1) */ + + +/******************************************************************************* +* Clock Distribution Registers +*******************************************************************************/ + +/* Analog Clock Mask Register */ +#define CY_LIB_CLKDIST_AMASK_REG (* (reg8 *) CYREG_CLKDIST_AMASK ) +#define CY_LIB_CLKDIST_AMASK_PTR ( (reg8 *) CYREG_CLKDIST_AMASK ) + +/* Digital Clock Mask Register */ +#define CY_LIB_CLKDIST_DMASK_REG (*(reg8 *) CYREG_CLKDIST_DMASK) +#define CY_LIB_CLKDIST_DMASK_PTR ( (reg8 *) CYREG_CLKDIST_DMASK) + +/* CLK_BUS Configuration Register */ +#define CY_LIB_CLKDIST_BCFG2_REG (*(reg8 *) CYREG_CLKDIST_BCFG2) +#define CY_LIB_CLKDIST_BCFG2_PTR ( (reg8 *) CYREG_CLKDIST_BCFG2) + +/* LSB Shadow Divider Value Register */ +#define CY_LIB_CLKDIST_WRK_LSB_REG (*(reg8 *) CYREG_CLKDIST_WRK0) +#define CY_LIB_CLKDIST_WRK_LSB_PTR ( (reg8 *) CYREG_CLKDIST_WRK0) + +/* MSB Shadow Divider Value Register */ +#define CY_LIB_CLKDIST_WRK_MSB_REG (*(reg8 *) CYREG_CLKDIST_WRK1) +#define CY_LIB_CLKDIST_WRK_MSB_PTR ( (reg8 *) CYREG_CLKDIST_WRK1) + +/* LOAD Register */ +#define CY_LIB_CLKDIST_LD_REG (*(reg8 *) CYREG_CLKDIST_LD) +#define CY_LIB_CLKDIST_LD_PTR ( (reg8 *) CYREG_CLKDIST_LD) + +/* CLK_BUS LSB Divider Value Register */ +#define CY_LIB_CLKDIST_BCFG_LSB_REG (*(reg8 *) CYREG_CLKDIST_BCFG0) +#define CY_LIB_CLKDIST_BCFG_LSB_PTR ( (reg8 *) CYREG_CLKDIST_BCFG0) + +/* CLK_BUS MSB Divider Value Register */ +#define CY_LIB_CLKDIST_BCFG_MSB_REG (*(reg8 *) CYREG_CLKDIST_BCFG1) +#define CY_LIB_CLKDIST_BCFG_MSB_PTR ( (reg8 *) CYREG_CLKDIST_BCFG1) + +/* Master clock (clk_sync_d) Divider Value Register */ +#define CY_LIB_CLKDIST_MSTR0_REG (*(reg8 *) CYREG_CLKDIST_MSTR0) +#define CY_LIB_CLKDIST_MSTR0_PTR ( (reg8 *) CYREG_CLKDIST_MSTR0) + +/* Master (clk_sync_d) Configuration Register/CPU Divider Value */ +#define CY_LIB_CLKDIST_MSTR1_REG (*(reg8 *) CYREG_CLKDIST_MSTR1) +#define CY_LIB_CLKDIST_MSTR1_PTR ( (reg8 *) CYREG_CLKDIST_MSTR1) + +/* Internal Main Oscillator Control Register */ +#define CY_LIB_FASTCLK_IMO_CR_REG (*(reg8 *) CYREG_FASTCLK_IMO_CR) +#define CY_LIB_FASTCLK_IMO_CR_PTR ( (reg8 *) CYREG_FASTCLK_IMO_CR) + +/* Configuration Register CR */ +#define CY_LIB_CLKDIST_CR_REG (*(reg8 *) CYREG_CLKDIST_CR) +#define CY_LIB_CLKDIST_CR_PTR ( (reg8 *) CYREG_CLKDIST_CR) + +/* Internal Low-speed Oscillator Control Register 0 */ +#define CY_LIB_SLOWCLK_ILO_CR0_REG (*(reg8 *) CYREG_SLOWCLK_ILO_CR0) +#define CY_LIB_SLOWCLK_ILO_CR0_PTR ( (reg8 *) CYREG_SLOWCLK_ILO_CR0) + + +/******************************************************************************* +* Interrupt Registers +*******************************************************************************/ + +#if(CY_PSOC5) + + /* Interrupt Vector Table Offset */ + #define CY_INT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET) + + /* Interrupt Priority 0-31 */ + #define CY_INT_PRIORITY_REG (* (reg8 *) CYREG_NVIC_PRI_0) + #define CY_INT_PRIORITY_PTR ( (reg8 *) CYREG_NVIC_PRI_0) + + /* Interrupt Enable Set 0-31 */ + #define CY_INT_ENABLE_REG (* (reg32 *) CYREG_NVIC_SETENA0) + #define CY_INT_ENABLE_PTR ( (reg32 *) CYREG_NVIC_SETENA0) + + /* Interrupt Enable Clear 0-31 */ + #define CY_INT_CLEAR_REG (* (reg32 *) CYREG_NVIC_CLRENA0) + #define CY_INT_CLEAR_PTR ( (reg32 *) CYREG_NVIC_CLRENA0) + + /* Interrupt Pending Set 0-31 */ + #define CY_INT_SET_PEND_REG (* (reg32 *) CYREG_NVIC_SETPEND0) + #define CY_INT_SET_PEND_PTR ( (reg32 *) CYREG_NVIC_SETPEND0) + + /* Interrupt Pending Clear 0-31 */ + #define CY_INT_CLR_PEND_REG (* (reg32 *) CYREG_NVIC_CLRPEND0) + #define CY_INT_CLR_PEND_PTR ( (reg32 *) CYREG_NVIC_CLRPEND0) + + /* Cache Control Register */ + #define CY_CACHE_CONTROL_REG (* (reg16 *) CYREG_CACHE_CC_CTL ) + #define CY_CACHE_CONTROL_PTR ( (reg16 *) CYREG_CACHE_CC_CTL ) + +#elif (CY_PSOC3) + + /* Interrupt Address Vector registers */ + #define CY_INT_VECT_TABLE ((cyisraddress CYXDATA *) CYREG_INTC_VECT_MBASE) + + /* Interrrupt Controller Priority Registers */ + #define CY_INT_PRIORITY_REG (* (reg8 *) CYREG_INTC_PRIOR0) + #define CY_INT_PRIORITY_PTR ( (reg8 *) CYREG_INTC_PRIOR0) + + /* Interrrupt Controller Set Enable Registers */ + #define CY_INT_ENABLE_REG (* (reg8 *) CYREG_INTC_SET_EN0) + #define CY_INT_ENABLE_PTR ( (reg8 *) CYREG_INTC_SET_EN0) + + #define CY_INT_SET_EN0_REG (* (reg8 *) CYREG_INTC_SET_EN0) + #define CY_INT_SET_EN0_PTR ( (reg8 *) CYREG_INTC_SET_EN0) + + #define CY_INT_SET_EN1_REG (* (reg8 *) CYREG_INTC_SET_EN1) + #define CY_INT_SET_EN1_PTR ( (reg8 *) CYREG_INTC_SET_EN1) + + #define CY_INT_SET_EN2_REG (* (reg8 *) CYREG_INTC_SET_EN2) + #define CY_INT_SET_EN2_PTR ( (reg8 *) CYREG_INTC_SET_EN2) + + #define CY_INT_SET_EN3_REG (* (reg8 *) CYREG_INTC_SET_EN3) + #define CY_INT_SET_EN3_PTR ( (reg8 *) CYREG_INTC_SET_EN3) + + /* Interrrupt Controller Clear Enable Registers */ + #define CY_INT_CLEAR_REG (* (reg8 *) CYREG_INTC_CLR_EN0) + #define CY_INT_CLEAR_PTR ( (reg8 *) CYREG_INTC_CLR_EN0) + + #define CY_INT_CLR_EN0_REG (* (reg8 *) CYREG_INTC_CLR_EN0) + #define CY_INT_CLR_EN0_PTR ( (reg8 *) CYREG_INTC_CLR_EN0) + + #define CY_INT_CLR_EN1_REG (* (reg8 *) CYREG_INTC_CLR_EN1) + #define CY_INT_CLR_EN1_PTR ( (reg8 *) CYREG_INTC_CLR_EN1) + + #define CY_INT_CLR_EN2_REG (* (reg8 *) CYREG_INTC_CLR_EN2) + #define CY_INT_CLR_EN2_PTR ( (reg8 *) CYREG_INTC_CLR_EN2) + + #define CY_INT_CLR_EN3_REG (* (reg8 *) CYREG_INTC_CLR_EN3) + #define CY_INT_CLR_EN3_PTR ( (reg8 *) CYREG_INTC_CLR_EN3) + + + /* Interrrupt Controller Set Pend Registers */ + #define CY_INT_SET_PEND_REG (* (reg8 *) CYREG_INTC_SET_PD0) + #define CY_INT_SET_PEND_PTR ( (reg8 *) CYREG_INTC_SET_PD0) + + /* Interrrupt Controller Clear Pend Registers */ + #define CY_INT_CLR_PEND_REG (* (reg8 *) CYREG_INTC_CLR_PD0) + #define CY_INT_CLR_PEND_PTR ( (reg8 *) CYREG_INTC_CLR_PD0) + + + /* Access Interrupt Controller Registers based on interrupt number */ + #define CY_INT_SET_EN_INDX_PTR(number) ((reg8 *) (CYREG_INTC_SET_EN0 + (((number) & CY_INT_NUMBER_MASK) >> 3u))) + #define CY_INT_CLR_EN_INDX_PTR(number) ((reg8 *) (CYREG_INTC_CLR_EN0 + (((number) & CY_INT_NUMBER_MASK) >> 3u))) + #define CY_INT_CLR_PEND_INDX_PTR(number) ((reg8 *) (CYREG_INTC_CLR_PD0 + (((number) & CY_INT_NUMBER_MASK) >> 3u))) + #define CY_INT_SET_PEND_INDX_PTR(number) ((reg8 *) (CYREG_INTC_SET_PD0 + (((number) & CY_INT_NUMBER_MASK) >> 3u))) + +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* Macro Name: CyAssert +******************************************************************************** +* Summary: +* Macro that evaluates the expression and if it is false (evaluates to 0) then +* the processor is halted. +* +* This macro is evaluated unless NDEBUG is defined. +* +* If NDEBUG is defined, then no code is generated for this macro. NDEBUG is +* defined by default for a Release build setting and not defined for a Debug +* build setting. +* +* Parameters: +* expr: Logical expression. Asserts if false. +* +* Return: +* None +* +*******************************************************************************/ +#if !defined(NDEBUG) + #define CYASSERT(x) { \ + if(!(x)) \ + { \ + CyHalt((uint8) 0u); \ + } \ + } +#else + #define CYASSERT(x) +#endif /* !defined(NDEBUG) */ + + +/* Reset register fields of RESET_SR0 (CyResetStatus) */ +#define CY_RESET_LVID (0x01u) +#define CY_RESET_LVIA (0x02u) +#define CY_RESET_HVIA (0x04u) +#define CY_RESET_WD (0x08u) +#define CY_RESET_SW (0x20u) +#define CY_RESET_GPIO0 (0x40u) +#define CY_RESET_GPIO1 (0x80u) + + +/* Interrrupt Controller Configuration and Status Register */ +#if(CY_PSOC3) + #define INTERRUPT_CSR ((reg8 *) CYREG_INTC_CSR_EN) + #define DISABLE_IRQ_SET ((uint8)(0x01u << 1u)) /* INTC_CSR_EN */ + #define INTERRUPT_DISABLE_IRQ {*INTERRUPT_CSR |= DISABLE_IRQ_SET;} + #define INTERRUPT_ENABLE_IRQ {*INTERRUPT_CSR = (uint8)(~DISABLE_IRQ_SET);} +#endif /* (CY_PSOC3) */ + + +#if defined(__ARMCC_VERSION) + #define CyGlobalIntEnable {__enable_irq();} + #define CyGlobalIntDisable {__disable_irq();} +#elif defined(__GNUC__) || defined (__ICCARM__) + #define CyGlobalIntEnable {__asm("CPSIE i");} + #define CyGlobalIntDisable {__asm("CPSID i");} +#elif defined(__C51__) + #define CyGlobalIntEnable {\ + EA = 1u; \ + INTERRUPT_ENABLE_IRQ\ + } + + #define CyGlobalIntDisable {\ + INTERRUPT_DISABLE_IRQ; \ + CY_NOP; \ + EA = 0u;\ + } +#else + #error No compiler toolchain defined + #define CyGlobalIntEnable + #define CyGlobalIntDisable +#endif /* (__ARMCC_VERSION) */ + + +#ifdef CYREG_MLOGIC_CPU_SCR_CPU_SCR + #define CYDEV_HALT_CPU CY_SET_REG8(CYREG_MLOGIC_CPU_SCR_CPU_SCR, 0x01u) +#else + #define CYDEV_HALT_CPU CY_SET_REG8(CYREG_MLOGIC_CPU_SCR, 0x01u) +#endif /* (CYREG_MLOGIC_CPU_SCR_CPU_SCR) */ + + +#ifdef CYREG_MLOGIC_REV_ID_REV_ID + #define CYDEV_CHIP_REV_ACTUAL (CY_GET_REG8(CYREG_MLOGIC_REV_ID_REV_ID)) +#else + #define CYDEV_CHIP_REV_ACTUAL (CY_GET_REG8(CYREG_MLOGIC_REV_ID)) +#endif /* (CYREG_MLOGIC_REV_ID_REV_ID) */ + + +/******************************************************************************* +* System API constants +*******************************************************************************/ +#define CY_CACHE_CONTROL_FLUSH (0x0004u) +#define CY_LIB_RESET_CR2_RESET (0x01u) + + +/******************************************************************************* +* Interrupt API constants +*******************************************************************************/ +#if(CY_PSOC5) + + #define CY_INT_IRQ_BASE (16u) + +#elif (CY_PSOC3) + + #define CY_INT_IRQ_BASE (0u) + +#endif /* (CY_PSOC5) */ + +/* Valid range of interrupt 0-31 */ +#define CY_INT_NUMBER_MAX (31u) + +/* Valid range of system interrupt 0-15 */ +#define CY_INT_SYS_NUMBER_MAX (15u) + +/* Valid range of system priority 0-7 */ +#define CY_INT_PRIORITY_MAX (7u) + +/* Mask to get valid range of interrupt 0-31 */ +#define CY_INT_NUMBER_MASK (0x1Fu) + +/* Mask to get valid range of system priority 0-7 */ +#define CY_INT_PRIORITY_MASK (0x7u) + +/* Mask to get valid range of system interrupt 0-15 */ +#define CY_INT_SYS_NUMBER_MASK (0xFu) + + +/******************************************************************************* +* Interrupt Macros +*******************************************************************************/ + +#if(CY_PSOC5) + + /******************************************************************************* + * Macro Name: CyIntEnable + ******************************************************************************** + * + * Summary: + * Enables the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number + * + * Return: + * None + * + *******************************************************************************/ + #define CyIntEnable(number) CY_SET_REG32(CY_INT_ENABLE_PTR, ((uint32)((uint32)1u << (0x1Fu & (number))))) + + /******************************************************************************* + * Macro Name: CyIntDisable + ******************************************************************************** + * + * Summary: + * Disables the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number. + * + * Return: + * None + * + *******************************************************************************/ + #define CyIntDisable(number) CY_SET_REG32(CY_INT_CLEAR_PTR, ((uint32)((uint32)1u << (0x1Fu & (number))))) + + + /******************************************************************************* + * Macro Name: CyIntSetPending + ******************************************************************************** + * + * Summary: + * Forces the specified interrupt number to be pending. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number. + * + * Return: + * None + * + *******************************************************************************/ + #define CyIntSetPending(number) CY_SET_REG32(CY_INT_SET_PEND_PTR, ((uint32)((uint32)1u << (0x1Fu & (number))))) + + + /******************************************************************************* + * Macro Name: CyIntClearPending + ******************************************************************************** + * + * Summary: + * Clears any pending interrupt for the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number. + * + * Return: + * None + * + *******************************************************************************/ + #define CyIntClearPending(number) CY_SET_REG32(CY_INT_CLR_PEND_PTR, ((uint32)((uint32)1u << (0x1Fu & (number))))) + + +#else /* PSoC3 */ + + + /******************************************************************************* + * Macro Name: CyIntEnable + ******************************************************************************** + * + * Summary: + * Enables the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number + * + * Return: + * None + * + *******************************************************************************/ + #define CyIntEnable(number) CY_SET_REG8(CY_INT_SET_EN_INDX_PTR((number)), \ + ((uint8)(1u << (0x07u & (number))))) + + + /******************************************************************************* + * Macro Name: CyIntDisable + ******************************************************************************** + * + * Summary: + * Disables the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number. + * + * Return: + * None + * + *******************************************************************************/ + #define CyIntDisable(number) CY_SET_REG8(CY_INT_CLR_EN_INDX_PTR((number)), \ + ((uint8)(1u << (0x07u & (number))))) + + + /******************************************************************************* + * Macro Name: CyIntSetPending + ******************************************************************************** + * + * Summary: + * Forces the specified interrupt number to be pending. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number. + * + * Return: + * None + * + *******************************************************************************/ + #define CyIntSetPending(number) CY_SET_REG8(CY_INT_SET_PEND_INDX_PTR((number)), \ + ((uint8)(1u << (0x07u & (number))))) + + + /******************************************************************************* + * Macro Name: CyIntClearPending + ******************************************************************************** + * Summary: + * Clears any pending interrupt for the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number. + * + * Return: + * None + * + *******************************************************************************/ + #define CyIntClearPending(number) CY_SET_REG8(CY_INT_CLR_PEND_INDX_PTR((number)), \ + ((uint8)(1u << (0x07u & (number))))) + +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used. +*******************************************************************************/ +#define CYGlobalIntEnable CyGlobalIntEnable +#define CYGlobalIntDisable CyGlobalIntDisable + +#define cymemset(s,c,n) memset((s),(c),(n)) +#define cymemcpy(d,s,n) memcpy((d),(s),(n)) + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from cy_boot 3.0 +*******************************************************************************/ +#define MFGCFG_X32_TR_PTR (CY_CLK_XTAL32_TR_PTR) +#define MFGCFG_X32_TR (CY_CLK_XTAL32_TR_REG) +#define SLOWCLK_X32_TST_PTR (CY_CLK_XTAL32_TST_PTR) +#define SLOWCLK_X32_TST (CY_CLK_XTAL32_TST_REG) +#define SLOWCLK_X32_CR_PTR (CY_CLK_XTAL32_CR_PTR) +#define SLOWCLK_X32_CR (CY_CLK_XTAL32_CR_REG) +#define SLOWCLK_X32_CFG_PTR (CY_CLK_XTAL32_CFG_PTR) +#define SLOWCLK_X32_CFG (CY_CLK_XTAL32_CFG_REG) + +#define X32_CONTROL_ANA_STAT (CY_CLK_XTAL32_CR_ANA_STAT) +#define X32_CONTROL_DIG_STAT (0x10u) +#define X32_CONTROL_LPM (CY_CLK_XTAL32_CR_LPM) +#define X32_CONTROL_LPM_POSITION (1u) +#define X32_CONTROL_X32EN (CY_CLK_XTAL32_CR_EN) +#define X32_CONTROL_PDBEN (CY_CLK_XTAL32_CR_PDBEN) +#define X32_TR_DPMODE (CY_CLK_XTAL32_TR_STARTUP) +#define X32_TR_CLEAR (CY_CLK_XTAL32_TR_POWERDOWN) +#define X32_TR_HPMODE (CY_CLK_XTAL32_TR_HIGH_POWER) +#define X32_TR_LPMODE (CY_CLK_XTAL32_TR_LOW_POWER) +#define X32_TST_SETALL (CY_CLK_XTAL32_TST_DEFAULT) +#define X32_CFG_LP_BITS_MASK (CY_CLK_XTAL32_CFG_LP_MASK) +#define X32_CFG_LP_DEFAULT (CY_CLK_XTAL32_CFG_LP_DEFAULT) +#define X32_CFG_LOWPOWERMODE (0x80u) +#define X32_CFG_LP_LOWPOWER (0x8u) +#define CY_X32_HIGHPOWER_MODE (0u) +#define CY_X32_LOWPOWER_MODE (1u) +#define CY_XTAL32K_DIG_STAT (0x10u) +#define CY_XTAL32K_STAT_FIELDS (0x30u) +#define CY_XTAL32K_DIG_STAT_UNSTABLE (0u) +#define CY_XTAL32K_ANA_STAT_UNSTABLE (0x0u) +#define CY_XTAL32K_STATUS (0x20u) + +#define FASTCLK_XMHZ_CSR_PTR (CY_CLK_XMHZ_CSR_PTR) +#define FASTCLK_XMHZ_CSR (CY_CLK_XMHZ_CSR_REG) +#define FASTCLK_XMHZ_CFG0_PTR (CY_CLK_XMHZ_CFG0_PTR) +#define FASTCLK_XMHZ_CFG0 (CY_CLK_XMHZ_CFG0_REG) +#define FASTCLK_XMHZ_CFG1_PTR (CY_CLK_XMHZ_CFG1_PTR) +#define FASTCLK_XMHZ_CFG1 (CY_CLK_XMHZ_CFG1_REG) +#define FASTCLK_XMHZ_GAINMASK (CY_CLK_XMHZ_CFG0_XCFG_MASK) +#define FASTCLK_XMHZ_VREFMASK (CY_CLK_XMHZ_CFG1_VREF_FB_MASK) +#define FASTCLK_XMHZ_VREF_WD_MASK (CY_CLK_XMHZ_CFG1_VREF_WD_MASK) +#define XMHZ_CONTROL_ENABLE (CY_CLK_XMHZ_CSR_ENABLE) +#define X32_CONTROL_XERR_MASK (CY_CLK_XMHZ_CSR_XERR) +#define X32_CONTROL_XERR_DIS (CY_CLK_XMHZ_CSR_XFB) +#define X32_CONTROL_XERR_POSITION (7u) +#define X32_CONTROL_FAULT_RECOVER (CY_CLK_XMHZ_CSR_XPROT) + +#define CYWDT_CFG (CY_WDT_CFG_PTR) +#define CYWDT_CR (CY_WDT_CR_PTR) + +#define CYWDT_TICKS_MASK (CY_WDT_CFG_INTERVAL_MASK) +#define CYWDT_RESET (CY_WDT_CFG_CTW_RESET) +#define CYWDT_LPMODE_SHIFT (CY_WDT_CFG_LPMODE_SHIFT) +#define CYWDT_LPMODE_MASK (CY_WDT_CFG_LPMODE_MASK) +#define CYWDT_ENABLE_BIT (CY_WDT_CFG_WDR_EN) + +#define FASTCLK_PLL_CFG0_PTR (CY_CLK_PLL_CFG0_PTR) +#define FASTCLK_PLL_CFG0 (CY_CLK_PLL_CFG0_REG) +#define FASTCLK_PLL_SR_PTR (CY_CLK_PLL_SR_PTR) +#define FASTCLK_PLL_SR (CY_CLK_PLL_SR_REG) + +#define MAX_FASTCLK_PLL_Q_VALUE (CY_CLK_PLL_MAX_Q_VALUE) +#define MIN_FASTCLK_PLL_Q_VALUE (CY_CLK_PLL_MIN_Q_VALUE) +#define MIN_FASTCLK_PLL_P_VALUE (CY_CLK_PLL_MIN_P_VALUE) +#define MIN_FASTCLK_PLL_CUR_VALUE (CY_CLK_PLL_MIN_CUR_VALUE) +#define MAX_FASTCLK_PLL_CUR_VALUE (CY_CLK_PLL_MAX_CUR_VALUE) + +#define PLL_CONTROL_ENABLE (CY_CLK_PLL_ENABLE) +#define PLL_STATUS_LOCK (CY_CLK_PLL_LOCK_STATUS) +#define PLL_STATUS_ENABLED (CY_CLK_PLL_ENABLE) +#define PLL_CURRENT_POSITION (CY_CLK_PLL_CURRENT_POSITION) +#define PLL_VCO_GAIN_2 (2u) + +#define FASTCLK_PLL_Q_PTR (CY_CLK_PLL_Q_PTR) +#define FASTCLK_PLL_Q (CY_CLK_PLL_Q_REG) +#define FASTCLK_PLL_P_PTR (CY_CLK_PLL_P_PTR) +#define FASTCLK_PLL_P (CY_CLK_PLL_P_REG) +#define FASTCLK_PLL_CFG1_PTR (CY_CLK_PLL_CFG1_REG) +#define FASTCLK_PLL_CFG1 (CY_CLK_PLL_CFG1_REG) + +#define CY_VD_PRESISTENT_STATUS_REG (CY_VD_PERSISTENT_STATUS_REG) +#define CY_VD_PRESISTENT_STATUS_PTR (CY_VD_PERSISTENT_STATUS_PTR) + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from cy_boot 3.20 +*******************************************************************************/ + +#if(CY_PSOC5) + + #define CYINT_IRQ_BASE (CY_INT_IRQ_BASE) + + #define CYINT_VECT_TABLE (CY_INT_VECT_TABLE) + #define CYINT_PRIORITY (CY_INT_PRIORITY_PTR) + #define CYINT_ENABLE (CY_INT_ENABLE_PTR) + #define CYINT_CLEAR (CY_INT_CLEAR_PTR) + #define CYINT_SET_PEND (CY_INT_SET_PEND_PTR) + #define CYINT_CLR_PEND (CY_INT_CLR_PEND_PTR) + #define CACHE_CC_CTL (CY_CACHE_CONTROL_PTR) + +#elif (CY_PSOC3) + + #define CYINT_IRQ_BASE (CY_INT_IRQ_BASE) + + #define CYINT_VECT_TABLE (CY_INT_VECT_TABLE) + #define CYINT_PRIORITY (CY_INT_PRIORITY_PTR) + #define CYINT_ENABLE (CY_INT_ENABLE_PTR) + #define CYINT_CLEAR (CY_INT_CLEAR_PTR) + #define CYINT_SET_PEND (CY_INT_SET_PEND_PTR) + #define CYINT_CLR_PEND (CY_INT_CLR_PEND_PTR) + +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from cy_boot 3.30 +*******************************************************************************/ +#define BUS_AMASK_CLEAR (0xF0u) +#define BUS_DMASK_CLEAR (0x00u) +#define CLKDIST_LD_LOAD_SET (0x01u) +#define CLKDIST_WRK0_MASK_SET (0x80u) /* Enable shadow loads */ +#define MASTERCLK_DIVIDER_VALUE (7u) +#define CLKDIST_BCFG2_SSS_SET (0x40u) /* Sync source is same frequency */ +#define MASTER_CLK_SRC_CLEAR (0xFCu) +#define IMO_DOUBLER_ENABLE (0x10u) +#define CLOCK_IMO_IMO (0x20u) +#define CLOCK_IMO2X_XTAL (0x40u) +#define CLOCK_IMO_RANGE_CLEAR (0xF8u) +#define CLOCK_CONTROL_DIST_MASK (0xFCu) + + +#define CLKDIST_AMASK (*(reg8 *) CYREG_CLKDIST_AMASK) +#define CLKDIST_AMASK_PTR ( (reg8 *) CYREG_CLKDIST_AMASK) +#define CLKDIST_DMASK_PTR ( (reg8 *) CYREG_CLKDIST_DMASK) +#define CLKDIST_DMASK (*(reg8 *) CYREG_CLKDIST_DMASK) +#define CLKDIST_BCFG2_PTR ( (reg8 *) CYREG_CLKDIST_BCFG2) +#define CLKDIST_BCFG2 (*(reg8 *) CYREG_CLKDIST_BCFG2) +#define CLKDIST_WRK0_PTR ( (reg8 *) CYREG_CLKDIST_WRK0) +#define CLKDIST_WRK0 (*(reg8 *) CYREG_CLKDIST_WRK0) +#define CLKDIST_LD_PTR ( (reg8 *) CYREG_CLKDIST_LD) +#define CLKDIST_LD (*(reg8 *) CYREG_CLKDIST_LD) +#define CLKDIST_BCFG0_PTR ( (reg8 *) CYREG_CLKDIST_BCFG0) +#define CLKDIST_BCFG0 (*(reg8 *) CYREG_CLKDIST_BCFG0) +#define CLKDIST_MSTR0_PTR ( (reg8 *) CYREG_CLKDIST_MSTR0) +#define CLKDIST_MSTR0 (*(reg8 *) CYREG_CLKDIST_MSTR0) +#define FASTCLK_IMO_CR_PTR ( (reg8 *) CYREG_FASTCLK_IMO_CR) +#define FASTCLK_IMO_CR (*(reg8 *) CYREG_FASTCLK_IMO_CR) +#define CLKDIST_CR_PTR ( (reg8 *) CYREG_CLKDIST_CR) +#define CLKDIST_CR (*(reg8 *) CYREG_CLKDIST_CR) + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from cy_boot 3.50 +*******************************************************************************/ +#define IMO_PM_ENABLE (0x10u) +#define PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0) +#define PM_ACT_CFG0 (*(reg8 *) CYREG_PM_ACT_CFG0) +#define SLOWCLK_ILO_CR0_PTR ( (reg8 *) CYREG_SLOWCLK_ILO_CR0) +#define SLOWCLK_ILO_CR0 (*(reg8 *) CYREG_SLOWCLK_ILO_CR0) +#define ILO_CONTROL_PD_MODE (0x10u) +#define ILO_CONTROL_PD_POSITION (4u) +#define ILO_CONTROL_1KHZ_ON (0x02u) +#define ILO_CONTROL_100KHZ_ON (0x04u) +#define ILO_CONTROL_33KHZ_ON (0x20u) +#define PM_TW_CFG0_PTR ( (reg8 *) CYREG_PM_TW_CFG0) +#define PM_TW_CFG0 (*(reg8 *) CYREG_PM_TW_CFG0) +#define PM_TW_CFG2_PTR ( (reg8 *) CYREG_PM_TW_CFG2) +#define PM_TW_CFG2 (*(reg8 *) CYREG_PM_TW_CFG2) +#define RESET_CR2 ((reg8 *) CYREG_RESET_CR2) +#define FASTCLK_IMO_USBCLK_ON_SET (0x40u) +#define CLOCK_IMO_3MHZ_VALUE (0x03u) +#define CLOCK_IMO_6MHZ_VALUE (0x01u) +#define CLOCK_IMO_12MHZ_VALUE (0x00u) +#define CLOCK_IMO_24MHZ_VALUE (0x02u) +#define CLOCK_IMO_48MHZ_VALUE (0x04u) +#define CLOCK_IMO_62MHZ_VALUE (0x05u) +#define CLOCK_IMO_74MHZ_VALUE (0x06u) +#define CLKDIST_DIV_POSITION (4u) +#define CLKDIST_MSTR1_DIV_CLEAR (0x0Fu) +#define SFR_USER_CPUCLK_DIV_MASK (0x0Fu) +#define CLOCK_USB_ENABLE (0x02u) +#define CLOCK_IMO_OUT_X2 (0x10u) +#define CLOCK_IMO_OUT_X1 ((uint8)(~CLOCK_IMO_OUT_X2)) +#define CLOCK_IMO2X_ECO ((uint8)(~CLOCK_IMO2X_DSI)) +#define USB_CLKDIST_CONFIG_MASK (0x03u) +#define USB_CLK_IMO2X (0x00u) +#define USB_CLK_IMO (0x01u) +#define USB_CLK_PLL (0x02u) +#define USB_CLK_DSI (0x03u) +#define USB_CLK_DIV2_ON (0x04u) +#define USB_CLK_STOP_FLAG (0x00u) +#define USB_CLK_START_FLAG (0x01u) +#define FTW_CLEAR_ALL_BITS (0x00u) +#define FTW_CLEAR_FTW_BITS (0xFCu) +#define FTW_ENABLE (0x01u) +#define PM_STBY_CFG0_PTR ( (reg8 *) CYREG_PM_STBY_CFG0) +#define PM_STBY_CFG0 (*(reg8 *) CYREG_PM_STBY_CFG0) +#define PM_AVAIL_CR2_PTR ( (reg8 *) CYREG_PM_AVAIL_CR2) +#define PM_AVAIL_CR2 (*(reg8 *) CYREG_PM_AVAIL_CR2) +#define CLKDIST_UCFG_PTR ( (reg8 *) CYREG_CLKDIST_UCFG) +#define CLKDIST_UCFG (*(reg8 *) CYREG_CLKDIST_UCFG) +#define CLKDIST_MSTR1_PTR ( (reg8 *) CYREG_CLKDIST_MSTR1) +#define CLKDIST_MSTR1 (*(reg8 *) CYREG_CLKDIST_MSTR1) +#define SFR_USER_CPUCLK_DIV_PTR ((void far *) CYREG_SFR_USER_CPUCLK_DIV) +#define IMO_TR1_PTR ( (reg8 *) CYREG_IMO_TR1) +#define IMO_TR1 (*(reg8 *) CYREG_IMO_TR1) +#define CLOCK_CONTROL ( (reg8 *) CYREG_CLKDIST_CR) +#define CY_USB_CR1_PTR ( (reg8 *) CYREG_USB_CR1 ) +#define CY_USB_CR1 (*(reg8 *) CYREG_USB_CR1 ) +#define USB_CLKDIST_CONFIG_PTR ( (reg8 *) CYREG_CLKDIST_UCFG) +#define USB_CLKDIST_CONFIG (*(reg8 *) CYREG_CLKDIST_UCFG) +#define CY_PM_ACT_CFG5_REG (* (reg8 *) CYREG_PM_ACT_CFG5 ) +#define CY_PM_ACT_CFG5_PTR ( (reg8 *) CYREG_PM_ACT_CFG5 ) +#define CY_PM_STBY_CFG5_REG (* (reg8 *) CYREG_PM_STBY_CFG5 ) +#define CY_PM_STBY_CFG5_PTR ( (reg8 *) CYREG_PM_STBY_CFG5 ) +#if(CY_PSOC3) + #define FLSHID_CUST_TABLES_IMO_3MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ) + #define FLSHID_CUST_TABLES_IMO_6MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ) + #define FLSHID_CUST_TABLES_IMO_12MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ) + #define FLSHID_CUST_TABLES_IMO_24MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ) + #define FLSHID_CUST_TABLES_IMO_67MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ) + #define FLSHID_CUST_TABLES_IMO_80MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ) + #define FLSHID_CUST_TABLES_IMO_USB_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_USB) + #define FLSHID_MFG_CFG_IMO_TR1_PTR ((void far *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u)) + #else + #define FLSHID_CUST_TABLES_IMO_3MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ) + #define FLSHID_CUST_TABLES_IMO_6MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ) + #define FLSHID_CUST_TABLES_IMO_12MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ) + #define FLSHID_CUST_TABLES_IMO_24MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ) + #define FLSHID_CUST_TABLES_IMO_67MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ) + #define FLSHID_CUST_TABLES_IMO_80MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ) + #define FLSHID_CUST_TABLES_IMO_USB_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_USB) + #define FLSHID_MFG_CFG_IMO_TR1_PTR ((reg8 *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u)) +#endif /* (CY_PSOC3) */ + + +#endif /* (CY_BOOT_CYLIB_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CySpc.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CySpc.c new file mode 100755 index 00000000..8ea15809 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CySpc.c @@ -0,0 +1,554 @@ +/******************************************************************************* +* File Name: CySpc.c +* Version 4.0 +* +* Description: +* Provides an API for the System Performance Component. +* The SPC functions are not meant to be called directly by the user +* application. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "CySpc.h" + +#define CY_SPC_KEY_ONE (0xB6u) +#define CY_SPC_KEY_TWO(x) ((uint8) (((uint16) 0xD3u) + ((uint16) (x)))) + +/* Command Codes */ +#define CY_SPC_CMD_LD_BYTE (0x00u) +#define CY_SPC_CMD_LD_MULTI_BYTE (0x01u) +#define CY_SPC_CMD_LD_ROW (0x02u) +#define CY_SPC_CMD_RD_BYTE (0x03u) +#define CY_SPC_CMD_RD_MULTI_BYTE (0x04u) +#define CY_SPC_CMD_WR_ROW (0x05u) +#define CY_SPC_CMD_WR_USER_NVL (0x06u) +#define CY_SPC_CMD_PRG_ROW (0x07u) +#define CY_SPC_CMD_ER_SECTOR (0x08u) +#define CY_SPC_CMD_ER_ALL (0x09u) +#define CY_SPC_CMD_RD_HIDDEN (0x0Au) +#define CY_SPC_CMD_PRG_PROTECT (0x0Bu) +#define CY_SPC_CMD_CHECKSUM (0x0Cu) +#define CY_SPC_CMD_DWNLD_ALGORITHM (0x0Du) +#define CY_SPC_CMD_GET_TEMP (0x0Eu) +#define CY_SPC_CMD_GET_ADC (0x0Fu) +#define CY_SPC_CMD_RD_NVL_VOLATILE (0x10u) +#define CY_SPC_CMD_SETUP_TS (0x11u) +#define CY_SPC_CMD_DISABLE_TS (0x12u) +#define CY_SPC_CMD_ER_ROW (0x13u) + +/* Enable bit in Active and Alternate Active mode templates */ +#define PM_SPC_PM_EN (0x08u) + +/* Gate calls to the SPC. */ +uint8 SpcLockState = CY_SPC_UNLOCKED; + + +#if(CY_PSOC5) + + /*************************************************************************** + * The wait-state pipeline must be enabled prior to accessing the SPC + * register interface regardless of CPU frequency. The CySpcLock() saves + * current wait-state pipeline state and enables it. The CySpcUnlock() + * function, which must be called after SPC transaction, restores original + * state. + ***************************************************************************/ + static uint32 spcWaitPipeBypass = 0u; + +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* Function Name: CySpcStart +******************************************************************************** +* Summary: +* Starts the SPC. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CySpcStart(void) +{ + /* Save current global interrupt enable and disable it */ + uint8 interruptState = CyEnterCriticalSection(); + + CY_SPC_PM_ACT_REG |= PM_SPC_PM_EN; + CY_SPC_PM_STBY_REG |= PM_SPC_PM_EN; + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CySpcStop +******************************************************************************** +* Summary: +* Stops the SPC. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CySpcStop(void) +{ + /* Save current global interrupt enable and disable it */ + uint8 interruptState = CyEnterCriticalSection(); + + CY_SPC_PM_ACT_REG &= ((uint8)(~PM_SPC_PM_EN)); + CY_SPC_PM_STBY_REG &= ((uint8)(~PM_SPC_PM_EN)); + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CySpcReadData +******************************************************************************** +* Summary: +* Reads data from the SPC. +* +* Parameters: +* uint8 buffer: +* Address to store data read. +* +* uint8 size: +* Number of bytes to read from the SPC. +* +* Return: +* uint8: +* The number of bytes read from the SPC. +* +*******************************************************************************/ +uint8 CySpcReadData(uint8 buffer[], uint8 size) +{ + uint8 i; + + for(i = 0u; i < size; i++) + { + while(!CY_SPC_DATA_READY) + { + CyDelayUs(1u); + } + buffer[i] = CY_SPC_CPU_DATA_REG; + } + + return(i); +} + + +/******************************************************************************* +* Function Name: CySpcLoadMultiByte +******************************************************************************** +* Summary: +* Loads 1 to 32 bytes of data into the row latch of a Flash/EEPROM array. +* +* Parameters: +* uint8 array: +* Id of the array. +* +* uint16 address: +* Flash/eeprom addrress +* +* uint8* buffer: +* Data to load to the row latch +* +* uint16 number: +* Number bytes to load. +* +* Return: +* CYRET_STARTED +* CYRET_CANCELED +* CYRET_LOCKED +* CYRET_BAD_PARAM +* +*******************************************************************************/ +cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)\ + +{ + cystatus status = CYRET_STARTED; + uint8 i; + + /*************************************************************************** + * Check if number is correct for array. Number must be less than + * 32 for Flash or less than 16 for EEPROM. + ***************************************************************************/ + if(((array < CY_SPC_LAST_FLASH_ARRAYID) && (size < 32u)) || + ((array > CY_SPC_LAST_FLASH_ARRAYID) && (size < 16u))) + { + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_MULTI_BYTE); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_MULTI_BYTE; + + if(CY_SPC_BUSY) + { + CY_SPC_CPU_DATA_REG = array; + CY_SPC_CPU_DATA_REG = 1u & HI8(address); + CY_SPC_CPU_DATA_REG = LO8(address); + CY_SPC_CPU_DATA_REG = ((uint8)(size - 1u)); + + for(i = 0u; i < size; i++) + { + CY_SPC_CPU_DATA_REG = buffer[i]; + } + } + else + { + status = CYRET_CANCELED; + } + } + else + { + status = CYRET_LOCKED; + } + } + else + { + status = CYRET_BAD_PARAM; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcLoadRow +******************************************************************************** +* Summary: +* Loads a row of data into the row latch of a Flash/EEPROM array. +* +* Parameters: +* uint8 array: +* Id of the array. +* +* uint8* buffer: +* Data to be loaded to the row latch +* +* uint8 size: +* The number of data bytes that the SPC expects to be written. Depends on the +* type of the array and, if the array is Flash, whether ECC is being enabled +* or not. There are following values: flash row latch size with ECC enabled, +* flash row latch size with ECC disabled and EEPROM row latch size. +* +* Return: +* CYRET_STARTED +* CYRET_CANCELED +* CYRET_LOCKED +* +*******************************************************************************/ +cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size) +{ + cystatus status = CYRET_STARTED; + uint16 i; + + /* Make sure the SPC is ready to accept command */ + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_ROW); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_ROW; + + /* Make sure the command was accepted */ + if(CY_SPC_BUSY) + { + CY_SPC_CPU_DATA_REG = array; + + for(i = 0u; i < size; i++) + { + CY_SPC_CPU_DATA_REG = buffer[i]; + } + } + else + { + status = CYRET_CANCELED; + } + } + else + { + status = CYRET_LOCKED; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcWriteRow +******************************************************************************** +* Summary: +* Erases then programs a row in Flash/EEPROM with data in row latch. +* +* Parameters: +* uint8 array: +* Id of the array. +* +* uint16 address: +* flash/eeprom addrress +* +* uint8 tempPolarity: +* temperature polarity. +* 1: the Temp Magnitude is interpreted as a positive value +* 0: the Temp Magnitude is interpreted as a negative value +* +* uint8 tempMagnitude: +* temperature magnitude. +* +* Return: +* CYRET_STARTED +* CYRET_CANCELED +* CYRET_LOCKED +* +*******************************************************************************/ +cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\ + +{ + cystatus status = CYRET_STARTED; + + /* Make sure the SPC is ready to accept command */ + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_WR_ROW); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_WR_ROW; + + /* Make sure the command was accepted */ + if(CY_SPC_BUSY) + { + CY_SPC_CPU_DATA_REG = array; + CY_SPC_CPU_DATA_REG = HI8(address); + CY_SPC_CPU_DATA_REG = LO8(address); + CY_SPC_CPU_DATA_REG = tempPolarity; + CY_SPC_CPU_DATA_REG = tempMagnitude; + } + else + { + status = CYRET_CANCELED; + } + } + else + { + status = CYRET_LOCKED; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcEraseSector +******************************************************************************** +* Summary: +* Erases all data in the addressed sector (block of 64 rows). +* +* Parameters: +* uint8 array: +* Id of the array. +* +* uint8 sectorNumber: +* Zero based sector number within Flash/EEPROM array +* +* Return: +* CYRET_STARTED +* CYRET_CANCELED +* CYRET_LOCKED +* +*******************************************************************************/ +cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber) +{ + cystatus status = CYRET_STARTED; + + /* Make sure the SPC is ready to accept command */ + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_ER_SECTOR); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_ER_SECTOR; + + /* Make sure the command was accepted */ + if(CY_SPC_BUSY) + { + CY_SPC_CPU_DATA_REG = array; + CY_SPC_CPU_DATA_REG = sectorNumber; + } + else + { + status = CYRET_CANCELED; + } + } + else + { + status = CYRET_LOCKED; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcGetTemp +******************************************************************************** +* Summary: +* Returns the internal die temperature +* +* Parameters: +* uint8 numSamples: +* Number of samples. Valid values are 1-5, resulting in 2 - 32 samples +* respectively. +* +* uint16 timerPeriod: +* Number of ADC ACLK cycles. A valid 14 bit value is accepted, higher 2 bits +* of 16 bit values are ignored. +* +* uint8 clkDivSelect: +* ADC ACLK clock divide value. Valid values are 2 - 225. +* +* Return: +* CYRET_STARTED +* CYRET_CANCELED +* CYRET_LOCKED +* +*******************************************************************************/ +cystatus CySpcGetTemp(uint8 numSamples) +{ + cystatus status = CYRET_STARTED; + + /* Make sure the SPC is ready to accept command */ + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_GET_TEMP); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_GET_TEMP; + + /* Make sure the command was accepted */ + if(CY_SPC_BUSY) + { + CY_SPC_CPU_DATA_REG = numSamples; + } + else + { + status = CYRET_CANCELED; + } + } + else + { + status = CYRET_LOCKED; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcLock +******************************************************************************** +* Summary: +* Locks the SPC so it can not be used by someone else: +* - Saves wait-pipeline enable state and enable pipeline (PSoC5) +* +* Parameters: +* Note +* +* Return: +* CYRET_SUCCESS - if the resource was free. +* CYRET_LOCKED - if the SPC is in use. +* +*******************************************************************************/ +cystatus CySpcLock(void) +{ + cystatus status = CYRET_LOCKED; + uint8 interruptState; + + /* Enter critical section */ + interruptState = CyEnterCriticalSection(); + + if(CY_SPC_UNLOCKED == SpcLockState) + { + SpcLockState = CY_SPC_LOCKED; + status = CYRET_SUCCESS; + + #if(CY_PSOC5) + + if(0u != (CY_SPC_CPU_WAITPIPE_REG & CY_SPC_CPU_WAITPIPE_BYPASS)) + { + /* Enable pipeline registers */ + CY_SPC_CPU_WAITPIPE_REG &= ((uint32)(~CY_SPC_CPU_WAITPIPE_BYPASS)); + + /* At least 2 NOP instructions are recommended */ + CY_NOP; + CY_NOP; + CY_NOP; + + spcWaitPipeBypass = CY_SPC_CPU_WAITPIPE_BYPASS; + } + + #endif /* (CY_PSOC5) */ + } + + /* Exit critical section */ + CyExitCriticalSection(interruptState); + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcUnlock +******************************************************************************** +* Summary: +* Unlocks the SPC so it can be used by someone else: +* - Restores wait-pipeline enable state (PSoC5) +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CySpcUnlock(void) +{ + uint8 interruptState; + + /* Enter critical section */ + interruptState = CyEnterCriticalSection(); + + /* Release the SPC object */ + SpcLockState = CY_SPC_UNLOCKED; + + #if(CY_PSOC5) + + if(CY_SPC_CPU_WAITPIPE_BYPASS == spcWaitPipeBypass) + { + /* Force to bypass pipeline registers */ + CY_SPC_CPU_WAITPIPE_REG |= CY_SPC_CPU_WAITPIPE_BYPASS; + + /* At least 2 NOP instructions are recommended */ + CY_NOP; + CY_NOP; + CY_NOP; + + spcWaitPipeBypass = 0u; + } + + #endif /* (CY_PSOC5) */ + + /* Exit critical section */ + CyExitCriticalSection(interruptState); +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CySpc.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CySpc.h new file mode 100755 index 00000000..3757e132 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/CySpc.h @@ -0,0 +1,154 @@ +/******************************************************************************* +* File Name: CySpc.c +* Version 4.0 +* +* Description: +* Provides definitions for the System Performance Component API. +* The SPC functions are not meant to be called directly by the user +* application. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYSPC_H) +#define CY_BOOT_CYSPC_H + +#include "cytypes.h" +#include "CyLib.h" +#include "cydevice_trm.h" + + +/*************************************** +* Global Variables +***************************************/ +extern uint8 SpcLockState; + + +/*************************************** +* Function Prototypes +***************************************/ +void CySpcStart(void); +void CySpcStop(void); +uint8 CySpcReadData(uint8 buffer[], uint8 size); +cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)\ +; +cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size); +cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\ +; +cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber); +cystatus CySpcGetTemp(uint8 numSamples); +cystatus CySpcLock(void); +void CySpcUnlock(void); + + +/*************************************** +* API Constants +***************************************/ + +#define CY_SPC_LOCKED (0x01u) +#define CY_SPC_UNLOCKED (0x00u) + +/******************************************************************************* +* The Array ID indicates the unique ID of the SONOS array being accessed: +* - 0x00-0x3E : Flash Arrays +* - 0x3F : Selects all Flash arrays simultaneously +* - 0x40-0x7F : Embedded EEPROM Arrays +*******************************************************************************/ +#define CY_SPC_FIRST_FLASH_ARRAYID (0x00u) +#define CY_SPC_LAST_FLASH_ARRAYID (0x3Fu) +#define CY_SPC_FIRST_EE_ARRAYID (0x40u) +#define CY_SPC_LAST_EE_ARRAYID (0x7Fu) + + +#define CY_SPC_STATUS_DATA_READY_MASK (0x01u) +#define CY_SPC_STATUS_IDLE_MASK (0x02u) +#define CY_SPC_STATUS_CODE_MASK (0xFCu) +#define CY_SPC_STATUS_CODE_SHIFT (0x02u) + +/* Status codes for the SPC. */ +#define CY_SPC_STATUS_SUCCESS (0x00u) /* Operation Successful */ +#define CY_SPC_STATUS_INVALID_ARRAY_ID (0x01u) /* Invalid Array ID for given command */ +#define CY_SPC_STATUS_INVALID_2BYTEKEY (0x02u) /* Invalid 2-byte key */ +#define CY_SPC_STATUS_ARRAY_ASLEEP (0x03u) /* Addressed Array is Asleep */ +#define CY_SPC_STATUS_EXTERN_ACCESS (0x04u) /* External Access Failure (SPC is not in external access mode) */ +#define CY_SPC_STATUS_INVALID_NUMBER (0x05u) /* Invalid 'N' Value for given command */ +#define CY_SPC_STATUS_TEST_MODE (0x06u) /* Test Mode Failure (SPC is not in test mode) */ +#define CY_SPC_STATUS_ALG_CSUM (0x07u) /* Smart Write Algorithm Checksum Failure */ +#define CY_SPC_STATUS_PARAM_CSUM (0x08u) /* Smart Write Parameter Checksum Failure */ +#define CY_SPC_STATUS_PROTECTION (0x09u) /* Protection Check Failure */ +#define CY_SPC_STATUS_ADDRESS_PARAM (0x0Au) /* Invalid Address parameter for the given command */ +#define CY_SPC_STATUS_COMMAND_CODE (0x0Bu) /* Invalid Command Code */ +#define CY_SPC_STATUS_ROW_ID (0x0Cu) /* Invalid Row ID parameter for given command */ +#define CY_SPC_STATUS_TADC_INPUT (0x0Du) /* Invalid input value for Get Temp & Get ADC commands */ +#define CY_SPC_STATUS_BUSY (0xFFu) /* SPC is busy */ + +#if(CY_PSOC5) + + /* Wait-state pipeline */ + #define CY_SPC_CPU_WAITPIPE_BYPASS ((uint32)0x01u) + +#endif /* (CY_PSOC5) */ + + +/*************************************** +* Registers +***************************************/ + +/* SPC CPU Data Register */ +#define CY_SPC_CPU_DATA_REG (* (reg8 *) CYREG_SPC_CPU_DATA ) +#define CY_SPC_CPU_DATA_PTR ( (reg8 *) CYREG_SPC_CPU_DATA ) + +/* SPC Status Register */ +#define CY_SPC_STATUS_REG (* (reg8 *) CYREG_SPC_SR ) +#define CY_SPC_STATUS_PTR ( (reg8 *) CYREG_SPC_SR ) + +/* Active Power Mode Configuration Register 0 */ +#define CY_SPC_PM_ACT_REG (* (reg8 *) CYREG_PM_ACT_CFG0 ) +#define CY_SPC_PM_ACT_PTR ( (reg8 *) CYREG_PM_ACT_CFG0 ) + +/* Standby Power Mode Configuration Register 0 */ +#define CY_SPC_PM_STBY_REG (* (reg8 *) CYREG_PM_STBY_CFG0 ) +#define CY_SPC_PM_STBY_PTR ( (reg8 *) CYREG_PM_STBY_CFG0 ) + +#if(CY_PSOC5) + + /* Wait State Pipeline */ + #define CY_SPC_CPU_WAITPIPE_REG (* (reg32 *) CYREG_PANTHER_WAITPIPE ) + #define CY_SPC_CPU_WAITPIPE_PTR ( (reg32 *) CYREG_PANTHER_WAITPIPE ) + +#endif /* (CY_PSOC5) */ + + +/*************************************** +* Macros +***************************************/ +#define CY_SPC_IDLE (0u != (CY_SPC_STATUS_REG & CY_SPC_STATUS_IDLE_MASK)) +#define CY_SPC_BUSY (0u == (CY_SPC_STATUS_REG & CY_SPC_STATUS_IDLE_MASK)) +#define CY_SPC_DATA_READY (0u != (CY_SPC_STATUS_REG & CY_SPC_STATUS_DATA_READY_MASK)) + +/* SPC must be in idle state in order to obtain correct status */ +#define CY_SPC_READ_STATUS (CY_SPC_IDLE ? \ + ((uint8)(CY_SPC_STATUS_REG >> CY_SPC_STATUS_CODE_SHIFT)) : \ + ((uint8) CY_SPC_STATUS_BUSY)) + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from cy_boot 3.0 +*******************************************************************************/ +#define FIRST_FLASH_ARRAYID (CY_SPC_FIRST_FLASH_ARRAYID) +#define LAST_FLASH_ARRAYID (CY_SPC_LAST_FLASH_ARRAYID) +#define FIRST_EE_ARRAYID (CY_SPC_FIRST_EE_ARRAYID) +#define LAST_EE_ARRAYID (CY_SPC_LAST_EE_ARRAYID) +#define SIZEOF_ECC_ROW (CYDEV_ECC_ROW_SIZE) +#define SIZEOF_FLASH_ROW (CYDEV_FLS_ROW_SIZE) +#define SIZEOF_EEPROM_ROW (CYDEV_EEPROM_ROW_SIZE) + + +#endif /* (CY_BOOT_CYSPC_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/LED1.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/LED1.c new file mode 100755 index 00000000..abb76427 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/LED1.c @@ -0,0 +1,137 @@ +/******************************************************************************* +* File Name: LED1.c +* Version 1.90 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "LED1.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + LED1__PORT == 15 && ((LED1__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: LED1_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void LED1_Write(uint8 value) +{ + uint8 staticBits = (LED1_DR & (uint8)(~LED1_MASK)); + LED1_DR = staticBits | ((uint8)(value << LED1_SHIFT) & LED1_MASK); +} + + +/******************************************************************************* +* Function Name: LED1_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to this drive mode. +* +* Return: +* None +* +*******************************************************************************/ +void LED1_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(LED1_0, mode); +} + + +/******************************************************************************* +* Function Name: LED1_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro LED1_ReadPS calls this function. +* +*******************************************************************************/ +uint8 LED1_Read(void) +{ + return (LED1_PS & LED1_MASK) >> LED1_SHIFT; +} + + +/******************************************************************************* +* Function Name: LED1_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 LED1_ReadDataReg(void) +{ + return (LED1_DR & LED1_MASK) >> LED1_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(LED1_INTSTAT) + + /******************************************************************************* + * Function Name: LED1_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 LED1_ClearInterrupt(void) + { + return (LED1_INTSTAT & LED1_MASK) >> LED1_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/LED1.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/LED1.h new file mode 100755 index 00000000..740e999d --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/LED1.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: LED1.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_LED1_H) /* Pins LED1_H */ +#define CY_PINS_LED1_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "LED1_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + LED1__PORT == 15 && ((LED1__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void LED1_Write(uint8 value) ; +void LED1_SetDriveMode(uint8 mode) ; +uint8 LED1_ReadDataReg(void) ; +uint8 LED1_Read(void) ; +uint8 LED1_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define LED1_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define LED1_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define LED1_DM_RES_UP PIN_DM_RES_UP +#define LED1_DM_RES_DWN PIN_DM_RES_DWN +#define LED1_DM_OD_LO PIN_DM_OD_LO +#define LED1_DM_OD_HI PIN_DM_OD_HI +#define LED1_DM_STRONG PIN_DM_STRONG +#define LED1_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define LED1_MASK LED1__MASK +#define LED1_SHIFT LED1__SHIFT +#define LED1_WIDTH 1u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define LED1_PS (* (reg8 *) LED1__PS) +/* Data Register */ +#define LED1_DR (* (reg8 *) LED1__DR) +/* Port Number */ +#define LED1_PRT_NUM (* (reg8 *) LED1__PRT) +/* Connect to Analog Globals */ +#define LED1_AG (* (reg8 *) LED1__AG) +/* Analog MUX bux enable */ +#define LED1_AMUX (* (reg8 *) LED1__AMUX) +/* Bidirectional Enable */ +#define LED1_BIE (* (reg8 *) LED1__BIE) +/* Bit-mask for Aliased Register Access */ +#define LED1_BIT_MASK (* (reg8 *) LED1__BIT_MASK) +/* Bypass Enable */ +#define LED1_BYP (* (reg8 *) LED1__BYP) +/* Port wide control signals */ +#define LED1_CTL (* (reg8 *) LED1__CTL) +/* Drive Modes */ +#define LED1_DM0 (* (reg8 *) LED1__DM0) +#define LED1_DM1 (* (reg8 *) LED1__DM1) +#define LED1_DM2 (* (reg8 *) LED1__DM2) +/* Input Buffer Disable Override */ +#define LED1_INP_DIS (* (reg8 *) LED1__INP_DIS) +/* LCD Common or Segment Drive */ +#define LED1_LCD_COM_SEG (* (reg8 *) LED1__LCD_COM_SEG) +/* Enable Segment LCD */ +#define LED1_LCD_EN (* (reg8 *) LED1__LCD_EN) +/* Slew Rate Control */ +#define LED1_SLW (* (reg8 *) LED1__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define LED1_PRTDSI__CAPS_SEL (* (reg8 *) LED1__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define LED1_PRTDSI__DBL_SYNC_IN (* (reg8 *) LED1__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define LED1_PRTDSI__OE_SEL0 (* (reg8 *) LED1__PRTDSI__OE_SEL0) +#define LED1_PRTDSI__OE_SEL1 (* (reg8 *) LED1__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define LED1_PRTDSI__OUT_SEL0 (* (reg8 *) LED1__PRTDSI__OUT_SEL0) +#define LED1_PRTDSI__OUT_SEL1 (* (reg8 *) LED1__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define LED1_PRTDSI__SYNC_OUT (* (reg8 *) LED1__PRTDSI__SYNC_OUT) + + +#if defined(LED1__INTSTAT) /* Interrupt Registers */ + + #define LED1_INTSTAT (* (reg8 *) LED1__INTSTAT) + #define LED1_SNAP (* (reg8 *) LED1__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_LED1_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/LED1_aliases.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/LED1_aliases.h new file mode 100755 index 00000000..02aa04d4 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/LED1_aliases.h @@ -0,0 +1,32 @@ +/******************************************************************************* +* File Name: LED1.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_LED1_ALIASES_H) /* Pins LED1_ALIASES_H */ +#define CY_PINS_LED1_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define LED1_0 LED1__0__PC + +#endif /* End Pins LED1_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_ATN.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_ATN.c new file mode 100755 index 00000000..327ddb73 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_ATN.c @@ -0,0 +1,137 @@ +/******************************************************************************* +* File Name: SCSI_ATN.c +* Version 1.90 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SCSI_ATN.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + SCSI_ATN__PORT == 15 && ((SCSI_ATN__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: SCSI_ATN_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_ATN_Write(uint8 value) +{ + uint8 staticBits = (SCSI_ATN_DR & (uint8)(~SCSI_ATN_MASK)); + SCSI_ATN_DR = staticBits | ((uint8)(value << SCSI_ATN_SHIFT) & SCSI_ATN_MASK); +} + + +/******************************************************************************* +* Function Name: SCSI_ATN_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to this drive mode. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_ATN_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(SCSI_ATN_0, mode); +} + + +/******************************************************************************* +* Function Name: SCSI_ATN_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro SCSI_ATN_ReadPS calls this function. +* +*******************************************************************************/ +uint8 SCSI_ATN_Read(void) +{ + return (SCSI_ATN_PS & SCSI_ATN_MASK) >> SCSI_ATN_SHIFT; +} + + +/******************************************************************************* +* Function Name: SCSI_ATN_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 SCSI_ATN_ReadDataReg(void) +{ + return (SCSI_ATN_DR & SCSI_ATN_MASK) >> SCSI_ATN_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(SCSI_ATN_INTSTAT) + + /******************************************************************************* + * Function Name: SCSI_ATN_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 SCSI_ATN_ClearInterrupt(void) + { + return (SCSI_ATN_INTSTAT & SCSI_ATN_MASK) >> SCSI_ATN_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_ATN.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_ATN.h new file mode 100755 index 00000000..2c89fad7 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_ATN.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: SCSI_ATN.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SCSI_ATN_H) /* Pins SCSI_ATN_H */ +#define CY_PINS_SCSI_ATN_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SCSI_ATN_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SCSI_ATN__PORT == 15 && ((SCSI_ATN__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void SCSI_ATN_Write(uint8 value) ; +void SCSI_ATN_SetDriveMode(uint8 mode) ; +uint8 SCSI_ATN_ReadDataReg(void) ; +uint8 SCSI_ATN_Read(void) ; +uint8 SCSI_ATN_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define SCSI_ATN_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define SCSI_ATN_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define SCSI_ATN_DM_RES_UP PIN_DM_RES_UP +#define SCSI_ATN_DM_RES_DWN PIN_DM_RES_DWN +#define SCSI_ATN_DM_OD_LO PIN_DM_OD_LO +#define SCSI_ATN_DM_OD_HI PIN_DM_OD_HI +#define SCSI_ATN_DM_STRONG PIN_DM_STRONG +#define SCSI_ATN_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define SCSI_ATN_MASK SCSI_ATN__MASK +#define SCSI_ATN_SHIFT SCSI_ATN__SHIFT +#define SCSI_ATN_WIDTH 1u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SCSI_ATN_PS (* (reg8 *) SCSI_ATN__PS) +/* Data Register */ +#define SCSI_ATN_DR (* (reg8 *) SCSI_ATN__DR) +/* Port Number */ +#define SCSI_ATN_PRT_NUM (* (reg8 *) SCSI_ATN__PRT) +/* Connect to Analog Globals */ +#define SCSI_ATN_AG (* (reg8 *) SCSI_ATN__AG) +/* Analog MUX bux enable */ +#define SCSI_ATN_AMUX (* (reg8 *) SCSI_ATN__AMUX) +/* Bidirectional Enable */ +#define SCSI_ATN_BIE (* (reg8 *) SCSI_ATN__BIE) +/* Bit-mask for Aliased Register Access */ +#define SCSI_ATN_BIT_MASK (* (reg8 *) SCSI_ATN__BIT_MASK) +/* Bypass Enable */ +#define SCSI_ATN_BYP (* (reg8 *) SCSI_ATN__BYP) +/* Port wide control signals */ +#define SCSI_ATN_CTL (* (reg8 *) SCSI_ATN__CTL) +/* Drive Modes */ +#define SCSI_ATN_DM0 (* (reg8 *) SCSI_ATN__DM0) +#define SCSI_ATN_DM1 (* (reg8 *) SCSI_ATN__DM1) +#define SCSI_ATN_DM2 (* (reg8 *) SCSI_ATN__DM2) +/* Input Buffer Disable Override */ +#define SCSI_ATN_INP_DIS (* (reg8 *) SCSI_ATN__INP_DIS) +/* LCD Common or Segment Drive */ +#define SCSI_ATN_LCD_COM_SEG (* (reg8 *) SCSI_ATN__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SCSI_ATN_LCD_EN (* (reg8 *) SCSI_ATN__LCD_EN) +/* Slew Rate Control */ +#define SCSI_ATN_SLW (* (reg8 *) SCSI_ATN__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SCSI_ATN_PRTDSI__CAPS_SEL (* (reg8 *) SCSI_ATN__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SCSI_ATN_PRTDSI__DBL_SYNC_IN (* (reg8 *) SCSI_ATN__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SCSI_ATN_PRTDSI__OE_SEL0 (* (reg8 *) SCSI_ATN__PRTDSI__OE_SEL0) +#define SCSI_ATN_PRTDSI__OE_SEL1 (* (reg8 *) SCSI_ATN__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SCSI_ATN_PRTDSI__OUT_SEL0 (* (reg8 *) SCSI_ATN__PRTDSI__OUT_SEL0) +#define SCSI_ATN_PRTDSI__OUT_SEL1 (* (reg8 *) SCSI_ATN__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SCSI_ATN_PRTDSI__SYNC_OUT (* (reg8 *) SCSI_ATN__PRTDSI__SYNC_OUT) + + +#if defined(SCSI_ATN__INTSTAT) /* Interrupt Registers */ + + #define SCSI_ATN_INTSTAT (* (reg8 *) SCSI_ATN__INTSTAT) + #define SCSI_ATN_SNAP (* (reg8 *) SCSI_ATN__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SCSI_ATN_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_ATN_aliases.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_ATN_aliases.h new file mode 100755 index 00000000..46aff1f8 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_ATN_aliases.h @@ -0,0 +1,34 @@ +/******************************************************************************* +* File Name: SCSI_ATN.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SCSI_ATN_ALIASES_H) /* Pins SCSI_ATN_ALIASES_H */ +#define CY_PINS_SCSI_ATN_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SCSI_ATN_0 SCSI_ATN__0__PC + +#define SCSI_ATN_INT SCSI_ATN__INT__PC + +#endif /* End Pins SCSI_ATN_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.c new file mode 100755 index 00000000..87f82734 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.c @@ -0,0 +1,63 @@ +/******************************************************************************* +* File Name: SCSI_CTL_IO.c +* Version 1.70 +* +* Description: +* This file contains API to enable firmware control of a Control Register. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SCSI_CTL_IO.h" + +#if !defined(SCSI_CTL_IO_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */ + +/******************************************************************************* +* Function Name: SCSI_CTL_IO_Write +******************************************************************************** +* +* Summary: +* Write a byte to the Control Register. +* +* Parameters: +* control: The value to be assigned to the Control Register. +* +* Return: +* None. +* +*******************************************************************************/ +void SCSI_CTL_IO_Write(uint8 control) +{ + SCSI_CTL_IO_Control = control; +} + + +/******************************************************************************* +* Function Name: SCSI_CTL_IO_Read +******************************************************************************** +* +* Summary: +* Reads the current value assigned to the Control Register. +* +* Parameters: +* None. +* +* Return: +* Returns the current value in the Control Register. +* +*******************************************************************************/ +uint8 SCSI_CTL_IO_Read(void) +{ + return SCSI_CTL_IO_Control; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.h new file mode 100755 index 00000000..d140e57d --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.h @@ -0,0 +1,42 @@ +/******************************************************************************* +* File Name: SCSI_CTL_IO.h +* Version 1.70 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CONTROL_REG_SCSI_CTL_IO_H) /* CY_CONTROL_REG_SCSI_CTL_IO_H */ +#define CY_CONTROL_REG_SCSI_CTL_IO_H + +#include "cytypes.h" + + +/*************************************** +* Function Prototypes +***************************************/ + +void SCSI_CTL_IO_Write(uint8 control) ; +uint8 SCSI_CTL_IO_Read(void) ; + + +/*************************************** +* Registers +***************************************/ + +/* Control Register */ +#define SCSI_CTL_IO_Control (* (reg8 *) SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG ) +#define SCSI_CTL_IO_Control_PTR ( (reg8 *) SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG ) + +#endif /* End CY_CONTROL_REG_SCSI_CTL_IO_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_In_DBx_aliases.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_In_DBx_aliases.h new file mode 100755 index 00000000..97e00b20 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_In_DBx_aliases.h @@ -0,0 +1,48 @@ +/******************************************************************************* +* File Name: SCSI_In_DBx.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SCSI_In_DBx_ALIASES_H) /* Pins SCSI_In_DBx_ALIASES_H */ +#define CY_PINS_SCSI_In_DBx_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SCSI_In_DBx_0 SCSI_In_DBx__0__PC +#define SCSI_In_DBx_1 SCSI_In_DBx__1__PC +#define SCSI_In_DBx_2 SCSI_In_DBx__2__PC +#define SCSI_In_DBx_3 SCSI_In_DBx__3__PC +#define SCSI_In_DBx_4 SCSI_In_DBx__4__PC +#define SCSI_In_DBx_5 SCSI_In_DBx__5__PC +#define SCSI_In_DBx_6 SCSI_In_DBx__6__PC +#define SCSI_In_DBx_7 SCSI_In_DBx__7__PC + +#define SCSI_In_DBx_DB0 SCSI_In_DBx__DB0__PC +#define SCSI_In_DBx_DB1 SCSI_In_DBx__DB1__PC +#define SCSI_In_DBx_DB2 SCSI_In_DBx__DB2__PC +#define SCSI_In_DBx_DB3 SCSI_In_DBx__DB3__PC +#define SCSI_In_DBx_DB4 SCSI_In_DBx__DB4__PC +#define SCSI_In_DBx_DB5 SCSI_In_DBx__DB5__PC +#define SCSI_In_DBx_DB6 SCSI_In_DBx__DB6__PC +#define SCSI_In_DBx_DB7 SCSI_In_DBx__DB7__PC + +#endif /* End Pins SCSI_In_DBx_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h new file mode 100755 index 00000000..3447a104 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h @@ -0,0 +1,48 @@ +/******************************************************************************* +* File Name: SCSI_In.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SCSI_In_ALIASES_H) /* Pins SCSI_In_ALIASES_H */ +#define CY_PINS_SCSI_In_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SCSI_In_0 SCSI_In__0__PC +#define SCSI_In_1 SCSI_In__1__PC +#define SCSI_In_2 SCSI_In__2__PC +#define SCSI_In_3 SCSI_In__3__PC +#define SCSI_In_4 SCSI_In__4__PC +#define SCSI_In_5 SCSI_In__5__PC +#define SCSI_In_6 SCSI_In__6__PC +#define SCSI_In_7 SCSI_In__7__PC + +#define SCSI_In_DBP SCSI_In__DBP__PC +#define SCSI_In_BSY SCSI_In__BSY__PC +#define SCSI_In_ACK SCSI_In__ACK__PC +#define SCSI_In_MSG SCSI_In__MSG__PC +#define SCSI_In_SEL SCSI_In__SEL__PC +#define SCSI_In_CD SCSI_In__CD__PC +#define SCSI_In_REQ SCSI_In__REQ__PC +#define SCSI_In_IO SCSI_In__IO__PC + +#endif /* End Pins SCSI_In_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h new file mode 100755 index 00000000..cab58f9f --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h @@ -0,0 +1,48 @@ +/******************************************************************************* +* File Name: SCSI_Out_DBx.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SCSI_Out_DBx_ALIASES_H) /* Pins SCSI_Out_DBx_ALIASES_H */ +#define CY_PINS_SCSI_Out_DBx_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SCSI_Out_DBx_0 SCSI_Out_DBx__0__PC +#define SCSI_Out_DBx_1 SCSI_Out_DBx__1__PC +#define SCSI_Out_DBx_2 SCSI_Out_DBx__2__PC +#define SCSI_Out_DBx_3 SCSI_Out_DBx__3__PC +#define SCSI_Out_DBx_4 SCSI_Out_DBx__4__PC +#define SCSI_Out_DBx_5 SCSI_Out_DBx__5__PC +#define SCSI_Out_DBx_6 SCSI_Out_DBx__6__PC +#define SCSI_Out_DBx_7 SCSI_Out_DBx__7__PC + +#define SCSI_Out_DBx_DB0 SCSI_Out_DBx__DB0__PC +#define SCSI_Out_DBx_DB1 SCSI_Out_DBx__DB1__PC +#define SCSI_Out_DBx_DB2 SCSI_Out_DBx__DB2__PC +#define SCSI_Out_DBx_DB3 SCSI_Out_DBx__DB3__PC +#define SCSI_Out_DBx_DB4 SCSI_Out_DBx__DB4__PC +#define SCSI_Out_DBx_DB5 SCSI_Out_DBx__DB5__PC +#define SCSI_Out_DBx_DB6 SCSI_Out_DBx__DB6__PC +#define SCSI_Out_DBx_DB7 SCSI_Out_DBx__DB7__PC + +#endif /* End Pins SCSI_Out_DBx_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h new file mode 100755 index 00000000..cd457bc8 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h @@ -0,0 +1,52 @@ +/******************************************************************************* +* File Name: SCSI_Out.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SCSI_Out_ALIASES_H) /* Pins SCSI_Out_ALIASES_H */ +#define CY_PINS_SCSI_Out_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SCSI_Out_0 SCSI_Out__0__PC +#define SCSI_Out_1 SCSI_Out__1__PC +#define SCSI_Out_2 SCSI_Out__2__PC +#define SCSI_Out_3 SCSI_Out__3__PC +#define SCSI_Out_4 SCSI_Out__4__PC +#define SCSI_Out_5 SCSI_Out__5__PC +#define SCSI_Out_6 SCSI_Out__6__PC +#define SCSI_Out_7 SCSI_Out__7__PC +#define SCSI_Out_8 SCSI_Out__8__PC +#define SCSI_Out_9 SCSI_Out__9__PC + +#define SCSI_Out_DBP_raw SCSI_Out__DBP_raw__PC +#define SCSI_Out_ATN SCSI_Out__ATN__PC +#define SCSI_Out_BSY SCSI_Out__BSY__PC +#define SCSI_Out_ACK SCSI_Out__ACK__PC +#define SCSI_Out_RST SCSI_Out__RST__PC +#define SCSI_Out_MSG SCSI_Out__MSG__PC +#define SCSI_Out_SEL SCSI_Out__SEL__PC +#define SCSI_Out_CD SCSI_Out__CD__PC +#define SCSI_Out_REQ SCSI_Out__REQ__PC +#define SCSI_Out_IO_raw SCSI_Out__IO_raw__PC + +#endif /* End Pins SCSI_Out_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_RST.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_RST.c new file mode 100755 index 00000000..0044ffd2 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_RST.c @@ -0,0 +1,137 @@ +/******************************************************************************* +* File Name: SCSI_RST.c +* Version 1.90 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SCSI_RST.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + SCSI_RST__PORT == 15 && ((SCSI_RST__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: SCSI_RST_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RST_Write(uint8 value) +{ + uint8 staticBits = (SCSI_RST_DR & (uint8)(~SCSI_RST_MASK)); + SCSI_RST_DR = staticBits | ((uint8)(value << SCSI_RST_SHIFT) & SCSI_RST_MASK); +} + + +/******************************************************************************* +* Function Name: SCSI_RST_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to this drive mode. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RST_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(SCSI_RST_0, mode); +} + + +/******************************************************************************* +* Function Name: SCSI_RST_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro SCSI_RST_ReadPS calls this function. +* +*******************************************************************************/ +uint8 SCSI_RST_Read(void) +{ + return (SCSI_RST_PS & SCSI_RST_MASK) >> SCSI_RST_SHIFT; +} + + +/******************************************************************************* +* Function Name: SCSI_RST_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 SCSI_RST_ReadDataReg(void) +{ + return (SCSI_RST_DR & SCSI_RST_MASK) >> SCSI_RST_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(SCSI_RST_INTSTAT) + + /******************************************************************************* + * Function Name: SCSI_RST_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 SCSI_RST_ClearInterrupt(void) + { + return (SCSI_RST_INTSTAT & SCSI_RST_MASK) >> SCSI_RST_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_RST.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_RST.h new file mode 100755 index 00000000..c0f868a9 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_RST.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: SCSI_RST.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SCSI_RST_H) /* Pins SCSI_RST_H */ +#define CY_PINS_SCSI_RST_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SCSI_RST_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SCSI_RST__PORT == 15 && ((SCSI_RST__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void SCSI_RST_Write(uint8 value) ; +void SCSI_RST_SetDriveMode(uint8 mode) ; +uint8 SCSI_RST_ReadDataReg(void) ; +uint8 SCSI_RST_Read(void) ; +uint8 SCSI_RST_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define SCSI_RST_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define SCSI_RST_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define SCSI_RST_DM_RES_UP PIN_DM_RES_UP +#define SCSI_RST_DM_RES_DWN PIN_DM_RES_DWN +#define SCSI_RST_DM_OD_LO PIN_DM_OD_LO +#define SCSI_RST_DM_OD_HI PIN_DM_OD_HI +#define SCSI_RST_DM_STRONG PIN_DM_STRONG +#define SCSI_RST_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define SCSI_RST_MASK SCSI_RST__MASK +#define SCSI_RST_SHIFT SCSI_RST__SHIFT +#define SCSI_RST_WIDTH 1u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SCSI_RST_PS (* (reg8 *) SCSI_RST__PS) +/* Data Register */ +#define SCSI_RST_DR (* (reg8 *) SCSI_RST__DR) +/* Port Number */ +#define SCSI_RST_PRT_NUM (* (reg8 *) SCSI_RST__PRT) +/* Connect to Analog Globals */ +#define SCSI_RST_AG (* (reg8 *) SCSI_RST__AG) +/* Analog MUX bux enable */ +#define SCSI_RST_AMUX (* (reg8 *) SCSI_RST__AMUX) +/* Bidirectional Enable */ +#define SCSI_RST_BIE (* (reg8 *) SCSI_RST__BIE) +/* Bit-mask for Aliased Register Access */ +#define SCSI_RST_BIT_MASK (* (reg8 *) SCSI_RST__BIT_MASK) +/* Bypass Enable */ +#define SCSI_RST_BYP (* (reg8 *) SCSI_RST__BYP) +/* Port wide control signals */ +#define SCSI_RST_CTL (* (reg8 *) SCSI_RST__CTL) +/* Drive Modes */ +#define SCSI_RST_DM0 (* (reg8 *) SCSI_RST__DM0) +#define SCSI_RST_DM1 (* (reg8 *) SCSI_RST__DM1) +#define SCSI_RST_DM2 (* (reg8 *) SCSI_RST__DM2) +/* Input Buffer Disable Override */ +#define SCSI_RST_INP_DIS (* (reg8 *) SCSI_RST__INP_DIS) +/* LCD Common or Segment Drive */ +#define SCSI_RST_LCD_COM_SEG (* (reg8 *) SCSI_RST__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SCSI_RST_LCD_EN (* (reg8 *) SCSI_RST__LCD_EN) +/* Slew Rate Control */ +#define SCSI_RST_SLW (* (reg8 *) SCSI_RST__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SCSI_RST_PRTDSI__CAPS_SEL (* (reg8 *) SCSI_RST__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SCSI_RST_PRTDSI__DBL_SYNC_IN (* (reg8 *) SCSI_RST__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SCSI_RST_PRTDSI__OE_SEL0 (* (reg8 *) SCSI_RST__PRTDSI__OE_SEL0) +#define SCSI_RST_PRTDSI__OE_SEL1 (* (reg8 *) SCSI_RST__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SCSI_RST_PRTDSI__OUT_SEL0 (* (reg8 *) SCSI_RST__PRTDSI__OUT_SEL0) +#define SCSI_RST_PRTDSI__OUT_SEL1 (* (reg8 *) SCSI_RST__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SCSI_RST_PRTDSI__SYNC_OUT (* (reg8 *) SCSI_RST__PRTDSI__SYNC_OUT) + + +#if defined(SCSI_RST__INTSTAT) /* Interrupt Registers */ + + #define SCSI_RST_INTSTAT (* (reg8 *) SCSI_RST__INTSTAT) + #define SCSI_RST_SNAP (* (reg8 *) SCSI_RST__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SCSI_RST_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_RST_ISR.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_RST_ISR.c new file mode 100755 index 00000000..5f173b9a --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_RST_ISR.c @@ -0,0 +1,356 @@ +/******************************************************************************* +* File Name: SCSI_RST_ISR.c +* Version 1.70 +* +* Description: +* API for controlling the state of an interrupt. +* +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#include +#include +#include + +#if !defined(SCSI_RST_ISR__REMOVED) /* Check for removal by optimization */ + +/******************************************************************************* +* Place your includes, defines and code here +********************************************************************************/ +/* `#START SCSI_RST_ISR_intc` */ + +/* `#END` */ + +#ifndef CYINT_IRQ_BASE +#define CYINT_IRQ_BASE 16 +#endif /* CYINT_IRQ_BASE */ +#ifndef CYINT_VECT_TABLE +#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET) +#endif /* CYINT_VECT_TABLE */ + +/* Declared in startup, used to set unused interrupts to. */ +CY_ISR_PROTO(IntDefaultHandler); + + +/******************************************************************************* +* Function Name: SCSI_RST_ISR_Start +******************************************************************************** +* +* Summary: +* Set up the interrupt and enable it. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RST_ISR_Start(void) +{ + /* For all we know the interrupt is active. */ + SCSI_RST_ISR_Disable(); + + /* Set the ISR to point to the SCSI_RST_ISR Interrupt. */ + SCSI_RST_ISR_SetVector(&SCSI_RST_ISR_Interrupt); + + /* Set the priority. */ + SCSI_RST_ISR_SetPriority((uint8)SCSI_RST_ISR_INTC_PRIOR_NUMBER); + + /* Enable it. */ + SCSI_RST_ISR_Enable(); +} + + +/******************************************************************************* +* Function Name: SCSI_RST_ISR_StartEx +******************************************************************************** +* +* Summary: +* Set up the interrupt and enable it. +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RST_ISR_StartEx(cyisraddress address) +{ + /* For all we know the interrupt is active. */ + SCSI_RST_ISR_Disable(); + + /* Set the ISR to point to the SCSI_RST_ISR Interrupt. */ + SCSI_RST_ISR_SetVector(address); + + /* Set the priority. */ + SCSI_RST_ISR_SetPriority((uint8)SCSI_RST_ISR_INTC_PRIOR_NUMBER); + + /* Enable it. */ + SCSI_RST_ISR_Enable(); +} + + +/******************************************************************************* +* Function Name: SCSI_RST_ISR_Stop +******************************************************************************** +* +* Summary: +* Disables and removes the interrupt. +* +* Parameters: +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RST_ISR_Stop(void) +{ + /* Disable this interrupt. */ + SCSI_RST_ISR_Disable(); + + /* Set the ISR to point to the passive one. */ + SCSI_RST_ISR_SetVector(&IntDefaultHandler); +} + + +/******************************************************************************* +* Function Name: SCSI_RST_ISR_Interrupt +******************************************************************************** +* +* Summary: +* The default Interrupt Service Routine for SCSI_RST_ISR. +* +* Add custom code between the coments to keep the next version of this file +* from over writting your code. +* +* Parameters: +* +* Return: +* None +* +*******************************************************************************/ +CY_ISR(SCSI_RST_ISR_Interrupt) +{ + /* Place your Interrupt code here. */ + /* `#START SCSI_RST_ISR_Interrupt` */ + + /* `#END` */ +} + + +/******************************************************************************* +* Function Name: SCSI_RST_ISR_SetVector +******************************************************************************** +* +* Summary: +* Change the ISR vector for the Interrupt. Note calling SCSI_RST_ISR_Start +* will override any effect this method would have had. To set the vector +* before the component has been started use SCSI_RST_ISR_StartEx instead. +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RST_ISR_SetVector(cyisraddress address) +{ + cyisraddress * ramVectorTable; + + ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE; + + ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_RST_ISR__INTC_NUMBER] = address; +} + + +/******************************************************************************* +* Function Name: SCSI_RST_ISR_GetVector +******************************************************************************** +* +* Summary: +* Gets the "address" of the current ISR vector for the Interrupt. +* +* Parameters: +* None +* +* Return: +* Address of the ISR in the interrupt vector table. +* +*******************************************************************************/ +cyisraddress SCSI_RST_ISR_GetVector(void) +{ + cyisraddress * ramVectorTable; + + ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE; + + return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_RST_ISR__INTC_NUMBER]; +} + + +/******************************************************************************* +* Function Name: SCSI_RST_ISR_SetPriority +******************************************************************************** +* +* Summary: +* Sets the Priority of the Interrupt. Note calling SCSI_RST_ISR_Start +* or SCSI_RST_ISR_StartEx will override any effect this method +* would have had. This method should only be called after +* SCSI_RST_ISR_Start or SCSI_RST_ISR_StartEx has been called. To set +* the initial priority for the component use the cydwr file in the tool. +* +* Parameters: +* priority: Priority of the interrupt. 0 - 7, 0 being the highest. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RST_ISR_SetPriority(uint8 priority) +{ + *SCSI_RST_ISR_INTC_PRIOR = priority << 5; +} + + +/******************************************************************************* +* Function Name: SCSI_RST_ISR_GetPriority +******************************************************************************** +* +* Summary: +* Gets the Priority of the Interrupt. +* +* Parameters: +* None +* +* Return: +* Priority of the interrupt. 0 - 7, 0 being the highest. +* +*******************************************************************************/ +uint8 SCSI_RST_ISR_GetPriority(void) +{ + uint8 priority; + + + priority = *SCSI_RST_ISR_INTC_PRIOR >> 5; + + return priority; +} + + +/******************************************************************************* +* Function Name: SCSI_RST_ISR_Enable +******************************************************************************** +* +* Summary: +* Enables the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RST_ISR_Enable(void) +{ + /* Enable the general interrupt. */ + *SCSI_RST_ISR_INTC_SET_EN = SCSI_RST_ISR__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SCSI_RST_ISR_GetState +******************************************************************************** +* +* Summary: +* Gets the state (enabled, disabled) of the Interrupt. +* +* Parameters: +* None +* +* Return: +* 1 if enabled, 0 if disabled. +* +*******************************************************************************/ +uint8 SCSI_RST_ISR_GetState(void) +{ + /* Get the state of the general interrupt. */ + return ((*SCSI_RST_ISR_INTC_SET_EN & (uint32)SCSI_RST_ISR__INTC_MASK) != 0u) ? 1u:0u; +} + + +/******************************************************************************* +* Function Name: SCSI_RST_ISR_Disable +******************************************************************************** +* +* Summary: +* Disables the Interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RST_ISR_Disable(void) +{ + /* Disable the general interrupt. */ + *SCSI_RST_ISR_INTC_CLR_EN = SCSI_RST_ISR__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SCSI_RST_ISR_SetPending +******************************************************************************** +* +* Summary: +* Causes the Interrupt to enter the pending state, a software method of +* generating the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RST_ISR_SetPending(void) +{ + *SCSI_RST_ISR_INTC_SET_PD = SCSI_RST_ISR__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SCSI_RST_ISR_ClearPending +******************************************************************************** +* +* Summary: +* Clears a pending interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RST_ISR_ClearPending(void) +{ + *SCSI_RST_ISR_INTC_CLR_PD = SCSI_RST_ISR__INTC_MASK; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_RST_ISR.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_RST_ISR.h new file mode 100755 index 00000000..35e65be1 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_RST_ISR.h @@ -0,0 +1,70 @@ +/******************************************************************************* +* File Name: SCSI_RST_ISR.h +* Version 1.70 +* +* Description: +* Provides the function definitions for the Interrupt Controller. +* +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#if !defined(CY_ISR_SCSI_RST_ISR_H) +#define CY_ISR_SCSI_RST_ISR_H + + +#include +#include + +/* Interrupt Controller API. */ +void SCSI_RST_ISR_Start(void); +void SCSI_RST_ISR_StartEx(cyisraddress address); +void SCSI_RST_ISR_Stop(void); + +CY_ISR_PROTO(SCSI_RST_ISR_Interrupt); + +void SCSI_RST_ISR_SetVector(cyisraddress address); +cyisraddress SCSI_RST_ISR_GetVector(void); + +void SCSI_RST_ISR_SetPriority(uint8 priority); +uint8 SCSI_RST_ISR_GetPriority(void); + +void SCSI_RST_ISR_Enable(void); +uint8 SCSI_RST_ISR_GetState(void); +void SCSI_RST_ISR_Disable(void); + +void SCSI_RST_ISR_SetPending(void); +void SCSI_RST_ISR_ClearPending(void); + + +/* Interrupt Controller Constants */ + +/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_RST_ISR ISR. */ +#define SCSI_RST_ISR_INTC_VECTOR ((reg32 *) SCSI_RST_ISR__INTC_VECT) + +/* Address of the SCSI_RST_ISR ISR priority. */ +#define SCSI_RST_ISR_INTC_PRIOR ((reg8 *) SCSI_RST_ISR__INTC_PRIOR_REG) + +/* Priority of the SCSI_RST_ISR interrupt. */ +#define SCSI_RST_ISR_INTC_PRIOR_NUMBER SCSI_RST_ISR__INTC_PRIOR_NUM + +/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_RST_ISR interrupt. */ +#define SCSI_RST_ISR_INTC_SET_EN ((reg32 *) SCSI_RST_ISR__INTC_SET_EN_REG) + +/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_RST_ISR interrupt. */ +#define SCSI_RST_ISR_INTC_CLR_EN ((reg32 *) SCSI_RST_ISR__INTC_CLR_EN_REG) + +/* Address of the INTC.SET_PD[x] register to set the SCSI_RST_ISR interrupt state to pending. */ +#define SCSI_RST_ISR_INTC_SET_PD ((reg32 *) SCSI_RST_ISR__INTC_SET_PD_REG) + +/* Address of the INTC.CLR_PD[x] register to clear the SCSI_RST_ISR interrupt. */ +#define SCSI_RST_ISR_INTC_CLR_PD ((reg32 *) SCSI_RST_ISR__INTC_CLR_PD_REG) + + +#endif /* CY_ISR_SCSI_RST_ISR_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_RST_aliases.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_RST_aliases.h new file mode 100755 index 00000000..d1a2496c --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SCSI_RST_aliases.h @@ -0,0 +1,34 @@ +/******************************************************************************* +* File Name: SCSI_RST.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SCSI_RST_ALIASES_H) /* Pins SCSI_RST_ALIASES_H */ +#define CY_PINS_SCSI_RST_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SCSI_RST_0 SCSI_RST__0__PC + +#define SCSI_RST_INT SCSI_RST__INT__PC + +#endif /* End Pins SCSI_RST_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SDCard.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SDCard.c new file mode 100755 index 00000000..a7c23d13 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SDCard.c @@ -0,0 +1,1155 @@ +/******************************************************************************* +* File Name: SDCard.c +* Version 2.40 +* +* Description: +* This file provides all API functionality of the SPI Master component. +* +* Note: +* None. +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SDCard_PVT.h" + +#if(SDCard_TX_SOFTWARE_BUF_ENABLED) + volatile uint8 SDCard_txBuffer[SDCard_TX_BUFFER_SIZE] = {0u}; + volatile uint8 SDCard_txBufferFull; + volatile uint8 SDCard_txBufferRead; + volatile uint8 SDCard_txBufferWrite; +#endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ + +#if(SDCard_RX_SOFTWARE_BUF_ENABLED) + volatile uint8 SDCard_rxBuffer[SDCard_RX_BUFFER_SIZE] = {0u}; + volatile uint8 SDCard_rxBufferFull; + volatile uint8 SDCard_rxBufferRead; + volatile uint8 SDCard_rxBufferWrite; +#endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */ + +uint8 SDCard_initVar = 0u; + +volatile uint8 SDCard_swStatusTx; +volatile uint8 SDCard_swStatusRx; + + +/******************************************************************************* +* Function Name: SDCard_Init +******************************************************************************** +* +* Summary: +* Inits/Restores default SPIM configuration provided with customizer. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Side Effects: +* When this function is called it initializes all of the necessary parameters +* for execution. i.e. setting the initial interrupt mask, configuring the +* interrupt service routine, configuring the bit-counter parameters and +* clearing the FIFO and Status Register. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SDCard_Init(void) +{ + /* Initialize the Bit counter */ + SDCard_COUNTER_PERIOD_REG = SDCard_BITCTR_INIT; + + /* Init TX ISR */ + #if(0u != SDCard_INTERNAL_TX_INT_ENABLED) + CyIntDisable (SDCard_TX_ISR_NUMBER); + CyIntSetPriority (SDCard_TX_ISR_NUMBER, SDCard_TX_ISR_PRIORITY); + (void) CyIntSetVector(SDCard_TX_ISR_NUMBER, &SDCard_TX_ISR); + #endif /* (0u != SDCard_INTERNAL_TX_INT_ENABLED) */ + + /* Init RX ISR */ + #if(0u != SDCard_INTERNAL_RX_INT_ENABLED) + CyIntDisable (SDCard_RX_ISR_NUMBER); + CyIntSetPriority (SDCard_RX_ISR_NUMBER, SDCard_RX_ISR_PRIORITY); + (void) CyIntSetVector(SDCard_RX_ISR_NUMBER, &SDCard_RX_ISR); + #endif /* (0u != SDCard_INTERNAL_RX_INT_ENABLED) */ + + /* Clear any stray data from the RX and TX FIFO */ + SDCard_ClearFIFO(); + + #if(SDCard_RX_SOFTWARE_BUF_ENABLED) + SDCard_rxBufferFull = 0u; + SDCard_rxBufferRead = 0u; + SDCard_rxBufferWrite = 0u; + #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */ + + #if(SDCard_TX_SOFTWARE_BUF_ENABLED) + SDCard_txBufferFull = 0u; + SDCard_txBufferRead = 0u; + SDCard_txBufferWrite = 0u; + #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ + + (void) SDCard_ReadTxStatus(); /* Clear Tx status and swStatusTx */ + (void) SDCard_ReadRxStatus(); /* Clear Rx status and swStatusRx */ + + /* Configure TX and RX interrupt mask */ + SDCard_TX_STATUS_MASK_REG = SDCard_TX_INIT_INTERRUPTS_MASK; + SDCard_RX_STATUS_MASK_REG = SDCard_RX_INIT_INTERRUPTS_MASK; +} + + +/******************************************************************************* +* Function Name: SDCard_Enable +******************************************************************************** +* +* Summary: +* Enable SPIM component. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void SDCard_Enable(void) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + SDCard_COUNTER_CONTROL_REG |= SDCard_CNTR_ENABLE; + SDCard_TX_STATUS_ACTL_REG |= SDCard_INT_ENABLE; + SDCard_RX_STATUS_ACTL_REG |= SDCard_INT_ENABLE; + CyExitCriticalSection(enableInterrupts); + + #if(0u != SDCard_INTERNAL_CLOCK) + SDCard_IntClock_Enable(); + #endif /* (0u != SDCard_INTERNAL_CLOCK) */ + + SDCard_EnableTxInt(); + SDCard_EnableRxInt(); +} + + +/******************************************************************************* +* Function Name: SDCard_Start +******************************************************************************** +* +* Summary: +* Initialize and Enable the SPI Master component. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* SDCard_initVar - used to check initial configuration, modified on +* first function call. +* +* Theory: +* Enable the clock input to enable operation. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SDCard_Start(void) +{ + if(0u == SDCard_initVar) + { + SDCard_Init(); + SDCard_initVar = 1u; + } + + SDCard_Enable(); +} + + +/******************************************************************************* +* Function Name: SDCard_Stop +******************************************************************************** +* +* Summary: +* Disable the SPI Master component. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Disable the clock input to enable operation. +* +*******************************************************************************/ +void SDCard_Stop(void) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + SDCard_TX_STATUS_ACTL_REG &= ((uint8) ~SDCard_INT_ENABLE); + SDCard_RX_STATUS_ACTL_REG &= ((uint8) ~SDCard_INT_ENABLE); + CyExitCriticalSection(enableInterrupts); + + #if(0u != SDCard_INTERNAL_CLOCK) + SDCard_IntClock_Disable(); + #endif /* (0u != SDCard_INTERNAL_CLOCK) */ + + SDCard_DisableTxInt(); + SDCard_DisableRxInt(); +} + + +/******************************************************************************* +* Function Name: SDCard_EnableTxInt +******************************************************************************** +* +* Summary: +* Enable internal Tx interrupt generation. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Enable the internal Tx interrupt output -or- the interrupt component itself. +* +*******************************************************************************/ +void SDCard_EnableTxInt(void) +{ + #if(0u != SDCard_INTERNAL_TX_INT_ENABLED) + CyIntEnable(SDCard_TX_ISR_NUMBER); + #endif /* (0u != SDCard_INTERNAL_TX_INT_ENABLED) */ +} + + +/******************************************************************************* +* Function Name: SDCard_EnableRxInt +******************************************************************************** +* +* Summary: +* Enable internal Rx interrupt generation. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Enable the internal Rx interrupt output -or- the interrupt component itself. +* +*******************************************************************************/ +void SDCard_EnableRxInt(void) +{ + #if(0u != SDCard_INTERNAL_RX_INT_ENABLED) + CyIntEnable(SDCard_RX_ISR_NUMBER); + #endif /* (0u != SDCard_INTERNAL_RX_INT_ENABLED) */ +} + + +/******************************************************************************* +* Function Name: SDCard_DisableTxInt +******************************************************************************** +* +* Summary: +* Disable internal Tx interrupt generation. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Disable the internal Tx interrupt output -or- the interrupt component itself. +* +*******************************************************************************/ +void SDCard_DisableTxInt(void) +{ + #if(0u != SDCard_INTERNAL_TX_INT_ENABLED) + CyIntDisable(SDCard_TX_ISR_NUMBER); + #endif /* (0u != SDCard_INTERNAL_TX_INT_ENABLED) */ +} + + +/******************************************************************************* +* Function Name: SDCard_DisableRxInt +******************************************************************************** +* +* Summary: +* Disable internal Rx interrupt generation. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Disable the internal Rx interrupt output -or- the interrupt component itself. +* +*******************************************************************************/ +void SDCard_DisableRxInt(void) +{ + #if(0u != SDCard_INTERNAL_RX_INT_ENABLED) + CyIntDisable(SDCard_RX_ISR_NUMBER); + #endif /* (0u != SDCard_INTERNAL_RX_INT_ENABLED) */ +} + + +/******************************************************************************* +* Function Name: SDCard_SetTxInterruptMode +******************************************************************************** +* +* Summary: +* Configure which status bits trigger an interrupt event. +* +* Parameters: +* intSrc: An or'd combination of the desired status bit masks (defined in the +* header file). +* +* Return: +* None. +* +* Theory: +* Enables the output of specific status bits to the interrupt controller. +* +*******************************************************************************/ +void SDCard_SetTxInterruptMode(uint8 intSrc) +{ + SDCard_TX_STATUS_MASK_REG = intSrc; +} + + +/******************************************************************************* +* Function Name: SDCard_SetRxInterruptMode +******************************************************************************** +* +* Summary: +* Configure which status bits trigger an interrupt event. +* +* Parameters: +* intSrc: An or'd combination of the desired status bit masks (defined in the +* header file). +* +* Return: +* None. +* +* Theory: +* Enables the output of specific status bits to the interrupt controller. +* +*******************************************************************************/ +void SDCard_SetRxInterruptMode(uint8 intSrc) +{ + SDCard_RX_STATUS_MASK_REG = intSrc; +} + + +/******************************************************************************* +* Function Name: SDCard_ReadTxStatus +******************************************************************************** +* +* Summary: +* Read the Tx status register for the component. +* +* Parameters: +* None. +* +* Return: +* Contents of the Tx status register. +* +* Global variables: +* SDCard_swStatusTx - used to store in software status register, +* modified every function call - resets to zero. +* +* Theory: +* Allows the user and the API to read the Tx status register for error +* detection and flow control. +* +* Side Effects: +* Clear Tx status register of the component. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 SDCard_ReadTxStatus(void) +{ + uint8 tmpStatus; + + #if(SDCard_TX_SOFTWARE_BUF_ENABLED) + /* Disable TX interrupt to protect global veriables */ + SDCard_DisableTxInt(); + + tmpStatus = SDCard_GET_STATUS_TX(SDCard_swStatusTx); + SDCard_swStatusTx = 0u; + + SDCard_EnableTxInt(); + + #else + + tmpStatus = SDCard_TX_STATUS_REG; + + #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ + + return(tmpStatus); +} + + +/******************************************************************************* +* Function Name: SDCard_ReadRxStatus +******************************************************************************** +* +* Summary: +* Read the Rx status register for the component. +* +* Parameters: +* None. +* +* Return: +* Contents of the Rx status register. +* +* Global variables: +* SDCard_swStatusRx - used to store in software Rx status register, +* modified every function call - resets to zero. +* +* Theory: +* Allows the user and the API to read the Rx status register for error +* detection and flow control. +* +* Side Effects: +* Clear Rx status register of the component. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 SDCard_ReadRxStatus(void) +{ + uint8 tmpStatus; + + #if(SDCard_RX_SOFTWARE_BUF_ENABLED) + /* Disable RX interrupt to protect global veriables */ + SDCard_DisableRxInt(); + + tmpStatus = SDCard_GET_STATUS_RX(SDCard_swStatusRx); + SDCard_swStatusRx = 0u; + + SDCard_EnableRxInt(); + + #else + + tmpStatus = SDCard_RX_STATUS_REG; + + #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */ + + return(tmpStatus); +} + + +/******************************************************************************* +* Function Name: SDCard_WriteTxData +******************************************************************************** +* +* Summary: +* Write a byte of data to be sent across the SPI. +* +* Parameters: +* txDataByte: The data value to send across the SPI. +* +* Return: +* None. +* +* Global variables: +* SDCard_txBufferWrite - used for the account of the bytes which +* have been written down in the TX software buffer, modified every function +* call if TX Software Buffer is used. +* SDCard_txBufferRead - used for the account of the bytes which +* have been read from the TX software buffer. +* SDCard_txBuffer[SDCard_TX_BUFFER_SIZE] - used to store +* data to sending, modified every function call if TX Software Buffer is used. +* +* Theory: +* Allows the user to transmit any byte of data in a single transfer. +* +* Side Effects: +* If this function is called again before the previous byte is finished then +* the next byte will be appended to the transfer with no time between +* the byte transfers. Clear Tx status register of the component. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SDCard_WriteTxData(uint8 txData) +{ + #if(SDCard_TX_SOFTWARE_BUF_ENABLED) + + uint8 tempStatus; + uint8 tmpTxBufferRead; + + /* Block if TX buffer is FULL: don't overwrite */ + do + { + tmpTxBufferRead = SDCard_txBufferRead; + if(0u == tmpTxBufferRead) + { + tmpTxBufferRead = (SDCard_TX_BUFFER_SIZE - 1u); + } + else + { + tmpTxBufferRead--; + } + + }while(tmpTxBufferRead == SDCard_txBufferWrite); + + /* Disable TX interrupt to protect global veriables */ + SDCard_DisableTxInt(); + + tempStatus = SDCard_GET_STATUS_TX(SDCard_swStatusTx); + SDCard_swStatusTx = tempStatus; + + + if((SDCard_txBufferRead == SDCard_txBufferWrite) && + (0u != (SDCard_swStatusTx & SDCard_STS_TX_FIFO_NOT_FULL))) + { + /* Add directly to the TX FIFO */ + CY_SET_REG8(SDCard_TXDATA_PTR, txData); + } + else + { + /* Add to the TX software buffer */ + SDCard_txBufferWrite++; + if(SDCard_txBufferWrite >= SDCard_TX_BUFFER_SIZE) + { + SDCard_txBufferWrite = 0u; + } + + if(SDCard_txBufferWrite == SDCard_txBufferRead) + { + SDCard_txBufferRead++; + if(SDCard_txBufferRead >= SDCard_TX_BUFFER_SIZE) + { + SDCard_txBufferRead = 0u; + } + SDCard_txBufferFull = 1u; + } + + SDCard_txBuffer[SDCard_txBufferWrite] = txData; + + SDCard_TX_STATUS_MASK_REG |= SDCard_STS_TX_FIFO_NOT_FULL; + } + + SDCard_EnableTxInt(); + + #else + + while(0u == (SDCard_TX_STATUS_REG & SDCard_STS_TX_FIFO_NOT_FULL)) + { + ; /* Wait for room in FIFO */ + } + + /* Put byte in TX FIFO */ + CY_SET_REG8(SDCard_TXDATA_PTR, txData); + + #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ +} + + +/******************************************************************************* +* Function Name: SDCard_ReadRxData +******************************************************************************** +* +* Summary: +* Read the next byte of data received across the SPI. +* +* Parameters: +* None. +* +* Return: +* The next byte of data read from the FIFO. +* +* Global variables: +* SDCard_rxBufferWrite - used for the account of the bytes which +* have been written down in the RX software buffer. +* SDCard_rxBufferRead - used for the account of the bytes which +* have been read from the RX software buffer, modified every function +* call if RX Software Buffer is used. +* SDCard_rxBuffer[SDCard_RX_BUFFER_SIZE] - used to store +* received data. +* +* Theory: +* Allows the user to read a byte of data received. +* +* Side Effects: +* Will return invalid data if the FIFO is empty. The user should Call +* GetRxBufferSize() and if it returns a non-zero value then it is safe to call +* ReadByte() function. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 SDCard_ReadRxData(void) +{ + uint8 rxData; + + #if(SDCard_RX_SOFTWARE_BUF_ENABLED) + + /* Disable RX interrupt to protect global veriables */ + SDCard_DisableRxInt(); + + if(SDCard_rxBufferRead != SDCard_rxBufferWrite) + { + if(0u == SDCard_rxBufferFull) + { + SDCard_rxBufferRead++; + if(SDCard_rxBufferRead >= SDCard_RX_BUFFER_SIZE) + { + SDCard_rxBufferRead = 0u; + } + } + else + { + SDCard_rxBufferFull = 0u; + } + } + + rxData = SDCard_rxBuffer[SDCard_rxBufferRead]; + + SDCard_EnableRxInt(); + + #else + + rxData = CY_GET_REG8(SDCard_RXDATA_PTR); + + #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */ + + return(rxData); +} + + +/******************************************************************************* +* Function Name: SDCard_GetRxBufferSize +******************************************************************************** +* +* Summary: +* Returns the number of bytes/words of data currently held in the RX buffer. +* If RX Software Buffer not used then function return 0 if FIFO empty or 1 if +* FIFO not empty. In another case function return size of RX Software Buffer. +* +* Parameters: +* None. +* +* Return: +* Integer count of the number of bytes/words in the RX buffer. +* +* Global variables: +* SDCard_rxBufferWrite - used for the account of the bytes which +* have been written down in the RX software buffer. +* SDCard_rxBufferRead - used for the account of the bytes which +* have been read from the RX software buffer. +* +* Side Effects: +* Clear status register of the component. +* +*******************************************************************************/ +uint8 SDCard_GetRxBufferSize(void) +{ + uint8 size; + + #if(SDCard_RX_SOFTWARE_BUF_ENABLED) + + /* Disable RX interrupt to protect global veriables */ + SDCard_DisableRxInt(); + + if(SDCard_rxBufferRead == SDCard_rxBufferWrite) + { + size = 0u; + } + else if(SDCard_rxBufferRead < SDCard_rxBufferWrite) + { + size = (SDCard_rxBufferWrite - SDCard_rxBufferRead); + } + else + { + size = (SDCard_RX_BUFFER_SIZE - SDCard_rxBufferRead) + SDCard_rxBufferWrite; + } + + SDCard_EnableRxInt(); + + #else + + /* We can only know if there is data in the RX FIFO */ + size = (0u != (SDCard_RX_STATUS_REG & SDCard_STS_RX_FIFO_NOT_EMPTY)) ? 1u : 0u; + + #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ + + return(size); +} + + +/******************************************************************************* +* Function Name: SDCard_GetTxBufferSize +******************************************************************************** +* +* Summary: +* Returns the number of bytes/words of data currently held in the TX buffer. +* If TX Software Buffer not used then function return 0 - if FIFO empty, 1 - if +* FIFO not full, 4 - if FIFO full. In another case function return size of TX +* Software Buffer. +* +* Parameters: +* None. +* +* Return: +* Integer count of the number of bytes/words in the TX buffer. +* +* Global variables: +* SDCard_txBufferWrite - used for the account of the bytes which +* have been written down in the TX software buffer. +* SDCard_txBufferRead - used for the account of the bytes which +* have been read from the TX software buffer. +* +* Side Effects: +* Clear status register of the component. +* +*******************************************************************************/ +uint8 SDCard_GetTxBufferSize(void) +{ + uint8 size; + + #if(SDCard_TX_SOFTWARE_BUF_ENABLED) + /* Disable TX interrupt to protect global veriables */ + SDCard_DisableTxInt(); + + if(SDCard_txBufferRead == SDCard_txBufferWrite) + { + size = 0u; + } + else if(SDCard_txBufferRead < SDCard_txBufferWrite) + { + size = (SDCard_txBufferWrite - SDCard_txBufferRead); + } + else + { + size = (SDCard_TX_BUFFER_SIZE - SDCard_txBufferRead) + SDCard_txBufferWrite; + } + + SDCard_EnableTxInt(); + + #else + + size = SDCard_TX_STATUS_REG; + + if(0u != (size & SDCard_STS_TX_FIFO_EMPTY)) + { + size = 0u; + } + else if(0u != (size & SDCard_STS_TX_FIFO_NOT_FULL)) + { + size = 1u; + } + else + { + size = SDCard_FIFO_SIZE; + } + + #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ + + return(size); +} + + +/******************************************************************************* +* Function Name: SDCard_ClearRxBuffer +******************************************************************************** +* +* Summary: +* Clear the RX RAM buffer by setting the read and write pointers both to zero. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* SDCard_rxBufferWrite - used for the account of the bytes which +* have been written down in the RX software buffer, modified every function +* call - resets to zero. +* SDCard_rxBufferRead - used for the account of the bytes which +* have been read from the RX software buffer, modified every function call - +* resets to zero. +* +* Theory: +* Setting the pointers to zero makes the system believe there is no data to +* read and writing will resume at address 0 overwriting any data that may have +* remained in the RAM. +* +* Side Effects: +* Any received data not read from the RAM buffer will be lost when overwritten. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SDCard_ClearRxBuffer(void) +{ + /* Clear Hardware RX FIFO */ + while(0u !=(SDCard_RX_STATUS_REG & SDCard_STS_RX_FIFO_NOT_EMPTY)) + { + (void) CY_GET_REG8(SDCard_RXDATA_PTR); + } + + #if(SDCard_RX_SOFTWARE_BUF_ENABLED) + /* Disable RX interrupt to protect global veriables */ + SDCard_DisableRxInt(); + + SDCard_rxBufferFull = 0u; + SDCard_rxBufferRead = 0u; + SDCard_rxBufferWrite = 0u; + + SDCard_EnableRxInt(); + #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */ +} + + +/******************************************************************************* +* Function Name: SDCard_ClearTxBuffer +******************************************************************************** +* +* Summary: +* Clear the TX RAM buffer by setting the read and write pointers both to zero. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* SDCard_txBufferWrite - used for the account of the bytes which +* have been written down in the TX software buffer, modified every function +* call - resets to zero. +* SDCard_txBufferRead - used for the account of the bytes which +* have been read from the TX software buffer, modified every function call - +* resets to zero. +* +* Theory: +* Setting the pointers to zero makes the system believe there is no data to +* read and writing will resume at address 0 overwriting any data that may have +* remained in the RAM. +* +* Side Effects: +* Any data not yet transmitted from the RAM buffer will be lost when +* overwritten. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SDCard_ClearTxBuffer(void) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + /* Clear TX FIFO */ + SDCard_AUX_CONTROL_DP0_REG |= ((uint8) SDCard_TX_FIFO_CLR); + SDCard_AUX_CONTROL_DP0_REG &= ((uint8) ~SDCard_TX_FIFO_CLR); + + #if(SDCard_USE_SECOND_DATAPATH) + /* Clear TX FIFO for 2nd Datapath */ + SDCard_AUX_CONTROL_DP1_REG |= ((uint8) SDCard_TX_FIFO_CLR); + SDCard_AUX_CONTROL_DP1_REG &= ((uint8) ~SDCard_TX_FIFO_CLR); + #endif /* (SDCard_USE_SECOND_DATAPATH) */ + CyExitCriticalSection(enableInterrupts); + + #if(SDCard_TX_SOFTWARE_BUF_ENABLED) + /* Disable TX interrupt to protect global veriables */ + SDCard_DisableTxInt(); + + SDCard_txBufferFull = 0u; + SDCard_txBufferRead = 0u; + SDCard_txBufferWrite = 0u; + + /* Buffer is EMPTY: disable TX FIFO NOT FULL interrupt */ + SDCard_TX_STATUS_MASK_REG &= ((uint8) ~SDCard_STS_TX_FIFO_NOT_FULL); + + SDCard_EnableTxInt(); + #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ +} + + +#if(0u != SDCard_BIDIRECTIONAL_MODE) + /******************************************************************************* + * Function Name: SDCard_TxEnable + ******************************************************************************** + * + * Summary: + * If the SPI master is configured to use a single bi-directional pin then this + * will set the bi-directional pin to transmit. + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + void SDCard_TxEnable(void) + { + SDCard_CONTROL_REG |= SDCard_CTRL_TX_SIGNAL_EN; + } + + + /******************************************************************************* + * Function Name: SDCard_TxDisable + ******************************************************************************** + * + * Summary: + * If the SPI master is configured to use a single bi-directional pin then this + * will set the bi-directional pin to receive. + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + void SDCard_TxDisable(void) + { + SDCard_CONTROL_REG &= ((uint8) ~SDCard_CTRL_TX_SIGNAL_EN); + } + +#endif /* (0u != SDCard_BIDIRECTIONAL_MODE) */ + + +/******************************************************************************* +* Function Name: SDCard_PutArray +******************************************************************************** +* +* Summary: +* Write available data from ROM/RAM to the TX buffer while space is available +* in the TX buffer. Keep trying until all data is passed to the TX buffer. +* +* Parameters: +* *buffer: Pointer to the location in RAM containing the data to send +* byteCount: The number of bytes to move to the transmit buffer. +* +* Return: +* None. +* +* Side Effects: +* Will stay in this routine until all data has been sent. May get locked in +* this loop if data is not being initiated by the master if there is not +* enough room in the TX FIFO. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SDCard_PutArray(const uint8 buffer[], uint8 byteCount) + +{ + uint8 bufIndex; + + bufIndex = 0u; + + while(byteCount > 0u) + { + SDCard_WriteTxData(buffer[bufIndex]); + bufIndex++; + byteCount--; + } +} + + +/******************************************************************************* +* Function Name: SDCard_ClearFIFO +******************************************************************************** +* +* Summary: +* Clear the RX and TX FIFO's of all data for a fresh start. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Side Effects: +* Clear status register of the component. +* +*******************************************************************************/ +void SDCard_ClearFIFO(void) +{ + uint8 enableInterrupts; + + /* Clear Hardware RX FIFO */ + while(0u !=(SDCard_RX_STATUS_REG & SDCard_STS_RX_FIFO_NOT_EMPTY)) + { + (void) CY_GET_REG8(SDCard_RXDATA_PTR); + } + + enableInterrupts = CyEnterCriticalSection(); + /* Clear TX FIFO */ + SDCard_AUX_CONTROL_DP0_REG |= ((uint8) SDCard_TX_FIFO_CLR); + SDCard_AUX_CONTROL_DP0_REG &= ((uint8) ~SDCard_TX_FIFO_CLR); + + #if(SDCard_USE_SECOND_DATAPATH) + /* Clear TX FIFO for 2nd Datapath */ + SDCard_AUX_CONTROL_DP1_REG |= ((uint8) SDCard_TX_FIFO_CLR); + SDCard_AUX_CONTROL_DP1_REG &= ((uint8) ~SDCard_TX_FIFO_CLR); + #endif /* (SDCard_USE_SECOND_DATAPATH) */ + CyExitCriticalSection(enableInterrupts); +} + + +/* Following functions are for version Compatibility, they are obsolete. +* Please do not use it in new projects. +*/ + + +/******************************************************************************* +* Function Name: SDCard_EnableInt +******************************************************************************** +* +* Summary: +* Enable internal interrupt generation. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Enable the internal interrupt output -or- the interrupt component itself. +* +*******************************************************************************/ +void SDCard_EnableInt(void) +{ + SDCard_EnableRxInt(); + SDCard_EnableTxInt(); +} + + +/******************************************************************************* +* Function Name: SDCard_DisableInt +******************************************************************************** +* +* Summary: +* Disable internal interrupt generation. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Disable the internal interrupt output -or- the interrupt component itself. +* +*******************************************************************************/ +void SDCard_DisableInt(void) +{ + SDCard_DisableTxInt(); + SDCard_DisableRxInt(); +} + + +/******************************************************************************* +* Function Name: SDCard_SetInterruptMode +******************************************************************************** +* +* Summary: +* Configure which status bits trigger an interrupt event. +* +* Parameters: +* intSrc: An or'd combination of the desired status bit masks (defined in the +* header file). +* +* Return: +* None. +* +* Theory: +* Enables the output of specific status bits to the interrupt controller. +* +*******************************************************************************/ +void SDCard_SetInterruptMode(uint8 intSrc) +{ + SDCard_TX_STATUS_MASK_REG = (intSrc & ((uint8) ~SDCard_STS_SPI_IDLE)); + SDCard_RX_STATUS_MASK_REG = intSrc; +} + + +/******************************************************************************* +* Function Name: SDCard_ReadStatus +******************************************************************************** +* +* Summary: +* Read the status register for the component. +* +* Parameters: +* None. +* +* Return: +* Contents of the status register. +* +* Global variables: +* SDCard_swStatus - used to store in software status register, +* modified every function call - resets to zero. +* +* Theory: +* Allows the user and the API to read the status register for error detection +* and flow control. +* +* Side Effects: +* Clear status register of the component. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 SDCard_ReadStatus(void) +{ + uint8 tmpStatus; + + #if(SDCard_TX_SOFTWARE_BUF_ENABLED || SDCard_RX_SOFTWARE_BUF_ENABLED) + + SDCard_DisableInt(); + + tmpStatus = SDCard_GET_STATUS_RX(SDCard_swStatusRx); + tmpStatus |= SDCard_GET_STATUS_TX(SDCard_swStatusTx); + tmpStatus &= ((uint8) ~SDCard_STS_SPI_IDLE); + + SDCard_swStatusTx = 0u; + SDCard_swStatusRx = 0u; + + SDCard_EnableInt(); + + #else + + tmpStatus = SDCard_RX_STATUS_REG; + tmpStatus |= SDCard_TX_STATUS_REG; + tmpStatus &= ((uint8) ~SDCard_STS_SPI_IDLE); + + #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED || SDCard_RX_SOFTWARE_BUF_ENABLED) */ + + return(tmpStatus); +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SDCard.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SDCard.h new file mode 100755 index 00000000..3b99496a --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SDCard.h @@ -0,0 +1,389 @@ +/******************************************************************************* +* File Name: SDCard.h +* Version 2.40 +* +* Description: +* Contains the function prototypes, constants and register definition +* of the SPI Master Component. +* +* Note: +* None +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_SPIM_SDCard_H) +#define CY_SPIM_SDCard_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "CyLib.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component SPI_Master_v2_40 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ + +#define SDCard_INTERNAL_CLOCK (0u) + +#if(0u != SDCard_INTERNAL_CLOCK) + #include "SDCard_IntClock.h" +#endif /* (0u != SDCard_INTERNAL_CLOCK) */ + +#define SDCard_MODE (1u) +#define SDCard_DATA_WIDTH (8u) +#define SDCard_MODE_USE_ZERO (1u) +#define SDCard_BIDIRECTIONAL_MODE (0u) + +/* Internal interrupt handling */ +#define SDCard_TX_BUFFER_SIZE (4u) +#define SDCard_RX_BUFFER_SIZE (4u) +#define SDCard_INTERNAL_TX_INT_ENABLED (0u) +#define SDCard_INTERNAL_RX_INT_ENABLED (0u) + +#define SDCard_SINGLE_REG_SIZE (8u) +#define SDCard_USE_SECOND_DATAPATH (SDCard_DATA_WIDTH > SDCard_SINGLE_REG_SIZE) + +#define SDCard_FIFO_SIZE (4u) +#define SDCard_TX_SOFTWARE_BUF_ENABLED ((0u != SDCard_INTERNAL_TX_INT_ENABLED) && \ + (SDCard_TX_BUFFER_SIZE > SDCard_FIFO_SIZE)) + +#define SDCard_RX_SOFTWARE_BUF_ENABLED ((0u != SDCard_INTERNAL_RX_INT_ENABLED) && \ + (SDCard_RX_BUFFER_SIZE > SDCard_FIFO_SIZE)) + + +/*************************************** +* Data Struct Definition +***************************************/ + +/* Sleep Mode API Support */ +typedef struct +{ + uint8 enableState; + uint8 cntrPeriod; + #if(CY_UDB_V0) + uint8 saveSrTxIntMask; + uint8 saveSrRxIntMask; + #endif /* (CY_UDB_V0) */ + +} SDCard_BACKUP_STRUCT; + + +/*************************************** +* Function Prototypes +***************************************/ + +void SDCard_Init(void) ; +void SDCard_Enable(void) ; +void SDCard_Start(void) ; +void SDCard_Stop(void) ; + +void SDCard_EnableTxInt(void) ; +void SDCard_EnableRxInt(void) ; +void SDCard_DisableTxInt(void) ; +void SDCard_DisableRxInt(void) ; + +void SDCard_Sleep(void) ; +void SDCard_Wakeup(void) ; +void SDCard_SaveConfig(void) ; +void SDCard_RestoreConfig(void) ; + +void SDCard_SetTxInterruptMode(uint8 intSrc) ; +void SDCard_SetRxInterruptMode(uint8 intSrc) ; +uint8 SDCard_ReadTxStatus(void) ; +uint8 SDCard_ReadRxStatus(void) ; +void SDCard_WriteTxData(uint8 txData) \ + ; +uint8 SDCard_ReadRxData(void) \ + ; +uint8 SDCard_GetRxBufferSize(void) ; +uint8 SDCard_GetTxBufferSize(void) ; +void SDCard_ClearRxBuffer(void) ; +void SDCard_ClearTxBuffer(void) ; +void SDCard_ClearFIFO(void) ; +void SDCard_PutArray(const uint8 buffer[], uint8 byteCount) \ + ; + +#if(0u != SDCard_BIDIRECTIONAL_MODE) + void SDCard_TxEnable(void) ; + void SDCard_TxDisable(void) ; +#endif /* (0u != SDCard_BIDIRECTIONAL_MODE) */ + +CY_ISR_PROTO(SDCard_TX_ISR); +CY_ISR_PROTO(SDCard_RX_ISR); + + +/********************************** +* Variable with external linkage +**********************************/ + +extern uint8 SDCard_initVar; + + +/*************************************** +* API Constants +***************************************/ + +#define SDCard_TX_ISR_NUMBER ((uint8) (SDCard_TxInternalInterrupt__INTC_NUMBER)) +#define SDCard_RX_ISR_NUMBER ((uint8) (SDCard_RxInternalInterrupt__INTC_NUMBER)) + +#define SDCard_TX_ISR_PRIORITY ((uint8) (SDCard_TxInternalInterrupt__INTC_PRIOR_NUM)) +#define SDCard_RX_ISR_PRIORITY ((uint8) (SDCard_RxInternalInterrupt__INTC_PRIOR_NUM)) + + +/*************************************** +* Initial Parameter Constants +***************************************/ + +#define SDCard_INT_ON_SPI_DONE ((uint8) (0u << SDCard_STS_SPI_DONE_SHIFT)) +#define SDCard_INT_ON_TX_EMPTY ((uint8) (0u << SDCard_STS_TX_FIFO_EMPTY_SHIFT)) +#define SDCard_INT_ON_TX_NOT_FULL ((uint8) (0u << \ + SDCard_STS_TX_FIFO_NOT_FULL_SHIFT)) +#define SDCard_INT_ON_BYTE_COMP ((uint8) (0u << SDCard_STS_BYTE_COMPLETE_SHIFT)) +#define SDCard_INT_ON_SPI_IDLE ((uint8) (0u << SDCard_STS_SPI_IDLE_SHIFT)) + +/* Disable TX_NOT_FULL if software buffer is used */ +#define SDCard_INT_ON_TX_NOT_FULL_DEF ((SDCard_TX_SOFTWARE_BUF_ENABLED) ? \ + (0u) : (SDCard_INT_ON_TX_NOT_FULL)) + +/* TX interrupt mask */ +#define SDCard_TX_INIT_INTERRUPTS_MASK (SDCard_INT_ON_SPI_DONE | \ + SDCard_INT_ON_TX_EMPTY | \ + SDCard_INT_ON_TX_NOT_FULL_DEF | \ + SDCard_INT_ON_BYTE_COMP | \ + SDCard_INT_ON_SPI_IDLE) + +#define SDCard_INT_ON_RX_FULL ((uint8) (0u << \ + SDCard_STS_RX_FIFO_FULL_SHIFT)) +#define SDCard_INT_ON_RX_NOT_EMPTY ((uint8) (0u << \ + SDCard_STS_RX_FIFO_NOT_EMPTY_SHIFT)) +#define SDCard_INT_ON_RX_OVER ((uint8) (0u << \ + SDCard_STS_RX_FIFO_OVERRUN_SHIFT)) + +/* RX interrupt mask */ +#define SDCard_RX_INIT_INTERRUPTS_MASK (SDCard_INT_ON_RX_FULL | \ + SDCard_INT_ON_RX_NOT_EMPTY | \ + SDCard_INT_ON_RX_OVER) +/* Nubmer of bits to receive/transmit */ +#define SDCard_BITCTR_INIT (((uint8) (SDCard_DATA_WIDTH << 1u)) - 1u) + + +/*************************************** +* Registers +***************************************/ + +#if(CY_PSOC3 || CY_PSOC5) + #define SDCard_TXDATA_REG (* (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u0__F0_REG) + #define SDCard_TXDATA_PTR ( (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u0__F0_REG) + #define SDCard_RXDATA_REG (* (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u0__F1_REG) + #define SDCard_RXDATA_PTR ( (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u0__F1_REG) +#else /* PSOC4 */ + #if(SDCard_USE_SECOND_DATAPATH) + #define SDCard_TXDATA_REG (* (reg16 *) \ + SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG) + #define SDCard_TXDATA_PTR ( (reg16 *) \ + SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG) + #define SDCard_RXDATA_REG (* (reg16 *) \ + SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG) + #define SDCard_RXDATA_PTR ( (reg16 *) \ + SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG) + #else + #define SDCard_TXDATA_REG (* (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u0__F0_REG) + #define SDCard_TXDATA_PTR ( (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u0__F0_REG) + #define SDCard_RXDATA_REG (* (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u0__F1_REG) + #define SDCard_RXDATA_PTR ( (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u0__F1_REG) + #endif /* (SDCard_USE_SECOND_DATAPATH) */ +#endif /* (CY_PSOC3 || CY_PSOC5) */ + +#define SDCard_AUX_CONTROL_DP0_REG (* (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG) +#define SDCard_AUX_CONTROL_DP0_PTR ( (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG) + +#if(SDCard_USE_SECOND_DATAPATH) + #define SDCard_AUX_CONTROL_DP1_REG (* (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u1__DP_AUX_CTL_REG) + #define SDCard_AUX_CONTROL_DP1_PTR ( (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u1__DP_AUX_CTL_REG) +#endif /* (SDCard_USE_SECOND_DATAPATH) */ + +#define SDCard_COUNTER_PERIOD_REG (* (reg8 *) SDCard_BSPIM_BitCounter__PERIOD_REG) +#define SDCard_COUNTER_PERIOD_PTR ( (reg8 *) SDCard_BSPIM_BitCounter__PERIOD_REG) +#define SDCard_COUNTER_CONTROL_REG (* (reg8 *) SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG) +#define SDCard_COUNTER_CONTROL_PTR ( (reg8 *) SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG) + +#define SDCard_TX_STATUS_REG (* (reg8 *) SDCard_BSPIM_TxStsReg__STATUS_REG) +#define SDCard_TX_STATUS_PTR ( (reg8 *) SDCard_BSPIM_TxStsReg__STATUS_REG) +#define SDCard_RX_STATUS_REG (* (reg8 *) SDCard_BSPIM_RxStsReg__STATUS_REG) +#define SDCard_RX_STATUS_PTR ( (reg8 *) SDCard_BSPIM_RxStsReg__STATUS_REG) + +#define SDCard_CONTROL_REG (* (reg8 *) \ + SDCard_BSPIM_BidirMode_SyncCtl_CtrlReg__CONTROL_REG) +#define SDCard_CONTROL_PTR ( (reg8 *) \ + SDCard_BSPIM_BidirMode_SyncCtl_CtrlReg__CONTROL_REG) + +#define SDCard_TX_STATUS_MASK_REG (* (reg8 *) SDCard_BSPIM_TxStsReg__MASK_REG) +#define SDCard_TX_STATUS_MASK_PTR ( (reg8 *) SDCard_BSPIM_TxStsReg__MASK_REG) +#define SDCard_RX_STATUS_MASK_REG (* (reg8 *) SDCard_BSPIM_RxStsReg__MASK_REG) +#define SDCard_RX_STATUS_MASK_PTR ( (reg8 *) SDCard_BSPIM_RxStsReg__MASK_REG) + +#define SDCard_TX_STATUS_ACTL_REG (* (reg8 *) SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG) +#define SDCard_TX_STATUS_ACTL_PTR ( (reg8 *) SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG) +#define SDCard_RX_STATUS_ACTL_REG (* (reg8 *) SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG) +#define SDCard_RX_STATUS_ACTL_PTR ( (reg8 *) SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG) + +#if(SDCard_USE_SECOND_DATAPATH) + #define SDCard_AUX_CONTROLDP1 (SDCard_AUX_CONTROL_DP1_REG) +#endif /* (SDCard_USE_SECOND_DATAPATH) */ + + +/*************************************** +* Register Constants +***************************************/ + +/* Status Register Definitions */ +#define SDCard_STS_SPI_DONE_SHIFT (0x00u) +#define SDCard_STS_TX_FIFO_EMPTY_SHIFT (0x01u) +#define SDCard_STS_TX_FIFO_NOT_FULL_SHIFT (0x02u) +#define SDCard_STS_BYTE_COMPLETE_SHIFT (0x03u) +#define SDCard_STS_SPI_IDLE_SHIFT (0x04u) +#define SDCard_STS_RX_FIFO_FULL_SHIFT (0x04u) +#define SDCard_STS_RX_FIFO_NOT_EMPTY_SHIFT (0x05u) +#define SDCard_STS_RX_FIFO_OVERRUN_SHIFT (0x06u) + +#define SDCard_STS_SPI_DONE ((uint8) (0x01u << SDCard_STS_SPI_DONE_SHIFT)) +#define SDCard_STS_TX_FIFO_EMPTY ((uint8) (0x01u << SDCard_STS_TX_FIFO_EMPTY_SHIFT)) +#define SDCard_STS_TX_FIFO_NOT_FULL ((uint8) (0x01u << SDCard_STS_TX_FIFO_NOT_FULL_SHIFT)) +#define SDCard_STS_BYTE_COMPLETE ((uint8) (0x01u << SDCard_STS_BYTE_COMPLETE_SHIFT)) +#define SDCard_STS_SPI_IDLE ((uint8) (0x01u << SDCard_STS_SPI_IDLE_SHIFT)) +#define SDCard_STS_RX_FIFO_FULL ((uint8) (0x01u << SDCard_STS_RX_FIFO_FULL_SHIFT)) +#define SDCard_STS_RX_FIFO_NOT_EMPTY ((uint8) (0x01u << SDCard_STS_RX_FIFO_NOT_EMPTY_SHIFT)) +#define SDCard_STS_RX_FIFO_OVERRUN ((uint8) (0x01u << SDCard_STS_RX_FIFO_OVERRUN_SHIFT)) + +/* TX and RX masks for clear on read bits */ +#define SDCard_TX_STS_CLR_ON_RD_BYTES_MASK (0x09u) +#define SDCard_RX_STS_CLR_ON_RD_BYTES_MASK (0x40u) + +/* StatusI Register Interrupt Enable Control Bits */ +/* As defined by the Register map for the AUX Control Register */ +#define SDCard_INT_ENABLE (0x10u) /* Enable interrupt from statusi */ +#define SDCard_TX_FIFO_CLR (0x01u) /* F0 - TX FIFO */ +#define SDCard_RX_FIFO_CLR (0x02u) /* F1 - RX FIFO */ +#define SDCard_FIFO_CLR (SDCard_TX_FIFO_CLR | SDCard_RX_FIFO_CLR) + +/* Bit Counter (7-bit) Control Register Bit Definitions */ +/* As defined by the Register map for the AUX Control Register */ +#define SDCard_CNTR_ENABLE (0x20u) /* Enable CNT7 */ + +/* Bi-Directional mode control bit */ +#define SDCard_CTRL_TX_SIGNAL_EN (0x01u) + +/* Datapath Auxillary Control Register definitions */ +#define SDCard_AUX_CTRL_FIFO0_CLR (0x01u) +#define SDCard_AUX_CTRL_FIFO1_CLR (0x02u) +#define SDCard_AUX_CTRL_FIFO0_LVL (0x04u) +#define SDCard_AUX_CTRL_FIFO1_LVL (0x08u) +#define SDCard_STATUS_ACTL_INT_EN_MASK (0x10u) + +/* Component disabled */ +#define SDCard_DISABLED (0u) + + +/*************************************** +* Macros +***************************************/ + +/* Returns true if componentn enabled */ +#define SDCard_IS_ENABLED (0u != (SDCard_TX_STATUS_ACTL_REG & SDCard_INT_ENABLE)) + +/* Retuns TX status register */ +#define SDCard_GET_STATUS_TX(swTxSts) ( (uint8)(SDCard_TX_STATUS_REG | \ + ((swTxSts) & SDCard_TX_STS_CLR_ON_RD_BYTES_MASK)) ) +/* Retuns RX status register */ +#define SDCard_GET_STATUS_RX(swRxSts) ( (uint8)(SDCard_RX_STATUS_REG | \ + ((swRxSts) & SDCard_RX_STS_CLR_ON_RD_BYTES_MASK)) ) + + +/*************************************** +* Obsolete definitions +***************************************/ + +/* Following definitions are for version compatibility. +* They are obsolete in SPIM v2_30. +* Please do not use it in new projects +*/ + +#define SDCard_WriteByte SDCard_WriteTxData +#define SDCard_ReadByte SDCard_ReadRxData +void SDCard_SetInterruptMode(uint8 intSrc) ; +uint8 SDCard_ReadStatus(void) ; +void SDCard_EnableInt(void) ; +void SDCard_DisableInt(void) ; + +/* Obsolete register names. Not to be used in new designs */ +#define SDCard_TXDATA (SDCard_TXDATA_REG) +#define SDCard_RXDATA (SDCard_RXDATA_REG) +#define SDCard_AUX_CONTROLDP0 (SDCard_AUX_CONTROL_DP0_REG) +#define SDCard_TXBUFFERREAD (SDCard_txBufferRead) +#define SDCard_TXBUFFERWRITE (SDCard_txBufferWrite) +#define SDCard_RXBUFFERREAD (SDCard_rxBufferRead) +#define SDCard_RXBUFFERWRITE (SDCard_rxBufferWrite) + +#define SDCard_COUNTER_PERIOD (SDCard_COUNTER_PERIOD_REG) +#define SDCard_COUNTER_CONTROL (SDCard_COUNTER_CONTROL_REG) +#define SDCard_STATUS (SDCard_TX_STATUS_REG) +#define SDCard_CONTROL (SDCard_CONTROL_REG) +#define SDCard_STATUS_MASK (SDCard_TX_STATUS_MASK_REG) +#define SDCard_STATUS_ACTL (SDCard_TX_STATUS_ACTL_REG) + +#define SDCard_INIT_INTERRUPTS_MASK (SDCard_INT_ON_SPI_DONE | \ + SDCard_INT_ON_TX_EMPTY | \ + SDCard_INT_ON_TX_NOT_FULL_DEF | \ + SDCard_INT_ON_RX_FULL | \ + SDCard_INT_ON_RX_NOT_EMPTY | \ + SDCard_INT_ON_RX_OVER | \ + SDCard_INT_ON_BYTE_COMP) + +/* Following definitions are for version Compatibility. +* They are obsolete in SPIM v2_40. +* Please do not use it in new projects +*/ + +#define SDCard_DataWidth (SDCard_DATA_WIDTH) +#define SDCard_InternalClockUsed (SDCard_INTERNAL_CLOCK) +#define SDCard_InternalTxInterruptEnabled (SDCard_INTERNAL_TX_INT_ENABLED) +#define SDCard_InternalRxInterruptEnabled (SDCard_INTERNAL_RX_INT_ENABLED) +#define SDCard_ModeUseZero (SDCard_MODE_USE_ZERO) +#define SDCard_BidirectionalMode (SDCard_BIDIRECTIONAL_MODE) +#define SDCard_Mode (SDCard_MODE) +#define SDCard_DATAWIDHT (SDCard_DATA_WIDTH) +#define SDCard_InternalInterruptEnabled (0u) + +#define SDCard_TXBUFFERSIZE (SDCard_TX_BUFFER_SIZE) +#define SDCard_RXBUFFERSIZE (SDCard_RX_BUFFER_SIZE) + +#define SDCard_TXBUFFER SDCard_txBuffer +#define SDCard_RXBUFFER SDCard_rxBuffer + +#endif /* (CY_SPIM_SDCard_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SDCard_INT.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SDCard_INT.c new file mode 100755 index 00000000..594ca67a --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SDCard_INT.c @@ -0,0 +1,189 @@ +/******************************************************************************* +* File Name: SDCard_INT.c +* Version 2.40 +* +* Description: +* This file provides all Interrupt Service Routine (ISR) for the SPI Master +* component. +* +* Note: +* None. +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SDCard_PVT.h" + +/* User code required at start of ISR */ +/* `#START SDCard_ISR_START_DEF` */ + +/* `#END` */ + + +/******************************************************************************* +* Function Name: SDCard_TX_ISR +******************************************************************************** +* +* Summary: +* Interrupt Service Routine for TX portion of the SPI Master. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* SDCard_txBufferWrite - used for the account of the bytes which +* have been written down in the TX software buffer. +* SDCard_txBufferRead - used for the account of the bytes which +* have been read from the TX software buffer, modified when exist data to +* sending and FIFO Not Full. +* SDCard_txBuffer[SDCard_TX_BUFFER_SIZE] - used to store +* data to sending. +* All described above Global variables are used when Software Buffer is used. +* +*******************************************************************************/ +CY_ISR(SDCard_TX_ISR) +{ + #if(SDCard_TX_SOFTWARE_BUF_ENABLED) + uint8 tmpStatus; + #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ + + /* User code required at start of ISR */ + /* `#START SDCard_TX_ISR_START` */ + + /* `#END` */ + + #if(SDCard_TX_SOFTWARE_BUF_ENABLED) + /* Check if TX data buffer is not empty and there is space in TX FIFO */ + while(SDCard_txBufferRead != SDCard_txBufferWrite) + { + tmpStatus = SDCard_GET_STATUS_TX(SDCard_swStatusTx); + SDCard_swStatusTx = tmpStatus; + + if(0u != (SDCard_swStatusTx & SDCard_STS_TX_FIFO_NOT_FULL)) + { + if(0u == SDCard_txBufferFull) + { + SDCard_txBufferRead++; + + if(SDCard_txBufferRead >= SDCard_TX_BUFFER_SIZE) + { + SDCard_txBufferRead = 0u; + } + } + else + { + SDCard_txBufferFull = 0u; + } + + /* Move data from the Buffer to the FIFO */ + CY_SET_REG8(SDCard_TXDATA_PTR, + SDCard_txBuffer[SDCard_txBufferRead]); + } + else + { + break; + } + } + + if(SDCard_txBufferRead == SDCard_txBufferWrite) + { + /* TX Buffer is EMPTY: disable interrupt on TX NOT FULL */ + SDCard_TX_STATUS_MASK_REG &= ((uint8) ~SDCard_STS_TX_FIFO_NOT_FULL); + } + + #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ + + /* User code required at end of ISR (Optional) */ + /* `#START SDCard_TX_ISR_END` */ + + /* `#END` */ +} + + +/******************************************************************************* +* Function Name: SDCard_RX_ISR +******************************************************************************** +* +* Summary: +* Interrupt Service Routine for RX portion of the SPI Master. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* SDCard_rxBufferWrite - used for the account of the bytes which +* have been written down in the RX software buffer modified when FIFO contains +* new data. +* SDCard_rxBufferRead - used for the account of the bytes which +* have been read from the RX software buffer, modified when overflow occurred. +* SDCard_rxBuffer[SDCard_RX_BUFFER_SIZE] - used to store +* received data, modified when FIFO contains new data. +* All described above Global variables are used when Software Buffer is used. +* +*******************************************************************************/ +CY_ISR(SDCard_RX_ISR) +{ + #if(SDCard_RX_SOFTWARE_BUF_ENABLED) + uint8 tmpStatus; + uint8 rxData; + #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */ + + /* User code required at start of ISR */ + /* `#START SDCard_RX_ISR_START` */ + + /* `#END` */ + + #if(SDCard_RX_SOFTWARE_BUF_ENABLED) + + tmpStatus = SDCard_GET_STATUS_RX(SDCard_swStatusRx); + SDCard_swStatusRx = tmpStatus; + + /* Check if RX data FIFO has some data to be moved into the RX Buffer */ + while(0u != (SDCard_swStatusRx & SDCard_STS_RX_FIFO_NOT_EMPTY)) + { + rxData = CY_GET_REG8(SDCard_RXDATA_PTR); + + /* Set next pointer. */ + SDCard_rxBufferWrite++; + if(SDCard_rxBufferWrite >= SDCard_RX_BUFFER_SIZE) + { + SDCard_rxBufferWrite = 0u; + } + + if(SDCard_rxBufferWrite == SDCard_rxBufferRead) + { + SDCard_rxBufferRead++; + if(SDCard_rxBufferRead >= SDCard_RX_BUFFER_SIZE) + { + SDCard_rxBufferRead = 0u; + } + + SDCard_rxBufferFull = 1u; + } + + /* Move data from the FIFO to the Buffer */ + SDCard_rxBuffer[SDCard_rxBufferWrite] = rxData; + + tmpStatus = SDCard_GET_STATUS_RX(SDCard_swStatusRx); + SDCard_swStatusRx = tmpStatus; + } + + #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */ + + /* User code required at end of ISR (Optional) */ + /* `#START SDCard_RX_ISR_END` */ + + /* `#END` */ +} + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SDCard_PM.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SDCard_PM.c new file mode 100755 index 00000000..69404519 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SDCard_PM.c @@ -0,0 +1,180 @@ +/******************************************************************************* +* File Name: SDCard_PM.c +* Version 2.40 +* +* Description: +* This file contains the setup, control and status commands to support +* component operations in low power mode. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SDCard_PVT.h" + +static SDCard_BACKUP_STRUCT SDCard_backup = +{ + SDCard_DISABLED, + SDCard_BITCTR_INIT, + #if(CY_UDB_V0) + SDCard_TX_INIT_INTERRUPTS_MASK, + SDCard_RX_INIT_INTERRUPTS_MASK + #endif /* CY_UDB_V0 */ +}; + + +/******************************************************************************* +* Function Name: SDCard_SaveConfig +******************************************************************************** +* +* Summary: +* Saves SPIM configuration. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global Variables: +* SDCard_backup - modified when non-retention registers are saved. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SDCard_SaveConfig(void) +{ + /* Store Status Mask registers */ + #if(CY_UDB_V0) + SDCard_backup.cntrPeriod = SDCard_COUNTER_PERIOD_REG; + SDCard_backup.saveSrTxIntMask = SDCard_TX_STATUS_MASK_REG; + SDCard_backup.saveSrRxIntMask = SDCard_RX_STATUS_MASK_REG; + #endif /* (CY_UDB_V0) */ +} + + +/******************************************************************************* +* Function Name: SDCard_RestoreConfig +******************************************************************************** +* +* Summary: +* Restores SPIM configuration. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global Variables: +* SDCard_backup - used when non-retention registers are restored. +* +* Side Effects: +* If this API is called without first calling SaveConfig then in the following +* registers will be default values from Customizer: +* SDCard_STATUS_MASK_REG and SDCard_COUNTER_PERIOD_REG. +* +*******************************************************************************/ +void SDCard_RestoreConfig(void) +{ + /* Restore the data, saved by SaveConfig() function */ + #if(CY_UDB_V0) + SDCard_COUNTER_PERIOD_REG = SDCard_backup.cntrPeriod; + SDCard_TX_STATUS_MASK_REG = ((uint8) SDCard_backup.saveSrTxIntMask); + SDCard_RX_STATUS_MASK_REG = ((uint8) SDCard_backup.saveSrRxIntMask); + #endif /* (CY_UDB_V0) */ +} + + +/******************************************************************************* +* Function Name: SDCard_Sleep +******************************************************************************** +* +* Summary: +* Prepare SPIM Component goes to sleep. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global Variables: +* SDCard_backup - modified when non-retention registers are saved. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SDCard_Sleep(void) +{ + /* Save components enable state */ + SDCard_backup.enableState = ((uint8) SDCard_IS_ENABLED); + + SDCard_Stop(); + SDCard_SaveConfig(); +} + + +/******************************************************************************* +* Function Name: SDCard_Wakeup +******************************************************************************** +* +* Summary: +* Prepare SPIM Component to wake up. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global Variables: +* SDCard_backup - used when non-retention registers are restored. +* SDCard_txBufferWrite - modified every function call - resets to +* zero. +* SDCard_txBufferRead - modified every function call - resets to +* zero. +* SDCard_rxBufferWrite - modified every function call - resets to +* zero. +* SDCard_rxBufferRead - modified every function call - resets to +* zero. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SDCard_Wakeup(void) +{ + SDCard_RestoreConfig(); + + #if(SDCard_RX_SOFTWARE_BUF_ENABLED) + SDCard_rxBufferFull = 0u; + SDCard_rxBufferRead = 0u; + SDCard_rxBufferWrite = 0u; + #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */ + + #if(SDCard_TX_SOFTWARE_BUF_ENABLED) + SDCard_txBufferFull = 0u; + SDCard_txBufferRead = 0u; + SDCard_txBufferWrite = 0u; + #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ + + /* Clear any data from the RX and TX FIFO */ + SDCard_ClearFIFO(); + + /* Restore components block enable state */ + if(0u != SDCard_backup.enableState) + { + SDCard_Enable(); + } +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SDCard_PVT.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SDCard_PVT.h new file mode 100755 index 00000000..523d0257 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SDCard_PVT.h @@ -0,0 +1,53 @@ +/******************************************************************************* +* File Name: .h +* Version 2.40 +* +* Description: +* This private header file contains internal definitions for the SPIM +* component. Do not use these definitions directly in your application. +* +* Note: +* +******************************************************************************** +* Copyright 2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_SPIM_PVT_SDCard_H) +#define CY_SPIM_PVT_SDCard_H + +#include "SDCard.h" + + +/********************************** +* Functions with external linkage +**********************************/ + + +/********************************** +* Variables with external linkage +**********************************/ + +extern volatile uint8 SDCard_swStatusTx; +extern volatile uint8 SDCard_swStatusRx; + +#if(SDCard_TX_SOFTWARE_BUF_ENABLED) + extern volatile uint8 SDCard_txBuffer[SDCard_TX_BUFFER_SIZE]; + extern volatile uint8 SDCard_txBufferRead; + extern volatile uint8 SDCard_txBufferWrite; + extern volatile uint8 SDCard_txBufferFull; +#endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ + +#if(SDCard_RX_SOFTWARE_BUF_ENABLED) + extern volatile uint8 SDCard_rxBuffer[SDCard_RX_BUFFER_SIZE]; + extern volatile uint8 SDCard_rxBufferRead; + extern volatile uint8 SDCard_rxBufferWrite; + extern volatile uint8 SDCard_rxBufferFull; +#endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */ + +#endif /* CY_SPIM_PVT_SDCard_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_CD.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_CD.c new file mode 100755 index 00000000..27d45e34 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_CD.c @@ -0,0 +1,137 @@ +/******************************************************************************* +* File Name: SD_CD.c +* Version 1.90 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SD_CD.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + SD_CD__PORT == 15 && ((SD_CD__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: SD_CD_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void SD_CD_Write(uint8 value) +{ + uint8 staticBits = (SD_CD_DR & (uint8)(~SD_CD_MASK)); + SD_CD_DR = staticBits | ((uint8)(value << SD_CD_SHIFT) & SD_CD_MASK); +} + + +/******************************************************************************* +* Function Name: SD_CD_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to this drive mode. +* +* Return: +* None +* +*******************************************************************************/ +void SD_CD_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(SD_CD_0, mode); +} + + +/******************************************************************************* +* Function Name: SD_CD_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro SD_CD_ReadPS calls this function. +* +*******************************************************************************/ +uint8 SD_CD_Read(void) +{ + return (SD_CD_PS & SD_CD_MASK) >> SD_CD_SHIFT; +} + + +/******************************************************************************* +* Function Name: SD_CD_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 SD_CD_ReadDataReg(void) +{ + return (SD_CD_DR & SD_CD_MASK) >> SD_CD_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(SD_CD_INTSTAT) + + /******************************************************************************* + * Function Name: SD_CD_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 SD_CD_ClearInterrupt(void) + { + return (SD_CD_INTSTAT & SD_CD_MASK) >> SD_CD_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_CD.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_CD.h new file mode 100755 index 00000000..a6b71774 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_CD.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: SD_CD.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_CD_H) /* Pins SD_CD_H */ +#define CY_PINS_SD_CD_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SD_CD_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SD_CD__PORT == 15 && ((SD_CD__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void SD_CD_Write(uint8 value) ; +void SD_CD_SetDriveMode(uint8 mode) ; +uint8 SD_CD_ReadDataReg(void) ; +uint8 SD_CD_Read(void) ; +uint8 SD_CD_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define SD_CD_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define SD_CD_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define SD_CD_DM_RES_UP PIN_DM_RES_UP +#define SD_CD_DM_RES_DWN PIN_DM_RES_DWN +#define SD_CD_DM_OD_LO PIN_DM_OD_LO +#define SD_CD_DM_OD_HI PIN_DM_OD_HI +#define SD_CD_DM_STRONG PIN_DM_STRONG +#define SD_CD_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define SD_CD_MASK SD_CD__MASK +#define SD_CD_SHIFT SD_CD__SHIFT +#define SD_CD_WIDTH 1u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SD_CD_PS (* (reg8 *) SD_CD__PS) +/* Data Register */ +#define SD_CD_DR (* (reg8 *) SD_CD__DR) +/* Port Number */ +#define SD_CD_PRT_NUM (* (reg8 *) SD_CD__PRT) +/* Connect to Analog Globals */ +#define SD_CD_AG (* (reg8 *) SD_CD__AG) +/* Analog MUX bux enable */ +#define SD_CD_AMUX (* (reg8 *) SD_CD__AMUX) +/* Bidirectional Enable */ +#define SD_CD_BIE (* (reg8 *) SD_CD__BIE) +/* Bit-mask for Aliased Register Access */ +#define SD_CD_BIT_MASK (* (reg8 *) SD_CD__BIT_MASK) +/* Bypass Enable */ +#define SD_CD_BYP (* (reg8 *) SD_CD__BYP) +/* Port wide control signals */ +#define SD_CD_CTL (* (reg8 *) SD_CD__CTL) +/* Drive Modes */ +#define SD_CD_DM0 (* (reg8 *) SD_CD__DM0) +#define SD_CD_DM1 (* (reg8 *) SD_CD__DM1) +#define SD_CD_DM2 (* (reg8 *) SD_CD__DM2) +/* Input Buffer Disable Override */ +#define SD_CD_INP_DIS (* (reg8 *) SD_CD__INP_DIS) +/* LCD Common or Segment Drive */ +#define SD_CD_LCD_COM_SEG (* (reg8 *) SD_CD__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SD_CD_LCD_EN (* (reg8 *) SD_CD__LCD_EN) +/* Slew Rate Control */ +#define SD_CD_SLW (* (reg8 *) SD_CD__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SD_CD_PRTDSI__CAPS_SEL (* (reg8 *) SD_CD__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SD_CD_PRTDSI__DBL_SYNC_IN (* (reg8 *) SD_CD__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SD_CD_PRTDSI__OE_SEL0 (* (reg8 *) SD_CD__PRTDSI__OE_SEL0) +#define SD_CD_PRTDSI__OE_SEL1 (* (reg8 *) SD_CD__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SD_CD_PRTDSI__OUT_SEL0 (* (reg8 *) SD_CD__PRTDSI__OUT_SEL0) +#define SD_CD_PRTDSI__OUT_SEL1 (* (reg8 *) SD_CD__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SD_CD_PRTDSI__SYNC_OUT (* (reg8 *) SD_CD__PRTDSI__SYNC_OUT) + + +#if defined(SD_CD__INTSTAT) /* Interrupt Registers */ + + #define SD_CD_INTSTAT (* (reg8 *) SD_CD__INTSTAT) + #define SD_CD_SNAP (* (reg8 *) SD_CD__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SD_CD_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_CD_aliases.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_CD_aliases.h new file mode 100755 index 00000000..6d4a2cd0 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_CD_aliases.h @@ -0,0 +1,32 @@ +/******************************************************************************* +* File Name: SD_CD.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_CD_ALIASES_H) /* Pins SD_CD_ALIASES_H */ +#define CY_PINS_SD_CD_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SD_CD_0 SD_CD__0__PC + +#endif /* End Pins SD_CD_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_CS.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_CS.c new file mode 100755 index 00000000..e6fe1f41 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_CS.c @@ -0,0 +1,137 @@ +/******************************************************************************* +* File Name: SD_CS.c +* Version 1.90 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SD_CS.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + SD_CS__PORT == 15 && ((SD_CS__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: SD_CS_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void SD_CS_Write(uint8 value) +{ + uint8 staticBits = (SD_CS_DR & (uint8)(~SD_CS_MASK)); + SD_CS_DR = staticBits | ((uint8)(value << SD_CS_SHIFT) & SD_CS_MASK); +} + + +/******************************************************************************* +* Function Name: SD_CS_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to this drive mode. +* +* Return: +* None +* +*******************************************************************************/ +void SD_CS_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(SD_CS_0, mode); +} + + +/******************************************************************************* +* Function Name: SD_CS_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro SD_CS_ReadPS calls this function. +* +*******************************************************************************/ +uint8 SD_CS_Read(void) +{ + return (SD_CS_PS & SD_CS_MASK) >> SD_CS_SHIFT; +} + + +/******************************************************************************* +* Function Name: SD_CS_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 SD_CS_ReadDataReg(void) +{ + return (SD_CS_DR & SD_CS_MASK) >> SD_CS_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(SD_CS_INTSTAT) + + /******************************************************************************* + * Function Name: SD_CS_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 SD_CS_ClearInterrupt(void) + { + return (SD_CS_INTSTAT & SD_CS_MASK) >> SD_CS_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_CS.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_CS.h new file mode 100755 index 00000000..c2d5c0de --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_CS.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: SD_CS.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_CS_H) /* Pins SD_CS_H */ +#define CY_PINS_SD_CS_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SD_CS_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SD_CS__PORT == 15 && ((SD_CS__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void SD_CS_Write(uint8 value) ; +void SD_CS_SetDriveMode(uint8 mode) ; +uint8 SD_CS_ReadDataReg(void) ; +uint8 SD_CS_Read(void) ; +uint8 SD_CS_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define SD_CS_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define SD_CS_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define SD_CS_DM_RES_UP PIN_DM_RES_UP +#define SD_CS_DM_RES_DWN PIN_DM_RES_DWN +#define SD_CS_DM_OD_LO PIN_DM_OD_LO +#define SD_CS_DM_OD_HI PIN_DM_OD_HI +#define SD_CS_DM_STRONG PIN_DM_STRONG +#define SD_CS_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define SD_CS_MASK SD_CS__MASK +#define SD_CS_SHIFT SD_CS__SHIFT +#define SD_CS_WIDTH 1u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SD_CS_PS (* (reg8 *) SD_CS__PS) +/* Data Register */ +#define SD_CS_DR (* (reg8 *) SD_CS__DR) +/* Port Number */ +#define SD_CS_PRT_NUM (* (reg8 *) SD_CS__PRT) +/* Connect to Analog Globals */ +#define SD_CS_AG (* (reg8 *) SD_CS__AG) +/* Analog MUX bux enable */ +#define SD_CS_AMUX (* (reg8 *) SD_CS__AMUX) +/* Bidirectional Enable */ +#define SD_CS_BIE (* (reg8 *) SD_CS__BIE) +/* Bit-mask for Aliased Register Access */ +#define SD_CS_BIT_MASK (* (reg8 *) SD_CS__BIT_MASK) +/* Bypass Enable */ +#define SD_CS_BYP (* (reg8 *) SD_CS__BYP) +/* Port wide control signals */ +#define SD_CS_CTL (* (reg8 *) SD_CS__CTL) +/* Drive Modes */ +#define SD_CS_DM0 (* (reg8 *) SD_CS__DM0) +#define SD_CS_DM1 (* (reg8 *) SD_CS__DM1) +#define SD_CS_DM2 (* (reg8 *) SD_CS__DM2) +/* Input Buffer Disable Override */ +#define SD_CS_INP_DIS (* (reg8 *) SD_CS__INP_DIS) +/* LCD Common or Segment Drive */ +#define SD_CS_LCD_COM_SEG (* (reg8 *) SD_CS__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SD_CS_LCD_EN (* (reg8 *) SD_CS__LCD_EN) +/* Slew Rate Control */ +#define SD_CS_SLW (* (reg8 *) SD_CS__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SD_CS_PRTDSI__CAPS_SEL (* (reg8 *) SD_CS__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SD_CS_PRTDSI__DBL_SYNC_IN (* (reg8 *) SD_CS__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SD_CS_PRTDSI__OE_SEL0 (* (reg8 *) SD_CS__PRTDSI__OE_SEL0) +#define SD_CS_PRTDSI__OE_SEL1 (* (reg8 *) SD_CS__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SD_CS_PRTDSI__OUT_SEL0 (* (reg8 *) SD_CS__PRTDSI__OUT_SEL0) +#define SD_CS_PRTDSI__OUT_SEL1 (* (reg8 *) SD_CS__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SD_CS_PRTDSI__SYNC_OUT (* (reg8 *) SD_CS__PRTDSI__SYNC_OUT) + + +#if defined(SD_CS__INTSTAT) /* Interrupt Registers */ + + #define SD_CS_INTSTAT (* (reg8 *) SD_CS__INTSTAT) + #define SD_CS_SNAP (* (reg8 *) SD_CS__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SD_CS_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_CS_aliases.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_CS_aliases.h new file mode 100755 index 00000000..32d2dca5 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_CS_aliases.h @@ -0,0 +1,32 @@ +/******************************************************************************* +* File Name: SD_CS.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_CS_ALIASES_H) /* Pins SD_CS_ALIASES_H */ +#define CY_PINS_SD_CS_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SD_CS_0 SD_CS__0__PC + +#endif /* End Pins SD_CS_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_Clk_Ctl.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_Clk_Ctl.c new file mode 100755 index 00000000..f674b358 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_Clk_Ctl.c @@ -0,0 +1,63 @@ +/******************************************************************************* +* File Name: SD_Clk_Ctl.c +* Version 1.70 +* +* Description: +* This file contains API to enable firmware control of a Control Register. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SD_Clk_Ctl.h" + +#if !defined(SD_Clk_Ctl_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */ + +/******************************************************************************* +* Function Name: SD_Clk_Ctl_Write +******************************************************************************** +* +* Summary: +* Write a byte to the Control Register. +* +* Parameters: +* control: The value to be assigned to the Control Register. +* +* Return: +* None. +* +*******************************************************************************/ +void SD_Clk_Ctl_Write(uint8 control) +{ + SD_Clk_Ctl_Control = control; +} + + +/******************************************************************************* +* Function Name: SD_Clk_Ctl_Read +******************************************************************************** +* +* Summary: +* Reads the current value assigned to the Control Register. +* +* Parameters: +* None. +* +* Return: +* Returns the current value in the Control Register. +* +*******************************************************************************/ +uint8 SD_Clk_Ctl_Read(void) +{ + return SD_Clk_Ctl_Control; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_Clk_Ctl.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_Clk_Ctl.h new file mode 100755 index 00000000..862a6513 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_Clk_Ctl.h @@ -0,0 +1,42 @@ +/******************************************************************************* +* File Name: SD_Clk_Ctl.h +* Version 1.70 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CONTROL_REG_SD_Clk_Ctl_H) /* CY_CONTROL_REG_SD_Clk_Ctl_H */ +#define CY_CONTROL_REG_SD_Clk_Ctl_H + +#include "cytypes.h" + + +/*************************************** +* Function Prototypes +***************************************/ + +void SD_Clk_Ctl_Write(uint8 control) ; +uint8 SD_Clk_Ctl_Read(void) ; + + +/*************************************** +* Registers +***************************************/ + +/* Control Register */ +#define SD_Clk_Ctl_Control (* (reg8 *) SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG ) +#define SD_Clk_Ctl_Control_PTR ( (reg8 *) SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG ) + +#endif /* End CY_CONTROL_REG_SD_Clk_Ctl_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_Data_Clk.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_Data_Clk.c new file mode 100755 index 00000000..f90dc2cc --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_Data_Clk.c @@ -0,0 +1,521 @@ +/******************************************************************************* +* File Name: SD_Data_Clk.c +* Version 2.10 +* +* Description: +* This file provides the source code to the API for the clock component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "SD_Data_Clk.h" + +/* Clock Distribution registers. */ +#define CLK_DIST_LD (* (reg8 *) CYREG_CLKDIST_LD) +#define CLK_DIST_BCFG2 (* (reg8 *) CYREG_CLKDIST_BCFG2) +#define BCFG2_MASK (0x80u) +#define CLK_DIST_DMASK (* (reg8 *) CYREG_CLKDIST_DMASK) +#define CLK_DIST_AMASK (* (reg8 *) CYREG_CLKDIST_AMASK) + +#define HAS_CLKDIST_LD_DISABLE (CY_PSOC3 || CY_PSOC5LP) + + +/******************************************************************************* +* Function Name: SD_Data_Clk_Start +******************************************************************************** +* +* Summary: +* Starts the clock. Note that on startup, clocks may be already running if the +* "Start on Reset" option is enabled in the DWR. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Data_Clk_Start(void) +{ + /* Set the bit to enable the clock. */ + SD_Data_Clk_CLKEN |= SD_Data_Clk_CLKEN_MASK; + SD_Data_Clk_CLKSTBY |= SD_Data_Clk_CLKSTBY_MASK; +} + + +/******************************************************************************* +* Function Name: SD_Data_Clk_Stop +******************************************************************************** +* +* Summary: +* Stops the clock and returns immediately. This API does not require the +* source clock to be running but may return before the hardware is actually +* disabled. If the settings of the clock are changed after calling this +* function, the clock may glitch when it is started. To avoid the clock +* glitch, use the StopBlock function. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Data_Clk_Stop(void) +{ + /* Clear the bit to disable the clock. */ + SD_Data_Clk_CLKEN &= (uint8)(~SD_Data_Clk_CLKEN_MASK); + SD_Data_Clk_CLKSTBY &= (uint8)(~SD_Data_Clk_CLKSTBY_MASK); +} + + +#if(CY_PSOC3 || CY_PSOC5LP) + + +/******************************************************************************* +* Function Name: SD_Data_Clk_StopBlock +******************************************************************************** +* +* Summary: +* Stops the clock and waits for the hardware to actually be disabled before +* returning. This ensures that the clock is never truncated (high part of the +* cycle will terminate before the clock is disabled and the API returns). +* Note that the source clock must be running or this API will never return as +* a stopped clock cannot be disabled. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Data_Clk_StopBlock(void) +{ + if ((SD_Data_Clk_CLKEN & SD_Data_Clk_CLKEN_MASK) != 0u) + { +#if HAS_CLKDIST_LD_DISABLE + uint16 oldDivider; + + CLK_DIST_LD = 0u; + + /* Clear all the mask bits except ours. */ +#if defined(SD_Data_Clk__CFG3) + CLK_DIST_AMASK = SD_Data_Clk_CLKEN_MASK; + CLK_DIST_DMASK = 0x00u; +#else + CLK_DIST_DMASK = SD_Data_Clk_CLKEN_MASK; + CLK_DIST_AMASK = 0x00u; +#endif /* SD_Data_Clk__CFG3 */ + + /* Clear mask of bus clock. */ + CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK); + + oldDivider = CY_GET_REG16(SD_Data_Clk_DIV_PTR); + CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider); + CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD; + + /* Wait for clock to be disabled */ + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } +#endif /* HAS_CLKDIST_LD_DISABLE */ + + /* Clear the bit to disable the clock. */ + SD_Data_Clk_CLKEN &= (uint8)(~SD_Data_Clk_CLKEN_MASK); + SD_Data_Clk_CLKSTBY &= (uint8)(~SD_Data_Clk_CLKSTBY_MASK); + +#if HAS_CLKDIST_LD_DISABLE + /* Clear the disable bit */ + CLK_DIST_LD = 0x00u; + CY_SET_REG16(SD_Data_Clk_DIV_PTR, oldDivider); +#endif /* HAS_CLKDIST_LD_DISABLE */ + } +} +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + +/******************************************************************************* +* Function Name: SD_Data_Clk_StandbyPower +******************************************************************************** +* +* Summary: +* Sets whether the clock is active in standby mode. +* +* Parameters: +* state: 0 to disable clock during standby, nonzero to enable. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Data_Clk_StandbyPower(uint8 state) +{ + if(state == 0u) + { + SD_Data_Clk_CLKSTBY &= (uint8)(~SD_Data_Clk_CLKSTBY_MASK); + } + else + { + SD_Data_Clk_CLKSTBY |= SD_Data_Clk_CLKSTBY_MASK; + } +} + + +/******************************************************************************* +* Function Name: SD_Data_Clk_SetDividerRegister +******************************************************************************** +* +* Summary: +* Modifies the clock divider and, thus, the frequency. When the clock divider +* register is set to zero or changed from zero, the clock will be temporarily +* disabled in order to change the SSS mode bit. If the clock is enabled when +* SetDividerRegister is called, then the source clock must be running. +* +* Parameters: +* clkDivider: Divider register value (0-65,535). This value is NOT the +* divider; the clock hardware divides by clkDivider plus one. For example, +* to divide the clock by 2, this parameter should be set to 1. +* restart: If nonzero, restarts the clock divider: the current clock cycle +* will be truncated and the new divide value will take effect immediately. If +* zero, the new divide value will take effect at the end of the current clock +* cycle. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Data_Clk_SetDividerRegister(uint16 clkDivider, uint8 restart) + +{ + uint8 enabled; + + uint8 currSrc = SD_Data_Clk_GetSourceRegister(); + uint16 oldDivider = SD_Data_Clk_GetDividerRegister(); + + if (clkDivider != oldDivider) + { + enabled = SD_Data_Clk_CLKEN & SD_Data_Clk_CLKEN_MASK; + + if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u))) + { + /* Moving to/from SSS requires correct ordering to prevent halting the clock */ + if (oldDivider == 0u) + { + /* Moving away from SSS, set the divider first so when SSS is cleared we */ + /* don't halt the clock. Using the shadow load isn't required as the */ + /* divider is ignored while SSS is set. */ + CY_SET_REG16(SD_Data_Clk_DIV_PTR, clkDivider); + SD_Data_Clk_MOD_SRC &= (uint8)(~CYCLK_SSS); + } + else + { + /* Moving to SSS, set SSS which then ignores the divider and we can set */ + /* it without bothering with the shadow load. */ + SD_Data_Clk_MOD_SRC |= CYCLK_SSS; + CY_SET_REG16(SD_Data_Clk_DIV_PTR, clkDivider); + } + } + else + { + + if (enabled != 0u) + { + CLK_DIST_LD = 0x00u; + + /* Clear all the mask bits except ours. */ +#if defined(SD_Data_Clk__CFG3) + CLK_DIST_AMASK = SD_Data_Clk_CLKEN_MASK; + CLK_DIST_DMASK = 0x00u; +#else + CLK_DIST_DMASK = SD_Data_Clk_CLKEN_MASK; + CLK_DIST_AMASK = 0x00u; +#endif /* SD_Data_Clk__CFG3 */ + /* Clear mask of bus clock. */ + CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK); + + /* If clock is currently enabled, disable it if async or going from N-to-1*/ + if (((SD_Data_Clk_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u)) + { +#if HAS_CLKDIST_LD_DISABLE + CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider); + CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD; + + /* Wait for clock to be disabled */ + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } +#endif /* HAS_CLKDIST_LD_DISABLE */ + + SD_Data_Clk_CLKEN &= (uint8)(~SD_Data_Clk_CLKEN_MASK); + +#if HAS_CLKDIST_LD_DISABLE + /* Clear the disable bit */ + CLK_DIST_LD = 0x00u; +#endif /* HAS_CLKDIST_LD_DISABLE */ + } + } + + /* Load divide value. */ + if ((SD_Data_Clk_CLKEN & SD_Data_Clk_CLKEN_MASK) != 0u) + { + /* If the clock is still enabled, use the shadow registers */ + CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider); + + CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u)); + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } + } + else + { + /* If the clock is disabled, set the divider directly */ + CY_SET_REG16(SD_Data_Clk_DIV_PTR, clkDivider); + SD_Data_Clk_CLKEN |= enabled; + } + } + } +} + + +/******************************************************************************* +* Function Name: SD_Data_Clk_GetDividerRegister +******************************************************************************** +* +* Summary: +* Gets the clock divider register value. +* +* Parameters: +* None +* +* Returns: +* Divide value of the clock minus 1. For example, if the clock is set to +* divide by 2, the return value will be 1. +* +*******************************************************************************/ +uint16 SD_Data_Clk_GetDividerRegister(void) +{ + return CY_GET_REG16(SD_Data_Clk_DIV_PTR); +} + + +/******************************************************************************* +* Function Name: SD_Data_Clk_SetModeRegister +******************************************************************************** +* +* Summary: +* Sets flags that control the operating mode of the clock. This function only +* changes flags from 0 to 1; flags that are already 1 will remain unchanged. +* To clear flags, use the ClearModeRegister function. The clock must be +* disabled before changing the mode. +* +* Parameters: +* clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5, +* clkMode should be a set of the following optional bits or'ed together. +* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will +* occur when the divider count reaches half of the divide +* value. +* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock +* is asserted for approximately half of its period. When +* disabled, the output clock is asserted for one period of the +* source clock. +* - CYCLK_SYNC Enable output synchronization to master clock. This should +* be enabled for all synchronous clocks. +* See the Technical Reference Manual for details about setting the mode of +* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Data_Clk_SetModeRegister(uint8 modeBitMask) +{ + SD_Data_Clk_MOD_SRC |= modeBitMask & (uint8)SD_Data_Clk_MODE_MASK; +} + + +/******************************************************************************* +* Function Name: SD_Data_Clk_ClearModeRegister +******************************************************************************** +* +* Summary: +* Clears flags that control the operating mode of the clock. This function +* only changes flags from 1 to 0; flags that are already 0 will remain +* unchanged. To set flags, use the SetModeRegister function. The clock must be +* disabled before changing the mode. +* +* Parameters: +* clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5, +* clkMode should be a set of the following optional bits or'ed together. +* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will +* occur when the divider count reaches half of the divide +* value. +* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock +* is asserted for approximately half of its period. When +* disabled, the output clock is asserted for one period of the +* source clock. +* - CYCLK_SYNC Enable output synchronization to master clock. This should +* be enabled for all synchronous clocks. +* See the Technical Reference Manual for details about setting the mode of +* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Data_Clk_ClearModeRegister(uint8 modeBitMask) +{ + SD_Data_Clk_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(SD_Data_Clk_MODE_MASK)); +} + + +/******************************************************************************* +* Function Name: SD_Data_Clk_GetModeRegister +******************************************************************************** +* +* Summary: +* Gets the clock mode register value. +* +* Parameters: +* None +* +* Returns: +* Bit mask representing the enabled mode bits. See the SetModeRegister and +* ClearModeRegister descriptions for details about the mode bits. +* +*******************************************************************************/ +uint8 SD_Data_Clk_GetModeRegister(void) +{ + return SD_Data_Clk_MOD_SRC & (uint8)(SD_Data_Clk_MODE_MASK); +} + + +/******************************************************************************* +* Function Name: SD_Data_Clk_SetSourceRegister +******************************************************************************** +* +* Summary: +* Sets the input source of the clock. The clock must be disabled before +* changing the source. The old and new clock sources must be running. +* +* Parameters: +* clkSource: For PSoC 3 and PSoC 5 devices, clkSource should be one of the +* following input sources: +* - CYCLK_SRC_SEL_SYNC_DIG +* - CYCLK_SRC_SEL_IMO +* - CYCLK_SRC_SEL_XTALM +* - CYCLK_SRC_SEL_ILO +* - CYCLK_SRC_SEL_PLL +* - CYCLK_SRC_SEL_XTALK +* - CYCLK_SRC_SEL_DSI_G +* - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A +* See the Technical Reference Manual for details on clock sources. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Data_Clk_SetSourceRegister(uint8 clkSource) +{ + uint16 currDiv = SD_Data_Clk_GetDividerRegister(); + uint8 oldSrc = SD_Data_Clk_GetSourceRegister(); + + if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && + (clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u)) + { + /* Switching to Master and divider is 1, set SSS, which will output master, */ + /* then set the source so we are consistent. */ + SD_Data_Clk_MOD_SRC |= CYCLK_SSS; + SD_Data_Clk_MOD_SRC = + (SD_Data_Clk_MOD_SRC & (uint8)(~SD_Data_Clk_SRC_SEL_MSK)) | clkSource; + } + else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && + (clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u)) + { + /* Switching from Master to not and divider is 1, set source, so we don't */ + /* lock when we clear SSS. */ + SD_Data_Clk_MOD_SRC = + (SD_Data_Clk_MOD_SRC & (uint8)(~SD_Data_Clk_SRC_SEL_MSK)) | clkSource; + SD_Data_Clk_MOD_SRC &= (uint8)(~CYCLK_SSS); + } + else + { + SD_Data_Clk_MOD_SRC = + (SD_Data_Clk_MOD_SRC & (uint8)(~SD_Data_Clk_SRC_SEL_MSK)) | clkSource; + } +} + + +/******************************************************************************* +* Function Name: SD_Data_Clk_GetSourceRegister +******************************************************************************** +* +* Summary: +* Gets the input source of the clock. +* +* Parameters: +* None +* +* Returns: +* The input source of the clock. See SetSourceRegister for details. +* +*******************************************************************************/ +uint8 SD_Data_Clk_GetSourceRegister(void) +{ + return SD_Data_Clk_MOD_SRC & SD_Data_Clk_SRC_SEL_MSK; +} + + +#if defined(SD_Data_Clk__CFG3) + + +/******************************************************************************* +* Function Name: SD_Data_Clk_SetPhaseRegister +******************************************************************************** +* +* Summary: +* Sets the phase delay of the analog clock. This function is only available +* for analog clocks. The clock must be disabled before changing the phase +* delay to avoid glitches. +* +* Parameters: +* clkPhase: Amount to delay the phase of the clock, in 1.0ns increments. +* clkPhase must be from 1 to 11 inclusive. Other values, including 0, +* disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11 +* produces a 10ns delay. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Data_Clk_SetPhaseRegister(uint8 clkPhase) +{ + SD_Data_Clk_PHASE = clkPhase & SD_Data_Clk_PHASE_MASK; +} + + +/******************************************************************************* +* Function Name: SD_Data_Clk_GetPhase +******************************************************************************** +* +* Summary: +* Gets the phase delay of the analog clock. This function is only available +* for analog clocks. +* +* Parameters: +* None +* +* Returns: +* Phase of the analog clock. See SetPhaseRegister for details. +* +*******************************************************************************/ +uint8 SD_Data_Clk_GetPhaseRegister(void) +{ + return SD_Data_Clk_PHASE & SD_Data_Clk_PHASE_MASK; +} + +#endif /* SD_Data_Clk__CFG3 */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_Data_Clk.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_Data_Clk.h new file mode 100755 index 00000000..ac373a31 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_Data_Clk.h @@ -0,0 +1,124 @@ +/******************************************************************************* +* File Name: SD_Data_Clk.h +* Version 2.10 +* +* Description: +* Provides the function and constant definitions for the clock component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CLOCK_SD_Data_Clk_H) +#define CY_CLOCK_SD_Data_Clk_H + +#include +#include + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ + +/* Check to see if required defines such as CY_PSOC5LP are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5LP) + #error Component cy_clock_v2_10 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5LP) */ + + +/*************************************** +* Function Prototypes +***************************************/ + +void SD_Data_Clk_Start(void) ; +void SD_Data_Clk_Stop(void) ; + +#if(CY_PSOC3 || CY_PSOC5LP) +void SD_Data_Clk_StopBlock(void) ; +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + +void SD_Data_Clk_StandbyPower(uint8 state) ; +void SD_Data_Clk_SetDividerRegister(uint16 clkDivider, uint8 restart) + ; +uint16 SD_Data_Clk_GetDividerRegister(void) ; +void SD_Data_Clk_SetModeRegister(uint8 modeBitMask) ; +void SD_Data_Clk_ClearModeRegister(uint8 modeBitMask) ; +uint8 SD_Data_Clk_GetModeRegister(void) ; +void SD_Data_Clk_SetSourceRegister(uint8 clkSource) ; +uint8 SD_Data_Clk_GetSourceRegister(void) ; +#if defined(SD_Data_Clk__CFG3) +void SD_Data_Clk_SetPhaseRegister(uint8 clkPhase) ; +uint8 SD_Data_Clk_GetPhaseRegister(void) ; +#endif /* defined(SD_Data_Clk__CFG3) */ + +#define SD_Data_Clk_Enable() SD_Data_Clk_Start() +#define SD_Data_Clk_Disable() SD_Data_Clk_Stop() +#define SD_Data_Clk_SetDivider(clkDivider) SD_Data_Clk_SetDividerRegister(clkDivider, 1u) +#define SD_Data_Clk_SetDividerValue(clkDivider) SD_Data_Clk_SetDividerRegister((clkDivider) - 1u, 1u) +#define SD_Data_Clk_SetMode(clkMode) SD_Data_Clk_SetModeRegister(clkMode) +#define SD_Data_Clk_SetSource(clkSource) SD_Data_Clk_SetSourceRegister(clkSource) +#if defined(SD_Data_Clk__CFG3) +#define SD_Data_Clk_SetPhase(clkPhase) SD_Data_Clk_SetPhaseRegister(clkPhase) +#define SD_Data_Clk_SetPhaseValue(clkPhase) SD_Data_Clk_SetPhaseRegister((clkPhase) + 1u) +#endif /* defined(SD_Data_Clk__CFG3) */ + + +/*************************************** +* Registers +***************************************/ + +/* Register to enable or disable the clock */ +#define SD_Data_Clk_CLKEN (* (reg8 *) SD_Data_Clk__PM_ACT_CFG) +#define SD_Data_Clk_CLKEN_PTR ((reg8 *) SD_Data_Clk__PM_ACT_CFG) + +/* Register to enable or disable the clock */ +#define SD_Data_Clk_CLKSTBY (* (reg8 *) SD_Data_Clk__PM_STBY_CFG) +#define SD_Data_Clk_CLKSTBY_PTR ((reg8 *) SD_Data_Clk__PM_STBY_CFG) + +/* Clock LSB divider configuration register. */ +#define SD_Data_Clk_DIV_LSB (* (reg8 *) SD_Data_Clk__CFG0) +#define SD_Data_Clk_DIV_LSB_PTR ((reg8 *) SD_Data_Clk__CFG0) +#define SD_Data_Clk_DIV_PTR ((reg16 *) SD_Data_Clk__CFG0) + +/* Clock MSB divider configuration register. */ +#define SD_Data_Clk_DIV_MSB (* (reg8 *) SD_Data_Clk__CFG1) +#define SD_Data_Clk_DIV_MSB_PTR ((reg8 *) SD_Data_Clk__CFG1) + +/* Mode and source configuration register */ +#define SD_Data_Clk_MOD_SRC (* (reg8 *) SD_Data_Clk__CFG2) +#define SD_Data_Clk_MOD_SRC_PTR ((reg8 *) SD_Data_Clk__CFG2) + +#if defined(SD_Data_Clk__CFG3) +/* Analog clock phase configuration register */ +#define SD_Data_Clk_PHASE (* (reg8 *) SD_Data_Clk__CFG3) +#define SD_Data_Clk_PHASE_PTR ((reg8 *) SD_Data_Clk__CFG3) +#endif /* defined(SD_Data_Clk__CFG3) */ + + +/************************************** +* Register Constants +**************************************/ + +/* Power manager register masks */ +#define SD_Data_Clk_CLKEN_MASK SD_Data_Clk__PM_ACT_MSK +#define SD_Data_Clk_CLKSTBY_MASK SD_Data_Clk__PM_STBY_MSK + +/* CFG2 field masks */ +#define SD_Data_Clk_SRC_SEL_MSK SD_Data_Clk__CFG2_SRC_SEL_MASK +#define SD_Data_Clk_MODE_MASK (~(SD_Data_Clk_SRC_SEL_MSK)) + +#if defined(SD_Data_Clk__CFG3) +/* CFG3 phase mask */ +#define SD_Data_Clk_PHASE_MASK SD_Data_Clk__CFG3_PHASE_DLY_MASK +#endif /* defined(SD_Data_Clk__CFG3) */ + +#endif /* CY_CLOCK_SD_Data_Clk_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_Init_Clk.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_Init_Clk.c new file mode 100755 index 00000000..b0614702 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_Init_Clk.c @@ -0,0 +1,521 @@ +/******************************************************************************* +* File Name: SD_Init_Clk.c +* Version 2.10 +* +* Description: +* This file provides the source code to the API for the clock component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "SD_Init_Clk.h" + +/* Clock Distribution registers. */ +#define CLK_DIST_LD (* (reg8 *) CYREG_CLKDIST_LD) +#define CLK_DIST_BCFG2 (* (reg8 *) CYREG_CLKDIST_BCFG2) +#define BCFG2_MASK (0x80u) +#define CLK_DIST_DMASK (* (reg8 *) CYREG_CLKDIST_DMASK) +#define CLK_DIST_AMASK (* (reg8 *) CYREG_CLKDIST_AMASK) + +#define HAS_CLKDIST_LD_DISABLE (CY_PSOC3 || CY_PSOC5LP) + + +/******************************************************************************* +* Function Name: SD_Init_Clk_Start +******************************************************************************** +* +* Summary: +* Starts the clock. Note that on startup, clocks may be already running if the +* "Start on Reset" option is enabled in the DWR. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Init_Clk_Start(void) +{ + /* Set the bit to enable the clock. */ + SD_Init_Clk_CLKEN |= SD_Init_Clk_CLKEN_MASK; + SD_Init_Clk_CLKSTBY |= SD_Init_Clk_CLKSTBY_MASK; +} + + +/******************************************************************************* +* Function Name: SD_Init_Clk_Stop +******************************************************************************** +* +* Summary: +* Stops the clock and returns immediately. This API does not require the +* source clock to be running but may return before the hardware is actually +* disabled. If the settings of the clock are changed after calling this +* function, the clock may glitch when it is started. To avoid the clock +* glitch, use the StopBlock function. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Init_Clk_Stop(void) +{ + /* Clear the bit to disable the clock. */ + SD_Init_Clk_CLKEN &= (uint8)(~SD_Init_Clk_CLKEN_MASK); + SD_Init_Clk_CLKSTBY &= (uint8)(~SD_Init_Clk_CLKSTBY_MASK); +} + + +#if(CY_PSOC3 || CY_PSOC5LP) + + +/******************************************************************************* +* Function Name: SD_Init_Clk_StopBlock +******************************************************************************** +* +* Summary: +* Stops the clock and waits for the hardware to actually be disabled before +* returning. This ensures that the clock is never truncated (high part of the +* cycle will terminate before the clock is disabled and the API returns). +* Note that the source clock must be running or this API will never return as +* a stopped clock cannot be disabled. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Init_Clk_StopBlock(void) +{ + if ((SD_Init_Clk_CLKEN & SD_Init_Clk_CLKEN_MASK) != 0u) + { +#if HAS_CLKDIST_LD_DISABLE + uint16 oldDivider; + + CLK_DIST_LD = 0u; + + /* Clear all the mask bits except ours. */ +#if defined(SD_Init_Clk__CFG3) + CLK_DIST_AMASK = SD_Init_Clk_CLKEN_MASK; + CLK_DIST_DMASK = 0x00u; +#else + CLK_DIST_DMASK = SD_Init_Clk_CLKEN_MASK; + CLK_DIST_AMASK = 0x00u; +#endif /* SD_Init_Clk__CFG3 */ + + /* Clear mask of bus clock. */ + CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK); + + oldDivider = CY_GET_REG16(SD_Init_Clk_DIV_PTR); + CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider); + CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD; + + /* Wait for clock to be disabled */ + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } +#endif /* HAS_CLKDIST_LD_DISABLE */ + + /* Clear the bit to disable the clock. */ + SD_Init_Clk_CLKEN &= (uint8)(~SD_Init_Clk_CLKEN_MASK); + SD_Init_Clk_CLKSTBY &= (uint8)(~SD_Init_Clk_CLKSTBY_MASK); + +#if HAS_CLKDIST_LD_DISABLE + /* Clear the disable bit */ + CLK_DIST_LD = 0x00u; + CY_SET_REG16(SD_Init_Clk_DIV_PTR, oldDivider); +#endif /* HAS_CLKDIST_LD_DISABLE */ + } +} +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + +/******************************************************************************* +* Function Name: SD_Init_Clk_StandbyPower +******************************************************************************** +* +* Summary: +* Sets whether the clock is active in standby mode. +* +* Parameters: +* state: 0 to disable clock during standby, nonzero to enable. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Init_Clk_StandbyPower(uint8 state) +{ + if(state == 0u) + { + SD_Init_Clk_CLKSTBY &= (uint8)(~SD_Init_Clk_CLKSTBY_MASK); + } + else + { + SD_Init_Clk_CLKSTBY |= SD_Init_Clk_CLKSTBY_MASK; + } +} + + +/******************************************************************************* +* Function Name: SD_Init_Clk_SetDividerRegister +******************************************************************************** +* +* Summary: +* Modifies the clock divider and, thus, the frequency. When the clock divider +* register is set to zero or changed from zero, the clock will be temporarily +* disabled in order to change the SSS mode bit. If the clock is enabled when +* SetDividerRegister is called, then the source clock must be running. +* +* Parameters: +* clkDivider: Divider register value (0-65,535). This value is NOT the +* divider; the clock hardware divides by clkDivider plus one. For example, +* to divide the clock by 2, this parameter should be set to 1. +* restart: If nonzero, restarts the clock divider: the current clock cycle +* will be truncated and the new divide value will take effect immediately. If +* zero, the new divide value will take effect at the end of the current clock +* cycle. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Init_Clk_SetDividerRegister(uint16 clkDivider, uint8 restart) + +{ + uint8 enabled; + + uint8 currSrc = SD_Init_Clk_GetSourceRegister(); + uint16 oldDivider = SD_Init_Clk_GetDividerRegister(); + + if (clkDivider != oldDivider) + { + enabled = SD_Init_Clk_CLKEN & SD_Init_Clk_CLKEN_MASK; + + if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u))) + { + /* Moving to/from SSS requires correct ordering to prevent halting the clock */ + if (oldDivider == 0u) + { + /* Moving away from SSS, set the divider first so when SSS is cleared we */ + /* don't halt the clock. Using the shadow load isn't required as the */ + /* divider is ignored while SSS is set. */ + CY_SET_REG16(SD_Init_Clk_DIV_PTR, clkDivider); + SD_Init_Clk_MOD_SRC &= (uint8)(~CYCLK_SSS); + } + else + { + /* Moving to SSS, set SSS which then ignores the divider and we can set */ + /* it without bothering with the shadow load. */ + SD_Init_Clk_MOD_SRC |= CYCLK_SSS; + CY_SET_REG16(SD_Init_Clk_DIV_PTR, clkDivider); + } + } + else + { + + if (enabled != 0u) + { + CLK_DIST_LD = 0x00u; + + /* Clear all the mask bits except ours. */ +#if defined(SD_Init_Clk__CFG3) + CLK_DIST_AMASK = SD_Init_Clk_CLKEN_MASK; + CLK_DIST_DMASK = 0x00u; +#else + CLK_DIST_DMASK = SD_Init_Clk_CLKEN_MASK; + CLK_DIST_AMASK = 0x00u; +#endif /* SD_Init_Clk__CFG3 */ + /* Clear mask of bus clock. */ + CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK); + + /* If clock is currently enabled, disable it if async or going from N-to-1*/ + if (((SD_Init_Clk_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u)) + { +#if HAS_CLKDIST_LD_DISABLE + CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider); + CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD; + + /* Wait for clock to be disabled */ + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } +#endif /* HAS_CLKDIST_LD_DISABLE */ + + SD_Init_Clk_CLKEN &= (uint8)(~SD_Init_Clk_CLKEN_MASK); + +#if HAS_CLKDIST_LD_DISABLE + /* Clear the disable bit */ + CLK_DIST_LD = 0x00u; +#endif /* HAS_CLKDIST_LD_DISABLE */ + } + } + + /* Load divide value. */ + if ((SD_Init_Clk_CLKEN & SD_Init_Clk_CLKEN_MASK) != 0u) + { + /* If the clock is still enabled, use the shadow registers */ + CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider); + + CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u)); + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } + } + else + { + /* If the clock is disabled, set the divider directly */ + CY_SET_REG16(SD_Init_Clk_DIV_PTR, clkDivider); + SD_Init_Clk_CLKEN |= enabled; + } + } + } +} + + +/******************************************************************************* +* Function Name: SD_Init_Clk_GetDividerRegister +******************************************************************************** +* +* Summary: +* Gets the clock divider register value. +* +* Parameters: +* None +* +* Returns: +* Divide value of the clock minus 1. For example, if the clock is set to +* divide by 2, the return value will be 1. +* +*******************************************************************************/ +uint16 SD_Init_Clk_GetDividerRegister(void) +{ + return CY_GET_REG16(SD_Init_Clk_DIV_PTR); +} + + +/******************************************************************************* +* Function Name: SD_Init_Clk_SetModeRegister +******************************************************************************** +* +* Summary: +* Sets flags that control the operating mode of the clock. This function only +* changes flags from 0 to 1; flags that are already 1 will remain unchanged. +* To clear flags, use the ClearModeRegister function. The clock must be +* disabled before changing the mode. +* +* Parameters: +* clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5, +* clkMode should be a set of the following optional bits or'ed together. +* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will +* occur when the divider count reaches half of the divide +* value. +* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock +* is asserted for approximately half of its period. When +* disabled, the output clock is asserted for one period of the +* source clock. +* - CYCLK_SYNC Enable output synchronization to master clock. This should +* be enabled for all synchronous clocks. +* See the Technical Reference Manual for details about setting the mode of +* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Init_Clk_SetModeRegister(uint8 modeBitMask) +{ + SD_Init_Clk_MOD_SRC |= modeBitMask & (uint8)SD_Init_Clk_MODE_MASK; +} + + +/******************************************************************************* +* Function Name: SD_Init_Clk_ClearModeRegister +******************************************************************************** +* +* Summary: +* Clears flags that control the operating mode of the clock. This function +* only changes flags from 1 to 0; flags that are already 0 will remain +* unchanged. To set flags, use the SetModeRegister function. The clock must be +* disabled before changing the mode. +* +* Parameters: +* clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5, +* clkMode should be a set of the following optional bits or'ed together. +* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will +* occur when the divider count reaches half of the divide +* value. +* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock +* is asserted for approximately half of its period. When +* disabled, the output clock is asserted for one period of the +* source clock. +* - CYCLK_SYNC Enable output synchronization to master clock. This should +* be enabled for all synchronous clocks. +* See the Technical Reference Manual for details about setting the mode of +* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Init_Clk_ClearModeRegister(uint8 modeBitMask) +{ + SD_Init_Clk_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(SD_Init_Clk_MODE_MASK)); +} + + +/******************************************************************************* +* Function Name: SD_Init_Clk_GetModeRegister +******************************************************************************** +* +* Summary: +* Gets the clock mode register value. +* +* Parameters: +* None +* +* Returns: +* Bit mask representing the enabled mode bits. See the SetModeRegister and +* ClearModeRegister descriptions for details about the mode bits. +* +*******************************************************************************/ +uint8 SD_Init_Clk_GetModeRegister(void) +{ + return SD_Init_Clk_MOD_SRC & (uint8)(SD_Init_Clk_MODE_MASK); +} + + +/******************************************************************************* +* Function Name: SD_Init_Clk_SetSourceRegister +******************************************************************************** +* +* Summary: +* Sets the input source of the clock. The clock must be disabled before +* changing the source. The old and new clock sources must be running. +* +* Parameters: +* clkSource: For PSoC 3 and PSoC 5 devices, clkSource should be one of the +* following input sources: +* - CYCLK_SRC_SEL_SYNC_DIG +* - CYCLK_SRC_SEL_IMO +* - CYCLK_SRC_SEL_XTALM +* - CYCLK_SRC_SEL_ILO +* - CYCLK_SRC_SEL_PLL +* - CYCLK_SRC_SEL_XTALK +* - CYCLK_SRC_SEL_DSI_G +* - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A +* See the Technical Reference Manual for details on clock sources. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Init_Clk_SetSourceRegister(uint8 clkSource) +{ + uint16 currDiv = SD_Init_Clk_GetDividerRegister(); + uint8 oldSrc = SD_Init_Clk_GetSourceRegister(); + + if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && + (clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u)) + { + /* Switching to Master and divider is 1, set SSS, which will output master, */ + /* then set the source so we are consistent. */ + SD_Init_Clk_MOD_SRC |= CYCLK_SSS; + SD_Init_Clk_MOD_SRC = + (SD_Init_Clk_MOD_SRC & (uint8)(~SD_Init_Clk_SRC_SEL_MSK)) | clkSource; + } + else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && + (clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u)) + { + /* Switching from Master to not and divider is 1, set source, so we don't */ + /* lock when we clear SSS. */ + SD_Init_Clk_MOD_SRC = + (SD_Init_Clk_MOD_SRC & (uint8)(~SD_Init_Clk_SRC_SEL_MSK)) | clkSource; + SD_Init_Clk_MOD_SRC &= (uint8)(~CYCLK_SSS); + } + else + { + SD_Init_Clk_MOD_SRC = + (SD_Init_Clk_MOD_SRC & (uint8)(~SD_Init_Clk_SRC_SEL_MSK)) | clkSource; + } +} + + +/******************************************************************************* +* Function Name: SD_Init_Clk_GetSourceRegister +******************************************************************************** +* +* Summary: +* Gets the input source of the clock. +* +* Parameters: +* None +* +* Returns: +* The input source of the clock. See SetSourceRegister for details. +* +*******************************************************************************/ +uint8 SD_Init_Clk_GetSourceRegister(void) +{ + return SD_Init_Clk_MOD_SRC & SD_Init_Clk_SRC_SEL_MSK; +} + + +#if defined(SD_Init_Clk__CFG3) + + +/******************************************************************************* +* Function Name: SD_Init_Clk_SetPhaseRegister +******************************************************************************** +* +* Summary: +* Sets the phase delay of the analog clock. This function is only available +* for analog clocks. The clock must be disabled before changing the phase +* delay to avoid glitches. +* +* Parameters: +* clkPhase: Amount to delay the phase of the clock, in 1.0ns increments. +* clkPhase must be from 1 to 11 inclusive. Other values, including 0, +* disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11 +* produces a 10ns delay. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Init_Clk_SetPhaseRegister(uint8 clkPhase) +{ + SD_Init_Clk_PHASE = clkPhase & SD_Init_Clk_PHASE_MASK; +} + + +/******************************************************************************* +* Function Name: SD_Init_Clk_GetPhase +******************************************************************************** +* +* Summary: +* Gets the phase delay of the analog clock. This function is only available +* for analog clocks. +* +* Parameters: +* None +* +* Returns: +* Phase of the analog clock. See SetPhaseRegister for details. +* +*******************************************************************************/ +uint8 SD_Init_Clk_GetPhaseRegister(void) +{ + return SD_Init_Clk_PHASE & SD_Init_Clk_PHASE_MASK; +} + +#endif /* SD_Init_Clk__CFG3 */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_Init_Clk.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_Init_Clk.h new file mode 100755 index 00000000..43c2e068 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_Init_Clk.h @@ -0,0 +1,124 @@ +/******************************************************************************* +* File Name: SD_Init_Clk.h +* Version 2.10 +* +* Description: +* Provides the function and constant definitions for the clock component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CLOCK_SD_Init_Clk_H) +#define CY_CLOCK_SD_Init_Clk_H + +#include +#include + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ + +/* Check to see if required defines such as CY_PSOC5LP are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5LP) + #error Component cy_clock_v2_10 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5LP) */ + + +/*************************************** +* Function Prototypes +***************************************/ + +void SD_Init_Clk_Start(void) ; +void SD_Init_Clk_Stop(void) ; + +#if(CY_PSOC3 || CY_PSOC5LP) +void SD_Init_Clk_StopBlock(void) ; +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + +void SD_Init_Clk_StandbyPower(uint8 state) ; +void SD_Init_Clk_SetDividerRegister(uint16 clkDivider, uint8 restart) + ; +uint16 SD_Init_Clk_GetDividerRegister(void) ; +void SD_Init_Clk_SetModeRegister(uint8 modeBitMask) ; +void SD_Init_Clk_ClearModeRegister(uint8 modeBitMask) ; +uint8 SD_Init_Clk_GetModeRegister(void) ; +void SD_Init_Clk_SetSourceRegister(uint8 clkSource) ; +uint8 SD_Init_Clk_GetSourceRegister(void) ; +#if defined(SD_Init_Clk__CFG3) +void SD_Init_Clk_SetPhaseRegister(uint8 clkPhase) ; +uint8 SD_Init_Clk_GetPhaseRegister(void) ; +#endif /* defined(SD_Init_Clk__CFG3) */ + +#define SD_Init_Clk_Enable() SD_Init_Clk_Start() +#define SD_Init_Clk_Disable() SD_Init_Clk_Stop() +#define SD_Init_Clk_SetDivider(clkDivider) SD_Init_Clk_SetDividerRegister(clkDivider, 1u) +#define SD_Init_Clk_SetDividerValue(clkDivider) SD_Init_Clk_SetDividerRegister((clkDivider) - 1u, 1u) +#define SD_Init_Clk_SetMode(clkMode) SD_Init_Clk_SetModeRegister(clkMode) +#define SD_Init_Clk_SetSource(clkSource) SD_Init_Clk_SetSourceRegister(clkSource) +#if defined(SD_Init_Clk__CFG3) +#define SD_Init_Clk_SetPhase(clkPhase) SD_Init_Clk_SetPhaseRegister(clkPhase) +#define SD_Init_Clk_SetPhaseValue(clkPhase) SD_Init_Clk_SetPhaseRegister((clkPhase) + 1u) +#endif /* defined(SD_Init_Clk__CFG3) */ + + +/*************************************** +* Registers +***************************************/ + +/* Register to enable or disable the clock */ +#define SD_Init_Clk_CLKEN (* (reg8 *) SD_Init_Clk__PM_ACT_CFG) +#define SD_Init_Clk_CLKEN_PTR ((reg8 *) SD_Init_Clk__PM_ACT_CFG) + +/* Register to enable or disable the clock */ +#define SD_Init_Clk_CLKSTBY (* (reg8 *) SD_Init_Clk__PM_STBY_CFG) +#define SD_Init_Clk_CLKSTBY_PTR ((reg8 *) SD_Init_Clk__PM_STBY_CFG) + +/* Clock LSB divider configuration register. */ +#define SD_Init_Clk_DIV_LSB (* (reg8 *) SD_Init_Clk__CFG0) +#define SD_Init_Clk_DIV_LSB_PTR ((reg8 *) SD_Init_Clk__CFG0) +#define SD_Init_Clk_DIV_PTR ((reg16 *) SD_Init_Clk__CFG0) + +/* Clock MSB divider configuration register. */ +#define SD_Init_Clk_DIV_MSB (* (reg8 *) SD_Init_Clk__CFG1) +#define SD_Init_Clk_DIV_MSB_PTR ((reg8 *) SD_Init_Clk__CFG1) + +/* Mode and source configuration register */ +#define SD_Init_Clk_MOD_SRC (* (reg8 *) SD_Init_Clk__CFG2) +#define SD_Init_Clk_MOD_SRC_PTR ((reg8 *) SD_Init_Clk__CFG2) + +#if defined(SD_Init_Clk__CFG3) +/* Analog clock phase configuration register */ +#define SD_Init_Clk_PHASE (* (reg8 *) SD_Init_Clk__CFG3) +#define SD_Init_Clk_PHASE_PTR ((reg8 *) SD_Init_Clk__CFG3) +#endif /* defined(SD_Init_Clk__CFG3) */ + + +/************************************** +* Register Constants +**************************************/ + +/* Power manager register masks */ +#define SD_Init_Clk_CLKEN_MASK SD_Init_Clk__PM_ACT_MSK +#define SD_Init_Clk_CLKSTBY_MASK SD_Init_Clk__PM_STBY_MSK + +/* CFG2 field masks */ +#define SD_Init_Clk_SRC_SEL_MSK SD_Init_Clk__CFG2_SRC_SEL_MASK +#define SD_Init_Clk_MODE_MASK (~(SD_Init_Clk_SRC_SEL_MSK)) + +#if defined(SD_Init_Clk__CFG3) +/* CFG3 phase mask */ +#define SD_Init_Clk_PHASE_MASK SD_Init_Clk__CFG3_PHASE_DLY_MASK +#endif /* defined(SD_Init_Clk__CFG3) */ + +#endif /* CY_CLOCK_SD_Init_Clk_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_MISO.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_MISO.c new file mode 100755 index 00000000..536c08e5 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_MISO.c @@ -0,0 +1,137 @@ +/******************************************************************************* +* File Name: SD_MISO.c +* Version 1.90 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SD_MISO.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + SD_MISO__PORT == 15 && ((SD_MISO__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: SD_MISO_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void SD_MISO_Write(uint8 value) +{ + uint8 staticBits = (SD_MISO_DR & (uint8)(~SD_MISO_MASK)); + SD_MISO_DR = staticBits | ((uint8)(value << SD_MISO_SHIFT) & SD_MISO_MASK); +} + + +/******************************************************************************* +* Function Name: SD_MISO_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to this drive mode. +* +* Return: +* None +* +*******************************************************************************/ +void SD_MISO_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(SD_MISO_0, mode); +} + + +/******************************************************************************* +* Function Name: SD_MISO_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro SD_MISO_ReadPS calls this function. +* +*******************************************************************************/ +uint8 SD_MISO_Read(void) +{ + return (SD_MISO_PS & SD_MISO_MASK) >> SD_MISO_SHIFT; +} + + +/******************************************************************************* +* Function Name: SD_MISO_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 SD_MISO_ReadDataReg(void) +{ + return (SD_MISO_DR & SD_MISO_MASK) >> SD_MISO_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(SD_MISO_INTSTAT) + + /******************************************************************************* + * Function Name: SD_MISO_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 SD_MISO_ClearInterrupt(void) + { + return (SD_MISO_INTSTAT & SD_MISO_MASK) >> SD_MISO_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_MISO.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_MISO.h new file mode 100755 index 00000000..5583fbdb --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_MISO.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: SD_MISO.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_MISO_H) /* Pins SD_MISO_H */ +#define CY_PINS_SD_MISO_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SD_MISO_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SD_MISO__PORT == 15 && ((SD_MISO__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void SD_MISO_Write(uint8 value) ; +void SD_MISO_SetDriveMode(uint8 mode) ; +uint8 SD_MISO_ReadDataReg(void) ; +uint8 SD_MISO_Read(void) ; +uint8 SD_MISO_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define SD_MISO_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define SD_MISO_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define SD_MISO_DM_RES_UP PIN_DM_RES_UP +#define SD_MISO_DM_RES_DWN PIN_DM_RES_DWN +#define SD_MISO_DM_OD_LO PIN_DM_OD_LO +#define SD_MISO_DM_OD_HI PIN_DM_OD_HI +#define SD_MISO_DM_STRONG PIN_DM_STRONG +#define SD_MISO_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define SD_MISO_MASK SD_MISO__MASK +#define SD_MISO_SHIFT SD_MISO__SHIFT +#define SD_MISO_WIDTH 1u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SD_MISO_PS (* (reg8 *) SD_MISO__PS) +/* Data Register */ +#define SD_MISO_DR (* (reg8 *) SD_MISO__DR) +/* Port Number */ +#define SD_MISO_PRT_NUM (* (reg8 *) SD_MISO__PRT) +/* Connect to Analog Globals */ +#define SD_MISO_AG (* (reg8 *) SD_MISO__AG) +/* Analog MUX bux enable */ +#define SD_MISO_AMUX (* (reg8 *) SD_MISO__AMUX) +/* Bidirectional Enable */ +#define SD_MISO_BIE (* (reg8 *) SD_MISO__BIE) +/* Bit-mask for Aliased Register Access */ +#define SD_MISO_BIT_MASK (* (reg8 *) SD_MISO__BIT_MASK) +/* Bypass Enable */ +#define SD_MISO_BYP (* (reg8 *) SD_MISO__BYP) +/* Port wide control signals */ +#define SD_MISO_CTL (* (reg8 *) SD_MISO__CTL) +/* Drive Modes */ +#define SD_MISO_DM0 (* (reg8 *) SD_MISO__DM0) +#define SD_MISO_DM1 (* (reg8 *) SD_MISO__DM1) +#define SD_MISO_DM2 (* (reg8 *) SD_MISO__DM2) +/* Input Buffer Disable Override */ +#define SD_MISO_INP_DIS (* (reg8 *) SD_MISO__INP_DIS) +/* LCD Common or Segment Drive */ +#define SD_MISO_LCD_COM_SEG (* (reg8 *) SD_MISO__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SD_MISO_LCD_EN (* (reg8 *) SD_MISO__LCD_EN) +/* Slew Rate Control */ +#define SD_MISO_SLW (* (reg8 *) SD_MISO__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SD_MISO_PRTDSI__CAPS_SEL (* (reg8 *) SD_MISO__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SD_MISO_PRTDSI__DBL_SYNC_IN (* (reg8 *) SD_MISO__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SD_MISO_PRTDSI__OE_SEL0 (* (reg8 *) SD_MISO__PRTDSI__OE_SEL0) +#define SD_MISO_PRTDSI__OE_SEL1 (* (reg8 *) SD_MISO__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SD_MISO_PRTDSI__OUT_SEL0 (* (reg8 *) SD_MISO__PRTDSI__OUT_SEL0) +#define SD_MISO_PRTDSI__OUT_SEL1 (* (reg8 *) SD_MISO__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SD_MISO_PRTDSI__SYNC_OUT (* (reg8 *) SD_MISO__PRTDSI__SYNC_OUT) + + +#if defined(SD_MISO__INTSTAT) /* Interrupt Registers */ + + #define SD_MISO_INTSTAT (* (reg8 *) SD_MISO__INTSTAT) + #define SD_MISO_SNAP (* (reg8 *) SD_MISO__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SD_MISO_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_MISO_aliases.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_MISO_aliases.h new file mode 100755 index 00000000..b392bb88 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_MISO_aliases.h @@ -0,0 +1,32 @@ +/******************************************************************************* +* File Name: SD_MISO.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_MISO_ALIASES_H) /* Pins SD_MISO_ALIASES_H */ +#define CY_PINS_SD_MISO_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SD_MISO_0 SD_MISO__0__PC + +#endif /* End Pins SD_MISO_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_MOSI.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_MOSI.c new file mode 100755 index 00000000..2658af80 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_MOSI.c @@ -0,0 +1,137 @@ +/******************************************************************************* +* File Name: SD_MOSI.c +* Version 1.90 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SD_MOSI.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + SD_MOSI__PORT == 15 && ((SD_MOSI__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: SD_MOSI_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void SD_MOSI_Write(uint8 value) +{ + uint8 staticBits = (SD_MOSI_DR & (uint8)(~SD_MOSI_MASK)); + SD_MOSI_DR = staticBits | ((uint8)(value << SD_MOSI_SHIFT) & SD_MOSI_MASK); +} + + +/******************************************************************************* +* Function Name: SD_MOSI_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to this drive mode. +* +* Return: +* None +* +*******************************************************************************/ +void SD_MOSI_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(SD_MOSI_0, mode); +} + + +/******************************************************************************* +* Function Name: SD_MOSI_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro SD_MOSI_ReadPS calls this function. +* +*******************************************************************************/ +uint8 SD_MOSI_Read(void) +{ + return (SD_MOSI_PS & SD_MOSI_MASK) >> SD_MOSI_SHIFT; +} + + +/******************************************************************************* +* Function Name: SD_MOSI_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 SD_MOSI_ReadDataReg(void) +{ + return (SD_MOSI_DR & SD_MOSI_MASK) >> SD_MOSI_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(SD_MOSI_INTSTAT) + + /******************************************************************************* + * Function Name: SD_MOSI_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 SD_MOSI_ClearInterrupt(void) + { + return (SD_MOSI_INTSTAT & SD_MOSI_MASK) >> SD_MOSI_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_MOSI.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_MOSI.h new file mode 100755 index 00000000..73f55e08 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_MOSI.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: SD_MOSI.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_MOSI_H) /* Pins SD_MOSI_H */ +#define CY_PINS_SD_MOSI_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SD_MOSI_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SD_MOSI__PORT == 15 && ((SD_MOSI__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void SD_MOSI_Write(uint8 value) ; +void SD_MOSI_SetDriveMode(uint8 mode) ; +uint8 SD_MOSI_ReadDataReg(void) ; +uint8 SD_MOSI_Read(void) ; +uint8 SD_MOSI_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define SD_MOSI_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define SD_MOSI_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define SD_MOSI_DM_RES_UP PIN_DM_RES_UP +#define SD_MOSI_DM_RES_DWN PIN_DM_RES_DWN +#define SD_MOSI_DM_OD_LO PIN_DM_OD_LO +#define SD_MOSI_DM_OD_HI PIN_DM_OD_HI +#define SD_MOSI_DM_STRONG PIN_DM_STRONG +#define SD_MOSI_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define SD_MOSI_MASK SD_MOSI__MASK +#define SD_MOSI_SHIFT SD_MOSI__SHIFT +#define SD_MOSI_WIDTH 1u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SD_MOSI_PS (* (reg8 *) SD_MOSI__PS) +/* Data Register */ +#define SD_MOSI_DR (* (reg8 *) SD_MOSI__DR) +/* Port Number */ +#define SD_MOSI_PRT_NUM (* (reg8 *) SD_MOSI__PRT) +/* Connect to Analog Globals */ +#define SD_MOSI_AG (* (reg8 *) SD_MOSI__AG) +/* Analog MUX bux enable */ +#define SD_MOSI_AMUX (* (reg8 *) SD_MOSI__AMUX) +/* Bidirectional Enable */ +#define SD_MOSI_BIE (* (reg8 *) SD_MOSI__BIE) +/* Bit-mask for Aliased Register Access */ +#define SD_MOSI_BIT_MASK (* (reg8 *) SD_MOSI__BIT_MASK) +/* Bypass Enable */ +#define SD_MOSI_BYP (* (reg8 *) SD_MOSI__BYP) +/* Port wide control signals */ +#define SD_MOSI_CTL (* (reg8 *) SD_MOSI__CTL) +/* Drive Modes */ +#define SD_MOSI_DM0 (* (reg8 *) SD_MOSI__DM0) +#define SD_MOSI_DM1 (* (reg8 *) SD_MOSI__DM1) +#define SD_MOSI_DM2 (* (reg8 *) SD_MOSI__DM2) +/* Input Buffer Disable Override */ +#define SD_MOSI_INP_DIS (* (reg8 *) SD_MOSI__INP_DIS) +/* LCD Common or Segment Drive */ +#define SD_MOSI_LCD_COM_SEG (* (reg8 *) SD_MOSI__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SD_MOSI_LCD_EN (* (reg8 *) SD_MOSI__LCD_EN) +/* Slew Rate Control */ +#define SD_MOSI_SLW (* (reg8 *) SD_MOSI__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SD_MOSI_PRTDSI__CAPS_SEL (* (reg8 *) SD_MOSI__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SD_MOSI_PRTDSI__DBL_SYNC_IN (* (reg8 *) SD_MOSI__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SD_MOSI_PRTDSI__OE_SEL0 (* (reg8 *) SD_MOSI__PRTDSI__OE_SEL0) +#define SD_MOSI_PRTDSI__OE_SEL1 (* (reg8 *) SD_MOSI__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SD_MOSI_PRTDSI__OUT_SEL0 (* (reg8 *) SD_MOSI__PRTDSI__OUT_SEL0) +#define SD_MOSI_PRTDSI__OUT_SEL1 (* (reg8 *) SD_MOSI__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SD_MOSI_PRTDSI__SYNC_OUT (* (reg8 *) SD_MOSI__PRTDSI__SYNC_OUT) + + +#if defined(SD_MOSI__INTSTAT) /* Interrupt Registers */ + + #define SD_MOSI_INTSTAT (* (reg8 *) SD_MOSI__INTSTAT) + #define SD_MOSI_SNAP (* (reg8 *) SD_MOSI__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SD_MOSI_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_MOSI_aliases.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_MOSI_aliases.h new file mode 100755 index 00000000..c97abbd8 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_MOSI_aliases.h @@ -0,0 +1,32 @@ +/******************************************************************************* +* File Name: SD_MOSI.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_MOSI_ALIASES_H) /* Pins SD_MOSI_ALIASES_H */ +#define CY_PINS_SD_MOSI_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SD_MOSI_0 SD_MOSI__0__PC + +#endif /* End Pins SD_MOSI_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_SCK.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_SCK.c new file mode 100755 index 00000000..1ca28998 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_SCK.c @@ -0,0 +1,137 @@ +/******************************************************************************* +* File Name: SD_SCK.c +* Version 1.90 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SD_SCK.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + SD_SCK__PORT == 15 && ((SD_SCK__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: SD_SCK_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void SD_SCK_Write(uint8 value) +{ + uint8 staticBits = (SD_SCK_DR & (uint8)(~SD_SCK_MASK)); + SD_SCK_DR = staticBits | ((uint8)(value << SD_SCK_SHIFT) & SD_SCK_MASK); +} + + +/******************************************************************************* +* Function Name: SD_SCK_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to this drive mode. +* +* Return: +* None +* +*******************************************************************************/ +void SD_SCK_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(SD_SCK_0, mode); +} + + +/******************************************************************************* +* Function Name: SD_SCK_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro SD_SCK_ReadPS calls this function. +* +*******************************************************************************/ +uint8 SD_SCK_Read(void) +{ + return (SD_SCK_PS & SD_SCK_MASK) >> SD_SCK_SHIFT; +} + + +/******************************************************************************* +* Function Name: SD_SCK_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 SD_SCK_ReadDataReg(void) +{ + return (SD_SCK_DR & SD_SCK_MASK) >> SD_SCK_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(SD_SCK_INTSTAT) + + /******************************************************************************* + * Function Name: SD_SCK_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 SD_SCK_ClearInterrupt(void) + { + return (SD_SCK_INTSTAT & SD_SCK_MASK) >> SD_SCK_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_SCK.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_SCK.h new file mode 100755 index 00000000..2fb0b372 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_SCK.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: SD_SCK.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_SCK_H) /* Pins SD_SCK_H */ +#define CY_PINS_SD_SCK_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SD_SCK_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SD_SCK__PORT == 15 && ((SD_SCK__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void SD_SCK_Write(uint8 value) ; +void SD_SCK_SetDriveMode(uint8 mode) ; +uint8 SD_SCK_ReadDataReg(void) ; +uint8 SD_SCK_Read(void) ; +uint8 SD_SCK_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define SD_SCK_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define SD_SCK_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define SD_SCK_DM_RES_UP PIN_DM_RES_UP +#define SD_SCK_DM_RES_DWN PIN_DM_RES_DWN +#define SD_SCK_DM_OD_LO PIN_DM_OD_LO +#define SD_SCK_DM_OD_HI PIN_DM_OD_HI +#define SD_SCK_DM_STRONG PIN_DM_STRONG +#define SD_SCK_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define SD_SCK_MASK SD_SCK__MASK +#define SD_SCK_SHIFT SD_SCK__SHIFT +#define SD_SCK_WIDTH 1u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SD_SCK_PS (* (reg8 *) SD_SCK__PS) +/* Data Register */ +#define SD_SCK_DR (* (reg8 *) SD_SCK__DR) +/* Port Number */ +#define SD_SCK_PRT_NUM (* (reg8 *) SD_SCK__PRT) +/* Connect to Analog Globals */ +#define SD_SCK_AG (* (reg8 *) SD_SCK__AG) +/* Analog MUX bux enable */ +#define SD_SCK_AMUX (* (reg8 *) SD_SCK__AMUX) +/* Bidirectional Enable */ +#define SD_SCK_BIE (* (reg8 *) SD_SCK__BIE) +/* Bit-mask for Aliased Register Access */ +#define SD_SCK_BIT_MASK (* (reg8 *) SD_SCK__BIT_MASK) +/* Bypass Enable */ +#define SD_SCK_BYP (* (reg8 *) SD_SCK__BYP) +/* Port wide control signals */ +#define SD_SCK_CTL (* (reg8 *) SD_SCK__CTL) +/* Drive Modes */ +#define SD_SCK_DM0 (* (reg8 *) SD_SCK__DM0) +#define SD_SCK_DM1 (* (reg8 *) SD_SCK__DM1) +#define SD_SCK_DM2 (* (reg8 *) SD_SCK__DM2) +/* Input Buffer Disable Override */ +#define SD_SCK_INP_DIS (* (reg8 *) SD_SCK__INP_DIS) +/* LCD Common or Segment Drive */ +#define SD_SCK_LCD_COM_SEG (* (reg8 *) SD_SCK__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SD_SCK_LCD_EN (* (reg8 *) SD_SCK__LCD_EN) +/* Slew Rate Control */ +#define SD_SCK_SLW (* (reg8 *) SD_SCK__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SD_SCK_PRTDSI__CAPS_SEL (* (reg8 *) SD_SCK__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SD_SCK_PRTDSI__DBL_SYNC_IN (* (reg8 *) SD_SCK__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SD_SCK_PRTDSI__OE_SEL0 (* (reg8 *) SD_SCK__PRTDSI__OE_SEL0) +#define SD_SCK_PRTDSI__OE_SEL1 (* (reg8 *) SD_SCK__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SD_SCK_PRTDSI__OUT_SEL0 (* (reg8 *) SD_SCK__PRTDSI__OUT_SEL0) +#define SD_SCK_PRTDSI__OUT_SEL1 (* (reg8 *) SD_SCK__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SD_SCK_PRTDSI__SYNC_OUT (* (reg8 *) SD_SCK__PRTDSI__SYNC_OUT) + + +#if defined(SD_SCK__INTSTAT) /* Interrupt Registers */ + + #define SD_SCK_INTSTAT (* (reg8 *) SD_SCK__INTSTAT) + #define SD_SCK_SNAP (* (reg8 *) SD_SCK__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SD_SCK_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_SCK_aliases.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_SCK_aliases.h new file mode 100755 index 00000000..026596c5 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/SD_SCK_aliases.h @@ -0,0 +1,32 @@ +/******************************************************************************* +* File Name: SD_SCK.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_SCK_ALIASES_H) /* Pins SD_SCK_ALIASES_H */ +#define CY_PINS_SD_SCK_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SD_SCK_0 SD_SCK__0__PC + +#endif /* End Pins SD_SCK_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS.c new file mode 100755 index 00000000..0750c413 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS.c @@ -0,0 +1,1335 @@ +/******************************************************************************* +* File Name: USBFS.c +* Version 2.60 +* +* Description: +* API for USBFS Component. +* +* Note: +* Many of the functions use endpoint number. RAM arrays are sized with 9 +* elements so they are indexed directly by epNumber. The SIE and ARB +* registers are indexed by variations of epNumber - 1. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "USBFS.h" +#include "USBFS_pvt.h" +#include "USBFS_hid.h" +#if(USBFS_DMA1_REMOVE == 0u) + #include "USBFS_ep1_dma.h" +#endif /* End USBFS_DMA1_REMOVE */ +#if(USBFS_DMA2_REMOVE == 0u) + #include "USBFS_ep2_dma.h" +#endif /* End USBFS_DMA2_REMOVE */ +#if(USBFS_DMA3_REMOVE == 0u) + #include "USBFS_ep3_dma.h" +#endif /* End USBFS_DMA3_REMOVE */ +#if(USBFS_DMA4_REMOVE == 0u) + #include "USBFS_ep4_dma.h" +#endif /* End USBFS_DMA4_REMOVE */ +#if(USBFS_DMA5_REMOVE == 0u) + #include "USBFS_ep5_dma.h" +#endif /* End USBFS_DMA5_REMOVE */ +#if(USBFS_DMA6_REMOVE == 0u) + #include "USBFS_ep6_dma.h" +#endif /* End USBFS_DMA6_REMOVE */ +#if(USBFS_DMA7_REMOVE == 0u) + #include "USBFS_ep7_dma.h" +#endif /* End USBFS_DMA7_REMOVE */ +#if(USBFS_DMA8_REMOVE == 0u) + #include "USBFS_ep8_dma.h" +#endif /* End USBFS_DMA8_REMOVE */ + + +/*************************************** +* Global data allocation +***************************************/ + +uint8 USBFS_initVar = 0u; +#if(USBFS_EP_MM != USBFS__EP_MANUAL) + uint8 USBFS_DmaChan[USBFS_MAX_EP]; + uint8 USBFS_DmaTd[USBFS_MAX_EP]; +#endif /* End USBFS_EP_MM */ + + +/******************************************************************************* +* Function Name: USBFS_Start +******************************************************************************** +* +* Summary: +* This function initialize the USB SIE, arbiter and the +* endpoint APIs, including setting the D+ Pullup +* +* Parameters: +* device: Contains the device number of the desired device descriptor. +* The device number can be found in the Device Descriptor Tab of +* "Configure" dialog, under the settings of desired Device Descriptor, +* in the "Device Number" field. +* mode: The operating voltage. This determines whether the voltage regulator +* is enabled for 5V operation or if pass through mode is used for 3.3V +* operation. Symbolic names and their associated values are given in the +* following table. +* USBFS_3V_OPERATION - Disable voltage regulator and pass-thru +* Vcc for pull-up +* USBFS_5V_OPERATION - Enable voltage regulator and use +* regulator for pull-up +* USBFS_DWR_VDDD_OPERATION - Enable or Disable voltage +* regulator depend on Vddd Voltage configuration in DWR. +* +* Return: +* None. +* +* Global variables: +* The USBFS_intiVar variable is used to indicate initial +* configuration of this component. The variable is initialized to zero (0u) +* and set to one (1u) the first time USBFS_Start() is called. +* This allows for component Re-Start without unnecessary re-initialization +* in all subsequent calls to the USBFS_Start() routine. +* If re-initialization of the component is required the variable should be set +* to zero before call of UART_Start() routine, or the user may call +* USBFS_Init() and USBFS_InitComponent() as done +* in the USBFS_Start() routine. +* +* Side Effects: +* This function will reset all communication states to default. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_Start(uint8 device, uint8 mode) +{ + /* If not Initialized then initialize all required hardware and software */ + if(USBFS_initVar == 0u) + { + USBFS_Init(); + USBFS_initVar = 1u; + } + USBFS_InitComponent(device, mode); +} + + +/******************************************************************************* +* Function Name: USBFS_Init +******************************************************************************** +* +* Summary: +* Initialize component's hardware. Usually called in USBFS_Start(). +* +* Parameters: +* None. +* +* Return: +* None. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_Init(void) +{ + uint8 enableInterrupts; + #if(USBFS_EP_MM != USBFS__EP_MANUAL) + uint16 i; + #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ + + enableInterrupts = CyEnterCriticalSection(); + + /* Enable USB block */ + USBFS_PM_ACT_CFG_REG |= USBFS_PM_ACT_EN_FSUSB; + /* Enable USB block for Standby Power Mode */ + USBFS_PM_STBY_CFG_REG |= USBFS_PM_STBY_EN_FSUSB; + + /* Enable core clock */ + USBFS_USB_CLK_EN_REG = USBFS_USB_CLK_ENABLE; + + USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK; + + /* ENABLING USBIO PADS IN USB MODE FROM I/O MODE */ + /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled */ + USBFS_USBIO_CR0_REG &= ((uint8)(~USBFS_USBIO_CR0_TEN)); + CyDelayUs(0u); /*~50ns delay */ + /* Disable the USBIO by asserting PM.USB_CR0.fsusbio_pd_n(Inverted) + * high. This will have been set low by the power manger out of reset. + * Also confirm USBIO pull-up disabled + */ + USBFS_PM_USB_CR0_REG &= ((uint8)(~(USBFS_PM_USB_CR0_PD_N | + USBFS_PM_USB_CR0_PD_PULLUP_N))); + + /* Select iomode to USB mode*/ + USBFS_USBIO_CR1_REG &= ((uint8)(~USBFS_USBIO_CR1_IOMODE)); + + /* Enable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/ + USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_REF_EN; + /* The reference will be available 1 us after the regulator is enabled */ + CyDelayUs(1u); + /* OR 40us after power restored */ + CyDelayUs(40u); + /* Ensure the single ended disable bits are low (PRT15.INP_DIS[7:6])(input receiver enabled). */ + USBFS_DM_INP_DIS_REG &= ((uint8)(~USBFS_DM_MASK)); + USBFS_DP_INP_DIS_REG &= ((uint8)(~USBFS_DP_MASK)); + + /* Enable USBIO */ + USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_N; + CyDelayUs(2u); + /* Set the USBIO pull-up enable */ + USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_PULLUP_N; + + /* Write WAx */ + CY_SET_REG8(USBFS_ARB_RW1_WA_PTR, 0u); + CY_SET_REG8(USBFS_ARB_RW1_WA_MSB_PTR, 0u); + + #if(USBFS_EP_MM != USBFS__EP_MANUAL) + /* Init transfer descriptor. This will be used to detect the DMA state - initialized or not. */ + for (i = 0u; i < USBFS_MAX_EP; i++) + { + USBFS_DmaTd[i] = DMA_INVALID_TD; + } + #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ + + CyExitCriticalSection(enableInterrupts); + + + /* Set the bus reset Interrupt. */ + (void) CyIntSetVector(USBFS_BUS_RESET_VECT_NUM, &USBFS_BUS_RESET_ISR); + CyIntSetPriority(USBFS_BUS_RESET_VECT_NUM, USBFS_BUS_RESET_PRIOR); + + /* Set the SOF Interrupt. */ + #if(USBFS_SOF_ISR_REMOVE == 0u) + (void) CyIntSetVector(USBFS_SOF_VECT_NUM, &USBFS_SOF_ISR); + CyIntSetPriority(USBFS_SOF_VECT_NUM, USBFS_SOF_PRIOR); + #endif /* End USBFS_SOF_ISR_REMOVE */ + + /* Set the Control Endpoint Interrupt. */ + (void) CyIntSetVector(USBFS_EP_0_VECT_NUM, &USBFS_EP_0_ISR); + CyIntSetPriority(USBFS_EP_0_VECT_NUM, USBFS_EP_0_PRIOR); + + /* Set the Data Endpoint 1 Interrupt. */ + #if(USBFS_EP1_ISR_REMOVE == 0u) + (void) CyIntSetVector(USBFS_EP_1_VECT_NUM, &USBFS_EP_1_ISR); + CyIntSetPriority(USBFS_EP_1_VECT_NUM, USBFS_EP_1_PRIOR); + #endif /* End USBFS_EP1_ISR_REMOVE */ + + /* Set the Data Endpoint 2 Interrupt. */ + #if(USBFS_EP2_ISR_REMOVE == 0u) + (void) CyIntSetVector(USBFS_EP_2_VECT_NUM, &USBFS_EP_2_ISR); + CyIntSetPriority(USBFS_EP_2_VECT_NUM, USBFS_EP_2_PRIOR); + #endif /* End USBFS_EP2_ISR_REMOVE */ + + /* Set the Data Endpoint 3 Interrupt. */ + #if(USBFS_EP3_ISR_REMOVE == 0u) + (void) CyIntSetVector(USBFS_EP_3_VECT_NUM, &USBFS_EP_3_ISR); + CyIntSetPriority(USBFS_EP_3_VECT_NUM, USBFS_EP_3_PRIOR); + #endif /* End USBFS_EP3_ISR_REMOVE */ + + /* Set the Data Endpoint 4 Interrupt. */ + #if(USBFS_EP4_ISR_REMOVE == 0u) + (void) CyIntSetVector(USBFS_EP_4_VECT_NUM, &USBFS_EP_4_ISR); + CyIntSetPriority(USBFS_EP_4_VECT_NUM, USBFS_EP_4_PRIOR); + #endif /* End USBFS_EP4_ISR_REMOVE */ + + /* Set the Data Endpoint 5 Interrupt. */ + #if(USBFS_EP5_ISR_REMOVE == 0u) + (void) CyIntSetVector(USBFS_EP_5_VECT_NUM, &USBFS_EP_5_ISR); + CyIntSetPriority(USBFS_EP_5_VECT_NUM, USBFS_EP_5_PRIOR); + #endif /* End USBFS_EP5_ISR_REMOVE */ + + /* Set the Data Endpoint 6 Interrupt. */ + #if(USBFS_EP6_ISR_REMOVE == 0u) + (void) CyIntSetVector(USBFS_EP_6_VECT_NUM, &USBFS_EP_6_ISR); + CyIntSetPriority(USBFS_EP_6_VECT_NUM, USBFS_EP_6_PRIOR); + #endif /* End USBFS_EP6_ISR_REMOVE */ + + /* Set the Data Endpoint 7 Interrupt. */ + #if(USBFS_EP7_ISR_REMOVE == 0u) + (void) CyIntSetVector(USBFS_EP_7_VECT_NUM, &USBFS_EP_7_ISR); + CyIntSetPriority(USBFS_EP_7_VECT_NUM, USBFS_EP_7_PRIOR); + #endif /* End USBFS_EP7_ISR_REMOVE */ + + /* Set the Data Endpoint 8 Interrupt. */ + #if(USBFS_EP8_ISR_REMOVE == 0u) + (void) CyIntSetVector(USBFS_EP_8_VECT_NUM, &USBFS_EP_8_ISR); + CyIntSetPriority(USBFS_EP_8_VECT_NUM, USBFS_EP_8_PRIOR); + #endif /* End USBFS_EP8_ISR_REMOVE */ + + #if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u)) + /* Set the ARB Interrupt. */ + (void) CyIntSetVector(USBFS_ARB_VECT_NUM, &USBFS_ARB_ISR); + CyIntSetPriority(USBFS_ARB_VECT_NUM, USBFS_ARB_PRIOR); + #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ + +} + + +/******************************************************************************* +* Function Name: USBFS_InitComponent +******************************************************************************** +* +* Summary: +* Initialize the component, except for the HW which is done one time in +* the Start function. This function pulls up D+. +* +* Parameters: +* device: Contains the device number of the desired device descriptor. +* The device number can be found in the Device Descriptor Tab of +* "Configure" dialog, under the settings of desired Device Descriptor, +* in the "Device Number" field. +* mode: The operating voltage. This determines whether the voltage regulator +* is enabled for 5V operation or if pass through mode is used for 3.3V +* operation. Symbolic names and their associated values are given in the +* following table. +* USBFS_3V_OPERATION - Disable voltage regulator and pass-thru +* Vcc for pull-up +* USBFS_5V_OPERATION - Enable voltage regulator and use +* regulator for pull-up +* USBFS_DWR_VDDD_OPERATION - Enable or Disable voltage +* regulator depend on Vddd Voltage configuration in DWR. +* +* Return: +* None. +* +* Global variables: +* USBFS_device: Contains the device number of the desired device +* descriptor. The device number can be found in the Device Descriptor Tab +* of "Configure" dialog, under the settings of desired Device Descriptor, +* in the "Device Number" field. +* USBFS_transferState: This variable used by the communication +* functions to handle current transfer state. Initialized to +* TRANS_STATE_IDLE in this API. +* USBFS_configuration: Contains current configuration number +* which is set by the Host using SET_CONFIGURATION request. +* Initialized to zero in this API. +* USBFS_deviceAddress: Contains current device address. This +* variable is initialized to zero in this API. Host starts to communicate +* to device with address 0 and then set it to whatever value using +* SET_ADDRESS request. +* USBFS_deviceStatus: initialized to 0. +* This is two bit variable which contain power status in first bit +* (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote +* wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit. +* USBFS_lastPacketSize initialized to 0; +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_InitComponent(uint8 device, uint8 mode) +{ + /* Initialize _hidProtocol variable to comply with + * HID 7.2.6 Set_Protocol Request: + * "When initialized, all devices default to report protocol." + */ + #if defined(USBFS_ENABLE_HID_CLASS) + uint8 i; + + for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++) + { + USBFS_hidProtocol[i] = USBFS_PROTOCOL_REPORT; + } + #endif /* USBFS_ENABLE_HID_CLASS */ + + /* Enable Interrupts. */ + CyIntEnable(USBFS_BUS_RESET_VECT_NUM); + CyIntEnable(USBFS_EP_0_VECT_NUM); + #if(USBFS_EP1_ISR_REMOVE == 0u) + CyIntEnable(USBFS_EP_1_VECT_NUM); + #endif /* End USBFS_EP1_ISR_REMOVE */ + #if(USBFS_EP2_ISR_REMOVE == 0u) + CyIntEnable(USBFS_EP_2_VECT_NUM); + #endif /* End USBFS_EP2_ISR_REMOVE */ + #if(USBFS_EP3_ISR_REMOVE == 0u) + CyIntEnable(USBFS_EP_3_VECT_NUM); + #endif /* End USBFS_EP3_ISR_REMOVE */ + #if(USBFS_EP4_ISR_REMOVE == 0u) + CyIntEnable(USBFS_EP_4_VECT_NUM); + #endif /* End USBFS_EP4_ISR_REMOVE */ + #if(USBFS_EP5_ISR_REMOVE == 0u) + CyIntEnable(USBFS_EP_5_VECT_NUM); + #endif /* End USBFS_EP5_ISR_REMOVE */ + #if(USBFS_EP6_ISR_REMOVE == 0u) + CyIntEnable(USBFS_EP_6_VECT_NUM); + #endif /* End USBFS_EP6_ISR_REMOVE */ + #if(USBFS_EP7_ISR_REMOVE == 0u) + CyIntEnable(USBFS_EP_7_VECT_NUM); + #endif /* End USBFS_EP7_ISR_REMOVE */ + #if(USBFS_EP8_ISR_REMOVE == 0u) + CyIntEnable(USBFS_EP_8_VECT_NUM); + #endif /* End USBFS_EP8_ISR_REMOVE */ + #if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u)) + /* usb arb interrupt enable */ + USBFS_ARB_INT_EN_REG = USBFS_ARB_INT_MASK; + CyIntEnable(USBFS_ARB_VECT_NUM); + #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ + + /* Arbiter configuration for DMA transfers */ + #if(USBFS_EP_MM != USBFS__EP_MANUAL) + + #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL) + USBFS_ARB_CFG_REG = USBFS_ARB_CFG_MANUAL_DMA; + #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */ + #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + /*Set cfg cmplt this rises DMA request when the full configuration is done */ + USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM; + #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ + #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ + + USBFS_transferState = USBFS_TRANS_STATE_IDLE; + + /* USB Locking: Enabled, VRegulator: depend on mode or DWR Voltage configuration*/ + switch(mode) + { + case USBFS_3V_OPERATION: + USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK; + break; + case USBFS_5V_OPERATION: + USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK | USBFS_CR1_REG_ENABLE; + break; + default: /*USBFS_DWR_VDDD_OPERATION */ + #if(USBFS_VDDD_MV < USBFS_3500MV) + USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK; + #else + USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK | USBFS_CR1_REG_ENABLE; + #endif /* End USBFS_VDDD_MV < USBFS_3500MV */ + break; + } + + /* Record the descriptor selection */ + USBFS_device = device; + + /* Clear all of the component data */ + USBFS_configuration = 0u; + USBFS_interfaceNumber = 0u; + USBFS_configurationChanged = 0u; + USBFS_deviceAddress = 0u; + USBFS_deviceStatus = 0u; + + USBFS_lastPacketSize = 0u; + + /* ACK Setup, Stall IN/OUT */ + CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT); + + /* Enable the SIE with an address 0 */ + CY_SET_REG8(USBFS_CR0_PTR, USBFS_CR0_ENABLE); + + /* Workaround for PSOC5LP */ + CyDelayCycles(1u); + + /* Finally, Enable d+ pullup and select iomode to USB mode*/ + CY_SET_REG8(USBFS_USBIO_CR1_PTR, USBFS_USBIO_CR1_USBPUEN); +} + + +/******************************************************************************* +* Function Name: USBFS_ReInitComponent +******************************************************************************** +* +* Summary: +* This function reinitialize the component configuration and is +* intend to be called from the Reset interrupt. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* USBFS_device: Contains the device number of the desired device +* descriptor. The device number can be found in the Device Descriptor Tab +* of "Configure" dialog, under the settings of desired Device Descriptor, +* in the "Device Number" field. +* USBFS_transferState: This variable used by the communication +* functions to handle current transfer state. Initialized to +* TRANS_STATE_IDLE in this API. +* USBFS_configuration: Contains current configuration number +* which is set by the Host using SET_CONFIGURATION request. +* Initialized to zero in this API. +* USBFS_deviceAddress: Contains current device address. This +* variable is initialized to zero in this API. Host starts to communicate +* to device with address 0 and then set it to whatever value using +* SET_ADDRESS request. +* USBFS_deviceStatus: initialized to 0. +* This is two bit variable which contain power status in first bit +* (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote +* wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit. +* USBFS_lastPacketSize initialized to 0; +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_ReInitComponent(void) +{ + /* Initialize _hidProtocol variable to comply with HID 7.2.6 Set_Protocol + * Request: "When initialized, all devices default to report protocol." + */ + #if defined(USBFS_ENABLE_HID_CLASS) + uint8 i; + + for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++) + { + USBFS_hidProtocol[i] = USBFS_PROTOCOL_REPORT; + } + #endif /* USBFS_ENABLE_HID_CLASS */ + + USBFS_transferState = USBFS_TRANS_STATE_IDLE; + + /* Clear all of the component data */ + USBFS_configuration = 0u; + USBFS_interfaceNumber = 0u; + USBFS_configurationChanged = 0u; + USBFS_deviceAddress = 0u; + USBFS_deviceStatus = 0u; + + USBFS_lastPacketSize = 0u; + + + /* ACK Setup, Stall IN/OUT */ + CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT); + + /* Enable the SIE with an address 0 */ + CY_SET_REG8(USBFS_CR0_PTR, USBFS_CR0_ENABLE); + +} + + +/******************************************************************************* +* Function Name: USBFS_Stop +******************************************************************************** +* +* Summary: +* This function shuts down the USB function including to release +* the D+ Pullup and disabling the SIE. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* USBFS_configuration: Contains current configuration number +* which is set by the Host using SET_CONFIGURATION request. +* Initialized to zero in this API. +* USBFS_deviceAddress: Contains current device address. This +* variable is initialized to zero in this API. Host starts to communicate +* to device with address 0 and then set it to whatever value using +* SET_ADDRESS request. +* USBFS_deviceStatus: initialized to 0. +* This is two bit variable which contain power status in first bit +* (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote +* wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit. +* USBFS_configurationChanged: This variable is set to one after +* SET_CONFIGURATION request and cleared in this function. +* USBFS_intiVar variable is set to zero +* +*******************************************************************************/ +void USBFS_Stop(void) +{ + + #if(USBFS_EP_MM != USBFS__EP_MANUAL) + USBFS_Stop_DMA(USBFS_MAX_EP); /* Stop all DMAs */ + #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ + + /* Disable the SIE */ + USBFS_CR0_REG &= (uint8)(~USBFS_CR0_ENABLE); + /* Disable the d+ pullup */ + USBFS_USBIO_CR1_REG &= (uint8)(~USBFS_USBIO_CR1_USBPUEN); + /* Disable USB in ACT PM */ + USBFS_PM_ACT_CFG_REG &= (uint8)(~USBFS_PM_ACT_EN_FSUSB); + /* Disable USB block for Standby Power Mode */ + USBFS_PM_STBY_CFG_REG &= (uint8)(~USBFS_PM_STBY_EN_FSUSB); + + /* Disable the reset and EP interrupts */ + CyIntDisable(USBFS_BUS_RESET_VECT_NUM); + CyIntDisable(USBFS_EP_0_VECT_NUM); + #if(USBFS_EP1_ISR_REMOVE == 0u) + CyIntDisable(USBFS_EP_1_VECT_NUM); + #endif /* End USBFS_EP1_ISR_REMOVE */ + #if(USBFS_EP2_ISR_REMOVE == 0u) + CyIntDisable(USBFS_EP_2_VECT_NUM); + #endif /* End USBFS_EP2_ISR_REMOVE */ + #if(USBFS_EP3_ISR_REMOVE == 0u) + CyIntDisable(USBFS_EP_3_VECT_NUM); + #endif /* End USBFS_EP3_ISR_REMOVE */ + #if(USBFS_EP4_ISR_REMOVE == 0u) + CyIntDisable(USBFS_EP_4_VECT_NUM); + #endif /* End USBFS_EP4_ISR_REMOVE */ + #if(USBFS_EP5_ISR_REMOVE == 0u) + CyIntDisable(USBFS_EP_5_VECT_NUM); + #endif /* End USBFS_EP5_ISR_REMOVE */ + #if(USBFS_EP6_ISR_REMOVE == 0u) + CyIntDisable(USBFS_EP_6_VECT_NUM); + #endif /* End USBFS_EP6_ISR_REMOVE */ + #if(USBFS_EP7_ISR_REMOVE == 0u) + CyIntDisable(USBFS_EP_7_VECT_NUM); + #endif /* End USBFS_EP7_ISR_REMOVE */ + #if(USBFS_EP8_ISR_REMOVE == 0u) + CyIntDisable(USBFS_EP_8_VECT_NUM); + #endif /* End USBFS_EP8_ISR_REMOVE */ + + /* Clear all of the component data */ + USBFS_configuration = 0u; + USBFS_interfaceNumber = 0u; + USBFS_configurationChanged = 0u; + USBFS_deviceAddress = 0u; + USBFS_deviceStatus = 0u; + USBFS_initVar = 0u; + +} + + +/******************************************************************************* +* Function Name: USBFS_CheckActivity +******************************************************************************** +* +* Summary: +* Returns the activity status of the bus. Clears the status hardware to +* provide fresh activity status on the next call of this routine. +* +* Parameters: +* None. +* +* Return: +* 1 - If bus activity was detected since the last call to this function +* 0 - If bus activity not was detected since the last call to this function +* +*******************************************************************************/ +uint8 USBFS_CheckActivity(void) +{ + uint8 r; + + r = CY_GET_REG8(USBFS_CR1_PTR); + CY_SET_REG8(USBFS_CR1_PTR, (r & ((uint8)(~USBFS_CR1_BUS_ACTIVITY)))); + + return((r & USBFS_CR1_BUS_ACTIVITY) >> USBFS_CR1_BUS_ACTIVITY_SHIFT); +} + + +/******************************************************************************* +* Function Name: USBFS_GetConfiguration +******************************************************************************** +* +* Summary: +* Returns the current configuration setting +* +* Parameters: +* None. +* +* Return: +* configuration. +* +*******************************************************************************/ +uint8 USBFS_GetConfiguration(void) +{ + return(USBFS_configuration); +} + + +/******************************************************************************* +* Function Name: USBFS_IsConfigurationChanged +******************************************************************************** +* +* Summary: +* Returns the clear on read configuration state. It is usefull when PC send +* double SET_CONFIGURATION request with same configuration number. +* +* Parameters: +* None. +* +* Return: +* Not zero value when new configuration has been changed, otherwise zero is +* returned. +* +* Global variables: +* USBFS_configurationChanged: This variable is set to one after +* SET_CONFIGURATION request and cleared in this function. +* +*******************************************************************************/ +uint8 USBFS_IsConfigurationChanged(void) +{ + uint8 res = 0u; + + if(USBFS_configurationChanged != 0u) + { + res = USBFS_configurationChanged; + USBFS_configurationChanged = 0u; + } + + return(res); +} + + +/******************************************************************************* +* Function Name: USBFS_GetInterfaceSetting +******************************************************************************** +* +* Summary: +* Returns the alternate setting from current interface +* +* Parameters: +* uint8 interfaceNumber, interface number +* +* Return: +* Alternate setting. +* +*******************************************************************************/ +uint8 USBFS_GetInterfaceSetting(uint8 interfaceNumber) + +{ + return(USBFS_interfaceSetting[interfaceNumber]); +} + + +/******************************************************************************* +* Function Name: USBFS_GetEPState +******************************************************************************** +* +* Summary: +* Returned the state of the requested endpoint. +* +* Parameters: +* epNumber: Endpoint Number +* +* Return: +* State of the requested endpoint. +* +*******************************************************************************/ +uint8 USBFS_GetEPState(uint8 epNumber) +{ + return(USBFS_EP[epNumber].apiEpState); +} + + +/******************************************************************************* +* Function Name: USBFS_GetEPCount +******************************************************************************** +* +* Summary: +* This function supports Data Endpoints only(EP1-EP8). +* Returns the transfer count for the requested endpoint. The value from +* the count registers includes 2 counts for the two byte checksum of the +* packet. This function subtracts the two counts. +* +* Parameters: +* epNumber: Data Endpoint Number. +* Valid values are between 1 and 8. +* +* Return: +* Returns the current byte count from the specified endpoint or 0 for an +* invalid endpoint. +* +*******************************************************************************/ +uint16 USBFS_GetEPCount(uint8 epNumber) +{ + uint8 ri; + uint16 result = 0u; + + if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); + + result = (uint8)(CY_GET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri)) & + USBFS_EPX_CNT0_MASK); + result = (result << 8u) | CY_GET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + ri)); + result -= USBFS_EPX_CNTX_CRC_COUNT; + } + return(result); +} + + +#if(USBFS_EP_MM != USBFS__EP_MANUAL) + + + /******************************************************************************* + * Function Name: USBFS_InitEP_DMA + ******************************************************************************** + * + * Summary: + * This function allocates and initializes a DMA channel to be used by the + * USBFS_LoadInEP() or USBFS_ReadOutEP() APIs for data + * transfer. + * + * Parameters: + * epNumber: Contains the data endpoint number. + * Valid values are between 1 and 8. + * *pData: Pointer to a data array that is related to the EP transfers. + * + * Return: + * None. + * + * Reentrant: + * No. + * + *******************************************************************************/ + void USBFS_InitEP_DMA(uint8 epNumber, const uint8 *pData) + + { + uint16 src; + uint16 dst; + #if (CY_PSOC3) /* PSoC 3 */ + src = HI16(CYDEV_SRAM_BASE); + dst = HI16(CYDEV_PERIPH_BASE); + pData = pData; + #else /* PSoC 5 */ + if((USBFS_EP[epNumber].addr & USBFS_DIR_IN) != 0u ) + { /* for the IN EP source is the SRAM memory buffer */ + src = HI16(pData); + dst = HI16(CYDEV_PERIPH_BASE); + } + else + { /* for the OUT EP source is the SIE register */ + src = HI16(CYDEV_PERIPH_BASE); + dst = HI16(pData); + } + #endif /* End C51 */ + switch(epNumber) + { + case USBFS_EP1: + #if(USBFS_DMA1_REMOVE == 0u) + USBFS_DmaChan[epNumber] = USBFS_ep1_DmaInitialize( + USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); + #endif /* End USBFS_DMA1_REMOVE */ + break; + case USBFS_EP2: + #if(USBFS_DMA2_REMOVE == 0u) + USBFS_DmaChan[epNumber] = USBFS_ep2_DmaInitialize( + USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); + #endif /* End USBFS_DMA2_REMOVE */ + break; + case USBFS_EP3: + #if(USBFS_DMA3_REMOVE == 0u) + USBFS_DmaChan[epNumber] = USBFS_ep3_DmaInitialize( + USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); + #endif /* End USBFS_DMA3_REMOVE */ + break; + case USBFS_EP4: + #if(USBFS_DMA4_REMOVE == 0u) + USBFS_DmaChan[epNumber] = USBFS_ep4_DmaInitialize( + USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); + #endif /* End USBFS_DMA4_REMOVE */ + break; + case USBFS_EP5: + #if(USBFS_DMA5_REMOVE == 0u) + USBFS_DmaChan[epNumber] = USBFS_ep5_DmaInitialize( + USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); + #endif /* End USBFS_DMA5_REMOVE */ + break; + case USBFS_EP6: + #if(USBFS_DMA6_REMOVE == 0u) + USBFS_DmaChan[epNumber] = USBFS_ep6_DmaInitialize( + USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); + #endif /* End USBFS_DMA6_REMOVE */ + break; + case USBFS_EP7: + #if(USBFS_DMA7_REMOVE == 0u) + USBFS_DmaChan[epNumber] = USBFS_ep7_DmaInitialize( + USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); + #endif /* End USBFS_DMA7_REMOVE */ + break; + case USBFS_EP8: + #if(USBFS_DMA8_REMOVE == 0u) + USBFS_DmaChan[epNumber] = USBFS_ep8_DmaInitialize( + USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); + #endif /* End USBFS_DMA8_REMOVE */ + break; + default: + /* Do not support EP0 DMA transfers */ + break; + } + if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + USBFS_DmaTd[epNumber] = CyDmaTdAllocate(); + } + } + + + /******************************************************************************* + * Function Name: USBFS_Stop_DMA + ******************************************************************************** + * + * Summary: Stops and free DMA + * + * Parameters: + * epNumber: Contains the data endpoint number or + * USBFS_MAX_EP to stop all DMAs + * + * Return: + * None. + * + * Reentrant: + * No. + * + *******************************************************************************/ + void USBFS_Stop_DMA(uint8 epNumber) + { + uint8 i; + i = (epNumber < USBFS_MAX_EP) ? epNumber : USBFS_EP1; + do + { + if(USBFS_DmaTd[i] != DMA_INVALID_TD) + { + (void) CyDmaChDisable(USBFS_DmaChan[i]); + CyDmaTdFree(USBFS_DmaTd[i]); + USBFS_DmaTd[i] = DMA_INVALID_TD; + } + i++; + }while((i < USBFS_MAX_EP) && (epNumber == USBFS_MAX_EP)); + } + +#endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ + + +/******************************************************************************* +* Function Name: USBFS_LoadInEP +******************************************************************************** +* +* Summary: +* Loads and enables the specified USB data endpoint for an IN interrupt or bulk +* transfer. +* +* Parameters: +* epNumber: Contains the data endpoint number. +* Valid values are between 1 and 8. +* *pData: A pointer to a data array from which the data for the endpoint space +* is loaded. +* length: The number of bytes to transfer from the array and then send as a +* result of an IN request. Valid values are between 0 and 512. +* +* Return: +* None. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length) + +{ + uint8 ri; + reg8 *p; + #if(USBFS_EP_MM == USBFS__EP_MANUAL) + uint16 i; + #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */ + + if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); + p = (reg8 *)(USBFS_ARB_RW1_DR_IND + ri); + + #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) + /* Limits length to available buffer space, auto MM could send packets up to 1024 bytes */ + if(length > (USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset)) + { + length = USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset; + } + #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */ + + /* Set the count and data toggle */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri), + (length >> 8u) | (USBFS_EP[epNumber].epToggle)); + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + ri), length & 0xFFu); + + #if(USBFS_EP_MM == USBFS__EP_MANUAL) + if(pData != NULL) + { + /* Copy the data using the arbiter data register */ + for (i = 0u; i < length; i++) + { + CY_SET_REG8(p, pData[i]); + } + } + USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; + /* Write the Mode register */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode); + #else + /* Init DMA if it was not initialized */ + if(USBFS_DmaTd[epNumber] == DMA_INVALID_TD) + { + USBFS_InitEP_DMA(epNumber, pData); + } + #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */ + + #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL) + USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; + if((pData != NULL) && (length > 0u)) + { + /* Enable DMA in mode2 for transferring data */ + (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); + (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, CY_DMA_DISABLE_TD, + TD_TERMIN_EN | TD_INC_SRC_ADR); + (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)pData), LO16((uint32)p)); + /* Enable the DMA */ + (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); + (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); + /* Generate DMA request */ + * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_DMA_REQ; + * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= ((uint8)(~USBFS_ARB_EPX_CFG_DMA_REQ)); + /* Mode register will be written in arb ISR after DMA transfer complete */ + } + else + { + /* When zero-length packet - write the Mode register directly */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode); + } + #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */ + + #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + if(pData != NULL) + { + /* Enable DMA in mode3 for transferring data */ + (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); + (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, + USBFS_DmaTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR); + (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)pData), LO16((uint32)p)); + /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */ + (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]); + /* Enable the DMA */ + (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); + (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); + } + else + { + USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; + if(length > 0u) + { + /* Set Data ready status, This will generate DMA request */ + * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY; + /* Mode register will be written in arb ISR(In Buffer Full) after first DMA transfer complete */ + } + else + { + /* When zero-length packet - write the Mode register directly */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode); + } + } + #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ + + } +} + + +/******************************************************************************* +* Function Name: USBFS_ReadOutEP +******************************************************************************** +* +* Summary: +* Read data from an endpoint. The application must call +* USBFS_GetEPState to see if an event is pending. +* +* Parameters: +* epNumber: Contains the data endpoint number. +* Valid values are between 1 and 8. +* pData: A pointer to a data array from which the data for the endpoint space +* is loaded. +* length: The number of bytes to transfer from the USB Out endpoint and loads +* it into data array. Valid values are between 0 and 1023. The function +* moves fewer than the requested number of bytes if the host sends +* fewer bytes than requested. +* +* Returns: +* Number of bytes received, 0 for an invalid endpoint. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length) + +{ + uint8 ri; + reg8 *p; + #if(USBFS_EP_MM == USBFS__EP_MANUAL) + uint16 i; + #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */ + #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) + uint16 xferCount; + #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */ + + if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP) && (pData != NULL)) + { + ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); + p = (reg8 *)(USBFS_ARB_RW1_DR_IND + ri); + + #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) + /* Determine which is smaller the requested data or the available data */ + xferCount = USBFS_GetEPCount(epNumber); + if (length > xferCount) + { + length = xferCount; + } + #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */ + + #if(USBFS_EP_MM == USBFS__EP_MANUAL) + /* Copy the data using the arbiter data register */ + for (i = 0u; i < length; i++) + { + pData[i] = CY_GET_REG8(p); + } + + /* (re)arming of OUT endpoint */ + USBFS_EnableOutEP(epNumber); + #else + /*Init DMA if it was not initialized */ + if(USBFS_DmaTd[epNumber] == DMA_INVALID_TD) + { + USBFS_InitEP_DMA(epNumber, pData); + } + #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */ + + #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL) + /* Enable DMA in mode2 for transferring data */ + (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); + (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, CY_DMA_DISABLE_TD, + TD_TERMIN_EN | TD_INC_DST_ADR); + (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)p), LO16((uint32)pData)); + /* Enable the DMA */ + (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); + (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); + + /* Generate DMA request */ + * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_DMA_REQ; + * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= ((uint8)(~USBFS_ARB_EPX_CFG_DMA_REQ)); + /* Out EP will be (re)armed in arb ISR after transfer complete */ + #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */ + + #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + /* Enable DMA in mode3 for transferring data */ + (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); + (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, USBFS_DmaTd[epNumber], + TD_TERMIN_EN | TD_INC_DST_ADR); + (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)p), LO16((uint32)pData)); + + /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */ + (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]); + /* Enable the DMA */ + (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); + (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); + /* Out EP will be (re)armed in arb ISR after transfer complete */ + #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ + + } + else + { + length = 0u; + } + + return(length); +} + + +/******************************************************************************* +* Function Name: USBFS_EnableOutEP +******************************************************************************** +* +* Summary: +* This function enables an OUT endpoint. It should not be +* called for an IN endpoint. +* +* Parameters: +* epNumber: Endpoint Number +* Valid values are between 1 and 8. +* +* Return: +* None. +* +* Global variables: +* USBFS_EP[epNumber].apiEpState - set to NO_EVENT_PENDING +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_EnableOutEP(uint8 epNumber) +{ + uint8 ri; + + if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); + USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; + /* Write the Mode register */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode); + } +} + + +/******************************************************************************* +* Function Name: USBFS_DisableOutEP +******************************************************************************** +* +* Summary: +* This function disables an OUT endpoint. It should not be +* called for an IN endpoint. +* +* Parameters: +* epNumber: Endpoint Number +* Valid values are between 1 and 8. +* +* Return: +* None. +* +*******************************************************************************/ +void USBFS_DisableOutEP(uint8 epNumber) +{ + uint8 ri ; + + if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); + /* Write the Mode register */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_OUT); + } +} + + +/******************************************************************************* +* Function Name: USBFS_Force +******************************************************************************** +* +* Summary: +* Forces the bus state +* +* Parameters: +* bState +* USBFS_FORCE_J +* USBFS_FORCE_K +* USBFS_FORCE_SE0 +* USBFS_FORCE_NONE +* +* Return: +* None. +* +*******************************************************************************/ +void USBFS_Force(uint8 bState) +{ + CY_SET_REG8(USBFS_USBIO_CR0_PTR, bState); +} + + +/******************************************************************************* +* Function Name: USBFS_GetEPAckState +******************************************************************************** +* +* Summary: +* Returns the ACK of the CR0 Register (ACKD) +* +* Parameters: +* epNumber: Endpoint Number +* Valid values are between 1 and 8. +* +* Returns +* 0 if nothing has been ACKD, non-=zero something has been ACKD +* +*******************************************************************************/ +uint8 USBFS_GetEPAckState(uint8 epNumber) +{ + uint8 ri; + uint8 cr = 0u; + + if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); + cr = CY_GET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri)) & USBFS_MODE_ACKD; + } + + return(cr); +} + + +/******************************************************************************* +* Function Name: USBFS_SetPowerStatus +******************************************************************************** +* +* Summary: +* Sets the device power status for reporting in the Get Device Status +* request +* +* Parameters: +* powerStatus: USBFS_DEVICE_STATUS_BUS_POWERED(0) - Bus Powered, +* USBFS_DEVICE_STATUS_SELF_POWERED(1) - Self Powered +* +* Return: +* None. +* +* Global variables: +* USBFS_deviceStatus - set power status +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_SetPowerStatus(uint8 powerStatus) +{ + if (powerStatus != USBFS_DEVICE_STATUS_BUS_POWERED) + { + USBFS_deviceStatus |= USBFS_DEVICE_STATUS_SELF_POWERED; + } + else + { + USBFS_deviceStatus &= ((uint8)(~USBFS_DEVICE_STATUS_SELF_POWERED)); + } +} + + +#if (USBFS_MON_VBUS == 1u) + + /******************************************************************************* + * Function Name: USBFS_VBusPresent + ******************************************************************************** + * + * Summary: + * Determines VBUS presence for Self Powered Devices. + * + * Parameters: + * None. + * + * Return: + * 1 if VBUS is present, otherwise 0. + * + *******************************************************************************/ + uint8 USBFS_VBusPresent(void) + { + return((0u != (CY_GET_REG8(USBFS_VBUS_PS_PTR) & USBFS_VBUS_MASK)) ? 1u : 0u); + } + +#endif /* USBFS_MON_VBUS */ + + +/******************************************************************************* +* Function Name: USBFS_RWUEnabled +******************************************************************************** +* +* Summary: +* Returns TRUE if Remote Wake Up is enabled, otherwise FALSE +* +* Parameters: +* None. +* +* Return: +* TRUE - Remote Wake Up Enabled +* FALSE - Remote Wake Up Disabled +* +* Global variables: +* USBFS_deviceStatus - checked to determine remote status +* +*******************************************************************************/ +uint8 USBFS_RWUEnabled(void) +{ + uint8 result = USBFS_FALSE; + if((USBFS_deviceStatus & USBFS_DEVICE_STATUS_REMOTE_WAKEUP) != 0u) + { + result = USBFS_TRUE; + } + + return(result); +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS.h new file mode 100755 index 00000000..41a8619d --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS.h @@ -0,0 +1,1189 @@ +/******************************************************************************* +* File Name: USBFS.h +* Version 2.60 +* +* Description: +* Header File for the USFS component. Contains prototypes and constant values. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_USBFS_USBFS_H) +#define CY_USBFS_USBFS_H + +#include "cytypes.h" +#include "cydevice_trm.h" +#include "cyfitter.h" +#include "CyLib.h" + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ + +/* Check to see if required defines such as CY_PSOC5LP are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5LP) + #error Component USBFS_v2_60 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5LP) */ + + +/*************************************** +* Memory Type Definitions +***************************************/ + +/* Renamed Type Definitions for backward compatibility. +* Should not be used in new designs. +*/ +#define USBFS_CODE CYCODE +#define USBFS_FAR CYFAR +#if defined(__C51__) || defined(__CX51__) + #define USBFS_DATA data + #define USBFS_XDATA xdata +#else + #define USBFS_DATA + #define USBFS_XDATA +#endif /* End __C51__ */ +#define USBFS_NULL NULL + + +/*************************************** +* Enumerated Types and Parameters +***************************************/ + +#define USBFS__EP_MANUAL 0 +#define USBFS__EP_DMAMANUAL 1 +#define USBFS__EP_DMAAUTO 2 + +#define USBFS__MA_STATIC 0 +#define USBFS__MA_DYNAMIC 1 + + + +/*************************************** +* Initial Parameter Constants +***************************************/ + +#define USBFS_NUM_DEVICES (1u) +#define USBFS_ENABLE_DESCRIPTOR_STRINGS +#define USBFS_ENABLE_SN_STRING +#define USBFS_ENABLE_STRINGS +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF_SIZE (65u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_NUM_IN_RPTS (1u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF_SIZE (65u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_NUM_OUT_RPTS (1u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_COUNT (1u) +#define USBFS_ENABLE_HID_CLASS +#define USBFS_HID_RPT_1_SIZE_LSB (0x24u) +#define USBFS_HID_RPT_1_SIZE_MSB (0x00u) +#define USBFS_MAX_REPORTID_NUMBER (0u) + +#define USBFS_MON_VBUS (0u) +#define USBFS_EXTERN_VBUS (0u) +#define USBFS_EXTERN_VND (0u) +#define USBFS_EXTERN_CLS (0u) +#define USBFS_MAX_INTERFACES_NUMBER (1u) +#define USBFS_EP0_ISR_REMOVE (0u) +#define USBFS_EP1_ISR_REMOVE (0u) +#define USBFS_EP2_ISR_REMOVE (0u) +#define USBFS_EP3_ISR_REMOVE (1u) +#define USBFS_EP4_ISR_REMOVE (1u) +#define USBFS_EP5_ISR_REMOVE (1u) +#define USBFS_EP6_ISR_REMOVE (1u) +#define USBFS_EP7_ISR_REMOVE (1u) +#define USBFS_EP8_ISR_REMOVE (1u) +#define USBFS_EP_MM (0u) +#define USBFS_EP_MA (0u) +#define USBFS_DMA1_REMOVE (1u) +#define USBFS_DMA2_REMOVE (1u) +#define USBFS_DMA3_REMOVE (1u) +#define USBFS_DMA4_REMOVE (1u) +#define USBFS_DMA5_REMOVE (1u) +#define USBFS_DMA6_REMOVE (1u) +#define USBFS_DMA7_REMOVE (1u) +#define USBFS_DMA8_REMOVE (1u) +#define USBFS_SOF_ISR_REMOVE (0u) +#define USBFS_ARB_ISR_REMOVE (0u) +#define USBFS_DP_ISR_REMOVE (0u) +#define USBFS_ENABLE_CDC_CLASS_API (1u) +#define USBFS_ENABLE_MIDI_API (1u) +#define USBFS_MIDI_EXT_MODE (0u) + + +/*************************************** +* Data Struct Definition +***************************************/ + +typedef struct +{ + uint8 attrib; + uint8 apiEpState; + uint8 hwEpState; + uint8 epToggle; + uint8 addr; + uint8 epMode; + uint16 buffOffset; + uint16 bufferSize; + uint8 interface; +} T_USBFS_EP_CTL_BLOCK; + +typedef struct +{ + uint8 interface; + uint8 altSetting; + uint8 addr; + uint8 attributes; + uint16 bufferSize; + uint8 bMisc; +} T_USBFS_EP_SETTINGS_BLOCK; + +typedef struct +{ + uint8 status; + uint16 length; +} T_USBFS_XFER_STATUS_BLOCK; + +typedef struct +{ + uint16 count; + volatile uint8 *pData; + T_USBFS_XFER_STATUS_BLOCK *pStatusBlock; +} T_USBFS_TD; + + +typedef struct +{ + uint8 c; + const void *p_list; +} T_USBFS_LUT; + +/* Resume/Suspend API Support */ +typedef struct +{ + uint8 enableState; + uint8 mode; +} USBFS_BACKUP_STRUCT; + + +/* Renamed structure fields for backward compatibility. +* Should not be used in new designs. +*/ +#define wBuffOffset buffOffset +#define wBufferSize bufferSize +#define bStatus status +#define wLength length +#define wCount count + +/* Renamed global variable for backward compatibility. +* Should not be used in new designs. +*/ +#define CurrentTD USBFS_currentTD + + +/*************************************** +* Function Prototypes +***************************************/ + +void USBFS_Start(uint8 device, uint8 mode) ; +void USBFS_Init(void) ; +void USBFS_InitComponent(uint8 device, uint8 mode) ; +void USBFS_Stop(void) ; +uint8 USBFS_CheckActivity(void) ; +uint8 USBFS_GetConfiguration(void) ; +uint8 USBFS_IsConfigurationChanged(void) ; +uint8 USBFS_GetInterfaceSetting(uint8 interfaceNumber) + ; +uint8 USBFS_GetEPState(uint8 epNumber) ; +uint16 USBFS_GetEPCount(uint8 epNumber) ; +void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length) + ; +uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length) + ; +void USBFS_EnableOutEP(uint8 epNumber) ; +void USBFS_DisableOutEP(uint8 epNumber) ; +void USBFS_Force(uint8 bState) ; +uint8 USBFS_GetEPAckState(uint8 epNumber) ; +void USBFS_SetPowerStatus(uint8 powerStatus) ; +uint8 USBFS_RWUEnabled(void) ; +void USBFS_TerminateEP(uint8 ep) ; + +void USBFS_Suspend(void) ; +void USBFS_Resume(void) ; + +#if defined(USBFS_ENABLE_FWSN_STRING) + void USBFS_SerialNumString(uint8 snString[]) ; +#endif /* USBFS_ENABLE_FWSN_STRING */ +#if (USBFS_MON_VBUS == 1u) + uint8 USBFS_VBusPresent(void) ; +#endif /* End USBFS_MON_VBUS */ + +#if defined(CYDEV_BOOTLOADER_IO_COMP) && ((CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) || \ + (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface)) + + void USBFS_CyBtldrCommStart(void) ; + void USBFS_CyBtldrCommStop(void) ; + void USBFS_CyBtldrCommReset(void) ; + cystatus USBFS_CyBtldrCommWrite(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL + ; + cystatus USBFS_CyBtldrCommRead( uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL + ; + + #define USBFS_BTLDR_SIZEOF_WRITE_BUFFER (64u) /* EP 1 OUT */ + #define USBFS_BTLDR_SIZEOF_READ_BUFFER (64u) /* EP 2 IN */ + #define USBFS_BTLDR_MAX_PACKET_SIZE USBFS_BTLDR_SIZEOF_WRITE_BUFFER + + /* These defines active if used USBFS interface as an + * IO Component for bootloading. When Custom_Interface selected + * in Bootloder configuration as the IO Component, user must + * provide these functions + */ + #if (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) + #define CyBtldrCommStart USBFS_CyBtldrCommStart + #define CyBtldrCommStop USBFS_CyBtldrCommStop + #define CyBtldrCommReset USBFS_CyBtldrCommReset + #define CyBtldrCommWrite USBFS_CyBtldrCommWrite + #define CyBtldrCommRead USBFS_CyBtldrCommRead + #endif /*End CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */ + +#endif /* End CYDEV_BOOTLOADER_IO_COMP */ + +#if(USBFS_EP_MM != USBFS__EP_MANUAL) + void USBFS_InitEP_DMA(uint8 epNumber, const uint8 *pData) + ; + void USBFS_Stop_DMA(uint8 epNumber) ; +#endif /* End USBFS_EP_MM != USBFS__EP_MANUAL) */ + +#if defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u) + void USBFS_MIDI_EP_Init(void) ; + + #if (USBFS_MIDI_IN_BUFF_SIZE > 0) + void USBFS_MIDI_IN_Service(void) ; + uint8 USBFS_PutUsbMidiIn(uint8 ic, const uint8 midiMsg[], uint8 cable) + ; + #endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */ + + #if (USBFS_MIDI_OUT_BUFF_SIZE > 0) + void USBFS_MIDI_OUT_EP_Service(void) ; + #endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */ + +#endif /* End USBFS_ENABLE_MIDI_API != 0u */ + +/* Renamed Functions for backward compatibility. +* Should not be used in new designs. +*/ + +#define USBFS_bCheckActivity USBFS_CheckActivity +#define USBFS_bGetConfiguration USBFS_GetConfiguration +#define USBFS_bGetInterfaceSetting USBFS_GetInterfaceSetting +#define USBFS_bGetEPState USBFS_GetEPState +#define USBFS_wGetEPCount USBFS_GetEPCount +#define USBFS_bGetEPAckState USBFS_GetEPAckState +#define USBFS_bRWUEnabled USBFS_RWUEnabled +#define USBFS_bVBusPresent USBFS_VBusPresent + +#define USBFS_bConfiguration USBFS_configuration +#define USBFS_bInterfaceSetting USBFS_interfaceSetting +#define USBFS_bDeviceAddress USBFS_deviceAddress +#define USBFS_bDeviceStatus USBFS_deviceStatus +#define USBFS_bDevice USBFS_device +#define USBFS_bTransferState USBFS_transferState +#define USBFS_bLastPacketSize USBFS_lastPacketSize + +#define USBFS_LoadEP USBFS_LoadInEP +#define USBFS_LoadInISOCEP USBFS_LoadInEP +#define USBFS_EnableOutISOCEP USBFS_EnableOutEP + +#define USBFS_SetVector CyIntSetVector +#define USBFS_SetPriority CyIntSetPriority +#define USBFS_EnableInt CyIntEnable + + +/*************************************** +* API Constants +***************************************/ + +#define USBFS_EP0 (0u) +#define USBFS_EP1 (1u) +#define USBFS_EP2 (2u) +#define USBFS_EP3 (3u) +#define USBFS_EP4 (4u) +#define USBFS_EP5 (5u) +#define USBFS_EP6 (6u) +#define USBFS_EP7 (7u) +#define USBFS_EP8 (8u) +#define USBFS_MAX_EP (9u) + +#define USBFS_TRUE (1u) +#define USBFS_FALSE (0u) + +#define USBFS_NO_EVENT_ALLOWED (2u) +#define USBFS_EVENT_PENDING (1u) +#define USBFS_NO_EVENT_PENDING (0u) + +#define USBFS_IN_BUFFER_FULL USBFS_NO_EVENT_PENDING +#define USBFS_IN_BUFFER_EMPTY USBFS_EVENT_PENDING +#define USBFS_OUT_BUFFER_FULL USBFS_EVENT_PENDING +#define USBFS_OUT_BUFFER_EMPTY USBFS_NO_EVENT_PENDING + +#define USBFS_FORCE_J (0xA0u) +#define USBFS_FORCE_K (0x80u) +#define USBFS_FORCE_SE0 (0xC0u) +#define USBFS_FORCE_NONE (0x00u) + +#define USBFS_IDLE_TIMER_RUNNING (0x02u) +#define USBFS_IDLE_TIMER_EXPIRED (0x01u) +#define USBFS_IDLE_TIMER_INDEFINITE (0x00u) + +#define USBFS_DEVICE_STATUS_BUS_POWERED (0x00u) +#define USBFS_DEVICE_STATUS_SELF_POWERED (0x01u) + +#define USBFS_3V_OPERATION (0x00u) +#define USBFS_5V_OPERATION (0x01u) +#define USBFS_DWR_VDDD_OPERATION (0x02u) + +#define USBFS_MODE_DISABLE (0x00u) +#define USBFS_MODE_NAK_IN_OUT (0x01u) +#define USBFS_MODE_STATUS_OUT_ONLY (0x02u) +#define USBFS_MODE_STALL_IN_OUT (0x03u) +#define USBFS_MODE_RESERVED_0100 (0x04u) +#define USBFS_MODE_ISO_OUT (0x05u) +#define USBFS_MODE_STATUS_IN_ONLY (0x06u) +#define USBFS_MODE_ISO_IN (0x07u) +#define USBFS_MODE_NAK_OUT (0x08u) +#define USBFS_MODE_ACK_OUT (0x09u) +#define USBFS_MODE_RESERVED_1010 (0x0Au) +#define USBFS_MODE_ACK_OUT_STATUS_IN (0x0Bu) +#define USBFS_MODE_NAK_IN (0x0Cu) +#define USBFS_MODE_ACK_IN (0x0Du) +#define USBFS_MODE_RESERVED_1110 (0x0Eu) +#define USBFS_MODE_ACK_IN_STATUS_OUT (0x0Fu) +#define USBFS_MODE_MASK (0x0Fu) +#define USBFS_MODE_STALL_DATA_EP (0x80u) + +#define USBFS_MODE_ACKD (0x10u) +#define USBFS_MODE_OUT_RCVD (0x20u) +#define USBFS_MODE_IN_RCVD (0x40u) +#define USBFS_MODE_SETUP_RCVD (0x80u) + +#define USBFS_RQST_TYPE_MASK (0x60u) +#define USBFS_RQST_TYPE_STD (0x00u) +#define USBFS_RQST_TYPE_CLS (0x20u) +#define USBFS_RQST_TYPE_VND (0x40u) +#define USBFS_RQST_DIR_MASK (0x80u) +#define USBFS_RQST_DIR_D2H (0x80u) +#define USBFS_RQST_DIR_H2D (0x00u) +#define USBFS_RQST_RCPT_MASK (0x03u) +#define USBFS_RQST_RCPT_DEV (0x00u) +#define USBFS_RQST_RCPT_IFC (0x01u) +#define USBFS_RQST_RCPT_EP (0x02u) +#define USBFS_RQST_RCPT_OTHER (0x03u) + +/* USB Class Codes */ +#define USBFS_CLASS_DEVICE (0x00u) /* Use class code info from Interface Descriptors */ +#define USBFS_CLASS_AUDIO (0x01u) /* Audio device */ +#define USBFS_CLASS_CDC (0x02u) /* Communication device class */ +#define USBFS_CLASS_HID (0x03u) /* Human Interface Device */ +#define USBFS_CLASS_PDC (0x05u) /* Physical device class */ +#define USBFS_CLASS_IMAGE (0x06u) /* Still Imaging device */ +#define USBFS_CLASS_PRINTER (0x07u) /* Printer device */ +#define USBFS_CLASS_MSD (0x08u) /* Mass Storage device */ +#define USBFS_CLASS_HUB (0x09u) /* Full/Hi speed Hub */ +#define USBFS_CLASS_CDC_DATA (0x0Au) /* CDC data device */ +#define USBFS_CLASS_SMART_CARD (0x0Bu) /* Smart Card device */ +#define USBFS_CLASS_CSD (0x0Du) /* Content Security device */ +#define USBFS_CLASS_VIDEO (0x0Eu) /* Video device */ +#define USBFS_CLASS_PHD (0x0Fu) /* Personal Healthcare device */ +#define USBFS_CLASS_WIRELESSD (0xDCu) /* Wireless Controller */ +#define USBFS_CLASS_MIS (0xE0u) /* Miscellaneous */ +#define USBFS_CLASS_APP (0xEFu) /* Application Specific */ +#define USBFS_CLASS_VENDOR (0xFFu) /* Vendor specific */ + + +/* Standard Request Types (Table 9-4) */ +#define USBFS_GET_STATUS (0x00u) +#define USBFS_CLEAR_FEATURE (0x01u) +#define USBFS_SET_FEATURE (0x03u) +#define USBFS_SET_ADDRESS (0x05u) +#define USBFS_GET_DESCRIPTOR (0x06u) +#define USBFS_SET_DESCRIPTOR (0x07u) +#define USBFS_GET_CONFIGURATION (0x08u) +#define USBFS_SET_CONFIGURATION (0x09u) +#define USBFS_GET_INTERFACE (0x0Au) +#define USBFS_SET_INTERFACE (0x0Bu) +#define USBFS_SYNCH_FRAME (0x0Cu) + +/* Vendor Specific Request Types */ +/* Request for Microsoft OS String Descriptor */ +#define USBFS_GET_EXTENDED_CONFIG_DESCRIPTOR (0x01u) + +/* Descriptor Types (Table 9-5) */ +#define USBFS_DESCR_DEVICE (1u) +#define USBFS_DESCR_CONFIG (2u) +#define USBFS_DESCR_STRING (3u) +#define USBFS_DESCR_INTERFACE (4u) +#define USBFS_DESCR_ENDPOINT (5u) +#define USBFS_DESCR_DEVICE_QUALIFIER (6u) +#define USBFS_DESCR_OTHER_SPEED (7u) +#define USBFS_DESCR_INTERFACE_POWER (8u) + +/* Device Descriptor Defines */ +#define USBFS_DEVICE_DESCR_LENGTH (18u) +#define USBFS_DEVICE_DESCR_SN_SHIFT (16u) + +/* Config Descriptor Shifts and Masks */ +#define USBFS_CONFIG_DESCR_LENGTH (0u) +#define USBFS_CONFIG_DESCR_TYPE (1u) +#define USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW (2u) +#define USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI (3u) +#define USBFS_CONFIG_DESCR_NUM_INTERFACES (4u) +#define USBFS_CONFIG_DESCR_CONFIG_VALUE (5u) +#define USBFS_CONFIG_DESCR_CONFIGURATION (6u) +#define USBFS_CONFIG_DESCR_ATTRIB (7u) +#define USBFS_CONFIG_DESCR_ATTRIB_SELF_POWERED (0x40u) +#define USBFS_CONFIG_DESCR_ATTRIB_RWU_EN (0x20u) + +/* Feature Selectors (Table 9-6) */ +#define USBFS_DEVICE_REMOTE_WAKEUP (0x01u) +#define USBFS_ENDPOINT_HALT (0x00u) +#define USBFS_TEST_MODE (0x02u) + +/* USB Device Status (Figure 9-4) */ +#define USBFS_DEVICE_STATUS_BUS_POWERED (0x00u) +#define USBFS_DEVICE_STATUS_SELF_POWERED (0x01u) +#define USBFS_DEVICE_STATUS_REMOTE_WAKEUP (0x02u) + +/* USB Endpoint Status (Figure 9-4) */ +#define USBFS_ENDPOINT_STATUS_HALT (0x01u) + +/* USB Endpoint Directions */ +#define USBFS_DIR_IN (0x80u) +#define USBFS_DIR_OUT (0x00u) +#define USBFS_DIR_UNUSED (0x7Fu) + +/* USB Endpoint Attributes */ +#define USBFS_EP_TYPE_CTRL (0x00u) +#define USBFS_EP_TYPE_ISOC (0x01u) +#define USBFS_EP_TYPE_BULK (0x02u) +#define USBFS_EP_TYPE_INT (0x03u) +#define USBFS_EP_TYPE_MASK (0x03u) + +#define USBFS_EP_SYNC_TYPE_NO_SYNC (0x00u) +#define USBFS_EP_SYNC_TYPE_ASYNC (0x04u) +#define USBFS_EP_SYNC_TYPE_ADAPTIVE (0x08u) +#define USBFS_EP_SYNC_TYPE_SYNCHRONOUS (0x0Cu) +#define USBFS_EP_SYNC_TYPE_MASK (0x0Cu) + +#define USBFS_EP_USAGE_TYPE_DATA (0x00u) +#define USBFS_EP_USAGE_TYPE_FEEDBACK (0x10u) +#define USBFS_EP_USAGE_TYPE_IMPLICIT (0x20u) +#define USBFS_EP_USAGE_TYPE_RESERVED (0x30u) +#define USBFS_EP_USAGE_TYPE_MASK (0x30u) + +/* Endpoint Status defines */ +#define USBFS_EP_STATUS_LENGTH (0x02u) + +/* Endpoint Device defines */ +#define USBFS_DEVICE_STATUS_LENGTH (0x02u) + +#define USBFS_STATUS_LENGTH_MAX \ + ( (USBFS_EP_STATUS_LENGTH > USBFS_DEVICE_STATUS_LENGTH) ? \ + USBFS_EP_STATUS_LENGTH : USBFS_DEVICE_STATUS_LENGTH ) +/* Transfer Completion Notification */ +#define USBFS_XFER_IDLE (0x00u) +#define USBFS_XFER_STATUS_ACK (0x01u) +#define USBFS_XFER_PREMATURE (0x02u) +#define USBFS_XFER_ERROR (0x03u) + +/* Driver State defines */ +#define USBFS_TRANS_STATE_IDLE (0x00u) +#define USBFS_TRANS_STATE_CONTROL_READ (0x02u) +#define USBFS_TRANS_STATE_CONTROL_WRITE (0x04u) +#define USBFS_TRANS_STATE_NO_DATA_CONTROL (0x06u) + +/* String Descriptor defines */ +#define USBFS_STRING_MSOS (0xEEu) +#define USBFS_MSOS_DESCRIPTOR_LENGTH (18u) +#define USBFS_MSOS_CONF_DESCR_LENGTH (40u) + +#if(USBFS_EP_MM == USBFS__EP_DMAMANUAL) + /* DMA manual mode defines */ + #define USBFS_DMA_BYTES_PER_BURST (0u) + #define USBFS_DMA_REQUEST_PER_BURST (0u) +#endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */ +#if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + /* DMA automatic mode defines */ + #define USBFS_DMA_BYTES_PER_BURST (32u) + /* BUF_SIZE-BYTES_PER_BURST examples: 55-32 bytes 44-16 bytes 33-8 bytes 22-4 bytes 11-2 bytes */ + #define USBFS_DMA_BUF_SIZE (0x55u) + #define USBFS_DMA_REQUEST_PER_BURST (1u) +#endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ + +/* DIE ID string descriptor defines */ +#if defined(USBFS_ENABLE_IDSN_STRING) + #define USBFS_IDSN_DESCR_LENGTH (0x22u) +#endif /* USBFS_ENABLE_IDSN_STRING */ + + +/*************************************** +* External data references +***************************************/ + +extern uint8 USBFS_initVar; +extern volatile uint8 USBFS_device; +extern volatile uint8 USBFS_transferState; +extern volatile uint8 USBFS_configuration; +extern volatile uint8 USBFS_configurationChanged; +extern volatile uint8 USBFS_deviceStatus; + +/* HID Variables */ +#if defined(USBFS_ENABLE_HID_CLASS) + extern volatile uint8 USBFS_hidProtocol[USBFS_MAX_INTERFACES_NUMBER]; + extern volatile uint8 USBFS_hidIdleRate[USBFS_MAX_INTERFACES_NUMBER]; + extern volatile uint8 USBFS_hidIdleTimer[USBFS_MAX_INTERFACES_NUMBER]; +#endif /* USBFS_ENABLE_HID_CLASS */ + + +/*************************************** +* Registers +***************************************/ + +#define USBFS_ARB_CFG_PTR ( (reg8 *) USBFS_USB__ARB_CFG) +#define USBFS_ARB_CFG_REG (* (reg8 *) USBFS_USB__ARB_CFG) + +#define USBFS_ARB_EP1_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP1_CFG) +#define USBFS_ARB_EP1_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP1_CFG) +#define USBFS_ARB_EP1_CFG_IND USBFS_USB__ARB_EP1_CFG +#define USBFS_ARB_EP1_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP1_INT_EN) +#define USBFS_ARB_EP1_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP1_INT_EN) +#define USBFS_ARB_EP1_INT_EN_IND USBFS_USB__ARB_EP1_INT_EN +#define USBFS_ARB_EP1_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP1_SR) +#define USBFS_ARB_EP1_SR_REG (* (reg8 *) USBFS_USB__ARB_EP1_SR) +#define USBFS_ARB_EP1_SR_IND USBFS_USB__ARB_EP1_SR + +#define USBFS_ARB_EP2_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP2_CFG) +#define USBFS_ARB_EP2_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP2_CFG) +#define USBFS_ARB_EP2_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP2_INT_EN) +#define USBFS_ARB_EP2_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP2_INT_EN) +#define USBFS_ARB_EP2_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP2_SR) +#define USBFS_ARB_EP2_SR_REG (* (reg8 *) USBFS_USB__ARB_EP2_SR) + +#define USBFS_ARB_EP3_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP3_CFG) +#define USBFS_ARB_EP3_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP3_CFG) +#define USBFS_ARB_EP3_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP3_INT_EN) +#define USBFS_ARB_EP3_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP3_INT_EN) +#define USBFS_ARB_EP3_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP3_SR) +#define USBFS_ARB_EP3_SR_REG (* (reg8 *) USBFS_USB__ARB_EP3_SR) + +#define USBFS_ARB_EP4_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP4_CFG) +#define USBFS_ARB_EP4_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP4_CFG) +#define USBFS_ARB_EP4_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP4_INT_EN) +#define USBFS_ARB_EP4_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP4_INT_EN) +#define USBFS_ARB_EP4_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP4_SR) +#define USBFS_ARB_EP4_SR_REG (* (reg8 *) USBFS_USB__ARB_EP4_SR) + +#define USBFS_ARB_EP5_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP5_CFG) +#define USBFS_ARB_EP5_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP5_CFG) +#define USBFS_ARB_EP5_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP5_INT_EN) +#define USBFS_ARB_EP5_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP5_INT_EN) +#define USBFS_ARB_EP5_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP5_SR) +#define USBFS_ARB_EP5_SR_REG (* (reg8 *) USBFS_USB__ARB_EP5_SR) + +#define USBFS_ARB_EP6_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP6_CFG) +#define USBFS_ARB_EP6_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP6_CFG) +#define USBFS_ARB_EP6_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP6_INT_EN) +#define USBFS_ARB_EP6_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP6_INT_EN) +#define USBFS_ARB_EP6_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP6_SR) +#define USBFS_ARB_EP6_SR_REG (* (reg8 *) USBFS_USB__ARB_EP6_SR) + +#define USBFS_ARB_EP7_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP7_CFG) +#define USBFS_ARB_EP7_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP7_CFG) +#define USBFS_ARB_EP7_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP7_INT_EN) +#define USBFS_ARB_EP7_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP7_INT_EN) +#define USBFS_ARB_EP7_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP7_SR) +#define USBFS_ARB_EP7_SR_REG (* (reg8 *) USBFS_USB__ARB_EP7_SR) + +#define USBFS_ARB_EP8_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP8_CFG) +#define USBFS_ARB_EP8_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP8_CFG) +#define USBFS_ARB_EP8_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP8_INT_EN) +#define USBFS_ARB_EP8_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP8_INT_EN) +#define USBFS_ARB_EP8_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP8_SR) +#define USBFS_ARB_EP8_SR_REG (* (reg8 *) USBFS_USB__ARB_EP8_SR) + +#define USBFS_ARB_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_INT_EN) +#define USBFS_ARB_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_INT_EN) +#define USBFS_ARB_INT_SR_PTR ( (reg8 *) USBFS_USB__ARB_INT_SR) +#define USBFS_ARB_INT_SR_REG (* (reg8 *) USBFS_USB__ARB_INT_SR) + +#define USBFS_ARB_RW1_DR_PTR ((reg8 *) USBFS_USB__ARB_RW1_DR) +#define USBFS_ARB_RW1_DR_IND USBFS_USB__ARB_RW1_DR +#define USBFS_ARB_RW1_RA_PTR ((reg8 *) USBFS_USB__ARB_RW1_RA) +#define USBFS_ARB_RW1_RA_IND USBFS_USB__ARB_RW1_RA +#define USBFS_ARB_RW1_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW1_RA_MSB) +#define USBFS_ARB_RW1_RA_MSB_IND USBFS_USB__ARB_RW1_RA_MSB +#define USBFS_ARB_RW1_WA_PTR ((reg8 *) USBFS_USB__ARB_RW1_WA) +#define USBFS_ARB_RW1_WA_IND USBFS_USB__ARB_RW1_WA +#define USBFS_ARB_RW1_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW1_WA_MSB) +#define USBFS_ARB_RW1_WA_MSB_IND USBFS_USB__ARB_RW1_WA_MSB + +#define USBFS_ARB_RW2_DR_PTR ((reg8 *) USBFS_USB__ARB_RW2_DR) +#define USBFS_ARB_RW2_RA_PTR ((reg8 *) USBFS_USB__ARB_RW2_RA) +#define USBFS_ARB_RW2_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW2_RA_MSB) +#define USBFS_ARB_RW2_WA_PTR ((reg8 *) USBFS_USB__ARB_RW2_WA) +#define USBFS_ARB_RW2_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW2_WA_MSB) + +#define USBFS_ARB_RW3_DR_PTR ((reg8 *) USBFS_USB__ARB_RW3_DR) +#define USBFS_ARB_RW3_RA_PTR ((reg8 *) USBFS_USB__ARB_RW3_RA) +#define USBFS_ARB_RW3_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW3_RA_MSB) +#define USBFS_ARB_RW3_WA_PTR ((reg8 *) USBFS_USB__ARB_RW3_WA) +#define USBFS_ARB_RW3_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW3_WA_MSB) + +#define USBFS_ARB_RW4_DR_PTR ((reg8 *) USBFS_USB__ARB_RW4_DR) +#define USBFS_ARB_RW4_RA_PTR ((reg8 *) USBFS_USB__ARB_RW4_RA) +#define USBFS_ARB_RW4_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW4_RA_MSB) +#define USBFS_ARB_RW4_WA_PTR ((reg8 *) USBFS_USB__ARB_RW4_WA) +#define USBFS_ARB_RW4_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW4_WA_MSB) + +#define USBFS_ARB_RW5_DR_PTR ((reg8 *) USBFS_USB__ARB_RW5_DR) +#define USBFS_ARB_RW5_RA_PTR ((reg8 *) USBFS_USB__ARB_RW5_RA) +#define USBFS_ARB_RW5_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW5_RA_MSB) +#define USBFS_ARB_RW5_WA_PTR ((reg8 *) USBFS_USB__ARB_RW5_WA) +#define USBFS_ARB_RW5_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW5_WA_MSB) + +#define USBFS_ARB_RW6_DR_PTR ((reg8 *) USBFS_USB__ARB_RW6_DR) +#define USBFS_ARB_RW6_RA_PTR ((reg8 *) USBFS_USB__ARB_RW6_RA) +#define USBFS_ARB_RW6_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW6_RA_MSB) +#define USBFS_ARB_RW6_WA_PTR ((reg8 *) USBFS_USB__ARB_RW6_WA) +#define USBFS_ARB_RW6_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW6_WA_MSB) + +#define USBFS_ARB_RW7_DR_PTR ((reg8 *) USBFS_USB__ARB_RW7_DR) +#define USBFS_ARB_RW7_RA_PTR ((reg8 *) USBFS_USB__ARB_RW7_RA) +#define USBFS_ARB_RW7_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW7_RA_MSB) +#define USBFS_ARB_RW7_WA_PTR ((reg8 *) USBFS_USB__ARB_RW7_WA) +#define USBFS_ARB_RW7_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW7_WA_MSB) + +#define USBFS_ARB_RW8_DR_PTR ((reg8 *) USBFS_USB__ARB_RW8_DR) +#define USBFS_ARB_RW8_RA_PTR ((reg8 *) USBFS_USB__ARB_RW8_RA) +#define USBFS_ARB_RW8_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW8_RA_MSB) +#define USBFS_ARB_RW8_WA_PTR ((reg8 *) USBFS_USB__ARB_RW8_WA) +#define USBFS_ARB_RW8_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW8_WA_MSB) + +#define USBFS_BUF_SIZE_PTR ( (reg8 *) USBFS_USB__BUF_SIZE) +#define USBFS_BUF_SIZE_REG (* (reg8 *) USBFS_USB__BUF_SIZE) +#define USBFS_BUS_RST_CNT_PTR ( (reg8 *) USBFS_USB__BUS_RST_CNT) +#define USBFS_BUS_RST_CNT_REG (* (reg8 *) USBFS_USB__BUS_RST_CNT) +#define USBFS_CWA_PTR ( (reg8 *) USBFS_USB__CWA) +#define USBFS_CWA_REG (* (reg8 *) USBFS_USB__CWA) +#define USBFS_CWA_MSB_PTR ( (reg8 *) USBFS_USB__CWA_MSB) +#define USBFS_CWA_MSB_REG (* (reg8 *) USBFS_USB__CWA_MSB) +#define USBFS_CR0_PTR ( (reg8 *) USBFS_USB__CR0) +#define USBFS_CR0_REG (* (reg8 *) USBFS_USB__CR0) +#define USBFS_CR1_PTR ( (reg8 *) USBFS_USB__CR1) +#define USBFS_CR1_REG (* (reg8 *) USBFS_USB__CR1) + +#define USBFS_DMA_THRES_PTR ( (reg8 *) USBFS_USB__DMA_THRES) +#define USBFS_DMA_THRES_REG (* (reg8 *) USBFS_USB__DMA_THRES) +#define USBFS_DMA_THRES_MSB_PTR ( (reg8 *) USBFS_USB__DMA_THRES_MSB) +#define USBFS_DMA_THRES_MSB_REG (* (reg8 *) USBFS_USB__DMA_THRES_MSB) + +#define USBFS_EP_ACTIVE_PTR ( (reg8 *) USBFS_USB__EP_ACTIVE) +#define USBFS_EP_ACTIVE_REG (* (reg8 *) USBFS_USB__EP_ACTIVE) +#define USBFS_EP_TYPE_PTR ( (reg8 *) USBFS_USB__EP_TYPE) +#define USBFS_EP_TYPE_REG (* (reg8 *) USBFS_USB__EP_TYPE) + +#define USBFS_EP0_CNT_PTR ( (reg8 *) USBFS_USB__EP0_CNT) +#define USBFS_EP0_CNT_REG (* (reg8 *) USBFS_USB__EP0_CNT) +#define USBFS_EP0_CR_PTR ( (reg8 *) USBFS_USB__EP0_CR) +#define USBFS_EP0_CR_REG (* (reg8 *) USBFS_USB__EP0_CR) +#define USBFS_EP0_DR0_PTR ( (reg8 *) USBFS_USB__EP0_DR0) +#define USBFS_EP0_DR0_REG (* (reg8 *) USBFS_USB__EP0_DR0) +#define USBFS_EP0_DR0_IND USBFS_USB__EP0_DR0 +#define USBFS_EP0_DR1_PTR ( (reg8 *) USBFS_USB__EP0_DR1) +#define USBFS_EP0_DR1_REG (* (reg8 *) USBFS_USB__EP0_DR1) +#define USBFS_EP0_DR2_PTR ( (reg8 *) USBFS_USB__EP0_DR2) +#define USBFS_EP0_DR2_REG (* (reg8 *) USBFS_USB__EP0_DR2) +#define USBFS_EP0_DR3_PTR ( (reg8 *) USBFS_USB__EP0_DR3) +#define USBFS_EP0_DR3_REG (* (reg8 *) USBFS_USB__EP0_DR3) +#define USBFS_EP0_DR4_PTR ( (reg8 *) USBFS_USB__EP0_DR4) +#define USBFS_EP0_DR4_REG (* (reg8 *) USBFS_USB__EP0_DR4) +#define USBFS_EP0_DR5_PTR ( (reg8 *) USBFS_USB__EP0_DR5) +#define USBFS_EP0_DR5_REG (* (reg8 *) USBFS_USB__EP0_DR5) +#define USBFS_EP0_DR6_PTR ( (reg8 *) USBFS_USB__EP0_DR6) +#define USBFS_EP0_DR6_REG (* (reg8 *) USBFS_USB__EP0_DR6) +#define USBFS_EP0_DR7_PTR ( (reg8 *) USBFS_USB__EP0_DR7) +#define USBFS_EP0_DR7_REG (* (reg8 *) USBFS_USB__EP0_DR7) + +#define USBFS_OSCLK_DR0_PTR ( (reg8 *) USBFS_USB__OSCLK_DR0) +#define USBFS_OSCLK_DR0_REG (* (reg8 *) USBFS_USB__OSCLK_DR0) +#define USBFS_OSCLK_DR1_PTR ( (reg8 *) USBFS_USB__OSCLK_DR1) +#define USBFS_OSCLK_DR1_REG (* (reg8 *) USBFS_USB__OSCLK_DR1) + +#define USBFS_PM_ACT_CFG_PTR ( (reg8 *) USBFS_USB__PM_ACT_CFG) +#define USBFS_PM_ACT_CFG_REG (* (reg8 *) USBFS_USB__PM_ACT_CFG) +#define USBFS_PM_STBY_CFG_PTR ( (reg8 *) USBFS_USB__PM_STBY_CFG) +#define USBFS_PM_STBY_CFG_REG (* (reg8 *) USBFS_USB__PM_STBY_CFG) + +#define USBFS_SIE_EP_INT_EN_PTR ( (reg8 *) USBFS_USB__SIE_EP_INT_EN) +#define USBFS_SIE_EP_INT_EN_REG (* (reg8 *) USBFS_USB__SIE_EP_INT_EN) +#define USBFS_SIE_EP_INT_SR_PTR ( (reg8 *) USBFS_USB__SIE_EP_INT_SR) +#define USBFS_SIE_EP_INT_SR_REG (* (reg8 *) USBFS_USB__SIE_EP_INT_SR) + +#define USBFS_SIE_EP1_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CNT0) +#define USBFS_SIE_EP1_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP1_CNT0) +#define USBFS_SIE_EP1_CNT0_IND USBFS_USB__SIE_EP1_CNT0 +#define USBFS_SIE_EP1_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CNT1) +#define USBFS_SIE_EP1_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP1_CNT1) +#define USBFS_SIE_EP1_CNT1_IND USBFS_USB__SIE_EP1_CNT1 +#define USBFS_SIE_EP1_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CR0) +#define USBFS_SIE_EP1_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP1_CR0) +#define USBFS_SIE_EP1_CR0_IND USBFS_USB__SIE_EP1_CR0 + +#define USBFS_SIE_EP2_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CNT0) +#define USBFS_SIE_EP2_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP2_CNT0) +#define USBFS_SIE_EP2_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CNT1) +#define USBFS_SIE_EP2_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP2_CNT1) +#define USBFS_SIE_EP2_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CR0) +#define USBFS_SIE_EP2_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP2_CR0) + +#define USBFS_SIE_EP3_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CNT0) +#define USBFS_SIE_EP3_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP3_CNT0) +#define USBFS_SIE_EP3_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CNT1) +#define USBFS_SIE_EP3_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP3_CNT1) +#define USBFS_SIE_EP3_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CR0) +#define USBFS_SIE_EP3_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP3_CR0) + +#define USBFS_SIE_EP4_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CNT0) +#define USBFS_SIE_EP4_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP4_CNT0) +#define USBFS_SIE_EP4_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CNT1) +#define USBFS_SIE_EP4_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP4_CNT1) +#define USBFS_SIE_EP4_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CR0) +#define USBFS_SIE_EP4_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP4_CR0) + +#define USBFS_SIE_EP5_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CNT0) +#define USBFS_SIE_EP5_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP5_CNT0) +#define USBFS_SIE_EP5_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CNT1) +#define USBFS_SIE_EP5_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP5_CNT1) +#define USBFS_SIE_EP5_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CR0) +#define USBFS_SIE_EP5_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP5_CR0) + +#define USBFS_SIE_EP6_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CNT0) +#define USBFS_SIE_EP6_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP6_CNT0) +#define USBFS_SIE_EP6_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CNT1) +#define USBFS_SIE_EP6_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP6_CNT1) +#define USBFS_SIE_EP6_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CR0) +#define USBFS_SIE_EP6_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP6_CR0) + +#define USBFS_SIE_EP7_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CNT0) +#define USBFS_SIE_EP7_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP7_CNT0) +#define USBFS_SIE_EP7_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CNT1) +#define USBFS_SIE_EP7_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP7_CNT1) +#define USBFS_SIE_EP7_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CR0) +#define USBFS_SIE_EP7_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP7_CR0) + +#define USBFS_SIE_EP8_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CNT0) +#define USBFS_SIE_EP8_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP8_CNT0) +#define USBFS_SIE_EP8_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CNT1) +#define USBFS_SIE_EP8_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP8_CNT1) +#define USBFS_SIE_EP8_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CR0) +#define USBFS_SIE_EP8_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP8_CR0) + +#define USBFS_SOF0_PTR ( (reg8 *) USBFS_USB__SOF0) +#define USBFS_SOF0_REG (* (reg8 *) USBFS_USB__SOF0) +#define USBFS_SOF1_PTR ( (reg8 *) USBFS_USB__SOF1) +#define USBFS_SOF1_REG (* (reg8 *) USBFS_USB__SOF1) + +#define USBFS_USB_CLK_EN_PTR ( (reg8 *) USBFS_USB__USB_CLK_EN) +#define USBFS_USB_CLK_EN_REG (* (reg8 *) USBFS_USB__USB_CLK_EN) + +#define USBFS_USBIO_CR0_PTR ( (reg8 *) USBFS_USB__USBIO_CR0) +#define USBFS_USBIO_CR0_REG (* (reg8 *) USBFS_USB__USBIO_CR0) +#define USBFS_USBIO_CR1_PTR ( (reg8 *) USBFS_USB__USBIO_CR1) +#define USBFS_USBIO_CR1_REG (* (reg8 *) USBFS_USB__USBIO_CR1) +#if(!CY_PSOC5LP) + #define USBFS_USBIO_CR2_PTR ( (reg8 *) USBFS_USB__USBIO_CR2) + #define USBFS_USBIO_CR2_REG (* (reg8 *) USBFS_USB__USBIO_CR2) +#endif /* End CY_PSOC5LP */ + +#define USBFS_DIE_ID CYDEV_FLSHID_CUST_TABLES_BASE + +#define USBFS_PM_USB_CR0_PTR ( (reg8 *) CYREG_PM_USB_CR0) +#define USBFS_PM_USB_CR0_REG (* (reg8 *) CYREG_PM_USB_CR0) +#define USBFS_DYN_RECONFIG_PTR ( (reg8 *) USBFS_USB__DYN_RECONFIG) +#define USBFS_DYN_RECONFIG_REG (* (reg8 *) USBFS_USB__DYN_RECONFIG) + +#define USBFS_DM_INP_DIS_PTR ( (reg8 *) USBFS_Dm__INP_DIS) +#define USBFS_DM_INP_DIS_REG (* (reg8 *) USBFS_Dm__INP_DIS) +#define USBFS_DP_INP_DIS_PTR ( (reg8 *) USBFS_Dp__INP_DIS) +#define USBFS_DP_INP_DIS_REG (* (reg8 *) USBFS_Dp__INP_DIS) +#define USBFS_DP_INTSTAT_PTR ( (reg8 *) USBFS_Dp__INTSTAT) +#define USBFS_DP_INTSTAT_REG (* (reg8 *) USBFS_Dp__INTSTAT) + +#if (USBFS_MON_VBUS == 1u) + #if (USBFS_EXTERN_VBUS == 0u) + #define USBFS_VBUS_DR_PTR ( (reg8 *) USBFS_VBUS__DR) + #define USBFS_VBUS_DR_REG (* (reg8 *) USBFS_VBUS__DR) + #define USBFS_VBUS_PS_PTR ( (reg8 *) USBFS_VBUS__PS) + #define USBFS_VBUS_PS_REG (* (reg8 *) USBFS_VBUS__PS) + #define USBFS_VBUS_MASK USBFS_VBUS__MASK + #else + #define USBFS_VBUS_PS_PTR ( (reg8 *) USBFS_Vbus_ps_sts_sts_reg__STATUS_REG ) + #define USBFS_VBUS_MASK (0x01u) + #endif /* End USBFS_EXTERN_VBUS == 0u */ +#endif /* End USBFS_MON_VBUS */ + +/* Renamed Registers for backward compatibility. +* Should not be used in new designs. +*/ +#define USBFS_ARB_CFG USBFS_ARB_CFG_PTR + +#define USBFS_ARB_EP1_CFG USBFS_ARB_EP1_CFG_PTR +#define USBFS_ARB_EP1_INT_EN USBFS_ARB_EP1_INT_EN_PTR +#define USBFS_ARB_EP1_SR USBFS_ARB_EP1_SR_PTR + +#define USBFS_ARB_EP2_CFG USBFS_ARB_EP2_CFG_PTR +#define USBFS_ARB_EP2_INT_EN USBFS_ARB_EP2_INT_EN_PTR +#define USBFS_ARB_EP2_SR USBFS_ARB_EP2_SR_PTR + +#define USBFS_ARB_EP3_CFG USBFS_ARB_EP3_CFG_PTR +#define USBFS_ARB_EP3_INT_EN USBFS_ARB_EP3_INT_EN_PTR +#define USBFS_ARB_EP3_SR USBFS_ARB_EP3_SR_PTR + +#define USBFS_ARB_EP4_CFG USBFS_ARB_EP4_CFG_PTR +#define USBFS_ARB_EP4_INT_EN USBFS_ARB_EP4_INT_EN_PTR +#define USBFS_ARB_EP4_SR USBFS_ARB_EP4_SR_PTR + +#define USBFS_ARB_EP5_CFG USBFS_ARB_EP5_CFG_PTR +#define USBFS_ARB_EP5_INT_EN USBFS_ARB_EP5_INT_EN_PTR +#define USBFS_ARB_EP5_SR USBFS_ARB_EP5_SR_PTR + +#define USBFS_ARB_EP6_CFG USBFS_ARB_EP6_CFG_PTR +#define USBFS_ARB_EP6_INT_EN USBFS_ARB_EP6_INT_EN_PTR +#define USBFS_ARB_EP6_SR USBFS_ARB_EP6_SR_PTR + +#define USBFS_ARB_EP7_CFG USBFS_ARB_EP7_CFG_PTR +#define USBFS_ARB_EP7_INT_EN USBFS_ARB_EP7_INT_EN_PTR +#define USBFS_ARB_EP7_SR USBFS_ARB_EP7_SR_PTR + +#define USBFS_ARB_EP8_CFG USBFS_ARB_EP8_CFG_PTR +#define USBFS_ARB_EP8_INT_EN USBFS_ARB_EP8_INT_EN_PTR +#define USBFS_ARB_EP8_SR USBFS_ARB_EP8_SR_PTR + +#define USBFS_ARB_INT_EN USBFS_ARB_INT_EN_PTR +#define USBFS_ARB_INT_SR USBFS_ARB_INT_SR_PTR + +#define USBFS_ARB_RW1_DR USBFS_ARB_RW1_DR_PTR +#define USBFS_ARB_RW1_RA USBFS_ARB_RW1_RA_PTR +#define USBFS_ARB_RW1_RA_MSB USBFS_ARB_RW1_RA_MSB_PTR +#define USBFS_ARB_RW1_WA USBFS_ARB_RW1_WA_PTR +#define USBFS_ARB_RW1_WA_MSB USBFS_ARB_RW1_WA_MSB_PTR + +#define USBFS_ARB_RW2_DR USBFS_ARB_RW2_DR_PTR +#define USBFS_ARB_RW2_RA USBFS_ARB_RW2_RA_PTR +#define USBFS_ARB_RW2_RA_MSB USBFS_ARB_RW2_RA_MSB_PTR +#define USBFS_ARB_RW2_WA USBFS_ARB_RW2_WA_PTR +#define USBFS_ARB_RW2_WA_MSB USBFS_ARB_RW2_WA_MSB_PTR + +#define USBFS_ARB_RW3_DR USBFS_ARB_RW3_DR_PTR +#define USBFS_ARB_RW3_RA USBFS_ARB_RW3_RA_PTR +#define USBFS_ARB_RW3_RA_MSB USBFS_ARB_RW3_RA_MSB_PTR +#define USBFS_ARB_RW3_WA USBFS_ARB_RW3_WA_PTR +#define USBFS_ARB_RW3_WA_MSB USBFS_ARB_RW3_WA_MSB_PTR + +#define USBFS_ARB_RW4_DR USBFS_ARB_RW4_DR_PTR +#define USBFS_ARB_RW4_RA USBFS_ARB_RW4_RA_PTR +#define USBFS_ARB_RW4_RA_MSB USBFS_ARB_RW4_RA_MSB_PTR +#define USBFS_ARB_RW4_WA USBFS_ARB_RW4_WA_PTR +#define USBFS_ARB_RW4_WA_MSB USBFS_ARB_RW4_WA_MSB_PTR + +#define USBFS_ARB_RW5_DR USBFS_ARB_RW5_DR_PTR +#define USBFS_ARB_RW5_RA USBFS_ARB_RW5_RA_PTR +#define USBFS_ARB_RW5_RA_MSB USBFS_ARB_RW5_RA_MSB_PTR +#define USBFS_ARB_RW5_WA USBFS_ARB_RW5_WA_PTR +#define USBFS_ARB_RW5_WA_MSB USBFS_ARB_RW5_WA_MSB_PTR + +#define USBFS_ARB_RW6_DR USBFS_ARB_RW6_DR_PTR +#define USBFS_ARB_RW6_RA USBFS_ARB_RW6_RA_PTR +#define USBFS_ARB_RW6_RA_MSB USBFS_ARB_RW6_RA_MSB_PTR +#define USBFS_ARB_RW6_WA USBFS_ARB_RW6_WA_PTR +#define USBFS_ARB_RW6_WA_MSB USBFS_ARB_RW6_WA_MSB_PTR + +#define USBFS_ARB_RW7_DR USBFS_ARB_RW7_DR_PTR +#define USBFS_ARB_RW7_RA USBFS_ARB_RW7_RA_PTR +#define USBFS_ARB_RW7_RA_MSB USBFS_ARB_RW7_RA_MSB_PTR +#define USBFS_ARB_RW7_WA USBFS_ARB_RW7_WA_PTR +#define USBFS_ARB_RW7_WA_MSB USBFS_ARB_RW7_WA_MSB_PTR + +#define USBFS_ARB_RW8_DR USBFS_ARB_RW8_DR_PTR +#define USBFS_ARB_RW8_RA USBFS_ARB_RW8_RA_PTR +#define USBFS_ARB_RW8_RA_MSB USBFS_ARB_RW8_RA_MSB_PTR +#define USBFS_ARB_RW8_WA USBFS_ARB_RW8_WA_PTR +#define USBFS_ARB_RW8_WA_MSB USBFS_ARB_RW8_WA_MSB_PTR + +#define USBFS_BUF_SIZE USBFS_BUF_SIZE_PTR +#define USBFS_BUS_RST_CNT USBFS_BUS_RST_CNT_PTR +#define USBFS_CR0 USBFS_CR0_PTR +#define USBFS_CR1 USBFS_CR1_PTR +#define USBFS_CWA USBFS_CWA_PTR +#define USBFS_CWA_MSB USBFS_CWA_MSB_PTR + +#define USBFS_DMA_THRES USBFS_DMA_THRES_PTR +#define USBFS_DMA_THRES_MSB USBFS_DMA_THRES_MSB_PTR + +#define USBFS_EP_ACTIVE USBFS_EP_ACTIVE_PTR +#define USBFS_EP_TYPE USBFS_EP_TYPE_PTR + +#define USBFS_EP0_CNT USBFS_EP0_CNT_PTR +#define USBFS_EP0_CR USBFS_EP0_CR_PTR +#define USBFS_EP0_DR0 USBFS_EP0_DR0_PTR +#define USBFS_EP0_DR1 USBFS_EP0_DR1_PTR +#define USBFS_EP0_DR2 USBFS_EP0_DR2_PTR +#define USBFS_EP0_DR3 USBFS_EP0_DR3_PTR +#define USBFS_EP0_DR4 USBFS_EP0_DR4_PTR +#define USBFS_EP0_DR5 USBFS_EP0_DR5_PTR +#define USBFS_EP0_DR6 USBFS_EP0_DR6_PTR +#define USBFS_EP0_DR7 USBFS_EP0_DR7_PTR + +#define USBFS_OSCLK_DR0 USBFS_OSCLK_DR0_PTR +#define USBFS_OSCLK_DR1 USBFS_OSCLK_DR1_PTR + +#define USBFS_PM_ACT_CFG USBFS_PM_ACT_CFG_PTR +#define USBFS_PM_STBY_CFG USBFS_PM_STBY_CFG_PTR + +#define USBFS_SIE_EP_INT_EN USBFS_SIE_EP_INT_EN_PTR +#define USBFS_SIE_EP_INT_SR USBFS_SIE_EP_INT_SR_PTR + +#define USBFS_SIE_EP1_CNT0 USBFS_SIE_EP1_CNT0_PTR +#define USBFS_SIE_EP1_CNT1 USBFS_SIE_EP1_CNT1_PTR +#define USBFS_SIE_EP1_CR0 USBFS_SIE_EP1_CR0_PTR + +#define USBFS_SIE_EP2_CNT0 USBFS_SIE_EP2_CNT0_PTR +#define USBFS_SIE_EP2_CNT1 USBFS_SIE_EP2_CNT1_PTR +#define USBFS_SIE_EP2_CR0 USBFS_SIE_EP2_CR0_PTR + +#define USBFS_SIE_EP3_CNT0 USBFS_SIE_EP3_CNT0_PTR +#define USBFS_SIE_EP3_CNT1 USBFS_SIE_EP3_CNT1_PTR +#define USBFS_SIE_EP3_CR0 USBFS_SIE_EP3_CR0_PTR + +#define USBFS_SIE_EP4_CNT0 USBFS_SIE_EP4_CNT0_PTR +#define USBFS_SIE_EP4_CNT1 USBFS_SIE_EP4_CNT1_PTR +#define USBFS_SIE_EP4_CR0 USBFS_SIE_EP4_CR0_PTR + +#define USBFS_SIE_EP5_CNT0 USBFS_SIE_EP5_CNT0_PTR +#define USBFS_SIE_EP5_CNT1 USBFS_SIE_EP5_CNT1_PTR +#define USBFS_SIE_EP5_CR0 USBFS_SIE_EP5_CR0_PTR + +#define USBFS_SIE_EP6_CNT0 USBFS_SIE_EP6_CNT0_PTR +#define USBFS_SIE_EP6_CNT1 USBFS_SIE_EP6_CNT1_PTR +#define USBFS_SIE_EP6_CR0 USBFS_SIE_EP6_CR0_PTR + +#define USBFS_SIE_EP7_CNT0 USBFS_SIE_EP7_CNT0_PTR +#define USBFS_SIE_EP7_CNT1 USBFS_SIE_EP7_CNT1_PTR +#define USBFS_SIE_EP7_CR0 USBFS_SIE_EP7_CR0_PTR + +#define USBFS_SIE_EP8_CNT0 USBFS_SIE_EP8_CNT0_PTR +#define USBFS_SIE_EP8_CNT1 USBFS_SIE_EP8_CNT1_PTR +#define USBFS_SIE_EP8_CR0 USBFS_SIE_EP8_CR0_PTR + +#define USBFS_SOF0 USBFS_SOF0_PTR +#define USBFS_SOF1 USBFS_SOF1_PTR + +#define USBFS_USB_CLK_EN USBFS_USB_CLK_EN_PTR + +#define USBFS_USBIO_CR0 USBFS_USBIO_CR0_PTR +#define USBFS_USBIO_CR1 USBFS_USBIO_CR1_PTR +#define USBFS_USBIO_CR2 USBFS_USBIO_CR2_PTR + +#define USBFS_USB_MEM ((reg8 *) CYDEV_USB_MEM_BASE) + +#if(CYDEV_CHIP_DIE_EXPECT == CYDEV_CHIP_DIE_LEOPARD) + /* PSoC3 interrupt registers*/ + #define USBFS_USB_ISR_PRIOR ((reg8 *) CYDEV_INTC_PRIOR0) + #define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_INTC_SET_EN0) + #define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_INTC_CLR_EN0) + #define USBFS_USB_ISR_VECT ((cyisraddress *) CYDEV_INTC_VECT_MBASE) +#elif(CYDEV_CHIP_DIE_EXPECT == CYDEV_CHIP_DIE_PANTHER) + /* PSoC5 interrupt registers*/ + #define USBFS_USB_ISR_PRIOR ((reg8 *) CYDEV_NVIC_PRI_0) + #define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_NVIC_SETENA0) + #define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_NVIC_CLRENA0) + #define USBFS_USB_ISR_VECT ((cyisraddress *) CYDEV_NVIC_VECT_OFFSET) +#endif /* End CYDEV_CHIP_DIE_EXPECT */ + + +/*************************************** +* Interrupt vectors, masks and priorities +***************************************/ + +#define USBFS_BUS_RESET_PRIOR USBFS_bus_reset__INTC_PRIOR_NUM +#define USBFS_BUS_RESET_MASK USBFS_bus_reset__INTC_MASK +#define USBFS_BUS_RESET_VECT_NUM USBFS_bus_reset__INTC_NUMBER + +#define USBFS_SOF_PRIOR USBFS_sof_int__INTC_PRIOR_NUM +#define USBFS_SOF_MASK USBFS_sof_int__INTC_MASK +#define USBFS_SOF_VECT_NUM USBFS_sof_int__INTC_NUMBER + +#define USBFS_EP_0_PRIOR USBFS_ep_0__INTC_PRIOR_NUM +#define USBFS_EP_0_MASK USBFS_ep_0__INTC_MASK +#define USBFS_EP_0_VECT_NUM USBFS_ep_0__INTC_NUMBER + +#define USBFS_EP_1_PRIOR USBFS_ep_1__INTC_PRIOR_NUM +#define USBFS_EP_1_MASK USBFS_ep_1__INTC_MASK +#define USBFS_EP_1_VECT_NUM USBFS_ep_1__INTC_NUMBER + +#define USBFS_EP_2_PRIOR USBFS_ep_2__INTC_PRIOR_NUM +#define USBFS_EP_2_MASK USBFS_ep_2__INTC_MASK +#define USBFS_EP_2_VECT_NUM USBFS_ep_2__INTC_NUMBER + +#define USBFS_EP_3_PRIOR USBFS_ep_3__INTC_PRIOR_NUM +#define USBFS_EP_3_MASK USBFS_ep_3__INTC_MASK +#define USBFS_EP_3_VECT_NUM USBFS_ep_3__INTC_NUMBER + +#define USBFS_EP_4_PRIOR USBFS_ep_4__INTC_PRIOR_NUM +#define USBFS_EP_4_MASK USBFS_ep_4__INTC_MASK +#define USBFS_EP_4_VECT_NUM USBFS_ep_4__INTC_NUMBER + +#define USBFS_EP_5_PRIOR USBFS_ep_5__INTC_PRIOR_NUM +#define USBFS_EP_5_MASK USBFS_ep_5__INTC_MASK +#define USBFS_EP_5_VECT_NUM USBFS_ep_5__INTC_NUMBER + +#define USBFS_EP_6_PRIOR USBFS_ep_6__INTC_PRIOR_NUM +#define USBFS_EP_6_MASK USBFS_ep_6__INTC_MASK +#define USBFS_EP_6_VECT_NUM USBFS_ep_6__INTC_NUMBER + +#define USBFS_EP_7_PRIOR USBFS_ep_7__INTC_PRIOR_NUM +#define USBFS_EP_7_MASK USBFS_ep_7__INTC_MASK +#define USBFS_EP_7_VECT_NUM USBFS_ep_7__INTC_NUMBER + +#define USBFS_EP_8_PRIOR USBFS_ep_8__INTC_PRIOR_NUM +#define USBFS_EP_8_MASK USBFS_ep_8__INTC_MASK +#define USBFS_EP_8_VECT_NUM USBFS_ep_8__INTC_NUMBER + +#define USBFS_DP_INTC_PRIOR USBFS_dp_int__INTC_PRIOR_NUM +#define USBFS_DP_INTC_MASK USBFS_dp_int__INTC_MASK +#define USBFS_DP_INTC_VECT_NUM USBFS_dp_int__INTC_NUMBER + +/* ARB ISR should have higher priority from EP_X ISR, therefore it is defined to highest (0) */ +#define USBFS_ARB_PRIOR (0u) +#define USBFS_ARB_MASK USBFS_arb_int__INTC_MASK +#define USBFS_ARB_VECT_NUM USBFS_arb_int__INTC_NUMBER + +/*************************************** + * Endpoint 0 offsets (Table 9-2) + **************************************/ + +#define USBFS_bmRequestType USBFS_EP0_DR0_PTR +#define USBFS_bRequest USBFS_EP0_DR1_PTR +#define USBFS_wValue USBFS_EP0_DR2_PTR +#define USBFS_wValueHi USBFS_EP0_DR3_PTR +#define USBFS_wValueLo USBFS_EP0_DR2_PTR +#define USBFS_wIndex USBFS_EP0_DR4_PTR +#define USBFS_wIndexHi USBFS_EP0_DR5_PTR +#define USBFS_wIndexLo USBFS_EP0_DR4_PTR +#define USBFS_length USBFS_EP0_DR6_PTR +#define USBFS_lengthHi USBFS_EP0_DR7_PTR +#define USBFS_lengthLo USBFS_EP0_DR6_PTR + + +/*************************************** +* Register Constants +***************************************/ +#define USBFS_VDDD_MV CYDEV_VDDD_MV +#define USBFS_3500MV (3500u) + +#define USBFS_CR1_REG_ENABLE (0x01u) +#define USBFS_CR1_ENABLE_LOCK (0x02u) +#define USBFS_CR1_BUS_ACTIVITY_SHIFT (0x02u) +#define USBFS_CR1_BUS_ACTIVITY ((uint8)(0x01u << USBFS_CR1_BUS_ACTIVITY_SHIFT)) +#define USBFS_CR1_TRIM_MSB_EN (0x08u) + +#define USBFS_EP0_CNT_DATA_TOGGLE (0x80u) +#define USBFS_EPX_CNT_DATA_TOGGLE (0x80u) +#define USBFS_EPX_CNT0_MASK (0x0Fu) +#define USBFS_EPX_CNTX_MSB_MASK (0x07u) +#define USBFS_EPX_CNTX_ADDR_SHIFT (0x04u) +#define USBFS_EPX_CNTX_ADDR_OFFSET (0x10u) +#define USBFS_EPX_CNTX_CRC_COUNT (0x02u) +#define USBFS_EPX_DATA_BUF_MAX (512u) + +#define USBFS_CR0_ENABLE (0x80u) + +/* A 100 KHz clock is used for BUS reset count. Recommended is to count 10 pulses */ +#define USBFS_BUS_RST_COUNT (0x0au) + +#define USBFS_USBIO_CR1_IOMODE (0x20u) +#define USBFS_USBIO_CR1_USBPUEN (0x04u) +#define USBFS_USBIO_CR1_DP0 (0x02u) +#define USBFS_USBIO_CR1_DM0 (0x01u) + +#define USBFS_USBIO_CR0_TEN (0x80u) +#define USBFS_USBIO_CR0_TSE0 (0x40u) +#define USBFS_USBIO_CR0_TD (0x20u) +#define USBFS_USBIO_CR0_RD (0x01u) + +#define USBFS_FASTCLK_IMO_CR_USBCLK_ON (0x40u) +#define USBFS_FASTCLK_IMO_CR_XCLKEN (0x20u) +#define USBFS_FASTCLK_IMO_CR_FX2ON (0x10u) + +#define USBFS_ARB_EPX_CFG_RESET (0x08u) +#define USBFS_ARB_EPX_CFG_CRC_BYPASS (0x04u) +#define USBFS_ARB_EPX_CFG_DMA_REQ (0x02u) +#define USBFS_ARB_EPX_CFG_IN_DATA_RDY (0x01u) + +#define USBFS_ARB_EPX_SR_IN_BUF_FULL (0x01u) +#define USBFS_ARB_EPX_SR_DMA_GNT (0x02u) +#define USBFS_ARB_EPX_SR_BUF_OVER (0x04u) +#define USBFS_ARB_EPX_SR_BUF_UNDER (0x08u) + +#define USBFS_ARB_CFG_AUTO_MEM (0x10u) +#define USBFS_ARB_CFG_MANUAL_DMA (0x20u) +#define USBFS_ARB_CFG_AUTO_DMA (0x40u) +#define USBFS_ARB_CFG_CFG_CPM (0x80u) + +#if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + #define USBFS_ARB_EPX_INT_MASK (0x1Du) +#else + #define USBFS_ARB_EPX_INT_MASK (0x1Fu) +#endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ +#define USBFS_ARB_INT_MASK (uint8)((USBFS_DMA1_REMOVE ^ 1u) | \ + (uint8)((USBFS_DMA2_REMOVE ^ 1u) << 1u) | \ + (uint8)((USBFS_DMA3_REMOVE ^ 1u) << 2u) | \ + (uint8)((USBFS_DMA4_REMOVE ^ 1u) << 3u) | \ + (uint8)((USBFS_DMA5_REMOVE ^ 1u) << 4u) | \ + (uint8)((USBFS_DMA6_REMOVE ^ 1u) << 5u) | \ + (uint8)((USBFS_DMA7_REMOVE ^ 1u) << 6u) | \ + (uint8)((USBFS_DMA8_REMOVE ^ 1u) << 7u) ) + +#define USBFS_SIE_EP_INT_EP1_MASK (0x01u) +#define USBFS_SIE_EP_INT_EP2_MASK (0x02u) +#define USBFS_SIE_EP_INT_EP3_MASK (0x04u) +#define USBFS_SIE_EP_INT_EP4_MASK (0x08u) +#define USBFS_SIE_EP_INT_EP5_MASK (0x10u) +#define USBFS_SIE_EP_INT_EP6_MASK (0x20u) +#define USBFS_SIE_EP_INT_EP7_MASK (0x40u) +#define USBFS_SIE_EP_INT_EP8_MASK (0x80u) + +#define USBFS_PM_ACT_EN_FSUSB USBFS_USB__PM_ACT_MSK +#define USBFS_PM_STBY_EN_FSUSB USBFS_USB__PM_STBY_MSK +#define USBFS_PM_AVAIL_EN_FSUSBIO (0x10u) + +#define USBFS_PM_USB_CR0_REF_EN (0x01u) +#define USBFS_PM_USB_CR0_PD_N (0x02u) +#define USBFS_PM_USB_CR0_PD_PULLUP_N (0x04u) + +#define USBFS_USB_CLK_ENABLE (0x01u) + +#define USBFS_DM_MASK USBFS_Dm__0__MASK +#define USBFS_DP_MASK USBFS_Dp__0__MASK + +#define USBFS_DYN_RECONFIG_ENABLE (0x01u) +#define USBFS_DYN_RECONFIG_EP_SHIFT (0x01u) +#define USBFS_DYN_RECONFIG_RDY_STS (0x10u) + + +#endif /* End CY_USBFS_USBFS_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_Dm.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_Dm.c new file mode 100755 index 00000000..e942a8f8 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_Dm.c @@ -0,0 +1,137 @@ +/******************************************************************************* +* File Name: USBFS_Dm.c +* Version 1.90 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "USBFS_Dm.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + USBFS_Dm__PORT == 15 && ((USBFS_Dm__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: USBFS_Dm_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void USBFS_Dm_Write(uint8 value) +{ + uint8 staticBits = (USBFS_Dm_DR & (uint8)(~USBFS_Dm_MASK)); + USBFS_Dm_DR = staticBits | ((uint8)(value << USBFS_Dm_SHIFT) & USBFS_Dm_MASK); +} + + +/******************************************************************************* +* Function Name: USBFS_Dm_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to this drive mode. +* +* Return: +* None +* +*******************************************************************************/ +void USBFS_Dm_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(USBFS_Dm_0, mode); +} + + +/******************************************************************************* +* Function Name: USBFS_Dm_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro USBFS_Dm_ReadPS calls this function. +* +*******************************************************************************/ +uint8 USBFS_Dm_Read(void) +{ + return (USBFS_Dm_PS & USBFS_Dm_MASK) >> USBFS_Dm_SHIFT; +} + + +/******************************************************************************* +* Function Name: USBFS_Dm_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 USBFS_Dm_ReadDataReg(void) +{ + return (USBFS_Dm_DR & USBFS_Dm_MASK) >> USBFS_Dm_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(USBFS_Dm_INTSTAT) + + /******************************************************************************* + * Function Name: USBFS_Dm_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 USBFS_Dm_ClearInterrupt(void) + { + return (USBFS_Dm_INTSTAT & USBFS_Dm_MASK) >> USBFS_Dm_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_Dm.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_Dm.h new file mode 100755 index 00000000..bbfcfee4 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_Dm.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: USBFS_Dm.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_USBFS_Dm_H) /* Pins USBFS_Dm_H */ +#define CY_PINS_USBFS_Dm_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "USBFS_Dm_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + USBFS_Dm__PORT == 15 && ((USBFS_Dm__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void USBFS_Dm_Write(uint8 value) ; +void USBFS_Dm_SetDriveMode(uint8 mode) ; +uint8 USBFS_Dm_ReadDataReg(void) ; +uint8 USBFS_Dm_Read(void) ; +uint8 USBFS_Dm_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define USBFS_Dm_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define USBFS_Dm_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define USBFS_Dm_DM_RES_UP PIN_DM_RES_UP +#define USBFS_Dm_DM_RES_DWN PIN_DM_RES_DWN +#define USBFS_Dm_DM_OD_LO PIN_DM_OD_LO +#define USBFS_Dm_DM_OD_HI PIN_DM_OD_HI +#define USBFS_Dm_DM_STRONG PIN_DM_STRONG +#define USBFS_Dm_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define USBFS_Dm_MASK USBFS_Dm__MASK +#define USBFS_Dm_SHIFT USBFS_Dm__SHIFT +#define USBFS_Dm_WIDTH 1u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define USBFS_Dm_PS (* (reg8 *) USBFS_Dm__PS) +/* Data Register */ +#define USBFS_Dm_DR (* (reg8 *) USBFS_Dm__DR) +/* Port Number */ +#define USBFS_Dm_PRT_NUM (* (reg8 *) USBFS_Dm__PRT) +/* Connect to Analog Globals */ +#define USBFS_Dm_AG (* (reg8 *) USBFS_Dm__AG) +/* Analog MUX bux enable */ +#define USBFS_Dm_AMUX (* (reg8 *) USBFS_Dm__AMUX) +/* Bidirectional Enable */ +#define USBFS_Dm_BIE (* (reg8 *) USBFS_Dm__BIE) +/* Bit-mask for Aliased Register Access */ +#define USBFS_Dm_BIT_MASK (* (reg8 *) USBFS_Dm__BIT_MASK) +/* Bypass Enable */ +#define USBFS_Dm_BYP (* (reg8 *) USBFS_Dm__BYP) +/* Port wide control signals */ +#define USBFS_Dm_CTL (* (reg8 *) USBFS_Dm__CTL) +/* Drive Modes */ +#define USBFS_Dm_DM0 (* (reg8 *) USBFS_Dm__DM0) +#define USBFS_Dm_DM1 (* (reg8 *) USBFS_Dm__DM1) +#define USBFS_Dm_DM2 (* (reg8 *) USBFS_Dm__DM2) +/* Input Buffer Disable Override */ +#define USBFS_Dm_INP_DIS (* (reg8 *) USBFS_Dm__INP_DIS) +/* LCD Common or Segment Drive */ +#define USBFS_Dm_LCD_COM_SEG (* (reg8 *) USBFS_Dm__LCD_COM_SEG) +/* Enable Segment LCD */ +#define USBFS_Dm_LCD_EN (* (reg8 *) USBFS_Dm__LCD_EN) +/* Slew Rate Control */ +#define USBFS_Dm_SLW (* (reg8 *) USBFS_Dm__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define USBFS_Dm_PRTDSI__CAPS_SEL (* (reg8 *) USBFS_Dm__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define USBFS_Dm_PRTDSI__DBL_SYNC_IN (* (reg8 *) USBFS_Dm__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define USBFS_Dm_PRTDSI__OE_SEL0 (* (reg8 *) USBFS_Dm__PRTDSI__OE_SEL0) +#define USBFS_Dm_PRTDSI__OE_SEL1 (* (reg8 *) USBFS_Dm__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define USBFS_Dm_PRTDSI__OUT_SEL0 (* (reg8 *) USBFS_Dm__PRTDSI__OUT_SEL0) +#define USBFS_Dm_PRTDSI__OUT_SEL1 (* (reg8 *) USBFS_Dm__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define USBFS_Dm_PRTDSI__SYNC_OUT (* (reg8 *) USBFS_Dm__PRTDSI__SYNC_OUT) + + +#if defined(USBFS_Dm__INTSTAT) /* Interrupt Registers */ + + #define USBFS_Dm_INTSTAT (* (reg8 *) USBFS_Dm__INTSTAT) + #define USBFS_Dm_SNAP (* (reg8 *) USBFS_Dm__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_USBFS_Dm_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h new file mode 100755 index 00000000..21242d52 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h @@ -0,0 +1,32 @@ +/******************************************************************************* +* File Name: USBFS_Dm.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_USBFS_Dm_ALIASES_H) /* Pins USBFS_Dm_ALIASES_H */ +#define CY_PINS_USBFS_Dm_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define USBFS_Dm_0 USBFS_Dm__0__PC + +#endif /* End Pins USBFS_Dm_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_Dp.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_Dp.c new file mode 100755 index 00000000..5904f4ae --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_Dp.c @@ -0,0 +1,137 @@ +/******************************************************************************* +* File Name: USBFS_Dp.c +* Version 1.90 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "USBFS_Dp.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + USBFS_Dp__PORT == 15 && ((USBFS_Dp__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: USBFS_Dp_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void USBFS_Dp_Write(uint8 value) +{ + uint8 staticBits = (USBFS_Dp_DR & (uint8)(~USBFS_Dp_MASK)); + USBFS_Dp_DR = staticBits | ((uint8)(value << USBFS_Dp_SHIFT) & USBFS_Dp_MASK); +} + + +/******************************************************************************* +* Function Name: USBFS_Dp_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to this drive mode. +* +* Return: +* None +* +*******************************************************************************/ +void USBFS_Dp_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(USBFS_Dp_0, mode); +} + + +/******************************************************************************* +* Function Name: USBFS_Dp_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro USBFS_Dp_ReadPS calls this function. +* +*******************************************************************************/ +uint8 USBFS_Dp_Read(void) +{ + return (USBFS_Dp_PS & USBFS_Dp_MASK) >> USBFS_Dp_SHIFT; +} + + +/******************************************************************************* +* Function Name: USBFS_Dp_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 USBFS_Dp_ReadDataReg(void) +{ + return (USBFS_Dp_DR & USBFS_Dp_MASK) >> USBFS_Dp_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(USBFS_Dp_INTSTAT) + + /******************************************************************************* + * Function Name: USBFS_Dp_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 USBFS_Dp_ClearInterrupt(void) + { + return (USBFS_Dp_INTSTAT & USBFS_Dp_MASK) >> USBFS_Dp_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_Dp.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_Dp.h new file mode 100755 index 00000000..217b6a3f --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_Dp.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: USBFS_Dp.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_USBFS_Dp_H) /* Pins USBFS_Dp_H */ +#define CY_PINS_USBFS_Dp_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "USBFS_Dp_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + USBFS_Dp__PORT == 15 && ((USBFS_Dp__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void USBFS_Dp_Write(uint8 value) ; +void USBFS_Dp_SetDriveMode(uint8 mode) ; +uint8 USBFS_Dp_ReadDataReg(void) ; +uint8 USBFS_Dp_Read(void) ; +uint8 USBFS_Dp_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define USBFS_Dp_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define USBFS_Dp_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define USBFS_Dp_DM_RES_UP PIN_DM_RES_UP +#define USBFS_Dp_DM_RES_DWN PIN_DM_RES_DWN +#define USBFS_Dp_DM_OD_LO PIN_DM_OD_LO +#define USBFS_Dp_DM_OD_HI PIN_DM_OD_HI +#define USBFS_Dp_DM_STRONG PIN_DM_STRONG +#define USBFS_Dp_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define USBFS_Dp_MASK USBFS_Dp__MASK +#define USBFS_Dp_SHIFT USBFS_Dp__SHIFT +#define USBFS_Dp_WIDTH 1u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define USBFS_Dp_PS (* (reg8 *) USBFS_Dp__PS) +/* Data Register */ +#define USBFS_Dp_DR (* (reg8 *) USBFS_Dp__DR) +/* Port Number */ +#define USBFS_Dp_PRT_NUM (* (reg8 *) USBFS_Dp__PRT) +/* Connect to Analog Globals */ +#define USBFS_Dp_AG (* (reg8 *) USBFS_Dp__AG) +/* Analog MUX bux enable */ +#define USBFS_Dp_AMUX (* (reg8 *) USBFS_Dp__AMUX) +/* Bidirectional Enable */ +#define USBFS_Dp_BIE (* (reg8 *) USBFS_Dp__BIE) +/* Bit-mask for Aliased Register Access */ +#define USBFS_Dp_BIT_MASK (* (reg8 *) USBFS_Dp__BIT_MASK) +/* Bypass Enable */ +#define USBFS_Dp_BYP (* (reg8 *) USBFS_Dp__BYP) +/* Port wide control signals */ +#define USBFS_Dp_CTL (* (reg8 *) USBFS_Dp__CTL) +/* Drive Modes */ +#define USBFS_Dp_DM0 (* (reg8 *) USBFS_Dp__DM0) +#define USBFS_Dp_DM1 (* (reg8 *) USBFS_Dp__DM1) +#define USBFS_Dp_DM2 (* (reg8 *) USBFS_Dp__DM2) +/* Input Buffer Disable Override */ +#define USBFS_Dp_INP_DIS (* (reg8 *) USBFS_Dp__INP_DIS) +/* LCD Common or Segment Drive */ +#define USBFS_Dp_LCD_COM_SEG (* (reg8 *) USBFS_Dp__LCD_COM_SEG) +/* Enable Segment LCD */ +#define USBFS_Dp_LCD_EN (* (reg8 *) USBFS_Dp__LCD_EN) +/* Slew Rate Control */ +#define USBFS_Dp_SLW (* (reg8 *) USBFS_Dp__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define USBFS_Dp_PRTDSI__CAPS_SEL (* (reg8 *) USBFS_Dp__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define USBFS_Dp_PRTDSI__DBL_SYNC_IN (* (reg8 *) USBFS_Dp__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define USBFS_Dp_PRTDSI__OE_SEL0 (* (reg8 *) USBFS_Dp__PRTDSI__OE_SEL0) +#define USBFS_Dp_PRTDSI__OE_SEL1 (* (reg8 *) USBFS_Dp__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define USBFS_Dp_PRTDSI__OUT_SEL0 (* (reg8 *) USBFS_Dp__PRTDSI__OUT_SEL0) +#define USBFS_Dp_PRTDSI__OUT_SEL1 (* (reg8 *) USBFS_Dp__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define USBFS_Dp_PRTDSI__SYNC_OUT (* (reg8 *) USBFS_Dp__PRTDSI__SYNC_OUT) + + +#if defined(USBFS_Dp__INTSTAT) /* Interrupt Registers */ + + #define USBFS_Dp_INTSTAT (* (reg8 *) USBFS_Dp__INTSTAT) + #define USBFS_Dp_SNAP (* (reg8 *) USBFS_Dp__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_USBFS_Dp_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h new file mode 100755 index 00000000..702fb7ed --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h @@ -0,0 +1,32 @@ +/******************************************************************************* +* File Name: USBFS_Dp.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_USBFS_Dp_ALIASES_H) /* Pins USBFS_Dp_ALIASES_H */ +#define CY_PINS_USBFS_Dp_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define USBFS_Dp_0 USBFS_Dp__0__PC + +#endif /* End Pins USBFS_Dp_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_audio.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_audio.c new file mode 100755 index 00000000..e837975c --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_audio.c @@ -0,0 +1,318 @@ +/******************************************************************************* +* File Name: USBFS_audio.c +* Version 2.60 +* +* Description: +* USB AUDIO Class request handler. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS.h" + +#if defined(USBFS_ENABLE_AUDIO_CLASS) + +#include "USBFS_audio.h" +#include "USBFS_pvt.h" +#if defined(USBFS_ENABLE_MIDI_STREAMING) + #include "USBFS_midi.h" +#endif /* End USBFS_ENABLE_MIDI_STREAMING*/ + + +/*************************************** +* Custom Declarations +***************************************/ + +/* `#START CUSTOM_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +#if !defined(USER_SUPPLIED_AUDIO_HANDLER) + + +/*************************************** +* AUDIO Variables +***************************************/ + +#if defined(USBFS_ENABLE_AUDIO_STREAMING) + volatile uint8 USBFS_currentSampleFrequency[USBFS_MAX_EP][USBFS_SAMPLE_FREQ_LEN]; + volatile uint8 USBFS_frequencyChanged; + volatile uint8 USBFS_currentMute; + volatile uint8 USBFS_currentVolume[USBFS_VOLUME_LEN]; + volatile uint8 USBFS_minimumVolume[USBFS_VOLUME_LEN] = {USBFS_VOL_MIN_LSB, + USBFS_VOL_MIN_MSB}; + volatile uint8 USBFS_maximumVolume[USBFS_VOLUME_LEN] = {USBFS_VOL_MAX_LSB, + USBFS_VOL_MAX_MSB}; + volatile uint8 USBFS_resolutionVolume[USBFS_VOLUME_LEN] = {USBFS_VOL_RES_LSB, + USBFS_VOL_RES_MSB}; +#endif /* End USBFS_ENABLE_AUDIO_STREAMING */ + + +/******************************************************************************* +* Function Name: USBFS_DispatchAUDIOClassRqst +******************************************************************************** +* +* Summary: +* This routine dispatches class requests +* +* Parameters: +* None. +* +* Return: +* requestHandled +* +* Global variables: +* USBFS_currentSampleFrequency: Contains the current audio Sample +* Frequency. It is set by the Host using SET_CUR request to the endpoint. +* USBFS_frequencyChanged: This variable is used as a flag for the +* user code, to be aware that Host has been sent request for changing +* Sample Frequency. Sample frequency will be sent on the next OUT +* transaction. It is contains endpoint address when set. The following +* code is recommended for detecting new Sample Frequency in main code: +* if((USBFS_frequencyChanged != 0) && +* (USBFS_transferState == USBFS_TRANS_STATE_IDLE)) +* { +* USBFS_frequencyChanged = 0; +* } +* USBFS_transferState variable is checked to be sure that +* transfer completes. +* USBFS_currentMute: Contains mute configuration set by Host. +* USBFS_currentVolume: Contains volume level set by Host. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_DispatchAUDIOClassRqst(void) +{ + uint8 requestHandled = USBFS_FALSE; + + #if defined(USBFS_ENABLE_AUDIO_STREAMING) + uint8 epNumber; + epNumber = CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED; + #endif /* End USBFS_ENABLE_AUDIO_STREAMING */ + + if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H) + { + /* Control Read */ + if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \ + USBFS_RQST_RCPT_EP) + { + /* Endpoint */ + switch (CY_GET_REG8(USBFS_bRequest)) + { + case USBFS_GET_CUR: + #if defined(USBFS_ENABLE_AUDIO_STREAMING) + if(CY_GET_REG8(USBFS_wValueHi) == USBFS_SAMPLING_FREQ_CONTROL) + { + /* Endpoint Control Selector is Sampling Frequency */ + USBFS_currentTD.wCount = USBFS_SAMPLE_FREQ_LEN; + USBFS_currentTD.pData = USBFS_currentSampleFrequency[epNumber]; + requestHandled = USBFS_InitControlRead(); + } + #endif /* End USBFS_ENABLE_AUDIO_STREAMING */ + + /* `#START AUDIO_READ_REQUESTS` Place other request handler here */ + + /* `#END` */ + break; + default: + break; + } + } + else if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \ + USBFS_RQST_RCPT_IFC) + { + /* Interface or Entity ID */ + switch (CY_GET_REG8(USBFS_bRequest)) + { + case USBFS_GET_CUR: + #if defined(USBFS_ENABLE_AUDIO_STREAMING) + if(CY_GET_REG8(USBFS_wValueHi) == USBFS_MUTE_CONTROL) + { + /* `#START MUTE_CONTROL_GET_REQUEST` Place multi-channel handler here */ + + /* `#END` */ + + /* Entity ID Control Selector is MUTE */ + USBFS_currentTD.wCount = 1u; + USBFS_currentTD.pData = &USBFS_currentMute; + requestHandled = USBFS_InitControlRead(); + } + else if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL) + { + /* `#START VOLUME_CONTROL_GET_REQUEST` Place multi-channel handler here */ + + /* `#END` */ + + /* Entity ID Control Selector is VOLUME, */ + USBFS_currentTD.wCount = USBFS_VOLUME_LEN; + USBFS_currentTD.pData = USBFS_currentVolume; + requestHandled = USBFS_InitControlRead(); + } + else + { + /* `#START OTHER_GET_CUR_REQUESTS` Place other request handler here */ + + /* `#END` */ + } + break; + case USBFS_GET_MIN: /* GET_MIN */ + if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL) + { + /* Entity ID Control Selector is VOLUME, */ + USBFS_currentTD.wCount = USBFS_VOLUME_LEN; + USBFS_currentTD.pData = &USBFS_minimumVolume[0]; + requestHandled = USBFS_InitControlRead(); + } + break; + case USBFS_GET_MAX: /* GET_MAX */ + if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL) + { + /* Entity ID Control Selector is VOLUME, */ + USBFS_currentTD.wCount = USBFS_VOLUME_LEN; + USBFS_currentTD.pData = &USBFS_maximumVolume[0]; + requestHandled = USBFS_InitControlRead(); + } + break; + case USBFS_GET_RES: /* GET_RES */ + if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL) + { + /* Entity ID Control Selector is VOLUME, */ + USBFS_currentTD.wCount = USBFS_VOLUME_LEN; + USBFS_currentTD.pData = &USBFS_resolutionVolume[0]; + requestHandled = USBFS_InitControlRead(); + } + break; + /* The contents of the status message is reserved for future use. + * For the time being, a null packet should be returned in the data stage of the + * control transfer, and the received null packet should be ACKed. + */ + case USBFS_GET_STAT: + USBFS_currentTD.wCount = 0u; + requestHandled = USBFS_InitControlWrite(); + + #endif /* End USBFS_ENABLE_AUDIO_STREAMING */ + + /* `#START AUDIO_WRITE_REQUESTS` Place other request handler here */ + + /* `#END` */ + break; + default: + break; + } + } + else + { /* USBFS_RQST_RCPT_OTHER */ + } + } + else if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == \ + USBFS_RQST_DIR_H2D) + { + /* Control Write */ + if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \ + USBFS_RQST_RCPT_EP) + { + /* Endpoint */ + switch (CY_GET_REG8(USBFS_bRequest)) + { + case USBFS_SET_CUR: + #if defined(USBFS_ENABLE_AUDIO_STREAMING) + if(CY_GET_REG8(USBFS_wValueHi) == USBFS_SAMPLING_FREQ_CONTROL) + { + /* Endpoint Control Selector is Sampling Frequency */ + USBFS_currentTD.wCount = USBFS_SAMPLE_FREQ_LEN; + USBFS_currentTD.pData = USBFS_currentSampleFrequency[epNumber]; + requestHandled = USBFS_InitControlWrite(); + USBFS_frequencyChanged = epNumber; + } + #endif /* End USBFS_ENABLE_AUDIO_STREAMING */ + + /* `#START AUDIO_SAMPLING_FREQ_REQUESTS` Place other request handler here */ + + /* `#END` */ + break; + default: + break; + } + } + else if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \ + USBFS_RQST_RCPT_IFC) + { + /* Interface or Entity ID */ + switch (CY_GET_REG8(USBFS_bRequest)) + { + case USBFS_SET_CUR: + #if defined(USBFS_ENABLE_AUDIO_STREAMING) + if(CY_GET_REG8(USBFS_wValueHi) == USBFS_MUTE_CONTROL) + { + /* `#START MUTE_SET_REQUEST` Place multi-channel handler here */ + + /* `#END` */ + + /* Entity ID Control Selector is MUTE */ + USBFS_currentTD.wCount = 1u; + USBFS_currentTD.pData = &USBFS_currentMute; + requestHandled = USBFS_InitControlWrite(); + } + else if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL) + { + /* `#START VOLUME_CONTROL_SET_REQUEST` Place multi-channel handler here */ + + /* `#END` */ + + /* Entity ID Control Selector is VOLUME */ + USBFS_currentTD.wCount = USBFS_VOLUME_LEN; + USBFS_currentTD.pData = USBFS_currentVolume; + requestHandled = USBFS_InitControlWrite(); + } + else + { + /* `#START OTHER_SET_CUR_REQUESTS` Place other request handler here */ + + /* `#END` */ + } + #endif /* End USBFS_ENABLE_AUDIO_STREAMING */ + + /* `#START AUDIO_CONTROL_SEL_REQUESTS` Place other request handler here */ + + /* `#END` */ + break; + default: + break; + } + } + else + { /* USBFS_RQST_RCPT_OTHER */ + } + } + else + { /* requestHandled is initialized as FALSE by default */ + } + + return(requestHandled); +} + + +#endif /* USER_SUPPLIED_AUDIO_HANDLER */ + + +/******************************************************************************* +* Additional user functions supporting AUDIO Requests +********************************************************************************/ + +/* `#START AUDIO_FUNCTIONS` Place any additional functions here */ + +/* `#END` */ + +#endif /* End USBFS_ENABLE_AUDIO_CLASS*/ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_audio.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_audio.h new file mode 100755 index 00000000..0e0feb20 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_audio.h @@ -0,0 +1,95 @@ +/******************************************************************************* +* File Name: USBFS_audio.h +* Version 2.60 +* +* Description: +* Header File for the USFS component. Contains prototypes and constant values. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_USBFS_USBFS_audio_H) +#define CY_USBFS_USBFS_audio_H + +#include "cytypes.h" + + +/*************************************** +* Custom Declarations +***************************************/ + +/* `#START CUSTOM_CONSTANTS` Place your declaration here */ + +/* `#END` */ + + +/*************************************** +* Constants for USBFS_audio API. +***************************************/ + +/* Audio Class-Specific Request Codes (AUDIO Table A-9) */ +#define USBFS_REQUEST_CODE_UNDEFINED (0x00u) +#define USBFS_SET_CUR (0x01u) +#define USBFS_GET_CUR (0x81u) +#define USBFS_SET_MIN (0x02u) +#define USBFS_GET_MIN (0x82u) +#define USBFS_SET_MAX (0x03u) +#define USBFS_GET_MAX (0x83u) +#define USBFS_SET_RES (0x04u) +#define USBFS_GET_RES (0x84u) +#define USBFS_SET_MEM (0x05u) +#define USBFS_GET_MEM (0x85u) +#define USBFS_GET_STAT (0xFFu) + +/* Endpoint Control Selectors (AUDIO Table A-19) */ +#define USBFS_EP_CONTROL_UNDEFINED (0x00u) +#define USBFS_SAMPLING_FREQ_CONTROL (0x01u) +#define USBFS_PITCH_CONTROL (0x02u) + +/* Feature Unit Control Selectors (AUDIO Table A-11) */ +#define USBFS_FU_CONTROL_UNDEFINED (0x00u) +#define USBFS_MUTE_CONTROL (0x01u) +#define USBFS_VOLUME_CONTROL (0x02u) +#define USBFS_BASS_CONTROL (0x03u) +#define USBFS_MID_CONTROL (0x04u) +#define USBFS_TREBLE_CONTROL (0x05u) +#define USBFS_GRAPHIC_EQUALIZER_CONTROL (0x06u) +#define USBFS_AUTOMATIC_GAIN_CONTROL (0x07u) +#define USBFS_DELAY_CONTROL (0x08u) +#define USBFS_BASS_BOOST_CONTROL (0x09u) +#define USBFS_LOUDNESS_CONTROL (0x0Au) + +#define USBFS_SAMPLE_FREQ_LEN (3u) +#define USBFS_VOLUME_LEN (2u) + +#if !defined(USER_SUPPLIED_DEFAULT_VOLUME_VALUE) + #define USBFS_VOL_MIN_MSB (0x80u) + #define USBFS_VOL_MIN_LSB (0x01u) + #define USBFS_VOL_MAX_MSB (0x7Fu) + #define USBFS_VOL_MAX_LSB (0xFFu) + #define USBFS_VOL_RES_MSB (0x00u) + #define USBFS_VOL_RES_LSB (0x01u) +#endif /* USER_SUPPLIED_DEFAULT_VOLUME_VALUE */ + + +/*************************************** +* External data references +***************************************/ + +extern volatile uint8 USBFS_currentSampleFrequency[USBFS_MAX_EP] + [USBFS_SAMPLE_FREQ_LEN]; +extern volatile uint8 USBFS_frequencyChanged; +extern volatile uint8 USBFS_currentMute; +extern volatile uint8 USBFS_currentVolume[USBFS_VOLUME_LEN]; +extern volatile uint8 USBFS_minimumVolume[USBFS_VOLUME_LEN]; +extern volatile uint8 USBFS_maximumVolume[USBFS_VOLUME_LEN]; +extern volatile uint8 USBFS_resolutionVolume[USBFS_VOLUME_LEN]; + +#endif /* End CY_USBFS_USBFS_audio_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_boot.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_boot.c new file mode 100755 index 00000000..3cbb2f9d --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_boot.c @@ -0,0 +1,262 @@ +/******************************************************************************* +* File Name: USBFS_boot.c +* Version 2.60 +* +* Description: +* Boot loader API for USBFS Component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS.h" + +#if defined(CYDEV_BOOTLOADER_IO_COMP) && ((CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) || \ + (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface)) + + +/*************************************** +* Bootloader defines +***************************************/ + +#define USBFS_CyBtLdrStarttimer(X, T) {USBFS_universalTime = T * 10; X = 0u;} +#define USBFS_CyBtLdrChecktimer(X) ((X++ < USBFS_universalTime) ? 1u : 0u) + +#define USBFS_BTLDR_OUT_EP (0x01u) +#define USBFS_BTLDR_IN_EP (0x02u) + + +/*************************************** +* Bootloader Variables +***************************************/ + +static uint16 USBFS_universalTime; +static uint8 USBFS_started = 0u; + + +/******************************************************************************* +* Function Name: USBFS_CyBtldrCommStart +******************************************************************************** +* +* Summary: +* Starts the component and enables the interrupt. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Side Effects: +* This function starts the USB with 3V or 5V operation. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_CyBtldrCommStart(void) +{ + CyGlobalIntEnable; /* Enable Global Interrupts */ + + /*Start USBFS Operation/device 0 and with 5V or 3V operation depend on Voltage Configuration in DWR */ + USBFS_Start(0u, USBFS_DWR_VDDD_OPERATION); + + /* USB component started, the correct enumeration will be checked in first Read operation */ + USBFS_started = 1u; + +} + + +/******************************************************************************* +* Function Name: USBFS_CyBtldrCommStop. +******************************************************************************** +* +* Summary: +* Disable the component and disable the interrupt. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void USBFS_CyBtldrCommStop(void) +{ + USBFS_Stop(); +} + + +/******************************************************************************* +* Function Name: USBFS_CyBtldrCommReset. +******************************************************************************** +* +* Summary: +* Resets the receive and transmit communication Buffers. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_CyBtldrCommReset(void) +{ + USBFS_EnableOutEP(USBFS_BTLDR_OUT_EP); /* Enable the OUT endpoint */ +} + + +/******************************************************************************* +* Function Name: USBFS_CyBtldrCommWrite. +******************************************************************************** +* +* Summary: +* Allows the caller to write data to the boot loader host. The function will +* handle polling to allow a block of data to be completely sent to the host +* device. +* +* Parameters: +* pData: A pointer to the block of data to send to the device +* size: The number of bytes to write. +* count: Pointer to an unsigned short variable to write the number of +* bytes actually written. +* timeOut: Number of units to wait before returning because of a timeout. +* +* Return: +* Returns the value that best describes the problem. +* +* Reentrant: +* No. +* +*******************************************************************************/ +cystatus USBFS_CyBtldrCommWrite(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL + +{ + uint16 time; + cystatus status; + + /* Enable IN transfer */ + USBFS_LoadInEP(USBFS_BTLDR_IN_EP, pData, USBFS_BTLDR_SIZEOF_READ_BUFFER); + + /* Start a timer to wait on. */ + USBFS_CyBtLdrStarttimer(time, timeOut); + + /* Wait for the master to read it. */ + while((USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL) && \ + USBFS_CyBtLdrChecktimer(time)) + { + CyDelay(1u); /* 1ms delay */ + } + + if (USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL) + { + status = CYRET_TIMEOUT; + } + else + { + *count = size; + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: USBFS_CyBtldrCommRead. +******************************************************************************** +* +* Summary: +* Allows the caller to read data from the boot loader host. The function will +* handle polling to allow a block of data to be completely received from the +* host device. +* +* Parameters: +* pData: A pointer to the area to store the block of data received +* from the device. +* size: The number of bytes to read. +* count: Pointer to an unsigned short variable to write the number +* of bytes actually read. +* timeOut: Number of units to wait before returning because of a timeOut. +* Timeout is measured in 10s of ms. +* +* Return: +* Returns the value that best describes the problem. +* +* Reentrant: +* No. +* +*******************************************************************************/ +cystatus USBFS_CyBtldrCommRead(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL + +{ + cystatus status; + uint16 time; + + if(size > USBFS_BTLDR_SIZEOF_WRITE_BUFFER) + { + size = USBFS_BTLDR_SIZEOF_WRITE_BUFFER; + } + /* Start a timer to wait on. */ + USBFS_CyBtLdrStarttimer(time, timeOut); + + /* Wait on enumeration in first time */ + if(USBFS_started) + { + /* Wait for Device to enumerate */ + while(!USBFS_GetConfiguration() && USBFS_CyBtLdrChecktimer(time)) + { + CyDelay(1u); /* 1ms delay */ + } + /* Enable first OUT, if enumeration complete */ + if(USBFS_GetConfiguration()) + { + USBFS_IsConfigurationChanged(); /* Clear configuration changes state status */ + USBFS_CyBtldrCommReset(); + USBFS_started = 0u; + } + } + else /* Check for configuration changes, has been done by Host */ + { + if(USBFS_IsConfigurationChanged() != 0u) /* Host could send double SET_INTERFACE request or RESET */ + { + if(USBFS_GetConfiguration() != 0u) /* Init OUT endpoints when device reconfigured */ + { + USBFS_CyBtldrCommReset(); + } + } + } + /* Wait on next packet */ + while((USBFS_GetEPState(USBFS_BTLDR_OUT_EP) != USBFS_OUT_BUFFER_FULL) && \ + USBFS_CyBtLdrChecktimer(time)) + { + CyDelay(1u); /* 1ms delay */ + } + + /* OUT EP has completed */ + if (USBFS_GetEPState(USBFS_BTLDR_OUT_EP) == USBFS_OUT_BUFFER_FULL) + { + *count = USBFS_ReadOutEP(USBFS_BTLDR_OUT_EP, pData, size); + status = CYRET_SUCCESS; + } + else + { + *count = 0u; + status = CYRET_TIMEOUT; + } + return(status); +} + +#endif /* End CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_cdc.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_cdc.c new file mode 100755 index 00000000..7d65d6b7 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_cdc.c @@ -0,0 +1,706 @@ +/******************************************************************************* +* File Name: USBFS_cdc.c +* Version 2.60 +* +* Description: +* USB HID Class request handler. +* +* Note: +* +******************************************************************************** +* Copyright 2012-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS.h" + +#if defined(USBFS_ENABLE_CDC_CLASS) + +#include "USBFS_cdc.h" +#include "USBFS_pvt.h" + + +/*************************************** +* CDC Variables +***************************************/ + +volatile uint8 USBFS_lineCoding[USBFS_LINE_CODING_SIZE]; +volatile uint8 USBFS_lineChanged; +volatile uint16 USBFS_lineControlBitmap; +volatile uint8 USBFS_cdc_data_in_ep; +volatile uint8 USBFS_cdc_data_out_ep; + + +/*************************************** +* Static Function Prototypes +***************************************/ +static uint16 USBFS_StrLen(const char8 string[]) ; + + +/*************************************** +* Custom Declarations +***************************************/ + +/* `#START CDC_CUSTOM_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +/******************************************************************************* +* Function Name: USBFS_DispatchCDCClassRqst +******************************************************************************** +* +* Summary: +* This routine dispatches CDC class requests. +* +* Parameters: +* None. +* +* Return: +* requestHandled +* +* Global variables: +* USBFS_lineCoding: Contains the current line coding structure. +* It is set by the Host using SET_LINE_CODING request and returned to the +* user code by the USBFS_GetDTERate(), USBFS_GetCharFormat(), +* USBFS_GetParityType(), USBFS_GetDataBits() APIs. +* USBFS_lineControlBitmap: Contains the current control signal +* bitmap. It is set by the Host using SET_CONTROL_LINE request and returned +* to the user code by the USBFS_GetLineControl() API. +* USBFS_lineChanged: This variable is used as a flag for the +* USBFS_IsLineChanged() API, to be aware that Host has been sent request +* for changing Line Coding or Control Bitmap. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_DispatchCDCClassRqst(void) +{ + uint8 requestHandled = USBFS_FALSE; + + if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H) + { /* Control Read */ + switch (CY_GET_REG8(USBFS_bRequest)) + { + case USBFS_CDC_GET_LINE_CODING: + USBFS_currentTD.count = USBFS_LINE_CODING_SIZE; + USBFS_currentTD.pData = USBFS_lineCoding; + requestHandled = USBFS_InitControlRead(); + break; + + /* `#START CDC_READ_REQUESTS` Place other request handler here */ + + /* `#END` */ + + default: /* requestHandled is initialized as FALSE by default */ + break; + } + } + else if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == \ + USBFS_RQST_DIR_H2D) + { /* Control Write */ + switch (CY_GET_REG8(USBFS_bRequest)) + { + case USBFS_CDC_SET_LINE_CODING: + USBFS_currentTD.count = USBFS_LINE_CODING_SIZE; + USBFS_currentTD.pData = USBFS_lineCoding; + USBFS_lineChanged |= USBFS_LINE_CODING_CHANGED; + requestHandled = USBFS_InitControlWrite(); + break; + + case USBFS_CDC_SET_CONTROL_LINE_STATE: + USBFS_lineControlBitmap = CY_GET_REG8(USBFS_wValueLo); + USBFS_lineChanged |= USBFS_LINE_CONTROL_CHANGED; + requestHandled = USBFS_InitNoDataControlTransfer(); + break; + + /* `#START CDC_WRITE_REQUESTS` Place other request handler here */ + + /* `#END` */ + + default: /* requestHandled is initialized as FALSE by default */ + break; + } + } + else + { /* requestHandled is initialized as FALSE by default */ + } + + return(requestHandled); +} + + +/*************************************** +* Optional CDC APIs +***************************************/ +#if (USBFS_ENABLE_CDC_CLASS_API != 0u) + + + /******************************************************************************* + * Function Name: USBFS_CDC_Init + ******************************************************************************** + * + * Summary: + * This function initialize the CDC interface to be ready for the receive data + * from the PC. + * + * Parameters: + * None. + * + * Return: + * None. + * + * Global variables: + * USBFS_lineChanged: Initialized to zero. + * USBFS_cdc_data_out_ep: Used as an OUT endpoint number. + * + * Reentrant: + * No. + * + *******************************************************************************/ + void USBFS_CDC_Init(void) + { + USBFS_lineChanged = 0u; + USBFS_EnableOutEP(USBFS_cdc_data_out_ep); + } + + + /******************************************************************************* + * Function Name: USBFS_PutData + ******************************************************************************** + * + * Summary: + * Sends a specified number of bytes from the location specified by a + * pointer to the PC. + * + * Parameters: + * pData: pointer to the buffer containing data to be sent. + * length: Specifies the number of bytes to send from the pData + * buffer. Maximum length will be limited by the maximum packet + * size for the endpoint. + * + * Return: + * None. + * + * Global variables: + * USBFS_cdc_data_in_ep: CDC IN endpoint number used for sending + * data. + * + * Reentrant: + * No. + * + *******************************************************************************/ + void USBFS_PutData(const uint8* pData, uint16 length) + { + /* Limits length to maximum packet size for the EP */ + if(length > USBFS_EP[USBFS_cdc_data_in_ep].bufferSize) + { + /* Caution: Data will be lost if length is greater than Max Packet Length */ + length = USBFS_EP[USBFS_cdc_data_in_ep].bufferSize; + /* Halt CPU in debug mode */ + CYASSERT(0u != 0u); + } + USBFS_LoadInEP(USBFS_cdc_data_in_ep, pData, length); + } + + + /******************************************************************************* + * Function Name: USBFS_StrLen + ******************************************************************************** + * + * Summary: + * Calculates length of a null terminated string. + * + * Parameters: + * string: pointer to the string. + * + * Return: + * Length of the string + * + *******************************************************************************/ + static uint16 USBFS_StrLen(const char8 string[]) + { + uint16 len = 0u; + + while (string[len] != (char8)0) + { + len++; + } + + return (len); + } + + + /******************************************************************************* + * Function Name: USBFS_PutString + ******************************************************************************** + * + * Summary: + * Sends a null terminated string to the PC. + * + * Parameters: + * string: pointer to the string to be sent to the PC + * + * Return: + * None. + * + * Global variables: + * USBFS_cdc_data_in_ep: CDC IN endpoint number used for sending + * data. + * + * Reentrant: + * No. + * + * Theory: + * This function will block if there is not enough memory to place the whole + * string, it will block until the entire string has been written to the + * transmit buffer. + * + *******************************************************************************/ + void USBFS_PutString(const char8 string[]) + { + uint16 str_length; + uint16 send_length; + uint16 buf_index = 0u; + + /* Get length of the null terminated string */ + str_length = USBFS_StrLen(string); + do + { + /* Limits length to maximum packet size for the EP */ + send_length = (str_length > USBFS_EP[USBFS_cdc_data_in_ep].bufferSize) ? + USBFS_EP[USBFS_cdc_data_in_ep].bufferSize : str_length; + /* Enable IN transfer */ + USBFS_LoadInEP(USBFS_cdc_data_in_ep, (const uint8 *)&string[buf_index], send_length); + str_length -= send_length; + + /* If more data are present to send */ + if(str_length > 0u) + { + buf_index += send_length; + /* Wait for the Host to read it. */ + while(USBFS_EP[USBFS_cdc_data_in_ep].apiEpState == + USBFS_IN_BUFFER_FULL) + { + ; + } + } + }while(str_length > 0u); + } + + + /******************************************************************************* + * Function Name: USBFS_PutChar + ******************************************************************************** + * + * Summary: + * Writes a single character to the PC. + * + * Parameters: + * txDataByte: Character to be sent to the PC. + * + * Return: + * None. + * + * Global variables: + * USBFS_cdc_data_in_ep: CDC IN endpoint number used for sending + * data. + * + * Reentrant: + * No. + * + *******************************************************************************/ + void USBFS_PutChar(char8 txDataByte) + { + uint8 dataByte; + dataByte = (uint8)txDataByte; + + USBFS_LoadInEP(USBFS_cdc_data_in_ep, &dataByte, 1u); + } + + + /******************************************************************************* + * Function Name: USBFS_PutCRLF + ******************************************************************************** + * + * Summary: + * Sends a carriage return (0x0D) and line feed (0x0A) to the PC + * + * Parameters: + * None. + * + * Return: + * None. + * + * Global variables: + * USBFS_cdc_data_in_ep: CDC IN endpoint number used for sending + * data. + * + * Reentrant: + * No. + * + *******************************************************************************/ + void USBFS_PutCRLF(void) + { + const uint8 CYCODE txData[] = {0x0Du, 0x0Au}; + + USBFS_LoadInEP(USBFS_cdc_data_in_ep, (const uint8 *)txData, 2u); + } + + + /******************************************************************************* + * Function Name: USBFS_GetCount + ******************************************************************************** + * + * Summary: + * This function returns the number of bytes that were received from the PC. + * + * Parameters: + * None. + * + * Return: + * Returns the number of received bytes. + * + * Global variables: + * USBFS_cdc_data_out_ep: CDC OUT endpoint number used. + * + *******************************************************************************/ + uint16 USBFS_GetCount(void) + { + uint16 bytesCount = 0u; + + if (USBFS_EP[USBFS_cdc_data_out_ep].apiEpState == USBFS_OUT_BUFFER_FULL) + { + bytesCount = USBFS_GetEPCount(USBFS_cdc_data_out_ep); + } + + return(bytesCount); + } + + + /******************************************************************************* + * Function Name: USBFS_DataIsReady + ******************************************************************************** + * + * Summary: + * Returns a nonzero value if the component received data or received + * zero-length packet. The GetAll() or GetData() API should be called to read + * data from the buffer and re-init OUT endpoint even when zero-length packet + * received. + * + * Parameters: + * None. + * + * Return: + * If the OUT packet received this function returns a nonzero value. + * Otherwise zero is returned. + * + * Global variables: + * USBFS_cdc_data_out_ep: CDC OUT endpoint number used. + * + *******************************************************************************/ + uint8 USBFS_DataIsReady(void) + { + return(USBFS_EP[USBFS_cdc_data_out_ep].apiEpState); + } + + + /******************************************************************************* + * Function Name: USBFS_CDCIsReady + ******************************************************************************** + * + * Summary: + * Returns a nonzero value if the component is ready to send more data to the + * PC. Otherwise returns zero. Should be called before sending new data to + * ensure the previous data has finished sending.This function returns the + * number of bytes that were received from the PC. + * + * Parameters: + * None. + * + * Return: + * If the buffer can accept new data then this function returns a nonzero value. + * Otherwise zero is returned. + * + * Global variables: + * USBFS_cdc_data_in_ep: CDC IN endpoint number used. + * + *******************************************************************************/ + uint8 USBFS_CDCIsReady(void) + { + return(USBFS_EP[USBFS_cdc_data_in_ep].apiEpState); + } + + + /******************************************************************************* + * Function Name: USBFS_GetData + ******************************************************************************** + * + * Summary: + * Gets a specified number of bytes from the input buffer and places it in a + * data array specified by the passed pointer. + * USBFS_DataIsReady() API should be called before, to be sure + * that data is received from the Host. + * + * Parameters: + * pData: Pointer to the data array where data will be placed. + * Length: Number of bytes to read into the data array from the RX buffer. + * Maximum length is limited by the the number of received bytes. + * + * Return: + * Number of bytes received. + * + * Global variables: + * USBFS_cdc_data_out_ep: CDC OUT endpoint number used. + * + * Reentrant: + * No. + * + *******************************************************************************/ + uint16 USBFS_GetData(uint8* pData, uint16 length) + { + return(USBFS_ReadOutEP(USBFS_cdc_data_out_ep, pData, length)); + } + + + /******************************************************************************* + * Function Name: USBFS_GetAll + ******************************************************************************** + * + * Summary: + * Gets all bytes of received data from the input buffer and places it into a + * specified data array. USBFS_DataIsReady() API should be called + * before, to be sure that data is received from the Host. + * + * Parameters: + * pData: Pointer to the data array where data will be placed. + * + * Return: + * Number of bytes received. + * + * Global variables: + * USBFS_cdc_data_out_ep: CDC OUT endpoint number used. + * USBFS_EP[].bufferSize: EP max packet size is used as a length + * to read all data from the EP buffer. + * + * Reentrant: + * No. + * + *******************************************************************************/ + uint16 USBFS_GetAll(uint8* pData) + { + return (USBFS_ReadOutEP(USBFS_cdc_data_out_ep, pData, + USBFS_EP[USBFS_cdc_data_out_ep].bufferSize)); + } + + + /******************************************************************************* + * Function Name: USBFS_GetChar + ******************************************************************************** + * + * Summary: + * Reads one byte of received data from the buffer. + * + * Parameters: + * None. + * + * Return: + * Received one character. + * + * Global variables: + * USBFS_cdc_data_out_ep: CDC OUT endpoint number used. + * + * Reentrant: + * No. + * + *******************************************************************************/ + uint8 USBFS_GetChar(void) + { + uint8 rxData; + + (void) USBFS_ReadOutEP(USBFS_cdc_data_out_ep, &rxData, 1u); + + return(rxData); + } + + /******************************************************************************* + * Function Name: USBFS_IsLineChanged + ******************************************************************************** + * + * Summary: + * This function returns clear on read status of the line. + * + * Parameters: + * None. + * + * Return: + * If SET_LINE_CODING or CDC_SET_CONTROL_LINE_STATE request received then not + * zero value returned. Otherwise zero is returned. + * + * Global variables: + * USBFS_transferState - it is checked to be sure then OUT data + * phase has been complete, and data written to the lineCoding or Control + * Bitmap buffer. + * USBFS_lineChanged: used as a flag to be aware that Host has been + * sent request for changing Line Coding or Control Bitmap. + * + *******************************************************************************/ + uint8 USBFS_IsLineChanged(void) + { + uint8 state = 0u; + + /* transferState is checked to be sure then OUT data phase has been complete */ + if(USBFS_transferState == USBFS_TRANS_STATE_IDLE) + { + if(USBFS_lineChanged != 0u) + { + state = USBFS_lineChanged; + USBFS_lineChanged = 0u; + } + } + + return(state); + } + + + /******************************************************************************* + * Function Name: USBFS_GetDTERate + ******************************************************************************** + * + * Summary: + * Returns the data terminal rate set for this port in bits per second. + * + * Parameters: + * None. + * + * Return: + * Returns a uint32 value of the data rate in bits per second. + * + * Global variables: + * USBFS_lineCoding: First four bytes converted to uint32 + * depend on compiler, and returned as a data rate. + * + *******************************************************************************/ + uint32 USBFS_GetDTERate(void) + { + uint32 rate; + + rate = USBFS_lineCoding[USBFS_LINE_CODING_RATE + 3u]; + rate = (rate << 8u) | USBFS_lineCoding[USBFS_LINE_CODING_RATE + 2u]; + rate = (rate << 8u) | USBFS_lineCoding[USBFS_LINE_CODING_RATE + 1u]; + rate = (rate << 8u) | USBFS_lineCoding[USBFS_LINE_CODING_RATE]; + + return(rate); + } + + + /******************************************************************************* + * Function Name: USBFS_GetCharFormat + ******************************************************************************** + * + * Summary: + * Returns the number of stop bits. + * + * Parameters: + * None. + * + * Return: + * Returns the number of stop bits. + * + * Global variables: + * USBFS_lineCoding: used to get a parameter. + * + *******************************************************************************/ + uint8 USBFS_GetCharFormat(void) + { + return(USBFS_lineCoding[USBFS_LINE_CODING_STOP_BITS]); + } + + + /******************************************************************************* + * Function Name: USBFS_GetParityType + ******************************************************************************** + * + * Summary: + * Returns the parity type for the CDC port. + * + * Parameters: + * None. + * + * Return: + * Returns the parity type. + * + * Global variables: + * USBFS_lineCoding: used to get a parameter. + * + *******************************************************************************/ + uint8 USBFS_GetParityType(void) + { + return(USBFS_lineCoding[USBFS_LINE_CODING_PARITY]); + } + + + /******************************************************************************* + * Function Name: USBFS_GetDataBits + ******************************************************************************** + * + * Summary: + * Returns the number of data bits for the CDC port. + * + * Parameters: + * None. + * + * Return: + * Returns the number of data bits. + * The number of data bits can be 5, 6, 7, 8 or 16. + * + * Global variables: + * USBFS_lineCoding: used to get a parameter. + * + *******************************************************************************/ + uint8 USBFS_GetDataBits(void) + { + return(USBFS_lineCoding[USBFS_LINE_CODING_DATA_BITS]); + } + + + /******************************************************************************* + * Function Name: USBFS_GetLineControl + ******************************************************************************** + * + * Summary: + * Returns Line control bitmap. + * + * Parameters: + * None. + * + * Return: + * Returns Line control bitmap. + * + * Global variables: + * USBFS_lineControlBitmap: used to get a parameter. + * + *******************************************************************************/ + uint16 USBFS_GetLineControl(void) + { + return(USBFS_lineControlBitmap); + } + +#endif /* End USBFS_ENABLE_CDC_CLASS_API*/ + + +/******************************************************************************* +* Additional user functions supporting CDC Requests +********************************************************************************/ + +/* `#START CDC_FUNCTIONS` Place any additional functions here */ + +/* `#END` */ + +#endif /* End USBFS_ENABLE_CDC_CLASS*/ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_cdc.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_cdc.h new file mode 100755 index 00000000..ca79f63e --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_cdc.h @@ -0,0 +1,92 @@ +/******************************************************************************* +* File Name: USBFS_cdc.h +* Version 2.60 +* +* Description: +* Header File for the USFS component. +* Contains CDC class prototypes and constant values. +* +******************************************************************************** +* Copyright 2012-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_USBFS_USBFS_cdc_H) +#define CY_USBFS_USBFS_cdc_H + +#include "cytypes.h" + + +/*************************************** +* Prototypes of the USBFS_cdc API. +***************************************/ + +#if (USBFS_ENABLE_CDC_CLASS_API != 0u) + void USBFS_CDC_Init(void) ; + void USBFS_PutData(const uint8* pData, uint16 length) ; + void USBFS_PutString(const char8 string[]) ; + void USBFS_PutChar(char8 txDataByte) ; + void USBFS_PutCRLF(void) ; + uint16 USBFS_GetCount(void) ; + uint8 USBFS_CDCIsReady(void) ; + uint8 USBFS_DataIsReady(void) ; + uint16 USBFS_GetData(uint8* pData, uint16 length) ; + uint16 USBFS_GetAll(uint8* pData) ; + uint8 USBFS_GetChar(void) ; + uint8 USBFS_IsLineChanged(void) ; + uint32 USBFS_GetDTERate(void) ; + uint8 USBFS_GetCharFormat(void) ; + uint8 USBFS_GetParityType(void) ; + uint8 USBFS_GetDataBits(void) ; + uint16 USBFS_GetLineControl(void) ; +#endif /* End USBFS_ENABLE_CDC_CLASS_API*/ + + +/*************************************** +* Constants for USBFS_cdc API. +***************************************/ + +/* CDC Class-Specific Request Codes (CDC ver 1.2 Table 19) */ +#define USBFS_CDC_SET_LINE_CODING (0x20u) +#define USBFS_CDC_GET_LINE_CODING (0x21u) +#define USBFS_CDC_SET_CONTROL_LINE_STATE (0x22u) + +#define USBFS_LINE_CODING_CHANGED (0x01u) +#define USBFS_LINE_CONTROL_CHANGED (0x02u) + +#define USBFS_1_STOPBIT (0x00u) +#define USBFS_1_5_STOPBITS (0x01u) +#define USBFS_2_STOPBITS (0x02u) + +#define USBFS_PARITY_NONE (0x00u) +#define USBFS_PARITY_ODD (0x01u) +#define USBFS_PARITY_EVEN (0x02u) +#define USBFS_PARITY_MARK (0x03u) +#define USBFS_PARITY_SPACE (0x04u) + +#define USBFS_LINE_CODING_SIZE (0x07u) +#define USBFS_LINE_CODING_RATE (0x00u) +#define USBFS_LINE_CODING_STOP_BITS (0x04u) +#define USBFS_LINE_CODING_PARITY (0x05u) +#define USBFS_LINE_CODING_DATA_BITS (0x06u) + +#define USBFS_LINE_CONTROL_DTR (0x01u) +#define USBFS_LINE_CONTROL_RTS (0x02u) + + +/*************************************** +* External data references +***************************************/ + +extern volatile uint8 USBFS_lineCoding[USBFS_LINE_CODING_SIZE]; +extern volatile uint8 USBFS_lineChanged; +extern volatile uint16 USBFS_lineControlBitmap; +extern volatile uint8 USBFS_cdc_data_in_ep; +extern volatile uint8 USBFS_cdc_data_out_ep; + +#endif /* End CY_USBFS_USBFS_cdc_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf new file mode 100755 index 00000000..8a8f5bea --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf @@ -0,0 +1,122 @@ +;****************************************************************************** +; File Name: USBFS_cdc.inf +; Version 2.60 +; +; Description: +; Windows USB CDC setup file for USBUART Device. +; +;****************************************************************************** +; Copyright 2007-2013, Cypress Semiconductor Corporation. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;****************************************************************************** + +[Version] +Signature="$Windows NT$" +Class=Ports +ClassGuid={4D36E978-E325-11CE-BFC1-08002BE10318} +Provider=%PROVIDER% +LayoutFile=layout.inf +DriverVer=03/05/2007,2.0.0000.0 + +[Manufacturer] +%MFGNAME%=DeviceList, NTx86, NTia64, NTamd64 + +[DestinationDirs] +DefaultDestDir=12 + +[SourceDisksFiles] + +[SourceDisksNames] + +[DeviceList.NTx86] +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232 + +[DeviceList.NTia64] +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232 + +[DeviceList.NTamd64] +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232 + + +;------------------------------------------------------------------------------ +; 32 bit section for Windows 2000/2003/XP/Vista +;------------------------------------------------------------------------------ + +[DriverInstall.NTx86] +include=mdmcpq.inf +CopyFiles=DriverCopyFiles +AddReg=DriverInstall.NTx86.AddReg + +[DriverCopyFiles] +usbser.sys,,,0x20 + +[DriverInstall.NTx86.AddReg] +HKR,,DevLoader,,*ntkern +HKR,,NTMPDriver,,usbser.sys +HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" + +[DriverInstall.NTx86.Services] +AddService=usbser, 0x00000002, DriverService + +;------------------------------------------------------------------------------ +; 64 bit section for Intel Itanium based systems +;------------------------------------------------------------------------------ + +[DriverInstall.NTia64] +include=mdmcpq.inf +CopyFiles=DriverCopyFiles +AddReg=DriverInstall.NTia64.AddReg + +[DriverCopyFiles] +usbser.sys,,,0x20 + +[DriverInstall.NTia64.AddReg] +HKR,,DevLoader,,*ntkern +HKR,,NTMPDriver,,usbser.sys +HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" + +[DriverInstall.NTia64.Services] +AddService=usbser, 0x00000002, DriverService + +;------------------------------------------------------------------------------ +; 64 bit section for AMD64 and Intel EM64T based systems +;------------------------------------------------------------------------------ + +[DriverInstall.NTamd64] +include=mdmcpq.inf +CopyFiles=DriverCopyFiles +AddReg=DriverInstall.NTamd64.AddReg + +[DriverCopyFiles] +usbser.sys,,,0x20 + +[DriverInstall.NTamd64.AddReg] +HKR,,DevLoader,,*ntkern +HKR,,NTMPDriver,,usbser.sys +HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" + +[DriverInstall.NTamd64.Services] +AddService=usbser, 0x00000002, DriverService + +;------------------------------------------------------------------------------ +; +;------------------------------------------------------------------------------ + +[DriverService] +DisplayName=%SERVICE% +ServiceType=1 +StartType=3 +ErrorControl=1 +ServiceBinary=%12%\usbser.sys + +;------------------------------------------------------------------------------ +; String Definitions +;------------------------------------------------------------------------------ + +[Strings] +PROVIDER="Cypress" +MFGNAME="Cypress Semiconductor Corporation" +DESCRIPTION="Cypress USB UART" +SERVICE="USB UART" diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_cls.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_cls.c new file mode 100755 index 00000000..7b5dc275 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_cls.c @@ -0,0 +1,107 @@ +/******************************************************************************* +* File Name: USBFS_cls.c +* Version 2.60 +* +* Description: +* USB Class request handler. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS.h" + +#if(USBFS_EXTERN_CLS == USBFS_FALSE) + +#include "USBFS_pvt.h" + + +/*************************************** +* User Implemented Class Driver Declarations. +***************************************/ +/* `#START USER_DEFINED_CLASS_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +/******************************************************************************* +* Function Name: USBFS_DispatchClassRqst +******************************************************************************** +* Summary: +* This routine dispatches class specific requests depend on interface class. +* +* Parameters: +* None. +* +* Return: +* requestHandled. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_DispatchClassRqst(void) +{ + uint8 requestHandled = USBFS_FALSE; + uint8 interfaceNumber = 0u; + + switch(CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) + { + case USBFS_RQST_RCPT_IFC: /* Class-specific request directed to an interface */ + interfaceNumber = CY_GET_REG8(USBFS_wIndexLo); /* wIndexLo contain Interface number */ + break; + case USBFS_RQST_RCPT_EP: /* Class-specific request directed to the endpoint */ + /* Find related interface to the endpoint, wIndexLo contain EP number */ + interfaceNumber = + USBFS_EP[CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED].interface; + break; + default: /* RequestHandled is initialized as FALSE by default */ + break; + } + /* Handle Class request depend on interface type */ + switch(USBFS_interfaceClass[interfaceNumber]) + { + case USBFS_CLASS_HID: + #if defined(USBFS_ENABLE_HID_CLASS) + requestHandled = USBFS_DispatchHIDClassRqst(); + #endif /* USBFS_ENABLE_HID_CLASS */ + break; + case USBFS_CLASS_AUDIO: + #if defined(USBFS_ENABLE_AUDIO_CLASS) + requestHandled = USBFS_DispatchAUDIOClassRqst(); + #endif /* USBFS_ENABLE_HID_CLASS */ + break; + case USBFS_CLASS_CDC: + #if defined(USBFS_ENABLE_CDC_CLASS) + requestHandled = USBFS_DispatchCDCClassRqst(); + #endif /* USBFS_ENABLE_CDC_CLASS */ + break; + default: /* requestHandled is initialized as FALSE by default */ + break; + } + + /* `#START USER_DEFINED_CLASS_CODE` Place your Class request here */ + + /* `#END` */ + + return(requestHandled); +} + + +/******************************************************************************* +* Additional user functions supporting Class Specific Requests +********************************************************************************/ + +/* `#START CLASS_SPECIFIC_FUNCTIONS` Place any additional functions here */ + +/* `#END` */ + +#endif /* USBFS_EXTERN_CLS */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_descr.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_descr.c new file mode 100755 index 00000000..23e0b906 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_descr.c @@ -0,0 +1,319 @@ +/******************************************************************************* +* File Name: USBFS_descr.c +* Version 2.60 +* +* Description: +* USB descriptors and storage. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS.h" +#include "USBFS_pvt.h" + + +/***************************************************************************** +* User supplied descriptors. If you want to specify your own descriptors, +* remove the comments around the define USER_SUPPLIED_DESCRIPTORS below and +* add your descriptors. +*****************************************************************************/ +/* `#START USER_DESCRIPTORS_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +/*************************************** +* USB Customizer Generated Descriptors +***************************************/ + +#if !defined(USER_SUPPLIED_DESCRIPTORS) +/********************************************************************* +* Device Descriptors +*********************************************************************/ +const uint8 CYCODE USBFS_DEVICE0_DESCR[18u] = { +/* Descriptor Length */ 0x12u, +/* DescriptorType: DEVICE */ 0x01u, +/* bcdUSB (ver 2.0) */ 0x00u, 0x02u, +/* bDeviceClass */ 0x00u, +/* bDeviceSubClass */ 0x00u, +/* bDeviceProtocol */ 0x00u, +/* bMaxPacketSize0 */ 0x08u, +/* idVendor */ 0xB4u, 0x04u, +/* idProduct */ 0x37u, 0x13u, +/* bcdDevice */ 0x00u, 0x30u, +/* iManufacturer */ 0x02u, +/* iProduct */ 0x01u, +/* iSerialNumber */ 0x80u, +/* bNumConfigurations */ 0x01u +}; +/********************************************************************* +* Config Descriptor +*********************************************************************/ +const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_DESCR[41u] = { +/* Config Descriptor Length */ 0x09u, +/* DescriptorType: CONFIG */ 0x02u, +/* wTotalLength */ 0x29u, 0x00u, +/* bNumInterfaces */ 0x01u, +/* bConfigurationValue */ 0x01u, +/* iConfiguration */ 0x00u, +/* bmAttributes */ 0x80u, +/* bMaxPower */ 0xFAu, +/********************************************************************* +* Interface Descriptor +*********************************************************************/ +/* Interface Descriptor Length */ 0x09u, +/* DescriptorType: INTERFACE */ 0x04u, +/* bInterfaceNumber */ 0x00u, +/* bAlternateSetting */ 0x00u, +/* bNumEndpoints */ 0x02u, +/* bInterfaceClass */ 0x03u, +/* bInterfaceSubClass */ 0x00u, +/* bInterfaceProtocol */ 0x00u, +/* iInterface */ 0x00u, +/********************************************************************* +* HID Class Descriptor +*********************************************************************/ +/* HID Class Descriptor Length */ 0x09u, +/* DescriptorType: HID_CLASS */ 0x21u, +/* bcdHID */ 0x11u, 0x01u, +/* bCountryCode */ 0x00u, +/* bNumDescriptors */ 0x01u, +/* bDescriptorType */ 0x22u, +/* wDescriptorLength (LSB) */ USBFS_HID_RPT_1_SIZE_LSB, +/* wDescriptorLength (MSB) */ USBFS_HID_RPT_1_SIZE_MSB, +/********************************************************************* +* Endpoint Descriptor +*********************************************************************/ +/* Endpoint Descriptor Length */ 0x07u, +/* DescriptorType: ENDPOINT */ 0x05u, +/* bEndpointAddress */ 0x01u, +/* bmAttributes */ 0x03u, +/* wMaxPacketSize */ 0x40u, 0x00u, +/* bInterval */ 0x80u, +/********************************************************************* +* Endpoint Descriptor +*********************************************************************/ +/* Endpoint Descriptor Length */ 0x07u, +/* DescriptorType: ENDPOINT */ 0x05u, +/* bEndpointAddress */ 0x82u, +/* bmAttributes */ 0x03u, +/* wMaxPacketSize */ 0x40u, 0x00u, +/* bInterval */ 0x40u +}; + +/********************************************************************* +* String Descriptor Table +*********************************************************************/ +const uint8 CYCODE USBFS_STRING_DESCRIPTORS[45u] = { +/********************************************************************* +* Language ID Descriptor +*********************************************************************/ +/* Descriptor Length */ 0x04u, +/* DescriptorType: STRING */ 0x03u, +/* Language Id */ 0x09u, 0x04u, +/********************************************************************* +* String Descriptor: "SCSI2SD" +*********************************************************************/ +/* Descriptor Length */ 0x10u, +/* DescriptorType: STRING */ 0x03u, + (uint8)'S', 0u,(uint8)'C', 0u,(uint8)'S', 0u,(uint8)'I', 0u,(uint8)'2', 0u, + (uint8)'S', 0u,(uint8)'D', 0u, +/********************************************************************* +* String Descriptor: "codesrc.com" +*********************************************************************/ +/* Descriptor Length */ 0x18u, +/* DescriptorType: STRING */ 0x03u, + (uint8)'c', 0u,(uint8)'o', 0u,(uint8)'d', 0u,(uint8)'e', 0u,(uint8)'s', 0u, + (uint8)'r', 0u,(uint8)'c', 0u,(uint8)'.', 0u,(uint8)'c', 0u,(uint8)'o', 0u, + (uint8)'m', 0u, +/*********************************************************************/ +/* Marks the end of the list. */ 0x00u}; +/*********************************************************************/ + +/********************************************************************* +* Serial Number String Descriptor +*********************************************************************/ +const uint8 CYCODE USBFS_SN_STRING_DESCRIPTOR[10] = { +/* Descriptor Length */ 0x0Au, +/* DescriptorType: STRING */ 0x03u, +(uint8)'1', 0u,(uint8)'2', 0u,(uint8)'3', 0u,(uint8)'4', 0u +}; + +/********************************************************************* +* HID Report Descriptor: Generic HID +*********************************************************************/ +const uint8 CYCODE USBFS_HIDREPORT_DESCRIPTOR1[40u] = { +/* Descriptor Size (Not part of descriptor)*/ USBFS_HID_RPT_1_SIZE_LSB, +USBFS_HID_RPT_1_SIZE_MSB, +/* USAGE_PAGE */ 0x05u, 0x01u, +/* USAGE */ 0x09u, 0x00u, +/* COLLECTION */ 0xA1u, 0x00u, +/* USAGE */ 0x09u, 0x00u, +/* COLLECTION */ 0xA1u, 0x00u, +/* USAGE */ 0x09u, 0x00u, +/* LOGICAL_MINIMUM */ 0x15u, 0x00u, +/* LOGICAL_MAXIMUM */ 0x25u, 0xFFu, +/* REPORT_SIZE */ 0x75u, 0x08u, +/* REPORT_COUNT */ 0x95u, 0x40u, +/* OUTPUT */ 0x91u, 0x02u, +/* USAGE */ 0x09u, 0x00u, +/* LOGICAL_MINIMUM */ 0x15u, 0x00u, +/* LOGICAL_MAXIMUM */ 0x25u, 0xFFu, +/* REPORT_SIZE */ 0x75u, 0x08u, +/* REPORT_COUNT */ 0x95u, 0x40u, +/* INPUT */ 0x81u, 0x02u, +/* END_COLLECTION */ 0xC0u, +/* END_COLLECTION */ 0xC0u, +/*********************************************************************/ +/* End of the HID Report Descriptor */ 0x00u, 0x00u}; +/*********************************************************************/ + +#if !defined(USER_DEFINE_USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_HID_RPT_STORAGE) +/********************************************************************* +* HID Input Report Storage +*********************************************************************/ +T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_RPT_SCB; +uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF[ + USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF_SIZE]; + +/********************************************************************* +* HID Input Report TD Table +*********************************************************************/ +const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_RPT_TABLE[1u] = { + {USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF_SIZE, + &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF[0u], + &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_RPT_SCB}, +}; +/********************************************************************* +* HID Output Report Storage +*********************************************************************/ +T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_RPT_SCB; +uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF[ + USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF_SIZE]; + +/********************************************************************* +* HID Output Report TD Table +*********************************************************************/ +const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_RPT_TABLE[1u] = { + {USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF_SIZE, + &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF[0u], + &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_RPT_SCB}, +}; +/********************************************************************* +* HID Report Look Up Table This table has four entries: +* IN Report Table +* OUT Report Table +* Feature Report Table +* HID Report Descriptor +* HID Class Descriptor +*********************************************************************/ +const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_TABLE[5u] = { + {0x00u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_RPT_TABLE}, + {0x00u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_RPT_TABLE}, + {0x00u, NULL}, + {0x01u, (const void *)&USBFS_HIDREPORT_DESCRIPTOR1[0]}, + {0x01u, (const void *)&USBFS_DEVICE0_CONFIGURATION0_DESCR[18]} +}; +#endif /* USER_DEFINE_USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_HID_RPT_STORAGE */ + +/********************************************************************* +* Interface Dispatch Table -- Points to the Class Dispatch Tables +*********************************************************************/ +const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_TABLE[1u] = { + {USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_COUNT, + &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_TABLE} +}; +/********************************************************************* +* Endpoint Setting Table -- This table contain the endpoint setting +* for each endpoint in the configuration. It +* contains the necessary information to +* configure the endpoint hardware for each +* interface and alternate setting. +*********************************************************************/ +const T_USBFS_EP_SETTINGS_BLOCK CYCODE USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE[2u] = { +/* IFC ALT EPAddr bmAttr MaxPktSize Class ********************/ +{0x00u, 0x00u, 0x01u, 0x03u, 0x0040u, 0x03u}, +{0x00u, 0x00u, 0x82u, 0x03u, 0x0040u, 0x03u} +}; +const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE_CLASS[1u] = { +0x03u +}; +/********************************************************************* +* Config Dispatch Table -- Points to the Config Descriptor and each of +* and endpoint setup table and to each +* interface table if it specifies a USB Class +*********************************************************************/ +const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_TABLE[4u] = { + {0x01u, &USBFS_DEVICE0_CONFIGURATION0_DESCR}, + {0x02u, &USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE}, + {0x01u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_TABLE}, + {0x00u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE_CLASS} +}; +/********************************************************************* +* Device Dispatch Table -- Points to the Device Descriptor and each of +* and Configuration Tables for this Device +*********************************************************************/ +const T_USBFS_LUT CYCODE USBFS_DEVICE0_TABLE[2u] = { + {0x01u, &USBFS_DEVICE0_DESCR}, + {0x01u, &USBFS_DEVICE0_CONFIGURATION0_TABLE} +}; +/********************************************************************* +* Device Table -- Indexed by the device number. +*********************************************************************/ +const T_USBFS_LUT CYCODE USBFS_TABLE[1u] = { + {0x01u, &USBFS_DEVICE0_TABLE} +}; + +#endif /* USER_SUPPLIED_DESCRIPTORS */ + +#if defined(USBFS_ENABLE_MSOS_STRING) + + /****************************************************************************** + * USB Microsoft OS String Descriptor + * "MSFT" identifies a Microsoft host + * "100" specifies version 1.00 + * USBFS_GET_EXTENDED_CONFIG_DESCRIPTOR becomes the bRequest value + * in a host vendor device/class request + ******************************************************************************/ + + const uint8 CYCODE USBFS_MSOS_DESCRIPTOR[USBFS_MSOS_DESCRIPTOR_LENGTH] = { + /* Descriptor Length */ 0x12u, + /* DescriptorType: STRING */ 0x03u, + /* qwSignature - "MSFT100" */ (uint8)'M', 0u, (uint8)'S', 0u, (uint8)'F', 0u, (uint8)'T', 0u, + (uint8)'1', 0u, (uint8)'0', 0u, (uint8)'0', 0u, + /* bMS_VendorCode: */ USBFS_GET_EXTENDED_CONFIG_DESCRIPTOR, + /* bPad */ 0x00u + }; + + /* Extended Configuration Descriptor */ + + const uint8 CYCODE USBFS_MSOS_CONFIGURATION_DESCR[USBFS_MSOS_CONF_DESCR_LENGTH] = { + /* Length of the descriptor 4 bytes */ 0x28u, 0x00u, 0x00u, 0x00u, + /* Version of the descriptor 2 bytes */ 0x00u, 0x01u, + /* wIndex - Fixed:INDEX_CONFIG_DESCRIPTOR */ 0x04u, 0x00u, + /* bCount - Count of device functions. */ 0x01u, + /* Reserved : 7 bytes */ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + /* bFirstInterfaceNumber */ 0x00u, + /* Reserved */ 0x01u, + /* compatibleID - "CYUSB\0\0" */ (uint8)'C', (uint8)'Y', (uint8)'U', (uint8)'S', (uint8)'B', + 0x00u, 0x00u, 0x00u, + /* subcompatibleID - "00001\0\0" */ (uint8)'0', (uint8)'0', (uint8)'0', (uint8)'0', (uint8)'1', + 0x00u, 0x00u, 0x00u, + /* Reserved : 6 bytes */ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u + }; + +#endif /* USBFS_ENABLE_MSOS_STRING */ + +/* DIE ID string descriptor for 8 bytes ID */ +#if defined(USBFS_ENABLE_IDSN_STRING) + uint8 USBFS_idSerialNumberStringDescriptor[USBFS_IDSN_DESCR_LENGTH]; +#endif /* USBFS_ENABLE_IDSN_STRING */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_drv.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_drv.c new file mode 100755 index 00000000..f4308eab --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_drv.c @@ -0,0 +1,781 @@ +/******************************************************************************* +* File Name: USBFS_drv.c +* Version 2.60 +* +* Description: +* Endpoint 0 Driver for the USBFS Component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS.h" +#include "USBFS_pvt.h" + + +/*************************************** +* Global data allocation +***************************************/ + +volatile T_USBFS_EP_CTL_BLOCK USBFS_EP[USBFS_MAX_EP]; +volatile uint8 USBFS_configuration; +volatile uint8 USBFS_interfaceNumber; +volatile uint8 USBFS_configurationChanged; +volatile uint8 USBFS_deviceAddress; +volatile uint8 USBFS_deviceStatus; +volatile uint8 USBFS_interfaceSetting[USBFS_MAX_INTERFACES_NUMBER]; +volatile uint8 USBFS_interfaceSetting_last[USBFS_MAX_INTERFACES_NUMBER]; +volatile uint8 USBFS_interfaceStatus[USBFS_MAX_INTERFACES_NUMBER]; +volatile uint8 USBFS_device; +const uint8 CYCODE *USBFS_interfaceClass; + + +/*************************************** +* Local data allocation +***************************************/ + +volatile uint8 USBFS_ep0Toggle; +volatile uint8 USBFS_lastPacketSize; +volatile uint8 USBFS_transferState; +volatile T_USBFS_TD USBFS_currentTD; +volatile uint8 USBFS_ep0Mode; +volatile uint8 USBFS_ep0Count; +volatile uint16 USBFS_transferByteCount; + + +/******************************************************************************* +* Function Name: USBFS_ep_0_Interrupt +******************************************************************************** +* +* Summary: +* This Interrupt Service Routine handles Endpoint 0 (Control Pipe) traffic. +* It dispatches setup requests and handles the data and status stages. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +CY_ISR(USBFS_EP_0_ISR) +{ + uint8 bRegTemp; + uint8 modifyReg; + + + bRegTemp = CY_GET_REG8(USBFS_EP0_CR_PTR); + if ((bRegTemp & USBFS_MODE_ACKD) != 0u) + { + modifyReg = 1u; + if ((bRegTemp & USBFS_MODE_SETUP_RCVD) != 0u) + { + if((bRegTemp & USBFS_MODE_MASK) != USBFS_MODE_NAK_IN_OUT) + { + modifyReg = 0u; /* When mode not NAK_IN_OUT => invalid setup */ + } + else + { + USBFS_HandleSetup(); + if((USBFS_ep0Mode & USBFS_MODE_SETUP_RCVD) != 0u) + { + modifyReg = 0u; /* if SETUP bit set -> exit without modifying the mode */ + } + + } + } + else if ((bRegTemp & USBFS_MODE_IN_RCVD) != 0u) + { + USBFS_HandleIN(); + } + else if ((bRegTemp & USBFS_MODE_OUT_RCVD) != 0u) + { + USBFS_HandleOUT(); + } + else + { + modifyReg = 0u; + } + if(modifyReg != 0u) + { + bRegTemp = CY_GET_REG8(USBFS_EP0_CR_PTR); /* unlock registers */ + if((bRegTemp & USBFS_MODE_SETUP_RCVD) == 0u) /* Check if SETUP bit is not set, otherwise exit */ + { + /* Update the count register */ + bRegTemp = USBFS_ep0Toggle | USBFS_ep0Count; + CY_SET_REG8(USBFS_EP0_CNT_PTR, bRegTemp); + if(bRegTemp == CY_GET_REG8(USBFS_EP0_CNT_PTR)) /* continue if writing was successful */ + { + do + { + modifyReg = USBFS_ep0Mode; /* Init temporary variable */ + /* Unlock registers */ + bRegTemp = CY_GET_REG8(USBFS_EP0_CR_PTR) & USBFS_MODE_SETUP_RCVD; + if(bRegTemp == 0u) /* Check if SETUP bit is not set */ + { + /* Set the Mode Register */ + CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_ep0Mode); + /* Writing check */ + modifyReg = CY_GET_REG8(USBFS_EP0_CR_PTR) & USBFS_MODE_MASK; + } + }while(modifyReg != USBFS_ep0Mode); /* Repeat if writing was not successful */ + } + } + } + } +} + + +/******************************************************************************* +* Function Name: USBFS_HandleSetup +******************************************************************************** +* +* Summary: +* This Routine dispatches requests for the four USB request types +* +* Parameters: +* None. +* +* Return: +* None. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_HandleSetup(void) +{ + uint8 requestHandled; + + requestHandled = CY_GET_REG8(USBFS_EP0_CR_PTR); /* unlock registers */ + CY_SET_REG8(USBFS_EP0_CR_PTR, requestHandled); /* clear setup bit */ + requestHandled = CY_GET_REG8(USBFS_EP0_CR_PTR); /* reread register */ + if((requestHandled & USBFS_MODE_SETUP_RCVD) != 0u) + { + USBFS_ep0Mode = requestHandled; /* if SETUP bit set -> exit without modifying the mode */ + } + else + { + /* In case the previous transfer did not complete, close it out */ + USBFS_UpdateStatusBlock(USBFS_XFER_PREMATURE); + + switch (CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_TYPE_MASK) + { + case USBFS_RQST_TYPE_STD: + requestHandled = USBFS_HandleStandardRqst(); + break; + case USBFS_RQST_TYPE_CLS: + requestHandled = USBFS_DispatchClassRqst(); + break; + case USBFS_RQST_TYPE_VND: + requestHandled = USBFS_HandleVendorRqst(); + break; + default: + requestHandled = USBFS_FALSE; + break; + } + if (requestHandled == USBFS_FALSE) + { + USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; + } + } +} + + +/******************************************************************************* +* Function Name: USBFS_HandleIN +******************************************************************************** +* +* Summary: +* This routine handles EP0 IN transfers. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_HandleIN(void) +{ + switch (USBFS_transferState) + { + case USBFS_TRANS_STATE_IDLE: + break; + case USBFS_TRANS_STATE_CONTROL_READ: + USBFS_ControlReadDataStage(); + break; + case USBFS_TRANS_STATE_CONTROL_WRITE: + USBFS_ControlWriteStatusStage(); + break; + case USBFS_TRANS_STATE_NO_DATA_CONTROL: + USBFS_NoDataControlStatusStage(); + break; + default: /* there are no more states */ + break; + } +} + + +/******************************************************************************* +* Function Name: USBFS_HandleOUT +******************************************************************************** +* +* Summary: +* This routine handles EP0 OUT transfers. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_HandleOUT(void) +{ + switch (USBFS_transferState) + { + case USBFS_TRANS_STATE_IDLE: + break; + case USBFS_TRANS_STATE_CONTROL_READ: + USBFS_ControlReadStatusStage(); + break; + case USBFS_TRANS_STATE_CONTROL_WRITE: + USBFS_ControlWriteDataStage(); + break; + case USBFS_TRANS_STATE_NO_DATA_CONTROL: + /* Update the completion block */ + USBFS_UpdateStatusBlock(USBFS_XFER_ERROR); + /* We expect no more data, so stall INs and OUTs */ + USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; + break; + default: /* There are no more states */ + break; + } +} + + +/******************************************************************************* +* Function Name: USBFS_LoadEP0 +******************************************************************************** +* +* Summary: +* This routine loads the EP0 data registers for OUT transfers. It uses the +* currentTD (previously initialized by the _InitControlWrite function and +* updated for each OUT transfer, and the bLastPacketSize) to determine how +* many uint8s to transfer on the current OUT. +* +* If the number of uint8s remaining is zero and the last transfer was full, +* we need to send a zero length packet. Otherwise we send the minimum +* of the control endpoint size (8) or remaining number of uint8s for the +* transaction. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* USBFS_transferByteCount - Update the transfer byte count from the +* last transaction. +* USBFS_ep0Count - counts the data loaded to the SIE memory in +* current packet. +* USBFS_lastPacketSize - remembers the USBFS_ep0Count value for the +* next packet. +* USBFS_transferByteCount - sum of the previous bytes transferred +* on previous packets(sum of USBFS_lastPacketSize) +* USBFS_ep0Toggle - inverted +* USBFS_ep0Mode - prepare for mode register content. +* USBFS_transferState - set to TRANS_STATE_CONTROL_READ +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_LoadEP0(void) +{ + uint8 ep0Count = 0u; + + /* Update the transfer byte count from the last transaction */ + USBFS_transferByteCount += USBFS_lastPacketSize; + /* Now load the next transaction */ + while ((USBFS_currentTD.count > 0u) && (ep0Count < 8u)) + { + CY_SET_REG8((reg8 *)(USBFS_EP0_DR0_IND + ep0Count), *USBFS_currentTD.pData); + USBFS_currentTD.pData = &USBFS_currentTD.pData[1u]; + ep0Count++; + USBFS_currentTD.count--; + } + /* Support zero-length packet*/ + if( (USBFS_lastPacketSize == 8u) || (ep0Count > 0u) ) + { + /* Update the data toggle */ + USBFS_ep0Toggle ^= USBFS_EP0_CNT_DATA_TOGGLE; + /* Set the Mode Register */ + USBFS_ep0Mode = USBFS_MODE_ACK_IN_STATUS_OUT; + /* Update the state (or stay the same) */ + USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ; + } + else + { + /* Expect Status Stage Out */ + USBFS_ep0Mode = USBFS_MODE_STATUS_OUT_ONLY; + /* Update the state (or stay the same) */ + USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ; + } + + /* Save the packet size for next time */ + USBFS_lastPacketSize = ep0Count; + USBFS_ep0Count = ep0Count; +} + + +/******************************************************************************* +* Function Name: USBFS_InitControlRead +******************************************************************************** +* +* Summary: +* Initialize a control read transaction, usable to send data to the host. +* The following global variables should be initialized before this function +* called. To send zero length packet use InitZeroLengthControlTransfer +* function. +* +* Parameters: +* None. +* +* Return: +* requestHandled state. +* +* Global variables: +* USBFS_currentTD.count - counts of data to be sent. +* USBFS_currentTD.pData - data pointer. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_InitControlRead(void) +{ + uint16 xferCount; + if(USBFS_currentTD.count == 0u) + { + (void) USBFS_InitZeroLengthControlTransfer(); + } + else + { + /* Set up the state machine */ + USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ; + /* Set the toggle, it gets updated in LoadEP */ + USBFS_ep0Toggle = 0u; + /* Initialize the Status Block */ + USBFS_InitializeStatusBlock(); + xferCount = (((uint16)CY_GET_REG8(USBFS_lengthHi) << 8u) | (CY_GET_REG8(USBFS_lengthLo))); + + if (USBFS_currentTD.count > xferCount) + { + USBFS_currentTD.count = xferCount; + } + USBFS_LoadEP0(); + } + + return(USBFS_TRUE); +} + + +/******************************************************************************* +* Function Name: USBFS_InitZeroLengthControlTransfer +******************************************************************************** +* +* Summary: +* Initialize a zero length data IN transfer. +* +* Parameters: +* None. +* +* Return: +* requestHandled state. +* +* Global variables: +* USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE +* USBFS_ep0Mode - prepare for mode register content. +* USBFS_transferState - set to TRANS_STATE_CONTROL_READ +* USBFS_ep0Count - cleared, means the zero-length packet. +* USBFS_lastPacketSize - cleared. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_InitZeroLengthControlTransfer(void) + +{ + /* Update the state */ + USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ; + /* Set the data toggle */ + USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE; + /* Set the Mode Register */ + USBFS_ep0Mode = USBFS_MODE_ACK_IN_STATUS_OUT; + /* Save the packet size for next time */ + USBFS_lastPacketSize = 0u; + USBFS_ep0Count = 0u; + + return(USBFS_TRUE); +} + + +/******************************************************************************* +* Function Name: USBFS_ControlReadDataStage +******************************************************************************** +* +* Summary: +* Handle the Data Stage of a control read transfer. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_ControlReadDataStage(void) + +{ + USBFS_LoadEP0(); +} + + +/******************************************************************************* +* Function Name: USBFS_ControlReadStatusStage +******************************************************************************** +* +* Summary: +* Handle the Status Stage of a control read transfer. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* USBFS_USBFS_transferByteCount - updated with last packet size. +* USBFS_transferState - set to TRANS_STATE_IDLE. +* USBFS_ep0Mode - set to MODE_STALL_IN_OUT. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_ControlReadStatusStage(void) +{ + /* Update the transfer byte count */ + USBFS_transferByteCount += USBFS_lastPacketSize; + /* Go Idle */ + USBFS_transferState = USBFS_TRANS_STATE_IDLE; + /* Update the completion block */ + USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK); + /* We expect no more data, so stall INs and OUTs */ + USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; +} + + +/******************************************************************************* +* Function Name: USBFS_InitControlWrite +******************************************************************************** +* +* Summary: +* Initialize a control write transaction +* +* Parameters: +* None. +* +* Return: +* requestHandled state. +* +* Global variables: +* USBFS_USBFS_transferState - set to TRANS_STATE_CONTROL_WRITE +* USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE +* USBFS_ep0Mode - set to MODE_ACK_OUT_STATUS_IN +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_InitControlWrite(void) +{ + uint16 xferCount; + + /* Set up the state machine */ + USBFS_transferState = USBFS_TRANS_STATE_CONTROL_WRITE; + /* This might not be necessary */ + USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE; + /* Initialize the Status Block */ + USBFS_InitializeStatusBlock(); + + xferCount = (((uint16)CY_GET_REG8(USBFS_lengthHi) << 8u) | (CY_GET_REG8(USBFS_lengthLo))); + + if (USBFS_currentTD.count > xferCount) + { + USBFS_currentTD.count = xferCount; + } + + /* Expect Data or Status Stage */ + USBFS_ep0Mode = USBFS_MODE_ACK_OUT_STATUS_IN; + + return(USBFS_TRUE); +} + + +/******************************************************************************* +* Function Name: USBFS_ControlWriteDataStage +******************************************************************************** +* +* Summary: +* Handle the Data Stage of a control write transfer +* 1. Get the data (We assume the destination was validated previously) +* 2. Update the count and data toggle +* 3. Update the mode register for the next transaction +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* USBFS_transferByteCount - Update the transfer byte count from the +* last transaction. +* USBFS_ep0Count - counts the data loaded from the SIE memory +* in current packet. +* USBFS_transferByteCount - sum of the previous bytes transferred +* on previous packets(sum of USBFS_lastPacketSize) +* USBFS_ep0Toggle - inverted +* USBFS_ep0Mode - set to MODE_ACK_OUT_STATUS_IN. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_ControlWriteDataStage(void) +{ + uint8 ep0Count; + uint8 regIndex = 0u; + + ep0Count = (CY_GET_REG8(USBFS_EP0_CNT_PTR) & USBFS_EPX_CNT0_MASK) - + USBFS_EPX_CNTX_CRC_COUNT; + + USBFS_transferByteCount += ep0Count; + + while ((USBFS_currentTD.count > 0u) && (ep0Count > 0u)) + { + *USBFS_currentTD.pData = CY_GET_REG8((reg8 *)(USBFS_EP0_DR0_IND + regIndex)); + USBFS_currentTD.pData = &USBFS_currentTD.pData[1u]; + regIndex++; + ep0Count--; + USBFS_currentTD.count--; + } + USBFS_ep0Count = ep0Count; + /* Update the data toggle */ + USBFS_ep0Toggle ^= USBFS_EP0_CNT_DATA_TOGGLE; + /* Expect Data or Status Stage */ + USBFS_ep0Mode = USBFS_MODE_ACK_OUT_STATUS_IN; +} + + +/******************************************************************************* +* Function Name: USBFS_ControlWriteStatusStage +******************************************************************************** +* +* Summary: +* Handle the Status Stage of a control write transfer +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* USBFS_transferState - set to TRANS_STATE_IDLE. +* USBFS_USBFS_ep0Mode - set to MODE_STALL_IN_OUT. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_ControlWriteStatusStage(void) +{ + /* Go Idle */ + USBFS_transferState = USBFS_TRANS_STATE_IDLE; + /* Update the completion block */ + USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK); + /* We expect no more data, so stall INs and OUTs */ + USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; +} + + +/******************************************************************************* +* Function Name: USBFS_InitNoDataControlTransfer +******************************************************************************** +* +* Summary: +* Initialize a no data control transfer +* +* Parameters: +* None. +* +* Return: +* requestHandled state. +* +* Global variables: +* USBFS_transferState - set to TRANS_STATE_NO_DATA_CONTROL. +* USBFS_ep0Mode - set to MODE_STATUS_IN_ONLY. +* USBFS_ep0Count - cleared. +* USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_InitNoDataControlTransfer(void) +{ + USBFS_transferState = USBFS_TRANS_STATE_NO_DATA_CONTROL; + USBFS_ep0Mode = USBFS_MODE_STATUS_IN_ONLY; + USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE; + USBFS_ep0Count = 0u; + + return(USBFS_TRUE); +} + + +/******************************************************************************* +* Function Name: USBFS_NoDataControlStatusStage +******************************************************************************** +* Summary: +* Handle the Status Stage of a no data control transfer. +* +* SET_ADDRESS is special, since we need to receive the status stage with +* the old address. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* USBFS_transferState - set to TRANS_STATE_IDLE. +* USBFS_ep0Mode - set to MODE_STALL_IN_OUT. +* USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE +* USBFS_deviceAddress - used to set new address and cleared +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_NoDataControlStatusStage(void) +{ + /* Change the USB address register if we got a SET_ADDRESS. */ + if (USBFS_deviceAddress != 0u) + { + CY_SET_REG8(USBFS_CR0_PTR, USBFS_deviceAddress | USBFS_CR0_ENABLE); + USBFS_deviceAddress = 0u; + } + /* Go Idle */ + USBFS_transferState = USBFS_TRANS_STATE_IDLE; + /* Update the completion block */ + USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK); + /* We expect no more data, so stall INs and OUTs */ + USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; +} + + +/******************************************************************************* +* Function Name: USBFS_UpdateStatusBlock +******************************************************************************** +* +* Summary: +* Update the Completion Status Block for a Request. The block is updated +* with the completion code the USBFS_transferByteCount. The +* StatusBlock Pointer is set to NULL. +* +* Parameters: +* completionCode - status. +* +* Return: +* None. +* +* Global variables: +* USBFS_currentTD.pStatusBlock->status - updated by the +* completionCode parameter. +* USBFS_currentTD.pStatusBlock->length - updated. +* USBFS_currentTD.pStatusBlock - cleared. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_UpdateStatusBlock(uint8 completionCode) +{ + if (USBFS_currentTD.pStatusBlock != NULL) + { + USBFS_currentTD.pStatusBlock->status = completionCode; + USBFS_currentTD.pStatusBlock->length = USBFS_transferByteCount; + USBFS_currentTD.pStatusBlock = NULL; + } +} + + +/******************************************************************************* +* Function Name: USBFS_InitializeStatusBlock +******************************************************************************** +* +* Summary: +* Initialize the Completion Status Block for a Request. The completion +* code is set to USB_XFER_IDLE. +* +* Also, initializes USBFS_transferByteCount. Save some space, +* this is the only consumer. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* USBFS_currentTD.pStatusBlock->status - set to XFER_IDLE. +* USBFS_currentTD.pStatusBlock->length - cleared. +* USBFS_transferByteCount - cleared. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_InitializeStatusBlock(void) +{ + USBFS_transferByteCount = 0u; + if(USBFS_currentTD.pStatusBlock != NULL) + { + USBFS_currentTD.pStatusBlock->status = USBFS_XFER_IDLE; + USBFS_currentTD.pStatusBlock->length = 0u; + } +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_episr.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_episr.c new file mode 100755 index 00000000..d758bf4d --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_episr.c @@ -0,0 +1,658 @@ +/******************************************************************************* +* File Name: USBFS_episr.c +* Version 2.60 +* +* Description: +* Data endpoint Interrupt Service Routines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS.h" +#include "USBFS_pvt.h" +#if defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u) + #include "USBFS_midi.h" +#endif /* End USBFS_ENABLE_MIDI_STREAMING*/ + + +/*************************************** +* Custom Declarations +***************************************/ +/* `#START CUSTOM_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +#if(USBFS_EP1_ISR_REMOVE == 0u) + + + /****************************************************************************** + * Function Name: USBFS_EP_1_ISR + ******************************************************************************* + * + * Summary: + * Endpoint 1 Interrupt Service Routine + * + * Parameters: + * None. + * + * Return: + * None. + * + ******************************************************************************/ + CY_ISR(USBFS_EP_1_ISR) + { + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + uint8 int_en; + #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ + + /* `#START EP1_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + int_en = EA; + CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ + #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ + + CY_GET_REG8(USBFS_SIE_EP1_CR0_PTR); /* Must read the mode reg */ + /* Do not toggle ISOC endpoint */ + if((USBFS_EP[USBFS_EP1].attrib & USBFS_EP_TYPE_MASK) != + USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP1].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + USBFS_EP[USBFS_EP1].apiEpState = USBFS_EVENT_PENDING; + CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) & + (uint8)~USBFS_SIE_EP_INT_EP1_MASK); + + #if( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT ) + if(USBFS_midi_out_ep == USBFS_EP1) + { + USBFS_MIDI_OUT_EP_Service(); + } + #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */ + + /* `#START EP1_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 ) + EA = int_en; + #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ + } + +#endif /* End USBFS_EP1_ISR_REMOVE */ + + +#if(USBFS_EP2_ISR_REMOVE == 0u) + + /******************************************************************************* + * Function Name: USBFS_EP_2_ISR + ******************************************************************************** + * + * Summary: + * Endpoint 2 Interrupt Service Routine + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + CY_ISR(USBFS_EP_2_ISR) + { + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + uint8 int_en; + #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ + + /* `#START EP2_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 ) + int_en = EA; + CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ + #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ + + CY_GET_REG8(USBFS_SIE_EP2_CR0_PTR); /* Must read the mode reg */ + /* Do not toggle ISOC endpoint */ + if((USBFS_EP[USBFS_EP2].attrib & USBFS_EP_TYPE_MASK) != + USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP2].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + USBFS_EP[USBFS_EP2].apiEpState = USBFS_EVENT_PENDING; + CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) + & (uint8)~USBFS_SIE_EP_INT_EP2_MASK); + + #if( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT ) + if(USBFS_midi_out_ep == USBFS_EP2) + { + USBFS_MIDI_OUT_EP_Service(); + } + #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */ + + /* `#START EP2_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + EA = int_en; + #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ + } + +#endif /* End USBFS_EP2_ISR_REMOVE */ + + +#if(USBFS_EP3_ISR_REMOVE == 0u) + + /******************************************************************************* + * Function Name: USBFS_EP_3_ISR + ******************************************************************************** + * + * Summary: + * Endpoint 3 Interrupt Service Routine + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + CY_ISR(USBFS_EP_3_ISR) + { + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + uint8 int_en; + #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ + + /* `#START EP3_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + int_en = EA; + CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + + CY_GET_REG8(USBFS_SIE_EP3_CR0_PTR); /* Must read the mode reg */ + /* Do not toggle ISOC endpoint */ + if((USBFS_EP[USBFS_EP3].attrib & USBFS_EP_TYPE_MASK) != + USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP3].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + USBFS_EP[USBFS_EP3].apiEpState = USBFS_EVENT_PENDING; + CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) + & (uint8)~USBFS_SIE_EP_INT_EP3_MASK); + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT) + if(USBFS_midi_out_ep == USBFS_EP3) + { + USBFS_MIDI_OUT_EP_Service(); + } + #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */ + + /* `#START EP3_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + EA = int_en; + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + } + +#endif /* End USBFS_EP3_ISR_REMOVE */ + + +#if(USBFS_EP4_ISR_REMOVE == 0u) + + /******************************************************************************* + * Function Name: USBFS_EP_4_ISR + ******************************************************************************** + * + * Summary: + * Endpoint 4 Interrupt Service Routine + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + CY_ISR(USBFS_EP_4_ISR) + { + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + uint8 int_en; + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + + /* `#START EP4_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + int_en = EA; + CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + + CY_GET_REG8(USBFS_SIE_EP4_CR0_PTR); /* Must read the mode reg */ + /* Do not toggle ISOC endpoint */ + if((USBFS_EP[USBFS_EP4].attrib & USBFS_EP_TYPE_MASK) != + USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP4].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + USBFS_EP[USBFS_EP4].apiEpState = USBFS_EVENT_PENDING; + CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) + & (uint8)~USBFS_SIE_EP_INT_EP4_MASK); + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT) + if(USBFS_midi_out_ep == USBFS_EP4) + { + USBFS_MIDI_OUT_EP_Service(); + } + #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */ + + /* `#START EP4_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + EA = int_en; + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + } + +#endif /* End USBFS_EP4_ISR_REMOVE */ + + +#if(USBFS_EP5_ISR_REMOVE == 0u) + + /******************************************************************************* + * Function Name: USBFS_EP_5_ISR + ******************************************************************************** + * + * Summary: + * Endpoint 5 Interrupt Service Routine + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + CY_ISR(USBFS_EP_5_ISR) + { + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + uint8 int_en; + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + + /* `#START EP5_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + int_en = EA; + CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + + CY_GET_REG8(USBFS_SIE_EP5_CR0_PTR); /* Must read the mode reg */ + /* Do not toggle ISOC endpoint */ + if((USBFS_EP[USBFS_EP5].attrib & USBFS_EP_TYPE_MASK) != + USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP5].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + USBFS_EP[USBFS_EP5].apiEpState = USBFS_EVENT_PENDING; + CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) + & (uint8)~USBFS_SIE_EP_INT_EP5_MASK); + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT) + if(USBFS_midi_out_ep == USBFS_EP5) + { + USBFS_MIDI_OUT_EP_Service(); + } + #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */ + + /* `#START EP5_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + EA = int_en; + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + } +#endif /* End USBFS_EP5_ISR_REMOVE */ + + +#if(USBFS_EP6_ISR_REMOVE == 0u) + + /******************************************************************************* + * Function Name: USBFS_EP_6_ISR + ******************************************************************************** + * + * Summary: + * Endpoint 6 Interrupt Service Routine + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + CY_ISR(USBFS_EP_6_ISR) + { + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + uint8 int_en; + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + + /* `#START EP6_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + int_en = EA; + CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + + CY_GET_REG8(USBFS_SIE_EP6_CR0_PTR); /* Must read the mode reg */ + /* Do not toggle ISOC endpoint */ + if((USBFS_EP[USBFS_EP6].attrib & USBFS_EP_TYPE_MASK) != + USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP6].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + USBFS_EP[USBFS_EP6].apiEpState = USBFS_EVENT_PENDING; + CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) + & (uint8)~USBFS_SIE_EP_INT_EP6_MASK); + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT) + if(USBFS_midi_out_ep == USBFS_EP6) + { + USBFS_MIDI_OUT_EP_Service(); + } + #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */ + + /* `#START EP6_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + EA = int_en; + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + } + +#endif /* End USBFS_EP6_ISR_REMOVE */ + + +#if(USBFS_EP7_ISR_REMOVE == 0u) + + /******************************************************************************* + * Function Name: USBFS_EP_7_ISR + ******************************************************************************** + * + * Summary: + * Endpoint 7 Interrupt Service Routine + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + CY_ISR(USBFS_EP_7_ISR) + { + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + uint8 int_en; + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + + /* `#START EP7_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + int_en = EA; + CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + + CY_GET_REG8(USBFS_SIE_EP7_CR0_PTR); /* Must read the mode reg */ + /* Do not toggle ISOC endpoint */ + if((USBFS_EP[USBFS_EP7].attrib & USBFS_EP_TYPE_MASK) != + USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP7].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + USBFS_EP[USBFS_EP7].apiEpState = USBFS_EVENT_PENDING; + CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) + & (uint8)~USBFS_SIE_EP_INT_EP7_MASK); + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT) + if(USBFS_midi_out_ep == USBFS_EP7) + { + USBFS_MIDI_OUT_EP_Service(); + } + #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */ + + /* `#START EP7_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + EA = int_en; + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + } + +#endif /* End USBFS_EP7_ISR_REMOVE */ + + +#if(USBFS_EP8_ISR_REMOVE == 0u) + + /******************************************************************************* + * Function Name: USBFS_EP_8_ISR + ******************************************************************************** + * + * Summary: + * Endpoint 8 Interrupt Service Routine + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + CY_ISR(USBFS_EP_8_ISR) + { + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + uint8 int_en; + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + + /* `#START EP8_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + int_en = EA; + CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + + CY_GET_REG8(USBFS_SIE_EP8_CR0_PTR); /* Must read the mode reg */ + /* Do not toggle ISOC endpoint */ + if((USBFS_EP[USBFS_EP8].attrib & USBFS_EP_TYPE_MASK) != + USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP8].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + USBFS_EP[USBFS_EP8].apiEpState = USBFS_EVENT_PENDING; + CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) + & (uint8)~USBFS_SIE_EP_INT_EP8_MASK); + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT) + if(USBFS_midi_out_ep == USBFS_EP8) + { + USBFS_MIDI_OUT_EP_Service(); + } + #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */ + + /* `#START EP8_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + EA = int_en; + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + } + +#endif /* End USBFS_EP8_ISR_REMOVE */ + + +/******************************************************************************* +* Function Name: USBFS_SOF_ISR +******************************************************************************** +* +* Summary: +* Start of Frame Interrupt Service Routine +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +CY_ISR(USBFS_SOF_ISR) +{ + /* `#START SOF_USER_CODE` Place your code here */ + + /* `#END` */ +} + + +/******************************************************************************* +* Function Name: USBFS_BUS_RESET_ISR +******************************************************************************** +* +* Summary: +* USB Bus Reset Interrupt Service Routine. Calls _Start with the same +* parameters as the last USER call to _Start +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +CY_ISR(USBFS_BUS_RESET_ISR) +{ + /* `#START BUS_RESET_USER_CODE` Place your code here */ + + /* `#END` */ + + USBFS_ReInitComponent(); +} + + +#if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u)) + + + /******************************************************************************* + * Function Name: USBFS_ARB_ISR + ******************************************************************************** + * + * Summary: + * Arbiter Interrupt Service Routine + * + * Parameters: + * None. + * + * Return: + * None. + * + * Side effect: + * Search for EP8 int_status will be much slower than search for EP1 int_status. + * + *******************************************************************************/ + CY_ISR(USBFS_ARB_ISR) + { + uint8 int_status; + uint8 ep_status; + uint8 ep = USBFS_EP1; + uint8 ptr = 0u; + + /* `#START ARB_BEGIN_USER_CODE` Place your code here */ + + /* `#END` */ + + int_status = USBFS_ARB_INT_SR_REG; /* read Arbiter Status Register */ + USBFS_ARB_INT_SR_REG = int_status; /* Clear Serviced Interrupts */ + + while(int_status != 0u) + { + if((int_status & 1u) != 0u) /* If EpX interrupt present */ + { /* read Endpoint Status Register */ + ep_status = CY_GET_REG8((reg8 *)(USBFS_ARB_EP1_SR_IND + ptr)); + /* If In Buffer Full */ + if((ep_status & USBFS_ARB_EPX_SR_IN_BUF_FULL) != 0u) + { + if((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u) + { + /* Clear Data ready status */ + *(reg8 *)(USBFS_ARB_EP1_CFG_IND + ptr) &= + (uint8)~USBFS_ARB_EPX_CFG_IN_DATA_RDY; + /* Write the Mode register */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ptr), USBFS_EP[ep].epMode); + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_IN) + if(ep == USBFS_midi_in_ep) + { /* Clear MIDI input pointer */ + USBFS_midiInPointer = 0u; + } + #endif /* End USBFS_ENABLE_MIDI_STREAMING*/ + } + } + /* (re)arm Out EP only for mode2 */ + #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) + /* If DMA Grant */ + if((ep_status & USBFS_ARB_EPX_SR_DMA_GNT) != 0u) + { + if((USBFS_EP[ep].addr & USBFS_DIR_IN) == 0u) + { + USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_PENDING; + /* Write the Mode register */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ptr), + USBFS_EP[ep].epMode); + } + } + #endif /* End USBFS_EP_MM */ + + /* `#START ARB_USER_CODE` Place your code here for handle Buffer Underflow/Overflow */ + + /* `#END` */ + + CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_SR_IND + ptr), ep_status); /* Clear Serviced events */ + } + ptr += USBFS_EPX_CNTX_ADDR_OFFSET; /* prepare pointer for next EP */ + ep++; + int_status >>= 1u; + } + + /* `#START ARB_END_USER_CODE` Place your code here */ + + /* `#END` */ + } + +#endif /* End USBFS_EP_MM */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_hid.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_hid.c new file mode 100755 index 00000000..cc1ea1e2 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_hid.c @@ -0,0 +1,422 @@ +/******************************************************************************* +* File Name: USBFS_hid.c +* Version 2.60 +* +* Description: +* USB HID Class request handler. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS.h" + +#if defined(USBFS_ENABLE_HID_CLASS) + +#include "USBFS_pvt.h" +#include "USBFS_hid.h" + + +/*************************************** +* HID Variables +***************************************/ + +volatile uint8 USBFS_hidProtocol[USBFS_MAX_INTERFACES_NUMBER]; /* HID device protocol status */ +volatile uint8 USBFS_hidIdleRate[USBFS_MAX_INTERFACES_NUMBER]; /* HID device idle reload value */ +volatile uint8 USBFS_hidIdleTimer[USBFS_MAX_INTERFACES_NUMBER]; /* HID device idle rate value */ + + +/*************************************** +* Custom Declarations +***************************************/ + +/* `#START HID_CUSTOM_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +/******************************************************************************* +* Function Name: USBFS_UpdateHIDTimer +******************************************************************************** +* +* Summary: +* Updates the HID report timer and reloads it if expired +* +* Parameters: +* interface: Interface Number. +* +* Return: +* status. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_UpdateHIDTimer(uint8 interface) +{ + uint8 stat = USBFS_IDLE_TIMER_INDEFINITE; + + if(USBFS_hidIdleRate[interface] != 0u) + { + if(USBFS_hidIdleTimer[interface] > 0u) + { + USBFS_hidIdleTimer[interface]--; + stat = USBFS_IDLE_TIMER_RUNNING; + } + else + { + USBFS_hidIdleTimer[interface] = USBFS_hidIdleRate[interface]; + stat = USBFS_IDLE_TIMER_EXPIRED; + } + } + + return(stat); +} + + +/******************************************************************************* +* Function Name: USBFS_GetProtocol +******************************************************************************** +* +* Summary: +* Returns the selected protocol value to the application +* +* Parameters: +* interface: Interface Number. +* +* Return: +* Interface protocol. +* +*******************************************************************************/ +uint8 USBFS_GetProtocol(uint8 interface) +{ + return(USBFS_hidProtocol[interface]); +} + + +/******************************************************************************* +* Function Name: USBFS_DispatchHIDClassRqst +******************************************************************************** +* +* Summary: +* This routine dispatches class requests +* +* Parameters: +* None. +* +* Return: +* requestHandled +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_DispatchHIDClassRqst(void) +{ + uint8 requestHandled = USBFS_FALSE; + uint8 interfaceNumber; + + interfaceNumber = CY_GET_REG8(USBFS_wIndexLo); + if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H) + { /* Control Read */ + switch (CY_GET_REG8(USBFS_bRequest)) + { + case USBFS_GET_DESCRIPTOR: + if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_HID_CLASS) + { + USBFS_FindHidClassDecriptor(); + if (USBFS_currentTD.count != 0u) + { + requestHandled = USBFS_InitControlRead(); + } + } + else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_HID_REPORT) + { + USBFS_FindReportDescriptor(); + if (USBFS_currentTD.count != 0u) + { + requestHandled = USBFS_InitControlRead(); + } + } + else + { /* requestHandled is initialezed as FALSE by default */ + } + break; + case USBFS_HID_GET_REPORT: + USBFS_FindReport(); + if (USBFS_currentTD.count != 0u) + { + requestHandled = USBFS_InitControlRead(); + } + break; + + case USBFS_HID_GET_IDLE: + /* This function does not support multiple reports per interface*/ + /* Validate interfaceNumber and Report ID (should be 0) */ + if( (interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && + (CY_GET_REG8(USBFS_wValueLo) == 0u ) ) /* Do not support Idle per Report ID */ + { + USBFS_currentTD.count = 1u; + USBFS_currentTD.pData = &USBFS_hidIdleRate[interfaceNumber]; + requestHandled = USBFS_InitControlRead(); + } + break; + case USBFS_HID_GET_PROTOCOL: + /* Validate interfaceNumber */ + if( interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) + { + USBFS_currentTD.count = 1u; + USBFS_currentTD.pData = &USBFS_hidProtocol[interfaceNumber]; + requestHandled = USBFS_InitControlRead(); + } + break; + default: /* requestHandled is initialized as FALSE by default */ + break; + } + } + else if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == + USBFS_RQST_DIR_H2D) + { /* Control Write */ + switch (CY_GET_REG8(USBFS_bRequest)) + { + case USBFS_HID_SET_REPORT: + USBFS_FindReport(); + if (USBFS_currentTD.count != 0u) + { + requestHandled = USBFS_InitControlWrite(); + } + break; + case USBFS_HID_SET_IDLE: + /* This function does not support multiple reports per interface */ + /* Validate interfaceNumber and Report ID (should be 0) */ + if( (interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && + (CY_GET_REG8(USBFS_wValueLo) == 0u ) ) /* Do not support Idle per Report ID */ + { + USBFS_hidIdleRate[interfaceNumber] = CY_GET_REG8(USBFS_wValueHi); + /* With regards to HID spec: "7.2.4 Set_Idle Request" + * Latency. If the current period has gone past the + * newly proscribed time duration, then a report + * will be generated immediately. + */ + if(USBFS_hidIdleRate[interfaceNumber] < + USBFS_hidIdleTimer[interfaceNumber]) + { + /* Set the timer to zero and let the UpdateHIDTimer() API return IDLE_TIMER_EXPIRED status*/ + USBFS_hidIdleTimer[interfaceNumber] = 0u; + } + /* If the new request is received within 4 milliseconds + * (1 count) of the end of the current period, then the + * new request will have no effect until after the report. + */ + else if(USBFS_hidIdleTimer[interfaceNumber] <= 1u) + { + /* Do nothing. + * Let the UpdateHIDTimer() API continue to work and + * return IDLE_TIMER_EXPIRED status + */ + } + else + { /* Reload the timer*/ + USBFS_hidIdleTimer[interfaceNumber] = + USBFS_hidIdleRate[interfaceNumber]; + } + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + + case USBFS_HID_SET_PROTOCOL: + /* Validate interfaceNumber and protocol (must be 0 or 1) */ + if( (interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && + (CY_GET_REG8(USBFS_wValueLo) <= 1u) ) + { + USBFS_hidProtocol[interfaceNumber] = CY_GET_REG8(USBFS_wValueLo); + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + default: /* requestHandled is initialized as FALSE by default */ + break; + } + } + else + { /* requestHandled is initialized as FALSE by default */ + } + + return(requestHandled); +} + + +/******************************************************************************* +* Function Name: USB_FindHidClassDescriptor +******************************************************************************** +* +* Summary: +* This routine find Hid Class Descriptor pointer based on the Interface number +* and Alternate setting then loads the currentTD structure with the address of +* the buffer and the size. +* The HID Class Descriptor resides inside the config descriptor. +* +* Parameters: +* None. +* +* Return: +* currentTD +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_FindHidClassDecriptor(void) +{ + const T_USBFS_LUT CYCODE *pTmp; + volatile uint8 *pDescr; + uint8 interfaceN; + + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + interfaceN = CY_GET_REG8(USBFS_wIndexLo); + /* Third entry in the LUT starts the Interface Table pointers */ + /* Now use the request interface number*/ + pTmp = &pTmp[interfaceN + 2u]; + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE */ + pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + /* Now use Alternate setting number */ + pTmp = &pTmp[USBFS_interfaceSetting[interfaceN]]; + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_ALTERNATEi_HID_TABLE */ + pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + /* Fifth entry in the LUT points to Hid Class Descriptor in Configuration Descriptor */ + pTmp = &pTmp[4u]; + pDescr = (volatile uint8 *)pTmp->p_list; + /* The first byte contains the descriptor length */ + USBFS_currentTD.count = *pDescr; + USBFS_currentTD.pData = pDescr; +} + + +/******************************************************************************* +* Function Name: USB_FindReportDescriptor +******************************************************************************** +* +* Summary: +* This routine find Hid Report Descriptor pointer based on the Interface +* number, then loads the currentTD structure with the address of the buffer +* and the size. +* Hid Report Descriptor is located after IN/OUT/FEATURE reports. +* +* Parameters: +* void +* +* Return: +* currentTD +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_FindReportDescriptor(void) +{ + const T_USBFS_LUT CYCODE *pTmp; + volatile uint8 *pDescr; + uint8 interfaceN; + + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + interfaceN = CY_GET_REG8(USBFS_wIndexLo); + /* Third entry in the LUT starts the Interface Table pointers */ + /* Now use the request interface number */ + pTmp = &pTmp[interfaceN + 2u]; + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE */ + pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + /* Now use Alternate setting number */ + pTmp = &pTmp[USBFS_interfaceSetting[interfaceN]]; + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_ALTERNATEi_HID_TABLE */ + pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + /* Fourth entry in the LUT starts the Hid Report Descriptor */ + pTmp = &pTmp[3u]; + pDescr = (volatile uint8 *)pTmp->p_list; + /* The 1st and 2nd bytes of descriptor contain its length. LSB is 1st. */ + USBFS_currentTD.count = (((uint16)pDescr[1u] << 8u) | pDescr[0u]); + USBFS_currentTD.pData = &pDescr[2u]; +} + + +/******************************************************************************* +* Function Name: USBFS_FindReport +******************************************************************************** +* +* Summary: +* This routine sets up a transfer based on the Interface number, Report Type +* and Report ID, then loads the currentTD structure with the address of the +* buffer and the size. The caller has to decide if it is a control read or +* control write. +* +* Parameters: +* None. +* +* Return: +* currentTD +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_FindReport(void) +{ + const T_USBFS_LUT CYCODE *pTmp; + T_USBFS_TD *pTD; + uint8 interfaceN; + uint8 reportType; + + /* `#START HID_FINDREPORT` Place custom handling here */ + + /* `#END` */ + USBFS_currentTD.count = 0u; /* Init not supported condition */ + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + reportType = CY_GET_REG8(USBFS_wValueHi); + interfaceN = CY_GET_REG8(USBFS_wIndexLo); + /* Third entry in the LUT COnfiguration Table starts the Interface Table pointers */ + /* Now use the request interface number */ + pTmp = &pTmp[interfaceN + 2u]; + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE*/ + pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + if(interfaceN < USBFS_MAX_INTERFACES_NUMBER) + { + /* Now use Alternate setting number */ + pTmp = &pTmp[USBFS_interfaceSetting[interfaceN]]; + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_ALTERNATEi_HID_TABLE */ + pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + /* Validate reportType to comply with "7.2.1 Get_Report Request" */ + if((reportType >= USBFS_HID_GET_REPORT_INPUT) && + (reportType <= USBFS_HID_GET_REPORT_FEATURE)) + { + /* Get the entry proper TD (IN, OUT or Feature Report Table)*/ + pTmp = &pTmp[reportType - 1u]; + reportType = CY_GET_REG8(USBFS_wValueLo); /* Get reportID */ + /* Validate table support by the HID descriptor, compare table count with reportID */ + if(pTmp->c >= reportType) + { + pTD = (T_USBFS_TD *) pTmp->p_list; + pTD = &pTD[reportType]; /* select entry depend on report ID*/ + USBFS_currentTD.pData = pTD->pData; /* Buffer pointer */ + USBFS_currentTD.count = pTD->count; /* Buffer Size */ + USBFS_currentTD.pStatusBlock = pTD->pStatusBlock; + } + } + } +} + + +/******************************************************************************* +* Additional user functions supporting HID Requests +********************************************************************************/ + +/* `#START HID_FUNCTIONS` Place any additional functions here */ + +/* `#END` */ + +#endif /* End USBFS_ENABLE_HID_CLASS */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_hid.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_hid.h new file mode 100755 index 00000000..a34e4e73 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_hid.h @@ -0,0 +1,64 @@ +/******************************************************************************* +* File Name: USBFS_hid.h +* Version 2.60 +* +* Description: +* Header File for the USFS component. Contains prototypes and constant values. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_USBFS_USBFS_hid_H) +#define CY_USBFS_USBFS_hid_H + +#include "cytypes.h" + + +/*************************************** +* Prototypes of the USBFS_hid API. +***************************************/ + +uint8 USBFS_UpdateHIDTimer(uint8 interface) ; +uint8 USBFS_GetProtocol(uint8 interface) ; + + +/*************************************** +*Renamed Functions for backward compatible +***************************************/ + +#define USBFS_bGetProtocol USBFS_GetProtocol + + +/*************************************** +* Constants for USBFS_hid API. +***************************************/ + +#define USBFS_PROTOCOL_BOOT (0x00u) +#define USBFS_PROTOCOL_REPORT (0x01u) + +/* Request Types (HID Chapter 7.2) */ +#define USBFS_HID_GET_REPORT (0x01u) +#define USBFS_HID_GET_IDLE (0x02u) +#define USBFS_HID_GET_PROTOCOL (0x03u) +#define USBFS_HID_SET_REPORT (0x09u) +#define USBFS_HID_SET_IDLE (0x0Au) +#define USBFS_HID_SET_PROTOCOL (0x0Bu) + +/* Descriptor Types (HID Chapter 7.1) */ +#define USBFS_DESCR_HID_CLASS (0x21u) +#define USBFS_DESCR_HID_REPORT (0x22u) +#define USBFS_DESCR_HID_PHYSICAL (0x23u) + +/* Report Request Types (HID Chapter 7.2.1) */ +#define USBFS_HID_GET_REPORT_INPUT (0x01u) +#define USBFS_HID_GET_REPORT_OUTPUT (0x02u) +#define USBFS_HID_GET_REPORT_FEATURE (0x03u) + +#endif /* End CY_USBFS_USBFS_hid_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_midi.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_midi.c new file mode 100755 index 00000000..0247caf2 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_midi.c @@ -0,0 +1,1341 @@ +/******************************************************************************* +* File Name: USBFS_midi.c +* Version 2.60 +* +* Description: +* MIDI Streaming request handler. +* This file contains routines for sending and receiving MIDI +* messages, and handles running status in both directions. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS.h" + +#if defined(USBFS_ENABLE_MIDI_STREAMING) + +#include "USBFS_midi.h" +#include "USBFS_pvt.h" + + +/*************************************** +* MIDI Constants +***************************************/ + +#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + /* The Size of the MIDI messages (MIDI Table 4-1) */ + static const uint8 CYCODE USBFS_MIDI_SIZE[] = { + /* Miscellaneous function codes(Reserved) */ 0x03u, + /* Cable events (Reserved) */ 0x03u, + /* Two-byte System Common messages */ 0x02u, + /* Three-byte System Common messages */ 0x03u, + /* SysEx starts or continues */ 0x03u, + /* Single-byte System Common Message or + SysEx ends with following single byte */ 0x01u, + /* SysEx ends with following two bytes */ 0x02u, + /* SysEx ends with following three bytes */ 0x03u, + /* Note-off */ 0x03u, + /* Note-on */ 0x03u, + /* Poly-KeyPress */ 0x03u, + /* Control Change */ 0x03u, + /* Program Change */ 0x02u, + /* Channel Pressure */ 0x02u, + /* PitchBend Change */ 0x03u, + /* Single Byte */ 0x01u + }; +#endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ + + + +/*************************************** +* Global variables +***************************************/ + +#if (USBFS_MIDI_IN_BUFF_SIZE > 0) + #if (USBFS_MIDI_IN_BUFF_SIZE >= 256) + volatile uint16 USBFS_midiInPointer; /* Input endpoint buffer pointer */ + #else + volatile uint8 USBFS_midiInPointer; /* Input endpoint buffer pointer */ + #endif /* End USBFS_MIDI_IN_BUFF_SIZE >=256 */ + volatile uint8 USBFS_midi_in_ep; /* Input endpoint number */ + uint8 USBFS_midiInBuffer[USBFS_MIDI_IN_BUFF_SIZE]; /* Input endpoint buffer */ +#endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */ + +#if (USBFS_MIDI_OUT_BUFF_SIZE > 0) + volatile uint8 USBFS_midi_out_ep; /* Output endpoint number */ + uint8 USBFS_midiOutBuffer[USBFS_MIDI_OUT_BUFF_SIZE]; /* Output endpoint buffer */ +#endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */ + +#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + static USBFS_MIDI_RX_STATUS USBFS_MIDI1_Event; /* MIDI RX status structure */ + static volatile uint8 USBFS_MIDI1_TxRunStat; /* MIDI Output running status */ + volatile uint8 USBFS_MIDI1_InqFlags; /* Device inquiry flag */ + + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + static USBFS_MIDI_RX_STATUS USBFS_MIDI2_Event; /* MIDI RX status structure */ + static volatile uint8 USBFS_MIDI2_TxRunStat; /* MIDI Output running status */ + volatile uint8 USBFS_MIDI2_InqFlags; /* Device inquiry flag */ + #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ +#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ + + +/*************************************** +* Custom Declarations +***************************************/ + +/* `#START MIDI_CUSTOM_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +/*************************************** +* Optional MIDI APIs +***************************************/ +#if (USBFS_ENABLE_MIDI_API != 0u) + + +/******************************************************************************* +* Function Name: USBFS_MIDI_EP_Init +******************************************************************************** +* +* Summary: +* This function initializes the MIDI interface and UART(s) to be ready to +* receive data from the PC and MIDI ports. +* +* Parameters: +* None +* +* Return: +* None +* +* Global variables: +* USBFS_midiInBuffer: This buffer is used for saving and combining +* the received data from UART(s) and(or) generated internally by +* PutUsbMidiIn() function messages. USBFS_MIDI_IN_EP_Service() +* function transfers the data from this buffer to the PC. +* USBFS_midiOutBuffer: This buffer is used by the +* USBFS_MIDI_OUT_EP_Service() function for saving the received +* from the PC data, then the data are parsed and transferred to UART(s) +* buffer and to the internal processing by the +* USBFS_callbackLocalMidiEvent function. +* USBFS_midi_out_ep: Used as an OUT endpoint number. +* USBFS_midi_in_ep: Used as an IN endpoint number. +* USBFS_midiInPointer: Initialized to zero. +* +* Reentrant: +* No +* +*******************************************************************************/ +void USBFS_MIDI_EP_Init(void) +{ + #if (USBFS_MIDI_IN_BUFF_SIZE > 0) + USBFS_midiInPointer = 0u; + #endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */ + + #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + #if (USBFS_MIDI_IN_BUFF_SIZE > 0) + /* Init DMA configurations for IN EP*/ + USBFS_LoadInEP(USBFS_midi_in_ep, USBFS_midiInBuffer, + USBFS_MIDI_IN_BUFF_SIZE); + + #endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */ + #if (USBFS_MIDI_OUT_BUFF_SIZE > 0) + /* Init DMA configurations for OUT EP*/ + (void)USBFS_ReadOutEP(USBFS_midi_out_ep, USBFS_midiOutBuffer, + USBFS_MIDI_OUT_BUFF_SIZE); + #endif /*USBFS_MIDI_OUT_BUFF_SIZE > 0 */ + #endif /* End USBFS__EP_DMAAUTO */ + + #if (USBFS_MIDI_OUT_BUFF_SIZE > 0) + USBFS_EnableOutEP(USBFS_midi_out_ep); + #endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */ + + /* Initialize the MIDI port(s) */ + #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + USBFS_MIDI_Init(); + #endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ +} + +#if (USBFS_MIDI_OUT_BUFF_SIZE > 0) + + + /******************************************************************************* + * Function Name: USBFS_MIDI_OUT_EP_Service + ******************************************************************************** + * + * Summary: + * Services the USB MIDI OUT endpoints. + * This function is called from OUT EP ISR. It transfers the received from PC + * data to the external MIDI port(UART TX buffer) and calls the + * USBFS_callbackLocalMidiEvent() function to internal process + * of the MIDI data. + * This function is blocked by UART, if not enough space is available in UART + * TX buffer. Therefore it is recommended to use large UART TX buffer size. + * + * Parameters: + * None + * + * Return: + * None + * + * Global variables: + * USBFS_midiOutBuffer: Used as temporary buffer between USB internal + * memory and UART TX buffer. + * USBFS_midi_out_ep: Used as an OUT endpoint number. + * + * Reentrant: + * No + * + *******************************************************************************/ + void USBFS_MIDI_OUT_EP_Service(void) + { + #if USBFS_MIDI_OUT_BUFF_SIZE >= 256 + uint16 outLength; + uint16 outPointer; + #else + uint8 outLength; + uint8 outPointer; + #endif /* End USBFS_MIDI_OUT_BUFF_SIZE >=256 */ + + uint8 dmaState = 0u; + + /* Service the USB MIDI output endpoint */ + if (USBFS_GetEPState(USBFS_midi_out_ep) == USBFS_OUT_BUFFER_FULL) + { + #if USBFS_MIDI_OUT_BUFF_SIZE >= 256 + outLength = USBFS_GetEPCount(USBFS_midi_out_ep); + #else + outLength = (uint8)USBFS_GetEPCount(USBFS_midi_out_ep); + #endif /* End USBFS_MIDI_OUT_BUFF_SIZE >= 256 */ + #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) + #if USBFS_MIDI_OUT_BUFF_SIZE >= 256 + outLength = USBFS_ReadOutEP(USBFS_midi_out_ep, + USBFS_midiOutBuffer, outLength); + #else + outLength = (uint8)USBFS_ReadOutEP(USBFS_midi_out_ep, + USBFS_midiOutBuffer, (uint16)outLength); + #endif /* End USBFS_MIDI_OUT_BUFF_SIZE >= 256 */ + #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL) + do /* wait for DMA transfer complete */ + { + (void)CyDmaChStatus(USBFS_DmaChan[USBFS_midi_out_ep], NULL, &dmaState); + }while((dmaState & (STATUS_TD_ACTIVE | STATUS_CHAIN_ACTIVE)) != 0u); + #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */ + #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */ + if(dmaState != 0u) + { + /* Suppress compiler warning */ + } + if (outLength >= USBFS_EVENT_LENGTH) + { + outPointer = 0u; + while (outPointer < outLength) + { + /* In some OS OUT packet could be appended by nulls which could be skipped */ + if (USBFS_midiOutBuffer[outPointer] == 0u) + { + break; + } + /* Route USB MIDI to the External connection */ + #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + if ((USBFS_midiOutBuffer[outPointer] & USBFS_CABLE_MASK) == + USBFS_MIDI_CABLE_00) + { + USBFS_MIDI1_ProcessUsbOut(&USBFS_midiOutBuffer[outPointer]); + } + else if ((USBFS_midiOutBuffer[outPointer] & USBFS_CABLE_MASK) == + USBFS_MIDI_CABLE_01) + { + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + USBFS_MIDI2_ProcessUsbOut(&USBFS_midiOutBuffer[outPointer]); + #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ + } + else + { + /* `#START CUSTOM_MIDI_OUT_EP_SERV` Place your code here */ + + /* `#END` */ + } + #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ + + /* Process any local MIDI output functions */ + USBFS_callbackLocalMidiEvent( + USBFS_midiOutBuffer[outPointer] & USBFS_CABLE_MASK, + &USBFS_midiOutBuffer[outPointer + USBFS_EVENT_BYTE1]); + outPointer += USBFS_EVENT_LENGTH; + } + } + #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + /* Enable Out EP*/ + USBFS_EnableOutEP(USBFS_midi_out_ep); + #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ + } + } + +#endif /* #if (USBFS_MIDI_OUT_BUFF_SIZE > 0) */ + +#if (USBFS_MIDI_IN_BUFF_SIZE > 0) + + + /******************************************************************************* + * Function Name: USBFS_MIDI_IN_EP_Service + ******************************************************************************** + * + * Summary: + * Services the USB MIDI IN endpoint. Non-blocking. + * Checks that previous packet was processed by HOST, otherwise service the + * input endpoint on the subsequent call. It is called from the + * USBFS_MIDI_IN_Service() and from the + * USBFS_PutUsbMidiIn() function. + * + * Parameters: + * None + * + * Return: + * None + * + * Global variables: + * USBFS_midi_in_ep: Used as an IN endpoint number. + * USBFS_midiInBuffer: Function loads the data from this buffer to + * the USB IN endpoint. + * USBFS_midiInPointer: Cleared to zero when data are sent. + * + * Reentrant: + * No + * + *******************************************************************************/ + void USBFS_MIDI_IN_EP_Service(void) + { + /* Service the USB MIDI input endpoint */ + /* Check that previous packet was processed by HOST, otherwise service the USB later */ + if (USBFS_midiInPointer != 0u) + { + if(USBFS_GetEPState(USBFS_midi_in_ep) == USBFS_EVENT_PENDING) + { + #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) + USBFS_LoadInEP(USBFS_midi_in_ep, USBFS_midiInBuffer, + (uint16)USBFS_midiInPointer); + #else /* USBFS_EP_MM != USBFS__EP_DMAAUTO */ + /* rearm IN EP */ + USBFS_LoadInEP(USBFS_midi_in_ep, NULL, (uint16)USBFS_midiInPointer); + #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO*/ + + /* Clear the midiInPointer. For DMA mode, clear this pointer in the ARB ISR when data are moved by DMA */ + #if(USBFS_EP_MM == USBFS__EP_MANUAL) + USBFS_midiInPointer = 0u; + #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */ + } + } + } + + + /******************************************************************************* + * Function Name: USBFS_MIDI_IN_Service + ******************************************************************************** + * + * Summary: + * Services the traffic from the MIDI input ports (RX UART) and prepare data + * in USB MIDI IN endpoint buffer. + * Calls the USBFS_MIDI_IN_EP_Service() function to sent the + * data from buffer to PC. Non-blocking. Should be called from main foreground + * task. + * This function is not protected from the reentrant calls. When it is required + * to use this function in UART RX ISR to guaranty low latency, care should be + * taken to protect from reentrant calls. + * + * Parameters: + * None + * + * Return: + * None + * + * Global variables: + * USBFS_midiInPointer: Cleared to zero when data are sent. + * + * Reentrant: + * No + * + *******************************************************************************/ + void USBFS_MIDI_IN_Service(void) + { + /* Service the MIDI UART inputs until either both receivers have no more + * events or until the input endpoint buffer fills up. + */ + #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + uint8 m1 = 0u; + uint8 m2 = 0u; + do + { + if (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH)) + { + /* Check MIDI1 input port for a complete event */ + m1 = USBFS_MIDI1_GetEvent(); + if (m1 != 0u) + { + USBFS_PrepareInBuffer(m1, (uint8 *)&USBFS_MIDI1_Event.msgBuff[0], + USBFS_MIDI1_Event.size, USBFS_MIDI_CABLE_00); + } + } + + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + if (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH)) + { + /* Check MIDI2 input port for a complete event */ + m2 = USBFS_MIDI2_GetEvent(); + if (m2 != 0u) + { + USBFS_PrepareInBuffer(m2, (uint8 *)&USBFS_MIDI2_Event.msgBuff[0], + USBFS_MIDI2_Event.size, USBFS_MIDI_CABLE_01); + } + } + #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ + + }while( (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH)) + && ((m1 != 0u) || (m2 != 0u)) ); + #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ + + /* Service the USB MIDI input endpoint */ + USBFS_MIDI_IN_EP_Service(); + } + + + /******************************************************************************* + * Function Name: USBFS_PutUsbMidiIn + ******************************************************************************** + * + * Summary: + * Puts one MIDI messages into the USB MIDI In endpoint buffer. These are + * MIDI input messages to the host. This function is only used if the device + * has internal MIDI input functionality. USBMIDI_MIDI_IN_Service() function + * should additionally be called to send the message from local buffer to + * IN endpoint. + * + * Parameters: + * ic: 0 = No message (should never happen) + * 1 - 3 = Complete MIDI message in midiMsg + * 3 - IN EP LENGTH = Complete SySEx message(without EOSEX byte) in + * midiMsg. The length is limited by the max BULK EP size(64) + * MIDI_SYSEX = Start or continuation of SysEx message + * (put event bytes in midiMsg buffer) + * MIDI_EOSEX = End of SysEx message + * (put event bytes in midiMsg buffer) + * MIDI_TUNEREQ = Tune Request message (single byte system common msg) + * 0xf8 - 0xff = Single byte real-time message + * midiMsg: pointer to MIDI message. + * cable: cable number. + * + * Return: + * USBFS_TRUE if error. + * USBFS_FALSE if success. + * + * Global variables: + * USBFS_midi_in_ep: MIDI IN endpoint number used for sending data. + * USBFS_midiInPointer: Checked this variable to see if there is + * enough free space in the IN endpoint buffer. If buffer is full, initiate + * sending to PC. + * + * Reentrant: + * No + * + *******************************************************************************/ + uint8 USBFS_PutUsbMidiIn(uint8 ic, const uint8 midiMsg[], uint8 cable) + + { + uint8 retError = USBFS_FALSE; + uint8 msgIndex; + + /* Protect PrepareInBuffer() function from concurrent calls */ + #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + MIDI1_UART_DisableRxInt(); + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + MIDI2_UART_DisableRxInt(); + #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ + #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ + + if (USBFS_midiInPointer > + (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH)) + { + USBFS_MIDI_IN_EP_Service(); + } + if (USBFS_midiInPointer <= + (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH)) + { + if((ic < USBFS_EVENT_LENGTH) || (ic >= USBFS_MIDI_STATUS_MASK)) + { + USBFS_PrepareInBuffer(ic, midiMsg, ic, cable); + } + else + { /* Only SysEx message is greater than 4 bytes */ + msgIndex = 0u; + do + { + USBFS_PrepareInBuffer(USBFS_MIDI_SYSEX, &midiMsg[msgIndex], + USBFS_EVENT_BYTE3, cable); + ic -= USBFS_EVENT_BYTE3; + msgIndex += USBFS_EVENT_BYTE3; + if (USBFS_midiInPointer > + (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH)) + { + USBFS_MIDI_IN_EP_Service(); + if (USBFS_midiInPointer > + (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH)) + { + /* Error condition. HOST is not ready to receive this packet. */ + retError = USBFS_TRUE; + break; + } + } + }while(ic > USBFS_EVENT_BYTE3); + + if(retError == USBFS_FALSE) + { + USBFS_PrepareInBuffer(USBFS_MIDI_EOSEX, midiMsg, ic, cable); + } + } + } + else + { + /* Error condition. HOST is not ready to receive this packet. */ + retError = USBFS_TRUE; + } + + #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + MIDI1_UART_EnableRxInt(); + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + MIDI2_UART_EnableRxInt(); + #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ + #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ + + return (retError); + } + + + /******************************************************************************* + * Function Name: USBFS_PrepareInBuffer + ******************************************************************************** + * + * Summary: + * Builds a USB MIDI event in the input endpoint buffer at the current pointer. + * Puts one MIDI message into the USB MIDI In endpoint buffer. + * + * Parameters: + * ic: 0 = No message (should never happen) + * 1 - 3 = Complete MIDI message at pMdat[0] + * MIDI_SYSEX = Start or continuation of SysEx message + * (put eventLen bytes in buffer) + * MIDI_EOSEX = End of SysEx message + * (put eventLen bytes in buffer, + * and append MIDI_EOSEX) + * MIDI_TUNEREQ = Tune Request message (single byte system common msg) + * 0xf8 - 0xff = Single byte real-time message + * + * srcBuff: pointer to MIDI data + * eventLen: number of bytes in MIDI event + * cable: MIDI source port number + * + * Return: + * None + * + * Global variables: + * USBFS_midiInBuffer: This buffer is used for saving and combine the + * received from UART(s) and(or) generated internally by + * USBFS_PutUsbMidiIn() function messages. + * USBFS_midiInPointer: Used as an index for midiInBuffer to + * write data. + * + * Reentrant: + * No + * + *******************************************************************************/ + void USBFS_PrepareInBuffer(uint8 ic, const uint8 srcBuff[], uint8 eventLen, uint8 cable) + + { + uint8 srcBuffZero; + uint8 srcBuffOne; + + srcBuffZero = srcBuff[0u]; + srcBuffOne = srcBuff[1u]; + + if (ic >= (USBFS_MIDI_STATUS_MASK | USBFS_MIDI_SINGLE_BYTE_MASK)) + { + USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_SINGLE_BYTE | cable; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = ic; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = 0u; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = 0u; + USBFS_midiInPointer++; + } + else if((ic < USBFS_EVENT_LENGTH) || (ic == USBFS_MIDI_SYSEX)) + { + if(ic == USBFS_MIDI_SYSEX) + { + USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_SYSEX | cable; + USBFS_midiInPointer++; + } + else if (srcBuffZero < USBFS_MIDI_SYSEX) + { + USBFS_midiInBuffer[USBFS_midiInPointer] = (srcBuffZero >> 4u) | cable; + USBFS_midiInPointer++; + } + else if (srcBuffZero == USBFS_MIDI_TUNEREQ) + { + USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_1BYTE_COMMON | cable; + USBFS_midiInPointer++; + } + else if ((srcBuffZero == USBFS_MIDI_QFM) || (srcBuffZero == USBFS_MIDI_SONGSEL)) + { + USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_2BYTE_COMMON | cable; + USBFS_midiInPointer++; + } + else if (srcBuffZero == USBFS_MIDI_SPP) + { + USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_3BYTE_COMMON | cable; + USBFS_midiInPointer++; + } + else + { + } + + USBFS_midiInBuffer[USBFS_midiInPointer] = srcBuffZero; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = srcBuffOne; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = srcBuff[2u]; + USBFS_midiInPointer++; + } + else if (ic == USBFS_MIDI_EOSEX) + { + switch (eventLen) + { + case 0u: + USBFS_midiInBuffer[USBFS_midiInPointer] = + USBFS_SYSEX_ENDS_WITH1 | cable; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_MIDI_EOSEX; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = 0u; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = 0u; + USBFS_midiInPointer++; + break; + case 1u: + USBFS_midiInBuffer[USBFS_midiInPointer] = + USBFS_SYSEX_ENDS_WITH2 | cable; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = srcBuffZero; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_MIDI_EOSEX; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = 0u; + USBFS_midiInPointer++; + break; + case 2u: + USBFS_midiInBuffer[USBFS_midiInPointer] = + USBFS_SYSEX_ENDS_WITH3 | cable; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = srcBuffZero; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = srcBuffOne; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_MIDI_EOSEX; + USBFS_midiInPointer++; + break; + default: + break; + } + } + else + { + } + } + +#endif /* #if (USBFS_MIDI_IN_BUFF_SIZE > 0) */ + + +/* The implementation for external serial input and output connections +* to route USB MIDI data to and from those connections. +*/ +#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + + + /******************************************************************************* + * Function Name: USBFS_MIDI_Init + ******************************************************************************** + * + * Summary: + * Initializes MIDI variables and starts the UART(s) hardware block(s). + * + * Parameters: + * None + * + * Return: + * None + * + * Side Effects: + * Change the priority of the UART(s) TX interrupts to be higher than the + * default EP ISR priority. + * + * Global variables: + * USBFS_MIDI_Event: initialized to zero. + * USBFS_MIDI_TxRunStat: initialized to zero. + * + *******************************************************************************/ + void USBFS_MIDI_Init(void) + { + USBFS_MIDI1_Event.length = 0u; + USBFS_MIDI1_Event.count = 0u; + USBFS_MIDI1_Event.size = 0u; + USBFS_MIDI1_Event.runstat = 0u; + USBFS_MIDI1_TxRunStat = 0u; + USBFS_MIDI1_InqFlags = 0u; + /* Start UART block */ + MIDI1_UART_Start(); + /* Change the priority of the UART TX and RX interrupt */ + CyIntSetPriority(MIDI1_UART_TX_VECT_NUM, USBFS_CUSTOM_UART_TX_PRIOR_NUM); + CyIntSetPriority(MIDI1_UART_RX_VECT_NUM, USBFS_CUSTOM_UART_RX_PRIOR_NUM); + + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + USBFS_MIDI2_Event.length = 0u; + USBFS_MIDI2_Event.count = 0u; + USBFS_MIDI2_Event.size = 0u; + USBFS_MIDI2_Event.runstat = 0u; + USBFS_MIDI2_TxRunStat = 0u; + USBFS_MIDI2_InqFlags = 0u; + /* Start second UART block */ + MIDI2_UART_Start(); + /* Change the priority of the UART TX interrupt */ + CyIntSetPriority(MIDI2_UART_TX_VECT_NUM, USBFS_CUSTOM_UART_TX_PRIOR_NUM); + CyIntSetPriority(MIDI2_UART_RX_VECT_NUM, USBFS_CUSTOM_UART_RX_PRIOR_NUM); + #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF*/ + + /* `#START MIDI_INIT_CUSTOM` Init other extended UARTs here */ + + /* `#END` */ + + } + + + /******************************************************************************* + * Function Name: USBFS_ProcessMidiIn + ******************************************************************************** + * + * Summary: + * Processes one byte of incoming MIDI data. + * + * Parameters: + * mData = current MIDI input data byte + * *rxStat = pointer to a MIDI_RX_STATUS structure + * + * Return: + * 0, if no complete message + * 1 - 4, if message complete + * MIDI_SYSEX, if start or continuation of system exclusive + * MIDI_EOSEX, if end of system exclusive + * 0xf8 - 0xff, if single byte real time message + * + *******************************************************************************/ + uint8 USBFS_ProcessMidiIn(uint8 mData, USBFS_MIDI_RX_STATUS *rxStat) + + { + uint8 midiReturn = 0u; + + /* Check for a MIDI status byte. All status bytes, except real time messages, + * which are a single byte, force the start of a new buffer cycle. + */ + if ((mData & USBFS_MIDI_STATUS_BYTE_MASK) != 0u) + { + if ((mData & USBFS_MIDI_STATUS_MASK) == USBFS_MIDI_STATUS_MASK) + { + if ((mData & USBFS_MIDI_SINGLE_BYTE_MASK) != 0u) /* System Real-Time Messages(single byte) */ + { + midiReturn = mData; + } + else /* System Common Messages */ + { + switch (mData) + { + case USBFS_MIDI_SYSEX: + rxStat->msgBuff[0u] = USBFS_MIDI_SYSEX; + rxStat->runstat = USBFS_MIDI_SYSEX; + rxStat->count = 1u; + rxStat->length = 3u; + break; + case USBFS_MIDI_EOSEX: + rxStat->runstat = 0u; + rxStat->size = rxStat->count; + rxStat->count = 0u; + midiReturn = USBFS_MIDI_EOSEX; + break; + case USBFS_MIDI_SPP: + rxStat->msgBuff[0u] = USBFS_MIDI_SPP; + rxStat->runstat = 0u; + rxStat->count = 1u; + rxStat->length = 3u; + break; + case USBFS_MIDI_SONGSEL: + rxStat->msgBuff[0u] = USBFS_MIDI_SONGSEL; + rxStat->runstat = 0u; + rxStat->count = 1u; + rxStat->length = 2u; + break; + case USBFS_MIDI_QFM: + rxStat->msgBuff[0u] = USBFS_MIDI_QFM; + rxStat->runstat = 0u; + rxStat->count = 1u; + rxStat->length = 2u; + break; + case USBFS_MIDI_TUNEREQ: + rxStat->msgBuff[0u] = USBFS_MIDI_TUNEREQ; + rxStat->runstat = 0u; + rxStat->size = 1u; + rxStat->count = 0u; + midiReturn = rxStat->size; + break; + default: + break; + } + } + } + else /* Channel Messages */ + { + rxStat->msgBuff[0u] = mData; + rxStat->runstat = mData; + rxStat->count = 1u; + switch (mData & USBFS_MIDI_STATUS_MASK) + { + case USBFS_MIDI_NOTE_OFF: + case USBFS_MIDI_NOTE_ON: + case USBFS_MIDI_POLY_KEY_PRESSURE: + case USBFS_MIDI_CONTROL_CHANGE: + case USBFS_MIDI_PITCH_BEND_CHANGE: + rxStat->length = 3u; + break; + case USBFS_MIDI_PROGRAM_CHANGE: + case USBFS_MIDI_CHANNEL_PRESSURE: + rxStat->length = 2u; + break; + default: + rxStat->runstat = 0u; + rxStat->count = 0u; + break; + } + } + } + + /* Otherwise, it's a data byte */ + else + { + if (rxStat->runstat == USBFS_MIDI_SYSEX) + { + rxStat->msgBuff[rxStat->count] = mData; + rxStat->count++; + if (rxStat->count >= rxStat->length) + { + rxStat->size = rxStat->count; + rxStat->count = 0u; + midiReturn = USBFS_MIDI_SYSEX; + } + } + else if (rxStat->count > 0u) + { + rxStat->msgBuff[rxStat->count] = mData; + rxStat->count++; + if (rxStat->count >= rxStat->length) + { + rxStat->size = rxStat->count; + rxStat->count = 0u; + midiReturn = rxStat->size; + } + } + else if (rxStat->runstat != 0u) + { + rxStat->msgBuff[0u] = rxStat->runstat; + rxStat->msgBuff[1u] = mData; + rxStat->count = 2u; + switch (rxStat->runstat & USBFS_MIDI_STATUS_MASK) + { + case USBFS_MIDI_NOTE_OFF: + case USBFS_MIDI_NOTE_ON: + case USBFS_MIDI_POLY_KEY_PRESSURE: + case USBFS_MIDI_CONTROL_CHANGE: + case USBFS_MIDI_PITCH_BEND_CHANGE: + rxStat->length = 3u; + break; + case USBFS_MIDI_PROGRAM_CHANGE: + case USBFS_MIDI_CHANNEL_PRESSURE: + rxStat->size =rxStat->count; + rxStat->count = 0u; + midiReturn = rxStat->size; + break; + default: + rxStat->count = 0u; + break; + } + } + else + { + } + } + return (midiReturn); + } + + + /******************************************************************************* + * Function Name: USBFS_MIDI1_GetEvent + ******************************************************************************** + * + * Summary: + * Checks for incoming MIDI data, calls the MIDI event builder if so. + * Returns either empty or with a complete event. + * + * Parameters: + * None + * + * Return: + * 0, if no complete message + * 1 - 4, if message complete + * MIDI_SYSEX, if start or continuation of system exclusive + * MIDI_EOSEX, if end of system exclusive + * 0xf8 - 0xff, if single byte real time message + * + * Global variables: + * USBFS_MIDI1_Event: RX status structure used to parse received + * data. + * + *******************************************************************************/ + uint8 USBFS_MIDI1_GetEvent(void) + { + uint8 msgRtn = 0u; + uint8 rxData; + #if (MIDI1_UART_RXBUFFERSIZE >= 256u) + uint16 rxBufferRead; + #if CY_PSOC3 /* This local variable is required only for PSOC3 and large buffer */ + uint16 rxBufferWrite; + #endif /* end CY_PSOC3 */ + #else + uint8 rxBufferRead; + #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */ + uint8 rxBufferLoopDetect; + /* Read buffer loop condition to the local variable */ + rxBufferLoopDetect = MIDI1_UART_rxBufferLoopDetect; + + if ( (MIDI1_UART_rxBufferRead != MIDI1_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u) ) + { + /* Protect variables that could change on interrupt by disabling Rx interrupt.*/ + #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntDisable(MIDI1_UART_RX_VECT_NUM); + #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */ + rxBufferRead = MIDI1_UART_rxBufferRead; + #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + rxBufferWrite = MIDI1_UART_rxBufferWrite; + CyIntEnable(MIDI1_UART_RX_VECT_NUM); + #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */ + + /* Stay here until either the buffer is empty or we have a complete message + * in the message buffer. Note that we must use a temporary buffer pointer + * since it takes two instructions to increment with a wrap, and we can't + * risk doing that with the real pointer and getting an interrupt in between + * instructions. + */ + + #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + while ( ((rxBufferRead != rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) ) + #else + while ( ((rxBufferRead != MIDI1_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) ) + #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 && CY_PSOC3 */ + { + rxData = MIDI1_UART_rxBuffer[rxBufferRead]; + /* Increment pointer with a wrap */ + rxBufferRead++; + if(rxBufferRead >= MIDI1_UART_RXBUFFERSIZE) + { + rxBufferRead = 0u; + } + /* If loop condition was set - update real read buffer pointer + * to avoid overflow status + */ + if(rxBufferLoopDetect != 0u ) + { + MIDI1_UART_rxBufferLoopDetect = 0u; + #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntDisable(MIDI1_UART_RX_VECT_NUM); + #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */ + MIDI1_UART_rxBufferRead = rxBufferRead; + #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntEnable(MIDI1_UART_RX_VECT_NUM); + #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */ + } + + msgRtn = USBFS_ProcessMidiIn(rxData, + (USBFS_MIDI_RX_STATUS *)&USBFS_MIDI1_Event); + + /* Read buffer loop condition to the local variable */ + rxBufferLoopDetect = MIDI1_UART_rxBufferLoopDetect; + } + + /* Finally, update the real output pointer, then return with + * an indication as to whether there's a complete message in the buffer. + */ + #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntDisable(MIDI1_UART_RX_VECT_NUM); + #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */ + MIDI1_UART_rxBufferRead = rxBufferRead; + #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntEnable(MIDI1_UART_RX_VECT_NUM); + #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */ + } + + return (msgRtn); + } + + + /******************************************************************************* + * Function Name: USBFS_MIDI1_ProcessUsbOut + ******************************************************************************** + * + * Summary: + * Process a USB MIDI output event. + * Puts data into the MIDI TX output buffer. + * + * Parameters: + * *epBuf: pointer on MIDI event. + * + * Return: + * None + * + * Global variables: + * USBFS_MIDI1_TxRunStat: This variable used to save the MIDI + * status byte and skip to send the repeated status byte in subsequent event. + * USBFS_MIDI1_InqFlags: The following flags are set when SysEx + * message comes. + * USBFS_INQ_SYSEX_FLAG: Non-Real Time SySEx message received. + * USBFS_INQ_IDENTITY_REQ_FLAG: Identity Request received. + * This bit should be cleared by user when Identity Reply message generated. + * + *******************************************************************************/ + void USBFS_MIDI1_ProcessUsbOut(const uint8 epBuf[]) + + { + uint8 cmd; + uint8 len; + uint8 i; + + /* User code is required at the beginning of the procedure */ + /* `#START MIDI1_PROCESS_OUT_BEGIN` */ + + /* `#END` */ + + cmd = epBuf[USBFS_EVENT_BYTE0] & USBFS_CIN_MASK; + if((cmd != USBFS_RESERVED0) && (cmd != USBFS_RESERVED1)) + { + len = USBFS_MIDI_SIZE[cmd]; + i = USBFS_EVENT_BYTE1; + /* Universal System Exclusive message parsing */ + if(cmd == USBFS_SYSEX) + { + if((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX) && + (epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_NON_REAL_TIME)) + { /* Non-Real Time SySEx starts */ + USBFS_MIDI1_InqFlags |= USBFS_INQ_SYSEX_FLAG; + } + else + { + USBFS_MIDI1_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; + } + } + else if(cmd == USBFS_SYSEX_ENDS_WITH1) + { + USBFS_MIDI1_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; + } + else if(cmd == USBFS_SYSEX_ENDS_WITH2) + { + USBFS_MIDI1_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; + } + else if(cmd == USBFS_SYSEX_ENDS_WITH3) + { + /* Identify Request support */ + if((USBFS_MIDI1_InqFlags & USBFS_INQ_SYSEX_FLAG) != 0u) + { + USBFS_MIDI1_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; + if((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX_GEN_INFORMATION) && + (epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_IDENTITY_REQ)) + { /* Set the flag about received the Identity Request. + * The Identity Reply message may be send by user code. + */ + USBFS_MIDI1_InqFlags |= USBFS_INQ_IDENTITY_REQ_FLAG; + } + } + } + else /* Do nothing for other command */ + { + } + /* Running Status for Voice and Mode messages only. */ + if((cmd >= USBFS_NOTE_OFF) && ( cmd <= USBFS_PITCH_BEND_CHANGE)) + { + if(USBFS_MIDI1_TxRunStat == epBuf[USBFS_EVENT_BYTE1]) + { /* Skip the repeated Status byte */ + i++; + } + else + { /* Save Status byte for next event */ + USBFS_MIDI1_TxRunStat = epBuf[USBFS_EVENT_BYTE1]; + } + } + else + { /* Clear Running Status */ + USBFS_MIDI1_TxRunStat = 0u; + } + /* Puts data into the MIDI TX output buffer.*/ + do + { + MIDI1_UART_PutChar(epBuf[i]); + i++; + } while (i <= len); + } + + /* User code is required at the end of the procedure */ + /* `#START MIDI1_PROCESS_OUT_END` */ + + /* `#END` */ + } + +#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + + + /******************************************************************************* + * Function Name: USBFS_MIDI2_GetEvent + ******************************************************************************** + * + * Summary: + * Checks for incoming MIDI data, calls the MIDI event builder if so. + * Returns either empty or with a complete event. + * + * Parameters: + * None + * + * Return: + * 0, if no complete message + * 1 - 4, if message complete + * MIDI_SYSEX, if start or continuation of system exclusive + * MIDI_EOSEX, if end of system exclusive + * 0xf8 - 0xff, if single byte real time message + * + * Global variables: + * USBFS_MIDI2_Event: RX status structure used to parse received + * data. + * + *******************************************************************************/ + uint8 USBFS_MIDI2_GetEvent(void) + { + uint8 msgRtn = 0u; + uint8 rxData; + #if (MIDI2_UART_RXBUFFERSIZE >= 256u) + uint16 rxBufferRead; + #if CY_PSOC3 /* This local variable required only for PSOC3 and large buffer */ + uint16 rxBufferWrite; + #endif /* end CY_PSOC3 */ + #else + uint8 rxBufferRead; + #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */ + uint8 rxBufferLoopDetect; + /* Read buffer loop condition to the local variable */ + rxBufferLoopDetect = MIDI2_UART_rxBufferLoopDetect; + + if ( (MIDI2_UART_rxBufferRead != MIDI2_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u) ) + { + /* Protect variables that could change on interrupt by disabling Rx interrupt.*/ + #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntDisable(MIDI2_UART_RX_VECT_NUM); + #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */ + rxBufferRead = MIDI2_UART_rxBufferRead; + #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + rxBufferWrite = MIDI2_UART_rxBufferWrite; + CyIntEnable(MIDI2_UART_RX_VECT_NUM); + #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */ + + /* Stay here until either the buffer is empty or we have a complete message + * in the message buffer. Note that we must use a temporary output pointer to + * since it takes two instructions to increment with a wrap, and we can't + * risk doing that with the real pointer and getting an interrupt in between + * instructions. + */ + + #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + while ( ((rxBufferRead != rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) ) + #else + while ( ((rxBufferRead != MIDI2_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) ) + #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 && CY_PSOC3 */ + { + rxData = MIDI2_UART_rxBuffer[rxBufferRead]; + rxBufferRead++; + if(rxBufferRead >= MIDI2_UART_RXBUFFERSIZE) + { + rxBufferRead = 0u; + } + /* If loop condition was set - update real read buffer pointer + * to avoid overflow status + */ + if(rxBufferLoopDetect != 0u ) + { + MIDI2_UART_rxBufferLoopDetect = 0u; + #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntDisable(MIDI2_UART_RX_VECT_NUM); + #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */ + MIDI2_UART_rxBufferRead = rxBufferRead; + #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntEnable(MIDI2_UART_RX_VECT_NUM); + #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */ + } + + msgRtn = USBFS_ProcessMidiIn(rxData, + (USBFS_MIDI_RX_STATUS *)&USBFS_MIDI2_Event); + + /* Read buffer loop condition to the local variable */ + rxBufferLoopDetect = MIDI2_UART_rxBufferLoopDetect; + } + + /* Finally, update the real output pointer, then return with + * an indication as to whether there's a complete message in the buffer. + */ + #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntDisable(MIDI2_UART_RX_VECT_NUM); + #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */ + MIDI2_UART_rxBufferRead = rxBufferRead; + #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntEnable(MIDI2_UART_RX_VECT_NUM); + #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */ + } + + return (msgRtn); + } + + + /******************************************************************************* + * Function Name: USBFS_MIDI2_ProcessUsbOut + ******************************************************************************** + * + * Summary: + * Process a USB MIDI output event. + * Puts data into the MIDI TX output buffer. + * + * Parameters: + * *epBuf: pointer on MIDI event. + * + * Return: + * None + * + * Global variables: + * USBFS_MIDI2_TxRunStat: This variable used to save the MIDI + * status byte and skip to send the repeated status byte in subsequent event. + * USBFS_MIDI2_InqFlags: The following flags are set when SysEx + * message comes. + * USBFS_INQ_SYSEX_FLAG: Non-Real Time SySEx message received. + * USBFS_INQ_IDENTITY_REQ_FLAG: Identity Request received. + * This bit should be cleared by user when Identity Reply message generated. + * + *******************************************************************************/ + void USBFS_MIDI2_ProcessUsbOut(const uint8 epBuf[]) + + { + uint8 cmd; + uint8 len; + uint8 i; + + /* User code is required at the beginning of the procedure */ + /* `#START MIDI2_PROCESS_OUT_START` */ + + /* `#END` */ + + cmd = epBuf[USBFS_EVENT_BYTE0] & USBFS_CIN_MASK; + if((cmd != USBFS_RESERVED0) && (cmd != USBFS_RESERVED1)) + { + len = USBFS_MIDI_SIZE[cmd]; + i = USBFS_EVENT_BYTE1; + /* Universal System Exclusive message parsing */ + if(cmd == USBFS_SYSEX) + { + if((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX) && + (epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_NON_REAL_TIME)) + { /* SySEx starts */ + USBFS_MIDI2_InqFlags |= USBFS_INQ_SYSEX_FLAG; + } + else + { + USBFS_MIDI2_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; + } + } + else if(cmd == USBFS_SYSEX_ENDS_WITH1) + { + USBFS_MIDI2_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; + } + else if(cmd == USBFS_SYSEX_ENDS_WITH2) + { + USBFS_MIDI2_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; + } + else if(cmd == USBFS_SYSEX_ENDS_WITH3) + { + /* Identify Request support */ + if((USBFS_MIDI2_InqFlags & USBFS_INQ_SYSEX_FLAG) != 0u) + { + USBFS_MIDI2_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; + if((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX_GEN_INFORMATION) && + (epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_IDENTITY_REQ)) + { /* Set the flag about received the Identity Request. + * The Identity Reply message may be send by user code. + */ + USBFS_MIDI2_InqFlags |= USBFS_INQ_IDENTITY_REQ_FLAG; + } + } + } + else /* Do nothing for other command */ + { + } + /* Running Status for Voice and Mode messages only. */ + if((cmd >= USBFS_NOTE_OFF) && ( cmd <= USBFS_PITCH_BEND_CHANGE)) + { + if(USBFS_MIDI2_TxRunStat == epBuf[USBFS_EVENT_BYTE1]) + { /* Skip the repeated Status byte */ + i++; + } + else + { /* Save Status byte for next event */ + USBFS_MIDI2_TxRunStat = epBuf[USBFS_EVENT_BYTE1]; + } + } + else + { /* Clear Running Status */ + USBFS_MIDI2_TxRunStat = 0u; + } + /* Puts data into the MIDI TX output buffer.*/ + do + { + MIDI2_UART_PutChar(epBuf[i]); + i++; + } while (i <= len); + } + + /* User code is required at the end of the procedure */ + /* `#START MIDI2_PROCESS_OUT_END` */ + + /* `#END` */ + } +#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ +#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ + +#endif /* End (USBFS_ENABLE_MIDI_API != 0u) */ + + +/* `#START MIDI_FUNCTIONS` Place any additional functions here */ + +/* `#END` */ + +#endif /* End defined(USBFS_ENABLE_MIDI_STREAMING) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_midi.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_midi.h new file mode 100755 index 00000000..473cc26d --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_midi.h @@ -0,0 +1,200 @@ +/******************************************************************************* +* File Name: USBFS_midi.h +* Version 2.60 +* +* Description: +* Header File for the USBFS MIDI module. +* Contains prototypes and constant values. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_USBFS_USBFS_midi_H) +#define CY_USBFS_USBFS_midi_H + +#include "cytypes.h" +#include "USBFS.h" + + +/*************************************** +* Data Struct Definition +***************************************/ + +/* The following structure is used to hold status information for + building and parsing incoming MIDI messages. */ +typedef struct +{ + uint8 length; /* expected length */ + uint8 count; /* current byte count */ + uint8 size; /* complete size */ + uint8 runstat; /* running status */ + uint8 msgBuff[4]; /* message buffer */ +} USBFS_MIDI_RX_STATUS; + + +/*************************************** +* MIDI Constants. +***************************************/ + +#define USBFS_ONE_EXT_INTRF (0x01u) +#define USBFS_TWO_EXT_INTRF (0x02u) + +/* Flag definitions for use with MIDI device inquiry */ +#define USBFS_INQ_SYSEX_FLAG (0x01u) +#define USBFS_INQ_IDENTITY_REQ_FLAG (0x02u) + +/* USB-MIDI Code Index Number Classifications (MIDI Table 4-1) */ +#define USBFS_CIN_MASK (0x0Fu) +#define USBFS_RESERVED0 (0x00u) +#define USBFS_RESERVED1 (0x01u) +#define USBFS_2BYTE_COMMON (0x02u) +#define USBFS_3BYTE_COMMON (0x03u) +#define USBFS_SYSEX (0x04u) +#define USBFS_1BYTE_COMMON (0x05u) +#define USBFS_SYSEX_ENDS_WITH1 (0x05u) +#define USBFS_SYSEX_ENDS_WITH2 (0x06u) +#define USBFS_SYSEX_ENDS_WITH3 (0x07u) +#define USBFS_NOTE_OFF (0x08u) +#define USBFS_NOTE_ON (0x09u) +#define USBFS_POLY_KEY_PRESSURE (0x0Au) +#define USBFS_CONTROL_CHANGE (0x0Bu) +#define USBFS_PROGRAM_CHANGE (0x0Cu) +#define USBFS_CHANNEL_PRESSURE (0x0Du) +#define USBFS_PITCH_BEND_CHANGE (0x0Eu) +#define USBFS_SINGLE_BYTE (0x0Fu) + +#define USBFS_CABLE_MASK (0xF0u) +#define USBFS_MIDI_CABLE_00 (0x00u) +#define USBFS_MIDI_CABLE_01 (0x10u) + +#define USBFS_EVENT_BYTE0 (0x00u) +#define USBFS_EVENT_BYTE1 (0x01u) +#define USBFS_EVENT_BYTE2 (0x02u) +#define USBFS_EVENT_BYTE3 (0x03u) +#define USBFS_EVENT_LENGTH (0x04u) + +#define USBFS_MIDI_STATUS_BYTE_MASK (0x80u) +#define USBFS_MIDI_STATUS_MASK (0xF0u) +#define USBFS_MIDI_SINGLE_BYTE_MASK (0x08u) +#define USBFS_MIDI_NOTE_OFF (0x80u) +#define USBFS_MIDI_NOTE_ON (0x90u) +#define USBFS_MIDI_POLY_KEY_PRESSURE (0xA0u) +#define USBFS_MIDI_CONTROL_CHANGE (0xB0u) +#define USBFS_MIDI_PROGRAM_CHANGE (0xC0u) +#define USBFS_MIDI_CHANNEL_PRESSURE (0xD0u) +#define USBFS_MIDI_PITCH_BEND_CHANGE (0xE0u) +#define USBFS_MIDI_SYSEX (0xF0u) +#define USBFS_MIDI_EOSEX (0xF7u) +#define USBFS_MIDI_QFM (0xF1u) +#define USBFS_MIDI_SPP (0xF2u) +#define USBFS_MIDI_SONGSEL (0xF3u) +#define USBFS_MIDI_TUNEREQ (0xF6u) +#define USBFS_MIDI_ACTIVESENSE (0xFEu) + +/* MIDI Universal System Exclusive defines */ +#define USBFS_MIDI_SYSEX_NON_REAL_TIME (0x7Eu) +#define USBFS_MIDI_SYSEX_REALTIME (0x7Fu) +/* ID of target device */ +#define USBFS_MIDI_SYSEX_ID_ALL (0x7Fu) +/* Sub-ID#1*/ +#define USBFS_MIDI_SYSEX_GEN_INFORMATION (0x06u) +#define USBFS_MIDI_SYSEX_GEN_MESSAGE (0x09u) +/* Sub-ID#2*/ +#define USBFS_MIDI_SYSEX_IDENTITY_REQ (0x01u) +#define USBFS_MIDI_SYSEX_IDENTITY_REPLY (0x02u) +#define USBFS_MIDI_SYSEX_SYSTEM_ON (0x01u) +#define USBFS_MIDI_SYSEX_SYSTEM_OFF (0x02u) + +#define USBFS_CUSTOM_UART_TX_PRIOR_NUM (0x04u) +#define USBFS_CUSTOM_UART_RX_PRIOR_NUM (0x02u) + +#define USBFS_ISR_SERVICE_MIDI_OUT \ + ( (USBFS_ENABLE_MIDI_API != 0u) && \ + (USBFS_MIDI_OUT_BUFF_SIZE > 0) && (USBFS_EP_MM == USBFS__EP_DMAAUTO) ) +#define USBFS_ISR_SERVICE_MIDI_IN \ + ( (USBFS_ENABLE_MIDI_API != 0u) && (USBFS_MIDI_IN_BUFF_SIZE > 0) ) + +/*************************************** +* External function references +***************************************/ + +void USBFS_callbackLocalMidiEvent(uint8 cable, uint8 *midiMsg) + ; + + +/*************************************** +* External references +***************************************/ + +#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + #include "MIDI1_UART.h" +#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ +#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + #include "MIDI2_UART.h" +#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ +#if(USBFS_EP_MM != USBFS__EP_MANUAL) + #include +#endif /* End USBFS_EP_MM */ + + +/*************************************** +* Private function prototypes +***************************************/ + +void USBFS_PrepareInBuffer(uint8 ic, const uint8 srcBuff[], uint8 eventLen, uint8 cable) + ; +#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + void USBFS_MIDI_Init(void) ; + uint8 USBFS_ProcessMidiIn(uint8 mData, USBFS_MIDI_RX_STATUS *rxStat) + ; + uint8 USBFS_MIDI1_GetEvent(void) ; + void USBFS_MIDI1_ProcessUsbOut(const uint8 epBuf[]) + ; + + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + uint8 USBFS_MIDI2_GetEvent(void) ; + void USBFS_MIDI2_ProcessUsbOut(const uint8 epBuf[]) + ; + #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ +#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ + + +/*************************************** +* External data references +***************************************/ + +#if defined(USBFS_ENABLE_MIDI_STREAMING) + +#if (USBFS_MIDI_IN_BUFF_SIZE > 0) + #if (USBFS_MIDI_IN_BUFF_SIZE >= 256) + extern volatile uint16 USBFS_midiInPointer; /* Input endpoint buffer pointer */ + #else + extern volatile uint8 USBFS_midiInPointer; /* Input endpoint buffer pointer */ + #endif /* End USBFS_MIDI_IN_BUFF_SIZE >=256 */ + extern volatile uint8 USBFS_midi_in_ep; /* Input endpoint number */ + extern uint8 USBFS_midiInBuffer[USBFS_MIDI_IN_BUFF_SIZE]; /* Input endpoint buffer */ +#endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */ + +#if (USBFS_MIDI_OUT_BUFF_SIZE > 0) + extern volatile uint8 USBFS_midi_out_ep; /* Output endpoint number */ + extern uint8 USBFS_midiOutBuffer[USBFS_MIDI_OUT_BUFF_SIZE]; /* Output endpoint buffer */ +#endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */ + +#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + extern volatile uint8 USBFS_MIDI1_InqFlags; /* Device inquiry flag */ + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + extern volatile uint8 USBFS_MIDI2_InqFlags; /* Device inquiry flag */ + #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ +#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ + +#endif /* USBFS_ENABLE_MIDI_STREAMING */ + + +#endif /* End CY_USBFS_USBFS_midi_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_pm.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_pm.c new file mode 100755 index 00000000..003d7f17 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_pm.c @@ -0,0 +1,277 @@ +/******************************************************************************* +* File Name: USBFS_pm.c +* Version 2.60 +* +* Description: +* This file provides Suspend/Resume APIs functionality. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "project.h" +#include "USBFS.h" +#include "USBFS_pvt.h" + + +/*************************************** +* Custom Declarations +***************************************/ +/* `#START PM_CUSTOM_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +/*************************************** +* Local data allocation +***************************************/ + +static USBFS_BACKUP_STRUCT USBFS_backup; + + +#if(USBFS_DP_ISR_REMOVE == 0u) + + + /******************************************************************************* + * Function Name: USBFS_DP_Interrupt + ******************************************************************************** + * + * Summary: + * This Interrupt Service Routine handles DP pin changes for wake-up from + * the sleep mode. + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + CY_ISR(USBFS_DP_ISR) + { + /* `#START DP_USER_CODE` Place your code here */ + + /* `#END` */ + + /* Clears active interrupt */ + CY_GET_REG8(USBFS_DP_INTSTAT_PTR); + } + +#endif /* (USBFS_DP_ISR_REMOVE == 0u) */ + + +/******************************************************************************* +* Function Name: USBFS_SaveConfig +******************************************************************************** +* +* Summary: +* Saves the current user configuration. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_SaveConfig(void) +{ + +} + + +/******************************************************************************* +* Function Name: USBFS_RestoreConfig +******************************************************************************** +* +* Summary: +* Restores the current user configuration. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_RestoreConfig(void) +{ + if(USBFS_configuration != 0u) + { + USBFS_ConfigReg(); + } +} + + +/******************************************************************************* +* Function Name: USBFS_Suspend +******************************************************************************** +* +* Summary: +* This function disables the USBFS block and prepares for power donwn mode. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* USBFS_backup.enable: modified. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_Suspend(void) +{ + uint8 enableInterrupts; + enableInterrupts = CyEnterCriticalSection(); + + if((CY_GET_REG8(USBFS_CR0_PTR) & USBFS_CR0_ENABLE) != 0u) + { /* USB block is enabled */ + USBFS_backup.enableState = 1u; + + #if(USBFS_EP_MM != USBFS__EP_MANUAL) + USBFS_Stop_DMA(USBFS_MAX_EP); /* Stop all DMAs */ + #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ + + /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled */ + USBFS_USBIO_CR0_REG &= (uint8)~USBFS_USBIO_CR0_TEN; + CyDelayUs(0u); /*~50ns delay */ + + /* Disable the USBIO by asserting PM.USB_CR0.fsusbio_pd_n(Inverted) and pd_pullup_hv(Inverted) high. */ + USBFS_PM_USB_CR0_REG &= + (uint8)~(USBFS_PM_USB_CR0_PD_N | USBFS_PM_USB_CR0_PD_PULLUP_N); + + /* Disable the SIE */ + USBFS_CR0_REG &= (uint8)~USBFS_CR0_ENABLE; + + CyDelayUs(0u); /*~50ns delay */ + /* Store mode and Disable VRegulator*/ + USBFS_backup.mode = USBFS_CR1_REG & USBFS_CR1_REG_ENABLE; + USBFS_CR1_REG &= (uint8)~USBFS_CR1_REG_ENABLE; + + CyDelayUs(1u); /* 0.5 us min delay */ + /* Disable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/ + USBFS_PM_USB_CR0_REG &= (uint8)~USBFS_PM_USB_CR0_REF_EN; + + /* Switch DP and DM terminals to GPIO mode and disconnect 1.5k pullup*/ + USBFS_USBIO_CR1_REG |= USBFS_USBIO_CR1_IOMODE; + + /* Disable USB in ACT PM */ + USBFS_PM_ACT_CFG_REG &= (uint8)~USBFS_PM_ACT_EN_FSUSB; + /* Disable USB block for Standby Power Mode */ + USBFS_PM_STBY_CFG_REG &= (uint8)~USBFS_PM_STBY_EN_FSUSB; + CyDelayUs(1u); /* min 0.5us delay required */ + + } + else + { + USBFS_backup.enableState = 0u; + } + CyExitCriticalSection(enableInterrupts); + + /* Set the DP Interrupt for wake-up from sleep mode. */ + #if(USBFS_DP_ISR_REMOVE == 0u) + (void) CyIntSetVector(USBFS_DP_INTC_VECT_NUM, &USBFS_DP_ISR); + CyIntSetPriority(USBFS_DP_INTC_VECT_NUM, USBFS_DP_INTC_PRIOR); + CyIntClearPending(USBFS_DP_INTC_VECT_NUM); + CyIntEnable(USBFS_DP_INTC_VECT_NUM); + #endif /* (USBFS_DP_ISR_REMOVE == 0u) */ + +} + + +/******************************************************************************* +* Function Name: USBFS_Resume +******************************************************************************** +* +* Summary: +* This function enables the USBFS block after power down mode. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* USBFS_backup - checked. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_Resume(void) +{ + uint8 enableInterrupts; + enableInterrupts = CyEnterCriticalSection(); + + if(USBFS_backup.enableState != 0u) + { + #if(USBFS_DP_ISR_REMOVE == 0u) + CyIntDisable(USBFS_DP_INTC_VECT_NUM); + #endif /* End USBFS_DP_ISR_REMOVE */ + + /* Enable USB block */ + USBFS_PM_ACT_CFG_REG |= USBFS_PM_ACT_EN_FSUSB; + /* Enable USB block for Standby Power Mode */ + USBFS_PM_STBY_CFG_REG |= USBFS_PM_STBY_EN_FSUSB; + /* Enable core clock */ + USBFS_USB_CLK_EN_REG |= USBFS_USB_CLK_ENABLE; + + /* Enable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/ + USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_REF_EN; + /* The reference will be available ~40us after power restored */ + CyDelayUs(40u); + /* Return VRegulator*/ + USBFS_CR1_REG |= USBFS_backup.mode; + CyDelayUs(0u); /*~50ns delay */ + /* Enable USBIO */ + USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_N; + CyDelayUs(2u); + /* Set the USBIO pull-up enable */ + USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_PULLUP_N; + + /* Reinit Arbiter configuration for DMA transfers */ + #if(USBFS_EP_MM != USBFS__EP_MANUAL) + /* usb arb interrupt enable */ + USBFS_ARB_INT_EN_REG = USBFS_ARB_INT_MASK; + #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL) + USBFS_ARB_CFG_REG = USBFS_ARB_CFG_MANUAL_DMA; + #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */ + #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + /*Set cfg cmplt this rises DMA request when the full configuration is done */ + USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM; + #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ + #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ + + /* STALL_IN_OUT */ + CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT); + /* Enable the SIE with a last address */ + USBFS_CR0_REG |= USBFS_CR0_ENABLE; + CyDelayCycles(1u); + /* Finally, Enable d+ pullup and select iomode to USB mode*/ + CY_SET_REG8(USBFS_USBIO_CR1_PTR, USBFS_USBIO_CR1_USBPUEN); + + /* Restore USB register settings */ + USBFS_RestoreConfig(); + + } + CyExitCriticalSection(enableInterrupts); +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_pvt.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_pvt.h new file mode 100755 index 00000000..7b61963c --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_pvt.h @@ -0,0 +1,203 @@ +/******************************************************************************* +* File Name: .h +* Version 2.60 +* +* Description: +* This private file provides constants and parameter values for the +* USBFS Component. +* Please do not use this file or its content in your project. +* +* Note: +* +******************************************************************************** +* Copyright 2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_USBFS_USBFS_pvt_H) +#define CY_USBFS_USBFS_pvt_H + + +/*************************************** +* Private Variables +***************************************/ + +/* Generated external references for descriptors*/ +extern const uint8 CYCODE USBFS_DEVICE0_DESCR[18u]; +extern const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_DESCR[41u]; +extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_TABLE[1u]; +extern const T_USBFS_EP_SETTINGS_BLOCK CYCODE USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE[2u]; +extern const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE_CLASS[1u]; +extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_TABLE[4u]; +extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_TABLE[2u]; +extern const T_USBFS_LUT CYCODE USBFS_TABLE[1u]; +extern const uint8 CYCODE USBFS_SN_STRING_DESCRIPTOR[10]; +extern const uint8 CYCODE USBFS_STRING_DESCRIPTORS[45u]; +extern T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_RPT_SCB; +extern uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF[ + USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF_SIZE]; +extern T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_RPT_SCB; +extern uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF[ + USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF_SIZE]; +extern const uint8 CYCODE USBFS_HIDREPORT_DESCRIPTOR1[40u]; +extern const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_RPT_TABLE[1u]; +extern const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_RPT_TABLE[1u]; +extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_TABLE[5u]; + + +extern const uint8 CYCODE USBFS_MSOS_DESCRIPTOR[USBFS_MSOS_DESCRIPTOR_LENGTH]; +extern const uint8 CYCODE USBFS_MSOS_CONFIGURATION_DESCR[USBFS_MSOS_CONF_DESCR_LENGTH]; +#if defined(USBFS_ENABLE_IDSN_STRING) + extern uint8 USBFS_idSerialNumberStringDescriptor[USBFS_IDSN_DESCR_LENGTH]; +#endif /* USBFS_ENABLE_IDSN_STRING */ + +extern volatile uint8 USBFS_interfaceNumber; +extern volatile uint8 USBFS_interfaceSetting[USBFS_MAX_INTERFACES_NUMBER]; +extern volatile uint8 USBFS_interfaceSetting_last[USBFS_MAX_INTERFACES_NUMBER]; +extern volatile uint8 USBFS_deviceAddress; +extern volatile uint8 USBFS_interfaceStatus[USBFS_MAX_INTERFACES_NUMBER]; +extern const uint8 CYCODE *USBFS_interfaceClass; + +extern volatile T_USBFS_EP_CTL_BLOCK USBFS_EP[USBFS_MAX_EP]; +extern volatile T_USBFS_TD USBFS_currentTD; + +#if(USBFS_EP_MM != USBFS__EP_MANUAL) + extern uint8 USBFS_DmaChan[USBFS_MAX_EP]; + extern uint8 USBFS_DmaTd[USBFS_MAX_EP]; +#endif /* End USBFS_EP_MM */ + +extern volatile uint8 USBFS_ep0Toggle; +extern volatile uint8 USBFS_lastPacketSize; +extern volatile uint8 USBFS_ep0Mode; +extern volatile uint8 USBFS_ep0Count; +extern volatile uint16 USBFS_transferByteCount; + + +/*************************************** +* Private Function Prototypes +***************************************/ +void USBFS_ReInitComponent(void) ; +void USBFS_HandleSetup(void) ; +void USBFS_HandleIN(void) ; +void USBFS_HandleOUT(void) ; +void USBFS_LoadEP0(void) ; +uint8 USBFS_InitControlRead(void) ; +uint8 USBFS_InitControlWrite(void) ; +void USBFS_ControlReadDataStage(void) ; +void USBFS_ControlReadStatusStage(void) ; +void USBFS_ControlReadPrematureStatus(void) + ; +uint8 USBFS_InitControlWrite(void) ; +uint8 USBFS_InitZeroLengthControlTransfer(void) + ; +void USBFS_ControlWriteDataStage(void) ; +void USBFS_ControlWriteStatusStage(void) ; +void USBFS_ControlWritePrematureStatus(void) + ; +uint8 USBFS_InitNoDataControlTransfer(void) ; +void USBFS_NoDataControlStatusStage(void) ; +void USBFS_InitializeStatusBlock(void) ; +void USBFS_UpdateStatusBlock(uint8 completionCode) ; +uint8 USBFS_DispatchClassRqst(void) ; + +void USBFS_Config(uint8 clearAltSetting) ; +void USBFS_ConfigAltChanged(void) ; +void USBFS_ConfigReg(void) ; + +const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 c) + ; +const T_USBFS_LUT CYCODE *USBFS_GetDeviceTablePtr(void) + ; +const uint8 CYCODE *USBFS_GetInterfaceClassTablePtr(void) + ; +uint8 USBFS_ClearEndpointHalt(void) ; +uint8 USBFS_SetEndpointHalt(void) ; +uint8 USBFS_ValidateAlternateSetting(void) ; + +void USBFS_SaveConfig(void) ; +void USBFS_RestoreConfig(void) ; + +#if defined(USBFS_ENABLE_IDSN_STRING) + void USBFS_ReadDieID(uint8 descr[]) ; +#endif /* USBFS_ENABLE_IDSN_STRING */ + +#if defined(USBFS_ENABLE_HID_CLASS) + uint8 USBFS_DispatchHIDClassRqst(void); +#endif /* End USBFS_ENABLE_HID_CLASS */ +#if defined(USBFS_ENABLE_AUDIO_CLASS) + uint8 USBFS_DispatchAUDIOClassRqst(void); +#endif /* End USBFS_ENABLE_HID_CLASS */ +#if defined(USBFS_ENABLE_CDC_CLASS) + uint8 USBFS_DispatchCDCClassRqst(void); +#endif /* End USBFS_ENABLE_CDC_CLASS */ + +CY_ISR_PROTO(USBFS_EP_0_ISR); +#if(USBFS_EP1_ISR_REMOVE == 0u) + CY_ISR_PROTO(USBFS_EP_1_ISR); +#endif /* End USBFS_EP1_ISR_REMOVE */ +#if(USBFS_EP2_ISR_REMOVE == 0u) + CY_ISR_PROTO(USBFS_EP_2_ISR); +#endif /* End USBFS_EP2_ISR_REMOVE */ +#if(USBFS_EP3_ISR_REMOVE == 0u) + CY_ISR_PROTO(USBFS_EP_3_ISR); +#endif /* End USBFS_EP3_ISR_REMOVE */ +#if(USBFS_EP4_ISR_REMOVE == 0u) + CY_ISR_PROTO(USBFS_EP_4_ISR); +#endif /* End USBFS_EP4_ISR_REMOVE */ +#if(USBFS_EP5_ISR_REMOVE == 0u) + CY_ISR_PROTO(USBFS_EP_5_ISR); +#endif /* End USBFS_EP5_ISR_REMOVE */ +#if(USBFS_EP6_ISR_REMOVE == 0u) + CY_ISR_PROTO(USBFS_EP_6_ISR); +#endif /* End USBFS_EP6_ISR_REMOVE */ +#if(USBFS_EP7_ISR_REMOVE == 0u) + CY_ISR_PROTO(USBFS_EP_7_ISR); +#endif /* End USBFS_EP7_ISR_REMOVE */ +#if(USBFS_EP8_ISR_REMOVE == 0u) + CY_ISR_PROTO(USBFS_EP_8_ISR); +#endif /* End USBFS_EP8_ISR_REMOVE */ +CY_ISR_PROTO(USBFS_BUS_RESET_ISR); +#if(USBFS_SOF_ISR_REMOVE == 0u) + CY_ISR_PROTO(USBFS_SOF_ISR); +#endif /* End USBFS_SOF_ISR_REMOVE */ +#if(USBFS_EP_MM != USBFS__EP_MANUAL) + CY_ISR_PROTO(USBFS_ARB_ISR); +#endif /* End USBFS_EP_MM */ +#if(USBFS_DP_ISR_REMOVE == 0u) + CY_ISR_PROTO(USBFS_DP_ISR); +#endif /* End USBFS_DP_ISR_REMOVE */ + + +/*************************************** +* Request Handlers +***************************************/ + +uint8 USBFS_HandleStandardRqst(void) ; +uint8 USBFS_DispatchClassRqst(void) ; +uint8 USBFS_HandleVendorRqst(void) ; + + +/*************************************** +* HID Internal references +***************************************/ +#if defined(USBFS_ENABLE_HID_CLASS) + void USBFS_FindReport(void) ; + void USBFS_FindReportDescriptor(void) ; + void USBFS_FindHidClassDecriptor(void) ; +#endif /* USBFS_ENABLE_HID_CLASS */ + + +/*************************************** +* MIDI Internal references +***************************************/ +#if defined(USBFS_ENABLE_MIDI_STREAMING) + void USBFS_MIDI_IN_EP_Service(void) ; +#endif /* USBFS_ENABLE_MIDI_STREAMING */ + + +#endif /* CY_USBFS_USBFS_pvt_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_std.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_std.c new file mode 100755 index 00000000..af2f201a --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_std.c @@ -0,0 +1,1134 @@ +/******************************************************************************* +* File Name: USBFS_std.c +* Version 2.60 +* +* Description: +* USB Standard request handler. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS.h" +#include "USBFS_cdc.h" +#include "USBFS_pvt.h" +#if defined(USBFS_ENABLE_MIDI_STREAMING) + #include "USBFS_midi.h" +#endif /* End USBFS_ENABLE_MIDI_STREAMING*/ + + +/*************************************** +* Static data allocation +***************************************/ + +#if defined(USBFS_ENABLE_FWSN_STRING) + static volatile uint8 *USBFS_fwSerialNumberStringDescriptor; + static volatile uint8 USBFS_snStringConfirm = USBFS_FALSE; +#endif /* USBFS_ENABLE_FWSN_STRING */ + +#if defined(USBFS_ENABLE_FWSN_STRING) + + + /******************************************************************************* + * Function Name: USBFS_SerialNumString + ******************************************************************************** + * + * Summary: + * Application firmware may supply the source of the USB device descriptors + * serial number string during runtime. + * + * Parameters: + * snString: pointer to string. + * + * Return: + * None. + * + * Reentrant: + * No. + * + *******************************************************************************/ + void USBFS_SerialNumString(uint8 snString[]) + { + USBFS_snStringConfirm = USBFS_FALSE; + if(snString != NULL) + { + USBFS_fwSerialNumberStringDescriptor = snString; + /* Check descriptor validation */ + if( (snString[0u] > 1u ) && (snString[1u] == USBFS_DESCR_STRING) ) + { + USBFS_snStringConfirm = USBFS_TRUE; + } + } + } + +#endif /* USBFS_ENABLE_FWSN_STRING */ + + +/******************************************************************************* +* Function Name: USBFS_HandleStandardRqst +******************************************************************************** +* +* Summary: +* This Routine dispatches standard requests +* +* Parameters: +* None. +* +* Return: +* TRUE if request handled. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_HandleStandardRqst(void) +{ + uint8 requestHandled = USBFS_FALSE; + uint8 interfaceNumber; + #if defined(USBFS_ENABLE_STRINGS) + volatile uint8 *pStr = 0u; + #if defined(USBFS_ENABLE_DESCRIPTOR_STRINGS) + uint8 nStr; + uint8 descrLength; + #endif /* USBFS_ENABLE_DESCRIPTOR_STRINGS */ + #endif /* USBFS_ENABLE_STRINGS */ + static volatile uint8 USBFS_tBuffer[USBFS_STATUS_LENGTH_MAX]; + const T_USBFS_LUT CYCODE *pTmp; + USBFS_currentTD.count = 0u; + + if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H) + { + /* Control Read */ + switch (CY_GET_REG8(USBFS_bRequest)) + { + case USBFS_GET_DESCRIPTOR: + if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_DEVICE) + { + pTmp = USBFS_GetDeviceTablePtr(); + USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list; + USBFS_currentTD.count = USBFS_DEVICE_DESCR_LENGTH; + requestHandled = USBFS_InitControlRead(); + } + else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_CONFIG) + { + pTmp = USBFS_GetConfigTablePtr(CY_GET_REG8(USBFS_wValueLo)); + USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list; + USBFS_currentTD.count = ((uint16)(USBFS_currentTD.pData)[ \ + USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI] << 8u) | \ + (USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW]; + requestHandled = USBFS_InitControlRead(); + } + #if defined(USBFS_ENABLE_STRINGS) + else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_STRING) + { + /* Descriptor Strings*/ + #if defined(USBFS_ENABLE_DESCRIPTOR_STRINGS) + nStr = 0u; + pStr = (volatile uint8 *)&USBFS_STRING_DESCRIPTORS[0u]; + while ( (CY_GET_REG8(USBFS_wValueLo) > nStr) && (*pStr != 0u) ) + { + /* Read descriptor length from 1st byte */ + descrLength = *pStr; + /* Move to next string descriptor */ + pStr = &pStr[descrLength]; + nStr++; + } + #endif /* End USBFS_ENABLE_DESCRIPTOR_STRINGS */ + /* Microsoft OS String*/ + #if defined(USBFS_ENABLE_MSOS_STRING) + if( CY_GET_REG8(USBFS_wValueLo) == USBFS_STRING_MSOS ) + { + pStr = (volatile uint8 *)&USBFS_MSOS_DESCRIPTOR[0u]; + } + #endif /* End USBFS_ENABLE_MSOS_STRING*/ + /* SN string */ + #if defined(USBFS_ENABLE_SN_STRING) + if( (CY_GET_REG8(USBFS_wValueLo) != 0u) && + (CY_GET_REG8(USBFS_wValueLo) == + USBFS_DEVICE0_DESCR[USBFS_DEVICE_DESCR_SN_SHIFT]) ) + { + pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u]; + #if defined(USBFS_ENABLE_FWSN_STRING) + if(USBFS_snStringConfirm != USBFS_FALSE) + { + pStr = USBFS_fwSerialNumberStringDescriptor; + } + #endif /* USBFS_ENABLE_FWSN_STRING */ + #if defined(USBFS_ENABLE_IDSN_STRING) + /* Read DIE ID and generate string descriptor in RAM */ + USBFS_ReadDieID(USBFS_idSerialNumberStringDescriptor); + pStr = USBFS_idSerialNumberStringDescriptor; + #endif /* End USBFS_ENABLE_IDSN_STRING */ + } + #endif /* End USBFS_ENABLE_SN_STRING */ + if (*pStr != 0u) + { + USBFS_currentTD.count = *pStr; + USBFS_currentTD.pData = pStr; + requestHandled = USBFS_InitControlRead(); + } + } + #endif /* End USBFS_ENABLE_STRINGS */ + else + { + requestHandled = USBFS_DispatchClassRqst(); + } + break; + case USBFS_GET_STATUS: + switch ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK)) + { + case USBFS_RQST_RCPT_EP: + USBFS_currentTD.count = USBFS_EP_STATUS_LENGTH; + USBFS_tBuffer[0u] = USBFS_EP[ \ + CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED].hwEpState; + USBFS_tBuffer[1u] = 0u; + USBFS_currentTD.pData = &USBFS_tBuffer[0u]; + requestHandled = USBFS_InitControlRead(); + break; + case USBFS_RQST_RCPT_DEV: + USBFS_currentTD.count = USBFS_DEVICE_STATUS_LENGTH; + USBFS_tBuffer[0u] = USBFS_deviceStatus; + USBFS_tBuffer[1u] = 0u; + USBFS_currentTD.pData = &USBFS_tBuffer[0u]; + requestHandled = USBFS_InitControlRead(); + break; + default: /* requestHandled is initialized as FALSE by default */ + break; + } + break; + case USBFS_GET_CONFIGURATION: + USBFS_currentTD.count = 1u; + USBFS_currentTD.pData = (volatile uint8 *)&USBFS_configuration; + requestHandled = USBFS_InitControlRead(); + break; + case USBFS_GET_INTERFACE: + USBFS_currentTD.count = 1u; + USBFS_currentTD.pData = (volatile uint8 *)&USBFS_interfaceSetting[ \ + CY_GET_REG8(USBFS_wIndexLo)]; + requestHandled = USBFS_InitControlRead(); + break; + default: /* requestHandled is initialized as FALSE by default */ + break; + } + } + else { + /* Control Write */ + switch (CY_GET_REG8(USBFS_bRequest)) + { + case USBFS_SET_ADDRESS: + USBFS_deviceAddress = CY_GET_REG8(USBFS_wValueLo); + requestHandled = USBFS_InitNoDataControlTransfer(); + break; + case USBFS_SET_CONFIGURATION: + USBFS_configuration = CY_GET_REG8(USBFS_wValueLo); + USBFS_configurationChanged = USBFS_TRUE; + USBFS_Config(USBFS_TRUE); + requestHandled = USBFS_InitNoDataControlTransfer(); + break; + case USBFS_SET_INTERFACE: + if (USBFS_ValidateAlternateSetting() != 0u) + { + interfaceNumber = CY_GET_REG8(USBFS_wIndexLo); + USBFS_interfaceNumber = interfaceNumber; + USBFS_configurationChanged = USBFS_TRUE; + #if ((USBFS_EP_MA == USBFS__MA_DYNAMIC) && \ + (USBFS_EP_MM == USBFS__EP_MANUAL) ) + USBFS_Config(USBFS_FALSE); + #else + USBFS_ConfigAltChanged(); + #endif /* End (USBFS_EP_MA == USBFS__MA_DYNAMIC) */ + /* Update handled Alt setting changes status */ + USBFS_interfaceSetting_last[interfaceNumber] = + USBFS_interfaceSetting[interfaceNumber]; + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + case USBFS_CLEAR_FEATURE: + switch (CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) + { + case USBFS_RQST_RCPT_EP: + if (CY_GET_REG8(USBFS_wValueLo) == USBFS_ENDPOINT_HALT) + { + requestHandled = USBFS_ClearEndpointHalt(); + } + break; + case USBFS_RQST_RCPT_DEV: + /* Clear device REMOTE_WAKEUP */ + if (CY_GET_REG8(USBFS_wValueLo) == USBFS_DEVICE_REMOTE_WAKEUP) + { + USBFS_deviceStatus &= (uint8)~USBFS_DEVICE_STATUS_REMOTE_WAKEUP; + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + case USBFS_RQST_RCPT_IFC: + /* Validate interfaceNumber */ + if (CY_GET_REG8(USBFS_wIndexLo) < USBFS_MAX_INTERFACES_NUMBER) + { + USBFS_interfaceStatus[CY_GET_REG8(USBFS_wIndexLo)] &= + (uint8)~(CY_GET_REG8(USBFS_wValueLo)); + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + default: /* requestHandled is initialized as FALSE by default */ + break; + } + break; + case USBFS_SET_FEATURE: + switch (CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) + { + case USBFS_RQST_RCPT_EP: + if (CY_GET_REG8(USBFS_wValueLo) == USBFS_ENDPOINT_HALT) + { + requestHandled = USBFS_SetEndpointHalt(); + } + break; + case USBFS_RQST_RCPT_DEV: + /* Set device REMOTE_WAKEUP */ + if (CY_GET_REG8(USBFS_wValueLo) == USBFS_DEVICE_REMOTE_WAKEUP) + { + USBFS_deviceStatus |= USBFS_DEVICE_STATUS_REMOTE_WAKEUP; + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + case USBFS_RQST_RCPT_IFC: + /* Validate interfaceNumber */ + if (CY_GET_REG8(USBFS_wIndexLo) < USBFS_MAX_INTERFACES_NUMBER) + { + USBFS_interfaceStatus[CY_GET_REG8(USBFS_wIndexLo)] &= + (uint8)~(CY_GET_REG8(USBFS_wValueLo)); + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + default: /* requestHandled is initialized as FALSE by default */ + break; + } + break; + default: /* requestHandled is initialized as FALSE by default */ + break; + } + } + return(requestHandled); +} + + +#if defined(USBFS_ENABLE_IDSN_STRING) + + /*************************************************************************** + * Function Name: USBFS_ReadDieID + **************************************************************************** + * + * Summary: + * This routine read Die ID and generate Serial Number string descriptor. + * + * Parameters: + * descr: pointer on string descriptor. + * + * Return: + * None. + * + * Reentrant: + * No. + * + ***************************************************************************/ + void USBFS_ReadDieID(uint8 descr[]) + { + uint8 i; + uint8 j = 0u; + uint8 value; + const char8 CYCODE hex[16u] = "0123456789ABCDEF"; + + + /* Check descriptor validation */ + if( descr != NULL) + { + descr[0u] = USBFS_IDSN_DESCR_LENGTH; + descr[1u] = USBFS_DESCR_STRING; + + /* fill descriptor */ + for(i = 2u; i < USBFS_IDSN_DESCR_LENGTH; i += 4u) + { + value = CY_GET_XTND_REG8((void CYFAR *)(USBFS_DIE_ID + j)); + j++; + descr[i] = (uint8)hex[value >> 4u]; + descr[i + 2u] = (uint8)hex[value & 0x0Fu]; + } + } + } + +#endif /* End USBFS_ENABLE_IDSN_STRING */ + + +/******************************************************************************* +* Function Name: USBFS_ConfigReg +******************************************************************************** +* +* Summary: +* This routine configures hardware registers from the variables. +* It is called from USBFS_Config() function and from RestoreConfig +* after Wakeup. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void USBFS_ConfigReg(void) +{ + uint8 ep; + uint8 i; + #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + uint8 ep_type = 0u; + #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ + + /* Set the endpoint buffer addresses */ + ep = USBFS_EP1; + for (i = 0u; i < 0x80u; i+= 0x10u) + { + CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_CFG_IND + i), USBFS_ARB_EPX_CFG_CRC_BYPASS | + USBFS_ARB_EPX_CFG_RESET); + + #if(USBFS_EP_MM != USBFS__EP_MANUAL) + /* Enable all Arbiter EP Interrupts : err, buf under, buf over, dma gnt(mode2 only), in buf full */ + CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_INT_EN_IND + i), USBFS_ARB_EPX_INT_MASK); + #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ + + if(USBFS_EP[ep].epMode != USBFS_MODE_DISABLE) + { + if((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u ) + { + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + i), USBFS_MODE_NAK_IN); + } + else + { + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + i), USBFS_MODE_NAK_OUT); + /* Prepare EP type mask for automatic memory allocation */ + #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + ep_type |= (uint8)(0x01u << (ep - USBFS_EP1)); + #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ + } + } + else + { + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + i), USBFS_MODE_STALL_DATA_EP); + } + + #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + i), USBFS_EP[ep].bufferSize >> 8u); + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + i), USBFS_EP[ep].bufferSize & 0xFFu); + + CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_IND + i), USBFS_EP[ep].buffOffset & 0xFFu); + CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u); + CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + i), USBFS_EP[ep].buffOffset & 0xFFu); + CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u); + #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */ + + ep++; + } + + #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + /* BUF_SIZE depend on DMA_THRESS value: 55-32 bytes 44-16 bytes 33-8 bytes 22-4 bytes 11-2 bytes */ + USBFS_BUF_SIZE_REG = USBFS_DMA_BUF_SIZE; + USBFS_DMA_THRES_REG = USBFS_DMA_BYTES_PER_BURST; /* DMA burst threshold */ + USBFS_DMA_THRES_MSB_REG = 0u; + USBFS_EP_ACTIVE_REG = USBFS_ARB_INT_MASK; + USBFS_EP_TYPE_REG = ep_type; + /* Cfg_cmp bit set to 1 once configuration is complete. */ + USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM | + USBFS_ARB_CFG_CFG_CPM; + /* Cfg_cmp bit set to 0 during configuration of PFSUSB Registers. */ + USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM; + #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ + + CY_SET_REG8(USBFS_SIE_EP_INT_EN_PTR, 0xFFu); +} + + +/******************************************************************************* +* Function Name: USBFS_Config +******************************************************************************** +* +* Summary: +* This routine configures endpoints for the entire configuration by scanning +* the configuration descriptor. +* +* Parameters: +* clearAltSetting: It configures the bAlternateSetting 0 for each interface. +* +* Return: +* None. +* +* USBFS_interfaceClass - Initialized class array for each interface. +* It is used for handling Class specific requests depend on interface class. +* Different classes in multiple Alternate settings does not supported. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_Config(uint8 clearAltSetting) +{ + uint8 ep; + uint8 cur_ep; + uint8 i; + uint8 ep_type; + const uint8 *pDescr; + #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) + uint16 buffCount = 0u; + #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */ + + const T_USBFS_LUT CYCODE *pTmp; + const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP; + + /* Clear all of the endpoints */ + for (ep = 0u; ep < USBFS_MAX_EP; ep++) + { + USBFS_EP[ep].attrib = 0u; + USBFS_EP[ep].hwEpState = 0u; + USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_PENDING; + USBFS_EP[ep].epToggle = 0u; + USBFS_EP[ep].epMode = USBFS_MODE_DISABLE; + USBFS_EP[ep].bufferSize = 0u; + USBFS_EP[ep].interface = 0u; + + } + + /* Clear Alternate settings for all interfaces */ + if(clearAltSetting != 0u) + { + for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++) + { + USBFS_interfaceSetting[i] = 0x00u; + USBFS_interfaceSetting_last[i] = 0x00u; + } + } + + /* Init Endpoints and Device Status if configured */ + if(USBFS_configuration > 0u) + { + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + /* Set Power status for current configuration */ + pDescr = (const uint8 *)pTmp->p_list; + if((pDescr[USBFS_CONFIG_DESCR_ATTRIB] & USBFS_CONFIG_DESCR_ATTRIB_SELF_POWERED) != 0u) + { + USBFS_deviceStatus |= USBFS_DEVICE_STATUS_SELF_POWERED; + } + else + { + USBFS_deviceStatus &= (uint8)~USBFS_DEVICE_STATUS_SELF_POWERED; + } + /* Move to next element */ + pTmp = &pTmp[1u]; + ep = pTmp->c; /* For this table, c is the number of endpoints configurations */ + + #if ((USBFS_EP_MA == USBFS__MA_DYNAMIC) && \ + (USBFS_EP_MM == USBFS__EP_MANUAL) ) + /* Configure for dynamic EP memory allocation */ + /* p_list points the endpoint setting table. */ + pEP = (T_USBFS_EP_SETTINGS_BLOCK *) pTmp->p_list; + for (i = 0u; i < ep; i++) + { + /* Compare current Alternate setting with EP Alt*/ + if(USBFS_interfaceSetting[pEP->interface] == pEP->altSetting) + { + cur_ep = pEP->addr & USBFS_DIR_UNUSED; + ep_type = pEP->attributes & USBFS_EP_TYPE_MASK; + if (pEP->addr & USBFS_DIR_IN) + { + /* IN Endpoint */ + USBFS_EP[cur_ep].apiEpState = USBFS_EVENT_PENDING; + USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ? + USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN; + #if defined(USBFS_ENABLE_CDC_CLASS) + if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) || + (pEP->bMisc == USBFS_CLASS_CDC)) && + (ep_type != USBFS_EP_TYPE_INT)) + { + USBFS_cdc_data_in_ep = cur_ep; + } + #endif /* End USBFS_ENABLE_CDC_CLASS*/ + #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \ + (USBFS_MIDI_IN_BUFF_SIZE > 0) ) + if((pEP->bMisc == USBFS_CLASS_AUDIO) && + (ep_type == USBFS_EP_TYPE_BULK)) + { + USBFS_midi_in_ep = cur_ep; + } + #endif /* End USBFS_ENABLE_MIDI_STREAMING*/ + } + else + { + /* OUT Endpoint */ + USBFS_EP[cur_ep].apiEpState = USBFS_NO_EVENT_PENDING; + USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ? + USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT; + #if defined(USBFS_ENABLE_CDC_CLASS) + if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) || + (pEP->bMisc == USBFS_CLASS_CDC)) && + (ep_type != USBFS_EP_TYPE_INT)) + { + USBFS_cdc_data_out_ep = cur_ep; + } + #endif /* End USBFS_ENABLE_CDC_CLASS*/ + #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \ + (USBFS_MIDI_OUT_BUFF_SIZE > 0) ) + if((pEP->bMisc == USBFS_CLASS_AUDIO) && + (ep_type == USBFS_EP_TYPE_BULK)) + { + USBFS_midi_out_ep = cur_ep; + } + #endif /* End USBFS_ENABLE_MIDI_STREAMING*/ + } + USBFS_EP[cur_ep].bufferSize = pEP->bufferSize; + USBFS_EP[cur_ep].addr = pEP->addr; + USBFS_EP[cur_ep].attrib = pEP->attributes; + } + pEP = &pEP[1u]; + } + #else /* Config for static EP memory allocation */ + for (i = USBFS_EP1; i < USBFS_MAX_EP; i++) + { + /* p_list points the endpoint setting table. */ + pEP = (const T_USBFS_EP_SETTINGS_BLOCK CYCODE *) pTmp->p_list; + /* Find max length for each EP and select it (length could be different in different Alt settings) */ + /* but other settings should be correct with regards to Interface alt Setting */ + for (cur_ep = 0u; cur_ep < ep; cur_ep++) + { + /* EP count is equal to EP # in table and we found larger EP length than have before*/ + if(i == (pEP->addr & USBFS_DIR_UNUSED)) + { + if(USBFS_EP[i].bufferSize < pEP->bufferSize) + { + USBFS_EP[i].bufferSize = pEP->bufferSize; + } + /* Compare current Alternate setting with EP Alt*/ + if(USBFS_interfaceSetting[pEP->interface] == pEP->altSetting) + { + ep_type = pEP->attributes & USBFS_EP_TYPE_MASK; + if ((pEP->addr & USBFS_DIR_IN) != 0u) + { + /* IN Endpoint */ + USBFS_EP[i].apiEpState = USBFS_EVENT_PENDING; + USBFS_EP[i].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ? + USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN; + /* Find and init CDC IN endpoint number */ + #if defined(USBFS_ENABLE_CDC_CLASS) + if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) || + (pEP->bMisc == USBFS_CLASS_CDC)) && + (ep_type != USBFS_EP_TYPE_INT)) + { + USBFS_cdc_data_in_ep = i; + } + #endif /* End USBFS_ENABLE_CDC_CLASS*/ + #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \ + (USBFS_MIDI_IN_BUFF_SIZE > 0) ) + if((pEP->bMisc == USBFS_CLASS_AUDIO) && + (ep_type == USBFS_EP_TYPE_BULK)) + { + USBFS_midi_in_ep = i; + } + #endif /* End USBFS_ENABLE_MIDI_STREAMING*/ + } + else + { + /* OUT Endpoint */ + USBFS_EP[i].apiEpState = USBFS_NO_EVENT_PENDING; + USBFS_EP[i].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ? + USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT; + /* Find and init CDC IN endpoint number */ + #if defined(USBFS_ENABLE_CDC_CLASS) + if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) || + (pEP->bMisc == USBFS_CLASS_CDC)) && + (ep_type != USBFS_EP_TYPE_INT)) + { + USBFS_cdc_data_out_ep = i; + } + #endif /* End USBFS_ENABLE_CDC_CLASS*/ + #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \ + (USBFS_MIDI_OUT_BUFF_SIZE > 0) ) + if((pEP->bMisc == USBFS_CLASS_AUDIO) && + (ep_type == USBFS_EP_TYPE_BULK)) + { + USBFS_midi_out_ep = i; + } + #endif /* End USBFS_ENABLE_MIDI_STREAMING*/ + } + USBFS_EP[i].addr = pEP->addr; + USBFS_EP[i].attrib = pEP->attributes; + + #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + break; /* use first EP setting in Auto memory managment */ + #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ + } + } + pEP = &pEP[1u]; + } + } + #endif /* End (USBFS_EP_MA == USBFS__MA_DYNAMIC) */ + + /* Init class array for each interface and interface number for each EP. + * It is used for handling Class specific requests directed to either an + * interface or the endpoint. + */ + /* p_list points the endpoint setting table. */ + pEP = (const T_USBFS_EP_SETTINGS_BLOCK CYCODE *) pTmp->p_list; + for (i = 0u; i < ep; i++) + { + /* Configure interface number for each EP*/ + USBFS_EP[pEP->addr & USBFS_DIR_UNUSED].interface = pEP->interface; + pEP = &pEP[1u]; + } + /* Init pointer on interface class table*/ + USBFS_interfaceClass = USBFS_GetInterfaceClassTablePtr(); + /* Set the endpoint buffer addresses */ + + #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) + for (ep = USBFS_EP1; ep < USBFS_MAX_EP; ep++) + { + USBFS_EP[ep].buffOffset = buffCount; + buffCount += USBFS_EP[ep].bufferSize; + } + #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */ + + /* Configure hardware registers */ + USBFS_ConfigReg(); + } /* USBFS_configuration > 0 */ +} + + +/******************************************************************************* +* Function Name: USBFS_ConfigAltChanged +******************************************************************************** +* +* Summary: +* This routine update configuration for the required endpoints only. +* It is called after SET_INTERFACE request when Static memory allocation used. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_ConfigAltChanged(void) +{ + uint8 ep; + uint8 cur_ep; + uint8 i; + uint8 ep_type; + uint8 ri; + + const T_USBFS_LUT CYCODE *pTmp; + const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP; + + + /* Init Endpoints and Device Status if configured */ + if(USBFS_configuration > 0u) + { + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + pTmp = &pTmp[1u]; + ep = pTmp->c; /* For this table, c is the number of endpoints configurations */ + + /* Do not touch EP which doesn't need reconfiguration */ + /* When Alt setting changed, the only required endpoints need to be reconfigured */ + /* p_list points the endpoint setting table. */ + pEP = (const T_USBFS_EP_SETTINGS_BLOCK CYCODE *) pTmp->p_list; + for (i = 0u; i < ep; i++) + { + /*If Alt setting changed and new is same with EP Alt */ + if((USBFS_interfaceSetting[pEP->interface] != + USBFS_interfaceSetting_last[pEP->interface] ) && + (USBFS_interfaceSetting[pEP->interface] == pEP->altSetting) && + (pEP->interface == CY_GET_REG8(USBFS_wIndexLo))) + { + cur_ep = pEP->addr & USBFS_DIR_UNUSED; + ri = ((cur_ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); + ep_type = pEP->attributes & USBFS_EP_TYPE_MASK; + if ((pEP->addr & USBFS_DIR_IN) != 0u) + { + /* IN Endpoint */ + USBFS_EP[cur_ep].apiEpState = USBFS_EVENT_PENDING; + USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ? + USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN; + } + else + { + /* OUT Endpoint */ + USBFS_EP[cur_ep].apiEpState = USBFS_NO_EVENT_PENDING; + USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ? + USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT; + } + /* Change the SIE mode for the selected EP to NAK ALL */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_IN_OUT); + USBFS_EP[cur_ep].bufferSize = pEP->bufferSize; + USBFS_EP[cur_ep].addr = pEP->addr; + USBFS_EP[cur_ep].attrib = pEP->attributes; + + /* Clear the data toggle */ + USBFS_EP[cur_ep].epToggle = 0u; + + /* Dynamic reconfiguration for mode 3 transfer */ + #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + /* In_data_rdy for selected EP should be set to 0 */ + * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= (uint8)~USBFS_ARB_EPX_CFG_IN_DATA_RDY; + + /* write the EP number for which reconfiguration is required */ + USBFS_DYN_RECONFIG_REG = (cur_ep - USBFS_EP1) << + USBFS_DYN_RECONFIG_EP_SHIFT; + /* Set the dyn_config_en bit in dynamic reconfiguration register */ + USBFS_DYN_RECONFIG_REG |= USBFS_DYN_RECONFIG_ENABLE; + /* wait for the dyn_config_rdy bit to set by the block, + * this bit will be set to 1 when block is ready for reconfiguration. + */ + while((USBFS_DYN_RECONFIG_REG & USBFS_DYN_RECONFIG_RDY_STS) == 0u) + { + ; + } + /* Once dyn_config_rdy bit is set, FW can change the EP configuration. */ + /* Change EP Type with new direction */ + if((pEP->addr & USBFS_DIR_IN) == 0u) + { + USBFS_EP_TYPE_REG |= (uint8)(0x01u << (cur_ep - USBFS_EP1)); + } + else + { + USBFS_EP_TYPE_REG &= (uint8)~(uint8)(0x01u << (cur_ep - USBFS_EP1)); + } + /* dynamic reconfiguration enable bit cleared, pointers and control/status + * signals for the selected EP is cleared/re-initialized on negative edge + * of dynamic reconfiguration enable bit). + */ + USBFS_DYN_RECONFIG_REG &= (uint8)~USBFS_DYN_RECONFIG_ENABLE; + /* The main loop has to re-enable DMA and OUT endpoint*/ + #else + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri), + USBFS_EP[cur_ep].bufferSize >> 8u); + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + ri), + USBFS_EP[cur_ep].bufferSize & 0xFFu); + CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_IND + ri), + USBFS_EP[cur_ep].buffOffset & 0xFFu); + CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_MSB_IND + ri), + USBFS_EP[cur_ep].buffOffset >> 8u); + CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + ri), + USBFS_EP[cur_ep].buffOffset & 0xFFu); + CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + ri), + USBFS_EP[cur_ep].buffOffset >> 8u); + #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ + } + /* Get next EP element */ + pEP = &pEP[1u]; + } + } /* USBFS_configuration > 0 */ +} + + +/******************************************************************************* +* Function Name: USBFS_GetConfigTablePtr +******************************************************************************** +* +* Summary: +* This routine returns a pointer a configuration table entry +* +* Parameters: +* c: Configuration Index +* +* Return: +* Device Descriptor pointer. +* +*******************************************************************************/ +const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 c) + +{ + /* Device Table */ + const T_USBFS_LUT CYCODE *pTmp; + + pTmp = (const T_USBFS_LUT CYCODE *) USBFS_TABLE[USBFS_device].p_list; + + /* The first entry points to the Device Descriptor, + * the rest configuration entries. + */ + return( (const T_USBFS_LUT CYCODE *) pTmp[c + 1u].p_list ); +} + + +/******************************************************************************* +* Function Name: USBFS_GetDeviceTablePtr +******************************************************************************** +* +* Summary: +* This routine returns a pointer to the Device table +* +* Parameters: +* None. +* +* Return: +* Device Table pointer +* +*******************************************************************************/ +const T_USBFS_LUT CYCODE *USBFS_GetDeviceTablePtr(void) + +{ + /* Device Table */ + return( (const T_USBFS_LUT CYCODE *) USBFS_TABLE[USBFS_device].p_list ); +} + + +/******************************************************************************* +* Function Name: USB_GetInterfaceClassTablePtr +******************************************************************************** +* +* Summary: +* This routine returns Interface Class table pointer, which contains +* the relation between interface number and interface class. +* +* Parameters: +* None. +* +* Return: +* Interface Class table pointer. +* +*******************************************************************************/ +const uint8 CYCODE *USBFS_GetInterfaceClassTablePtr(void) + +{ + const T_USBFS_LUT CYCODE *pTmp; + uint8 currentInterfacesNum; + + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + currentInterfacesNum = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES]; + /* Third entry in the LUT starts the Interface Table pointers */ + /* The INTERFACE_CLASS table is located after all interfaces */ + pTmp = &pTmp[currentInterfacesNum + 2u]; + return( (const uint8 CYCODE *) pTmp->p_list ); +} + + +/******************************************************************************* +* Function Name: USBFS_TerminateEP +******************************************************************************** +* +* Summary: +* This function terminates the specified USBFS endpoint. +* This function should be used before endpoint reconfiguration. +* +* Parameters: +* Endpoint number. +* +* Return: +* None. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_TerminateEP(uint8 ep) +{ + uint8 ri; + + ep &= USBFS_DIR_UNUSED; + ri = ((ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); + + if ((ep > USBFS_EP0) && (ep < USBFS_MAX_EP)) + { + /* Set the endpoint Halt */ + USBFS_EP[ep].hwEpState |= (USBFS_ENDPOINT_STATUS_HALT); + + /* Clear the data toggle */ + USBFS_EP[ep].epToggle = 0u; + USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_ALLOWED; + + if ((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u) + { + /* IN Endpoint */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_IN); + } + else + { + /* OUT Endpoint */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_OUT); + } + } +} + + +/******************************************************************************* +* Function Name: USBFS_SetEndpointHalt +******************************************************************************** +* +* Summary: +* This routine handles set endpoint halt. +* +* Parameters: +* None. +* +* Return: +* requestHandled. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_SetEndpointHalt(void) +{ + uint8 ep; + uint8 ri; + uint8 requestHandled = USBFS_FALSE; + + /* Set endpoint halt */ + ep = CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED; + ri = ((ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); + + if ((ep > USBFS_EP0) && (ep < USBFS_MAX_EP)) + { + /* Set the endpoint Halt */ + USBFS_EP[ep].hwEpState |= (USBFS_ENDPOINT_STATUS_HALT); + + /* Clear the data toggle */ + USBFS_EP[ep].epToggle = 0u; + USBFS_EP[ep].apiEpState |= USBFS_NO_EVENT_ALLOWED; + + if ((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u) + { + /* IN Endpoint */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_STALL_DATA_EP | + USBFS_MODE_ACK_IN); + } + else + { + /* OUT Endpoint */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_STALL_DATA_EP | + USBFS_MODE_ACK_OUT); + } + requestHandled = USBFS_InitNoDataControlTransfer(); + } + + return(requestHandled); +} + + +/******************************************************************************* +* Function Name: USBFS_ClearEndpointHalt +******************************************************************************** +* +* Summary: +* This routine handles clear endpoint halt. +* +* Parameters: +* None. +* +* Return: +* requestHandled. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_ClearEndpointHalt(void) +{ + uint8 ep; + uint8 ri; + uint8 requestHandled = USBFS_FALSE; + + /* Clear endpoint halt */ + ep = CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED; + ri = ((ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); + + if ((ep > USBFS_EP0) && (ep < USBFS_MAX_EP)) + { + /* Clear the endpoint Halt */ + USBFS_EP[ep].hwEpState &= (uint8)~(USBFS_ENDPOINT_STATUS_HALT); + + /* Clear the data toggle */ + USBFS_EP[ep].epToggle = 0u; + /* Clear toggle bit for already armed packet */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri), CY_GET_REG8( + (reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri)) & (uint8)~USBFS_EPX_CNT_DATA_TOGGLE); + /* Return API State as it was defined before */ + USBFS_EP[ep].apiEpState &= (uint8)~USBFS_NO_EVENT_ALLOWED; + + if ((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u) + { + /* IN Endpoint */ + if(USBFS_EP[ep].apiEpState == USBFS_IN_BUFFER_EMPTY) + { /* Wait for next packet from application */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_IN); + } + else /* Continue armed transfer */ + { + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_ACK_IN); + } + } + else + { + /* OUT Endpoint */ + if(USBFS_EP[ep].apiEpState == USBFS_OUT_BUFFER_FULL) + { /* Allow application to read full buffer */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_OUT); + } + else /* Mark endpoint as empty, so it will be reloaded */ + { + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_ACK_OUT); + } + } + requestHandled = USBFS_InitNoDataControlTransfer(); + } + + return(requestHandled); +} + + +/******************************************************************************* +* Function Name: USBFS_ValidateAlternateSetting +******************************************************************************** +* +* Summary: +* Validates (and records) a SET INTERFACE request. +* +* Parameters: +* None. +* +* Return: +* requestHandled. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_ValidateAlternateSetting(void) +{ + uint8 requestHandled = USBFS_TRUE; + uint8 interfaceNum; + const T_USBFS_LUT CYCODE *pTmp; + uint8 currentInterfacesNum; + + interfaceNum = CY_GET_REG8(USBFS_wIndexLo); + /* Validate interface setting, stall if invalid. */ + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + currentInterfacesNum = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES]; + + if((interfaceNum >= currentInterfacesNum) || (interfaceNum >= USBFS_MAX_INTERFACES_NUMBER)) + { /* Wrong interface number */ + requestHandled = USBFS_FALSE; + } + else + { + /* Save current Alt setting to find out the difference in Config() function */ + USBFS_interfaceSetting_last[interfaceNum] = USBFS_interfaceSetting[interfaceNum]; + USBFS_interfaceSetting[interfaceNum] = CY_GET_REG8(USBFS_wValueLo); + } + + return (requestHandled); +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_vnd.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_vnd.c new file mode 100755 index 00000000..6543a676 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/USBFS_vnd.c @@ -0,0 +1,96 @@ +/******************************************************************************* +* File Name: USBFS_vnd.c +* Version 2.60 +* +* Description: +* USB vendor request handler. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS.h" +#include "USBFS_pvt.h" + +#if(USBFS_EXTERN_VND == USBFS_FALSE) + + +/*************************************** +* Vendor Specific Declarations +***************************************/ + +/* `#START VENDOR_SPECIFIC_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +/******************************************************************************* +* Function Name: USBFS_HandleVendorRqst +******************************************************************************** +* +* Summary: +* This routine provide users with a method to implement vendor specifc +* requests. +* +* To implement vendor specific requests, add your code in this function to +* decode and disposition the request. If the request is handled, your code +* must set the variable "requestHandled" to TRUE, indicating that the +* request has been handled. +* +* Parameters: +* None. +* +* Return: +* requestHandled. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_HandleVendorRqst(void) +{ + uint8 requestHandled = USBFS_FALSE; + + if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H) + { + /* Control Read */ + switch (CY_GET_REG8(USBFS_bRequest)) + { + case USBFS_GET_EXTENDED_CONFIG_DESCRIPTOR: + #if defined(USBFS_ENABLE_MSOS_STRING) + USBFS_currentTD.pData = (volatile uint8 *)&USBFS_MSOS_CONFIGURATION_DESCR[0u]; + USBFS_currentTD.count = USBFS_MSOS_CONFIGURATION_DESCR[0u]; + requestHandled = USBFS_InitControlRead(); + #endif /* End USBFS_ENABLE_MSOS_STRING */ + break; + default: + break; + } + } + + /* `#START VENDOR_SPECIFIC_CODE` Place your vendor specific request here */ + + /* `#END` */ + + return(requestHandled); +} + + +/******************************************************************************* +* Additional user functions supporting Vendor Specific Requests +********************************************************************************/ + +/* `#START VENDOR_SPECIFIC_FUNCTIONS` Place any additional functions here */ + +/* `#END` */ + + +#endif /* USBFS_EXTERN_VND */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cm3gcc.ld b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cm3gcc.ld new file mode 100755 index 00000000..784e93eb --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cm3gcc.ld @@ -0,0 +1,295 @@ +/* Linker script for ARM M-profile Simulator + * + * Version: Sourcery G++ Lite 2010q1-188 + * Support: https://support.codesourcery.com/GNUToolchain/ + * + * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc. + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +ENTRY(__cy_reset) +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) + + +MEMORY +{ + rom (rx) : ORIGIN = 0x0, LENGTH = 131072 + ram (rwx) : ORIGIN = 0x20000000 - (32768 / 2), LENGTH = 32768 +} + + +CY_APPL_ORIGIN = 0; +CY_FLASH_ROW_SIZE = 256; +CY_ECC_ROW_SIZE = 32; +CY_EE_IN_BTLDR = 0x00; +CY_APPL_LOADABLE = 1; +CY_EE_SIZE = 2048; +CY_APPL_NUM = 1; +CY_APPL_MAX = 1; +CY_METADATA_SIZE = 64; + + +/* These force the linker to search for particular symbols from + * the start of the link process and thus ensure the user's + * overrides are picked up + */ +EXTERN(Reset) + +/* Bring in the interrupt routines & vector */ +EXTERN(main) + +/* Bring in the meta data */ +EXTERN(cy_meta_loader cy_bootloader cy_meta_loadable cy_meta_bootloader) +EXTERN(cy_meta_custnvl cy_meta_wolatch cy_meta_flashprotect cy_metadata) + +/* Provide fall-back values */ +PROVIDE(__cy_heap_start = _end); +PROVIDE(__cy_region_num = (__cy_regions_end - __cy_regions) / 16); +PROVIDE(__cy_stack = ORIGIN(ram) + LENGTH(ram)); +PROVIDE(__cy_heap_end = __cy_stack - 0x4000); + + +SECTIONS +{ + /* The bootloader location */ + .cybootloader 0x0 : { KEEP(*(.cybootloader)) } >rom + + /* Calculate where the loadables should start */ + appl1_start = CY_APPL_ORIGIN ? CY_APPL_ORIGIN : ALIGN(CY_FLASH_ROW_SIZE); + appl2_start = appl1_start + ALIGN((LENGTH(rom) - appl1_start - 2 * CY_FLASH_ROW_SIZE) / 2, CY_FLASH_ROW_SIZE); + appl_start = (CY_APPL_NUM == 1) ? appl1_start : appl2_start; + ecc_offset = (appl_start / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE; + ee_offset = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? ((CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1)) : 0; + ee_size = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? (CY_EE_SIZE / CY_APPL_MAX) : CY_EE_SIZE; + PROVIDE(CY_ECC_OFFSET = ecc_offset); + + .text appl_start : + { + CREATE_OBJECT_SYMBOLS + PROVIDE(__cy_interrupt_vector = RomVectors); + + *(.romvectors) + + /* Make sure we pulled in an interrupt vector. */ + ASSERT (. != __cy_interrupt_vector, "No interrupt vector"); + + ASSERT (CY_APPL_ORIGIN ? (SIZEOF(.cybootloader) <= CY_APPL_ORIGIN) : 1, "Wrong image location"); + + PROVIDE(__cy_reset = Reset); + *(.text.Reset) + /* Make sure we pulled in some reset code. */ + ASSERT (. != __cy_reset, "No reset code"); + + /* Place the DMA initialization before text to ensure it gets placed in first 64K of flash */ + *(.dma_init) + ASSERT(appl_start + . <= 0x10000 || !0, "DMA Init must be within the first 64k of flash"); + + *(.text .text.* .gnu.linkonce.t.*) + *(.plt) + *(.gnu.warning) + *(.glue_7t) *(.glue_7) *(.vfp11_veneer) + + KEEP(*(.bootloader)) /* necessary for bootloader's, but doesn't impact non-bootloaders */ + + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.gcc_except_table) + } >rom + .eh_frame_hdr : ALIGN (4) + { + KEEP (*(.eh_frame_hdr)) + } >rom + .eh_frame : ALIGN (4) + { + KEEP (*(.eh_frame)) + } >rom + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >rom + __exidx_end = .; + .rodata : ALIGN (4) + { + *(.rodata .rodata.* .gnu.linkonce.r.*) + + . = ALIGN(4); + KEEP(*(.init)) + + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + __cy_regions = .; + LONG (__cy_region_init_ram) + LONG (__cy_region_start_data) + LONG (__cy_region_init_size_ram) + LONG (__cy_region_zero_size_ram) + __cy_regions_end = .; + + . = ALIGN (8); + _etext = .; + } >rom + + .ramvectors (NOLOAD) : ALIGN(8) + { + __cy_region_start_ram = .; + KEEP(*(.ramvectors)) + } + + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } + + .data : ALIGN(8) + { + __cy_region_start_data = .; + + KEEP(*(.jcr)) + *(.got.plt) *(.got) + *(.shdata) + *(.data .data.* .gnu.linkonce.d.*) + . = ALIGN (8); + *(.ram) + _edata = .; + } >ram AT>rom + .bss : ALIGN(8) + { + PROVIDE(__bss_start__ = .); + *(.shbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + *(.ram.b) + _end = .; + __end = .; + } >ram AT>rom + PROVIDE(end = .); + PROVIDE(__bss_end__ = .); + + __cy_region_init_ram = LOADADDR (.data); + __cy_region_init_size_ram = _edata - ADDR (.data); + __cy_region_zero_size_ram = _end - _edata; + + /* The .stack and .heap sections don't contain any symbols. + * They are only used for linker to calculate RAM utilization. + */ + .heap (NOLOAD) : + { + . = _end; + . += 0x1000; + __cy_heap_limit = .; + } >ram + + .stack (__cy_stack - 0x4000) (NOLOAD) : + { + __cy_stack_limit = .; + . += 0x4000; + } >ram + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__cy_stack_limit >= __cy_heap_limit, "region RAM overflowed with stack") + + .cyloadermeta ((appl_start == 0) ? (LENGTH(rom) - CY_METADATA_SIZE) : 0xF0000000) : + { + KEEP(*(.cyloadermeta)) + } :NONE + + .cyloadablemeta (LENGTH(rom) - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) : + { + KEEP(*(.cyloadablemeta)) + } >rom + + .cyconfigecc (0x80000000 + ecc_offset) : + { + KEEP(*(.cyconfigecc)) + } :NONE + + .cycustnvl 0x90000000 : { KEEP(*(.cycustnvl)) } :NONE + .cywolatch 0x90100000 : { KEEP(*(.cywolatch)) } :NONE + + .cyeeprom (0x90200000 + ee_offset) : + { + KEEP(*(.cyeeprom)) + ASSERT(. <= (0x90200000 + ee_offset + ee_size), ".cyeeprom data will not fit in EEPROM"); + } :NONE + + .cyflashprotect 0x90400000 : { KEEP(*(.cyflashprotect)) } :NONE + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE + + .stab 0 (NOLOAD) : { *(.stab) } + .stabstr 0 (NOLOAD) : { *(.stabstr) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. + */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* DWARF 2.1 */ + .debug_ranges 0 : { *(.debug_ranges) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) } + .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) } + /DISCARD/ : { *(.note.GNU-stack) } +} + diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/core_cm3.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/core_cm3.h new file mode 100755 index 00000000..122c9aa4 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/core_cm3.h @@ -0,0 +1,1627 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200 + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h new file mode 100755 index 00000000..cb5d1655 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h @@ -0,0 +1,54 @@ +/******************************************************************************* +* File Name: core_cm3_psoc5.h +* Version 4.0 +* +* Description: +* Provides important type information for the PSoC5. This includes types +* necessary for core_cm3.h. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + + +#if !defined(__CORE_CM3_PSOC5_H__) +#define __CORE_CM3_PSOC5_H__ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1 /*!< 15 Cortex-M3 System Tick Interrupt */ +/****** PSoC5 Peripheral Interrupt Numbers *******************************************************/ + /* Not relevant. All peripheral interrupts are defined by the user */ +} IRQn_Type; + +#include + +#define __CHECK_DEVICE_DEFINES + +#define __CM3_REV 0x0201 + +#define __MPU_PRESENT 0 +#define __NVIC_PRIO_BITS 3 +#define __Vendor_SysTickConfig 0 + +#include + + +#endif /* __CORE_CM3_PSOC5_H__ */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/core_cmFunc.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/core_cmFunc.h new file mode 100755 index 00000000..0a18fafc --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/core_cmFunc.h @@ -0,0 +1,636 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CORE_CMFUNC_H */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/core_cmInstr.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/core_cmInstr.h new file mode 100755 index 00000000..ab3a0109 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/core_cmInstr.h @@ -0,0 +1,688 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V3.20 + * @date 05. March 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + uint32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return(result); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return(result); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyPm.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyPm.c new file mode 100755 index 00000000..9906255c --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyPm.c @@ -0,0 +1,1819 @@ +/******************************************************************************* +* File Name: cyPm.c +* Version 4.0 +* +* Description: +* Provides an API for the power management. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cyPm.h" + + +/******************************************************************* +* Place your includes, defines and code here. Do not use merge +* region below unless any component datasheet suggest to do so. +*******************************************************************/ +/* `#START CY_PM_HEADER_INCLUDE` */ + +/* `#END` */ + + +static CY_PM_BACKUP_STRUCT cyPmBackup; +static CY_PM_CLOCK_BACKUP_STRUCT cyPmClockBackup; + +/* Convertion table between register's values and frequency in MHz */ +static const uint8 CYCODE cyPmImoFreqReg2Mhz[7u] = {12u, 6u, 24u, 3u, 48u, 62u, 74u}; + +/* Function Prototypes */ +static void CyPmHibSaveSet(void); +static void CyPmHibRestore(void) ; + +static void CyPmHibSlpSaveSet(void) ; +static void CyPmHibSlpRestore(void) ; + +static void CyPmHviLviSaveDisable(void) ; +static void CyPmHviLviRestore(void) ; + + +/******************************************************************************* +* Function Name: CyPmSaveClocks +******************************************************************************** +* +* Summary: +* This function is called in preparation for entering sleep or hibernate low +* power modes. Saves all state of the clocking system that does not persist +* during sleep/hibernate or that needs to be altered in preparation for +* sleep/hibernate. Shutdowns all the digital and analog clock dividers for the +* active power mode configuration. +* +* Switches the master clock over to the IMO and shuts down the PLL and MHz +* Crystal. The IMO frequency is set to either 12 MHz or 48 MHz to match the +* Design-Wide Resources System Editor "Enable Fast IMO During Startup" setting. +* The ILO and 32 KHz oscillators are not impacted. The current Flash wait state +* setting is saved and the Flash wait state setting is set for the current IMO +* speed. +* +* Note If the Master Clock source is routed through the DSI inputs, then it +* must be set manually to another source before using the +* CyPmSaveClocks()/CyPmRestoreClocks() functions. +* +* Parameters: +* None +* +* Return: +* None +* +* Side Effects: +* All peripheral clocks are going to be off after this API method call. +* +*******************************************************************************/ +void CyPmSaveClocks(void) +{ + /* Digital and analog clocks - save enable state and disable them all */ + cyPmClockBackup.enClkA = CY_PM_ACT_CFG1_REG & CY_PM_ACT_EN_CLK_A_MASK; + cyPmClockBackup.enClkD = CY_PM_ACT_CFG2_REG; + CY_PM_ACT_CFG1_REG &= ((uint8)(~CY_PM_ACT_EN_CLK_A_MASK)); + CY_PM_ACT_CFG2_REG &= ((uint8)(~CY_PM_ACT_EN_CLK_D_MASK)); + + /* Save current flash wait cycles and set the maximum value */ + cyPmClockBackup.flashWaitCycles = CY_PM_CACHE_CR_CYCLES_MASK & CY_PM_CACHE_CR_REG; + CyFlash_SetWaitCycles(CY_PM_MAX_FLASH_WAIT_CYCLES); + + /* IMO - save current IMO MHz OSC frequency and USB mode is on bit */ + cyPmClockBackup.imoFreq = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK; + cyPmClockBackup.imoUsbClk = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_USB; + + /* IMO doubler - save enable state */ + if(0u != (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_F2XON)) + { + /* IMO doubler enabled - save and disable */ + cyPmClockBackup.imo2x = CY_PM_ENABLED; + } + else + { + /* IMO doubler disabled */ + cyPmClockBackup.imo2x = CY_PM_DISABLED; + } + + /* IMO - set appropriate frequency for LPM */ + CyIMO_SetFreq(CY_PM_IMO_FREQ_LPM); + + /* IMO - save enable state and enable without wait to settle */ + if(0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG)) + { + /* IMO - save enabled state */ + cyPmClockBackup.imoEnable = CY_PM_ENABLED; + } + else + { + /* IMO - save disabled state */ + cyPmClockBackup.imoEnable = CY_PM_DISABLED; + + /* IMO - enable */ + CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE); + } + + /* IMO - save the current IMOCLK source and set to IMO if not yet */ + if(0u != (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_XCLKEN)) + { + /* DSI or XTAL CLK */ + cyPmClockBackup.imoClkSrc = + (0u == (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO2X_SRC)) ? CY_IMO_SOURCE_DSI : CY_IMO_SOURCE_XTAL; + + /* IMO - set IMOCLK source to MHz OSC */ + CyIMO_SetSource(CY_IMO_SOURCE_IMO); + } + else + { + /* IMO */ + cyPmClockBackup.imoClkSrc = CY_IMO_SOURCE_IMO; + } + + /* Save clk_imo source */ + cyPmClockBackup.clkImoSrc = CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO_OUT_MASK; + + /* If IMOCLK2X or SPC OSC is source for clk_imo, set it to IMOCLK */ + if(CY_PM_CLKDIST_IMO_OUT_IMO != cyPmClockBackup.clkImoSrc) + { + /* Set IMOCLK to source for clk_imo */ + CY_PM_CLKDIST_CR_REG = (CY_PM_CLKDIST_CR_REG & ((uint8)(~CY_PM_CLKDIST_IMO_OUT_MASK))) | + CY_PM_CLKDIST_IMO_OUT_IMO; + } /* Need to change nothing if IMOCLK is source clk_imo */ + + /* IMO doubler - disable it (saved above) */ + if(0u != (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_F2XON)) + { + CyIMO_DisableDoubler(); + } + + /* Master clock - save divider and set it to divide-by-one (if no yet) */ + cyPmClockBackup.clkSyncDiv = CY_PM_CLKDIST_MSTR0_REG; + if(CY_PM_DIV_BY_ONE != cyPmClockBackup.clkSyncDiv) + { + CyMasterClk_SetDivider(CY_PM_DIV_BY_ONE); + } /* Need to change nothing if master clock divider is 1 */ + + /* Master clock - save current source */ + cyPmClockBackup.masterClkSrc = CY_PM_CLKDIST_MSTR1_REG & CY_PM_MASTER_CLK_SRC_MASK; + + /* Master clock source - set it to IMO if not yet. */ + if(CY_MASTER_SOURCE_IMO != cyPmClockBackup.masterClkSrc) + { + CyMasterClk_SetSource(CY_MASTER_SOURCE_IMO); + } /* Need to change nothing if master clock source is IMO */ + + /* Bus clock - save divider and set it, if needed, to divide-by-one */ + cyPmClockBackup.clkBusDiv = (uint16) ((uint16) CY_PM_CLK_BUS_MSB_DIV_REG << 8u); + cyPmClockBackup.clkBusDiv |= CY_PM_CLK_BUS_LSB_DIV_REG; + if(CY_PM_BUS_CLK_DIV_BY_ONE != cyPmClockBackup.clkBusDiv) + { + CyBusClk_SetDivider(CY_PM_BUS_CLK_DIV_BY_ONE); + } /* Do nothing if saved and actual values are equal */ + + /* Set number of wait cycles for the flash according CPU frequency in MHz */ + CyFlash_SetWaitCycles((uint8)CY_PM_GET_CPU_FREQ_MHZ); + + /* PLL - check enable state, disable if needed */ + if(0u != (CY_PM_FASTCLK_PLL_CFG0_REG & CY_PM_PLL_CFG0_ENABLE)) + { + /* PLL is enabled - save state and disable */ + cyPmClockBackup.pllEnableState = CY_PM_ENABLED; + CyPLL_OUT_Stop(); + } + else + { + /* PLL is disabled - save state */ + cyPmClockBackup.pllEnableState = CY_PM_DISABLED; + } + + /* MHz ECO - check enable state and disable if needed */ + if(0u != (CY_PM_FASTCLK_XMHZ_CSR_REG & CY_PM_XMHZ_CSR_ENABLE)) + { + /* MHz ECO is enabled - save state and disable */ + cyPmClockBackup.xmhzEnableState = CY_PM_ENABLED; + CyXTAL_Stop(); + } + else + { + /* MHz ECO is disabled - save state */ + cyPmClockBackup.xmhzEnableState = CY_PM_DISABLED; + } + + + /*************************************************************************** + * Save enable state of delay between the system bus clock and each of the + * 4 individual analog clocks. This bit non-retention and it's value should + * be restored on wakeup. + ***************************************************************************/ + if(0u != (CY_PM_CLKDIST_DELAY_REG & CY_PM_CLKDIST_DELAY_EN)) + { + cyPmClockBackup.clkDistDelay = CY_PM_ENABLED; + } + else + { + cyPmClockBackup.clkDistDelay = CY_PM_DISABLED; + } +} + + +/******************************************************************************* +* Function Name: CyPmRestoreClocks +******************************************************************************** +* +* Summary: +* Restores any state that was preserved by the last call to CyPmSaveClocks(). +* The Flash wait state setting is also restored. +* +* Note If the Master Clock source is routed through the DSI inputs, then it +* must be set manually to another source before using the +* CyPmSaveClocks()/CyPmRestoreClocks() functions. +* +* PSoC 3 and PSoC 5LP: +* The merge region could be used to process state when the megahertz crystal is +* not ready after the hold-off timeout. +* +* PSoC 5: +* The 130 ms is given for the megahertz crystal to stabilize. It's readiness is +* not verified after the hold-off timeout. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyPmRestoreClocks(void) +{ + cystatus status = CYRET_TIMEOUT; + uint16 i; + uint16 clkBusDivTmp; + + + /* Convertion table between CyIMO_SetFreq() parameters and register's value */ + const uint8 CYCODE cyPmImoFreqMhz2Reg[7u] = { + CY_IMO_FREQ_12MHZ, CY_IMO_FREQ_6MHZ, CY_IMO_FREQ_24MHZ, CY_IMO_FREQ_3MHZ, + CY_IMO_FREQ_48MHZ, 5u, 6u}; + + /* Restore enable state of delay between the system bus clock and ACLKs. */ + if(CY_PM_ENABLED == cyPmClockBackup.clkDistDelay) + { + /* Delay for both the bandgap and the delay line to settle out */ + CyDelayCycles((uint32)(CY_PM_CLK_DELAY_BANDGAP_SETTLE_US + CY_PM_CLK_DELAY_BIAS_SETTLE_US) * + CY_PM_GET_CPU_FREQ_MHZ); + + CY_PM_CLKDIST_DELAY_REG |= CY_PM_CLKDIST_DELAY_EN; + } + + /* MHz ECO restore state */ + if(CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState) + { + /*********************************************************************** + * Enabling XMHZ XTAL. The actual CyXTAL_Start() with non zero wait + * period uses FTW for period measurement. This could cause a problem + * if CTW/FTW is used as a wake up time in the low power modes APIs. + * So, the XTAL wait procedure is implemented with a software delay. + ***********************************************************************/ + + /* Enable XMHZ XTAL with no wait */ + (void) CyXTAL_Start(CY_PM_XTAL_MHZ_NO_WAIT); + + /* Read XERR bit to clear it */ + (void) CY_PM_FASTCLK_XMHZ_CSR_REG; + + /* Wait */ + for(i = CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US; i > 0u; i--) + { + /* Make a 200 microseconds delay */ + CyDelayCycles((uint32)CY_PM_WAIT_200_US * CY_PM_GET_CPU_FREQ_MHZ); + + /* High output indicates oscillator failure */ + if(0u == (CY_PM_FASTCLK_XMHZ_CSR_REG & CY_PM_XMHZ_CSR_XERR)) + { + status = CYRET_SUCCESS; + break; + } + } + + if(CYRET_TIMEOUT == status) + { + /******************************************************************* + * Process the situation when megahertz crystal is not ready. + * Time to stabialize value is crystal specific. + *******************************************************************/ + /* `#START_MHZ_ECO_TIMEOUT` */ + + /* `#END` */ + } + } /* (CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState) */ + + + /* Temprorary set the maximum flash wait cycles */ + CyFlash_SetWaitCycles(CY_PM_MAX_FLASH_WAIT_CYCLES); + + /* The XTAL and DSI clocks are ready to be source for Master clock. */ + if((CY_PM_MASTER_CLK_SRC_XTAL == cyPmClockBackup.masterClkSrc) || + (CY_PM_MASTER_CLK_SRC_DSI == cyPmClockBackup.masterClkSrc)) + { + /* Restore Master clock's divider */ + if(CY_PM_CLKDIST_MSTR0_REG != cyPmClockBackup.clkSyncDiv) + { + /* Restore Master clock divider */ + CyMasterClk_SetDivider(cyPmClockBackup.clkSyncDiv); + } + + /* Restore Master clock source */ + CyMasterClk_SetSource(cyPmClockBackup.masterClkSrc); + } + + /* IMO - restore IMO frequency */ + if((0u != (cyPmClockBackup.imoUsbClk & CY_PM_FASTCLK_IMO_CR_USB)) && + (CY_IMO_FREQ_24MHZ == cyPmImoFreqMhz2Reg[cyPmClockBackup.imoFreq])) + { + /* Restore IMO frequency (24 MHz) and trim it for USB */ + CyIMO_SetFreq(CY_IMO_FREQ_USB); + } + else + { + /* Restore IMO frequency */ + CyIMO_SetFreq(cyPmImoFreqMhz2Reg[cyPmClockBackup.imoFreq]); + + if(0u != (cyPmClockBackup.imoUsbClk & CY_PM_FASTCLK_IMO_CR_USB)) + { + CY_PM_FASTCLK_IMO_CR_REG |= CY_PM_FASTCLK_IMO_CR_USB; + } + else + { + CY_PM_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_PM_FASTCLK_IMO_CR_USB)); + } + } + + /* IMO - restore enable state if needed */ + if((CY_PM_ENABLED == cyPmClockBackup.imoEnable) && + (0u == (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG))) + { + /* IMO - restore enabled state */ + CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE); + } + + /* IMO - restore disable state if needed */ + if((CY_PM_DISABLED == cyPmClockBackup.imoEnable) && + (0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG))) + { + CyIMO_Stop(); + } + + /* IMO - restore IMOCLK source */ + CyIMO_SetSource(cyPmClockBackup.imoClkSrc); + + /* Restore IMO doubler enable state (turned off by CyPmSaveClocks()) */ + if(CY_PM_ENABLED == cyPmClockBackup.imo2x) + { + CyIMO_EnableDoubler(); + } + + /* IMO - restore clk_imo source, if needed */ + if(cyPmClockBackup.clkImoSrc != (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO_OUT_MASK)) + { + CY_PM_CLKDIST_CR_REG = (CY_PM_CLKDIST_CR_REG & ((uint8)(~CY_PM_CLKDIST_IMO_OUT_MASK))) | + cyPmClockBackup.clkImoSrc; + } + + /* PLL restore state */ + if(CY_PM_ENABLED == cyPmClockBackup.pllEnableState) + { + /*********************************************************************** + * Enable PLL. The actual CyPLL_OUT_Start() without wait period uses FTW + * for period measurement. This could cause a problem if CTW/FTW is used + * as a wakeup time in the low power modes APIs. To omit this issue PLL + * wait procedure is implemented with a software delay. + ***********************************************************************/ + + /* Enable PLL */ + (void) CyPLL_OUT_Start(CY_PM_PLL_OUT_NO_WAIT); + + /* Make a 250 us delay */ + CyDelayCycles((uint32)CY_PM_WAIT_250_US * CY_PM_GET_CPU_FREQ_MHZ); + } /* (CY_PM_ENABLED == cyPmClockBackup.pllEnableState) */ + + + /* PLL and IMO is ready to be source for Master clock */ + if((CY_PM_MASTER_CLK_SRC_IMO == cyPmClockBackup.masterClkSrc) || + (CY_PM_MASTER_CLK_SRC_PLL == cyPmClockBackup.masterClkSrc)) + { + /* Restore Master clock divider */ + if(CY_PM_CLKDIST_MSTR0_REG != cyPmClockBackup.clkSyncDiv) + { + CyMasterClk_SetDivider(cyPmClockBackup.clkSyncDiv); + } + + /* Restore Master clock source */ + CyMasterClk_SetSource(cyPmClockBackup.masterClkSrc); + } + + /* Bus clock - restore divider, if needed */ + clkBusDivTmp = (uint16) ((uint16)CY_PM_CLK_BUS_MSB_DIV_REG << 8u); + clkBusDivTmp |= CY_PM_CLK_BUS_LSB_DIV_REG; + if(cyPmClockBackup.clkBusDiv != clkBusDivTmp) + { + CyBusClk_SetDivider(cyPmClockBackup.clkBusDiv); + } + + /* Restore flash wait cycles */ + CY_PM_CACHE_CR_REG = ((CY_PM_CACHE_CR_REG & ((uint8)(~CY_PM_CACHE_CR_CYCLES_MASK))) | + cyPmClockBackup.flashWaitCycles); + + /* Digital and analog clocks - restore state */ + CY_PM_ACT_CFG1_REG = cyPmClockBackup.enClkA; + CY_PM_ACT_CFG2_REG = cyPmClockBackup.enClkD; +} + + +/******************************************************************************* +* Function Name: CyPmAltAct +******************************************************************************** +* +* Summary: +* Puts the part into the Alternate Active (Standby) state. The Alternate Active +* state can allow for any of the capabilities of the device to be active, but +* the operation of this function is dependent on the CPU being disabled during +* the Alternate Active state. The configuration code and the component APIs +* will configure the template for the Alternate Active state to be the same as +* the Active state with the exception that the CPU will be disabled during +* Alternate Active. +* +* Note Before calling this function, you must manually configure the power mode +* of the source clocks for the timer that is used as the wakeup timer. +* +* PSoC 3: +* Before switching to Alternate Active, if a wakeupTime other than NONE is +* specified, then the appropriate timer state is configured as specified with +* the interrupt for that timer disabled. The wakeup source will be the +* combination of the values specified in the wakeupSource and any timer +* specified in the wakeupTime argument. Once the wakeup condition is +* satisfied, then all saved state is restored and the function returns in the +* Active state. +* +* Note that if the wakeupTime is made with a different value, the period before +* the wakeup occurs can be significantly shorter than the specified time. If +* the next call is made with the same wakeupTime value, then the wakeup will +* occur the specified period after the previous wakeup occurred. +* +* If a wakeupTime other than NONE is specified, then upon exit the state of the +* specified timer will be left as specified by wakeupTime with the timer +* enabled and the interrupt disabled. If the CTW, FTW or One PPS is already +* configured for wakeup, for example with the SleepTimer or RTC components, +* then specify NONE for the wakeupTime and include the appropriate source for +* wakeupSource. +* +* PSoC 5LP: +* This function is used to both enter the Alternate Active mode and halt the +* processor. For PSoC 3 these two actions must be paired together. With PSoC +* 5LP the processor can be halted independently with the __WFI() function from +* the CMSIS library that is included in Creator. This function should be used +* instead when the action required is just to halt the processor until an +* enabled interrupt occurs. +* +* The wakeupTime parameter is not used for this device. It must be set to zero +* (PM_ALT_ACT_TIME_NONE). The wake up time configuration can be done by a +* separate component: the CTW wakeup interval should be configured with the +* Sleep Timer component and one second interval should be configured with the +* RTC component. +* +* The wakeup behavior depends on wakeupSource parameter in the following +* manner: upon function execution the device will be switched from Active to +* Alternate Active mode and then the CPU will be halted. When an enabled wakeup +* event occurs the device will return to Active mode. Similarly when an +* enabled interrupt occurs the CPU will be started. These two actions will +* occur together provided that the event that occurs is an enabled wakeup +* source and also generates an interrupt. If just the wakeup event occurs then +* the device will be in Active mode, but the CPU will remain halted waiting for +* an interrupt. If an interrupt occurs from something other than a wakeup +* source, then the CPU will restart with the device in Alternate Active mode +* until a wakeup event occurs. +* +* For example, if CyPmAltAct(PM_ALT_ACT_TIME_NONE, PM_ALT_ACT_SRC_PICU) is +* called and PICU interrupt occurs, the CPU will be started and device will be +* switched into Active mode. And if CyPmAltAct(PM_ALT_ACT_TIME_NONE, +* PM_ALT_ACT_SRC_NONE) is called and PICU interrupt occurs, the CPU will be +* started while device remains in Alternate Active mode. +* +* Parameters: +* wakeupTime: Specifies a timer wakeup source and the frequency of that +* source. For PSoC 5LP this parameter is ignored. +* +* Define Time +* PM_ALT_ACT_TIME_NONE None +* PM_ALT_ACT_TIME_ONE_PPS One PPS: 1 second +* PM_ALT_ACT_TIME_CTW_2MS CTW: 2 ms +* PM_ALT_ACT_TIME_CTW_4MS CTW: 4 ms +* PM_ALT_ACT_TIME_CTW_8MS CTW: 8 ms +* PM_ALT_ACT_TIME_CTW_16MS CTW: 16 ms +* PM_ALT_ACT_TIME_CTW_32MS CTW: 32 ms +* PM_ALT_ACT_TIME_CTW_64MS CTW: 64 ms +* PM_ALT_ACT_TIME_CTW_128MS CTW: 128 ms +* PM_ALT_ACT_TIME_CTW_256MS CTW: 256 ms +* PM_ALT_ACT_TIME_CTW_512MS CTW: 512 ms +* PM_ALT_ACT_TIME_CTW_1024MS CTW: 1024 ms +* PM_ALT_ACT_TIME_CTW_2048MS CTW: 2048 ms +* PM_ALT_ACT_TIME_CTW_4096MS CTW: 4096 ms +* PM_ALT_ACT_TIME_FTW(1-256)* FTW: 10us to 2.56 ms +* +* *Note: PM_ALT_ACT_TIME_FTW() is a macro that takes an argument that +* specifies how many increments of 10 us to delay. + For PSoC 3 silicon the valid range of values is 1 to 256. +* +* wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if +* a wakeupTime has been specified the associated timer will be +* included as a wakeup source. +* +* Define Source +* PM_ALT_ACT_SRC_NONE None +* PM_ALT_ACT_SRC_COMPARATOR0 Comparator 0 +* PM_ALT_ACT_SRC_COMPARATOR1 Comparator 1 +* PM_ALT_ACT_SRC_COMPARATOR2 Comparator 2 +* PM_ALT_ACT_SRC_COMPARATOR3 Comparator 3 +* PM_ALT_ACT_SRC_INTERRUPT Interrupt +* PM_ALT_ACT_SRC_PICU PICU +* PM_ALT_ACT_SRC_I2C I2C +* PM_ALT_ACT_SRC_BOOSTCONVERTER Boost Converter +* PM_ALT_ACT_SRC_FTW Fast Timewheel* +* PM_ALT_ACT_SRC_VD High and Low Voltage Detection (HVI, LVI)* +* PM_ALT_ACT_SRC_CTW Central Timewheel** +* PM_ALT_ACT_SRC_ONE_PPS One PPS** +* PM_ALT_ACT_SRC_LCD LCD +* +* *Note : FTW and HVI/LVI wakeup signals are in the same mask bit. +* **Note: CTW and One PPS wakeup signals are in the same mask bit. +* +* When specifying a Comparator as the wakeupSource an instance specific define +* should be used that will track with the specific comparator that the instance +* is placed into. As an example, for a Comparator instance named MyComp the +* value to OR into the mask is: MyComp_ctComp__CMP_MASK. +* +* When CTW, FTW or One PPS is used as a wakeup source, the CyPmReadStatus() +* function must be called upon wakeup with corresponding parameter. Please +* refer to the CyPmReadStatus() API in the System Reference Guide for more +* information. +* +* Return: +* None +* +* Reentrant: +* No +* +* Side Effects: +* If a wakeupTime other than NONE is specified, then upon exit the state of the +* specified timer will be left as specified by wakeupTime with the timer +* enabled and the interrupt disabled. Also, the ILO 1 KHz (if CTW timer is +* used as wakeup time) or ILO 100 KHz (if FTW timer is used as wakeup time) +* will be left started. +* +*******************************************************************************/ +void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource) +{ + #if(CY_PSOC5) + + /* Arguments expected to be 0 */ + CYASSERT(PM_ALT_ACT_TIME_NONE == wakeupTime); + + if(0u != wakeupTime) + { + /* To remove unreferenced local variable warning */ + } + + #endif /* (CY_PSOC5) */ + + + #if(CY_PSOC3) + + /* FTW - save current and set new configuration */ + if((wakeupTime >= PM_ALT_ACT_TIME_FTW(1u)) && (wakeupTime <= PM_ALT_ACT_TIME_FTW(256u))) + { + CyPmFtwSetInterval(PM_ALT_ACT_FTW_INTERVAL(wakeupTime)); + + /* Include associated timer to the wakeupSource */ + wakeupSource |= PM_ALT_ACT_SRC_FTW; + } + + /* CTW - save current and set new configuration */ + if((wakeupTime >= PM_ALT_ACT_TIME_CTW_2MS) && (wakeupTime <= PM_ALT_ACT_TIME_CTW_4096MS)) + { + /* Save current CTW configuration and set new one */ + CyPmCtwSetInterval((uint8)(wakeupTime - 1u)); + + /* Include associated timer to the wakeupSource */ + wakeupSource |= PM_ALT_ACT_SRC_CTW; + } + + /* 1PPS - save current and set new configuration */ + if(PM_ALT_ACT_TIME_ONE_PPS == wakeupTime) + { + /* Save current 1PPS configuration and set new one */ + CyPmOppsSet(); + + /* Include associated timer to the wakeupSource */ + wakeupSource |= PM_ALT_ACT_SRC_ONE_PPS; + } + + #endif /* (CY_PSOC3) */ + + + /* Save and set new wake up configuration */ + + /* Interrupt, PICU, I2C, Boost converter, CTW/1PPS */ + cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG; + CY_PM_WAKEUP_CFG0_REG = (uint8) (wakeupSource >> 4u); + + /* Comparators */ + cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG; + CY_PM_WAKEUP_CFG1_REG = (((uint8) wakeupSource) & CY_PM_WAKEUP_SRC_CMPS_MASK); + + /* LCD */ + cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG; + CY_PM_WAKEUP_CFG2_REG = ((uint8) ((wakeupSource >> 12u) & 0x01u)); + + + /* Switch to the Alternate Active mode */ + CY_PM_MODE_CSR_REG = ((CY_PM_MODE_CSR_REG & ((uint8)(~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_ALT_ACT); + + /* Recommended readback. */ + (void) CY_PM_MODE_CSR_REG; + + /* Two recommended NOPs to get into the mode. */ + CY_NOP; + CY_NOP; + + /* Execute WFI instruction (for ARM-based devices only) */ + CY_PM_WFI; + + /* Point of return from Alternate Active Mode */ + + /* Restore wake up configuration */ + CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0; + CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1; + CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2; +} + + +/******************************************************************************* +* Function Name: CyPmSleep +******************************************************************************** +* +* Summary: +* Puts the part into the Sleep state. +* +* Note Before calling this function, you must manually configure the power +* mode of the source clocks for the timer that is used as wakeup timer. +* +* Note Before calling this function, you must prepare clock tree configuration +* for the low power mode by calling CyPmSaveClocks(). And restore clock +* configuration after CyPmSleep() execution by calling CyPmRestoreClocks(). See +* Power Management section, Clock Configuration subsection of the System +* Reference Guide for more information. +* +* PSoC 3: +* Before switching to Sleep, if a wakeupTime other than NONE is specified, +* then the appropriate timer state is configured as specified with the +* interrupt for that timer disabled. The wakeup source will be the combination +* of the values specified in the wakeupSource and any timer specified in the +* wakeupTime argument. Once the wakeup condition is satisfied, then all saved +* state is restored and the function returns in the Active state. +* +* Note that if the wakeupTime is made with a different value, the period before +* the wakeup occurs can be significantly shorter than the specified time. If +* the next call is made with the same wakeupTime value, then the wakeup will +* occur the specified period after the previous wakeup occurred. +* +* If a wakeupTime other than NONE is specified, then upon exit the state of the +* specified timer will be left as specified by wakeupTime with the timer +* enabled and the interrupt disabled. If the CTW or One PPS is already +* configured for wakeup, for example with the SleepTimer or RTC components, +* then specify NONE for the wakeupTime and include the appropriate source for +* wakeupSource. +* +* PSoC 5LP: +* The wakeupTime parameter is not used and the only NONE can be specified. +* The wakeup time must be configured with the component, SleepTimer for CTW +* intervals and RTC for 1PPS interval. The component must be configured to +* generate an interrrupt. +* +* Parameters: +* wakeupTime: Specifies a timer wakeup source and the frequency of that +* source. For PSoC 5LP, this parameter is ignored. +* +* Define Time +* PM_SLEEP_TIME_NONE None +* PM_SLEEP_TIME_ONE_PPS One PPS: 1 second +* PM_SLEEP_TIME_CTW_2MS CTW: 2 ms +* PM_SLEEP_TIME_CTW_4MS CTW: 4 ms +* PM_SLEEP_TIME_CTW_8MS CTW: 8 ms +* PM_SLEEP_TIME_CTW_16MS CTW: 16 ms +* PM_SLEEP_TIME_CTW_32MS CTW: 32 ms +* PM_SLEEP_TIME_CTW_64MS CTW: 64 ms +* PM_SLEEP_TIME_CTW_128MS CTW: 128 ms +* PM_SLEEP_TIME_CTW_256MS CTW: 256 ms +* PM_SLEEP_TIME_CTW_512MS CTW: 512 ms +* PM_SLEEP_TIME_CTW_1024MS CTW: 1024 ms +* PM_SLEEP_TIME_CTW_2048MS CTW: 2048 ms +* PM_SLEEP_TIME_CTW_4096MS CTW: 4096 ms +* +* wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if +* a wakeupTime has been specified the associated timer will be +* included as a wakeup source. +* +* Define Source +* PM_SLEEP_SRC_NONE None +* PM_SLEEP_SRC_COMPARATOR0 Comparator 0 +* PM_SLEEP_SRC_COMPARATOR1 Comparator 1 +* PM_SLEEP_SRC_COMPARATOR2 Comparator 2 +* PM_SLEEP_SRC_COMPARATOR3 Comparator 3 +* PM_SLEEP_SRC_PICU PICU +* PM_SLEEP_SRC_I2C I2C +* PM_SLEEP_SRC_BOOSTCONVERTER Boost Converter +* PM_SLEEP_SRC_VD High and Low Voltage Detection (HVI, LVI) +* PM_SLEEP_SRC_CTW Central Timewheel* +* PM_SLEEP_SRC_ONE_PPS One PPS* +* PM_SLEEP_SRC_LCD LCD +* +* *Note: CTW and One PPS wakeup signals are in the same mask bit. +* +* When specifying a Comparator as the wakeupSource an instance specific define +* should be used that will track with the specific comparator that the instance +* is placed into. As an example for a Comparator instance named MyComp the +* value to OR into the mask is: MyComp_ctComp__CMP_MASK. +* +* When CTW or One PPS is used as a wakeup source, the CyPmReadStatus() +* function must be called upon wakeup with corresponding parameter. Please +* refer to the CyPmReadStatus() API in the System Reference Guide for more +* information. +* +* Return: +* None +* +* Reentrant: +* No +* +* Side Effects and Restrictions: +* If a wakeupTime other than NONE is specified, then upon exit the state of the +* specified timer will be left as specified by wakeupTime with the timer +* enabled and the interrupt disabled. Also, the ILO 1 KHz (if CTW timer is +* used as wake up time) will be left started. +* +* The 1 kHz ILO clock is expected to be enabled for PSoC 3 and PSoC 5LP to +* measure Hibernate/Sleep regulator settling time after a reset. The holdoff +* delay is measured using rising edges of the 1 kHz ILO. +* +* For PSoC 3 silicon hardware buzz should be disabled before entering a sleep +* power mode. It is disabled by PSoC Creator during startup. +* If a Low Voltage Interrupt (LVI), High Voltage Interrupt (HVI) or Brown Out +* detect (power supply supervising capabilities) are required in a design +* during sleep, use the Central Time Wheel (CTW) to periodically wake the +* device, perform software buzz, and refresh the supervisory services. If LVI, +* HVI, or Brown Out is not required, then use of the CTW is not required. +* Refer to the device errata for more information. +* +*******************************************************************************/ +void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource) +{ + uint8 interruptState; + + /* Save current global interrupt enable and disable it */ + interruptState = CyEnterCriticalSection(); + + + /*********************************************************************** + * The Hibernate/Sleep regulator has a settling time after a reset. + * During this time, the system ignores requests to enter Sleep and + * Hibernate modes. The holdoff delay is measured using rising edges of + * the 1 kHz ILO. + ***********************************************************************/ + if(0u == (CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_PWRUP_PULSE_Q)) + { + /* Disable hold off - no action on restore */ + CY_PM_PWRSYS_SLP_TR_REG &= CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK; + } + else + { + /* Abort, device is not ready for low power mode entry */ + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); + + return; + } + + + /*********************************************************************** + * PSoC3 < TO6: + * - Hardware buzz must be disabled before sleep mode entry. + * - Voltage supervision (HVI/LVI) requires hardware buzz, so they must + * be aslo disabled. + * + * PSoC3 >= TO6: + * - Voltage supervision (HVI/LVI) requires hardware buzz, so hardware buzz must be + * enabled before sleep mode entry and restored on wakeup. + ***********************************************************************/ + #if(CY_PSOC3) + + /* Silicon Revision ID is below TO6 */ + if(CYDEV_CHIP_REV_ACTUAL < 5u) + { + /* Hardware buzz expected to be disabled in Sleep mode */ + CYASSERT(0u == (CY_PM_PWRSYS_WAKE_TR2_REG & CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ)); + } + + + if(0u != (CY_PM_RESET_CR1_REG & (CY_PM_RESET_CR1_HVIA_EN | + CY_PM_RESET_CR1_LVIA_EN | CY_PM_RESET_CR1_LVID_EN))) + { + if(CYDEV_CHIP_REV_ACTUAL < 5u) + { + /* LVI/HVI requires hardware buzz to be enabled */ + CYASSERT(0u != 0u); + } + else + { + if (0u == (CY_PM_PWRSYS_WAKE_TR2_REG & CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ)) + { + cyPmBackup.hardwareBuzz = CY_PM_DISABLED; + CY_PM_PWRSYS_WAKE_TR2_REG |= CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ; + } + else + { + cyPmBackup.hardwareBuzz = CY_PM_ENABLED; + } + } + } + + #endif /* (CY_PSOC3) */ + + + /******************************************************************************* + * For ARM-based devices, an interrupt is required for the CPU to wake up. The + * Power Management implementation assumes that wakeup time is configured with a + * separate component (component-based wakeup time configuration) for an + * interrupt to be issued on terminal count. For more information, refer to the + * Wakeup Time Configuration section of System Reference Guide. + *******************************************************************************/ + #if(CY_PSOC5) + + /* Arguments expected to be 0 */ + CYASSERT(PM_SLEEP_TIME_NONE == wakeupTime); + + if(0u != wakeupTime) + { + /* To remove unreferenced local variable warning */ + } + + #endif /* (CY_PSOC5) */ + + + CyPmHibSlpSaveSet(); + + + #if(CY_PSOC3) + + /* CTW - save current and set new configuration */ + if((wakeupTime >= PM_SLEEP_TIME_CTW_2MS) && (wakeupTime <= PM_SLEEP_TIME_CTW_4096MS)) + { + /* Save current and set new configuration of the CTW */ + CyPmCtwSetInterval((uint8)(wakeupTime - 1u)); + + /* Include associated timer to the wakeupSource */ + wakeupSource |= PM_SLEEP_SRC_CTW; + } + + /* 1PPS - save current and set new configuration */ + if(PM_SLEEP_TIME_ONE_PPS == wakeupTime) + { + /* Save current and set new configuration of the 1PPS */ + CyPmOppsSet(); + + /* Include associated timer to the wakeupSource */ + wakeupSource |= PM_SLEEP_SRC_ONE_PPS; + } + + #endif /* (CY_PSOC3) */ + + + /* Save and set new wake up configuration */ + + /* Interrupt, PICU, I2C, Boost converter, CTW/1PPS */ + cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG; + CY_PM_WAKEUP_CFG0_REG = (uint8) (wakeupSource >> 4u); + + /* Comparators */ + cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG; + CY_PM_WAKEUP_CFG1_REG = (((uint8) wakeupSource) & CY_PM_WAKEUP_SRC_CMPS_MASK); + + /* LCD */ + cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG; + CY_PM_WAKEUP_CFG2_REG = ((uint8) ((wakeupSource >> 12u) & 0x01u)); + + + /******************************************************************* + * Do not use merge region below unless any component datasheet + * suggest to do so. + *******************************************************************/ + /* `#START CY_PM_JUST_BEFORE_SLEEP` */ + + /* `#END` */ + + + /* Last moment IMO frequency change */ + if(0u == (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK)) + { + /* IMO frequency is 12 MHz */ + cyPmBackup.imoActFreq12Mhz = CY_PM_ENABLED; + } + else + { + /* IMO frequency is not 12 MHz */ + cyPmBackup.imoActFreq12Mhz = CY_PM_DISABLED; + + /* Save IMO frequency */ + cyPmBackup.imoActFreq = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK; + + /* Set IMO frequency to 12 MHz */ + CY_PM_FASTCLK_IMO_CR_REG &= ((uint8) (~CY_PM_FASTCLK_IMO_CR_FREQ_MASK)); + } + + /* Switch to the Sleep mode */ + CY_PM_MODE_CSR_REG = ((CY_PM_MODE_CSR_REG & ((uint8)(~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_SLEEP); + + /* Recommended readback. */ + (void) CY_PM_MODE_CSR_REG; + + /* Two recommended NOPs to get into the mode. */ + CY_NOP; + CY_NOP; + + /* Execute WFI instruction (for ARM-based devices only) */ + CY_PM_WFI; + + /* Point of return from Sleep Mode */ + + /* Restore last moment IMO frequency change */ + if(CY_PM_ENABLED != cyPmBackup.imoActFreq12Mhz) + { + CY_PM_FASTCLK_IMO_CR_REG = (CY_PM_FASTCLK_IMO_CR_REG & ((uint8)(~CY_PM_FASTCLK_IMO_CR_FREQ_MASK))) | + cyPmBackup.imoActFreq; + } + + + /******************************************************************* + * Do not use merge region below unless any component datasheet + * suggest to do so. + *******************************************************************/ + /* `#START CY_PM_JUST_AFTER_WAKEUP_FROM_SLEEP` */ + + /* `#END` */ + + + /* Restore hardware configuration */ + CyPmHibSlpRestore(); + + + /* Disable hardware buzz, if it was previously enabled */ + #if(CY_PSOC3) + + if(0u != (CY_PM_RESET_CR1_REG & (CY_PM_RESET_CR1_HVIA_EN | + CY_PM_RESET_CR1_LVIA_EN | CY_PM_RESET_CR1_LVID_EN))) + { + if(CYDEV_CHIP_REV_ACTUAL >= 5u) + { + if (CY_PM_DISABLED == cyPmBackup.hardwareBuzz) + { + CY_PM_PWRSYS_WAKE_TR2_REG &= (uint8)(~CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ); + } + } + } + + #endif /* (CY_PSOC3) */ + + + /* Restore current wake up configuration */ + CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0; + CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1; + CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2; + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyPmHibernate +******************************************************************************** +* +* Summary: +* Puts the part into the Hibernate state. +* +* PSoC 3 and PSoC 5LP: +* Before switching to Hibernate, the current status of the PICU wakeup source +* bit is saved and then set. This configures the device to wake up from the +* PICU. Make sure you have at least one pin configured to generate a PICU +* interrupt. For pin Px.y, the register "PICU_INTTYPE_PICUx_INTTYPEy" controls +* the PICU behavior. In the TRM, this register is "PICU[0..15]_INTTYPE[0..7]." +* In the Pins component datasheet, this register is referred to as the IRQ +* option. Once the wakeup occurs, the PICU wakeup source bit is restored and +* the PSoC returns to the Active state. +* +* Parameters: +* None +* +* Return: +* None +* +* Reentrant: +* No +* +* Side Effects: +* Applications must wait 20 us before re-entering hibernate or sleep after +* waking up from hibernate. The 20 us allows the sleep regulator time to +* stabilize before the next hibernate / sleep event occurs. The 20 us +* requirement begins when the device wakes up. There is no hardware check that +* this requirement is met. The specified delay should be done on ISR entry. +* +* After wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin is +* instance name of the Pins component) function must be called to clear the +* latched pin events to allow proper Hibernate mode entry andd to enable +* detection of future events. +* +* The 1 kHz ILO clock is expected to be enabled for PSoC 3 and PSoC 5LP to +* measure Hibernate/Sleep regulator settling time after a reset. The holdoff +* delay is measured using rising edges of the 1 kHz ILO. +* +*******************************************************************************/ +void CyPmHibernate(void) +{ + uint8 interruptState; + + /* Save current global interrupt enable and disable it */ + interruptState = CyEnterCriticalSection(); + + /*********************************************************************** + * The Hibernate/Sleep regulator has a settling time after a reset. + * During this time, the system ignores requests to enter Sleep and + * Hibernate modes. The holdoff delay is measured using rising edges of + * the 1 kHz ILO. + ***********************************************************************/ + if(0u == (CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_PWRUP_PULSE_Q)) + { + /* Disable hold off - no action on restore */ + CY_PM_PWRSYS_SLP_TR_REG &= CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK; + } + else + { + /* Abort, device is not ready for low power mode entry */ + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); + + return; + } + + CyPmHibSaveSet(); + + + /* Save and enable only wakeup on PICU */ + cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG; + CY_PM_WAKEUP_CFG0_REG = CY_PM_WAKEUP_PICU; + + cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG; + CY_PM_WAKEUP_CFG1_REG = 0x00u; + + cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG; + CY_PM_WAKEUP_CFG2_REG = 0x00u; + + + /* Last moment IMO frequency change */ + if(0u == (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK)) + { + /* IMO frequency is 12 MHz */ + cyPmBackup.imoActFreq12Mhz = CY_PM_ENABLED; + } + else + { + /* IMO frequency is not 12 MHz */ + cyPmBackup.imoActFreq12Mhz = CY_PM_DISABLED; + + /* Save IMO frequency */ + cyPmBackup.imoActFreq = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK; + + /* Set IMO frequency to 12 MHz */ + CY_PM_FASTCLK_IMO_CR_REG &= ((uint8) (~CY_PM_FASTCLK_IMO_CR_FREQ_MASK)); + } + + + /* Switch to Hibernate Mode */ + CY_PM_MODE_CSR_REG = (CY_PM_MODE_CSR_REG & ((uint8) (~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_HIBERNATE; + + /* Recommended readback. */ + (void) CY_PM_MODE_CSR_REG; + + /* Two recommended NOPs to get into the mode. */ + CY_NOP; + CY_NOP; + + /* Execute WFI instruction (for ARM-based devices only) */ + CY_PM_WFI; + + + /* Point of return from Hibernate mode */ + + + /* Restore last moment IMO frequency change */ + if(CY_PM_ENABLED != cyPmBackup.imoActFreq12Mhz) + { + CY_PM_FASTCLK_IMO_CR_REG = (CY_PM_FASTCLK_IMO_CR_REG & ((uint8)(~CY_PM_FASTCLK_IMO_CR_FREQ_MASK))) | + cyPmBackup.imoActFreq; + } + + + /* Restore device for proper Hibernate mode exit*/ + CyPmHibRestore(); + + /* Restore current wake up configuration */ + CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0; + CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1; + CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2; + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyPmReadStatus +******************************************************************************** +* +* Summary: +* Manages the Power Manager Interrupt Status Register. This register has the +* interrupt status for the one pulse per second, central timewheel and fast +* timewheel timers. This hardware register clears on read. To allow for only +* clearing the bits of interest and preserving the other bits, this function +* uses a shadow register that retains the state. This function reads the +* status register and ORs that value with the shadow register. That is the +* value that is returned. Then the bits in the mask that are set are cleared +* from this value and written back to the shadow register. +* +* Note You must call this function within 1 ms (1 clock cycle of the ILO) +* after a CTW event has occurred. +* +* Parameters: +* mask: Bits in the shadow register to clear. +* +* Define Source +* CY_PM_FTW_INT Fast Timewheel +* CY_PM_CTW_INT Central Timewheel +* CY_PM_ONEPPS_INT One Pulse Per Second +* +* Return: +* Status. Same bits values as the mask parameter. +* +*******************************************************************************/ +uint8 CyPmReadStatus(uint8 mask) +{ + static uint8 interruptStatus; + uint8 interruptState; + uint8 tmpStatus; + + /* Enter critical section */ + interruptState = CyEnterCriticalSection(); + + /* Save value of the register, copy it and clear desired bit */ + interruptStatus |= CY_PM_INT_SR_REG; + tmpStatus = interruptStatus; + interruptStatus &= ((uint8)(~mask)); + + /* Exit critical section */ + CyExitCriticalSection(interruptState); + + return(tmpStatus); +} + + +/******************************************************************************* +* Function Name: CyPmHibSaveSet +******************************************************************************** +* +* Summary: +* Prepare device for proper Hibernate low power mode entry: +* - Disables I2C backup regulator +* - Saves ILO power down mode state and enable it +* - Saves state of 1 kHz and 100 kHz ILO and disable them +* - Disables sleep regulator and shorts vccd to vpwrsleep +* - Save LVI/HVI configuration and disable them - CyPmHviLviSaveDisable() +* - CyPmHibSlpSaveSet() function is called +* +* Parameters: +* None +* +* Return: +* None +* +* Reentrant: +* No +* +*******************************************************************************/ +static void CyPmHibSaveSet(void) +{ + /* I2C backup reg must be off when the sleep regulator is unavailable */ + if(0u != (CY_PM_PWRSYS_CR1_REG & CY_PM_PWRSYS_CR1_I2CREG_BACKUP)) + { + /*********************************************************************** + * If I2C backup regulator is enabled, all the fixed-function registers + * store their values while device is in low power mode, otherwise their + * configuration is lost. The I2C API makes a decision to restore or not + * to restore I2C registers based on this. If this regulator will be + * disabled and then enabled, I2C API will suppose that I2C block + * registers preserved their values, while this is not true. So, the + * backup regulator is disabled. The I2C sleep APIs is responsible for + * restoration. + ***********************************************************************/ + + /* Disable I2C backup register */ + CY_PM_PWRSYS_CR1_REG &= ((uint8)(~CY_PM_PWRSYS_CR1_I2CREG_BACKUP)); + } + + + /* Save current ILO power mode and ensure low power mode */ + cyPmBackup.iloPowerMode = CyILO_SetPowerMode(CY_PM_POWERDOWN_MODE); + + /* Save current 1kHz ILO enable state. Disabled automatically. */ + cyPmBackup.ilo1kEnable = (0u == (CY_PM_SLOWCLK_ILO_CR0_REG & CY_PM_ILO_CR0_EN_1K)) ? + CY_PM_DISABLED : CY_PM_ENABLED; + + /* Save current 100kHz ILO enable state. Disabled automatically. */ + cyPmBackup.ilo100kEnable = (0u == (CY_PM_SLOWCLK_ILO_CR0_REG & CY_PM_ILO_CR0_EN_100K)) ? + CY_PM_DISABLED : CY_PM_ENABLED; + + + /* Disable the sleep regulator and shorts vccd to vpwrsleep */ + if(0u == (CY_PM_PWRSYS_SLP_TR_REG & CY_PM_PWRSYS_SLP_TR_BYPASS)) + { + /* Save current bypass state */ + cyPmBackup.slpTrBypass = CY_PM_DISABLED; + CY_PM_PWRSYS_SLP_TR_REG |= CY_PM_PWRSYS_SLP_TR_BYPASS; + } + else + { + cyPmBackup.slpTrBypass = CY_PM_ENABLED; + } + + /* LPCOMPs are always enabled (even when BOTH ext_vccd=1 and ext_vcca=1)*/ + + + /*************************************************************************** + * LVI/HVI must be disabled in Hibernate + ***************************************************************************/ + + /* Save LVI/HVI configuration and disable them */ + CyPmHviLviSaveDisable(); + + + /* Make the same preparations for Hibernate and Sleep modes */ + CyPmHibSlpSaveSet(); + + + /*************************************************************************** + * Save and set power mode wakeup trim registers + ***************************************************************************/ + cyPmBackup.wakeupTrim0 = CY_PM_PWRSYS_WAKE_TR0_REG; + cyPmBackup.wakeupTrim1 = CY_PM_PWRSYS_WAKE_TR1_REG; + + CY_PM_PWRSYS_WAKE_TR0_REG = CY_PM_PWRSYS_WAKE_TR0; + CY_PM_PWRSYS_WAKE_TR1_REG = CY_PM_PWRSYS_WAKE_TR1; +} + + +/******************************************************************************* +* Function Name: CyPmHibRestore +******************************************************************************** +* +* Summary: +* Restore device for proper Hibernate mode exit: +* - Restore LVI/HVI configuration - call CyPmHviLviRestore() +* - CyPmHibSlpSaveRestore() function is called +* - Restores ILO power down mode state and enable it +* - Restores state of 1 kHz and 100 kHz ILO and disable them +* - Restores sleep regulator settings +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +static void CyPmHibRestore(void) +{ + /* Restore LVI/HVI configuration */ + CyPmHviLviRestore(); + + /* Restore the same configuration for Hibernate and Sleep modes */ + CyPmHibSlpRestore(); + + /* Restore 1kHz ILO enable state */ + if(CY_PM_ENABLED == cyPmBackup.ilo1kEnable) + { + /* Enable 1kHz ILO */ + CyILO_Start1K(); + } + + /* Restore 100kHz ILO enable state */ + if(CY_PM_ENABLED == cyPmBackup.ilo100kEnable) + { + /* Enable 100kHz ILO */ + CyILO_Start100K(); + } + + /* Restore ILO power mode */ + (void) CyILO_SetPowerMode(cyPmBackup.iloPowerMode); + + + if(CY_PM_DISABLED == cyPmBackup.slpTrBypass) + { + /* Enable the sleep regulator */ + CY_PM_PWRSYS_SLP_TR_REG &= ((uint8)(~CY_PM_PWRSYS_SLP_TR_BYPASS)); + } + + + /*************************************************************************** + * Restore power mode wakeup trim registers + ***************************************************************************/ + CY_PM_PWRSYS_WAKE_TR0_REG = cyPmBackup.wakeupTrim0; + CY_PM_PWRSYS_WAKE_TR1_REG = cyPmBackup.wakeupTrim1; +} + + +/******************************************************************************* +* Function Name: CyPmCtwSetInterval +******************************************************************************** +* +* Summary: +* Performs CTW configuration: +* - Disables CTW interrupt +* - Enables 1 kHz ILO +* - Sets new CTW interval +* +* Parameters: +* ctwInterval: the CTW interval to be set. +* +* Return: +* None +* +* Side Effects: +* Enables ILO 1 KHz clock and leaves it enabled. +* +*******************************************************************************/ +void CyPmCtwSetInterval(uint8 ctwInterval) +{ + /* Disable CTW interrupt enable */ + CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_CTW_IE)); + + /* Enable 1kHz ILO (required for CTW operation) */ + CyILO_Start1K(); + + /* Interval could be set only while CTW is disabled */ + if(0u != (CY_PM_TW_CFG2_REG & CY_PM_CTW_EN)) + { + /* Set CTW interval if needed */ + if(CY_PM_TW_CFG1_REG != ctwInterval) + { + /* Disable the CTW, set new CTW interval and enable it again */ + CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_CTW_EN)); + CY_PM_TW_CFG1_REG = ctwInterval; + CY_PM_TW_CFG2_REG |= CY_PM_CTW_EN; + } /* Required interval is already set */ + } + else + { + /* Set CTW interval if needed */ + if(CY_PM_TW_CFG1_REG != ctwInterval) + { + /* Set the new CTW interval. Could be changed if CTW is disabled */ + CY_PM_TW_CFG1_REG = ctwInterval; + } /* Required interval is already set */ + + /* Enable the CTW */ + CY_PM_TW_CFG2_REG |= CY_PM_CTW_EN; + } +} + + +/******************************************************************************* +* Function Name: CyPmOppsSet +******************************************************************************** +* +* Summary: +* Performs 1PPS configuration: +* - Starts 32 KHz XTAL +* - Disables 1PPS interupts +* - Enables 1PPS +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyPmOppsSet(void) +{ + /* Enable 32kHz XTAL if needed */ + if(0u == (CY_PM_SLOWCLK_X32_CR_REG & CY_PM_X32_CR_X32EN)) + { + /* Enable 32kHz XTAL */ + CyXTAL_32KHZ_Start(); + } + + /* Disable 1PPS interrupt enable */ + CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_1PPS_IE)); + + /* Enable 1PPS operation */ + CY_PM_TW_CFG2_REG |= CY_PM_1PPS_EN; +} + + +/******************************************************************************* +* Function Name: CyPmFtwSetInterval +******************************************************************************** +* +* Summary: +* Performs FTW configuration: +* - Disables FTW interrupt +* - Enables 100 kHz ILO +* - Sets new FTW interval. +* +* Parameters: +* ftwInterval - FTW counter interval. +* +* Return: +* None +* +* Side Effects: +* Enables ILO 100 KHz clock and leaves it enabled. +* +*******************************************************************************/ +void CyPmFtwSetInterval(uint8 ftwInterval) +{ + /* Disable FTW interrupt enable */ + CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_FTW_IE)); + + /* Enable 100kHz ILO */ + CyILO_Start100K(); + + /* Iterval could be set only while FTW is disabled */ + if(0u != (CY_PM_TW_CFG2_REG & CY_PM_FTW_EN)) + { + /* Disable FTW, set new FTW interval if needed and enable it again */ + if(CY_PM_TW_CFG0_REG != ftwInterval) + { + /* Disable the CTW, set new CTW interval and enable it again */ + CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_FTW_EN)); + CY_PM_TW_CFG0_REG = ftwInterval; + CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN; + } /* Required interval is already set */ + } + else + { + /* Set new FTW counter interval if needed. FTW is disabled. */ + if(CY_PM_TW_CFG0_REG != ftwInterval) + { + /* Set the new CTW interval. Could be changed if CTW is disabled */ + CY_PM_TW_CFG0_REG = ftwInterval; + } /* Required interval is already set */ + + /* Enable the FTW */ + CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN; + } +} + + +/******************************************************************************* +* Function Name: CyPmHibSlpSaveSet +******************************************************************************** +* +* Summary: +* This API is used for preparing device for Sleep and Hibernate low power +* modes entry: +* - Saves COMP, VIDAC, DSM and SAR routing connections (PSoC 5) +* - Saves SC/CT routing connections (PSoC 3/5/5LP) +* - Disables Serial Wire Viewer (SWV) (PSoC 3) +* - Save boost reference selection and set it to internal +* +* Parameters: +* None +* +* Return: +* None +* +* Reentrant: +* No +* +*******************************************************************************/ +static void CyPmHibSlpSaveSet(void) +{ + /* Save SC/CT routing registers */ + cyPmBackup.scctData[0u] = CY_GET_REG8(CYREG_SC0_SW0 ); + cyPmBackup.scctData[1u] = CY_GET_REG8(CYREG_SC0_SW2 ); + cyPmBackup.scctData[2u] = CY_GET_REG8(CYREG_SC0_SW3 ); + cyPmBackup.scctData[3u] = CY_GET_REG8(CYREG_SC0_SW4 ); + cyPmBackup.scctData[4u] = CY_GET_REG8(CYREG_SC0_SW6 ); + cyPmBackup.scctData[5u] = CY_GET_REG8(CYREG_SC0_SW8 ); + cyPmBackup.scctData[6u] = CY_GET_REG8(CYREG_SC0_SW10); + + cyPmBackup.scctData[7u] = CY_GET_REG8(CYREG_SC1_SW0 ); + cyPmBackup.scctData[8u] = CY_GET_REG8(CYREG_SC1_SW2 ); + cyPmBackup.scctData[9u] = CY_GET_REG8(CYREG_SC1_SW3 ); + cyPmBackup.scctData[10u] = CY_GET_REG8(CYREG_SC1_SW4 ); + cyPmBackup.scctData[11u] = CY_GET_REG8(CYREG_SC1_SW6 ); + cyPmBackup.scctData[12u] = CY_GET_REG8(CYREG_SC1_SW8 ); + cyPmBackup.scctData[13u] = CY_GET_REG8(CYREG_SC1_SW10); + + cyPmBackup.scctData[14u] = CY_GET_REG8(CYREG_SC2_SW0 ); + cyPmBackup.scctData[15u] = CY_GET_REG8(CYREG_SC2_SW2 ); + cyPmBackup.scctData[16u] = CY_GET_REG8(CYREG_SC2_SW3 ); + cyPmBackup.scctData[17u] = CY_GET_REG8(CYREG_SC2_SW4 ); + cyPmBackup.scctData[18u] = CY_GET_REG8(CYREG_SC2_SW6 ); + cyPmBackup.scctData[19u] = CY_GET_REG8(CYREG_SC2_SW8 ); + cyPmBackup.scctData[20u] = CY_GET_REG8(CYREG_SC2_SW10); + + cyPmBackup.scctData[21u] = CY_GET_REG8(CYREG_SC3_SW0 ); + cyPmBackup.scctData[22u] = CY_GET_REG8(CYREG_SC3_SW2 ); + cyPmBackup.scctData[23u] = CY_GET_REG8(CYREG_SC3_SW3 ); + cyPmBackup.scctData[24u] = CY_GET_REG8(CYREG_SC3_SW4 ); + cyPmBackup.scctData[25u] = CY_GET_REG8(CYREG_SC3_SW6 ); + cyPmBackup.scctData[26u] = CY_GET_REG8(CYREG_SC3_SW8 ); + cyPmBackup.scctData[27u] = CY_GET_REG8(CYREG_SC3_SW10); + + CY_SET_REG8(CYREG_SC0_SW0 , 0u); + CY_SET_REG8(CYREG_SC0_SW2 , 0u); + CY_SET_REG8(CYREG_SC0_SW3 , 0u); + CY_SET_REG8(CYREG_SC0_SW4 , 0u); + CY_SET_REG8(CYREG_SC0_SW6 , 0u); + CY_SET_REG8(CYREG_SC0_SW8 , 0u); + CY_SET_REG8(CYREG_SC0_SW10, 0u); + + CY_SET_REG8(CYREG_SC1_SW0 , 0u); + CY_SET_REG8(CYREG_SC1_SW2 , 0u); + CY_SET_REG8(CYREG_SC1_SW3 , 0u); + CY_SET_REG8(CYREG_SC1_SW4 , 0u); + CY_SET_REG8(CYREG_SC1_SW6 , 0u); + CY_SET_REG8(CYREG_SC1_SW8 , 0u); + CY_SET_REG8(CYREG_SC1_SW10, 0u); + + CY_SET_REG8(CYREG_SC2_SW0 , 0u); + CY_SET_REG8(CYREG_SC2_SW2 , 0u); + CY_SET_REG8(CYREG_SC2_SW3 , 0u); + CY_SET_REG8(CYREG_SC2_SW4 , 0u); + CY_SET_REG8(CYREG_SC2_SW6 , 0u); + CY_SET_REG8(CYREG_SC2_SW8 , 0u); + CY_SET_REG8(CYREG_SC2_SW10, 0u); + + CY_SET_REG8(CYREG_SC3_SW0 , 0u); + CY_SET_REG8(CYREG_SC3_SW2 , 0u); + CY_SET_REG8(CYREG_SC3_SW3 , 0u); + CY_SET_REG8(CYREG_SC3_SW4 , 0u); + CY_SET_REG8(CYREG_SC3_SW6 , 0u); + CY_SET_REG8(CYREG_SC3_SW8 , 0u); + CY_SET_REG8(CYREG_SC3_SW10, 0u); + + + #if(CY_PSOC3) + + /* Serial Wire Viewer (SWV) workaround */ + + /* Disable SWV before entering low power mode */ + if(0u != (CY_PM_MLOGIC_DBG_REG & CY_PM_MLOGIC_DBG_SWV_CLK_EN)) + { + /* Save SWV clock enabled state */ + cyPmBackup.swvClkEnabled = CY_PM_ENABLED; + + /* Save current ports drive mode settings */ + cyPmBackup.prt1Dm = CY_PM_PRT1_PC3_REG & ((uint8)(~CY_PM_PRT1_PC3_DM_MASK)); + + /* Set drive mode to strong output */ + CY_PM_PRT1_PC3_REG = (CY_PM_PRT1_PC3_REG & CY_PM_PRT1_PC3_DM_MASK) | + CY_PM_PRT1_PC3_DM_STRONG; + + /* Disable SWV clocks */ + CY_PM_MLOGIC_DBG_REG &= ((uint8)(~CY_PM_MLOGIC_DBG_SWV_CLK_EN)); + } + else + { + /* Save SWV clock disabled state */ + cyPmBackup.swvClkEnabled = CY_PM_DISABLED; + } + + #endif /* (CY_PSOC3) */ + + + /*************************************************************************** + * Save boost reference and set it to boost's internal by clearing the bit. + * External (chip bandgap) reference is not available in Sleep and Hibernate. + ***************************************************************************/ + if(0u != (CY_PM_BOOST_CR2_REG & CY_PM_BOOST_CR2_EREFSEL_EXT)) + { + cyPmBackup.boostRefExt = CY_PM_ENABLED; + CY_PM_BOOST_CR2_REG &= ((uint8)(~CY_PM_BOOST_CR2_EREFSEL_EXT)); + } + else + { + cyPmBackup.boostRefExt = CY_PM_DISABLED; + } +} + + +/******************************************************************************* +* Function Name: CyPmHibSlpRestore +******************************************************************************** +* +* Summary: +* This API is used for restoring device configurations after wakeup from Sleep +* and Hibernate low power modes: +* - Restores SC/CT routing connections +* - Restores enable state of Serial Wire Viewer (SWV) (PSoC 3) +* - Restore boost reference selection +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +static void CyPmHibSlpRestore(void) +{ + /* Restore SC/CT routing registers */ + CY_SET_REG8(CYREG_SC0_SW0 , cyPmBackup.scctData[0u] ); + CY_SET_REG8(CYREG_SC0_SW2 , cyPmBackup.scctData[1u] ); + CY_SET_REG8(CYREG_SC0_SW3 , cyPmBackup.scctData[2u] ); + CY_SET_REG8(CYREG_SC0_SW4 , cyPmBackup.scctData[3u] ); + CY_SET_REG8(CYREG_SC0_SW6 , cyPmBackup.scctData[4u] ); + CY_SET_REG8(CYREG_SC0_SW8 , cyPmBackup.scctData[5u] ); + CY_SET_REG8(CYREG_SC0_SW10, cyPmBackup.scctData[6u] ); + + CY_SET_REG8(CYREG_SC1_SW0 , cyPmBackup.scctData[7u] ); + CY_SET_REG8(CYREG_SC1_SW2 , cyPmBackup.scctData[8u] ); + CY_SET_REG8(CYREG_SC1_SW3 , cyPmBackup.scctData[9u] ); + CY_SET_REG8(CYREG_SC1_SW4 , cyPmBackup.scctData[10u]); + CY_SET_REG8(CYREG_SC1_SW6 , cyPmBackup.scctData[11u]); + CY_SET_REG8(CYREG_SC1_SW8 , cyPmBackup.scctData[12u]); + CY_SET_REG8(CYREG_SC1_SW10, cyPmBackup.scctData[13u]); + + CY_SET_REG8(CYREG_SC2_SW0 , cyPmBackup.scctData[14u]); + CY_SET_REG8(CYREG_SC2_SW2 , cyPmBackup.scctData[15u]); + CY_SET_REG8(CYREG_SC2_SW3 , cyPmBackup.scctData[16u]); + CY_SET_REG8(CYREG_SC2_SW4 , cyPmBackup.scctData[17u]); + CY_SET_REG8(CYREG_SC2_SW6 , cyPmBackup.scctData[18u]); + CY_SET_REG8(CYREG_SC2_SW8 , cyPmBackup.scctData[19u]); + CY_SET_REG8(CYREG_SC2_SW10, cyPmBackup.scctData[20u]); + + CY_SET_REG8(CYREG_SC3_SW0 , cyPmBackup.scctData[21u]); + CY_SET_REG8(CYREG_SC3_SW2 , cyPmBackup.scctData[22u]); + CY_SET_REG8(CYREG_SC3_SW3 , cyPmBackup.scctData[23u]); + CY_SET_REG8(CYREG_SC3_SW4 , cyPmBackup.scctData[24u]); + CY_SET_REG8(CYREG_SC3_SW6 , cyPmBackup.scctData[25u]); + CY_SET_REG8(CYREG_SC3_SW8 , cyPmBackup.scctData[26u]); + CY_SET_REG8(CYREG_SC3_SW10, cyPmBackup.scctData[27u]); + + + #if(CY_PSOC3) + + /* Serial Wire Viewer (SWV) workaround */ + if(CY_PM_ENABLED == cyPmBackup.swvClkEnabled) + { + /* Restore ports drive mode */ + CY_PM_PRT1_PC3_REG = (CY_PM_PRT1_PC3_REG & CY_PM_PRT1_PC3_DM_MASK) | + cyPmBackup.prt1Dm; + + /* Enable SWV clocks */ + CY_PM_MLOGIC_DBG_REG |= CY_PM_MLOGIC_DBG_SWV_CLK_EN; + } + + #endif /* (CY_PSOC3) */ + + + /* Restore boost reference */ + if(CY_PM_ENABLED == cyPmBackup.boostRefExt) + { + CY_PM_BOOST_CR2_REG |= CY_PM_BOOST_CR2_EREFSEL_EXT; + } +} + + +/******************************************************************************* +* Function Name: CyPmHviLviSaveDisable +******************************************************************************** +* +* Summary: +* Saves analog and digital LVI and HVI configuration and disables them. +* +* Parameters: +* None +* +* Return: +* None +* +* Reentrant: +* No +* +*******************************************************************************/ +static void CyPmHviLviSaveDisable(void) +{ + if(0u != (CY_VD_LVI_HVI_CONTROL_REG & CY_VD_LVID_EN)) + { + cyPmBackup.lvidEn = CY_PM_ENABLED; + cyPmBackup.lvidTrip = CY_VD_LVI_TRIP_REG & CY_VD_LVI_TRIP_LVID_MASK; + + /* Save state of reset device at a specified Vddd threshold */ + cyPmBackup.lvidRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESD_EN)) ? \ + CY_PM_DISABLED : CY_PM_ENABLED; + + CyVdLvDigitDisable(); + } + else + { + cyPmBackup.lvidEn = CY_PM_DISABLED; + } + + if(0u != (CY_VD_LVI_HVI_CONTROL_REG & CY_VD_LVIA_EN)) + { + cyPmBackup.lviaEn = CY_PM_ENABLED; + cyPmBackup.lviaTrip = CY_VD_LVI_TRIP_REG >> 4u; + + /* Save state of reset device at a specified Vdda threshold */ + cyPmBackup.lviaRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESA_EN)) ? \ + CY_PM_DISABLED : CY_PM_ENABLED; + + CyVdLvAnalogDisable(); + } + else + { + cyPmBackup.lviaEn = CY_PM_DISABLED; + } + + if(0u != (CY_VD_LVI_HVI_CONTROL_REG & CY_VD_HVIA_EN)) + { + cyPmBackup.hviaEn = CY_PM_ENABLED; + CyVdHvAnalogDisable(); + } + else + { + cyPmBackup.hviaEn = CY_PM_DISABLED; + } +} + + +/******************************************************************************* +* Function Name: CyPmHviLviRestore +******************************************************************************** +* +* Summary: +* Restores analog and digital LVI and HVI configuration. +* +* Parameters: +* None +* +* Return: +* None +* +* Reentrant: +* No +* +*******************************************************************************/ +static void CyPmHviLviRestore(void) +{ + /* Restore LVI/HVI configuration */ + if(CY_PM_ENABLED == cyPmBackup.lvidEn) + { + CyVdLvDigitEnable(cyPmBackup.lvidRst, cyPmBackup.lvidTrip); + } + + if(CY_PM_ENABLED == cyPmBackup.lviaEn) + { + CyVdLvAnalogEnable(cyPmBackup.lviaRst, cyPmBackup.lviaTrip); + } + + if(CY_PM_ENABLED == cyPmBackup.hviaEn) + { + CyVdHvAnalogEnable(); + } +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyPm.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyPm.h new file mode 100755 index 00000000..327908be --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyPm.h @@ -0,0 +1,635 @@ +/******************************************************************************* +* File Name: cyPm.h +* Version 4.0 +* +* Description: +* Provides the function definitions for the power management API. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYPM_H) +#define CY_BOOT_CYPM_H + +#include "cytypes.h" /* Register access API */ +#include "cydevice_trm.h" /* Registers addresses */ +#include "cyfitter.h" /* Comparators placement */ +#include "CyLib.h" /* Clock API */ +#include "CyFlash.h" /* Flash API - CyFlash_SetWaitCycles() */ + + +/*************************************** +* Function Prototypes +***************************************/ +void CyPmSaveClocks(void) ; +void CyPmRestoreClocks(void) ; +void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource) ; +void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource) ; +void CyPmHibernate(void) ; + +uint8 CyPmReadStatus(uint8 mask) ; + +/* Internal APIs and are not meant to be called directly by the user */ +void CyPmCtwSetInterval(uint8 ctwInterval) ; +void CyPmFtwSetInterval(uint8 ftwInterval) ; +void CyPmOppsSet(void) ; + + +/*************************************** +* API Constants +***************************************/ + +#define PM_SLEEP_SRC_NONE (0x0000u) +#define PM_SLEEP_TIME_NONE (0x00u) +#define PM_ALT_ACT_SRC_NONE (0x0000u) +#define PM_ALT_ACT_TIME_NONE (0x0000u) + +#if(CY_PSOC3) + + /* Wake up time for the Sleep mode */ + #define PM_SLEEP_TIME_ONE_PPS (0x01u) + #define PM_SLEEP_TIME_CTW_2MS (0x02u) + #define PM_SLEEP_TIME_CTW_4MS (0x03u) + #define PM_SLEEP_TIME_CTW_8MS (0x04u) + #define PM_SLEEP_TIME_CTW_16MS (0x05u) + #define PM_SLEEP_TIME_CTW_32MS (0x06u) + #define PM_SLEEP_TIME_CTW_64MS (0x07u) + #define PM_SLEEP_TIME_CTW_128MS (0x08u) + #define PM_SLEEP_TIME_CTW_256MS (0x09u) + #define PM_SLEEP_TIME_CTW_512MS (0x0Au) + #define PM_SLEEP_TIME_CTW_1024MS (0x0Bu) + #define PM_SLEEP_TIME_CTW_2048MS (0x0Cu) + #define PM_SLEEP_TIME_CTW_4096MS (0x0Du) + + /* Difference between parameter's value and register's one */ + #define CY_PM_FTW_INTERVAL_SHIFT (0x000Eu) + + /* Wake up time for the Alternate Active mode */ + #define PM_ALT_ACT_TIME_ONE_PPS (0x0001u) + #define PM_ALT_ACT_TIME_CTW_2MS (0x0002u) + #define PM_ALT_ACT_TIME_CTW_4MS (0x0003u) + #define PM_ALT_ACT_TIME_CTW_8MS (0x0004u) + #define PM_ALT_ACT_TIME_CTW_16MS (0x0005u) + #define PM_ALT_ACT_TIME_CTW_32MS (0x0006u) + #define PM_ALT_ACT_TIME_CTW_64MS (0x0007u) + #define PM_ALT_ACT_TIME_CTW_128MS (0x0008u) + #define PM_ALT_ACT_TIME_CTW_256MS (0x0009u) + #define PM_ALT_ACT_TIME_CTW_512MS (0x000Au) + #define PM_ALT_ACT_TIME_CTW_1024MS (0x000Bu) + #define PM_ALT_ACT_TIME_CTW_2048MS (0x000Cu) + #define PM_ALT_ACT_TIME_CTW_4096MS (0x000Du) + #define PM_ALT_ACT_TIME_FTW(x) ((x) + CY_PM_FTW_INTERVAL_SHIFT) + +#endif /* (CY_PSOC3) */ + + +/* Wake up sources for the Sleep mode */ +#define PM_SLEEP_SRC_COMPARATOR0 (0x0001u) +#define PM_SLEEP_SRC_COMPARATOR1 (0x0002u) +#define PM_SLEEP_SRC_COMPARATOR2 (0x0004u) +#define PM_SLEEP_SRC_COMPARATOR3 (0x0008u) +#define PM_SLEEP_SRC_PICU (0x0040u) +#define PM_SLEEP_SRC_I2C (0x0080u) +#define PM_SLEEP_SRC_BOOSTCONVERTER (0x0200u) +#define PM_SLEEP_SRC_VD (0x0400u) +#define PM_SLEEP_SRC_CTW (0x0800u) +#define PM_SLEEP_SRC_ONE_PPS (0x0800u) +#define PM_SLEEP_SRC_LCD (0x1000u) + +/* Wake up sources for the Alternate Active mode */ +#define PM_ALT_ACT_SRC_COMPARATOR0 (0x0001u) +#define PM_ALT_ACT_SRC_COMPARATOR1 (0x0002u) +#define PM_ALT_ACT_SRC_COMPARATOR2 (0x0004u) +#define PM_ALT_ACT_SRC_COMPARATOR3 (0x0008u) +#define PM_ALT_ACT_SRC_INTERRUPT (0x0010u) +#define PM_ALT_ACT_SRC_PICU (0x0040u) +#define PM_ALT_ACT_SRC_I2C (0x0080u) +#define PM_ALT_ACT_SRC_BOOSTCONVERTER (0x0200u) +#define PM_ALT_ACT_SRC_FTW (0x0400u) +#define PM_ALT_ACT_SRC_VD (0x0400u) +#define PM_ALT_ACT_SRC_CTW (0x0800u) +#define PM_ALT_ACT_SRC_ONE_PPS (0x0800u) +#define PM_ALT_ACT_SRC_LCD (0x1000u) + + +#define CY_PM_WAKEUP_PICU (0x04u) +#define CY_PM_IMO_NO_WAIT_TO_SETTLE (0x00u) +#define CY_PM_POWERDOWN_MODE (0x01u) +#define CY_PM_HIGHPOWER_MODE (0x00u) /* Deprecated */ +#define CY_PM_ENABLED (0x01u) +#define CY_PM_DISABLED (0x00u) + +/* No wait for PLL to stabilize, used in CyPLL_OUT_Start() */ +#define CY_PM_PLL_OUT_NO_WAIT (0u) + +/* No wait for MHZ XTAL to stabilize, used in CyXTAL_Start() */ +#define CY_PM_XTAL_MHZ_NO_WAIT (0u) + +#define CY_PM_WAIT_200_US (200u) +#define CY_PM_WAIT_250_US (250u) +#define CY_PM_WAIT_20_US (20u) + +#define CY_PM_FREQ_3MHZ (3u) +#define CY_PM_FREQ_12MHZ (12u) +#define CY_PM_FREQ_48MHZ (48u) + + +#define CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US (5u) + + +/* Delay line bandgap current settling time starting from a wakeup event */ +#define CY_PM_CLK_DELAY_BANDGAP_SETTLE_US (50u) + +/* Delay line internal bias settling */ +#define CY_PM_CLK_DELAY_BIAS_SETTLE_US (25u) + + +/* Max flash wait cycles for each device */ +#if(CY_PSOC3) + #define CY_PM_MAX_FLASH_WAIT_CYCLES (45u) +#endif /* (CY_PSOC3) */ + +#if(CY_PSOC5) + #define CY_PM_MAX_FLASH_WAIT_CYCLES (55u) +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* This marco is used to obtain the CPU frequency in MHz. It should be only used +* when the clock distribution system is prepared for the low power mode entry. +* This macro is silicon dependent as PSoC 5 devices have no CPU clock divider +* and PSoC 3 devices have different placement of the CPU clock divider register +* bitfield. +*******************************************************************************/ +#if(CY_PSOC3) + #define CY_PM_GET_CPU_FREQ_MHZ \ + ((uint32)(cyPmImoFreqReg2Mhz[CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK]) / \ + ((uint8)(((CY_PM_CLKDIST_MSTR1_REG & CY_PM_CLKDIST_CPU_DIV_MASK) >> 4u) + 1u))) +#endif /* (CY_PSOC3) */ + +#if(CY_PSOC5) + + /* The CPU clock is directly derived from bus clock */ + #define CY_PM_GET_CPU_FREQ_MHZ (cyPmImoFreqReg2Mhz[CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK]) + +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* The low power mode entry is different for PSoC 3 and PSoC 5 devices. The low +* power modes in PSoC 5 devices are invoked by Wait-For-Interrupt (WFI) +* instruction. The ARM compilers has __wfi() instristic that inserts a WFI +* instruction into the instruction stream generated by the compiler. The GCC +* compiler has to execute assembly language instruction. +*******************************************************************************/ +#if(CY_PSOC5) + + #if defined(__ARMCC_VERSION) /* Instristic for Keil compilers */ + #define CY_PM_WFI __wfi() + #else /* ASM for GCC & IAR */ + #define CY_PM_WFI asm volatile ("WFI \n") + #endif /* (__ARMCC_VERSION) */ + +#else + + #define CY_PM_WFI CY_NOP + +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* Macro for the wakeupTime argument of the CyPmAltAct() function. The FTW should +* be programmed manually for non PSoC 3 devices. +*******************************************************************************/ +#if(CY_PSOC3) + + #define PM_ALT_ACT_FTW_INTERVAL(x) ((uint8)((x) - CY_PM_FTW_INTERVAL_SHIFT)) + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* This macro defines the IMO frequency that will be set by CyPmSaveClocks() +* function based on Enable Fast IMO during Startup option from the DWR file. +* The CyPmSleep()/CyPmHibernate() will set IMO 12 MHz just before entering +* low power mode and restore IMO back to the value set by CyPmSaveClocks() +* immediately on wakeup. +*******************************************************************************/ + +/* Enable Fast IMO during Startup - enabled */ +#if(1u == CYDEV_CONFIGURATION_IMOENABLED) + + /* IMO will be configured to 48 MHz */ + #define CY_PM_IMO_FREQ_LPM (CY_IMO_FREQ_48MHZ) + +#else + + /* IMO will be configured to 12 MHz */ + #define CY_PM_IMO_FREQ_LPM (CY_IMO_FREQ_12MHZ) + +#endif /* (1u == CYDEV_CONFIGURATION_IMOENABLED) */ + + +typedef struct cyPmClockBackupStruct +{ + /* CyPmSaveClocks()/CyPmRestoreClocks() */ + uint8 enClkA; /* Analog clocks enable */ + uint8 enClkD; /* Digital clocks enable */ + uint8 masterClkSrc; /* The Master clock source */ + uint8 imoFreq; /* IMO frequency (reg's value) */ + uint8 imoUsbClk; /* IMO USB CLK (reg's value) */ + uint8 flashWaitCycles; /* Flash wait cycles */ + uint8 imoEnable; /* IMO enable in Active mode */ + uint8 imoClkSrc; /* The IMO output */ + uint8 clkImoSrc; + uint8 imo2x; /* IMO doubler enable state */ + uint8 clkSyncDiv; /* Master clk divider */ + uint16 clkBusDiv; /* The clk_bus divider */ + uint8 pllEnableState; /* PLL enable state */ + uint8 xmhzEnableState; /* XM HZ enable state */ + uint8 clkDistDelay; /* Delay for clk_bus and ACLKs */ + +} CY_PM_CLOCK_BACKUP_STRUCT; + + +typedef struct cyPmBackupStruct +{ + uint8 iloPowerMode; /* ILO power mode */ + uint8 ilo1kEnable; /* ILO 1K enable state */ + uint8 ilo100kEnable; /* ILO 100K enable state */ + + uint8 slpTrBypass; /* Sleep Trim Bypass */ + + #if(CY_PSOC3) + + uint8 swvClkEnabled; /* SWV clock enable state */ + uint8 prt1Dm; /* Ports drive mode configuration */ + uint8 hardwareBuzz; + + #endif /* (CY_PSOC3) */ + + uint8 wakeupCfg0; /* Wake up configuration 0 */ + uint8 wakeupCfg1; /* Wake up configuration 1 */ + uint8 wakeupCfg2; /* Wake up configuration 2 */ + + uint8 wakeupTrim0; + uint8 wakeupTrim1; + + uint8 scctData[28u]; /* SC/CT routing registers */ + + /* CyPmHviLviSaveDisable()/CyPmHviLviRestore() */ + uint8 lvidEn; + uint8 lvidTrip; + uint8 lviaEn; + uint8 lviaTrip; + uint8 hviaEn; + uint8 lvidRst; + uint8 lviaRst; + + uint8 imoActFreq; /* Last moment IMO change */ + uint8 imoActFreq12Mhz; /* 12 MHz or not */ + + uint8 boostRefExt; /* Boost reference selection */ + +} CY_PM_BACKUP_STRUCT; + + +/*************************************** +* Registers +***************************************/ + +/* Power Mode Wakeup Trim Register 1 */ +#define CY_PM_PWRSYS_WAKE_TR1_REG (* (reg8 *) CYREG_PWRSYS_WAKE_TR1 ) +#define CY_PM_PWRSYS_WAKE_TR1_PTR ( (reg8 *) CYREG_PWRSYS_WAKE_TR1 ) + +/* Master clock Divider Value Register */ +#define CY_PM_CLKDIST_MSTR0_REG (* (reg8 *) CYREG_CLKDIST_MSTR0 ) +#define CY_PM_CLKDIST_MSTR0_PTR ( (reg8 *) CYREG_CLKDIST_MSTR0 ) + +/* Master Clock Configuration Register/CPU Divider Value */ +#define CY_PM_CLKDIST_MSTR1_REG (* (reg8 *) CYREG_CLKDIST_MSTR1 ) +#define CY_PM_CLKDIST_MSTR1_PTR ( (reg8 *) CYREG_CLKDIST_MSTR1 ) + +/* Clock distribution configuration Register */ +#define CY_PM_CLKDIST_CR_REG (* (reg8 *) CYREG_CLKDIST_CR ) +#define CY_PM_CLKDIST_CR_PTR ( (reg8 *) CYREG_CLKDIST_CR ) + +/* CLK_BUS LSB Divider Value Register */ +#define CY_PM_CLK_BUS_LSB_DIV_REG (* (reg8 *) CYREG_CLKDIST_BCFG0 ) +#define CY_PM_CLK_BUS_LSB_DIV_PTR ( (reg8 *) CYREG_CLKDIST_BCFG0 ) + +/* CLK_BUS MSB Divider Value Register */ +#define CY_PM_CLK_BUS_MSB_DIV_REG (* (reg8 *) CYREG_CLKDIST_BCFG1 ) +#define CY_PM_CLK_BUS_MSB_DIV_PTR ( (reg8 *) CYREG_CLKDIST_BCFG1 ) + +/* CLK_BUS Configuration Register */ +#define CLK_BUS_CFG_REG (* (reg8 *) CYREG_CLKDIST_BCFG2 ) +#define CLK_BUS_CFG_PTR ( (reg8 *) CYREG_CLKDIST_BCFG2 ) + +/* Power Mode Control/Status Register */ +#define CY_PM_MODE_CSR_REG (* (reg8 *) CYREG_PM_MODE_CSR ) +#define CY_PM_MODE_CSR_PTR ( (reg8 *) CYREG_PM_MODE_CSR ) + +/* Power System Control Register 1 */ +#define CY_PM_PWRSYS_CR1_REG (* (reg8 *) CYREG_PWRSYS_CR1 ) +#define CY_PM_PWRSYS_CR1_PTR ( (reg8 *) CYREG_PWRSYS_CR1 ) + +/* Power System Control Register 0 */ +#define CY_PM_PWRSYS_CR0_REG (* (reg8 *) CYREG_PWRSYS_CR0 ) +#define CY_PM_PWRSYS_CR0_PTR ( (reg8 *) CYREG_PWRSYS_CR0 ) + +/* Internal Low-speed Oscillator Control Register 0 */ +#define CY_PM_SLOWCLK_ILO_CR0_REG (* (reg8 *) CYREG_SLOWCLK_ILO_CR0 ) +#define CY_PM_SLOWCLK_ILO_CR0_PTR ( (reg8 *) CYREG_SLOWCLK_ILO_CR0 ) + +/* External 32kHz Crystal Oscillator Control Register */ +#define CY_PM_SLOWCLK_X32_CR_REG (* (reg8 *) CYREG_SLOWCLK_X32_CR ) +#define CY_PM_SLOWCLK_X32_CR_PTR ( (reg8 *) CYREG_SLOWCLK_X32_CR ) + +#if(CY_PSOC3) + + /* MLOGIC Debug Register */ + #define CY_PM_MLOGIC_DBG_REG (* (reg8 *) CYREG_MLOGIC_DEBUG ) + #define CY_PM_MLOGIC_DBG_PTR ( (reg8 *) CYREG_MLOGIC_DEBUG ) + + /* Port Pin Configuration Register */ + #define CY_PM_PRT1_PC3_REG (* (reg8 *) CYREG_PRT1_PC3 ) + #define CY_PM_PRT1_PC3_PTR ( (reg8 *) CYREG_PRT1_PC3 ) + +#endif /* (CY_PSOC3) */ + + +/* Sleep Regulator Trim Register */ +#define CY_PM_PWRSYS_SLP_TR_REG (* (reg8 *) CYREG_PWRSYS_SLP_TR ) +#define CY_PM_PWRSYS_SLP_TR_PTR ( (reg8 *) CYREG_PWRSYS_SLP_TR ) + + +/* Reset System Control Register */ +#define CY_PM_RESET_CR1_REG (* (reg8 *) CYREG_RESET_CR1 ) +#define CY_PM_RESET_CR1_PTR ( (reg8 *) CYREG_RESET_CR1 ) + +/* Power Mode Wakeup Trim Register 0 */ +#define CY_PM_PWRSYS_WAKE_TR0_REG (* (reg8 *) CYREG_PWRSYS_WAKE_TR0 ) +#define CY_PM_PWRSYS_WAKE_TR0_PTR ( (reg8 *) CYREG_PWRSYS_WAKE_TR0 ) + +#if(CY_PSOC3) + + /* Power Mode Wakeup Trim Register 2 */ + #define CY_PM_PWRSYS_WAKE_TR2_REG (* (reg8 *) CYREG_PWRSYS_WAKE_TR2 ) + #define CY_PM_PWRSYS_WAKE_TR2_PTR ( (reg8 *) CYREG_PWRSYS_WAKE_TR2 ) + +#endif /* (CY_PSOC3) */ + +/* Power Manager Interrupt Status Register */ +#define CY_PM_INT_SR_REG (* (reg8 *) CYREG_PM_INT_SR ) +#define CY_PM_INT_SR_PTR ( (reg8 *) CYREG_PM_INT_SR ) + +/* Active Power Mode Configuration Register 0 */ +#define CY_PM_ACT_CFG0_REG (* (reg8 *) CYREG_PM_ACT_CFG0 ) +#define CY_PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0 ) + +/* Active Power Mode Configuration Register 1 */ +#define CY_PM_ACT_CFG1_REG (* (reg8 *) CYREG_PM_ACT_CFG1 ) +#define CY_PM_ACT_CFG1_PTR ( (reg8 *) CYREG_PM_ACT_CFG1 ) + +/* Active Power Mode Configuration Register 2 */ +#define CY_PM_ACT_CFG2_REG (* (reg8 *) CYREG_PM_ACT_CFG2 ) +#define CY_PM_ACT_CFG2_PTR ( (reg8 *) CYREG_PM_ACT_CFG2 ) + +/* Boost Control 1 */ +#define CY_PM_BOOST_CR1_REG (* (reg8 *) CYREG_BOOST_CR1 ) +#define CY_PM_BOOST_CR1_PTR ( (reg8 *) CYREG_BOOST_CR1 ) + +/* Timewheel Configuration Register 0 */ +#define CY_PM_TW_CFG0_REG (* (reg8 *) CYREG_PM_TW_CFG0 ) +#define CY_PM_TW_CFG0_PTR ( (reg8 *) CYREG_PM_TW_CFG0 ) + +/* Timewheel Configuration Register 1 */ +#define CY_PM_TW_CFG1_REG (* (reg8 *) CYREG_PM_TW_CFG1 ) +#define CY_PM_TW_CFG1_PTR ( (reg8 *) CYREG_PM_TW_CFG1 ) + +/* Timewheel Configuration Register 2 */ +#define CY_PM_TW_CFG2_REG (* (reg8 *) CYREG_PM_TW_CFG2 ) +#define CY_PM_TW_CFG2_PTR ( (reg8 *) CYREG_PM_TW_CFG2 ) + +/* PLL Status Register */ +#define CY_PM_FASTCLK_PLL_SR_REG (*(reg8 *) CYREG_FASTCLK_PLL_SR ) +#define CY_PM_FASTCLK_PLL_SR_PTR ( (reg8 *) CYREG_FASTCLK_PLL_SR ) + +/* Internal Main Oscillator Control Register */ +#define CY_PM_FASTCLK_IMO_CR_REG (* (reg8 *) CYREG_FASTCLK_IMO_CR ) +#define CY_PM_FASTCLK_IMO_CR_PTR ( (reg8 *) CYREG_FASTCLK_IMO_CR ) + +/* PLL Configuration Register */ +#define CY_PM_FASTCLK_PLL_CFG0_REG (* (reg8 *) CYREG_FASTCLK_PLL_CFG0 ) +#define CY_PM_FASTCLK_PLL_CFG0_PTR ( (reg8 *) CYREG_FASTCLK_PLL_CFG0 ) + +/* External 4-33 MHz Crystal Oscillator Status and Control Register */ +#define CY_PM_FASTCLK_XMHZ_CSR_REG (* (reg8 *) CYREG_FASTCLK_XMHZ_CSR ) +#define CY_PM_FASTCLK_XMHZ_CSR_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CSR ) + +/* Delay block Configuration Register */ +#define CY_PM_CLKDIST_DELAY_REG (* (reg8 *) CYREG_CLKDIST_DLY1 ) +#define CY_PM_CLKDIST_DELAY_PTR ( (reg8 *) CYREG_CLKDIST_DLY1 ) + + +#if(CY_PSOC3) + + /* Cache Control Register */ + #define CY_PM_CACHE_CR_REG (* (reg8 *) CYREG_CACHE_CR ) + #define CY_PM_CACHE_CR_PTR ( (reg8 *) CYREG_CACHE_CR ) + +#else /* Device is PSoC 5 */ + + /* Cache Control Register */ + #define CY_PM_CACHE_CR_REG (* (reg8 *) CYREG_CACHE_CC_CTL ) + #define CY_PM_CACHE_CR_PTR ( (reg8 *) CYREG_CACHE_CC_CTL ) + +#endif /* (CY_PSOC3) */ + + +/* Power Mode Wakeup Mask Configuration Register 0 */ +#define CY_PM_WAKEUP_CFG0_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG0 ) +#define CY_PM_WAKEUP_CFG0_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG0 ) + +/* Power Mode Wakeup Mask Configuration Register 1 */ +#define CY_PM_WAKEUP_CFG1_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG1 ) +#define CY_PM_WAKEUP_CFG1_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG1 ) + +/* Power Mode Wakeup Mask Configuration Register 2 */ +#define CY_PM_WAKEUP_CFG2_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG2 ) +#define CY_PM_WAKEUP_CFG2_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG2 ) + +/* Boost Control 2 */ +#define CY_PM_BOOST_CR2_REG (* (reg8 *) CYREG_BOOST_CR2 ) +#define CY_PM_BOOST_CR2_PTR ( (reg8 *) CYREG_BOOST_CR2 ) + + +/*************************************** +* Register Constants +***************************************/ + +/* Internal Main Oscillator Control Register */ + +#define CY_PM_FASTCLK_IMO_CR_FREQ_MASK (0x07u) /* IMO frequency mask */ +#define CY_PM_FASTCLK_IMO_CR_FREQ_12MHZ (0x00u) /* IMO frequency 12 MHz */ +#define CY_PM_FASTCLK_IMO_CR_F2XON (0x10u) /* IMO doubler enable */ +#define CY_PM_FASTCLK_IMO_CR_USB (0x40u) /* IMO is in USB mode */ + +#define CY_PM_MASTER_CLK_SRC_IMO (0u) +#define CY_PM_MASTER_CLK_SRC_PLL (1u) +#define CY_PM_MASTER_CLK_SRC_XTAL (2u) +#define CY_PM_MASTER_CLK_SRC_DSI (3u) +#define CY_PM_MASTER_CLK_SRC_MASK (3u) + +#define CY_PM_PLL_CFG0_ENABLE (0x01u) /* PLL enable */ +#define CY_PM_PLL_STATUS_LOCK (0x01u) /* PLL Lock Status */ +#define CY_PM_XMHZ_CSR_ENABLE (0x01u) /* Enable X MHz OSC */ +#define CY_PM_XMHZ_CSR_XERR (0x80u) /* High indicates failure */ +#define CY_PM_BOOST_ENABLE (0x08u) /* Boost enable */ +#define CY_PM_ILO_CR0_EN_1K (0x02u) /* Enable 1kHz ILO */ +#define CY_PM_ILO_CR0_EN_100K (0x04u) /* Enable 100kHz ILO */ +#define CY_PM_ILO_CR0_PD_MODE (0x10u) /* Power down mode for ILO*/ +#define CY_PM_X32_CR_X32EN (0x01u) /* Enable 32kHz OSC */ + +#define CY_PM_CTW_IE (0x08u) /* CTW interrupt enable */ +#define CY_PM_CTW_EN (0x04u) /* CTW enable */ +#define CY_PM_FTW_IE (0x02u) /* FTW interrupt enable */ +#define CY_PM_FTW_EN (0x01u) /* FTW enable */ +#define CY_PM_1PPS_EN (0x10u) /* 1PPS enable */ +#define CY_PM_1PPS_IE (0x20u) /* 1PPS interrupt enable */ + + +#define CY_PM_ACT_EN_CLK_A_MASK (0x0Fu) +#define CY_PM_ACT_EN_CLK_D_MASK (0xFFu) + +#define CY_PM_DIV_BY_ONE (0x00u) + +/* Internal Main Oscillator Control Register */ +#define CY_PM_FASTCLK_IMO_CR_XCLKEN (0x20u) + +/* Clock distribution configuration Register */ +#define CY_PM_CLKDIST_IMO_OUT_MASK (0x30u) +#define CY_PM_CLKDIST_IMO_OUT_IMO (0x00u) +#define CY_PM_CLKDIST_IMO2X_SRC (0x40u) + +/* Waiting for the hibernate/sleep regulator to stabilize */ +#define CY_PM_MODE_CSR_PWRUP_PULSE_Q (0x08u) + +#define CY_PM_MODE_CSR_ACTIVE (0x00u) /* Active power mode */ +#define CY_PM_MODE_CSR_ALT_ACT (0x01u) /* Alternate Active power */ +#define CY_PM_MODE_CSR_SLEEP (0x03u) /* Sleep power mode */ +#define CY_PM_MODE_CSR_HIBERNATE (0x04u) /* Hibernate power mode */ +#define CY_PM_MODE_CSR_MASK (0x07u) + +/* I2C regulator backup enable */ +#define CY_PM_PWRSYS_CR1_I2CREG_BACKUP (0x04u) + +/* When set, prepares the system to disable the LDO-A */ +#define CY_PM_PWRSYS_CR1_LDOA_ISO (0x01u) + +/* When set, disables the analog LDO regulator */ +#define CY_PM_PWRSYS_CR1_LDOA_DIS (0x02u) + +#define CY_PM_PWRSYS_WAKE_TR2_VCCD_CLK_DET (0x04u) + +#define CY_PM_FTW_INT (0x01u) /* FTW event has occured */ +#define CY_PM_CTW_INT (0x02u) /* CTW event has occured */ +#define CY_PM_ONEPPS_INT (0x04u) /* 1PPS event has occured */ + +/* Active Power Mode Configuration Register 0 */ +#define CY_PM_ACT_CFG0_IMO (0x10u) /* IMO enable in Active */ + +/* Cache Control Register (same mask for all device revisions) */ +#define CY_PM_CACHE_CR_CYCLES_MASK (0xC0u) + +/* Bus Clock divider to divide-by-one */ +#define CY_PM_BUS_CLK_DIV_BY_ONE (0x00u) + +/* HVI/LVI feature on the external analog and digital supply mask */ +#define CY_PM_RESET_CR1_HVI_LVI_EN_MASK (0x07u) + +/* The high-voltage-interrupt feature on the external analog supply */ +#define CY_PM_RESET_CR1_HVIA_EN (0x04u) + +/* The low-voltage-interrupt feature on the external analog supply */ +#define CY_PM_RESET_CR1_LVIA_EN (0x02u) + +/* The low-voltage-interrupt feature on the external digital supply */ +#define CY_PM_RESET_CR1_LVID_EN (0x01u) + +/* Allows the system to program delays on clk_sync_d */ +#define CY_PM_CLKDIST_DELAY_EN (0x04u) + + +#define CY_PM_WAKEUP_SRC_CMPS_MASK (0x000Fu) + +/* Holdoff mask sleep trim */ +#define CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK (0x1Fu) + +#if(CY_PSOC3) + + /* CPU clock divider mask */ + #define CY_PM_CLKDIST_CPU_DIV_MASK (0xF0u) + + /* Serial Wire View (SWV) clock enable */ + #define CY_PM_MLOGIC_DBG_SWV_CLK_EN (0x04u) + + /* Port drive mode */ + #define CY_PM_PRT1_PC3_DM_MASK (0xf1u) + + /* Mode 6, stong pull-up, strong pull-down */ + #define CY_PM_PRT1_PC3_DM_STRONG (0x0Cu) + + /* When set, enables buzz wakeups */ + #define CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ (0x01u) + +#endif /* (CY_PSOC3) */ + + +/* Disable the sleep regulator and shorts vccd to vpwrsleep */ +#define CY_PM_PWRSYS_SLP_TR_BYPASS (0x10u) + +/* Boost Control 2: Select external precision reference */ +#define CY_PM_BOOST_CR2_EREFSEL_EXT (0x08u) + +#if(CY_PSOC3) + + #define CY_PM_PWRSYS_WAKE_TR0 (0xFFu) + #define CY_PM_PWRSYS_WAKE_TR1 (0x90u) + +#endif /* (CY_PSOC3) */ + +#if(CY_PSOC5) + + #define CY_PM_PWRSYS_WAKE_TR0 (0xFFu) + #define CY_PM_PWRSYS_WAKE_TR1 (0xB0u) + +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from cy_boot 3.30 +*******************************************************************************/ +#if(CY_PSOC3) + + /* Was removed as redundant */ + #define CY_PM_FTW_INTERVAL_MASK (0xFFu) + +#endif /* (CY_PSOC3) */ + +/* Was removed as redundant */ +#define CY_PM_CTW_INTERVAL_MASK (0x0Fu) + +#endif /* (CY_BOOT_CYPM_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cybootloader.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cybootloader.c new file mode 100755 index 00000000..1faf25ba --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cybootloader.c @@ -0,0 +1,1206 @@ +/* GENERATED CODE -- CHANGES WILL BE OVERWRITTEN */ + +#include "cytypes.h" + + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +__attribute__ ((__section__(".cyloadermeta"), used)) +#elif defined(__ICCARM__) +#pragma location=".cyloadermeta" +#else +#error "Unsupported toolchain" +#endif +const uint8 cy_meta_loader[] = { + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x01u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +__attribute__ ((__section__(".cybootloader"), used)) +#elif defined(__ICCARM__) +#pragma location=".cybootloader" +#else +#error "Unsupported toolchain" +#endif +const uint8 cy_bootloader[] = { + 0x00u, 0x40u, 0x00u, 0x20u, 0x11u, 0x00u, 0x00u, 0x00u, + 0x59u, 0x01u, 0x00u, 0x00u, 0x59u, 0x01u, 0x00u, 0x00u, + 0x08u, 0xB5u, 0x04u, 0x4Bu, 0x04u, 0x48u, 0x1Au, 0x68u, + 0x02u, 0x60u, 0x00u, 0xF0u, 0x87u, 0xFCu, 0x00u, 0xF0u, + 0x9Du, 0xF8u, 0x00u, 0xBFu, 0xFAu, 0x46u, 0x00u, 0x40u, + 0xBCu, 0x76u, 0x00u, 0x40u, 0x10u, 0xB5u, 0x05u, 0x4Cu, + 0x23u, 0x78u, 0x33u, 0xB9u, 0x04u, 0x48u, 0x10u, 0xB1u, + 0x04u, 0x48u, 0xAFu, 0xF3u, 0x00u, 0x80u, 0x01u, 0x21u, + 0x21u, 0x70u, 0x10u, 0xBDu, 0x28u, 0xC1u, 0xFFu, 0x1Fu, + 0x00u, 0x00u, 0x00u, 0x00u, 0x24u, 0x20u, 0x00u, 0x00u, + 0x08u, 0xB5u, 0x06u, 0x4Bu, 0x1Bu, 0xB1u, 0x06u, 0x48u, + 0x06u, 0x49u, 0xAFu, 0xF3u, 0x00u, 0x80u, 0x06u, 0x48u, + 0x01u, 0x68u, 0x11u, 0xB1u, 0x05u, 0x4Au, 0x02u, 0xB1u, + 0x90u, 0x47u, 0x08u, 0xBDu, 0x00u, 0x00u, 0x00u, 0x00u, + 0x24u, 0x20u, 0x00u, 0x00u, 0x2Cu, 0xC1u, 0xFFu, 0x1Fu, + 0x08u, 0xC1u, 0xFFu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, + 0x08u, 0xB5u, 0x34u, 0x4Bu, 0x1Au, 0x78u, 0x02u, 0xF0u, + 0xFEu, 0x00u, 0x18u, 0x70u, 0x93u, 0xF8u, 0x7Au, 0x10u, + 0x01u, 0xF0u, 0xFEu, 0x02u, 0x83u, 0xF8u, 0x7Au, 0x20u, + 0x2Fu, 0x33u, 0x18u, 0x78u, 0x00u, 0xF0u, 0xFEu, 0x01u, + 0x19u, 0x70u, 0x13u, 0xF8u, 0x01u, 0x2Cu, 0x02u, 0xF0u, + 0xFEu, 0x00u, 0x03u, 0xF8u, 0x01u, 0x0Cu, 0x13u, 0xF8u, + 0x0Cu, 0x1Cu, 0x01u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u, + 0x0Cu, 0x2Cu, 0x13u, 0xF8u, 0x2Au, 0x0Cu, 0x00u, 0xF0u, + 0xFEu, 0x01u, 0x03u, 0xF8u, 0x2Au, 0x1Cu, 0x13u, 0xF8u, + 0x2Eu, 0x2Cu, 0x02u, 0xF0u, 0xFEu, 0x00u, 0x03u, 0xF8u, + 0x2Eu, 0x0Cu, 0x13u, 0xF8u, 0x0Du, 0x1Cu, 0x01u, 0xF0u, + 0xFEu, 0x02u, 0x03u, 0xF8u, 0x0Du, 0x2Cu, 0x13u, 0xF8u, + 0x2Bu, 0x0Cu, 0x00u, 0xF0u, 0xFEu, 0x01u, 0x03u, 0xF8u, + 0x2Bu, 0x1Cu, 0x13u, 0xF8u, 0x08u, 0x2Cu, 0x02u, 0xF0u, + 0xFEu, 0x00u, 0x03u, 0xF8u, 0x08u, 0x0Cu, 0x0Cu, 0x3Bu, + 0x03u, 0x33u, 0x19u, 0x78u, 0x01u, 0xF0u, 0xFEu, 0x02u, + 0x1Au, 0x70u, 0x58u, 0x7Bu, 0x00u, 0xF0u, 0xFEu, 0x01u, + 0x59u, 0x73u, 0x1Au, 0x7Bu, 0x02u, 0xF0u, 0xFEu, 0x00u, + 0x18u, 0x73u, 0x13u, 0xF8u, 0x11u, 0x1Cu, 0x01u, 0xF0u, + 0xFEu, 0x02u, 0x03u, 0xF8u, 0x11u, 0x2Cu, 0x13u, 0xF8u, + 0x12u, 0x0Cu, 0x00u, 0xF0u, 0xFEu, 0x01u, 0x03u, 0xF8u, + 0x12u, 0x1Cu, 0x13u, 0xF8u, 0x15u, 0x2Cu, 0x02u, 0xF0u, + 0xFEu, 0x00u, 0x03u, 0xF8u, 0x15u, 0x0Cu, 0x13u, 0xF8u, + 0x16u, 0x1Cu, 0x01u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u, + 0x16u, 0x2Cu, 0x93u, 0xF8u, 0x55u, 0x00u, 0x00u, 0xF0u, + 0xFEu, 0x01u, 0x83u, 0xF8u, 0x55u, 0x10u, 0x00u, 0xF0u, + 0xADu, 0xFBu, 0xFEu, 0xE7u, 0x02u, 0x50u, 0x00u, 0x40u, + 0xFEu, 0xE7u, 0x00u, 0x00u, 0x08u, 0xB5u, 0x12u, 0x49u, + 0x12u, 0x4Bu, 0x4Au, 0x1Cu, 0x1Au, 0xD0u, 0x53u, 0xF8u, + 0x10u, 0x6Cu, 0x53u, 0xF8u, 0x0Cu, 0x0Cu, 0x53u, 0xF8u, + 0x08u, 0x5Cu, 0x00u, 0x22u, 0xAAu, 0x42u, 0x00u, 0xEBu, + 0x02u, 0x04u, 0x03u, 0xD0u, 0xB4u, 0x58u, 0x84u, 0x50u, + 0x04u, 0x32u, 0xF7u, 0xE7u, 0x53u, 0xF8u, 0x04u, 0x0Cu, + 0x00u, 0x22u, 0x82u, 0x42u, 0x03u, 0xD0u, 0x00u, 0x25u, + 0xA5u, 0x50u, 0x04u, 0x32u, 0xF9u, 0xE7u, 0x01u, 0x39u, + 0x10u, 0x33u, 0xE2u, 0xE7u, 0x01u, 0xF0u, 0x06u, 0xFFu, + 0xFFu, 0xF7u, 0x6Eu, 0xFFu, 0xFEu, 0xE7u, 0x00u, 0xBFu, + 0x00u, 0x00u, 0x00u, 0x00u, 0x80u, 0x22u, 0x00u, 0x00u, + 0x08u, 0xB5u, 0x10u, 0x4Au, 0x10u, 0x4Bu, 0x1Au, 0x60u, + 0x98u, 0x68u, 0x40u, 0xF4u, 0x00u, 0x72u, 0x9Au, 0x60u, + 0x00u, 0x23u, 0x03u, 0x2Bu, 0x96u, 0xBFu, 0x0Du, 0x4Au, + 0x0Du, 0x49u, 0x52u, 0xF8u, 0x23u, 0x10u, 0x0Du, 0x4Au, + 0x42u, 0xF8u, 0x23u, 0x10u, 0x01u, 0x33u, 0x30u, 0x2Bu, + 0xF3u, 0xD1u, 0x0Bu, 0x49u, 0x0Bu, 0x4Bu, 0x08u, 0x78u, + 0x0Bu, 0x49u, 0x18u, 0x70u, 0x0Au, 0x60u, 0x00u, 0xF0u, + 0x17u, 0xF8u, 0x0Au, 0x48u, 0x00u, 0x22u, 0x02u, 0x60u, + 0x08u, 0xBDu, 0x00u, 0xBFu, 0x00u, 0x04u, 0xFAu, 0x05u, + 0x0Cu, 0xEDu, 0x00u, 0xE0u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x59u, 0x01u, 0x00u, 0x00u, 0x00u, 0xC0u, 0xFFu, 0x1Fu, + 0xBCu, 0x76u, 0x00u, 0x40u, 0x04u, 0xC1u, 0xFFu, 0x1Fu, + 0x08u, 0xEDu, 0x00u, 0xE0u, 0x00u, 0xC1u, 0xFFu, 0x1Fu, + 0xF8u, 0xB5u, 0x72u, 0xB6u, 0x67u, 0x4Bu, 0x01u, 0x22u, + 0xA3u, 0xF5u, 0xA0u, 0x61u, 0xA1u, 0xF5u, 0x80u, 0x75u, + 0x06u, 0x20u, 0x52u, 0x24u, 0x64u, 0x4Eu, 0x1Au, 0x70u, + 0x08u, 0x70u, 0x2Cu, 0x70u, 0x37u, 0x78u, 0x63u, 0x4Bu, + 0x63u, 0x4Au, 0x40u, 0xF6u, 0x18u, 0x00u, 0x41u, 0xF2u, + 0x51u, 0x21u, 0x17u, 0x70u, 0x19u, 0x25u, 0x18u, 0x80u, + 0x00u, 0x24u, 0x23u, 0xF8u, 0x02u, 0x1Cu, 0x5Fu, 0x4Eu, + 0x4Fu, 0xF4u, 0xF0u, 0x70u, 0x37u, 0x78u, 0x07u, 0xF0u, + 0x01u, 0x02u, 0x42u, 0xEAu, 0x44u, 0x04u, 0x00u, 0xF0u, + 0x7Fu, 0xFBu, 0x01u, 0x3Du, 0x04u, 0xF0u, 0x03u, 0x04u, + 0x17u, 0xD0u, 0x03u, 0x2Cu, 0xEFu, 0xD1u, 0x58u, 0x48u, + 0x58u, 0x4Fu, 0x00u, 0x26u, 0x4Fu, 0xF4u, 0x80u, 0x73u, + 0x57u, 0x4Du, 0x07u, 0x21u, 0x48u, 0x22u, 0x02u, 0x24u, + 0x03u, 0x80u, 0x01u, 0x70u, 0x3Eu, 0x70u, 0xBAu, 0x70u, + 0x06u, 0x70u, 0x46u, 0x71u, 0x00u, 0xF8u, 0x03u, 0x4Cu, + 0x28u, 0x78u, 0x40u, 0xF0u, 0x04u, 0x03u, 0x2Bu, 0x70u, + 0x00u, 0xE0u, 0xFEu, 0xE7u, 0x4Fu, 0x4Fu, 0x06u, 0x21u, + 0x01u, 0xFBu, 0x06u, 0x72u, 0x00u, 0x21u, 0x10u, 0x68u, + 0x01u, 0x36u, 0x92u, 0x88u, 0x01u, 0xF0u, 0xADu, 0xFEu, + 0x07u, 0x2Eu, 0xF3u, 0xD1u, 0x00u, 0x23u, 0x19u, 0x46u, + 0x49u, 0x4Cu, 0x00u, 0x22u, 0x18u, 0x59u, 0x30u, 0x34u, + 0xC6u, 0xB2u, 0x20u, 0xF0u, 0xFFu, 0x07u, 0x04u, 0xEBu, + 0x41u, 0x04u, 0xD5u, 0xB2u, 0xAEu, 0x42u, 0x09u, 0xD0u, + 0x04u, 0xEBu, 0x42u, 0x0Cu, 0x14u, 0xF8u, 0x12u, 0x50u, + 0x9Cu, 0xF8u, 0x01u, 0xE0u, 0x01u, 0x32u, 0x05u, 0xF8u, + 0x07u, 0xE0u, 0xF2u, 0xE7u, 0x04u, 0x33u, 0xC0u, 0xB2u, + 0x30u, 0x2Bu, 0x01u, 0x44u, 0xE4u, 0xD1u, 0x3Du, 0x4Cu, + 0x22u, 0x78u, 0x42u, 0xF0u, 0x02u, 0x00u, 0x20u, 0x70u, + 0x21u, 0x7Cu, 0x3Bu, 0x48u, 0x41u, 0xF0u, 0x02u, 0x03u, + 0x3Au, 0x49u, 0x23u, 0x74u, 0x0Cu, 0x78u, 0x44u, 0xF0u, + 0x40u, 0x02u, 0x0Au, 0x70u, 0x03u, 0x78u, 0x38u, 0x4Au, + 0x43u, 0xF0u, 0x10u, 0x04u, 0x37u, 0x4Bu, 0x04u, 0x70u, + 0x18u, 0x68u, 0x5Cu, 0x68u, 0x10u, 0x60u, 0x18u, 0x89u, + 0x54u, 0x60u, 0x10u, 0x81u, 0x1Au, 0x46u, 0x34u, 0x48u, + 0x52u, 0xF8u, 0x0Au, 0x4Fu, 0x04u, 0x60u, 0x54u, 0x68u, + 0x12u, 0x89u, 0x44u, 0x60u, 0x02u, 0x81u, 0x1Au, 0x46u, + 0x52u, 0xF8u, 0x14u, 0x4Fu, 0x52u, 0x68u, 0x40u, 0xF8u, + 0xCEu, 0x4Cu, 0x40u, 0xF8u, 0xCAu, 0x2Cu, 0x1Au, 0x46u, + 0x52u, 0xF8u, 0x1Cu, 0x4Fu, 0x52u, 0x68u, 0x40u, 0xF8u, + 0xBEu, 0x4Cu, 0x40u, 0xF8u, 0xBAu, 0x2Cu, 0x1Au, 0x46u, + 0x52u, 0xF8u, 0x24u, 0x4Fu, 0x52u, 0x68u, 0x40u, 0xF8u, + 0xAEu, 0x4Cu, 0x40u, 0xF8u, 0xAAu, 0x2Cu, 0x1Au, 0x46u, + 0x52u, 0xF8u, 0x2Cu, 0x4Fu, 0x40u, 0xF8u, 0x9Eu, 0x4Cu, + 0x52u, 0x68u, 0x40u, 0xF8u, 0x9Au, 0x2Cu, 0x53u, 0xF8u, + 0x34u, 0x0Fu, 0x20u, 0x4Au, 0x5Bu, 0x68u, 0x10u, 0x60u, + 0x1Fu, 0x48u, 0x53u, 0x60u, 0x02u, 0x78u, 0x42u, 0xF0u, + 0x08u, 0x03u, 0x03u, 0x70u, 0x1Du, 0x48u, 0x1Eu, 0x4Au, + 0x03u, 0x78u, 0x03u, 0xF0u, 0x07u, 0x00u, 0x1Bu, 0x09u, + 0x10u, 0x70u, 0x53u, 0x70u, 0x1Bu, 0x4Au, 0x44u, 0x20u, + 0x10u, 0x70u, 0x1Bu, 0x4Au, 0x0Bu, 0x46u, 0x0Cu, 0x31u, + 0x53u, 0xF8u, 0x04u, 0x0Bu, 0x8Bu, 0x42u, 0x42u, 0xF8u, + 0x04u, 0x0Bu, 0xF9u, 0xD1u, 0x19u, 0x88u, 0x11u, 0x80u, + 0xF8u, 0xBDu, 0x00u, 0xBFu, 0x00u, 0x48u, 0x00u, 0x40u, + 0x0Fu, 0x01u, 0x00u, 0x49u, 0x22u, 0x42u, 0x00u, 0x40u, + 0xA1u, 0x46u, 0x00u, 0x40u, 0x25u, 0x42u, 0x00u, 0x40u, + 0x04u, 0x40u, 0x00u, 0x40u, 0x06u, 0x40u, 0x00u, 0x40u, + 0xE8u, 0x46u, 0x00u, 0x40u, 0x28u, 0x20u, 0x00u, 0x00u, + 0x54u, 0x20u, 0x00u, 0x00u, 0x03u, 0x50u, 0x01u, 0x40u, + 0xC2u, 0x43u, 0x00u, 0x40u, 0xA0u, 0x43u, 0x00u, 0x40u, + 0x00u, 0x51u, 0x00u, 0x40u, 0xB2u, 0x20u, 0x00u, 0x00u, + 0xF0u, 0x51u, 0x00u, 0x40u, 0x62u, 0x51u, 0x00u, 0x40u, + 0x22u, 0x43u, 0x00u, 0x40u, 0xCFu, 0x01u, 0x00u, 0x49u, + 0x6Eu, 0x58u, 0x00u, 0x40u, 0x76u, 0x58u, 0x00u, 0x40u, + 0xB0u, 0x43u, 0x00u, 0x40u, 0x00u, 0x47u, 0x00u, 0x00u, + 0x43u, 0x1Eu, 0x10u, 0xB5u, 0x02u, 0x46u, 0x06u, 0x2Bu, + 0x0Du, 0xD8u, 0xDFu, 0xE8u, 0x03u, 0xF0u, 0x06u, 0x0Eu, + 0x23u, 0x04u, 0x08u, 0x0Au, 0x21u, 0x00u, 0x16u, 0x48u, + 0x08u, 0xE0u, 0x16u, 0x4Bu, 0x1Bu, 0xE0u, 0x16u, 0x48u, + 0x04u, 0xE0u, 0x16u, 0x48u, 0x02u, 0xE0u, 0x00u, 0x20u, + 0x00u, 0xE0u, 0x15u, 0x48u, 0x41u, 0x78u, 0x00u, 0x78u, + 0x41u, 0xEAu, 0x00u, 0x20u, 0x02u, 0x2Au, 0x04u, 0xD0u, + 0x03u, 0x2Au, 0x07u, 0xD0u, 0x01u, 0x2Au, 0x15u, 0xD1u, + 0x04u, 0xE0u, 0x02u, 0x02u, 0x42u, 0xEAu, 0x10u, 0x23u, + 0x98u, 0xB2u, 0x10u, 0xBDu, 0x00u, 0xBAu, 0x10u, 0xBDu, + 0x0Cu, 0x4Bu, 0x00u, 0xE0u, 0x0Cu, 0x4Bu, 0xD8u, 0x78u, + 0x9Cu, 0x78u, 0x59u, 0x78u, 0x1Bu, 0x78u, 0x40u, 0xEAu, + 0x03u, 0x60u, 0x40u, 0xEAu, 0x04u, 0x23u, 0x43u, 0xEAu, + 0x01u, 0x40u, 0xE3u, 0xE7u, 0x10u, 0xBDu, 0x00u, 0xBFu, + 0xD2u, 0xFFu, 0x01u, 0x00u, 0xC1u, 0xFFu, 0x01u, 0x00u, + 0xD6u, 0xFFu, 0x01u, 0x00u, 0xD4u, 0xFFu, 0x01u, 0x00u, + 0xC5u, 0xFFu, 0x01u, 0x00u, 0xD8u, 0xFFu, 0x01u, 0x00u, + 0xC9u, 0xFFu, 0x01u, 0x00u, 0x70u, 0xB5u, 0x02u, 0x20u, + 0xFFu, 0xF7u, 0xB6u, 0xFFu, 0x06u, 0x46u, 0x03u, 0x20u, + 0xFFu, 0xF7u, 0xB2u, 0xFFu, 0x71u, 0x1Cu, 0x00u, 0xEBu, + 0x01u, 0x26u, 0x02u, 0x20u, 0xFFu, 0xF7u, 0xACu, 0xFFu, + 0x00u, 0x24u, 0x01u, 0x30u, 0x01u, 0x02u, 0x25u, 0x46u, + 0xB1u, 0x42u, 0x09u, 0xD2u, 0x11u, 0xF8u, 0x01u, 0x0Bu, + 0x42u, 0x1Eu, 0xD3u, 0xB2u, 0x04u, 0x19u, 0xFDu, 0x2Bu, + 0x98u, 0xBFu, 0x01u, 0x25u, 0xE4u, 0xB2u, 0xF3u, 0xE7u, + 0x02u, 0x20u, 0xFFu, 0xF7u, 0x99u, 0xFFu, 0x0Fu, 0x49u, + 0x42u, 0x1Cu, 0x13u, 0x02u, 0xDBu, 0x08u, 0x8Eu, 0x42u, + 0x01u, 0xD0u, 0xF6u, 0x08u, 0x01u, 0xE0u, 0x4Fu, 0xF4u, + 0x80u, 0x46u, 0xB3u, 0x42u, 0x06u, 0xD2u, 0x03u, 0xF1u, + 0x90u, 0x41u, 0x08u, 0x78u, 0x01u, 0x33u, 0x02u, 0x19u, + 0xD4u, 0xB2u, 0xF6u, 0xE7u, 0x05u, 0x48u, 0x64u, 0x42u, + 0x02u, 0x78u, 0xE4u, 0xB2u, 0x94u, 0x42u, 0x01u, 0xD0u, + 0x06u, 0x20u, 0x70u, 0xBDu, 0x00u, 0x2Du, 0xFBu, 0xD0u, + 0x00u, 0x20u, 0x70u, 0xBDu, 0xC0u, 0xFFu, 0x01u, 0x00u, + 0x2Du, 0xE9u, 0xF0u, 0x4Fu, 0xADu, 0xF5u, 0x61u, 0x7Du, + 0x80u, 0x46u, 0x00u, 0xF0u, 0xE5u, 0xFBu, 0x62u, 0xB6u, + 0x00u, 0x26u, 0xB2u, 0x46u, 0x4Fu, 0xF0u, 0x0Au, 0x09u, + 0x37u, 0x46u, 0xB8u, 0xF1u, 0x00u, 0x0Fu, 0x01u, 0xD1u, + 0xFFu, 0x23u, 0x00u, 0xE0u, 0x43u, 0x46u, 0x4Au, 0xA8u, + 0x4Fu, 0xF4u, 0x96u, 0x71u, 0x01u, 0xAAu, 0x00u, 0xF0u, + 0x0Du, 0xFCu, 0xB8u, 0xF1u, 0x00u, 0x0Fu, 0x03u, 0xD0u, + 0x09u, 0xF1u, 0xFFu, 0x39u, 0x5Fu, 0xFAu, 0x89u, 0xF9u, + 0xB9u, 0xF1u, 0x00u, 0x0Fu, 0x02u, 0xD0u, 0x00u, 0x28u, + 0xE7u, 0xD1u, 0x01u, 0xE0u, 0x00u, 0x28u, 0x71u, 0xD1u, + 0xBDu, 0xF8u, 0x04u, 0x20u, 0x06u, 0x2Au, 0x40u, 0xF2u, + 0x7Bu, 0x81u, 0x9Du, 0xF8u, 0x28u, 0x31u, 0x01u, 0x2Bu, + 0x40u, 0xF0u, 0x76u, 0x81u, 0x9Du, 0xF8u, 0x2Au, 0x01u, + 0x9Du, 0xF8u, 0x2Bu, 0x51u, 0x4Au, 0xA9u, 0x40u, 0xEAu, + 0x05u, 0x25u, 0xECu, 0x1Du, 0x4Bu, 0x19u, 0x94u, 0x42u, + 0x58u, 0x79u, 0x19u, 0x79u, 0x00u, 0xF2u, 0x66u, 0x81u, + 0x9Au, 0x79u, 0x17u, 0x2Au, 0x40u, 0xF0u, 0x64u, 0x81u, + 0x2Bu, 0x1Du, 0x9Bu, 0xB2u, 0x00u, 0x22u, 0x3Bu, 0xB1u, + 0x0Du, 0xF2u, 0x27u, 0x14u, 0xE4u, 0x5Cu, 0x01u, 0x3Bu, + 0x12u, 0x19u, 0x92u, 0xB2u, 0x9Bu, 0xB2u, 0xF6u, 0xE7u, + 0x52u, 0x42u, 0x41u, 0xEAu, 0x00u, 0x20u, 0x91u, 0xB2u, + 0x88u, 0x42u, 0x40u, 0xF0u, 0x53u, 0x81u, 0x4Au, 0xE0u, + 0x00u, 0x2Eu, 0x00u, 0xF0u, 0x4Du, 0x81u, 0x01u, 0x2Du, + 0x4Fu, 0xF0u, 0x00u, 0x04u, 0x40u, 0xF0u, 0x3Cu, 0x81u, + 0xBBu, 0xF1u, 0x01u, 0x0Fu, 0x00u, 0xF2u, 0x38u, 0x81u, + 0xFFu, 0x23u, 0x8Du, 0xF8u, 0x2Cu, 0x41u, 0x8Du, 0xF8u, + 0x2Du, 0x41u, 0x25u, 0x46u, 0x8Du, 0xF8u, 0x2Eu, 0x31u, + 0x8Du, 0xF8u, 0x2Fu, 0x61u, 0x04u, 0x24u, 0x01u, 0x20u, + 0x00u, 0x22u, 0x21u, 0x1Du, 0xADu, 0xF8u, 0x06u, 0x40u, + 0x8Du, 0xF8u, 0x28u, 0x01u, 0x8Du, 0xF8u, 0x29u, 0x51u, + 0x8Du, 0xF8u, 0x2Au, 0x41u, 0x8Du, 0xF8u, 0x2Bu, 0x21u, + 0x8Bu, 0xB2u, 0x0Du, 0xF2u, 0x27u, 0x10u, 0xC1u, 0x5Cu, + 0x01u, 0x3Bu, 0x52u, 0x18u, 0x9Bu, 0xB2u, 0x92u, 0xB2u, + 0x00u, 0x2Bu, 0xF6u, 0xD1u, 0x50u, 0x42u, 0x81u, 0xB2u, + 0x08u, 0x0Au, 0x4Bu, 0xAAu, 0x0Du, 0xF2u, 0x2Du, 0x13u, + 0x11u, 0x55u, 0x18u, 0x55u, 0x17u, 0x21u, 0x0Du, 0xF5u, + 0x97u, 0x72u, 0xE3u, 0x1Du, 0x11u, 0x55u, 0x4Au, 0xA8u, + 0x99u, 0xB2u, 0x0Du, 0xF1u, 0x06u, 0x02u, 0x96u, 0x23u, + 0x00u, 0xF0u, 0x62u, 0xFBu, 0xB8u, 0xF1u, 0x00u, 0x0Fu, + 0x3Fu, 0xF4u, 0x72u, 0xAFu, 0x00u, 0x2Eu, 0x00u, 0xF0u, + 0x12u, 0x81u, 0x01u, 0x26u, 0x69u, 0xE7u, 0x9Du, 0xF8u, + 0x29u, 0x21u, 0x9Du, 0xF8u, 0x2Cu, 0xB1u, 0xA2u, 0xF1u, + 0x31u, 0x03u, 0x0Au, 0x2Bu, 0x00u, 0xF2u, 0xF7u, 0x80u, + 0x01u, 0xA1u, 0x51u, 0xF8u, 0x23u, 0xF0u, 0x00u, 0xBFu, + 0xB5u, 0x06u, 0x00u, 0x00u, 0xD9u, 0x05u, 0x00u, 0x00u, + 0x6Fu, 0x08u, 0x00u, 0x00u, 0xD3u, 0x06u, 0x00u, 0x00u, + 0x85u, 0x07u, 0x00u, 0x00u, 0x6Fu, 0x08u, 0x00u, 0x00u, + 0x8Bu, 0x07u, 0x00u, 0x00u, 0xA9u, 0x07u, 0x00u, 0x00u, + 0xD3u, 0x06u, 0x00u, 0x00u, 0xC3u, 0x07u, 0x00u, 0x00u, + 0x4Fu, 0x08u, 0x00u, 0x00u, 0x00u, 0x2Eu, 0x00u, 0xF0u, + 0xDFu, 0x80u, 0x00u, 0x2Du, 0x40u, 0xF0u, 0xDCu, 0x80u, + 0xFFu, 0xF7u, 0xF0u, 0xFEu, 0xD0u, 0xF1u, 0x01u, 0x02u, + 0x38u, 0xBFu, 0x00u, 0x22u, 0x8Du, 0xF8u, 0x2Cu, 0x21u, + 0xBBu, 0xE0u, 0x34u, 0x2Au, 0x12u, 0xD1u, 0x00u, 0x2Eu, + 0x00u, 0xF0u, 0xCEu, 0x80u, 0x03u, 0x2Du, 0x40u, 0xF0u, + 0xCBu, 0x80u, 0xABu, 0xF1u, 0x40u, 0x07u, 0x3Fu, 0x2Fu, + 0x8Cu, 0xBFu, 0x4Fu, 0xF4u, 0x90u, 0x77u, 0x10u, 0x27u, + 0x95u, 0xA8u, 0x00u, 0x21u, 0x3Au, 0x46u, 0x01u, 0xF0u, + 0x88u, 0xFCu, 0x05u, 0xE0u, 0x00u, 0x2Eu, 0x00u, 0xF0u, + 0xBBu, 0x80u, 0x02u, 0x2Du, 0x40u, 0xF2u, 0xB8u, 0x80u, + 0x03u, 0x3Du, 0x95u, 0xABu, 0x2Au, 0x46u, 0xD8u, 0x19u, + 0x0Du, 0xF2u, 0x2Fu, 0x11u, 0x01u, 0xF0u, 0x70u, 0xFCu, + 0xABu, 0xF1u, 0x40u, 0x00u, 0x7Au, 0x19u, 0x3Fu, 0x28u, + 0x96u, 0xB2u, 0x03u, 0xD8u, 0x00u, 0xF0u, 0xD4u, 0xF9u, + 0x10u, 0x24u, 0x01u, 0xE0u, 0x4Fu, 0xF4u, 0x90u, 0x74u, + 0xA6u, 0x42u, 0x40u, 0xF0u, 0x97u, 0x80u, 0x9Du, 0xF8u, + 0x2Eu, 0x11u, 0x9Du, 0xF8u, 0x2Du, 0x71u, 0xBBu, 0xF1u, + 0x3Fu, 0x0Fu, 0x47u, 0xEAu, 0x01u, 0x25u, 0x11u, 0xD8u, + 0xBAu, 0xF1u, 0x00u, 0x0Fu, 0x0Eu, 0xD1u, 0x51u, 0x46u, + 0x4Fu, 0xF4u, 0x90u, 0x72u, 0x02u, 0xA8u, 0x01u, 0xF0u, + 0x58u, 0xFCu, 0x01u, 0x20u, 0xFFu, 0x21u, 0x02u, 0xAAu, + 0x4Fu, 0xF4u, 0x90u, 0x73u, 0x00u, 0xF0u, 0x64u, 0xF9u, + 0x4Fu, 0xF0u, 0x01u, 0x0Au, 0x33u, 0x46u, 0x58u, 0x46u, + 0x29u, 0x46u, 0x95u, 0xAAu, 0x00u, 0xF0u, 0x5Cu, 0xF9u, + 0x01u, 0x26u, 0x00u, 0x28u, 0x75u, 0xD0u, 0x00u, 0x27u, + 0x0Au, 0x25u, 0x75u, 0xE0u, 0x00u, 0x2Eu, 0x77u, 0xD0u, + 0x7Au, 0xE0u, 0x00u, 0x2Eu, 0x74u, 0xD0u, 0x7Cu, 0x19u, + 0xB4u, 0xF5u, 0x96u, 0x7Fu, 0x6Eu, 0xD8u, 0x95u, 0xA9u, + 0xC8u, 0x19u, 0x2Au, 0x46u, 0x4Bu, 0xA9u, 0x01u, 0xF0u, + 0x2Bu, 0xFCu, 0xA7u, 0xB2u, 0x00u, 0x25u, 0x63u, 0xE0u, + 0x00u, 0x2Du, 0x65u, 0xD1u, 0x3Au, 0x48u, 0x02u, 0xAEu, + 0x4Bu, 0xACu, 0x03u, 0xC8u, 0x86u, 0xE8u, 0x03u, 0x00u, + 0x84u, 0xE8u, 0x03u, 0x00u, 0x01u, 0x26u, 0x08u, 0x24u, + 0x21u, 0xE7u, 0x00u, 0x2Eu, 0x58u, 0xD0u, 0x03u, 0x2Du, + 0x56u, 0xD1u, 0x9Du, 0xF8u, 0x2Eu, 0x01u, 0x9Du, 0xF8u, + 0x2Du, 0x11u, 0xABu, 0xF1u, 0x40u, 0x02u, 0x3Fu, 0x2Au, + 0x41u, 0xEAu, 0x00u, 0x25u, 0x0Au, 0xD8u, 0x2Du, 0x01u, + 0x00u, 0x23u, 0x10u, 0x22u, 0x2Du, 0x48u, 0x11u, 0x18u, + 0x4Cu, 0x5Du, 0x01u, 0x3Au, 0x23u, 0x44u, 0xDBu, 0xB2u, + 0xF8u, 0xD1u, 0x26u, 0xE0u, 0x05u, 0xEBu, 0x0Bu, 0x23u, + 0x1Cu, 0x02u, 0x4Fu, 0xF4u, 0x80u, 0x72u, 0x00u, 0x23u, + 0x01u, 0x3Au, 0x10u, 0x5Du, 0x19u, 0x18u, 0xCBu, 0xB2u, + 0x00u, 0x2Au, 0xF9u, 0xD1u, 0xBBu, 0xF1u, 0x3Fu, 0x0Fu, + 0x17u, 0xD8u, 0x0Bu, 0xF5u, 0x10u, 0x34u, 0x05u, 0xEBu, + 0x04u, 0x20u, 0x41u, 0x01u, 0x54u, 0x5Cu, 0x01u, 0x32u, + 0x1Bu, 0x19u, 0x20u, 0x2Au, 0xDBu, 0xB2u, 0xF9u, 0xD1u, + 0xBBu, 0xF1u, 0x01u, 0x0Fu, 0x09u, 0xD1u, 0xFFu, 0x2Du, + 0x07u, 0xD1u, 0x1Bu, 0x4Du, 0x1Bu, 0x4Cu, 0x28u, 0x78u, + 0x19u, 0x1Au, 0x23u, 0x78u, 0xCAu, 0x1Au, 0x02u, 0xF0u, + 0xFFu, 0x03u, 0x5Du, 0x42u, 0x8Du, 0xF8u, 0x2Cu, 0x51u, + 0x00u, 0x25u, 0x01u, 0x24u, 0xDBu, 0xE6u, 0xFFu, 0xF7u, + 0x29u, 0xFEu, 0x10u, 0xB9u, 0x14u, 0x4Du, 0x80u, 0x24u, + 0x2Cu, 0x70u, 0x00u, 0xF0u, 0x47u, 0xF9u, 0x0Bu, 0xE0u, + 0x04u, 0x25u, 0xD0u, 0xE6u, 0x01u, 0x26u, 0x00u, 0x27u, + 0x04u, 0xE0u, 0x07u, 0x46u, 0x9Au, 0xE7u, 0x05u, 0x25u, + 0x00u, 0x24u, 0xC8u, 0xE6u, 0x03u, 0x25u, 0xFBu, 0xE7u, + 0x04u, 0x25u, 0xF9u, 0xE7u, 0x08u, 0x25u, 0xF7u, 0xE7u, + 0xB8u, 0xF1u, 0x00u, 0x0Fu, 0x01u, 0xD1u, 0x47u, 0x46u, + 0x5Eu, 0xE6u, 0x00u, 0x27u, 0xEDu, 0xE6u, 0x0Du, 0xF5u, + 0x61u, 0x7Du, 0xBDu, 0xE8u, 0xF0u, 0x8Fu, 0x00u, 0xBFu, + 0xF0u, 0x20u, 0x00u, 0x00u, 0xFFu, 0x7Fu, 0x00u, 0x40u, + 0xD0u, 0xFFu, 0x01u, 0x00u, 0xD1u, 0xFFu, 0x01u, 0x00u, + 0xFAu, 0x46u, 0x00u, 0x40u, 0x10u, 0xB5u, 0xC8u, 0xB0u, + 0x00u, 0xF0u, 0x94u, 0xF8u, 0x10u, 0xB1u, 0x00u, 0x20u, + 0x00u, 0xF0u, 0x16u, 0xF9u, 0x68u, 0x46u, 0x00u, 0xF0u, + 0xA1u, 0xF8u, 0x10u, 0xB1u, 0x00u, 0x20u, 0x00u, 0xF0u, + 0x0Fu, 0xF9u, 0x16u, 0x48u, 0x03u, 0x68u, 0x19u, 0x68u, + 0x00u, 0x23u, 0x0Au, 0x46u, 0x22u, 0xB1u, 0x12u, 0xF8u, + 0x01u, 0x4Du, 0xE3u, 0x18u, 0xDBu, 0xB2u, 0xF9u, 0xE7u, + 0x42u, 0x68u, 0x10u, 0x78u, 0xC4u, 0x1Au, 0x04u, 0xF0u, + 0xFFu, 0x03u, 0x83u, 0x42u, 0x00u, 0xD1u, 0x11u, 0xB9u, + 0x00u, 0x20u, 0x00u, 0xF0u, 0xF9u, 0xF8u, 0x0Cu, 0x4Cu, + 0xFFu, 0xF7u, 0xD4u, 0xFDu, 0x21u, 0x78u, 0x01u, 0xF0u, + 0xC0u, 0x02u, 0x40u, 0x2Au, 0x00u, 0xD0u, 0x18u, 0xB1u, + 0x00u, 0x20u, 0x20u, 0x70u, 0xFFu, 0xF7u, 0x0Cu, 0xFEu, + 0x14u, 0x20u, 0xFFu, 0xF7u, 0x09u, 0xFEu, 0x80u, 0x20u, + 0x20u, 0x70u, 0x00u, 0xF0u, 0xE7u, 0xF8u, 0x48u, 0xB0u, + 0x10u, 0xBDu, 0x00u, 0xBFu, 0x0Cu, 0xC1u, 0xFFu, 0x1Fu, + 0xFAu, 0x46u, 0x00u, 0x40u, 0x08u, 0xB5u, 0x0Au, 0x4Bu, + 0x1Au, 0x78u, 0x02u, 0xF0u, 0xC0u, 0x00u, 0x80u, 0x28u, + 0x0Cu, 0xD1u, 0x00u, 0x21u, 0x19u, 0x70u, 0x01u, 0x20u, + 0xFFu, 0xF7u, 0x6Au, 0xFDu, 0x30u, 0xB1u, 0x01u, 0x20u, + 0xFFu, 0xF7u, 0x66u, 0xFDu, 0xBDu, 0xE8u, 0x08u, 0x40u, + 0xFFu, 0xF7u, 0x60u, 0xBDu, 0x08u, 0xBDu, 0x00u, 0xBFu, + 0xFAu, 0x46u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x02u, 0x30u, 0x80u, 0x08u, 0x00u, 0xF0u, 0x05u, 0x80u, + 0x00u, 0xBFu, 0x01u, 0x38u, 0x00u, 0x46u, 0x7Fu, 0xF4u, + 0xFCu, 0xAFu, 0x70u, 0x47u, 0xEFu, 0xF3u, 0x10u, 0x80u, + 0x72u, 0xB6u, 0x70u, 0x47u, 0x80u, 0xF3u, 0x10u, 0x88u, + 0x70u, 0x47u, 0x00u, 0xBFu, 0xAFu, 0xF3u, 0x00u, 0x80u, + 0x01u, 0x20u, 0x10u, 0xB5u, 0x00u, 0xF0u, 0x60u, 0xF9u, + 0x07u, 0x28u, 0x09u, 0xD0u, 0x4Fu, 0xF0u, 0xFFu, 0x34u, + 0x17u, 0xE0u, 0x0Eu, 0x4Bu, 0x18u, 0x78u, 0x00u, 0xF0u, + 0x02u, 0x01u, 0xCAu, 0xB2u, 0x00u, 0x2Au, 0xF5u, 0xD1u, + 0x02u, 0x21u, 0x0Bu, 0x48u, 0x00u, 0xF0u, 0xECu, 0xF8u, + 0x02u, 0x28u, 0xF2u, 0xD1u, 0x07u, 0x4Cu, 0x23u, 0x78u, + 0x03u, 0xF0u, 0x02u, 0x00u, 0xC1u, 0xB2u, 0x19u, 0xB9u, + 0x01u, 0x20u, 0x00u, 0xF0u, 0xAFu, 0xF8u, 0xF5u, 0xE7u, + 0x00u, 0x24u, 0x00u, 0xF0u, 0x7Fu, 0xF9u, 0x20u, 0x46u, + 0x10u, 0xBDu, 0x00u, 0xBFu, 0x22u, 0x47u, 0x00u, 0x40u, + 0x57u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0x00u, 0xF0u, + 0xC1u, 0xF8u, 0x00u, 0xF0u, 0x53u, 0xF9u, 0x58u, 0xB9u, + 0xFFu, 0xF7u, 0xCEu, 0xFFu, 0x48u, 0xB9u, 0x00u, 0xF0u, + 0xB9u, 0xF8u, 0x00u, 0xF0u, 0x4Bu, 0xF9u, 0x18u, 0xB9u, + 0xBDu, 0xE8u, 0x08u, 0x40u, 0xFFu, 0xF7u, 0xC4u, 0xBFu, + 0x04u, 0x20u, 0x08u, 0xBDu, 0x38u, 0xB5u, 0x04u, 0x46u, + 0x00u, 0xF0u, 0xACu, 0xF8u, 0x4Cu, 0xB1u, 0x00u, 0xF0u, + 0x3Du, 0xF9u, 0x05u, 0x46u, 0x38u, 0xB9u, 0x05u, 0x4Bu, + 0x1Cu, 0x60u, 0x00u, 0xF0u, 0x57u, 0xF9u, 0x28u, 0x46u, + 0x38u, 0xBDu, 0x01u, 0x20u, 0x38u, 0xBDu, 0x04u, 0x20u, + 0x38u, 0xBDu, 0x00u, 0xBFu, 0x44u, 0xC1u, 0xFFu, 0x1Fu, + 0xF8u, 0xB5u, 0x05u, 0x46u, 0x0Eu, 0x46u, 0x17u, 0x46u, + 0x1Cu, 0x46u, 0x00u, 0xF0u, 0x27u, 0xF9u, 0xF0u, 0xB9u, + 0x22u, 0x46u, 0x28u, 0x46u, 0x39u, 0x46u, 0x00u, 0xF0u, + 0xB9u, 0xF8u, 0x07u, 0x28u, 0x04u, 0x46u, 0x13u, 0xD1u, + 0x1Du, 0x4Bu, 0x1Au, 0x78u, 0x02u, 0xF0u, 0x02u, 0x00u, + 0xC1u, 0xB2u, 0x19u, 0xB9u, 0x01u, 0x20u, 0x00u, 0xF0u, + 0x61u, 0xF8u, 0xF5u, 0xE7u, 0x1Cu, 0x78u, 0x04u, 0xF0u, + 0x02u, 0x02u, 0xD0u, 0xB2u, 0x10u, 0xB1u, 0x1Bu, 0x78u, + 0x9Bu, 0x08u, 0x06u, 0xD0u, 0x4Fu, 0xF0u, 0xFFu, 0x34u, + 0x00u, 0xF0u, 0x28u, 0xF9u, 0x22u, 0xE0u, 0x04u, 0x24u, + 0x20u, 0xE0u, 0x12u, 0x4Cu, 0x28u, 0x46u, 0x22u, 0x78u, + 0x63u, 0x78u, 0x31u, 0x46u, 0x00u, 0xF0u, 0xBCu, 0xF8u, + 0x07u, 0x28u, 0x04u, 0x46u, 0xF0u, 0xD1u, 0x0Cu, 0x49u, + 0x0Au, 0x78u, 0x02u, 0xF0u, 0x02u, 0x00u, 0xC3u, 0xB2u, + 0x1Bu, 0xB9u, 0x01u, 0x20u, 0x00u, 0xF0u, 0x3Eu, 0xF8u, + 0xF5u, 0xE7u, 0x0Cu, 0x78u, 0x04u, 0xF0u, 0x02u, 0x02u, + 0xD0u, 0xB2u, 0x00u, 0x28u, 0xDEu, 0xD0u, 0x09u, 0x78u, + 0x8Bu, 0x08u, 0x14u, 0xBFu, 0x4Fu, 0xF0u, 0xFFu, 0x34u, + 0x00u, 0x24u, 0xD9u, 0xE7u, 0x20u, 0x46u, 0xF8u, 0xBDu, + 0x22u, 0x47u, 0x00u, 0x40u, 0x57u, 0xC1u, 0xFFu, 0x1Fu, + 0x04u, 0x4Bu, 0x1Au, 0x78u, 0x42u, 0xF0u, 0x10u, 0x00u, + 0x18u, 0x70u, 0x19u, 0x7Cu, 0x41u, 0xF0u, 0x10u, 0x02u, + 0x1Au, 0x74u, 0x70u, 0x47u, 0xACu, 0x43u, 0x00u, 0x40u, + 0x01u, 0xBEu, 0x70u, 0x47u, 0x02u, 0x4Bu, 0x1Au, 0x78u, + 0x42u, 0xF0u, 0x01u, 0x00u, 0x18u, 0x70u, 0x70u, 0x47u, + 0xF6u, 0x46u, 0x00u, 0x40u, 0x10u, 0xB5u, 0x04u, 0x46u, + 0xB4u, 0xF5u, 0x00u, 0x4Fu, 0x06u, 0x4Bu, 0x05u, 0xD9u, + 0x18u, 0x68u, 0xFFu, 0xF7u, 0x29u, 0xFFu, 0xA4u, 0xF5u, + 0x00u, 0x44u, 0xF5u, 0xE7u, 0x58u, 0x68u, 0x60u, 0x43u, + 0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u, 0x20u, 0xBFu, + 0x14u, 0xC1u, 0xFFu, 0x1Fu, 0x02u, 0x4Bu, 0x19u, 0x7Au, + 0x48u, 0x43u, 0xFFu, 0xF7u, 0x19u, 0xBFu, 0x00u, 0xBFu, + 0x14u, 0xC1u, 0xFFu, 0x1Fu, 0x05u, 0x4Bu, 0x00u, 0xF0u, + 0x1Fu, 0x00u, 0x1Bu, 0x68u, 0x00u, 0xF1u, 0x10u, 0x02u, + 0x53u, 0xF8u, 0x22u, 0x00u, 0x43u, 0xF8u, 0x22u, 0x10u, + 0x70u, 0x47u, 0x00u, 0xBFu, 0x08u, 0xEDu, 0x00u, 0xE0u, + 0x00u, 0xF0u, 0x1Fu, 0x00u, 0x00u, 0xF1u, 0x60u, 0x43u, + 0x49u, 0x01u, 0x03u, 0xF5u, 0x64u, 0x42u, 0xC8u, 0xB2u, + 0x10u, 0x70u, 0x70u, 0x47u, 0x08u, 0xB5u, 0xFFu, 0xF7u, + 0x05u, 0xFFu, 0x06u, 0x4Bu, 0x1Au, 0x78u, 0x42u, 0xF0u, + 0x08u, 0x01u, 0x19u, 0x70u, 0x1Au, 0x7Cu, 0x42u, 0xF0u, + 0x08u, 0x01u, 0x19u, 0x74u, 0xBDu, 0xE8u, 0x08u, 0x40u, + 0xFFu, 0xF7u, 0xFCu, 0xBEu, 0xA0u, 0x43u, 0x00u, 0x40u, + 0x70u, 0xB5u, 0x06u, 0x46u, 0x0Du, 0x46u, 0x00u, 0x24u, + 0xE3u, 0xB2u, 0xABu, 0x42u, 0x0Cu, 0xD2u, 0x07u, 0x48u, + 0x01u, 0x78u, 0xCBu, 0x07u, 0x03u, 0xD4u, 0x01u, 0x20u, + 0xFFu, 0xF7u, 0xC0u, 0xFFu, 0xF7u, 0xE7u, 0x04u, 0x4Au, + 0x13u, 0x78u, 0x33u, 0x55u, 0x01u, 0x34u, 0xEFu, 0xE7u, + 0x28u, 0x46u, 0x70u, 0xBDu, 0x22u, 0x47u, 0x00u, 0x40u, + 0x20u, 0x47u, 0x00u, 0x40u, 0x30u, 0xB5u, 0x10u, 0x4Bu, + 0x1Cu, 0x78u, 0x04u, 0xF0u, 0x02u, 0x04u, 0xE4u, 0xB2u, + 0xACu, 0xB1u, 0x0Eu, 0x4Cu, 0xB6u, 0x25u, 0x25u, 0x70u, + 0xD5u, 0x25u, 0x25u, 0x70u, 0x02u, 0x25u, 0x25u, 0x70u, + 0x1Bu, 0x78u, 0x2Bu, 0x40u, 0xDBu, 0xB2u, 0x63u, 0xB9u, + 0x20u, 0x70u, 0x98u, 0xB2u, 0x90u, 0x42u, 0x04u, 0xD2u, + 0xCCu, 0x5Cu, 0x06u, 0x48u, 0x01u, 0x33u, 0x04u, 0x70u, + 0xF7u, 0xE7u, 0x07u, 0x20u, 0x30u, 0xBDu, 0x04u, 0x20u, + 0x30u, 0xBDu, 0x09u, 0x20u, 0x30u, 0xBDu, 0x00u, 0xBFu, + 0x22u, 0x47u, 0x00u, 0x40u, 0x20u, 0x47u, 0x00u, 0x40u, + 0x70u, 0xB5u, 0x0Fu, 0x4Du, 0x2Cu, 0x78u, 0x04u, 0xF0u, + 0x02u, 0x04u, 0xE4u, 0xB2u, 0xA4u, 0xB1u, 0x0Du, 0x4Cu, + 0xB6u, 0x26u, 0x26u, 0x70u, 0xD8u, 0x26u, 0x26u, 0x70u, + 0x05u, 0x26u, 0x26u, 0x70u, 0x2Du, 0x78u, 0x05u, 0xF0u, + 0x02u, 0x05u, 0xEDu, 0xB2u, 0x55u, 0xB9u, 0x20u, 0x70u, + 0x08u, 0x0Au, 0xC9u, 0xB2u, 0x20u, 0x70u, 0x21u, 0x70u, + 0x07u, 0x20u, 0x22u, 0x70u, 0x23u, 0x70u, 0x70u, 0xBDu, + 0x04u, 0x20u, 0x70u, 0xBDu, 0x09u, 0x20u, 0x70u, 0xBDu, + 0x22u, 0x47u, 0x00u, 0x40u, 0x20u, 0x47u, 0x00u, 0x40u, + 0x0Cu, 0x4Au, 0x13u, 0x78u, 0x03u, 0xF0u, 0x02u, 0x01u, + 0xCBu, 0xB2u, 0x73u, 0xB1u, 0x0Au, 0x4Bu, 0xB6u, 0x21u, + 0x19u, 0x70u, 0xE1u, 0x21u, 0x19u, 0x70u, 0x0Eu, 0x21u, + 0x19u, 0x70u, 0x12u, 0x78u, 0x02u, 0xF0u, 0x02u, 0x01u, + 0xCAu, 0xB2u, 0x22u, 0xB9u, 0x18u, 0x70u, 0x07u, 0x20u, + 0x70u, 0x47u, 0x04u, 0x20u, 0x70u, 0x47u, 0x09u, 0x20u, + 0x70u, 0x47u, 0x00u, 0xBFu, 0x22u, 0x47u, 0x00u, 0x40u, + 0x20u, 0x47u, 0x00u, 0x40u, 0x38u, 0xB5u, 0xFFu, 0xF7u, + 0x71u, 0xFEu, 0x0Cu, 0x4Bu, 0x19u, 0x78u, 0x79u, 0xB9u, + 0x01u, 0x25u, 0x0Bu, 0x4Au, 0x1Du, 0x70u, 0x14u, 0x68u, + 0x2Cu, 0x40u, 0x0Au, 0xD0u, 0x14u, 0x68u, 0x24u, 0xF0u, + 0x01u, 0x04u, 0x14u, 0x60u, 0x00u, 0xBFu, 0x00u, 0xBFu, + 0x00u, 0xBFu, 0x5Du, 0x60u, 0x0Cu, 0x46u, 0x00u, 0xE0u, + 0x04u, 0x24u, 0xFFu, 0xF7u, 0x5Fu, 0xFEu, 0x20u, 0x46u, + 0x38u, 0xBDu, 0x00u, 0xBFu, 0x48u, 0xC1u, 0xFFu, 0x1Fu, + 0x04u, 0x00u, 0x08u, 0x40u, 0x10u, 0xB5u, 0xFFu, 0xF7u, + 0x51u, 0xFEu, 0x09u, 0x4Bu, 0x00u, 0x22u, 0x59u, 0x68u, + 0x1Au, 0x70u, 0x01u, 0x29u, 0x08u, 0xD1u, 0x07u, 0x49u, + 0x0Cu, 0x68u, 0x44u, 0xF0u, 0x01u, 0x04u, 0x0Cu, 0x60u, + 0x00u, 0xBFu, 0x00u, 0xBFu, 0x00u, 0xBFu, 0x5Au, 0x60u, + 0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u, 0x42u, 0xBEu, + 0x48u, 0xC1u, 0xFFu, 0x1Fu, 0x04u, 0x00u, 0x08u, 0x40u, + 0x08u, 0xB5u, 0x62u, 0xB6u, 0x00u, 0x20u, 0x02u, 0x21u, + 0x00u, 0xF0u, 0x62u, 0xF9u, 0x01u, 0x4Bu, 0x01u, 0x22u, + 0x1Au, 0x70u, 0x08u, 0xBDu, 0x50u, 0xC1u, 0xFFu, 0x1Fu, + 0x01u, 0x20u, 0x00u, 0xF0u, 0x03u, 0xBAu, 0x00u, 0x00u, + 0xF8u, 0xB5u, 0x07u, 0x46u, 0x0Eu, 0x46u, 0x02u, 0x20u, + 0x15u, 0x46u, 0x39u, 0x46u, 0x40u, 0x22u, 0x1Cu, 0x46u, + 0x00u, 0xF0u, 0xBAu, 0xF9u, 0x0Au, 0x23u, 0x5Cu, 0x43u, + 0x0Du, 0x48u, 0x44u, 0x80u, 0x00u, 0x24u, 0x02u, 0x20u, + 0x00u, 0xF0u, 0x94u, 0xF9u, 0x50u, 0xB9u, 0x0Au, 0x49u, + 0x67u, 0x1Cu, 0x4Au, 0x88u, 0xBFu, 0xB2u, 0xA2u, 0x42u, + 0x04u, 0xD9u, 0x01u, 0x20u, 0xFFu, 0xF7u, 0xD2u, 0xFEu, + 0x3Cu, 0x46u, 0xF0u, 0xE7u, 0x02u, 0x20u, 0x00u, 0xF0u, + 0x85u, 0xF9u, 0x10u, 0xB1u, 0x2Eu, 0x80u, 0x00u, 0x20u, + 0xF8u, 0xBDu, 0x10u, 0x20u, 0xF8u, 0xBDu, 0x00u, 0xBFu, + 0x50u, 0xC1u, 0xFFu, 0x1Fu, 0x2Du, 0xE9u, 0xF0u, 0x41u, + 0x15u, 0x46u, 0x0Au, 0x22u, 0x53u, 0x43u, 0x28u, 0x4Cu, + 0x80u, 0x46u, 0x63u, 0x80u, 0x24u, 0x78u, 0x0Fu, 0x46u, + 0xD4u, 0xB1u, 0x00u, 0x24u, 0x00u, 0xF0u, 0x5Eu, 0xF9u, + 0x58u, 0xB9u, 0x23u, 0x4Bu, 0x66u, 0x1Cu, 0x58u, 0x88u, + 0xB6u, 0xB2u, 0xA0u, 0x42u, 0x04u, 0xD9u, 0x01u, 0x20u, + 0xFFu, 0xF7u, 0xACu, 0xFEu, 0x34u, 0x46u, 0xF1u, 0xE7u, + 0x34u, 0x46u, 0x00u, 0xF0u, 0x4Fu, 0xF9u, 0xE0u, 0xB1u, + 0x00u, 0xF0u, 0x52u, 0xF9u, 0xFFu, 0xF7u, 0xB0u, 0xFFu, + 0x19u, 0x4Au, 0x00u, 0x21u, 0x11u, 0x70u, 0x14u, 0xE0u, + 0x00u, 0xF0u, 0x4Au, 0xF9u, 0x08u, 0xB9u, 0x00u, 0x24u, + 0x0Fu, 0xE0u, 0x00u, 0xF0u, 0x3Fu, 0xF9u, 0x00u, 0x28u, + 0xF9u, 0xD0u, 0xFFu, 0xF7u, 0xA1u, 0xFFu, 0x08u, 0xE0u, + 0x11u, 0x4Bu, 0x66u, 0x1Cu, 0x59u, 0x88u, 0xB6u, 0xB2u, + 0xA1u, 0x42u, 0x09u, 0xD9u, 0xFFu, 0xF7u, 0x8Au, 0xFEu, + 0x34u, 0x46u, 0x01u, 0x20u, 0x00u, 0xF0u, 0x3Eu, 0xF9u, + 0x01u, 0x28u, 0x4Fu, 0xF0u, 0x01u, 0x00u, 0xEFu, 0xD1u, + 0x00u, 0xF0u, 0x38u, 0xF9u, 0x01u, 0x28u, 0x0Au, 0xD1u, + 0x41u, 0x46u, 0x40u, 0x2Fu, 0x34u, 0xBFu, 0x3Au, 0x46u, + 0x40u, 0x22u, 0x00u, 0xF0u, 0x9Fu, 0xF9u, 0x28u, 0x80u, + 0x00u, 0x20u, 0xBDu, 0xE8u, 0xF0u, 0x81u, 0x00u, 0x20u, + 0x28u, 0x80u, 0x10u, 0x20u, 0xBDu, 0xE8u, 0xF0u, 0x81u, + 0x50u, 0xC1u, 0xFFu, 0x1Fu, 0xF8u, 0xB5u, 0xFFu, 0xF7u, + 0xA5u, 0xFDu, 0x38u, 0x4Bu, 0x07u, 0x46u, 0x1Au, 0x78u, + 0x01u, 0x25u, 0x42u, 0xF0u, 0x01u, 0x00u, 0x18u, 0x70u, + 0x19u, 0x7Cu, 0x02u, 0x26u, 0x41u, 0xF0u, 0x01u, 0x04u, + 0x1Cu, 0x74u, 0x33u, 0x4Bu, 0x33u, 0x4Cu, 0x1Du, 0x70u, + 0x03u, 0xF8u, 0x94u, 0x6Cu, 0x13u, 0xF8u, 0x8Du, 0x2Cu, + 0x02u, 0xF0u, 0x7Fu, 0x00u, 0x03u, 0xF8u, 0x8Du, 0x0Cu, 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0x20u, 0x12u, 0x49u, 0x18u, 0x70u, + 0x12u, 0x4Bu, 0x10u, 0x70u, 0x08u, 0x70u, 0x12u, 0x4Au, + 0x12u, 0x49u, 0x18u, 0x70u, 0x12u, 0x4Bu, 0x10u, 0x70u, + 0x08u, 0x70u, 0x80u, 0x22u, 0x03u, 0x20u, 0x18u, 0x70u, + 0x01u, 0x20u, 0x03u, 0xF8u, 0x20u, 0x2Cu, 0xFFu, 0xF7u, + 0xE7u, 0xFCu, 0x0Eu, 0x48u, 0x04u, 0x21u, 0x01u, 0x70u, + 0x10u, 0xBDu, 0x00u, 0xBFu, 0xECu, 0xC1u, 0xFFu, 0x1Fu, + 0x00u, 0xE1u, 0x00u, 0xE0u, 0x72u, 0xC1u, 0xFFu, 0x1Fu, + 0x09u, 0x60u, 0x00u, 0x40u, 0x6Cu, 0xC1u, 0xFFu, 0x1Fu, + 0x71u, 0xC1u, 0xFFu, 0x1Fu, 0x6Du, 0xC1u, 0xFFu, 0x1Fu, + 0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x5Cu, 0xC1u, 0xFFu, 0x1Fu, + 0x6Fu, 0xC1u, 0xFFu, 0x1Fu, 0xE5u, 0xC1u, 0xFFu, 0x1Fu, + 0x28u, 0x60u, 0x00u, 0x40u, 0x12u, 0x60u, 0x00u, 0x40u, + 0x70u, 0xB5u, 0x07u, 0x4Cu, 0x06u, 0x46u, 0x23u, 0x78u, + 0x0Du, 0x46u, 0x1Bu, 0xB9u, 0xFFu, 0xF7u, 0x22u, 0xFFu, + 0x01u, 0x20u, 0x20u, 0x70u, 0x30u, 0x46u, 0x29u, 0x46u, + 0xBDu, 0xE8u, 0x70u, 0x40u, 0xFFu, 0xF7u, 0xA4u, 0xBFu, + 0x54u, 0xC1u, 0xFFu, 0x1Fu, 0x0Cu, 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0x00u, 0x00u, 0xA0u, 0x22u, 0x00u, 0x00u, + 0x32u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x10u, 0x51u, 0x00u, 0x40u, 0x10u, 0x00u, 0xC0u, 0x51u, + 0x00u, 0x40u, 0x10u, 0x00u, 0x00u, 0x00u, 0x01u, 0x40u, + 0x00u, 0x10u, 0x00u, 0x14u, 0x01u, 0x40u, 0x00u, 0x08u, + 0x00u, 0x40u, 0x01u, 0x40u, 0x00u, 0x0Au, 0x00u, 0x4Cu, + 0x01u, 0x40u, 0x00u, 0x02u, 0x00u, 0x50u, 0x01u, 0x40u, + 0x20u, 0x00u, 0x00u, 0x00u, 0x01u, 0x45u, 0x00u, 0x40u, + 0x02u, 0x52u, 0x00u, 0x40u, 0x01u, 0x17u, 0x01u, 0x40u, + 0x01u, 0x19u, 0x01u, 0x40u, 0x03u, 0x40u, 0x01u, 0x40u, + 0x02u, 0x41u, 0x01u, 0x40u, 0x02u, 0x42u, 0x01u, 0x40u, + 0x02u, 0x43u, 0x01u, 0x40u, 0x03u, 0x47u, 0x01u, 0x40u, + 0x03u, 0x48u, 0x01u, 0x40u, 0x02u, 0x4Cu, 0x01u, 0x40u, + 0x01u, 0x51u, 0x01u, 0x40u, 0x7Eu, 0x02u, 0x1Cu, 0x3Eu, + 0x7Cu, 0x40u, 0xEEu, 0x0Au, 0xEEu, 0x0Au, 0x33u, 0x80u, + 0x36u, 0x40u, 0xCCu, 0x30u, 0xA6u, 0x40u, 0xA7u, 0x80u, + 0xA6u, 0x40u, 0xA7u, 0x80u, 0xA6u, 0x40u, 0xA7u, 0x80u, + 0x08u, 0x08u, 0x0Fu, 0x40u, 0xC2u, 0x0Cu, 0xAEu, 0x40u, + 0xAFu, 0x80u, 0xEEu, 0x50u, 0xACu, 0x08u, 0xAFu, 0x40u, + 0x00u, 0x0Au, 0x02u, 0x00u, 0x00u, 0xCEu, 0xCCu, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x30u, + 0x30u, 0x00u, 0x00u, 0x00u, 0xC0u, 0x00u, 0x00u, 0xCCu, + 0xCCu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x3Eu, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x30u, + 0x30u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, + 0x03u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x33u, + 0x33u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x69u, 0x30u, 0x13u, 0x2Eu, 0x00u, 0x14u, 0x01u, 0x01u, + 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x21u, 0x00u, 0x00u, + 0x01u, 0x00u, 0x00u, 0x00u, 0x3Au, 0x22u, 0x00u, 0x00u, + 0x01u, 0x00u, 0x00u, 0x00u, 0x10u, 0x21u, 0x00u, 0x00u, + 0x01u, 0x00u, 0x00u, 0x00u, 0x11u, 0x22u, 0x00u, 0x00u, + 0x02u, 0x00u, 0x00u, 0x00u, 0x32u, 0x21u, 0x00u, 0x00u, + 0x01u, 0x00u, 0x00u, 0x00u, 0x44u, 0x21u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x30u, 0x21u, 0x00u, 0x00u, + 0x03u, 0x00u, 0x00u, 0x00u, 0x01u, 0x03u, 0x40u, 0x00u, + 0x03u, 0x00u, 0x00u, 0x00u, 0x82u, 0x03u, 0x40u, 0x00u, + 0x03u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, + 0x4Cu, 0x21u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x80u, 0x21u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x74u, 0x21u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, + 0x8Cu, 0x21u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, + 0x23u, 0x22u, 0x00u, 0x00u, 0x41u, 0x00u, 0x00u, 0x00u, + 0x33u, 0xC2u, 0xFFu, 0x1Fu, 0x74u, 0xC2u, 0xFFu, 0x1Fu, + 0x41u, 0x00u, 0x00u, 0x00u, 0xF2u, 0xC1u, 0xFFu, 0x1Fu, + 0xEEu, 0xC1u, 0xFFu, 0x1Fu, 0x24u, 0x00u, 0x05u, 0x01u, + 0x09u, 0x00u, 0xA1u, 0x00u, 0x09u, 0x00u, 0xA1u, 0x00u, + 0x09u, 0x00u, 0x15u, 0x00u, 0x25u, 0xFFu, 0x75u, 0x08u, + 0x95u, 0x40u, 0x91u, 0x02u, 0x09u, 0x00u, 0x15u, 0x00u, + 0x25u, 0xFFu, 0x75u, 0x08u, 0x95u, 0x40u, 0x81u, 0x02u, + 0xC0u, 0xC0u, 0x00u, 0x00u, 0x0Au, 0x03u, 0x30u, 0x00u, + 0x30u, 0x00u, 0x30u, 0x00u, 0x31u, 0x00u, 0x04u, 0x03u, + 0x09u, 0x04u, 0x2Cu, 0x03u, 0x43u, 0x00u, 0x79u, 0x00u, + 0x70u, 0x00u, 0x72u, 0x00u, 0x65u, 0x00u, 0x73u, 0x00u, + 0x73u, 0x00u, 0x20u, 0x00u, 0x53u, 0x00u, 0x65u, 0x00u, + 0x6Du, 0x00u, 0x69u, 0x00u, 0x63u, 0x00u, 0x6Fu, 0x00u, + 0x6Eu, 0x00u, 0x64u, 0x00u, 0x75u, 0x00u, 0x63u, 0x00u, + 0x74u, 0x00u, 0x6Fu, 0x00u, 0x72u, 0x00u, 0x22u, 0x03u, + 0x50u, 0x00u, 0x53u, 0x00u, 0x6Fu, 0x00u, 0x43u, 0x00u, + 0x33u, 0x00u, 0x20u, 0x00u, 0x42u, 0x00u, 0x6Fu, 0x00u, + 0x6Fu, 0x00u, 0x74u, 0x00u, 0x6Cu, 0x00u, 0x6Fu, 0x00u, + 0x61u, 0x00u, 0x64u, 0x00u, 0x65u, 0x00u, 0x72u, 0x00u, + 0x00u, 0x09u, 0x02u, 0x29u, 0x00u, 0x01u, 0x01u, 0x00u, + 0x80u, 0x00u, 0x09u, 0x04u, 0x00u, 0x00u, 0x02u, 0x03u, + 0x00u, 0x00u, 0x02u, 0x09u, 0x21u, 0x11u, 0x01u, 0x00u, + 0x01u, 0x22u, 0x24u, 0x00u, 0x07u, 0x05u, 0x01u, 0x03u, + 0x40u, 0x00u, 0x01u, 0x07u, 0x05u, 0x82u, 0x03u, 0x40u, + 0x00u, 0x01u, 0x12u, 0x01u, 0x00u, 0x02u, 0x00u, 0x00u, + 0x00u, 0x08u, 0xB4u, 0x04u, 0x1Du, 0xB7u, 0x02u, 0x30u, + 0x01u, 0x02u, 0x80u, 0x01u, 0xF8u, 0xB5u, 0x00u, 0xBFu, + 0xF8u, 0xBCu, 0x08u, 0xBCu, 0x9Eu, 0x46u, 0x70u, 0x47u, + 0x51u, 0x00u, 0x00u, 0x00u, 0xB1u, 0x01u, 0x00u, 0x00u, + 0xF8u, 0xB5u, 0x00u, 0xBFu, 0xF8u, 0xBCu, 0x08u, 0xBCu, + 0x9Eu, 0x46u, 0x70u, 0x47u, 0x2Du, 0x00u, 0x00u, 0x00u, + 0x80u, 0x22u, 0x00u, 0x00u, 0x08u, 0xC1u, 0xFFu, 0x1Fu, + 0x20u, 0x00u, 0x00u, 0x00u, 0x50u, 0x01u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x20u, 0x00u, 0x00u, + 0x20u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x7Du, + 0x00u, 0xFAu, 0x00u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x90u, 0xD0u, 0x03u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +__attribute__ ((__section__(".cymeta"), used)) +#elif defined(__ICCARM__) +#pragma location=".cymeta" +#else +#error "Unsupported toolchain" +#endif +const uint8 cy_metadata[] = { + 0x00u, 0x01u, 0x2Eu, 0x13u, 0x30u, 0x69u, 0x00u, 0x01u, + 0x2Eu, 0x1Fu, 0x9Au, 0x6Bu}; + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +__attribute__ ((__section__(".cycustnvl"), used)) +#elif defined(__ICCARM__) +#pragma location=".cycustnvl" +#else +#error "Unsupported toolchain" +#endif +const uint8 cy_meta_custnvl[] = { + 0x80u, 0x00u, 0x40u, 0x05u}; + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +__attribute__ ((__section__(".cywolatch"), used)) +#elif defined(__ICCARM__) +#pragma location=".cywolatch" +#else +#error "Unsupported toolchain" +#endif +const uint8 cy_meta_wonvl[] = { + 0xBCu, 0x90u, 0xACu, 0xAFu}; + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +__attribute__ ((__section__(".cyflashprotect"), used)) +#elif defined(__ICCARM__) +#pragma location=".cyflashprotect" +#else +#error "Unsupported toolchain" +#endif +const uint8 cy_meta_flashprotect[] = { + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cybootloader.icf b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cybootloader.icf new file mode 100755 index 00000000..a1d4bde7 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cybootloader.icf @@ -0,0 +1,3 @@ +/* GENERATED CODE -- CHANGES WILL BE OVERWRITTEN */ + +define symbol CYDEV_BTLDR_SIZE = 0x00002300; diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydevice.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydevice.h new file mode 100755 index 00000000..2514d9aa --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydevice.h @@ -0,0 +1,5360 @@ +/******************************************************************************* +* FILENAME: cydevice.h +* OBSOLETE: Do not use this file. Use the _trm version instead. +* PSoC Creator 3.0 Component Pack 7 +* +* DESCRIPTION: +* This file provides all of the address values for the entire PSoC device. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#if !defined(CYDEVICE_H) +#define CYDEVICE_H +#define CYDEV_FLASH_BASE 0x00000000u +#define CYDEV_FLASH_SIZE 0x00020000u +#define CYDEV_FLASH_DATA_MBASE 0x00000000u +#define CYDEV_FLASH_DATA_MSIZE 0x00020000u +#define CYDEV_SRAM_BASE 0x1fffc000u +#define CYDEV_SRAM_SIZE 0x00008000u +#define CYDEV_SRAM_CODE64K_MBASE 0x1fff8000u +#define CYDEV_SRAM_CODE64K_MSIZE 0x00004000u +#define CYDEV_SRAM_CODE32K_MBASE 0x1fffc000u +#define CYDEV_SRAM_CODE32K_MSIZE 0x00002000u +#define CYDEV_SRAM_CODE16K_MBASE 0x1fffe000u +#define CYDEV_SRAM_CODE16K_MSIZE 0x00001000u +#define CYDEV_SRAM_CODE_MBASE 0x1fffc000u +#define CYDEV_SRAM_CODE_MSIZE 0x00004000u +#define CYDEV_SRAM_DATA_MBASE 0x20000000u +#define CYDEV_SRAM_DATA_MSIZE 0x00004000u +#define CYDEV_SRAM_DATA16K_MBASE 0x20001000u +#define CYDEV_SRAM_DATA16K_MSIZE 0x00001000u +#define CYDEV_SRAM_DATA32K_MBASE 0x20002000u +#define CYDEV_SRAM_DATA32K_MSIZE 0x00002000u +#define CYDEV_SRAM_DATA64K_MBASE 0x20004000u +#define CYDEV_SRAM_DATA64K_MSIZE 0x00004000u +#define CYDEV_DMA_BASE 0x20008000u +#define CYDEV_DMA_SIZE 0x00008000u +#define CYDEV_DMA_SRAM64K_MBASE 0x20008000u +#define CYDEV_DMA_SRAM64K_MSIZE 0x00004000u +#define CYDEV_DMA_SRAM32K_MBASE 0x2000c000u +#define CYDEV_DMA_SRAM32K_MSIZE 0x00002000u +#define CYDEV_DMA_SRAM16K_MBASE 0x2000e000u +#define CYDEV_DMA_SRAM16K_MSIZE 0x00001000u +#define CYDEV_DMA_SRAM_MBASE 0x2000f000u +#define CYDEV_DMA_SRAM_MSIZE 0x00001000u +#define CYDEV_CLKDIST_BASE 0x40004000u +#define CYDEV_CLKDIST_SIZE 0x00000110u +#define CYDEV_CLKDIST_CR 0x40004000u +#define CYDEV_CLKDIST_LD 0x40004001u +#define CYDEV_CLKDIST_WRK0 0x40004002u +#define CYDEV_CLKDIST_WRK1 0x40004003u +#define CYDEV_CLKDIST_MSTR0 0x40004004u +#define CYDEV_CLKDIST_MSTR1 0x40004005u +#define CYDEV_CLKDIST_BCFG0 0x40004006u +#define CYDEV_CLKDIST_BCFG1 0x40004007u +#define CYDEV_CLKDIST_BCFG2 0x40004008u +#define CYDEV_CLKDIST_UCFG 0x40004009u +#define CYDEV_CLKDIST_DLY0 0x4000400au +#define CYDEV_CLKDIST_DLY1 0x4000400bu +#define CYDEV_CLKDIST_DMASK 0x40004010u +#define CYDEV_CLKDIST_AMASK 0x40004014u +#define CYDEV_CLKDIST_DCFG0_BASE 0x40004080u +#define CYDEV_CLKDIST_DCFG0_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG0_CFG0 0x40004080u +#define CYDEV_CLKDIST_DCFG0_CFG1 0x40004081u +#define CYDEV_CLKDIST_DCFG0_CFG2 0x40004082u +#define CYDEV_CLKDIST_DCFG1_BASE 0x40004084u +#define CYDEV_CLKDIST_DCFG1_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG1_CFG0 0x40004084u +#define CYDEV_CLKDIST_DCFG1_CFG1 0x40004085u +#define CYDEV_CLKDIST_DCFG1_CFG2 0x40004086u +#define CYDEV_CLKDIST_DCFG2_BASE 0x40004088u +#define CYDEV_CLKDIST_DCFG2_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG2_CFG0 0x40004088u +#define CYDEV_CLKDIST_DCFG2_CFG1 0x40004089u +#define CYDEV_CLKDIST_DCFG2_CFG2 0x4000408au +#define CYDEV_CLKDIST_DCFG3_BASE 0x4000408cu +#define CYDEV_CLKDIST_DCFG3_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG3_CFG0 0x4000408cu +#define CYDEV_CLKDIST_DCFG3_CFG1 0x4000408du +#define CYDEV_CLKDIST_DCFG3_CFG2 0x4000408eu +#define CYDEV_CLKDIST_DCFG4_BASE 0x40004090u +#define CYDEV_CLKDIST_DCFG4_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG4_CFG0 0x40004090u +#define CYDEV_CLKDIST_DCFG4_CFG1 0x40004091u +#define CYDEV_CLKDIST_DCFG4_CFG2 0x40004092u +#define CYDEV_CLKDIST_DCFG5_BASE 0x40004094u +#define CYDEV_CLKDIST_DCFG5_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG5_CFG0 0x40004094u +#define CYDEV_CLKDIST_DCFG5_CFG1 0x40004095u +#define CYDEV_CLKDIST_DCFG5_CFG2 0x40004096u +#define CYDEV_CLKDIST_DCFG6_BASE 0x40004098u +#define CYDEV_CLKDIST_DCFG6_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG6_CFG0 0x40004098u +#define CYDEV_CLKDIST_DCFG6_CFG1 0x40004099u +#define CYDEV_CLKDIST_DCFG6_CFG2 0x4000409au +#define CYDEV_CLKDIST_DCFG7_BASE 0x4000409cu +#define CYDEV_CLKDIST_DCFG7_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG7_CFG0 0x4000409cu +#define CYDEV_CLKDIST_DCFG7_CFG1 0x4000409du +#define CYDEV_CLKDIST_DCFG7_CFG2 0x4000409eu +#define CYDEV_CLKDIST_ACFG0_BASE 0x40004100u +#define CYDEV_CLKDIST_ACFG0_SIZE 0x00000004u +#define CYDEV_CLKDIST_ACFG0_CFG0 0x40004100u +#define CYDEV_CLKDIST_ACFG0_CFG1 0x40004101u +#define CYDEV_CLKDIST_ACFG0_CFG2 0x40004102u +#define CYDEV_CLKDIST_ACFG0_CFG3 0x40004103u +#define CYDEV_CLKDIST_ACFG1_BASE 0x40004104u +#define CYDEV_CLKDIST_ACFG1_SIZE 0x00000004u +#define CYDEV_CLKDIST_ACFG1_CFG0 0x40004104u +#define CYDEV_CLKDIST_ACFG1_CFG1 0x40004105u +#define CYDEV_CLKDIST_ACFG1_CFG2 0x40004106u +#define CYDEV_CLKDIST_ACFG1_CFG3 0x40004107u +#define CYDEV_CLKDIST_ACFG2_BASE 0x40004108u +#define CYDEV_CLKDIST_ACFG2_SIZE 0x00000004u +#define CYDEV_CLKDIST_ACFG2_CFG0 0x40004108u +#define CYDEV_CLKDIST_ACFG2_CFG1 0x40004109u +#define CYDEV_CLKDIST_ACFG2_CFG2 0x4000410au +#define CYDEV_CLKDIST_ACFG2_CFG3 0x4000410bu +#define CYDEV_CLKDIST_ACFG3_BASE 0x4000410cu +#define CYDEV_CLKDIST_ACFG3_SIZE 0x00000004u +#define CYDEV_CLKDIST_ACFG3_CFG0 0x4000410cu +#define CYDEV_CLKDIST_ACFG3_CFG1 0x4000410du +#define CYDEV_CLKDIST_ACFG3_CFG2 0x4000410eu +#define CYDEV_CLKDIST_ACFG3_CFG3 0x4000410fu +#define CYDEV_FASTCLK_BASE 0x40004200u +#define CYDEV_FASTCLK_SIZE 0x00000026u +#define CYDEV_FASTCLK_IMO_BASE 0x40004200u +#define CYDEV_FASTCLK_IMO_SIZE 0x00000001u +#define CYDEV_FASTCLK_IMO_CR 0x40004200u +#define CYDEV_FASTCLK_XMHZ_BASE 0x40004210u +#define CYDEV_FASTCLK_XMHZ_SIZE 0x00000004u +#define CYDEV_FASTCLK_XMHZ_CSR 0x40004210u +#define CYDEV_FASTCLK_XMHZ_CFG0 0x40004212u +#define CYDEV_FASTCLK_XMHZ_CFG1 0x40004213u +#define CYDEV_FASTCLK_PLL_BASE 0x40004220u +#define CYDEV_FASTCLK_PLL_SIZE 0x00000006u +#define CYDEV_FASTCLK_PLL_CFG0 0x40004220u +#define CYDEV_FASTCLK_PLL_CFG1 0x40004221u +#define CYDEV_FASTCLK_PLL_P 0x40004222u +#define CYDEV_FASTCLK_PLL_Q 0x40004223u +#define CYDEV_FASTCLK_PLL_SR 0x40004225u +#define CYDEV_SLOWCLK_BASE 0x40004300u +#define CYDEV_SLOWCLK_SIZE 0x0000000bu +#define CYDEV_SLOWCLK_ILO_BASE 0x40004300u +#define CYDEV_SLOWCLK_ILO_SIZE 0x00000002u +#define CYDEV_SLOWCLK_ILO_CR0 0x40004300u +#define CYDEV_SLOWCLK_ILO_CR1 0x40004301u +#define CYDEV_SLOWCLK_X32_BASE 0x40004308u +#define CYDEV_SLOWCLK_X32_SIZE 0x00000003u +#define CYDEV_SLOWCLK_X32_CR 0x40004308u +#define CYDEV_SLOWCLK_X32_CFG 0x40004309u +#define CYDEV_SLOWCLK_X32_TST 0x4000430au +#define CYDEV_BOOST_BASE 0x40004320u +#define CYDEV_BOOST_SIZE 0x00000007u +#define CYDEV_BOOST_CR0 0x40004320u +#define CYDEV_BOOST_CR1 0x40004321u +#define CYDEV_BOOST_CR2 0x40004322u +#define CYDEV_BOOST_CR3 0x40004323u +#define CYDEV_BOOST_SR 0x40004324u +#define CYDEV_BOOST_CR4 0x40004325u +#define CYDEV_BOOST_SR2 0x40004326u +#define CYDEV_PWRSYS_BASE 0x40004330u +#define CYDEV_PWRSYS_SIZE 0x00000002u +#define CYDEV_PWRSYS_CR0 0x40004330u +#define CYDEV_PWRSYS_CR1 0x40004331u +#define CYDEV_PM_BASE 0x40004380u +#define CYDEV_PM_SIZE 0x00000057u +#define CYDEV_PM_TW_CFG0 0x40004380u +#define CYDEV_PM_TW_CFG1 0x40004381u +#define CYDEV_PM_TW_CFG2 0x40004382u +#define CYDEV_PM_WDT_CFG 0x40004383u +#define CYDEV_PM_WDT_CR 0x40004384u +#define CYDEV_PM_INT_SR 0x40004390u +#define CYDEV_PM_MODE_CFG0 0x40004391u +#define CYDEV_PM_MODE_CFG1 0x40004392u +#define CYDEV_PM_MODE_CSR 0x40004393u +#define CYDEV_PM_USB_CR0 0x40004394u +#define CYDEV_PM_WAKEUP_CFG0 0x40004398u +#define CYDEV_PM_WAKEUP_CFG1 0x40004399u +#define CYDEV_PM_WAKEUP_CFG2 0x4000439au +#define CYDEV_PM_ACT_BASE 0x400043a0u +#define CYDEV_PM_ACT_SIZE 0x0000000eu +#define CYDEV_PM_ACT_CFG0 0x400043a0u +#define CYDEV_PM_ACT_CFG1 0x400043a1u +#define CYDEV_PM_ACT_CFG2 0x400043a2u +#define CYDEV_PM_ACT_CFG3 0x400043a3u +#define CYDEV_PM_ACT_CFG4 0x400043a4u +#define CYDEV_PM_ACT_CFG5 0x400043a5u +#define CYDEV_PM_ACT_CFG6 0x400043a6u +#define CYDEV_PM_ACT_CFG7 0x400043a7u +#define CYDEV_PM_ACT_CFG8 0x400043a8u +#define CYDEV_PM_ACT_CFG9 0x400043a9u +#define CYDEV_PM_ACT_CFG10 0x400043aau +#define CYDEV_PM_ACT_CFG11 0x400043abu +#define CYDEV_PM_ACT_CFG12 0x400043acu +#define CYDEV_PM_ACT_CFG13 0x400043adu +#define CYDEV_PM_STBY_BASE 0x400043b0u +#define CYDEV_PM_STBY_SIZE 0x0000000eu +#define CYDEV_PM_STBY_CFG0 0x400043b0u +#define CYDEV_PM_STBY_CFG1 0x400043b1u +#define CYDEV_PM_STBY_CFG2 0x400043b2u +#define CYDEV_PM_STBY_CFG3 0x400043b3u +#define CYDEV_PM_STBY_CFG4 0x400043b4u +#define CYDEV_PM_STBY_CFG5 0x400043b5u +#define CYDEV_PM_STBY_CFG6 0x400043b6u +#define CYDEV_PM_STBY_CFG7 0x400043b7u +#define CYDEV_PM_STBY_CFG8 0x400043b8u +#define CYDEV_PM_STBY_CFG9 0x400043b9u +#define CYDEV_PM_STBY_CFG10 0x400043bau +#define CYDEV_PM_STBY_CFG11 0x400043bbu +#define CYDEV_PM_STBY_CFG12 0x400043bcu +#define CYDEV_PM_STBY_CFG13 0x400043bdu +#define CYDEV_PM_AVAIL_BASE 0x400043c0u +#define CYDEV_PM_AVAIL_SIZE 0x00000017u +#define CYDEV_PM_AVAIL_CR0 0x400043c0u +#define CYDEV_PM_AVAIL_CR1 0x400043c1u +#define CYDEV_PM_AVAIL_CR2 0x400043c2u +#define CYDEV_PM_AVAIL_CR3 0x400043c3u +#define CYDEV_PM_AVAIL_CR4 0x400043c4u +#define CYDEV_PM_AVAIL_CR5 0x400043c5u +#define CYDEV_PM_AVAIL_CR6 0x400043c6u +#define CYDEV_PM_AVAIL_SR0 0x400043d0u +#define CYDEV_PM_AVAIL_SR1 0x400043d1u +#define CYDEV_PM_AVAIL_SR2 0x400043d2u +#define CYDEV_PM_AVAIL_SR3 0x400043d3u +#define CYDEV_PM_AVAIL_SR4 0x400043d4u +#define CYDEV_PM_AVAIL_SR5 0x400043d5u +#define CYDEV_PM_AVAIL_SR6 0x400043d6u +#define CYDEV_PICU_BASE 0x40004500u +#define CYDEV_PICU_SIZE 0x000000b0u +#define CYDEV_PICU_INTTYPE_BASE 0x40004500u +#define CYDEV_PICU_INTTYPE_SIZE 0x00000080u +#define CYDEV_PICU_INTTYPE_PICU0_BASE 0x40004500u +#define CYDEV_PICU_INTTYPE_PICU0_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE0 0x40004500u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE1 0x40004501u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE2 0x40004502u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE3 0x40004503u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE4 0x40004504u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE5 0x40004505u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE6 0x40004506u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE7 0x40004507u +#define CYDEV_PICU_INTTYPE_PICU1_BASE 0x40004508u +#define CYDEV_PICU_INTTYPE_PICU1_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE0 0x40004508u +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE1 0x40004509u +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE2 0x4000450au +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE3 0x4000450bu +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE4 0x4000450cu +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE5 0x4000450du +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE6 0x4000450eu +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE7 0x4000450fu +#define CYDEV_PICU_INTTYPE_PICU2_BASE 0x40004510u +#define CYDEV_PICU_INTTYPE_PICU2_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE0 0x40004510u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE1 0x40004511u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE2 0x40004512u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE3 0x40004513u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE4 0x40004514u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE5 0x40004515u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE6 0x40004516u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE7 0x40004517u +#define CYDEV_PICU_INTTYPE_PICU3_BASE 0x40004518u +#define CYDEV_PICU_INTTYPE_PICU3_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE0 0x40004518u +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE1 0x40004519u +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE2 0x4000451au +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE3 0x4000451bu +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE4 0x4000451cu +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE5 0x4000451du +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE6 0x4000451eu +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE7 0x4000451fu +#define CYDEV_PICU_INTTYPE_PICU4_BASE 0x40004520u +#define CYDEV_PICU_INTTYPE_PICU4_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE0 0x40004520u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE1 0x40004521u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE2 0x40004522u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE3 0x40004523u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE4 0x40004524u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE5 0x40004525u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE6 0x40004526u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE7 0x40004527u +#define CYDEV_PICU_INTTYPE_PICU5_BASE 0x40004528u +#define CYDEV_PICU_INTTYPE_PICU5_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE0 0x40004528u +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE1 0x40004529u +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE2 0x4000452au +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE3 0x4000452bu +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE4 0x4000452cu +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE5 0x4000452du +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE6 0x4000452eu +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE7 0x4000452fu +#define CYDEV_PICU_INTTYPE_PICU6_BASE 0x40004530u +#define CYDEV_PICU_INTTYPE_PICU6_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE0 0x40004530u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE1 0x40004531u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE2 0x40004532u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE3 0x40004533u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE4 0x40004534u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE5 0x40004535u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE6 0x40004536u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE7 0x40004537u +#define CYDEV_PICU_INTTYPE_PICU12_BASE 0x40004560u +#define CYDEV_PICU_INTTYPE_PICU12_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE0 0x40004560u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE1 0x40004561u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE2 0x40004562u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE3 0x40004563u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE4 0x40004564u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE5 0x40004565u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE6 0x40004566u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE7 0x40004567u +#define CYDEV_PICU_INTTYPE_PICU15_BASE 0x40004578u +#define CYDEV_PICU_INTTYPE_PICU15_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE0 0x40004578u +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE1 0x40004579u +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE2 0x4000457au +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE3 0x4000457bu +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE4 0x4000457cu +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE5 0x4000457du +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE6 0x4000457eu +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE7 0x4000457fu +#define CYDEV_PICU_STAT_BASE 0x40004580u +#define CYDEV_PICU_STAT_SIZE 0x00000010u +#define CYDEV_PICU_STAT_PICU0_BASE 0x40004580u +#define CYDEV_PICU_STAT_PICU0_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU0_INTSTAT 0x40004580u +#define CYDEV_PICU_STAT_PICU1_BASE 0x40004581u +#define CYDEV_PICU_STAT_PICU1_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU1_INTSTAT 0x40004581u +#define CYDEV_PICU_STAT_PICU2_BASE 0x40004582u +#define CYDEV_PICU_STAT_PICU2_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU2_INTSTAT 0x40004582u +#define CYDEV_PICU_STAT_PICU3_BASE 0x40004583u +#define CYDEV_PICU_STAT_PICU3_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU3_INTSTAT 0x40004583u +#define CYDEV_PICU_STAT_PICU4_BASE 0x40004584u +#define CYDEV_PICU_STAT_PICU4_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU4_INTSTAT 0x40004584u +#define CYDEV_PICU_STAT_PICU5_BASE 0x40004585u +#define CYDEV_PICU_STAT_PICU5_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU5_INTSTAT 0x40004585u +#define CYDEV_PICU_STAT_PICU6_BASE 0x40004586u +#define CYDEV_PICU_STAT_PICU6_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU6_INTSTAT 0x40004586u +#define CYDEV_PICU_STAT_PICU12_BASE 0x4000458cu +#define CYDEV_PICU_STAT_PICU12_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU12_INTSTAT 0x4000458cu +#define CYDEV_PICU_STAT_PICU15_BASE 0x4000458fu +#define CYDEV_PICU_STAT_PICU15_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU15_INTSTAT 0x4000458fu +#define CYDEV_PICU_SNAP_BASE 0x40004590u +#define CYDEV_PICU_SNAP_SIZE 0x00000010u +#define CYDEV_PICU_SNAP_PICU0_BASE 0x40004590u +#define CYDEV_PICU_SNAP_PICU0_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU0_SNAP 0x40004590u +#define CYDEV_PICU_SNAP_PICU1_BASE 0x40004591u +#define CYDEV_PICU_SNAP_PICU1_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU1_SNAP 0x40004591u +#define CYDEV_PICU_SNAP_PICU2_BASE 0x40004592u +#define CYDEV_PICU_SNAP_PICU2_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU2_SNAP 0x40004592u +#define CYDEV_PICU_SNAP_PICU3_BASE 0x40004593u +#define CYDEV_PICU_SNAP_PICU3_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU3_SNAP 0x40004593u +#define CYDEV_PICU_SNAP_PICU4_BASE 0x40004594u +#define CYDEV_PICU_SNAP_PICU4_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU4_SNAP 0x40004594u +#define CYDEV_PICU_SNAP_PICU5_BASE 0x40004595u +#define CYDEV_PICU_SNAP_PICU5_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU5_SNAP 0x40004595u +#define CYDEV_PICU_SNAP_PICU6_BASE 0x40004596u +#define CYDEV_PICU_SNAP_PICU6_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU6_SNAP 0x40004596u +#define CYDEV_PICU_SNAP_PICU12_BASE 0x4000459cu +#define CYDEV_PICU_SNAP_PICU12_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU12_SNAP 0x4000459cu +#define CYDEV_PICU_SNAP_PICU_15_BASE 0x4000459fu +#define CYDEV_PICU_SNAP_PICU_15_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU_15_SNAP_15 0x4000459fu +#define CYDEV_PICU_DISABLE_COR_BASE 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_SIZE 0x00000010u +#define CYDEV_PICU_DISABLE_COR_PICU0_BASE 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_PICU0_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_PICU1_BASE 0x400045a1u +#define CYDEV_PICU_DISABLE_COR_PICU1_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR 0x400045a1u +#define CYDEV_PICU_DISABLE_COR_PICU2_BASE 0x400045a2u +#define CYDEV_PICU_DISABLE_COR_PICU2_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR 0x400045a2u +#define CYDEV_PICU_DISABLE_COR_PICU3_BASE 0x400045a3u +#define CYDEV_PICU_DISABLE_COR_PICU3_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR 0x400045a3u +#define CYDEV_PICU_DISABLE_COR_PICU4_BASE 0x400045a4u +#define CYDEV_PICU_DISABLE_COR_PICU4_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR 0x400045a4u +#define CYDEV_PICU_DISABLE_COR_PICU5_BASE 0x400045a5u +#define CYDEV_PICU_DISABLE_COR_PICU5_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR 0x400045a5u +#define CYDEV_PICU_DISABLE_COR_PICU6_BASE 0x400045a6u +#define CYDEV_PICU_DISABLE_COR_PICU6_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR 0x400045a6u +#define CYDEV_PICU_DISABLE_COR_PICU12_BASE 0x400045acu +#define CYDEV_PICU_DISABLE_COR_PICU12_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR 0x400045acu +#define CYDEV_PICU_DISABLE_COR_PICU15_BASE 0x400045afu +#define CYDEV_PICU_DISABLE_COR_PICU15_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR 0x400045afu +#define CYDEV_MFGCFG_BASE 0x40004600u +#define CYDEV_MFGCFG_SIZE 0x000000edu +#define CYDEV_MFGCFG_ANAIF_BASE 0x40004600u +#define CYDEV_MFGCFG_ANAIF_SIZE 0x00000038u +#define CYDEV_MFGCFG_ANAIF_DAC0_BASE 0x40004608u +#define CYDEV_MFGCFG_ANAIF_DAC0_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_DAC0_TR 0x40004608u +#define CYDEV_MFGCFG_ANAIF_DAC1_BASE 0x40004609u +#define CYDEV_MFGCFG_ANAIF_DAC1_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_DAC1_TR 0x40004609u +#define CYDEV_MFGCFG_ANAIF_DAC2_BASE 0x4000460au +#define CYDEV_MFGCFG_ANAIF_DAC2_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_DAC2_TR 0x4000460au +#define CYDEV_MFGCFG_ANAIF_DAC3_BASE 0x4000460bu +#define CYDEV_MFGCFG_ANAIF_DAC3_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_DAC3_TR 0x4000460bu +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE 0x40004610u +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0 0x40004610u +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE 0x40004611u +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0 0x40004611u +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE 0x40004612u +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0 0x40004612u +#define CYDEV_MFGCFG_ANAIF_SAR0_BASE 0x40004614u +#define CYDEV_MFGCFG_ANAIF_SAR0_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_SAR0_TR0 0x40004614u +#define CYDEV_MFGCFG_ANAIF_SAR1_BASE 0x40004616u +#define CYDEV_MFGCFG_ANAIF_SAR1_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_SAR1_TR0 0x40004616u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_BASE 0x40004620u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_TR0 0x40004620u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_TR1 0x40004621u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_BASE 0x40004622u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_TR0 0x40004622u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_TR1 0x40004623u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_BASE 0x40004624u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_TR0 0x40004624u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_TR1 0x40004625u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_BASE 0x40004626u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_TR0 0x40004626u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_TR1 0x40004627u +#define CYDEV_MFGCFG_ANAIF_CMP0_BASE 0x40004630u +#define CYDEV_MFGCFG_ANAIF_CMP0_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_CMP0_TR0 0x40004630u +#define CYDEV_MFGCFG_ANAIF_CMP0_TR1 0x40004631u +#define CYDEV_MFGCFG_ANAIF_CMP1_BASE 0x40004632u +#define CYDEV_MFGCFG_ANAIF_CMP1_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_CMP1_TR0 0x40004632u +#define CYDEV_MFGCFG_ANAIF_CMP1_TR1 0x40004633u +#define CYDEV_MFGCFG_ANAIF_CMP2_BASE 0x40004634u +#define CYDEV_MFGCFG_ANAIF_CMP2_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_CMP2_TR0 0x40004634u +#define CYDEV_MFGCFG_ANAIF_CMP2_TR1 0x40004635u +#define CYDEV_MFGCFG_ANAIF_CMP3_BASE 0x40004636u +#define CYDEV_MFGCFG_ANAIF_CMP3_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_CMP3_TR0 0x40004636u +#define CYDEV_MFGCFG_ANAIF_CMP3_TR1 0x40004637u +#define CYDEV_MFGCFG_PWRSYS_BASE 0x40004680u +#define CYDEV_MFGCFG_PWRSYS_SIZE 0x0000000bu +#define CYDEV_MFGCFG_PWRSYS_HIB_TR0 0x40004680u +#define CYDEV_MFGCFG_PWRSYS_HIB_TR1 0x40004681u +#define CYDEV_MFGCFG_PWRSYS_I2C_TR 0x40004682u +#define CYDEV_MFGCFG_PWRSYS_SLP_TR 0x40004683u +#define CYDEV_MFGCFG_PWRSYS_BUZZ_TR 0x40004684u +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR0 0x40004685u +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR1 0x40004686u +#define CYDEV_MFGCFG_PWRSYS_BREF_TR 0x40004687u +#define CYDEV_MFGCFG_PWRSYS_BG_TR 0x40004688u +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR2 0x40004689u +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR3 0x4000468au +#define CYDEV_MFGCFG_ILO_BASE 0x40004690u +#define CYDEV_MFGCFG_ILO_SIZE 0x00000002u +#define CYDEV_MFGCFG_ILO_TR0 0x40004690u +#define CYDEV_MFGCFG_ILO_TR1 0x40004691u +#define CYDEV_MFGCFG_X32_BASE 0x40004698u +#define CYDEV_MFGCFG_X32_SIZE 0x00000001u +#define CYDEV_MFGCFG_X32_TR 0x40004698u +#define CYDEV_MFGCFG_IMO_BASE 0x400046a0u +#define CYDEV_MFGCFG_IMO_SIZE 0x00000005u +#define CYDEV_MFGCFG_IMO_TR0 0x400046a0u +#define CYDEV_MFGCFG_IMO_TR1 0x400046a1u +#define CYDEV_MFGCFG_IMO_GAIN 0x400046a2u +#define CYDEV_MFGCFG_IMO_C36M 0x400046a3u +#define CYDEV_MFGCFG_IMO_TR2 0x400046a4u +#define CYDEV_MFGCFG_XMHZ_BASE 0x400046a8u +#define CYDEV_MFGCFG_XMHZ_SIZE 0x00000001u +#define CYDEV_MFGCFG_XMHZ_TR 0x400046a8u +#define CYDEV_MFGCFG_DLY 0x400046c0u +#define CYDEV_MFGCFG_MLOGIC_BASE 0x400046e0u +#define CYDEV_MFGCFG_MLOGIC_SIZE 0x0000000du +#define CYDEV_MFGCFG_MLOGIC_DMPSTR 0x400046e2u +#define CYDEV_MFGCFG_MLOGIC_SEG_BASE 0x400046e4u +#define CYDEV_MFGCFG_MLOGIC_SEG_SIZE 0x00000002u +#define CYDEV_MFGCFG_MLOGIC_SEG_CR 0x400046e4u +#define CYDEV_MFGCFG_MLOGIC_SEG_CFG0 0x400046e5u +#define CYDEV_MFGCFG_MLOGIC_DEBUG 0x400046e8u +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE 0x400046eau +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE 0x00000001u +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR 0x400046eau +#define CYDEV_MFGCFG_MLOGIC_REV_ID 0x400046ecu +#define CYDEV_RESET_BASE 0x400046f0u +#define CYDEV_RESET_SIZE 0x0000000fu +#define CYDEV_RESET_IPOR_CR0 0x400046f0u +#define CYDEV_RESET_IPOR_CR1 0x400046f1u +#define CYDEV_RESET_IPOR_CR2 0x400046f2u +#define CYDEV_RESET_IPOR_CR3 0x400046f3u +#define CYDEV_RESET_CR0 0x400046f4u +#define CYDEV_RESET_CR1 0x400046f5u +#define CYDEV_RESET_CR2 0x400046f6u +#define CYDEV_RESET_CR3 0x400046f7u +#define CYDEV_RESET_CR4 0x400046f8u +#define CYDEV_RESET_CR5 0x400046f9u +#define CYDEV_RESET_SR0 0x400046fau +#define CYDEV_RESET_SR1 0x400046fbu +#define CYDEV_RESET_SR2 0x400046fcu +#define CYDEV_RESET_SR3 0x400046fdu +#define CYDEV_RESET_TR 0x400046feu +#define CYDEV_SPC_BASE 0x40004700u +#define CYDEV_SPC_SIZE 0x00000100u +#define CYDEV_SPC_FM_EE_CR 0x40004700u +#define CYDEV_SPC_FM_EE_WAKE_CNT 0x40004701u +#define CYDEV_SPC_EE_SCR 0x40004702u +#define CYDEV_SPC_EE_ERR 0x40004703u +#define CYDEV_SPC_CPU_DATA 0x40004720u +#define CYDEV_SPC_DMA_DATA 0x40004721u +#define CYDEV_SPC_SR 0x40004722u +#define CYDEV_SPC_CR 0x40004723u +#define CYDEV_SPC_DMM_MAP_BASE 0x40004780u +#define CYDEV_SPC_DMM_MAP_SIZE 0x00000080u +#define CYDEV_SPC_DMM_MAP_SRAM_MBASE 0x40004780u +#define CYDEV_SPC_DMM_MAP_SRAM_MSIZE 0x00000080u +#define CYDEV_CACHE_BASE 0x40004800u +#define CYDEV_CACHE_SIZE 0x0000009cu +#define CYDEV_CACHE_CC_CTL 0x40004800u +#define CYDEV_CACHE_ECC_CORR 0x40004880u +#define CYDEV_CACHE_ECC_ERR 0x40004888u +#define CYDEV_CACHE_FLASH_ERR 0x40004890u +#define CYDEV_CACHE_HITMISS 0x40004898u +#define CYDEV_I2C_BASE 0x40004900u +#define CYDEV_I2C_SIZE 0x000000e1u +#define CYDEV_I2C_XCFG 0x400049c8u +#define CYDEV_I2C_ADR 0x400049cau +#define CYDEV_I2C_CFG 0x400049d6u +#define CYDEV_I2C_CSR 0x400049d7u +#define CYDEV_I2C_D 0x400049d8u +#define CYDEV_I2C_MCSR 0x400049d9u +#define CYDEV_I2C_CLK_DIV1 0x400049dbu +#define CYDEV_I2C_CLK_DIV2 0x400049dcu +#define CYDEV_I2C_TMOUT_CSR 0x400049ddu +#define CYDEV_I2C_TMOUT_SR 0x400049deu +#define CYDEV_I2C_TMOUT_CFG0 0x400049dfu +#define CYDEV_I2C_TMOUT_CFG1 0x400049e0u +#define CYDEV_DEC_BASE 0x40004e00u +#define CYDEV_DEC_SIZE 0x00000015u +#define CYDEV_DEC_CR 0x40004e00u +#define CYDEV_DEC_SR 0x40004e01u +#define CYDEV_DEC_SHIFT1 0x40004e02u +#define CYDEV_DEC_SHIFT2 0x40004e03u +#define CYDEV_DEC_DR2 0x40004e04u +#define CYDEV_DEC_DR2H 0x40004e05u +#define CYDEV_DEC_DR1 0x40004e06u +#define CYDEV_DEC_OCOR 0x40004e08u +#define CYDEV_DEC_OCORM 0x40004e09u +#define CYDEV_DEC_OCORH 0x40004e0au +#define CYDEV_DEC_GCOR 0x40004e0cu +#define CYDEV_DEC_GCORH 0x40004e0du +#define CYDEV_DEC_GVAL 0x40004e0eu +#define CYDEV_DEC_OUTSAMP 0x40004e10u +#define CYDEV_DEC_OUTSAMPM 0x40004e11u +#define CYDEV_DEC_OUTSAMPH 0x40004e12u +#define CYDEV_DEC_OUTSAMPS 0x40004e13u +#define CYDEV_DEC_COHER 0x40004e14u +#define CYDEV_TMR0_BASE 0x40004f00u +#define CYDEV_TMR0_SIZE 0x0000000cu +#define CYDEV_TMR0_CFG0 0x40004f00u +#define CYDEV_TMR0_CFG1 0x40004f01u +#define CYDEV_TMR0_CFG2 0x40004f02u +#define CYDEV_TMR0_SR0 0x40004f03u +#define CYDEV_TMR0_PER0 0x40004f04u +#define CYDEV_TMR0_PER1 0x40004f05u +#define CYDEV_TMR0_CNT_CMP0 0x40004f06u +#define CYDEV_TMR0_CNT_CMP1 0x40004f07u +#define CYDEV_TMR0_CAP0 0x40004f08u +#define CYDEV_TMR0_CAP1 0x40004f09u +#define CYDEV_TMR0_RT0 0x40004f0au +#define CYDEV_TMR0_RT1 0x40004f0bu +#define CYDEV_TMR1_BASE 0x40004f0cu +#define CYDEV_TMR1_SIZE 0x0000000cu +#define CYDEV_TMR1_CFG0 0x40004f0cu +#define CYDEV_TMR1_CFG1 0x40004f0du +#define CYDEV_TMR1_CFG2 0x40004f0eu +#define CYDEV_TMR1_SR0 0x40004f0fu +#define CYDEV_TMR1_PER0 0x40004f10u +#define CYDEV_TMR1_PER1 0x40004f11u +#define CYDEV_TMR1_CNT_CMP0 0x40004f12u +#define CYDEV_TMR1_CNT_CMP1 0x40004f13u +#define CYDEV_TMR1_CAP0 0x40004f14u +#define CYDEV_TMR1_CAP1 0x40004f15u +#define CYDEV_TMR1_RT0 0x40004f16u +#define CYDEV_TMR1_RT1 0x40004f17u +#define CYDEV_TMR2_BASE 0x40004f18u +#define CYDEV_TMR2_SIZE 0x0000000cu +#define CYDEV_TMR2_CFG0 0x40004f18u +#define CYDEV_TMR2_CFG1 0x40004f19u +#define CYDEV_TMR2_CFG2 0x40004f1au +#define CYDEV_TMR2_SR0 0x40004f1bu +#define CYDEV_TMR2_PER0 0x40004f1cu +#define CYDEV_TMR2_PER1 0x40004f1du +#define CYDEV_TMR2_CNT_CMP0 0x40004f1eu +#define CYDEV_TMR2_CNT_CMP1 0x40004f1fu +#define CYDEV_TMR2_CAP0 0x40004f20u +#define CYDEV_TMR2_CAP1 0x40004f21u +#define CYDEV_TMR2_RT0 0x40004f22u +#define CYDEV_TMR2_RT1 0x40004f23u +#define CYDEV_TMR3_BASE 0x40004f24u +#define CYDEV_TMR3_SIZE 0x0000000cu +#define CYDEV_TMR3_CFG0 0x40004f24u +#define CYDEV_TMR3_CFG1 0x40004f25u +#define CYDEV_TMR3_CFG2 0x40004f26u +#define CYDEV_TMR3_SR0 0x40004f27u +#define CYDEV_TMR3_PER0 0x40004f28u +#define CYDEV_TMR3_PER1 0x40004f29u +#define CYDEV_TMR3_CNT_CMP0 0x40004f2au +#define CYDEV_TMR3_CNT_CMP1 0x40004f2bu +#define CYDEV_TMR3_CAP0 0x40004f2cu +#define CYDEV_TMR3_CAP1 0x40004f2du +#define CYDEV_TMR3_RT0 0x40004f2eu +#define CYDEV_TMR3_RT1 0x40004f2fu +#define CYDEV_IO_BASE 0x40005000u +#define CYDEV_IO_SIZE 0x00000200u +#define CYDEV_IO_PC_BASE 0x40005000u +#define CYDEV_IO_PC_SIZE 0x00000080u +#define CYDEV_IO_PC_PRT0_BASE 0x40005000u +#define CYDEV_IO_PC_PRT0_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT0_PC0 0x40005000u +#define CYDEV_IO_PC_PRT0_PC1 0x40005001u +#define CYDEV_IO_PC_PRT0_PC2 0x40005002u +#define CYDEV_IO_PC_PRT0_PC3 0x40005003u +#define CYDEV_IO_PC_PRT0_PC4 0x40005004u +#define CYDEV_IO_PC_PRT0_PC5 0x40005005u +#define CYDEV_IO_PC_PRT0_PC6 0x40005006u +#define CYDEV_IO_PC_PRT0_PC7 0x40005007u +#define CYDEV_IO_PC_PRT1_BASE 0x40005008u +#define CYDEV_IO_PC_PRT1_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT1_PC0 0x40005008u +#define CYDEV_IO_PC_PRT1_PC1 0x40005009u +#define CYDEV_IO_PC_PRT1_PC2 0x4000500au +#define CYDEV_IO_PC_PRT1_PC3 0x4000500bu +#define CYDEV_IO_PC_PRT1_PC4 0x4000500cu +#define CYDEV_IO_PC_PRT1_PC5 0x4000500du +#define CYDEV_IO_PC_PRT1_PC6 0x4000500eu +#define CYDEV_IO_PC_PRT1_PC7 0x4000500fu +#define CYDEV_IO_PC_PRT2_BASE 0x40005010u +#define CYDEV_IO_PC_PRT2_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT2_PC0 0x40005010u +#define CYDEV_IO_PC_PRT2_PC1 0x40005011u +#define CYDEV_IO_PC_PRT2_PC2 0x40005012u +#define CYDEV_IO_PC_PRT2_PC3 0x40005013u +#define CYDEV_IO_PC_PRT2_PC4 0x40005014u +#define CYDEV_IO_PC_PRT2_PC5 0x40005015u +#define CYDEV_IO_PC_PRT2_PC6 0x40005016u +#define CYDEV_IO_PC_PRT2_PC7 0x40005017u +#define CYDEV_IO_PC_PRT3_BASE 0x40005018u +#define CYDEV_IO_PC_PRT3_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT3_PC0 0x40005018u +#define CYDEV_IO_PC_PRT3_PC1 0x40005019u +#define CYDEV_IO_PC_PRT3_PC2 0x4000501au +#define CYDEV_IO_PC_PRT3_PC3 0x4000501bu +#define CYDEV_IO_PC_PRT3_PC4 0x4000501cu +#define CYDEV_IO_PC_PRT3_PC5 0x4000501du +#define CYDEV_IO_PC_PRT3_PC6 0x4000501eu +#define CYDEV_IO_PC_PRT3_PC7 0x4000501fu +#define CYDEV_IO_PC_PRT4_BASE 0x40005020u +#define CYDEV_IO_PC_PRT4_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT4_PC0 0x40005020u +#define CYDEV_IO_PC_PRT4_PC1 0x40005021u +#define CYDEV_IO_PC_PRT4_PC2 0x40005022u +#define CYDEV_IO_PC_PRT4_PC3 0x40005023u +#define CYDEV_IO_PC_PRT4_PC4 0x40005024u +#define CYDEV_IO_PC_PRT4_PC5 0x40005025u +#define CYDEV_IO_PC_PRT4_PC6 0x40005026u +#define CYDEV_IO_PC_PRT4_PC7 0x40005027u +#define CYDEV_IO_PC_PRT5_BASE 0x40005028u +#define CYDEV_IO_PC_PRT5_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT5_PC0 0x40005028u +#define CYDEV_IO_PC_PRT5_PC1 0x40005029u +#define CYDEV_IO_PC_PRT5_PC2 0x4000502au +#define CYDEV_IO_PC_PRT5_PC3 0x4000502bu +#define CYDEV_IO_PC_PRT5_PC4 0x4000502cu +#define CYDEV_IO_PC_PRT5_PC5 0x4000502du +#define CYDEV_IO_PC_PRT5_PC6 0x4000502eu +#define CYDEV_IO_PC_PRT5_PC7 0x4000502fu +#define CYDEV_IO_PC_PRT6_BASE 0x40005030u +#define CYDEV_IO_PC_PRT6_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT6_PC0 0x40005030u +#define CYDEV_IO_PC_PRT6_PC1 0x40005031u +#define CYDEV_IO_PC_PRT6_PC2 0x40005032u +#define CYDEV_IO_PC_PRT6_PC3 0x40005033u +#define CYDEV_IO_PC_PRT6_PC4 0x40005034u +#define CYDEV_IO_PC_PRT6_PC5 0x40005035u +#define CYDEV_IO_PC_PRT6_PC6 0x40005036u +#define CYDEV_IO_PC_PRT6_PC7 0x40005037u +#define CYDEV_IO_PC_PRT12_BASE 0x40005060u +#define CYDEV_IO_PC_PRT12_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT12_PC0 0x40005060u +#define CYDEV_IO_PC_PRT12_PC1 0x40005061u +#define CYDEV_IO_PC_PRT12_PC2 0x40005062u +#define CYDEV_IO_PC_PRT12_PC3 0x40005063u +#define CYDEV_IO_PC_PRT12_PC4 0x40005064u +#define CYDEV_IO_PC_PRT12_PC5 0x40005065u +#define CYDEV_IO_PC_PRT12_PC6 0x40005066u +#define CYDEV_IO_PC_PRT12_PC7 0x40005067u +#define CYDEV_IO_PC_PRT15_BASE 0x40005078u +#define CYDEV_IO_PC_PRT15_SIZE 0x00000006u +#define CYDEV_IO_PC_PRT15_PC0 0x40005078u +#define CYDEV_IO_PC_PRT15_PC1 0x40005079u +#define CYDEV_IO_PC_PRT15_PC2 0x4000507au +#define CYDEV_IO_PC_PRT15_PC3 0x4000507bu +#define CYDEV_IO_PC_PRT15_PC4 0x4000507cu +#define CYDEV_IO_PC_PRT15_PC5 0x4000507du +#define CYDEV_IO_PC_PRT15_7_6_BASE 0x4000507eu +#define CYDEV_IO_PC_PRT15_7_6_SIZE 0x00000002u +#define CYDEV_IO_PC_PRT15_7_6_PC0 0x4000507eu +#define CYDEV_IO_PC_PRT15_7_6_PC1 0x4000507fu +#define CYDEV_IO_DR_BASE 0x40005080u +#define CYDEV_IO_DR_SIZE 0x00000010u +#define CYDEV_IO_DR_PRT0_BASE 0x40005080u +#define CYDEV_IO_DR_PRT0_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT0_DR_ALIAS 0x40005080u +#define CYDEV_IO_DR_PRT1_BASE 0x40005081u +#define CYDEV_IO_DR_PRT1_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT1_DR_ALIAS 0x40005081u +#define CYDEV_IO_DR_PRT2_BASE 0x40005082u +#define CYDEV_IO_DR_PRT2_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT2_DR_ALIAS 0x40005082u +#define CYDEV_IO_DR_PRT3_BASE 0x40005083u +#define CYDEV_IO_DR_PRT3_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT3_DR_ALIAS 0x40005083u +#define CYDEV_IO_DR_PRT4_BASE 0x40005084u +#define CYDEV_IO_DR_PRT4_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT4_DR_ALIAS 0x40005084u +#define CYDEV_IO_DR_PRT5_BASE 0x40005085u +#define CYDEV_IO_DR_PRT5_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT5_DR_ALIAS 0x40005085u +#define CYDEV_IO_DR_PRT6_BASE 0x40005086u +#define CYDEV_IO_DR_PRT6_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT6_DR_ALIAS 0x40005086u +#define CYDEV_IO_DR_PRT12_BASE 0x4000508cu +#define CYDEV_IO_DR_PRT12_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT12_DR_ALIAS 0x4000508cu +#define CYDEV_IO_DR_PRT15_BASE 0x4000508fu +#define CYDEV_IO_DR_PRT15_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT15_DR_15_ALIAS 0x4000508fu +#define CYDEV_IO_PS_BASE 0x40005090u +#define CYDEV_IO_PS_SIZE 0x00000010u +#define CYDEV_IO_PS_PRT0_BASE 0x40005090u +#define CYDEV_IO_PS_PRT0_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT0_PS_ALIAS 0x40005090u +#define CYDEV_IO_PS_PRT1_BASE 0x40005091u +#define CYDEV_IO_PS_PRT1_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT1_PS_ALIAS 0x40005091u +#define CYDEV_IO_PS_PRT2_BASE 0x40005092u +#define CYDEV_IO_PS_PRT2_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT2_PS_ALIAS 0x40005092u +#define CYDEV_IO_PS_PRT3_BASE 0x40005093u +#define CYDEV_IO_PS_PRT3_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT3_PS_ALIAS 0x40005093u +#define CYDEV_IO_PS_PRT4_BASE 0x40005094u +#define CYDEV_IO_PS_PRT4_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT4_PS_ALIAS 0x40005094u +#define CYDEV_IO_PS_PRT5_BASE 0x40005095u +#define CYDEV_IO_PS_PRT5_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT5_PS_ALIAS 0x40005095u +#define CYDEV_IO_PS_PRT6_BASE 0x40005096u +#define CYDEV_IO_PS_PRT6_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT6_PS_ALIAS 0x40005096u +#define CYDEV_IO_PS_PRT12_BASE 0x4000509cu +#define CYDEV_IO_PS_PRT12_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT12_PS_ALIAS 0x4000509cu +#define CYDEV_IO_PS_PRT15_BASE 0x4000509fu +#define CYDEV_IO_PS_PRT15_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT15_PS15_ALIAS 0x4000509fu +#define CYDEV_IO_PRT_BASE 0x40005100u +#define CYDEV_IO_PRT_SIZE 0x00000100u +#define CYDEV_IO_PRT_PRT0_BASE 0x40005100u +#define CYDEV_IO_PRT_PRT0_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT0_DR 0x40005100u +#define CYDEV_IO_PRT_PRT0_PS 0x40005101u +#define CYDEV_IO_PRT_PRT0_DM0 0x40005102u +#define CYDEV_IO_PRT_PRT0_DM1 0x40005103u +#define CYDEV_IO_PRT_PRT0_DM2 0x40005104u +#define CYDEV_IO_PRT_PRT0_SLW 0x40005105u +#define CYDEV_IO_PRT_PRT0_BYP 0x40005106u +#define CYDEV_IO_PRT_PRT0_BIE 0x40005107u +#define CYDEV_IO_PRT_PRT0_INP_DIS 0x40005108u +#define CYDEV_IO_PRT_PRT0_CTL 0x40005109u +#define CYDEV_IO_PRT_PRT0_PRT 0x4000510au +#define CYDEV_IO_PRT_PRT0_BIT_MASK 0x4000510bu +#define CYDEV_IO_PRT_PRT0_AMUX 0x4000510cu +#define CYDEV_IO_PRT_PRT0_AG 0x4000510du +#define CYDEV_IO_PRT_PRT0_LCD_COM_SEG 0x4000510eu +#define CYDEV_IO_PRT_PRT0_LCD_EN 0x4000510fu +#define CYDEV_IO_PRT_PRT1_BASE 0x40005110u +#define CYDEV_IO_PRT_PRT1_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT1_DR 0x40005110u +#define CYDEV_IO_PRT_PRT1_PS 0x40005111u +#define CYDEV_IO_PRT_PRT1_DM0 0x40005112u +#define CYDEV_IO_PRT_PRT1_DM1 0x40005113u +#define CYDEV_IO_PRT_PRT1_DM2 0x40005114u +#define CYDEV_IO_PRT_PRT1_SLW 0x40005115u +#define CYDEV_IO_PRT_PRT1_BYP 0x40005116u +#define CYDEV_IO_PRT_PRT1_BIE 0x40005117u +#define CYDEV_IO_PRT_PRT1_INP_DIS 0x40005118u +#define CYDEV_IO_PRT_PRT1_CTL 0x40005119u +#define CYDEV_IO_PRT_PRT1_PRT 0x4000511au +#define CYDEV_IO_PRT_PRT1_BIT_MASK 0x4000511bu +#define CYDEV_IO_PRT_PRT1_AMUX 0x4000511cu +#define CYDEV_IO_PRT_PRT1_AG 0x4000511du +#define CYDEV_IO_PRT_PRT1_LCD_COM_SEG 0x4000511eu +#define CYDEV_IO_PRT_PRT1_LCD_EN 0x4000511fu +#define CYDEV_IO_PRT_PRT2_BASE 0x40005120u +#define CYDEV_IO_PRT_PRT2_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT2_DR 0x40005120u +#define CYDEV_IO_PRT_PRT2_PS 0x40005121u +#define CYDEV_IO_PRT_PRT2_DM0 0x40005122u +#define CYDEV_IO_PRT_PRT2_DM1 0x40005123u +#define CYDEV_IO_PRT_PRT2_DM2 0x40005124u +#define CYDEV_IO_PRT_PRT2_SLW 0x40005125u +#define CYDEV_IO_PRT_PRT2_BYP 0x40005126u +#define CYDEV_IO_PRT_PRT2_BIE 0x40005127u +#define CYDEV_IO_PRT_PRT2_INP_DIS 0x40005128u +#define CYDEV_IO_PRT_PRT2_CTL 0x40005129u +#define CYDEV_IO_PRT_PRT2_PRT 0x4000512au +#define CYDEV_IO_PRT_PRT2_BIT_MASK 0x4000512bu +#define CYDEV_IO_PRT_PRT2_AMUX 0x4000512cu +#define CYDEV_IO_PRT_PRT2_AG 0x4000512du +#define CYDEV_IO_PRT_PRT2_LCD_COM_SEG 0x4000512eu +#define CYDEV_IO_PRT_PRT2_LCD_EN 0x4000512fu +#define CYDEV_IO_PRT_PRT3_BASE 0x40005130u +#define CYDEV_IO_PRT_PRT3_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT3_DR 0x40005130u +#define CYDEV_IO_PRT_PRT3_PS 0x40005131u +#define CYDEV_IO_PRT_PRT3_DM0 0x40005132u +#define CYDEV_IO_PRT_PRT3_DM1 0x40005133u +#define CYDEV_IO_PRT_PRT3_DM2 0x40005134u +#define CYDEV_IO_PRT_PRT3_SLW 0x40005135u +#define CYDEV_IO_PRT_PRT3_BYP 0x40005136u +#define CYDEV_IO_PRT_PRT3_BIE 0x40005137u +#define CYDEV_IO_PRT_PRT3_INP_DIS 0x40005138u +#define CYDEV_IO_PRT_PRT3_CTL 0x40005139u +#define CYDEV_IO_PRT_PRT3_PRT 0x4000513au +#define CYDEV_IO_PRT_PRT3_BIT_MASK 0x4000513bu +#define CYDEV_IO_PRT_PRT3_AMUX 0x4000513cu +#define CYDEV_IO_PRT_PRT3_AG 0x4000513du +#define CYDEV_IO_PRT_PRT3_LCD_COM_SEG 0x4000513eu +#define CYDEV_IO_PRT_PRT3_LCD_EN 0x4000513fu +#define CYDEV_IO_PRT_PRT4_BASE 0x40005140u +#define CYDEV_IO_PRT_PRT4_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT4_DR 0x40005140u +#define CYDEV_IO_PRT_PRT4_PS 0x40005141u +#define CYDEV_IO_PRT_PRT4_DM0 0x40005142u +#define CYDEV_IO_PRT_PRT4_DM1 0x40005143u +#define CYDEV_IO_PRT_PRT4_DM2 0x40005144u +#define CYDEV_IO_PRT_PRT4_SLW 0x40005145u +#define CYDEV_IO_PRT_PRT4_BYP 0x40005146u +#define CYDEV_IO_PRT_PRT4_BIE 0x40005147u +#define CYDEV_IO_PRT_PRT4_INP_DIS 0x40005148u +#define CYDEV_IO_PRT_PRT4_CTL 0x40005149u +#define CYDEV_IO_PRT_PRT4_PRT 0x4000514au +#define CYDEV_IO_PRT_PRT4_BIT_MASK 0x4000514bu +#define CYDEV_IO_PRT_PRT4_AMUX 0x4000514cu +#define CYDEV_IO_PRT_PRT4_AG 0x4000514du +#define CYDEV_IO_PRT_PRT4_LCD_COM_SEG 0x4000514eu +#define CYDEV_IO_PRT_PRT4_LCD_EN 0x4000514fu +#define CYDEV_IO_PRT_PRT5_BASE 0x40005150u +#define CYDEV_IO_PRT_PRT5_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT5_DR 0x40005150u +#define CYDEV_IO_PRT_PRT5_PS 0x40005151u +#define CYDEV_IO_PRT_PRT5_DM0 0x40005152u +#define CYDEV_IO_PRT_PRT5_DM1 0x40005153u +#define CYDEV_IO_PRT_PRT5_DM2 0x40005154u +#define CYDEV_IO_PRT_PRT5_SLW 0x40005155u +#define CYDEV_IO_PRT_PRT5_BYP 0x40005156u +#define CYDEV_IO_PRT_PRT5_BIE 0x40005157u +#define CYDEV_IO_PRT_PRT5_INP_DIS 0x40005158u +#define CYDEV_IO_PRT_PRT5_CTL 0x40005159u +#define CYDEV_IO_PRT_PRT5_PRT 0x4000515au +#define CYDEV_IO_PRT_PRT5_BIT_MASK 0x4000515bu +#define CYDEV_IO_PRT_PRT5_AMUX 0x4000515cu +#define CYDEV_IO_PRT_PRT5_AG 0x4000515du +#define CYDEV_IO_PRT_PRT5_LCD_COM_SEG 0x4000515eu +#define CYDEV_IO_PRT_PRT5_LCD_EN 0x4000515fu +#define CYDEV_IO_PRT_PRT6_BASE 0x40005160u +#define CYDEV_IO_PRT_PRT6_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT6_DR 0x40005160u +#define CYDEV_IO_PRT_PRT6_PS 0x40005161u +#define CYDEV_IO_PRT_PRT6_DM0 0x40005162u +#define CYDEV_IO_PRT_PRT6_DM1 0x40005163u +#define CYDEV_IO_PRT_PRT6_DM2 0x40005164u +#define CYDEV_IO_PRT_PRT6_SLW 0x40005165u +#define CYDEV_IO_PRT_PRT6_BYP 0x40005166u +#define CYDEV_IO_PRT_PRT6_BIE 0x40005167u +#define CYDEV_IO_PRT_PRT6_INP_DIS 0x40005168u +#define CYDEV_IO_PRT_PRT6_CTL 0x40005169u +#define CYDEV_IO_PRT_PRT6_PRT 0x4000516au +#define CYDEV_IO_PRT_PRT6_BIT_MASK 0x4000516bu +#define CYDEV_IO_PRT_PRT6_AMUX 0x4000516cu +#define CYDEV_IO_PRT_PRT6_AG 0x4000516du +#define CYDEV_IO_PRT_PRT6_LCD_COM_SEG 0x4000516eu +#define CYDEV_IO_PRT_PRT6_LCD_EN 0x4000516fu +#define CYDEV_IO_PRT_PRT12_BASE 0x400051c0u +#define CYDEV_IO_PRT_PRT12_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT12_DR 0x400051c0u +#define CYDEV_IO_PRT_PRT12_PS 0x400051c1u +#define CYDEV_IO_PRT_PRT12_DM0 0x400051c2u +#define CYDEV_IO_PRT_PRT12_DM1 0x400051c3u +#define CYDEV_IO_PRT_PRT12_DM2 0x400051c4u +#define CYDEV_IO_PRT_PRT12_SLW 0x400051c5u +#define CYDEV_IO_PRT_PRT12_BYP 0x400051c6u +#define CYDEV_IO_PRT_PRT12_BIE 0x400051c7u +#define CYDEV_IO_PRT_PRT12_INP_DIS 0x400051c8u +#define CYDEV_IO_PRT_PRT12_SIO_HYST_EN 0x400051c9u +#define CYDEV_IO_PRT_PRT12_PRT 0x400051cau +#define CYDEV_IO_PRT_PRT12_BIT_MASK 0x400051cbu +#define CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ 0x400051ccu +#define CYDEV_IO_PRT_PRT12_AG 0x400051cdu +#define CYDEV_IO_PRT_PRT12_SIO_CFG 0x400051ceu +#define CYDEV_IO_PRT_PRT12_SIO_DIFF 0x400051cfu +#define CYDEV_IO_PRT_PRT15_BASE 0x400051f0u +#define CYDEV_IO_PRT_PRT15_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT15_DR 0x400051f0u +#define CYDEV_IO_PRT_PRT15_PS 0x400051f1u +#define CYDEV_IO_PRT_PRT15_DM0 0x400051f2u +#define CYDEV_IO_PRT_PRT15_DM1 0x400051f3u +#define CYDEV_IO_PRT_PRT15_DM2 0x400051f4u +#define CYDEV_IO_PRT_PRT15_SLW 0x400051f5u +#define CYDEV_IO_PRT_PRT15_BYP 0x400051f6u +#define CYDEV_IO_PRT_PRT15_BIE 0x400051f7u +#define CYDEV_IO_PRT_PRT15_INP_DIS 0x400051f8u +#define CYDEV_IO_PRT_PRT15_CTL 0x400051f9u +#define CYDEV_IO_PRT_PRT15_PRT 0x400051fau +#define CYDEV_IO_PRT_PRT15_BIT_MASK 0x400051fbu +#define CYDEV_IO_PRT_PRT15_AMUX 0x400051fcu +#define CYDEV_IO_PRT_PRT15_AG 0x400051fdu +#define CYDEV_IO_PRT_PRT15_LCD_COM_SEG 0x400051feu +#define CYDEV_IO_PRT_PRT15_LCD_EN 0x400051ffu +#define CYDEV_PRTDSI_BASE 0x40005200u +#define CYDEV_PRTDSI_SIZE 0x0000007fu +#define CYDEV_PRTDSI_PRT0_BASE 0x40005200u +#define CYDEV_PRTDSI_PRT0_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT0_OUT_SEL0 0x40005200u +#define CYDEV_PRTDSI_PRT0_OUT_SEL1 0x40005201u +#define CYDEV_PRTDSI_PRT0_OE_SEL0 0x40005202u +#define CYDEV_PRTDSI_PRT0_OE_SEL1 0x40005203u +#define CYDEV_PRTDSI_PRT0_DBL_SYNC_IN 0x40005204u +#define CYDEV_PRTDSI_PRT0_SYNC_OUT 0x40005205u +#define CYDEV_PRTDSI_PRT0_CAPS_SEL 0x40005206u +#define CYDEV_PRTDSI_PRT1_BASE 0x40005208u +#define CYDEV_PRTDSI_PRT1_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT1_OUT_SEL0 0x40005208u +#define CYDEV_PRTDSI_PRT1_OUT_SEL1 0x40005209u +#define CYDEV_PRTDSI_PRT1_OE_SEL0 0x4000520au +#define CYDEV_PRTDSI_PRT1_OE_SEL1 0x4000520bu +#define CYDEV_PRTDSI_PRT1_DBL_SYNC_IN 0x4000520cu +#define CYDEV_PRTDSI_PRT1_SYNC_OUT 0x4000520du +#define CYDEV_PRTDSI_PRT1_CAPS_SEL 0x4000520eu +#define CYDEV_PRTDSI_PRT2_BASE 0x40005210u +#define CYDEV_PRTDSI_PRT2_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT2_OUT_SEL0 0x40005210u +#define CYDEV_PRTDSI_PRT2_OUT_SEL1 0x40005211u +#define CYDEV_PRTDSI_PRT2_OE_SEL0 0x40005212u +#define CYDEV_PRTDSI_PRT2_OE_SEL1 0x40005213u +#define CYDEV_PRTDSI_PRT2_DBL_SYNC_IN 0x40005214u +#define CYDEV_PRTDSI_PRT2_SYNC_OUT 0x40005215u +#define CYDEV_PRTDSI_PRT2_CAPS_SEL 0x40005216u +#define CYDEV_PRTDSI_PRT3_BASE 0x40005218u +#define CYDEV_PRTDSI_PRT3_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT3_OUT_SEL0 0x40005218u +#define CYDEV_PRTDSI_PRT3_OUT_SEL1 0x40005219u +#define CYDEV_PRTDSI_PRT3_OE_SEL0 0x4000521au +#define CYDEV_PRTDSI_PRT3_OE_SEL1 0x4000521bu +#define CYDEV_PRTDSI_PRT3_DBL_SYNC_IN 0x4000521cu +#define CYDEV_PRTDSI_PRT3_SYNC_OUT 0x4000521du +#define CYDEV_PRTDSI_PRT3_CAPS_SEL 0x4000521eu +#define CYDEV_PRTDSI_PRT4_BASE 0x40005220u +#define CYDEV_PRTDSI_PRT4_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT4_OUT_SEL0 0x40005220u +#define CYDEV_PRTDSI_PRT4_OUT_SEL1 0x40005221u +#define CYDEV_PRTDSI_PRT4_OE_SEL0 0x40005222u +#define CYDEV_PRTDSI_PRT4_OE_SEL1 0x40005223u +#define CYDEV_PRTDSI_PRT4_DBL_SYNC_IN 0x40005224u +#define CYDEV_PRTDSI_PRT4_SYNC_OUT 0x40005225u +#define CYDEV_PRTDSI_PRT4_CAPS_SEL 0x40005226u +#define CYDEV_PRTDSI_PRT5_BASE 0x40005228u +#define CYDEV_PRTDSI_PRT5_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT5_OUT_SEL0 0x40005228u +#define CYDEV_PRTDSI_PRT5_OUT_SEL1 0x40005229u +#define CYDEV_PRTDSI_PRT5_OE_SEL0 0x4000522au +#define CYDEV_PRTDSI_PRT5_OE_SEL1 0x4000522bu +#define CYDEV_PRTDSI_PRT5_DBL_SYNC_IN 0x4000522cu +#define CYDEV_PRTDSI_PRT5_SYNC_OUT 0x4000522du +#define CYDEV_PRTDSI_PRT5_CAPS_SEL 0x4000522eu +#define CYDEV_PRTDSI_PRT6_BASE 0x40005230u +#define CYDEV_PRTDSI_PRT6_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT6_OUT_SEL0 0x40005230u +#define CYDEV_PRTDSI_PRT6_OUT_SEL1 0x40005231u +#define CYDEV_PRTDSI_PRT6_OE_SEL0 0x40005232u +#define CYDEV_PRTDSI_PRT6_OE_SEL1 0x40005233u +#define CYDEV_PRTDSI_PRT6_DBL_SYNC_IN 0x40005234u +#define CYDEV_PRTDSI_PRT6_SYNC_OUT 0x40005235u +#define CYDEV_PRTDSI_PRT6_CAPS_SEL 0x40005236u +#define CYDEV_PRTDSI_PRT12_BASE 0x40005260u +#define CYDEV_PRTDSI_PRT12_SIZE 0x00000006u +#define CYDEV_PRTDSI_PRT12_OUT_SEL0 0x40005260u +#define CYDEV_PRTDSI_PRT12_OUT_SEL1 0x40005261u +#define CYDEV_PRTDSI_PRT12_OE_SEL0 0x40005262u +#define CYDEV_PRTDSI_PRT12_OE_SEL1 0x40005263u +#define CYDEV_PRTDSI_PRT12_DBL_SYNC_IN 0x40005264u +#define CYDEV_PRTDSI_PRT12_SYNC_OUT 0x40005265u +#define CYDEV_PRTDSI_PRT15_BASE 0x40005278u +#define CYDEV_PRTDSI_PRT15_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT15_OUT_SEL0 0x40005278u +#define CYDEV_PRTDSI_PRT15_OUT_SEL1 0x40005279u +#define CYDEV_PRTDSI_PRT15_OE_SEL0 0x4000527au +#define CYDEV_PRTDSI_PRT15_OE_SEL1 0x4000527bu +#define CYDEV_PRTDSI_PRT15_DBL_SYNC_IN 0x4000527cu +#define CYDEV_PRTDSI_PRT15_SYNC_OUT 0x4000527du +#define CYDEV_PRTDSI_PRT15_CAPS_SEL 0x4000527eu +#define CYDEV_EMIF_BASE 0x40005400u +#define CYDEV_EMIF_SIZE 0x00000007u +#define CYDEV_EMIF_NO_UDB 0x40005400u +#define CYDEV_EMIF_RP_WAIT_STATES 0x40005401u +#define CYDEV_EMIF_MEM_DWN 0x40005402u +#define CYDEV_EMIF_MEMCLK_DIV 0x40005403u +#define CYDEV_EMIF_CLOCK_EN 0x40005404u +#define CYDEV_EMIF_EM_TYPE 0x40005405u +#define CYDEV_EMIF_WP_WAIT_STATES 0x40005406u +#define CYDEV_ANAIF_BASE 0x40005800u +#define CYDEV_ANAIF_SIZE 0x000003a9u +#define CYDEV_ANAIF_CFG_BASE 0x40005800u +#define CYDEV_ANAIF_CFG_SIZE 0x0000010fu +#define CYDEV_ANAIF_CFG_SC0_BASE 0x40005800u +#define CYDEV_ANAIF_CFG_SC0_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_SC0_CR0 0x40005800u +#define CYDEV_ANAIF_CFG_SC0_CR1 0x40005801u +#define CYDEV_ANAIF_CFG_SC0_CR2 0x40005802u +#define CYDEV_ANAIF_CFG_SC1_BASE 0x40005804u +#define CYDEV_ANAIF_CFG_SC1_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_SC1_CR0 0x40005804u +#define CYDEV_ANAIF_CFG_SC1_CR1 0x40005805u +#define CYDEV_ANAIF_CFG_SC1_CR2 0x40005806u +#define CYDEV_ANAIF_CFG_SC2_BASE 0x40005808u +#define CYDEV_ANAIF_CFG_SC2_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_SC2_CR0 0x40005808u +#define CYDEV_ANAIF_CFG_SC2_CR1 0x40005809u +#define CYDEV_ANAIF_CFG_SC2_CR2 0x4000580au +#define CYDEV_ANAIF_CFG_SC3_BASE 0x4000580cu +#define CYDEV_ANAIF_CFG_SC3_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_SC3_CR0 0x4000580cu +#define CYDEV_ANAIF_CFG_SC3_CR1 0x4000580du +#define CYDEV_ANAIF_CFG_SC3_CR2 0x4000580eu +#define CYDEV_ANAIF_CFG_DAC0_BASE 0x40005820u +#define CYDEV_ANAIF_CFG_DAC0_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_DAC0_CR0 0x40005820u +#define CYDEV_ANAIF_CFG_DAC0_CR1 0x40005821u +#define CYDEV_ANAIF_CFG_DAC0_TST 0x40005822u +#define CYDEV_ANAIF_CFG_DAC1_BASE 0x40005824u +#define CYDEV_ANAIF_CFG_DAC1_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_DAC1_CR0 0x40005824u +#define CYDEV_ANAIF_CFG_DAC1_CR1 0x40005825u +#define CYDEV_ANAIF_CFG_DAC1_TST 0x40005826u +#define CYDEV_ANAIF_CFG_DAC2_BASE 0x40005828u +#define CYDEV_ANAIF_CFG_DAC2_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_DAC2_CR0 0x40005828u +#define CYDEV_ANAIF_CFG_DAC2_CR1 0x40005829u +#define CYDEV_ANAIF_CFG_DAC2_TST 0x4000582au +#define CYDEV_ANAIF_CFG_DAC3_BASE 0x4000582cu +#define CYDEV_ANAIF_CFG_DAC3_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_DAC3_CR0 0x4000582cu +#define CYDEV_ANAIF_CFG_DAC3_CR1 0x4000582du +#define CYDEV_ANAIF_CFG_DAC3_TST 0x4000582eu +#define CYDEV_ANAIF_CFG_CMP0_BASE 0x40005840u +#define CYDEV_ANAIF_CFG_CMP0_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_CMP0_CR 0x40005840u +#define CYDEV_ANAIF_CFG_CMP1_BASE 0x40005841u +#define CYDEV_ANAIF_CFG_CMP1_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_CMP1_CR 0x40005841u +#define CYDEV_ANAIF_CFG_CMP2_BASE 0x40005842u +#define CYDEV_ANAIF_CFG_CMP2_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_CMP2_CR 0x40005842u +#define CYDEV_ANAIF_CFG_CMP3_BASE 0x40005843u +#define CYDEV_ANAIF_CFG_CMP3_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_CMP3_CR 0x40005843u +#define CYDEV_ANAIF_CFG_LUT0_BASE 0x40005848u +#define CYDEV_ANAIF_CFG_LUT0_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LUT0_CR 0x40005848u +#define CYDEV_ANAIF_CFG_LUT0_MX 0x40005849u +#define CYDEV_ANAIF_CFG_LUT1_BASE 0x4000584au +#define CYDEV_ANAIF_CFG_LUT1_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LUT1_CR 0x4000584au +#define CYDEV_ANAIF_CFG_LUT1_MX 0x4000584bu +#define CYDEV_ANAIF_CFG_LUT2_BASE 0x4000584cu +#define CYDEV_ANAIF_CFG_LUT2_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LUT2_CR 0x4000584cu +#define CYDEV_ANAIF_CFG_LUT2_MX 0x4000584du +#define CYDEV_ANAIF_CFG_LUT3_BASE 0x4000584eu +#define CYDEV_ANAIF_CFG_LUT3_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LUT3_CR 0x4000584eu +#define CYDEV_ANAIF_CFG_LUT3_MX 0x4000584fu +#define CYDEV_ANAIF_CFG_OPAMP0_BASE 0x40005858u +#define CYDEV_ANAIF_CFG_OPAMP0_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_OPAMP0_CR 0x40005858u +#define CYDEV_ANAIF_CFG_OPAMP0_RSVD 0x40005859u +#define CYDEV_ANAIF_CFG_OPAMP1_BASE 0x4000585au +#define CYDEV_ANAIF_CFG_OPAMP1_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_OPAMP1_CR 0x4000585au +#define CYDEV_ANAIF_CFG_OPAMP1_RSVD 0x4000585bu +#define CYDEV_ANAIF_CFG_OPAMP2_BASE 0x4000585cu +#define CYDEV_ANAIF_CFG_OPAMP2_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_OPAMP2_CR 0x4000585cu +#define CYDEV_ANAIF_CFG_OPAMP2_RSVD 0x4000585du +#define CYDEV_ANAIF_CFG_OPAMP3_BASE 0x4000585eu +#define CYDEV_ANAIF_CFG_OPAMP3_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_OPAMP3_CR 0x4000585eu +#define CYDEV_ANAIF_CFG_OPAMP3_RSVD 0x4000585fu +#define CYDEV_ANAIF_CFG_LCDDAC_BASE 0x40005868u +#define CYDEV_ANAIF_CFG_LCDDAC_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LCDDAC_CR0 0x40005868u +#define CYDEV_ANAIF_CFG_LCDDAC_CR1 0x40005869u +#define CYDEV_ANAIF_CFG_LCDDRV_BASE 0x4000586au +#define CYDEV_ANAIF_CFG_LCDDRV_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_LCDDRV_CR 0x4000586au +#define CYDEV_ANAIF_CFG_LCDTMR_BASE 0x4000586bu +#define CYDEV_ANAIF_CFG_LCDTMR_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_LCDTMR_CFG 0x4000586bu +#define CYDEV_ANAIF_CFG_BG_BASE 0x4000586cu +#define CYDEV_ANAIF_CFG_BG_SIZE 0x00000004u +#define CYDEV_ANAIF_CFG_BG_CR0 0x4000586cu +#define CYDEV_ANAIF_CFG_BG_RSVD 0x4000586du +#define CYDEV_ANAIF_CFG_BG_DFT0 0x4000586eu +#define CYDEV_ANAIF_CFG_BG_DFT1 0x4000586fu +#define CYDEV_ANAIF_CFG_CAPSL_BASE 0x40005870u +#define CYDEV_ANAIF_CFG_CAPSL_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_CAPSL_CFG0 0x40005870u +#define CYDEV_ANAIF_CFG_CAPSL_CFG1 0x40005871u +#define CYDEV_ANAIF_CFG_CAPSR_BASE 0x40005872u +#define CYDEV_ANAIF_CFG_CAPSR_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_CAPSR_CFG0 0x40005872u +#define CYDEV_ANAIF_CFG_CAPSR_CFG1 0x40005873u +#define CYDEV_ANAIF_CFG_PUMP_BASE 0x40005876u +#define CYDEV_ANAIF_CFG_PUMP_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_PUMP_CR0 0x40005876u +#define CYDEV_ANAIF_CFG_PUMP_CR1 0x40005877u +#define CYDEV_ANAIF_CFG_LPF0_BASE 0x40005878u +#define CYDEV_ANAIF_CFG_LPF0_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LPF0_CR0 0x40005878u +#define CYDEV_ANAIF_CFG_LPF0_RSVD 0x40005879u +#define CYDEV_ANAIF_CFG_LPF1_BASE 0x4000587au +#define CYDEV_ANAIF_CFG_LPF1_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LPF1_CR0 0x4000587au +#define CYDEV_ANAIF_CFG_LPF1_RSVD 0x4000587bu +#define CYDEV_ANAIF_CFG_MISC_BASE 0x4000587cu +#define CYDEV_ANAIF_CFG_MISC_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_MISC_CR0 0x4000587cu +#define CYDEV_ANAIF_CFG_DSM0_BASE 0x40005880u +#define CYDEV_ANAIF_CFG_DSM0_SIZE 0x00000020u +#define CYDEV_ANAIF_CFG_DSM0_CR0 0x40005880u +#define CYDEV_ANAIF_CFG_DSM0_CR1 0x40005881u +#define CYDEV_ANAIF_CFG_DSM0_CR2 0x40005882u +#define CYDEV_ANAIF_CFG_DSM0_CR3 0x40005883u +#define CYDEV_ANAIF_CFG_DSM0_CR4 0x40005884u +#define CYDEV_ANAIF_CFG_DSM0_CR5 0x40005885u +#define CYDEV_ANAIF_CFG_DSM0_CR6 0x40005886u +#define CYDEV_ANAIF_CFG_DSM0_CR7 0x40005887u +#define CYDEV_ANAIF_CFG_DSM0_CR8 0x40005888u +#define CYDEV_ANAIF_CFG_DSM0_CR9 0x40005889u +#define CYDEV_ANAIF_CFG_DSM0_CR10 0x4000588au +#define CYDEV_ANAIF_CFG_DSM0_CR11 0x4000588bu +#define CYDEV_ANAIF_CFG_DSM0_CR12 0x4000588cu +#define CYDEV_ANAIF_CFG_DSM0_CR13 0x4000588du +#define CYDEV_ANAIF_CFG_DSM0_CR14 0x4000588eu +#define CYDEV_ANAIF_CFG_DSM0_CR15 0x4000588fu +#define CYDEV_ANAIF_CFG_DSM0_CR16 0x40005890u +#define CYDEV_ANAIF_CFG_DSM0_CR17 0x40005891u +#define CYDEV_ANAIF_CFG_DSM0_REF0 0x40005892u +#define CYDEV_ANAIF_CFG_DSM0_REF1 0x40005893u +#define CYDEV_ANAIF_CFG_DSM0_REF2 0x40005894u +#define CYDEV_ANAIF_CFG_DSM0_REF3 0x40005895u +#define CYDEV_ANAIF_CFG_DSM0_DEM0 0x40005896u +#define CYDEV_ANAIF_CFG_DSM0_DEM1 0x40005897u +#define CYDEV_ANAIF_CFG_DSM0_TST0 0x40005898u +#define CYDEV_ANAIF_CFG_DSM0_TST1 0x40005899u +#define CYDEV_ANAIF_CFG_DSM0_BUF0 0x4000589au +#define CYDEV_ANAIF_CFG_DSM0_BUF1 0x4000589bu +#define CYDEV_ANAIF_CFG_DSM0_BUF2 0x4000589cu +#define CYDEV_ANAIF_CFG_DSM0_BUF3 0x4000589du +#define CYDEV_ANAIF_CFG_DSM0_MISC 0x4000589eu +#define CYDEV_ANAIF_CFG_DSM0_RSVD1 0x4000589fu +#define CYDEV_ANAIF_CFG_SAR0_BASE 0x40005900u +#define CYDEV_ANAIF_CFG_SAR0_SIZE 0x00000007u +#define CYDEV_ANAIF_CFG_SAR0_CSR0 0x40005900u +#define CYDEV_ANAIF_CFG_SAR0_CSR1 0x40005901u +#define CYDEV_ANAIF_CFG_SAR0_CSR2 0x40005902u +#define CYDEV_ANAIF_CFG_SAR0_CSR3 0x40005903u +#define CYDEV_ANAIF_CFG_SAR0_CSR4 0x40005904u +#define CYDEV_ANAIF_CFG_SAR0_CSR5 0x40005905u +#define CYDEV_ANAIF_CFG_SAR0_CSR6 0x40005906u +#define CYDEV_ANAIF_CFG_SAR1_BASE 0x40005908u +#define CYDEV_ANAIF_CFG_SAR1_SIZE 0x00000007u +#define CYDEV_ANAIF_CFG_SAR1_CSR0 0x40005908u +#define CYDEV_ANAIF_CFG_SAR1_CSR1 0x40005909u +#define CYDEV_ANAIF_CFG_SAR1_CSR2 0x4000590au +#define CYDEV_ANAIF_CFG_SAR1_CSR3 0x4000590bu +#define CYDEV_ANAIF_CFG_SAR1_CSR4 0x4000590cu +#define CYDEV_ANAIF_CFG_SAR1_CSR5 0x4000590du +#define CYDEV_ANAIF_CFG_SAR1_CSR6 0x4000590eu +#define CYDEV_ANAIF_RT_BASE 0x40005a00u +#define CYDEV_ANAIF_RT_SIZE 0x00000162u +#define CYDEV_ANAIF_RT_SC0_BASE 0x40005a00u +#define CYDEV_ANAIF_RT_SC0_SIZE 0x0000000du +#define CYDEV_ANAIF_RT_SC0_SW0 0x40005a00u +#define CYDEV_ANAIF_RT_SC0_SW2 0x40005a02u +#define CYDEV_ANAIF_RT_SC0_SW3 0x40005a03u +#define CYDEV_ANAIF_RT_SC0_SW4 0x40005a04u +#define CYDEV_ANAIF_RT_SC0_SW6 0x40005a06u +#define CYDEV_ANAIF_RT_SC0_SW7 0x40005a07u +#define CYDEV_ANAIF_RT_SC0_SW8 0x40005a08u +#define CYDEV_ANAIF_RT_SC0_SW10 0x40005a0au +#define CYDEV_ANAIF_RT_SC0_CLK 0x40005a0bu +#define CYDEV_ANAIF_RT_SC0_BST 0x40005a0cu +#define CYDEV_ANAIF_RT_SC1_BASE 0x40005a10u +#define CYDEV_ANAIF_RT_SC1_SIZE 0x0000000du +#define CYDEV_ANAIF_RT_SC1_SW0 0x40005a10u +#define CYDEV_ANAIF_RT_SC1_SW2 0x40005a12u +#define CYDEV_ANAIF_RT_SC1_SW3 0x40005a13u +#define CYDEV_ANAIF_RT_SC1_SW4 0x40005a14u +#define CYDEV_ANAIF_RT_SC1_SW6 0x40005a16u +#define CYDEV_ANAIF_RT_SC1_SW7 0x40005a17u +#define CYDEV_ANAIF_RT_SC1_SW8 0x40005a18u +#define CYDEV_ANAIF_RT_SC1_SW10 0x40005a1au +#define CYDEV_ANAIF_RT_SC1_CLK 0x40005a1bu +#define CYDEV_ANAIF_RT_SC1_BST 0x40005a1cu +#define CYDEV_ANAIF_RT_SC2_BASE 0x40005a20u +#define CYDEV_ANAIF_RT_SC2_SIZE 0x0000000du +#define CYDEV_ANAIF_RT_SC2_SW0 0x40005a20u +#define CYDEV_ANAIF_RT_SC2_SW2 0x40005a22u +#define CYDEV_ANAIF_RT_SC2_SW3 0x40005a23u +#define CYDEV_ANAIF_RT_SC2_SW4 0x40005a24u +#define CYDEV_ANAIF_RT_SC2_SW6 0x40005a26u +#define CYDEV_ANAIF_RT_SC2_SW7 0x40005a27u +#define CYDEV_ANAIF_RT_SC2_SW8 0x40005a28u +#define CYDEV_ANAIF_RT_SC2_SW10 0x40005a2au +#define CYDEV_ANAIF_RT_SC2_CLK 0x40005a2bu +#define CYDEV_ANAIF_RT_SC2_BST 0x40005a2cu +#define CYDEV_ANAIF_RT_SC3_BASE 0x40005a30u +#define CYDEV_ANAIF_RT_SC3_SIZE 0x0000000du +#define CYDEV_ANAIF_RT_SC3_SW0 0x40005a30u +#define CYDEV_ANAIF_RT_SC3_SW2 0x40005a32u +#define CYDEV_ANAIF_RT_SC3_SW3 0x40005a33u +#define CYDEV_ANAIF_RT_SC3_SW4 0x40005a34u +#define CYDEV_ANAIF_RT_SC3_SW6 0x40005a36u +#define CYDEV_ANAIF_RT_SC3_SW7 0x40005a37u +#define CYDEV_ANAIF_RT_SC3_SW8 0x40005a38u +#define CYDEV_ANAIF_RT_SC3_SW10 0x40005a3au +#define CYDEV_ANAIF_RT_SC3_CLK 0x40005a3bu +#define CYDEV_ANAIF_RT_SC3_BST 0x40005a3cu +#define CYDEV_ANAIF_RT_DAC0_BASE 0x40005a80u +#define CYDEV_ANAIF_RT_DAC0_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_DAC0_SW0 0x40005a80u +#define CYDEV_ANAIF_RT_DAC0_SW2 0x40005a82u +#define CYDEV_ANAIF_RT_DAC0_SW3 0x40005a83u +#define CYDEV_ANAIF_RT_DAC0_SW4 0x40005a84u +#define CYDEV_ANAIF_RT_DAC0_STROBE 0x40005a87u +#define CYDEV_ANAIF_RT_DAC1_BASE 0x40005a88u +#define CYDEV_ANAIF_RT_DAC1_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_DAC1_SW0 0x40005a88u +#define CYDEV_ANAIF_RT_DAC1_SW2 0x40005a8au +#define CYDEV_ANAIF_RT_DAC1_SW3 0x40005a8bu +#define CYDEV_ANAIF_RT_DAC1_SW4 0x40005a8cu +#define CYDEV_ANAIF_RT_DAC1_STROBE 0x40005a8fu +#define CYDEV_ANAIF_RT_DAC2_BASE 0x40005a90u +#define CYDEV_ANAIF_RT_DAC2_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_DAC2_SW0 0x40005a90u +#define CYDEV_ANAIF_RT_DAC2_SW2 0x40005a92u +#define CYDEV_ANAIF_RT_DAC2_SW3 0x40005a93u +#define CYDEV_ANAIF_RT_DAC2_SW4 0x40005a94u +#define CYDEV_ANAIF_RT_DAC2_STROBE 0x40005a97u +#define CYDEV_ANAIF_RT_DAC3_BASE 0x40005a98u +#define CYDEV_ANAIF_RT_DAC3_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_DAC3_SW0 0x40005a98u +#define CYDEV_ANAIF_RT_DAC3_SW2 0x40005a9au +#define CYDEV_ANAIF_RT_DAC3_SW3 0x40005a9bu +#define CYDEV_ANAIF_RT_DAC3_SW4 0x40005a9cu +#define CYDEV_ANAIF_RT_DAC3_STROBE 0x40005a9fu +#define CYDEV_ANAIF_RT_CMP0_BASE 0x40005ac0u +#define CYDEV_ANAIF_RT_CMP0_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_CMP0_SW0 0x40005ac0u +#define CYDEV_ANAIF_RT_CMP0_SW2 0x40005ac2u +#define CYDEV_ANAIF_RT_CMP0_SW3 0x40005ac3u +#define CYDEV_ANAIF_RT_CMP0_SW4 0x40005ac4u +#define CYDEV_ANAIF_RT_CMP0_SW6 0x40005ac6u +#define CYDEV_ANAIF_RT_CMP0_CLK 0x40005ac7u +#define CYDEV_ANAIF_RT_CMP1_BASE 0x40005ac8u +#define CYDEV_ANAIF_RT_CMP1_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_CMP1_SW0 0x40005ac8u +#define CYDEV_ANAIF_RT_CMP1_SW2 0x40005acau +#define CYDEV_ANAIF_RT_CMP1_SW3 0x40005acbu +#define CYDEV_ANAIF_RT_CMP1_SW4 0x40005accu +#define CYDEV_ANAIF_RT_CMP1_SW6 0x40005aceu +#define CYDEV_ANAIF_RT_CMP1_CLK 0x40005acfu +#define CYDEV_ANAIF_RT_CMP2_BASE 0x40005ad0u +#define CYDEV_ANAIF_RT_CMP2_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_CMP2_SW0 0x40005ad0u +#define CYDEV_ANAIF_RT_CMP2_SW2 0x40005ad2u +#define CYDEV_ANAIF_RT_CMP2_SW3 0x40005ad3u +#define CYDEV_ANAIF_RT_CMP2_SW4 0x40005ad4u +#define CYDEV_ANAIF_RT_CMP2_SW6 0x40005ad6u +#define CYDEV_ANAIF_RT_CMP2_CLK 0x40005ad7u +#define CYDEV_ANAIF_RT_CMP3_BASE 0x40005ad8u +#define CYDEV_ANAIF_RT_CMP3_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_CMP3_SW0 0x40005ad8u +#define CYDEV_ANAIF_RT_CMP3_SW2 0x40005adau +#define CYDEV_ANAIF_RT_CMP3_SW3 0x40005adbu +#define CYDEV_ANAIF_RT_CMP3_SW4 0x40005adcu +#define CYDEV_ANAIF_RT_CMP3_SW6 0x40005adeu +#define CYDEV_ANAIF_RT_CMP3_CLK 0x40005adfu +#define CYDEV_ANAIF_RT_DSM0_BASE 0x40005b00u +#define CYDEV_ANAIF_RT_DSM0_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_DSM0_SW0 0x40005b00u +#define CYDEV_ANAIF_RT_DSM0_SW2 0x40005b02u +#define CYDEV_ANAIF_RT_DSM0_SW3 0x40005b03u +#define CYDEV_ANAIF_RT_DSM0_SW4 0x40005b04u +#define CYDEV_ANAIF_RT_DSM0_SW6 0x40005b06u +#define CYDEV_ANAIF_RT_DSM0_CLK 0x40005b07u +#define CYDEV_ANAIF_RT_SAR0_BASE 0x40005b20u +#define CYDEV_ANAIF_RT_SAR0_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_SAR0_SW0 0x40005b20u +#define CYDEV_ANAIF_RT_SAR0_SW2 0x40005b22u +#define CYDEV_ANAIF_RT_SAR0_SW3 0x40005b23u +#define CYDEV_ANAIF_RT_SAR0_SW4 0x40005b24u +#define CYDEV_ANAIF_RT_SAR0_SW6 0x40005b26u +#define CYDEV_ANAIF_RT_SAR0_CLK 0x40005b27u +#define CYDEV_ANAIF_RT_SAR1_BASE 0x40005b28u +#define CYDEV_ANAIF_RT_SAR1_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_SAR1_SW0 0x40005b28u +#define CYDEV_ANAIF_RT_SAR1_SW2 0x40005b2au +#define CYDEV_ANAIF_RT_SAR1_SW3 0x40005b2bu +#define CYDEV_ANAIF_RT_SAR1_SW4 0x40005b2cu +#define CYDEV_ANAIF_RT_SAR1_SW6 0x40005b2eu +#define CYDEV_ANAIF_RT_SAR1_CLK 0x40005b2fu +#define CYDEV_ANAIF_RT_OPAMP0_BASE 0x40005b40u +#define CYDEV_ANAIF_RT_OPAMP0_SIZE 0x00000002u +#define CYDEV_ANAIF_RT_OPAMP0_MX 0x40005b40u +#define CYDEV_ANAIF_RT_OPAMP0_SW 0x40005b41u +#define CYDEV_ANAIF_RT_OPAMP1_BASE 0x40005b42u +#define CYDEV_ANAIF_RT_OPAMP1_SIZE 0x00000002u +#define CYDEV_ANAIF_RT_OPAMP1_MX 0x40005b42u +#define CYDEV_ANAIF_RT_OPAMP1_SW 0x40005b43u +#define CYDEV_ANAIF_RT_OPAMP2_BASE 0x40005b44u +#define CYDEV_ANAIF_RT_OPAMP2_SIZE 0x00000002u +#define CYDEV_ANAIF_RT_OPAMP2_MX 0x40005b44u +#define CYDEV_ANAIF_RT_OPAMP2_SW 0x40005b45u +#define CYDEV_ANAIF_RT_OPAMP3_BASE 0x40005b46u +#define CYDEV_ANAIF_RT_OPAMP3_SIZE 0x00000002u +#define CYDEV_ANAIF_RT_OPAMP3_MX 0x40005b46u +#define CYDEV_ANAIF_RT_OPAMP3_SW 0x40005b47u +#define CYDEV_ANAIF_RT_LCDDAC_BASE 0x40005b50u +#define CYDEV_ANAIF_RT_LCDDAC_SIZE 0x00000005u +#define CYDEV_ANAIF_RT_LCDDAC_SW0 0x40005b50u +#define CYDEV_ANAIF_RT_LCDDAC_SW1 0x40005b51u +#define CYDEV_ANAIF_RT_LCDDAC_SW2 0x40005b52u +#define CYDEV_ANAIF_RT_LCDDAC_SW3 0x40005b53u +#define CYDEV_ANAIF_RT_LCDDAC_SW4 0x40005b54u +#define CYDEV_ANAIF_RT_SC_BASE 0x40005b56u +#define CYDEV_ANAIF_RT_SC_SIZE 0x00000001u +#define CYDEV_ANAIF_RT_SC_MISC 0x40005b56u +#define CYDEV_ANAIF_RT_BUS_BASE 0x40005b58u +#define CYDEV_ANAIF_RT_BUS_SIZE 0x00000004u +#define CYDEV_ANAIF_RT_BUS_SW0 0x40005b58u +#define CYDEV_ANAIF_RT_BUS_SW2 0x40005b5au +#define CYDEV_ANAIF_RT_BUS_SW3 0x40005b5bu +#define CYDEV_ANAIF_RT_DFT_BASE 0x40005b5cu +#define CYDEV_ANAIF_RT_DFT_SIZE 0x00000006u +#define CYDEV_ANAIF_RT_DFT_CR0 0x40005b5cu +#define CYDEV_ANAIF_RT_DFT_CR1 0x40005b5du +#define CYDEV_ANAIF_RT_DFT_CR2 0x40005b5eu +#define CYDEV_ANAIF_RT_DFT_CR3 0x40005b5fu +#define CYDEV_ANAIF_RT_DFT_CR4 0x40005b60u +#define CYDEV_ANAIF_RT_DFT_CR5 0x40005b61u +#define CYDEV_ANAIF_WRK_BASE 0x40005b80u +#define CYDEV_ANAIF_WRK_SIZE 0x00000029u +#define CYDEV_ANAIF_WRK_DAC0_BASE 0x40005b80u +#define CYDEV_ANAIF_WRK_DAC0_SIZE 0x00000001u +#define CYDEV_ANAIF_WRK_DAC0_D 0x40005b80u +#define CYDEV_ANAIF_WRK_DAC1_BASE 0x40005b81u +#define CYDEV_ANAIF_WRK_DAC1_SIZE 0x00000001u +#define CYDEV_ANAIF_WRK_DAC1_D 0x40005b81u +#define CYDEV_ANAIF_WRK_DAC2_BASE 0x40005b82u +#define CYDEV_ANAIF_WRK_DAC2_SIZE 0x00000001u +#define CYDEV_ANAIF_WRK_DAC2_D 0x40005b82u +#define CYDEV_ANAIF_WRK_DAC3_BASE 0x40005b83u +#define CYDEV_ANAIF_WRK_DAC3_SIZE 0x00000001u +#define CYDEV_ANAIF_WRK_DAC3_D 0x40005b83u +#define CYDEV_ANAIF_WRK_DSM0_BASE 0x40005b88u +#define CYDEV_ANAIF_WRK_DSM0_SIZE 0x00000002u +#define CYDEV_ANAIF_WRK_DSM0_OUT0 0x40005b88u +#define CYDEV_ANAIF_WRK_DSM0_OUT1 0x40005b89u +#define CYDEV_ANAIF_WRK_LUT_BASE 0x40005b90u +#define CYDEV_ANAIF_WRK_LUT_SIZE 0x00000005u +#define CYDEV_ANAIF_WRK_LUT_SR 0x40005b90u +#define CYDEV_ANAIF_WRK_LUT_WRK1 0x40005b91u +#define CYDEV_ANAIF_WRK_LUT_MSK 0x40005b92u +#define CYDEV_ANAIF_WRK_LUT_CLK 0x40005b93u +#define CYDEV_ANAIF_WRK_LUT_CPTR 0x40005b94u +#define CYDEV_ANAIF_WRK_CMP_BASE 0x40005b96u +#define CYDEV_ANAIF_WRK_CMP_SIZE 0x00000002u +#define CYDEV_ANAIF_WRK_CMP_WRK 0x40005b96u +#define CYDEV_ANAIF_WRK_CMP_TST 0x40005b97u +#define CYDEV_ANAIF_WRK_SC_BASE 0x40005b98u +#define CYDEV_ANAIF_WRK_SC_SIZE 0x00000005u +#define CYDEV_ANAIF_WRK_SC_SR 0x40005b98u +#define CYDEV_ANAIF_WRK_SC_WRK1 0x40005b99u +#define CYDEV_ANAIF_WRK_SC_MSK 0x40005b9au +#define CYDEV_ANAIF_WRK_SC_CMPINV 0x40005b9bu +#define CYDEV_ANAIF_WRK_SC_CPTR 0x40005b9cu +#define CYDEV_ANAIF_WRK_SAR0_BASE 0x40005ba0u +#define CYDEV_ANAIF_WRK_SAR0_SIZE 0x00000002u +#define CYDEV_ANAIF_WRK_SAR0_WRK0 0x40005ba0u +#define CYDEV_ANAIF_WRK_SAR0_WRK1 0x40005ba1u +#define CYDEV_ANAIF_WRK_SAR1_BASE 0x40005ba2u +#define CYDEV_ANAIF_WRK_SAR1_SIZE 0x00000002u +#define CYDEV_ANAIF_WRK_SAR1_WRK0 0x40005ba2u +#define CYDEV_ANAIF_WRK_SAR1_WRK1 0x40005ba3u +#define CYDEV_ANAIF_WRK_SARS_BASE 0x40005ba8u +#define CYDEV_ANAIF_WRK_SARS_SIZE 0x00000001u +#define CYDEV_ANAIF_WRK_SARS_SOF 0x40005ba8u +#define CYDEV_USB_BASE 0x40006000u +#define CYDEV_USB_SIZE 0x00000300u +#define CYDEV_USB_EP0_DR0 0x40006000u +#define CYDEV_USB_EP0_DR1 0x40006001u +#define CYDEV_USB_EP0_DR2 0x40006002u +#define CYDEV_USB_EP0_DR3 0x40006003u +#define CYDEV_USB_EP0_DR4 0x40006004u +#define CYDEV_USB_EP0_DR5 0x40006005u +#define CYDEV_USB_EP0_DR6 0x40006006u +#define CYDEV_USB_EP0_DR7 0x40006007u +#define CYDEV_USB_CR0 0x40006008u +#define CYDEV_USB_CR1 0x40006009u +#define CYDEV_USB_SIE_EP_INT_EN 0x4000600au +#define CYDEV_USB_SIE_EP_INT_SR 0x4000600bu +#define CYDEV_USB_SIE_EP1_BASE 0x4000600cu +#define CYDEV_USB_SIE_EP1_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP1_CNT0 0x4000600cu +#define CYDEV_USB_SIE_EP1_CNT1 0x4000600du +#define CYDEV_USB_SIE_EP1_CR0 0x4000600eu +#define CYDEV_USB_USBIO_CR0 0x40006010u +#define CYDEV_USB_USBIO_CR1 0x40006012u +#define CYDEV_USB_DYN_RECONFIG 0x40006014u +#define CYDEV_USB_SOF0 0x40006018u +#define CYDEV_USB_SOF1 0x40006019u +#define CYDEV_USB_SIE_EP2_BASE 0x4000601cu +#define CYDEV_USB_SIE_EP2_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP2_CNT0 0x4000601cu +#define CYDEV_USB_SIE_EP2_CNT1 0x4000601du +#define CYDEV_USB_SIE_EP2_CR0 0x4000601eu +#define CYDEV_USB_EP0_CR 0x40006028u +#define CYDEV_USB_EP0_CNT 0x40006029u +#define CYDEV_USB_SIE_EP3_BASE 0x4000602cu +#define CYDEV_USB_SIE_EP3_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP3_CNT0 0x4000602cu +#define CYDEV_USB_SIE_EP3_CNT1 0x4000602du +#define CYDEV_USB_SIE_EP3_CR0 0x4000602eu +#define CYDEV_USB_SIE_EP4_BASE 0x4000603cu +#define CYDEV_USB_SIE_EP4_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP4_CNT0 0x4000603cu +#define CYDEV_USB_SIE_EP4_CNT1 0x4000603du +#define CYDEV_USB_SIE_EP4_CR0 0x4000603eu +#define CYDEV_USB_SIE_EP5_BASE 0x4000604cu +#define CYDEV_USB_SIE_EP5_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP5_CNT0 0x4000604cu +#define CYDEV_USB_SIE_EP5_CNT1 0x4000604du +#define CYDEV_USB_SIE_EP5_CR0 0x4000604eu +#define CYDEV_USB_SIE_EP6_BASE 0x4000605cu +#define CYDEV_USB_SIE_EP6_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP6_CNT0 0x4000605cu +#define CYDEV_USB_SIE_EP6_CNT1 0x4000605du +#define CYDEV_USB_SIE_EP6_CR0 0x4000605eu +#define CYDEV_USB_SIE_EP7_BASE 0x4000606cu +#define CYDEV_USB_SIE_EP7_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP7_CNT0 0x4000606cu +#define CYDEV_USB_SIE_EP7_CNT1 0x4000606du +#define CYDEV_USB_SIE_EP7_CR0 0x4000606eu +#define CYDEV_USB_SIE_EP8_BASE 0x4000607cu +#define CYDEV_USB_SIE_EP8_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP8_CNT0 0x4000607cu +#define CYDEV_USB_SIE_EP8_CNT1 0x4000607du +#define CYDEV_USB_SIE_EP8_CR0 0x4000607eu +#define CYDEV_USB_ARB_EP1_BASE 0x40006080u +#define CYDEV_USB_ARB_EP1_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP1_CFG 0x40006080u +#define CYDEV_USB_ARB_EP1_INT_EN 0x40006081u +#define CYDEV_USB_ARB_EP1_SR 0x40006082u +#define CYDEV_USB_ARB_RW1_BASE 0x40006084u +#define CYDEV_USB_ARB_RW1_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW1_WA 0x40006084u +#define CYDEV_USB_ARB_RW1_WA_MSB 0x40006085u +#define CYDEV_USB_ARB_RW1_RA 0x40006086u +#define CYDEV_USB_ARB_RW1_RA_MSB 0x40006087u +#define CYDEV_USB_ARB_RW1_DR 0x40006088u +#define CYDEV_USB_BUF_SIZE 0x4000608cu +#define CYDEV_USB_EP_ACTIVE 0x4000608eu +#define CYDEV_USB_EP_TYPE 0x4000608fu +#define CYDEV_USB_ARB_EP2_BASE 0x40006090u +#define CYDEV_USB_ARB_EP2_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP2_CFG 0x40006090u +#define CYDEV_USB_ARB_EP2_INT_EN 0x40006091u +#define CYDEV_USB_ARB_EP2_SR 0x40006092u +#define CYDEV_USB_ARB_RW2_BASE 0x40006094u +#define CYDEV_USB_ARB_RW2_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW2_WA 0x40006094u +#define CYDEV_USB_ARB_RW2_WA_MSB 0x40006095u +#define CYDEV_USB_ARB_RW2_RA 0x40006096u +#define CYDEV_USB_ARB_RW2_RA_MSB 0x40006097u +#define CYDEV_USB_ARB_RW2_DR 0x40006098u +#define CYDEV_USB_ARB_CFG 0x4000609cu +#define CYDEV_USB_USB_CLK_EN 0x4000609du +#define CYDEV_USB_ARB_INT_EN 0x4000609eu +#define CYDEV_USB_ARB_INT_SR 0x4000609fu +#define CYDEV_USB_ARB_EP3_BASE 0x400060a0u +#define CYDEV_USB_ARB_EP3_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP3_CFG 0x400060a0u +#define CYDEV_USB_ARB_EP3_INT_EN 0x400060a1u +#define CYDEV_USB_ARB_EP3_SR 0x400060a2u +#define CYDEV_USB_ARB_RW3_BASE 0x400060a4u +#define CYDEV_USB_ARB_RW3_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW3_WA 0x400060a4u +#define CYDEV_USB_ARB_RW3_WA_MSB 0x400060a5u +#define CYDEV_USB_ARB_RW3_RA 0x400060a6u +#define CYDEV_USB_ARB_RW3_RA_MSB 0x400060a7u +#define CYDEV_USB_ARB_RW3_DR 0x400060a8u +#define CYDEV_USB_CWA 0x400060acu +#define CYDEV_USB_CWA_MSB 0x400060adu +#define CYDEV_USB_ARB_EP4_BASE 0x400060b0u +#define CYDEV_USB_ARB_EP4_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP4_CFG 0x400060b0u +#define CYDEV_USB_ARB_EP4_INT_EN 0x400060b1u +#define CYDEV_USB_ARB_EP4_SR 0x400060b2u +#define CYDEV_USB_ARB_RW4_BASE 0x400060b4u +#define CYDEV_USB_ARB_RW4_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW4_WA 0x400060b4u +#define CYDEV_USB_ARB_RW4_WA_MSB 0x400060b5u +#define CYDEV_USB_ARB_RW4_RA 0x400060b6u +#define CYDEV_USB_ARB_RW4_RA_MSB 0x400060b7u +#define CYDEV_USB_ARB_RW4_DR 0x400060b8u +#define CYDEV_USB_DMA_THRES 0x400060bcu +#define CYDEV_USB_DMA_THRES_MSB 0x400060bdu +#define CYDEV_USB_ARB_EP5_BASE 0x400060c0u +#define CYDEV_USB_ARB_EP5_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP5_CFG 0x400060c0u +#define CYDEV_USB_ARB_EP5_INT_EN 0x400060c1u +#define CYDEV_USB_ARB_EP5_SR 0x400060c2u +#define CYDEV_USB_ARB_RW5_BASE 0x400060c4u +#define CYDEV_USB_ARB_RW5_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW5_WA 0x400060c4u +#define CYDEV_USB_ARB_RW5_WA_MSB 0x400060c5u +#define CYDEV_USB_ARB_RW5_RA 0x400060c6u +#define CYDEV_USB_ARB_RW5_RA_MSB 0x400060c7u +#define CYDEV_USB_ARB_RW5_DR 0x400060c8u +#define CYDEV_USB_BUS_RST_CNT 0x400060ccu +#define CYDEV_USB_ARB_EP6_BASE 0x400060d0u +#define CYDEV_USB_ARB_EP6_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP6_CFG 0x400060d0u +#define CYDEV_USB_ARB_EP6_INT_EN 0x400060d1u +#define CYDEV_USB_ARB_EP6_SR 0x400060d2u +#define CYDEV_USB_ARB_RW6_BASE 0x400060d4u +#define CYDEV_USB_ARB_RW6_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW6_WA 0x400060d4u +#define CYDEV_USB_ARB_RW6_WA_MSB 0x400060d5u +#define CYDEV_USB_ARB_RW6_RA 0x400060d6u +#define CYDEV_USB_ARB_RW6_RA_MSB 0x400060d7u +#define CYDEV_USB_ARB_RW6_DR 0x400060d8u +#define CYDEV_USB_ARB_EP7_BASE 0x400060e0u +#define CYDEV_USB_ARB_EP7_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP7_CFG 0x400060e0u +#define CYDEV_USB_ARB_EP7_INT_EN 0x400060e1u +#define CYDEV_USB_ARB_EP7_SR 0x400060e2u +#define CYDEV_USB_ARB_RW7_BASE 0x400060e4u +#define CYDEV_USB_ARB_RW7_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW7_WA 0x400060e4u +#define CYDEV_USB_ARB_RW7_WA_MSB 0x400060e5u +#define CYDEV_USB_ARB_RW7_RA 0x400060e6u +#define CYDEV_USB_ARB_RW7_RA_MSB 0x400060e7u +#define CYDEV_USB_ARB_RW7_DR 0x400060e8u +#define CYDEV_USB_ARB_EP8_BASE 0x400060f0u +#define CYDEV_USB_ARB_EP8_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP8_CFG 0x400060f0u +#define CYDEV_USB_ARB_EP8_INT_EN 0x400060f1u +#define CYDEV_USB_ARB_EP8_SR 0x400060f2u +#define CYDEV_USB_ARB_RW8_BASE 0x400060f4u +#define CYDEV_USB_ARB_RW8_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW8_WA 0x400060f4u +#define CYDEV_USB_ARB_RW8_WA_MSB 0x400060f5u +#define CYDEV_USB_ARB_RW8_RA 0x400060f6u +#define CYDEV_USB_ARB_RW8_RA_MSB 0x400060f7u +#define CYDEV_USB_ARB_RW8_DR 0x400060f8u +#define CYDEV_USB_MEM_BASE 0x40006100u +#define CYDEV_USB_MEM_SIZE 0x00000200u +#define CYDEV_USB_MEM_DATA_MBASE 0x40006100u +#define CYDEV_USB_MEM_DATA_MSIZE 0x00000200u +#define CYDEV_UWRK_BASE 0x40006400u +#define CYDEV_UWRK_SIZE 0x00000b60u +#define CYDEV_UWRK_UWRK8_BASE 0x40006400u +#define CYDEV_UWRK_UWRK8_SIZE 0x000003b0u +#define CYDEV_UWRK_UWRK8_B0_BASE 0x40006400u +#define CYDEV_UWRK_UWRK8_B0_SIZE 0x000000b0u +#define CYDEV_UWRK_UWRK8_B0_UDB00_A0 0x40006400u +#define CYDEV_UWRK_UWRK8_B0_UDB01_A0 0x40006401u +#define CYDEV_UWRK_UWRK8_B0_UDB02_A0 0x40006402u +#define CYDEV_UWRK_UWRK8_B0_UDB03_A0 0x40006403u +#define CYDEV_UWRK_UWRK8_B0_UDB04_A0 0x40006404u +#define CYDEV_UWRK_UWRK8_B0_UDB05_A0 0x40006405u +#define CYDEV_UWRK_UWRK8_B0_UDB06_A0 0x40006406u +#define CYDEV_UWRK_UWRK8_B0_UDB07_A0 0x40006407u +#define CYDEV_UWRK_UWRK8_B0_UDB08_A0 0x40006408u +#define CYDEV_UWRK_UWRK8_B0_UDB09_A0 0x40006409u +#define CYDEV_UWRK_UWRK8_B0_UDB10_A0 0x4000640au +#define CYDEV_UWRK_UWRK8_B0_UDB11_A0 0x4000640bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_A0 0x4000640cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_A0 0x4000640du +#define CYDEV_UWRK_UWRK8_B0_UDB14_A0 0x4000640eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_A0 0x4000640fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_A1 0x40006410u +#define CYDEV_UWRK_UWRK8_B0_UDB01_A1 0x40006411u +#define CYDEV_UWRK_UWRK8_B0_UDB02_A1 0x40006412u +#define CYDEV_UWRK_UWRK8_B0_UDB03_A1 0x40006413u +#define CYDEV_UWRK_UWRK8_B0_UDB04_A1 0x40006414u +#define CYDEV_UWRK_UWRK8_B0_UDB05_A1 0x40006415u +#define CYDEV_UWRK_UWRK8_B0_UDB06_A1 0x40006416u +#define CYDEV_UWRK_UWRK8_B0_UDB07_A1 0x40006417u +#define CYDEV_UWRK_UWRK8_B0_UDB08_A1 0x40006418u +#define CYDEV_UWRK_UWRK8_B0_UDB09_A1 0x40006419u +#define CYDEV_UWRK_UWRK8_B0_UDB10_A1 0x4000641au +#define CYDEV_UWRK_UWRK8_B0_UDB11_A1 0x4000641bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_A1 0x4000641cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_A1 0x4000641du +#define CYDEV_UWRK_UWRK8_B0_UDB14_A1 0x4000641eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_A1 0x4000641fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_D0 0x40006420u +#define CYDEV_UWRK_UWRK8_B0_UDB01_D0 0x40006421u +#define CYDEV_UWRK_UWRK8_B0_UDB02_D0 0x40006422u +#define CYDEV_UWRK_UWRK8_B0_UDB03_D0 0x40006423u +#define CYDEV_UWRK_UWRK8_B0_UDB04_D0 0x40006424u +#define CYDEV_UWRK_UWRK8_B0_UDB05_D0 0x40006425u +#define CYDEV_UWRK_UWRK8_B0_UDB06_D0 0x40006426u +#define CYDEV_UWRK_UWRK8_B0_UDB07_D0 0x40006427u +#define CYDEV_UWRK_UWRK8_B0_UDB08_D0 0x40006428u +#define CYDEV_UWRK_UWRK8_B0_UDB09_D0 0x40006429u +#define CYDEV_UWRK_UWRK8_B0_UDB10_D0 0x4000642au +#define CYDEV_UWRK_UWRK8_B0_UDB11_D0 0x4000642bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_D0 0x4000642cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_D0 0x4000642du +#define CYDEV_UWRK_UWRK8_B0_UDB14_D0 0x4000642eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_D0 0x4000642fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_D1 0x40006430u +#define CYDEV_UWRK_UWRK8_B0_UDB01_D1 0x40006431u +#define CYDEV_UWRK_UWRK8_B0_UDB02_D1 0x40006432u +#define CYDEV_UWRK_UWRK8_B0_UDB03_D1 0x40006433u +#define CYDEV_UWRK_UWRK8_B0_UDB04_D1 0x40006434u +#define CYDEV_UWRK_UWRK8_B0_UDB05_D1 0x40006435u +#define CYDEV_UWRK_UWRK8_B0_UDB06_D1 0x40006436u +#define CYDEV_UWRK_UWRK8_B0_UDB07_D1 0x40006437u +#define CYDEV_UWRK_UWRK8_B0_UDB08_D1 0x40006438u +#define CYDEV_UWRK_UWRK8_B0_UDB09_D1 0x40006439u +#define CYDEV_UWRK_UWRK8_B0_UDB10_D1 0x4000643au +#define CYDEV_UWRK_UWRK8_B0_UDB11_D1 0x4000643bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_D1 0x4000643cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_D1 0x4000643du +#define CYDEV_UWRK_UWRK8_B0_UDB14_D1 0x4000643eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_D1 0x4000643fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_F0 0x40006440u +#define CYDEV_UWRK_UWRK8_B0_UDB01_F0 0x40006441u +#define CYDEV_UWRK_UWRK8_B0_UDB02_F0 0x40006442u +#define CYDEV_UWRK_UWRK8_B0_UDB03_F0 0x40006443u +#define CYDEV_UWRK_UWRK8_B0_UDB04_F0 0x40006444u +#define CYDEV_UWRK_UWRK8_B0_UDB05_F0 0x40006445u +#define CYDEV_UWRK_UWRK8_B0_UDB06_F0 0x40006446u +#define CYDEV_UWRK_UWRK8_B0_UDB07_F0 0x40006447u +#define CYDEV_UWRK_UWRK8_B0_UDB08_F0 0x40006448u +#define CYDEV_UWRK_UWRK8_B0_UDB09_F0 0x40006449u +#define CYDEV_UWRK_UWRK8_B0_UDB10_F0 0x4000644au +#define CYDEV_UWRK_UWRK8_B0_UDB11_F0 0x4000644bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_F0 0x4000644cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_F0 0x4000644du +#define CYDEV_UWRK_UWRK8_B0_UDB14_F0 0x4000644eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_F0 0x4000644fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_F1 0x40006450u +#define CYDEV_UWRK_UWRK8_B0_UDB01_F1 0x40006451u +#define CYDEV_UWRK_UWRK8_B0_UDB02_F1 0x40006452u +#define CYDEV_UWRK_UWRK8_B0_UDB03_F1 0x40006453u +#define CYDEV_UWRK_UWRK8_B0_UDB04_F1 0x40006454u +#define CYDEV_UWRK_UWRK8_B0_UDB05_F1 0x40006455u +#define CYDEV_UWRK_UWRK8_B0_UDB06_F1 0x40006456u +#define CYDEV_UWRK_UWRK8_B0_UDB07_F1 0x40006457u +#define CYDEV_UWRK_UWRK8_B0_UDB08_F1 0x40006458u +#define CYDEV_UWRK_UWRK8_B0_UDB09_F1 0x40006459u +#define CYDEV_UWRK_UWRK8_B0_UDB10_F1 0x4000645au +#define CYDEV_UWRK_UWRK8_B0_UDB11_F1 0x4000645bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_F1 0x4000645cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_F1 0x4000645du +#define CYDEV_UWRK_UWRK8_B0_UDB14_F1 0x4000645eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_F1 0x4000645fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_ST 0x40006460u +#define CYDEV_UWRK_UWRK8_B0_UDB01_ST 0x40006461u +#define CYDEV_UWRK_UWRK8_B0_UDB02_ST 0x40006462u +#define CYDEV_UWRK_UWRK8_B0_UDB03_ST 0x40006463u +#define CYDEV_UWRK_UWRK8_B0_UDB04_ST 0x40006464u +#define CYDEV_UWRK_UWRK8_B0_UDB05_ST 0x40006465u +#define CYDEV_UWRK_UWRK8_B0_UDB06_ST 0x40006466u +#define CYDEV_UWRK_UWRK8_B0_UDB07_ST 0x40006467u +#define CYDEV_UWRK_UWRK8_B0_UDB08_ST 0x40006468u +#define CYDEV_UWRK_UWRK8_B0_UDB09_ST 0x40006469u +#define CYDEV_UWRK_UWRK8_B0_UDB10_ST 0x4000646au +#define CYDEV_UWRK_UWRK8_B0_UDB11_ST 0x4000646bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_ST 0x4000646cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_ST 0x4000646du +#define CYDEV_UWRK_UWRK8_B0_UDB14_ST 0x4000646eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_ST 0x4000646fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_CTL 0x40006470u +#define CYDEV_UWRK_UWRK8_B0_UDB01_CTL 0x40006471u +#define CYDEV_UWRK_UWRK8_B0_UDB02_CTL 0x40006472u +#define CYDEV_UWRK_UWRK8_B0_UDB03_CTL 0x40006473u +#define CYDEV_UWRK_UWRK8_B0_UDB04_CTL 0x40006474u +#define CYDEV_UWRK_UWRK8_B0_UDB05_CTL 0x40006475u +#define CYDEV_UWRK_UWRK8_B0_UDB06_CTL 0x40006476u +#define CYDEV_UWRK_UWRK8_B0_UDB07_CTL 0x40006477u +#define CYDEV_UWRK_UWRK8_B0_UDB08_CTL 0x40006478u +#define CYDEV_UWRK_UWRK8_B0_UDB09_CTL 0x40006479u +#define CYDEV_UWRK_UWRK8_B0_UDB10_CTL 0x4000647au +#define CYDEV_UWRK_UWRK8_B0_UDB11_CTL 0x4000647bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_CTL 0x4000647cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_CTL 0x4000647du +#define CYDEV_UWRK_UWRK8_B0_UDB14_CTL 0x4000647eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_CTL 0x4000647fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_MSK 0x40006480u +#define CYDEV_UWRK_UWRK8_B0_UDB01_MSK 0x40006481u +#define CYDEV_UWRK_UWRK8_B0_UDB02_MSK 0x40006482u +#define CYDEV_UWRK_UWRK8_B0_UDB03_MSK 0x40006483u +#define CYDEV_UWRK_UWRK8_B0_UDB04_MSK 0x40006484u +#define CYDEV_UWRK_UWRK8_B0_UDB05_MSK 0x40006485u +#define CYDEV_UWRK_UWRK8_B0_UDB06_MSK 0x40006486u +#define CYDEV_UWRK_UWRK8_B0_UDB07_MSK 0x40006487u +#define CYDEV_UWRK_UWRK8_B0_UDB08_MSK 0x40006488u +#define CYDEV_UWRK_UWRK8_B0_UDB09_MSK 0x40006489u +#define CYDEV_UWRK_UWRK8_B0_UDB10_MSK 0x4000648au +#define CYDEV_UWRK_UWRK8_B0_UDB11_MSK 0x4000648bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_MSK 0x4000648cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_MSK 0x4000648du +#define CYDEV_UWRK_UWRK8_B0_UDB14_MSK 0x4000648eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_MSK 0x4000648fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_ACTL 0x40006490u +#define CYDEV_UWRK_UWRK8_B0_UDB01_ACTL 0x40006491u +#define CYDEV_UWRK_UWRK8_B0_UDB02_ACTL 0x40006492u +#define CYDEV_UWRK_UWRK8_B0_UDB03_ACTL 0x40006493u +#define CYDEV_UWRK_UWRK8_B0_UDB04_ACTL 0x40006494u +#define CYDEV_UWRK_UWRK8_B0_UDB05_ACTL 0x40006495u +#define CYDEV_UWRK_UWRK8_B0_UDB06_ACTL 0x40006496u +#define CYDEV_UWRK_UWRK8_B0_UDB07_ACTL 0x40006497u +#define CYDEV_UWRK_UWRK8_B0_UDB08_ACTL 0x40006498u +#define CYDEV_UWRK_UWRK8_B0_UDB09_ACTL 0x40006499u +#define CYDEV_UWRK_UWRK8_B0_UDB10_ACTL 0x4000649au +#define CYDEV_UWRK_UWRK8_B0_UDB11_ACTL 0x4000649bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_ACTL 0x4000649cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_ACTL 0x4000649du +#define CYDEV_UWRK_UWRK8_B0_UDB14_ACTL 0x4000649eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_ACTL 0x4000649fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_MC 0x400064a0u +#define CYDEV_UWRK_UWRK8_B0_UDB01_MC 0x400064a1u +#define CYDEV_UWRK_UWRK8_B0_UDB02_MC 0x400064a2u +#define CYDEV_UWRK_UWRK8_B0_UDB03_MC 0x400064a3u +#define CYDEV_UWRK_UWRK8_B0_UDB04_MC 0x400064a4u +#define CYDEV_UWRK_UWRK8_B0_UDB05_MC 0x400064a5u +#define CYDEV_UWRK_UWRK8_B0_UDB06_MC 0x400064a6u +#define CYDEV_UWRK_UWRK8_B0_UDB07_MC 0x400064a7u +#define CYDEV_UWRK_UWRK8_B0_UDB08_MC 0x400064a8u +#define CYDEV_UWRK_UWRK8_B0_UDB09_MC 0x400064a9u +#define CYDEV_UWRK_UWRK8_B0_UDB10_MC 0x400064aau +#define CYDEV_UWRK_UWRK8_B0_UDB11_MC 0x400064abu +#define CYDEV_UWRK_UWRK8_B0_UDB12_MC 0x400064acu +#define CYDEV_UWRK_UWRK8_B0_UDB13_MC 0x400064adu +#define CYDEV_UWRK_UWRK8_B0_UDB14_MC 0x400064aeu +#define CYDEV_UWRK_UWRK8_B0_UDB15_MC 0x400064afu +#define CYDEV_UWRK_UWRK8_B1_BASE 0x40006500u +#define CYDEV_UWRK_UWRK8_B1_SIZE 0x000000b0u +#define CYDEV_UWRK_UWRK8_B1_UDB04_A0 0x40006504u +#define CYDEV_UWRK_UWRK8_B1_UDB05_A0 0x40006505u +#define CYDEV_UWRK_UWRK8_B1_UDB06_A0 0x40006506u +#define CYDEV_UWRK_UWRK8_B1_UDB07_A0 0x40006507u +#define CYDEV_UWRK_UWRK8_B1_UDB08_A0 0x40006508u +#define CYDEV_UWRK_UWRK8_B1_UDB09_A0 0x40006509u +#define CYDEV_UWRK_UWRK8_B1_UDB10_A0 0x4000650au +#define CYDEV_UWRK_UWRK8_B1_UDB11_A0 0x4000650bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_A1 0x40006514u +#define CYDEV_UWRK_UWRK8_B1_UDB05_A1 0x40006515u +#define CYDEV_UWRK_UWRK8_B1_UDB06_A1 0x40006516u +#define CYDEV_UWRK_UWRK8_B1_UDB07_A1 0x40006517u +#define CYDEV_UWRK_UWRK8_B1_UDB08_A1 0x40006518u +#define CYDEV_UWRK_UWRK8_B1_UDB09_A1 0x40006519u +#define CYDEV_UWRK_UWRK8_B1_UDB10_A1 0x4000651au +#define CYDEV_UWRK_UWRK8_B1_UDB11_A1 0x4000651bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_D0 0x40006524u +#define CYDEV_UWRK_UWRK8_B1_UDB05_D0 0x40006525u +#define CYDEV_UWRK_UWRK8_B1_UDB06_D0 0x40006526u +#define CYDEV_UWRK_UWRK8_B1_UDB07_D0 0x40006527u +#define CYDEV_UWRK_UWRK8_B1_UDB08_D0 0x40006528u +#define CYDEV_UWRK_UWRK8_B1_UDB09_D0 0x40006529u +#define CYDEV_UWRK_UWRK8_B1_UDB10_D0 0x4000652au +#define CYDEV_UWRK_UWRK8_B1_UDB11_D0 0x4000652bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_D1 0x40006534u +#define CYDEV_UWRK_UWRK8_B1_UDB05_D1 0x40006535u +#define CYDEV_UWRK_UWRK8_B1_UDB06_D1 0x40006536u +#define CYDEV_UWRK_UWRK8_B1_UDB07_D1 0x40006537u +#define CYDEV_UWRK_UWRK8_B1_UDB08_D1 0x40006538u +#define CYDEV_UWRK_UWRK8_B1_UDB09_D1 0x40006539u +#define CYDEV_UWRK_UWRK8_B1_UDB10_D1 0x4000653au +#define CYDEV_UWRK_UWRK8_B1_UDB11_D1 0x4000653bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_F0 0x40006544u +#define CYDEV_UWRK_UWRK8_B1_UDB05_F0 0x40006545u +#define CYDEV_UWRK_UWRK8_B1_UDB06_F0 0x40006546u +#define CYDEV_UWRK_UWRK8_B1_UDB07_F0 0x40006547u +#define CYDEV_UWRK_UWRK8_B1_UDB08_F0 0x40006548u +#define CYDEV_UWRK_UWRK8_B1_UDB09_F0 0x40006549u +#define CYDEV_UWRK_UWRK8_B1_UDB10_F0 0x4000654au +#define CYDEV_UWRK_UWRK8_B1_UDB11_F0 0x4000654bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_F1 0x40006554u +#define CYDEV_UWRK_UWRK8_B1_UDB05_F1 0x40006555u +#define CYDEV_UWRK_UWRK8_B1_UDB06_F1 0x40006556u +#define CYDEV_UWRK_UWRK8_B1_UDB07_F1 0x40006557u +#define CYDEV_UWRK_UWRK8_B1_UDB08_F1 0x40006558u +#define CYDEV_UWRK_UWRK8_B1_UDB09_F1 0x40006559u +#define CYDEV_UWRK_UWRK8_B1_UDB10_F1 0x4000655au +#define CYDEV_UWRK_UWRK8_B1_UDB11_F1 0x4000655bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_ST 0x40006564u +#define CYDEV_UWRK_UWRK8_B1_UDB05_ST 0x40006565u +#define CYDEV_UWRK_UWRK8_B1_UDB06_ST 0x40006566u +#define CYDEV_UWRK_UWRK8_B1_UDB07_ST 0x40006567u +#define CYDEV_UWRK_UWRK8_B1_UDB08_ST 0x40006568u +#define CYDEV_UWRK_UWRK8_B1_UDB09_ST 0x40006569u +#define CYDEV_UWRK_UWRK8_B1_UDB10_ST 0x4000656au +#define CYDEV_UWRK_UWRK8_B1_UDB11_ST 0x4000656bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_CTL 0x40006574u +#define CYDEV_UWRK_UWRK8_B1_UDB05_CTL 0x40006575u +#define CYDEV_UWRK_UWRK8_B1_UDB06_CTL 0x40006576u +#define CYDEV_UWRK_UWRK8_B1_UDB07_CTL 0x40006577u +#define CYDEV_UWRK_UWRK8_B1_UDB08_CTL 0x40006578u +#define CYDEV_UWRK_UWRK8_B1_UDB09_CTL 0x40006579u +#define CYDEV_UWRK_UWRK8_B1_UDB10_CTL 0x4000657au +#define CYDEV_UWRK_UWRK8_B1_UDB11_CTL 0x4000657bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_MSK 0x40006584u +#define CYDEV_UWRK_UWRK8_B1_UDB05_MSK 0x40006585u +#define CYDEV_UWRK_UWRK8_B1_UDB06_MSK 0x40006586u +#define CYDEV_UWRK_UWRK8_B1_UDB07_MSK 0x40006587u +#define CYDEV_UWRK_UWRK8_B1_UDB08_MSK 0x40006588u +#define CYDEV_UWRK_UWRK8_B1_UDB09_MSK 0x40006589u +#define CYDEV_UWRK_UWRK8_B1_UDB10_MSK 0x4000658au +#define CYDEV_UWRK_UWRK8_B1_UDB11_MSK 0x4000658bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_ACTL 0x40006594u +#define CYDEV_UWRK_UWRK8_B1_UDB05_ACTL 0x40006595u +#define CYDEV_UWRK_UWRK8_B1_UDB06_ACTL 0x40006596u +#define CYDEV_UWRK_UWRK8_B1_UDB07_ACTL 0x40006597u +#define CYDEV_UWRK_UWRK8_B1_UDB08_ACTL 0x40006598u +#define CYDEV_UWRK_UWRK8_B1_UDB09_ACTL 0x40006599u +#define CYDEV_UWRK_UWRK8_B1_UDB10_ACTL 0x4000659au +#define CYDEV_UWRK_UWRK8_B1_UDB11_ACTL 0x4000659bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_MC 0x400065a4u +#define CYDEV_UWRK_UWRK8_B1_UDB05_MC 0x400065a5u +#define CYDEV_UWRK_UWRK8_B1_UDB06_MC 0x400065a6u +#define CYDEV_UWRK_UWRK8_B1_UDB07_MC 0x400065a7u +#define CYDEV_UWRK_UWRK8_B1_UDB08_MC 0x400065a8u +#define CYDEV_UWRK_UWRK8_B1_UDB09_MC 0x400065a9u +#define CYDEV_UWRK_UWRK8_B1_UDB10_MC 0x400065aau +#define CYDEV_UWRK_UWRK8_B1_UDB11_MC 0x400065abu +#define CYDEV_UWRK_UWRK16_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_SIZE 0x00000760u +#define CYDEV_UWRK_UWRK16_CAT_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_CAT_SIZE 0x00000760u +#define CYDEV_UWRK_UWRK16_CAT_B0_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_CAT_B0_SIZE 0x00000160u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1 0x40006800u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1 0x40006802u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1 0x40006804u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1 0x40006806u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1 0x40006808u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1 0x4000680au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1 0x4000680cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1 0x4000680eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1 0x40006810u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1 0x40006812u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1 0x40006814u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1 0x40006816u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1 0x40006818u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1 0x4000681au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1 0x4000681cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1 0x4000681eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1 0x40006840u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1 0x40006842u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1 0x40006844u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1 0x40006846u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1 0x40006848u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1 0x4000684au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1 0x4000684cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1 0x4000684eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1 0x40006850u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1 0x40006852u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1 0x40006854u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1 0x40006856u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1 0x40006858u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1 0x4000685au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1 0x4000685cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1 0x4000685eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1 0x40006880u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1 0x40006882u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1 0x40006884u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1 0x40006886u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1 0x40006888u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1 0x4000688au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1 0x4000688cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1 0x4000688eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1 0x40006890u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1 0x40006892u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1 0x40006894u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1 0x40006896u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1 0x40006898u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1 0x4000689au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1 0x4000689cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1 0x4000689eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL 0x400068c0u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL 0x400068c2u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL 0x400068c4u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL 0x400068c6u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL 0x400068c8u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL 0x400068cau +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL 0x400068ccu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL 0x400068ceu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL 0x400068d0u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL 0x400068d2u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL 0x400068d4u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL 0x400068d6u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL 0x400068d8u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL 0x400068dau +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL 0x400068dcu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL 0x400068deu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL 0x40006900u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL 0x40006902u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL 0x40006904u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL 0x40006906u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL 0x40006908u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL 0x4000690au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL 0x4000690cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL 0x4000690eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL 0x40006910u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL 0x40006912u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL 0x40006914u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL 0x40006916u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL 0x40006918u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL 0x4000691au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL 0x4000691cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL 0x4000691eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00 0x40006940u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00 0x40006942u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00 0x40006944u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00 0x40006946u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00 0x40006948u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00 0x4000694au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00 0x4000694cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00 0x4000694eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00 0x40006950u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00 0x40006952u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00 0x40006954u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00 0x40006956u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00 0x40006958u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00 0x4000695au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00 0x4000695cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00 0x4000695eu +#define CYDEV_UWRK_UWRK16_CAT_B1_BASE 0x40006a00u +#define CYDEV_UWRK_UWRK16_CAT_B1_SIZE 0x00000160u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1 0x40006a08u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1 0x40006a0au +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1 0x40006a0cu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1 0x40006a0eu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1 0x40006a10u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1 0x40006a12u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1 0x40006a14u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1 0x40006a16u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1 0x40006a48u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1 0x40006a4au +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1 0x40006a4cu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1 0x40006a4eu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1 0x40006a50u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1 0x40006a52u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1 0x40006a54u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1 0x40006a56u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1 0x40006a88u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1 0x40006a8au +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1 0x40006a8cu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1 0x40006a8eu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1 0x40006a90u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1 0x40006a92u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1 0x40006a94u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1 0x40006a96u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL 0x40006ac8u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL 0x40006acau +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL 0x40006accu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL 0x40006aceu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL 0x40006ad0u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL 0x40006ad2u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL 0x40006ad4u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL 0x40006ad6u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL 0x40006b08u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL 0x40006b0au +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL 0x40006b0cu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL 0x40006b0eu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL 0x40006b10u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL 0x40006b12u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL 0x40006b14u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL 0x40006b16u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00 0x40006b48u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00 0x40006b4au +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00 0x40006b4cu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00 0x40006b4eu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00 0x40006b50u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00 0x40006b52u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00 0x40006b54u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00 0x40006b56u +#define CYDEV_UWRK_UWRK16_DEF_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_DEF_SIZE 0x0000075eu +#define CYDEV_UWRK_UWRK16_DEF_B0_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_DEF_B0_SIZE 0x0000015eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0 0x40006800u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0 0x40006802u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0 0x40006804u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0 0x40006806u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0 0x40006808u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0 0x4000680au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0 0x4000680cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0 0x4000680eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0 0x40006810u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0 0x40006812u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0 0x40006814u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0 0x40006816u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0 0x40006818u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0 0x4000681au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0 0x4000681cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1 0x40006820u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1 0x40006822u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1 0x40006824u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1 0x40006826u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1 0x40006828u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1 0x4000682au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1 0x4000682cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1 0x4000682eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1 0x40006830u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1 0x40006832u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1 0x40006834u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1 0x40006836u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1 0x40006838u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1 0x4000683au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1 0x4000683cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0 0x40006840u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0 0x40006842u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0 0x40006844u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0 0x40006846u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0 0x40006848u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0 0x4000684au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0 0x4000684cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0 0x4000684eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0 0x40006850u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0 0x40006852u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0 0x40006854u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0 0x40006856u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0 0x40006858u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0 0x4000685au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0 0x4000685cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1 0x40006860u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1 0x40006862u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1 0x40006864u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1 0x40006866u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1 0x40006868u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1 0x4000686au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1 0x4000686cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1 0x4000686eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1 0x40006870u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1 0x40006872u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1 0x40006874u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1 0x40006876u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1 0x40006878u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1 0x4000687au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1 0x4000687cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0 0x40006880u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0 0x40006882u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0 0x40006884u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0 0x40006886u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0 0x40006888u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0 0x4000688au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0 0x4000688cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0 0x4000688eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0 0x40006890u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0 0x40006892u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0 0x40006894u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0 0x40006896u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0 0x40006898u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0 0x4000689au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0 0x4000689cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1 0x400068a0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1 0x400068a2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1 0x400068a4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1 0x400068a6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1 0x400068a8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1 0x400068aau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1 0x400068acu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1 0x400068aeu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1 0x400068b0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1 0x400068b2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1 0x400068b4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1 0x400068b6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1 0x400068b8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1 0x400068bau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1 0x400068bcu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST 0x400068c0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST 0x400068c2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST 0x400068c4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST 0x400068c6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST 0x400068c8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST 0x400068cau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST 0x400068ccu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST 0x400068ceu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST 0x400068d0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST 0x400068d2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST 0x400068d4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST 0x400068d6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST 0x400068d8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST 0x400068dau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST 0x400068dcu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL 0x400068e0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL 0x400068e2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL 0x400068e4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL 0x400068e6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL 0x400068e8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL 0x400068eau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL 0x400068ecu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL 0x400068eeu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL 0x400068f0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL 0x400068f2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL 0x400068f4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL 0x400068f6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL 0x400068f8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL 0x400068fau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL 0x400068fcu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK 0x40006900u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK 0x40006902u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK 0x40006904u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK 0x40006906u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK 0x40006908u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK 0x4000690au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK 0x4000690cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK 0x4000690eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK 0x40006910u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK 0x40006912u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK 0x40006914u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK 0x40006916u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK 0x40006918u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK 0x4000691au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK 0x4000691cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL 0x40006920u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL 0x40006922u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL 0x40006924u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL 0x40006926u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL 0x40006928u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL 0x4000692au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL 0x4000692cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL 0x4000692eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL 0x40006930u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL 0x40006932u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL 0x40006934u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL 0x40006936u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL 0x40006938u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL 0x4000693au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL 0x4000693cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC 0x40006940u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC 0x40006942u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC 0x40006944u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC 0x40006946u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC 0x40006948u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC 0x4000694au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC 0x4000694cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC 0x4000694eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC 0x40006950u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC 0x40006952u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC 0x40006954u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC 0x40006956u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC 0x40006958u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC 0x4000695au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC 0x4000695cu +#define CYDEV_UWRK_UWRK16_DEF_B1_BASE 0x40006a00u +#define CYDEV_UWRK_UWRK16_DEF_B1_SIZE 0x0000015eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0 0x40006a08u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0 0x40006a0au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0 0x40006a0cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0 0x40006a0eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0 0x40006a10u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0 0x40006a12u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0 0x40006a14u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0 0x40006a16u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1 0x40006a28u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1 0x40006a2au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1 0x40006a2cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1 0x40006a2eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1 0x40006a30u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1 0x40006a32u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1 0x40006a34u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1 0x40006a36u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0 0x40006a48u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0 0x40006a4au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0 0x40006a4cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0 0x40006a4eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0 0x40006a50u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0 0x40006a52u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0 0x40006a54u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0 0x40006a56u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1 0x40006a68u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1 0x40006a6au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1 0x40006a6cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1 0x40006a6eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1 0x40006a70u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1 0x40006a72u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1 0x40006a74u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1 0x40006a76u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0 0x40006a88u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0 0x40006a8au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0 0x40006a8cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0 0x40006a8eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0 0x40006a90u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0 0x40006a92u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0 0x40006a94u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0 0x40006a96u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1 0x40006aa8u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1 0x40006aaau +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1 0x40006aacu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1 0x40006aaeu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1 0x40006ab0u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1 0x40006ab2u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1 0x40006ab4u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1 0x40006ab6u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST 0x40006ac8u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST 0x40006acau +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST 0x40006accu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST 0x40006aceu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST 0x40006ad0u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST 0x40006ad2u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST 0x40006ad4u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST 0x40006ad6u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL 0x40006ae8u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL 0x40006aeau +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL 0x40006aecu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL 0x40006aeeu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL 0x40006af0u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL 0x40006af2u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL 0x40006af4u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL 0x40006af6u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK 0x40006b08u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK 0x40006b0au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK 0x40006b0cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK 0x40006b0eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK 0x40006b10u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK 0x40006b12u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK 0x40006b14u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK 0x40006b16u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL 0x40006b28u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL 0x40006b2au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL 0x40006b2cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL 0x40006b2eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL 0x40006b30u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL 0x40006b32u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL 0x40006b34u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL 0x40006b36u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC 0x40006b48u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC 0x40006b4au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC 0x40006b4cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC 0x40006b4eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC 0x40006b50u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC 0x40006b52u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC 0x40006b54u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC 0x40006b56u +#define CYDEV_PHUB_BASE 0x40007000u +#define CYDEV_PHUB_SIZE 0x00000c00u +#define CYDEV_PHUB_CFG 0x40007000u +#define CYDEV_PHUB_ERR 0x40007004u +#define CYDEV_PHUB_ERR_ADR 0x40007008u +#define CYDEV_PHUB_CH0_BASE 0x40007010u +#define CYDEV_PHUB_CH0_SIZE 0x0000000cu +#define CYDEV_PHUB_CH0_BASIC_CFG 0x40007010u +#define CYDEV_PHUB_CH0_ACTION 0x40007014u +#define CYDEV_PHUB_CH0_BASIC_STATUS 0x40007018u +#define CYDEV_PHUB_CH1_BASE 0x40007020u +#define CYDEV_PHUB_CH1_SIZE 0x0000000cu +#define CYDEV_PHUB_CH1_BASIC_CFG 0x40007020u +#define CYDEV_PHUB_CH1_ACTION 0x40007024u +#define CYDEV_PHUB_CH1_BASIC_STATUS 0x40007028u +#define CYDEV_PHUB_CH2_BASE 0x40007030u +#define CYDEV_PHUB_CH2_SIZE 0x0000000cu +#define CYDEV_PHUB_CH2_BASIC_CFG 0x40007030u +#define CYDEV_PHUB_CH2_ACTION 0x40007034u +#define CYDEV_PHUB_CH2_BASIC_STATUS 0x40007038u +#define CYDEV_PHUB_CH3_BASE 0x40007040u +#define CYDEV_PHUB_CH3_SIZE 0x0000000cu +#define CYDEV_PHUB_CH3_BASIC_CFG 0x40007040u +#define CYDEV_PHUB_CH3_ACTION 0x40007044u +#define CYDEV_PHUB_CH3_BASIC_STATUS 0x40007048u +#define CYDEV_PHUB_CH4_BASE 0x40007050u +#define CYDEV_PHUB_CH4_SIZE 0x0000000cu +#define CYDEV_PHUB_CH4_BASIC_CFG 0x40007050u +#define CYDEV_PHUB_CH4_ACTION 0x40007054u +#define CYDEV_PHUB_CH4_BASIC_STATUS 0x40007058u +#define CYDEV_PHUB_CH5_BASE 0x40007060u +#define CYDEV_PHUB_CH5_SIZE 0x0000000cu +#define CYDEV_PHUB_CH5_BASIC_CFG 0x40007060u +#define CYDEV_PHUB_CH5_ACTION 0x40007064u +#define CYDEV_PHUB_CH5_BASIC_STATUS 0x40007068u +#define CYDEV_PHUB_CH6_BASE 0x40007070u +#define CYDEV_PHUB_CH6_SIZE 0x0000000cu +#define CYDEV_PHUB_CH6_BASIC_CFG 0x40007070u +#define CYDEV_PHUB_CH6_ACTION 0x40007074u +#define CYDEV_PHUB_CH6_BASIC_STATUS 0x40007078u +#define CYDEV_PHUB_CH7_BASE 0x40007080u +#define CYDEV_PHUB_CH7_SIZE 0x0000000cu +#define CYDEV_PHUB_CH7_BASIC_CFG 0x40007080u +#define CYDEV_PHUB_CH7_ACTION 0x40007084u +#define CYDEV_PHUB_CH7_BASIC_STATUS 0x40007088u +#define CYDEV_PHUB_CH8_BASE 0x40007090u +#define CYDEV_PHUB_CH8_SIZE 0x0000000cu +#define CYDEV_PHUB_CH8_BASIC_CFG 0x40007090u +#define CYDEV_PHUB_CH8_ACTION 0x40007094u +#define CYDEV_PHUB_CH8_BASIC_STATUS 0x40007098u +#define CYDEV_PHUB_CH9_BASE 0x400070a0u +#define CYDEV_PHUB_CH9_SIZE 0x0000000cu +#define CYDEV_PHUB_CH9_BASIC_CFG 0x400070a0u +#define CYDEV_PHUB_CH9_ACTION 0x400070a4u +#define CYDEV_PHUB_CH9_BASIC_STATUS 0x400070a8u +#define CYDEV_PHUB_CH10_BASE 0x400070b0u +#define CYDEV_PHUB_CH10_SIZE 0x0000000cu +#define CYDEV_PHUB_CH10_BASIC_CFG 0x400070b0u +#define CYDEV_PHUB_CH10_ACTION 0x400070b4u +#define CYDEV_PHUB_CH10_BASIC_STATUS 0x400070b8u +#define CYDEV_PHUB_CH11_BASE 0x400070c0u +#define CYDEV_PHUB_CH11_SIZE 0x0000000cu +#define CYDEV_PHUB_CH11_BASIC_CFG 0x400070c0u +#define CYDEV_PHUB_CH11_ACTION 0x400070c4u +#define CYDEV_PHUB_CH11_BASIC_STATUS 0x400070c8u +#define CYDEV_PHUB_CH12_BASE 0x400070d0u +#define CYDEV_PHUB_CH12_SIZE 0x0000000cu +#define CYDEV_PHUB_CH12_BASIC_CFG 0x400070d0u +#define CYDEV_PHUB_CH12_ACTION 0x400070d4u +#define CYDEV_PHUB_CH12_BASIC_STATUS 0x400070d8u +#define CYDEV_PHUB_CH13_BASE 0x400070e0u +#define CYDEV_PHUB_CH13_SIZE 0x0000000cu +#define CYDEV_PHUB_CH13_BASIC_CFG 0x400070e0u +#define CYDEV_PHUB_CH13_ACTION 0x400070e4u +#define CYDEV_PHUB_CH13_BASIC_STATUS 0x400070e8u +#define CYDEV_PHUB_CH14_BASE 0x400070f0u +#define CYDEV_PHUB_CH14_SIZE 0x0000000cu +#define CYDEV_PHUB_CH14_BASIC_CFG 0x400070f0u +#define CYDEV_PHUB_CH14_ACTION 0x400070f4u +#define CYDEV_PHUB_CH14_BASIC_STATUS 0x400070f8u +#define CYDEV_PHUB_CH15_BASE 0x40007100u +#define CYDEV_PHUB_CH15_SIZE 0x0000000cu +#define CYDEV_PHUB_CH15_BASIC_CFG 0x40007100u +#define CYDEV_PHUB_CH15_ACTION 0x40007104u +#define CYDEV_PHUB_CH15_BASIC_STATUS 0x40007108u +#define CYDEV_PHUB_CH16_BASE 0x40007110u +#define CYDEV_PHUB_CH16_SIZE 0x0000000cu +#define CYDEV_PHUB_CH16_BASIC_CFG 0x40007110u +#define CYDEV_PHUB_CH16_ACTION 0x40007114u +#define CYDEV_PHUB_CH16_BASIC_STATUS 0x40007118u +#define CYDEV_PHUB_CH17_BASE 0x40007120u +#define CYDEV_PHUB_CH17_SIZE 0x0000000cu +#define CYDEV_PHUB_CH17_BASIC_CFG 0x40007120u +#define CYDEV_PHUB_CH17_ACTION 0x40007124u +#define CYDEV_PHUB_CH17_BASIC_STATUS 0x40007128u +#define CYDEV_PHUB_CH18_BASE 0x40007130u +#define CYDEV_PHUB_CH18_SIZE 0x0000000cu +#define CYDEV_PHUB_CH18_BASIC_CFG 0x40007130u +#define CYDEV_PHUB_CH18_ACTION 0x40007134u +#define CYDEV_PHUB_CH18_BASIC_STATUS 0x40007138u +#define CYDEV_PHUB_CH19_BASE 0x40007140u +#define CYDEV_PHUB_CH19_SIZE 0x0000000cu +#define CYDEV_PHUB_CH19_BASIC_CFG 0x40007140u +#define CYDEV_PHUB_CH19_ACTION 0x40007144u +#define CYDEV_PHUB_CH19_BASIC_STATUS 0x40007148u +#define CYDEV_PHUB_CH20_BASE 0x40007150u +#define CYDEV_PHUB_CH20_SIZE 0x0000000cu +#define CYDEV_PHUB_CH20_BASIC_CFG 0x40007150u +#define CYDEV_PHUB_CH20_ACTION 0x40007154u +#define CYDEV_PHUB_CH20_BASIC_STATUS 0x40007158u +#define CYDEV_PHUB_CH21_BASE 0x40007160u +#define CYDEV_PHUB_CH21_SIZE 0x0000000cu +#define CYDEV_PHUB_CH21_BASIC_CFG 0x40007160u +#define CYDEV_PHUB_CH21_ACTION 0x40007164u +#define CYDEV_PHUB_CH21_BASIC_STATUS 0x40007168u +#define CYDEV_PHUB_CH22_BASE 0x40007170u +#define CYDEV_PHUB_CH22_SIZE 0x0000000cu +#define CYDEV_PHUB_CH22_BASIC_CFG 0x40007170u +#define CYDEV_PHUB_CH22_ACTION 0x40007174u +#define CYDEV_PHUB_CH22_BASIC_STATUS 0x40007178u +#define CYDEV_PHUB_CH23_BASE 0x40007180u +#define CYDEV_PHUB_CH23_SIZE 0x0000000cu +#define CYDEV_PHUB_CH23_BASIC_CFG 0x40007180u +#define CYDEV_PHUB_CH23_ACTION 0x40007184u +#define CYDEV_PHUB_CH23_BASIC_STATUS 0x40007188u +#define CYDEV_PHUB_CFGMEM0_BASE 0x40007600u +#define CYDEV_PHUB_CFGMEM0_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM0_CFG0 0x40007600u +#define CYDEV_PHUB_CFGMEM0_CFG1 0x40007604u +#define CYDEV_PHUB_CFGMEM1_BASE 0x40007608u +#define CYDEV_PHUB_CFGMEM1_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM1_CFG0 0x40007608u +#define CYDEV_PHUB_CFGMEM1_CFG1 0x4000760cu +#define CYDEV_PHUB_CFGMEM2_BASE 0x40007610u +#define CYDEV_PHUB_CFGMEM2_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM2_CFG0 0x40007610u +#define CYDEV_PHUB_CFGMEM2_CFG1 0x40007614u +#define CYDEV_PHUB_CFGMEM3_BASE 0x40007618u +#define CYDEV_PHUB_CFGMEM3_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM3_CFG0 0x40007618u +#define CYDEV_PHUB_CFGMEM3_CFG1 0x4000761cu +#define CYDEV_PHUB_CFGMEM4_BASE 0x40007620u +#define CYDEV_PHUB_CFGMEM4_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM4_CFG0 0x40007620u +#define CYDEV_PHUB_CFGMEM4_CFG1 0x40007624u +#define CYDEV_PHUB_CFGMEM5_BASE 0x40007628u +#define CYDEV_PHUB_CFGMEM5_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM5_CFG0 0x40007628u +#define CYDEV_PHUB_CFGMEM5_CFG1 0x4000762cu +#define CYDEV_PHUB_CFGMEM6_BASE 0x40007630u +#define CYDEV_PHUB_CFGMEM6_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM6_CFG0 0x40007630u +#define CYDEV_PHUB_CFGMEM6_CFG1 0x40007634u +#define CYDEV_PHUB_CFGMEM7_BASE 0x40007638u +#define CYDEV_PHUB_CFGMEM7_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM7_CFG0 0x40007638u +#define CYDEV_PHUB_CFGMEM7_CFG1 0x4000763cu +#define CYDEV_PHUB_CFGMEM8_BASE 0x40007640u +#define CYDEV_PHUB_CFGMEM8_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM8_CFG0 0x40007640u +#define CYDEV_PHUB_CFGMEM8_CFG1 0x40007644u +#define CYDEV_PHUB_CFGMEM9_BASE 0x40007648u +#define CYDEV_PHUB_CFGMEM9_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM9_CFG0 0x40007648u +#define CYDEV_PHUB_CFGMEM9_CFG1 0x4000764cu +#define CYDEV_PHUB_CFGMEM10_BASE 0x40007650u +#define CYDEV_PHUB_CFGMEM10_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM10_CFG0 0x40007650u +#define CYDEV_PHUB_CFGMEM10_CFG1 0x40007654u +#define CYDEV_PHUB_CFGMEM11_BASE 0x40007658u +#define CYDEV_PHUB_CFGMEM11_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM11_CFG0 0x40007658u +#define CYDEV_PHUB_CFGMEM11_CFG1 0x4000765cu +#define CYDEV_PHUB_CFGMEM12_BASE 0x40007660u +#define CYDEV_PHUB_CFGMEM12_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM12_CFG0 0x40007660u +#define CYDEV_PHUB_CFGMEM12_CFG1 0x40007664u +#define CYDEV_PHUB_CFGMEM13_BASE 0x40007668u +#define CYDEV_PHUB_CFGMEM13_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM13_CFG0 0x40007668u +#define CYDEV_PHUB_CFGMEM13_CFG1 0x4000766cu +#define CYDEV_PHUB_CFGMEM14_BASE 0x40007670u +#define CYDEV_PHUB_CFGMEM14_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM14_CFG0 0x40007670u +#define CYDEV_PHUB_CFGMEM14_CFG1 0x40007674u +#define CYDEV_PHUB_CFGMEM15_BASE 0x40007678u +#define CYDEV_PHUB_CFGMEM15_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM15_CFG0 0x40007678u +#define CYDEV_PHUB_CFGMEM15_CFG1 0x4000767cu +#define CYDEV_PHUB_CFGMEM16_BASE 0x40007680u +#define CYDEV_PHUB_CFGMEM16_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM16_CFG0 0x40007680u +#define CYDEV_PHUB_CFGMEM16_CFG1 0x40007684u +#define CYDEV_PHUB_CFGMEM17_BASE 0x40007688u +#define CYDEV_PHUB_CFGMEM17_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM17_CFG0 0x40007688u +#define CYDEV_PHUB_CFGMEM17_CFG1 0x4000768cu +#define CYDEV_PHUB_CFGMEM18_BASE 0x40007690u +#define CYDEV_PHUB_CFGMEM18_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM18_CFG0 0x40007690u +#define CYDEV_PHUB_CFGMEM18_CFG1 0x40007694u +#define CYDEV_PHUB_CFGMEM19_BASE 0x40007698u +#define CYDEV_PHUB_CFGMEM19_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM19_CFG0 0x40007698u +#define CYDEV_PHUB_CFGMEM19_CFG1 0x4000769cu +#define CYDEV_PHUB_CFGMEM20_BASE 0x400076a0u +#define CYDEV_PHUB_CFGMEM20_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM20_CFG0 0x400076a0u +#define CYDEV_PHUB_CFGMEM20_CFG1 0x400076a4u +#define CYDEV_PHUB_CFGMEM21_BASE 0x400076a8u +#define CYDEV_PHUB_CFGMEM21_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM21_CFG0 0x400076a8u +#define CYDEV_PHUB_CFGMEM21_CFG1 0x400076acu +#define CYDEV_PHUB_CFGMEM22_BASE 0x400076b0u +#define CYDEV_PHUB_CFGMEM22_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM22_CFG0 0x400076b0u +#define CYDEV_PHUB_CFGMEM22_CFG1 0x400076b4u +#define CYDEV_PHUB_CFGMEM23_BASE 0x400076b8u +#define CYDEV_PHUB_CFGMEM23_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM23_CFG0 0x400076b8u +#define CYDEV_PHUB_CFGMEM23_CFG1 0x400076bcu +#define CYDEV_PHUB_TDMEM0_BASE 0x40007800u +#define CYDEV_PHUB_TDMEM0_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM0_ORIG_TD0 0x40007800u +#define CYDEV_PHUB_TDMEM0_ORIG_TD1 0x40007804u +#define CYDEV_PHUB_TDMEM1_BASE 0x40007808u +#define CYDEV_PHUB_TDMEM1_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM1_ORIG_TD0 0x40007808u +#define CYDEV_PHUB_TDMEM1_ORIG_TD1 0x4000780cu +#define CYDEV_PHUB_TDMEM2_BASE 0x40007810u +#define CYDEV_PHUB_TDMEM2_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM2_ORIG_TD0 0x40007810u +#define CYDEV_PHUB_TDMEM2_ORIG_TD1 0x40007814u +#define CYDEV_PHUB_TDMEM3_BASE 0x40007818u +#define CYDEV_PHUB_TDMEM3_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM3_ORIG_TD0 0x40007818u +#define CYDEV_PHUB_TDMEM3_ORIG_TD1 0x4000781cu +#define CYDEV_PHUB_TDMEM4_BASE 0x40007820u +#define CYDEV_PHUB_TDMEM4_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM4_ORIG_TD0 0x40007820u +#define CYDEV_PHUB_TDMEM4_ORIG_TD1 0x40007824u +#define CYDEV_PHUB_TDMEM5_BASE 0x40007828u +#define CYDEV_PHUB_TDMEM5_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM5_ORIG_TD0 0x40007828u +#define CYDEV_PHUB_TDMEM5_ORIG_TD1 0x4000782cu +#define CYDEV_PHUB_TDMEM6_BASE 0x40007830u +#define CYDEV_PHUB_TDMEM6_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM6_ORIG_TD0 0x40007830u +#define CYDEV_PHUB_TDMEM6_ORIG_TD1 0x40007834u +#define CYDEV_PHUB_TDMEM7_BASE 0x40007838u +#define CYDEV_PHUB_TDMEM7_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM7_ORIG_TD0 0x40007838u +#define CYDEV_PHUB_TDMEM7_ORIG_TD1 0x4000783cu +#define CYDEV_PHUB_TDMEM8_BASE 0x40007840u +#define CYDEV_PHUB_TDMEM8_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM8_ORIG_TD0 0x40007840u +#define CYDEV_PHUB_TDMEM8_ORIG_TD1 0x40007844u +#define CYDEV_PHUB_TDMEM9_BASE 0x40007848u +#define CYDEV_PHUB_TDMEM9_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM9_ORIG_TD0 0x40007848u +#define CYDEV_PHUB_TDMEM9_ORIG_TD1 0x4000784cu +#define CYDEV_PHUB_TDMEM10_BASE 0x40007850u +#define CYDEV_PHUB_TDMEM10_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM10_ORIG_TD0 0x40007850u +#define CYDEV_PHUB_TDMEM10_ORIG_TD1 0x40007854u +#define CYDEV_PHUB_TDMEM11_BASE 0x40007858u +#define CYDEV_PHUB_TDMEM11_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM11_ORIG_TD0 0x40007858u +#define CYDEV_PHUB_TDMEM11_ORIG_TD1 0x4000785cu +#define CYDEV_PHUB_TDMEM12_BASE 0x40007860u +#define CYDEV_PHUB_TDMEM12_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM12_ORIG_TD0 0x40007860u +#define CYDEV_PHUB_TDMEM12_ORIG_TD1 0x40007864u +#define CYDEV_PHUB_TDMEM13_BASE 0x40007868u +#define CYDEV_PHUB_TDMEM13_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM13_ORIG_TD0 0x40007868u +#define CYDEV_PHUB_TDMEM13_ORIG_TD1 0x4000786cu +#define CYDEV_PHUB_TDMEM14_BASE 0x40007870u +#define CYDEV_PHUB_TDMEM14_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM14_ORIG_TD0 0x40007870u +#define CYDEV_PHUB_TDMEM14_ORIG_TD1 0x40007874u +#define CYDEV_PHUB_TDMEM15_BASE 0x40007878u +#define CYDEV_PHUB_TDMEM15_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM15_ORIG_TD0 0x40007878u +#define CYDEV_PHUB_TDMEM15_ORIG_TD1 0x4000787cu +#define CYDEV_PHUB_TDMEM16_BASE 0x40007880u +#define CYDEV_PHUB_TDMEM16_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM16_ORIG_TD0 0x40007880u +#define CYDEV_PHUB_TDMEM16_ORIG_TD1 0x40007884u +#define CYDEV_PHUB_TDMEM17_BASE 0x40007888u +#define CYDEV_PHUB_TDMEM17_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM17_ORIG_TD0 0x40007888u +#define CYDEV_PHUB_TDMEM17_ORIG_TD1 0x4000788cu +#define CYDEV_PHUB_TDMEM18_BASE 0x40007890u +#define CYDEV_PHUB_TDMEM18_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM18_ORIG_TD0 0x40007890u +#define CYDEV_PHUB_TDMEM18_ORIG_TD1 0x40007894u +#define CYDEV_PHUB_TDMEM19_BASE 0x40007898u +#define CYDEV_PHUB_TDMEM19_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM19_ORIG_TD0 0x40007898u +#define CYDEV_PHUB_TDMEM19_ORIG_TD1 0x4000789cu +#define CYDEV_PHUB_TDMEM20_BASE 0x400078a0u +#define CYDEV_PHUB_TDMEM20_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM20_ORIG_TD0 0x400078a0u +#define CYDEV_PHUB_TDMEM20_ORIG_TD1 0x400078a4u +#define CYDEV_PHUB_TDMEM21_BASE 0x400078a8u +#define CYDEV_PHUB_TDMEM21_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM21_ORIG_TD0 0x400078a8u +#define CYDEV_PHUB_TDMEM21_ORIG_TD1 0x400078acu +#define CYDEV_PHUB_TDMEM22_BASE 0x400078b0u +#define CYDEV_PHUB_TDMEM22_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM22_ORIG_TD0 0x400078b0u +#define CYDEV_PHUB_TDMEM22_ORIG_TD1 0x400078b4u +#define CYDEV_PHUB_TDMEM23_BASE 0x400078b8u +#define CYDEV_PHUB_TDMEM23_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM23_ORIG_TD0 0x400078b8u +#define CYDEV_PHUB_TDMEM23_ORIG_TD1 0x400078bcu +#define CYDEV_PHUB_TDMEM24_BASE 0x400078c0u +#define CYDEV_PHUB_TDMEM24_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM24_ORIG_TD0 0x400078c0u +#define CYDEV_PHUB_TDMEM24_ORIG_TD1 0x400078c4u +#define CYDEV_PHUB_TDMEM25_BASE 0x400078c8u +#define CYDEV_PHUB_TDMEM25_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM25_ORIG_TD0 0x400078c8u +#define CYDEV_PHUB_TDMEM25_ORIG_TD1 0x400078ccu +#define CYDEV_PHUB_TDMEM26_BASE 0x400078d0u +#define CYDEV_PHUB_TDMEM26_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM26_ORIG_TD0 0x400078d0u +#define CYDEV_PHUB_TDMEM26_ORIG_TD1 0x400078d4u +#define CYDEV_PHUB_TDMEM27_BASE 0x400078d8u +#define CYDEV_PHUB_TDMEM27_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM27_ORIG_TD0 0x400078d8u +#define CYDEV_PHUB_TDMEM27_ORIG_TD1 0x400078dcu +#define CYDEV_PHUB_TDMEM28_BASE 0x400078e0u +#define CYDEV_PHUB_TDMEM28_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM28_ORIG_TD0 0x400078e0u +#define CYDEV_PHUB_TDMEM28_ORIG_TD1 0x400078e4u +#define CYDEV_PHUB_TDMEM29_BASE 0x400078e8u +#define CYDEV_PHUB_TDMEM29_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM29_ORIG_TD0 0x400078e8u +#define CYDEV_PHUB_TDMEM29_ORIG_TD1 0x400078ecu +#define CYDEV_PHUB_TDMEM30_BASE 0x400078f0u +#define CYDEV_PHUB_TDMEM30_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM30_ORIG_TD0 0x400078f0u +#define CYDEV_PHUB_TDMEM30_ORIG_TD1 0x400078f4u +#define CYDEV_PHUB_TDMEM31_BASE 0x400078f8u +#define CYDEV_PHUB_TDMEM31_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM31_ORIG_TD0 0x400078f8u +#define CYDEV_PHUB_TDMEM31_ORIG_TD1 0x400078fcu +#define CYDEV_PHUB_TDMEM32_BASE 0x40007900u +#define CYDEV_PHUB_TDMEM32_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM32_ORIG_TD0 0x40007900u +#define CYDEV_PHUB_TDMEM32_ORIG_TD1 0x40007904u +#define CYDEV_PHUB_TDMEM33_BASE 0x40007908u +#define CYDEV_PHUB_TDMEM33_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM33_ORIG_TD0 0x40007908u +#define CYDEV_PHUB_TDMEM33_ORIG_TD1 0x4000790cu +#define CYDEV_PHUB_TDMEM34_BASE 0x40007910u +#define CYDEV_PHUB_TDMEM34_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM34_ORIG_TD0 0x40007910u +#define CYDEV_PHUB_TDMEM34_ORIG_TD1 0x40007914u +#define CYDEV_PHUB_TDMEM35_BASE 0x40007918u +#define CYDEV_PHUB_TDMEM35_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM35_ORIG_TD0 0x40007918u +#define CYDEV_PHUB_TDMEM35_ORIG_TD1 0x4000791cu +#define CYDEV_PHUB_TDMEM36_BASE 0x40007920u +#define CYDEV_PHUB_TDMEM36_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM36_ORIG_TD0 0x40007920u +#define CYDEV_PHUB_TDMEM36_ORIG_TD1 0x40007924u +#define CYDEV_PHUB_TDMEM37_BASE 0x40007928u +#define CYDEV_PHUB_TDMEM37_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM37_ORIG_TD0 0x40007928u +#define CYDEV_PHUB_TDMEM37_ORIG_TD1 0x4000792cu +#define CYDEV_PHUB_TDMEM38_BASE 0x40007930u +#define CYDEV_PHUB_TDMEM38_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM38_ORIG_TD0 0x40007930u +#define CYDEV_PHUB_TDMEM38_ORIG_TD1 0x40007934u +#define CYDEV_PHUB_TDMEM39_BASE 0x40007938u +#define CYDEV_PHUB_TDMEM39_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM39_ORIG_TD0 0x40007938u +#define CYDEV_PHUB_TDMEM39_ORIG_TD1 0x4000793cu +#define CYDEV_PHUB_TDMEM40_BASE 0x40007940u +#define CYDEV_PHUB_TDMEM40_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM40_ORIG_TD0 0x40007940u +#define CYDEV_PHUB_TDMEM40_ORIG_TD1 0x40007944u +#define CYDEV_PHUB_TDMEM41_BASE 0x40007948u +#define CYDEV_PHUB_TDMEM41_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM41_ORIG_TD0 0x40007948u +#define CYDEV_PHUB_TDMEM41_ORIG_TD1 0x4000794cu +#define CYDEV_PHUB_TDMEM42_BASE 0x40007950u +#define CYDEV_PHUB_TDMEM42_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM42_ORIG_TD0 0x40007950u +#define CYDEV_PHUB_TDMEM42_ORIG_TD1 0x40007954u +#define CYDEV_PHUB_TDMEM43_BASE 0x40007958u +#define CYDEV_PHUB_TDMEM43_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM43_ORIG_TD0 0x40007958u +#define CYDEV_PHUB_TDMEM43_ORIG_TD1 0x4000795cu +#define CYDEV_PHUB_TDMEM44_BASE 0x40007960u +#define CYDEV_PHUB_TDMEM44_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM44_ORIG_TD0 0x40007960u +#define CYDEV_PHUB_TDMEM44_ORIG_TD1 0x40007964u +#define CYDEV_PHUB_TDMEM45_BASE 0x40007968u +#define CYDEV_PHUB_TDMEM45_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM45_ORIG_TD0 0x40007968u +#define CYDEV_PHUB_TDMEM45_ORIG_TD1 0x4000796cu +#define CYDEV_PHUB_TDMEM46_BASE 0x40007970u +#define CYDEV_PHUB_TDMEM46_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM46_ORIG_TD0 0x40007970u +#define CYDEV_PHUB_TDMEM46_ORIG_TD1 0x40007974u +#define CYDEV_PHUB_TDMEM47_BASE 0x40007978u +#define CYDEV_PHUB_TDMEM47_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM47_ORIG_TD0 0x40007978u +#define CYDEV_PHUB_TDMEM47_ORIG_TD1 0x4000797cu +#define CYDEV_PHUB_TDMEM48_BASE 0x40007980u +#define CYDEV_PHUB_TDMEM48_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM48_ORIG_TD0 0x40007980u +#define CYDEV_PHUB_TDMEM48_ORIG_TD1 0x40007984u +#define CYDEV_PHUB_TDMEM49_BASE 0x40007988u +#define CYDEV_PHUB_TDMEM49_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM49_ORIG_TD0 0x40007988u +#define CYDEV_PHUB_TDMEM49_ORIG_TD1 0x4000798cu +#define CYDEV_PHUB_TDMEM50_BASE 0x40007990u +#define CYDEV_PHUB_TDMEM50_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM50_ORIG_TD0 0x40007990u +#define CYDEV_PHUB_TDMEM50_ORIG_TD1 0x40007994u +#define CYDEV_PHUB_TDMEM51_BASE 0x40007998u +#define CYDEV_PHUB_TDMEM51_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM51_ORIG_TD0 0x40007998u +#define CYDEV_PHUB_TDMEM51_ORIG_TD1 0x4000799cu +#define CYDEV_PHUB_TDMEM52_BASE 0x400079a0u +#define CYDEV_PHUB_TDMEM52_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM52_ORIG_TD0 0x400079a0u +#define CYDEV_PHUB_TDMEM52_ORIG_TD1 0x400079a4u +#define CYDEV_PHUB_TDMEM53_BASE 0x400079a8u +#define CYDEV_PHUB_TDMEM53_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM53_ORIG_TD0 0x400079a8u +#define CYDEV_PHUB_TDMEM53_ORIG_TD1 0x400079acu +#define CYDEV_PHUB_TDMEM54_BASE 0x400079b0u +#define CYDEV_PHUB_TDMEM54_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM54_ORIG_TD0 0x400079b0u +#define CYDEV_PHUB_TDMEM54_ORIG_TD1 0x400079b4u +#define CYDEV_PHUB_TDMEM55_BASE 0x400079b8u +#define CYDEV_PHUB_TDMEM55_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM55_ORIG_TD0 0x400079b8u +#define CYDEV_PHUB_TDMEM55_ORIG_TD1 0x400079bcu +#define CYDEV_PHUB_TDMEM56_BASE 0x400079c0u +#define CYDEV_PHUB_TDMEM56_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM56_ORIG_TD0 0x400079c0u +#define CYDEV_PHUB_TDMEM56_ORIG_TD1 0x400079c4u +#define CYDEV_PHUB_TDMEM57_BASE 0x400079c8u +#define CYDEV_PHUB_TDMEM57_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM57_ORIG_TD0 0x400079c8u +#define CYDEV_PHUB_TDMEM57_ORIG_TD1 0x400079ccu +#define CYDEV_PHUB_TDMEM58_BASE 0x400079d0u +#define CYDEV_PHUB_TDMEM58_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM58_ORIG_TD0 0x400079d0u +#define CYDEV_PHUB_TDMEM58_ORIG_TD1 0x400079d4u +#define CYDEV_PHUB_TDMEM59_BASE 0x400079d8u +#define CYDEV_PHUB_TDMEM59_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM59_ORIG_TD0 0x400079d8u +#define CYDEV_PHUB_TDMEM59_ORIG_TD1 0x400079dcu +#define CYDEV_PHUB_TDMEM60_BASE 0x400079e0u +#define CYDEV_PHUB_TDMEM60_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM60_ORIG_TD0 0x400079e0u +#define CYDEV_PHUB_TDMEM60_ORIG_TD1 0x400079e4u +#define CYDEV_PHUB_TDMEM61_BASE 0x400079e8u +#define CYDEV_PHUB_TDMEM61_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM61_ORIG_TD0 0x400079e8u +#define CYDEV_PHUB_TDMEM61_ORIG_TD1 0x400079ecu +#define CYDEV_PHUB_TDMEM62_BASE 0x400079f0u +#define CYDEV_PHUB_TDMEM62_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM62_ORIG_TD0 0x400079f0u +#define CYDEV_PHUB_TDMEM62_ORIG_TD1 0x400079f4u +#define CYDEV_PHUB_TDMEM63_BASE 0x400079f8u +#define CYDEV_PHUB_TDMEM63_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM63_ORIG_TD0 0x400079f8u +#define CYDEV_PHUB_TDMEM63_ORIG_TD1 0x400079fcu +#define CYDEV_PHUB_TDMEM64_BASE 0x40007a00u +#define CYDEV_PHUB_TDMEM64_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM64_ORIG_TD0 0x40007a00u +#define CYDEV_PHUB_TDMEM64_ORIG_TD1 0x40007a04u +#define CYDEV_PHUB_TDMEM65_BASE 0x40007a08u +#define CYDEV_PHUB_TDMEM65_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM65_ORIG_TD0 0x40007a08u +#define CYDEV_PHUB_TDMEM65_ORIG_TD1 0x40007a0cu +#define CYDEV_PHUB_TDMEM66_BASE 0x40007a10u +#define CYDEV_PHUB_TDMEM66_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM66_ORIG_TD0 0x40007a10u +#define CYDEV_PHUB_TDMEM66_ORIG_TD1 0x40007a14u +#define CYDEV_PHUB_TDMEM67_BASE 0x40007a18u +#define CYDEV_PHUB_TDMEM67_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM67_ORIG_TD0 0x40007a18u +#define CYDEV_PHUB_TDMEM67_ORIG_TD1 0x40007a1cu +#define CYDEV_PHUB_TDMEM68_BASE 0x40007a20u +#define CYDEV_PHUB_TDMEM68_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM68_ORIG_TD0 0x40007a20u +#define CYDEV_PHUB_TDMEM68_ORIG_TD1 0x40007a24u +#define CYDEV_PHUB_TDMEM69_BASE 0x40007a28u +#define CYDEV_PHUB_TDMEM69_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM69_ORIG_TD0 0x40007a28u +#define CYDEV_PHUB_TDMEM69_ORIG_TD1 0x40007a2cu +#define CYDEV_PHUB_TDMEM70_BASE 0x40007a30u +#define CYDEV_PHUB_TDMEM70_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM70_ORIG_TD0 0x40007a30u +#define CYDEV_PHUB_TDMEM70_ORIG_TD1 0x40007a34u +#define CYDEV_PHUB_TDMEM71_BASE 0x40007a38u +#define CYDEV_PHUB_TDMEM71_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM71_ORIG_TD0 0x40007a38u +#define CYDEV_PHUB_TDMEM71_ORIG_TD1 0x40007a3cu +#define CYDEV_PHUB_TDMEM72_BASE 0x40007a40u +#define CYDEV_PHUB_TDMEM72_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM72_ORIG_TD0 0x40007a40u +#define CYDEV_PHUB_TDMEM72_ORIG_TD1 0x40007a44u +#define CYDEV_PHUB_TDMEM73_BASE 0x40007a48u +#define CYDEV_PHUB_TDMEM73_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM73_ORIG_TD0 0x40007a48u +#define CYDEV_PHUB_TDMEM73_ORIG_TD1 0x40007a4cu +#define CYDEV_PHUB_TDMEM74_BASE 0x40007a50u +#define CYDEV_PHUB_TDMEM74_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM74_ORIG_TD0 0x40007a50u +#define CYDEV_PHUB_TDMEM74_ORIG_TD1 0x40007a54u +#define CYDEV_PHUB_TDMEM75_BASE 0x40007a58u +#define CYDEV_PHUB_TDMEM75_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM75_ORIG_TD0 0x40007a58u +#define CYDEV_PHUB_TDMEM75_ORIG_TD1 0x40007a5cu +#define CYDEV_PHUB_TDMEM76_BASE 0x40007a60u +#define CYDEV_PHUB_TDMEM76_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM76_ORIG_TD0 0x40007a60u +#define CYDEV_PHUB_TDMEM76_ORIG_TD1 0x40007a64u +#define CYDEV_PHUB_TDMEM77_BASE 0x40007a68u +#define CYDEV_PHUB_TDMEM77_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM77_ORIG_TD0 0x40007a68u +#define CYDEV_PHUB_TDMEM77_ORIG_TD1 0x40007a6cu +#define CYDEV_PHUB_TDMEM78_BASE 0x40007a70u +#define CYDEV_PHUB_TDMEM78_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM78_ORIG_TD0 0x40007a70u +#define CYDEV_PHUB_TDMEM78_ORIG_TD1 0x40007a74u +#define CYDEV_PHUB_TDMEM79_BASE 0x40007a78u +#define CYDEV_PHUB_TDMEM79_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM79_ORIG_TD0 0x40007a78u +#define CYDEV_PHUB_TDMEM79_ORIG_TD1 0x40007a7cu +#define CYDEV_PHUB_TDMEM80_BASE 0x40007a80u +#define CYDEV_PHUB_TDMEM80_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM80_ORIG_TD0 0x40007a80u +#define CYDEV_PHUB_TDMEM80_ORIG_TD1 0x40007a84u +#define CYDEV_PHUB_TDMEM81_BASE 0x40007a88u +#define CYDEV_PHUB_TDMEM81_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM81_ORIG_TD0 0x40007a88u +#define CYDEV_PHUB_TDMEM81_ORIG_TD1 0x40007a8cu +#define CYDEV_PHUB_TDMEM82_BASE 0x40007a90u +#define CYDEV_PHUB_TDMEM82_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM82_ORIG_TD0 0x40007a90u +#define CYDEV_PHUB_TDMEM82_ORIG_TD1 0x40007a94u +#define CYDEV_PHUB_TDMEM83_BASE 0x40007a98u +#define CYDEV_PHUB_TDMEM83_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM83_ORIG_TD0 0x40007a98u +#define CYDEV_PHUB_TDMEM83_ORIG_TD1 0x40007a9cu +#define CYDEV_PHUB_TDMEM84_BASE 0x40007aa0u +#define CYDEV_PHUB_TDMEM84_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM84_ORIG_TD0 0x40007aa0u +#define CYDEV_PHUB_TDMEM84_ORIG_TD1 0x40007aa4u +#define CYDEV_PHUB_TDMEM85_BASE 0x40007aa8u +#define CYDEV_PHUB_TDMEM85_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM85_ORIG_TD0 0x40007aa8u +#define CYDEV_PHUB_TDMEM85_ORIG_TD1 0x40007aacu +#define CYDEV_PHUB_TDMEM86_BASE 0x40007ab0u +#define CYDEV_PHUB_TDMEM86_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM86_ORIG_TD0 0x40007ab0u +#define CYDEV_PHUB_TDMEM86_ORIG_TD1 0x40007ab4u +#define CYDEV_PHUB_TDMEM87_BASE 0x40007ab8u +#define CYDEV_PHUB_TDMEM87_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM87_ORIG_TD0 0x40007ab8u +#define CYDEV_PHUB_TDMEM87_ORIG_TD1 0x40007abcu +#define CYDEV_PHUB_TDMEM88_BASE 0x40007ac0u +#define CYDEV_PHUB_TDMEM88_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM88_ORIG_TD0 0x40007ac0u +#define CYDEV_PHUB_TDMEM88_ORIG_TD1 0x40007ac4u +#define CYDEV_PHUB_TDMEM89_BASE 0x40007ac8u +#define CYDEV_PHUB_TDMEM89_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM89_ORIG_TD0 0x40007ac8u +#define CYDEV_PHUB_TDMEM89_ORIG_TD1 0x40007accu +#define CYDEV_PHUB_TDMEM90_BASE 0x40007ad0u +#define CYDEV_PHUB_TDMEM90_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM90_ORIG_TD0 0x40007ad0u +#define CYDEV_PHUB_TDMEM90_ORIG_TD1 0x40007ad4u +#define CYDEV_PHUB_TDMEM91_BASE 0x40007ad8u +#define CYDEV_PHUB_TDMEM91_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM91_ORIG_TD0 0x40007ad8u +#define CYDEV_PHUB_TDMEM91_ORIG_TD1 0x40007adcu +#define CYDEV_PHUB_TDMEM92_BASE 0x40007ae0u +#define CYDEV_PHUB_TDMEM92_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM92_ORIG_TD0 0x40007ae0u +#define CYDEV_PHUB_TDMEM92_ORIG_TD1 0x40007ae4u +#define CYDEV_PHUB_TDMEM93_BASE 0x40007ae8u +#define CYDEV_PHUB_TDMEM93_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM93_ORIG_TD0 0x40007ae8u +#define CYDEV_PHUB_TDMEM93_ORIG_TD1 0x40007aecu +#define CYDEV_PHUB_TDMEM94_BASE 0x40007af0u +#define CYDEV_PHUB_TDMEM94_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM94_ORIG_TD0 0x40007af0u +#define CYDEV_PHUB_TDMEM94_ORIG_TD1 0x40007af4u +#define CYDEV_PHUB_TDMEM95_BASE 0x40007af8u +#define CYDEV_PHUB_TDMEM95_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM95_ORIG_TD0 0x40007af8u +#define CYDEV_PHUB_TDMEM95_ORIG_TD1 0x40007afcu +#define CYDEV_PHUB_TDMEM96_BASE 0x40007b00u +#define CYDEV_PHUB_TDMEM96_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM96_ORIG_TD0 0x40007b00u +#define CYDEV_PHUB_TDMEM96_ORIG_TD1 0x40007b04u +#define CYDEV_PHUB_TDMEM97_BASE 0x40007b08u +#define CYDEV_PHUB_TDMEM97_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM97_ORIG_TD0 0x40007b08u +#define CYDEV_PHUB_TDMEM97_ORIG_TD1 0x40007b0cu +#define CYDEV_PHUB_TDMEM98_BASE 0x40007b10u +#define CYDEV_PHUB_TDMEM98_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM98_ORIG_TD0 0x40007b10u +#define CYDEV_PHUB_TDMEM98_ORIG_TD1 0x40007b14u +#define CYDEV_PHUB_TDMEM99_BASE 0x40007b18u +#define CYDEV_PHUB_TDMEM99_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM99_ORIG_TD0 0x40007b18u +#define CYDEV_PHUB_TDMEM99_ORIG_TD1 0x40007b1cu +#define CYDEV_PHUB_TDMEM100_BASE 0x40007b20u +#define CYDEV_PHUB_TDMEM100_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM100_ORIG_TD0 0x40007b20u +#define CYDEV_PHUB_TDMEM100_ORIG_TD1 0x40007b24u +#define CYDEV_PHUB_TDMEM101_BASE 0x40007b28u +#define CYDEV_PHUB_TDMEM101_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM101_ORIG_TD0 0x40007b28u +#define CYDEV_PHUB_TDMEM101_ORIG_TD1 0x40007b2cu +#define CYDEV_PHUB_TDMEM102_BASE 0x40007b30u +#define CYDEV_PHUB_TDMEM102_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM102_ORIG_TD0 0x40007b30u +#define CYDEV_PHUB_TDMEM102_ORIG_TD1 0x40007b34u +#define CYDEV_PHUB_TDMEM103_BASE 0x40007b38u +#define CYDEV_PHUB_TDMEM103_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM103_ORIG_TD0 0x40007b38u +#define CYDEV_PHUB_TDMEM103_ORIG_TD1 0x40007b3cu +#define CYDEV_PHUB_TDMEM104_BASE 0x40007b40u +#define CYDEV_PHUB_TDMEM104_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM104_ORIG_TD0 0x40007b40u +#define CYDEV_PHUB_TDMEM104_ORIG_TD1 0x40007b44u +#define CYDEV_PHUB_TDMEM105_BASE 0x40007b48u +#define CYDEV_PHUB_TDMEM105_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM105_ORIG_TD0 0x40007b48u +#define CYDEV_PHUB_TDMEM105_ORIG_TD1 0x40007b4cu +#define CYDEV_PHUB_TDMEM106_BASE 0x40007b50u +#define CYDEV_PHUB_TDMEM106_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM106_ORIG_TD0 0x40007b50u +#define CYDEV_PHUB_TDMEM106_ORIG_TD1 0x40007b54u +#define CYDEV_PHUB_TDMEM107_BASE 0x40007b58u +#define CYDEV_PHUB_TDMEM107_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM107_ORIG_TD0 0x40007b58u +#define CYDEV_PHUB_TDMEM107_ORIG_TD1 0x40007b5cu +#define CYDEV_PHUB_TDMEM108_BASE 0x40007b60u +#define CYDEV_PHUB_TDMEM108_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM108_ORIG_TD0 0x40007b60u +#define CYDEV_PHUB_TDMEM108_ORIG_TD1 0x40007b64u +#define CYDEV_PHUB_TDMEM109_BASE 0x40007b68u +#define CYDEV_PHUB_TDMEM109_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM109_ORIG_TD0 0x40007b68u +#define CYDEV_PHUB_TDMEM109_ORIG_TD1 0x40007b6cu +#define CYDEV_PHUB_TDMEM110_BASE 0x40007b70u +#define CYDEV_PHUB_TDMEM110_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM110_ORIG_TD0 0x40007b70u +#define CYDEV_PHUB_TDMEM110_ORIG_TD1 0x40007b74u +#define CYDEV_PHUB_TDMEM111_BASE 0x40007b78u +#define CYDEV_PHUB_TDMEM111_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM111_ORIG_TD0 0x40007b78u +#define CYDEV_PHUB_TDMEM111_ORIG_TD1 0x40007b7cu +#define CYDEV_PHUB_TDMEM112_BASE 0x40007b80u +#define CYDEV_PHUB_TDMEM112_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM112_ORIG_TD0 0x40007b80u +#define CYDEV_PHUB_TDMEM112_ORIG_TD1 0x40007b84u +#define CYDEV_PHUB_TDMEM113_BASE 0x40007b88u +#define CYDEV_PHUB_TDMEM113_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM113_ORIG_TD0 0x40007b88u +#define CYDEV_PHUB_TDMEM113_ORIG_TD1 0x40007b8cu +#define CYDEV_PHUB_TDMEM114_BASE 0x40007b90u +#define CYDEV_PHUB_TDMEM114_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM114_ORIG_TD0 0x40007b90u +#define CYDEV_PHUB_TDMEM114_ORIG_TD1 0x40007b94u +#define CYDEV_PHUB_TDMEM115_BASE 0x40007b98u +#define CYDEV_PHUB_TDMEM115_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM115_ORIG_TD0 0x40007b98u +#define CYDEV_PHUB_TDMEM115_ORIG_TD1 0x40007b9cu +#define CYDEV_PHUB_TDMEM116_BASE 0x40007ba0u +#define CYDEV_PHUB_TDMEM116_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM116_ORIG_TD0 0x40007ba0u +#define CYDEV_PHUB_TDMEM116_ORIG_TD1 0x40007ba4u +#define CYDEV_PHUB_TDMEM117_BASE 0x40007ba8u +#define CYDEV_PHUB_TDMEM117_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM117_ORIG_TD0 0x40007ba8u +#define CYDEV_PHUB_TDMEM117_ORIG_TD1 0x40007bacu +#define CYDEV_PHUB_TDMEM118_BASE 0x40007bb0u +#define CYDEV_PHUB_TDMEM118_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM118_ORIG_TD0 0x40007bb0u +#define CYDEV_PHUB_TDMEM118_ORIG_TD1 0x40007bb4u +#define CYDEV_PHUB_TDMEM119_BASE 0x40007bb8u +#define CYDEV_PHUB_TDMEM119_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM119_ORIG_TD0 0x40007bb8u +#define CYDEV_PHUB_TDMEM119_ORIG_TD1 0x40007bbcu +#define CYDEV_PHUB_TDMEM120_BASE 0x40007bc0u +#define CYDEV_PHUB_TDMEM120_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM120_ORIG_TD0 0x40007bc0u +#define CYDEV_PHUB_TDMEM120_ORIG_TD1 0x40007bc4u +#define CYDEV_PHUB_TDMEM121_BASE 0x40007bc8u +#define CYDEV_PHUB_TDMEM121_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM121_ORIG_TD0 0x40007bc8u +#define CYDEV_PHUB_TDMEM121_ORIG_TD1 0x40007bccu +#define CYDEV_PHUB_TDMEM122_BASE 0x40007bd0u +#define CYDEV_PHUB_TDMEM122_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM122_ORIG_TD0 0x40007bd0u +#define CYDEV_PHUB_TDMEM122_ORIG_TD1 0x40007bd4u +#define CYDEV_PHUB_TDMEM123_BASE 0x40007bd8u +#define CYDEV_PHUB_TDMEM123_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM123_ORIG_TD0 0x40007bd8u +#define CYDEV_PHUB_TDMEM123_ORIG_TD1 0x40007bdcu +#define CYDEV_PHUB_TDMEM124_BASE 0x40007be0u +#define CYDEV_PHUB_TDMEM124_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM124_ORIG_TD0 0x40007be0u +#define CYDEV_PHUB_TDMEM124_ORIG_TD1 0x40007be4u +#define CYDEV_PHUB_TDMEM125_BASE 0x40007be8u +#define CYDEV_PHUB_TDMEM125_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM125_ORIG_TD0 0x40007be8u +#define CYDEV_PHUB_TDMEM125_ORIG_TD1 0x40007becu +#define CYDEV_PHUB_TDMEM126_BASE 0x40007bf0u +#define CYDEV_PHUB_TDMEM126_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM126_ORIG_TD0 0x40007bf0u +#define CYDEV_PHUB_TDMEM126_ORIG_TD1 0x40007bf4u +#define CYDEV_PHUB_TDMEM127_BASE 0x40007bf8u +#define CYDEV_PHUB_TDMEM127_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM127_ORIG_TD0 0x40007bf8u +#define CYDEV_PHUB_TDMEM127_ORIG_TD1 0x40007bfcu +#define CYDEV_EE_BASE 0x40008000u +#define CYDEV_EE_SIZE 0x00000800u +#define CYDEV_EE_DATA_MBASE 0x40008000u +#define CYDEV_EE_DATA_MSIZE 0x00000800u +#define CYDEV_CAN0_BASE 0x4000a000u +#define CYDEV_CAN0_SIZE 0x000002a0u +#define CYDEV_CAN0_CSR_BASE 0x4000a000u +#define CYDEV_CAN0_CSR_SIZE 0x00000018u +#define CYDEV_CAN0_CSR_INT_SR 0x4000a000u +#define CYDEV_CAN0_CSR_INT_EN 0x4000a004u +#define CYDEV_CAN0_CSR_BUF_SR 0x4000a008u +#define CYDEV_CAN0_CSR_ERR_SR 0x4000a00cu +#define CYDEV_CAN0_CSR_CMD 0x4000a010u +#define CYDEV_CAN0_CSR_CFG 0x4000a014u +#define CYDEV_CAN0_TX0_BASE 0x4000a020u +#define CYDEV_CAN0_TX0_SIZE 0x00000010u +#define CYDEV_CAN0_TX0_CMD 0x4000a020u +#define CYDEV_CAN0_TX0_ID 0x4000a024u +#define CYDEV_CAN0_TX0_DH 0x4000a028u +#define CYDEV_CAN0_TX0_DL 0x4000a02cu +#define CYDEV_CAN0_TX1_BASE 0x4000a030u +#define CYDEV_CAN0_TX1_SIZE 0x00000010u +#define CYDEV_CAN0_TX1_CMD 0x4000a030u +#define CYDEV_CAN0_TX1_ID 0x4000a034u +#define CYDEV_CAN0_TX1_DH 0x4000a038u +#define CYDEV_CAN0_TX1_DL 0x4000a03cu +#define CYDEV_CAN0_TX2_BASE 0x4000a040u +#define CYDEV_CAN0_TX2_SIZE 0x00000010u +#define CYDEV_CAN0_TX2_CMD 0x4000a040u +#define CYDEV_CAN0_TX2_ID 0x4000a044u +#define CYDEV_CAN0_TX2_DH 0x4000a048u +#define CYDEV_CAN0_TX2_DL 0x4000a04cu +#define CYDEV_CAN0_TX3_BASE 0x4000a050u +#define CYDEV_CAN0_TX3_SIZE 0x00000010u +#define CYDEV_CAN0_TX3_CMD 0x4000a050u +#define CYDEV_CAN0_TX3_ID 0x4000a054u +#define CYDEV_CAN0_TX3_DH 0x4000a058u +#define CYDEV_CAN0_TX3_DL 0x4000a05cu +#define CYDEV_CAN0_TX4_BASE 0x4000a060u +#define CYDEV_CAN0_TX4_SIZE 0x00000010u +#define CYDEV_CAN0_TX4_CMD 0x4000a060u +#define CYDEV_CAN0_TX4_ID 0x4000a064u +#define CYDEV_CAN0_TX4_DH 0x4000a068u +#define CYDEV_CAN0_TX4_DL 0x4000a06cu +#define CYDEV_CAN0_TX5_BASE 0x4000a070u +#define CYDEV_CAN0_TX5_SIZE 0x00000010u +#define CYDEV_CAN0_TX5_CMD 0x4000a070u +#define CYDEV_CAN0_TX5_ID 0x4000a074u +#define CYDEV_CAN0_TX5_DH 0x4000a078u +#define CYDEV_CAN0_TX5_DL 0x4000a07cu +#define CYDEV_CAN0_TX6_BASE 0x4000a080u +#define CYDEV_CAN0_TX6_SIZE 0x00000010u +#define CYDEV_CAN0_TX6_CMD 0x4000a080u +#define CYDEV_CAN0_TX6_ID 0x4000a084u +#define CYDEV_CAN0_TX6_DH 0x4000a088u +#define CYDEV_CAN0_TX6_DL 0x4000a08cu +#define CYDEV_CAN0_TX7_BASE 0x4000a090u +#define CYDEV_CAN0_TX7_SIZE 0x00000010u +#define CYDEV_CAN0_TX7_CMD 0x4000a090u +#define CYDEV_CAN0_TX7_ID 0x4000a094u +#define CYDEV_CAN0_TX7_DH 0x4000a098u +#define CYDEV_CAN0_TX7_DL 0x4000a09cu +#define CYDEV_CAN0_RX0_BASE 0x4000a0a0u +#define CYDEV_CAN0_RX0_SIZE 0x00000020u +#define CYDEV_CAN0_RX0_CMD 0x4000a0a0u +#define CYDEV_CAN0_RX0_ID 0x4000a0a4u +#define CYDEV_CAN0_RX0_DH 0x4000a0a8u +#define CYDEV_CAN0_RX0_DL 0x4000a0acu +#define CYDEV_CAN0_RX0_AMR 0x4000a0b0u +#define CYDEV_CAN0_RX0_ACR 0x4000a0b4u +#define CYDEV_CAN0_RX0_AMRD 0x4000a0b8u +#define CYDEV_CAN0_RX0_ACRD 0x4000a0bcu +#define CYDEV_CAN0_RX1_BASE 0x4000a0c0u +#define CYDEV_CAN0_RX1_SIZE 0x00000020u +#define CYDEV_CAN0_RX1_CMD 0x4000a0c0u +#define CYDEV_CAN0_RX1_ID 0x4000a0c4u +#define CYDEV_CAN0_RX1_DH 0x4000a0c8u +#define CYDEV_CAN0_RX1_DL 0x4000a0ccu +#define CYDEV_CAN0_RX1_AMR 0x4000a0d0u +#define CYDEV_CAN0_RX1_ACR 0x4000a0d4u +#define CYDEV_CAN0_RX1_AMRD 0x4000a0d8u +#define CYDEV_CAN0_RX1_ACRD 0x4000a0dcu +#define CYDEV_CAN0_RX2_BASE 0x4000a0e0u +#define CYDEV_CAN0_RX2_SIZE 0x00000020u +#define CYDEV_CAN0_RX2_CMD 0x4000a0e0u +#define CYDEV_CAN0_RX2_ID 0x4000a0e4u +#define CYDEV_CAN0_RX2_DH 0x4000a0e8u +#define CYDEV_CAN0_RX2_DL 0x4000a0ecu +#define CYDEV_CAN0_RX2_AMR 0x4000a0f0u +#define CYDEV_CAN0_RX2_ACR 0x4000a0f4u +#define CYDEV_CAN0_RX2_AMRD 0x4000a0f8u +#define CYDEV_CAN0_RX2_ACRD 0x4000a0fcu +#define CYDEV_CAN0_RX3_BASE 0x4000a100u +#define CYDEV_CAN0_RX3_SIZE 0x00000020u +#define CYDEV_CAN0_RX3_CMD 0x4000a100u +#define CYDEV_CAN0_RX3_ID 0x4000a104u +#define CYDEV_CAN0_RX3_DH 0x4000a108u +#define CYDEV_CAN0_RX3_DL 0x4000a10cu +#define CYDEV_CAN0_RX3_AMR 0x4000a110u +#define CYDEV_CAN0_RX3_ACR 0x4000a114u +#define CYDEV_CAN0_RX3_AMRD 0x4000a118u +#define CYDEV_CAN0_RX3_ACRD 0x4000a11cu +#define CYDEV_CAN0_RX4_BASE 0x4000a120u +#define CYDEV_CAN0_RX4_SIZE 0x00000020u +#define CYDEV_CAN0_RX4_CMD 0x4000a120u +#define CYDEV_CAN0_RX4_ID 0x4000a124u +#define CYDEV_CAN0_RX4_DH 0x4000a128u +#define CYDEV_CAN0_RX4_DL 0x4000a12cu +#define CYDEV_CAN0_RX4_AMR 0x4000a130u +#define CYDEV_CAN0_RX4_ACR 0x4000a134u +#define CYDEV_CAN0_RX4_AMRD 0x4000a138u +#define CYDEV_CAN0_RX4_ACRD 0x4000a13cu +#define CYDEV_CAN0_RX5_BASE 0x4000a140u +#define CYDEV_CAN0_RX5_SIZE 0x00000020u +#define CYDEV_CAN0_RX5_CMD 0x4000a140u +#define CYDEV_CAN0_RX5_ID 0x4000a144u +#define CYDEV_CAN0_RX5_DH 0x4000a148u +#define CYDEV_CAN0_RX5_DL 0x4000a14cu +#define CYDEV_CAN0_RX5_AMR 0x4000a150u +#define CYDEV_CAN0_RX5_ACR 0x4000a154u +#define CYDEV_CAN0_RX5_AMRD 0x4000a158u +#define CYDEV_CAN0_RX5_ACRD 0x4000a15cu +#define CYDEV_CAN0_RX6_BASE 0x4000a160u +#define CYDEV_CAN0_RX6_SIZE 0x00000020u +#define CYDEV_CAN0_RX6_CMD 0x4000a160u +#define CYDEV_CAN0_RX6_ID 0x4000a164u +#define CYDEV_CAN0_RX6_DH 0x4000a168u +#define CYDEV_CAN0_RX6_DL 0x4000a16cu +#define CYDEV_CAN0_RX6_AMR 0x4000a170u +#define CYDEV_CAN0_RX6_ACR 0x4000a174u +#define CYDEV_CAN0_RX6_AMRD 0x4000a178u +#define CYDEV_CAN0_RX6_ACRD 0x4000a17cu +#define CYDEV_CAN0_RX7_BASE 0x4000a180u +#define CYDEV_CAN0_RX7_SIZE 0x00000020u +#define CYDEV_CAN0_RX7_CMD 0x4000a180u +#define CYDEV_CAN0_RX7_ID 0x4000a184u +#define CYDEV_CAN0_RX7_DH 0x4000a188u +#define CYDEV_CAN0_RX7_DL 0x4000a18cu +#define CYDEV_CAN0_RX7_AMR 0x4000a190u +#define CYDEV_CAN0_RX7_ACR 0x4000a194u +#define CYDEV_CAN0_RX7_AMRD 0x4000a198u +#define CYDEV_CAN0_RX7_ACRD 0x4000a19cu +#define CYDEV_CAN0_RX8_BASE 0x4000a1a0u +#define CYDEV_CAN0_RX8_SIZE 0x00000020u +#define CYDEV_CAN0_RX8_CMD 0x4000a1a0u +#define CYDEV_CAN0_RX8_ID 0x4000a1a4u +#define CYDEV_CAN0_RX8_DH 0x4000a1a8u +#define CYDEV_CAN0_RX8_DL 0x4000a1acu +#define CYDEV_CAN0_RX8_AMR 0x4000a1b0u +#define CYDEV_CAN0_RX8_ACR 0x4000a1b4u +#define CYDEV_CAN0_RX8_AMRD 0x4000a1b8u +#define CYDEV_CAN0_RX8_ACRD 0x4000a1bcu +#define CYDEV_CAN0_RX9_BASE 0x4000a1c0u +#define CYDEV_CAN0_RX9_SIZE 0x00000020u +#define CYDEV_CAN0_RX9_CMD 0x4000a1c0u +#define CYDEV_CAN0_RX9_ID 0x4000a1c4u +#define CYDEV_CAN0_RX9_DH 0x4000a1c8u +#define CYDEV_CAN0_RX9_DL 0x4000a1ccu +#define CYDEV_CAN0_RX9_AMR 0x4000a1d0u +#define CYDEV_CAN0_RX9_ACR 0x4000a1d4u +#define CYDEV_CAN0_RX9_AMRD 0x4000a1d8u +#define CYDEV_CAN0_RX9_ACRD 0x4000a1dcu +#define CYDEV_CAN0_RX10_BASE 0x4000a1e0u +#define CYDEV_CAN0_RX10_SIZE 0x00000020u +#define CYDEV_CAN0_RX10_CMD 0x4000a1e0u +#define CYDEV_CAN0_RX10_ID 0x4000a1e4u +#define CYDEV_CAN0_RX10_DH 0x4000a1e8u +#define CYDEV_CAN0_RX10_DL 0x4000a1ecu +#define CYDEV_CAN0_RX10_AMR 0x4000a1f0u +#define CYDEV_CAN0_RX10_ACR 0x4000a1f4u +#define CYDEV_CAN0_RX10_AMRD 0x4000a1f8u +#define CYDEV_CAN0_RX10_ACRD 0x4000a1fcu +#define CYDEV_CAN0_RX11_BASE 0x4000a200u +#define CYDEV_CAN0_RX11_SIZE 0x00000020u +#define CYDEV_CAN0_RX11_CMD 0x4000a200u +#define CYDEV_CAN0_RX11_ID 0x4000a204u +#define CYDEV_CAN0_RX11_DH 0x4000a208u +#define CYDEV_CAN0_RX11_DL 0x4000a20cu +#define CYDEV_CAN0_RX11_AMR 0x4000a210u +#define CYDEV_CAN0_RX11_ACR 0x4000a214u +#define CYDEV_CAN0_RX11_AMRD 0x4000a218u +#define CYDEV_CAN0_RX11_ACRD 0x4000a21cu +#define CYDEV_CAN0_RX12_BASE 0x4000a220u +#define CYDEV_CAN0_RX12_SIZE 0x00000020u +#define CYDEV_CAN0_RX12_CMD 0x4000a220u +#define CYDEV_CAN0_RX12_ID 0x4000a224u +#define CYDEV_CAN0_RX12_DH 0x4000a228u +#define CYDEV_CAN0_RX12_DL 0x4000a22cu +#define CYDEV_CAN0_RX12_AMR 0x4000a230u +#define CYDEV_CAN0_RX12_ACR 0x4000a234u +#define CYDEV_CAN0_RX12_AMRD 0x4000a238u +#define CYDEV_CAN0_RX12_ACRD 0x4000a23cu +#define CYDEV_CAN0_RX13_BASE 0x4000a240u +#define CYDEV_CAN0_RX13_SIZE 0x00000020u +#define CYDEV_CAN0_RX13_CMD 0x4000a240u +#define CYDEV_CAN0_RX13_ID 0x4000a244u +#define CYDEV_CAN0_RX13_DH 0x4000a248u +#define CYDEV_CAN0_RX13_DL 0x4000a24cu +#define CYDEV_CAN0_RX13_AMR 0x4000a250u +#define CYDEV_CAN0_RX13_ACR 0x4000a254u +#define CYDEV_CAN0_RX13_AMRD 0x4000a258u +#define CYDEV_CAN0_RX13_ACRD 0x4000a25cu +#define CYDEV_CAN0_RX14_BASE 0x4000a260u +#define CYDEV_CAN0_RX14_SIZE 0x00000020u +#define CYDEV_CAN0_RX14_CMD 0x4000a260u +#define CYDEV_CAN0_RX14_ID 0x4000a264u +#define CYDEV_CAN0_RX14_DH 0x4000a268u +#define CYDEV_CAN0_RX14_DL 0x4000a26cu +#define CYDEV_CAN0_RX14_AMR 0x4000a270u +#define CYDEV_CAN0_RX14_ACR 0x4000a274u +#define CYDEV_CAN0_RX14_AMRD 0x4000a278u +#define CYDEV_CAN0_RX14_ACRD 0x4000a27cu +#define CYDEV_CAN0_RX15_BASE 0x4000a280u +#define CYDEV_CAN0_RX15_SIZE 0x00000020u +#define CYDEV_CAN0_RX15_CMD 0x4000a280u +#define CYDEV_CAN0_RX15_ID 0x4000a284u +#define CYDEV_CAN0_RX15_DH 0x4000a288u +#define CYDEV_CAN0_RX15_DL 0x4000a28cu +#define CYDEV_CAN0_RX15_AMR 0x4000a290u +#define CYDEV_CAN0_RX15_ACR 0x4000a294u +#define CYDEV_CAN0_RX15_AMRD 0x4000a298u +#define CYDEV_CAN0_RX15_ACRD 0x4000a29cu +#define CYDEV_DFB0_BASE 0x4000c000u +#define CYDEV_DFB0_SIZE 0x000007b5u +#define CYDEV_DFB0_DPA_SRAM_BASE 0x4000c000u +#define CYDEV_DFB0_DPA_SRAM_SIZE 0x00000200u +#define CYDEV_DFB0_DPA_SRAM_DATA_MBASE 0x4000c000u +#define CYDEV_DFB0_DPA_SRAM_DATA_MSIZE 0x00000200u +#define CYDEV_DFB0_DPB_SRAM_BASE 0x4000c200u +#define CYDEV_DFB0_DPB_SRAM_SIZE 0x00000200u +#define CYDEV_DFB0_DPB_SRAM_DATA_MBASE 0x4000c200u +#define CYDEV_DFB0_DPB_SRAM_DATA_MSIZE 0x00000200u +#define CYDEV_DFB0_CSA_SRAM_BASE 0x4000c400u +#define CYDEV_DFB0_CSA_SRAM_SIZE 0x00000100u +#define CYDEV_DFB0_CSA_SRAM_DATA_MBASE 0x4000c400u +#define CYDEV_DFB0_CSA_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_CSB_SRAM_BASE 0x4000c500u +#define CYDEV_DFB0_CSB_SRAM_SIZE 0x00000100u +#define CYDEV_DFB0_CSB_SRAM_DATA_MBASE 0x4000c500u +#define CYDEV_DFB0_CSB_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_FSM_SRAM_BASE 0x4000c600u +#define CYDEV_DFB0_FSM_SRAM_SIZE 0x00000100u +#define CYDEV_DFB0_FSM_SRAM_DATA_MBASE 0x4000c600u +#define CYDEV_DFB0_FSM_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_ACU_SRAM_BASE 0x4000c700u +#define CYDEV_DFB0_ACU_SRAM_SIZE 0x00000040u +#define CYDEV_DFB0_ACU_SRAM_DATA_MBASE 0x4000c700u +#define CYDEV_DFB0_ACU_SRAM_DATA_MSIZE 0x00000040u +#define CYDEV_DFB0_CR 0x4000c780u +#define CYDEV_DFB0_SR 0x4000c784u +#define CYDEV_DFB0_RAM_EN 0x4000c788u +#define CYDEV_DFB0_RAM_DIR 0x4000c78cu +#define CYDEV_DFB0_SEMA 0x4000c790u +#define CYDEV_DFB0_DSI_CTRL 0x4000c794u +#define CYDEV_DFB0_INT_CTRL 0x4000c798u +#define CYDEV_DFB0_DMA_CTRL 0x4000c79cu +#define CYDEV_DFB0_STAGEA 0x4000c7a0u +#define CYDEV_DFB0_STAGEAM 0x4000c7a1u +#define CYDEV_DFB0_STAGEAH 0x4000c7a2u +#define CYDEV_DFB0_STAGEB 0x4000c7a4u +#define CYDEV_DFB0_STAGEBM 0x4000c7a5u +#define CYDEV_DFB0_STAGEBH 0x4000c7a6u +#define CYDEV_DFB0_HOLDA 0x4000c7a8u +#define CYDEV_DFB0_HOLDAM 0x4000c7a9u +#define CYDEV_DFB0_HOLDAH 0x4000c7aau +#define CYDEV_DFB0_HOLDAS 0x4000c7abu +#define CYDEV_DFB0_HOLDB 0x4000c7acu +#define CYDEV_DFB0_HOLDBM 0x4000c7adu +#define CYDEV_DFB0_HOLDBH 0x4000c7aeu +#define CYDEV_DFB0_HOLDBS 0x4000c7afu +#define CYDEV_DFB0_COHER 0x4000c7b0u +#define CYDEV_DFB0_DALIGN 0x4000c7b4u +#define CYDEV_UCFG_BASE 0x40010000u +#define CYDEV_UCFG_SIZE 0x00005040u +#define CYDEV_UCFG_B0_BASE 0x40010000u +#define CYDEV_UCFG_B0_SIZE 0x00000fefu +#define CYDEV_UCFG_B0_P0_BASE 0x40010000u +#define CYDEV_UCFG_B0_P0_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P0_U0_BASE 0x40010000u +#define CYDEV_UCFG_B0_P0_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT0 0x40010000u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT1 0x40010004u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT2 0x40010008u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT3 0x4001000cu +#define CYDEV_UCFG_B0_P0_U0_PLD_IT4 0x40010010u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT5 0x40010014u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT6 0x40010018u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT7 0x4001001cu +#define CYDEV_UCFG_B0_P0_U0_PLD_IT8 0x40010020u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT9 0x40010024u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT10 0x40010028u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT11 0x4001002cu +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT0 0x40010030u +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT1 0x40010032u +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT2 0x40010034u +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT3 0x40010036u +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST 0x40010038u +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB 0x4001003au +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET 0x4001003cu +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS 0x4001003eu +#define CYDEV_UCFG_B0_P0_U0_CFG0 0x40010040u +#define CYDEV_UCFG_B0_P0_U0_CFG1 0x40010041u +#define CYDEV_UCFG_B0_P0_U0_CFG2 0x40010042u +#define CYDEV_UCFG_B0_P0_U0_CFG3 0x40010043u +#define CYDEV_UCFG_B0_P0_U0_CFG4 0x40010044u +#define CYDEV_UCFG_B0_P0_U0_CFG5 0x40010045u +#define CYDEV_UCFG_B0_P0_U0_CFG6 0x40010046u +#define CYDEV_UCFG_B0_P0_U0_CFG7 0x40010047u +#define CYDEV_UCFG_B0_P0_U0_CFG8 0x40010048u +#define CYDEV_UCFG_B0_P0_U0_CFG9 0x40010049u +#define CYDEV_UCFG_B0_P0_U0_CFG10 0x4001004au +#define CYDEV_UCFG_B0_P0_U0_CFG11 0x4001004bu +#define CYDEV_UCFG_B0_P0_U0_CFG12 0x4001004cu +#define CYDEV_UCFG_B0_P0_U0_CFG13 0x4001004du +#define CYDEV_UCFG_B0_P0_U0_CFG14 0x4001004eu +#define CYDEV_UCFG_B0_P0_U0_CFG15 0x4001004fu +#define CYDEV_UCFG_B0_P0_U0_CFG16 0x40010050u +#define CYDEV_UCFG_B0_P0_U0_CFG17 0x40010051u +#define CYDEV_UCFG_B0_P0_U0_CFG18 0x40010052u +#define CYDEV_UCFG_B0_P0_U0_CFG19 0x40010053u +#define CYDEV_UCFG_B0_P0_U0_CFG20 0x40010054u +#define CYDEV_UCFG_B0_P0_U0_CFG21 0x40010055u +#define CYDEV_UCFG_B0_P0_U0_CFG22 0x40010056u +#define CYDEV_UCFG_B0_P0_U0_CFG23 0x40010057u +#define CYDEV_UCFG_B0_P0_U0_CFG24 0x40010058u +#define CYDEV_UCFG_B0_P0_U0_CFG25 0x40010059u +#define CYDEV_UCFG_B0_P0_U0_CFG26 0x4001005au +#define CYDEV_UCFG_B0_P0_U0_CFG27 0x4001005bu +#define CYDEV_UCFG_B0_P0_U0_CFG28 0x4001005cu +#define CYDEV_UCFG_B0_P0_U0_CFG29 0x4001005du +#define CYDEV_UCFG_B0_P0_U0_CFG30 0x4001005eu +#define CYDEV_UCFG_B0_P0_U0_CFG31 0x4001005fu +#define CYDEV_UCFG_B0_P0_U0_DCFG0 0x40010060u +#define CYDEV_UCFG_B0_P0_U0_DCFG1 0x40010062u +#define CYDEV_UCFG_B0_P0_U0_DCFG2 0x40010064u +#define CYDEV_UCFG_B0_P0_U0_DCFG3 0x40010066u +#define CYDEV_UCFG_B0_P0_U0_DCFG4 0x40010068u +#define CYDEV_UCFG_B0_P0_U0_DCFG5 0x4001006au +#define CYDEV_UCFG_B0_P0_U0_DCFG6 0x4001006cu +#define CYDEV_UCFG_B0_P0_U0_DCFG7 0x4001006eu +#define CYDEV_UCFG_B0_P0_U1_BASE 0x40010080u +#define CYDEV_UCFG_B0_P0_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT0 0x40010080u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT1 0x40010084u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT2 0x40010088u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT3 0x4001008cu +#define CYDEV_UCFG_B0_P0_U1_PLD_IT4 0x40010090u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT5 0x40010094u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT6 0x40010098u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT7 0x4001009cu +#define CYDEV_UCFG_B0_P0_U1_PLD_IT8 0x400100a0u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT9 0x400100a4u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT10 0x400100a8u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT11 0x400100acu +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT0 0x400100b0u +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT1 0x400100b2u +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT2 0x400100b4u +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT3 0x400100b6u +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST 0x400100b8u +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB 0x400100bau +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET 0x400100bcu +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS 0x400100beu +#define CYDEV_UCFG_B0_P0_U1_CFG0 0x400100c0u +#define CYDEV_UCFG_B0_P0_U1_CFG1 0x400100c1u +#define CYDEV_UCFG_B0_P0_U1_CFG2 0x400100c2u +#define CYDEV_UCFG_B0_P0_U1_CFG3 0x400100c3u +#define CYDEV_UCFG_B0_P0_U1_CFG4 0x400100c4u +#define CYDEV_UCFG_B0_P0_U1_CFG5 0x400100c5u +#define CYDEV_UCFG_B0_P0_U1_CFG6 0x400100c6u +#define CYDEV_UCFG_B0_P0_U1_CFG7 0x400100c7u +#define CYDEV_UCFG_B0_P0_U1_CFG8 0x400100c8u +#define CYDEV_UCFG_B0_P0_U1_CFG9 0x400100c9u +#define CYDEV_UCFG_B0_P0_U1_CFG10 0x400100cau +#define CYDEV_UCFG_B0_P0_U1_CFG11 0x400100cbu +#define CYDEV_UCFG_B0_P0_U1_CFG12 0x400100ccu +#define CYDEV_UCFG_B0_P0_U1_CFG13 0x400100cdu +#define CYDEV_UCFG_B0_P0_U1_CFG14 0x400100ceu +#define CYDEV_UCFG_B0_P0_U1_CFG15 0x400100cfu +#define CYDEV_UCFG_B0_P0_U1_CFG16 0x400100d0u +#define CYDEV_UCFG_B0_P0_U1_CFG17 0x400100d1u +#define CYDEV_UCFG_B0_P0_U1_CFG18 0x400100d2u +#define CYDEV_UCFG_B0_P0_U1_CFG19 0x400100d3u +#define CYDEV_UCFG_B0_P0_U1_CFG20 0x400100d4u +#define CYDEV_UCFG_B0_P0_U1_CFG21 0x400100d5u +#define CYDEV_UCFG_B0_P0_U1_CFG22 0x400100d6u +#define CYDEV_UCFG_B0_P0_U1_CFG23 0x400100d7u +#define CYDEV_UCFG_B0_P0_U1_CFG24 0x400100d8u +#define CYDEV_UCFG_B0_P0_U1_CFG25 0x400100d9u +#define CYDEV_UCFG_B0_P0_U1_CFG26 0x400100dau +#define CYDEV_UCFG_B0_P0_U1_CFG27 0x400100dbu +#define CYDEV_UCFG_B0_P0_U1_CFG28 0x400100dcu +#define CYDEV_UCFG_B0_P0_U1_CFG29 0x400100ddu +#define CYDEV_UCFG_B0_P0_U1_CFG30 0x400100deu +#define CYDEV_UCFG_B0_P0_U1_CFG31 0x400100dfu +#define CYDEV_UCFG_B0_P0_U1_DCFG0 0x400100e0u +#define CYDEV_UCFG_B0_P0_U1_DCFG1 0x400100e2u +#define CYDEV_UCFG_B0_P0_U1_DCFG2 0x400100e4u +#define CYDEV_UCFG_B0_P0_U1_DCFG3 0x400100e6u +#define CYDEV_UCFG_B0_P0_U1_DCFG4 0x400100e8u +#define CYDEV_UCFG_B0_P0_U1_DCFG5 0x400100eau +#define CYDEV_UCFG_B0_P0_U1_DCFG6 0x400100ecu +#define CYDEV_UCFG_B0_P0_U1_DCFG7 0x400100eeu +#define CYDEV_UCFG_B0_P0_ROUTE_BASE 0x40010100u +#define CYDEV_UCFG_B0_P0_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P1_BASE 0x40010200u +#define CYDEV_UCFG_B0_P1_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P1_U0_BASE 0x40010200u +#define CYDEV_UCFG_B0_P1_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT0 0x40010200u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT1 0x40010204u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT2 0x40010208u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT3 0x4001020cu +#define CYDEV_UCFG_B0_P1_U0_PLD_IT4 0x40010210u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT5 0x40010214u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT6 0x40010218u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT7 0x4001021cu +#define CYDEV_UCFG_B0_P1_U0_PLD_IT8 0x40010220u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT9 0x40010224u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT10 0x40010228u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT11 0x4001022cu +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT0 0x40010230u +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT1 0x40010232u +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT2 0x40010234u +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT3 0x40010236u +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST 0x40010238u +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB 0x4001023au +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET 0x4001023cu +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS 0x4001023eu +#define CYDEV_UCFG_B0_P1_U0_CFG0 0x40010240u +#define CYDEV_UCFG_B0_P1_U0_CFG1 0x40010241u +#define CYDEV_UCFG_B0_P1_U0_CFG2 0x40010242u +#define CYDEV_UCFG_B0_P1_U0_CFG3 0x40010243u +#define CYDEV_UCFG_B0_P1_U0_CFG4 0x40010244u +#define CYDEV_UCFG_B0_P1_U0_CFG5 0x40010245u +#define CYDEV_UCFG_B0_P1_U0_CFG6 0x40010246u +#define CYDEV_UCFG_B0_P1_U0_CFG7 0x40010247u +#define CYDEV_UCFG_B0_P1_U0_CFG8 0x40010248u +#define CYDEV_UCFG_B0_P1_U0_CFG9 0x40010249u +#define CYDEV_UCFG_B0_P1_U0_CFG10 0x4001024au +#define CYDEV_UCFG_B0_P1_U0_CFG11 0x4001024bu +#define CYDEV_UCFG_B0_P1_U0_CFG12 0x4001024cu +#define CYDEV_UCFG_B0_P1_U0_CFG13 0x4001024du +#define CYDEV_UCFG_B0_P1_U0_CFG14 0x4001024eu +#define CYDEV_UCFG_B0_P1_U0_CFG15 0x4001024fu +#define CYDEV_UCFG_B0_P1_U0_CFG16 0x40010250u +#define CYDEV_UCFG_B0_P1_U0_CFG17 0x40010251u +#define CYDEV_UCFG_B0_P1_U0_CFG18 0x40010252u +#define CYDEV_UCFG_B0_P1_U0_CFG19 0x40010253u +#define CYDEV_UCFG_B0_P1_U0_CFG20 0x40010254u +#define CYDEV_UCFG_B0_P1_U0_CFG21 0x40010255u +#define CYDEV_UCFG_B0_P1_U0_CFG22 0x40010256u +#define CYDEV_UCFG_B0_P1_U0_CFG23 0x40010257u +#define CYDEV_UCFG_B0_P1_U0_CFG24 0x40010258u +#define CYDEV_UCFG_B0_P1_U0_CFG25 0x40010259u +#define CYDEV_UCFG_B0_P1_U0_CFG26 0x4001025au +#define CYDEV_UCFG_B0_P1_U0_CFG27 0x4001025bu +#define CYDEV_UCFG_B0_P1_U0_CFG28 0x4001025cu +#define CYDEV_UCFG_B0_P1_U0_CFG29 0x4001025du +#define CYDEV_UCFG_B0_P1_U0_CFG30 0x4001025eu +#define CYDEV_UCFG_B0_P1_U0_CFG31 0x4001025fu +#define CYDEV_UCFG_B0_P1_U0_DCFG0 0x40010260u +#define CYDEV_UCFG_B0_P1_U0_DCFG1 0x40010262u +#define CYDEV_UCFG_B0_P1_U0_DCFG2 0x40010264u +#define CYDEV_UCFG_B0_P1_U0_DCFG3 0x40010266u +#define CYDEV_UCFG_B0_P1_U0_DCFG4 0x40010268u +#define CYDEV_UCFG_B0_P1_U0_DCFG5 0x4001026au +#define CYDEV_UCFG_B0_P1_U0_DCFG6 0x4001026cu +#define CYDEV_UCFG_B0_P1_U0_DCFG7 0x4001026eu +#define CYDEV_UCFG_B0_P1_U1_BASE 0x40010280u +#define CYDEV_UCFG_B0_P1_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT0 0x40010280u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT1 0x40010284u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT2 0x40010288u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT3 0x4001028cu +#define CYDEV_UCFG_B0_P1_U1_PLD_IT4 0x40010290u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT5 0x40010294u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT6 0x40010298u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT7 0x4001029cu +#define CYDEV_UCFG_B0_P1_U1_PLD_IT8 0x400102a0u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT9 0x400102a4u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT10 0x400102a8u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT11 0x400102acu +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT0 0x400102b0u +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT1 0x400102b2u +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT2 0x400102b4u +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT3 0x400102b6u +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST 0x400102b8u +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB 0x400102bau +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET 0x400102bcu +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS 0x400102beu +#define CYDEV_UCFG_B0_P1_U1_CFG0 0x400102c0u +#define CYDEV_UCFG_B0_P1_U1_CFG1 0x400102c1u +#define CYDEV_UCFG_B0_P1_U1_CFG2 0x400102c2u +#define CYDEV_UCFG_B0_P1_U1_CFG3 0x400102c3u +#define CYDEV_UCFG_B0_P1_U1_CFG4 0x400102c4u +#define CYDEV_UCFG_B0_P1_U1_CFG5 0x400102c5u +#define CYDEV_UCFG_B0_P1_U1_CFG6 0x400102c6u +#define CYDEV_UCFG_B0_P1_U1_CFG7 0x400102c7u +#define CYDEV_UCFG_B0_P1_U1_CFG8 0x400102c8u +#define CYDEV_UCFG_B0_P1_U1_CFG9 0x400102c9u +#define CYDEV_UCFG_B0_P1_U1_CFG10 0x400102cau +#define CYDEV_UCFG_B0_P1_U1_CFG11 0x400102cbu +#define CYDEV_UCFG_B0_P1_U1_CFG12 0x400102ccu +#define CYDEV_UCFG_B0_P1_U1_CFG13 0x400102cdu +#define CYDEV_UCFG_B0_P1_U1_CFG14 0x400102ceu +#define CYDEV_UCFG_B0_P1_U1_CFG15 0x400102cfu +#define CYDEV_UCFG_B0_P1_U1_CFG16 0x400102d0u +#define CYDEV_UCFG_B0_P1_U1_CFG17 0x400102d1u +#define CYDEV_UCFG_B0_P1_U1_CFG18 0x400102d2u +#define CYDEV_UCFG_B0_P1_U1_CFG19 0x400102d3u +#define CYDEV_UCFG_B0_P1_U1_CFG20 0x400102d4u +#define CYDEV_UCFG_B0_P1_U1_CFG21 0x400102d5u +#define CYDEV_UCFG_B0_P1_U1_CFG22 0x400102d6u +#define CYDEV_UCFG_B0_P1_U1_CFG23 0x400102d7u +#define CYDEV_UCFG_B0_P1_U1_CFG24 0x400102d8u +#define CYDEV_UCFG_B0_P1_U1_CFG25 0x400102d9u +#define CYDEV_UCFG_B0_P1_U1_CFG26 0x400102dau +#define CYDEV_UCFG_B0_P1_U1_CFG27 0x400102dbu +#define CYDEV_UCFG_B0_P1_U1_CFG28 0x400102dcu +#define CYDEV_UCFG_B0_P1_U1_CFG29 0x400102ddu +#define CYDEV_UCFG_B0_P1_U1_CFG30 0x400102deu +#define CYDEV_UCFG_B0_P1_U1_CFG31 0x400102dfu +#define CYDEV_UCFG_B0_P1_U1_DCFG0 0x400102e0u +#define CYDEV_UCFG_B0_P1_U1_DCFG1 0x400102e2u +#define CYDEV_UCFG_B0_P1_U1_DCFG2 0x400102e4u +#define CYDEV_UCFG_B0_P1_U1_DCFG3 0x400102e6u +#define CYDEV_UCFG_B0_P1_U1_DCFG4 0x400102e8u +#define CYDEV_UCFG_B0_P1_U1_DCFG5 0x400102eau +#define CYDEV_UCFG_B0_P1_U1_DCFG6 0x400102ecu +#define CYDEV_UCFG_B0_P1_U1_DCFG7 0x400102eeu +#define CYDEV_UCFG_B0_P1_ROUTE_BASE 0x40010300u +#define CYDEV_UCFG_B0_P1_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P2_BASE 0x40010400u +#define CYDEV_UCFG_B0_P2_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P2_U0_BASE 0x40010400u +#define CYDEV_UCFG_B0_P2_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT0 0x40010400u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT1 0x40010404u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT2 0x40010408u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT3 0x4001040cu +#define CYDEV_UCFG_B0_P2_U0_PLD_IT4 0x40010410u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT5 0x40010414u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT6 0x40010418u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT7 0x4001041cu +#define CYDEV_UCFG_B0_P2_U0_PLD_IT8 0x40010420u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT9 0x40010424u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT10 0x40010428u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT11 0x4001042cu +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT0 0x40010430u +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT1 0x40010432u +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT2 0x40010434u +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT3 0x40010436u +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST 0x40010438u +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB 0x4001043au +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET 0x4001043cu +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS 0x4001043eu +#define CYDEV_UCFG_B0_P2_U0_CFG0 0x40010440u +#define CYDEV_UCFG_B0_P2_U0_CFG1 0x40010441u +#define CYDEV_UCFG_B0_P2_U0_CFG2 0x40010442u +#define CYDEV_UCFG_B0_P2_U0_CFG3 0x40010443u +#define CYDEV_UCFG_B0_P2_U0_CFG4 0x40010444u +#define CYDEV_UCFG_B0_P2_U0_CFG5 0x40010445u +#define CYDEV_UCFG_B0_P2_U0_CFG6 0x40010446u +#define CYDEV_UCFG_B0_P2_U0_CFG7 0x40010447u +#define CYDEV_UCFG_B0_P2_U0_CFG8 0x40010448u +#define CYDEV_UCFG_B0_P2_U0_CFG9 0x40010449u +#define CYDEV_UCFG_B0_P2_U0_CFG10 0x4001044au +#define CYDEV_UCFG_B0_P2_U0_CFG11 0x4001044bu +#define CYDEV_UCFG_B0_P2_U0_CFG12 0x4001044cu +#define CYDEV_UCFG_B0_P2_U0_CFG13 0x4001044du +#define CYDEV_UCFG_B0_P2_U0_CFG14 0x4001044eu +#define CYDEV_UCFG_B0_P2_U0_CFG15 0x4001044fu +#define CYDEV_UCFG_B0_P2_U0_CFG16 0x40010450u +#define CYDEV_UCFG_B0_P2_U0_CFG17 0x40010451u +#define CYDEV_UCFG_B0_P2_U0_CFG18 0x40010452u +#define CYDEV_UCFG_B0_P2_U0_CFG19 0x40010453u +#define CYDEV_UCFG_B0_P2_U0_CFG20 0x40010454u +#define CYDEV_UCFG_B0_P2_U0_CFG21 0x40010455u +#define CYDEV_UCFG_B0_P2_U0_CFG22 0x40010456u +#define CYDEV_UCFG_B0_P2_U0_CFG23 0x40010457u +#define CYDEV_UCFG_B0_P2_U0_CFG24 0x40010458u +#define CYDEV_UCFG_B0_P2_U0_CFG25 0x40010459u +#define CYDEV_UCFG_B0_P2_U0_CFG26 0x4001045au +#define CYDEV_UCFG_B0_P2_U0_CFG27 0x4001045bu +#define CYDEV_UCFG_B0_P2_U0_CFG28 0x4001045cu +#define CYDEV_UCFG_B0_P2_U0_CFG29 0x4001045du +#define CYDEV_UCFG_B0_P2_U0_CFG30 0x4001045eu +#define CYDEV_UCFG_B0_P2_U0_CFG31 0x4001045fu +#define CYDEV_UCFG_B0_P2_U0_DCFG0 0x40010460u +#define CYDEV_UCFG_B0_P2_U0_DCFG1 0x40010462u +#define CYDEV_UCFG_B0_P2_U0_DCFG2 0x40010464u +#define CYDEV_UCFG_B0_P2_U0_DCFG3 0x40010466u +#define CYDEV_UCFG_B0_P2_U0_DCFG4 0x40010468u +#define CYDEV_UCFG_B0_P2_U0_DCFG5 0x4001046au +#define CYDEV_UCFG_B0_P2_U0_DCFG6 0x4001046cu +#define CYDEV_UCFG_B0_P2_U0_DCFG7 0x4001046eu +#define CYDEV_UCFG_B0_P2_U1_BASE 0x40010480u +#define CYDEV_UCFG_B0_P2_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT0 0x40010480u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT1 0x40010484u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT2 0x40010488u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT3 0x4001048cu +#define CYDEV_UCFG_B0_P2_U1_PLD_IT4 0x40010490u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT5 0x40010494u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT6 0x40010498u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT7 0x4001049cu +#define CYDEV_UCFG_B0_P2_U1_PLD_IT8 0x400104a0u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT9 0x400104a4u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT10 0x400104a8u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT11 0x400104acu +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT0 0x400104b0u +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT1 0x400104b2u +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT2 0x400104b4u +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT3 0x400104b6u +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST 0x400104b8u +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB 0x400104bau +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET 0x400104bcu +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS 0x400104beu +#define CYDEV_UCFG_B0_P2_U1_CFG0 0x400104c0u +#define CYDEV_UCFG_B0_P2_U1_CFG1 0x400104c1u +#define CYDEV_UCFG_B0_P2_U1_CFG2 0x400104c2u +#define CYDEV_UCFG_B0_P2_U1_CFG3 0x400104c3u +#define CYDEV_UCFG_B0_P2_U1_CFG4 0x400104c4u +#define CYDEV_UCFG_B0_P2_U1_CFG5 0x400104c5u +#define CYDEV_UCFG_B0_P2_U1_CFG6 0x400104c6u +#define CYDEV_UCFG_B0_P2_U1_CFG7 0x400104c7u +#define CYDEV_UCFG_B0_P2_U1_CFG8 0x400104c8u +#define CYDEV_UCFG_B0_P2_U1_CFG9 0x400104c9u +#define CYDEV_UCFG_B0_P2_U1_CFG10 0x400104cau +#define CYDEV_UCFG_B0_P2_U1_CFG11 0x400104cbu +#define CYDEV_UCFG_B0_P2_U1_CFG12 0x400104ccu +#define CYDEV_UCFG_B0_P2_U1_CFG13 0x400104cdu +#define CYDEV_UCFG_B0_P2_U1_CFG14 0x400104ceu +#define CYDEV_UCFG_B0_P2_U1_CFG15 0x400104cfu +#define CYDEV_UCFG_B0_P2_U1_CFG16 0x400104d0u +#define CYDEV_UCFG_B0_P2_U1_CFG17 0x400104d1u +#define CYDEV_UCFG_B0_P2_U1_CFG18 0x400104d2u +#define CYDEV_UCFG_B0_P2_U1_CFG19 0x400104d3u +#define CYDEV_UCFG_B0_P2_U1_CFG20 0x400104d4u +#define CYDEV_UCFG_B0_P2_U1_CFG21 0x400104d5u +#define CYDEV_UCFG_B0_P2_U1_CFG22 0x400104d6u +#define CYDEV_UCFG_B0_P2_U1_CFG23 0x400104d7u +#define CYDEV_UCFG_B0_P2_U1_CFG24 0x400104d8u +#define CYDEV_UCFG_B0_P2_U1_CFG25 0x400104d9u +#define CYDEV_UCFG_B0_P2_U1_CFG26 0x400104dau +#define CYDEV_UCFG_B0_P2_U1_CFG27 0x400104dbu +#define CYDEV_UCFG_B0_P2_U1_CFG28 0x400104dcu +#define CYDEV_UCFG_B0_P2_U1_CFG29 0x400104ddu +#define CYDEV_UCFG_B0_P2_U1_CFG30 0x400104deu +#define CYDEV_UCFG_B0_P2_U1_CFG31 0x400104dfu +#define CYDEV_UCFG_B0_P2_U1_DCFG0 0x400104e0u +#define CYDEV_UCFG_B0_P2_U1_DCFG1 0x400104e2u +#define CYDEV_UCFG_B0_P2_U1_DCFG2 0x400104e4u +#define CYDEV_UCFG_B0_P2_U1_DCFG3 0x400104e6u +#define CYDEV_UCFG_B0_P2_U1_DCFG4 0x400104e8u +#define CYDEV_UCFG_B0_P2_U1_DCFG5 0x400104eau +#define CYDEV_UCFG_B0_P2_U1_DCFG6 0x400104ecu +#define CYDEV_UCFG_B0_P2_U1_DCFG7 0x400104eeu +#define CYDEV_UCFG_B0_P2_ROUTE_BASE 0x40010500u +#define CYDEV_UCFG_B0_P2_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P3_BASE 0x40010600u +#define CYDEV_UCFG_B0_P3_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P3_U0_BASE 0x40010600u +#define CYDEV_UCFG_B0_P3_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT0 0x40010600u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT1 0x40010604u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT2 0x40010608u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT3 0x4001060cu +#define CYDEV_UCFG_B0_P3_U0_PLD_IT4 0x40010610u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT5 0x40010614u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT6 0x40010618u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT7 0x4001061cu +#define CYDEV_UCFG_B0_P3_U0_PLD_IT8 0x40010620u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT9 0x40010624u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT10 0x40010628u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT11 0x4001062cu +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT0 0x40010630u +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT1 0x40010632u +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT2 0x40010634u +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT3 0x40010636u +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST 0x40010638u +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB 0x4001063au +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET 0x4001063cu +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS 0x4001063eu +#define CYDEV_UCFG_B0_P3_U0_CFG0 0x40010640u +#define CYDEV_UCFG_B0_P3_U0_CFG1 0x40010641u +#define CYDEV_UCFG_B0_P3_U0_CFG2 0x40010642u +#define CYDEV_UCFG_B0_P3_U0_CFG3 0x40010643u +#define CYDEV_UCFG_B0_P3_U0_CFG4 0x40010644u +#define CYDEV_UCFG_B0_P3_U0_CFG5 0x40010645u +#define CYDEV_UCFG_B0_P3_U0_CFG6 0x40010646u +#define CYDEV_UCFG_B0_P3_U0_CFG7 0x40010647u +#define CYDEV_UCFG_B0_P3_U0_CFG8 0x40010648u +#define CYDEV_UCFG_B0_P3_U0_CFG9 0x40010649u +#define CYDEV_UCFG_B0_P3_U0_CFG10 0x4001064au +#define CYDEV_UCFG_B0_P3_U0_CFG11 0x4001064bu +#define CYDEV_UCFG_B0_P3_U0_CFG12 0x4001064cu +#define CYDEV_UCFG_B0_P3_U0_CFG13 0x4001064du +#define CYDEV_UCFG_B0_P3_U0_CFG14 0x4001064eu +#define CYDEV_UCFG_B0_P3_U0_CFG15 0x4001064fu +#define CYDEV_UCFG_B0_P3_U0_CFG16 0x40010650u +#define CYDEV_UCFG_B0_P3_U0_CFG17 0x40010651u +#define CYDEV_UCFG_B0_P3_U0_CFG18 0x40010652u +#define CYDEV_UCFG_B0_P3_U0_CFG19 0x40010653u +#define CYDEV_UCFG_B0_P3_U0_CFG20 0x40010654u +#define CYDEV_UCFG_B0_P3_U0_CFG21 0x40010655u +#define CYDEV_UCFG_B0_P3_U0_CFG22 0x40010656u +#define CYDEV_UCFG_B0_P3_U0_CFG23 0x40010657u +#define CYDEV_UCFG_B0_P3_U0_CFG24 0x40010658u +#define CYDEV_UCFG_B0_P3_U0_CFG25 0x40010659u +#define CYDEV_UCFG_B0_P3_U0_CFG26 0x4001065au +#define CYDEV_UCFG_B0_P3_U0_CFG27 0x4001065bu +#define CYDEV_UCFG_B0_P3_U0_CFG28 0x4001065cu +#define CYDEV_UCFG_B0_P3_U0_CFG29 0x4001065du +#define CYDEV_UCFG_B0_P3_U0_CFG30 0x4001065eu +#define CYDEV_UCFG_B0_P3_U0_CFG31 0x4001065fu +#define CYDEV_UCFG_B0_P3_U0_DCFG0 0x40010660u +#define CYDEV_UCFG_B0_P3_U0_DCFG1 0x40010662u +#define CYDEV_UCFG_B0_P3_U0_DCFG2 0x40010664u +#define CYDEV_UCFG_B0_P3_U0_DCFG3 0x40010666u +#define CYDEV_UCFG_B0_P3_U0_DCFG4 0x40010668u +#define CYDEV_UCFG_B0_P3_U0_DCFG5 0x4001066au +#define CYDEV_UCFG_B0_P3_U0_DCFG6 0x4001066cu +#define CYDEV_UCFG_B0_P3_U0_DCFG7 0x4001066eu +#define CYDEV_UCFG_B0_P3_U1_BASE 0x40010680u +#define CYDEV_UCFG_B0_P3_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT0 0x40010680u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT1 0x40010684u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT2 0x40010688u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT3 0x4001068cu +#define CYDEV_UCFG_B0_P3_U1_PLD_IT4 0x40010690u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT5 0x40010694u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT6 0x40010698u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT7 0x4001069cu +#define CYDEV_UCFG_B0_P3_U1_PLD_IT8 0x400106a0u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT9 0x400106a4u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT10 0x400106a8u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT11 0x400106acu +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT0 0x400106b0u +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT1 0x400106b2u +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT2 0x400106b4u +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT3 0x400106b6u +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST 0x400106b8u +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB 0x400106bau +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET 0x400106bcu +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS 0x400106beu +#define CYDEV_UCFG_B0_P3_U1_CFG0 0x400106c0u +#define CYDEV_UCFG_B0_P3_U1_CFG1 0x400106c1u +#define CYDEV_UCFG_B0_P3_U1_CFG2 0x400106c2u +#define CYDEV_UCFG_B0_P3_U1_CFG3 0x400106c3u +#define CYDEV_UCFG_B0_P3_U1_CFG4 0x400106c4u +#define CYDEV_UCFG_B0_P3_U1_CFG5 0x400106c5u +#define CYDEV_UCFG_B0_P3_U1_CFG6 0x400106c6u +#define CYDEV_UCFG_B0_P3_U1_CFG7 0x400106c7u +#define CYDEV_UCFG_B0_P3_U1_CFG8 0x400106c8u +#define CYDEV_UCFG_B0_P3_U1_CFG9 0x400106c9u +#define CYDEV_UCFG_B0_P3_U1_CFG10 0x400106cau +#define CYDEV_UCFG_B0_P3_U1_CFG11 0x400106cbu +#define CYDEV_UCFG_B0_P3_U1_CFG12 0x400106ccu +#define CYDEV_UCFG_B0_P3_U1_CFG13 0x400106cdu +#define CYDEV_UCFG_B0_P3_U1_CFG14 0x400106ceu +#define CYDEV_UCFG_B0_P3_U1_CFG15 0x400106cfu +#define CYDEV_UCFG_B0_P3_U1_CFG16 0x400106d0u +#define CYDEV_UCFG_B0_P3_U1_CFG17 0x400106d1u +#define CYDEV_UCFG_B0_P3_U1_CFG18 0x400106d2u +#define CYDEV_UCFG_B0_P3_U1_CFG19 0x400106d3u +#define CYDEV_UCFG_B0_P3_U1_CFG20 0x400106d4u +#define CYDEV_UCFG_B0_P3_U1_CFG21 0x400106d5u +#define CYDEV_UCFG_B0_P3_U1_CFG22 0x400106d6u +#define CYDEV_UCFG_B0_P3_U1_CFG23 0x400106d7u +#define CYDEV_UCFG_B0_P3_U1_CFG24 0x400106d8u +#define CYDEV_UCFG_B0_P3_U1_CFG25 0x400106d9u +#define CYDEV_UCFG_B0_P3_U1_CFG26 0x400106dau +#define CYDEV_UCFG_B0_P3_U1_CFG27 0x400106dbu +#define CYDEV_UCFG_B0_P3_U1_CFG28 0x400106dcu +#define CYDEV_UCFG_B0_P3_U1_CFG29 0x400106ddu +#define CYDEV_UCFG_B0_P3_U1_CFG30 0x400106deu +#define CYDEV_UCFG_B0_P3_U1_CFG31 0x400106dfu +#define CYDEV_UCFG_B0_P3_U1_DCFG0 0x400106e0u +#define CYDEV_UCFG_B0_P3_U1_DCFG1 0x400106e2u +#define CYDEV_UCFG_B0_P3_U1_DCFG2 0x400106e4u +#define CYDEV_UCFG_B0_P3_U1_DCFG3 0x400106e6u +#define CYDEV_UCFG_B0_P3_U1_DCFG4 0x400106e8u +#define CYDEV_UCFG_B0_P3_U1_DCFG5 0x400106eau +#define CYDEV_UCFG_B0_P3_U1_DCFG6 0x400106ecu +#define CYDEV_UCFG_B0_P3_U1_DCFG7 0x400106eeu +#define CYDEV_UCFG_B0_P3_ROUTE_BASE 0x40010700u +#define CYDEV_UCFG_B0_P3_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P4_BASE 0x40010800u +#define CYDEV_UCFG_B0_P4_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P4_U0_BASE 0x40010800u +#define CYDEV_UCFG_B0_P4_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT0 0x40010800u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT1 0x40010804u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT2 0x40010808u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT3 0x4001080cu +#define CYDEV_UCFG_B0_P4_U0_PLD_IT4 0x40010810u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT5 0x40010814u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT6 0x40010818u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT7 0x4001081cu +#define CYDEV_UCFG_B0_P4_U0_PLD_IT8 0x40010820u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT9 0x40010824u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT10 0x40010828u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT11 0x4001082cu +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT0 0x40010830u +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT1 0x40010832u +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT2 0x40010834u +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT3 0x40010836u +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST 0x40010838u +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB 0x4001083au +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET 0x4001083cu +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS 0x4001083eu +#define CYDEV_UCFG_B0_P4_U0_CFG0 0x40010840u +#define CYDEV_UCFG_B0_P4_U0_CFG1 0x40010841u +#define CYDEV_UCFG_B0_P4_U0_CFG2 0x40010842u +#define CYDEV_UCFG_B0_P4_U0_CFG3 0x40010843u +#define CYDEV_UCFG_B0_P4_U0_CFG4 0x40010844u +#define CYDEV_UCFG_B0_P4_U0_CFG5 0x40010845u +#define CYDEV_UCFG_B0_P4_U0_CFG6 0x40010846u +#define CYDEV_UCFG_B0_P4_U0_CFG7 0x40010847u +#define CYDEV_UCFG_B0_P4_U0_CFG8 0x40010848u +#define CYDEV_UCFG_B0_P4_U0_CFG9 0x40010849u +#define CYDEV_UCFG_B0_P4_U0_CFG10 0x4001084au +#define CYDEV_UCFG_B0_P4_U0_CFG11 0x4001084bu +#define CYDEV_UCFG_B0_P4_U0_CFG12 0x4001084cu +#define CYDEV_UCFG_B0_P4_U0_CFG13 0x4001084du +#define CYDEV_UCFG_B0_P4_U0_CFG14 0x4001084eu +#define CYDEV_UCFG_B0_P4_U0_CFG15 0x4001084fu +#define CYDEV_UCFG_B0_P4_U0_CFG16 0x40010850u +#define CYDEV_UCFG_B0_P4_U0_CFG17 0x40010851u +#define CYDEV_UCFG_B0_P4_U0_CFG18 0x40010852u +#define CYDEV_UCFG_B0_P4_U0_CFG19 0x40010853u +#define CYDEV_UCFG_B0_P4_U0_CFG20 0x40010854u +#define CYDEV_UCFG_B0_P4_U0_CFG21 0x40010855u +#define CYDEV_UCFG_B0_P4_U0_CFG22 0x40010856u +#define CYDEV_UCFG_B0_P4_U0_CFG23 0x40010857u +#define CYDEV_UCFG_B0_P4_U0_CFG24 0x40010858u +#define CYDEV_UCFG_B0_P4_U0_CFG25 0x40010859u +#define CYDEV_UCFG_B0_P4_U0_CFG26 0x4001085au +#define CYDEV_UCFG_B0_P4_U0_CFG27 0x4001085bu +#define CYDEV_UCFG_B0_P4_U0_CFG28 0x4001085cu +#define CYDEV_UCFG_B0_P4_U0_CFG29 0x4001085du +#define CYDEV_UCFG_B0_P4_U0_CFG30 0x4001085eu +#define CYDEV_UCFG_B0_P4_U0_CFG31 0x4001085fu +#define CYDEV_UCFG_B0_P4_U0_DCFG0 0x40010860u +#define CYDEV_UCFG_B0_P4_U0_DCFG1 0x40010862u +#define CYDEV_UCFG_B0_P4_U0_DCFG2 0x40010864u +#define CYDEV_UCFG_B0_P4_U0_DCFG3 0x40010866u +#define CYDEV_UCFG_B0_P4_U0_DCFG4 0x40010868u +#define CYDEV_UCFG_B0_P4_U0_DCFG5 0x4001086au +#define CYDEV_UCFG_B0_P4_U0_DCFG6 0x4001086cu +#define CYDEV_UCFG_B0_P4_U0_DCFG7 0x4001086eu +#define CYDEV_UCFG_B0_P4_U1_BASE 0x40010880u +#define CYDEV_UCFG_B0_P4_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT0 0x40010880u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT1 0x40010884u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT2 0x40010888u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT3 0x4001088cu +#define CYDEV_UCFG_B0_P4_U1_PLD_IT4 0x40010890u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT5 0x40010894u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT6 0x40010898u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT7 0x4001089cu +#define CYDEV_UCFG_B0_P4_U1_PLD_IT8 0x400108a0u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT9 0x400108a4u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT10 0x400108a8u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT11 0x400108acu +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT0 0x400108b0u +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT1 0x400108b2u +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT2 0x400108b4u +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT3 0x400108b6u +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST 0x400108b8u +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB 0x400108bau +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET 0x400108bcu +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS 0x400108beu +#define CYDEV_UCFG_B0_P4_U1_CFG0 0x400108c0u +#define CYDEV_UCFG_B0_P4_U1_CFG1 0x400108c1u +#define CYDEV_UCFG_B0_P4_U1_CFG2 0x400108c2u +#define CYDEV_UCFG_B0_P4_U1_CFG3 0x400108c3u +#define CYDEV_UCFG_B0_P4_U1_CFG4 0x400108c4u +#define CYDEV_UCFG_B0_P4_U1_CFG5 0x400108c5u +#define CYDEV_UCFG_B0_P4_U1_CFG6 0x400108c6u +#define CYDEV_UCFG_B0_P4_U1_CFG7 0x400108c7u +#define CYDEV_UCFG_B0_P4_U1_CFG8 0x400108c8u +#define CYDEV_UCFG_B0_P4_U1_CFG9 0x400108c9u +#define CYDEV_UCFG_B0_P4_U1_CFG10 0x400108cau +#define CYDEV_UCFG_B0_P4_U1_CFG11 0x400108cbu +#define CYDEV_UCFG_B0_P4_U1_CFG12 0x400108ccu +#define CYDEV_UCFG_B0_P4_U1_CFG13 0x400108cdu +#define CYDEV_UCFG_B0_P4_U1_CFG14 0x400108ceu +#define CYDEV_UCFG_B0_P4_U1_CFG15 0x400108cfu +#define CYDEV_UCFG_B0_P4_U1_CFG16 0x400108d0u +#define CYDEV_UCFG_B0_P4_U1_CFG17 0x400108d1u +#define CYDEV_UCFG_B0_P4_U1_CFG18 0x400108d2u +#define CYDEV_UCFG_B0_P4_U1_CFG19 0x400108d3u +#define CYDEV_UCFG_B0_P4_U1_CFG20 0x400108d4u +#define CYDEV_UCFG_B0_P4_U1_CFG21 0x400108d5u +#define CYDEV_UCFG_B0_P4_U1_CFG22 0x400108d6u +#define CYDEV_UCFG_B0_P4_U1_CFG23 0x400108d7u +#define CYDEV_UCFG_B0_P4_U1_CFG24 0x400108d8u +#define CYDEV_UCFG_B0_P4_U1_CFG25 0x400108d9u +#define CYDEV_UCFG_B0_P4_U1_CFG26 0x400108dau +#define CYDEV_UCFG_B0_P4_U1_CFG27 0x400108dbu +#define CYDEV_UCFG_B0_P4_U1_CFG28 0x400108dcu +#define CYDEV_UCFG_B0_P4_U1_CFG29 0x400108ddu +#define CYDEV_UCFG_B0_P4_U1_CFG30 0x400108deu +#define CYDEV_UCFG_B0_P4_U1_CFG31 0x400108dfu +#define CYDEV_UCFG_B0_P4_U1_DCFG0 0x400108e0u +#define CYDEV_UCFG_B0_P4_U1_DCFG1 0x400108e2u +#define CYDEV_UCFG_B0_P4_U1_DCFG2 0x400108e4u +#define CYDEV_UCFG_B0_P4_U1_DCFG3 0x400108e6u +#define CYDEV_UCFG_B0_P4_U1_DCFG4 0x400108e8u +#define CYDEV_UCFG_B0_P4_U1_DCFG5 0x400108eau +#define CYDEV_UCFG_B0_P4_U1_DCFG6 0x400108ecu +#define CYDEV_UCFG_B0_P4_U1_DCFG7 0x400108eeu +#define CYDEV_UCFG_B0_P4_ROUTE_BASE 0x40010900u +#define CYDEV_UCFG_B0_P4_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P5_BASE 0x40010a00u +#define CYDEV_UCFG_B0_P5_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P5_U0_BASE 0x40010a00u +#define CYDEV_UCFG_B0_P5_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT0 0x40010a00u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT1 0x40010a04u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT2 0x40010a08u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT3 0x40010a0cu +#define CYDEV_UCFG_B0_P5_U0_PLD_IT4 0x40010a10u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT5 0x40010a14u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT6 0x40010a18u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT7 0x40010a1cu +#define CYDEV_UCFG_B0_P5_U0_PLD_IT8 0x40010a20u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT9 0x40010a24u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT10 0x40010a28u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT11 0x40010a2cu +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT0 0x40010a30u +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT1 0x40010a32u +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT2 0x40010a34u +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT3 0x40010a36u +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST 0x40010a38u +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB 0x40010a3au +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET 0x40010a3cu +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS 0x40010a3eu +#define CYDEV_UCFG_B0_P5_U0_CFG0 0x40010a40u +#define CYDEV_UCFG_B0_P5_U0_CFG1 0x40010a41u +#define CYDEV_UCFG_B0_P5_U0_CFG2 0x40010a42u +#define CYDEV_UCFG_B0_P5_U0_CFG3 0x40010a43u +#define CYDEV_UCFG_B0_P5_U0_CFG4 0x40010a44u +#define CYDEV_UCFG_B0_P5_U0_CFG5 0x40010a45u +#define CYDEV_UCFG_B0_P5_U0_CFG6 0x40010a46u +#define CYDEV_UCFG_B0_P5_U0_CFG7 0x40010a47u +#define CYDEV_UCFG_B0_P5_U0_CFG8 0x40010a48u +#define CYDEV_UCFG_B0_P5_U0_CFG9 0x40010a49u +#define CYDEV_UCFG_B0_P5_U0_CFG10 0x40010a4au +#define CYDEV_UCFG_B0_P5_U0_CFG11 0x40010a4bu +#define CYDEV_UCFG_B0_P5_U0_CFG12 0x40010a4cu +#define CYDEV_UCFG_B0_P5_U0_CFG13 0x40010a4du +#define CYDEV_UCFG_B0_P5_U0_CFG14 0x40010a4eu +#define CYDEV_UCFG_B0_P5_U0_CFG15 0x40010a4fu +#define CYDEV_UCFG_B0_P5_U0_CFG16 0x40010a50u +#define CYDEV_UCFG_B0_P5_U0_CFG17 0x40010a51u +#define CYDEV_UCFG_B0_P5_U0_CFG18 0x40010a52u +#define CYDEV_UCFG_B0_P5_U0_CFG19 0x40010a53u +#define CYDEV_UCFG_B0_P5_U0_CFG20 0x40010a54u +#define CYDEV_UCFG_B0_P5_U0_CFG21 0x40010a55u +#define CYDEV_UCFG_B0_P5_U0_CFG22 0x40010a56u +#define CYDEV_UCFG_B0_P5_U0_CFG23 0x40010a57u +#define CYDEV_UCFG_B0_P5_U0_CFG24 0x40010a58u +#define CYDEV_UCFG_B0_P5_U0_CFG25 0x40010a59u +#define CYDEV_UCFG_B0_P5_U0_CFG26 0x40010a5au +#define CYDEV_UCFG_B0_P5_U0_CFG27 0x40010a5bu +#define CYDEV_UCFG_B0_P5_U0_CFG28 0x40010a5cu +#define CYDEV_UCFG_B0_P5_U0_CFG29 0x40010a5du +#define CYDEV_UCFG_B0_P5_U0_CFG30 0x40010a5eu +#define CYDEV_UCFG_B0_P5_U0_CFG31 0x40010a5fu +#define CYDEV_UCFG_B0_P5_U0_DCFG0 0x40010a60u +#define CYDEV_UCFG_B0_P5_U0_DCFG1 0x40010a62u +#define CYDEV_UCFG_B0_P5_U0_DCFG2 0x40010a64u +#define CYDEV_UCFG_B0_P5_U0_DCFG3 0x40010a66u +#define CYDEV_UCFG_B0_P5_U0_DCFG4 0x40010a68u +#define CYDEV_UCFG_B0_P5_U0_DCFG5 0x40010a6au +#define CYDEV_UCFG_B0_P5_U0_DCFG6 0x40010a6cu +#define CYDEV_UCFG_B0_P5_U0_DCFG7 0x40010a6eu +#define CYDEV_UCFG_B0_P5_U1_BASE 0x40010a80u +#define CYDEV_UCFG_B0_P5_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT0 0x40010a80u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT1 0x40010a84u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT2 0x40010a88u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT3 0x40010a8cu +#define CYDEV_UCFG_B0_P5_U1_PLD_IT4 0x40010a90u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT5 0x40010a94u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT6 0x40010a98u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT7 0x40010a9cu +#define CYDEV_UCFG_B0_P5_U1_PLD_IT8 0x40010aa0u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT9 0x40010aa4u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT10 0x40010aa8u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT11 0x40010aacu +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT0 0x40010ab0u +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT1 0x40010ab2u +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT2 0x40010ab4u +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT3 0x40010ab6u +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST 0x40010ab8u +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB 0x40010abau +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET 0x40010abcu +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS 0x40010abeu +#define CYDEV_UCFG_B0_P5_U1_CFG0 0x40010ac0u +#define CYDEV_UCFG_B0_P5_U1_CFG1 0x40010ac1u +#define CYDEV_UCFG_B0_P5_U1_CFG2 0x40010ac2u +#define CYDEV_UCFG_B0_P5_U1_CFG3 0x40010ac3u +#define CYDEV_UCFG_B0_P5_U1_CFG4 0x40010ac4u +#define CYDEV_UCFG_B0_P5_U1_CFG5 0x40010ac5u +#define CYDEV_UCFG_B0_P5_U1_CFG6 0x40010ac6u +#define CYDEV_UCFG_B0_P5_U1_CFG7 0x40010ac7u +#define CYDEV_UCFG_B0_P5_U1_CFG8 0x40010ac8u +#define CYDEV_UCFG_B0_P5_U1_CFG9 0x40010ac9u +#define CYDEV_UCFG_B0_P5_U1_CFG10 0x40010acau +#define CYDEV_UCFG_B0_P5_U1_CFG11 0x40010acbu +#define CYDEV_UCFG_B0_P5_U1_CFG12 0x40010accu +#define CYDEV_UCFG_B0_P5_U1_CFG13 0x40010acdu +#define CYDEV_UCFG_B0_P5_U1_CFG14 0x40010aceu +#define CYDEV_UCFG_B0_P5_U1_CFG15 0x40010acfu +#define CYDEV_UCFG_B0_P5_U1_CFG16 0x40010ad0u +#define CYDEV_UCFG_B0_P5_U1_CFG17 0x40010ad1u +#define CYDEV_UCFG_B0_P5_U1_CFG18 0x40010ad2u +#define CYDEV_UCFG_B0_P5_U1_CFG19 0x40010ad3u +#define CYDEV_UCFG_B0_P5_U1_CFG20 0x40010ad4u +#define CYDEV_UCFG_B0_P5_U1_CFG21 0x40010ad5u +#define CYDEV_UCFG_B0_P5_U1_CFG22 0x40010ad6u +#define CYDEV_UCFG_B0_P5_U1_CFG23 0x40010ad7u +#define CYDEV_UCFG_B0_P5_U1_CFG24 0x40010ad8u +#define CYDEV_UCFG_B0_P5_U1_CFG25 0x40010ad9u +#define CYDEV_UCFG_B0_P5_U1_CFG26 0x40010adau +#define CYDEV_UCFG_B0_P5_U1_CFG27 0x40010adbu +#define CYDEV_UCFG_B0_P5_U1_CFG28 0x40010adcu +#define CYDEV_UCFG_B0_P5_U1_CFG29 0x40010addu +#define CYDEV_UCFG_B0_P5_U1_CFG30 0x40010adeu +#define CYDEV_UCFG_B0_P5_U1_CFG31 0x40010adfu +#define CYDEV_UCFG_B0_P5_U1_DCFG0 0x40010ae0u +#define CYDEV_UCFG_B0_P5_U1_DCFG1 0x40010ae2u +#define CYDEV_UCFG_B0_P5_U1_DCFG2 0x40010ae4u +#define CYDEV_UCFG_B0_P5_U1_DCFG3 0x40010ae6u +#define CYDEV_UCFG_B0_P5_U1_DCFG4 0x40010ae8u +#define CYDEV_UCFG_B0_P5_U1_DCFG5 0x40010aeau +#define CYDEV_UCFG_B0_P5_U1_DCFG6 0x40010aecu +#define CYDEV_UCFG_B0_P5_U1_DCFG7 0x40010aeeu +#define CYDEV_UCFG_B0_P5_ROUTE_BASE 0x40010b00u +#define CYDEV_UCFG_B0_P5_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P6_BASE 0x40010c00u +#define CYDEV_UCFG_B0_P6_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P6_U0_BASE 0x40010c00u +#define CYDEV_UCFG_B0_P6_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT0 0x40010c00u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT1 0x40010c04u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT2 0x40010c08u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT3 0x40010c0cu +#define CYDEV_UCFG_B0_P6_U0_PLD_IT4 0x40010c10u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT5 0x40010c14u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT6 0x40010c18u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT7 0x40010c1cu +#define CYDEV_UCFG_B0_P6_U0_PLD_IT8 0x40010c20u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT9 0x40010c24u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT10 0x40010c28u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT11 0x40010c2cu +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT0 0x40010c30u +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT1 0x40010c32u +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT2 0x40010c34u +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT3 0x40010c36u +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST 0x40010c38u +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB 0x40010c3au +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET 0x40010c3cu +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS 0x40010c3eu +#define CYDEV_UCFG_B0_P6_U0_CFG0 0x40010c40u +#define CYDEV_UCFG_B0_P6_U0_CFG1 0x40010c41u +#define CYDEV_UCFG_B0_P6_U0_CFG2 0x40010c42u +#define CYDEV_UCFG_B0_P6_U0_CFG3 0x40010c43u +#define CYDEV_UCFG_B0_P6_U0_CFG4 0x40010c44u +#define CYDEV_UCFG_B0_P6_U0_CFG5 0x40010c45u +#define CYDEV_UCFG_B0_P6_U0_CFG6 0x40010c46u +#define CYDEV_UCFG_B0_P6_U0_CFG7 0x40010c47u +#define CYDEV_UCFG_B0_P6_U0_CFG8 0x40010c48u +#define CYDEV_UCFG_B0_P6_U0_CFG9 0x40010c49u +#define CYDEV_UCFG_B0_P6_U0_CFG10 0x40010c4au +#define CYDEV_UCFG_B0_P6_U0_CFG11 0x40010c4bu +#define CYDEV_UCFG_B0_P6_U0_CFG12 0x40010c4cu +#define CYDEV_UCFG_B0_P6_U0_CFG13 0x40010c4du +#define CYDEV_UCFG_B0_P6_U0_CFG14 0x40010c4eu +#define CYDEV_UCFG_B0_P6_U0_CFG15 0x40010c4fu +#define CYDEV_UCFG_B0_P6_U0_CFG16 0x40010c50u +#define CYDEV_UCFG_B0_P6_U0_CFG17 0x40010c51u +#define CYDEV_UCFG_B0_P6_U0_CFG18 0x40010c52u +#define CYDEV_UCFG_B0_P6_U0_CFG19 0x40010c53u +#define CYDEV_UCFG_B0_P6_U0_CFG20 0x40010c54u +#define CYDEV_UCFG_B0_P6_U0_CFG21 0x40010c55u +#define CYDEV_UCFG_B0_P6_U0_CFG22 0x40010c56u +#define CYDEV_UCFG_B0_P6_U0_CFG23 0x40010c57u +#define CYDEV_UCFG_B0_P6_U0_CFG24 0x40010c58u +#define CYDEV_UCFG_B0_P6_U0_CFG25 0x40010c59u +#define CYDEV_UCFG_B0_P6_U0_CFG26 0x40010c5au +#define CYDEV_UCFG_B0_P6_U0_CFG27 0x40010c5bu +#define CYDEV_UCFG_B0_P6_U0_CFG28 0x40010c5cu +#define CYDEV_UCFG_B0_P6_U0_CFG29 0x40010c5du +#define CYDEV_UCFG_B0_P6_U0_CFG30 0x40010c5eu +#define CYDEV_UCFG_B0_P6_U0_CFG31 0x40010c5fu +#define CYDEV_UCFG_B0_P6_U0_DCFG0 0x40010c60u +#define CYDEV_UCFG_B0_P6_U0_DCFG1 0x40010c62u +#define CYDEV_UCFG_B0_P6_U0_DCFG2 0x40010c64u +#define CYDEV_UCFG_B0_P6_U0_DCFG3 0x40010c66u +#define CYDEV_UCFG_B0_P6_U0_DCFG4 0x40010c68u +#define CYDEV_UCFG_B0_P6_U0_DCFG5 0x40010c6au +#define CYDEV_UCFG_B0_P6_U0_DCFG6 0x40010c6cu +#define CYDEV_UCFG_B0_P6_U0_DCFG7 0x40010c6eu +#define CYDEV_UCFG_B0_P6_U1_BASE 0x40010c80u +#define CYDEV_UCFG_B0_P6_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT0 0x40010c80u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT1 0x40010c84u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT2 0x40010c88u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT3 0x40010c8cu +#define CYDEV_UCFG_B0_P6_U1_PLD_IT4 0x40010c90u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT5 0x40010c94u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT6 0x40010c98u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT7 0x40010c9cu +#define CYDEV_UCFG_B0_P6_U1_PLD_IT8 0x40010ca0u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT9 0x40010ca4u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT10 0x40010ca8u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT11 0x40010cacu +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT0 0x40010cb0u +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT1 0x40010cb2u +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT2 0x40010cb4u +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT3 0x40010cb6u +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST 0x40010cb8u +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB 0x40010cbau +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET 0x40010cbcu +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS 0x40010cbeu +#define CYDEV_UCFG_B0_P6_U1_CFG0 0x40010cc0u +#define CYDEV_UCFG_B0_P6_U1_CFG1 0x40010cc1u +#define CYDEV_UCFG_B0_P6_U1_CFG2 0x40010cc2u +#define CYDEV_UCFG_B0_P6_U1_CFG3 0x40010cc3u +#define CYDEV_UCFG_B0_P6_U1_CFG4 0x40010cc4u +#define CYDEV_UCFG_B0_P6_U1_CFG5 0x40010cc5u +#define CYDEV_UCFG_B0_P6_U1_CFG6 0x40010cc6u +#define CYDEV_UCFG_B0_P6_U1_CFG7 0x40010cc7u +#define CYDEV_UCFG_B0_P6_U1_CFG8 0x40010cc8u +#define CYDEV_UCFG_B0_P6_U1_CFG9 0x40010cc9u +#define CYDEV_UCFG_B0_P6_U1_CFG10 0x40010ccau +#define CYDEV_UCFG_B0_P6_U1_CFG11 0x40010ccbu +#define CYDEV_UCFG_B0_P6_U1_CFG12 0x40010cccu +#define CYDEV_UCFG_B0_P6_U1_CFG13 0x40010ccdu +#define CYDEV_UCFG_B0_P6_U1_CFG14 0x40010cceu +#define CYDEV_UCFG_B0_P6_U1_CFG15 0x40010ccfu +#define CYDEV_UCFG_B0_P6_U1_CFG16 0x40010cd0u +#define CYDEV_UCFG_B0_P6_U1_CFG17 0x40010cd1u +#define CYDEV_UCFG_B0_P6_U1_CFG18 0x40010cd2u +#define CYDEV_UCFG_B0_P6_U1_CFG19 0x40010cd3u +#define CYDEV_UCFG_B0_P6_U1_CFG20 0x40010cd4u +#define CYDEV_UCFG_B0_P6_U1_CFG21 0x40010cd5u +#define CYDEV_UCFG_B0_P6_U1_CFG22 0x40010cd6u +#define CYDEV_UCFG_B0_P6_U1_CFG23 0x40010cd7u +#define CYDEV_UCFG_B0_P6_U1_CFG24 0x40010cd8u +#define CYDEV_UCFG_B0_P6_U1_CFG25 0x40010cd9u +#define CYDEV_UCFG_B0_P6_U1_CFG26 0x40010cdau +#define CYDEV_UCFG_B0_P6_U1_CFG27 0x40010cdbu +#define CYDEV_UCFG_B0_P6_U1_CFG28 0x40010cdcu +#define CYDEV_UCFG_B0_P6_U1_CFG29 0x40010cddu +#define CYDEV_UCFG_B0_P6_U1_CFG30 0x40010cdeu +#define CYDEV_UCFG_B0_P6_U1_CFG31 0x40010cdfu +#define CYDEV_UCFG_B0_P6_U1_DCFG0 0x40010ce0u +#define CYDEV_UCFG_B0_P6_U1_DCFG1 0x40010ce2u +#define CYDEV_UCFG_B0_P6_U1_DCFG2 0x40010ce4u +#define CYDEV_UCFG_B0_P6_U1_DCFG3 0x40010ce6u +#define CYDEV_UCFG_B0_P6_U1_DCFG4 0x40010ce8u +#define CYDEV_UCFG_B0_P6_U1_DCFG5 0x40010ceau +#define CYDEV_UCFG_B0_P6_U1_DCFG6 0x40010cecu +#define CYDEV_UCFG_B0_P6_U1_DCFG7 0x40010ceeu +#define CYDEV_UCFG_B0_P6_ROUTE_BASE 0x40010d00u +#define CYDEV_UCFG_B0_P6_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P7_BASE 0x40010e00u +#define CYDEV_UCFG_B0_P7_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P7_U0_BASE 0x40010e00u +#define CYDEV_UCFG_B0_P7_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT0 0x40010e00u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT1 0x40010e04u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT2 0x40010e08u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT3 0x40010e0cu +#define CYDEV_UCFG_B0_P7_U0_PLD_IT4 0x40010e10u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT5 0x40010e14u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT6 0x40010e18u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT7 0x40010e1cu +#define CYDEV_UCFG_B0_P7_U0_PLD_IT8 0x40010e20u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT9 0x40010e24u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT10 0x40010e28u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT11 0x40010e2cu +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT0 0x40010e30u +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT1 0x40010e32u +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT2 0x40010e34u +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT3 0x40010e36u +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST 0x40010e38u +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB 0x40010e3au +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET 0x40010e3cu +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS 0x40010e3eu +#define CYDEV_UCFG_B0_P7_U0_CFG0 0x40010e40u +#define CYDEV_UCFG_B0_P7_U0_CFG1 0x40010e41u +#define CYDEV_UCFG_B0_P7_U0_CFG2 0x40010e42u +#define CYDEV_UCFG_B0_P7_U0_CFG3 0x40010e43u +#define CYDEV_UCFG_B0_P7_U0_CFG4 0x40010e44u +#define CYDEV_UCFG_B0_P7_U0_CFG5 0x40010e45u +#define CYDEV_UCFG_B0_P7_U0_CFG6 0x40010e46u +#define CYDEV_UCFG_B0_P7_U0_CFG7 0x40010e47u +#define CYDEV_UCFG_B0_P7_U0_CFG8 0x40010e48u +#define CYDEV_UCFG_B0_P7_U0_CFG9 0x40010e49u +#define CYDEV_UCFG_B0_P7_U0_CFG10 0x40010e4au +#define CYDEV_UCFG_B0_P7_U0_CFG11 0x40010e4bu +#define CYDEV_UCFG_B0_P7_U0_CFG12 0x40010e4cu +#define CYDEV_UCFG_B0_P7_U0_CFG13 0x40010e4du +#define CYDEV_UCFG_B0_P7_U0_CFG14 0x40010e4eu +#define CYDEV_UCFG_B0_P7_U0_CFG15 0x40010e4fu +#define CYDEV_UCFG_B0_P7_U0_CFG16 0x40010e50u +#define CYDEV_UCFG_B0_P7_U0_CFG17 0x40010e51u +#define CYDEV_UCFG_B0_P7_U0_CFG18 0x40010e52u +#define CYDEV_UCFG_B0_P7_U0_CFG19 0x40010e53u +#define CYDEV_UCFG_B0_P7_U0_CFG20 0x40010e54u +#define CYDEV_UCFG_B0_P7_U0_CFG21 0x40010e55u +#define CYDEV_UCFG_B0_P7_U0_CFG22 0x40010e56u +#define CYDEV_UCFG_B0_P7_U0_CFG23 0x40010e57u +#define CYDEV_UCFG_B0_P7_U0_CFG24 0x40010e58u +#define CYDEV_UCFG_B0_P7_U0_CFG25 0x40010e59u +#define CYDEV_UCFG_B0_P7_U0_CFG26 0x40010e5au +#define CYDEV_UCFG_B0_P7_U0_CFG27 0x40010e5bu +#define CYDEV_UCFG_B0_P7_U0_CFG28 0x40010e5cu +#define CYDEV_UCFG_B0_P7_U0_CFG29 0x40010e5du +#define CYDEV_UCFG_B0_P7_U0_CFG30 0x40010e5eu +#define CYDEV_UCFG_B0_P7_U0_CFG31 0x40010e5fu +#define CYDEV_UCFG_B0_P7_U0_DCFG0 0x40010e60u +#define CYDEV_UCFG_B0_P7_U0_DCFG1 0x40010e62u +#define CYDEV_UCFG_B0_P7_U0_DCFG2 0x40010e64u +#define CYDEV_UCFG_B0_P7_U0_DCFG3 0x40010e66u +#define CYDEV_UCFG_B0_P7_U0_DCFG4 0x40010e68u +#define CYDEV_UCFG_B0_P7_U0_DCFG5 0x40010e6au +#define CYDEV_UCFG_B0_P7_U0_DCFG6 0x40010e6cu +#define CYDEV_UCFG_B0_P7_U0_DCFG7 0x40010e6eu +#define CYDEV_UCFG_B0_P7_U1_BASE 0x40010e80u +#define CYDEV_UCFG_B0_P7_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT0 0x40010e80u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT1 0x40010e84u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT2 0x40010e88u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT3 0x40010e8cu +#define CYDEV_UCFG_B0_P7_U1_PLD_IT4 0x40010e90u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT5 0x40010e94u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT6 0x40010e98u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT7 0x40010e9cu +#define CYDEV_UCFG_B0_P7_U1_PLD_IT8 0x40010ea0u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT9 0x40010ea4u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT10 0x40010ea8u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT11 0x40010eacu +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT0 0x40010eb0u +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT1 0x40010eb2u +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT2 0x40010eb4u +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT3 0x40010eb6u +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST 0x40010eb8u +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB 0x40010ebau +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET 0x40010ebcu +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS 0x40010ebeu +#define CYDEV_UCFG_B0_P7_U1_CFG0 0x40010ec0u +#define CYDEV_UCFG_B0_P7_U1_CFG1 0x40010ec1u +#define CYDEV_UCFG_B0_P7_U1_CFG2 0x40010ec2u +#define CYDEV_UCFG_B0_P7_U1_CFG3 0x40010ec3u +#define CYDEV_UCFG_B0_P7_U1_CFG4 0x40010ec4u +#define CYDEV_UCFG_B0_P7_U1_CFG5 0x40010ec5u +#define CYDEV_UCFG_B0_P7_U1_CFG6 0x40010ec6u +#define CYDEV_UCFG_B0_P7_U1_CFG7 0x40010ec7u +#define CYDEV_UCFG_B0_P7_U1_CFG8 0x40010ec8u +#define CYDEV_UCFG_B0_P7_U1_CFG9 0x40010ec9u +#define CYDEV_UCFG_B0_P7_U1_CFG10 0x40010ecau +#define CYDEV_UCFG_B0_P7_U1_CFG11 0x40010ecbu +#define CYDEV_UCFG_B0_P7_U1_CFG12 0x40010eccu +#define CYDEV_UCFG_B0_P7_U1_CFG13 0x40010ecdu +#define CYDEV_UCFG_B0_P7_U1_CFG14 0x40010eceu +#define CYDEV_UCFG_B0_P7_U1_CFG15 0x40010ecfu +#define CYDEV_UCFG_B0_P7_U1_CFG16 0x40010ed0u +#define CYDEV_UCFG_B0_P7_U1_CFG17 0x40010ed1u +#define CYDEV_UCFG_B0_P7_U1_CFG18 0x40010ed2u +#define CYDEV_UCFG_B0_P7_U1_CFG19 0x40010ed3u +#define CYDEV_UCFG_B0_P7_U1_CFG20 0x40010ed4u +#define CYDEV_UCFG_B0_P7_U1_CFG21 0x40010ed5u +#define CYDEV_UCFG_B0_P7_U1_CFG22 0x40010ed6u +#define CYDEV_UCFG_B0_P7_U1_CFG23 0x40010ed7u +#define CYDEV_UCFG_B0_P7_U1_CFG24 0x40010ed8u +#define CYDEV_UCFG_B0_P7_U1_CFG25 0x40010ed9u +#define CYDEV_UCFG_B0_P7_U1_CFG26 0x40010edau +#define CYDEV_UCFG_B0_P7_U1_CFG27 0x40010edbu +#define CYDEV_UCFG_B0_P7_U1_CFG28 0x40010edcu +#define CYDEV_UCFG_B0_P7_U1_CFG29 0x40010eddu +#define CYDEV_UCFG_B0_P7_U1_CFG30 0x40010edeu +#define CYDEV_UCFG_B0_P7_U1_CFG31 0x40010edfu +#define CYDEV_UCFG_B0_P7_U1_DCFG0 0x40010ee0u +#define CYDEV_UCFG_B0_P7_U1_DCFG1 0x40010ee2u +#define CYDEV_UCFG_B0_P7_U1_DCFG2 0x40010ee4u +#define CYDEV_UCFG_B0_P7_U1_DCFG3 0x40010ee6u +#define CYDEV_UCFG_B0_P7_U1_DCFG4 0x40010ee8u +#define CYDEV_UCFG_B0_P7_U1_DCFG5 0x40010eeau +#define CYDEV_UCFG_B0_P7_U1_DCFG6 0x40010eecu +#define CYDEV_UCFG_B0_P7_U1_DCFG7 0x40010eeeu +#define CYDEV_UCFG_B0_P7_ROUTE_BASE 0x40010f00u +#define CYDEV_UCFG_B0_P7_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_BASE 0x40011000u +#define CYDEV_UCFG_B1_SIZE 0x00000fefu +#define CYDEV_UCFG_B1_P2_BASE 0x40011400u +#define CYDEV_UCFG_B1_P2_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P2_U0_BASE 0x40011400u +#define CYDEV_UCFG_B1_P2_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT0 0x40011400u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT1 0x40011404u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT2 0x40011408u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT3 0x4001140cu +#define CYDEV_UCFG_B1_P2_U0_PLD_IT4 0x40011410u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT5 0x40011414u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT6 0x40011418u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT7 0x4001141cu +#define CYDEV_UCFG_B1_P2_U0_PLD_IT8 0x40011420u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT9 0x40011424u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT10 0x40011428u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT11 0x4001142cu +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT0 0x40011430u +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT1 0x40011432u +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT2 0x40011434u +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT3 0x40011436u +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST 0x40011438u +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB 0x4001143au +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET 0x4001143cu +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS 0x4001143eu +#define CYDEV_UCFG_B1_P2_U0_CFG0 0x40011440u +#define CYDEV_UCFG_B1_P2_U0_CFG1 0x40011441u +#define CYDEV_UCFG_B1_P2_U0_CFG2 0x40011442u +#define CYDEV_UCFG_B1_P2_U0_CFG3 0x40011443u +#define CYDEV_UCFG_B1_P2_U0_CFG4 0x40011444u +#define CYDEV_UCFG_B1_P2_U0_CFG5 0x40011445u +#define CYDEV_UCFG_B1_P2_U0_CFG6 0x40011446u +#define CYDEV_UCFG_B1_P2_U0_CFG7 0x40011447u +#define CYDEV_UCFG_B1_P2_U0_CFG8 0x40011448u +#define CYDEV_UCFG_B1_P2_U0_CFG9 0x40011449u +#define CYDEV_UCFG_B1_P2_U0_CFG10 0x4001144au +#define CYDEV_UCFG_B1_P2_U0_CFG11 0x4001144bu +#define CYDEV_UCFG_B1_P2_U0_CFG12 0x4001144cu +#define CYDEV_UCFG_B1_P2_U0_CFG13 0x4001144du +#define CYDEV_UCFG_B1_P2_U0_CFG14 0x4001144eu +#define CYDEV_UCFG_B1_P2_U0_CFG15 0x4001144fu +#define CYDEV_UCFG_B1_P2_U0_CFG16 0x40011450u +#define CYDEV_UCFG_B1_P2_U0_CFG17 0x40011451u +#define CYDEV_UCFG_B1_P2_U0_CFG18 0x40011452u +#define CYDEV_UCFG_B1_P2_U0_CFG19 0x40011453u +#define CYDEV_UCFG_B1_P2_U0_CFG20 0x40011454u +#define CYDEV_UCFG_B1_P2_U0_CFG21 0x40011455u +#define CYDEV_UCFG_B1_P2_U0_CFG22 0x40011456u +#define CYDEV_UCFG_B1_P2_U0_CFG23 0x40011457u +#define CYDEV_UCFG_B1_P2_U0_CFG24 0x40011458u +#define CYDEV_UCFG_B1_P2_U0_CFG25 0x40011459u +#define CYDEV_UCFG_B1_P2_U0_CFG26 0x4001145au +#define CYDEV_UCFG_B1_P2_U0_CFG27 0x4001145bu +#define CYDEV_UCFG_B1_P2_U0_CFG28 0x4001145cu +#define CYDEV_UCFG_B1_P2_U0_CFG29 0x4001145du +#define CYDEV_UCFG_B1_P2_U0_CFG30 0x4001145eu +#define CYDEV_UCFG_B1_P2_U0_CFG31 0x4001145fu +#define CYDEV_UCFG_B1_P2_U0_DCFG0 0x40011460u +#define CYDEV_UCFG_B1_P2_U0_DCFG1 0x40011462u +#define CYDEV_UCFG_B1_P2_U0_DCFG2 0x40011464u +#define CYDEV_UCFG_B1_P2_U0_DCFG3 0x40011466u +#define CYDEV_UCFG_B1_P2_U0_DCFG4 0x40011468u +#define CYDEV_UCFG_B1_P2_U0_DCFG5 0x4001146au +#define CYDEV_UCFG_B1_P2_U0_DCFG6 0x4001146cu +#define CYDEV_UCFG_B1_P2_U0_DCFG7 0x4001146eu +#define CYDEV_UCFG_B1_P2_U1_BASE 0x40011480u +#define CYDEV_UCFG_B1_P2_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT0 0x40011480u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT1 0x40011484u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT2 0x40011488u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT3 0x4001148cu +#define CYDEV_UCFG_B1_P2_U1_PLD_IT4 0x40011490u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT5 0x40011494u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT6 0x40011498u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT7 0x4001149cu +#define CYDEV_UCFG_B1_P2_U1_PLD_IT8 0x400114a0u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT9 0x400114a4u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT10 0x400114a8u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT11 0x400114acu +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT0 0x400114b0u +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT1 0x400114b2u +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT2 0x400114b4u +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT3 0x400114b6u +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST 0x400114b8u +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB 0x400114bau +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET 0x400114bcu +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS 0x400114beu +#define CYDEV_UCFG_B1_P2_U1_CFG0 0x400114c0u +#define CYDEV_UCFG_B1_P2_U1_CFG1 0x400114c1u +#define CYDEV_UCFG_B1_P2_U1_CFG2 0x400114c2u +#define CYDEV_UCFG_B1_P2_U1_CFG3 0x400114c3u +#define CYDEV_UCFG_B1_P2_U1_CFG4 0x400114c4u +#define CYDEV_UCFG_B1_P2_U1_CFG5 0x400114c5u +#define CYDEV_UCFG_B1_P2_U1_CFG6 0x400114c6u +#define CYDEV_UCFG_B1_P2_U1_CFG7 0x400114c7u +#define CYDEV_UCFG_B1_P2_U1_CFG8 0x400114c8u +#define CYDEV_UCFG_B1_P2_U1_CFG9 0x400114c9u +#define CYDEV_UCFG_B1_P2_U1_CFG10 0x400114cau +#define CYDEV_UCFG_B1_P2_U1_CFG11 0x400114cbu +#define CYDEV_UCFG_B1_P2_U1_CFG12 0x400114ccu +#define CYDEV_UCFG_B1_P2_U1_CFG13 0x400114cdu +#define CYDEV_UCFG_B1_P2_U1_CFG14 0x400114ceu +#define CYDEV_UCFG_B1_P2_U1_CFG15 0x400114cfu +#define CYDEV_UCFG_B1_P2_U1_CFG16 0x400114d0u +#define CYDEV_UCFG_B1_P2_U1_CFG17 0x400114d1u +#define CYDEV_UCFG_B1_P2_U1_CFG18 0x400114d2u +#define CYDEV_UCFG_B1_P2_U1_CFG19 0x400114d3u +#define CYDEV_UCFG_B1_P2_U1_CFG20 0x400114d4u +#define CYDEV_UCFG_B1_P2_U1_CFG21 0x400114d5u +#define CYDEV_UCFG_B1_P2_U1_CFG22 0x400114d6u +#define CYDEV_UCFG_B1_P2_U1_CFG23 0x400114d7u +#define CYDEV_UCFG_B1_P2_U1_CFG24 0x400114d8u +#define CYDEV_UCFG_B1_P2_U1_CFG25 0x400114d9u +#define CYDEV_UCFG_B1_P2_U1_CFG26 0x400114dau +#define CYDEV_UCFG_B1_P2_U1_CFG27 0x400114dbu +#define CYDEV_UCFG_B1_P2_U1_CFG28 0x400114dcu +#define CYDEV_UCFG_B1_P2_U1_CFG29 0x400114ddu +#define CYDEV_UCFG_B1_P2_U1_CFG30 0x400114deu +#define CYDEV_UCFG_B1_P2_U1_CFG31 0x400114dfu +#define CYDEV_UCFG_B1_P2_U1_DCFG0 0x400114e0u +#define CYDEV_UCFG_B1_P2_U1_DCFG1 0x400114e2u +#define CYDEV_UCFG_B1_P2_U1_DCFG2 0x400114e4u +#define CYDEV_UCFG_B1_P2_U1_DCFG3 0x400114e6u +#define CYDEV_UCFG_B1_P2_U1_DCFG4 0x400114e8u +#define CYDEV_UCFG_B1_P2_U1_DCFG5 0x400114eau +#define CYDEV_UCFG_B1_P2_U1_DCFG6 0x400114ecu +#define CYDEV_UCFG_B1_P2_U1_DCFG7 0x400114eeu +#define CYDEV_UCFG_B1_P2_ROUTE_BASE 0x40011500u +#define CYDEV_UCFG_B1_P2_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P3_BASE 0x40011600u +#define CYDEV_UCFG_B1_P3_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P3_U0_BASE 0x40011600u +#define CYDEV_UCFG_B1_P3_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT0 0x40011600u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT1 0x40011604u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT2 0x40011608u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT3 0x4001160cu +#define CYDEV_UCFG_B1_P3_U0_PLD_IT4 0x40011610u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT5 0x40011614u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT6 0x40011618u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT7 0x4001161cu +#define CYDEV_UCFG_B1_P3_U0_PLD_IT8 0x40011620u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT9 0x40011624u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT10 0x40011628u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT11 0x4001162cu +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT0 0x40011630u +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT1 0x40011632u +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT2 0x40011634u +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT3 0x40011636u +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST 0x40011638u +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB 0x4001163au +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET 0x4001163cu +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS 0x4001163eu +#define CYDEV_UCFG_B1_P3_U0_CFG0 0x40011640u +#define CYDEV_UCFG_B1_P3_U0_CFG1 0x40011641u +#define CYDEV_UCFG_B1_P3_U0_CFG2 0x40011642u +#define CYDEV_UCFG_B1_P3_U0_CFG3 0x40011643u +#define CYDEV_UCFG_B1_P3_U0_CFG4 0x40011644u +#define CYDEV_UCFG_B1_P3_U0_CFG5 0x40011645u +#define CYDEV_UCFG_B1_P3_U0_CFG6 0x40011646u +#define CYDEV_UCFG_B1_P3_U0_CFG7 0x40011647u +#define CYDEV_UCFG_B1_P3_U0_CFG8 0x40011648u +#define CYDEV_UCFG_B1_P3_U0_CFG9 0x40011649u +#define CYDEV_UCFG_B1_P3_U0_CFG10 0x4001164au +#define CYDEV_UCFG_B1_P3_U0_CFG11 0x4001164bu +#define CYDEV_UCFG_B1_P3_U0_CFG12 0x4001164cu +#define CYDEV_UCFG_B1_P3_U0_CFG13 0x4001164du +#define CYDEV_UCFG_B1_P3_U0_CFG14 0x4001164eu +#define CYDEV_UCFG_B1_P3_U0_CFG15 0x4001164fu +#define CYDEV_UCFG_B1_P3_U0_CFG16 0x40011650u +#define CYDEV_UCFG_B1_P3_U0_CFG17 0x40011651u +#define CYDEV_UCFG_B1_P3_U0_CFG18 0x40011652u +#define CYDEV_UCFG_B1_P3_U0_CFG19 0x40011653u +#define CYDEV_UCFG_B1_P3_U0_CFG20 0x40011654u +#define CYDEV_UCFG_B1_P3_U0_CFG21 0x40011655u +#define CYDEV_UCFG_B1_P3_U0_CFG22 0x40011656u +#define CYDEV_UCFG_B1_P3_U0_CFG23 0x40011657u +#define CYDEV_UCFG_B1_P3_U0_CFG24 0x40011658u +#define CYDEV_UCFG_B1_P3_U0_CFG25 0x40011659u +#define CYDEV_UCFG_B1_P3_U0_CFG26 0x4001165au +#define CYDEV_UCFG_B1_P3_U0_CFG27 0x4001165bu +#define CYDEV_UCFG_B1_P3_U0_CFG28 0x4001165cu +#define CYDEV_UCFG_B1_P3_U0_CFG29 0x4001165du +#define CYDEV_UCFG_B1_P3_U0_CFG30 0x4001165eu +#define CYDEV_UCFG_B1_P3_U0_CFG31 0x4001165fu +#define CYDEV_UCFG_B1_P3_U0_DCFG0 0x40011660u +#define CYDEV_UCFG_B1_P3_U0_DCFG1 0x40011662u +#define CYDEV_UCFG_B1_P3_U0_DCFG2 0x40011664u +#define CYDEV_UCFG_B1_P3_U0_DCFG3 0x40011666u +#define CYDEV_UCFG_B1_P3_U0_DCFG4 0x40011668u +#define CYDEV_UCFG_B1_P3_U0_DCFG5 0x4001166au +#define CYDEV_UCFG_B1_P3_U0_DCFG6 0x4001166cu +#define CYDEV_UCFG_B1_P3_U0_DCFG7 0x4001166eu +#define CYDEV_UCFG_B1_P3_U1_BASE 0x40011680u +#define CYDEV_UCFG_B1_P3_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT0 0x40011680u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT1 0x40011684u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT2 0x40011688u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT3 0x4001168cu +#define CYDEV_UCFG_B1_P3_U1_PLD_IT4 0x40011690u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT5 0x40011694u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT6 0x40011698u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT7 0x4001169cu +#define CYDEV_UCFG_B1_P3_U1_PLD_IT8 0x400116a0u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT9 0x400116a4u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT10 0x400116a8u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT11 0x400116acu +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT0 0x400116b0u +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT1 0x400116b2u +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT2 0x400116b4u +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT3 0x400116b6u +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST 0x400116b8u +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB 0x400116bau +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET 0x400116bcu +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS 0x400116beu +#define CYDEV_UCFG_B1_P3_U1_CFG0 0x400116c0u +#define CYDEV_UCFG_B1_P3_U1_CFG1 0x400116c1u +#define CYDEV_UCFG_B1_P3_U1_CFG2 0x400116c2u +#define CYDEV_UCFG_B1_P3_U1_CFG3 0x400116c3u +#define CYDEV_UCFG_B1_P3_U1_CFG4 0x400116c4u +#define CYDEV_UCFG_B1_P3_U1_CFG5 0x400116c5u +#define CYDEV_UCFG_B1_P3_U1_CFG6 0x400116c6u +#define CYDEV_UCFG_B1_P3_U1_CFG7 0x400116c7u +#define CYDEV_UCFG_B1_P3_U1_CFG8 0x400116c8u +#define CYDEV_UCFG_B1_P3_U1_CFG9 0x400116c9u +#define CYDEV_UCFG_B1_P3_U1_CFG10 0x400116cau +#define CYDEV_UCFG_B1_P3_U1_CFG11 0x400116cbu +#define CYDEV_UCFG_B1_P3_U1_CFG12 0x400116ccu +#define CYDEV_UCFG_B1_P3_U1_CFG13 0x400116cdu +#define CYDEV_UCFG_B1_P3_U1_CFG14 0x400116ceu +#define CYDEV_UCFG_B1_P3_U1_CFG15 0x400116cfu +#define CYDEV_UCFG_B1_P3_U1_CFG16 0x400116d0u +#define CYDEV_UCFG_B1_P3_U1_CFG17 0x400116d1u +#define CYDEV_UCFG_B1_P3_U1_CFG18 0x400116d2u +#define CYDEV_UCFG_B1_P3_U1_CFG19 0x400116d3u +#define CYDEV_UCFG_B1_P3_U1_CFG20 0x400116d4u +#define CYDEV_UCFG_B1_P3_U1_CFG21 0x400116d5u +#define CYDEV_UCFG_B1_P3_U1_CFG22 0x400116d6u +#define CYDEV_UCFG_B1_P3_U1_CFG23 0x400116d7u +#define CYDEV_UCFG_B1_P3_U1_CFG24 0x400116d8u +#define CYDEV_UCFG_B1_P3_U1_CFG25 0x400116d9u +#define CYDEV_UCFG_B1_P3_U1_CFG26 0x400116dau +#define CYDEV_UCFG_B1_P3_U1_CFG27 0x400116dbu +#define CYDEV_UCFG_B1_P3_U1_CFG28 0x400116dcu +#define CYDEV_UCFG_B1_P3_U1_CFG29 0x400116ddu +#define CYDEV_UCFG_B1_P3_U1_CFG30 0x400116deu +#define CYDEV_UCFG_B1_P3_U1_CFG31 0x400116dfu +#define CYDEV_UCFG_B1_P3_U1_DCFG0 0x400116e0u +#define CYDEV_UCFG_B1_P3_U1_DCFG1 0x400116e2u +#define CYDEV_UCFG_B1_P3_U1_DCFG2 0x400116e4u +#define CYDEV_UCFG_B1_P3_U1_DCFG3 0x400116e6u +#define CYDEV_UCFG_B1_P3_U1_DCFG4 0x400116e8u +#define CYDEV_UCFG_B1_P3_U1_DCFG5 0x400116eau +#define CYDEV_UCFG_B1_P3_U1_DCFG6 0x400116ecu +#define CYDEV_UCFG_B1_P3_U1_DCFG7 0x400116eeu +#define CYDEV_UCFG_B1_P3_ROUTE_BASE 0x40011700u +#define CYDEV_UCFG_B1_P3_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P4_BASE 0x40011800u +#define CYDEV_UCFG_B1_P4_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P4_U0_BASE 0x40011800u +#define CYDEV_UCFG_B1_P4_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT0 0x40011800u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT1 0x40011804u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT2 0x40011808u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT3 0x4001180cu +#define CYDEV_UCFG_B1_P4_U0_PLD_IT4 0x40011810u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT5 0x40011814u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT6 0x40011818u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT7 0x4001181cu +#define CYDEV_UCFG_B1_P4_U0_PLD_IT8 0x40011820u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT9 0x40011824u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT10 0x40011828u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT11 0x4001182cu +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT0 0x40011830u +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT1 0x40011832u +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT2 0x40011834u +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT3 0x40011836u +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST 0x40011838u +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB 0x4001183au +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET 0x4001183cu +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS 0x4001183eu +#define CYDEV_UCFG_B1_P4_U0_CFG0 0x40011840u +#define CYDEV_UCFG_B1_P4_U0_CFG1 0x40011841u +#define CYDEV_UCFG_B1_P4_U0_CFG2 0x40011842u +#define CYDEV_UCFG_B1_P4_U0_CFG3 0x40011843u +#define CYDEV_UCFG_B1_P4_U0_CFG4 0x40011844u +#define CYDEV_UCFG_B1_P4_U0_CFG5 0x40011845u +#define CYDEV_UCFG_B1_P4_U0_CFG6 0x40011846u +#define CYDEV_UCFG_B1_P4_U0_CFG7 0x40011847u +#define CYDEV_UCFG_B1_P4_U0_CFG8 0x40011848u +#define CYDEV_UCFG_B1_P4_U0_CFG9 0x40011849u +#define CYDEV_UCFG_B1_P4_U0_CFG10 0x4001184au +#define CYDEV_UCFG_B1_P4_U0_CFG11 0x4001184bu +#define CYDEV_UCFG_B1_P4_U0_CFG12 0x4001184cu +#define CYDEV_UCFG_B1_P4_U0_CFG13 0x4001184du +#define CYDEV_UCFG_B1_P4_U0_CFG14 0x4001184eu +#define CYDEV_UCFG_B1_P4_U0_CFG15 0x4001184fu +#define CYDEV_UCFG_B1_P4_U0_CFG16 0x40011850u +#define CYDEV_UCFG_B1_P4_U0_CFG17 0x40011851u +#define CYDEV_UCFG_B1_P4_U0_CFG18 0x40011852u +#define CYDEV_UCFG_B1_P4_U0_CFG19 0x40011853u +#define CYDEV_UCFG_B1_P4_U0_CFG20 0x40011854u +#define CYDEV_UCFG_B1_P4_U0_CFG21 0x40011855u +#define CYDEV_UCFG_B1_P4_U0_CFG22 0x40011856u +#define CYDEV_UCFG_B1_P4_U0_CFG23 0x40011857u +#define CYDEV_UCFG_B1_P4_U0_CFG24 0x40011858u +#define CYDEV_UCFG_B1_P4_U0_CFG25 0x40011859u +#define CYDEV_UCFG_B1_P4_U0_CFG26 0x4001185au +#define CYDEV_UCFG_B1_P4_U0_CFG27 0x4001185bu +#define CYDEV_UCFG_B1_P4_U0_CFG28 0x4001185cu +#define CYDEV_UCFG_B1_P4_U0_CFG29 0x4001185du +#define CYDEV_UCFG_B1_P4_U0_CFG30 0x4001185eu +#define CYDEV_UCFG_B1_P4_U0_CFG31 0x4001185fu +#define CYDEV_UCFG_B1_P4_U0_DCFG0 0x40011860u +#define CYDEV_UCFG_B1_P4_U0_DCFG1 0x40011862u +#define CYDEV_UCFG_B1_P4_U0_DCFG2 0x40011864u +#define CYDEV_UCFG_B1_P4_U0_DCFG3 0x40011866u +#define CYDEV_UCFG_B1_P4_U0_DCFG4 0x40011868u +#define CYDEV_UCFG_B1_P4_U0_DCFG5 0x4001186au +#define CYDEV_UCFG_B1_P4_U0_DCFG6 0x4001186cu +#define CYDEV_UCFG_B1_P4_U0_DCFG7 0x4001186eu +#define CYDEV_UCFG_B1_P4_U1_BASE 0x40011880u +#define CYDEV_UCFG_B1_P4_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT0 0x40011880u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT1 0x40011884u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT2 0x40011888u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT3 0x4001188cu +#define CYDEV_UCFG_B1_P4_U1_PLD_IT4 0x40011890u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT5 0x40011894u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT6 0x40011898u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT7 0x4001189cu +#define CYDEV_UCFG_B1_P4_U1_PLD_IT8 0x400118a0u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT9 0x400118a4u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT10 0x400118a8u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT11 0x400118acu +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT0 0x400118b0u +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT1 0x400118b2u +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT2 0x400118b4u +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT3 0x400118b6u +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST 0x400118b8u +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB 0x400118bau +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET 0x400118bcu +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS 0x400118beu +#define CYDEV_UCFG_B1_P4_U1_CFG0 0x400118c0u +#define CYDEV_UCFG_B1_P4_U1_CFG1 0x400118c1u +#define CYDEV_UCFG_B1_P4_U1_CFG2 0x400118c2u +#define CYDEV_UCFG_B1_P4_U1_CFG3 0x400118c3u +#define CYDEV_UCFG_B1_P4_U1_CFG4 0x400118c4u +#define CYDEV_UCFG_B1_P4_U1_CFG5 0x400118c5u +#define CYDEV_UCFG_B1_P4_U1_CFG6 0x400118c6u +#define CYDEV_UCFG_B1_P4_U1_CFG7 0x400118c7u +#define CYDEV_UCFG_B1_P4_U1_CFG8 0x400118c8u +#define CYDEV_UCFG_B1_P4_U1_CFG9 0x400118c9u +#define CYDEV_UCFG_B1_P4_U1_CFG10 0x400118cau +#define CYDEV_UCFG_B1_P4_U1_CFG11 0x400118cbu +#define CYDEV_UCFG_B1_P4_U1_CFG12 0x400118ccu +#define CYDEV_UCFG_B1_P4_U1_CFG13 0x400118cdu +#define CYDEV_UCFG_B1_P4_U1_CFG14 0x400118ceu +#define CYDEV_UCFG_B1_P4_U1_CFG15 0x400118cfu +#define CYDEV_UCFG_B1_P4_U1_CFG16 0x400118d0u +#define CYDEV_UCFG_B1_P4_U1_CFG17 0x400118d1u +#define CYDEV_UCFG_B1_P4_U1_CFG18 0x400118d2u +#define CYDEV_UCFG_B1_P4_U1_CFG19 0x400118d3u +#define CYDEV_UCFG_B1_P4_U1_CFG20 0x400118d4u +#define CYDEV_UCFG_B1_P4_U1_CFG21 0x400118d5u +#define CYDEV_UCFG_B1_P4_U1_CFG22 0x400118d6u +#define CYDEV_UCFG_B1_P4_U1_CFG23 0x400118d7u +#define CYDEV_UCFG_B1_P4_U1_CFG24 0x400118d8u +#define CYDEV_UCFG_B1_P4_U1_CFG25 0x400118d9u +#define CYDEV_UCFG_B1_P4_U1_CFG26 0x400118dau +#define CYDEV_UCFG_B1_P4_U1_CFG27 0x400118dbu +#define CYDEV_UCFG_B1_P4_U1_CFG28 0x400118dcu +#define CYDEV_UCFG_B1_P4_U1_CFG29 0x400118ddu +#define CYDEV_UCFG_B1_P4_U1_CFG30 0x400118deu +#define CYDEV_UCFG_B1_P4_U1_CFG31 0x400118dfu +#define CYDEV_UCFG_B1_P4_U1_DCFG0 0x400118e0u +#define CYDEV_UCFG_B1_P4_U1_DCFG1 0x400118e2u +#define CYDEV_UCFG_B1_P4_U1_DCFG2 0x400118e4u +#define CYDEV_UCFG_B1_P4_U1_DCFG3 0x400118e6u +#define CYDEV_UCFG_B1_P4_U1_DCFG4 0x400118e8u +#define CYDEV_UCFG_B1_P4_U1_DCFG5 0x400118eau +#define CYDEV_UCFG_B1_P4_U1_DCFG6 0x400118ecu +#define CYDEV_UCFG_B1_P4_U1_DCFG7 0x400118eeu +#define CYDEV_UCFG_B1_P4_ROUTE_BASE 0x40011900u +#define CYDEV_UCFG_B1_P4_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P5_BASE 0x40011a00u +#define CYDEV_UCFG_B1_P5_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P5_U0_BASE 0x40011a00u +#define CYDEV_UCFG_B1_P5_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT0 0x40011a00u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT1 0x40011a04u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT2 0x40011a08u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT3 0x40011a0cu +#define CYDEV_UCFG_B1_P5_U0_PLD_IT4 0x40011a10u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT5 0x40011a14u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT6 0x40011a18u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT7 0x40011a1cu +#define CYDEV_UCFG_B1_P5_U0_PLD_IT8 0x40011a20u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT9 0x40011a24u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT10 0x40011a28u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT11 0x40011a2cu +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT0 0x40011a30u +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT1 0x40011a32u +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT2 0x40011a34u +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT3 0x40011a36u +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST 0x40011a38u +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB 0x40011a3au +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET 0x40011a3cu +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS 0x40011a3eu +#define CYDEV_UCFG_B1_P5_U0_CFG0 0x40011a40u +#define CYDEV_UCFG_B1_P5_U0_CFG1 0x40011a41u +#define CYDEV_UCFG_B1_P5_U0_CFG2 0x40011a42u +#define CYDEV_UCFG_B1_P5_U0_CFG3 0x40011a43u +#define CYDEV_UCFG_B1_P5_U0_CFG4 0x40011a44u +#define CYDEV_UCFG_B1_P5_U0_CFG5 0x40011a45u +#define CYDEV_UCFG_B1_P5_U0_CFG6 0x40011a46u +#define CYDEV_UCFG_B1_P5_U0_CFG7 0x40011a47u +#define CYDEV_UCFG_B1_P5_U0_CFG8 0x40011a48u +#define CYDEV_UCFG_B1_P5_U0_CFG9 0x40011a49u +#define CYDEV_UCFG_B1_P5_U0_CFG10 0x40011a4au +#define CYDEV_UCFG_B1_P5_U0_CFG11 0x40011a4bu +#define CYDEV_UCFG_B1_P5_U0_CFG12 0x40011a4cu +#define CYDEV_UCFG_B1_P5_U0_CFG13 0x40011a4du +#define CYDEV_UCFG_B1_P5_U0_CFG14 0x40011a4eu +#define CYDEV_UCFG_B1_P5_U0_CFG15 0x40011a4fu +#define CYDEV_UCFG_B1_P5_U0_CFG16 0x40011a50u +#define CYDEV_UCFG_B1_P5_U0_CFG17 0x40011a51u +#define CYDEV_UCFG_B1_P5_U0_CFG18 0x40011a52u +#define CYDEV_UCFG_B1_P5_U0_CFG19 0x40011a53u +#define CYDEV_UCFG_B1_P5_U0_CFG20 0x40011a54u +#define CYDEV_UCFG_B1_P5_U0_CFG21 0x40011a55u +#define CYDEV_UCFG_B1_P5_U0_CFG22 0x40011a56u +#define CYDEV_UCFG_B1_P5_U0_CFG23 0x40011a57u +#define CYDEV_UCFG_B1_P5_U0_CFG24 0x40011a58u +#define CYDEV_UCFG_B1_P5_U0_CFG25 0x40011a59u +#define CYDEV_UCFG_B1_P5_U0_CFG26 0x40011a5au +#define CYDEV_UCFG_B1_P5_U0_CFG27 0x40011a5bu +#define CYDEV_UCFG_B1_P5_U0_CFG28 0x40011a5cu +#define CYDEV_UCFG_B1_P5_U0_CFG29 0x40011a5du +#define CYDEV_UCFG_B1_P5_U0_CFG30 0x40011a5eu +#define CYDEV_UCFG_B1_P5_U0_CFG31 0x40011a5fu +#define CYDEV_UCFG_B1_P5_U0_DCFG0 0x40011a60u +#define CYDEV_UCFG_B1_P5_U0_DCFG1 0x40011a62u +#define CYDEV_UCFG_B1_P5_U0_DCFG2 0x40011a64u +#define CYDEV_UCFG_B1_P5_U0_DCFG3 0x40011a66u +#define CYDEV_UCFG_B1_P5_U0_DCFG4 0x40011a68u +#define CYDEV_UCFG_B1_P5_U0_DCFG5 0x40011a6au +#define CYDEV_UCFG_B1_P5_U0_DCFG6 0x40011a6cu +#define CYDEV_UCFG_B1_P5_U0_DCFG7 0x40011a6eu +#define CYDEV_UCFG_B1_P5_U1_BASE 0x40011a80u +#define CYDEV_UCFG_B1_P5_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT0 0x40011a80u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT1 0x40011a84u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT2 0x40011a88u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT3 0x40011a8cu +#define CYDEV_UCFG_B1_P5_U1_PLD_IT4 0x40011a90u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT5 0x40011a94u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT6 0x40011a98u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT7 0x40011a9cu +#define CYDEV_UCFG_B1_P5_U1_PLD_IT8 0x40011aa0u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT9 0x40011aa4u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT10 0x40011aa8u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT11 0x40011aacu +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT0 0x40011ab0u +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT1 0x40011ab2u +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT2 0x40011ab4u +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT3 0x40011ab6u +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST 0x40011ab8u +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB 0x40011abau +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET 0x40011abcu +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS 0x40011abeu +#define CYDEV_UCFG_B1_P5_U1_CFG0 0x40011ac0u +#define CYDEV_UCFG_B1_P5_U1_CFG1 0x40011ac1u +#define CYDEV_UCFG_B1_P5_U1_CFG2 0x40011ac2u +#define CYDEV_UCFG_B1_P5_U1_CFG3 0x40011ac3u +#define CYDEV_UCFG_B1_P5_U1_CFG4 0x40011ac4u +#define CYDEV_UCFG_B1_P5_U1_CFG5 0x40011ac5u +#define CYDEV_UCFG_B1_P5_U1_CFG6 0x40011ac6u +#define CYDEV_UCFG_B1_P5_U1_CFG7 0x40011ac7u +#define CYDEV_UCFG_B1_P5_U1_CFG8 0x40011ac8u +#define CYDEV_UCFG_B1_P5_U1_CFG9 0x40011ac9u +#define CYDEV_UCFG_B1_P5_U1_CFG10 0x40011acau +#define CYDEV_UCFG_B1_P5_U1_CFG11 0x40011acbu +#define CYDEV_UCFG_B1_P5_U1_CFG12 0x40011accu +#define CYDEV_UCFG_B1_P5_U1_CFG13 0x40011acdu +#define CYDEV_UCFG_B1_P5_U1_CFG14 0x40011aceu +#define CYDEV_UCFG_B1_P5_U1_CFG15 0x40011acfu +#define CYDEV_UCFG_B1_P5_U1_CFG16 0x40011ad0u +#define CYDEV_UCFG_B1_P5_U1_CFG17 0x40011ad1u +#define CYDEV_UCFG_B1_P5_U1_CFG18 0x40011ad2u +#define CYDEV_UCFG_B1_P5_U1_CFG19 0x40011ad3u +#define CYDEV_UCFG_B1_P5_U1_CFG20 0x40011ad4u +#define CYDEV_UCFG_B1_P5_U1_CFG21 0x40011ad5u +#define CYDEV_UCFG_B1_P5_U1_CFG22 0x40011ad6u +#define CYDEV_UCFG_B1_P5_U1_CFG23 0x40011ad7u +#define CYDEV_UCFG_B1_P5_U1_CFG24 0x40011ad8u +#define CYDEV_UCFG_B1_P5_U1_CFG25 0x40011ad9u +#define CYDEV_UCFG_B1_P5_U1_CFG26 0x40011adau +#define CYDEV_UCFG_B1_P5_U1_CFG27 0x40011adbu +#define CYDEV_UCFG_B1_P5_U1_CFG28 0x40011adcu +#define CYDEV_UCFG_B1_P5_U1_CFG29 0x40011addu +#define CYDEV_UCFG_B1_P5_U1_CFG30 0x40011adeu +#define CYDEV_UCFG_B1_P5_U1_CFG31 0x40011adfu +#define CYDEV_UCFG_B1_P5_U1_DCFG0 0x40011ae0u +#define CYDEV_UCFG_B1_P5_U1_DCFG1 0x40011ae2u +#define CYDEV_UCFG_B1_P5_U1_DCFG2 0x40011ae4u +#define CYDEV_UCFG_B1_P5_U1_DCFG3 0x40011ae6u +#define CYDEV_UCFG_B1_P5_U1_DCFG4 0x40011ae8u +#define CYDEV_UCFG_B1_P5_U1_DCFG5 0x40011aeau +#define CYDEV_UCFG_B1_P5_U1_DCFG6 0x40011aecu +#define CYDEV_UCFG_B1_P5_U1_DCFG7 0x40011aeeu +#define CYDEV_UCFG_B1_P5_ROUTE_BASE 0x40011b00u +#define CYDEV_UCFG_B1_P5_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_DSI0_BASE 0x40014000u +#define CYDEV_UCFG_DSI0_SIZE 0x000000efu +#define CYDEV_UCFG_DSI1_BASE 0x40014100u +#define CYDEV_UCFG_DSI1_SIZE 0x000000efu +#define CYDEV_UCFG_DSI2_BASE 0x40014200u +#define CYDEV_UCFG_DSI2_SIZE 0x000000efu +#define CYDEV_UCFG_DSI3_BASE 0x40014300u +#define CYDEV_UCFG_DSI3_SIZE 0x000000efu +#define CYDEV_UCFG_DSI4_BASE 0x40014400u +#define CYDEV_UCFG_DSI4_SIZE 0x000000efu +#define CYDEV_UCFG_DSI5_BASE 0x40014500u +#define CYDEV_UCFG_DSI5_SIZE 0x000000efu +#define CYDEV_UCFG_DSI6_BASE 0x40014600u +#define CYDEV_UCFG_DSI6_SIZE 0x000000efu +#define CYDEV_UCFG_DSI7_BASE 0x40014700u +#define CYDEV_UCFG_DSI7_SIZE 0x000000efu +#define CYDEV_UCFG_DSI8_BASE 0x40014800u +#define CYDEV_UCFG_DSI8_SIZE 0x000000efu +#define CYDEV_UCFG_DSI9_BASE 0x40014900u +#define CYDEV_UCFG_DSI9_SIZE 0x000000efu +#define CYDEV_UCFG_DSI12_BASE 0x40014c00u +#define CYDEV_UCFG_DSI12_SIZE 0x000000efu +#define CYDEV_UCFG_DSI13_BASE 0x40014d00u +#define CYDEV_UCFG_DSI13_SIZE 0x000000efu +#define CYDEV_UCFG_BCTL0_BASE 0x40015000u +#define CYDEV_UCFG_BCTL0_SIZE 0x00000010u +#define CYDEV_UCFG_BCTL0_MDCLK_EN 0x40015000u +#define CYDEV_UCFG_BCTL0_MBCLK_EN 0x40015001u +#define CYDEV_UCFG_BCTL0_WAIT_CFG 0x40015002u +#define CYDEV_UCFG_BCTL0_BANK_CTL 0x40015003u +#define CYDEV_UCFG_BCTL0_UDB_TEST_3 0x40015007u +#define CYDEV_UCFG_BCTL0_DCLK_EN0 0x40015008u +#define CYDEV_UCFG_BCTL0_BCLK_EN0 0x40015009u +#define CYDEV_UCFG_BCTL0_DCLK_EN1 0x4001500au +#define CYDEV_UCFG_BCTL0_BCLK_EN1 0x4001500bu +#define CYDEV_UCFG_BCTL0_DCLK_EN2 0x4001500cu +#define CYDEV_UCFG_BCTL0_BCLK_EN2 0x4001500du +#define CYDEV_UCFG_BCTL0_DCLK_EN3 0x4001500eu +#define CYDEV_UCFG_BCTL0_BCLK_EN3 0x4001500fu +#define CYDEV_UCFG_BCTL1_BASE 0x40015010u +#define CYDEV_UCFG_BCTL1_SIZE 0x00000010u +#define CYDEV_UCFG_BCTL1_MDCLK_EN 0x40015010u +#define CYDEV_UCFG_BCTL1_MBCLK_EN 0x40015011u +#define CYDEV_UCFG_BCTL1_WAIT_CFG 0x40015012u +#define CYDEV_UCFG_BCTL1_BANK_CTL 0x40015013u +#define CYDEV_UCFG_BCTL1_UDB_TEST_3 0x40015017u +#define CYDEV_UCFG_BCTL1_DCLK_EN0 0x40015018u +#define CYDEV_UCFG_BCTL1_BCLK_EN0 0x40015019u +#define CYDEV_UCFG_BCTL1_DCLK_EN1 0x4001501au +#define CYDEV_UCFG_BCTL1_BCLK_EN1 0x4001501bu +#define CYDEV_UCFG_BCTL1_DCLK_EN2 0x4001501cu +#define CYDEV_UCFG_BCTL1_BCLK_EN2 0x4001501du +#define CYDEV_UCFG_BCTL1_DCLK_EN3 0x4001501eu +#define CYDEV_UCFG_BCTL1_BCLK_EN3 0x4001501fu +#define CYDEV_IDMUX_BASE 0x40015100u +#define CYDEV_IDMUX_SIZE 0x00000016u +#define CYDEV_IDMUX_IRQ_CTL0 0x40015100u +#define CYDEV_IDMUX_IRQ_CTL1 0x40015101u +#define CYDEV_IDMUX_IRQ_CTL2 0x40015102u +#define CYDEV_IDMUX_IRQ_CTL3 0x40015103u +#define CYDEV_IDMUX_IRQ_CTL4 0x40015104u +#define CYDEV_IDMUX_IRQ_CTL5 0x40015105u +#define CYDEV_IDMUX_IRQ_CTL6 0x40015106u +#define CYDEV_IDMUX_IRQ_CTL7 0x40015107u +#define CYDEV_IDMUX_DRQ_CTL0 0x40015110u +#define CYDEV_IDMUX_DRQ_CTL1 0x40015111u +#define CYDEV_IDMUX_DRQ_CTL2 0x40015112u +#define CYDEV_IDMUX_DRQ_CTL3 0x40015113u +#define CYDEV_IDMUX_DRQ_CTL4 0x40015114u +#define CYDEV_IDMUX_DRQ_CTL5 0x40015115u +#define CYDEV_CACHERAM_BASE 0x40030000u +#define CYDEV_CACHERAM_SIZE 0x00000400u +#define CYDEV_CACHERAM_DATA_MBASE 0x40030000u +#define CYDEV_CACHERAM_DATA_MSIZE 0x00000400u +#define CYDEV_SFR_BASE 0x40050100u +#define CYDEV_SFR_SIZE 0x000000fbu +#define CYDEV_SFR_GPIO0 0x40050180u +#define CYDEV_SFR_GPIRD0 0x40050189u +#define CYDEV_SFR_GPIO0_SEL 0x4005018au +#define CYDEV_SFR_GPIO1 0x40050190u +#define CYDEV_SFR_GPIRD1 0x40050191u +#define CYDEV_SFR_GPIO2 0x40050198u +#define CYDEV_SFR_GPIRD2 0x40050199u +#define CYDEV_SFR_GPIO2_SEL 0x4005019au +#define CYDEV_SFR_GPIO1_SEL 0x400501a2u +#define CYDEV_SFR_GPIO3 0x400501b0u +#define CYDEV_SFR_GPIRD3 0x400501b1u +#define CYDEV_SFR_GPIO3_SEL 0x400501b2u +#define CYDEV_SFR_GPIO4 0x400501c0u +#define CYDEV_SFR_GPIRD4 0x400501c1u +#define CYDEV_SFR_GPIO4_SEL 0x400501c2u +#define CYDEV_SFR_GPIO5 0x400501c8u +#define CYDEV_SFR_GPIRD5 0x400501c9u +#define CYDEV_SFR_GPIO5_SEL 0x400501cau +#define CYDEV_SFR_GPIO6 0x400501d8u +#define CYDEV_SFR_GPIRD6 0x400501d9u +#define CYDEV_SFR_GPIO6_SEL 0x400501dau +#define CYDEV_SFR_GPIO12 0x400501e8u +#define CYDEV_SFR_GPIRD12 0x400501e9u +#define CYDEV_SFR_GPIO12_SEL 0x400501f2u +#define CYDEV_SFR_GPIO15 0x400501f8u +#define CYDEV_SFR_GPIRD15 0x400501f9u +#define CYDEV_SFR_GPIO15_SEL 0x400501fau +#define CYDEV_P3BA_BASE 0x40050300u +#define CYDEV_P3BA_SIZE 0x0000002bu +#define CYDEV_P3BA_Y_START 0x40050300u +#define CYDEV_P3BA_YROLL 0x40050301u +#define CYDEV_P3BA_YCFG 0x40050302u +#define CYDEV_P3BA_X_START1 0x40050303u +#define CYDEV_P3BA_X_START2 0x40050304u +#define CYDEV_P3BA_XROLL1 0x40050305u +#define CYDEV_P3BA_XROLL2 0x40050306u +#define CYDEV_P3BA_XINC 0x40050307u +#define CYDEV_P3BA_XCFG 0x40050308u +#define CYDEV_P3BA_OFFSETADDR1 0x40050309u +#define CYDEV_P3BA_OFFSETADDR2 0x4005030au +#define CYDEV_P3BA_OFFSETADDR3 0x4005030bu +#define CYDEV_P3BA_ABSADDR1 0x4005030cu +#define CYDEV_P3BA_ABSADDR2 0x4005030du +#define CYDEV_P3BA_ABSADDR3 0x4005030eu +#define CYDEV_P3BA_ABSADDR4 0x4005030fu +#define CYDEV_P3BA_DATCFG1 0x40050310u +#define CYDEV_P3BA_DATCFG2 0x40050311u +#define CYDEV_P3BA_CMP_RSLT1 0x40050314u +#define CYDEV_P3BA_CMP_RSLT2 0x40050315u +#define CYDEV_P3BA_CMP_RSLT3 0x40050316u +#define CYDEV_P3BA_CMP_RSLT4 0x40050317u +#define CYDEV_P3BA_DATA_REG1 0x40050318u +#define CYDEV_P3BA_DATA_REG2 0x40050319u +#define CYDEV_P3BA_DATA_REG3 0x4005031au +#define CYDEV_P3BA_DATA_REG4 0x4005031bu +#define CYDEV_P3BA_EXP_DATA1 0x4005031cu +#define CYDEV_P3BA_EXP_DATA2 0x4005031du +#define CYDEV_P3BA_EXP_DATA3 0x4005031eu +#define CYDEV_P3BA_EXP_DATA4 0x4005031fu +#define CYDEV_P3BA_MSTR_HRDATA1 0x40050320u +#define CYDEV_P3BA_MSTR_HRDATA2 0x40050321u +#define CYDEV_P3BA_MSTR_HRDATA3 0x40050322u +#define CYDEV_P3BA_MSTR_HRDATA4 0x40050323u +#define CYDEV_P3BA_BIST_EN 0x40050324u +#define CYDEV_P3BA_PHUB_MASTER_SSR 0x40050325u +#define CYDEV_P3BA_SEQCFG1 0x40050326u +#define CYDEV_P3BA_SEQCFG2 0x40050327u +#define CYDEV_P3BA_Y_CURR 0x40050328u +#define CYDEV_P3BA_X_CURR1 0x40050329u +#define CYDEV_P3BA_X_CURR2 0x4005032au +#define CYDEV_PANTHER_BASE 0x40080000u +#define CYDEV_PANTHER_SIZE 0x00000020u +#define CYDEV_PANTHER_STCALIB_CFG 0x40080000u +#define CYDEV_PANTHER_WAITPIPE 0x40080004u +#define CYDEV_PANTHER_TRACE_CFG 0x40080008u +#define CYDEV_PANTHER_DBG_CFG 0x4008000cu +#define CYDEV_PANTHER_CM3_LCKRST_STAT 0x40080018u +#define CYDEV_PANTHER_DEVICE_ID 0x4008001cu +#define CYDEV_FLSECC_BASE 0x48000000u +#define CYDEV_FLSECC_SIZE 0x00008000u +#define CYDEV_FLSECC_DATA_MBASE 0x48000000u +#define CYDEV_FLSECC_DATA_MSIZE 0x00008000u +#define CYDEV_FLSHID_BASE 0x49000000u +#define CYDEV_FLSHID_SIZE 0x00000200u +#define CYDEV_FLSHID_RSVD_MBASE 0x49000000u +#define CYDEV_FLSHID_RSVD_MSIZE 0x00000080u +#define CYDEV_FLSHID_CUST_MDATA_MBASE 0x49000080u +#define CYDEV_FLSHID_CUST_MDATA_MSIZE 0x00000080u +#define CYDEV_FLSHID_CUST_TABLES_BASE 0x49000100u +#define CYDEV_FLSHID_CUST_TABLES_SIZE 0x00000040u +#define CYDEV_FLSHID_CUST_TABLES_Y_LOC 0x49000100u +#define CYDEV_FLSHID_CUST_TABLES_X_LOC 0x49000101u +#define CYDEV_FLSHID_CUST_TABLES_WAFER_NUM 0x49000102u +#define CYDEV_FLSHID_CUST_TABLES_LOT_LSB 0x49000103u +#define CYDEV_FLSHID_CUST_TABLES_LOT_MSB 0x49000104u +#define CYDEV_FLSHID_CUST_TABLES_WRK_WK 0x49000105u +#define CYDEV_FLSHID_CUST_TABLES_FAB_YR 0x49000106u +#define CYDEV_FLSHID_CUST_TABLES_MINOR 0x49000107u +#define CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ 0x49000108u +#define CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ 0x49000109u +#define CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ 0x4900010au +#define CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ 0x4900010bu +#define CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ 0x4900010cu +#define CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ 0x4900010du +#define CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ 0x4900010eu +#define CYDEV_FLSHID_CUST_TABLES_IMO_USB 0x4900010fu +#define CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS 0x49000110u +#define CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS 0x49000111u +#define CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS 0x49000112u +#define CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS 0x49000113u +#define CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS 0x49000114u +#define CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS 0x49000115u +#define CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS 0x49000116u +#define CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS 0x49000117u +#define CYDEV_FLSHID_CUST_TABLES_DEC_M1 0x49000118u +#define CYDEV_FLSHID_CUST_TABLES_DEC_M2 0x49000119u +#define CYDEV_FLSHID_CUST_TABLES_DEC_M3 0x4900011au +#define CYDEV_FLSHID_CUST_TABLES_DEC_M4 0x4900011bu +#define CYDEV_FLSHID_CUST_TABLES_DEC_M5 0x4900011cu +#define CYDEV_FLSHID_CUST_TABLES_DEC_M6 0x4900011du +#define CYDEV_FLSHID_CUST_TABLES_DEC_M7 0x4900011eu +#define CYDEV_FLSHID_CUST_TABLES_DEC_M8 0x4900011fu +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M1 0x49000120u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M2 0x49000121u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M3 0x49000122u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M4 0x49000123u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M5 0x49000124u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M6 0x49000125u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M7 0x49000126u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M8 0x49000127u +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M1 0x49000128u +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M2 0x49000129u +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M3 0x4900012au +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M4 0x4900012bu +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M5 0x4900012cu +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M6 0x4900012du +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M7 0x4900012eu +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M8 0x4900012fu +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M1 0x49000130u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M2 0x49000131u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M3 0x49000132u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M4 0x49000133u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M5 0x49000134u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M6 0x49000135u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M7 0x49000136u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M8 0x49000137u +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M1 0x49000138u +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M2 0x49000139u +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M3 0x4900013au +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M4 0x4900013bu +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M5 0x4900013cu +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M6 0x4900013du +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M7 0x4900013eu +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M8 0x4900013fu +#define CYDEV_FLSHID_MFG_CFG_BASE 0x49000180u +#define CYDEV_FLSHID_MFG_CFG_SIZE 0x00000080u +#define CYDEV_FLSHID_MFG_CFG_IMO_TR1 0x49000188u +#define CYDEV_FLSHID_MFG_CFG_CMP0_TR0 0x490001acu +#define CYDEV_FLSHID_MFG_CFG_CMP1_TR0 0x490001aeu +#define CYDEV_FLSHID_MFG_CFG_CMP2_TR0 0x490001b0u +#define CYDEV_FLSHID_MFG_CFG_CMP3_TR0 0x490001b2u +#define CYDEV_FLSHID_MFG_CFG_CMP0_TR1 0x490001b4u +#define CYDEV_FLSHID_MFG_CFG_CMP1_TR1 0x490001b6u +#define CYDEV_FLSHID_MFG_CFG_CMP2_TR1 0x490001b8u +#define CYDEV_FLSHID_MFG_CFG_CMP3_TR1 0x490001bau +#define CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM 0x490001ceu +#define CYDEV_EXTMEM_BASE 0x60000000u +#define CYDEV_EXTMEM_SIZE 0x00800000u +#define CYDEV_EXTMEM_DATA_MBASE 0x60000000u +#define CYDEV_EXTMEM_DATA_MSIZE 0x00800000u +#define CYDEV_ITM_BASE 0xe0000000u +#define CYDEV_ITM_SIZE 0x00001000u +#define CYDEV_ITM_TRACE_EN 0xe0000e00u +#define CYDEV_ITM_TRACE_PRIVILEGE 0xe0000e40u +#define CYDEV_ITM_TRACE_CTRL 0xe0000e80u +#define CYDEV_ITM_LOCK_ACCESS 0xe0000fb0u +#define CYDEV_ITM_LOCK_STATUS 0xe0000fb4u +#define CYDEV_ITM_PID4 0xe0000fd0u +#define CYDEV_ITM_PID5 0xe0000fd4u +#define CYDEV_ITM_PID6 0xe0000fd8u +#define CYDEV_ITM_PID7 0xe0000fdcu +#define CYDEV_ITM_PID0 0xe0000fe0u +#define CYDEV_ITM_PID1 0xe0000fe4u +#define CYDEV_ITM_PID2 0xe0000fe8u +#define CYDEV_ITM_PID3 0xe0000fecu +#define CYDEV_ITM_CID0 0xe0000ff0u +#define CYDEV_ITM_CID1 0xe0000ff4u +#define CYDEV_ITM_CID2 0xe0000ff8u +#define CYDEV_ITM_CID3 0xe0000ffcu +#define CYDEV_DWT_BASE 0xe0001000u +#define CYDEV_DWT_SIZE 0x0000005cu +#define CYDEV_DWT_CTRL 0xe0001000u +#define CYDEV_DWT_CYCLE_COUNT 0xe0001004u +#define CYDEV_DWT_CPI_COUNT 0xe0001008u +#define CYDEV_DWT_EXC_OVHD_COUNT 0xe000100cu +#define CYDEV_DWT_SLEEP_COUNT 0xe0001010u +#define CYDEV_DWT_LSU_COUNT 0xe0001014u +#define CYDEV_DWT_FOLD_COUNT 0xe0001018u +#define CYDEV_DWT_PC_SAMPLE 0xe000101cu +#define CYDEV_DWT_COMP_0 0xe0001020u +#define CYDEV_DWT_MASK_0 0xe0001024u +#define CYDEV_DWT_FUNCTION_0 0xe0001028u +#define CYDEV_DWT_COMP_1 0xe0001030u +#define CYDEV_DWT_MASK_1 0xe0001034u +#define CYDEV_DWT_FUNCTION_1 0xe0001038u +#define CYDEV_DWT_COMP_2 0xe0001040u +#define CYDEV_DWT_MASK_2 0xe0001044u +#define CYDEV_DWT_FUNCTION_2 0xe0001048u +#define CYDEV_DWT_COMP_3 0xe0001050u +#define CYDEV_DWT_MASK_3 0xe0001054u +#define CYDEV_DWT_FUNCTION_3 0xe0001058u +#define CYDEV_FPB_BASE 0xe0002000u +#define CYDEV_FPB_SIZE 0x00001000u +#define CYDEV_FPB_CTRL 0xe0002000u +#define CYDEV_FPB_REMAP 0xe0002004u +#define CYDEV_FPB_FP_COMP_0 0xe0002008u +#define CYDEV_FPB_FP_COMP_1 0xe000200cu +#define CYDEV_FPB_FP_COMP_2 0xe0002010u +#define CYDEV_FPB_FP_COMP_3 0xe0002014u +#define CYDEV_FPB_FP_COMP_4 0xe0002018u +#define CYDEV_FPB_FP_COMP_5 0xe000201cu +#define CYDEV_FPB_FP_COMP_6 0xe0002020u +#define CYDEV_FPB_FP_COMP_7 0xe0002024u +#define CYDEV_FPB_PID4 0xe0002fd0u +#define CYDEV_FPB_PID5 0xe0002fd4u +#define CYDEV_FPB_PID6 0xe0002fd8u +#define CYDEV_FPB_PID7 0xe0002fdcu +#define CYDEV_FPB_PID0 0xe0002fe0u +#define CYDEV_FPB_PID1 0xe0002fe4u +#define CYDEV_FPB_PID2 0xe0002fe8u +#define CYDEV_FPB_PID3 0xe0002fecu +#define CYDEV_FPB_CID0 0xe0002ff0u +#define CYDEV_FPB_CID1 0xe0002ff4u +#define CYDEV_FPB_CID2 0xe0002ff8u +#define CYDEV_FPB_CID3 0xe0002ffcu +#define CYDEV_NVIC_BASE 0xe000e000u +#define CYDEV_NVIC_SIZE 0x00000d3cu +#define CYDEV_NVIC_INT_CTL_TYPE 0xe000e004u +#define CYDEV_NVIC_SYSTICK_CTL 0xe000e010u +#define CYDEV_NVIC_SYSTICK_RELOAD 0xe000e014u +#define CYDEV_NVIC_SYSTICK_CURRENT 0xe000e018u +#define CYDEV_NVIC_SYSTICK_CAL 0xe000e01cu +#define CYDEV_NVIC_SETENA0 0xe000e100u +#define CYDEV_NVIC_CLRENA0 0xe000e180u +#define CYDEV_NVIC_SETPEND0 0xe000e200u +#define CYDEV_NVIC_CLRPEND0 0xe000e280u +#define CYDEV_NVIC_ACTIVE0 0xe000e300u +#define CYDEV_NVIC_PRI_0 0xe000e400u +#define CYDEV_NVIC_PRI_1 0xe000e401u +#define CYDEV_NVIC_PRI_2 0xe000e402u +#define CYDEV_NVIC_PRI_3 0xe000e403u +#define CYDEV_NVIC_PRI_4 0xe000e404u +#define CYDEV_NVIC_PRI_5 0xe000e405u +#define CYDEV_NVIC_PRI_6 0xe000e406u +#define CYDEV_NVIC_PRI_7 0xe000e407u +#define CYDEV_NVIC_PRI_8 0xe000e408u +#define CYDEV_NVIC_PRI_9 0xe000e409u +#define CYDEV_NVIC_PRI_10 0xe000e40au +#define CYDEV_NVIC_PRI_11 0xe000e40bu +#define CYDEV_NVIC_PRI_12 0xe000e40cu +#define CYDEV_NVIC_PRI_13 0xe000e40du +#define CYDEV_NVIC_PRI_14 0xe000e40eu +#define CYDEV_NVIC_PRI_15 0xe000e40fu +#define CYDEV_NVIC_PRI_16 0xe000e410u +#define CYDEV_NVIC_PRI_17 0xe000e411u +#define CYDEV_NVIC_PRI_18 0xe000e412u +#define CYDEV_NVIC_PRI_19 0xe000e413u +#define CYDEV_NVIC_PRI_20 0xe000e414u +#define CYDEV_NVIC_PRI_21 0xe000e415u +#define CYDEV_NVIC_PRI_22 0xe000e416u +#define CYDEV_NVIC_PRI_23 0xe000e417u +#define CYDEV_NVIC_PRI_24 0xe000e418u +#define CYDEV_NVIC_PRI_25 0xe000e419u +#define CYDEV_NVIC_PRI_26 0xe000e41au +#define CYDEV_NVIC_PRI_27 0xe000e41bu +#define CYDEV_NVIC_PRI_28 0xe000e41cu +#define CYDEV_NVIC_PRI_29 0xe000e41du +#define CYDEV_NVIC_PRI_30 0xe000e41eu +#define CYDEV_NVIC_PRI_31 0xe000e41fu +#define CYDEV_NVIC_CPUID_BASE 0xe000ed00u +#define CYDEV_NVIC_INTR_CTRL_STATE 0xe000ed04u +#define CYDEV_NVIC_VECT_OFFSET 0xe000ed08u +#define CYDEV_NVIC_APPLN_INTR 0xe000ed0cu +#define CYDEV_NVIC_SYSTEM_CONTROL 0xe000ed10u +#define CYDEV_NVIC_CFG_CONTROL 0xe000ed14u +#define CYDEV_NVIC_SYS_PRIO_HANDLER_4_7 0xe000ed18u +#define CYDEV_NVIC_SYS_PRIO_HANDLER_8_11 0xe000ed1cu +#define CYDEV_NVIC_SYS_PRIO_HANDLER_12_15 0xe000ed20u +#define CYDEV_NVIC_SYS_HANDLER_CSR 0xe000ed24u +#define CYDEV_NVIC_MEMMAN_FAULT_STATUS 0xe000ed28u +#define CYDEV_NVIC_BUS_FAULT_STATUS 0xe000ed29u +#define CYDEV_NVIC_USAGE_FAULT_STATUS 0xe000ed2au +#define CYDEV_NVIC_HARD_FAULT_STATUS 0xe000ed2cu +#define CYDEV_NVIC_DEBUG_FAULT_STATUS 0xe000ed30u +#define CYDEV_NVIC_MEMMAN_FAULT_ADD 0xe000ed34u +#define CYDEV_NVIC_BUS_FAULT_ADD 0xe000ed38u +#define CYDEV_CORE_DBG_BASE 0xe000edf0u +#define CYDEV_CORE_DBG_SIZE 0x00000010u +#define CYDEV_CORE_DBG_DBG_HLT_CS 0xe000edf0u +#define CYDEV_CORE_DBG_DBG_REG_SEL 0xe000edf4u +#define CYDEV_CORE_DBG_DBG_REG_DATA 0xe000edf8u +#define CYDEV_CORE_DBG_EXC_MON_CTL 0xe000edfcu +#define CYDEV_TPIU_BASE 0xe0040000u +#define CYDEV_TPIU_SIZE 0x00001000u +#define CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ 0xe0040000u +#define CYDEV_TPIU_CURRENT_SYNC_PRT_SZ 0xe0040004u +#define CYDEV_TPIU_ASYNC_CLK_PRESCALER 0xe0040010u +#define CYDEV_TPIU_PROTOCOL 0xe00400f0u +#define CYDEV_TPIU_FORM_FLUSH_STAT 0xe0040300u +#define CYDEV_TPIU_FORM_FLUSH_CTRL 0xe0040304u +#define CYDEV_TPIU_TRIGGER 0xe0040ee8u +#define CYDEV_TPIU_ITETMDATA 0xe0040eecu +#define CYDEV_TPIU_ITATBCTR2 0xe0040ef0u +#define CYDEV_TPIU_ITATBCTR0 0xe0040ef8u +#define CYDEV_TPIU_ITITMDATA 0xe0040efcu +#define CYDEV_TPIU_ITCTRL 0xe0040f00u +#define CYDEV_TPIU_DEVID 0xe0040fc8u +#define CYDEV_TPIU_DEVTYPE 0xe0040fccu +#define CYDEV_TPIU_PID4 0xe0040fd0u +#define CYDEV_TPIU_PID5 0xe0040fd4u +#define CYDEV_TPIU_PID6 0xe0040fd8u +#define CYDEV_TPIU_PID7 0xe0040fdcu +#define CYDEV_TPIU_PID0 0xe0040fe0u +#define CYDEV_TPIU_PID1 0xe0040fe4u +#define CYDEV_TPIU_PID2 0xe0040fe8u +#define CYDEV_TPIU_PID3 0xe0040fecu +#define CYDEV_TPIU_CID0 0xe0040ff0u +#define CYDEV_TPIU_CID1 0xe0040ff4u +#define CYDEV_TPIU_CID2 0xe0040ff8u +#define CYDEV_TPIU_CID3 0xe0040ffcu +#define CYDEV_ETM_BASE 0xe0041000u +#define CYDEV_ETM_SIZE 0x00001000u +#define CYDEV_ETM_CTL 0xe0041000u +#define CYDEV_ETM_CFG_CODE 0xe0041004u +#define CYDEV_ETM_TRIG_EVENT 0xe0041008u +#define CYDEV_ETM_STATUS 0xe0041010u +#define CYDEV_ETM_SYS_CFG 0xe0041014u +#define CYDEV_ETM_TRACE_ENB_EVENT 0xe0041020u +#define CYDEV_ETM_TRACE_EN_CTRL1 0xe0041024u +#define CYDEV_ETM_FIFOFULL_LEVEL 0xe004102cu +#define CYDEV_ETM_SYNC_FREQ 0xe00411e0u +#define CYDEV_ETM_ETM_ID 0xe00411e4u +#define CYDEV_ETM_CFG_CODE_EXT 0xe00411e8u +#define CYDEV_ETM_TR_SS_EMBICE_CTRL 0xe00411f0u +#define CYDEV_ETM_CS_TRACE_ID 0xe0041200u +#define CYDEV_ETM_OS_LOCK_ACCESS 0xe0041300u +#define CYDEV_ETM_OS_LOCK_STATUS 0xe0041304u +#define CYDEV_ETM_PDSR 0xe0041314u +#define CYDEV_ETM_ITMISCIN 0xe0041ee0u +#define CYDEV_ETM_ITTRIGOUT 0xe0041ee8u +#define CYDEV_ETM_ITATBCTR2 0xe0041ef0u +#define CYDEV_ETM_ITATBCTR0 0xe0041ef8u +#define CYDEV_ETM_INT_MODE_CTRL 0xe0041f00u +#define CYDEV_ETM_CLM_TAG_SET 0xe0041fa0u +#define CYDEV_ETM_CLM_TAG_CLR 0xe0041fa4u +#define CYDEV_ETM_LOCK_ACCESS 0xe0041fb0u +#define CYDEV_ETM_LOCK_STATUS 0xe0041fb4u +#define CYDEV_ETM_AUTH_STATUS 0xe0041fb8u +#define CYDEV_ETM_DEV_TYPE 0xe0041fccu +#define CYDEV_ETM_PID4 0xe0041fd0u +#define CYDEV_ETM_PID5 0xe0041fd4u +#define CYDEV_ETM_PID6 0xe0041fd8u +#define CYDEV_ETM_PID7 0xe0041fdcu +#define CYDEV_ETM_PID0 0xe0041fe0u +#define CYDEV_ETM_PID1 0xe0041fe4u +#define CYDEV_ETM_PID2 0xe0041fe8u +#define CYDEV_ETM_PID3 0xe0041fecu +#define CYDEV_ETM_CID0 0xe0041ff0u +#define CYDEV_ETM_CID1 0xe0041ff4u +#define CYDEV_ETM_CID2 0xe0041ff8u +#define CYDEV_ETM_CID3 0xe0041ffcu +#define CYDEV_ROM_TABLE_BASE 0xe00ff000u +#define CYDEV_ROM_TABLE_SIZE 0x00001000u +#define CYDEV_ROM_TABLE_NVIC 0xe00ff000u +#define CYDEV_ROM_TABLE_DWT 0xe00ff004u +#define CYDEV_ROM_TABLE_FPB 0xe00ff008u +#define CYDEV_ROM_TABLE_ITM 0xe00ff00cu +#define CYDEV_ROM_TABLE_TPIU 0xe00ff010u +#define CYDEV_ROM_TABLE_ETM 0xe00ff014u +#define CYDEV_ROM_TABLE_END 0xe00ff018u +#define CYDEV_ROM_TABLE_MEMTYPE 0xe00fffccu +#define CYDEV_ROM_TABLE_PID4 0xe00fffd0u +#define CYDEV_ROM_TABLE_PID5 0xe00fffd4u +#define CYDEV_ROM_TABLE_PID6 0xe00fffd8u +#define CYDEV_ROM_TABLE_PID7 0xe00fffdcu +#define CYDEV_ROM_TABLE_PID0 0xe00fffe0u +#define CYDEV_ROM_TABLE_PID1 0xe00fffe4u +#define CYDEV_ROM_TABLE_PID2 0xe00fffe8u +#define CYDEV_ROM_TABLE_PID3 0xe00fffecu +#define CYDEV_ROM_TABLE_CID0 0xe00ffff0u +#define CYDEV_ROM_TABLE_CID1 0xe00ffff4u +#define CYDEV_ROM_TABLE_CID2 0xe00ffff8u +#define CYDEV_ROM_TABLE_CID3 0xe00ffffcu +#define CYDEV_FLS_SIZE CYDEV_FLASH_SIZE +#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE +#define CYDEV_FLS_SECTOR_SIZE 0x00010000u +#define CYDEV_FLS_ROW_SIZE 0x00000100u +#define CYDEV_ECC_SECTOR_SIZE 0x00002000u +#define CYDEV_ECC_ROW_SIZE 0x00000020u +#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400u +#define CYDEV_EEPROM_ROW_SIZE 0x00000010u +#define CYDEV_PERIPH_BASE CYDEV_CLKDIST_BASE +#define CYCLK_LD_DISABLE 0x00000004u +#define CYCLK_LD_SYNC_EN 0x00000002u +#define CYCLK_LD_LOAD 0x00000001u +#define CYCLK_PIPE 0x00000080u +#define CYCLK_SSS 0x00000040u +#define CYCLK_EARLY 0x00000020u +#define CYCLK_DUTY 0x00000010u +#define CYCLK_SYNC 0x00000008u +#define CYCLK_SRC_SEL_CLK_SYNC_D 0 +#define CYCLK_SRC_SEL_SYNC_DIG 0 +#define CYCLK_SRC_SEL_IMO 1 +#define CYCLK_SRC_SEL_XTAL_MHZ 2 +#define CYCLK_SRC_SEL_XTALM 2 +#define CYCLK_SRC_SEL_ILO 3 +#define CYCLK_SRC_SEL_PLL 4 +#define CYCLK_SRC_SEL_XTAL_KHZ 5 +#define CYCLK_SRC_SEL_XTALK 5 +#define CYCLK_SRC_SEL_DSI_G 6 +#define CYCLK_SRC_SEL_DSI_D 7 +#define CYCLK_SRC_SEL_CLK_SYNC_A 0 +#define CYCLK_SRC_SEL_DSI_A 7 +#endif /* CYDEVICE_H */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydevice_trm.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydevice_trm.h new file mode 100755 index 00000000..27a4bffb --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydevice_trm.h @@ -0,0 +1,5360 @@ +/******************************************************************************* +* FILENAME: cydevice_trm.h +* +* PSoC Creator 3.0 Component Pack 7 +* +* DESCRIPTION: +* This file provides all of the address values for the entire PSoC device. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#if !defined(CYDEVICE_TRM_H) +#define CYDEVICE_TRM_H +#define CYDEV_FLASH_BASE 0x00000000u +#define CYDEV_FLASH_SIZE 0x00020000u +#define CYREG_FLASH_DATA_MBASE 0x00000000u +#define CYREG_FLASH_DATA_MSIZE 0x00020000u +#define CYDEV_SRAM_BASE 0x1fffc000u +#define CYDEV_SRAM_SIZE 0x00008000u +#define CYREG_SRAM_CODE64K_MBASE 0x1fff8000u +#define CYREG_SRAM_CODE64K_MSIZE 0x00004000u +#define CYREG_SRAM_CODE32K_MBASE 0x1fffc000u +#define CYREG_SRAM_CODE32K_MSIZE 0x00002000u +#define CYREG_SRAM_CODE16K_MBASE 0x1fffe000u +#define CYREG_SRAM_CODE16K_MSIZE 0x00001000u +#define CYREG_SRAM_CODE_MBASE 0x1fffc000u +#define CYREG_SRAM_CODE_MSIZE 0x00004000u +#define CYREG_SRAM_DATA_MBASE 0x20000000u +#define CYREG_SRAM_DATA_MSIZE 0x00004000u +#define CYREG_SRAM_DATA16K_MBASE 0x20001000u +#define CYREG_SRAM_DATA16K_MSIZE 0x00001000u +#define CYREG_SRAM_DATA32K_MBASE 0x20002000u +#define CYREG_SRAM_DATA32K_MSIZE 0x00002000u +#define CYREG_SRAM_DATA64K_MBASE 0x20004000u +#define CYREG_SRAM_DATA64K_MSIZE 0x00004000u +#define CYDEV_DMA_BASE 0x20008000u +#define CYDEV_DMA_SIZE 0x00008000u +#define CYREG_DMA_SRAM64K_MBASE 0x20008000u +#define CYREG_DMA_SRAM64K_MSIZE 0x00004000u +#define CYREG_DMA_SRAM32K_MBASE 0x2000c000u +#define CYREG_DMA_SRAM32K_MSIZE 0x00002000u +#define CYREG_DMA_SRAM16K_MBASE 0x2000e000u +#define CYREG_DMA_SRAM16K_MSIZE 0x00001000u +#define CYREG_DMA_SRAM_MBASE 0x2000f000u +#define CYREG_DMA_SRAM_MSIZE 0x00001000u +#define CYDEV_CLKDIST_BASE 0x40004000u +#define CYDEV_CLKDIST_SIZE 0x00000110u +#define CYREG_CLKDIST_CR 0x40004000u +#define CYREG_CLKDIST_LD 0x40004001u +#define CYREG_CLKDIST_WRK0 0x40004002u +#define CYREG_CLKDIST_WRK1 0x40004003u +#define CYREG_CLKDIST_MSTR0 0x40004004u +#define CYREG_CLKDIST_MSTR1 0x40004005u +#define CYREG_CLKDIST_BCFG0 0x40004006u +#define CYREG_CLKDIST_BCFG1 0x40004007u +#define CYREG_CLKDIST_BCFG2 0x40004008u +#define CYREG_CLKDIST_UCFG 0x40004009u +#define CYREG_CLKDIST_DLY0 0x4000400au +#define CYREG_CLKDIST_DLY1 0x4000400bu +#define CYREG_CLKDIST_DMASK 0x40004010u +#define CYREG_CLKDIST_AMASK 0x40004014u +#define CYDEV_CLKDIST_DCFG0_BASE 0x40004080u +#define CYDEV_CLKDIST_DCFG0_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG0_CFG0 0x40004080u +#define CYREG_CLKDIST_DCFG0_CFG1 0x40004081u +#define CYREG_CLKDIST_DCFG0_CFG2 0x40004082u +#define CYDEV_CLKDIST_DCFG1_BASE 0x40004084u +#define CYDEV_CLKDIST_DCFG1_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG1_CFG0 0x40004084u +#define CYREG_CLKDIST_DCFG1_CFG1 0x40004085u +#define CYREG_CLKDIST_DCFG1_CFG2 0x40004086u +#define CYDEV_CLKDIST_DCFG2_BASE 0x40004088u +#define CYDEV_CLKDIST_DCFG2_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG2_CFG0 0x40004088u +#define CYREG_CLKDIST_DCFG2_CFG1 0x40004089u +#define CYREG_CLKDIST_DCFG2_CFG2 0x4000408au +#define CYDEV_CLKDIST_DCFG3_BASE 0x4000408cu +#define CYDEV_CLKDIST_DCFG3_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG3_CFG0 0x4000408cu +#define CYREG_CLKDIST_DCFG3_CFG1 0x4000408du +#define CYREG_CLKDIST_DCFG3_CFG2 0x4000408eu +#define CYDEV_CLKDIST_DCFG4_BASE 0x40004090u +#define CYDEV_CLKDIST_DCFG4_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG4_CFG0 0x40004090u +#define CYREG_CLKDIST_DCFG4_CFG1 0x40004091u +#define CYREG_CLKDIST_DCFG4_CFG2 0x40004092u +#define CYDEV_CLKDIST_DCFG5_BASE 0x40004094u +#define CYDEV_CLKDIST_DCFG5_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG5_CFG0 0x40004094u +#define CYREG_CLKDIST_DCFG5_CFG1 0x40004095u +#define CYREG_CLKDIST_DCFG5_CFG2 0x40004096u +#define CYDEV_CLKDIST_DCFG6_BASE 0x40004098u +#define CYDEV_CLKDIST_DCFG6_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG6_CFG0 0x40004098u +#define CYREG_CLKDIST_DCFG6_CFG1 0x40004099u +#define CYREG_CLKDIST_DCFG6_CFG2 0x4000409au +#define CYDEV_CLKDIST_DCFG7_BASE 0x4000409cu +#define CYDEV_CLKDIST_DCFG7_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG7_CFG0 0x4000409cu +#define CYREG_CLKDIST_DCFG7_CFG1 0x4000409du +#define CYREG_CLKDIST_DCFG7_CFG2 0x4000409eu +#define CYDEV_CLKDIST_ACFG0_BASE 0x40004100u +#define CYDEV_CLKDIST_ACFG0_SIZE 0x00000004u +#define CYREG_CLKDIST_ACFG0_CFG0 0x40004100u +#define CYREG_CLKDIST_ACFG0_CFG1 0x40004101u +#define CYREG_CLKDIST_ACFG0_CFG2 0x40004102u +#define CYREG_CLKDIST_ACFG0_CFG3 0x40004103u +#define CYDEV_CLKDIST_ACFG1_BASE 0x40004104u +#define CYDEV_CLKDIST_ACFG1_SIZE 0x00000004u +#define CYREG_CLKDIST_ACFG1_CFG0 0x40004104u +#define CYREG_CLKDIST_ACFG1_CFG1 0x40004105u +#define CYREG_CLKDIST_ACFG1_CFG2 0x40004106u +#define CYREG_CLKDIST_ACFG1_CFG3 0x40004107u +#define CYDEV_CLKDIST_ACFG2_BASE 0x40004108u +#define CYDEV_CLKDIST_ACFG2_SIZE 0x00000004u +#define CYREG_CLKDIST_ACFG2_CFG0 0x40004108u +#define CYREG_CLKDIST_ACFG2_CFG1 0x40004109u +#define CYREG_CLKDIST_ACFG2_CFG2 0x4000410au +#define CYREG_CLKDIST_ACFG2_CFG3 0x4000410bu +#define CYDEV_CLKDIST_ACFG3_BASE 0x4000410cu +#define CYDEV_CLKDIST_ACFG3_SIZE 0x00000004u +#define CYREG_CLKDIST_ACFG3_CFG0 0x4000410cu +#define CYREG_CLKDIST_ACFG3_CFG1 0x4000410du +#define CYREG_CLKDIST_ACFG3_CFG2 0x4000410eu +#define CYREG_CLKDIST_ACFG3_CFG3 0x4000410fu +#define CYDEV_FASTCLK_BASE 0x40004200u +#define CYDEV_FASTCLK_SIZE 0x00000026u +#define CYDEV_FASTCLK_IMO_BASE 0x40004200u +#define CYDEV_FASTCLK_IMO_SIZE 0x00000001u +#define CYREG_FASTCLK_IMO_CR 0x40004200u +#define CYDEV_FASTCLK_XMHZ_BASE 0x40004210u +#define CYDEV_FASTCLK_XMHZ_SIZE 0x00000004u +#define CYREG_FASTCLK_XMHZ_CSR 0x40004210u +#define CYREG_FASTCLK_XMHZ_CFG0 0x40004212u +#define CYREG_FASTCLK_XMHZ_CFG1 0x40004213u +#define CYDEV_FASTCLK_PLL_BASE 0x40004220u +#define CYDEV_FASTCLK_PLL_SIZE 0x00000006u +#define CYREG_FASTCLK_PLL_CFG0 0x40004220u +#define CYREG_FASTCLK_PLL_CFG1 0x40004221u +#define CYREG_FASTCLK_PLL_P 0x40004222u +#define CYREG_FASTCLK_PLL_Q 0x40004223u +#define CYREG_FASTCLK_PLL_SR 0x40004225u +#define CYDEV_SLOWCLK_BASE 0x40004300u +#define CYDEV_SLOWCLK_SIZE 0x0000000bu +#define CYDEV_SLOWCLK_ILO_BASE 0x40004300u +#define CYDEV_SLOWCLK_ILO_SIZE 0x00000002u +#define CYREG_SLOWCLK_ILO_CR0 0x40004300u +#define CYREG_SLOWCLK_ILO_CR1 0x40004301u +#define CYDEV_SLOWCLK_X32_BASE 0x40004308u +#define CYDEV_SLOWCLK_X32_SIZE 0x00000003u +#define CYREG_SLOWCLK_X32_CR 0x40004308u +#define CYREG_SLOWCLK_X32_CFG 0x40004309u +#define CYREG_SLOWCLK_X32_TST 0x4000430au +#define CYDEV_BOOST_BASE 0x40004320u +#define CYDEV_BOOST_SIZE 0x00000007u +#define CYREG_BOOST_CR0 0x40004320u +#define CYREG_BOOST_CR1 0x40004321u +#define CYREG_BOOST_CR2 0x40004322u +#define CYREG_BOOST_CR3 0x40004323u +#define CYREG_BOOST_SR 0x40004324u +#define CYREG_BOOST_CR4 0x40004325u +#define CYREG_BOOST_SR2 0x40004326u +#define CYDEV_PWRSYS_BASE 0x40004330u +#define CYDEV_PWRSYS_SIZE 0x00000002u +#define CYREG_PWRSYS_CR0 0x40004330u +#define CYREG_PWRSYS_CR1 0x40004331u +#define CYDEV_PM_BASE 0x40004380u +#define CYDEV_PM_SIZE 0x00000057u +#define CYREG_PM_TW_CFG0 0x40004380u +#define CYREG_PM_TW_CFG1 0x40004381u +#define CYREG_PM_TW_CFG2 0x40004382u +#define CYREG_PM_WDT_CFG 0x40004383u +#define CYREG_PM_WDT_CR 0x40004384u +#define CYREG_PM_INT_SR 0x40004390u +#define CYREG_PM_MODE_CFG0 0x40004391u +#define CYREG_PM_MODE_CFG1 0x40004392u +#define CYREG_PM_MODE_CSR 0x40004393u +#define CYREG_PM_USB_CR0 0x40004394u +#define CYREG_PM_WAKEUP_CFG0 0x40004398u +#define CYREG_PM_WAKEUP_CFG1 0x40004399u +#define CYREG_PM_WAKEUP_CFG2 0x4000439au +#define CYDEV_PM_ACT_BASE 0x400043a0u +#define CYDEV_PM_ACT_SIZE 0x0000000eu +#define CYREG_PM_ACT_CFG0 0x400043a0u +#define CYREG_PM_ACT_CFG1 0x400043a1u +#define CYREG_PM_ACT_CFG2 0x400043a2u +#define CYREG_PM_ACT_CFG3 0x400043a3u +#define CYREG_PM_ACT_CFG4 0x400043a4u +#define CYREG_PM_ACT_CFG5 0x400043a5u +#define CYREG_PM_ACT_CFG6 0x400043a6u +#define CYREG_PM_ACT_CFG7 0x400043a7u +#define CYREG_PM_ACT_CFG8 0x400043a8u +#define CYREG_PM_ACT_CFG9 0x400043a9u +#define CYREG_PM_ACT_CFG10 0x400043aau +#define CYREG_PM_ACT_CFG11 0x400043abu +#define CYREG_PM_ACT_CFG12 0x400043acu +#define CYREG_PM_ACT_CFG13 0x400043adu +#define CYDEV_PM_STBY_BASE 0x400043b0u +#define CYDEV_PM_STBY_SIZE 0x0000000eu +#define CYREG_PM_STBY_CFG0 0x400043b0u +#define CYREG_PM_STBY_CFG1 0x400043b1u +#define CYREG_PM_STBY_CFG2 0x400043b2u +#define CYREG_PM_STBY_CFG3 0x400043b3u +#define CYREG_PM_STBY_CFG4 0x400043b4u +#define CYREG_PM_STBY_CFG5 0x400043b5u +#define CYREG_PM_STBY_CFG6 0x400043b6u +#define CYREG_PM_STBY_CFG7 0x400043b7u +#define CYREG_PM_STBY_CFG8 0x400043b8u +#define CYREG_PM_STBY_CFG9 0x400043b9u +#define CYREG_PM_STBY_CFG10 0x400043bau +#define CYREG_PM_STBY_CFG11 0x400043bbu +#define CYREG_PM_STBY_CFG12 0x400043bcu +#define CYREG_PM_STBY_CFG13 0x400043bdu +#define CYDEV_PM_AVAIL_BASE 0x400043c0u +#define CYDEV_PM_AVAIL_SIZE 0x00000017u +#define CYREG_PM_AVAIL_CR0 0x400043c0u +#define CYREG_PM_AVAIL_CR1 0x400043c1u +#define CYREG_PM_AVAIL_CR2 0x400043c2u +#define CYREG_PM_AVAIL_CR3 0x400043c3u +#define CYREG_PM_AVAIL_CR4 0x400043c4u +#define CYREG_PM_AVAIL_CR5 0x400043c5u +#define CYREG_PM_AVAIL_CR6 0x400043c6u +#define CYREG_PM_AVAIL_SR0 0x400043d0u +#define CYREG_PM_AVAIL_SR1 0x400043d1u +#define CYREG_PM_AVAIL_SR2 0x400043d2u +#define CYREG_PM_AVAIL_SR3 0x400043d3u +#define CYREG_PM_AVAIL_SR4 0x400043d4u +#define CYREG_PM_AVAIL_SR5 0x400043d5u +#define CYREG_PM_AVAIL_SR6 0x400043d6u +#define CYDEV_PICU_BASE 0x40004500u +#define CYDEV_PICU_SIZE 0x000000b0u +#define CYDEV_PICU_INTTYPE_BASE 0x40004500u +#define CYDEV_PICU_INTTYPE_SIZE 0x00000080u +#define CYDEV_PICU_INTTYPE_PICU0_BASE 0x40004500u +#define CYDEV_PICU_INTTYPE_PICU0_SIZE 0x00000008u +#define CYREG_PICU0_INTTYPE0 0x40004500u +#define CYREG_PICU0_INTTYPE1 0x40004501u +#define CYREG_PICU0_INTTYPE2 0x40004502u +#define CYREG_PICU0_INTTYPE3 0x40004503u +#define CYREG_PICU0_INTTYPE4 0x40004504u +#define CYREG_PICU0_INTTYPE5 0x40004505u +#define CYREG_PICU0_INTTYPE6 0x40004506u +#define CYREG_PICU0_INTTYPE7 0x40004507u +#define CYDEV_PICU_INTTYPE_PICU1_BASE 0x40004508u +#define CYDEV_PICU_INTTYPE_PICU1_SIZE 0x00000008u +#define CYREG_PICU1_INTTYPE0 0x40004508u +#define CYREG_PICU1_INTTYPE1 0x40004509u +#define CYREG_PICU1_INTTYPE2 0x4000450au +#define CYREG_PICU1_INTTYPE3 0x4000450bu +#define CYREG_PICU1_INTTYPE4 0x4000450cu +#define CYREG_PICU1_INTTYPE5 0x4000450du +#define CYREG_PICU1_INTTYPE6 0x4000450eu +#define CYREG_PICU1_INTTYPE7 0x4000450fu +#define CYDEV_PICU_INTTYPE_PICU2_BASE 0x40004510u +#define CYDEV_PICU_INTTYPE_PICU2_SIZE 0x00000008u +#define CYREG_PICU2_INTTYPE0 0x40004510u +#define CYREG_PICU2_INTTYPE1 0x40004511u +#define CYREG_PICU2_INTTYPE2 0x40004512u +#define CYREG_PICU2_INTTYPE3 0x40004513u +#define CYREG_PICU2_INTTYPE4 0x40004514u +#define CYREG_PICU2_INTTYPE5 0x40004515u +#define CYREG_PICU2_INTTYPE6 0x40004516u +#define CYREG_PICU2_INTTYPE7 0x40004517u +#define CYDEV_PICU_INTTYPE_PICU3_BASE 0x40004518u +#define CYDEV_PICU_INTTYPE_PICU3_SIZE 0x00000008u +#define CYREG_PICU3_INTTYPE0 0x40004518u +#define CYREG_PICU3_INTTYPE1 0x40004519u +#define CYREG_PICU3_INTTYPE2 0x4000451au +#define CYREG_PICU3_INTTYPE3 0x4000451bu +#define CYREG_PICU3_INTTYPE4 0x4000451cu +#define CYREG_PICU3_INTTYPE5 0x4000451du +#define CYREG_PICU3_INTTYPE6 0x4000451eu +#define CYREG_PICU3_INTTYPE7 0x4000451fu +#define CYDEV_PICU_INTTYPE_PICU4_BASE 0x40004520u +#define CYDEV_PICU_INTTYPE_PICU4_SIZE 0x00000008u +#define CYREG_PICU4_INTTYPE0 0x40004520u +#define CYREG_PICU4_INTTYPE1 0x40004521u +#define CYREG_PICU4_INTTYPE2 0x40004522u +#define CYREG_PICU4_INTTYPE3 0x40004523u +#define CYREG_PICU4_INTTYPE4 0x40004524u +#define CYREG_PICU4_INTTYPE5 0x40004525u +#define CYREG_PICU4_INTTYPE6 0x40004526u +#define CYREG_PICU4_INTTYPE7 0x40004527u +#define CYDEV_PICU_INTTYPE_PICU5_BASE 0x40004528u +#define CYDEV_PICU_INTTYPE_PICU5_SIZE 0x00000008u +#define CYREG_PICU5_INTTYPE0 0x40004528u +#define CYREG_PICU5_INTTYPE1 0x40004529u +#define CYREG_PICU5_INTTYPE2 0x4000452au +#define CYREG_PICU5_INTTYPE3 0x4000452bu +#define CYREG_PICU5_INTTYPE4 0x4000452cu +#define CYREG_PICU5_INTTYPE5 0x4000452du +#define CYREG_PICU5_INTTYPE6 0x4000452eu +#define CYREG_PICU5_INTTYPE7 0x4000452fu +#define CYDEV_PICU_INTTYPE_PICU6_BASE 0x40004530u +#define CYDEV_PICU_INTTYPE_PICU6_SIZE 0x00000008u +#define CYREG_PICU6_INTTYPE0 0x40004530u +#define CYREG_PICU6_INTTYPE1 0x40004531u +#define CYREG_PICU6_INTTYPE2 0x40004532u +#define CYREG_PICU6_INTTYPE3 0x40004533u +#define CYREG_PICU6_INTTYPE4 0x40004534u +#define CYREG_PICU6_INTTYPE5 0x40004535u +#define CYREG_PICU6_INTTYPE6 0x40004536u +#define CYREG_PICU6_INTTYPE7 0x40004537u +#define CYDEV_PICU_INTTYPE_PICU12_BASE 0x40004560u +#define CYDEV_PICU_INTTYPE_PICU12_SIZE 0x00000008u +#define CYREG_PICU12_INTTYPE0 0x40004560u +#define CYREG_PICU12_INTTYPE1 0x40004561u +#define CYREG_PICU12_INTTYPE2 0x40004562u +#define CYREG_PICU12_INTTYPE3 0x40004563u +#define CYREG_PICU12_INTTYPE4 0x40004564u +#define CYREG_PICU12_INTTYPE5 0x40004565u +#define CYREG_PICU12_INTTYPE6 0x40004566u +#define CYREG_PICU12_INTTYPE7 0x40004567u +#define CYDEV_PICU_INTTYPE_PICU15_BASE 0x40004578u +#define CYDEV_PICU_INTTYPE_PICU15_SIZE 0x00000008u +#define CYREG_PICU15_INTTYPE0 0x40004578u +#define CYREG_PICU15_INTTYPE1 0x40004579u +#define CYREG_PICU15_INTTYPE2 0x4000457au +#define CYREG_PICU15_INTTYPE3 0x4000457bu +#define CYREG_PICU15_INTTYPE4 0x4000457cu +#define CYREG_PICU15_INTTYPE5 0x4000457du +#define CYREG_PICU15_INTTYPE6 0x4000457eu +#define CYREG_PICU15_INTTYPE7 0x4000457fu +#define CYDEV_PICU_STAT_BASE 0x40004580u +#define CYDEV_PICU_STAT_SIZE 0x00000010u +#define CYDEV_PICU_STAT_PICU0_BASE 0x40004580u +#define CYDEV_PICU_STAT_PICU0_SIZE 0x00000001u +#define CYREG_PICU0_INTSTAT 0x40004580u +#define CYDEV_PICU_STAT_PICU1_BASE 0x40004581u +#define CYDEV_PICU_STAT_PICU1_SIZE 0x00000001u +#define CYREG_PICU1_INTSTAT 0x40004581u +#define CYDEV_PICU_STAT_PICU2_BASE 0x40004582u +#define CYDEV_PICU_STAT_PICU2_SIZE 0x00000001u +#define CYREG_PICU2_INTSTAT 0x40004582u +#define CYDEV_PICU_STAT_PICU3_BASE 0x40004583u +#define CYDEV_PICU_STAT_PICU3_SIZE 0x00000001u +#define CYREG_PICU3_INTSTAT 0x40004583u +#define CYDEV_PICU_STAT_PICU4_BASE 0x40004584u +#define CYDEV_PICU_STAT_PICU4_SIZE 0x00000001u +#define CYREG_PICU4_INTSTAT 0x40004584u +#define CYDEV_PICU_STAT_PICU5_BASE 0x40004585u +#define CYDEV_PICU_STAT_PICU5_SIZE 0x00000001u +#define CYREG_PICU5_INTSTAT 0x40004585u +#define CYDEV_PICU_STAT_PICU6_BASE 0x40004586u +#define CYDEV_PICU_STAT_PICU6_SIZE 0x00000001u +#define CYREG_PICU6_INTSTAT 0x40004586u +#define CYDEV_PICU_STAT_PICU12_BASE 0x4000458cu +#define CYDEV_PICU_STAT_PICU12_SIZE 0x00000001u +#define CYREG_PICU12_INTSTAT 0x4000458cu +#define CYDEV_PICU_STAT_PICU15_BASE 0x4000458fu +#define CYDEV_PICU_STAT_PICU15_SIZE 0x00000001u +#define CYREG_PICU15_INTSTAT 0x4000458fu +#define CYDEV_PICU_SNAP_BASE 0x40004590u +#define CYDEV_PICU_SNAP_SIZE 0x00000010u +#define CYDEV_PICU_SNAP_PICU0_BASE 0x40004590u +#define CYDEV_PICU_SNAP_PICU0_SIZE 0x00000001u +#define CYREG_PICU0_SNAP 0x40004590u +#define CYDEV_PICU_SNAP_PICU1_BASE 0x40004591u +#define CYDEV_PICU_SNAP_PICU1_SIZE 0x00000001u +#define CYREG_PICU1_SNAP 0x40004591u +#define CYDEV_PICU_SNAP_PICU2_BASE 0x40004592u +#define CYDEV_PICU_SNAP_PICU2_SIZE 0x00000001u +#define CYREG_PICU2_SNAP 0x40004592u +#define CYDEV_PICU_SNAP_PICU3_BASE 0x40004593u +#define CYDEV_PICU_SNAP_PICU3_SIZE 0x00000001u +#define CYREG_PICU3_SNAP 0x40004593u +#define CYDEV_PICU_SNAP_PICU4_BASE 0x40004594u +#define CYDEV_PICU_SNAP_PICU4_SIZE 0x00000001u +#define CYREG_PICU4_SNAP 0x40004594u +#define CYDEV_PICU_SNAP_PICU5_BASE 0x40004595u +#define CYDEV_PICU_SNAP_PICU5_SIZE 0x00000001u +#define CYREG_PICU5_SNAP 0x40004595u +#define CYDEV_PICU_SNAP_PICU6_BASE 0x40004596u +#define CYDEV_PICU_SNAP_PICU6_SIZE 0x00000001u +#define CYREG_PICU6_SNAP 0x40004596u +#define CYDEV_PICU_SNAP_PICU12_BASE 0x4000459cu +#define CYDEV_PICU_SNAP_PICU12_SIZE 0x00000001u +#define CYREG_PICU12_SNAP 0x4000459cu +#define CYDEV_PICU_SNAP_PICU_15_BASE 0x4000459fu +#define CYDEV_PICU_SNAP_PICU_15_SIZE 0x00000001u +#define CYREG_PICU_15_SNAP_15 0x4000459fu +#define CYDEV_PICU_DISABLE_COR_BASE 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_SIZE 0x00000010u +#define CYDEV_PICU_DISABLE_COR_PICU0_BASE 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_PICU0_SIZE 0x00000001u +#define CYREG_PICU0_DISABLE_COR 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_PICU1_BASE 0x400045a1u +#define CYDEV_PICU_DISABLE_COR_PICU1_SIZE 0x00000001u +#define CYREG_PICU1_DISABLE_COR 0x400045a1u +#define CYDEV_PICU_DISABLE_COR_PICU2_BASE 0x400045a2u +#define CYDEV_PICU_DISABLE_COR_PICU2_SIZE 0x00000001u +#define CYREG_PICU2_DISABLE_COR 0x400045a2u +#define CYDEV_PICU_DISABLE_COR_PICU3_BASE 0x400045a3u +#define CYDEV_PICU_DISABLE_COR_PICU3_SIZE 0x00000001u +#define CYREG_PICU3_DISABLE_COR 0x400045a3u +#define CYDEV_PICU_DISABLE_COR_PICU4_BASE 0x400045a4u +#define CYDEV_PICU_DISABLE_COR_PICU4_SIZE 0x00000001u +#define CYREG_PICU4_DISABLE_COR 0x400045a4u +#define CYDEV_PICU_DISABLE_COR_PICU5_BASE 0x400045a5u +#define CYDEV_PICU_DISABLE_COR_PICU5_SIZE 0x00000001u +#define CYREG_PICU5_DISABLE_COR 0x400045a5u +#define CYDEV_PICU_DISABLE_COR_PICU6_BASE 0x400045a6u +#define CYDEV_PICU_DISABLE_COR_PICU6_SIZE 0x00000001u +#define CYREG_PICU6_DISABLE_COR 0x400045a6u +#define CYDEV_PICU_DISABLE_COR_PICU12_BASE 0x400045acu +#define CYDEV_PICU_DISABLE_COR_PICU12_SIZE 0x00000001u +#define CYREG_PICU12_DISABLE_COR 0x400045acu +#define CYDEV_PICU_DISABLE_COR_PICU15_BASE 0x400045afu +#define CYDEV_PICU_DISABLE_COR_PICU15_SIZE 0x00000001u +#define CYREG_PICU15_DISABLE_COR 0x400045afu +#define CYDEV_MFGCFG_BASE 0x40004600u +#define CYDEV_MFGCFG_SIZE 0x000000edu +#define CYDEV_MFGCFG_ANAIF_BASE 0x40004600u +#define CYDEV_MFGCFG_ANAIF_SIZE 0x00000038u +#define CYDEV_MFGCFG_ANAIF_DAC0_BASE 0x40004608u +#define CYDEV_MFGCFG_ANAIF_DAC0_SIZE 0x00000001u +#define CYREG_DAC0_TR 0x40004608u +#define CYDEV_MFGCFG_ANAIF_DAC1_BASE 0x40004609u +#define CYDEV_MFGCFG_ANAIF_DAC1_SIZE 0x00000001u +#define CYREG_DAC1_TR 0x40004609u +#define CYDEV_MFGCFG_ANAIF_DAC2_BASE 0x4000460au +#define CYDEV_MFGCFG_ANAIF_DAC2_SIZE 0x00000001u +#define CYREG_DAC2_TR 0x4000460au +#define CYDEV_MFGCFG_ANAIF_DAC3_BASE 0x4000460bu +#define CYDEV_MFGCFG_ANAIF_DAC3_SIZE 0x00000001u +#define CYREG_DAC3_TR 0x4000460bu +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE 0x40004610u +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE 0x00000001u +#define CYREG_NPUMP_DSM_TR0 0x40004610u +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE 0x40004611u +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE 0x00000001u +#define CYREG_NPUMP_SC_TR0 0x40004611u +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE 0x40004612u +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE 0x00000001u +#define CYREG_NPUMP_OPAMP_TR0 0x40004612u +#define CYDEV_MFGCFG_ANAIF_SAR0_BASE 0x40004614u +#define CYDEV_MFGCFG_ANAIF_SAR0_SIZE 0x00000001u +#define CYREG_SAR0_TR0 0x40004614u +#define CYDEV_MFGCFG_ANAIF_SAR1_BASE 0x40004616u +#define CYDEV_MFGCFG_ANAIF_SAR1_SIZE 0x00000001u +#define CYREG_SAR1_TR0 0x40004616u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_BASE 0x40004620u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE 0x00000002u +#define CYREG_OPAMP0_TR0 0x40004620u +#define CYREG_OPAMP0_TR1 0x40004621u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_BASE 0x40004622u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE 0x00000002u +#define CYREG_OPAMP1_TR0 0x40004622u +#define CYREG_OPAMP1_TR1 0x40004623u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_BASE 0x40004624u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE 0x00000002u +#define CYREG_OPAMP2_TR0 0x40004624u +#define CYREG_OPAMP2_TR1 0x40004625u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_BASE 0x40004626u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE 0x00000002u +#define CYREG_OPAMP3_TR0 0x40004626u +#define CYREG_OPAMP3_TR1 0x40004627u +#define CYDEV_MFGCFG_ANAIF_CMP0_BASE 0x40004630u +#define CYDEV_MFGCFG_ANAIF_CMP0_SIZE 0x00000002u +#define CYREG_CMP0_TR0 0x40004630u +#define CYREG_CMP0_TR1 0x40004631u +#define CYDEV_MFGCFG_ANAIF_CMP1_BASE 0x40004632u +#define CYDEV_MFGCFG_ANAIF_CMP1_SIZE 0x00000002u +#define CYREG_CMP1_TR0 0x40004632u +#define CYREG_CMP1_TR1 0x40004633u +#define CYDEV_MFGCFG_ANAIF_CMP2_BASE 0x40004634u +#define CYDEV_MFGCFG_ANAIF_CMP2_SIZE 0x00000002u +#define CYREG_CMP2_TR0 0x40004634u +#define CYREG_CMP2_TR1 0x40004635u +#define CYDEV_MFGCFG_ANAIF_CMP3_BASE 0x40004636u +#define CYDEV_MFGCFG_ANAIF_CMP3_SIZE 0x00000002u +#define CYREG_CMP3_TR0 0x40004636u +#define CYREG_CMP3_TR1 0x40004637u +#define CYDEV_MFGCFG_PWRSYS_BASE 0x40004680u +#define CYDEV_MFGCFG_PWRSYS_SIZE 0x0000000bu +#define CYREG_PWRSYS_HIB_TR0 0x40004680u +#define CYREG_PWRSYS_HIB_TR1 0x40004681u +#define CYREG_PWRSYS_I2C_TR 0x40004682u +#define CYREG_PWRSYS_SLP_TR 0x40004683u +#define CYREG_PWRSYS_BUZZ_TR 0x40004684u +#define CYREG_PWRSYS_WAKE_TR0 0x40004685u +#define CYREG_PWRSYS_WAKE_TR1 0x40004686u +#define CYREG_PWRSYS_BREF_TR 0x40004687u +#define CYREG_PWRSYS_BG_TR 0x40004688u +#define CYREG_PWRSYS_WAKE_TR2 0x40004689u +#define CYREG_PWRSYS_WAKE_TR3 0x4000468au +#define CYDEV_MFGCFG_ILO_BASE 0x40004690u +#define CYDEV_MFGCFG_ILO_SIZE 0x00000002u +#define CYREG_ILO_TR0 0x40004690u +#define CYREG_ILO_TR1 0x40004691u +#define CYDEV_MFGCFG_X32_BASE 0x40004698u +#define CYDEV_MFGCFG_X32_SIZE 0x00000001u +#define CYREG_X32_TR 0x40004698u +#define CYDEV_MFGCFG_IMO_BASE 0x400046a0u +#define CYDEV_MFGCFG_IMO_SIZE 0x00000005u +#define CYREG_IMO_TR0 0x400046a0u +#define CYREG_IMO_TR1 0x400046a1u +#define CYREG_IMO_GAIN 0x400046a2u +#define CYREG_IMO_C36M 0x400046a3u +#define CYREG_IMO_TR2 0x400046a4u +#define CYDEV_MFGCFG_XMHZ_BASE 0x400046a8u +#define CYDEV_MFGCFG_XMHZ_SIZE 0x00000001u +#define CYREG_XMHZ_TR 0x400046a8u +#define CYREG_MFGCFG_DLY 0x400046c0u +#define CYDEV_MFGCFG_MLOGIC_BASE 0x400046e0u +#define CYDEV_MFGCFG_MLOGIC_SIZE 0x0000000du +#define CYREG_MLOGIC_DMPSTR 0x400046e2u +#define CYDEV_MFGCFG_MLOGIC_SEG_BASE 0x400046e4u +#define CYDEV_MFGCFG_MLOGIC_SEG_SIZE 0x00000002u +#define CYREG_MLOGIC_SEG_CR 0x400046e4u +#define CYREG_MLOGIC_SEG_CFG0 0x400046e5u +#define CYREG_MLOGIC_DEBUG 0x400046e8u +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE 0x400046eau +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE 0x00000001u +#define CYREG_MLOGIC_CPU_SCR_CPU_SCR 0x400046eau +#define CYREG_MLOGIC_REV_ID 0x400046ecu +#define CYDEV_RESET_BASE 0x400046f0u +#define CYDEV_RESET_SIZE 0x0000000fu +#define CYREG_RESET_IPOR_CR0 0x400046f0u +#define CYREG_RESET_IPOR_CR1 0x400046f1u +#define CYREG_RESET_IPOR_CR2 0x400046f2u +#define CYREG_RESET_IPOR_CR3 0x400046f3u +#define CYREG_RESET_CR0 0x400046f4u +#define CYREG_RESET_CR1 0x400046f5u +#define CYREG_RESET_CR2 0x400046f6u +#define CYREG_RESET_CR3 0x400046f7u +#define CYREG_RESET_CR4 0x400046f8u +#define CYREG_RESET_CR5 0x400046f9u +#define CYREG_RESET_SR0 0x400046fau +#define CYREG_RESET_SR1 0x400046fbu +#define CYREG_RESET_SR2 0x400046fcu +#define CYREG_RESET_SR3 0x400046fdu +#define CYREG_RESET_TR 0x400046feu +#define CYDEV_SPC_BASE 0x40004700u +#define CYDEV_SPC_SIZE 0x00000100u +#define CYREG_SPC_FM_EE_CR 0x40004700u +#define CYREG_SPC_FM_EE_WAKE_CNT 0x40004701u +#define CYREG_SPC_EE_SCR 0x40004702u +#define CYREG_SPC_EE_ERR 0x40004703u +#define CYREG_SPC_CPU_DATA 0x40004720u +#define CYREG_SPC_DMA_DATA 0x40004721u +#define CYREG_SPC_SR 0x40004722u +#define CYREG_SPC_CR 0x40004723u +#define CYDEV_SPC_DMM_MAP_BASE 0x40004780u +#define CYDEV_SPC_DMM_MAP_SIZE 0x00000080u +#define CYREG_SPC_DMM_MAP_SRAM_MBASE 0x40004780u +#define CYREG_SPC_DMM_MAP_SRAM_MSIZE 0x00000080u +#define CYDEV_CACHE_BASE 0x40004800u +#define CYDEV_CACHE_SIZE 0x0000009cu +#define CYREG_CACHE_CC_CTL 0x40004800u +#define CYREG_CACHE_ECC_CORR 0x40004880u +#define CYREG_CACHE_ECC_ERR 0x40004888u +#define CYREG_CACHE_FLASH_ERR 0x40004890u +#define CYREG_CACHE_HITMISS 0x40004898u +#define CYDEV_I2C_BASE 0x40004900u +#define CYDEV_I2C_SIZE 0x000000e1u +#define CYREG_I2C_XCFG 0x400049c8u +#define CYREG_I2C_ADR 0x400049cau +#define CYREG_I2C_CFG 0x400049d6u +#define CYREG_I2C_CSR 0x400049d7u +#define CYREG_I2C_D 0x400049d8u +#define CYREG_I2C_MCSR 0x400049d9u +#define CYREG_I2C_CLK_DIV1 0x400049dbu +#define CYREG_I2C_CLK_DIV2 0x400049dcu +#define CYREG_I2C_TMOUT_CSR 0x400049ddu +#define CYREG_I2C_TMOUT_SR 0x400049deu +#define CYREG_I2C_TMOUT_CFG0 0x400049dfu +#define CYREG_I2C_TMOUT_CFG1 0x400049e0u +#define CYDEV_DEC_BASE 0x40004e00u +#define CYDEV_DEC_SIZE 0x00000015u +#define CYREG_DEC_CR 0x40004e00u +#define CYREG_DEC_SR 0x40004e01u +#define CYREG_DEC_SHIFT1 0x40004e02u +#define CYREG_DEC_SHIFT2 0x40004e03u +#define CYREG_DEC_DR2 0x40004e04u +#define CYREG_DEC_DR2H 0x40004e05u +#define CYREG_DEC_DR1 0x40004e06u +#define CYREG_DEC_OCOR 0x40004e08u +#define CYREG_DEC_OCORM 0x40004e09u +#define CYREG_DEC_OCORH 0x40004e0au +#define CYREG_DEC_GCOR 0x40004e0cu +#define CYREG_DEC_GCORH 0x40004e0du +#define CYREG_DEC_GVAL 0x40004e0eu +#define CYREG_DEC_OUTSAMP 0x40004e10u +#define CYREG_DEC_OUTSAMPM 0x40004e11u +#define CYREG_DEC_OUTSAMPH 0x40004e12u +#define CYREG_DEC_OUTSAMPS 0x40004e13u +#define CYREG_DEC_COHER 0x40004e14u +#define CYDEV_TMR0_BASE 0x40004f00u +#define CYDEV_TMR0_SIZE 0x0000000cu +#define CYREG_TMR0_CFG0 0x40004f00u +#define CYREG_TMR0_CFG1 0x40004f01u +#define CYREG_TMR0_CFG2 0x40004f02u +#define CYREG_TMR0_SR0 0x40004f03u +#define CYREG_TMR0_PER0 0x40004f04u +#define CYREG_TMR0_PER1 0x40004f05u +#define CYREG_TMR0_CNT_CMP0 0x40004f06u +#define CYREG_TMR0_CNT_CMP1 0x40004f07u +#define CYREG_TMR0_CAP0 0x40004f08u +#define CYREG_TMR0_CAP1 0x40004f09u +#define CYREG_TMR0_RT0 0x40004f0au +#define CYREG_TMR0_RT1 0x40004f0bu +#define CYDEV_TMR1_BASE 0x40004f0cu +#define CYDEV_TMR1_SIZE 0x0000000cu +#define CYREG_TMR1_CFG0 0x40004f0cu +#define CYREG_TMR1_CFG1 0x40004f0du +#define CYREG_TMR1_CFG2 0x40004f0eu +#define CYREG_TMR1_SR0 0x40004f0fu +#define CYREG_TMR1_PER0 0x40004f10u +#define CYREG_TMR1_PER1 0x40004f11u +#define CYREG_TMR1_CNT_CMP0 0x40004f12u +#define CYREG_TMR1_CNT_CMP1 0x40004f13u +#define CYREG_TMR1_CAP0 0x40004f14u +#define CYREG_TMR1_CAP1 0x40004f15u +#define CYREG_TMR1_RT0 0x40004f16u +#define CYREG_TMR1_RT1 0x40004f17u +#define CYDEV_TMR2_BASE 0x40004f18u +#define CYDEV_TMR2_SIZE 0x0000000cu +#define CYREG_TMR2_CFG0 0x40004f18u +#define CYREG_TMR2_CFG1 0x40004f19u +#define CYREG_TMR2_CFG2 0x40004f1au +#define CYREG_TMR2_SR0 0x40004f1bu +#define CYREG_TMR2_PER0 0x40004f1cu +#define CYREG_TMR2_PER1 0x40004f1du +#define CYREG_TMR2_CNT_CMP0 0x40004f1eu +#define CYREG_TMR2_CNT_CMP1 0x40004f1fu +#define CYREG_TMR2_CAP0 0x40004f20u +#define CYREG_TMR2_CAP1 0x40004f21u +#define CYREG_TMR2_RT0 0x40004f22u +#define CYREG_TMR2_RT1 0x40004f23u +#define CYDEV_TMR3_BASE 0x40004f24u +#define CYDEV_TMR3_SIZE 0x0000000cu +#define CYREG_TMR3_CFG0 0x40004f24u +#define CYREG_TMR3_CFG1 0x40004f25u +#define CYREG_TMR3_CFG2 0x40004f26u +#define CYREG_TMR3_SR0 0x40004f27u +#define CYREG_TMR3_PER0 0x40004f28u +#define CYREG_TMR3_PER1 0x40004f29u +#define CYREG_TMR3_CNT_CMP0 0x40004f2au +#define CYREG_TMR3_CNT_CMP1 0x40004f2bu +#define CYREG_TMR3_CAP0 0x40004f2cu +#define CYREG_TMR3_CAP1 0x40004f2du +#define CYREG_TMR3_RT0 0x40004f2eu +#define CYREG_TMR3_RT1 0x40004f2fu +#define CYDEV_IO_BASE 0x40005000u +#define CYDEV_IO_SIZE 0x00000200u +#define CYDEV_IO_PC_BASE 0x40005000u +#define CYDEV_IO_PC_SIZE 0x00000080u +#define CYDEV_IO_PC_PRT0_BASE 0x40005000u +#define CYDEV_IO_PC_PRT0_SIZE 0x00000008u +#define CYREG_PRT0_PC0 0x40005000u +#define CYREG_PRT0_PC1 0x40005001u +#define CYREG_PRT0_PC2 0x40005002u +#define CYREG_PRT0_PC3 0x40005003u +#define CYREG_PRT0_PC4 0x40005004u +#define CYREG_PRT0_PC5 0x40005005u +#define CYREG_PRT0_PC6 0x40005006u +#define CYREG_PRT0_PC7 0x40005007u +#define CYDEV_IO_PC_PRT1_BASE 0x40005008u +#define CYDEV_IO_PC_PRT1_SIZE 0x00000008u +#define CYREG_PRT1_PC0 0x40005008u +#define CYREG_PRT1_PC1 0x40005009u +#define CYREG_PRT1_PC2 0x4000500au +#define CYREG_PRT1_PC3 0x4000500bu +#define CYREG_PRT1_PC4 0x4000500cu +#define CYREG_PRT1_PC5 0x4000500du +#define CYREG_PRT1_PC6 0x4000500eu +#define CYREG_PRT1_PC7 0x4000500fu +#define CYDEV_IO_PC_PRT2_BASE 0x40005010u +#define CYDEV_IO_PC_PRT2_SIZE 0x00000008u +#define CYREG_PRT2_PC0 0x40005010u +#define CYREG_PRT2_PC1 0x40005011u +#define CYREG_PRT2_PC2 0x40005012u +#define CYREG_PRT2_PC3 0x40005013u +#define CYREG_PRT2_PC4 0x40005014u +#define CYREG_PRT2_PC5 0x40005015u +#define CYREG_PRT2_PC6 0x40005016u +#define CYREG_PRT2_PC7 0x40005017u +#define CYDEV_IO_PC_PRT3_BASE 0x40005018u +#define CYDEV_IO_PC_PRT3_SIZE 0x00000008u +#define CYREG_PRT3_PC0 0x40005018u +#define CYREG_PRT3_PC1 0x40005019u +#define CYREG_PRT3_PC2 0x4000501au +#define CYREG_PRT3_PC3 0x4000501bu +#define CYREG_PRT3_PC4 0x4000501cu +#define CYREG_PRT3_PC5 0x4000501du +#define CYREG_PRT3_PC6 0x4000501eu +#define CYREG_PRT3_PC7 0x4000501fu +#define CYDEV_IO_PC_PRT4_BASE 0x40005020u +#define CYDEV_IO_PC_PRT4_SIZE 0x00000008u +#define CYREG_PRT4_PC0 0x40005020u +#define CYREG_PRT4_PC1 0x40005021u +#define CYREG_PRT4_PC2 0x40005022u +#define CYREG_PRT4_PC3 0x40005023u +#define CYREG_PRT4_PC4 0x40005024u +#define CYREG_PRT4_PC5 0x40005025u +#define CYREG_PRT4_PC6 0x40005026u +#define CYREG_PRT4_PC7 0x40005027u +#define CYDEV_IO_PC_PRT5_BASE 0x40005028u +#define CYDEV_IO_PC_PRT5_SIZE 0x00000008u +#define CYREG_PRT5_PC0 0x40005028u +#define CYREG_PRT5_PC1 0x40005029u +#define CYREG_PRT5_PC2 0x4000502au +#define CYREG_PRT5_PC3 0x4000502bu +#define CYREG_PRT5_PC4 0x4000502cu +#define CYREG_PRT5_PC5 0x4000502du +#define CYREG_PRT5_PC6 0x4000502eu +#define CYREG_PRT5_PC7 0x4000502fu +#define CYDEV_IO_PC_PRT6_BASE 0x40005030u +#define CYDEV_IO_PC_PRT6_SIZE 0x00000008u +#define CYREG_PRT6_PC0 0x40005030u +#define CYREG_PRT6_PC1 0x40005031u +#define CYREG_PRT6_PC2 0x40005032u +#define CYREG_PRT6_PC3 0x40005033u +#define CYREG_PRT6_PC4 0x40005034u +#define CYREG_PRT6_PC5 0x40005035u +#define CYREG_PRT6_PC6 0x40005036u +#define CYREG_PRT6_PC7 0x40005037u +#define CYDEV_IO_PC_PRT12_BASE 0x40005060u +#define CYDEV_IO_PC_PRT12_SIZE 0x00000008u +#define CYREG_PRT12_PC0 0x40005060u +#define CYREG_PRT12_PC1 0x40005061u +#define CYREG_PRT12_PC2 0x40005062u +#define CYREG_PRT12_PC3 0x40005063u +#define CYREG_PRT12_PC4 0x40005064u +#define CYREG_PRT12_PC5 0x40005065u +#define CYREG_PRT12_PC6 0x40005066u +#define CYREG_PRT12_PC7 0x40005067u +#define CYDEV_IO_PC_PRT15_BASE 0x40005078u +#define CYDEV_IO_PC_PRT15_SIZE 0x00000006u +#define CYREG_IO_PC_PRT15_PC0 0x40005078u +#define CYREG_IO_PC_PRT15_PC1 0x40005079u +#define CYREG_IO_PC_PRT15_PC2 0x4000507au +#define CYREG_IO_PC_PRT15_PC3 0x4000507bu +#define CYREG_IO_PC_PRT15_PC4 0x4000507cu +#define CYREG_IO_PC_PRT15_PC5 0x4000507du +#define CYDEV_IO_PC_PRT15_7_6_BASE 0x4000507eu +#define CYDEV_IO_PC_PRT15_7_6_SIZE 0x00000002u +#define CYREG_IO_PC_PRT15_7_6_PC0 0x4000507eu +#define CYREG_IO_PC_PRT15_7_6_PC1 0x4000507fu +#define CYDEV_IO_DR_BASE 0x40005080u +#define CYDEV_IO_DR_SIZE 0x00000010u +#define CYDEV_IO_DR_PRT0_BASE 0x40005080u +#define CYDEV_IO_DR_PRT0_SIZE 0x00000001u +#define CYREG_PRT0_DR_ALIAS 0x40005080u +#define CYDEV_IO_DR_PRT1_BASE 0x40005081u +#define CYDEV_IO_DR_PRT1_SIZE 0x00000001u +#define CYREG_PRT1_DR_ALIAS 0x40005081u +#define CYDEV_IO_DR_PRT2_BASE 0x40005082u +#define CYDEV_IO_DR_PRT2_SIZE 0x00000001u +#define CYREG_PRT2_DR_ALIAS 0x40005082u +#define CYDEV_IO_DR_PRT3_BASE 0x40005083u +#define CYDEV_IO_DR_PRT3_SIZE 0x00000001u +#define CYREG_PRT3_DR_ALIAS 0x40005083u +#define CYDEV_IO_DR_PRT4_BASE 0x40005084u +#define CYDEV_IO_DR_PRT4_SIZE 0x00000001u +#define CYREG_PRT4_DR_ALIAS 0x40005084u +#define CYDEV_IO_DR_PRT5_BASE 0x40005085u +#define CYDEV_IO_DR_PRT5_SIZE 0x00000001u +#define CYREG_PRT5_DR_ALIAS 0x40005085u +#define CYDEV_IO_DR_PRT6_BASE 0x40005086u +#define CYDEV_IO_DR_PRT6_SIZE 0x00000001u +#define CYREG_PRT6_DR_ALIAS 0x40005086u +#define CYDEV_IO_DR_PRT12_BASE 0x4000508cu +#define CYDEV_IO_DR_PRT12_SIZE 0x00000001u +#define CYREG_PRT12_DR_ALIAS 0x4000508cu +#define CYDEV_IO_DR_PRT15_BASE 0x4000508fu +#define CYDEV_IO_DR_PRT15_SIZE 0x00000001u +#define CYREG_PRT15_DR_15_ALIAS 0x4000508fu +#define CYDEV_IO_PS_BASE 0x40005090u +#define CYDEV_IO_PS_SIZE 0x00000010u +#define CYDEV_IO_PS_PRT0_BASE 0x40005090u +#define CYDEV_IO_PS_PRT0_SIZE 0x00000001u +#define CYREG_PRT0_PS_ALIAS 0x40005090u +#define CYDEV_IO_PS_PRT1_BASE 0x40005091u +#define CYDEV_IO_PS_PRT1_SIZE 0x00000001u +#define CYREG_PRT1_PS_ALIAS 0x40005091u +#define CYDEV_IO_PS_PRT2_BASE 0x40005092u +#define CYDEV_IO_PS_PRT2_SIZE 0x00000001u +#define CYREG_PRT2_PS_ALIAS 0x40005092u +#define CYDEV_IO_PS_PRT3_BASE 0x40005093u +#define CYDEV_IO_PS_PRT3_SIZE 0x00000001u +#define CYREG_PRT3_PS_ALIAS 0x40005093u +#define CYDEV_IO_PS_PRT4_BASE 0x40005094u +#define CYDEV_IO_PS_PRT4_SIZE 0x00000001u +#define CYREG_PRT4_PS_ALIAS 0x40005094u +#define CYDEV_IO_PS_PRT5_BASE 0x40005095u +#define CYDEV_IO_PS_PRT5_SIZE 0x00000001u +#define CYREG_PRT5_PS_ALIAS 0x40005095u +#define CYDEV_IO_PS_PRT6_BASE 0x40005096u +#define CYDEV_IO_PS_PRT6_SIZE 0x00000001u +#define CYREG_PRT6_PS_ALIAS 0x40005096u +#define CYDEV_IO_PS_PRT12_BASE 0x4000509cu +#define CYDEV_IO_PS_PRT12_SIZE 0x00000001u +#define CYREG_PRT12_PS_ALIAS 0x4000509cu +#define CYDEV_IO_PS_PRT15_BASE 0x4000509fu +#define CYDEV_IO_PS_PRT15_SIZE 0x00000001u +#define CYREG_PRT15_PS15_ALIAS 0x4000509fu +#define CYDEV_IO_PRT_BASE 0x40005100u +#define CYDEV_IO_PRT_SIZE 0x00000100u +#define CYDEV_IO_PRT_PRT0_BASE 0x40005100u +#define CYDEV_IO_PRT_PRT0_SIZE 0x00000010u +#define CYREG_PRT0_DR 0x40005100u +#define CYREG_PRT0_PS 0x40005101u +#define CYREG_PRT0_DM0 0x40005102u +#define CYREG_PRT0_DM1 0x40005103u +#define CYREG_PRT0_DM2 0x40005104u +#define CYREG_PRT0_SLW 0x40005105u +#define CYREG_PRT0_BYP 0x40005106u +#define CYREG_PRT0_BIE 0x40005107u +#define CYREG_PRT0_INP_DIS 0x40005108u +#define CYREG_PRT0_CTL 0x40005109u +#define CYREG_PRT0_PRT 0x4000510au +#define CYREG_PRT0_BIT_MASK 0x4000510bu +#define CYREG_PRT0_AMUX 0x4000510cu +#define CYREG_PRT0_AG 0x4000510du +#define CYREG_PRT0_LCD_COM_SEG 0x4000510eu +#define CYREG_PRT0_LCD_EN 0x4000510fu +#define CYDEV_IO_PRT_PRT1_BASE 0x40005110u +#define CYDEV_IO_PRT_PRT1_SIZE 0x00000010u +#define CYREG_PRT1_DR 0x40005110u +#define CYREG_PRT1_PS 0x40005111u +#define CYREG_PRT1_DM0 0x40005112u +#define CYREG_PRT1_DM1 0x40005113u +#define CYREG_PRT1_DM2 0x40005114u +#define CYREG_PRT1_SLW 0x40005115u +#define CYREG_PRT1_BYP 0x40005116u +#define CYREG_PRT1_BIE 0x40005117u +#define CYREG_PRT1_INP_DIS 0x40005118u +#define CYREG_PRT1_CTL 0x40005119u +#define CYREG_PRT1_PRT 0x4000511au +#define CYREG_PRT1_BIT_MASK 0x4000511bu +#define CYREG_PRT1_AMUX 0x4000511cu +#define CYREG_PRT1_AG 0x4000511du +#define CYREG_PRT1_LCD_COM_SEG 0x4000511eu +#define CYREG_PRT1_LCD_EN 0x4000511fu +#define CYDEV_IO_PRT_PRT2_BASE 0x40005120u +#define CYDEV_IO_PRT_PRT2_SIZE 0x00000010u +#define CYREG_PRT2_DR 0x40005120u +#define CYREG_PRT2_PS 0x40005121u +#define CYREG_PRT2_DM0 0x40005122u +#define CYREG_PRT2_DM1 0x40005123u +#define CYREG_PRT2_DM2 0x40005124u +#define CYREG_PRT2_SLW 0x40005125u +#define CYREG_PRT2_BYP 0x40005126u +#define CYREG_PRT2_BIE 0x40005127u +#define CYREG_PRT2_INP_DIS 0x40005128u +#define CYREG_PRT2_CTL 0x40005129u +#define CYREG_PRT2_PRT 0x4000512au +#define CYREG_PRT2_BIT_MASK 0x4000512bu +#define CYREG_PRT2_AMUX 0x4000512cu +#define CYREG_PRT2_AG 0x4000512du +#define CYREG_PRT2_LCD_COM_SEG 0x4000512eu +#define CYREG_PRT2_LCD_EN 0x4000512fu +#define CYDEV_IO_PRT_PRT3_BASE 0x40005130u +#define CYDEV_IO_PRT_PRT3_SIZE 0x00000010u +#define CYREG_PRT3_DR 0x40005130u +#define CYREG_PRT3_PS 0x40005131u +#define CYREG_PRT3_DM0 0x40005132u +#define CYREG_PRT3_DM1 0x40005133u +#define CYREG_PRT3_DM2 0x40005134u +#define CYREG_PRT3_SLW 0x40005135u +#define CYREG_PRT3_BYP 0x40005136u +#define CYREG_PRT3_BIE 0x40005137u +#define CYREG_PRT3_INP_DIS 0x40005138u +#define CYREG_PRT3_CTL 0x40005139u +#define CYREG_PRT3_PRT 0x4000513au +#define CYREG_PRT3_BIT_MASK 0x4000513bu +#define CYREG_PRT3_AMUX 0x4000513cu +#define CYREG_PRT3_AG 0x4000513du +#define CYREG_PRT3_LCD_COM_SEG 0x4000513eu +#define CYREG_PRT3_LCD_EN 0x4000513fu +#define CYDEV_IO_PRT_PRT4_BASE 0x40005140u +#define CYDEV_IO_PRT_PRT4_SIZE 0x00000010u +#define CYREG_PRT4_DR 0x40005140u +#define CYREG_PRT4_PS 0x40005141u +#define CYREG_PRT4_DM0 0x40005142u +#define CYREG_PRT4_DM1 0x40005143u +#define CYREG_PRT4_DM2 0x40005144u +#define CYREG_PRT4_SLW 0x40005145u +#define CYREG_PRT4_BYP 0x40005146u +#define CYREG_PRT4_BIE 0x40005147u +#define CYREG_PRT4_INP_DIS 0x40005148u +#define CYREG_PRT4_CTL 0x40005149u +#define CYREG_PRT4_PRT 0x4000514au +#define CYREG_PRT4_BIT_MASK 0x4000514bu +#define CYREG_PRT4_AMUX 0x4000514cu +#define CYREG_PRT4_AG 0x4000514du +#define CYREG_PRT4_LCD_COM_SEG 0x4000514eu +#define CYREG_PRT4_LCD_EN 0x4000514fu +#define CYDEV_IO_PRT_PRT5_BASE 0x40005150u +#define CYDEV_IO_PRT_PRT5_SIZE 0x00000010u +#define CYREG_PRT5_DR 0x40005150u +#define CYREG_PRT5_PS 0x40005151u +#define CYREG_PRT5_DM0 0x40005152u +#define CYREG_PRT5_DM1 0x40005153u +#define CYREG_PRT5_DM2 0x40005154u +#define CYREG_PRT5_SLW 0x40005155u +#define CYREG_PRT5_BYP 0x40005156u +#define CYREG_PRT5_BIE 0x40005157u +#define CYREG_PRT5_INP_DIS 0x40005158u +#define CYREG_PRT5_CTL 0x40005159u +#define CYREG_PRT5_PRT 0x4000515au +#define CYREG_PRT5_BIT_MASK 0x4000515bu +#define CYREG_PRT5_AMUX 0x4000515cu +#define CYREG_PRT5_AG 0x4000515du +#define CYREG_PRT5_LCD_COM_SEG 0x4000515eu +#define CYREG_PRT5_LCD_EN 0x4000515fu +#define CYDEV_IO_PRT_PRT6_BASE 0x40005160u +#define CYDEV_IO_PRT_PRT6_SIZE 0x00000010u +#define CYREG_PRT6_DR 0x40005160u +#define CYREG_PRT6_PS 0x40005161u +#define CYREG_PRT6_DM0 0x40005162u +#define CYREG_PRT6_DM1 0x40005163u +#define CYREG_PRT6_DM2 0x40005164u +#define CYREG_PRT6_SLW 0x40005165u +#define CYREG_PRT6_BYP 0x40005166u +#define CYREG_PRT6_BIE 0x40005167u +#define CYREG_PRT6_INP_DIS 0x40005168u +#define CYREG_PRT6_CTL 0x40005169u +#define CYREG_PRT6_PRT 0x4000516au +#define CYREG_PRT6_BIT_MASK 0x4000516bu +#define CYREG_PRT6_AMUX 0x4000516cu +#define CYREG_PRT6_AG 0x4000516du +#define CYREG_PRT6_LCD_COM_SEG 0x4000516eu +#define CYREG_PRT6_LCD_EN 0x4000516fu +#define CYDEV_IO_PRT_PRT12_BASE 0x400051c0u +#define CYDEV_IO_PRT_PRT12_SIZE 0x00000010u +#define CYREG_PRT12_DR 0x400051c0u +#define CYREG_PRT12_PS 0x400051c1u +#define CYREG_PRT12_DM0 0x400051c2u +#define CYREG_PRT12_DM1 0x400051c3u +#define CYREG_PRT12_DM2 0x400051c4u +#define CYREG_PRT12_SLW 0x400051c5u +#define CYREG_PRT12_BYP 0x400051c6u +#define CYREG_PRT12_BIE 0x400051c7u +#define CYREG_PRT12_INP_DIS 0x400051c8u +#define CYREG_PRT12_SIO_HYST_EN 0x400051c9u +#define CYREG_PRT12_PRT 0x400051cau +#define CYREG_PRT12_BIT_MASK 0x400051cbu +#define CYREG_PRT12_SIO_REG_HIFREQ 0x400051ccu +#define CYREG_PRT12_AG 0x400051cdu +#define CYREG_PRT12_SIO_CFG 0x400051ceu +#define CYREG_PRT12_SIO_DIFF 0x400051cfu +#define CYDEV_IO_PRT_PRT15_BASE 0x400051f0u +#define CYDEV_IO_PRT_PRT15_SIZE 0x00000010u +#define CYREG_PRT15_DR 0x400051f0u +#define CYREG_PRT15_PS 0x400051f1u +#define CYREG_PRT15_DM0 0x400051f2u +#define CYREG_PRT15_DM1 0x400051f3u +#define CYREG_PRT15_DM2 0x400051f4u +#define CYREG_PRT15_SLW 0x400051f5u +#define CYREG_PRT15_BYP 0x400051f6u +#define CYREG_PRT15_BIE 0x400051f7u +#define CYREG_PRT15_INP_DIS 0x400051f8u +#define CYREG_PRT15_CTL 0x400051f9u +#define CYREG_PRT15_PRT 0x400051fau +#define CYREG_PRT15_BIT_MASK 0x400051fbu +#define CYREG_PRT15_AMUX 0x400051fcu +#define CYREG_PRT15_AG 0x400051fdu +#define CYREG_PRT15_LCD_COM_SEG 0x400051feu +#define CYREG_PRT15_LCD_EN 0x400051ffu +#define CYDEV_PRTDSI_BASE 0x40005200u +#define CYDEV_PRTDSI_SIZE 0x0000007fu +#define CYDEV_PRTDSI_PRT0_BASE 0x40005200u +#define CYDEV_PRTDSI_PRT0_SIZE 0x00000007u +#define CYREG_PRT0_OUT_SEL0 0x40005200u +#define CYREG_PRT0_OUT_SEL1 0x40005201u +#define CYREG_PRT0_OE_SEL0 0x40005202u +#define CYREG_PRT0_OE_SEL1 0x40005203u +#define CYREG_PRT0_DBL_SYNC_IN 0x40005204u +#define CYREG_PRT0_SYNC_OUT 0x40005205u +#define CYREG_PRT0_CAPS_SEL 0x40005206u +#define CYDEV_PRTDSI_PRT1_BASE 0x40005208u +#define CYDEV_PRTDSI_PRT1_SIZE 0x00000007u +#define CYREG_PRT1_OUT_SEL0 0x40005208u +#define CYREG_PRT1_OUT_SEL1 0x40005209u +#define CYREG_PRT1_OE_SEL0 0x4000520au +#define CYREG_PRT1_OE_SEL1 0x4000520bu +#define CYREG_PRT1_DBL_SYNC_IN 0x4000520cu +#define CYREG_PRT1_SYNC_OUT 0x4000520du +#define CYREG_PRT1_CAPS_SEL 0x4000520eu +#define CYDEV_PRTDSI_PRT2_BASE 0x40005210u +#define CYDEV_PRTDSI_PRT2_SIZE 0x00000007u +#define CYREG_PRT2_OUT_SEL0 0x40005210u +#define CYREG_PRT2_OUT_SEL1 0x40005211u +#define CYREG_PRT2_OE_SEL0 0x40005212u +#define CYREG_PRT2_OE_SEL1 0x40005213u +#define CYREG_PRT2_DBL_SYNC_IN 0x40005214u +#define CYREG_PRT2_SYNC_OUT 0x40005215u +#define CYREG_PRT2_CAPS_SEL 0x40005216u +#define CYDEV_PRTDSI_PRT3_BASE 0x40005218u +#define CYDEV_PRTDSI_PRT3_SIZE 0x00000007u +#define CYREG_PRT3_OUT_SEL0 0x40005218u +#define CYREG_PRT3_OUT_SEL1 0x40005219u +#define CYREG_PRT3_OE_SEL0 0x4000521au +#define CYREG_PRT3_OE_SEL1 0x4000521bu +#define CYREG_PRT3_DBL_SYNC_IN 0x4000521cu +#define CYREG_PRT3_SYNC_OUT 0x4000521du +#define CYREG_PRT3_CAPS_SEL 0x4000521eu +#define CYDEV_PRTDSI_PRT4_BASE 0x40005220u +#define CYDEV_PRTDSI_PRT4_SIZE 0x00000007u +#define CYREG_PRT4_OUT_SEL0 0x40005220u +#define CYREG_PRT4_OUT_SEL1 0x40005221u +#define CYREG_PRT4_OE_SEL0 0x40005222u +#define CYREG_PRT4_OE_SEL1 0x40005223u +#define CYREG_PRT4_DBL_SYNC_IN 0x40005224u +#define CYREG_PRT4_SYNC_OUT 0x40005225u +#define CYREG_PRT4_CAPS_SEL 0x40005226u +#define CYDEV_PRTDSI_PRT5_BASE 0x40005228u +#define CYDEV_PRTDSI_PRT5_SIZE 0x00000007u +#define CYREG_PRT5_OUT_SEL0 0x40005228u +#define CYREG_PRT5_OUT_SEL1 0x40005229u +#define CYREG_PRT5_OE_SEL0 0x4000522au +#define CYREG_PRT5_OE_SEL1 0x4000522bu +#define CYREG_PRT5_DBL_SYNC_IN 0x4000522cu +#define CYREG_PRT5_SYNC_OUT 0x4000522du +#define CYREG_PRT5_CAPS_SEL 0x4000522eu +#define CYDEV_PRTDSI_PRT6_BASE 0x40005230u +#define CYDEV_PRTDSI_PRT6_SIZE 0x00000007u +#define CYREG_PRT6_OUT_SEL0 0x40005230u +#define CYREG_PRT6_OUT_SEL1 0x40005231u +#define CYREG_PRT6_OE_SEL0 0x40005232u +#define CYREG_PRT6_OE_SEL1 0x40005233u +#define CYREG_PRT6_DBL_SYNC_IN 0x40005234u +#define CYREG_PRT6_SYNC_OUT 0x40005235u +#define CYREG_PRT6_CAPS_SEL 0x40005236u +#define CYDEV_PRTDSI_PRT12_BASE 0x40005260u +#define CYDEV_PRTDSI_PRT12_SIZE 0x00000006u +#define CYREG_PRT12_OUT_SEL0 0x40005260u +#define CYREG_PRT12_OUT_SEL1 0x40005261u +#define CYREG_PRT12_OE_SEL0 0x40005262u +#define CYREG_PRT12_OE_SEL1 0x40005263u +#define CYREG_PRT12_DBL_SYNC_IN 0x40005264u +#define CYREG_PRT12_SYNC_OUT 0x40005265u +#define CYDEV_PRTDSI_PRT15_BASE 0x40005278u +#define CYDEV_PRTDSI_PRT15_SIZE 0x00000007u +#define CYREG_PRT15_OUT_SEL0 0x40005278u +#define CYREG_PRT15_OUT_SEL1 0x40005279u +#define CYREG_PRT15_OE_SEL0 0x4000527au +#define CYREG_PRT15_OE_SEL1 0x4000527bu +#define CYREG_PRT15_DBL_SYNC_IN 0x4000527cu +#define CYREG_PRT15_SYNC_OUT 0x4000527du +#define CYREG_PRT15_CAPS_SEL 0x4000527eu +#define CYDEV_EMIF_BASE 0x40005400u +#define CYDEV_EMIF_SIZE 0x00000007u +#define CYREG_EMIF_NO_UDB 0x40005400u +#define CYREG_EMIF_RP_WAIT_STATES 0x40005401u +#define CYREG_EMIF_MEM_DWN 0x40005402u +#define CYREG_EMIF_MEMCLK_DIV 0x40005403u +#define CYREG_EMIF_CLOCK_EN 0x40005404u +#define CYREG_EMIF_EM_TYPE 0x40005405u +#define CYREG_EMIF_WP_WAIT_STATES 0x40005406u +#define CYDEV_ANAIF_BASE 0x40005800u +#define CYDEV_ANAIF_SIZE 0x000003a9u +#define CYDEV_ANAIF_CFG_BASE 0x40005800u +#define CYDEV_ANAIF_CFG_SIZE 0x0000010fu +#define CYDEV_ANAIF_CFG_SC0_BASE 0x40005800u +#define CYDEV_ANAIF_CFG_SC0_SIZE 0x00000003u +#define CYREG_SC0_CR0 0x40005800u +#define CYREG_SC0_CR1 0x40005801u +#define CYREG_SC0_CR2 0x40005802u +#define CYDEV_ANAIF_CFG_SC1_BASE 0x40005804u +#define CYDEV_ANAIF_CFG_SC1_SIZE 0x00000003u +#define CYREG_SC1_CR0 0x40005804u +#define CYREG_SC1_CR1 0x40005805u +#define CYREG_SC1_CR2 0x40005806u +#define CYDEV_ANAIF_CFG_SC2_BASE 0x40005808u +#define CYDEV_ANAIF_CFG_SC2_SIZE 0x00000003u +#define CYREG_SC2_CR0 0x40005808u +#define CYREG_SC2_CR1 0x40005809u +#define CYREG_SC2_CR2 0x4000580au +#define CYDEV_ANAIF_CFG_SC3_BASE 0x4000580cu +#define CYDEV_ANAIF_CFG_SC3_SIZE 0x00000003u +#define CYREG_SC3_CR0 0x4000580cu +#define CYREG_SC3_CR1 0x4000580du +#define CYREG_SC3_CR2 0x4000580eu +#define CYDEV_ANAIF_CFG_DAC0_BASE 0x40005820u +#define CYDEV_ANAIF_CFG_DAC0_SIZE 0x00000003u +#define CYREG_DAC0_CR0 0x40005820u +#define CYREG_DAC0_CR1 0x40005821u +#define CYREG_DAC0_TST 0x40005822u +#define CYDEV_ANAIF_CFG_DAC1_BASE 0x40005824u +#define CYDEV_ANAIF_CFG_DAC1_SIZE 0x00000003u +#define CYREG_DAC1_CR0 0x40005824u +#define CYREG_DAC1_CR1 0x40005825u +#define CYREG_DAC1_TST 0x40005826u +#define CYDEV_ANAIF_CFG_DAC2_BASE 0x40005828u +#define CYDEV_ANAIF_CFG_DAC2_SIZE 0x00000003u +#define CYREG_DAC2_CR0 0x40005828u +#define CYREG_DAC2_CR1 0x40005829u +#define CYREG_DAC2_TST 0x4000582au +#define CYDEV_ANAIF_CFG_DAC3_BASE 0x4000582cu +#define CYDEV_ANAIF_CFG_DAC3_SIZE 0x00000003u +#define CYREG_DAC3_CR0 0x4000582cu +#define CYREG_DAC3_CR1 0x4000582du +#define CYREG_DAC3_TST 0x4000582eu +#define CYDEV_ANAIF_CFG_CMP0_BASE 0x40005840u +#define CYDEV_ANAIF_CFG_CMP0_SIZE 0x00000001u +#define CYREG_CMP0_CR 0x40005840u +#define CYDEV_ANAIF_CFG_CMP1_BASE 0x40005841u +#define CYDEV_ANAIF_CFG_CMP1_SIZE 0x00000001u +#define CYREG_CMP1_CR 0x40005841u +#define CYDEV_ANAIF_CFG_CMP2_BASE 0x40005842u +#define CYDEV_ANAIF_CFG_CMP2_SIZE 0x00000001u +#define CYREG_CMP2_CR 0x40005842u +#define CYDEV_ANAIF_CFG_CMP3_BASE 0x40005843u +#define CYDEV_ANAIF_CFG_CMP3_SIZE 0x00000001u +#define CYREG_CMP3_CR 0x40005843u +#define CYDEV_ANAIF_CFG_LUT0_BASE 0x40005848u +#define CYDEV_ANAIF_CFG_LUT0_SIZE 0x00000002u +#define CYREG_LUT0_CR 0x40005848u +#define CYREG_LUT0_MX 0x40005849u +#define CYDEV_ANAIF_CFG_LUT1_BASE 0x4000584au +#define CYDEV_ANAIF_CFG_LUT1_SIZE 0x00000002u +#define CYREG_LUT1_CR 0x4000584au +#define CYREG_LUT1_MX 0x4000584bu +#define CYDEV_ANAIF_CFG_LUT2_BASE 0x4000584cu +#define CYDEV_ANAIF_CFG_LUT2_SIZE 0x00000002u +#define CYREG_LUT2_CR 0x4000584cu +#define CYREG_LUT2_MX 0x4000584du +#define CYDEV_ANAIF_CFG_LUT3_BASE 0x4000584eu +#define CYDEV_ANAIF_CFG_LUT3_SIZE 0x00000002u +#define CYREG_LUT3_CR 0x4000584eu +#define CYREG_LUT3_MX 0x4000584fu +#define CYDEV_ANAIF_CFG_OPAMP0_BASE 0x40005858u +#define CYDEV_ANAIF_CFG_OPAMP0_SIZE 0x00000002u +#define CYREG_OPAMP0_CR 0x40005858u +#define CYREG_OPAMP0_RSVD 0x40005859u +#define CYDEV_ANAIF_CFG_OPAMP1_BASE 0x4000585au +#define CYDEV_ANAIF_CFG_OPAMP1_SIZE 0x00000002u +#define CYREG_OPAMP1_CR 0x4000585au +#define CYREG_OPAMP1_RSVD 0x4000585bu +#define CYDEV_ANAIF_CFG_OPAMP2_BASE 0x4000585cu +#define CYDEV_ANAIF_CFG_OPAMP2_SIZE 0x00000002u +#define CYREG_OPAMP2_CR 0x4000585cu +#define CYREG_OPAMP2_RSVD 0x4000585du +#define CYDEV_ANAIF_CFG_OPAMP3_BASE 0x4000585eu +#define CYDEV_ANAIF_CFG_OPAMP3_SIZE 0x00000002u +#define CYREG_OPAMP3_CR 0x4000585eu +#define CYREG_OPAMP3_RSVD 0x4000585fu +#define CYDEV_ANAIF_CFG_LCDDAC_BASE 0x40005868u +#define CYDEV_ANAIF_CFG_LCDDAC_SIZE 0x00000002u +#define CYREG_LCDDAC_CR0 0x40005868u +#define CYREG_LCDDAC_CR1 0x40005869u +#define CYDEV_ANAIF_CFG_LCDDRV_BASE 0x4000586au +#define CYDEV_ANAIF_CFG_LCDDRV_SIZE 0x00000001u +#define CYREG_LCDDRV_CR 0x4000586au +#define CYDEV_ANAIF_CFG_LCDTMR_BASE 0x4000586bu +#define CYDEV_ANAIF_CFG_LCDTMR_SIZE 0x00000001u +#define CYREG_LCDTMR_CFG 0x4000586bu +#define CYDEV_ANAIF_CFG_BG_BASE 0x4000586cu +#define CYDEV_ANAIF_CFG_BG_SIZE 0x00000004u +#define CYREG_BG_CR0 0x4000586cu +#define CYREG_BG_RSVD 0x4000586du +#define CYREG_BG_DFT0 0x4000586eu +#define CYREG_BG_DFT1 0x4000586fu +#define CYDEV_ANAIF_CFG_CAPSL_BASE 0x40005870u +#define CYDEV_ANAIF_CFG_CAPSL_SIZE 0x00000002u +#define CYREG_CAPSL_CFG0 0x40005870u +#define CYREG_CAPSL_CFG1 0x40005871u +#define CYDEV_ANAIF_CFG_CAPSR_BASE 0x40005872u +#define CYDEV_ANAIF_CFG_CAPSR_SIZE 0x00000002u +#define CYREG_CAPSR_CFG0 0x40005872u +#define CYREG_CAPSR_CFG1 0x40005873u +#define CYDEV_ANAIF_CFG_PUMP_BASE 0x40005876u +#define CYDEV_ANAIF_CFG_PUMP_SIZE 0x00000002u +#define CYREG_PUMP_CR0 0x40005876u +#define CYREG_PUMP_CR1 0x40005877u +#define CYDEV_ANAIF_CFG_LPF0_BASE 0x40005878u +#define CYDEV_ANAIF_CFG_LPF0_SIZE 0x00000002u +#define CYREG_LPF0_CR0 0x40005878u +#define CYREG_LPF0_RSVD 0x40005879u +#define CYDEV_ANAIF_CFG_LPF1_BASE 0x4000587au +#define CYDEV_ANAIF_CFG_LPF1_SIZE 0x00000002u +#define CYREG_LPF1_CR0 0x4000587au +#define CYREG_LPF1_RSVD 0x4000587bu +#define CYDEV_ANAIF_CFG_MISC_BASE 0x4000587cu +#define CYDEV_ANAIF_CFG_MISC_SIZE 0x00000001u +#define CYREG_ANAIF_CFG_MISC_CR0 0x4000587cu +#define CYDEV_ANAIF_CFG_DSM0_BASE 0x40005880u +#define CYDEV_ANAIF_CFG_DSM0_SIZE 0x00000020u +#define CYREG_DSM0_CR0 0x40005880u +#define CYREG_DSM0_CR1 0x40005881u +#define CYREG_DSM0_CR2 0x40005882u +#define CYREG_DSM0_CR3 0x40005883u +#define CYREG_DSM0_CR4 0x40005884u +#define CYREG_DSM0_CR5 0x40005885u +#define CYREG_DSM0_CR6 0x40005886u +#define CYREG_DSM0_CR7 0x40005887u +#define CYREG_DSM0_CR8 0x40005888u +#define CYREG_DSM0_CR9 0x40005889u +#define CYREG_DSM0_CR10 0x4000588au +#define CYREG_DSM0_CR11 0x4000588bu +#define CYREG_DSM0_CR12 0x4000588cu +#define CYREG_DSM0_CR13 0x4000588du +#define CYREG_DSM0_CR14 0x4000588eu +#define CYREG_DSM0_CR15 0x4000588fu +#define CYREG_DSM0_CR16 0x40005890u +#define CYREG_DSM0_CR17 0x40005891u +#define CYREG_DSM0_REF0 0x40005892u +#define CYREG_DSM0_REF1 0x40005893u +#define CYREG_DSM0_REF2 0x40005894u +#define CYREG_DSM0_REF3 0x40005895u +#define CYREG_DSM0_DEM0 0x40005896u +#define CYREG_DSM0_DEM1 0x40005897u +#define CYREG_DSM0_TST0 0x40005898u +#define CYREG_DSM0_TST1 0x40005899u +#define CYREG_DSM0_BUF0 0x4000589au +#define CYREG_DSM0_BUF1 0x4000589bu +#define CYREG_DSM0_BUF2 0x4000589cu +#define CYREG_DSM0_BUF3 0x4000589du +#define CYREG_DSM0_MISC 0x4000589eu +#define CYREG_DSM0_RSVD1 0x4000589fu +#define CYDEV_ANAIF_CFG_SAR0_BASE 0x40005900u +#define CYDEV_ANAIF_CFG_SAR0_SIZE 0x00000007u +#define CYREG_SAR0_CSR0 0x40005900u +#define CYREG_SAR0_CSR1 0x40005901u +#define CYREG_SAR0_CSR2 0x40005902u +#define CYREG_SAR0_CSR3 0x40005903u +#define CYREG_SAR0_CSR4 0x40005904u +#define CYREG_SAR0_CSR5 0x40005905u +#define CYREG_SAR0_CSR6 0x40005906u +#define CYDEV_ANAIF_CFG_SAR1_BASE 0x40005908u +#define CYDEV_ANAIF_CFG_SAR1_SIZE 0x00000007u +#define CYREG_SAR1_CSR0 0x40005908u +#define CYREG_SAR1_CSR1 0x40005909u +#define CYREG_SAR1_CSR2 0x4000590au +#define CYREG_SAR1_CSR3 0x4000590bu +#define CYREG_SAR1_CSR4 0x4000590cu +#define CYREG_SAR1_CSR5 0x4000590du +#define CYREG_SAR1_CSR6 0x4000590eu +#define CYDEV_ANAIF_RT_BASE 0x40005a00u +#define CYDEV_ANAIF_RT_SIZE 0x00000162u +#define CYDEV_ANAIF_RT_SC0_BASE 0x40005a00u +#define CYDEV_ANAIF_RT_SC0_SIZE 0x0000000du +#define CYREG_SC0_SW0 0x40005a00u +#define CYREG_SC0_SW2 0x40005a02u +#define CYREG_SC0_SW3 0x40005a03u +#define CYREG_SC0_SW4 0x40005a04u +#define CYREG_SC0_SW6 0x40005a06u +#define CYREG_SC0_SW7 0x40005a07u +#define CYREG_SC0_SW8 0x40005a08u +#define CYREG_SC0_SW10 0x40005a0au +#define CYREG_SC0_CLK 0x40005a0bu +#define CYREG_SC0_BST 0x40005a0cu +#define CYDEV_ANAIF_RT_SC1_BASE 0x40005a10u +#define CYDEV_ANAIF_RT_SC1_SIZE 0x0000000du +#define CYREG_SC1_SW0 0x40005a10u +#define CYREG_SC1_SW2 0x40005a12u +#define CYREG_SC1_SW3 0x40005a13u +#define CYREG_SC1_SW4 0x40005a14u +#define CYREG_SC1_SW6 0x40005a16u +#define CYREG_SC1_SW7 0x40005a17u +#define CYREG_SC1_SW8 0x40005a18u +#define CYREG_SC1_SW10 0x40005a1au +#define CYREG_SC1_CLK 0x40005a1bu +#define CYREG_SC1_BST 0x40005a1cu +#define CYDEV_ANAIF_RT_SC2_BASE 0x40005a20u +#define CYDEV_ANAIF_RT_SC2_SIZE 0x0000000du +#define CYREG_SC2_SW0 0x40005a20u +#define CYREG_SC2_SW2 0x40005a22u +#define CYREG_SC2_SW3 0x40005a23u +#define CYREG_SC2_SW4 0x40005a24u +#define CYREG_SC2_SW6 0x40005a26u +#define CYREG_SC2_SW7 0x40005a27u +#define CYREG_SC2_SW8 0x40005a28u +#define CYREG_SC2_SW10 0x40005a2au +#define CYREG_SC2_CLK 0x40005a2bu +#define CYREG_SC2_BST 0x40005a2cu +#define CYDEV_ANAIF_RT_SC3_BASE 0x40005a30u +#define CYDEV_ANAIF_RT_SC3_SIZE 0x0000000du +#define CYREG_SC3_SW0 0x40005a30u +#define CYREG_SC3_SW2 0x40005a32u +#define CYREG_SC3_SW3 0x40005a33u +#define CYREG_SC3_SW4 0x40005a34u +#define CYREG_SC3_SW6 0x40005a36u +#define CYREG_SC3_SW7 0x40005a37u +#define CYREG_SC3_SW8 0x40005a38u +#define CYREG_SC3_SW10 0x40005a3au +#define CYREG_SC3_CLK 0x40005a3bu +#define CYREG_SC3_BST 0x40005a3cu +#define CYDEV_ANAIF_RT_DAC0_BASE 0x40005a80u +#define CYDEV_ANAIF_RT_DAC0_SIZE 0x00000008u +#define CYREG_DAC0_SW0 0x40005a80u +#define CYREG_DAC0_SW2 0x40005a82u +#define CYREG_DAC0_SW3 0x40005a83u +#define CYREG_DAC0_SW4 0x40005a84u +#define CYREG_DAC0_STROBE 0x40005a87u +#define CYDEV_ANAIF_RT_DAC1_BASE 0x40005a88u +#define CYDEV_ANAIF_RT_DAC1_SIZE 0x00000008u +#define CYREG_DAC1_SW0 0x40005a88u +#define CYREG_DAC1_SW2 0x40005a8au +#define CYREG_DAC1_SW3 0x40005a8bu +#define CYREG_DAC1_SW4 0x40005a8cu +#define CYREG_DAC1_STROBE 0x40005a8fu +#define CYDEV_ANAIF_RT_DAC2_BASE 0x40005a90u +#define CYDEV_ANAIF_RT_DAC2_SIZE 0x00000008u +#define CYREG_DAC2_SW0 0x40005a90u +#define CYREG_DAC2_SW2 0x40005a92u +#define CYREG_DAC2_SW3 0x40005a93u +#define CYREG_DAC2_SW4 0x40005a94u +#define CYREG_DAC2_STROBE 0x40005a97u +#define CYDEV_ANAIF_RT_DAC3_BASE 0x40005a98u +#define CYDEV_ANAIF_RT_DAC3_SIZE 0x00000008u +#define CYREG_DAC3_SW0 0x40005a98u +#define CYREG_DAC3_SW2 0x40005a9au +#define CYREG_DAC3_SW3 0x40005a9bu +#define CYREG_DAC3_SW4 0x40005a9cu +#define CYREG_DAC3_STROBE 0x40005a9fu +#define CYDEV_ANAIF_RT_CMP0_BASE 0x40005ac0u +#define CYDEV_ANAIF_RT_CMP0_SIZE 0x00000008u +#define CYREG_CMP0_SW0 0x40005ac0u +#define CYREG_CMP0_SW2 0x40005ac2u +#define CYREG_CMP0_SW3 0x40005ac3u +#define CYREG_CMP0_SW4 0x40005ac4u +#define CYREG_CMP0_SW6 0x40005ac6u +#define CYREG_CMP0_CLK 0x40005ac7u +#define CYDEV_ANAIF_RT_CMP1_BASE 0x40005ac8u +#define CYDEV_ANAIF_RT_CMP1_SIZE 0x00000008u +#define CYREG_CMP1_SW0 0x40005ac8u +#define CYREG_CMP1_SW2 0x40005acau +#define CYREG_CMP1_SW3 0x40005acbu +#define CYREG_CMP1_SW4 0x40005accu +#define CYREG_CMP1_SW6 0x40005aceu +#define CYREG_CMP1_CLK 0x40005acfu +#define CYDEV_ANAIF_RT_CMP2_BASE 0x40005ad0u +#define CYDEV_ANAIF_RT_CMP2_SIZE 0x00000008u +#define CYREG_CMP2_SW0 0x40005ad0u +#define CYREG_CMP2_SW2 0x40005ad2u +#define CYREG_CMP2_SW3 0x40005ad3u +#define CYREG_CMP2_SW4 0x40005ad4u +#define CYREG_CMP2_SW6 0x40005ad6u +#define CYREG_CMP2_CLK 0x40005ad7u +#define CYDEV_ANAIF_RT_CMP3_BASE 0x40005ad8u +#define CYDEV_ANAIF_RT_CMP3_SIZE 0x00000008u +#define CYREG_CMP3_SW0 0x40005ad8u +#define CYREG_CMP3_SW2 0x40005adau +#define CYREG_CMP3_SW3 0x40005adbu +#define CYREG_CMP3_SW4 0x40005adcu +#define CYREG_CMP3_SW6 0x40005adeu +#define CYREG_CMP3_CLK 0x40005adfu +#define CYDEV_ANAIF_RT_DSM0_BASE 0x40005b00u +#define CYDEV_ANAIF_RT_DSM0_SIZE 0x00000008u +#define CYREG_DSM0_SW0 0x40005b00u +#define CYREG_DSM0_SW2 0x40005b02u +#define CYREG_DSM0_SW3 0x40005b03u +#define CYREG_DSM0_SW4 0x40005b04u +#define CYREG_DSM0_SW6 0x40005b06u +#define CYREG_DSM0_CLK 0x40005b07u +#define CYDEV_ANAIF_RT_SAR0_BASE 0x40005b20u +#define CYDEV_ANAIF_RT_SAR0_SIZE 0x00000008u +#define CYREG_SAR0_SW0 0x40005b20u +#define CYREG_SAR0_SW2 0x40005b22u +#define CYREG_SAR0_SW3 0x40005b23u +#define CYREG_SAR0_SW4 0x40005b24u +#define CYREG_SAR0_SW6 0x40005b26u +#define CYREG_SAR0_CLK 0x40005b27u +#define CYDEV_ANAIF_RT_SAR1_BASE 0x40005b28u +#define CYDEV_ANAIF_RT_SAR1_SIZE 0x00000008u +#define CYREG_SAR1_SW0 0x40005b28u +#define CYREG_SAR1_SW2 0x40005b2au +#define CYREG_SAR1_SW3 0x40005b2bu +#define CYREG_SAR1_SW4 0x40005b2cu +#define CYREG_SAR1_SW6 0x40005b2eu +#define CYREG_SAR1_CLK 0x40005b2fu +#define CYDEV_ANAIF_RT_OPAMP0_BASE 0x40005b40u +#define CYDEV_ANAIF_RT_OPAMP0_SIZE 0x00000002u +#define CYREG_OPAMP0_MX 0x40005b40u +#define CYREG_OPAMP0_SW 0x40005b41u +#define CYDEV_ANAIF_RT_OPAMP1_BASE 0x40005b42u +#define CYDEV_ANAIF_RT_OPAMP1_SIZE 0x00000002u +#define CYREG_OPAMP1_MX 0x40005b42u +#define CYREG_OPAMP1_SW 0x40005b43u +#define CYDEV_ANAIF_RT_OPAMP2_BASE 0x40005b44u +#define CYDEV_ANAIF_RT_OPAMP2_SIZE 0x00000002u +#define CYREG_OPAMP2_MX 0x40005b44u +#define CYREG_OPAMP2_SW 0x40005b45u +#define CYDEV_ANAIF_RT_OPAMP3_BASE 0x40005b46u +#define CYDEV_ANAIF_RT_OPAMP3_SIZE 0x00000002u +#define CYREG_OPAMP3_MX 0x40005b46u +#define CYREG_OPAMP3_SW 0x40005b47u +#define CYDEV_ANAIF_RT_LCDDAC_BASE 0x40005b50u +#define CYDEV_ANAIF_RT_LCDDAC_SIZE 0x00000005u +#define CYREG_LCDDAC_SW0 0x40005b50u +#define CYREG_LCDDAC_SW1 0x40005b51u +#define CYREG_LCDDAC_SW2 0x40005b52u +#define CYREG_LCDDAC_SW3 0x40005b53u +#define CYREG_LCDDAC_SW4 0x40005b54u +#define CYDEV_ANAIF_RT_SC_BASE 0x40005b56u +#define CYDEV_ANAIF_RT_SC_SIZE 0x00000001u +#define CYREG_SC_MISC 0x40005b56u +#define CYDEV_ANAIF_RT_BUS_BASE 0x40005b58u +#define CYDEV_ANAIF_RT_BUS_SIZE 0x00000004u +#define CYREG_BUS_SW0 0x40005b58u +#define CYREG_BUS_SW2 0x40005b5au +#define CYREG_BUS_SW3 0x40005b5bu +#define CYDEV_ANAIF_RT_DFT_BASE 0x40005b5cu +#define CYDEV_ANAIF_RT_DFT_SIZE 0x00000006u +#define CYREG_DFT_CR0 0x40005b5cu +#define CYREG_DFT_CR1 0x40005b5du +#define CYREG_DFT_CR2 0x40005b5eu +#define CYREG_DFT_CR3 0x40005b5fu +#define CYREG_DFT_CR4 0x40005b60u +#define CYREG_DFT_CR5 0x40005b61u +#define CYDEV_ANAIF_WRK_BASE 0x40005b80u +#define CYDEV_ANAIF_WRK_SIZE 0x00000029u +#define CYDEV_ANAIF_WRK_DAC0_BASE 0x40005b80u +#define CYDEV_ANAIF_WRK_DAC0_SIZE 0x00000001u +#define CYREG_DAC0_D 0x40005b80u +#define CYDEV_ANAIF_WRK_DAC1_BASE 0x40005b81u +#define CYDEV_ANAIF_WRK_DAC1_SIZE 0x00000001u +#define CYREG_DAC1_D 0x40005b81u +#define CYDEV_ANAIF_WRK_DAC2_BASE 0x40005b82u +#define CYDEV_ANAIF_WRK_DAC2_SIZE 0x00000001u +#define CYREG_DAC2_D 0x40005b82u +#define CYDEV_ANAIF_WRK_DAC3_BASE 0x40005b83u +#define CYDEV_ANAIF_WRK_DAC3_SIZE 0x00000001u +#define CYREG_DAC3_D 0x40005b83u +#define CYDEV_ANAIF_WRK_DSM0_BASE 0x40005b88u +#define CYDEV_ANAIF_WRK_DSM0_SIZE 0x00000002u +#define CYREG_DSM0_OUT0 0x40005b88u +#define CYREG_DSM0_OUT1 0x40005b89u +#define CYDEV_ANAIF_WRK_LUT_BASE 0x40005b90u +#define CYDEV_ANAIF_WRK_LUT_SIZE 0x00000005u +#define CYREG_LUT_SR 0x40005b90u +#define CYREG_LUT_WRK1 0x40005b91u +#define CYREG_LUT_MSK 0x40005b92u +#define CYREG_LUT_CLK 0x40005b93u +#define CYREG_LUT_CPTR 0x40005b94u +#define CYDEV_ANAIF_WRK_CMP_BASE 0x40005b96u +#define CYDEV_ANAIF_WRK_CMP_SIZE 0x00000002u +#define CYREG_CMP_WRK 0x40005b96u +#define CYREG_CMP_TST 0x40005b97u +#define CYDEV_ANAIF_WRK_SC_BASE 0x40005b98u +#define CYDEV_ANAIF_WRK_SC_SIZE 0x00000005u +#define CYREG_SC_SR 0x40005b98u +#define CYREG_SC_WRK1 0x40005b99u +#define CYREG_SC_MSK 0x40005b9au +#define CYREG_SC_CMPINV 0x40005b9bu +#define CYREG_SC_CPTR 0x40005b9cu +#define CYDEV_ANAIF_WRK_SAR0_BASE 0x40005ba0u +#define CYDEV_ANAIF_WRK_SAR0_SIZE 0x00000002u +#define CYREG_SAR0_WRK0 0x40005ba0u +#define CYREG_SAR0_WRK1 0x40005ba1u +#define CYDEV_ANAIF_WRK_SAR1_BASE 0x40005ba2u +#define CYDEV_ANAIF_WRK_SAR1_SIZE 0x00000002u +#define CYREG_SAR1_WRK0 0x40005ba2u +#define CYREG_SAR1_WRK1 0x40005ba3u +#define CYDEV_ANAIF_WRK_SARS_BASE 0x40005ba8u +#define CYDEV_ANAIF_WRK_SARS_SIZE 0x00000001u +#define CYREG_ANAIF_WRK_SARS_SOF 0x40005ba8u +#define CYDEV_USB_BASE 0x40006000u +#define CYDEV_USB_SIZE 0x00000300u +#define CYREG_USB_EP0_DR0 0x40006000u +#define CYREG_USB_EP0_DR1 0x40006001u +#define CYREG_USB_EP0_DR2 0x40006002u +#define CYREG_USB_EP0_DR3 0x40006003u +#define CYREG_USB_EP0_DR4 0x40006004u +#define CYREG_USB_EP0_DR5 0x40006005u +#define CYREG_USB_EP0_DR6 0x40006006u +#define CYREG_USB_EP0_DR7 0x40006007u +#define CYREG_USB_CR0 0x40006008u +#define CYREG_USB_CR1 0x40006009u +#define CYREG_USB_SIE_EP_INT_EN 0x4000600au +#define CYREG_USB_SIE_EP_INT_SR 0x4000600bu +#define CYDEV_USB_SIE_EP1_BASE 0x4000600cu +#define CYDEV_USB_SIE_EP1_SIZE 0x00000003u +#define CYREG_USB_SIE_EP1_CNT0 0x4000600cu +#define CYREG_USB_SIE_EP1_CNT1 0x4000600du +#define CYREG_USB_SIE_EP1_CR0 0x4000600eu +#define CYREG_USB_USBIO_CR0 0x40006010u +#define CYREG_USB_USBIO_CR1 0x40006012u +#define CYREG_USB_DYN_RECONFIG 0x40006014u +#define CYREG_USB_SOF0 0x40006018u +#define CYREG_USB_SOF1 0x40006019u +#define CYDEV_USB_SIE_EP2_BASE 0x4000601cu +#define CYDEV_USB_SIE_EP2_SIZE 0x00000003u +#define CYREG_USB_SIE_EP2_CNT0 0x4000601cu +#define CYREG_USB_SIE_EP2_CNT1 0x4000601du +#define CYREG_USB_SIE_EP2_CR0 0x4000601eu +#define CYREG_USB_EP0_CR 0x40006028u +#define CYREG_USB_EP0_CNT 0x40006029u +#define CYDEV_USB_SIE_EP3_BASE 0x4000602cu +#define CYDEV_USB_SIE_EP3_SIZE 0x00000003u +#define CYREG_USB_SIE_EP3_CNT0 0x4000602cu +#define CYREG_USB_SIE_EP3_CNT1 0x4000602du +#define CYREG_USB_SIE_EP3_CR0 0x4000602eu +#define CYDEV_USB_SIE_EP4_BASE 0x4000603cu +#define CYDEV_USB_SIE_EP4_SIZE 0x00000003u +#define CYREG_USB_SIE_EP4_CNT0 0x4000603cu +#define CYREG_USB_SIE_EP4_CNT1 0x4000603du +#define CYREG_USB_SIE_EP4_CR0 0x4000603eu +#define CYDEV_USB_SIE_EP5_BASE 0x4000604cu +#define CYDEV_USB_SIE_EP5_SIZE 0x00000003u +#define CYREG_USB_SIE_EP5_CNT0 0x4000604cu +#define CYREG_USB_SIE_EP5_CNT1 0x4000604du +#define CYREG_USB_SIE_EP5_CR0 0x4000604eu +#define CYDEV_USB_SIE_EP6_BASE 0x4000605cu +#define CYDEV_USB_SIE_EP6_SIZE 0x00000003u +#define CYREG_USB_SIE_EP6_CNT0 0x4000605cu +#define CYREG_USB_SIE_EP6_CNT1 0x4000605du +#define CYREG_USB_SIE_EP6_CR0 0x4000605eu +#define CYDEV_USB_SIE_EP7_BASE 0x4000606cu +#define CYDEV_USB_SIE_EP7_SIZE 0x00000003u +#define CYREG_USB_SIE_EP7_CNT0 0x4000606cu +#define CYREG_USB_SIE_EP7_CNT1 0x4000606du +#define CYREG_USB_SIE_EP7_CR0 0x4000606eu +#define CYDEV_USB_SIE_EP8_BASE 0x4000607cu +#define CYDEV_USB_SIE_EP8_SIZE 0x00000003u +#define CYREG_USB_SIE_EP8_CNT0 0x4000607cu +#define CYREG_USB_SIE_EP8_CNT1 0x4000607du +#define CYREG_USB_SIE_EP8_CR0 0x4000607eu +#define CYDEV_USB_ARB_EP1_BASE 0x40006080u +#define CYDEV_USB_ARB_EP1_SIZE 0x00000003u +#define CYREG_USB_ARB_EP1_CFG 0x40006080u +#define CYREG_USB_ARB_EP1_INT_EN 0x40006081u +#define CYREG_USB_ARB_EP1_SR 0x40006082u +#define CYDEV_USB_ARB_RW1_BASE 0x40006084u +#define CYDEV_USB_ARB_RW1_SIZE 0x00000005u +#define CYREG_USB_ARB_RW1_WA 0x40006084u +#define CYREG_USB_ARB_RW1_WA_MSB 0x40006085u +#define CYREG_USB_ARB_RW1_RA 0x40006086u +#define CYREG_USB_ARB_RW1_RA_MSB 0x40006087u +#define CYREG_USB_ARB_RW1_DR 0x40006088u +#define CYREG_USB_BUF_SIZE 0x4000608cu +#define CYREG_USB_EP_ACTIVE 0x4000608eu +#define CYREG_USB_EP_TYPE 0x4000608fu +#define CYDEV_USB_ARB_EP2_BASE 0x40006090u +#define CYDEV_USB_ARB_EP2_SIZE 0x00000003u +#define CYREG_USB_ARB_EP2_CFG 0x40006090u +#define CYREG_USB_ARB_EP2_INT_EN 0x40006091u +#define CYREG_USB_ARB_EP2_SR 0x40006092u +#define CYDEV_USB_ARB_RW2_BASE 0x40006094u +#define CYDEV_USB_ARB_RW2_SIZE 0x00000005u +#define CYREG_USB_ARB_RW2_WA 0x40006094u +#define CYREG_USB_ARB_RW2_WA_MSB 0x40006095u +#define CYREG_USB_ARB_RW2_RA 0x40006096u +#define CYREG_USB_ARB_RW2_RA_MSB 0x40006097u +#define CYREG_USB_ARB_RW2_DR 0x40006098u +#define CYREG_USB_ARB_CFG 0x4000609cu +#define CYREG_USB_USB_CLK_EN 0x4000609du +#define CYREG_USB_ARB_INT_EN 0x4000609eu +#define CYREG_USB_ARB_INT_SR 0x4000609fu +#define CYDEV_USB_ARB_EP3_BASE 0x400060a0u +#define CYDEV_USB_ARB_EP3_SIZE 0x00000003u +#define CYREG_USB_ARB_EP3_CFG 0x400060a0u +#define CYREG_USB_ARB_EP3_INT_EN 0x400060a1u +#define CYREG_USB_ARB_EP3_SR 0x400060a2u +#define CYDEV_USB_ARB_RW3_BASE 0x400060a4u +#define CYDEV_USB_ARB_RW3_SIZE 0x00000005u +#define CYREG_USB_ARB_RW3_WA 0x400060a4u +#define CYREG_USB_ARB_RW3_WA_MSB 0x400060a5u +#define CYREG_USB_ARB_RW3_RA 0x400060a6u +#define CYREG_USB_ARB_RW3_RA_MSB 0x400060a7u +#define CYREG_USB_ARB_RW3_DR 0x400060a8u +#define CYREG_USB_CWA 0x400060acu +#define CYREG_USB_CWA_MSB 0x400060adu +#define CYDEV_USB_ARB_EP4_BASE 0x400060b0u +#define CYDEV_USB_ARB_EP4_SIZE 0x00000003u +#define CYREG_USB_ARB_EP4_CFG 0x400060b0u +#define CYREG_USB_ARB_EP4_INT_EN 0x400060b1u +#define CYREG_USB_ARB_EP4_SR 0x400060b2u +#define CYDEV_USB_ARB_RW4_BASE 0x400060b4u +#define CYDEV_USB_ARB_RW4_SIZE 0x00000005u +#define CYREG_USB_ARB_RW4_WA 0x400060b4u +#define CYREG_USB_ARB_RW4_WA_MSB 0x400060b5u +#define CYREG_USB_ARB_RW4_RA 0x400060b6u +#define CYREG_USB_ARB_RW4_RA_MSB 0x400060b7u +#define CYREG_USB_ARB_RW4_DR 0x400060b8u +#define CYREG_USB_DMA_THRES 0x400060bcu +#define CYREG_USB_DMA_THRES_MSB 0x400060bdu +#define CYDEV_USB_ARB_EP5_BASE 0x400060c0u +#define CYDEV_USB_ARB_EP5_SIZE 0x00000003u +#define CYREG_USB_ARB_EP5_CFG 0x400060c0u +#define CYREG_USB_ARB_EP5_INT_EN 0x400060c1u +#define CYREG_USB_ARB_EP5_SR 0x400060c2u +#define CYDEV_USB_ARB_RW5_BASE 0x400060c4u +#define CYDEV_USB_ARB_RW5_SIZE 0x00000005u +#define CYREG_USB_ARB_RW5_WA 0x400060c4u +#define CYREG_USB_ARB_RW5_WA_MSB 0x400060c5u +#define CYREG_USB_ARB_RW5_RA 0x400060c6u +#define CYREG_USB_ARB_RW5_RA_MSB 0x400060c7u +#define CYREG_USB_ARB_RW5_DR 0x400060c8u +#define CYREG_USB_BUS_RST_CNT 0x400060ccu +#define CYDEV_USB_ARB_EP6_BASE 0x400060d0u +#define CYDEV_USB_ARB_EP6_SIZE 0x00000003u +#define CYREG_USB_ARB_EP6_CFG 0x400060d0u +#define CYREG_USB_ARB_EP6_INT_EN 0x400060d1u +#define CYREG_USB_ARB_EP6_SR 0x400060d2u +#define CYDEV_USB_ARB_RW6_BASE 0x400060d4u +#define CYDEV_USB_ARB_RW6_SIZE 0x00000005u +#define CYREG_USB_ARB_RW6_WA 0x400060d4u +#define CYREG_USB_ARB_RW6_WA_MSB 0x400060d5u +#define CYREG_USB_ARB_RW6_RA 0x400060d6u +#define CYREG_USB_ARB_RW6_RA_MSB 0x400060d7u +#define CYREG_USB_ARB_RW6_DR 0x400060d8u +#define CYDEV_USB_ARB_EP7_BASE 0x400060e0u +#define CYDEV_USB_ARB_EP7_SIZE 0x00000003u +#define CYREG_USB_ARB_EP7_CFG 0x400060e0u +#define CYREG_USB_ARB_EP7_INT_EN 0x400060e1u +#define CYREG_USB_ARB_EP7_SR 0x400060e2u +#define CYDEV_USB_ARB_RW7_BASE 0x400060e4u +#define CYDEV_USB_ARB_RW7_SIZE 0x00000005u +#define CYREG_USB_ARB_RW7_WA 0x400060e4u +#define CYREG_USB_ARB_RW7_WA_MSB 0x400060e5u +#define CYREG_USB_ARB_RW7_RA 0x400060e6u +#define CYREG_USB_ARB_RW7_RA_MSB 0x400060e7u +#define CYREG_USB_ARB_RW7_DR 0x400060e8u +#define CYDEV_USB_ARB_EP8_BASE 0x400060f0u +#define CYDEV_USB_ARB_EP8_SIZE 0x00000003u +#define CYREG_USB_ARB_EP8_CFG 0x400060f0u +#define CYREG_USB_ARB_EP8_INT_EN 0x400060f1u +#define CYREG_USB_ARB_EP8_SR 0x400060f2u +#define CYDEV_USB_ARB_RW8_BASE 0x400060f4u +#define CYDEV_USB_ARB_RW8_SIZE 0x00000005u +#define CYREG_USB_ARB_RW8_WA 0x400060f4u +#define CYREG_USB_ARB_RW8_WA_MSB 0x400060f5u +#define CYREG_USB_ARB_RW8_RA 0x400060f6u +#define CYREG_USB_ARB_RW8_RA_MSB 0x400060f7u +#define CYREG_USB_ARB_RW8_DR 0x400060f8u +#define CYDEV_USB_MEM_BASE 0x40006100u +#define CYDEV_USB_MEM_SIZE 0x00000200u +#define CYREG_USB_MEM_DATA_MBASE 0x40006100u +#define CYREG_USB_MEM_DATA_MSIZE 0x00000200u +#define CYDEV_UWRK_BASE 0x40006400u +#define CYDEV_UWRK_SIZE 0x00000b60u +#define CYDEV_UWRK_UWRK8_BASE 0x40006400u +#define CYDEV_UWRK_UWRK8_SIZE 0x000003b0u +#define CYDEV_UWRK_UWRK8_B0_BASE 0x40006400u +#define CYDEV_UWRK_UWRK8_B0_SIZE 0x000000b0u +#define CYREG_B0_UDB00_A0 0x40006400u +#define CYREG_B0_UDB01_A0 0x40006401u +#define CYREG_B0_UDB02_A0 0x40006402u +#define CYREG_B0_UDB03_A0 0x40006403u +#define CYREG_B0_UDB04_A0 0x40006404u +#define CYREG_B0_UDB05_A0 0x40006405u +#define CYREG_B0_UDB06_A0 0x40006406u +#define CYREG_B0_UDB07_A0 0x40006407u +#define CYREG_B0_UDB08_A0 0x40006408u +#define CYREG_B0_UDB09_A0 0x40006409u +#define CYREG_B0_UDB10_A0 0x4000640au +#define CYREG_B0_UDB11_A0 0x4000640bu +#define CYREG_B0_UDB12_A0 0x4000640cu +#define CYREG_B0_UDB13_A0 0x4000640du +#define CYREG_B0_UDB14_A0 0x4000640eu +#define CYREG_B0_UDB15_A0 0x4000640fu +#define CYREG_B0_UDB00_A1 0x40006410u +#define CYREG_B0_UDB01_A1 0x40006411u +#define CYREG_B0_UDB02_A1 0x40006412u +#define CYREG_B0_UDB03_A1 0x40006413u +#define CYREG_B0_UDB04_A1 0x40006414u +#define CYREG_B0_UDB05_A1 0x40006415u +#define CYREG_B0_UDB06_A1 0x40006416u +#define CYREG_B0_UDB07_A1 0x40006417u +#define CYREG_B0_UDB08_A1 0x40006418u +#define CYREG_B0_UDB09_A1 0x40006419u +#define CYREG_B0_UDB10_A1 0x4000641au +#define CYREG_B0_UDB11_A1 0x4000641bu +#define CYREG_B0_UDB12_A1 0x4000641cu +#define CYREG_B0_UDB13_A1 0x4000641du +#define CYREG_B0_UDB14_A1 0x4000641eu +#define CYREG_B0_UDB15_A1 0x4000641fu +#define CYREG_B0_UDB00_D0 0x40006420u +#define CYREG_B0_UDB01_D0 0x40006421u +#define CYREG_B0_UDB02_D0 0x40006422u +#define CYREG_B0_UDB03_D0 0x40006423u +#define CYREG_B0_UDB04_D0 0x40006424u +#define CYREG_B0_UDB05_D0 0x40006425u +#define CYREG_B0_UDB06_D0 0x40006426u +#define CYREG_B0_UDB07_D0 0x40006427u +#define CYREG_B0_UDB08_D0 0x40006428u +#define CYREG_B0_UDB09_D0 0x40006429u +#define CYREG_B0_UDB10_D0 0x4000642au +#define CYREG_B0_UDB11_D0 0x4000642bu +#define CYREG_B0_UDB12_D0 0x4000642cu +#define CYREG_B0_UDB13_D0 0x4000642du +#define CYREG_B0_UDB14_D0 0x4000642eu +#define CYREG_B0_UDB15_D0 0x4000642fu +#define CYREG_B0_UDB00_D1 0x40006430u +#define CYREG_B0_UDB01_D1 0x40006431u +#define CYREG_B0_UDB02_D1 0x40006432u +#define CYREG_B0_UDB03_D1 0x40006433u +#define CYREG_B0_UDB04_D1 0x40006434u +#define CYREG_B0_UDB05_D1 0x40006435u +#define CYREG_B0_UDB06_D1 0x40006436u +#define CYREG_B0_UDB07_D1 0x40006437u +#define CYREG_B0_UDB08_D1 0x40006438u +#define CYREG_B0_UDB09_D1 0x40006439u +#define CYREG_B0_UDB10_D1 0x4000643au +#define CYREG_B0_UDB11_D1 0x4000643bu +#define CYREG_B0_UDB12_D1 0x4000643cu +#define CYREG_B0_UDB13_D1 0x4000643du +#define CYREG_B0_UDB14_D1 0x4000643eu +#define CYREG_B0_UDB15_D1 0x4000643fu +#define CYREG_B0_UDB00_F0 0x40006440u +#define CYREG_B0_UDB01_F0 0x40006441u +#define CYREG_B0_UDB02_F0 0x40006442u +#define CYREG_B0_UDB03_F0 0x40006443u +#define CYREG_B0_UDB04_F0 0x40006444u +#define CYREG_B0_UDB05_F0 0x40006445u +#define CYREG_B0_UDB06_F0 0x40006446u +#define CYREG_B0_UDB07_F0 0x40006447u +#define CYREG_B0_UDB08_F0 0x40006448u +#define CYREG_B0_UDB09_F0 0x40006449u +#define CYREG_B0_UDB10_F0 0x4000644au +#define CYREG_B0_UDB11_F0 0x4000644bu +#define CYREG_B0_UDB12_F0 0x4000644cu +#define CYREG_B0_UDB13_F0 0x4000644du +#define CYREG_B0_UDB14_F0 0x4000644eu +#define CYREG_B0_UDB15_F0 0x4000644fu +#define CYREG_B0_UDB00_F1 0x40006450u +#define CYREG_B0_UDB01_F1 0x40006451u +#define CYREG_B0_UDB02_F1 0x40006452u +#define CYREG_B0_UDB03_F1 0x40006453u +#define CYREG_B0_UDB04_F1 0x40006454u +#define CYREG_B0_UDB05_F1 0x40006455u +#define CYREG_B0_UDB06_F1 0x40006456u +#define CYREG_B0_UDB07_F1 0x40006457u +#define CYREG_B0_UDB08_F1 0x40006458u +#define CYREG_B0_UDB09_F1 0x40006459u +#define CYREG_B0_UDB10_F1 0x4000645au +#define CYREG_B0_UDB11_F1 0x4000645bu +#define CYREG_B0_UDB12_F1 0x4000645cu +#define CYREG_B0_UDB13_F1 0x4000645du +#define CYREG_B0_UDB14_F1 0x4000645eu +#define CYREG_B0_UDB15_F1 0x4000645fu +#define CYREG_B0_UDB00_ST 0x40006460u +#define CYREG_B0_UDB01_ST 0x40006461u +#define CYREG_B0_UDB02_ST 0x40006462u +#define CYREG_B0_UDB03_ST 0x40006463u +#define CYREG_B0_UDB04_ST 0x40006464u +#define CYREG_B0_UDB05_ST 0x40006465u +#define CYREG_B0_UDB06_ST 0x40006466u +#define CYREG_B0_UDB07_ST 0x40006467u +#define CYREG_B0_UDB08_ST 0x40006468u +#define CYREG_B0_UDB09_ST 0x40006469u +#define CYREG_B0_UDB10_ST 0x4000646au +#define CYREG_B0_UDB11_ST 0x4000646bu +#define CYREG_B0_UDB12_ST 0x4000646cu +#define CYREG_B0_UDB13_ST 0x4000646du +#define CYREG_B0_UDB14_ST 0x4000646eu +#define CYREG_B0_UDB15_ST 0x4000646fu +#define CYREG_B0_UDB00_CTL 0x40006470u +#define CYREG_B0_UDB01_CTL 0x40006471u +#define CYREG_B0_UDB02_CTL 0x40006472u +#define CYREG_B0_UDB03_CTL 0x40006473u +#define CYREG_B0_UDB04_CTL 0x40006474u +#define CYREG_B0_UDB05_CTL 0x40006475u +#define CYREG_B0_UDB06_CTL 0x40006476u +#define CYREG_B0_UDB07_CTL 0x40006477u +#define CYREG_B0_UDB08_CTL 0x40006478u +#define CYREG_B0_UDB09_CTL 0x40006479u +#define CYREG_B0_UDB10_CTL 0x4000647au +#define CYREG_B0_UDB11_CTL 0x4000647bu +#define CYREG_B0_UDB12_CTL 0x4000647cu +#define CYREG_B0_UDB13_CTL 0x4000647du +#define CYREG_B0_UDB14_CTL 0x4000647eu +#define CYREG_B0_UDB15_CTL 0x4000647fu +#define CYREG_B0_UDB00_MSK 0x40006480u +#define CYREG_B0_UDB01_MSK 0x40006481u +#define CYREG_B0_UDB02_MSK 0x40006482u +#define CYREG_B0_UDB03_MSK 0x40006483u +#define CYREG_B0_UDB04_MSK 0x40006484u +#define CYREG_B0_UDB05_MSK 0x40006485u +#define CYREG_B0_UDB06_MSK 0x40006486u +#define CYREG_B0_UDB07_MSK 0x40006487u +#define CYREG_B0_UDB08_MSK 0x40006488u +#define CYREG_B0_UDB09_MSK 0x40006489u +#define CYREG_B0_UDB10_MSK 0x4000648au +#define CYREG_B0_UDB11_MSK 0x4000648bu +#define CYREG_B0_UDB12_MSK 0x4000648cu +#define CYREG_B0_UDB13_MSK 0x4000648du +#define CYREG_B0_UDB14_MSK 0x4000648eu +#define CYREG_B0_UDB15_MSK 0x4000648fu +#define CYREG_B0_UDB00_ACTL 0x40006490u +#define CYREG_B0_UDB01_ACTL 0x40006491u +#define CYREG_B0_UDB02_ACTL 0x40006492u +#define CYREG_B0_UDB03_ACTL 0x40006493u +#define CYREG_B0_UDB04_ACTL 0x40006494u +#define CYREG_B0_UDB05_ACTL 0x40006495u +#define CYREG_B0_UDB06_ACTL 0x40006496u +#define CYREG_B0_UDB07_ACTL 0x40006497u +#define CYREG_B0_UDB08_ACTL 0x40006498u +#define CYREG_B0_UDB09_ACTL 0x40006499u +#define CYREG_B0_UDB10_ACTL 0x4000649au +#define CYREG_B0_UDB11_ACTL 0x4000649bu +#define CYREG_B0_UDB12_ACTL 0x4000649cu +#define CYREG_B0_UDB13_ACTL 0x4000649du +#define CYREG_B0_UDB14_ACTL 0x4000649eu +#define CYREG_B0_UDB15_ACTL 0x4000649fu +#define CYREG_B0_UDB00_MC 0x400064a0u +#define CYREG_B0_UDB01_MC 0x400064a1u +#define CYREG_B0_UDB02_MC 0x400064a2u +#define CYREG_B0_UDB03_MC 0x400064a3u +#define CYREG_B0_UDB04_MC 0x400064a4u +#define CYREG_B0_UDB05_MC 0x400064a5u +#define CYREG_B0_UDB06_MC 0x400064a6u +#define CYREG_B0_UDB07_MC 0x400064a7u +#define CYREG_B0_UDB08_MC 0x400064a8u +#define CYREG_B0_UDB09_MC 0x400064a9u +#define CYREG_B0_UDB10_MC 0x400064aau +#define CYREG_B0_UDB11_MC 0x400064abu +#define CYREG_B0_UDB12_MC 0x400064acu +#define CYREG_B0_UDB13_MC 0x400064adu +#define CYREG_B0_UDB14_MC 0x400064aeu +#define CYREG_B0_UDB15_MC 0x400064afu +#define CYDEV_UWRK_UWRK8_B1_BASE 0x40006500u +#define CYDEV_UWRK_UWRK8_B1_SIZE 0x000000b0u +#define CYREG_B1_UDB04_A0 0x40006504u +#define CYREG_B1_UDB05_A0 0x40006505u +#define CYREG_B1_UDB06_A0 0x40006506u +#define CYREG_B1_UDB07_A0 0x40006507u +#define CYREG_B1_UDB08_A0 0x40006508u +#define CYREG_B1_UDB09_A0 0x40006509u +#define CYREG_B1_UDB10_A0 0x4000650au +#define CYREG_B1_UDB11_A0 0x4000650bu +#define CYREG_B1_UDB04_A1 0x40006514u +#define CYREG_B1_UDB05_A1 0x40006515u +#define CYREG_B1_UDB06_A1 0x40006516u +#define CYREG_B1_UDB07_A1 0x40006517u +#define CYREG_B1_UDB08_A1 0x40006518u +#define CYREG_B1_UDB09_A1 0x40006519u +#define CYREG_B1_UDB10_A1 0x4000651au +#define CYREG_B1_UDB11_A1 0x4000651bu +#define CYREG_B1_UDB04_D0 0x40006524u +#define CYREG_B1_UDB05_D0 0x40006525u +#define CYREG_B1_UDB06_D0 0x40006526u +#define CYREG_B1_UDB07_D0 0x40006527u +#define CYREG_B1_UDB08_D0 0x40006528u +#define CYREG_B1_UDB09_D0 0x40006529u +#define CYREG_B1_UDB10_D0 0x4000652au +#define CYREG_B1_UDB11_D0 0x4000652bu +#define CYREG_B1_UDB04_D1 0x40006534u +#define CYREG_B1_UDB05_D1 0x40006535u +#define CYREG_B1_UDB06_D1 0x40006536u +#define CYREG_B1_UDB07_D1 0x40006537u +#define CYREG_B1_UDB08_D1 0x40006538u +#define CYREG_B1_UDB09_D1 0x40006539u +#define CYREG_B1_UDB10_D1 0x4000653au +#define CYREG_B1_UDB11_D1 0x4000653bu +#define CYREG_B1_UDB04_F0 0x40006544u +#define CYREG_B1_UDB05_F0 0x40006545u +#define CYREG_B1_UDB06_F0 0x40006546u +#define CYREG_B1_UDB07_F0 0x40006547u +#define CYREG_B1_UDB08_F0 0x40006548u +#define CYREG_B1_UDB09_F0 0x40006549u +#define CYREG_B1_UDB10_F0 0x4000654au +#define CYREG_B1_UDB11_F0 0x4000654bu +#define CYREG_B1_UDB04_F1 0x40006554u +#define CYREG_B1_UDB05_F1 0x40006555u +#define CYREG_B1_UDB06_F1 0x40006556u +#define CYREG_B1_UDB07_F1 0x40006557u +#define CYREG_B1_UDB08_F1 0x40006558u +#define CYREG_B1_UDB09_F1 0x40006559u +#define CYREG_B1_UDB10_F1 0x4000655au +#define CYREG_B1_UDB11_F1 0x4000655bu +#define CYREG_B1_UDB04_ST 0x40006564u +#define CYREG_B1_UDB05_ST 0x40006565u +#define CYREG_B1_UDB06_ST 0x40006566u +#define CYREG_B1_UDB07_ST 0x40006567u +#define CYREG_B1_UDB08_ST 0x40006568u +#define CYREG_B1_UDB09_ST 0x40006569u +#define CYREG_B1_UDB10_ST 0x4000656au +#define CYREG_B1_UDB11_ST 0x4000656bu +#define CYREG_B1_UDB04_CTL 0x40006574u +#define CYREG_B1_UDB05_CTL 0x40006575u +#define CYREG_B1_UDB06_CTL 0x40006576u +#define CYREG_B1_UDB07_CTL 0x40006577u +#define CYREG_B1_UDB08_CTL 0x40006578u +#define CYREG_B1_UDB09_CTL 0x40006579u +#define CYREG_B1_UDB10_CTL 0x4000657au +#define CYREG_B1_UDB11_CTL 0x4000657bu +#define CYREG_B1_UDB04_MSK 0x40006584u +#define CYREG_B1_UDB05_MSK 0x40006585u +#define CYREG_B1_UDB06_MSK 0x40006586u +#define CYREG_B1_UDB07_MSK 0x40006587u +#define CYREG_B1_UDB08_MSK 0x40006588u +#define CYREG_B1_UDB09_MSK 0x40006589u +#define CYREG_B1_UDB10_MSK 0x4000658au +#define CYREG_B1_UDB11_MSK 0x4000658bu +#define CYREG_B1_UDB04_ACTL 0x40006594u +#define CYREG_B1_UDB05_ACTL 0x40006595u +#define CYREG_B1_UDB06_ACTL 0x40006596u +#define CYREG_B1_UDB07_ACTL 0x40006597u +#define CYREG_B1_UDB08_ACTL 0x40006598u +#define CYREG_B1_UDB09_ACTL 0x40006599u +#define CYREG_B1_UDB10_ACTL 0x4000659au +#define CYREG_B1_UDB11_ACTL 0x4000659bu +#define CYREG_B1_UDB04_MC 0x400065a4u +#define CYREG_B1_UDB05_MC 0x400065a5u +#define CYREG_B1_UDB06_MC 0x400065a6u +#define CYREG_B1_UDB07_MC 0x400065a7u +#define CYREG_B1_UDB08_MC 0x400065a8u +#define CYREG_B1_UDB09_MC 0x400065a9u +#define CYREG_B1_UDB10_MC 0x400065aau +#define CYREG_B1_UDB11_MC 0x400065abu +#define CYDEV_UWRK_UWRK16_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_SIZE 0x00000760u +#define CYDEV_UWRK_UWRK16_CAT_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_CAT_SIZE 0x00000760u +#define CYDEV_UWRK_UWRK16_CAT_B0_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_CAT_B0_SIZE 0x00000160u +#define CYREG_B0_UDB00_A0_A1 0x40006800u +#define CYREG_B0_UDB01_A0_A1 0x40006802u +#define CYREG_B0_UDB02_A0_A1 0x40006804u +#define CYREG_B0_UDB03_A0_A1 0x40006806u +#define CYREG_B0_UDB04_A0_A1 0x40006808u +#define CYREG_B0_UDB05_A0_A1 0x4000680au +#define CYREG_B0_UDB06_A0_A1 0x4000680cu +#define CYREG_B0_UDB07_A0_A1 0x4000680eu +#define CYREG_B0_UDB08_A0_A1 0x40006810u +#define CYREG_B0_UDB09_A0_A1 0x40006812u +#define CYREG_B0_UDB10_A0_A1 0x40006814u +#define CYREG_B0_UDB11_A0_A1 0x40006816u +#define CYREG_B0_UDB12_A0_A1 0x40006818u +#define CYREG_B0_UDB13_A0_A1 0x4000681au +#define CYREG_B0_UDB14_A0_A1 0x4000681cu +#define CYREG_B0_UDB15_A0_A1 0x4000681eu +#define CYREG_B0_UDB00_D0_D1 0x40006840u +#define CYREG_B0_UDB01_D0_D1 0x40006842u +#define CYREG_B0_UDB02_D0_D1 0x40006844u +#define CYREG_B0_UDB03_D0_D1 0x40006846u +#define CYREG_B0_UDB04_D0_D1 0x40006848u +#define CYREG_B0_UDB05_D0_D1 0x4000684au +#define CYREG_B0_UDB06_D0_D1 0x4000684cu +#define CYREG_B0_UDB07_D0_D1 0x4000684eu +#define CYREG_B0_UDB08_D0_D1 0x40006850u +#define CYREG_B0_UDB09_D0_D1 0x40006852u +#define CYREG_B0_UDB10_D0_D1 0x40006854u +#define CYREG_B0_UDB11_D0_D1 0x40006856u +#define CYREG_B0_UDB12_D0_D1 0x40006858u +#define CYREG_B0_UDB13_D0_D1 0x4000685au +#define CYREG_B0_UDB14_D0_D1 0x4000685cu +#define CYREG_B0_UDB15_D0_D1 0x4000685eu +#define CYREG_B0_UDB00_F0_F1 0x40006880u +#define CYREG_B0_UDB01_F0_F1 0x40006882u +#define CYREG_B0_UDB02_F0_F1 0x40006884u +#define CYREG_B0_UDB03_F0_F1 0x40006886u +#define CYREG_B0_UDB04_F0_F1 0x40006888u +#define CYREG_B0_UDB05_F0_F1 0x4000688au +#define CYREG_B0_UDB06_F0_F1 0x4000688cu +#define CYREG_B0_UDB07_F0_F1 0x4000688eu +#define CYREG_B0_UDB08_F0_F1 0x40006890u +#define CYREG_B0_UDB09_F0_F1 0x40006892u +#define CYREG_B0_UDB10_F0_F1 0x40006894u +#define CYREG_B0_UDB11_F0_F1 0x40006896u +#define CYREG_B0_UDB12_F0_F1 0x40006898u +#define CYREG_B0_UDB13_F0_F1 0x4000689au +#define CYREG_B0_UDB14_F0_F1 0x4000689cu +#define CYREG_B0_UDB15_F0_F1 0x4000689eu +#define CYREG_B0_UDB00_ST_CTL 0x400068c0u +#define CYREG_B0_UDB01_ST_CTL 0x400068c2u +#define CYREG_B0_UDB02_ST_CTL 0x400068c4u +#define CYREG_B0_UDB03_ST_CTL 0x400068c6u +#define CYREG_B0_UDB04_ST_CTL 0x400068c8u +#define CYREG_B0_UDB05_ST_CTL 0x400068cau +#define CYREG_B0_UDB06_ST_CTL 0x400068ccu +#define CYREG_B0_UDB07_ST_CTL 0x400068ceu +#define CYREG_B0_UDB08_ST_CTL 0x400068d0u +#define CYREG_B0_UDB09_ST_CTL 0x400068d2u +#define CYREG_B0_UDB10_ST_CTL 0x400068d4u +#define CYREG_B0_UDB11_ST_CTL 0x400068d6u +#define CYREG_B0_UDB12_ST_CTL 0x400068d8u +#define CYREG_B0_UDB13_ST_CTL 0x400068dau +#define CYREG_B0_UDB14_ST_CTL 0x400068dcu +#define CYREG_B0_UDB15_ST_CTL 0x400068deu +#define CYREG_B0_UDB00_MSK_ACTL 0x40006900u +#define CYREG_B0_UDB01_MSK_ACTL 0x40006902u +#define CYREG_B0_UDB02_MSK_ACTL 0x40006904u +#define CYREG_B0_UDB03_MSK_ACTL 0x40006906u +#define CYREG_B0_UDB04_MSK_ACTL 0x40006908u +#define CYREG_B0_UDB05_MSK_ACTL 0x4000690au +#define CYREG_B0_UDB06_MSK_ACTL 0x4000690cu +#define CYREG_B0_UDB07_MSK_ACTL 0x4000690eu +#define CYREG_B0_UDB08_MSK_ACTL 0x40006910u +#define CYREG_B0_UDB09_MSK_ACTL 0x40006912u +#define CYREG_B0_UDB10_MSK_ACTL 0x40006914u +#define CYREG_B0_UDB11_MSK_ACTL 0x40006916u +#define CYREG_B0_UDB12_MSK_ACTL 0x40006918u +#define CYREG_B0_UDB13_MSK_ACTL 0x4000691au +#define CYREG_B0_UDB14_MSK_ACTL 0x4000691cu +#define CYREG_B0_UDB15_MSK_ACTL 0x4000691eu +#define CYREG_B0_UDB00_MC_00 0x40006940u +#define CYREG_B0_UDB01_MC_00 0x40006942u +#define CYREG_B0_UDB02_MC_00 0x40006944u +#define CYREG_B0_UDB03_MC_00 0x40006946u +#define CYREG_B0_UDB04_MC_00 0x40006948u +#define CYREG_B0_UDB05_MC_00 0x4000694au +#define CYREG_B0_UDB06_MC_00 0x4000694cu +#define CYREG_B0_UDB07_MC_00 0x4000694eu +#define CYREG_B0_UDB08_MC_00 0x40006950u +#define CYREG_B0_UDB09_MC_00 0x40006952u +#define CYREG_B0_UDB10_MC_00 0x40006954u +#define CYREG_B0_UDB11_MC_00 0x40006956u +#define CYREG_B0_UDB12_MC_00 0x40006958u +#define CYREG_B0_UDB13_MC_00 0x4000695au +#define CYREG_B0_UDB14_MC_00 0x4000695cu +#define CYREG_B0_UDB15_MC_00 0x4000695eu +#define CYDEV_UWRK_UWRK16_CAT_B1_BASE 0x40006a00u +#define CYDEV_UWRK_UWRK16_CAT_B1_SIZE 0x00000160u +#define CYREG_B1_UDB04_A0_A1 0x40006a08u +#define CYREG_B1_UDB05_A0_A1 0x40006a0au +#define CYREG_B1_UDB06_A0_A1 0x40006a0cu +#define CYREG_B1_UDB07_A0_A1 0x40006a0eu +#define CYREG_B1_UDB08_A0_A1 0x40006a10u +#define CYREG_B1_UDB09_A0_A1 0x40006a12u +#define CYREG_B1_UDB10_A0_A1 0x40006a14u +#define CYREG_B1_UDB11_A0_A1 0x40006a16u +#define CYREG_B1_UDB04_D0_D1 0x40006a48u +#define CYREG_B1_UDB05_D0_D1 0x40006a4au +#define CYREG_B1_UDB06_D0_D1 0x40006a4cu +#define CYREG_B1_UDB07_D0_D1 0x40006a4eu +#define CYREG_B1_UDB08_D0_D1 0x40006a50u +#define CYREG_B1_UDB09_D0_D1 0x40006a52u +#define CYREG_B1_UDB10_D0_D1 0x40006a54u +#define CYREG_B1_UDB11_D0_D1 0x40006a56u +#define CYREG_B1_UDB04_F0_F1 0x40006a88u +#define CYREG_B1_UDB05_F0_F1 0x40006a8au +#define CYREG_B1_UDB06_F0_F1 0x40006a8cu +#define CYREG_B1_UDB07_F0_F1 0x40006a8eu +#define CYREG_B1_UDB08_F0_F1 0x40006a90u +#define CYREG_B1_UDB09_F0_F1 0x40006a92u +#define CYREG_B1_UDB10_F0_F1 0x40006a94u +#define CYREG_B1_UDB11_F0_F1 0x40006a96u +#define CYREG_B1_UDB04_ST_CTL 0x40006ac8u +#define CYREG_B1_UDB05_ST_CTL 0x40006acau +#define CYREG_B1_UDB06_ST_CTL 0x40006accu +#define CYREG_B1_UDB07_ST_CTL 0x40006aceu +#define CYREG_B1_UDB08_ST_CTL 0x40006ad0u +#define CYREG_B1_UDB09_ST_CTL 0x40006ad2u +#define CYREG_B1_UDB10_ST_CTL 0x40006ad4u +#define CYREG_B1_UDB11_ST_CTL 0x40006ad6u +#define CYREG_B1_UDB04_MSK_ACTL 0x40006b08u +#define CYREG_B1_UDB05_MSK_ACTL 0x40006b0au +#define CYREG_B1_UDB06_MSK_ACTL 0x40006b0cu +#define CYREG_B1_UDB07_MSK_ACTL 0x40006b0eu +#define CYREG_B1_UDB08_MSK_ACTL 0x40006b10u +#define CYREG_B1_UDB09_MSK_ACTL 0x40006b12u +#define CYREG_B1_UDB10_MSK_ACTL 0x40006b14u +#define CYREG_B1_UDB11_MSK_ACTL 0x40006b16u +#define CYREG_B1_UDB04_MC_00 0x40006b48u +#define CYREG_B1_UDB05_MC_00 0x40006b4au +#define CYREG_B1_UDB06_MC_00 0x40006b4cu +#define CYREG_B1_UDB07_MC_00 0x40006b4eu +#define CYREG_B1_UDB08_MC_00 0x40006b50u +#define CYREG_B1_UDB09_MC_00 0x40006b52u +#define CYREG_B1_UDB10_MC_00 0x40006b54u +#define CYREG_B1_UDB11_MC_00 0x40006b56u +#define CYDEV_UWRK_UWRK16_DEF_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_DEF_SIZE 0x0000075eu +#define CYDEV_UWRK_UWRK16_DEF_B0_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_DEF_B0_SIZE 0x0000015eu +#define CYREG_B0_UDB00_01_A0 0x40006800u +#define CYREG_B0_UDB01_02_A0 0x40006802u +#define CYREG_B0_UDB02_03_A0 0x40006804u +#define CYREG_B0_UDB03_04_A0 0x40006806u +#define CYREG_B0_UDB04_05_A0 0x40006808u +#define CYREG_B0_UDB05_06_A0 0x4000680au +#define CYREG_B0_UDB06_07_A0 0x4000680cu +#define CYREG_B0_UDB07_08_A0 0x4000680eu +#define CYREG_B0_UDB08_09_A0 0x40006810u +#define CYREG_B0_UDB09_10_A0 0x40006812u +#define CYREG_B0_UDB10_11_A0 0x40006814u +#define CYREG_B0_UDB11_12_A0 0x40006816u +#define CYREG_B0_UDB12_13_A0 0x40006818u +#define CYREG_B0_UDB13_14_A0 0x4000681au +#define CYREG_B0_UDB14_15_A0 0x4000681cu +#define CYREG_B0_UDB00_01_A1 0x40006820u +#define CYREG_B0_UDB01_02_A1 0x40006822u +#define CYREG_B0_UDB02_03_A1 0x40006824u +#define CYREG_B0_UDB03_04_A1 0x40006826u +#define CYREG_B0_UDB04_05_A1 0x40006828u +#define CYREG_B0_UDB05_06_A1 0x4000682au +#define CYREG_B0_UDB06_07_A1 0x4000682cu +#define CYREG_B0_UDB07_08_A1 0x4000682eu +#define CYREG_B0_UDB08_09_A1 0x40006830u +#define CYREG_B0_UDB09_10_A1 0x40006832u +#define CYREG_B0_UDB10_11_A1 0x40006834u +#define CYREG_B0_UDB11_12_A1 0x40006836u +#define CYREG_B0_UDB12_13_A1 0x40006838u +#define CYREG_B0_UDB13_14_A1 0x4000683au +#define CYREG_B0_UDB14_15_A1 0x4000683cu +#define CYREG_B0_UDB00_01_D0 0x40006840u +#define CYREG_B0_UDB01_02_D0 0x40006842u +#define CYREG_B0_UDB02_03_D0 0x40006844u +#define CYREG_B0_UDB03_04_D0 0x40006846u +#define CYREG_B0_UDB04_05_D0 0x40006848u +#define CYREG_B0_UDB05_06_D0 0x4000684au +#define CYREG_B0_UDB06_07_D0 0x4000684cu +#define CYREG_B0_UDB07_08_D0 0x4000684eu +#define CYREG_B0_UDB08_09_D0 0x40006850u +#define CYREG_B0_UDB09_10_D0 0x40006852u +#define CYREG_B0_UDB10_11_D0 0x40006854u +#define CYREG_B0_UDB11_12_D0 0x40006856u +#define CYREG_B0_UDB12_13_D0 0x40006858u +#define CYREG_B0_UDB13_14_D0 0x4000685au +#define CYREG_B0_UDB14_15_D0 0x4000685cu +#define CYREG_B0_UDB00_01_D1 0x40006860u +#define CYREG_B0_UDB01_02_D1 0x40006862u +#define CYREG_B0_UDB02_03_D1 0x40006864u +#define CYREG_B0_UDB03_04_D1 0x40006866u +#define CYREG_B0_UDB04_05_D1 0x40006868u +#define CYREG_B0_UDB05_06_D1 0x4000686au +#define CYREG_B0_UDB06_07_D1 0x4000686cu +#define CYREG_B0_UDB07_08_D1 0x4000686eu +#define CYREG_B0_UDB08_09_D1 0x40006870u +#define CYREG_B0_UDB09_10_D1 0x40006872u +#define CYREG_B0_UDB10_11_D1 0x40006874u +#define CYREG_B0_UDB11_12_D1 0x40006876u +#define CYREG_B0_UDB12_13_D1 0x40006878u +#define CYREG_B0_UDB13_14_D1 0x4000687au +#define CYREG_B0_UDB14_15_D1 0x4000687cu +#define CYREG_B0_UDB00_01_F0 0x40006880u +#define CYREG_B0_UDB01_02_F0 0x40006882u +#define CYREG_B0_UDB02_03_F0 0x40006884u +#define CYREG_B0_UDB03_04_F0 0x40006886u +#define CYREG_B0_UDB04_05_F0 0x40006888u +#define CYREG_B0_UDB05_06_F0 0x4000688au +#define CYREG_B0_UDB06_07_F0 0x4000688cu +#define CYREG_B0_UDB07_08_F0 0x4000688eu +#define CYREG_B0_UDB08_09_F0 0x40006890u +#define CYREG_B0_UDB09_10_F0 0x40006892u +#define CYREG_B0_UDB10_11_F0 0x40006894u +#define CYREG_B0_UDB11_12_F0 0x40006896u +#define CYREG_B0_UDB12_13_F0 0x40006898u +#define CYREG_B0_UDB13_14_F0 0x4000689au +#define CYREG_B0_UDB14_15_F0 0x4000689cu +#define CYREG_B0_UDB00_01_F1 0x400068a0u +#define CYREG_B0_UDB01_02_F1 0x400068a2u +#define CYREG_B0_UDB02_03_F1 0x400068a4u +#define CYREG_B0_UDB03_04_F1 0x400068a6u +#define CYREG_B0_UDB04_05_F1 0x400068a8u +#define CYREG_B0_UDB05_06_F1 0x400068aau +#define CYREG_B0_UDB06_07_F1 0x400068acu +#define CYREG_B0_UDB07_08_F1 0x400068aeu +#define CYREG_B0_UDB08_09_F1 0x400068b0u +#define CYREG_B0_UDB09_10_F1 0x400068b2u +#define CYREG_B0_UDB10_11_F1 0x400068b4u +#define CYREG_B0_UDB11_12_F1 0x400068b6u +#define CYREG_B0_UDB12_13_F1 0x400068b8u +#define CYREG_B0_UDB13_14_F1 0x400068bau +#define CYREG_B0_UDB14_15_F1 0x400068bcu +#define CYREG_B0_UDB00_01_ST 0x400068c0u +#define CYREG_B0_UDB01_02_ST 0x400068c2u +#define CYREG_B0_UDB02_03_ST 0x400068c4u +#define CYREG_B0_UDB03_04_ST 0x400068c6u +#define CYREG_B0_UDB04_05_ST 0x400068c8u +#define CYREG_B0_UDB05_06_ST 0x400068cau +#define CYREG_B0_UDB06_07_ST 0x400068ccu +#define CYREG_B0_UDB07_08_ST 0x400068ceu +#define CYREG_B0_UDB08_09_ST 0x400068d0u +#define CYREG_B0_UDB09_10_ST 0x400068d2u +#define CYREG_B0_UDB10_11_ST 0x400068d4u +#define CYREG_B0_UDB11_12_ST 0x400068d6u +#define CYREG_B0_UDB12_13_ST 0x400068d8u +#define CYREG_B0_UDB13_14_ST 0x400068dau +#define CYREG_B0_UDB14_15_ST 0x400068dcu +#define CYREG_B0_UDB00_01_CTL 0x400068e0u +#define CYREG_B0_UDB01_02_CTL 0x400068e2u +#define CYREG_B0_UDB02_03_CTL 0x400068e4u +#define CYREG_B0_UDB03_04_CTL 0x400068e6u +#define CYREG_B0_UDB04_05_CTL 0x400068e8u +#define CYREG_B0_UDB05_06_CTL 0x400068eau +#define CYREG_B0_UDB06_07_CTL 0x400068ecu +#define CYREG_B0_UDB07_08_CTL 0x400068eeu +#define CYREG_B0_UDB08_09_CTL 0x400068f0u +#define CYREG_B0_UDB09_10_CTL 0x400068f2u +#define CYREG_B0_UDB10_11_CTL 0x400068f4u +#define CYREG_B0_UDB11_12_CTL 0x400068f6u +#define CYREG_B0_UDB12_13_CTL 0x400068f8u +#define CYREG_B0_UDB13_14_CTL 0x400068fau +#define CYREG_B0_UDB14_15_CTL 0x400068fcu +#define CYREG_B0_UDB00_01_MSK 0x40006900u +#define CYREG_B0_UDB01_02_MSK 0x40006902u +#define CYREG_B0_UDB02_03_MSK 0x40006904u +#define CYREG_B0_UDB03_04_MSK 0x40006906u +#define CYREG_B0_UDB04_05_MSK 0x40006908u +#define CYREG_B0_UDB05_06_MSK 0x4000690au +#define CYREG_B0_UDB06_07_MSK 0x4000690cu +#define CYREG_B0_UDB07_08_MSK 0x4000690eu +#define CYREG_B0_UDB08_09_MSK 0x40006910u +#define CYREG_B0_UDB09_10_MSK 0x40006912u +#define CYREG_B0_UDB10_11_MSK 0x40006914u +#define CYREG_B0_UDB11_12_MSK 0x40006916u +#define CYREG_B0_UDB12_13_MSK 0x40006918u +#define CYREG_B0_UDB13_14_MSK 0x4000691au +#define CYREG_B0_UDB14_15_MSK 0x4000691cu +#define CYREG_B0_UDB00_01_ACTL 0x40006920u +#define CYREG_B0_UDB01_02_ACTL 0x40006922u +#define CYREG_B0_UDB02_03_ACTL 0x40006924u +#define CYREG_B0_UDB03_04_ACTL 0x40006926u +#define CYREG_B0_UDB04_05_ACTL 0x40006928u +#define CYREG_B0_UDB05_06_ACTL 0x4000692au +#define CYREG_B0_UDB06_07_ACTL 0x4000692cu +#define CYREG_B0_UDB07_08_ACTL 0x4000692eu +#define CYREG_B0_UDB08_09_ACTL 0x40006930u +#define CYREG_B0_UDB09_10_ACTL 0x40006932u +#define CYREG_B0_UDB10_11_ACTL 0x40006934u +#define CYREG_B0_UDB11_12_ACTL 0x40006936u +#define CYREG_B0_UDB12_13_ACTL 0x40006938u +#define CYREG_B0_UDB13_14_ACTL 0x4000693au +#define CYREG_B0_UDB14_15_ACTL 0x4000693cu +#define CYREG_B0_UDB00_01_MC 0x40006940u +#define CYREG_B0_UDB01_02_MC 0x40006942u +#define CYREG_B0_UDB02_03_MC 0x40006944u +#define CYREG_B0_UDB03_04_MC 0x40006946u +#define CYREG_B0_UDB04_05_MC 0x40006948u +#define CYREG_B0_UDB05_06_MC 0x4000694au +#define CYREG_B0_UDB06_07_MC 0x4000694cu +#define CYREG_B0_UDB07_08_MC 0x4000694eu +#define CYREG_B0_UDB08_09_MC 0x40006950u +#define CYREG_B0_UDB09_10_MC 0x40006952u +#define CYREG_B0_UDB10_11_MC 0x40006954u +#define CYREG_B0_UDB11_12_MC 0x40006956u +#define CYREG_B0_UDB12_13_MC 0x40006958u +#define CYREG_B0_UDB13_14_MC 0x4000695au +#define CYREG_B0_UDB14_15_MC 0x4000695cu +#define CYDEV_UWRK_UWRK16_DEF_B1_BASE 0x40006a00u +#define CYDEV_UWRK_UWRK16_DEF_B1_SIZE 0x0000015eu +#define CYREG_B1_UDB04_05_A0 0x40006a08u +#define CYREG_B1_UDB05_06_A0 0x40006a0au +#define CYREG_B1_UDB06_07_A0 0x40006a0cu +#define CYREG_B1_UDB07_08_A0 0x40006a0eu +#define CYREG_B1_UDB08_09_A0 0x40006a10u +#define CYREG_B1_UDB09_10_A0 0x40006a12u +#define CYREG_B1_UDB10_11_A0 0x40006a14u +#define CYREG_B1_UDB11_12_A0 0x40006a16u +#define CYREG_B1_UDB04_05_A1 0x40006a28u +#define CYREG_B1_UDB05_06_A1 0x40006a2au +#define CYREG_B1_UDB06_07_A1 0x40006a2cu +#define CYREG_B1_UDB07_08_A1 0x40006a2eu +#define CYREG_B1_UDB08_09_A1 0x40006a30u +#define CYREG_B1_UDB09_10_A1 0x40006a32u +#define CYREG_B1_UDB10_11_A1 0x40006a34u +#define CYREG_B1_UDB11_12_A1 0x40006a36u +#define CYREG_B1_UDB04_05_D0 0x40006a48u +#define CYREG_B1_UDB05_06_D0 0x40006a4au +#define CYREG_B1_UDB06_07_D0 0x40006a4cu +#define CYREG_B1_UDB07_08_D0 0x40006a4eu +#define CYREG_B1_UDB08_09_D0 0x40006a50u +#define CYREG_B1_UDB09_10_D0 0x40006a52u +#define CYREG_B1_UDB10_11_D0 0x40006a54u +#define CYREG_B1_UDB11_12_D0 0x40006a56u +#define CYREG_B1_UDB04_05_D1 0x40006a68u +#define CYREG_B1_UDB05_06_D1 0x40006a6au +#define CYREG_B1_UDB06_07_D1 0x40006a6cu +#define CYREG_B1_UDB07_08_D1 0x40006a6eu +#define CYREG_B1_UDB08_09_D1 0x40006a70u +#define CYREG_B1_UDB09_10_D1 0x40006a72u +#define CYREG_B1_UDB10_11_D1 0x40006a74u +#define CYREG_B1_UDB11_12_D1 0x40006a76u +#define CYREG_B1_UDB04_05_F0 0x40006a88u +#define CYREG_B1_UDB05_06_F0 0x40006a8au +#define CYREG_B1_UDB06_07_F0 0x40006a8cu +#define CYREG_B1_UDB07_08_F0 0x40006a8eu +#define CYREG_B1_UDB08_09_F0 0x40006a90u +#define CYREG_B1_UDB09_10_F0 0x40006a92u +#define CYREG_B1_UDB10_11_F0 0x40006a94u +#define CYREG_B1_UDB11_12_F0 0x40006a96u +#define CYREG_B1_UDB04_05_F1 0x40006aa8u +#define CYREG_B1_UDB05_06_F1 0x40006aaau +#define CYREG_B1_UDB06_07_F1 0x40006aacu +#define CYREG_B1_UDB07_08_F1 0x40006aaeu +#define CYREG_B1_UDB08_09_F1 0x40006ab0u +#define CYREG_B1_UDB09_10_F1 0x40006ab2u +#define CYREG_B1_UDB10_11_F1 0x40006ab4u +#define CYREG_B1_UDB11_12_F1 0x40006ab6u +#define CYREG_B1_UDB04_05_ST 0x40006ac8u +#define CYREG_B1_UDB05_06_ST 0x40006acau +#define CYREG_B1_UDB06_07_ST 0x40006accu +#define CYREG_B1_UDB07_08_ST 0x40006aceu +#define CYREG_B1_UDB08_09_ST 0x40006ad0u +#define CYREG_B1_UDB09_10_ST 0x40006ad2u +#define CYREG_B1_UDB10_11_ST 0x40006ad4u +#define CYREG_B1_UDB11_12_ST 0x40006ad6u +#define CYREG_B1_UDB04_05_CTL 0x40006ae8u +#define CYREG_B1_UDB05_06_CTL 0x40006aeau +#define CYREG_B1_UDB06_07_CTL 0x40006aecu +#define CYREG_B1_UDB07_08_CTL 0x40006aeeu +#define CYREG_B1_UDB08_09_CTL 0x40006af0u +#define CYREG_B1_UDB09_10_CTL 0x40006af2u +#define CYREG_B1_UDB10_11_CTL 0x40006af4u +#define CYREG_B1_UDB11_12_CTL 0x40006af6u +#define CYREG_B1_UDB04_05_MSK 0x40006b08u +#define CYREG_B1_UDB05_06_MSK 0x40006b0au +#define CYREG_B1_UDB06_07_MSK 0x40006b0cu +#define CYREG_B1_UDB07_08_MSK 0x40006b0eu +#define CYREG_B1_UDB08_09_MSK 0x40006b10u +#define CYREG_B1_UDB09_10_MSK 0x40006b12u +#define CYREG_B1_UDB10_11_MSK 0x40006b14u +#define CYREG_B1_UDB11_12_MSK 0x40006b16u +#define CYREG_B1_UDB04_05_ACTL 0x40006b28u +#define CYREG_B1_UDB05_06_ACTL 0x40006b2au +#define CYREG_B1_UDB06_07_ACTL 0x40006b2cu +#define CYREG_B1_UDB07_08_ACTL 0x40006b2eu +#define CYREG_B1_UDB08_09_ACTL 0x40006b30u +#define CYREG_B1_UDB09_10_ACTL 0x40006b32u +#define CYREG_B1_UDB10_11_ACTL 0x40006b34u +#define CYREG_B1_UDB11_12_ACTL 0x40006b36u +#define CYREG_B1_UDB04_05_MC 0x40006b48u +#define CYREG_B1_UDB05_06_MC 0x40006b4au +#define CYREG_B1_UDB06_07_MC 0x40006b4cu +#define CYREG_B1_UDB07_08_MC 0x40006b4eu +#define CYREG_B1_UDB08_09_MC 0x40006b50u +#define CYREG_B1_UDB09_10_MC 0x40006b52u +#define CYREG_B1_UDB10_11_MC 0x40006b54u +#define CYREG_B1_UDB11_12_MC 0x40006b56u +#define CYDEV_PHUB_BASE 0x40007000u +#define CYDEV_PHUB_SIZE 0x00000c00u +#define CYREG_PHUB_CFG 0x40007000u +#define CYREG_PHUB_ERR 0x40007004u +#define CYREG_PHUB_ERR_ADR 0x40007008u +#define CYDEV_PHUB_CH0_BASE 0x40007010u +#define CYDEV_PHUB_CH0_SIZE 0x0000000cu +#define CYREG_PHUB_CH0_BASIC_CFG 0x40007010u +#define CYREG_PHUB_CH0_ACTION 0x40007014u +#define CYREG_PHUB_CH0_BASIC_STATUS 0x40007018u +#define CYDEV_PHUB_CH1_BASE 0x40007020u +#define CYDEV_PHUB_CH1_SIZE 0x0000000cu +#define CYREG_PHUB_CH1_BASIC_CFG 0x40007020u +#define CYREG_PHUB_CH1_ACTION 0x40007024u +#define CYREG_PHUB_CH1_BASIC_STATUS 0x40007028u +#define CYDEV_PHUB_CH2_BASE 0x40007030u +#define CYDEV_PHUB_CH2_SIZE 0x0000000cu +#define CYREG_PHUB_CH2_BASIC_CFG 0x40007030u +#define CYREG_PHUB_CH2_ACTION 0x40007034u +#define CYREG_PHUB_CH2_BASIC_STATUS 0x40007038u +#define CYDEV_PHUB_CH3_BASE 0x40007040u +#define CYDEV_PHUB_CH3_SIZE 0x0000000cu +#define CYREG_PHUB_CH3_BASIC_CFG 0x40007040u +#define CYREG_PHUB_CH3_ACTION 0x40007044u +#define CYREG_PHUB_CH3_BASIC_STATUS 0x40007048u +#define CYDEV_PHUB_CH4_BASE 0x40007050u +#define CYDEV_PHUB_CH4_SIZE 0x0000000cu +#define CYREG_PHUB_CH4_BASIC_CFG 0x40007050u +#define CYREG_PHUB_CH4_ACTION 0x40007054u +#define CYREG_PHUB_CH4_BASIC_STATUS 0x40007058u +#define CYDEV_PHUB_CH5_BASE 0x40007060u +#define CYDEV_PHUB_CH5_SIZE 0x0000000cu +#define CYREG_PHUB_CH5_BASIC_CFG 0x40007060u +#define CYREG_PHUB_CH5_ACTION 0x40007064u +#define CYREG_PHUB_CH5_BASIC_STATUS 0x40007068u +#define CYDEV_PHUB_CH6_BASE 0x40007070u +#define CYDEV_PHUB_CH6_SIZE 0x0000000cu +#define CYREG_PHUB_CH6_BASIC_CFG 0x40007070u +#define CYREG_PHUB_CH6_ACTION 0x40007074u +#define CYREG_PHUB_CH6_BASIC_STATUS 0x40007078u +#define CYDEV_PHUB_CH7_BASE 0x40007080u +#define CYDEV_PHUB_CH7_SIZE 0x0000000cu +#define CYREG_PHUB_CH7_BASIC_CFG 0x40007080u +#define CYREG_PHUB_CH7_ACTION 0x40007084u +#define CYREG_PHUB_CH7_BASIC_STATUS 0x40007088u +#define CYDEV_PHUB_CH8_BASE 0x40007090u +#define CYDEV_PHUB_CH8_SIZE 0x0000000cu +#define CYREG_PHUB_CH8_BASIC_CFG 0x40007090u +#define CYREG_PHUB_CH8_ACTION 0x40007094u +#define CYREG_PHUB_CH8_BASIC_STATUS 0x40007098u +#define CYDEV_PHUB_CH9_BASE 0x400070a0u +#define CYDEV_PHUB_CH9_SIZE 0x0000000cu +#define CYREG_PHUB_CH9_BASIC_CFG 0x400070a0u +#define CYREG_PHUB_CH9_ACTION 0x400070a4u +#define CYREG_PHUB_CH9_BASIC_STATUS 0x400070a8u +#define CYDEV_PHUB_CH10_BASE 0x400070b0u +#define CYDEV_PHUB_CH10_SIZE 0x0000000cu +#define CYREG_PHUB_CH10_BASIC_CFG 0x400070b0u +#define CYREG_PHUB_CH10_ACTION 0x400070b4u +#define CYREG_PHUB_CH10_BASIC_STATUS 0x400070b8u +#define CYDEV_PHUB_CH11_BASE 0x400070c0u +#define CYDEV_PHUB_CH11_SIZE 0x0000000cu +#define CYREG_PHUB_CH11_BASIC_CFG 0x400070c0u +#define CYREG_PHUB_CH11_ACTION 0x400070c4u +#define CYREG_PHUB_CH11_BASIC_STATUS 0x400070c8u +#define CYDEV_PHUB_CH12_BASE 0x400070d0u +#define CYDEV_PHUB_CH12_SIZE 0x0000000cu +#define CYREG_PHUB_CH12_BASIC_CFG 0x400070d0u +#define CYREG_PHUB_CH12_ACTION 0x400070d4u +#define CYREG_PHUB_CH12_BASIC_STATUS 0x400070d8u +#define CYDEV_PHUB_CH13_BASE 0x400070e0u +#define CYDEV_PHUB_CH13_SIZE 0x0000000cu +#define CYREG_PHUB_CH13_BASIC_CFG 0x400070e0u +#define CYREG_PHUB_CH13_ACTION 0x400070e4u +#define CYREG_PHUB_CH13_BASIC_STATUS 0x400070e8u +#define CYDEV_PHUB_CH14_BASE 0x400070f0u +#define CYDEV_PHUB_CH14_SIZE 0x0000000cu +#define CYREG_PHUB_CH14_BASIC_CFG 0x400070f0u +#define CYREG_PHUB_CH14_ACTION 0x400070f4u +#define CYREG_PHUB_CH14_BASIC_STATUS 0x400070f8u +#define CYDEV_PHUB_CH15_BASE 0x40007100u +#define CYDEV_PHUB_CH15_SIZE 0x0000000cu +#define CYREG_PHUB_CH15_BASIC_CFG 0x40007100u +#define CYREG_PHUB_CH15_ACTION 0x40007104u +#define CYREG_PHUB_CH15_BASIC_STATUS 0x40007108u +#define CYDEV_PHUB_CH16_BASE 0x40007110u +#define CYDEV_PHUB_CH16_SIZE 0x0000000cu +#define CYREG_PHUB_CH16_BASIC_CFG 0x40007110u +#define CYREG_PHUB_CH16_ACTION 0x40007114u +#define CYREG_PHUB_CH16_BASIC_STATUS 0x40007118u +#define CYDEV_PHUB_CH17_BASE 0x40007120u +#define CYDEV_PHUB_CH17_SIZE 0x0000000cu +#define CYREG_PHUB_CH17_BASIC_CFG 0x40007120u +#define CYREG_PHUB_CH17_ACTION 0x40007124u +#define CYREG_PHUB_CH17_BASIC_STATUS 0x40007128u +#define CYDEV_PHUB_CH18_BASE 0x40007130u +#define CYDEV_PHUB_CH18_SIZE 0x0000000cu +#define CYREG_PHUB_CH18_BASIC_CFG 0x40007130u +#define CYREG_PHUB_CH18_ACTION 0x40007134u +#define CYREG_PHUB_CH18_BASIC_STATUS 0x40007138u +#define CYDEV_PHUB_CH19_BASE 0x40007140u +#define CYDEV_PHUB_CH19_SIZE 0x0000000cu +#define CYREG_PHUB_CH19_BASIC_CFG 0x40007140u +#define CYREG_PHUB_CH19_ACTION 0x40007144u +#define CYREG_PHUB_CH19_BASIC_STATUS 0x40007148u +#define CYDEV_PHUB_CH20_BASE 0x40007150u +#define CYDEV_PHUB_CH20_SIZE 0x0000000cu +#define CYREG_PHUB_CH20_BASIC_CFG 0x40007150u +#define CYREG_PHUB_CH20_ACTION 0x40007154u +#define CYREG_PHUB_CH20_BASIC_STATUS 0x40007158u +#define CYDEV_PHUB_CH21_BASE 0x40007160u +#define CYDEV_PHUB_CH21_SIZE 0x0000000cu +#define CYREG_PHUB_CH21_BASIC_CFG 0x40007160u +#define CYREG_PHUB_CH21_ACTION 0x40007164u +#define CYREG_PHUB_CH21_BASIC_STATUS 0x40007168u +#define CYDEV_PHUB_CH22_BASE 0x40007170u +#define CYDEV_PHUB_CH22_SIZE 0x0000000cu +#define CYREG_PHUB_CH22_BASIC_CFG 0x40007170u +#define CYREG_PHUB_CH22_ACTION 0x40007174u +#define CYREG_PHUB_CH22_BASIC_STATUS 0x40007178u +#define CYDEV_PHUB_CH23_BASE 0x40007180u +#define CYDEV_PHUB_CH23_SIZE 0x0000000cu +#define CYREG_PHUB_CH23_BASIC_CFG 0x40007180u +#define CYREG_PHUB_CH23_ACTION 0x40007184u +#define CYREG_PHUB_CH23_BASIC_STATUS 0x40007188u +#define CYDEV_PHUB_CFGMEM0_BASE 0x40007600u +#define CYDEV_PHUB_CFGMEM0_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM0_CFG0 0x40007600u +#define CYREG_PHUB_CFGMEM0_CFG1 0x40007604u +#define CYDEV_PHUB_CFGMEM1_BASE 0x40007608u +#define CYDEV_PHUB_CFGMEM1_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM1_CFG0 0x40007608u +#define CYREG_PHUB_CFGMEM1_CFG1 0x4000760cu +#define CYDEV_PHUB_CFGMEM2_BASE 0x40007610u +#define CYDEV_PHUB_CFGMEM2_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM2_CFG0 0x40007610u +#define CYREG_PHUB_CFGMEM2_CFG1 0x40007614u +#define CYDEV_PHUB_CFGMEM3_BASE 0x40007618u +#define CYDEV_PHUB_CFGMEM3_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM3_CFG0 0x40007618u +#define CYREG_PHUB_CFGMEM3_CFG1 0x4000761cu +#define CYDEV_PHUB_CFGMEM4_BASE 0x40007620u +#define CYDEV_PHUB_CFGMEM4_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM4_CFG0 0x40007620u +#define CYREG_PHUB_CFGMEM4_CFG1 0x40007624u +#define CYDEV_PHUB_CFGMEM5_BASE 0x40007628u +#define CYDEV_PHUB_CFGMEM5_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM5_CFG0 0x40007628u +#define CYREG_PHUB_CFGMEM5_CFG1 0x4000762cu +#define CYDEV_PHUB_CFGMEM6_BASE 0x40007630u +#define CYDEV_PHUB_CFGMEM6_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM6_CFG0 0x40007630u +#define CYREG_PHUB_CFGMEM6_CFG1 0x40007634u +#define CYDEV_PHUB_CFGMEM7_BASE 0x40007638u +#define CYDEV_PHUB_CFGMEM7_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM7_CFG0 0x40007638u +#define CYREG_PHUB_CFGMEM7_CFG1 0x4000763cu +#define CYDEV_PHUB_CFGMEM8_BASE 0x40007640u +#define CYDEV_PHUB_CFGMEM8_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM8_CFG0 0x40007640u +#define CYREG_PHUB_CFGMEM8_CFG1 0x40007644u +#define CYDEV_PHUB_CFGMEM9_BASE 0x40007648u +#define CYDEV_PHUB_CFGMEM9_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM9_CFG0 0x40007648u +#define CYREG_PHUB_CFGMEM9_CFG1 0x4000764cu +#define CYDEV_PHUB_CFGMEM10_BASE 0x40007650u +#define CYDEV_PHUB_CFGMEM10_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM10_CFG0 0x40007650u +#define CYREG_PHUB_CFGMEM10_CFG1 0x40007654u +#define CYDEV_PHUB_CFGMEM11_BASE 0x40007658u +#define CYDEV_PHUB_CFGMEM11_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM11_CFG0 0x40007658u +#define CYREG_PHUB_CFGMEM11_CFG1 0x4000765cu +#define CYDEV_PHUB_CFGMEM12_BASE 0x40007660u +#define CYDEV_PHUB_CFGMEM12_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM12_CFG0 0x40007660u +#define CYREG_PHUB_CFGMEM12_CFG1 0x40007664u +#define CYDEV_PHUB_CFGMEM13_BASE 0x40007668u +#define CYDEV_PHUB_CFGMEM13_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM13_CFG0 0x40007668u +#define CYREG_PHUB_CFGMEM13_CFG1 0x4000766cu +#define CYDEV_PHUB_CFGMEM14_BASE 0x40007670u +#define CYDEV_PHUB_CFGMEM14_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM14_CFG0 0x40007670u +#define CYREG_PHUB_CFGMEM14_CFG1 0x40007674u +#define CYDEV_PHUB_CFGMEM15_BASE 0x40007678u +#define CYDEV_PHUB_CFGMEM15_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM15_CFG0 0x40007678u +#define CYREG_PHUB_CFGMEM15_CFG1 0x4000767cu +#define CYDEV_PHUB_CFGMEM16_BASE 0x40007680u +#define CYDEV_PHUB_CFGMEM16_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM16_CFG0 0x40007680u +#define CYREG_PHUB_CFGMEM16_CFG1 0x40007684u +#define CYDEV_PHUB_CFGMEM17_BASE 0x40007688u +#define CYDEV_PHUB_CFGMEM17_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM17_CFG0 0x40007688u +#define CYREG_PHUB_CFGMEM17_CFG1 0x4000768cu +#define CYDEV_PHUB_CFGMEM18_BASE 0x40007690u +#define CYDEV_PHUB_CFGMEM18_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM18_CFG0 0x40007690u +#define CYREG_PHUB_CFGMEM18_CFG1 0x40007694u +#define CYDEV_PHUB_CFGMEM19_BASE 0x40007698u +#define CYDEV_PHUB_CFGMEM19_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM19_CFG0 0x40007698u +#define CYREG_PHUB_CFGMEM19_CFG1 0x4000769cu +#define CYDEV_PHUB_CFGMEM20_BASE 0x400076a0u +#define CYDEV_PHUB_CFGMEM20_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM20_CFG0 0x400076a0u +#define CYREG_PHUB_CFGMEM20_CFG1 0x400076a4u +#define CYDEV_PHUB_CFGMEM21_BASE 0x400076a8u +#define CYDEV_PHUB_CFGMEM21_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM21_CFG0 0x400076a8u +#define CYREG_PHUB_CFGMEM21_CFG1 0x400076acu +#define CYDEV_PHUB_CFGMEM22_BASE 0x400076b0u +#define CYDEV_PHUB_CFGMEM22_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM22_CFG0 0x400076b0u +#define CYREG_PHUB_CFGMEM22_CFG1 0x400076b4u +#define CYDEV_PHUB_CFGMEM23_BASE 0x400076b8u +#define CYDEV_PHUB_CFGMEM23_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM23_CFG0 0x400076b8u +#define CYREG_PHUB_CFGMEM23_CFG1 0x400076bcu +#define CYDEV_PHUB_TDMEM0_BASE 0x40007800u +#define CYDEV_PHUB_TDMEM0_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM0_ORIG_TD0 0x40007800u +#define CYREG_PHUB_TDMEM0_ORIG_TD1 0x40007804u +#define CYDEV_PHUB_TDMEM1_BASE 0x40007808u +#define CYDEV_PHUB_TDMEM1_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM1_ORIG_TD0 0x40007808u +#define CYREG_PHUB_TDMEM1_ORIG_TD1 0x4000780cu +#define CYDEV_PHUB_TDMEM2_BASE 0x40007810u +#define CYDEV_PHUB_TDMEM2_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM2_ORIG_TD0 0x40007810u +#define CYREG_PHUB_TDMEM2_ORIG_TD1 0x40007814u +#define CYDEV_PHUB_TDMEM3_BASE 0x40007818u +#define CYDEV_PHUB_TDMEM3_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM3_ORIG_TD0 0x40007818u +#define CYREG_PHUB_TDMEM3_ORIG_TD1 0x4000781cu +#define CYDEV_PHUB_TDMEM4_BASE 0x40007820u +#define CYDEV_PHUB_TDMEM4_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM4_ORIG_TD0 0x40007820u +#define CYREG_PHUB_TDMEM4_ORIG_TD1 0x40007824u +#define CYDEV_PHUB_TDMEM5_BASE 0x40007828u +#define CYDEV_PHUB_TDMEM5_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM5_ORIG_TD0 0x40007828u +#define CYREG_PHUB_TDMEM5_ORIG_TD1 0x4000782cu +#define CYDEV_PHUB_TDMEM6_BASE 0x40007830u +#define CYDEV_PHUB_TDMEM6_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM6_ORIG_TD0 0x40007830u +#define CYREG_PHUB_TDMEM6_ORIG_TD1 0x40007834u +#define CYDEV_PHUB_TDMEM7_BASE 0x40007838u +#define CYDEV_PHUB_TDMEM7_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM7_ORIG_TD0 0x40007838u +#define CYREG_PHUB_TDMEM7_ORIG_TD1 0x4000783cu +#define CYDEV_PHUB_TDMEM8_BASE 0x40007840u +#define CYDEV_PHUB_TDMEM8_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM8_ORIG_TD0 0x40007840u +#define CYREG_PHUB_TDMEM8_ORIG_TD1 0x40007844u +#define CYDEV_PHUB_TDMEM9_BASE 0x40007848u +#define CYDEV_PHUB_TDMEM9_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM9_ORIG_TD0 0x40007848u +#define CYREG_PHUB_TDMEM9_ORIG_TD1 0x4000784cu +#define CYDEV_PHUB_TDMEM10_BASE 0x40007850u +#define CYDEV_PHUB_TDMEM10_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM10_ORIG_TD0 0x40007850u +#define CYREG_PHUB_TDMEM10_ORIG_TD1 0x40007854u +#define CYDEV_PHUB_TDMEM11_BASE 0x40007858u +#define CYDEV_PHUB_TDMEM11_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM11_ORIG_TD0 0x40007858u +#define CYREG_PHUB_TDMEM11_ORIG_TD1 0x4000785cu +#define CYDEV_PHUB_TDMEM12_BASE 0x40007860u +#define CYDEV_PHUB_TDMEM12_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM12_ORIG_TD0 0x40007860u +#define CYREG_PHUB_TDMEM12_ORIG_TD1 0x40007864u +#define CYDEV_PHUB_TDMEM13_BASE 0x40007868u +#define CYDEV_PHUB_TDMEM13_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM13_ORIG_TD0 0x40007868u +#define CYREG_PHUB_TDMEM13_ORIG_TD1 0x4000786cu +#define CYDEV_PHUB_TDMEM14_BASE 0x40007870u +#define CYDEV_PHUB_TDMEM14_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM14_ORIG_TD0 0x40007870u +#define CYREG_PHUB_TDMEM14_ORIG_TD1 0x40007874u +#define CYDEV_PHUB_TDMEM15_BASE 0x40007878u +#define CYDEV_PHUB_TDMEM15_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM15_ORIG_TD0 0x40007878u +#define CYREG_PHUB_TDMEM15_ORIG_TD1 0x4000787cu +#define CYDEV_PHUB_TDMEM16_BASE 0x40007880u +#define CYDEV_PHUB_TDMEM16_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM16_ORIG_TD0 0x40007880u +#define CYREG_PHUB_TDMEM16_ORIG_TD1 0x40007884u +#define CYDEV_PHUB_TDMEM17_BASE 0x40007888u +#define CYDEV_PHUB_TDMEM17_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM17_ORIG_TD0 0x40007888u +#define CYREG_PHUB_TDMEM17_ORIG_TD1 0x4000788cu +#define CYDEV_PHUB_TDMEM18_BASE 0x40007890u +#define CYDEV_PHUB_TDMEM18_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM18_ORIG_TD0 0x40007890u +#define CYREG_PHUB_TDMEM18_ORIG_TD1 0x40007894u +#define CYDEV_PHUB_TDMEM19_BASE 0x40007898u +#define CYDEV_PHUB_TDMEM19_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM19_ORIG_TD0 0x40007898u +#define CYREG_PHUB_TDMEM19_ORIG_TD1 0x4000789cu +#define CYDEV_PHUB_TDMEM20_BASE 0x400078a0u +#define CYDEV_PHUB_TDMEM20_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM20_ORIG_TD0 0x400078a0u +#define CYREG_PHUB_TDMEM20_ORIG_TD1 0x400078a4u +#define CYDEV_PHUB_TDMEM21_BASE 0x400078a8u +#define CYDEV_PHUB_TDMEM21_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM21_ORIG_TD0 0x400078a8u +#define CYREG_PHUB_TDMEM21_ORIG_TD1 0x400078acu +#define CYDEV_PHUB_TDMEM22_BASE 0x400078b0u +#define CYDEV_PHUB_TDMEM22_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM22_ORIG_TD0 0x400078b0u +#define CYREG_PHUB_TDMEM22_ORIG_TD1 0x400078b4u +#define CYDEV_PHUB_TDMEM23_BASE 0x400078b8u +#define CYDEV_PHUB_TDMEM23_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM23_ORIG_TD0 0x400078b8u +#define CYREG_PHUB_TDMEM23_ORIG_TD1 0x400078bcu +#define CYDEV_PHUB_TDMEM24_BASE 0x400078c0u +#define CYDEV_PHUB_TDMEM24_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM24_ORIG_TD0 0x400078c0u +#define CYREG_PHUB_TDMEM24_ORIG_TD1 0x400078c4u +#define CYDEV_PHUB_TDMEM25_BASE 0x400078c8u +#define CYDEV_PHUB_TDMEM25_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM25_ORIG_TD0 0x400078c8u +#define CYREG_PHUB_TDMEM25_ORIG_TD1 0x400078ccu +#define CYDEV_PHUB_TDMEM26_BASE 0x400078d0u +#define CYDEV_PHUB_TDMEM26_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM26_ORIG_TD0 0x400078d0u +#define CYREG_PHUB_TDMEM26_ORIG_TD1 0x400078d4u +#define CYDEV_PHUB_TDMEM27_BASE 0x400078d8u +#define CYDEV_PHUB_TDMEM27_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM27_ORIG_TD0 0x400078d8u +#define CYREG_PHUB_TDMEM27_ORIG_TD1 0x400078dcu +#define CYDEV_PHUB_TDMEM28_BASE 0x400078e0u +#define CYDEV_PHUB_TDMEM28_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM28_ORIG_TD0 0x400078e0u +#define CYREG_PHUB_TDMEM28_ORIG_TD1 0x400078e4u +#define CYDEV_PHUB_TDMEM29_BASE 0x400078e8u +#define CYDEV_PHUB_TDMEM29_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM29_ORIG_TD0 0x400078e8u +#define CYREG_PHUB_TDMEM29_ORIG_TD1 0x400078ecu +#define CYDEV_PHUB_TDMEM30_BASE 0x400078f0u +#define CYDEV_PHUB_TDMEM30_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM30_ORIG_TD0 0x400078f0u +#define CYREG_PHUB_TDMEM30_ORIG_TD1 0x400078f4u +#define CYDEV_PHUB_TDMEM31_BASE 0x400078f8u +#define CYDEV_PHUB_TDMEM31_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM31_ORIG_TD0 0x400078f8u +#define CYREG_PHUB_TDMEM31_ORIG_TD1 0x400078fcu +#define CYDEV_PHUB_TDMEM32_BASE 0x40007900u +#define CYDEV_PHUB_TDMEM32_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM32_ORIG_TD0 0x40007900u +#define CYREG_PHUB_TDMEM32_ORIG_TD1 0x40007904u +#define CYDEV_PHUB_TDMEM33_BASE 0x40007908u +#define CYDEV_PHUB_TDMEM33_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM33_ORIG_TD0 0x40007908u +#define CYREG_PHUB_TDMEM33_ORIG_TD1 0x4000790cu +#define CYDEV_PHUB_TDMEM34_BASE 0x40007910u +#define CYDEV_PHUB_TDMEM34_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM34_ORIG_TD0 0x40007910u +#define CYREG_PHUB_TDMEM34_ORIG_TD1 0x40007914u +#define CYDEV_PHUB_TDMEM35_BASE 0x40007918u +#define CYDEV_PHUB_TDMEM35_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM35_ORIG_TD0 0x40007918u +#define CYREG_PHUB_TDMEM35_ORIG_TD1 0x4000791cu +#define CYDEV_PHUB_TDMEM36_BASE 0x40007920u +#define CYDEV_PHUB_TDMEM36_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM36_ORIG_TD0 0x40007920u +#define CYREG_PHUB_TDMEM36_ORIG_TD1 0x40007924u +#define CYDEV_PHUB_TDMEM37_BASE 0x40007928u +#define CYDEV_PHUB_TDMEM37_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM37_ORIG_TD0 0x40007928u +#define CYREG_PHUB_TDMEM37_ORIG_TD1 0x4000792cu +#define CYDEV_PHUB_TDMEM38_BASE 0x40007930u +#define CYDEV_PHUB_TDMEM38_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM38_ORIG_TD0 0x40007930u +#define CYREG_PHUB_TDMEM38_ORIG_TD1 0x40007934u +#define CYDEV_PHUB_TDMEM39_BASE 0x40007938u +#define CYDEV_PHUB_TDMEM39_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM39_ORIG_TD0 0x40007938u +#define CYREG_PHUB_TDMEM39_ORIG_TD1 0x4000793cu +#define CYDEV_PHUB_TDMEM40_BASE 0x40007940u +#define CYDEV_PHUB_TDMEM40_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM40_ORIG_TD0 0x40007940u +#define CYREG_PHUB_TDMEM40_ORIG_TD1 0x40007944u +#define CYDEV_PHUB_TDMEM41_BASE 0x40007948u +#define CYDEV_PHUB_TDMEM41_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM41_ORIG_TD0 0x40007948u +#define CYREG_PHUB_TDMEM41_ORIG_TD1 0x4000794cu +#define CYDEV_PHUB_TDMEM42_BASE 0x40007950u +#define CYDEV_PHUB_TDMEM42_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM42_ORIG_TD0 0x40007950u +#define CYREG_PHUB_TDMEM42_ORIG_TD1 0x40007954u +#define CYDEV_PHUB_TDMEM43_BASE 0x40007958u +#define CYDEV_PHUB_TDMEM43_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM43_ORIG_TD0 0x40007958u +#define CYREG_PHUB_TDMEM43_ORIG_TD1 0x4000795cu +#define CYDEV_PHUB_TDMEM44_BASE 0x40007960u +#define CYDEV_PHUB_TDMEM44_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM44_ORIG_TD0 0x40007960u +#define CYREG_PHUB_TDMEM44_ORIG_TD1 0x40007964u +#define CYDEV_PHUB_TDMEM45_BASE 0x40007968u +#define CYDEV_PHUB_TDMEM45_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM45_ORIG_TD0 0x40007968u +#define CYREG_PHUB_TDMEM45_ORIG_TD1 0x4000796cu +#define CYDEV_PHUB_TDMEM46_BASE 0x40007970u +#define CYDEV_PHUB_TDMEM46_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM46_ORIG_TD0 0x40007970u +#define CYREG_PHUB_TDMEM46_ORIG_TD1 0x40007974u +#define CYDEV_PHUB_TDMEM47_BASE 0x40007978u +#define CYDEV_PHUB_TDMEM47_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM47_ORIG_TD0 0x40007978u +#define CYREG_PHUB_TDMEM47_ORIG_TD1 0x4000797cu +#define CYDEV_PHUB_TDMEM48_BASE 0x40007980u +#define CYDEV_PHUB_TDMEM48_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM48_ORIG_TD0 0x40007980u +#define CYREG_PHUB_TDMEM48_ORIG_TD1 0x40007984u +#define CYDEV_PHUB_TDMEM49_BASE 0x40007988u +#define CYDEV_PHUB_TDMEM49_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM49_ORIG_TD0 0x40007988u +#define CYREG_PHUB_TDMEM49_ORIG_TD1 0x4000798cu +#define CYDEV_PHUB_TDMEM50_BASE 0x40007990u +#define CYDEV_PHUB_TDMEM50_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM50_ORIG_TD0 0x40007990u +#define CYREG_PHUB_TDMEM50_ORIG_TD1 0x40007994u +#define CYDEV_PHUB_TDMEM51_BASE 0x40007998u +#define CYDEV_PHUB_TDMEM51_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM51_ORIG_TD0 0x40007998u +#define CYREG_PHUB_TDMEM51_ORIG_TD1 0x4000799cu +#define CYDEV_PHUB_TDMEM52_BASE 0x400079a0u +#define CYDEV_PHUB_TDMEM52_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM52_ORIG_TD0 0x400079a0u +#define CYREG_PHUB_TDMEM52_ORIG_TD1 0x400079a4u +#define CYDEV_PHUB_TDMEM53_BASE 0x400079a8u +#define CYDEV_PHUB_TDMEM53_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM53_ORIG_TD0 0x400079a8u +#define CYREG_PHUB_TDMEM53_ORIG_TD1 0x400079acu +#define CYDEV_PHUB_TDMEM54_BASE 0x400079b0u +#define CYDEV_PHUB_TDMEM54_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM54_ORIG_TD0 0x400079b0u +#define CYREG_PHUB_TDMEM54_ORIG_TD1 0x400079b4u +#define CYDEV_PHUB_TDMEM55_BASE 0x400079b8u +#define CYDEV_PHUB_TDMEM55_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM55_ORIG_TD0 0x400079b8u +#define CYREG_PHUB_TDMEM55_ORIG_TD1 0x400079bcu +#define CYDEV_PHUB_TDMEM56_BASE 0x400079c0u +#define CYDEV_PHUB_TDMEM56_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM56_ORIG_TD0 0x400079c0u +#define CYREG_PHUB_TDMEM56_ORIG_TD1 0x400079c4u +#define CYDEV_PHUB_TDMEM57_BASE 0x400079c8u +#define CYDEV_PHUB_TDMEM57_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM57_ORIG_TD0 0x400079c8u +#define CYREG_PHUB_TDMEM57_ORIG_TD1 0x400079ccu +#define CYDEV_PHUB_TDMEM58_BASE 0x400079d0u +#define CYDEV_PHUB_TDMEM58_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM58_ORIG_TD0 0x400079d0u +#define CYREG_PHUB_TDMEM58_ORIG_TD1 0x400079d4u +#define CYDEV_PHUB_TDMEM59_BASE 0x400079d8u +#define CYDEV_PHUB_TDMEM59_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM59_ORIG_TD0 0x400079d8u +#define CYREG_PHUB_TDMEM59_ORIG_TD1 0x400079dcu +#define CYDEV_PHUB_TDMEM60_BASE 0x400079e0u +#define CYDEV_PHUB_TDMEM60_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM60_ORIG_TD0 0x400079e0u +#define CYREG_PHUB_TDMEM60_ORIG_TD1 0x400079e4u +#define CYDEV_PHUB_TDMEM61_BASE 0x400079e8u +#define CYDEV_PHUB_TDMEM61_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM61_ORIG_TD0 0x400079e8u +#define CYREG_PHUB_TDMEM61_ORIG_TD1 0x400079ecu +#define CYDEV_PHUB_TDMEM62_BASE 0x400079f0u +#define CYDEV_PHUB_TDMEM62_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM62_ORIG_TD0 0x400079f0u +#define CYREG_PHUB_TDMEM62_ORIG_TD1 0x400079f4u +#define CYDEV_PHUB_TDMEM63_BASE 0x400079f8u +#define CYDEV_PHUB_TDMEM63_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM63_ORIG_TD0 0x400079f8u +#define CYREG_PHUB_TDMEM63_ORIG_TD1 0x400079fcu +#define CYDEV_PHUB_TDMEM64_BASE 0x40007a00u +#define CYDEV_PHUB_TDMEM64_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM64_ORIG_TD0 0x40007a00u +#define CYREG_PHUB_TDMEM64_ORIG_TD1 0x40007a04u +#define CYDEV_PHUB_TDMEM65_BASE 0x40007a08u +#define CYDEV_PHUB_TDMEM65_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM65_ORIG_TD0 0x40007a08u +#define CYREG_PHUB_TDMEM65_ORIG_TD1 0x40007a0cu +#define CYDEV_PHUB_TDMEM66_BASE 0x40007a10u +#define CYDEV_PHUB_TDMEM66_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM66_ORIG_TD0 0x40007a10u +#define CYREG_PHUB_TDMEM66_ORIG_TD1 0x40007a14u +#define CYDEV_PHUB_TDMEM67_BASE 0x40007a18u +#define CYDEV_PHUB_TDMEM67_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM67_ORIG_TD0 0x40007a18u +#define CYREG_PHUB_TDMEM67_ORIG_TD1 0x40007a1cu +#define CYDEV_PHUB_TDMEM68_BASE 0x40007a20u +#define CYDEV_PHUB_TDMEM68_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM68_ORIG_TD0 0x40007a20u +#define CYREG_PHUB_TDMEM68_ORIG_TD1 0x40007a24u +#define CYDEV_PHUB_TDMEM69_BASE 0x40007a28u +#define CYDEV_PHUB_TDMEM69_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM69_ORIG_TD0 0x40007a28u +#define CYREG_PHUB_TDMEM69_ORIG_TD1 0x40007a2cu +#define CYDEV_PHUB_TDMEM70_BASE 0x40007a30u +#define CYDEV_PHUB_TDMEM70_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM70_ORIG_TD0 0x40007a30u +#define CYREG_PHUB_TDMEM70_ORIG_TD1 0x40007a34u +#define CYDEV_PHUB_TDMEM71_BASE 0x40007a38u +#define CYDEV_PHUB_TDMEM71_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM71_ORIG_TD0 0x40007a38u +#define CYREG_PHUB_TDMEM71_ORIG_TD1 0x40007a3cu +#define CYDEV_PHUB_TDMEM72_BASE 0x40007a40u +#define CYDEV_PHUB_TDMEM72_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM72_ORIG_TD0 0x40007a40u +#define CYREG_PHUB_TDMEM72_ORIG_TD1 0x40007a44u +#define CYDEV_PHUB_TDMEM73_BASE 0x40007a48u +#define CYDEV_PHUB_TDMEM73_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM73_ORIG_TD0 0x40007a48u +#define CYREG_PHUB_TDMEM73_ORIG_TD1 0x40007a4cu +#define CYDEV_PHUB_TDMEM74_BASE 0x40007a50u +#define CYDEV_PHUB_TDMEM74_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM74_ORIG_TD0 0x40007a50u +#define CYREG_PHUB_TDMEM74_ORIG_TD1 0x40007a54u +#define CYDEV_PHUB_TDMEM75_BASE 0x40007a58u +#define CYDEV_PHUB_TDMEM75_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM75_ORIG_TD0 0x40007a58u +#define CYREG_PHUB_TDMEM75_ORIG_TD1 0x40007a5cu +#define CYDEV_PHUB_TDMEM76_BASE 0x40007a60u +#define CYDEV_PHUB_TDMEM76_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM76_ORIG_TD0 0x40007a60u +#define CYREG_PHUB_TDMEM76_ORIG_TD1 0x40007a64u +#define CYDEV_PHUB_TDMEM77_BASE 0x40007a68u +#define CYDEV_PHUB_TDMEM77_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM77_ORIG_TD0 0x40007a68u +#define CYREG_PHUB_TDMEM77_ORIG_TD1 0x40007a6cu +#define CYDEV_PHUB_TDMEM78_BASE 0x40007a70u +#define CYDEV_PHUB_TDMEM78_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM78_ORIG_TD0 0x40007a70u +#define CYREG_PHUB_TDMEM78_ORIG_TD1 0x40007a74u +#define CYDEV_PHUB_TDMEM79_BASE 0x40007a78u +#define CYDEV_PHUB_TDMEM79_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM79_ORIG_TD0 0x40007a78u +#define CYREG_PHUB_TDMEM79_ORIG_TD1 0x40007a7cu +#define CYDEV_PHUB_TDMEM80_BASE 0x40007a80u +#define CYDEV_PHUB_TDMEM80_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM80_ORIG_TD0 0x40007a80u +#define CYREG_PHUB_TDMEM80_ORIG_TD1 0x40007a84u +#define CYDEV_PHUB_TDMEM81_BASE 0x40007a88u +#define CYDEV_PHUB_TDMEM81_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM81_ORIG_TD0 0x40007a88u +#define CYREG_PHUB_TDMEM81_ORIG_TD1 0x40007a8cu +#define CYDEV_PHUB_TDMEM82_BASE 0x40007a90u +#define CYDEV_PHUB_TDMEM82_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM82_ORIG_TD0 0x40007a90u +#define CYREG_PHUB_TDMEM82_ORIG_TD1 0x40007a94u +#define CYDEV_PHUB_TDMEM83_BASE 0x40007a98u +#define CYDEV_PHUB_TDMEM83_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM83_ORIG_TD0 0x40007a98u +#define CYREG_PHUB_TDMEM83_ORIG_TD1 0x40007a9cu +#define CYDEV_PHUB_TDMEM84_BASE 0x40007aa0u +#define CYDEV_PHUB_TDMEM84_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM84_ORIG_TD0 0x40007aa0u +#define CYREG_PHUB_TDMEM84_ORIG_TD1 0x40007aa4u +#define CYDEV_PHUB_TDMEM85_BASE 0x40007aa8u +#define CYDEV_PHUB_TDMEM85_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM85_ORIG_TD0 0x40007aa8u +#define CYREG_PHUB_TDMEM85_ORIG_TD1 0x40007aacu +#define CYDEV_PHUB_TDMEM86_BASE 0x40007ab0u +#define CYDEV_PHUB_TDMEM86_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM86_ORIG_TD0 0x40007ab0u +#define CYREG_PHUB_TDMEM86_ORIG_TD1 0x40007ab4u +#define CYDEV_PHUB_TDMEM87_BASE 0x40007ab8u +#define CYDEV_PHUB_TDMEM87_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM87_ORIG_TD0 0x40007ab8u +#define CYREG_PHUB_TDMEM87_ORIG_TD1 0x40007abcu +#define CYDEV_PHUB_TDMEM88_BASE 0x40007ac0u +#define CYDEV_PHUB_TDMEM88_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM88_ORIG_TD0 0x40007ac0u +#define CYREG_PHUB_TDMEM88_ORIG_TD1 0x40007ac4u +#define CYDEV_PHUB_TDMEM89_BASE 0x40007ac8u +#define CYDEV_PHUB_TDMEM89_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM89_ORIG_TD0 0x40007ac8u +#define CYREG_PHUB_TDMEM89_ORIG_TD1 0x40007accu +#define CYDEV_PHUB_TDMEM90_BASE 0x40007ad0u +#define CYDEV_PHUB_TDMEM90_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM90_ORIG_TD0 0x40007ad0u +#define CYREG_PHUB_TDMEM90_ORIG_TD1 0x40007ad4u +#define CYDEV_PHUB_TDMEM91_BASE 0x40007ad8u +#define CYDEV_PHUB_TDMEM91_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM91_ORIG_TD0 0x40007ad8u +#define CYREG_PHUB_TDMEM91_ORIG_TD1 0x40007adcu +#define CYDEV_PHUB_TDMEM92_BASE 0x40007ae0u +#define CYDEV_PHUB_TDMEM92_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM92_ORIG_TD0 0x40007ae0u +#define CYREG_PHUB_TDMEM92_ORIG_TD1 0x40007ae4u +#define CYDEV_PHUB_TDMEM93_BASE 0x40007ae8u +#define CYDEV_PHUB_TDMEM93_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM93_ORIG_TD0 0x40007ae8u +#define CYREG_PHUB_TDMEM93_ORIG_TD1 0x40007aecu +#define CYDEV_PHUB_TDMEM94_BASE 0x40007af0u +#define CYDEV_PHUB_TDMEM94_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM94_ORIG_TD0 0x40007af0u +#define CYREG_PHUB_TDMEM94_ORIG_TD1 0x40007af4u +#define CYDEV_PHUB_TDMEM95_BASE 0x40007af8u +#define CYDEV_PHUB_TDMEM95_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM95_ORIG_TD0 0x40007af8u +#define CYREG_PHUB_TDMEM95_ORIG_TD1 0x40007afcu +#define CYDEV_PHUB_TDMEM96_BASE 0x40007b00u +#define CYDEV_PHUB_TDMEM96_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM96_ORIG_TD0 0x40007b00u +#define CYREG_PHUB_TDMEM96_ORIG_TD1 0x40007b04u +#define CYDEV_PHUB_TDMEM97_BASE 0x40007b08u +#define CYDEV_PHUB_TDMEM97_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM97_ORIG_TD0 0x40007b08u +#define CYREG_PHUB_TDMEM97_ORIG_TD1 0x40007b0cu +#define CYDEV_PHUB_TDMEM98_BASE 0x40007b10u +#define CYDEV_PHUB_TDMEM98_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM98_ORIG_TD0 0x40007b10u +#define CYREG_PHUB_TDMEM98_ORIG_TD1 0x40007b14u +#define CYDEV_PHUB_TDMEM99_BASE 0x40007b18u +#define CYDEV_PHUB_TDMEM99_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM99_ORIG_TD0 0x40007b18u +#define CYREG_PHUB_TDMEM99_ORIG_TD1 0x40007b1cu +#define CYDEV_PHUB_TDMEM100_BASE 0x40007b20u +#define CYDEV_PHUB_TDMEM100_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM100_ORIG_TD0 0x40007b20u +#define CYREG_PHUB_TDMEM100_ORIG_TD1 0x40007b24u +#define CYDEV_PHUB_TDMEM101_BASE 0x40007b28u +#define CYDEV_PHUB_TDMEM101_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM101_ORIG_TD0 0x40007b28u +#define CYREG_PHUB_TDMEM101_ORIG_TD1 0x40007b2cu +#define CYDEV_PHUB_TDMEM102_BASE 0x40007b30u +#define CYDEV_PHUB_TDMEM102_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM102_ORIG_TD0 0x40007b30u +#define CYREG_PHUB_TDMEM102_ORIG_TD1 0x40007b34u +#define CYDEV_PHUB_TDMEM103_BASE 0x40007b38u +#define CYDEV_PHUB_TDMEM103_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM103_ORIG_TD0 0x40007b38u +#define CYREG_PHUB_TDMEM103_ORIG_TD1 0x40007b3cu +#define CYDEV_PHUB_TDMEM104_BASE 0x40007b40u +#define CYDEV_PHUB_TDMEM104_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM104_ORIG_TD0 0x40007b40u +#define CYREG_PHUB_TDMEM104_ORIG_TD1 0x40007b44u +#define CYDEV_PHUB_TDMEM105_BASE 0x40007b48u +#define CYDEV_PHUB_TDMEM105_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM105_ORIG_TD0 0x40007b48u +#define CYREG_PHUB_TDMEM105_ORIG_TD1 0x40007b4cu +#define CYDEV_PHUB_TDMEM106_BASE 0x40007b50u +#define CYDEV_PHUB_TDMEM106_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM106_ORIG_TD0 0x40007b50u +#define CYREG_PHUB_TDMEM106_ORIG_TD1 0x40007b54u +#define CYDEV_PHUB_TDMEM107_BASE 0x40007b58u +#define CYDEV_PHUB_TDMEM107_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM107_ORIG_TD0 0x40007b58u +#define CYREG_PHUB_TDMEM107_ORIG_TD1 0x40007b5cu +#define CYDEV_PHUB_TDMEM108_BASE 0x40007b60u +#define CYDEV_PHUB_TDMEM108_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM108_ORIG_TD0 0x40007b60u +#define CYREG_PHUB_TDMEM108_ORIG_TD1 0x40007b64u +#define CYDEV_PHUB_TDMEM109_BASE 0x40007b68u +#define CYDEV_PHUB_TDMEM109_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM109_ORIG_TD0 0x40007b68u +#define CYREG_PHUB_TDMEM109_ORIG_TD1 0x40007b6cu +#define CYDEV_PHUB_TDMEM110_BASE 0x40007b70u +#define CYDEV_PHUB_TDMEM110_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM110_ORIG_TD0 0x40007b70u +#define CYREG_PHUB_TDMEM110_ORIG_TD1 0x40007b74u +#define CYDEV_PHUB_TDMEM111_BASE 0x40007b78u +#define CYDEV_PHUB_TDMEM111_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM111_ORIG_TD0 0x40007b78u +#define CYREG_PHUB_TDMEM111_ORIG_TD1 0x40007b7cu +#define CYDEV_PHUB_TDMEM112_BASE 0x40007b80u +#define CYDEV_PHUB_TDMEM112_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM112_ORIG_TD0 0x40007b80u +#define CYREG_PHUB_TDMEM112_ORIG_TD1 0x40007b84u +#define CYDEV_PHUB_TDMEM113_BASE 0x40007b88u +#define CYDEV_PHUB_TDMEM113_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM113_ORIG_TD0 0x40007b88u +#define CYREG_PHUB_TDMEM113_ORIG_TD1 0x40007b8cu +#define CYDEV_PHUB_TDMEM114_BASE 0x40007b90u +#define CYDEV_PHUB_TDMEM114_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM114_ORIG_TD0 0x40007b90u +#define CYREG_PHUB_TDMEM114_ORIG_TD1 0x40007b94u +#define CYDEV_PHUB_TDMEM115_BASE 0x40007b98u +#define CYDEV_PHUB_TDMEM115_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM115_ORIG_TD0 0x40007b98u +#define CYREG_PHUB_TDMEM115_ORIG_TD1 0x40007b9cu +#define CYDEV_PHUB_TDMEM116_BASE 0x40007ba0u +#define CYDEV_PHUB_TDMEM116_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM116_ORIG_TD0 0x40007ba0u +#define CYREG_PHUB_TDMEM116_ORIG_TD1 0x40007ba4u +#define CYDEV_PHUB_TDMEM117_BASE 0x40007ba8u +#define CYDEV_PHUB_TDMEM117_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM117_ORIG_TD0 0x40007ba8u +#define CYREG_PHUB_TDMEM117_ORIG_TD1 0x40007bacu +#define CYDEV_PHUB_TDMEM118_BASE 0x40007bb0u +#define CYDEV_PHUB_TDMEM118_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM118_ORIG_TD0 0x40007bb0u +#define CYREG_PHUB_TDMEM118_ORIG_TD1 0x40007bb4u +#define CYDEV_PHUB_TDMEM119_BASE 0x40007bb8u +#define CYDEV_PHUB_TDMEM119_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM119_ORIG_TD0 0x40007bb8u +#define CYREG_PHUB_TDMEM119_ORIG_TD1 0x40007bbcu +#define CYDEV_PHUB_TDMEM120_BASE 0x40007bc0u +#define CYDEV_PHUB_TDMEM120_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM120_ORIG_TD0 0x40007bc0u +#define CYREG_PHUB_TDMEM120_ORIG_TD1 0x40007bc4u +#define CYDEV_PHUB_TDMEM121_BASE 0x40007bc8u +#define CYDEV_PHUB_TDMEM121_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM121_ORIG_TD0 0x40007bc8u +#define CYREG_PHUB_TDMEM121_ORIG_TD1 0x40007bccu +#define CYDEV_PHUB_TDMEM122_BASE 0x40007bd0u +#define CYDEV_PHUB_TDMEM122_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM122_ORIG_TD0 0x40007bd0u +#define CYREG_PHUB_TDMEM122_ORIG_TD1 0x40007bd4u +#define CYDEV_PHUB_TDMEM123_BASE 0x40007bd8u +#define CYDEV_PHUB_TDMEM123_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM123_ORIG_TD0 0x40007bd8u +#define CYREG_PHUB_TDMEM123_ORIG_TD1 0x40007bdcu +#define CYDEV_PHUB_TDMEM124_BASE 0x40007be0u +#define CYDEV_PHUB_TDMEM124_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM124_ORIG_TD0 0x40007be0u +#define CYREG_PHUB_TDMEM124_ORIG_TD1 0x40007be4u +#define CYDEV_PHUB_TDMEM125_BASE 0x40007be8u +#define CYDEV_PHUB_TDMEM125_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM125_ORIG_TD0 0x40007be8u +#define CYREG_PHUB_TDMEM125_ORIG_TD1 0x40007becu +#define CYDEV_PHUB_TDMEM126_BASE 0x40007bf0u +#define CYDEV_PHUB_TDMEM126_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM126_ORIG_TD0 0x40007bf0u +#define CYREG_PHUB_TDMEM126_ORIG_TD1 0x40007bf4u +#define CYDEV_PHUB_TDMEM127_BASE 0x40007bf8u +#define CYDEV_PHUB_TDMEM127_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM127_ORIG_TD0 0x40007bf8u +#define CYREG_PHUB_TDMEM127_ORIG_TD1 0x40007bfcu +#define CYDEV_EE_BASE 0x40008000u +#define CYDEV_EE_SIZE 0x00000800u +#define CYREG_EE_DATA_MBASE 0x40008000u +#define CYREG_EE_DATA_MSIZE 0x00000800u +#define CYDEV_CAN0_BASE 0x4000a000u +#define CYDEV_CAN0_SIZE 0x000002a0u +#define CYDEV_CAN0_CSR_BASE 0x4000a000u +#define CYDEV_CAN0_CSR_SIZE 0x00000018u +#define CYREG_CAN0_CSR_INT_SR 0x4000a000u +#define CYREG_CAN0_CSR_INT_EN 0x4000a004u +#define CYREG_CAN0_CSR_BUF_SR 0x4000a008u +#define CYREG_CAN0_CSR_ERR_SR 0x4000a00cu +#define CYREG_CAN0_CSR_CMD 0x4000a010u +#define CYREG_CAN0_CSR_CFG 0x4000a014u +#define CYDEV_CAN0_TX0_BASE 0x4000a020u +#define CYDEV_CAN0_TX0_SIZE 0x00000010u +#define CYREG_CAN0_TX0_CMD 0x4000a020u +#define CYREG_CAN0_TX0_ID 0x4000a024u +#define CYREG_CAN0_TX0_DH 0x4000a028u +#define CYREG_CAN0_TX0_DL 0x4000a02cu +#define CYDEV_CAN0_TX1_BASE 0x4000a030u +#define CYDEV_CAN0_TX1_SIZE 0x00000010u +#define CYREG_CAN0_TX1_CMD 0x4000a030u +#define CYREG_CAN0_TX1_ID 0x4000a034u +#define CYREG_CAN0_TX1_DH 0x4000a038u +#define CYREG_CAN0_TX1_DL 0x4000a03cu +#define CYDEV_CAN0_TX2_BASE 0x4000a040u +#define CYDEV_CAN0_TX2_SIZE 0x00000010u +#define CYREG_CAN0_TX2_CMD 0x4000a040u +#define CYREG_CAN0_TX2_ID 0x4000a044u +#define CYREG_CAN0_TX2_DH 0x4000a048u +#define CYREG_CAN0_TX2_DL 0x4000a04cu +#define CYDEV_CAN0_TX3_BASE 0x4000a050u +#define CYDEV_CAN0_TX3_SIZE 0x00000010u +#define CYREG_CAN0_TX3_CMD 0x4000a050u +#define CYREG_CAN0_TX3_ID 0x4000a054u +#define CYREG_CAN0_TX3_DH 0x4000a058u +#define CYREG_CAN0_TX3_DL 0x4000a05cu +#define CYDEV_CAN0_TX4_BASE 0x4000a060u +#define CYDEV_CAN0_TX4_SIZE 0x00000010u +#define CYREG_CAN0_TX4_CMD 0x4000a060u +#define CYREG_CAN0_TX4_ID 0x4000a064u +#define CYREG_CAN0_TX4_DH 0x4000a068u +#define CYREG_CAN0_TX4_DL 0x4000a06cu +#define CYDEV_CAN0_TX5_BASE 0x4000a070u +#define CYDEV_CAN0_TX5_SIZE 0x00000010u +#define CYREG_CAN0_TX5_CMD 0x4000a070u +#define CYREG_CAN0_TX5_ID 0x4000a074u +#define CYREG_CAN0_TX5_DH 0x4000a078u +#define CYREG_CAN0_TX5_DL 0x4000a07cu +#define CYDEV_CAN0_TX6_BASE 0x4000a080u +#define CYDEV_CAN0_TX6_SIZE 0x00000010u +#define CYREG_CAN0_TX6_CMD 0x4000a080u +#define CYREG_CAN0_TX6_ID 0x4000a084u +#define CYREG_CAN0_TX6_DH 0x4000a088u +#define CYREG_CAN0_TX6_DL 0x4000a08cu +#define CYDEV_CAN0_TX7_BASE 0x4000a090u +#define CYDEV_CAN0_TX7_SIZE 0x00000010u +#define CYREG_CAN0_TX7_CMD 0x4000a090u +#define CYREG_CAN0_TX7_ID 0x4000a094u +#define CYREG_CAN0_TX7_DH 0x4000a098u +#define CYREG_CAN0_TX7_DL 0x4000a09cu +#define CYDEV_CAN0_RX0_BASE 0x4000a0a0u +#define CYDEV_CAN0_RX0_SIZE 0x00000020u +#define CYREG_CAN0_RX0_CMD 0x4000a0a0u +#define CYREG_CAN0_RX0_ID 0x4000a0a4u +#define CYREG_CAN0_RX0_DH 0x4000a0a8u +#define CYREG_CAN0_RX0_DL 0x4000a0acu +#define CYREG_CAN0_RX0_AMR 0x4000a0b0u +#define CYREG_CAN0_RX0_ACR 0x4000a0b4u +#define CYREG_CAN0_RX0_AMRD 0x4000a0b8u +#define CYREG_CAN0_RX0_ACRD 0x4000a0bcu +#define CYDEV_CAN0_RX1_BASE 0x4000a0c0u +#define CYDEV_CAN0_RX1_SIZE 0x00000020u +#define CYREG_CAN0_RX1_CMD 0x4000a0c0u +#define CYREG_CAN0_RX1_ID 0x4000a0c4u +#define CYREG_CAN0_RX1_DH 0x4000a0c8u +#define CYREG_CAN0_RX1_DL 0x4000a0ccu +#define CYREG_CAN0_RX1_AMR 0x4000a0d0u +#define CYREG_CAN0_RX1_ACR 0x4000a0d4u +#define CYREG_CAN0_RX1_AMRD 0x4000a0d8u +#define CYREG_CAN0_RX1_ACRD 0x4000a0dcu +#define CYDEV_CAN0_RX2_BASE 0x4000a0e0u +#define CYDEV_CAN0_RX2_SIZE 0x00000020u +#define CYREG_CAN0_RX2_CMD 0x4000a0e0u +#define CYREG_CAN0_RX2_ID 0x4000a0e4u +#define CYREG_CAN0_RX2_DH 0x4000a0e8u +#define CYREG_CAN0_RX2_DL 0x4000a0ecu +#define CYREG_CAN0_RX2_AMR 0x4000a0f0u +#define CYREG_CAN0_RX2_ACR 0x4000a0f4u +#define CYREG_CAN0_RX2_AMRD 0x4000a0f8u +#define CYREG_CAN0_RX2_ACRD 0x4000a0fcu +#define CYDEV_CAN0_RX3_BASE 0x4000a100u +#define CYDEV_CAN0_RX3_SIZE 0x00000020u +#define CYREG_CAN0_RX3_CMD 0x4000a100u +#define CYREG_CAN0_RX3_ID 0x4000a104u +#define CYREG_CAN0_RX3_DH 0x4000a108u +#define CYREG_CAN0_RX3_DL 0x4000a10cu +#define CYREG_CAN0_RX3_AMR 0x4000a110u +#define CYREG_CAN0_RX3_ACR 0x4000a114u +#define CYREG_CAN0_RX3_AMRD 0x4000a118u +#define CYREG_CAN0_RX3_ACRD 0x4000a11cu +#define CYDEV_CAN0_RX4_BASE 0x4000a120u +#define CYDEV_CAN0_RX4_SIZE 0x00000020u +#define CYREG_CAN0_RX4_CMD 0x4000a120u +#define CYREG_CAN0_RX4_ID 0x4000a124u +#define CYREG_CAN0_RX4_DH 0x4000a128u +#define CYREG_CAN0_RX4_DL 0x4000a12cu +#define CYREG_CAN0_RX4_AMR 0x4000a130u +#define CYREG_CAN0_RX4_ACR 0x4000a134u +#define CYREG_CAN0_RX4_AMRD 0x4000a138u +#define CYREG_CAN0_RX4_ACRD 0x4000a13cu +#define CYDEV_CAN0_RX5_BASE 0x4000a140u +#define CYDEV_CAN0_RX5_SIZE 0x00000020u +#define CYREG_CAN0_RX5_CMD 0x4000a140u +#define CYREG_CAN0_RX5_ID 0x4000a144u +#define CYREG_CAN0_RX5_DH 0x4000a148u +#define CYREG_CAN0_RX5_DL 0x4000a14cu +#define CYREG_CAN0_RX5_AMR 0x4000a150u +#define CYREG_CAN0_RX5_ACR 0x4000a154u +#define CYREG_CAN0_RX5_AMRD 0x4000a158u +#define CYREG_CAN0_RX5_ACRD 0x4000a15cu +#define CYDEV_CAN0_RX6_BASE 0x4000a160u +#define CYDEV_CAN0_RX6_SIZE 0x00000020u +#define CYREG_CAN0_RX6_CMD 0x4000a160u +#define CYREG_CAN0_RX6_ID 0x4000a164u +#define CYREG_CAN0_RX6_DH 0x4000a168u +#define CYREG_CAN0_RX6_DL 0x4000a16cu +#define CYREG_CAN0_RX6_AMR 0x4000a170u +#define CYREG_CAN0_RX6_ACR 0x4000a174u +#define CYREG_CAN0_RX6_AMRD 0x4000a178u +#define CYREG_CAN0_RX6_ACRD 0x4000a17cu +#define CYDEV_CAN0_RX7_BASE 0x4000a180u +#define CYDEV_CAN0_RX7_SIZE 0x00000020u +#define CYREG_CAN0_RX7_CMD 0x4000a180u +#define CYREG_CAN0_RX7_ID 0x4000a184u +#define CYREG_CAN0_RX7_DH 0x4000a188u +#define CYREG_CAN0_RX7_DL 0x4000a18cu +#define CYREG_CAN0_RX7_AMR 0x4000a190u +#define CYREG_CAN0_RX7_ACR 0x4000a194u +#define CYREG_CAN0_RX7_AMRD 0x4000a198u +#define CYREG_CAN0_RX7_ACRD 0x4000a19cu +#define CYDEV_CAN0_RX8_BASE 0x4000a1a0u +#define CYDEV_CAN0_RX8_SIZE 0x00000020u +#define CYREG_CAN0_RX8_CMD 0x4000a1a0u +#define CYREG_CAN0_RX8_ID 0x4000a1a4u +#define CYREG_CAN0_RX8_DH 0x4000a1a8u +#define CYREG_CAN0_RX8_DL 0x4000a1acu +#define CYREG_CAN0_RX8_AMR 0x4000a1b0u +#define CYREG_CAN0_RX8_ACR 0x4000a1b4u +#define CYREG_CAN0_RX8_AMRD 0x4000a1b8u +#define CYREG_CAN0_RX8_ACRD 0x4000a1bcu +#define CYDEV_CAN0_RX9_BASE 0x4000a1c0u +#define CYDEV_CAN0_RX9_SIZE 0x00000020u +#define CYREG_CAN0_RX9_CMD 0x4000a1c0u +#define CYREG_CAN0_RX9_ID 0x4000a1c4u +#define CYREG_CAN0_RX9_DH 0x4000a1c8u +#define CYREG_CAN0_RX9_DL 0x4000a1ccu +#define CYREG_CAN0_RX9_AMR 0x4000a1d0u +#define CYREG_CAN0_RX9_ACR 0x4000a1d4u +#define CYREG_CAN0_RX9_AMRD 0x4000a1d8u +#define CYREG_CAN0_RX9_ACRD 0x4000a1dcu +#define CYDEV_CAN0_RX10_BASE 0x4000a1e0u +#define CYDEV_CAN0_RX10_SIZE 0x00000020u +#define CYREG_CAN0_RX10_CMD 0x4000a1e0u +#define CYREG_CAN0_RX10_ID 0x4000a1e4u +#define CYREG_CAN0_RX10_DH 0x4000a1e8u +#define CYREG_CAN0_RX10_DL 0x4000a1ecu +#define CYREG_CAN0_RX10_AMR 0x4000a1f0u +#define CYREG_CAN0_RX10_ACR 0x4000a1f4u +#define CYREG_CAN0_RX10_AMRD 0x4000a1f8u +#define CYREG_CAN0_RX10_ACRD 0x4000a1fcu +#define CYDEV_CAN0_RX11_BASE 0x4000a200u +#define CYDEV_CAN0_RX11_SIZE 0x00000020u +#define CYREG_CAN0_RX11_CMD 0x4000a200u +#define CYREG_CAN0_RX11_ID 0x4000a204u +#define CYREG_CAN0_RX11_DH 0x4000a208u +#define CYREG_CAN0_RX11_DL 0x4000a20cu +#define CYREG_CAN0_RX11_AMR 0x4000a210u +#define CYREG_CAN0_RX11_ACR 0x4000a214u +#define CYREG_CAN0_RX11_AMRD 0x4000a218u +#define CYREG_CAN0_RX11_ACRD 0x4000a21cu +#define CYDEV_CAN0_RX12_BASE 0x4000a220u +#define CYDEV_CAN0_RX12_SIZE 0x00000020u +#define CYREG_CAN0_RX12_CMD 0x4000a220u +#define CYREG_CAN0_RX12_ID 0x4000a224u +#define CYREG_CAN0_RX12_DH 0x4000a228u +#define CYREG_CAN0_RX12_DL 0x4000a22cu +#define CYREG_CAN0_RX12_AMR 0x4000a230u +#define CYREG_CAN0_RX12_ACR 0x4000a234u +#define CYREG_CAN0_RX12_AMRD 0x4000a238u +#define CYREG_CAN0_RX12_ACRD 0x4000a23cu +#define CYDEV_CAN0_RX13_BASE 0x4000a240u +#define CYDEV_CAN0_RX13_SIZE 0x00000020u +#define CYREG_CAN0_RX13_CMD 0x4000a240u +#define CYREG_CAN0_RX13_ID 0x4000a244u +#define CYREG_CAN0_RX13_DH 0x4000a248u +#define CYREG_CAN0_RX13_DL 0x4000a24cu +#define CYREG_CAN0_RX13_AMR 0x4000a250u +#define CYREG_CAN0_RX13_ACR 0x4000a254u +#define CYREG_CAN0_RX13_AMRD 0x4000a258u +#define CYREG_CAN0_RX13_ACRD 0x4000a25cu +#define CYDEV_CAN0_RX14_BASE 0x4000a260u +#define CYDEV_CAN0_RX14_SIZE 0x00000020u +#define CYREG_CAN0_RX14_CMD 0x4000a260u +#define CYREG_CAN0_RX14_ID 0x4000a264u +#define CYREG_CAN0_RX14_DH 0x4000a268u +#define CYREG_CAN0_RX14_DL 0x4000a26cu +#define CYREG_CAN0_RX14_AMR 0x4000a270u +#define CYREG_CAN0_RX14_ACR 0x4000a274u +#define CYREG_CAN0_RX14_AMRD 0x4000a278u +#define CYREG_CAN0_RX14_ACRD 0x4000a27cu +#define CYDEV_CAN0_RX15_BASE 0x4000a280u +#define CYDEV_CAN0_RX15_SIZE 0x00000020u +#define CYREG_CAN0_RX15_CMD 0x4000a280u +#define CYREG_CAN0_RX15_ID 0x4000a284u +#define CYREG_CAN0_RX15_DH 0x4000a288u +#define CYREG_CAN0_RX15_DL 0x4000a28cu +#define CYREG_CAN0_RX15_AMR 0x4000a290u +#define CYREG_CAN0_RX15_ACR 0x4000a294u +#define CYREG_CAN0_RX15_AMRD 0x4000a298u +#define CYREG_CAN0_RX15_ACRD 0x4000a29cu +#define CYDEV_DFB0_BASE 0x4000c000u +#define CYDEV_DFB0_SIZE 0x000007b5u +#define CYDEV_DFB0_DPA_SRAM_BASE 0x4000c000u +#define CYDEV_DFB0_DPA_SRAM_SIZE 0x00000200u +#define CYREG_DFB0_DPA_SRAM_DATA_MBASE 0x4000c000u +#define CYREG_DFB0_DPA_SRAM_DATA_MSIZE 0x00000200u +#define CYDEV_DFB0_DPB_SRAM_BASE 0x4000c200u +#define CYDEV_DFB0_DPB_SRAM_SIZE 0x00000200u +#define CYREG_DFB0_DPB_SRAM_DATA_MBASE 0x4000c200u +#define CYREG_DFB0_DPB_SRAM_DATA_MSIZE 0x00000200u +#define CYDEV_DFB0_CSA_SRAM_BASE 0x4000c400u +#define CYDEV_DFB0_CSA_SRAM_SIZE 0x00000100u +#define CYREG_DFB0_CSA_SRAM_DATA_MBASE 0x4000c400u +#define CYREG_DFB0_CSA_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_CSB_SRAM_BASE 0x4000c500u +#define CYDEV_DFB0_CSB_SRAM_SIZE 0x00000100u +#define CYREG_DFB0_CSB_SRAM_DATA_MBASE 0x4000c500u +#define CYREG_DFB0_CSB_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_FSM_SRAM_BASE 0x4000c600u +#define CYDEV_DFB0_FSM_SRAM_SIZE 0x00000100u +#define CYREG_DFB0_FSM_SRAM_DATA_MBASE 0x4000c600u +#define CYREG_DFB0_FSM_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_ACU_SRAM_BASE 0x4000c700u +#define CYDEV_DFB0_ACU_SRAM_SIZE 0x00000040u +#define CYREG_DFB0_ACU_SRAM_DATA_MBASE 0x4000c700u +#define CYREG_DFB0_ACU_SRAM_DATA_MSIZE 0x00000040u +#define CYREG_DFB0_CR 0x4000c780u +#define CYREG_DFB0_SR 0x4000c784u +#define CYREG_DFB0_RAM_EN 0x4000c788u +#define CYREG_DFB0_RAM_DIR 0x4000c78cu +#define CYREG_DFB0_SEMA 0x4000c790u +#define CYREG_DFB0_DSI_CTRL 0x4000c794u +#define CYREG_DFB0_INT_CTRL 0x4000c798u +#define CYREG_DFB0_DMA_CTRL 0x4000c79cu +#define CYREG_DFB0_STAGEA 0x4000c7a0u +#define CYREG_DFB0_STAGEAM 0x4000c7a1u +#define CYREG_DFB0_STAGEAH 0x4000c7a2u +#define CYREG_DFB0_STAGEB 0x4000c7a4u +#define CYREG_DFB0_STAGEBM 0x4000c7a5u +#define CYREG_DFB0_STAGEBH 0x4000c7a6u +#define CYREG_DFB0_HOLDA 0x4000c7a8u +#define CYREG_DFB0_HOLDAM 0x4000c7a9u +#define CYREG_DFB0_HOLDAH 0x4000c7aau +#define CYREG_DFB0_HOLDAS 0x4000c7abu +#define CYREG_DFB0_HOLDB 0x4000c7acu +#define CYREG_DFB0_HOLDBM 0x4000c7adu +#define CYREG_DFB0_HOLDBH 0x4000c7aeu +#define CYREG_DFB0_HOLDBS 0x4000c7afu +#define CYREG_DFB0_COHER 0x4000c7b0u +#define CYREG_DFB0_DALIGN 0x4000c7b4u +#define CYDEV_UCFG_BASE 0x40010000u +#define CYDEV_UCFG_SIZE 0x00005040u +#define CYDEV_UCFG_B0_BASE 0x40010000u +#define CYDEV_UCFG_B0_SIZE 0x00000fefu +#define CYDEV_UCFG_B0_P0_BASE 0x40010000u +#define CYDEV_UCFG_B0_P0_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P0_U0_BASE 0x40010000u +#define CYDEV_UCFG_B0_P0_U0_SIZE 0x00000070u +#define CYREG_B0_P0_U0_PLD_IT0 0x40010000u +#define CYREG_B0_P0_U0_PLD_IT1 0x40010004u +#define CYREG_B0_P0_U0_PLD_IT2 0x40010008u +#define CYREG_B0_P0_U0_PLD_IT3 0x4001000cu +#define CYREG_B0_P0_U0_PLD_IT4 0x40010010u +#define CYREG_B0_P0_U0_PLD_IT5 0x40010014u +#define CYREG_B0_P0_U0_PLD_IT6 0x40010018u +#define CYREG_B0_P0_U0_PLD_IT7 0x4001001cu +#define CYREG_B0_P0_U0_PLD_IT8 0x40010020u +#define CYREG_B0_P0_U0_PLD_IT9 0x40010024u +#define CYREG_B0_P0_U0_PLD_IT10 0x40010028u +#define CYREG_B0_P0_U0_PLD_IT11 0x4001002cu +#define CYREG_B0_P0_U0_PLD_ORT0 0x40010030u +#define CYREG_B0_P0_U0_PLD_ORT1 0x40010032u +#define CYREG_B0_P0_U0_PLD_ORT2 0x40010034u +#define CYREG_B0_P0_U0_PLD_ORT3 0x40010036u +#define CYREG_B0_P0_U0_MC_CFG_CEN_CONST 0x40010038u +#define CYREG_B0_P0_U0_MC_CFG_XORFB 0x4001003au +#define CYREG_B0_P0_U0_MC_CFG_SET_RESET 0x4001003cu +#define CYREG_B0_P0_U0_MC_CFG_BYPASS 0x4001003eu +#define CYREG_B0_P0_U0_CFG0 0x40010040u +#define CYREG_B0_P0_U0_CFG1 0x40010041u +#define CYREG_B0_P0_U0_CFG2 0x40010042u +#define CYREG_B0_P0_U0_CFG3 0x40010043u +#define CYREG_B0_P0_U0_CFG4 0x40010044u +#define CYREG_B0_P0_U0_CFG5 0x40010045u +#define CYREG_B0_P0_U0_CFG6 0x40010046u +#define CYREG_B0_P0_U0_CFG7 0x40010047u +#define CYREG_B0_P0_U0_CFG8 0x40010048u +#define CYREG_B0_P0_U0_CFG9 0x40010049u +#define CYREG_B0_P0_U0_CFG10 0x4001004au +#define CYREG_B0_P0_U0_CFG11 0x4001004bu +#define CYREG_B0_P0_U0_CFG12 0x4001004cu +#define CYREG_B0_P0_U0_CFG13 0x4001004du +#define CYREG_B0_P0_U0_CFG14 0x4001004eu +#define CYREG_B0_P0_U0_CFG15 0x4001004fu +#define CYREG_B0_P0_U0_CFG16 0x40010050u +#define CYREG_B0_P0_U0_CFG17 0x40010051u +#define CYREG_B0_P0_U0_CFG18 0x40010052u +#define CYREG_B0_P0_U0_CFG19 0x40010053u +#define CYREG_B0_P0_U0_CFG20 0x40010054u +#define CYREG_B0_P0_U0_CFG21 0x40010055u +#define CYREG_B0_P0_U0_CFG22 0x40010056u +#define CYREG_B0_P0_U0_CFG23 0x40010057u +#define CYREG_B0_P0_U0_CFG24 0x40010058u +#define CYREG_B0_P0_U0_CFG25 0x40010059u +#define CYREG_B0_P0_U0_CFG26 0x4001005au +#define CYREG_B0_P0_U0_CFG27 0x4001005bu +#define CYREG_B0_P0_U0_CFG28 0x4001005cu +#define CYREG_B0_P0_U0_CFG29 0x4001005du +#define CYREG_B0_P0_U0_CFG30 0x4001005eu +#define CYREG_B0_P0_U0_CFG31 0x4001005fu +#define CYREG_B0_P0_U0_DCFG0 0x40010060u +#define CYREG_B0_P0_U0_DCFG1 0x40010062u +#define CYREG_B0_P0_U0_DCFG2 0x40010064u +#define CYREG_B0_P0_U0_DCFG3 0x40010066u +#define CYREG_B0_P0_U0_DCFG4 0x40010068u +#define CYREG_B0_P0_U0_DCFG5 0x4001006au +#define CYREG_B0_P0_U0_DCFG6 0x4001006cu +#define CYREG_B0_P0_U0_DCFG7 0x4001006eu +#define CYDEV_UCFG_B0_P0_U1_BASE 0x40010080u +#define CYDEV_UCFG_B0_P0_U1_SIZE 0x00000070u +#define CYREG_B0_P0_U1_PLD_IT0 0x40010080u +#define CYREG_B0_P0_U1_PLD_IT1 0x40010084u +#define CYREG_B0_P0_U1_PLD_IT2 0x40010088u +#define CYREG_B0_P0_U1_PLD_IT3 0x4001008cu +#define CYREG_B0_P0_U1_PLD_IT4 0x40010090u +#define CYREG_B0_P0_U1_PLD_IT5 0x40010094u +#define CYREG_B0_P0_U1_PLD_IT6 0x40010098u +#define CYREG_B0_P0_U1_PLD_IT7 0x4001009cu +#define CYREG_B0_P0_U1_PLD_IT8 0x400100a0u +#define CYREG_B0_P0_U1_PLD_IT9 0x400100a4u +#define CYREG_B0_P0_U1_PLD_IT10 0x400100a8u +#define CYREG_B0_P0_U1_PLD_IT11 0x400100acu +#define CYREG_B0_P0_U1_PLD_ORT0 0x400100b0u +#define CYREG_B0_P0_U1_PLD_ORT1 0x400100b2u +#define CYREG_B0_P0_U1_PLD_ORT2 0x400100b4u +#define CYREG_B0_P0_U1_PLD_ORT3 0x400100b6u +#define CYREG_B0_P0_U1_MC_CFG_CEN_CONST 0x400100b8u +#define CYREG_B0_P0_U1_MC_CFG_XORFB 0x400100bau +#define CYREG_B0_P0_U1_MC_CFG_SET_RESET 0x400100bcu +#define CYREG_B0_P0_U1_MC_CFG_BYPASS 0x400100beu +#define CYREG_B0_P0_U1_CFG0 0x400100c0u +#define CYREG_B0_P0_U1_CFG1 0x400100c1u +#define CYREG_B0_P0_U1_CFG2 0x400100c2u +#define CYREG_B0_P0_U1_CFG3 0x400100c3u +#define CYREG_B0_P0_U1_CFG4 0x400100c4u +#define CYREG_B0_P0_U1_CFG5 0x400100c5u +#define CYREG_B0_P0_U1_CFG6 0x400100c6u +#define CYREG_B0_P0_U1_CFG7 0x400100c7u +#define CYREG_B0_P0_U1_CFG8 0x400100c8u +#define CYREG_B0_P0_U1_CFG9 0x400100c9u +#define CYREG_B0_P0_U1_CFG10 0x400100cau +#define CYREG_B0_P0_U1_CFG11 0x400100cbu +#define CYREG_B0_P0_U1_CFG12 0x400100ccu +#define CYREG_B0_P0_U1_CFG13 0x400100cdu +#define CYREG_B0_P0_U1_CFG14 0x400100ceu +#define CYREG_B0_P0_U1_CFG15 0x400100cfu +#define CYREG_B0_P0_U1_CFG16 0x400100d0u +#define CYREG_B0_P0_U1_CFG17 0x400100d1u +#define CYREG_B0_P0_U1_CFG18 0x400100d2u +#define CYREG_B0_P0_U1_CFG19 0x400100d3u +#define CYREG_B0_P0_U1_CFG20 0x400100d4u +#define CYREG_B0_P0_U1_CFG21 0x400100d5u +#define CYREG_B0_P0_U1_CFG22 0x400100d6u +#define CYREG_B0_P0_U1_CFG23 0x400100d7u +#define CYREG_B0_P0_U1_CFG24 0x400100d8u +#define CYREG_B0_P0_U1_CFG25 0x400100d9u +#define CYREG_B0_P0_U1_CFG26 0x400100dau +#define CYREG_B0_P0_U1_CFG27 0x400100dbu +#define CYREG_B0_P0_U1_CFG28 0x400100dcu +#define CYREG_B0_P0_U1_CFG29 0x400100ddu +#define CYREG_B0_P0_U1_CFG30 0x400100deu +#define CYREG_B0_P0_U1_CFG31 0x400100dfu +#define CYREG_B0_P0_U1_DCFG0 0x400100e0u +#define CYREG_B0_P0_U1_DCFG1 0x400100e2u +#define CYREG_B0_P0_U1_DCFG2 0x400100e4u +#define CYREG_B0_P0_U1_DCFG3 0x400100e6u +#define CYREG_B0_P0_U1_DCFG4 0x400100e8u +#define CYREG_B0_P0_U1_DCFG5 0x400100eau +#define CYREG_B0_P0_U1_DCFG6 0x400100ecu +#define CYREG_B0_P0_U1_DCFG7 0x400100eeu +#define CYDEV_UCFG_B0_P0_ROUTE_BASE 0x40010100u +#define CYDEV_UCFG_B0_P0_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P1_BASE 0x40010200u +#define CYDEV_UCFG_B0_P1_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P1_U0_BASE 0x40010200u +#define CYDEV_UCFG_B0_P1_U0_SIZE 0x00000070u +#define CYREG_B0_P1_U0_PLD_IT0 0x40010200u +#define CYREG_B0_P1_U0_PLD_IT1 0x40010204u +#define CYREG_B0_P1_U0_PLD_IT2 0x40010208u +#define CYREG_B0_P1_U0_PLD_IT3 0x4001020cu +#define CYREG_B0_P1_U0_PLD_IT4 0x40010210u +#define CYREG_B0_P1_U0_PLD_IT5 0x40010214u +#define CYREG_B0_P1_U0_PLD_IT6 0x40010218u +#define CYREG_B0_P1_U0_PLD_IT7 0x4001021cu +#define CYREG_B0_P1_U0_PLD_IT8 0x40010220u +#define CYREG_B0_P1_U0_PLD_IT9 0x40010224u +#define CYREG_B0_P1_U0_PLD_IT10 0x40010228u +#define CYREG_B0_P1_U0_PLD_IT11 0x4001022cu +#define CYREG_B0_P1_U0_PLD_ORT0 0x40010230u +#define CYREG_B0_P1_U0_PLD_ORT1 0x40010232u +#define CYREG_B0_P1_U0_PLD_ORT2 0x40010234u +#define CYREG_B0_P1_U0_PLD_ORT3 0x40010236u +#define CYREG_B0_P1_U0_MC_CFG_CEN_CONST 0x40010238u +#define CYREG_B0_P1_U0_MC_CFG_XORFB 0x4001023au +#define CYREG_B0_P1_U0_MC_CFG_SET_RESET 0x4001023cu +#define CYREG_B0_P1_U0_MC_CFG_BYPASS 0x4001023eu +#define CYREG_B0_P1_U0_CFG0 0x40010240u +#define CYREG_B0_P1_U0_CFG1 0x40010241u +#define CYREG_B0_P1_U0_CFG2 0x40010242u +#define CYREG_B0_P1_U0_CFG3 0x40010243u +#define CYREG_B0_P1_U0_CFG4 0x40010244u +#define CYREG_B0_P1_U0_CFG5 0x40010245u +#define CYREG_B0_P1_U0_CFG6 0x40010246u +#define CYREG_B0_P1_U0_CFG7 0x40010247u +#define CYREG_B0_P1_U0_CFG8 0x40010248u +#define CYREG_B0_P1_U0_CFG9 0x40010249u +#define CYREG_B0_P1_U0_CFG10 0x4001024au +#define CYREG_B0_P1_U0_CFG11 0x4001024bu +#define CYREG_B0_P1_U0_CFG12 0x4001024cu +#define CYREG_B0_P1_U0_CFG13 0x4001024du +#define CYREG_B0_P1_U0_CFG14 0x4001024eu +#define CYREG_B0_P1_U0_CFG15 0x4001024fu +#define CYREG_B0_P1_U0_CFG16 0x40010250u +#define CYREG_B0_P1_U0_CFG17 0x40010251u +#define CYREG_B0_P1_U0_CFG18 0x40010252u +#define CYREG_B0_P1_U0_CFG19 0x40010253u +#define CYREG_B0_P1_U0_CFG20 0x40010254u +#define CYREG_B0_P1_U0_CFG21 0x40010255u +#define CYREG_B0_P1_U0_CFG22 0x40010256u +#define CYREG_B0_P1_U0_CFG23 0x40010257u +#define CYREG_B0_P1_U0_CFG24 0x40010258u +#define CYREG_B0_P1_U0_CFG25 0x40010259u +#define CYREG_B0_P1_U0_CFG26 0x4001025au +#define CYREG_B0_P1_U0_CFG27 0x4001025bu +#define CYREG_B0_P1_U0_CFG28 0x4001025cu +#define CYREG_B0_P1_U0_CFG29 0x4001025du +#define CYREG_B0_P1_U0_CFG30 0x4001025eu +#define CYREG_B0_P1_U0_CFG31 0x4001025fu +#define CYREG_B0_P1_U0_DCFG0 0x40010260u +#define CYREG_B0_P1_U0_DCFG1 0x40010262u +#define CYREG_B0_P1_U0_DCFG2 0x40010264u +#define CYREG_B0_P1_U0_DCFG3 0x40010266u +#define CYREG_B0_P1_U0_DCFG4 0x40010268u +#define CYREG_B0_P1_U0_DCFG5 0x4001026au +#define CYREG_B0_P1_U0_DCFG6 0x4001026cu +#define CYREG_B0_P1_U0_DCFG7 0x4001026eu +#define CYDEV_UCFG_B0_P1_U1_BASE 0x40010280u +#define CYDEV_UCFG_B0_P1_U1_SIZE 0x00000070u +#define CYREG_B0_P1_U1_PLD_IT0 0x40010280u +#define CYREG_B0_P1_U1_PLD_IT1 0x40010284u +#define CYREG_B0_P1_U1_PLD_IT2 0x40010288u +#define CYREG_B0_P1_U1_PLD_IT3 0x4001028cu +#define CYREG_B0_P1_U1_PLD_IT4 0x40010290u +#define CYREG_B0_P1_U1_PLD_IT5 0x40010294u +#define CYREG_B0_P1_U1_PLD_IT6 0x40010298u +#define CYREG_B0_P1_U1_PLD_IT7 0x4001029cu +#define CYREG_B0_P1_U1_PLD_IT8 0x400102a0u +#define CYREG_B0_P1_U1_PLD_IT9 0x400102a4u +#define CYREG_B0_P1_U1_PLD_IT10 0x400102a8u +#define CYREG_B0_P1_U1_PLD_IT11 0x400102acu +#define CYREG_B0_P1_U1_PLD_ORT0 0x400102b0u +#define CYREG_B0_P1_U1_PLD_ORT1 0x400102b2u +#define CYREG_B0_P1_U1_PLD_ORT2 0x400102b4u +#define CYREG_B0_P1_U1_PLD_ORT3 0x400102b6u +#define CYREG_B0_P1_U1_MC_CFG_CEN_CONST 0x400102b8u +#define CYREG_B0_P1_U1_MC_CFG_XORFB 0x400102bau +#define CYREG_B0_P1_U1_MC_CFG_SET_RESET 0x400102bcu +#define CYREG_B0_P1_U1_MC_CFG_BYPASS 0x400102beu +#define CYREG_B0_P1_U1_CFG0 0x400102c0u +#define CYREG_B0_P1_U1_CFG1 0x400102c1u +#define CYREG_B0_P1_U1_CFG2 0x400102c2u +#define CYREG_B0_P1_U1_CFG3 0x400102c3u +#define CYREG_B0_P1_U1_CFG4 0x400102c4u +#define CYREG_B0_P1_U1_CFG5 0x400102c5u +#define CYREG_B0_P1_U1_CFG6 0x400102c6u +#define CYREG_B0_P1_U1_CFG7 0x400102c7u +#define CYREG_B0_P1_U1_CFG8 0x400102c8u +#define CYREG_B0_P1_U1_CFG9 0x400102c9u +#define CYREG_B0_P1_U1_CFG10 0x400102cau +#define CYREG_B0_P1_U1_CFG11 0x400102cbu +#define CYREG_B0_P1_U1_CFG12 0x400102ccu +#define CYREG_B0_P1_U1_CFG13 0x400102cdu +#define CYREG_B0_P1_U1_CFG14 0x400102ceu +#define CYREG_B0_P1_U1_CFG15 0x400102cfu +#define CYREG_B0_P1_U1_CFG16 0x400102d0u +#define CYREG_B0_P1_U1_CFG17 0x400102d1u +#define CYREG_B0_P1_U1_CFG18 0x400102d2u +#define CYREG_B0_P1_U1_CFG19 0x400102d3u +#define CYREG_B0_P1_U1_CFG20 0x400102d4u +#define CYREG_B0_P1_U1_CFG21 0x400102d5u +#define CYREG_B0_P1_U1_CFG22 0x400102d6u +#define CYREG_B0_P1_U1_CFG23 0x400102d7u +#define CYREG_B0_P1_U1_CFG24 0x400102d8u +#define CYREG_B0_P1_U1_CFG25 0x400102d9u +#define CYREG_B0_P1_U1_CFG26 0x400102dau +#define CYREG_B0_P1_U1_CFG27 0x400102dbu +#define CYREG_B0_P1_U1_CFG28 0x400102dcu +#define CYREG_B0_P1_U1_CFG29 0x400102ddu +#define CYREG_B0_P1_U1_CFG30 0x400102deu +#define CYREG_B0_P1_U1_CFG31 0x400102dfu +#define CYREG_B0_P1_U1_DCFG0 0x400102e0u +#define CYREG_B0_P1_U1_DCFG1 0x400102e2u +#define CYREG_B0_P1_U1_DCFG2 0x400102e4u +#define CYREG_B0_P1_U1_DCFG3 0x400102e6u +#define CYREG_B0_P1_U1_DCFG4 0x400102e8u +#define CYREG_B0_P1_U1_DCFG5 0x400102eau +#define CYREG_B0_P1_U1_DCFG6 0x400102ecu +#define CYREG_B0_P1_U1_DCFG7 0x400102eeu +#define CYDEV_UCFG_B0_P1_ROUTE_BASE 0x40010300u +#define CYDEV_UCFG_B0_P1_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P2_BASE 0x40010400u +#define CYDEV_UCFG_B0_P2_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P2_U0_BASE 0x40010400u +#define CYDEV_UCFG_B0_P2_U0_SIZE 0x00000070u +#define CYREG_B0_P2_U0_PLD_IT0 0x40010400u +#define CYREG_B0_P2_U0_PLD_IT1 0x40010404u +#define CYREG_B0_P2_U0_PLD_IT2 0x40010408u +#define CYREG_B0_P2_U0_PLD_IT3 0x4001040cu +#define CYREG_B0_P2_U0_PLD_IT4 0x40010410u +#define CYREG_B0_P2_U0_PLD_IT5 0x40010414u +#define CYREG_B0_P2_U0_PLD_IT6 0x40010418u +#define CYREG_B0_P2_U0_PLD_IT7 0x4001041cu +#define CYREG_B0_P2_U0_PLD_IT8 0x40010420u +#define CYREG_B0_P2_U0_PLD_IT9 0x40010424u +#define CYREG_B0_P2_U0_PLD_IT10 0x40010428u +#define CYREG_B0_P2_U0_PLD_IT11 0x4001042cu +#define CYREG_B0_P2_U0_PLD_ORT0 0x40010430u +#define CYREG_B0_P2_U0_PLD_ORT1 0x40010432u +#define CYREG_B0_P2_U0_PLD_ORT2 0x40010434u +#define CYREG_B0_P2_U0_PLD_ORT3 0x40010436u +#define CYREG_B0_P2_U0_MC_CFG_CEN_CONST 0x40010438u +#define CYREG_B0_P2_U0_MC_CFG_XORFB 0x4001043au +#define CYREG_B0_P2_U0_MC_CFG_SET_RESET 0x4001043cu +#define CYREG_B0_P2_U0_MC_CFG_BYPASS 0x4001043eu +#define CYREG_B0_P2_U0_CFG0 0x40010440u +#define CYREG_B0_P2_U0_CFG1 0x40010441u +#define CYREG_B0_P2_U0_CFG2 0x40010442u +#define CYREG_B0_P2_U0_CFG3 0x40010443u +#define CYREG_B0_P2_U0_CFG4 0x40010444u +#define CYREG_B0_P2_U0_CFG5 0x40010445u +#define CYREG_B0_P2_U0_CFG6 0x40010446u +#define CYREG_B0_P2_U0_CFG7 0x40010447u +#define CYREG_B0_P2_U0_CFG8 0x40010448u +#define CYREG_B0_P2_U0_CFG9 0x40010449u +#define CYREG_B0_P2_U0_CFG10 0x4001044au +#define CYREG_B0_P2_U0_CFG11 0x4001044bu +#define CYREG_B0_P2_U0_CFG12 0x4001044cu +#define CYREG_B0_P2_U0_CFG13 0x4001044du +#define CYREG_B0_P2_U0_CFG14 0x4001044eu +#define CYREG_B0_P2_U0_CFG15 0x4001044fu +#define CYREG_B0_P2_U0_CFG16 0x40010450u +#define CYREG_B0_P2_U0_CFG17 0x40010451u +#define CYREG_B0_P2_U0_CFG18 0x40010452u +#define CYREG_B0_P2_U0_CFG19 0x40010453u +#define CYREG_B0_P2_U0_CFG20 0x40010454u +#define CYREG_B0_P2_U0_CFG21 0x40010455u +#define CYREG_B0_P2_U0_CFG22 0x40010456u +#define CYREG_B0_P2_U0_CFG23 0x40010457u +#define CYREG_B0_P2_U0_CFG24 0x40010458u +#define CYREG_B0_P2_U0_CFG25 0x40010459u +#define CYREG_B0_P2_U0_CFG26 0x4001045au +#define CYREG_B0_P2_U0_CFG27 0x4001045bu +#define CYREG_B0_P2_U0_CFG28 0x4001045cu +#define CYREG_B0_P2_U0_CFG29 0x4001045du +#define CYREG_B0_P2_U0_CFG30 0x4001045eu +#define CYREG_B0_P2_U0_CFG31 0x4001045fu +#define CYREG_B0_P2_U0_DCFG0 0x40010460u +#define CYREG_B0_P2_U0_DCFG1 0x40010462u +#define CYREG_B0_P2_U0_DCFG2 0x40010464u +#define CYREG_B0_P2_U0_DCFG3 0x40010466u +#define CYREG_B0_P2_U0_DCFG4 0x40010468u +#define CYREG_B0_P2_U0_DCFG5 0x4001046au +#define CYREG_B0_P2_U0_DCFG6 0x4001046cu +#define CYREG_B0_P2_U0_DCFG7 0x4001046eu +#define CYDEV_UCFG_B0_P2_U1_BASE 0x40010480u +#define CYDEV_UCFG_B0_P2_U1_SIZE 0x00000070u +#define CYREG_B0_P2_U1_PLD_IT0 0x40010480u +#define CYREG_B0_P2_U1_PLD_IT1 0x40010484u +#define CYREG_B0_P2_U1_PLD_IT2 0x40010488u +#define CYREG_B0_P2_U1_PLD_IT3 0x4001048cu +#define CYREG_B0_P2_U1_PLD_IT4 0x40010490u +#define CYREG_B0_P2_U1_PLD_IT5 0x40010494u +#define CYREG_B0_P2_U1_PLD_IT6 0x40010498u +#define CYREG_B0_P2_U1_PLD_IT7 0x4001049cu +#define CYREG_B0_P2_U1_PLD_IT8 0x400104a0u +#define CYREG_B0_P2_U1_PLD_IT9 0x400104a4u +#define CYREG_B0_P2_U1_PLD_IT10 0x400104a8u +#define CYREG_B0_P2_U1_PLD_IT11 0x400104acu +#define CYREG_B0_P2_U1_PLD_ORT0 0x400104b0u +#define CYREG_B0_P2_U1_PLD_ORT1 0x400104b2u +#define CYREG_B0_P2_U1_PLD_ORT2 0x400104b4u +#define CYREG_B0_P2_U1_PLD_ORT3 0x400104b6u +#define CYREG_B0_P2_U1_MC_CFG_CEN_CONST 0x400104b8u +#define CYREG_B0_P2_U1_MC_CFG_XORFB 0x400104bau +#define CYREG_B0_P2_U1_MC_CFG_SET_RESET 0x400104bcu +#define CYREG_B0_P2_U1_MC_CFG_BYPASS 0x400104beu +#define CYREG_B0_P2_U1_CFG0 0x400104c0u +#define CYREG_B0_P2_U1_CFG1 0x400104c1u +#define CYREG_B0_P2_U1_CFG2 0x400104c2u +#define CYREG_B0_P2_U1_CFG3 0x400104c3u +#define CYREG_B0_P2_U1_CFG4 0x400104c4u +#define CYREG_B0_P2_U1_CFG5 0x400104c5u +#define CYREG_B0_P2_U1_CFG6 0x400104c6u +#define CYREG_B0_P2_U1_CFG7 0x400104c7u +#define CYREG_B0_P2_U1_CFG8 0x400104c8u +#define CYREG_B0_P2_U1_CFG9 0x400104c9u +#define CYREG_B0_P2_U1_CFG10 0x400104cau +#define CYREG_B0_P2_U1_CFG11 0x400104cbu +#define CYREG_B0_P2_U1_CFG12 0x400104ccu +#define CYREG_B0_P2_U1_CFG13 0x400104cdu +#define CYREG_B0_P2_U1_CFG14 0x400104ceu +#define CYREG_B0_P2_U1_CFG15 0x400104cfu +#define CYREG_B0_P2_U1_CFG16 0x400104d0u +#define CYREG_B0_P2_U1_CFG17 0x400104d1u +#define CYREG_B0_P2_U1_CFG18 0x400104d2u +#define CYREG_B0_P2_U1_CFG19 0x400104d3u +#define CYREG_B0_P2_U1_CFG20 0x400104d4u +#define CYREG_B0_P2_U1_CFG21 0x400104d5u +#define CYREG_B0_P2_U1_CFG22 0x400104d6u +#define CYREG_B0_P2_U1_CFG23 0x400104d7u +#define CYREG_B0_P2_U1_CFG24 0x400104d8u +#define CYREG_B0_P2_U1_CFG25 0x400104d9u +#define CYREG_B0_P2_U1_CFG26 0x400104dau +#define CYREG_B0_P2_U1_CFG27 0x400104dbu +#define CYREG_B0_P2_U1_CFG28 0x400104dcu +#define CYREG_B0_P2_U1_CFG29 0x400104ddu +#define CYREG_B0_P2_U1_CFG30 0x400104deu +#define CYREG_B0_P2_U1_CFG31 0x400104dfu +#define CYREG_B0_P2_U1_DCFG0 0x400104e0u +#define CYREG_B0_P2_U1_DCFG1 0x400104e2u +#define CYREG_B0_P2_U1_DCFG2 0x400104e4u +#define CYREG_B0_P2_U1_DCFG3 0x400104e6u +#define CYREG_B0_P2_U1_DCFG4 0x400104e8u +#define CYREG_B0_P2_U1_DCFG5 0x400104eau +#define CYREG_B0_P2_U1_DCFG6 0x400104ecu +#define CYREG_B0_P2_U1_DCFG7 0x400104eeu +#define CYDEV_UCFG_B0_P2_ROUTE_BASE 0x40010500u +#define CYDEV_UCFG_B0_P2_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P3_BASE 0x40010600u +#define CYDEV_UCFG_B0_P3_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P3_U0_BASE 0x40010600u +#define CYDEV_UCFG_B0_P3_U0_SIZE 0x00000070u +#define CYREG_B0_P3_U0_PLD_IT0 0x40010600u +#define CYREG_B0_P3_U0_PLD_IT1 0x40010604u +#define CYREG_B0_P3_U0_PLD_IT2 0x40010608u +#define CYREG_B0_P3_U0_PLD_IT3 0x4001060cu +#define CYREG_B0_P3_U0_PLD_IT4 0x40010610u +#define CYREG_B0_P3_U0_PLD_IT5 0x40010614u +#define CYREG_B0_P3_U0_PLD_IT6 0x40010618u +#define CYREG_B0_P3_U0_PLD_IT7 0x4001061cu +#define CYREG_B0_P3_U0_PLD_IT8 0x40010620u +#define CYREG_B0_P3_U0_PLD_IT9 0x40010624u +#define CYREG_B0_P3_U0_PLD_IT10 0x40010628u +#define CYREG_B0_P3_U0_PLD_IT11 0x4001062cu +#define CYREG_B0_P3_U0_PLD_ORT0 0x40010630u +#define CYREG_B0_P3_U0_PLD_ORT1 0x40010632u +#define CYREG_B0_P3_U0_PLD_ORT2 0x40010634u +#define CYREG_B0_P3_U0_PLD_ORT3 0x40010636u +#define CYREG_B0_P3_U0_MC_CFG_CEN_CONST 0x40010638u +#define CYREG_B0_P3_U0_MC_CFG_XORFB 0x4001063au +#define CYREG_B0_P3_U0_MC_CFG_SET_RESET 0x4001063cu +#define CYREG_B0_P3_U0_MC_CFG_BYPASS 0x4001063eu +#define CYREG_B0_P3_U0_CFG0 0x40010640u +#define CYREG_B0_P3_U0_CFG1 0x40010641u +#define CYREG_B0_P3_U0_CFG2 0x40010642u +#define CYREG_B0_P3_U0_CFG3 0x40010643u +#define CYREG_B0_P3_U0_CFG4 0x40010644u +#define CYREG_B0_P3_U0_CFG5 0x40010645u +#define CYREG_B0_P3_U0_CFG6 0x40010646u +#define CYREG_B0_P3_U0_CFG7 0x40010647u +#define CYREG_B0_P3_U0_CFG8 0x40010648u +#define CYREG_B0_P3_U0_CFG9 0x40010649u +#define CYREG_B0_P3_U0_CFG10 0x4001064au +#define CYREG_B0_P3_U0_CFG11 0x4001064bu +#define CYREG_B0_P3_U0_CFG12 0x4001064cu +#define CYREG_B0_P3_U0_CFG13 0x4001064du +#define CYREG_B0_P3_U0_CFG14 0x4001064eu +#define CYREG_B0_P3_U0_CFG15 0x4001064fu +#define CYREG_B0_P3_U0_CFG16 0x40010650u +#define CYREG_B0_P3_U0_CFG17 0x40010651u +#define CYREG_B0_P3_U0_CFG18 0x40010652u +#define CYREG_B0_P3_U0_CFG19 0x40010653u +#define CYREG_B0_P3_U0_CFG20 0x40010654u +#define CYREG_B0_P3_U0_CFG21 0x40010655u +#define CYREG_B0_P3_U0_CFG22 0x40010656u +#define CYREG_B0_P3_U0_CFG23 0x40010657u +#define CYREG_B0_P3_U0_CFG24 0x40010658u +#define CYREG_B0_P3_U0_CFG25 0x40010659u +#define CYREG_B0_P3_U0_CFG26 0x4001065au +#define CYREG_B0_P3_U0_CFG27 0x4001065bu +#define CYREG_B0_P3_U0_CFG28 0x4001065cu +#define CYREG_B0_P3_U0_CFG29 0x4001065du +#define CYREG_B0_P3_U0_CFG30 0x4001065eu +#define CYREG_B0_P3_U0_CFG31 0x4001065fu +#define CYREG_B0_P3_U0_DCFG0 0x40010660u +#define CYREG_B0_P3_U0_DCFG1 0x40010662u +#define CYREG_B0_P3_U0_DCFG2 0x40010664u +#define CYREG_B0_P3_U0_DCFG3 0x40010666u +#define CYREG_B0_P3_U0_DCFG4 0x40010668u +#define CYREG_B0_P3_U0_DCFG5 0x4001066au +#define CYREG_B0_P3_U0_DCFG6 0x4001066cu +#define CYREG_B0_P3_U0_DCFG7 0x4001066eu +#define CYDEV_UCFG_B0_P3_U1_BASE 0x40010680u +#define CYDEV_UCFG_B0_P3_U1_SIZE 0x00000070u +#define CYREG_B0_P3_U1_PLD_IT0 0x40010680u +#define CYREG_B0_P3_U1_PLD_IT1 0x40010684u +#define CYREG_B0_P3_U1_PLD_IT2 0x40010688u +#define CYREG_B0_P3_U1_PLD_IT3 0x4001068cu +#define CYREG_B0_P3_U1_PLD_IT4 0x40010690u +#define CYREG_B0_P3_U1_PLD_IT5 0x40010694u +#define CYREG_B0_P3_U1_PLD_IT6 0x40010698u +#define CYREG_B0_P3_U1_PLD_IT7 0x4001069cu +#define CYREG_B0_P3_U1_PLD_IT8 0x400106a0u +#define CYREG_B0_P3_U1_PLD_IT9 0x400106a4u +#define CYREG_B0_P3_U1_PLD_IT10 0x400106a8u +#define CYREG_B0_P3_U1_PLD_IT11 0x400106acu +#define CYREG_B0_P3_U1_PLD_ORT0 0x400106b0u +#define CYREG_B0_P3_U1_PLD_ORT1 0x400106b2u +#define CYREG_B0_P3_U1_PLD_ORT2 0x400106b4u +#define CYREG_B0_P3_U1_PLD_ORT3 0x400106b6u +#define CYREG_B0_P3_U1_MC_CFG_CEN_CONST 0x400106b8u +#define CYREG_B0_P3_U1_MC_CFG_XORFB 0x400106bau +#define CYREG_B0_P3_U1_MC_CFG_SET_RESET 0x400106bcu +#define CYREG_B0_P3_U1_MC_CFG_BYPASS 0x400106beu +#define CYREG_B0_P3_U1_CFG0 0x400106c0u +#define CYREG_B0_P3_U1_CFG1 0x400106c1u +#define CYREG_B0_P3_U1_CFG2 0x400106c2u +#define CYREG_B0_P3_U1_CFG3 0x400106c3u +#define CYREG_B0_P3_U1_CFG4 0x400106c4u +#define CYREG_B0_P3_U1_CFG5 0x400106c5u +#define CYREG_B0_P3_U1_CFG6 0x400106c6u +#define CYREG_B0_P3_U1_CFG7 0x400106c7u +#define CYREG_B0_P3_U1_CFG8 0x400106c8u +#define CYREG_B0_P3_U1_CFG9 0x400106c9u +#define CYREG_B0_P3_U1_CFG10 0x400106cau +#define CYREG_B0_P3_U1_CFG11 0x400106cbu +#define CYREG_B0_P3_U1_CFG12 0x400106ccu +#define CYREG_B0_P3_U1_CFG13 0x400106cdu +#define CYREG_B0_P3_U1_CFG14 0x400106ceu +#define CYREG_B0_P3_U1_CFG15 0x400106cfu +#define CYREG_B0_P3_U1_CFG16 0x400106d0u +#define CYREG_B0_P3_U1_CFG17 0x400106d1u +#define CYREG_B0_P3_U1_CFG18 0x400106d2u +#define CYREG_B0_P3_U1_CFG19 0x400106d3u +#define CYREG_B0_P3_U1_CFG20 0x400106d4u +#define CYREG_B0_P3_U1_CFG21 0x400106d5u +#define CYREG_B0_P3_U1_CFG22 0x400106d6u +#define CYREG_B0_P3_U1_CFG23 0x400106d7u +#define CYREG_B0_P3_U1_CFG24 0x400106d8u +#define CYREG_B0_P3_U1_CFG25 0x400106d9u +#define CYREG_B0_P3_U1_CFG26 0x400106dau +#define CYREG_B0_P3_U1_CFG27 0x400106dbu +#define CYREG_B0_P3_U1_CFG28 0x400106dcu +#define CYREG_B0_P3_U1_CFG29 0x400106ddu +#define CYREG_B0_P3_U1_CFG30 0x400106deu +#define CYREG_B0_P3_U1_CFG31 0x400106dfu +#define CYREG_B0_P3_U1_DCFG0 0x400106e0u +#define CYREG_B0_P3_U1_DCFG1 0x400106e2u +#define CYREG_B0_P3_U1_DCFG2 0x400106e4u +#define CYREG_B0_P3_U1_DCFG3 0x400106e6u +#define CYREG_B0_P3_U1_DCFG4 0x400106e8u +#define CYREG_B0_P3_U1_DCFG5 0x400106eau +#define CYREG_B0_P3_U1_DCFG6 0x400106ecu +#define CYREG_B0_P3_U1_DCFG7 0x400106eeu +#define CYDEV_UCFG_B0_P3_ROUTE_BASE 0x40010700u +#define CYDEV_UCFG_B0_P3_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P4_BASE 0x40010800u +#define CYDEV_UCFG_B0_P4_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P4_U0_BASE 0x40010800u +#define CYDEV_UCFG_B0_P4_U0_SIZE 0x00000070u +#define CYREG_B0_P4_U0_PLD_IT0 0x40010800u +#define CYREG_B0_P4_U0_PLD_IT1 0x40010804u +#define CYREG_B0_P4_U0_PLD_IT2 0x40010808u +#define CYREG_B0_P4_U0_PLD_IT3 0x4001080cu +#define CYREG_B0_P4_U0_PLD_IT4 0x40010810u +#define CYREG_B0_P4_U0_PLD_IT5 0x40010814u +#define CYREG_B0_P4_U0_PLD_IT6 0x40010818u +#define CYREG_B0_P4_U0_PLD_IT7 0x4001081cu +#define CYREG_B0_P4_U0_PLD_IT8 0x40010820u +#define CYREG_B0_P4_U0_PLD_IT9 0x40010824u +#define CYREG_B0_P4_U0_PLD_IT10 0x40010828u +#define CYREG_B0_P4_U0_PLD_IT11 0x4001082cu +#define CYREG_B0_P4_U0_PLD_ORT0 0x40010830u +#define CYREG_B0_P4_U0_PLD_ORT1 0x40010832u +#define CYREG_B0_P4_U0_PLD_ORT2 0x40010834u +#define CYREG_B0_P4_U0_PLD_ORT3 0x40010836u +#define CYREG_B0_P4_U0_MC_CFG_CEN_CONST 0x40010838u +#define CYREG_B0_P4_U0_MC_CFG_XORFB 0x4001083au +#define CYREG_B0_P4_U0_MC_CFG_SET_RESET 0x4001083cu +#define CYREG_B0_P4_U0_MC_CFG_BYPASS 0x4001083eu +#define CYREG_B0_P4_U0_CFG0 0x40010840u +#define CYREG_B0_P4_U0_CFG1 0x40010841u +#define CYREG_B0_P4_U0_CFG2 0x40010842u +#define CYREG_B0_P4_U0_CFG3 0x40010843u +#define CYREG_B0_P4_U0_CFG4 0x40010844u +#define CYREG_B0_P4_U0_CFG5 0x40010845u +#define CYREG_B0_P4_U0_CFG6 0x40010846u +#define CYREG_B0_P4_U0_CFG7 0x40010847u +#define CYREG_B0_P4_U0_CFG8 0x40010848u +#define CYREG_B0_P4_U0_CFG9 0x40010849u +#define CYREG_B0_P4_U0_CFG10 0x4001084au +#define CYREG_B0_P4_U0_CFG11 0x4001084bu +#define CYREG_B0_P4_U0_CFG12 0x4001084cu +#define CYREG_B0_P4_U0_CFG13 0x4001084du +#define CYREG_B0_P4_U0_CFG14 0x4001084eu +#define CYREG_B0_P4_U0_CFG15 0x4001084fu +#define CYREG_B0_P4_U0_CFG16 0x40010850u +#define CYREG_B0_P4_U0_CFG17 0x40010851u +#define CYREG_B0_P4_U0_CFG18 0x40010852u +#define CYREG_B0_P4_U0_CFG19 0x40010853u +#define CYREG_B0_P4_U0_CFG20 0x40010854u +#define CYREG_B0_P4_U0_CFG21 0x40010855u +#define CYREG_B0_P4_U0_CFG22 0x40010856u +#define CYREG_B0_P4_U0_CFG23 0x40010857u +#define CYREG_B0_P4_U0_CFG24 0x40010858u +#define CYREG_B0_P4_U0_CFG25 0x40010859u +#define CYREG_B0_P4_U0_CFG26 0x4001085au +#define CYREG_B0_P4_U0_CFG27 0x4001085bu +#define CYREG_B0_P4_U0_CFG28 0x4001085cu +#define CYREG_B0_P4_U0_CFG29 0x4001085du +#define CYREG_B0_P4_U0_CFG30 0x4001085eu +#define CYREG_B0_P4_U0_CFG31 0x4001085fu +#define CYREG_B0_P4_U0_DCFG0 0x40010860u +#define CYREG_B0_P4_U0_DCFG1 0x40010862u +#define CYREG_B0_P4_U0_DCFG2 0x40010864u +#define CYREG_B0_P4_U0_DCFG3 0x40010866u +#define CYREG_B0_P4_U0_DCFG4 0x40010868u +#define CYREG_B0_P4_U0_DCFG5 0x4001086au +#define CYREG_B0_P4_U0_DCFG6 0x4001086cu +#define CYREG_B0_P4_U0_DCFG7 0x4001086eu +#define CYDEV_UCFG_B0_P4_U1_BASE 0x40010880u +#define CYDEV_UCFG_B0_P4_U1_SIZE 0x00000070u +#define CYREG_B0_P4_U1_PLD_IT0 0x40010880u +#define CYREG_B0_P4_U1_PLD_IT1 0x40010884u +#define CYREG_B0_P4_U1_PLD_IT2 0x40010888u +#define CYREG_B0_P4_U1_PLD_IT3 0x4001088cu +#define CYREG_B0_P4_U1_PLD_IT4 0x40010890u +#define CYREG_B0_P4_U1_PLD_IT5 0x40010894u +#define CYREG_B0_P4_U1_PLD_IT6 0x40010898u +#define CYREG_B0_P4_U1_PLD_IT7 0x4001089cu +#define CYREG_B0_P4_U1_PLD_IT8 0x400108a0u +#define CYREG_B0_P4_U1_PLD_IT9 0x400108a4u +#define CYREG_B0_P4_U1_PLD_IT10 0x400108a8u +#define CYREG_B0_P4_U1_PLD_IT11 0x400108acu +#define CYREG_B0_P4_U1_PLD_ORT0 0x400108b0u +#define CYREG_B0_P4_U1_PLD_ORT1 0x400108b2u +#define CYREG_B0_P4_U1_PLD_ORT2 0x400108b4u +#define CYREG_B0_P4_U1_PLD_ORT3 0x400108b6u +#define CYREG_B0_P4_U1_MC_CFG_CEN_CONST 0x400108b8u +#define CYREG_B0_P4_U1_MC_CFG_XORFB 0x400108bau +#define CYREG_B0_P4_U1_MC_CFG_SET_RESET 0x400108bcu +#define CYREG_B0_P4_U1_MC_CFG_BYPASS 0x400108beu +#define CYREG_B0_P4_U1_CFG0 0x400108c0u +#define CYREG_B0_P4_U1_CFG1 0x400108c1u +#define CYREG_B0_P4_U1_CFG2 0x400108c2u +#define CYREG_B0_P4_U1_CFG3 0x400108c3u +#define CYREG_B0_P4_U1_CFG4 0x400108c4u +#define CYREG_B0_P4_U1_CFG5 0x400108c5u +#define CYREG_B0_P4_U1_CFG6 0x400108c6u +#define CYREG_B0_P4_U1_CFG7 0x400108c7u +#define CYREG_B0_P4_U1_CFG8 0x400108c8u +#define CYREG_B0_P4_U1_CFG9 0x400108c9u +#define CYREG_B0_P4_U1_CFG10 0x400108cau +#define CYREG_B0_P4_U1_CFG11 0x400108cbu +#define CYREG_B0_P4_U1_CFG12 0x400108ccu +#define CYREG_B0_P4_U1_CFG13 0x400108cdu +#define CYREG_B0_P4_U1_CFG14 0x400108ceu +#define CYREG_B0_P4_U1_CFG15 0x400108cfu +#define CYREG_B0_P4_U1_CFG16 0x400108d0u +#define CYREG_B0_P4_U1_CFG17 0x400108d1u +#define CYREG_B0_P4_U1_CFG18 0x400108d2u +#define CYREG_B0_P4_U1_CFG19 0x400108d3u +#define CYREG_B0_P4_U1_CFG20 0x400108d4u +#define CYREG_B0_P4_U1_CFG21 0x400108d5u +#define CYREG_B0_P4_U1_CFG22 0x400108d6u +#define CYREG_B0_P4_U1_CFG23 0x400108d7u +#define CYREG_B0_P4_U1_CFG24 0x400108d8u +#define CYREG_B0_P4_U1_CFG25 0x400108d9u +#define CYREG_B0_P4_U1_CFG26 0x400108dau +#define CYREG_B0_P4_U1_CFG27 0x400108dbu +#define CYREG_B0_P4_U1_CFG28 0x400108dcu +#define CYREG_B0_P4_U1_CFG29 0x400108ddu +#define CYREG_B0_P4_U1_CFG30 0x400108deu +#define CYREG_B0_P4_U1_CFG31 0x400108dfu +#define CYREG_B0_P4_U1_DCFG0 0x400108e0u +#define CYREG_B0_P4_U1_DCFG1 0x400108e2u +#define CYREG_B0_P4_U1_DCFG2 0x400108e4u +#define CYREG_B0_P4_U1_DCFG3 0x400108e6u +#define CYREG_B0_P4_U1_DCFG4 0x400108e8u +#define CYREG_B0_P4_U1_DCFG5 0x400108eau +#define CYREG_B0_P4_U1_DCFG6 0x400108ecu +#define CYREG_B0_P4_U1_DCFG7 0x400108eeu +#define CYDEV_UCFG_B0_P4_ROUTE_BASE 0x40010900u +#define CYDEV_UCFG_B0_P4_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P5_BASE 0x40010a00u +#define CYDEV_UCFG_B0_P5_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P5_U0_BASE 0x40010a00u +#define CYDEV_UCFG_B0_P5_U0_SIZE 0x00000070u +#define CYREG_B0_P5_U0_PLD_IT0 0x40010a00u +#define CYREG_B0_P5_U0_PLD_IT1 0x40010a04u +#define CYREG_B0_P5_U0_PLD_IT2 0x40010a08u +#define CYREG_B0_P5_U0_PLD_IT3 0x40010a0cu +#define CYREG_B0_P5_U0_PLD_IT4 0x40010a10u +#define CYREG_B0_P5_U0_PLD_IT5 0x40010a14u +#define CYREG_B0_P5_U0_PLD_IT6 0x40010a18u +#define CYREG_B0_P5_U0_PLD_IT7 0x40010a1cu +#define CYREG_B0_P5_U0_PLD_IT8 0x40010a20u +#define CYREG_B0_P5_U0_PLD_IT9 0x40010a24u +#define CYREG_B0_P5_U0_PLD_IT10 0x40010a28u +#define CYREG_B0_P5_U0_PLD_IT11 0x40010a2cu +#define CYREG_B0_P5_U0_PLD_ORT0 0x40010a30u +#define CYREG_B0_P5_U0_PLD_ORT1 0x40010a32u +#define CYREG_B0_P5_U0_PLD_ORT2 0x40010a34u +#define CYREG_B0_P5_U0_PLD_ORT3 0x40010a36u +#define CYREG_B0_P5_U0_MC_CFG_CEN_CONST 0x40010a38u +#define CYREG_B0_P5_U0_MC_CFG_XORFB 0x40010a3au +#define CYREG_B0_P5_U0_MC_CFG_SET_RESET 0x40010a3cu +#define CYREG_B0_P5_U0_MC_CFG_BYPASS 0x40010a3eu +#define CYREG_B0_P5_U0_CFG0 0x40010a40u +#define CYREG_B0_P5_U0_CFG1 0x40010a41u +#define CYREG_B0_P5_U0_CFG2 0x40010a42u +#define CYREG_B0_P5_U0_CFG3 0x40010a43u +#define CYREG_B0_P5_U0_CFG4 0x40010a44u +#define CYREG_B0_P5_U0_CFG5 0x40010a45u +#define CYREG_B0_P5_U0_CFG6 0x40010a46u +#define CYREG_B0_P5_U0_CFG7 0x40010a47u +#define CYREG_B0_P5_U0_CFG8 0x40010a48u +#define CYREG_B0_P5_U0_CFG9 0x40010a49u +#define CYREG_B0_P5_U0_CFG10 0x40010a4au +#define CYREG_B0_P5_U0_CFG11 0x40010a4bu +#define CYREG_B0_P5_U0_CFG12 0x40010a4cu +#define CYREG_B0_P5_U0_CFG13 0x40010a4du +#define CYREG_B0_P5_U0_CFG14 0x40010a4eu +#define CYREG_B0_P5_U0_CFG15 0x40010a4fu +#define CYREG_B0_P5_U0_CFG16 0x40010a50u +#define CYREG_B0_P5_U0_CFG17 0x40010a51u +#define CYREG_B0_P5_U0_CFG18 0x40010a52u +#define CYREG_B0_P5_U0_CFG19 0x40010a53u +#define CYREG_B0_P5_U0_CFG20 0x40010a54u +#define CYREG_B0_P5_U0_CFG21 0x40010a55u +#define CYREG_B0_P5_U0_CFG22 0x40010a56u +#define CYREG_B0_P5_U0_CFG23 0x40010a57u +#define CYREG_B0_P5_U0_CFG24 0x40010a58u +#define CYREG_B0_P5_U0_CFG25 0x40010a59u +#define CYREG_B0_P5_U0_CFG26 0x40010a5au +#define CYREG_B0_P5_U0_CFG27 0x40010a5bu +#define CYREG_B0_P5_U0_CFG28 0x40010a5cu +#define CYREG_B0_P5_U0_CFG29 0x40010a5du +#define CYREG_B0_P5_U0_CFG30 0x40010a5eu +#define CYREG_B0_P5_U0_CFG31 0x40010a5fu +#define CYREG_B0_P5_U0_DCFG0 0x40010a60u +#define CYREG_B0_P5_U0_DCFG1 0x40010a62u +#define CYREG_B0_P5_U0_DCFG2 0x40010a64u +#define CYREG_B0_P5_U0_DCFG3 0x40010a66u +#define CYREG_B0_P5_U0_DCFG4 0x40010a68u +#define CYREG_B0_P5_U0_DCFG5 0x40010a6au +#define CYREG_B0_P5_U0_DCFG6 0x40010a6cu +#define CYREG_B0_P5_U0_DCFG7 0x40010a6eu +#define CYDEV_UCFG_B0_P5_U1_BASE 0x40010a80u +#define CYDEV_UCFG_B0_P5_U1_SIZE 0x00000070u +#define CYREG_B0_P5_U1_PLD_IT0 0x40010a80u +#define CYREG_B0_P5_U1_PLD_IT1 0x40010a84u +#define CYREG_B0_P5_U1_PLD_IT2 0x40010a88u +#define CYREG_B0_P5_U1_PLD_IT3 0x40010a8cu +#define CYREG_B0_P5_U1_PLD_IT4 0x40010a90u +#define CYREG_B0_P5_U1_PLD_IT5 0x40010a94u +#define CYREG_B0_P5_U1_PLD_IT6 0x40010a98u +#define CYREG_B0_P5_U1_PLD_IT7 0x40010a9cu +#define CYREG_B0_P5_U1_PLD_IT8 0x40010aa0u +#define CYREG_B0_P5_U1_PLD_IT9 0x40010aa4u +#define CYREG_B0_P5_U1_PLD_IT10 0x40010aa8u +#define CYREG_B0_P5_U1_PLD_IT11 0x40010aacu +#define CYREG_B0_P5_U1_PLD_ORT0 0x40010ab0u +#define CYREG_B0_P5_U1_PLD_ORT1 0x40010ab2u +#define CYREG_B0_P5_U1_PLD_ORT2 0x40010ab4u +#define CYREG_B0_P5_U1_PLD_ORT3 0x40010ab6u +#define CYREG_B0_P5_U1_MC_CFG_CEN_CONST 0x40010ab8u +#define CYREG_B0_P5_U1_MC_CFG_XORFB 0x40010abau +#define CYREG_B0_P5_U1_MC_CFG_SET_RESET 0x40010abcu +#define CYREG_B0_P5_U1_MC_CFG_BYPASS 0x40010abeu +#define CYREG_B0_P5_U1_CFG0 0x40010ac0u +#define CYREG_B0_P5_U1_CFG1 0x40010ac1u +#define CYREG_B0_P5_U1_CFG2 0x40010ac2u +#define CYREG_B0_P5_U1_CFG3 0x40010ac3u +#define CYREG_B0_P5_U1_CFG4 0x40010ac4u +#define CYREG_B0_P5_U1_CFG5 0x40010ac5u +#define CYREG_B0_P5_U1_CFG6 0x40010ac6u +#define CYREG_B0_P5_U1_CFG7 0x40010ac7u +#define CYREG_B0_P5_U1_CFG8 0x40010ac8u +#define CYREG_B0_P5_U1_CFG9 0x40010ac9u +#define CYREG_B0_P5_U1_CFG10 0x40010acau +#define CYREG_B0_P5_U1_CFG11 0x40010acbu +#define CYREG_B0_P5_U1_CFG12 0x40010accu +#define CYREG_B0_P5_U1_CFG13 0x40010acdu +#define CYREG_B0_P5_U1_CFG14 0x40010aceu +#define CYREG_B0_P5_U1_CFG15 0x40010acfu +#define CYREG_B0_P5_U1_CFG16 0x40010ad0u +#define CYREG_B0_P5_U1_CFG17 0x40010ad1u +#define CYREG_B0_P5_U1_CFG18 0x40010ad2u +#define CYREG_B0_P5_U1_CFG19 0x40010ad3u +#define CYREG_B0_P5_U1_CFG20 0x40010ad4u +#define CYREG_B0_P5_U1_CFG21 0x40010ad5u +#define CYREG_B0_P5_U1_CFG22 0x40010ad6u +#define CYREG_B0_P5_U1_CFG23 0x40010ad7u +#define CYREG_B0_P5_U1_CFG24 0x40010ad8u +#define CYREG_B0_P5_U1_CFG25 0x40010ad9u +#define CYREG_B0_P5_U1_CFG26 0x40010adau +#define CYREG_B0_P5_U1_CFG27 0x40010adbu +#define CYREG_B0_P5_U1_CFG28 0x40010adcu +#define CYREG_B0_P5_U1_CFG29 0x40010addu +#define CYREG_B0_P5_U1_CFG30 0x40010adeu +#define CYREG_B0_P5_U1_CFG31 0x40010adfu +#define CYREG_B0_P5_U1_DCFG0 0x40010ae0u +#define CYREG_B0_P5_U1_DCFG1 0x40010ae2u +#define CYREG_B0_P5_U1_DCFG2 0x40010ae4u +#define CYREG_B0_P5_U1_DCFG3 0x40010ae6u +#define CYREG_B0_P5_U1_DCFG4 0x40010ae8u +#define CYREG_B0_P5_U1_DCFG5 0x40010aeau +#define CYREG_B0_P5_U1_DCFG6 0x40010aecu +#define CYREG_B0_P5_U1_DCFG7 0x40010aeeu +#define CYDEV_UCFG_B0_P5_ROUTE_BASE 0x40010b00u +#define CYDEV_UCFG_B0_P5_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P6_BASE 0x40010c00u +#define CYDEV_UCFG_B0_P6_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P6_U0_BASE 0x40010c00u +#define CYDEV_UCFG_B0_P6_U0_SIZE 0x00000070u +#define CYREG_B0_P6_U0_PLD_IT0 0x40010c00u +#define CYREG_B0_P6_U0_PLD_IT1 0x40010c04u +#define CYREG_B0_P6_U0_PLD_IT2 0x40010c08u +#define CYREG_B0_P6_U0_PLD_IT3 0x40010c0cu +#define CYREG_B0_P6_U0_PLD_IT4 0x40010c10u +#define CYREG_B0_P6_U0_PLD_IT5 0x40010c14u +#define CYREG_B0_P6_U0_PLD_IT6 0x40010c18u +#define CYREG_B0_P6_U0_PLD_IT7 0x40010c1cu +#define CYREG_B0_P6_U0_PLD_IT8 0x40010c20u +#define CYREG_B0_P6_U0_PLD_IT9 0x40010c24u +#define CYREG_B0_P6_U0_PLD_IT10 0x40010c28u +#define CYREG_B0_P6_U0_PLD_IT11 0x40010c2cu +#define CYREG_B0_P6_U0_PLD_ORT0 0x40010c30u +#define CYREG_B0_P6_U0_PLD_ORT1 0x40010c32u +#define CYREG_B0_P6_U0_PLD_ORT2 0x40010c34u +#define CYREG_B0_P6_U0_PLD_ORT3 0x40010c36u +#define CYREG_B0_P6_U0_MC_CFG_CEN_CONST 0x40010c38u +#define CYREG_B0_P6_U0_MC_CFG_XORFB 0x40010c3au +#define CYREG_B0_P6_U0_MC_CFG_SET_RESET 0x40010c3cu +#define CYREG_B0_P6_U0_MC_CFG_BYPASS 0x40010c3eu +#define CYREG_B0_P6_U0_CFG0 0x40010c40u +#define CYREG_B0_P6_U0_CFG1 0x40010c41u +#define CYREG_B0_P6_U0_CFG2 0x40010c42u +#define CYREG_B0_P6_U0_CFG3 0x40010c43u +#define CYREG_B0_P6_U0_CFG4 0x40010c44u +#define CYREG_B0_P6_U0_CFG5 0x40010c45u +#define CYREG_B0_P6_U0_CFG6 0x40010c46u +#define CYREG_B0_P6_U0_CFG7 0x40010c47u +#define CYREG_B0_P6_U0_CFG8 0x40010c48u +#define CYREG_B0_P6_U0_CFG9 0x40010c49u +#define CYREG_B0_P6_U0_CFG10 0x40010c4au +#define CYREG_B0_P6_U0_CFG11 0x40010c4bu +#define CYREG_B0_P6_U0_CFG12 0x40010c4cu +#define CYREG_B0_P6_U0_CFG13 0x40010c4du +#define CYREG_B0_P6_U0_CFG14 0x40010c4eu +#define CYREG_B0_P6_U0_CFG15 0x40010c4fu +#define CYREG_B0_P6_U0_CFG16 0x40010c50u +#define CYREG_B0_P6_U0_CFG17 0x40010c51u +#define CYREG_B0_P6_U0_CFG18 0x40010c52u +#define CYREG_B0_P6_U0_CFG19 0x40010c53u +#define CYREG_B0_P6_U0_CFG20 0x40010c54u +#define CYREG_B0_P6_U0_CFG21 0x40010c55u +#define CYREG_B0_P6_U0_CFG22 0x40010c56u +#define CYREG_B0_P6_U0_CFG23 0x40010c57u +#define CYREG_B0_P6_U0_CFG24 0x40010c58u +#define CYREG_B0_P6_U0_CFG25 0x40010c59u +#define CYREG_B0_P6_U0_CFG26 0x40010c5au +#define CYREG_B0_P6_U0_CFG27 0x40010c5bu +#define CYREG_B0_P6_U0_CFG28 0x40010c5cu +#define CYREG_B0_P6_U0_CFG29 0x40010c5du +#define CYREG_B0_P6_U0_CFG30 0x40010c5eu +#define CYREG_B0_P6_U0_CFG31 0x40010c5fu +#define CYREG_B0_P6_U0_DCFG0 0x40010c60u +#define CYREG_B0_P6_U0_DCFG1 0x40010c62u +#define CYREG_B0_P6_U0_DCFG2 0x40010c64u +#define CYREG_B0_P6_U0_DCFG3 0x40010c66u +#define CYREG_B0_P6_U0_DCFG4 0x40010c68u +#define CYREG_B0_P6_U0_DCFG5 0x40010c6au +#define CYREG_B0_P6_U0_DCFG6 0x40010c6cu +#define CYREG_B0_P6_U0_DCFG7 0x40010c6eu +#define CYDEV_UCFG_B0_P6_U1_BASE 0x40010c80u +#define CYDEV_UCFG_B0_P6_U1_SIZE 0x00000070u +#define CYREG_B0_P6_U1_PLD_IT0 0x40010c80u +#define CYREG_B0_P6_U1_PLD_IT1 0x40010c84u +#define CYREG_B0_P6_U1_PLD_IT2 0x40010c88u +#define CYREG_B0_P6_U1_PLD_IT3 0x40010c8cu +#define CYREG_B0_P6_U1_PLD_IT4 0x40010c90u +#define CYREG_B0_P6_U1_PLD_IT5 0x40010c94u +#define CYREG_B0_P6_U1_PLD_IT6 0x40010c98u +#define CYREG_B0_P6_U1_PLD_IT7 0x40010c9cu +#define CYREG_B0_P6_U1_PLD_IT8 0x40010ca0u +#define CYREG_B0_P6_U1_PLD_IT9 0x40010ca4u +#define CYREG_B0_P6_U1_PLD_IT10 0x40010ca8u +#define CYREG_B0_P6_U1_PLD_IT11 0x40010cacu +#define CYREG_B0_P6_U1_PLD_ORT0 0x40010cb0u +#define CYREG_B0_P6_U1_PLD_ORT1 0x40010cb2u +#define CYREG_B0_P6_U1_PLD_ORT2 0x40010cb4u +#define CYREG_B0_P6_U1_PLD_ORT3 0x40010cb6u +#define CYREG_B0_P6_U1_MC_CFG_CEN_CONST 0x40010cb8u +#define CYREG_B0_P6_U1_MC_CFG_XORFB 0x40010cbau +#define CYREG_B0_P6_U1_MC_CFG_SET_RESET 0x40010cbcu +#define CYREG_B0_P6_U1_MC_CFG_BYPASS 0x40010cbeu +#define CYREG_B0_P6_U1_CFG0 0x40010cc0u +#define CYREG_B0_P6_U1_CFG1 0x40010cc1u +#define CYREG_B0_P6_U1_CFG2 0x40010cc2u +#define CYREG_B0_P6_U1_CFG3 0x40010cc3u +#define CYREG_B0_P6_U1_CFG4 0x40010cc4u +#define CYREG_B0_P6_U1_CFG5 0x40010cc5u +#define CYREG_B0_P6_U1_CFG6 0x40010cc6u +#define CYREG_B0_P6_U1_CFG7 0x40010cc7u +#define CYREG_B0_P6_U1_CFG8 0x40010cc8u +#define CYREG_B0_P6_U1_CFG9 0x40010cc9u +#define CYREG_B0_P6_U1_CFG10 0x40010ccau +#define CYREG_B0_P6_U1_CFG11 0x40010ccbu +#define CYREG_B0_P6_U1_CFG12 0x40010cccu +#define CYREG_B0_P6_U1_CFG13 0x40010ccdu +#define CYREG_B0_P6_U1_CFG14 0x40010cceu +#define CYREG_B0_P6_U1_CFG15 0x40010ccfu +#define CYREG_B0_P6_U1_CFG16 0x40010cd0u +#define CYREG_B0_P6_U1_CFG17 0x40010cd1u +#define CYREG_B0_P6_U1_CFG18 0x40010cd2u +#define CYREG_B0_P6_U1_CFG19 0x40010cd3u +#define CYREG_B0_P6_U1_CFG20 0x40010cd4u +#define CYREG_B0_P6_U1_CFG21 0x40010cd5u +#define CYREG_B0_P6_U1_CFG22 0x40010cd6u +#define CYREG_B0_P6_U1_CFG23 0x40010cd7u +#define CYREG_B0_P6_U1_CFG24 0x40010cd8u +#define CYREG_B0_P6_U1_CFG25 0x40010cd9u +#define CYREG_B0_P6_U1_CFG26 0x40010cdau +#define CYREG_B0_P6_U1_CFG27 0x40010cdbu +#define CYREG_B0_P6_U1_CFG28 0x40010cdcu +#define CYREG_B0_P6_U1_CFG29 0x40010cddu +#define CYREG_B0_P6_U1_CFG30 0x40010cdeu +#define CYREG_B0_P6_U1_CFG31 0x40010cdfu +#define CYREG_B0_P6_U1_DCFG0 0x40010ce0u +#define CYREG_B0_P6_U1_DCFG1 0x40010ce2u +#define CYREG_B0_P6_U1_DCFG2 0x40010ce4u +#define CYREG_B0_P6_U1_DCFG3 0x40010ce6u +#define CYREG_B0_P6_U1_DCFG4 0x40010ce8u +#define CYREG_B0_P6_U1_DCFG5 0x40010ceau +#define CYREG_B0_P6_U1_DCFG6 0x40010cecu +#define CYREG_B0_P6_U1_DCFG7 0x40010ceeu +#define CYDEV_UCFG_B0_P6_ROUTE_BASE 0x40010d00u +#define CYDEV_UCFG_B0_P6_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P7_BASE 0x40010e00u +#define CYDEV_UCFG_B0_P7_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P7_U0_BASE 0x40010e00u +#define CYDEV_UCFG_B0_P7_U0_SIZE 0x00000070u +#define CYREG_B0_P7_U0_PLD_IT0 0x40010e00u +#define CYREG_B0_P7_U0_PLD_IT1 0x40010e04u +#define CYREG_B0_P7_U0_PLD_IT2 0x40010e08u +#define CYREG_B0_P7_U0_PLD_IT3 0x40010e0cu +#define CYREG_B0_P7_U0_PLD_IT4 0x40010e10u +#define CYREG_B0_P7_U0_PLD_IT5 0x40010e14u +#define CYREG_B0_P7_U0_PLD_IT6 0x40010e18u +#define CYREG_B0_P7_U0_PLD_IT7 0x40010e1cu +#define CYREG_B0_P7_U0_PLD_IT8 0x40010e20u +#define CYREG_B0_P7_U0_PLD_IT9 0x40010e24u +#define CYREG_B0_P7_U0_PLD_IT10 0x40010e28u +#define CYREG_B0_P7_U0_PLD_IT11 0x40010e2cu +#define CYREG_B0_P7_U0_PLD_ORT0 0x40010e30u +#define CYREG_B0_P7_U0_PLD_ORT1 0x40010e32u +#define CYREG_B0_P7_U0_PLD_ORT2 0x40010e34u +#define CYREG_B0_P7_U0_PLD_ORT3 0x40010e36u +#define CYREG_B0_P7_U0_MC_CFG_CEN_CONST 0x40010e38u +#define CYREG_B0_P7_U0_MC_CFG_XORFB 0x40010e3au +#define CYREG_B0_P7_U0_MC_CFG_SET_RESET 0x40010e3cu +#define CYREG_B0_P7_U0_MC_CFG_BYPASS 0x40010e3eu +#define CYREG_B0_P7_U0_CFG0 0x40010e40u +#define CYREG_B0_P7_U0_CFG1 0x40010e41u +#define CYREG_B0_P7_U0_CFG2 0x40010e42u +#define CYREG_B0_P7_U0_CFG3 0x40010e43u +#define CYREG_B0_P7_U0_CFG4 0x40010e44u +#define CYREG_B0_P7_U0_CFG5 0x40010e45u +#define CYREG_B0_P7_U0_CFG6 0x40010e46u +#define CYREG_B0_P7_U0_CFG7 0x40010e47u +#define CYREG_B0_P7_U0_CFG8 0x40010e48u +#define CYREG_B0_P7_U0_CFG9 0x40010e49u +#define CYREG_B0_P7_U0_CFG10 0x40010e4au +#define CYREG_B0_P7_U0_CFG11 0x40010e4bu +#define CYREG_B0_P7_U0_CFG12 0x40010e4cu +#define CYREG_B0_P7_U0_CFG13 0x40010e4du +#define CYREG_B0_P7_U0_CFG14 0x40010e4eu +#define CYREG_B0_P7_U0_CFG15 0x40010e4fu +#define CYREG_B0_P7_U0_CFG16 0x40010e50u +#define CYREG_B0_P7_U0_CFG17 0x40010e51u +#define CYREG_B0_P7_U0_CFG18 0x40010e52u +#define CYREG_B0_P7_U0_CFG19 0x40010e53u +#define CYREG_B0_P7_U0_CFG20 0x40010e54u +#define CYREG_B0_P7_U0_CFG21 0x40010e55u +#define CYREG_B0_P7_U0_CFG22 0x40010e56u +#define CYREG_B0_P7_U0_CFG23 0x40010e57u +#define CYREG_B0_P7_U0_CFG24 0x40010e58u +#define CYREG_B0_P7_U0_CFG25 0x40010e59u +#define CYREG_B0_P7_U0_CFG26 0x40010e5au +#define CYREG_B0_P7_U0_CFG27 0x40010e5bu +#define CYREG_B0_P7_U0_CFG28 0x40010e5cu +#define CYREG_B0_P7_U0_CFG29 0x40010e5du +#define CYREG_B0_P7_U0_CFG30 0x40010e5eu +#define CYREG_B0_P7_U0_CFG31 0x40010e5fu +#define CYREG_B0_P7_U0_DCFG0 0x40010e60u +#define CYREG_B0_P7_U0_DCFG1 0x40010e62u +#define CYREG_B0_P7_U0_DCFG2 0x40010e64u +#define CYREG_B0_P7_U0_DCFG3 0x40010e66u +#define CYREG_B0_P7_U0_DCFG4 0x40010e68u +#define CYREG_B0_P7_U0_DCFG5 0x40010e6au +#define CYREG_B0_P7_U0_DCFG6 0x40010e6cu +#define CYREG_B0_P7_U0_DCFG7 0x40010e6eu +#define CYDEV_UCFG_B0_P7_U1_BASE 0x40010e80u +#define CYDEV_UCFG_B0_P7_U1_SIZE 0x00000070u +#define CYREG_B0_P7_U1_PLD_IT0 0x40010e80u +#define CYREG_B0_P7_U1_PLD_IT1 0x40010e84u +#define CYREG_B0_P7_U1_PLD_IT2 0x40010e88u +#define CYREG_B0_P7_U1_PLD_IT3 0x40010e8cu +#define CYREG_B0_P7_U1_PLD_IT4 0x40010e90u +#define CYREG_B0_P7_U1_PLD_IT5 0x40010e94u +#define CYREG_B0_P7_U1_PLD_IT6 0x40010e98u +#define CYREG_B0_P7_U1_PLD_IT7 0x40010e9cu +#define CYREG_B0_P7_U1_PLD_IT8 0x40010ea0u +#define CYREG_B0_P7_U1_PLD_IT9 0x40010ea4u +#define CYREG_B0_P7_U1_PLD_IT10 0x40010ea8u +#define CYREG_B0_P7_U1_PLD_IT11 0x40010eacu +#define CYREG_B0_P7_U1_PLD_ORT0 0x40010eb0u +#define CYREG_B0_P7_U1_PLD_ORT1 0x40010eb2u +#define CYREG_B0_P7_U1_PLD_ORT2 0x40010eb4u +#define CYREG_B0_P7_U1_PLD_ORT3 0x40010eb6u +#define CYREG_B0_P7_U1_MC_CFG_CEN_CONST 0x40010eb8u +#define CYREG_B0_P7_U1_MC_CFG_XORFB 0x40010ebau +#define CYREG_B0_P7_U1_MC_CFG_SET_RESET 0x40010ebcu +#define CYREG_B0_P7_U1_MC_CFG_BYPASS 0x40010ebeu +#define CYREG_B0_P7_U1_CFG0 0x40010ec0u +#define CYREG_B0_P7_U1_CFG1 0x40010ec1u +#define CYREG_B0_P7_U1_CFG2 0x40010ec2u +#define CYREG_B0_P7_U1_CFG3 0x40010ec3u +#define CYREG_B0_P7_U1_CFG4 0x40010ec4u +#define CYREG_B0_P7_U1_CFG5 0x40010ec5u +#define CYREG_B0_P7_U1_CFG6 0x40010ec6u +#define CYREG_B0_P7_U1_CFG7 0x40010ec7u +#define CYREG_B0_P7_U1_CFG8 0x40010ec8u +#define CYREG_B0_P7_U1_CFG9 0x40010ec9u +#define CYREG_B0_P7_U1_CFG10 0x40010ecau +#define CYREG_B0_P7_U1_CFG11 0x40010ecbu +#define CYREG_B0_P7_U1_CFG12 0x40010eccu +#define CYREG_B0_P7_U1_CFG13 0x40010ecdu +#define CYREG_B0_P7_U1_CFG14 0x40010eceu +#define CYREG_B0_P7_U1_CFG15 0x40010ecfu +#define CYREG_B0_P7_U1_CFG16 0x40010ed0u +#define CYREG_B0_P7_U1_CFG17 0x40010ed1u +#define CYREG_B0_P7_U1_CFG18 0x40010ed2u +#define CYREG_B0_P7_U1_CFG19 0x40010ed3u +#define CYREG_B0_P7_U1_CFG20 0x40010ed4u +#define CYREG_B0_P7_U1_CFG21 0x40010ed5u +#define CYREG_B0_P7_U1_CFG22 0x40010ed6u +#define CYREG_B0_P7_U1_CFG23 0x40010ed7u +#define CYREG_B0_P7_U1_CFG24 0x40010ed8u +#define CYREG_B0_P7_U1_CFG25 0x40010ed9u +#define CYREG_B0_P7_U1_CFG26 0x40010edau +#define CYREG_B0_P7_U1_CFG27 0x40010edbu +#define CYREG_B0_P7_U1_CFG28 0x40010edcu +#define CYREG_B0_P7_U1_CFG29 0x40010eddu +#define CYREG_B0_P7_U1_CFG30 0x40010edeu +#define CYREG_B0_P7_U1_CFG31 0x40010edfu +#define CYREG_B0_P7_U1_DCFG0 0x40010ee0u +#define CYREG_B0_P7_U1_DCFG1 0x40010ee2u +#define CYREG_B0_P7_U1_DCFG2 0x40010ee4u +#define CYREG_B0_P7_U1_DCFG3 0x40010ee6u +#define CYREG_B0_P7_U1_DCFG4 0x40010ee8u +#define CYREG_B0_P7_U1_DCFG5 0x40010eeau +#define CYREG_B0_P7_U1_DCFG6 0x40010eecu +#define CYREG_B0_P7_U1_DCFG7 0x40010eeeu +#define CYDEV_UCFG_B0_P7_ROUTE_BASE 0x40010f00u +#define CYDEV_UCFG_B0_P7_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_BASE 0x40011000u +#define CYDEV_UCFG_B1_SIZE 0x00000fefu +#define CYDEV_UCFG_B1_P2_BASE 0x40011400u +#define CYDEV_UCFG_B1_P2_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P2_U0_BASE 0x40011400u +#define CYDEV_UCFG_B1_P2_U0_SIZE 0x00000070u +#define CYREG_B1_P2_U0_PLD_IT0 0x40011400u +#define CYREG_B1_P2_U0_PLD_IT1 0x40011404u +#define CYREG_B1_P2_U0_PLD_IT2 0x40011408u +#define CYREG_B1_P2_U0_PLD_IT3 0x4001140cu +#define CYREG_B1_P2_U0_PLD_IT4 0x40011410u +#define CYREG_B1_P2_U0_PLD_IT5 0x40011414u +#define CYREG_B1_P2_U0_PLD_IT6 0x40011418u +#define CYREG_B1_P2_U0_PLD_IT7 0x4001141cu +#define CYREG_B1_P2_U0_PLD_IT8 0x40011420u +#define CYREG_B1_P2_U0_PLD_IT9 0x40011424u +#define CYREG_B1_P2_U0_PLD_IT10 0x40011428u +#define CYREG_B1_P2_U0_PLD_IT11 0x4001142cu +#define CYREG_B1_P2_U0_PLD_ORT0 0x40011430u +#define CYREG_B1_P2_U0_PLD_ORT1 0x40011432u +#define CYREG_B1_P2_U0_PLD_ORT2 0x40011434u +#define CYREG_B1_P2_U0_PLD_ORT3 0x40011436u +#define CYREG_B1_P2_U0_MC_CFG_CEN_CONST 0x40011438u +#define CYREG_B1_P2_U0_MC_CFG_XORFB 0x4001143au +#define CYREG_B1_P2_U0_MC_CFG_SET_RESET 0x4001143cu +#define CYREG_B1_P2_U0_MC_CFG_BYPASS 0x4001143eu +#define CYREG_B1_P2_U0_CFG0 0x40011440u +#define CYREG_B1_P2_U0_CFG1 0x40011441u +#define CYREG_B1_P2_U0_CFG2 0x40011442u +#define CYREG_B1_P2_U0_CFG3 0x40011443u +#define CYREG_B1_P2_U0_CFG4 0x40011444u +#define CYREG_B1_P2_U0_CFG5 0x40011445u +#define CYREG_B1_P2_U0_CFG6 0x40011446u +#define CYREG_B1_P2_U0_CFG7 0x40011447u +#define CYREG_B1_P2_U0_CFG8 0x40011448u +#define CYREG_B1_P2_U0_CFG9 0x40011449u +#define CYREG_B1_P2_U0_CFG10 0x4001144au +#define CYREG_B1_P2_U0_CFG11 0x4001144bu +#define CYREG_B1_P2_U0_CFG12 0x4001144cu +#define CYREG_B1_P2_U0_CFG13 0x4001144du +#define CYREG_B1_P2_U0_CFG14 0x4001144eu +#define CYREG_B1_P2_U0_CFG15 0x4001144fu +#define CYREG_B1_P2_U0_CFG16 0x40011450u +#define CYREG_B1_P2_U0_CFG17 0x40011451u +#define CYREG_B1_P2_U0_CFG18 0x40011452u +#define CYREG_B1_P2_U0_CFG19 0x40011453u +#define CYREG_B1_P2_U0_CFG20 0x40011454u +#define CYREG_B1_P2_U0_CFG21 0x40011455u +#define CYREG_B1_P2_U0_CFG22 0x40011456u +#define CYREG_B1_P2_U0_CFG23 0x40011457u +#define CYREG_B1_P2_U0_CFG24 0x40011458u +#define CYREG_B1_P2_U0_CFG25 0x40011459u +#define CYREG_B1_P2_U0_CFG26 0x4001145au +#define CYREG_B1_P2_U0_CFG27 0x4001145bu +#define CYREG_B1_P2_U0_CFG28 0x4001145cu +#define CYREG_B1_P2_U0_CFG29 0x4001145du +#define CYREG_B1_P2_U0_CFG30 0x4001145eu +#define CYREG_B1_P2_U0_CFG31 0x4001145fu +#define CYREG_B1_P2_U0_DCFG0 0x40011460u +#define CYREG_B1_P2_U0_DCFG1 0x40011462u +#define CYREG_B1_P2_U0_DCFG2 0x40011464u +#define CYREG_B1_P2_U0_DCFG3 0x40011466u +#define CYREG_B1_P2_U0_DCFG4 0x40011468u +#define CYREG_B1_P2_U0_DCFG5 0x4001146au +#define CYREG_B1_P2_U0_DCFG6 0x4001146cu +#define CYREG_B1_P2_U0_DCFG7 0x4001146eu +#define CYDEV_UCFG_B1_P2_U1_BASE 0x40011480u +#define CYDEV_UCFG_B1_P2_U1_SIZE 0x00000070u +#define CYREG_B1_P2_U1_PLD_IT0 0x40011480u +#define CYREG_B1_P2_U1_PLD_IT1 0x40011484u +#define CYREG_B1_P2_U1_PLD_IT2 0x40011488u +#define CYREG_B1_P2_U1_PLD_IT3 0x4001148cu +#define CYREG_B1_P2_U1_PLD_IT4 0x40011490u +#define CYREG_B1_P2_U1_PLD_IT5 0x40011494u +#define CYREG_B1_P2_U1_PLD_IT6 0x40011498u +#define CYREG_B1_P2_U1_PLD_IT7 0x4001149cu +#define CYREG_B1_P2_U1_PLD_IT8 0x400114a0u +#define CYREG_B1_P2_U1_PLD_IT9 0x400114a4u +#define CYREG_B1_P2_U1_PLD_IT10 0x400114a8u +#define CYREG_B1_P2_U1_PLD_IT11 0x400114acu +#define CYREG_B1_P2_U1_PLD_ORT0 0x400114b0u +#define CYREG_B1_P2_U1_PLD_ORT1 0x400114b2u +#define CYREG_B1_P2_U1_PLD_ORT2 0x400114b4u +#define CYREG_B1_P2_U1_PLD_ORT3 0x400114b6u +#define CYREG_B1_P2_U1_MC_CFG_CEN_CONST 0x400114b8u +#define CYREG_B1_P2_U1_MC_CFG_XORFB 0x400114bau +#define CYREG_B1_P2_U1_MC_CFG_SET_RESET 0x400114bcu +#define CYREG_B1_P2_U1_MC_CFG_BYPASS 0x400114beu +#define CYREG_B1_P2_U1_CFG0 0x400114c0u +#define CYREG_B1_P2_U1_CFG1 0x400114c1u +#define CYREG_B1_P2_U1_CFG2 0x400114c2u +#define CYREG_B1_P2_U1_CFG3 0x400114c3u +#define CYREG_B1_P2_U1_CFG4 0x400114c4u +#define CYREG_B1_P2_U1_CFG5 0x400114c5u +#define CYREG_B1_P2_U1_CFG6 0x400114c6u +#define CYREG_B1_P2_U1_CFG7 0x400114c7u +#define CYREG_B1_P2_U1_CFG8 0x400114c8u +#define CYREG_B1_P2_U1_CFG9 0x400114c9u +#define CYREG_B1_P2_U1_CFG10 0x400114cau +#define CYREG_B1_P2_U1_CFG11 0x400114cbu +#define CYREG_B1_P2_U1_CFG12 0x400114ccu +#define CYREG_B1_P2_U1_CFG13 0x400114cdu +#define CYREG_B1_P2_U1_CFG14 0x400114ceu +#define CYREG_B1_P2_U1_CFG15 0x400114cfu +#define CYREG_B1_P2_U1_CFG16 0x400114d0u +#define CYREG_B1_P2_U1_CFG17 0x400114d1u +#define CYREG_B1_P2_U1_CFG18 0x400114d2u +#define CYREG_B1_P2_U1_CFG19 0x400114d3u +#define CYREG_B1_P2_U1_CFG20 0x400114d4u +#define CYREG_B1_P2_U1_CFG21 0x400114d5u +#define CYREG_B1_P2_U1_CFG22 0x400114d6u +#define CYREG_B1_P2_U1_CFG23 0x400114d7u +#define CYREG_B1_P2_U1_CFG24 0x400114d8u +#define CYREG_B1_P2_U1_CFG25 0x400114d9u +#define CYREG_B1_P2_U1_CFG26 0x400114dau +#define CYREG_B1_P2_U1_CFG27 0x400114dbu +#define CYREG_B1_P2_U1_CFG28 0x400114dcu +#define CYREG_B1_P2_U1_CFG29 0x400114ddu +#define CYREG_B1_P2_U1_CFG30 0x400114deu +#define CYREG_B1_P2_U1_CFG31 0x400114dfu +#define CYREG_B1_P2_U1_DCFG0 0x400114e0u +#define CYREG_B1_P2_U1_DCFG1 0x400114e2u +#define CYREG_B1_P2_U1_DCFG2 0x400114e4u +#define CYREG_B1_P2_U1_DCFG3 0x400114e6u +#define CYREG_B1_P2_U1_DCFG4 0x400114e8u +#define CYREG_B1_P2_U1_DCFG5 0x400114eau +#define CYREG_B1_P2_U1_DCFG6 0x400114ecu +#define CYREG_B1_P2_U1_DCFG7 0x400114eeu +#define CYDEV_UCFG_B1_P2_ROUTE_BASE 0x40011500u +#define CYDEV_UCFG_B1_P2_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P3_BASE 0x40011600u +#define CYDEV_UCFG_B1_P3_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P3_U0_BASE 0x40011600u +#define CYDEV_UCFG_B1_P3_U0_SIZE 0x00000070u +#define CYREG_B1_P3_U0_PLD_IT0 0x40011600u +#define CYREG_B1_P3_U0_PLD_IT1 0x40011604u +#define CYREG_B1_P3_U0_PLD_IT2 0x40011608u +#define CYREG_B1_P3_U0_PLD_IT3 0x4001160cu +#define CYREG_B1_P3_U0_PLD_IT4 0x40011610u +#define CYREG_B1_P3_U0_PLD_IT5 0x40011614u +#define CYREG_B1_P3_U0_PLD_IT6 0x40011618u +#define CYREG_B1_P3_U0_PLD_IT7 0x4001161cu +#define CYREG_B1_P3_U0_PLD_IT8 0x40011620u +#define CYREG_B1_P3_U0_PLD_IT9 0x40011624u +#define CYREG_B1_P3_U0_PLD_IT10 0x40011628u +#define CYREG_B1_P3_U0_PLD_IT11 0x4001162cu +#define CYREG_B1_P3_U0_PLD_ORT0 0x40011630u +#define CYREG_B1_P3_U0_PLD_ORT1 0x40011632u +#define CYREG_B1_P3_U0_PLD_ORT2 0x40011634u +#define CYREG_B1_P3_U0_PLD_ORT3 0x40011636u +#define CYREG_B1_P3_U0_MC_CFG_CEN_CONST 0x40011638u +#define CYREG_B1_P3_U0_MC_CFG_XORFB 0x4001163au +#define CYREG_B1_P3_U0_MC_CFG_SET_RESET 0x4001163cu +#define CYREG_B1_P3_U0_MC_CFG_BYPASS 0x4001163eu +#define CYREG_B1_P3_U0_CFG0 0x40011640u +#define CYREG_B1_P3_U0_CFG1 0x40011641u +#define CYREG_B1_P3_U0_CFG2 0x40011642u +#define CYREG_B1_P3_U0_CFG3 0x40011643u +#define CYREG_B1_P3_U0_CFG4 0x40011644u +#define CYREG_B1_P3_U0_CFG5 0x40011645u +#define CYREG_B1_P3_U0_CFG6 0x40011646u +#define CYREG_B1_P3_U0_CFG7 0x40011647u +#define CYREG_B1_P3_U0_CFG8 0x40011648u +#define CYREG_B1_P3_U0_CFG9 0x40011649u +#define CYREG_B1_P3_U0_CFG10 0x4001164au +#define CYREG_B1_P3_U0_CFG11 0x4001164bu +#define CYREG_B1_P3_U0_CFG12 0x4001164cu +#define CYREG_B1_P3_U0_CFG13 0x4001164du +#define CYREG_B1_P3_U0_CFG14 0x4001164eu +#define CYREG_B1_P3_U0_CFG15 0x4001164fu +#define CYREG_B1_P3_U0_CFG16 0x40011650u +#define CYREG_B1_P3_U0_CFG17 0x40011651u +#define CYREG_B1_P3_U0_CFG18 0x40011652u +#define CYREG_B1_P3_U0_CFG19 0x40011653u +#define CYREG_B1_P3_U0_CFG20 0x40011654u +#define CYREG_B1_P3_U0_CFG21 0x40011655u +#define CYREG_B1_P3_U0_CFG22 0x40011656u +#define CYREG_B1_P3_U0_CFG23 0x40011657u +#define CYREG_B1_P3_U0_CFG24 0x40011658u +#define CYREG_B1_P3_U0_CFG25 0x40011659u +#define CYREG_B1_P3_U0_CFG26 0x4001165au +#define CYREG_B1_P3_U0_CFG27 0x4001165bu +#define CYREG_B1_P3_U0_CFG28 0x4001165cu +#define CYREG_B1_P3_U0_CFG29 0x4001165du +#define CYREG_B1_P3_U0_CFG30 0x4001165eu +#define CYREG_B1_P3_U0_CFG31 0x4001165fu +#define CYREG_B1_P3_U0_DCFG0 0x40011660u +#define CYREG_B1_P3_U0_DCFG1 0x40011662u +#define CYREG_B1_P3_U0_DCFG2 0x40011664u +#define CYREG_B1_P3_U0_DCFG3 0x40011666u +#define CYREG_B1_P3_U0_DCFG4 0x40011668u +#define CYREG_B1_P3_U0_DCFG5 0x4001166au +#define CYREG_B1_P3_U0_DCFG6 0x4001166cu +#define CYREG_B1_P3_U0_DCFG7 0x4001166eu +#define CYDEV_UCFG_B1_P3_U1_BASE 0x40011680u +#define CYDEV_UCFG_B1_P3_U1_SIZE 0x00000070u +#define CYREG_B1_P3_U1_PLD_IT0 0x40011680u +#define CYREG_B1_P3_U1_PLD_IT1 0x40011684u +#define CYREG_B1_P3_U1_PLD_IT2 0x40011688u +#define CYREG_B1_P3_U1_PLD_IT3 0x4001168cu +#define CYREG_B1_P3_U1_PLD_IT4 0x40011690u +#define CYREG_B1_P3_U1_PLD_IT5 0x40011694u +#define CYREG_B1_P3_U1_PLD_IT6 0x40011698u +#define CYREG_B1_P3_U1_PLD_IT7 0x4001169cu +#define CYREG_B1_P3_U1_PLD_IT8 0x400116a0u +#define CYREG_B1_P3_U1_PLD_IT9 0x400116a4u +#define CYREG_B1_P3_U1_PLD_IT10 0x400116a8u +#define CYREG_B1_P3_U1_PLD_IT11 0x400116acu +#define CYREG_B1_P3_U1_PLD_ORT0 0x400116b0u +#define CYREG_B1_P3_U1_PLD_ORT1 0x400116b2u +#define CYREG_B1_P3_U1_PLD_ORT2 0x400116b4u +#define CYREG_B1_P3_U1_PLD_ORT3 0x400116b6u +#define CYREG_B1_P3_U1_MC_CFG_CEN_CONST 0x400116b8u +#define CYREG_B1_P3_U1_MC_CFG_XORFB 0x400116bau +#define CYREG_B1_P3_U1_MC_CFG_SET_RESET 0x400116bcu +#define CYREG_B1_P3_U1_MC_CFG_BYPASS 0x400116beu +#define CYREG_B1_P3_U1_CFG0 0x400116c0u +#define CYREG_B1_P3_U1_CFG1 0x400116c1u +#define CYREG_B1_P3_U1_CFG2 0x400116c2u +#define CYREG_B1_P3_U1_CFG3 0x400116c3u +#define CYREG_B1_P3_U1_CFG4 0x400116c4u +#define CYREG_B1_P3_U1_CFG5 0x400116c5u +#define CYREG_B1_P3_U1_CFG6 0x400116c6u +#define CYREG_B1_P3_U1_CFG7 0x400116c7u +#define CYREG_B1_P3_U1_CFG8 0x400116c8u +#define CYREG_B1_P3_U1_CFG9 0x400116c9u +#define CYREG_B1_P3_U1_CFG10 0x400116cau +#define CYREG_B1_P3_U1_CFG11 0x400116cbu +#define CYREG_B1_P3_U1_CFG12 0x400116ccu +#define CYREG_B1_P3_U1_CFG13 0x400116cdu +#define CYREG_B1_P3_U1_CFG14 0x400116ceu +#define CYREG_B1_P3_U1_CFG15 0x400116cfu +#define CYREG_B1_P3_U1_CFG16 0x400116d0u +#define CYREG_B1_P3_U1_CFG17 0x400116d1u +#define CYREG_B1_P3_U1_CFG18 0x400116d2u +#define CYREG_B1_P3_U1_CFG19 0x400116d3u +#define CYREG_B1_P3_U1_CFG20 0x400116d4u +#define CYREG_B1_P3_U1_CFG21 0x400116d5u +#define CYREG_B1_P3_U1_CFG22 0x400116d6u +#define CYREG_B1_P3_U1_CFG23 0x400116d7u +#define CYREG_B1_P3_U1_CFG24 0x400116d8u +#define CYREG_B1_P3_U1_CFG25 0x400116d9u +#define CYREG_B1_P3_U1_CFG26 0x400116dau +#define CYREG_B1_P3_U1_CFG27 0x400116dbu +#define CYREG_B1_P3_U1_CFG28 0x400116dcu +#define CYREG_B1_P3_U1_CFG29 0x400116ddu +#define CYREG_B1_P3_U1_CFG30 0x400116deu +#define CYREG_B1_P3_U1_CFG31 0x400116dfu +#define CYREG_B1_P3_U1_DCFG0 0x400116e0u +#define CYREG_B1_P3_U1_DCFG1 0x400116e2u +#define CYREG_B1_P3_U1_DCFG2 0x400116e4u +#define CYREG_B1_P3_U1_DCFG3 0x400116e6u +#define CYREG_B1_P3_U1_DCFG4 0x400116e8u +#define CYREG_B1_P3_U1_DCFG5 0x400116eau +#define CYREG_B1_P3_U1_DCFG6 0x400116ecu +#define CYREG_B1_P3_U1_DCFG7 0x400116eeu +#define CYDEV_UCFG_B1_P3_ROUTE_BASE 0x40011700u +#define CYDEV_UCFG_B1_P3_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P4_BASE 0x40011800u +#define CYDEV_UCFG_B1_P4_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P4_U0_BASE 0x40011800u +#define CYDEV_UCFG_B1_P4_U0_SIZE 0x00000070u +#define CYREG_B1_P4_U0_PLD_IT0 0x40011800u +#define CYREG_B1_P4_U0_PLD_IT1 0x40011804u +#define CYREG_B1_P4_U0_PLD_IT2 0x40011808u +#define CYREG_B1_P4_U0_PLD_IT3 0x4001180cu +#define CYREG_B1_P4_U0_PLD_IT4 0x40011810u +#define CYREG_B1_P4_U0_PLD_IT5 0x40011814u +#define CYREG_B1_P4_U0_PLD_IT6 0x40011818u +#define CYREG_B1_P4_U0_PLD_IT7 0x4001181cu +#define CYREG_B1_P4_U0_PLD_IT8 0x40011820u +#define CYREG_B1_P4_U0_PLD_IT9 0x40011824u +#define CYREG_B1_P4_U0_PLD_IT10 0x40011828u +#define CYREG_B1_P4_U0_PLD_IT11 0x4001182cu +#define CYREG_B1_P4_U0_PLD_ORT0 0x40011830u +#define CYREG_B1_P4_U0_PLD_ORT1 0x40011832u +#define CYREG_B1_P4_U0_PLD_ORT2 0x40011834u +#define CYREG_B1_P4_U0_PLD_ORT3 0x40011836u +#define CYREG_B1_P4_U0_MC_CFG_CEN_CONST 0x40011838u +#define CYREG_B1_P4_U0_MC_CFG_XORFB 0x4001183au +#define CYREG_B1_P4_U0_MC_CFG_SET_RESET 0x4001183cu +#define CYREG_B1_P4_U0_MC_CFG_BYPASS 0x4001183eu +#define CYREG_B1_P4_U0_CFG0 0x40011840u +#define CYREG_B1_P4_U0_CFG1 0x40011841u +#define CYREG_B1_P4_U0_CFG2 0x40011842u +#define CYREG_B1_P4_U0_CFG3 0x40011843u +#define CYREG_B1_P4_U0_CFG4 0x40011844u +#define CYREG_B1_P4_U0_CFG5 0x40011845u +#define CYREG_B1_P4_U0_CFG6 0x40011846u +#define CYREG_B1_P4_U0_CFG7 0x40011847u +#define CYREG_B1_P4_U0_CFG8 0x40011848u +#define CYREG_B1_P4_U0_CFG9 0x40011849u +#define CYREG_B1_P4_U0_CFG10 0x4001184au +#define CYREG_B1_P4_U0_CFG11 0x4001184bu +#define CYREG_B1_P4_U0_CFG12 0x4001184cu +#define CYREG_B1_P4_U0_CFG13 0x4001184du +#define CYREG_B1_P4_U0_CFG14 0x4001184eu +#define CYREG_B1_P4_U0_CFG15 0x4001184fu +#define CYREG_B1_P4_U0_CFG16 0x40011850u +#define CYREG_B1_P4_U0_CFG17 0x40011851u +#define CYREG_B1_P4_U0_CFG18 0x40011852u +#define CYREG_B1_P4_U0_CFG19 0x40011853u +#define CYREG_B1_P4_U0_CFG20 0x40011854u +#define CYREG_B1_P4_U0_CFG21 0x40011855u +#define CYREG_B1_P4_U0_CFG22 0x40011856u +#define CYREG_B1_P4_U0_CFG23 0x40011857u +#define CYREG_B1_P4_U0_CFG24 0x40011858u +#define CYREG_B1_P4_U0_CFG25 0x40011859u +#define CYREG_B1_P4_U0_CFG26 0x4001185au +#define CYREG_B1_P4_U0_CFG27 0x4001185bu +#define CYREG_B1_P4_U0_CFG28 0x4001185cu +#define CYREG_B1_P4_U0_CFG29 0x4001185du +#define CYREG_B1_P4_U0_CFG30 0x4001185eu +#define CYREG_B1_P4_U0_CFG31 0x4001185fu +#define CYREG_B1_P4_U0_DCFG0 0x40011860u +#define CYREG_B1_P4_U0_DCFG1 0x40011862u +#define CYREG_B1_P4_U0_DCFG2 0x40011864u +#define CYREG_B1_P4_U0_DCFG3 0x40011866u +#define CYREG_B1_P4_U0_DCFG4 0x40011868u +#define CYREG_B1_P4_U0_DCFG5 0x4001186au +#define CYREG_B1_P4_U0_DCFG6 0x4001186cu +#define CYREG_B1_P4_U0_DCFG7 0x4001186eu +#define CYDEV_UCFG_B1_P4_U1_BASE 0x40011880u +#define CYDEV_UCFG_B1_P4_U1_SIZE 0x00000070u +#define CYREG_B1_P4_U1_PLD_IT0 0x40011880u +#define CYREG_B1_P4_U1_PLD_IT1 0x40011884u +#define CYREG_B1_P4_U1_PLD_IT2 0x40011888u +#define CYREG_B1_P4_U1_PLD_IT3 0x4001188cu +#define CYREG_B1_P4_U1_PLD_IT4 0x40011890u +#define CYREG_B1_P4_U1_PLD_IT5 0x40011894u +#define CYREG_B1_P4_U1_PLD_IT6 0x40011898u +#define CYREG_B1_P4_U1_PLD_IT7 0x4001189cu +#define CYREG_B1_P4_U1_PLD_IT8 0x400118a0u +#define CYREG_B1_P4_U1_PLD_IT9 0x400118a4u +#define CYREG_B1_P4_U1_PLD_IT10 0x400118a8u +#define CYREG_B1_P4_U1_PLD_IT11 0x400118acu +#define CYREG_B1_P4_U1_PLD_ORT0 0x400118b0u +#define CYREG_B1_P4_U1_PLD_ORT1 0x400118b2u +#define CYREG_B1_P4_U1_PLD_ORT2 0x400118b4u +#define CYREG_B1_P4_U1_PLD_ORT3 0x400118b6u +#define CYREG_B1_P4_U1_MC_CFG_CEN_CONST 0x400118b8u +#define CYREG_B1_P4_U1_MC_CFG_XORFB 0x400118bau +#define CYREG_B1_P4_U1_MC_CFG_SET_RESET 0x400118bcu +#define CYREG_B1_P4_U1_MC_CFG_BYPASS 0x400118beu +#define CYREG_B1_P4_U1_CFG0 0x400118c0u +#define CYREG_B1_P4_U1_CFG1 0x400118c1u +#define CYREG_B1_P4_U1_CFG2 0x400118c2u +#define CYREG_B1_P4_U1_CFG3 0x400118c3u +#define CYREG_B1_P4_U1_CFG4 0x400118c4u +#define CYREG_B1_P4_U1_CFG5 0x400118c5u +#define CYREG_B1_P4_U1_CFG6 0x400118c6u +#define CYREG_B1_P4_U1_CFG7 0x400118c7u +#define CYREG_B1_P4_U1_CFG8 0x400118c8u +#define CYREG_B1_P4_U1_CFG9 0x400118c9u +#define CYREG_B1_P4_U1_CFG10 0x400118cau +#define CYREG_B1_P4_U1_CFG11 0x400118cbu +#define CYREG_B1_P4_U1_CFG12 0x400118ccu +#define CYREG_B1_P4_U1_CFG13 0x400118cdu +#define CYREG_B1_P4_U1_CFG14 0x400118ceu +#define CYREG_B1_P4_U1_CFG15 0x400118cfu +#define CYREG_B1_P4_U1_CFG16 0x400118d0u +#define CYREG_B1_P4_U1_CFG17 0x400118d1u +#define CYREG_B1_P4_U1_CFG18 0x400118d2u +#define CYREG_B1_P4_U1_CFG19 0x400118d3u +#define CYREG_B1_P4_U1_CFG20 0x400118d4u +#define CYREG_B1_P4_U1_CFG21 0x400118d5u +#define CYREG_B1_P4_U1_CFG22 0x400118d6u +#define CYREG_B1_P4_U1_CFG23 0x400118d7u +#define CYREG_B1_P4_U1_CFG24 0x400118d8u +#define CYREG_B1_P4_U1_CFG25 0x400118d9u +#define CYREG_B1_P4_U1_CFG26 0x400118dau +#define CYREG_B1_P4_U1_CFG27 0x400118dbu +#define CYREG_B1_P4_U1_CFG28 0x400118dcu +#define CYREG_B1_P4_U1_CFG29 0x400118ddu +#define CYREG_B1_P4_U1_CFG30 0x400118deu +#define CYREG_B1_P4_U1_CFG31 0x400118dfu +#define CYREG_B1_P4_U1_DCFG0 0x400118e0u +#define CYREG_B1_P4_U1_DCFG1 0x400118e2u +#define CYREG_B1_P4_U1_DCFG2 0x400118e4u +#define CYREG_B1_P4_U1_DCFG3 0x400118e6u +#define CYREG_B1_P4_U1_DCFG4 0x400118e8u +#define CYREG_B1_P4_U1_DCFG5 0x400118eau +#define CYREG_B1_P4_U1_DCFG6 0x400118ecu +#define CYREG_B1_P4_U1_DCFG7 0x400118eeu +#define CYDEV_UCFG_B1_P4_ROUTE_BASE 0x40011900u +#define CYDEV_UCFG_B1_P4_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P5_BASE 0x40011a00u +#define CYDEV_UCFG_B1_P5_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P5_U0_BASE 0x40011a00u +#define CYDEV_UCFG_B1_P5_U0_SIZE 0x00000070u +#define CYREG_B1_P5_U0_PLD_IT0 0x40011a00u +#define CYREG_B1_P5_U0_PLD_IT1 0x40011a04u +#define CYREG_B1_P5_U0_PLD_IT2 0x40011a08u +#define CYREG_B1_P5_U0_PLD_IT3 0x40011a0cu +#define CYREG_B1_P5_U0_PLD_IT4 0x40011a10u +#define CYREG_B1_P5_U0_PLD_IT5 0x40011a14u +#define CYREG_B1_P5_U0_PLD_IT6 0x40011a18u +#define CYREG_B1_P5_U0_PLD_IT7 0x40011a1cu +#define CYREG_B1_P5_U0_PLD_IT8 0x40011a20u +#define CYREG_B1_P5_U0_PLD_IT9 0x40011a24u +#define CYREG_B1_P5_U0_PLD_IT10 0x40011a28u +#define CYREG_B1_P5_U0_PLD_IT11 0x40011a2cu +#define CYREG_B1_P5_U0_PLD_ORT0 0x40011a30u +#define CYREG_B1_P5_U0_PLD_ORT1 0x40011a32u +#define CYREG_B1_P5_U0_PLD_ORT2 0x40011a34u +#define CYREG_B1_P5_U0_PLD_ORT3 0x40011a36u +#define CYREG_B1_P5_U0_MC_CFG_CEN_CONST 0x40011a38u +#define CYREG_B1_P5_U0_MC_CFG_XORFB 0x40011a3au +#define CYREG_B1_P5_U0_MC_CFG_SET_RESET 0x40011a3cu +#define CYREG_B1_P5_U0_MC_CFG_BYPASS 0x40011a3eu +#define CYREG_B1_P5_U0_CFG0 0x40011a40u +#define CYREG_B1_P5_U0_CFG1 0x40011a41u +#define CYREG_B1_P5_U0_CFG2 0x40011a42u +#define CYREG_B1_P5_U0_CFG3 0x40011a43u +#define CYREG_B1_P5_U0_CFG4 0x40011a44u +#define CYREG_B1_P5_U0_CFG5 0x40011a45u +#define CYREG_B1_P5_U0_CFG6 0x40011a46u +#define CYREG_B1_P5_U0_CFG7 0x40011a47u +#define CYREG_B1_P5_U0_CFG8 0x40011a48u +#define CYREG_B1_P5_U0_CFG9 0x40011a49u +#define CYREG_B1_P5_U0_CFG10 0x40011a4au +#define CYREG_B1_P5_U0_CFG11 0x40011a4bu +#define CYREG_B1_P5_U0_CFG12 0x40011a4cu +#define CYREG_B1_P5_U0_CFG13 0x40011a4du +#define CYREG_B1_P5_U0_CFG14 0x40011a4eu +#define CYREG_B1_P5_U0_CFG15 0x40011a4fu +#define CYREG_B1_P5_U0_CFG16 0x40011a50u +#define CYREG_B1_P5_U0_CFG17 0x40011a51u +#define CYREG_B1_P5_U0_CFG18 0x40011a52u +#define CYREG_B1_P5_U0_CFG19 0x40011a53u +#define CYREG_B1_P5_U0_CFG20 0x40011a54u +#define CYREG_B1_P5_U0_CFG21 0x40011a55u +#define CYREG_B1_P5_U0_CFG22 0x40011a56u +#define CYREG_B1_P5_U0_CFG23 0x40011a57u +#define CYREG_B1_P5_U0_CFG24 0x40011a58u +#define CYREG_B1_P5_U0_CFG25 0x40011a59u +#define CYREG_B1_P5_U0_CFG26 0x40011a5au +#define CYREG_B1_P5_U0_CFG27 0x40011a5bu +#define CYREG_B1_P5_U0_CFG28 0x40011a5cu +#define CYREG_B1_P5_U0_CFG29 0x40011a5du +#define CYREG_B1_P5_U0_CFG30 0x40011a5eu +#define CYREG_B1_P5_U0_CFG31 0x40011a5fu +#define CYREG_B1_P5_U0_DCFG0 0x40011a60u +#define CYREG_B1_P5_U0_DCFG1 0x40011a62u +#define CYREG_B1_P5_U0_DCFG2 0x40011a64u +#define CYREG_B1_P5_U0_DCFG3 0x40011a66u +#define CYREG_B1_P5_U0_DCFG4 0x40011a68u +#define CYREG_B1_P5_U0_DCFG5 0x40011a6au +#define CYREG_B1_P5_U0_DCFG6 0x40011a6cu +#define CYREG_B1_P5_U0_DCFG7 0x40011a6eu +#define CYDEV_UCFG_B1_P5_U1_BASE 0x40011a80u +#define CYDEV_UCFG_B1_P5_U1_SIZE 0x00000070u +#define CYREG_B1_P5_U1_PLD_IT0 0x40011a80u +#define CYREG_B1_P5_U1_PLD_IT1 0x40011a84u +#define CYREG_B1_P5_U1_PLD_IT2 0x40011a88u +#define CYREG_B1_P5_U1_PLD_IT3 0x40011a8cu +#define CYREG_B1_P5_U1_PLD_IT4 0x40011a90u +#define CYREG_B1_P5_U1_PLD_IT5 0x40011a94u +#define CYREG_B1_P5_U1_PLD_IT6 0x40011a98u +#define CYREG_B1_P5_U1_PLD_IT7 0x40011a9cu +#define CYREG_B1_P5_U1_PLD_IT8 0x40011aa0u +#define CYREG_B1_P5_U1_PLD_IT9 0x40011aa4u +#define CYREG_B1_P5_U1_PLD_IT10 0x40011aa8u +#define CYREG_B1_P5_U1_PLD_IT11 0x40011aacu +#define CYREG_B1_P5_U1_PLD_ORT0 0x40011ab0u +#define CYREG_B1_P5_U1_PLD_ORT1 0x40011ab2u +#define CYREG_B1_P5_U1_PLD_ORT2 0x40011ab4u +#define CYREG_B1_P5_U1_PLD_ORT3 0x40011ab6u +#define CYREG_B1_P5_U1_MC_CFG_CEN_CONST 0x40011ab8u +#define CYREG_B1_P5_U1_MC_CFG_XORFB 0x40011abau +#define CYREG_B1_P5_U1_MC_CFG_SET_RESET 0x40011abcu +#define CYREG_B1_P5_U1_MC_CFG_BYPASS 0x40011abeu +#define CYREG_B1_P5_U1_CFG0 0x40011ac0u +#define CYREG_B1_P5_U1_CFG1 0x40011ac1u +#define CYREG_B1_P5_U1_CFG2 0x40011ac2u +#define CYREG_B1_P5_U1_CFG3 0x40011ac3u +#define CYREG_B1_P5_U1_CFG4 0x40011ac4u +#define CYREG_B1_P5_U1_CFG5 0x40011ac5u +#define CYREG_B1_P5_U1_CFG6 0x40011ac6u +#define CYREG_B1_P5_U1_CFG7 0x40011ac7u +#define CYREG_B1_P5_U1_CFG8 0x40011ac8u +#define CYREG_B1_P5_U1_CFG9 0x40011ac9u +#define CYREG_B1_P5_U1_CFG10 0x40011acau +#define CYREG_B1_P5_U1_CFG11 0x40011acbu +#define CYREG_B1_P5_U1_CFG12 0x40011accu +#define CYREG_B1_P5_U1_CFG13 0x40011acdu +#define CYREG_B1_P5_U1_CFG14 0x40011aceu +#define CYREG_B1_P5_U1_CFG15 0x40011acfu +#define CYREG_B1_P5_U1_CFG16 0x40011ad0u +#define CYREG_B1_P5_U1_CFG17 0x40011ad1u +#define CYREG_B1_P5_U1_CFG18 0x40011ad2u +#define CYREG_B1_P5_U1_CFG19 0x40011ad3u +#define CYREG_B1_P5_U1_CFG20 0x40011ad4u +#define CYREG_B1_P5_U1_CFG21 0x40011ad5u +#define CYREG_B1_P5_U1_CFG22 0x40011ad6u +#define CYREG_B1_P5_U1_CFG23 0x40011ad7u +#define CYREG_B1_P5_U1_CFG24 0x40011ad8u +#define CYREG_B1_P5_U1_CFG25 0x40011ad9u +#define CYREG_B1_P5_U1_CFG26 0x40011adau +#define CYREG_B1_P5_U1_CFG27 0x40011adbu +#define CYREG_B1_P5_U1_CFG28 0x40011adcu +#define CYREG_B1_P5_U1_CFG29 0x40011addu +#define CYREG_B1_P5_U1_CFG30 0x40011adeu +#define CYREG_B1_P5_U1_CFG31 0x40011adfu +#define CYREG_B1_P5_U1_DCFG0 0x40011ae0u +#define CYREG_B1_P5_U1_DCFG1 0x40011ae2u +#define CYREG_B1_P5_U1_DCFG2 0x40011ae4u +#define CYREG_B1_P5_U1_DCFG3 0x40011ae6u +#define CYREG_B1_P5_U1_DCFG4 0x40011ae8u +#define CYREG_B1_P5_U1_DCFG5 0x40011aeau +#define CYREG_B1_P5_U1_DCFG6 0x40011aecu +#define CYREG_B1_P5_U1_DCFG7 0x40011aeeu +#define CYDEV_UCFG_B1_P5_ROUTE_BASE 0x40011b00u +#define CYDEV_UCFG_B1_P5_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_DSI0_BASE 0x40014000u +#define CYDEV_UCFG_DSI0_SIZE 0x000000efu +#define CYDEV_UCFG_DSI1_BASE 0x40014100u +#define CYDEV_UCFG_DSI1_SIZE 0x000000efu +#define CYDEV_UCFG_DSI2_BASE 0x40014200u +#define CYDEV_UCFG_DSI2_SIZE 0x000000efu +#define CYDEV_UCFG_DSI3_BASE 0x40014300u +#define CYDEV_UCFG_DSI3_SIZE 0x000000efu +#define CYDEV_UCFG_DSI4_BASE 0x40014400u +#define CYDEV_UCFG_DSI4_SIZE 0x000000efu +#define CYDEV_UCFG_DSI5_BASE 0x40014500u +#define CYDEV_UCFG_DSI5_SIZE 0x000000efu +#define CYDEV_UCFG_DSI6_BASE 0x40014600u +#define CYDEV_UCFG_DSI6_SIZE 0x000000efu +#define CYDEV_UCFG_DSI7_BASE 0x40014700u +#define CYDEV_UCFG_DSI7_SIZE 0x000000efu +#define CYDEV_UCFG_DSI8_BASE 0x40014800u +#define CYDEV_UCFG_DSI8_SIZE 0x000000efu +#define CYDEV_UCFG_DSI9_BASE 0x40014900u +#define CYDEV_UCFG_DSI9_SIZE 0x000000efu +#define CYDEV_UCFG_DSI12_BASE 0x40014c00u +#define CYDEV_UCFG_DSI12_SIZE 0x000000efu +#define CYDEV_UCFG_DSI13_BASE 0x40014d00u +#define CYDEV_UCFG_DSI13_SIZE 0x000000efu +#define CYDEV_UCFG_BCTL0_BASE 0x40015000u +#define CYDEV_UCFG_BCTL0_SIZE 0x00000010u +#define CYREG_BCTL0_MDCLK_EN 0x40015000u +#define CYREG_BCTL0_MBCLK_EN 0x40015001u +#define CYREG_BCTL0_WAIT_CFG 0x40015002u +#define CYREG_BCTL0_BANK_CTL 0x40015003u +#define CYREG_BCTL0_UDB_TEST_3 0x40015007u +#define CYREG_BCTL0_DCLK_EN0 0x40015008u +#define CYREG_BCTL0_BCLK_EN0 0x40015009u +#define CYREG_BCTL0_DCLK_EN1 0x4001500au +#define CYREG_BCTL0_BCLK_EN1 0x4001500bu +#define CYREG_BCTL0_DCLK_EN2 0x4001500cu +#define CYREG_BCTL0_BCLK_EN2 0x4001500du +#define CYREG_BCTL0_DCLK_EN3 0x4001500eu +#define CYREG_BCTL0_BCLK_EN3 0x4001500fu +#define CYDEV_UCFG_BCTL1_BASE 0x40015010u +#define CYDEV_UCFG_BCTL1_SIZE 0x00000010u +#define CYREG_BCTL1_MDCLK_EN 0x40015010u +#define CYREG_BCTL1_MBCLK_EN 0x40015011u +#define CYREG_BCTL1_WAIT_CFG 0x40015012u +#define CYREG_BCTL1_BANK_CTL 0x40015013u +#define CYREG_BCTL1_UDB_TEST_3 0x40015017u +#define CYREG_BCTL1_DCLK_EN0 0x40015018u +#define CYREG_BCTL1_BCLK_EN0 0x40015019u +#define CYREG_BCTL1_DCLK_EN1 0x4001501au +#define CYREG_BCTL1_BCLK_EN1 0x4001501bu +#define CYREG_BCTL1_DCLK_EN2 0x4001501cu +#define CYREG_BCTL1_BCLK_EN2 0x4001501du +#define CYREG_BCTL1_DCLK_EN3 0x4001501eu +#define CYREG_BCTL1_BCLK_EN3 0x4001501fu +#define CYDEV_IDMUX_BASE 0x40015100u +#define CYDEV_IDMUX_SIZE 0x00000016u +#define CYREG_IDMUX_IRQ_CTL0 0x40015100u +#define CYREG_IDMUX_IRQ_CTL1 0x40015101u +#define CYREG_IDMUX_IRQ_CTL2 0x40015102u +#define CYREG_IDMUX_IRQ_CTL3 0x40015103u +#define CYREG_IDMUX_IRQ_CTL4 0x40015104u +#define CYREG_IDMUX_IRQ_CTL5 0x40015105u +#define CYREG_IDMUX_IRQ_CTL6 0x40015106u +#define CYREG_IDMUX_IRQ_CTL7 0x40015107u +#define CYREG_IDMUX_DRQ_CTL0 0x40015110u +#define CYREG_IDMUX_DRQ_CTL1 0x40015111u +#define CYREG_IDMUX_DRQ_CTL2 0x40015112u +#define CYREG_IDMUX_DRQ_CTL3 0x40015113u +#define CYREG_IDMUX_DRQ_CTL4 0x40015114u +#define CYREG_IDMUX_DRQ_CTL5 0x40015115u +#define CYDEV_CACHERAM_BASE 0x40030000u +#define CYDEV_CACHERAM_SIZE 0x00000400u +#define CYREG_CACHERAM_DATA_MBASE 0x40030000u +#define CYREG_CACHERAM_DATA_MSIZE 0x00000400u +#define CYDEV_SFR_BASE 0x40050100u +#define CYDEV_SFR_SIZE 0x000000fbu +#define CYREG_SFR_GPIO0 0x40050180u +#define CYREG_SFR_GPIRD0 0x40050189u +#define CYREG_SFR_GPIO0_SEL 0x4005018au +#define CYREG_SFR_GPIO1 0x40050190u +#define CYREG_SFR_GPIRD1 0x40050191u +#define CYREG_SFR_GPIO2 0x40050198u +#define CYREG_SFR_GPIRD2 0x40050199u +#define CYREG_SFR_GPIO2_SEL 0x4005019au +#define CYREG_SFR_GPIO1_SEL 0x400501a2u +#define CYREG_SFR_GPIO3 0x400501b0u +#define CYREG_SFR_GPIRD3 0x400501b1u +#define CYREG_SFR_GPIO3_SEL 0x400501b2u +#define CYREG_SFR_GPIO4 0x400501c0u +#define CYREG_SFR_GPIRD4 0x400501c1u +#define CYREG_SFR_GPIO4_SEL 0x400501c2u +#define CYREG_SFR_GPIO5 0x400501c8u +#define CYREG_SFR_GPIRD5 0x400501c9u +#define CYREG_SFR_GPIO5_SEL 0x400501cau +#define CYREG_SFR_GPIO6 0x400501d8u +#define CYREG_SFR_GPIRD6 0x400501d9u +#define CYREG_SFR_GPIO6_SEL 0x400501dau +#define CYREG_SFR_GPIO12 0x400501e8u +#define CYREG_SFR_GPIRD12 0x400501e9u +#define CYREG_SFR_GPIO12_SEL 0x400501f2u +#define CYREG_SFR_GPIO15 0x400501f8u +#define CYREG_SFR_GPIRD15 0x400501f9u +#define CYREG_SFR_GPIO15_SEL 0x400501fau +#define CYDEV_P3BA_BASE 0x40050300u +#define CYDEV_P3BA_SIZE 0x0000002bu +#define CYREG_P3BA_Y_START 0x40050300u +#define CYREG_P3BA_YROLL 0x40050301u +#define CYREG_P3BA_YCFG 0x40050302u +#define CYREG_P3BA_X_START1 0x40050303u +#define CYREG_P3BA_X_START2 0x40050304u +#define CYREG_P3BA_XROLL1 0x40050305u +#define CYREG_P3BA_XROLL2 0x40050306u +#define CYREG_P3BA_XINC 0x40050307u +#define CYREG_P3BA_XCFG 0x40050308u +#define CYREG_P3BA_OFFSETADDR1 0x40050309u +#define CYREG_P3BA_OFFSETADDR2 0x4005030au +#define CYREG_P3BA_OFFSETADDR3 0x4005030bu +#define CYREG_P3BA_ABSADDR1 0x4005030cu +#define CYREG_P3BA_ABSADDR2 0x4005030du +#define CYREG_P3BA_ABSADDR3 0x4005030eu +#define CYREG_P3BA_ABSADDR4 0x4005030fu +#define CYREG_P3BA_DATCFG1 0x40050310u +#define CYREG_P3BA_DATCFG2 0x40050311u +#define CYREG_P3BA_CMP_RSLT1 0x40050314u +#define CYREG_P3BA_CMP_RSLT2 0x40050315u +#define CYREG_P3BA_CMP_RSLT3 0x40050316u +#define CYREG_P3BA_CMP_RSLT4 0x40050317u +#define CYREG_P3BA_DATA_REG1 0x40050318u +#define CYREG_P3BA_DATA_REG2 0x40050319u +#define CYREG_P3BA_DATA_REG3 0x4005031au +#define CYREG_P3BA_DATA_REG4 0x4005031bu +#define CYREG_P3BA_EXP_DATA1 0x4005031cu +#define CYREG_P3BA_EXP_DATA2 0x4005031du +#define CYREG_P3BA_EXP_DATA3 0x4005031eu +#define CYREG_P3BA_EXP_DATA4 0x4005031fu +#define CYREG_P3BA_MSTR_HRDATA1 0x40050320u +#define CYREG_P3BA_MSTR_HRDATA2 0x40050321u +#define CYREG_P3BA_MSTR_HRDATA3 0x40050322u +#define CYREG_P3BA_MSTR_HRDATA4 0x40050323u +#define CYREG_P3BA_BIST_EN 0x40050324u +#define CYREG_P3BA_PHUB_MASTER_SSR 0x40050325u +#define CYREG_P3BA_SEQCFG1 0x40050326u +#define CYREG_P3BA_SEQCFG2 0x40050327u +#define CYREG_P3BA_Y_CURR 0x40050328u +#define CYREG_P3BA_X_CURR1 0x40050329u +#define CYREG_P3BA_X_CURR2 0x4005032au +#define CYDEV_PANTHER_BASE 0x40080000u +#define CYDEV_PANTHER_SIZE 0x00000020u +#define CYREG_PANTHER_STCALIB_CFG 0x40080000u +#define CYREG_PANTHER_WAITPIPE 0x40080004u +#define CYREG_PANTHER_TRACE_CFG 0x40080008u +#define CYREG_PANTHER_DBG_CFG 0x4008000cu +#define CYREG_PANTHER_CM3_LCKRST_STAT 0x40080018u +#define CYREG_PANTHER_DEVICE_ID 0x4008001cu +#define CYDEV_FLSECC_BASE 0x48000000u +#define CYDEV_FLSECC_SIZE 0x00008000u +#define CYREG_FLSECC_DATA_MBASE 0x48000000u +#define CYREG_FLSECC_DATA_MSIZE 0x00008000u +#define CYDEV_FLSHID_BASE 0x49000000u +#define CYDEV_FLSHID_SIZE 0x00000200u +#define CYREG_FLSHID_RSVD_MBASE 0x49000000u +#define CYREG_FLSHID_RSVD_MSIZE 0x00000080u +#define CYREG_FLSHID_CUST_MDATA_MBASE 0x49000080u +#define CYREG_FLSHID_CUST_MDATA_MSIZE 0x00000080u +#define CYDEV_FLSHID_CUST_TABLES_BASE 0x49000100u +#define CYDEV_FLSHID_CUST_TABLES_SIZE 0x00000040u +#define CYREG_FLSHID_CUST_TABLES_Y_LOC 0x49000100u +#define CYREG_FLSHID_CUST_TABLES_X_LOC 0x49000101u +#define CYREG_FLSHID_CUST_TABLES_WAFER_NUM 0x49000102u +#define CYREG_FLSHID_CUST_TABLES_LOT_LSB 0x49000103u +#define CYREG_FLSHID_CUST_TABLES_LOT_MSB 0x49000104u +#define CYREG_FLSHID_CUST_TABLES_WRK_WK 0x49000105u +#define CYREG_FLSHID_CUST_TABLES_FAB_YR 0x49000106u +#define CYREG_FLSHID_CUST_TABLES_MINOR 0x49000107u +#define CYREG_FLSHID_CUST_TABLES_IMO_3MHZ 0x49000108u +#define CYREG_FLSHID_CUST_TABLES_IMO_6MHZ 0x49000109u +#define CYREG_FLSHID_CUST_TABLES_IMO_12MHZ 0x4900010au +#define CYREG_FLSHID_CUST_TABLES_IMO_24MHZ 0x4900010bu +#define CYREG_FLSHID_CUST_TABLES_IMO_67MHZ 0x4900010cu +#define CYREG_FLSHID_CUST_TABLES_IMO_80MHZ 0x4900010du +#define CYREG_FLSHID_CUST_TABLES_IMO_92MHZ 0x4900010eu +#define CYREG_FLSHID_CUST_TABLES_IMO_USB 0x4900010fu +#define CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS 0x49000110u +#define CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS 0x49000111u +#define CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS 0x49000112u +#define CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS 0x49000113u +#define CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS 0x49000114u +#define CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS 0x49000115u +#define CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS 0x49000116u +#define CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS 0x49000117u +#define CYREG_FLSHID_CUST_TABLES_DEC_M1 0x49000118u +#define CYREG_FLSHID_CUST_TABLES_DEC_M2 0x49000119u +#define CYREG_FLSHID_CUST_TABLES_DEC_M3 0x4900011au +#define CYREG_FLSHID_CUST_TABLES_DEC_M4 0x4900011bu +#define CYREG_FLSHID_CUST_TABLES_DEC_M5 0x4900011cu +#define CYREG_FLSHID_CUST_TABLES_DEC_M6 0x4900011du +#define CYREG_FLSHID_CUST_TABLES_DEC_M7 0x4900011eu +#define CYREG_FLSHID_CUST_TABLES_DEC_M8 0x4900011fu +#define CYREG_FLSHID_CUST_TABLES_DAC0_M1 0x49000120u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M2 0x49000121u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M3 0x49000122u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M4 0x49000123u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M5 0x49000124u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M6 0x49000125u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M7 0x49000126u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M8 0x49000127u +#define CYREG_FLSHID_CUST_TABLES_DAC2_M1 0x49000128u +#define CYREG_FLSHID_CUST_TABLES_DAC2_M2 0x49000129u +#define CYREG_FLSHID_CUST_TABLES_DAC2_M3 0x4900012au +#define CYREG_FLSHID_CUST_TABLES_DAC2_M4 0x4900012bu +#define CYREG_FLSHID_CUST_TABLES_DAC2_M5 0x4900012cu +#define CYREG_FLSHID_CUST_TABLES_DAC2_M6 0x4900012du +#define CYREG_FLSHID_CUST_TABLES_DAC2_M7 0x4900012eu +#define CYREG_FLSHID_CUST_TABLES_DAC2_M8 0x4900012fu +#define CYREG_FLSHID_CUST_TABLES_DAC1_M1 0x49000130u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M2 0x49000131u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M3 0x49000132u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M4 0x49000133u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M5 0x49000134u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M6 0x49000135u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M7 0x49000136u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M8 0x49000137u +#define CYREG_FLSHID_CUST_TABLES_DAC3_M1 0x49000138u +#define CYREG_FLSHID_CUST_TABLES_DAC3_M2 0x49000139u +#define CYREG_FLSHID_CUST_TABLES_DAC3_M3 0x4900013au +#define CYREG_FLSHID_CUST_TABLES_DAC3_M4 0x4900013bu +#define CYREG_FLSHID_CUST_TABLES_DAC3_M5 0x4900013cu +#define CYREG_FLSHID_CUST_TABLES_DAC3_M6 0x4900013du +#define CYREG_FLSHID_CUST_TABLES_DAC3_M7 0x4900013eu +#define CYREG_FLSHID_CUST_TABLES_DAC3_M8 0x4900013fu +#define CYDEV_FLSHID_MFG_CFG_BASE 0x49000180u +#define CYDEV_FLSHID_MFG_CFG_SIZE 0x00000080u +#define CYREG_FLSHID_MFG_CFG_IMO_TR1 0x49000188u +#define CYREG_FLSHID_MFG_CFG_CMP0_TR0 0x490001acu +#define CYREG_FLSHID_MFG_CFG_CMP1_TR0 0x490001aeu +#define CYREG_FLSHID_MFG_CFG_CMP2_TR0 0x490001b0u +#define CYREG_FLSHID_MFG_CFG_CMP3_TR0 0x490001b2u +#define CYREG_FLSHID_MFG_CFG_CMP0_TR1 0x490001b4u +#define CYREG_FLSHID_MFG_CFG_CMP1_TR1 0x490001b6u +#define CYREG_FLSHID_MFG_CFG_CMP2_TR1 0x490001b8u +#define CYREG_FLSHID_MFG_CFG_CMP3_TR1 0x490001bau +#define CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM 0x490001ceu +#define CYDEV_EXTMEM_BASE 0x60000000u +#define CYDEV_EXTMEM_SIZE 0x00800000u +#define CYREG_EXTMEM_DATA_MBASE 0x60000000u +#define CYREG_EXTMEM_DATA_MSIZE 0x00800000u +#define CYDEV_ITM_BASE 0xe0000000u +#define CYDEV_ITM_SIZE 0x00001000u +#define CYREG_ITM_TRACE_EN 0xe0000e00u +#define CYREG_ITM_TRACE_PRIVILEGE 0xe0000e40u +#define CYREG_ITM_TRACE_CTRL 0xe0000e80u +#define CYREG_ITM_LOCK_ACCESS 0xe0000fb0u +#define CYREG_ITM_LOCK_STATUS 0xe0000fb4u +#define CYREG_ITM_PID4 0xe0000fd0u +#define CYREG_ITM_PID5 0xe0000fd4u +#define CYREG_ITM_PID6 0xe0000fd8u +#define CYREG_ITM_PID7 0xe0000fdcu +#define CYREG_ITM_PID0 0xe0000fe0u +#define CYREG_ITM_PID1 0xe0000fe4u +#define CYREG_ITM_PID2 0xe0000fe8u +#define CYREG_ITM_PID3 0xe0000fecu +#define CYREG_ITM_CID0 0xe0000ff0u +#define CYREG_ITM_CID1 0xe0000ff4u +#define CYREG_ITM_CID2 0xe0000ff8u +#define CYREG_ITM_CID3 0xe0000ffcu +#define CYDEV_DWT_BASE 0xe0001000u +#define CYDEV_DWT_SIZE 0x0000005cu +#define CYREG_DWT_CTRL 0xe0001000u +#define CYREG_DWT_CYCLE_COUNT 0xe0001004u +#define CYREG_DWT_CPI_COUNT 0xe0001008u +#define CYREG_DWT_EXC_OVHD_COUNT 0xe000100cu +#define CYREG_DWT_SLEEP_COUNT 0xe0001010u +#define CYREG_DWT_LSU_COUNT 0xe0001014u +#define CYREG_DWT_FOLD_COUNT 0xe0001018u +#define CYREG_DWT_PC_SAMPLE 0xe000101cu +#define CYREG_DWT_COMP_0 0xe0001020u +#define CYREG_DWT_MASK_0 0xe0001024u +#define CYREG_DWT_FUNCTION_0 0xe0001028u +#define CYREG_DWT_COMP_1 0xe0001030u +#define CYREG_DWT_MASK_1 0xe0001034u +#define CYREG_DWT_FUNCTION_1 0xe0001038u +#define CYREG_DWT_COMP_2 0xe0001040u +#define CYREG_DWT_MASK_2 0xe0001044u +#define CYREG_DWT_FUNCTION_2 0xe0001048u +#define CYREG_DWT_COMP_3 0xe0001050u +#define CYREG_DWT_MASK_3 0xe0001054u +#define CYREG_DWT_FUNCTION_3 0xe0001058u +#define CYDEV_FPB_BASE 0xe0002000u +#define CYDEV_FPB_SIZE 0x00001000u +#define CYREG_FPB_CTRL 0xe0002000u +#define CYREG_FPB_REMAP 0xe0002004u +#define CYREG_FPB_FP_COMP_0 0xe0002008u +#define CYREG_FPB_FP_COMP_1 0xe000200cu +#define CYREG_FPB_FP_COMP_2 0xe0002010u +#define CYREG_FPB_FP_COMP_3 0xe0002014u +#define CYREG_FPB_FP_COMP_4 0xe0002018u +#define CYREG_FPB_FP_COMP_5 0xe000201cu +#define CYREG_FPB_FP_COMP_6 0xe0002020u +#define CYREG_FPB_FP_COMP_7 0xe0002024u +#define CYREG_FPB_PID4 0xe0002fd0u +#define CYREG_FPB_PID5 0xe0002fd4u +#define CYREG_FPB_PID6 0xe0002fd8u +#define CYREG_FPB_PID7 0xe0002fdcu +#define CYREG_FPB_PID0 0xe0002fe0u +#define CYREG_FPB_PID1 0xe0002fe4u +#define CYREG_FPB_PID2 0xe0002fe8u +#define CYREG_FPB_PID3 0xe0002fecu +#define CYREG_FPB_CID0 0xe0002ff0u +#define CYREG_FPB_CID1 0xe0002ff4u +#define CYREG_FPB_CID2 0xe0002ff8u +#define CYREG_FPB_CID3 0xe0002ffcu +#define CYDEV_NVIC_BASE 0xe000e000u +#define CYDEV_NVIC_SIZE 0x00000d3cu +#define CYREG_NVIC_INT_CTL_TYPE 0xe000e004u +#define CYREG_NVIC_SYSTICK_CTL 0xe000e010u +#define CYREG_NVIC_SYSTICK_RELOAD 0xe000e014u +#define CYREG_NVIC_SYSTICK_CURRENT 0xe000e018u +#define CYREG_NVIC_SYSTICK_CAL 0xe000e01cu +#define CYREG_NVIC_SETENA0 0xe000e100u +#define CYREG_NVIC_CLRENA0 0xe000e180u +#define CYREG_NVIC_SETPEND0 0xe000e200u +#define CYREG_NVIC_CLRPEND0 0xe000e280u +#define CYREG_NVIC_ACTIVE0 0xe000e300u +#define CYREG_NVIC_PRI_0 0xe000e400u +#define CYREG_NVIC_PRI_1 0xe000e401u +#define CYREG_NVIC_PRI_2 0xe000e402u +#define CYREG_NVIC_PRI_3 0xe000e403u +#define CYREG_NVIC_PRI_4 0xe000e404u +#define CYREG_NVIC_PRI_5 0xe000e405u +#define CYREG_NVIC_PRI_6 0xe000e406u +#define CYREG_NVIC_PRI_7 0xe000e407u +#define CYREG_NVIC_PRI_8 0xe000e408u +#define CYREG_NVIC_PRI_9 0xe000e409u +#define CYREG_NVIC_PRI_10 0xe000e40au +#define CYREG_NVIC_PRI_11 0xe000e40bu +#define CYREG_NVIC_PRI_12 0xe000e40cu +#define CYREG_NVIC_PRI_13 0xe000e40du +#define CYREG_NVIC_PRI_14 0xe000e40eu +#define CYREG_NVIC_PRI_15 0xe000e40fu +#define CYREG_NVIC_PRI_16 0xe000e410u +#define CYREG_NVIC_PRI_17 0xe000e411u +#define CYREG_NVIC_PRI_18 0xe000e412u +#define CYREG_NVIC_PRI_19 0xe000e413u +#define CYREG_NVIC_PRI_20 0xe000e414u +#define CYREG_NVIC_PRI_21 0xe000e415u +#define CYREG_NVIC_PRI_22 0xe000e416u +#define CYREG_NVIC_PRI_23 0xe000e417u +#define CYREG_NVIC_PRI_24 0xe000e418u +#define CYREG_NVIC_PRI_25 0xe000e419u +#define CYREG_NVIC_PRI_26 0xe000e41au +#define CYREG_NVIC_PRI_27 0xe000e41bu +#define CYREG_NVIC_PRI_28 0xe000e41cu +#define CYREG_NVIC_PRI_29 0xe000e41du +#define CYREG_NVIC_PRI_30 0xe000e41eu +#define CYREG_NVIC_PRI_31 0xe000e41fu +#define CYREG_NVIC_CPUID_BASE 0xe000ed00u +#define CYREG_NVIC_INTR_CTRL_STATE 0xe000ed04u +#define CYREG_NVIC_VECT_OFFSET 0xe000ed08u +#define CYREG_NVIC_APPLN_INTR 0xe000ed0cu +#define CYREG_NVIC_SYSTEM_CONTROL 0xe000ed10u +#define CYREG_NVIC_CFG_CONTROL 0xe000ed14u +#define CYREG_NVIC_SYS_PRIO_HANDLER_4_7 0xe000ed18u +#define CYREG_NVIC_SYS_PRIO_HANDLER_8_11 0xe000ed1cu +#define CYREG_NVIC_SYS_PRIO_HANDLER_12_15 0xe000ed20u +#define CYREG_NVIC_SYS_HANDLER_CSR 0xe000ed24u +#define CYREG_NVIC_MEMMAN_FAULT_STATUS 0xe000ed28u +#define CYREG_NVIC_BUS_FAULT_STATUS 0xe000ed29u +#define CYREG_NVIC_USAGE_FAULT_STATUS 0xe000ed2au +#define CYREG_NVIC_HARD_FAULT_STATUS 0xe000ed2cu +#define CYREG_NVIC_DEBUG_FAULT_STATUS 0xe000ed30u +#define CYREG_NVIC_MEMMAN_FAULT_ADD 0xe000ed34u +#define CYREG_NVIC_BUS_FAULT_ADD 0xe000ed38u +#define CYDEV_CORE_DBG_BASE 0xe000edf0u +#define CYDEV_CORE_DBG_SIZE 0x00000010u +#define CYREG_CORE_DBG_DBG_HLT_CS 0xe000edf0u +#define CYREG_CORE_DBG_DBG_REG_SEL 0xe000edf4u +#define CYREG_CORE_DBG_DBG_REG_DATA 0xe000edf8u +#define CYREG_CORE_DBG_EXC_MON_CTL 0xe000edfcu +#define CYDEV_TPIU_BASE 0xe0040000u +#define CYDEV_TPIU_SIZE 0x00001000u +#define CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ 0xe0040000u +#define CYREG_TPIU_CURRENT_SYNC_PRT_SZ 0xe0040004u +#define CYREG_TPIU_ASYNC_CLK_PRESCALER 0xe0040010u +#define CYREG_TPIU_PROTOCOL 0xe00400f0u +#define CYREG_TPIU_FORM_FLUSH_STAT 0xe0040300u +#define CYREG_TPIU_FORM_FLUSH_CTRL 0xe0040304u +#define CYREG_TPIU_TRIGGER 0xe0040ee8u +#define CYREG_TPIU_ITETMDATA 0xe0040eecu +#define CYREG_TPIU_ITATBCTR2 0xe0040ef0u +#define CYREG_TPIU_ITATBCTR0 0xe0040ef8u +#define CYREG_TPIU_ITITMDATA 0xe0040efcu +#define CYREG_TPIU_ITCTRL 0xe0040f00u +#define CYREG_TPIU_DEVID 0xe0040fc8u +#define CYREG_TPIU_DEVTYPE 0xe0040fccu +#define CYREG_TPIU_PID4 0xe0040fd0u +#define CYREG_TPIU_PID5 0xe0040fd4u +#define CYREG_TPIU_PID6 0xe0040fd8u +#define CYREG_TPIU_PID7 0xe0040fdcu +#define CYREG_TPIU_PID0 0xe0040fe0u +#define CYREG_TPIU_PID1 0xe0040fe4u +#define CYREG_TPIU_PID2 0xe0040fe8u +#define CYREG_TPIU_PID3 0xe0040fecu +#define CYREG_TPIU_CID0 0xe0040ff0u +#define CYREG_TPIU_CID1 0xe0040ff4u +#define CYREG_TPIU_CID2 0xe0040ff8u +#define CYREG_TPIU_CID3 0xe0040ffcu +#define CYDEV_ETM_BASE 0xe0041000u +#define CYDEV_ETM_SIZE 0x00001000u +#define CYREG_ETM_CTL 0xe0041000u +#define CYREG_ETM_CFG_CODE 0xe0041004u +#define CYREG_ETM_TRIG_EVENT 0xe0041008u +#define CYREG_ETM_STATUS 0xe0041010u +#define CYREG_ETM_SYS_CFG 0xe0041014u +#define CYREG_ETM_TRACE_ENB_EVENT 0xe0041020u +#define CYREG_ETM_TRACE_EN_CTRL1 0xe0041024u +#define CYREG_ETM_FIFOFULL_LEVEL 0xe004102cu +#define CYREG_ETM_SYNC_FREQ 0xe00411e0u +#define CYREG_ETM_ETM_ID 0xe00411e4u +#define CYREG_ETM_CFG_CODE_EXT 0xe00411e8u +#define CYREG_ETM_TR_SS_EMBICE_CTRL 0xe00411f0u +#define CYREG_ETM_CS_TRACE_ID 0xe0041200u +#define CYREG_ETM_OS_LOCK_ACCESS 0xe0041300u +#define CYREG_ETM_OS_LOCK_STATUS 0xe0041304u +#define CYREG_ETM_PDSR 0xe0041314u +#define CYREG_ETM_ITMISCIN 0xe0041ee0u +#define CYREG_ETM_ITTRIGOUT 0xe0041ee8u +#define CYREG_ETM_ITATBCTR2 0xe0041ef0u +#define CYREG_ETM_ITATBCTR0 0xe0041ef8u +#define CYREG_ETM_INT_MODE_CTRL 0xe0041f00u +#define CYREG_ETM_CLM_TAG_SET 0xe0041fa0u +#define CYREG_ETM_CLM_TAG_CLR 0xe0041fa4u +#define CYREG_ETM_LOCK_ACCESS 0xe0041fb0u +#define CYREG_ETM_LOCK_STATUS 0xe0041fb4u +#define CYREG_ETM_AUTH_STATUS 0xe0041fb8u +#define CYREG_ETM_DEV_TYPE 0xe0041fccu +#define CYREG_ETM_PID4 0xe0041fd0u +#define CYREG_ETM_PID5 0xe0041fd4u +#define CYREG_ETM_PID6 0xe0041fd8u +#define CYREG_ETM_PID7 0xe0041fdcu +#define CYREG_ETM_PID0 0xe0041fe0u +#define CYREG_ETM_PID1 0xe0041fe4u +#define CYREG_ETM_PID2 0xe0041fe8u +#define CYREG_ETM_PID3 0xe0041fecu +#define CYREG_ETM_CID0 0xe0041ff0u +#define CYREG_ETM_CID1 0xe0041ff4u +#define CYREG_ETM_CID2 0xe0041ff8u +#define CYREG_ETM_CID3 0xe0041ffcu +#define CYDEV_ROM_TABLE_BASE 0xe00ff000u +#define CYDEV_ROM_TABLE_SIZE 0x00001000u +#define CYREG_ROM_TABLE_NVIC 0xe00ff000u +#define CYREG_ROM_TABLE_DWT 0xe00ff004u +#define CYREG_ROM_TABLE_FPB 0xe00ff008u +#define CYREG_ROM_TABLE_ITM 0xe00ff00cu +#define CYREG_ROM_TABLE_TPIU 0xe00ff010u +#define CYREG_ROM_TABLE_ETM 0xe00ff014u +#define CYREG_ROM_TABLE_END 0xe00ff018u +#define CYREG_ROM_TABLE_MEMTYPE 0xe00fffccu +#define CYREG_ROM_TABLE_PID4 0xe00fffd0u +#define CYREG_ROM_TABLE_PID5 0xe00fffd4u +#define CYREG_ROM_TABLE_PID6 0xe00fffd8u +#define CYREG_ROM_TABLE_PID7 0xe00fffdcu +#define CYREG_ROM_TABLE_PID0 0xe00fffe0u +#define CYREG_ROM_TABLE_PID1 0xe00fffe4u +#define CYREG_ROM_TABLE_PID2 0xe00fffe8u +#define CYREG_ROM_TABLE_PID3 0xe00fffecu +#define CYREG_ROM_TABLE_CID0 0xe00ffff0u +#define CYREG_ROM_TABLE_CID1 0xe00ffff4u +#define CYREG_ROM_TABLE_CID2 0xe00ffff8u +#define CYREG_ROM_TABLE_CID3 0xe00ffffcu +#define CYDEV_FLS_SIZE CYDEV_FLASH_SIZE +#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE +#define CYDEV_FLS_SECTOR_SIZE 0x00010000u +#define CYDEV_FLS_ROW_SIZE 0x00000100u +#define CYDEV_ECC_SECTOR_SIZE 0x00002000u +#define CYDEV_ECC_ROW_SIZE 0x00000020u +#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400u +#define CYDEV_EEPROM_ROW_SIZE 0x00000010u +#define CYDEV_PERIPH_BASE CYDEV_CLKDIST_BASE +#define CYCLK_LD_DISABLE 0x00000004u +#define CYCLK_LD_SYNC_EN 0x00000002u +#define CYCLK_LD_LOAD 0x00000001u +#define CYCLK_PIPE 0x00000080u +#define CYCLK_SSS 0x00000040u +#define CYCLK_EARLY 0x00000020u +#define CYCLK_DUTY 0x00000010u +#define CYCLK_SYNC 0x00000008u +#define CYCLK_SRC_SEL_CLK_SYNC_D 0 +#define CYCLK_SRC_SEL_SYNC_DIG 0 +#define CYCLK_SRC_SEL_IMO 1 +#define CYCLK_SRC_SEL_XTAL_MHZ 2 +#define CYCLK_SRC_SEL_XTALM 2 +#define CYCLK_SRC_SEL_ILO 3 +#define CYCLK_SRC_SEL_PLL 4 +#define CYCLK_SRC_SEL_XTAL_KHZ 5 +#define CYCLK_SRC_SEL_XTALK 5 +#define CYCLK_SRC_SEL_DSI_G 6 +#define CYCLK_SRC_SEL_DSI_D 7 +#define CYCLK_SRC_SEL_CLK_SYNC_A 0 +#define CYCLK_SRC_SEL_DSI_A 7 +#endif /* CYDEVICE_TRM_H */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydevicegnu.inc b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydevicegnu.inc new file mode 100755 index 00000000..dc11e6db --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydevicegnu.inc @@ -0,0 +1,5357 @@ +/******************************************************************************* +* FILENAME: cydevicegnu.inc +* OBSOLETE: Do not use this file. Use the _trm version instead. +* PSoC Creator 3.0 Component Pack 7 +* +* DESCRIPTION: +* This file provides all of the address values for the entire PSoC device. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +.set CYDEV_FLASH_BASE, 0x00000000 +.set CYDEV_FLASH_SIZE, 0x00020000 +.set CYDEV_FLASH_DATA_MBASE, 0x00000000 +.set CYDEV_FLASH_DATA_MSIZE, 0x00020000 +.set CYDEV_SRAM_BASE, 0x1fffc000 +.set CYDEV_SRAM_SIZE, 0x00008000 +.set CYDEV_SRAM_CODE64K_MBASE, 0x1fff8000 +.set CYDEV_SRAM_CODE64K_MSIZE, 0x00004000 +.set CYDEV_SRAM_CODE32K_MBASE, 0x1fffc000 +.set CYDEV_SRAM_CODE32K_MSIZE, 0x00002000 +.set CYDEV_SRAM_CODE16K_MBASE, 0x1fffe000 +.set CYDEV_SRAM_CODE16K_MSIZE, 0x00001000 +.set CYDEV_SRAM_CODE_MBASE, 0x1fffc000 +.set CYDEV_SRAM_CODE_MSIZE, 0x00004000 +.set CYDEV_SRAM_DATA_MBASE, 0x20000000 +.set CYDEV_SRAM_DATA_MSIZE, 0x00004000 +.set CYDEV_SRAM_DATA16K_MBASE, 0x20001000 +.set CYDEV_SRAM_DATA16K_MSIZE, 0x00001000 +.set CYDEV_SRAM_DATA32K_MBASE, 0x20002000 +.set CYDEV_SRAM_DATA32K_MSIZE, 0x00002000 +.set CYDEV_SRAM_DATA64K_MBASE, 0x20004000 +.set CYDEV_SRAM_DATA64K_MSIZE, 0x00004000 +.set CYDEV_DMA_BASE, 0x20008000 +.set CYDEV_DMA_SIZE, 0x00008000 +.set CYDEV_DMA_SRAM64K_MBASE, 0x20008000 +.set CYDEV_DMA_SRAM64K_MSIZE, 0x00004000 +.set CYDEV_DMA_SRAM32K_MBASE, 0x2000c000 +.set CYDEV_DMA_SRAM32K_MSIZE, 0x00002000 +.set CYDEV_DMA_SRAM16K_MBASE, 0x2000e000 +.set CYDEV_DMA_SRAM16K_MSIZE, 0x00001000 +.set CYDEV_DMA_SRAM_MBASE, 0x2000f000 +.set CYDEV_DMA_SRAM_MSIZE, 0x00001000 +.set CYDEV_CLKDIST_BASE, 0x40004000 +.set CYDEV_CLKDIST_SIZE, 0x00000110 +.set CYDEV_CLKDIST_CR, 0x40004000 +.set CYDEV_CLKDIST_LD, 0x40004001 +.set CYDEV_CLKDIST_WRK0, 0x40004002 +.set CYDEV_CLKDIST_WRK1, 0x40004003 +.set CYDEV_CLKDIST_MSTR0, 0x40004004 +.set CYDEV_CLKDIST_MSTR1, 0x40004005 +.set CYDEV_CLKDIST_BCFG0, 0x40004006 +.set CYDEV_CLKDIST_BCFG1, 0x40004007 +.set CYDEV_CLKDIST_BCFG2, 0x40004008 +.set CYDEV_CLKDIST_UCFG, 0x40004009 +.set CYDEV_CLKDIST_DLY0, 0x4000400a +.set CYDEV_CLKDIST_DLY1, 0x4000400b +.set CYDEV_CLKDIST_DMASK, 0x40004010 +.set CYDEV_CLKDIST_AMASK, 0x40004014 +.set CYDEV_CLKDIST_DCFG0_BASE, 0x40004080 +.set CYDEV_CLKDIST_DCFG0_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG0_CFG0, 0x40004080 +.set CYDEV_CLKDIST_DCFG0_CFG1, 0x40004081 +.set CYDEV_CLKDIST_DCFG0_CFG2, 0x40004082 +.set CYDEV_CLKDIST_DCFG1_BASE, 0x40004084 +.set CYDEV_CLKDIST_DCFG1_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG1_CFG0, 0x40004084 +.set CYDEV_CLKDIST_DCFG1_CFG1, 0x40004085 +.set CYDEV_CLKDIST_DCFG1_CFG2, 0x40004086 +.set CYDEV_CLKDIST_DCFG2_BASE, 0x40004088 +.set CYDEV_CLKDIST_DCFG2_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG2_CFG0, 0x40004088 +.set CYDEV_CLKDIST_DCFG2_CFG1, 0x40004089 +.set CYDEV_CLKDIST_DCFG2_CFG2, 0x4000408a +.set CYDEV_CLKDIST_DCFG3_BASE, 0x4000408c +.set CYDEV_CLKDIST_DCFG3_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG3_CFG0, 0x4000408c +.set CYDEV_CLKDIST_DCFG3_CFG1, 0x4000408d +.set CYDEV_CLKDIST_DCFG3_CFG2, 0x4000408e +.set CYDEV_CLKDIST_DCFG4_BASE, 0x40004090 +.set CYDEV_CLKDIST_DCFG4_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG4_CFG0, 0x40004090 +.set CYDEV_CLKDIST_DCFG4_CFG1, 0x40004091 +.set CYDEV_CLKDIST_DCFG4_CFG2, 0x40004092 +.set CYDEV_CLKDIST_DCFG5_BASE, 0x40004094 +.set CYDEV_CLKDIST_DCFG5_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG5_CFG0, 0x40004094 +.set CYDEV_CLKDIST_DCFG5_CFG1, 0x40004095 +.set CYDEV_CLKDIST_DCFG5_CFG2, 0x40004096 +.set CYDEV_CLKDIST_DCFG6_BASE, 0x40004098 +.set CYDEV_CLKDIST_DCFG6_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG6_CFG0, 0x40004098 +.set CYDEV_CLKDIST_DCFG6_CFG1, 0x40004099 +.set CYDEV_CLKDIST_DCFG6_CFG2, 0x4000409a +.set CYDEV_CLKDIST_DCFG7_BASE, 0x4000409c +.set CYDEV_CLKDIST_DCFG7_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG7_CFG0, 0x4000409c +.set CYDEV_CLKDIST_DCFG7_CFG1, 0x4000409d +.set CYDEV_CLKDIST_DCFG7_CFG2, 0x4000409e +.set CYDEV_CLKDIST_ACFG0_BASE, 0x40004100 +.set CYDEV_CLKDIST_ACFG0_SIZE, 0x00000004 +.set CYDEV_CLKDIST_ACFG0_CFG0, 0x40004100 +.set CYDEV_CLKDIST_ACFG0_CFG1, 0x40004101 +.set CYDEV_CLKDIST_ACFG0_CFG2, 0x40004102 +.set CYDEV_CLKDIST_ACFG0_CFG3, 0x40004103 +.set CYDEV_CLKDIST_ACFG1_BASE, 0x40004104 +.set CYDEV_CLKDIST_ACFG1_SIZE, 0x00000004 +.set CYDEV_CLKDIST_ACFG1_CFG0, 0x40004104 +.set CYDEV_CLKDIST_ACFG1_CFG1, 0x40004105 +.set CYDEV_CLKDIST_ACFG1_CFG2, 0x40004106 +.set CYDEV_CLKDIST_ACFG1_CFG3, 0x40004107 +.set CYDEV_CLKDIST_ACFG2_BASE, 0x40004108 +.set CYDEV_CLKDIST_ACFG2_SIZE, 0x00000004 +.set CYDEV_CLKDIST_ACFG2_CFG0, 0x40004108 +.set CYDEV_CLKDIST_ACFG2_CFG1, 0x40004109 +.set CYDEV_CLKDIST_ACFG2_CFG2, 0x4000410a +.set CYDEV_CLKDIST_ACFG2_CFG3, 0x4000410b +.set CYDEV_CLKDIST_ACFG3_BASE, 0x4000410c +.set CYDEV_CLKDIST_ACFG3_SIZE, 0x00000004 +.set CYDEV_CLKDIST_ACFG3_CFG0, 0x4000410c +.set CYDEV_CLKDIST_ACFG3_CFG1, 0x4000410d +.set CYDEV_CLKDIST_ACFG3_CFG2, 0x4000410e +.set CYDEV_CLKDIST_ACFG3_CFG3, 0x4000410f +.set CYDEV_FASTCLK_BASE, 0x40004200 +.set CYDEV_FASTCLK_SIZE, 0x00000026 +.set CYDEV_FASTCLK_IMO_BASE, 0x40004200 +.set CYDEV_FASTCLK_IMO_SIZE, 0x00000001 +.set CYDEV_FASTCLK_IMO_CR, 0x40004200 +.set CYDEV_FASTCLK_XMHZ_BASE, 0x40004210 +.set CYDEV_FASTCLK_XMHZ_SIZE, 0x00000004 +.set CYDEV_FASTCLK_XMHZ_CSR, 0x40004210 +.set CYDEV_FASTCLK_XMHZ_CFG0, 0x40004212 +.set CYDEV_FASTCLK_XMHZ_CFG1, 0x40004213 +.set CYDEV_FASTCLK_PLL_BASE, 0x40004220 +.set CYDEV_FASTCLK_PLL_SIZE, 0x00000006 +.set CYDEV_FASTCLK_PLL_CFG0, 0x40004220 +.set CYDEV_FASTCLK_PLL_CFG1, 0x40004221 +.set CYDEV_FASTCLK_PLL_P, 0x40004222 +.set CYDEV_FASTCLK_PLL_Q, 0x40004223 +.set CYDEV_FASTCLK_PLL_SR, 0x40004225 +.set CYDEV_SLOWCLK_BASE, 0x40004300 +.set CYDEV_SLOWCLK_SIZE, 0x0000000b +.set CYDEV_SLOWCLK_ILO_BASE, 0x40004300 +.set CYDEV_SLOWCLK_ILO_SIZE, 0x00000002 +.set CYDEV_SLOWCLK_ILO_CR0, 0x40004300 +.set CYDEV_SLOWCLK_ILO_CR1, 0x40004301 +.set CYDEV_SLOWCLK_X32_BASE, 0x40004308 +.set CYDEV_SLOWCLK_X32_SIZE, 0x00000003 +.set CYDEV_SLOWCLK_X32_CR, 0x40004308 +.set CYDEV_SLOWCLK_X32_CFG, 0x40004309 +.set CYDEV_SLOWCLK_X32_TST, 0x4000430a +.set CYDEV_BOOST_BASE, 0x40004320 +.set CYDEV_BOOST_SIZE, 0x00000007 +.set CYDEV_BOOST_CR0, 0x40004320 +.set CYDEV_BOOST_CR1, 0x40004321 +.set CYDEV_BOOST_CR2, 0x40004322 +.set CYDEV_BOOST_CR3, 0x40004323 +.set CYDEV_BOOST_SR, 0x40004324 +.set CYDEV_BOOST_CR4, 0x40004325 +.set CYDEV_BOOST_SR2, 0x40004326 +.set CYDEV_PWRSYS_BASE, 0x40004330 +.set CYDEV_PWRSYS_SIZE, 0x00000002 +.set CYDEV_PWRSYS_CR0, 0x40004330 +.set CYDEV_PWRSYS_CR1, 0x40004331 +.set CYDEV_PM_BASE, 0x40004380 +.set CYDEV_PM_SIZE, 0x00000057 +.set CYDEV_PM_TW_CFG0, 0x40004380 +.set CYDEV_PM_TW_CFG1, 0x40004381 +.set CYDEV_PM_TW_CFG2, 0x40004382 +.set CYDEV_PM_WDT_CFG, 0x40004383 +.set CYDEV_PM_WDT_CR, 0x40004384 +.set CYDEV_PM_INT_SR, 0x40004390 +.set CYDEV_PM_MODE_CFG0, 0x40004391 +.set CYDEV_PM_MODE_CFG1, 0x40004392 +.set CYDEV_PM_MODE_CSR, 0x40004393 +.set CYDEV_PM_USB_CR0, 0x40004394 +.set CYDEV_PM_WAKEUP_CFG0, 0x40004398 +.set CYDEV_PM_WAKEUP_CFG1, 0x40004399 +.set CYDEV_PM_WAKEUP_CFG2, 0x4000439a +.set CYDEV_PM_ACT_BASE, 0x400043a0 +.set CYDEV_PM_ACT_SIZE, 0x0000000e +.set CYDEV_PM_ACT_CFG0, 0x400043a0 +.set CYDEV_PM_ACT_CFG1, 0x400043a1 +.set CYDEV_PM_ACT_CFG2, 0x400043a2 +.set CYDEV_PM_ACT_CFG3, 0x400043a3 +.set CYDEV_PM_ACT_CFG4, 0x400043a4 +.set CYDEV_PM_ACT_CFG5, 0x400043a5 +.set CYDEV_PM_ACT_CFG6, 0x400043a6 +.set CYDEV_PM_ACT_CFG7, 0x400043a7 +.set CYDEV_PM_ACT_CFG8, 0x400043a8 +.set CYDEV_PM_ACT_CFG9, 0x400043a9 +.set CYDEV_PM_ACT_CFG10, 0x400043aa +.set CYDEV_PM_ACT_CFG11, 0x400043ab +.set CYDEV_PM_ACT_CFG12, 0x400043ac +.set CYDEV_PM_ACT_CFG13, 0x400043ad +.set CYDEV_PM_STBY_BASE, 0x400043b0 +.set CYDEV_PM_STBY_SIZE, 0x0000000e +.set CYDEV_PM_STBY_CFG0, 0x400043b0 +.set CYDEV_PM_STBY_CFG1, 0x400043b1 +.set CYDEV_PM_STBY_CFG2, 0x400043b2 +.set CYDEV_PM_STBY_CFG3, 0x400043b3 +.set CYDEV_PM_STBY_CFG4, 0x400043b4 +.set CYDEV_PM_STBY_CFG5, 0x400043b5 +.set CYDEV_PM_STBY_CFG6, 0x400043b6 +.set CYDEV_PM_STBY_CFG7, 0x400043b7 +.set CYDEV_PM_STBY_CFG8, 0x400043b8 +.set CYDEV_PM_STBY_CFG9, 0x400043b9 +.set CYDEV_PM_STBY_CFG10, 0x400043ba +.set CYDEV_PM_STBY_CFG11, 0x400043bb +.set CYDEV_PM_STBY_CFG12, 0x400043bc +.set CYDEV_PM_STBY_CFG13, 0x400043bd +.set CYDEV_PM_AVAIL_BASE, 0x400043c0 +.set CYDEV_PM_AVAIL_SIZE, 0x00000017 +.set CYDEV_PM_AVAIL_CR0, 0x400043c0 +.set CYDEV_PM_AVAIL_CR1, 0x400043c1 +.set CYDEV_PM_AVAIL_CR2, 0x400043c2 +.set CYDEV_PM_AVAIL_CR3, 0x400043c3 +.set CYDEV_PM_AVAIL_CR4, 0x400043c4 +.set CYDEV_PM_AVAIL_CR5, 0x400043c5 +.set CYDEV_PM_AVAIL_CR6, 0x400043c6 +.set CYDEV_PM_AVAIL_SR0, 0x400043d0 +.set CYDEV_PM_AVAIL_SR1, 0x400043d1 +.set CYDEV_PM_AVAIL_SR2, 0x400043d2 +.set CYDEV_PM_AVAIL_SR3, 0x400043d3 +.set CYDEV_PM_AVAIL_SR4, 0x400043d4 +.set CYDEV_PM_AVAIL_SR5, 0x400043d5 +.set CYDEV_PM_AVAIL_SR6, 0x400043d6 +.set CYDEV_PICU_BASE, 0x40004500 +.set CYDEV_PICU_SIZE, 0x000000b0 +.set CYDEV_PICU_INTTYPE_BASE, 0x40004500 +.set CYDEV_PICU_INTTYPE_SIZE, 0x00000080 +.set CYDEV_PICU_INTTYPE_PICU0_BASE, 0x40004500 +.set CYDEV_PICU_INTTYPE_PICU0_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE0, 0x40004500 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE1, 0x40004501 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE2, 0x40004502 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE3, 0x40004503 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE4, 0x40004504 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE5, 0x40004505 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE6, 0x40004506 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE7, 0x40004507 +.set CYDEV_PICU_INTTYPE_PICU1_BASE, 0x40004508 +.set CYDEV_PICU_INTTYPE_PICU1_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE0, 0x40004508 +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE1, 0x40004509 +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE2, 0x4000450a +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE3, 0x4000450b +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE4, 0x4000450c +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE5, 0x4000450d +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE6, 0x4000450e +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE7, 0x4000450f +.set CYDEV_PICU_INTTYPE_PICU2_BASE, 0x40004510 +.set CYDEV_PICU_INTTYPE_PICU2_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE0, 0x40004510 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE1, 0x40004511 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE2, 0x40004512 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE3, 0x40004513 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE4, 0x40004514 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE5, 0x40004515 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE6, 0x40004516 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE7, 0x40004517 +.set CYDEV_PICU_INTTYPE_PICU3_BASE, 0x40004518 +.set CYDEV_PICU_INTTYPE_PICU3_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE0, 0x40004518 +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE1, 0x40004519 +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE2, 0x4000451a +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE3, 0x4000451b +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE4, 0x4000451c +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE5, 0x4000451d +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE6, 0x4000451e +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE7, 0x4000451f +.set CYDEV_PICU_INTTYPE_PICU4_BASE, 0x40004520 +.set CYDEV_PICU_INTTYPE_PICU4_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE0, 0x40004520 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE1, 0x40004521 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE2, 0x40004522 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE3, 0x40004523 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE4, 0x40004524 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE5, 0x40004525 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE6, 0x40004526 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE7, 0x40004527 +.set CYDEV_PICU_INTTYPE_PICU5_BASE, 0x40004528 +.set CYDEV_PICU_INTTYPE_PICU5_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE0, 0x40004528 +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE1, 0x40004529 +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE2, 0x4000452a +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE3, 0x4000452b +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE4, 0x4000452c +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE5, 0x4000452d +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE6, 0x4000452e +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE7, 0x4000452f +.set CYDEV_PICU_INTTYPE_PICU6_BASE, 0x40004530 +.set CYDEV_PICU_INTTYPE_PICU6_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE0, 0x40004530 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE1, 0x40004531 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE2, 0x40004532 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE3, 0x40004533 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE4, 0x40004534 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE5, 0x40004535 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE6, 0x40004536 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE7, 0x40004537 +.set CYDEV_PICU_INTTYPE_PICU12_BASE, 0x40004560 +.set CYDEV_PICU_INTTYPE_PICU12_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE0, 0x40004560 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE1, 0x40004561 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE2, 0x40004562 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE3, 0x40004563 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE4, 0x40004564 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE5, 0x40004565 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE6, 0x40004566 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE7, 0x40004567 +.set CYDEV_PICU_INTTYPE_PICU15_BASE, 0x40004578 +.set CYDEV_PICU_INTTYPE_PICU15_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE0, 0x40004578 +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE1, 0x40004579 +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE2, 0x4000457a +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE3, 0x4000457b +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE4, 0x4000457c +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE5, 0x4000457d +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE6, 0x4000457e +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE7, 0x4000457f +.set CYDEV_PICU_STAT_BASE, 0x40004580 +.set CYDEV_PICU_STAT_SIZE, 0x00000010 +.set CYDEV_PICU_STAT_PICU0_BASE, 0x40004580 +.set CYDEV_PICU_STAT_PICU0_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU0_INTSTAT, 0x40004580 +.set CYDEV_PICU_STAT_PICU1_BASE, 0x40004581 +.set CYDEV_PICU_STAT_PICU1_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU1_INTSTAT, 0x40004581 +.set CYDEV_PICU_STAT_PICU2_BASE, 0x40004582 +.set CYDEV_PICU_STAT_PICU2_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU2_INTSTAT, 0x40004582 +.set CYDEV_PICU_STAT_PICU3_BASE, 0x40004583 +.set CYDEV_PICU_STAT_PICU3_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU3_INTSTAT, 0x40004583 +.set CYDEV_PICU_STAT_PICU4_BASE, 0x40004584 +.set CYDEV_PICU_STAT_PICU4_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU4_INTSTAT, 0x40004584 +.set CYDEV_PICU_STAT_PICU5_BASE, 0x40004585 +.set CYDEV_PICU_STAT_PICU5_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU5_INTSTAT, 0x40004585 +.set CYDEV_PICU_STAT_PICU6_BASE, 0x40004586 +.set CYDEV_PICU_STAT_PICU6_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU6_INTSTAT, 0x40004586 +.set CYDEV_PICU_STAT_PICU12_BASE, 0x4000458c +.set CYDEV_PICU_STAT_PICU12_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU12_INTSTAT, 0x4000458c +.set CYDEV_PICU_STAT_PICU15_BASE, 0x4000458f +.set CYDEV_PICU_STAT_PICU15_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU15_INTSTAT, 0x4000458f +.set CYDEV_PICU_SNAP_BASE, 0x40004590 +.set CYDEV_PICU_SNAP_SIZE, 0x00000010 +.set CYDEV_PICU_SNAP_PICU0_BASE, 0x40004590 +.set CYDEV_PICU_SNAP_PICU0_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU0_SNAP, 0x40004590 +.set CYDEV_PICU_SNAP_PICU1_BASE, 0x40004591 +.set CYDEV_PICU_SNAP_PICU1_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU1_SNAP, 0x40004591 +.set CYDEV_PICU_SNAP_PICU2_BASE, 0x40004592 +.set CYDEV_PICU_SNAP_PICU2_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU2_SNAP, 0x40004592 +.set CYDEV_PICU_SNAP_PICU3_BASE, 0x40004593 +.set CYDEV_PICU_SNAP_PICU3_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU3_SNAP, 0x40004593 +.set CYDEV_PICU_SNAP_PICU4_BASE, 0x40004594 +.set CYDEV_PICU_SNAP_PICU4_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU4_SNAP, 0x40004594 +.set CYDEV_PICU_SNAP_PICU5_BASE, 0x40004595 +.set CYDEV_PICU_SNAP_PICU5_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU5_SNAP, 0x40004595 +.set CYDEV_PICU_SNAP_PICU6_BASE, 0x40004596 +.set CYDEV_PICU_SNAP_PICU6_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU6_SNAP, 0x40004596 +.set CYDEV_PICU_SNAP_PICU12_BASE, 0x4000459c +.set CYDEV_PICU_SNAP_PICU12_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU12_SNAP, 0x4000459c +.set CYDEV_PICU_SNAP_PICU_15_BASE, 0x4000459f +.set CYDEV_PICU_SNAP_PICU_15_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU_15_SNAP_15, 0x4000459f +.set CYDEV_PICU_DISABLE_COR_BASE, 0x400045a0 +.set CYDEV_PICU_DISABLE_COR_SIZE, 0x00000010 +.set CYDEV_PICU_DISABLE_COR_PICU0_BASE, 0x400045a0 +.set CYDEV_PICU_DISABLE_COR_PICU0_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR, 0x400045a0 +.set CYDEV_PICU_DISABLE_COR_PICU1_BASE, 0x400045a1 +.set CYDEV_PICU_DISABLE_COR_PICU1_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR, 0x400045a1 +.set CYDEV_PICU_DISABLE_COR_PICU2_BASE, 0x400045a2 +.set CYDEV_PICU_DISABLE_COR_PICU2_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR, 0x400045a2 +.set CYDEV_PICU_DISABLE_COR_PICU3_BASE, 0x400045a3 +.set CYDEV_PICU_DISABLE_COR_PICU3_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR, 0x400045a3 +.set CYDEV_PICU_DISABLE_COR_PICU4_BASE, 0x400045a4 +.set CYDEV_PICU_DISABLE_COR_PICU4_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR, 0x400045a4 +.set CYDEV_PICU_DISABLE_COR_PICU5_BASE, 0x400045a5 +.set CYDEV_PICU_DISABLE_COR_PICU5_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR, 0x400045a5 +.set CYDEV_PICU_DISABLE_COR_PICU6_BASE, 0x400045a6 +.set CYDEV_PICU_DISABLE_COR_PICU6_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR, 0x400045a6 +.set CYDEV_PICU_DISABLE_COR_PICU12_BASE, 0x400045ac +.set CYDEV_PICU_DISABLE_COR_PICU12_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR, 0x400045ac +.set CYDEV_PICU_DISABLE_COR_PICU15_BASE, 0x400045af +.set CYDEV_PICU_DISABLE_COR_PICU15_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR, 0x400045af +.set CYDEV_MFGCFG_BASE, 0x40004600 +.set CYDEV_MFGCFG_SIZE, 0x000000ed +.set CYDEV_MFGCFG_ANAIF_BASE, 0x40004600 +.set CYDEV_MFGCFG_ANAIF_SIZE, 0x00000038 +.set CYDEV_MFGCFG_ANAIF_DAC0_BASE, 0x40004608 +.set CYDEV_MFGCFG_ANAIF_DAC0_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_DAC0_TR, 0x40004608 +.set CYDEV_MFGCFG_ANAIF_DAC1_BASE, 0x40004609 +.set CYDEV_MFGCFG_ANAIF_DAC1_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_DAC1_TR, 0x40004609 +.set CYDEV_MFGCFG_ANAIF_DAC2_BASE, 0x4000460a +.set CYDEV_MFGCFG_ANAIF_DAC2_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_DAC2_TR, 0x4000460a +.set CYDEV_MFGCFG_ANAIF_DAC3_BASE, 0x4000460b +.set CYDEV_MFGCFG_ANAIF_DAC3_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_DAC3_TR, 0x4000460b +.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE, 0x40004610 +.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0, 0x40004610 +.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE, 0x40004611 +.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0, 0x40004611 +.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE, 0x40004612 +.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0, 0x40004612 +.set CYDEV_MFGCFG_ANAIF_SAR0_BASE, 0x40004614 +.set CYDEV_MFGCFG_ANAIF_SAR0_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_SAR0_TR0, 0x40004614 +.set CYDEV_MFGCFG_ANAIF_SAR1_BASE, 0x40004616 +.set CYDEV_MFGCFG_ANAIF_SAR1_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_SAR1_TR0, 0x40004616 +.set CYDEV_MFGCFG_ANAIF_OPAMP0_BASE, 0x40004620 +.set CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_OPAMP0_TR0, 0x40004620 +.set CYDEV_MFGCFG_ANAIF_OPAMP0_TR1, 0x40004621 +.set CYDEV_MFGCFG_ANAIF_OPAMP1_BASE, 0x40004622 +.set CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_OPAMP1_TR0, 0x40004622 +.set CYDEV_MFGCFG_ANAIF_OPAMP1_TR1, 0x40004623 +.set CYDEV_MFGCFG_ANAIF_OPAMP2_BASE, 0x40004624 +.set CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_OPAMP2_TR0, 0x40004624 +.set CYDEV_MFGCFG_ANAIF_OPAMP2_TR1, 0x40004625 +.set CYDEV_MFGCFG_ANAIF_OPAMP3_BASE, 0x40004626 +.set CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_OPAMP3_TR0, 0x40004626 +.set CYDEV_MFGCFG_ANAIF_OPAMP3_TR1, 0x40004627 +.set CYDEV_MFGCFG_ANAIF_CMP0_BASE, 0x40004630 +.set CYDEV_MFGCFG_ANAIF_CMP0_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_CMP0_TR0, 0x40004630 +.set CYDEV_MFGCFG_ANAIF_CMP0_TR1, 0x40004631 +.set CYDEV_MFGCFG_ANAIF_CMP1_BASE, 0x40004632 +.set CYDEV_MFGCFG_ANAIF_CMP1_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_CMP1_TR0, 0x40004632 +.set CYDEV_MFGCFG_ANAIF_CMP1_TR1, 0x40004633 +.set CYDEV_MFGCFG_ANAIF_CMP2_BASE, 0x40004634 +.set CYDEV_MFGCFG_ANAIF_CMP2_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_CMP2_TR0, 0x40004634 +.set CYDEV_MFGCFG_ANAIF_CMP2_TR1, 0x40004635 +.set CYDEV_MFGCFG_ANAIF_CMP3_BASE, 0x40004636 +.set CYDEV_MFGCFG_ANAIF_CMP3_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_CMP3_TR0, 0x40004636 +.set CYDEV_MFGCFG_ANAIF_CMP3_TR1, 0x40004637 +.set CYDEV_MFGCFG_PWRSYS_BASE, 0x40004680 +.set CYDEV_MFGCFG_PWRSYS_SIZE, 0x0000000b +.set CYDEV_MFGCFG_PWRSYS_HIB_TR0, 0x40004680 +.set CYDEV_MFGCFG_PWRSYS_HIB_TR1, 0x40004681 +.set CYDEV_MFGCFG_PWRSYS_I2C_TR, 0x40004682 +.set CYDEV_MFGCFG_PWRSYS_SLP_TR, 0x40004683 +.set CYDEV_MFGCFG_PWRSYS_BUZZ_TR, 0x40004684 +.set CYDEV_MFGCFG_PWRSYS_WAKE_TR0, 0x40004685 +.set CYDEV_MFGCFG_PWRSYS_WAKE_TR1, 0x40004686 +.set CYDEV_MFGCFG_PWRSYS_BREF_TR, 0x40004687 +.set CYDEV_MFGCFG_PWRSYS_BG_TR, 0x40004688 +.set CYDEV_MFGCFG_PWRSYS_WAKE_TR2, 0x40004689 +.set CYDEV_MFGCFG_PWRSYS_WAKE_TR3, 0x4000468a +.set CYDEV_MFGCFG_ILO_BASE, 0x40004690 +.set CYDEV_MFGCFG_ILO_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ILO_TR0, 0x40004690 +.set CYDEV_MFGCFG_ILO_TR1, 0x40004691 +.set CYDEV_MFGCFG_X32_BASE, 0x40004698 +.set CYDEV_MFGCFG_X32_SIZE, 0x00000001 +.set CYDEV_MFGCFG_X32_TR, 0x40004698 +.set CYDEV_MFGCFG_IMO_BASE, 0x400046a0 +.set CYDEV_MFGCFG_IMO_SIZE, 0x00000005 +.set CYDEV_MFGCFG_IMO_TR0, 0x400046a0 +.set CYDEV_MFGCFG_IMO_TR1, 0x400046a1 +.set CYDEV_MFGCFG_IMO_GAIN, 0x400046a2 +.set CYDEV_MFGCFG_IMO_C36M, 0x400046a3 +.set CYDEV_MFGCFG_IMO_TR2, 0x400046a4 +.set CYDEV_MFGCFG_XMHZ_BASE, 0x400046a8 +.set CYDEV_MFGCFG_XMHZ_SIZE, 0x00000001 +.set CYDEV_MFGCFG_XMHZ_TR, 0x400046a8 +.set CYDEV_MFGCFG_DLY, 0x400046c0 +.set CYDEV_MFGCFG_MLOGIC_BASE, 0x400046e0 +.set CYDEV_MFGCFG_MLOGIC_SIZE, 0x0000000d +.set CYDEV_MFGCFG_MLOGIC_DMPSTR, 0x400046e2 +.set CYDEV_MFGCFG_MLOGIC_SEG_BASE, 0x400046e4 +.set CYDEV_MFGCFG_MLOGIC_SEG_SIZE, 0x00000002 +.set CYDEV_MFGCFG_MLOGIC_SEG_CR, 0x400046e4 +.set CYDEV_MFGCFG_MLOGIC_SEG_CFG0, 0x400046e5 +.set CYDEV_MFGCFG_MLOGIC_DEBUG, 0x400046e8 +.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE, 0x400046ea +.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE, 0x00000001 +.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR, 0x400046ea +.set CYDEV_MFGCFG_MLOGIC_REV_ID, 0x400046ec +.set CYDEV_RESET_BASE, 0x400046f0 +.set CYDEV_RESET_SIZE, 0x0000000f +.set CYDEV_RESET_IPOR_CR0, 0x400046f0 +.set CYDEV_RESET_IPOR_CR1, 0x400046f1 +.set CYDEV_RESET_IPOR_CR2, 0x400046f2 +.set CYDEV_RESET_IPOR_CR3, 0x400046f3 +.set CYDEV_RESET_CR0, 0x400046f4 +.set CYDEV_RESET_CR1, 0x400046f5 +.set CYDEV_RESET_CR2, 0x400046f6 +.set CYDEV_RESET_CR3, 0x400046f7 +.set CYDEV_RESET_CR4, 0x400046f8 +.set CYDEV_RESET_CR5, 0x400046f9 +.set CYDEV_RESET_SR0, 0x400046fa +.set CYDEV_RESET_SR1, 0x400046fb +.set CYDEV_RESET_SR2, 0x400046fc +.set CYDEV_RESET_SR3, 0x400046fd +.set CYDEV_RESET_TR, 0x400046fe +.set CYDEV_SPC_BASE, 0x40004700 +.set CYDEV_SPC_SIZE, 0x00000100 +.set CYDEV_SPC_FM_EE_CR, 0x40004700 +.set CYDEV_SPC_FM_EE_WAKE_CNT, 0x40004701 +.set CYDEV_SPC_EE_SCR, 0x40004702 +.set CYDEV_SPC_EE_ERR, 0x40004703 +.set CYDEV_SPC_CPU_DATA, 0x40004720 +.set CYDEV_SPC_DMA_DATA, 0x40004721 +.set CYDEV_SPC_SR, 0x40004722 +.set CYDEV_SPC_CR, 0x40004723 +.set CYDEV_SPC_DMM_MAP_BASE, 0x40004780 +.set CYDEV_SPC_DMM_MAP_SIZE, 0x00000080 +.set CYDEV_SPC_DMM_MAP_SRAM_MBASE, 0x40004780 +.set CYDEV_SPC_DMM_MAP_SRAM_MSIZE, 0x00000080 +.set CYDEV_CACHE_BASE, 0x40004800 +.set CYDEV_CACHE_SIZE, 0x0000009c +.set CYDEV_CACHE_CC_CTL, 0x40004800 +.set CYDEV_CACHE_ECC_CORR, 0x40004880 +.set CYDEV_CACHE_ECC_ERR, 0x40004888 +.set CYDEV_CACHE_FLASH_ERR, 0x40004890 +.set CYDEV_CACHE_HITMISS, 0x40004898 +.set CYDEV_I2C_BASE, 0x40004900 +.set CYDEV_I2C_SIZE, 0x000000e1 +.set CYDEV_I2C_XCFG, 0x400049c8 +.set CYDEV_I2C_ADR, 0x400049ca +.set CYDEV_I2C_CFG, 0x400049d6 +.set CYDEV_I2C_CSR, 0x400049d7 +.set CYDEV_I2C_D, 0x400049d8 +.set CYDEV_I2C_MCSR, 0x400049d9 +.set CYDEV_I2C_CLK_DIV1, 0x400049db +.set CYDEV_I2C_CLK_DIV2, 0x400049dc +.set CYDEV_I2C_TMOUT_CSR, 0x400049dd +.set CYDEV_I2C_TMOUT_SR, 0x400049de +.set CYDEV_I2C_TMOUT_CFG0, 0x400049df +.set CYDEV_I2C_TMOUT_CFG1, 0x400049e0 +.set CYDEV_DEC_BASE, 0x40004e00 +.set CYDEV_DEC_SIZE, 0x00000015 +.set CYDEV_DEC_CR, 0x40004e00 +.set CYDEV_DEC_SR, 0x40004e01 +.set CYDEV_DEC_SHIFT1, 0x40004e02 +.set CYDEV_DEC_SHIFT2, 0x40004e03 +.set CYDEV_DEC_DR2, 0x40004e04 +.set CYDEV_DEC_DR2H, 0x40004e05 +.set CYDEV_DEC_DR1, 0x40004e06 +.set CYDEV_DEC_OCOR, 0x40004e08 +.set CYDEV_DEC_OCORM, 0x40004e09 +.set CYDEV_DEC_OCORH, 0x40004e0a +.set CYDEV_DEC_GCOR, 0x40004e0c +.set CYDEV_DEC_GCORH, 0x40004e0d +.set CYDEV_DEC_GVAL, 0x40004e0e +.set CYDEV_DEC_OUTSAMP, 0x40004e10 +.set CYDEV_DEC_OUTSAMPM, 0x40004e11 +.set CYDEV_DEC_OUTSAMPH, 0x40004e12 +.set CYDEV_DEC_OUTSAMPS, 0x40004e13 +.set CYDEV_DEC_COHER, 0x40004e14 +.set CYDEV_TMR0_BASE, 0x40004f00 +.set CYDEV_TMR0_SIZE, 0x0000000c +.set CYDEV_TMR0_CFG0, 0x40004f00 +.set CYDEV_TMR0_CFG1, 0x40004f01 +.set CYDEV_TMR0_CFG2, 0x40004f02 +.set CYDEV_TMR0_SR0, 0x40004f03 +.set CYDEV_TMR0_PER0, 0x40004f04 +.set CYDEV_TMR0_PER1, 0x40004f05 +.set CYDEV_TMR0_CNT_CMP0, 0x40004f06 +.set CYDEV_TMR0_CNT_CMP1, 0x40004f07 +.set CYDEV_TMR0_CAP0, 0x40004f08 +.set CYDEV_TMR0_CAP1, 0x40004f09 +.set CYDEV_TMR0_RT0, 0x40004f0a +.set CYDEV_TMR0_RT1, 0x40004f0b +.set CYDEV_TMR1_BASE, 0x40004f0c +.set CYDEV_TMR1_SIZE, 0x0000000c +.set CYDEV_TMR1_CFG0, 0x40004f0c +.set CYDEV_TMR1_CFG1, 0x40004f0d +.set CYDEV_TMR1_CFG2, 0x40004f0e +.set CYDEV_TMR1_SR0, 0x40004f0f +.set CYDEV_TMR1_PER0, 0x40004f10 +.set CYDEV_TMR1_PER1, 0x40004f11 +.set CYDEV_TMR1_CNT_CMP0, 0x40004f12 +.set CYDEV_TMR1_CNT_CMP1, 0x40004f13 +.set CYDEV_TMR1_CAP0, 0x40004f14 +.set CYDEV_TMR1_CAP1, 0x40004f15 +.set CYDEV_TMR1_RT0, 0x40004f16 +.set CYDEV_TMR1_RT1, 0x40004f17 +.set CYDEV_TMR2_BASE, 0x40004f18 +.set CYDEV_TMR2_SIZE, 0x0000000c +.set CYDEV_TMR2_CFG0, 0x40004f18 +.set CYDEV_TMR2_CFG1, 0x40004f19 +.set CYDEV_TMR2_CFG2, 0x40004f1a +.set CYDEV_TMR2_SR0, 0x40004f1b +.set CYDEV_TMR2_PER0, 0x40004f1c +.set CYDEV_TMR2_PER1, 0x40004f1d +.set CYDEV_TMR2_CNT_CMP0, 0x40004f1e +.set CYDEV_TMR2_CNT_CMP1, 0x40004f1f +.set CYDEV_TMR2_CAP0, 0x40004f20 +.set CYDEV_TMR2_CAP1, 0x40004f21 +.set CYDEV_TMR2_RT0, 0x40004f22 +.set CYDEV_TMR2_RT1, 0x40004f23 +.set CYDEV_TMR3_BASE, 0x40004f24 +.set CYDEV_TMR3_SIZE, 0x0000000c +.set CYDEV_TMR3_CFG0, 0x40004f24 +.set CYDEV_TMR3_CFG1, 0x40004f25 +.set CYDEV_TMR3_CFG2, 0x40004f26 +.set CYDEV_TMR3_SR0, 0x40004f27 +.set CYDEV_TMR3_PER0, 0x40004f28 +.set CYDEV_TMR3_PER1, 0x40004f29 +.set CYDEV_TMR3_CNT_CMP0, 0x40004f2a +.set CYDEV_TMR3_CNT_CMP1, 0x40004f2b +.set CYDEV_TMR3_CAP0, 0x40004f2c +.set CYDEV_TMR3_CAP1, 0x40004f2d +.set CYDEV_TMR3_RT0, 0x40004f2e +.set CYDEV_TMR3_RT1, 0x40004f2f +.set CYDEV_IO_BASE, 0x40005000 +.set CYDEV_IO_SIZE, 0x00000200 +.set CYDEV_IO_PC_BASE, 0x40005000 +.set CYDEV_IO_PC_SIZE, 0x00000080 +.set CYDEV_IO_PC_PRT0_BASE, 0x40005000 +.set CYDEV_IO_PC_PRT0_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT0_PC0, 0x40005000 +.set CYDEV_IO_PC_PRT0_PC1, 0x40005001 +.set CYDEV_IO_PC_PRT0_PC2, 0x40005002 +.set CYDEV_IO_PC_PRT0_PC3, 0x40005003 +.set CYDEV_IO_PC_PRT0_PC4, 0x40005004 +.set CYDEV_IO_PC_PRT0_PC5, 0x40005005 +.set CYDEV_IO_PC_PRT0_PC6, 0x40005006 +.set CYDEV_IO_PC_PRT0_PC7, 0x40005007 +.set CYDEV_IO_PC_PRT1_BASE, 0x40005008 +.set CYDEV_IO_PC_PRT1_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT1_PC0, 0x40005008 +.set CYDEV_IO_PC_PRT1_PC1, 0x40005009 +.set CYDEV_IO_PC_PRT1_PC2, 0x4000500a +.set CYDEV_IO_PC_PRT1_PC3, 0x4000500b +.set CYDEV_IO_PC_PRT1_PC4, 0x4000500c +.set CYDEV_IO_PC_PRT1_PC5, 0x4000500d +.set CYDEV_IO_PC_PRT1_PC6, 0x4000500e +.set CYDEV_IO_PC_PRT1_PC7, 0x4000500f +.set CYDEV_IO_PC_PRT2_BASE, 0x40005010 +.set CYDEV_IO_PC_PRT2_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT2_PC0, 0x40005010 +.set CYDEV_IO_PC_PRT2_PC1, 0x40005011 +.set CYDEV_IO_PC_PRT2_PC2, 0x40005012 +.set CYDEV_IO_PC_PRT2_PC3, 0x40005013 +.set CYDEV_IO_PC_PRT2_PC4, 0x40005014 +.set CYDEV_IO_PC_PRT2_PC5, 0x40005015 +.set CYDEV_IO_PC_PRT2_PC6, 0x40005016 +.set CYDEV_IO_PC_PRT2_PC7, 0x40005017 +.set CYDEV_IO_PC_PRT3_BASE, 0x40005018 +.set CYDEV_IO_PC_PRT3_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT3_PC0, 0x40005018 +.set CYDEV_IO_PC_PRT3_PC1, 0x40005019 +.set CYDEV_IO_PC_PRT3_PC2, 0x4000501a +.set CYDEV_IO_PC_PRT3_PC3, 0x4000501b +.set CYDEV_IO_PC_PRT3_PC4, 0x4000501c +.set CYDEV_IO_PC_PRT3_PC5, 0x4000501d +.set CYDEV_IO_PC_PRT3_PC6, 0x4000501e +.set CYDEV_IO_PC_PRT3_PC7, 0x4000501f +.set CYDEV_IO_PC_PRT4_BASE, 0x40005020 +.set CYDEV_IO_PC_PRT4_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT4_PC0, 0x40005020 +.set CYDEV_IO_PC_PRT4_PC1, 0x40005021 +.set CYDEV_IO_PC_PRT4_PC2, 0x40005022 +.set CYDEV_IO_PC_PRT4_PC3, 0x40005023 +.set CYDEV_IO_PC_PRT4_PC4, 0x40005024 +.set CYDEV_IO_PC_PRT4_PC5, 0x40005025 +.set CYDEV_IO_PC_PRT4_PC6, 0x40005026 +.set CYDEV_IO_PC_PRT4_PC7, 0x40005027 +.set CYDEV_IO_PC_PRT5_BASE, 0x40005028 +.set CYDEV_IO_PC_PRT5_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT5_PC0, 0x40005028 +.set CYDEV_IO_PC_PRT5_PC1, 0x40005029 +.set CYDEV_IO_PC_PRT5_PC2, 0x4000502a +.set CYDEV_IO_PC_PRT5_PC3, 0x4000502b +.set CYDEV_IO_PC_PRT5_PC4, 0x4000502c +.set CYDEV_IO_PC_PRT5_PC5, 0x4000502d +.set CYDEV_IO_PC_PRT5_PC6, 0x4000502e +.set CYDEV_IO_PC_PRT5_PC7, 0x4000502f +.set CYDEV_IO_PC_PRT6_BASE, 0x40005030 +.set CYDEV_IO_PC_PRT6_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT6_PC0, 0x40005030 +.set CYDEV_IO_PC_PRT6_PC1, 0x40005031 +.set CYDEV_IO_PC_PRT6_PC2, 0x40005032 +.set CYDEV_IO_PC_PRT6_PC3, 0x40005033 +.set CYDEV_IO_PC_PRT6_PC4, 0x40005034 +.set CYDEV_IO_PC_PRT6_PC5, 0x40005035 +.set CYDEV_IO_PC_PRT6_PC6, 0x40005036 +.set CYDEV_IO_PC_PRT6_PC7, 0x40005037 +.set CYDEV_IO_PC_PRT12_BASE, 0x40005060 +.set CYDEV_IO_PC_PRT12_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT12_PC0, 0x40005060 +.set CYDEV_IO_PC_PRT12_PC1, 0x40005061 +.set CYDEV_IO_PC_PRT12_PC2, 0x40005062 +.set CYDEV_IO_PC_PRT12_PC3, 0x40005063 +.set CYDEV_IO_PC_PRT12_PC4, 0x40005064 +.set CYDEV_IO_PC_PRT12_PC5, 0x40005065 +.set CYDEV_IO_PC_PRT12_PC6, 0x40005066 +.set CYDEV_IO_PC_PRT12_PC7, 0x40005067 +.set CYDEV_IO_PC_PRT15_BASE, 0x40005078 +.set CYDEV_IO_PC_PRT15_SIZE, 0x00000006 +.set CYDEV_IO_PC_PRT15_PC0, 0x40005078 +.set CYDEV_IO_PC_PRT15_PC1, 0x40005079 +.set CYDEV_IO_PC_PRT15_PC2, 0x4000507a +.set CYDEV_IO_PC_PRT15_PC3, 0x4000507b +.set CYDEV_IO_PC_PRT15_PC4, 0x4000507c +.set CYDEV_IO_PC_PRT15_PC5, 0x4000507d +.set CYDEV_IO_PC_PRT15_7_6_BASE, 0x4000507e +.set CYDEV_IO_PC_PRT15_7_6_SIZE, 0x00000002 +.set CYDEV_IO_PC_PRT15_7_6_PC0, 0x4000507e +.set CYDEV_IO_PC_PRT15_7_6_PC1, 0x4000507f +.set CYDEV_IO_DR_BASE, 0x40005080 +.set CYDEV_IO_DR_SIZE, 0x00000010 +.set CYDEV_IO_DR_PRT0_BASE, 0x40005080 +.set CYDEV_IO_DR_PRT0_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT0_DR_ALIAS, 0x40005080 +.set CYDEV_IO_DR_PRT1_BASE, 0x40005081 +.set CYDEV_IO_DR_PRT1_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT1_DR_ALIAS, 0x40005081 +.set CYDEV_IO_DR_PRT2_BASE, 0x40005082 +.set CYDEV_IO_DR_PRT2_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT2_DR_ALIAS, 0x40005082 +.set CYDEV_IO_DR_PRT3_BASE, 0x40005083 +.set CYDEV_IO_DR_PRT3_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT3_DR_ALIAS, 0x40005083 +.set CYDEV_IO_DR_PRT4_BASE, 0x40005084 +.set CYDEV_IO_DR_PRT4_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT4_DR_ALIAS, 0x40005084 +.set CYDEV_IO_DR_PRT5_BASE, 0x40005085 +.set CYDEV_IO_DR_PRT5_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT5_DR_ALIAS, 0x40005085 +.set CYDEV_IO_DR_PRT6_BASE, 0x40005086 +.set CYDEV_IO_DR_PRT6_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT6_DR_ALIAS, 0x40005086 +.set CYDEV_IO_DR_PRT12_BASE, 0x4000508c +.set CYDEV_IO_DR_PRT12_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT12_DR_ALIAS, 0x4000508c +.set CYDEV_IO_DR_PRT15_BASE, 0x4000508f +.set CYDEV_IO_DR_PRT15_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT15_DR_15_ALIAS, 0x4000508f +.set CYDEV_IO_PS_BASE, 0x40005090 +.set CYDEV_IO_PS_SIZE, 0x00000010 +.set CYDEV_IO_PS_PRT0_BASE, 0x40005090 +.set CYDEV_IO_PS_PRT0_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT0_PS_ALIAS, 0x40005090 +.set CYDEV_IO_PS_PRT1_BASE, 0x40005091 +.set CYDEV_IO_PS_PRT1_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT1_PS_ALIAS, 0x40005091 +.set CYDEV_IO_PS_PRT2_BASE, 0x40005092 +.set CYDEV_IO_PS_PRT2_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT2_PS_ALIAS, 0x40005092 +.set CYDEV_IO_PS_PRT3_BASE, 0x40005093 +.set CYDEV_IO_PS_PRT3_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT3_PS_ALIAS, 0x40005093 +.set CYDEV_IO_PS_PRT4_BASE, 0x40005094 +.set CYDEV_IO_PS_PRT4_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT4_PS_ALIAS, 0x40005094 +.set CYDEV_IO_PS_PRT5_BASE, 0x40005095 +.set CYDEV_IO_PS_PRT5_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT5_PS_ALIAS, 0x40005095 +.set CYDEV_IO_PS_PRT6_BASE, 0x40005096 +.set CYDEV_IO_PS_PRT6_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT6_PS_ALIAS, 0x40005096 +.set CYDEV_IO_PS_PRT12_BASE, 0x4000509c +.set CYDEV_IO_PS_PRT12_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT12_PS_ALIAS, 0x4000509c +.set CYDEV_IO_PS_PRT15_BASE, 0x4000509f +.set CYDEV_IO_PS_PRT15_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT15_PS15_ALIAS, 0x4000509f +.set CYDEV_IO_PRT_BASE, 0x40005100 +.set CYDEV_IO_PRT_SIZE, 0x00000100 +.set CYDEV_IO_PRT_PRT0_BASE, 0x40005100 +.set CYDEV_IO_PRT_PRT0_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT0_DR, 0x40005100 +.set CYDEV_IO_PRT_PRT0_PS, 0x40005101 +.set CYDEV_IO_PRT_PRT0_DM0, 0x40005102 +.set CYDEV_IO_PRT_PRT0_DM1, 0x40005103 +.set CYDEV_IO_PRT_PRT0_DM2, 0x40005104 +.set CYDEV_IO_PRT_PRT0_SLW, 0x40005105 +.set CYDEV_IO_PRT_PRT0_BYP, 0x40005106 +.set CYDEV_IO_PRT_PRT0_BIE, 0x40005107 +.set CYDEV_IO_PRT_PRT0_INP_DIS, 0x40005108 +.set CYDEV_IO_PRT_PRT0_CTL, 0x40005109 +.set CYDEV_IO_PRT_PRT0_PRT, 0x4000510a +.set CYDEV_IO_PRT_PRT0_BIT_MASK, 0x4000510b +.set CYDEV_IO_PRT_PRT0_AMUX, 0x4000510c +.set CYDEV_IO_PRT_PRT0_AG, 0x4000510d +.set CYDEV_IO_PRT_PRT0_LCD_COM_SEG, 0x4000510e +.set CYDEV_IO_PRT_PRT0_LCD_EN, 0x4000510f +.set CYDEV_IO_PRT_PRT1_BASE, 0x40005110 +.set CYDEV_IO_PRT_PRT1_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT1_DR, 0x40005110 +.set CYDEV_IO_PRT_PRT1_PS, 0x40005111 +.set CYDEV_IO_PRT_PRT1_DM0, 0x40005112 +.set CYDEV_IO_PRT_PRT1_DM1, 0x40005113 +.set CYDEV_IO_PRT_PRT1_DM2, 0x40005114 +.set CYDEV_IO_PRT_PRT1_SLW, 0x40005115 +.set CYDEV_IO_PRT_PRT1_BYP, 0x40005116 +.set CYDEV_IO_PRT_PRT1_BIE, 0x40005117 +.set CYDEV_IO_PRT_PRT1_INP_DIS, 0x40005118 +.set CYDEV_IO_PRT_PRT1_CTL, 0x40005119 +.set CYDEV_IO_PRT_PRT1_PRT, 0x4000511a +.set CYDEV_IO_PRT_PRT1_BIT_MASK, 0x4000511b +.set CYDEV_IO_PRT_PRT1_AMUX, 0x4000511c +.set CYDEV_IO_PRT_PRT1_AG, 0x4000511d +.set CYDEV_IO_PRT_PRT1_LCD_COM_SEG, 0x4000511e +.set CYDEV_IO_PRT_PRT1_LCD_EN, 0x4000511f +.set CYDEV_IO_PRT_PRT2_BASE, 0x40005120 +.set CYDEV_IO_PRT_PRT2_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT2_DR, 0x40005120 +.set CYDEV_IO_PRT_PRT2_PS, 0x40005121 +.set CYDEV_IO_PRT_PRT2_DM0, 0x40005122 +.set CYDEV_IO_PRT_PRT2_DM1, 0x40005123 +.set CYDEV_IO_PRT_PRT2_DM2, 0x40005124 +.set CYDEV_IO_PRT_PRT2_SLW, 0x40005125 +.set CYDEV_IO_PRT_PRT2_BYP, 0x40005126 +.set CYDEV_IO_PRT_PRT2_BIE, 0x40005127 +.set CYDEV_IO_PRT_PRT2_INP_DIS, 0x40005128 +.set CYDEV_IO_PRT_PRT2_CTL, 0x40005129 +.set CYDEV_IO_PRT_PRT2_PRT, 0x4000512a +.set CYDEV_IO_PRT_PRT2_BIT_MASK, 0x4000512b +.set CYDEV_IO_PRT_PRT2_AMUX, 0x4000512c +.set CYDEV_IO_PRT_PRT2_AG, 0x4000512d +.set CYDEV_IO_PRT_PRT2_LCD_COM_SEG, 0x4000512e +.set CYDEV_IO_PRT_PRT2_LCD_EN, 0x4000512f +.set CYDEV_IO_PRT_PRT3_BASE, 0x40005130 +.set CYDEV_IO_PRT_PRT3_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT3_DR, 0x40005130 +.set CYDEV_IO_PRT_PRT3_PS, 0x40005131 +.set CYDEV_IO_PRT_PRT3_DM0, 0x40005132 +.set CYDEV_IO_PRT_PRT3_DM1, 0x40005133 +.set CYDEV_IO_PRT_PRT3_DM2, 0x40005134 +.set CYDEV_IO_PRT_PRT3_SLW, 0x40005135 +.set CYDEV_IO_PRT_PRT3_BYP, 0x40005136 +.set CYDEV_IO_PRT_PRT3_BIE, 0x40005137 +.set CYDEV_IO_PRT_PRT3_INP_DIS, 0x40005138 +.set CYDEV_IO_PRT_PRT3_CTL, 0x40005139 +.set CYDEV_IO_PRT_PRT3_PRT, 0x4000513a +.set CYDEV_IO_PRT_PRT3_BIT_MASK, 0x4000513b +.set CYDEV_IO_PRT_PRT3_AMUX, 0x4000513c +.set CYDEV_IO_PRT_PRT3_AG, 0x4000513d +.set CYDEV_IO_PRT_PRT3_LCD_COM_SEG, 0x4000513e +.set CYDEV_IO_PRT_PRT3_LCD_EN, 0x4000513f +.set CYDEV_IO_PRT_PRT4_BASE, 0x40005140 +.set CYDEV_IO_PRT_PRT4_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT4_DR, 0x40005140 +.set CYDEV_IO_PRT_PRT4_PS, 0x40005141 +.set CYDEV_IO_PRT_PRT4_DM0, 0x40005142 +.set CYDEV_IO_PRT_PRT4_DM1, 0x40005143 +.set CYDEV_IO_PRT_PRT4_DM2, 0x40005144 +.set CYDEV_IO_PRT_PRT4_SLW, 0x40005145 +.set CYDEV_IO_PRT_PRT4_BYP, 0x40005146 +.set CYDEV_IO_PRT_PRT4_BIE, 0x40005147 +.set CYDEV_IO_PRT_PRT4_INP_DIS, 0x40005148 +.set CYDEV_IO_PRT_PRT4_CTL, 0x40005149 +.set CYDEV_IO_PRT_PRT4_PRT, 0x4000514a +.set CYDEV_IO_PRT_PRT4_BIT_MASK, 0x4000514b +.set CYDEV_IO_PRT_PRT4_AMUX, 0x4000514c +.set CYDEV_IO_PRT_PRT4_AG, 0x4000514d +.set CYDEV_IO_PRT_PRT4_LCD_COM_SEG, 0x4000514e +.set CYDEV_IO_PRT_PRT4_LCD_EN, 0x4000514f +.set CYDEV_IO_PRT_PRT5_BASE, 0x40005150 +.set CYDEV_IO_PRT_PRT5_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT5_DR, 0x40005150 +.set CYDEV_IO_PRT_PRT5_PS, 0x40005151 +.set CYDEV_IO_PRT_PRT5_DM0, 0x40005152 +.set CYDEV_IO_PRT_PRT5_DM1, 0x40005153 +.set CYDEV_IO_PRT_PRT5_DM2, 0x40005154 +.set CYDEV_IO_PRT_PRT5_SLW, 0x40005155 +.set CYDEV_IO_PRT_PRT5_BYP, 0x40005156 +.set CYDEV_IO_PRT_PRT5_BIE, 0x40005157 +.set CYDEV_IO_PRT_PRT5_INP_DIS, 0x40005158 +.set CYDEV_IO_PRT_PRT5_CTL, 0x40005159 +.set CYDEV_IO_PRT_PRT5_PRT, 0x4000515a +.set CYDEV_IO_PRT_PRT5_BIT_MASK, 0x4000515b +.set CYDEV_IO_PRT_PRT5_AMUX, 0x4000515c +.set CYDEV_IO_PRT_PRT5_AG, 0x4000515d +.set CYDEV_IO_PRT_PRT5_LCD_COM_SEG, 0x4000515e +.set CYDEV_IO_PRT_PRT5_LCD_EN, 0x4000515f +.set CYDEV_IO_PRT_PRT6_BASE, 0x40005160 +.set CYDEV_IO_PRT_PRT6_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT6_DR, 0x40005160 +.set CYDEV_IO_PRT_PRT6_PS, 0x40005161 +.set CYDEV_IO_PRT_PRT6_DM0, 0x40005162 +.set CYDEV_IO_PRT_PRT6_DM1, 0x40005163 +.set CYDEV_IO_PRT_PRT6_DM2, 0x40005164 +.set CYDEV_IO_PRT_PRT6_SLW, 0x40005165 +.set CYDEV_IO_PRT_PRT6_BYP, 0x40005166 +.set CYDEV_IO_PRT_PRT6_BIE, 0x40005167 +.set CYDEV_IO_PRT_PRT6_INP_DIS, 0x40005168 +.set CYDEV_IO_PRT_PRT6_CTL, 0x40005169 +.set CYDEV_IO_PRT_PRT6_PRT, 0x4000516a +.set CYDEV_IO_PRT_PRT6_BIT_MASK, 0x4000516b +.set CYDEV_IO_PRT_PRT6_AMUX, 0x4000516c +.set CYDEV_IO_PRT_PRT6_AG, 0x4000516d +.set CYDEV_IO_PRT_PRT6_LCD_COM_SEG, 0x4000516e +.set CYDEV_IO_PRT_PRT6_LCD_EN, 0x4000516f +.set CYDEV_IO_PRT_PRT12_BASE, 0x400051c0 +.set CYDEV_IO_PRT_PRT12_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT12_DR, 0x400051c0 +.set CYDEV_IO_PRT_PRT12_PS, 0x400051c1 +.set CYDEV_IO_PRT_PRT12_DM0, 0x400051c2 +.set CYDEV_IO_PRT_PRT12_DM1, 0x400051c3 +.set CYDEV_IO_PRT_PRT12_DM2, 0x400051c4 +.set CYDEV_IO_PRT_PRT12_SLW, 0x400051c5 +.set CYDEV_IO_PRT_PRT12_BYP, 0x400051c6 +.set CYDEV_IO_PRT_PRT12_BIE, 0x400051c7 +.set CYDEV_IO_PRT_PRT12_INP_DIS, 0x400051c8 +.set CYDEV_IO_PRT_PRT12_SIO_HYST_EN, 0x400051c9 +.set CYDEV_IO_PRT_PRT12_PRT, 0x400051ca +.set CYDEV_IO_PRT_PRT12_BIT_MASK, 0x400051cb +.set CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ, 0x400051cc +.set CYDEV_IO_PRT_PRT12_AG, 0x400051cd +.set CYDEV_IO_PRT_PRT12_SIO_CFG, 0x400051ce +.set CYDEV_IO_PRT_PRT12_SIO_DIFF, 0x400051cf +.set CYDEV_IO_PRT_PRT15_BASE, 0x400051f0 +.set CYDEV_IO_PRT_PRT15_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT15_DR, 0x400051f0 +.set CYDEV_IO_PRT_PRT15_PS, 0x400051f1 +.set CYDEV_IO_PRT_PRT15_DM0, 0x400051f2 +.set CYDEV_IO_PRT_PRT15_DM1, 0x400051f3 +.set CYDEV_IO_PRT_PRT15_DM2, 0x400051f4 +.set CYDEV_IO_PRT_PRT15_SLW, 0x400051f5 +.set CYDEV_IO_PRT_PRT15_BYP, 0x400051f6 +.set CYDEV_IO_PRT_PRT15_BIE, 0x400051f7 +.set CYDEV_IO_PRT_PRT15_INP_DIS, 0x400051f8 +.set CYDEV_IO_PRT_PRT15_CTL, 0x400051f9 +.set CYDEV_IO_PRT_PRT15_PRT, 0x400051fa +.set CYDEV_IO_PRT_PRT15_BIT_MASK, 0x400051fb +.set CYDEV_IO_PRT_PRT15_AMUX, 0x400051fc +.set CYDEV_IO_PRT_PRT15_AG, 0x400051fd +.set CYDEV_IO_PRT_PRT15_LCD_COM_SEG, 0x400051fe +.set CYDEV_IO_PRT_PRT15_LCD_EN, 0x400051ff +.set CYDEV_PRTDSI_BASE, 0x40005200 +.set CYDEV_PRTDSI_SIZE, 0x0000007f +.set CYDEV_PRTDSI_PRT0_BASE, 0x40005200 +.set CYDEV_PRTDSI_PRT0_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT0_OUT_SEL0, 0x40005200 +.set CYDEV_PRTDSI_PRT0_OUT_SEL1, 0x40005201 +.set CYDEV_PRTDSI_PRT0_OE_SEL0, 0x40005202 +.set CYDEV_PRTDSI_PRT0_OE_SEL1, 0x40005203 +.set CYDEV_PRTDSI_PRT0_DBL_SYNC_IN, 0x40005204 +.set CYDEV_PRTDSI_PRT0_SYNC_OUT, 0x40005205 +.set CYDEV_PRTDSI_PRT0_CAPS_SEL, 0x40005206 +.set CYDEV_PRTDSI_PRT1_BASE, 0x40005208 +.set CYDEV_PRTDSI_PRT1_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT1_OUT_SEL0, 0x40005208 +.set CYDEV_PRTDSI_PRT1_OUT_SEL1, 0x40005209 +.set CYDEV_PRTDSI_PRT1_OE_SEL0, 0x4000520a +.set CYDEV_PRTDSI_PRT1_OE_SEL1, 0x4000520b +.set CYDEV_PRTDSI_PRT1_DBL_SYNC_IN, 0x4000520c +.set CYDEV_PRTDSI_PRT1_SYNC_OUT, 0x4000520d +.set CYDEV_PRTDSI_PRT1_CAPS_SEL, 0x4000520e +.set CYDEV_PRTDSI_PRT2_BASE, 0x40005210 +.set CYDEV_PRTDSI_PRT2_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT2_OUT_SEL0, 0x40005210 +.set CYDEV_PRTDSI_PRT2_OUT_SEL1, 0x40005211 +.set CYDEV_PRTDSI_PRT2_OE_SEL0, 0x40005212 +.set CYDEV_PRTDSI_PRT2_OE_SEL1, 0x40005213 +.set CYDEV_PRTDSI_PRT2_DBL_SYNC_IN, 0x40005214 +.set CYDEV_PRTDSI_PRT2_SYNC_OUT, 0x40005215 +.set CYDEV_PRTDSI_PRT2_CAPS_SEL, 0x40005216 +.set CYDEV_PRTDSI_PRT3_BASE, 0x40005218 +.set CYDEV_PRTDSI_PRT3_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT3_OUT_SEL0, 0x40005218 +.set CYDEV_PRTDSI_PRT3_OUT_SEL1, 0x40005219 +.set CYDEV_PRTDSI_PRT3_OE_SEL0, 0x4000521a +.set CYDEV_PRTDSI_PRT3_OE_SEL1, 0x4000521b +.set CYDEV_PRTDSI_PRT3_DBL_SYNC_IN, 0x4000521c +.set CYDEV_PRTDSI_PRT3_SYNC_OUT, 0x4000521d +.set CYDEV_PRTDSI_PRT3_CAPS_SEL, 0x4000521e +.set CYDEV_PRTDSI_PRT4_BASE, 0x40005220 +.set CYDEV_PRTDSI_PRT4_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT4_OUT_SEL0, 0x40005220 +.set CYDEV_PRTDSI_PRT4_OUT_SEL1, 0x40005221 +.set CYDEV_PRTDSI_PRT4_OE_SEL0, 0x40005222 +.set CYDEV_PRTDSI_PRT4_OE_SEL1, 0x40005223 +.set CYDEV_PRTDSI_PRT4_DBL_SYNC_IN, 0x40005224 +.set CYDEV_PRTDSI_PRT4_SYNC_OUT, 0x40005225 +.set CYDEV_PRTDSI_PRT4_CAPS_SEL, 0x40005226 +.set CYDEV_PRTDSI_PRT5_BASE, 0x40005228 +.set CYDEV_PRTDSI_PRT5_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT5_OUT_SEL0, 0x40005228 +.set CYDEV_PRTDSI_PRT5_OUT_SEL1, 0x40005229 +.set CYDEV_PRTDSI_PRT5_OE_SEL0, 0x4000522a +.set CYDEV_PRTDSI_PRT5_OE_SEL1, 0x4000522b +.set CYDEV_PRTDSI_PRT5_DBL_SYNC_IN, 0x4000522c +.set CYDEV_PRTDSI_PRT5_SYNC_OUT, 0x4000522d +.set CYDEV_PRTDSI_PRT5_CAPS_SEL, 0x4000522e +.set CYDEV_PRTDSI_PRT6_BASE, 0x40005230 +.set CYDEV_PRTDSI_PRT6_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT6_OUT_SEL0, 0x40005230 +.set CYDEV_PRTDSI_PRT6_OUT_SEL1, 0x40005231 +.set CYDEV_PRTDSI_PRT6_OE_SEL0, 0x40005232 +.set CYDEV_PRTDSI_PRT6_OE_SEL1, 0x40005233 +.set CYDEV_PRTDSI_PRT6_DBL_SYNC_IN, 0x40005234 +.set CYDEV_PRTDSI_PRT6_SYNC_OUT, 0x40005235 +.set CYDEV_PRTDSI_PRT6_CAPS_SEL, 0x40005236 +.set CYDEV_PRTDSI_PRT12_BASE, 0x40005260 +.set CYDEV_PRTDSI_PRT12_SIZE, 0x00000006 +.set CYDEV_PRTDSI_PRT12_OUT_SEL0, 0x40005260 +.set CYDEV_PRTDSI_PRT12_OUT_SEL1, 0x40005261 +.set CYDEV_PRTDSI_PRT12_OE_SEL0, 0x40005262 +.set CYDEV_PRTDSI_PRT12_OE_SEL1, 0x40005263 +.set CYDEV_PRTDSI_PRT12_DBL_SYNC_IN, 0x40005264 +.set CYDEV_PRTDSI_PRT12_SYNC_OUT, 0x40005265 +.set CYDEV_PRTDSI_PRT15_BASE, 0x40005278 +.set CYDEV_PRTDSI_PRT15_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT15_OUT_SEL0, 0x40005278 +.set CYDEV_PRTDSI_PRT15_OUT_SEL1, 0x40005279 +.set CYDEV_PRTDSI_PRT15_OE_SEL0, 0x4000527a +.set CYDEV_PRTDSI_PRT15_OE_SEL1, 0x4000527b +.set CYDEV_PRTDSI_PRT15_DBL_SYNC_IN, 0x4000527c +.set CYDEV_PRTDSI_PRT15_SYNC_OUT, 0x4000527d +.set CYDEV_PRTDSI_PRT15_CAPS_SEL, 0x4000527e +.set CYDEV_EMIF_BASE, 0x40005400 +.set CYDEV_EMIF_SIZE, 0x00000007 +.set CYDEV_EMIF_NO_UDB, 0x40005400 +.set CYDEV_EMIF_RP_WAIT_STATES, 0x40005401 +.set CYDEV_EMIF_MEM_DWN, 0x40005402 +.set CYDEV_EMIF_MEMCLK_DIV, 0x40005403 +.set CYDEV_EMIF_CLOCK_EN, 0x40005404 +.set CYDEV_EMIF_EM_TYPE, 0x40005405 +.set CYDEV_EMIF_WP_WAIT_STATES, 0x40005406 +.set CYDEV_ANAIF_BASE, 0x40005800 +.set CYDEV_ANAIF_SIZE, 0x000003a9 +.set CYDEV_ANAIF_CFG_BASE, 0x40005800 +.set CYDEV_ANAIF_CFG_SIZE, 0x0000010f +.set CYDEV_ANAIF_CFG_SC0_BASE, 0x40005800 +.set CYDEV_ANAIF_CFG_SC0_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_SC0_CR0, 0x40005800 +.set CYDEV_ANAIF_CFG_SC0_CR1, 0x40005801 +.set CYDEV_ANAIF_CFG_SC0_CR2, 0x40005802 +.set CYDEV_ANAIF_CFG_SC1_BASE, 0x40005804 +.set CYDEV_ANAIF_CFG_SC1_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_SC1_CR0, 0x40005804 +.set CYDEV_ANAIF_CFG_SC1_CR1, 0x40005805 +.set CYDEV_ANAIF_CFG_SC1_CR2, 0x40005806 +.set CYDEV_ANAIF_CFG_SC2_BASE, 0x40005808 +.set CYDEV_ANAIF_CFG_SC2_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_SC2_CR0, 0x40005808 +.set CYDEV_ANAIF_CFG_SC2_CR1, 0x40005809 +.set CYDEV_ANAIF_CFG_SC2_CR2, 0x4000580a +.set CYDEV_ANAIF_CFG_SC3_BASE, 0x4000580c +.set CYDEV_ANAIF_CFG_SC3_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_SC3_CR0, 0x4000580c +.set CYDEV_ANAIF_CFG_SC3_CR1, 0x4000580d +.set CYDEV_ANAIF_CFG_SC3_CR2, 0x4000580e +.set CYDEV_ANAIF_CFG_DAC0_BASE, 0x40005820 +.set CYDEV_ANAIF_CFG_DAC0_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_DAC0_CR0, 0x40005820 +.set CYDEV_ANAIF_CFG_DAC0_CR1, 0x40005821 +.set CYDEV_ANAIF_CFG_DAC0_TST, 0x40005822 +.set CYDEV_ANAIF_CFG_DAC1_BASE, 0x40005824 +.set CYDEV_ANAIF_CFG_DAC1_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_DAC1_CR0, 0x40005824 +.set CYDEV_ANAIF_CFG_DAC1_CR1, 0x40005825 +.set CYDEV_ANAIF_CFG_DAC1_TST, 0x40005826 +.set CYDEV_ANAIF_CFG_DAC2_BASE, 0x40005828 +.set CYDEV_ANAIF_CFG_DAC2_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_DAC2_CR0, 0x40005828 +.set CYDEV_ANAIF_CFG_DAC2_CR1, 0x40005829 +.set CYDEV_ANAIF_CFG_DAC2_TST, 0x4000582a +.set CYDEV_ANAIF_CFG_DAC3_BASE, 0x4000582c +.set CYDEV_ANAIF_CFG_DAC3_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_DAC3_CR0, 0x4000582c +.set CYDEV_ANAIF_CFG_DAC3_CR1, 0x4000582d +.set CYDEV_ANAIF_CFG_DAC3_TST, 0x4000582e +.set CYDEV_ANAIF_CFG_CMP0_BASE, 0x40005840 +.set CYDEV_ANAIF_CFG_CMP0_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_CMP0_CR, 0x40005840 +.set CYDEV_ANAIF_CFG_CMP1_BASE, 0x40005841 +.set CYDEV_ANAIF_CFG_CMP1_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_CMP1_CR, 0x40005841 +.set CYDEV_ANAIF_CFG_CMP2_BASE, 0x40005842 +.set CYDEV_ANAIF_CFG_CMP2_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_CMP2_CR, 0x40005842 +.set CYDEV_ANAIF_CFG_CMP3_BASE, 0x40005843 +.set CYDEV_ANAIF_CFG_CMP3_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_CMP3_CR, 0x40005843 +.set CYDEV_ANAIF_CFG_LUT0_BASE, 0x40005848 +.set CYDEV_ANAIF_CFG_LUT0_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LUT0_CR, 0x40005848 +.set CYDEV_ANAIF_CFG_LUT0_MX, 0x40005849 +.set CYDEV_ANAIF_CFG_LUT1_BASE, 0x4000584a +.set CYDEV_ANAIF_CFG_LUT1_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LUT1_CR, 0x4000584a +.set CYDEV_ANAIF_CFG_LUT1_MX, 0x4000584b +.set CYDEV_ANAIF_CFG_LUT2_BASE, 0x4000584c +.set CYDEV_ANAIF_CFG_LUT2_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LUT2_CR, 0x4000584c +.set CYDEV_ANAIF_CFG_LUT2_MX, 0x4000584d +.set CYDEV_ANAIF_CFG_LUT3_BASE, 0x4000584e +.set CYDEV_ANAIF_CFG_LUT3_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LUT3_CR, 0x4000584e +.set CYDEV_ANAIF_CFG_LUT3_MX, 0x4000584f +.set CYDEV_ANAIF_CFG_OPAMP0_BASE, 0x40005858 +.set CYDEV_ANAIF_CFG_OPAMP0_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_OPAMP0_CR, 0x40005858 +.set CYDEV_ANAIF_CFG_OPAMP0_RSVD, 0x40005859 +.set CYDEV_ANAIF_CFG_OPAMP1_BASE, 0x4000585a +.set CYDEV_ANAIF_CFG_OPAMP1_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_OPAMP1_CR, 0x4000585a +.set CYDEV_ANAIF_CFG_OPAMP1_RSVD, 0x4000585b +.set CYDEV_ANAIF_CFG_OPAMP2_BASE, 0x4000585c +.set CYDEV_ANAIF_CFG_OPAMP2_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_OPAMP2_CR, 0x4000585c +.set CYDEV_ANAIF_CFG_OPAMP2_RSVD, 0x4000585d +.set CYDEV_ANAIF_CFG_OPAMP3_BASE, 0x4000585e +.set CYDEV_ANAIF_CFG_OPAMP3_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_OPAMP3_CR, 0x4000585e +.set CYDEV_ANAIF_CFG_OPAMP3_RSVD, 0x4000585f +.set CYDEV_ANAIF_CFG_LCDDAC_BASE, 0x40005868 +.set CYDEV_ANAIF_CFG_LCDDAC_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LCDDAC_CR0, 0x40005868 +.set CYDEV_ANAIF_CFG_LCDDAC_CR1, 0x40005869 +.set CYDEV_ANAIF_CFG_LCDDRV_BASE, 0x4000586a +.set CYDEV_ANAIF_CFG_LCDDRV_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_LCDDRV_CR, 0x4000586a +.set CYDEV_ANAIF_CFG_LCDTMR_BASE, 0x4000586b +.set CYDEV_ANAIF_CFG_LCDTMR_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_LCDTMR_CFG, 0x4000586b +.set CYDEV_ANAIF_CFG_BG_BASE, 0x4000586c +.set CYDEV_ANAIF_CFG_BG_SIZE, 0x00000004 +.set CYDEV_ANAIF_CFG_BG_CR0, 0x4000586c +.set CYDEV_ANAIF_CFG_BG_RSVD, 0x4000586d +.set CYDEV_ANAIF_CFG_BG_DFT0, 0x4000586e +.set CYDEV_ANAIF_CFG_BG_DFT1, 0x4000586f +.set CYDEV_ANAIF_CFG_CAPSL_BASE, 0x40005870 +.set CYDEV_ANAIF_CFG_CAPSL_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_CAPSL_CFG0, 0x40005870 +.set CYDEV_ANAIF_CFG_CAPSL_CFG1, 0x40005871 +.set CYDEV_ANAIF_CFG_CAPSR_BASE, 0x40005872 +.set CYDEV_ANAIF_CFG_CAPSR_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_CAPSR_CFG0, 0x40005872 +.set CYDEV_ANAIF_CFG_CAPSR_CFG1, 0x40005873 +.set CYDEV_ANAIF_CFG_PUMP_BASE, 0x40005876 +.set CYDEV_ANAIF_CFG_PUMP_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_PUMP_CR0, 0x40005876 +.set CYDEV_ANAIF_CFG_PUMP_CR1, 0x40005877 +.set CYDEV_ANAIF_CFG_LPF0_BASE, 0x40005878 +.set CYDEV_ANAIF_CFG_LPF0_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LPF0_CR0, 0x40005878 +.set CYDEV_ANAIF_CFG_LPF0_RSVD, 0x40005879 +.set CYDEV_ANAIF_CFG_LPF1_BASE, 0x4000587a +.set CYDEV_ANAIF_CFG_LPF1_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LPF1_CR0, 0x4000587a +.set CYDEV_ANAIF_CFG_LPF1_RSVD, 0x4000587b +.set CYDEV_ANAIF_CFG_MISC_BASE, 0x4000587c +.set CYDEV_ANAIF_CFG_MISC_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_MISC_CR0, 0x4000587c +.set CYDEV_ANAIF_CFG_DSM0_BASE, 0x40005880 +.set CYDEV_ANAIF_CFG_DSM0_SIZE, 0x00000020 +.set CYDEV_ANAIF_CFG_DSM0_CR0, 0x40005880 +.set CYDEV_ANAIF_CFG_DSM0_CR1, 0x40005881 +.set CYDEV_ANAIF_CFG_DSM0_CR2, 0x40005882 +.set CYDEV_ANAIF_CFG_DSM0_CR3, 0x40005883 +.set CYDEV_ANAIF_CFG_DSM0_CR4, 0x40005884 +.set CYDEV_ANAIF_CFG_DSM0_CR5, 0x40005885 +.set CYDEV_ANAIF_CFG_DSM0_CR6, 0x40005886 +.set CYDEV_ANAIF_CFG_DSM0_CR7, 0x40005887 +.set CYDEV_ANAIF_CFG_DSM0_CR8, 0x40005888 +.set CYDEV_ANAIF_CFG_DSM0_CR9, 0x40005889 +.set CYDEV_ANAIF_CFG_DSM0_CR10, 0x4000588a +.set CYDEV_ANAIF_CFG_DSM0_CR11, 0x4000588b +.set CYDEV_ANAIF_CFG_DSM0_CR12, 0x4000588c +.set CYDEV_ANAIF_CFG_DSM0_CR13, 0x4000588d +.set CYDEV_ANAIF_CFG_DSM0_CR14, 0x4000588e +.set CYDEV_ANAIF_CFG_DSM0_CR15, 0x4000588f +.set CYDEV_ANAIF_CFG_DSM0_CR16, 0x40005890 +.set CYDEV_ANAIF_CFG_DSM0_CR17, 0x40005891 +.set CYDEV_ANAIF_CFG_DSM0_REF0, 0x40005892 +.set CYDEV_ANAIF_CFG_DSM0_REF1, 0x40005893 +.set CYDEV_ANAIF_CFG_DSM0_REF2, 0x40005894 +.set CYDEV_ANAIF_CFG_DSM0_REF3, 0x40005895 +.set CYDEV_ANAIF_CFG_DSM0_DEM0, 0x40005896 +.set CYDEV_ANAIF_CFG_DSM0_DEM1, 0x40005897 +.set CYDEV_ANAIF_CFG_DSM0_TST0, 0x40005898 +.set CYDEV_ANAIF_CFG_DSM0_TST1, 0x40005899 +.set CYDEV_ANAIF_CFG_DSM0_BUF0, 0x4000589a +.set CYDEV_ANAIF_CFG_DSM0_BUF1, 0x4000589b +.set CYDEV_ANAIF_CFG_DSM0_BUF2, 0x4000589c +.set CYDEV_ANAIF_CFG_DSM0_BUF3, 0x4000589d +.set CYDEV_ANAIF_CFG_DSM0_MISC, 0x4000589e +.set CYDEV_ANAIF_CFG_DSM0_RSVD1, 0x4000589f +.set CYDEV_ANAIF_CFG_SAR0_BASE, 0x40005900 +.set CYDEV_ANAIF_CFG_SAR0_SIZE, 0x00000007 +.set CYDEV_ANAIF_CFG_SAR0_CSR0, 0x40005900 +.set CYDEV_ANAIF_CFG_SAR0_CSR1, 0x40005901 +.set CYDEV_ANAIF_CFG_SAR0_CSR2, 0x40005902 +.set CYDEV_ANAIF_CFG_SAR0_CSR3, 0x40005903 +.set CYDEV_ANAIF_CFG_SAR0_CSR4, 0x40005904 +.set CYDEV_ANAIF_CFG_SAR0_CSR5, 0x40005905 +.set CYDEV_ANAIF_CFG_SAR0_CSR6, 0x40005906 +.set CYDEV_ANAIF_CFG_SAR1_BASE, 0x40005908 +.set CYDEV_ANAIF_CFG_SAR1_SIZE, 0x00000007 +.set CYDEV_ANAIF_CFG_SAR1_CSR0, 0x40005908 +.set CYDEV_ANAIF_CFG_SAR1_CSR1, 0x40005909 +.set CYDEV_ANAIF_CFG_SAR1_CSR2, 0x4000590a +.set CYDEV_ANAIF_CFG_SAR1_CSR3, 0x4000590b +.set CYDEV_ANAIF_CFG_SAR1_CSR4, 0x4000590c +.set CYDEV_ANAIF_CFG_SAR1_CSR5, 0x4000590d +.set CYDEV_ANAIF_CFG_SAR1_CSR6, 0x4000590e +.set CYDEV_ANAIF_RT_BASE, 0x40005a00 +.set CYDEV_ANAIF_RT_SIZE, 0x00000162 +.set CYDEV_ANAIF_RT_SC0_BASE, 0x40005a00 +.set CYDEV_ANAIF_RT_SC0_SIZE, 0x0000000d +.set CYDEV_ANAIF_RT_SC0_SW0, 0x40005a00 +.set CYDEV_ANAIF_RT_SC0_SW2, 0x40005a02 +.set CYDEV_ANAIF_RT_SC0_SW3, 0x40005a03 +.set CYDEV_ANAIF_RT_SC0_SW4, 0x40005a04 +.set CYDEV_ANAIF_RT_SC0_SW6, 0x40005a06 +.set CYDEV_ANAIF_RT_SC0_SW7, 0x40005a07 +.set CYDEV_ANAIF_RT_SC0_SW8, 0x40005a08 +.set CYDEV_ANAIF_RT_SC0_SW10, 0x40005a0a +.set CYDEV_ANAIF_RT_SC0_CLK, 0x40005a0b +.set CYDEV_ANAIF_RT_SC0_BST, 0x40005a0c +.set CYDEV_ANAIF_RT_SC1_BASE, 0x40005a10 +.set CYDEV_ANAIF_RT_SC1_SIZE, 0x0000000d +.set CYDEV_ANAIF_RT_SC1_SW0, 0x40005a10 +.set CYDEV_ANAIF_RT_SC1_SW2, 0x40005a12 +.set CYDEV_ANAIF_RT_SC1_SW3, 0x40005a13 +.set CYDEV_ANAIF_RT_SC1_SW4, 0x40005a14 +.set CYDEV_ANAIF_RT_SC1_SW6, 0x40005a16 +.set CYDEV_ANAIF_RT_SC1_SW7, 0x40005a17 +.set CYDEV_ANAIF_RT_SC1_SW8, 0x40005a18 +.set CYDEV_ANAIF_RT_SC1_SW10, 0x40005a1a +.set CYDEV_ANAIF_RT_SC1_CLK, 0x40005a1b +.set CYDEV_ANAIF_RT_SC1_BST, 0x40005a1c +.set CYDEV_ANAIF_RT_SC2_BASE, 0x40005a20 +.set CYDEV_ANAIF_RT_SC2_SIZE, 0x0000000d +.set CYDEV_ANAIF_RT_SC2_SW0, 0x40005a20 +.set CYDEV_ANAIF_RT_SC2_SW2, 0x40005a22 +.set CYDEV_ANAIF_RT_SC2_SW3, 0x40005a23 +.set CYDEV_ANAIF_RT_SC2_SW4, 0x40005a24 +.set CYDEV_ANAIF_RT_SC2_SW6, 0x40005a26 +.set CYDEV_ANAIF_RT_SC2_SW7, 0x40005a27 +.set CYDEV_ANAIF_RT_SC2_SW8, 0x40005a28 +.set CYDEV_ANAIF_RT_SC2_SW10, 0x40005a2a +.set CYDEV_ANAIF_RT_SC2_CLK, 0x40005a2b +.set CYDEV_ANAIF_RT_SC2_BST, 0x40005a2c +.set CYDEV_ANAIF_RT_SC3_BASE, 0x40005a30 +.set CYDEV_ANAIF_RT_SC3_SIZE, 0x0000000d +.set CYDEV_ANAIF_RT_SC3_SW0, 0x40005a30 +.set CYDEV_ANAIF_RT_SC3_SW2, 0x40005a32 +.set CYDEV_ANAIF_RT_SC3_SW3, 0x40005a33 +.set CYDEV_ANAIF_RT_SC3_SW4, 0x40005a34 +.set CYDEV_ANAIF_RT_SC3_SW6, 0x40005a36 +.set CYDEV_ANAIF_RT_SC3_SW7, 0x40005a37 +.set CYDEV_ANAIF_RT_SC3_SW8, 0x40005a38 +.set CYDEV_ANAIF_RT_SC3_SW10, 0x40005a3a +.set CYDEV_ANAIF_RT_SC3_CLK, 0x40005a3b +.set CYDEV_ANAIF_RT_SC3_BST, 0x40005a3c +.set CYDEV_ANAIF_RT_DAC0_BASE, 0x40005a80 +.set CYDEV_ANAIF_RT_DAC0_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_DAC0_SW0, 0x40005a80 +.set CYDEV_ANAIF_RT_DAC0_SW2, 0x40005a82 +.set CYDEV_ANAIF_RT_DAC0_SW3, 0x40005a83 +.set CYDEV_ANAIF_RT_DAC0_SW4, 0x40005a84 +.set CYDEV_ANAIF_RT_DAC0_STROBE, 0x40005a87 +.set CYDEV_ANAIF_RT_DAC1_BASE, 0x40005a88 +.set CYDEV_ANAIF_RT_DAC1_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_DAC1_SW0, 0x40005a88 +.set CYDEV_ANAIF_RT_DAC1_SW2, 0x40005a8a +.set CYDEV_ANAIF_RT_DAC1_SW3, 0x40005a8b +.set CYDEV_ANAIF_RT_DAC1_SW4, 0x40005a8c +.set CYDEV_ANAIF_RT_DAC1_STROBE, 0x40005a8f +.set CYDEV_ANAIF_RT_DAC2_BASE, 0x40005a90 +.set CYDEV_ANAIF_RT_DAC2_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_DAC2_SW0, 0x40005a90 +.set CYDEV_ANAIF_RT_DAC2_SW2, 0x40005a92 +.set CYDEV_ANAIF_RT_DAC2_SW3, 0x40005a93 +.set CYDEV_ANAIF_RT_DAC2_SW4, 0x40005a94 +.set CYDEV_ANAIF_RT_DAC2_STROBE, 0x40005a97 +.set CYDEV_ANAIF_RT_DAC3_BASE, 0x40005a98 +.set CYDEV_ANAIF_RT_DAC3_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_DAC3_SW0, 0x40005a98 +.set CYDEV_ANAIF_RT_DAC3_SW2, 0x40005a9a +.set CYDEV_ANAIF_RT_DAC3_SW3, 0x40005a9b +.set CYDEV_ANAIF_RT_DAC3_SW4, 0x40005a9c +.set CYDEV_ANAIF_RT_DAC3_STROBE, 0x40005a9f +.set CYDEV_ANAIF_RT_CMP0_BASE, 0x40005ac0 +.set CYDEV_ANAIF_RT_CMP0_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_CMP0_SW0, 0x40005ac0 +.set CYDEV_ANAIF_RT_CMP0_SW2, 0x40005ac2 +.set CYDEV_ANAIF_RT_CMP0_SW3, 0x40005ac3 +.set CYDEV_ANAIF_RT_CMP0_SW4, 0x40005ac4 +.set CYDEV_ANAIF_RT_CMP0_SW6, 0x40005ac6 +.set CYDEV_ANAIF_RT_CMP0_CLK, 0x40005ac7 +.set CYDEV_ANAIF_RT_CMP1_BASE, 0x40005ac8 +.set CYDEV_ANAIF_RT_CMP1_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_CMP1_SW0, 0x40005ac8 +.set CYDEV_ANAIF_RT_CMP1_SW2, 0x40005aca +.set CYDEV_ANAIF_RT_CMP1_SW3, 0x40005acb +.set CYDEV_ANAIF_RT_CMP1_SW4, 0x40005acc +.set CYDEV_ANAIF_RT_CMP1_SW6, 0x40005ace +.set CYDEV_ANAIF_RT_CMP1_CLK, 0x40005acf +.set CYDEV_ANAIF_RT_CMP2_BASE, 0x40005ad0 +.set CYDEV_ANAIF_RT_CMP2_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_CMP2_SW0, 0x40005ad0 +.set CYDEV_ANAIF_RT_CMP2_SW2, 0x40005ad2 +.set CYDEV_ANAIF_RT_CMP2_SW3, 0x40005ad3 +.set CYDEV_ANAIF_RT_CMP2_SW4, 0x40005ad4 +.set CYDEV_ANAIF_RT_CMP2_SW6, 0x40005ad6 +.set CYDEV_ANAIF_RT_CMP2_CLK, 0x40005ad7 +.set CYDEV_ANAIF_RT_CMP3_BASE, 0x40005ad8 +.set CYDEV_ANAIF_RT_CMP3_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_CMP3_SW0, 0x40005ad8 +.set CYDEV_ANAIF_RT_CMP3_SW2, 0x40005ada +.set CYDEV_ANAIF_RT_CMP3_SW3, 0x40005adb +.set CYDEV_ANAIF_RT_CMP3_SW4, 0x40005adc +.set CYDEV_ANAIF_RT_CMP3_SW6, 0x40005ade +.set CYDEV_ANAIF_RT_CMP3_CLK, 0x40005adf +.set CYDEV_ANAIF_RT_DSM0_BASE, 0x40005b00 +.set CYDEV_ANAIF_RT_DSM0_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_DSM0_SW0, 0x40005b00 +.set CYDEV_ANAIF_RT_DSM0_SW2, 0x40005b02 +.set CYDEV_ANAIF_RT_DSM0_SW3, 0x40005b03 +.set CYDEV_ANAIF_RT_DSM0_SW4, 0x40005b04 +.set CYDEV_ANAIF_RT_DSM0_SW6, 0x40005b06 +.set CYDEV_ANAIF_RT_DSM0_CLK, 0x40005b07 +.set CYDEV_ANAIF_RT_SAR0_BASE, 0x40005b20 +.set CYDEV_ANAIF_RT_SAR0_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_SAR0_SW0, 0x40005b20 +.set CYDEV_ANAIF_RT_SAR0_SW2, 0x40005b22 +.set CYDEV_ANAIF_RT_SAR0_SW3, 0x40005b23 +.set CYDEV_ANAIF_RT_SAR0_SW4, 0x40005b24 +.set CYDEV_ANAIF_RT_SAR0_SW6, 0x40005b26 +.set CYDEV_ANAIF_RT_SAR0_CLK, 0x40005b27 +.set CYDEV_ANAIF_RT_SAR1_BASE, 0x40005b28 +.set CYDEV_ANAIF_RT_SAR1_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_SAR1_SW0, 0x40005b28 +.set CYDEV_ANAIF_RT_SAR1_SW2, 0x40005b2a +.set CYDEV_ANAIF_RT_SAR1_SW3, 0x40005b2b +.set CYDEV_ANAIF_RT_SAR1_SW4, 0x40005b2c +.set CYDEV_ANAIF_RT_SAR1_SW6, 0x40005b2e +.set CYDEV_ANAIF_RT_SAR1_CLK, 0x40005b2f +.set CYDEV_ANAIF_RT_OPAMP0_BASE, 0x40005b40 +.set CYDEV_ANAIF_RT_OPAMP0_SIZE, 0x00000002 +.set CYDEV_ANAIF_RT_OPAMP0_MX, 0x40005b40 +.set CYDEV_ANAIF_RT_OPAMP0_SW, 0x40005b41 +.set CYDEV_ANAIF_RT_OPAMP1_BASE, 0x40005b42 +.set CYDEV_ANAIF_RT_OPAMP1_SIZE, 0x00000002 +.set CYDEV_ANAIF_RT_OPAMP1_MX, 0x40005b42 +.set CYDEV_ANAIF_RT_OPAMP1_SW, 0x40005b43 +.set CYDEV_ANAIF_RT_OPAMP2_BASE, 0x40005b44 +.set CYDEV_ANAIF_RT_OPAMP2_SIZE, 0x00000002 +.set CYDEV_ANAIF_RT_OPAMP2_MX, 0x40005b44 +.set CYDEV_ANAIF_RT_OPAMP2_SW, 0x40005b45 +.set CYDEV_ANAIF_RT_OPAMP3_BASE, 0x40005b46 +.set CYDEV_ANAIF_RT_OPAMP3_SIZE, 0x00000002 +.set CYDEV_ANAIF_RT_OPAMP3_MX, 0x40005b46 +.set CYDEV_ANAIF_RT_OPAMP3_SW, 0x40005b47 +.set CYDEV_ANAIF_RT_LCDDAC_BASE, 0x40005b50 +.set CYDEV_ANAIF_RT_LCDDAC_SIZE, 0x00000005 +.set CYDEV_ANAIF_RT_LCDDAC_SW0, 0x40005b50 +.set CYDEV_ANAIF_RT_LCDDAC_SW1, 0x40005b51 +.set CYDEV_ANAIF_RT_LCDDAC_SW2, 0x40005b52 +.set CYDEV_ANAIF_RT_LCDDAC_SW3, 0x40005b53 +.set CYDEV_ANAIF_RT_LCDDAC_SW4, 0x40005b54 +.set CYDEV_ANAIF_RT_SC_BASE, 0x40005b56 +.set CYDEV_ANAIF_RT_SC_SIZE, 0x00000001 +.set CYDEV_ANAIF_RT_SC_MISC, 0x40005b56 +.set CYDEV_ANAIF_RT_BUS_BASE, 0x40005b58 +.set CYDEV_ANAIF_RT_BUS_SIZE, 0x00000004 +.set CYDEV_ANAIF_RT_BUS_SW0, 0x40005b58 +.set CYDEV_ANAIF_RT_BUS_SW2, 0x40005b5a +.set CYDEV_ANAIF_RT_BUS_SW3, 0x40005b5b +.set CYDEV_ANAIF_RT_DFT_BASE, 0x40005b5c +.set CYDEV_ANAIF_RT_DFT_SIZE, 0x00000006 +.set CYDEV_ANAIF_RT_DFT_CR0, 0x40005b5c +.set CYDEV_ANAIF_RT_DFT_CR1, 0x40005b5d +.set CYDEV_ANAIF_RT_DFT_CR2, 0x40005b5e +.set CYDEV_ANAIF_RT_DFT_CR3, 0x40005b5f +.set CYDEV_ANAIF_RT_DFT_CR4, 0x40005b60 +.set CYDEV_ANAIF_RT_DFT_CR5, 0x40005b61 +.set CYDEV_ANAIF_WRK_BASE, 0x40005b80 +.set CYDEV_ANAIF_WRK_SIZE, 0x00000029 +.set CYDEV_ANAIF_WRK_DAC0_BASE, 0x40005b80 +.set CYDEV_ANAIF_WRK_DAC0_SIZE, 0x00000001 +.set CYDEV_ANAIF_WRK_DAC0_D, 0x40005b80 +.set CYDEV_ANAIF_WRK_DAC1_BASE, 0x40005b81 +.set CYDEV_ANAIF_WRK_DAC1_SIZE, 0x00000001 +.set CYDEV_ANAIF_WRK_DAC1_D, 0x40005b81 +.set CYDEV_ANAIF_WRK_DAC2_BASE, 0x40005b82 +.set CYDEV_ANAIF_WRK_DAC2_SIZE, 0x00000001 +.set CYDEV_ANAIF_WRK_DAC2_D, 0x40005b82 +.set CYDEV_ANAIF_WRK_DAC3_BASE, 0x40005b83 +.set CYDEV_ANAIF_WRK_DAC3_SIZE, 0x00000001 +.set CYDEV_ANAIF_WRK_DAC3_D, 0x40005b83 +.set CYDEV_ANAIF_WRK_DSM0_BASE, 0x40005b88 +.set CYDEV_ANAIF_WRK_DSM0_SIZE, 0x00000002 +.set CYDEV_ANAIF_WRK_DSM0_OUT0, 0x40005b88 +.set CYDEV_ANAIF_WRK_DSM0_OUT1, 0x40005b89 +.set CYDEV_ANAIF_WRK_LUT_BASE, 0x40005b90 +.set CYDEV_ANAIF_WRK_LUT_SIZE, 0x00000005 +.set CYDEV_ANAIF_WRK_LUT_SR, 0x40005b90 +.set CYDEV_ANAIF_WRK_LUT_WRK1, 0x40005b91 +.set CYDEV_ANAIF_WRK_LUT_MSK, 0x40005b92 +.set CYDEV_ANAIF_WRK_LUT_CLK, 0x40005b93 +.set CYDEV_ANAIF_WRK_LUT_CPTR, 0x40005b94 +.set CYDEV_ANAIF_WRK_CMP_BASE, 0x40005b96 +.set CYDEV_ANAIF_WRK_CMP_SIZE, 0x00000002 +.set CYDEV_ANAIF_WRK_CMP_WRK, 0x40005b96 +.set CYDEV_ANAIF_WRK_CMP_TST, 0x40005b97 +.set CYDEV_ANAIF_WRK_SC_BASE, 0x40005b98 +.set CYDEV_ANAIF_WRK_SC_SIZE, 0x00000005 +.set CYDEV_ANAIF_WRK_SC_SR, 0x40005b98 +.set CYDEV_ANAIF_WRK_SC_WRK1, 0x40005b99 +.set CYDEV_ANAIF_WRK_SC_MSK, 0x40005b9a +.set CYDEV_ANAIF_WRK_SC_CMPINV, 0x40005b9b +.set CYDEV_ANAIF_WRK_SC_CPTR, 0x40005b9c +.set CYDEV_ANAIF_WRK_SAR0_BASE, 0x40005ba0 +.set CYDEV_ANAIF_WRK_SAR0_SIZE, 0x00000002 +.set CYDEV_ANAIF_WRK_SAR0_WRK0, 0x40005ba0 +.set CYDEV_ANAIF_WRK_SAR0_WRK1, 0x40005ba1 +.set CYDEV_ANAIF_WRK_SAR1_BASE, 0x40005ba2 +.set CYDEV_ANAIF_WRK_SAR1_SIZE, 0x00000002 +.set CYDEV_ANAIF_WRK_SAR1_WRK0, 0x40005ba2 +.set CYDEV_ANAIF_WRK_SAR1_WRK1, 0x40005ba3 +.set CYDEV_ANAIF_WRK_SARS_BASE, 0x40005ba8 +.set CYDEV_ANAIF_WRK_SARS_SIZE, 0x00000001 +.set CYDEV_ANAIF_WRK_SARS_SOF, 0x40005ba8 +.set CYDEV_USB_BASE, 0x40006000 +.set CYDEV_USB_SIZE, 0x00000300 +.set CYDEV_USB_EP0_DR0, 0x40006000 +.set CYDEV_USB_EP0_DR1, 0x40006001 +.set CYDEV_USB_EP0_DR2, 0x40006002 +.set CYDEV_USB_EP0_DR3, 0x40006003 +.set CYDEV_USB_EP0_DR4, 0x40006004 +.set CYDEV_USB_EP0_DR5, 0x40006005 +.set CYDEV_USB_EP0_DR6, 0x40006006 +.set CYDEV_USB_EP0_DR7, 0x40006007 +.set CYDEV_USB_CR0, 0x40006008 +.set CYDEV_USB_CR1, 0x40006009 +.set CYDEV_USB_SIE_EP_INT_EN, 0x4000600a +.set CYDEV_USB_SIE_EP_INT_SR, 0x4000600b +.set CYDEV_USB_SIE_EP1_BASE, 0x4000600c +.set CYDEV_USB_SIE_EP1_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP1_CNT0, 0x4000600c +.set CYDEV_USB_SIE_EP1_CNT1, 0x4000600d +.set CYDEV_USB_SIE_EP1_CR0, 0x4000600e +.set CYDEV_USB_USBIO_CR0, 0x40006010 +.set CYDEV_USB_USBIO_CR1, 0x40006012 +.set CYDEV_USB_DYN_RECONFIG, 0x40006014 +.set CYDEV_USB_SOF0, 0x40006018 +.set CYDEV_USB_SOF1, 0x40006019 +.set CYDEV_USB_SIE_EP2_BASE, 0x4000601c +.set CYDEV_USB_SIE_EP2_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP2_CNT0, 0x4000601c +.set CYDEV_USB_SIE_EP2_CNT1, 0x4000601d +.set CYDEV_USB_SIE_EP2_CR0, 0x4000601e +.set CYDEV_USB_EP0_CR, 0x40006028 +.set CYDEV_USB_EP0_CNT, 0x40006029 +.set CYDEV_USB_SIE_EP3_BASE, 0x4000602c +.set CYDEV_USB_SIE_EP3_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP3_CNT0, 0x4000602c +.set CYDEV_USB_SIE_EP3_CNT1, 0x4000602d +.set CYDEV_USB_SIE_EP3_CR0, 0x4000602e +.set CYDEV_USB_SIE_EP4_BASE, 0x4000603c +.set CYDEV_USB_SIE_EP4_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP4_CNT0, 0x4000603c +.set CYDEV_USB_SIE_EP4_CNT1, 0x4000603d +.set CYDEV_USB_SIE_EP4_CR0, 0x4000603e +.set CYDEV_USB_SIE_EP5_BASE, 0x4000604c +.set CYDEV_USB_SIE_EP5_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP5_CNT0, 0x4000604c +.set CYDEV_USB_SIE_EP5_CNT1, 0x4000604d +.set CYDEV_USB_SIE_EP5_CR0, 0x4000604e +.set CYDEV_USB_SIE_EP6_BASE, 0x4000605c +.set CYDEV_USB_SIE_EP6_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP6_CNT0, 0x4000605c +.set CYDEV_USB_SIE_EP6_CNT1, 0x4000605d +.set CYDEV_USB_SIE_EP6_CR0, 0x4000605e +.set CYDEV_USB_SIE_EP7_BASE, 0x4000606c +.set CYDEV_USB_SIE_EP7_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP7_CNT0, 0x4000606c +.set CYDEV_USB_SIE_EP7_CNT1, 0x4000606d +.set CYDEV_USB_SIE_EP7_CR0, 0x4000606e +.set CYDEV_USB_SIE_EP8_BASE, 0x4000607c +.set CYDEV_USB_SIE_EP8_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP8_CNT0, 0x4000607c +.set CYDEV_USB_SIE_EP8_CNT1, 0x4000607d +.set CYDEV_USB_SIE_EP8_CR0, 0x4000607e +.set CYDEV_USB_ARB_EP1_BASE, 0x40006080 +.set CYDEV_USB_ARB_EP1_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP1_CFG, 0x40006080 +.set CYDEV_USB_ARB_EP1_INT_EN, 0x40006081 +.set CYDEV_USB_ARB_EP1_SR, 0x40006082 +.set CYDEV_USB_ARB_RW1_BASE, 0x40006084 +.set CYDEV_USB_ARB_RW1_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW1_WA, 0x40006084 +.set CYDEV_USB_ARB_RW1_WA_MSB, 0x40006085 +.set CYDEV_USB_ARB_RW1_RA, 0x40006086 +.set CYDEV_USB_ARB_RW1_RA_MSB, 0x40006087 +.set CYDEV_USB_ARB_RW1_DR, 0x40006088 +.set CYDEV_USB_BUF_SIZE, 0x4000608c +.set CYDEV_USB_EP_ACTIVE, 0x4000608e +.set CYDEV_USB_EP_TYPE, 0x4000608f +.set CYDEV_USB_ARB_EP2_BASE, 0x40006090 +.set CYDEV_USB_ARB_EP2_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP2_CFG, 0x40006090 +.set CYDEV_USB_ARB_EP2_INT_EN, 0x40006091 +.set CYDEV_USB_ARB_EP2_SR, 0x40006092 +.set CYDEV_USB_ARB_RW2_BASE, 0x40006094 +.set CYDEV_USB_ARB_RW2_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW2_WA, 0x40006094 +.set CYDEV_USB_ARB_RW2_WA_MSB, 0x40006095 +.set CYDEV_USB_ARB_RW2_RA, 0x40006096 +.set CYDEV_USB_ARB_RW2_RA_MSB, 0x40006097 +.set CYDEV_USB_ARB_RW2_DR, 0x40006098 +.set CYDEV_USB_ARB_CFG, 0x4000609c +.set CYDEV_USB_USB_CLK_EN, 0x4000609d +.set CYDEV_USB_ARB_INT_EN, 0x4000609e +.set CYDEV_USB_ARB_INT_SR, 0x4000609f +.set CYDEV_USB_ARB_EP3_BASE, 0x400060a0 +.set CYDEV_USB_ARB_EP3_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP3_CFG, 0x400060a0 +.set CYDEV_USB_ARB_EP3_INT_EN, 0x400060a1 +.set CYDEV_USB_ARB_EP3_SR, 0x400060a2 +.set CYDEV_USB_ARB_RW3_BASE, 0x400060a4 +.set CYDEV_USB_ARB_RW3_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW3_WA, 0x400060a4 +.set CYDEV_USB_ARB_RW3_WA_MSB, 0x400060a5 +.set CYDEV_USB_ARB_RW3_RA, 0x400060a6 +.set CYDEV_USB_ARB_RW3_RA_MSB, 0x400060a7 +.set CYDEV_USB_ARB_RW3_DR, 0x400060a8 +.set CYDEV_USB_CWA, 0x400060ac +.set CYDEV_USB_CWA_MSB, 0x400060ad +.set CYDEV_USB_ARB_EP4_BASE, 0x400060b0 +.set CYDEV_USB_ARB_EP4_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP4_CFG, 0x400060b0 +.set CYDEV_USB_ARB_EP4_INT_EN, 0x400060b1 +.set CYDEV_USB_ARB_EP4_SR, 0x400060b2 +.set CYDEV_USB_ARB_RW4_BASE, 0x400060b4 +.set CYDEV_USB_ARB_RW4_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW4_WA, 0x400060b4 +.set CYDEV_USB_ARB_RW4_WA_MSB, 0x400060b5 +.set CYDEV_USB_ARB_RW4_RA, 0x400060b6 +.set CYDEV_USB_ARB_RW4_RA_MSB, 0x400060b7 +.set CYDEV_USB_ARB_RW4_DR, 0x400060b8 +.set CYDEV_USB_DMA_THRES, 0x400060bc +.set CYDEV_USB_DMA_THRES_MSB, 0x400060bd +.set CYDEV_USB_ARB_EP5_BASE, 0x400060c0 +.set CYDEV_USB_ARB_EP5_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP5_CFG, 0x400060c0 +.set CYDEV_USB_ARB_EP5_INT_EN, 0x400060c1 +.set CYDEV_USB_ARB_EP5_SR, 0x400060c2 +.set CYDEV_USB_ARB_RW5_BASE, 0x400060c4 +.set CYDEV_USB_ARB_RW5_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW5_WA, 0x400060c4 +.set CYDEV_USB_ARB_RW5_WA_MSB, 0x400060c5 +.set CYDEV_USB_ARB_RW5_RA, 0x400060c6 +.set CYDEV_USB_ARB_RW5_RA_MSB, 0x400060c7 +.set CYDEV_USB_ARB_RW5_DR, 0x400060c8 +.set CYDEV_USB_BUS_RST_CNT, 0x400060cc +.set CYDEV_USB_ARB_EP6_BASE, 0x400060d0 +.set CYDEV_USB_ARB_EP6_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP6_CFG, 0x400060d0 +.set CYDEV_USB_ARB_EP6_INT_EN, 0x400060d1 +.set CYDEV_USB_ARB_EP6_SR, 0x400060d2 +.set CYDEV_USB_ARB_RW6_BASE, 0x400060d4 +.set CYDEV_USB_ARB_RW6_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW6_WA, 0x400060d4 +.set CYDEV_USB_ARB_RW6_WA_MSB, 0x400060d5 +.set CYDEV_USB_ARB_RW6_RA, 0x400060d6 +.set CYDEV_USB_ARB_RW6_RA_MSB, 0x400060d7 +.set CYDEV_USB_ARB_RW6_DR, 0x400060d8 +.set CYDEV_USB_ARB_EP7_BASE, 0x400060e0 +.set CYDEV_USB_ARB_EP7_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP7_CFG, 0x400060e0 +.set CYDEV_USB_ARB_EP7_INT_EN, 0x400060e1 +.set CYDEV_USB_ARB_EP7_SR, 0x400060e2 +.set CYDEV_USB_ARB_RW7_BASE, 0x400060e4 +.set CYDEV_USB_ARB_RW7_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW7_WA, 0x400060e4 +.set CYDEV_USB_ARB_RW7_WA_MSB, 0x400060e5 +.set CYDEV_USB_ARB_RW7_RA, 0x400060e6 +.set CYDEV_USB_ARB_RW7_RA_MSB, 0x400060e7 +.set CYDEV_USB_ARB_RW7_DR, 0x400060e8 +.set CYDEV_USB_ARB_EP8_BASE, 0x400060f0 +.set CYDEV_USB_ARB_EP8_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP8_CFG, 0x400060f0 +.set CYDEV_USB_ARB_EP8_INT_EN, 0x400060f1 +.set CYDEV_USB_ARB_EP8_SR, 0x400060f2 +.set CYDEV_USB_ARB_RW8_BASE, 0x400060f4 +.set CYDEV_USB_ARB_RW8_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW8_WA, 0x400060f4 +.set CYDEV_USB_ARB_RW8_WA_MSB, 0x400060f5 +.set CYDEV_USB_ARB_RW8_RA, 0x400060f6 +.set CYDEV_USB_ARB_RW8_RA_MSB, 0x400060f7 +.set CYDEV_USB_ARB_RW8_DR, 0x400060f8 +.set CYDEV_USB_MEM_BASE, 0x40006100 +.set CYDEV_USB_MEM_SIZE, 0x00000200 +.set CYDEV_USB_MEM_DATA_MBASE, 0x40006100 +.set CYDEV_USB_MEM_DATA_MSIZE, 0x00000200 +.set CYDEV_UWRK_BASE, 0x40006400 +.set CYDEV_UWRK_SIZE, 0x00000b60 +.set CYDEV_UWRK_UWRK8_BASE, 0x40006400 +.set CYDEV_UWRK_UWRK8_SIZE, 0x000003b0 +.set CYDEV_UWRK_UWRK8_B0_BASE, 0x40006400 +.set CYDEV_UWRK_UWRK8_B0_SIZE, 0x000000b0 +.set CYDEV_UWRK_UWRK8_B0_UDB00_A0, 0x40006400 +.set CYDEV_UWRK_UWRK8_B0_UDB01_A0, 0x40006401 +.set CYDEV_UWRK_UWRK8_B0_UDB02_A0, 0x40006402 +.set CYDEV_UWRK_UWRK8_B0_UDB03_A0, 0x40006403 +.set CYDEV_UWRK_UWRK8_B0_UDB04_A0, 0x40006404 +.set CYDEV_UWRK_UWRK8_B0_UDB05_A0, 0x40006405 +.set CYDEV_UWRK_UWRK8_B0_UDB06_A0, 0x40006406 +.set CYDEV_UWRK_UWRK8_B0_UDB07_A0, 0x40006407 +.set CYDEV_UWRK_UWRK8_B0_UDB08_A0, 0x40006408 +.set CYDEV_UWRK_UWRK8_B0_UDB09_A0, 0x40006409 +.set CYDEV_UWRK_UWRK8_B0_UDB10_A0, 0x4000640a +.set CYDEV_UWRK_UWRK8_B0_UDB11_A0, 0x4000640b +.set CYDEV_UWRK_UWRK8_B0_UDB12_A0, 0x4000640c +.set CYDEV_UWRK_UWRK8_B0_UDB13_A0, 0x4000640d +.set CYDEV_UWRK_UWRK8_B0_UDB14_A0, 0x4000640e +.set CYDEV_UWRK_UWRK8_B0_UDB15_A0, 0x4000640f +.set CYDEV_UWRK_UWRK8_B0_UDB00_A1, 0x40006410 +.set CYDEV_UWRK_UWRK8_B0_UDB01_A1, 0x40006411 +.set CYDEV_UWRK_UWRK8_B0_UDB02_A1, 0x40006412 +.set CYDEV_UWRK_UWRK8_B0_UDB03_A1, 0x40006413 +.set CYDEV_UWRK_UWRK8_B0_UDB04_A1, 0x40006414 +.set CYDEV_UWRK_UWRK8_B0_UDB05_A1, 0x40006415 +.set CYDEV_UWRK_UWRK8_B0_UDB06_A1, 0x40006416 +.set CYDEV_UWRK_UWRK8_B0_UDB07_A1, 0x40006417 +.set CYDEV_UWRK_UWRK8_B0_UDB08_A1, 0x40006418 +.set CYDEV_UWRK_UWRK8_B0_UDB09_A1, 0x40006419 +.set CYDEV_UWRK_UWRK8_B0_UDB10_A1, 0x4000641a +.set CYDEV_UWRK_UWRK8_B0_UDB11_A1, 0x4000641b +.set CYDEV_UWRK_UWRK8_B0_UDB12_A1, 0x4000641c +.set CYDEV_UWRK_UWRK8_B0_UDB13_A1, 0x4000641d +.set CYDEV_UWRK_UWRK8_B0_UDB14_A1, 0x4000641e +.set CYDEV_UWRK_UWRK8_B0_UDB15_A1, 0x4000641f +.set CYDEV_UWRK_UWRK8_B0_UDB00_D0, 0x40006420 +.set CYDEV_UWRK_UWRK8_B0_UDB01_D0, 0x40006421 +.set CYDEV_UWRK_UWRK8_B0_UDB02_D0, 0x40006422 +.set CYDEV_UWRK_UWRK8_B0_UDB03_D0, 0x40006423 +.set CYDEV_UWRK_UWRK8_B0_UDB04_D0, 0x40006424 +.set CYDEV_UWRK_UWRK8_B0_UDB05_D0, 0x40006425 +.set CYDEV_UWRK_UWRK8_B0_UDB06_D0, 0x40006426 +.set CYDEV_UWRK_UWRK8_B0_UDB07_D0, 0x40006427 +.set CYDEV_UWRK_UWRK8_B0_UDB08_D0, 0x40006428 +.set CYDEV_UWRK_UWRK8_B0_UDB09_D0, 0x40006429 +.set CYDEV_UWRK_UWRK8_B0_UDB10_D0, 0x4000642a +.set CYDEV_UWRK_UWRK8_B0_UDB11_D0, 0x4000642b +.set CYDEV_UWRK_UWRK8_B0_UDB12_D0, 0x4000642c +.set CYDEV_UWRK_UWRK8_B0_UDB13_D0, 0x4000642d +.set CYDEV_UWRK_UWRK8_B0_UDB14_D0, 0x4000642e +.set CYDEV_UWRK_UWRK8_B0_UDB15_D0, 0x4000642f +.set CYDEV_UWRK_UWRK8_B0_UDB00_D1, 0x40006430 +.set CYDEV_UWRK_UWRK8_B0_UDB01_D1, 0x40006431 +.set CYDEV_UWRK_UWRK8_B0_UDB02_D1, 0x40006432 +.set CYDEV_UWRK_UWRK8_B0_UDB03_D1, 0x40006433 +.set CYDEV_UWRK_UWRK8_B0_UDB04_D1, 0x40006434 +.set CYDEV_UWRK_UWRK8_B0_UDB05_D1, 0x40006435 +.set CYDEV_UWRK_UWRK8_B0_UDB06_D1, 0x40006436 +.set CYDEV_UWRK_UWRK8_B0_UDB07_D1, 0x40006437 +.set CYDEV_UWRK_UWRK8_B0_UDB08_D1, 0x40006438 +.set CYDEV_UWRK_UWRK8_B0_UDB09_D1, 0x40006439 +.set CYDEV_UWRK_UWRK8_B0_UDB10_D1, 0x4000643a +.set CYDEV_UWRK_UWRK8_B0_UDB11_D1, 0x4000643b +.set CYDEV_UWRK_UWRK8_B0_UDB12_D1, 0x4000643c +.set CYDEV_UWRK_UWRK8_B0_UDB13_D1, 0x4000643d +.set CYDEV_UWRK_UWRK8_B0_UDB14_D1, 0x4000643e +.set CYDEV_UWRK_UWRK8_B0_UDB15_D1, 0x4000643f +.set CYDEV_UWRK_UWRK8_B0_UDB00_F0, 0x40006440 +.set CYDEV_UWRK_UWRK8_B0_UDB01_F0, 0x40006441 +.set CYDEV_UWRK_UWRK8_B0_UDB02_F0, 0x40006442 +.set CYDEV_UWRK_UWRK8_B0_UDB03_F0, 0x40006443 +.set CYDEV_UWRK_UWRK8_B0_UDB04_F0, 0x40006444 +.set CYDEV_UWRK_UWRK8_B0_UDB05_F0, 0x40006445 +.set CYDEV_UWRK_UWRK8_B0_UDB06_F0, 0x40006446 +.set CYDEV_UWRK_UWRK8_B0_UDB07_F0, 0x40006447 +.set CYDEV_UWRK_UWRK8_B0_UDB08_F0, 0x40006448 +.set CYDEV_UWRK_UWRK8_B0_UDB09_F0, 0x40006449 +.set CYDEV_UWRK_UWRK8_B0_UDB10_F0, 0x4000644a +.set CYDEV_UWRK_UWRK8_B0_UDB11_F0, 0x4000644b +.set CYDEV_UWRK_UWRK8_B0_UDB12_F0, 0x4000644c +.set CYDEV_UWRK_UWRK8_B0_UDB13_F0, 0x4000644d +.set CYDEV_UWRK_UWRK8_B0_UDB14_F0, 0x4000644e +.set CYDEV_UWRK_UWRK8_B0_UDB15_F0, 0x4000644f +.set CYDEV_UWRK_UWRK8_B0_UDB00_F1, 0x40006450 +.set CYDEV_UWRK_UWRK8_B0_UDB01_F1, 0x40006451 +.set CYDEV_UWRK_UWRK8_B0_UDB02_F1, 0x40006452 +.set CYDEV_UWRK_UWRK8_B0_UDB03_F1, 0x40006453 +.set CYDEV_UWRK_UWRK8_B0_UDB04_F1, 0x40006454 +.set CYDEV_UWRK_UWRK8_B0_UDB05_F1, 0x40006455 +.set CYDEV_UWRK_UWRK8_B0_UDB06_F1, 0x40006456 +.set CYDEV_UWRK_UWRK8_B0_UDB07_F1, 0x40006457 +.set CYDEV_UWRK_UWRK8_B0_UDB08_F1, 0x40006458 +.set CYDEV_UWRK_UWRK8_B0_UDB09_F1, 0x40006459 +.set CYDEV_UWRK_UWRK8_B0_UDB10_F1, 0x4000645a +.set CYDEV_UWRK_UWRK8_B0_UDB11_F1, 0x4000645b +.set CYDEV_UWRK_UWRK8_B0_UDB12_F1, 0x4000645c +.set CYDEV_UWRK_UWRK8_B0_UDB13_F1, 0x4000645d +.set CYDEV_UWRK_UWRK8_B0_UDB14_F1, 0x4000645e +.set CYDEV_UWRK_UWRK8_B0_UDB15_F1, 0x4000645f +.set CYDEV_UWRK_UWRK8_B0_UDB00_ST, 0x40006460 +.set CYDEV_UWRK_UWRK8_B0_UDB01_ST, 0x40006461 +.set CYDEV_UWRK_UWRK8_B0_UDB02_ST, 0x40006462 +.set CYDEV_UWRK_UWRK8_B0_UDB03_ST, 0x40006463 +.set CYDEV_UWRK_UWRK8_B0_UDB04_ST, 0x40006464 +.set CYDEV_UWRK_UWRK8_B0_UDB05_ST, 0x40006465 +.set CYDEV_UWRK_UWRK8_B0_UDB06_ST, 0x40006466 +.set CYDEV_UWRK_UWRK8_B0_UDB07_ST, 0x40006467 +.set CYDEV_UWRK_UWRK8_B0_UDB08_ST, 0x40006468 +.set CYDEV_UWRK_UWRK8_B0_UDB09_ST, 0x40006469 +.set CYDEV_UWRK_UWRK8_B0_UDB10_ST, 0x4000646a +.set CYDEV_UWRK_UWRK8_B0_UDB11_ST, 0x4000646b +.set CYDEV_UWRK_UWRK8_B0_UDB12_ST, 0x4000646c +.set CYDEV_UWRK_UWRK8_B0_UDB13_ST, 0x4000646d +.set CYDEV_UWRK_UWRK8_B0_UDB14_ST, 0x4000646e +.set CYDEV_UWRK_UWRK8_B0_UDB15_ST, 0x4000646f +.set CYDEV_UWRK_UWRK8_B0_UDB00_CTL, 0x40006470 +.set CYDEV_UWRK_UWRK8_B0_UDB01_CTL, 0x40006471 +.set CYDEV_UWRK_UWRK8_B0_UDB02_CTL, 0x40006472 +.set CYDEV_UWRK_UWRK8_B0_UDB03_CTL, 0x40006473 +.set CYDEV_UWRK_UWRK8_B0_UDB04_CTL, 0x40006474 +.set CYDEV_UWRK_UWRK8_B0_UDB05_CTL, 0x40006475 +.set CYDEV_UWRK_UWRK8_B0_UDB06_CTL, 0x40006476 +.set CYDEV_UWRK_UWRK8_B0_UDB07_CTL, 0x40006477 +.set CYDEV_UWRK_UWRK8_B0_UDB08_CTL, 0x40006478 +.set CYDEV_UWRK_UWRK8_B0_UDB09_CTL, 0x40006479 +.set CYDEV_UWRK_UWRK8_B0_UDB10_CTL, 0x4000647a +.set CYDEV_UWRK_UWRK8_B0_UDB11_CTL, 0x4000647b +.set CYDEV_UWRK_UWRK8_B0_UDB12_CTL, 0x4000647c +.set CYDEV_UWRK_UWRK8_B0_UDB13_CTL, 0x4000647d +.set CYDEV_UWRK_UWRK8_B0_UDB14_CTL, 0x4000647e +.set CYDEV_UWRK_UWRK8_B0_UDB15_CTL, 0x4000647f +.set CYDEV_UWRK_UWRK8_B0_UDB00_MSK, 0x40006480 +.set CYDEV_UWRK_UWRK8_B0_UDB01_MSK, 0x40006481 +.set CYDEV_UWRK_UWRK8_B0_UDB02_MSK, 0x40006482 +.set CYDEV_UWRK_UWRK8_B0_UDB03_MSK, 0x40006483 +.set CYDEV_UWRK_UWRK8_B0_UDB04_MSK, 0x40006484 +.set CYDEV_UWRK_UWRK8_B0_UDB05_MSK, 0x40006485 +.set CYDEV_UWRK_UWRK8_B0_UDB06_MSK, 0x40006486 +.set CYDEV_UWRK_UWRK8_B0_UDB07_MSK, 0x40006487 +.set CYDEV_UWRK_UWRK8_B0_UDB08_MSK, 0x40006488 +.set CYDEV_UWRK_UWRK8_B0_UDB09_MSK, 0x40006489 +.set CYDEV_UWRK_UWRK8_B0_UDB10_MSK, 0x4000648a +.set CYDEV_UWRK_UWRK8_B0_UDB11_MSK, 0x4000648b +.set CYDEV_UWRK_UWRK8_B0_UDB12_MSK, 0x4000648c +.set CYDEV_UWRK_UWRK8_B0_UDB13_MSK, 0x4000648d +.set CYDEV_UWRK_UWRK8_B0_UDB14_MSK, 0x4000648e +.set CYDEV_UWRK_UWRK8_B0_UDB15_MSK, 0x4000648f +.set CYDEV_UWRK_UWRK8_B0_UDB00_ACTL, 0x40006490 +.set CYDEV_UWRK_UWRK8_B0_UDB01_ACTL, 0x40006491 +.set CYDEV_UWRK_UWRK8_B0_UDB02_ACTL, 0x40006492 +.set CYDEV_UWRK_UWRK8_B0_UDB03_ACTL, 0x40006493 +.set CYDEV_UWRK_UWRK8_B0_UDB04_ACTL, 0x40006494 +.set CYDEV_UWRK_UWRK8_B0_UDB05_ACTL, 0x40006495 +.set CYDEV_UWRK_UWRK8_B0_UDB06_ACTL, 0x40006496 +.set CYDEV_UWRK_UWRK8_B0_UDB07_ACTL, 0x40006497 +.set CYDEV_UWRK_UWRK8_B0_UDB08_ACTL, 0x40006498 +.set CYDEV_UWRK_UWRK8_B0_UDB09_ACTL, 0x40006499 +.set CYDEV_UWRK_UWRK8_B0_UDB10_ACTL, 0x4000649a +.set CYDEV_UWRK_UWRK8_B0_UDB11_ACTL, 0x4000649b +.set CYDEV_UWRK_UWRK8_B0_UDB12_ACTL, 0x4000649c +.set CYDEV_UWRK_UWRK8_B0_UDB13_ACTL, 0x4000649d +.set CYDEV_UWRK_UWRK8_B0_UDB14_ACTL, 0x4000649e +.set CYDEV_UWRK_UWRK8_B0_UDB15_ACTL, 0x4000649f +.set CYDEV_UWRK_UWRK8_B0_UDB00_MC, 0x400064a0 +.set CYDEV_UWRK_UWRK8_B0_UDB01_MC, 0x400064a1 +.set CYDEV_UWRK_UWRK8_B0_UDB02_MC, 0x400064a2 +.set CYDEV_UWRK_UWRK8_B0_UDB03_MC, 0x400064a3 +.set CYDEV_UWRK_UWRK8_B0_UDB04_MC, 0x400064a4 +.set CYDEV_UWRK_UWRK8_B0_UDB05_MC, 0x400064a5 +.set CYDEV_UWRK_UWRK8_B0_UDB06_MC, 0x400064a6 +.set CYDEV_UWRK_UWRK8_B0_UDB07_MC, 0x400064a7 +.set CYDEV_UWRK_UWRK8_B0_UDB08_MC, 0x400064a8 +.set CYDEV_UWRK_UWRK8_B0_UDB09_MC, 0x400064a9 +.set CYDEV_UWRK_UWRK8_B0_UDB10_MC, 0x400064aa +.set CYDEV_UWRK_UWRK8_B0_UDB11_MC, 0x400064ab +.set CYDEV_UWRK_UWRK8_B0_UDB12_MC, 0x400064ac +.set CYDEV_UWRK_UWRK8_B0_UDB13_MC, 0x400064ad +.set CYDEV_UWRK_UWRK8_B0_UDB14_MC, 0x400064ae +.set CYDEV_UWRK_UWRK8_B0_UDB15_MC, 0x400064af +.set CYDEV_UWRK_UWRK8_B1_BASE, 0x40006500 +.set CYDEV_UWRK_UWRK8_B1_SIZE, 0x000000b0 +.set CYDEV_UWRK_UWRK8_B1_UDB04_A0, 0x40006504 +.set CYDEV_UWRK_UWRK8_B1_UDB05_A0, 0x40006505 +.set CYDEV_UWRK_UWRK8_B1_UDB06_A0, 0x40006506 +.set CYDEV_UWRK_UWRK8_B1_UDB07_A0, 0x40006507 +.set CYDEV_UWRK_UWRK8_B1_UDB08_A0, 0x40006508 +.set CYDEV_UWRK_UWRK8_B1_UDB09_A0, 0x40006509 +.set CYDEV_UWRK_UWRK8_B1_UDB10_A0, 0x4000650a +.set CYDEV_UWRK_UWRK8_B1_UDB11_A0, 0x4000650b +.set CYDEV_UWRK_UWRK8_B1_UDB04_A1, 0x40006514 +.set CYDEV_UWRK_UWRK8_B1_UDB05_A1, 0x40006515 +.set CYDEV_UWRK_UWRK8_B1_UDB06_A1, 0x40006516 +.set CYDEV_UWRK_UWRK8_B1_UDB07_A1, 0x40006517 +.set CYDEV_UWRK_UWRK8_B1_UDB08_A1, 0x40006518 +.set CYDEV_UWRK_UWRK8_B1_UDB09_A1, 0x40006519 +.set CYDEV_UWRK_UWRK8_B1_UDB10_A1, 0x4000651a +.set CYDEV_UWRK_UWRK8_B1_UDB11_A1, 0x4000651b +.set CYDEV_UWRK_UWRK8_B1_UDB04_D0, 0x40006524 +.set CYDEV_UWRK_UWRK8_B1_UDB05_D0, 0x40006525 +.set CYDEV_UWRK_UWRK8_B1_UDB06_D0, 0x40006526 +.set CYDEV_UWRK_UWRK8_B1_UDB07_D0, 0x40006527 +.set CYDEV_UWRK_UWRK8_B1_UDB08_D0, 0x40006528 +.set CYDEV_UWRK_UWRK8_B1_UDB09_D0, 0x40006529 +.set CYDEV_UWRK_UWRK8_B1_UDB10_D0, 0x4000652a +.set CYDEV_UWRK_UWRK8_B1_UDB11_D0, 0x4000652b +.set CYDEV_UWRK_UWRK8_B1_UDB04_D1, 0x40006534 +.set CYDEV_UWRK_UWRK8_B1_UDB05_D1, 0x40006535 +.set CYDEV_UWRK_UWRK8_B1_UDB06_D1, 0x40006536 +.set CYDEV_UWRK_UWRK8_B1_UDB07_D1, 0x40006537 +.set CYDEV_UWRK_UWRK8_B1_UDB08_D1, 0x40006538 +.set CYDEV_UWRK_UWRK8_B1_UDB09_D1, 0x40006539 +.set CYDEV_UWRK_UWRK8_B1_UDB10_D1, 0x4000653a +.set CYDEV_UWRK_UWRK8_B1_UDB11_D1, 0x4000653b +.set CYDEV_UWRK_UWRK8_B1_UDB04_F0, 0x40006544 +.set CYDEV_UWRK_UWRK8_B1_UDB05_F0, 0x40006545 +.set CYDEV_UWRK_UWRK8_B1_UDB06_F0, 0x40006546 +.set CYDEV_UWRK_UWRK8_B1_UDB07_F0, 0x40006547 +.set CYDEV_UWRK_UWRK8_B1_UDB08_F0, 0x40006548 +.set CYDEV_UWRK_UWRK8_B1_UDB09_F0, 0x40006549 +.set CYDEV_UWRK_UWRK8_B1_UDB10_F0, 0x4000654a +.set CYDEV_UWRK_UWRK8_B1_UDB11_F0, 0x4000654b +.set CYDEV_UWRK_UWRK8_B1_UDB04_F1, 0x40006554 +.set CYDEV_UWRK_UWRK8_B1_UDB05_F1, 0x40006555 +.set CYDEV_UWRK_UWRK8_B1_UDB06_F1, 0x40006556 +.set CYDEV_UWRK_UWRK8_B1_UDB07_F1, 0x40006557 +.set CYDEV_UWRK_UWRK8_B1_UDB08_F1, 0x40006558 +.set CYDEV_UWRK_UWRK8_B1_UDB09_F1, 0x40006559 +.set CYDEV_UWRK_UWRK8_B1_UDB10_F1, 0x4000655a +.set CYDEV_UWRK_UWRK8_B1_UDB11_F1, 0x4000655b +.set CYDEV_UWRK_UWRK8_B1_UDB04_ST, 0x40006564 +.set CYDEV_UWRK_UWRK8_B1_UDB05_ST, 0x40006565 +.set CYDEV_UWRK_UWRK8_B1_UDB06_ST, 0x40006566 +.set CYDEV_UWRK_UWRK8_B1_UDB07_ST, 0x40006567 +.set CYDEV_UWRK_UWRK8_B1_UDB08_ST, 0x40006568 +.set CYDEV_UWRK_UWRK8_B1_UDB09_ST, 0x40006569 +.set CYDEV_UWRK_UWRK8_B1_UDB10_ST, 0x4000656a +.set CYDEV_UWRK_UWRK8_B1_UDB11_ST, 0x4000656b +.set CYDEV_UWRK_UWRK8_B1_UDB04_CTL, 0x40006574 +.set CYDEV_UWRK_UWRK8_B1_UDB05_CTL, 0x40006575 +.set CYDEV_UWRK_UWRK8_B1_UDB06_CTL, 0x40006576 +.set CYDEV_UWRK_UWRK8_B1_UDB07_CTL, 0x40006577 +.set CYDEV_UWRK_UWRK8_B1_UDB08_CTL, 0x40006578 +.set CYDEV_UWRK_UWRK8_B1_UDB09_CTL, 0x40006579 +.set CYDEV_UWRK_UWRK8_B1_UDB10_CTL, 0x4000657a +.set CYDEV_UWRK_UWRK8_B1_UDB11_CTL, 0x4000657b +.set CYDEV_UWRK_UWRK8_B1_UDB04_MSK, 0x40006584 +.set CYDEV_UWRK_UWRK8_B1_UDB05_MSK, 0x40006585 +.set CYDEV_UWRK_UWRK8_B1_UDB06_MSK, 0x40006586 +.set CYDEV_UWRK_UWRK8_B1_UDB07_MSK, 0x40006587 +.set CYDEV_UWRK_UWRK8_B1_UDB08_MSK, 0x40006588 +.set CYDEV_UWRK_UWRK8_B1_UDB09_MSK, 0x40006589 +.set CYDEV_UWRK_UWRK8_B1_UDB10_MSK, 0x4000658a +.set CYDEV_UWRK_UWRK8_B1_UDB11_MSK, 0x4000658b +.set CYDEV_UWRK_UWRK8_B1_UDB04_ACTL, 0x40006594 +.set CYDEV_UWRK_UWRK8_B1_UDB05_ACTL, 0x40006595 +.set CYDEV_UWRK_UWRK8_B1_UDB06_ACTL, 0x40006596 +.set CYDEV_UWRK_UWRK8_B1_UDB07_ACTL, 0x40006597 +.set CYDEV_UWRK_UWRK8_B1_UDB08_ACTL, 0x40006598 +.set CYDEV_UWRK_UWRK8_B1_UDB09_ACTL, 0x40006599 +.set CYDEV_UWRK_UWRK8_B1_UDB10_ACTL, 0x4000659a +.set CYDEV_UWRK_UWRK8_B1_UDB11_ACTL, 0x4000659b +.set CYDEV_UWRK_UWRK8_B1_UDB04_MC, 0x400065a4 +.set CYDEV_UWRK_UWRK8_B1_UDB05_MC, 0x400065a5 +.set CYDEV_UWRK_UWRK8_B1_UDB06_MC, 0x400065a6 +.set CYDEV_UWRK_UWRK8_B1_UDB07_MC, 0x400065a7 +.set CYDEV_UWRK_UWRK8_B1_UDB08_MC, 0x400065a8 +.set CYDEV_UWRK_UWRK8_B1_UDB09_MC, 0x400065a9 +.set CYDEV_UWRK_UWRK8_B1_UDB10_MC, 0x400065aa +.set CYDEV_UWRK_UWRK8_B1_UDB11_MC, 0x400065ab +.set CYDEV_UWRK_UWRK16_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_SIZE, 0x00000760 +.set CYDEV_UWRK_UWRK16_CAT_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_CAT_SIZE, 0x00000760 +.set CYDEV_UWRK_UWRK16_CAT_B0_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_CAT_B0_SIZE, 0x00000160 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1, 0x40006800 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1, 0x40006802 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1, 0x40006804 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1, 0x40006806 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1, 0x40006808 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1, 0x4000680a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1, 0x4000680c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1, 0x4000680e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1, 0x40006810 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1, 0x40006812 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1, 0x40006814 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1, 0x40006816 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1, 0x40006818 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1, 0x4000681a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1, 0x4000681c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1, 0x4000681e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1, 0x40006840 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1, 0x40006842 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1, 0x40006844 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1, 0x40006846 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1, 0x40006848 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1, 0x4000684a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1, 0x4000684c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1, 0x4000684e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1, 0x40006850 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1, 0x40006852 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1, 0x40006854 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1, 0x40006856 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1, 0x40006858 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1, 0x4000685a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1, 0x4000685c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1, 0x4000685e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1, 0x40006880 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1, 0x40006882 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1, 0x40006884 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1, 0x40006886 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1, 0x40006888 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1, 0x4000688a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1, 0x4000688c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1, 0x4000688e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1, 0x40006890 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1, 0x40006892 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1, 0x40006894 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1, 0x40006896 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1, 0x40006898 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1, 0x4000689a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1, 0x4000689c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1, 0x4000689e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL, 0x400068c0 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL, 0x400068c2 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL, 0x400068c4 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL, 0x400068c6 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL, 0x400068c8 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL, 0x400068ca +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL, 0x400068cc +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL, 0x400068ce +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL, 0x400068d0 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL, 0x400068d2 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL, 0x400068d4 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL, 0x400068d6 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL, 0x400068d8 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL, 0x400068da +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL, 0x400068dc +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL, 0x400068de +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL, 0x40006900 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL, 0x40006902 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL, 0x40006904 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL, 0x40006906 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL, 0x40006908 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL, 0x4000690a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL, 0x4000690c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL, 0x4000690e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL, 0x40006910 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL, 0x40006912 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL, 0x40006914 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL, 0x40006916 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL, 0x40006918 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL, 0x4000691a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL, 0x4000691c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL, 0x4000691e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00, 0x40006940 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00, 0x40006942 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00, 0x40006944 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00, 0x40006946 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00, 0x40006948 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00, 0x4000694a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00, 0x4000694c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00, 0x4000694e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00, 0x40006950 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00, 0x40006952 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00, 0x40006954 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00, 0x40006956 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00, 0x40006958 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00, 0x4000695a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00, 0x4000695c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00, 0x4000695e +.set CYDEV_UWRK_UWRK16_CAT_B1_BASE, 0x40006a00 +.set CYDEV_UWRK_UWRK16_CAT_B1_SIZE, 0x00000160 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1, 0x40006a08 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1, 0x40006a0a +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1, 0x40006a0c +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1, 0x40006a0e +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1, 0x40006a10 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1, 0x40006a12 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1, 0x40006a14 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1, 0x40006a16 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1, 0x40006a48 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1, 0x40006a4a +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1, 0x40006a4c +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1, 0x40006a4e +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1, 0x40006a50 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1, 0x40006a52 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1, 0x40006a54 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1, 0x40006a56 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1, 0x40006a88 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1, 0x40006a8a +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1, 0x40006a8c +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1, 0x40006a8e +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1, 0x40006a90 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1, 0x40006a92 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1, 0x40006a94 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1, 0x40006a96 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL, 0x40006ac8 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL, 0x40006aca +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL, 0x40006acc +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL, 0x40006ace +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL, 0x40006ad0 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL, 0x40006ad2 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL, 0x40006ad4 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL, 0x40006ad6 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL, 0x40006b08 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL, 0x40006b0a +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL, 0x40006b0c +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL, 0x40006b0e +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL, 0x40006b10 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL, 0x40006b12 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL, 0x40006b14 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL, 0x40006b16 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00, 0x40006b48 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00, 0x40006b4a +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00, 0x40006b4c +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00, 0x40006b4e +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00, 0x40006b50 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00, 0x40006b52 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00, 0x40006b54 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00, 0x40006b56 +.set CYDEV_UWRK_UWRK16_DEF_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_DEF_SIZE, 0x0000075e +.set CYDEV_UWRK_UWRK16_DEF_B0_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_DEF_B0_SIZE, 0x0000015e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0, 0x40006800 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0, 0x40006802 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0, 0x40006804 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0, 0x40006806 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0, 0x40006808 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0, 0x4000680a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0, 0x4000680c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0, 0x4000680e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0, 0x40006810 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0, 0x40006812 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0, 0x40006814 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0, 0x40006816 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0, 0x40006818 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0, 0x4000681a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0, 0x4000681c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1, 0x40006820 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1, 0x40006822 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1, 0x40006824 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1, 0x40006826 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1, 0x40006828 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1, 0x4000682a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1, 0x4000682c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1, 0x4000682e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1, 0x40006830 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1, 0x40006832 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1, 0x40006834 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1, 0x40006836 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1, 0x40006838 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1, 0x4000683a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1, 0x4000683c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0, 0x40006840 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0, 0x40006842 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0, 0x40006844 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0, 0x40006846 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0, 0x40006848 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0, 0x4000684a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0, 0x4000684c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0, 0x4000684e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0, 0x40006850 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0, 0x40006852 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0, 0x40006854 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0, 0x40006856 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0, 0x40006858 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0, 0x4000685a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0, 0x4000685c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1, 0x40006860 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1, 0x40006862 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1, 0x40006864 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1, 0x40006866 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1, 0x40006868 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1, 0x4000686a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1, 0x4000686c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1, 0x4000686e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1, 0x40006870 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1, 0x40006872 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1, 0x40006874 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1, 0x40006876 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1, 0x40006878 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1, 0x4000687a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1, 0x4000687c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0, 0x40006880 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0, 0x40006882 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0, 0x40006884 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0, 0x40006886 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0, 0x40006888 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0, 0x4000688a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0, 0x4000688c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0, 0x4000688e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0, 0x40006890 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0, 0x40006892 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0, 0x40006894 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0, 0x40006896 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0, 0x40006898 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0, 0x4000689a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0, 0x4000689c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1, 0x400068a0 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1, 0x400068a2 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1, 0x400068a4 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1, 0x400068a6 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1, 0x400068a8 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1, 0x400068aa +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1, 0x400068ac +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1, 0x400068ae +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1, 0x400068b0 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1, 0x400068b2 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1, 0x400068b4 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1, 0x400068b6 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1, 0x400068b8 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1, 0x400068ba +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1, 0x400068bc +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST, 0x400068c0 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST, 0x400068c2 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST, 0x400068c4 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST, 0x400068c6 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST, 0x400068c8 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST, 0x400068ca +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST, 0x400068cc +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST, 0x400068ce +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST, 0x400068d0 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST, 0x400068d2 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST, 0x400068d4 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST, 0x400068d6 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST, 0x400068d8 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST, 0x400068da +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST, 0x400068dc +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL, 0x400068e0 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL, 0x400068e2 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL, 0x400068e4 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL, 0x400068e6 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL, 0x400068e8 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL, 0x400068ea +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL, 0x400068ec +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL, 0x400068ee +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL, 0x400068f0 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL, 0x400068f2 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL, 0x400068f4 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL, 0x400068f6 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL, 0x400068f8 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL, 0x400068fa +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL, 0x400068fc +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK, 0x40006900 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK, 0x40006902 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK, 0x40006904 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK, 0x40006906 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK, 0x40006908 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK, 0x4000690a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK, 0x4000690c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK, 0x4000690e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK, 0x40006910 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK, 0x40006912 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK, 0x40006914 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK, 0x40006916 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK, 0x40006918 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK, 0x4000691a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK, 0x4000691c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL, 0x40006920 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL, 0x40006922 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL, 0x40006924 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL, 0x40006926 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL, 0x40006928 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL, 0x4000692a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL, 0x4000692c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL, 0x4000692e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL, 0x40006930 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL, 0x40006932 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL, 0x40006934 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL, 0x40006936 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL, 0x40006938 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL, 0x4000693a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL, 0x4000693c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC, 0x40006940 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC, 0x40006942 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC, 0x40006944 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC, 0x40006946 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC, 0x40006948 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC, 0x4000694a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC, 0x4000694c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC, 0x4000694e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC, 0x40006950 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC, 0x40006952 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC, 0x40006954 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC, 0x40006956 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC, 0x40006958 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC, 0x4000695a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC, 0x4000695c +.set CYDEV_UWRK_UWRK16_DEF_B1_BASE, 0x40006a00 +.set CYDEV_UWRK_UWRK16_DEF_B1_SIZE, 0x0000015e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0, 0x40006a08 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0, 0x40006a0a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0, 0x40006a0c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0, 0x40006a0e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0, 0x40006a10 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0, 0x40006a12 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0, 0x40006a14 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0, 0x40006a16 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1, 0x40006a28 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1, 0x40006a2a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1, 0x40006a2c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1, 0x40006a2e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1, 0x40006a30 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1, 0x40006a32 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1, 0x40006a34 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1, 0x40006a36 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0, 0x40006a48 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0, 0x40006a4a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0, 0x40006a4c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0, 0x40006a4e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0, 0x40006a50 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0, 0x40006a52 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0, 0x40006a54 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0, 0x40006a56 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1, 0x40006a68 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1, 0x40006a6a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1, 0x40006a6c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1, 0x40006a6e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1, 0x40006a70 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1, 0x40006a72 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1, 0x40006a74 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1, 0x40006a76 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0, 0x40006a88 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0, 0x40006a8a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0, 0x40006a8c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0, 0x40006a8e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0, 0x40006a90 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0, 0x40006a92 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0, 0x40006a94 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0, 0x40006a96 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1, 0x40006aa8 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1, 0x40006aaa +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1, 0x40006aac +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1, 0x40006aae +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1, 0x40006ab0 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1, 0x40006ab2 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1, 0x40006ab4 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1, 0x40006ab6 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST, 0x40006ac8 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST, 0x40006aca +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST, 0x40006acc +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST, 0x40006ace +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST, 0x40006ad0 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST, 0x40006ad2 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST, 0x40006ad4 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST, 0x40006ad6 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL, 0x40006ae8 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL, 0x40006aea +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL, 0x40006aec +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL, 0x40006aee +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL, 0x40006af0 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL, 0x40006af2 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL, 0x40006af4 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL, 0x40006af6 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK, 0x40006b08 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK, 0x40006b0a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK, 0x40006b0c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK, 0x40006b0e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK, 0x40006b10 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK, 0x40006b12 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK, 0x40006b14 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK, 0x40006b16 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL, 0x40006b28 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL, 0x40006b2a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL, 0x40006b2c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL, 0x40006b2e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL, 0x40006b30 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL, 0x40006b32 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL, 0x40006b34 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL, 0x40006b36 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC, 0x40006b48 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC, 0x40006b4a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC, 0x40006b4c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC, 0x40006b4e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC, 0x40006b50 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC, 0x40006b52 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC, 0x40006b54 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC, 0x40006b56 +.set CYDEV_PHUB_BASE, 0x40007000 +.set CYDEV_PHUB_SIZE, 0x00000c00 +.set CYDEV_PHUB_CFG, 0x40007000 +.set CYDEV_PHUB_ERR, 0x40007004 +.set CYDEV_PHUB_ERR_ADR, 0x40007008 +.set CYDEV_PHUB_CH0_BASE, 0x40007010 +.set CYDEV_PHUB_CH0_SIZE, 0x0000000c +.set CYDEV_PHUB_CH0_BASIC_CFG, 0x40007010 +.set CYDEV_PHUB_CH0_ACTION, 0x40007014 +.set CYDEV_PHUB_CH0_BASIC_STATUS, 0x40007018 +.set CYDEV_PHUB_CH1_BASE, 0x40007020 +.set CYDEV_PHUB_CH1_SIZE, 0x0000000c +.set CYDEV_PHUB_CH1_BASIC_CFG, 0x40007020 +.set CYDEV_PHUB_CH1_ACTION, 0x40007024 +.set CYDEV_PHUB_CH1_BASIC_STATUS, 0x40007028 +.set CYDEV_PHUB_CH2_BASE, 0x40007030 +.set CYDEV_PHUB_CH2_SIZE, 0x0000000c +.set CYDEV_PHUB_CH2_BASIC_CFG, 0x40007030 +.set CYDEV_PHUB_CH2_ACTION, 0x40007034 +.set CYDEV_PHUB_CH2_BASIC_STATUS, 0x40007038 +.set CYDEV_PHUB_CH3_BASE, 0x40007040 +.set CYDEV_PHUB_CH3_SIZE, 0x0000000c +.set CYDEV_PHUB_CH3_BASIC_CFG, 0x40007040 +.set CYDEV_PHUB_CH3_ACTION, 0x40007044 +.set CYDEV_PHUB_CH3_BASIC_STATUS, 0x40007048 +.set CYDEV_PHUB_CH4_BASE, 0x40007050 +.set CYDEV_PHUB_CH4_SIZE, 0x0000000c +.set CYDEV_PHUB_CH4_BASIC_CFG, 0x40007050 +.set CYDEV_PHUB_CH4_ACTION, 0x40007054 +.set CYDEV_PHUB_CH4_BASIC_STATUS, 0x40007058 +.set CYDEV_PHUB_CH5_BASE, 0x40007060 +.set CYDEV_PHUB_CH5_SIZE, 0x0000000c +.set CYDEV_PHUB_CH5_BASIC_CFG, 0x40007060 +.set CYDEV_PHUB_CH5_ACTION, 0x40007064 +.set CYDEV_PHUB_CH5_BASIC_STATUS, 0x40007068 +.set CYDEV_PHUB_CH6_BASE, 0x40007070 +.set CYDEV_PHUB_CH6_SIZE, 0x0000000c +.set CYDEV_PHUB_CH6_BASIC_CFG, 0x40007070 +.set CYDEV_PHUB_CH6_ACTION, 0x40007074 +.set CYDEV_PHUB_CH6_BASIC_STATUS, 0x40007078 +.set CYDEV_PHUB_CH7_BASE, 0x40007080 +.set CYDEV_PHUB_CH7_SIZE, 0x0000000c +.set CYDEV_PHUB_CH7_BASIC_CFG, 0x40007080 +.set CYDEV_PHUB_CH7_ACTION, 0x40007084 +.set CYDEV_PHUB_CH7_BASIC_STATUS, 0x40007088 +.set CYDEV_PHUB_CH8_BASE, 0x40007090 +.set CYDEV_PHUB_CH8_SIZE, 0x0000000c +.set CYDEV_PHUB_CH8_BASIC_CFG, 0x40007090 +.set CYDEV_PHUB_CH8_ACTION, 0x40007094 +.set CYDEV_PHUB_CH8_BASIC_STATUS, 0x40007098 +.set CYDEV_PHUB_CH9_BASE, 0x400070a0 +.set CYDEV_PHUB_CH9_SIZE, 0x0000000c +.set CYDEV_PHUB_CH9_BASIC_CFG, 0x400070a0 +.set CYDEV_PHUB_CH9_ACTION, 0x400070a4 +.set CYDEV_PHUB_CH9_BASIC_STATUS, 0x400070a8 +.set CYDEV_PHUB_CH10_BASE, 0x400070b0 +.set CYDEV_PHUB_CH10_SIZE, 0x0000000c +.set CYDEV_PHUB_CH10_BASIC_CFG, 0x400070b0 +.set CYDEV_PHUB_CH10_ACTION, 0x400070b4 +.set CYDEV_PHUB_CH10_BASIC_STATUS, 0x400070b8 +.set CYDEV_PHUB_CH11_BASE, 0x400070c0 +.set CYDEV_PHUB_CH11_SIZE, 0x0000000c +.set CYDEV_PHUB_CH11_BASIC_CFG, 0x400070c0 +.set CYDEV_PHUB_CH11_ACTION, 0x400070c4 +.set CYDEV_PHUB_CH11_BASIC_STATUS, 0x400070c8 +.set CYDEV_PHUB_CH12_BASE, 0x400070d0 +.set CYDEV_PHUB_CH12_SIZE, 0x0000000c +.set CYDEV_PHUB_CH12_BASIC_CFG, 0x400070d0 +.set CYDEV_PHUB_CH12_ACTION, 0x400070d4 +.set CYDEV_PHUB_CH12_BASIC_STATUS, 0x400070d8 +.set CYDEV_PHUB_CH13_BASE, 0x400070e0 +.set CYDEV_PHUB_CH13_SIZE, 0x0000000c +.set CYDEV_PHUB_CH13_BASIC_CFG, 0x400070e0 +.set CYDEV_PHUB_CH13_ACTION, 0x400070e4 +.set CYDEV_PHUB_CH13_BASIC_STATUS, 0x400070e8 +.set CYDEV_PHUB_CH14_BASE, 0x400070f0 +.set CYDEV_PHUB_CH14_SIZE, 0x0000000c +.set CYDEV_PHUB_CH14_BASIC_CFG, 0x400070f0 +.set CYDEV_PHUB_CH14_ACTION, 0x400070f4 +.set CYDEV_PHUB_CH14_BASIC_STATUS, 0x400070f8 +.set CYDEV_PHUB_CH15_BASE, 0x40007100 +.set CYDEV_PHUB_CH15_SIZE, 0x0000000c +.set CYDEV_PHUB_CH15_BASIC_CFG, 0x40007100 +.set CYDEV_PHUB_CH15_ACTION, 0x40007104 +.set CYDEV_PHUB_CH15_BASIC_STATUS, 0x40007108 +.set CYDEV_PHUB_CH16_BASE, 0x40007110 +.set CYDEV_PHUB_CH16_SIZE, 0x0000000c +.set CYDEV_PHUB_CH16_BASIC_CFG, 0x40007110 +.set CYDEV_PHUB_CH16_ACTION, 0x40007114 +.set CYDEV_PHUB_CH16_BASIC_STATUS, 0x40007118 +.set CYDEV_PHUB_CH17_BASE, 0x40007120 +.set CYDEV_PHUB_CH17_SIZE, 0x0000000c +.set CYDEV_PHUB_CH17_BASIC_CFG, 0x40007120 +.set CYDEV_PHUB_CH17_ACTION, 0x40007124 +.set CYDEV_PHUB_CH17_BASIC_STATUS, 0x40007128 +.set CYDEV_PHUB_CH18_BASE, 0x40007130 +.set CYDEV_PHUB_CH18_SIZE, 0x0000000c +.set CYDEV_PHUB_CH18_BASIC_CFG, 0x40007130 +.set CYDEV_PHUB_CH18_ACTION, 0x40007134 +.set CYDEV_PHUB_CH18_BASIC_STATUS, 0x40007138 +.set CYDEV_PHUB_CH19_BASE, 0x40007140 +.set CYDEV_PHUB_CH19_SIZE, 0x0000000c +.set CYDEV_PHUB_CH19_BASIC_CFG, 0x40007140 +.set CYDEV_PHUB_CH19_ACTION, 0x40007144 +.set CYDEV_PHUB_CH19_BASIC_STATUS, 0x40007148 +.set CYDEV_PHUB_CH20_BASE, 0x40007150 +.set CYDEV_PHUB_CH20_SIZE, 0x0000000c +.set CYDEV_PHUB_CH20_BASIC_CFG, 0x40007150 +.set CYDEV_PHUB_CH20_ACTION, 0x40007154 +.set CYDEV_PHUB_CH20_BASIC_STATUS, 0x40007158 +.set CYDEV_PHUB_CH21_BASE, 0x40007160 +.set CYDEV_PHUB_CH21_SIZE, 0x0000000c +.set CYDEV_PHUB_CH21_BASIC_CFG, 0x40007160 +.set CYDEV_PHUB_CH21_ACTION, 0x40007164 +.set CYDEV_PHUB_CH21_BASIC_STATUS, 0x40007168 +.set CYDEV_PHUB_CH22_BASE, 0x40007170 +.set CYDEV_PHUB_CH22_SIZE, 0x0000000c +.set CYDEV_PHUB_CH22_BASIC_CFG, 0x40007170 +.set CYDEV_PHUB_CH22_ACTION, 0x40007174 +.set CYDEV_PHUB_CH22_BASIC_STATUS, 0x40007178 +.set CYDEV_PHUB_CH23_BASE, 0x40007180 +.set CYDEV_PHUB_CH23_SIZE, 0x0000000c +.set CYDEV_PHUB_CH23_BASIC_CFG, 0x40007180 +.set CYDEV_PHUB_CH23_ACTION, 0x40007184 +.set CYDEV_PHUB_CH23_BASIC_STATUS, 0x40007188 +.set CYDEV_PHUB_CFGMEM0_BASE, 0x40007600 +.set CYDEV_PHUB_CFGMEM0_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM0_CFG0, 0x40007600 +.set CYDEV_PHUB_CFGMEM0_CFG1, 0x40007604 +.set CYDEV_PHUB_CFGMEM1_BASE, 0x40007608 +.set CYDEV_PHUB_CFGMEM1_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM1_CFG0, 0x40007608 +.set CYDEV_PHUB_CFGMEM1_CFG1, 0x4000760c +.set CYDEV_PHUB_CFGMEM2_BASE, 0x40007610 +.set CYDEV_PHUB_CFGMEM2_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM2_CFG0, 0x40007610 +.set CYDEV_PHUB_CFGMEM2_CFG1, 0x40007614 +.set CYDEV_PHUB_CFGMEM3_BASE, 0x40007618 +.set CYDEV_PHUB_CFGMEM3_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM3_CFG0, 0x40007618 +.set CYDEV_PHUB_CFGMEM3_CFG1, 0x4000761c +.set CYDEV_PHUB_CFGMEM4_BASE, 0x40007620 +.set CYDEV_PHUB_CFGMEM4_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM4_CFG0, 0x40007620 +.set CYDEV_PHUB_CFGMEM4_CFG1, 0x40007624 +.set CYDEV_PHUB_CFGMEM5_BASE, 0x40007628 +.set CYDEV_PHUB_CFGMEM5_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM5_CFG0, 0x40007628 +.set CYDEV_PHUB_CFGMEM5_CFG1, 0x4000762c +.set CYDEV_PHUB_CFGMEM6_BASE, 0x40007630 +.set CYDEV_PHUB_CFGMEM6_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM6_CFG0, 0x40007630 +.set CYDEV_PHUB_CFGMEM6_CFG1, 0x40007634 +.set CYDEV_PHUB_CFGMEM7_BASE, 0x40007638 +.set CYDEV_PHUB_CFGMEM7_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM7_CFG0, 0x40007638 +.set CYDEV_PHUB_CFGMEM7_CFG1, 0x4000763c +.set CYDEV_PHUB_CFGMEM8_BASE, 0x40007640 +.set CYDEV_PHUB_CFGMEM8_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM8_CFG0, 0x40007640 +.set CYDEV_PHUB_CFGMEM8_CFG1, 0x40007644 +.set CYDEV_PHUB_CFGMEM9_BASE, 0x40007648 +.set CYDEV_PHUB_CFGMEM9_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM9_CFG0, 0x40007648 +.set CYDEV_PHUB_CFGMEM9_CFG1, 0x4000764c +.set CYDEV_PHUB_CFGMEM10_BASE, 0x40007650 +.set CYDEV_PHUB_CFGMEM10_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM10_CFG0, 0x40007650 +.set CYDEV_PHUB_CFGMEM10_CFG1, 0x40007654 +.set CYDEV_PHUB_CFGMEM11_BASE, 0x40007658 +.set CYDEV_PHUB_CFGMEM11_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM11_CFG0, 0x40007658 +.set CYDEV_PHUB_CFGMEM11_CFG1, 0x4000765c +.set CYDEV_PHUB_CFGMEM12_BASE, 0x40007660 +.set CYDEV_PHUB_CFGMEM12_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM12_CFG0, 0x40007660 +.set CYDEV_PHUB_CFGMEM12_CFG1, 0x40007664 +.set CYDEV_PHUB_CFGMEM13_BASE, 0x40007668 +.set CYDEV_PHUB_CFGMEM13_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM13_CFG0, 0x40007668 +.set CYDEV_PHUB_CFGMEM13_CFG1, 0x4000766c +.set CYDEV_PHUB_CFGMEM14_BASE, 0x40007670 +.set CYDEV_PHUB_CFGMEM14_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM14_CFG0, 0x40007670 +.set CYDEV_PHUB_CFGMEM14_CFG1, 0x40007674 +.set CYDEV_PHUB_CFGMEM15_BASE, 0x40007678 +.set CYDEV_PHUB_CFGMEM15_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM15_CFG0, 0x40007678 +.set CYDEV_PHUB_CFGMEM15_CFG1, 0x4000767c +.set CYDEV_PHUB_CFGMEM16_BASE, 0x40007680 +.set CYDEV_PHUB_CFGMEM16_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM16_CFG0, 0x40007680 +.set CYDEV_PHUB_CFGMEM16_CFG1, 0x40007684 +.set CYDEV_PHUB_CFGMEM17_BASE, 0x40007688 +.set CYDEV_PHUB_CFGMEM17_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM17_CFG0, 0x40007688 +.set CYDEV_PHUB_CFGMEM17_CFG1, 0x4000768c +.set CYDEV_PHUB_CFGMEM18_BASE, 0x40007690 +.set CYDEV_PHUB_CFGMEM18_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM18_CFG0, 0x40007690 +.set CYDEV_PHUB_CFGMEM18_CFG1, 0x40007694 +.set CYDEV_PHUB_CFGMEM19_BASE, 0x40007698 +.set CYDEV_PHUB_CFGMEM19_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM19_CFG0, 0x40007698 +.set CYDEV_PHUB_CFGMEM19_CFG1, 0x4000769c +.set CYDEV_PHUB_CFGMEM20_BASE, 0x400076a0 +.set CYDEV_PHUB_CFGMEM20_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM20_CFG0, 0x400076a0 +.set CYDEV_PHUB_CFGMEM20_CFG1, 0x400076a4 +.set CYDEV_PHUB_CFGMEM21_BASE, 0x400076a8 +.set CYDEV_PHUB_CFGMEM21_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM21_CFG0, 0x400076a8 +.set CYDEV_PHUB_CFGMEM21_CFG1, 0x400076ac +.set CYDEV_PHUB_CFGMEM22_BASE, 0x400076b0 +.set CYDEV_PHUB_CFGMEM22_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM22_CFG0, 0x400076b0 +.set CYDEV_PHUB_CFGMEM22_CFG1, 0x400076b4 +.set CYDEV_PHUB_CFGMEM23_BASE, 0x400076b8 +.set CYDEV_PHUB_CFGMEM23_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM23_CFG0, 0x400076b8 +.set CYDEV_PHUB_CFGMEM23_CFG1, 0x400076bc +.set CYDEV_PHUB_TDMEM0_BASE, 0x40007800 +.set CYDEV_PHUB_TDMEM0_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM0_ORIG_TD0, 0x40007800 +.set CYDEV_PHUB_TDMEM0_ORIG_TD1, 0x40007804 +.set CYDEV_PHUB_TDMEM1_BASE, 0x40007808 +.set CYDEV_PHUB_TDMEM1_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM1_ORIG_TD0, 0x40007808 +.set CYDEV_PHUB_TDMEM1_ORIG_TD1, 0x4000780c +.set CYDEV_PHUB_TDMEM2_BASE, 0x40007810 +.set CYDEV_PHUB_TDMEM2_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM2_ORIG_TD0, 0x40007810 +.set CYDEV_PHUB_TDMEM2_ORIG_TD1, 0x40007814 +.set CYDEV_PHUB_TDMEM3_BASE, 0x40007818 +.set CYDEV_PHUB_TDMEM3_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM3_ORIG_TD0, 0x40007818 +.set CYDEV_PHUB_TDMEM3_ORIG_TD1, 0x4000781c +.set CYDEV_PHUB_TDMEM4_BASE, 0x40007820 +.set CYDEV_PHUB_TDMEM4_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM4_ORIG_TD0, 0x40007820 +.set CYDEV_PHUB_TDMEM4_ORIG_TD1, 0x40007824 +.set CYDEV_PHUB_TDMEM5_BASE, 0x40007828 +.set CYDEV_PHUB_TDMEM5_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM5_ORIG_TD0, 0x40007828 +.set CYDEV_PHUB_TDMEM5_ORIG_TD1, 0x4000782c +.set CYDEV_PHUB_TDMEM6_BASE, 0x40007830 +.set CYDEV_PHUB_TDMEM6_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM6_ORIG_TD0, 0x40007830 +.set CYDEV_PHUB_TDMEM6_ORIG_TD1, 0x40007834 +.set CYDEV_PHUB_TDMEM7_BASE, 0x40007838 +.set CYDEV_PHUB_TDMEM7_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM7_ORIG_TD0, 0x40007838 +.set CYDEV_PHUB_TDMEM7_ORIG_TD1, 0x4000783c +.set CYDEV_PHUB_TDMEM8_BASE, 0x40007840 +.set CYDEV_PHUB_TDMEM8_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM8_ORIG_TD0, 0x40007840 +.set CYDEV_PHUB_TDMEM8_ORIG_TD1, 0x40007844 +.set CYDEV_PHUB_TDMEM9_BASE, 0x40007848 +.set CYDEV_PHUB_TDMEM9_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM9_ORIG_TD0, 0x40007848 +.set CYDEV_PHUB_TDMEM9_ORIG_TD1, 0x4000784c +.set CYDEV_PHUB_TDMEM10_BASE, 0x40007850 +.set CYDEV_PHUB_TDMEM10_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM10_ORIG_TD0, 0x40007850 +.set CYDEV_PHUB_TDMEM10_ORIG_TD1, 0x40007854 +.set CYDEV_PHUB_TDMEM11_BASE, 0x40007858 +.set CYDEV_PHUB_TDMEM11_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM11_ORIG_TD0, 0x40007858 +.set CYDEV_PHUB_TDMEM11_ORIG_TD1, 0x4000785c +.set CYDEV_PHUB_TDMEM12_BASE, 0x40007860 +.set CYDEV_PHUB_TDMEM12_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM12_ORIG_TD0, 0x40007860 +.set CYDEV_PHUB_TDMEM12_ORIG_TD1, 0x40007864 +.set CYDEV_PHUB_TDMEM13_BASE, 0x40007868 +.set CYDEV_PHUB_TDMEM13_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM13_ORIG_TD0, 0x40007868 +.set CYDEV_PHUB_TDMEM13_ORIG_TD1, 0x4000786c +.set CYDEV_PHUB_TDMEM14_BASE, 0x40007870 +.set CYDEV_PHUB_TDMEM14_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM14_ORIG_TD0, 0x40007870 +.set CYDEV_PHUB_TDMEM14_ORIG_TD1, 0x40007874 +.set CYDEV_PHUB_TDMEM15_BASE, 0x40007878 +.set CYDEV_PHUB_TDMEM15_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM15_ORIG_TD0, 0x40007878 +.set CYDEV_PHUB_TDMEM15_ORIG_TD1, 0x4000787c +.set CYDEV_PHUB_TDMEM16_BASE, 0x40007880 +.set CYDEV_PHUB_TDMEM16_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM16_ORIG_TD0, 0x40007880 +.set CYDEV_PHUB_TDMEM16_ORIG_TD1, 0x40007884 +.set CYDEV_PHUB_TDMEM17_BASE, 0x40007888 +.set CYDEV_PHUB_TDMEM17_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM17_ORIG_TD0, 0x40007888 +.set CYDEV_PHUB_TDMEM17_ORIG_TD1, 0x4000788c +.set CYDEV_PHUB_TDMEM18_BASE, 0x40007890 +.set CYDEV_PHUB_TDMEM18_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM18_ORIG_TD0, 0x40007890 +.set CYDEV_PHUB_TDMEM18_ORIG_TD1, 0x40007894 +.set CYDEV_PHUB_TDMEM19_BASE, 0x40007898 +.set CYDEV_PHUB_TDMEM19_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM19_ORIG_TD0, 0x40007898 +.set CYDEV_PHUB_TDMEM19_ORIG_TD1, 0x4000789c +.set CYDEV_PHUB_TDMEM20_BASE, 0x400078a0 +.set CYDEV_PHUB_TDMEM20_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM20_ORIG_TD0, 0x400078a0 +.set CYDEV_PHUB_TDMEM20_ORIG_TD1, 0x400078a4 +.set CYDEV_PHUB_TDMEM21_BASE, 0x400078a8 +.set CYDEV_PHUB_TDMEM21_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM21_ORIG_TD0, 0x400078a8 +.set CYDEV_PHUB_TDMEM21_ORIG_TD1, 0x400078ac +.set CYDEV_PHUB_TDMEM22_BASE, 0x400078b0 +.set CYDEV_PHUB_TDMEM22_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM22_ORIG_TD0, 0x400078b0 +.set CYDEV_PHUB_TDMEM22_ORIG_TD1, 0x400078b4 +.set CYDEV_PHUB_TDMEM23_BASE, 0x400078b8 +.set CYDEV_PHUB_TDMEM23_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM23_ORIG_TD0, 0x400078b8 +.set CYDEV_PHUB_TDMEM23_ORIG_TD1, 0x400078bc +.set CYDEV_PHUB_TDMEM24_BASE, 0x400078c0 +.set CYDEV_PHUB_TDMEM24_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM24_ORIG_TD0, 0x400078c0 +.set CYDEV_PHUB_TDMEM24_ORIG_TD1, 0x400078c4 +.set CYDEV_PHUB_TDMEM25_BASE, 0x400078c8 +.set CYDEV_PHUB_TDMEM25_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM25_ORIG_TD0, 0x400078c8 +.set CYDEV_PHUB_TDMEM25_ORIG_TD1, 0x400078cc +.set CYDEV_PHUB_TDMEM26_BASE, 0x400078d0 +.set CYDEV_PHUB_TDMEM26_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM26_ORIG_TD0, 0x400078d0 +.set CYDEV_PHUB_TDMEM26_ORIG_TD1, 0x400078d4 +.set CYDEV_PHUB_TDMEM27_BASE, 0x400078d8 +.set CYDEV_PHUB_TDMEM27_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM27_ORIG_TD0, 0x400078d8 +.set CYDEV_PHUB_TDMEM27_ORIG_TD1, 0x400078dc +.set CYDEV_PHUB_TDMEM28_BASE, 0x400078e0 +.set CYDEV_PHUB_TDMEM28_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM28_ORIG_TD0, 0x400078e0 +.set CYDEV_PHUB_TDMEM28_ORIG_TD1, 0x400078e4 +.set CYDEV_PHUB_TDMEM29_BASE, 0x400078e8 +.set CYDEV_PHUB_TDMEM29_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM29_ORIG_TD0, 0x400078e8 +.set CYDEV_PHUB_TDMEM29_ORIG_TD1, 0x400078ec +.set CYDEV_PHUB_TDMEM30_BASE, 0x400078f0 +.set CYDEV_PHUB_TDMEM30_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM30_ORIG_TD0, 0x400078f0 +.set CYDEV_PHUB_TDMEM30_ORIG_TD1, 0x400078f4 +.set CYDEV_PHUB_TDMEM31_BASE, 0x400078f8 +.set CYDEV_PHUB_TDMEM31_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM31_ORIG_TD0, 0x400078f8 +.set CYDEV_PHUB_TDMEM31_ORIG_TD1, 0x400078fc +.set CYDEV_PHUB_TDMEM32_BASE, 0x40007900 +.set CYDEV_PHUB_TDMEM32_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM32_ORIG_TD0, 0x40007900 +.set CYDEV_PHUB_TDMEM32_ORIG_TD1, 0x40007904 +.set CYDEV_PHUB_TDMEM33_BASE, 0x40007908 +.set CYDEV_PHUB_TDMEM33_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM33_ORIG_TD0, 0x40007908 +.set CYDEV_PHUB_TDMEM33_ORIG_TD1, 0x4000790c +.set CYDEV_PHUB_TDMEM34_BASE, 0x40007910 +.set CYDEV_PHUB_TDMEM34_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM34_ORIG_TD0, 0x40007910 +.set CYDEV_PHUB_TDMEM34_ORIG_TD1, 0x40007914 +.set CYDEV_PHUB_TDMEM35_BASE, 0x40007918 +.set CYDEV_PHUB_TDMEM35_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM35_ORIG_TD0, 0x40007918 +.set CYDEV_PHUB_TDMEM35_ORIG_TD1, 0x4000791c +.set CYDEV_PHUB_TDMEM36_BASE, 0x40007920 +.set CYDEV_PHUB_TDMEM36_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM36_ORIG_TD0, 0x40007920 +.set CYDEV_PHUB_TDMEM36_ORIG_TD1, 0x40007924 +.set CYDEV_PHUB_TDMEM37_BASE, 0x40007928 +.set CYDEV_PHUB_TDMEM37_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM37_ORIG_TD0, 0x40007928 +.set CYDEV_PHUB_TDMEM37_ORIG_TD1, 0x4000792c +.set CYDEV_PHUB_TDMEM38_BASE, 0x40007930 +.set CYDEV_PHUB_TDMEM38_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM38_ORIG_TD0, 0x40007930 +.set CYDEV_PHUB_TDMEM38_ORIG_TD1, 0x40007934 +.set CYDEV_PHUB_TDMEM39_BASE, 0x40007938 +.set CYDEV_PHUB_TDMEM39_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM39_ORIG_TD0, 0x40007938 +.set CYDEV_PHUB_TDMEM39_ORIG_TD1, 0x4000793c +.set CYDEV_PHUB_TDMEM40_BASE, 0x40007940 +.set CYDEV_PHUB_TDMEM40_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM40_ORIG_TD0, 0x40007940 +.set CYDEV_PHUB_TDMEM40_ORIG_TD1, 0x40007944 +.set CYDEV_PHUB_TDMEM41_BASE, 0x40007948 +.set CYDEV_PHUB_TDMEM41_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM41_ORIG_TD0, 0x40007948 +.set CYDEV_PHUB_TDMEM41_ORIG_TD1, 0x4000794c +.set CYDEV_PHUB_TDMEM42_BASE, 0x40007950 +.set CYDEV_PHUB_TDMEM42_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM42_ORIG_TD0, 0x40007950 +.set CYDEV_PHUB_TDMEM42_ORIG_TD1, 0x40007954 +.set CYDEV_PHUB_TDMEM43_BASE, 0x40007958 +.set CYDEV_PHUB_TDMEM43_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM43_ORIG_TD0, 0x40007958 +.set CYDEV_PHUB_TDMEM43_ORIG_TD1, 0x4000795c +.set CYDEV_PHUB_TDMEM44_BASE, 0x40007960 +.set CYDEV_PHUB_TDMEM44_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM44_ORIG_TD0, 0x40007960 +.set CYDEV_PHUB_TDMEM44_ORIG_TD1, 0x40007964 +.set CYDEV_PHUB_TDMEM45_BASE, 0x40007968 +.set CYDEV_PHUB_TDMEM45_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM45_ORIG_TD0, 0x40007968 +.set CYDEV_PHUB_TDMEM45_ORIG_TD1, 0x4000796c +.set CYDEV_PHUB_TDMEM46_BASE, 0x40007970 +.set CYDEV_PHUB_TDMEM46_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM46_ORIG_TD0, 0x40007970 +.set CYDEV_PHUB_TDMEM46_ORIG_TD1, 0x40007974 +.set CYDEV_PHUB_TDMEM47_BASE, 0x40007978 +.set CYDEV_PHUB_TDMEM47_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM47_ORIG_TD0, 0x40007978 +.set CYDEV_PHUB_TDMEM47_ORIG_TD1, 0x4000797c +.set CYDEV_PHUB_TDMEM48_BASE, 0x40007980 +.set CYDEV_PHUB_TDMEM48_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM48_ORIG_TD0, 0x40007980 +.set CYDEV_PHUB_TDMEM48_ORIG_TD1, 0x40007984 +.set CYDEV_PHUB_TDMEM49_BASE, 0x40007988 +.set CYDEV_PHUB_TDMEM49_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM49_ORIG_TD0, 0x40007988 +.set CYDEV_PHUB_TDMEM49_ORIG_TD1, 0x4000798c +.set CYDEV_PHUB_TDMEM50_BASE, 0x40007990 +.set CYDEV_PHUB_TDMEM50_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM50_ORIG_TD0, 0x40007990 +.set CYDEV_PHUB_TDMEM50_ORIG_TD1, 0x40007994 +.set CYDEV_PHUB_TDMEM51_BASE, 0x40007998 +.set CYDEV_PHUB_TDMEM51_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM51_ORIG_TD0, 0x40007998 +.set CYDEV_PHUB_TDMEM51_ORIG_TD1, 0x4000799c +.set CYDEV_PHUB_TDMEM52_BASE, 0x400079a0 +.set CYDEV_PHUB_TDMEM52_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM52_ORIG_TD0, 0x400079a0 +.set CYDEV_PHUB_TDMEM52_ORIG_TD1, 0x400079a4 +.set CYDEV_PHUB_TDMEM53_BASE, 0x400079a8 +.set CYDEV_PHUB_TDMEM53_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM53_ORIG_TD0, 0x400079a8 +.set CYDEV_PHUB_TDMEM53_ORIG_TD1, 0x400079ac +.set CYDEV_PHUB_TDMEM54_BASE, 0x400079b0 +.set CYDEV_PHUB_TDMEM54_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM54_ORIG_TD0, 0x400079b0 +.set CYDEV_PHUB_TDMEM54_ORIG_TD1, 0x400079b4 +.set CYDEV_PHUB_TDMEM55_BASE, 0x400079b8 +.set CYDEV_PHUB_TDMEM55_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM55_ORIG_TD0, 0x400079b8 +.set CYDEV_PHUB_TDMEM55_ORIG_TD1, 0x400079bc +.set CYDEV_PHUB_TDMEM56_BASE, 0x400079c0 +.set CYDEV_PHUB_TDMEM56_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM56_ORIG_TD0, 0x400079c0 +.set CYDEV_PHUB_TDMEM56_ORIG_TD1, 0x400079c4 +.set CYDEV_PHUB_TDMEM57_BASE, 0x400079c8 +.set CYDEV_PHUB_TDMEM57_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM57_ORIG_TD0, 0x400079c8 +.set CYDEV_PHUB_TDMEM57_ORIG_TD1, 0x400079cc +.set CYDEV_PHUB_TDMEM58_BASE, 0x400079d0 +.set CYDEV_PHUB_TDMEM58_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM58_ORIG_TD0, 0x400079d0 +.set CYDEV_PHUB_TDMEM58_ORIG_TD1, 0x400079d4 +.set CYDEV_PHUB_TDMEM59_BASE, 0x400079d8 +.set CYDEV_PHUB_TDMEM59_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM59_ORIG_TD0, 0x400079d8 +.set CYDEV_PHUB_TDMEM59_ORIG_TD1, 0x400079dc +.set CYDEV_PHUB_TDMEM60_BASE, 0x400079e0 +.set CYDEV_PHUB_TDMEM60_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM60_ORIG_TD0, 0x400079e0 +.set CYDEV_PHUB_TDMEM60_ORIG_TD1, 0x400079e4 +.set CYDEV_PHUB_TDMEM61_BASE, 0x400079e8 +.set CYDEV_PHUB_TDMEM61_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM61_ORIG_TD0, 0x400079e8 +.set CYDEV_PHUB_TDMEM61_ORIG_TD1, 0x400079ec +.set CYDEV_PHUB_TDMEM62_BASE, 0x400079f0 +.set CYDEV_PHUB_TDMEM62_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM62_ORIG_TD0, 0x400079f0 +.set CYDEV_PHUB_TDMEM62_ORIG_TD1, 0x400079f4 +.set CYDEV_PHUB_TDMEM63_BASE, 0x400079f8 +.set CYDEV_PHUB_TDMEM63_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM63_ORIG_TD0, 0x400079f8 +.set CYDEV_PHUB_TDMEM63_ORIG_TD1, 0x400079fc +.set CYDEV_PHUB_TDMEM64_BASE, 0x40007a00 +.set CYDEV_PHUB_TDMEM64_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM64_ORIG_TD0, 0x40007a00 +.set CYDEV_PHUB_TDMEM64_ORIG_TD1, 0x40007a04 +.set CYDEV_PHUB_TDMEM65_BASE, 0x40007a08 +.set CYDEV_PHUB_TDMEM65_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM65_ORIG_TD0, 0x40007a08 +.set CYDEV_PHUB_TDMEM65_ORIG_TD1, 0x40007a0c +.set CYDEV_PHUB_TDMEM66_BASE, 0x40007a10 +.set CYDEV_PHUB_TDMEM66_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM66_ORIG_TD0, 0x40007a10 +.set CYDEV_PHUB_TDMEM66_ORIG_TD1, 0x40007a14 +.set CYDEV_PHUB_TDMEM67_BASE, 0x40007a18 +.set CYDEV_PHUB_TDMEM67_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM67_ORIG_TD0, 0x40007a18 +.set CYDEV_PHUB_TDMEM67_ORIG_TD1, 0x40007a1c +.set CYDEV_PHUB_TDMEM68_BASE, 0x40007a20 +.set CYDEV_PHUB_TDMEM68_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM68_ORIG_TD0, 0x40007a20 +.set CYDEV_PHUB_TDMEM68_ORIG_TD1, 0x40007a24 +.set CYDEV_PHUB_TDMEM69_BASE, 0x40007a28 +.set CYDEV_PHUB_TDMEM69_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM69_ORIG_TD0, 0x40007a28 +.set CYDEV_PHUB_TDMEM69_ORIG_TD1, 0x40007a2c +.set CYDEV_PHUB_TDMEM70_BASE, 0x40007a30 +.set CYDEV_PHUB_TDMEM70_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM70_ORIG_TD0, 0x40007a30 +.set CYDEV_PHUB_TDMEM70_ORIG_TD1, 0x40007a34 +.set CYDEV_PHUB_TDMEM71_BASE, 0x40007a38 +.set CYDEV_PHUB_TDMEM71_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM71_ORIG_TD0, 0x40007a38 +.set CYDEV_PHUB_TDMEM71_ORIG_TD1, 0x40007a3c +.set CYDEV_PHUB_TDMEM72_BASE, 0x40007a40 +.set CYDEV_PHUB_TDMEM72_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM72_ORIG_TD0, 0x40007a40 +.set CYDEV_PHUB_TDMEM72_ORIG_TD1, 0x40007a44 +.set CYDEV_PHUB_TDMEM73_BASE, 0x40007a48 +.set CYDEV_PHUB_TDMEM73_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM73_ORIG_TD0, 0x40007a48 +.set CYDEV_PHUB_TDMEM73_ORIG_TD1, 0x40007a4c +.set CYDEV_PHUB_TDMEM74_BASE, 0x40007a50 +.set CYDEV_PHUB_TDMEM74_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM74_ORIG_TD0, 0x40007a50 +.set CYDEV_PHUB_TDMEM74_ORIG_TD1, 0x40007a54 +.set CYDEV_PHUB_TDMEM75_BASE, 0x40007a58 +.set CYDEV_PHUB_TDMEM75_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM75_ORIG_TD0, 0x40007a58 +.set CYDEV_PHUB_TDMEM75_ORIG_TD1, 0x40007a5c +.set CYDEV_PHUB_TDMEM76_BASE, 0x40007a60 +.set CYDEV_PHUB_TDMEM76_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM76_ORIG_TD0, 0x40007a60 +.set CYDEV_PHUB_TDMEM76_ORIG_TD1, 0x40007a64 +.set CYDEV_PHUB_TDMEM77_BASE, 0x40007a68 +.set CYDEV_PHUB_TDMEM77_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM77_ORIG_TD0, 0x40007a68 +.set CYDEV_PHUB_TDMEM77_ORIG_TD1, 0x40007a6c +.set CYDEV_PHUB_TDMEM78_BASE, 0x40007a70 +.set CYDEV_PHUB_TDMEM78_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM78_ORIG_TD0, 0x40007a70 +.set CYDEV_PHUB_TDMEM78_ORIG_TD1, 0x40007a74 +.set CYDEV_PHUB_TDMEM79_BASE, 0x40007a78 +.set CYDEV_PHUB_TDMEM79_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM79_ORIG_TD0, 0x40007a78 +.set CYDEV_PHUB_TDMEM79_ORIG_TD1, 0x40007a7c +.set CYDEV_PHUB_TDMEM80_BASE, 0x40007a80 +.set CYDEV_PHUB_TDMEM80_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM80_ORIG_TD0, 0x40007a80 +.set CYDEV_PHUB_TDMEM80_ORIG_TD1, 0x40007a84 +.set CYDEV_PHUB_TDMEM81_BASE, 0x40007a88 +.set CYDEV_PHUB_TDMEM81_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM81_ORIG_TD0, 0x40007a88 +.set CYDEV_PHUB_TDMEM81_ORIG_TD1, 0x40007a8c +.set CYDEV_PHUB_TDMEM82_BASE, 0x40007a90 +.set CYDEV_PHUB_TDMEM82_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM82_ORIG_TD0, 0x40007a90 +.set CYDEV_PHUB_TDMEM82_ORIG_TD1, 0x40007a94 +.set CYDEV_PHUB_TDMEM83_BASE, 0x40007a98 +.set CYDEV_PHUB_TDMEM83_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM83_ORIG_TD0, 0x40007a98 +.set CYDEV_PHUB_TDMEM83_ORIG_TD1, 0x40007a9c +.set CYDEV_PHUB_TDMEM84_BASE, 0x40007aa0 +.set CYDEV_PHUB_TDMEM84_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM84_ORIG_TD0, 0x40007aa0 +.set CYDEV_PHUB_TDMEM84_ORIG_TD1, 0x40007aa4 +.set CYDEV_PHUB_TDMEM85_BASE, 0x40007aa8 +.set CYDEV_PHUB_TDMEM85_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM85_ORIG_TD0, 0x40007aa8 +.set CYDEV_PHUB_TDMEM85_ORIG_TD1, 0x40007aac +.set CYDEV_PHUB_TDMEM86_BASE, 0x40007ab0 +.set CYDEV_PHUB_TDMEM86_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM86_ORIG_TD0, 0x40007ab0 +.set CYDEV_PHUB_TDMEM86_ORIG_TD1, 0x40007ab4 +.set CYDEV_PHUB_TDMEM87_BASE, 0x40007ab8 +.set CYDEV_PHUB_TDMEM87_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM87_ORIG_TD0, 0x40007ab8 +.set CYDEV_PHUB_TDMEM87_ORIG_TD1, 0x40007abc +.set CYDEV_PHUB_TDMEM88_BASE, 0x40007ac0 +.set CYDEV_PHUB_TDMEM88_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM88_ORIG_TD0, 0x40007ac0 +.set CYDEV_PHUB_TDMEM88_ORIG_TD1, 0x40007ac4 +.set CYDEV_PHUB_TDMEM89_BASE, 0x40007ac8 +.set CYDEV_PHUB_TDMEM89_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM89_ORIG_TD0, 0x40007ac8 +.set CYDEV_PHUB_TDMEM89_ORIG_TD1, 0x40007acc +.set CYDEV_PHUB_TDMEM90_BASE, 0x40007ad0 +.set CYDEV_PHUB_TDMEM90_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM90_ORIG_TD0, 0x40007ad0 +.set CYDEV_PHUB_TDMEM90_ORIG_TD1, 0x40007ad4 +.set CYDEV_PHUB_TDMEM91_BASE, 0x40007ad8 +.set CYDEV_PHUB_TDMEM91_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM91_ORIG_TD0, 0x40007ad8 +.set CYDEV_PHUB_TDMEM91_ORIG_TD1, 0x40007adc +.set CYDEV_PHUB_TDMEM92_BASE, 0x40007ae0 +.set CYDEV_PHUB_TDMEM92_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM92_ORIG_TD0, 0x40007ae0 +.set CYDEV_PHUB_TDMEM92_ORIG_TD1, 0x40007ae4 +.set CYDEV_PHUB_TDMEM93_BASE, 0x40007ae8 +.set CYDEV_PHUB_TDMEM93_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM93_ORIG_TD0, 0x40007ae8 +.set CYDEV_PHUB_TDMEM93_ORIG_TD1, 0x40007aec +.set CYDEV_PHUB_TDMEM94_BASE, 0x40007af0 +.set CYDEV_PHUB_TDMEM94_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM94_ORIG_TD0, 0x40007af0 +.set CYDEV_PHUB_TDMEM94_ORIG_TD1, 0x40007af4 +.set CYDEV_PHUB_TDMEM95_BASE, 0x40007af8 +.set CYDEV_PHUB_TDMEM95_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM95_ORIG_TD0, 0x40007af8 +.set CYDEV_PHUB_TDMEM95_ORIG_TD1, 0x40007afc +.set CYDEV_PHUB_TDMEM96_BASE, 0x40007b00 +.set CYDEV_PHUB_TDMEM96_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM96_ORIG_TD0, 0x40007b00 +.set CYDEV_PHUB_TDMEM96_ORIG_TD1, 0x40007b04 +.set CYDEV_PHUB_TDMEM97_BASE, 0x40007b08 +.set CYDEV_PHUB_TDMEM97_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM97_ORIG_TD0, 0x40007b08 +.set CYDEV_PHUB_TDMEM97_ORIG_TD1, 0x40007b0c +.set CYDEV_PHUB_TDMEM98_BASE, 0x40007b10 +.set CYDEV_PHUB_TDMEM98_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM98_ORIG_TD0, 0x40007b10 +.set CYDEV_PHUB_TDMEM98_ORIG_TD1, 0x40007b14 +.set CYDEV_PHUB_TDMEM99_BASE, 0x40007b18 +.set CYDEV_PHUB_TDMEM99_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM99_ORIG_TD0, 0x40007b18 +.set CYDEV_PHUB_TDMEM99_ORIG_TD1, 0x40007b1c +.set CYDEV_PHUB_TDMEM100_BASE, 0x40007b20 +.set CYDEV_PHUB_TDMEM100_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM100_ORIG_TD0, 0x40007b20 +.set CYDEV_PHUB_TDMEM100_ORIG_TD1, 0x40007b24 +.set CYDEV_PHUB_TDMEM101_BASE, 0x40007b28 +.set CYDEV_PHUB_TDMEM101_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM101_ORIG_TD0, 0x40007b28 +.set CYDEV_PHUB_TDMEM101_ORIG_TD1, 0x40007b2c +.set CYDEV_PHUB_TDMEM102_BASE, 0x40007b30 +.set CYDEV_PHUB_TDMEM102_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM102_ORIG_TD0, 0x40007b30 +.set CYDEV_PHUB_TDMEM102_ORIG_TD1, 0x40007b34 +.set CYDEV_PHUB_TDMEM103_BASE, 0x40007b38 +.set CYDEV_PHUB_TDMEM103_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM103_ORIG_TD0, 0x40007b38 +.set CYDEV_PHUB_TDMEM103_ORIG_TD1, 0x40007b3c +.set CYDEV_PHUB_TDMEM104_BASE, 0x40007b40 +.set CYDEV_PHUB_TDMEM104_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM104_ORIG_TD0, 0x40007b40 +.set CYDEV_PHUB_TDMEM104_ORIG_TD1, 0x40007b44 +.set CYDEV_PHUB_TDMEM105_BASE, 0x40007b48 +.set CYDEV_PHUB_TDMEM105_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM105_ORIG_TD0, 0x40007b48 +.set CYDEV_PHUB_TDMEM105_ORIG_TD1, 0x40007b4c +.set CYDEV_PHUB_TDMEM106_BASE, 0x40007b50 +.set CYDEV_PHUB_TDMEM106_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM106_ORIG_TD0, 0x40007b50 +.set CYDEV_PHUB_TDMEM106_ORIG_TD1, 0x40007b54 +.set CYDEV_PHUB_TDMEM107_BASE, 0x40007b58 +.set CYDEV_PHUB_TDMEM107_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM107_ORIG_TD0, 0x40007b58 +.set CYDEV_PHUB_TDMEM107_ORIG_TD1, 0x40007b5c +.set CYDEV_PHUB_TDMEM108_BASE, 0x40007b60 +.set CYDEV_PHUB_TDMEM108_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM108_ORIG_TD0, 0x40007b60 +.set CYDEV_PHUB_TDMEM108_ORIG_TD1, 0x40007b64 +.set CYDEV_PHUB_TDMEM109_BASE, 0x40007b68 +.set CYDEV_PHUB_TDMEM109_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM109_ORIG_TD0, 0x40007b68 +.set CYDEV_PHUB_TDMEM109_ORIG_TD1, 0x40007b6c +.set CYDEV_PHUB_TDMEM110_BASE, 0x40007b70 +.set CYDEV_PHUB_TDMEM110_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM110_ORIG_TD0, 0x40007b70 +.set CYDEV_PHUB_TDMEM110_ORIG_TD1, 0x40007b74 +.set CYDEV_PHUB_TDMEM111_BASE, 0x40007b78 +.set CYDEV_PHUB_TDMEM111_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM111_ORIG_TD0, 0x40007b78 +.set CYDEV_PHUB_TDMEM111_ORIG_TD1, 0x40007b7c +.set CYDEV_PHUB_TDMEM112_BASE, 0x40007b80 +.set CYDEV_PHUB_TDMEM112_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM112_ORIG_TD0, 0x40007b80 +.set CYDEV_PHUB_TDMEM112_ORIG_TD1, 0x40007b84 +.set CYDEV_PHUB_TDMEM113_BASE, 0x40007b88 +.set CYDEV_PHUB_TDMEM113_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM113_ORIG_TD0, 0x40007b88 +.set CYDEV_PHUB_TDMEM113_ORIG_TD1, 0x40007b8c +.set CYDEV_PHUB_TDMEM114_BASE, 0x40007b90 +.set CYDEV_PHUB_TDMEM114_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM114_ORIG_TD0, 0x40007b90 +.set CYDEV_PHUB_TDMEM114_ORIG_TD1, 0x40007b94 +.set CYDEV_PHUB_TDMEM115_BASE, 0x40007b98 +.set CYDEV_PHUB_TDMEM115_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM115_ORIG_TD0, 0x40007b98 +.set CYDEV_PHUB_TDMEM115_ORIG_TD1, 0x40007b9c +.set CYDEV_PHUB_TDMEM116_BASE, 0x40007ba0 +.set CYDEV_PHUB_TDMEM116_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM116_ORIG_TD0, 0x40007ba0 +.set CYDEV_PHUB_TDMEM116_ORIG_TD1, 0x40007ba4 +.set CYDEV_PHUB_TDMEM117_BASE, 0x40007ba8 +.set CYDEV_PHUB_TDMEM117_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM117_ORIG_TD0, 0x40007ba8 +.set CYDEV_PHUB_TDMEM117_ORIG_TD1, 0x40007bac +.set CYDEV_PHUB_TDMEM118_BASE, 0x40007bb0 +.set CYDEV_PHUB_TDMEM118_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM118_ORIG_TD0, 0x40007bb0 +.set CYDEV_PHUB_TDMEM118_ORIG_TD1, 0x40007bb4 +.set CYDEV_PHUB_TDMEM119_BASE, 0x40007bb8 +.set CYDEV_PHUB_TDMEM119_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM119_ORIG_TD0, 0x40007bb8 +.set CYDEV_PHUB_TDMEM119_ORIG_TD1, 0x40007bbc +.set CYDEV_PHUB_TDMEM120_BASE, 0x40007bc0 +.set CYDEV_PHUB_TDMEM120_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM120_ORIG_TD0, 0x40007bc0 +.set CYDEV_PHUB_TDMEM120_ORIG_TD1, 0x40007bc4 +.set CYDEV_PHUB_TDMEM121_BASE, 0x40007bc8 +.set CYDEV_PHUB_TDMEM121_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM121_ORIG_TD0, 0x40007bc8 +.set CYDEV_PHUB_TDMEM121_ORIG_TD1, 0x40007bcc +.set CYDEV_PHUB_TDMEM122_BASE, 0x40007bd0 +.set CYDEV_PHUB_TDMEM122_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM122_ORIG_TD0, 0x40007bd0 +.set CYDEV_PHUB_TDMEM122_ORIG_TD1, 0x40007bd4 +.set CYDEV_PHUB_TDMEM123_BASE, 0x40007bd8 +.set CYDEV_PHUB_TDMEM123_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM123_ORIG_TD0, 0x40007bd8 +.set CYDEV_PHUB_TDMEM123_ORIG_TD1, 0x40007bdc +.set CYDEV_PHUB_TDMEM124_BASE, 0x40007be0 +.set CYDEV_PHUB_TDMEM124_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM124_ORIG_TD0, 0x40007be0 +.set CYDEV_PHUB_TDMEM124_ORIG_TD1, 0x40007be4 +.set CYDEV_PHUB_TDMEM125_BASE, 0x40007be8 +.set CYDEV_PHUB_TDMEM125_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM125_ORIG_TD0, 0x40007be8 +.set CYDEV_PHUB_TDMEM125_ORIG_TD1, 0x40007bec +.set CYDEV_PHUB_TDMEM126_BASE, 0x40007bf0 +.set CYDEV_PHUB_TDMEM126_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM126_ORIG_TD0, 0x40007bf0 +.set CYDEV_PHUB_TDMEM126_ORIG_TD1, 0x40007bf4 +.set CYDEV_PHUB_TDMEM127_BASE, 0x40007bf8 +.set CYDEV_PHUB_TDMEM127_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM127_ORIG_TD0, 0x40007bf8 +.set CYDEV_PHUB_TDMEM127_ORIG_TD1, 0x40007bfc +.set CYDEV_EE_BASE, 0x40008000 +.set CYDEV_EE_SIZE, 0x00000800 +.set CYDEV_EE_DATA_MBASE, 0x40008000 +.set CYDEV_EE_DATA_MSIZE, 0x00000800 +.set CYDEV_CAN0_BASE, 0x4000a000 +.set CYDEV_CAN0_SIZE, 0x000002a0 +.set CYDEV_CAN0_CSR_BASE, 0x4000a000 +.set CYDEV_CAN0_CSR_SIZE, 0x00000018 +.set CYDEV_CAN0_CSR_INT_SR, 0x4000a000 +.set CYDEV_CAN0_CSR_INT_EN, 0x4000a004 +.set CYDEV_CAN0_CSR_BUF_SR, 0x4000a008 +.set CYDEV_CAN0_CSR_ERR_SR, 0x4000a00c +.set CYDEV_CAN0_CSR_CMD, 0x4000a010 +.set CYDEV_CAN0_CSR_CFG, 0x4000a014 +.set CYDEV_CAN0_TX0_BASE, 0x4000a020 +.set CYDEV_CAN0_TX0_SIZE, 0x00000010 +.set CYDEV_CAN0_TX0_CMD, 0x4000a020 +.set CYDEV_CAN0_TX0_ID, 0x4000a024 +.set CYDEV_CAN0_TX0_DH, 0x4000a028 +.set CYDEV_CAN0_TX0_DL, 0x4000a02c +.set CYDEV_CAN0_TX1_BASE, 0x4000a030 +.set CYDEV_CAN0_TX1_SIZE, 0x00000010 +.set CYDEV_CAN0_TX1_CMD, 0x4000a030 +.set CYDEV_CAN0_TX1_ID, 0x4000a034 +.set CYDEV_CAN0_TX1_DH, 0x4000a038 +.set CYDEV_CAN0_TX1_DL, 0x4000a03c +.set CYDEV_CAN0_TX2_BASE, 0x4000a040 +.set CYDEV_CAN0_TX2_SIZE, 0x00000010 +.set CYDEV_CAN0_TX2_CMD, 0x4000a040 +.set CYDEV_CAN0_TX2_ID, 0x4000a044 +.set CYDEV_CAN0_TX2_DH, 0x4000a048 +.set CYDEV_CAN0_TX2_DL, 0x4000a04c +.set CYDEV_CAN0_TX3_BASE, 0x4000a050 +.set CYDEV_CAN0_TX3_SIZE, 0x00000010 +.set CYDEV_CAN0_TX3_CMD, 0x4000a050 +.set CYDEV_CAN0_TX3_ID, 0x4000a054 +.set CYDEV_CAN0_TX3_DH, 0x4000a058 +.set CYDEV_CAN0_TX3_DL, 0x4000a05c +.set CYDEV_CAN0_TX4_BASE, 0x4000a060 +.set CYDEV_CAN0_TX4_SIZE, 0x00000010 +.set CYDEV_CAN0_TX4_CMD, 0x4000a060 +.set CYDEV_CAN0_TX4_ID, 0x4000a064 +.set CYDEV_CAN0_TX4_DH, 0x4000a068 +.set CYDEV_CAN0_TX4_DL, 0x4000a06c +.set CYDEV_CAN0_TX5_BASE, 0x4000a070 +.set CYDEV_CAN0_TX5_SIZE, 0x00000010 +.set CYDEV_CAN0_TX5_CMD, 0x4000a070 +.set CYDEV_CAN0_TX5_ID, 0x4000a074 +.set CYDEV_CAN0_TX5_DH, 0x4000a078 +.set CYDEV_CAN0_TX5_DL, 0x4000a07c +.set CYDEV_CAN0_TX6_BASE, 0x4000a080 +.set CYDEV_CAN0_TX6_SIZE, 0x00000010 +.set CYDEV_CAN0_TX6_CMD, 0x4000a080 +.set CYDEV_CAN0_TX6_ID, 0x4000a084 +.set CYDEV_CAN0_TX6_DH, 0x4000a088 +.set CYDEV_CAN0_TX6_DL, 0x4000a08c +.set CYDEV_CAN0_TX7_BASE, 0x4000a090 +.set CYDEV_CAN0_TX7_SIZE, 0x00000010 +.set CYDEV_CAN0_TX7_CMD, 0x4000a090 +.set CYDEV_CAN0_TX7_ID, 0x4000a094 +.set CYDEV_CAN0_TX7_DH, 0x4000a098 +.set CYDEV_CAN0_TX7_DL, 0x4000a09c +.set CYDEV_CAN0_RX0_BASE, 0x4000a0a0 +.set CYDEV_CAN0_RX0_SIZE, 0x00000020 +.set CYDEV_CAN0_RX0_CMD, 0x4000a0a0 +.set CYDEV_CAN0_RX0_ID, 0x4000a0a4 +.set CYDEV_CAN0_RX0_DH, 0x4000a0a8 +.set CYDEV_CAN0_RX0_DL, 0x4000a0ac +.set CYDEV_CAN0_RX0_AMR, 0x4000a0b0 +.set CYDEV_CAN0_RX0_ACR, 0x4000a0b4 +.set CYDEV_CAN0_RX0_AMRD, 0x4000a0b8 +.set CYDEV_CAN0_RX0_ACRD, 0x4000a0bc +.set CYDEV_CAN0_RX1_BASE, 0x4000a0c0 +.set CYDEV_CAN0_RX1_SIZE, 0x00000020 +.set CYDEV_CAN0_RX1_CMD, 0x4000a0c0 +.set CYDEV_CAN0_RX1_ID, 0x4000a0c4 +.set CYDEV_CAN0_RX1_DH, 0x4000a0c8 +.set CYDEV_CAN0_RX1_DL, 0x4000a0cc +.set CYDEV_CAN0_RX1_AMR, 0x4000a0d0 +.set CYDEV_CAN0_RX1_ACR, 0x4000a0d4 +.set CYDEV_CAN0_RX1_AMRD, 0x4000a0d8 +.set CYDEV_CAN0_RX1_ACRD, 0x4000a0dc +.set CYDEV_CAN0_RX2_BASE, 0x4000a0e0 +.set CYDEV_CAN0_RX2_SIZE, 0x00000020 +.set CYDEV_CAN0_RX2_CMD, 0x4000a0e0 +.set CYDEV_CAN0_RX2_ID, 0x4000a0e4 +.set CYDEV_CAN0_RX2_DH, 0x4000a0e8 +.set CYDEV_CAN0_RX2_DL, 0x4000a0ec +.set CYDEV_CAN0_RX2_AMR, 0x4000a0f0 +.set CYDEV_CAN0_RX2_ACR, 0x4000a0f4 +.set CYDEV_CAN0_RX2_AMRD, 0x4000a0f8 +.set CYDEV_CAN0_RX2_ACRD, 0x4000a0fc +.set CYDEV_CAN0_RX3_BASE, 0x4000a100 +.set CYDEV_CAN0_RX3_SIZE, 0x00000020 +.set CYDEV_CAN0_RX3_CMD, 0x4000a100 +.set CYDEV_CAN0_RX3_ID, 0x4000a104 +.set CYDEV_CAN0_RX3_DH, 0x4000a108 +.set CYDEV_CAN0_RX3_DL, 0x4000a10c +.set CYDEV_CAN0_RX3_AMR, 0x4000a110 +.set CYDEV_CAN0_RX3_ACR, 0x4000a114 +.set CYDEV_CAN0_RX3_AMRD, 0x4000a118 +.set CYDEV_CAN0_RX3_ACRD, 0x4000a11c +.set CYDEV_CAN0_RX4_BASE, 0x4000a120 +.set CYDEV_CAN0_RX4_SIZE, 0x00000020 +.set CYDEV_CAN0_RX4_CMD, 0x4000a120 +.set CYDEV_CAN0_RX4_ID, 0x4000a124 +.set CYDEV_CAN0_RX4_DH, 0x4000a128 +.set CYDEV_CAN0_RX4_DL, 0x4000a12c +.set CYDEV_CAN0_RX4_AMR, 0x4000a130 +.set CYDEV_CAN0_RX4_ACR, 0x4000a134 +.set CYDEV_CAN0_RX4_AMRD, 0x4000a138 +.set CYDEV_CAN0_RX4_ACRD, 0x4000a13c +.set CYDEV_CAN0_RX5_BASE, 0x4000a140 +.set CYDEV_CAN0_RX5_SIZE, 0x00000020 +.set CYDEV_CAN0_RX5_CMD, 0x4000a140 +.set CYDEV_CAN0_RX5_ID, 0x4000a144 +.set CYDEV_CAN0_RX5_DH, 0x4000a148 +.set CYDEV_CAN0_RX5_DL, 0x4000a14c +.set CYDEV_CAN0_RX5_AMR, 0x4000a150 +.set CYDEV_CAN0_RX5_ACR, 0x4000a154 +.set CYDEV_CAN0_RX5_AMRD, 0x4000a158 +.set CYDEV_CAN0_RX5_ACRD, 0x4000a15c +.set CYDEV_CAN0_RX6_BASE, 0x4000a160 +.set CYDEV_CAN0_RX6_SIZE, 0x00000020 +.set CYDEV_CAN0_RX6_CMD, 0x4000a160 +.set CYDEV_CAN0_RX6_ID, 0x4000a164 +.set CYDEV_CAN0_RX6_DH, 0x4000a168 +.set CYDEV_CAN0_RX6_DL, 0x4000a16c +.set CYDEV_CAN0_RX6_AMR, 0x4000a170 +.set CYDEV_CAN0_RX6_ACR, 0x4000a174 +.set CYDEV_CAN0_RX6_AMRD, 0x4000a178 +.set CYDEV_CAN0_RX6_ACRD, 0x4000a17c +.set CYDEV_CAN0_RX7_BASE, 0x4000a180 +.set CYDEV_CAN0_RX7_SIZE, 0x00000020 +.set CYDEV_CAN0_RX7_CMD, 0x4000a180 +.set CYDEV_CAN0_RX7_ID, 0x4000a184 +.set CYDEV_CAN0_RX7_DH, 0x4000a188 +.set CYDEV_CAN0_RX7_DL, 0x4000a18c +.set CYDEV_CAN0_RX7_AMR, 0x4000a190 +.set CYDEV_CAN0_RX7_ACR, 0x4000a194 +.set CYDEV_CAN0_RX7_AMRD, 0x4000a198 +.set CYDEV_CAN0_RX7_ACRD, 0x4000a19c +.set CYDEV_CAN0_RX8_BASE, 0x4000a1a0 +.set CYDEV_CAN0_RX8_SIZE, 0x00000020 +.set CYDEV_CAN0_RX8_CMD, 0x4000a1a0 +.set CYDEV_CAN0_RX8_ID, 0x4000a1a4 +.set CYDEV_CAN0_RX8_DH, 0x4000a1a8 +.set CYDEV_CAN0_RX8_DL, 0x4000a1ac +.set CYDEV_CAN0_RX8_AMR, 0x4000a1b0 +.set CYDEV_CAN0_RX8_ACR, 0x4000a1b4 +.set CYDEV_CAN0_RX8_AMRD, 0x4000a1b8 +.set CYDEV_CAN0_RX8_ACRD, 0x4000a1bc +.set CYDEV_CAN0_RX9_BASE, 0x4000a1c0 +.set CYDEV_CAN0_RX9_SIZE, 0x00000020 +.set CYDEV_CAN0_RX9_CMD, 0x4000a1c0 +.set CYDEV_CAN0_RX9_ID, 0x4000a1c4 +.set CYDEV_CAN0_RX9_DH, 0x4000a1c8 +.set CYDEV_CAN0_RX9_DL, 0x4000a1cc +.set CYDEV_CAN0_RX9_AMR, 0x4000a1d0 +.set CYDEV_CAN0_RX9_ACR, 0x4000a1d4 +.set CYDEV_CAN0_RX9_AMRD, 0x4000a1d8 +.set CYDEV_CAN0_RX9_ACRD, 0x4000a1dc +.set CYDEV_CAN0_RX10_BASE, 0x4000a1e0 +.set CYDEV_CAN0_RX10_SIZE, 0x00000020 +.set CYDEV_CAN0_RX10_CMD, 0x4000a1e0 +.set CYDEV_CAN0_RX10_ID, 0x4000a1e4 +.set CYDEV_CAN0_RX10_DH, 0x4000a1e8 +.set CYDEV_CAN0_RX10_DL, 0x4000a1ec +.set CYDEV_CAN0_RX10_AMR, 0x4000a1f0 +.set CYDEV_CAN0_RX10_ACR, 0x4000a1f4 +.set CYDEV_CAN0_RX10_AMRD, 0x4000a1f8 +.set CYDEV_CAN0_RX10_ACRD, 0x4000a1fc +.set CYDEV_CAN0_RX11_BASE, 0x4000a200 +.set CYDEV_CAN0_RX11_SIZE, 0x00000020 +.set CYDEV_CAN0_RX11_CMD, 0x4000a200 +.set CYDEV_CAN0_RX11_ID, 0x4000a204 +.set CYDEV_CAN0_RX11_DH, 0x4000a208 +.set CYDEV_CAN0_RX11_DL, 0x4000a20c +.set CYDEV_CAN0_RX11_AMR, 0x4000a210 +.set CYDEV_CAN0_RX11_ACR, 0x4000a214 +.set CYDEV_CAN0_RX11_AMRD, 0x4000a218 +.set CYDEV_CAN0_RX11_ACRD, 0x4000a21c +.set CYDEV_CAN0_RX12_BASE, 0x4000a220 +.set CYDEV_CAN0_RX12_SIZE, 0x00000020 +.set CYDEV_CAN0_RX12_CMD, 0x4000a220 +.set CYDEV_CAN0_RX12_ID, 0x4000a224 +.set CYDEV_CAN0_RX12_DH, 0x4000a228 +.set CYDEV_CAN0_RX12_DL, 0x4000a22c +.set CYDEV_CAN0_RX12_AMR, 0x4000a230 +.set CYDEV_CAN0_RX12_ACR, 0x4000a234 +.set CYDEV_CAN0_RX12_AMRD, 0x4000a238 +.set CYDEV_CAN0_RX12_ACRD, 0x4000a23c +.set CYDEV_CAN0_RX13_BASE, 0x4000a240 +.set CYDEV_CAN0_RX13_SIZE, 0x00000020 +.set CYDEV_CAN0_RX13_CMD, 0x4000a240 +.set CYDEV_CAN0_RX13_ID, 0x4000a244 +.set CYDEV_CAN0_RX13_DH, 0x4000a248 +.set CYDEV_CAN0_RX13_DL, 0x4000a24c +.set CYDEV_CAN0_RX13_AMR, 0x4000a250 +.set CYDEV_CAN0_RX13_ACR, 0x4000a254 +.set CYDEV_CAN0_RX13_AMRD, 0x4000a258 +.set CYDEV_CAN0_RX13_ACRD, 0x4000a25c +.set CYDEV_CAN0_RX14_BASE, 0x4000a260 +.set CYDEV_CAN0_RX14_SIZE, 0x00000020 +.set CYDEV_CAN0_RX14_CMD, 0x4000a260 +.set CYDEV_CAN0_RX14_ID, 0x4000a264 +.set CYDEV_CAN0_RX14_DH, 0x4000a268 +.set CYDEV_CAN0_RX14_DL, 0x4000a26c +.set CYDEV_CAN0_RX14_AMR, 0x4000a270 +.set CYDEV_CAN0_RX14_ACR, 0x4000a274 +.set CYDEV_CAN0_RX14_AMRD, 0x4000a278 +.set CYDEV_CAN0_RX14_ACRD, 0x4000a27c +.set CYDEV_CAN0_RX15_BASE, 0x4000a280 +.set CYDEV_CAN0_RX15_SIZE, 0x00000020 +.set CYDEV_CAN0_RX15_CMD, 0x4000a280 +.set CYDEV_CAN0_RX15_ID, 0x4000a284 +.set CYDEV_CAN0_RX15_DH, 0x4000a288 +.set CYDEV_CAN0_RX15_DL, 0x4000a28c +.set CYDEV_CAN0_RX15_AMR, 0x4000a290 +.set CYDEV_CAN0_RX15_ACR, 0x4000a294 +.set CYDEV_CAN0_RX15_AMRD, 0x4000a298 +.set CYDEV_CAN0_RX15_ACRD, 0x4000a29c +.set CYDEV_DFB0_BASE, 0x4000c000 +.set CYDEV_DFB0_SIZE, 0x000007b5 +.set CYDEV_DFB0_DPA_SRAM_BASE, 0x4000c000 +.set CYDEV_DFB0_DPA_SRAM_SIZE, 0x00000200 +.set CYDEV_DFB0_DPA_SRAM_DATA_MBASE, 0x4000c000 +.set CYDEV_DFB0_DPA_SRAM_DATA_MSIZE, 0x00000200 +.set CYDEV_DFB0_DPB_SRAM_BASE, 0x4000c200 +.set CYDEV_DFB0_DPB_SRAM_SIZE, 0x00000200 +.set CYDEV_DFB0_DPB_SRAM_DATA_MBASE, 0x4000c200 +.set CYDEV_DFB0_DPB_SRAM_DATA_MSIZE, 0x00000200 +.set CYDEV_DFB0_CSA_SRAM_BASE, 0x4000c400 +.set CYDEV_DFB0_CSA_SRAM_SIZE, 0x00000100 +.set CYDEV_DFB0_CSA_SRAM_DATA_MBASE, 0x4000c400 +.set CYDEV_DFB0_CSA_SRAM_DATA_MSIZE, 0x00000100 +.set CYDEV_DFB0_CSB_SRAM_BASE, 0x4000c500 +.set CYDEV_DFB0_CSB_SRAM_SIZE, 0x00000100 +.set CYDEV_DFB0_CSB_SRAM_DATA_MBASE, 0x4000c500 +.set CYDEV_DFB0_CSB_SRAM_DATA_MSIZE, 0x00000100 +.set CYDEV_DFB0_FSM_SRAM_BASE, 0x4000c600 +.set CYDEV_DFB0_FSM_SRAM_SIZE, 0x00000100 +.set CYDEV_DFB0_FSM_SRAM_DATA_MBASE, 0x4000c600 +.set CYDEV_DFB0_FSM_SRAM_DATA_MSIZE, 0x00000100 +.set CYDEV_DFB0_ACU_SRAM_BASE, 0x4000c700 +.set CYDEV_DFB0_ACU_SRAM_SIZE, 0x00000040 +.set CYDEV_DFB0_ACU_SRAM_DATA_MBASE, 0x4000c700 +.set CYDEV_DFB0_ACU_SRAM_DATA_MSIZE, 0x00000040 +.set CYDEV_DFB0_CR, 0x4000c780 +.set CYDEV_DFB0_SR, 0x4000c784 +.set CYDEV_DFB0_RAM_EN, 0x4000c788 +.set CYDEV_DFB0_RAM_DIR, 0x4000c78c +.set CYDEV_DFB0_SEMA, 0x4000c790 +.set CYDEV_DFB0_DSI_CTRL, 0x4000c794 +.set CYDEV_DFB0_INT_CTRL, 0x4000c798 +.set CYDEV_DFB0_DMA_CTRL, 0x4000c79c +.set CYDEV_DFB0_STAGEA, 0x4000c7a0 +.set CYDEV_DFB0_STAGEAM, 0x4000c7a1 +.set CYDEV_DFB0_STAGEAH, 0x4000c7a2 +.set CYDEV_DFB0_STAGEB, 0x4000c7a4 +.set CYDEV_DFB0_STAGEBM, 0x4000c7a5 +.set CYDEV_DFB0_STAGEBH, 0x4000c7a6 +.set CYDEV_DFB0_HOLDA, 0x4000c7a8 +.set CYDEV_DFB0_HOLDAM, 0x4000c7a9 +.set CYDEV_DFB0_HOLDAH, 0x4000c7aa +.set CYDEV_DFB0_HOLDAS, 0x4000c7ab +.set CYDEV_DFB0_HOLDB, 0x4000c7ac +.set CYDEV_DFB0_HOLDBM, 0x4000c7ad +.set CYDEV_DFB0_HOLDBH, 0x4000c7ae +.set CYDEV_DFB0_HOLDBS, 0x4000c7af +.set CYDEV_DFB0_COHER, 0x4000c7b0 +.set CYDEV_DFB0_DALIGN, 0x4000c7b4 +.set CYDEV_UCFG_BASE, 0x40010000 +.set CYDEV_UCFG_SIZE, 0x00005040 +.set CYDEV_UCFG_B0_BASE, 0x40010000 +.set CYDEV_UCFG_B0_SIZE, 0x00000fef +.set CYDEV_UCFG_B0_P0_BASE, 0x40010000 +.set CYDEV_UCFG_B0_P0_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P0_U0_BASE, 0x40010000 +.set CYDEV_UCFG_B0_P0_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT0, 0x40010000 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT1, 0x40010004 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT2, 0x40010008 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT3, 0x4001000c +.set CYDEV_UCFG_B0_P0_U0_PLD_IT4, 0x40010010 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT5, 0x40010014 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT6, 0x40010018 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT7, 0x4001001c +.set CYDEV_UCFG_B0_P0_U0_PLD_IT8, 0x40010020 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT9, 0x40010024 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT10, 0x40010028 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT11, 0x4001002c +.set CYDEV_UCFG_B0_P0_U0_PLD_ORT0, 0x40010030 +.set CYDEV_UCFG_B0_P0_U0_PLD_ORT1, 0x40010032 +.set CYDEV_UCFG_B0_P0_U0_PLD_ORT2, 0x40010034 +.set CYDEV_UCFG_B0_P0_U0_PLD_ORT3, 0x40010036 +.set CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST, 0x40010038 +.set CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB, 0x4001003a +.set CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET, 0x4001003c +.set CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS, 0x4001003e +.set CYDEV_UCFG_B0_P0_U0_CFG0, 0x40010040 +.set CYDEV_UCFG_B0_P0_U0_CFG1, 0x40010041 +.set CYDEV_UCFG_B0_P0_U0_CFG2, 0x40010042 +.set CYDEV_UCFG_B0_P0_U0_CFG3, 0x40010043 +.set CYDEV_UCFG_B0_P0_U0_CFG4, 0x40010044 +.set CYDEV_UCFG_B0_P0_U0_CFG5, 0x40010045 +.set CYDEV_UCFG_B0_P0_U0_CFG6, 0x40010046 +.set CYDEV_UCFG_B0_P0_U0_CFG7, 0x40010047 +.set CYDEV_UCFG_B0_P0_U0_CFG8, 0x40010048 +.set CYDEV_UCFG_B0_P0_U0_CFG9, 0x40010049 +.set CYDEV_UCFG_B0_P0_U0_CFG10, 0x4001004a +.set CYDEV_UCFG_B0_P0_U0_CFG11, 0x4001004b +.set CYDEV_UCFG_B0_P0_U0_CFG12, 0x4001004c +.set CYDEV_UCFG_B0_P0_U0_CFG13, 0x4001004d +.set CYDEV_UCFG_B0_P0_U0_CFG14, 0x4001004e +.set CYDEV_UCFG_B0_P0_U0_CFG15, 0x4001004f +.set CYDEV_UCFG_B0_P0_U0_CFG16, 0x40010050 +.set CYDEV_UCFG_B0_P0_U0_CFG17, 0x40010051 +.set CYDEV_UCFG_B0_P0_U0_CFG18, 0x40010052 +.set CYDEV_UCFG_B0_P0_U0_CFG19, 0x40010053 +.set CYDEV_UCFG_B0_P0_U0_CFG20, 0x40010054 +.set CYDEV_UCFG_B0_P0_U0_CFG21, 0x40010055 +.set CYDEV_UCFG_B0_P0_U0_CFG22, 0x40010056 +.set CYDEV_UCFG_B0_P0_U0_CFG23, 0x40010057 +.set CYDEV_UCFG_B0_P0_U0_CFG24, 0x40010058 +.set CYDEV_UCFG_B0_P0_U0_CFG25, 0x40010059 +.set CYDEV_UCFG_B0_P0_U0_CFG26, 0x4001005a +.set CYDEV_UCFG_B0_P0_U0_CFG27, 0x4001005b +.set CYDEV_UCFG_B0_P0_U0_CFG28, 0x4001005c +.set CYDEV_UCFG_B0_P0_U0_CFG29, 0x4001005d +.set CYDEV_UCFG_B0_P0_U0_CFG30, 0x4001005e +.set CYDEV_UCFG_B0_P0_U0_CFG31, 0x4001005f +.set CYDEV_UCFG_B0_P0_U0_DCFG0, 0x40010060 +.set CYDEV_UCFG_B0_P0_U0_DCFG1, 0x40010062 +.set CYDEV_UCFG_B0_P0_U0_DCFG2, 0x40010064 +.set CYDEV_UCFG_B0_P0_U0_DCFG3, 0x40010066 +.set CYDEV_UCFG_B0_P0_U0_DCFG4, 0x40010068 +.set CYDEV_UCFG_B0_P0_U0_DCFG5, 0x4001006a +.set CYDEV_UCFG_B0_P0_U0_DCFG6, 0x4001006c +.set CYDEV_UCFG_B0_P0_U0_DCFG7, 0x4001006e +.set CYDEV_UCFG_B0_P0_U1_BASE, 0x40010080 +.set CYDEV_UCFG_B0_P0_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT0, 0x40010080 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT1, 0x40010084 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT2, 0x40010088 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT3, 0x4001008c +.set CYDEV_UCFG_B0_P0_U1_PLD_IT4, 0x40010090 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT5, 0x40010094 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT6, 0x40010098 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT7, 0x4001009c +.set CYDEV_UCFG_B0_P0_U1_PLD_IT8, 0x400100a0 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT9, 0x400100a4 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT10, 0x400100a8 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT11, 0x400100ac +.set CYDEV_UCFG_B0_P0_U1_PLD_ORT0, 0x400100b0 +.set CYDEV_UCFG_B0_P0_U1_PLD_ORT1, 0x400100b2 +.set CYDEV_UCFG_B0_P0_U1_PLD_ORT2, 0x400100b4 +.set CYDEV_UCFG_B0_P0_U1_PLD_ORT3, 0x400100b6 +.set CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST, 0x400100b8 +.set CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB, 0x400100ba +.set CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET, 0x400100bc +.set CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS, 0x400100be +.set CYDEV_UCFG_B0_P0_U1_CFG0, 0x400100c0 +.set CYDEV_UCFG_B0_P0_U1_CFG1, 0x400100c1 +.set CYDEV_UCFG_B0_P0_U1_CFG2, 0x400100c2 +.set CYDEV_UCFG_B0_P0_U1_CFG3, 0x400100c3 +.set CYDEV_UCFG_B0_P0_U1_CFG4, 0x400100c4 +.set CYDEV_UCFG_B0_P0_U1_CFG5, 0x400100c5 +.set CYDEV_UCFG_B0_P0_U1_CFG6, 0x400100c6 +.set CYDEV_UCFG_B0_P0_U1_CFG7, 0x400100c7 +.set CYDEV_UCFG_B0_P0_U1_CFG8, 0x400100c8 +.set CYDEV_UCFG_B0_P0_U1_CFG9, 0x400100c9 +.set CYDEV_UCFG_B0_P0_U1_CFG10, 0x400100ca +.set CYDEV_UCFG_B0_P0_U1_CFG11, 0x400100cb +.set CYDEV_UCFG_B0_P0_U1_CFG12, 0x400100cc +.set CYDEV_UCFG_B0_P0_U1_CFG13, 0x400100cd +.set CYDEV_UCFG_B0_P0_U1_CFG14, 0x400100ce +.set CYDEV_UCFG_B0_P0_U1_CFG15, 0x400100cf +.set CYDEV_UCFG_B0_P0_U1_CFG16, 0x400100d0 +.set CYDEV_UCFG_B0_P0_U1_CFG17, 0x400100d1 +.set CYDEV_UCFG_B0_P0_U1_CFG18, 0x400100d2 +.set CYDEV_UCFG_B0_P0_U1_CFG19, 0x400100d3 +.set CYDEV_UCFG_B0_P0_U1_CFG20, 0x400100d4 +.set CYDEV_UCFG_B0_P0_U1_CFG21, 0x400100d5 +.set CYDEV_UCFG_B0_P0_U1_CFG22, 0x400100d6 +.set CYDEV_UCFG_B0_P0_U1_CFG23, 0x400100d7 +.set CYDEV_UCFG_B0_P0_U1_CFG24, 0x400100d8 +.set CYDEV_UCFG_B0_P0_U1_CFG25, 0x400100d9 +.set CYDEV_UCFG_B0_P0_U1_CFG26, 0x400100da +.set CYDEV_UCFG_B0_P0_U1_CFG27, 0x400100db +.set CYDEV_UCFG_B0_P0_U1_CFG28, 0x400100dc +.set CYDEV_UCFG_B0_P0_U1_CFG29, 0x400100dd +.set CYDEV_UCFG_B0_P0_U1_CFG30, 0x400100de +.set CYDEV_UCFG_B0_P0_U1_CFG31, 0x400100df +.set CYDEV_UCFG_B0_P0_U1_DCFG0, 0x400100e0 +.set CYDEV_UCFG_B0_P0_U1_DCFG1, 0x400100e2 +.set CYDEV_UCFG_B0_P0_U1_DCFG2, 0x400100e4 +.set CYDEV_UCFG_B0_P0_U1_DCFG3, 0x400100e6 +.set CYDEV_UCFG_B0_P0_U1_DCFG4, 0x400100e8 +.set CYDEV_UCFG_B0_P0_U1_DCFG5, 0x400100ea +.set CYDEV_UCFG_B0_P0_U1_DCFG6, 0x400100ec +.set CYDEV_UCFG_B0_P0_U1_DCFG7, 0x400100ee +.set CYDEV_UCFG_B0_P0_ROUTE_BASE, 0x40010100 +.set CYDEV_UCFG_B0_P0_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P1_BASE, 0x40010200 +.set CYDEV_UCFG_B0_P1_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P1_U0_BASE, 0x40010200 +.set CYDEV_UCFG_B0_P1_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT0, 0x40010200 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT1, 0x40010204 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT2, 0x40010208 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT3, 0x4001020c +.set CYDEV_UCFG_B0_P1_U0_PLD_IT4, 0x40010210 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT5, 0x40010214 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT6, 0x40010218 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT7, 0x4001021c +.set CYDEV_UCFG_B0_P1_U0_PLD_IT8, 0x40010220 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT9, 0x40010224 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT10, 0x40010228 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT11, 0x4001022c +.set CYDEV_UCFG_B0_P1_U0_PLD_ORT0, 0x40010230 +.set CYDEV_UCFG_B0_P1_U0_PLD_ORT1, 0x40010232 +.set CYDEV_UCFG_B0_P1_U0_PLD_ORT2, 0x40010234 +.set CYDEV_UCFG_B0_P1_U0_PLD_ORT3, 0x40010236 +.set CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST, 0x40010238 +.set CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB, 0x4001023a +.set CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET, 0x4001023c +.set CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS, 0x4001023e +.set CYDEV_UCFG_B0_P1_U0_CFG0, 0x40010240 +.set CYDEV_UCFG_B0_P1_U0_CFG1, 0x40010241 +.set CYDEV_UCFG_B0_P1_U0_CFG2, 0x40010242 +.set CYDEV_UCFG_B0_P1_U0_CFG3, 0x40010243 +.set CYDEV_UCFG_B0_P1_U0_CFG4, 0x40010244 +.set CYDEV_UCFG_B0_P1_U0_CFG5, 0x40010245 +.set CYDEV_UCFG_B0_P1_U0_CFG6, 0x40010246 +.set CYDEV_UCFG_B0_P1_U0_CFG7, 0x40010247 +.set CYDEV_UCFG_B0_P1_U0_CFG8, 0x40010248 +.set CYDEV_UCFG_B0_P1_U0_CFG9, 0x40010249 +.set CYDEV_UCFG_B0_P1_U0_CFG10, 0x4001024a +.set CYDEV_UCFG_B0_P1_U0_CFG11, 0x4001024b +.set CYDEV_UCFG_B0_P1_U0_CFG12, 0x4001024c +.set CYDEV_UCFG_B0_P1_U0_CFG13, 0x4001024d +.set CYDEV_UCFG_B0_P1_U0_CFG14, 0x4001024e +.set CYDEV_UCFG_B0_P1_U0_CFG15, 0x4001024f +.set CYDEV_UCFG_B0_P1_U0_CFG16, 0x40010250 +.set CYDEV_UCFG_B0_P1_U0_CFG17, 0x40010251 +.set CYDEV_UCFG_B0_P1_U0_CFG18, 0x40010252 +.set CYDEV_UCFG_B0_P1_U0_CFG19, 0x40010253 +.set CYDEV_UCFG_B0_P1_U0_CFG20, 0x40010254 +.set CYDEV_UCFG_B0_P1_U0_CFG21, 0x40010255 +.set CYDEV_UCFG_B0_P1_U0_CFG22, 0x40010256 +.set CYDEV_UCFG_B0_P1_U0_CFG23, 0x40010257 +.set CYDEV_UCFG_B0_P1_U0_CFG24, 0x40010258 +.set CYDEV_UCFG_B0_P1_U0_CFG25, 0x40010259 +.set CYDEV_UCFG_B0_P1_U0_CFG26, 0x4001025a +.set CYDEV_UCFG_B0_P1_U0_CFG27, 0x4001025b +.set CYDEV_UCFG_B0_P1_U0_CFG28, 0x4001025c +.set CYDEV_UCFG_B0_P1_U0_CFG29, 0x4001025d +.set CYDEV_UCFG_B0_P1_U0_CFG30, 0x4001025e +.set CYDEV_UCFG_B0_P1_U0_CFG31, 0x4001025f +.set CYDEV_UCFG_B0_P1_U0_DCFG0, 0x40010260 +.set CYDEV_UCFG_B0_P1_U0_DCFG1, 0x40010262 +.set CYDEV_UCFG_B0_P1_U0_DCFG2, 0x40010264 +.set CYDEV_UCFG_B0_P1_U0_DCFG3, 0x40010266 +.set CYDEV_UCFG_B0_P1_U0_DCFG4, 0x40010268 +.set CYDEV_UCFG_B0_P1_U0_DCFG5, 0x4001026a +.set CYDEV_UCFG_B0_P1_U0_DCFG6, 0x4001026c +.set CYDEV_UCFG_B0_P1_U0_DCFG7, 0x4001026e +.set CYDEV_UCFG_B0_P1_U1_BASE, 0x40010280 +.set CYDEV_UCFG_B0_P1_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT0, 0x40010280 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT1, 0x40010284 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT2, 0x40010288 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT3, 0x4001028c +.set CYDEV_UCFG_B0_P1_U1_PLD_IT4, 0x40010290 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT5, 0x40010294 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT6, 0x40010298 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT7, 0x4001029c +.set CYDEV_UCFG_B0_P1_U1_PLD_IT8, 0x400102a0 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT9, 0x400102a4 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT10, 0x400102a8 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT11, 0x400102ac +.set CYDEV_UCFG_B0_P1_U1_PLD_ORT0, 0x400102b0 +.set CYDEV_UCFG_B0_P1_U1_PLD_ORT1, 0x400102b2 +.set CYDEV_UCFG_B0_P1_U1_PLD_ORT2, 0x400102b4 +.set CYDEV_UCFG_B0_P1_U1_PLD_ORT3, 0x400102b6 +.set CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST, 0x400102b8 +.set CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB, 0x400102ba +.set CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET, 0x400102bc +.set CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS, 0x400102be +.set CYDEV_UCFG_B0_P1_U1_CFG0, 0x400102c0 +.set CYDEV_UCFG_B0_P1_U1_CFG1, 0x400102c1 +.set CYDEV_UCFG_B0_P1_U1_CFG2, 0x400102c2 +.set CYDEV_UCFG_B0_P1_U1_CFG3, 0x400102c3 +.set CYDEV_UCFG_B0_P1_U1_CFG4, 0x400102c4 +.set CYDEV_UCFG_B0_P1_U1_CFG5, 0x400102c5 +.set CYDEV_UCFG_B0_P1_U1_CFG6, 0x400102c6 +.set CYDEV_UCFG_B0_P1_U1_CFG7, 0x400102c7 +.set CYDEV_UCFG_B0_P1_U1_CFG8, 0x400102c8 +.set CYDEV_UCFG_B0_P1_U1_CFG9, 0x400102c9 +.set CYDEV_UCFG_B0_P1_U1_CFG10, 0x400102ca +.set CYDEV_UCFG_B0_P1_U1_CFG11, 0x400102cb +.set CYDEV_UCFG_B0_P1_U1_CFG12, 0x400102cc +.set CYDEV_UCFG_B0_P1_U1_CFG13, 0x400102cd +.set CYDEV_UCFG_B0_P1_U1_CFG14, 0x400102ce +.set CYDEV_UCFG_B0_P1_U1_CFG15, 0x400102cf +.set CYDEV_UCFG_B0_P1_U1_CFG16, 0x400102d0 +.set CYDEV_UCFG_B0_P1_U1_CFG17, 0x400102d1 +.set CYDEV_UCFG_B0_P1_U1_CFG18, 0x400102d2 +.set CYDEV_UCFG_B0_P1_U1_CFG19, 0x400102d3 +.set CYDEV_UCFG_B0_P1_U1_CFG20, 0x400102d4 +.set CYDEV_UCFG_B0_P1_U1_CFG21, 0x400102d5 +.set CYDEV_UCFG_B0_P1_U1_CFG22, 0x400102d6 +.set CYDEV_UCFG_B0_P1_U1_CFG23, 0x400102d7 +.set CYDEV_UCFG_B0_P1_U1_CFG24, 0x400102d8 +.set CYDEV_UCFG_B0_P1_U1_CFG25, 0x400102d9 +.set CYDEV_UCFG_B0_P1_U1_CFG26, 0x400102da +.set CYDEV_UCFG_B0_P1_U1_CFG27, 0x400102db +.set CYDEV_UCFG_B0_P1_U1_CFG28, 0x400102dc +.set CYDEV_UCFG_B0_P1_U1_CFG29, 0x400102dd +.set CYDEV_UCFG_B0_P1_U1_CFG30, 0x400102de +.set CYDEV_UCFG_B0_P1_U1_CFG31, 0x400102df +.set CYDEV_UCFG_B0_P1_U1_DCFG0, 0x400102e0 +.set CYDEV_UCFG_B0_P1_U1_DCFG1, 0x400102e2 +.set CYDEV_UCFG_B0_P1_U1_DCFG2, 0x400102e4 +.set CYDEV_UCFG_B0_P1_U1_DCFG3, 0x400102e6 +.set CYDEV_UCFG_B0_P1_U1_DCFG4, 0x400102e8 +.set CYDEV_UCFG_B0_P1_U1_DCFG5, 0x400102ea +.set CYDEV_UCFG_B0_P1_U1_DCFG6, 0x400102ec +.set CYDEV_UCFG_B0_P1_U1_DCFG7, 0x400102ee +.set CYDEV_UCFG_B0_P1_ROUTE_BASE, 0x40010300 +.set CYDEV_UCFG_B0_P1_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P2_BASE, 0x40010400 +.set CYDEV_UCFG_B0_P2_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P2_U0_BASE, 0x40010400 +.set CYDEV_UCFG_B0_P2_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT0, 0x40010400 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT1, 0x40010404 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT2, 0x40010408 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT3, 0x4001040c +.set CYDEV_UCFG_B0_P2_U0_PLD_IT4, 0x40010410 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT5, 0x40010414 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT6, 0x40010418 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT7, 0x4001041c +.set CYDEV_UCFG_B0_P2_U0_PLD_IT8, 0x40010420 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT9, 0x40010424 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT10, 0x40010428 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT11, 0x4001042c +.set CYDEV_UCFG_B0_P2_U0_PLD_ORT0, 0x40010430 +.set CYDEV_UCFG_B0_P2_U0_PLD_ORT1, 0x40010432 +.set CYDEV_UCFG_B0_P2_U0_PLD_ORT2, 0x40010434 +.set CYDEV_UCFG_B0_P2_U0_PLD_ORT3, 0x40010436 +.set CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST, 0x40010438 +.set CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB, 0x4001043a +.set CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET, 0x4001043c +.set CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS, 0x4001043e +.set CYDEV_UCFG_B0_P2_U0_CFG0, 0x40010440 +.set CYDEV_UCFG_B0_P2_U0_CFG1, 0x40010441 +.set CYDEV_UCFG_B0_P2_U0_CFG2, 0x40010442 +.set CYDEV_UCFG_B0_P2_U0_CFG3, 0x40010443 +.set CYDEV_UCFG_B0_P2_U0_CFG4, 0x40010444 +.set CYDEV_UCFG_B0_P2_U0_CFG5, 0x40010445 +.set CYDEV_UCFG_B0_P2_U0_CFG6, 0x40010446 +.set CYDEV_UCFG_B0_P2_U0_CFG7, 0x40010447 +.set CYDEV_UCFG_B0_P2_U0_CFG8, 0x40010448 +.set CYDEV_UCFG_B0_P2_U0_CFG9, 0x40010449 +.set CYDEV_UCFG_B0_P2_U0_CFG10, 0x4001044a +.set CYDEV_UCFG_B0_P2_U0_CFG11, 0x4001044b +.set CYDEV_UCFG_B0_P2_U0_CFG12, 0x4001044c +.set CYDEV_UCFG_B0_P2_U0_CFG13, 0x4001044d +.set CYDEV_UCFG_B0_P2_U0_CFG14, 0x4001044e +.set CYDEV_UCFG_B0_P2_U0_CFG15, 0x4001044f +.set CYDEV_UCFG_B0_P2_U0_CFG16, 0x40010450 +.set CYDEV_UCFG_B0_P2_U0_CFG17, 0x40010451 +.set CYDEV_UCFG_B0_P2_U0_CFG18, 0x40010452 +.set CYDEV_UCFG_B0_P2_U0_CFG19, 0x40010453 +.set CYDEV_UCFG_B0_P2_U0_CFG20, 0x40010454 +.set CYDEV_UCFG_B0_P2_U0_CFG21, 0x40010455 +.set CYDEV_UCFG_B0_P2_U0_CFG22, 0x40010456 +.set CYDEV_UCFG_B0_P2_U0_CFG23, 0x40010457 +.set CYDEV_UCFG_B0_P2_U0_CFG24, 0x40010458 +.set CYDEV_UCFG_B0_P2_U0_CFG25, 0x40010459 +.set CYDEV_UCFG_B0_P2_U0_CFG26, 0x4001045a +.set CYDEV_UCFG_B0_P2_U0_CFG27, 0x4001045b +.set CYDEV_UCFG_B0_P2_U0_CFG28, 0x4001045c +.set CYDEV_UCFG_B0_P2_U0_CFG29, 0x4001045d +.set CYDEV_UCFG_B0_P2_U0_CFG30, 0x4001045e +.set CYDEV_UCFG_B0_P2_U0_CFG31, 0x4001045f +.set CYDEV_UCFG_B0_P2_U0_DCFG0, 0x40010460 +.set CYDEV_UCFG_B0_P2_U0_DCFG1, 0x40010462 +.set CYDEV_UCFG_B0_P2_U0_DCFG2, 0x40010464 +.set CYDEV_UCFG_B0_P2_U0_DCFG3, 0x40010466 +.set CYDEV_UCFG_B0_P2_U0_DCFG4, 0x40010468 +.set CYDEV_UCFG_B0_P2_U0_DCFG5, 0x4001046a +.set CYDEV_UCFG_B0_P2_U0_DCFG6, 0x4001046c +.set CYDEV_UCFG_B0_P2_U0_DCFG7, 0x4001046e +.set CYDEV_UCFG_B0_P2_U1_BASE, 0x40010480 +.set CYDEV_UCFG_B0_P2_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT0, 0x40010480 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT1, 0x40010484 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT2, 0x40010488 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT3, 0x4001048c +.set CYDEV_UCFG_B0_P2_U1_PLD_IT4, 0x40010490 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT5, 0x40010494 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT6, 0x40010498 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT7, 0x4001049c +.set CYDEV_UCFG_B0_P2_U1_PLD_IT8, 0x400104a0 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT9, 0x400104a4 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT10, 0x400104a8 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT11, 0x400104ac +.set CYDEV_UCFG_B0_P2_U1_PLD_ORT0, 0x400104b0 +.set CYDEV_UCFG_B0_P2_U1_PLD_ORT1, 0x400104b2 +.set CYDEV_UCFG_B0_P2_U1_PLD_ORT2, 0x400104b4 +.set CYDEV_UCFG_B0_P2_U1_PLD_ORT3, 0x400104b6 +.set CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST, 0x400104b8 +.set CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB, 0x400104ba +.set CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET, 0x400104bc +.set CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS, 0x400104be +.set CYDEV_UCFG_B0_P2_U1_CFG0, 0x400104c0 +.set CYDEV_UCFG_B0_P2_U1_CFG1, 0x400104c1 +.set CYDEV_UCFG_B0_P2_U1_CFG2, 0x400104c2 +.set CYDEV_UCFG_B0_P2_U1_CFG3, 0x400104c3 +.set CYDEV_UCFG_B0_P2_U1_CFG4, 0x400104c4 +.set CYDEV_UCFG_B0_P2_U1_CFG5, 0x400104c5 +.set CYDEV_UCFG_B0_P2_U1_CFG6, 0x400104c6 +.set CYDEV_UCFG_B0_P2_U1_CFG7, 0x400104c7 +.set CYDEV_UCFG_B0_P2_U1_CFG8, 0x400104c8 +.set CYDEV_UCFG_B0_P2_U1_CFG9, 0x400104c9 +.set CYDEV_UCFG_B0_P2_U1_CFG10, 0x400104ca +.set CYDEV_UCFG_B0_P2_U1_CFG11, 0x400104cb +.set CYDEV_UCFG_B0_P2_U1_CFG12, 0x400104cc +.set CYDEV_UCFG_B0_P2_U1_CFG13, 0x400104cd +.set CYDEV_UCFG_B0_P2_U1_CFG14, 0x400104ce +.set CYDEV_UCFG_B0_P2_U1_CFG15, 0x400104cf +.set CYDEV_UCFG_B0_P2_U1_CFG16, 0x400104d0 +.set CYDEV_UCFG_B0_P2_U1_CFG17, 0x400104d1 +.set CYDEV_UCFG_B0_P2_U1_CFG18, 0x400104d2 +.set CYDEV_UCFG_B0_P2_U1_CFG19, 0x400104d3 +.set CYDEV_UCFG_B0_P2_U1_CFG20, 0x400104d4 +.set CYDEV_UCFG_B0_P2_U1_CFG21, 0x400104d5 +.set CYDEV_UCFG_B0_P2_U1_CFG22, 0x400104d6 +.set CYDEV_UCFG_B0_P2_U1_CFG23, 0x400104d7 +.set CYDEV_UCFG_B0_P2_U1_CFG24, 0x400104d8 +.set CYDEV_UCFG_B0_P2_U1_CFG25, 0x400104d9 +.set CYDEV_UCFG_B0_P2_U1_CFG26, 0x400104da +.set CYDEV_UCFG_B0_P2_U1_CFG27, 0x400104db +.set CYDEV_UCFG_B0_P2_U1_CFG28, 0x400104dc +.set CYDEV_UCFG_B0_P2_U1_CFG29, 0x400104dd +.set CYDEV_UCFG_B0_P2_U1_CFG30, 0x400104de +.set CYDEV_UCFG_B0_P2_U1_CFG31, 0x400104df +.set CYDEV_UCFG_B0_P2_U1_DCFG0, 0x400104e0 +.set CYDEV_UCFG_B0_P2_U1_DCFG1, 0x400104e2 +.set CYDEV_UCFG_B0_P2_U1_DCFG2, 0x400104e4 +.set CYDEV_UCFG_B0_P2_U1_DCFG3, 0x400104e6 +.set CYDEV_UCFG_B0_P2_U1_DCFG4, 0x400104e8 +.set CYDEV_UCFG_B0_P2_U1_DCFG5, 0x400104ea +.set CYDEV_UCFG_B0_P2_U1_DCFG6, 0x400104ec +.set CYDEV_UCFG_B0_P2_U1_DCFG7, 0x400104ee +.set CYDEV_UCFG_B0_P2_ROUTE_BASE, 0x40010500 +.set CYDEV_UCFG_B0_P2_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P3_BASE, 0x40010600 +.set CYDEV_UCFG_B0_P3_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P3_U0_BASE, 0x40010600 +.set CYDEV_UCFG_B0_P3_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT0, 0x40010600 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT1, 0x40010604 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT2, 0x40010608 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT3, 0x4001060c +.set CYDEV_UCFG_B0_P3_U0_PLD_IT4, 0x40010610 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT5, 0x40010614 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT6, 0x40010618 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT7, 0x4001061c +.set CYDEV_UCFG_B0_P3_U0_PLD_IT8, 0x40010620 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT9, 0x40010624 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT10, 0x40010628 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT11, 0x4001062c +.set CYDEV_UCFG_B0_P3_U0_PLD_ORT0, 0x40010630 +.set CYDEV_UCFG_B0_P3_U0_PLD_ORT1, 0x40010632 +.set CYDEV_UCFG_B0_P3_U0_PLD_ORT2, 0x40010634 +.set CYDEV_UCFG_B0_P3_U0_PLD_ORT3, 0x40010636 +.set CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST, 0x40010638 +.set CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB, 0x4001063a +.set CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET, 0x4001063c +.set CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS, 0x4001063e +.set CYDEV_UCFG_B0_P3_U0_CFG0, 0x40010640 +.set CYDEV_UCFG_B0_P3_U0_CFG1, 0x40010641 +.set CYDEV_UCFG_B0_P3_U0_CFG2, 0x40010642 +.set CYDEV_UCFG_B0_P3_U0_CFG3, 0x40010643 +.set CYDEV_UCFG_B0_P3_U0_CFG4, 0x40010644 +.set CYDEV_UCFG_B0_P3_U0_CFG5, 0x40010645 +.set CYDEV_UCFG_B0_P3_U0_CFG6, 0x40010646 +.set CYDEV_UCFG_B0_P3_U0_CFG7, 0x40010647 +.set CYDEV_UCFG_B0_P3_U0_CFG8, 0x40010648 +.set CYDEV_UCFG_B0_P3_U0_CFG9, 0x40010649 +.set CYDEV_UCFG_B0_P3_U0_CFG10, 0x4001064a +.set CYDEV_UCFG_B0_P3_U0_CFG11, 0x4001064b +.set CYDEV_UCFG_B0_P3_U0_CFG12, 0x4001064c +.set CYDEV_UCFG_B0_P3_U0_CFG13, 0x4001064d +.set CYDEV_UCFG_B0_P3_U0_CFG14, 0x4001064e +.set CYDEV_UCFG_B0_P3_U0_CFG15, 0x4001064f +.set CYDEV_UCFG_B0_P3_U0_CFG16, 0x40010650 +.set CYDEV_UCFG_B0_P3_U0_CFG17, 0x40010651 +.set CYDEV_UCFG_B0_P3_U0_CFG18, 0x40010652 +.set CYDEV_UCFG_B0_P3_U0_CFG19, 0x40010653 +.set CYDEV_UCFG_B0_P3_U0_CFG20, 0x40010654 +.set CYDEV_UCFG_B0_P3_U0_CFG21, 0x40010655 +.set CYDEV_UCFG_B0_P3_U0_CFG22, 0x40010656 +.set CYDEV_UCFG_B0_P3_U0_CFG23, 0x40010657 +.set CYDEV_UCFG_B0_P3_U0_CFG24, 0x40010658 +.set CYDEV_UCFG_B0_P3_U0_CFG25, 0x40010659 +.set CYDEV_UCFG_B0_P3_U0_CFG26, 0x4001065a +.set CYDEV_UCFG_B0_P3_U0_CFG27, 0x4001065b +.set CYDEV_UCFG_B0_P3_U0_CFG28, 0x4001065c +.set CYDEV_UCFG_B0_P3_U0_CFG29, 0x4001065d +.set CYDEV_UCFG_B0_P3_U0_CFG30, 0x4001065e +.set CYDEV_UCFG_B0_P3_U0_CFG31, 0x4001065f +.set CYDEV_UCFG_B0_P3_U0_DCFG0, 0x40010660 +.set CYDEV_UCFG_B0_P3_U0_DCFG1, 0x40010662 +.set CYDEV_UCFG_B0_P3_U0_DCFG2, 0x40010664 +.set CYDEV_UCFG_B0_P3_U0_DCFG3, 0x40010666 +.set CYDEV_UCFG_B0_P3_U0_DCFG4, 0x40010668 +.set CYDEV_UCFG_B0_P3_U0_DCFG5, 0x4001066a +.set CYDEV_UCFG_B0_P3_U0_DCFG6, 0x4001066c +.set CYDEV_UCFG_B0_P3_U0_DCFG7, 0x4001066e +.set CYDEV_UCFG_B0_P3_U1_BASE, 0x40010680 +.set CYDEV_UCFG_B0_P3_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT0, 0x40010680 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT1, 0x40010684 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT2, 0x40010688 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT3, 0x4001068c +.set CYDEV_UCFG_B0_P3_U1_PLD_IT4, 0x40010690 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT5, 0x40010694 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT6, 0x40010698 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT7, 0x4001069c +.set CYDEV_UCFG_B0_P3_U1_PLD_IT8, 0x400106a0 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT9, 0x400106a4 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT10, 0x400106a8 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT11, 0x400106ac +.set CYDEV_UCFG_B0_P3_U1_PLD_ORT0, 0x400106b0 +.set CYDEV_UCFG_B0_P3_U1_PLD_ORT1, 0x400106b2 +.set CYDEV_UCFG_B0_P3_U1_PLD_ORT2, 0x400106b4 +.set CYDEV_UCFG_B0_P3_U1_PLD_ORT3, 0x400106b6 +.set CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST, 0x400106b8 +.set CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB, 0x400106ba +.set CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET, 0x400106bc +.set CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS, 0x400106be +.set CYDEV_UCFG_B0_P3_U1_CFG0, 0x400106c0 +.set CYDEV_UCFG_B0_P3_U1_CFG1, 0x400106c1 +.set CYDEV_UCFG_B0_P3_U1_CFG2, 0x400106c2 +.set CYDEV_UCFG_B0_P3_U1_CFG3, 0x400106c3 +.set CYDEV_UCFG_B0_P3_U1_CFG4, 0x400106c4 +.set CYDEV_UCFG_B0_P3_U1_CFG5, 0x400106c5 +.set CYDEV_UCFG_B0_P3_U1_CFG6, 0x400106c6 +.set CYDEV_UCFG_B0_P3_U1_CFG7, 0x400106c7 +.set CYDEV_UCFG_B0_P3_U1_CFG8, 0x400106c8 +.set CYDEV_UCFG_B0_P3_U1_CFG9, 0x400106c9 +.set CYDEV_UCFG_B0_P3_U1_CFG10, 0x400106ca +.set CYDEV_UCFG_B0_P3_U1_CFG11, 0x400106cb +.set CYDEV_UCFG_B0_P3_U1_CFG12, 0x400106cc +.set CYDEV_UCFG_B0_P3_U1_CFG13, 0x400106cd +.set CYDEV_UCFG_B0_P3_U1_CFG14, 0x400106ce +.set CYDEV_UCFG_B0_P3_U1_CFG15, 0x400106cf +.set CYDEV_UCFG_B0_P3_U1_CFG16, 0x400106d0 +.set CYDEV_UCFG_B0_P3_U1_CFG17, 0x400106d1 +.set CYDEV_UCFG_B0_P3_U1_CFG18, 0x400106d2 +.set CYDEV_UCFG_B0_P3_U1_CFG19, 0x400106d3 +.set CYDEV_UCFG_B0_P3_U1_CFG20, 0x400106d4 +.set CYDEV_UCFG_B0_P3_U1_CFG21, 0x400106d5 +.set CYDEV_UCFG_B0_P3_U1_CFG22, 0x400106d6 +.set CYDEV_UCFG_B0_P3_U1_CFG23, 0x400106d7 +.set CYDEV_UCFG_B0_P3_U1_CFG24, 0x400106d8 +.set CYDEV_UCFG_B0_P3_U1_CFG25, 0x400106d9 +.set CYDEV_UCFG_B0_P3_U1_CFG26, 0x400106da +.set CYDEV_UCFG_B0_P3_U1_CFG27, 0x400106db +.set CYDEV_UCFG_B0_P3_U1_CFG28, 0x400106dc +.set CYDEV_UCFG_B0_P3_U1_CFG29, 0x400106dd +.set CYDEV_UCFG_B0_P3_U1_CFG30, 0x400106de +.set CYDEV_UCFG_B0_P3_U1_CFG31, 0x400106df +.set CYDEV_UCFG_B0_P3_U1_DCFG0, 0x400106e0 +.set CYDEV_UCFG_B0_P3_U1_DCFG1, 0x400106e2 +.set CYDEV_UCFG_B0_P3_U1_DCFG2, 0x400106e4 +.set CYDEV_UCFG_B0_P3_U1_DCFG3, 0x400106e6 +.set CYDEV_UCFG_B0_P3_U1_DCFG4, 0x400106e8 +.set CYDEV_UCFG_B0_P3_U1_DCFG5, 0x400106ea +.set CYDEV_UCFG_B0_P3_U1_DCFG6, 0x400106ec +.set CYDEV_UCFG_B0_P3_U1_DCFG7, 0x400106ee +.set CYDEV_UCFG_B0_P3_ROUTE_BASE, 0x40010700 +.set CYDEV_UCFG_B0_P3_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P4_BASE, 0x40010800 +.set CYDEV_UCFG_B0_P4_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P4_U0_BASE, 0x40010800 +.set CYDEV_UCFG_B0_P4_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT0, 0x40010800 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT1, 0x40010804 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT2, 0x40010808 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT3, 0x4001080c +.set CYDEV_UCFG_B0_P4_U0_PLD_IT4, 0x40010810 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT5, 0x40010814 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT6, 0x40010818 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT7, 0x4001081c +.set CYDEV_UCFG_B0_P4_U0_PLD_IT8, 0x40010820 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT9, 0x40010824 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT10, 0x40010828 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT11, 0x4001082c +.set CYDEV_UCFG_B0_P4_U0_PLD_ORT0, 0x40010830 +.set CYDEV_UCFG_B0_P4_U0_PLD_ORT1, 0x40010832 +.set CYDEV_UCFG_B0_P4_U0_PLD_ORT2, 0x40010834 +.set CYDEV_UCFG_B0_P4_U0_PLD_ORT3, 0x40010836 +.set CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST, 0x40010838 +.set CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB, 0x4001083a +.set CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET, 0x4001083c +.set CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS, 0x4001083e +.set CYDEV_UCFG_B0_P4_U0_CFG0, 0x40010840 +.set CYDEV_UCFG_B0_P4_U0_CFG1, 0x40010841 +.set CYDEV_UCFG_B0_P4_U0_CFG2, 0x40010842 +.set CYDEV_UCFG_B0_P4_U0_CFG3, 0x40010843 +.set CYDEV_UCFG_B0_P4_U0_CFG4, 0x40010844 +.set CYDEV_UCFG_B0_P4_U0_CFG5, 0x40010845 +.set CYDEV_UCFG_B0_P4_U0_CFG6, 0x40010846 +.set CYDEV_UCFG_B0_P4_U0_CFG7, 0x40010847 +.set CYDEV_UCFG_B0_P4_U0_CFG8, 0x40010848 +.set CYDEV_UCFG_B0_P4_U0_CFG9, 0x40010849 +.set CYDEV_UCFG_B0_P4_U0_CFG10, 0x4001084a +.set CYDEV_UCFG_B0_P4_U0_CFG11, 0x4001084b +.set CYDEV_UCFG_B0_P4_U0_CFG12, 0x4001084c +.set CYDEV_UCFG_B0_P4_U0_CFG13, 0x4001084d +.set CYDEV_UCFG_B0_P4_U0_CFG14, 0x4001084e +.set CYDEV_UCFG_B0_P4_U0_CFG15, 0x4001084f +.set CYDEV_UCFG_B0_P4_U0_CFG16, 0x40010850 +.set CYDEV_UCFG_B0_P4_U0_CFG17, 0x40010851 +.set CYDEV_UCFG_B0_P4_U0_CFG18, 0x40010852 +.set CYDEV_UCFG_B0_P4_U0_CFG19, 0x40010853 +.set CYDEV_UCFG_B0_P4_U0_CFG20, 0x40010854 +.set CYDEV_UCFG_B0_P4_U0_CFG21, 0x40010855 +.set CYDEV_UCFG_B0_P4_U0_CFG22, 0x40010856 +.set CYDEV_UCFG_B0_P4_U0_CFG23, 0x40010857 +.set CYDEV_UCFG_B0_P4_U0_CFG24, 0x40010858 +.set CYDEV_UCFG_B0_P4_U0_CFG25, 0x40010859 +.set CYDEV_UCFG_B0_P4_U0_CFG26, 0x4001085a +.set CYDEV_UCFG_B0_P4_U0_CFG27, 0x4001085b +.set CYDEV_UCFG_B0_P4_U0_CFG28, 0x4001085c +.set CYDEV_UCFG_B0_P4_U0_CFG29, 0x4001085d +.set CYDEV_UCFG_B0_P4_U0_CFG30, 0x4001085e +.set CYDEV_UCFG_B0_P4_U0_CFG31, 0x4001085f +.set CYDEV_UCFG_B0_P4_U0_DCFG0, 0x40010860 +.set CYDEV_UCFG_B0_P4_U0_DCFG1, 0x40010862 +.set CYDEV_UCFG_B0_P4_U0_DCFG2, 0x40010864 +.set CYDEV_UCFG_B0_P4_U0_DCFG3, 0x40010866 +.set CYDEV_UCFG_B0_P4_U0_DCFG4, 0x40010868 +.set CYDEV_UCFG_B0_P4_U0_DCFG5, 0x4001086a +.set CYDEV_UCFG_B0_P4_U0_DCFG6, 0x4001086c +.set CYDEV_UCFG_B0_P4_U0_DCFG7, 0x4001086e +.set CYDEV_UCFG_B0_P4_U1_BASE, 0x40010880 +.set CYDEV_UCFG_B0_P4_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT0, 0x40010880 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT1, 0x40010884 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT2, 0x40010888 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT3, 0x4001088c +.set CYDEV_UCFG_B0_P4_U1_PLD_IT4, 0x40010890 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT5, 0x40010894 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT6, 0x40010898 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT7, 0x4001089c +.set CYDEV_UCFG_B0_P4_U1_PLD_IT8, 0x400108a0 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT9, 0x400108a4 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT10, 0x400108a8 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT11, 0x400108ac +.set CYDEV_UCFG_B0_P4_U1_PLD_ORT0, 0x400108b0 +.set CYDEV_UCFG_B0_P4_U1_PLD_ORT1, 0x400108b2 +.set CYDEV_UCFG_B0_P4_U1_PLD_ORT2, 0x400108b4 +.set CYDEV_UCFG_B0_P4_U1_PLD_ORT3, 0x400108b6 +.set CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST, 0x400108b8 +.set CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB, 0x400108ba +.set CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET, 0x400108bc +.set CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS, 0x400108be +.set CYDEV_UCFG_B0_P4_U1_CFG0, 0x400108c0 +.set CYDEV_UCFG_B0_P4_U1_CFG1, 0x400108c1 +.set CYDEV_UCFG_B0_P4_U1_CFG2, 0x400108c2 +.set CYDEV_UCFG_B0_P4_U1_CFG3, 0x400108c3 +.set CYDEV_UCFG_B0_P4_U1_CFG4, 0x400108c4 +.set CYDEV_UCFG_B0_P4_U1_CFG5, 0x400108c5 +.set CYDEV_UCFG_B0_P4_U1_CFG6, 0x400108c6 +.set CYDEV_UCFG_B0_P4_U1_CFG7, 0x400108c7 +.set CYDEV_UCFG_B0_P4_U1_CFG8, 0x400108c8 +.set CYDEV_UCFG_B0_P4_U1_CFG9, 0x400108c9 +.set CYDEV_UCFG_B0_P4_U1_CFG10, 0x400108ca +.set CYDEV_UCFG_B0_P4_U1_CFG11, 0x400108cb +.set CYDEV_UCFG_B0_P4_U1_CFG12, 0x400108cc +.set CYDEV_UCFG_B0_P4_U1_CFG13, 0x400108cd +.set CYDEV_UCFG_B0_P4_U1_CFG14, 0x400108ce +.set CYDEV_UCFG_B0_P4_U1_CFG15, 0x400108cf +.set CYDEV_UCFG_B0_P4_U1_CFG16, 0x400108d0 +.set CYDEV_UCFG_B0_P4_U1_CFG17, 0x400108d1 +.set CYDEV_UCFG_B0_P4_U1_CFG18, 0x400108d2 +.set CYDEV_UCFG_B0_P4_U1_CFG19, 0x400108d3 +.set CYDEV_UCFG_B0_P4_U1_CFG20, 0x400108d4 +.set CYDEV_UCFG_B0_P4_U1_CFG21, 0x400108d5 +.set CYDEV_UCFG_B0_P4_U1_CFG22, 0x400108d6 +.set CYDEV_UCFG_B0_P4_U1_CFG23, 0x400108d7 +.set CYDEV_UCFG_B0_P4_U1_CFG24, 0x400108d8 +.set CYDEV_UCFG_B0_P4_U1_CFG25, 0x400108d9 +.set CYDEV_UCFG_B0_P4_U1_CFG26, 0x400108da +.set CYDEV_UCFG_B0_P4_U1_CFG27, 0x400108db +.set CYDEV_UCFG_B0_P4_U1_CFG28, 0x400108dc +.set CYDEV_UCFG_B0_P4_U1_CFG29, 0x400108dd +.set CYDEV_UCFG_B0_P4_U1_CFG30, 0x400108de +.set CYDEV_UCFG_B0_P4_U1_CFG31, 0x400108df +.set CYDEV_UCFG_B0_P4_U1_DCFG0, 0x400108e0 +.set CYDEV_UCFG_B0_P4_U1_DCFG1, 0x400108e2 +.set CYDEV_UCFG_B0_P4_U1_DCFG2, 0x400108e4 +.set CYDEV_UCFG_B0_P4_U1_DCFG3, 0x400108e6 +.set CYDEV_UCFG_B0_P4_U1_DCFG4, 0x400108e8 +.set CYDEV_UCFG_B0_P4_U1_DCFG5, 0x400108ea +.set CYDEV_UCFG_B0_P4_U1_DCFG6, 0x400108ec +.set CYDEV_UCFG_B0_P4_U1_DCFG7, 0x400108ee +.set CYDEV_UCFG_B0_P4_ROUTE_BASE, 0x40010900 +.set CYDEV_UCFG_B0_P4_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P5_BASE, 0x40010a00 +.set CYDEV_UCFG_B0_P5_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P5_U0_BASE, 0x40010a00 +.set CYDEV_UCFG_B0_P5_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT0, 0x40010a00 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT1, 0x40010a04 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT2, 0x40010a08 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT3, 0x40010a0c +.set CYDEV_UCFG_B0_P5_U0_PLD_IT4, 0x40010a10 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT5, 0x40010a14 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT6, 0x40010a18 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT7, 0x40010a1c +.set CYDEV_UCFG_B0_P5_U0_PLD_IT8, 0x40010a20 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT9, 0x40010a24 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT10, 0x40010a28 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT11, 0x40010a2c +.set CYDEV_UCFG_B0_P5_U0_PLD_ORT0, 0x40010a30 +.set CYDEV_UCFG_B0_P5_U0_PLD_ORT1, 0x40010a32 +.set CYDEV_UCFG_B0_P5_U0_PLD_ORT2, 0x40010a34 +.set CYDEV_UCFG_B0_P5_U0_PLD_ORT3, 0x40010a36 +.set CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST, 0x40010a38 +.set CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB, 0x40010a3a +.set CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET, 0x40010a3c +.set CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS, 0x40010a3e +.set CYDEV_UCFG_B0_P5_U0_CFG0, 0x40010a40 +.set CYDEV_UCFG_B0_P5_U0_CFG1, 0x40010a41 +.set CYDEV_UCFG_B0_P5_U0_CFG2, 0x40010a42 +.set CYDEV_UCFG_B0_P5_U0_CFG3, 0x40010a43 +.set CYDEV_UCFG_B0_P5_U0_CFG4, 0x40010a44 +.set CYDEV_UCFG_B0_P5_U0_CFG5, 0x40010a45 +.set CYDEV_UCFG_B0_P5_U0_CFG6, 0x40010a46 +.set CYDEV_UCFG_B0_P5_U0_CFG7, 0x40010a47 +.set CYDEV_UCFG_B0_P5_U0_CFG8, 0x40010a48 +.set CYDEV_UCFG_B0_P5_U0_CFG9, 0x40010a49 +.set CYDEV_UCFG_B0_P5_U0_CFG10, 0x40010a4a +.set CYDEV_UCFG_B0_P5_U0_CFG11, 0x40010a4b +.set CYDEV_UCFG_B0_P5_U0_CFG12, 0x40010a4c +.set CYDEV_UCFG_B0_P5_U0_CFG13, 0x40010a4d +.set CYDEV_UCFG_B0_P5_U0_CFG14, 0x40010a4e +.set CYDEV_UCFG_B0_P5_U0_CFG15, 0x40010a4f +.set CYDEV_UCFG_B0_P5_U0_CFG16, 0x40010a50 +.set CYDEV_UCFG_B0_P5_U0_CFG17, 0x40010a51 +.set CYDEV_UCFG_B0_P5_U0_CFG18, 0x40010a52 +.set CYDEV_UCFG_B0_P5_U0_CFG19, 0x40010a53 +.set CYDEV_UCFG_B0_P5_U0_CFG20, 0x40010a54 +.set CYDEV_UCFG_B0_P5_U0_CFG21, 0x40010a55 +.set CYDEV_UCFG_B0_P5_U0_CFG22, 0x40010a56 +.set CYDEV_UCFG_B0_P5_U0_CFG23, 0x40010a57 +.set CYDEV_UCFG_B0_P5_U0_CFG24, 0x40010a58 +.set CYDEV_UCFG_B0_P5_U0_CFG25, 0x40010a59 +.set CYDEV_UCFG_B0_P5_U0_CFG26, 0x40010a5a +.set CYDEV_UCFG_B0_P5_U0_CFG27, 0x40010a5b +.set CYDEV_UCFG_B0_P5_U0_CFG28, 0x40010a5c +.set CYDEV_UCFG_B0_P5_U0_CFG29, 0x40010a5d +.set CYDEV_UCFG_B0_P5_U0_CFG30, 0x40010a5e +.set CYDEV_UCFG_B0_P5_U0_CFG31, 0x40010a5f +.set CYDEV_UCFG_B0_P5_U0_DCFG0, 0x40010a60 +.set CYDEV_UCFG_B0_P5_U0_DCFG1, 0x40010a62 +.set CYDEV_UCFG_B0_P5_U0_DCFG2, 0x40010a64 +.set CYDEV_UCFG_B0_P5_U0_DCFG3, 0x40010a66 +.set CYDEV_UCFG_B0_P5_U0_DCFG4, 0x40010a68 +.set CYDEV_UCFG_B0_P5_U0_DCFG5, 0x40010a6a +.set CYDEV_UCFG_B0_P5_U0_DCFG6, 0x40010a6c +.set CYDEV_UCFG_B0_P5_U0_DCFG7, 0x40010a6e +.set CYDEV_UCFG_B0_P5_U1_BASE, 0x40010a80 +.set CYDEV_UCFG_B0_P5_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT0, 0x40010a80 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT1, 0x40010a84 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT2, 0x40010a88 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT3, 0x40010a8c +.set CYDEV_UCFG_B0_P5_U1_PLD_IT4, 0x40010a90 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT5, 0x40010a94 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT6, 0x40010a98 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT7, 0x40010a9c +.set CYDEV_UCFG_B0_P5_U1_PLD_IT8, 0x40010aa0 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT9, 0x40010aa4 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT10, 0x40010aa8 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT11, 0x40010aac +.set CYDEV_UCFG_B0_P5_U1_PLD_ORT0, 0x40010ab0 +.set CYDEV_UCFG_B0_P5_U1_PLD_ORT1, 0x40010ab2 +.set CYDEV_UCFG_B0_P5_U1_PLD_ORT2, 0x40010ab4 +.set CYDEV_UCFG_B0_P5_U1_PLD_ORT3, 0x40010ab6 +.set CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST, 0x40010ab8 +.set CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB, 0x40010aba +.set CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET, 0x40010abc +.set CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS, 0x40010abe +.set CYDEV_UCFG_B0_P5_U1_CFG0, 0x40010ac0 +.set CYDEV_UCFG_B0_P5_U1_CFG1, 0x40010ac1 +.set CYDEV_UCFG_B0_P5_U1_CFG2, 0x40010ac2 +.set CYDEV_UCFG_B0_P5_U1_CFG3, 0x40010ac3 +.set CYDEV_UCFG_B0_P5_U1_CFG4, 0x40010ac4 +.set CYDEV_UCFG_B0_P5_U1_CFG5, 0x40010ac5 +.set CYDEV_UCFG_B0_P5_U1_CFG6, 0x40010ac6 +.set CYDEV_UCFG_B0_P5_U1_CFG7, 0x40010ac7 +.set CYDEV_UCFG_B0_P5_U1_CFG8, 0x40010ac8 +.set CYDEV_UCFG_B0_P5_U1_CFG9, 0x40010ac9 +.set CYDEV_UCFG_B0_P5_U1_CFG10, 0x40010aca +.set CYDEV_UCFG_B0_P5_U1_CFG11, 0x40010acb +.set CYDEV_UCFG_B0_P5_U1_CFG12, 0x40010acc +.set CYDEV_UCFG_B0_P5_U1_CFG13, 0x40010acd +.set CYDEV_UCFG_B0_P5_U1_CFG14, 0x40010ace +.set CYDEV_UCFG_B0_P5_U1_CFG15, 0x40010acf +.set CYDEV_UCFG_B0_P5_U1_CFG16, 0x40010ad0 +.set CYDEV_UCFG_B0_P5_U1_CFG17, 0x40010ad1 +.set CYDEV_UCFG_B0_P5_U1_CFG18, 0x40010ad2 +.set CYDEV_UCFG_B0_P5_U1_CFG19, 0x40010ad3 +.set CYDEV_UCFG_B0_P5_U1_CFG20, 0x40010ad4 +.set CYDEV_UCFG_B0_P5_U1_CFG21, 0x40010ad5 +.set CYDEV_UCFG_B0_P5_U1_CFG22, 0x40010ad6 +.set CYDEV_UCFG_B0_P5_U1_CFG23, 0x40010ad7 +.set CYDEV_UCFG_B0_P5_U1_CFG24, 0x40010ad8 +.set CYDEV_UCFG_B0_P5_U1_CFG25, 0x40010ad9 +.set CYDEV_UCFG_B0_P5_U1_CFG26, 0x40010ada +.set CYDEV_UCFG_B0_P5_U1_CFG27, 0x40010adb +.set CYDEV_UCFG_B0_P5_U1_CFG28, 0x40010adc +.set CYDEV_UCFG_B0_P5_U1_CFG29, 0x40010add +.set CYDEV_UCFG_B0_P5_U1_CFG30, 0x40010ade +.set CYDEV_UCFG_B0_P5_U1_CFG31, 0x40010adf +.set CYDEV_UCFG_B0_P5_U1_DCFG0, 0x40010ae0 +.set CYDEV_UCFG_B0_P5_U1_DCFG1, 0x40010ae2 +.set CYDEV_UCFG_B0_P5_U1_DCFG2, 0x40010ae4 +.set CYDEV_UCFG_B0_P5_U1_DCFG3, 0x40010ae6 +.set CYDEV_UCFG_B0_P5_U1_DCFG4, 0x40010ae8 +.set CYDEV_UCFG_B0_P5_U1_DCFG5, 0x40010aea +.set CYDEV_UCFG_B0_P5_U1_DCFG6, 0x40010aec +.set CYDEV_UCFG_B0_P5_U1_DCFG7, 0x40010aee +.set CYDEV_UCFG_B0_P5_ROUTE_BASE, 0x40010b00 +.set CYDEV_UCFG_B0_P5_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P6_BASE, 0x40010c00 +.set CYDEV_UCFG_B0_P6_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P6_U0_BASE, 0x40010c00 +.set CYDEV_UCFG_B0_P6_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT0, 0x40010c00 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT1, 0x40010c04 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT2, 0x40010c08 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT3, 0x40010c0c +.set CYDEV_UCFG_B0_P6_U0_PLD_IT4, 0x40010c10 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT5, 0x40010c14 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT6, 0x40010c18 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT7, 0x40010c1c +.set CYDEV_UCFG_B0_P6_U0_PLD_IT8, 0x40010c20 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT9, 0x40010c24 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT10, 0x40010c28 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT11, 0x40010c2c +.set CYDEV_UCFG_B0_P6_U0_PLD_ORT0, 0x40010c30 +.set CYDEV_UCFG_B0_P6_U0_PLD_ORT1, 0x40010c32 +.set CYDEV_UCFG_B0_P6_U0_PLD_ORT2, 0x40010c34 +.set CYDEV_UCFG_B0_P6_U0_PLD_ORT3, 0x40010c36 +.set CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST, 0x40010c38 +.set CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB, 0x40010c3a +.set CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET, 0x40010c3c +.set CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS, 0x40010c3e +.set CYDEV_UCFG_B0_P6_U0_CFG0, 0x40010c40 +.set CYDEV_UCFG_B0_P6_U0_CFG1, 0x40010c41 +.set CYDEV_UCFG_B0_P6_U0_CFG2, 0x40010c42 +.set CYDEV_UCFG_B0_P6_U0_CFG3, 0x40010c43 +.set CYDEV_UCFG_B0_P6_U0_CFG4, 0x40010c44 +.set CYDEV_UCFG_B0_P6_U0_CFG5, 0x40010c45 +.set CYDEV_UCFG_B0_P6_U0_CFG6, 0x40010c46 +.set CYDEV_UCFG_B0_P6_U0_CFG7, 0x40010c47 +.set CYDEV_UCFG_B0_P6_U0_CFG8, 0x40010c48 +.set CYDEV_UCFG_B0_P6_U0_CFG9, 0x40010c49 +.set CYDEV_UCFG_B0_P6_U0_CFG10, 0x40010c4a +.set CYDEV_UCFG_B0_P6_U0_CFG11, 0x40010c4b +.set CYDEV_UCFG_B0_P6_U0_CFG12, 0x40010c4c +.set CYDEV_UCFG_B0_P6_U0_CFG13, 0x40010c4d +.set CYDEV_UCFG_B0_P6_U0_CFG14, 0x40010c4e +.set CYDEV_UCFG_B0_P6_U0_CFG15, 0x40010c4f +.set CYDEV_UCFG_B0_P6_U0_CFG16, 0x40010c50 +.set CYDEV_UCFG_B0_P6_U0_CFG17, 0x40010c51 +.set CYDEV_UCFG_B0_P6_U0_CFG18, 0x40010c52 +.set CYDEV_UCFG_B0_P6_U0_CFG19, 0x40010c53 +.set CYDEV_UCFG_B0_P6_U0_CFG20, 0x40010c54 +.set CYDEV_UCFG_B0_P6_U0_CFG21, 0x40010c55 +.set CYDEV_UCFG_B0_P6_U0_CFG22, 0x40010c56 +.set CYDEV_UCFG_B0_P6_U0_CFG23, 0x40010c57 +.set CYDEV_UCFG_B0_P6_U0_CFG24, 0x40010c58 +.set CYDEV_UCFG_B0_P6_U0_CFG25, 0x40010c59 +.set CYDEV_UCFG_B0_P6_U0_CFG26, 0x40010c5a +.set CYDEV_UCFG_B0_P6_U0_CFG27, 0x40010c5b +.set CYDEV_UCFG_B0_P6_U0_CFG28, 0x40010c5c +.set CYDEV_UCFG_B0_P6_U0_CFG29, 0x40010c5d +.set CYDEV_UCFG_B0_P6_U0_CFG30, 0x40010c5e +.set CYDEV_UCFG_B0_P6_U0_CFG31, 0x40010c5f +.set CYDEV_UCFG_B0_P6_U0_DCFG0, 0x40010c60 +.set CYDEV_UCFG_B0_P6_U0_DCFG1, 0x40010c62 +.set CYDEV_UCFG_B0_P6_U0_DCFG2, 0x40010c64 +.set CYDEV_UCFG_B0_P6_U0_DCFG3, 0x40010c66 +.set CYDEV_UCFG_B0_P6_U0_DCFG4, 0x40010c68 +.set CYDEV_UCFG_B0_P6_U0_DCFG5, 0x40010c6a +.set CYDEV_UCFG_B0_P6_U0_DCFG6, 0x40010c6c +.set CYDEV_UCFG_B0_P6_U0_DCFG7, 0x40010c6e +.set CYDEV_UCFG_B0_P6_U1_BASE, 0x40010c80 +.set CYDEV_UCFG_B0_P6_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT0, 0x40010c80 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT1, 0x40010c84 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT2, 0x40010c88 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT3, 0x40010c8c +.set CYDEV_UCFG_B0_P6_U1_PLD_IT4, 0x40010c90 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT5, 0x40010c94 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT6, 0x40010c98 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT7, 0x40010c9c +.set CYDEV_UCFG_B0_P6_U1_PLD_IT8, 0x40010ca0 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT9, 0x40010ca4 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT10, 0x40010ca8 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT11, 0x40010cac +.set CYDEV_UCFG_B0_P6_U1_PLD_ORT0, 0x40010cb0 +.set CYDEV_UCFG_B0_P6_U1_PLD_ORT1, 0x40010cb2 +.set CYDEV_UCFG_B0_P6_U1_PLD_ORT2, 0x40010cb4 +.set CYDEV_UCFG_B0_P6_U1_PLD_ORT3, 0x40010cb6 +.set CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST, 0x40010cb8 +.set CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB, 0x40010cba +.set CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET, 0x40010cbc +.set CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS, 0x40010cbe +.set CYDEV_UCFG_B0_P6_U1_CFG0, 0x40010cc0 +.set CYDEV_UCFG_B0_P6_U1_CFG1, 0x40010cc1 +.set CYDEV_UCFG_B0_P6_U1_CFG2, 0x40010cc2 +.set CYDEV_UCFG_B0_P6_U1_CFG3, 0x40010cc3 +.set CYDEV_UCFG_B0_P6_U1_CFG4, 0x40010cc4 +.set CYDEV_UCFG_B0_P6_U1_CFG5, 0x40010cc5 +.set CYDEV_UCFG_B0_P6_U1_CFG6, 0x40010cc6 +.set CYDEV_UCFG_B0_P6_U1_CFG7, 0x40010cc7 +.set CYDEV_UCFG_B0_P6_U1_CFG8, 0x40010cc8 +.set CYDEV_UCFG_B0_P6_U1_CFG9, 0x40010cc9 +.set CYDEV_UCFG_B0_P6_U1_CFG10, 0x40010cca +.set CYDEV_UCFG_B0_P6_U1_CFG11, 0x40010ccb +.set CYDEV_UCFG_B0_P6_U1_CFG12, 0x40010ccc +.set CYDEV_UCFG_B0_P6_U1_CFG13, 0x40010ccd +.set CYDEV_UCFG_B0_P6_U1_CFG14, 0x40010cce +.set CYDEV_UCFG_B0_P6_U1_CFG15, 0x40010ccf +.set CYDEV_UCFG_B0_P6_U1_CFG16, 0x40010cd0 +.set CYDEV_UCFG_B0_P6_U1_CFG17, 0x40010cd1 +.set CYDEV_UCFG_B0_P6_U1_CFG18, 0x40010cd2 +.set CYDEV_UCFG_B0_P6_U1_CFG19, 0x40010cd3 +.set CYDEV_UCFG_B0_P6_U1_CFG20, 0x40010cd4 +.set CYDEV_UCFG_B0_P6_U1_CFG21, 0x40010cd5 +.set CYDEV_UCFG_B0_P6_U1_CFG22, 0x40010cd6 +.set CYDEV_UCFG_B0_P6_U1_CFG23, 0x40010cd7 +.set CYDEV_UCFG_B0_P6_U1_CFG24, 0x40010cd8 +.set CYDEV_UCFG_B0_P6_U1_CFG25, 0x40010cd9 +.set CYDEV_UCFG_B0_P6_U1_CFG26, 0x40010cda +.set CYDEV_UCFG_B0_P6_U1_CFG27, 0x40010cdb +.set CYDEV_UCFG_B0_P6_U1_CFG28, 0x40010cdc +.set CYDEV_UCFG_B0_P6_U1_CFG29, 0x40010cdd +.set CYDEV_UCFG_B0_P6_U1_CFG30, 0x40010cde +.set CYDEV_UCFG_B0_P6_U1_CFG31, 0x40010cdf +.set CYDEV_UCFG_B0_P6_U1_DCFG0, 0x40010ce0 +.set CYDEV_UCFG_B0_P6_U1_DCFG1, 0x40010ce2 +.set CYDEV_UCFG_B0_P6_U1_DCFG2, 0x40010ce4 +.set CYDEV_UCFG_B0_P6_U1_DCFG3, 0x40010ce6 +.set CYDEV_UCFG_B0_P6_U1_DCFG4, 0x40010ce8 +.set CYDEV_UCFG_B0_P6_U1_DCFG5, 0x40010cea +.set CYDEV_UCFG_B0_P6_U1_DCFG6, 0x40010cec +.set CYDEV_UCFG_B0_P6_U1_DCFG7, 0x40010cee +.set CYDEV_UCFG_B0_P6_ROUTE_BASE, 0x40010d00 +.set CYDEV_UCFG_B0_P6_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P7_BASE, 0x40010e00 +.set CYDEV_UCFG_B0_P7_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P7_U0_BASE, 0x40010e00 +.set CYDEV_UCFG_B0_P7_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT0, 0x40010e00 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT1, 0x40010e04 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT2, 0x40010e08 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT3, 0x40010e0c +.set CYDEV_UCFG_B0_P7_U0_PLD_IT4, 0x40010e10 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT5, 0x40010e14 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT6, 0x40010e18 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT7, 0x40010e1c +.set CYDEV_UCFG_B0_P7_U0_PLD_IT8, 0x40010e20 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT9, 0x40010e24 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT10, 0x40010e28 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT11, 0x40010e2c +.set CYDEV_UCFG_B0_P7_U0_PLD_ORT0, 0x40010e30 +.set CYDEV_UCFG_B0_P7_U0_PLD_ORT1, 0x40010e32 +.set CYDEV_UCFG_B0_P7_U0_PLD_ORT2, 0x40010e34 +.set CYDEV_UCFG_B0_P7_U0_PLD_ORT3, 0x40010e36 +.set CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST, 0x40010e38 +.set CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB, 0x40010e3a +.set CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET, 0x40010e3c +.set CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS, 0x40010e3e +.set CYDEV_UCFG_B0_P7_U0_CFG0, 0x40010e40 +.set CYDEV_UCFG_B0_P7_U0_CFG1, 0x40010e41 +.set CYDEV_UCFG_B0_P7_U0_CFG2, 0x40010e42 +.set CYDEV_UCFG_B0_P7_U0_CFG3, 0x40010e43 +.set CYDEV_UCFG_B0_P7_U0_CFG4, 0x40010e44 +.set CYDEV_UCFG_B0_P7_U0_CFG5, 0x40010e45 +.set CYDEV_UCFG_B0_P7_U0_CFG6, 0x40010e46 +.set CYDEV_UCFG_B0_P7_U0_CFG7, 0x40010e47 +.set CYDEV_UCFG_B0_P7_U0_CFG8, 0x40010e48 +.set CYDEV_UCFG_B0_P7_U0_CFG9, 0x40010e49 +.set CYDEV_UCFG_B0_P7_U0_CFG10, 0x40010e4a +.set CYDEV_UCFG_B0_P7_U0_CFG11, 0x40010e4b +.set CYDEV_UCFG_B0_P7_U0_CFG12, 0x40010e4c +.set CYDEV_UCFG_B0_P7_U0_CFG13, 0x40010e4d +.set CYDEV_UCFG_B0_P7_U0_CFG14, 0x40010e4e +.set CYDEV_UCFG_B0_P7_U0_CFG15, 0x40010e4f +.set CYDEV_UCFG_B0_P7_U0_CFG16, 0x40010e50 +.set CYDEV_UCFG_B0_P7_U0_CFG17, 0x40010e51 +.set CYDEV_UCFG_B0_P7_U0_CFG18, 0x40010e52 +.set CYDEV_UCFG_B0_P7_U0_CFG19, 0x40010e53 +.set CYDEV_UCFG_B0_P7_U0_CFG20, 0x40010e54 +.set CYDEV_UCFG_B0_P7_U0_CFG21, 0x40010e55 +.set CYDEV_UCFG_B0_P7_U0_CFG22, 0x40010e56 +.set CYDEV_UCFG_B0_P7_U0_CFG23, 0x40010e57 +.set CYDEV_UCFG_B0_P7_U0_CFG24, 0x40010e58 +.set CYDEV_UCFG_B0_P7_U0_CFG25, 0x40010e59 +.set CYDEV_UCFG_B0_P7_U0_CFG26, 0x40010e5a +.set CYDEV_UCFG_B0_P7_U0_CFG27, 0x40010e5b +.set CYDEV_UCFG_B0_P7_U0_CFG28, 0x40010e5c +.set CYDEV_UCFG_B0_P7_U0_CFG29, 0x40010e5d +.set CYDEV_UCFG_B0_P7_U0_CFG30, 0x40010e5e +.set CYDEV_UCFG_B0_P7_U0_CFG31, 0x40010e5f +.set CYDEV_UCFG_B0_P7_U0_DCFG0, 0x40010e60 +.set CYDEV_UCFG_B0_P7_U0_DCFG1, 0x40010e62 +.set CYDEV_UCFG_B0_P7_U0_DCFG2, 0x40010e64 +.set CYDEV_UCFG_B0_P7_U0_DCFG3, 0x40010e66 +.set CYDEV_UCFG_B0_P7_U0_DCFG4, 0x40010e68 +.set CYDEV_UCFG_B0_P7_U0_DCFG5, 0x40010e6a +.set CYDEV_UCFG_B0_P7_U0_DCFG6, 0x40010e6c +.set CYDEV_UCFG_B0_P7_U0_DCFG7, 0x40010e6e +.set CYDEV_UCFG_B0_P7_U1_BASE, 0x40010e80 +.set CYDEV_UCFG_B0_P7_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT0, 0x40010e80 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT1, 0x40010e84 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT2, 0x40010e88 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT3, 0x40010e8c +.set CYDEV_UCFG_B0_P7_U1_PLD_IT4, 0x40010e90 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT5, 0x40010e94 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT6, 0x40010e98 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT7, 0x40010e9c +.set CYDEV_UCFG_B0_P7_U1_PLD_IT8, 0x40010ea0 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT9, 0x40010ea4 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT10, 0x40010ea8 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT11, 0x40010eac +.set CYDEV_UCFG_B0_P7_U1_PLD_ORT0, 0x40010eb0 +.set CYDEV_UCFG_B0_P7_U1_PLD_ORT1, 0x40010eb2 +.set CYDEV_UCFG_B0_P7_U1_PLD_ORT2, 0x40010eb4 +.set CYDEV_UCFG_B0_P7_U1_PLD_ORT3, 0x40010eb6 +.set CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST, 0x40010eb8 +.set CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB, 0x40010eba +.set CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET, 0x40010ebc +.set CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS, 0x40010ebe +.set CYDEV_UCFG_B0_P7_U1_CFG0, 0x40010ec0 +.set CYDEV_UCFG_B0_P7_U1_CFG1, 0x40010ec1 +.set CYDEV_UCFG_B0_P7_U1_CFG2, 0x40010ec2 +.set CYDEV_UCFG_B0_P7_U1_CFG3, 0x40010ec3 +.set CYDEV_UCFG_B0_P7_U1_CFG4, 0x40010ec4 +.set CYDEV_UCFG_B0_P7_U1_CFG5, 0x40010ec5 +.set CYDEV_UCFG_B0_P7_U1_CFG6, 0x40010ec6 +.set CYDEV_UCFG_B0_P7_U1_CFG7, 0x40010ec7 +.set CYDEV_UCFG_B0_P7_U1_CFG8, 0x40010ec8 +.set CYDEV_UCFG_B0_P7_U1_CFG9, 0x40010ec9 +.set CYDEV_UCFG_B0_P7_U1_CFG10, 0x40010eca +.set CYDEV_UCFG_B0_P7_U1_CFG11, 0x40010ecb +.set CYDEV_UCFG_B0_P7_U1_CFG12, 0x40010ecc +.set CYDEV_UCFG_B0_P7_U1_CFG13, 0x40010ecd +.set CYDEV_UCFG_B0_P7_U1_CFG14, 0x40010ece +.set CYDEV_UCFG_B0_P7_U1_CFG15, 0x40010ecf +.set CYDEV_UCFG_B0_P7_U1_CFG16, 0x40010ed0 +.set CYDEV_UCFG_B0_P7_U1_CFG17, 0x40010ed1 +.set CYDEV_UCFG_B0_P7_U1_CFG18, 0x40010ed2 +.set CYDEV_UCFG_B0_P7_U1_CFG19, 0x40010ed3 +.set CYDEV_UCFG_B0_P7_U1_CFG20, 0x40010ed4 +.set CYDEV_UCFG_B0_P7_U1_CFG21, 0x40010ed5 +.set CYDEV_UCFG_B0_P7_U1_CFG22, 0x40010ed6 +.set CYDEV_UCFG_B0_P7_U1_CFG23, 0x40010ed7 +.set CYDEV_UCFG_B0_P7_U1_CFG24, 0x40010ed8 +.set CYDEV_UCFG_B0_P7_U1_CFG25, 0x40010ed9 +.set CYDEV_UCFG_B0_P7_U1_CFG26, 0x40010eda +.set CYDEV_UCFG_B0_P7_U1_CFG27, 0x40010edb +.set CYDEV_UCFG_B0_P7_U1_CFG28, 0x40010edc +.set CYDEV_UCFG_B0_P7_U1_CFG29, 0x40010edd +.set CYDEV_UCFG_B0_P7_U1_CFG30, 0x40010ede +.set CYDEV_UCFG_B0_P7_U1_CFG31, 0x40010edf +.set CYDEV_UCFG_B0_P7_U1_DCFG0, 0x40010ee0 +.set CYDEV_UCFG_B0_P7_U1_DCFG1, 0x40010ee2 +.set CYDEV_UCFG_B0_P7_U1_DCFG2, 0x40010ee4 +.set CYDEV_UCFG_B0_P7_U1_DCFG3, 0x40010ee6 +.set CYDEV_UCFG_B0_P7_U1_DCFG4, 0x40010ee8 +.set CYDEV_UCFG_B0_P7_U1_DCFG5, 0x40010eea +.set CYDEV_UCFG_B0_P7_U1_DCFG6, 0x40010eec +.set CYDEV_UCFG_B0_P7_U1_DCFG7, 0x40010eee +.set CYDEV_UCFG_B0_P7_ROUTE_BASE, 0x40010f00 +.set CYDEV_UCFG_B0_P7_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_BASE, 0x40011000 +.set CYDEV_UCFG_B1_SIZE, 0x00000fef +.set CYDEV_UCFG_B1_P2_BASE, 0x40011400 +.set CYDEV_UCFG_B1_P2_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P2_U0_BASE, 0x40011400 +.set CYDEV_UCFG_B1_P2_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT0, 0x40011400 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT1, 0x40011404 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT2, 0x40011408 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT3, 0x4001140c +.set CYDEV_UCFG_B1_P2_U0_PLD_IT4, 0x40011410 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT5, 0x40011414 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT6, 0x40011418 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT7, 0x4001141c +.set CYDEV_UCFG_B1_P2_U0_PLD_IT8, 0x40011420 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT9, 0x40011424 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT10, 0x40011428 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT11, 0x4001142c +.set CYDEV_UCFG_B1_P2_U0_PLD_ORT0, 0x40011430 +.set CYDEV_UCFG_B1_P2_U0_PLD_ORT1, 0x40011432 +.set CYDEV_UCFG_B1_P2_U0_PLD_ORT2, 0x40011434 +.set CYDEV_UCFG_B1_P2_U0_PLD_ORT3, 0x40011436 +.set CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST, 0x40011438 +.set CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB, 0x4001143a +.set CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET, 0x4001143c +.set CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS, 0x4001143e +.set CYDEV_UCFG_B1_P2_U0_CFG0, 0x40011440 +.set CYDEV_UCFG_B1_P2_U0_CFG1, 0x40011441 +.set CYDEV_UCFG_B1_P2_U0_CFG2, 0x40011442 +.set CYDEV_UCFG_B1_P2_U0_CFG3, 0x40011443 +.set CYDEV_UCFG_B1_P2_U0_CFG4, 0x40011444 +.set CYDEV_UCFG_B1_P2_U0_CFG5, 0x40011445 +.set CYDEV_UCFG_B1_P2_U0_CFG6, 0x40011446 +.set CYDEV_UCFG_B1_P2_U0_CFG7, 0x40011447 +.set CYDEV_UCFG_B1_P2_U0_CFG8, 0x40011448 +.set CYDEV_UCFG_B1_P2_U0_CFG9, 0x40011449 +.set CYDEV_UCFG_B1_P2_U0_CFG10, 0x4001144a +.set CYDEV_UCFG_B1_P2_U0_CFG11, 0x4001144b +.set CYDEV_UCFG_B1_P2_U0_CFG12, 0x4001144c +.set CYDEV_UCFG_B1_P2_U0_CFG13, 0x4001144d +.set CYDEV_UCFG_B1_P2_U0_CFG14, 0x4001144e +.set CYDEV_UCFG_B1_P2_U0_CFG15, 0x4001144f +.set CYDEV_UCFG_B1_P2_U0_CFG16, 0x40011450 +.set CYDEV_UCFG_B1_P2_U0_CFG17, 0x40011451 +.set CYDEV_UCFG_B1_P2_U0_CFG18, 0x40011452 +.set CYDEV_UCFG_B1_P2_U0_CFG19, 0x40011453 +.set CYDEV_UCFG_B1_P2_U0_CFG20, 0x40011454 +.set CYDEV_UCFG_B1_P2_U0_CFG21, 0x40011455 +.set CYDEV_UCFG_B1_P2_U0_CFG22, 0x40011456 +.set CYDEV_UCFG_B1_P2_U0_CFG23, 0x40011457 +.set CYDEV_UCFG_B1_P2_U0_CFG24, 0x40011458 +.set CYDEV_UCFG_B1_P2_U0_CFG25, 0x40011459 +.set CYDEV_UCFG_B1_P2_U0_CFG26, 0x4001145a +.set CYDEV_UCFG_B1_P2_U0_CFG27, 0x4001145b +.set CYDEV_UCFG_B1_P2_U0_CFG28, 0x4001145c +.set CYDEV_UCFG_B1_P2_U0_CFG29, 0x4001145d +.set CYDEV_UCFG_B1_P2_U0_CFG30, 0x4001145e +.set CYDEV_UCFG_B1_P2_U0_CFG31, 0x4001145f +.set CYDEV_UCFG_B1_P2_U0_DCFG0, 0x40011460 +.set CYDEV_UCFG_B1_P2_U0_DCFG1, 0x40011462 +.set CYDEV_UCFG_B1_P2_U0_DCFG2, 0x40011464 +.set CYDEV_UCFG_B1_P2_U0_DCFG3, 0x40011466 +.set CYDEV_UCFG_B1_P2_U0_DCFG4, 0x40011468 +.set CYDEV_UCFG_B1_P2_U0_DCFG5, 0x4001146a +.set CYDEV_UCFG_B1_P2_U0_DCFG6, 0x4001146c +.set CYDEV_UCFG_B1_P2_U0_DCFG7, 0x4001146e +.set CYDEV_UCFG_B1_P2_U1_BASE, 0x40011480 +.set CYDEV_UCFG_B1_P2_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT0, 0x40011480 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT1, 0x40011484 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT2, 0x40011488 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT3, 0x4001148c +.set CYDEV_UCFG_B1_P2_U1_PLD_IT4, 0x40011490 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT5, 0x40011494 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT6, 0x40011498 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT7, 0x4001149c +.set CYDEV_UCFG_B1_P2_U1_PLD_IT8, 0x400114a0 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT9, 0x400114a4 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT10, 0x400114a8 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT11, 0x400114ac +.set CYDEV_UCFG_B1_P2_U1_PLD_ORT0, 0x400114b0 +.set CYDEV_UCFG_B1_P2_U1_PLD_ORT1, 0x400114b2 +.set CYDEV_UCFG_B1_P2_U1_PLD_ORT2, 0x400114b4 +.set CYDEV_UCFG_B1_P2_U1_PLD_ORT3, 0x400114b6 +.set CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST, 0x400114b8 +.set CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB, 0x400114ba +.set CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET, 0x400114bc +.set CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS, 0x400114be +.set CYDEV_UCFG_B1_P2_U1_CFG0, 0x400114c0 +.set CYDEV_UCFG_B1_P2_U1_CFG1, 0x400114c1 +.set CYDEV_UCFG_B1_P2_U1_CFG2, 0x400114c2 +.set CYDEV_UCFG_B1_P2_U1_CFG3, 0x400114c3 +.set CYDEV_UCFG_B1_P2_U1_CFG4, 0x400114c4 +.set CYDEV_UCFG_B1_P2_U1_CFG5, 0x400114c5 +.set CYDEV_UCFG_B1_P2_U1_CFG6, 0x400114c6 +.set CYDEV_UCFG_B1_P2_U1_CFG7, 0x400114c7 +.set CYDEV_UCFG_B1_P2_U1_CFG8, 0x400114c8 +.set CYDEV_UCFG_B1_P2_U1_CFG9, 0x400114c9 +.set CYDEV_UCFG_B1_P2_U1_CFG10, 0x400114ca +.set CYDEV_UCFG_B1_P2_U1_CFG11, 0x400114cb +.set CYDEV_UCFG_B1_P2_U1_CFG12, 0x400114cc +.set CYDEV_UCFG_B1_P2_U1_CFG13, 0x400114cd +.set CYDEV_UCFG_B1_P2_U1_CFG14, 0x400114ce +.set CYDEV_UCFG_B1_P2_U1_CFG15, 0x400114cf +.set CYDEV_UCFG_B1_P2_U1_CFG16, 0x400114d0 +.set CYDEV_UCFG_B1_P2_U1_CFG17, 0x400114d1 +.set CYDEV_UCFG_B1_P2_U1_CFG18, 0x400114d2 +.set CYDEV_UCFG_B1_P2_U1_CFG19, 0x400114d3 +.set CYDEV_UCFG_B1_P2_U1_CFG20, 0x400114d4 +.set CYDEV_UCFG_B1_P2_U1_CFG21, 0x400114d5 +.set CYDEV_UCFG_B1_P2_U1_CFG22, 0x400114d6 +.set CYDEV_UCFG_B1_P2_U1_CFG23, 0x400114d7 +.set CYDEV_UCFG_B1_P2_U1_CFG24, 0x400114d8 +.set CYDEV_UCFG_B1_P2_U1_CFG25, 0x400114d9 +.set CYDEV_UCFG_B1_P2_U1_CFG26, 0x400114da +.set CYDEV_UCFG_B1_P2_U1_CFG27, 0x400114db +.set CYDEV_UCFG_B1_P2_U1_CFG28, 0x400114dc +.set CYDEV_UCFG_B1_P2_U1_CFG29, 0x400114dd +.set CYDEV_UCFG_B1_P2_U1_CFG30, 0x400114de +.set CYDEV_UCFG_B1_P2_U1_CFG31, 0x400114df +.set CYDEV_UCFG_B1_P2_U1_DCFG0, 0x400114e0 +.set CYDEV_UCFG_B1_P2_U1_DCFG1, 0x400114e2 +.set CYDEV_UCFG_B1_P2_U1_DCFG2, 0x400114e4 +.set CYDEV_UCFG_B1_P2_U1_DCFG3, 0x400114e6 +.set CYDEV_UCFG_B1_P2_U1_DCFG4, 0x400114e8 +.set CYDEV_UCFG_B1_P2_U1_DCFG5, 0x400114ea +.set CYDEV_UCFG_B1_P2_U1_DCFG6, 0x400114ec +.set CYDEV_UCFG_B1_P2_U1_DCFG7, 0x400114ee +.set CYDEV_UCFG_B1_P2_ROUTE_BASE, 0x40011500 +.set CYDEV_UCFG_B1_P2_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_P3_BASE, 0x40011600 +.set CYDEV_UCFG_B1_P3_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P3_U0_BASE, 0x40011600 +.set CYDEV_UCFG_B1_P3_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT0, 0x40011600 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT1, 0x40011604 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT2, 0x40011608 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT3, 0x4001160c +.set CYDEV_UCFG_B1_P3_U0_PLD_IT4, 0x40011610 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT5, 0x40011614 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT6, 0x40011618 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT7, 0x4001161c +.set CYDEV_UCFG_B1_P3_U0_PLD_IT8, 0x40011620 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT9, 0x40011624 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT10, 0x40011628 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT11, 0x4001162c +.set CYDEV_UCFG_B1_P3_U0_PLD_ORT0, 0x40011630 +.set CYDEV_UCFG_B1_P3_U0_PLD_ORT1, 0x40011632 +.set CYDEV_UCFG_B1_P3_U0_PLD_ORT2, 0x40011634 +.set CYDEV_UCFG_B1_P3_U0_PLD_ORT3, 0x40011636 +.set CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST, 0x40011638 +.set CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB, 0x4001163a +.set CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET, 0x4001163c +.set CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS, 0x4001163e +.set CYDEV_UCFG_B1_P3_U0_CFG0, 0x40011640 +.set CYDEV_UCFG_B1_P3_U0_CFG1, 0x40011641 +.set CYDEV_UCFG_B1_P3_U0_CFG2, 0x40011642 +.set CYDEV_UCFG_B1_P3_U0_CFG3, 0x40011643 +.set CYDEV_UCFG_B1_P3_U0_CFG4, 0x40011644 +.set CYDEV_UCFG_B1_P3_U0_CFG5, 0x40011645 +.set CYDEV_UCFG_B1_P3_U0_CFG6, 0x40011646 +.set CYDEV_UCFG_B1_P3_U0_CFG7, 0x40011647 +.set CYDEV_UCFG_B1_P3_U0_CFG8, 0x40011648 +.set CYDEV_UCFG_B1_P3_U0_CFG9, 0x40011649 +.set CYDEV_UCFG_B1_P3_U0_CFG10, 0x4001164a +.set CYDEV_UCFG_B1_P3_U0_CFG11, 0x4001164b +.set CYDEV_UCFG_B1_P3_U0_CFG12, 0x4001164c +.set CYDEV_UCFG_B1_P3_U0_CFG13, 0x4001164d +.set CYDEV_UCFG_B1_P3_U0_CFG14, 0x4001164e +.set CYDEV_UCFG_B1_P3_U0_CFG15, 0x4001164f +.set CYDEV_UCFG_B1_P3_U0_CFG16, 0x40011650 +.set CYDEV_UCFG_B1_P3_U0_CFG17, 0x40011651 +.set CYDEV_UCFG_B1_P3_U0_CFG18, 0x40011652 +.set CYDEV_UCFG_B1_P3_U0_CFG19, 0x40011653 +.set CYDEV_UCFG_B1_P3_U0_CFG20, 0x40011654 +.set CYDEV_UCFG_B1_P3_U0_CFG21, 0x40011655 +.set CYDEV_UCFG_B1_P3_U0_CFG22, 0x40011656 +.set CYDEV_UCFG_B1_P3_U0_CFG23, 0x40011657 +.set CYDEV_UCFG_B1_P3_U0_CFG24, 0x40011658 +.set CYDEV_UCFG_B1_P3_U0_CFG25, 0x40011659 +.set CYDEV_UCFG_B1_P3_U0_CFG26, 0x4001165a +.set CYDEV_UCFG_B1_P3_U0_CFG27, 0x4001165b +.set CYDEV_UCFG_B1_P3_U0_CFG28, 0x4001165c +.set CYDEV_UCFG_B1_P3_U0_CFG29, 0x4001165d +.set CYDEV_UCFG_B1_P3_U0_CFG30, 0x4001165e +.set CYDEV_UCFG_B1_P3_U0_CFG31, 0x4001165f +.set CYDEV_UCFG_B1_P3_U0_DCFG0, 0x40011660 +.set CYDEV_UCFG_B1_P3_U0_DCFG1, 0x40011662 +.set CYDEV_UCFG_B1_P3_U0_DCFG2, 0x40011664 +.set CYDEV_UCFG_B1_P3_U0_DCFG3, 0x40011666 +.set CYDEV_UCFG_B1_P3_U0_DCFG4, 0x40011668 +.set CYDEV_UCFG_B1_P3_U0_DCFG5, 0x4001166a +.set CYDEV_UCFG_B1_P3_U0_DCFG6, 0x4001166c +.set CYDEV_UCFG_B1_P3_U0_DCFG7, 0x4001166e +.set CYDEV_UCFG_B1_P3_U1_BASE, 0x40011680 +.set CYDEV_UCFG_B1_P3_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT0, 0x40011680 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT1, 0x40011684 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT2, 0x40011688 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT3, 0x4001168c +.set CYDEV_UCFG_B1_P3_U1_PLD_IT4, 0x40011690 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT5, 0x40011694 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT6, 0x40011698 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT7, 0x4001169c +.set CYDEV_UCFG_B1_P3_U1_PLD_IT8, 0x400116a0 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT9, 0x400116a4 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT10, 0x400116a8 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT11, 0x400116ac +.set CYDEV_UCFG_B1_P3_U1_PLD_ORT0, 0x400116b0 +.set CYDEV_UCFG_B1_P3_U1_PLD_ORT1, 0x400116b2 +.set CYDEV_UCFG_B1_P3_U1_PLD_ORT2, 0x400116b4 +.set CYDEV_UCFG_B1_P3_U1_PLD_ORT3, 0x400116b6 +.set CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST, 0x400116b8 +.set CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB, 0x400116ba +.set CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET, 0x400116bc +.set CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS, 0x400116be +.set CYDEV_UCFG_B1_P3_U1_CFG0, 0x400116c0 +.set CYDEV_UCFG_B1_P3_U1_CFG1, 0x400116c1 +.set CYDEV_UCFG_B1_P3_U1_CFG2, 0x400116c2 +.set CYDEV_UCFG_B1_P3_U1_CFG3, 0x400116c3 +.set CYDEV_UCFG_B1_P3_U1_CFG4, 0x400116c4 +.set CYDEV_UCFG_B1_P3_U1_CFG5, 0x400116c5 +.set CYDEV_UCFG_B1_P3_U1_CFG6, 0x400116c6 +.set CYDEV_UCFG_B1_P3_U1_CFG7, 0x400116c7 +.set CYDEV_UCFG_B1_P3_U1_CFG8, 0x400116c8 +.set CYDEV_UCFG_B1_P3_U1_CFG9, 0x400116c9 +.set CYDEV_UCFG_B1_P3_U1_CFG10, 0x400116ca +.set CYDEV_UCFG_B1_P3_U1_CFG11, 0x400116cb +.set CYDEV_UCFG_B1_P3_U1_CFG12, 0x400116cc +.set CYDEV_UCFG_B1_P3_U1_CFG13, 0x400116cd +.set CYDEV_UCFG_B1_P3_U1_CFG14, 0x400116ce +.set CYDEV_UCFG_B1_P3_U1_CFG15, 0x400116cf +.set CYDEV_UCFG_B1_P3_U1_CFG16, 0x400116d0 +.set CYDEV_UCFG_B1_P3_U1_CFG17, 0x400116d1 +.set CYDEV_UCFG_B1_P3_U1_CFG18, 0x400116d2 +.set CYDEV_UCFG_B1_P3_U1_CFG19, 0x400116d3 +.set CYDEV_UCFG_B1_P3_U1_CFG20, 0x400116d4 +.set CYDEV_UCFG_B1_P3_U1_CFG21, 0x400116d5 +.set CYDEV_UCFG_B1_P3_U1_CFG22, 0x400116d6 +.set CYDEV_UCFG_B1_P3_U1_CFG23, 0x400116d7 +.set CYDEV_UCFG_B1_P3_U1_CFG24, 0x400116d8 +.set CYDEV_UCFG_B1_P3_U1_CFG25, 0x400116d9 +.set CYDEV_UCFG_B1_P3_U1_CFG26, 0x400116da +.set CYDEV_UCFG_B1_P3_U1_CFG27, 0x400116db +.set CYDEV_UCFG_B1_P3_U1_CFG28, 0x400116dc +.set CYDEV_UCFG_B1_P3_U1_CFG29, 0x400116dd +.set CYDEV_UCFG_B1_P3_U1_CFG30, 0x400116de +.set CYDEV_UCFG_B1_P3_U1_CFG31, 0x400116df +.set CYDEV_UCFG_B1_P3_U1_DCFG0, 0x400116e0 +.set CYDEV_UCFG_B1_P3_U1_DCFG1, 0x400116e2 +.set CYDEV_UCFG_B1_P3_U1_DCFG2, 0x400116e4 +.set CYDEV_UCFG_B1_P3_U1_DCFG3, 0x400116e6 +.set CYDEV_UCFG_B1_P3_U1_DCFG4, 0x400116e8 +.set CYDEV_UCFG_B1_P3_U1_DCFG5, 0x400116ea +.set CYDEV_UCFG_B1_P3_U1_DCFG6, 0x400116ec +.set CYDEV_UCFG_B1_P3_U1_DCFG7, 0x400116ee +.set CYDEV_UCFG_B1_P3_ROUTE_BASE, 0x40011700 +.set CYDEV_UCFG_B1_P3_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_P4_BASE, 0x40011800 +.set CYDEV_UCFG_B1_P4_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P4_U0_BASE, 0x40011800 +.set CYDEV_UCFG_B1_P4_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT0, 0x40011800 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT1, 0x40011804 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT2, 0x40011808 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT3, 0x4001180c +.set CYDEV_UCFG_B1_P4_U0_PLD_IT4, 0x40011810 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT5, 0x40011814 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT6, 0x40011818 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT7, 0x4001181c +.set CYDEV_UCFG_B1_P4_U0_PLD_IT8, 0x40011820 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT9, 0x40011824 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT10, 0x40011828 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT11, 0x4001182c +.set CYDEV_UCFG_B1_P4_U0_PLD_ORT0, 0x40011830 +.set CYDEV_UCFG_B1_P4_U0_PLD_ORT1, 0x40011832 +.set CYDEV_UCFG_B1_P4_U0_PLD_ORT2, 0x40011834 +.set CYDEV_UCFG_B1_P4_U0_PLD_ORT3, 0x40011836 +.set CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST, 0x40011838 +.set CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB, 0x4001183a +.set CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET, 0x4001183c +.set CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS, 0x4001183e +.set CYDEV_UCFG_B1_P4_U0_CFG0, 0x40011840 +.set CYDEV_UCFG_B1_P4_U0_CFG1, 0x40011841 +.set CYDEV_UCFG_B1_P4_U0_CFG2, 0x40011842 +.set CYDEV_UCFG_B1_P4_U0_CFG3, 0x40011843 +.set CYDEV_UCFG_B1_P4_U0_CFG4, 0x40011844 +.set CYDEV_UCFG_B1_P4_U0_CFG5, 0x40011845 +.set CYDEV_UCFG_B1_P4_U0_CFG6, 0x40011846 +.set CYDEV_UCFG_B1_P4_U0_CFG7, 0x40011847 +.set CYDEV_UCFG_B1_P4_U0_CFG8, 0x40011848 +.set CYDEV_UCFG_B1_P4_U0_CFG9, 0x40011849 +.set CYDEV_UCFG_B1_P4_U0_CFG10, 0x4001184a +.set CYDEV_UCFG_B1_P4_U0_CFG11, 0x4001184b +.set CYDEV_UCFG_B1_P4_U0_CFG12, 0x4001184c +.set CYDEV_UCFG_B1_P4_U0_CFG13, 0x4001184d +.set CYDEV_UCFG_B1_P4_U0_CFG14, 0x4001184e +.set CYDEV_UCFG_B1_P4_U0_CFG15, 0x4001184f +.set CYDEV_UCFG_B1_P4_U0_CFG16, 0x40011850 +.set CYDEV_UCFG_B1_P4_U0_CFG17, 0x40011851 +.set CYDEV_UCFG_B1_P4_U0_CFG18, 0x40011852 +.set CYDEV_UCFG_B1_P4_U0_CFG19, 0x40011853 +.set CYDEV_UCFG_B1_P4_U0_CFG20, 0x40011854 +.set CYDEV_UCFG_B1_P4_U0_CFG21, 0x40011855 +.set CYDEV_UCFG_B1_P4_U0_CFG22, 0x40011856 +.set CYDEV_UCFG_B1_P4_U0_CFG23, 0x40011857 +.set CYDEV_UCFG_B1_P4_U0_CFG24, 0x40011858 +.set CYDEV_UCFG_B1_P4_U0_CFG25, 0x40011859 +.set CYDEV_UCFG_B1_P4_U0_CFG26, 0x4001185a +.set CYDEV_UCFG_B1_P4_U0_CFG27, 0x4001185b +.set CYDEV_UCFG_B1_P4_U0_CFG28, 0x4001185c +.set CYDEV_UCFG_B1_P4_U0_CFG29, 0x4001185d +.set CYDEV_UCFG_B1_P4_U0_CFG30, 0x4001185e +.set CYDEV_UCFG_B1_P4_U0_CFG31, 0x4001185f +.set CYDEV_UCFG_B1_P4_U0_DCFG0, 0x40011860 +.set CYDEV_UCFG_B1_P4_U0_DCFG1, 0x40011862 +.set CYDEV_UCFG_B1_P4_U0_DCFG2, 0x40011864 +.set CYDEV_UCFG_B1_P4_U0_DCFG3, 0x40011866 +.set CYDEV_UCFG_B1_P4_U0_DCFG4, 0x40011868 +.set CYDEV_UCFG_B1_P4_U0_DCFG5, 0x4001186a +.set CYDEV_UCFG_B1_P4_U0_DCFG6, 0x4001186c +.set CYDEV_UCFG_B1_P4_U0_DCFG7, 0x4001186e +.set CYDEV_UCFG_B1_P4_U1_BASE, 0x40011880 +.set CYDEV_UCFG_B1_P4_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT0, 0x40011880 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT1, 0x40011884 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT2, 0x40011888 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT3, 0x4001188c +.set CYDEV_UCFG_B1_P4_U1_PLD_IT4, 0x40011890 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT5, 0x40011894 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT6, 0x40011898 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT7, 0x4001189c +.set CYDEV_UCFG_B1_P4_U1_PLD_IT8, 0x400118a0 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT9, 0x400118a4 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT10, 0x400118a8 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT11, 0x400118ac +.set CYDEV_UCFG_B1_P4_U1_PLD_ORT0, 0x400118b0 +.set CYDEV_UCFG_B1_P4_U1_PLD_ORT1, 0x400118b2 +.set CYDEV_UCFG_B1_P4_U1_PLD_ORT2, 0x400118b4 +.set CYDEV_UCFG_B1_P4_U1_PLD_ORT3, 0x400118b6 +.set CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST, 0x400118b8 +.set CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB, 0x400118ba +.set CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET, 0x400118bc +.set CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS, 0x400118be +.set CYDEV_UCFG_B1_P4_U1_CFG0, 0x400118c0 +.set CYDEV_UCFG_B1_P4_U1_CFG1, 0x400118c1 +.set CYDEV_UCFG_B1_P4_U1_CFG2, 0x400118c2 +.set CYDEV_UCFG_B1_P4_U1_CFG3, 0x400118c3 +.set CYDEV_UCFG_B1_P4_U1_CFG4, 0x400118c4 +.set CYDEV_UCFG_B1_P4_U1_CFG5, 0x400118c5 +.set CYDEV_UCFG_B1_P4_U1_CFG6, 0x400118c6 +.set CYDEV_UCFG_B1_P4_U1_CFG7, 0x400118c7 +.set CYDEV_UCFG_B1_P4_U1_CFG8, 0x400118c8 +.set CYDEV_UCFG_B1_P4_U1_CFG9, 0x400118c9 +.set CYDEV_UCFG_B1_P4_U1_CFG10, 0x400118ca +.set CYDEV_UCFG_B1_P4_U1_CFG11, 0x400118cb +.set CYDEV_UCFG_B1_P4_U1_CFG12, 0x400118cc +.set CYDEV_UCFG_B1_P4_U1_CFG13, 0x400118cd +.set CYDEV_UCFG_B1_P4_U1_CFG14, 0x400118ce +.set CYDEV_UCFG_B1_P4_U1_CFG15, 0x400118cf +.set CYDEV_UCFG_B1_P4_U1_CFG16, 0x400118d0 +.set CYDEV_UCFG_B1_P4_U1_CFG17, 0x400118d1 +.set CYDEV_UCFG_B1_P4_U1_CFG18, 0x400118d2 +.set CYDEV_UCFG_B1_P4_U1_CFG19, 0x400118d3 +.set CYDEV_UCFG_B1_P4_U1_CFG20, 0x400118d4 +.set CYDEV_UCFG_B1_P4_U1_CFG21, 0x400118d5 +.set CYDEV_UCFG_B1_P4_U1_CFG22, 0x400118d6 +.set CYDEV_UCFG_B1_P4_U1_CFG23, 0x400118d7 +.set CYDEV_UCFG_B1_P4_U1_CFG24, 0x400118d8 +.set CYDEV_UCFG_B1_P4_U1_CFG25, 0x400118d9 +.set CYDEV_UCFG_B1_P4_U1_CFG26, 0x400118da +.set CYDEV_UCFG_B1_P4_U1_CFG27, 0x400118db +.set CYDEV_UCFG_B1_P4_U1_CFG28, 0x400118dc +.set CYDEV_UCFG_B1_P4_U1_CFG29, 0x400118dd +.set CYDEV_UCFG_B1_P4_U1_CFG30, 0x400118de +.set CYDEV_UCFG_B1_P4_U1_CFG31, 0x400118df +.set CYDEV_UCFG_B1_P4_U1_DCFG0, 0x400118e0 +.set CYDEV_UCFG_B1_P4_U1_DCFG1, 0x400118e2 +.set CYDEV_UCFG_B1_P4_U1_DCFG2, 0x400118e4 +.set CYDEV_UCFG_B1_P4_U1_DCFG3, 0x400118e6 +.set CYDEV_UCFG_B1_P4_U1_DCFG4, 0x400118e8 +.set CYDEV_UCFG_B1_P4_U1_DCFG5, 0x400118ea +.set CYDEV_UCFG_B1_P4_U1_DCFG6, 0x400118ec +.set CYDEV_UCFG_B1_P4_U1_DCFG7, 0x400118ee +.set CYDEV_UCFG_B1_P4_ROUTE_BASE, 0x40011900 +.set CYDEV_UCFG_B1_P4_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_P5_BASE, 0x40011a00 +.set CYDEV_UCFG_B1_P5_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P5_U0_BASE, 0x40011a00 +.set CYDEV_UCFG_B1_P5_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT0, 0x40011a00 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT1, 0x40011a04 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT2, 0x40011a08 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT3, 0x40011a0c +.set CYDEV_UCFG_B1_P5_U0_PLD_IT4, 0x40011a10 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT5, 0x40011a14 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT6, 0x40011a18 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT7, 0x40011a1c +.set CYDEV_UCFG_B1_P5_U0_PLD_IT8, 0x40011a20 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT9, 0x40011a24 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT10, 0x40011a28 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT11, 0x40011a2c +.set CYDEV_UCFG_B1_P5_U0_PLD_ORT0, 0x40011a30 +.set CYDEV_UCFG_B1_P5_U0_PLD_ORT1, 0x40011a32 +.set CYDEV_UCFG_B1_P5_U0_PLD_ORT2, 0x40011a34 +.set CYDEV_UCFG_B1_P5_U0_PLD_ORT3, 0x40011a36 +.set CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST, 0x40011a38 +.set CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB, 0x40011a3a +.set CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET, 0x40011a3c +.set CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS, 0x40011a3e +.set CYDEV_UCFG_B1_P5_U0_CFG0, 0x40011a40 +.set CYDEV_UCFG_B1_P5_U0_CFG1, 0x40011a41 +.set CYDEV_UCFG_B1_P5_U0_CFG2, 0x40011a42 +.set CYDEV_UCFG_B1_P5_U0_CFG3, 0x40011a43 +.set CYDEV_UCFG_B1_P5_U0_CFG4, 0x40011a44 +.set CYDEV_UCFG_B1_P5_U0_CFG5, 0x40011a45 +.set CYDEV_UCFG_B1_P5_U0_CFG6, 0x40011a46 +.set CYDEV_UCFG_B1_P5_U0_CFG7, 0x40011a47 +.set CYDEV_UCFG_B1_P5_U0_CFG8, 0x40011a48 +.set CYDEV_UCFG_B1_P5_U0_CFG9, 0x40011a49 +.set CYDEV_UCFG_B1_P5_U0_CFG10, 0x40011a4a +.set CYDEV_UCFG_B1_P5_U0_CFG11, 0x40011a4b +.set CYDEV_UCFG_B1_P5_U0_CFG12, 0x40011a4c +.set CYDEV_UCFG_B1_P5_U0_CFG13, 0x40011a4d +.set CYDEV_UCFG_B1_P5_U0_CFG14, 0x40011a4e +.set CYDEV_UCFG_B1_P5_U0_CFG15, 0x40011a4f +.set CYDEV_UCFG_B1_P5_U0_CFG16, 0x40011a50 +.set CYDEV_UCFG_B1_P5_U0_CFG17, 0x40011a51 +.set CYDEV_UCFG_B1_P5_U0_CFG18, 0x40011a52 +.set CYDEV_UCFG_B1_P5_U0_CFG19, 0x40011a53 +.set CYDEV_UCFG_B1_P5_U0_CFG20, 0x40011a54 +.set CYDEV_UCFG_B1_P5_U0_CFG21, 0x40011a55 +.set CYDEV_UCFG_B1_P5_U0_CFG22, 0x40011a56 +.set CYDEV_UCFG_B1_P5_U0_CFG23, 0x40011a57 +.set CYDEV_UCFG_B1_P5_U0_CFG24, 0x40011a58 +.set CYDEV_UCFG_B1_P5_U0_CFG25, 0x40011a59 +.set CYDEV_UCFG_B1_P5_U0_CFG26, 0x40011a5a +.set CYDEV_UCFG_B1_P5_U0_CFG27, 0x40011a5b +.set CYDEV_UCFG_B1_P5_U0_CFG28, 0x40011a5c +.set CYDEV_UCFG_B1_P5_U0_CFG29, 0x40011a5d +.set CYDEV_UCFG_B1_P5_U0_CFG30, 0x40011a5e +.set CYDEV_UCFG_B1_P5_U0_CFG31, 0x40011a5f +.set CYDEV_UCFG_B1_P5_U0_DCFG0, 0x40011a60 +.set CYDEV_UCFG_B1_P5_U0_DCFG1, 0x40011a62 +.set CYDEV_UCFG_B1_P5_U0_DCFG2, 0x40011a64 +.set CYDEV_UCFG_B1_P5_U0_DCFG3, 0x40011a66 +.set CYDEV_UCFG_B1_P5_U0_DCFG4, 0x40011a68 +.set CYDEV_UCFG_B1_P5_U0_DCFG5, 0x40011a6a +.set CYDEV_UCFG_B1_P5_U0_DCFG6, 0x40011a6c +.set CYDEV_UCFG_B1_P5_U0_DCFG7, 0x40011a6e +.set CYDEV_UCFG_B1_P5_U1_BASE, 0x40011a80 +.set CYDEV_UCFG_B1_P5_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT0, 0x40011a80 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT1, 0x40011a84 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT2, 0x40011a88 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT3, 0x40011a8c +.set CYDEV_UCFG_B1_P5_U1_PLD_IT4, 0x40011a90 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT5, 0x40011a94 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT6, 0x40011a98 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT7, 0x40011a9c +.set CYDEV_UCFG_B1_P5_U1_PLD_IT8, 0x40011aa0 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT9, 0x40011aa4 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT10, 0x40011aa8 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT11, 0x40011aac +.set CYDEV_UCFG_B1_P5_U1_PLD_ORT0, 0x40011ab0 +.set CYDEV_UCFG_B1_P5_U1_PLD_ORT1, 0x40011ab2 +.set CYDEV_UCFG_B1_P5_U1_PLD_ORT2, 0x40011ab4 +.set CYDEV_UCFG_B1_P5_U1_PLD_ORT3, 0x40011ab6 +.set CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST, 0x40011ab8 +.set CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB, 0x40011aba +.set CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET, 0x40011abc +.set CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS, 0x40011abe +.set CYDEV_UCFG_B1_P5_U1_CFG0, 0x40011ac0 +.set CYDEV_UCFG_B1_P5_U1_CFG1, 0x40011ac1 +.set CYDEV_UCFG_B1_P5_U1_CFG2, 0x40011ac2 +.set CYDEV_UCFG_B1_P5_U1_CFG3, 0x40011ac3 +.set CYDEV_UCFG_B1_P5_U1_CFG4, 0x40011ac4 +.set CYDEV_UCFG_B1_P5_U1_CFG5, 0x40011ac5 +.set CYDEV_UCFG_B1_P5_U1_CFG6, 0x40011ac6 +.set CYDEV_UCFG_B1_P5_U1_CFG7, 0x40011ac7 +.set CYDEV_UCFG_B1_P5_U1_CFG8, 0x40011ac8 +.set CYDEV_UCFG_B1_P5_U1_CFG9, 0x40011ac9 +.set CYDEV_UCFG_B1_P5_U1_CFG10, 0x40011aca +.set CYDEV_UCFG_B1_P5_U1_CFG11, 0x40011acb +.set CYDEV_UCFG_B1_P5_U1_CFG12, 0x40011acc +.set CYDEV_UCFG_B1_P5_U1_CFG13, 0x40011acd +.set CYDEV_UCFG_B1_P5_U1_CFG14, 0x40011ace +.set CYDEV_UCFG_B1_P5_U1_CFG15, 0x40011acf +.set CYDEV_UCFG_B1_P5_U1_CFG16, 0x40011ad0 +.set CYDEV_UCFG_B1_P5_U1_CFG17, 0x40011ad1 +.set CYDEV_UCFG_B1_P5_U1_CFG18, 0x40011ad2 +.set CYDEV_UCFG_B1_P5_U1_CFG19, 0x40011ad3 +.set CYDEV_UCFG_B1_P5_U1_CFG20, 0x40011ad4 +.set CYDEV_UCFG_B1_P5_U1_CFG21, 0x40011ad5 +.set CYDEV_UCFG_B1_P5_U1_CFG22, 0x40011ad6 +.set CYDEV_UCFG_B1_P5_U1_CFG23, 0x40011ad7 +.set CYDEV_UCFG_B1_P5_U1_CFG24, 0x40011ad8 +.set CYDEV_UCFG_B1_P5_U1_CFG25, 0x40011ad9 +.set CYDEV_UCFG_B1_P5_U1_CFG26, 0x40011ada +.set CYDEV_UCFG_B1_P5_U1_CFG27, 0x40011adb +.set CYDEV_UCFG_B1_P5_U1_CFG28, 0x40011adc +.set CYDEV_UCFG_B1_P5_U1_CFG29, 0x40011add +.set CYDEV_UCFG_B1_P5_U1_CFG30, 0x40011ade +.set CYDEV_UCFG_B1_P5_U1_CFG31, 0x40011adf +.set CYDEV_UCFG_B1_P5_U1_DCFG0, 0x40011ae0 +.set CYDEV_UCFG_B1_P5_U1_DCFG1, 0x40011ae2 +.set CYDEV_UCFG_B1_P5_U1_DCFG2, 0x40011ae4 +.set CYDEV_UCFG_B1_P5_U1_DCFG3, 0x40011ae6 +.set CYDEV_UCFG_B1_P5_U1_DCFG4, 0x40011ae8 +.set CYDEV_UCFG_B1_P5_U1_DCFG5, 0x40011aea +.set CYDEV_UCFG_B1_P5_U1_DCFG6, 0x40011aec +.set CYDEV_UCFG_B1_P5_U1_DCFG7, 0x40011aee +.set CYDEV_UCFG_B1_P5_ROUTE_BASE, 0x40011b00 +.set CYDEV_UCFG_B1_P5_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI0_BASE, 0x40014000 +.set CYDEV_UCFG_DSI0_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI1_BASE, 0x40014100 +.set CYDEV_UCFG_DSI1_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI2_BASE, 0x40014200 +.set CYDEV_UCFG_DSI2_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI3_BASE, 0x40014300 +.set CYDEV_UCFG_DSI3_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI4_BASE, 0x40014400 +.set CYDEV_UCFG_DSI4_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI5_BASE, 0x40014500 +.set CYDEV_UCFG_DSI5_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI6_BASE, 0x40014600 +.set CYDEV_UCFG_DSI6_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI7_BASE, 0x40014700 +.set CYDEV_UCFG_DSI7_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI8_BASE, 0x40014800 +.set CYDEV_UCFG_DSI8_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI9_BASE, 0x40014900 +.set CYDEV_UCFG_DSI9_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI12_BASE, 0x40014c00 +.set CYDEV_UCFG_DSI12_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI13_BASE, 0x40014d00 +.set CYDEV_UCFG_DSI13_SIZE, 0x000000ef +.set CYDEV_UCFG_BCTL0_BASE, 0x40015000 +.set CYDEV_UCFG_BCTL0_SIZE, 0x00000010 +.set CYDEV_UCFG_BCTL0_MDCLK_EN, 0x40015000 +.set CYDEV_UCFG_BCTL0_MBCLK_EN, 0x40015001 +.set CYDEV_UCFG_BCTL0_WAIT_CFG, 0x40015002 +.set CYDEV_UCFG_BCTL0_BANK_CTL, 0x40015003 +.set CYDEV_UCFG_BCTL0_UDB_TEST_3, 0x40015007 +.set CYDEV_UCFG_BCTL0_DCLK_EN0, 0x40015008 +.set CYDEV_UCFG_BCTL0_BCLK_EN0, 0x40015009 +.set CYDEV_UCFG_BCTL0_DCLK_EN1, 0x4001500a +.set CYDEV_UCFG_BCTL0_BCLK_EN1, 0x4001500b +.set CYDEV_UCFG_BCTL0_DCLK_EN2, 0x4001500c +.set CYDEV_UCFG_BCTL0_BCLK_EN2, 0x4001500d +.set CYDEV_UCFG_BCTL0_DCLK_EN3, 0x4001500e +.set CYDEV_UCFG_BCTL0_BCLK_EN3, 0x4001500f +.set CYDEV_UCFG_BCTL1_BASE, 0x40015010 +.set CYDEV_UCFG_BCTL1_SIZE, 0x00000010 +.set CYDEV_UCFG_BCTL1_MDCLK_EN, 0x40015010 +.set CYDEV_UCFG_BCTL1_MBCLK_EN, 0x40015011 +.set CYDEV_UCFG_BCTL1_WAIT_CFG, 0x40015012 +.set CYDEV_UCFG_BCTL1_BANK_CTL, 0x40015013 +.set CYDEV_UCFG_BCTL1_UDB_TEST_3, 0x40015017 +.set CYDEV_UCFG_BCTL1_DCLK_EN0, 0x40015018 +.set CYDEV_UCFG_BCTL1_BCLK_EN0, 0x40015019 +.set CYDEV_UCFG_BCTL1_DCLK_EN1, 0x4001501a +.set CYDEV_UCFG_BCTL1_BCLK_EN1, 0x4001501b +.set CYDEV_UCFG_BCTL1_DCLK_EN2, 0x4001501c +.set CYDEV_UCFG_BCTL1_BCLK_EN2, 0x4001501d +.set CYDEV_UCFG_BCTL1_DCLK_EN3, 0x4001501e +.set CYDEV_UCFG_BCTL1_BCLK_EN3, 0x4001501f +.set CYDEV_IDMUX_BASE, 0x40015100 +.set CYDEV_IDMUX_SIZE, 0x00000016 +.set CYDEV_IDMUX_IRQ_CTL0, 0x40015100 +.set CYDEV_IDMUX_IRQ_CTL1, 0x40015101 +.set CYDEV_IDMUX_IRQ_CTL2, 0x40015102 +.set CYDEV_IDMUX_IRQ_CTL3, 0x40015103 +.set CYDEV_IDMUX_IRQ_CTL4, 0x40015104 +.set CYDEV_IDMUX_IRQ_CTL5, 0x40015105 +.set CYDEV_IDMUX_IRQ_CTL6, 0x40015106 +.set CYDEV_IDMUX_IRQ_CTL7, 0x40015107 +.set CYDEV_IDMUX_DRQ_CTL0, 0x40015110 +.set CYDEV_IDMUX_DRQ_CTL1, 0x40015111 +.set CYDEV_IDMUX_DRQ_CTL2, 0x40015112 +.set CYDEV_IDMUX_DRQ_CTL3, 0x40015113 +.set CYDEV_IDMUX_DRQ_CTL4, 0x40015114 +.set CYDEV_IDMUX_DRQ_CTL5, 0x40015115 +.set CYDEV_CACHERAM_BASE, 0x40030000 +.set CYDEV_CACHERAM_SIZE, 0x00000400 +.set CYDEV_CACHERAM_DATA_MBASE, 0x40030000 +.set CYDEV_CACHERAM_DATA_MSIZE, 0x00000400 +.set CYDEV_SFR_BASE, 0x40050100 +.set CYDEV_SFR_SIZE, 0x000000fb +.set CYDEV_SFR_GPIO0, 0x40050180 +.set CYDEV_SFR_GPIRD0, 0x40050189 +.set CYDEV_SFR_GPIO0_SEL, 0x4005018a +.set CYDEV_SFR_GPIO1, 0x40050190 +.set CYDEV_SFR_GPIRD1, 0x40050191 +.set CYDEV_SFR_GPIO2, 0x40050198 +.set CYDEV_SFR_GPIRD2, 0x40050199 +.set CYDEV_SFR_GPIO2_SEL, 0x4005019a +.set CYDEV_SFR_GPIO1_SEL, 0x400501a2 +.set CYDEV_SFR_GPIO3, 0x400501b0 +.set CYDEV_SFR_GPIRD3, 0x400501b1 +.set CYDEV_SFR_GPIO3_SEL, 0x400501b2 +.set CYDEV_SFR_GPIO4, 0x400501c0 +.set CYDEV_SFR_GPIRD4, 0x400501c1 +.set CYDEV_SFR_GPIO4_SEL, 0x400501c2 +.set CYDEV_SFR_GPIO5, 0x400501c8 +.set CYDEV_SFR_GPIRD5, 0x400501c9 +.set CYDEV_SFR_GPIO5_SEL, 0x400501ca +.set CYDEV_SFR_GPIO6, 0x400501d8 +.set CYDEV_SFR_GPIRD6, 0x400501d9 +.set CYDEV_SFR_GPIO6_SEL, 0x400501da +.set CYDEV_SFR_GPIO12, 0x400501e8 +.set CYDEV_SFR_GPIRD12, 0x400501e9 +.set CYDEV_SFR_GPIO12_SEL, 0x400501f2 +.set CYDEV_SFR_GPIO15, 0x400501f8 +.set CYDEV_SFR_GPIRD15, 0x400501f9 +.set CYDEV_SFR_GPIO15_SEL, 0x400501fa +.set CYDEV_P3BA_BASE, 0x40050300 +.set CYDEV_P3BA_SIZE, 0x0000002b +.set CYDEV_P3BA_Y_START, 0x40050300 +.set CYDEV_P3BA_YROLL, 0x40050301 +.set CYDEV_P3BA_YCFG, 0x40050302 +.set CYDEV_P3BA_X_START1, 0x40050303 +.set CYDEV_P3BA_X_START2, 0x40050304 +.set CYDEV_P3BA_XROLL1, 0x40050305 +.set CYDEV_P3BA_XROLL2, 0x40050306 +.set CYDEV_P3BA_XINC, 0x40050307 +.set CYDEV_P3BA_XCFG, 0x40050308 +.set CYDEV_P3BA_OFFSETADDR1, 0x40050309 +.set CYDEV_P3BA_OFFSETADDR2, 0x4005030a +.set CYDEV_P3BA_OFFSETADDR3, 0x4005030b +.set CYDEV_P3BA_ABSADDR1, 0x4005030c +.set CYDEV_P3BA_ABSADDR2, 0x4005030d +.set CYDEV_P3BA_ABSADDR3, 0x4005030e +.set CYDEV_P3BA_ABSADDR4, 0x4005030f +.set CYDEV_P3BA_DATCFG1, 0x40050310 +.set CYDEV_P3BA_DATCFG2, 0x40050311 +.set CYDEV_P3BA_CMP_RSLT1, 0x40050314 +.set CYDEV_P3BA_CMP_RSLT2, 0x40050315 +.set CYDEV_P3BA_CMP_RSLT3, 0x40050316 +.set CYDEV_P3BA_CMP_RSLT4, 0x40050317 +.set CYDEV_P3BA_DATA_REG1, 0x40050318 +.set CYDEV_P3BA_DATA_REG2, 0x40050319 +.set CYDEV_P3BA_DATA_REG3, 0x4005031a +.set CYDEV_P3BA_DATA_REG4, 0x4005031b +.set CYDEV_P3BA_EXP_DATA1, 0x4005031c +.set CYDEV_P3BA_EXP_DATA2, 0x4005031d +.set CYDEV_P3BA_EXP_DATA3, 0x4005031e +.set CYDEV_P3BA_EXP_DATA4, 0x4005031f +.set CYDEV_P3BA_MSTR_HRDATA1, 0x40050320 +.set CYDEV_P3BA_MSTR_HRDATA2, 0x40050321 +.set CYDEV_P3BA_MSTR_HRDATA3, 0x40050322 +.set CYDEV_P3BA_MSTR_HRDATA4, 0x40050323 +.set CYDEV_P3BA_BIST_EN, 0x40050324 +.set CYDEV_P3BA_PHUB_MASTER_SSR, 0x40050325 +.set CYDEV_P3BA_SEQCFG1, 0x40050326 +.set CYDEV_P3BA_SEQCFG2, 0x40050327 +.set CYDEV_P3BA_Y_CURR, 0x40050328 +.set CYDEV_P3BA_X_CURR1, 0x40050329 +.set CYDEV_P3BA_X_CURR2, 0x4005032a +.set CYDEV_PANTHER_BASE, 0x40080000 +.set CYDEV_PANTHER_SIZE, 0x00000020 +.set CYDEV_PANTHER_STCALIB_CFG, 0x40080000 +.set CYDEV_PANTHER_WAITPIPE, 0x40080004 +.set CYDEV_PANTHER_TRACE_CFG, 0x40080008 +.set CYDEV_PANTHER_DBG_CFG, 0x4008000c +.set CYDEV_PANTHER_CM3_LCKRST_STAT, 0x40080018 +.set CYDEV_PANTHER_DEVICE_ID, 0x4008001c +.set CYDEV_FLSECC_BASE, 0x48000000 +.set CYDEV_FLSECC_SIZE, 0x00008000 +.set CYDEV_FLSECC_DATA_MBASE, 0x48000000 +.set CYDEV_FLSECC_DATA_MSIZE, 0x00008000 +.set CYDEV_FLSHID_BASE, 0x49000000 +.set CYDEV_FLSHID_SIZE, 0x00000200 +.set CYDEV_FLSHID_RSVD_MBASE, 0x49000000 +.set CYDEV_FLSHID_RSVD_MSIZE, 0x00000080 +.set CYDEV_FLSHID_CUST_MDATA_MBASE, 0x49000080 +.set CYDEV_FLSHID_CUST_MDATA_MSIZE, 0x00000080 +.set CYDEV_FLSHID_CUST_TABLES_BASE, 0x49000100 +.set CYDEV_FLSHID_CUST_TABLES_SIZE, 0x00000040 +.set CYDEV_FLSHID_CUST_TABLES_Y_LOC, 0x49000100 +.set CYDEV_FLSHID_CUST_TABLES_X_LOC, 0x49000101 +.set CYDEV_FLSHID_CUST_TABLES_WAFER_NUM, 0x49000102 +.set CYDEV_FLSHID_CUST_TABLES_LOT_LSB, 0x49000103 +.set CYDEV_FLSHID_CUST_TABLES_LOT_MSB, 0x49000104 +.set CYDEV_FLSHID_CUST_TABLES_WRK_WK, 0x49000105 +.set CYDEV_FLSHID_CUST_TABLES_FAB_YR, 0x49000106 +.set CYDEV_FLSHID_CUST_TABLES_MINOR, 0x49000107 +.set CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ, 0x49000108 +.set CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ, 0x49000109 +.set CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ, 0x4900010a +.set CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ, 0x4900010b +.set CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ, 0x4900010c +.set CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ, 0x4900010d +.set CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ, 0x4900010e +.set CYDEV_FLSHID_CUST_TABLES_IMO_USB, 0x4900010f +.set CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS, 0x49000110 +.set CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS, 0x49000111 +.set CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS, 0x49000112 +.set CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS, 0x49000113 +.set CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS, 0x49000114 +.set CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS, 0x49000115 +.set CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS, 0x49000116 +.set CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS, 0x49000117 +.set CYDEV_FLSHID_CUST_TABLES_DEC_M1, 0x49000118 +.set CYDEV_FLSHID_CUST_TABLES_DEC_M2, 0x49000119 +.set CYDEV_FLSHID_CUST_TABLES_DEC_M3, 0x4900011a +.set CYDEV_FLSHID_CUST_TABLES_DEC_M4, 0x4900011b +.set CYDEV_FLSHID_CUST_TABLES_DEC_M5, 0x4900011c +.set CYDEV_FLSHID_CUST_TABLES_DEC_M6, 0x4900011d +.set CYDEV_FLSHID_CUST_TABLES_DEC_M7, 0x4900011e +.set CYDEV_FLSHID_CUST_TABLES_DEC_M8, 0x4900011f +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M1, 0x49000120 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M2, 0x49000121 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M3, 0x49000122 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M4, 0x49000123 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M5, 0x49000124 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M6, 0x49000125 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M7, 0x49000126 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M8, 0x49000127 +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M1, 0x49000128 +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M2, 0x49000129 +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M3, 0x4900012a +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M4, 0x4900012b +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M5, 0x4900012c +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M6, 0x4900012d +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M7, 0x4900012e +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M8, 0x4900012f +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M1, 0x49000130 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M2, 0x49000131 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M3, 0x49000132 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M4, 0x49000133 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M5, 0x49000134 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M6, 0x49000135 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M7, 0x49000136 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M8, 0x49000137 +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M1, 0x49000138 +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M2, 0x49000139 +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M3, 0x4900013a +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M4, 0x4900013b +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M5, 0x4900013c +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M6, 0x4900013d +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M7, 0x4900013e +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M8, 0x4900013f +.set CYDEV_FLSHID_MFG_CFG_BASE, 0x49000180 +.set CYDEV_FLSHID_MFG_CFG_SIZE, 0x00000080 +.set CYDEV_FLSHID_MFG_CFG_IMO_TR1, 0x49000188 +.set CYDEV_FLSHID_MFG_CFG_CMP0_TR0, 0x490001ac +.set CYDEV_FLSHID_MFG_CFG_CMP1_TR0, 0x490001ae +.set CYDEV_FLSHID_MFG_CFG_CMP2_TR0, 0x490001b0 +.set CYDEV_FLSHID_MFG_CFG_CMP3_TR0, 0x490001b2 +.set CYDEV_FLSHID_MFG_CFG_CMP0_TR1, 0x490001b4 +.set CYDEV_FLSHID_MFG_CFG_CMP1_TR1, 0x490001b6 +.set CYDEV_FLSHID_MFG_CFG_CMP2_TR1, 0x490001b8 +.set CYDEV_FLSHID_MFG_CFG_CMP3_TR1, 0x490001ba +.set CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM, 0x490001ce +.set CYDEV_EXTMEM_BASE, 0x60000000 +.set CYDEV_EXTMEM_SIZE, 0x00800000 +.set CYDEV_EXTMEM_DATA_MBASE, 0x60000000 +.set CYDEV_EXTMEM_DATA_MSIZE, 0x00800000 +.set CYDEV_ITM_BASE, 0xe0000000 +.set CYDEV_ITM_SIZE, 0x00001000 +.set CYDEV_ITM_TRACE_EN, 0xe0000e00 +.set CYDEV_ITM_TRACE_PRIVILEGE, 0xe0000e40 +.set CYDEV_ITM_TRACE_CTRL, 0xe0000e80 +.set CYDEV_ITM_LOCK_ACCESS, 0xe0000fb0 +.set CYDEV_ITM_LOCK_STATUS, 0xe0000fb4 +.set CYDEV_ITM_PID4, 0xe0000fd0 +.set CYDEV_ITM_PID5, 0xe0000fd4 +.set CYDEV_ITM_PID6, 0xe0000fd8 +.set CYDEV_ITM_PID7, 0xe0000fdc +.set CYDEV_ITM_PID0, 0xe0000fe0 +.set CYDEV_ITM_PID1, 0xe0000fe4 +.set CYDEV_ITM_PID2, 0xe0000fe8 +.set CYDEV_ITM_PID3, 0xe0000fec +.set CYDEV_ITM_CID0, 0xe0000ff0 +.set CYDEV_ITM_CID1, 0xe0000ff4 +.set CYDEV_ITM_CID2, 0xe0000ff8 +.set CYDEV_ITM_CID3, 0xe0000ffc +.set CYDEV_DWT_BASE, 0xe0001000 +.set CYDEV_DWT_SIZE, 0x0000005c +.set CYDEV_DWT_CTRL, 0xe0001000 +.set CYDEV_DWT_CYCLE_COUNT, 0xe0001004 +.set CYDEV_DWT_CPI_COUNT, 0xe0001008 +.set CYDEV_DWT_EXC_OVHD_COUNT, 0xe000100c +.set CYDEV_DWT_SLEEP_COUNT, 0xe0001010 +.set CYDEV_DWT_LSU_COUNT, 0xe0001014 +.set CYDEV_DWT_FOLD_COUNT, 0xe0001018 +.set CYDEV_DWT_PC_SAMPLE, 0xe000101c +.set CYDEV_DWT_COMP_0, 0xe0001020 +.set CYDEV_DWT_MASK_0, 0xe0001024 +.set CYDEV_DWT_FUNCTION_0, 0xe0001028 +.set CYDEV_DWT_COMP_1, 0xe0001030 +.set CYDEV_DWT_MASK_1, 0xe0001034 +.set CYDEV_DWT_FUNCTION_1, 0xe0001038 +.set CYDEV_DWT_COMP_2, 0xe0001040 +.set CYDEV_DWT_MASK_2, 0xe0001044 +.set CYDEV_DWT_FUNCTION_2, 0xe0001048 +.set CYDEV_DWT_COMP_3, 0xe0001050 +.set CYDEV_DWT_MASK_3, 0xe0001054 +.set CYDEV_DWT_FUNCTION_3, 0xe0001058 +.set CYDEV_FPB_BASE, 0xe0002000 +.set CYDEV_FPB_SIZE, 0x00001000 +.set CYDEV_FPB_CTRL, 0xe0002000 +.set CYDEV_FPB_REMAP, 0xe0002004 +.set CYDEV_FPB_FP_COMP_0, 0xe0002008 +.set CYDEV_FPB_FP_COMP_1, 0xe000200c +.set CYDEV_FPB_FP_COMP_2, 0xe0002010 +.set CYDEV_FPB_FP_COMP_3, 0xe0002014 +.set CYDEV_FPB_FP_COMP_4, 0xe0002018 +.set CYDEV_FPB_FP_COMP_5, 0xe000201c +.set CYDEV_FPB_FP_COMP_6, 0xe0002020 +.set CYDEV_FPB_FP_COMP_7, 0xe0002024 +.set CYDEV_FPB_PID4, 0xe0002fd0 +.set CYDEV_FPB_PID5, 0xe0002fd4 +.set CYDEV_FPB_PID6, 0xe0002fd8 +.set CYDEV_FPB_PID7, 0xe0002fdc +.set CYDEV_FPB_PID0, 0xe0002fe0 +.set CYDEV_FPB_PID1, 0xe0002fe4 +.set CYDEV_FPB_PID2, 0xe0002fe8 +.set CYDEV_FPB_PID3, 0xe0002fec +.set CYDEV_FPB_CID0, 0xe0002ff0 +.set CYDEV_FPB_CID1, 0xe0002ff4 +.set CYDEV_FPB_CID2, 0xe0002ff8 +.set CYDEV_FPB_CID3, 0xe0002ffc +.set CYDEV_NVIC_BASE, 0xe000e000 +.set CYDEV_NVIC_SIZE, 0x00000d3c +.set CYDEV_NVIC_INT_CTL_TYPE, 0xe000e004 +.set CYDEV_NVIC_SYSTICK_CTL, 0xe000e010 +.set CYDEV_NVIC_SYSTICK_RELOAD, 0xe000e014 +.set CYDEV_NVIC_SYSTICK_CURRENT, 0xe000e018 +.set CYDEV_NVIC_SYSTICK_CAL, 0xe000e01c +.set CYDEV_NVIC_SETENA0, 0xe000e100 +.set CYDEV_NVIC_CLRENA0, 0xe000e180 +.set CYDEV_NVIC_SETPEND0, 0xe000e200 +.set CYDEV_NVIC_CLRPEND0, 0xe000e280 +.set CYDEV_NVIC_ACTIVE0, 0xe000e300 +.set CYDEV_NVIC_PRI_0, 0xe000e400 +.set CYDEV_NVIC_PRI_1, 0xe000e401 +.set CYDEV_NVIC_PRI_2, 0xe000e402 +.set CYDEV_NVIC_PRI_3, 0xe000e403 +.set CYDEV_NVIC_PRI_4, 0xe000e404 +.set CYDEV_NVIC_PRI_5, 0xe000e405 +.set CYDEV_NVIC_PRI_6, 0xe000e406 +.set CYDEV_NVIC_PRI_7, 0xe000e407 +.set CYDEV_NVIC_PRI_8, 0xe000e408 +.set CYDEV_NVIC_PRI_9, 0xe000e409 +.set CYDEV_NVIC_PRI_10, 0xe000e40a +.set CYDEV_NVIC_PRI_11, 0xe000e40b +.set CYDEV_NVIC_PRI_12, 0xe000e40c +.set CYDEV_NVIC_PRI_13, 0xe000e40d +.set CYDEV_NVIC_PRI_14, 0xe000e40e +.set CYDEV_NVIC_PRI_15, 0xe000e40f +.set CYDEV_NVIC_PRI_16, 0xe000e410 +.set CYDEV_NVIC_PRI_17, 0xe000e411 +.set CYDEV_NVIC_PRI_18, 0xe000e412 +.set CYDEV_NVIC_PRI_19, 0xe000e413 +.set CYDEV_NVIC_PRI_20, 0xe000e414 +.set CYDEV_NVIC_PRI_21, 0xe000e415 +.set CYDEV_NVIC_PRI_22, 0xe000e416 +.set CYDEV_NVIC_PRI_23, 0xe000e417 +.set CYDEV_NVIC_PRI_24, 0xe000e418 +.set CYDEV_NVIC_PRI_25, 0xe000e419 +.set CYDEV_NVIC_PRI_26, 0xe000e41a +.set CYDEV_NVIC_PRI_27, 0xe000e41b +.set CYDEV_NVIC_PRI_28, 0xe000e41c +.set CYDEV_NVIC_PRI_29, 0xe000e41d +.set CYDEV_NVIC_PRI_30, 0xe000e41e +.set CYDEV_NVIC_PRI_31, 0xe000e41f +.set CYDEV_NVIC_CPUID_BASE, 0xe000ed00 +.set CYDEV_NVIC_INTR_CTRL_STATE, 0xe000ed04 +.set CYDEV_NVIC_VECT_OFFSET, 0xe000ed08 +.set CYDEV_NVIC_APPLN_INTR, 0xe000ed0c +.set CYDEV_NVIC_SYSTEM_CONTROL, 0xe000ed10 +.set CYDEV_NVIC_CFG_CONTROL, 0xe000ed14 +.set CYDEV_NVIC_SYS_PRIO_HANDLER_4_7, 0xe000ed18 +.set CYDEV_NVIC_SYS_PRIO_HANDLER_8_11, 0xe000ed1c +.set CYDEV_NVIC_SYS_PRIO_HANDLER_12_15, 0xe000ed20 +.set CYDEV_NVIC_SYS_HANDLER_CSR, 0xe000ed24 +.set CYDEV_NVIC_MEMMAN_FAULT_STATUS, 0xe000ed28 +.set CYDEV_NVIC_BUS_FAULT_STATUS, 0xe000ed29 +.set CYDEV_NVIC_USAGE_FAULT_STATUS, 0xe000ed2a +.set CYDEV_NVIC_HARD_FAULT_STATUS, 0xe000ed2c +.set CYDEV_NVIC_DEBUG_FAULT_STATUS, 0xe000ed30 +.set CYDEV_NVIC_MEMMAN_FAULT_ADD, 0xe000ed34 +.set CYDEV_NVIC_BUS_FAULT_ADD, 0xe000ed38 +.set CYDEV_CORE_DBG_BASE, 0xe000edf0 +.set CYDEV_CORE_DBG_SIZE, 0x00000010 +.set CYDEV_CORE_DBG_DBG_HLT_CS, 0xe000edf0 +.set CYDEV_CORE_DBG_DBG_REG_SEL, 0xe000edf4 +.set CYDEV_CORE_DBG_DBG_REG_DATA, 0xe000edf8 +.set CYDEV_CORE_DBG_EXC_MON_CTL, 0xe000edfc +.set CYDEV_TPIU_BASE, 0xe0040000 +.set CYDEV_TPIU_SIZE, 0x00001000 +.set CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ, 0xe0040000 +.set CYDEV_TPIU_CURRENT_SYNC_PRT_SZ, 0xe0040004 +.set CYDEV_TPIU_ASYNC_CLK_PRESCALER, 0xe0040010 +.set CYDEV_TPIU_PROTOCOL, 0xe00400f0 +.set CYDEV_TPIU_FORM_FLUSH_STAT, 0xe0040300 +.set CYDEV_TPIU_FORM_FLUSH_CTRL, 0xe0040304 +.set CYDEV_TPIU_TRIGGER, 0xe0040ee8 +.set CYDEV_TPIU_ITETMDATA, 0xe0040eec +.set CYDEV_TPIU_ITATBCTR2, 0xe0040ef0 +.set CYDEV_TPIU_ITATBCTR0, 0xe0040ef8 +.set CYDEV_TPIU_ITITMDATA, 0xe0040efc +.set CYDEV_TPIU_ITCTRL, 0xe0040f00 +.set CYDEV_TPIU_DEVID, 0xe0040fc8 +.set CYDEV_TPIU_DEVTYPE, 0xe0040fcc +.set CYDEV_TPIU_PID4, 0xe0040fd0 +.set CYDEV_TPIU_PID5, 0xe0040fd4 +.set CYDEV_TPIU_PID6, 0xe0040fd8 +.set CYDEV_TPIU_PID7, 0xe0040fdc +.set CYDEV_TPIU_PID0, 0xe0040fe0 +.set CYDEV_TPIU_PID1, 0xe0040fe4 +.set CYDEV_TPIU_PID2, 0xe0040fe8 +.set CYDEV_TPIU_PID3, 0xe0040fec +.set CYDEV_TPIU_CID0, 0xe0040ff0 +.set CYDEV_TPIU_CID1, 0xe0040ff4 +.set CYDEV_TPIU_CID2, 0xe0040ff8 +.set CYDEV_TPIU_CID3, 0xe0040ffc +.set CYDEV_ETM_BASE, 0xe0041000 +.set CYDEV_ETM_SIZE, 0x00001000 +.set CYDEV_ETM_CTL, 0xe0041000 +.set CYDEV_ETM_CFG_CODE, 0xe0041004 +.set CYDEV_ETM_TRIG_EVENT, 0xe0041008 +.set CYDEV_ETM_STATUS, 0xe0041010 +.set CYDEV_ETM_SYS_CFG, 0xe0041014 +.set CYDEV_ETM_TRACE_ENB_EVENT, 0xe0041020 +.set CYDEV_ETM_TRACE_EN_CTRL1, 0xe0041024 +.set CYDEV_ETM_FIFOFULL_LEVEL, 0xe004102c +.set CYDEV_ETM_SYNC_FREQ, 0xe00411e0 +.set CYDEV_ETM_ETM_ID, 0xe00411e4 +.set CYDEV_ETM_CFG_CODE_EXT, 0xe00411e8 +.set CYDEV_ETM_TR_SS_EMBICE_CTRL, 0xe00411f0 +.set CYDEV_ETM_CS_TRACE_ID, 0xe0041200 +.set CYDEV_ETM_OS_LOCK_ACCESS, 0xe0041300 +.set CYDEV_ETM_OS_LOCK_STATUS, 0xe0041304 +.set CYDEV_ETM_PDSR, 0xe0041314 +.set CYDEV_ETM_ITMISCIN, 0xe0041ee0 +.set CYDEV_ETM_ITTRIGOUT, 0xe0041ee8 +.set CYDEV_ETM_ITATBCTR2, 0xe0041ef0 +.set CYDEV_ETM_ITATBCTR0, 0xe0041ef8 +.set CYDEV_ETM_INT_MODE_CTRL, 0xe0041f00 +.set CYDEV_ETM_CLM_TAG_SET, 0xe0041fa0 +.set CYDEV_ETM_CLM_TAG_CLR, 0xe0041fa4 +.set CYDEV_ETM_LOCK_ACCESS, 0xe0041fb0 +.set CYDEV_ETM_LOCK_STATUS, 0xe0041fb4 +.set CYDEV_ETM_AUTH_STATUS, 0xe0041fb8 +.set CYDEV_ETM_DEV_TYPE, 0xe0041fcc +.set CYDEV_ETM_PID4, 0xe0041fd0 +.set CYDEV_ETM_PID5, 0xe0041fd4 +.set CYDEV_ETM_PID6, 0xe0041fd8 +.set CYDEV_ETM_PID7, 0xe0041fdc +.set CYDEV_ETM_PID0, 0xe0041fe0 +.set CYDEV_ETM_PID1, 0xe0041fe4 +.set CYDEV_ETM_PID2, 0xe0041fe8 +.set CYDEV_ETM_PID3, 0xe0041fec +.set CYDEV_ETM_CID0, 0xe0041ff0 +.set CYDEV_ETM_CID1, 0xe0041ff4 +.set CYDEV_ETM_CID2, 0xe0041ff8 +.set CYDEV_ETM_CID3, 0xe0041ffc +.set CYDEV_ROM_TABLE_BASE, 0xe00ff000 +.set CYDEV_ROM_TABLE_SIZE, 0x00001000 +.set CYDEV_ROM_TABLE_NVIC, 0xe00ff000 +.set CYDEV_ROM_TABLE_DWT, 0xe00ff004 +.set CYDEV_ROM_TABLE_FPB, 0xe00ff008 +.set CYDEV_ROM_TABLE_ITM, 0xe00ff00c +.set CYDEV_ROM_TABLE_TPIU, 0xe00ff010 +.set CYDEV_ROM_TABLE_ETM, 0xe00ff014 +.set CYDEV_ROM_TABLE_END, 0xe00ff018 +.set CYDEV_ROM_TABLE_MEMTYPE, 0xe00fffcc +.set CYDEV_ROM_TABLE_PID4, 0xe00fffd0 +.set CYDEV_ROM_TABLE_PID5, 0xe00fffd4 +.set CYDEV_ROM_TABLE_PID6, 0xe00fffd8 +.set CYDEV_ROM_TABLE_PID7, 0xe00fffdc +.set CYDEV_ROM_TABLE_PID0, 0xe00fffe0 +.set CYDEV_ROM_TABLE_PID1, 0xe00fffe4 +.set CYDEV_ROM_TABLE_PID2, 0xe00fffe8 +.set CYDEV_ROM_TABLE_PID3, 0xe00fffec +.set CYDEV_ROM_TABLE_CID0, 0xe00ffff0 +.set CYDEV_ROM_TABLE_CID1, 0xe00ffff4 +.set CYDEV_ROM_TABLE_CID2, 0xe00ffff8 +.set CYDEV_ROM_TABLE_CID3, 0xe00ffffc +.set CYDEV_FLS_SIZE, CYDEV_FLASH_SIZE +.set CYDEV_ECC_BASE, CYDEV_FLSECC_BASE +.set CYDEV_FLS_SECTOR_SIZE, 0x00010000 +.set CYDEV_FLS_ROW_SIZE, 0x00000100 +.set CYDEV_ECC_SECTOR_SIZE, 0x00002000 +.set CYDEV_ECC_ROW_SIZE, 0x00000020 +.set CYDEV_EEPROM_SECTOR_SIZE, 0x00000400 +.set CYDEV_EEPROM_ROW_SIZE, 0x00000010 +.set CYDEV_PERIPH_BASE, CYDEV_CLKDIST_BASE +.set CYCLK_LD_DISABLE, 0x00000004 +.set CYCLK_LD_SYNC_EN, 0x00000002 +.set CYCLK_LD_LOAD, 0x00000001 +.set CYCLK_PIPE, 0x00000080 +.set CYCLK_SSS, 0x00000040 +.set CYCLK_EARLY, 0x00000020 +.set CYCLK_DUTY, 0x00000010 +.set CYCLK_SYNC, 0x00000008 +.set CYCLK_SRC_SEL_CLK_SYNC_D, 0 +.set CYCLK_SRC_SEL_SYNC_DIG, 0 +.set CYCLK_SRC_SEL_IMO, 1 +.set CYCLK_SRC_SEL_XTAL_MHZ, 2 +.set CYCLK_SRC_SEL_XTALM, 2 +.set CYCLK_SRC_SEL_ILO, 3 +.set CYCLK_SRC_SEL_PLL, 4 +.set CYCLK_SRC_SEL_XTAL_KHZ, 5 +.set CYCLK_SRC_SEL_XTALK, 5 +.set CYCLK_SRC_SEL_DSI_G, 6 +.set CYCLK_SRC_SEL_DSI_D, 7 +.set CYCLK_SRC_SEL_CLK_SYNC_A, 0 +.set CYCLK_SRC_SEL_DSI_A, 7 diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc new file mode 100755 index 00000000..ede64b20 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc @@ -0,0 +1,5357 @@ +/******************************************************************************* +* FILENAME: cydevicegnu_trm.inc +* +* PSoC Creator 3.0 Component Pack 7 +* +* DESCRIPTION: +* This file provides all of the address values for the entire PSoC device. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +.set CYDEV_FLASH_BASE, 0x00000000 +.set CYDEV_FLASH_SIZE, 0x00020000 +.set CYREG_FLASH_DATA_MBASE, 0x00000000 +.set CYREG_FLASH_DATA_MSIZE, 0x00020000 +.set CYDEV_SRAM_BASE, 0x1fffc000 +.set CYDEV_SRAM_SIZE, 0x00008000 +.set CYREG_SRAM_CODE64K_MBASE, 0x1fff8000 +.set CYREG_SRAM_CODE64K_MSIZE, 0x00004000 +.set CYREG_SRAM_CODE32K_MBASE, 0x1fffc000 +.set CYREG_SRAM_CODE32K_MSIZE, 0x00002000 +.set CYREG_SRAM_CODE16K_MBASE, 0x1fffe000 +.set CYREG_SRAM_CODE16K_MSIZE, 0x00001000 +.set CYREG_SRAM_CODE_MBASE, 0x1fffc000 +.set CYREG_SRAM_CODE_MSIZE, 0x00004000 +.set CYREG_SRAM_DATA_MBASE, 0x20000000 +.set CYREG_SRAM_DATA_MSIZE, 0x00004000 +.set CYREG_SRAM_DATA16K_MBASE, 0x20001000 +.set CYREG_SRAM_DATA16K_MSIZE, 0x00001000 +.set CYREG_SRAM_DATA32K_MBASE, 0x20002000 +.set CYREG_SRAM_DATA32K_MSIZE, 0x00002000 +.set CYREG_SRAM_DATA64K_MBASE, 0x20004000 +.set CYREG_SRAM_DATA64K_MSIZE, 0x00004000 +.set CYDEV_DMA_BASE, 0x20008000 +.set CYDEV_DMA_SIZE, 0x00008000 +.set CYREG_DMA_SRAM64K_MBASE, 0x20008000 +.set CYREG_DMA_SRAM64K_MSIZE, 0x00004000 +.set CYREG_DMA_SRAM32K_MBASE, 0x2000c000 +.set CYREG_DMA_SRAM32K_MSIZE, 0x00002000 +.set CYREG_DMA_SRAM16K_MBASE, 0x2000e000 +.set CYREG_DMA_SRAM16K_MSIZE, 0x00001000 +.set CYREG_DMA_SRAM_MBASE, 0x2000f000 +.set CYREG_DMA_SRAM_MSIZE, 0x00001000 +.set CYDEV_CLKDIST_BASE, 0x40004000 +.set CYDEV_CLKDIST_SIZE, 0x00000110 +.set CYREG_CLKDIST_CR, 0x40004000 +.set CYREG_CLKDIST_LD, 0x40004001 +.set CYREG_CLKDIST_WRK0, 0x40004002 +.set CYREG_CLKDIST_WRK1, 0x40004003 +.set CYREG_CLKDIST_MSTR0, 0x40004004 +.set CYREG_CLKDIST_MSTR1, 0x40004005 +.set CYREG_CLKDIST_BCFG0, 0x40004006 +.set CYREG_CLKDIST_BCFG1, 0x40004007 +.set CYREG_CLKDIST_BCFG2, 0x40004008 +.set CYREG_CLKDIST_UCFG, 0x40004009 +.set CYREG_CLKDIST_DLY0, 0x4000400a +.set CYREG_CLKDIST_DLY1, 0x4000400b +.set CYREG_CLKDIST_DMASK, 0x40004010 +.set CYREG_CLKDIST_AMASK, 0x40004014 +.set CYDEV_CLKDIST_DCFG0_BASE, 0x40004080 +.set CYDEV_CLKDIST_DCFG0_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG0_CFG0, 0x40004080 +.set CYREG_CLKDIST_DCFG0_CFG1, 0x40004081 +.set CYREG_CLKDIST_DCFG0_CFG2, 0x40004082 +.set CYDEV_CLKDIST_DCFG1_BASE, 0x40004084 +.set CYDEV_CLKDIST_DCFG1_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG1_CFG0, 0x40004084 +.set CYREG_CLKDIST_DCFG1_CFG1, 0x40004085 +.set CYREG_CLKDIST_DCFG1_CFG2, 0x40004086 +.set CYDEV_CLKDIST_DCFG2_BASE, 0x40004088 +.set CYDEV_CLKDIST_DCFG2_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG2_CFG0, 0x40004088 +.set CYREG_CLKDIST_DCFG2_CFG1, 0x40004089 +.set CYREG_CLKDIST_DCFG2_CFG2, 0x4000408a +.set CYDEV_CLKDIST_DCFG3_BASE, 0x4000408c +.set CYDEV_CLKDIST_DCFG3_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG3_CFG0, 0x4000408c +.set CYREG_CLKDIST_DCFG3_CFG1, 0x4000408d +.set CYREG_CLKDIST_DCFG3_CFG2, 0x4000408e +.set CYDEV_CLKDIST_DCFG4_BASE, 0x40004090 +.set CYDEV_CLKDIST_DCFG4_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG4_CFG0, 0x40004090 +.set CYREG_CLKDIST_DCFG4_CFG1, 0x40004091 +.set CYREG_CLKDIST_DCFG4_CFG2, 0x40004092 +.set CYDEV_CLKDIST_DCFG5_BASE, 0x40004094 +.set CYDEV_CLKDIST_DCFG5_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG5_CFG0, 0x40004094 +.set CYREG_CLKDIST_DCFG5_CFG1, 0x40004095 +.set CYREG_CLKDIST_DCFG5_CFG2, 0x40004096 +.set CYDEV_CLKDIST_DCFG6_BASE, 0x40004098 +.set CYDEV_CLKDIST_DCFG6_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG6_CFG0, 0x40004098 +.set CYREG_CLKDIST_DCFG6_CFG1, 0x40004099 +.set CYREG_CLKDIST_DCFG6_CFG2, 0x4000409a +.set CYDEV_CLKDIST_DCFG7_BASE, 0x4000409c +.set CYDEV_CLKDIST_DCFG7_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG7_CFG0, 0x4000409c +.set CYREG_CLKDIST_DCFG7_CFG1, 0x4000409d +.set CYREG_CLKDIST_DCFG7_CFG2, 0x4000409e +.set CYDEV_CLKDIST_ACFG0_BASE, 0x40004100 +.set CYDEV_CLKDIST_ACFG0_SIZE, 0x00000004 +.set CYREG_CLKDIST_ACFG0_CFG0, 0x40004100 +.set CYREG_CLKDIST_ACFG0_CFG1, 0x40004101 +.set CYREG_CLKDIST_ACFG0_CFG2, 0x40004102 +.set CYREG_CLKDIST_ACFG0_CFG3, 0x40004103 +.set CYDEV_CLKDIST_ACFG1_BASE, 0x40004104 +.set CYDEV_CLKDIST_ACFG1_SIZE, 0x00000004 +.set CYREG_CLKDIST_ACFG1_CFG0, 0x40004104 +.set CYREG_CLKDIST_ACFG1_CFG1, 0x40004105 +.set CYREG_CLKDIST_ACFG1_CFG2, 0x40004106 +.set CYREG_CLKDIST_ACFG1_CFG3, 0x40004107 +.set CYDEV_CLKDIST_ACFG2_BASE, 0x40004108 +.set CYDEV_CLKDIST_ACFG2_SIZE, 0x00000004 +.set CYREG_CLKDIST_ACFG2_CFG0, 0x40004108 +.set CYREG_CLKDIST_ACFG2_CFG1, 0x40004109 +.set CYREG_CLKDIST_ACFG2_CFG2, 0x4000410a +.set CYREG_CLKDIST_ACFG2_CFG3, 0x4000410b +.set CYDEV_CLKDIST_ACFG3_BASE, 0x4000410c +.set CYDEV_CLKDIST_ACFG3_SIZE, 0x00000004 +.set CYREG_CLKDIST_ACFG3_CFG0, 0x4000410c +.set CYREG_CLKDIST_ACFG3_CFG1, 0x4000410d +.set CYREG_CLKDIST_ACFG3_CFG2, 0x4000410e +.set CYREG_CLKDIST_ACFG3_CFG3, 0x4000410f +.set CYDEV_FASTCLK_BASE, 0x40004200 +.set CYDEV_FASTCLK_SIZE, 0x00000026 +.set CYDEV_FASTCLK_IMO_BASE, 0x40004200 +.set CYDEV_FASTCLK_IMO_SIZE, 0x00000001 +.set CYREG_FASTCLK_IMO_CR, 0x40004200 +.set CYDEV_FASTCLK_XMHZ_BASE, 0x40004210 +.set CYDEV_FASTCLK_XMHZ_SIZE, 0x00000004 +.set CYREG_FASTCLK_XMHZ_CSR, 0x40004210 +.set CYREG_FASTCLK_XMHZ_CFG0, 0x40004212 +.set CYREG_FASTCLK_XMHZ_CFG1, 0x40004213 +.set CYDEV_FASTCLK_PLL_BASE, 0x40004220 +.set CYDEV_FASTCLK_PLL_SIZE, 0x00000006 +.set CYREG_FASTCLK_PLL_CFG0, 0x40004220 +.set CYREG_FASTCLK_PLL_CFG1, 0x40004221 +.set CYREG_FASTCLK_PLL_P, 0x40004222 +.set CYREG_FASTCLK_PLL_Q, 0x40004223 +.set CYREG_FASTCLK_PLL_SR, 0x40004225 +.set CYDEV_SLOWCLK_BASE, 0x40004300 +.set CYDEV_SLOWCLK_SIZE, 0x0000000b +.set CYDEV_SLOWCLK_ILO_BASE, 0x40004300 +.set CYDEV_SLOWCLK_ILO_SIZE, 0x00000002 +.set CYREG_SLOWCLK_ILO_CR0, 0x40004300 +.set CYREG_SLOWCLK_ILO_CR1, 0x40004301 +.set CYDEV_SLOWCLK_X32_BASE, 0x40004308 +.set CYDEV_SLOWCLK_X32_SIZE, 0x00000003 +.set CYREG_SLOWCLK_X32_CR, 0x40004308 +.set CYREG_SLOWCLK_X32_CFG, 0x40004309 +.set CYREG_SLOWCLK_X32_TST, 0x4000430a +.set CYDEV_BOOST_BASE, 0x40004320 +.set CYDEV_BOOST_SIZE, 0x00000007 +.set CYREG_BOOST_CR0, 0x40004320 +.set CYREG_BOOST_CR1, 0x40004321 +.set CYREG_BOOST_CR2, 0x40004322 +.set CYREG_BOOST_CR3, 0x40004323 +.set CYREG_BOOST_SR, 0x40004324 +.set CYREG_BOOST_CR4, 0x40004325 +.set CYREG_BOOST_SR2, 0x40004326 +.set CYDEV_PWRSYS_BASE, 0x40004330 +.set CYDEV_PWRSYS_SIZE, 0x00000002 +.set CYREG_PWRSYS_CR0, 0x40004330 +.set CYREG_PWRSYS_CR1, 0x40004331 +.set CYDEV_PM_BASE, 0x40004380 +.set CYDEV_PM_SIZE, 0x00000057 +.set CYREG_PM_TW_CFG0, 0x40004380 +.set CYREG_PM_TW_CFG1, 0x40004381 +.set CYREG_PM_TW_CFG2, 0x40004382 +.set CYREG_PM_WDT_CFG, 0x40004383 +.set CYREG_PM_WDT_CR, 0x40004384 +.set CYREG_PM_INT_SR, 0x40004390 +.set CYREG_PM_MODE_CFG0, 0x40004391 +.set CYREG_PM_MODE_CFG1, 0x40004392 +.set CYREG_PM_MODE_CSR, 0x40004393 +.set CYREG_PM_USB_CR0, 0x40004394 +.set CYREG_PM_WAKEUP_CFG0, 0x40004398 +.set CYREG_PM_WAKEUP_CFG1, 0x40004399 +.set CYREG_PM_WAKEUP_CFG2, 0x4000439a +.set CYDEV_PM_ACT_BASE, 0x400043a0 +.set CYDEV_PM_ACT_SIZE, 0x0000000e +.set CYREG_PM_ACT_CFG0, 0x400043a0 +.set CYREG_PM_ACT_CFG1, 0x400043a1 +.set CYREG_PM_ACT_CFG2, 0x400043a2 +.set CYREG_PM_ACT_CFG3, 0x400043a3 +.set CYREG_PM_ACT_CFG4, 0x400043a4 +.set CYREG_PM_ACT_CFG5, 0x400043a5 +.set CYREG_PM_ACT_CFG6, 0x400043a6 +.set CYREG_PM_ACT_CFG7, 0x400043a7 +.set CYREG_PM_ACT_CFG8, 0x400043a8 +.set CYREG_PM_ACT_CFG9, 0x400043a9 +.set CYREG_PM_ACT_CFG10, 0x400043aa +.set CYREG_PM_ACT_CFG11, 0x400043ab +.set CYREG_PM_ACT_CFG12, 0x400043ac +.set CYREG_PM_ACT_CFG13, 0x400043ad +.set CYDEV_PM_STBY_BASE, 0x400043b0 +.set CYDEV_PM_STBY_SIZE, 0x0000000e +.set CYREG_PM_STBY_CFG0, 0x400043b0 +.set CYREG_PM_STBY_CFG1, 0x400043b1 +.set CYREG_PM_STBY_CFG2, 0x400043b2 +.set CYREG_PM_STBY_CFG3, 0x400043b3 +.set CYREG_PM_STBY_CFG4, 0x400043b4 +.set CYREG_PM_STBY_CFG5, 0x400043b5 +.set CYREG_PM_STBY_CFG6, 0x400043b6 +.set CYREG_PM_STBY_CFG7, 0x400043b7 +.set CYREG_PM_STBY_CFG8, 0x400043b8 +.set CYREG_PM_STBY_CFG9, 0x400043b9 +.set CYREG_PM_STBY_CFG10, 0x400043ba +.set CYREG_PM_STBY_CFG11, 0x400043bb +.set CYREG_PM_STBY_CFG12, 0x400043bc +.set CYREG_PM_STBY_CFG13, 0x400043bd +.set CYDEV_PM_AVAIL_BASE, 0x400043c0 +.set CYDEV_PM_AVAIL_SIZE, 0x00000017 +.set CYREG_PM_AVAIL_CR0, 0x400043c0 +.set CYREG_PM_AVAIL_CR1, 0x400043c1 +.set CYREG_PM_AVAIL_CR2, 0x400043c2 +.set CYREG_PM_AVAIL_CR3, 0x400043c3 +.set CYREG_PM_AVAIL_CR4, 0x400043c4 +.set CYREG_PM_AVAIL_CR5, 0x400043c5 +.set CYREG_PM_AVAIL_CR6, 0x400043c6 +.set CYREG_PM_AVAIL_SR0, 0x400043d0 +.set CYREG_PM_AVAIL_SR1, 0x400043d1 +.set CYREG_PM_AVAIL_SR2, 0x400043d2 +.set CYREG_PM_AVAIL_SR3, 0x400043d3 +.set CYREG_PM_AVAIL_SR4, 0x400043d4 +.set CYREG_PM_AVAIL_SR5, 0x400043d5 +.set CYREG_PM_AVAIL_SR6, 0x400043d6 +.set CYDEV_PICU_BASE, 0x40004500 +.set CYDEV_PICU_SIZE, 0x000000b0 +.set CYDEV_PICU_INTTYPE_BASE, 0x40004500 +.set CYDEV_PICU_INTTYPE_SIZE, 0x00000080 +.set CYDEV_PICU_INTTYPE_PICU0_BASE, 0x40004500 +.set CYDEV_PICU_INTTYPE_PICU0_SIZE, 0x00000008 +.set CYREG_PICU0_INTTYPE0, 0x40004500 +.set CYREG_PICU0_INTTYPE1, 0x40004501 +.set CYREG_PICU0_INTTYPE2, 0x40004502 +.set CYREG_PICU0_INTTYPE3, 0x40004503 +.set CYREG_PICU0_INTTYPE4, 0x40004504 +.set CYREG_PICU0_INTTYPE5, 0x40004505 +.set CYREG_PICU0_INTTYPE6, 0x40004506 +.set CYREG_PICU0_INTTYPE7, 0x40004507 +.set CYDEV_PICU_INTTYPE_PICU1_BASE, 0x40004508 +.set CYDEV_PICU_INTTYPE_PICU1_SIZE, 0x00000008 +.set CYREG_PICU1_INTTYPE0, 0x40004508 +.set CYREG_PICU1_INTTYPE1, 0x40004509 +.set CYREG_PICU1_INTTYPE2, 0x4000450a +.set CYREG_PICU1_INTTYPE3, 0x4000450b +.set CYREG_PICU1_INTTYPE4, 0x4000450c +.set CYREG_PICU1_INTTYPE5, 0x4000450d +.set CYREG_PICU1_INTTYPE6, 0x4000450e +.set CYREG_PICU1_INTTYPE7, 0x4000450f +.set CYDEV_PICU_INTTYPE_PICU2_BASE, 0x40004510 +.set CYDEV_PICU_INTTYPE_PICU2_SIZE, 0x00000008 +.set CYREG_PICU2_INTTYPE0, 0x40004510 +.set CYREG_PICU2_INTTYPE1, 0x40004511 +.set CYREG_PICU2_INTTYPE2, 0x40004512 +.set CYREG_PICU2_INTTYPE3, 0x40004513 +.set CYREG_PICU2_INTTYPE4, 0x40004514 +.set CYREG_PICU2_INTTYPE5, 0x40004515 +.set CYREG_PICU2_INTTYPE6, 0x40004516 +.set CYREG_PICU2_INTTYPE7, 0x40004517 +.set CYDEV_PICU_INTTYPE_PICU3_BASE, 0x40004518 +.set CYDEV_PICU_INTTYPE_PICU3_SIZE, 0x00000008 +.set CYREG_PICU3_INTTYPE0, 0x40004518 +.set CYREG_PICU3_INTTYPE1, 0x40004519 +.set CYREG_PICU3_INTTYPE2, 0x4000451a +.set CYREG_PICU3_INTTYPE3, 0x4000451b +.set CYREG_PICU3_INTTYPE4, 0x4000451c +.set CYREG_PICU3_INTTYPE5, 0x4000451d +.set CYREG_PICU3_INTTYPE6, 0x4000451e +.set CYREG_PICU3_INTTYPE7, 0x4000451f +.set CYDEV_PICU_INTTYPE_PICU4_BASE, 0x40004520 +.set CYDEV_PICU_INTTYPE_PICU4_SIZE, 0x00000008 +.set CYREG_PICU4_INTTYPE0, 0x40004520 +.set CYREG_PICU4_INTTYPE1, 0x40004521 +.set CYREG_PICU4_INTTYPE2, 0x40004522 +.set CYREG_PICU4_INTTYPE3, 0x40004523 +.set CYREG_PICU4_INTTYPE4, 0x40004524 +.set CYREG_PICU4_INTTYPE5, 0x40004525 +.set CYREG_PICU4_INTTYPE6, 0x40004526 +.set CYREG_PICU4_INTTYPE7, 0x40004527 +.set CYDEV_PICU_INTTYPE_PICU5_BASE, 0x40004528 +.set CYDEV_PICU_INTTYPE_PICU5_SIZE, 0x00000008 +.set CYREG_PICU5_INTTYPE0, 0x40004528 +.set CYREG_PICU5_INTTYPE1, 0x40004529 +.set CYREG_PICU5_INTTYPE2, 0x4000452a +.set CYREG_PICU5_INTTYPE3, 0x4000452b +.set CYREG_PICU5_INTTYPE4, 0x4000452c +.set CYREG_PICU5_INTTYPE5, 0x4000452d +.set CYREG_PICU5_INTTYPE6, 0x4000452e +.set CYREG_PICU5_INTTYPE7, 0x4000452f +.set CYDEV_PICU_INTTYPE_PICU6_BASE, 0x40004530 +.set CYDEV_PICU_INTTYPE_PICU6_SIZE, 0x00000008 +.set CYREG_PICU6_INTTYPE0, 0x40004530 +.set CYREG_PICU6_INTTYPE1, 0x40004531 +.set CYREG_PICU6_INTTYPE2, 0x40004532 +.set CYREG_PICU6_INTTYPE3, 0x40004533 +.set CYREG_PICU6_INTTYPE4, 0x40004534 +.set CYREG_PICU6_INTTYPE5, 0x40004535 +.set CYREG_PICU6_INTTYPE6, 0x40004536 +.set CYREG_PICU6_INTTYPE7, 0x40004537 +.set CYDEV_PICU_INTTYPE_PICU12_BASE, 0x40004560 +.set CYDEV_PICU_INTTYPE_PICU12_SIZE, 0x00000008 +.set CYREG_PICU12_INTTYPE0, 0x40004560 +.set CYREG_PICU12_INTTYPE1, 0x40004561 +.set CYREG_PICU12_INTTYPE2, 0x40004562 +.set CYREG_PICU12_INTTYPE3, 0x40004563 +.set CYREG_PICU12_INTTYPE4, 0x40004564 +.set CYREG_PICU12_INTTYPE5, 0x40004565 +.set CYREG_PICU12_INTTYPE6, 0x40004566 +.set CYREG_PICU12_INTTYPE7, 0x40004567 +.set CYDEV_PICU_INTTYPE_PICU15_BASE, 0x40004578 +.set CYDEV_PICU_INTTYPE_PICU15_SIZE, 0x00000008 +.set CYREG_PICU15_INTTYPE0, 0x40004578 +.set CYREG_PICU15_INTTYPE1, 0x40004579 +.set CYREG_PICU15_INTTYPE2, 0x4000457a +.set CYREG_PICU15_INTTYPE3, 0x4000457b +.set CYREG_PICU15_INTTYPE4, 0x4000457c +.set CYREG_PICU15_INTTYPE5, 0x4000457d +.set CYREG_PICU15_INTTYPE6, 0x4000457e +.set CYREG_PICU15_INTTYPE7, 0x4000457f +.set CYDEV_PICU_STAT_BASE, 0x40004580 +.set CYDEV_PICU_STAT_SIZE, 0x00000010 +.set CYDEV_PICU_STAT_PICU0_BASE, 0x40004580 +.set CYDEV_PICU_STAT_PICU0_SIZE, 0x00000001 +.set CYREG_PICU0_INTSTAT, 0x40004580 +.set CYDEV_PICU_STAT_PICU1_BASE, 0x40004581 +.set CYDEV_PICU_STAT_PICU1_SIZE, 0x00000001 +.set CYREG_PICU1_INTSTAT, 0x40004581 +.set CYDEV_PICU_STAT_PICU2_BASE, 0x40004582 +.set CYDEV_PICU_STAT_PICU2_SIZE, 0x00000001 +.set CYREG_PICU2_INTSTAT, 0x40004582 +.set CYDEV_PICU_STAT_PICU3_BASE, 0x40004583 +.set CYDEV_PICU_STAT_PICU3_SIZE, 0x00000001 +.set CYREG_PICU3_INTSTAT, 0x40004583 +.set CYDEV_PICU_STAT_PICU4_BASE, 0x40004584 +.set CYDEV_PICU_STAT_PICU4_SIZE, 0x00000001 +.set CYREG_PICU4_INTSTAT, 0x40004584 +.set CYDEV_PICU_STAT_PICU5_BASE, 0x40004585 +.set CYDEV_PICU_STAT_PICU5_SIZE, 0x00000001 +.set CYREG_PICU5_INTSTAT, 0x40004585 +.set CYDEV_PICU_STAT_PICU6_BASE, 0x40004586 +.set CYDEV_PICU_STAT_PICU6_SIZE, 0x00000001 +.set CYREG_PICU6_INTSTAT, 0x40004586 +.set CYDEV_PICU_STAT_PICU12_BASE, 0x4000458c +.set CYDEV_PICU_STAT_PICU12_SIZE, 0x00000001 +.set CYREG_PICU12_INTSTAT, 0x4000458c +.set CYDEV_PICU_STAT_PICU15_BASE, 0x4000458f +.set CYDEV_PICU_STAT_PICU15_SIZE, 0x00000001 +.set CYREG_PICU15_INTSTAT, 0x4000458f +.set CYDEV_PICU_SNAP_BASE, 0x40004590 +.set CYDEV_PICU_SNAP_SIZE, 0x00000010 +.set CYDEV_PICU_SNAP_PICU0_BASE, 0x40004590 +.set CYDEV_PICU_SNAP_PICU0_SIZE, 0x00000001 +.set CYREG_PICU0_SNAP, 0x40004590 +.set CYDEV_PICU_SNAP_PICU1_BASE, 0x40004591 +.set CYDEV_PICU_SNAP_PICU1_SIZE, 0x00000001 +.set CYREG_PICU1_SNAP, 0x40004591 +.set CYDEV_PICU_SNAP_PICU2_BASE, 0x40004592 +.set CYDEV_PICU_SNAP_PICU2_SIZE, 0x00000001 +.set CYREG_PICU2_SNAP, 0x40004592 +.set CYDEV_PICU_SNAP_PICU3_BASE, 0x40004593 +.set CYDEV_PICU_SNAP_PICU3_SIZE, 0x00000001 +.set CYREG_PICU3_SNAP, 0x40004593 +.set CYDEV_PICU_SNAP_PICU4_BASE, 0x40004594 +.set CYDEV_PICU_SNAP_PICU4_SIZE, 0x00000001 +.set CYREG_PICU4_SNAP, 0x40004594 +.set CYDEV_PICU_SNAP_PICU5_BASE, 0x40004595 +.set CYDEV_PICU_SNAP_PICU5_SIZE, 0x00000001 +.set CYREG_PICU5_SNAP, 0x40004595 +.set CYDEV_PICU_SNAP_PICU6_BASE, 0x40004596 +.set CYDEV_PICU_SNAP_PICU6_SIZE, 0x00000001 +.set CYREG_PICU6_SNAP, 0x40004596 +.set CYDEV_PICU_SNAP_PICU12_BASE, 0x4000459c +.set CYDEV_PICU_SNAP_PICU12_SIZE, 0x00000001 +.set CYREG_PICU12_SNAP, 0x4000459c +.set CYDEV_PICU_SNAP_PICU_15_BASE, 0x4000459f +.set CYDEV_PICU_SNAP_PICU_15_SIZE, 0x00000001 +.set CYREG_PICU_15_SNAP_15, 0x4000459f +.set CYDEV_PICU_DISABLE_COR_BASE, 0x400045a0 +.set CYDEV_PICU_DISABLE_COR_SIZE, 0x00000010 +.set CYDEV_PICU_DISABLE_COR_PICU0_BASE, 0x400045a0 +.set CYDEV_PICU_DISABLE_COR_PICU0_SIZE, 0x00000001 +.set CYREG_PICU0_DISABLE_COR, 0x400045a0 +.set CYDEV_PICU_DISABLE_COR_PICU1_BASE, 0x400045a1 +.set CYDEV_PICU_DISABLE_COR_PICU1_SIZE, 0x00000001 +.set CYREG_PICU1_DISABLE_COR, 0x400045a1 +.set CYDEV_PICU_DISABLE_COR_PICU2_BASE, 0x400045a2 +.set CYDEV_PICU_DISABLE_COR_PICU2_SIZE, 0x00000001 +.set CYREG_PICU2_DISABLE_COR, 0x400045a2 +.set CYDEV_PICU_DISABLE_COR_PICU3_BASE, 0x400045a3 +.set CYDEV_PICU_DISABLE_COR_PICU3_SIZE, 0x00000001 +.set CYREG_PICU3_DISABLE_COR, 0x400045a3 +.set CYDEV_PICU_DISABLE_COR_PICU4_BASE, 0x400045a4 +.set CYDEV_PICU_DISABLE_COR_PICU4_SIZE, 0x00000001 +.set CYREG_PICU4_DISABLE_COR, 0x400045a4 +.set CYDEV_PICU_DISABLE_COR_PICU5_BASE, 0x400045a5 +.set CYDEV_PICU_DISABLE_COR_PICU5_SIZE, 0x00000001 +.set CYREG_PICU5_DISABLE_COR, 0x400045a5 +.set CYDEV_PICU_DISABLE_COR_PICU6_BASE, 0x400045a6 +.set CYDEV_PICU_DISABLE_COR_PICU6_SIZE, 0x00000001 +.set CYREG_PICU6_DISABLE_COR, 0x400045a6 +.set CYDEV_PICU_DISABLE_COR_PICU12_BASE, 0x400045ac +.set CYDEV_PICU_DISABLE_COR_PICU12_SIZE, 0x00000001 +.set CYREG_PICU12_DISABLE_COR, 0x400045ac +.set CYDEV_PICU_DISABLE_COR_PICU15_BASE, 0x400045af +.set CYDEV_PICU_DISABLE_COR_PICU15_SIZE, 0x00000001 +.set CYREG_PICU15_DISABLE_COR, 0x400045af +.set CYDEV_MFGCFG_BASE, 0x40004600 +.set CYDEV_MFGCFG_SIZE, 0x000000ed +.set CYDEV_MFGCFG_ANAIF_BASE, 0x40004600 +.set CYDEV_MFGCFG_ANAIF_SIZE, 0x00000038 +.set CYDEV_MFGCFG_ANAIF_DAC0_BASE, 0x40004608 +.set CYDEV_MFGCFG_ANAIF_DAC0_SIZE, 0x00000001 +.set CYREG_DAC0_TR, 0x40004608 +.set CYDEV_MFGCFG_ANAIF_DAC1_BASE, 0x40004609 +.set CYDEV_MFGCFG_ANAIF_DAC1_SIZE, 0x00000001 +.set CYREG_DAC1_TR, 0x40004609 +.set CYDEV_MFGCFG_ANAIF_DAC2_BASE, 0x4000460a +.set CYDEV_MFGCFG_ANAIF_DAC2_SIZE, 0x00000001 +.set CYREG_DAC2_TR, 0x4000460a +.set CYDEV_MFGCFG_ANAIF_DAC3_BASE, 0x4000460b +.set CYDEV_MFGCFG_ANAIF_DAC3_SIZE, 0x00000001 +.set CYREG_DAC3_TR, 0x4000460b +.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE, 0x40004610 +.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE, 0x00000001 +.set CYREG_NPUMP_DSM_TR0, 0x40004610 +.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE, 0x40004611 +.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE, 0x00000001 +.set CYREG_NPUMP_SC_TR0, 0x40004611 +.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE, 0x40004612 +.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE, 0x00000001 +.set CYREG_NPUMP_OPAMP_TR0, 0x40004612 +.set CYDEV_MFGCFG_ANAIF_SAR0_BASE, 0x40004614 +.set CYDEV_MFGCFG_ANAIF_SAR0_SIZE, 0x00000001 +.set CYREG_SAR0_TR0, 0x40004614 +.set CYDEV_MFGCFG_ANAIF_SAR1_BASE, 0x40004616 +.set CYDEV_MFGCFG_ANAIF_SAR1_SIZE, 0x00000001 +.set CYREG_SAR1_TR0, 0x40004616 +.set CYDEV_MFGCFG_ANAIF_OPAMP0_BASE, 0x40004620 +.set CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE, 0x00000002 +.set CYREG_OPAMP0_TR0, 0x40004620 +.set CYREG_OPAMP0_TR1, 0x40004621 +.set CYDEV_MFGCFG_ANAIF_OPAMP1_BASE, 0x40004622 +.set CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE, 0x00000002 +.set CYREG_OPAMP1_TR0, 0x40004622 +.set CYREG_OPAMP1_TR1, 0x40004623 +.set CYDEV_MFGCFG_ANAIF_OPAMP2_BASE, 0x40004624 +.set CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE, 0x00000002 +.set CYREG_OPAMP2_TR0, 0x40004624 +.set CYREG_OPAMP2_TR1, 0x40004625 +.set CYDEV_MFGCFG_ANAIF_OPAMP3_BASE, 0x40004626 +.set CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE, 0x00000002 +.set CYREG_OPAMP3_TR0, 0x40004626 +.set CYREG_OPAMP3_TR1, 0x40004627 +.set CYDEV_MFGCFG_ANAIF_CMP0_BASE, 0x40004630 +.set CYDEV_MFGCFG_ANAIF_CMP0_SIZE, 0x00000002 +.set CYREG_CMP0_TR0, 0x40004630 +.set CYREG_CMP0_TR1, 0x40004631 +.set CYDEV_MFGCFG_ANAIF_CMP1_BASE, 0x40004632 +.set CYDEV_MFGCFG_ANAIF_CMP1_SIZE, 0x00000002 +.set CYREG_CMP1_TR0, 0x40004632 +.set CYREG_CMP1_TR1, 0x40004633 +.set CYDEV_MFGCFG_ANAIF_CMP2_BASE, 0x40004634 +.set CYDEV_MFGCFG_ANAIF_CMP2_SIZE, 0x00000002 +.set CYREG_CMP2_TR0, 0x40004634 +.set CYREG_CMP2_TR1, 0x40004635 +.set CYDEV_MFGCFG_ANAIF_CMP3_BASE, 0x40004636 +.set CYDEV_MFGCFG_ANAIF_CMP3_SIZE, 0x00000002 +.set CYREG_CMP3_TR0, 0x40004636 +.set CYREG_CMP3_TR1, 0x40004637 +.set CYDEV_MFGCFG_PWRSYS_BASE, 0x40004680 +.set CYDEV_MFGCFG_PWRSYS_SIZE, 0x0000000b +.set CYREG_PWRSYS_HIB_TR0, 0x40004680 +.set CYREG_PWRSYS_HIB_TR1, 0x40004681 +.set CYREG_PWRSYS_I2C_TR, 0x40004682 +.set CYREG_PWRSYS_SLP_TR, 0x40004683 +.set CYREG_PWRSYS_BUZZ_TR, 0x40004684 +.set CYREG_PWRSYS_WAKE_TR0, 0x40004685 +.set CYREG_PWRSYS_WAKE_TR1, 0x40004686 +.set CYREG_PWRSYS_BREF_TR, 0x40004687 +.set CYREG_PWRSYS_BG_TR, 0x40004688 +.set CYREG_PWRSYS_WAKE_TR2, 0x40004689 +.set CYREG_PWRSYS_WAKE_TR3, 0x4000468a +.set CYDEV_MFGCFG_ILO_BASE, 0x40004690 +.set CYDEV_MFGCFG_ILO_SIZE, 0x00000002 +.set CYREG_ILO_TR0, 0x40004690 +.set CYREG_ILO_TR1, 0x40004691 +.set CYDEV_MFGCFG_X32_BASE, 0x40004698 +.set CYDEV_MFGCFG_X32_SIZE, 0x00000001 +.set CYREG_X32_TR, 0x40004698 +.set CYDEV_MFGCFG_IMO_BASE, 0x400046a0 +.set CYDEV_MFGCFG_IMO_SIZE, 0x00000005 +.set CYREG_IMO_TR0, 0x400046a0 +.set CYREG_IMO_TR1, 0x400046a1 +.set CYREG_IMO_GAIN, 0x400046a2 +.set CYREG_IMO_C36M, 0x400046a3 +.set CYREG_IMO_TR2, 0x400046a4 +.set CYDEV_MFGCFG_XMHZ_BASE, 0x400046a8 +.set CYDEV_MFGCFG_XMHZ_SIZE, 0x00000001 +.set CYREG_XMHZ_TR, 0x400046a8 +.set CYREG_MFGCFG_DLY, 0x400046c0 +.set CYDEV_MFGCFG_MLOGIC_BASE, 0x400046e0 +.set CYDEV_MFGCFG_MLOGIC_SIZE, 0x0000000d +.set CYREG_MLOGIC_DMPSTR, 0x400046e2 +.set CYDEV_MFGCFG_MLOGIC_SEG_BASE, 0x400046e4 +.set CYDEV_MFGCFG_MLOGIC_SEG_SIZE, 0x00000002 +.set CYREG_MLOGIC_SEG_CR, 0x400046e4 +.set CYREG_MLOGIC_SEG_CFG0, 0x400046e5 +.set CYREG_MLOGIC_DEBUG, 0x400046e8 +.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE, 0x400046ea +.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE, 0x00000001 +.set CYREG_MLOGIC_CPU_SCR_CPU_SCR, 0x400046ea +.set CYREG_MLOGIC_REV_ID, 0x400046ec +.set CYDEV_RESET_BASE, 0x400046f0 +.set CYDEV_RESET_SIZE, 0x0000000f +.set CYREG_RESET_IPOR_CR0, 0x400046f0 +.set CYREG_RESET_IPOR_CR1, 0x400046f1 +.set CYREG_RESET_IPOR_CR2, 0x400046f2 +.set CYREG_RESET_IPOR_CR3, 0x400046f3 +.set CYREG_RESET_CR0, 0x400046f4 +.set CYREG_RESET_CR1, 0x400046f5 +.set CYREG_RESET_CR2, 0x400046f6 +.set CYREG_RESET_CR3, 0x400046f7 +.set CYREG_RESET_CR4, 0x400046f8 +.set CYREG_RESET_CR5, 0x400046f9 +.set CYREG_RESET_SR0, 0x400046fa +.set CYREG_RESET_SR1, 0x400046fb +.set CYREG_RESET_SR2, 0x400046fc +.set CYREG_RESET_SR3, 0x400046fd +.set CYREG_RESET_TR, 0x400046fe +.set CYDEV_SPC_BASE, 0x40004700 +.set CYDEV_SPC_SIZE, 0x00000100 +.set CYREG_SPC_FM_EE_CR, 0x40004700 +.set CYREG_SPC_FM_EE_WAKE_CNT, 0x40004701 +.set CYREG_SPC_EE_SCR, 0x40004702 +.set CYREG_SPC_EE_ERR, 0x40004703 +.set CYREG_SPC_CPU_DATA, 0x40004720 +.set CYREG_SPC_DMA_DATA, 0x40004721 +.set CYREG_SPC_SR, 0x40004722 +.set CYREG_SPC_CR, 0x40004723 +.set CYDEV_SPC_DMM_MAP_BASE, 0x40004780 +.set CYDEV_SPC_DMM_MAP_SIZE, 0x00000080 +.set CYREG_SPC_DMM_MAP_SRAM_MBASE, 0x40004780 +.set CYREG_SPC_DMM_MAP_SRAM_MSIZE, 0x00000080 +.set CYDEV_CACHE_BASE, 0x40004800 +.set CYDEV_CACHE_SIZE, 0x0000009c +.set CYREG_CACHE_CC_CTL, 0x40004800 +.set CYREG_CACHE_ECC_CORR, 0x40004880 +.set CYREG_CACHE_ECC_ERR, 0x40004888 +.set CYREG_CACHE_FLASH_ERR, 0x40004890 +.set CYREG_CACHE_HITMISS, 0x40004898 +.set CYDEV_I2C_BASE, 0x40004900 +.set CYDEV_I2C_SIZE, 0x000000e1 +.set CYREG_I2C_XCFG, 0x400049c8 +.set CYREG_I2C_ADR, 0x400049ca +.set CYREG_I2C_CFG, 0x400049d6 +.set CYREG_I2C_CSR, 0x400049d7 +.set CYREG_I2C_D, 0x400049d8 +.set CYREG_I2C_MCSR, 0x400049d9 +.set CYREG_I2C_CLK_DIV1, 0x400049db +.set CYREG_I2C_CLK_DIV2, 0x400049dc +.set CYREG_I2C_TMOUT_CSR, 0x400049dd +.set CYREG_I2C_TMOUT_SR, 0x400049de +.set CYREG_I2C_TMOUT_CFG0, 0x400049df +.set CYREG_I2C_TMOUT_CFG1, 0x400049e0 +.set CYDEV_DEC_BASE, 0x40004e00 +.set CYDEV_DEC_SIZE, 0x00000015 +.set CYREG_DEC_CR, 0x40004e00 +.set CYREG_DEC_SR, 0x40004e01 +.set CYREG_DEC_SHIFT1, 0x40004e02 +.set CYREG_DEC_SHIFT2, 0x40004e03 +.set CYREG_DEC_DR2, 0x40004e04 +.set CYREG_DEC_DR2H, 0x40004e05 +.set CYREG_DEC_DR1, 0x40004e06 +.set CYREG_DEC_OCOR, 0x40004e08 +.set CYREG_DEC_OCORM, 0x40004e09 +.set CYREG_DEC_OCORH, 0x40004e0a +.set CYREG_DEC_GCOR, 0x40004e0c +.set CYREG_DEC_GCORH, 0x40004e0d +.set CYREG_DEC_GVAL, 0x40004e0e +.set CYREG_DEC_OUTSAMP, 0x40004e10 +.set CYREG_DEC_OUTSAMPM, 0x40004e11 +.set CYREG_DEC_OUTSAMPH, 0x40004e12 +.set CYREG_DEC_OUTSAMPS, 0x40004e13 +.set CYREG_DEC_COHER, 0x40004e14 +.set CYDEV_TMR0_BASE, 0x40004f00 +.set CYDEV_TMR0_SIZE, 0x0000000c +.set CYREG_TMR0_CFG0, 0x40004f00 +.set CYREG_TMR0_CFG1, 0x40004f01 +.set CYREG_TMR0_CFG2, 0x40004f02 +.set CYREG_TMR0_SR0, 0x40004f03 +.set CYREG_TMR0_PER0, 0x40004f04 +.set CYREG_TMR0_PER1, 0x40004f05 +.set CYREG_TMR0_CNT_CMP0, 0x40004f06 +.set CYREG_TMR0_CNT_CMP1, 0x40004f07 +.set CYREG_TMR0_CAP0, 0x40004f08 +.set CYREG_TMR0_CAP1, 0x40004f09 +.set CYREG_TMR0_RT0, 0x40004f0a +.set CYREG_TMR0_RT1, 0x40004f0b +.set CYDEV_TMR1_BASE, 0x40004f0c +.set CYDEV_TMR1_SIZE, 0x0000000c +.set CYREG_TMR1_CFG0, 0x40004f0c +.set CYREG_TMR1_CFG1, 0x40004f0d +.set CYREG_TMR1_CFG2, 0x40004f0e +.set CYREG_TMR1_SR0, 0x40004f0f +.set CYREG_TMR1_PER0, 0x40004f10 +.set CYREG_TMR1_PER1, 0x40004f11 +.set CYREG_TMR1_CNT_CMP0, 0x40004f12 +.set CYREG_TMR1_CNT_CMP1, 0x40004f13 +.set CYREG_TMR1_CAP0, 0x40004f14 +.set CYREG_TMR1_CAP1, 0x40004f15 +.set CYREG_TMR1_RT0, 0x40004f16 +.set CYREG_TMR1_RT1, 0x40004f17 +.set CYDEV_TMR2_BASE, 0x40004f18 +.set CYDEV_TMR2_SIZE, 0x0000000c +.set CYREG_TMR2_CFG0, 0x40004f18 +.set CYREG_TMR2_CFG1, 0x40004f19 +.set CYREG_TMR2_CFG2, 0x40004f1a +.set CYREG_TMR2_SR0, 0x40004f1b +.set CYREG_TMR2_PER0, 0x40004f1c +.set CYREG_TMR2_PER1, 0x40004f1d +.set CYREG_TMR2_CNT_CMP0, 0x40004f1e +.set CYREG_TMR2_CNT_CMP1, 0x40004f1f +.set CYREG_TMR2_CAP0, 0x40004f20 +.set CYREG_TMR2_CAP1, 0x40004f21 +.set CYREG_TMR2_RT0, 0x40004f22 +.set CYREG_TMR2_RT1, 0x40004f23 +.set CYDEV_TMR3_BASE, 0x40004f24 +.set CYDEV_TMR3_SIZE, 0x0000000c +.set CYREG_TMR3_CFG0, 0x40004f24 +.set CYREG_TMR3_CFG1, 0x40004f25 +.set CYREG_TMR3_CFG2, 0x40004f26 +.set CYREG_TMR3_SR0, 0x40004f27 +.set CYREG_TMR3_PER0, 0x40004f28 +.set CYREG_TMR3_PER1, 0x40004f29 +.set CYREG_TMR3_CNT_CMP0, 0x40004f2a +.set CYREG_TMR3_CNT_CMP1, 0x40004f2b +.set CYREG_TMR3_CAP0, 0x40004f2c +.set CYREG_TMR3_CAP1, 0x40004f2d +.set CYREG_TMR3_RT0, 0x40004f2e +.set CYREG_TMR3_RT1, 0x40004f2f +.set CYDEV_IO_BASE, 0x40005000 +.set CYDEV_IO_SIZE, 0x00000200 +.set CYDEV_IO_PC_BASE, 0x40005000 +.set CYDEV_IO_PC_SIZE, 0x00000080 +.set CYDEV_IO_PC_PRT0_BASE, 0x40005000 +.set CYDEV_IO_PC_PRT0_SIZE, 0x00000008 +.set CYREG_PRT0_PC0, 0x40005000 +.set CYREG_PRT0_PC1, 0x40005001 +.set CYREG_PRT0_PC2, 0x40005002 +.set CYREG_PRT0_PC3, 0x40005003 +.set CYREG_PRT0_PC4, 0x40005004 +.set CYREG_PRT0_PC5, 0x40005005 +.set CYREG_PRT0_PC6, 0x40005006 +.set CYREG_PRT0_PC7, 0x40005007 +.set CYDEV_IO_PC_PRT1_BASE, 0x40005008 +.set CYDEV_IO_PC_PRT1_SIZE, 0x00000008 +.set CYREG_PRT1_PC0, 0x40005008 +.set CYREG_PRT1_PC1, 0x40005009 +.set CYREG_PRT1_PC2, 0x4000500a +.set CYREG_PRT1_PC3, 0x4000500b +.set CYREG_PRT1_PC4, 0x4000500c +.set CYREG_PRT1_PC5, 0x4000500d +.set CYREG_PRT1_PC6, 0x4000500e +.set CYREG_PRT1_PC7, 0x4000500f +.set CYDEV_IO_PC_PRT2_BASE, 0x40005010 +.set CYDEV_IO_PC_PRT2_SIZE, 0x00000008 +.set CYREG_PRT2_PC0, 0x40005010 +.set CYREG_PRT2_PC1, 0x40005011 +.set CYREG_PRT2_PC2, 0x40005012 +.set CYREG_PRT2_PC3, 0x40005013 +.set CYREG_PRT2_PC4, 0x40005014 +.set CYREG_PRT2_PC5, 0x40005015 +.set CYREG_PRT2_PC6, 0x40005016 +.set CYREG_PRT2_PC7, 0x40005017 +.set CYDEV_IO_PC_PRT3_BASE, 0x40005018 +.set CYDEV_IO_PC_PRT3_SIZE, 0x00000008 +.set CYREG_PRT3_PC0, 0x40005018 +.set CYREG_PRT3_PC1, 0x40005019 +.set CYREG_PRT3_PC2, 0x4000501a +.set CYREG_PRT3_PC3, 0x4000501b +.set CYREG_PRT3_PC4, 0x4000501c +.set CYREG_PRT3_PC5, 0x4000501d +.set CYREG_PRT3_PC6, 0x4000501e +.set CYREG_PRT3_PC7, 0x4000501f +.set CYDEV_IO_PC_PRT4_BASE, 0x40005020 +.set CYDEV_IO_PC_PRT4_SIZE, 0x00000008 +.set CYREG_PRT4_PC0, 0x40005020 +.set CYREG_PRT4_PC1, 0x40005021 +.set CYREG_PRT4_PC2, 0x40005022 +.set CYREG_PRT4_PC3, 0x40005023 +.set CYREG_PRT4_PC4, 0x40005024 +.set CYREG_PRT4_PC5, 0x40005025 +.set CYREG_PRT4_PC6, 0x40005026 +.set CYREG_PRT4_PC7, 0x40005027 +.set CYDEV_IO_PC_PRT5_BASE, 0x40005028 +.set CYDEV_IO_PC_PRT5_SIZE, 0x00000008 +.set CYREG_PRT5_PC0, 0x40005028 +.set CYREG_PRT5_PC1, 0x40005029 +.set CYREG_PRT5_PC2, 0x4000502a +.set CYREG_PRT5_PC3, 0x4000502b +.set CYREG_PRT5_PC4, 0x4000502c +.set CYREG_PRT5_PC5, 0x4000502d +.set CYREG_PRT5_PC6, 0x4000502e +.set CYREG_PRT5_PC7, 0x4000502f +.set CYDEV_IO_PC_PRT6_BASE, 0x40005030 +.set CYDEV_IO_PC_PRT6_SIZE, 0x00000008 +.set CYREG_PRT6_PC0, 0x40005030 +.set CYREG_PRT6_PC1, 0x40005031 +.set CYREG_PRT6_PC2, 0x40005032 +.set CYREG_PRT6_PC3, 0x40005033 +.set CYREG_PRT6_PC4, 0x40005034 +.set CYREG_PRT6_PC5, 0x40005035 +.set CYREG_PRT6_PC6, 0x40005036 +.set CYREG_PRT6_PC7, 0x40005037 +.set CYDEV_IO_PC_PRT12_BASE, 0x40005060 +.set CYDEV_IO_PC_PRT12_SIZE, 0x00000008 +.set CYREG_PRT12_PC0, 0x40005060 +.set CYREG_PRT12_PC1, 0x40005061 +.set CYREG_PRT12_PC2, 0x40005062 +.set CYREG_PRT12_PC3, 0x40005063 +.set CYREG_PRT12_PC4, 0x40005064 +.set CYREG_PRT12_PC5, 0x40005065 +.set CYREG_PRT12_PC6, 0x40005066 +.set CYREG_PRT12_PC7, 0x40005067 +.set CYDEV_IO_PC_PRT15_BASE, 0x40005078 +.set CYDEV_IO_PC_PRT15_SIZE, 0x00000006 +.set CYREG_IO_PC_PRT15_PC0, 0x40005078 +.set CYREG_IO_PC_PRT15_PC1, 0x40005079 +.set CYREG_IO_PC_PRT15_PC2, 0x4000507a +.set CYREG_IO_PC_PRT15_PC3, 0x4000507b +.set CYREG_IO_PC_PRT15_PC4, 0x4000507c +.set CYREG_IO_PC_PRT15_PC5, 0x4000507d +.set CYDEV_IO_PC_PRT15_7_6_BASE, 0x4000507e +.set CYDEV_IO_PC_PRT15_7_6_SIZE, 0x00000002 +.set CYREG_IO_PC_PRT15_7_6_PC0, 0x4000507e +.set CYREG_IO_PC_PRT15_7_6_PC1, 0x4000507f +.set CYDEV_IO_DR_BASE, 0x40005080 +.set CYDEV_IO_DR_SIZE, 0x00000010 +.set CYDEV_IO_DR_PRT0_BASE, 0x40005080 +.set CYDEV_IO_DR_PRT0_SIZE, 0x00000001 +.set CYREG_PRT0_DR_ALIAS, 0x40005080 +.set CYDEV_IO_DR_PRT1_BASE, 0x40005081 +.set CYDEV_IO_DR_PRT1_SIZE, 0x00000001 +.set CYREG_PRT1_DR_ALIAS, 0x40005081 +.set CYDEV_IO_DR_PRT2_BASE, 0x40005082 +.set CYDEV_IO_DR_PRT2_SIZE, 0x00000001 +.set CYREG_PRT2_DR_ALIAS, 0x40005082 +.set CYDEV_IO_DR_PRT3_BASE, 0x40005083 +.set CYDEV_IO_DR_PRT3_SIZE, 0x00000001 +.set CYREG_PRT3_DR_ALIAS, 0x40005083 +.set CYDEV_IO_DR_PRT4_BASE, 0x40005084 +.set CYDEV_IO_DR_PRT4_SIZE, 0x00000001 +.set CYREG_PRT4_DR_ALIAS, 0x40005084 +.set CYDEV_IO_DR_PRT5_BASE, 0x40005085 +.set CYDEV_IO_DR_PRT5_SIZE, 0x00000001 +.set CYREG_PRT5_DR_ALIAS, 0x40005085 +.set CYDEV_IO_DR_PRT6_BASE, 0x40005086 +.set CYDEV_IO_DR_PRT6_SIZE, 0x00000001 +.set CYREG_PRT6_DR_ALIAS, 0x40005086 +.set CYDEV_IO_DR_PRT12_BASE, 0x4000508c +.set CYDEV_IO_DR_PRT12_SIZE, 0x00000001 +.set CYREG_PRT12_DR_ALIAS, 0x4000508c +.set CYDEV_IO_DR_PRT15_BASE, 0x4000508f +.set CYDEV_IO_DR_PRT15_SIZE, 0x00000001 +.set CYREG_PRT15_DR_15_ALIAS, 0x4000508f +.set CYDEV_IO_PS_BASE, 0x40005090 +.set CYDEV_IO_PS_SIZE, 0x00000010 +.set CYDEV_IO_PS_PRT0_BASE, 0x40005090 +.set CYDEV_IO_PS_PRT0_SIZE, 0x00000001 +.set CYREG_PRT0_PS_ALIAS, 0x40005090 +.set CYDEV_IO_PS_PRT1_BASE, 0x40005091 +.set CYDEV_IO_PS_PRT1_SIZE, 0x00000001 +.set CYREG_PRT1_PS_ALIAS, 0x40005091 +.set CYDEV_IO_PS_PRT2_BASE, 0x40005092 +.set CYDEV_IO_PS_PRT2_SIZE, 0x00000001 +.set CYREG_PRT2_PS_ALIAS, 0x40005092 +.set CYDEV_IO_PS_PRT3_BASE, 0x40005093 +.set CYDEV_IO_PS_PRT3_SIZE, 0x00000001 +.set CYREG_PRT3_PS_ALIAS, 0x40005093 +.set CYDEV_IO_PS_PRT4_BASE, 0x40005094 +.set CYDEV_IO_PS_PRT4_SIZE, 0x00000001 +.set CYREG_PRT4_PS_ALIAS, 0x40005094 +.set CYDEV_IO_PS_PRT5_BASE, 0x40005095 +.set CYDEV_IO_PS_PRT5_SIZE, 0x00000001 +.set CYREG_PRT5_PS_ALIAS, 0x40005095 +.set CYDEV_IO_PS_PRT6_BASE, 0x40005096 +.set CYDEV_IO_PS_PRT6_SIZE, 0x00000001 +.set CYREG_PRT6_PS_ALIAS, 0x40005096 +.set CYDEV_IO_PS_PRT12_BASE, 0x4000509c +.set CYDEV_IO_PS_PRT12_SIZE, 0x00000001 +.set CYREG_PRT12_PS_ALIAS, 0x4000509c +.set CYDEV_IO_PS_PRT15_BASE, 0x4000509f +.set CYDEV_IO_PS_PRT15_SIZE, 0x00000001 +.set CYREG_PRT15_PS15_ALIAS, 0x4000509f +.set CYDEV_IO_PRT_BASE, 0x40005100 +.set CYDEV_IO_PRT_SIZE, 0x00000100 +.set CYDEV_IO_PRT_PRT0_BASE, 0x40005100 +.set CYDEV_IO_PRT_PRT0_SIZE, 0x00000010 +.set CYREG_PRT0_DR, 0x40005100 +.set CYREG_PRT0_PS, 0x40005101 +.set CYREG_PRT0_DM0, 0x40005102 +.set CYREG_PRT0_DM1, 0x40005103 +.set CYREG_PRT0_DM2, 0x40005104 +.set CYREG_PRT0_SLW, 0x40005105 +.set CYREG_PRT0_BYP, 0x40005106 +.set CYREG_PRT0_BIE, 0x40005107 +.set CYREG_PRT0_INP_DIS, 0x40005108 +.set CYREG_PRT0_CTL, 0x40005109 +.set CYREG_PRT0_PRT, 0x4000510a +.set CYREG_PRT0_BIT_MASK, 0x4000510b +.set CYREG_PRT0_AMUX, 0x4000510c +.set CYREG_PRT0_AG, 0x4000510d +.set CYREG_PRT0_LCD_COM_SEG, 0x4000510e +.set CYREG_PRT0_LCD_EN, 0x4000510f +.set CYDEV_IO_PRT_PRT1_BASE, 0x40005110 +.set CYDEV_IO_PRT_PRT1_SIZE, 0x00000010 +.set CYREG_PRT1_DR, 0x40005110 +.set CYREG_PRT1_PS, 0x40005111 +.set CYREG_PRT1_DM0, 0x40005112 +.set CYREG_PRT1_DM1, 0x40005113 +.set CYREG_PRT1_DM2, 0x40005114 +.set CYREG_PRT1_SLW, 0x40005115 +.set CYREG_PRT1_BYP, 0x40005116 +.set CYREG_PRT1_BIE, 0x40005117 +.set CYREG_PRT1_INP_DIS, 0x40005118 +.set CYREG_PRT1_CTL, 0x40005119 +.set CYREG_PRT1_PRT, 0x4000511a +.set CYREG_PRT1_BIT_MASK, 0x4000511b +.set CYREG_PRT1_AMUX, 0x4000511c +.set CYREG_PRT1_AG, 0x4000511d +.set CYREG_PRT1_LCD_COM_SEG, 0x4000511e +.set CYREG_PRT1_LCD_EN, 0x4000511f +.set CYDEV_IO_PRT_PRT2_BASE, 0x40005120 +.set CYDEV_IO_PRT_PRT2_SIZE, 0x00000010 +.set CYREG_PRT2_DR, 0x40005120 +.set CYREG_PRT2_PS, 0x40005121 +.set CYREG_PRT2_DM0, 0x40005122 +.set CYREG_PRT2_DM1, 0x40005123 +.set CYREG_PRT2_DM2, 0x40005124 +.set CYREG_PRT2_SLW, 0x40005125 +.set CYREG_PRT2_BYP, 0x40005126 +.set CYREG_PRT2_BIE, 0x40005127 +.set CYREG_PRT2_INP_DIS, 0x40005128 +.set CYREG_PRT2_CTL, 0x40005129 +.set CYREG_PRT2_PRT, 0x4000512a +.set CYREG_PRT2_BIT_MASK, 0x4000512b +.set CYREG_PRT2_AMUX, 0x4000512c +.set CYREG_PRT2_AG, 0x4000512d +.set CYREG_PRT2_LCD_COM_SEG, 0x4000512e +.set CYREG_PRT2_LCD_EN, 0x4000512f +.set CYDEV_IO_PRT_PRT3_BASE, 0x40005130 +.set CYDEV_IO_PRT_PRT3_SIZE, 0x00000010 +.set CYREG_PRT3_DR, 0x40005130 +.set CYREG_PRT3_PS, 0x40005131 +.set CYREG_PRT3_DM0, 0x40005132 +.set CYREG_PRT3_DM1, 0x40005133 +.set CYREG_PRT3_DM2, 0x40005134 +.set CYREG_PRT3_SLW, 0x40005135 +.set CYREG_PRT3_BYP, 0x40005136 +.set CYREG_PRT3_BIE, 0x40005137 +.set CYREG_PRT3_INP_DIS, 0x40005138 +.set CYREG_PRT3_CTL, 0x40005139 +.set CYREG_PRT3_PRT, 0x4000513a +.set CYREG_PRT3_BIT_MASK, 0x4000513b +.set CYREG_PRT3_AMUX, 0x4000513c +.set CYREG_PRT3_AG, 0x4000513d +.set CYREG_PRT3_LCD_COM_SEG, 0x4000513e +.set CYREG_PRT3_LCD_EN, 0x4000513f +.set CYDEV_IO_PRT_PRT4_BASE, 0x40005140 +.set CYDEV_IO_PRT_PRT4_SIZE, 0x00000010 +.set CYREG_PRT4_DR, 0x40005140 +.set CYREG_PRT4_PS, 0x40005141 +.set CYREG_PRT4_DM0, 0x40005142 +.set CYREG_PRT4_DM1, 0x40005143 +.set CYREG_PRT4_DM2, 0x40005144 +.set CYREG_PRT4_SLW, 0x40005145 +.set CYREG_PRT4_BYP, 0x40005146 +.set CYREG_PRT4_BIE, 0x40005147 +.set CYREG_PRT4_INP_DIS, 0x40005148 +.set CYREG_PRT4_CTL, 0x40005149 +.set CYREG_PRT4_PRT, 0x4000514a +.set CYREG_PRT4_BIT_MASK, 0x4000514b +.set CYREG_PRT4_AMUX, 0x4000514c +.set CYREG_PRT4_AG, 0x4000514d +.set CYREG_PRT4_LCD_COM_SEG, 0x4000514e +.set CYREG_PRT4_LCD_EN, 0x4000514f +.set CYDEV_IO_PRT_PRT5_BASE, 0x40005150 +.set CYDEV_IO_PRT_PRT5_SIZE, 0x00000010 +.set CYREG_PRT5_DR, 0x40005150 +.set CYREG_PRT5_PS, 0x40005151 +.set CYREG_PRT5_DM0, 0x40005152 +.set CYREG_PRT5_DM1, 0x40005153 +.set CYREG_PRT5_DM2, 0x40005154 +.set CYREG_PRT5_SLW, 0x40005155 +.set CYREG_PRT5_BYP, 0x40005156 +.set CYREG_PRT5_BIE, 0x40005157 +.set CYREG_PRT5_INP_DIS, 0x40005158 +.set CYREG_PRT5_CTL, 0x40005159 +.set CYREG_PRT5_PRT, 0x4000515a +.set CYREG_PRT5_BIT_MASK, 0x4000515b +.set CYREG_PRT5_AMUX, 0x4000515c +.set CYREG_PRT5_AG, 0x4000515d +.set CYREG_PRT5_LCD_COM_SEG, 0x4000515e +.set CYREG_PRT5_LCD_EN, 0x4000515f +.set CYDEV_IO_PRT_PRT6_BASE, 0x40005160 +.set CYDEV_IO_PRT_PRT6_SIZE, 0x00000010 +.set CYREG_PRT6_DR, 0x40005160 +.set CYREG_PRT6_PS, 0x40005161 +.set CYREG_PRT6_DM0, 0x40005162 +.set CYREG_PRT6_DM1, 0x40005163 +.set CYREG_PRT6_DM2, 0x40005164 +.set CYREG_PRT6_SLW, 0x40005165 +.set CYREG_PRT6_BYP, 0x40005166 +.set CYREG_PRT6_BIE, 0x40005167 +.set CYREG_PRT6_INP_DIS, 0x40005168 +.set CYREG_PRT6_CTL, 0x40005169 +.set CYREG_PRT6_PRT, 0x4000516a +.set CYREG_PRT6_BIT_MASK, 0x4000516b +.set CYREG_PRT6_AMUX, 0x4000516c +.set CYREG_PRT6_AG, 0x4000516d +.set CYREG_PRT6_LCD_COM_SEG, 0x4000516e +.set CYREG_PRT6_LCD_EN, 0x4000516f +.set CYDEV_IO_PRT_PRT12_BASE, 0x400051c0 +.set CYDEV_IO_PRT_PRT12_SIZE, 0x00000010 +.set CYREG_PRT12_DR, 0x400051c0 +.set CYREG_PRT12_PS, 0x400051c1 +.set CYREG_PRT12_DM0, 0x400051c2 +.set CYREG_PRT12_DM1, 0x400051c3 +.set CYREG_PRT12_DM2, 0x400051c4 +.set CYREG_PRT12_SLW, 0x400051c5 +.set CYREG_PRT12_BYP, 0x400051c6 +.set CYREG_PRT12_BIE, 0x400051c7 +.set CYREG_PRT12_INP_DIS, 0x400051c8 +.set CYREG_PRT12_SIO_HYST_EN, 0x400051c9 +.set CYREG_PRT12_PRT, 0x400051ca +.set CYREG_PRT12_BIT_MASK, 0x400051cb +.set CYREG_PRT12_SIO_REG_HIFREQ, 0x400051cc +.set CYREG_PRT12_AG, 0x400051cd +.set CYREG_PRT12_SIO_CFG, 0x400051ce +.set CYREG_PRT12_SIO_DIFF, 0x400051cf +.set CYDEV_IO_PRT_PRT15_BASE, 0x400051f0 +.set CYDEV_IO_PRT_PRT15_SIZE, 0x00000010 +.set CYREG_PRT15_DR, 0x400051f0 +.set CYREG_PRT15_PS, 0x400051f1 +.set CYREG_PRT15_DM0, 0x400051f2 +.set CYREG_PRT15_DM1, 0x400051f3 +.set CYREG_PRT15_DM2, 0x400051f4 +.set CYREG_PRT15_SLW, 0x400051f5 +.set CYREG_PRT15_BYP, 0x400051f6 +.set CYREG_PRT15_BIE, 0x400051f7 +.set CYREG_PRT15_INP_DIS, 0x400051f8 +.set CYREG_PRT15_CTL, 0x400051f9 +.set CYREG_PRT15_PRT, 0x400051fa +.set CYREG_PRT15_BIT_MASK, 0x400051fb +.set CYREG_PRT15_AMUX, 0x400051fc +.set CYREG_PRT15_AG, 0x400051fd +.set CYREG_PRT15_LCD_COM_SEG, 0x400051fe +.set CYREG_PRT15_LCD_EN, 0x400051ff +.set CYDEV_PRTDSI_BASE, 0x40005200 +.set CYDEV_PRTDSI_SIZE, 0x0000007f +.set CYDEV_PRTDSI_PRT0_BASE, 0x40005200 +.set CYDEV_PRTDSI_PRT0_SIZE, 0x00000007 +.set CYREG_PRT0_OUT_SEL0, 0x40005200 +.set CYREG_PRT0_OUT_SEL1, 0x40005201 +.set CYREG_PRT0_OE_SEL0, 0x40005202 +.set CYREG_PRT0_OE_SEL1, 0x40005203 +.set CYREG_PRT0_DBL_SYNC_IN, 0x40005204 +.set CYREG_PRT0_SYNC_OUT, 0x40005205 +.set CYREG_PRT0_CAPS_SEL, 0x40005206 +.set CYDEV_PRTDSI_PRT1_BASE, 0x40005208 +.set CYDEV_PRTDSI_PRT1_SIZE, 0x00000007 +.set CYREG_PRT1_OUT_SEL0, 0x40005208 +.set CYREG_PRT1_OUT_SEL1, 0x40005209 +.set CYREG_PRT1_OE_SEL0, 0x4000520a +.set CYREG_PRT1_OE_SEL1, 0x4000520b +.set CYREG_PRT1_DBL_SYNC_IN, 0x4000520c +.set CYREG_PRT1_SYNC_OUT, 0x4000520d +.set CYREG_PRT1_CAPS_SEL, 0x4000520e +.set CYDEV_PRTDSI_PRT2_BASE, 0x40005210 +.set CYDEV_PRTDSI_PRT2_SIZE, 0x00000007 +.set CYREG_PRT2_OUT_SEL0, 0x40005210 +.set CYREG_PRT2_OUT_SEL1, 0x40005211 +.set CYREG_PRT2_OE_SEL0, 0x40005212 +.set CYREG_PRT2_OE_SEL1, 0x40005213 +.set CYREG_PRT2_DBL_SYNC_IN, 0x40005214 +.set CYREG_PRT2_SYNC_OUT, 0x40005215 +.set CYREG_PRT2_CAPS_SEL, 0x40005216 +.set CYDEV_PRTDSI_PRT3_BASE, 0x40005218 +.set CYDEV_PRTDSI_PRT3_SIZE, 0x00000007 +.set CYREG_PRT3_OUT_SEL0, 0x40005218 +.set CYREG_PRT3_OUT_SEL1, 0x40005219 +.set CYREG_PRT3_OE_SEL0, 0x4000521a +.set CYREG_PRT3_OE_SEL1, 0x4000521b +.set CYREG_PRT3_DBL_SYNC_IN, 0x4000521c +.set CYREG_PRT3_SYNC_OUT, 0x4000521d +.set CYREG_PRT3_CAPS_SEL, 0x4000521e +.set CYDEV_PRTDSI_PRT4_BASE, 0x40005220 +.set CYDEV_PRTDSI_PRT4_SIZE, 0x00000007 +.set CYREG_PRT4_OUT_SEL0, 0x40005220 +.set CYREG_PRT4_OUT_SEL1, 0x40005221 +.set CYREG_PRT4_OE_SEL0, 0x40005222 +.set CYREG_PRT4_OE_SEL1, 0x40005223 +.set CYREG_PRT4_DBL_SYNC_IN, 0x40005224 +.set CYREG_PRT4_SYNC_OUT, 0x40005225 +.set CYREG_PRT4_CAPS_SEL, 0x40005226 +.set CYDEV_PRTDSI_PRT5_BASE, 0x40005228 +.set CYDEV_PRTDSI_PRT5_SIZE, 0x00000007 +.set CYREG_PRT5_OUT_SEL0, 0x40005228 +.set CYREG_PRT5_OUT_SEL1, 0x40005229 +.set CYREG_PRT5_OE_SEL0, 0x4000522a +.set CYREG_PRT5_OE_SEL1, 0x4000522b +.set CYREG_PRT5_DBL_SYNC_IN, 0x4000522c +.set CYREG_PRT5_SYNC_OUT, 0x4000522d +.set CYREG_PRT5_CAPS_SEL, 0x4000522e +.set CYDEV_PRTDSI_PRT6_BASE, 0x40005230 +.set CYDEV_PRTDSI_PRT6_SIZE, 0x00000007 +.set CYREG_PRT6_OUT_SEL0, 0x40005230 +.set CYREG_PRT6_OUT_SEL1, 0x40005231 +.set CYREG_PRT6_OE_SEL0, 0x40005232 +.set CYREG_PRT6_OE_SEL1, 0x40005233 +.set CYREG_PRT6_DBL_SYNC_IN, 0x40005234 +.set CYREG_PRT6_SYNC_OUT, 0x40005235 +.set CYREG_PRT6_CAPS_SEL, 0x40005236 +.set CYDEV_PRTDSI_PRT12_BASE, 0x40005260 +.set CYDEV_PRTDSI_PRT12_SIZE, 0x00000006 +.set CYREG_PRT12_OUT_SEL0, 0x40005260 +.set CYREG_PRT12_OUT_SEL1, 0x40005261 +.set CYREG_PRT12_OE_SEL0, 0x40005262 +.set CYREG_PRT12_OE_SEL1, 0x40005263 +.set CYREG_PRT12_DBL_SYNC_IN, 0x40005264 +.set CYREG_PRT12_SYNC_OUT, 0x40005265 +.set CYDEV_PRTDSI_PRT15_BASE, 0x40005278 +.set CYDEV_PRTDSI_PRT15_SIZE, 0x00000007 +.set CYREG_PRT15_OUT_SEL0, 0x40005278 +.set CYREG_PRT15_OUT_SEL1, 0x40005279 +.set CYREG_PRT15_OE_SEL0, 0x4000527a +.set CYREG_PRT15_OE_SEL1, 0x4000527b +.set CYREG_PRT15_DBL_SYNC_IN, 0x4000527c +.set CYREG_PRT15_SYNC_OUT, 0x4000527d +.set CYREG_PRT15_CAPS_SEL, 0x4000527e +.set CYDEV_EMIF_BASE, 0x40005400 +.set CYDEV_EMIF_SIZE, 0x00000007 +.set CYREG_EMIF_NO_UDB, 0x40005400 +.set CYREG_EMIF_RP_WAIT_STATES, 0x40005401 +.set CYREG_EMIF_MEM_DWN, 0x40005402 +.set CYREG_EMIF_MEMCLK_DIV, 0x40005403 +.set CYREG_EMIF_CLOCK_EN, 0x40005404 +.set CYREG_EMIF_EM_TYPE, 0x40005405 +.set CYREG_EMIF_WP_WAIT_STATES, 0x40005406 +.set CYDEV_ANAIF_BASE, 0x40005800 +.set CYDEV_ANAIF_SIZE, 0x000003a9 +.set CYDEV_ANAIF_CFG_BASE, 0x40005800 +.set CYDEV_ANAIF_CFG_SIZE, 0x0000010f +.set CYDEV_ANAIF_CFG_SC0_BASE, 0x40005800 +.set CYDEV_ANAIF_CFG_SC0_SIZE, 0x00000003 +.set CYREG_SC0_CR0, 0x40005800 +.set CYREG_SC0_CR1, 0x40005801 +.set CYREG_SC0_CR2, 0x40005802 +.set CYDEV_ANAIF_CFG_SC1_BASE, 0x40005804 +.set CYDEV_ANAIF_CFG_SC1_SIZE, 0x00000003 +.set CYREG_SC1_CR0, 0x40005804 +.set CYREG_SC1_CR1, 0x40005805 +.set CYREG_SC1_CR2, 0x40005806 +.set CYDEV_ANAIF_CFG_SC2_BASE, 0x40005808 +.set CYDEV_ANAIF_CFG_SC2_SIZE, 0x00000003 +.set CYREG_SC2_CR0, 0x40005808 +.set CYREG_SC2_CR1, 0x40005809 +.set CYREG_SC2_CR2, 0x4000580a +.set CYDEV_ANAIF_CFG_SC3_BASE, 0x4000580c +.set CYDEV_ANAIF_CFG_SC3_SIZE, 0x00000003 +.set CYREG_SC3_CR0, 0x4000580c +.set CYREG_SC3_CR1, 0x4000580d +.set CYREG_SC3_CR2, 0x4000580e +.set CYDEV_ANAIF_CFG_DAC0_BASE, 0x40005820 +.set CYDEV_ANAIF_CFG_DAC0_SIZE, 0x00000003 +.set CYREG_DAC0_CR0, 0x40005820 +.set CYREG_DAC0_CR1, 0x40005821 +.set CYREG_DAC0_TST, 0x40005822 +.set CYDEV_ANAIF_CFG_DAC1_BASE, 0x40005824 +.set CYDEV_ANAIF_CFG_DAC1_SIZE, 0x00000003 +.set CYREG_DAC1_CR0, 0x40005824 +.set CYREG_DAC1_CR1, 0x40005825 +.set CYREG_DAC1_TST, 0x40005826 +.set CYDEV_ANAIF_CFG_DAC2_BASE, 0x40005828 +.set CYDEV_ANAIF_CFG_DAC2_SIZE, 0x00000003 +.set CYREG_DAC2_CR0, 0x40005828 +.set CYREG_DAC2_CR1, 0x40005829 +.set CYREG_DAC2_TST, 0x4000582a +.set CYDEV_ANAIF_CFG_DAC3_BASE, 0x4000582c +.set CYDEV_ANAIF_CFG_DAC3_SIZE, 0x00000003 +.set CYREG_DAC3_CR0, 0x4000582c +.set CYREG_DAC3_CR1, 0x4000582d +.set CYREG_DAC3_TST, 0x4000582e +.set CYDEV_ANAIF_CFG_CMP0_BASE, 0x40005840 +.set CYDEV_ANAIF_CFG_CMP0_SIZE, 0x00000001 +.set CYREG_CMP0_CR, 0x40005840 +.set CYDEV_ANAIF_CFG_CMP1_BASE, 0x40005841 +.set CYDEV_ANAIF_CFG_CMP1_SIZE, 0x00000001 +.set CYREG_CMP1_CR, 0x40005841 +.set CYDEV_ANAIF_CFG_CMP2_BASE, 0x40005842 +.set CYDEV_ANAIF_CFG_CMP2_SIZE, 0x00000001 +.set CYREG_CMP2_CR, 0x40005842 +.set CYDEV_ANAIF_CFG_CMP3_BASE, 0x40005843 +.set CYDEV_ANAIF_CFG_CMP3_SIZE, 0x00000001 +.set CYREG_CMP3_CR, 0x40005843 +.set CYDEV_ANAIF_CFG_LUT0_BASE, 0x40005848 +.set CYDEV_ANAIF_CFG_LUT0_SIZE, 0x00000002 +.set CYREG_LUT0_CR, 0x40005848 +.set CYREG_LUT0_MX, 0x40005849 +.set CYDEV_ANAIF_CFG_LUT1_BASE, 0x4000584a +.set CYDEV_ANAIF_CFG_LUT1_SIZE, 0x00000002 +.set CYREG_LUT1_CR, 0x4000584a +.set CYREG_LUT1_MX, 0x4000584b +.set CYDEV_ANAIF_CFG_LUT2_BASE, 0x4000584c +.set CYDEV_ANAIF_CFG_LUT2_SIZE, 0x00000002 +.set CYREG_LUT2_CR, 0x4000584c +.set CYREG_LUT2_MX, 0x4000584d +.set CYDEV_ANAIF_CFG_LUT3_BASE, 0x4000584e +.set CYDEV_ANAIF_CFG_LUT3_SIZE, 0x00000002 +.set CYREG_LUT3_CR, 0x4000584e +.set CYREG_LUT3_MX, 0x4000584f +.set CYDEV_ANAIF_CFG_OPAMP0_BASE, 0x40005858 +.set CYDEV_ANAIF_CFG_OPAMP0_SIZE, 0x00000002 +.set CYREG_OPAMP0_CR, 0x40005858 +.set CYREG_OPAMP0_RSVD, 0x40005859 +.set CYDEV_ANAIF_CFG_OPAMP1_BASE, 0x4000585a +.set CYDEV_ANAIF_CFG_OPAMP1_SIZE, 0x00000002 +.set CYREG_OPAMP1_CR, 0x4000585a +.set CYREG_OPAMP1_RSVD, 0x4000585b +.set CYDEV_ANAIF_CFG_OPAMP2_BASE, 0x4000585c +.set CYDEV_ANAIF_CFG_OPAMP2_SIZE, 0x00000002 +.set CYREG_OPAMP2_CR, 0x4000585c +.set CYREG_OPAMP2_RSVD, 0x4000585d +.set CYDEV_ANAIF_CFG_OPAMP3_BASE, 0x4000585e +.set CYDEV_ANAIF_CFG_OPAMP3_SIZE, 0x00000002 +.set CYREG_OPAMP3_CR, 0x4000585e +.set CYREG_OPAMP3_RSVD, 0x4000585f +.set CYDEV_ANAIF_CFG_LCDDAC_BASE, 0x40005868 +.set CYDEV_ANAIF_CFG_LCDDAC_SIZE, 0x00000002 +.set CYREG_LCDDAC_CR0, 0x40005868 +.set CYREG_LCDDAC_CR1, 0x40005869 +.set CYDEV_ANAIF_CFG_LCDDRV_BASE, 0x4000586a +.set CYDEV_ANAIF_CFG_LCDDRV_SIZE, 0x00000001 +.set CYREG_LCDDRV_CR, 0x4000586a +.set CYDEV_ANAIF_CFG_LCDTMR_BASE, 0x4000586b +.set CYDEV_ANAIF_CFG_LCDTMR_SIZE, 0x00000001 +.set CYREG_LCDTMR_CFG, 0x4000586b +.set CYDEV_ANAIF_CFG_BG_BASE, 0x4000586c +.set CYDEV_ANAIF_CFG_BG_SIZE, 0x00000004 +.set CYREG_BG_CR0, 0x4000586c +.set CYREG_BG_RSVD, 0x4000586d +.set CYREG_BG_DFT0, 0x4000586e +.set CYREG_BG_DFT1, 0x4000586f +.set CYDEV_ANAIF_CFG_CAPSL_BASE, 0x40005870 +.set CYDEV_ANAIF_CFG_CAPSL_SIZE, 0x00000002 +.set CYREG_CAPSL_CFG0, 0x40005870 +.set CYREG_CAPSL_CFG1, 0x40005871 +.set CYDEV_ANAIF_CFG_CAPSR_BASE, 0x40005872 +.set CYDEV_ANAIF_CFG_CAPSR_SIZE, 0x00000002 +.set CYREG_CAPSR_CFG0, 0x40005872 +.set CYREG_CAPSR_CFG1, 0x40005873 +.set CYDEV_ANAIF_CFG_PUMP_BASE, 0x40005876 +.set CYDEV_ANAIF_CFG_PUMP_SIZE, 0x00000002 +.set CYREG_PUMP_CR0, 0x40005876 +.set CYREG_PUMP_CR1, 0x40005877 +.set CYDEV_ANAIF_CFG_LPF0_BASE, 0x40005878 +.set CYDEV_ANAIF_CFG_LPF0_SIZE, 0x00000002 +.set CYREG_LPF0_CR0, 0x40005878 +.set CYREG_LPF0_RSVD, 0x40005879 +.set CYDEV_ANAIF_CFG_LPF1_BASE, 0x4000587a +.set CYDEV_ANAIF_CFG_LPF1_SIZE, 0x00000002 +.set CYREG_LPF1_CR0, 0x4000587a +.set CYREG_LPF1_RSVD, 0x4000587b +.set CYDEV_ANAIF_CFG_MISC_BASE, 0x4000587c +.set CYDEV_ANAIF_CFG_MISC_SIZE, 0x00000001 +.set CYREG_ANAIF_CFG_MISC_CR0, 0x4000587c +.set CYDEV_ANAIF_CFG_DSM0_BASE, 0x40005880 +.set CYDEV_ANAIF_CFG_DSM0_SIZE, 0x00000020 +.set CYREG_DSM0_CR0, 0x40005880 +.set CYREG_DSM0_CR1, 0x40005881 +.set CYREG_DSM0_CR2, 0x40005882 +.set CYREG_DSM0_CR3, 0x40005883 +.set CYREG_DSM0_CR4, 0x40005884 +.set CYREG_DSM0_CR5, 0x40005885 +.set CYREG_DSM0_CR6, 0x40005886 +.set CYREG_DSM0_CR7, 0x40005887 +.set CYREG_DSM0_CR8, 0x40005888 +.set CYREG_DSM0_CR9, 0x40005889 +.set CYREG_DSM0_CR10, 0x4000588a +.set CYREG_DSM0_CR11, 0x4000588b +.set CYREG_DSM0_CR12, 0x4000588c +.set CYREG_DSM0_CR13, 0x4000588d +.set CYREG_DSM0_CR14, 0x4000588e +.set CYREG_DSM0_CR15, 0x4000588f +.set CYREG_DSM0_CR16, 0x40005890 +.set CYREG_DSM0_CR17, 0x40005891 +.set CYREG_DSM0_REF0, 0x40005892 +.set CYREG_DSM0_REF1, 0x40005893 +.set CYREG_DSM0_REF2, 0x40005894 +.set CYREG_DSM0_REF3, 0x40005895 +.set CYREG_DSM0_DEM0, 0x40005896 +.set CYREG_DSM0_DEM1, 0x40005897 +.set CYREG_DSM0_TST0, 0x40005898 +.set CYREG_DSM0_TST1, 0x40005899 +.set CYREG_DSM0_BUF0, 0x4000589a +.set CYREG_DSM0_BUF1, 0x4000589b +.set CYREG_DSM0_BUF2, 0x4000589c +.set CYREG_DSM0_BUF3, 0x4000589d +.set CYREG_DSM0_MISC, 0x4000589e +.set CYREG_DSM0_RSVD1, 0x4000589f +.set CYDEV_ANAIF_CFG_SAR0_BASE, 0x40005900 +.set CYDEV_ANAIF_CFG_SAR0_SIZE, 0x00000007 +.set CYREG_SAR0_CSR0, 0x40005900 +.set CYREG_SAR0_CSR1, 0x40005901 +.set CYREG_SAR0_CSR2, 0x40005902 +.set CYREG_SAR0_CSR3, 0x40005903 +.set CYREG_SAR0_CSR4, 0x40005904 +.set CYREG_SAR0_CSR5, 0x40005905 +.set CYREG_SAR0_CSR6, 0x40005906 +.set CYDEV_ANAIF_CFG_SAR1_BASE, 0x40005908 +.set CYDEV_ANAIF_CFG_SAR1_SIZE, 0x00000007 +.set CYREG_SAR1_CSR0, 0x40005908 +.set CYREG_SAR1_CSR1, 0x40005909 +.set CYREG_SAR1_CSR2, 0x4000590a +.set CYREG_SAR1_CSR3, 0x4000590b +.set CYREG_SAR1_CSR4, 0x4000590c +.set CYREG_SAR1_CSR5, 0x4000590d +.set CYREG_SAR1_CSR6, 0x4000590e +.set CYDEV_ANAIF_RT_BASE, 0x40005a00 +.set CYDEV_ANAIF_RT_SIZE, 0x00000162 +.set CYDEV_ANAIF_RT_SC0_BASE, 0x40005a00 +.set CYDEV_ANAIF_RT_SC0_SIZE, 0x0000000d +.set CYREG_SC0_SW0, 0x40005a00 +.set CYREG_SC0_SW2, 0x40005a02 +.set CYREG_SC0_SW3, 0x40005a03 +.set CYREG_SC0_SW4, 0x40005a04 +.set CYREG_SC0_SW6, 0x40005a06 +.set CYREG_SC0_SW7, 0x40005a07 +.set CYREG_SC0_SW8, 0x40005a08 +.set CYREG_SC0_SW10, 0x40005a0a +.set CYREG_SC0_CLK, 0x40005a0b +.set CYREG_SC0_BST, 0x40005a0c +.set CYDEV_ANAIF_RT_SC1_BASE, 0x40005a10 +.set CYDEV_ANAIF_RT_SC1_SIZE, 0x0000000d +.set CYREG_SC1_SW0, 0x40005a10 +.set CYREG_SC1_SW2, 0x40005a12 +.set CYREG_SC1_SW3, 0x40005a13 +.set CYREG_SC1_SW4, 0x40005a14 +.set CYREG_SC1_SW6, 0x40005a16 +.set CYREG_SC1_SW7, 0x40005a17 +.set CYREG_SC1_SW8, 0x40005a18 +.set CYREG_SC1_SW10, 0x40005a1a +.set CYREG_SC1_CLK, 0x40005a1b +.set CYREG_SC1_BST, 0x40005a1c +.set CYDEV_ANAIF_RT_SC2_BASE, 0x40005a20 +.set CYDEV_ANAIF_RT_SC2_SIZE, 0x0000000d +.set CYREG_SC2_SW0, 0x40005a20 +.set CYREG_SC2_SW2, 0x40005a22 +.set CYREG_SC2_SW3, 0x40005a23 +.set CYREG_SC2_SW4, 0x40005a24 +.set CYREG_SC2_SW6, 0x40005a26 +.set CYREG_SC2_SW7, 0x40005a27 +.set CYREG_SC2_SW8, 0x40005a28 +.set CYREG_SC2_SW10, 0x40005a2a +.set CYREG_SC2_CLK, 0x40005a2b +.set CYREG_SC2_BST, 0x40005a2c +.set CYDEV_ANAIF_RT_SC3_BASE, 0x40005a30 +.set CYDEV_ANAIF_RT_SC3_SIZE, 0x0000000d +.set CYREG_SC3_SW0, 0x40005a30 +.set CYREG_SC3_SW2, 0x40005a32 +.set CYREG_SC3_SW3, 0x40005a33 +.set CYREG_SC3_SW4, 0x40005a34 +.set CYREG_SC3_SW6, 0x40005a36 +.set CYREG_SC3_SW7, 0x40005a37 +.set CYREG_SC3_SW8, 0x40005a38 +.set CYREG_SC3_SW10, 0x40005a3a +.set CYREG_SC3_CLK, 0x40005a3b +.set CYREG_SC3_BST, 0x40005a3c +.set CYDEV_ANAIF_RT_DAC0_BASE, 0x40005a80 +.set CYDEV_ANAIF_RT_DAC0_SIZE, 0x00000008 +.set CYREG_DAC0_SW0, 0x40005a80 +.set CYREG_DAC0_SW2, 0x40005a82 +.set CYREG_DAC0_SW3, 0x40005a83 +.set CYREG_DAC0_SW4, 0x40005a84 +.set CYREG_DAC0_STROBE, 0x40005a87 +.set CYDEV_ANAIF_RT_DAC1_BASE, 0x40005a88 +.set CYDEV_ANAIF_RT_DAC1_SIZE, 0x00000008 +.set CYREG_DAC1_SW0, 0x40005a88 +.set CYREG_DAC1_SW2, 0x40005a8a +.set CYREG_DAC1_SW3, 0x40005a8b +.set CYREG_DAC1_SW4, 0x40005a8c +.set CYREG_DAC1_STROBE, 0x40005a8f +.set CYDEV_ANAIF_RT_DAC2_BASE, 0x40005a90 +.set CYDEV_ANAIF_RT_DAC2_SIZE, 0x00000008 +.set CYREG_DAC2_SW0, 0x40005a90 +.set CYREG_DAC2_SW2, 0x40005a92 +.set CYREG_DAC2_SW3, 0x40005a93 +.set CYREG_DAC2_SW4, 0x40005a94 +.set CYREG_DAC2_STROBE, 0x40005a97 +.set CYDEV_ANAIF_RT_DAC3_BASE, 0x40005a98 +.set CYDEV_ANAIF_RT_DAC3_SIZE, 0x00000008 +.set CYREG_DAC3_SW0, 0x40005a98 +.set CYREG_DAC3_SW2, 0x40005a9a +.set CYREG_DAC3_SW3, 0x40005a9b +.set CYREG_DAC3_SW4, 0x40005a9c +.set CYREG_DAC3_STROBE, 0x40005a9f +.set CYDEV_ANAIF_RT_CMP0_BASE, 0x40005ac0 +.set CYDEV_ANAIF_RT_CMP0_SIZE, 0x00000008 +.set CYREG_CMP0_SW0, 0x40005ac0 +.set CYREG_CMP0_SW2, 0x40005ac2 +.set CYREG_CMP0_SW3, 0x40005ac3 +.set CYREG_CMP0_SW4, 0x40005ac4 +.set CYREG_CMP0_SW6, 0x40005ac6 +.set CYREG_CMP0_CLK, 0x40005ac7 +.set CYDEV_ANAIF_RT_CMP1_BASE, 0x40005ac8 +.set CYDEV_ANAIF_RT_CMP1_SIZE, 0x00000008 +.set CYREG_CMP1_SW0, 0x40005ac8 +.set CYREG_CMP1_SW2, 0x40005aca +.set CYREG_CMP1_SW3, 0x40005acb +.set CYREG_CMP1_SW4, 0x40005acc +.set CYREG_CMP1_SW6, 0x40005ace +.set CYREG_CMP1_CLK, 0x40005acf +.set CYDEV_ANAIF_RT_CMP2_BASE, 0x40005ad0 +.set CYDEV_ANAIF_RT_CMP2_SIZE, 0x00000008 +.set CYREG_CMP2_SW0, 0x40005ad0 +.set CYREG_CMP2_SW2, 0x40005ad2 +.set CYREG_CMP2_SW3, 0x40005ad3 +.set CYREG_CMP2_SW4, 0x40005ad4 +.set CYREG_CMP2_SW6, 0x40005ad6 +.set CYREG_CMP2_CLK, 0x40005ad7 +.set CYDEV_ANAIF_RT_CMP3_BASE, 0x40005ad8 +.set CYDEV_ANAIF_RT_CMP3_SIZE, 0x00000008 +.set CYREG_CMP3_SW0, 0x40005ad8 +.set CYREG_CMP3_SW2, 0x40005ada +.set CYREG_CMP3_SW3, 0x40005adb +.set CYREG_CMP3_SW4, 0x40005adc +.set CYREG_CMP3_SW6, 0x40005ade +.set CYREG_CMP3_CLK, 0x40005adf +.set CYDEV_ANAIF_RT_DSM0_BASE, 0x40005b00 +.set CYDEV_ANAIF_RT_DSM0_SIZE, 0x00000008 +.set CYREG_DSM0_SW0, 0x40005b00 +.set CYREG_DSM0_SW2, 0x40005b02 +.set CYREG_DSM0_SW3, 0x40005b03 +.set CYREG_DSM0_SW4, 0x40005b04 +.set CYREG_DSM0_SW6, 0x40005b06 +.set CYREG_DSM0_CLK, 0x40005b07 +.set CYDEV_ANAIF_RT_SAR0_BASE, 0x40005b20 +.set CYDEV_ANAIF_RT_SAR0_SIZE, 0x00000008 +.set CYREG_SAR0_SW0, 0x40005b20 +.set CYREG_SAR0_SW2, 0x40005b22 +.set CYREG_SAR0_SW3, 0x40005b23 +.set CYREG_SAR0_SW4, 0x40005b24 +.set CYREG_SAR0_SW6, 0x40005b26 +.set CYREG_SAR0_CLK, 0x40005b27 +.set CYDEV_ANAIF_RT_SAR1_BASE, 0x40005b28 +.set CYDEV_ANAIF_RT_SAR1_SIZE, 0x00000008 +.set CYREG_SAR1_SW0, 0x40005b28 +.set CYREG_SAR1_SW2, 0x40005b2a +.set CYREG_SAR1_SW3, 0x40005b2b +.set CYREG_SAR1_SW4, 0x40005b2c +.set CYREG_SAR1_SW6, 0x40005b2e +.set CYREG_SAR1_CLK, 0x40005b2f +.set CYDEV_ANAIF_RT_OPAMP0_BASE, 0x40005b40 +.set CYDEV_ANAIF_RT_OPAMP0_SIZE, 0x00000002 +.set CYREG_OPAMP0_MX, 0x40005b40 +.set CYREG_OPAMP0_SW, 0x40005b41 +.set CYDEV_ANAIF_RT_OPAMP1_BASE, 0x40005b42 +.set CYDEV_ANAIF_RT_OPAMP1_SIZE, 0x00000002 +.set CYREG_OPAMP1_MX, 0x40005b42 +.set CYREG_OPAMP1_SW, 0x40005b43 +.set CYDEV_ANAIF_RT_OPAMP2_BASE, 0x40005b44 +.set CYDEV_ANAIF_RT_OPAMP2_SIZE, 0x00000002 +.set CYREG_OPAMP2_MX, 0x40005b44 +.set CYREG_OPAMP2_SW, 0x40005b45 +.set CYDEV_ANAIF_RT_OPAMP3_BASE, 0x40005b46 +.set CYDEV_ANAIF_RT_OPAMP3_SIZE, 0x00000002 +.set CYREG_OPAMP3_MX, 0x40005b46 +.set CYREG_OPAMP3_SW, 0x40005b47 +.set CYDEV_ANAIF_RT_LCDDAC_BASE, 0x40005b50 +.set CYDEV_ANAIF_RT_LCDDAC_SIZE, 0x00000005 +.set CYREG_LCDDAC_SW0, 0x40005b50 +.set CYREG_LCDDAC_SW1, 0x40005b51 +.set CYREG_LCDDAC_SW2, 0x40005b52 +.set CYREG_LCDDAC_SW3, 0x40005b53 +.set CYREG_LCDDAC_SW4, 0x40005b54 +.set CYDEV_ANAIF_RT_SC_BASE, 0x40005b56 +.set CYDEV_ANAIF_RT_SC_SIZE, 0x00000001 +.set CYREG_SC_MISC, 0x40005b56 +.set CYDEV_ANAIF_RT_BUS_BASE, 0x40005b58 +.set CYDEV_ANAIF_RT_BUS_SIZE, 0x00000004 +.set CYREG_BUS_SW0, 0x40005b58 +.set CYREG_BUS_SW2, 0x40005b5a +.set CYREG_BUS_SW3, 0x40005b5b +.set CYDEV_ANAIF_RT_DFT_BASE, 0x40005b5c +.set CYDEV_ANAIF_RT_DFT_SIZE, 0x00000006 +.set CYREG_DFT_CR0, 0x40005b5c +.set CYREG_DFT_CR1, 0x40005b5d +.set CYREG_DFT_CR2, 0x40005b5e +.set CYREG_DFT_CR3, 0x40005b5f +.set CYREG_DFT_CR4, 0x40005b60 +.set CYREG_DFT_CR5, 0x40005b61 +.set CYDEV_ANAIF_WRK_BASE, 0x40005b80 +.set CYDEV_ANAIF_WRK_SIZE, 0x00000029 +.set CYDEV_ANAIF_WRK_DAC0_BASE, 0x40005b80 +.set CYDEV_ANAIF_WRK_DAC0_SIZE, 0x00000001 +.set CYREG_DAC0_D, 0x40005b80 +.set CYDEV_ANAIF_WRK_DAC1_BASE, 0x40005b81 +.set CYDEV_ANAIF_WRK_DAC1_SIZE, 0x00000001 +.set CYREG_DAC1_D, 0x40005b81 +.set CYDEV_ANAIF_WRK_DAC2_BASE, 0x40005b82 +.set CYDEV_ANAIF_WRK_DAC2_SIZE, 0x00000001 +.set CYREG_DAC2_D, 0x40005b82 +.set CYDEV_ANAIF_WRK_DAC3_BASE, 0x40005b83 +.set CYDEV_ANAIF_WRK_DAC3_SIZE, 0x00000001 +.set CYREG_DAC3_D, 0x40005b83 +.set CYDEV_ANAIF_WRK_DSM0_BASE, 0x40005b88 +.set CYDEV_ANAIF_WRK_DSM0_SIZE, 0x00000002 +.set CYREG_DSM0_OUT0, 0x40005b88 +.set CYREG_DSM0_OUT1, 0x40005b89 +.set CYDEV_ANAIF_WRK_LUT_BASE, 0x40005b90 +.set CYDEV_ANAIF_WRK_LUT_SIZE, 0x00000005 +.set CYREG_LUT_SR, 0x40005b90 +.set CYREG_LUT_WRK1, 0x40005b91 +.set CYREG_LUT_MSK, 0x40005b92 +.set CYREG_LUT_CLK, 0x40005b93 +.set CYREG_LUT_CPTR, 0x40005b94 +.set CYDEV_ANAIF_WRK_CMP_BASE, 0x40005b96 +.set CYDEV_ANAIF_WRK_CMP_SIZE, 0x00000002 +.set CYREG_CMP_WRK, 0x40005b96 +.set CYREG_CMP_TST, 0x40005b97 +.set CYDEV_ANAIF_WRK_SC_BASE, 0x40005b98 +.set CYDEV_ANAIF_WRK_SC_SIZE, 0x00000005 +.set CYREG_SC_SR, 0x40005b98 +.set CYREG_SC_WRK1, 0x40005b99 +.set CYREG_SC_MSK, 0x40005b9a +.set CYREG_SC_CMPINV, 0x40005b9b +.set CYREG_SC_CPTR, 0x40005b9c +.set CYDEV_ANAIF_WRK_SAR0_BASE, 0x40005ba0 +.set CYDEV_ANAIF_WRK_SAR0_SIZE, 0x00000002 +.set CYREG_SAR0_WRK0, 0x40005ba0 +.set CYREG_SAR0_WRK1, 0x40005ba1 +.set CYDEV_ANAIF_WRK_SAR1_BASE, 0x40005ba2 +.set CYDEV_ANAIF_WRK_SAR1_SIZE, 0x00000002 +.set CYREG_SAR1_WRK0, 0x40005ba2 +.set CYREG_SAR1_WRK1, 0x40005ba3 +.set CYDEV_ANAIF_WRK_SARS_BASE, 0x40005ba8 +.set CYDEV_ANAIF_WRK_SARS_SIZE, 0x00000001 +.set CYREG_ANAIF_WRK_SARS_SOF, 0x40005ba8 +.set CYDEV_USB_BASE, 0x40006000 +.set CYDEV_USB_SIZE, 0x00000300 +.set CYREG_USB_EP0_DR0, 0x40006000 +.set CYREG_USB_EP0_DR1, 0x40006001 +.set CYREG_USB_EP0_DR2, 0x40006002 +.set CYREG_USB_EP0_DR3, 0x40006003 +.set CYREG_USB_EP0_DR4, 0x40006004 +.set CYREG_USB_EP0_DR5, 0x40006005 +.set CYREG_USB_EP0_DR6, 0x40006006 +.set CYREG_USB_EP0_DR7, 0x40006007 +.set CYREG_USB_CR0, 0x40006008 +.set CYREG_USB_CR1, 0x40006009 +.set CYREG_USB_SIE_EP_INT_EN, 0x4000600a +.set CYREG_USB_SIE_EP_INT_SR, 0x4000600b +.set CYDEV_USB_SIE_EP1_BASE, 0x4000600c +.set CYDEV_USB_SIE_EP1_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP1_CNT0, 0x4000600c +.set CYREG_USB_SIE_EP1_CNT1, 0x4000600d +.set CYREG_USB_SIE_EP1_CR0, 0x4000600e +.set CYREG_USB_USBIO_CR0, 0x40006010 +.set CYREG_USB_USBIO_CR1, 0x40006012 +.set CYREG_USB_DYN_RECONFIG, 0x40006014 +.set CYREG_USB_SOF0, 0x40006018 +.set CYREG_USB_SOF1, 0x40006019 +.set CYDEV_USB_SIE_EP2_BASE, 0x4000601c +.set CYDEV_USB_SIE_EP2_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP2_CNT0, 0x4000601c +.set CYREG_USB_SIE_EP2_CNT1, 0x4000601d +.set CYREG_USB_SIE_EP2_CR0, 0x4000601e +.set CYREG_USB_EP0_CR, 0x40006028 +.set CYREG_USB_EP0_CNT, 0x40006029 +.set CYDEV_USB_SIE_EP3_BASE, 0x4000602c +.set CYDEV_USB_SIE_EP3_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP3_CNT0, 0x4000602c +.set CYREG_USB_SIE_EP3_CNT1, 0x4000602d +.set CYREG_USB_SIE_EP3_CR0, 0x4000602e +.set CYDEV_USB_SIE_EP4_BASE, 0x4000603c +.set CYDEV_USB_SIE_EP4_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP4_CNT0, 0x4000603c +.set CYREG_USB_SIE_EP4_CNT1, 0x4000603d +.set CYREG_USB_SIE_EP4_CR0, 0x4000603e +.set CYDEV_USB_SIE_EP5_BASE, 0x4000604c +.set CYDEV_USB_SIE_EP5_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP5_CNT0, 0x4000604c +.set CYREG_USB_SIE_EP5_CNT1, 0x4000604d +.set CYREG_USB_SIE_EP5_CR0, 0x4000604e +.set CYDEV_USB_SIE_EP6_BASE, 0x4000605c +.set CYDEV_USB_SIE_EP6_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP6_CNT0, 0x4000605c +.set CYREG_USB_SIE_EP6_CNT1, 0x4000605d +.set CYREG_USB_SIE_EP6_CR0, 0x4000605e +.set CYDEV_USB_SIE_EP7_BASE, 0x4000606c +.set CYDEV_USB_SIE_EP7_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP7_CNT0, 0x4000606c +.set CYREG_USB_SIE_EP7_CNT1, 0x4000606d +.set CYREG_USB_SIE_EP7_CR0, 0x4000606e +.set CYDEV_USB_SIE_EP8_BASE, 0x4000607c +.set CYDEV_USB_SIE_EP8_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP8_CNT0, 0x4000607c +.set CYREG_USB_SIE_EP8_CNT1, 0x4000607d +.set CYREG_USB_SIE_EP8_CR0, 0x4000607e +.set CYDEV_USB_ARB_EP1_BASE, 0x40006080 +.set CYDEV_USB_ARB_EP1_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP1_CFG, 0x40006080 +.set CYREG_USB_ARB_EP1_INT_EN, 0x40006081 +.set CYREG_USB_ARB_EP1_SR, 0x40006082 +.set CYDEV_USB_ARB_RW1_BASE, 0x40006084 +.set CYDEV_USB_ARB_RW1_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW1_WA, 0x40006084 +.set CYREG_USB_ARB_RW1_WA_MSB, 0x40006085 +.set CYREG_USB_ARB_RW1_RA, 0x40006086 +.set CYREG_USB_ARB_RW1_RA_MSB, 0x40006087 +.set CYREG_USB_ARB_RW1_DR, 0x40006088 +.set CYREG_USB_BUF_SIZE, 0x4000608c +.set CYREG_USB_EP_ACTIVE, 0x4000608e +.set CYREG_USB_EP_TYPE, 0x4000608f +.set CYDEV_USB_ARB_EP2_BASE, 0x40006090 +.set CYDEV_USB_ARB_EP2_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP2_CFG, 0x40006090 +.set CYREG_USB_ARB_EP2_INT_EN, 0x40006091 +.set CYREG_USB_ARB_EP2_SR, 0x40006092 +.set CYDEV_USB_ARB_RW2_BASE, 0x40006094 +.set CYDEV_USB_ARB_RW2_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW2_WA, 0x40006094 +.set CYREG_USB_ARB_RW2_WA_MSB, 0x40006095 +.set CYREG_USB_ARB_RW2_RA, 0x40006096 +.set CYREG_USB_ARB_RW2_RA_MSB, 0x40006097 +.set CYREG_USB_ARB_RW2_DR, 0x40006098 +.set CYREG_USB_ARB_CFG, 0x4000609c +.set CYREG_USB_USB_CLK_EN, 0x4000609d +.set CYREG_USB_ARB_INT_EN, 0x4000609e +.set CYREG_USB_ARB_INT_SR, 0x4000609f +.set CYDEV_USB_ARB_EP3_BASE, 0x400060a0 +.set CYDEV_USB_ARB_EP3_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP3_CFG, 0x400060a0 +.set CYREG_USB_ARB_EP3_INT_EN, 0x400060a1 +.set CYREG_USB_ARB_EP3_SR, 0x400060a2 +.set CYDEV_USB_ARB_RW3_BASE, 0x400060a4 +.set CYDEV_USB_ARB_RW3_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW3_WA, 0x400060a4 +.set CYREG_USB_ARB_RW3_WA_MSB, 0x400060a5 +.set CYREG_USB_ARB_RW3_RA, 0x400060a6 +.set CYREG_USB_ARB_RW3_RA_MSB, 0x400060a7 +.set CYREG_USB_ARB_RW3_DR, 0x400060a8 +.set CYREG_USB_CWA, 0x400060ac +.set CYREG_USB_CWA_MSB, 0x400060ad +.set CYDEV_USB_ARB_EP4_BASE, 0x400060b0 +.set CYDEV_USB_ARB_EP4_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP4_CFG, 0x400060b0 +.set CYREG_USB_ARB_EP4_INT_EN, 0x400060b1 +.set CYREG_USB_ARB_EP4_SR, 0x400060b2 +.set CYDEV_USB_ARB_RW4_BASE, 0x400060b4 +.set CYDEV_USB_ARB_RW4_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW4_WA, 0x400060b4 +.set CYREG_USB_ARB_RW4_WA_MSB, 0x400060b5 +.set CYREG_USB_ARB_RW4_RA, 0x400060b6 +.set CYREG_USB_ARB_RW4_RA_MSB, 0x400060b7 +.set CYREG_USB_ARB_RW4_DR, 0x400060b8 +.set CYREG_USB_DMA_THRES, 0x400060bc +.set CYREG_USB_DMA_THRES_MSB, 0x400060bd +.set CYDEV_USB_ARB_EP5_BASE, 0x400060c0 +.set CYDEV_USB_ARB_EP5_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP5_CFG, 0x400060c0 +.set CYREG_USB_ARB_EP5_INT_EN, 0x400060c1 +.set CYREG_USB_ARB_EP5_SR, 0x400060c2 +.set CYDEV_USB_ARB_RW5_BASE, 0x400060c4 +.set CYDEV_USB_ARB_RW5_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW5_WA, 0x400060c4 +.set CYREG_USB_ARB_RW5_WA_MSB, 0x400060c5 +.set CYREG_USB_ARB_RW5_RA, 0x400060c6 +.set CYREG_USB_ARB_RW5_RA_MSB, 0x400060c7 +.set CYREG_USB_ARB_RW5_DR, 0x400060c8 +.set CYREG_USB_BUS_RST_CNT, 0x400060cc +.set CYDEV_USB_ARB_EP6_BASE, 0x400060d0 +.set CYDEV_USB_ARB_EP6_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP6_CFG, 0x400060d0 +.set CYREG_USB_ARB_EP6_INT_EN, 0x400060d1 +.set CYREG_USB_ARB_EP6_SR, 0x400060d2 +.set CYDEV_USB_ARB_RW6_BASE, 0x400060d4 +.set CYDEV_USB_ARB_RW6_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW6_WA, 0x400060d4 +.set CYREG_USB_ARB_RW6_WA_MSB, 0x400060d5 +.set CYREG_USB_ARB_RW6_RA, 0x400060d6 +.set CYREG_USB_ARB_RW6_RA_MSB, 0x400060d7 +.set CYREG_USB_ARB_RW6_DR, 0x400060d8 +.set CYDEV_USB_ARB_EP7_BASE, 0x400060e0 +.set CYDEV_USB_ARB_EP7_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP7_CFG, 0x400060e0 +.set CYREG_USB_ARB_EP7_INT_EN, 0x400060e1 +.set CYREG_USB_ARB_EP7_SR, 0x400060e2 +.set CYDEV_USB_ARB_RW7_BASE, 0x400060e4 +.set CYDEV_USB_ARB_RW7_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW7_WA, 0x400060e4 +.set CYREG_USB_ARB_RW7_WA_MSB, 0x400060e5 +.set CYREG_USB_ARB_RW7_RA, 0x400060e6 +.set CYREG_USB_ARB_RW7_RA_MSB, 0x400060e7 +.set CYREG_USB_ARB_RW7_DR, 0x400060e8 +.set CYDEV_USB_ARB_EP8_BASE, 0x400060f0 +.set CYDEV_USB_ARB_EP8_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP8_CFG, 0x400060f0 +.set CYREG_USB_ARB_EP8_INT_EN, 0x400060f1 +.set CYREG_USB_ARB_EP8_SR, 0x400060f2 +.set CYDEV_USB_ARB_RW8_BASE, 0x400060f4 +.set CYDEV_USB_ARB_RW8_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW8_WA, 0x400060f4 +.set CYREG_USB_ARB_RW8_WA_MSB, 0x400060f5 +.set CYREG_USB_ARB_RW8_RA, 0x400060f6 +.set CYREG_USB_ARB_RW8_RA_MSB, 0x400060f7 +.set CYREG_USB_ARB_RW8_DR, 0x400060f8 +.set CYDEV_USB_MEM_BASE, 0x40006100 +.set CYDEV_USB_MEM_SIZE, 0x00000200 +.set CYREG_USB_MEM_DATA_MBASE, 0x40006100 +.set CYREG_USB_MEM_DATA_MSIZE, 0x00000200 +.set CYDEV_UWRK_BASE, 0x40006400 +.set CYDEV_UWRK_SIZE, 0x00000b60 +.set CYDEV_UWRK_UWRK8_BASE, 0x40006400 +.set CYDEV_UWRK_UWRK8_SIZE, 0x000003b0 +.set CYDEV_UWRK_UWRK8_B0_BASE, 0x40006400 +.set CYDEV_UWRK_UWRK8_B0_SIZE, 0x000000b0 +.set CYREG_B0_UDB00_A0, 0x40006400 +.set CYREG_B0_UDB01_A0, 0x40006401 +.set CYREG_B0_UDB02_A0, 0x40006402 +.set CYREG_B0_UDB03_A0, 0x40006403 +.set CYREG_B0_UDB04_A0, 0x40006404 +.set CYREG_B0_UDB05_A0, 0x40006405 +.set CYREG_B0_UDB06_A0, 0x40006406 +.set CYREG_B0_UDB07_A0, 0x40006407 +.set CYREG_B0_UDB08_A0, 0x40006408 +.set CYREG_B0_UDB09_A0, 0x40006409 +.set CYREG_B0_UDB10_A0, 0x4000640a +.set CYREG_B0_UDB11_A0, 0x4000640b +.set CYREG_B0_UDB12_A0, 0x4000640c +.set CYREG_B0_UDB13_A0, 0x4000640d +.set CYREG_B0_UDB14_A0, 0x4000640e +.set CYREG_B0_UDB15_A0, 0x4000640f +.set CYREG_B0_UDB00_A1, 0x40006410 +.set CYREG_B0_UDB01_A1, 0x40006411 +.set CYREG_B0_UDB02_A1, 0x40006412 +.set CYREG_B0_UDB03_A1, 0x40006413 +.set CYREG_B0_UDB04_A1, 0x40006414 +.set CYREG_B0_UDB05_A1, 0x40006415 +.set CYREG_B0_UDB06_A1, 0x40006416 +.set CYREG_B0_UDB07_A1, 0x40006417 +.set CYREG_B0_UDB08_A1, 0x40006418 +.set CYREG_B0_UDB09_A1, 0x40006419 +.set CYREG_B0_UDB10_A1, 0x4000641a +.set CYREG_B0_UDB11_A1, 0x4000641b +.set CYREG_B0_UDB12_A1, 0x4000641c +.set CYREG_B0_UDB13_A1, 0x4000641d +.set CYREG_B0_UDB14_A1, 0x4000641e +.set CYREG_B0_UDB15_A1, 0x4000641f +.set CYREG_B0_UDB00_D0, 0x40006420 +.set CYREG_B0_UDB01_D0, 0x40006421 +.set CYREG_B0_UDB02_D0, 0x40006422 +.set CYREG_B0_UDB03_D0, 0x40006423 +.set CYREG_B0_UDB04_D0, 0x40006424 +.set CYREG_B0_UDB05_D0, 0x40006425 +.set CYREG_B0_UDB06_D0, 0x40006426 +.set CYREG_B0_UDB07_D0, 0x40006427 +.set CYREG_B0_UDB08_D0, 0x40006428 +.set CYREG_B0_UDB09_D0, 0x40006429 +.set CYREG_B0_UDB10_D0, 0x4000642a +.set CYREG_B0_UDB11_D0, 0x4000642b +.set CYREG_B0_UDB12_D0, 0x4000642c +.set CYREG_B0_UDB13_D0, 0x4000642d +.set CYREG_B0_UDB14_D0, 0x4000642e +.set CYREG_B0_UDB15_D0, 0x4000642f +.set CYREG_B0_UDB00_D1, 0x40006430 +.set CYREG_B0_UDB01_D1, 0x40006431 +.set CYREG_B0_UDB02_D1, 0x40006432 +.set CYREG_B0_UDB03_D1, 0x40006433 +.set CYREG_B0_UDB04_D1, 0x40006434 +.set CYREG_B0_UDB05_D1, 0x40006435 +.set CYREG_B0_UDB06_D1, 0x40006436 +.set CYREG_B0_UDB07_D1, 0x40006437 +.set CYREG_B0_UDB08_D1, 0x40006438 +.set CYREG_B0_UDB09_D1, 0x40006439 +.set CYREG_B0_UDB10_D1, 0x4000643a +.set CYREG_B0_UDB11_D1, 0x4000643b +.set CYREG_B0_UDB12_D1, 0x4000643c +.set CYREG_B0_UDB13_D1, 0x4000643d +.set CYREG_B0_UDB14_D1, 0x4000643e +.set CYREG_B0_UDB15_D1, 0x4000643f +.set CYREG_B0_UDB00_F0, 0x40006440 +.set CYREG_B0_UDB01_F0, 0x40006441 +.set CYREG_B0_UDB02_F0, 0x40006442 +.set CYREG_B0_UDB03_F0, 0x40006443 +.set CYREG_B0_UDB04_F0, 0x40006444 +.set CYREG_B0_UDB05_F0, 0x40006445 +.set CYREG_B0_UDB06_F0, 0x40006446 +.set CYREG_B0_UDB07_F0, 0x40006447 +.set CYREG_B0_UDB08_F0, 0x40006448 +.set CYREG_B0_UDB09_F0, 0x40006449 +.set CYREG_B0_UDB10_F0, 0x4000644a +.set CYREG_B0_UDB11_F0, 0x4000644b +.set CYREG_B0_UDB12_F0, 0x4000644c +.set CYREG_B0_UDB13_F0, 0x4000644d +.set CYREG_B0_UDB14_F0, 0x4000644e +.set CYREG_B0_UDB15_F0, 0x4000644f +.set CYREG_B0_UDB00_F1, 0x40006450 +.set CYREG_B0_UDB01_F1, 0x40006451 +.set CYREG_B0_UDB02_F1, 0x40006452 +.set CYREG_B0_UDB03_F1, 0x40006453 +.set CYREG_B0_UDB04_F1, 0x40006454 +.set CYREG_B0_UDB05_F1, 0x40006455 +.set CYREG_B0_UDB06_F1, 0x40006456 +.set CYREG_B0_UDB07_F1, 0x40006457 +.set CYREG_B0_UDB08_F1, 0x40006458 +.set CYREG_B0_UDB09_F1, 0x40006459 +.set CYREG_B0_UDB10_F1, 0x4000645a +.set CYREG_B0_UDB11_F1, 0x4000645b +.set CYREG_B0_UDB12_F1, 0x4000645c +.set CYREG_B0_UDB13_F1, 0x4000645d +.set CYREG_B0_UDB14_F1, 0x4000645e +.set CYREG_B0_UDB15_F1, 0x4000645f +.set CYREG_B0_UDB00_ST, 0x40006460 +.set CYREG_B0_UDB01_ST, 0x40006461 +.set CYREG_B0_UDB02_ST, 0x40006462 +.set CYREG_B0_UDB03_ST, 0x40006463 +.set CYREG_B0_UDB04_ST, 0x40006464 +.set CYREG_B0_UDB05_ST, 0x40006465 +.set CYREG_B0_UDB06_ST, 0x40006466 +.set CYREG_B0_UDB07_ST, 0x40006467 +.set CYREG_B0_UDB08_ST, 0x40006468 +.set CYREG_B0_UDB09_ST, 0x40006469 +.set CYREG_B0_UDB10_ST, 0x4000646a +.set CYREG_B0_UDB11_ST, 0x4000646b +.set CYREG_B0_UDB12_ST, 0x4000646c +.set CYREG_B0_UDB13_ST, 0x4000646d +.set CYREG_B0_UDB14_ST, 0x4000646e +.set CYREG_B0_UDB15_ST, 0x4000646f +.set CYREG_B0_UDB00_CTL, 0x40006470 +.set CYREG_B0_UDB01_CTL, 0x40006471 +.set CYREG_B0_UDB02_CTL, 0x40006472 +.set CYREG_B0_UDB03_CTL, 0x40006473 +.set CYREG_B0_UDB04_CTL, 0x40006474 +.set CYREG_B0_UDB05_CTL, 0x40006475 +.set CYREG_B0_UDB06_CTL, 0x40006476 +.set CYREG_B0_UDB07_CTL, 0x40006477 +.set CYREG_B0_UDB08_CTL, 0x40006478 +.set CYREG_B0_UDB09_CTL, 0x40006479 +.set CYREG_B0_UDB10_CTL, 0x4000647a +.set CYREG_B0_UDB11_CTL, 0x4000647b +.set CYREG_B0_UDB12_CTL, 0x4000647c +.set CYREG_B0_UDB13_CTL, 0x4000647d +.set CYREG_B0_UDB14_CTL, 0x4000647e +.set CYREG_B0_UDB15_CTL, 0x4000647f +.set CYREG_B0_UDB00_MSK, 0x40006480 +.set CYREG_B0_UDB01_MSK, 0x40006481 +.set CYREG_B0_UDB02_MSK, 0x40006482 +.set CYREG_B0_UDB03_MSK, 0x40006483 +.set CYREG_B0_UDB04_MSK, 0x40006484 +.set CYREG_B0_UDB05_MSK, 0x40006485 +.set CYREG_B0_UDB06_MSK, 0x40006486 +.set CYREG_B0_UDB07_MSK, 0x40006487 +.set CYREG_B0_UDB08_MSK, 0x40006488 +.set CYREG_B0_UDB09_MSK, 0x40006489 +.set CYREG_B0_UDB10_MSK, 0x4000648a +.set CYREG_B0_UDB11_MSK, 0x4000648b +.set CYREG_B0_UDB12_MSK, 0x4000648c +.set CYREG_B0_UDB13_MSK, 0x4000648d +.set CYREG_B0_UDB14_MSK, 0x4000648e +.set CYREG_B0_UDB15_MSK, 0x4000648f +.set CYREG_B0_UDB00_ACTL, 0x40006490 +.set CYREG_B0_UDB01_ACTL, 0x40006491 +.set CYREG_B0_UDB02_ACTL, 0x40006492 +.set CYREG_B0_UDB03_ACTL, 0x40006493 +.set CYREG_B0_UDB04_ACTL, 0x40006494 +.set CYREG_B0_UDB05_ACTL, 0x40006495 +.set CYREG_B0_UDB06_ACTL, 0x40006496 +.set CYREG_B0_UDB07_ACTL, 0x40006497 +.set CYREG_B0_UDB08_ACTL, 0x40006498 +.set CYREG_B0_UDB09_ACTL, 0x40006499 +.set CYREG_B0_UDB10_ACTL, 0x4000649a +.set CYREG_B0_UDB11_ACTL, 0x4000649b +.set CYREG_B0_UDB12_ACTL, 0x4000649c +.set CYREG_B0_UDB13_ACTL, 0x4000649d +.set CYREG_B0_UDB14_ACTL, 0x4000649e +.set CYREG_B0_UDB15_ACTL, 0x4000649f +.set CYREG_B0_UDB00_MC, 0x400064a0 +.set CYREG_B0_UDB01_MC, 0x400064a1 +.set CYREG_B0_UDB02_MC, 0x400064a2 +.set CYREG_B0_UDB03_MC, 0x400064a3 +.set CYREG_B0_UDB04_MC, 0x400064a4 +.set CYREG_B0_UDB05_MC, 0x400064a5 +.set CYREG_B0_UDB06_MC, 0x400064a6 +.set CYREG_B0_UDB07_MC, 0x400064a7 +.set CYREG_B0_UDB08_MC, 0x400064a8 +.set CYREG_B0_UDB09_MC, 0x400064a9 +.set CYREG_B0_UDB10_MC, 0x400064aa +.set CYREG_B0_UDB11_MC, 0x400064ab +.set CYREG_B0_UDB12_MC, 0x400064ac +.set CYREG_B0_UDB13_MC, 0x400064ad +.set CYREG_B0_UDB14_MC, 0x400064ae +.set CYREG_B0_UDB15_MC, 0x400064af +.set CYDEV_UWRK_UWRK8_B1_BASE, 0x40006500 +.set CYDEV_UWRK_UWRK8_B1_SIZE, 0x000000b0 +.set CYREG_B1_UDB04_A0, 0x40006504 +.set CYREG_B1_UDB05_A0, 0x40006505 +.set CYREG_B1_UDB06_A0, 0x40006506 +.set CYREG_B1_UDB07_A0, 0x40006507 +.set CYREG_B1_UDB08_A0, 0x40006508 +.set CYREG_B1_UDB09_A0, 0x40006509 +.set CYREG_B1_UDB10_A0, 0x4000650a +.set CYREG_B1_UDB11_A0, 0x4000650b +.set CYREG_B1_UDB04_A1, 0x40006514 +.set CYREG_B1_UDB05_A1, 0x40006515 +.set CYREG_B1_UDB06_A1, 0x40006516 +.set CYREG_B1_UDB07_A1, 0x40006517 +.set CYREG_B1_UDB08_A1, 0x40006518 +.set CYREG_B1_UDB09_A1, 0x40006519 +.set CYREG_B1_UDB10_A1, 0x4000651a +.set CYREG_B1_UDB11_A1, 0x4000651b +.set CYREG_B1_UDB04_D0, 0x40006524 +.set CYREG_B1_UDB05_D0, 0x40006525 +.set CYREG_B1_UDB06_D0, 0x40006526 +.set CYREG_B1_UDB07_D0, 0x40006527 +.set CYREG_B1_UDB08_D0, 0x40006528 +.set CYREG_B1_UDB09_D0, 0x40006529 +.set CYREG_B1_UDB10_D0, 0x4000652a +.set CYREG_B1_UDB11_D0, 0x4000652b +.set CYREG_B1_UDB04_D1, 0x40006534 +.set CYREG_B1_UDB05_D1, 0x40006535 +.set CYREG_B1_UDB06_D1, 0x40006536 +.set CYREG_B1_UDB07_D1, 0x40006537 +.set CYREG_B1_UDB08_D1, 0x40006538 +.set CYREG_B1_UDB09_D1, 0x40006539 +.set CYREG_B1_UDB10_D1, 0x4000653a +.set CYREG_B1_UDB11_D1, 0x4000653b +.set CYREG_B1_UDB04_F0, 0x40006544 +.set CYREG_B1_UDB05_F0, 0x40006545 +.set CYREG_B1_UDB06_F0, 0x40006546 +.set CYREG_B1_UDB07_F0, 0x40006547 +.set CYREG_B1_UDB08_F0, 0x40006548 +.set CYREG_B1_UDB09_F0, 0x40006549 +.set CYREG_B1_UDB10_F0, 0x4000654a +.set CYREG_B1_UDB11_F0, 0x4000654b +.set CYREG_B1_UDB04_F1, 0x40006554 +.set CYREG_B1_UDB05_F1, 0x40006555 +.set CYREG_B1_UDB06_F1, 0x40006556 +.set CYREG_B1_UDB07_F1, 0x40006557 +.set CYREG_B1_UDB08_F1, 0x40006558 +.set CYREG_B1_UDB09_F1, 0x40006559 +.set CYREG_B1_UDB10_F1, 0x4000655a +.set CYREG_B1_UDB11_F1, 0x4000655b +.set CYREG_B1_UDB04_ST, 0x40006564 +.set CYREG_B1_UDB05_ST, 0x40006565 +.set CYREG_B1_UDB06_ST, 0x40006566 +.set CYREG_B1_UDB07_ST, 0x40006567 +.set CYREG_B1_UDB08_ST, 0x40006568 +.set CYREG_B1_UDB09_ST, 0x40006569 +.set CYREG_B1_UDB10_ST, 0x4000656a +.set CYREG_B1_UDB11_ST, 0x4000656b +.set CYREG_B1_UDB04_CTL, 0x40006574 +.set CYREG_B1_UDB05_CTL, 0x40006575 +.set CYREG_B1_UDB06_CTL, 0x40006576 +.set CYREG_B1_UDB07_CTL, 0x40006577 +.set CYREG_B1_UDB08_CTL, 0x40006578 +.set CYREG_B1_UDB09_CTL, 0x40006579 +.set CYREG_B1_UDB10_CTL, 0x4000657a +.set CYREG_B1_UDB11_CTL, 0x4000657b +.set CYREG_B1_UDB04_MSK, 0x40006584 +.set CYREG_B1_UDB05_MSK, 0x40006585 +.set CYREG_B1_UDB06_MSK, 0x40006586 +.set CYREG_B1_UDB07_MSK, 0x40006587 +.set CYREG_B1_UDB08_MSK, 0x40006588 +.set CYREG_B1_UDB09_MSK, 0x40006589 +.set CYREG_B1_UDB10_MSK, 0x4000658a +.set CYREG_B1_UDB11_MSK, 0x4000658b +.set CYREG_B1_UDB04_ACTL, 0x40006594 +.set CYREG_B1_UDB05_ACTL, 0x40006595 +.set CYREG_B1_UDB06_ACTL, 0x40006596 +.set CYREG_B1_UDB07_ACTL, 0x40006597 +.set CYREG_B1_UDB08_ACTL, 0x40006598 +.set CYREG_B1_UDB09_ACTL, 0x40006599 +.set CYREG_B1_UDB10_ACTL, 0x4000659a +.set CYREG_B1_UDB11_ACTL, 0x4000659b +.set CYREG_B1_UDB04_MC, 0x400065a4 +.set CYREG_B1_UDB05_MC, 0x400065a5 +.set CYREG_B1_UDB06_MC, 0x400065a6 +.set CYREG_B1_UDB07_MC, 0x400065a7 +.set CYREG_B1_UDB08_MC, 0x400065a8 +.set CYREG_B1_UDB09_MC, 0x400065a9 +.set CYREG_B1_UDB10_MC, 0x400065aa +.set CYREG_B1_UDB11_MC, 0x400065ab +.set CYDEV_UWRK_UWRK16_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_SIZE, 0x00000760 +.set CYDEV_UWRK_UWRK16_CAT_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_CAT_SIZE, 0x00000760 +.set CYDEV_UWRK_UWRK16_CAT_B0_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_CAT_B0_SIZE, 0x00000160 +.set CYREG_B0_UDB00_A0_A1, 0x40006800 +.set CYREG_B0_UDB01_A0_A1, 0x40006802 +.set CYREG_B0_UDB02_A0_A1, 0x40006804 +.set CYREG_B0_UDB03_A0_A1, 0x40006806 +.set CYREG_B0_UDB04_A0_A1, 0x40006808 +.set CYREG_B0_UDB05_A0_A1, 0x4000680a +.set CYREG_B0_UDB06_A0_A1, 0x4000680c +.set CYREG_B0_UDB07_A0_A1, 0x4000680e +.set CYREG_B0_UDB08_A0_A1, 0x40006810 +.set CYREG_B0_UDB09_A0_A1, 0x40006812 +.set CYREG_B0_UDB10_A0_A1, 0x40006814 +.set CYREG_B0_UDB11_A0_A1, 0x40006816 +.set CYREG_B0_UDB12_A0_A1, 0x40006818 +.set CYREG_B0_UDB13_A0_A1, 0x4000681a +.set CYREG_B0_UDB14_A0_A1, 0x4000681c +.set CYREG_B0_UDB15_A0_A1, 0x4000681e +.set CYREG_B0_UDB00_D0_D1, 0x40006840 +.set CYREG_B0_UDB01_D0_D1, 0x40006842 +.set CYREG_B0_UDB02_D0_D1, 0x40006844 +.set CYREG_B0_UDB03_D0_D1, 0x40006846 +.set CYREG_B0_UDB04_D0_D1, 0x40006848 +.set CYREG_B0_UDB05_D0_D1, 0x4000684a +.set CYREG_B0_UDB06_D0_D1, 0x4000684c +.set CYREG_B0_UDB07_D0_D1, 0x4000684e +.set CYREG_B0_UDB08_D0_D1, 0x40006850 +.set CYREG_B0_UDB09_D0_D1, 0x40006852 +.set CYREG_B0_UDB10_D0_D1, 0x40006854 +.set CYREG_B0_UDB11_D0_D1, 0x40006856 +.set CYREG_B0_UDB12_D0_D1, 0x40006858 +.set CYREG_B0_UDB13_D0_D1, 0x4000685a +.set CYREG_B0_UDB14_D0_D1, 0x4000685c +.set CYREG_B0_UDB15_D0_D1, 0x4000685e +.set CYREG_B0_UDB00_F0_F1, 0x40006880 +.set CYREG_B0_UDB01_F0_F1, 0x40006882 +.set CYREG_B0_UDB02_F0_F1, 0x40006884 +.set CYREG_B0_UDB03_F0_F1, 0x40006886 +.set CYREG_B0_UDB04_F0_F1, 0x40006888 +.set CYREG_B0_UDB05_F0_F1, 0x4000688a +.set CYREG_B0_UDB06_F0_F1, 0x4000688c +.set CYREG_B0_UDB07_F0_F1, 0x4000688e +.set CYREG_B0_UDB08_F0_F1, 0x40006890 +.set CYREG_B0_UDB09_F0_F1, 0x40006892 +.set CYREG_B0_UDB10_F0_F1, 0x40006894 +.set CYREG_B0_UDB11_F0_F1, 0x40006896 +.set CYREG_B0_UDB12_F0_F1, 0x40006898 +.set CYREG_B0_UDB13_F0_F1, 0x4000689a +.set CYREG_B0_UDB14_F0_F1, 0x4000689c +.set CYREG_B0_UDB15_F0_F1, 0x4000689e +.set CYREG_B0_UDB00_ST_CTL, 0x400068c0 +.set CYREG_B0_UDB01_ST_CTL, 0x400068c2 +.set CYREG_B0_UDB02_ST_CTL, 0x400068c4 +.set CYREG_B0_UDB03_ST_CTL, 0x400068c6 +.set CYREG_B0_UDB04_ST_CTL, 0x400068c8 +.set CYREG_B0_UDB05_ST_CTL, 0x400068ca +.set CYREG_B0_UDB06_ST_CTL, 0x400068cc +.set CYREG_B0_UDB07_ST_CTL, 0x400068ce +.set CYREG_B0_UDB08_ST_CTL, 0x400068d0 +.set CYREG_B0_UDB09_ST_CTL, 0x400068d2 +.set CYREG_B0_UDB10_ST_CTL, 0x400068d4 +.set CYREG_B0_UDB11_ST_CTL, 0x400068d6 +.set CYREG_B0_UDB12_ST_CTL, 0x400068d8 +.set CYREG_B0_UDB13_ST_CTL, 0x400068da +.set CYREG_B0_UDB14_ST_CTL, 0x400068dc +.set CYREG_B0_UDB15_ST_CTL, 0x400068de +.set CYREG_B0_UDB00_MSK_ACTL, 0x40006900 +.set CYREG_B0_UDB01_MSK_ACTL, 0x40006902 +.set CYREG_B0_UDB02_MSK_ACTL, 0x40006904 +.set CYREG_B0_UDB03_MSK_ACTL, 0x40006906 +.set CYREG_B0_UDB04_MSK_ACTL, 0x40006908 +.set CYREG_B0_UDB05_MSK_ACTL, 0x4000690a +.set CYREG_B0_UDB06_MSK_ACTL, 0x4000690c +.set CYREG_B0_UDB07_MSK_ACTL, 0x4000690e +.set CYREG_B0_UDB08_MSK_ACTL, 0x40006910 +.set CYREG_B0_UDB09_MSK_ACTL, 0x40006912 +.set CYREG_B0_UDB10_MSK_ACTL, 0x40006914 +.set CYREG_B0_UDB11_MSK_ACTL, 0x40006916 +.set CYREG_B0_UDB12_MSK_ACTL, 0x40006918 +.set CYREG_B0_UDB13_MSK_ACTL, 0x4000691a +.set CYREG_B0_UDB14_MSK_ACTL, 0x4000691c +.set CYREG_B0_UDB15_MSK_ACTL, 0x4000691e +.set CYREG_B0_UDB00_MC_00, 0x40006940 +.set CYREG_B0_UDB01_MC_00, 0x40006942 +.set CYREG_B0_UDB02_MC_00, 0x40006944 +.set CYREG_B0_UDB03_MC_00, 0x40006946 +.set CYREG_B0_UDB04_MC_00, 0x40006948 +.set CYREG_B0_UDB05_MC_00, 0x4000694a +.set CYREG_B0_UDB06_MC_00, 0x4000694c +.set CYREG_B0_UDB07_MC_00, 0x4000694e +.set CYREG_B0_UDB08_MC_00, 0x40006950 +.set CYREG_B0_UDB09_MC_00, 0x40006952 +.set CYREG_B0_UDB10_MC_00, 0x40006954 +.set CYREG_B0_UDB11_MC_00, 0x40006956 +.set CYREG_B0_UDB12_MC_00, 0x40006958 +.set CYREG_B0_UDB13_MC_00, 0x4000695a +.set CYREG_B0_UDB14_MC_00, 0x4000695c +.set CYREG_B0_UDB15_MC_00, 0x4000695e +.set CYDEV_UWRK_UWRK16_CAT_B1_BASE, 0x40006a00 +.set CYDEV_UWRK_UWRK16_CAT_B1_SIZE, 0x00000160 +.set CYREG_B1_UDB04_A0_A1, 0x40006a08 +.set CYREG_B1_UDB05_A0_A1, 0x40006a0a +.set CYREG_B1_UDB06_A0_A1, 0x40006a0c +.set CYREG_B1_UDB07_A0_A1, 0x40006a0e +.set CYREG_B1_UDB08_A0_A1, 0x40006a10 +.set CYREG_B1_UDB09_A0_A1, 0x40006a12 +.set CYREG_B1_UDB10_A0_A1, 0x40006a14 +.set CYREG_B1_UDB11_A0_A1, 0x40006a16 +.set CYREG_B1_UDB04_D0_D1, 0x40006a48 +.set CYREG_B1_UDB05_D0_D1, 0x40006a4a +.set CYREG_B1_UDB06_D0_D1, 0x40006a4c +.set CYREG_B1_UDB07_D0_D1, 0x40006a4e +.set CYREG_B1_UDB08_D0_D1, 0x40006a50 +.set CYREG_B1_UDB09_D0_D1, 0x40006a52 +.set CYREG_B1_UDB10_D0_D1, 0x40006a54 +.set CYREG_B1_UDB11_D0_D1, 0x40006a56 +.set CYREG_B1_UDB04_F0_F1, 0x40006a88 +.set CYREG_B1_UDB05_F0_F1, 0x40006a8a +.set CYREG_B1_UDB06_F0_F1, 0x40006a8c +.set CYREG_B1_UDB07_F0_F1, 0x40006a8e +.set CYREG_B1_UDB08_F0_F1, 0x40006a90 +.set CYREG_B1_UDB09_F0_F1, 0x40006a92 +.set CYREG_B1_UDB10_F0_F1, 0x40006a94 +.set CYREG_B1_UDB11_F0_F1, 0x40006a96 +.set CYREG_B1_UDB04_ST_CTL, 0x40006ac8 +.set CYREG_B1_UDB05_ST_CTL, 0x40006aca +.set CYREG_B1_UDB06_ST_CTL, 0x40006acc +.set CYREG_B1_UDB07_ST_CTL, 0x40006ace +.set CYREG_B1_UDB08_ST_CTL, 0x40006ad0 +.set CYREG_B1_UDB09_ST_CTL, 0x40006ad2 +.set CYREG_B1_UDB10_ST_CTL, 0x40006ad4 +.set CYREG_B1_UDB11_ST_CTL, 0x40006ad6 +.set CYREG_B1_UDB04_MSK_ACTL, 0x40006b08 +.set CYREG_B1_UDB05_MSK_ACTL, 0x40006b0a +.set CYREG_B1_UDB06_MSK_ACTL, 0x40006b0c +.set CYREG_B1_UDB07_MSK_ACTL, 0x40006b0e +.set CYREG_B1_UDB08_MSK_ACTL, 0x40006b10 +.set CYREG_B1_UDB09_MSK_ACTL, 0x40006b12 +.set CYREG_B1_UDB10_MSK_ACTL, 0x40006b14 +.set CYREG_B1_UDB11_MSK_ACTL, 0x40006b16 +.set CYREG_B1_UDB04_MC_00, 0x40006b48 +.set CYREG_B1_UDB05_MC_00, 0x40006b4a +.set CYREG_B1_UDB06_MC_00, 0x40006b4c +.set CYREG_B1_UDB07_MC_00, 0x40006b4e +.set CYREG_B1_UDB08_MC_00, 0x40006b50 +.set CYREG_B1_UDB09_MC_00, 0x40006b52 +.set CYREG_B1_UDB10_MC_00, 0x40006b54 +.set CYREG_B1_UDB11_MC_00, 0x40006b56 +.set CYDEV_UWRK_UWRK16_DEF_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_DEF_SIZE, 0x0000075e +.set CYDEV_UWRK_UWRK16_DEF_B0_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_DEF_B0_SIZE, 0x0000015e +.set CYREG_B0_UDB00_01_A0, 0x40006800 +.set CYREG_B0_UDB01_02_A0, 0x40006802 +.set CYREG_B0_UDB02_03_A0, 0x40006804 +.set CYREG_B0_UDB03_04_A0, 0x40006806 +.set CYREG_B0_UDB04_05_A0, 0x40006808 +.set CYREG_B0_UDB05_06_A0, 0x4000680a +.set CYREG_B0_UDB06_07_A0, 0x4000680c +.set CYREG_B0_UDB07_08_A0, 0x4000680e +.set CYREG_B0_UDB08_09_A0, 0x40006810 +.set CYREG_B0_UDB09_10_A0, 0x40006812 +.set CYREG_B0_UDB10_11_A0, 0x40006814 +.set CYREG_B0_UDB11_12_A0, 0x40006816 +.set CYREG_B0_UDB12_13_A0, 0x40006818 +.set CYREG_B0_UDB13_14_A0, 0x4000681a +.set CYREG_B0_UDB14_15_A0, 0x4000681c +.set CYREG_B0_UDB00_01_A1, 0x40006820 +.set CYREG_B0_UDB01_02_A1, 0x40006822 +.set CYREG_B0_UDB02_03_A1, 0x40006824 +.set CYREG_B0_UDB03_04_A1, 0x40006826 +.set CYREG_B0_UDB04_05_A1, 0x40006828 +.set CYREG_B0_UDB05_06_A1, 0x4000682a +.set CYREG_B0_UDB06_07_A1, 0x4000682c +.set CYREG_B0_UDB07_08_A1, 0x4000682e +.set CYREG_B0_UDB08_09_A1, 0x40006830 +.set CYREG_B0_UDB09_10_A1, 0x40006832 +.set CYREG_B0_UDB10_11_A1, 0x40006834 +.set CYREG_B0_UDB11_12_A1, 0x40006836 +.set CYREG_B0_UDB12_13_A1, 0x40006838 +.set CYREG_B0_UDB13_14_A1, 0x4000683a +.set CYREG_B0_UDB14_15_A1, 0x4000683c +.set CYREG_B0_UDB00_01_D0, 0x40006840 +.set CYREG_B0_UDB01_02_D0, 0x40006842 +.set CYREG_B0_UDB02_03_D0, 0x40006844 +.set CYREG_B0_UDB03_04_D0, 0x40006846 +.set CYREG_B0_UDB04_05_D0, 0x40006848 +.set CYREG_B0_UDB05_06_D0, 0x4000684a +.set CYREG_B0_UDB06_07_D0, 0x4000684c +.set CYREG_B0_UDB07_08_D0, 0x4000684e +.set CYREG_B0_UDB08_09_D0, 0x40006850 +.set CYREG_B0_UDB09_10_D0, 0x40006852 +.set CYREG_B0_UDB10_11_D0, 0x40006854 +.set CYREG_B0_UDB11_12_D0, 0x40006856 +.set CYREG_B0_UDB12_13_D0, 0x40006858 +.set CYREG_B0_UDB13_14_D0, 0x4000685a +.set CYREG_B0_UDB14_15_D0, 0x4000685c +.set CYREG_B0_UDB00_01_D1, 0x40006860 +.set CYREG_B0_UDB01_02_D1, 0x40006862 +.set CYREG_B0_UDB02_03_D1, 0x40006864 +.set CYREG_B0_UDB03_04_D1, 0x40006866 +.set CYREG_B0_UDB04_05_D1, 0x40006868 +.set CYREG_B0_UDB05_06_D1, 0x4000686a +.set CYREG_B0_UDB06_07_D1, 0x4000686c +.set CYREG_B0_UDB07_08_D1, 0x4000686e +.set CYREG_B0_UDB08_09_D1, 0x40006870 +.set CYREG_B0_UDB09_10_D1, 0x40006872 +.set CYREG_B0_UDB10_11_D1, 0x40006874 +.set CYREG_B0_UDB11_12_D1, 0x40006876 +.set CYREG_B0_UDB12_13_D1, 0x40006878 +.set CYREG_B0_UDB13_14_D1, 0x4000687a +.set CYREG_B0_UDB14_15_D1, 0x4000687c +.set CYREG_B0_UDB00_01_F0, 0x40006880 +.set CYREG_B0_UDB01_02_F0, 0x40006882 +.set CYREG_B0_UDB02_03_F0, 0x40006884 +.set CYREG_B0_UDB03_04_F0, 0x40006886 +.set CYREG_B0_UDB04_05_F0, 0x40006888 +.set CYREG_B0_UDB05_06_F0, 0x4000688a +.set CYREG_B0_UDB06_07_F0, 0x4000688c +.set CYREG_B0_UDB07_08_F0, 0x4000688e +.set CYREG_B0_UDB08_09_F0, 0x40006890 +.set CYREG_B0_UDB09_10_F0, 0x40006892 +.set CYREG_B0_UDB10_11_F0, 0x40006894 +.set CYREG_B0_UDB11_12_F0, 0x40006896 +.set CYREG_B0_UDB12_13_F0, 0x40006898 +.set CYREG_B0_UDB13_14_F0, 0x4000689a +.set CYREG_B0_UDB14_15_F0, 0x4000689c +.set CYREG_B0_UDB00_01_F1, 0x400068a0 +.set CYREG_B0_UDB01_02_F1, 0x400068a2 +.set CYREG_B0_UDB02_03_F1, 0x400068a4 +.set CYREG_B0_UDB03_04_F1, 0x400068a6 +.set CYREG_B0_UDB04_05_F1, 0x400068a8 +.set CYREG_B0_UDB05_06_F1, 0x400068aa +.set CYREG_B0_UDB06_07_F1, 0x400068ac +.set CYREG_B0_UDB07_08_F1, 0x400068ae +.set CYREG_B0_UDB08_09_F1, 0x400068b0 +.set CYREG_B0_UDB09_10_F1, 0x400068b2 +.set CYREG_B0_UDB10_11_F1, 0x400068b4 +.set CYREG_B0_UDB11_12_F1, 0x400068b6 +.set CYREG_B0_UDB12_13_F1, 0x400068b8 +.set CYREG_B0_UDB13_14_F1, 0x400068ba +.set CYREG_B0_UDB14_15_F1, 0x400068bc +.set CYREG_B0_UDB00_01_ST, 0x400068c0 +.set CYREG_B0_UDB01_02_ST, 0x400068c2 +.set CYREG_B0_UDB02_03_ST, 0x400068c4 +.set CYREG_B0_UDB03_04_ST, 0x400068c6 +.set CYREG_B0_UDB04_05_ST, 0x400068c8 +.set CYREG_B0_UDB05_06_ST, 0x400068ca +.set CYREG_B0_UDB06_07_ST, 0x400068cc +.set CYREG_B0_UDB07_08_ST, 0x400068ce +.set CYREG_B0_UDB08_09_ST, 0x400068d0 +.set CYREG_B0_UDB09_10_ST, 0x400068d2 +.set CYREG_B0_UDB10_11_ST, 0x400068d4 +.set CYREG_B0_UDB11_12_ST, 0x400068d6 +.set CYREG_B0_UDB12_13_ST, 0x400068d8 +.set CYREG_B0_UDB13_14_ST, 0x400068da +.set CYREG_B0_UDB14_15_ST, 0x400068dc +.set CYREG_B0_UDB00_01_CTL, 0x400068e0 +.set CYREG_B0_UDB01_02_CTL, 0x400068e2 +.set CYREG_B0_UDB02_03_CTL, 0x400068e4 +.set CYREG_B0_UDB03_04_CTL, 0x400068e6 +.set CYREG_B0_UDB04_05_CTL, 0x400068e8 +.set CYREG_B0_UDB05_06_CTL, 0x400068ea +.set CYREG_B0_UDB06_07_CTL, 0x400068ec +.set CYREG_B0_UDB07_08_CTL, 0x400068ee +.set CYREG_B0_UDB08_09_CTL, 0x400068f0 +.set CYREG_B0_UDB09_10_CTL, 0x400068f2 +.set CYREG_B0_UDB10_11_CTL, 0x400068f4 +.set CYREG_B0_UDB11_12_CTL, 0x400068f6 +.set CYREG_B0_UDB12_13_CTL, 0x400068f8 +.set CYREG_B0_UDB13_14_CTL, 0x400068fa +.set CYREG_B0_UDB14_15_CTL, 0x400068fc +.set CYREG_B0_UDB00_01_MSK, 0x40006900 +.set CYREG_B0_UDB01_02_MSK, 0x40006902 +.set CYREG_B0_UDB02_03_MSK, 0x40006904 +.set CYREG_B0_UDB03_04_MSK, 0x40006906 +.set CYREG_B0_UDB04_05_MSK, 0x40006908 +.set CYREG_B0_UDB05_06_MSK, 0x4000690a +.set CYREG_B0_UDB06_07_MSK, 0x4000690c +.set CYREG_B0_UDB07_08_MSK, 0x4000690e +.set CYREG_B0_UDB08_09_MSK, 0x40006910 +.set CYREG_B0_UDB09_10_MSK, 0x40006912 +.set CYREG_B0_UDB10_11_MSK, 0x40006914 +.set CYREG_B0_UDB11_12_MSK, 0x40006916 +.set CYREG_B0_UDB12_13_MSK, 0x40006918 +.set CYREG_B0_UDB13_14_MSK, 0x4000691a +.set CYREG_B0_UDB14_15_MSK, 0x4000691c +.set CYREG_B0_UDB00_01_ACTL, 0x40006920 +.set CYREG_B0_UDB01_02_ACTL, 0x40006922 +.set CYREG_B0_UDB02_03_ACTL, 0x40006924 +.set CYREG_B0_UDB03_04_ACTL, 0x40006926 +.set CYREG_B0_UDB04_05_ACTL, 0x40006928 +.set CYREG_B0_UDB05_06_ACTL, 0x4000692a +.set CYREG_B0_UDB06_07_ACTL, 0x4000692c +.set CYREG_B0_UDB07_08_ACTL, 0x4000692e +.set CYREG_B0_UDB08_09_ACTL, 0x40006930 +.set CYREG_B0_UDB09_10_ACTL, 0x40006932 +.set CYREG_B0_UDB10_11_ACTL, 0x40006934 +.set CYREG_B0_UDB11_12_ACTL, 0x40006936 +.set CYREG_B0_UDB12_13_ACTL, 0x40006938 +.set CYREG_B0_UDB13_14_ACTL, 0x4000693a +.set CYREG_B0_UDB14_15_ACTL, 0x4000693c +.set CYREG_B0_UDB00_01_MC, 0x40006940 +.set CYREG_B0_UDB01_02_MC, 0x40006942 +.set CYREG_B0_UDB02_03_MC, 0x40006944 +.set CYREG_B0_UDB03_04_MC, 0x40006946 +.set CYREG_B0_UDB04_05_MC, 0x40006948 +.set CYREG_B0_UDB05_06_MC, 0x4000694a +.set CYREG_B0_UDB06_07_MC, 0x4000694c +.set CYREG_B0_UDB07_08_MC, 0x4000694e +.set CYREG_B0_UDB08_09_MC, 0x40006950 +.set CYREG_B0_UDB09_10_MC, 0x40006952 +.set CYREG_B0_UDB10_11_MC, 0x40006954 +.set CYREG_B0_UDB11_12_MC, 0x40006956 +.set CYREG_B0_UDB12_13_MC, 0x40006958 +.set CYREG_B0_UDB13_14_MC, 0x4000695a +.set CYREG_B0_UDB14_15_MC, 0x4000695c +.set CYDEV_UWRK_UWRK16_DEF_B1_BASE, 0x40006a00 +.set CYDEV_UWRK_UWRK16_DEF_B1_SIZE, 0x0000015e +.set CYREG_B1_UDB04_05_A0, 0x40006a08 +.set CYREG_B1_UDB05_06_A0, 0x40006a0a +.set CYREG_B1_UDB06_07_A0, 0x40006a0c +.set CYREG_B1_UDB07_08_A0, 0x40006a0e +.set CYREG_B1_UDB08_09_A0, 0x40006a10 +.set CYREG_B1_UDB09_10_A0, 0x40006a12 +.set CYREG_B1_UDB10_11_A0, 0x40006a14 +.set CYREG_B1_UDB11_12_A0, 0x40006a16 +.set CYREG_B1_UDB04_05_A1, 0x40006a28 +.set CYREG_B1_UDB05_06_A1, 0x40006a2a +.set CYREG_B1_UDB06_07_A1, 0x40006a2c +.set CYREG_B1_UDB07_08_A1, 0x40006a2e +.set CYREG_B1_UDB08_09_A1, 0x40006a30 +.set CYREG_B1_UDB09_10_A1, 0x40006a32 +.set CYREG_B1_UDB10_11_A1, 0x40006a34 +.set CYREG_B1_UDB11_12_A1, 0x40006a36 +.set CYREG_B1_UDB04_05_D0, 0x40006a48 +.set CYREG_B1_UDB05_06_D0, 0x40006a4a +.set CYREG_B1_UDB06_07_D0, 0x40006a4c +.set CYREG_B1_UDB07_08_D0, 0x40006a4e +.set CYREG_B1_UDB08_09_D0, 0x40006a50 +.set CYREG_B1_UDB09_10_D0, 0x40006a52 +.set CYREG_B1_UDB10_11_D0, 0x40006a54 +.set CYREG_B1_UDB11_12_D0, 0x40006a56 +.set CYREG_B1_UDB04_05_D1, 0x40006a68 +.set CYREG_B1_UDB05_06_D1, 0x40006a6a +.set CYREG_B1_UDB06_07_D1, 0x40006a6c +.set CYREG_B1_UDB07_08_D1, 0x40006a6e +.set CYREG_B1_UDB08_09_D1, 0x40006a70 +.set CYREG_B1_UDB09_10_D1, 0x40006a72 +.set CYREG_B1_UDB10_11_D1, 0x40006a74 +.set CYREG_B1_UDB11_12_D1, 0x40006a76 +.set CYREG_B1_UDB04_05_F0, 0x40006a88 +.set CYREG_B1_UDB05_06_F0, 0x40006a8a +.set CYREG_B1_UDB06_07_F0, 0x40006a8c +.set CYREG_B1_UDB07_08_F0, 0x40006a8e +.set CYREG_B1_UDB08_09_F0, 0x40006a90 +.set CYREG_B1_UDB09_10_F0, 0x40006a92 +.set CYREG_B1_UDB10_11_F0, 0x40006a94 +.set CYREG_B1_UDB11_12_F0, 0x40006a96 +.set CYREG_B1_UDB04_05_F1, 0x40006aa8 +.set CYREG_B1_UDB05_06_F1, 0x40006aaa +.set CYREG_B1_UDB06_07_F1, 0x40006aac +.set CYREG_B1_UDB07_08_F1, 0x40006aae +.set CYREG_B1_UDB08_09_F1, 0x40006ab0 +.set CYREG_B1_UDB09_10_F1, 0x40006ab2 +.set CYREG_B1_UDB10_11_F1, 0x40006ab4 +.set CYREG_B1_UDB11_12_F1, 0x40006ab6 +.set CYREG_B1_UDB04_05_ST, 0x40006ac8 +.set CYREG_B1_UDB05_06_ST, 0x40006aca +.set CYREG_B1_UDB06_07_ST, 0x40006acc +.set CYREG_B1_UDB07_08_ST, 0x40006ace +.set CYREG_B1_UDB08_09_ST, 0x40006ad0 +.set CYREG_B1_UDB09_10_ST, 0x40006ad2 +.set CYREG_B1_UDB10_11_ST, 0x40006ad4 +.set CYREG_B1_UDB11_12_ST, 0x40006ad6 +.set CYREG_B1_UDB04_05_CTL, 0x40006ae8 +.set CYREG_B1_UDB05_06_CTL, 0x40006aea +.set CYREG_B1_UDB06_07_CTL, 0x40006aec +.set CYREG_B1_UDB07_08_CTL, 0x40006aee +.set CYREG_B1_UDB08_09_CTL, 0x40006af0 +.set CYREG_B1_UDB09_10_CTL, 0x40006af2 +.set CYREG_B1_UDB10_11_CTL, 0x40006af4 +.set CYREG_B1_UDB11_12_CTL, 0x40006af6 +.set CYREG_B1_UDB04_05_MSK, 0x40006b08 +.set CYREG_B1_UDB05_06_MSK, 0x40006b0a +.set CYREG_B1_UDB06_07_MSK, 0x40006b0c +.set CYREG_B1_UDB07_08_MSK, 0x40006b0e +.set CYREG_B1_UDB08_09_MSK, 0x40006b10 +.set CYREG_B1_UDB09_10_MSK, 0x40006b12 +.set CYREG_B1_UDB10_11_MSK, 0x40006b14 +.set CYREG_B1_UDB11_12_MSK, 0x40006b16 +.set CYREG_B1_UDB04_05_ACTL, 0x40006b28 +.set CYREG_B1_UDB05_06_ACTL, 0x40006b2a +.set CYREG_B1_UDB06_07_ACTL, 0x40006b2c +.set CYREG_B1_UDB07_08_ACTL, 0x40006b2e +.set CYREG_B1_UDB08_09_ACTL, 0x40006b30 +.set CYREG_B1_UDB09_10_ACTL, 0x40006b32 +.set CYREG_B1_UDB10_11_ACTL, 0x40006b34 +.set CYREG_B1_UDB11_12_ACTL, 0x40006b36 +.set CYREG_B1_UDB04_05_MC, 0x40006b48 +.set CYREG_B1_UDB05_06_MC, 0x40006b4a +.set CYREG_B1_UDB06_07_MC, 0x40006b4c +.set CYREG_B1_UDB07_08_MC, 0x40006b4e +.set CYREG_B1_UDB08_09_MC, 0x40006b50 +.set CYREG_B1_UDB09_10_MC, 0x40006b52 +.set CYREG_B1_UDB10_11_MC, 0x40006b54 +.set CYREG_B1_UDB11_12_MC, 0x40006b56 +.set CYDEV_PHUB_BASE, 0x40007000 +.set CYDEV_PHUB_SIZE, 0x00000c00 +.set CYREG_PHUB_CFG, 0x40007000 +.set CYREG_PHUB_ERR, 0x40007004 +.set CYREG_PHUB_ERR_ADR, 0x40007008 +.set CYDEV_PHUB_CH0_BASE, 0x40007010 +.set CYDEV_PHUB_CH0_SIZE, 0x0000000c +.set CYREG_PHUB_CH0_BASIC_CFG, 0x40007010 +.set CYREG_PHUB_CH0_ACTION, 0x40007014 +.set CYREG_PHUB_CH0_BASIC_STATUS, 0x40007018 +.set CYDEV_PHUB_CH1_BASE, 0x40007020 +.set CYDEV_PHUB_CH1_SIZE, 0x0000000c +.set CYREG_PHUB_CH1_BASIC_CFG, 0x40007020 +.set CYREG_PHUB_CH1_ACTION, 0x40007024 +.set CYREG_PHUB_CH1_BASIC_STATUS, 0x40007028 +.set CYDEV_PHUB_CH2_BASE, 0x40007030 +.set CYDEV_PHUB_CH2_SIZE, 0x0000000c +.set CYREG_PHUB_CH2_BASIC_CFG, 0x40007030 +.set CYREG_PHUB_CH2_ACTION, 0x40007034 +.set CYREG_PHUB_CH2_BASIC_STATUS, 0x40007038 +.set CYDEV_PHUB_CH3_BASE, 0x40007040 +.set CYDEV_PHUB_CH3_SIZE, 0x0000000c +.set CYREG_PHUB_CH3_BASIC_CFG, 0x40007040 +.set CYREG_PHUB_CH3_ACTION, 0x40007044 +.set CYREG_PHUB_CH3_BASIC_STATUS, 0x40007048 +.set CYDEV_PHUB_CH4_BASE, 0x40007050 +.set CYDEV_PHUB_CH4_SIZE, 0x0000000c +.set CYREG_PHUB_CH4_BASIC_CFG, 0x40007050 +.set CYREG_PHUB_CH4_ACTION, 0x40007054 +.set CYREG_PHUB_CH4_BASIC_STATUS, 0x40007058 +.set CYDEV_PHUB_CH5_BASE, 0x40007060 +.set CYDEV_PHUB_CH5_SIZE, 0x0000000c +.set CYREG_PHUB_CH5_BASIC_CFG, 0x40007060 +.set CYREG_PHUB_CH5_ACTION, 0x40007064 +.set CYREG_PHUB_CH5_BASIC_STATUS, 0x40007068 +.set CYDEV_PHUB_CH6_BASE, 0x40007070 +.set CYDEV_PHUB_CH6_SIZE, 0x0000000c +.set CYREG_PHUB_CH6_BASIC_CFG, 0x40007070 +.set CYREG_PHUB_CH6_ACTION, 0x40007074 +.set CYREG_PHUB_CH6_BASIC_STATUS, 0x40007078 +.set CYDEV_PHUB_CH7_BASE, 0x40007080 +.set CYDEV_PHUB_CH7_SIZE, 0x0000000c +.set CYREG_PHUB_CH7_BASIC_CFG, 0x40007080 +.set CYREG_PHUB_CH7_ACTION, 0x40007084 +.set CYREG_PHUB_CH7_BASIC_STATUS, 0x40007088 +.set CYDEV_PHUB_CH8_BASE, 0x40007090 +.set CYDEV_PHUB_CH8_SIZE, 0x0000000c +.set CYREG_PHUB_CH8_BASIC_CFG, 0x40007090 +.set CYREG_PHUB_CH8_ACTION, 0x40007094 +.set CYREG_PHUB_CH8_BASIC_STATUS, 0x40007098 +.set CYDEV_PHUB_CH9_BASE, 0x400070a0 +.set CYDEV_PHUB_CH9_SIZE, 0x0000000c +.set CYREG_PHUB_CH9_BASIC_CFG, 0x400070a0 +.set CYREG_PHUB_CH9_ACTION, 0x400070a4 +.set CYREG_PHUB_CH9_BASIC_STATUS, 0x400070a8 +.set CYDEV_PHUB_CH10_BASE, 0x400070b0 +.set CYDEV_PHUB_CH10_SIZE, 0x0000000c +.set CYREG_PHUB_CH10_BASIC_CFG, 0x400070b0 +.set CYREG_PHUB_CH10_ACTION, 0x400070b4 +.set CYREG_PHUB_CH10_BASIC_STATUS, 0x400070b8 +.set CYDEV_PHUB_CH11_BASE, 0x400070c0 +.set CYDEV_PHUB_CH11_SIZE, 0x0000000c +.set CYREG_PHUB_CH11_BASIC_CFG, 0x400070c0 +.set CYREG_PHUB_CH11_ACTION, 0x400070c4 +.set CYREG_PHUB_CH11_BASIC_STATUS, 0x400070c8 +.set CYDEV_PHUB_CH12_BASE, 0x400070d0 +.set CYDEV_PHUB_CH12_SIZE, 0x0000000c +.set CYREG_PHUB_CH12_BASIC_CFG, 0x400070d0 +.set CYREG_PHUB_CH12_ACTION, 0x400070d4 +.set CYREG_PHUB_CH12_BASIC_STATUS, 0x400070d8 +.set CYDEV_PHUB_CH13_BASE, 0x400070e0 +.set CYDEV_PHUB_CH13_SIZE, 0x0000000c +.set CYREG_PHUB_CH13_BASIC_CFG, 0x400070e0 +.set CYREG_PHUB_CH13_ACTION, 0x400070e4 +.set CYREG_PHUB_CH13_BASIC_STATUS, 0x400070e8 +.set CYDEV_PHUB_CH14_BASE, 0x400070f0 +.set CYDEV_PHUB_CH14_SIZE, 0x0000000c +.set CYREG_PHUB_CH14_BASIC_CFG, 0x400070f0 +.set CYREG_PHUB_CH14_ACTION, 0x400070f4 +.set CYREG_PHUB_CH14_BASIC_STATUS, 0x400070f8 +.set CYDEV_PHUB_CH15_BASE, 0x40007100 +.set CYDEV_PHUB_CH15_SIZE, 0x0000000c +.set CYREG_PHUB_CH15_BASIC_CFG, 0x40007100 +.set CYREG_PHUB_CH15_ACTION, 0x40007104 +.set CYREG_PHUB_CH15_BASIC_STATUS, 0x40007108 +.set CYDEV_PHUB_CH16_BASE, 0x40007110 +.set CYDEV_PHUB_CH16_SIZE, 0x0000000c +.set CYREG_PHUB_CH16_BASIC_CFG, 0x40007110 +.set CYREG_PHUB_CH16_ACTION, 0x40007114 +.set CYREG_PHUB_CH16_BASIC_STATUS, 0x40007118 +.set CYDEV_PHUB_CH17_BASE, 0x40007120 +.set CYDEV_PHUB_CH17_SIZE, 0x0000000c +.set CYREG_PHUB_CH17_BASIC_CFG, 0x40007120 +.set CYREG_PHUB_CH17_ACTION, 0x40007124 +.set CYREG_PHUB_CH17_BASIC_STATUS, 0x40007128 +.set CYDEV_PHUB_CH18_BASE, 0x40007130 +.set CYDEV_PHUB_CH18_SIZE, 0x0000000c +.set CYREG_PHUB_CH18_BASIC_CFG, 0x40007130 +.set CYREG_PHUB_CH18_ACTION, 0x40007134 +.set CYREG_PHUB_CH18_BASIC_STATUS, 0x40007138 +.set CYDEV_PHUB_CH19_BASE, 0x40007140 +.set CYDEV_PHUB_CH19_SIZE, 0x0000000c +.set CYREG_PHUB_CH19_BASIC_CFG, 0x40007140 +.set CYREG_PHUB_CH19_ACTION, 0x40007144 +.set CYREG_PHUB_CH19_BASIC_STATUS, 0x40007148 +.set CYDEV_PHUB_CH20_BASE, 0x40007150 +.set CYDEV_PHUB_CH20_SIZE, 0x0000000c +.set CYREG_PHUB_CH20_BASIC_CFG, 0x40007150 +.set CYREG_PHUB_CH20_ACTION, 0x40007154 +.set CYREG_PHUB_CH20_BASIC_STATUS, 0x40007158 +.set CYDEV_PHUB_CH21_BASE, 0x40007160 +.set CYDEV_PHUB_CH21_SIZE, 0x0000000c +.set CYREG_PHUB_CH21_BASIC_CFG, 0x40007160 +.set CYREG_PHUB_CH21_ACTION, 0x40007164 +.set CYREG_PHUB_CH21_BASIC_STATUS, 0x40007168 +.set CYDEV_PHUB_CH22_BASE, 0x40007170 +.set CYDEV_PHUB_CH22_SIZE, 0x0000000c +.set CYREG_PHUB_CH22_BASIC_CFG, 0x40007170 +.set CYREG_PHUB_CH22_ACTION, 0x40007174 +.set CYREG_PHUB_CH22_BASIC_STATUS, 0x40007178 +.set CYDEV_PHUB_CH23_BASE, 0x40007180 +.set CYDEV_PHUB_CH23_SIZE, 0x0000000c +.set CYREG_PHUB_CH23_BASIC_CFG, 0x40007180 +.set CYREG_PHUB_CH23_ACTION, 0x40007184 +.set CYREG_PHUB_CH23_BASIC_STATUS, 0x40007188 +.set CYDEV_PHUB_CFGMEM0_BASE, 0x40007600 +.set CYDEV_PHUB_CFGMEM0_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM0_CFG0, 0x40007600 +.set CYREG_PHUB_CFGMEM0_CFG1, 0x40007604 +.set CYDEV_PHUB_CFGMEM1_BASE, 0x40007608 +.set CYDEV_PHUB_CFGMEM1_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM1_CFG0, 0x40007608 +.set CYREG_PHUB_CFGMEM1_CFG1, 0x4000760c +.set CYDEV_PHUB_CFGMEM2_BASE, 0x40007610 +.set CYDEV_PHUB_CFGMEM2_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM2_CFG0, 0x40007610 +.set CYREG_PHUB_CFGMEM2_CFG1, 0x40007614 +.set CYDEV_PHUB_CFGMEM3_BASE, 0x40007618 +.set CYDEV_PHUB_CFGMEM3_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM3_CFG0, 0x40007618 +.set CYREG_PHUB_CFGMEM3_CFG1, 0x4000761c +.set CYDEV_PHUB_CFGMEM4_BASE, 0x40007620 +.set CYDEV_PHUB_CFGMEM4_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM4_CFG0, 0x40007620 +.set CYREG_PHUB_CFGMEM4_CFG1, 0x40007624 +.set CYDEV_PHUB_CFGMEM5_BASE, 0x40007628 +.set CYDEV_PHUB_CFGMEM5_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM5_CFG0, 0x40007628 +.set CYREG_PHUB_CFGMEM5_CFG1, 0x4000762c +.set CYDEV_PHUB_CFGMEM6_BASE, 0x40007630 +.set CYDEV_PHUB_CFGMEM6_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM6_CFG0, 0x40007630 +.set CYREG_PHUB_CFGMEM6_CFG1, 0x40007634 +.set CYDEV_PHUB_CFGMEM7_BASE, 0x40007638 +.set CYDEV_PHUB_CFGMEM7_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM7_CFG0, 0x40007638 +.set CYREG_PHUB_CFGMEM7_CFG1, 0x4000763c +.set CYDEV_PHUB_CFGMEM8_BASE, 0x40007640 +.set CYDEV_PHUB_CFGMEM8_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM8_CFG0, 0x40007640 +.set CYREG_PHUB_CFGMEM8_CFG1, 0x40007644 +.set CYDEV_PHUB_CFGMEM9_BASE, 0x40007648 +.set CYDEV_PHUB_CFGMEM9_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM9_CFG0, 0x40007648 +.set CYREG_PHUB_CFGMEM9_CFG1, 0x4000764c +.set CYDEV_PHUB_CFGMEM10_BASE, 0x40007650 +.set CYDEV_PHUB_CFGMEM10_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM10_CFG0, 0x40007650 +.set CYREG_PHUB_CFGMEM10_CFG1, 0x40007654 +.set CYDEV_PHUB_CFGMEM11_BASE, 0x40007658 +.set CYDEV_PHUB_CFGMEM11_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM11_CFG0, 0x40007658 +.set CYREG_PHUB_CFGMEM11_CFG1, 0x4000765c +.set CYDEV_PHUB_CFGMEM12_BASE, 0x40007660 +.set CYDEV_PHUB_CFGMEM12_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM12_CFG0, 0x40007660 +.set CYREG_PHUB_CFGMEM12_CFG1, 0x40007664 +.set CYDEV_PHUB_CFGMEM13_BASE, 0x40007668 +.set CYDEV_PHUB_CFGMEM13_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM13_CFG0, 0x40007668 +.set CYREG_PHUB_CFGMEM13_CFG1, 0x4000766c +.set CYDEV_PHUB_CFGMEM14_BASE, 0x40007670 +.set CYDEV_PHUB_CFGMEM14_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM14_CFG0, 0x40007670 +.set CYREG_PHUB_CFGMEM14_CFG1, 0x40007674 +.set CYDEV_PHUB_CFGMEM15_BASE, 0x40007678 +.set CYDEV_PHUB_CFGMEM15_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM15_CFG0, 0x40007678 +.set CYREG_PHUB_CFGMEM15_CFG1, 0x4000767c +.set CYDEV_PHUB_CFGMEM16_BASE, 0x40007680 +.set CYDEV_PHUB_CFGMEM16_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM16_CFG0, 0x40007680 +.set CYREG_PHUB_CFGMEM16_CFG1, 0x40007684 +.set CYDEV_PHUB_CFGMEM17_BASE, 0x40007688 +.set CYDEV_PHUB_CFGMEM17_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM17_CFG0, 0x40007688 +.set CYREG_PHUB_CFGMEM17_CFG1, 0x4000768c +.set CYDEV_PHUB_CFGMEM18_BASE, 0x40007690 +.set CYDEV_PHUB_CFGMEM18_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM18_CFG0, 0x40007690 +.set CYREG_PHUB_CFGMEM18_CFG1, 0x40007694 +.set CYDEV_PHUB_CFGMEM19_BASE, 0x40007698 +.set CYDEV_PHUB_CFGMEM19_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM19_CFG0, 0x40007698 +.set CYREG_PHUB_CFGMEM19_CFG1, 0x4000769c +.set CYDEV_PHUB_CFGMEM20_BASE, 0x400076a0 +.set CYDEV_PHUB_CFGMEM20_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM20_CFG0, 0x400076a0 +.set CYREG_PHUB_CFGMEM20_CFG1, 0x400076a4 +.set CYDEV_PHUB_CFGMEM21_BASE, 0x400076a8 +.set CYDEV_PHUB_CFGMEM21_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM21_CFG0, 0x400076a8 +.set CYREG_PHUB_CFGMEM21_CFG1, 0x400076ac +.set CYDEV_PHUB_CFGMEM22_BASE, 0x400076b0 +.set CYDEV_PHUB_CFGMEM22_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM22_CFG0, 0x400076b0 +.set CYREG_PHUB_CFGMEM22_CFG1, 0x400076b4 +.set CYDEV_PHUB_CFGMEM23_BASE, 0x400076b8 +.set CYDEV_PHUB_CFGMEM23_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM23_CFG0, 0x400076b8 +.set CYREG_PHUB_CFGMEM23_CFG1, 0x400076bc +.set CYDEV_PHUB_TDMEM0_BASE, 0x40007800 +.set CYDEV_PHUB_TDMEM0_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM0_ORIG_TD0, 0x40007800 +.set CYREG_PHUB_TDMEM0_ORIG_TD1, 0x40007804 +.set CYDEV_PHUB_TDMEM1_BASE, 0x40007808 +.set CYDEV_PHUB_TDMEM1_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM1_ORIG_TD0, 0x40007808 +.set CYREG_PHUB_TDMEM1_ORIG_TD1, 0x4000780c +.set CYDEV_PHUB_TDMEM2_BASE, 0x40007810 +.set CYDEV_PHUB_TDMEM2_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM2_ORIG_TD0, 0x40007810 +.set CYREG_PHUB_TDMEM2_ORIG_TD1, 0x40007814 +.set CYDEV_PHUB_TDMEM3_BASE, 0x40007818 +.set CYDEV_PHUB_TDMEM3_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM3_ORIG_TD0, 0x40007818 +.set CYREG_PHUB_TDMEM3_ORIG_TD1, 0x4000781c +.set CYDEV_PHUB_TDMEM4_BASE, 0x40007820 +.set CYDEV_PHUB_TDMEM4_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM4_ORIG_TD0, 0x40007820 +.set CYREG_PHUB_TDMEM4_ORIG_TD1, 0x40007824 +.set CYDEV_PHUB_TDMEM5_BASE, 0x40007828 +.set CYDEV_PHUB_TDMEM5_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM5_ORIG_TD0, 0x40007828 +.set CYREG_PHUB_TDMEM5_ORIG_TD1, 0x4000782c +.set CYDEV_PHUB_TDMEM6_BASE, 0x40007830 +.set CYDEV_PHUB_TDMEM6_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM6_ORIG_TD0, 0x40007830 +.set CYREG_PHUB_TDMEM6_ORIG_TD1, 0x40007834 +.set CYDEV_PHUB_TDMEM7_BASE, 0x40007838 +.set CYDEV_PHUB_TDMEM7_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM7_ORIG_TD0, 0x40007838 +.set CYREG_PHUB_TDMEM7_ORIG_TD1, 0x4000783c +.set CYDEV_PHUB_TDMEM8_BASE, 0x40007840 +.set CYDEV_PHUB_TDMEM8_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM8_ORIG_TD0, 0x40007840 +.set CYREG_PHUB_TDMEM8_ORIG_TD1, 0x40007844 +.set CYDEV_PHUB_TDMEM9_BASE, 0x40007848 +.set CYDEV_PHUB_TDMEM9_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM9_ORIG_TD0, 0x40007848 +.set CYREG_PHUB_TDMEM9_ORIG_TD1, 0x4000784c +.set CYDEV_PHUB_TDMEM10_BASE, 0x40007850 +.set CYDEV_PHUB_TDMEM10_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM10_ORIG_TD0, 0x40007850 +.set CYREG_PHUB_TDMEM10_ORIG_TD1, 0x40007854 +.set CYDEV_PHUB_TDMEM11_BASE, 0x40007858 +.set CYDEV_PHUB_TDMEM11_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM11_ORIG_TD0, 0x40007858 +.set CYREG_PHUB_TDMEM11_ORIG_TD1, 0x4000785c +.set CYDEV_PHUB_TDMEM12_BASE, 0x40007860 +.set CYDEV_PHUB_TDMEM12_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM12_ORIG_TD0, 0x40007860 +.set CYREG_PHUB_TDMEM12_ORIG_TD1, 0x40007864 +.set CYDEV_PHUB_TDMEM13_BASE, 0x40007868 +.set CYDEV_PHUB_TDMEM13_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM13_ORIG_TD0, 0x40007868 +.set CYREG_PHUB_TDMEM13_ORIG_TD1, 0x4000786c +.set CYDEV_PHUB_TDMEM14_BASE, 0x40007870 +.set CYDEV_PHUB_TDMEM14_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM14_ORIG_TD0, 0x40007870 +.set CYREG_PHUB_TDMEM14_ORIG_TD1, 0x40007874 +.set CYDEV_PHUB_TDMEM15_BASE, 0x40007878 +.set CYDEV_PHUB_TDMEM15_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM15_ORIG_TD0, 0x40007878 +.set CYREG_PHUB_TDMEM15_ORIG_TD1, 0x4000787c +.set CYDEV_PHUB_TDMEM16_BASE, 0x40007880 +.set CYDEV_PHUB_TDMEM16_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM16_ORIG_TD0, 0x40007880 +.set CYREG_PHUB_TDMEM16_ORIG_TD1, 0x40007884 +.set CYDEV_PHUB_TDMEM17_BASE, 0x40007888 +.set CYDEV_PHUB_TDMEM17_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM17_ORIG_TD0, 0x40007888 +.set CYREG_PHUB_TDMEM17_ORIG_TD1, 0x4000788c +.set CYDEV_PHUB_TDMEM18_BASE, 0x40007890 +.set CYDEV_PHUB_TDMEM18_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM18_ORIG_TD0, 0x40007890 +.set CYREG_PHUB_TDMEM18_ORIG_TD1, 0x40007894 +.set CYDEV_PHUB_TDMEM19_BASE, 0x40007898 +.set CYDEV_PHUB_TDMEM19_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM19_ORIG_TD0, 0x40007898 +.set CYREG_PHUB_TDMEM19_ORIG_TD1, 0x4000789c +.set CYDEV_PHUB_TDMEM20_BASE, 0x400078a0 +.set CYDEV_PHUB_TDMEM20_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM20_ORIG_TD0, 0x400078a0 +.set CYREG_PHUB_TDMEM20_ORIG_TD1, 0x400078a4 +.set CYDEV_PHUB_TDMEM21_BASE, 0x400078a8 +.set CYDEV_PHUB_TDMEM21_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM21_ORIG_TD0, 0x400078a8 +.set CYREG_PHUB_TDMEM21_ORIG_TD1, 0x400078ac +.set CYDEV_PHUB_TDMEM22_BASE, 0x400078b0 +.set CYDEV_PHUB_TDMEM22_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM22_ORIG_TD0, 0x400078b0 +.set CYREG_PHUB_TDMEM22_ORIG_TD1, 0x400078b4 +.set CYDEV_PHUB_TDMEM23_BASE, 0x400078b8 +.set CYDEV_PHUB_TDMEM23_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM23_ORIG_TD0, 0x400078b8 +.set CYREG_PHUB_TDMEM23_ORIG_TD1, 0x400078bc +.set CYDEV_PHUB_TDMEM24_BASE, 0x400078c0 +.set CYDEV_PHUB_TDMEM24_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM24_ORIG_TD0, 0x400078c0 +.set CYREG_PHUB_TDMEM24_ORIG_TD1, 0x400078c4 +.set CYDEV_PHUB_TDMEM25_BASE, 0x400078c8 +.set CYDEV_PHUB_TDMEM25_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM25_ORIG_TD0, 0x400078c8 +.set CYREG_PHUB_TDMEM25_ORIG_TD1, 0x400078cc +.set CYDEV_PHUB_TDMEM26_BASE, 0x400078d0 +.set CYDEV_PHUB_TDMEM26_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM26_ORIG_TD0, 0x400078d0 +.set CYREG_PHUB_TDMEM26_ORIG_TD1, 0x400078d4 +.set CYDEV_PHUB_TDMEM27_BASE, 0x400078d8 +.set CYDEV_PHUB_TDMEM27_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM27_ORIG_TD0, 0x400078d8 +.set CYREG_PHUB_TDMEM27_ORIG_TD1, 0x400078dc +.set CYDEV_PHUB_TDMEM28_BASE, 0x400078e0 +.set CYDEV_PHUB_TDMEM28_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM28_ORIG_TD0, 0x400078e0 +.set CYREG_PHUB_TDMEM28_ORIG_TD1, 0x400078e4 +.set CYDEV_PHUB_TDMEM29_BASE, 0x400078e8 +.set CYDEV_PHUB_TDMEM29_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM29_ORIG_TD0, 0x400078e8 +.set CYREG_PHUB_TDMEM29_ORIG_TD1, 0x400078ec +.set CYDEV_PHUB_TDMEM30_BASE, 0x400078f0 +.set CYDEV_PHUB_TDMEM30_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM30_ORIG_TD0, 0x400078f0 +.set CYREG_PHUB_TDMEM30_ORIG_TD1, 0x400078f4 +.set CYDEV_PHUB_TDMEM31_BASE, 0x400078f8 +.set CYDEV_PHUB_TDMEM31_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM31_ORIG_TD0, 0x400078f8 +.set CYREG_PHUB_TDMEM31_ORIG_TD1, 0x400078fc +.set CYDEV_PHUB_TDMEM32_BASE, 0x40007900 +.set CYDEV_PHUB_TDMEM32_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM32_ORIG_TD0, 0x40007900 +.set CYREG_PHUB_TDMEM32_ORIG_TD1, 0x40007904 +.set CYDEV_PHUB_TDMEM33_BASE, 0x40007908 +.set CYDEV_PHUB_TDMEM33_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM33_ORIG_TD0, 0x40007908 +.set CYREG_PHUB_TDMEM33_ORIG_TD1, 0x4000790c +.set CYDEV_PHUB_TDMEM34_BASE, 0x40007910 +.set CYDEV_PHUB_TDMEM34_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM34_ORIG_TD0, 0x40007910 +.set CYREG_PHUB_TDMEM34_ORIG_TD1, 0x40007914 +.set CYDEV_PHUB_TDMEM35_BASE, 0x40007918 +.set CYDEV_PHUB_TDMEM35_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM35_ORIG_TD0, 0x40007918 +.set CYREG_PHUB_TDMEM35_ORIG_TD1, 0x4000791c +.set CYDEV_PHUB_TDMEM36_BASE, 0x40007920 +.set CYDEV_PHUB_TDMEM36_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM36_ORIG_TD0, 0x40007920 +.set CYREG_PHUB_TDMEM36_ORIG_TD1, 0x40007924 +.set CYDEV_PHUB_TDMEM37_BASE, 0x40007928 +.set CYDEV_PHUB_TDMEM37_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM37_ORIG_TD0, 0x40007928 +.set CYREG_PHUB_TDMEM37_ORIG_TD1, 0x4000792c +.set CYDEV_PHUB_TDMEM38_BASE, 0x40007930 +.set CYDEV_PHUB_TDMEM38_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM38_ORIG_TD0, 0x40007930 +.set CYREG_PHUB_TDMEM38_ORIG_TD1, 0x40007934 +.set CYDEV_PHUB_TDMEM39_BASE, 0x40007938 +.set CYDEV_PHUB_TDMEM39_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM39_ORIG_TD0, 0x40007938 +.set CYREG_PHUB_TDMEM39_ORIG_TD1, 0x4000793c +.set CYDEV_PHUB_TDMEM40_BASE, 0x40007940 +.set CYDEV_PHUB_TDMEM40_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM40_ORIG_TD0, 0x40007940 +.set CYREG_PHUB_TDMEM40_ORIG_TD1, 0x40007944 +.set CYDEV_PHUB_TDMEM41_BASE, 0x40007948 +.set CYDEV_PHUB_TDMEM41_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM41_ORIG_TD0, 0x40007948 +.set CYREG_PHUB_TDMEM41_ORIG_TD1, 0x4000794c +.set CYDEV_PHUB_TDMEM42_BASE, 0x40007950 +.set CYDEV_PHUB_TDMEM42_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM42_ORIG_TD0, 0x40007950 +.set CYREG_PHUB_TDMEM42_ORIG_TD1, 0x40007954 +.set CYDEV_PHUB_TDMEM43_BASE, 0x40007958 +.set CYDEV_PHUB_TDMEM43_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM43_ORIG_TD0, 0x40007958 +.set CYREG_PHUB_TDMEM43_ORIG_TD1, 0x4000795c +.set CYDEV_PHUB_TDMEM44_BASE, 0x40007960 +.set CYDEV_PHUB_TDMEM44_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM44_ORIG_TD0, 0x40007960 +.set CYREG_PHUB_TDMEM44_ORIG_TD1, 0x40007964 +.set CYDEV_PHUB_TDMEM45_BASE, 0x40007968 +.set CYDEV_PHUB_TDMEM45_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM45_ORIG_TD0, 0x40007968 +.set CYREG_PHUB_TDMEM45_ORIG_TD1, 0x4000796c +.set CYDEV_PHUB_TDMEM46_BASE, 0x40007970 +.set CYDEV_PHUB_TDMEM46_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM46_ORIG_TD0, 0x40007970 +.set CYREG_PHUB_TDMEM46_ORIG_TD1, 0x40007974 +.set CYDEV_PHUB_TDMEM47_BASE, 0x40007978 +.set CYDEV_PHUB_TDMEM47_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM47_ORIG_TD0, 0x40007978 +.set CYREG_PHUB_TDMEM47_ORIG_TD1, 0x4000797c +.set CYDEV_PHUB_TDMEM48_BASE, 0x40007980 +.set CYDEV_PHUB_TDMEM48_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM48_ORIG_TD0, 0x40007980 +.set CYREG_PHUB_TDMEM48_ORIG_TD1, 0x40007984 +.set CYDEV_PHUB_TDMEM49_BASE, 0x40007988 +.set CYDEV_PHUB_TDMEM49_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM49_ORIG_TD0, 0x40007988 +.set CYREG_PHUB_TDMEM49_ORIG_TD1, 0x4000798c +.set CYDEV_PHUB_TDMEM50_BASE, 0x40007990 +.set CYDEV_PHUB_TDMEM50_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM50_ORIG_TD0, 0x40007990 +.set CYREG_PHUB_TDMEM50_ORIG_TD1, 0x40007994 +.set CYDEV_PHUB_TDMEM51_BASE, 0x40007998 +.set CYDEV_PHUB_TDMEM51_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM51_ORIG_TD0, 0x40007998 +.set CYREG_PHUB_TDMEM51_ORIG_TD1, 0x4000799c +.set CYDEV_PHUB_TDMEM52_BASE, 0x400079a0 +.set CYDEV_PHUB_TDMEM52_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM52_ORIG_TD0, 0x400079a0 +.set CYREG_PHUB_TDMEM52_ORIG_TD1, 0x400079a4 +.set CYDEV_PHUB_TDMEM53_BASE, 0x400079a8 +.set CYDEV_PHUB_TDMEM53_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM53_ORIG_TD0, 0x400079a8 +.set CYREG_PHUB_TDMEM53_ORIG_TD1, 0x400079ac +.set CYDEV_PHUB_TDMEM54_BASE, 0x400079b0 +.set CYDEV_PHUB_TDMEM54_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM54_ORIG_TD0, 0x400079b0 +.set CYREG_PHUB_TDMEM54_ORIG_TD1, 0x400079b4 +.set CYDEV_PHUB_TDMEM55_BASE, 0x400079b8 +.set CYDEV_PHUB_TDMEM55_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM55_ORIG_TD0, 0x400079b8 +.set CYREG_PHUB_TDMEM55_ORIG_TD1, 0x400079bc +.set CYDEV_PHUB_TDMEM56_BASE, 0x400079c0 +.set CYDEV_PHUB_TDMEM56_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM56_ORIG_TD0, 0x400079c0 +.set CYREG_PHUB_TDMEM56_ORIG_TD1, 0x400079c4 +.set CYDEV_PHUB_TDMEM57_BASE, 0x400079c8 +.set CYDEV_PHUB_TDMEM57_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM57_ORIG_TD0, 0x400079c8 +.set CYREG_PHUB_TDMEM57_ORIG_TD1, 0x400079cc +.set CYDEV_PHUB_TDMEM58_BASE, 0x400079d0 +.set CYDEV_PHUB_TDMEM58_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM58_ORIG_TD0, 0x400079d0 +.set CYREG_PHUB_TDMEM58_ORIG_TD1, 0x400079d4 +.set CYDEV_PHUB_TDMEM59_BASE, 0x400079d8 +.set CYDEV_PHUB_TDMEM59_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM59_ORIG_TD0, 0x400079d8 +.set CYREG_PHUB_TDMEM59_ORIG_TD1, 0x400079dc +.set CYDEV_PHUB_TDMEM60_BASE, 0x400079e0 +.set CYDEV_PHUB_TDMEM60_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM60_ORIG_TD0, 0x400079e0 +.set CYREG_PHUB_TDMEM60_ORIG_TD1, 0x400079e4 +.set CYDEV_PHUB_TDMEM61_BASE, 0x400079e8 +.set CYDEV_PHUB_TDMEM61_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM61_ORIG_TD0, 0x400079e8 +.set CYREG_PHUB_TDMEM61_ORIG_TD1, 0x400079ec +.set CYDEV_PHUB_TDMEM62_BASE, 0x400079f0 +.set CYDEV_PHUB_TDMEM62_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM62_ORIG_TD0, 0x400079f0 +.set CYREG_PHUB_TDMEM62_ORIG_TD1, 0x400079f4 +.set CYDEV_PHUB_TDMEM63_BASE, 0x400079f8 +.set CYDEV_PHUB_TDMEM63_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM63_ORIG_TD0, 0x400079f8 +.set CYREG_PHUB_TDMEM63_ORIG_TD1, 0x400079fc +.set CYDEV_PHUB_TDMEM64_BASE, 0x40007a00 +.set CYDEV_PHUB_TDMEM64_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM64_ORIG_TD0, 0x40007a00 +.set CYREG_PHUB_TDMEM64_ORIG_TD1, 0x40007a04 +.set CYDEV_PHUB_TDMEM65_BASE, 0x40007a08 +.set CYDEV_PHUB_TDMEM65_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM65_ORIG_TD0, 0x40007a08 +.set CYREG_PHUB_TDMEM65_ORIG_TD1, 0x40007a0c +.set CYDEV_PHUB_TDMEM66_BASE, 0x40007a10 +.set CYDEV_PHUB_TDMEM66_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM66_ORIG_TD0, 0x40007a10 +.set CYREG_PHUB_TDMEM66_ORIG_TD1, 0x40007a14 +.set CYDEV_PHUB_TDMEM67_BASE, 0x40007a18 +.set CYDEV_PHUB_TDMEM67_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM67_ORIG_TD0, 0x40007a18 +.set CYREG_PHUB_TDMEM67_ORIG_TD1, 0x40007a1c +.set CYDEV_PHUB_TDMEM68_BASE, 0x40007a20 +.set CYDEV_PHUB_TDMEM68_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM68_ORIG_TD0, 0x40007a20 +.set CYREG_PHUB_TDMEM68_ORIG_TD1, 0x40007a24 +.set CYDEV_PHUB_TDMEM69_BASE, 0x40007a28 +.set CYDEV_PHUB_TDMEM69_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM69_ORIG_TD0, 0x40007a28 +.set CYREG_PHUB_TDMEM69_ORIG_TD1, 0x40007a2c +.set CYDEV_PHUB_TDMEM70_BASE, 0x40007a30 +.set CYDEV_PHUB_TDMEM70_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM70_ORIG_TD0, 0x40007a30 +.set CYREG_PHUB_TDMEM70_ORIG_TD1, 0x40007a34 +.set CYDEV_PHUB_TDMEM71_BASE, 0x40007a38 +.set CYDEV_PHUB_TDMEM71_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM71_ORIG_TD0, 0x40007a38 +.set CYREG_PHUB_TDMEM71_ORIG_TD1, 0x40007a3c +.set CYDEV_PHUB_TDMEM72_BASE, 0x40007a40 +.set CYDEV_PHUB_TDMEM72_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM72_ORIG_TD0, 0x40007a40 +.set CYREG_PHUB_TDMEM72_ORIG_TD1, 0x40007a44 +.set CYDEV_PHUB_TDMEM73_BASE, 0x40007a48 +.set CYDEV_PHUB_TDMEM73_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM73_ORIG_TD0, 0x40007a48 +.set CYREG_PHUB_TDMEM73_ORIG_TD1, 0x40007a4c +.set CYDEV_PHUB_TDMEM74_BASE, 0x40007a50 +.set CYDEV_PHUB_TDMEM74_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM74_ORIG_TD0, 0x40007a50 +.set CYREG_PHUB_TDMEM74_ORIG_TD1, 0x40007a54 +.set CYDEV_PHUB_TDMEM75_BASE, 0x40007a58 +.set CYDEV_PHUB_TDMEM75_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM75_ORIG_TD0, 0x40007a58 +.set CYREG_PHUB_TDMEM75_ORIG_TD1, 0x40007a5c +.set CYDEV_PHUB_TDMEM76_BASE, 0x40007a60 +.set CYDEV_PHUB_TDMEM76_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM76_ORIG_TD0, 0x40007a60 +.set CYREG_PHUB_TDMEM76_ORIG_TD1, 0x40007a64 +.set CYDEV_PHUB_TDMEM77_BASE, 0x40007a68 +.set CYDEV_PHUB_TDMEM77_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM77_ORIG_TD0, 0x40007a68 +.set CYREG_PHUB_TDMEM77_ORIG_TD1, 0x40007a6c +.set CYDEV_PHUB_TDMEM78_BASE, 0x40007a70 +.set CYDEV_PHUB_TDMEM78_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM78_ORIG_TD0, 0x40007a70 +.set CYREG_PHUB_TDMEM78_ORIG_TD1, 0x40007a74 +.set CYDEV_PHUB_TDMEM79_BASE, 0x40007a78 +.set CYDEV_PHUB_TDMEM79_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM79_ORIG_TD0, 0x40007a78 +.set CYREG_PHUB_TDMEM79_ORIG_TD1, 0x40007a7c +.set CYDEV_PHUB_TDMEM80_BASE, 0x40007a80 +.set CYDEV_PHUB_TDMEM80_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM80_ORIG_TD0, 0x40007a80 +.set CYREG_PHUB_TDMEM80_ORIG_TD1, 0x40007a84 +.set CYDEV_PHUB_TDMEM81_BASE, 0x40007a88 +.set CYDEV_PHUB_TDMEM81_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM81_ORIG_TD0, 0x40007a88 +.set CYREG_PHUB_TDMEM81_ORIG_TD1, 0x40007a8c +.set CYDEV_PHUB_TDMEM82_BASE, 0x40007a90 +.set CYDEV_PHUB_TDMEM82_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM82_ORIG_TD0, 0x40007a90 +.set CYREG_PHUB_TDMEM82_ORIG_TD1, 0x40007a94 +.set CYDEV_PHUB_TDMEM83_BASE, 0x40007a98 +.set CYDEV_PHUB_TDMEM83_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM83_ORIG_TD0, 0x40007a98 +.set CYREG_PHUB_TDMEM83_ORIG_TD1, 0x40007a9c +.set CYDEV_PHUB_TDMEM84_BASE, 0x40007aa0 +.set CYDEV_PHUB_TDMEM84_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM84_ORIG_TD0, 0x40007aa0 +.set CYREG_PHUB_TDMEM84_ORIG_TD1, 0x40007aa4 +.set CYDEV_PHUB_TDMEM85_BASE, 0x40007aa8 +.set CYDEV_PHUB_TDMEM85_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM85_ORIG_TD0, 0x40007aa8 +.set CYREG_PHUB_TDMEM85_ORIG_TD1, 0x40007aac +.set CYDEV_PHUB_TDMEM86_BASE, 0x40007ab0 +.set CYDEV_PHUB_TDMEM86_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM86_ORIG_TD0, 0x40007ab0 +.set CYREG_PHUB_TDMEM86_ORIG_TD1, 0x40007ab4 +.set CYDEV_PHUB_TDMEM87_BASE, 0x40007ab8 +.set CYDEV_PHUB_TDMEM87_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM87_ORIG_TD0, 0x40007ab8 +.set CYREG_PHUB_TDMEM87_ORIG_TD1, 0x40007abc +.set CYDEV_PHUB_TDMEM88_BASE, 0x40007ac0 +.set CYDEV_PHUB_TDMEM88_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM88_ORIG_TD0, 0x40007ac0 +.set CYREG_PHUB_TDMEM88_ORIG_TD1, 0x40007ac4 +.set CYDEV_PHUB_TDMEM89_BASE, 0x40007ac8 +.set CYDEV_PHUB_TDMEM89_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM89_ORIG_TD0, 0x40007ac8 +.set CYREG_PHUB_TDMEM89_ORIG_TD1, 0x40007acc +.set CYDEV_PHUB_TDMEM90_BASE, 0x40007ad0 +.set CYDEV_PHUB_TDMEM90_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM90_ORIG_TD0, 0x40007ad0 +.set CYREG_PHUB_TDMEM90_ORIG_TD1, 0x40007ad4 +.set CYDEV_PHUB_TDMEM91_BASE, 0x40007ad8 +.set CYDEV_PHUB_TDMEM91_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM91_ORIG_TD0, 0x40007ad8 +.set CYREG_PHUB_TDMEM91_ORIG_TD1, 0x40007adc +.set CYDEV_PHUB_TDMEM92_BASE, 0x40007ae0 +.set CYDEV_PHUB_TDMEM92_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM92_ORIG_TD0, 0x40007ae0 +.set CYREG_PHUB_TDMEM92_ORIG_TD1, 0x40007ae4 +.set CYDEV_PHUB_TDMEM93_BASE, 0x40007ae8 +.set CYDEV_PHUB_TDMEM93_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM93_ORIG_TD0, 0x40007ae8 +.set CYREG_PHUB_TDMEM93_ORIG_TD1, 0x40007aec +.set CYDEV_PHUB_TDMEM94_BASE, 0x40007af0 +.set CYDEV_PHUB_TDMEM94_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM94_ORIG_TD0, 0x40007af0 +.set CYREG_PHUB_TDMEM94_ORIG_TD1, 0x40007af4 +.set CYDEV_PHUB_TDMEM95_BASE, 0x40007af8 +.set CYDEV_PHUB_TDMEM95_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM95_ORIG_TD0, 0x40007af8 +.set CYREG_PHUB_TDMEM95_ORIG_TD1, 0x40007afc +.set CYDEV_PHUB_TDMEM96_BASE, 0x40007b00 +.set CYDEV_PHUB_TDMEM96_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM96_ORIG_TD0, 0x40007b00 +.set CYREG_PHUB_TDMEM96_ORIG_TD1, 0x40007b04 +.set CYDEV_PHUB_TDMEM97_BASE, 0x40007b08 +.set CYDEV_PHUB_TDMEM97_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM97_ORIG_TD0, 0x40007b08 +.set CYREG_PHUB_TDMEM97_ORIG_TD1, 0x40007b0c +.set CYDEV_PHUB_TDMEM98_BASE, 0x40007b10 +.set CYDEV_PHUB_TDMEM98_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM98_ORIG_TD0, 0x40007b10 +.set CYREG_PHUB_TDMEM98_ORIG_TD1, 0x40007b14 +.set CYDEV_PHUB_TDMEM99_BASE, 0x40007b18 +.set CYDEV_PHUB_TDMEM99_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM99_ORIG_TD0, 0x40007b18 +.set CYREG_PHUB_TDMEM99_ORIG_TD1, 0x40007b1c +.set CYDEV_PHUB_TDMEM100_BASE, 0x40007b20 +.set CYDEV_PHUB_TDMEM100_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM100_ORIG_TD0, 0x40007b20 +.set CYREG_PHUB_TDMEM100_ORIG_TD1, 0x40007b24 +.set CYDEV_PHUB_TDMEM101_BASE, 0x40007b28 +.set CYDEV_PHUB_TDMEM101_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM101_ORIG_TD0, 0x40007b28 +.set CYREG_PHUB_TDMEM101_ORIG_TD1, 0x40007b2c +.set CYDEV_PHUB_TDMEM102_BASE, 0x40007b30 +.set CYDEV_PHUB_TDMEM102_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM102_ORIG_TD0, 0x40007b30 +.set CYREG_PHUB_TDMEM102_ORIG_TD1, 0x40007b34 +.set CYDEV_PHUB_TDMEM103_BASE, 0x40007b38 +.set CYDEV_PHUB_TDMEM103_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM103_ORIG_TD0, 0x40007b38 +.set CYREG_PHUB_TDMEM103_ORIG_TD1, 0x40007b3c +.set CYDEV_PHUB_TDMEM104_BASE, 0x40007b40 +.set CYDEV_PHUB_TDMEM104_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM104_ORIG_TD0, 0x40007b40 +.set CYREG_PHUB_TDMEM104_ORIG_TD1, 0x40007b44 +.set CYDEV_PHUB_TDMEM105_BASE, 0x40007b48 +.set CYDEV_PHUB_TDMEM105_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM105_ORIG_TD0, 0x40007b48 +.set CYREG_PHUB_TDMEM105_ORIG_TD1, 0x40007b4c +.set CYDEV_PHUB_TDMEM106_BASE, 0x40007b50 +.set CYDEV_PHUB_TDMEM106_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM106_ORIG_TD0, 0x40007b50 +.set CYREG_PHUB_TDMEM106_ORIG_TD1, 0x40007b54 +.set CYDEV_PHUB_TDMEM107_BASE, 0x40007b58 +.set CYDEV_PHUB_TDMEM107_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM107_ORIG_TD0, 0x40007b58 +.set CYREG_PHUB_TDMEM107_ORIG_TD1, 0x40007b5c +.set CYDEV_PHUB_TDMEM108_BASE, 0x40007b60 +.set CYDEV_PHUB_TDMEM108_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM108_ORIG_TD0, 0x40007b60 +.set CYREG_PHUB_TDMEM108_ORIG_TD1, 0x40007b64 +.set CYDEV_PHUB_TDMEM109_BASE, 0x40007b68 +.set CYDEV_PHUB_TDMEM109_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM109_ORIG_TD0, 0x40007b68 +.set CYREG_PHUB_TDMEM109_ORIG_TD1, 0x40007b6c +.set CYDEV_PHUB_TDMEM110_BASE, 0x40007b70 +.set CYDEV_PHUB_TDMEM110_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM110_ORIG_TD0, 0x40007b70 +.set CYREG_PHUB_TDMEM110_ORIG_TD1, 0x40007b74 +.set CYDEV_PHUB_TDMEM111_BASE, 0x40007b78 +.set CYDEV_PHUB_TDMEM111_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM111_ORIG_TD0, 0x40007b78 +.set CYREG_PHUB_TDMEM111_ORIG_TD1, 0x40007b7c +.set CYDEV_PHUB_TDMEM112_BASE, 0x40007b80 +.set CYDEV_PHUB_TDMEM112_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM112_ORIG_TD0, 0x40007b80 +.set CYREG_PHUB_TDMEM112_ORIG_TD1, 0x40007b84 +.set CYDEV_PHUB_TDMEM113_BASE, 0x40007b88 +.set CYDEV_PHUB_TDMEM113_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM113_ORIG_TD0, 0x40007b88 +.set CYREG_PHUB_TDMEM113_ORIG_TD1, 0x40007b8c +.set CYDEV_PHUB_TDMEM114_BASE, 0x40007b90 +.set CYDEV_PHUB_TDMEM114_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM114_ORIG_TD0, 0x40007b90 +.set CYREG_PHUB_TDMEM114_ORIG_TD1, 0x40007b94 +.set CYDEV_PHUB_TDMEM115_BASE, 0x40007b98 +.set CYDEV_PHUB_TDMEM115_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM115_ORIG_TD0, 0x40007b98 +.set CYREG_PHUB_TDMEM115_ORIG_TD1, 0x40007b9c +.set CYDEV_PHUB_TDMEM116_BASE, 0x40007ba0 +.set CYDEV_PHUB_TDMEM116_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM116_ORIG_TD0, 0x40007ba0 +.set CYREG_PHUB_TDMEM116_ORIG_TD1, 0x40007ba4 +.set CYDEV_PHUB_TDMEM117_BASE, 0x40007ba8 +.set CYDEV_PHUB_TDMEM117_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM117_ORIG_TD0, 0x40007ba8 +.set CYREG_PHUB_TDMEM117_ORIG_TD1, 0x40007bac +.set CYDEV_PHUB_TDMEM118_BASE, 0x40007bb0 +.set CYDEV_PHUB_TDMEM118_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM118_ORIG_TD0, 0x40007bb0 +.set CYREG_PHUB_TDMEM118_ORIG_TD1, 0x40007bb4 +.set CYDEV_PHUB_TDMEM119_BASE, 0x40007bb8 +.set CYDEV_PHUB_TDMEM119_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM119_ORIG_TD0, 0x40007bb8 +.set CYREG_PHUB_TDMEM119_ORIG_TD1, 0x40007bbc +.set CYDEV_PHUB_TDMEM120_BASE, 0x40007bc0 +.set CYDEV_PHUB_TDMEM120_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM120_ORIG_TD0, 0x40007bc0 +.set CYREG_PHUB_TDMEM120_ORIG_TD1, 0x40007bc4 +.set CYDEV_PHUB_TDMEM121_BASE, 0x40007bc8 +.set CYDEV_PHUB_TDMEM121_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM121_ORIG_TD0, 0x40007bc8 +.set CYREG_PHUB_TDMEM121_ORIG_TD1, 0x40007bcc +.set CYDEV_PHUB_TDMEM122_BASE, 0x40007bd0 +.set CYDEV_PHUB_TDMEM122_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM122_ORIG_TD0, 0x40007bd0 +.set CYREG_PHUB_TDMEM122_ORIG_TD1, 0x40007bd4 +.set CYDEV_PHUB_TDMEM123_BASE, 0x40007bd8 +.set CYDEV_PHUB_TDMEM123_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM123_ORIG_TD0, 0x40007bd8 +.set CYREG_PHUB_TDMEM123_ORIG_TD1, 0x40007bdc +.set CYDEV_PHUB_TDMEM124_BASE, 0x40007be0 +.set CYDEV_PHUB_TDMEM124_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM124_ORIG_TD0, 0x40007be0 +.set CYREG_PHUB_TDMEM124_ORIG_TD1, 0x40007be4 +.set CYDEV_PHUB_TDMEM125_BASE, 0x40007be8 +.set CYDEV_PHUB_TDMEM125_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM125_ORIG_TD0, 0x40007be8 +.set CYREG_PHUB_TDMEM125_ORIG_TD1, 0x40007bec +.set CYDEV_PHUB_TDMEM126_BASE, 0x40007bf0 +.set CYDEV_PHUB_TDMEM126_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM126_ORIG_TD0, 0x40007bf0 +.set CYREG_PHUB_TDMEM126_ORIG_TD1, 0x40007bf4 +.set CYDEV_PHUB_TDMEM127_BASE, 0x40007bf8 +.set CYDEV_PHUB_TDMEM127_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM127_ORIG_TD0, 0x40007bf8 +.set CYREG_PHUB_TDMEM127_ORIG_TD1, 0x40007bfc +.set CYDEV_EE_BASE, 0x40008000 +.set CYDEV_EE_SIZE, 0x00000800 +.set CYREG_EE_DATA_MBASE, 0x40008000 +.set CYREG_EE_DATA_MSIZE, 0x00000800 +.set CYDEV_CAN0_BASE, 0x4000a000 +.set CYDEV_CAN0_SIZE, 0x000002a0 +.set CYDEV_CAN0_CSR_BASE, 0x4000a000 +.set CYDEV_CAN0_CSR_SIZE, 0x00000018 +.set CYREG_CAN0_CSR_INT_SR, 0x4000a000 +.set CYREG_CAN0_CSR_INT_EN, 0x4000a004 +.set CYREG_CAN0_CSR_BUF_SR, 0x4000a008 +.set CYREG_CAN0_CSR_ERR_SR, 0x4000a00c +.set CYREG_CAN0_CSR_CMD, 0x4000a010 +.set CYREG_CAN0_CSR_CFG, 0x4000a014 +.set CYDEV_CAN0_TX0_BASE, 0x4000a020 +.set CYDEV_CAN0_TX0_SIZE, 0x00000010 +.set CYREG_CAN0_TX0_CMD, 0x4000a020 +.set CYREG_CAN0_TX0_ID, 0x4000a024 +.set CYREG_CAN0_TX0_DH, 0x4000a028 +.set CYREG_CAN0_TX0_DL, 0x4000a02c +.set CYDEV_CAN0_TX1_BASE, 0x4000a030 +.set CYDEV_CAN0_TX1_SIZE, 0x00000010 +.set CYREG_CAN0_TX1_CMD, 0x4000a030 +.set CYREG_CAN0_TX1_ID, 0x4000a034 +.set CYREG_CAN0_TX1_DH, 0x4000a038 +.set CYREG_CAN0_TX1_DL, 0x4000a03c +.set CYDEV_CAN0_TX2_BASE, 0x4000a040 +.set CYDEV_CAN0_TX2_SIZE, 0x00000010 +.set CYREG_CAN0_TX2_CMD, 0x4000a040 +.set CYREG_CAN0_TX2_ID, 0x4000a044 +.set CYREG_CAN0_TX2_DH, 0x4000a048 +.set CYREG_CAN0_TX2_DL, 0x4000a04c +.set CYDEV_CAN0_TX3_BASE, 0x4000a050 +.set CYDEV_CAN0_TX3_SIZE, 0x00000010 +.set CYREG_CAN0_TX3_CMD, 0x4000a050 +.set CYREG_CAN0_TX3_ID, 0x4000a054 +.set CYREG_CAN0_TX3_DH, 0x4000a058 +.set CYREG_CAN0_TX3_DL, 0x4000a05c +.set CYDEV_CAN0_TX4_BASE, 0x4000a060 +.set CYDEV_CAN0_TX4_SIZE, 0x00000010 +.set CYREG_CAN0_TX4_CMD, 0x4000a060 +.set CYREG_CAN0_TX4_ID, 0x4000a064 +.set CYREG_CAN0_TX4_DH, 0x4000a068 +.set CYREG_CAN0_TX4_DL, 0x4000a06c +.set CYDEV_CAN0_TX5_BASE, 0x4000a070 +.set CYDEV_CAN0_TX5_SIZE, 0x00000010 +.set CYREG_CAN0_TX5_CMD, 0x4000a070 +.set CYREG_CAN0_TX5_ID, 0x4000a074 +.set CYREG_CAN0_TX5_DH, 0x4000a078 +.set CYREG_CAN0_TX5_DL, 0x4000a07c +.set CYDEV_CAN0_TX6_BASE, 0x4000a080 +.set CYDEV_CAN0_TX6_SIZE, 0x00000010 +.set CYREG_CAN0_TX6_CMD, 0x4000a080 +.set CYREG_CAN0_TX6_ID, 0x4000a084 +.set CYREG_CAN0_TX6_DH, 0x4000a088 +.set CYREG_CAN0_TX6_DL, 0x4000a08c +.set CYDEV_CAN0_TX7_BASE, 0x4000a090 +.set CYDEV_CAN0_TX7_SIZE, 0x00000010 +.set CYREG_CAN0_TX7_CMD, 0x4000a090 +.set CYREG_CAN0_TX7_ID, 0x4000a094 +.set CYREG_CAN0_TX7_DH, 0x4000a098 +.set CYREG_CAN0_TX7_DL, 0x4000a09c +.set CYDEV_CAN0_RX0_BASE, 0x4000a0a0 +.set CYDEV_CAN0_RX0_SIZE, 0x00000020 +.set CYREG_CAN0_RX0_CMD, 0x4000a0a0 +.set CYREG_CAN0_RX0_ID, 0x4000a0a4 +.set CYREG_CAN0_RX0_DH, 0x4000a0a8 +.set CYREG_CAN0_RX0_DL, 0x4000a0ac +.set CYREG_CAN0_RX0_AMR, 0x4000a0b0 +.set CYREG_CAN0_RX0_ACR, 0x4000a0b4 +.set CYREG_CAN0_RX0_AMRD, 0x4000a0b8 +.set CYREG_CAN0_RX0_ACRD, 0x4000a0bc +.set CYDEV_CAN0_RX1_BASE, 0x4000a0c0 +.set CYDEV_CAN0_RX1_SIZE, 0x00000020 +.set CYREG_CAN0_RX1_CMD, 0x4000a0c0 +.set CYREG_CAN0_RX1_ID, 0x4000a0c4 +.set CYREG_CAN0_RX1_DH, 0x4000a0c8 +.set CYREG_CAN0_RX1_DL, 0x4000a0cc +.set CYREG_CAN0_RX1_AMR, 0x4000a0d0 +.set CYREG_CAN0_RX1_ACR, 0x4000a0d4 +.set CYREG_CAN0_RX1_AMRD, 0x4000a0d8 +.set CYREG_CAN0_RX1_ACRD, 0x4000a0dc +.set CYDEV_CAN0_RX2_BASE, 0x4000a0e0 +.set CYDEV_CAN0_RX2_SIZE, 0x00000020 +.set CYREG_CAN0_RX2_CMD, 0x4000a0e0 +.set CYREG_CAN0_RX2_ID, 0x4000a0e4 +.set CYREG_CAN0_RX2_DH, 0x4000a0e8 +.set CYREG_CAN0_RX2_DL, 0x4000a0ec +.set CYREG_CAN0_RX2_AMR, 0x4000a0f0 +.set CYREG_CAN0_RX2_ACR, 0x4000a0f4 +.set CYREG_CAN0_RX2_AMRD, 0x4000a0f8 +.set CYREG_CAN0_RX2_ACRD, 0x4000a0fc +.set CYDEV_CAN0_RX3_BASE, 0x4000a100 +.set CYDEV_CAN0_RX3_SIZE, 0x00000020 +.set CYREG_CAN0_RX3_CMD, 0x4000a100 +.set CYREG_CAN0_RX3_ID, 0x4000a104 +.set CYREG_CAN0_RX3_DH, 0x4000a108 +.set CYREG_CAN0_RX3_DL, 0x4000a10c +.set CYREG_CAN0_RX3_AMR, 0x4000a110 +.set CYREG_CAN0_RX3_ACR, 0x4000a114 +.set CYREG_CAN0_RX3_AMRD, 0x4000a118 +.set CYREG_CAN0_RX3_ACRD, 0x4000a11c +.set CYDEV_CAN0_RX4_BASE, 0x4000a120 +.set CYDEV_CAN0_RX4_SIZE, 0x00000020 +.set CYREG_CAN0_RX4_CMD, 0x4000a120 +.set CYREG_CAN0_RX4_ID, 0x4000a124 +.set CYREG_CAN0_RX4_DH, 0x4000a128 +.set CYREG_CAN0_RX4_DL, 0x4000a12c +.set CYREG_CAN0_RX4_AMR, 0x4000a130 +.set CYREG_CAN0_RX4_ACR, 0x4000a134 +.set CYREG_CAN0_RX4_AMRD, 0x4000a138 +.set CYREG_CAN0_RX4_ACRD, 0x4000a13c +.set CYDEV_CAN0_RX5_BASE, 0x4000a140 +.set CYDEV_CAN0_RX5_SIZE, 0x00000020 +.set CYREG_CAN0_RX5_CMD, 0x4000a140 +.set CYREG_CAN0_RX5_ID, 0x4000a144 +.set CYREG_CAN0_RX5_DH, 0x4000a148 +.set CYREG_CAN0_RX5_DL, 0x4000a14c +.set CYREG_CAN0_RX5_AMR, 0x4000a150 +.set CYREG_CAN0_RX5_ACR, 0x4000a154 +.set CYREG_CAN0_RX5_AMRD, 0x4000a158 +.set CYREG_CAN0_RX5_ACRD, 0x4000a15c +.set CYDEV_CAN0_RX6_BASE, 0x4000a160 +.set CYDEV_CAN0_RX6_SIZE, 0x00000020 +.set CYREG_CAN0_RX6_CMD, 0x4000a160 +.set CYREG_CAN0_RX6_ID, 0x4000a164 +.set CYREG_CAN0_RX6_DH, 0x4000a168 +.set CYREG_CAN0_RX6_DL, 0x4000a16c +.set CYREG_CAN0_RX6_AMR, 0x4000a170 +.set CYREG_CAN0_RX6_ACR, 0x4000a174 +.set CYREG_CAN0_RX6_AMRD, 0x4000a178 +.set CYREG_CAN0_RX6_ACRD, 0x4000a17c +.set CYDEV_CAN0_RX7_BASE, 0x4000a180 +.set CYDEV_CAN0_RX7_SIZE, 0x00000020 +.set CYREG_CAN0_RX7_CMD, 0x4000a180 +.set CYREG_CAN0_RX7_ID, 0x4000a184 +.set CYREG_CAN0_RX7_DH, 0x4000a188 +.set CYREG_CAN0_RX7_DL, 0x4000a18c +.set CYREG_CAN0_RX7_AMR, 0x4000a190 +.set CYREG_CAN0_RX7_ACR, 0x4000a194 +.set CYREG_CAN0_RX7_AMRD, 0x4000a198 +.set CYREG_CAN0_RX7_ACRD, 0x4000a19c +.set CYDEV_CAN0_RX8_BASE, 0x4000a1a0 +.set CYDEV_CAN0_RX8_SIZE, 0x00000020 +.set CYREG_CAN0_RX8_CMD, 0x4000a1a0 +.set CYREG_CAN0_RX8_ID, 0x4000a1a4 +.set CYREG_CAN0_RX8_DH, 0x4000a1a8 +.set CYREG_CAN0_RX8_DL, 0x4000a1ac +.set CYREG_CAN0_RX8_AMR, 0x4000a1b0 +.set CYREG_CAN0_RX8_ACR, 0x4000a1b4 +.set CYREG_CAN0_RX8_AMRD, 0x4000a1b8 +.set CYREG_CAN0_RX8_ACRD, 0x4000a1bc +.set CYDEV_CAN0_RX9_BASE, 0x4000a1c0 +.set CYDEV_CAN0_RX9_SIZE, 0x00000020 +.set CYREG_CAN0_RX9_CMD, 0x4000a1c0 +.set CYREG_CAN0_RX9_ID, 0x4000a1c4 +.set CYREG_CAN0_RX9_DH, 0x4000a1c8 +.set CYREG_CAN0_RX9_DL, 0x4000a1cc +.set CYREG_CAN0_RX9_AMR, 0x4000a1d0 +.set CYREG_CAN0_RX9_ACR, 0x4000a1d4 +.set CYREG_CAN0_RX9_AMRD, 0x4000a1d8 +.set CYREG_CAN0_RX9_ACRD, 0x4000a1dc +.set CYDEV_CAN0_RX10_BASE, 0x4000a1e0 +.set CYDEV_CAN0_RX10_SIZE, 0x00000020 +.set CYREG_CAN0_RX10_CMD, 0x4000a1e0 +.set CYREG_CAN0_RX10_ID, 0x4000a1e4 +.set CYREG_CAN0_RX10_DH, 0x4000a1e8 +.set CYREG_CAN0_RX10_DL, 0x4000a1ec +.set CYREG_CAN0_RX10_AMR, 0x4000a1f0 +.set CYREG_CAN0_RX10_ACR, 0x4000a1f4 +.set CYREG_CAN0_RX10_AMRD, 0x4000a1f8 +.set CYREG_CAN0_RX10_ACRD, 0x4000a1fc +.set CYDEV_CAN0_RX11_BASE, 0x4000a200 +.set CYDEV_CAN0_RX11_SIZE, 0x00000020 +.set CYREG_CAN0_RX11_CMD, 0x4000a200 +.set CYREG_CAN0_RX11_ID, 0x4000a204 +.set CYREG_CAN0_RX11_DH, 0x4000a208 +.set CYREG_CAN0_RX11_DL, 0x4000a20c +.set CYREG_CAN0_RX11_AMR, 0x4000a210 +.set CYREG_CAN0_RX11_ACR, 0x4000a214 +.set CYREG_CAN0_RX11_AMRD, 0x4000a218 +.set CYREG_CAN0_RX11_ACRD, 0x4000a21c +.set CYDEV_CAN0_RX12_BASE, 0x4000a220 +.set CYDEV_CAN0_RX12_SIZE, 0x00000020 +.set CYREG_CAN0_RX12_CMD, 0x4000a220 +.set CYREG_CAN0_RX12_ID, 0x4000a224 +.set CYREG_CAN0_RX12_DH, 0x4000a228 +.set CYREG_CAN0_RX12_DL, 0x4000a22c +.set CYREG_CAN0_RX12_AMR, 0x4000a230 +.set CYREG_CAN0_RX12_ACR, 0x4000a234 +.set CYREG_CAN0_RX12_AMRD, 0x4000a238 +.set CYREG_CAN0_RX12_ACRD, 0x4000a23c +.set CYDEV_CAN0_RX13_BASE, 0x4000a240 +.set CYDEV_CAN0_RX13_SIZE, 0x00000020 +.set CYREG_CAN0_RX13_CMD, 0x4000a240 +.set CYREG_CAN0_RX13_ID, 0x4000a244 +.set CYREG_CAN0_RX13_DH, 0x4000a248 +.set CYREG_CAN0_RX13_DL, 0x4000a24c +.set CYREG_CAN0_RX13_AMR, 0x4000a250 +.set CYREG_CAN0_RX13_ACR, 0x4000a254 +.set CYREG_CAN0_RX13_AMRD, 0x4000a258 +.set CYREG_CAN0_RX13_ACRD, 0x4000a25c +.set CYDEV_CAN0_RX14_BASE, 0x4000a260 +.set CYDEV_CAN0_RX14_SIZE, 0x00000020 +.set CYREG_CAN0_RX14_CMD, 0x4000a260 +.set CYREG_CAN0_RX14_ID, 0x4000a264 +.set CYREG_CAN0_RX14_DH, 0x4000a268 +.set CYREG_CAN0_RX14_DL, 0x4000a26c +.set CYREG_CAN0_RX14_AMR, 0x4000a270 +.set CYREG_CAN0_RX14_ACR, 0x4000a274 +.set CYREG_CAN0_RX14_AMRD, 0x4000a278 +.set CYREG_CAN0_RX14_ACRD, 0x4000a27c +.set CYDEV_CAN0_RX15_BASE, 0x4000a280 +.set CYDEV_CAN0_RX15_SIZE, 0x00000020 +.set CYREG_CAN0_RX15_CMD, 0x4000a280 +.set CYREG_CAN0_RX15_ID, 0x4000a284 +.set CYREG_CAN0_RX15_DH, 0x4000a288 +.set CYREG_CAN0_RX15_DL, 0x4000a28c +.set CYREG_CAN0_RX15_AMR, 0x4000a290 +.set CYREG_CAN0_RX15_ACR, 0x4000a294 +.set CYREG_CAN0_RX15_AMRD, 0x4000a298 +.set CYREG_CAN0_RX15_ACRD, 0x4000a29c +.set CYDEV_DFB0_BASE, 0x4000c000 +.set CYDEV_DFB0_SIZE, 0x000007b5 +.set CYDEV_DFB0_DPA_SRAM_BASE, 0x4000c000 +.set CYDEV_DFB0_DPA_SRAM_SIZE, 0x00000200 +.set CYREG_DFB0_DPA_SRAM_DATA_MBASE, 0x4000c000 +.set CYREG_DFB0_DPA_SRAM_DATA_MSIZE, 0x00000200 +.set CYDEV_DFB0_DPB_SRAM_BASE, 0x4000c200 +.set CYDEV_DFB0_DPB_SRAM_SIZE, 0x00000200 +.set CYREG_DFB0_DPB_SRAM_DATA_MBASE, 0x4000c200 +.set CYREG_DFB0_DPB_SRAM_DATA_MSIZE, 0x00000200 +.set CYDEV_DFB0_CSA_SRAM_BASE, 0x4000c400 +.set CYDEV_DFB0_CSA_SRAM_SIZE, 0x00000100 +.set CYREG_DFB0_CSA_SRAM_DATA_MBASE, 0x4000c400 +.set CYREG_DFB0_CSA_SRAM_DATA_MSIZE, 0x00000100 +.set CYDEV_DFB0_CSB_SRAM_BASE, 0x4000c500 +.set CYDEV_DFB0_CSB_SRAM_SIZE, 0x00000100 +.set CYREG_DFB0_CSB_SRAM_DATA_MBASE, 0x4000c500 +.set CYREG_DFB0_CSB_SRAM_DATA_MSIZE, 0x00000100 +.set CYDEV_DFB0_FSM_SRAM_BASE, 0x4000c600 +.set CYDEV_DFB0_FSM_SRAM_SIZE, 0x00000100 +.set CYREG_DFB0_FSM_SRAM_DATA_MBASE, 0x4000c600 +.set CYREG_DFB0_FSM_SRAM_DATA_MSIZE, 0x00000100 +.set CYDEV_DFB0_ACU_SRAM_BASE, 0x4000c700 +.set CYDEV_DFB0_ACU_SRAM_SIZE, 0x00000040 +.set CYREG_DFB0_ACU_SRAM_DATA_MBASE, 0x4000c700 +.set CYREG_DFB0_ACU_SRAM_DATA_MSIZE, 0x00000040 +.set CYREG_DFB0_CR, 0x4000c780 +.set CYREG_DFB0_SR, 0x4000c784 +.set CYREG_DFB0_RAM_EN, 0x4000c788 +.set CYREG_DFB0_RAM_DIR, 0x4000c78c +.set CYREG_DFB0_SEMA, 0x4000c790 +.set CYREG_DFB0_DSI_CTRL, 0x4000c794 +.set CYREG_DFB0_INT_CTRL, 0x4000c798 +.set CYREG_DFB0_DMA_CTRL, 0x4000c79c +.set CYREG_DFB0_STAGEA, 0x4000c7a0 +.set CYREG_DFB0_STAGEAM, 0x4000c7a1 +.set CYREG_DFB0_STAGEAH, 0x4000c7a2 +.set CYREG_DFB0_STAGEB, 0x4000c7a4 +.set CYREG_DFB0_STAGEBM, 0x4000c7a5 +.set CYREG_DFB0_STAGEBH, 0x4000c7a6 +.set CYREG_DFB0_HOLDA, 0x4000c7a8 +.set CYREG_DFB0_HOLDAM, 0x4000c7a9 +.set CYREG_DFB0_HOLDAH, 0x4000c7aa +.set CYREG_DFB0_HOLDAS, 0x4000c7ab +.set CYREG_DFB0_HOLDB, 0x4000c7ac +.set CYREG_DFB0_HOLDBM, 0x4000c7ad +.set CYREG_DFB0_HOLDBH, 0x4000c7ae +.set CYREG_DFB0_HOLDBS, 0x4000c7af +.set CYREG_DFB0_COHER, 0x4000c7b0 +.set CYREG_DFB0_DALIGN, 0x4000c7b4 +.set CYDEV_UCFG_BASE, 0x40010000 +.set CYDEV_UCFG_SIZE, 0x00005040 +.set CYDEV_UCFG_B0_BASE, 0x40010000 +.set CYDEV_UCFG_B0_SIZE, 0x00000fef +.set CYDEV_UCFG_B0_P0_BASE, 0x40010000 +.set CYDEV_UCFG_B0_P0_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P0_U0_BASE, 0x40010000 +.set CYDEV_UCFG_B0_P0_U0_SIZE, 0x00000070 +.set CYREG_B0_P0_U0_PLD_IT0, 0x40010000 +.set CYREG_B0_P0_U0_PLD_IT1, 0x40010004 +.set CYREG_B0_P0_U0_PLD_IT2, 0x40010008 +.set CYREG_B0_P0_U0_PLD_IT3, 0x4001000c +.set CYREG_B0_P0_U0_PLD_IT4, 0x40010010 +.set CYREG_B0_P0_U0_PLD_IT5, 0x40010014 +.set CYREG_B0_P0_U0_PLD_IT6, 0x40010018 +.set CYREG_B0_P0_U0_PLD_IT7, 0x4001001c +.set CYREG_B0_P0_U0_PLD_IT8, 0x40010020 +.set CYREG_B0_P0_U0_PLD_IT9, 0x40010024 +.set CYREG_B0_P0_U0_PLD_IT10, 0x40010028 +.set CYREG_B0_P0_U0_PLD_IT11, 0x4001002c +.set CYREG_B0_P0_U0_PLD_ORT0, 0x40010030 +.set CYREG_B0_P0_U0_PLD_ORT1, 0x40010032 +.set CYREG_B0_P0_U0_PLD_ORT2, 0x40010034 +.set CYREG_B0_P0_U0_PLD_ORT3, 0x40010036 +.set CYREG_B0_P0_U0_MC_CFG_CEN_CONST, 0x40010038 +.set CYREG_B0_P0_U0_MC_CFG_XORFB, 0x4001003a +.set CYREG_B0_P0_U0_MC_CFG_SET_RESET, 0x4001003c +.set CYREG_B0_P0_U0_MC_CFG_BYPASS, 0x4001003e +.set CYREG_B0_P0_U0_CFG0, 0x40010040 +.set CYREG_B0_P0_U0_CFG1, 0x40010041 +.set CYREG_B0_P0_U0_CFG2, 0x40010042 +.set CYREG_B0_P0_U0_CFG3, 0x40010043 +.set CYREG_B0_P0_U0_CFG4, 0x40010044 +.set CYREG_B0_P0_U0_CFG5, 0x40010045 +.set CYREG_B0_P0_U0_CFG6, 0x40010046 +.set CYREG_B0_P0_U0_CFG7, 0x40010047 +.set CYREG_B0_P0_U0_CFG8, 0x40010048 +.set CYREG_B0_P0_U0_CFG9, 0x40010049 +.set CYREG_B0_P0_U0_CFG10, 0x4001004a +.set CYREG_B0_P0_U0_CFG11, 0x4001004b +.set CYREG_B0_P0_U0_CFG12, 0x4001004c +.set CYREG_B0_P0_U0_CFG13, 0x4001004d +.set CYREG_B0_P0_U0_CFG14, 0x4001004e +.set CYREG_B0_P0_U0_CFG15, 0x4001004f +.set CYREG_B0_P0_U0_CFG16, 0x40010050 +.set CYREG_B0_P0_U0_CFG17, 0x40010051 +.set CYREG_B0_P0_U0_CFG18, 0x40010052 +.set CYREG_B0_P0_U0_CFG19, 0x40010053 +.set CYREG_B0_P0_U0_CFG20, 0x40010054 +.set CYREG_B0_P0_U0_CFG21, 0x40010055 +.set CYREG_B0_P0_U0_CFG22, 0x40010056 +.set CYREG_B0_P0_U0_CFG23, 0x40010057 +.set CYREG_B0_P0_U0_CFG24, 0x40010058 +.set CYREG_B0_P0_U0_CFG25, 0x40010059 +.set CYREG_B0_P0_U0_CFG26, 0x4001005a +.set CYREG_B0_P0_U0_CFG27, 0x4001005b +.set CYREG_B0_P0_U0_CFG28, 0x4001005c +.set CYREG_B0_P0_U0_CFG29, 0x4001005d +.set CYREG_B0_P0_U0_CFG30, 0x4001005e +.set CYREG_B0_P0_U0_CFG31, 0x4001005f +.set CYREG_B0_P0_U0_DCFG0, 0x40010060 +.set CYREG_B0_P0_U0_DCFG1, 0x40010062 +.set CYREG_B0_P0_U0_DCFG2, 0x40010064 +.set CYREG_B0_P0_U0_DCFG3, 0x40010066 +.set CYREG_B0_P0_U0_DCFG4, 0x40010068 +.set CYREG_B0_P0_U0_DCFG5, 0x4001006a +.set CYREG_B0_P0_U0_DCFG6, 0x4001006c +.set CYREG_B0_P0_U0_DCFG7, 0x4001006e +.set CYDEV_UCFG_B0_P0_U1_BASE, 0x40010080 +.set CYDEV_UCFG_B0_P0_U1_SIZE, 0x00000070 +.set CYREG_B0_P0_U1_PLD_IT0, 0x40010080 +.set CYREG_B0_P0_U1_PLD_IT1, 0x40010084 +.set CYREG_B0_P0_U1_PLD_IT2, 0x40010088 +.set CYREG_B0_P0_U1_PLD_IT3, 0x4001008c +.set CYREG_B0_P0_U1_PLD_IT4, 0x40010090 +.set CYREG_B0_P0_U1_PLD_IT5, 0x40010094 +.set CYREG_B0_P0_U1_PLD_IT6, 0x40010098 +.set CYREG_B0_P0_U1_PLD_IT7, 0x4001009c +.set CYREG_B0_P0_U1_PLD_IT8, 0x400100a0 +.set CYREG_B0_P0_U1_PLD_IT9, 0x400100a4 +.set CYREG_B0_P0_U1_PLD_IT10, 0x400100a8 +.set CYREG_B0_P0_U1_PLD_IT11, 0x400100ac +.set CYREG_B0_P0_U1_PLD_ORT0, 0x400100b0 +.set CYREG_B0_P0_U1_PLD_ORT1, 0x400100b2 +.set CYREG_B0_P0_U1_PLD_ORT2, 0x400100b4 +.set CYREG_B0_P0_U1_PLD_ORT3, 0x400100b6 +.set CYREG_B0_P0_U1_MC_CFG_CEN_CONST, 0x400100b8 +.set CYREG_B0_P0_U1_MC_CFG_XORFB, 0x400100ba +.set CYREG_B0_P0_U1_MC_CFG_SET_RESET, 0x400100bc +.set CYREG_B0_P0_U1_MC_CFG_BYPASS, 0x400100be +.set CYREG_B0_P0_U1_CFG0, 0x400100c0 +.set CYREG_B0_P0_U1_CFG1, 0x400100c1 +.set CYREG_B0_P0_U1_CFG2, 0x400100c2 +.set CYREG_B0_P0_U1_CFG3, 0x400100c3 +.set CYREG_B0_P0_U1_CFG4, 0x400100c4 +.set CYREG_B0_P0_U1_CFG5, 0x400100c5 +.set CYREG_B0_P0_U1_CFG6, 0x400100c6 +.set CYREG_B0_P0_U1_CFG7, 0x400100c7 +.set CYREG_B0_P0_U1_CFG8, 0x400100c8 +.set CYREG_B0_P0_U1_CFG9, 0x400100c9 +.set CYREG_B0_P0_U1_CFG10, 0x400100ca +.set CYREG_B0_P0_U1_CFG11, 0x400100cb +.set CYREG_B0_P0_U1_CFG12, 0x400100cc +.set CYREG_B0_P0_U1_CFG13, 0x400100cd +.set CYREG_B0_P0_U1_CFG14, 0x400100ce +.set CYREG_B0_P0_U1_CFG15, 0x400100cf +.set CYREG_B0_P0_U1_CFG16, 0x400100d0 +.set CYREG_B0_P0_U1_CFG17, 0x400100d1 +.set CYREG_B0_P0_U1_CFG18, 0x400100d2 +.set CYREG_B0_P0_U1_CFG19, 0x400100d3 +.set CYREG_B0_P0_U1_CFG20, 0x400100d4 +.set CYREG_B0_P0_U1_CFG21, 0x400100d5 +.set CYREG_B0_P0_U1_CFG22, 0x400100d6 +.set CYREG_B0_P0_U1_CFG23, 0x400100d7 +.set CYREG_B0_P0_U1_CFG24, 0x400100d8 +.set CYREG_B0_P0_U1_CFG25, 0x400100d9 +.set CYREG_B0_P0_U1_CFG26, 0x400100da +.set CYREG_B0_P0_U1_CFG27, 0x400100db +.set CYREG_B0_P0_U1_CFG28, 0x400100dc +.set CYREG_B0_P0_U1_CFG29, 0x400100dd +.set CYREG_B0_P0_U1_CFG30, 0x400100de +.set CYREG_B0_P0_U1_CFG31, 0x400100df +.set CYREG_B0_P0_U1_DCFG0, 0x400100e0 +.set CYREG_B0_P0_U1_DCFG1, 0x400100e2 +.set CYREG_B0_P0_U1_DCFG2, 0x400100e4 +.set CYREG_B0_P0_U1_DCFG3, 0x400100e6 +.set CYREG_B0_P0_U1_DCFG4, 0x400100e8 +.set CYREG_B0_P0_U1_DCFG5, 0x400100ea +.set CYREG_B0_P0_U1_DCFG6, 0x400100ec +.set CYREG_B0_P0_U1_DCFG7, 0x400100ee +.set CYDEV_UCFG_B0_P0_ROUTE_BASE, 0x40010100 +.set CYDEV_UCFG_B0_P0_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P1_BASE, 0x40010200 +.set CYDEV_UCFG_B0_P1_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P1_U0_BASE, 0x40010200 +.set CYDEV_UCFG_B0_P1_U0_SIZE, 0x00000070 +.set CYREG_B0_P1_U0_PLD_IT0, 0x40010200 +.set CYREG_B0_P1_U0_PLD_IT1, 0x40010204 +.set CYREG_B0_P1_U0_PLD_IT2, 0x40010208 +.set CYREG_B0_P1_U0_PLD_IT3, 0x4001020c +.set CYREG_B0_P1_U0_PLD_IT4, 0x40010210 +.set CYREG_B0_P1_U0_PLD_IT5, 0x40010214 +.set CYREG_B0_P1_U0_PLD_IT6, 0x40010218 +.set CYREG_B0_P1_U0_PLD_IT7, 0x4001021c +.set CYREG_B0_P1_U0_PLD_IT8, 0x40010220 +.set CYREG_B0_P1_U0_PLD_IT9, 0x40010224 +.set CYREG_B0_P1_U0_PLD_IT10, 0x40010228 +.set CYREG_B0_P1_U0_PLD_IT11, 0x4001022c +.set CYREG_B0_P1_U0_PLD_ORT0, 0x40010230 +.set CYREG_B0_P1_U0_PLD_ORT1, 0x40010232 +.set CYREG_B0_P1_U0_PLD_ORT2, 0x40010234 +.set CYREG_B0_P1_U0_PLD_ORT3, 0x40010236 +.set CYREG_B0_P1_U0_MC_CFG_CEN_CONST, 0x40010238 +.set CYREG_B0_P1_U0_MC_CFG_XORFB, 0x4001023a +.set CYREG_B0_P1_U0_MC_CFG_SET_RESET, 0x4001023c +.set CYREG_B0_P1_U0_MC_CFG_BYPASS, 0x4001023e +.set CYREG_B0_P1_U0_CFG0, 0x40010240 +.set CYREG_B0_P1_U0_CFG1, 0x40010241 +.set CYREG_B0_P1_U0_CFG2, 0x40010242 +.set CYREG_B0_P1_U0_CFG3, 0x40010243 +.set CYREG_B0_P1_U0_CFG4, 0x40010244 +.set CYREG_B0_P1_U0_CFG5, 0x40010245 +.set CYREG_B0_P1_U0_CFG6, 0x40010246 +.set CYREG_B0_P1_U0_CFG7, 0x40010247 +.set CYREG_B0_P1_U0_CFG8, 0x40010248 +.set CYREG_B0_P1_U0_CFG9, 0x40010249 +.set CYREG_B0_P1_U0_CFG10, 0x4001024a +.set CYREG_B0_P1_U0_CFG11, 0x4001024b +.set CYREG_B0_P1_U0_CFG12, 0x4001024c +.set CYREG_B0_P1_U0_CFG13, 0x4001024d +.set CYREG_B0_P1_U0_CFG14, 0x4001024e +.set CYREG_B0_P1_U0_CFG15, 0x4001024f +.set CYREG_B0_P1_U0_CFG16, 0x40010250 +.set CYREG_B0_P1_U0_CFG17, 0x40010251 +.set CYREG_B0_P1_U0_CFG18, 0x40010252 +.set CYREG_B0_P1_U0_CFG19, 0x40010253 +.set CYREG_B0_P1_U0_CFG20, 0x40010254 +.set CYREG_B0_P1_U0_CFG21, 0x40010255 +.set CYREG_B0_P1_U0_CFG22, 0x40010256 +.set CYREG_B0_P1_U0_CFG23, 0x40010257 +.set CYREG_B0_P1_U0_CFG24, 0x40010258 +.set CYREG_B0_P1_U0_CFG25, 0x40010259 +.set CYREG_B0_P1_U0_CFG26, 0x4001025a +.set CYREG_B0_P1_U0_CFG27, 0x4001025b +.set CYREG_B0_P1_U0_CFG28, 0x4001025c +.set CYREG_B0_P1_U0_CFG29, 0x4001025d +.set CYREG_B0_P1_U0_CFG30, 0x4001025e +.set CYREG_B0_P1_U0_CFG31, 0x4001025f +.set CYREG_B0_P1_U0_DCFG0, 0x40010260 +.set CYREG_B0_P1_U0_DCFG1, 0x40010262 +.set CYREG_B0_P1_U0_DCFG2, 0x40010264 +.set CYREG_B0_P1_U0_DCFG3, 0x40010266 +.set CYREG_B0_P1_U0_DCFG4, 0x40010268 +.set CYREG_B0_P1_U0_DCFG5, 0x4001026a +.set CYREG_B0_P1_U0_DCFG6, 0x4001026c +.set CYREG_B0_P1_U0_DCFG7, 0x4001026e +.set CYDEV_UCFG_B0_P1_U1_BASE, 0x40010280 +.set CYDEV_UCFG_B0_P1_U1_SIZE, 0x00000070 +.set CYREG_B0_P1_U1_PLD_IT0, 0x40010280 +.set CYREG_B0_P1_U1_PLD_IT1, 0x40010284 +.set CYREG_B0_P1_U1_PLD_IT2, 0x40010288 +.set CYREG_B0_P1_U1_PLD_IT3, 0x4001028c +.set CYREG_B0_P1_U1_PLD_IT4, 0x40010290 +.set CYREG_B0_P1_U1_PLD_IT5, 0x40010294 +.set CYREG_B0_P1_U1_PLD_IT6, 0x40010298 +.set CYREG_B0_P1_U1_PLD_IT7, 0x4001029c +.set CYREG_B0_P1_U1_PLD_IT8, 0x400102a0 +.set CYREG_B0_P1_U1_PLD_IT9, 0x400102a4 +.set CYREG_B0_P1_U1_PLD_IT10, 0x400102a8 +.set CYREG_B0_P1_U1_PLD_IT11, 0x400102ac +.set CYREG_B0_P1_U1_PLD_ORT0, 0x400102b0 +.set CYREG_B0_P1_U1_PLD_ORT1, 0x400102b2 +.set CYREG_B0_P1_U1_PLD_ORT2, 0x400102b4 +.set CYREG_B0_P1_U1_PLD_ORT3, 0x400102b6 +.set CYREG_B0_P1_U1_MC_CFG_CEN_CONST, 0x400102b8 +.set CYREG_B0_P1_U1_MC_CFG_XORFB, 0x400102ba +.set CYREG_B0_P1_U1_MC_CFG_SET_RESET, 0x400102bc +.set CYREG_B0_P1_U1_MC_CFG_BYPASS, 0x400102be +.set CYREG_B0_P1_U1_CFG0, 0x400102c0 +.set CYREG_B0_P1_U1_CFG1, 0x400102c1 +.set CYREG_B0_P1_U1_CFG2, 0x400102c2 +.set CYREG_B0_P1_U1_CFG3, 0x400102c3 +.set CYREG_B0_P1_U1_CFG4, 0x400102c4 +.set CYREG_B0_P1_U1_CFG5, 0x400102c5 +.set CYREG_B0_P1_U1_CFG6, 0x400102c6 +.set CYREG_B0_P1_U1_CFG7, 0x400102c7 +.set CYREG_B0_P1_U1_CFG8, 0x400102c8 +.set CYREG_B0_P1_U1_CFG9, 0x400102c9 +.set CYREG_B0_P1_U1_CFG10, 0x400102ca +.set CYREG_B0_P1_U1_CFG11, 0x400102cb +.set CYREG_B0_P1_U1_CFG12, 0x400102cc +.set CYREG_B0_P1_U1_CFG13, 0x400102cd +.set CYREG_B0_P1_U1_CFG14, 0x400102ce +.set CYREG_B0_P1_U1_CFG15, 0x400102cf +.set CYREG_B0_P1_U1_CFG16, 0x400102d0 +.set CYREG_B0_P1_U1_CFG17, 0x400102d1 +.set CYREG_B0_P1_U1_CFG18, 0x400102d2 +.set CYREG_B0_P1_U1_CFG19, 0x400102d3 +.set CYREG_B0_P1_U1_CFG20, 0x400102d4 +.set CYREG_B0_P1_U1_CFG21, 0x400102d5 +.set CYREG_B0_P1_U1_CFG22, 0x400102d6 +.set CYREG_B0_P1_U1_CFG23, 0x400102d7 +.set CYREG_B0_P1_U1_CFG24, 0x400102d8 +.set CYREG_B0_P1_U1_CFG25, 0x400102d9 +.set CYREG_B0_P1_U1_CFG26, 0x400102da +.set CYREG_B0_P1_U1_CFG27, 0x400102db +.set CYREG_B0_P1_U1_CFG28, 0x400102dc +.set CYREG_B0_P1_U1_CFG29, 0x400102dd +.set CYREG_B0_P1_U1_CFG30, 0x400102de +.set CYREG_B0_P1_U1_CFG31, 0x400102df +.set CYREG_B0_P1_U1_DCFG0, 0x400102e0 +.set CYREG_B0_P1_U1_DCFG1, 0x400102e2 +.set CYREG_B0_P1_U1_DCFG2, 0x400102e4 +.set CYREG_B0_P1_U1_DCFG3, 0x400102e6 +.set CYREG_B0_P1_U1_DCFG4, 0x400102e8 +.set CYREG_B0_P1_U1_DCFG5, 0x400102ea +.set CYREG_B0_P1_U1_DCFG6, 0x400102ec +.set CYREG_B0_P1_U1_DCFG7, 0x400102ee +.set CYDEV_UCFG_B0_P1_ROUTE_BASE, 0x40010300 +.set CYDEV_UCFG_B0_P1_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P2_BASE, 0x40010400 +.set CYDEV_UCFG_B0_P2_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P2_U0_BASE, 0x40010400 +.set CYDEV_UCFG_B0_P2_U0_SIZE, 0x00000070 +.set CYREG_B0_P2_U0_PLD_IT0, 0x40010400 +.set CYREG_B0_P2_U0_PLD_IT1, 0x40010404 +.set CYREG_B0_P2_U0_PLD_IT2, 0x40010408 +.set CYREG_B0_P2_U0_PLD_IT3, 0x4001040c +.set CYREG_B0_P2_U0_PLD_IT4, 0x40010410 +.set CYREG_B0_P2_U0_PLD_IT5, 0x40010414 +.set CYREG_B0_P2_U0_PLD_IT6, 0x40010418 +.set CYREG_B0_P2_U0_PLD_IT7, 0x4001041c +.set CYREG_B0_P2_U0_PLD_IT8, 0x40010420 +.set CYREG_B0_P2_U0_PLD_IT9, 0x40010424 +.set CYREG_B0_P2_U0_PLD_IT10, 0x40010428 +.set CYREG_B0_P2_U0_PLD_IT11, 0x4001042c +.set CYREG_B0_P2_U0_PLD_ORT0, 0x40010430 +.set CYREG_B0_P2_U0_PLD_ORT1, 0x40010432 +.set CYREG_B0_P2_U0_PLD_ORT2, 0x40010434 +.set CYREG_B0_P2_U0_PLD_ORT3, 0x40010436 +.set CYREG_B0_P2_U0_MC_CFG_CEN_CONST, 0x40010438 +.set CYREG_B0_P2_U0_MC_CFG_XORFB, 0x4001043a +.set CYREG_B0_P2_U0_MC_CFG_SET_RESET, 0x4001043c +.set CYREG_B0_P2_U0_MC_CFG_BYPASS, 0x4001043e +.set CYREG_B0_P2_U0_CFG0, 0x40010440 +.set CYREG_B0_P2_U0_CFG1, 0x40010441 +.set CYREG_B0_P2_U0_CFG2, 0x40010442 +.set CYREG_B0_P2_U0_CFG3, 0x40010443 +.set CYREG_B0_P2_U0_CFG4, 0x40010444 +.set CYREG_B0_P2_U0_CFG5, 0x40010445 +.set CYREG_B0_P2_U0_CFG6, 0x40010446 +.set CYREG_B0_P2_U0_CFG7, 0x40010447 +.set CYREG_B0_P2_U0_CFG8, 0x40010448 +.set CYREG_B0_P2_U0_CFG9, 0x40010449 +.set CYREG_B0_P2_U0_CFG10, 0x4001044a +.set CYREG_B0_P2_U0_CFG11, 0x4001044b +.set CYREG_B0_P2_U0_CFG12, 0x4001044c +.set CYREG_B0_P2_U0_CFG13, 0x4001044d +.set CYREG_B0_P2_U0_CFG14, 0x4001044e +.set CYREG_B0_P2_U0_CFG15, 0x4001044f +.set CYREG_B0_P2_U0_CFG16, 0x40010450 +.set CYREG_B0_P2_U0_CFG17, 0x40010451 +.set CYREG_B0_P2_U0_CFG18, 0x40010452 +.set CYREG_B0_P2_U0_CFG19, 0x40010453 +.set CYREG_B0_P2_U0_CFG20, 0x40010454 +.set CYREG_B0_P2_U0_CFG21, 0x40010455 +.set CYREG_B0_P2_U0_CFG22, 0x40010456 +.set CYREG_B0_P2_U0_CFG23, 0x40010457 +.set CYREG_B0_P2_U0_CFG24, 0x40010458 +.set CYREG_B0_P2_U0_CFG25, 0x40010459 +.set CYREG_B0_P2_U0_CFG26, 0x4001045a +.set CYREG_B0_P2_U0_CFG27, 0x4001045b +.set CYREG_B0_P2_U0_CFG28, 0x4001045c +.set CYREG_B0_P2_U0_CFG29, 0x4001045d +.set CYREG_B0_P2_U0_CFG30, 0x4001045e +.set CYREG_B0_P2_U0_CFG31, 0x4001045f +.set CYREG_B0_P2_U0_DCFG0, 0x40010460 +.set CYREG_B0_P2_U0_DCFG1, 0x40010462 +.set CYREG_B0_P2_U0_DCFG2, 0x40010464 +.set CYREG_B0_P2_U0_DCFG3, 0x40010466 +.set CYREG_B0_P2_U0_DCFG4, 0x40010468 +.set CYREG_B0_P2_U0_DCFG5, 0x4001046a +.set CYREG_B0_P2_U0_DCFG6, 0x4001046c +.set CYREG_B0_P2_U0_DCFG7, 0x4001046e +.set CYDEV_UCFG_B0_P2_U1_BASE, 0x40010480 +.set CYDEV_UCFG_B0_P2_U1_SIZE, 0x00000070 +.set CYREG_B0_P2_U1_PLD_IT0, 0x40010480 +.set CYREG_B0_P2_U1_PLD_IT1, 0x40010484 +.set CYREG_B0_P2_U1_PLD_IT2, 0x40010488 +.set CYREG_B0_P2_U1_PLD_IT3, 0x4001048c +.set CYREG_B0_P2_U1_PLD_IT4, 0x40010490 +.set CYREG_B0_P2_U1_PLD_IT5, 0x40010494 +.set CYREG_B0_P2_U1_PLD_IT6, 0x40010498 +.set CYREG_B0_P2_U1_PLD_IT7, 0x4001049c +.set CYREG_B0_P2_U1_PLD_IT8, 0x400104a0 +.set CYREG_B0_P2_U1_PLD_IT9, 0x400104a4 +.set CYREG_B0_P2_U1_PLD_IT10, 0x400104a8 +.set CYREG_B0_P2_U1_PLD_IT11, 0x400104ac +.set CYREG_B0_P2_U1_PLD_ORT0, 0x400104b0 +.set CYREG_B0_P2_U1_PLD_ORT1, 0x400104b2 +.set CYREG_B0_P2_U1_PLD_ORT2, 0x400104b4 +.set CYREG_B0_P2_U1_PLD_ORT3, 0x400104b6 +.set CYREG_B0_P2_U1_MC_CFG_CEN_CONST, 0x400104b8 +.set CYREG_B0_P2_U1_MC_CFG_XORFB, 0x400104ba +.set CYREG_B0_P2_U1_MC_CFG_SET_RESET, 0x400104bc +.set CYREG_B0_P2_U1_MC_CFG_BYPASS, 0x400104be +.set CYREG_B0_P2_U1_CFG0, 0x400104c0 +.set CYREG_B0_P2_U1_CFG1, 0x400104c1 +.set CYREG_B0_P2_U1_CFG2, 0x400104c2 +.set CYREG_B0_P2_U1_CFG3, 0x400104c3 +.set CYREG_B0_P2_U1_CFG4, 0x400104c4 +.set CYREG_B0_P2_U1_CFG5, 0x400104c5 +.set CYREG_B0_P2_U1_CFG6, 0x400104c6 +.set CYREG_B0_P2_U1_CFG7, 0x400104c7 +.set CYREG_B0_P2_U1_CFG8, 0x400104c8 +.set CYREG_B0_P2_U1_CFG9, 0x400104c9 +.set CYREG_B0_P2_U1_CFG10, 0x400104ca +.set CYREG_B0_P2_U1_CFG11, 0x400104cb +.set CYREG_B0_P2_U1_CFG12, 0x400104cc +.set CYREG_B0_P2_U1_CFG13, 0x400104cd +.set CYREG_B0_P2_U1_CFG14, 0x400104ce +.set CYREG_B0_P2_U1_CFG15, 0x400104cf +.set CYREG_B0_P2_U1_CFG16, 0x400104d0 +.set CYREG_B0_P2_U1_CFG17, 0x400104d1 +.set CYREG_B0_P2_U1_CFG18, 0x400104d2 +.set CYREG_B0_P2_U1_CFG19, 0x400104d3 +.set CYREG_B0_P2_U1_CFG20, 0x400104d4 +.set CYREG_B0_P2_U1_CFG21, 0x400104d5 +.set CYREG_B0_P2_U1_CFG22, 0x400104d6 +.set CYREG_B0_P2_U1_CFG23, 0x400104d7 +.set CYREG_B0_P2_U1_CFG24, 0x400104d8 +.set CYREG_B0_P2_U1_CFG25, 0x400104d9 +.set CYREG_B0_P2_U1_CFG26, 0x400104da +.set CYREG_B0_P2_U1_CFG27, 0x400104db +.set CYREG_B0_P2_U1_CFG28, 0x400104dc +.set CYREG_B0_P2_U1_CFG29, 0x400104dd +.set CYREG_B0_P2_U1_CFG30, 0x400104de +.set CYREG_B0_P2_U1_CFG31, 0x400104df +.set CYREG_B0_P2_U1_DCFG0, 0x400104e0 +.set CYREG_B0_P2_U1_DCFG1, 0x400104e2 +.set CYREG_B0_P2_U1_DCFG2, 0x400104e4 +.set CYREG_B0_P2_U1_DCFG3, 0x400104e6 +.set CYREG_B0_P2_U1_DCFG4, 0x400104e8 +.set CYREG_B0_P2_U1_DCFG5, 0x400104ea +.set CYREG_B0_P2_U1_DCFG6, 0x400104ec +.set CYREG_B0_P2_U1_DCFG7, 0x400104ee +.set CYDEV_UCFG_B0_P2_ROUTE_BASE, 0x40010500 +.set CYDEV_UCFG_B0_P2_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P3_BASE, 0x40010600 +.set CYDEV_UCFG_B0_P3_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P3_U0_BASE, 0x40010600 +.set CYDEV_UCFG_B0_P3_U0_SIZE, 0x00000070 +.set CYREG_B0_P3_U0_PLD_IT0, 0x40010600 +.set CYREG_B0_P3_U0_PLD_IT1, 0x40010604 +.set CYREG_B0_P3_U0_PLD_IT2, 0x40010608 +.set CYREG_B0_P3_U0_PLD_IT3, 0x4001060c +.set CYREG_B0_P3_U0_PLD_IT4, 0x40010610 +.set CYREG_B0_P3_U0_PLD_IT5, 0x40010614 +.set CYREG_B0_P3_U0_PLD_IT6, 0x40010618 +.set CYREG_B0_P3_U0_PLD_IT7, 0x4001061c +.set CYREG_B0_P3_U0_PLD_IT8, 0x40010620 +.set CYREG_B0_P3_U0_PLD_IT9, 0x40010624 +.set CYREG_B0_P3_U0_PLD_IT10, 0x40010628 +.set CYREG_B0_P3_U0_PLD_IT11, 0x4001062c +.set CYREG_B0_P3_U0_PLD_ORT0, 0x40010630 +.set CYREG_B0_P3_U0_PLD_ORT1, 0x40010632 +.set CYREG_B0_P3_U0_PLD_ORT2, 0x40010634 +.set CYREG_B0_P3_U0_PLD_ORT3, 0x40010636 +.set CYREG_B0_P3_U0_MC_CFG_CEN_CONST, 0x40010638 +.set CYREG_B0_P3_U0_MC_CFG_XORFB, 0x4001063a +.set CYREG_B0_P3_U0_MC_CFG_SET_RESET, 0x4001063c +.set CYREG_B0_P3_U0_MC_CFG_BYPASS, 0x4001063e +.set CYREG_B0_P3_U0_CFG0, 0x40010640 +.set CYREG_B0_P3_U0_CFG1, 0x40010641 +.set CYREG_B0_P3_U0_CFG2, 0x40010642 +.set CYREG_B0_P3_U0_CFG3, 0x40010643 +.set CYREG_B0_P3_U0_CFG4, 0x40010644 +.set CYREG_B0_P3_U0_CFG5, 0x40010645 +.set CYREG_B0_P3_U0_CFG6, 0x40010646 +.set CYREG_B0_P3_U0_CFG7, 0x40010647 +.set CYREG_B0_P3_U0_CFG8, 0x40010648 +.set CYREG_B0_P3_U0_CFG9, 0x40010649 +.set CYREG_B0_P3_U0_CFG10, 0x4001064a +.set CYREG_B0_P3_U0_CFG11, 0x4001064b +.set CYREG_B0_P3_U0_CFG12, 0x4001064c +.set CYREG_B0_P3_U0_CFG13, 0x4001064d +.set CYREG_B0_P3_U0_CFG14, 0x4001064e +.set CYREG_B0_P3_U0_CFG15, 0x4001064f +.set CYREG_B0_P3_U0_CFG16, 0x40010650 +.set CYREG_B0_P3_U0_CFG17, 0x40010651 +.set CYREG_B0_P3_U0_CFG18, 0x40010652 +.set CYREG_B0_P3_U0_CFG19, 0x40010653 +.set CYREG_B0_P3_U0_CFG20, 0x40010654 +.set CYREG_B0_P3_U0_CFG21, 0x40010655 +.set CYREG_B0_P3_U0_CFG22, 0x40010656 +.set CYREG_B0_P3_U0_CFG23, 0x40010657 +.set CYREG_B0_P3_U0_CFG24, 0x40010658 +.set CYREG_B0_P3_U0_CFG25, 0x40010659 +.set CYREG_B0_P3_U0_CFG26, 0x4001065a +.set CYREG_B0_P3_U0_CFG27, 0x4001065b +.set CYREG_B0_P3_U0_CFG28, 0x4001065c +.set CYREG_B0_P3_U0_CFG29, 0x4001065d +.set CYREG_B0_P3_U0_CFG30, 0x4001065e +.set CYREG_B0_P3_U0_CFG31, 0x4001065f +.set CYREG_B0_P3_U0_DCFG0, 0x40010660 +.set CYREG_B0_P3_U0_DCFG1, 0x40010662 +.set CYREG_B0_P3_U0_DCFG2, 0x40010664 +.set CYREG_B0_P3_U0_DCFG3, 0x40010666 +.set CYREG_B0_P3_U0_DCFG4, 0x40010668 +.set CYREG_B0_P3_U0_DCFG5, 0x4001066a +.set CYREG_B0_P3_U0_DCFG6, 0x4001066c +.set CYREG_B0_P3_U0_DCFG7, 0x4001066e +.set CYDEV_UCFG_B0_P3_U1_BASE, 0x40010680 +.set CYDEV_UCFG_B0_P3_U1_SIZE, 0x00000070 +.set CYREG_B0_P3_U1_PLD_IT0, 0x40010680 +.set CYREG_B0_P3_U1_PLD_IT1, 0x40010684 +.set CYREG_B0_P3_U1_PLD_IT2, 0x40010688 +.set CYREG_B0_P3_U1_PLD_IT3, 0x4001068c +.set CYREG_B0_P3_U1_PLD_IT4, 0x40010690 +.set CYREG_B0_P3_U1_PLD_IT5, 0x40010694 +.set CYREG_B0_P3_U1_PLD_IT6, 0x40010698 +.set CYREG_B0_P3_U1_PLD_IT7, 0x4001069c +.set CYREG_B0_P3_U1_PLD_IT8, 0x400106a0 +.set CYREG_B0_P3_U1_PLD_IT9, 0x400106a4 +.set CYREG_B0_P3_U1_PLD_IT10, 0x400106a8 +.set CYREG_B0_P3_U1_PLD_IT11, 0x400106ac +.set CYREG_B0_P3_U1_PLD_ORT0, 0x400106b0 +.set CYREG_B0_P3_U1_PLD_ORT1, 0x400106b2 +.set CYREG_B0_P3_U1_PLD_ORT2, 0x400106b4 +.set CYREG_B0_P3_U1_PLD_ORT3, 0x400106b6 +.set CYREG_B0_P3_U1_MC_CFG_CEN_CONST, 0x400106b8 +.set CYREG_B0_P3_U1_MC_CFG_XORFB, 0x400106ba +.set CYREG_B0_P3_U1_MC_CFG_SET_RESET, 0x400106bc +.set CYREG_B0_P3_U1_MC_CFG_BYPASS, 0x400106be +.set CYREG_B0_P3_U1_CFG0, 0x400106c0 +.set CYREG_B0_P3_U1_CFG1, 0x400106c1 +.set CYREG_B0_P3_U1_CFG2, 0x400106c2 +.set CYREG_B0_P3_U1_CFG3, 0x400106c3 +.set CYREG_B0_P3_U1_CFG4, 0x400106c4 +.set CYREG_B0_P3_U1_CFG5, 0x400106c5 +.set CYREG_B0_P3_U1_CFG6, 0x400106c6 +.set CYREG_B0_P3_U1_CFG7, 0x400106c7 +.set CYREG_B0_P3_U1_CFG8, 0x400106c8 +.set CYREG_B0_P3_U1_CFG9, 0x400106c9 +.set CYREG_B0_P3_U1_CFG10, 0x400106ca +.set CYREG_B0_P3_U1_CFG11, 0x400106cb +.set CYREG_B0_P3_U1_CFG12, 0x400106cc +.set CYREG_B0_P3_U1_CFG13, 0x400106cd +.set CYREG_B0_P3_U1_CFG14, 0x400106ce +.set CYREG_B0_P3_U1_CFG15, 0x400106cf +.set CYREG_B0_P3_U1_CFG16, 0x400106d0 +.set CYREG_B0_P3_U1_CFG17, 0x400106d1 +.set CYREG_B0_P3_U1_CFG18, 0x400106d2 +.set CYREG_B0_P3_U1_CFG19, 0x400106d3 +.set CYREG_B0_P3_U1_CFG20, 0x400106d4 +.set CYREG_B0_P3_U1_CFG21, 0x400106d5 +.set CYREG_B0_P3_U1_CFG22, 0x400106d6 +.set CYREG_B0_P3_U1_CFG23, 0x400106d7 +.set CYREG_B0_P3_U1_CFG24, 0x400106d8 +.set CYREG_B0_P3_U1_CFG25, 0x400106d9 +.set CYREG_B0_P3_U1_CFG26, 0x400106da +.set CYREG_B0_P3_U1_CFG27, 0x400106db +.set CYREG_B0_P3_U1_CFG28, 0x400106dc +.set CYREG_B0_P3_U1_CFG29, 0x400106dd +.set CYREG_B0_P3_U1_CFG30, 0x400106de +.set CYREG_B0_P3_U1_CFG31, 0x400106df +.set CYREG_B0_P3_U1_DCFG0, 0x400106e0 +.set CYREG_B0_P3_U1_DCFG1, 0x400106e2 +.set CYREG_B0_P3_U1_DCFG2, 0x400106e4 +.set CYREG_B0_P3_U1_DCFG3, 0x400106e6 +.set CYREG_B0_P3_U1_DCFG4, 0x400106e8 +.set CYREG_B0_P3_U1_DCFG5, 0x400106ea +.set CYREG_B0_P3_U1_DCFG6, 0x400106ec +.set CYREG_B0_P3_U1_DCFG7, 0x400106ee +.set CYDEV_UCFG_B0_P3_ROUTE_BASE, 0x40010700 +.set CYDEV_UCFG_B0_P3_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P4_BASE, 0x40010800 +.set CYDEV_UCFG_B0_P4_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P4_U0_BASE, 0x40010800 +.set CYDEV_UCFG_B0_P4_U0_SIZE, 0x00000070 +.set CYREG_B0_P4_U0_PLD_IT0, 0x40010800 +.set CYREG_B0_P4_U0_PLD_IT1, 0x40010804 +.set CYREG_B0_P4_U0_PLD_IT2, 0x40010808 +.set CYREG_B0_P4_U0_PLD_IT3, 0x4001080c +.set CYREG_B0_P4_U0_PLD_IT4, 0x40010810 +.set CYREG_B0_P4_U0_PLD_IT5, 0x40010814 +.set CYREG_B0_P4_U0_PLD_IT6, 0x40010818 +.set CYREG_B0_P4_U0_PLD_IT7, 0x4001081c +.set CYREG_B0_P4_U0_PLD_IT8, 0x40010820 +.set CYREG_B0_P4_U0_PLD_IT9, 0x40010824 +.set CYREG_B0_P4_U0_PLD_IT10, 0x40010828 +.set CYREG_B0_P4_U0_PLD_IT11, 0x4001082c +.set CYREG_B0_P4_U0_PLD_ORT0, 0x40010830 +.set CYREG_B0_P4_U0_PLD_ORT1, 0x40010832 +.set CYREG_B0_P4_U0_PLD_ORT2, 0x40010834 +.set CYREG_B0_P4_U0_PLD_ORT3, 0x40010836 +.set CYREG_B0_P4_U0_MC_CFG_CEN_CONST, 0x40010838 +.set CYREG_B0_P4_U0_MC_CFG_XORFB, 0x4001083a +.set CYREG_B0_P4_U0_MC_CFG_SET_RESET, 0x4001083c +.set CYREG_B0_P4_U0_MC_CFG_BYPASS, 0x4001083e +.set CYREG_B0_P4_U0_CFG0, 0x40010840 +.set CYREG_B0_P4_U0_CFG1, 0x40010841 +.set CYREG_B0_P4_U0_CFG2, 0x40010842 +.set CYREG_B0_P4_U0_CFG3, 0x40010843 +.set CYREG_B0_P4_U0_CFG4, 0x40010844 +.set CYREG_B0_P4_U0_CFG5, 0x40010845 +.set CYREG_B0_P4_U0_CFG6, 0x40010846 +.set CYREG_B0_P4_U0_CFG7, 0x40010847 +.set CYREG_B0_P4_U0_CFG8, 0x40010848 +.set CYREG_B0_P4_U0_CFG9, 0x40010849 +.set CYREG_B0_P4_U0_CFG10, 0x4001084a +.set CYREG_B0_P4_U0_CFG11, 0x4001084b +.set CYREG_B0_P4_U0_CFG12, 0x4001084c +.set CYREG_B0_P4_U0_CFG13, 0x4001084d +.set CYREG_B0_P4_U0_CFG14, 0x4001084e +.set CYREG_B0_P4_U0_CFG15, 0x4001084f +.set CYREG_B0_P4_U0_CFG16, 0x40010850 +.set CYREG_B0_P4_U0_CFG17, 0x40010851 +.set CYREG_B0_P4_U0_CFG18, 0x40010852 +.set CYREG_B0_P4_U0_CFG19, 0x40010853 +.set CYREG_B0_P4_U0_CFG20, 0x40010854 +.set CYREG_B0_P4_U0_CFG21, 0x40010855 +.set CYREG_B0_P4_U0_CFG22, 0x40010856 +.set CYREG_B0_P4_U0_CFG23, 0x40010857 +.set CYREG_B0_P4_U0_CFG24, 0x40010858 +.set CYREG_B0_P4_U0_CFG25, 0x40010859 +.set CYREG_B0_P4_U0_CFG26, 0x4001085a +.set CYREG_B0_P4_U0_CFG27, 0x4001085b +.set CYREG_B0_P4_U0_CFG28, 0x4001085c +.set CYREG_B0_P4_U0_CFG29, 0x4001085d +.set CYREG_B0_P4_U0_CFG30, 0x4001085e +.set CYREG_B0_P4_U0_CFG31, 0x4001085f +.set CYREG_B0_P4_U0_DCFG0, 0x40010860 +.set CYREG_B0_P4_U0_DCFG1, 0x40010862 +.set CYREG_B0_P4_U0_DCFG2, 0x40010864 +.set CYREG_B0_P4_U0_DCFG3, 0x40010866 +.set CYREG_B0_P4_U0_DCFG4, 0x40010868 +.set CYREG_B0_P4_U0_DCFG5, 0x4001086a +.set CYREG_B0_P4_U0_DCFG6, 0x4001086c +.set CYREG_B0_P4_U0_DCFG7, 0x4001086e +.set CYDEV_UCFG_B0_P4_U1_BASE, 0x40010880 +.set CYDEV_UCFG_B0_P4_U1_SIZE, 0x00000070 +.set CYREG_B0_P4_U1_PLD_IT0, 0x40010880 +.set CYREG_B0_P4_U1_PLD_IT1, 0x40010884 +.set CYREG_B0_P4_U1_PLD_IT2, 0x40010888 +.set CYREG_B0_P4_U1_PLD_IT3, 0x4001088c +.set CYREG_B0_P4_U1_PLD_IT4, 0x40010890 +.set CYREG_B0_P4_U1_PLD_IT5, 0x40010894 +.set CYREG_B0_P4_U1_PLD_IT6, 0x40010898 +.set CYREG_B0_P4_U1_PLD_IT7, 0x4001089c +.set CYREG_B0_P4_U1_PLD_IT8, 0x400108a0 +.set CYREG_B0_P4_U1_PLD_IT9, 0x400108a4 +.set CYREG_B0_P4_U1_PLD_IT10, 0x400108a8 +.set CYREG_B0_P4_U1_PLD_IT11, 0x400108ac +.set CYREG_B0_P4_U1_PLD_ORT0, 0x400108b0 +.set CYREG_B0_P4_U1_PLD_ORT1, 0x400108b2 +.set CYREG_B0_P4_U1_PLD_ORT2, 0x400108b4 +.set CYREG_B0_P4_U1_PLD_ORT3, 0x400108b6 +.set CYREG_B0_P4_U1_MC_CFG_CEN_CONST, 0x400108b8 +.set CYREG_B0_P4_U1_MC_CFG_XORFB, 0x400108ba +.set CYREG_B0_P4_U1_MC_CFG_SET_RESET, 0x400108bc +.set CYREG_B0_P4_U1_MC_CFG_BYPASS, 0x400108be +.set CYREG_B0_P4_U1_CFG0, 0x400108c0 +.set CYREG_B0_P4_U1_CFG1, 0x400108c1 +.set CYREG_B0_P4_U1_CFG2, 0x400108c2 +.set CYREG_B0_P4_U1_CFG3, 0x400108c3 +.set CYREG_B0_P4_U1_CFG4, 0x400108c4 +.set CYREG_B0_P4_U1_CFG5, 0x400108c5 +.set CYREG_B0_P4_U1_CFG6, 0x400108c6 +.set CYREG_B0_P4_U1_CFG7, 0x400108c7 +.set CYREG_B0_P4_U1_CFG8, 0x400108c8 +.set CYREG_B0_P4_U1_CFG9, 0x400108c9 +.set CYREG_B0_P4_U1_CFG10, 0x400108ca +.set CYREG_B0_P4_U1_CFG11, 0x400108cb +.set CYREG_B0_P4_U1_CFG12, 0x400108cc +.set CYREG_B0_P4_U1_CFG13, 0x400108cd +.set CYREG_B0_P4_U1_CFG14, 0x400108ce +.set CYREG_B0_P4_U1_CFG15, 0x400108cf +.set CYREG_B0_P4_U1_CFG16, 0x400108d0 +.set CYREG_B0_P4_U1_CFG17, 0x400108d1 +.set CYREG_B0_P4_U1_CFG18, 0x400108d2 +.set CYREG_B0_P4_U1_CFG19, 0x400108d3 +.set CYREG_B0_P4_U1_CFG20, 0x400108d4 +.set CYREG_B0_P4_U1_CFG21, 0x400108d5 +.set CYREG_B0_P4_U1_CFG22, 0x400108d6 +.set CYREG_B0_P4_U1_CFG23, 0x400108d7 +.set CYREG_B0_P4_U1_CFG24, 0x400108d8 +.set CYREG_B0_P4_U1_CFG25, 0x400108d9 +.set CYREG_B0_P4_U1_CFG26, 0x400108da +.set CYREG_B0_P4_U1_CFG27, 0x400108db +.set CYREG_B0_P4_U1_CFG28, 0x400108dc +.set CYREG_B0_P4_U1_CFG29, 0x400108dd +.set CYREG_B0_P4_U1_CFG30, 0x400108de +.set CYREG_B0_P4_U1_CFG31, 0x400108df +.set CYREG_B0_P4_U1_DCFG0, 0x400108e0 +.set CYREG_B0_P4_U1_DCFG1, 0x400108e2 +.set CYREG_B0_P4_U1_DCFG2, 0x400108e4 +.set CYREG_B0_P4_U1_DCFG3, 0x400108e6 +.set CYREG_B0_P4_U1_DCFG4, 0x400108e8 +.set CYREG_B0_P4_U1_DCFG5, 0x400108ea +.set CYREG_B0_P4_U1_DCFG6, 0x400108ec +.set CYREG_B0_P4_U1_DCFG7, 0x400108ee +.set CYDEV_UCFG_B0_P4_ROUTE_BASE, 0x40010900 +.set CYDEV_UCFG_B0_P4_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P5_BASE, 0x40010a00 +.set CYDEV_UCFG_B0_P5_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P5_U0_BASE, 0x40010a00 +.set CYDEV_UCFG_B0_P5_U0_SIZE, 0x00000070 +.set CYREG_B0_P5_U0_PLD_IT0, 0x40010a00 +.set CYREG_B0_P5_U0_PLD_IT1, 0x40010a04 +.set CYREG_B0_P5_U0_PLD_IT2, 0x40010a08 +.set CYREG_B0_P5_U0_PLD_IT3, 0x40010a0c +.set CYREG_B0_P5_U0_PLD_IT4, 0x40010a10 +.set CYREG_B0_P5_U0_PLD_IT5, 0x40010a14 +.set CYREG_B0_P5_U0_PLD_IT6, 0x40010a18 +.set CYREG_B0_P5_U0_PLD_IT7, 0x40010a1c +.set CYREG_B0_P5_U0_PLD_IT8, 0x40010a20 +.set CYREG_B0_P5_U0_PLD_IT9, 0x40010a24 +.set CYREG_B0_P5_U0_PLD_IT10, 0x40010a28 +.set CYREG_B0_P5_U0_PLD_IT11, 0x40010a2c +.set CYREG_B0_P5_U0_PLD_ORT0, 0x40010a30 +.set CYREG_B0_P5_U0_PLD_ORT1, 0x40010a32 +.set CYREG_B0_P5_U0_PLD_ORT2, 0x40010a34 +.set CYREG_B0_P5_U0_PLD_ORT3, 0x40010a36 +.set CYREG_B0_P5_U0_MC_CFG_CEN_CONST, 0x40010a38 +.set CYREG_B0_P5_U0_MC_CFG_XORFB, 0x40010a3a +.set CYREG_B0_P5_U0_MC_CFG_SET_RESET, 0x40010a3c +.set CYREG_B0_P5_U0_MC_CFG_BYPASS, 0x40010a3e +.set CYREG_B0_P5_U0_CFG0, 0x40010a40 +.set CYREG_B0_P5_U0_CFG1, 0x40010a41 +.set CYREG_B0_P5_U0_CFG2, 0x40010a42 +.set CYREG_B0_P5_U0_CFG3, 0x40010a43 +.set CYREG_B0_P5_U0_CFG4, 0x40010a44 +.set CYREG_B0_P5_U0_CFG5, 0x40010a45 +.set CYREG_B0_P5_U0_CFG6, 0x40010a46 +.set CYREG_B0_P5_U0_CFG7, 0x40010a47 +.set CYREG_B0_P5_U0_CFG8, 0x40010a48 +.set CYREG_B0_P5_U0_CFG9, 0x40010a49 +.set CYREG_B0_P5_U0_CFG10, 0x40010a4a +.set CYREG_B0_P5_U0_CFG11, 0x40010a4b +.set CYREG_B0_P5_U0_CFG12, 0x40010a4c +.set CYREG_B0_P5_U0_CFG13, 0x40010a4d +.set CYREG_B0_P5_U0_CFG14, 0x40010a4e +.set CYREG_B0_P5_U0_CFG15, 0x40010a4f +.set CYREG_B0_P5_U0_CFG16, 0x40010a50 +.set CYREG_B0_P5_U0_CFG17, 0x40010a51 +.set CYREG_B0_P5_U0_CFG18, 0x40010a52 +.set CYREG_B0_P5_U0_CFG19, 0x40010a53 +.set CYREG_B0_P5_U0_CFG20, 0x40010a54 +.set CYREG_B0_P5_U0_CFG21, 0x40010a55 +.set CYREG_B0_P5_U0_CFG22, 0x40010a56 +.set CYREG_B0_P5_U0_CFG23, 0x40010a57 +.set CYREG_B0_P5_U0_CFG24, 0x40010a58 +.set CYREG_B0_P5_U0_CFG25, 0x40010a59 +.set CYREG_B0_P5_U0_CFG26, 0x40010a5a +.set CYREG_B0_P5_U0_CFG27, 0x40010a5b +.set CYREG_B0_P5_U0_CFG28, 0x40010a5c +.set CYREG_B0_P5_U0_CFG29, 0x40010a5d +.set CYREG_B0_P5_U0_CFG30, 0x40010a5e +.set CYREG_B0_P5_U0_CFG31, 0x40010a5f +.set CYREG_B0_P5_U0_DCFG0, 0x40010a60 +.set CYREG_B0_P5_U0_DCFG1, 0x40010a62 +.set CYREG_B0_P5_U0_DCFG2, 0x40010a64 +.set CYREG_B0_P5_U0_DCFG3, 0x40010a66 +.set CYREG_B0_P5_U0_DCFG4, 0x40010a68 +.set CYREG_B0_P5_U0_DCFG5, 0x40010a6a +.set CYREG_B0_P5_U0_DCFG6, 0x40010a6c +.set CYREG_B0_P5_U0_DCFG7, 0x40010a6e +.set CYDEV_UCFG_B0_P5_U1_BASE, 0x40010a80 +.set CYDEV_UCFG_B0_P5_U1_SIZE, 0x00000070 +.set CYREG_B0_P5_U1_PLD_IT0, 0x40010a80 +.set CYREG_B0_P5_U1_PLD_IT1, 0x40010a84 +.set CYREG_B0_P5_U1_PLD_IT2, 0x40010a88 +.set CYREG_B0_P5_U1_PLD_IT3, 0x40010a8c +.set CYREG_B0_P5_U1_PLD_IT4, 0x40010a90 +.set CYREG_B0_P5_U1_PLD_IT5, 0x40010a94 +.set CYREG_B0_P5_U1_PLD_IT6, 0x40010a98 +.set CYREG_B0_P5_U1_PLD_IT7, 0x40010a9c +.set CYREG_B0_P5_U1_PLD_IT8, 0x40010aa0 +.set CYREG_B0_P5_U1_PLD_IT9, 0x40010aa4 +.set CYREG_B0_P5_U1_PLD_IT10, 0x40010aa8 +.set CYREG_B0_P5_U1_PLD_IT11, 0x40010aac +.set CYREG_B0_P5_U1_PLD_ORT0, 0x40010ab0 +.set CYREG_B0_P5_U1_PLD_ORT1, 0x40010ab2 +.set CYREG_B0_P5_U1_PLD_ORT2, 0x40010ab4 +.set CYREG_B0_P5_U1_PLD_ORT3, 0x40010ab6 +.set CYREG_B0_P5_U1_MC_CFG_CEN_CONST, 0x40010ab8 +.set CYREG_B0_P5_U1_MC_CFG_XORFB, 0x40010aba +.set CYREG_B0_P5_U1_MC_CFG_SET_RESET, 0x40010abc +.set CYREG_B0_P5_U1_MC_CFG_BYPASS, 0x40010abe +.set CYREG_B0_P5_U1_CFG0, 0x40010ac0 +.set CYREG_B0_P5_U1_CFG1, 0x40010ac1 +.set CYREG_B0_P5_U1_CFG2, 0x40010ac2 +.set CYREG_B0_P5_U1_CFG3, 0x40010ac3 +.set CYREG_B0_P5_U1_CFG4, 0x40010ac4 +.set CYREG_B0_P5_U1_CFG5, 0x40010ac5 +.set CYREG_B0_P5_U1_CFG6, 0x40010ac6 +.set CYREG_B0_P5_U1_CFG7, 0x40010ac7 +.set CYREG_B0_P5_U1_CFG8, 0x40010ac8 +.set CYREG_B0_P5_U1_CFG9, 0x40010ac9 +.set CYREG_B0_P5_U1_CFG10, 0x40010aca +.set CYREG_B0_P5_U1_CFG11, 0x40010acb +.set CYREG_B0_P5_U1_CFG12, 0x40010acc +.set CYREG_B0_P5_U1_CFG13, 0x40010acd +.set CYREG_B0_P5_U1_CFG14, 0x40010ace +.set CYREG_B0_P5_U1_CFG15, 0x40010acf +.set CYREG_B0_P5_U1_CFG16, 0x40010ad0 +.set CYREG_B0_P5_U1_CFG17, 0x40010ad1 +.set CYREG_B0_P5_U1_CFG18, 0x40010ad2 +.set CYREG_B0_P5_U1_CFG19, 0x40010ad3 +.set CYREG_B0_P5_U1_CFG20, 0x40010ad4 +.set CYREG_B0_P5_U1_CFG21, 0x40010ad5 +.set CYREG_B0_P5_U1_CFG22, 0x40010ad6 +.set CYREG_B0_P5_U1_CFG23, 0x40010ad7 +.set CYREG_B0_P5_U1_CFG24, 0x40010ad8 +.set CYREG_B0_P5_U1_CFG25, 0x40010ad9 +.set CYREG_B0_P5_U1_CFG26, 0x40010ada +.set CYREG_B0_P5_U1_CFG27, 0x40010adb +.set CYREG_B0_P5_U1_CFG28, 0x40010adc +.set CYREG_B0_P5_U1_CFG29, 0x40010add +.set CYREG_B0_P5_U1_CFG30, 0x40010ade +.set CYREG_B0_P5_U1_CFG31, 0x40010adf +.set CYREG_B0_P5_U1_DCFG0, 0x40010ae0 +.set CYREG_B0_P5_U1_DCFG1, 0x40010ae2 +.set CYREG_B0_P5_U1_DCFG2, 0x40010ae4 +.set CYREG_B0_P5_U1_DCFG3, 0x40010ae6 +.set CYREG_B0_P5_U1_DCFG4, 0x40010ae8 +.set CYREG_B0_P5_U1_DCFG5, 0x40010aea +.set CYREG_B0_P5_U1_DCFG6, 0x40010aec +.set CYREG_B0_P5_U1_DCFG7, 0x40010aee +.set CYDEV_UCFG_B0_P5_ROUTE_BASE, 0x40010b00 +.set CYDEV_UCFG_B0_P5_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P6_BASE, 0x40010c00 +.set CYDEV_UCFG_B0_P6_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P6_U0_BASE, 0x40010c00 +.set CYDEV_UCFG_B0_P6_U0_SIZE, 0x00000070 +.set CYREG_B0_P6_U0_PLD_IT0, 0x40010c00 +.set CYREG_B0_P6_U0_PLD_IT1, 0x40010c04 +.set CYREG_B0_P6_U0_PLD_IT2, 0x40010c08 +.set CYREG_B0_P6_U0_PLD_IT3, 0x40010c0c +.set CYREG_B0_P6_U0_PLD_IT4, 0x40010c10 +.set CYREG_B0_P6_U0_PLD_IT5, 0x40010c14 +.set CYREG_B0_P6_U0_PLD_IT6, 0x40010c18 +.set CYREG_B0_P6_U0_PLD_IT7, 0x40010c1c +.set CYREG_B0_P6_U0_PLD_IT8, 0x40010c20 +.set CYREG_B0_P6_U0_PLD_IT9, 0x40010c24 +.set CYREG_B0_P6_U0_PLD_IT10, 0x40010c28 +.set CYREG_B0_P6_U0_PLD_IT11, 0x40010c2c +.set CYREG_B0_P6_U0_PLD_ORT0, 0x40010c30 +.set CYREG_B0_P6_U0_PLD_ORT1, 0x40010c32 +.set CYREG_B0_P6_U0_PLD_ORT2, 0x40010c34 +.set CYREG_B0_P6_U0_PLD_ORT3, 0x40010c36 +.set CYREG_B0_P6_U0_MC_CFG_CEN_CONST, 0x40010c38 +.set CYREG_B0_P6_U0_MC_CFG_XORFB, 0x40010c3a +.set CYREG_B0_P6_U0_MC_CFG_SET_RESET, 0x40010c3c +.set CYREG_B0_P6_U0_MC_CFG_BYPASS, 0x40010c3e +.set CYREG_B0_P6_U0_CFG0, 0x40010c40 +.set CYREG_B0_P6_U0_CFG1, 0x40010c41 +.set CYREG_B0_P6_U0_CFG2, 0x40010c42 +.set CYREG_B0_P6_U0_CFG3, 0x40010c43 +.set CYREG_B0_P6_U0_CFG4, 0x40010c44 +.set CYREG_B0_P6_U0_CFG5, 0x40010c45 +.set CYREG_B0_P6_U0_CFG6, 0x40010c46 +.set CYREG_B0_P6_U0_CFG7, 0x40010c47 +.set CYREG_B0_P6_U0_CFG8, 0x40010c48 +.set CYREG_B0_P6_U0_CFG9, 0x40010c49 +.set CYREG_B0_P6_U0_CFG10, 0x40010c4a +.set CYREG_B0_P6_U0_CFG11, 0x40010c4b +.set CYREG_B0_P6_U0_CFG12, 0x40010c4c +.set CYREG_B0_P6_U0_CFG13, 0x40010c4d +.set CYREG_B0_P6_U0_CFG14, 0x40010c4e +.set CYREG_B0_P6_U0_CFG15, 0x40010c4f +.set CYREG_B0_P6_U0_CFG16, 0x40010c50 +.set CYREG_B0_P6_U0_CFG17, 0x40010c51 +.set CYREG_B0_P6_U0_CFG18, 0x40010c52 +.set CYREG_B0_P6_U0_CFG19, 0x40010c53 +.set CYREG_B0_P6_U0_CFG20, 0x40010c54 +.set CYREG_B0_P6_U0_CFG21, 0x40010c55 +.set CYREG_B0_P6_U0_CFG22, 0x40010c56 +.set CYREG_B0_P6_U0_CFG23, 0x40010c57 +.set CYREG_B0_P6_U0_CFG24, 0x40010c58 +.set CYREG_B0_P6_U0_CFG25, 0x40010c59 +.set CYREG_B0_P6_U0_CFG26, 0x40010c5a +.set CYREG_B0_P6_U0_CFG27, 0x40010c5b +.set CYREG_B0_P6_U0_CFG28, 0x40010c5c +.set CYREG_B0_P6_U0_CFG29, 0x40010c5d +.set CYREG_B0_P6_U0_CFG30, 0x40010c5e +.set CYREG_B0_P6_U0_CFG31, 0x40010c5f +.set CYREG_B0_P6_U0_DCFG0, 0x40010c60 +.set CYREG_B0_P6_U0_DCFG1, 0x40010c62 +.set CYREG_B0_P6_U0_DCFG2, 0x40010c64 +.set CYREG_B0_P6_U0_DCFG3, 0x40010c66 +.set CYREG_B0_P6_U0_DCFG4, 0x40010c68 +.set CYREG_B0_P6_U0_DCFG5, 0x40010c6a +.set CYREG_B0_P6_U0_DCFG6, 0x40010c6c +.set CYREG_B0_P6_U0_DCFG7, 0x40010c6e +.set CYDEV_UCFG_B0_P6_U1_BASE, 0x40010c80 +.set CYDEV_UCFG_B0_P6_U1_SIZE, 0x00000070 +.set CYREG_B0_P6_U1_PLD_IT0, 0x40010c80 +.set CYREG_B0_P6_U1_PLD_IT1, 0x40010c84 +.set CYREG_B0_P6_U1_PLD_IT2, 0x40010c88 +.set CYREG_B0_P6_U1_PLD_IT3, 0x40010c8c +.set CYREG_B0_P6_U1_PLD_IT4, 0x40010c90 +.set CYREG_B0_P6_U1_PLD_IT5, 0x40010c94 +.set CYREG_B0_P6_U1_PLD_IT6, 0x40010c98 +.set CYREG_B0_P6_U1_PLD_IT7, 0x40010c9c +.set CYREG_B0_P6_U1_PLD_IT8, 0x40010ca0 +.set CYREG_B0_P6_U1_PLD_IT9, 0x40010ca4 +.set CYREG_B0_P6_U1_PLD_IT10, 0x40010ca8 +.set CYREG_B0_P6_U1_PLD_IT11, 0x40010cac +.set CYREG_B0_P6_U1_PLD_ORT0, 0x40010cb0 +.set CYREG_B0_P6_U1_PLD_ORT1, 0x40010cb2 +.set CYREG_B0_P6_U1_PLD_ORT2, 0x40010cb4 +.set CYREG_B0_P6_U1_PLD_ORT3, 0x40010cb6 +.set CYREG_B0_P6_U1_MC_CFG_CEN_CONST, 0x40010cb8 +.set CYREG_B0_P6_U1_MC_CFG_XORFB, 0x40010cba +.set CYREG_B0_P6_U1_MC_CFG_SET_RESET, 0x40010cbc +.set CYREG_B0_P6_U1_MC_CFG_BYPASS, 0x40010cbe +.set CYREG_B0_P6_U1_CFG0, 0x40010cc0 +.set CYREG_B0_P6_U1_CFG1, 0x40010cc1 +.set CYREG_B0_P6_U1_CFG2, 0x40010cc2 +.set CYREG_B0_P6_U1_CFG3, 0x40010cc3 +.set CYREG_B0_P6_U1_CFG4, 0x40010cc4 +.set CYREG_B0_P6_U1_CFG5, 0x40010cc5 +.set CYREG_B0_P6_U1_CFG6, 0x40010cc6 +.set CYREG_B0_P6_U1_CFG7, 0x40010cc7 +.set CYREG_B0_P6_U1_CFG8, 0x40010cc8 +.set CYREG_B0_P6_U1_CFG9, 0x40010cc9 +.set CYREG_B0_P6_U1_CFG10, 0x40010cca +.set CYREG_B0_P6_U1_CFG11, 0x40010ccb +.set CYREG_B0_P6_U1_CFG12, 0x40010ccc +.set CYREG_B0_P6_U1_CFG13, 0x40010ccd +.set CYREG_B0_P6_U1_CFG14, 0x40010cce +.set CYREG_B0_P6_U1_CFG15, 0x40010ccf +.set CYREG_B0_P6_U1_CFG16, 0x40010cd0 +.set CYREG_B0_P6_U1_CFG17, 0x40010cd1 +.set CYREG_B0_P6_U1_CFG18, 0x40010cd2 +.set CYREG_B0_P6_U1_CFG19, 0x40010cd3 +.set CYREG_B0_P6_U1_CFG20, 0x40010cd4 +.set CYREG_B0_P6_U1_CFG21, 0x40010cd5 +.set CYREG_B0_P6_U1_CFG22, 0x40010cd6 +.set CYREG_B0_P6_U1_CFG23, 0x40010cd7 +.set CYREG_B0_P6_U1_CFG24, 0x40010cd8 +.set CYREG_B0_P6_U1_CFG25, 0x40010cd9 +.set CYREG_B0_P6_U1_CFG26, 0x40010cda +.set CYREG_B0_P6_U1_CFG27, 0x40010cdb +.set CYREG_B0_P6_U1_CFG28, 0x40010cdc +.set CYREG_B0_P6_U1_CFG29, 0x40010cdd +.set CYREG_B0_P6_U1_CFG30, 0x40010cde +.set CYREG_B0_P6_U1_CFG31, 0x40010cdf +.set CYREG_B0_P6_U1_DCFG0, 0x40010ce0 +.set CYREG_B0_P6_U1_DCFG1, 0x40010ce2 +.set CYREG_B0_P6_U1_DCFG2, 0x40010ce4 +.set CYREG_B0_P6_U1_DCFG3, 0x40010ce6 +.set CYREG_B0_P6_U1_DCFG4, 0x40010ce8 +.set CYREG_B0_P6_U1_DCFG5, 0x40010cea +.set CYREG_B0_P6_U1_DCFG6, 0x40010cec +.set CYREG_B0_P6_U1_DCFG7, 0x40010cee +.set CYDEV_UCFG_B0_P6_ROUTE_BASE, 0x40010d00 +.set CYDEV_UCFG_B0_P6_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P7_BASE, 0x40010e00 +.set CYDEV_UCFG_B0_P7_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P7_U0_BASE, 0x40010e00 +.set CYDEV_UCFG_B0_P7_U0_SIZE, 0x00000070 +.set CYREG_B0_P7_U0_PLD_IT0, 0x40010e00 +.set CYREG_B0_P7_U0_PLD_IT1, 0x40010e04 +.set CYREG_B0_P7_U0_PLD_IT2, 0x40010e08 +.set CYREG_B0_P7_U0_PLD_IT3, 0x40010e0c +.set CYREG_B0_P7_U0_PLD_IT4, 0x40010e10 +.set CYREG_B0_P7_U0_PLD_IT5, 0x40010e14 +.set CYREG_B0_P7_U0_PLD_IT6, 0x40010e18 +.set CYREG_B0_P7_U0_PLD_IT7, 0x40010e1c +.set CYREG_B0_P7_U0_PLD_IT8, 0x40010e20 +.set CYREG_B0_P7_U0_PLD_IT9, 0x40010e24 +.set CYREG_B0_P7_U0_PLD_IT10, 0x40010e28 +.set CYREG_B0_P7_U0_PLD_IT11, 0x40010e2c +.set CYREG_B0_P7_U0_PLD_ORT0, 0x40010e30 +.set CYREG_B0_P7_U0_PLD_ORT1, 0x40010e32 +.set CYREG_B0_P7_U0_PLD_ORT2, 0x40010e34 +.set CYREG_B0_P7_U0_PLD_ORT3, 0x40010e36 +.set CYREG_B0_P7_U0_MC_CFG_CEN_CONST, 0x40010e38 +.set CYREG_B0_P7_U0_MC_CFG_XORFB, 0x40010e3a +.set CYREG_B0_P7_U0_MC_CFG_SET_RESET, 0x40010e3c +.set CYREG_B0_P7_U0_MC_CFG_BYPASS, 0x40010e3e +.set CYREG_B0_P7_U0_CFG0, 0x40010e40 +.set CYREG_B0_P7_U0_CFG1, 0x40010e41 +.set CYREG_B0_P7_U0_CFG2, 0x40010e42 +.set CYREG_B0_P7_U0_CFG3, 0x40010e43 +.set CYREG_B0_P7_U0_CFG4, 0x40010e44 +.set CYREG_B0_P7_U0_CFG5, 0x40010e45 +.set CYREG_B0_P7_U0_CFG6, 0x40010e46 +.set CYREG_B0_P7_U0_CFG7, 0x40010e47 +.set CYREG_B0_P7_U0_CFG8, 0x40010e48 +.set CYREG_B0_P7_U0_CFG9, 0x40010e49 +.set CYREG_B0_P7_U0_CFG10, 0x40010e4a +.set CYREG_B0_P7_U0_CFG11, 0x40010e4b +.set CYREG_B0_P7_U0_CFG12, 0x40010e4c +.set CYREG_B0_P7_U0_CFG13, 0x40010e4d +.set CYREG_B0_P7_U0_CFG14, 0x40010e4e +.set CYREG_B0_P7_U0_CFG15, 0x40010e4f +.set CYREG_B0_P7_U0_CFG16, 0x40010e50 +.set CYREG_B0_P7_U0_CFG17, 0x40010e51 +.set CYREG_B0_P7_U0_CFG18, 0x40010e52 +.set CYREG_B0_P7_U0_CFG19, 0x40010e53 +.set CYREG_B0_P7_U0_CFG20, 0x40010e54 +.set CYREG_B0_P7_U0_CFG21, 0x40010e55 +.set CYREG_B0_P7_U0_CFG22, 0x40010e56 +.set CYREG_B0_P7_U0_CFG23, 0x40010e57 +.set CYREG_B0_P7_U0_CFG24, 0x40010e58 +.set CYREG_B0_P7_U0_CFG25, 0x40010e59 +.set CYREG_B0_P7_U0_CFG26, 0x40010e5a +.set CYREG_B0_P7_U0_CFG27, 0x40010e5b +.set CYREG_B0_P7_U0_CFG28, 0x40010e5c +.set CYREG_B0_P7_U0_CFG29, 0x40010e5d +.set CYREG_B0_P7_U0_CFG30, 0x40010e5e +.set CYREG_B0_P7_U0_CFG31, 0x40010e5f +.set CYREG_B0_P7_U0_DCFG0, 0x40010e60 +.set CYREG_B0_P7_U0_DCFG1, 0x40010e62 +.set CYREG_B0_P7_U0_DCFG2, 0x40010e64 +.set CYREG_B0_P7_U0_DCFG3, 0x40010e66 +.set CYREG_B0_P7_U0_DCFG4, 0x40010e68 +.set CYREG_B0_P7_U0_DCFG5, 0x40010e6a +.set CYREG_B0_P7_U0_DCFG6, 0x40010e6c +.set CYREG_B0_P7_U0_DCFG7, 0x40010e6e +.set CYDEV_UCFG_B0_P7_U1_BASE, 0x40010e80 +.set CYDEV_UCFG_B0_P7_U1_SIZE, 0x00000070 +.set CYREG_B0_P7_U1_PLD_IT0, 0x40010e80 +.set CYREG_B0_P7_U1_PLD_IT1, 0x40010e84 +.set CYREG_B0_P7_U1_PLD_IT2, 0x40010e88 +.set CYREG_B0_P7_U1_PLD_IT3, 0x40010e8c +.set CYREG_B0_P7_U1_PLD_IT4, 0x40010e90 +.set CYREG_B0_P7_U1_PLD_IT5, 0x40010e94 +.set CYREG_B0_P7_U1_PLD_IT6, 0x40010e98 +.set CYREG_B0_P7_U1_PLD_IT7, 0x40010e9c +.set CYREG_B0_P7_U1_PLD_IT8, 0x40010ea0 +.set CYREG_B0_P7_U1_PLD_IT9, 0x40010ea4 +.set CYREG_B0_P7_U1_PLD_IT10, 0x40010ea8 +.set CYREG_B0_P7_U1_PLD_IT11, 0x40010eac +.set CYREG_B0_P7_U1_PLD_ORT0, 0x40010eb0 +.set CYREG_B0_P7_U1_PLD_ORT1, 0x40010eb2 +.set CYREG_B0_P7_U1_PLD_ORT2, 0x40010eb4 +.set CYREG_B0_P7_U1_PLD_ORT3, 0x40010eb6 +.set CYREG_B0_P7_U1_MC_CFG_CEN_CONST, 0x40010eb8 +.set CYREG_B0_P7_U1_MC_CFG_XORFB, 0x40010eba +.set CYREG_B0_P7_U1_MC_CFG_SET_RESET, 0x40010ebc +.set CYREG_B0_P7_U1_MC_CFG_BYPASS, 0x40010ebe +.set CYREG_B0_P7_U1_CFG0, 0x40010ec0 +.set CYREG_B0_P7_U1_CFG1, 0x40010ec1 +.set CYREG_B0_P7_U1_CFG2, 0x40010ec2 +.set CYREG_B0_P7_U1_CFG3, 0x40010ec3 +.set CYREG_B0_P7_U1_CFG4, 0x40010ec4 +.set CYREG_B0_P7_U1_CFG5, 0x40010ec5 +.set CYREG_B0_P7_U1_CFG6, 0x40010ec6 +.set CYREG_B0_P7_U1_CFG7, 0x40010ec7 +.set CYREG_B0_P7_U1_CFG8, 0x40010ec8 +.set CYREG_B0_P7_U1_CFG9, 0x40010ec9 +.set CYREG_B0_P7_U1_CFG10, 0x40010eca +.set CYREG_B0_P7_U1_CFG11, 0x40010ecb +.set CYREG_B0_P7_U1_CFG12, 0x40010ecc +.set CYREG_B0_P7_U1_CFG13, 0x40010ecd +.set CYREG_B0_P7_U1_CFG14, 0x40010ece +.set CYREG_B0_P7_U1_CFG15, 0x40010ecf +.set CYREG_B0_P7_U1_CFG16, 0x40010ed0 +.set CYREG_B0_P7_U1_CFG17, 0x40010ed1 +.set CYREG_B0_P7_U1_CFG18, 0x40010ed2 +.set CYREG_B0_P7_U1_CFG19, 0x40010ed3 +.set CYREG_B0_P7_U1_CFG20, 0x40010ed4 +.set CYREG_B0_P7_U1_CFG21, 0x40010ed5 +.set CYREG_B0_P7_U1_CFG22, 0x40010ed6 +.set CYREG_B0_P7_U1_CFG23, 0x40010ed7 +.set CYREG_B0_P7_U1_CFG24, 0x40010ed8 +.set CYREG_B0_P7_U1_CFG25, 0x40010ed9 +.set CYREG_B0_P7_U1_CFG26, 0x40010eda +.set CYREG_B0_P7_U1_CFG27, 0x40010edb +.set CYREG_B0_P7_U1_CFG28, 0x40010edc +.set CYREG_B0_P7_U1_CFG29, 0x40010edd +.set CYREG_B0_P7_U1_CFG30, 0x40010ede +.set CYREG_B0_P7_U1_CFG31, 0x40010edf +.set CYREG_B0_P7_U1_DCFG0, 0x40010ee0 +.set CYREG_B0_P7_U1_DCFG1, 0x40010ee2 +.set CYREG_B0_P7_U1_DCFG2, 0x40010ee4 +.set CYREG_B0_P7_U1_DCFG3, 0x40010ee6 +.set CYREG_B0_P7_U1_DCFG4, 0x40010ee8 +.set CYREG_B0_P7_U1_DCFG5, 0x40010eea +.set CYREG_B0_P7_U1_DCFG6, 0x40010eec +.set CYREG_B0_P7_U1_DCFG7, 0x40010eee +.set CYDEV_UCFG_B0_P7_ROUTE_BASE, 0x40010f00 +.set CYDEV_UCFG_B0_P7_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_BASE, 0x40011000 +.set CYDEV_UCFG_B1_SIZE, 0x00000fef +.set CYDEV_UCFG_B1_P2_BASE, 0x40011400 +.set CYDEV_UCFG_B1_P2_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P2_U0_BASE, 0x40011400 +.set CYDEV_UCFG_B1_P2_U0_SIZE, 0x00000070 +.set CYREG_B1_P2_U0_PLD_IT0, 0x40011400 +.set CYREG_B1_P2_U0_PLD_IT1, 0x40011404 +.set CYREG_B1_P2_U0_PLD_IT2, 0x40011408 +.set CYREG_B1_P2_U0_PLD_IT3, 0x4001140c +.set CYREG_B1_P2_U0_PLD_IT4, 0x40011410 +.set CYREG_B1_P2_U0_PLD_IT5, 0x40011414 +.set CYREG_B1_P2_U0_PLD_IT6, 0x40011418 +.set CYREG_B1_P2_U0_PLD_IT7, 0x4001141c +.set CYREG_B1_P2_U0_PLD_IT8, 0x40011420 +.set CYREG_B1_P2_U0_PLD_IT9, 0x40011424 +.set CYREG_B1_P2_U0_PLD_IT10, 0x40011428 +.set CYREG_B1_P2_U0_PLD_IT11, 0x4001142c +.set CYREG_B1_P2_U0_PLD_ORT0, 0x40011430 +.set CYREG_B1_P2_U0_PLD_ORT1, 0x40011432 +.set CYREG_B1_P2_U0_PLD_ORT2, 0x40011434 +.set CYREG_B1_P2_U0_PLD_ORT3, 0x40011436 +.set CYREG_B1_P2_U0_MC_CFG_CEN_CONST, 0x40011438 +.set CYREG_B1_P2_U0_MC_CFG_XORFB, 0x4001143a +.set CYREG_B1_P2_U0_MC_CFG_SET_RESET, 0x4001143c +.set CYREG_B1_P2_U0_MC_CFG_BYPASS, 0x4001143e +.set CYREG_B1_P2_U0_CFG0, 0x40011440 +.set CYREG_B1_P2_U0_CFG1, 0x40011441 +.set CYREG_B1_P2_U0_CFG2, 0x40011442 +.set CYREG_B1_P2_U0_CFG3, 0x40011443 +.set CYREG_B1_P2_U0_CFG4, 0x40011444 +.set CYREG_B1_P2_U0_CFG5, 0x40011445 +.set CYREG_B1_P2_U0_CFG6, 0x40011446 +.set CYREG_B1_P2_U0_CFG7, 0x40011447 +.set CYREG_B1_P2_U0_CFG8, 0x40011448 +.set CYREG_B1_P2_U0_CFG9, 0x40011449 +.set CYREG_B1_P2_U0_CFG10, 0x4001144a +.set CYREG_B1_P2_U0_CFG11, 0x4001144b +.set CYREG_B1_P2_U0_CFG12, 0x4001144c +.set CYREG_B1_P2_U0_CFG13, 0x4001144d +.set CYREG_B1_P2_U0_CFG14, 0x4001144e +.set CYREG_B1_P2_U0_CFG15, 0x4001144f +.set CYREG_B1_P2_U0_CFG16, 0x40011450 +.set CYREG_B1_P2_U0_CFG17, 0x40011451 +.set CYREG_B1_P2_U0_CFG18, 0x40011452 +.set CYREG_B1_P2_U0_CFG19, 0x40011453 +.set CYREG_B1_P2_U0_CFG20, 0x40011454 +.set CYREG_B1_P2_U0_CFG21, 0x40011455 +.set CYREG_B1_P2_U0_CFG22, 0x40011456 +.set CYREG_B1_P2_U0_CFG23, 0x40011457 +.set CYREG_B1_P2_U0_CFG24, 0x40011458 +.set CYREG_B1_P2_U0_CFG25, 0x40011459 +.set CYREG_B1_P2_U0_CFG26, 0x4001145a +.set CYREG_B1_P2_U0_CFG27, 0x4001145b +.set CYREG_B1_P2_U0_CFG28, 0x4001145c +.set CYREG_B1_P2_U0_CFG29, 0x4001145d +.set CYREG_B1_P2_U0_CFG30, 0x4001145e +.set CYREG_B1_P2_U0_CFG31, 0x4001145f +.set CYREG_B1_P2_U0_DCFG0, 0x40011460 +.set CYREG_B1_P2_U0_DCFG1, 0x40011462 +.set CYREG_B1_P2_U0_DCFG2, 0x40011464 +.set CYREG_B1_P2_U0_DCFG3, 0x40011466 +.set CYREG_B1_P2_U0_DCFG4, 0x40011468 +.set CYREG_B1_P2_U0_DCFG5, 0x4001146a +.set CYREG_B1_P2_U0_DCFG6, 0x4001146c +.set CYREG_B1_P2_U0_DCFG7, 0x4001146e +.set CYDEV_UCFG_B1_P2_U1_BASE, 0x40011480 +.set CYDEV_UCFG_B1_P2_U1_SIZE, 0x00000070 +.set CYREG_B1_P2_U1_PLD_IT0, 0x40011480 +.set CYREG_B1_P2_U1_PLD_IT1, 0x40011484 +.set CYREG_B1_P2_U1_PLD_IT2, 0x40011488 +.set CYREG_B1_P2_U1_PLD_IT3, 0x4001148c +.set CYREG_B1_P2_U1_PLD_IT4, 0x40011490 +.set CYREG_B1_P2_U1_PLD_IT5, 0x40011494 +.set CYREG_B1_P2_U1_PLD_IT6, 0x40011498 +.set CYREG_B1_P2_U1_PLD_IT7, 0x4001149c +.set CYREG_B1_P2_U1_PLD_IT8, 0x400114a0 +.set CYREG_B1_P2_U1_PLD_IT9, 0x400114a4 +.set CYREG_B1_P2_U1_PLD_IT10, 0x400114a8 +.set CYREG_B1_P2_U1_PLD_IT11, 0x400114ac +.set CYREG_B1_P2_U1_PLD_ORT0, 0x400114b0 +.set CYREG_B1_P2_U1_PLD_ORT1, 0x400114b2 +.set CYREG_B1_P2_U1_PLD_ORT2, 0x400114b4 +.set CYREG_B1_P2_U1_PLD_ORT3, 0x400114b6 +.set CYREG_B1_P2_U1_MC_CFG_CEN_CONST, 0x400114b8 +.set CYREG_B1_P2_U1_MC_CFG_XORFB, 0x400114ba +.set CYREG_B1_P2_U1_MC_CFG_SET_RESET, 0x400114bc +.set CYREG_B1_P2_U1_MC_CFG_BYPASS, 0x400114be +.set CYREG_B1_P2_U1_CFG0, 0x400114c0 +.set CYREG_B1_P2_U1_CFG1, 0x400114c1 +.set CYREG_B1_P2_U1_CFG2, 0x400114c2 +.set CYREG_B1_P2_U1_CFG3, 0x400114c3 +.set CYREG_B1_P2_U1_CFG4, 0x400114c4 +.set CYREG_B1_P2_U1_CFG5, 0x400114c5 +.set CYREG_B1_P2_U1_CFG6, 0x400114c6 +.set CYREG_B1_P2_U1_CFG7, 0x400114c7 +.set CYREG_B1_P2_U1_CFG8, 0x400114c8 +.set CYREG_B1_P2_U1_CFG9, 0x400114c9 +.set CYREG_B1_P2_U1_CFG10, 0x400114ca +.set CYREG_B1_P2_U1_CFG11, 0x400114cb +.set CYREG_B1_P2_U1_CFG12, 0x400114cc +.set CYREG_B1_P2_U1_CFG13, 0x400114cd +.set CYREG_B1_P2_U1_CFG14, 0x400114ce +.set CYREG_B1_P2_U1_CFG15, 0x400114cf +.set CYREG_B1_P2_U1_CFG16, 0x400114d0 +.set CYREG_B1_P2_U1_CFG17, 0x400114d1 +.set CYREG_B1_P2_U1_CFG18, 0x400114d2 +.set CYREG_B1_P2_U1_CFG19, 0x400114d3 +.set CYREG_B1_P2_U1_CFG20, 0x400114d4 +.set CYREG_B1_P2_U1_CFG21, 0x400114d5 +.set CYREG_B1_P2_U1_CFG22, 0x400114d6 +.set CYREG_B1_P2_U1_CFG23, 0x400114d7 +.set CYREG_B1_P2_U1_CFG24, 0x400114d8 +.set CYREG_B1_P2_U1_CFG25, 0x400114d9 +.set CYREG_B1_P2_U1_CFG26, 0x400114da +.set CYREG_B1_P2_U1_CFG27, 0x400114db +.set CYREG_B1_P2_U1_CFG28, 0x400114dc +.set CYREG_B1_P2_U1_CFG29, 0x400114dd +.set CYREG_B1_P2_U1_CFG30, 0x400114de +.set CYREG_B1_P2_U1_CFG31, 0x400114df +.set CYREG_B1_P2_U1_DCFG0, 0x400114e0 +.set CYREG_B1_P2_U1_DCFG1, 0x400114e2 +.set CYREG_B1_P2_U1_DCFG2, 0x400114e4 +.set CYREG_B1_P2_U1_DCFG3, 0x400114e6 +.set CYREG_B1_P2_U1_DCFG4, 0x400114e8 +.set CYREG_B1_P2_U1_DCFG5, 0x400114ea +.set CYREG_B1_P2_U1_DCFG6, 0x400114ec +.set CYREG_B1_P2_U1_DCFG7, 0x400114ee +.set CYDEV_UCFG_B1_P2_ROUTE_BASE, 0x40011500 +.set CYDEV_UCFG_B1_P2_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_P3_BASE, 0x40011600 +.set CYDEV_UCFG_B1_P3_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P3_U0_BASE, 0x40011600 +.set CYDEV_UCFG_B1_P3_U0_SIZE, 0x00000070 +.set CYREG_B1_P3_U0_PLD_IT0, 0x40011600 +.set CYREG_B1_P3_U0_PLD_IT1, 0x40011604 +.set CYREG_B1_P3_U0_PLD_IT2, 0x40011608 +.set CYREG_B1_P3_U0_PLD_IT3, 0x4001160c +.set CYREG_B1_P3_U0_PLD_IT4, 0x40011610 +.set CYREG_B1_P3_U0_PLD_IT5, 0x40011614 +.set CYREG_B1_P3_U0_PLD_IT6, 0x40011618 +.set CYREG_B1_P3_U0_PLD_IT7, 0x4001161c +.set CYREG_B1_P3_U0_PLD_IT8, 0x40011620 +.set CYREG_B1_P3_U0_PLD_IT9, 0x40011624 +.set CYREG_B1_P3_U0_PLD_IT10, 0x40011628 +.set CYREG_B1_P3_U0_PLD_IT11, 0x4001162c +.set CYREG_B1_P3_U0_PLD_ORT0, 0x40011630 +.set CYREG_B1_P3_U0_PLD_ORT1, 0x40011632 +.set CYREG_B1_P3_U0_PLD_ORT2, 0x40011634 +.set CYREG_B1_P3_U0_PLD_ORT3, 0x40011636 +.set CYREG_B1_P3_U0_MC_CFG_CEN_CONST, 0x40011638 +.set CYREG_B1_P3_U0_MC_CFG_XORFB, 0x4001163a +.set CYREG_B1_P3_U0_MC_CFG_SET_RESET, 0x4001163c +.set CYREG_B1_P3_U0_MC_CFG_BYPASS, 0x4001163e +.set CYREG_B1_P3_U0_CFG0, 0x40011640 +.set CYREG_B1_P3_U0_CFG1, 0x40011641 +.set CYREG_B1_P3_U0_CFG2, 0x40011642 +.set CYREG_B1_P3_U0_CFG3, 0x40011643 +.set CYREG_B1_P3_U0_CFG4, 0x40011644 +.set CYREG_B1_P3_U0_CFG5, 0x40011645 +.set CYREG_B1_P3_U0_CFG6, 0x40011646 +.set CYREG_B1_P3_U0_CFG7, 0x40011647 +.set CYREG_B1_P3_U0_CFG8, 0x40011648 +.set CYREG_B1_P3_U0_CFG9, 0x40011649 +.set CYREG_B1_P3_U0_CFG10, 0x4001164a +.set CYREG_B1_P3_U0_CFG11, 0x4001164b +.set CYREG_B1_P3_U0_CFG12, 0x4001164c +.set CYREG_B1_P3_U0_CFG13, 0x4001164d +.set CYREG_B1_P3_U0_CFG14, 0x4001164e +.set CYREG_B1_P3_U0_CFG15, 0x4001164f +.set CYREG_B1_P3_U0_CFG16, 0x40011650 +.set CYREG_B1_P3_U0_CFG17, 0x40011651 +.set CYREG_B1_P3_U0_CFG18, 0x40011652 +.set CYREG_B1_P3_U0_CFG19, 0x40011653 +.set CYREG_B1_P3_U0_CFG20, 0x40011654 +.set CYREG_B1_P3_U0_CFG21, 0x40011655 +.set CYREG_B1_P3_U0_CFG22, 0x40011656 +.set CYREG_B1_P3_U0_CFG23, 0x40011657 +.set CYREG_B1_P3_U0_CFG24, 0x40011658 +.set CYREG_B1_P3_U0_CFG25, 0x40011659 +.set CYREG_B1_P3_U0_CFG26, 0x4001165a +.set CYREG_B1_P3_U0_CFG27, 0x4001165b +.set CYREG_B1_P3_U0_CFG28, 0x4001165c +.set CYREG_B1_P3_U0_CFG29, 0x4001165d +.set CYREG_B1_P3_U0_CFG30, 0x4001165e +.set CYREG_B1_P3_U0_CFG31, 0x4001165f +.set CYREG_B1_P3_U0_DCFG0, 0x40011660 +.set CYREG_B1_P3_U0_DCFG1, 0x40011662 +.set CYREG_B1_P3_U0_DCFG2, 0x40011664 +.set CYREG_B1_P3_U0_DCFG3, 0x40011666 +.set CYREG_B1_P3_U0_DCFG4, 0x40011668 +.set CYREG_B1_P3_U0_DCFG5, 0x4001166a +.set CYREG_B1_P3_U0_DCFG6, 0x4001166c +.set CYREG_B1_P3_U0_DCFG7, 0x4001166e +.set CYDEV_UCFG_B1_P3_U1_BASE, 0x40011680 +.set CYDEV_UCFG_B1_P3_U1_SIZE, 0x00000070 +.set CYREG_B1_P3_U1_PLD_IT0, 0x40011680 +.set CYREG_B1_P3_U1_PLD_IT1, 0x40011684 +.set CYREG_B1_P3_U1_PLD_IT2, 0x40011688 +.set CYREG_B1_P3_U1_PLD_IT3, 0x4001168c +.set CYREG_B1_P3_U1_PLD_IT4, 0x40011690 +.set CYREG_B1_P3_U1_PLD_IT5, 0x40011694 +.set CYREG_B1_P3_U1_PLD_IT6, 0x40011698 +.set CYREG_B1_P3_U1_PLD_IT7, 0x4001169c +.set CYREG_B1_P3_U1_PLD_IT8, 0x400116a0 +.set CYREG_B1_P3_U1_PLD_IT9, 0x400116a4 +.set CYREG_B1_P3_U1_PLD_IT10, 0x400116a8 +.set CYREG_B1_P3_U1_PLD_IT11, 0x400116ac +.set CYREG_B1_P3_U1_PLD_ORT0, 0x400116b0 +.set CYREG_B1_P3_U1_PLD_ORT1, 0x400116b2 +.set CYREG_B1_P3_U1_PLD_ORT2, 0x400116b4 +.set CYREG_B1_P3_U1_PLD_ORT3, 0x400116b6 +.set CYREG_B1_P3_U1_MC_CFG_CEN_CONST, 0x400116b8 +.set CYREG_B1_P3_U1_MC_CFG_XORFB, 0x400116ba +.set CYREG_B1_P3_U1_MC_CFG_SET_RESET, 0x400116bc +.set CYREG_B1_P3_U1_MC_CFG_BYPASS, 0x400116be +.set CYREG_B1_P3_U1_CFG0, 0x400116c0 +.set CYREG_B1_P3_U1_CFG1, 0x400116c1 +.set CYREG_B1_P3_U1_CFG2, 0x400116c2 +.set CYREG_B1_P3_U1_CFG3, 0x400116c3 +.set CYREG_B1_P3_U1_CFG4, 0x400116c4 +.set CYREG_B1_P3_U1_CFG5, 0x400116c5 +.set CYREG_B1_P3_U1_CFG6, 0x400116c6 +.set CYREG_B1_P3_U1_CFG7, 0x400116c7 +.set CYREG_B1_P3_U1_CFG8, 0x400116c8 +.set CYREG_B1_P3_U1_CFG9, 0x400116c9 +.set CYREG_B1_P3_U1_CFG10, 0x400116ca +.set CYREG_B1_P3_U1_CFG11, 0x400116cb +.set CYREG_B1_P3_U1_CFG12, 0x400116cc +.set CYREG_B1_P3_U1_CFG13, 0x400116cd +.set CYREG_B1_P3_U1_CFG14, 0x400116ce +.set CYREG_B1_P3_U1_CFG15, 0x400116cf +.set CYREG_B1_P3_U1_CFG16, 0x400116d0 +.set CYREG_B1_P3_U1_CFG17, 0x400116d1 +.set CYREG_B1_P3_U1_CFG18, 0x400116d2 +.set CYREG_B1_P3_U1_CFG19, 0x400116d3 +.set CYREG_B1_P3_U1_CFG20, 0x400116d4 +.set CYREG_B1_P3_U1_CFG21, 0x400116d5 +.set CYREG_B1_P3_U1_CFG22, 0x400116d6 +.set CYREG_B1_P3_U1_CFG23, 0x400116d7 +.set CYREG_B1_P3_U1_CFG24, 0x400116d8 +.set CYREG_B1_P3_U1_CFG25, 0x400116d9 +.set CYREG_B1_P3_U1_CFG26, 0x400116da +.set CYREG_B1_P3_U1_CFG27, 0x400116db +.set CYREG_B1_P3_U1_CFG28, 0x400116dc +.set CYREG_B1_P3_U1_CFG29, 0x400116dd +.set CYREG_B1_P3_U1_CFG30, 0x400116de +.set CYREG_B1_P3_U1_CFG31, 0x400116df +.set CYREG_B1_P3_U1_DCFG0, 0x400116e0 +.set CYREG_B1_P3_U1_DCFG1, 0x400116e2 +.set CYREG_B1_P3_U1_DCFG2, 0x400116e4 +.set CYREG_B1_P3_U1_DCFG3, 0x400116e6 +.set CYREG_B1_P3_U1_DCFG4, 0x400116e8 +.set CYREG_B1_P3_U1_DCFG5, 0x400116ea +.set CYREG_B1_P3_U1_DCFG6, 0x400116ec +.set CYREG_B1_P3_U1_DCFG7, 0x400116ee +.set CYDEV_UCFG_B1_P3_ROUTE_BASE, 0x40011700 +.set CYDEV_UCFG_B1_P3_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_P4_BASE, 0x40011800 +.set CYDEV_UCFG_B1_P4_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P4_U0_BASE, 0x40011800 +.set CYDEV_UCFG_B1_P4_U0_SIZE, 0x00000070 +.set CYREG_B1_P4_U0_PLD_IT0, 0x40011800 +.set CYREG_B1_P4_U0_PLD_IT1, 0x40011804 +.set CYREG_B1_P4_U0_PLD_IT2, 0x40011808 +.set CYREG_B1_P4_U0_PLD_IT3, 0x4001180c +.set CYREG_B1_P4_U0_PLD_IT4, 0x40011810 +.set CYREG_B1_P4_U0_PLD_IT5, 0x40011814 +.set CYREG_B1_P4_U0_PLD_IT6, 0x40011818 +.set CYREG_B1_P4_U0_PLD_IT7, 0x4001181c +.set CYREG_B1_P4_U0_PLD_IT8, 0x40011820 +.set CYREG_B1_P4_U0_PLD_IT9, 0x40011824 +.set CYREG_B1_P4_U0_PLD_IT10, 0x40011828 +.set CYREG_B1_P4_U0_PLD_IT11, 0x4001182c +.set CYREG_B1_P4_U0_PLD_ORT0, 0x40011830 +.set CYREG_B1_P4_U0_PLD_ORT1, 0x40011832 +.set CYREG_B1_P4_U0_PLD_ORT2, 0x40011834 +.set CYREG_B1_P4_U0_PLD_ORT3, 0x40011836 +.set CYREG_B1_P4_U0_MC_CFG_CEN_CONST, 0x40011838 +.set CYREG_B1_P4_U0_MC_CFG_XORFB, 0x4001183a +.set CYREG_B1_P4_U0_MC_CFG_SET_RESET, 0x4001183c +.set CYREG_B1_P4_U0_MC_CFG_BYPASS, 0x4001183e +.set CYREG_B1_P4_U0_CFG0, 0x40011840 +.set CYREG_B1_P4_U0_CFG1, 0x40011841 +.set CYREG_B1_P4_U0_CFG2, 0x40011842 +.set CYREG_B1_P4_U0_CFG3, 0x40011843 +.set CYREG_B1_P4_U0_CFG4, 0x40011844 +.set CYREG_B1_P4_U0_CFG5, 0x40011845 +.set CYREG_B1_P4_U0_CFG6, 0x40011846 +.set CYREG_B1_P4_U0_CFG7, 0x40011847 +.set CYREG_B1_P4_U0_CFG8, 0x40011848 +.set CYREG_B1_P4_U0_CFG9, 0x40011849 +.set CYREG_B1_P4_U0_CFG10, 0x4001184a +.set CYREG_B1_P4_U0_CFG11, 0x4001184b +.set CYREG_B1_P4_U0_CFG12, 0x4001184c +.set CYREG_B1_P4_U0_CFG13, 0x4001184d +.set CYREG_B1_P4_U0_CFG14, 0x4001184e +.set CYREG_B1_P4_U0_CFG15, 0x4001184f +.set CYREG_B1_P4_U0_CFG16, 0x40011850 +.set CYREG_B1_P4_U0_CFG17, 0x40011851 +.set CYREG_B1_P4_U0_CFG18, 0x40011852 +.set CYREG_B1_P4_U0_CFG19, 0x40011853 +.set CYREG_B1_P4_U0_CFG20, 0x40011854 +.set CYREG_B1_P4_U0_CFG21, 0x40011855 +.set CYREG_B1_P4_U0_CFG22, 0x40011856 +.set CYREG_B1_P4_U0_CFG23, 0x40011857 +.set CYREG_B1_P4_U0_CFG24, 0x40011858 +.set CYREG_B1_P4_U0_CFG25, 0x40011859 +.set CYREG_B1_P4_U0_CFG26, 0x4001185a +.set CYREG_B1_P4_U0_CFG27, 0x4001185b +.set CYREG_B1_P4_U0_CFG28, 0x4001185c +.set CYREG_B1_P4_U0_CFG29, 0x4001185d +.set CYREG_B1_P4_U0_CFG30, 0x4001185e +.set CYREG_B1_P4_U0_CFG31, 0x4001185f +.set CYREG_B1_P4_U0_DCFG0, 0x40011860 +.set CYREG_B1_P4_U0_DCFG1, 0x40011862 +.set CYREG_B1_P4_U0_DCFG2, 0x40011864 +.set CYREG_B1_P4_U0_DCFG3, 0x40011866 +.set CYREG_B1_P4_U0_DCFG4, 0x40011868 +.set CYREG_B1_P4_U0_DCFG5, 0x4001186a +.set CYREG_B1_P4_U0_DCFG6, 0x4001186c +.set CYREG_B1_P4_U0_DCFG7, 0x4001186e +.set CYDEV_UCFG_B1_P4_U1_BASE, 0x40011880 +.set CYDEV_UCFG_B1_P4_U1_SIZE, 0x00000070 +.set CYREG_B1_P4_U1_PLD_IT0, 0x40011880 +.set CYREG_B1_P4_U1_PLD_IT1, 0x40011884 +.set CYREG_B1_P4_U1_PLD_IT2, 0x40011888 +.set CYREG_B1_P4_U1_PLD_IT3, 0x4001188c +.set CYREG_B1_P4_U1_PLD_IT4, 0x40011890 +.set CYREG_B1_P4_U1_PLD_IT5, 0x40011894 +.set CYREG_B1_P4_U1_PLD_IT6, 0x40011898 +.set CYREG_B1_P4_U1_PLD_IT7, 0x4001189c +.set CYREG_B1_P4_U1_PLD_IT8, 0x400118a0 +.set CYREG_B1_P4_U1_PLD_IT9, 0x400118a4 +.set CYREG_B1_P4_U1_PLD_IT10, 0x400118a8 +.set CYREG_B1_P4_U1_PLD_IT11, 0x400118ac +.set CYREG_B1_P4_U1_PLD_ORT0, 0x400118b0 +.set CYREG_B1_P4_U1_PLD_ORT1, 0x400118b2 +.set CYREG_B1_P4_U1_PLD_ORT2, 0x400118b4 +.set CYREG_B1_P4_U1_PLD_ORT3, 0x400118b6 +.set CYREG_B1_P4_U1_MC_CFG_CEN_CONST, 0x400118b8 +.set CYREG_B1_P4_U1_MC_CFG_XORFB, 0x400118ba +.set CYREG_B1_P4_U1_MC_CFG_SET_RESET, 0x400118bc +.set CYREG_B1_P4_U1_MC_CFG_BYPASS, 0x400118be +.set CYREG_B1_P4_U1_CFG0, 0x400118c0 +.set CYREG_B1_P4_U1_CFG1, 0x400118c1 +.set CYREG_B1_P4_U1_CFG2, 0x400118c2 +.set CYREG_B1_P4_U1_CFG3, 0x400118c3 +.set CYREG_B1_P4_U1_CFG4, 0x400118c4 +.set CYREG_B1_P4_U1_CFG5, 0x400118c5 +.set CYREG_B1_P4_U1_CFG6, 0x400118c6 +.set CYREG_B1_P4_U1_CFG7, 0x400118c7 +.set CYREG_B1_P4_U1_CFG8, 0x400118c8 +.set CYREG_B1_P4_U1_CFG9, 0x400118c9 +.set CYREG_B1_P4_U1_CFG10, 0x400118ca +.set CYREG_B1_P4_U1_CFG11, 0x400118cb +.set CYREG_B1_P4_U1_CFG12, 0x400118cc +.set CYREG_B1_P4_U1_CFG13, 0x400118cd +.set CYREG_B1_P4_U1_CFG14, 0x400118ce +.set CYREG_B1_P4_U1_CFG15, 0x400118cf +.set CYREG_B1_P4_U1_CFG16, 0x400118d0 +.set CYREG_B1_P4_U1_CFG17, 0x400118d1 +.set CYREG_B1_P4_U1_CFG18, 0x400118d2 +.set CYREG_B1_P4_U1_CFG19, 0x400118d3 +.set CYREG_B1_P4_U1_CFG20, 0x400118d4 +.set CYREG_B1_P4_U1_CFG21, 0x400118d5 +.set CYREG_B1_P4_U1_CFG22, 0x400118d6 +.set CYREG_B1_P4_U1_CFG23, 0x400118d7 +.set CYREG_B1_P4_U1_CFG24, 0x400118d8 +.set CYREG_B1_P4_U1_CFG25, 0x400118d9 +.set CYREG_B1_P4_U1_CFG26, 0x400118da +.set CYREG_B1_P4_U1_CFG27, 0x400118db +.set CYREG_B1_P4_U1_CFG28, 0x400118dc +.set CYREG_B1_P4_U1_CFG29, 0x400118dd +.set CYREG_B1_P4_U1_CFG30, 0x400118de +.set CYREG_B1_P4_U1_CFG31, 0x400118df +.set CYREG_B1_P4_U1_DCFG0, 0x400118e0 +.set CYREG_B1_P4_U1_DCFG1, 0x400118e2 +.set CYREG_B1_P4_U1_DCFG2, 0x400118e4 +.set CYREG_B1_P4_U1_DCFG3, 0x400118e6 +.set CYREG_B1_P4_U1_DCFG4, 0x400118e8 +.set CYREG_B1_P4_U1_DCFG5, 0x400118ea +.set CYREG_B1_P4_U1_DCFG6, 0x400118ec +.set CYREG_B1_P4_U1_DCFG7, 0x400118ee +.set CYDEV_UCFG_B1_P4_ROUTE_BASE, 0x40011900 +.set CYDEV_UCFG_B1_P4_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_P5_BASE, 0x40011a00 +.set CYDEV_UCFG_B1_P5_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P5_U0_BASE, 0x40011a00 +.set CYDEV_UCFG_B1_P5_U0_SIZE, 0x00000070 +.set CYREG_B1_P5_U0_PLD_IT0, 0x40011a00 +.set CYREG_B1_P5_U0_PLD_IT1, 0x40011a04 +.set CYREG_B1_P5_U0_PLD_IT2, 0x40011a08 +.set CYREG_B1_P5_U0_PLD_IT3, 0x40011a0c +.set CYREG_B1_P5_U0_PLD_IT4, 0x40011a10 +.set CYREG_B1_P5_U0_PLD_IT5, 0x40011a14 +.set CYREG_B1_P5_U0_PLD_IT6, 0x40011a18 +.set CYREG_B1_P5_U0_PLD_IT7, 0x40011a1c +.set CYREG_B1_P5_U0_PLD_IT8, 0x40011a20 +.set CYREG_B1_P5_U0_PLD_IT9, 0x40011a24 +.set CYREG_B1_P5_U0_PLD_IT10, 0x40011a28 +.set CYREG_B1_P5_U0_PLD_IT11, 0x40011a2c +.set CYREG_B1_P5_U0_PLD_ORT0, 0x40011a30 +.set CYREG_B1_P5_U0_PLD_ORT1, 0x40011a32 +.set CYREG_B1_P5_U0_PLD_ORT2, 0x40011a34 +.set CYREG_B1_P5_U0_PLD_ORT3, 0x40011a36 +.set CYREG_B1_P5_U0_MC_CFG_CEN_CONST, 0x40011a38 +.set CYREG_B1_P5_U0_MC_CFG_XORFB, 0x40011a3a +.set CYREG_B1_P5_U0_MC_CFG_SET_RESET, 0x40011a3c +.set CYREG_B1_P5_U0_MC_CFG_BYPASS, 0x40011a3e +.set CYREG_B1_P5_U0_CFG0, 0x40011a40 +.set CYREG_B1_P5_U0_CFG1, 0x40011a41 +.set CYREG_B1_P5_U0_CFG2, 0x40011a42 +.set CYREG_B1_P5_U0_CFG3, 0x40011a43 +.set CYREG_B1_P5_U0_CFG4, 0x40011a44 +.set CYREG_B1_P5_U0_CFG5, 0x40011a45 +.set CYREG_B1_P5_U0_CFG6, 0x40011a46 +.set CYREG_B1_P5_U0_CFG7, 0x40011a47 +.set CYREG_B1_P5_U0_CFG8, 0x40011a48 +.set CYREG_B1_P5_U0_CFG9, 0x40011a49 +.set CYREG_B1_P5_U0_CFG10, 0x40011a4a +.set CYREG_B1_P5_U0_CFG11, 0x40011a4b +.set CYREG_B1_P5_U0_CFG12, 0x40011a4c +.set CYREG_B1_P5_U0_CFG13, 0x40011a4d +.set CYREG_B1_P5_U0_CFG14, 0x40011a4e +.set CYREG_B1_P5_U0_CFG15, 0x40011a4f +.set CYREG_B1_P5_U0_CFG16, 0x40011a50 +.set CYREG_B1_P5_U0_CFG17, 0x40011a51 +.set CYREG_B1_P5_U0_CFG18, 0x40011a52 +.set CYREG_B1_P5_U0_CFG19, 0x40011a53 +.set CYREG_B1_P5_U0_CFG20, 0x40011a54 +.set CYREG_B1_P5_U0_CFG21, 0x40011a55 +.set CYREG_B1_P5_U0_CFG22, 0x40011a56 +.set CYREG_B1_P5_U0_CFG23, 0x40011a57 +.set CYREG_B1_P5_U0_CFG24, 0x40011a58 +.set CYREG_B1_P5_U0_CFG25, 0x40011a59 +.set CYREG_B1_P5_U0_CFG26, 0x40011a5a +.set CYREG_B1_P5_U0_CFG27, 0x40011a5b +.set CYREG_B1_P5_U0_CFG28, 0x40011a5c +.set CYREG_B1_P5_U0_CFG29, 0x40011a5d +.set CYREG_B1_P5_U0_CFG30, 0x40011a5e +.set CYREG_B1_P5_U0_CFG31, 0x40011a5f +.set CYREG_B1_P5_U0_DCFG0, 0x40011a60 +.set CYREG_B1_P5_U0_DCFG1, 0x40011a62 +.set CYREG_B1_P5_U0_DCFG2, 0x40011a64 +.set CYREG_B1_P5_U0_DCFG3, 0x40011a66 +.set CYREG_B1_P5_U0_DCFG4, 0x40011a68 +.set CYREG_B1_P5_U0_DCFG5, 0x40011a6a +.set CYREG_B1_P5_U0_DCFG6, 0x40011a6c +.set CYREG_B1_P5_U0_DCFG7, 0x40011a6e +.set CYDEV_UCFG_B1_P5_U1_BASE, 0x40011a80 +.set CYDEV_UCFG_B1_P5_U1_SIZE, 0x00000070 +.set CYREG_B1_P5_U1_PLD_IT0, 0x40011a80 +.set CYREG_B1_P5_U1_PLD_IT1, 0x40011a84 +.set CYREG_B1_P5_U1_PLD_IT2, 0x40011a88 +.set CYREG_B1_P5_U1_PLD_IT3, 0x40011a8c +.set CYREG_B1_P5_U1_PLD_IT4, 0x40011a90 +.set CYREG_B1_P5_U1_PLD_IT5, 0x40011a94 +.set CYREG_B1_P5_U1_PLD_IT6, 0x40011a98 +.set CYREG_B1_P5_U1_PLD_IT7, 0x40011a9c +.set CYREG_B1_P5_U1_PLD_IT8, 0x40011aa0 +.set CYREG_B1_P5_U1_PLD_IT9, 0x40011aa4 +.set CYREG_B1_P5_U1_PLD_IT10, 0x40011aa8 +.set CYREG_B1_P5_U1_PLD_IT11, 0x40011aac +.set CYREG_B1_P5_U1_PLD_ORT0, 0x40011ab0 +.set CYREG_B1_P5_U1_PLD_ORT1, 0x40011ab2 +.set CYREG_B1_P5_U1_PLD_ORT2, 0x40011ab4 +.set CYREG_B1_P5_U1_PLD_ORT3, 0x40011ab6 +.set CYREG_B1_P5_U1_MC_CFG_CEN_CONST, 0x40011ab8 +.set CYREG_B1_P5_U1_MC_CFG_XORFB, 0x40011aba +.set CYREG_B1_P5_U1_MC_CFG_SET_RESET, 0x40011abc +.set CYREG_B1_P5_U1_MC_CFG_BYPASS, 0x40011abe +.set CYREG_B1_P5_U1_CFG0, 0x40011ac0 +.set CYREG_B1_P5_U1_CFG1, 0x40011ac1 +.set CYREG_B1_P5_U1_CFG2, 0x40011ac2 +.set CYREG_B1_P5_U1_CFG3, 0x40011ac3 +.set CYREG_B1_P5_U1_CFG4, 0x40011ac4 +.set CYREG_B1_P5_U1_CFG5, 0x40011ac5 +.set CYREG_B1_P5_U1_CFG6, 0x40011ac6 +.set CYREG_B1_P5_U1_CFG7, 0x40011ac7 +.set CYREG_B1_P5_U1_CFG8, 0x40011ac8 +.set CYREG_B1_P5_U1_CFG9, 0x40011ac9 +.set CYREG_B1_P5_U1_CFG10, 0x40011aca +.set CYREG_B1_P5_U1_CFG11, 0x40011acb +.set CYREG_B1_P5_U1_CFG12, 0x40011acc +.set CYREG_B1_P5_U1_CFG13, 0x40011acd +.set CYREG_B1_P5_U1_CFG14, 0x40011ace +.set CYREG_B1_P5_U1_CFG15, 0x40011acf +.set CYREG_B1_P5_U1_CFG16, 0x40011ad0 +.set CYREG_B1_P5_U1_CFG17, 0x40011ad1 +.set CYREG_B1_P5_U1_CFG18, 0x40011ad2 +.set CYREG_B1_P5_U1_CFG19, 0x40011ad3 +.set CYREG_B1_P5_U1_CFG20, 0x40011ad4 +.set CYREG_B1_P5_U1_CFG21, 0x40011ad5 +.set CYREG_B1_P5_U1_CFG22, 0x40011ad6 +.set CYREG_B1_P5_U1_CFG23, 0x40011ad7 +.set CYREG_B1_P5_U1_CFG24, 0x40011ad8 +.set CYREG_B1_P5_U1_CFG25, 0x40011ad9 +.set CYREG_B1_P5_U1_CFG26, 0x40011ada +.set CYREG_B1_P5_U1_CFG27, 0x40011adb +.set CYREG_B1_P5_U1_CFG28, 0x40011adc +.set CYREG_B1_P5_U1_CFG29, 0x40011add +.set CYREG_B1_P5_U1_CFG30, 0x40011ade +.set CYREG_B1_P5_U1_CFG31, 0x40011adf +.set CYREG_B1_P5_U1_DCFG0, 0x40011ae0 +.set CYREG_B1_P5_U1_DCFG1, 0x40011ae2 +.set CYREG_B1_P5_U1_DCFG2, 0x40011ae4 +.set CYREG_B1_P5_U1_DCFG3, 0x40011ae6 +.set CYREG_B1_P5_U1_DCFG4, 0x40011ae8 +.set CYREG_B1_P5_U1_DCFG5, 0x40011aea +.set CYREG_B1_P5_U1_DCFG6, 0x40011aec +.set CYREG_B1_P5_U1_DCFG7, 0x40011aee +.set CYDEV_UCFG_B1_P5_ROUTE_BASE, 0x40011b00 +.set CYDEV_UCFG_B1_P5_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI0_BASE, 0x40014000 +.set CYDEV_UCFG_DSI0_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI1_BASE, 0x40014100 +.set CYDEV_UCFG_DSI1_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI2_BASE, 0x40014200 +.set CYDEV_UCFG_DSI2_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI3_BASE, 0x40014300 +.set CYDEV_UCFG_DSI3_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI4_BASE, 0x40014400 +.set CYDEV_UCFG_DSI4_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI5_BASE, 0x40014500 +.set CYDEV_UCFG_DSI5_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI6_BASE, 0x40014600 +.set CYDEV_UCFG_DSI6_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI7_BASE, 0x40014700 +.set CYDEV_UCFG_DSI7_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI8_BASE, 0x40014800 +.set CYDEV_UCFG_DSI8_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI9_BASE, 0x40014900 +.set CYDEV_UCFG_DSI9_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI12_BASE, 0x40014c00 +.set CYDEV_UCFG_DSI12_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI13_BASE, 0x40014d00 +.set CYDEV_UCFG_DSI13_SIZE, 0x000000ef +.set CYDEV_UCFG_BCTL0_BASE, 0x40015000 +.set CYDEV_UCFG_BCTL0_SIZE, 0x00000010 +.set CYREG_BCTL0_MDCLK_EN, 0x40015000 +.set CYREG_BCTL0_MBCLK_EN, 0x40015001 +.set CYREG_BCTL0_WAIT_CFG, 0x40015002 +.set CYREG_BCTL0_BANK_CTL, 0x40015003 +.set CYREG_BCTL0_UDB_TEST_3, 0x40015007 +.set CYREG_BCTL0_DCLK_EN0, 0x40015008 +.set CYREG_BCTL0_BCLK_EN0, 0x40015009 +.set CYREG_BCTL0_DCLK_EN1, 0x4001500a +.set CYREG_BCTL0_BCLK_EN1, 0x4001500b +.set CYREG_BCTL0_DCLK_EN2, 0x4001500c +.set CYREG_BCTL0_BCLK_EN2, 0x4001500d +.set CYREG_BCTL0_DCLK_EN3, 0x4001500e +.set CYREG_BCTL0_BCLK_EN3, 0x4001500f +.set CYDEV_UCFG_BCTL1_BASE, 0x40015010 +.set CYDEV_UCFG_BCTL1_SIZE, 0x00000010 +.set CYREG_BCTL1_MDCLK_EN, 0x40015010 +.set CYREG_BCTL1_MBCLK_EN, 0x40015011 +.set CYREG_BCTL1_WAIT_CFG, 0x40015012 +.set CYREG_BCTL1_BANK_CTL, 0x40015013 +.set CYREG_BCTL1_UDB_TEST_3, 0x40015017 +.set CYREG_BCTL1_DCLK_EN0, 0x40015018 +.set CYREG_BCTL1_BCLK_EN0, 0x40015019 +.set CYREG_BCTL1_DCLK_EN1, 0x4001501a +.set CYREG_BCTL1_BCLK_EN1, 0x4001501b +.set CYREG_BCTL1_DCLK_EN2, 0x4001501c +.set CYREG_BCTL1_BCLK_EN2, 0x4001501d +.set CYREG_BCTL1_DCLK_EN3, 0x4001501e +.set CYREG_BCTL1_BCLK_EN3, 0x4001501f +.set CYDEV_IDMUX_BASE, 0x40015100 +.set CYDEV_IDMUX_SIZE, 0x00000016 +.set CYREG_IDMUX_IRQ_CTL0, 0x40015100 +.set CYREG_IDMUX_IRQ_CTL1, 0x40015101 +.set CYREG_IDMUX_IRQ_CTL2, 0x40015102 +.set CYREG_IDMUX_IRQ_CTL3, 0x40015103 +.set CYREG_IDMUX_IRQ_CTL4, 0x40015104 +.set CYREG_IDMUX_IRQ_CTL5, 0x40015105 +.set CYREG_IDMUX_IRQ_CTL6, 0x40015106 +.set CYREG_IDMUX_IRQ_CTL7, 0x40015107 +.set CYREG_IDMUX_DRQ_CTL0, 0x40015110 +.set CYREG_IDMUX_DRQ_CTL1, 0x40015111 +.set CYREG_IDMUX_DRQ_CTL2, 0x40015112 +.set CYREG_IDMUX_DRQ_CTL3, 0x40015113 +.set CYREG_IDMUX_DRQ_CTL4, 0x40015114 +.set CYREG_IDMUX_DRQ_CTL5, 0x40015115 +.set CYDEV_CACHERAM_BASE, 0x40030000 +.set CYDEV_CACHERAM_SIZE, 0x00000400 +.set CYREG_CACHERAM_DATA_MBASE, 0x40030000 +.set CYREG_CACHERAM_DATA_MSIZE, 0x00000400 +.set CYDEV_SFR_BASE, 0x40050100 +.set CYDEV_SFR_SIZE, 0x000000fb +.set CYREG_SFR_GPIO0, 0x40050180 +.set CYREG_SFR_GPIRD0, 0x40050189 +.set CYREG_SFR_GPIO0_SEL, 0x4005018a +.set CYREG_SFR_GPIO1, 0x40050190 +.set CYREG_SFR_GPIRD1, 0x40050191 +.set CYREG_SFR_GPIO2, 0x40050198 +.set CYREG_SFR_GPIRD2, 0x40050199 +.set CYREG_SFR_GPIO2_SEL, 0x4005019a +.set CYREG_SFR_GPIO1_SEL, 0x400501a2 +.set CYREG_SFR_GPIO3, 0x400501b0 +.set CYREG_SFR_GPIRD3, 0x400501b1 +.set CYREG_SFR_GPIO3_SEL, 0x400501b2 +.set CYREG_SFR_GPIO4, 0x400501c0 +.set CYREG_SFR_GPIRD4, 0x400501c1 +.set CYREG_SFR_GPIO4_SEL, 0x400501c2 +.set CYREG_SFR_GPIO5, 0x400501c8 +.set CYREG_SFR_GPIRD5, 0x400501c9 +.set CYREG_SFR_GPIO5_SEL, 0x400501ca +.set CYREG_SFR_GPIO6, 0x400501d8 +.set CYREG_SFR_GPIRD6, 0x400501d9 +.set CYREG_SFR_GPIO6_SEL, 0x400501da +.set CYREG_SFR_GPIO12, 0x400501e8 +.set CYREG_SFR_GPIRD12, 0x400501e9 +.set CYREG_SFR_GPIO12_SEL, 0x400501f2 +.set CYREG_SFR_GPIO15, 0x400501f8 +.set CYREG_SFR_GPIRD15, 0x400501f9 +.set CYREG_SFR_GPIO15_SEL, 0x400501fa +.set CYDEV_P3BA_BASE, 0x40050300 +.set CYDEV_P3BA_SIZE, 0x0000002b +.set CYREG_P3BA_Y_START, 0x40050300 +.set CYREG_P3BA_YROLL, 0x40050301 +.set CYREG_P3BA_YCFG, 0x40050302 +.set CYREG_P3BA_X_START1, 0x40050303 +.set CYREG_P3BA_X_START2, 0x40050304 +.set CYREG_P3BA_XROLL1, 0x40050305 +.set CYREG_P3BA_XROLL2, 0x40050306 +.set CYREG_P3BA_XINC, 0x40050307 +.set CYREG_P3BA_XCFG, 0x40050308 +.set CYREG_P3BA_OFFSETADDR1, 0x40050309 +.set CYREG_P3BA_OFFSETADDR2, 0x4005030a +.set CYREG_P3BA_OFFSETADDR3, 0x4005030b +.set CYREG_P3BA_ABSADDR1, 0x4005030c +.set CYREG_P3BA_ABSADDR2, 0x4005030d +.set CYREG_P3BA_ABSADDR3, 0x4005030e +.set CYREG_P3BA_ABSADDR4, 0x4005030f +.set CYREG_P3BA_DATCFG1, 0x40050310 +.set CYREG_P3BA_DATCFG2, 0x40050311 +.set CYREG_P3BA_CMP_RSLT1, 0x40050314 +.set CYREG_P3BA_CMP_RSLT2, 0x40050315 +.set CYREG_P3BA_CMP_RSLT3, 0x40050316 +.set CYREG_P3BA_CMP_RSLT4, 0x40050317 +.set CYREG_P3BA_DATA_REG1, 0x40050318 +.set CYREG_P3BA_DATA_REG2, 0x40050319 +.set CYREG_P3BA_DATA_REG3, 0x4005031a +.set CYREG_P3BA_DATA_REG4, 0x4005031b +.set CYREG_P3BA_EXP_DATA1, 0x4005031c +.set CYREG_P3BA_EXP_DATA2, 0x4005031d +.set CYREG_P3BA_EXP_DATA3, 0x4005031e +.set CYREG_P3BA_EXP_DATA4, 0x4005031f +.set CYREG_P3BA_MSTR_HRDATA1, 0x40050320 +.set CYREG_P3BA_MSTR_HRDATA2, 0x40050321 +.set CYREG_P3BA_MSTR_HRDATA3, 0x40050322 +.set CYREG_P3BA_MSTR_HRDATA4, 0x40050323 +.set CYREG_P3BA_BIST_EN, 0x40050324 +.set CYREG_P3BA_PHUB_MASTER_SSR, 0x40050325 +.set CYREG_P3BA_SEQCFG1, 0x40050326 +.set CYREG_P3BA_SEQCFG2, 0x40050327 +.set CYREG_P3BA_Y_CURR, 0x40050328 +.set CYREG_P3BA_X_CURR1, 0x40050329 +.set CYREG_P3BA_X_CURR2, 0x4005032a +.set CYDEV_PANTHER_BASE, 0x40080000 +.set CYDEV_PANTHER_SIZE, 0x00000020 +.set CYREG_PANTHER_STCALIB_CFG, 0x40080000 +.set CYREG_PANTHER_WAITPIPE, 0x40080004 +.set CYREG_PANTHER_TRACE_CFG, 0x40080008 +.set CYREG_PANTHER_DBG_CFG, 0x4008000c +.set CYREG_PANTHER_CM3_LCKRST_STAT, 0x40080018 +.set CYREG_PANTHER_DEVICE_ID, 0x4008001c +.set CYDEV_FLSECC_BASE, 0x48000000 +.set CYDEV_FLSECC_SIZE, 0x00008000 +.set CYREG_FLSECC_DATA_MBASE, 0x48000000 +.set CYREG_FLSECC_DATA_MSIZE, 0x00008000 +.set CYDEV_FLSHID_BASE, 0x49000000 +.set CYDEV_FLSHID_SIZE, 0x00000200 +.set CYREG_FLSHID_RSVD_MBASE, 0x49000000 +.set CYREG_FLSHID_RSVD_MSIZE, 0x00000080 +.set CYREG_FLSHID_CUST_MDATA_MBASE, 0x49000080 +.set CYREG_FLSHID_CUST_MDATA_MSIZE, 0x00000080 +.set CYDEV_FLSHID_CUST_TABLES_BASE, 0x49000100 +.set CYDEV_FLSHID_CUST_TABLES_SIZE, 0x00000040 +.set CYREG_FLSHID_CUST_TABLES_Y_LOC, 0x49000100 +.set CYREG_FLSHID_CUST_TABLES_X_LOC, 0x49000101 +.set CYREG_FLSHID_CUST_TABLES_WAFER_NUM, 0x49000102 +.set CYREG_FLSHID_CUST_TABLES_LOT_LSB, 0x49000103 +.set CYREG_FLSHID_CUST_TABLES_LOT_MSB, 0x49000104 +.set CYREG_FLSHID_CUST_TABLES_WRK_WK, 0x49000105 +.set CYREG_FLSHID_CUST_TABLES_FAB_YR, 0x49000106 +.set CYREG_FLSHID_CUST_TABLES_MINOR, 0x49000107 +.set CYREG_FLSHID_CUST_TABLES_IMO_3MHZ, 0x49000108 +.set CYREG_FLSHID_CUST_TABLES_IMO_6MHZ, 0x49000109 +.set CYREG_FLSHID_CUST_TABLES_IMO_12MHZ, 0x4900010a +.set CYREG_FLSHID_CUST_TABLES_IMO_24MHZ, 0x4900010b +.set CYREG_FLSHID_CUST_TABLES_IMO_67MHZ, 0x4900010c +.set CYREG_FLSHID_CUST_TABLES_IMO_80MHZ, 0x4900010d +.set CYREG_FLSHID_CUST_TABLES_IMO_92MHZ, 0x4900010e +.set CYREG_FLSHID_CUST_TABLES_IMO_USB, 0x4900010f +.set CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS, 0x49000110 +.set CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS, 0x49000111 +.set CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS, 0x49000112 +.set CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS, 0x49000113 +.set CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS, 0x49000114 +.set CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS, 0x49000115 +.set CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS, 0x49000116 +.set CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS, 0x49000117 +.set CYREG_FLSHID_CUST_TABLES_DEC_M1, 0x49000118 +.set CYREG_FLSHID_CUST_TABLES_DEC_M2, 0x49000119 +.set CYREG_FLSHID_CUST_TABLES_DEC_M3, 0x4900011a +.set CYREG_FLSHID_CUST_TABLES_DEC_M4, 0x4900011b +.set CYREG_FLSHID_CUST_TABLES_DEC_M5, 0x4900011c +.set CYREG_FLSHID_CUST_TABLES_DEC_M6, 0x4900011d +.set CYREG_FLSHID_CUST_TABLES_DEC_M7, 0x4900011e +.set CYREG_FLSHID_CUST_TABLES_DEC_M8, 0x4900011f +.set CYREG_FLSHID_CUST_TABLES_DAC0_M1, 0x49000120 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M2, 0x49000121 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M3, 0x49000122 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M4, 0x49000123 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M5, 0x49000124 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M6, 0x49000125 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M7, 0x49000126 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M8, 0x49000127 +.set CYREG_FLSHID_CUST_TABLES_DAC2_M1, 0x49000128 +.set CYREG_FLSHID_CUST_TABLES_DAC2_M2, 0x49000129 +.set CYREG_FLSHID_CUST_TABLES_DAC2_M3, 0x4900012a +.set CYREG_FLSHID_CUST_TABLES_DAC2_M4, 0x4900012b +.set CYREG_FLSHID_CUST_TABLES_DAC2_M5, 0x4900012c +.set CYREG_FLSHID_CUST_TABLES_DAC2_M6, 0x4900012d +.set CYREG_FLSHID_CUST_TABLES_DAC2_M7, 0x4900012e +.set CYREG_FLSHID_CUST_TABLES_DAC2_M8, 0x4900012f +.set CYREG_FLSHID_CUST_TABLES_DAC1_M1, 0x49000130 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M2, 0x49000131 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M3, 0x49000132 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M4, 0x49000133 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M5, 0x49000134 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M6, 0x49000135 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M7, 0x49000136 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M8, 0x49000137 +.set CYREG_FLSHID_CUST_TABLES_DAC3_M1, 0x49000138 +.set CYREG_FLSHID_CUST_TABLES_DAC3_M2, 0x49000139 +.set CYREG_FLSHID_CUST_TABLES_DAC3_M3, 0x4900013a +.set CYREG_FLSHID_CUST_TABLES_DAC3_M4, 0x4900013b +.set CYREG_FLSHID_CUST_TABLES_DAC3_M5, 0x4900013c +.set CYREG_FLSHID_CUST_TABLES_DAC3_M6, 0x4900013d +.set CYREG_FLSHID_CUST_TABLES_DAC3_M7, 0x4900013e +.set CYREG_FLSHID_CUST_TABLES_DAC3_M8, 0x4900013f +.set CYDEV_FLSHID_MFG_CFG_BASE, 0x49000180 +.set CYDEV_FLSHID_MFG_CFG_SIZE, 0x00000080 +.set CYREG_FLSHID_MFG_CFG_IMO_TR1, 0x49000188 +.set CYREG_FLSHID_MFG_CFG_CMP0_TR0, 0x490001ac +.set CYREG_FLSHID_MFG_CFG_CMP1_TR0, 0x490001ae +.set CYREG_FLSHID_MFG_CFG_CMP2_TR0, 0x490001b0 +.set CYREG_FLSHID_MFG_CFG_CMP3_TR0, 0x490001b2 +.set CYREG_FLSHID_MFG_CFG_CMP0_TR1, 0x490001b4 +.set CYREG_FLSHID_MFG_CFG_CMP1_TR1, 0x490001b6 +.set CYREG_FLSHID_MFG_CFG_CMP2_TR1, 0x490001b8 +.set CYREG_FLSHID_MFG_CFG_CMP3_TR1, 0x490001ba +.set CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM, 0x490001ce +.set CYDEV_EXTMEM_BASE, 0x60000000 +.set CYDEV_EXTMEM_SIZE, 0x00800000 +.set CYREG_EXTMEM_DATA_MBASE, 0x60000000 +.set CYREG_EXTMEM_DATA_MSIZE, 0x00800000 +.set CYDEV_ITM_BASE, 0xe0000000 +.set CYDEV_ITM_SIZE, 0x00001000 +.set CYREG_ITM_TRACE_EN, 0xe0000e00 +.set CYREG_ITM_TRACE_PRIVILEGE, 0xe0000e40 +.set CYREG_ITM_TRACE_CTRL, 0xe0000e80 +.set CYREG_ITM_LOCK_ACCESS, 0xe0000fb0 +.set CYREG_ITM_LOCK_STATUS, 0xe0000fb4 +.set CYREG_ITM_PID4, 0xe0000fd0 +.set CYREG_ITM_PID5, 0xe0000fd4 +.set CYREG_ITM_PID6, 0xe0000fd8 +.set CYREG_ITM_PID7, 0xe0000fdc +.set CYREG_ITM_PID0, 0xe0000fe0 +.set CYREG_ITM_PID1, 0xe0000fe4 +.set CYREG_ITM_PID2, 0xe0000fe8 +.set CYREG_ITM_PID3, 0xe0000fec +.set CYREG_ITM_CID0, 0xe0000ff0 +.set CYREG_ITM_CID1, 0xe0000ff4 +.set CYREG_ITM_CID2, 0xe0000ff8 +.set CYREG_ITM_CID3, 0xe0000ffc +.set CYDEV_DWT_BASE, 0xe0001000 +.set CYDEV_DWT_SIZE, 0x0000005c +.set CYREG_DWT_CTRL, 0xe0001000 +.set CYREG_DWT_CYCLE_COUNT, 0xe0001004 +.set CYREG_DWT_CPI_COUNT, 0xe0001008 +.set CYREG_DWT_EXC_OVHD_COUNT, 0xe000100c +.set CYREG_DWT_SLEEP_COUNT, 0xe0001010 +.set CYREG_DWT_LSU_COUNT, 0xe0001014 +.set CYREG_DWT_FOLD_COUNT, 0xe0001018 +.set CYREG_DWT_PC_SAMPLE, 0xe000101c +.set CYREG_DWT_COMP_0, 0xe0001020 +.set CYREG_DWT_MASK_0, 0xe0001024 +.set CYREG_DWT_FUNCTION_0, 0xe0001028 +.set CYREG_DWT_COMP_1, 0xe0001030 +.set CYREG_DWT_MASK_1, 0xe0001034 +.set CYREG_DWT_FUNCTION_1, 0xe0001038 +.set CYREG_DWT_COMP_2, 0xe0001040 +.set CYREG_DWT_MASK_2, 0xe0001044 +.set CYREG_DWT_FUNCTION_2, 0xe0001048 +.set CYREG_DWT_COMP_3, 0xe0001050 +.set CYREG_DWT_MASK_3, 0xe0001054 +.set CYREG_DWT_FUNCTION_3, 0xe0001058 +.set CYDEV_FPB_BASE, 0xe0002000 +.set CYDEV_FPB_SIZE, 0x00001000 +.set CYREG_FPB_CTRL, 0xe0002000 +.set CYREG_FPB_REMAP, 0xe0002004 +.set CYREG_FPB_FP_COMP_0, 0xe0002008 +.set CYREG_FPB_FP_COMP_1, 0xe000200c +.set CYREG_FPB_FP_COMP_2, 0xe0002010 +.set CYREG_FPB_FP_COMP_3, 0xe0002014 +.set CYREG_FPB_FP_COMP_4, 0xe0002018 +.set CYREG_FPB_FP_COMP_5, 0xe000201c +.set CYREG_FPB_FP_COMP_6, 0xe0002020 +.set CYREG_FPB_FP_COMP_7, 0xe0002024 +.set CYREG_FPB_PID4, 0xe0002fd0 +.set CYREG_FPB_PID5, 0xe0002fd4 +.set CYREG_FPB_PID6, 0xe0002fd8 +.set CYREG_FPB_PID7, 0xe0002fdc +.set CYREG_FPB_PID0, 0xe0002fe0 +.set CYREG_FPB_PID1, 0xe0002fe4 +.set CYREG_FPB_PID2, 0xe0002fe8 +.set CYREG_FPB_PID3, 0xe0002fec +.set CYREG_FPB_CID0, 0xe0002ff0 +.set CYREG_FPB_CID1, 0xe0002ff4 +.set CYREG_FPB_CID2, 0xe0002ff8 +.set CYREG_FPB_CID3, 0xe0002ffc +.set CYDEV_NVIC_BASE, 0xe000e000 +.set CYDEV_NVIC_SIZE, 0x00000d3c +.set CYREG_NVIC_INT_CTL_TYPE, 0xe000e004 +.set CYREG_NVIC_SYSTICK_CTL, 0xe000e010 +.set CYREG_NVIC_SYSTICK_RELOAD, 0xe000e014 +.set CYREG_NVIC_SYSTICK_CURRENT, 0xe000e018 +.set CYREG_NVIC_SYSTICK_CAL, 0xe000e01c +.set CYREG_NVIC_SETENA0, 0xe000e100 +.set CYREG_NVIC_CLRENA0, 0xe000e180 +.set CYREG_NVIC_SETPEND0, 0xe000e200 +.set CYREG_NVIC_CLRPEND0, 0xe000e280 +.set CYREG_NVIC_ACTIVE0, 0xe000e300 +.set CYREG_NVIC_PRI_0, 0xe000e400 +.set CYREG_NVIC_PRI_1, 0xe000e401 +.set CYREG_NVIC_PRI_2, 0xe000e402 +.set CYREG_NVIC_PRI_3, 0xe000e403 +.set CYREG_NVIC_PRI_4, 0xe000e404 +.set CYREG_NVIC_PRI_5, 0xe000e405 +.set CYREG_NVIC_PRI_6, 0xe000e406 +.set CYREG_NVIC_PRI_7, 0xe000e407 +.set CYREG_NVIC_PRI_8, 0xe000e408 +.set CYREG_NVIC_PRI_9, 0xe000e409 +.set CYREG_NVIC_PRI_10, 0xe000e40a +.set CYREG_NVIC_PRI_11, 0xe000e40b +.set CYREG_NVIC_PRI_12, 0xe000e40c +.set CYREG_NVIC_PRI_13, 0xe000e40d +.set CYREG_NVIC_PRI_14, 0xe000e40e +.set CYREG_NVIC_PRI_15, 0xe000e40f +.set CYREG_NVIC_PRI_16, 0xe000e410 +.set CYREG_NVIC_PRI_17, 0xe000e411 +.set CYREG_NVIC_PRI_18, 0xe000e412 +.set CYREG_NVIC_PRI_19, 0xe000e413 +.set CYREG_NVIC_PRI_20, 0xe000e414 +.set CYREG_NVIC_PRI_21, 0xe000e415 +.set CYREG_NVIC_PRI_22, 0xe000e416 +.set CYREG_NVIC_PRI_23, 0xe000e417 +.set CYREG_NVIC_PRI_24, 0xe000e418 +.set CYREG_NVIC_PRI_25, 0xe000e419 +.set CYREG_NVIC_PRI_26, 0xe000e41a +.set CYREG_NVIC_PRI_27, 0xe000e41b +.set CYREG_NVIC_PRI_28, 0xe000e41c +.set CYREG_NVIC_PRI_29, 0xe000e41d +.set CYREG_NVIC_PRI_30, 0xe000e41e +.set CYREG_NVIC_PRI_31, 0xe000e41f +.set CYREG_NVIC_CPUID_BASE, 0xe000ed00 +.set CYREG_NVIC_INTR_CTRL_STATE, 0xe000ed04 +.set CYREG_NVIC_VECT_OFFSET, 0xe000ed08 +.set CYREG_NVIC_APPLN_INTR, 0xe000ed0c +.set CYREG_NVIC_SYSTEM_CONTROL, 0xe000ed10 +.set CYREG_NVIC_CFG_CONTROL, 0xe000ed14 +.set CYREG_NVIC_SYS_PRIO_HANDLER_4_7, 0xe000ed18 +.set CYREG_NVIC_SYS_PRIO_HANDLER_8_11, 0xe000ed1c +.set CYREG_NVIC_SYS_PRIO_HANDLER_12_15, 0xe000ed20 +.set CYREG_NVIC_SYS_HANDLER_CSR, 0xe000ed24 +.set CYREG_NVIC_MEMMAN_FAULT_STATUS, 0xe000ed28 +.set CYREG_NVIC_BUS_FAULT_STATUS, 0xe000ed29 +.set CYREG_NVIC_USAGE_FAULT_STATUS, 0xe000ed2a +.set CYREG_NVIC_HARD_FAULT_STATUS, 0xe000ed2c +.set CYREG_NVIC_DEBUG_FAULT_STATUS, 0xe000ed30 +.set CYREG_NVIC_MEMMAN_FAULT_ADD, 0xe000ed34 +.set CYREG_NVIC_BUS_FAULT_ADD, 0xe000ed38 +.set CYDEV_CORE_DBG_BASE, 0xe000edf0 +.set CYDEV_CORE_DBG_SIZE, 0x00000010 +.set CYREG_CORE_DBG_DBG_HLT_CS, 0xe000edf0 +.set CYREG_CORE_DBG_DBG_REG_SEL, 0xe000edf4 +.set CYREG_CORE_DBG_DBG_REG_DATA, 0xe000edf8 +.set CYREG_CORE_DBG_EXC_MON_CTL, 0xe000edfc +.set CYDEV_TPIU_BASE, 0xe0040000 +.set CYDEV_TPIU_SIZE, 0x00001000 +.set CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ, 0xe0040000 +.set CYREG_TPIU_CURRENT_SYNC_PRT_SZ, 0xe0040004 +.set CYREG_TPIU_ASYNC_CLK_PRESCALER, 0xe0040010 +.set CYREG_TPIU_PROTOCOL, 0xe00400f0 +.set CYREG_TPIU_FORM_FLUSH_STAT, 0xe0040300 +.set CYREG_TPIU_FORM_FLUSH_CTRL, 0xe0040304 +.set CYREG_TPIU_TRIGGER, 0xe0040ee8 +.set CYREG_TPIU_ITETMDATA, 0xe0040eec +.set CYREG_TPIU_ITATBCTR2, 0xe0040ef0 +.set CYREG_TPIU_ITATBCTR0, 0xe0040ef8 +.set CYREG_TPIU_ITITMDATA, 0xe0040efc +.set CYREG_TPIU_ITCTRL, 0xe0040f00 +.set CYREG_TPIU_DEVID, 0xe0040fc8 +.set CYREG_TPIU_DEVTYPE, 0xe0040fcc +.set CYREG_TPIU_PID4, 0xe0040fd0 +.set CYREG_TPIU_PID5, 0xe0040fd4 +.set CYREG_TPIU_PID6, 0xe0040fd8 +.set CYREG_TPIU_PID7, 0xe0040fdc +.set CYREG_TPIU_PID0, 0xe0040fe0 +.set CYREG_TPIU_PID1, 0xe0040fe4 +.set CYREG_TPIU_PID2, 0xe0040fe8 +.set CYREG_TPIU_PID3, 0xe0040fec +.set CYREG_TPIU_CID0, 0xe0040ff0 +.set CYREG_TPIU_CID1, 0xe0040ff4 +.set CYREG_TPIU_CID2, 0xe0040ff8 +.set CYREG_TPIU_CID3, 0xe0040ffc +.set CYDEV_ETM_BASE, 0xe0041000 +.set CYDEV_ETM_SIZE, 0x00001000 +.set CYREG_ETM_CTL, 0xe0041000 +.set CYREG_ETM_CFG_CODE, 0xe0041004 +.set CYREG_ETM_TRIG_EVENT, 0xe0041008 +.set CYREG_ETM_STATUS, 0xe0041010 +.set CYREG_ETM_SYS_CFG, 0xe0041014 +.set CYREG_ETM_TRACE_ENB_EVENT, 0xe0041020 +.set CYREG_ETM_TRACE_EN_CTRL1, 0xe0041024 +.set CYREG_ETM_FIFOFULL_LEVEL, 0xe004102c +.set CYREG_ETM_SYNC_FREQ, 0xe00411e0 +.set CYREG_ETM_ETM_ID, 0xe00411e4 +.set CYREG_ETM_CFG_CODE_EXT, 0xe00411e8 +.set CYREG_ETM_TR_SS_EMBICE_CTRL, 0xe00411f0 +.set CYREG_ETM_CS_TRACE_ID, 0xe0041200 +.set CYREG_ETM_OS_LOCK_ACCESS, 0xe0041300 +.set CYREG_ETM_OS_LOCK_STATUS, 0xe0041304 +.set CYREG_ETM_PDSR, 0xe0041314 +.set CYREG_ETM_ITMISCIN, 0xe0041ee0 +.set CYREG_ETM_ITTRIGOUT, 0xe0041ee8 +.set CYREG_ETM_ITATBCTR2, 0xe0041ef0 +.set CYREG_ETM_ITATBCTR0, 0xe0041ef8 +.set CYREG_ETM_INT_MODE_CTRL, 0xe0041f00 +.set CYREG_ETM_CLM_TAG_SET, 0xe0041fa0 +.set CYREG_ETM_CLM_TAG_CLR, 0xe0041fa4 +.set CYREG_ETM_LOCK_ACCESS, 0xe0041fb0 +.set CYREG_ETM_LOCK_STATUS, 0xe0041fb4 +.set CYREG_ETM_AUTH_STATUS, 0xe0041fb8 +.set CYREG_ETM_DEV_TYPE, 0xe0041fcc +.set CYREG_ETM_PID4, 0xe0041fd0 +.set CYREG_ETM_PID5, 0xe0041fd4 +.set CYREG_ETM_PID6, 0xe0041fd8 +.set CYREG_ETM_PID7, 0xe0041fdc +.set CYREG_ETM_PID0, 0xe0041fe0 +.set CYREG_ETM_PID1, 0xe0041fe4 +.set CYREG_ETM_PID2, 0xe0041fe8 +.set CYREG_ETM_PID3, 0xe0041fec +.set CYREG_ETM_CID0, 0xe0041ff0 +.set CYREG_ETM_CID1, 0xe0041ff4 +.set CYREG_ETM_CID2, 0xe0041ff8 +.set CYREG_ETM_CID3, 0xe0041ffc +.set CYDEV_ROM_TABLE_BASE, 0xe00ff000 +.set CYDEV_ROM_TABLE_SIZE, 0x00001000 +.set CYREG_ROM_TABLE_NVIC, 0xe00ff000 +.set CYREG_ROM_TABLE_DWT, 0xe00ff004 +.set CYREG_ROM_TABLE_FPB, 0xe00ff008 +.set CYREG_ROM_TABLE_ITM, 0xe00ff00c +.set CYREG_ROM_TABLE_TPIU, 0xe00ff010 +.set CYREG_ROM_TABLE_ETM, 0xe00ff014 +.set CYREG_ROM_TABLE_END, 0xe00ff018 +.set CYREG_ROM_TABLE_MEMTYPE, 0xe00fffcc +.set CYREG_ROM_TABLE_PID4, 0xe00fffd0 +.set CYREG_ROM_TABLE_PID5, 0xe00fffd4 +.set CYREG_ROM_TABLE_PID6, 0xe00fffd8 +.set CYREG_ROM_TABLE_PID7, 0xe00fffdc +.set CYREG_ROM_TABLE_PID0, 0xe00fffe0 +.set CYREG_ROM_TABLE_PID1, 0xe00fffe4 +.set CYREG_ROM_TABLE_PID2, 0xe00fffe8 +.set CYREG_ROM_TABLE_PID3, 0xe00fffec +.set CYREG_ROM_TABLE_CID0, 0xe00ffff0 +.set CYREG_ROM_TABLE_CID1, 0xe00ffff4 +.set CYREG_ROM_TABLE_CID2, 0xe00ffff8 +.set CYREG_ROM_TABLE_CID3, 0xe00ffffc +.set CYDEV_FLS_SIZE, CYDEV_FLASH_SIZE +.set CYDEV_ECC_BASE, CYDEV_FLSECC_BASE +.set CYDEV_FLS_SECTOR_SIZE, 0x00010000 +.set CYDEV_FLS_ROW_SIZE, 0x00000100 +.set CYDEV_ECC_SECTOR_SIZE, 0x00002000 +.set CYDEV_ECC_ROW_SIZE, 0x00000020 +.set CYDEV_EEPROM_SECTOR_SIZE, 0x00000400 +.set CYDEV_EEPROM_ROW_SIZE, 0x00000010 +.set CYDEV_PERIPH_BASE, CYDEV_CLKDIST_BASE +.set CYCLK_LD_DISABLE, 0x00000004 +.set CYCLK_LD_SYNC_EN, 0x00000002 +.set CYCLK_LD_LOAD, 0x00000001 +.set CYCLK_PIPE, 0x00000080 +.set CYCLK_SSS, 0x00000040 +.set CYCLK_EARLY, 0x00000020 +.set CYCLK_DUTY, 0x00000010 +.set CYCLK_SYNC, 0x00000008 +.set CYCLK_SRC_SEL_CLK_SYNC_D, 0 +.set CYCLK_SRC_SEL_SYNC_DIG, 0 +.set CYCLK_SRC_SEL_IMO, 1 +.set CYCLK_SRC_SEL_XTAL_MHZ, 2 +.set CYCLK_SRC_SEL_XTALM, 2 +.set CYCLK_SRC_SEL_ILO, 3 +.set CYCLK_SRC_SEL_PLL, 4 +.set CYCLK_SRC_SEL_XTAL_KHZ, 5 +.set CYCLK_SRC_SEL_XTALK, 5 +.set CYCLK_SRC_SEL_DSI_G, 6 +.set CYCLK_SRC_SEL_DSI_D, 7 +.set CYCLK_SRC_SEL_CLK_SYNC_A, 0 +.set CYCLK_SRC_SEL_DSI_A, 7 diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydeviceiar.inc b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydeviceiar.inc new file mode 100755 index 00000000..8f6fcc72 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydeviceiar.inc @@ -0,0 +1,5356 @@ +; +; FILENAME: cydeviceiar.inc +; OBSOLETE: Do not use this file. Use the _trm version instead. +; PSoC Creator 3.0 Component Pack 7 +; +; DESCRIPTION: +; This file provides all of the address values for the entire PSoC device. +; +;------------------------------------------------------------------------------- +; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + +#define CYDEV_FLASH_BASE 0x00000000 +#define CYDEV_FLASH_SIZE 0x00020000 +#define CYDEV_FLASH_DATA_MBASE 0x00000000 +#define CYDEV_FLASH_DATA_MSIZE 0x00020000 +#define CYDEV_SRAM_BASE 0x1fffc000 +#define CYDEV_SRAM_SIZE 0x00008000 +#define CYDEV_SRAM_CODE64K_MBASE 0x1fff8000 +#define CYDEV_SRAM_CODE64K_MSIZE 0x00004000 +#define CYDEV_SRAM_CODE32K_MBASE 0x1fffc000 +#define CYDEV_SRAM_CODE32K_MSIZE 0x00002000 +#define CYDEV_SRAM_CODE16K_MBASE 0x1fffe000 +#define CYDEV_SRAM_CODE16K_MSIZE 0x00001000 +#define CYDEV_SRAM_CODE_MBASE 0x1fffc000 +#define CYDEV_SRAM_CODE_MSIZE 0x00004000 +#define CYDEV_SRAM_DATA_MBASE 0x20000000 +#define CYDEV_SRAM_DATA_MSIZE 0x00004000 +#define CYDEV_SRAM_DATA16K_MBASE 0x20001000 +#define CYDEV_SRAM_DATA16K_MSIZE 0x00001000 +#define CYDEV_SRAM_DATA32K_MBASE 0x20002000 +#define CYDEV_SRAM_DATA32K_MSIZE 0x00002000 +#define CYDEV_SRAM_DATA64K_MBASE 0x20004000 +#define CYDEV_SRAM_DATA64K_MSIZE 0x00004000 +#define CYDEV_DMA_BASE 0x20008000 +#define CYDEV_DMA_SIZE 0x00008000 +#define CYDEV_DMA_SRAM64K_MBASE 0x20008000 +#define CYDEV_DMA_SRAM64K_MSIZE 0x00004000 +#define CYDEV_DMA_SRAM32K_MBASE 0x2000c000 +#define CYDEV_DMA_SRAM32K_MSIZE 0x00002000 +#define CYDEV_DMA_SRAM16K_MBASE 0x2000e000 +#define CYDEV_DMA_SRAM16K_MSIZE 0x00001000 +#define CYDEV_DMA_SRAM_MBASE 0x2000f000 +#define CYDEV_DMA_SRAM_MSIZE 0x00001000 +#define CYDEV_CLKDIST_BASE 0x40004000 +#define CYDEV_CLKDIST_SIZE 0x00000110 +#define CYDEV_CLKDIST_CR 0x40004000 +#define CYDEV_CLKDIST_LD 0x40004001 +#define CYDEV_CLKDIST_WRK0 0x40004002 +#define CYDEV_CLKDIST_WRK1 0x40004003 +#define CYDEV_CLKDIST_MSTR0 0x40004004 +#define CYDEV_CLKDIST_MSTR1 0x40004005 +#define CYDEV_CLKDIST_BCFG0 0x40004006 +#define CYDEV_CLKDIST_BCFG1 0x40004007 +#define CYDEV_CLKDIST_BCFG2 0x40004008 +#define CYDEV_CLKDIST_UCFG 0x40004009 +#define CYDEV_CLKDIST_DLY0 0x4000400a +#define CYDEV_CLKDIST_DLY1 0x4000400b +#define CYDEV_CLKDIST_DMASK 0x40004010 +#define CYDEV_CLKDIST_AMASK 0x40004014 +#define CYDEV_CLKDIST_DCFG0_BASE 0x40004080 +#define CYDEV_CLKDIST_DCFG0_SIZE 0x00000003 +#define CYDEV_CLKDIST_DCFG0_CFG0 0x40004080 +#define CYDEV_CLKDIST_DCFG0_CFG1 0x40004081 +#define CYDEV_CLKDIST_DCFG0_CFG2 0x40004082 +#define CYDEV_CLKDIST_DCFG1_BASE 0x40004084 +#define CYDEV_CLKDIST_DCFG1_SIZE 0x00000003 +#define CYDEV_CLKDIST_DCFG1_CFG0 0x40004084 +#define CYDEV_CLKDIST_DCFG1_CFG1 0x40004085 +#define CYDEV_CLKDIST_DCFG1_CFG2 0x40004086 +#define CYDEV_CLKDIST_DCFG2_BASE 0x40004088 +#define CYDEV_CLKDIST_DCFG2_SIZE 0x00000003 +#define CYDEV_CLKDIST_DCFG2_CFG0 0x40004088 +#define CYDEV_CLKDIST_DCFG2_CFG1 0x40004089 +#define CYDEV_CLKDIST_DCFG2_CFG2 0x4000408a +#define CYDEV_CLKDIST_DCFG3_BASE 0x4000408c +#define CYDEV_CLKDIST_DCFG3_SIZE 0x00000003 +#define CYDEV_CLKDIST_DCFG3_CFG0 0x4000408c +#define CYDEV_CLKDIST_DCFG3_CFG1 0x4000408d +#define CYDEV_CLKDIST_DCFG3_CFG2 0x4000408e +#define CYDEV_CLKDIST_DCFG4_BASE 0x40004090 +#define CYDEV_CLKDIST_DCFG4_SIZE 0x00000003 +#define CYDEV_CLKDIST_DCFG4_CFG0 0x40004090 +#define CYDEV_CLKDIST_DCFG4_CFG1 0x40004091 +#define CYDEV_CLKDIST_DCFG4_CFG2 0x40004092 +#define CYDEV_CLKDIST_DCFG5_BASE 0x40004094 +#define CYDEV_CLKDIST_DCFG5_SIZE 0x00000003 +#define CYDEV_CLKDIST_DCFG5_CFG0 0x40004094 +#define CYDEV_CLKDIST_DCFG5_CFG1 0x40004095 +#define CYDEV_CLKDIST_DCFG5_CFG2 0x40004096 +#define CYDEV_CLKDIST_DCFG6_BASE 0x40004098 +#define CYDEV_CLKDIST_DCFG6_SIZE 0x00000003 +#define CYDEV_CLKDIST_DCFG6_CFG0 0x40004098 +#define CYDEV_CLKDIST_DCFG6_CFG1 0x40004099 +#define CYDEV_CLKDIST_DCFG6_CFG2 0x4000409a +#define CYDEV_CLKDIST_DCFG7_BASE 0x4000409c +#define CYDEV_CLKDIST_DCFG7_SIZE 0x00000003 +#define CYDEV_CLKDIST_DCFG7_CFG0 0x4000409c +#define CYDEV_CLKDIST_DCFG7_CFG1 0x4000409d +#define CYDEV_CLKDIST_DCFG7_CFG2 0x4000409e +#define CYDEV_CLKDIST_ACFG0_BASE 0x40004100 +#define CYDEV_CLKDIST_ACFG0_SIZE 0x00000004 +#define CYDEV_CLKDIST_ACFG0_CFG0 0x40004100 +#define CYDEV_CLKDIST_ACFG0_CFG1 0x40004101 +#define CYDEV_CLKDIST_ACFG0_CFG2 0x40004102 +#define CYDEV_CLKDIST_ACFG0_CFG3 0x40004103 +#define CYDEV_CLKDIST_ACFG1_BASE 0x40004104 +#define CYDEV_CLKDIST_ACFG1_SIZE 0x00000004 +#define CYDEV_CLKDIST_ACFG1_CFG0 0x40004104 +#define CYDEV_CLKDIST_ACFG1_CFG1 0x40004105 +#define CYDEV_CLKDIST_ACFG1_CFG2 0x40004106 +#define CYDEV_CLKDIST_ACFG1_CFG3 0x40004107 +#define CYDEV_CLKDIST_ACFG2_BASE 0x40004108 +#define CYDEV_CLKDIST_ACFG2_SIZE 0x00000004 +#define CYDEV_CLKDIST_ACFG2_CFG0 0x40004108 +#define CYDEV_CLKDIST_ACFG2_CFG1 0x40004109 +#define CYDEV_CLKDIST_ACFG2_CFG2 0x4000410a +#define CYDEV_CLKDIST_ACFG2_CFG3 0x4000410b +#define CYDEV_CLKDIST_ACFG3_BASE 0x4000410c +#define CYDEV_CLKDIST_ACFG3_SIZE 0x00000004 +#define CYDEV_CLKDIST_ACFG3_CFG0 0x4000410c +#define CYDEV_CLKDIST_ACFG3_CFG1 0x4000410d +#define CYDEV_CLKDIST_ACFG3_CFG2 0x4000410e +#define CYDEV_CLKDIST_ACFG3_CFG3 0x4000410f +#define CYDEV_FASTCLK_BASE 0x40004200 +#define CYDEV_FASTCLK_SIZE 0x00000026 +#define CYDEV_FASTCLK_IMO_BASE 0x40004200 +#define CYDEV_FASTCLK_IMO_SIZE 0x00000001 +#define CYDEV_FASTCLK_IMO_CR 0x40004200 +#define CYDEV_FASTCLK_XMHZ_BASE 0x40004210 +#define CYDEV_FASTCLK_XMHZ_SIZE 0x00000004 +#define CYDEV_FASTCLK_XMHZ_CSR 0x40004210 +#define CYDEV_FASTCLK_XMHZ_CFG0 0x40004212 +#define CYDEV_FASTCLK_XMHZ_CFG1 0x40004213 +#define CYDEV_FASTCLK_PLL_BASE 0x40004220 +#define CYDEV_FASTCLK_PLL_SIZE 0x00000006 +#define CYDEV_FASTCLK_PLL_CFG0 0x40004220 +#define CYDEV_FASTCLK_PLL_CFG1 0x40004221 +#define CYDEV_FASTCLK_PLL_P 0x40004222 +#define CYDEV_FASTCLK_PLL_Q 0x40004223 +#define CYDEV_FASTCLK_PLL_SR 0x40004225 +#define CYDEV_SLOWCLK_BASE 0x40004300 +#define CYDEV_SLOWCLK_SIZE 0x0000000b +#define CYDEV_SLOWCLK_ILO_BASE 0x40004300 +#define CYDEV_SLOWCLK_ILO_SIZE 0x00000002 +#define CYDEV_SLOWCLK_ILO_CR0 0x40004300 +#define CYDEV_SLOWCLK_ILO_CR1 0x40004301 +#define CYDEV_SLOWCLK_X32_BASE 0x40004308 +#define CYDEV_SLOWCLK_X32_SIZE 0x00000003 +#define CYDEV_SLOWCLK_X32_CR 0x40004308 +#define CYDEV_SLOWCLK_X32_CFG 0x40004309 +#define CYDEV_SLOWCLK_X32_TST 0x4000430a +#define CYDEV_BOOST_BASE 0x40004320 +#define CYDEV_BOOST_SIZE 0x00000007 +#define CYDEV_BOOST_CR0 0x40004320 +#define CYDEV_BOOST_CR1 0x40004321 +#define CYDEV_BOOST_CR2 0x40004322 +#define CYDEV_BOOST_CR3 0x40004323 +#define CYDEV_BOOST_SR 0x40004324 +#define CYDEV_BOOST_CR4 0x40004325 +#define CYDEV_BOOST_SR2 0x40004326 +#define CYDEV_PWRSYS_BASE 0x40004330 +#define CYDEV_PWRSYS_SIZE 0x00000002 +#define CYDEV_PWRSYS_CR0 0x40004330 +#define CYDEV_PWRSYS_CR1 0x40004331 +#define CYDEV_PM_BASE 0x40004380 +#define CYDEV_PM_SIZE 0x00000057 +#define CYDEV_PM_TW_CFG0 0x40004380 +#define CYDEV_PM_TW_CFG1 0x40004381 +#define CYDEV_PM_TW_CFG2 0x40004382 +#define CYDEV_PM_WDT_CFG 0x40004383 +#define CYDEV_PM_WDT_CR 0x40004384 +#define CYDEV_PM_INT_SR 0x40004390 +#define CYDEV_PM_MODE_CFG0 0x40004391 +#define CYDEV_PM_MODE_CFG1 0x40004392 +#define CYDEV_PM_MODE_CSR 0x40004393 +#define CYDEV_PM_USB_CR0 0x40004394 +#define CYDEV_PM_WAKEUP_CFG0 0x40004398 +#define CYDEV_PM_WAKEUP_CFG1 0x40004399 +#define CYDEV_PM_WAKEUP_CFG2 0x4000439a +#define CYDEV_PM_ACT_BASE 0x400043a0 +#define CYDEV_PM_ACT_SIZE 0x0000000e +#define CYDEV_PM_ACT_CFG0 0x400043a0 +#define CYDEV_PM_ACT_CFG1 0x400043a1 +#define CYDEV_PM_ACT_CFG2 0x400043a2 +#define CYDEV_PM_ACT_CFG3 0x400043a3 +#define CYDEV_PM_ACT_CFG4 0x400043a4 +#define CYDEV_PM_ACT_CFG5 0x400043a5 +#define CYDEV_PM_ACT_CFG6 0x400043a6 +#define CYDEV_PM_ACT_CFG7 0x400043a7 +#define CYDEV_PM_ACT_CFG8 0x400043a8 +#define CYDEV_PM_ACT_CFG9 0x400043a9 +#define CYDEV_PM_ACT_CFG10 0x400043aa +#define CYDEV_PM_ACT_CFG11 0x400043ab +#define CYDEV_PM_ACT_CFG12 0x400043ac +#define CYDEV_PM_ACT_CFG13 0x400043ad +#define CYDEV_PM_STBY_BASE 0x400043b0 +#define CYDEV_PM_STBY_SIZE 0x0000000e +#define CYDEV_PM_STBY_CFG0 0x400043b0 +#define CYDEV_PM_STBY_CFG1 0x400043b1 +#define CYDEV_PM_STBY_CFG2 0x400043b2 +#define CYDEV_PM_STBY_CFG3 0x400043b3 +#define CYDEV_PM_STBY_CFG4 0x400043b4 +#define CYDEV_PM_STBY_CFG5 0x400043b5 +#define CYDEV_PM_STBY_CFG6 0x400043b6 +#define CYDEV_PM_STBY_CFG7 0x400043b7 +#define CYDEV_PM_STBY_CFG8 0x400043b8 +#define CYDEV_PM_STBY_CFG9 0x400043b9 +#define CYDEV_PM_STBY_CFG10 0x400043ba +#define CYDEV_PM_STBY_CFG11 0x400043bb +#define CYDEV_PM_STBY_CFG12 0x400043bc +#define CYDEV_PM_STBY_CFG13 0x400043bd +#define CYDEV_PM_AVAIL_BASE 0x400043c0 +#define CYDEV_PM_AVAIL_SIZE 0x00000017 +#define CYDEV_PM_AVAIL_CR0 0x400043c0 +#define CYDEV_PM_AVAIL_CR1 0x400043c1 +#define CYDEV_PM_AVAIL_CR2 0x400043c2 +#define CYDEV_PM_AVAIL_CR3 0x400043c3 +#define CYDEV_PM_AVAIL_CR4 0x400043c4 +#define CYDEV_PM_AVAIL_CR5 0x400043c5 +#define CYDEV_PM_AVAIL_CR6 0x400043c6 +#define CYDEV_PM_AVAIL_SR0 0x400043d0 +#define CYDEV_PM_AVAIL_SR1 0x400043d1 +#define CYDEV_PM_AVAIL_SR2 0x400043d2 +#define CYDEV_PM_AVAIL_SR3 0x400043d3 +#define CYDEV_PM_AVAIL_SR4 0x400043d4 +#define CYDEV_PM_AVAIL_SR5 0x400043d5 +#define CYDEV_PM_AVAIL_SR6 0x400043d6 +#define CYDEV_PICU_BASE 0x40004500 +#define CYDEV_PICU_SIZE 0x000000b0 +#define CYDEV_PICU_INTTYPE_BASE 0x40004500 +#define CYDEV_PICU_INTTYPE_SIZE 0x00000080 +#define CYDEV_PICU_INTTYPE_PICU0_BASE 0x40004500 +#define CYDEV_PICU_INTTYPE_PICU0_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE0 0x40004500 +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE1 0x40004501 +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE2 0x40004502 +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE3 0x40004503 +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE4 0x40004504 +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE5 0x40004505 +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE6 0x40004506 +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE7 0x40004507 +#define CYDEV_PICU_INTTYPE_PICU1_BASE 0x40004508 +#define CYDEV_PICU_INTTYPE_PICU1_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE0 0x40004508 +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE1 0x40004509 +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE2 0x4000450a +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE3 0x4000450b +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE4 0x4000450c +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE5 0x4000450d +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE6 0x4000450e +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE7 0x4000450f +#define CYDEV_PICU_INTTYPE_PICU2_BASE 0x40004510 +#define CYDEV_PICU_INTTYPE_PICU2_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE0 0x40004510 +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE1 0x40004511 +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE2 0x40004512 +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE3 0x40004513 +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE4 0x40004514 +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE5 0x40004515 +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE6 0x40004516 +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE7 0x40004517 +#define CYDEV_PICU_INTTYPE_PICU3_BASE 0x40004518 +#define CYDEV_PICU_INTTYPE_PICU3_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE0 0x40004518 +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE1 0x40004519 +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE2 0x4000451a +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE3 0x4000451b +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE4 0x4000451c +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE5 0x4000451d +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE6 0x4000451e +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE7 0x4000451f +#define CYDEV_PICU_INTTYPE_PICU4_BASE 0x40004520 +#define CYDEV_PICU_INTTYPE_PICU4_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE0 0x40004520 +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE1 0x40004521 +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE2 0x40004522 +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE3 0x40004523 +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE4 0x40004524 +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE5 0x40004525 +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE6 0x40004526 +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE7 0x40004527 +#define CYDEV_PICU_INTTYPE_PICU5_BASE 0x40004528 +#define CYDEV_PICU_INTTYPE_PICU5_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE0 0x40004528 +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE1 0x40004529 +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE2 0x4000452a +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE3 0x4000452b +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE4 0x4000452c +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE5 0x4000452d +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE6 0x4000452e +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE7 0x4000452f +#define CYDEV_PICU_INTTYPE_PICU6_BASE 0x40004530 +#define CYDEV_PICU_INTTYPE_PICU6_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE0 0x40004530 +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE1 0x40004531 +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE2 0x40004532 +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE3 0x40004533 +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE4 0x40004534 +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE5 0x40004535 +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE6 0x40004536 +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE7 0x40004537 +#define CYDEV_PICU_INTTYPE_PICU12_BASE 0x40004560 +#define CYDEV_PICU_INTTYPE_PICU12_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE0 0x40004560 +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE1 0x40004561 +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE2 0x40004562 +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE3 0x40004563 +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE4 0x40004564 +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE5 0x40004565 +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE6 0x40004566 +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE7 0x40004567 +#define CYDEV_PICU_INTTYPE_PICU15_BASE 0x40004578 +#define CYDEV_PICU_INTTYPE_PICU15_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE0 0x40004578 +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE1 0x40004579 +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE2 0x4000457a +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE3 0x4000457b +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE4 0x4000457c +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE5 0x4000457d +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE6 0x4000457e +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE7 0x4000457f +#define CYDEV_PICU_STAT_BASE 0x40004580 +#define CYDEV_PICU_STAT_SIZE 0x00000010 +#define CYDEV_PICU_STAT_PICU0_BASE 0x40004580 +#define CYDEV_PICU_STAT_PICU0_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU0_INTSTAT 0x40004580 +#define CYDEV_PICU_STAT_PICU1_BASE 0x40004581 +#define CYDEV_PICU_STAT_PICU1_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU1_INTSTAT 0x40004581 +#define CYDEV_PICU_STAT_PICU2_BASE 0x40004582 +#define CYDEV_PICU_STAT_PICU2_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU2_INTSTAT 0x40004582 +#define CYDEV_PICU_STAT_PICU3_BASE 0x40004583 +#define CYDEV_PICU_STAT_PICU3_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU3_INTSTAT 0x40004583 +#define CYDEV_PICU_STAT_PICU4_BASE 0x40004584 +#define CYDEV_PICU_STAT_PICU4_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU4_INTSTAT 0x40004584 +#define CYDEV_PICU_STAT_PICU5_BASE 0x40004585 +#define CYDEV_PICU_STAT_PICU5_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU5_INTSTAT 0x40004585 +#define CYDEV_PICU_STAT_PICU6_BASE 0x40004586 +#define CYDEV_PICU_STAT_PICU6_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU6_INTSTAT 0x40004586 +#define CYDEV_PICU_STAT_PICU12_BASE 0x4000458c +#define CYDEV_PICU_STAT_PICU12_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU12_INTSTAT 0x4000458c +#define CYDEV_PICU_STAT_PICU15_BASE 0x4000458f +#define CYDEV_PICU_STAT_PICU15_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU15_INTSTAT 0x4000458f +#define CYDEV_PICU_SNAP_BASE 0x40004590 +#define CYDEV_PICU_SNAP_SIZE 0x00000010 +#define CYDEV_PICU_SNAP_PICU0_BASE 0x40004590 +#define CYDEV_PICU_SNAP_PICU0_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU0_SNAP 0x40004590 +#define CYDEV_PICU_SNAP_PICU1_BASE 0x40004591 +#define CYDEV_PICU_SNAP_PICU1_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU1_SNAP 0x40004591 +#define CYDEV_PICU_SNAP_PICU2_BASE 0x40004592 +#define CYDEV_PICU_SNAP_PICU2_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU2_SNAP 0x40004592 +#define CYDEV_PICU_SNAP_PICU3_BASE 0x40004593 +#define CYDEV_PICU_SNAP_PICU3_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU3_SNAP 0x40004593 +#define CYDEV_PICU_SNAP_PICU4_BASE 0x40004594 +#define CYDEV_PICU_SNAP_PICU4_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU4_SNAP 0x40004594 +#define CYDEV_PICU_SNAP_PICU5_BASE 0x40004595 +#define CYDEV_PICU_SNAP_PICU5_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU5_SNAP 0x40004595 +#define CYDEV_PICU_SNAP_PICU6_BASE 0x40004596 +#define CYDEV_PICU_SNAP_PICU6_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU6_SNAP 0x40004596 +#define CYDEV_PICU_SNAP_PICU12_BASE 0x4000459c +#define CYDEV_PICU_SNAP_PICU12_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU12_SNAP 0x4000459c +#define CYDEV_PICU_SNAP_PICU_15_BASE 0x4000459f +#define CYDEV_PICU_SNAP_PICU_15_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU_15_SNAP_15 0x4000459f +#define CYDEV_PICU_DISABLE_COR_BASE 0x400045a0 +#define CYDEV_PICU_DISABLE_COR_SIZE 0x00000010 +#define CYDEV_PICU_DISABLE_COR_PICU0_BASE 0x400045a0 +#define CYDEV_PICU_DISABLE_COR_PICU0_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR 0x400045a0 +#define CYDEV_PICU_DISABLE_COR_PICU1_BASE 0x400045a1 +#define CYDEV_PICU_DISABLE_COR_PICU1_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR 0x400045a1 +#define CYDEV_PICU_DISABLE_COR_PICU2_BASE 0x400045a2 +#define CYDEV_PICU_DISABLE_COR_PICU2_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR 0x400045a2 +#define CYDEV_PICU_DISABLE_COR_PICU3_BASE 0x400045a3 +#define CYDEV_PICU_DISABLE_COR_PICU3_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR 0x400045a3 +#define CYDEV_PICU_DISABLE_COR_PICU4_BASE 0x400045a4 +#define CYDEV_PICU_DISABLE_COR_PICU4_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR 0x400045a4 +#define CYDEV_PICU_DISABLE_COR_PICU5_BASE 0x400045a5 +#define CYDEV_PICU_DISABLE_COR_PICU5_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR 0x400045a5 +#define CYDEV_PICU_DISABLE_COR_PICU6_BASE 0x400045a6 +#define CYDEV_PICU_DISABLE_COR_PICU6_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR 0x400045a6 +#define CYDEV_PICU_DISABLE_COR_PICU12_BASE 0x400045ac +#define CYDEV_PICU_DISABLE_COR_PICU12_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR 0x400045ac +#define CYDEV_PICU_DISABLE_COR_PICU15_BASE 0x400045af +#define CYDEV_PICU_DISABLE_COR_PICU15_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR 0x400045af +#define CYDEV_MFGCFG_BASE 0x40004600 +#define CYDEV_MFGCFG_SIZE 0x000000ed +#define CYDEV_MFGCFG_ANAIF_BASE 0x40004600 +#define CYDEV_MFGCFG_ANAIF_SIZE 0x00000038 +#define CYDEV_MFGCFG_ANAIF_DAC0_BASE 0x40004608 +#define CYDEV_MFGCFG_ANAIF_DAC0_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_DAC0_TR 0x40004608 +#define CYDEV_MFGCFG_ANAIF_DAC1_BASE 0x40004609 +#define CYDEV_MFGCFG_ANAIF_DAC1_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_DAC1_TR 0x40004609 +#define CYDEV_MFGCFG_ANAIF_DAC2_BASE 0x4000460a +#define CYDEV_MFGCFG_ANAIF_DAC2_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_DAC2_TR 0x4000460a +#define CYDEV_MFGCFG_ANAIF_DAC3_BASE 0x4000460b +#define CYDEV_MFGCFG_ANAIF_DAC3_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_DAC3_TR 0x4000460b +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE 0x40004610 +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0 0x40004610 +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE 0x40004611 +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0 0x40004611 +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE 0x40004612 +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0 0x40004612 +#define CYDEV_MFGCFG_ANAIF_SAR0_BASE 0x40004614 +#define CYDEV_MFGCFG_ANAIF_SAR0_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_SAR0_TR0 0x40004614 +#define CYDEV_MFGCFG_ANAIF_SAR1_BASE 0x40004616 +#define CYDEV_MFGCFG_ANAIF_SAR1_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_SAR1_TR0 0x40004616 +#define CYDEV_MFGCFG_ANAIF_OPAMP0_BASE 0x40004620 +#define CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE 0x00000002 +#define CYDEV_MFGCFG_ANAIF_OPAMP0_TR0 0x40004620 +#define CYDEV_MFGCFG_ANAIF_OPAMP0_TR1 0x40004621 +#define CYDEV_MFGCFG_ANAIF_OPAMP1_BASE 0x40004622 +#define CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE 0x00000002 +#define CYDEV_MFGCFG_ANAIF_OPAMP1_TR0 0x40004622 +#define CYDEV_MFGCFG_ANAIF_OPAMP1_TR1 0x40004623 +#define CYDEV_MFGCFG_ANAIF_OPAMP2_BASE 0x40004624 +#define CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE 0x00000002 +#define CYDEV_MFGCFG_ANAIF_OPAMP2_TR0 0x40004624 +#define CYDEV_MFGCFG_ANAIF_OPAMP2_TR1 0x40004625 +#define CYDEV_MFGCFG_ANAIF_OPAMP3_BASE 0x40004626 +#define CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE 0x00000002 +#define CYDEV_MFGCFG_ANAIF_OPAMP3_TR0 0x40004626 +#define CYDEV_MFGCFG_ANAIF_OPAMP3_TR1 0x40004627 +#define CYDEV_MFGCFG_ANAIF_CMP0_BASE 0x40004630 +#define CYDEV_MFGCFG_ANAIF_CMP0_SIZE 0x00000002 +#define CYDEV_MFGCFG_ANAIF_CMP0_TR0 0x40004630 +#define CYDEV_MFGCFG_ANAIF_CMP0_TR1 0x40004631 +#define CYDEV_MFGCFG_ANAIF_CMP1_BASE 0x40004632 +#define CYDEV_MFGCFG_ANAIF_CMP1_SIZE 0x00000002 +#define CYDEV_MFGCFG_ANAIF_CMP1_TR0 0x40004632 +#define CYDEV_MFGCFG_ANAIF_CMP1_TR1 0x40004633 +#define CYDEV_MFGCFG_ANAIF_CMP2_BASE 0x40004634 +#define CYDEV_MFGCFG_ANAIF_CMP2_SIZE 0x00000002 +#define CYDEV_MFGCFG_ANAIF_CMP2_TR0 0x40004634 +#define CYDEV_MFGCFG_ANAIF_CMP2_TR1 0x40004635 +#define CYDEV_MFGCFG_ANAIF_CMP3_BASE 0x40004636 +#define CYDEV_MFGCFG_ANAIF_CMP3_SIZE 0x00000002 +#define CYDEV_MFGCFG_ANAIF_CMP3_TR0 0x40004636 +#define CYDEV_MFGCFG_ANAIF_CMP3_TR1 0x40004637 +#define CYDEV_MFGCFG_PWRSYS_BASE 0x40004680 +#define CYDEV_MFGCFG_PWRSYS_SIZE 0x0000000b +#define CYDEV_MFGCFG_PWRSYS_HIB_TR0 0x40004680 +#define CYDEV_MFGCFG_PWRSYS_HIB_TR1 0x40004681 +#define CYDEV_MFGCFG_PWRSYS_I2C_TR 0x40004682 +#define CYDEV_MFGCFG_PWRSYS_SLP_TR 0x40004683 +#define CYDEV_MFGCFG_PWRSYS_BUZZ_TR 0x40004684 +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR0 0x40004685 +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR1 0x40004686 +#define CYDEV_MFGCFG_PWRSYS_BREF_TR 0x40004687 +#define CYDEV_MFGCFG_PWRSYS_BG_TR 0x40004688 +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR2 0x40004689 +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR3 0x4000468a +#define CYDEV_MFGCFG_ILO_BASE 0x40004690 +#define CYDEV_MFGCFG_ILO_SIZE 0x00000002 +#define CYDEV_MFGCFG_ILO_TR0 0x40004690 +#define CYDEV_MFGCFG_ILO_TR1 0x40004691 +#define CYDEV_MFGCFG_X32_BASE 0x40004698 +#define CYDEV_MFGCFG_X32_SIZE 0x00000001 +#define CYDEV_MFGCFG_X32_TR 0x40004698 +#define CYDEV_MFGCFG_IMO_BASE 0x400046a0 +#define CYDEV_MFGCFG_IMO_SIZE 0x00000005 +#define CYDEV_MFGCFG_IMO_TR0 0x400046a0 +#define CYDEV_MFGCFG_IMO_TR1 0x400046a1 +#define CYDEV_MFGCFG_IMO_GAIN 0x400046a2 +#define CYDEV_MFGCFG_IMO_C36M 0x400046a3 +#define CYDEV_MFGCFG_IMO_TR2 0x400046a4 +#define CYDEV_MFGCFG_XMHZ_BASE 0x400046a8 +#define CYDEV_MFGCFG_XMHZ_SIZE 0x00000001 +#define CYDEV_MFGCFG_XMHZ_TR 0x400046a8 +#define CYDEV_MFGCFG_DLY 0x400046c0 +#define CYDEV_MFGCFG_MLOGIC_BASE 0x400046e0 +#define CYDEV_MFGCFG_MLOGIC_SIZE 0x0000000d +#define CYDEV_MFGCFG_MLOGIC_DMPSTR 0x400046e2 +#define CYDEV_MFGCFG_MLOGIC_SEG_BASE 0x400046e4 +#define CYDEV_MFGCFG_MLOGIC_SEG_SIZE 0x00000002 +#define CYDEV_MFGCFG_MLOGIC_SEG_CR 0x400046e4 +#define CYDEV_MFGCFG_MLOGIC_SEG_CFG0 0x400046e5 +#define CYDEV_MFGCFG_MLOGIC_DEBUG 0x400046e8 +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE 0x400046ea +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE 0x00000001 +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR 0x400046ea +#define CYDEV_MFGCFG_MLOGIC_REV_ID 0x400046ec +#define CYDEV_RESET_BASE 0x400046f0 +#define CYDEV_RESET_SIZE 0x0000000f +#define CYDEV_RESET_IPOR_CR0 0x400046f0 +#define CYDEV_RESET_IPOR_CR1 0x400046f1 +#define CYDEV_RESET_IPOR_CR2 0x400046f2 +#define CYDEV_RESET_IPOR_CR3 0x400046f3 +#define CYDEV_RESET_CR0 0x400046f4 +#define CYDEV_RESET_CR1 0x400046f5 +#define CYDEV_RESET_CR2 0x400046f6 +#define CYDEV_RESET_CR3 0x400046f7 +#define CYDEV_RESET_CR4 0x400046f8 +#define CYDEV_RESET_CR5 0x400046f9 +#define CYDEV_RESET_SR0 0x400046fa +#define CYDEV_RESET_SR1 0x400046fb +#define CYDEV_RESET_SR2 0x400046fc +#define CYDEV_RESET_SR3 0x400046fd +#define CYDEV_RESET_TR 0x400046fe +#define CYDEV_SPC_BASE 0x40004700 +#define CYDEV_SPC_SIZE 0x00000100 +#define CYDEV_SPC_FM_EE_CR 0x40004700 +#define CYDEV_SPC_FM_EE_WAKE_CNT 0x40004701 +#define CYDEV_SPC_EE_SCR 0x40004702 +#define CYDEV_SPC_EE_ERR 0x40004703 +#define CYDEV_SPC_CPU_DATA 0x40004720 +#define CYDEV_SPC_DMA_DATA 0x40004721 +#define CYDEV_SPC_SR 0x40004722 +#define CYDEV_SPC_CR 0x40004723 +#define CYDEV_SPC_DMM_MAP_BASE 0x40004780 +#define CYDEV_SPC_DMM_MAP_SIZE 0x00000080 +#define CYDEV_SPC_DMM_MAP_SRAM_MBASE 0x40004780 +#define CYDEV_SPC_DMM_MAP_SRAM_MSIZE 0x00000080 +#define CYDEV_CACHE_BASE 0x40004800 +#define CYDEV_CACHE_SIZE 0x0000009c +#define CYDEV_CACHE_CC_CTL 0x40004800 +#define CYDEV_CACHE_ECC_CORR 0x40004880 +#define CYDEV_CACHE_ECC_ERR 0x40004888 +#define CYDEV_CACHE_FLASH_ERR 0x40004890 +#define CYDEV_CACHE_HITMISS 0x40004898 +#define CYDEV_I2C_BASE 0x40004900 +#define CYDEV_I2C_SIZE 0x000000e1 +#define CYDEV_I2C_XCFG 0x400049c8 +#define CYDEV_I2C_ADR 0x400049ca +#define CYDEV_I2C_CFG 0x400049d6 +#define CYDEV_I2C_CSR 0x400049d7 +#define CYDEV_I2C_D 0x400049d8 +#define CYDEV_I2C_MCSR 0x400049d9 +#define CYDEV_I2C_CLK_DIV1 0x400049db +#define CYDEV_I2C_CLK_DIV2 0x400049dc +#define CYDEV_I2C_TMOUT_CSR 0x400049dd +#define CYDEV_I2C_TMOUT_SR 0x400049de +#define CYDEV_I2C_TMOUT_CFG0 0x400049df +#define CYDEV_I2C_TMOUT_CFG1 0x400049e0 +#define CYDEV_DEC_BASE 0x40004e00 +#define CYDEV_DEC_SIZE 0x00000015 +#define CYDEV_DEC_CR 0x40004e00 +#define CYDEV_DEC_SR 0x40004e01 +#define CYDEV_DEC_SHIFT1 0x40004e02 +#define CYDEV_DEC_SHIFT2 0x40004e03 +#define CYDEV_DEC_DR2 0x40004e04 +#define CYDEV_DEC_DR2H 0x40004e05 +#define CYDEV_DEC_DR1 0x40004e06 +#define CYDEV_DEC_OCOR 0x40004e08 +#define CYDEV_DEC_OCORM 0x40004e09 +#define CYDEV_DEC_OCORH 0x40004e0a +#define CYDEV_DEC_GCOR 0x40004e0c +#define CYDEV_DEC_GCORH 0x40004e0d +#define CYDEV_DEC_GVAL 0x40004e0e +#define CYDEV_DEC_OUTSAMP 0x40004e10 +#define CYDEV_DEC_OUTSAMPM 0x40004e11 +#define CYDEV_DEC_OUTSAMPH 0x40004e12 +#define CYDEV_DEC_OUTSAMPS 0x40004e13 +#define CYDEV_DEC_COHER 0x40004e14 +#define CYDEV_TMR0_BASE 0x40004f00 +#define CYDEV_TMR0_SIZE 0x0000000c +#define CYDEV_TMR0_CFG0 0x40004f00 +#define CYDEV_TMR0_CFG1 0x40004f01 +#define CYDEV_TMR0_CFG2 0x40004f02 +#define CYDEV_TMR0_SR0 0x40004f03 +#define CYDEV_TMR0_PER0 0x40004f04 +#define CYDEV_TMR0_PER1 0x40004f05 +#define CYDEV_TMR0_CNT_CMP0 0x40004f06 +#define CYDEV_TMR0_CNT_CMP1 0x40004f07 +#define CYDEV_TMR0_CAP0 0x40004f08 +#define CYDEV_TMR0_CAP1 0x40004f09 +#define CYDEV_TMR0_RT0 0x40004f0a +#define CYDEV_TMR0_RT1 0x40004f0b +#define CYDEV_TMR1_BASE 0x40004f0c +#define CYDEV_TMR1_SIZE 0x0000000c +#define CYDEV_TMR1_CFG0 0x40004f0c +#define CYDEV_TMR1_CFG1 0x40004f0d +#define CYDEV_TMR1_CFG2 0x40004f0e +#define CYDEV_TMR1_SR0 0x40004f0f +#define CYDEV_TMR1_PER0 0x40004f10 +#define CYDEV_TMR1_PER1 0x40004f11 +#define CYDEV_TMR1_CNT_CMP0 0x40004f12 +#define CYDEV_TMR1_CNT_CMP1 0x40004f13 +#define CYDEV_TMR1_CAP0 0x40004f14 +#define CYDEV_TMR1_CAP1 0x40004f15 +#define CYDEV_TMR1_RT0 0x40004f16 +#define CYDEV_TMR1_RT1 0x40004f17 +#define CYDEV_TMR2_BASE 0x40004f18 +#define CYDEV_TMR2_SIZE 0x0000000c +#define CYDEV_TMR2_CFG0 0x40004f18 +#define CYDEV_TMR2_CFG1 0x40004f19 +#define CYDEV_TMR2_CFG2 0x40004f1a +#define CYDEV_TMR2_SR0 0x40004f1b +#define CYDEV_TMR2_PER0 0x40004f1c +#define CYDEV_TMR2_PER1 0x40004f1d +#define CYDEV_TMR2_CNT_CMP0 0x40004f1e +#define CYDEV_TMR2_CNT_CMP1 0x40004f1f +#define CYDEV_TMR2_CAP0 0x40004f20 +#define CYDEV_TMR2_CAP1 0x40004f21 +#define CYDEV_TMR2_RT0 0x40004f22 +#define CYDEV_TMR2_RT1 0x40004f23 +#define CYDEV_TMR3_BASE 0x40004f24 +#define CYDEV_TMR3_SIZE 0x0000000c +#define CYDEV_TMR3_CFG0 0x40004f24 +#define CYDEV_TMR3_CFG1 0x40004f25 +#define CYDEV_TMR3_CFG2 0x40004f26 +#define CYDEV_TMR3_SR0 0x40004f27 +#define CYDEV_TMR3_PER0 0x40004f28 +#define CYDEV_TMR3_PER1 0x40004f29 +#define CYDEV_TMR3_CNT_CMP0 0x40004f2a +#define CYDEV_TMR3_CNT_CMP1 0x40004f2b +#define CYDEV_TMR3_CAP0 0x40004f2c +#define CYDEV_TMR3_CAP1 0x40004f2d +#define CYDEV_TMR3_RT0 0x40004f2e +#define CYDEV_TMR3_RT1 0x40004f2f +#define CYDEV_IO_BASE 0x40005000 +#define CYDEV_IO_SIZE 0x00000200 +#define CYDEV_IO_PC_BASE 0x40005000 +#define CYDEV_IO_PC_SIZE 0x00000080 +#define CYDEV_IO_PC_PRT0_BASE 0x40005000 +#define CYDEV_IO_PC_PRT0_SIZE 0x00000008 +#define CYDEV_IO_PC_PRT0_PC0 0x40005000 +#define CYDEV_IO_PC_PRT0_PC1 0x40005001 +#define CYDEV_IO_PC_PRT0_PC2 0x40005002 +#define CYDEV_IO_PC_PRT0_PC3 0x40005003 +#define CYDEV_IO_PC_PRT0_PC4 0x40005004 +#define CYDEV_IO_PC_PRT0_PC5 0x40005005 +#define CYDEV_IO_PC_PRT0_PC6 0x40005006 +#define CYDEV_IO_PC_PRT0_PC7 0x40005007 +#define CYDEV_IO_PC_PRT1_BASE 0x40005008 +#define CYDEV_IO_PC_PRT1_SIZE 0x00000008 +#define CYDEV_IO_PC_PRT1_PC0 0x40005008 +#define CYDEV_IO_PC_PRT1_PC1 0x40005009 +#define CYDEV_IO_PC_PRT1_PC2 0x4000500a +#define CYDEV_IO_PC_PRT1_PC3 0x4000500b +#define CYDEV_IO_PC_PRT1_PC4 0x4000500c +#define CYDEV_IO_PC_PRT1_PC5 0x4000500d +#define CYDEV_IO_PC_PRT1_PC6 0x4000500e +#define CYDEV_IO_PC_PRT1_PC7 0x4000500f +#define CYDEV_IO_PC_PRT2_BASE 0x40005010 +#define CYDEV_IO_PC_PRT2_SIZE 0x00000008 +#define CYDEV_IO_PC_PRT2_PC0 0x40005010 +#define CYDEV_IO_PC_PRT2_PC1 0x40005011 +#define CYDEV_IO_PC_PRT2_PC2 0x40005012 +#define CYDEV_IO_PC_PRT2_PC3 0x40005013 +#define CYDEV_IO_PC_PRT2_PC4 0x40005014 +#define CYDEV_IO_PC_PRT2_PC5 0x40005015 +#define CYDEV_IO_PC_PRT2_PC6 0x40005016 +#define CYDEV_IO_PC_PRT2_PC7 0x40005017 +#define CYDEV_IO_PC_PRT3_BASE 0x40005018 +#define CYDEV_IO_PC_PRT3_SIZE 0x00000008 +#define CYDEV_IO_PC_PRT3_PC0 0x40005018 +#define CYDEV_IO_PC_PRT3_PC1 0x40005019 +#define CYDEV_IO_PC_PRT3_PC2 0x4000501a +#define CYDEV_IO_PC_PRT3_PC3 0x4000501b +#define CYDEV_IO_PC_PRT3_PC4 0x4000501c +#define CYDEV_IO_PC_PRT3_PC5 0x4000501d +#define CYDEV_IO_PC_PRT3_PC6 0x4000501e +#define CYDEV_IO_PC_PRT3_PC7 0x4000501f +#define CYDEV_IO_PC_PRT4_BASE 0x40005020 +#define CYDEV_IO_PC_PRT4_SIZE 0x00000008 +#define CYDEV_IO_PC_PRT4_PC0 0x40005020 +#define CYDEV_IO_PC_PRT4_PC1 0x40005021 +#define CYDEV_IO_PC_PRT4_PC2 0x40005022 +#define CYDEV_IO_PC_PRT4_PC3 0x40005023 +#define CYDEV_IO_PC_PRT4_PC4 0x40005024 +#define CYDEV_IO_PC_PRT4_PC5 0x40005025 +#define CYDEV_IO_PC_PRT4_PC6 0x40005026 +#define CYDEV_IO_PC_PRT4_PC7 0x40005027 +#define CYDEV_IO_PC_PRT5_BASE 0x40005028 +#define CYDEV_IO_PC_PRT5_SIZE 0x00000008 +#define CYDEV_IO_PC_PRT5_PC0 0x40005028 +#define CYDEV_IO_PC_PRT5_PC1 0x40005029 +#define CYDEV_IO_PC_PRT5_PC2 0x4000502a +#define CYDEV_IO_PC_PRT5_PC3 0x4000502b +#define CYDEV_IO_PC_PRT5_PC4 0x4000502c +#define CYDEV_IO_PC_PRT5_PC5 0x4000502d +#define CYDEV_IO_PC_PRT5_PC6 0x4000502e +#define CYDEV_IO_PC_PRT5_PC7 0x4000502f +#define CYDEV_IO_PC_PRT6_BASE 0x40005030 +#define CYDEV_IO_PC_PRT6_SIZE 0x00000008 +#define CYDEV_IO_PC_PRT6_PC0 0x40005030 +#define CYDEV_IO_PC_PRT6_PC1 0x40005031 +#define CYDEV_IO_PC_PRT6_PC2 0x40005032 +#define CYDEV_IO_PC_PRT6_PC3 0x40005033 +#define CYDEV_IO_PC_PRT6_PC4 0x40005034 +#define CYDEV_IO_PC_PRT6_PC5 0x40005035 +#define CYDEV_IO_PC_PRT6_PC6 0x40005036 +#define CYDEV_IO_PC_PRT6_PC7 0x40005037 +#define CYDEV_IO_PC_PRT12_BASE 0x40005060 +#define CYDEV_IO_PC_PRT12_SIZE 0x00000008 +#define CYDEV_IO_PC_PRT12_PC0 0x40005060 +#define CYDEV_IO_PC_PRT12_PC1 0x40005061 +#define CYDEV_IO_PC_PRT12_PC2 0x40005062 +#define CYDEV_IO_PC_PRT12_PC3 0x40005063 +#define CYDEV_IO_PC_PRT12_PC4 0x40005064 +#define CYDEV_IO_PC_PRT12_PC5 0x40005065 +#define CYDEV_IO_PC_PRT12_PC6 0x40005066 +#define CYDEV_IO_PC_PRT12_PC7 0x40005067 +#define CYDEV_IO_PC_PRT15_BASE 0x40005078 +#define CYDEV_IO_PC_PRT15_SIZE 0x00000006 +#define CYDEV_IO_PC_PRT15_PC0 0x40005078 +#define CYDEV_IO_PC_PRT15_PC1 0x40005079 +#define CYDEV_IO_PC_PRT15_PC2 0x4000507a +#define CYDEV_IO_PC_PRT15_PC3 0x4000507b +#define CYDEV_IO_PC_PRT15_PC4 0x4000507c +#define CYDEV_IO_PC_PRT15_PC5 0x4000507d +#define CYDEV_IO_PC_PRT15_7_6_BASE 0x4000507e +#define CYDEV_IO_PC_PRT15_7_6_SIZE 0x00000002 +#define CYDEV_IO_PC_PRT15_7_6_PC0 0x4000507e +#define CYDEV_IO_PC_PRT15_7_6_PC1 0x4000507f +#define CYDEV_IO_DR_BASE 0x40005080 +#define CYDEV_IO_DR_SIZE 0x00000010 +#define CYDEV_IO_DR_PRT0_BASE 0x40005080 +#define CYDEV_IO_DR_PRT0_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT0_DR_ALIAS 0x40005080 +#define CYDEV_IO_DR_PRT1_BASE 0x40005081 +#define CYDEV_IO_DR_PRT1_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT1_DR_ALIAS 0x40005081 +#define CYDEV_IO_DR_PRT2_BASE 0x40005082 +#define CYDEV_IO_DR_PRT2_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT2_DR_ALIAS 0x40005082 +#define CYDEV_IO_DR_PRT3_BASE 0x40005083 +#define CYDEV_IO_DR_PRT3_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT3_DR_ALIAS 0x40005083 +#define CYDEV_IO_DR_PRT4_BASE 0x40005084 +#define CYDEV_IO_DR_PRT4_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT4_DR_ALIAS 0x40005084 +#define CYDEV_IO_DR_PRT5_BASE 0x40005085 +#define CYDEV_IO_DR_PRT5_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT5_DR_ALIAS 0x40005085 +#define CYDEV_IO_DR_PRT6_BASE 0x40005086 +#define CYDEV_IO_DR_PRT6_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT6_DR_ALIAS 0x40005086 +#define CYDEV_IO_DR_PRT12_BASE 0x4000508c +#define CYDEV_IO_DR_PRT12_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT12_DR_ALIAS 0x4000508c +#define CYDEV_IO_DR_PRT15_BASE 0x4000508f +#define CYDEV_IO_DR_PRT15_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT15_DR_15_ALIAS 0x4000508f +#define CYDEV_IO_PS_BASE 0x40005090 +#define CYDEV_IO_PS_SIZE 0x00000010 +#define CYDEV_IO_PS_PRT0_BASE 0x40005090 +#define CYDEV_IO_PS_PRT0_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT0_PS_ALIAS 0x40005090 +#define CYDEV_IO_PS_PRT1_BASE 0x40005091 +#define CYDEV_IO_PS_PRT1_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT1_PS_ALIAS 0x40005091 +#define CYDEV_IO_PS_PRT2_BASE 0x40005092 +#define CYDEV_IO_PS_PRT2_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT2_PS_ALIAS 0x40005092 +#define CYDEV_IO_PS_PRT3_BASE 0x40005093 +#define CYDEV_IO_PS_PRT3_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT3_PS_ALIAS 0x40005093 +#define CYDEV_IO_PS_PRT4_BASE 0x40005094 +#define CYDEV_IO_PS_PRT4_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT4_PS_ALIAS 0x40005094 +#define CYDEV_IO_PS_PRT5_BASE 0x40005095 +#define CYDEV_IO_PS_PRT5_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT5_PS_ALIAS 0x40005095 +#define CYDEV_IO_PS_PRT6_BASE 0x40005096 +#define CYDEV_IO_PS_PRT6_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT6_PS_ALIAS 0x40005096 +#define CYDEV_IO_PS_PRT12_BASE 0x4000509c +#define CYDEV_IO_PS_PRT12_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT12_PS_ALIAS 0x4000509c +#define CYDEV_IO_PS_PRT15_BASE 0x4000509f +#define CYDEV_IO_PS_PRT15_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT15_PS15_ALIAS 0x4000509f +#define CYDEV_IO_PRT_BASE 0x40005100 +#define CYDEV_IO_PRT_SIZE 0x00000100 +#define CYDEV_IO_PRT_PRT0_BASE 0x40005100 +#define CYDEV_IO_PRT_PRT0_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT0_DR 0x40005100 +#define CYDEV_IO_PRT_PRT0_PS 0x40005101 +#define CYDEV_IO_PRT_PRT0_DM0 0x40005102 +#define CYDEV_IO_PRT_PRT0_DM1 0x40005103 +#define CYDEV_IO_PRT_PRT0_DM2 0x40005104 +#define CYDEV_IO_PRT_PRT0_SLW 0x40005105 +#define CYDEV_IO_PRT_PRT0_BYP 0x40005106 +#define CYDEV_IO_PRT_PRT0_BIE 0x40005107 +#define CYDEV_IO_PRT_PRT0_INP_DIS 0x40005108 +#define CYDEV_IO_PRT_PRT0_CTL 0x40005109 +#define CYDEV_IO_PRT_PRT0_PRT 0x4000510a +#define CYDEV_IO_PRT_PRT0_BIT_MASK 0x4000510b +#define CYDEV_IO_PRT_PRT0_AMUX 0x4000510c +#define CYDEV_IO_PRT_PRT0_AG 0x4000510d +#define CYDEV_IO_PRT_PRT0_LCD_COM_SEG 0x4000510e +#define CYDEV_IO_PRT_PRT0_LCD_EN 0x4000510f +#define CYDEV_IO_PRT_PRT1_BASE 0x40005110 +#define CYDEV_IO_PRT_PRT1_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT1_DR 0x40005110 +#define CYDEV_IO_PRT_PRT1_PS 0x40005111 +#define CYDEV_IO_PRT_PRT1_DM0 0x40005112 +#define CYDEV_IO_PRT_PRT1_DM1 0x40005113 +#define CYDEV_IO_PRT_PRT1_DM2 0x40005114 +#define CYDEV_IO_PRT_PRT1_SLW 0x40005115 +#define CYDEV_IO_PRT_PRT1_BYP 0x40005116 +#define CYDEV_IO_PRT_PRT1_BIE 0x40005117 +#define CYDEV_IO_PRT_PRT1_INP_DIS 0x40005118 +#define CYDEV_IO_PRT_PRT1_CTL 0x40005119 +#define CYDEV_IO_PRT_PRT1_PRT 0x4000511a +#define CYDEV_IO_PRT_PRT1_BIT_MASK 0x4000511b +#define CYDEV_IO_PRT_PRT1_AMUX 0x4000511c +#define CYDEV_IO_PRT_PRT1_AG 0x4000511d +#define CYDEV_IO_PRT_PRT1_LCD_COM_SEG 0x4000511e +#define CYDEV_IO_PRT_PRT1_LCD_EN 0x4000511f +#define CYDEV_IO_PRT_PRT2_BASE 0x40005120 +#define CYDEV_IO_PRT_PRT2_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT2_DR 0x40005120 +#define CYDEV_IO_PRT_PRT2_PS 0x40005121 +#define CYDEV_IO_PRT_PRT2_DM0 0x40005122 +#define CYDEV_IO_PRT_PRT2_DM1 0x40005123 +#define CYDEV_IO_PRT_PRT2_DM2 0x40005124 +#define CYDEV_IO_PRT_PRT2_SLW 0x40005125 +#define CYDEV_IO_PRT_PRT2_BYP 0x40005126 +#define CYDEV_IO_PRT_PRT2_BIE 0x40005127 +#define CYDEV_IO_PRT_PRT2_INP_DIS 0x40005128 +#define CYDEV_IO_PRT_PRT2_CTL 0x40005129 +#define CYDEV_IO_PRT_PRT2_PRT 0x4000512a +#define CYDEV_IO_PRT_PRT2_BIT_MASK 0x4000512b +#define CYDEV_IO_PRT_PRT2_AMUX 0x4000512c +#define CYDEV_IO_PRT_PRT2_AG 0x4000512d +#define CYDEV_IO_PRT_PRT2_LCD_COM_SEG 0x4000512e +#define CYDEV_IO_PRT_PRT2_LCD_EN 0x4000512f +#define CYDEV_IO_PRT_PRT3_BASE 0x40005130 +#define CYDEV_IO_PRT_PRT3_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT3_DR 0x40005130 +#define CYDEV_IO_PRT_PRT3_PS 0x40005131 +#define CYDEV_IO_PRT_PRT3_DM0 0x40005132 +#define CYDEV_IO_PRT_PRT3_DM1 0x40005133 +#define CYDEV_IO_PRT_PRT3_DM2 0x40005134 +#define CYDEV_IO_PRT_PRT3_SLW 0x40005135 +#define CYDEV_IO_PRT_PRT3_BYP 0x40005136 +#define CYDEV_IO_PRT_PRT3_BIE 0x40005137 +#define CYDEV_IO_PRT_PRT3_INP_DIS 0x40005138 +#define CYDEV_IO_PRT_PRT3_CTL 0x40005139 +#define CYDEV_IO_PRT_PRT3_PRT 0x4000513a +#define CYDEV_IO_PRT_PRT3_BIT_MASK 0x4000513b +#define CYDEV_IO_PRT_PRT3_AMUX 0x4000513c +#define CYDEV_IO_PRT_PRT3_AG 0x4000513d +#define CYDEV_IO_PRT_PRT3_LCD_COM_SEG 0x4000513e +#define CYDEV_IO_PRT_PRT3_LCD_EN 0x4000513f +#define CYDEV_IO_PRT_PRT4_BASE 0x40005140 +#define CYDEV_IO_PRT_PRT4_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT4_DR 0x40005140 +#define CYDEV_IO_PRT_PRT4_PS 0x40005141 +#define CYDEV_IO_PRT_PRT4_DM0 0x40005142 +#define CYDEV_IO_PRT_PRT4_DM1 0x40005143 +#define CYDEV_IO_PRT_PRT4_DM2 0x40005144 +#define CYDEV_IO_PRT_PRT4_SLW 0x40005145 +#define CYDEV_IO_PRT_PRT4_BYP 0x40005146 +#define CYDEV_IO_PRT_PRT4_BIE 0x40005147 +#define CYDEV_IO_PRT_PRT4_INP_DIS 0x40005148 +#define CYDEV_IO_PRT_PRT4_CTL 0x40005149 +#define CYDEV_IO_PRT_PRT4_PRT 0x4000514a +#define CYDEV_IO_PRT_PRT4_BIT_MASK 0x4000514b +#define CYDEV_IO_PRT_PRT4_AMUX 0x4000514c +#define CYDEV_IO_PRT_PRT4_AG 0x4000514d +#define CYDEV_IO_PRT_PRT4_LCD_COM_SEG 0x4000514e +#define CYDEV_IO_PRT_PRT4_LCD_EN 0x4000514f +#define CYDEV_IO_PRT_PRT5_BASE 0x40005150 +#define CYDEV_IO_PRT_PRT5_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT5_DR 0x40005150 +#define CYDEV_IO_PRT_PRT5_PS 0x40005151 +#define CYDEV_IO_PRT_PRT5_DM0 0x40005152 +#define CYDEV_IO_PRT_PRT5_DM1 0x40005153 +#define CYDEV_IO_PRT_PRT5_DM2 0x40005154 +#define CYDEV_IO_PRT_PRT5_SLW 0x40005155 +#define CYDEV_IO_PRT_PRT5_BYP 0x40005156 +#define CYDEV_IO_PRT_PRT5_BIE 0x40005157 +#define CYDEV_IO_PRT_PRT5_INP_DIS 0x40005158 +#define CYDEV_IO_PRT_PRT5_CTL 0x40005159 +#define CYDEV_IO_PRT_PRT5_PRT 0x4000515a +#define CYDEV_IO_PRT_PRT5_BIT_MASK 0x4000515b +#define CYDEV_IO_PRT_PRT5_AMUX 0x4000515c +#define CYDEV_IO_PRT_PRT5_AG 0x4000515d +#define CYDEV_IO_PRT_PRT5_LCD_COM_SEG 0x4000515e +#define CYDEV_IO_PRT_PRT5_LCD_EN 0x4000515f +#define CYDEV_IO_PRT_PRT6_BASE 0x40005160 +#define CYDEV_IO_PRT_PRT6_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT6_DR 0x40005160 +#define CYDEV_IO_PRT_PRT6_PS 0x40005161 +#define CYDEV_IO_PRT_PRT6_DM0 0x40005162 +#define CYDEV_IO_PRT_PRT6_DM1 0x40005163 +#define CYDEV_IO_PRT_PRT6_DM2 0x40005164 +#define CYDEV_IO_PRT_PRT6_SLW 0x40005165 +#define CYDEV_IO_PRT_PRT6_BYP 0x40005166 +#define CYDEV_IO_PRT_PRT6_BIE 0x40005167 +#define CYDEV_IO_PRT_PRT6_INP_DIS 0x40005168 +#define CYDEV_IO_PRT_PRT6_CTL 0x40005169 +#define CYDEV_IO_PRT_PRT6_PRT 0x4000516a +#define CYDEV_IO_PRT_PRT6_BIT_MASK 0x4000516b +#define CYDEV_IO_PRT_PRT6_AMUX 0x4000516c +#define CYDEV_IO_PRT_PRT6_AG 0x4000516d +#define CYDEV_IO_PRT_PRT6_LCD_COM_SEG 0x4000516e +#define CYDEV_IO_PRT_PRT6_LCD_EN 0x4000516f +#define CYDEV_IO_PRT_PRT12_BASE 0x400051c0 +#define CYDEV_IO_PRT_PRT12_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT12_DR 0x400051c0 +#define CYDEV_IO_PRT_PRT12_PS 0x400051c1 +#define CYDEV_IO_PRT_PRT12_DM0 0x400051c2 +#define CYDEV_IO_PRT_PRT12_DM1 0x400051c3 +#define CYDEV_IO_PRT_PRT12_DM2 0x400051c4 +#define CYDEV_IO_PRT_PRT12_SLW 0x400051c5 +#define CYDEV_IO_PRT_PRT12_BYP 0x400051c6 +#define CYDEV_IO_PRT_PRT12_BIE 0x400051c7 +#define CYDEV_IO_PRT_PRT12_INP_DIS 0x400051c8 +#define CYDEV_IO_PRT_PRT12_SIO_HYST_EN 0x400051c9 +#define CYDEV_IO_PRT_PRT12_PRT 0x400051ca +#define CYDEV_IO_PRT_PRT12_BIT_MASK 0x400051cb +#define CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ 0x400051cc +#define CYDEV_IO_PRT_PRT12_AG 0x400051cd +#define CYDEV_IO_PRT_PRT12_SIO_CFG 0x400051ce +#define CYDEV_IO_PRT_PRT12_SIO_DIFF 0x400051cf +#define CYDEV_IO_PRT_PRT15_BASE 0x400051f0 +#define CYDEV_IO_PRT_PRT15_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT15_DR 0x400051f0 +#define CYDEV_IO_PRT_PRT15_PS 0x400051f1 +#define CYDEV_IO_PRT_PRT15_DM0 0x400051f2 +#define CYDEV_IO_PRT_PRT15_DM1 0x400051f3 +#define CYDEV_IO_PRT_PRT15_DM2 0x400051f4 +#define CYDEV_IO_PRT_PRT15_SLW 0x400051f5 +#define CYDEV_IO_PRT_PRT15_BYP 0x400051f6 +#define CYDEV_IO_PRT_PRT15_BIE 0x400051f7 +#define CYDEV_IO_PRT_PRT15_INP_DIS 0x400051f8 +#define CYDEV_IO_PRT_PRT15_CTL 0x400051f9 +#define CYDEV_IO_PRT_PRT15_PRT 0x400051fa +#define CYDEV_IO_PRT_PRT15_BIT_MASK 0x400051fb +#define CYDEV_IO_PRT_PRT15_AMUX 0x400051fc +#define CYDEV_IO_PRT_PRT15_AG 0x400051fd +#define CYDEV_IO_PRT_PRT15_LCD_COM_SEG 0x400051fe +#define CYDEV_IO_PRT_PRT15_LCD_EN 0x400051ff +#define CYDEV_PRTDSI_BASE 0x40005200 +#define CYDEV_PRTDSI_SIZE 0x0000007f +#define CYDEV_PRTDSI_PRT0_BASE 0x40005200 +#define CYDEV_PRTDSI_PRT0_SIZE 0x00000007 +#define CYDEV_PRTDSI_PRT0_OUT_SEL0 0x40005200 +#define CYDEV_PRTDSI_PRT0_OUT_SEL1 0x40005201 +#define CYDEV_PRTDSI_PRT0_OE_SEL0 0x40005202 +#define CYDEV_PRTDSI_PRT0_OE_SEL1 0x40005203 +#define CYDEV_PRTDSI_PRT0_DBL_SYNC_IN 0x40005204 +#define CYDEV_PRTDSI_PRT0_SYNC_OUT 0x40005205 +#define CYDEV_PRTDSI_PRT0_CAPS_SEL 0x40005206 +#define CYDEV_PRTDSI_PRT1_BASE 0x40005208 +#define CYDEV_PRTDSI_PRT1_SIZE 0x00000007 +#define CYDEV_PRTDSI_PRT1_OUT_SEL0 0x40005208 +#define CYDEV_PRTDSI_PRT1_OUT_SEL1 0x40005209 +#define CYDEV_PRTDSI_PRT1_OE_SEL0 0x4000520a +#define CYDEV_PRTDSI_PRT1_OE_SEL1 0x4000520b +#define CYDEV_PRTDSI_PRT1_DBL_SYNC_IN 0x4000520c +#define CYDEV_PRTDSI_PRT1_SYNC_OUT 0x4000520d +#define CYDEV_PRTDSI_PRT1_CAPS_SEL 0x4000520e +#define CYDEV_PRTDSI_PRT2_BASE 0x40005210 +#define CYDEV_PRTDSI_PRT2_SIZE 0x00000007 +#define CYDEV_PRTDSI_PRT2_OUT_SEL0 0x40005210 +#define CYDEV_PRTDSI_PRT2_OUT_SEL1 0x40005211 +#define CYDEV_PRTDSI_PRT2_OE_SEL0 0x40005212 +#define CYDEV_PRTDSI_PRT2_OE_SEL1 0x40005213 +#define CYDEV_PRTDSI_PRT2_DBL_SYNC_IN 0x40005214 +#define CYDEV_PRTDSI_PRT2_SYNC_OUT 0x40005215 +#define CYDEV_PRTDSI_PRT2_CAPS_SEL 0x40005216 +#define CYDEV_PRTDSI_PRT3_BASE 0x40005218 +#define CYDEV_PRTDSI_PRT3_SIZE 0x00000007 +#define CYDEV_PRTDSI_PRT3_OUT_SEL0 0x40005218 +#define CYDEV_PRTDSI_PRT3_OUT_SEL1 0x40005219 +#define CYDEV_PRTDSI_PRT3_OE_SEL0 0x4000521a +#define CYDEV_PRTDSI_PRT3_OE_SEL1 0x4000521b +#define CYDEV_PRTDSI_PRT3_DBL_SYNC_IN 0x4000521c +#define CYDEV_PRTDSI_PRT3_SYNC_OUT 0x4000521d +#define CYDEV_PRTDSI_PRT3_CAPS_SEL 0x4000521e +#define CYDEV_PRTDSI_PRT4_BASE 0x40005220 +#define CYDEV_PRTDSI_PRT4_SIZE 0x00000007 +#define CYDEV_PRTDSI_PRT4_OUT_SEL0 0x40005220 +#define CYDEV_PRTDSI_PRT4_OUT_SEL1 0x40005221 +#define CYDEV_PRTDSI_PRT4_OE_SEL0 0x40005222 +#define CYDEV_PRTDSI_PRT4_OE_SEL1 0x40005223 +#define CYDEV_PRTDSI_PRT4_DBL_SYNC_IN 0x40005224 +#define CYDEV_PRTDSI_PRT4_SYNC_OUT 0x40005225 +#define CYDEV_PRTDSI_PRT4_CAPS_SEL 0x40005226 +#define CYDEV_PRTDSI_PRT5_BASE 0x40005228 +#define CYDEV_PRTDSI_PRT5_SIZE 0x00000007 +#define CYDEV_PRTDSI_PRT5_OUT_SEL0 0x40005228 +#define CYDEV_PRTDSI_PRT5_OUT_SEL1 0x40005229 +#define CYDEV_PRTDSI_PRT5_OE_SEL0 0x4000522a +#define CYDEV_PRTDSI_PRT5_OE_SEL1 0x4000522b +#define CYDEV_PRTDSI_PRT5_DBL_SYNC_IN 0x4000522c +#define CYDEV_PRTDSI_PRT5_SYNC_OUT 0x4000522d +#define CYDEV_PRTDSI_PRT5_CAPS_SEL 0x4000522e +#define CYDEV_PRTDSI_PRT6_BASE 0x40005230 +#define CYDEV_PRTDSI_PRT6_SIZE 0x00000007 +#define CYDEV_PRTDSI_PRT6_OUT_SEL0 0x40005230 +#define CYDEV_PRTDSI_PRT6_OUT_SEL1 0x40005231 +#define CYDEV_PRTDSI_PRT6_OE_SEL0 0x40005232 +#define CYDEV_PRTDSI_PRT6_OE_SEL1 0x40005233 +#define CYDEV_PRTDSI_PRT6_DBL_SYNC_IN 0x40005234 +#define CYDEV_PRTDSI_PRT6_SYNC_OUT 0x40005235 +#define CYDEV_PRTDSI_PRT6_CAPS_SEL 0x40005236 +#define CYDEV_PRTDSI_PRT12_BASE 0x40005260 +#define CYDEV_PRTDSI_PRT12_SIZE 0x00000006 +#define CYDEV_PRTDSI_PRT12_OUT_SEL0 0x40005260 +#define CYDEV_PRTDSI_PRT12_OUT_SEL1 0x40005261 +#define CYDEV_PRTDSI_PRT12_OE_SEL0 0x40005262 +#define CYDEV_PRTDSI_PRT12_OE_SEL1 0x40005263 +#define CYDEV_PRTDSI_PRT12_DBL_SYNC_IN 0x40005264 +#define CYDEV_PRTDSI_PRT12_SYNC_OUT 0x40005265 +#define CYDEV_PRTDSI_PRT15_BASE 0x40005278 +#define CYDEV_PRTDSI_PRT15_SIZE 0x00000007 +#define CYDEV_PRTDSI_PRT15_OUT_SEL0 0x40005278 +#define CYDEV_PRTDSI_PRT15_OUT_SEL1 0x40005279 +#define CYDEV_PRTDSI_PRT15_OE_SEL0 0x4000527a +#define CYDEV_PRTDSI_PRT15_OE_SEL1 0x4000527b +#define CYDEV_PRTDSI_PRT15_DBL_SYNC_IN 0x4000527c +#define CYDEV_PRTDSI_PRT15_SYNC_OUT 0x4000527d +#define CYDEV_PRTDSI_PRT15_CAPS_SEL 0x4000527e +#define CYDEV_EMIF_BASE 0x40005400 +#define CYDEV_EMIF_SIZE 0x00000007 +#define CYDEV_EMIF_NO_UDB 0x40005400 +#define CYDEV_EMIF_RP_WAIT_STATES 0x40005401 +#define CYDEV_EMIF_MEM_DWN 0x40005402 +#define CYDEV_EMIF_MEMCLK_DIV 0x40005403 +#define CYDEV_EMIF_CLOCK_EN 0x40005404 +#define CYDEV_EMIF_EM_TYPE 0x40005405 +#define CYDEV_EMIF_WP_WAIT_STATES 0x40005406 +#define CYDEV_ANAIF_BASE 0x40005800 +#define CYDEV_ANAIF_SIZE 0x000003a9 +#define CYDEV_ANAIF_CFG_BASE 0x40005800 +#define CYDEV_ANAIF_CFG_SIZE 0x0000010f +#define CYDEV_ANAIF_CFG_SC0_BASE 0x40005800 +#define CYDEV_ANAIF_CFG_SC0_SIZE 0x00000003 +#define CYDEV_ANAIF_CFG_SC0_CR0 0x40005800 +#define CYDEV_ANAIF_CFG_SC0_CR1 0x40005801 +#define CYDEV_ANAIF_CFG_SC0_CR2 0x40005802 +#define CYDEV_ANAIF_CFG_SC1_BASE 0x40005804 +#define CYDEV_ANAIF_CFG_SC1_SIZE 0x00000003 +#define CYDEV_ANAIF_CFG_SC1_CR0 0x40005804 +#define CYDEV_ANAIF_CFG_SC1_CR1 0x40005805 +#define CYDEV_ANAIF_CFG_SC1_CR2 0x40005806 +#define CYDEV_ANAIF_CFG_SC2_BASE 0x40005808 +#define CYDEV_ANAIF_CFG_SC2_SIZE 0x00000003 +#define CYDEV_ANAIF_CFG_SC2_CR0 0x40005808 +#define CYDEV_ANAIF_CFG_SC2_CR1 0x40005809 +#define CYDEV_ANAIF_CFG_SC2_CR2 0x4000580a +#define CYDEV_ANAIF_CFG_SC3_BASE 0x4000580c +#define CYDEV_ANAIF_CFG_SC3_SIZE 0x00000003 +#define CYDEV_ANAIF_CFG_SC3_CR0 0x4000580c +#define CYDEV_ANAIF_CFG_SC3_CR1 0x4000580d +#define CYDEV_ANAIF_CFG_SC3_CR2 0x4000580e +#define CYDEV_ANAIF_CFG_DAC0_BASE 0x40005820 +#define CYDEV_ANAIF_CFG_DAC0_SIZE 0x00000003 +#define CYDEV_ANAIF_CFG_DAC0_CR0 0x40005820 +#define CYDEV_ANAIF_CFG_DAC0_CR1 0x40005821 +#define CYDEV_ANAIF_CFG_DAC0_TST 0x40005822 +#define CYDEV_ANAIF_CFG_DAC1_BASE 0x40005824 +#define CYDEV_ANAIF_CFG_DAC1_SIZE 0x00000003 +#define CYDEV_ANAIF_CFG_DAC1_CR0 0x40005824 +#define CYDEV_ANAIF_CFG_DAC1_CR1 0x40005825 +#define CYDEV_ANAIF_CFG_DAC1_TST 0x40005826 +#define CYDEV_ANAIF_CFG_DAC2_BASE 0x40005828 +#define CYDEV_ANAIF_CFG_DAC2_SIZE 0x00000003 +#define CYDEV_ANAIF_CFG_DAC2_CR0 0x40005828 +#define CYDEV_ANAIF_CFG_DAC2_CR1 0x40005829 +#define CYDEV_ANAIF_CFG_DAC2_TST 0x4000582a +#define CYDEV_ANAIF_CFG_DAC3_BASE 0x4000582c +#define CYDEV_ANAIF_CFG_DAC3_SIZE 0x00000003 +#define CYDEV_ANAIF_CFG_DAC3_CR0 0x4000582c +#define CYDEV_ANAIF_CFG_DAC3_CR1 0x4000582d +#define CYDEV_ANAIF_CFG_DAC3_TST 0x4000582e +#define CYDEV_ANAIF_CFG_CMP0_BASE 0x40005840 +#define CYDEV_ANAIF_CFG_CMP0_SIZE 0x00000001 +#define CYDEV_ANAIF_CFG_CMP0_CR 0x40005840 +#define CYDEV_ANAIF_CFG_CMP1_BASE 0x40005841 +#define CYDEV_ANAIF_CFG_CMP1_SIZE 0x00000001 +#define CYDEV_ANAIF_CFG_CMP1_CR 0x40005841 +#define CYDEV_ANAIF_CFG_CMP2_BASE 0x40005842 +#define CYDEV_ANAIF_CFG_CMP2_SIZE 0x00000001 +#define CYDEV_ANAIF_CFG_CMP2_CR 0x40005842 +#define CYDEV_ANAIF_CFG_CMP3_BASE 0x40005843 +#define CYDEV_ANAIF_CFG_CMP3_SIZE 0x00000001 +#define CYDEV_ANAIF_CFG_CMP3_CR 0x40005843 +#define CYDEV_ANAIF_CFG_LUT0_BASE 0x40005848 +#define CYDEV_ANAIF_CFG_LUT0_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_LUT0_CR 0x40005848 +#define CYDEV_ANAIF_CFG_LUT0_MX 0x40005849 +#define CYDEV_ANAIF_CFG_LUT1_BASE 0x4000584a +#define CYDEV_ANAIF_CFG_LUT1_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_LUT1_CR 0x4000584a +#define CYDEV_ANAIF_CFG_LUT1_MX 0x4000584b +#define CYDEV_ANAIF_CFG_LUT2_BASE 0x4000584c +#define CYDEV_ANAIF_CFG_LUT2_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_LUT2_CR 0x4000584c +#define CYDEV_ANAIF_CFG_LUT2_MX 0x4000584d +#define CYDEV_ANAIF_CFG_LUT3_BASE 0x4000584e +#define CYDEV_ANAIF_CFG_LUT3_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_LUT3_CR 0x4000584e +#define CYDEV_ANAIF_CFG_LUT3_MX 0x4000584f +#define CYDEV_ANAIF_CFG_OPAMP0_BASE 0x40005858 +#define CYDEV_ANAIF_CFG_OPAMP0_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_OPAMP0_CR 0x40005858 +#define CYDEV_ANAIF_CFG_OPAMP0_RSVD 0x40005859 +#define CYDEV_ANAIF_CFG_OPAMP1_BASE 0x4000585a +#define CYDEV_ANAIF_CFG_OPAMP1_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_OPAMP1_CR 0x4000585a +#define CYDEV_ANAIF_CFG_OPAMP1_RSVD 0x4000585b +#define CYDEV_ANAIF_CFG_OPAMP2_BASE 0x4000585c +#define CYDEV_ANAIF_CFG_OPAMP2_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_OPAMP2_CR 0x4000585c +#define CYDEV_ANAIF_CFG_OPAMP2_RSVD 0x4000585d +#define CYDEV_ANAIF_CFG_OPAMP3_BASE 0x4000585e +#define CYDEV_ANAIF_CFG_OPAMP3_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_OPAMP3_CR 0x4000585e +#define CYDEV_ANAIF_CFG_OPAMP3_RSVD 0x4000585f +#define CYDEV_ANAIF_CFG_LCDDAC_BASE 0x40005868 +#define CYDEV_ANAIF_CFG_LCDDAC_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_LCDDAC_CR0 0x40005868 +#define CYDEV_ANAIF_CFG_LCDDAC_CR1 0x40005869 +#define CYDEV_ANAIF_CFG_LCDDRV_BASE 0x4000586a +#define CYDEV_ANAIF_CFG_LCDDRV_SIZE 0x00000001 +#define CYDEV_ANAIF_CFG_LCDDRV_CR 0x4000586a +#define CYDEV_ANAIF_CFG_LCDTMR_BASE 0x4000586b +#define CYDEV_ANAIF_CFG_LCDTMR_SIZE 0x00000001 +#define CYDEV_ANAIF_CFG_LCDTMR_CFG 0x4000586b +#define CYDEV_ANAIF_CFG_BG_BASE 0x4000586c +#define CYDEV_ANAIF_CFG_BG_SIZE 0x00000004 +#define CYDEV_ANAIF_CFG_BG_CR0 0x4000586c +#define CYDEV_ANAIF_CFG_BG_RSVD 0x4000586d +#define CYDEV_ANAIF_CFG_BG_DFT0 0x4000586e +#define CYDEV_ANAIF_CFG_BG_DFT1 0x4000586f +#define CYDEV_ANAIF_CFG_CAPSL_BASE 0x40005870 +#define CYDEV_ANAIF_CFG_CAPSL_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_CAPSL_CFG0 0x40005870 +#define CYDEV_ANAIF_CFG_CAPSL_CFG1 0x40005871 +#define CYDEV_ANAIF_CFG_CAPSR_BASE 0x40005872 +#define CYDEV_ANAIF_CFG_CAPSR_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_CAPSR_CFG0 0x40005872 +#define CYDEV_ANAIF_CFG_CAPSR_CFG1 0x40005873 +#define CYDEV_ANAIF_CFG_PUMP_BASE 0x40005876 +#define CYDEV_ANAIF_CFG_PUMP_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_PUMP_CR0 0x40005876 +#define CYDEV_ANAIF_CFG_PUMP_CR1 0x40005877 +#define CYDEV_ANAIF_CFG_LPF0_BASE 0x40005878 +#define CYDEV_ANAIF_CFG_LPF0_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_LPF0_CR0 0x40005878 +#define CYDEV_ANAIF_CFG_LPF0_RSVD 0x40005879 +#define CYDEV_ANAIF_CFG_LPF1_BASE 0x4000587a +#define CYDEV_ANAIF_CFG_LPF1_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_LPF1_CR0 0x4000587a +#define CYDEV_ANAIF_CFG_LPF1_RSVD 0x4000587b +#define CYDEV_ANAIF_CFG_MISC_BASE 0x4000587c +#define CYDEV_ANAIF_CFG_MISC_SIZE 0x00000001 +#define CYDEV_ANAIF_CFG_MISC_CR0 0x4000587c +#define CYDEV_ANAIF_CFG_DSM0_BASE 0x40005880 +#define CYDEV_ANAIF_CFG_DSM0_SIZE 0x00000020 +#define CYDEV_ANAIF_CFG_DSM0_CR0 0x40005880 +#define CYDEV_ANAIF_CFG_DSM0_CR1 0x40005881 +#define CYDEV_ANAIF_CFG_DSM0_CR2 0x40005882 +#define CYDEV_ANAIF_CFG_DSM0_CR3 0x40005883 +#define CYDEV_ANAIF_CFG_DSM0_CR4 0x40005884 +#define CYDEV_ANAIF_CFG_DSM0_CR5 0x40005885 +#define CYDEV_ANAIF_CFG_DSM0_CR6 0x40005886 +#define CYDEV_ANAIF_CFG_DSM0_CR7 0x40005887 +#define CYDEV_ANAIF_CFG_DSM0_CR8 0x40005888 +#define CYDEV_ANAIF_CFG_DSM0_CR9 0x40005889 +#define CYDEV_ANAIF_CFG_DSM0_CR10 0x4000588a +#define CYDEV_ANAIF_CFG_DSM0_CR11 0x4000588b +#define CYDEV_ANAIF_CFG_DSM0_CR12 0x4000588c +#define CYDEV_ANAIF_CFG_DSM0_CR13 0x4000588d +#define CYDEV_ANAIF_CFG_DSM0_CR14 0x4000588e +#define CYDEV_ANAIF_CFG_DSM0_CR15 0x4000588f +#define CYDEV_ANAIF_CFG_DSM0_CR16 0x40005890 +#define CYDEV_ANAIF_CFG_DSM0_CR17 0x40005891 +#define CYDEV_ANAIF_CFG_DSM0_REF0 0x40005892 +#define CYDEV_ANAIF_CFG_DSM0_REF1 0x40005893 +#define CYDEV_ANAIF_CFG_DSM0_REF2 0x40005894 +#define CYDEV_ANAIF_CFG_DSM0_REF3 0x40005895 +#define CYDEV_ANAIF_CFG_DSM0_DEM0 0x40005896 +#define CYDEV_ANAIF_CFG_DSM0_DEM1 0x40005897 +#define CYDEV_ANAIF_CFG_DSM0_TST0 0x40005898 +#define CYDEV_ANAIF_CFG_DSM0_TST1 0x40005899 +#define CYDEV_ANAIF_CFG_DSM0_BUF0 0x4000589a +#define CYDEV_ANAIF_CFG_DSM0_BUF1 0x4000589b +#define CYDEV_ANAIF_CFG_DSM0_BUF2 0x4000589c +#define CYDEV_ANAIF_CFG_DSM0_BUF3 0x4000589d +#define CYDEV_ANAIF_CFG_DSM0_MISC 0x4000589e +#define CYDEV_ANAIF_CFG_DSM0_RSVD1 0x4000589f +#define CYDEV_ANAIF_CFG_SAR0_BASE 0x40005900 +#define CYDEV_ANAIF_CFG_SAR0_SIZE 0x00000007 +#define CYDEV_ANAIF_CFG_SAR0_CSR0 0x40005900 +#define CYDEV_ANAIF_CFG_SAR0_CSR1 0x40005901 +#define CYDEV_ANAIF_CFG_SAR0_CSR2 0x40005902 +#define CYDEV_ANAIF_CFG_SAR0_CSR3 0x40005903 +#define CYDEV_ANAIF_CFG_SAR0_CSR4 0x40005904 +#define CYDEV_ANAIF_CFG_SAR0_CSR5 0x40005905 +#define CYDEV_ANAIF_CFG_SAR0_CSR6 0x40005906 +#define CYDEV_ANAIF_CFG_SAR1_BASE 0x40005908 +#define CYDEV_ANAIF_CFG_SAR1_SIZE 0x00000007 +#define CYDEV_ANAIF_CFG_SAR1_CSR0 0x40005908 +#define CYDEV_ANAIF_CFG_SAR1_CSR1 0x40005909 +#define CYDEV_ANAIF_CFG_SAR1_CSR2 0x4000590a +#define CYDEV_ANAIF_CFG_SAR1_CSR3 0x4000590b +#define CYDEV_ANAIF_CFG_SAR1_CSR4 0x4000590c +#define CYDEV_ANAIF_CFG_SAR1_CSR5 0x4000590d +#define CYDEV_ANAIF_CFG_SAR1_CSR6 0x4000590e +#define CYDEV_ANAIF_RT_BASE 0x40005a00 +#define CYDEV_ANAIF_RT_SIZE 0x00000162 +#define CYDEV_ANAIF_RT_SC0_BASE 0x40005a00 +#define CYDEV_ANAIF_RT_SC0_SIZE 0x0000000d +#define CYDEV_ANAIF_RT_SC0_SW0 0x40005a00 +#define CYDEV_ANAIF_RT_SC0_SW2 0x40005a02 +#define CYDEV_ANAIF_RT_SC0_SW3 0x40005a03 +#define CYDEV_ANAIF_RT_SC0_SW4 0x40005a04 +#define CYDEV_ANAIF_RT_SC0_SW6 0x40005a06 +#define CYDEV_ANAIF_RT_SC0_SW7 0x40005a07 +#define CYDEV_ANAIF_RT_SC0_SW8 0x40005a08 +#define CYDEV_ANAIF_RT_SC0_SW10 0x40005a0a +#define CYDEV_ANAIF_RT_SC0_CLK 0x40005a0b +#define CYDEV_ANAIF_RT_SC0_BST 0x40005a0c +#define CYDEV_ANAIF_RT_SC1_BASE 0x40005a10 +#define CYDEV_ANAIF_RT_SC1_SIZE 0x0000000d +#define CYDEV_ANAIF_RT_SC1_SW0 0x40005a10 +#define CYDEV_ANAIF_RT_SC1_SW2 0x40005a12 +#define CYDEV_ANAIF_RT_SC1_SW3 0x40005a13 +#define CYDEV_ANAIF_RT_SC1_SW4 0x40005a14 +#define CYDEV_ANAIF_RT_SC1_SW6 0x40005a16 +#define CYDEV_ANAIF_RT_SC1_SW7 0x40005a17 +#define CYDEV_ANAIF_RT_SC1_SW8 0x40005a18 +#define CYDEV_ANAIF_RT_SC1_SW10 0x40005a1a +#define CYDEV_ANAIF_RT_SC1_CLK 0x40005a1b +#define CYDEV_ANAIF_RT_SC1_BST 0x40005a1c +#define CYDEV_ANAIF_RT_SC2_BASE 0x40005a20 +#define CYDEV_ANAIF_RT_SC2_SIZE 0x0000000d +#define CYDEV_ANAIF_RT_SC2_SW0 0x40005a20 +#define CYDEV_ANAIF_RT_SC2_SW2 0x40005a22 +#define CYDEV_ANAIF_RT_SC2_SW3 0x40005a23 +#define CYDEV_ANAIF_RT_SC2_SW4 0x40005a24 +#define CYDEV_ANAIF_RT_SC2_SW6 0x40005a26 +#define CYDEV_ANAIF_RT_SC2_SW7 0x40005a27 +#define CYDEV_ANAIF_RT_SC2_SW8 0x40005a28 +#define CYDEV_ANAIF_RT_SC2_SW10 0x40005a2a +#define CYDEV_ANAIF_RT_SC2_CLK 0x40005a2b +#define CYDEV_ANAIF_RT_SC2_BST 0x40005a2c +#define CYDEV_ANAIF_RT_SC3_BASE 0x40005a30 +#define CYDEV_ANAIF_RT_SC3_SIZE 0x0000000d +#define CYDEV_ANAIF_RT_SC3_SW0 0x40005a30 +#define CYDEV_ANAIF_RT_SC3_SW2 0x40005a32 +#define CYDEV_ANAIF_RT_SC3_SW3 0x40005a33 +#define CYDEV_ANAIF_RT_SC3_SW4 0x40005a34 +#define CYDEV_ANAIF_RT_SC3_SW6 0x40005a36 +#define CYDEV_ANAIF_RT_SC3_SW7 0x40005a37 +#define CYDEV_ANAIF_RT_SC3_SW8 0x40005a38 +#define CYDEV_ANAIF_RT_SC3_SW10 0x40005a3a +#define CYDEV_ANAIF_RT_SC3_CLK 0x40005a3b +#define CYDEV_ANAIF_RT_SC3_BST 0x40005a3c +#define CYDEV_ANAIF_RT_DAC0_BASE 0x40005a80 +#define CYDEV_ANAIF_RT_DAC0_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_DAC0_SW0 0x40005a80 +#define CYDEV_ANAIF_RT_DAC0_SW2 0x40005a82 +#define CYDEV_ANAIF_RT_DAC0_SW3 0x40005a83 +#define CYDEV_ANAIF_RT_DAC0_SW4 0x40005a84 +#define CYDEV_ANAIF_RT_DAC0_STROBE 0x40005a87 +#define CYDEV_ANAIF_RT_DAC1_BASE 0x40005a88 +#define CYDEV_ANAIF_RT_DAC1_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_DAC1_SW0 0x40005a88 +#define CYDEV_ANAIF_RT_DAC1_SW2 0x40005a8a +#define CYDEV_ANAIF_RT_DAC1_SW3 0x40005a8b +#define CYDEV_ANAIF_RT_DAC1_SW4 0x40005a8c +#define CYDEV_ANAIF_RT_DAC1_STROBE 0x40005a8f +#define CYDEV_ANAIF_RT_DAC2_BASE 0x40005a90 +#define CYDEV_ANAIF_RT_DAC2_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_DAC2_SW0 0x40005a90 +#define CYDEV_ANAIF_RT_DAC2_SW2 0x40005a92 +#define CYDEV_ANAIF_RT_DAC2_SW3 0x40005a93 +#define CYDEV_ANAIF_RT_DAC2_SW4 0x40005a94 +#define CYDEV_ANAIF_RT_DAC2_STROBE 0x40005a97 +#define CYDEV_ANAIF_RT_DAC3_BASE 0x40005a98 +#define CYDEV_ANAIF_RT_DAC3_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_DAC3_SW0 0x40005a98 +#define CYDEV_ANAIF_RT_DAC3_SW2 0x40005a9a +#define CYDEV_ANAIF_RT_DAC3_SW3 0x40005a9b +#define CYDEV_ANAIF_RT_DAC3_SW4 0x40005a9c +#define CYDEV_ANAIF_RT_DAC3_STROBE 0x40005a9f +#define CYDEV_ANAIF_RT_CMP0_BASE 0x40005ac0 +#define CYDEV_ANAIF_RT_CMP0_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_CMP0_SW0 0x40005ac0 +#define CYDEV_ANAIF_RT_CMP0_SW2 0x40005ac2 +#define CYDEV_ANAIF_RT_CMP0_SW3 0x40005ac3 +#define CYDEV_ANAIF_RT_CMP0_SW4 0x40005ac4 +#define CYDEV_ANAIF_RT_CMP0_SW6 0x40005ac6 +#define CYDEV_ANAIF_RT_CMP0_CLK 0x40005ac7 +#define CYDEV_ANAIF_RT_CMP1_BASE 0x40005ac8 +#define CYDEV_ANAIF_RT_CMP1_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_CMP1_SW0 0x40005ac8 +#define CYDEV_ANAIF_RT_CMP1_SW2 0x40005aca +#define CYDEV_ANAIF_RT_CMP1_SW3 0x40005acb +#define CYDEV_ANAIF_RT_CMP1_SW4 0x40005acc +#define CYDEV_ANAIF_RT_CMP1_SW6 0x40005ace +#define CYDEV_ANAIF_RT_CMP1_CLK 0x40005acf +#define CYDEV_ANAIF_RT_CMP2_BASE 0x40005ad0 +#define CYDEV_ANAIF_RT_CMP2_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_CMP2_SW0 0x40005ad0 +#define CYDEV_ANAIF_RT_CMP2_SW2 0x40005ad2 +#define CYDEV_ANAIF_RT_CMP2_SW3 0x40005ad3 +#define CYDEV_ANAIF_RT_CMP2_SW4 0x40005ad4 +#define CYDEV_ANAIF_RT_CMP2_SW6 0x40005ad6 +#define CYDEV_ANAIF_RT_CMP2_CLK 0x40005ad7 +#define CYDEV_ANAIF_RT_CMP3_BASE 0x40005ad8 +#define CYDEV_ANAIF_RT_CMP3_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_CMP3_SW0 0x40005ad8 +#define CYDEV_ANAIF_RT_CMP3_SW2 0x40005ada +#define CYDEV_ANAIF_RT_CMP3_SW3 0x40005adb +#define CYDEV_ANAIF_RT_CMP3_SW4 0x40005adc +#define CYDEV_ANAIF_RT_CMP3_SW6 0x40005ade +#define CYDEV_ANAIF_RT_CMP3_CLK 0x40005adf +#define CYDEV_ANAIF_RT_DSM0_BASE 0x40005b00 +#define CYDEV_ANAIF_RT_DSM0_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_DSM0_SW0 0x40005b00 +#define CYDEV_ANAIF_RT_DSM0_SW2 0x40005b02 +#define CYDEV_ANAIF_RT_DSM0_SW3 0x40005b03 +#define CYDEV_ANAIF_RT_DSM0_SW4 0x40005b04 +#define CYDEV_ANAIF_RT_DSM0_SW6 0x40005b06 +#define CYDEV_ANAIF_RT_DSM0_CLK 0x40005b07 +#define CYDEV_ANAIF_RT_SAR0_BASE 0x40005b20 +#define CYDEV_ANAIF_RT_SAR0_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_SAR0_SW0 0x40005b20 +#define CYDEV_ANAIF_RT_SAR0_SW2 0x40005b22 +#define CYDEV_ANAIF_RT_SAR0_SW3 0x40005b23 +#define CYDEV_ANAIF_RT_SAR0_SW4 0x40005b24 +#define CYDEV_ANAIF_RT_SAR0_SW6 0x40005b26 +#define CYDEV_ANAIF_RT_SAR0_CLK 0x40005b27 +#define CYDEV_ANAIF_RT_SAR1_BASE 0x40005b28 +#define CYDEV_ANAIF_RT_SAR1_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_SAR1_SW0 0x40005b28 +#define CYDEV_ANAIF_RT_SAR1_SW2 0x40005b2a +#define CYDEV_ANAIF_RT_SAR1_SW3 0x40005b2b +#define CYDEV_ANAIF_RT_SAR1_SW4 0x40005b2c +#define CYDEV_ANAIF_RT_SAR1_SW6 0x40005b2e +#define CYDEV_ANAIF_RT_SAR1_CLK 0x40005b2f +#define CYDEV_ANAIF_RT_OPAMP0_BASE 0x40005b40 +#define CYDEV_ANAIF_RT_OPAMP0_SIZE 0x00000002 +#define CYDEV_ANAIF_RT_OPAMP0_MX 0x40005b40 +#define CYDEV_ANAIF_RT_OPAMP0_SW 0x40005b41 +#define CYDEV_ANAIF_RT_OPAMP1_BASE 0x40005b42 +#define CYDEV_ANAIF_RT_OPAMP1_SIZE 0x00000002 +#define CYDEV_ANAIF_RT_OPAMP1_MX 0x40005b42 +#define CYDEV_ANAIF_RT_OPAMP1_SW 0x40005b43 +#define CYDEV_ANAIF_RT_OPAMP2_BASE 0x40005b44 +#define CYDEV_ANAIF_RT_OPAMP2_SIZE 0x00000002 +#define CYDEV_ANAIF_RT_OPAMP2_MX 0x40005b44 +#define CYDEV_ANAIF_RT_OPAMP2_SW 0x40005b45 +#define CYDEV_ANAIF_RT_OPAMP3_BASE 0x40005b46 +#define CYDEV_ANAIF_RT_OPAMP3_SIZE 0x00000002 +#define CYDEV_ANAIF_RT_OPAMP3_MX 0x40005b46 +#define CYDEV_ANAIF_RT_OPAMP3_SW 0x40005b47 +#define CYDEV_ANAIF_RT_LCDDAC_BASE 0x40005b50 +#define CYDEV_ANAIF_RT_LCDDAC_SIZE 0x00000005 +#define CYDEV_ANAIF_RT_LCDDAC_SW0 0x40005b50 +#define CYDEV_ANAIF_RT_LCDDAC_SW1 0x40005b51 +#define CYDEV_ANAIF_RT_LCDDAC_SW2 0x40005b52 +#define CYDEV_ANAIF_RT_LCDDAC_SW3 0x40005b53 +#define CYDEV_ANAIF_RT_LCDDAC_SW4 0x40005b54 +#define CYDEV_ANAIF_RT_SC_BASE 0x40005b56 +#define CYDEV_ANAIF_RT_SC_SIZE 0x00000001 +#define CYDEV_ANAIF_RT_SC_MISC 0x40005b56 +#define CYDEV_ANAIF_RT_BUS_BASE 0x40005b58 +#define CYDEV_ANAIF_RT_BUS_SIZE 0x00000004 +#define CYDEV_ANAIF_RT_BUS_SW0 0x40005b58 +#define CYDEV_ANAIF_RT_BUS_SW2 0x40005b5a +#define CYDEV_ANAIF_RT_BUS_SW3 0x40005b5b +#define CYDEV_ANAIF_RT_DFT_BASE 0x40005b5c +#define CYDEV_ANAIF_RT_DFT_SIZE 0x00000006 +#define CYDEV_ANAIF_RT_DFT_CR0 0x40005b5c +#define CYDEV_ANAIF_RT_DFT_CR1 0x40005b5d +#define CYDEV_ANAIF_RT_DFT_CR2 0x40005b5e +#define CYDEV_ANAIF_RT_DFT_CR3 0x40005b5f +#define CYDEV_ANAIF_RT_DFT_CR4 0x40005b60 +#define CYDEV_ANAIF_RT_DFT_CR5 0x40005b61 +#define CYDEV_ANAIF_WRK_BASE 0x40005b80 +#define CYDEV_ANAIF_WRK_SIZE 0x00000029 +#define CYDEV_ANAIF_WRK_DAC0_BASE 0x40005b80 +#define CYDEV_ANAIF_WRK_DAC0_SIZE 0x00000001 +#define CYDEV_ANAIF_WRK_DAC0_D 0x40005b80 +#define CYDEV_ANAIF_WRK_DAC1_BASE 0x40005b81 +#define CYDEV_ANAIF_WRK_DAC1_SIZE 0x00000001 +#define CYDEV_ANAIF_WRK_DAC1_D 0x40005b81 +#define CYDEV_ANAIF_WRK_DAC2_BASE 0x40005b82 +#define CYDEV_ANAIF_WRK_DAC2_SIZE 0x00000001 +#define CYDEV_ANAIF_WRK_DAC2_D 0x40005b82 +#define CYDEV_ANAIF_WRK_DAC3_BASE 0x40005b83 +#define CYDEV_ANAIF_WRK_DAC3_SIZE 0x00000001 +#define CYDEV_ANAIF_WRK_DAC3_D 0x40005b83 +#define CYDEV_ANAIF_WRK_DSM0_BASE 0x40005b88 +#define CYDEV_ANAIF_WRK_DSM0_SIZE 0x00000002 +#define CYDEV_ANAIF_WRK_DSM0_OUT0 0x40005b88 +#define CYDEV_ANAIF_WRK_DSM0_OUT1 0x40005b89 +#define CYDEV_ANAIF_WRK_LUT_BASE 0x40005b90 +#define CYDEV_ANAIF_WRK_LUT_SIZE 0x00000005 +#define CYDEV_ANAIF_WRK_LUT_SR 0x40005b90 +#define CYDEV_ANAIF_WRK_LUT_WRK1 0x40005b91 +#define CYDEV_ANAIF_WRK_LUT_MSK 0x40005b92 +#define CYDEV_ANAIF_WRK_LUT_CLK 0x40005b93 +#define CYDEV_ANAIF_WRK_LUT_CPTR 0x40005b94 +#define CYDEV_ANAIF_WRK_CMP_BASE 0x40005b96 +#define CYDEV_ANAIF_WRK_CMP_SIZE 0x00000002 +#define CYDEV_ANAIF_WRK_CMP_WRK 0x40005b96 +#define CYDEV_ANAIF_WRK_CMP_TST 0x40005b97 +#define CYDEV_ANAIF_WRK_SC_BASE 0x40005b98 +#define CYDEV_ANAIF_WRK_SC_SIZE 0x00000005 +#define CYDEV_ANAIF_WRK_SC_SR 0x40005b98 +#define CYDEV_ANAIF_WRK_SC_WRK1 0x40005b99 +#define CYDEV_ANAIF_WRK_SC_MSK 0x40005b9a +#define CYDEV_ANAIF_WRK_SC_CMPINV 0x40005b9b +#define CYDEV_ANAIF_WRK_SC_CPTR 0x40005b9c +#define CYDEV_ANAIF_WRK_SAR0_BASE 0x40005ba0 +#define CYDEV_ANAIF_WRK_SAR0_SIZE 0x00000002 +#define CYDEV_ANAIF_WRK_SAR0_WRK0 0x40005ba0 +#define CYDEV_ANAIF_WRK_SAR0_WRK1 0x40005ba1 +#define CYDEV_ANAIF_WRK_SAR1_BASE 0x40005ba2 +#define CYDEV_ANAIF_WRK_SAR1_SIZE 0x00000002 +#define CYDEV_ANAIF_WRK_SAR1_WRK0 0x40005ba2 +#define CYDEV_ANAIF_WRK_SAR1_WRK1 0x40005ba3 +#define CYDEV_ANAIF_WRK_SARS_BASE 0x40005ba8 +#define CYDEV_ANAIF_WRK_SARS_SIZE 0x00000001 +#define CYDEV_ANAIF_WRK_SARS_SOF 0x40005ba8 +#define CYDEV_USB_BASE 0x40006000 +#define CYDEV_USB_SIZE 0x00000300 +#define CYDEV_USB_EP0_DR0 0x40006000 +#define CYDEV_USB_EP0_DR1 0x40006001 +#define CYDEV_USB_EP0_DR2 0x40006002 +#define CYDEV_USB_EP0_DR3 0x40006003 +#define CYDEV_USB_EP0_DR4 0x40006004 +#define CYDEV_USB_EP0_DR5 0x40006005 +#define CYDEV_USB_EP0_DR6 0x40006006 +#define CYDEV_USB_EP0_DR7 0x40006007 +#define CYDEV_USB_CR0 0x40006008 +#define CYDEV_USB_CR1 0x40006009 +#define CYDEV_USB_SIE_EP_INT_EN 0x4000600a +#define CYDEV_USB_SIE_EP_INT_SR 0x4000600b +#define CYDEV_USB_SIE_EP1_BASE 0x4000600c +#define CYDEV_USB_SIE_EP1_SIZE 0x00000003 +#define CYDEV_USB_SIE_EP1_CNT0 0x4000600c +#define CYDEV_USB_SIE_EP1_CNT1 0x4000600d +#define CYDEV_USB_SIE_EP1_CR0 0x4000600e +#define CYDEV_USB_USBIO_CR0 0x40006010 +#define CYDEV_USB_USBIO_CR1 0x40006012 +#define CYDEV_USB_DYN_RECONFIG 0x40006014 +#define CYDEV_USB_SOF0 0x40006018 +#define CYDEV_USB_SOF1 0x40006019 +#define CYDEV_USB_SIE_EP2_BASE 0x4000601c +#define CYDEV_USB_SIE_EP2_SIZE 0x00000003 +#define CYDEV_USB_SIE_EP2_CNT0 0x4000601c +#define CYDEV_USB_SIE_EP2_CNT1 0x4000601d +#define CYDEV_USB_SIE_EP2_CR0 0x4000601e +#define CYDEV_USB_EP0_CR 0x40006028 +#define CYDEV_USB_EP0_CNT 0x40006029 +#define CYDEV_USB_SIE_EP3_BASE 0x4000602c +#define CYDEV_USB_SIE_EP3_SIZE 0x00000003 +#define CYDEV_USB_SIE_EP3_CNT0 0x4000602c +#define CYDEV_USB_SIE_EP3_CNT1 0x4000602d +#define CYDEV_USB_SIE_EP3_CR0 0x4000602e +#define CYDEV_USB_SIE_EP4_BASE 0x4000603c +#define CYDEV_USB_SIE_EP4_SIZE 0x00000003 +#define CYDEV_USB_SIE_EP4_CNT0 0x4000603c +#define CYDEV_USB_SIE_EP4_CNT1 0x4000603d +#define CYDEV_USB_SIE_EP4_CR0 0x4000603e +#define CYDEV_USB_SIE_EP5_BASE 0x4000604c +#define CYDEV_USB_SIE_EP5_SIZE 0x00000003 +#define CYDEV_USB_SIE_EP5_CNT0 0x4000604c +#define CYDEV_USB_SIE_EP5_CNT1 0x4000604d +#define CYDEV_USB_SIE_EP5_CR0 0x4000604e +#define CYDEV_USB_SIE_EP6_BASE 0x4000605c +#define CYDEV_USB_SIE_EP6_SIZE 0x00000003 +#define CYDEV_USB_SIE_EP6_CNT0 0x4000605c +#define CYDEV_USB_SIE_EP6_CNT1 0x4000605d +#define CYDEV_USB_SIE_EP6_CR0 0x4000605e +#define CYDEV_USB_SIE_EP7_BASE 0x4000606c +#define CYDEV_USB_SIE_EP7_SIZE 0x00000003 +#define CYDEV_USB_SIE_EP7_CNT0 0x4000606c +#define CYDEV_USB_SIE_EP7_CNT1 0x4000606d +#define CYDEV_USB_SIE_EP7_CR0 0x4000606e +#define CYDEV_USB_SIE_EP8_BASE 0x4000607c +#define CYDEV_USB_SIE_EP8_SIZE 0x00000003 +#define CYDEV_USB_SIE_EP8_CNT0 0x4000607c +#define CYDEV_USB_SIE_EP8_CNT1 0x4000607d +#define CYDEV_USB_SIE_EP8_CR0 0x4000607e +#define CYDEV_USB_ARB_EP1_BASE 0x40006080 +#define CYDEV_USB_ARB_EP1_SIZE 0x00000003 +#define CYDEV_USB_ARB_EP1_CFG 0x40006080 +#define CYDEV_USB_ARB_EP1_INT_EN 0x40006081 +#define CYDEV_USB_ARB_EP1_SR 0x40006082 +#define CYDEV_USB_ARB_RW1_BASE 0x40006084 +#define CYDEV_USB_ARB_RW1_SIZE 0x00000005 +#define CYDEV_USB_ARB_RW1_WA 0x40006084 +#define CYDEV_USB_ARB_RW1_WA_MSB 0x40006085 +#define CYDEV_USB_ARB_RW1_RA 0x40006086 +#define CYDEV_USB_ARB_RW1_RA_MSB 0x40006087 +#define CYDEV_USB_ARB_RW1_DR 0x40006088 +#define CYDEV_USB_BUF_SIZE 0x4000608c +#define CYDEV_USB_EP_ACTIVE 0x4000608e +#define CYDEV_USB_EP_TYPE 0x4000608f +#define CYDEV_USB_ARB_EP2_BASE 0x40006090 +#define CYDEV_USB_ARB_EP2_SIZE 0x00000003 +#define CYDEV_USB_ARB_EP2_CFG 0x40006090 +#define CYDEV_USB_ARB_EP2_INT_EN 0x40006091 +#define CYDEV_USB_ARB_EP2_SR 0x40006092 +#define CYDEV_USB_ARB_RW2_BASE 0x40006094 +#define CYDEV_USB_ARB_RW2_SIZE 0x00000005 +#define CYDEV_USB_ARB_RW2_WA 0x40006094 +#define CYDEV_USB_ARB_RW2_WA_MSB 0x40006095 +#define CYDEV_USB_ARB_RW2_RA 0x40006096 +#define CYDEV_USB_ARB_RW2_RA_MSB 0x40006097 +#define CYDEV_USB_ARB_RW2_DR 0x40006098 +#define CYDEV_USB_ARB_CFG 0x4000609c +#define CYDEV_USB_USB_CLK_EN 0x4000609d +#define CYDEV_USB_ARB_INT_EN 0x4000609e +#define CYDEV_USB_ARB_INT_SR 0x4000609f +#define CYDEV_USB_ARB_EP3_BASE 0x400060a0 +#define CYDEV_USB_ARB_EP3_SIZE 0x00000003 +#define CYDEV_USB_ARB_EP3_CFG 0x400060a0 +#define CYDEV_USB_ARB_EP3_INT_EN 0x400060a1 +#define CYDEV_USB_ARB_EP3_SR 0x400060a2 +#define CYDEV_USB_ARB_RW3_BASE 0x400060a4 +#define CYDEV_USB_ARB_RW3_SIZE 0x00000005 +#define CYDEV_USB_ARB_RW3_WA 0x400060a4 +#define CYDEV_USB_ARB_RW3_WA_MSB 0x400060a5 +#define CYDEV_USB_ARB_RW3_RA 0x400060a6 +#define CYDEV_USB_ARB_RW3_RA_MSB 0x400060a7 +#define CYDEV_USB_ARB_RW3_DR 0x400060a8 +#define CYDEV_USB_CWA 0x400060ac +#define CYDEV_USB_CWA_MSB 0x400060ad +#define CYDEV_USB_ARB_EP4_BASE 0x400060b0 +#define CYDEV_USB_ARB_EP4_SIZE 0x00000003 +#define CYDEV_USB_ARB_EP4_CFG 0x400060b0 +#define CYDEV_USB_ARB_EP4_INT_EN 0x400060b1 +#define CYDEV_USB_ARB_EP4_SR 0x400060b2 +#define CYDEV_USB_ARB_RW4_BASE 0x400060b4 +#define CYDEV_USB_ARB_RW4_SIZE 0x00000005 +#define CYDEV_USB_ARB_RW4_WA 0x400060b4 +#define CYDEV_USB_ARB_RW4_WA_MSB 0x400060b5 +#define CYDEV_USB_ARB_RW4_RA 0x400060b6 +#define CYDEV_USB_ARB_RW4_RA_MSB 0x400060b7 +#define CYDEV_USB_ARB_RW4_DR 0x400060b8 +#define CYDEV_USB_DMA_THRES 0x400060bc +#define CYDEV_USB_DMA_THRES_MSB 0x400060bd +#define CYDEV_USB_ARB_EP5_BASE 0x400060c0 +#define CYDEV_USB_ARB_EP5_SIZE 0x00000003 +#define CYDEV_USB_ARB_EP5_CFG 0x400060c0 +#define CYDEV_USB_ARB_EP5_INT_EN 0x400060c1 +#define CYDEV_USB_ARB_EP5_SR 0x400060c2 +#define CYDEV_USB_ARB_RW5_BASE 0x400060c4 +#define CYDEV_USB_ARB_RW5_SIZE 0x00000005 +#define CYDEV_USB_ARB_RW5_WA 0x400060c4 +#define CYDEV_USB_ARB_RW5_WA_MSB 0x400060c5 +#define CYDEV_USB_ARB_RW5_RA 0x400060c6 +#define CYDEV_USB_ARB_RW5_RA_MSB 0x400060c7 +#define CYDEV_USB_ARB_RW5_DR 0x400060c8 +#define CYDEV_USB_BUS_RST_CNT 0x400060cc +#define CYDEV_USB_ARB_EP6_BASE 0x400060d0 +#define CYDEV_USB_ARB_EP6_SIZE 0x00000003 +#define CYDEV_USB_ARB_EP6_CFG 0x400060d0 +#define CYDEV_USB_ARB_EP6_INT_EN 0x400060d1 +#define CYDEV_USB_ARB_EP6_SR 0x400060d2 +#define CYDEV_USB_ARB_RW6_BASE 0x400060d4 +#define CYDEV_USB_ARB_RW6_SIZE 0x00000005 +#define CYDEV_USB_ARB_RW6_WA 0x400060d4 +#define CYDEV_USB_ARB_RW6_WA_MSB 0x400060d5 +#define CYDEV_USB_ARB_RW6_RA 0x400060d6 +#define CYDEV_USB_ARB_RW6_RA_MSB 0x400060d7 +#define CYDEV_USB_ARB_RW6_DR 0x400060d8 +#define CYDEV_USB_ARB_EP7_BASE 0x400060e0 +#define CYDEV_USB_ARB_EP7_SIZE 0x00000003 +#define CYDEV_USB_ARB_EP7_CFG 0x400060e0 +#define CYDEV_USB_ARB_EP7_INT_EN 0x400060e1 +#define CYDEV_USB_ARB_EP7_SR 0x400060e2 +#define CYDEV_USB_ARB_RW7_BASE 0x400060e4 +#define CYDEV_USB_ARB_RW7_SIZE 0x00000005 +#define CYDEV_USB_ARB_RW7_WA 0x400060e4 +#define CYDEV_USB_ARB_RW7_WA_MSB 0x400060e5 +#define CYDEV_USB_ARB_RW7_RA 0x400060e6 +#define CYDEV_USB_ARB_RW7_RA_MSB 0x400060e7 +#define CYDEV_USB_ARB_RW7_DR 0x400060e8 +#define CYDEV_USB_ARB_EP8_BASE 0x400060f0 +#define CYDEV_USB_ARB_EP8_SIZE 0x00000003 +#define CYDEV_USB_ARB_EP8_CFG 0x400060f0 +#define CYDEV_USB_ARB_EP8_INT_EN 0x400060f1 +#define CYDEV_USB_ARB_EP8_SR 0x400060f2 +#define CYDEV_USB_ARB_RW8_BASE 0x400060f4 +#define CYDEV_USB_ARB_RW8_SIZE 0x00000005 +#define CYDEV_USB_ARB_RW8_WA 0x400060f4 +#define CYDEV_USB_ARB_RW8_WA_MSB 0x400060f5 +#define CYDEV_USB_ARB_RW8_RA 0x400060f6 +#define CYDEV_USB_ARB_RW8_RA_MSB 0x400060f7 +#define CYDEV_USB_ARB_RW8_DR 0x400060f8 +#define CYDEV_USB_MEM_BASE 0x40006100 +#define CYDEV_USB_MEM_SIZE 0x00000200 +#define CYDEV_USB_MEM_DATA_MBASE 0x40006100 +#define CYDEV_USB_MEM_DATA_MSIZE 0x00000200 +#define CYDEV_UWRK_BASE 0x40006400 +#define CYDEV_UWRK_SIZE 0x00000b60 +#define CYDEV_UWRK_UWRK8_BASE 0x40006400 +#define CYDEV_UWRK_UWRK8_SIZE 0x000003b0 +#define CYDEV_UWRK_UWRK8_B0_BASE 0x40006400 +#define CYDEV_UWRK_UWRK8_B0_SIZE 0x000000b0 +#define CYDEV_UWRK_UWRK8_B0_UDB00_A0 0x40006400 +#define CYDEV_UWRK_UWRK8_B0_UDB01_A0 0x40006401 +#define CYDEV_UWRK_UWRK8_B0_UDB02_A0 0x40006402 +#define CYDEV_UWRK_UWRK8_B0_UDB03_A0 0x40006403 +#define CYDEV_UWRK_UWRK8_B0_UDB04_A0 0x40006404 +#define CYDEV_UWRK_UWRK8_B0_UDB05_A0 0x40006405 +#define CYDEV_UWRK_UWRK8_B0_UDB06_A0 0x40006406 +#define CYDEV_UWRK_UWRK8_B0_UDB07_A0 0x40006407 +#define CYDEV_UWRK_UWRK8_B0_UDB08_A0 0x40006408 +#define CYDEV_UWRK_UWRK8_B0_UDB09_A0 0x40006409 +#define CYDEV_UWRK_UWRK8_B0_UDB10_A0 0x4000640a +#define CYDEV_UWRK_UWRK8_B0_UDB11_A0 0x4000640b +#define CYDEV_UWRK_UWRK8_B0_UDB12_A0 0x4000640c +#define CYDEV_UWRK_UWRK8_B0_UDB13_A0 0x4000640d +#define CYDEV_UWRK_UWRK8_B0_UDB14_A0 0x4000640e +#define CYDEV_UWRK_UWRK8_B0_UDB15_A0 0x4000640f +#define CYDEV_UWRK_UWRK8_B0_UDB00_A1 0x40006410 +#define CYDEV_UWRK_UWRK8_B0_UDB01_A1 0x40006411 +#define CYDEV_UWRK_UWRK8_B0_UDB02_A1 0x40006412 +#define CYDEV_UWRK_UWRK8_B0_UDB03_A1 0x40006413 +#define CYDEV_UWRK_UWRK8_B0_UDB04_A1 0x40006414 +#define CYDEV_UWRK_UWRK8_B0_UDB05_A1 0x40006415 +#define CYDEV_UWRK_UWRK8_B0_UDB06_A1 0x40006416 +#define CYDEV_UWRK_UWRK8_B0_UDB07_A1 0x40006417 +#define CYDEV_UWRK_UWRK8_B0_UDB08_A1 0x40006418 +#define CYDEV_UWRK_UWRK8_B0_UDB09_A1 0x40006419 +#define CYDEV_UWRK_UWRK8_B0_UDB10_A1 0x4000641a +#define CYDEV_UWRK_UWRK8_B0_UDB11_A1 0x4000641b +#define CYDEV_UWRK_UWRK8_B0_UDB12_A1 0x4000641c +#define CYDEV_UWRK_UWRK8_B0_UDB13_A1 0x4000641d +#define CYDEV_UWRK_UWRK8_B0_UDB14_A1 0x4000641e +#define CYDEV_UWRK_UWRK8_B0_UDB15_A1 0x4000641f +#define CYDEV_UWRK_UWRK8_B0_UDB00_D0 0x40006420 +#define CYDEV_UWRK_UWRK8_B0_UDB01_D0 0x40006421 +#define CYDEV_UWRK_UWRK8_B0_UDB02_D0 0x40006422 +#define CYDEV_UWRK_UWRK8_B0_UDB03_D0 0x40006423 +#define CYDEV_UWRK_UWRK8_B0_UDB04_D0 0x40006424 +#define CYDEV_UWRK_UWRK8_B0_UDB05_D0 0x40006425 +#define CYDEV_UWRK_UWRK8_B0_UDB06_D0 0x40006426 +#define CYDEV_UWRK_UWRK8_B0_UDB07_D0 0x40006427 +#define CYDEV_UWRK_UWRK8_B0_UDB08_D0 0x40006428 +#define CYDEV_UWRK_UWRK8_B0_UDB09_D0 0x40006429 +#define CYDEV_UWRK_UWRK8_B0_UDB10_D0 0x4000642a +#define CYDEV_UWRK_UWRK8_B0_UDB11_D0 0x4000642b +#define CYDEV_UWRK_UWRK8_B0_UDB12_D0 0x4000642c +#define CYDEV_UWRK_UWRK8_B0_UDB13_D0 0x4000642d +#define CYDEV_UWRK_UWRK8_B0_UDB14_D0 0x4000642e +#define CYDEV_UWRK_UWRK8_B0_UDB15_D0 0x4000642f +#define CYDEV_UWRK_UWRK8_B0_UDB00_D1 0x40006430 +#define CYDEV_UWRK_UWRK8_B0_UDB01_D1 0x40006431 +#define CYDEV_UWRK_UWRK8_B0_UDB02_D1 0x40006432 +#define CYDEV_UWRK_UWRK8_B0_UDB03_D1 0x40006433 +#define CYDEV_UWRK_UWRK8_B0_UDB04_D1 0x40006434 +#define CYDEV_UWRK_UWRK8_B0_UDB05_D1 0x40006435 +#define CYDEV_UWRK_UWRK8_B0_UDB06_D1 0x40006436 +#define CYDEV_UWRK_UWRK8_B0_UDB07_D1 0x40006437 +#define CYDEV_UWRK_UWRK8_B0_UDB08_D1 0x40006438 +#define CYDEV_UWRK_UWRK8_B0_UDB09_D1 0x40006439 +#define CYDEV_UWRK_UWRK8_B0_UDB10_D1 0x4000643a +#define CYDEV_UWRK_UWRK8_B0_UDB11_D1 0x4000643b +#define CYDEV_UWRK_UWRK8_B0_UDB12_D1 0x4000643c +#define CYDEV_UWRK_UWRK8_B0_UDB13_D1 0x4000643d +#define CYDEV_UWRK_UWRK8_B0_UDB14_D1 0x4000643e +#define CYDEV_UWRK_UWRK8_B0_UDB15_D1 0x4000643f +#define CYDEV_UWRK_UWRK8_B0_UDB00_F0 0x40006440 +#define CYDEV_UWRK_UWRK8_B0_UDB01_F0 0x40006441 +#define CYDEV_UWRK_UWRK8_B0_UDB02_F0 0x40006442 +#define CYDEV_UWRK_UWRK8_B0_UDB03_F0 0x40006443 +#define CYDEV_UWRK_UWRK8_B0_UDB04_F0 0x40006444 +#define CYDEV_UWRK_UWRK8_B0_UDB05_F0 0x40006445 +#define CYDEV_UWRK_UWRK8_B0_UDB06_F0 0x40006446 +#define CYDEV_UWRK_UWRK8_B0_UDB07_F0 0x40006447 +#define CYDEV_UWRK_UWRK8_B0_UDB08_F0 0x40006448 +#define CYDEV_UWRK_UWRK8_B0_UDB09_F0 0x40006449 +#define CYDEV_UWRK_UWRK8_B0_UDB10_F0 0x4000644a +#define CYDEV_UWRK_UWRK8_B0_UDB11_F0 0x4000644b +#define CYDEV_UWRK_UWRK8_B0_UDB12_F0 0x4000644c +#define CYDEV_UWRK_UWRK8_B0_UDB13_F0 0x4000644d +#define CYDEV_UWRK_UWRK8_B0_UDB14_F0 0x4000644e +#define CYDEV_UWRK_UWRK8_B0_UDB15_F0 0x4000644f +#define CYDEV_UWRK_UWRK8_B0_UDB00_F1 0x40006450 +#define CYDEV_UWRK_UWRK8_B0_UDB01_F1 0x40006451 +#define CYDEV_UWRK_UWRK8_B0_UDB02_F1 0x40006452 +#define CYDEV_UWRK_UWRK8_B0_UDB03_F1 0x40006453 +#define CYDEV_UWRK_UWRK8_B0_UDB04_F1 0x40006454 +#define CYDEV_UWRK_UWRK8_B0_UDB05_F1 0x40006455 +#define CYDEV_UWRK_UWRK8_B0_UDB06_F1 0x40006456 +#define CYDEV_UWRK_UWRK8_B0_UDB07_F1 0x40006457 +#define CYDEV_UWRK_UWRK8_B0_UDB08_F1 0x40006458 +#define CYDEV_UWRK_UWRK8_B0_UDB09_F1 0x40006459 +#define CYDEV_UWRK_UWRK8_B0_UDB10_F1 0x4000645a +#define CYDEV_UWRK_UWRK8_B0_UDB11_F1 0x4000645b +#define CYDEV_UWRK_UWRK8_B0_UDB12_F1 0x4000645c +#define CYDEV_UWRK_UWRK8_B0_UDB13_F1 0x4000645d +#define CYDEV_UWRK_UWRK8_B0_UDB14_F1 0x4000645e +#define CYDEV_UWRK_UWRK8_B0_UDB15_F1 0x4000645f +#define CYDEV_UWRK_UWRK8_B0_UDB00_ST 0x40006460 +#define CYDEV_UWRK_UWRK8_B0_UDB01_ST 0x40006461 +#define CYDEV_UWRK_UWRK8_B0_UDB02_ST 0x40006462 +#define CYDEV_UWRK_UWRK8_B0_UDB03_ST 0x40006463 +#define CYDEV_UWRK_UWRK8_B0_UDB04_ST 0x40006464 +#define CYDEV_UWRK_UWRK8_B0_UDB05_ST 0x40006465 +#define CYDEV_UWRK_UWRK8_B0_UDB06_ST 0x40006466 +#define CYDEV_UWRK_UWRK8_B0_UDB07_ST 0x40006467 +#define CYDEV_UWRK_UWRK8_B0_UDB08_ST 0x40006468 +#define CYDEV_UWRK_UWRK8_B0_UDB09_ST 0x40006469 +#define CYDEV_UWRK_UWRK8_B0_UDB10_ST 0x4000646a +#define CYDEV_UWRK_UWRK8_B0_UDB11_ST 0x4000646b +#define CYDEV_UWRK_UWRK8_B0_UDB12_ST 0x4000646c +#define CYDEV_UWRK_UWRK8_B0_UDB13_ST 0x4000646d +#define CYDEV_UWRK_UWRK8_B0_UDB14_ST 0x4000646e +#define CYDEV_UWRK_UWRK8_B0_UDB15_ST 0x4000646f +#define CYDEV_UWRK_UWRK8_B0_UDB00_CTL 0x40006470 +#define CYDEV_UWRK_UWRK8_B0_UDB01_CTL 0x40006471 +#define CYDEV_UWRK_UWRK8_B0_UDB02_CTL 0x40006472 +#define CYDEV_UWRK_UWRK8_B0_UDB03_CTL 0x40006473 +#define CYDEV_UWRK_UWRK8_B0_UDB04_CTL 0x40006474 +#define CYDEV_UWRK_UWRK8_B0_UDB05_CTL 0x40006475 +#define CYDEV_UWRK_UWRK8_B0_UDB06_CTL 0x40006476 +#define CYDEV_UWRK_UWRK8_B0_UDB07_CTL 0x40006477 +#define CYDEV_UWRK_UWRK8_B0_UDB08_CTL 0x40006478 +#define CYDEV_UWRK_UWRK8_B0_UDB09_CTL 0x40006479 +#define CYDEV_UWRK_UWRK8_B0_UDB10_CTL 0x4000647a +#define CYDEV_UWRK_UWRK8_B0_UDB11_CTL 0x4000647b +#define CYDEV_UWRK_UWRK8_B0_UDB12_CTL 0x4000647c +#define CYDEV_UWRK_UWRK8_B0_UDB13_CTL 0x4000647d +#define CYDEV_UWRK_UWRK8_B0_UDB14_CTL 0x4000647e +#define CYDEV_UWRK_UWRK8_B0_UDB15_CTL 0x4000647f +#define CYDEV_UWRK_UWRK8_B0_UDB00_MSK 0x40006480 +#define CYDEV_UWRK_UWRK8_B0_UDB01_MSK 0x40006481 +#define CYDEV_UWRK_UWRK8_B0_UDB02_MSK 0x40006482 +#define CYDEV_UWRK_UWRK8_B0_UDB03_MSK 0x40006483 +#define CYDEV_UWRK_UWRK8_B0_UDB04_MSK 0x40006484 +#define CYDEV_UWRK_UWRK8_B0_UDB05_MSK 0x40006485 +#define CYDEV_UWRK_UWRK8_B0_UDB06_MSK 0x40006486 +#define CYDEV_UWRK_UWRK8_B0_UDB07_MSK 0x40006487 +#define CYDEV_UWRK_UWRK8_B0_UDB08_MSK 0x40006488 +#define CYDEV_UWRK_UWRK8_B0_UDB09_MSK 0x40006489 +#define CYDEV_UWRK_UWRK8_B0_UDB10_MSK 0x4000648a +#define CYDEV_UWRK_UWRK8_B0_UDB11_MSK 0x4000648b +#define CYDEV_UWRK_UWRK8_B0_UDB12_MSK 0x4000648c +#define CYDEV_UWRK_UWRK8_B0_UDB13_MSK 0x4000648d +#define CYDEV_UWRK_UWRK8_B0_UDB14_MSK 0x4000648e +#define CYDEV_UWRK_UWRK8_B0_UDB15_MSK 0x4000648f +#define CYDEV_UWRK_UWRK8_B0_UDB00_ACTL 0x40006490 +#define CYDEV_UWRK_UWRK8_B0_UDB01_ACTL 0x40006491 +#define CYDEV_UWRK_UWRK8_B0_UDB02_ACTL 0x40006492 +#define CYDEV_UWRK_UWRK8_B0_UDB03_ACTL 0x40006493 +#define CYDEV_UWRK_UWRK8_B0_UDB04_ACTL 0x40006494 +#define CYDEV_UWRK_UWRK8_B0_UDB05_ACTL 0x40006495 +#define CYDEV_UWRK_UWRK8_B0_UDB06_ACTL 0x40006496 +#define CYDEV_UWRK_UWRK8_B0_UDB07_ACTL 0x40006497 +#define CYDEV_UWRK_UWRK8_B0_UDB08_ACTL 0x40006498 +#define CYDEV_UWRK_UWRK8_B0_UDB09_ACTL 0x40006499 +#define CYDEV_UWRK_UWRK8_B0_UDB10_ACTL 0x4000649a +#define CYDEV_UWRK_UWRK8_B0_UDB11_ACTL 0x4000649b +#define CYDEV_UWRK_UWRK8_B0_UDB12_ACTL 0x4000649c +#define CYDEV_UWRK_UWRK8_B0_UDB13_ACTL 0x4000649d +#define CYDEV_UWRK_UWRK8_B0_UDB14_ACTL 0x4000649e +#define CYDEV_UWRK_UWRK8_B0_UDB15_ACTL 0x4000649f +#define CYDEV_UWRK_UWRK8_B0_UDB00_MC 0x400064a0 +#define CYDEV_UWRK_UWRK8_B0_UDB01_MC 0x400064a1 +#define CYDEV_UWRK_UWRK8_B0_UDB02_MC 0x400064a2 +#define CYDEV_UWRK_UWRK8_B0_UDB03_MC 0x400064a3 +#define CYDEV_UWRK_UWRK8_B0_UDB04_MC 0x400064a4 +#define CYDEV_UWRK_UWRK8_B0_UDB05_MC 0x400064a5 +#define CYDEV_UWRK_UWRK8_B0_UDB06_MC 0x400064a6 +#define CYDEV_UWRK_UWRK8_B0_UDB07_MC 0x400064a7 +#define CYDEV_UWRK_UWRK8_B0_UDB08_MC 0x400064a8 +#define CYDEV_UWRK_UWRK8_B0_UDB09_MC 0x400064a9 +#define CYDEV_UWRK_UWRK8_B0_UDB10_MC 0x400064aa +#define CYDEV_UWRK_UWRK8_B0_UDB11_MC 0x400064ab +#define CYDEV_UWRK_UWRK8_B0_UDB12_MC 0x400064ac +#define CYDEV_UWRK_UWRK8_B0_UDB13_MC 0x400064ad +#define CYDEV_UWRK_UWRK8_B0_UDB14_MC 0x400064ae +#define CYDEV_UWRK_UWRK8_B0_UDB15_MC 0x400064af +#define CYDEV_UWRK_UWRK8_B1_BASE 0x40006500 +#define CYDEV_UWRK_UWRK8_B1_SIZE 0x000000b0 +#define CYDEV_UWRK_UWRK8_B1_UDB04_A0 0x40006504 +#define CYDEV_UWRK_UWRK8_B1_UDB05_A0 0x40006505 +#define CYDEV_UWRK_UWRK8_B1_UDB06_A0 0x40006506 +#define CYDEV_UWRK_UWRK8_B1_UDB07_A0 0x40006507 +#define CYDEV_UWRK_UWRK8_B1_UDB08_A0 0x40006508 +#define CYDEV_UWRK_UWRK8_B1_UDB09_A0 0x40006509 +#define CYDEV_UWRK_UWRK8_B1_UDB10_A0 0x4000650a +#define CYDEV_UWRK_UWRK8_B1_UDB11_A0 0x4000650b +#define CYDEV_UWRK_UWRK8_B1_UDB04_A1 0x40006514 +#define CYDEV_UWRK_UWRK8_B1_UDB05_A1 0x40006515 +#define CYDEV_UWRK_UWRK8_B1_UDB06_A1 0x40006516 +#define CYDEV_UWRK_UWRK8_B1_UDB07_A1 0x40006517 +#define CYDEV_UWRK_UWRK8_B1_UDB08_A1 0x40006518 +#define CYDEV_UWRK_UWRK8_B1_UDB09_A1 0x40006519 +#define CYDEV_UWRK_UWRK8_B1_UDB10_A1 0x4000651a +#define CYDEV_UWRK_UWRK8_B1_UDB11_A1 0x4000651b +#define CYDEV_UWRK_UWRK8_B1_UDB04_D0 0x40006524 +#define CYDEV_UWRK_UWRK8_B1_UDB05_D0 0x40006525 +#define CYDEV_UWRK_UWRK8_B1_UDB06_D0 0x40006526 +#define CYDEV_UWRK_UWRK8_B1_UDB07_D0 0x40006527 +#define CYDEV_UWRK_UWRK8_B1_UDB08_D0 0x40006528 +#define CYDEV_UWRK_UWRK8_B1_UDB09_D0 0x40006529 +#define CYDEV_UWRK_UWRK8_B1_UDB10_D0 0x4000652a +#define CYDEV_UWRK_UWRK8_B1_UDB11_D0 0x4000652b +#define CYDEV_UWRK_UWRK8_B1_UDB04_D1 0x40006534 +#define CYDEV_UWRK_UWRK8_B1_UDB05_D1 0x40006535 +#define CYDEV_UWRK_UWRK8_B1_UDB06_D1 0x40006536 +#define CYDEV_UWRK_UWRK8_B1_UDB07_D1 0x40006537 +#define CYDEV_UWRK_UWRK8_B1_UDB08_D1 0x40006538 +#define CYDEV_UWRK_UWRK8_B1_UDB09_D1 0x40006539 +#define CYDEV_UWRK_UWRK8_B1_UDB10_D1 0x4000653a +#define CYDEV_UWRK_UWRK8_B1_UDB11_D1 0x4000653b +#define CYDEV_UWRK_UWRK8_B1_UDB04_F0 0x40006544 +#define CYDEV_UWRK_UWRK8_B1_UDB05_F0 0x40006545 +#define CYDEV_UWRK_UWRK8_B1_UDB06_F0 0x40006546 +#define CYDEV_UWRK_UWRK8_B1_UDB07_F0 0x40006547 +#define CYDEV_UWRK_UWRK8_B1_UDB08_F0 0x40006548 +#define CYDEV_UWRK_UWRK8_B1_UDB09_F0 0x40006549 +#define CYDEV_UWRK_UWRK8_B1_UDB10_F0 0x4000654a +#define CYDEV_UWRK_UWRK8_B1_UDB11_F0 0x4000654b +#define CYDEV_UWRK_UWRK8_B1_UDB04_F1 0x40006554 +#define CYDEV_UWRK_UWRK8_B1_UDB05_F1 0x40006555 +#define CYDEV_UWRK_UWRK8_B1_UDB06_F1 0x40006556 +#define CYDEV_UWRK_UWRK8_B1_UDB07_F1 0x40006557 +#define CYDEV_UWRK_UWRK8_B1_UDB08_F1 0x40006558 +#define CYDEV_UWRK_UWRK8_B1_UDB09_F1 0x40006559 +#define CYDEV_UWRK_UWRK8_B1_UDB10_F1 0x4000655a +#define CYDEV_UWRK_UWRK8_B1_UDB11_F1 0x4000655b +#define CYDEV_UWRK_UWRK8_B1_UDB04_ST 0x40006564 +#define CYDEV_UWRK_UWRK8_B1_UDB05_ST 0x40006565 +#define CYDEV_UWRK_UWRK8_B1_UDB06_ST 0x40006566 +#define CYDEV_UWRK_UWRK8_B1_UDB07_ST 0x40006567 +#define CYDEV_UWRK_UWRK8_B1_UDB08_ST 0x40006568 +#define CYDEV_UWRK_UWRK8_B1_UDB09_ST 0x40006569 +#define CYDEV_UWRK_UWRK8_B1_UDB10_ST 0x4000656a +#define CYDEV_UWRK_UWRK8_B1_UDB11_ST 0x4000656b +#define CYDEV_UWRK_UWRK8_B1_UDB04_CTL 0x40006574 +#define CYDEV_UWRK_UWRK8_B1_UDB05_CTL 0x40006575 +#define CYDEV_UWRK_UWRK8_B1_UDB06_CTL 0x40006576 +#define CYDEV_UWRK_UWRK8_B1_UDB07_CTL 0x40006577 +#define CYDEV_UWRK_UWRK8_B1_UDB08_CTL 0x40006578 +#define CYDEV_UWRK_UWRK8_B1_UDB09_CTL 0x40006579 +#define CYDEV_UWRK_UWRK8_B1_UDB10_CTL 0x4000657a +#define CYDEV_UWRK_UWRK8_B1_UDB11_CTL 0x4000657b +#define CYDEV_UWRK_UWRK8_B1_UDB04_MSK 0x40006584 +#define CYDEV_UWRK_UWRK8_B1_UDB05_MSK 0x40006585 +#define CYDEV_UWRK_UWRK8_B1_UDB06_MSK 0x40006586 +#define CYDEV_UWRK_UWRK8_B1_UDB07_MSK 0x40006587 +#define CYDEV_UWRK_UWRK8_B1_UDB08_MSK 0x40006588 +#define CYDEV_UWRK_UWRK8_B1_UDB09_MSK 0x40006589 +#define CYDEV_UWRK_UWRK8_B1_UDB10_MSK 0x4000658a +#define CYDEV_UWRK_UWRK8_B1_UDB11_MSK 0x4000658b +#define CYDEV_UWRK_UWRK8_B1_UDB04_ACTL 0x40006594 +#define CYDEV_UWRK_UWRK8_B1_UDB05_ACTL 0x40006595 +#define CYDEV_UWRK_UWRK8_B1_UDB06_ACTL 0x40006596 +#define CYDEV_UWRK_UWRK8_B1_UDB07_ACTL 0x40006597 +#define CYDEV_UWRK_UWRK8_B1_UDB08_ACTL 0x40006598 +#define CYDEV_UWRK_UWRK8_B1_UDB09_ACTL 0x40006599 +#define CYDEV_UWRK_UWRK8_B1_UDB10_ACTL 0x4000659a +#define CYDEV_UWRK_UWRK8_B1_UDB11_ACTL 0x4000659b +#define CYDEV_UWRK_UWRK8_B1_UDB04_MC 0x400065a4 +#define CYDEV_UWRK_UWRK8_B1_UDB05_MC 0x400065a5 +#define CYDEV_UWRK_UWRK8_B1_UDB06_MC 0x400065a6 +#define CYDEV_UWRK_UWRK8_B1_UDB07_MC 0x400065a7 +#define CYDEV_UWRK_UWRK8_B1_UDB08_MC 0x400065a8 +#define CYDEV_UWRK_UWRK8_B1_UDB09_MC 0x400065a9 +#define CYDEV_UWRK_UWRK8_B1_UDB10_MC 0x400065aa +#define CYDEV_UWRK_UWRK8_B1_UDB11_MC 0x400065ab +#define CYDEV_UWRK_UWRK16_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_SIZE 0x00000760 +#define CYDEV_UWRK_UWRK16_CAT_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_CAT_SIZE 0x00000760 +#define CYDEV_UWRK_UWRK16_CAT_B0_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_CAT_B0_SIZE 0x00000160 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1 0x40006800 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1 0x40006802 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1 0x40006804 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1 0x40006806 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1 0x40006808 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1 0x4000680a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1 0x4000680c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1 0x4000680e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1 0x40006810 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1 0x40006812 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1 0x40006814 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1 0x40006816 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1 0x40006818 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1 0x4000681a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1 0x4000681c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1 0x4000681e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1 0x40006840 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1 0x40006842 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1 0x40006844 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1 0x40006846 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1 0x40006848 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1 0x4000684a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1 0x4000684c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1 0x4000684e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1 0x40006850 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1 0x40006852 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1 0x40006854 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1 0x40006856 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1 0x40006858 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1 0x4000685a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1 0x4000685c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1 0x4000685e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1 0x40006880 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1 0x40006882 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1 0x40006884 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1 0x40006886 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1 0x40006888 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1 0x4000688a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1 0x4000688c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1 0x4000688e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1 0x40006890 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1 0x40006892 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1 0x40006894 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1 0x40006896 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1 0x40006898 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1 0x4000689a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1 0x4000689c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1 0x4000689e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL 0x400068c0 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL 0x400068c2 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL 0x400068c4 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL 0x400068c6 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL 0x400068c8 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL 0x400068ca +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL 0x400068cc +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL 0x400068ce +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL 0x400068d0 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL 0x400068d2 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL 0x400068d4 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL 0x400068d6 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL 0x400068d8 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL 0x400068da +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL 0x400068dc +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL 0x400068de +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL 0x40006900 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL 0x40006902 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL 0x40006904 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL 0x40006906 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL 0x40006908 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL 0x4000690a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL 0x4000690c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL 0x4000690e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL 0x40006910 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL 0x40006912 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL 0x40006914 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL 0x40006916 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL 0x40006918 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL 0x4000691a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL 0x4000691c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL 0x4000691e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00 0x40006940 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00 0x40006942 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00 0x40006944 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00 0x40006946 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00 0x40006948 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00 0x4000694a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00 0x4000694c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00 0x4000694e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00 0x40006950 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00 0x40006952 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00 0x40006954 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00 0x40006956 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00 0x40006958 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00 0x4000695a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00 0x4000695c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00 0x4000695e +#define CYDEV_UWRK_UWRK16_CAT_B1_BASE 0x40006a00 +#define CYDEV_UWRK_UWRK16_CAT_B1_SIZE 0x00000160 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1 0x40006a08 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1 0x40006a0a +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1 0x40006a0c +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1 0x40006a0e +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1 0x40006a10 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1 0x40006a12 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1 0x40006a14 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1 0x40006a16 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1 0x40006a48 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1 0x40006a4a +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1 0x40006a4c +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1 0x40006a4e +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1 0x40006a50 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1 0x40006a52 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1 0x40006a54 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1 0x40006a56 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1 0x40006a88 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1 0x40006a8a +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1 0x40006a8c +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1 0x40006a8e +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1 0x40006a90 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1 0x40006a92 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1 0x40006a94 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1 0x40006a96 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL 0x40006ac8 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL 0x40006aca +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL 0x40006acc +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL 0x40006ace +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL 0x40006ad0 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL 0x40006ad2 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL 0x40006ad4 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL 0x40006ad6 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL 0x40006b08 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL 0x40006b0a +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL 0x40006b0c +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL 0x40006b0e +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL 0x40006b10 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL 0x40006b12 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL 0x40006b14 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL 0x40006b16 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00 0x40006b48 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00 0x40006b4a +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00 0x40006b4c +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00 0x40006b4e +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00 0x40006b50 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00 0x40006b52 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00 0x40006b54 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00 0x40006b56 +#define CYDEV_UWRK_UWRK16_DEF_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_DEF_SIZE 0x0000075e +#define CYDEV_UWRK_UWRK16_DEF_B0_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_DEF_B0_SIZE 0x0000015e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0 0x40006800 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0 0x40006802 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0 0x40006804 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0 0x40006806 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0 0x40006808 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0 0x4000680a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0 0x4000680c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0 0x4000680e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0 0x40006810 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0 0x40006812 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0 0x40006814 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0 0x40006816 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0 0x40006818 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0 0x4000681a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0 0x4000681c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1 0x40006820 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1 0x40006822 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1 0x40006824 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1 0x40006826 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1 0x40006828 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1 0x4000682a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1 0x4000682c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1 0x4000682e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1 0x40006830 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1 0x40006832 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1 0x40006834 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1 0x40006836 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1 0x40006838 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1 0x4000683a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1 0x4000683c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0 0x40006840 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0 0x40006842 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0 0x40006844 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0 0x40006846 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0 0x40006848 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0 0x4000684a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0 0x4000684c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0 0x4000684e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0 0x40006850 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0 0x40006852 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0 0x40006854 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0 0x40006856 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0 0x40006858 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0 0x4000685a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0 0x4000685c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1 0x40006860 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1 0x40006862 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1 0x40006864 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1 0x40006866 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1 0x40006868 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1 0x4000686a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1 0x4000686c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1 0x4000686e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1 0x40006870 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1 0x40006872 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1 0x40006874 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1 0x40006876 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1 0x40006878 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1 0x4000687a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1 0x4000687c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0 0x40006880 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0 0x40006882 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0 0x40006884 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0 0x40006886 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0 0x40006888 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0 0x4000688a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0 0x4000688c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0 0x4000688e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0 0x40006890 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0 0x40006892 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0 0x40006894 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0 0x40006896 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0 0x40006898 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0 0x4000689a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0 0x4000689c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1 0x400068a0 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1 0x400068a2 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1 0x400068a4 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1 0x400068a6 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1 0x400068a8 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1 0x400068aa +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1 0x400068ac +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1 0x400068ae +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1 0x400068b0 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1 0x400068b2 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1 0x400068b4 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1 0x400068b6 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1 0x400068b8 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1 0x400068ba +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1 0x400068bc +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST 0x400068c0 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST 0x400068c2 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST 0x400068c4 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST 0x400068c6 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST 0x400068c8 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST 0x400068ca +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST 0x400068cc +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST 0x400068ce +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST 0x400068d0 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST 0x400068d2 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST 0x400068d4 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST 0x400068d6 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST 0x400068d8 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST 0x400068da +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST 0x400068dc +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL 0x400068e0 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL 0x400068e2 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL 0x400068e4 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL 0x400068e6 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL 0x400068e8 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL 0x400068ea +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL 0x400068ec +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL 0x400068ee +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL 0x400068f0 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL 0x400068f2 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL 0x400068f4 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL 0x400068f6 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL 0x400068f8 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL 0x400068fa +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL 0x400068fc +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK 0x40006900 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK 0x40006902 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK 0x40006904 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK 0x40006906 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK 0x40006908 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK 0x4000690a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK 0x4000690c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK 0x4000690e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK 0x40006910 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK 0x40006912 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK 0x40006914 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK 0x40006916 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK 0x40006918 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK 0x4000691a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK 0x4000691c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL 0x40006920 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL 0x40006922 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL 0x40006924 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL 0x40006926 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL 0x40006928 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL 0x4000692a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL 0x4000692c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL 0x4000692e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL 0x40006930 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL 0x40006932 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL 0x40006934 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL 0x40006936 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL 0x40006938 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL 0x4000693a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL 0x4000693c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC 0x40006940 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC 0x40006942 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC 0x40006944 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC 0x40006946 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC 0x40006948 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC 0x4000694a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC 0x4000694c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC 0x4000694e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC 0x40006950 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC 0x40006952 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC 0x40006954 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC 0x40006956 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC 0x40006958 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC 0x4000695a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC 0x4000695c +#define CYDEV_UWRK_UWRK16_DEF_B1_BASE 0x40006a00 +#define CYDEV_UWRK_UWRK16_DEF_B1_SIZE 0x0000015e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0 0x40006a08 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0 0x40006a0a +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0 0x40006a0c +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0 0x40006a0e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0 0x40006a10 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0 0x40006a12 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0 0x40006a14 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0 0x40006a16 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1 0x40006a28 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1 0x40006a2a +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1 0x40006a2c +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1 0x40006a2e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1 0x40006a30 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1 0x40006a32 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1 0x40006a34 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1 0x40006a36 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0 0x40006a48 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0 0x40006a4a +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0 0x40006a4c +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0 0x40006a4e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0 0x40006a50 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0 0x40006a52 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0 0x40006a54 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0 0x40006a56 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1 0x40006a68 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1 0x40006a6a +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1 0x40006a6c +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1 0x40006a6e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1 0x40006a70 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1 0x40006a72 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1 0x40006a74 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1 0x40006a76 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0 0x40006a88 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0 0x40006a8a +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0 0x40006a8c +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0 0x40006a8e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0 0x40006a90 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0 0x40006a92 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0 0x40006a94 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0 0x40006a96 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1 0x40006aa8 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1 0x40006aaa +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1 0x40006aac +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1 0x40006aae +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1 0x40006ab0 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1 0x40006ab2 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1 0x40006ab4 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1 0x40006ab6 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST 0x40006ac8 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST 0x40006aca +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST 0x40006acc +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST 0x40006ace +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST 0x40006ad0 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST 0x40006ad2 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST 0x40006ad4 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST 0x40006ad6 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL 0x40006ae8 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL 0x40006aea +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL 0x40006aec +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL 0x40006aee +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL 0x40006af0 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL 0x40006af2 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL 0x40006af4 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL 0x40006af6 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK 0x40006b08 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK 0x40006b0a +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK 0x40006b0c +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK 0x40006b0e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK 0x40006b10 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK 0x40006b12 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK 0x40006b14 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK 0x40006b16 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL 0x40006b28 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL 0x40006b2a +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL 0x40006b2c +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL 0x40006b2e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL 0x40006b30 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL 0x40006b32 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL 0x40006b34 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL 0x40006b36 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC 0x40006b48 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC 0x40006b4a +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC 0x40006b4c +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC 0x40006b4e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC 0x40006b50 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC 0x40006b52 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC 0x40006b54 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC 0x40006b56 +#define CYDEV_PHUB_BASE 0x40007000 +#define CYDEV_PHUB_SIZE 0x00000c00 +#define CYDEV_PHUB_CFG 0x40007000 +#define CYDEV_PHUB_ERR 0x40007004 +#define CYDEV_PHUB_ERR_ADR 0x40007008 +#define CYDEV_PHUB_CH0_BASE 0x40007010 +#define CYDEV_PHUB_CH0_SIZE 0x0000000c +#define CYDEV_PHUB_CH0_BASIC_CFG 0x40007010 +#define CYDEV_PHUB_CH0_ACTION 0x40007014 +#define CYDEV_PHUB_CH0_BASIC_STATUS 0x40007018 +#define CYDEV_PHUB_CH1_BASE 0x40007020 +#define CYDEV_PHUB_CH1_SIZE 0x0000000c +#define CYDEV_PHUB_CH1_BASIC_CFG 0x40007020 +#define CYDEV_PHUB_CH1_ACTION 0x40007024 +#define CYDEV_PHUB_CH1_BASIC_STATUS 0x40007028 +#define CYDEV_PHUB_CH2_BASE 0x40007030 +#define CYDEV_PHUB_CH2_SIZE 0x0000000c +#define CYDEV_PHUB_CH2_BASIC_CFG 0x40007030 +#define CYDEV_PHUB_CH2_ACTION 0x40007034 +#define CYDEV_PHUB_CH2_BASIC_STATUS 0x40007038 +#define CYDEV_PHUB_CH3_BASE 0x40007040 +#define CYDEV_PHUB_CH3_SIZE 0x0000000c +#define CYDEV_PHUB_CH3_BASIC_CFG 0x40007040 +#define CYDEV_PHUB_CH3_ACTION 0x40007044 +#define CYDEV_PHUB_CH3_BASIC_STATUS 0x40007048 +#define CYDEV_PHUB_CH4_BASE 0x40007050 +#define CYDEV_PHUB_CH4_SIZE 0x0000000c +#define CYDEV_PHUB_CH4_BASIC_CFG 0x40007050 +#define CYDEV_PHUB_CH4_ACTION 0x40007054 +#define CYDEV_PHUB_CH4_BASIC_STATUS 0x40007058 +#define CYDEV_PHUB_CH5_BASE 0x40007060 +#define CYDEV_PHUB_CH5_SIZE 0x0000000c +#define CYDEV_PHUB_CH5_BASIC_CFG 0x40007060 +#define CYDEV_PHUB_CH5_ACTION 0x40007064 +#define CYDEV_PHUB_CH5_BASIC_STATUS 0x40007068 +#define CYDEV_PHUB_CH6_BASE 0x40007070 +#define CYDEV_PHUB_CH6_SIZE 0x0000000c +#define CYDEV_PHUB_CH6_BASIC_CFG 0x40007070 +#define CYDEV_PHUB_CH6_ACTION 0x40007074 +#define CYDEV_PHUB_CH6_BASIC_STATUS 0x40007078 +#define CYDEV_PHUB_CH7_BASE 0x40007080 +#define CYDEV_PHUB_CH7_SIZE 0x0000000c +#define CYDEV_PHUB_CH7_BASIC_CFG 0x40007080 +#define CYDEV_PHUB_CH7_ACTION 0x40007084 +#define CYDEV_PHUB_CH7_BASIC_STATUS 0x40007088 +#define CYDEV_PHUB_CH8_BASE 0x40007090 +#define CYDEV_PHUB_CH8_SIZE 0x0000000c +#define CYDEV_PHUB_CH8_BASIC_CFG 0x40007090 +#define CYDEV_PHUB_CH8_ACTION 0x40007094 +#define CYDEV_PHUB_CH8_BASIC_STATUS 0x40007098 +#define CYDEV_PHUB_CH9_BASE 0x400070a0 +#define CYDEV_PHUB_CH9_SIZE 0x0000000c +#define CYDEV_PHUB_CH9_BASIC_CFG 0x400070a0 +#define CYDEV_PHUB_CH9_ACTION 0x400070a4 +#define CYDEV_PHUB_CH9_BASIC_STATUS 0x400070a8 +#define CYDEV_PHUB_CH10_BASE 0x400070b0 +#define CYDEV_PHUB_CH10_SIZE 0x0000000c +#define CYDEV_PHUB_CH10_BASIC_CFG 0x400070b0 +#define CYDEV_PHUB_CH10_ACTION 0x400070b4 +#define CYDEV_PHUB_CH10_BASIC_STATUS 0x400070b8 +#define CYDEV_PHUB_CH11_BASE 0x400070c0 +#define CYDEV_PHUB_CH11_SIZE 0x0000000c +#define CYDEV_PHUB_CH11_BASIC_CFG 0x400070c0 +#define CYDEV_PHUB_CH11_ACTION 0x400070c4 +#define CYDEV_PHUB_CH11_BASIC_STATUS 0x400070c8 +#define CYDEV_PHUB_CH12_BASE 0x400070d0 +#define CYDEV_PHUB_CH12_SIZE 0x0000000c +#define CYDEV_PHUB_CH12_BASIC_CFG 0x400070d0 +#define CYDEV_PHUB_CH12_ACTION 0x400070d4 +#define CYDEV_PHUB_CH12_BASIC_STATUS 0x400070d8 +#define CYDEV_PHUB_CH13_BASE 0x400070e0 +#define CYDEV_PHUB_CH13_SIZE 0x0000000c +#define CYDEV_PHUB_CH13_BASIC_CFG 0x400070e0 +#define CYDEV_PHUB_CH13_ACTION 0x400070e4 +#define CYDEV_PHUB_CH13_BASIC_STATUS 0x400070e8 +#define CYDEV_PHUB_CH14_BASE 0x400070f0 +#define CYDEV_PHUB_CH14_SIZE 0x0000000c +#define CYDEV_PHUB_CH14_BASIC_CFG 0x400070f0 +#define CYDEV_PHUB_CH14_ACTION 0x400070f4 +#define CYDEV_PHUB_CH14_BASIC_STATUS 0x400070f8 +#define CYDEV_PHUB_CH15_BASE 0x40007100 +#define CYDEV_PHUB_CH15_SIZE 0x0000000c +#define CYDEV_PHUB_CH15_BASIC_CFG 0x40007100 +#define CYDEV_PHUB_CH15_ACTION 0x40007104 +#define CYDEV_PHUB_CH15_BASIC_STATUS 0x40007108 +#define CYDEV_PHUB_CH16_BASE 0x40007110 +#define CYDEV_PHUB_CH16_SIZE 0x0000000c +#define CYDEV_PHUB_CH16_BASIC_CFG 0x40007110 +#define CYDEV_PHUB_CH16_ACTION 0x40007114 +#define CYDEV_PHUB_CH16_BASIC_STATUS 0x40007118 +#define CYDEV_PHUB_CH17_BASE 0x40007120 +#define CYDEV_PHUB_CH17_SIZE 0x0000000c +#define CYDEV_PHUB_CH17_BASIC_CFG 0x40007120 +#define CYDEV_PHUB_CH17_ACTION 0x40007124 +#define CYDEV_PHUB_CH17_BASIC_STATUS 0x40007128 +#define CYDEV_PHUB_CH18_BASE 0x40007130 +#define CYDEV_PHUB_CH18_SIZE 0x0000000c +#define CYDEV_PHUB_CH18_BASIC_CFG 0x40007130 +#define CYDEV_PHUB_CH18_ACTION 0x40007134 +#define CYDEV_PHUB_CH18_BASIC_STATUS 0x40007138 +#define CYDEV_PHUB_CH19_BASE 0x40007140 +#define CYDEV_PHUB_CH19_SIZE 0x0000000c +#define CYDEV_PHUB_CH19_BASIC_CFG 0x40007140 +#define CYDEV_PHUB_CH19_ACTION 0x40007144 +#define CYDEV_PHUB_CH19_BASIC_STATUS 0x40007148 +#define CYDEV_PHUB_CH20_BASE 0x40007150 +#define CYDEV_PHUB_CH20_SIZE 0x0000000c +#define CYDEV_PHUB_CH20_BASIC_CFG 0x40007150 +#define CYDEV_PHUB_CH20_ACTION 0x40007154 +#define CYDEV_PHUB_CH20_BASIC_STATUS 0x40007158 +#define CYDEV_PHUB_CH21_BASE 0x40007160 +#define CYDEV_PHUB_CH21_SIZE 0x0000000c +#define CYDEV_PHUB_CH21_BASIC_CFG 0x40007160 +#define CYDEV_PHUB_CH21_ACTION 0x40007164 +#define CYDEV_PHUB_CH21_BASIC_STATUS 0x40007168 +#define CYDEV_PHUB_CH22_BASE 0x40007170 +#define CYDEV_PHUB_CH22_SIZE 0x0000000c +#define CYDEV_PHUB_CH22_BASIC_CFG 0x40007170 +#define CYDEV_PHUB_CH22_ACTION 0x40007174 +#define CYDEV_PHUB_CH22_BASIC_STATUS 0x40007178 +#define CYDEV_PHUB_CH23_BASE 0x40007180 +#define CYDEV_PHUB_CH23_SIZE 0x0000000c +#define CYDEV_PHUB_CH23_BASIC_CFG 0x40007180 +#define CYDEV_PHUB_CH23_ACTION 0x40007184 +#define CYDEV_PHUB_CH23_BASIC_STATUS 0x40007188 +#define CYDEV_PHUB_CFGMEM0_BASE 0x40007600 +#define CYDEV_PHUB_CFGMEM0_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM0_CFG0 0x40007600 +#define CYDEV_PHUB_CFGMEM0_CFG1 0x40007604 +#define CYDEV_PHUB_CFGMEM1_BASE 0x40007608 +#define CYDEV_PHUB_CFGMEM1_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM1_CFG0 0x40007608 +#define CYDEV_PHUB_CFGMEM1_CFG1 0x4000760c +#define CYDEV_PHUB_CFGMEM2_BASE 0x40007610 +#define CYDEV_PHUB_CFGMEM2_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM2_CFG0 0x40007610 +#define CYDEV_PHUB_CFGMEM2_CFG1 0x40007614 +#define CYDEV_PHUB_CFGMEM3_BASE 0x40007618 +#define CYDEV_PHUB_CFGMEM3_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM3_CFG0 0x40007618 +#define CYDEV_PHUB_CFGMEM3_CFG1 0x4000761c +#define CYDEV_PHUB_CFGMEM4_BASE 0x40007620 +#define CYDEV_PHUB_CFGMEM4_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM4_CFG0 0x40007620 +#define CYDEV_PHUB_CFGMEM4_CFG1 0x40007624 +#define CYDEV_PHUB_CFGMEM5_BASE 0x40007628 +#define CYDEV_PHUB_CFGMEM5_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM5_CFG0 0x40007628 +#define CYDEV_PHUB_CFGMEM5_CFG1 0x4000762c +#define CYDEV_PHUB_CFGMEM6_BASE 0x40007630 +#define CYDEV_PHUB_CFGMEM6_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM6_CFG0 0x40007630 +#define CYDEV_PHUB_CFGMEM6_CFG1 0x40007634 +#define CYDEV_PHUB_CFGMEM7_BASE 0x40007638 +#define CYDEV_PHUB_CFGMEM7_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM7_CFG0 0x40007638 +#define CYDEV_PHUB_CFGMEM7_CFG1 0x4000763c +#define CYDEV_PHUB_CFGMEM8_BASE 0x40007640 +#define CYDEV_PHUB_CFGMEM8_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM8_CFG0 0x40007640 +#define CYDEV_PHUB_CFGMEM8_CFG1 0x40007644 +#define CYDEV_PHUB_CFGMEM9_BASE 0x40007648 +#define CYDEV_PHUB_CFGMEM9_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM9_CFG0 0x40007648 +#define CYDEV_PHUB_CFGMEM9_CFG1 0x4000764c +#define CYDEV_PHUB_CFGMEM10_BASE 0x40007650 +#define CYDEV_PHUB_CFGMEM10_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM10_CFG0 0x40007650 +#define CYDEV_PHUB_CFGMEM10_CFG1 0x40007654 +#define CYDEV_PHUB_CFGMEM11_BASE 0x40007658 +#define CYDEV_PHUB_CFGMEM11_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM11_CFG0 0x40007658 +#define CYDEV_PHUB_CFGMEM11_CFG1 0x4000765c +#define CYDEV_PHUB_CFGMEM12_BASE 0x40007660 +#define CYDEV_PHUB_CFGMEM12_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM12_CFG0 0x40007660 +#define CYDEV_PHUB_CFGMEM12_CFG1 0x40007664 +#define CYDEV_PHUB_CFGMEM13_BASE 0x40007668 +#define CYDEV_PHUB_CFGMEM13_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM13_CFG0 0x40007668 +#define CYDEV_PHUB_CFGMEM13_CFG1 0x4000766c +#define CYDEV_PHUB_CFGMEM14_BASE 0x40007670 +#define CYDEV_PHUB_CFGMEM14_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM14_CFG0 0x40007670 +#define CYDEV_PHUB_CFGMEM14_CFG1 0x40007674 +#define CYDEV_PHUB_CFGMEM15_BASE 0x40007678 +#define CYDEV_PHUB_CFGMEM15_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM15_CFG0 0x40007678 +#define CYDEV_PHUB_CFGMEM15_CFG1 0x4000767c +#define CYDEV_PHUB_CFGMEM16_BASE 0x40007680 +#define CYDEV_PHUB_CFGMEM16_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM16_CFG0 0x40007680 +#define CYDEV_PHUB_CFGMEM16_CFG1 0x40007684 +#define CYDEV_PHUB_CFGMEM17_BASE 0x40007688 +#define CYDEV_PHUB_CFGMEM17_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM17_CFG0 0x40007688 +#define CYDEV_PHUB_CFGMEM17_CFG1 0x4000768c +#define CYDEV_PHUB_CFGMEM18_BASE 0x40007690 +#define CYDEV_PHUB_CFGMEM18_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM18_CFG0 0x40007690 +#define CYDEV_PHUB_CFGMEM18_CFG1 0x40007694 +#define CYDEV_PHUB_CFGMEM19_BASE 0x40007698 +#define CYDEV_PHUB_CFGMEM19_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM19_CFG0 0x40007698 +#define CYDEV_PHUB_CFGMEM19_CFG1 0x4000769c +#define CYDEV_PHUB_CFGMEM20_BASE 0x400076a0 +#define CYDEV_PHUB_CFGMEM20_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM20_CFG0 0x400076a0 +#define CYDEV_PHUB_CFGMEM20_CFG1 0x400076a4 +#define CYDEV_PHUB_CFGMEM21_BASE 0x400076a8 +#define CYDEV_PHUB_CFGMEM21_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM21_CFG0 0x400076a8 +#define CYDEV_PHUB_CFGMEM21_CFG1 0x400076ac +#define CYDEV_PHUB_CFGMEM22_BASE 0x400076b0 +#define CYDEV_PHUB_CFGMEM22_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM22_CFG0 0x400076b0 +#define CYDEV_PHUB_CFGMEM22_CFG1 0x400076b4 +#define CYDEV_PHUB_CFGMEM23_BASE 0x400076b8 +#define CYDEV_PHUB_CFGMEM23_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM23_CFG0 0x400076b8 +#define CYDEV_PHUB_CFGMEM23_CFG1 0x400076bc +#define CYDEV_PHUB_TDMEM0_BASE 0x40007800 +#define CYDEV_PHUB_TDMEM0_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM0_ORIG_TD0 0x40007800 +#define CYDEV_PHUB_TDMEM0_ORIG_TD1 0x40007804 +#define CYDEV_PHUB_TDMEM1_BASE 0x40007808 +#define CYDEV_PHUB_TDMEM1_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM1_ORIG_TD0 0x40007808 +#define CYDEV_PHUB_TDMEM1_ORIG_TD1 0x4000780c +#define CYDEV_PHUB_TDMEM2_BASE 0x40007810 +#define CYDEV_PHUB_TDMEM2_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM2_ORIG_TD0 0x40007810 +#define CYDEV_PHUB_TDMEM2_ORIG_TD1 0x40007814 +#define CYDEV_PHUB_TDMEM3_BASE 0x40007818 +#define CYDEV_PHUB_TDMEM3_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM3_ORIG_TD0 0x40007818 +#define CYDEV_PHUB_TDMEM3_ORIG_TD1 0x4000781c +#define CYDEV_PHUB_TDMEM4_BASE 0x40007820 +#define CYDEV_PHUB_TDMEM4_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM4_ORIG_TD0 0x40007820 +#define CYDEV_PHUB_TDMEM4_ORIG_TD1 0x40007824 +#define CYDEV_PHUB_TDMEM5_BASE 0x40007828 +#define CYDEV_PHUB_TDMEM5_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM5_ORIG_TD0 0x40007828 +#define CYDEV_PHUB_TDMEM5_ORIG_TD1 0x4000782c +#define CYDEV_PHUB_TDMEM6_BASE 0x40007830 +#define CYDEV_PHUB_TDMEM6_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM6_ORIG_TD0 0x40007830 +#define CYDEV_PHUB_TDMEM6_ORIG_TD1 0x40007834 +#define CYDEV_PHUB_TDMEM7_BASE 0x40007838 +#define CYDEV_PHUB_TDMEM7_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM7_ORIG_TD0 0x40007838 +#define CYDEV_PHUB_TDMEM7_ORIG_TD1 0x4000783c +#define CYDEV_PHUB_TDMEM8_BASE 0x40007840 +#define CYDEV_PHUB_TDMEM8_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM8_ORIG_TD0 0x40007840 +#define CYDEV_PHUB_TDMEM8_ORIG_TD1 0x40007844 +#define CYDEV_PHUB_TDMEM9_BASE 0x40007848 +#define CYDEV_PHUB_TDMEM9_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM9_ORIG_TD0 0x40007848 +#define CYDEV_PHUB_TDMEM9_ORIG_TD1 0x4000784c +#define CYDEV_PHUB_TDMEM10_BASE 0x40007850 +#define CYDEV_PHUB_TDMEM10_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM10_ORIG_TD0 0x40007850 +#define CYDEV_PHUB_TDMEM10_ORIG_TD1 0x40007854 +#define CYDEV_PHUB_TDMEM11_BASE 0x40007858 +#define CYDEV_PHUB_TDMEM11_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM11_ORIG_TD0 0x40007858 +#define CYDEV_PHUB_TDMEM11_ORIG_TD1 0x4000785c +#define CYDEV_PHUB_TDMEM12_BASE 0x40007860 +#define CYDEV_PHUB_TDMEM12_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM12_ORIG_TD0 0x40007860 +#define CYDEV_PHUB_TDMEM12_ORIG_TD1 0x40007864 +#define CYDEV_PHUB_TDMEM13_BASE 0x40007868 +#define CYDEV_PHUB_TDMEM13_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM13_ORIG_TD0 0x40007868 +#define CYDEV_PHUB_TDMEM13_ORIG_TD1 0x4000786c +#define CYDEV_PHUB_TDMEM14_BASE 0x40007870 +#define CYDEV_PHUB_TDMEM14_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM14_ORIG_TD0 0x40007870 +#define CYDEV_PHUB_TDMEM14_ORIG_TD1 0x40007874 +#define CYDEV_PHUB_TDMEM15_BASE 0x40007878 +#define CYDEV_PHUB_TDMEM15_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM15_ORIG_TD0 0x40007878 +#define CYDEV_PHUB_TDMEM15_ORIG_TD1 0x4000787c +#define CYDEV_PHUB_TDMEM16_BASE 0x40007880 +#define CYDEV_PHUB_TDMEM16_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM16_ORIG_TD0 0x40007880 +#define CYDEV_PHUB_TDMEM16_ORIG_TD1 0x40007884 +#define CYDEV_PHUB_TDMEM17_BASE 0x40007888 +#define CYDEV_PHUB_TDMEM17_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM17_ORIG_TD0 0x40007888 +#define CYDEV_PHUB_TDMEM17_ORIG_TD1 0x4000788c +#define CYDEV_PHUB_TDMEM18_BASE 0x40007890 +#define CYDEV_PHUB_TDMEM18_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM18_ORIG_TD0 0x40007890 +#define CYDEV_PHUB_TDMEM18_ORIG_TD1 0x40007894 +#define CYDEV_PHUB_TDMEM19_BASE 0x40007898 +#define CYDEV_PHUB_TDMEM19_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM19_ORIG_TD0 0x40007898 +#define CYDEV_PHUB_TDMEM19_ORIG_TD1 0x4000789c +#define CYDEV_PHUB_TDMEM20_BASE 0x400078a0 +#define CYDEV_PHUB_TDMEM20_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM20_ORIG_TD0 0x400078a0 +#define CYDEV_PHUB_TDMEM20_ORIG_TD1 0x400078a4 +#define CYDEV_PHUB_TDMEM21_BASE 0x400078a8 +#define CYDEV_PHUB_TDMEM21_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM21_ORIG_TD0 0x400078a8 +#define CYDEV_PHUB_TDMEM21_ORIG_TD1 0x400078ac +#define CYDEV_PHUB_TDMEM22_BASE 0x400078b0 +#define CYDEV_PHUB_TDMEM22_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM22_ORIG_TD0 0x400078b0 +#define CYDEV_PHUB_TDMEM22_ORIG_TD1 0x400078b4 +#define CYDEV_PHUB_TDMEM23_BASE 0x400078b8 +#define CYDEV_PHUB_TDMEM23_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM23_ORIG_TD0 0x400078b8 +#define CYDEV_PHUB_TDMEM23_ORIG_TD1 0x400078bc +#define CYDEV_PHUB_TDMEM24_BASE 0x400078c0 +#define CYDEV_PHUB_TDMEM24_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM24_ORIG_TD0 0x400078c0 +#define CYDEV_PHUB_TDMEM24_ORIG_TD1 0x400078c4 +#define CYDEV_PHUB_TDMEM25_BASE 0x400078c8 +#define CYDEV_PHUB_TDMEM25_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM25_ORIG_TD0 0x400078c8 +#define CYDEV_PHUB_TDMEM25_ORIG_TD1 0x400078cc +#define CYDEV_PHUB_TDMEM26_BASE 0x400078d0 +#define CYDEV_PHUB_TDMEM26_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM26_ORIG_TD0 0x400078d0 +#define CYDEV_PHUB_TDMEM26_ORIG_TD1 0x400078d4 +#define CYDEV_PHUB_TDMEM27_BASE 0x400078d8 +#define CYDEV_PHUB_TDMEM27_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM27_ORIG_TD0 0x400078d8 +#define CYDEV_PHUB_TDMEM27_ORIG_TD1 0x400078dc +#define CYDEV_PHUB_TDMEM28_BASE 0x400078e0 +#define CYDEV_PHUB_TDMEM28_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM28_ORIG_TD0 0x400078e0 +#define CYDEV_PHUB_TDMEM28_ORIG_TD1 0x400078e4 +#define CYDEV_PHUB_TDMEM29_BASE 0x400078e8 +#define CYDEV_PHUB_TDMEM29_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM29_ORIG_TD0 0x400078e8 +#define CYDEV_PHUB_TDMEM29_ORIG_TD1 0x400078ec +#define CYDEV_PHUB_TDMEM30_BASE 0x400078f0 +#define CYDEV_PHUB_TDMEM30_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM30_ORIG_TD0 0x400078f0 +#define CYDEV_PHUB_TDMEM30_ORIG_TD1 0x400078f4 +#define CYDEV_PHUB_TDMEM31_BASE 0x400078f8 +#define CYDEV_PHUB_TDMEM31_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM31_ORIG_TD0 0x400078f8 +#define CYDEV_PHUB_TDMEM31_ORIG_TD1 0x400078fc +#define CYDEV_PHUB_TDMEM32_BASE 0x40007900 +#define CYDEV_PHUB_TDMEM32_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM32_ORIG_TD0 0x40007900 +#define CYDEV_PHUB_TDMEM32_ORIG_TD1 0x40007904 +#define CYDEV_PHUB_TDMEM33_BASE 0x40007908 +#define CYDEV_PHUB_TDMEM33_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM33_ORIG_TD0 0x40007908 +#define CYDEV_PHUB_TDMEM33_ORIG_TD1 0x4000790c +#define CYDEV_PHUB_TDMEM34_BASE 0x40007910 +#define CYDEV_PHUB_TDMEM34_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM34_ORIG_TD0 0x40007910 +#define CYDEV_PHUB_TDMEM34_ORIG_TD1 0x40007914 +#define CYDEV_PHUB_TDMEM35_BASE 0x40007918 +#define CYDEV_PHUB_TDMEM35_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM35_ORIG_TD0 0x40007918 +#define CYDEV_PHUB_TDMEM35_ORIG_TD1 0x4000791c +#define CYDEV_PHUB_TDMEM36_BASE 0x40007920 +#define CYDEV_PHUB_TDMEM36_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM36_ORIG_TD0 0x40007920 +#define CYDEV_PHUB_TDMEM36_ORIG_TD1 0x40007924 +#define CYDEV_PHUB_TDMEM37_BASE 0x40007928 +#define CYDEV_PHUB_TDMEM37_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM37_ORIG_TD0 0x40007928 +#define CYDEV_PHUB_TDMEM37_ORIG_TD1 0x4000792c +#define CYDEV_PHUB_TDMEM38_BASE 0x40007930 +#define CYDEV_PHUB_TDMEM38_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM38_ORIG_TD0 0x40007930 +#define CYDEV_PHUB_TDMEM38_ORIG_TD1 0x40007934 +#define CYDEV_PHUB_TDMEM39_BASE 0x40007938 +#define CYDEV_PHUB_TDMEM39_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM39_ORIG_TD0 0x40007938 +#define CYDEV_PHUB_TDMEM39_ORIG_TD1 0x4000793c +#define CYDEV_PHUB_TDMEM40_BASE 0x40007940 +#define CYDEV_PHUB_TDMEM40_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM40_ORIG_TD0 0x40007940 +#define CYDEV_PHUB_TDMEM40_ORIG_TD1 0x40007944 +#define CYDEV_PHUB_TDMEM41_BASE 0x40007948 +#define CYDEV_PHUB_TDMEM41_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM41_ORIG_TD0 0x40007948 +#define CYDEV_PHUB_TDMEM41_ORIG_TD1 0x4000794c +#define CYDEV_PHUB_TDMEM42_BASE 0x40007950 +#define CYDEV_PHUB_TDMEM42_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM42_ORIG_TD0 0x40007950 +#define CYDEV_PHUB_TDMEM42_ORIG_TD1 0x40007954 +#define CYDEV_PHUB_TDMEM43_BASE 0x40007958 +#define CYDEV_PHUB_TDMEM43_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM43_ORIG_TD0 0x40007958 +#define CYDEV_PHUB_TDMEM43_ORIG_TD1 0x4000795c +#define CYDEV_PHUB_TDMEM44_BASE 0x40007960 +#define CYDEV_PHUB_TDMEM44_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM44_ORIG_TD0 0x40007960 +#define CYDEV_PHUB_TDMEM44_ORIG_TD1 0x40007964 +#define CYDEV_PHUB_TDMEM45_BASE 0x40007968 +#define CYDEV_PHUB_TDMEM45_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM45_ORIG_TD0 0x40007968 +#define CYDEV_PHUB_TDMEM45_ORIG_TD1 0x4000796c +#define CYDEV_PHUB_TDMEM46_BASE 0x40007970 +#define CYDEV_PHUB_TDMEM46_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM46_ORIG_TD0 0x40007970 +#define CYDEV_PHUB_TDMEM46_ORIG_TD1 0x40007974 +#define CYDEV_PHUB_TDMEM47_BASE 0x40007978 +#define CYDEV_PHUB_TDMEM47_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM47_ORIG_TD0 0x40007978 +#define CYDEV_PHUB_TDMEM47_ORIG_TD1 0x4000797c +#define CYDEV_PHUB_TDMEM48_BASE 0x40007980 +#define CYDEV_PHUB_TDMEM48_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM48_ORIG_TD0 0x40007980 +#define CYDEV_PHUB_TDMEM48_ORIG_TD1 0x40007984 +#define CYDEV_PHUB_TDMEM49_BASE 0x40007988 +#define CYDEV_PHUB_TDMEM49_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM49_ORIG_TD0 0x40007988 +#define CYDEV_PHUB_TDMEM49_ORIG_TD1 0x4000798c +#define CYDEV_PHUB_TDMEM50_BASE 0x40007990 +#define CYDEV_PHUB_TDMEM50_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM50_ORIG_TD0 0x40007990 +#define CYDEV_PHUB_TDMEM50_ORIG_TD1 0x40007994 +#define CYDEV_PHUB_TDMEM51_BASE 0x40007998 +#define CYDEV_PHUB_TDMEM51_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM51_ORIG_TD0 0x40007998 +#define CYDEV_PHUB_TDMEM51_ORIG_TD1 0x4000799c +#define CYDEV_PHUB_TDMEM52_BASE 0x400079a0 +#define CYDEV_PHUB_TDMEM52_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM52_ORIG_TD0 0x400079a0 +#define CYDEV_PHUB_TDMEM52_ORIG_TD1 0x400079a4 +#define CYDEV_PHUB_TDMEM53_BASE 0x400079a8 +#define CYDEV_PHUB_TDMEM53_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM53_ORIG_TD0 0x400079a8 +#define CYDEV_PHUB_TDMEM53_ORIG_TD1 0x400079ac +#define CYDEV_PHUB_TDMEM54_BASE 0x400079b0 +#define CYDEV_PHUB_TDMEM54_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM54_ORIG_TD0 0x400079b0 +#define CYDEV_PHUB_TDMEM54_ORIG_TD1 0x400079b4 +#define CYDEV_PHUB_TDMEM55_BASE 0x400079b8 +#define CYDEV_PHUB_TDMEM55_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM55_ORIG_TD0 0x400079b8 +#define CYDEV_PHUB_TDMEM55_ORIG_TD1 0x400079bc +#define CYDEV_PHUB_TDMEM56_BASE 0x400079c0 +#define CYDEV_PHUB_TDMEM56_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM56_ORIG_TD0 0x400079c0 +#define CYDEV_PHUB_TDMEM56_ORIG_TD1 0x400079c4 +#define CYDEV_PHUB_TDMEM57_BASE 0x400079c8 +#define CYDEV_PHUB_TDMEM57_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM57_ORIG_TD0 0x400079c8 +#define CYDEV_PHUB_TDMEM57_ORIG_TD1 0x400079cc +#define CYDEV_PHUB_TDMEM58_BASE 0x400079d0 +#define CYDEV_PHUB_TDMEM58_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM58_ORIG_TD0 0x400079d0 +#define CYDEV_PHUB_TDMEM58_ORIG_TD1 0x400079d4 +#define CYDEV_PHUB_TDMEM59_BASE 0x400079d8 +#define CYDEV_PHUB_TDMEM59_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM59_ORIG_TD0 0x400079d8 +#define CYDEV_PHUB_TDMEM59_ORIG_TD1 0x400079dc +#define CYDEV_PHUB_TDMEM60_BASE 0x400079e0 +#define CYDEV_PHUB_TDMEM60_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM60_ORIG_TD0 0x400079e0 +#define CYDEV_PHUB_TDMEM60_ORIG_TD1 0x400079e4 +#define CYDEV_PHUB_TDMEM61_BASE 0x400079e8 +#define CYDEV_PHUB_TDMEM61_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM61_ORIG_TD0 0x400079e8 +#define CYDEV_PHUB_TDMEM61_ORIG_TD1 0x400079ec +#define CYDEV_PHUB_TDMEM62_BASE 0x400079f0 +#define CYDEV_PHUB_TDMEM62_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM62_ORIG_TD0 0x400079f0 +#define CYDEV_PHUB_TDMEM62_ORIG_TD1 0x400079f4 +#define CYDEV_PHUB_TDMEM63_BASE 0x400079f8 +#define CYDEV_PHUB_TDMEM63_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM63_ORIG_TD0 0x400079f8 +#define CYDEV_PHUB_TDMEM63_ORIG_TD1 0x400079fc +#define CYDEV_PHUB_TDMEM64_BASE 0x40007a00 +#define CYDEV_PHUB_TDMEM64_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM64_ORIG_TD0 0x40007a00 +#define CYDEV_PHUB_TDMEM64_ORIG_TD1 0x40007a04 +#define CYDEV_PHUB_TDMEM65_BASE 0x40007a08 +#define CYDEV_PHUB_TDMEM65_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM65_ORIG_TD0 0x40007a08 +#define CYDEV_PHUB_TDMEM65_ORIG_TD1 0x40007a0c +#define CYDEV_PHUB_TDMEM66_BASE 0x40007a10 +#define CYDEV_PHUB_TDMEM66_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM66_ORIG_TD0 0x40007a10 +#define CYDEV_PHUB_TDMEM66_ORIG_TD1 0x40007a14 +#define CYDEV_PHUB_TDMEM67_BASE 0x40007a18 +#define CYDEV_PHUB_TDMEM67_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM67_ORIG_TD0 0x40007a18 +#define CYDEV_PHUB_TDMEM67_ORIG_TD1 0x40007a1c +#define CYDEV_PHUB_TDMEM68_BASE 0x40007a20 +#define CYDEV_PHUB_TDMEM68_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM68_ORIG_TD0 0x40007a20 +#define CYDEV_PHUB_TDMEM68_ORIG_TD1 0x40007a24 +#define CYDEV_PHUB_TDMEM69_BASE 0x40007a28 +#define CYDEV_PHUB_TDMEM69_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM69_ORIG_TD0 0x40007a28 +#define CYDEV_PHUB_TDMEM69_ORIG_TD1 0x40007a2c +#define CYDEV_PHUB_TDMEM70_BASE 0x40007a30 +#define CYDEV_PHUB_TDMEM70_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM70_ORIG_TD0 0x40007a30 +#define CYDEV_PHUB_TDMEM70_ORIG_TD1 0x40007a34 +#define CYDEV_PHUB_TDMEM71_BASE 0x40007a38 +#define CYDEV_PHUB_TDMEM71_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM71_ORIG_TD0 0x40007a38 +#define CYDEV_PHUB_TDMEM71_ORIG_TD1 0x40007a3c +#define CYDEV_PHUB_TDMEM72_BASE 0x40007a40 +#define CYDEV_PHUB_TDMEM72_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM72_ORIG_TD0 0x40007a40 +#define CYDEV_PHUB_TDMEM72_ORIG_TD1 0x40007a44 +#define CYDEV_PHUB_TDMEM73_BASE 0x40007a48 +#define CYDEV_PHUB_TDMEM73_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM73_ORIG_TD0 0x40007a48 +#define CYDEV_PHUB_TDMEM73_ORIG_TD1 0x40007a4c +#define CYDEV_PHUB_TDMEM74_BASE 0x40007a50 +#define CYDEV_PHUB_TDMEM74_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM74_ORIG_TD0 0x40007a50 +#define CYDEV_PHUB_TDMEM74_ORIG_TD1 0x40007a54 +#define CYDEV_PHUB_TDMEM75_BASE 0x40007a58 +#define CYDEV_PHUB_TDMEM75_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM75_ORIG_TD0 0x40007a58 +#define CYDEV_PHUB_TDMEM75_ORIG_TD1 0x40007a5c +#define CYDEV_PHUB_TDMEM76_BASE 0x40007a60 +#define CYDEV_PHUB_TDMEM76_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM76_ORIG_TD0 0x40007a60 +#define CYDEV_PHUB_TDMEM76_ORIG_TD1 0x40007a64 +#define CYDEV_PHUB_TDMEM77_BASE 0x40007a68 +#define CYDEV_PHUB_TDMEM77_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM77_ORIG_TD0 0x40007a68 +#define CYDEV_PHUB_TDMEM77_ORIG_TD1 0x40007a6c +#define CYDEV_PHUB_TDMEM78_BASE 0x40007a70 +#define CYDEV_PHUB_TDMEM78_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM78_ORIG_TD0 0x40007a70 +#define CYDEV_PHUB_TDMEM78_ORIG_TD1 0x40007a74 +#define CYDEV_PHUB_TDMEM79_BASE 0x40007a78 +#define CYDEV_PHUB_TDMEM79_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM79_ORIG_TD0 0x40007a78 +#define CYDEV_PHUB_TDMEM79_ORIG_TD1 0x40007a7c +#define CYDEV_PHUB_TDMEM80_BASE 0x40007a80 +#define CYDEV_PHUB_TDMEM80_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM80_ORIG_TD0 0x40007a80 +#define CYDEV_PHUB_TDMEM80_ORIG_TD1 0x40007a84 +#define CYDEV_PHUB_TDMEM81_BASE 0x40007a88 +#define CYDEV_PHUB_TDMEM81_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM81_ORIG_TD0 0x40007a88 +#define CYDEV_PHUB_TDMEM81_ORIG_TD1 0x40007a8c +#define CYDEV_PHUB_TDMEM82_BASE 0x40007a90 +#define CYDEV_PHUB_TDMEM82_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM82_ORIG_TD0 0x40007a90 +#define CYDEV_PHUB_TDMEM82_ORIG_TD1 0x40007a94 +#define CYDEV_PHUB_TDMEM83_BASE 0x40007a98 +#define CYDEV_PHUB_TDMEM83_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM83_ORIG_TD0 0x40007a98 +#define CYDEV_PHUB_TDMEM83_ORIG_TD1 0x40007a9c +#define CYDEV_PHUB_TDMEM84_BASE 0x40007aa0 +#define CYDEV_PHUB_TDMEM84_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM84_ORIG_TD0 0x40007aa0 +#define CYDEV_PHUB_TDMEM84_ORIG_TD1 0x40007aa4 +#define CYDEV_PHUB_TDMEM85_BASE 0x40007aa8 +#define CYDEV_PHUB_TDMEM85_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM85_ORIG_TD0 0x40007aa8 +#define CYDEV_PHUB_TDMEM85_ORIG_TD1 0x40007aac +#define CYDEV_PHUB_TDMEM86_BASE 0x40007ab0 +#define CYDEV_PHUB_TDMEM86_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM86_ORIG_TD0 0x40007ab0 +#define CYDEV_PHUB_TDMEM86_ORIG_TD1 0x40007ab4 +#define CYDEV_PHUB_TDMEM87_BASE 0x40007ab8 +#define CYDEV_PHUB_TDMEM87_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM87_ORIG_TD0 0x40007ab8 +#define CYDEV_PHUB_TDMEM87_ORIG_TD1 0x40007abc +#define CYDEV_PHUB_TDMEM88_BASE 0x40007ac0 +#define CYDEV_PHUB_TDMEM88_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM88_ORIG_TD0 0x40007ac0 +#define CYDEV_PHUB_TDMEM88_ORIG_TD1 0x40007ac4 +#define CYDEV_PHUB_TDMEM89_BASE 0x40007ac8 +#define CYDEV_PHUB_TDMEM89_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM89_ORIG_TD0 0x40007ac8 +#define CYDEV_PHUB_TDMEM89_ORIG_TD1 0x40007acc +#define CYDEV_PHUB_TDMEM90_BASE 0x40007ad0 +#define CYDEV_PHUB_TDMEM90_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM90_ORIG_TD0 0x40007ad0 +#define CYDEV_PHUB_TDMEM90_ORIG_TD1 0x40007ad4 +#define CYDEV_PHUB_TDMEM91_BASE 0x40007ad8 +#define CYDEV_PHUB_TDMEM91_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM91_ORIG_TD0 0x40007ad8 +#define CYDEV_PHUB_TDMEM91_ORIG_TD1 0x40007adc +#define CYDEV_PHUB_TDMEM92_BASE 0x40007ae0 +#define CYDEV_PHUB_TDMEM92_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM92_ORIG_TD0 0x40007ae0 +#define CYDEV_PHUB_TDMEM92_ORIG_TD1 0x40007ae4 +#define CYDEV_PHUB_TDMEM93_BASE 0x40007ae8 +#define CYDEV_PHUB_TDMEM93_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM93_ORIG_TD0 0x40007ae8 +#define CYDEV_PHUB_TDMEM93_ORIG_TD1 0x40007aec +#define CYDEV_PHUB_TDMEM94_BASE 0x40007af0 +#define CYDEV_PHUB_TDMEM94_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM94_ORIG_TD0 0x40007af0 +#define CYDEV_PHUB_TDMEM94_ORIG_TD1 0x40007af4 +#define CYDEV_PHUB_TDMEM95_BASE 0x40007af8 +#define CYDEV_PHUB_TDMEM95_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM95_ORIG_TD0 0x40007af8 +#define CYDEV_PHUB_TDMEM95_ORIG_TD1 0x40007afc +#define CYDEV_PHUB_TDMEM96_BASE 0x40007b00 +#define CYDEV_PHUB_TDMEM96_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM96_ORIG_TD0 0x40007b00 +#define CYDEV_PHUB_TDMEM96_ORIG_TD1 0x40007b04 +#define CYDEV_PHUB_TDMEM97_BASE 0x40007b08 +#define CYDEV_PHUB_TDMEM97_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM97_ORIG_TD0 0x40007b08 +#define CYDEV_PHUB_TDMEM97_ORIG_TD1 0x40007b0c +#define CYDEV_PHUB_TDMEM98_BASE 0x40007b10 +#define CYDEV_PHUB_TDMEM98_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM98_ORIG_TD0 0x40007b10 +#define CYDEV_PHUB_TDMEM98_ORIG_TD1 0x40007b14 +#define CYDEV_PHUB_TDMEM99_BASE 0x40007b18 +#define CYDEV_PHUB_TDMEM99_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM99_ORIG_TD0 0x40007b18 +#define CYDEV_PHUB_TDMEM99_ORIG_TD1 0x40007b1c +#define CYDEV_PHUB_TDMEM100_BASE 0x40007b20 +#define CYDEV_PHUB_TDMEM100_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM100_ORIG_TD0 0x40007b20 +#define CYDEV_PHUB_TDMEM100_ORIG_TD1 0x40007b24 +#define CYDEV_PHUB_TDMEM101_BASE 0x40007b28 +#define CYDEV_PHUB_TDMEM101_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM101_ORIG_TD0 0x40007b28 +#define CYDEV_PHUB_TDMEM101_ORIG_TD1 0x40007b2c +#define CYDEV_PHUB_TDMEM102_BASE 0x40007b30 +#define CYDEV_PHUB_TDMEM102_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM102_ORIG_TD0 0x40007b30 +#define CYDEV_PHUB_TDMEM102_ORIG_TD1 0x40007b34 +#define CYDEV_PHUB_TDMEM103_BASE 0x40007b38 +#define CYDEV_PHUB_TDMEM103_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM103_ORIG_TD0 0x40007b38 +#define CYDEV_PHUB_TDMEM103_ORIG_TD1 0x40007b3c +#define CYDEV_PHUB_TDMEM104_BASE 0x40007b40 +#define CYDEV_PHUB_TDMEM104_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM104_ORIG_TD0 0x40007b40 +#define CYDEV_PHUB_TDMEM104_ORIG_TD1 0x40007b44 +#define CYDEV_PHUB_TDMEM105_BASE 0x40007b48 +#define CYDEV_PHUB_TDMEM105_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM105_ORIG_TD0 0x40007b48 +#define CYDEV_PHUB_TDMEM105_ORIG_TD1 0x40007b4c +#define CYDEV_PHUB_TDMEM106_BASE 0x40007b50 +#define CYDEV_PHUB_TDMEM106_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM106_ORIG_TD0 0x40007b50 +#define CYDEV_PHUB_TDMEM106_ORIG_TD1 0x40007b54 +#define CYDEV_PHUB_TDMEM107_BASE 0x40007b58 +#define CYDEV_PHUB_TDMEM107_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM107_ORIG_TD0 0x40007b58 +#define CYDEV_PHUB_TDMEM107_ORIG_TD1 0x40007b5c +#define CYDEV_PHUB_TDMEM108_BASE 0x40007b60 +#define CYDEV_PHUB_TDMEM108_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM108_ORIG_TD0 0x40007b60 +#define CYDEV_PHUB_TDMEM108_ORIG_TD1 0x40007b64 +#define CYDEV_PHUB_TDMEM109_BASE 0x40007b68 +#define CYDEV_PHUB_TDMEM109_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM109_ORIG_TD0 0x40007b68 +#define CYDEV_PHUB_TDMEM109_ORIG_TD1 0x40007b6c +#define CYDEV_PHUB_TDMEM110_BASE 0x40007b70 +#define CYDEV_PHUB_TDMEM110_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM110_ORIG_TD0 0x40007b70 +#define CYDEV_PHUB_TDMEM110_ORIG_TD1 0x40007b74 +#define CYDEV_PHUB_TDMEM111_BASE 0x40007b78 +#define CYDEV_PHUB_TDMEM111_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM111_ORIG_TD0 0x40007b78 +#define CYDEV_PHUB_TDMEM111_ORIG_TD1 0x40007b7c +#define CYDEV_PHUB_TDMEM112_BASE 0x40007b80 +#define CYDEV_PHUB_TDMEM112_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM112_ORIG_TD0 0x40007b80 +#define CYDEV_PHUB_TDMEM112_ORIG_TD1 0x40007b84 +#define CYDEV_PHUB_TDMEM113_BASE 0x40007b88 +#define CYDEV_PHUB_TDMEM113_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM113_ORIG_TD0 0x40007b88 +#define CYDEV_PHUB_TDMEM113_ORIG_TD1 0x40007b8c +#define CYDEV_PHUB_TDMEM114_BASE 0x40007b90 +#define CYDEV_PHUB_TDMEM114_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM114_ORIG_TD0 0x40007b90 +#define CYDEV_PHUB_TDMEM114_ORIG_TD1 0x40007b94 +#define CYDEV_PHUB_TDMEM115_BASE 0x40007b98 +#define CYDEV_PHUB_TDMEM115_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM115_ORIG_TD0 0x40007b98 +#define CYDEV_PHUB_TDMEM115_ORIG_TD1 0x40007b9c +#define CYDEV_PHUB_TDMEM116_BASE 0x40007ba0 +#define CYDEV_PHUB_TDMEM116_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM116_ORIG_TD0 0x40007ba0 +#define CYDEV_PHUB_TDMEM116_ORIG_TD1 0x40007ba4 +#define CYDEV_PHUB_TDMEM117_BASE 0x40007ba8 +#define CYDEV_PHUB_TDMEM117_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM117_ORIG_TD0 0x40007ba8 +#define CYDEV_PHUB_TDMEM117_ORIG_TD1 0x40007bac +#define CYDEV_PHUB_TDMEM118_BASE 0x40007bb0 +#define CYDEV_PHUB_TDMEM118_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM118_ORIG_TD0 0x40007bb0 +#define CYDEV_PHUB_TDMEM118_ORIG_TD1 0x40007bb4 +#define CYDEV_PHUB_TDMEM119_BASE 0x40007bb8 +#define CYDEV_PHUB_TDMEM119_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM119_ORIG_TD0 0x40007bb8 +#define CYDEV_PHUB_TDMEM119_ORIG_TD1 0x40007bbc +#define CYDEV_PHUB_TDMEM120_BASE 0x40007bc0 +#define CYDEV_PHUB_TDMEM120_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM120_ORIG_TD0 0x40007bc0 +#define CYDEV_PHUB_TDMEM120_ORIG_TD1 0x40007bc4 +#define CYDEV_PHUB_TDMEM121_BASE 0x40007bc8 +#define CYDEV_PHUB_TDMEM121_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM121_ORIG_TD0 0x40007bc8 +#define CYDEV_PHUB_TDMEM121_ORIG_TD1 0x40007bcc +#define CYDEV_PHUB_TDMEM122_BASE 0x40007bd0 +#define CYDEV_PHUB_TDMEM122_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM122_ORIG_TD0 0x40007bd0 +#define CYDEV_PHUB_TDMEM122_ORIG_TD1 0x40007bd4 +#define CYDEV_PHUB_TDMEM123_BASE 0x40007bd8 +#define CYDEV_PHUB_TDMEM123_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM123_ORIG_TD0 0x40007bd8 +#define CYDEV_PHUB_TDMEM123_ORIG_TD1 0x40007bdc +#define CYDEV_PHUB_TDMEM124_BASE 0x40007be0 +#define CYDEV_PHUB_TDMEM124_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM124_ORIG_TD0 0x40007be0 +#define CYDEV_PHUB_TDMEM124_ORIG_TD1 0x40007be4 +#define CYDEV_PHUB_TDMEM125_BASE 0x40007be8 +#define CYDEV_PHUB_TDMEM125_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM125_ORIG_TD0 0x40007be8 +#define CYDEV_PHUB_TDMEM125_ORIG_TD1 0x40007bec +#define CYDEV_PHUB_TDMEM126_BASE 0x40007bf0 +#define CYDEV_PHUB_TDMEM126_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM126_ORIG_TD0 0x40007bf0 +#define CYDEV_PHUB_TDMEM126_ORIG_TD1 0x40007bf4 +#define CYDEV_PHUB_TDMEM127_BASE 0x40007bf8 +#define CYDEV_PHUB_TDMEM127_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM127_ORIG_TD0 0x40007bf8 +#define CYDEV_PHUB_TDMEM127_ORIG_TD1 0x40007bfc +#define CYDEV_EE_BASE 0x40008000 +#define CYDEV_EE_SIZE 0x00000800 +#define CYDEV_EE_DATA_MBASE 0x40008000 +#define CYDEV_EE_DATA_MSIZE 0x00000800 +#define CYDEV_CAN0_BASE 0x4000a000 +#define CYDEV_CAN0_SIZE 0x000002a0 +#define CYDEV_CAN0_CSR_BASE 0x4000a000 +#define CYDEV_CAN0_CSR_SIZE 0x00000018 +#define CYDEV_CAN0_CSR_INT_SR 0x4000a000 +#define CYDEV_CAN0_CSR_INT_EN 0x4000a004 +#define CYDEV_CAN0_CSR_BUF_SR 0x4000a008 +#define CYDEV_CAN0_CSR_ERR_SR 0x4000a00c +#define CYDEV_CAN0_CSR_CMD 0x4000a010 +#define CYDEV_CAN0_CSR_CFG 0x4000a014 +#define CYDEV_CAN0_TX0_BASE 0x4000a020 +#define CYDEV_CAN0_TX0_SIZE 0x00000010 +#define CYDEV_CAN0_TX0_CMD 0x4000a020 +#define CYDEV_CAN0_TX0_ID 0x4000a024 +#define CYDEV_CAN0_TX0_DH 0x4000a028 +#define CYDEV_CAN0_TX0_DL 0x4000a02c +#define CYDEV_CAN0_TX1_BASE 0x4000a030 +#define CYDEV_CAN0_TX1_SIZE 0x00000010 +#define CYDEV_CAN0_TX1_CMD 0x4000a030 +#define CYDEV_CAN0_TX1_ID 0x4000a034 +#define CYDEV_CAN0_TX1_DH 0x4000a038 +#define CYDEV_CAN0_TX1_DL 0x4000a03c +#define CYDEV_CAN0_TX2_BASE 0x4000a040 +#define CYDEV_CAN0_TX2_SIZE 0x00000010 +#define CYDEV_CAN0_TX2_CMD 0x4000a040 +#define CYDEV_CAN0_TX2_ID 0x4000a044 +#define CYDEV_CAN0_TX2_DH 0x4000a048 +#define CYDEV_CAN0_TX2_DL 0x4000a04c +#define CYDEV_CAN0_TX3_BASE 0x4000a050 +#define CYDEV_CAN0_TX3_SIZE 0x00000010 +#define CYDEV_CAN0_TX3_CMD 0x4000a050 +#define CYDEV_CAN0_TX3_ID 0x4000a054 +#define CYDEV_CAN0_TX3_DH 0x4000a058 +#define CYDEV_CAN0_TX3_DL 0x4000a05c +#define CYDEV_CAN0_TX4_BASE 0x4000a060 +#define CYDEV_CAN0_TX4_SIZE 0x00000010 +#define CYDEV_CAN0_TX4_CMD 0x4000a060 +#define CYDEV_CAN0_TX4_ID 0x4000a064 +#define CYDEV_CAN0_TX4_DH 0x4000a068 +#define CYDEV_CAN0_TX4_DL 0x4000a06c +#define CYDEV_CAN0_TX5_BASE 0x4000a070 +#define CYDEV_CAN0_TX5_SIZE 0x00000010 +#define CYDEV_CAN0_TX5_CMD 0x4000a070 +#define CYDEV_CAN0_TX5_ID 0x4000a074 +#define CYDEV_CAN0_TX5_DH 0x4000a078 +#define CYDEV_CAN0_TX5_DL 0x4000a07c +#define CYDEV_CAN0_TX6_BASE 0x4000a080 +#define CYDEV_CAN0_TX6_SIZE 0x00000010 +#define CYDEV_CAN0_TX6_CMD 0x4000a080 +#define CYDEV_CAN0_TX6_ID 0x4000a084 +#define CYDEV_CAN0_TX6_DH 0x4000a088 +#define CYDEV_CAN0_TX6_DL 0x4000a08c +#define CYDEV_CAN0_TX7_BASE 0x4000a090 +#define CYDEV_CAN0_TX7_SIZE 0x00000010 +#define CYDEV_CAN0_TX7_CMD 0x4000a090 +#define CYDEV_CAN0_TX7_ID 0x4000a094 +#define CYDEV_CAN0_TX7_DH 0x4000a098 +#define CYDEV_CAN0_TX7_DL 0x4000a09c +#define CYDEV_CAN0_RX0_BASE 0x4000a0a0 +#define CYDEV_CAN0_RX0_SIZE 0x00000020 +#define CYDEV_CAN0_RX0_CMD 0x4000a0a0 +#define CYDEV_CAN0_RX0_ID 0x4000a0a4 +#define CYDEV_CAN0_RX0_DH 0x4000a0a8 +#define CYDEV_CAN0_RX0_DL 0x4000a0ac +#define CYDEV_CAN0_RX0_AMR 0x4000a0b0 +#define CYDEV_CAN0_RX0_ACR 0x4000a0b4 +#define CYDEV_CAN0_RX0_AMRD 0x4000a0b8 +#define CYDEV_CAN0_RX0_ACRD 0x4000a0bc +#define CYDEV_CAN0_RX1_BASE 0x4000a0c0 +#define CYDEV_CAN0_RX1_SIZE 0x00000020 +#define CYDEV_CAN0_RX1_CMD 0x4000a0c0 +#define CYDEV_CAN0_RX1_ID 0x4000a0c4 +#define CYDEV_CAN0_RX1_DH 0x4000a0c8 +#define CYDEV_CAN0_RX1_DL 0x4000a0cc +#define CYDEV_CAN0_RX1_AMR 0x4000a0d0 +#define CYDEV_CAN0_RX1_ACR 0x4000a0d4 +#define CYDEV_CAN0_RX1_AMRD 0x4000a0d8 +#define CYDEV_CAN0_RX1_ACRD 0x4000a0dc +#define CYDEV_CAN0_RX2_BASE 0x4000a0e0 +#define CYDEV_CAN0_RX2_SIZE 0x00000020 +#define CYDEV_CAN0_RX2_CMD 0x4000a0e0 +#define CYDEV_CAN0_RX2_ID 0x4000a0e4 +#define CYDEV_CAN0_RX2_DH 0x4000a0e8 +#define CYDEV_CAN0_RX2_DL 0x4000a0ec +#define CYDEV_CAN0_RX2_AMR 0x4000a0f0 +#define CYDEV_CAN0_RX2_ACR 0x4000a0f4 +#define CYDEV_CAN0_RX2_AMRD 0x4000a0f8 +#define CYDEV_CAN0_RX2_ACRD 0x4000a0fc +#define CYDEV_CAN0_RX3_BASE 0x4000a100 +#define CYDEV_CAN0_RX3_SIZE 0x00000020 +#define CYDEV_CAN0_RX3_CMD 0x4000a100 +#define CYDEV_CAN0_RX3_ID 0x4000a104 +#define CYDEV_CAN0_RX3_DH 0x4000a108 +#define CYDEV_CAN0_RX3_DL 0x4000a10c +#define CYDEV_CAN0_RX3_AMR 0x4000a110 +#define CYDEV_CAN0_RX3_ACR 0x4000a114 +#define CYDEV_CAN0_RX3_AMRD 0x4000a118 +#define CYDEV_CAN0_RX3_ACRD 0x4000a11c +#define CYDEV_CAN0_RX4_BASE 0x4000a120 +#define CYDEV_CAN0_RX4_SIZE 0x00000020 +#define CYDEV_CAN0_RX4_CMD 0x4000a120 +#define CYDEV_CAN0_RX4_ID 0x4000a124 +#define CYDEV_CAN0_RX4_DH 0x4000a128 +#define CYDEV_CAN0_RX4_DL 0x4000a12c +#define CYDEV_CAN0_RX4_AMR 0x4000a130 +#define CYDEV_CAN0_RX4_ACR 0x4000a134 +#define CYDEV_CAN0_RX4_AMRD 0x4000a138 +#define CYDEV_CAN0_RX4_ACRD 0x4000a13c +#define CYDEV_CAN0_RX5_BASE 0x4000a140 +#define CYDEV_CAN0_RX5_SIZE 0x00000020 +#define CYDEV_CAN0_RX5_CMD 0x4000a140 +#define CYDEV_CAN0_RX5_ID 0x4000a144 +#define CYDEV_CAN0_RX5_DH 0x4000a148 +#define CYDEV_CAN0_RX5_DL 0x4000a14c +#define CYDEV_CAN0_RX5_AMR 0x4000a150 +#define CYDEV_CAN0_RX5_ACR 0x4000a154 +#define CYDEV_CAN0_RX5_AMRD 0x4000a158 +#define CYDEV_CAN0_RX5_ACRD 0x4000a15c +#define CYDEV_CAN0_RX6_BASE 0x4000a160 +#define CYDEV_CAN0_RX6_SIZE 0x00000020 +#define CYDEV_CAN0_RX6_CMD 0x4000a160 +#define CYDEV_CAN0_RX6_ID 0x4000a164 +#define CYDEV_CAN0_RX6_DH 0x4000a168 +#define CYDEV_CAN0_RX6_DL 0x4000a16c +#define CYDEV_CAN0_RX6_AMR 0x4000a170 +#define CYDEV_CAN0_RX6_ACR 0x4000a174 +#define CYDEV_CAN0_RX6_AMRD 0x4000a178 +#define CYDEV_CAN0_RX6_ACRD 0x4000a17c +#define CYDEV_CAN0_RX7_BASE 0x4000a180 +#define CYDEV_CAN0_RX7_SIZE 0x00000020 +#define CYDEV_CAN0_RX7_CMD 0x4000a180 +#define CYDEV_CAN0_RX7_ID 0x4000a184 +#define CYDEV_CAN0_RX7_DH 0x4000a188 +#define CYDEV_CAN0_RX7_DL 0x4000a18c +#define CYDEV_CAN0_RX7_AMR 0x4000a190 +#define CYDEV_CAN0_RX7_ACR 0x4000a194 +#define CYDEV_CAN0_RX7_AMRD 0x4000a198 +#define CYDEV_CAN0_RX7_ACRD 0x4000a19c +#define CYDEV_CAN0_RX8_BASE 0x4000a1a0 +#define CYDEV_CAN0_RX8_SIZE 0x00000020 +#define CYDEV_CAN0_RX8_CMD 0x4000a1a0 +#define CYDEV_CAN0_RX8_ID 0x4000a1a4 +#define CYDEV_CAN0_RX8_DH 0x4000a1a8 +#define CYDEV_CAN0_RX8_DL 0x4000a1ac +#define CYDEV_CAN0_RX8_AMR 0x4000a1b0 +#define CYDEV_CAN0_RX8_ACR 0x4000a1b4 +#define CYDEV_CAN0_RX8_AMRD 0x4000a1b8 +#define CYDEV_CAN0_RX8_ACRD 0x4000a1bc +#define CYDEV_CAN0_RX9_BASE 0x4000a1c0 +#define CYDEV_CAN0_RX9_SIZE 0x00000020 +#define CYDEV_CAN0_RX9_CMD 0x4000a1c0 +#define CYDEV_CAN0_RX9_ID 0x4000a1c4 +#define CYDEV_CAN0_RX9_DH 0x4000a1c8 +#define CYDEV_CAN0_RX9_DL 0x4000a1cc +#define CYDEV_CAN0_RX9_AMR 0x4000a1d0 +#define CYDEV_CAN0_RX9_ACR 0x4000a1d4 +#define CYDEV_CAN0_RX9_AMRD 0x4000a1d8 +#define CYDEV_CAN0_RX9_ACRD 0x4000a1dc +#define CYDEV_CAN0_RX10_BASE 0x4000a1e0 +#define CYDEV_CAN0_RX10_SIZE 0x00000020 +#define CYDEV_CAN0_RX10_CMD 0x4000a1e0 +#define CYDEV_CAN0_RX10_ID 0x4000a1e4 +#define CYDEV_CAN0_RX10_DH 0x4000a1e8 +#define CYDEV_CAN0_RX10_DL 0x4000a1ec +#define CYDEV_CAN0_RX10_AMR 0x4000a1f0 +#define CYDEV_CAN0_RX10_ACR 0x4000a1f4 +#define CYDEV_CAN0_RX10_AMRD 0x4000a1f8 +#define CYDEV_CAN0_RX10_ACRD 0x4000a1fc +#define CYDEV_CAN0_RX11_BASE 0x4000a200 +#define CYDEV_CAN0_RX11_SIZE 0x00000020 +#define CYDEV_CAN0_RX11_CMD 0x4000a200 +#define CYDEV_CAN0_RX11_ID 0x4000a204 +#define CYDEV_CAN0_RX11_DH 0x4000a208 +#define CYDEV_CAN0_RX11_DL 0x4000a20c +#define CYDEV_CAN0_RX11_AMR 0x4000a210 +#define CYDEV_CAN0_RX11_ACR 0x4000a214 +#define CYDEV_CAN0_RX11_AMRD 0x4000a218 +#define CYDEV_CAN0_RX11_ACRD 0x4000a21c +#define CYDEV_CAN0_RX12_BASE 0x4000a220 +#define CYDEV_CAN0_RX12_SIZE 0x00000020 +#define CYDEV_CAN0_RX12_CMD 0x4000a220 +#define CYDEV_CAN0_RX12_ID 0x4000a224 +#define CYDEV_CAN0_RX12_DH 0x4000a228 +#define CYDEV_CAN0_RX12_DL 0x4000a22c +#define CYDEV_CAN0_RX12_AMR 0x4000a230 +#define CYDEV_CAN0_RX12_ACR 0x4000a234 +#define CYDEV_CAN0_RX12_AMRD 0x4000a238 +#define CYDEV_CAN0_RX12_ACRD 0x4000a23c +#define CYDEV_CAN0_RX13_BASE 0x4000a240 +#define CYDEV_CAN0_RX13_SIZE 0x00000020 +#define CYDEV_CAN0_RX13_CMD 0x4000a240 +#define CYDEV_CAN0_RX13_ID 0x4000a244 +#define CYDEV_CAN0_RX13_DH 0x4000a248 +#define CYDEV_CAN0_RX13_DL 0x4000a24c +#define CYDEV_CAN0_RX13_AMR 0x4000a250 +#define CYDEV_CAN0_RX13_ACR 0x4000a254 +#define CYDEV_CAN0_RX13_AMRD 0x4000a258 +#define CYDEV_CAN0_RX13_ACRD 0x4000a25c +#define CYDEV_CAN0_RX14_BASE 0x4000a260 +#define CYDEV_CAN0_RX14_SIZE 0x00000020 +#define CYDEV_CAN0_RX14_CMD 0x4000a260 +#define CYDEV_CAN0_RX14_ID 0x4000a264 +#define CYDEV_CAN0_RX14_DH 0x4000a268 +#define CYDEV_CAN0_RX14_DL 0x4000a26c +#define CYDEV_CAN0_RX14_AMR 0x4000a270 +#define CYDEV_CAN0_RX14_ACR 0x4000a274 +#define CYDEV_CAN0_RX14_AMRD 0x4000a278 +#define CYDEV_CAN0_RX14_ACRD 0x4000a27c +#define CYDEV_CAN0_RX15_BASE 0x4000a280 +#define CYDEV_CAN0_RX15_SIZE 0x00000020 +#define CYDEV_CAN0_RX15_CMD 0x4000a280 +#define CYDEV_CAN0_RX15_ID 0x4000a284 +#define CYDEV_CAN0_RX15_DH 0x4000a288 +#define CYDEV_CAN0_RX15_DL 0x4000a28c +#define CYDEV_CAN0_RX15_AMR 0x4000a290 +#define CYDEV_CAN0_RX15_ACR 0x4000a294 +#define CYDEV_CAN0_RX15_AMRD 0x4000a298 +#define CYDEV_CAN0_RX15_ACRD 0x4000a29c +#define CYDEV_DFB0_BASE 0x4000c000 +#define CYDEV_DFB0_SIZE 0x000007b5 +#define CYDEV_DFB0_DPA_SRAM_BASE 0x4000c000 +#define CYDEV_DFB0_DPA_SRAM_SIZE 0x00000200 +#define CYDEV_DFB0_DPA_SRAM_DATA_MBASE 0x4000c000 +#define CYDEV_DFB0_DPA_SRAM_DATA_MSIZE 0x00000200 +#define CYDEV_DFB0_DPB_SRAM_BASE 0x4000c200 +#define CYDEV_DFB0_DPB_SRAM_SIZE 0x00000200 +#define CYDEV_DFB0_DPB_SRAM_DATA_MBASE 0x4000c200 +#define CYDEV_DFB0_DPB_SRAM_DATA_MSIZE 0x00000200 +#define CYDEV_DFB0_CSA_SRAM_BASE 0x4000c400 +#define CYDEV_DFB0_CSA_SRAM_SIZE 0x00000100 +#define CYDEV_DFB0_CSA_SRAM_DATA_MBASE 0x4000c400 +#define CYDEV_DFB0_CSA_SRAM_DATA_MSIZE 0x00000100 +#define CYDEV_DFB0_CSB_SRAM_BASE 0x4000c500 +#define CYDEV_DFB0_CSB_SRAM_SIZE 0x00000100 +#define CYDEV_DFB0_CSB_SRAM_DATA_MBASE 0x4000c500 +#define CYDEV_DFB0_CSB_SRAM_DATA_MSIZE 0x00000100 +#define CYDEV_DFB0_FSM_SRAM_BASE 0x4000c600 +#define CYDEV_DFB0_FSM_SRAM_SIZE 0x00000100 +#define CYDEV_DFB0_FSM_SRAM_DATA_MBASE 0x4000c600 +#define CYDEV_DFB0_FSM_SRAM_DATA_MSIZE 0x00000100 +#define CYDEV_DFB0_ACU_SRAM_BASE 0x4000c700 +#define CYDEV_DFB0_ACU_SRAM_SIZE 0x00000040 +#define CYDEV_DFB0_ACU_SRAM_DATA_MBASE 0x4000c700 +#define CYDEV_DFB0_ACU_SRAM_DATA_MSIZE 0x00000040 +#define CYDEV_DFB0_CR 0x4000c780 +#define CYDEV_DFB0_SR 0x4000c784 +#define CYDEV_DFB0_RAM_EN 0x4000c788 +#define CYDEV_DFB0_RAM_DIR 0x4000c78c +#define CYDEV_DFB0_SEMA 0x4000c790 +#define CYDEV_DFB0_DSI_CTRL 0x4000c794 +#define CYDEV_DFB0_INT_CTRL 0x4000c798 +#define CYDEV_DFB0_DMA_CTRL 0x4000c79c +#define CYDEV_DFB0_STAGEA 0x4000c7a0 +#define CYDEV_DFB0_STAGEAM 0x4000c7a1 +#define CYDEV_DFB0_STAGEAH 0x4000c7a2 +#define CYDEV_DFB0_STAGEB 0x4000c7a4 +#define CYDEV_DFB0_STAGEBM 0x4000c7a5 +#define CYDEV_DFB0_STAGEBH 0x4000c7a6 +#define CYDEV_DFB0_HOLDA 0x4000c7a8 +#define CYDEV_DFB0_HOLDAM 0x4000c7a9 +#define CYDEV_DFB0_HOLDAH 0x4000c7aa +#define CYDEV_DFB0_HOLDAS 0x4000c7ab +#define CYDEV_DFB0_HOLDB 0x4000c7ac +#define CYDEV_DFB0_HOLDBM 0x4000c7ad +#define CYDEV_DFB0_HOLDBH 0x4000c7ae +#define CYDEV_DFB0_HOLDBS 0x4000c7af +#define CYDEV_DFB0_COHER 0x4000c7b0 +#define CYDEV_DFB0_DALIGN 0x4000c7b4 +#define CYDEV_UCFG_BASE 0x40010000 +#define CYDEV_UCFG_SIZE 0x00005040 +#define CYDEV_UCFG_B0_BASE 0x40010000 +#define CYDEV_UCFG_B0_SIZE 0x00000fef +#define CYDEV_UCFG_B0_P0_BASE 0x40010000 +#define CYDEV_UCFG_B0_P0_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P0_U0_BASE 0x40010000 +#define CYDEV_UCFG_B0_P0_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT0 0x40010000 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT1 0x40010004 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT2 0x40010008 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT3 0x4001000c +#define CYDEV_UCFG_B0_P0_U0_PLD_IT4 0x40010010 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT5 0x40010014 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT6 0x40010018 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT7 0x4001001c +#define CYDEV_UCFG_B0_P0_U0_PLD_IT8 0x40010020 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT9 0x40010024 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT10 0x40010028 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT11 0x4001002c +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT0 0x40010030 +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT1 0x40010032 +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT2 0x40010034 +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT3 0x40010036 +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST 0x40010038 +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB 0x4001003a +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET 0x4001003c +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS 0x4001003e +#define CYDEV_UCFG_B0_P0_U0_CFG0 0x40010040 +#define CYDEV_UCFG_B0_P0_U0_CFG1 0x40010041 +#define CYDEV_UCFG_B0_P0_U0_CFG2 0x40010042 +#define CYDEV_UCFG_B0_P0_U0_CFG3 0x40010043 +#define CYDEV_UCFG_B0_P0_U0_CFG4 0x40010044 +#define CYDEV_UCFG_B0_P0_U0_CFG5 0x40010045 +#define CYDEV_UCFG_B0_P0_U0_CFG6 0x40010046 +#define CYDEV_UCFG_B0_P0_U0_CFG7 0x40010047 +#define CYDEV_UCFG_B0_P0_U0_CFG8 0x40010048 +#define CYDEV_UCFG_B0_P0_U0_CFG9 0x40010049 +#define CYDEV_UCFG_B0_P0_U0_CFG10 0x4001004a +#define CYDEV_UCFG_B0_P0_U0_CFG11 0x4001004b +#define CYDEV_UCFG_B0_P0_U0_CFG12 0x4001004c +#define CYDEV_UCFG_B0_P0_U0_CFG13 0x4001004d +#define CYDEV_UCFG_B0_P0_U0_CFG14 0x4001004e +#define CYDEV_UCFG_B0_P0_U0_CFG15 0x4001004f +#define CYDEV_UCFG_B0_P0_U0_CFG16 0x40010050 +#define CYDEV_UCFG_B0_P0_U0_CFG17 0x40010051 +#define CYDEV_UCFG_B0_P0_U0_CFG18 0x40010052 +#define CYDEV_UCFG_B0_P0_U0_CFG19 0x40010053 +#define CYDEV_UCFG_B0_P0_U0_CFG20 0x40010054 +#define CYDEV_UCFG_B0_P0_U0_CFG21 0x40010055 +#define CYDEV_UCFG_B0_P0_U0_CFG22 0x40010056 +#define CYDEV_UCFG_B0_P0_U0_CFG23 0x40010057 +#define CYDEV_UCFG_B0_P0_U0_CFG24 0x40010058 +#define CYDEV_UCFG_B0_P0_U0_CFG25 0x40010059 +#define CYDEV_UCFG_B0_P0_U0_CFG26 0x4001005a +#define CYDEV_UCFG_B0_P0_U0_CFG27 0x4001005b +#define CYDEV_UCFG_B0_P0_U0_CFG28 0x4001005c +#define CYDEV_UCFG_B0_P0_U0_CFG29 0x4001005d +#define CYDEV_UCFG_B0_P0_U0_CFG30 0x4001005e +#define CYDEV_UCFG_B0_P0_U0_CFG31 0x4001005f +#define CYDEV_UCFG_B0_P0_U0_DCFG0 0x40010060 +#define CYDEV_UCFG_B0_P0_U0_DCFG1 0x40010062 +#define CYDEV_UCFG_B0_P0_U0_DCFG2 0x40010064 +#define CYDEV_UCFG_B0_P0_U0_DCFG3 0x40010066 +#define CYDEV_UCFG_B0_P0_U0_DCFG4 0x40010068 +#define CYDEV_UCFG_B0_P0_U0_DCFG5 0x4001006a +#define CYDEV_UCFG_B0_P0_U0_DCFG6 0x4001006c +#define CYDEV_UCFG_B0_P0_U0_DCFG7 0x4001006e +#define CYDEV_UCFG_B0_P0_U1_BASE 0x40010080 +#define CYDEV_UCFG_B0_P0_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT0 0x40010080 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT1 0x40010084 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT2 0x40010088 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT3 0x4001008c +#define CYDEV_UCFG_B0_P0_U1_PLD_IT4 0x40010090 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT5 0x40010094 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT6 0x40010098 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT7 0x4001009c +#define CYDEV_UCFG_B0_P0_U1_PLD_IT8 0x400100a0 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT9 0x400100a4 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT10 0x400100a8 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT11 0x400100ac +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT0 0x400100b0 +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT1 0x400100b2 +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT2 0x400100b4 +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT3 0x400100b6 +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST 0x400100b8 +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB 0x400100ba +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET 0x400100bc +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS 0x400100be +#define CYDEV_UCFG_B0_P0_U1_CFG0 0x400100c0 +#define CYDEV_UCFG_B0_P0_U1_CFG1 0x400100c1 +#define CYDEV_UCFG_B0_P0_U1_CFG2 0x400100c2 +#define CYDEV_UCFG_B0_P0_U1_CFG3 0x400100c3 +#define CYDEV_UCFG_B0_P0_U1_CFG4 0x400100c4 +#define CYDEV_UCFG_B0_P0_U1_CFG5 0x400100c5 +#define CYDEV_UCFG_B0_P0_U1_CFG6 0x400100c6 +#define CYDEV_UCFG_B0_P0_U1_CFG7 0x400100c7 +#define CYDEV_UCFG_B0_P0_U1_CFG8 0x400100c8 +#define CYDEV_UCFG_B0_P0_U1_CFG9 0x400100c9 +#define CYDEV_UCFG_B0_P0_U1_CFG10 0x400100ca +#define CYDEV_UCFG_B0_P0_U1_CFG11 0x400100cb +#define CYDEV_UCFG_B0_P0_U1_CFG12 0x400100cc +#define CYDEV_UCFG_B0_P0_U1_CFG13 0x400100cd +#define CYDEV_UCFG_B0_P0_U1_CFG14 0x400100ce +#define CYDEV_UCFG_B0_P0_U1_CFG15 0x400100cf +#define CYDEV_UCFG_B0_P0_U1_CFG16 0x400100d0 +#define CYDEV_UCFG_B0_P0_U1_CFG17 0x400100d1 +#define CYDEV_UCFG_B0_P0_U1_CFG18 0x400100d2 +#define CYDEV_UCFG_B0_P0_U1_CFG19 0x400100d3 +#define CYDEV_UCFG_B0_P0_U1_CFG20 0x400100d4 +#define CYDEV_UCFG_B0_P0_U1_CFG21 0x400100d5 +#define CYDEV_UCFG_B0_P0_U1_CFG22 0x400100d6 +#define CYDEV_UCFG_B0_P0_U1_CFG23 0x400100d7 +#define CYDEV_UCFG_B0_P0_U1_CFG24 0x400100d8 +#define CYDEV_UCFG_B0_P0_U1_CFG25 0x400100d9 +#define CYDEV_UCFG_B0_P0_U1_CFG26 0x400100da +#define CYDEV_UCFG_B0_P0_U1_CFG27 0x400100db +#define CYDEV_UCFG_B0_P0_U1_CFG28 0x400100dc +#define CYDEV_UCFG_B0_P0_U1_CFG29 0x400100dd +#define CYDEV_UCFG_B0_P0_U1_CFG30 0x400100de +#define CYDEV_UCFG_B0_P0_U1_CFG31 0x400100df +#define CYDEV_UCFG_B0_P0_U1_DCFG0 0x400100e0 +#define CYDEV_UCFG_B0_P0_U1_DCFG1 0x400100e2 +#define CYDEV_UCFG_B0_P0_U1_DCFG2 0x400100e4 +#define CYDEV_UCFG_B0_P0_U1_DCFG3 0x400100e6 +#define CYDEV_UCFG_B0_P0_U1_DCFG4 0x400100e8 +#define CYDEV_UCFG_B0_P0_U1_DCFG5 0x400100ea +#define CYDEV_UCFG_B0_P0_U1_DCFG6 0x400100ec +#define CYDEV_UCFG_B0_P0_U1_DCFG7 0x400100ee +#define CYDEV_UCFG_B0_P0_ROUTE_BASE 0x40010100 +#define CYDEV_UCFG_B0_P0_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P1_BASE 0x40010200 +#define CYDEV_UCFG_B0_P1_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P1_U0_BASE 0x40010200 +#define CYDEV_UCFG_B0_P1_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT0 0x40010200 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT1 0x40010204 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT2 0x40010208 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT3 0x4001020c +#define CYDEV_UCFG_B0_P1_U0_PLD_IT4 0x40010210 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT5 0x40010214 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT6 0x40010218 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT7 0x4001021c +#define CYDEV_UCFG_B0_P1_U0_PLD_IT8 0x40010220 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT9 0x40010224 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT10 0x40010228 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT11 0x4001022c +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT0 0x40010230 +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT1 0x40010232 +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT2 0x40010234 +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT3 0x40010236 +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST 0x40010238 +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB 0x4001023a +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET 0x4001023c +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS 0x4001023e +#define CYDEV_UCFG_B0_P1_U0_CFG0 0x40010240 +#define CYDEV_UCFG_B0_P1_U0_CFG1 0x40010241 +#define CYDEV_UCFG_B0_P1_U0_CFG2 0x40010242 +#define CYDEV_UCFG_B0_P1_U0_CFG3 0x40010243 +#define CYDEV_UCFG_B0_P1_U0_CFG4 0x40010244 +#define CYDEV_UCFG_B0_P1_U0_CFG5 0x40010245 +#define CYDEV_UCFG_B0_P1_U0_CFG6 0x40010246 +#define CYDEV_UCFG_B0_P1_U0_CFG7 0x40010247 +#define CYDEV_UCFG_B0_P1_U0_CFG8 0x40010248 +#define CYDEV_UCFG_B0_P1_U0_CFG9 0x40010249 +#define CYDEV_UCFG_B0_P1_U0_CFG10 0x4001024a +#define CYDEV_UCFG_B0_P1_U0_CFG11 0x4001024b +#define CYDEV_UCFG_B0_P1_U0_CFG12 0x4001024c +#define CYDEV_UCFG_B0_P1_U0_CFG13 0x4001024d +#define CYDEV_UCFG_B0_P1_U0_CFG14 0x4001024e +#define CYDEV_UCFG_B0_P1_U0_CFG15 0x4001024f +#define CYDEV_UCFG_B0_P1_U0_CFG16 0x40010250 +#define CYDEV_UCFG_B0_P1_U0_CFG17 0x40010251 +#define CYDEV_UCFG_B0_P1_U0_CFG18 0x40010252 +#define CYDEV_UCFG_B0_P1_U0_CFG19 0x40010253 +#define CYDEV_UCFG_B0_P1_U0_CFG20 0x40010254 +#define CYDEV_UCFG_B0_P1_U0_CFG21 0x40010255 +#define CYDEV_UCFG_B0_P1_U0_CFG22 0x40010256 +#define CYDEV_UCFG_B0_P1_U0_CFG23 0x40010257 +#define CYDEV_UCFG_B0_P1_U0_CFG24 0x40010258 +#define CYDEV_UCFG_B0_P1_U0_CFG25 0x40010259 +#define CYDEV_UCFG_B0_P1_U0_CFG26 0x4001025a +#define CYDEV_UCFG_B0_P1_U0_CFG27 0x4001025b +#define CYDEV_UCFG_B0_P1_U0_CFG28 0x4001025c +#define CYDEV_UCFG_B0_P1_U0_CFG29 0x4001025d +#define CYDEV_UCFG_B0_P1_U0_CFG30 0x4001025e +#define CYDEV_UCFG_B0_P1_U0_CFG31 0x4001025f +#define CYDEV_UCFG_B0_P1_U0_DCFG0 0x40010260 +#define CYDEV_UCFG_B0_P1_U0_DCFG1 0x40010262 +#define CYDEV_UCFG_B0_P1_U0_DCFG2 0x40010264 +#define CYDEV_UCFG_B0_P1_U0_DCFG3 0x40010266 +#define CYDEV_UCFG_B0_P1_U0_DCFG4 0x40010268 +#define CYDEV_UCFG_B0_P1_U0_DCFG5 0x4001026a +#define CYDEV_UCFG_B0_P1_U0_DCFG6 0x4001026c +#define CYDEV_UCFG_B0_P1_U0_DCFG7 0x4001026e +#define CYDEV_UCFG_B0_P1_U1_BASE 0x40010280 +#define CYDEV_UCFG_B0_P1_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT0 0x40010280 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT1 0x40010284 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT2 0x40010288 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT3 0x4001028c +#define CYDEV_UCFG_B0_P1_U1_PLD_IT4 0x40010290 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT5 0x40010294 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT6 0x40010298 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT7 0x4001029c +#define CYDEV_UCFG_B0_P1_U1_PLD_IT8 0x400102a0 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT9 0x400102a4 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT10 0x400102a8 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT11 0x400102ac +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT0 0x400102b0 +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT1 0x400102b2 +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT2 0x400102b4 +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT3 0x400102b6 +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST 0x400102b8 +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB 0x400102ba +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET 0x400102bc +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS 0x400102be +#define CYDEV_UCFG_B0_P1_U1_CFG0 0x400102c0 +#define CYDEV_UCFG_B0_P1_U1_CFG1 0x400102c1 +#define CYDEV_UCFG_B0_P1_U1_CFG2 0x400102c2 +#define CYDEV_UCFG_B0_P1_U1_CFG3 0x400102c3 +#define CYDEV_UCFG_B0_P1_U1_CFG4 0x400102c4 +#define CYDEV_UCFG_B0_P1_U1_CFG5 0x400102c5 +#define CYDEV_UCFG_B0_P1_U1_CFG6 0x400102c6 +#define CYDEV_UCFG_B0_P1_U1_CFG7 0x400102c7 +#define CYDEV_UCFG_B0_P1_U1_CFG8 0x400102c8 +#define CYDEV_UCFG_B0_P1_U1_CFG9 0x400102c9 +#define CYDEV_UCFG_B0_P1_U1_CFG10 0x400102ca +#define CYDEV_UCFG_B0_P1_U1_CFG11 0x400102cb +#define CYDEV_UCFG_B0_P1_U1_CFG12 0x400102cc +#define CYDEV_UCFG_B0_P1_U1_CFG13 0x400102cd +#define CYDEV_UCFG_B0_P1_U1_CFG14 0x400102ce +#define CYDEV_UCFG_B0_P1_U1_CFG15 0x400102cf +#define CYDEV_UCFG_B0_P1_U1_CFG16 0x400102d0 +#define CYDEV_UCFG_B0_P1_U1_CFG17 0x400102d1 +#define CYDEV_UCFG_B0_P1_U1_CFG18 0x400102d2 +#define CYDEV_UCFG_B0_P1_U1_CFG19 0x400102d3 +#define CYDEV_UCFG_B0_P1_U1_CFG20 0x400102d4 +#define CYDEV_UCFG_B0_P1_U1_CFG21 0x400102d5 +#define CYDEV_UCFG_B0_P1_U1_CFG22 0x400102d6 +#define CYDEV_UCFG_B0_P1_U1_CFG23 0x400102d7 +#define CYDEV_UCFG_B0_P1_U1_CFG24 0x400102d8 +#define CYDEV_UCFG_B0_P1_U1_CFG25 0x400102d9 +#define CYDEV_UCFG_B0_P1_U1_CFG26 0x400102da +#define CYDEV_UCFG_B0_P1_U1_CFG27 0x400102db +#define CYDEV_UCFG_B0_P1_U1_CFG28 0x400102dc +#define CYDEV_UCFG_B0_P1_U1_CFG29 0x400102dd +#define CYDEV_UCFG_B0_P1_U1_CFG30 0x400102de +#define CYDEV_UCFG_B0_P1_U1_CFG31 0x400102df +#define CYDEV_UCFG_B0_P1_U1_DCFG0 0x400102e0 +#define CYDEV_UCFG_B0_P1_U1_DCFG1 0x400102e2 +#define CYDEV_UCFG_B0_P1_U1_DCFG2 0x400102e4 +#define CYDEV_UCFG_B0_P1_U1_DCFG3 0x400102e6 +#define CYDEV_UCFG_B0_P1_U1_DCFG4 0x400102e8 +#define CYDEV_UCFG_B0_P1_U1_DCFG5 0x400102ea +#define CYDEV_UCFG_B0_P1_U1_DCFG6 0x400102ec +#define CYDEV_UCFG_B0_P1_U1_DCFG7 0x400102ee +#define CYDEV_UCFG_B0_P1_ROUTE_BASE 0x40010300 +#define CYDEV_UCFG_B0_P1_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P2_BASE 0x40010400 +#define CYDEV_UCFG_B0_P2_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P2_U0_BASE 0x40010400 +#define CYDEV_UCFG_B0_P2_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT0 0x40010400 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT1 0x40010404 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT2 0x40010408 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT3 0x4001040c +#define CYDEV_UCFG_B0_P2_U0_PLD_IT4 0x40010410 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT5 0x40010414 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT6 0x40010418 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT7 0x4001041c +#define CYDEV_UCFG_B0_P2_U0_PLD_IT8 0x40010420 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT9 0x40010424 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT10 0x40010428 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT11 0x4001042c +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT0 0x40010430 +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT1 0x40010432 +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT2 0x40010434 +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT3 0x40010436 +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST 0x40010438 +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB 0x4001043a +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET 0x4001043c +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS 0x4001043e +#define CYDEV_UCFG_B0_P2_U0_CFG0 0x40010440 +#define CYDEV_UCFG_B0_P2_U0_CFG1 0x40010441 +#define CYDEV_UCFG_B0_P2_U0_CFG2 0x40010442 +#define CYDEV_UCFG_B0_P2_U0_CFG3 0x40010443 +#define CYDEV_UCFG_B0_P2_U0_CFG4 0x40010444 +#define CYDEV_UCFG_B0_P2_U0_CFG5 0x40010445 +#define CYDEV_UCFG_B0_P2_U0_CFG6 0x40010446 +#define CYDEV_UCFG_B0_P2_U0_CFG7 0x40010447 +#define CYDEV_UCFG_B0_P2_U0_CFG8 0x40010448 +#define CYDEV_UCFG_B0_P2_U0_CFG9 0x40010449 +#define CYDEV_UCFG_B0_P2_U0_CFG10 0x4001044a +#define CYDEV_UCFG_B0_P2_U0_CFG11 0x4001044b +#define CYDEV_UCFG_B0_P2_U0_CFG12 0x4001044c +#define CYDEV_UCFG_B0_P2_U0_CFG13 0x4001044d +#define CYDEV_UCFG_B0_P2_U0_CFG14 0x4001044e +#define CYDEV_UCFG_B0_P2_U0_CFG15 0x4001044f +#define CYDEV_UCFG_B0_P2_U0_CFG16 0x40010450 +#define CYDEV_UCFG_B0_P2_U0_CFG17 0x40010451 +#define CYDEV_UCFG_B0_P2_U0_CFG18 0x40010452 +#define CYDEV_UCFG_B0_P2_U0_CFG19 0x40010453 +#define CYDEV_UCFG_B0_P2_U0_CFG20 0x40010454 +#define CYDEV_UCFG_B0_P2_U0_CFG21 0x40010455 +#define CYDEV_UCFG_B0_P2_U0_CFG22 0x40010456 +#define CYDEV_UCFG_B0_P2_U0_CFG23 0x40010457 +#define CYDEV_UCFG_B0_P2_U0_CFG24 0x40010458 +#define CYDEV_UCFG_B0_P2_U0_CFG25 0x40010459 +#define CYDEV_UCFG_B0_P2_U0_CFG26 0x4001045a +#define CYDEV_UCFG_B0_P2_U0_CFG27 0x4001045b +#define CYDEV_UCFG_B0_P2_U0_CFG28 0x4001045c +#define CYDEV_UCFG_B0_P2_U0_CFG29 0x4001045d +#define CYDEV_UCFG_B0_P2_U0_CFG30 0x4001045e +#define CYDEV_UCFG_B0_P2_U0_CFG31 0x4001045f +#define CYDEV_UCFG_B0_P2_U0_DCFG0 0x40010460 +#define CYDEV_UCFG_B0_P2_U0_DCFG1 0x40010462 +#define CYDEV_UCFG_B0_P2_U0_DCFG2 0x40010464 +#define CYDEV_UCFG_B0_P2_U0_DCFG3 0x40010466 +#define CYDEV_UCFG_B0_P2_U0_DCFG4 0x40010468 +#define CYDEV_UCFG_B0_P2_U0_DCFG5 0x4001046a +#define CYDEV_UCFG_B0_P2_U0_DCFG6 0x4001046c +#define CYDEV_UCFG_B0_P2_U0_DCFG7 0x4001046e +#define CYDEV_UCFG_B0_P2_U1_BASE 0x40010480 +#define CYDEV_UCFG_B0_P2_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT0 0x40010480 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT1 0x40010484 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT2 0x40010488 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT3 0x4001048c +#define CYDEV_UCFG_B0_P2_U1_PLD_IT4 0x40010490 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT5 0x40010494 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT6 0x40010498 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT7 0x4001049c +#define CYDEV_UCFG_B0_P2_U1_PLD_IT8 0x400104a0 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT9 0x400104a4 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT10 0x400104a8 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT11 0x400104ac +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT0 0x400104b0 +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT1 0x400104b2 +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT2 0x400104b4 +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT3 0x400104b6 +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST 0x400104b8 +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB 0x400104ba +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET 0x400104bc +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS 0x400104be +#define CYDEV_UCFG_B0_P2_U1_CFG0 0x400104c0 +#define CYDEV_UCFG_B0_P2_U1_CFG1 0x400104c1 +#define CYDEV_UCFG_B0_P2_U1_CFG2 0x400104c2 +#define CYDEV_UCFG_B0_P2_U1_CFG3 0x400104c3 +#define CYDEV_UCFG_B0_P2_U1_CFG4 0x400104c4 +#define CYDEV_UCFG_B0_P2_U1_CFG5 0x400104c5 +#define CYDEV_UCFG_B0_P2_U1_CFG6 0x400104c6 +#define CYDEV_UCFG_B0_P2_U1_CFG7 0x400104c7 +#define CYDEV_UCFG_B0_P2_U1_CFG8 0x400104c8 +#define CYDEV_UCFG_B0_P2_U1_CFG9 0x400104c9 +#define CYDEV_UCFG_B0_P2_U1_CFG10 0x400104ca +#define CYDEV_UCFG_B0_P2_U1_CFG11 0x400104cb +#define CYDEV_UCFG_B0_P2_U1_CFG12 0x400104cc +#define CYDEV_UCFG_B0_P2_U1_CFG13 0x400104cd +#define CYDEV_UCFG_B0_P2_U1_CFG14 0x400104ce +#define CYDEV_UCFG_B0_P2_U1_CFG15 0x400104cf +#define CYDEV_UCFG_B0_P2_U1_CFG16 0x400104d0 +#define CYDEV_UCFG_B0_P2_U1_CFG17 0x400104d1 +#define CYDEV_UCFG_B0_P2_U1_CFG18 0x400104d2 +#define CYDEV_UCFG_B0_P2_U1_CFG19 0x400104d3 +#define CYDEV_UCFG_B0_P2_U1_CFG20 0x400104d4 +#define CYDEV_UCFG_B0_P2_U1_CFG21 0x400104d5 +#define CYDEV_UCFG_B0_P2_U1_CFG22 0x400104d6 +#define CYDEV_UCFG_B0_P2_U1_CFG23 0x400104d7 +#define CYDEV_UCFG_B0_P2_U1_CFG24 0x400104d8 +#define CYDEV_UCFG_B0_P2_U1_CFG25 0x400104d9 +#define CYDEV_UCFG_B0_P2_U1_CFG26 0x400104da +#define CYDEV_UCFG_B0_P2_U1_CFG27 0x400104db +#define CYDEV_UCFG_B0_P2_U1_CFG28 0x400104dc +#define CYDEV_UCFG_B0_P2_U1_CFG29 0x400104dd +#define CYDEV_UCFG_B0_P2_U1_CFG30 0x400104de +#define CYDEV_UCFG_B0_P2_U1_CFG31 0x400104df +#define CYDEV_UCFG_B0_P2_U1_DCFG0 0x400104e0 +#define CYDEV_UCFG_B0_P2_U1_DCFG1 0x400104e2 +#define CYDEV_UCFG_B0_P2_U1_DCFG2 0x400104e4 +#define CYDEV_UCFG_B0_P2_U1_DCFG3 0x400104e6 +#define CYDEV_UCFG_B0_P2_U1_DCFG4 0x400104e8 +#define CYDEV_UCFG_B0_P2_U1_DCFG5 0x400104ea +#define CYDEV_UCFG_B0_P2_U1_DCFG6 0x400104ec +#define CYDEV_UCFG_B0_P2_U1_DCFG7 0x400104ee +#define CYDEV_UCFG_B0_P2_ROUTE_BASE 0x40010500 +#define CYDEV_UCFG_B0_P2_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P3_BASE 0x40010600 +#define CYDEV_UCFG_B0_P3_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P3_U0_BASE 0x40010600 +#define CYDEV_UCFG_B0_P3_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT0 0x40010600 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT1 0x40010604 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT2 0x40010608 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT3 0x4001060c +#define CYDEV_UCFG_B0_P3_U0_PLD_IT4 0x40010610 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT5 0x40010614 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT6 0x40010618 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT7 0x4001061c +#define CYDEV_UCFG_B0_P3_U0_PLD_IT8 0x40010620 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT9 0x40010624 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT10 0x40010628 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT11 0x4001062c +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT0 0x40010630 +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT1 0x40010632 +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT2 0x40010634 +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT3 0x40010636 +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST 0x40010638 +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB 0x4001063a +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET 0x4001063c +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS 0x4001063e +#define CYDEV_UCFG_B0_P3_U0_CFG0 0x40010640 +#define CYDEV_UCFG_B0_P3_U0_CFG1 0x40010641 +#define CYDEV_UCFG_B0_P3_U0_CFG2 0x40010642 +#define CYDEV_UCFG_B0_P3_U0_CFG3 0x40010643 +#define CYDEV_UCFG_B0_P3_U0_CFG4 0x40010644 +#define CYDEV_UCFG_B0_P3_U0_CFG5 0x40010645 +#define CYDEV_UCFG_B0_P3_U0_CFG6 0x40010646 +#define CYDEV_UCFG_B0_P3_U0_CFG7 0x40010647 +#define CYDEV_UCFG_B0_P3_U0_CFG8 0x40010648 +#define CYDEV_UCFG_B0_P3_U0_CFG9 0x40010649 +#define CYDEV_UCFG_B0_P3_U0_CFG10 0x4001064a +#define CYDEV_UCFG_B0_P3_U0_CFG11 0x4001064b +#define CYDEV_UCFG_B0_P3_U0_CFG12 0x4001064c +#define CYDEV_UCFG_B0_P3_U0_CFG13 0x4001064d +#define CYDEV_UCFG_B0_P3_U0_CFG14 0x4001064e +#define CYDEV_UCFG_B0_P3_U0_CFG15 0x4001064f +#define CYDEV_UCFG_B0_P3_U0_CFG16 0x40010650 +#define CYDEV_UCFG_B0_P3_U0_CFG17 0x40010651 +#define CYDEV_UCFG_B0_P3_U0_CFG18 0x40010652 +#define CYDEV_UCFG_B0_P3_U0_CFG19 0x40010653 +#define CYDEV_UCFG_B0_P3_U0_CFG20 0x40010654 +#define CYDEV_UCFG_B0_P3_U0_CFG21 0x40010655 +#define CYDEV_UCFG_B0_P3_U0_CFG22 0x40010656 +#define CYDEV_UCFG_B0_P3_U0_CFG23 0x40010657 +#define CYDEV_UCFG_B0_P3_U0_CFG24 0x40010658 +#define CYDEV_UCFG_B0_P3_U0_CFG25 0x40010659 +#define CYDEV_UCFG_B0_P3_U0_CFG26 0x4001065a +#define CYDEV_UCFG_B0_P3_U0_CFG27 0x4001065b +#define CYDEV_UCFG_B0_P3_U0_CFG28 0x4001065c +#define CYDEV_UCFG_B0_P3_U0_CFG29 0x4001065d +#define CYDEV_UCFG_B0_P3_U0_CFG30 0x4001065e +#define CYDEV_UCFG_B0_P3_U0_CFG31 0x4001065f +#define CYDEV_UCFG_B0_P3_U0_DCFG0 0x40010660 +#define CYDEV_UCFG_B0_P3_U0_DCFG1 0x40010662 +#define CYDEV_UCFG_B0_P3_U0_DCFG2 0x40010664 +#define CYDEV_UCFG_B0_P3_U0_DCFG3 0x40010666 +#define CYDEV_UCFG_B0_P3_U0_DCFG4 0x40010668 +#define CYDEV_UCFG_B0_P3_U0_DCFG5 0x4001066a +#define CYDEV_UCFG_B0_P3_U0_DCFG6 0x4001066c +#define CYDEV_UCFG_B0_P3_U0_DCFG7 0x4001066e +#define CYDEV_UCFG_B0_P3_U1_BASE 0x40010680 +#define CYDEV_UCFG_B0_P3_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT0 0x40010680 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT1 0x40010684 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT2 0x40010688 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT3 0x4001068c +#define CYDEV_UCFG_B0_P3_U1_PLD_IT4 0x40010690 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT5 0x40010694 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT6 0x40010698 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT7 0x4001069c +#define CYDEV_UCFG_B0_P3_U1_PLD_IT8 0x400106a0 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT9 0x400106a4 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT10 0x400106a8 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT11 0x400106ac +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT0 0x400106b0 +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT1 0x400106b2 +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT2 0x400106b4 +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT3 0x400106b6 +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST 0x400106b8 +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB 0x400106ba +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET 0x400106bc +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS 0x400106be +#define CYDEV_UCFG_B0_P3_U1_CFG0 0x400106c0 +#define CYDEV_UCFG_B0_P3_U1_CFG1 0x400106c1 +#define CYDEV_UCFG_B0_P3_U1_CFG2 0x400106c2 +#define CYDEV_UCFG_B0_P3_U1_CFG3 0x400106c3 +#define CYDEV_UCFG_B0_P3_U1_CFG4 0x400106c4 +#define CYDEV_UCFG_B0_P3_U1_CFG5 0x400106c5 +#define CYDEV_UCFG_B0_P3_U1_CFG6 0x400106c6 +#define CYDEV_UCFG_B0_P3_U1_CFG7 0x400106c7 +#define CYDEV_UCFG_B0_P3_U1_CFG8 0x400106c8 +#define CYDEV_UCFG_B0_P3_U1_CFG9 0x400106c9 +#define CYDEV_UCFG_B0_P3_U1_CFG10 0x400106ca +#define CYDEV_UCFG_B0_P3_U1_CFG11 0x400106cb +#define CYDEV_UCFG_B0_P3_U1_CFG12 0x400106cc +#define CYDEV_UCFG_B0_P3_U1_CFG13 0x400106cd +#define CYDEV_UCFG_B0_P3_U1_CFG14 0x400106ce +#define CYDEV_UCFG_B0_P3_U1_CFG15 0x400106cf +#define CYDEV_UCFG_B0_P3_U1_CFG16 0x400106d0 +#define CYDEV_UCFG_B0_P3_U1_CFG17 0x400106d1 +#define CYDEV_UCFG_B0_P3_U1_CFG18 0x400106d2 +#define CYDEV_UCFG_B0_P3_U1_CFG19 0x400106d3 +#define CYDEV_UCFG_B0_P3_U1_CFG20 0x400106d4 +#define CYDEV_UCFG_B0_P3_U1_CFG21 0x400106d5 +#define CYDEV_UCFG_B0_P3_U1_CFG22 0x400106d6 +#define CYDEV_UCFG_B0_P3_U1_CFG23 0x400106d7 +#define CYDEV_UCFG_B0_P3_U1_CFG24 0x400106d8 +#define CYDEV_UCFG_B0_P3_U1_CFG25 0x400106d9 +#define CYDEV_UCFG_B0_P3_U1_CFG26 0x400106da +#define CYDEV_UCFG_B0_P3_U1_CFG27 0x400106db +#define CYDEV_UCFG_B0_P3_U1_CFG28 0x400106dc +#define CYDEV_UCFG_B0_P3_U1_CFG29 0x400106dd +#define CYDEV_UCFG_B0_P3_U1_CFG30 0x400106de +#define CYDEV_UCFG_B0_P3_U1_CFG31 0x400106df +#define CYDEV_UCFG_B0_P3_U1_DCFG0 0x400106e0 +#define CYDEV_UCFG_B0_P3_U1_DCFG1 0x400106e2 +#define CYDEV_UCFG_B0_P3_U1_DCFG2 0x400106e4 +#define CYDEV_UCFG_B0_P3_U1_DCFG3 0x400106e6 +#define CYDEV_UCFG_B0_P3_U1_DCFG4 0x400106e8 +#define CYDEV_UCFG_B0_P3_U1_DCFG5 0x400106ea +#define CYDEV_UCFG_B0_P3_U1_DCFG6 0x400106ec +#define CYDEV_UCFG_B0_P3_U1_DCFG7 0x400106ee +#define CYDEV_UCFG_B0_P3_ROUTE_BASE 0x40010700 +#define CYDEV_UCFG_B0_P3_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P4_BASE 0x40010800 +#define CYDEV_UCFG_B0_P4_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P4_U0_BASE 0x40010800 +#define CYDEV_UCFG_B0_P4_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT0 0x40010800 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT1 0x40010804 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT2 0x40010808 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT3 0x4001080c +#define CYDEV_UCFG_B0_P4_U0_PLD_IT4 0x40010810 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT5 0x40010814 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT6 0x40010818 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT7 0x4001081c +#define CYDEV_UCFG_B0_P4_U0_PLD_IT8 0x40010820 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT9 0x40010824 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT10 0x40010828 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT11 0x4001082c +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT0 0x40010830 +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT1 0x40010832 +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT2 0x40010834 +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT3 0x40010836 +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST 0x40010838 +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB 0x4001083a +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET 0x4001083c +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS 0x4001083e +#define CYDEV_UCFG_B0_P4_U0_CFG0 0x40010840 +#define CYDEV_UCFG_B0_P4_U0_CFG1 0x40010841 +#define CYDEV_UCFG_B0_P4_U0_CFG2 0x40010842 +#define CYDEV_UCFG_B0_P4_U0_CFG3 0x40010843 +#define CYDEV_UCFG_B0_P4_U0_CFG4 0x40010844 +#define CYDEV_UCFG_B0_P4_U0_CFG5 0x40010845 +#define CYDEV_UCFG_B0_P4_U0_CFG6 0x40010846 +#define CYDEV_UCFG_B0_P4_U0_CFG7 0x40010847 +#define CYDEV_UCFG_B0_P4_U0_CFG8 0x40010848 +#define CYDEV_UCFG_B0_P4_U0_CFG9 0x40010849 +#define CYDEV_UCFG_B0_P4_U0_CFG10 0x4001084a +#define CYDEV_UCFG_B0_P4_U0_CFG11 0x4001084b +#define CYDEV_UCFG_B0_P4_U0_CFG12 0x4001084c +#define CYDEV_UCFG_B0_P4_U0_CFG13 0x4001084d +#define CYDEV_UCFG_B0_P4_U0_CFG14 0x4001084e +#define CYDEV_UCFG_B0_P4_U0_CFG15 0x4001084f +#define CYDEV_UCFG_B0_P4_U0_CFG16 0x40010850 +#define CYDEV_UCFG_B0_P4_U0_CFG17 0x40010851 +#define CYDEV_UCFG_B0_P4_U0_CFG18 0x40010852 +#define CYDEV_UCFG_B0_P4_U0_CFG19 0x40010853 +#define CYDEV_UCFG_B0_P4_U0_CFG20 0x40010854 +#define CYDEV_UCFG_B0_P4_U0_CFG21 0x40010855 +#define CYDEV_UCFG_B0_P4_U0_CFG22 0x40010856 +#define CYDEV_UCFG_B0_P4_U0_CFG23 0x40010857 +#define CYDEV_UCFG_B0_P4_U0_CFG24 0x40010858 +#define CYDEV_UCFG_B0_P4_U0_CFG25 0x40010859 +#define CYDEV_UCFG_B0_P4_U0_CFG26 0x4001085a +#define CYDEV_UCFG_B0_P4_U0_CFG27 0x4001085b +#define CYDEV_UCFG_B0_P4_U0_CFG28 0x4001085c +#define CYDEV_UCFG_B0_P4_U0_CFG29 0x4001085d +#define CYDEV_UCFG_B0_P4_U0_CFG30 0x4001085e +#define CYDEV_UCFG_B0_P4_U0_CFG31 0x4001085f +#define CYDEV_UCFG_B0_P4_U0_DCFG0 0x40010860 +#define CYDEV_UCFG_B0_P4_U0_DCFG1 0x40010862 +#define CYDEV_UCFG_B0_P4_U0_DCFG2 0x40010864 +#define CYDEV_UCFG_B0_P4_U0_DCFG3 0x40010866 +#define CYDEV_UCFG_B0_P4_U0_DCFG4 0x40010868 +#define CYDEV_UCFG_B0_P4_U0_DCFG5 0x4001086a +#define CYDEV_UCFG_B0_P4_U0_DCFG6 0x4001086c +#define CYDEV_UCFG_B0_P4_U0_DCFG7 0x4001086e +#define CYDEV_UCFG_B0_P4_U1_BASE 0x40010880 +#define CYDEV_UCFG_B0_P4_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT0 0x40010880 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT1 0x40010884 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT2 0x40010888 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT3 0x4001088c +#define CYDEV_UCFG_B0_P4_U1_PLD_IT4 0x40010890 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT5 0x40010894 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT6 0x40010898 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT7 0x4001089c +#define CYDEV_UCFG_B0_P4_U1_PLD_IT8 0x400108a0 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT9 0x400108a4 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT10 0x400108a8 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT11 0x400108ac +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT0 0x400108b0 +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT1 0x400108b2 +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT2 0x400108b4 +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT3 0x400108b6 +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST 0x400108b8 +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB 0x400108ba +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET 0x400108bc +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS 0x400108be +#define CYDEV_UCFG_B0_P4_U1_CFG0 0x400108c0 +#define CYDEV_UCFG_B0_P4_U1_CFG1 0x400108c1 +#define CYDEV_UCFG_B0_P4_U1_CFG2 0x400108c2 +#define CYDEV_UCFG_B0_P4_U1_CFG3 0x400108c3 +#define CYDEV_UCFG_B0_P4_U1_CFG4 0x400108c4 +#define CYDEV_UCFG_B0_P4_U1_CFG5 0x400108c5 +#define CYDEV_UCFG_B0_P4_U1_CFG6 0x400108c6 +#define CYDEV_UCFG_B0_P4_U1_CFG7 0x400108c7 +#define CYDEV_UCFG_B0_P4_U1_CFG8 0x400108c8 +#define CYDEV_UCFG_B0_P4_U1_CFG9 0x400108c9 +#define CYDEV_UCFG_B0_P4_U1_CFG10 0x400108ca +#define CYDEV_UCFG_B0_P4_U1_CFG11 0x400108cb +#define CYDEV_UCFG_B0_P4_U1_CFG12 0x400108cc +#define CYDEV_UCFG_B0_P4_U1_CFG13 0x400108cd +#define CYDEV_UCFG_B0_P4_U1_CFG14 0x400108ce +#define CYDEV_UCFG_B0_P4_U1_CFG15 0x400108cf +#define CYDEV_UCFG_B0_P4_U1_CFG16 0x400108d0 +#define CYDEV_UCFG_B0_P4_U1_CFG17 0x400108d1 +#define CYDEV_UCFG_B0_P4_U1_CFG18 0x400108d2 +#define CYDEV_UCFG_B0_P4_U1_CFG19 0x400108d3 +#define CYDEV_UCFG_B0_P4_U1_CFG20 0x400108d4 +#define CYDEV_UCFG_B0_P4_U1_CFG21 0x400108d5 +#define CYDEV_UCFG_B0_P4_U1_CFG22 0x400108d6 +#define CYDEV_UCFG_B0_P4_U1_CFG23 0x400108d7 +#define CYDEV_UCFG_B0_P4_U1_CFG24 0x400108d8 +#define CYDEV_UCFG_B0_P4_U1_CFG25 0x400108d9 +#define CYDEV_UCFG_B0_P4_U1_CFG26 0x400108da +#define CYDEV_UCFG_B0_P4_U1_CFG27 0x400108db +#define CYDEV_UCFG_B0_P4_U1_CFG28 0x400108dc +#define CYDEV_UCFG_B0_P4_U1_CFG29 0x400108dd +#define CYDEV_UCFG_B0_P4_U1_CFG30 0x400108de +#define CYDEV_UCFG_B0_P4_U1_CFG31 0x400108df +#define CYDEV_UCFG_B0_P4_U1_DCFG0 0x400108e0 +#define CYDEV_UCFG_B0_P4_U1_DCFG1 0x400108e2 +#define CYDEV_UCFG_B0_P4_U1_DCFG2 0x400108e4 +#define CYDEV_UCFG_B0_P4_U1_DCFG3 0x400108e6 +#define CYDEV_UCFG_B0_P4_U1_DCFG4 0x400108e8 +#define CYDEV_UCFG_B0_P4_U1_DCFG5 0x400108ea +#define CYDEV_UCFG_B0_P4_U1_DCFG6 0x400108ec +#define CYDEV_UCFG_B0_P4_U1_DCFG7 0x400108ee +#define CYDEV_UCFG_B0_P4_ROUTE_BASE 0x40010900 +#define CYDEV_UCFG_B0_P4_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P5_BASE 0x40010a00 +#define CYDEV_UCFG_B0_P5_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P5_U0_BASE 0x40010a00 +#define CYDEV_UCFG_B0_P5_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT0 0x40010a00 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT1 0x40010a04 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT2 0x40010a08 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT3 0x40010a0c +#define CYDEV_UCFG_B0_P5_U0_PLD_IT4 0x40010a10 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT5 0x40010a14 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT6 0x40010a18 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT7 0x40010a1c +#define CYDEV_UCFG_B0_P5_U0_PLD_IT8 0x40010a20 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT9 0x40010a24 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT10 0x40010a28 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT11 0x40010a2c +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT0 0x40010a30 +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT1 0x40010a32 +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT2 0x40010a34 +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT3 0x40010a36 +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST 0x40010a38 +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB 0x40010a3a +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET 0x40010a3c +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS 0x40010a3e +#define CYDEV_UCFG_B0_P5_U0_CFG0 0x40010a40 +#define CYDEV_UCFG_B0_P5_U0_CFG1 0x40010a41 +#define CYDEV_UCFG_B0_P5_U0_CFG2 0x40010a42 +#define CYDEV_UCFG_B0_P5_U0_CFG3 0x40010a43 +#define CYDEV_UCFG_B0_P5_U0_CFG4 0x40010a44 +#define CYDEV_UCFG_B0_P5_U0_CFG5 0x40010a45 +#define CYDEV_UCFG_B0_P5_U0_CFG6 0x40010a46 +#define CYDEV_UCFG_B0_P5_U0_CFG7 0x40010a47 +#define CYDEV_UCFG_B0_P5_U0_CFG8 0x40010a48 +#define CYDEV_UCFG_B0_P5_U0_CFG9 0x40010a49 +#define CYDEV_UCFG_B0_P5_U0_CFG10 0x40010a4a +#define CYDEV_UCFG_B0_P5_U0_CFG11 0x40010a4b +#define CYDEV_UCFG_B0_P5_U0_CFG12 0x40010a4c +#define CYDEV_UCFG_B0_P5_U0_CFG13 0x40010a4d +#define CYDEV_UCFG_B0_P5_U0_CFG14 0x40010a4e +#define CYDEV_UCFG_B0_P5_U0_CFG15 0x40010a4f +#define CYDEV_UCFG_B0_P5_U0_CFG16 0x40010a50 +#define CYDEV_UCFG_B0_P5_U0_CFG17 0x40010a51 +#define CYDEV_UCFG_B0_P5_U0_CFG18 0x40010a52 +#define CYDEV_UCFG_B0_P5_U0_CFG19 0x40010a53 +#define CYDEV_UCFG_B0_P5_U0_CFG20 0x40010a54 +#define CYDEV_UCFG_B0_P5_U0_CFG21 0x40010a55 +#define CYDEV_UCFG_B0_P5_U0_CFG22 0x40010a56 +#define CYDEV_UCFG_B0_P5_U0_CFG23 0x40010a57 +#define CYDEV_UCFG_B0_P5_U0_CFG24 0x40010a58 +#define CYDEV_UCFG_B0_P5_U0_CFG25 0x40010a59 +#define CYDEV_UCFG_B0_P5_U0_CFG26 0x40010a5a +#define CYDEV_UCFG_B0_P5_U0_CFG27 0x40010a5b +#define CYDEV_UCFG_B0_P5_U0_CFG28 0x40010a5c +#define CYDEV_UCFG_B0_P5_U0_CFG29 0x40010a5d +#define CYDEV_UCFG_B0_P5_U0_CFG30 0x40010a5e +#define CYDEV_UCFG_B0_P5_U0_CFG31 0x40010a5f +#define CYDEV_UCFG_B0_P5_U0_DCFG0 0x40010a60 +#define CYDEV_UCFG_B0_P5_U0_DCFG1 0x40010a62 +#define CYDEV_UCFG_B0_P5_U0_DCFG2 0x40010a64 +#define CYDEV_UCFG_B0_P5_U0_DCFG3 0x40010a66 +#define CYDEV_UCFG_B0_P5_U0_DCFG4 0x40010a68 +#define CYDEV_UCFG_B0_P5_U0_DCFG5 0x40010a6a +#define CYDEV_UCFG_B0_P5_U0_DCFG6 0x40010a6c +#define CYDEV_UCFG_B0_P5_U0_DCFG7 0x40010a6e +#define CYDEV_UCFG_B0_P5_U1_BASE 0x40010a80 +#define CYDEV_UCFG_B0_P5_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT0 0x40010a80 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT1 0x40010a84 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT2 0x40010a88 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT3 0x40010a8c +#define CYDEV_UCFG_B0_P5_U1_PLD_IT4 0x40010a90 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT5 0x40010a94 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT6 0x40010a98 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT7 0x40010a9c +#define CYDEV_UCFG_B0_P5_U1_PLD_IT8 0x40010aa0 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT9 0x40010aa4 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT10 0x40010aa8 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT11 0x40010aac +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT0 0x40010ab0 +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT1 0x40010ab2 +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT2 0x40010ab4 +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT3 0x40010ab6 +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST 0x40010ab8 +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB 0x40010aba +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET 0x40010abc +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS 0x40010abe +#define CYDEV_UCFG_B0_P5_U1_CFG0 0x40010ac0 +#define CYDEV_UCFG_B0_P5_U1_CFG1 0x40010ac1 +#define CYDEV_UCFG_B0_P5_U1_CFG2 0x40010ac2 +#define CYDEV_UCFG_B0_P5_U1_CFG3 0x40010ac3 +#define CYDEV_UCFG_B0_P5_U1_CFG4 0x40010ac4 +#define CYDEV_UCFG_B0_P5_U1_CFG5 0x40010ac5 +#define CYDEV_UCFG_B0_P5_U1_CFG6 0x40010ac6 +#define CYDEV_UCFG_B0_P5_U1_CFG7 0x40010ac7 +#define CYDEV_UCFG_B0_P5_U1_CFG8 0x40010ac8 +#define CYDEV_UCFG_B0_P5_U1_CFG9 0x40010ac9 +#define CYDEV_UCFG_B0_P5_U1_CFG10 0x40010aca +#define CYDEV_UCFG_B0_P5_U1_CFG11 0x40010acb +#define CYDEV_UCFG_B0_P5_U1_CFG12 0x40010acc +#define CYDEV_UCFG_B0_P5_U1_CFG13 0x40010acd +#define CYDEV_UCFG_B0_P5_U1_CFG14 0x40010ace +#define CYDEV_UCFG_B0_P5_U1_CFG15 0x40010acf +#define CYDEV_UCFG_B0_P5_U1_CFG16 0x40010ad0 +#define CYDEV_UCFG_B0_P5_U1_CFG17 0x40010ad1 +#define CYDEV_UCFG_B0_P5_U1_CFG18 0x40010ad2 +#define CYDEV_UCFG_B0_P5_U1_CFG19 0x40010ad3 +#define CYDEV_UCFG_B0_P5_U1_CFG20 0x40010ad4 +#define CYDEV_UCFG_B0_P5_U1_CFG21 0x40010ad5 +#define CYDEV_UCFG_B0_P5_U1_CFG22 0x40010ad6 +#define CYDEV_UCFG_B0_P5_U1_CFG23 0x40010ad7 +#define CYDEV_UCFG_B0_P5_U1_CFG24 0x40010ad8 +#define CYDEV_UCFG_B0_P5_U1_CFG25 0x40010ad9 +#define CYDEV_UCFG_B0_P5_U1_CFG26 0x40010ada +#define CYDEV_UCFG_B0_P5_U1_CFG27 0x40010adb +#define CYDEV_UCFG_B0_P5_U1_CFG28 0x40010adc +#define CYDEV_UCFG_B0_P5_U1_CFG29 0x40010add +#define CYDEV_UCFG_B0_P5_U1_CFG30 0x40010ade +#define CYDEV_UCFG_B0_P5_U1_CFG31 0x40010adf +#define CYDEV_UCFG_B0_P5_U1_DCFG0 0x40010ae0 +#define CYDEV_UCFG_B0_P5_U1_DCFG1 0x40010ae2 +#define CYDEV_UCFG_B0_P5_U1_DCFG2 0x40010ae4 +#define CYDEV_UCFG_B0_P5_U1_DCFG3 0x40010ae6 +#define CYDEV_UCFG_B0_P5_U1_DCFG4 0x40010ae8 +#define CYDEV_UCFG_B0_P5_U1_DCFG5 0x40010aea +#define CYDEV_UCFG_B0_P5_U1_DCFG6 0x40010aec +#define CYDEV_UCFG_B0_P5_U1_DCFG7 0x40010aee +#define CYDEV_UCFG_B0_P5_ROUTE_BASE 0x40010b00 +#define CYDEV_UCFG_B0_P5_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P6_BASE 0x40010c00 +#define CYDEV_UCFG_B0_P6_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P6_U0_BASE 0x40010c00 +#define CYDEV_UCFG_B0_P6_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT0 0x40010c00 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT1 0x40010c04 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT2 0x40010c08 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT3 0x40010c0c +#define CYDEV_UCFG_B0_P6_U0_PLD_IT4 0x40010c10 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT5 0x40010c14 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT6 0x40010c18 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT7 0x40010c1c +#define CYDEV_UCFG_B0_P6_U0_PLD_IT8 0x40010c20 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT9 0x40010c24 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT10 0x40010c28 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT11 0x40010c2c +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT0 0x40010c30 +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT1 0x40010c32 +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT2 0x40010c34 +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT3 0x40010c36 +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST 0x40010c38 +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB 0x40010c3a +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET 0x40010c3c +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS 0x40010c3e +#define CYDEV_UCFG_B0_P6_U0_CFG0 0x40010c40 +#define CYDEV_UCFG_B0_P6_U0_CFG1 0x40010c41 +#define CYDEV_UCFG_B0_P6_U0_CFG2 0x40010c42 +#define CYDEV_UCFG_B0_P6_U0_CFG3 0x40010c43 +#define CYDEV_UCFG_B0_P6_U0_CFG4 0x40010c44 +#define CYDEV_UCFG_B0_P6_U0_CFG5 0x40010c45 +#define CYDEV_UCFG_B0_P6_U0_CFG6 0x40010c46 +#define CYDEV_UCFG_B0_P6_U0_CFG7 0x40010c47 +#define CYDEV_UCFG_B0_P6_U0_CFG8 0x40010c48 +#define CYDEV_UCFG_B0_P6_U0_CFG9 0x40010c49 +#define CYDEV_UCFG_B0_P6_U0_CFG10 0x40010c4a +#define CYDEV_UCFG_B0_P6_U0_CFG11 0x40010c4b +#define CYDEV_UCFG_B0_P6_U0_CFG12 0x40010c4c +#define CYDEV_UCFG_B0_P6_U0_CFG13 0x40010c4d +#define CYDEV_UCFG_B0_P6_U0_CFG14 0x40010c4e +#define CYDEV_UCFG_B0_P6_U0_CFG15 0x40010c4f +#define CYDEV_UCFG_B0_P6_U0_CFG16 0x40010c50 +#define CYDEV_UCFG_B0_P6_U0_CFG17 0x40010c51 +#define CYDEV_UCFG_B0_P6_U0_CFG18 0x40010c52 +#define CYDEV_UCFG_B0_P6_U0_CFG19 0x40010c53 +#define CYDEV_UCFG_B0_P6_U0_CFG20 0x40010c54 +#define CYDEV_UCFG_B0_P6_U0_CFG21 0x40010c55 +#define CYDEV_UCFG_B0_P6_U0_CFG22 0x40010c56 +#define CYDEV_UCFG_B0_P6_U0_CFG23 0x40010c57 +#define CYDEV_UCFG_B0_P6_U0_CFG24 0x40010c58 +#define CYDEV_UCFG_B0_P6_U0_CFG25 0x40010c59 +#define CYDEV_UCFG_B0_P6_U0_CFG26 0x40010c5a +#define CYDEV_UCFG_B0_P6_U0_CFG27 0x40010c5b +#define CYDEV_UCFG_B0_P6_U0_CFG28 0x40010c5c +#define CYDEV_UCFG_B0_P6_U0_CFG29 0x40010c5d +#define CYDEV_UCFG_B0_P6_U0_CFG30 0x40010c5e +#define CYDEV_UCFG_B0_P6_U0_CFG31 0x40010c5f +#define CYDEV_UCFG_B0_P6_U0_DCFG0 0x40010c60 +#define CYDEV_UCFG_B0_P6_U0_DCFG1 0x40010c62 +#define CYDEV_UCFG_B0_P6_U0_DCFG2 0x40010c64 +#define CYDEV_UCFG_B0_P6_U0_DCFG3 0x40010c66 +#define CYDEV_UCFG_B0_P6_U0_DCFG4 0x40010c68 +#define CYDEV_UCFG_B0_P6_U0_DCFG5 0x40010c6a +#define CYDEV_UCFG_B0_P6_U0_DCFG6 0x40010c6c +#define CYDEV_UCFG_B0_P6_U0_DCFG7 0x40010c6e +#define CYDEV_UCFG_B0_P6_U1_BASE 0x40010c80 +#define CYDEV_UCFG_B0_P6_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT0 0x40010c80 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT1 0x40010c84 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT2 0x40010c88 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT3 0x40010c8c +#define CYDEV_UCFG_B0_P6_U1_PLD_IT4 0x40010c90 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT5 0x40010c94 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT6 0x40010c98 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT7 0x40010c9c +#define CYDEV_UCFG_B0_P6_U1_PLD_IT8 0x40010ca0 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT9 0x40010ca4 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT10 0x40010ca8 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT11 0x40010cac +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT0 0x40010cb0 +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT1 0x40010cb2 +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT2 0x40010cb4 +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT3 0x40010cb6 +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST 0x40010cb8 +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB 0x40010cba +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET 0x40010cbc +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS 0x40010cbe +#define CYDEV_UCFG_B0_P6_U1_CFG0 0x40010cc0 +#define CYDEV_UCFG_B0_P6_U1_CFG1 0x40010cc1 +#define CYDEV_UCFG_B0_P6_U1_CFG2 0x40010cc2 +#define CYDEV_UCFG_B0_P6_U1_CFG3 0x40010cc3 +#define CYDEV_UCFG_B0_P6_U1_CFG4 0x40010cc4 +#define CYDEV_UCFG_B0_P6_U1_CFG5 0x40010cc5 +#define CYDEV_UCFG_B0_P6_U1_CFG6 0x40010cc6 +#define CYDEV_UCFG_B0_P6_U1_CFG7 0x40010cc7 +#define CYDEV_UCFG_B0_P6_U1_CFG8 0x40010cc8 +#define CYDEV_UCFG_B0_P6_U1_CFG9 0x40010cc9 +#define CYDEV_UCFG_B0_P6_U1_CFG10 0x40010cca +#define CYDEV_UCFG_B0_P6_U1_CFG11 0x40010ccb +#define CYDEV_UCFG_B0_P6_U1_CFG12 0x40010ccc +#define CYDEV_UCFG_B0_P6_U1_CFG13 0x40010ccd +#define CYDEV_UCFG_B0_P6_U1_CFG14 0x40010cce +#define CYDEV_UCFG_B0_P6_U1_CFG15 0x40010ccf +#define CYDEV_UCFG_B0_P6_U1_CFG16 0x40010cd0 +#define CYDEV_UCFG_B0_P6_U1_CFG17 0x40010cd1 +#define CYDEV_UCFG_B0_P6_U1_CFG18 0x40010cd2 +#define CYDEV_UCFG_B0_P6_U1_CFG19 0x40010cd3 +#define CYDEV_UCFG_B0_P6_U1_CFG20 0x40010cd4 +#define CYDEV_UCFG_B0_P6_U1_CFG21 0x40010cd5 +#define CYDEV_UCFG_B0_P6_U1_CFG22 0x40010cd6 +#define CYDEV_UCFG_B0_P6_U1_CFG23 0x40010cd7 +#define CYDEV_UCFG_B0_P6_U1_CFG24 0x40010cd8 +#define CYDEV_UCFG_B0_P6_U1_CFG25 0x40010cd9 +#define CYDEV_UCFG_B0_P6_U1_CFG26 0x40010cda +#define CYDEV_UCFG_B0_P6_U1_CFG27 0x40010cdb +#define CYDEV_UCFG_B0_P6_U1_CFG28 0x40010cdc +#define CYDEV_UCFG_B0_P6_U1_CFG29 0x40010cdd +#define CYDEV_UCFG_B0_P6_U1_CFG30 0x40010cde +#define CYDEV_UCFG_B0_P6_U1_CFG31 0x40010cdf +#define CYDEV_UCFG_B0_P6_U1_DCFG0 0x40010ce0 +#define CYDEV_UCFG_B0_P6_U1_DCFG1 0x40010ce2 +#define CYDEV_UCFG_B0_P6_U1_DCFG2 0x40010ce4 +#define CYDEV_UCFG_B0_P6_U1_DCFG3 0x40010ce6 +#define CYDEV_UCFG_B0_P6_U1_DCFG4 0x40010ce8 +#define CYDEV_UCFG_B0_P6_U1_DCFG5 0x40010cea +#define CYDEV_UCFG_B0_P6_U1_DCFG6 0x40010cec +#define CYDEV_UCFG_B0_P6_U1_DCFG7 0x40010cee +#define CYDEV_UCFG_B0_P6_ROUTE_BASE 0x40010d00 +#define CYDEV_UCFG_B0_P6_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P7_BASE 0x40010e00 +#define CYDEV_UCFG_B0_P7_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P7_U0_BASE 0x40010e00 +#define CYDEV_UCFG_B0_P7_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT0 0x40010e00 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT1 0x40010e04 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT2 0x40010e08 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT3 0x40010e0c +#define CYDEV_UCFG_B0_P7_U0_PLD_IT4 0x40010e10 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT5 0x40010e14 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT6 0x40010e18 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT7 0x40010e1c +#define CYDEV_UCFG_B0_P7_U0_PLD_IT8 0x40010e20 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT9 0x40010e24 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT10 0x40010e28 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT11 0x40010e2c +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT0 0x40010e30 +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT1 0x40010e32 +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT2 0x40010e34 +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT3 0x40010e36 +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST 0x40010e38 +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB 0x40010e3a +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET 0x40010e3c +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS 0x40010e3e +#define CYDEV_UCFG_B0_P7_U0_CFG0 0x40010e40 +#define CYDEV_UCFG_B0_P7_U0_CFG1 0x40010e41 +#define CYDEV_UCFG_B0_P7_U0_CFG2 0x40010e42 +#define CYDEV_UCFG_B0_P7_U0_CFG3 0x40010e43 +#define CYDEV_UCFG_B0_P7_U0_CFG4 0x40010e44 +#define CYDEV_UCFG_B0_P7_U0_CFG5 0x40010e45 +#define CYDEV_UCFG_B0_P7_U0_CFG6 0x40010e46 +#define CYDEV_UCFG_B0_P7_U0_CFG7 0x40010e47 +#define CYDEV_UCFG_B0_P7_U0_CFG8 0x40010e48 +#define CYDEV_UCFG_B0_P7_U0_CFG9 0x40010e49 +#define CYDEV_UCFG_B0_P7_U0_CFG10 0x40010e4a +#define CYDEV_UCFG_B0_P7_U0_CFG11 0x40010e4b +#define CYDEV_UCFG_B0_P7_U0_CFG12 0x40010e4c +#define CYDEV_UCFG_B0_P7_U0_CFG13 0x40010e4d +#define CYDEV_UCFG_B0_P7_U0_CFG14 0x40010e4e +#define CYDEV_UCFG_B0_P7_U0_CFG15 0x40010e4f +#define CYDEV_UCFG_B0_P7_U0_CFG16 0x40010e50 +#define CYDEV_UCFG_B0_P7_U0_CFG17 0x40010e51 +#define CYDEV_UCFG_B0_P7_U0_CFG18 0x40010e52 +#define CYDEV_UCFG_B0_P7_U0_CFG19 0x40010e53 +#define CYDEV_UCFG_B0_P7_U0_CFG20 0x40010e54 +#define CYDEV_UCFG_B0_P7_U0_CFG21 0x40010e55 +#define CYDEV_UCFG_B0_P7_U0_CFG22 0x40010e56 +#define CYDEV_UCFG_B0_P7_U0_CFG23 0x40010e57 +#define CYDEV_UCFG_B0_P7_U0_CFG24 0x40010e58 +#define CYDEV_UCFG_B0_P7_U0_CFG25 0x40010e59 +#define CYDEV_UCFG_B0_P7_U0_CFG26 0x40010e5a +#define CYDEV_UCFG_B0_P7_U0_CFG27 0x40010e5b +#define CYDEV_UCFG_B0_P7_U0_CFG28 0x40010e5c +#define CYDEV_UCFG_B0_P7_U0_CFG29 0x40010e5d +#define CYDEV_UCFG_B0_P7_U0_CFG30 0x40010e5e +#define CYDEV_UCFG_B0_P7_U0_CFG31 0x40010e5f +#define CYDEV_UCFG_B0_P7_U0_DCFG0 0x40010e60 +#define CYDEV_UCFG_B0_P7_U0_DCFG1 0x40010e62 +#define CYDEV_UCFG_B0_P7_U0_DCFG2 0x40010e64 +#define CYDEV_UCFG_B0_P7_U0_DCFG3 0x40010e66 +#define CYDEV_UCFG_B0_P7_U0_DCFG4 0x40010e68 +#define CYDEV_UCFG_B0_P7_U0_DCFG5 0x40010e6a +#define CYDEV_UCFG_B0_P7_U0_DCFG6 0x40010e6c +#define CYDEV_UCFG_B0_P7_U0_DCFG7 0x40010e6e +#define CYDEV_UCFG_B0_P7_U1_BASE 0x40010e80 +#define CYDEV_UCFG_B0_P7_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT0 0x40010e80 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT1 0x40010e84 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT2 0x40010e88 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT3 0x40010e8c +#define CYDEV_UCFG_B0_P7_U1_PLD_IT4 0x40010e90 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT5 0x40010e94 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT6 0x40010e98 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT7 0x40010e9c +#define CYDEV_UCFG_B0_P7_U1_PLD_IT8 0x40010ea0 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT9 0x40010ea4 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT10 0x40010ea8 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT11 0x40010eac +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT0 0x40010eb0 +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT1 0x40010eb2 +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT2 0x40010eb4 +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT3 0x40010eb6 +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST 0x40010eb8 +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB 0x40010eba +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET 0x40010ebc +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS 0x40010ebe +#define CYDEV_UCFG_B0_P7_U1_CFG0 0x40010ec0 +#define CYDEV_UCFG_B0_P7_U1_CFG1 0x40010ec1 +#define CYDEV_UCFG_B0_P7_U1_CFG2 0x40010ec2 +#define CYDEV_UCFG_B0_P7_U1_CFG3 0x40010ec3 +#define CYDEV_UCFG_B0_P7_U1_CFG4 0x40010ec4 +#define CYDEV_UCFG_B0_P7_U1_CFG5 0x40010ec5 +#define CYDEV_UCFG_B0_P7_U1_CFG6 0x40010ec6 +#define CYDEV_UCFG_B0_P7_U1_CFG7 0x40010ec7 +#define CYDEV_UCFG_B0_P7_U1_CFG8 0x40010ec8 +#define CYDEV_UCFG_B0_P7_U1_CFG9 0x40010ec9 +#define CYDEV_UCFG_B0_P7_U1_CFG10 0x40010eca +#define CYDEV_UCFG_B0_P7_U1_CFG11 0x40010ecb +#define CYDEV_UCFG_B0_P7_U1_CFG12 0x40010ecc +#define CYDEV_UCFG_B0_P7_U1_CFG13 0x40010ecd +#define CYDEV_UCFG_B0_P7_U1_CFG14 0x40010ece +#define CYDEV_UCFG_B0_P7_U1_CFG15 0x40010ecf +#define CYDEV_UCFG_B0_P7_U1_CFG16 0x40010ed0 +#define CYDEV_UCFG_B0_P7_U1_CFG17 0x40010ed1 +#define CYDEV_UCFG_B0_P7_U1_CFG18 0x40010ed2 +#define CYDEV_UCFG_B0_P7_U1_CFG19 0x40010ed3 +#define CYDEV_UCFG_B0_P7_U1_CFG20 0x40010ed4 +#define CYDEV_UCFG_B0_P7_U1_CFG21 0x40010ed5 +#define CYDEV_UCFG_B0_P7_U1_CFG22 0x40010ed6 +#define CYDEV_UCFG_B0_P7_U1_CFG23 0x40010ed7 +#define CYDEV_UCFG_B0_P7_U1_CFG24 0x40010ed8 +#define CYDEV_UCFG_B0_P7_U1_CFG25 0x40010ed9 +#define CYDEV_UCFG_B0_P7_U1_CFG26 0x40010eda +#define CYDEV_UCFG_B0_P7_U1_CFG27 0x40010edb +#define CYDEV_UCFG_B0_P7_U1_CFG28 0x40010edc +#define CYDEV_UCFG_B0_P7_U1_CFG29 0x40010edd +#define CYDEV_UCFG_B0_P7_U1_CFG30 0x40010ede +#define CYDEV_UCFG_B0_P7_U1_CFG31 0x40010edf +#define CYDEV_UCFG_B0_P7_U1_DCFG0 0x40010ee0 +#define CYDEV_UCFG_B0_P7_U1_DCFG1 0x40010ee2 +#define CYDEV_UCFG_B0_P7_U1_DCFG2 0x40010ee4 +#define CYDEV_UCFG_B0_P7_U1_DCFG3 0x40010ee6 +#define CYDEV_UCFG_B0_P7_U1_DCFG4 0x40010ee8 +#define CYDEV_UCFG_B0_P7_U1_DCFG5 0x40010eea +#define CYDEV_UCFG_B0_P7_U1_DCFG6 0x40010eec +#define CYDEV_UCFG_B0_P7_U1_DCFG7 0x40010eee +#define CYDEV_UCFG_B0_P7_ROUTE_BASE 0x40010f00 +#define CYDEV_UCFG_B0_P7_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B1_BASE 0x40011000 +#define CYDEV_UCFG_B1_SIZE 0x00000fef +#define CYDEV_UCFG_B1_P2_BASE 0x40011400 +#define CYDEV_UCFG_B1_P2_SIZE 0x000001ef +#define CYDEV_UCFG_B1_P2_U0_BASE 0x40011400 +#define CYDEV_UCFG_B1_P2_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT0 0x40011400 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT1 0x40011404 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT2 0x40011408 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT3 0x4001140c +#define CYDEV_UCFG_B1_P2_U0_PLD_IT4 0x40011410 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT5 0x40011414 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT6 0x40011418 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT7 0x4001141c +#define CYDEV_UCFG_B1_P2_U0_PLD_IT8 0x40011420 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT9 0x40011424 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT10 0x40011428 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT11 0x4001142c +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT0 0x40011430 +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT1 0x40011432 +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT2 0x40011434 +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT3 0x40011436 +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST 0x40011438 +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB 0x4001143a +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET 0x4001143c +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS 0x4001143e +#define CYDEV_UCFG_B1_P2_U0_CFG0 0x40011440 +#define CYDEV_UCFG_B1_P2_U0_CFG1 0x40011441 +#define CYDEV_UCFG_B1_P2_U0_CFG2 0x40011442 +#define CYDEV_UCFG_B1_P2_U0_CFG3 0x40011443 +#define CYDEV_UCFG_B1_P2_U0_CFG4 0x40011444 +#define CYDEV_UCFG_B1_P2_U0_CFG5 0x40011445 +#define CYDEV_UCFG_B1_P2_U0_CFG6 0x40011446 +#define CYDEV_UCFG_B1_P2_U0_CFG7 0x40011447 +#define CYDEV_UCFG_B1_P2_U0_CFG8 0x40011448 +#define CYDEV_UCFG_B1_P2_U0_CFG9 0x40011449 +#define CYDEV_UCFG_B1_P2_U0_CFG10 0x4001144a +#define CYDEV_UCFG_B1_P2_U0_CFG11 0x4001144b +#define CYDEV_UCFG_B1_P2_U0_CFG12 0x4001144c +#define CYDEV_UCFG_B1_P2_U0_CFG13 0x4001144d +#define CYDEV_UCFG_B1_P2_U0_CFG14 0x4001144e +#define CYDEV_UCFG_B1_P2_U0_CFG15 0x4001144f +#define CYDEV_UCFG_B1_P2_U0_CFG16 0x40011450 +#define CYDEV_UCFG_B1_P2_U0_CFG17 0x40011451 +#define CYDEV_UCFG_B1_P2_U0_CFG18 0x40011452 +#define CYDEV_UCFG_B1_P2_U0_CFG19 0x40011453 +#define CYDEV_UCFG_B1_P2_U0_CFG20 0x40011454 +#define CYDEV_UCFG_B1_P2_U0_CFG21 0x40011455 +#define CYDEV_UCFG_B1_P2_U0_CFG22 0x40011456 +#define CYDEV_UCFG_B1_P2_U0_CFG23 0x40011457 +#define CYDEV_UCFG_B1_P2_U0_CFG24 0x40011458 +#define CYDEV_UCFG_B1_P2_U0_CFG25 0x40011459 +#define CYDEV_UCFG_B1_P2_U0_CFG26 0x4001145a +#define CYDEV_UCFG_B1_P2_U0_CFG27 0x4001145b +#define CYDEV_UCFG_B1_P2_U0_CFG28 0x4001145c +#define CYDEV_UCFG_B1_P2_U0_CFG29 0x4001145d +#define CYDEV_UCFG_B1_P2_U0_CFG30 0x4001145e +#define CYDEV_UCFG_B1_P2_U0_CFG31 0x4001145f +#define CYDEV_UCFG_B1_P2_U0_DCFG0 0x40011460 +#define CYDEV_UCFG_B1_P2_U0_DCFG1 0x40011462 +#define CYDEV_UCFG_B1_P2_U0_DCFG2 0x40011464 +#define CYDEV_UCFG_B1_P2_U0_DCFG3 0x40011466 +#define CYDEV_UCFG_B1_P2_U0_DCFG4 0x40011468 +#define CYDEV_UCFG_B1_P2_U0_DCFG5 0x4001146a +#define CYDEV_UCFG_B1_P2_U0_DCFG6 0x4001146c +#define CYDEV_UCFG_B1_P2_U0_DCFG7 0x4001146e +#define CYDEV_UCFG_B1_P2_U1_BASE 0x40011480 +#define CYDEV_UCFG_B1_P2_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT0 0x40011480 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT1 0x40011484 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT2 0x40011488 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT3 0x4001148c +#define CYDEV_UCFG_B1_P2_U1_PLD_IT4 0x40011490 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT5 0x40011494 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT6 0x40011498 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT7 0x4001149c +#define CYDEV_UCFG_B1_P2_U1_PLD_IT8 0x400114a0 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT9 0x400114a4 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT10 0x400114a8 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT11 0x400114ac +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT0 0x400114b0 +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT1 0x400114b2 +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT2 0x400114b4 +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT3 0x400114b6 +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST 0x400114b8 +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB 0x400114ba +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET 0x400114bc +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS 0x400114be +#define CYDEV_UCFG_B1_P2_U1_CFG0 0x400114c0 +#define CYDEV_UCFG_B1_P2_U1_CFG1 0x400114c1 +#define CYDEV_UCFG_B1_P2_U1_CFG2 0x400114c2 +#define CYDEV_UCFG_B1_P2_U1_CFG3 0x400114c3 +#define CYDEV_UCFG_B1_P2_U1_CFG4 0x400114c4 +#define CYDEV_UCFG_B1_P2_U1_CFG5 0x400114c5 +#define CYDEV_UCFG_B1_P2_U1_CFG6 0x400114c6 +#define CYDEV_UCFG_B1_P2_U1_CFG7 0x400114c7 +#define CYDEV_UCFG_B1_P2_U1_CFG8 0x400114c8 +#define CYDEV_UCFG_B1_P2_U1_CFG9 0x400114c9 +#define CYDEV_UCFG_B1_P2_U1_CFG10 0x400114ca +#define CYDEV_UCFG_B1_P2_U1_CFG11 0x400114cb +#define CYDEV_UCFG_B1_P2_U1_CFG12 0x400114cc +#define CYDEV_UCFG_B1_P2_U1_CFG13 0x400114cd +#define CYDEV_UCFG_B1_P2_U1_CFG14 0x400114ce +#define CYDEV_UCFG_B1_P2_U1_CFG15 0x400114cf +#define CYDEV_UCFG_B1_P2_U1_CFG16 0x400114d0 +#define CYDEV_UCFG_B1_P2_U1_CFG17 0x400114d1 +#define CYDEV_UCFG_B1_P2_U1_CFG18 0x400114d2 +#define CYDEV_UCFG_B1_P2_U1_CFG19 0x400114d3 +#define CYDEV_UCFG_B1_P2_U1_CFG20 0x400114d4 +#define CYDEV_UCFG_B1_P2_U1_CFG21 0x400114d5 +#define CYDEV_UCFG_B1_P2_U1_CFG22 0x400114d6 +#define CYDEV_UCFG_B1_P2_U1_CFG23 0x400114d7 +#define CYDEV_UCFG_B1_P2_U1_CFG24 0x400114d8 +#define CYDEV_UCFG_B1_P2_U1_CFG25 0x400114d9 +#define CYDEV_UCFG_B1_P2_U1_CFG26 0x400114da +#define CYDEV_UCFG_B1_P2_U1_CFG27 0x400114db +#define CYDEV_UCFG_B1_P2_U1_CFG28 0x400114dc +#define CYDEV_UCFG_B1_P2_U1_CFG29 0x400114dd +#define CYDEV_UCFG_B1_P2_U1_CFG30 0x400114de +#define CYDEV_UCFG_B1_P2_U1_CFG31 0x400114df +#define CYDEV_UCFG_B1_P2_U1_DCFG0 0x400114e0 +#define CYDEV_UCFG_B1_P2_U1_DCFG1 0x400114e2 +#define CYDEV_UCFG_B1_P2_U1_DCFG2 0x400114e4 +#define CYDEV_UCFG_B1_P2_U1_DCFG3 0x400114e6 +#define CYDEV_UCFG_B1_P2_U1_DCFG4 0x400114e8 +#define CYDEV_UCFG_B1_P2_U1_DCFG5 0x400114ea +#define CYDEV_UCFG_B1_P2_U1_DCFG6 0x400114ec +#define CYDEV_UCFG_B1_P2_U1_DCFG7 0x400114ee +#define CYDEV_UCFG_B1_P2_ROUTE_BASE 0x40011500 +#define CYDEV_UCFG_B1_P2_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B1_P3_BASE 0x40011600 +#define CYDEV_UCFG_B1_P3_SIZE 0x000001ef +#define CYDEV_UCFG_B1_P3_U0_BASE 0x40011600 +#define CYDEV_UCFG_B1_P3_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT0 0x40011600 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT1 0x40011604 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT2 0x40011608 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT3 0x4001160c +#define CYDEV_UCFG_B1_P3_U0_PLD_IT4 0x40011610 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT5 0x40011614 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT6 0x40011618 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT7 0x4001161c +#define CYDEV_UCFG_B1_P3_U0_PLD_IT8 0x40011620 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT9 0x40011624 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT10 0x40011628 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT11 0x4001162c +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT0 0x40011630 +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT1 0x40011632 +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT2 0x40011634 +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT3 0x40011636 +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST 0x40011638 +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB 0x4001163a +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET 0x4001163c +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS 0x4001163e +#define CYDEV_UCFG_B1_P3_U0_CFG0 0x40011640 +#define CYDEV_UCFG_B1_P3_U0_CFG1 0x40011641 +#define CYDEV_UCFG_B1_P3_U0_CFG2 0x40011642 +#define CYDEV_UCFG_B1_P3_U0_CFG3 0x40011643 +#define CYDEV_UCFG_B1_P3_U0_CFG4 0x40011644 +#define CYDEV_UCFG_B1_P3_U0_CFG5 0x40011645 +#define CYDEV_UCFG_B1_P3_U0_CFG6 0x40011646 +#define CYDEV_UCFG_B1_P3_U0_CFG7 0x40011647 +#define CYDEV_UCFG_B1_P3_U0_CFG8 0x40011648 +#define CYDEV_UCFG_B1_P3_U0_CFG9 0x40011649 +#define CYDEV_UCFG_B1_P3_U0_CFG10 0x4001164a +#define CYDEV_UCFG_B1_P3_U0_CFG11 0x4001164b +#define CYDEV_UCFG_B1_P3_U0_CFG12 0x4001164c +#define CYDEV_UCFG_B1_P3_U0_CFG13 0x4001164d +#define CYDEV_UCFG_B1_P3_U0_CFG14 0x4001164e +#define CYDEV_UCFG_B1_P3_U0_CFG15 0x4001164f +#define CYDEV_UCFG_B1_P3_U0_CFG16 0x40011650 +#define CYDEV_UCFG_B1_P3_U0_CFG17 0x40011651 +#define CYDEV_UCFG_B1_P3_U0_CFG18 0x40011652 +#define CYDEV_UCFG_B1_P3_U0_CFG19 0x40011653 +#define CYDEV_UCFG_B1_P3_U0_CFG20 0x40011654 +#define CYDEV_UCFG_B1_P3_U0_CFG21 0x40011655 +#define CYDEV_UCFG_B1_P3_U0_CFG22 0x40011656 +#define CYDEV_UCFG_B1_P3_U0_CFG23 0x40011657 +#define CYDEV_UCFG_B1_P3_U0_CFG24 0x40011658 +#define CYDEV_UCFG_B1_P3_U0_CFG25 0x40011659 +#define CYDEV_UCFG_B1_P3_U0_CFG26 0x4001165a +#define CYDEV_UCFG_B1_P3_U0_CFG27 0x4001165b +#define CYDEV_UCFG_B1_P3_U0_CFG28 0x4001165c +#define CYDEV_UCFG_B1_P3_U0_CFG29 0x4001165d +#define CYDEV_UCFG_B1_P3_U0_CFG30 0x4001165e +#define CYDEV_UCFG_B1_P3_U0_CFG31 0x4001165f +#define CYDEV_UCFG_B1_P3_U0_DCFG0 0x40011660 +#define CYDEV_UCFG_B1_P3_U0_DCFG1 0x40011662 +#define CYDEV_UCFG_B1_P3_U0_DCFG2 0x40011664 +#define CYDEV_UCFG_B1_P3_U0_DCFG3 0x40011666 +#define CYDEV_UCFG_B1_P3_U0_DCFG4 0x40011668 +#define CYDEV_UCFG_B1_P3_U0_DCFG5 0x4001166a +#define CYDEV_UCFG_B1_P3_U0_DCFG6 0x4001166c +#define CYDEV_UCFG_B1_P3_U0_DCFG7 0x4001166e +#define CYDEV_UCFG_B1_P3_U1_BASE 0x40011680 +#define CYDEV_UCFG_B1_P3_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT0 0x40011680 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT1 0x40011684 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT2 0x40011688 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT3 0x4001168c +#define CYDEV_UCFG_B1_P3_U1_PLD_IT4 0x40011690 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT5 0x40011694 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT6 0x40011698 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT7 0x4001169c +#define CYDEV_UCFG_B1_P3_U1_PLD_IT8 0x400116a0 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT9 0x400116a4 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT10 0x400116a8 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT11 0x400116ac +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT0 0x400116b0 +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT1 0x400116b2 +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT2 0x400116b4 +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT3 0x400116b6 +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST 0x400116b8 +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB 0x400116ba +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET 0x400116bc +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS 0x400116be +#define CYDEV_UCFG_B1_P3_U1_CFG0 0x400116c0 +#define CYDEV_UCFG_B1_P3_U1_CFG1 0x400116c1 +#define CYDEV_UCFG_B1_P3_U1_CFG2 0x400116c2 +#define CYDEV_UCFG_B1_P3_U1_CFG3 0x400116c3 +#define CYDEV_UCFG_B1_P3_U1_CFG4 0x400116c4 +#define CYDEV_UCFG_B1_P3_U1_CFG5 0x400116c5 +#define CYDEV_UCFG_B1_P3_U1_CFG6 0x400116c6 +#define CYDEV_UCFG_B1_P3_U1_CFG7 0x400116c7 +#define CYDEV_UCFG_B1_P3_U1_CFG8 0x400116c8 +#define CYDEV_UCFG_B1_P3_U1_CFG9 0x400116c9 +#define CYDEV_UCFG_B1_P3_U1_CFG10 0x400116ca +#define CYDEV_UCFG_B1_P3_U1_CFG11 0x400116cb +#define CYDEV_UCFG_B1_P3_U1_CFG12 0x400116cc +#define CYDEV_UCFG_B1_P3_U1_CFG13 0x400116cd +#define CYDEV_UCFG_B1_P3_U1_CFG14 0x400116ce +#define CYDEV_UCFG_B1_P3_U1_CFG15 0x400116cf +#define CYDEV_UCFG_B1_P3_U1_CFG16 0x400116d0 +#define CYDEV_UCFG_B1_P3_U1_CFG17 0x400116d1 +#define CYDEV_UCFG_B1_P3_U1_CFG18 0x400116d2 +#define CYDEV_UCFG_B1_P3_U1_CFG19 0x400116d3 +#define CYDEV_UCFG_B1_P3_U1_CFG20 0x400116d4 +#define CYDEV_UCFG_B1_P3_U1_CFG21 0x400116d5 +#define CYDEV_UCFG_B1_P3_U1_CFG22 0x400116d6 +#define CYDEV_UCFG_B1_P3_U1_CFG23 0x400116d7 +#define CYDEV_UCFG_B1_P3_U1_CFG24 0x400116d8 +#define CYDEV_UCFG_B1_P3_U1_CFG25 0x400116d9 +#define CYDEV_UCFG_B1_P3_U1_CFG26 0x400116da +#define CYDEV_UCFG_B1_P3_U1_CFG27 0x400116db +#define CYDEV_UCFG_B1_P3_U1_CFG28 0x400116dc +#define CYDEV_UCFG_B1_P3_U1_CFG29 0x400116dd +#define CYDEV_UCFG_B1_P3_U1_CFG30 0x400116de +#define CYDEV_UCFG_B1_P3_U1_CFG31 0x400116df +#define CYDEV_UCFG_B1_P3_U1_DCFG0 0x400116e0 +#define CYDEV_UCFG_B1_P3_U1_DCFG1 0x400116e2 +#define CYDEV_UCFG_B1_P3_U1_DCFG2 0x400116e4 +#define CYDEV_UCFG_B1_P3_U1_DCFG3 0x400116e6 +#define CYDEV_UCFG_B1_P3_U1_DCFG4 0x400116e8 +#define CYDEV_UCFG_B1_P3_U1_DCFG5 0x400116ea +#define CYDEV_UCFG_B1_P3_U1_DCFG6 0x400116ec +#define CYDEV_UCFG_B1_P3_U1_DCFG7 0x400116ee +#define CYDEV_UCFG_B1_P3_ROUTE_BASE 0x40011700 +#define CYDEV_UCFG_B1_P3_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B1_P4_BASE 0x40011800 +#define CYDEV_UCFG_B1_P4_SIZE 0x000001ef +#define CYDEV_UCFG_B1_P4_U0_BASE 0x40011800 +#define CYDEV_UCFG_B1_P4_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT0 0x40011800 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT1 0x40011804 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT2 0x40011808 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT3 0x4001180c +#define CYDEV_UCFG_B1_P4_U0_PLD_IT4 0x40011810 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT5 0x40011814 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT6 0x40011818 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT7 0x4001181c +#define CYDEV_UCFG_B1_P4_U0_PLD_IT8 0x40011820 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT9 0x40011824 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT10 0x40011828 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT11 0x4001182c +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT0 0x40011830 +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT1 0x40011832 +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT2 0x40011834 +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT3 0x40011836 +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST 0x40011838 +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB 0x4001183a +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET 0x4001183c +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS 0x4001183e +#define CYDEV_UCFG_B1_P4_U0_CFG0 0x40011840 +#define CYDEV_UCFG_B1_P4_U0_CFG1 0x40011841 +#define CYDEV_UCFG_B1_P4_U0_CFG2 0x40011842 +#define CYDEV_UCFG_B1_P4_U0_CFG3 0x40011843 +#define CYDEV_UCFG_B1_P4_U0_CFG4 0x40011844 +#define CYDEV_UCFG_B1_P4_U0_CFG5 0x40011845 +#define CYDEV_UCFG_B1_P4_U0_CFG6 0x40011846 +#define CYDEV_UCFG_B1_P4_U0_CFG7 0x40011847 +#define CYDEV_UCFG_B1_P4_U0_CFG8 0x40011848 +#define CYDEV_UCFG_B1_P4_U0_CFG9 0x40011849 +#define CYDEV_UCFG_B1_P4_U0_CFG10 0x4001184a +#define CYDEV_UCFG_B1_P4_U0_CFG11 0x4001184b +#define CYDEV_UCFG_B1_P4_U0_CFG12 0x4001184c +#define CYDEV_UCFG_B1_P4_U0_CFG13 0x4001184d +#define CYDEV_UCFG_B1_P4_U0_CFG14 0x4001184e +#define CYDEV_UCFG_B1_P4_U0_CFG15 0x4001184f +#define CYDEV_UCFG_B1_P4_U0_CFG16 0x40011850 +#define CYDEV_UCFG_B1_P4_U0_CFG17 0x40011851 +#define CYDEV_UCFG_B1_P4_U0_CFG18 0x40011852 +#define CYDEV_UCFG_B1_P4_U0_CFG19 0x40011853 +#define CYDEV_UCFG_B1_P4_U0_CFG20 0x40011854 +#define CYDEV_UCFG_B1_P4_U0_CFG21 0x40011855 +#define CYDEV_UCFG_B1_P4_U0_CFG22 0x40011856 +#define CYDEV_UCFG_B1_P4_U0_CFG23 0x40011857 +#define CYDEV_UCFG_B1_P4_U0_CFG24 0x40011858 +#define CYDEV_UCFG_B1_P4_U0_CFG25 0x40011859 +#define CYDEV_UCFG_B1_P4_U0_CFG26 0x4001185a +#define CYDEV_UCFG_B1_P4_U0_CFG27 0x4001185b +#define CYDEV_UCFG_B1_P4_U0_CFG28 0x4001185c +#define CYDEV_UCFG_B1_P4_U0_CFG29 0x4001185d +#define CYDEV_UCFG_B1_P4_U0_CFG30 0x4001185e +#define CYDEV_UCFG_B1_P4_U0_CFG31 0x4001185f +#define CYDEV_UCFG_B1_P4_U0_DCFG0 0x40011860 +#define CYDEV_UCFG_B1_P4_U0_DCFG1 0x40011862 +#define CYDEV_UCFG_B1_P4_U0_DCFG2 0x40011864 +#define CYDEV_UCFG_B1_P4_U0_DCFG3 0x40011866 +#define CYDEV_UCFG_B1_P4_U0_DCFG4 0x40011868 +#define CYDEV_UCFG_B1_P4_U0_DCFG5 0x4001186a +#define CYDEV_UCFG_B1_P4_U0_DCFG6 0x4001186c +#define CYDEV_UCFG_B1_P4_U0_DCFG7 0x4001186e +#define CYDEV_UCFG_B1_P4_U1_BASE 0x40011880 +#define CYDEV_UCFG_B1_P4_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT0 0x40011880 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT1 0x40011884 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT2 0x40011888 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT3 0x4001188c +#define CYDEV_UCFG_B1_P4_U1_PLD_IT4 0x40011890 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT5 0x40011894 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT6 0x40011898 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT7 0x4001189c +#define CYDEV_UCFG_B1_P4_U1_PLD_IT8 0x400118a0 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT9 0x400118a4 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT10 0x400118a8 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT11 0x400118ac +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT0 0x400118b0 +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT1 0x400118b2 +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT2 0x400118b4 +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT3 0x400118b6 +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST 0x400118b8 +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB 0x400118ba +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET 0x400118bc +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS 0x400118be +#define CYDEV_UCFG_B1_P4_U1_CFG0 0x400118c0 +#define CYDEV_UCFG_B1_P4_U1_CFG1 0x400118c1 +#define CYDEV_UCFG_B1_P4_U1_CFG2 0x400118c2 +#define CYDEV_UCFG_B1_P4_U1_CFG3 0x400118c3 +#define CYDEV_UCFG_B1_P4_U1_CFG4 0x400118c4 +#define CYDEV_UCFG_B1_P4_U1_CFG5 0x400118c5 +#define CYDEV_UCFG_B1_P4_U1_CFG6 0x400118c6 +#define CYDEV_UCFG_B1_P4_U1_CFG7 0x400118c7 +#define CYDEV_UCFG_B1_P4_U1_CFG8 0x400118c8 +#define CYDEV_UCFG_B1_P4_U1_CFG9 0x400118c9 +#define CYDEV_UCFG_B1_P4_U1_CFG10 0x400118ca +#define CYDEV_UCFG_B1_P4_U1_CFG11 0x400118cb +#define CYDEV_UCFG_B1_P4_U1_CFG12 0x400118cc +#define CYDEV_UCFG_B1_P4_U1_CFG13 0x400118cd +#define CYDEV_UCFG_B1_P4_U1_CFG14 0x400118ce +#define CYDEV_UCFG_B1_P4_U1_CFG15 0x400118cf +#define CYDEV_UCFG_B1_P4_U1_CFG16 0x400118d0 +#define CYDEV_UCFG_B1_P4_U1_CFG17 0x400118d1 +#define CYDEV_UCFG_B1_P4_U1_CFG18 0x400118d2 +#define CYDEV_UCFG_B1_P4_U1_CFG19 0x400118d3 +#define CYDEV_UCFG_B1_P4_U1_CFG20 0x400118d4 +#define CYDEV_UCFG_B1_P4_U1_CFG21 0x400118d5 +#define CYDEV_UCFG_B1_P4_U1_CFG22 0x400118d6 +#define CYDEV_UCFG_B1_P4_U1_CFG23 0x400118d7 +#define CYDEV_UCFG_B1_P4_U1_CFG24 0x400118d8 +#define CYDEV_UCFG_B1_P4_U1_CFG25 0x400118d9 +#define CYDEV_UCFG_B1_P4_U1_CFG26 0x400118da +#define CYDEV_UCFG_B1_P4_U1_CFG27 0x400118db +#define CYDEV_UCFG_B1_P4_U1_CFG28 0x400118dc +#define CYDEV_UCFG_B1_P4_U1_CFG29 0x400118dd +#define CYDEV_UCFG_B1_P4_U1_CFG30 0x400118de +#define CYDEV_UCFG_B1_P4_U1_CFG31 0x400118df +#define CYDEV_UCFG_B1_P4_U1_DCFG0 0x400118e0 +#define CYDEV_UCFG_B1_P4_U1_DCFG1 0x400118e2 +#define CYDEV_UCFG_B1_P4_U1_DCFG2 0x400118e4 +#define CYDEV_UCFG_B1_P4_U1_DCFG3 0x400118e6 +#define CYDEV_UCFG_B1_P4_U1_DCFG4 0x400118e8 +#define CYDEV_UCFG_B1_P4_U1_DCFG5 0x400118ea +#define CYDEV_UCFG_B1_P4_U1_DCFG6 0x400118ec +#define CYDEV_UCFG_B1_P4_U1_DCFG7 0x400118ee +#define CYDEV_UCFG_B1_P4_ROUTE_BASE 0x40011900 +#define CYDEV_UCFG_B1_P4_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B1_P5_BASE 0x40011a00 +#define CYDEV_UCFG_B1_P5_SIZE 0x000001ef +#define CYDEV_UCFG_B1_P5_U0_BASE 0x40011a00 +#define CYDEV_UCFG_B1_P5_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT0 0x40011a00 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT1 0x40011a04 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT2 0x40011a08 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT3 0x40011a0c +#define CYDEV_UCFG_B1_P5_U0_PLD_IT4 0x40011a10 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT5 0x40011a14 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT6 0x40011a18 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT7 0x40011a1c +#define CYDEV_UCFG_B1_P5_U0_PLD_IT8 0x40011a20 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT9 0x40011a24 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT10 0x40011a28 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT11 0x40011a2c +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT0 0x40011a30 +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT1 0x40011a32 +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT2 0x40011a34 +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT3 0x40011a36 +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST 0x40011a38 +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB 0x40011a3a +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET 0x40011a3c +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS 0x40011a3e +#define CYDEV_UCFG_B1_P5_U0_CFG0 0x40011a40 +#define CYDEV_UCFG_B1_P5_U0_CFG1 0x40011a41 +#define CYDEV_UCFG_B1_P5_U0_CFG2 0x40011a42 +#define CYDEV_UCFG_B1_P5_U0_CFG3 0x40011a43 +#define CYDEV_UCFG_B1_P5_U0_CFG4 0x40011a44 +#define CYDEV_UCFG_B1_P5_U0_CFG5 0x40011a45 +#define CYDEV_UCFG_B1_P5_U0_CFG6 0x40011a46 +#define CYDEV_UCFG_B1_P5_U0_CFG7 0x40011a47 +#define CYDEV_UCFG_B1_P5_U0_CFG8 0x40011a48 +#define CYDEV_UCFG_B1_P5_U0_CFG9 0x40011a49 +#define CYDEV_UCFG_B1_P5_U0_CFG10 0x40011a4a +#define CYDEV_UCFG_B1_P5_U0_CFG11 0x40011a4b +#define CYDEV_UCFG_B1_P5_U0_CFG12 0x40011a4c +#define CYDEV_UCFG_B1_P5_U0_CFG13 0x40011a4d +#define CYDEV_UCFG_B1_P5_U0_CFG14 0x40011a4e +#define CYDEV_UCFG_B1_P5_U0_CFG15 0x40011a4f +#define CYDEV_UCFG_B1_P5_U0_CFG16 0x40011a50 +#define CYDEV_UCFG_B1_P5_U0_CFG17 0x40011a51 +#define CYDEV_UCFG_B1_P5_U0_CFG18 0x40011a52 +#define CYDEV_UCFG_B1_P5_U0_CFG19 0x40011a53 +#define CYDEV_UCFG_B1_P5_U0_CFG20 0x40011a54 +#define CYDEV_UCFG_B1_P5_U0_CFG21 0x40011a55 +#define CYDEV_UCFG_B1_P5_U0_CFG22 0x40011a56 +#define CYDEV_UCFG_B1_P5_U0_CFG23 0x40011a57 +#define CYDEV_UCFG_B1_P5_U0_CFG24 0x40011a58 +#define CYDEV_UCFG_B1_P5_U0_CFG25 0x40011a59 +#define CYDEV_UCFG_B1_P5_U0_CFG26 0x40011a5a +#define CYDEV_UCFG_B1_P5_U0_CFG27 0x40011a5b +#define CYDEV_UCFG_B1_P5_U0_CFG28 0x40011a5c +#define CYDEV_UCFG_B1_P5_U0_CFG29 0x40011a5d +#define CYDEV_UCFG_B1_P5_U0_CFG30 0x40011a5e +#define CYDEV_UCFG_B1_P5_U0_CFG31 0x40011a5f +#define CYDEV_UCFG_B1_P5_U0_DCFG0 0x40011a60 +#define CYDEV_UCFG_B1_P5_U0_DCFG1 0x40011a62 +#define CYDEV_UCFG_B1_P5_U0_DCFG2 0x40011a64 +#define CYDEV_UCFG_B1_P5_U0_DCFG3 0x40011a66 +#define CYDEV_UCFG_B1_P5_U0_DCFG4 0x40011a68 +#define CYDEV_UCFG_B1_P5_U0_DCFG5 0x40011a6a +#define CYDEV_UCFG_B1_P5_U0_DCFG6 0x40011a6c +#define CYDEV_UCFG_B1_P5_U0_DCFG7 0x40011a6e +#define CYDEV_UCFG_B1_P5_U1_BASE 0x40011a80 +#define CYDEV_UCFG_B1_P5_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT0 0x40011a80 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT1 0x40011a84 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT2 0x40011a88 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT3 0x40011a8c +#define CYDEV_UCFG_B1_P5_U1_PLD_IT4 0x40011a90 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT5 0x40011a94 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT6 0x40011a98 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT7 0x40011a9c +#define CYDEV_UCFG_B1_P5_U1_PLD_IT8 0x40011aa0 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT9 0x40011aa4 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT10 0x40011aa8 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT11 0x40011aac +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT0 0x40011ab0 +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT1 0x40011ab2 +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT2 0x40011ab4 +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT3 0x40011ab6 +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST 0x40011ab8 +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB 0x40011aba +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET 0x40011abc +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS 0x40011abe +#define CYDEV_UCFG_B1_P5_U1_CFG0 0x40011ac0 +#define CYDEV_UCFG_B1_P5_U1_CFG1 0x40011ac1 +#define CYDEV_UCFG_B1_P5_U1_CFG2 0x40011ac2 +#define CYDEV_UCFG_B1_P5_U1_CFG3 0x40011ac3 +#define CYDEV_UCFG_B1_P5_U1_CFG4 0x40011ac4 +#define CYDEV_UCFG_B1_P5_U1_CFG5 0x40011ac5 +#define CYDEV_UCFG_B1_P5_U1_CFG6 0x40011ac6 +#define CYDEV_UCFG_B1_P5_U1_CFG7 0x40011ac7 +#define CYDEV_UCFG_B1_P5_U1_CFG8 0x40011ac8 +#define CYDEV_UCFG_B1_P5_U1_CFG9 0x40011ac9 +#define CYDEV_UCFG_B1_P5_U1_CFG10 0x40011aca +#define CYDEV_UCFG_B1_P5_U1_CFG11 0x40011acb +#define CYDEV_UCFG_B1_P5_U1_CFG12 0x40011acc +#define CYDEV_UCFG_B1_P5_U1_CFG13 0x40011acd +#define CYDEV_UCFG_B1_P5_U1_CFG14 0x40011ace +#define CYDEV_UCFG_B1_P5_U1_CFG15 0x40011acf +#define CYDEV_UCFG_B1_P5_U1_CFG16 0x40011ad0 +#define CYDEV_UCFG_B1_P5_U1_CFG17 0x40011ad1 +#define CYDEV_UCFG_B1_P5_U1_CFG18 0x40011ad2 +#define CYDEV_UCFG_B1_P5_U1_CFG19 0x40011ad3 +#define CYDEV_UCFG_B1_P5_U1_CFG20 0x40011ad4 +#define CYDEV_UCFG_B1_P5_U1_CFG21 0x40011ad5 +#define CYDEV_UCFG_B1_P5_U1_CFG22 0x40011ad6 +#define CYDEV_UCFG_B1_P5_U1_CFG23 0x40011ad7 +#define CYDEV_UCFG_B1_P5_U1_CFG24 0x40011ad8 +#define CYDEV_UCFG_B1_P5_U1_CFG25 0x40011ad9 +#define CYDEV_UCFG_B1_P5_U1_CFG26 0x40011ada +#define CYDEV_UCFG_B1_P5_U1_CFG27 0x40011adb +#define CYDEV_UCFG_B1_P5_U1_CFG28 0x40011adc +#define CYDEV_UCFG_B1_P5_U1_CFG29 0x40011add +#define CYDEV_UCFG_B1_P5_U1_CFG30 0x40011ade +#define CYDEV_UCFG_B1_P5_U1_CFG31 0x40011adf +#define CYDEV_UCFG_B1_P5_U1_DCFG0 0x40011ae0 +#define CYDEV_UCFG_B1_P5_U1_DCFG1 0x40011ae2 +#define CYDEV_UCFG_B1_P5_U1_DCFG2 0x40011ae4 +#define CYDEV_UCFG_B1_P5_U1_DCFG3 0x40011ae6 +#define CYDEV_UCFG_B1_P5_U1_DCFG4 0x40011ae8 +#define CYDEV_UCFG_B1_P5_U1_DCFG5 0x40011aea +#define CYDEV_UCFG_B1_P5_U1_DCFG6 0x40011aec +#define CYDEV_UCFG_B1_P5_U1_DCFG7 0x40011aee +#define CYDEV_UCFG_B1_P5_ROUTE_BASE 0x40011b00 +#define CYDEV_UCFG_B1_P5_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_DSI0_BASE 0x40014000 +#define CYDEV_UCFG_DSI0_SIZE 0x000000ef +#define CYDEV_UCFG_DSI1_BASE 0x40014100 +#define CYDEV_UCFG_DSI1_SIZE 0x000000ef +#define CYDEV_UCFG_DSI2_BASE 0x40014200 +#define CYDEV_UCFG_DSI2_SIZE 0x000000ef +#define CYDEV_UCFG_DSI3_BASE 0x40014300 +#define CYDEV_UCFG_DSI3_SIZE 0x000000ef +#define CYDEV_UCFG_DSI4_BASE 0x40014400 +#define CYDEV_UCFG_DSI4_SIZE 0x000000ef +#define CYDEV_UCFG_DSI5_BASE 0x40014500 +#define CYDEV_UCFG_DSI5_SIZE 0x000000ef +#define CYDEV_UCFG_DSI6_BASE 0x40014600 +#define CYDEV_UCFG_DSI6_SIZE 0x000000ef +#define CYDEV_UCFG_DSI7_BASE 0x40014700 +#define CYDEV_UCFG_DSI7_SIZE 0x000000ef +#define CYDEV_UCFG_DSI8_BASE 0x40014800 +#define CYDEV_UCFG_DSI8_SIZE 0x000000ef +#define CYDEV_UCFG_DSI9_BASE 0x40014900 +#define CYDEV_UCFG_DSI9_SIZE 0x000000ef +#define CYDEV_UCFG_DSI12_BASE 0x40014c00 +#define CYDEV_UCFG_DSI12_SIZE 0x000000ef +#define CYDEV_UCFG_DSI13_BASE 0x40014d00 +#define CYDEV_UCFG_DSI13_SIZE 0x000000ef +#define CYDEV_UCFG_BCTL0_BASE 0x40015000 +#define CYDEV_UCFG_BCTL0_SIZE 0x00000010 +#define CYDEV_UCFG_BCTL0_MDCLK_EN 0x40015000 +#define CYDEV_UCFG_BCTL0_MBCLK_EN 0x40015001 +#define CYDEV_UCFG_BCTL0_WAIT_CFG 0x40015002 +#define CYDEV_UCFG_BCTL0_BANK_CTL 0x40015003 +#define CYDEV_UCFG_BCTL0_UDB_TEST_3 0x40015007 +#define CYDEV_UCFG_BCTL0_DCLK_EN0 0x40015008 +#define CYDEV_UCFG_BCTL0_BCLK_EN0 0x40015009 +#define CYDEV_UCFG_BCTL0_DCLK_EN1 0x4001500a +#define CYDEV_UCFG_BCTL0_BCLK_EN1 0x4001500b +#define CYDEV_UCFG_BCTL0_DCLK_EN2 0x4001500c +#define CYDEV_UCFG_BCTL0_BCLK_EN2 0x4001500d +#define CYDEV_UCFG_BCTL0_DCLK_EN3 0x4001500e +#define CYDEV_UCFG_BCTL0_BCLK_EN3 0x4001500f +#define CYDEV_UCFG_BCTL1_BASE 0x40015010 +#define CYDEV_UCFG_BCTL1_SIZE 0x00000010 +#define CYDEV_UCFG_BCTL1_MDCLK_EN 0x40015010 +#define CYDEV_UCFG_BCTL1_MBCLK_EN 0x40015011 +#define CYDEV_UCFG_BCTL1_WAIT_CFG 0x40015012 +#define CYDEV_UCFG_BCTL1_BANK_CTL 0x40015013 +#define CYDEV_UCFG_BCTL1_UDB_TEST_3 0x40015017 +#define CYDEV_UCFG_BCTL1_DCLK_EN0 0x40015018 +#define CYDEV_UCFG_BCTL1_BCLK_EN0 0x40015019 +#define CYDEV_UCFG_BCTL1_DCLK_EN1 0x4001501a +#define CYDEV_UCFG_BCTL1_BCLK_EN1 0x4001501b +#define CYDEV_UCFG_BCTL1_DCLK_EN2 0x4001501c +#define CYDEV_UCFG_BCTL1_BCLK_EN2 0x4001501d +#define CYDEV_UCFG_BCTL1_DCLK_EN3 0x4001501e +#define CYDEV_UCFG_BCTL1_BCLK_EN3 0x4001501f +#define CYDEV_IDMUX_BASE 0x40015100 +#define CYDEV_IDMUX_SIZE 0x00000016 +#define CYDEV_IDMUX_IRQ_CTL0 0x40015100 +#define CYDEV_IDMUX_IRQ_CTL1 0x40015101 +#define CYDEV_IDMUX_IRQ_CTL2 0x40015102 +#define CYDEV_IDMUX_IRQ_CTL3 0x40015103 +#define CYDEV_IDMUX_IRQ_CTL4 0x40015104 +#define CYDEV_IDMUX_IRQ_CTL5 0x40015105 +#define CYDEV_IDMUX_IRQ_CTL6 0x40015106 +#define CYDEV_IDMUX_IRQ_CTL7 0x40015107 +#define CYDEV_IDMUX_DRQ_CTL0 0x40015110 +#define CYDEV_IDMUX_DRQ_CTL1 0x40015111 +#define CYDEV_IDMUX_DRQ_CTL2 0x40015112 +#define CYDEV_IDMUX_DRQ_CTL3 0x40015113 +#define CYDEV_IDMUX_DRQ_CTL4 0x40015114 +#define CYDEV_IDMUX_DRQ_CTL5 0x40015115 +#define CYDEV_CACHERAM_BASE 0x40030000 +#define CYDEV_CACHERAM_SIZE 0x00000400 +#define CYDEV_CACHERAM_DATA_MBASE 0x40030000 +#define CYDEV_CACHERAM_DATA_MSIZE 0x00000400 +#define CYDEV_SFR_BASE 0x40050100 +#define CYDEV_SFR_SIZE 0x000000fb +#define CYDEV_SFR_GPIO0 0x40050180 +#define CYDEV_SFR_GPIRD0 0x40050189 +#define CYDEV_SFR_GPIO0_SEL 0x4005018a +#define CYDEV_SFR_GPIO1 0x40050190 +#define CYDEV_SFR_GPIRD1 0x40050191 +#define CYDEV_SFR_GPIO2 0x40050198 +#define CYDEV_SFR_GPIRD2 0x40050199 +#define CYDEV_SFR_GPIO2_SEL 0x4005019a +#define CYDEV_SFR_GPIO1_SEL 0x400501a2 +#define CYDEV_SFR_GPIO3 0x400501b0 +#define CYDEV_SFR_GPIRD3 0x400501b1 +#define CYDEV_SFR_GPIO3_SEL 0x400501b2 +#define CYDEV_SFR_GPIO4 0x400501c0 +#define CYDEV_SFR_GPIRD4 0x400501c1 +#define CYDEV_SFR_GPIO4_SEL 0x400501c2 +#define CYDEV_SFR_GPIO5 0x400501c8 +#define CYDEV_SFR_GPIRD5 0x400501c9 +#define CYDEV_SFR_GPIO5_SEL 0x400501ca +#define CYDEV_SFR_GPIO6 0x400501d8 +#define CYDEV_SFR_GPIRD6 0x400501d9 +#define CYDEV_SFR_GPIO6_SEL 0x400501da +#define CYDEV_SFR_GPIO12 0x400501e8 +#define CYDEV_SFR_GPIRD12 0x400501e9 +#define CYDEV_SFR_GPIO12_SEL 0x400501f2 +#define CYDEV_SFR_GPIO15 0x400501f8 +#define CYDEV_SFR_GPIRD15 0x400501f9 +#define CYDEV_SFR_GPIO15_SEL 0x400501fa +#define CYDEV_P3BA_BASE 0x40050300 +#define CYDEV_P3BA_SIZE 0x0000002b +#define CYDEV_P3BA_Y_START 0x40050300 +#define CYDEV_P3BA_YROLL 0x40050301 +#define CYDEV_P3BA_YCFG 0x40050302 +#define CYDEV_P3BA_X_START1 0x40050303 +#define CYDEV_P3BA_X_START2 0x40050304 +#define CYDEV_P3BA_XROLL1 0x40050305 +#define CYDEV_P3BA_XROLL2 0x40050306 +#define CYDEV_P3BA_XINC 0x40050307 +#define CYDEV_P3BA_XCFG 0x40050308 +#define CYDEV_P3BA_OFFSETADDR1 0x40050309 +#define CYDEV_P3BA_OFFSETADDR2 0x4005030a +#define CYDEV_P3BA_OFFSETADDR3 0x4005030b +#define CYDEV_P3BA_ABSADDR1 0x4005030c +#define CYDEV_P3BA_ABSADDR2 0x4005030d +#define CYDEV_P3BA_ABSADDR3 0x4005030e +#define CYDEV_P3BA_ABSADDR4 0x4005030f +#define CYDEV_P3BA_DATCFG1 0x40050310 +#define CYDEV_P3BA_DATCFG2 0x40050311 +#define CYDEV_P3BA_CMP_RSLT1 0x40050314 +#define CYDEV_P3BA_CMP_RSLT2 0x40050315 +#define CYDEV_P3BA_CMP_RSLT3 0x40050316 +#define CYDEV_P3BA_CMP_RSLT4 0x40050317 +#define CYDEV_P3BA_DATA_REG1 0x40050318 +#define CYDEV_P3BA_DATA_REG2 0x40050319 +#define CYDEV_P3BA_DATA_REG3 0x4005031a +#define CYDEV_P3BA_DATA_REG4 0x4005031b +#define CYDEV_P3BA_EXP_DATA1 0x4005031c +#define CYDEV_P3BA_EXP_DATA2 0x4005031d +#define CYDEV_P3BA_EXP_DATA3 0x4005031e +#define CYDEV_P3BA_EXP_DATA4 0x4005031f +#define CYDEV_P3BA_MSTR_HRDATA1 0x40050320 +#define CYDEV_P3BA_MSTR_HRDATA2 0x40050321 +#define CYDEV_P3BA_MSTR_HRDATA3 0x40050322 +#define CYDEV_P3BA_MSTR_HRDATA4 0x40050323 +#define CYDEV_P3BA_BIST_EN 0x40050324 +#define CYDEV_P3BA_PHUB_MASTER_SSR 0x40050325 +#define CYDEV_P3BA_SEQCFG1 0x40050326 +#define CYDEV_P3BA_SEQCFG2 0x40050327 +#define CYDEV_P3BA_Y_CURR 0x40050328 +#define CYDEV_P3BA_X_CURR1 0x40050329 +#define CYDEV_P3BA_X_CURR2 0x4005032a +#define CYDEV_PANTHER_BASE 0x40080000 +#define CYDEV_PANTHER_SIZE 0x00000020 +#define CYDEV_PANTHER_STCALIB_CFG 0x40080000 +#define CYDEV_PANTHER_WAITPIPE 0x40080004 +#define CYDEV_PANTHER_TRACE_CFG 0x40080008 +#define CYDEV_PANTHER_DBG_CFG 0x4008000c +#define CYDEV_PANTHER_CM3_LCKRST_STAT 0x40080018 +#define CYDEV_PANTHER_DEVICE_ID 0x4008001c +#define CYDEV_FLSECC_BASE 0x48000000 +#define CYDEV_FLSECC_SIZE 0x00008000 +#define CYDEV_FLSECC_DATA_MBASE 0x48000000 +#define CYDEV_FLSECC_DATA_MSIZE 0x00008000 +#define CYDEV_FLSHID_BASE 0x49000000 +#define CYDEV_FLSHID_SIZE 0x00000200 +#define CYDEV_FLSHID_RSVD_MBASE 0x49000000 +#define CYDEV_FLSHID_RSVD_MSIZE 0x00000080 +#define CYDEV_FLSHID_CUST_MDATA_MBASE 0x49000080 +#define CYDEV_FLSHID_CUST_MDATA_MSIZE 0x00000080 +#define CYDEV_FLSHID_CUST_TABLES_BASE 0x49000100 +#define CYDEV_FLSHID_CUST_TABLES_SIZE 0x00000040 +#define CYDEV_FLSHID_CUST_TABLES_Y_LOC 0x49000100 +#define CYDEV_FLSHID_CUST_TABLES_X_LOC 0x49000101 +#define CYDEV_FLSHID_CUST_TABLES_WAFER_NUM 0x49000102 +#define CYDEV_FLSHID_CUST_TABLES_LOT_LSB 0x49000103 +#define CYDEV_FLSHID_CUST_TABLES_LOT_MSB 0x49000104 +#define CYDEV_FLSHID_CUST_TABLES_WRK_WK 0x49000105 +#define CYDEV_FLSHID_CUST_TABLES_FAB_YR 0x49000106 +#define CYDEV_FLSHID_CUST_TABLES_MINOR 0x49000107 +#define CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ 0x49000108 +#define CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ 0x49000109 +#define CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ 0x4900010a +#define CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ 0x4900010b +#define CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ 0x4900010c +#define CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ 0x4900010d +#define CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ 0x4900010e +#define CYDEV_FLSHID_CUST_TABLES_IMO_USB 0x4900010f +#define CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS 0x49000110 +#define CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS 0x49000111 +#define CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS 0x49000112 +#define CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS 0x49000113 +#define CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS 0x49000114 +#define CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS 0x49000115 +#define CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS 0x49000116 +#define CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS 0x49000117 +#define CYDEV_FLSHID_CUST_TABLES_DEC_M1 0x49000118 +#define CYDEV_FLSHID_CUST_TABLES_DEC_M2 0x49000119 +#define CYDEV_FLSHID_CUST_TABLES_DEC_M3 0x4900011a +#define CYDEV_FLSHID_CUST_TABLES_DEC_M4 0x4900011b +#define CYDEV_FLSHID_CUST_TABLES_DEC_M5 0x4900011c +#define CYDEV_FLSHID_CUST_TABLES_DEC_M6 0x4900011d +#define CYDEV_FLSHID_CUST_TABLES_DEC_M7 0x4900011e +#define CYDEV_FLSHID_CUST_TABLES_DEC_M8 0x4900011f +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M1 0x49000120 +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M2 0x49000121 +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M3 0x49000122 +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M4 0x49000123 +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M5 0x49000124 +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M6 0x49000125 +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M7 0x49000126 +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M8 0x49000127 +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M1 0x49000128 +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M2 0x49000129 +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M3 0x4900012a +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M4 0x4900012b +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M5 0x4900012c +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M6 0x4900012d +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M7 0x4900012e +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M8 0x4900012f +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M1 0x49000130 +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M2 0x49000131 +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M3 0x49000132 +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M4 0x49000133 +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M5 0x49000134 +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M6 0x49000135 +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M7 0x49000136 +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M8 0x49000137 +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M1 0x49000138 +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M2 0x49000139 +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M3 0x4900013a +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M4 0x4900013b +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M5 0x4900013c +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M6 0x4900013d +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M7 0x4900013e +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M8 0x4900013f +#define CYDEV_FLSHID_MFG_CFG_BASE 0x49000180 +#define CYDEV_FLSHID_MFG_CFG_SIZE 0x00000080 +#define CYDEV_FLSHID_MFG_CFG_IMO_TR1 0x49000188 +#define CYDEV_FLSHID_MFG_CFG_CMP0_TR0 0x490001ac +#define CYDEV_FLSHID_MFG_CFG_CMP1_TR0 0x490001ae +#define CYDEV_FLSHID_MFG_CFG_CMP2_TR0 0x490001b0 +#define CYDEV_FLSHID_MFG_CFG_CMP3_TR0 0x490001b2 +#define CYDEV_FLSHID_MFG_CFG_CMP0_TR1 0x490001b4 +#define CYDEV_FLSHID_MFG_CFG_CMP1_TR1 0x490001b6 +#define CYDEV_FLSHID_MFG_CFG_CMP2_TR1 0x490001b8 +#define CYDEV_FLSHID_MFG_CFG_CMP3_TR1 0x490001ba +#define CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM 0x490001ce +#define CYDEV_EXTMEM_BASE 0x60000000 +#define CYDEV_EXTMEM_SIZE 0x00800000 +#define CYDEV_EXTMEM_DATA_MBASE 0x60000000 +#define CYDEV_EXTMEM_DATA_MSIZE 0x00800000 +#define CYDEV_ITM_BASE 0xe0000000 +#define CYDEV_ITM_SIZE 0x00001000 +#define CYDEV_ITM_TRACE_EN 0xe0000e00 +#define CYDEV_ITM_TRACE_PRIVILEGE 0xe0000e40 +#define CYDEV_ITM_TRACE_CTRL 0xe0000e80 +#define CYDEV_ITM_LOCK_ACCESS 0xe0000fb0 +#define CYDEV_ITM_LOCK_STATUS 0xe0000fb4 +#define CYDEV_ITM_PID4 0xe0000fd0 +#define CYDEV_ITM_PID5 0xe0000fd4 +#define CYDEV_ITM_PID6 0xe0000fd8 +#define CYDEV_ITM_PID7 0xe0000fdc +#define CYDEV_ITM_PID0 0xe0000fe0 +#define CYDEV_ITM_PID1 0xe0000fe4 +#define CYDEV_ITM_PID2 0xe0000fe8 +#define CYDEV_ITM_PID3 0xe0000fec +#define CYDEV_ITM_CID0 0xe0000ff0 +#define CYDEV_ITM_CID1 0xe0000ff4 +#define CYDEV_ITM_CID2 0xe0000ff8 +#define CYDEV_ITM_CID3 0xe0000ffc +#define CYDEV_DWT_BASE 0xe0001000 +#define CYDEV_DWT_SIZE 0x0000005c +#define CYDEV_DWT_CTRL 0xe0001000 +#define CYDEV_DWT_CYCLE_COUNT 0xe0001004 +#define CYDEV_DWT_CPI_COUNT 0xe0001008 +#define CYDEV_DWT_EXC_OVHD_COUNT 0xe000100c +#define CYDEV_DWT_SLEEP_COUNT 0xe0001010 +#define CYDEV_DWT_LSU_COUNT 0xe0001014 +#define CYDEV_DWT_FOLD_COUNT 0xe0001018 +#define CYDEV_DWT_PC_SAMPLE 0xe000101c +#define CYDEV_DWT_COMP_0 0xe0001020 +#define CYDEV_DWT_MASK_0 0xe0001024 +#define CYDEV_DWT_FUNCTION_0 0xe0001028 +#define CYDEV_DWT_COMP_1 0xe0001030 +#define CYDEV_DWT_MASK_1 0xe0001034 +#define CYDEV_DWT_FUNCTION_1 0xe0001038 +#define CYDEV_DWT_COMP_2 0xe0001040 +#define CYDEV_DWT_MASK_2 0xe0001044 +#define CYDEV_DWT_FUNCTION_2 0xe0001048 +#define CYDEV_DWT_COMP_3 0xe0001050 +#define CYDEV_DWT_MASK_3 0xe0001054 +#define CYDEV_DWT_FUNCTION_3 0xe0001058 +#define CYDEV_FPB_BASE 0xe0002000 +#define CYDEV_FPB_SIZE 0x00001000 +#define CYDEV_FPB_CTRL 0xe0002000 +#define CYDEV_FPB_REMAP 0xe0002004 +#define CYDEV_FPB_FP_COMP_0 0xe0002008 +#define CYDEV_FPB_FP_COMP_1 0xe000200c +#define CYDEV_FPB_FP_COMP_2 0xe0002010 +#define CYDEV_FPB_FP_COMP_3 0xe0002014 +#define CYDEV_FPB_FP_COMP_4 0xe0002018 +#define CYDEV_FPB_FP_COMP_5 0xe000201c +#define CYDEV_FPB_FP_COMP_6 0xe0002020 +#define CYDEV_FPB_FP_COMP_7 0xe0002024 +#define CYDEV_FPB_PID4 0xe0002fd0 +#define CYDEV_FPB_PID5 0xe0002fd4 +#define CYDEV_FPB_PID6 0xe0002fd8 +#define CYDEV_FPB_PID7 0xe0002fdc +#define CYDEV_FPB_PID0 0xe0002fe0 +#define CYDEV_FPB_PID1 0xe0002fe4 +#define CYDEV_FPB_PID2 0xe0002fe8 +#define CYDEV_FPB_PID3 0xe0002fec +#define CYDEV_FPB_CID0 0xe0002ff0 +#define CYDEV_FPB_CID1 0xe0002ff4 +#define CYDEV_FPB_CID2 0xe0002ff8 +#define CYDEV_FPB_CID3 0xe0002ffc +#define CYDEV_NVIC_BASE 0xe000e000 +#define CYDEV_NVIC_SIZE 0x00000d3c +#define CYDEV_NVIC_INT_CTL_TYPE 0xe000e004 +#define CYDEV_NVIC_SYSTICK_CTL 0xe000e010 +#define CYDEV_NVIC_SYSTICK_RELOAD 0xe000e014 +#define CYDEV_NVIC_SYSTICK_CURRENT 0xe000e018 +#define CYDEV_NVIC_SYSTICK_CAL 0xe000e01c +#define CYDEV_NVIC_SETENA0 0xe000e100 +#define CYDEV_NVIC_CLRENA0 0xe000e180 +#define CYDEV_NVIC_SETPEND0 0xe000e200 +#define CYDEV_NVIC_CLRPEND0 0xe000e280 +#define CYDEV_NVIC_ACTIVE0 0xe000e300 +#define CYDEV_NVIC_PRI_0 0xe000e400 +#define CYDEV_NVIC_PRI_1 0xe000e401 +#define CYDEV_NVIC_PRI_2 0xe000e402 +#define CYDEV_NVIC_PRI_3 0xe000e403 +#define CYDEV_NVIC_PRI_4 0xe000e404 +#define CYDEV_NVIC_PRI_5 0xe000e405 +#define CYDEV_NVIC_PRI_6 0xe000e406 +#define CYDEV_NVIC_PRI_7 0xe000e407 +#define CYDEV_NVIC_PRI_8 0xe000e408 +#define CYDEV_NVIC_PRI_9 0xe000e409 +#define CYDEV_NVIC_PRI_10 0xe000e40a +#define CYDEV_NVIC_PRI_11 0xe000e40b +#define CYDEV_NVIC_PRI_12 0xe000e40c +#define CYDEV_NVIC_PRI_13 0xe000e40d +#define CYDEV_NVIC_PRI_14 0xe000e40e +#define CYDEV_NVIC_PRI_15 0xe000e40f +#define CYDEV_NVIC_PRI_16 0xe000e410 +#define CYDEV_NVIC_PRI_17 0xe000e411 +#define CYDEV_NVIC_PRI_18 0xe000e412 +#define CYDEV_NVIC_PRI_19 0xe000e413 +#define CYDEV_NVIC_PRI_20 0xe000e414 +#define CYDEV_NVIC_PRI_21 0xe000e415 +#define CYDEV_NVIC_PRI_22 0xe000e416 +#define CYDEV_NVIC_PRI_23 0xe000e417 +#define CYDEV_NVIC_PRI_24 0xe000e418 +#define CYDEV_NVIC_PRI_25 0xe000e419 +#define CYDEV_NVIC_PRI_26 0xe000e41a +#define CYDEV_NVIC_PRI_27 0xe000e41b +#define CYDEV_NVIC_PRI_28 0xe000e41c +#define CYDEV_NVIC_PRI_29 0xe000e41d +#define CYDEV_NVIC_PRI_30 0xe000e41e +#define CYDEV_NVIC_PRI_31 0xe000e41f +#define CYDEV_NVIC_CPUID_BASE 0xe000ed00 +#define CYDEV_NVIC_INTR_CTRL_STATE 0xe000ed04 +#define CYDEV_NVIC_VECT_OFFSET 0xe000ed08 +#define CYDEV_NVIC_APPLN_INTR 0xe000ed0c +#define CYDEV_NVIC_SYSTEM_CONTROL 0xe000ed10 +#define CYDEV_NVIC_CFG_CONTROL 0xe000ed14 +#define CYDEV_NVIC_SYS_PRIO_HANDLER_4_7 0xe000ed18 +#define CYDEV_NVIC_SYS_PRIO_HANDLER_8_11 0xe000ed1c +#define CYDEV_NVIC_SYS_PRIO_HANDLER_12_15 0xe000ed20 +#define CYDEV_NVIC_SYS_HANDLER_CSR 0xe000ed24 +#define CYDEV_NVIC_MEMMAN_FAULT_STATUS 0xe000ed28 +#define CYDEV_NVIC_BUS_FAULT_STATUS 0xe000ed29 +#define CYDEV_NVIC_USAGE_FAULT_STATUS 0xe000ed2a +#define CYDEV_NVIC_HARD_FAULT_STATUS 0xe000ed2c +#define CYDEV_NVIC_DEBUG_FAULT_STATUS 0xe000ed30 +#define CYDEV_NVIC_MEMMAN_FAULT_ADD 0xe000ed34 +#define CYDEV_NVIC_BUS_FAULT_ADD 0xe000ed38 +#define CYDEV_CORE_DBG_BASE 0xe000edf0 +#define CYDEV_CORE_DBG_SIZE 0x00000010 +#define CYDEV_CORE_DBG_DBG_HLT_CS 0xe000edf0 +#define CYDEV_CORE_DBG_DBG_REG_SEL 0xe000edf4 +#define CYDEV_CORE_DBG_DBG_REG_DATA 0xe000edf8 +#define CYDEV_CORE_DBG_EXC_MON_CTL 0xe000edfc +#define CYDEV_TPIU_BASE 0xe0040000 +#define CYDEV_TPIU_SIZE 0x00001000 +#define CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ 0xe0040000 +#define CYDEV_TPIU_CURRENT_SYNC_PRT_SZ 0xe0040004 +#define CYDEV_TPIU_ASYNC_CLK_PRESCALER 0xe0040010 +#define CYDEV_TPIU_PROTOCOL 0xe00400f0 +#define CYDEV_TPIU_FORM_FLUSH_STAT 0xe0040300 +#define CYDEV_TPIU_FORM_FLUSH_CTRL 0xe0040304 +#define CYDEV_TPIU_TRIGGER 0xe0040ee8 +#define CYDEV_TPIU_ITETMDATA 0xe0040eec +#define CYDEV_TPIU_ITATBCTR2 0xe0040ef0 +#define CYDEV_TPIU_ITATBCTR0 0xe0040ef8 +#define CYDEV_TPIU_ITITMDATA 0xe0040efc +#define CYDEV_TPIU_ITCTRL 0xe0040f00 +#define CYDEV_TPIU_DEVID 0xe0040fc8 +#define CYDEV_TPIU_DEVTYPE 0xe0040fcc +#define CYDEV_TPIU_PID4 0xe0040fd0 +#define CYDEV_TPIU_PID5 0xe0040fd4 +#define CYDEV_TPIU_PID6 0xe0040fd8 +#define CYDEV_TPIU_PID7 0xe0040fdc +#define CYDEV_TPIU_PID0 0xe0040fe0 +#define CYDEV_TPIU_PID1 0xe0040fe4 +#define CYDEV_TPIU_PID2 0xe0040fe8 +#define CYDEV_TPIU_PID3 0xe0040fec +#define CYDEV_TPIU_CID0 0xe0040ff0 +#define CYDEV_TPIU_CID1 0xe0040ff4 +#define CYDEV_TPIU_CID2 0xe0040ff8 +#define CYDEV_TPIU_CID3 0xe0040ffc +#define CYDEV_ETM_BASE 0xe0041000 +#define CYDEV_ETM_SIZE 0x00001000 +#define CYDEV_ETM_CTL 0xe0041000 +#define CYDEV_ETM_CFG_CODE 0xe0041004 +#define CYDEV_ETM_TRIG_EVENT 0xe0041008 +#define CYDEV_ETM_STATUS 0xe0041010 +#define CYDEV_ETM_SYS_CFG 0xe0041014 +#define CYDEV_ETM_TRACE_ENB_EVENT 0xe0041020 +#define CYDEV_ETM_TRACE_EN_CTRL1 0xe0041024 +#define CYDEV_ETM_FIFOFULL_LEVEL 0xe004102c +#define CYDEV_ETM_SYNC_FREQ 0xe00411e0 +#define CYDEV_ETM_ETM_ID 0xe00411e4 +#define CYDEV_ETM_CFG_CODE_EXT 0xe00411e8 +#define CYDEV_ETM_TR_SS_EMBICE_CTRL 0xe00411f0 +#define CYDEV_ETM_CS_TRACE_ID 0xe0041200 +#define CYDEV_ETM_OS_LOCK_ACCESS 0xe0041300 +#define CYDEV_ETM_OS_LOCK_STATUS 0xe0041304 +#define CYDEV_ETM_PDSR 0xe0041314 +#define CYDEV_ETM_ITMISCIN 0xe0041ee0 +#define CYDEV_ETM_ITTRIGOUT 0xe0041ee8 +#define CYDEV_ETM_ITATBCTR2 0xe0041ef0 +#define CYDEV_ETM_ITATBCTR0 0xe0041ef8 +#define CYDEV_ETM_INT_MODE_CTRL 0xe0041f00 +#define CYDEV_ETM_CLM_TAG_SET 0xe0041fa0 +#define CYDEV_ETM_CLM_TAG_CLR 0xe0041fa4 +#define CYDEV_ETM_LOCK_ACCESS 0xe0041fb0 +#define CYDEV_ETM_LOCK_STATUS 0xe0041fb4 +#define CYDEV_ETM_AUTH_STATUS 0xe0041fb8 +#define CYDEV_ETM_DEV_TYPE 0xe0041fcc +#define CYDEV_ETM_PID4 0xe0041fd0 +#define CYDEV_ETM_PID5 0xe0041fd4 +#define CYDEV_ETM_PID6 0xe0041fd8 +#define CYDEV_ETM_PID7 0xe0041fdc +#define CYDEV_ETM_PID0 0xe0041fe0 +#define CYDEV_ETM_PID1 0xe0041fe4 +#define CYDEV_ETM_PID2 0xe0041fe8 +#define CYDEV_ETM_PID3 0xe0041fec +#define CYDEV_ETM_CID0 0xe0041ff0 +#define CYDEV_ETM_CID1 0xe0041ff4 +#define CYDEV_ETM_CID2 0xe0041ff8 +#define CYDEV_ETM_CID3 0xe0041ffc +#define CYDEV_ROM_TABLE_BASE 0xe00ff000 +#define CYDEV_ROM_TABLE_SIZE 0x00001000 +#define CYDEV_ROM_TABLE_NVIC 0xe00ff000 +#define CYDEV_ROM_TABLE_DWT 0xe00ff004 +#define CYDEV_ROM_TABLE_FPB 0xe00ff008 +#define CYDEV_ROM_TABLE_ITM 0xe00ff00c +#define CYDEV_ROM_TABLE_TPIU 0xe00ff010 +#define CYDEV_ROM_TABLE_ETM 0xe00ff014 +#define CYDEV_ROM_TABLE_END 0xe00ff018 +#define CYDEV_ROM_TABLE_MEMTYPE 0xe00fffcc +#define CYDEV_ROM_TABLE_PID4 0xe00fffd0 +#define CYDEV_ROM_TABLE_PID5 0xe00fffd4 +#define CYDEV_ROM_TABLE_PID6 0xe00fffd8 +#define CYDEV_ROM_TABLE_PID7 0xe00fffdc +#define CYDEV_ROM_TABLE_PID0 0xe00fffe0 +#define CYDEV_ROM_TABLE_PID1 0xe00fffe4 +#define CYDEV_ROM_TABLE_PID2 0xe00fffe8 +#define CYDEV_ROM_TABLE_PID3 0xe00fffec +#define CYDEV_ROM_TABLE_CID0 0xe00ffff0 +#define CYDEV_ROM_TABLE_CID1 0xe00ffff4 +#define CYDEV_ROM_TABLE_CID2 0xe00ffff8 +#define CYDEV_ROM_TABLE_CID3 0xe00ffffc +#define CYDEV_FLS_SIZE CYDEV_FLASH_SIZE +#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE +#define CYDEV_FLS_SECTOR_SIZE 0x00010000 +#define CYDEV_FLS_ROW_SIZE 0x00000100 +#define CYDEV_ECC_SECTOR_SIZE 0x00002000 +#define CYDEV_ECC_ROW_SIZE 0x00000020 +#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400 +#define CYDEV_EEPROM_ROW_SIZE 0x00000010 +#define CYDEV_PERIPH_BASE CYDEV_CLKDIST_BASE +#define CYCLK_LD_DISABLE 0x00000004 +#define CYCLK_LD_SYNC_EN 0x00000002 +#define CYCLK_LD_LOAD 0x00000001 +#define CYCLK_PIPE 0x00000080 +#define CYCLK_SSS 0x00000040 +#define CYCLK_EARLY 0x00000020 +#define CYCLK_DUTY 0x00000010 +#define CYCLK_SYNC 0x00000008 +#define CYCLK_SRC_SEL_CLK_SYNC_D 0 +#define CYCLK_SRC_SEL_SYNC_DIG 0 +#define CYCLK_SRC_SEL_IMO 1 +#define CYCLK_SRC_SEL_XTAL_MHZ 2 +#define CYCLK_SRC_SEL_XTALM 2 +#define CYCLK_SRC_SEL_ILO 3 +#define CYCLK_SRC_SEL_PLL 4 +#define CYCLK_SRC_SEL_XTAL_KHZ 5 +#define CYCLK_SRC_SEL_XTALK 5 +#define CYCLK_SRC_SEL_DSI_G 6 +#define CYCLK_SRC_SEL_DSI_D 7 +#define CYCLK_SRC_SEL_CLK_SYNC_A 0 +#define CYCLK_SRC_SEL_DSI_A 7 diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc new file mode 100755 index 00000000..9ce82ff8 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc @@ -0,0 +1,5356 @@ +; +; FILENAME: cydeviceiar_trm.inc +; +; PSoC Creator 3.0 Component Pack 7 +; +; DESCRIPTION: +; This file provides all of the address values for the entire PSoC device. +; +;------------------------------------------------------------------------------- +; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + +#define CYDEV_FLASH_BASE 0x00000000 +#define CYDEV_FLASH_SIZE 0x00020000 +#define CYREG_FLASH_DATA_MBASE 0x00000000 +#define CYREG_FLASH_DATA_MSIZE 0x00020000 +#define CYDEV_SRAM_BASE 0x1fffc000 +#define CYDEV_SRAM_SIZE 0x00008000 +#define CYREG_SRAM_CODE64K_MBASE 0x1fff8000 +#define CYREG_SRAM_CODE64K_MSIZE 0x00004000 +#define CYREG_SRAM_CODE32K_MBASE 0x1fffc000 +#define CYREG_SRAM_CODE32K_MSIZE 0x00002000 +#define CYREG_SRAM_CODE16K_MBASE 0x1fffe000 +#define CYREG_SRAM_CODE16K_MSIZE 0x00001000 +#define CYREG_SRAM_CODE_MBASE 0x1fffc000 +#define CYREG_SRAM_CODE_MSIZE 0x00004000 +#define CYREG_SRAM_DATA_MBASE 0x20000000 +#define CYREG_SRAM_DATA_MSIZE 0x00004000 +#define CYREG_SRAM_DATA16K_MBASE 0x20001000 +#define CYREG_SRAM_DATA16K_MSIZE 0x00001000 +#define CYREG_SRAM_DATA32K_MBASE 0x20002000 +#define CYREG_SRAM_DATA32K_MSIZE 0x00002000 +#define CYREG_SRAM_DATA64K_MBASE 0x20004000 +#define CYREG_SRAM_DATA64K_MSIZE 0x00004000 +#define CYDEV_DMA_BASE 0x20008000 +#define CYDEV_DMA_SIZE 0x00008000 +#define CYREG_DMA_SRAM64K_MBASE 0x20008000 +#define CYREG_DMA_SRAM64K_MSIZE 0x00004000 +#define CYREG_DMA_SRAM32K_MBASE 0x2000c000 +#define CYREG_DMA_SRAM32K_MSIZE 0x00002000 +#define CYREG_DMA_SRAM16K_MBASE 0x2000e000 +#define CYREG_DMA_SRAM16K_MSIZE 0x00001000 +#define CYREG_DMA_SRAM_MBASE 0x2000f000 +#define CYREG_DMA_SRAM_MSIZE 0x00001000 +#define CYDEV_CLKDIST_BASE 0x40004000 +#define CYDEV_CLKDIST_SIZE 0x00000110 +#define CYREG_CLKDIST_CR 0x40004000 +#define CYREG_CLKDIST_LD 0x40004001 +#define CYREG_CLKDIST_WRK0 0x40004002 +#define CYREG_CLKDIST_WRK1 0x40004003 +#define CYREG_CLKDIST_MSTR0 0x40004004 +#define CYREG_CLKDIST_MSTR1 0x40004005 +#define CYREG_CLKDIST_BCFG0 0x40004006 +#define CYREG_CLKDIST_BCFG1 0x40004007 +#define CYREG_CLKDIST_BCFG2 0x40004008 +#define CYREG_CLKDIST_UCFG 0x40004009 +#define CYREG_CLKDIST_DLY0 0x4000400a +#define CYREG_CLKDIST_DLY1 0x4000400b +#define CYREG_CLKDIST_DMASK 0x40004010 +#define CYREG_CLKDIST_AMASK 0x40004014 +#define CYDEV_CLKDIST_DCFG0_BASE 0x40004080 +#define CYDEV_CLKDIST_DCFG0_SIZE 0x00000003 +#define CYREG_CLKDIST_DCFG0_CFG0 0x40004080 +#define CYREG_CLKDIST_DCFG0_CFG1 0x40004081 +#define CYREG_CLKDIST_DCFG0_CFG2 0x40004082 +#define CYDEV_CLKDIST_DCFG1_BASE 0x40004084 +#define CYDEV_CLKDIST_DCFG1_SIZE 0x00000003 +#define CYREG_CLKDIST_DCFG1_CFG0 0x40004084 +#define CYREG_CLKDIST_DCFG1_CFG1 0x40004085 +#define CYREG_CLKDIST_DCFG1_CFG2 0x40004086 +#define CYDEV_CLKDIST_DCFG2_BASE 0x40004088 +#define CYDEV_CLKDIST_DCFG2_SIZE 0x00000003 +#define CYREG_CLKDIST_DCFG2_CFG0 0x40004088 +#define CYREG_CLKDIST_DCFG2_CFG1 0x40004089 +#define CYREG_CLKDIST_DCFG2_CFG2 0x4000408a +#define CYDEV_CLKDIST_DCFG3_BASE 0x4000408c +#define CYDEV_CLKDIST_DCFG3_SIZE 0x00000003 +#define CYREG_CLKDIST_DCFG3_CFG0 0x4000408c +#define CYREG_CLKDIST_DCFG3_CFG1 0x4000408d +#define CYREG_CLKDIST_DCFG3_CFG2 0x4000408e +#define CYDEV_CLKDIST_DCFG4_BASE 0x40004090 +#define CYDEV_CLKDIST_DCFG4_SIZE 0x00000003 +#define CYREG_CLKDIST_DCFG4_CFG0 0x40004090 +#define CYREG_CLKDIST_DCFG4_CFG1 0x40004091 +#define CYREG_CLKDIST_DCFG4_CFG2 0x40004092 +#define CYDEV_CLKDIST_DCFG5_BASE 0x40004094 +#define CYDEV_CLKDIST_DCFG5_SIZE 0x00000003 +#define CYREG_CLKDIST_DCFG5_CFG0 0x40004094 +#define CYREG_CLKDIST_DCFG5_CFG1 0x40004095 +#define CYREG_CLKDIST_DCFG5_CFG2 0x40004096 +#define CYDEV_CLKDIST_DCFG6_BASE 0x40004098 +#define CYDEV_CLKDIST_DCFG6_SIZE 0x00000003 +#define CYREG_CLKDIST_DCFG6_CFG0 0x40004098 +#define CYREG_CLKDIST_DCFG6_CFG1 0x40004099 +#define CYREG_CLKDIST_DCFG6_CFG2 0x4000409a +#define CYDEV_CLKDIST_DCFG7_BASE 0x4000409c +#define CYDEV_CLKDIST_DCFG7_SIZE 0x00000003 +#define CYREG_CLKDIST_DCFG7_CFG0 0x4000409c +#define CYREG_CLKDIST_DCFG7_CFG1 0x4000409d +#define CYREG_CLKDIST_DCFG7_CFG2 0x4000409e +#define CYDEV_CLKDIST_ACFG0_BASE 0x40004100 +#define CYDEV_CLKDIST_ACFG0_SIZE 0x00000004 +#define CYREG_CLKDIST_ACFG0_CFG0 0x40004100 +#define CYREG_CLKDIST_ACFG0_CFG1 0x40004101 +#define CYREG_CLKDIST_ACFG0_CFG2 0x40004102 +#define CYREG_CLKDIST_ACFG0_CFG3 0x40004103 +#define CYDEV_CLKDIST_ACFG1_BASE 0x40004104 +#define CYDEV_CLKDIST_ACFG1_SIZE 0x00000004 +#define CYREG_CLKDIST_ACFG1_CFG0 0x40004104 +#define CYREG_CLKDIST_ACFG1_CFG1 0x40004105 +#define CYREG_CLKDIST_ACFG1_CFG2 0x40004106 +#define CYREG_CLKDIST_ACFG1_CFG3 0x40004107 +#define CYDEV_CLKDIST_ACFG2_BASE 0x40004108 +#define CYDEV_CLKDIST_ACFG2_SIZE 0x00000004 +#define CYREG_CLKDIST_ACFG2_CFG0 0x40004108 +#define CYREG_CLKDIST_ACFG2_CFG1 0x40004109 +#define CYREG_CLKDIST_ACFG2_CFG2 0x4000410a +#define CYREG_CLKDIST_ACFG2_CFG3 0x4000410b +#define CYDEV_CLKDIST_ACFG3_BASE 0x4000410c +#define CYDEV_CLKDIST_ACFG3_SIZE 0x00000004 +#define CYREG_CLKDIST_ACFG3_CFG0 0x4000410c +#define CYREG_CLKDIST_ACFG3_CFG1 0x4000410d +#define CYREG_CLKDIST_ACFG3_CFG2 0x4000410e +#define CYREG_CLKDIST_ACFG3_CFG3 0x4000410f +#define CYDEV_FASTCLK_BASE 0x40004200 +#define CYDEV_FASTCLK_SIZE 0x00000026 +#define CYDEV_FASTCLK_IMO_BASE 0x40004200 +#define CYDEV_FASTCLK_IMO_SIZE 0x00000001 +#define CYREG_FASTCLK_IMO_CR 0x40004200 +#define CYDEV_FASTCLK_XMHZ_BASE 0x40004210 +#define CYDEV_FASTCLK_XMHZ_SIZE 0x00000004 +#define CYREG_FASTCLK_XMHZ_CSR 0x40004210 +#define CYREG_FASTCLK_XMHZ_CFG0 0x40004212 +#define CYREG_FASTCLK_XMHZ_CFG1 0x40004213 +#define CYDEV_FASTCLK_PLL_BASE 0x40004220 +#define CYDEV_FASTCLK_PLL_SIZE 0x00000006 +#define CYREG_FASTCLK_PLL_CFG0 0x40004220 +#define CYREG_FASTCLK_PLL_CFG1 0x40004221 +#define CYREG_FASTCLK_PLL_P 0x40004222 +#define CYREG_FASTCLK_PLL_Q 0x40004223 +#define CYREG_FASTCLK_PLL_SR 0x40004225 +#define CYDEV_SLOWCLK_BASE 0x40004300 +#define CYDEV_SLOWCLK_SIZE 0x0000000b +#define CYDEV_SLOWCLK_ILO_BASE 0x40004300 +#define CYDEV_SLOWCLK_ILO_SIZE 0x00000002 +#define CYREG_SLOWCLK_ILO_CR0 0x40004300 +#define CYREG_SLOWCLK_ILO_CR1 0x40004301 +#define CYDEV_SLOWCLK_X32_BASE 0x40004308 +#define CYDEV_SLOWCLK_X32_SIZE 0x00000003 +#define CYREG_SLOWCLK_X32_CR 0x40004308 +#define CYREG_SLOWCLK_X32_CFG 0x40004309 +#define CYREG_SLOWCLK_X32_TST 0x4000430a +#define CYDEV_BOOST_BASE 0x40004320 +#define CYDEV_BOOST_SIZE 0x00000007 +#define CYREG_BOOST_CR0 0x40004320 +#define CYREG_BOOST_CR1 0x40004321 +#define CYREG_BOOST_CR2 0x40004322 +#define CYREG_BOOST_CR3 0x40004323 +#define CYREG_BOOST_SR 0x40004324 +#define CYREG_BOOST_CR4 0x40004325 +#define CYREG_BOOST_SR2 0x40004326 +#define CYDEV_PWRSYS_BASE 0x40004330 +#define CYDEV_PWRSYS_SIZE 0x00000002 +#define CYREG_PWRSYS_CR0 0x40004330 +#define CYREG_PWRSYS_CR1 0x40004331 +#define CYDEV_PM_BASE 0x40004380 +#define CYDEV_PM_SIZE 0x00000057 +#define CYREG_PM_TW_CFG0 0x40004380 +#define CYREG_PM_TW_CFG1 0x40004381 +#define CYREG_PM_TW_CFG2 0x40004382 +#define CYREG_PM_WDT_CFG 0x40004383 +#define CYREG_PM_WDT_CR 0x40004384 +#define CYREG_PM_INT_SR 0x40004390 +#define CYREG_PM_MODE_CFG0 0x40004391 +#define CYREG_PM_MODE_CFG1 0x40004392 +#define CYREG_PM_MODE_CSR 0x40004393 +#define CYREG_PM_USB_CR0 0x40004394 +#define CYREG_PM_WAKEUP_CFG0 0x40004398 +#define CYREG_PM_WAKEUP_CFG1 0x40004399 +#define CYREG_PM_WAKEUP_CFG2 0x4000439a +#define CYDEV_PM_ACT_BASE 0x400043a0 +#define CYDEV_PM_ACT_SIZE 0x0000000e +#define CYREG_PM_ACT_CFG0 0x400043a0 +#define CYREG_PM_ACT_CFG1 0x400043a1 +#define CYREG_PM_ACT_CFG2 0x400043a2 +#define CYREG_PM_ACT_CFG3 0x400043a3 +#define CYREG_PM_ACT_CFG4 0x400043a4 +#define CYREG_PM_ACT_CFG5 0x400043a5 +#define CYREG_PM_ACT_CFG6 0x400043a6 +#define CYREG_PM_ACT_CFG7 0x400043a7 +#define CYREG_PM_ACT_CFG8 0x400043a8 +#define CYREG_PM_ACT_CFG9 0x400043a9 +#define CYREG_PM_ACT_CFG10 0x400043aa +#define CYREG_PM_ACT_CFG11 0x400043ab +#define CYREG_PM_ACT_CFG12 0x400043ac +#define CYREG_PM_ACT_CFG13 0x400043ad +#define CYDEV_PM_STBY_BASE 0x400043b0 +#define CYDEV_PM_STBY_SIZE 0x0000000e +#define CYREG_PM_STBY_CFG0 0x400043b0 +#define CYREG_PM_STBY_CFG1 0x400043b1 +#define CYREG_PM_STBY_CFG2 0x400043b2 +#define CYREG_PM_STBY_CFG3 0x400043b3 +#define CYREG_PM_STBY_CFG4 0x400043b4 +#define CYREG_PM_STBY_CFG5 0x400043b5 +#define CYREG_PM_STBY_CFG6 0x400043b6 +#define CYREG_PM_STBY_CFG7 0x400043b7 +#define CYREG_PM_STBY_CFG8 0x400043b8 +#define CYREG_PM_STBY_CFG9 0x400043b9 +#define CYREG_PM_STBY_CFG10 0x400043ba +#define CYREG_PM_STBY_CFG11 0x400043bb +#define CYREG_PM_STBY_CFG12 0x400043bc +#define CYREG_PM_STBY_CFG13 0x400043bd +#define CYDEV_PM_AVAIL_BASE 0x400043c0 +#define CYDEV_PM_AVAIL_SIZE 0x00000017 +#define CYREG_PM_AVAIL_CR0 0x400043c0 +#define CYREG_PM_AVAIL_CR1 0x400043c1 +#define CYREG_PM_AVAIL_CR2 0x400043c2 +#define CYREG_PM_AVAIL_CR3 0x400043c3 +#define CYREG_PM_AVAIL_CR4 0x400043c4 +#define CYREG_PM_AVAIL_CR5 0x400043c5 +#define CYREG_PM_AVAIL_CR6 0x400043c6 +#define CYREG_PM_AVAIL_SR0 0x400043d0 +#define CYREG_PM_AVAIL_SR1 0x400043d1 +#define CYREG_PM_AVAIL_SR2 0x400043d2 +#define CYREG_PM_AVAIL_SR3 0x400043d3 +#define CYREG_PM_AVAIL_SR4 0x400043d4 +#define CYREG_PM_AVAIL_SR5 0x400043d5 +#define CYREG_PM_AVAIL_SR6 0x400043d6 +#define CYDEV_PICU_BASE 0x40004500 +#define CYDEV_PICU_SIZE 0x000000b0 +#define CYDEV_PICU_INTTYPE_BASE 0x40004500 +#define CYDEV_PICU_INTTYPE_SIZE 0x00000080 +#define CYDEV_PICU_INTTYPE_PICU0_BASE 0x40004500 +#define CYDEV_PICU_INTTYPE_PICU0_SIZE 0x00000008 +#define CYREG_PICU0_INTTYPE0 0x40004500 +#define CYREG_PICU0_INTTYPE1 0x40004501 +#define CYREG_PICU0_INTTYPE2 0x40004502 +#define CYREG_PICU0_INTTYPE3 0x40004503 +#define CYREG_PICU0_INTTYPE4 0x40004504 +#define CYREG_PICU0_INTTYPE5 0x40004505 +#define CYREG_PICU0_INTTYPE6 0x40004506 +#define CYREG_PICU0_INTTYPE7 0x40004507 +#define CYDEV_PICU_INTTYPE_PICU1_BASE 0x40004508 +#define CYDEV_PICU_INTTYPE_PICU1_SIZE 0x00000008 +#define CYREG_PICU1_INTTYPE0 0x40004508 +#define CYREG_PICU1_INTTYPE1 0x40004509 +#define CYREG_PICU1_INTTYPE2 0x4000450a +#define CYREG_PICU1_INTTYPE3 0x4000450b +#define CYREG_PICU1_INTTYPE4 0x4000450c +#define CYREG_PICU1_INTTYPE5 0x4000450d +#define CYREG_PICU1_INTTYPE6 0x4000450e +#define CYREG_PICU1_INTTYPE7 0x4000450f +#define CYDEV_PICU_INTTYPE_PICU2_BASE 0x40004510 +#define CYDEV_PICU_INTTYPE_PICU2_SIZE 0x00000008 +#define CYREG_PICU2_INTTYPE0 0x40004510 +#define CYREG_PICU2_INTTYPE1 0x40004511 +#define CYREG_PICU2_INTTYPE2 0x40004512 +#define CYREG_PICU2_INTTYPE3 0x40004513 +#define CYREG_PICU2_INTTYPE4 0x40004514 +#define CYREG_PICU2_INTTYPE5 0x40004515 +#define CYREG_PICU2_INTTYPE6 0x40004516 +#define CYREG_PICU2_INTTYPE7 0x40004517 +#define CYDEV_PICU_INTTYPE_PICU3_BASE 0x40004518 +#define CYDEV_PICU_INTTYPE_PICU3_SIZE 0x00000008 +#define CYREG_PICU3_INTTYPE0 0x40004518 +#define CYREG_PICU3_INTTYPE1 0x40004519 +#define CYREG_PICU3_INTTYPE2 0x4000451a +#define CYREG_PICU3_INTTYPE3 0x4000451b +#define CYREG_PICU3_INTTYPE4 0x4000451c +#define CYREG_PICU3_INTTYPE5 0x4000451d +#define CYREG_PICU3_INTTYPE6 0x4000451e +#define CYREG_PICU3_INTTYPE7 0x4000451f +#define CYDEV_PICU_INTTYPE_PICU4_BASE 0x40004520 +#define CYDEV_PICU_INTTYPE_PICU4_SIZE 0x00000008 +#define CYREG_PICU4_INTTYPE0 0x40004520 +#define CYREG_PICU4_INTTYPE1 0x40004521 +#define CYREG_PICU4_INTTYPE2 0x40004522 +#define CYREG_PICU4_INTTYPE3 0x40004523 +#define CYREG_PICU4_INTTYPE4 0x40004524 +#define CYREG_PICU4_INTTYPE5 0x40004525 +#define CYREG_PICU4_INTTYPE6 0x40004526 +#define CYREG_PICU4_INTTYPE7 0x40004527 +#define CYDEV_PICU_INTTYPE_PICU5_BASE 0x40004528 +#define CYDEV_PICU_INTTYPE_PICU5_SIZE 0x00000008 +#define CYREG_PICU5_INTTYPE0 0x40004528 +#define CYREG_PICU5_INTTYPE1 0x40004529 +#define CYREG_PICU5_INTTYPE2 0x4000452a +#define CYREG_PICU5_INTTYPE3 0x4000452b +#define CYREG_PICU5_INTTYPE4 0x4000452c +#define CYREG_PICU5_INTTYPE5 0x4000452d +#define CYREG_PICU5_INTTYPE6 0x4000452e +#define CYREG_PICU5_INTTYPE7 0x4000452f +#define CYDEV_PICU_INTTYPE_PICU6_BASE 0x40004530 +#define CYDEV_PICU_INTTYPE_PICU6_SIZE 0x00000008 +#define CYREG_PICU6_INTTYPE0 0x40004530 +#define CYREG_PICU6_INTTYPE1 0x40004531 +#define CYREG_PICU6_INTTYPE2 0x40004532 +#define CYREG_PICU6_INTTYPE3 0x40004533 +#define CYREG_PICU6_INTTYPE4 0x40004534 +#define CYREG_PICU6_INTTYPE5 0x40004535 +#define CYREG_PICU6_INTTYPE6 0x40004536 +#define CYREG_PICU6_INTTYPE7 0x40004537 +#define CYDEV_PICU_INTTYPE_PICU12_BASE 0x40004560 +#define CYDEV_PICU_INTTYPE_PICU12_SIZE 0x00000008 +#define CYREG_PICU12_INTTYPE0 0x40004560 +#define CYREG_PICU12_INTTYPE1 0x40004561 +#define CYREG_PICU12_INTTYPE2 0x40004562 +#define CYREG_PICU12_INTTYPE3 0x40004563 +#define CYREG_PICU12_INTTYPE4 0x40004564 +#define CYREG_PICU12_INTTYPE5 0x40004565 +#define CYREG_PICU12_INTTYPE6 0x40004566 +#define CYREG_PICU12_INTTYPE7 0x40004567 +#define CYDEV_PICU_INTTYPE_PICU15_BASE 0x40004578 +#define CYDEV_PICU_INTTYPE_PICU15_SIZE 0x00000008 +#define CYREG_PICU15_INTTYPE0 0x40004578 +#define CYREG_PICU15_INTTYPE1 0x40004579 +#define CYREG_PICU15_INTTYPE2 0x4000457a +#define CYREG_PICU15_INTTYPE3 0x4000457b +#define CYREG_PICU15_INTTYPE4 0x4000457c +#define CYREG_PICU15_INTTYPE5 0x4000457d +#define CYREG_PICU15_INTTYPE6 0x4000457e +#define CYREG_PICU15_INTTYPE7 0x4000457f +#define CYDEV_PICU_STAT_BASE 0x40004580 +#define CYDEV_PICU_STAT_SIZE 0x00000010 +#define CYDEV_PICU_STAT_PICU0_BASE 0x40004580 +#define CYDEV_PICU_STAT_PICU0_SIZE 0x00000001 +#define CYREG_PICU0_INTSTAT 0x40004580 +#define CYDEV_PICU_STAT_PICU1_BASE 0x40004581 +#define CYDEV_PICU_STAT_PICU1_SIZE 0x00000001 +#define CYREG_PICU1_INTSTAT 0x40004581 +#define CYDEV_PICU_STAT_PICU2_BASE 0x40004582 +#define CYDEV_PICU_STAT_PICU2_SIZE 0x00000001 +#define CYREG_PICU2_INTSTAT 0x40004582 +#define CYDEV_PICU_STAT_PICU3_BASE 0x40004583 +#define CYDEV_PICU_STAT_PICU3_SIZE 0x00000001 +#define CYREG_PICU3_INTSTAT 0x40004583 +#define CYDEV_PICU_STAT_PICU4_BASE 0x40004584 +#define CYDEV_PICU_STAT_PICU4_SIZE 0x00000001 +#define CYREG_PICU4_INTSTAT 0x40004584 +#define CYDEV_PICU_STAT_PICU5_BASE 0x40004585 +#define CYDEV_PICU_STAT_PICU5_SIZE 0x00000001 +#define CYREG_PICU5_INTSTAT 0x40004585 +#define CYDEV_PICU_STAT_PICU6_BASE 0x40004586 +#define CYDEV_PICU_STAT_PICU6_SIZE 0x00000001 +#define CYREG_PICU6_INTSTAT 0x40004586 +#define CYDEV_PICU_STAT_PICU12_BASE 0x4000458c +#define CYDEV_PICU_STAT_PICU12_SIZE 0x00000001 +#define CYREG_PICU12_INTSTAT 0x4000458c +#define CYDEV_PICU_STAT_PICU15_BASE 0x4000458f +#define CYDEV_PICU_STAT_PICU15_SIZE 0x00000001 +#define CYREG_PICU15_INTSTAT 0x4000458f +#define CYDEV_PICU_SNAP_BASE 0x40004590 +#define CYDEV_PICU_SNAP_SIZE 0x00000010 +#define CYDEV_PICU_SNAP_PICU0_BASE 0x40004590 +#define CYDEV_PICU_SNAP_PICU0_SIZE 0x00000001 +#define CYREG_PICU0_SNAP 0x40004590 +#define CYDEV_PICU_SNAP_PICU1_BASE 0x40004591 +#define CYDEV_PICU_SNAP_PICU1_SIZE 0x00000001 +#define CYREG_PICU1_SNAP 0x40004591 +#define CYDEV_PICU_SNAP_PICU2_BASE 0x40004592 +#define CYDEV_PICU_SNAP_PICU2_SIZE 0x00000001 +#define CYREG_PICU2_SNAP 0x40004592 +#define CYDEV_PICU_SNAP_PICU3_BASE 0x40004593 +#define CYDEV_PICU_SNAP_PICU3_SIZE 0x00000001 +#define CYREG_PICU3_SNAP 0x40004593 +#define CYDEV_PICU_SNAP_PICU4_BASE 0x40004594 +#define CYDEV_PICU_SNAP_PICU4_SIZE 0x00000001 +#define CYREG_PICU4_SNAP 0x40004594 +#define CYDEV_PICU_SNAP_PICU5_BASE 0x40004595 +#define CYDEV_PICU_SNAP_PICU5_SIZE 0x00000001 +#define CYREG_PICU5_SNAP 0x40004595 +#define CYDEV_PICU_SNAP_PICU6_BASE 0x40004596 +#define CYDEV_PICU_SNAP_PICU6_SIZE 0x00000001 +#define CYREG_PICU6_SNAP 0x40004596 +#define CYDEV_PICU_SNAP_PICU12_BASE 0x4000459c +#define CYDEV_PICU_SNAP_PICU12_SIZE 0x00000001 +#define CYREG_PICU12_SNAP 0x4000459c +#define CYDEV_PICU_SNAP_PICU_15_BASE 0x4000459f +#define CYDEV_PICU_SNAP_PICU_15_SIZE 0x00000001 +#define CYREG_PICU_15_SNAP_15 0x4000459f +#define CYDEV_PICU_DISABLE_COR_BASE 0x400045a0 +#define CYDEV_PICU_DISABLE_COR_SIZE 0x00000010 +#define CYDEV_PICU_DISABLE_COR_PICU0_BASE 0x400045a0 +#define CYDEV_PICU_DISABLE_COR_PICU0_SIZE 0x00000001 +#define CYREG_PICU0_DISABLE_COR 0x400045a0 +#define CYDEV_PICU_DISABLE_COR_PICU1_BASE 0x400045a1 +#define CYDEV_PICU_DISABLE_COR_PICU1_SIZE 0x00000001 +#define CYREG_PICU1_DISABLE_COR 0x400045a1 +#define CYDEV_PICU_DISABLE_COR_PICU2_BASE 0x400045a2 +#define CYDEV_PICU_DISABLE_COR_PICU2_SIZE 0x00000001 +#define CYREG_PICU2_DISABLE_COR 0x400045a2 +#define CYDEV_PICU_DISABLE_COR_PICU3_BASE 0x400045a3 +#define CYDEV_PICU_DISABLE_COR_PICU3_SIZE 0x00000001 +#define CYREG_PICU3_DISABLE_COR 0x400045a3 +#define CYDEV_PICU_DISABLE_COR_PICU4_BASE 0x400045a4 +#define CYDEV_PICU_DISABLE_COR_PICU4_SIZE 0x00000001 +#define CYREG_PICU4_DISABLE_COR 0x400045a4 +#define CYDEV_PICU_DISABLE_COR_PICU5_BASE 0x400045a5 +#define CYDEV_PICU_DISABLE_COR_PICU5_SIZE 0x00000001 +#define CYREG_PICU5_DISABLE_COR 0x400045a5 +#define CYDEV_PICU_DISABLE_COR_PICU6_BASE 0x400045a6 +#define CYDEV_PICU_DISABLE_COR_PICU6_SIZE 0x00000001 +#define CYREG_PICU6_DISABLE_COR 0x400045a6 +#define CYDEV_PICU_DISABLE_COR_PICU12_BASE 0x400045ac +#define CYDEV_PICU_DISABLE_COR_PICU12_SIZE 0x00000001 +#define CYREG_PICU12_DISABLE_COR 0x400045ac +#define CYDEV_PICU_DISABLE_COR_PICU15_BASE 0x400045af +#define CYDEV_PICU_DISABLE_COR_PICU15_SIZE 0x00000001 +#define CYREG_PICU15_DISABLE_COR 0x400045af +#define CYDEV_MFGCFG_BASE 0x40004600 +#define CYDEV_MFGCFG_SIZE 0x000000ed +#define CYDEV_MFGCFG_ANAIF_BASE 0x40004600 +#define CYDEV_MFGCFG_ANAIF_SIZE 0x00000038 +#define CYDEV_MFGCFG_ANAIF_DAC0_BASE 0x40004608 +#define CYDEV_MFGCFG_ANAIF_DAC0_SIZE 0x00000001 +#define CYREG_DAC0_TR 0x40004608 +#define CYDEV_MFGCFG_ANAIF_DAC1_BASE 0x40004609 +#define CYDEV_MFGCFG_ANAIF_DAC1_SIZE 0x00000001 +#define CYREG_DAC1_TR 0x40004609 +#define CYDEV_MFGCFG_ANAIF_DAC2_BASE 0x4000460a +#define CYDEV_MFGCFG_ANAIF_DAC2_SIZE 0x00000001 +#define CYREG_DAC2_TR 0x4000460a +#define CYDEV_MFGCFG_ANAIF_DAC3_BASE 0x4000460b +#define CYDEV_MFGCFG_ANAIF_DAC3_SIZE 0x00000001 +#define CYREG_DAC3_TR 0x4000460b +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE 0x40004610 +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE 0x00000001 +#define CYREG_NPUMP_DSM_TR0 0x40004610 +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE 0x40004611 +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE 0x00000001 +#define CYREG_NPUMP_SC_TR0 0x40004611 +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE 0x40004612 +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE 0x00000001 +#define CYREG_NPUMP_OPAMP_TR0 0x40004612 +#define CYDEV_MFGCFG_ANAIF_SAR0_BASE 0x40004614 +#define CYDEV_MFGCFG_ANAIF_SAR0_SIZE 0x00000001 +#define CYREG_SAR0_TR0 0x40004614 +#define CYDEV_MFGCFG_ANAIF_SAR1_BASE 0x40004616 +#define CYDEV_MFGCFG_ANAIF_SAR1_SIZE 0x00000001 +#define CYREG_SAR1_TR0 0x40004616 +#define CYDEV_MFGCFG_ANAIF_OPAMP0_BASE 0x40004620 +#define CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE 0x00000002 +#define CYREG_OPAMP0_TR0 0x40004620 +#define CYREG_OPAMP0_TR1 0x40004621 +#define CYDEV_MFGCFG_ANAIF_OPAMP1_BASE 0x40004622 +#define CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE 0x00000002 +#define CYREG_OPAMP1_TR0 0x40004622 +#define CYREG_OPAMP1_TR1 0x40004623 +#define CYDEV_MFGCFG_ANAIF_OPAMP2_BASE 0x40004624 +#define CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE 0x00000002 +#define CYREG_OPAMP2_TR0 0x40004624 +#define CYREG_OPAMP2_TR1 0x40004625 +#define CYDEV_MFGCFG_ANAIF_OPAMP3_BASE 0x40004626 +#define CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE 0x00000002 +#define CYREG_OPAMP3_TR0 0x40004626 +#define CYREG_OPAMP3_TR1 0x40004627 +#define CYDEV_MFGCFG_ANAIF_CMP0_BASE 0x40004630 +#define CYDEV_MFGCFG_ANAIF_CMP0_SIZE 0x00000002 +#define CYREG_CMP0_TR0 0x40004630 +#define CYREG_CMP0_TR1 0x40004631 +#define CYDEV_MFGCFG_ANAIF_CMP1_BASE 0x40004632 +#define CYDEV_MFGCFG_ANAIF_CMP1_SIZE 0x00000002 +#define CYREG_CMP1_TR0 0x40004632 +#define CYREG_CMP1_TR1 0x40004633 +#define CYDEV_MFGCFG_ANAIF_CMP2_BASE 0x40004634 +#define CYDEV_MFGCFG_ANAIF_CMP2_SIZE 0x00000002 +#define CYREG_CMP2_TR0 0x40004634 +#define CYREG_CMP2_TR1 0x40004635 +#define CYDEV_MFGCFG_ANAIF_CMP3_BASE 0x40004636 +#define CYDEV_MFGCFG_ANAIF_CMP3_SIZE 0x00000002 +#define CYREG_CMP3_TR0 0x40004636 +#define CYREG_CMP3_TR1 0x40004637 +#define CYDEV_MFGCFG_PWRSYS_BASE 0x40004680 +#define CYDEV_MFGCFG_PWRSYS_SIZE 0x0000000b +#define CYREG_PWRSYS_HIB_TR0 0x40004680 +#define CYREG_PWRSYS_HIB_TR1 0x40004681 +#define CYREG_PWRSYS_I2C_TR 0x40004682 +#define CYREG_PWRSYS_SLP_TR 0x40004683 +#define CYREG_PWRSYS_BUZZ_TR 0x40004684 +#define CYREG_PWRSYS_WAKE_TR0 0x40004685 +#define CYREG_PWRSYS_WAKE_TR1 0x40004686 +#define CYREG_PWRSYS_BREF_TR 0x40004687 +#define CYREG_PWRSYS_BG_TR 0x40004688 +#define CYREG_PWRSYS_WAKE_TR2 0x40004689 +#define CYREG_PWRSYS_WAKE_TR3 0x4000468a +#define CYDEV_MFGCFG_ILO_BASE 0x40004690 +#define CYDEV_MFGCFG_ILO_SIZE 0x00000002 +#define CYREG_ILO_TR0 0x40004690 +#define CYREG_ILO_TR1 0x40004691 +#define CYDEV_MFGCFG_X32_BASE 0x40004698 +#define CYDEV_MFGCFG_X32_SIZE 0x00000001 +#define CYREG_X32_TR 0x40004698 +#define CYDEV_MFGCFG_IMO_BASE 0x400046a0 +#define CYDEV_MFGCFG_IMO_SIZE 0x00000005 +#define CYREG_IMO_TR0 0x400046a0 +#define CYREG_IMO_TR1 0x400046a1 +#define CYREG_IMO_GAIN 0x400046a2 +#define CYREG_IMO_C36M 0x400046a3 +#define CYREG_IMO_TR2 0x400046a4 +#define CYDEV_MFGCFG_XMHZ_BASE 0x400046a8 +#define CYDEV_MFGCFG_XMHZ_SIZE 0x00000001 +#define CYREG_XMHZ_TR 0x400046a8 +#define CYREG_MFGCFG_DLY 0x400046c0 +#define CYDEV_MFGCFG_MLOGIC_BASE 0x400046e0 +#define CYDEV_MFGCFG_MLOGIC_SIZE 0x0000000d +#define CYREG_MLOGIC_DMPSTR 0x400046e2 +#define CYDEV_MFGCFG_MLOGIC_SEG_BASE 0x400046e4 +#define CYDEV_MFGCFG_MLOGIC_SEG_SIZE 0x00000002 +#define CYREG_MLOGIC_SEG_CR 0x400046e4 +#define CYREG_MLOGIC_SEG_CFG0 0x400046e5 +#define CYREG_MLOGIC_DEBUG 0x400046e8 +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE 0x400046ea +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE 0x00000001 +#define CYREG_MLOGIC_CPU_SCR_CPU_SCR 0x400046ea +#define CYREG_MLOGIC_REV_ID 0x400046ec +#define CYDEV_RESET_BASE 0x400046f0 +#define CYDEV_RESET_SIZE 0x0000000f +#define CYREG_RESET_IPOR_CR0 0x400046f0 +#define CYREG_RESET_IPOR_CR1 0x400046f1 +#define CYREG_RESET_IPOR_CR2 0x400046f2 +#define CYREG_RESET_IPOR_CR3 0x400046f3 +#define CYREG_RESET_CR0 0x400046f4 +#define CYREG_RESET_CR1 0x400046f5 +#define CYREG_RESET_CR2 0x400046f6 +#define CYREG_RESET_CR3 0x400046f7 +#define CYREG_RESET_CR4 0x400046f8 +#define CYREG_RESET_CR5 0x400046f9 +#define CYREG_RESET_SR0 0x400046fa +#define CYREG_RESET_SR1 0x400046fb +#define CYREG_RESET_SR2 0x400046fc +#define CYREG_RESET_SR3 0x400046fd +#define CYREG_RESET_TR 0x400046fe +#define CYDEV_SPC_BASE 0x40004700 +#define CYDEV_SPC_SIZE 0x00000100 +#define CYREG_SPC_FM_EE_CR 0x40004700 +#define CYREG_SPC_FM_EE_WAKE_CNT 0x40004701 +#define CYREG_SPC_EE_SCR 0x40004702 +#define CYREG_SPC_EE_ERR 0x40004703 +#define CYREG_SPC_CPU_DATA 0x40004720 +#define CYREG_SPC_DMA_DATA 0x40004721 +#define CYREG_SPC_SR 0x40004722 +#define CYREG_SPC_CR 0x40004723 +#define CYDEV_SPC_DMM_MAP_BASE 0x40004780 +#define CYDEV_SPC_DMM_MAP_SIZE 0x00000080 +#define CYREG_SPC_DMM_MAP_SRAM_MBASE 0x40004780 +#define CYREG_SPC_DMM_MAP_SRAM_MSIZE 0x00000080 +#define CYDEV_CACHE_BASE 0x40004800 +#define CYDEV_CACHE_SIZE 0x0000009c +#define CYREG_CACHE_CC_CTL 0x40004800 +#define CYREG_CACHE_ECC_CORR 0x40004880 +#define CYREG_CACHE_ECC_ERR 0x40004888 +#define CYREG_CACHE_FLASH_ERR 0x40004890 +#define CYREG_CACHE_HITMISS 0x40004898 +#define CYDEV_I2C_BASE 0x40004900 +#define CYDEV_I2C_SIZE 0x000000e1 +#define CYREG_I2C_XCFG 0x400049c8 +#define CYREG_I2C_ADR 0x400049ca +#define CYREG_I2C_CFG 0x400049d6 +#define CYREG_I2C_CSR 0x400049d7 +#define CYREG_I2C_D 0x400049d8 +#define CYREG_I2C_MCSR 0x400049d9 +#define CYREG_I2C_CLK_DIV1 0x400049db +#define CYREG_I2C_CLK_DIV2 0x400049dc +#define CYREG_I2C_TMOUT_CSR 0x400049dd +#define CYREG_I2C_TMOUT_SR 0x400049de +#define CYREG_I2C_TMOUT_CFG0 0x400049df +#define CYREG_I2C_TMOUT_CFG1 0x400049e0 +#define CYDEV_DEC_BASE 0x40004e00 +#define CYDEV_DEC_SIZE 0x00000015 +#define CYREG_DEC_CR 0x40004e00 +#define CYREG_DEC_SR 0x40004e01 +#define CYREG_DEC_SHIFT1 0x40004e02 +#define CYREG_DEC_SHIFT2 0x40004e03 +#define CYREG_DEC_DR2 0x40004e04 +#define CYREG_DEC_DR2H 0x40004e05 +#define CYREG_DEC_DR1 0x40004e06 +#define CYREG_DEC_OCOR 0x40004e08 +#define CYREG_DEC_OCORM 0x40004e09 +#define CYREG_DEC_OCORH 0x40004e0a +#define CYREG_DEC_GCOR 0x40004e0c +#define CYREG_DEC_GCORH 0x40004e0d +#define CYREG_DEC_GVAL 0x40004e0e +#define CYREG_DEC_OUTSAMP 0x40004e10 +#define CYREG_DEC_OUTSAMPM 0x40004e11 +#define CYREG_DEC_OUTSAMPH 0x40004e12 +#define CYREG_DEC_OUTSAMPS 0x40004e13 +#define CYREG_DEC_COHER 0x40004e14 +#define CYDEV_TMR0_BASE 0x40004f00 +#define CYDEV_TMR0_SIZE 0x0000000c +#define CYREG_TMR0_CFG0 0x40004f00 +#define CYREG_TMR0_CFG1 0x40004f01 +#define CYREG_TMR0_CFG2 0x40004f02 +#define CYREG_TMR0_SR0 0x40004f03 +#define CYREG_TMR0_PER0 0x40004f04 +#define CYREG_TMR0_PER1 0x40004f05 +#define CYREG_TMR0_CNT_CMP0 0x40004f06 +#define CYREG_TMR0_CNT_CMP1 0x40004f07 +#define CYREG_TMR0_CAP0 0x40004f08 +#define CYREG_TMR0_CAP1 0x40004f09 +#define CYREG_TMR0_RT0 0x40004f0a +#define CYREG_TMR0_RT1 0x40004f0b +#define CYDEV_TMR1_BASE 0x40004f0c +#define CYDEV_TMR1_SIZE 0x0000000c +#define CYREG_TMR1_CFG0 0x40004f0c +#define CYREG_TMR1_CFG1 0x40004f0d +#define CYREG_TMR1_CFG2 0x40004f0e +#define CYREG_TMR1_SR0 0x40004f0f +#define CYREG_TMR1_PER0 0x40004f10 +#define CYREG_TMR1_PER1 0x40004f11 +#define CYREG_TMR1_CNT_CMP0 0x40004f12 +#define CYREG_TMR1_CNT_CMP1 0x40004f13 +#define CYREG_TMR1_CAP0 0x40004f14 +#define CYREG_TMR1_CAP1 0x40004f15 +#define CYREG_TMR1_RT0 0x40004f16 +#define CYREG_TMR1_RT1 0x40004f17 +#define CYDEV_TMR2_BASE 0x40004f18 +#define CYDEV_TMR2_SIZE 0x0000000c +#define CYREG_TMR2_CFG0 0x40004f18 +#define CYREG_TMR2_CFG1 0x40004f19 +#define CYREG_TMR2_CFG2 0x40004f1a +#define CYREG_TMR2_SR0 0x40004f1b +#define CYREG_TMR2_PER0 0x40004f1c +#define CYREG_TMR2_PER1 0x40004f1d +#define CYREG_TMR2_CNT_CMP0 0x40004f1e +#define CYREG_TMR2_CNT_CMP1 0x40004f1f +#define CYREG_TMR2_CAP0 0x40004f20 +#define CYREG_TMR2_CAP1 0x40004f21 +#define CYREG_TMR2_RT0 0x40004f22 +#define CYREG_TMR2_RT1 0x40004f23 +#define CYDEV_TMR3_BASE 0x40004f24 +#define CYDEV_TMR3_SIZE 0x0000000c +#define CYREG_TMR3_CFG0 0x40004f24 +#define CYREG_TMR3_CFG1 0x40004f25 +#define CYREG_TMR3_CFG2 0x40004f26 +#define CYREG_TMR3_SR0 0x40004f27 +#define CYREG_TMR3_PER0 0x40004f28 +#define CYREG_TMR3_PER1 0x40004f29 +#define CYREG_TMR3_CNT_CMP0 0x40004f2a +#define CYREG_TMR3_CNT_CMP1 0x40004f2b +#define CYREG_TMR3_CAP0 0x40004f2c +#define CYREG_TMR3_CAP1 0x40004f2d +#define CYREG_TMR3_RT0 0x40004f2e +#define CYREG_TMR3_RT1 0x40004f2f +#define CYDEV_IO_BASE 0x40005000 +#define CYDEV_IO_SIZE 0x00000200 +#define CYDEV_IO_PC_BASE 0x40005000 +#define CYDEV_IO_PC_SIZE 0x00000080 +#define CYDEV_IO_PC_PRT0_BASE 0x40005000 +#define CYDEV_IO_PC_PRT0_SIZE 0x00000008 +#define CYREG_PRT0_PC0 0x40005000 +#define CYREG_PRT0_PC1 0x40005001 +#define CYREG_PRT0_PC2 0x40005002 +#define CYREG_PRT0_PC3 0x40005003 +#define CYREG_PRT0_PC4 0x40005004 +#define CYREG_PRT0_PC5 0x40005005 +#define CYREG_PRT0_PC6 0x40005006 +#define CYREG_PRT0_PC7 0x40005007 +#define CYDEV_IO_PC_PRT1_BASE 0x40005008 +#define CYDEV_IO_PC_PRT1_SIZE 0x00000008 +#define CYREG_PRT1_PC0 0x40005008 +#define CYREG_PRT1_PC1 0x40005009 +#define CYREG_PRT1_PC2 0x4000500a +#define CYREG_PRT1_PC3 0x4000500b +#define CYREG_PRT1_PC4 0x4000500c +#define CYREG_PRT1_PC5 0x4000500d +#define CYREG_PRT1_PC6 0x4000500e +#define CYREG_PRT1_PC7 0x4000500f +#define CYDEV_IO_PC_PRT2_BASE 0x40005010 +#define CYDEV_IO_PC_PRT2_SIZE 0x00000008 +#define CYREG_PRT2_PC0 0x40005010 +#define CYREG_PRT2_PC1 0x40005011 +#define CYREG_PRT2_PC2 0x40005012 +#define CYREG_PRT2_PC3 0x40005013 +#define CYREG_PRT2_PC4 0x40005014 +#define CYREG_PRT2_PC5 0x40005015 +#define CYREG_PRT2_PC6 0x40005016 +#define CYREG_PRT2_PC7 0x40005017 +#define CYDEV_IO_PC_PRT3_BASE 0x40005018 +#define CYDEV_IO_PC_PRT3_SIZE 0x00000008 +#define CYREG_PRT3_PC0 0x40005018 +#define CYREG_PRT3_PC1 0x40005019 +#define CYREG_PRT3_PC2 0x4000501a +#define CYREG_PRT3_PC3 0x4000501b +#define CYREG_PRT3_PC4 0x4000501c +#define CYREG_PRT3_PC5 0x4000501d +#define CYREG_PRT3_PC6 0x4000501e +#define CYREG_PRT3_PC7 0x4000501f +#define CYDEV_IO_PC_PRT4_BASE 0x40005020 +#define CYDEV_IO_PC_PRT4_SIZE 0x00000008 +#define CYREG_PRT4_PC0 0x40005020 +#define CYREG_PRT4_PC1 0x40005021 +#define CYREG_PRT4_PC2 0x40005022 +#define CYREG_PRT4_PC3 0x40005023 +#define CYREG_PRT4_PC4 0x40005024 +#define CYREG_PRT4_PC5 0x40005025 +#define CYREG_PRT4_PC6 0x40005026 +#define CYREG_PRT4_PC7 0x40005027 +#define CYDEV_IO_PC_PRT5_BASE 0x40005028 +#define CYDEV_IO_PC_PRT5_SIZE 0x00000008 +#define CYREG_PRT5_PC0 0x40005028 +#define CYREG_PRT5_PC1 0x40005029 +#define CYREG_PRT5_PC2 0x4000502a +#define CYREG_PRT5_PC3 0x4000502b +#define CYREG_PRT5_PC4 0x4000502c +#define CYREG_PRT5_PC5 0x4000502d +#define CYREG_PRT5_PC6 0x4000502e +#define CYREG_PRT5_PC7 0x4000502f +#define CYDEV_IO_PC_PRT6_BASE 0x40005030 +#define CYDEV_IO_PC_PRT6_SIZE 0x00000008 +#define CYREG_PRT6_PC0 0x40005030 +#define CYREG_PRT6_PC1 0x40005031 +#define CYREG_PRT6_PC2 0x40005032 +#define CYREG_PRT6_PC3 0x40005033 +#define CYREG_PRT6_PC4 0x40005034 +#define CYREG_PRT6_PC5 0x40005035 +#define CYREG_PRT6_PC6 0x40005036 +#define CYREG_PRT6_PC7 0x40005037 +#define CYDEV_IO_PC_PRT12_BASE 0x40005060 +#define CYDEV_IO_PC_PRT12_SIZE 0x00000008 +#define CYREG_PRT12_PC0 0x40005060 +#define CYREG_PRT12_PC1 0x40005061 +#define CYREG_PRT12_PC2 0x40005062 +#define CYREG_PRT12_PC3 0x40005063 +#define CYREG_PRT12_PC4 0x40005064 +#define CYREG_PRT12_PC5 0x40005065 +#define CYREG_PRT12_PC6 0x40005066 +#define CYREG_PRT12_PC7 0x40005067 +#define CYDEV_IO_PC_PRT15_BASE 0x40005078 +#define CYDEV_IO_PC_PRT15_SIZE 0x00000006 +#define CYREG_IO_PC_PRT15_PC0 0x40005078 +#define CYREG_IO_PC_PRT15_PC1 0x40005079 +#define CYREG_IO_PC_PRT15_PC2 0x4000507a +#define CYREG_IO_PC_PRT15_PC3 0x4000507b +#define CYREG_IO_PC_PRT15_PC4 0x4000507c +#define CYREG_IO_PC_PRT15_PC5 0x4000507d +#define CYDEV_IO_PC_PRT15_7_6_BASE 0x4000507e +#define CYDEV_IO_PC_PRT15_7_6_SIZE 0x00000002 +#define CYREG_IO_PC_PRT15_7_6_PC0 0x4000507e +#define CYREG_IO_PC_PRT15_7_6_PC1 0x4000507f +#define CYDEV_IO_DR_BASE 0x40005080 +#define CYDEV_IO_DR_SIZE 0x00000010 +#define CYDEV_IO_DR_PRT0_BASE 0x40005080 +#define CYDEV_IO_DR_PRT0_SIZE 0x00000001 +#define CYREG_PRT0_DR_ALIAS 0x40005080 +#define CYDEV_IO_DR_PRT1_BASE 0x40005081 +#define CYDEV_IO_DR_PRT1_SIZE 0x00000001 +#define CYREG_PRT1_DR_ALIAS 0x40005081 +#define CYDEV_IO_DR_PRT2_BASE 0x40005082 +#define CYDEV_IO_DR_PRT2_SIZE 0x00000001 +#define CYREG_PRT2_DR_ALIAS 0x40005082 +#define CYDEV_IO_DR_PRT3_BASE 0x40005083 +#define CYDEV_IO_DR_PRT3_SIZE 0x00000001 +#define CYREG_PRT3_DR_ALIAS 0x40005083 +#define CYDEV_IO_DR_PRT4_BASE 0x40005084 +#define CYDEV_IO_DR_PRT4_SIZE 0x00000001 +#define CYREG_PRT4_DR_ALIAS 0x40005084 +#define CYDEV_IO_DR_PRT5_BASE 0x40005085 +#define CYDEV_IO_DR_PRT5_SIZE 0x00000001 +#define CYREG_PRT5_DR_ALIAS 0x40005085 +#define CYDEV_IO_DR_PRT6_BASE 0x40005086 +#define CYDEV_IO_DR_PRT6_SIZE 0x00000001 +#define CYREG_PRT6_DR_ALIAS 0x40005086 +#define CYDEV_IO_DR_PRT12_BASE 0x4000508c +#define CYDEV_IO_DR_PRT12_SIZE 0x00000001 +#define CYREG_PRT12_DR_ALIAS 0x4000508c +#define CYDEV_IO_DR_PRT15_BASE 0x4000508f +#define CYDEV_IO_DR_PRT15_SIZE 0x00000001 +#define CYREG_PRT15_DR_15_ALIAS 0x4000508f +#define CYDEV_IO_PS_BASE 0x40005090 +#define CYDEV_IO_PS_SIZE 0x00000010 +#define CYDEV_IO_PS_PRT0_BASE 0x40005090 +#define CYDEV_IO_PS_PRT0_SIZE 0x00000001 +#define CYREG_PRT0_PS_ALIAS 0x40005090 +#define CYDEV_IO_PS_PRT1_BASE 0x40005091 +#define CYDEV_IO_PS_PRT1_SIZE 0x00000001 +#define CYREG_PRT1_PS_ALIAS 0x40005091 +#define CYDEV_IO_PS_PRT2_BASE 0x40005092 +#define CYDEV_IO_PS_PRT2_SIZE 0x00000001 +#define CYREG_PRT2_PS_ALIAS 0x40005092 +#define CYDEV_IO_PS_PRT3_BASE 0x40005093 +#define CYDEV_IO_PS_PRT3_SIZE 0x00000001 +#define CYREG_PRT3_PS_ALIAS 0x40005093 +#define CYDEV_IO_PS_PRT4_BASE 0x40005094 +#define CYDEV_IO_PS_PRT4_SIZE 0x00000001 +#define CYREG_PRT4_PS_ALIAS 0x40005094 +#define CYDEV_IO_PS_PRT5_BASE 0x40005095 +#define CYDEV_IO_PS_PRT5_SIZE 0x00000001 +#define CYREG_PRT5_PS_ALIAS 0x40005095 +#define CYDEV_IO_PS_PRT6_BASE 0x40005096 +#define CYDEV_IO_PS_PRT6_SIZE 0x00000001 +#define CYREG_PRT6_PS_ALIAS 0x40005096 +#define CYDEV_IO_PS_PRT12_BASE 0x4000509c +#define CYDEV_IO_PS_PRT12_SIZE 0x00000001 +#define CYREG_PRT12_PS_ALIAS 0x4000509c +#define CYDEV_IO_PS_PRT15_BASE 0x4000509f +#define CYDEV_IO_PS_PRT15_SIZE 0x00000001 +#define CYREG_PRT15_PS15_ALIAS 0x4000509f +#define CYDEV_IO_PRT_BASE 0x40005100 +#define CYDEV_IO_PRT_SIZE 0x00000100 +#define CYDEV_IO_PRT_PRT0_BASE 0x40005100 +#define CYDEV_IO_PRT_PRT0_SIZE 0x00000010 +#define CYREG_PRT0_DR 0x40005100 +#define CYREG_PRT0_PS 0x40005101 +#define CYREG_PRT0_DM0 0x40005102 +#define CYREG_PRT0_DM1 0x40005103 +#define CYREG_PRT0_DM2 0x40005104 +#define CYREG_PRT0_SLW 0x40005105 +#define CYREG_PRT0_BYP 0x40005106 +#define CYREG_PRT0_BIE 0x40005107 +#define CYREG_PRT0_INP_DIS 0x40005108 +#define CYREG_PRT0_CTL 0x40005109 +#define CYREG_PRT0_PRT 0x4000510a +#define CYREG_PRT0_BIT_MASK 0x4000510b +#define CYREG_PRT0_AMUX 0x4000510c +#define CYREG_PRT0_AG 0x4000510d +#define CYREG_PRT0_LCD_COM_SEG 0x4000510e +#define CYREG_PRT0_LCD_EN 0x4000510f +#define CYDEV_IO_PRT_PRT1_BASE 0x40005110 +#define CYDEV_IO_PRT_PRT1_SIZE 0x00000010 +#define CYREG_PRT1_DR 0x40005110 +#define CYREG_PRT1_PS 0x40005111 +#define CYREG_PRT1_DM0 0x40005112 +#define CYREG_PRT1_DM1 0x40005113 +#define CYREG_PRT1_DM2 0x40005114 +#define CYREG_PRT1_SLW 0x40005115 +#define CYREG_PRT1_BYP 0x40005116 +#define CYREG_PRT1_BIE 0x40005117 +#define CYREG_PRT1_INP_DIS 0x40005118 +#define CYREG_PRT1_CTL 0x40005119 +#define CYREG_PRT1_PRT 0x4000511a +#define CYREG_PRT1_BIT_MASK 0x4000511b +#define CYREG_PRT1_AMUX 0x4000511c +#define CYREG_PRT1_AG 0x4000511d +#define CYREG_PRT1_LCD_COM_SEG 0x4000511e +#define CYREG_PRT1_LCD_EN 0x4000511f +#define CYDEV_IO_PRT_PRT2_BASE 0x40005120 +#define CYDEV_IO_PRT_PRT2_SIZE 0x00000010 +#define CYREG_PRT2_DR 0x40005120 +#define CYREG_PRT2_PS 0x40005121 +#define CYREG_PRT2_DM0 0x40005122 +#define CYREG_PRT2_DM1 0x40005123 +#define CYREG_PRT2_DM2 0x40005124 +#define CYREG_PRT2_SLW 0x40005125 +#define CYREG_PRT2_BYP 0x40005126 +#define CYREG_PRT2_BIE 0x40005127 +#define CYREG_PRT2_INP_DIS 0x40005128 +#define CYREG_PRT2_CTL 0x40005129 +#define CYREG_PRT2_PRT 0x4000512a +#define CYREG_PRT2_BIT_MASK 0x4000512b +#define CYREG_PRT2_AMUX 0x4000512c +#define CYREG_PRT2_AG 0x4000512d +#define CYREG_PRT2_LCD_COM_SEG 0x4000512e +#define CYREG_PRT2_LCD_EN 0x4000512f +#define CYDEV_IO_PRT_PRT3_BASE 0x40005130 +#define CYDEV_IO_PRT_PRT3_SIZE 0x00000010 +#define CYREG_PRT3_DR 0x40005130 +#define CYREG_PRT3_PS 0x40005131 +#define CYREG_PRT3_DM0 0x40005132 +#define CYREG_PRT3_DM1 0x40005133 +#define CYREG_PRT3_DM2 0x40005134 +#define CYREG_PRT3_SLW 0x40005135 +#define CYREG_PRT3_BYP 0x40005136 +#define CYREG_PRT3_BIE 0x40005137 +#define CYREG_PRT3_INP_DIS 0x40005138 +#define CYREG_PRT3_CTL 0x40005139 +#define CYREG_PRT3_PRT 0x4000513a +#define CYREG_PRT3_BIT_MASK 0x4000513b +#define CYREG_PRT3_AMUX 0x4000513c +#define CYREG_PRT3_AG 0x4000513d +#define CYREG_PRT3_LCD_COM_SEG 0x4000513e +#define CYREG_PRT3_LCD_EN 0x4000513f +#define CYDEV_IO_PRT_PRT4_BASE 0x40005140 +#define CYDEV_IO_PRT_PRT4_SIZE 0x00000010 +#define CYREG_PRT4_DR 0x40005140 +#define CYREG_PRT4_PS 0x40005141 +#define CYREG_PRT4_DM0 0x40005142 +#define CYREG_PRT4_DM1 0x40005143 +#define CYREG_PRT4_DM2 0x40005144 +#define CYREG_PRT4_SLW 0x40005145 +#define CYREG_PRT4_BYP 0x40005146 +#define CYREG_PRT4_BIE 0x40005147 +#define CYREG_PRT4_INP_DIS 0x40005148 +#define CYREG_PRT4_CTL 0x40005149 +#define CYREG_PRT4_PRT 0x4000514a +#define CYREG_PRT4_BIT_MASK 0x4000514b +#define CYREG_PRT4_AMUX 0x4000514c +#define CYREG_PRT4_AG 0x4000514d +#define CYREG_PRT4_LCD_COM_SEG 0x4000514e +#define CYREG_PRT4_LCD_EN 0x4000514f +#define CYDEV_IO_PRT_PRT5_BASE 0x40005150 +#define CYDEV_IO_PRT_PRT5_SIZE 0x00000010 +#define CYREG_PRT5_DR 0x40005150 +#define CYREG_PRT5_PS 0x40005151 +#define CYREG_PRT5_DM0 0x40005152 +#define CYREG_PRT5_DM1 0x40005153 +#define CYREG_PRT5_DM2 0x40005154 +#define CYREG_PRT5_SLW 0x40005155 +#define CYREG_PRT5_BYP 0x40005156 +#define CYREG_PRT5_BIE 0x40005157 +#define CYREG_PRT5_INP_DIS 0x40005158 +#define CYREG_PRT5_CTL 0x40005159 +#define CYREG_PRT5_PRT 0x4000515a +#define CYREG_PRT5_BIT_MASK 0x4000515b +#define CYREG_PRT5_AMUX 0x4000515c +#define CYREG_PRT5_AG 0x4000515d +#define CYREG_PRT5_LCD_COM_SEG 0x4000515e +#define CYREG_PRT5_LCD_EN 0x4000515f +#define CYDEV_IO_PRT_PRT6_BASE 0x40005160 +#define CYDEV_IO_PRT_PRT6_SIZE 0x00000010 +#define CYREG_PRT6_DR 0x40005160 +#define CYREG_PRT6_PS 0x40005161 +#define CYREG_PRT6_DM0 0x40005162 +#define CYREG_PRT6_DM1 0x40005163 +#define CYREG_PRT6_DM2 0x40005164 +#define CYREG_PRT6_SLW 0x40005165 +#define CYREG_PRT6_BYP 0x40005166 +#define CYREG_PRT6_BIE 0x40005167 +#define CYREG_PRT6_INP_DIS 0x40005168 +#define CYREG_PRT6_CTL 0x40005169 +#define CYREG_PRT6_PRT 0x4000516a +#define CYREG_PRT6_BIT_MASK 0x4000516b +#define CYREG_PRT6_AMUX 0x4000516c +#define CYREG_PRT6_AG 0x4000516d +#define CYREG_PRT6_LCD_COM_SEG 0x4000516e +#define CYREG_PRT6_LCD_EN 0x4000516f +#define CYDEV_IO_PRT_PRT12_BASE 0x400051c0 +#define CYDEV_IO_PRT_PRT12_SIZE 0x00000010 +#define CYREG_PRT12_DR 0x400051c0 +#define CYREG_PRT12_PS 0x400051c1 +#define CYREG_PRT12_DM0 0x400051c2 +#define CYREG_PRT12_DM1 0x400051c3 +#define CYREG_PRT12_DM2 0x400051c4 +#define CYREG_PRT12_SLW 0x400051c5 +#define CYREG_PRT12_BYP 0x400051c6 +#define CYREG_PRT12_BIE 0x400051c7 +#define CYREG_PRT12_INP_DIS 0x400051c8 +#define CYREG_PRT12_SIO_HYST_EN 0x400051c9 +#define CYREG_PRT12_PRT 0x400051ca +#define CYREG_PRT12_BIT_MASK 0x400051cb +#define CYREG_PRT12_SIO_REG_HIFREQ 0x400051cc +#define CYREG_PRT12_AG 0x400051cd +#define CYREG_PRT12_SIO_CFG 0x400051ce +#define CYREG_PRT12_SIO_DIFF 0x400051cf +#define CYDEV_IO_PRT_PRT15_BASE 0x400051f0 +#define CYDEV_IO_PRT_PRT15_SIZE 0x00000010 +#define CYREG_PRT15_DR 0x400051f0 +#define CYREG_PRT15_PS 0x400051f1 +#define CYREG_PRT15_DM0 0x400051f2 +#define CYREG_PRT15_DM1 0x400051f3 +#define CYREG_PRT15_DM2 0x400051f4 +#define CYREG_PRT15_SLW 0x400051f5 +#define CYREG_PRT15_BYP 0x400051f6 +#define CYREG_PRT15_BIE 0x400051f7 +#define CYREG_PRT15_INP_DIS 0x400051f8 +#define CYREG_PRT15_CTL 0x400051f9 +#define CYREG_PRT15_PRT 0x400051fa +#define CYREG_PRT15_BIT_MASK 0x400051fb +#define CYREG_PRT15_AMUX 0x400051fc +#define CYREG_PRT15_AG 0x400051fd +#define CYREG_PRT15_LCD_COM_SEG 0x400051fe +#define CYREG_PRT15_LCD_EN 0x400051ff +#define CYDEV_PRTDSI_BASE 0x40005200 +#define CYDEV_PRTDSI_SIZE 0x0000007f +#define CYDEV_PRTDSI_PRT0_BASE 0x40005200 +#define CYDEV_PRTDSI_PRT0_SIZE 0x00000007 +#define CYREG_PRT0_OUT_SEL0 0x40005200 +#define CYREG_PRT0_OUT_SEL1 0x40005201 +#define CYREG_PRT0_OE_SEL0 0x40005202 +#define CYREG_PRT0_OE_SEL1 0x40005203 +#define CYREG_PRT0_DBL_SYNC_IN 0x40005204 +#define CYREG_PRT0_SYNC_OUT 0x40005205 +#define CYREG_PRT0_CAPS_SEL 0x40005206 +#define CYDEV_PRTDSI_PRT1_BASE 0x40005208 +#define CYDEV_PRTDSI_PRT1_SIZE 0x00000007 +#define CYREG_PRT1_OUT_SEL0 0x40005208 +#define CYREG_PRT1_OUT_SEL1 0x40005209 +#define CYREG_PRT1_OE_SEL0 0x4000520a +#define CYREG_PRT1_OE_SEL1 0x4000520b +#define CYREG_PRT1_DBL_SYNC_IN 0x4000520c +#define CYREG_PRT1_SYNC_OUT 0x4000520d +#define CYREG_PRT1_CAPS_SEL 0x4000520e +#define CYDEV_PRTDSI_PRT2_BASE 0x40005210 +#define CYDEV_PRTDSI_PRT2_SIZE 0x00000007 +#define CYREG_PRT2_OUT_SEL0 0x40005210 +#define CYREG_PRT2_OUT_SEL1 0x40005211 +#define CYREG_PRT2_OE_SEL0 0x40005212 +#define CYREG_PRT2_OE_SEL1 0x40005213 +#define CYREG_PRT2_DBL_SYNC_IN 0x40005214 +#define CYREG_PRT2_SYNC_OUT 0x40005215 +#define CYREG_PRT2_CAPS_SEL 0x40005216 +#define CYDEV_PRTDSI_PRT3_BASE 0x40005218 +#define CYDEV_PRTDSI_PRT3_SIZE 0x00000007 +#define CYREG_PRT3_OUT_SEL0 0x40005218 +#define CYREG_PRT3_OUT_SEL1 0x40005219 +#define CYREG_PRT3_OE_SEL0 0x4000521a +#define CYREG_PRT3_OE_SEL1 0x4000521b +#define CYREG_PRT3_DBL_SYNC_IN 0x4000521c +#define CYREG_PRT3_SYNC_OUT 0x4000521d +#define CYREG_PRT3_CAPS_SEL 0x4000521e +#define CYDEV_PRTDSI_PRT4_BASE 0x40005220 +#define CYDEV_PRTDSI_PRT4_SIZE 0x00000007 +#define CYREG_PRT4_OUT_SEL0 0x40005220 +#define CYREG_PRT4_OUT_SEL1 0x40005221 +#define CYREG_PRT4_OE_SEL0 0x40005222 +#define CYREG_PRT4_OE_SEL1 0x40005223 +#define CYREG_PRT4_DBL_SYNC_IN 0x40005224 +#define CYREG_PRT4_SYNC_OUT 0x40005225 +#define CYREG_PRT4_CAPS_SEL 0x40005226 +#define CYDEV_PRTDSI_PRT5_BASE 0x40005228 +#define CYDEV_PRTDSI_PRT5_SIZE 0x00000007 +#define CYREG_PRT5_OUT_SEL0 0x40005228 +#define CYREG_PRT5_OUT_SEL1 0x40005229 +#define CYREG_PRT5_OE_SEL0 0x4000522a +#define CYREG_PRT5_OE_SEL1 0x4000522b +#define CYREG_PRT5_DBL_SYNC_IN 0x4000522c +#define CYREG_PRT5_SYNC_OUT 0x4000522d +#define CYREG_PRT5_CAPS_SEL 0x4000522e +#define CYDEV_PRTDSI_PRT6_BASE 0x40005230 +#define CYDEV_PRTDSI_PRT6_SIZE 0x00000007 +#define CYREG_PRT6_OUT_SEL0 0x40005230 +#define CYREG_PRT6_OUT_SEL1 0x40005231 +#define CYREG_PRT6_OE_SEL0 0x40005232 +#define CYREG_PRT6_OE_SEL1 0x40005233 +#define CYREG_PRT6_DBL_SYNC_IN 0x40005234 +#define CYREG_PRT6_SYNC_OUT 0x40005235 +#define CYREG_PRT6_CAPS_SEL 0x40005236 +#define CYDEV_PRTDSI_PRT12_BASE 0x40005260 +#define CYDEV_PRTDSI_PRT12_SIZE 0x00000006 +#define CYREG_PRT12_OUT_SEL0 0x40005260 +#define CYREG_PRT12_OUT_SEL1 0x40005261 +#define CYREG_PRT12_OE_SEL0 0x40005262 +#define CYREG_PRT12_OE_SEL1 0x40005263 +#define CYREG_PRT12_DBL_SYNC_IN 0x40005264 +#define CYREG_PRT12_SYNC_OUT 0x40005265 +#define CYDEV_PRTDSI_PRT15_BASE 0x40005278 +#define CYDEV_PRTDSI_PRT15_SIZE 0x00000007 +#define CYREG_PRT15_OUT_SEL0 0x40005278 +#define CYREG_PRT15_OUT_SEL1 0x40005279 +#define CYREG_PRT15_OE_SEL0 0x4000527a +#define CYREG_PRT15_OE_SEL1 0x4000527b +#define CYREG_PRT15_DBL_SYNC_IN 0x4000527c +#define CYREG_PRT15_SYNC_OUT 0x4000527d +#define CYREG_PRT15_CAPS_SEL 0x4000527e +#define CYDEV_EMIF_BASE 0x40005400 +#define CYDEV_EMIF_SIZE 0x00000007 +#define CYREG_EMIF_NO_UDB 0x40005400 +#define CYREG_EMIF_RP_WAIT_STATES 0x40005401 +#define CYREG_EMIF_MEM_DWN 0x40005402 +#define CYREG_EMIF_MEMCLK_DIV 0x40005403 +#define CYREG_EMIF_CLOCK_EN 0x40005404 +#define CYREG_EMIF_EM_TYPE 0x40005405 +#define CYREG_EMIF_WP_WAIT_STATES 0x40005406 +#define CYDEV_ANAIF_BASE 0x40005800 +#define CYDEV_ANAIF_SIZE 0x000003a9 +#define CYDEV_ANAIF_CFG_BASE 0x40005800 +#define CYDEV_ANAIF_CFG_SIZE 0x0000010f +#define CYDEV_ANAIF_CFG_SC0_BASE 0x40005800 +#define CYDEV_ANAIF_CFG_SC0_SIZE 0x00000003 +#define CYREG_SC0_CR0 0x40005800 +#define CYREG_SC0_CR1 0x40005801 +#define CYREG_SC0_CR2 0x40005802 +#define CYDEV_ANAIF_CFG_SC1_BASE 0x40005804 +#define CYDEV_ANAIF_CFG_SC1_SIZE 0x00000003 +#define CYREG_SC1_CR0 0x40005804 +#define CYREG_SC1_CR1 0x40005805 +#define CYREG_SC1_CR2 0x40005806 +#define CYDEV_ANAIF_CFG_SC2_BASE 0x40005808 +#define CYDEV_ANAIF_CFG_SC2_SIZE 0x00000003 +#define CYREG_SC2_CR0 0x40005808 +#define CYREG_SC2_CR1 0x40005809 +#define CYREG_SC2_CR2 0x4000580a +#define CYDEV_ANAIF_CFG_SC3_BASE 0x4000580c +#define CYDEV_ANAIF_CFG_SC3_SIZE 0x00000003 +#define CYREG_SC3_CR0 0x4000580c +#define CYREG_SC3_CR1 0x4000580d +#define CYREG_SC3_CR2 0x4000580e +#define CYDEV_ANAIF_CFG_DAC0_BASE 0x40005820 +#define CYDEV_ANAIF_CFG_DAC0_SIZE 0x00000003 +#define CYREG_DAC0_CR0 0x40005820 +#define CYREG_DAC0_CR1 0x40005821 +#define CYREG_DAC0_TST 0x40005822 +#define CYDEV_ANAIF_CFG_DAC1_BASE 0x40005824 +#define CYDEV_ANAIF_CFG_DAC1_SIZE 0x00000003 +#define CYREG_DAC1_CR0 0x40005824 +#define CYREG_DAC1_CR1 0x40005825 +#define CYREG_DAC1_TST 0x40005826 +#define CYDEV_ANAIF_CFG_DAC2_BASE 0x40005828 +#define CYDEV_ANAIF_CFG_DAC2_SIZE 0x00000003 +#define CYREG_DAC2_CR0 0x40005828 +#define CYREG_DAC2_CR1 0x40005829 +#define CYREG_DAC2_TST 0x4000582a +#define CYDEV_ANAIF_CFG_DAC3_BASE 0x4000582c +#define CYDEV_ANAIF_CFG_DAC3_SIZE 0x00000003 +#define CYREG_DAC3_CR0 0x4000582c +#define CYREG_DAC3_CR1 0x4000582d +#define CYREG_DAC3_TST 0x4000582e +#define CYDEV_ANAIF_CFG_CMP0_BASE 0x40005840 +#define CYDEV_ANAIF_CFG_CMP0_SIZE 0x00000001 +#define CYREG_CMP0_CR 0x40005840 +#define CYDEV_ANAIF_CFG_CMP1_BASE 0x40005841 +#define CYDEV_ANAIF_CFG_CMP1_SIZE 0x00000001 +#define CYREG_CMP1_CR 0x40005841 +#define CYDEV_ANAIF_CFG_CMP2_BASE 0x40005842 +#define CYDEV_ANAIF_CFG_CMP2_SIZE 0x00000001 +#define CYREG_CMP2_CR 0x40005842 +#define CYDEV_ANAIF_CFG_CMP3_BASE 0x40005843 +#define CYDEV_ANAIF_CFG_CMP3_SIZE 0x00000001 +#define CYREG_CMP3_CR 0x40005843 +#define CYDEV_ANAIF_CFG_LUT0_BASE 0x40005848 +#define CYDEV_ANAIF_CFG_LUT0_SIZE 0x00000002 +#define CYREG_LUT0_CR 0x40005848 +#define CYREG_LUT0_MX 0x40005849 +#define CYDEV_ANAIF_CFG_LUT1_BASE 0x4000584a +#define CYDEV_ANAIF_CFG_LUT1_SIZE 0x00000002 +#define CYREG_LUT1_CR 0x4000584a +#define CYREG_LUT1_MX 0x4000584b +#define CYDEV_ANAIF_CFG_LUT2_BASE 0x4000584c +#define CYDEV_ANAIF_CFG_LUT2_SIZE 0x00000002 +#define CYREG_LUT2_CR 0x4000584c +#define CYREG_LUT2_MX 0x4000584d +#define CYDEV_ANAIF_CFG_LUT3_BASE 0x4000584e +#define CYDEV_ANAIF_CFG_LUT3_SIZE 0x00000002 +#define CYREG_LUT3_CR 0x4000584e +#define CYREG_LUT3_MX 0x4000584f +#define CYDEV_ANAIF_CFG_OPAMP0_BASE 0x40005858 +#define CYDEV_ANAIF_CFG_OPAMP0_SIZE 0x00000002 +#define CYREG_OPAMP0_CR 0x40005858 +#define CYREG_OPAMP0_RSVD 0x40005859 +#define CYDEV_ANAIF_CFG_OPAMP1_BASE 0x4000585a +#define CYDEV_ANAIF_CFG_OPAMP1_SIZE 0x00000002 +#define CYREG_OPAMP1_CR 0x4000585a +#define CYREG_OPAMP1_RSVD 0x4000585b +#define CYDEV_ANAIF_CFG_OPAMP2_BASE 0x4000585c +#define CYDEV_ANAIF_CFG_OPAMP2_SIZE 0x00000002 +#define CYREG_OPAMP2_CR 0x4000585c +#define CYREG_OPAMP2_RSVD 0x4000585d +#define CYDEV_ANAIF_CFG_OPAMP3_BASE 0x4000585e +#define CYDEV_ANAIF_CFG_OPAMP3_SIZE 0x00000002 +#define CYREG_OPAMP3_CR 0x4000585e +#define CYREG_OPAMP3_RSVD 0x4000585f +#define CYDEV_ANAIF_CFG_LCDDAC_BASE 0x40005868 +#define CYDEV_ANAIF_CFG_LCDDAC_SIZE 0x00000002 +#define CYREG_LCDDAC_CR0 0x40005868 +#define CYREG_LCDDAC_CR1 0x40005869 +#define CYDEV_ANAIF_CFG_LCDDRV_BASE 0x4000586a +#define CYDEV_ANAIF_CFG_LCDDRV_SIZE 0x00000001 +#define CYREG_LCDDRV_CR 0x4000586a +#define CYDEV_ANAIF_CFG_LCDTMR_BASE 0x4000586b +#define CYDEV_ANAIF_CFG_LCDTMR_SIZE 0x00000001 +#define CYREG_LCDTMR_CFG 0x4000586b +#define CYDEV_ANAIF_CFG_BG_BASE 0x4000586c +#define CYDEV_ANAIF_CFG_BG_SIZE 0x00000004 +#define CYREG_BG_CR0 0x4000586c +#define CYREG_BG_RSVD 0x4000586d +#define CYREG_BG_DFT0 0x4000586e +#define CYREG_BG_DFT1 0x4000586f +#define CYDEV_ANAIF_CFG_CAPSL_BASE 0x40005870 +#define CYDEV_ANAIF_CFG_CAPSL_SIZE 0x00000002 +#define CYREG_CAPSL_CFG0 0x40005870 +#define CYREG_CAPSL_CFG1 0x40005871 +#define CYDEV_ANAIF_CFG_CAPSR_BASE 0x40005872 +#define CYDEV_ANAIF_CFG_CAPSR_SIZE 0x00000002 +#define CYREG_CAPSR_CFG0 0x40005872 +#define CYREG_CAPSR_CFG1 0x40005873 +#define CYDEV_ANAIF_CFG_PUMP_BASE 0x40005876 +#define CYDEV_ANAIF_CFG_PUMP_SIZE 0x00000002 +#define CYREG_PUMP_CR0 0x40005876 +#define CYREG_PUMP_CR1 0x40005877 +#define CYDEV_ANAIF_CFG_LPF0_BASE 0x40005878 +#define CYDEV_ANAIF_CFG_LPF0_SIZE 0x00000002 +#define CYREG_LPF0_CR0 0x40005878 +#define CYREG_LPF0_RSVD 0x40005879 +#define CYDEV_ANAIF_CFG_LPF1_BASE 0x4000587a +#define CYDEV_ANAIF_CFG_LPF1_SIZE 0x00000002 +#define CYREG_LPF1_CR0 0x4000587a +#define CYREG_LPF1_RSVD 0x4000587b +#define CYDEV_ANAIF_CFG_MISC_BASE 0x4000587c +#define CYDEV_ANAIF_CFG_MISC_SIZE 0x00000001 +#define CYREG_ANAIF_CFG_MISC_CR0 0x4000587c +#define CYDEV_ANAIF_CFG_DSM0_BASE 0x40005880 +#define CYDEV_ANAIF_CFG_DSM0_SIZE 0x00000020 +#define CYREG_DSM0_CR0 0x40005880 +#define CYREG_DSM0_CR1 0x40005881 +#define CYREG_DSM0_CR2 0x40005882 +#define CYREG_DSM0_CR3 0x40005883 +#define CYREG_DSM0_CR4 0x40005884 +#define CYREG_DSM0_CR5 0x40005885 +#define CYREG_DSM0_CR6 0x40005886 +#define CYREG_DSM0_CR7 0x40005887 +#define CYREG_DSM0_CR8 0x40005888 +#define CYREG_DSM0_CR9 0x40005889 +#define CYREG_DSM0_CR10 0x4000588a +#define CYREG_DSM0_CR11 0x4000588b +#define CYREG_DSM0_CR12 0x4000588c +#define CYREG_DSM0_CR13 0x4000588d +#define CYREG_DSM0_CR14 0x4000588e +#define CYREG_DSM0_CR15 0x4000588f +#define CYREG_DSM0_CR16 0x40005890 +#define CYREG_DSM0_CR17 0x40005891 +#define CYREG_DSM0_REF0 0x40005892 +#define CYREG_DSM0_REF1 0x40005893 +#define CYREG_DSM0_REF2 0x40005894 +#define CYREG_DSM0_REF3 0x40005895 +#define CYREG_DSM0_DEM0 0x40005896 +#define CYREG_DSM0_DEM1 0x40005897 +#define CYREG_DSM0_TST0 0x40005898 +#define CYREG_DSM0_TST1 0x40005899 +#define CYREG_DSM0_BUF0 0x4000589a +#define CYREG_DSM0_BUF1 0x4000589b +#define CYREG_DSM0_BUF2 0x4000589c +#define CYREG_DSM0_BUF3 0x4000589d +#define CYREG_DSM0_MISC 0x4000589e +#define CYREG_DSM0_RSVD1 0x4000589f +#define CYDEV_ANAIF_CFG_SAR0_BASE 0x40005900 +#define CYDEV_ANAIF_CFG_SAR0_SIZE 0x00000007 +#define CYREG_SAR0_CSR0 0x40005900 +#define CYREG_SAR0_CSR1 0x40005901 +#define CYREG_SAR0_CSR2 0x40005902 +#define CYREG_SAR0_CSR3 0x40005903 +#define CYREG_SAR0_CSR4 0x40005904 +#define CYREG_SAR0_CSR5 0x40005905 +#define CYREG_SAR0_CSR6 0x40005906 +#define CYDEV_ANAIF_CFG_SAR1_BASE 0x40005908 +#define CYDEV_ANAIF_CFG_SAR1_SIZE 0x00000007 +#define CYREG_SAR1_CSR0 0x40005908 +#define CYREG_SAR1_CSR1 0x40005909 +#define CYREG_SAR1_CSR2 0x4000590a +#define CYREG_SAR1_CSR3 0x4000590b +#define CYREG_SAR1_CSR4 0x4000590c +#define CYREG_SAR1_CSR5 0x4000590d +#define CYREG_SAR1_CSR6 0x4000590e +#define CYDEV_ANAIF_RT_BASE 0x40005a00 +#define CYDEV_ANAIF_RT_SIZE 0x00000162 +#define CYDEV_ANAIF_RT_SC0_BASE 0x40005a00 +#define CYDEV_ANAIF_RT_SC0_SIZE 0x0000000d +#define CYREG_SC0_SW0 0x40005a00 +#define CYREG_SC0_SW2 0x40005a02 +#define CYREG_SC0_SW3 0x40005a03 +#define CYREG_SC0_SW4 0x40005a04 +#define CYREG_SC0_SW6 0x40005a06 +#define CYREG_SC0_SW7 0x40005a07 +#define CYREG_SC0_SW8 0x40005a08 +#define CYREG_SC0_SW10 0x40005a0a +#define CYREG_SC0_CLK 0x40005a0b +#define CYREG_SC0_BST 0x40005a0c +#define CYDEV_ANAIF_RT_SC1_BASE 0x40005a10 +#define CYDEV_ANAIF_RT_SC1_SIZE 0x0000000d +#define CYREG_SC1_SW0 0x40005a10 +#define CYREG_SC1_SW2 0x40005a12 +#define CYREG_SC1_SW3 0x40005a13 +#define CYREG_SC1_SW4 0x40005a14 +#define CYREG_SC1_SW6 0x40005a16 +#define CYREG_SC1_SW7 0x40005a17 +#define CYREG_SC1_SW8 0x40005a18 +#define CYREG_SC1_SW10 0x40005a1a +#define CYREG_SC1_CLK 0x40005a1b +#define CYREG_SC1_BST 0x40005a1c +#define CYDEV_ANAIF_RT_SC2_BASE 0x40005a20 +#define CYDEV_ANAIF_RT_SC2_SIZE 0x0000000d +#define CYREG_SC2_SW0 0x40005a20 +#define CYREG_SC2_SW2 0x40005a22 +#define CYREG_SC2_SW3 0x40005a23 +#define CYREG_SC2_SW4 0x40005a24 +#define CYREG_SC2_SW6 0x40005a26 +#define CYREG_SC2_SW7 0x40005a27 +#define CYREG_SC2_SW8 0x40005a28 +#define CYREG_SC2_SW10 0x40005a2a +#define CYREG_SC2_CLK 0x40005a2b +#define CYREG_SC2_BST 0x40005a2c +#define CYDEV_ANAIF_RT_SC3_BASE 0x40005a30 +#define CYDEV_ANAIF_RT_SC3_SIZE 0x0000000d +#define CYREG_SC3_SW0 0x40005a30 +#define CYREG_SC3_SW2 0x40005a32 +#define CYREG_SC3_SW3 0x40005a33 +#define CYREG_SC3_SW4 0x40005a34 +#define CYREG_SC3_SW6 0x40005a36 +#define CYREG_SC3_SW7 0x40005a37 +#define CYREG_SC3_SW8 0x40005a38 +#define CYREG_SC3_SW10 0x40005a3a +#define CYREG_SC3_CLK 0x40005a3b +#define CYREG_SC3_BST 0x40005a3c +#define CYDEV_ANAIF_RT_DAC0_BASE 0x40005a80 +#define CYDEV_ANAIF_RT_DAC0_SIZE 0x00000008 +#define CYREG_DAC0_SW0 0x40005a80 +#define CYREG_DAC0_SW2 0x40005a82 +#define CYREG_DAC0_SW3 0x40005a83 +#define CYREG_DAC0_SW4 0x40005a84 +#define CYREG_DAC0_STROBE 0x40005a87 +#define CYDEV_ANAIF_RT_DAC1_BASE 0x40005a88 +#define CYDEV_ANAIF_RT_DAC1_SIZE 0x00000008 +#define CYREG_DAC1_SW0 0x40005a88 +#define CYREG_DAC1_SW2 0x40005a8a +#define CYREG_DAC1_SW3 0x40005a8b +#define CYREG_DAC1_SW4 0x40005a8c +#define CYREG_DAC1_STROBE 0x40005a8f +#define CYDEV_ANAIF_RT_DAC2_BASE 0x40005a90 +#define CYDEV_ANAIF_RT_DAC2_SIZE 0x00000008 +#define CYREG_DAC2_SW0 0x40005a90 +#define CYREG_DAC2_SW2 0x40005a92 +#define CYREG_DAC2_SW3 0x40005a93 +#define CYREG_DAC2_SW4 0x40005a94 +#define CYREG_DAC2_STROBE 0x40005a97 +#define CYDEV_ANAIF_RT_DAC3_BASE 0x40005a98 +#define CYDEV_ANAIF_RT_DAC3_SIZE 0x00000008 +#define CYREG_DAC3_SW0 0x40005a98 +#define CYREG_DAC3_SW2 0x40005a9a +#define CYREG_DAC3_SW3 0x40005a9b +#define CYREG_DAC3_SW4 0x40005a9c +#define CYREG_DAC3_STROBE 0x40005a9f +#define CYDEV_ANAIF_RT_CMP0_BASE 0x40005ac0 +#define CYDEV_ANAIF_RT_CMP0_SIZE 0x00000008 +#define CYREG_CMP0_SW0 0x40005ac0 +#define CYREG_CMP0_SW2 0x40005ac2 +#define CYREG_CMP0_SW3 0x40005ac3 +#define CYREG_CMP0_SW4 0x40005ac4 +#define CYREG_CMP0_SW6 0x40005ac6 +#define CYREG_CMP0_CLK 0x40005ac7 +#define CYDEV_ANAIF_RT_CMP1_BASE 0x40005ac8 +#define CYDEV_ANAIF_RT_CMP1_SIZE 0x00000008 +#define CYREG_CMP1_SW0 0x40005ac8 +#define CYREG_CMP1_SW2 0x40005aca +#define CYREG_CMP1_SW3 0x40005acb +#define CYREG_CMP1_SW4 0x40005acc +#define CYREG_CMP1_SW6 0x40005ace +#define CYREG_CMP1_CLK 0x40005acf +#define CYDEV_ANAIF_RT_CMP2_BASE 0x40005ad0 +#define CYDEV_ANAIF_RT_CMP2_SIZE 0x00000008 +#define CYREG_CMP2_SW0 0x40005ad0 +#define CYREG_CMP2_SW2 0x40005ad2 +#define CYREG_CMP2_SW3 0x40005ad3 +#define CYREG_CMP2_SW4 0x40005ad4 +#define CYREG_CMP2_SW6 0x40005ad6 +#define CYREG_CMP2_CLK 0x40005ad7 +#define CYDEV_ANAIF_RT_CMP3_BASE 0x40005ad8 +#define CYDEV_ANAIF_RT_CMP3_SIZE 0x00000008 +#define CYREG_CMP3_SW0 0x40005ad8 +#define CYREG_CMP3_SW2 0x40005ada +#define CYREG_CMP3_SW3 0x40005adb +#define CYREG_CMP3_SW4 0x40005adc +#define CYREG_CMP3_SW6 0x40005ade +#define CYREG_CMP3_CLK 0x40005adf +#define CYDEV_ANAIF_RT_DSM0_BASE 0x40005b00 +#define CYDEV_ANAIF_RT_DSM0_SIZE 0x00000008 +#define CYREG_DSM0_SW0 0x40005b00 +#define CYREG_DSM0_SW2 0x40005b02 +#define CYREG_DSM0_SW3 0x40005b03 +#define CYREG_DSM0_SW4 0x40005b04 +#define CYREG_DSM0_SW6 0x40005b06 +#define CYREG_DSM0_CLK 0x40005b07 +#define CYDEV_ANAIF_RT_SAR0_BASE 0x40005b20 +#define CYDEV_ANAIF_RT_SAR0_SIZE 0x00000008 +#define CYREG_SAR0_SW0 0x40005b20 +#define CYREG_SAR0_SW2 0x40005b22 +#define CYREG_SAR0_SW3 0x40005b23 +#define CYREG_SAR0_SW4 0x40005b24 +#define CYREG_SAR0_SW6 0x40005b26 +#define CYREG_SAR0_CLK 0x40005b27 +#define CYDEV_ANAIF_RT_SAR1_BASE 0x40005b28 +#define CYDEV_ANAIF_RT_SAR1_SIZE 0x00000008 +#define CYREG_SAR1_SW0 0x40005b28 +#define CYREG_SAR1_SW2 0x40005b2a +#define CYREG_SAR1_SW3 0x40005b2b +#define CYREG_SAR1_SW4 0x40005b2c +#define CYREG_SAR1_SW6 0x40005b2e +#define CYREG_SAR1_CLK 0x40005b2f +#define CYDEV_ANAIF_RT_OPAMP0_BASE 0x40005b40 +#define CYDEV_ANAIF_RT_OPAMP0_SIZE 0x00000002 +#define CYREG_OPAMP0_MX 0x40005b40 +#define CYREG_OPAMP0_SW 0x40005b41 +#define CYDEV_ANAIF_RT_OPAMP1_BASE 0x40005b42 +#define CYDEV_ANAIF_RT_OPAMP1_SIZE 0x00000002 +#define CYREG_OPAMP1_MX 0x40005b42 +#define CYREG_OPAMP1_SW 0x40005b43 +#define CYDEV_ANAIF_RT_OPAMP2_BASE 0x40005b44 +#define CYDEV_ANAIF_RT_OPAMP2_SIZE 0x00000002 +#define CYREG_OPAMP2_MX 0x40005b44 +#define CYREG_OPAMP2_SW 0x40005b45 +#define CYDEV_ANAIF_RT_OPAMP3_BASE 0x40005b46 +#define CYDEV_ANAIF_RT_OPAMP3_SIZE 0x00000002 +#define CYREG_OPAMP3_MX 0x40005b46 +#define CYREG_OPAMP3_SW 0x40005b47 +#define CYDEV_ANAIF_RT_LCDDAC_BASE 0x40005b50 +#define CYDEV_ANAIF_RT_LCDDAC_SIZE 0x00000005 +#define CYREG_LCDDAC_SW0 0x40005b50 +#define CYREG_LCDDAC_SW1 0x40005b51 +#define CYREG_LCDDAC_SW2 0x40005b52 +#define CYREG_LCDDAC_SW3 0x40005b53 +#define CYREG_LCDDAC_SW4 0x40005b54 +#define CYDEV_ANAIF_RT_SC_BASE 0x40005b56 +#define CYDEV_ANAIF_RT_SC_SIZE 0x00000001 +#define CYREG_SC_MISC 0x40005b56 +#define CYDEV_ANAIF_RT_BUS_BASE 0x40005b58 +#define CYDEV_ANAIF_RT_BUS_SIZE 0x00000004 +#define CYREG_BUS_SW0 0x40005b58 +#define CYREG_BUS_SW2 0x40005b5a +#define CYREG_BUS_SW3 0x40005b5b +#define CYDEV_ANAIF_RT_DFT_BASE 0x40005b5c +#define CYDEV_ANAIF_RT_DFT_SIZE 0x00000006 +#define CYREG_DFT_CR0 0x40005b5c +#define CYREG_DFT_CR1 0x40005b5d +#define CYREG_DFT_CR2 0x40005b5e +#define CYREG_DFT_CR3 0x40005b5f +#define CYREG_DFT_CR4 0x40005b60 +#define CYREG_DFT_CR5 0x40005b61 +#define CYDEV_ANAIF_WRK_BASE 0x40005b80 +#define CYDEV_ANAIF_WRK_SIZE 0x00000029 +#define CYDEV_ANAIF_WRK_DAC0_BASE 0x40005b80 +#define CYDEV_ANAIF_WRK_DAC0_SIZE 0x00000001 +#define CYREG_DAC0_D 0x40005b80 +#define CYDEV_ANAIF_WRK_DAC1_BASE 0x40005b81 +#define CYDEV_ANAIF_WRK_DAC1_SIZE 0x00000001 +#define CYREG_DAC1_D 0x40005b81 +#define CYDEV_ANAIF_WRK_DAC2_BASE 0x40005b82 +#define CYDEV_ANAIF_WRK_DAC2_SIZE 0x00000001 +#define CYREG_DAC2_D 0x40005b82 +#define CYDEV_ANAIF_WRK_DAC3_BASE 0x40005b83 +#define CYDEV_ANAIF_WRK_DAC3_SIZE 0x00000001 +#define CYREG_DAC3_D 0x40005b83 +#define CYDEV_ANAIF_WRK_DSM0_BASE 0x40005b88 +#define CYDEV_ANAIF_WRK_DSM0_SIZE 0x00000002 +#define CYREG_DSM0_OUT0 0x40005b88 +#define CYREG_DSM0_OUT1 0x40005b89 +#define CYDEV_ANAIF_WRK_LUT_BASE 0x40005b90 +#define CYDEV_ANAIF_WRK_LUT_SIZE 0x00000005 +#define CYREG_LUT_SR 0x40005b90 +#define CYREG_LUT_WRK1 0x40005b91 +#define CYREG_LUT_MSK 0x40005b92 +#define CYREG_LUT_CLK 0x40005b93 +#define CYREG_LUT_CPTR 0x40005b94 +#define CYDEV_ANAIF_WRK_CMP_BASE 0x40005b96 +#define CYDEV_ANAIF_WRK_CMP_SIZE 0x00000002 +#define CYREG_CMP_WRK 0x40005b96 +#define CYREG_CMP_TST 0x40005b97 +#define CYDEV_ANAIF_WRK_SC_BASE 0x40005b98 +#define CYDEV_ANAIF_WRK_SC_SIZE 0x00000005 +#define CYREG_SC_SR 0x40005b98 +#define CYREG_SC_WRK1 0x40005b99 +#define CYREG_SC_MSK 0x40005b9a +#define CYREG_SC_CMPINV 0x40005b9b +#define CYREG_SC_CPTR 0x40005b9c +#define CYDEV_ANAIF_WRK_SAR0_BASE 0x40005ba0 +#define CYDEV_ANAIF_WRK_SAR0_SIZE 0x00000002 +#define CYREG_SAR0_WRK0 0x40005ba0 +#define CYREG_SAR0_WRK1 0x40005ba1 +#define CYDEV_ANAIF_WRK_SAR1_BASE 0x40005ba2 +#define CYDEV_ANAIF_WRK_SAR1_SIZE 0x00000002 +#define CYREG_SAR1_WRK0 0x40005ba2 +#define CYREG_SAR1_WRK1 0x40005ba3 +#define CYDEV_ANAIF_WRK_SARS_BASE 0x40005ba8 +#define CYDEV_ANAIF_WRK_SARS_SIZE 0x00000001 +#define CYREG_ANAIF_WRK_SARS_SOF 0x40005ba8 +#define CYDEV_USB_BASE 0x40006000 +#define CYDEV_USB_SIZE 0x00000300 +#define CYREG_USB_EP0_DR0 0x40006000 +#define CYREG_USB_EP0_DR1 0x40006001 +#define CYREG_USB_EP0_DR2 0x40006002 +#define CYREG_USB_EP0_DR3 0x40006003 +#define CYREG_USB_EP0_DR4 0x40006004 +#define CYREG_USB_EP0_DR5 0x40006005 +#define CYREG_USB_EP0_DR6 0x40006006 +#define CYREG_USB_EP0_DR7 0x40006007 +#define CYREG_USB_CR0 0x40006008 +#define CYREG_USB_CR1 0x40006009 +#define CYREG_USB_SIE_EP_INT_EN 0x4000600a +#define CYREG_USB_SIE_EP_INT_SR 0x4000600b +#define CYDEV_USB_SIE_EP1_BASE 0x4000600c +#define CYDEV_USB_SIE_EP1_SIZE 0x00000003 +#define CYREG_USB_SIE_EP1_CNT0 0x4000600c +#define CYREG_USB_SIE_EP1_CNT1 0x4000600d +#define CYREG_USB_SIE_EP1_CR0 0x4000600e +#define CYREG_USB_USBIO_CR0 0x40006010 +#define CYREG_USB_USBIO_CR1 0x40006012 +#define CYREG_USB_DYN_RECONFIG 0x40006014 +#define CYREG_USB_SOF0 0x40006018 +#define CYREG_USB_SOF1 0x40006019 +#define CYDEV_USB_SIE_EP2_BASE 0x4000601c +#define CYDEV_USB_SIE_EP2_SIZE 0x00000003 +#define CYREG_USB_SIE_EP2_CNT0 0x4000601c +#define CYREG_USB_SIE_EP2_CNT1 0x4000601d +#define CYREG_USB_SIE_EP2_CR0 0x4000601e +#define CYREG_USB_EP0_CR 0x40006028 +#define CYREG_USB_EP0_CNT 0x40006029 +#define CYDEV_USB_SIE_EP3_BASE 0x4000602c +#define CYDEV_USB_SIE_EP3_SIZE 0x00000003 +#define CYREG_USB_SIE_EP3_CNT0 0x4000602c +#define CYREG_USB_SIE_EP3_CNT1 0x4000602d +#define CYREG_USB_SIE_EP3_CR0 0x4000602e +#define CYDEV_USB_SIE_EP4_BASE 0x4000603c +#define CYDEV_USB_SIE_EP4_SIZE 0x00000003 +#define CYREG_USB_SIE_EP4_CNT0 0x4000603c +#define CYREG_USB_SIE_EP4_CNT1 0x4000603d +#define CYREG_USB_SIE_EP4_CR0 0x4000603e +#define CYDEV_USB_SIE_EP5_BASE 0x4000604c +#define CYDEV_USB_SIE_EP5_SIZE 0x00000003 +#define CYREG_USB_SIE_EP5_CNT0 0x4000604c +#define CYREG_USB_SIE_EP5_CNT1 0x4000604d +#define CYREG_USB_SIE_EP5_CR0 0x4000604e +#define CYDEV_USB_SIE_EP6_BASE 0x4000605c +#define CYDEV_USB_SIE_EP6_SIZE 0x00000003 +#define CYREG_USB_SIE_EP6_CNT0 0x4000605c +#define CYREG_USB_SIE_EP6_CNT1 0x4000605d +#define CYREG_USB_SIE_EP6_CR0 0x4000605e +#define CYDEV_USB_SIE_EP7_BASE 0x4000606c +#define CYDEV_USB_SIE_EP7_SIZE 0x00000003 +#define CYREG_USB_SIE_EP7_CNT0 0x4000606c +#define CYREG_USB_SIE_EP7_CNT1 0x4000606d +#define CYREG_USB_SIE_EP7_CR0 0x4000606e +#define CYDEV_USB_SIE_EP8_BASE 0x4000607c +#define CYDEV_USB_SIE_EP8_SIZE 0x00000003 +#define CYREG_USB_SIE_EP8_CNT0 0x4000607c +#define CYREG_USB_SIE_EP8_CNT1 0x4000607d +#define CYREG_USB_SIE_EP8_CR0 0x4000607e +#define CYDEV_USB_ARB_EP1_BASE 0x40006080 +#define CYDEV_USB_ARB_EP1_SIZE 0x00000003 +#define CYREG_USB_ARB_EP1_CFG 0x40006080 +#define CYREG_USB_ARB_EP1_INT_EN 0x40006081 +#define CYREG_USB_ARB_EP1_SR 0x40006082 +#define CYDEV_USB_ARB_RW1_BASE 0x40006084 +#define CYDEV_USB_ARB_RW1_SIZE 0x00000005 +#define CYREG_USB_ARB_RW1_WA 0x40006084 +#define CYREG_USB_ARB_RW1_WA_MSB 0x40006085 +#define CYREG_USB_ARB_RW1_RA 0x40006086 +#define CYREG_USB_ARB_RW1_RA_MSB 0x40006087 +#define CYREG_USB_ARB_RW1_DR 0x40006088 +#define CYREG_USB_BUF_SIZE 0x4000608c +#define CYREG_USB_EP_ACTIVE 0x4000608e +#define CYREG_USB_EP_TYPE 0x4000608f +#define CYDEV_USB_ARB_EP2_BASE 0x40006090 +#define CYDEV_USB_ARB_EP2_SIZE 0x00000003 +#define CYREG_USB_ARB_EP2_CFG 0x40006090 +#define CYREG_USB_ARB_EP2_INT_EN 0x40006091 +#define CYREG_USB_ARB_EP2_SR 0x40006092 +#define CYDEV_USB_ARB_RW2_BASE 0x40006094 +#define CYDEV_USB_ARB_RW2_SIZE 0x00000005 +#define CYREG_USB_ARB_RW2_WA 0x40006094 +#define CYREG_USB_ARB_RW2_WA_MSB 0x40006095 +#define CYREG_USB_ARB_RW2_RA 0x40006096 +#define CYREG_USB_ARB_RW2_RA_MSB 0x40006097 +#define CYREG_USB_ARB_RW2_DR 0x40006098 +#define CYREG_USB_ARB_CFG 0x4000609c +#define CYREG_USB_USB_CLK_EN 0x4000609d +#define CYREG_USB_ARB_INT_EN 0x4000609e +#define CYREG_USB_ARB_INT_SR 0x4000609f +#define CYDEV_USB_ARB_EP3_BASE 0x400060a0 +#define CYDEV_USB_ARB_EP3_SIZE 0x00000003 +#define CYREG_USB_ARB_EP3_CFG 0x400060a0 +#define CYREG_USB_ARB_EP3_INT_EN 0x400060a1 +#define CYREG_USB_ARB_EP3_SR 0x400060a2 +#define CYDEV_USB_ARB_RW3_BASE 0x400060a4 +#define CYDEV_USB_ARB_RW3_SIZE 0x00000005 +#define CYREG_USB_ARB_RW3_WA 0x400060a4 +#define CYREG_USB_ARB_RW3_WA_MSB 0x400060a5 +#define CYREG_USB_ARB_RW3_RA 0x400060a6 +#define CYREG_USB_ARB_RW3_RA_MSB 0x400060a7 +#define CYREG_USB_ARB_RW3_DR 0x400060a8 +#define CYREG_USB_CWA 0x400060ac +#define CYREG_USB_CWA_MSB 0x400060ad +#define CYDEV_USB_ARB_EP4_BASE 0x400060b0 +#define CYDEV_USB_ARB_EP4_SIZE 0x00000003 +#define CYREG_USB_ARB_EP4_CFG 0x400060b0 +#define CYREG_USB_ARB_EP4_INT_EN 0x400060b1 +#define CYREG_USB_ARB_EP4_SR 0x400060b2 +#define CYDEV_USB_ARB_RW4_BASE 0x400060b4 +#define CYDEV_USB_ARB_RW4_SIZE 0x00000005 +#define CYREG_USB_ARB_RW4_WA 0x400060b4 +#define CYREG_USB_ARB_RW4_WA_MSB 0x400060b5 +#define CYREG_USB_ARB_RW4_RA 0x400060b6 +#define CYREG_USB_ARB_RW4_RA_MSB 0x400060b7 +#define CYREG_USB_ARB_RW4_DR 0x400060b8 +#define CYREG_USB_DMA_THRES 0x400060bc +#define CYREG_USB_DMA_THRES_MSB 0x400060bd +#define CYDEV_USB_ARB_EP5_BASE 0x400060c0 +#define CYDEV_USB_ARB_EP5_SIZE 0x00000003 +#define CYREG_USB_ARB_EP5_CFG 0x400060c0 +#define CYREG_USB_ARB_EP5_INT_EN 0x400060c1 +#define CYREG_USB_ARB_EP5_SR 0x400060c2 +#define CYDEV_USB_ARB_RW5_BASE 0x400060c4 +#define CYDEV_USB_ARB_RW5_SIZE 0x00000005 +#define CYREG_USB_ARB_RW5_WA 0x400060c4 +#define CYREG_USB_ARB_RW5_WA_MSB 0x400060c5 +#define CYREG_USB_ARB_RW5_RA 0x400060c6 +#define CYREG_USB_ARB_RW5_RA_MSB 0x400060c7 +#define CYREG_USB_ARB_RW5_DR 0x400060c8 +#define CYREG_USB_BUS_RST_CNT 0x400060cc +#define CYDEV_USB_ARB_EP6_BASE 0x400060d0 +#define CYDEV_USB_ARB_EP6_SIZE 0x00000003 +#define CYREG_USB_ARB_EP6_CFG 0x400060d0 +#define CYREG_USB_ARB_EP6_INT_EN 0x400060d1 +#define CYREG_USB_ARB_EP6_SR 0x400060d2 +#define CYDEV_USB_ARB_RW6_BASE 0x400060d4 +#define CYDEV_USB_ARB_RW6_SIZE 0x00000005 +#define CYREG_USB_ARB_RW6_WA 0x400060d4 +#define CYREG_USB_ARB_RW6_WA_MSB 0x400060d5 +#define CYREG_USB_ARB_RW6_RA 0x400060d6 +#define CYREG_USB_ARB_RW6_RA_MSB 0x400060d7 +#define CYREG_USB_ARB_RW6_DR 0x400060d8 +#define CYDEV_USB_ARB_EP7_BASE 0x400060e0 +#define CYDEV_USB_ARB_EP7_SIZE 0x00000003 +#define CYREG_USB_ARB_EP7_CFG 0x400060e0 +#define CYREG_USB_ARB_EP7_INT_EN 0x400060e1 +#define CYREG_USB_ARB_EP7_SR 0x400060e2 +#define CYDEV_USB_ARB_RW7_BASE 0x400060e4 +#define CYDEV_USB_ARB_RW7_SIZE 0x00000005 +#define CYREG_USB_ARB_RW7_WA 0x400060e4 +#define CYREG_USB_ARB_RW7_WA_MSB 0x400060e5 +#define CYREG_USB_ARB_RW7_RA 0x400060e6 +#define CYREG_USB_ARB_RW7_RA_MSB 0x400060e7 +#define CYREG_USB_ARB_RW7_DR 0x400060e8 +#define CYDEV_USB_ARB_EP8_BASE 0x400060f0 +#define CYDEV_USB_ARB_EP8_SIZE 0x00000003 +#define CYREG_USB_ARB_EP8_CFG 0x400060f0 +#define CYREG_USB_ARB_EP8_INT_EN 0x400060f1 +#define CYREG_USB_ARB_EP8_SR 0x400060f2 +#define CYDEV_USB_ARB_RW8_BASE 0x400060f4 +#define CYDEV_USB_ARB_RW8_SIZE 0x00000005 +#define CYREG_USB_ARB_RW8_WA 0x400060f4 +#define CYREG_USB_ARB_RW8_WA_MSB 0x400060f5 +#define CYREG_USB_ARB_RW8_RA 0x400060f6 +#define CYREG_USB_ARB_RW8_RA_MSB 0x400060f7 +#define CYREG_USB_ARB_RW8_DR 0x400060f8 +#define CYDEV_USB_MEM_BASE 0x40006100 +#define CYDEV_USB_MEM_SIZE 0x00000200 +#define CYREG_USB_MEM_DATA_MBASE 0x40006100 +#define CYREG_USB_MEM_DATA_MSIZE 0x00000200 +#define CYDEV_UWRK_BASE 0x40006400 +#define CYDEV_UWRK_SIZE 0x00000b60 +#define CYDEV_UWRK_UWRK8_BASE 0x40006400 +#define CYDEV_UWRK_UWRK8_SIZE 0x000003b0 +#define CYDEV_UWRK_UWRK8_B0_BASE 0x40006400 +#define CYDEV_UWRK_UWRK8_B0_SIZE 0x000000b0 +#define CYREG_B0_UDB00_A0 0x40006400 +#define CYREG_B0_UDB01_A0 0x40006401 +#define CYREG_B0_UDB02_A0 0x40006402 +#define CYREG_B0_UDB03_A0 0x40006403 +#define CYREG_B0_UDB04_A0 0x40006404 +#define CYREG_B0_UDB05_A0 0x40006405 +#define CYREG_B0_UDB06_A0 0x40006406 +#define CYREG_B0_UDB07_A0 0x40006407 +#define CYREG_B0_UDB08_A0 0x40006408 +#define CYREG_B0_UDB09_A0 0x40006409 +#define CYREG_B0_UDB10_A0 0x4000640a +#define CYREG_B0_UDB11_A0 0x4000640b +#define CYREG_B0_UDB12_A0 0x4000640c +#define CYREG_B0_UDB13_A0 0x4000640d +#define CYREG_B0_UDB14_A0 0x4000640e +#define CYREG_B0_UDB15_A0 0x4000640f +#define CYREG_B0_UDB00_A1 0x40006410 +#define CYREG_B0_UDB01_A1 0x40006411 +#define CYREG_B0_UDB02_A1 0x40006412 +#define CYREG_B0_UDB03_A1 0x40006413 +#define CYREG_B0_UDB04_A1 0x40006414 +#define CYREG_B0_UDB05_A1 0x40006415 +#define CYREG_B0_UDB06_A1 0x40006416 +#define CYREG_B0_UDB07_A1 0x40006417 +#define CYREG_B0_UDB08_A1 0x40006418 +#define CYREG_B0_UDB09_A1 0x40006419 +#define CYREG_B0_UDB10_A1 0x4000641a +#define CYREG_B0_UDB11_A1 0x4000641b +#define CYREG_B0_UDB12_A1 0x4000641c +#define CYREG_B0_UDB13_A1 0x4000641d +#define CYREG_B0_UDB14_A1 0x4000641e +#define CYREG_B0_UDB15_A1 0x4000641f +#define CYREG_B0_UDB00_D0 0x40006420 +#define CYREG_B0_UDB01_D0 0x40006421 +#define CYREG_B0_UDB02_D0 0x40006422 +#define CYREG_B0_UDB03_D0 0x40006423 +#define CYREG_B0_UDB04_D0 0x40006424 +#define CYREG_B0_UDB05_D0 0x40006425 +#define CYREG_B0_UDB06_D0 0x40006426 +#define CYREG_B0_UDB07_D0 0x40006427 +#define CYREG_B0_UDB08_D0 0x40006428 +#define CYREG_B0_UDB09_D0 0x40006429 +#define CYREG_B0_UDB10_D0 0x4000642a +#define CYREG_B0_UDB11_D0 0x4000642b +#define CYREG_B0_UDB12_D0 0x4000642c +#define CYREG_B0_UDB13_D0 0x4000642d +#define CYREG_B0_UDB14_D0 0x4000642e +#define CYREG_B0_UDB15_D0 0x4000642f +#define CYREG_B0_UDB00_D1 0x40006430 +#define CYREG_B0_UDB01_D1 0x40006431 +#define CYREG_B0_UDB02_D1 0x40006432 +#define CYREG_B0_UDB03_D1 0x40006433 +#define CYREG_B0_UDB04_D1 0x40006434 +#define CYREG_B0_UDB05_D1 0x40006435 +#define CYREG_B0_UDB06_D1 0x40006436 +#define CYREG_B0_UDB07_D1 0x40006437 +#define CYREG_B0_UDB08_D1 0x40006438 +#define CYREG_B0_UDB09_D1 0x40006439 +#define CYREG_B0_UDB10_D1 0x4000643a +#define CYREG_B0_UDB11_D1 0x4000643b +#define CYREG_B0_UDB12_D1 0x4000643c +#define CYREG_B0_UDB13_D1 0x4000643d +#define CYREG_B0_UDB14_D1 0x4000643e +#define CYREG_B0_UDB15_D1 0x4000643f +#define CYREG_B0_UDB00_F0 0x40006440 +#define CYREG_B0_UDB01_F0 0x40006441 +#define CYREG_B0_UDB02_F0 0x40006442 +#define CYREG_B0_UDB03_F0 0x40006443 +#define CYREG_B0_UDB04_F0 0x40006444 +#define CYREG_B0_UDB05_F0 0x40006445 +#define CYREG_B0_UDB06_F0 0x40006446 +#define CYREG_B0_UDB07_F0 0x40006447 +#define CYREG_B0_UDB08_F0 0x40006448 +#define CYREG_B0_UDB09_F0 0x40006449 +#define CYREG_B0_UDB10_F0 0x4000644a +#define CYREG_B0_UDB11_F0 0x4000644b +#define CYREG_B0_UDB12_F0 0x4000644c +#define CYREG_B0_UDB13_F0 0x4000644d +#define CYREG_B0_UDB14_F0 0x4000644e +#define CYREG_B0_UDB15_F0 0x4000644f +#define CYREG_B0_UDB00_F1 0x40006450 +#define CYREG_B0_UDB01_F1 0x40006451 +#define CYREG_B0_UDB02_F1 0x40006452 +#define CYREG_B0_UDB03_F1 0x40006453 +#define CYREG_B0_UDB04_F1 0x40006454 +#define CYREG_B0_UDB05_F1 0x40006455 +#define CYREG_B0_UDB06_F1 0x40006456 +#define CYREG_B0_UDB07_F1 0x40006457 +#define CYREG_B0_UDB08_F1 0x40006458 +#define CYREG_B0_UDB09_F1 0x40006459 +#define CYREG_B0_UDB10_F1 0x4000645a +#define CYREG_B0_UDB11_F1 0x4000645b +#define CYREG_B0_UDB12_F1 0x4000645c +#define CYREG_B0_UDB13_F1 0x4000645d +#define CYREG_B0_UDB14_F1 0x4000645e +#define CYREG_B0_UDB15_F1 0x4000645f +#define CYREG_B0_UDB00_ST 0x40006460 +#define CYREG_B0_UDB01_ST 0x40006461 +#define CYREG_B0_UDB02_ST 0x40006462 +#define CYREG_B0_UDB03_ST 0x40006463 +#define CYREG_B0_UDB04_ST 0x40006464 +#define CYREG_B0_UDB05_ST 0x40006465 +#define CYREG_B0_UDB06_ST 0x40006466 +#define CYREG_B0_UDB07_ST 0x40006467 +#define CYREG_B0_UDB08_ST 0x40006468 +#define CYREG_B0_UDB09_ST 0x40006469 +#define CYREG_B0_UDB10_ST 0x4000646a +#define CYREG_B0_UDB11_ST 0x4000646b +#define CYREG_B0_UDB12_ST 0x4000646c +#define CYREG_B0_UDB13_ST 0x4000646d +#define CYREG_B0_UDB14_ST 0x4000646e +#define CYREG_B0_UDB15_ST 0x4000646f +#define CYREG_B0_UDB00_CTL 0x40006470 +#define CYREG_B0_UDB01_CTL 0x40006471 +#define CYREG_B0_UDB02_CTL 0x40006472 +#define CYREG_B0_UDB03_CTL 0x40006473 +#define CYREG_B0_UDB04_CTL 0x40006474 +#define CYREG_B0_UDB05_CTL 0x40006475 +#define CYREG_B0_UDB06_CTL 0x40006476 +#define CYREG_B0_UDB07_CTL 0x40006477 +#define CYREG_B0_UDB08_CTL 0x40006478 +#define CYREG_B0_UDB09_CTL 0x40006479 +#define CYREG_B0_UDB10_CTL 0x4000647a +#define CYREG_B0_UDB11_CTL 0x4000647b +#define CYREG_B0_UDB12_CTL 0x4000647c +#define CYREG_B0_UDB13_CTL 0x4000647d +#define CYREG_B0_UDB14_CTL 0x4000647e +#define CYREG_B0_UDB15_CTL 0x4000647f +#define CYREG_B0_UDB00_MSK 0x40006480 +#define CYREG_B0_UDB01_MSK 0x40006481 +#define CYREG_B0_UDB02_MSK 0x40006482 +#define CYREG_B0_UDB03_MSK 0x40006483 +#define CYREG_B0_UDB04_MSK 0x40006484 +#define CYREG_B0_UDB05_MSK 0x40006485 +#define CYREG_B0_UDB06_MSK 0x40006486 +#define CYREG_B0_UDB07_MSK 0x40006487 +#define CYREG_B0_UDB08_MSK 0x40006488 +#define CYREG_B0_UDB09_MSK 0x40006489 +#define CYREG_B0_UDB10_MSK 0x4000648a +#define CYREG_B0_UDB11_MSK 0x4000648b +#define CYREG_B0_UDB12_MSK 0x4000648c +#define CYREG_B0_UDB13_MSK 0x4000648d +#define CYREG_B0_UDB14_MSK 0x4000648e +#define CYREG_B0_UDB15_MSK 0x4000648f +#define CYREG_B0_UDB00_ACTL 0x40006490 +#define CYREG_B0_UDB01_ACTL 0x40006491 +#define CYREG_B0_UDB02_ACTL 0x40006492 +#define CYREG_B0_UDB03_ACTL 0x40006493 +#define CYREG_B0_UDB04_ACTL 0x40006494 +#define CYREG_B0_UDB05_ACTL 0x40006495 +#define CYREG_B0_UDB06_ACTL 0x40006496 +#define CYREG_B0_UDB07_ACTL 0x40006497 +#define CYREG_B0_UDB08_ACTL 0x40006498 +#define CYREG_B0_UDB09_ACTL 0x40006499 +#define CYREG_B0_UDB10_ACTL 0x4000649a +#define CYREG_B0_UDB11_ACTL 0x4000649b +#define CYREG_B0_UDB12_ACTL 0x4000649c +#define CYREG_B0_UDB13_ACTL 0x4000649d +#define CYREG_B0_UDB14_ACTL 0x4000649e +#define CYREG_B0_UDB15_ACTL 0x4000649f +#define CYREG_B0_UDB00_MC 0x400064a0 +#define CYREG_B0_UDB01_MC 0x400064a1 +#define CYREG_B0_UDB02_MC 0x400064a2 +#define CYREG_B0_UDB03_MC 0x400064a3 +#define CYREG_B0_UDB04_MC 0x400064a4 +#define CYREG_B0_UDB05_MC 0x400064a5 +#define CYREG_B0_UDB06_MC 0x400064a6 +#define CYREG_B0_UDB07_MC 0x400064a7 +#define CYREG_B0_UDB08_MC 0x400064a8 +#define CYREG_B0_UDB09_MC 0x400064a9 +#define CYREG_B0_UDB10_MC 0x400064aa +#define CYREG_B0_UDB11_MC 0x400064ab +#define CYREG_B0_UDB12_MC 0x400064ac +#define CYREG_B0_UDB13_MC 0x400064ad +#define CYREG_B0_UDB14_MC 0x400064ae +#define CYREG_B0_UDB15_MC 0x400064af +#define CYDEV_UWRK_UWRK8_B1_BASE 0x40006500 +#define CYDEV_UWRK_UWRK8_B1_SIZE 0x000000b0 +#define CYREG_B1_UDB04_A0 0x40006504 +#define CYREG_B1_UDB05_A0 0x40006505 +#define CYREG_B1_UDB06_A0 0x40006506 +#define CYREG_B1_UDB07_A0 0x40006507 +#define CYREG_B1_UDB08_A0 0x40006508 +#define CYREG_B1_UDB09_A0 0x40006509 +#define CYREG_B1_UDB10_A0 0x4000650a +#define CYREG_B1_UDB11_A0 0x4000650b +#define CYREG_B1_UDB04_A1 0x40006514 +#define CYREG_B1_UDB05_A1 0x40006515 +#define CYREG_B1_UDB06_A1 0x40006516 +#define CYREG_B1_UDB07_A1 0x40006517 +#define CYREG_B1_UDB08_A1 0x40006518 +#define CYREG_B1_UDB09_A1 0x40006519 +#define CYREG_B1_UDB10_A1 0x4000651a +#define CYREG_B1_UDB11_A1 0x4000651b +#define CYREG_B1_UDB04_D0 0x40006524 +#define CYREG_B1_UDB05_D0 0x40006525 +#define CYREG_B1_UDB06_D0 0x40006526 +#define CYREG_B1_UDB07_D0 0x40006527 +#define CYREG_B1_UDB08_D0 0x40006528 +#define CYREG_B1_UDB09_D0 0x40006529 +#define CYREG_B1_UDB10_D0 0x4000652a +#define CYREG_B1_UDB11_D0 0x4000652b +#define CYREG_B1_UDB04_D1 0x40006534 +#define CYREG_B1_UDB05_D1 0x40006535 +#define CYREG_B1_UDB06_D1 0x40006536 +#define CYREG_B1_UDB07_D1 0x40006537 +#define CYREG_B1_UDB08_D1 0x40006538 +#define CYREG_B1_UDB09_D1 0x40006539 +#define CYREG_B1_UDB10_D1 0x4000653a +#define CYREG_B1_UDB11_D1 0x4000653b +#define CYREG_B1_UDB04_F0 0x40006544 +#define CYREG_B1_UDB05_F0 0x40006545 +#define CYREG_B1_UDB06_F0 0x40006546 +#define CYREG_B1_UDB07_F0 0x40006547 +#define CYREG_B1_UDB08_F0 0x40006548 +#define CYREG_B1_UDB09_F0 0x40006549 +#define CYREG_B1_UDB10_F0 0x4000654a +#define CYREG_B1_UDB11_F0 0x4000654b +#define CYREG_B1_UDB04_F1 0x40006554 +#define CYREG_B1_UDB05_F1 0x40006555 +#define CYREG_B1_UDB06_F1 0x40006556 +#define CYREG_B1_UDB07_F1 0x40006557 +#define CYREG_B1_UDB08_F1 0x40006558 +#define CYREG_B1_UDB09_F1 0x40006559 +#define CYREG_B1_UDB10_F1 0x4000655a +#define CYREG_B1_UDB11_F1 0x4000655b +#define CYREG_B1_UDB04_ST 0x40006564 +#define CYREG_B1_UDB05_ST 0x40006565 +#define CYREG_B1_UDB06_ST 0x40006566 +#define CYREG_B1_UDB07_ST 0x40006567 +#define CYREG_B1_UDB08_ST 0x40006568 +#define CYREG_B1_UDB09_ST 0x40006569 +#define CYREG_B1_UDB10_ST 0x4000656a +#define CYREG_B1_UDB11_ST 0x4000656b +#define CYREG_B1_UDB04_CTL 0x40006574 +#define CYREG_B1_UDB05_CTL 0x40006575 +#define CYREG_B1_UDB06_CTL 0x40006576 +#define CYREG_B1_UDB07_CTL 0x40006577 +#define CYREG_B1_UDB08_CTL 0x40006578 +#define CYREG_B1_UDB09_CTL 0x40006579 +#define CYREG_B1_UDB10_CTL 0x4000657a +#define CYREG_B1_UDB11_CTL 0x4000657b +#define CYREG_B1_UDB04_MSK 0x40006584 +#define CYREG_B1_UDB05_MSK 0x40006585 +#define CYREG_B1_UDB06_MSK 0x40006586 +#define CYREG_B1_UDB07_MSK 0x40006587 +#define CYREG_B1_UDB08_MSK 0x40006588 +#define CYREG_B1_UDB09_MSK 0x40006589 +#define CYREG_B1_UDB10_MSK 0x4000658a +#define CYREG_B1_UDB11_MSK 0x4000658b +#define CYREG_B1_UDB04_ACTL 0x40006594 +#define CYREG_B1_UDB05_ACTL 0x40006595 +#define CYREG_B1_UDB06_ACTL 0x40006596 +#define CYREG_B1_UDB07_ACTL 0x40006597 +#define CYREG_B1_UDB08_ACTL 0x40006598 +#define CYREG_B1_UDB09_ACTL 0x40006599 +#define CYREG_B1_UDB10_ACTL 0x4000659a +#define CYREG_B1_UDB11_ACTL 0x4000659b +#define CYREG_B1_UDB04_MC 0x400065a4 +#define CYREG_B1_UDB05_MC 0x400065a5 +#define CYREG_B1_UDB06_MC 0x400065a6 +#define CYREG_B1_UDB07_MC 0x400065a7 +#define CYREG_B1_UDB08_MC 0x400065a8 +#define CYREG_B1_UDB09_MC 0x400065a9 +#define CYREG_B1_UDB10_MC 0x400065aa +#define CYREG_B1_UDB11_MC 0x400065ab +#define CYDEV_UWRK_UWRK16_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_SIZE 0x00000760 +#define CYDEV_UWRK_UWRK16_CAT_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_CAT_SIZE 0x00000760 +#define CYDEV_UWRK_UWRK16_CAT_B0_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_CAT_B0_SIZE 0x00000160 +#define CYREG_B0_UDB00_A0_A1 0x40006800 +#define CYREG_B0_UDB01_A0_A1 0x40006802 +#define CYREG_B0_UDB02_A0_A1 0x40006804 +#define CYREG_B0_UDB03_A0_A1 0x40006806 +#define CYREG_B0_UDB04_A0_A1 0x40006808 +#define CYREG_B0_UDB05_A0_A1 0x4000680a +#define CYREG_B0_UDB06_A0_A1 0x4000680c +#define CYREG_B0_UDB07_A0_A1 0x4000680e +#define CYREG_B0_UDB08_A0_A1 0x40006810 +#define CYREG_B0_UDB09_A0_A1 0x40006812 +#define CYREG_B0_UDB10_A0_A1 0x40006814 +#define CYREG_B0_UDB11_A0_A1 0x40006816 +#define CYREG_B0_UDB12_A0_A1 0x40006818 +#define CYREG_B0_UDB13_A0_A1 0x4000681a +#define CYREG_B0_UDB14_A0_A1 0x4000681c +#define CYREG_B0_UDB15_A0_A1 0x4000681e +#define CYREG_B0_UDB00_D0_D1 0x40006840 +#define CYREG_B0_UDB01_D0_D1 0x40006842 +#define CYREG_B0_UDB02_D0_D1 0x40006844 +#define CYREG_B0_UDB03_D0_D1 0x40006846 +#define CYREG_B0_UDB04_D0_D1 0x40006848 +#define CYREG_B0_UDB05_D0_D1 0x4000684a +#define CYREG_B0_UDB06_D0_D1 0x4000684c +#define CYREG_B0_UDB07_D0_D1 0x4000684e +#define CYREG_B0_UDB08_D0_D1 0x40006850 +#define CYREG_B0_UDB09_D0_D1 0x40006852 +#define CYREG_B0_UDB10_D0_D1 0x40006854 +#define CYREG_B0_UDB11_D0_D1 0x40006856 +#define CYREG_B0_UDB12_D0_D1 0x40006858 +#define CYREG_B0_UDB13_D0_D1 0x4000685a +#define CYREG_B0_UDB14_D0_D1 0x4000685c +#define CYREG_B0_UDB15_D0_D1 0x4000685e +#define CYREG_B0_UDB00_F0_F1 0x40006880 +#define CYREG_B0_UDB01_F0_F1 0x40006882 +#define CYREG_B0_UDB02_F0_F1 0x40006884 +#define CYREG_B0_UDB03_F0_F1 0x40006886 +#define CYREG_B0_UDB04_F0_F1 0x40006888 +#define CYREG_B0_UDB05_F0_F1 0x4000688a +#define CYREG_B0_UDB06_F0_F1 0x4000688c +#define CYREG_B0_UDB07_F0_F1 0x4000688e +#define CYREG_B0_UDB08_F0_F1 0x40006890 +#define CYREG_B0_UDB09_F0_F1 0x40006892 +#define CYREG_B0_UDB10_F0_F1 0x40006894 +#define CYREG_B0_UDB11_F0_F1 0x40006896 +#define CYREG_B0_UDB12_F0_F1 0x40006898 +#define CYREG_B0_UDB13_F0_F1 0x4000689a +#define CYREG_B0_UDB14_F0_F1 0x4000689c +#define CYREG_B0_UDB15_F0_F1 0x4000689e +#define CYREG_B0_UDB00_ST_CTL 0x400068c0 +#define CYREG_B0_UDB01_ST_CTL 0x400068c2 +#define CYREG_B0_UDB02_ST_CTL 0x400068c4 +#define CYREG_B0_UDB03_ST_CTL 0x400068c6 +#define CYREG_B0_UDB04_ST_CTL 0x400068c8 +#define CYREG_B0_UDB05_ST_CTL 0x400068ca +#define CYREG_B0_UDB06_ST_CTL 0x400068cc +#define CYREG_B0_UDB07_ST_CTL 0x400068ce +#define CYREG_B0_UDB08_ST_CTL 0x400068d0 +#define CYREG_B0_UDB09_ST_CTL 0x400068d2 +#define CYREG_B0_UDB10_ST_CTL 0x400068d4 +#define CYREG_B0_UDB11_ST_CTL 0x400068d6 +#define CYREG_B0_UDB12_ST_CTL 0x400068d8 +#define CYREG_B0_UDB13_ST_CTL 0x400068da +#define CYREG_B0_UDB14_ST_CTL 0x400068dc +#define CYREG_B0_UDB15_ST_CTL 0x400068de +#define CYREG_B0_UDB00_MSK_ACTL 0x40006900 +#define CYREG_B0_UDB01_MSK_ACTL 0x40006902 +#define CYREG_B0_UDB02_MSK_ACTL 0x40006904 +#define CYREG_B0_UDB03_MSK_ACTL 0x40006906 +#define CYREG_B0_UDB04_MSK_ACTL 0x40006908 +#define CYREG_B0_UDB05_MSK_ACTL 0x4000690a +#define CYREG_B0_UDB06_MSK_ACTL 0x4000690c +#define CYREG_B0_UDB07_MSK_ACTL 0x4000690e +#define CYREG_B0_UDB08_MSK_ACTL 0x40006910 +#define CYREG_B0_UDB09_MSK_ACTL 0x40006912 +#define CYREG_B0_UDB10_MSK_ACTL 0x40006914 +#define CYREG_B0_UDB11_MSK_ACTL 0x40006916 +#define CYREG_B0_UDB12_MSK_ACTL 0x40006918 +#define CYREG_B0_UDB13_MSK_ACTL 0x4000691a +#define CYREG_B0_UDB14_MSK_ACTL 0x4000691c +#define CYREG_B0_UDB15_MSK_ACTL 0x4000691e +#define CYREG_B0_UDB00_MC_00 0x40006940 +#define CYREG_B0_UDB01_MC_00 0x40006942 +#define CYREG_B0_UDB02_MC_00 0x40006944 +#define CYREG_B0_UDB03_MC_00 0x40006946 +#define CYREG_B0_UDB04_MC_00 0x40006948 +#define CYREG_B0_UDB05_MC_00 0x4000694a +#define CYREG_B0_UDB06_MC_00 0x4000694c +#define CYREG_B0_UDB07_MC_00 0x4000694e +#define CYREG_B0_UDB08_MC_00 0x40006950 +#define CYREG_B0_UDB09_MC_00 0x40006952 +#define CYREG_B0_UDB10_MC_00 0x40006954 +#define CYREG_B0_UDB11_MC_00 0x40006956 +#define CYREG_B0_UDB12_MC_00 0x40006958 +#define CYREG_B0_UDB13_MC_00 0x4000695a +#define CYREG_B0_UDB14_MC_00 0x4000695c +#define CYREG_B0_UDB15_MC_00 0x4000695e +#define CYDEV_UWRK_UWRK16_CAT_B1_BASE 0x40006a00 +#define CYDEV_UWRK_UWRK16_CAT_B1_SIZE 0x00000160 +#define CYREG_B1_UDB04_A0_A1 0x40006a08 +#define CYREG_B1_UDB05_A0_A1 0x40006a0a +#define CYREG_B1_UDB06_A0_A1 0x40006a0c +#define CYREG_B1_UDB07_A0_A1 0x40006a0e +#define CYREG_B1_UDB08_A0_A1 0x40006a10 +#define CYREG_B1_UDB09_A0_A1 0x40006a12 +#define CYREG_B1_UDB10_A0_A1 0x40006a14 +#define CYREG_B1_UDB11_A0_A1 0x40006a16 +#define CYREG_B1_UDB04_D0_D1 0x40006a48 +#define CYREG_B1_UDB05_D0_D1 0x40006a4a +#define CYREG_B1_UDB06_D0_D1 0x40006a4c +#define CYREG_B1_UDB07_D0_D1 0x40006a4e +#define CYREG_B1_UDB08_D0_D1 0x40006a50 +#define CYREG_B1_UDB09_D0_D1 0x40006a52 +#define CYREG_B1_UDB10_D0_D1 0x40006a54 +#define CYREG_B1_UDB11_D0_D1 0x40006a56 +#define CYREG_B1_UDB04_F0_F1 0x40006a88 +#define CYREG_B1_UDB05_F0_F1 0x40006a8a +#define CYREG_B1_UDB06_F0_F1 0x40006a8c +#define CYREG_B1_UDB07_F0_F1 0x40006a8e +#define CYREG_B1_UDB08_F0_F1 0x40006a90 +#define CYREG_B1_UDB09_F0_F1 0x40006a92 +#define CYREG_B1_UDB10_F0_F1 0x40006a94 +#define CYREG_B1_UDB11_F0_F1 0x40006a96 +#define CYREG_B1_UDB04_ST_CTL 0x40006ac8 +#define CYREG_B1_UDB05_ST_CTL 0x40006aca +#define CYREG_B1_UDB06_ST_CTL 0x40006acc +#define CYREG_B1_UDB07_ST_CTL 0x40006ace +#define CYREG_B1_UDB08_ST_CTL 0x40006ad0 +#define CYREG_B1_UDB09_ST_CTL 0x40006ad2 +#define CYREG_B1_UDB10_ST_CTL 0x40006ad4 +#define CYREG_B1_UDB11_ST_CTL 0x40006ad6 +#define CYREG_B1_UDB04_MSK_ACTL 0x40006b08 +#define CYREG_B1_UDB05_MSK_ACTL 0x40006b0a +#define CYREG_B1_UDB06_MSK_ACTL 0x40006b0c +#define CYREG_B1_UDB07_MSK_ACTL 0x40006b0e +#define CYREG_B1_UDB08_MSK_ACTL 0x40006b10 +#define CYREG_B1_UDB09_MSK_ACTL 0x40006b12 +#define CYREG_B1_UDB10_MSK_ACTL 0x40006b14 +#define CYREG_B1_UDB11_MSK_ACTL 0x40006b16 +#define CYREG_B1_UDB04_MC_00 0x40006b48 +#define CYREG_B1_UDB05_MC_00 0x40006b4a +#define CYREG_B1_UDB06_MC_00 0x40006b4c +#define CYREG_B1_UDB07_MC_00 0x40006b4e +#define CYREG_B1_UDB08_MC_00 0x40006b50 +#define CYREG_B1_UDB09_MC_00 0x40006b52 +#define CYREG_B1_UDB10_MC_00 0x40006b54 +#define CYREG_B1_UDB11_MC_00 0x40006b56 +#define CYDEV_UWRK_UWRK16_DEF_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_DEF_SIZE 0x0000075e +#define CYDEV_UWRK_UWRK16_DEF_B0_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_DEF_B0_SIZE 0x0000015e +#define CYREG_B0_UDB00_01_A0 0x40006800 +#define CYREG_B0_UDB01_02_A0 0x40006802 +#define CYREG_B0_UDB02_03_A0 0x40006804 +#define CYREG_B0_UDB03_04_A0 0x40006806 +#define CYREG_B0_UDB04_05_A0 0x40006808 +#define CYREG_B0_UDB05_06_A0 0x4000680a +#define CYREG_B0_UDB06_07_A0 0x4000680c +#define CYREG_B0_UDB07_08_A0 0x4000680e +#define CYREG_B0_UDB08_09_A0 0x40006810 +#define CYREG_B0_UDB09_10_A0 0x40006812 +#define CYREG_B0_UDB10_11_A0 0x40006814 +#define CYREG_B0_UDB11_12_A0 0x40006816 +#define CYREG_B0_UDB12_13_A0 0x40006818 +#define CYREG_B0_UDB13_14_A0 0x4000681a +#define CYREG_B0_UDB14_15_A0 0x4000681c +#define CYREG_B0_UDB00_01_A1 0x40006820 +#define CYREG_B0_UDB01_02_A1 0x40006822 +#define CYREG_B0_UDB02_03_A1 0x40006824 +#define CYREG_B0_UDB03_04_A1 0x40006826 +#define CYREG_B0_UDB04_05_A1 0x40006828 +#define CYREG_B0_UDB05_06_A1 0x4000682a +#define CYREG_B0_UDB06_07_A1 0x4000682c +#define CYREG_B0_UDB07_08_A1 0x4000682e +#define CYREG_B0_UDB08_09_A1 0x40006830 +#define CYREG_B0_UDB09_10_A1 0x40006832 +#define CYREG_B0_UDB10_11_A1 0x40006834 +#define CYREG_B0_UDB11_12_A1 0x40006836 +#define CYREG_B0_UDB12_13_A1 0x40006838 +#define CYREG_B0_UDB13_14_A1 0x4000683a +#define CYREG_B0_UDB14_15_A1 0x4000683c +#define CYREG_B0_UDB00_01_D0 0x40006840 +#define CYREG_B0_UDB01_02_D0 0x40006842 +#define CYREG_B0_UDB02_03_D0 0x40006844 +#define CYREG_B0_UDB03_04_D0 0x40006846 +#define CYREG_B0_UDB04_05_D0 0x40006848 +#define CYREG_B0_UDB05_06_D0 0x4000684a +#define CYREG_B0_UDB06_07_D0 0x4000684c +#define CYREG_B0_UDB07_08_D0 0x4000684e +#define CYREG_B0_UDB08_09_D0 0x40006850 +#define CYREG_B0_UDB09_10_D0 0x40006852 +#define CYREG_B0_UDB10_11_D0 0x40006854 +#define CYREG_B0_UDB11_12_D0 0x40006856 +#define CYREG_B0_UDB12_13_D0 0x40006858 +#define CYREG_B0_UDB13_14_D0 0x4000685a +#define CYREG_B0_UDB14_15_D0 0x4000685c +#define CYREG_B0_UDB00_01_D1 0x40006860 +#define CYREG_B0_UDB01_02_D1 0x40006862 +#define CYREG_B0_UDB02_03_D1 0x40006864 +#define CYREG_B0_UDB03_04_D1 0x40006866 +#define CYREG_B0_UDB04_05_D1 0x40006868 +#define CYREG_B0_UDB05_06_D1 0x4000686a +#define CYREG_B0_UDB06_07_D1 0x4000686c +#define CYREG_B0_UDB07_08_D1 0x4000686e +#define CYREG_B0_UDB08_09_D1 0x40006870 +#define CYREG_B0_UDB09_10_D1 0x40006872 +#define CYREG_B0_UDB10_11_D1 0x40006874 +#define CYREG_B0_UDB11_12_D1 0x40006876 +#define CYREG_B0_UDB12_13_D1 0x40006878 +#define CYREG_B0_UDB13_14_D1 0x4000687a +#define CYREG_B0_UDB14_15_D1 0x4000687c +#define CYREG_B0_UDB00_01_F0 0x40006880 +#define CYREG_B0_UDB01_02_F0 0x40006882 +#define CYREG_B0_UDB02_03_F0 0x40006884 +#define CYREG_B0_UDB03_04_F0 0x40006886 +#define CYREG_B0_UDB04_05_F0 0x40006888 +#define CYREG_B0_UDB05_06_F0 0x4000688a +#define CYREG_B0_UDB06_07_F0 0x4000688c +#define CYREG_B0_UDB07_08_F0 0x4000688e +#define CYREG_B0_UDB08_09_F0 0x40006890 +#define CYREG_B0_UDB09_10_F0 0x40006892 +#define CYREG_B0_UDB10_11_F0 0x40006894 +#define CYREG_B0_UDB11_12_F0 0x40006896 +#define CYREG_B0_UDB12_13_F0 0x40006898 +#define CYREG_B0_UDB13_14_F0 0x4000689a +#define CYREG_B0_UDB14_15_F0 0x4000689c +#define CYREG_B0_UDB00_01_F1 0x400068a0 +#define CYREG_B0_UDB01_02_F1 0x400068a2 +#define CYREG_B0_UDB02_03_F1 0x400068a4 +#define CYREG_B0_UDB03_04_F1 0x400068a6 +#define CYREG_B0_UDB04_05_F1 0x400068a8 +#define CYREG_B0_UDB05_06_F1 0x400068aa +#define CYREG_B0_UDB06_07_F1 0x400068ac +#define CYREG_B0_UDB07_08_F1 0x400068ae +#define CYREG_B0_UDB08_09_F1 0x400068b0 +#define CYREG_B0_UDB09_10_F1 0x400068b2 +#define CYREG_B0_UDB10_11_F1 0x400068b4 +#define CYREG_B0_UDB11_12_F1 0x400068b6 +#define CYREG_B0_UDB12_13_F1 0x400068b8 +#define CYREG_B0_UDB13_14_F1 0x400068ba +#define CYREG_B0_UDB14_15_F1 0x400068bc +#define CYREG_B0_UDB00_01_ST 0x400068c0 +#define CYREG_B0_UDB01_02_ST 0x400068c2 +#define CYREG_B0_UDB02_03_ST 0x400068c4 +#define CYREG_B0_UDB03_04_ST 0x400068c6 +#define CYREG_B0_UDB04_05_ST 0x400068c8 +#define CYREG_B0_UDB05_06_ST 0x400068ca +#define CYREG_B0_UDB06_07_ST 0x400068cc +#define CYREG_B0_UDB07_08_ST 0x400068ce +#define CYREG_B0_UDB08_09_ST 0x400068d0 +#define CYREG_B0_UDB09_10_ST 0x400068d2 +#define CYREG_B0_UDB10_11_ST 0x400068d4 +#define CYREG_B0_UDB11_12_ST 0x400068d6 +#define CYREG_B0_UDB12_13_ST 0x400068d8 +#define CYREG_B0_UDB13_14_ST 0x400068da +#define CYREG_B0_UDB14_15_ST 0x400068dc +#define CYREG_B0_UDB00_01_CTL 0x400068e0 +#define CYREG_B0_UDB01_02_CTL 0x400068e2 +#define CYREG_B0_UDB02_03_CTL 0x400068e4 +#define CYREG_B0_UDB03_04_CTL 0x400068e6 +#define CYREG_B0_UDB04_05_CTL 0x400068e8 +#define CYREG_B0_UDB05_06_CTL 0x400068ea +#define CYREG_B0_UDB06_07_CTL 0x400068ec +#define CYREG_B0_UDB07_08_CTL 0x400068ee +#define CYREG_B0_UDB08_09_CTL 0x400068f0 +#define CYREG_B0_UDB09_10_CTL 0x400068f2 +#define CYREG_B0_UDB10_11_CTL 0x400068f4 +#define CYREG_B0_UDB11_12_CTL 0x400068f6 +#define CYREG_B0_UDB12_13_CTL 0x400068f8 +#define CYREG_B0_UDB13_14_CTL 0x400068fa +#define CYREG_B0_UDB14_15_CTL 0x400068fc +#define CYREG_B0_UDB00_01_MSK 0x40006900 +#define CYREG_B0_UDB01_02_MSK 0x40006902 +#define CYREG_B0_UDB02_03_MSK 0x40006904 +#define CYREG_B0_UDB03_04_MSK 0x40006906 +#define CYREG_B0_UDB04_05_MSK 0x40006908 +#define CYREG_B0_UDB05_06_MSK 0x4000690a +#define CYREG_B0_UDB06_07_MSK 0x4000690c +#define CYREG_B0_UDB07_08_MSK 0x4000690e +#define CYREG_B0_UDB08_09_MSK 0x40006910 +#define CYREG_B0_UDB09_10_MSK 0x40006912 +#define CYREG_B0_UDB10_11_MSK 0x40006914 +#define CYREG_B0_UDB11_12_MSK 0x40006916 +#define CYREG_B0_UDB12_13_MSK 0x40006918 +#define CYREG_B0_UDB13_14_MSK 0x4000691a +#define CYREG_B0_UDB14_15_MSK 0x4000691c +#define CYREG_B0_UDB00_01_ACTL 0x40006920 +#define CYREG_B0_UDB01_02_ACTL 0x40006922 +#define CYREG_B0_UDB02_03_ACTL 0x40006924 +#define CYREG_B0_UDB03_04_ACTL 0x40006926 +#define CYREG_B0_UDB04_05_ACTL 0x40006928 +#define CYREG_B0_UDB05_06_ACTL 0x4000692a +#define CYREG_B0_UDB06_07_ACTL 0x4000692c +#define CYREG_B0_UDB07_08_ACTL 0x4000692e +#define CYREG_B0_UDB08_09_ACTL 0x40006930 +#define CYREG_B0_UDB09_10_ACTL 0x40006932 +#define CYREG_B0_UDB10_11_ACTL 0x40006934 +#define CYREG_B0_UDB11_12_ACTL 0x40006936 +#define CYREG_B0_UDB12_13_ACTL 0x40006938 +#define CYREG_B0_UDB13_14_ACTL 0x4000693a +#define CYREG_B0_UDB14_15_ACTL 0x4000693c +#define CYREG_B0_UDB00_01_MC 0x40006940 +#define CYREG_B0_UDB01_02_MC 0x40006942 +#define CYREG_B0_UDB02_03_MC 0x40006944 +#define CYREG_B0_UDB03_04_MC 0x40006946 +#define CYREG_B0_UDB04_05_MC 0x40006948 +#define CYREG_B0_UDB05_06_MC 0x4000694a +#define CYREG_B0_UDB06_07_MC 0x4000694c +#define CYREG_B0_UDB07_08_MC 0x4000694e +#define CYREG_B0_UDB08_09_MC 0x40006950 +#define CYREG_B0_UDB09_10_MC 0x40006952 +#define CYREG_B0_UDB10_11_MC 0x40006954 +#define CYREG_B0_UDB11_12_MC 0x40006956 +#define CYREG_B0_UDB12_13_MC 0x40006958 +#define CYREG_B0_UDB13_14_MC 0x4000695a +#define CYREG_B0_UDB14_15_MC 0x4000695c +#define CYDEV_UWRK_UWRK16_DEF_B1_BASE 0x40006a00 +#define CYDEV_UWRK_UWRK16_DEF_B1_SIZE 0x0000015e +#define CYREG_B1_UDB04_05_A0 0x40006a08 +#define CYREG_B1_UDB05_06_A0 0x40006a0a +#define CYREG_B1_UDB06_07_A0 0x40006a0c +#define CYREG_B1_UDB07_08_A0 0x40006a0e +#define CYREG_B1_UDB08_09_A0 0x40006a10 +#define CYREG_B1_UDB09_10_A0 0x40006a12 +#define CYREG_B1_UDB10_11_A0 0x40006a14 +#define CYREG_B1_UDB11_12_A0 0x40006a16 +#define CYREG_B1_UDB04_05_A1 0x40006a28 +#define CYREG_B1_UDB05_06_A1 0x40006a2a +#define CYREG_B1_UDB06_07_A1 0x40006a2c +#define CYREG_B1_UDB07_08_A1 0x40006a2e +#define CYREG_B1_UDB08_09_A1 0x40006a30 +#define CYREG_B1_UDB09_10_A1 0x40006a32 +#define CYREG_B1_UDB10_11_A1 0x40006a34 +#define CYREG_B1_UDB11_12_A1 0x40006a36 +#define CYREG_B1_UDB04_05_D0 0x40006a48 +#define CYREG_B1_UDB05_06_D0 0x40006a4a +#define CYREG_B1_UDB06_07_D0 0x40006a4c +#define CYREG_B1_UDB07_08_D0 0x40006a4e +#define CYREG_B1_UDB08_09_D0 0x40006a50 +#define CYREG_B1_UDB09_10_D0 0x40006a52 +#define CYREG_B1_UDB10_11_D0 0x40006a54 +#define CYREG_B1_UDB11_12_D0 0x40006a56 +#define CYREG_B1_UDB04_05_D1 0x40006a68 +#define CYREG_B1_UDB05_06_D1 0x40006a6a +#define CYREG_B1_UDB06_07_D1 0x40006a6c +#define CYREG_B1_UDB07_08_D1 0x40006a6e +#define CYREG_B1_UDB08_09_D1 0x40006a70 +#define CYREG_B1_UDB09_10_D1 0x40006a72 +#define CYREG_B1_UDB10_11_D1 0x40006a74 +#define CYREG_B1_UDB11_12_D1 0x40006a76 +#define CYREG_B1_UDB04_05_F0 0x40006a88 +#define CYREG_B1_UDB05_06_F0 0x40006a8a +#define CYREG_B1_UDB06_07_F0 0x40006a8c +#define CYREG_B1_UDB07_08_F0 0x40006a8e +#define CYREG_B1_UDB08_09_F0 0x40006a90 +#define CYREG_B1_UDB09_10_F0 0x40006a92 +#define CYREG_B1_UDB10_11_F0 0x40006a94 +#define CYREG_B1_UDB11_12_F0 0x40006a96 +#define CYREG_B1_UDB04_05_F1 0x40006aa8 +#define CYREG_B1_UDB05_06_F1 0x40006aaa +#define CYREG_B1_UDB06_07_F1 0x40006aac +#define CYREG_B1_UDB07_08_F1 0x40006aae +#define CYREG_B1_UDB08_09_F1 0x40006ab0 +#define CYREG_B1_UDB09_10_F1 0x40006ab2 +#define CYREG_B1_UDB10_11_F1 0x40006ab4 +#define CYREG_B1_UDB11_12_F1 0x40006ab6 +#define CYREG_B1_UDB04_05_ST 0x40006ac8 +#define CYREG_B1_UDB05_06_ST 0x40006aca +#define CYREG_B1_UDB06_07_ST 0x40006acc +#define CYREG_B1_UDB07_08_ST 0x40006ace +#define CYREG_B1_UDB08_09_ST 0x40006ad0 +#define CYREG_B1_UDB09_10_ST 0x40006ad2 +#define CYREG_B1_UDB10_11_ST 0x40006ad4 +#define CYREG_B1_UDB11_12_ST 0x40006ad6 +#define CYREG_B1_UDB04_05_CTL 0x40006ae8 +#define CYREG_B1_UDB05_06_CTL 0x40006aea +#define CYREG_B1_UDB06_07_CTL 0x40006aec +#define CYREG_B1_UDB07_08_CTL 0x40006aee +#define CYREG_B1_UDB08_09_CTL 0x40006af0 +#define CYREG_B1_UDB09_10_CTL 0x40006af2 +#define CYREG_B1_UDB10_11_CTL 0x40006af4 +#define CYREG_B1_UDB11_12_CTL 0x40006af6 +#define CYREG_B1_UDB04_05_MSK 0x40006b08 +#define CYREG_B1_UDB05_06_MSK 0x40006b0a +#define CYREG_B1_UDB06_07_MSK 0x40006b0c +#define CYREG_B1_UDB07_08_MSK 0x40006b0e +#define CYREG_B1_UDB08_09_MSK 0x40006b10 +#define CYREG_B1_UDB09_10_MSK 0x40006b12 +#define CYREG_B1_UDB10_11_MSK 0x40006b14 +#define CYREG_B1_UDB11_12_MSK 0x40006b16 +#define CYREG_B1_UDB04_05_ACTL 0x40006b28 +#define CYREG_B1_UDB05_06_ACTL 0x40006b2a +#define CYREG_B1_UDB06_07_ACTL 0x40006b2c +#define CYREG_B1_UDB07_08_ACTL 0x40006b2e +#define CYREG_B1_UDB08_09_ACTL 0x40006b30 +#define CYREG_B1_UDB09_10_ACTL 0x40006b32 +#define CYREG_B1_UDB10_11_ACTL 0x40006b34 +#define CYREG_B1_UDB11_12_ACTL 0x40006b36 +#define CYREG_B1_UDB04_05_MC 0x40006b48 +#define CYREG_B1_UDB05_06_MC 0x40006b4a +#define CYREG_B1_UDB06_07_MC 0x40006b4c +#define CYREG_B1_UDB07_08_MC 0x40006b4e +#define CYREG_B1_UDB08_09_MC 0x40006b50 +#define CYREG_B1_UDB09_10_MC 0x40006b52 +#define CYREG_B1_UDB10_11_MC 0x40006b54 +#define CYREG_B1_UDB11_12_MC 0x40006b56 +#define CYDEV_PHUB_BASE 0x40007000 +#define CYDEV_PHUB_SIZE 0x00000c00 +#define CYREG_PHUB_CFG 0x40007000 +#define CYREG_PHUB_ERR 0x40007004 +#define CYREG_PHUB_ERR_ADR 0x40007008 +#define CYDEV_PHUB_CH0_BASE 0x40007010 +#define CYDEV_PHUB_CH0_SIZE 0x0000000c +#define CYREG_PHUB_CH0_BASIC_CFG 0x40007010 +#define CYREG_PHUB_CH0_ACTION 0x40007014 +#define CYREG_PHUB_CH0_BASIC_STATUS 0x40007018 +#define CYDEV_PHUB_CH1_BASE 0x40007020 +#define CYDEV_PHUB_CH1_SIZE 0x0000000c +#define CYREG_PHUB_CH1_BASIC_CFG 0x40007020 +#define CYREG_PHUB_CH1_ACTION 0x40007024 +#define CYREG_PHUB_CH1_BASIC_STATUS 0x40007028 +#define CYDEV_PHUB_CH2_BASE 0x40007030 +#define CYDEV_PHUB_CH2_SIZE 0x0000000c +#define CYREG_PHUB_CH2_BASIC_CFG 0x40007030 +#define CYREG_PHUB_CH2_ACTION 0x40007034 +#define CYREG_PHUB_CH2_BASIC_STATUS 0x40007038 +#define CYDEV_PHUB_CH3_BASE 0x40007040 +#define CYDEV_PHUB_CH3_SIZE 0x0000000c +#define CYREG_PHUB_CH3_BASIC_CFG 0x40007040 +#define CYREG_PHUB_CH3_ACTION 0x40007044 +#define CYREG_PHUB_CH3_BASIC_STATUS 0x40007048 +#define CYDEV_PHUB_CH4_BASE 0x40007050 +#define CYDEV_PHUB_CH4_SIZE 0x0000000c +#define CYREG_PHUB_CH4_BASIC_CFG 0x40007050 +#define CYREG_PHUB_CH4_ACTION 0x40007054 +#define CYREG_PHUB_CH4_BASIC_STATUS 0x40007058 +#define CYDEV_PHUB_CH5_BASE 0x40007060 +#define CYDEV_PHUB_CH5_SIZE 0x0000000c +#define CYREG_PHUB_CH5_BASIC_CFG 0x40007060 +#define CYREG_PHUB_CH5_ACTION 0x40007064 +#define CYREG_PHUB_CH5_BASIC_STATUS 0x40007068 +#define CYDEV_PHUB_CH6_BASE 0x40007070 +#define CYDEV_PHUB_CH6_SIZE 0x0000000c +#define CYREG_PHUB_CH6_BASIC_CFG 0x40007070 +#define CYREG_PHUB_CH6_ACTION 0x40007074 +#define CYREG_PHUB_CH6_BASIC_STATUS 0x40007078 +#define CYDEV_PHUB_CH7_BASE 0x40007080 +#define CYDEV_PHUB_CH7_SIZE 0x0000000c +#define CYREG_PHUB_CH7_BASIC_CFG 0x40007080 +#define CYREG_PHUB_CH7_ACTION 0x40007084 +#define CYREG_PHUB_CH7_BASIC_STATUS 0x40007088 +#define CYDEV_PHUB_CH8_BASE 0x40007090 +#define CYDEV_PHUB_CH8_SIZE 0x0000000c +#define CYREG_PHUB_CH8_BASIC_CFG 0x40007090 +#define CYREG_PHUB_CH8_ACTION 0x40007094 +#define CYREG_PHUB_CH8_BASIC_STATUS 0x40007098 +#define CYDEV_PHUB_CH9_BASE 0x400070a0 +#define CYDEV_PHUB_CH9_SIZE 0x0000000c +#define CYREG_PHUB_CH9_BASIC_CFG 0x400070a0 +#define CYREG_PHUB_CH9_ACTION 0x400070a4 +#define CYREG_PHUB_CH9_BASIC_STATUS 0x400070a8 +#define CYDEV_PHUB_CH10_BASE 0x400070b0 +#define CYDEV_PHUB_CH10_SIZE 0x0000000c +#define CYREG_PHUB_CH10_BASIC_CFG 0x400070b0 +#define CYREG_PHUB_CH10_ACTION 0x400070b4 +#define CYREG_PHUB_CH10_BASIC_STATUS 0x400070b8 +#define CYDEV_PHUB_CH11_BASE 0x400070c0 +#define CYDEV_PHUB_CH11_SIZE 0x0000000c +#define CYREG_PHUB_CH11_BASIC_CFG 0x400070c0 +#define CYREG_PHUB_CH11_ACTION 0x400070c4 +#define CYREG_PHUB_CH11_BASIC_STATUS 0x400070c8 +#define CYDEV_PHUB_CH12_BASE 0x400070d0 +#define CYDEV_PHUB_CH12_SIZE 0x0000000c +#define CYREG_PHUB_CH12_BASIC_CFG 0x400070d0 +#define CYREG_PHUB_CH12_ACTION 0x400070d4 +#define CYREG_PHUB_CH12_BASIC_STATUS 0x400070d8 +#define CYDEV_PHUB_CH13_BASE 0x400070e0 +#define CYDEV_PHUB_CH13_SIZE 0x0000000c +#define CYREG_PHUB_CH13_BASIC_CFG 0x400070e0 +#define CYREG_PHUB_CH13_ACTION 0x400070e4 +#define CYREG_PHUB_CH13_BASIC_STATUS 0x400070e8 +#define CYDEV_PHUB_CH14_BASE 0x400070f0 +#define CYDEV_PHUB_CH14_SIZE 0x0000000c +#define CYREG_PHUB_CH14_BASIC_CFG 0x400070f0 +#define CYREG_PHUB_CH14_ACTION 0x400070f4 +#define CYREG_PHUB_CH14_BASIC_STATUS 0x400070f8 +#define CYDEV_PHUB_CH15_BASE 0x40007100 +#define CYDEV_PHUB_CH15_SIZE 0x0000000c +#define CYREG_PHUB_CH15_BASIC_CFG 0x40007100 +#define CYREG_PHUB_CH15_ACTION 0x40007104 +#define CYREG_PHUB_CH15_BASIC_STATUS 0x40007108 +#define CYDEV_PHUB_CH16_BASE 0x40007110 +#define CYDEV_PHUB_CH16_SIZE 0x0000000c +#define CYREG_PHUB_CH16_BASIC_CFG 0x40007110 +#define CYREG_PHUB_CH16_ACTION 0x40007114 +#define CYREG_PHUB_CH16_BASIC_STATUS 0x40007118 +#define CYDEV_PHUB_CH17_BASE 0x40007120 +#define CYDEV_PHUB_CH17_SIZE 0x0000000c +#define CYREG_PHUB_CH17_BASIC_CFG 0x40007120 +#define CYREG_PHUB_CH17_ACTION 0x40007124 +#define CYREG_PHUB_CH17_BASIC_STATUS 0x40007128 +#define CYDEV_PHUB_CH18_BASE 0x40007130 +#define CYDEV_PHUB_CH18_SIZE 0x0000000c +#define CYREG_PHUB_CH18_BASIC_CFG 0x40007130 +#define CYREG_PHUB_CH18_ACTION 0x40007134 +#define CYREG_PHUB_CH18_BASIC_STATUS 0x40007138 +#define CYDEV_PHUB_CH19_BASE 0x40007140 +#define CYDEV_PHUB_CH19_SIZE 0x0000000c +#define CYREG_PHUB_CH19_BASIC_CFG 0x40007140 +#define CYREG_PHUB_CH19_ACTION 0x40007144 +#define CYREG_PHUB_CH19_BASIC_STATUS 0x40007148 +#define CYDEV_PHUB_CH20_BASE 0x40007150 +#define CYDEV_PHUB_CH20_SIZE 0x0000000c +#define CYREG_PHUB_CH20_BASIC_CFG 0x40007150 +#define CYREG_PHUB_CH20_ACTION 0x40007154 +#define CYREG_PHUB_CH20_BASIC_STATUS 0x40007158 +#define CYDEV_PHUB_CH21_BASE 0x40007160 +#define CYDEV_PHUB_CH21_SIZE 0x0000000c +#define CYREG_PHUB_CH21_BASIC_CFG 0x40007160 +#define CYREG_PHUB_CH21_ACTION 0x40007164 +#define CYREG_PHUB_CH21_BASIC_STATUS 0x40007168 +#define CYDEV_PHUB_CH22_BASE 0x40007170 +#define CYDEV_PHUB_CH22_SIZE 0x0000000c +#define CYREG_PHUB_CH22_BASIC_CFG 0x40007170 +#define CYREG_PHUB_CH22_ACTION 0x40007174 +#define CYREG_PHUB_CH22_BASIC_STATUS 0x40007178 +#define CYDEV_PHUB_CH23_BASE 0x40007180 +#define CYDEV_PHUB_CH23_SIZE 0x0000000c +#define CYREG_PHUB_CH23_BASIC_CFG 0x40007180 +#define CYREG_PHUB_CH23_ACTION 0x40007184 +#define CYREG_PHUB_CH23_BASIC_STATUS 0x40007188 +#define CYDEV_PHUB_CFGMEM0_BASE 0x40007600 +#define CYDEV_PHUB_CFGMEM0_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM0_CFG0 0x40007600 +#define CYREG_PHUB_CFGMEM0_CFG1 0x40007604 +#define CYDEV_PHUB_CFGMEM1_BASE 0x40007608 +#define CYDEV_PHUB_CFGMEM1_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM1_CFG0 0x40007608 +#define CYREG_PHUB_CFGMEM1_CFG1 0x4000760c +#define CYDEV_PHUB_CFGMEM2_BASE 0x40007610 +#define CYDEV_PHUB_CFGMEM2_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM2_CFG0 0x40007610 +#define CYREG_PHUB_CFGMEM2_CFG1 0x40007614 +#define CYDEV_PHUB_CFGMEM3_BASE 0x40007618 +#define CYDEV_PHUB_CFGMEM3_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM3_CFG0 0x40007618 +#define CYREG_PHUB_CFGMEM3_CFG1 0x4000761c +#define CYDEV_PHUB_CFGMEM4_BASE 0x40007620 +#define CYDEV_PHUB_CFGMEM4_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM4_CFG0 0x40007620 +#define CYREG_PHUB_CFGMEM4_CFG1 0x40007624 +#define CYDEV_PHUB_CFGMEM5_BASE 0x40007628 +#define CYDEV_PHUB_CFGMEM5_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM5_CFG0 0x40007628 +#define CYREG_PHUB_CFGMEM5_CFG1 0x4000762c +#define CYDEV_PHUB_CFGMEM6_BASE 0x40007630 +#define CYDEV_PHUB_CFGMEM6_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM6_CFG0 0x40007630 +#define CYREG_PHUB_CFGMEM6_CFG1 0x40007634 +#define CYDEV_PHUB_CFGMEM7_BASE 0x40007638 +#define CYDEV_PHUB_CFGMEM7_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM7_CFG0 0x40007638 +#define CYREG_PHUB_CFGMEM7_CFG1 0x4000763c +#define CYDEV_PHUB_CFGMEM8_BASE 0x40007640 +#define CYDEV_PHUB_CFGMEM8_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM8_CFG0 0x40007640 +#define CYREG_PHUB_CFGMEM8_CFG1 0x40007644 +#define CYDEV_PHUB_CFGMEM9_BASE 0x40007648 +#define CYDEV_PHUB_CFGMEM9_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM9_CFG0 0x40007648 +#define CYREG_PHUB_CFGMEM9_CFG1 0x4000764c +#define CYDEV_PHUB_CFGMEM10_BASE 0x40007650 +#define CYDEV_PHUB_CFGMEM10_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM10_CFG0 0x40007650 +#define CYREG_PHUB_CFGMEM10_CFG1 0x40007654 +#define CYDEV_PHUB_CFGMEM11_BASE 0x40007658 +#define CYDEV_PHUB_CFGMEM11_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM11_CFG0 0x40007658 +#define CYREG_PHUB_CFGMEM11_CFG1 0x4000765c +#define CYDEV_PHUB_CFGMEM12_BASE 0x40007660 +#define CYDEV_PHUB_CFGMEM12_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM12_CFG0 0x40007660 +#define CYREG_PHUB_CFGMEM12_CFG1 0x40007664 +#define CYDEV_PHUB_CFGMEM13_BASE 0x40007668 +#define CYDEV_PHUB_CFGMEM13_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM13_CFG0 0x40007668 +#define CYREG_PHUB_CFGMEM13_CFG1 0x4000766c +#define CYDEV_PHUB_CFGMEM14_BASE 0x40007670 +#define CYDEV_PHUB_CFGMEM14_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM14_CFG0 0x40007670 +#define CYREG_PHUB_CFGMEM14_CFG1 0x40007674 +#define CYDEV_PHUB_CFGMEM15_BASE 0x40007678 +#define CYDEV_PHUB_CFGMEM15_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM15_CFG0 0x40007678 +#define CYREG_PHUB_CFGMEM15_CFG1 0x4000767c +#define CYDEV_PHUB_CFGMEM16_BASE 0x40007680 +#define CYDEV_PHUB_CFGMEM16_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM16_CFG0 0x40007680 +#define CYREG_PHUB_CFGMEM16_CFG1 0x40007684 +#define CYDEV_PHUB_CFGMEM17_BASE 0x40007688 +#define CYDEV_PHUB_CFGMEM17_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM17_CFG0 0x40007688 +#define CYREG_PHUB_CFGMEM17_CFG1 0x4000768c +#define CYDEV_PHUB_CFGMEM18_BASE 0x40007690 +#define CYDEV_PHUB_CFGMEM18_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM18_CFG0 0x40007690 +#define CYREG_PHUB_CFGMEM18_CFG1 0x40007694 +#define CYDEV_PHUB_CFGMEM19_BASE 0x40007698 +#define CYDEV_PHUB_CFGMEM19_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM19_CFG0 0x40007698 +#define CYREG_PHUB_CFGMEM19_CFG1 0x4000769c +#define CYDEV_PHUB_CFGMEM20_BASE 0x400076a0 +#define CYDEV_PHUB_CFGMEM20_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM20_CFG0 0x400076a0 +#define CYREG_PHUB_CFGMEM20_CFG1 0x400076a4 +#define CYDEV_PHUB_CFGMEM21_BASE 0x400076a8 +#define CYDEV_PHUB_CFGMEM21_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM21_CFG0 0x400076a8 +#define CYREG_PHUB_CFGMEM21_CFG1 0x400076ac +#define CYDEV_PHUB_CFGMEM22_BASE 0x400076b0 +#define CYDEV_PHUB_CFGMEM22_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM22_CFG0 0x400076b0 +#define CYREG_PHUB_CFGMEM22_CFG1 0x400076b4 +#define CYDEV_PHUB_CFGMEM23_BASE 0x400076b8 +#define CYDEV_PHUB_CFGMEM23_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM23_CFG0 0x400076b8 +#define CYREG_PHUB_CFGMEM23_CFG1 0x400076bc +#define CYDEV_PHUB_TDMEM0_BASE 0x40007800 +#define CYDEV_PHUB_TDMEM0_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM0_ORIG_TD0 0x40007800 +#define CYREG_PHUB_TDMEM0_ORIG_TD1 0x40007804 +#define CYDEV_PHUB_TDMEM1_BASE 0x40007808 +#define CYDEV_PHUB_TDMEM1_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM1_ORIG_TD0 0x40007808 +#define CYREG_PHUB_TDMEM1_ORIG_TD1 0x4000780c +#define CYDEV_PHUB_TDMEM2_BASE 0x40007810 +#define CYDEV_PHUB_TDMEM2_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM2_ORIG_TD0 0x40007810 +#define CYREG_PHUB_TDMEM2_ORIG_TD1 0x40007814 +#define CYDEV_PHUB_TDMEM3_BASE 0x40007818 +#define CYDEV_PHUB_TDMEM3_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM3_ORIG_TD0 0x40007818 +#define CYREG_PHUB_TDMEM3_ORIG_TD1 0x4000781c +#define CYDEV_PHUB_TDMEM4_BASE 0x40007820 +#define CYDEV_PHUB_TDMEM4_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM4_ORIG_TD0 0x40007820 +#define CYREG_PHUB_TDMEM4_ORIG_TD1 0x40007824 +#define CYDEV_PHUB_TDMEM5_BASE 0x40007828 +#define CYDEV_PHUB_TDMEM5_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM5_ORIG_TD0 0x40007828 +#define CYREG_PHUB_TDMEM5_ORIG_TD1 0x4000782c +#define CYDEV_PHUB_TDMEM6_BASE 0x40007830 +#define CYDEV_PHUB_TDMEM6_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM6_ORIG_TD0 0x40007830 +#define CYREG_PHUB_TDMEM6_ORIG_TD1 0x40007834 +#define CYDEV_PHUB_TDMEM7_BASE 0x40007838 +#define CYDEV_PHUB_TDMEM7_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM7_ORIG_TD0 0x40007838 +#define CYREG_PHUB_TDMEM7_ORIG_TD1 0x4000783c +#define CYDEV_PHUB_TDMEM8_BASE 0x40007840 +#define CYDEV_PHUB_TDMEM8_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM8_ORIG_TD0 0x40007840 +#define CYREG_PHUB_TDMEM8_ORIG_TD1 0x40007844 +#define CYDEV_PHUB_TDMEM9_BASE 0x40007848 +#define CYDEV_PHUB_TDMEM9_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM9_ORIG_TD0 0x40007848 +#define CYREG_PHUB_TDMEM9_ORIG_TD1 0x4000784c +#define CYDEV_PHUB_TDMEM10_BASE 0x40007850 +#define CYDEV_PHUB_TDMEM10_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM10_ORIG_TD0 0x40007850 +#define CYREG_PHUB_TDMEM10_ORIG_TD1 0x40007854 +#define CYDEV_PHUB_TDMEM11_BASE 0x40007858 +#define CYDEV_PHUB_TDMEM11_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM11_ORIG_TD0 0x40007858 +#define CYREG_PHUB_TDMEM11_ORIG_TD1 0x4000785c +#define CYDEV_PHUB_TDMEM12_BASE 0x40007860 +#define CYDEV_PHUB_TDMEM12_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM12_ORIG_TD0 0x40007860 +#define CYREG_PHUB_TDMEM12_ORIG_TD1 0x40007864 +#define CYDEV_PHUB_TDMEM13_BASE 0x40007868 +#define CYDEV_PHUB_TDMEM13_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM13_ORIG_TD0 0x40007868 +#define CYREG_PHUB_TDMEM13_ORIG_TD1 0x4000786c +#define CYDEV_PHUB_TDMEM14_BASE 0x40007870 +#define CYDEV_PHUB_TDMEM14_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM14_ORIG_TD0 0x40007870 +#define CYREG_PHUB_TDMEM14_ORIG_TD1 0x40007874 +#define CYDEV_PHUB_TDMEM15_BASE 0x40007878 +#define CYDEV_PHUB_TDMEM15_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM15_ORIG_TD0 0x40007878 +#define CYREG_PHUB_TDMEM15_ORIG_TD1 0x4000787c +#define CYDEV_PHUB_TDMEM16_BASE 0x40007880 +#define CYDEV_PHUB_TDMEM16_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM16_ORIG_TD0 0x40007880 +#define CYREG_PHUB_TDMEM16_ORIG_TD1 0x40007884 +#define CYDEV_PHUB_TDMEM17_BASE 0x40007888 +#define CYDEV_PHUB_TDMEM17_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM17_ORIG_TD0 0x40007888 +#define CYREG_PHUB_TDMEM17_ORIG_TD1 0x4000788c +#define CYDEV_PHUB_TDMEM18_BASE 0x40007890 +#define CYDEV_PHUB_TDMEM18_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM18_ORIG_TD0 0x40007890 +#define CYREG_PHUB_TDMEM18_ORIG_TD1 0x40007894 +#define CYDEV_PHUB_TDMEM19_BASE 0x40007898 +#define CYDEV_PHUB_TDMEM19_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM19_ORIG_TD0 0x40007898 +#define CYREG_PHUB_TDMEM19_ORIG_TD1 0x4000789c +#define CYDEV_PHUB_TDMEM20_BASE 0x400078a0 +#define CYDEV_PHUB_TDMEM20_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM20_ORIG_TD0 0x400078a0 +#define CYREG_PHUB_TDMEM20_ORIG_TD1 0x400078a4 +#define CYDEV_PHUB_TDMEM21_BASE 0x400078a8 +#define CYDEV_PHUB_TDMEM21_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM21_ORIG_TD0 0x400078a8 +#define CYREG_PHUB_TDMEM21_ORIG_TD1 0x400078ac +#define CYDEV_PHUB_TDMEM22_BASE 0x400078b0 +#define CYDEV_PHUB_TDMEM22_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM22_ORIG_TD0 0x400078b0 +#define CYREG_PHUB_TDMEM22_ORIG_TD1 0x400078b4 +#define CYDEV_PHUB_TDMEM23_BASE 0x400078b8 +#define CYDEV_PHUB_TDMEM23_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM23_ORIG_TD0 0x400078b8 +#define CYREG_PHUB_TDMEM23_ORIG_TD1 0x400078bc +#define CYDEV_PHUB_TDMEM24_BASE 0x400078c0 +#define CYDEV_PHUB_TDMEM24_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM24_ORIG_TD0 0x400078c0 +#define CYREG_PHUB_TDMEM24_ORIG_TD1 0x400078c4 +#define CYDEV_PHUB_TDMEM25_BASE 0x400078c8 +#define CYDEV_PHUB_TDMEM25_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM25_ORIG_TD0 0x400078c8 +#define CYREG_PHUB_TDMEM25_ORIG_TD1 0x400078cc +#define CYDEV_PHUB_TDMEM26_BASE 0x400078d0 +#define CYDEV_PHUB_TDMEM26_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM26_ORIG_TD0 0x400078d0 +#define CYREG_PHUB_TDMEM26_ORIG_TD1 0x400078d4 +#define CYDEV_PHUB_TDMEM27_BASE 0x400078d8 +#define CYDEV_PHUB_TDMEM27_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM27_ORIG_TD0 0x400078d8 +#define CYREG_PHUB_TDMEM27_ORIG_TD1 0x400078dc +#define CYDEV_PHUB_TDMEM28_BASE 0x400078e0 +#define CYDEV_PHUB_TDMEM28_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM28_ORIG_TD0 0x400078e0 +#define CYREG_PHUB_TDMEM28_ORIG_TD1 0x400078e4 +#define CYDEV_PHUB_TDMEM29_BASE 0x400078e8 +#define CYDEV_PHUB_TDMEM29_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM29_ORIG_TD0 0x400078e8 +#define CYREG_PHUB_TDMEM29_ORIG_TD1 0x400078ec +#define CYDEV_PHUB_TDMEM30_BASE 0x400078f0 +#define CYDEV_PHUB_TDMEM30_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM30_ORIG_TD0 0x400078f0 +#define CYREG_PHUB_TDMEM30_ORIG_TD1 0x400078f4 +#define CYDEV_PHUB_TDMEM31_BASE 0x400078f8 +#define CYDEV_PHUB_TDMEM31_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM31_ORIG_TD0 0x400078f8 +#define CYREG_PHUB_TDMEM31_ORIG_TD1 0x400078fc +#define CYDEV_PHUB_TDMEM32_BASE 0x40007900 +#define CYDEV_PHUB_TDMEM32_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM32_ORIG_TD0 0x40007900 +#define CYREG_PHUB_TDMEM32_ORIG_TD1 0x40007904 +#define CYDEV_PHUB_TDMEM33_BASE 0x40007908 +#define CYDEV_PHUB_TDMEM33_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM33_ORIG_TD0 0x40007908 +#define CYREG_PHUB_TDMEM33_ORIG_TD1 0x4000790c +#define CYDEV_PHUB_TDMEM34_BASE 0x40007910 +#define CYDEV_PHUB_TDMEM34_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM34_ORIG_TD0 0x40007910 +#define CYREG_PHUB_TDMEM34_ORIG_TD1 0x40007914 +#define CYDEV_PHUB_TDMEM35_BASE 0x40007918 +#define CYDEV_PHUB_TDMEM35_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM35_ORIG_TD0 0x40007918 +#define CYREG_PHUB_TDMEM35_ORIG_TD1 0x4000791c +#define CYDEV_PHUB_TDMEM36_BASE 0x40007920 +#define CYDEV_PHUB_TDMEM36_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM36_ORIG_TD0 0x40007920 +#define CYREG_PHUB_TDMEM36_ORIG_TD1 0x40007924 +#define CYDEV_PHUB_TDMEM37_BASE 0x40007928 +#define CYDEV_PHUB_TDMEM37_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM37_ORIG_TD0 0x40007928 +#define CYREG_PHUB_TDMEM37_ORIG_TD1 0x4000792c +#define CYDEV_PHUB_TDMEM38_BASE 0x40007930 +#define CYDEV_PHUB_TDMEM38_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM38_ORIG_TD0 0x40007930 +#define CYREG_PHUB_TDMEM38_ORIG_TD1 0x40007934 +#define CYDEV_PHUB_TDMEM39_BASE 0x40007938 +#define CYDEV_PHUB_TDMEM39_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM39_ORIG_TD0 0x40007938 +#define CYREG_PHUB_TDMEM39_ORIG_TD1 0x4000793c +#define CYDEV_PHUB_TDMEM40_BASE 0x40007940 +#define CYDEV_PHUB_TDMEM40_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM40_ORIG_TD0 0x40007940 +#define CYREG_PHUB_TDMEM40_ORIG_TD1 0x40007944 +#define CYDEV_PHUB_TDMEM41_BASE 0x40007948 +#define CYDEV_PHUB_TDMEM41_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM41_ORIG_TD0 0x40007948 +#define CYREG_PHUB_TDMEM41_ORIG_TD1 0x4000794c +#define CYDEV_PHUB_TDMEM42_BASE 0x40007950 +#define CYDEV_PHUB_TDMEM42_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM42_ORIG_TD0 0x40007950 +#define CYREG_PHUB_TDMEM42_ORIG_TD1 0x40007954 +#define CYDEV_PHUB_TDMEM43_BASE 0x40007958 +#define CYDEV_PHUB_TDMEM43_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM43_ORIG_TD0 0x40007958 +#define CYREG_PHUB_TDMEM43_ORIG_TD1 0x4000795c +#define CYDEV_PHUB_TDMEM44_BASE 0x40007960 +#define CYDEV_PHUB_TDMEM44_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM44_ORIG_TD0 0x40007960 +#define CYREG_PHUB_TDMEM44_ORIG_TD1 0x40007964 +#define CYDEV_PHUB_TDMEM45_BASE 0x40007968 +#define CYDEV_PHUB_TDMEM45_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM45_ORIG_TD0 0x40007968 +#define CYREG_PHUB_TDMEM45_ORIG_TD1 0x4000796c +#define CYDEV_PHUB_TDMEM46_BASE 0x40007970 +#define CYDEV_PHUB_TDMEM46_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM46_ORIG_TD0 0x40007970 +#define CYREG_PHUB_TDMEM46_ORIG_TD1 0x40007974 +#define CYDEV_PHUB_TDMEM47_BASE 0x40007978 +#define CYDEV_PHUB_TDMEM47_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM47_ORIG_TD0 0x40007978 +#define CYREG_PHUB_TDMEM47_ORIG_TD1 0x4000797c +#define CYDEV_PHUB_TDMEM48_BASE 0x40007980 +#define CYDEV_PHUB_TDMEM48_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM48_ORIG_TD0 0x40007980 +#define CYREG_PHUB_TDMEM48_ORIG_TD1 0x40007984 +#define CYDEV_PHUB_TDMEM49_BASE 0x40007988 +#define CYDEV_PHUB_TDMEM49_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM49_ORIG_TD0 0x40007988 +#define CYREG_PHUB_TDMEM49_ORIG_TD1 0x4000798c +#define CYDEV_PHUB_TDMEM50_BASE 0x40007990 +#define CYDEV_PHUB_TDMEM50_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM50_ORIG_TD0 0x40007990 +#define CYREG_PHUB_TDMEM50_ORIG_TD1 0x40007994 +#define CYDEV_PHUB_TDMEM51_BASE 0x40007998 +#define CYDEV_PHUB_TDMEM51_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM51_ORIG_TD0 0x40007998 +#define CYREG_PHUB_TDMEM51_ORIG_TD1 0x4000799c +#define CYDEV_PHUB_TDMEM52_BASE 0x400079a0 +#define CYDEV_PHUB_TDMEM52_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM52_ORIG_TD0 0x400079a0 +#define CYREG_PHUB_TDMEM52_ORIG_TD1 0x400079a4 +#define CYDEV_PHUB_TDMEM53_BASE 0x400079a8 +#define CYDEV_PHUB_TDMEM53_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM53_ORIG_TD0 0x400079a8 +#define CYREG_PHUB_TDMEM53_ORIG_TD1 0x400079ac +#define CYDEV_PHUB_TDMEM54_BASE 0x400079b0 +#define CYDEV_PHUB_TDMEM54_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM54_ORIG_TD0 0x400079b0 +#define CYREG_PHUB_TDMEM54_ORIG_TD1 0x400079b4 +#define CYDEV_PHUB_TDMEM55_BASE 0x400079b8 +#define CYDEV_PHUB_TDMEM55_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM55_ORIG_TD0 0x400079b8 +#define CYREG_PHUB_TDMEM55_ORIG_TD1 0x400079bc +#define CYDEV_PHUB_TDMEM56_BASE 0x400079c0 +#define CYDEV_PHUB_TDMEM56_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM56_ORIG_TD0 0x400079c0 +#define CYREG_PHUB_TDMEM56_ORIG_TD1 0x400079c4 +#define CYDEV_PHUB_TDMEM57_BASE 0x400079c8 +#define CYDEV_PHUB_TDMEM57_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM57_ORIG_TD0 0x400079c8 +#define CYREG_PHUB_TDMEM57_ORIG_TD1 0x400079cc +#define CYDEV_PHUB_TDMEM58_BASE 0x400079d0 +#define CYDEV_PHUB_TDMEM58_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM58_ORIG_TD0 0x400079d0 +#define CYREG_PHUB_TDMEM58_ORIG_TD1 0x400079d4 +#define CYDEV_PHUB_TDMEM59_BASE 0x400079d8 +#define CYDEV_PHUB_TDMEM59_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM59_ORIG_TD0 0x400079d8 +#define CYREG_PHUB_TDMEM59_ORIG_TD1 0x400079dc +#define CYDEV_PHUB_TDMEM60_BASE 0x400079e0 +#define CYDEV_PHUB_TDMEM60_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM60_ORIG_TD0 0x400079e0 +#define CYREG_PHUB_TDMEM60_ORIG_TD1 0x400079e4 +#define CYDEV_PHUB_TDMEM61_BASE 0x400079e8 +#define CYDEV_PHUB_TDMEM61_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM61_ORIG_TD0 0x400079e8 +#define CYREG_PHUB_TDMEM61_ORIG_TD1 0x400079ec +#define CYDEV_PHUB_TDMEM62_BASE 0x400079f0 +#define CYDEV_PHUB_TDMEM62_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM62_ORIG_TD0 0x400079f0 +#define CYREG_PHUB_TDMEM62_ORIG_TD1 0x400079f4 +#define CYDEV_PHUB_TDMEM63_BASE 0x400079f8 +#define CYDEV_PHUB_TDMEM63_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM63_ORIG_TD0 0x400079f8 +#define CYREG_PHUB_TDMEM63_ORIG_TD1 0x400079fc +#define CYDEV_PHUB_TDMEM64_BASE 0x40007a00 +#define CYDEV_PHUB_TDMEM64_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM64_ORIG_TD0 0x40007a00 +#define CYREG_PHUB_TDMEM64_ORIG_TD1 0x40007a04 +#define CYDEV_PHUB_TDMEM65_BASE 0x40007a08 +#define CYDEV_PHUB_TDMEM65_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM65_ORIG_TD0 0x40007a08 +#define CYREG_PHUB_TDMEM65_ORIG_TD1 0x40007a0c +#define CYDEV_PHUB_TDMEM66_BASE 0x40007a10 +#define CYDEV_PHUB_TDMEM66_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM66_ORIG_TD0 0x40007a10 +#define CYREG_PHUB_TDMEM66_ORIG_TD1 0x40007a14 +#define CYDEV_PHUB_TDMEM67_BASE 0x40007a18 +#define CYDEV_PHUB_TDMEM67_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM67_ORIG_TD0 0x40007a18 +#define CYREG_PHUB_TDMEM67_ORIG_TD1 0x40007a1c +#define CYDEV_PHUB_TDMEM68_BASE 0x40007a20 +#define CYDEV_PHUB_TDMEM68_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM68_ORIG_TD0 0x40007a20 +#define CYREG_PHUB_TDMEM68_ORIG_TD1 0x40007a24 +#define CYDEV_PHUB_TDMEM69_BASE 0x40007a28 +#define CYDEV_PHUB_TDMEM69_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM69_ORIG_TD0 0x40007a28 +#define CYREG_PHUB_TDMEM69_ORIG_TD1 0x40007a2c +#define CYDEV_PHUB_TDMEM70_BASE 0x40007a30 +#define CYDEV_PHUB_TDMEM70_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM70_ORIG_TD0 0x40007a30 +#define CYREG_PHUB_TDMEM70_ORIG_TD1 0x40007a34 +#define CYDEV_PHUB_TDMEM71_BASE 0x40007a38 +#define CYDEV_PHUB_TDMEM71_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM71_ORIG_TD0 0x40007a38 +#define CYREG_PHUB_TDMEM71_ORIG_TD1 0x40007a3c +#define CYDEV_PHUB_TDMEM72_BASE 0x40007a40 +#define CYDEV_PHUB_TDMEM72_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM72_ORIG_TD0 0x40007a40 +#define CYREG_PHUB_TDMEM72_ORIG_TD1 0x40007a44 +#define CYDEV_PHUB_TDMEM73_BASE 0x40007a48 +#define CYDEV_PHUB_TDMEM73_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM73_ORIG_TD0 0x40007a48 +#define CYREG_PHUB_TDMEM73_ORIG_TD1 0x40007a4c +#define CYDEV_PHUB_TDMEM74_BASE 0x40007a50 +#define CYDEV_PHUB_TDMEM74_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM74_ORIG_TD0 0x40007a50 +#define CYREG_PHUB_TDMEM74_ORIG_TD1 0x40007a54 +#define CYDEV_PHUB_TDMEM75_BASE 0x40007a58 +#define CYDEV_PHUB_TDMEM75_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM75_ORIG_TD0 0x40007a58 +#define CYREG_PHUB_TDMEM75_ORIG_TD1 0x40007a5c +#define CYDEV_PHUB_TDMEM76_BASE 0x40007a60 +#define CYDEV_PHUB_TDMEM76_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM76_ORIG_TD0 0x40007a60 +#define CYREG_PHUB_TDMEM76_ORIG_TD1 0x40007a64 +#define CYDEV_PHUB_TDMEM77_BASE 0x40007a68 +#define CYDEV_PHUB_TDMEM77_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM77_ORIG_TD0 0x40007a68 +#define CYREG_PHUB_TDMEM77_ORIG_TD1 0x40007a6c +#define CYDEV_PHUB_TDMEM78_BASE 0x40007a70 +#define CYDEV_PHUB_TDMEM78_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM78_ORIG_TD0 0x40007a70 +#define CYREG_PHUB_TDMEM78_ORIG_TD1 0x40007a74 +#define CYDEV_PHUB_TDMEM79_BASE 0x40007a78 +#define CYDEV_PHUB_TDMEM79_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM79_ORIG_TD0 0x40007a78 +#define CYREG_PHUB_TDMEM79_ORIG_TD1 0x40007a7c +#define CYDEV_PHUB_TDMEM80_BASE 0x40007a80 +#define CYDEV_PHUB_TDMEM80_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM80_ORIG_TD0 0x40007a80 +#define CYREG_PHUB_TDMEM80_ORIG_TD1 0x40007a84 +#define CYDEV_PHUB_TDMEM81_BASE 0x40007a88 +#define CYDEV_PHUB_TDMEM81_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM81_ORIG_TD0 0x40007a88 +#define CYREG_PHUB_TDMEM81_ORIG_TD1 0x40007a8c +#define CYDEV_PHUB_TDMEM82_BASE 0x40007a90 +#define CYDEV_PHUB_TDMEM82_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM82_ORIG_TD0 0x40007a90 +#define CYREG_PHUB_TDMEM82_ORIG_TD1 0x40007a94 +#define CYDEV_PHUB_TDMEM83_BASE 0x40007a98 +#define CYDEV_PHUB_TDMEM83_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM83_ORIG_TD0 0x40007a98 +#define CYREG_PHUB_TDMEM83_ORIG_TD1 0x40007a9c +#define CYDEV_PHUB_TDMEM84_BASE 0x40007aa0 +#define CYDEV_PHUB_TDMEM84_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM84_ORIG_TD0 0x40007aa0 +#define CYREG_PHUB_TDMEM84_ORIG_TD1 0x40007aa4 +#define CYDEV_PHUB_TDMEM85_BASE 0x40007aa8 +#define CYDEV_PHUB_TDMEM85_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM85_ORIG_TD0 0x40007aa8 +#define CYREG_PHUB_TDMEM85_ORIG_TD1 0x40007aac +#define CYDEV_PHUB_TDMEM86_BASE 0x40007ab0 +#define CYDEV_PHUB_TDMEM86_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM86_ORIG_TD0 0x40007ab0 +#define CYREG_PHUB_TDMEM86_ORIG_TD1 0x40007ab4 +#define CYDEV_PHUB_TDMEM87_BASE 0x40007ab8 +#define CYDEV_PHUB_TDMEM87_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM87_ORIG_TD0 0x40007ab8 +#define CYREG_PHUB_TDMEM87_ORIG_TD1 0x40007abc +#define CYDEV_PHUB_TDMEM88_BASE 0x40007ac0 +#define CYDEV_PHUB_TDMEM88_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM88_ORIG_TD0 0x40007ac0 +#define CYREG_PHUB_TDMEM88_ORIG_TD1 0x40007ac4 +#define CYDEV_PHUB_TDMEM89_BASE 0x40007ac8 +#define CYDEV_PHUB_TDMEM89_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM89_ORIG_TD0 0x40007ac8 +#define CYREG_PHUB_TDMEM89_ORIG_TD1 0x40007acc +#define CYDEV_PHUB_TDMEM90_BASE 0x40007ad0 +#define CYDEV_PHUB_TDMEM90_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM90_ORIG_TD0 0x40007ad0 +#define CYREG_PHUB_TDMEM90_ORIG_TD1 0x40007ad4 +#define CYDEV_PHUB_TDMEM91_BASE 0x40007ad8 +#define CYDEV_PHUB_TDMEM91_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM91_ORIG_TD0 0x40007ad8 +#define CYREG_PHUB_TDMEM91_ORIG_TD1 0x40007adc +#define CYDEV_PHUB_TDMEM92_BASE 0x40007ae0 +#define CYDEV_PHUB_TDMEM92_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM92_ORIG_TD0 0x40007ae0 +#define CYREG_PHUB_TDMEM92_ORIG_TD1 0x40007ae4 +#define CYDEV_PHUB_TDMEM93_BASE 0x40007ae8 +#define CYDEV_PHUB_TDMEM93_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM93_ORIG_TD0 0x40007ae8 +#define CYREG_PHUB_TDMEM93_ORIG_TD1 0x40007aec +#define CYDEV_PHUB_TDMEM94_BASE 0x40007af0 +#define CYDEV_PHUB_TDMEM94_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM94_ORIG_TD0 0x40007af0 +#define CYREG_PHUB_TDMEM94_ORIG_TD1 0x40007af4 +#define CYDEV_PHUB_TDMEM95_BASE 0x40007af8 +#define CYDEV_PHUB_TDMEM95_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM95_ORIG_TD0 0x40007af8 +#define CYREG_PHUB_TDMEM95_ORIG_TD1 0x40007afc +#define CYDEV_PHUB_TDMEM96_BASE 0x40007b00 +#define CYDEV_PHUB_TDMEM96_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM96_ORIG_TD0 0x40007b00 +#define CYREG_PHUB_TDMEM96_ORIG_TD1 0x40007b04 +#define CYDEV_PHUB_TDMEM97_BASE 0x40007b08 +#define CYDEV_PHUB_TDMEM97_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM97_ORIG_TD0 0x40007b08 +#define CYREG_PHUB_TDMEM97_ORIG_TD1 0x40007b0c +#define CYDEV_PHUB_TDMEM98_BASE 0x40007b10 +#define CYDEV_PHUB_TDMEM98_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM98_ORIG_TD0 0x40007b10 +#define CYREG_PHUB_TDMEM98_ORIG_TD1 0x40007b14 +#define CYDEV_PHUB_TDMEM99_BASE 0x40007b18 +#define CYDEV_PHUB_TDMEM99_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM99_ORIG_TD0 0x40007b18 +#define CYREG_PHUB_TDMEM99_ORIG_TD1 0x40007b1c +#define CYDEV_PHUB_TDMEM100_BASE 0x40007b20 +#define CYDEV_PHUB_TDMEM100_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM100_ORIG_TD0 0x40007b20 +#define CYREG_PHUB_TDMEM100_ORIG_TD1 0x40007b24 +#define CYDEV_PHUB_TDMEM101_BASE 0x40007b28 +#define CYDEV_PHUB_TDMEM101_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM101_ORIG_TD0 0x40007b28 +#define CYREG_PHUB_TDMEM101_ORIG_TD1 0x40007b2c +#define CYDEV_PHUB_TDMEM102_BASE 0x40007b30 +#define CYDEV_PHUB_TDMEM102_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM102_ORIG_TD0 0x40007b30 +#define CYREG_PHUB_TDMEM102_ORIG_TD1 0x40007b34 +#define CYDEV_PHUB_TDMEM103_BASE 0x40007b38 +#define CYDEV_PHUB_TDMEM103_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM103_ORIG_TD0 0x40007b38 +#define CYREG_PHUB_TDMEM103_ORIG_TD1 0x40007b3c +#define CYDEV_PHUB_TDMEM104_BASE 0x40007b40 +#define CYDEV_PHUB_TDMEM104_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM104_ORIG_TD0 0x40007b40 +#define CYREG_PHUB_TDMEM104_ORIG_TD1 0x40007b44 +#define CYDEV_PHUB_TDMEM105_BASE 0x40007b48 +#define CYDEV_PHUB_TDMEM105_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM105_ORIG_TD0 0x40007b48 +#define CYREG_PHUB_TDMEM105_ORIG_TD1 0x40007b4c +#define CYDEV_PHUB_TDMEM106_BASE 0x40007b50 +#define CYDEV_PHUB_TDMEM106_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM106_ORIG_TD0 0x40007b50 +#define CYREG_PHUB_TDMEM106_ORIG_TD1 0x40007b54 +#define CYDEV_PHUB_TDMEM107_BASE 0x40007b58 +#define CYDEV_PHUB_TDMEM107_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM107_ORIG_TD0 0x40007b58 +#define CYREG_PHUB_TDMEM107_ORIG_TD1 0x40007b5c +#define CYDEV_PHUB_TDMEM108_BASE 0x40007b60 +#define CYDEV_PHUB_TDMEM108_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM108_ORIG_TD0 0x40007b60 +#define CYREG_PHUB_TDMEM108_ORIG_TD1 0x40007b64 +#define CYDEV_PHUB_TDMEM109_BASE 0x40007b68 +#define CYDEV_PHUB_TDMEM109_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM109_ORIG_TD0 0x40007b68 +#define CYREG_PHUB_TDMEM109_ORIG_TD1 0x40007b6c +#define CYDEV_PHUB_TDMEM110_BASE 0x40007b70 +#define CYDEV_PHUB_TDMEM110_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM110_ORIG_TD0 0x40007b70 +#define CYREG_PHUB_TDMEM110_ORIG_TD1 0x40007b74 +#define CYDEV_PHUB_TDMEM111_BASE 0x40007b78 +#define CYDEV_PHUB_TDMEM111_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM111_ORIG_TD0 0x40007b78 +#define CYREG_PHUB_TDMEM111_ORIG_TD1 0x40007b7c +#define CYDEV_PHUB_TDMEM112_BASE 0x40007b80 +#define CYDEV_PHUB_TDMEM112_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM112_ORIG_TD0 0x40007b80 +#define CYREG_PHUB_TDMEM112_ORIG_TD1 0x40007b84 +#define CYDEV_PHUB_TDMEM113_BASE 0x40007b88 +#define CYDEV_PHUB_TDMEM113_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM113_ORIG_TD0 0x40007b88 +#define CYREG_PHUB_TDMEM113_ORIG_TD1 0x40007b8c +#define CYDEV_PHUB_TDMEM114_BASE 0x40007b90 +#define CYDEV_PHUB_TDMEM114_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM114_ORIG_TD0 0x40007b90 +#define CYREG_PHUB_TDMEM114_ORIG_TD1 0x40007b94 +#define CYDEV_PHUB_TDMEM115_BASE 0x40007b98 +#define CYDEV_PHUB_TDMEM115_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM115_ORIG_TD0 0x40007b98 +#define CYREG_PHUB_TDMEM115_ORIG_TD1 0x40007b9c +#define CYDEV_PHUB_TDMEM116_BASE 0x40007ba0 +#define CYDEV_PHUB_TDMEM116_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM116_ORIG_TD0 0x40007ba0 +#define CYREG_PHUB_TDMEM116_ORIG_TD1 0x40007ba4 +#define CYDEV_PHUB_TDMEM117_BASE 0x40007ba8 +#define CYDEV_PHUB_TDMEM117_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM117_ORIG_TD0 0x40007ba8 +#define CYREG_PHUB_TDMEM117_ORIG_TD1 0x40007bac +#define CYDEV_PHUB_TDMEM118_BASE 0x40007bb0 +#define CYDEV_PHUB_TDMEM118_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM118_ORIG_TD0 0x40007bb0 +#define CYREG_PHUB_TDMEM118_ORIG_TD1 0x40007bb4 +#define CYDEV_PHUB_TDMEM119_BASE 0x40007bb8 +#define CYDEV_PHUB_TDMEM119_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM119_ORIG_TD0 0x40007bb8 +#define CYREG_PHUB_TDMEM119_ORIG_TD1 0x40007bbc +#define CYDEV_PHUB_TDMEM120_BASE 0x40007bc0 +#define CYDEV_PHUB_TDMEM120_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM120_ORIG_TD0 0x40007bc0 +#define CYREG_PHUB_TDMEM120_ORIG_TD1 0x40007bc4 +#define CYDEV_PHUB_TDMEM121_BASE 0x40007bc8 +#define CYDEV_PHUB_TDMEM121_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM121_ORIG_TD0 0x40007bc8 +#define CYREG_PHUB_TDMEM121_ORIG_TD1 0x40007bcc +#define CYDEV_PHUB_TDMEM122_BASE 0x40007bd0 +#define CYDEV_PHUB_TDMEM122_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM122_ORIG_TD0 0x40007bd0 +#define CYREG_PHUB_TDMEM122_ORIG_TD1 0x40007bd4 +#define CYDEV_PHUB_TDMEM123_BASE 0x40007bd8 +#define CYDEV_PHUB_TDMEM123_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM123_ORIG_TD0 0x40007bd8 +#define CYREG_PHUB_TDMEM123_ORIG_TD1 0x40007bdc +#define CYDEV_PHUB_TDMEM124_BASE 0x40007be0 +#define CYDEV_PHUB_TDMEM124_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM124_ORIG_TD0 0x40007be0 +#define CYREG_PHUB_TDMEM124_ORIG_TD1 0x40007be4 +#define CYDEV_PHUB_TDMEM125_BASE 0x40007be8 +#define CYDEV_PHUB_TDMEM125_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM125_ORIG_TD0 0x40007be8 +#define CYREG_PHUB_TDMEM125_ORIG_TD1 0x40007bec +#define CYDEV_PHUB_TDMEM126_BASE 0x40007bf0 +#define CYDEV_PHUB_TDMEM126_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM126_ORIG_TD0 0x40007bf0 +#define CYREG_PHUB_TDMEM126_ORIG_TD1 0x40007bf4 +#define CYDEV_PHUB_TDMEM127_BASE 0x40007bf8 +#define CYDEV_PHUB_TDMEM127_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM127_ORIG_TD0 0x40007bf8 +#define CYREG_PHUB_TDMEM127_ORIG_TD1 0x40007bfc +#define CYDEV_EE_BASE 0x40008000 +#define CYDEV_EE_SIZE 0x00000800 +#define CYREG_EE_DATA_MBASE 0x40008000 +#define CYREG_EE_DATA_MSIZE 0x00000800 +#define CYDEV_CAN0_BASE 0x4000a000 +#define CYDEV_CAN0_SIZE 0x000002a0 +#define CYDEV_CAN0_CSR_BASE 0x4000a000 +#define CYDEV_CAN0_CSR_SIZE 0x00000018 +#define CYREG_CAN0_CSR_INT_SR 0x4000a000 +#define CYREG_CAN0_CSR_INT_EN 0x4000a004 +#define CYREG_CAN0_CSR_BUF_SR 0x4000a008 +#define CYREG_CAN0_CSR_ERR_SR 0x4000a00c +#define CYREG_CAN0_CSR_CMD 0x4000a010 +#define CYREG_CAN0_CSR_CFG 0x4000a014 +#define CYDEV_CAN0_TX0_BASE 0x4000a020 +#define CYDEV_CAN0_TX0_SIZE 0x00000010 +#define CYREG_CAN0_TX0_CMD 0x4000a020 +#define CYREG_CAN0_TX0_ID 0x4000a024 +#define CYREG_CAN0_TX0_DH 0x4000a028 +#define CYREG_CAN0_TX0_DL 0x4000a02c +#define CYDEV_CAN0_TX1_BASE 0x4000a030 +#define CYDEV_CAN0_TX1_SIZE 0x00000010 +#define CYREG_CAN0_TX1_CMD 0x4000a030 +#define CYREG_CAN0_TX1_ID 0x4000a034 +#define CYREG_CAN0_TX1_DH 0x4000a038 +#define CYREG_CAN0_TX1_DL 0x4000a03c +#define CYDEV_CAN0_TX2_BASE 0x4000a040 +#define CYDEV_CAN0_TX2_SIZE 0x00000010 +#define CYREG_CAN0_TX2_CMD 0x4000a040 +#define CYREG_CAN0_TX2_ID 0x4000a044 +#define CYREG_CAN0_TX2_DH 0x4000a048 +#define CYREG_CAN0_TX2_DL 0x4000a04c +#define CYDEV_CAN0_TX3_BASE 0x4000a050 +#define CYDEV_CAN0_TX3_SIZE 0x00000010 +#define CYREG_CAN0_TX3_CMD 0x4000a050 +#define CYREG_CAN0_TX3_ID 0x4000a054 +#define CYREG_CAN0_TX3_DH 0x4000a058 +#define CYREG_CAN0_TX3_DL 0x4000a05c +#define CYDEV_CAN0_TX4_BASE 0x4000a060 +#define CYDEV_CAN0_TX4_SIZE 0x00000010 +#define CYREG_CAN0_TX4_CMD 0x4000a060 +#define CYREG_CAN0_TX4_ID 0x4000a064 +#define CYREG_CAN0_TX4_DH 0x4000a068 +#define CYREG_CAN0_TX4_DL 0x4000a06c +#define CYDEV_CAN0_TX5_BASE 0x4000a070 +#define CYDEV_CAN0_TX5_SIZE 0x00000010 +#define CYREG_CAN0_TX5_CMD 0x4000a070 +#define CYREG_CAN0_TX5_ID 0x4000a074 +#define CYREG_CAN0_TX5_DH 0x4000a078 +#define CYREG_CAN0_TX5_DL 0x4000a07c +#define CYDEV_CAN0_TX6_BASE 0x4000a080 +#define CYDEV_CAN0_TX6_SIZE 0x00000010 +#define CYREG_CAN0_TX6_CMD 0x4000a080 +#define CYREG_CAN0_TX6_ID 0x4000a084 +#define CYREG_CAN0_TX6_DH 0x4000a088 +#define CYREG_CAN0_TX6_DL 0x4000a08c +#define CYDEV_CAN0_TX7_BASE 0x4000a090 +#define CYDEV_CAN0_TX7_SIZE 0x00000010 +#define CYREG_CAN0_TX7_CMD 0x4000a090 +#define CYREG_CAN0_TX7_ID 0x4000a094 +#define CYREG_CAN0_TX7_DH 0x4000a098 +#define CYREG_CAN0_TX7_DL 0x4000a09c +#define CYDEV_CAN0_RX0_BASE 0x4000a0a0 +#define CYDEV_CAN0_RX0_SIZE 0x00000020 +#define CYREG_CAN0_RX0_CMD 0x4000a0a0 +#define CYREG_CAN0_RX0_ID 0x4000a0a4 +#define CYREG_CAN0_RX0_DH 0x4000a0a8 +#define CYREG_CAN0_RX0_DL 0x4000a0ac +#define CYREG_CAN0_RX0_AMR 0x4000a0b0 +#define CYREG_CAN0_RX0_ACR 0x4000a0b4 +#define CYREG_CAN0_RX0_AMRD 0x4000a0b8 +#define CYREG_CAN0_RX0_ACRD 0x4000a0bc +#define CYDEV_CAN0_RX1_BASE 0x4000a0c0 +#define CYDEV_CAN0_RX1_SIZE 0x00000020 +#define CYREG_CAN0_RX1_CMD 0x4000a0c0 +#define CYREG_CAN0_RX1_ID 0x4000a0c4 +#define CYREG_CAN0_RX1_DH 0x4000a0c8 +#define CYREG_CAN0_RX1_DL 0x4000a0cc +#define CYREG_CAN0_RX1_AMR 0x4000a0d0 +#define CYREG_CAN0_RX1_ACR 0x4000a0d4 +#define CYREG_CAN0_RX1_AMRD 0x4000a0d8 +#define CYREG_CAN0_RX1_ACRD 0x4000a0dc +#define CYDEV_CAN0_RX2_BASE 0x4000a0e0 +#define CYDEV_CAN0_RX2_SIZE 0x00000020 +#define CYREG_CAN0_RX2_CMD 0x4000a0e0 +#define CYREG_CAN0_RX2_ID 0x4000a0e4 +#define CYREG_CAN0_RX2_DH 0x4000a0e8 +#define CYREG_CAN0_RX2_DL 0x4000a0ec +#define CYREG_CAN0_RX2_AMR 0x4000a0f0 +#define CYREG_CAN0_RX2_ACR 0x4000a0f4 +#define CYREG_CAN0_RX2_AMRD 0x4000a0f8 +#define CYREG_CAN0_RX2_ACRD 0x4000a0fc +#define CYDEV_CAN0_RX3_BASE 0x4000a100 +#define CYDEV_CAN0_RX3_SIZE 0x00000020 +#define CYREG_CAN0_RX3_CMD 0x4000a100 +#define CYREG_CAN0_RX3_ID 0x4000a104 +#define CYREG_CAN0_RX3_DH 0x4000a108 +#define CYREG_CAN0_RX3_DL 0x4000a10c +#define CYREG_CAN0_RX3_AMR 0x4000a110 +#define CYREG_CAN0_RX3_ACR 0x4000a114 +#define CYREG_CAN0_RX3_AMRD 0x4000a118 +#define CYREG_CAN0_RX3_ACRD 0x4000a11c +#define CYDEV_CAN0_RX4_BASE 0x4000a120 +#define CYDEV_CAN0_RX4_SIZE 0x00000020 +#define CYREG_CAN0_RX4_CMD 0x4000a120 +#define CYREG_CAN0_RX4_ID 0x4000a124 +#define CYREG_CAN0_RX4_DH 0x4000a128 +#define CYREG_CAN0_RX4_DL 0x4000a12c +#define CYREG_CAN0_RX4_AMR 0x4000a130 +#define CYREG_CAN0_RX4_ACR 0x4000a134 +#define CYREG_CAN0_RX4_AMRD 0x4000a138 +#define CYREG_CAN0_RX4_ACRD 0x4000a13c +#define CYDEV_CAN0_RX5_BASE 0x4000a140 +#define CYDEV_CAN0_RX5_SIZE 0x00000020 +#define CYREG_CAN0_RX5_CMD 0x4000a140 +#define CYREG_CAN0_RX5_ID 0x4000a144 +#define CYREG_CAN0_RX5_DH 0x4000a148 +#define CYREG_CAN0_RX5_DL 0x4000a14c +#define CYREG_CAN0_RX5_AMR 0x4000a150 +#define CYREG_CAN0_RX5_ACR 0x4000a154 +#define CYREG_CAN0_RX5_AMRD 0x4000a158 +#define CYREG_CAN0_RX5_ACRD 0x4000a15c +#define CYDEV_CAN0_RX6_BASE 0x4000a160 +#define CYDEV_CAN0_RX6_SIZE 0x00000020 +#define CYREG_CAN0_RX6_CMD 0x4000a160 +#define CYREG_CAN0_RX6_ID 0x4000a164 +#define CYREG_CAN0_RX6_DH 0x4000a168 +#define CYREG_CAN0_RX6_DL 0x4000a16c +#define CYREG_CAN0_RX6_AMR 0x4000a170 +#define CYREG_CAN0_RX6_ACR 0x4000a174 +#define CYREG_CAN0_RX6_AMRD 0x4000a178 +#define CYREG_CAN0_RX6_ACRD 0x4000a17c +#define CYDEV_CAN0_RX7_BASE 0x4000a180 +#define CYDEV_CAN0_RX7_SIZE 0x00000020 +#define CYREG_CAN0_RX7_CMD 0x4000a180 +#define CYREG_CAN0_RX7_ID 0x4000a184 +#define CYREG_CAN0_RX7_DH 0x4000a188 +#define CYREG_CAN0_RX7_DL 0x4000a18c +#define CYREG_CAN0_RX7_AMR 0x4000a190 +#define CYREG_CAN0_RX7_ACR 0x4000a194 +#define CYREG_CAN0_RX7_AMRD 0x4000a198 +#define CYREG_CAN0_RX7_ACRD 0x4000a19c +#define CYDEV_CAN0_RX8_BASE 0x4000a1a0 +#define CYDEV_CAN0_RX8_SIZE 0x00000020 +#define CYREG_CAN0_RX8_CMD 0x4000a1a0 +#define CYREG_CAN0_RX8_ID 0x4000a1a4 +#define CYREG_CAN0_RX8_DH 0x4000a1a8 +#define CYREG_CAN0_RX8_DL 0x4000a1ac +#define CYREG_CAN0_RX8_AMR 0x4000a1b0 +#define CYREG_CAN0_RX8_ACR 0x4000a1b4 +#define CYREG_CAN0_RX8_AMRD 0x4000a1b8 +#define CYREG_CAN0_RX8_ACRD 0x4000a1bc +#define CYDEV_CAN0_RX9_BASE 0x4000a1c0 +#define CYDEV_CAN0_RX9_SIZE 0x00000020 +#define CYREG_CAN0_RX9_CMD 0x4000a1c0 +#define CYREG_CAN0_RX9_ID 0x4000a1c4 +#define CYREG_CAN0_RX9_DH 0x4000a1c8 +#define CYREG_CAN0_RX9_DL 0x4000a1cc +#define CYREG_CAN0_RX9_AMR 0x4000a1d0 +#define CYREG_CAN0_RX9_ACR 0x4000a1d4 +#define CYREG_CAN0_RX9_AMRD 0x4000a1d8 +#define CYREG_CAN0_RX9_ACRD 0x4000a1dc +#define CYDEV_CAN0_RX10_BASE 0x4000a1e0 +#define CYDEV_CAN0_RX10_SIZE 0x00000020 +#define CYREG_CAN0_RX10_CMD 0x4000a1e0 +#define CYREG_CAN0_RX10_ID 0x4000a1e4 +#define CYREG_CAN0_RX10_DH 0x4000a1e8 +#define CYREG_CAN0_RX10_DL 0x4000a1ec +#define CYREG_CAN0_RX10_AMR 0x4000a1f0 +#define CYREG_CAN0_RX10_ACR 0x4000a1f4 +#define CYREG_CAN0_RX10_AMRD 0x4000a1f8 +#define CYREG_CAN0_RX10_ACRD 0x4000a1fc +#define CYDEV_CAN0_RX11_BASE 0x4000a200 +#define CYDEV_CAN0_RX11_SIZE 0x00000020 +#define CYREG_CAN0_RX11_CMD 0x4000a200 +#define CYREG_CAN0_RX11_ID 0x4000a204 +#define CYREG_CAN0_RX11_DH 0x4000a208 +#define CYREG_CAN0_RX11_DL 0x4000a20c +#define CYREG_CAN0_RX11_AMR 0x4000a210 +#define CYREG_CAN0_RX11_ACR 0x4000a214 +#define CYREG_CAN0_RX11_AMRD 0x4000a218 +#define CYREG_CAN0_RX11_ACRD 0x4000a21c +#define CYDEV_CAN0_RX12_BASE 0x4000a220 +#define CYDEV_CAN0_RX12_SIZE 0x00000020 +#define CYREG_CAN0_RX12_CMD 0x4000a220 +#define CYREG_CAN0_RX12_ID 0x4000a224 +#define CYREG_CAN0_RX12_DH 0x4000a228 +#define CYREG_CAN0_RX12_DL 0x4000a22c +#define CYREG_CAN0_RX12_AMR 0x4000a230 +#define CYREG_CAN0_RX12_ACR 0x4000a234 +#define CYREG_CAN0_RX12_AMRD 0x4000a238 +#define CYREG_CAN0_RX12_ACRD 0x4000a23c +#define CYDEV_CAN0_RX13_BASE 0x4000a240 +#define CYDEV_CAN0_RX13_SIZE 0x00000020 +#define CYREG_CAN0_RX13_CMD 0x4000a240 +#define CYREG_CAN0_RX13_ID 0x4000a244 +#define CYREG_CAN0_RX13_DH 0x4000a248 +#define CYREG_CAN0_RX13_DL 0x4000a24c +#define CYREG_CAN0_RX13_AMR 0x4000a250 +#define CYREG_CAN0_RX13_ACR 0x4000a254 +#define CYREG_CAN0_RX13_AMRD 0x4000a258 +#define CYREG_CAN0_RX13_ACRD 0x4000a25c +#define CYDEV_CAN0_RX14_BASE 0x4000a260 +#define CYDEV_CAN0_RX14_SIZE 0x00000020 +#define CYREG_CAN0_RX14_CMD 0x4000a260 +#define CYREG_CAN0_RX14_ID 0x4000a264 +#define CYREG_CAN0_RX14_DH 0x4000a268 +#define CYREG_CAN0_RX14_DL 0x4000a26c +#define CYREG_CAN0_RX14_AMR 0x4000a270 +#define CYREG_CAN0_RX14_ACR 0x4000a274 +#define CYREG_CAN0_RX14_AMRD 0x4000a278 +#define CYREG_CAN0_RX14_ACRD 0x4000a27c +#define CYDEV_CAN0_RX15_BASE 0x4000a280 +#define CYDEV_CAN0_RX15_SIZE 0x00000020 +#define CYREG_CAN0_RX15_CMD 0x4000a280 +#define CYREG_CAN0_RX15_ID 0x4000a284 +#define CYREG_CAN0_RX15_DH 0x4000a288 +#define CYREG_CAN0_RX15_DL 0x4000a28c +#define CYREG_CAN0_RX15_AMR 0x4000a290 +#define CYREG_CAN0_RX15_ACR 0x4000a294 +#define CYREG_CAN0_RX15_AMRD 0x4000a298 +#define CYREG_CAN0_RX15_ACRD 0x4000a29c +#define CYDEV_DFB0_BASE 0x4000c000 +#define CYDEV_DFB0_SIZE 0x000007b5 +#define CYDEV_DFB0_DPA_SRAM_BASE 0x4000c000 +#define CYDEV_DFB0_DPA_SRAM_SIZE 0x00000200 +#define CYREG_DFB0_DPA_SRAM_DATA_MBASE 0x4000c000 +#define CYREG_DFB0_DPA_SRAM_DATA_MSIZE 0x00000200 +#define CYDEV_DFB0_DPB_SRAM_BASE 0x4000c200 +#define CYDEV_DFB0_DPB_SRAM_SIZE 0x00000200 +#define CYREG_DFB0_DPB_SRAM_DATA_MBASE 0x4000c200 +#define CYREG_DFB0_DPB_SRAM_DATA_MSIZE 0x00000200 +#define CYDEV_DFB0_CSA_SRAM_BASE 0x4000c400 +#define CYDEV_DFB0_CSA_SRAM_SIZE 0x00000100 +#define CYREG_DFB0_CSA_SRAM_DATA_MBASE 0x4000c400 +#define CYREG_DFB0_CSA_SRAM_DATA_MSIZE 0x00000100 +#define CYDEV_DFB0_CSB_SRAM_BASE 0x4000c500 +#define CYDEV_DFB0_CSB_SRAM_SIZE 0x00000100 +#define CYREG_DFB0_CSB_SRAM_DATA_MBASE 0x4000c500 +#define CYREG_DFB0_CSB_SRAM_DATA_MSIZE 0x00000100 +#define CYDEV_DFB0_FSM_SRAM_BASE 0x4000c600 +#define CYDEV_DFB0_FSM_SRAM_SIZE 0x00000100 +#define CYREG_DFB0_FSM_SRAM_DATA_MBASE 0x4000c600 +#define CYREG_DFB0_FSM_SRAM_DATA_MSIZE 0x00000100 +#define CYDEV_DFB0_ACU_SRAM_BASE 0x4000c700 +#define CYDEV_DFB0_ACU_SRAM_SIZE 0x00000040 +#define CYREG_DFB0_ACU_SRAM_DATA_MBASE 0x4000c700 +#define CYREG_DFB0_ACU_SRAM_DATA_MSIZE 0x00000040 +#define CYREG_DFB0_CR 0x4000c780 +#define CYREG_DFB0_SR 0x4000c784 +#define CYREG_DFB0_RAM_EN 0x4000c788 +#define CYREG_DFB0_RAM_DIR 0x4000c78c +#define CYREG_DFB0_SEMA 0x4000c790 +#define CYREG_DFB0_DSI_CTRL 0x4000c794 +#define CYREG_DFB0_INT_CTRL 0x4000c798 +#define CYREG_DFB0_DMA_CTRL 0x4000c79c +#define CYREG_DFB0_STAGEA 0x4000c7a0 +#define CYREG_DFB0_STAGEAM 0x4000c7a1 +#define CYREG_DFB0_STAGEAH 0x4000c7a2 +#define CYREG_DFB0_STAGEB 0x4000c7a4 +#define CYREG_DFB0_STAGEBM 0x4000c7a5 +#define CYREG_DFB0_STAGEBH 0x4000c7a6 +#define CYREG_DFB0_HOLDA 0x4000c7a8 +#define CYREG_DFB0_HOLDAM 0x4000c7a9 +#define CYREG_DFB0_HOLDAH 0x4000c7aa +#define CYREG_DFB0_HOLDAS 0x4000c7ab +#define CYREG_DFB0_HOLDB 0x4000c7ac +#define CYREG_DFB0_HOLDBM 0x4000c7ad +#define CYREG_DFB0_HOLDBH 0x4000c7ae +#define CYREG_DFB0_HOLDBS 0x4000c7af +#define CYREG_DFB0_COHER 0x4000c7b0 +#define CYREG_DFB0_DALIGN 0x4000c7b4 +#define CYDEV_UCFG_BASE 0x40010000 +#define CYDEV_UCFG_SIZE 0x00005040 +#define CYDEV_UCFG_B0_BASE 0x40010000 +#define CYDEV_UCFG_B0_SIZE 0x00000fef +#define CYDEV_UCFG_B0_P0_BASE 0x40010000 +#define CYDEV_UCFG_B0_P0_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P0_U0_BASE 0x40010000 +#define CYDEV_UCFG_B0_P0_U0_SIZE 0x00000070 +#define CYREG_B0_P0_U0_PLD_IT0 0x40010000 +#define CYREG_B0_P0_U0_PLD_IT1 0x40010004 +#define CYREG_B0_P0_U0_PLD_IT2 0x40010008 +#define CYREG_B0_P0_U0_PLD_IT3 0x4001000c +#define CYREG_B0_P0_U0_PLD_IT4 0x40010010 +#define CYREG_B0_P0_U0_PLD_IT5 0x40010014 +#define CYREG_B0_P0_U0_PLD_IT6 0x40010018 +#define CYREG_B0_P0_U0_PLD_IT7 0x4001001c +#define CYREG_B0_P0_U0_PLD_IT8 0x40010020 +#define CYREG_B0_P0_U0_PLD_IT9 0x40010024 +#define CYREG_B0_P0_U0_PLD_IT10 0x40010028 +#define CYREG_B0_P0_U0_PLD_IT11 0x4001002c +#define CYREG_B0_P0_U0_PLD_ORT0 0x40010030 +#define CYREG_B0_P0_U0_PLD_ORT1 0x40010032 +#define CYREG_B0_P0_U0_PLD_ORT2 0x40010034 +#define CYREG_B0_P0_U0_PLD_ORT3 0x40010036 +#define CYREG_B0_P0_U0_MC_CFG_CEN_CONST 0x40010038 +#define CYREG_B0_P0_U0_MC_CFG_XORFB 0x4001003a +#define CYREG_B0_P0_U0_MC_CFG_SET_RESET 0x4001003c +#define CYREG_B0_P0_U0_MC_CFG_BYPASS 0x4001003e +#define CYREG_B0_P0_U0_CFG0 0x40010040 +#define CYREG_B0_P0_U0_CFG1 0x40010041 +#define CYREG_B0_P0_U0_CFG2 0x40010042 +#define CYREG_B0_P0_U0_CFG3 0x40010043 +#define CYREG_B0_P0_U0_CFG4 0x40010044 +#define CYREG_B0_P0_U0_CFG5 0x40010045 +#define CYREG_B0_P0_U0_CFG6 0x40010046 +#define CYREG_B0_P0_U0_CFG7 0x40010047 +#define CYREG_B0_P0_U0_CFG8 0x40010048 +#define CYREG_B0_P0_U0_CFG9 0x40010049 +#define CYREG_B0_P0_U0_CFG10 0x4001004a +#define CYREG_B0_P0_U0_CFG11 0x4001004b +#define CYREG_B0_P0_U0_CFG12 0x4001004c +#define CYREG_B0_P0_U0_CFG13 0x4001004d +#define CYREG_B0_P0_U0_CFG14 0x4001004e +#define CYREG_B0_P0_U0_CFG15 0x4001004f +#define CYREG_B0_P0_U0_CFG16 0x40010050 +#define CYREG_B0_P0_U0_CFG17 0x40010051 +#define CYREG_B0_P0_U0_CFG18 0x40010052 +#define CYREG_B0_P0_U0_CFG19 0x40010053 +#define CYREG_B0_P0_U0_CFG20 0x40010054 +#define CYREG_B0_P0_U0_CFG21 0x40010055 +#define CYREG_B0_P0_U0_CFG22 0x40010056 +#define CYREG_B0_P0_U0_CFG23 0x40010057 +#define CYREG_B0_P0_U0_CFG24 0x40010058 +#define CYREG_B0_P0_U0_CFG25 0x40010059 +#define CYREG_B0_P0_U0_CFG26 0x4001005a +#define CYREG_B0_P0_U0_CFG27 0x4001005b +#define CYREG_B0_P0_U0_CFG28 0x4001005c +#define CYREG_B0_P0_U0_CFG29 0x4001005d +#define CYREG_B0_P0_U0_CFG30 0x4001005e +#define CYREG_B0_P0_U0_CFG31 0x4001005f +#define CYREG_B0_P0_U0_DCFG0 0x40010060 +#define CYREG_B0_P0_U0_DCFG1 0x40010062 +#define CYREG_B0_P0_U0_DCFG2 0x40010064 +#define CYREG_B0_P0_U0_DCFG3 0x40010066 +#define CYREG_B0_P0_U0_DCFG4 0x40010068 +#define CYREG_B0_P0_U0_DCFG5 0x4001006a +#define CYREG_B0_P0_U0_DCFG6 0x4001006c +#define CYREG_B0_P0_U0_DCFG7 0x4001006e +#define CYDEV_UCFG_B0_P0_U1_BASE 0x40010080 +#define CYDEV_UCFG_B0_P0_U1_SIZE 0x00000070 +#define CYREG_B0_P0_U1_PLD_IT0 0x40010080 +#define CYREG_B0_P0_U1_PLD_IT1 0x40010084 +#define CYREG_B0_P0_U1_PLD_IT2 0x40010088 +#define CYREG_B0_P0_U1_PLD_IT3 0x4001008c +#define CYREG_B0_P0_U1_PLD_IT4 0x40010090 +#define CYREG_B0_P0_U1_PLD_IT5 0x40010094 +#define CYREG_B0_P0_U1_PLD_IT6 0x40010098 +#define CYREG_B0_P0_U1_PLD_IT7 0x4001009c +#define CYREG_B0_P0_U1_PLD_IT8 0x400100a0 +#define CYREG_B0_P0_U1_PLD_IT9 0x400100a4 +#define CYREG_B0_P0_U1_PLD_IT10 0x400100a8 +#define CYREG_B0_P0_U1_PLD_IT11 0x400100ac +#define CYREG_B0_P0_U1_PLD_ORT0 0x400100b0 +#define CYREG_B0_P0_U1_PLD_ORT1 0x400100b2 +#define CYREG_B0_P0_U1_PLD_ORT2 0x400100b4 +#define CYREG_B0_P0_U1_PLD_ORT3 0x400100b6 +#define CYREG_B0_P0_U1_MC_CFG_CEN_CONST 0x400100b8 +#define CYREG_B0_P0_U1_MC_CFG_XORFB 0x400100ba +#define CYREG_B0_P0_U1_MC_CFG_SET_RESET 0x400100bc +#define CYREG_B0_P0_U1_MC_CFG_BYPASS 0x400100be +#define CYREG_B0_P0_U1_CFG0 0x400100c0 +#define CYREG_B0_P0_U1_CFG1 0x400100c1 +#define CYREG_B0_P0_U1_CFG2 0x400100c2 +#define CYREG_B0_P0_U1_CFG3 0x400100c3 +#define CYREG_B0_P0_U1_CFG4 0x400100c4 +#define CYREG_B0_P0_U1_CFG5 0x400100c5 +#define CYREG_B0_P0_U1_CFG6 0x400100c6 +#define CYREG_B0_P0_U1_CFG7 0x400100c7 +#define CYREG_B0_P0_U1_CFG8 0x400100c8 +#define CYREG_B0_P0_U1_CFG9 0x400100c9 +#define CYREG_B0_P0_U1_CFG10 0x400100ca +#define CYREG_B0_P0_U1_CFG11 0x400100cb +#define CYREG_B0_P0_U1_CFG12 0x400100cc +#define CYREG_B0_P0_U1_CFG13 0x400100cd +#define CYREG_B0_P0_U1_CFG14 0x400100ce +#define CYREG_B0_P0_U1_CFG15 0x400100cf +#define CYREG_B0_P0_U1_CFG16 0x400100d0 +#define CYREG_B0_P0_U1_CFG17 0x400100d1 +#define CYREG_B0_P0_U1_CFG18 0x400100d2 +#define CYREG_B0_P0_U1_CFG19 0x400100d3 +#define CYREG_B0_P0_U1_CFG20 0x400100d4 +#define CYREG_B0_P0_U1_CFG21 0x400100d5 +#define CYREG_B0_P0_U1_CFG22 0x400100d6 +#define CYREG_B0_P0_U1_CFG23 0x400100d7 +#define CYREG_B0_P0_U1_CFG24 0x400100d8 +#define CYREG_B0_P0_U1_CFG25 0x400100d9 +#define CYREG_B0_P0_U1_CFG26 0x400100da +#define CYREG_B0_P0_U1_CFG27 0x400100db +#define CYREG_B0_P0_U1_CFG28 0x400100dc +#define CYREG_B0_P0_U1_CFG29 0x400100dd +#define CYREG_B0_P0_U1_CFG30 0x400100de +#define CYREG_B0_P0_U1_CFG31 0x400100df +#define CYREG_B0_P0_U1_DCFG0 0x400100e0 +#define CYREG_B0_P0_U1_DCFG1 0x400100e2 +#define CYREG_B0_P0_U1_DCFG2 0x400100e4 +#define CYREG_B0_P0_U1_DCFG3 0x400100e6 +#define CYREG_B0_P0_U1_DCFG4 0x400100e8 +#define CYREG_B0_P0_U1_DCFG5 0x400100ea +#define CYREG_B0_P0_U1_DCFG6 0x400100ec +#define CYREG_B0_P0_U1_DCFG7 0x400100ee +#define CYDEV_UCFG_B0_P0_ROUTE_BASE 0x40010100 +#define CYDEV_UCFG_B0_P0_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P1_BASE 0x40010200 +#define CYDEV_UCFG_B0_P1_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P1_U0_BASE 0x40010200 +#define CYDEV_UCFG_B0_P1_U0_SIZE 0x00000070 +#define CYREG_B0_P1_U0_PLD_IT0 0x40010200 +#define CYREG_B0_P1_U0_PLD_IT1 0x40010204 +#define CYREG_B0_P1_U0_PLD_IT2 0x40010208 +#define CYREG_B0_P1_U0_PLD_IT3 0x4001020c +#define CYREG_B0_P1_U0_PLD_IT4 0x40010210 +#define CYREG_B0_P1_U0_PLD_IT5 0x40010214 +#define CYREG_B0_P1_U0_PLD_IT6 0x40010218 +#define CYREG_B0_P1_U0_PLD_IT7 0x4001021c +#define CYREG_B0_P1_U0_PLD_IT8 0x40010220 +#define CYREG_B0_P1_U0_PLD_IT9 0x40010224 +#define CYREG_B0_P1_U0_PLD_IT10 0x40010228 +#define CYREG_B0_P1_U0_PLD_IT11 0x4001022c +#define CYREG_B0_P1_U0_PLD_ORT0 0x40010230 +#define CYREG_B0_P1_U0_PLD_ORT1 0x40010232 +#define CYREG_B0_P1_U0_PLD_ORT2 0x40010234 +#define CYREG_B0_P1_U0_PLD_ORT3 0x40010236 +#define CYREG_B0_P1_U0_MC_CFG_CEN_CONST 0x40010238 +#define CYREG_B0_P1_U0_MC_CFG_XORFB 0x4001023a +#define CYREG_B0_P1_U0_MC_CFG_SET_RESET 0x4001023c +#define CYREG_B0_P1_U0_MC_CFG_BYPASS 0x4001023e +#define CYREG_B0_P1_U0_CFG0 0x40010240 +#define CYREG_B0_P1_U0_CFG1 0x40010241 +#define CYREG_B0_P1_U0_CFG2 0x40010242 +#define CYREG_B0_P1_U0_CFG3 0x40010243 +#define CYREG_B0_P1_U0_CFG4 0x40010244 +#define CYREG_B0_P1_U0_CFG5 0x40010245 +#define CYREG_B0_P1_U0_CFG6 0x40010246 +#define CYREG_B0_P1_U0_CFG7 0x40010247 +#define CYREG_B0_P1_U0_CFG8 0x40010248 +#define CYREG_B0_P1_U0_CFG9 0x40010249 +#define CYREG_B0_P1_U0_CFG10 0x4001024a +#define CYREG_B0_P1_U0_CFG11 0x4001024b +#define CYREG_B0_P1_U0_CFG12 0x4001024c +#define CYREG_B0_P1_U0_CFG13 0x4001024d +#define CYREG_B0_P1_U0_CFG14 0x4001024e +#define CYREG_B0_P1_U0_CFG15 0x4001024f +#define CYREG_B0_P1_U0_CFG16 0x40010250 +#define CYREG_B0_P1_U0_CFG17 0x40010251 +#define CYREG_B0_P1_U0_CFG18 0x40010252 +#define CYREG_B0_P1_U0_CFG19 0x40010253 +#define CYREG_B0_P1_U0_CFG20 0x40010254 +#define CYREG_B0_P1_U0_CFG21 0x40010255 +#define CYREG_B0_P1_U0_CFG22 0x40010256 +#define CYREG_B0_P1_U0_CFG23 0x40010257 +#define CYREG_B0_P1_U0_CFG24 0x40010258 +#define CYREG_B0_P1_U0_CFG25 0x40010259 +#define CYREG_B0_P1_U0_CFG26 0x4001025a +#define CYREG_B0_P1_U0_CFG27 0x4001025b +#define CYREG_B0_P1_U0_CFG28 0x4001025c +#define CYREG_B0_P1_U0_CFG29 0x4001025d +#define CYREG_B0_P1_U0_CFG30 0x4001025e +#define CYREG_B0_P1_U0_CFG31 0x4001025f +#define CYREG_B0_P1_U0_DCFG0 0x40010260 +#define CYREG_B0_P1_U0_DCFG1 0x40010262 +#define CYREG_B0_P1_U0_DCFG2 0x40010264 +#define CYREG_B0_P1_U0_DCFG3 0x40010266 +#define CYREG_B0_P1_U0_DCFG4 0x40010268 +#define CYREG_B0_P1_U0_DCFG5 0x4001026a +#define CYREG_B0_P1_U0_DCFG6 0x4001026c +#define CYREG_B0_P1_U0_DCFG7 0x4001026e +#define CYDEV_UCFG_B0_P1_U1_BASE 0x40010280 +#define CYDEV_UCFG_B0_P1_U1_SIZE 0x00000070 +#define CYREG_B0_P1_U1_PLD_IT0 0x40010280 +#define CYREG_B0_P1_U1_PLD_IT1 0x40010284 +#define CYREG_B0_P1_U1_PLD_IT2 0x40010288 +#define CYREG_B0_P1_U1_PLD_IT3 0x4001028c +#define CYREG_B0_P1_U1_PLD_IT4 0x40010290 +#define CYREG_B0_P1_U1_PLD_IT5 0x40010294 +#define CYREG_B0_P1_U1_PLD_IT6 0x40010298 +#define CYREG_B0_P1_U1_PLD_IT7 0x4001029c +#define CYREG_B0_P1_U1_PLD_IT8 0x400102a0 +#define CYREG_B0_P1_U1_PLD_IT9 0x400102a4 +#define CYREG_B0_P1_U1_PLD_IT10 0x400102a8 +#define CYREG_B0_P1_U1_PLD_IT11 0x400102ac +#define CYREG_B0_P1_U1_PLD_ORT0 0x400102b0 +#define CYREG_B0_P1_U1_PLD_ORT1 0x400102b2 +#define CYREG_B0_P1_U1_PLD_ORT2 0x400102b4 +#define CYREG_B0_P1_U1_PLD_ORT3 0x400102b6 +#define CYREG_B0_P1_U1_MC_CFG_CEN_CONST 0x400102b8 +#define CYREG_B0_P1_U1_MC_CFG_XORFB 0x400102ba +#define CYREG_B0_P1_U1_MC_CFG_SET_RESET 0x400102bc +#define CYREG_B0_P1_U1_MC_CFG_BYPASS 0x400102be +#define CYREG_B0_P1_U1_CFG0 0x400102c0 +#define CYREG_B0_P1_U1_CFG1 0x400102c1 +#define CYREG_B0_P1_U1_CFG2 0x400102c2 +#define CYREG_B0_P1_U1_CFG3 0x400102c3 +#define CYREG_B0_P1_U1_CFG4 0x400102c4 +#define CYREG_B0_P1_U1_CFG5 0x400102c5 +#define CYREG_B0_P1_U1_CFG6 0x400102c6 +#define CYREG_B0_P1_U1_CFG7 0x400102c7 +#define CYREG_B0_P1_U1_CFG8 0x400102c8 +#define CYREG_B0_P1_U1_CFG9 0x400102c9 +#define CYREG_B0_P1_U1_CFG10 0x400102ca +#define CYREG_B0_P1_U1_CFG11 0x400102cb +#define CYREG_B0_P1_U1_CFG12 0x400102cc +#define CYREG_B0_P1_U1_CFG13 0x400102cd +#define CYREG_B0_P1_U1_CFG14 0x400102ce +#define CYREG_B0_P1_U1_CFG15 0x400102cf +#define CYREG_B0_P1_U1_CFG16 0x400102d0 +#define CYREG_B0_P1_U1_CFG17 0x400102d1 +#define CYREG_B0_P1_U1_CFG18 0x400102d2 +#define CYREG_B0_P1_U1_CFG19 0x400102d3 +#define CYREG_B0_P1_U1_CFG20 0x400102d4 +#define CYREG_B0_P1_U1_CFG21 0x400102d5 +#define CYREG_B0_P1_U1_CFG22 0x400102d6 +#define CYREG_B0_P1_U1_CFG23 0x400102d7 +#define CYREG_B0_P1_U1_CFG24 0x400102d8 +#define CYREG_B0_P1_U1_CFG25 0x400102d9 +#define CYREG_B0_P1_U1_CFG26 0x400102da +#define CYREG_B0_P1_U1_CFG27 0x400102db +#define CYREG_B0_P1_U1_CFG28 0x400102dc +#define CYREG_B0_P1_U1_CFG29 0x400102dd +#define CYREG_B0_P1_U1_CFG30 0x400102de +#define CYREG_B0_P1_U1_CFG31 0x400102df +#define CYREG_B0_P1_U1_DCFG0 0x400102e0 +#define CYREG_B0_P1_U1_DCFG1 0x400102e2 +#define CYREG_B0_P1_U1_DCFG2 0x400102e4 +#define CYREG_B0_P1_U1_DCFG3 0x400102e6 +#define CYREG_B0_P1_U1_DCFG4 0x400102e8 +#define CYREG_B0_P1_U1_DCFG5 0x400102ea +#define CYREG_B0_P1_U1_DCFG6 0x400102ec +#define CYREG_B0_P1_U1_DCFG7 0x400102ee +#define CYDEV_UCFG_B0_P1_ROUTE_BASE 0x40010300 +#define CYDEV_UCFG_B0_P1_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P2_BASE 0x40010400 +#define CYDEV_UCFG_B0_P2_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P2_U0_BASE 0x40010400 +#define CYDEV_UCFG_B0_P2_U0_SIZE 0x00000070 +#define CYREG_B0_P2_U0_PLD_IT0 0x40010400 +#define CYREG_B0_P2_U0_PLD_IT1 0x40010404 +#define CYREG_B0_P2_U0_PLD_IT2 0x40010408 +#define CYREG_B0_P2_U0_PLD_IT3 0x4001040c +#define CYREG_B0_P2_U0_PLD_IT4 0x40010410 +#define CYREG_B0_P2_U0_PLD_IT5 0x40010414 +#define CYREG_B0_P2_U0_PLD_IT6 0x40010418 +#define CYREG_B0_P2_U0_PLD_IT7 0x4001041c +#define CYREG_B0_P2_U0_PLD_IT8 0x40010420 +#define CYREG_B0_P2_U0_PLD_IT9 0x40010424 +#define CYREG_B0_P2_U0_PLD_IT10 0x40010428 +#define CYREG_B0_P2_U0_PLD_IT11 0x4001042c +#define CYREG_B0_P2_U0_PLD_ORT0 0x40010430 +#define CYREG_B0_P2_U0_PLD_ORT1 0x40010432 +#define CYREG_B0_P2_U0_PLD_ORT2 0x40010434 +#define CYREG_B0_P2_U0_PLD_ORT3 0x40010436 +#define CYREG_B0_P2_U0_MC_CFG_CEN_CONST 0x40010438 +#define CYREG_B0_P2_U0_MC_CFG_XORFB 0x4001043a +#define CYREG_B0_P2_U0_MC_CFG_SET_RESET 0x4001043c +#define CYREG_B0_P2_U0_MC_CFG_BYPASS 0x4001043e +#define CYREG_B0_P2_U0_CFG0 0x40010440 +#define CYREG_B0_P2_U0_CFG1 0x40010441 +#define CYREG_B0_P2_U0_CFG2 0x40010442 +#define CYREG_B0_P2_U0_CFG3 0x40010443 +#define CYREG_B0_P2_U0_CFG4 0x40010444 +#define CYREG_B0_P2_U0_CFG5 0x40010445 +#define CYREG_B0_P2_U0_CFG6 0x40010446 +#define CYREG_B0_P2_U0_CFG7 0x40010447 +#define CYREG_B0_P2_U0_CFG8 0x40010448 +#define CYREG_B0_P2_U0_CFG9 0x40010449 +#define CYREG_B0_P2_U0_CFG10 0x4001044a +#define CYREG_B0_P2_U0_CFG11 0x4001044b +#define CYREG_B0_P2_U0_CFG12 0x4001044c +#define CYREG_B0_P2_U0_CFG13 0x4001044d +#define CYREG_B0_P2_U0_CFG14 0x4001044e +#define CYREG_B0_P2_U0_CFG15 0x4001044f +#define CYREG_B0_P2_U0_CFG16 0x40010450 +#define CYREG_B0_P2_U0_CFG17 0x40010451 +#define CYREG_B0_P2_U0_CFG18 0x40010452 +#define CYREG_B0_P2_U0_CFG19 0x40010453 +#define CYREG_B0_P2_U0_CFG20 0x40010454 +#define CYREG_B0_P2_U0_CFG21 0x40010455 +#define CYREG_B0_P2_U0_CFG22 0x40010456 +#define CYREG_B0_P2_U0_CFG23 0x40010457 +#define CYREG_B0_P2_U0_CFG24 0x40010458 +#define CYREG_B0_P2_U0_CFG25 0x40010459 +#define CYREG_B0_P2_U0_CFG26 0x4001045a +#define CYREG_B0_P2_U0_CFG27 0x4001045b +#define CYREG_B0_P2_U0_CFG28 0x4001045c +#define CYREG_B0_P2_U0_CFG29 0x4001045d +#define CYREG_B0_P2_U0_CFG30 0x4001045e +#define CYREG_B0_P2_U0_CFG31 0x4001045f +#define CYREG_B0_P2_U0_DCFG0 0x40010460 +#define CYREG_B0_P2_U0_DCFG1 0x40010462 +#define CYREG_B0_P2_U0_DCFG2 0x40010464 +#define CYREG_B0_P2_U0_DCFG3 0x40010466 +#define CYREG_B0_P2_U0_DCFG4 0x40010468 +#define CYREG_B0_P2_U0_DCFG5 0x4001046a +#define CYREG_B0_P2_U0_DCFG6 0x4001046c +#define CYREG_B0_P2_U0_DCFG7 0x4001046e +#define CYDEV_UCFG_B0_P2_U1_BASE 0x40010480 +#define CYDEV_UCFG_B0_P2_U1_SIZE 0x00000070 +#define CYREG_B0_P2_U1_PLD_IT0 0x40010480 +#define CYREG_B0_P2_U1_PLD_IT1 0x40010484 +#define CYREG_B0_P2_U1_PLD_IT2 0x40010488 +#define CYREG_B0_P2_U1_PLD_IT3 0x4001048c +#define CYREG_B0_P2_U1_PLD_IT4 0x40010490 +#define CYREG_B0_P2_U1_PLD_IT5 0x40010494 +#define CYREG_B0_P2_U1_PLD_IT6 0x40010498 +#define CYREG_B0_P2_U1_PLD_IT7 0x4001049c +#define CYREG_B0_P2_U1_PLD_IT8 0x400104a0 +#define CYREG_B0_P2_U1_PLD_IT9 0x400104a4 +#define CYREG_B0_P2_U1_PLD_IT10 0x400104a8 +#define CYREG_B0_P2_U1_PLD_IT11 0x400104ac +#define CYREG_B0_P2_U1_PLD_ORT0 0x400104b0 +#define CYREG_B0_P2_U1_PLD_ORT1 0x400104b2 +#define CYREG_B0_P2_U1_PLD_ORT2 0x400104b4 +#define CYREG_B0_P2_U1_PLD_ORT3 0x400104b6 +#define CYREG_B0_P2_U1_MC_CFG_CEN_CONST 0x400104b8 +#define CYREG_B0_P2_U1_MC_CFG_XORFB 0x400104ba +#define CYREG_B0_P2_U1_MC_CFG_SET_RESET 0x400104bc +#define CYREG_B0_P2_U1_MC_CFG_BYPASS 0x400104be +#define CYREG_B0_P2_U1_CFG0 0x400104c0 +#define CYREG_B0_P2_U1_CFG1 0x400104c1 +#define CYREG_B0_P2_U1_CFG2 0x400104c2 +#define CYREG_B0_P2_U1_CFG3 0x400104c3 +#define CYREG_B0_P2_U1_CFG4 0x400104c4 +#define CYREG_B0_P2_U1_CFG5 0x400104c5 +#define CYREG_B0_P2_U1_CFG6 0x400104c6 +#define CYREG_B0_P2_U1_CFG7 0x400104c7 +#define CYREG_B0_P2_U1_CFG8 0x400104c8 +#define CYREG_B0_P2_U1_CFG9 0x400104c9 +#define CYREG_B0_P2_U1_CFG10 0x400104ca +#define CYREG_B0_P2_U1_CFG11 0x400104cb +#define CYREG_B0_P2_U1_CFG12 0x400104cc +#define CYREG_B0_P2_U1_CFG13 0x400104cd +#define CYREG_B0_P2_U1_CFG14 0x400104ce +#define CYREG_B0_P2_U1_CFG15 0x400104cf +#define CYREG_B0_P2_U1_CFG16 0x400104d0 +#define CYREG_B0_P2_U1_CFG17 0x400104d1 +#define CYREG_B0_P2_U1_CFG18 0x400104d2 +#define CYREG_B0_P2_U1_CFG19 0x400104d3 +#define CYREG_B0_P2_U1_CFG20 0x400104d4 +#define CYREG_B0_P2_U1_CFG21 0x400104d5 +#define CYREG_B0_P2_U1_CFG22 0x400104d6 +#define CYREG_B0_P2_U1_CFG23 0x400104d7 +#define CYREG_B0_P2_U1_CFG24 0x400104d8 +#define CYREG_B0_P2_U1_CFG25 0x400104d9 +#define CYREG_B0_P2_U1_CFG26 0x400104da +#define CYREG_B0_P2_U1_CFG27 0x400104db +#define CYREG_B0_P2_U1_CFG28 0x400104dc +#define CYREG_B0_P2_U1_CFG29 0x400104dd +#define CYREG_B0_P2_U1_CFG30 0x400104de +#define CYREG_B0_P2_U1_CFG31 0x400104df +#define CYREG_B0_P2_U1_DCFG0 0x400104e0 +#define CYREG_B0_P2_U1_DCFG1 0x400104e2 +#define CYREG_B0_P2_U1_DCFG2 0x400104e4 +#define CYREG_B0_P2_U1_DCFG3 0x400104e6 +#define CYREG_B0_P2_U1_DCFG4 0x400104e8 +#define CYREG_B0_P2_U1_DCFG5 0x400104ea +#define CYREG_B0_P2_U1_DCFG6 0x400104ec +#define CYREG_B0_P2_U1_DCFG7 0x400104ee +#define CYDEV_UCFG_B0_P2_ROUTE_BASE 0x40010500 +#define CYDEV_UCFG_B0_P2_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P3_BASE 0x40010600 +#define CYDEV_UCFG_B0_P3_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P3_U0_BASE 0x40010600 +#define CYDEV_UCFG_B0_P3_U0_SIZE 0x00000070 +#define CYREG_B0_P3_U0_PLD_IT0 0x40010600 +#define CYREG_B0_P3_U0_PLD_IT1 0x40010604 +#define CYREG_B0_P3_U0_PLD_IT2 0x40010608 +#define CYREG_B0_P3_U0_PLD_IT3 0x4001060c +#define CYREG_B0_P3_U0_PLD_IT4 0x40010610 +#define CYREG_B0_P3_U0_PLD_IT5 0x40010614 +#define CYREG_B0_P3_U0_PLD_IT6 0x40010618 +#define CYREG_B0_P3_U0_PLD_IT7 0x4001061c +#define CYREG_B0_P3_U0_PLD_IT8 0x40010620 +#define CYREG_B0_P3_U0_PLD_IT9 0x40010624 +#define CYREG_B0_P3_U0_PLD_IT10 0x40010628 +#define CYREG_B0_P3_U0_PLD_IT11 0x4001062c +#define CYREG_B0_P3_U0_PLD_ORT0 0x40010630 +#define CYREG_B0_P3_U0_PLD_ORT1 0x40010632 +#define CYREG_B0_P3_U0_PLD_ORT2 0x40010634 +#define CYREG_B0_P3_U0_PLD_ORT3 0x40010636 +#define CYREG_B0_P3_U0_MC_CFG_CEN_CONST 0x40010638 +#define CYREG_B0_P3_U0_MC_CFG_XORFB 0x4001063a +#define CYREG_B0_P3_U0_MC_CFG_SET_RESET 0x4001063c +#define CYREG_B0_P3_U0_MC_CFG_BYPASS 0x4001063e +#define CYREG_B0_P3_U0_CFG0 0x40010640 +#define CYREG_B0_P3_U0_CFG1 0x40010641 +#define CYREG_B0_P3_U0_CFG2 0x40010642 +#define CYREG_B0_P3_U0_CFG3 0x40010643 +#define CYREG_B0_P3_U0_CFG4 0x40010644 +#define CYREG_B0_P3_U0_CFG5 0x40010645 +#define CYREG_B0_P3_U0_CFG6 0x40010646 +#define CYREG_B0_P3_U0_CFG7 0x40010647 +#define CYREG_B0_P3_U0_CFG8 0x40010648 +#define CYREG_B0_P3_U0_CFG9 0x40010649 +#define CYREG_B0_P3_U0_CFG10 0x4001064a +#define CYREG_B0_P3_U0_CFG11 0x4001064b +#define CYREG_B0_P3_U0_CFG12 0x4001064c +#define CYREG_B0_P3_U0_CFG13 0x4001064d +#define CYREG_B0_P3_U0_CFG14 0x4001064e +#define CYREG_B0_P3_U0_CFG15 0x4001064f +#define CYREG_B0_P3_U0_CFG16 0x40010650 +#define CYREG_B0_P3_U0_CFG17 0x40010651 +#define CYREG_B0_P3_U0_CFG18 0x40010652 +#define CYREG_B0_P3_U0_CFG19 0x40010653 +#define CYREG_B0_P3_U0_CFG20 0x40010654 +#define CYREG_B0_P3_U0_CFG21 0x40010655 +#define CYREG_B0_P3_U0_CFG22 0x40010656 +#define CYREG_B0_P3_U0_CFG23 0x40010657 +#define CYREG_B0_P3_U0_CFG24 0x40010658 +#define CYREG_B0_P3_U0_CFG25 0x40010659 +#define CYREG_B0_P3_U0_CFG26 0x4001065a +#define CYREG_B0_P3_U0_CFG27 0x4001065b +#define CYREG_B0_P3_U0_CFG28 0x4001065c +#define CYREG_B0_P3_U0_CFG29 0x4001065d +#define CYREG_B0_P3_U0_CFG30 0x4001065e +#define CYREG_B0_P3_U0_CFG31 0x4001065f +#define CYREG_B0_P3_U0_DCFG0 0x40010660 +#define CYREG_B0_P3_U0_DCFG1 0x40010662 +#define CYREG_B0_P3_U0_DCFG2 0x40010664 +#define CYREG_B0_P3_U0_DCFG3 0x40010666 +#define CYREG_B0_P3_U0_DCFG4 0x40010668 +#define CYREG_B0_P3_U0_DCFG5 0x4001066a +#define CYREG_B0_P3_U0_DCFG6 0x4001066c +#define CYREG_B0_P3_U0_DCFG7 0x4001066e +#define CYDEV_UCFG_B0_P3_U1_BASE 0x40010680 +#define CYDEV_UCFG_B0_P3_U1_SIZE 0x00000070 +#define CYREG_B0_P3_U1_PLD_IT0 0x40010680 +#define CYREG_B0_P3_U1_PLD_IT1 0x40010684 +#define CYREG_B0_P3_U1_PLD_IT2 0x40010688 +#define CYREG_B0_P3_U1_PLD_IT3 0x4001068c +#define CYREG_B0_P3_U1_PLD_IT4 0x40010690 +#define CYREG_B0_P3_U1_PLD_IT5 0x40010694 +#define CYREG_B0_P3_U1_PLD_IT6 0x40010698 +#define CYREG_B0_P3_U1_PLD_IT7 0x4001069c +#define CYREG_B0_P3_U1_PLD_IT8 0x400106a0 +#define CYREG_B0_P3_U1_PLD_IT9 0x400106a4 +#define CYREG_B0_P3_U1_PLD_IT10 0x400106a8 +#define CYREG_B0_P3_U1_PLD_IT11 0x400106ac +#define CYREG_B0_P3_U1_PLD_ORT0 0x400106b0 +#define CYREG_B0_P3_U1_PLD_ORT1 0x400106b2 +#define CYREG_B0_P3_U1_PLD_ORT2 0x400106b4 +#define CYREG_B0_P3_U1_PLD_ORT3 0x400106b6 +#define CYREG_B0_P3_U1_MC_CFG_CEN_CONST 0x400106b8 +#define CYREG_B0_P3_U1_MC_CFG_XORFB 0x400106ba +#define CYREG_B0_P3_U1_MC_CFG_SET_RESET 0x400106bc +#define CYREG_B0_P3_U1_MC_CFG_BYPASS 0x400106be +#define CYREG_B0_P3_U1_CFG0 0x400106c0 +#define CYREG_B0_P3_U1_CFG1 0x400106c1 +#define CYREG_B0_P3_U1_CFG2 0x400106c2 +#define CYREG_B0_P3_U1_CFG3 0x400106c3 +#define CYREG_B0_P3_U1_CFG4 0x400106c4 +#define CYREG_B0_P3_U1_CFG5 0x400106c5 +#define CYREG_B0_P3_U1_CFG6 0x400106c6 +#define CYREG_B0_P3_U1_CFG7 0x400106c7 +#define CYREG_B0_P3_U1_CFG8 0x400106c8 +#define CYREG_B0_P3_U1_CFG9 0x400106c9 +#define CYREG_B0_P3_U1_CFG10 0x400106ca +#define CYREG_B0_P3_U1_CFG11 0x400106cb +#define CYREG_B0_P3_U1_CFG12 0x400106cc +#define CYREG_B0_P3_U1_CFG13 0x400106cd +#define CYREG_B0_P3_U1_CFG14 0x400106ce +#define CYREG_B0_P3_U1_CFG15 0x400106cf +#define CYREG_B0_P3_U1_CFG16 0x400106d0 +#define CYREG_B0_P3_U1_CFG17 0x400106d1 +#define CYREG_B0_P3_U1_CFG18 0x400106d2 +#define CYREG_B0_P3_U1_CFG19 0x400106d3 +#define CYREG_B0_P3_U1_CFG20 0x400106d4 +#define CYREG_B0_P3_U1_CFG21 0x400106d5 +#define CYREG_B0_P3_U1_CFG22 0x400106d6 +#define CYREG_B0_P3_U1_CFG23 0x400106d7 +#define CYREG_B0_P3_U1_CFG24 0x400106d8 +#define CYREG_B0_P3_U1_CFG25 0x400106d9 +#define CYREG_B0_P3_U1_CFG26 0x400106da +#define CYREG_B0_P3_U1_CFG27 0x400106db +#define CYREG_B0_P3_U1_CFG28 0x400106dc +#define CYREG_B0_P3_U1_CFG29 0x400106dd +#define CYREG_B0_P3_U1_CFG30 0x400106de +#define CYREG_B0_P3_U1_CFG31 0x400106df +#define CYREG_B0_P3_U1_DCFG0 0x400106e0 +#define CYREG_B0_P3_U1_DCFG1 0x400106e2 +#define CYREG_B0_P3_U1_DCFG2 0x400106e4 +#define CYREG_B0_P3_U1_DCFG3 0x400106e6 +#define CYREG_B0_P3_U1_DCFG4 0x400106e8 +#define CYREG_B0_P3_U1_DCFG5 0x400106ea +#define CYREG_B0_P3_U1_DCFG6 0x400106ec +#define CYREG_B0_P3_U1_DCFG7 0x400106ee +#define CYDEV_UCFG_B0_P3_ROUTE_BASE 0x40010700 +#define CYDEV_UCFG_B0_P3_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P4_BASE 0x40010800 +#define CYDEV_UCFG_B0_P4_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P4_U0_BASE 0x40010800 +#define CYDEV_UCFG_B0_P4_U0_SIZE 0x00000070 +#define CYREG_B0_P4_U0_PLD_IT0 0x40010800 +#define CYREG_B0_P4_U0_PLD_IT1 0x40010804 +#define CYREG_B0_P4_U0_PLD_IT2 0x40010808 +#define CYREG_B0_P4_U0_PLD_IT3 0x4001080c +#define CYREG_B0_P4_U0_PLD_IT4 0x40010810 +#define CYREG_B0_P4_U0_PLD_IT5 0x40010814 +#define CYREG_B0_P4_U0_PLD_IT6 0x40010818 +#define CYREG_B0_P4_U0_PLD_IT7 0x4001081c +#define CYREG_B0_P4_U0_PLD_IT8 0x40010820 +#define CYREG_B0_P4_U0_PLD_IT9 0x40010824 +#define CYREG_B0_P4_U0_PLD_IT10 0x40010828 +#define CYREG_B0_P4_U0_PLD_IT11 0x4001082c +#define CYREG_B0_P4_U0_PLD_ORT0 0x40010830 +#define CYREG_B0_P4_U0_PLD_ORT1 0x40010832 +#define CYREG_B0_P4_U0_PLD_ORT2 0x40010834 +#define CYREG_B0_P4_U0_PLD_ORT3 0x40010836 +#define CYREG_B0_P4_U0_MC_CFG_CEN_CONST 0x40010838 +#define CYREG_B0_P4_U0_MC_CFG_XORFB 0x4001083a +#define CYREG_B0_P4_U0_MC_CFG_SET_RESET 0x4001083c +#define CYREG_B0_P4_U0_MC_CFG_BYPASS 0x4001083e +#define CYREG_B0_P4_U0_CFG0 0x40010840 +#define CYREG_B0_P4_U0_CFG1 0x40010841 +#define CYREG_B0_P4_U0_CFG2 0x40010842 +#define CYREG_B0_P4_U0_CFG3 0x40010843 +#define CYREG_B0_P4_U0_CFG4 0x40010844 +#define CYREG_B0_P4_U0_CFG5 0x40010845 +#define CYREG_B0_P4_U0_CFG6 0x40010846 +#define CYREG_B0_P4_U0_CFG7 0x40010847 +#define CYREG_B0_P4_U0_CFG8 0x40010848 +#define CYREG_B0_P4_U0_CFG9 0x40010849 +#define CYREG_B0_P4_U0_CFG10 0x4001084a +#define CYREG_B0_P4_U0_CFG11 0x4001084b +#define CYREG_B0_P4_U0_CFG12 0x4001084c +#define CYREG_B0_P4_U0_CFG13 0x4001084d +#define CYREG_B0_P4_U0_CFG14 0x4001084e +#define CYREG_B0_P4_U0_CFG15 0x4001084f +#define CYREG_B0_P4_U0_CFG16 0x40010850 +#define CYREG_B0_P4_U0_CFG17 0x40010851 +#define CYREG_B0_P4_U0_CFG18 0x40010852 +#define CYREG_B0_P4_U0_CFG19 0x40010853 +#define CYREG_B0_P4_U0_CFG20 0x40010854 +#define CYREG_B0_P4_U0_CFG21 0x40010855 +#define CYREG_B0_P4_U0_CFG22 0x40010856 +#define CYREG_B0_P4_U0_CFG23 0x40010857 +#define CYREG_B0_P4_U0_CFG24 0x40010858 +#define CYREG_B0_P4_U0_CFG25 0x40010859 +#define CYREG_B0_P4_U0_CFG26 0x4001085a +#define CYREG_B0_P4_U0_CFG27 0x4001085b +#define CYREG_B0_P4_U0_CFG28 0x4001085c +#define CYREG_B0_P4_U0_CFG29 0x4001085d +#define CYREG_B0_P4_U0_CFG30 0x4001085e +#define CYREG_B0_P4_U0_CFG31 0x4001085f +#define CYREG_B0_P4_U0_DCFG0 0x40010860 +#define CYREG_B0_P4_U0_DCFG1 0x40010862 +#define CYREG_B0_P4_U0_DCFG2 0x40010864 +#define CYREG_B0_P4_U0_DCFG3 0x40010866 +#define CYREG_B0_P4_U0_DCFG4 0x40010868 +#define CYREG_B0_P4_U0_DCFG5 0x4001086a +#define CYREG_B0_P4_U0_DCFG6 0x4001086c +#define CYREG_B0_P4_U0_DCFG7 0x4001086e +#define CYDEV_UCFG_B0_P4_U1_BASE 0x40010880 +#define CYDEV_UCFG_B0_P4_U1_SIZE 0x00000070 +#define CYREG_B0_P4_U1_PLD_IT0 0x40010880 +#define CYREG_B0_P4_U1_PLD_IT1 0x40010884 +#define CYREG_B0_P4_U1_PLD_IT2 0x40010888 +#define CYREG_B0_P4_U1_PLD_IT3 0x4001088c +#define CYREG_B0_P4_U1_PLD_IT4 0x40010890 +#define CYREG_B0_P4_U1_PLD_IT5 0x40010894 +#define CYREG_B0_P4_U1_PLD_IT6 0x40010898 +#define CYREG_B0_P4_U1_PLD_IT7 0x4001089c +#define CYREG_B0_P4_U1_PLD_IT8 0x400108a0 +#define CYREG_B0_P4_U1_PLD_IT9 0x400108a4 +#define CYREG_B0_P4_U1_PLD_IT10 0x400108a8 +#define CYREG_B0_P4_U1_PLD_IT11 0x400108ac +#define CYREG_B0_P4_U1_PLD_ORT0 0x400108b0 +#define CYREG_B0_P4_U1_PLD_ORT1 0x400108b2 +#define CYREG_B0_P4_U1_PLD_ORT2 0x400108b4 +#define CYREG_B0_P4_U1_PLD_ORT3 0x400108b6 +#define CYREG_B0_P4_U1_MC_CFG_CEN_CONST 0x400108b8 +#define CYREG_B0_P4_U1_MC_CFG_XORFB 0x400108ba +#define CYREG_B0_P4_U1_MC_CFG_SET_RESET 0x400108bc +#define CYREG_B0_P4_U1_MC_CFG_BYPASS 0x400108be +#define CYREG_B0_P4_U1_CFG0 0x400108c0 +#define CYREG_B0_P4_U1_CFG1 0x400108c1 +#define CYREG_B0_P4_U1_CFG2 0x400108c2 +#define CYREG_B0_P4_U1_CFG3 0x400108c3 +#define CYREG_B0_P4_U1_CFG4 0x400108c4 +#define CYREG_B0_P4_U1_CFG5 0x400108c5 +#define CYREG_B0_P4_U1_CFG6 0x400108c6 +#define CYREG_B0_P4_U1_CFG7 0x400108c7 +#define CYREG_B0_P4_U1_CFG8 0x400108c8 +#define CYREG_B0_P4_U1_CFG9 0x400108c9 +#define CYREG_B0_P4_U1_CFG10 0x400108ca +#define CYREG_B0_P4_U1_CFG11 0x400108cb +#define CYREG_B0_P4_U1_CFG12 0x400108cc +#define CYREG_B0_P4_U1_CFG13 0x400108cd +#define CYREG_B0_P4_U1_CFG14 0x400108ce +#define CYREG_B0_P4_U1_CFG15 0x400108cf +#define CYREG_B0_P4_U1_CFG16 0x400108d0 +#define CYREG_B0_P4_U1_CFG17 0x400108d1 +#define CYREG_B0_P4_U1_CFG18 0x400108d2 +#define CYREG_B0_P4_U1_CFG19 0x400108d3 +#define CYREG_B0_P4_U1_CFG20 0x400108d4 +#define CYREG_B0_P4_U1_CFG21 0x400108d5 +#define CYREG_B0_P4_U1_CFG22 0x400108d6 +#define CYREG_B0_P4_U1_CFG23 0x400108d7 +#define CYREG_B0_P4_U1_CFG24 0x400108d8 +#define CYREG_B0_P4_U1_CFG25 0x400108d9 +#define CYREG_B0_P4_U1_CFG26 0x400108da +#define CYREG_B0_P4_U1_CFG27 0x400108db +#define CYREG_B0_P4_U1_CFG28 0x400108dc +#define CYREG_B0_P4_U1_CFG29 0x400108dd +#define CYREG_B0_P4_U1_CFG30 0x400108de +#define CYREG_B0_P4_U1_CFG31 0x400108df +#define CYREG_B0_P4_U1_DCFG0 0x400108e0 +#define CYREG_B0_P4_U1_DCFG1 0x400108e2 +#define CYREG_B0_P4_U1_DCFG2 0x400108e4 +#define CYREG_B0_P4_U1_DCFG3 0x400108e6 +#define CYREG_B0_P4_U1_DCFG4 0x400108e8 +#define CYREG_B0_P4_U1_DCFG5 0x400108ea +#define CYREG_B0_P4_U1_DCFG6 0x400108ec +#define CYREG_B0_P4_U1_DCFG7 0x400108ee +#define CYDEV_UCFG_B0_P4_ROUTE_BASE 0x40010900 +#define CYDEV_UCFG_B0_P4_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P5_BASE 0x40010a00 +#define CYDEV_UCFG_B0_P5_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P5_U0_BASE 0x40010a00 +#define CYDEV_UCFG_B0_P5_U0_SIZE 0x00000070 +#define CYREG_B0_P5_U0_PLD_IT0 0x40010a00 +#define CYREG_B0_P5_U0_PLD_IT1 0x40010a04 +#define CYREG_B0_P5_U0_PLD_IT2 0x40010a08 +#define CYREG_B0_P5_U0_PLD_IT3 0x40010a0c +#define CYREG_B0_P5_U0_PLD_IT4 0x40010a10 +#define CYREG_B0_P5_U0_PLD_IT5 0x40010a14 +#define CYREG_B0_P5_U0_PLD_IT6 0x40010a18 +#define CYREG_B0_P5_U0_PLD_IT7 0x40010a1c +#define CYREG_B0_P5_U0_PLD_IT8 0x40010a20 +#define CYREG_B0_P5_U0_PLD_IT9 0x40010a24 +#define CYREG_B0_P5_U0_PLD_IT10 0x40010a28 +#define CYREG_B0_P5_U0_PLD_IT11 0x40010a2c +#define CYREG_B0_P5_U0_PLD_ORT0 0x40010a30 +#define CYREG_B0_P5_U0_PLD_ORT1 0x40010a32 +#define CYREG_B0_P5_U0_PLD_ORT2 0x40010a34 +#define CYREG_B0_P5_U0_PLD_ORT3 0x40010a36 +#define CYREG_B0_P5_U0_MC_CFG_CEN_CONST 0x40010a38 +#define CYREG_B0_P5_U0_MC_CFG_XORFB 0x40010a3a +#define CYREG_B0_P5_U0_MC_CFG_SET_RESET 0x40010a3c +#define CYREG_B0_P5_U0_MC_CFG_BYPASS 0x40010a3e +#define CYREG_B0_P5_U0_CFG0 0x40010a40 +#define CYREG_B0_P5_U0_CFG1 0x40010a41 +#define CYREG_B0_P5_U0_CFG2 0x40010a42 +#define CYREG_B0_P5_U0_CFG3 0x40010a43 +#define CYREG_B0_P5_U0_CFG4 0x40010a44 +#define CYREG_B0_P5_U0_CFG5 0x40010a45 +#define CYREG_B0_P5_U0_CFG6 0x40010a46 +#define CYREG_B0_P5_U0_CFG7 0x40010a47 +#define CYREG_B0_P5_U0_CFG8 0x40010a48 +#define CYREG_B0_P5_U0_CFG9 0x40010a49 +#define CYREG_B0_P5_U0_CFG10 0x40010a4a +#define CYREG_B0_P5_U0_CFG11 0x40010a4b +#define CYREG_B0_P5_U0_CFG12 0x40010a4c +#define CYREG_B0_P5_U0_CFG13 0x40010a4d +#define CYREG_B0_P5_U0_CFG14 0x40010a4e +#define CYREG_B0_P5_U0_CFG15 0x40010a4f +#define CYREG_B0_P5_U0_CFG16 0x40010a50 +#define CYREG_B0_P5_U0_CFG17 0x40010a51 +#define CYREG_B0_P5_U0_CFG18 0x40010a52 +#define CYREG_B0_P5_U0_CFG19 0x40010a53 +#define CYREG_B0_P5_U0_CFG20 0x40010a54 +#define CYREG_B0_P5_U0_CFG21 0x40010a55 +#define CYREG_B0_P5_U0_CFG22 0x40010a56 +#define CYREG_B0_P5_U0_CFG23 0x40010a57 +#define CYREG_B0_P5_U0_CFG24 0x40010a58 +#define CYREG_B0_P5_U0_CFG25 0x40010a59 +#define CYREG_B0_P5_U0_CFG26 0x40010a5a +#define CYREG_B0_P5_U0_CFG27 0x40010a5b +#define CYREG_B0_P5_U0_CFG28 0x40010a5c +#define CYREG_B0_P5_U0_CFG29 0x40010a5d +#define CYREG_B0_P5_U0_CFG30 0x40010a5e +#define CYREG_B0_P5_U0_CFG31 0x40010a5f +#define CYREG_B0_P5_U0_DCFG0 0x40010a60 +#define CYREG_B0_P5_U0_DCFG1 0x40010a62 +#define CYREG_B0_P5_U0_DCFG2 0x40010a64 +#define CYREG_B0_P5_U0_DCFG3 0x40010a66 +#define CYREG_B0_P5_U0_DCFG4 0x40010a68 +#define CYREG_B0_P5_U0_DCFG5 0x40010a6a +#define CYREG_B0_P5_U0_DCFG6 0x40010a6c +#define CYREG_B0_P5_U0_DCFG7 0x40010a6e +#define CYDEV_UCFG_B0_P5_U1_BASE 0x40010a80 +#define CYDEV_UCFG_B0_P5_U1_SIZE 0x00000070 +#define CYREG_B0_P5_U1_PLD_IT0 0x40010a80 +#define CYREG_B0_P5_U1_PLD_IT1 0x40010a84 +#define CYREG_B0_P5_U1_PLD_IT2 0x40010a88 +#define CYREG_B0_P5_U1_PLD_IT3 0x40010a8c +#define CYREG_B0_P5_U1_PLD_IT4 0x40010a90 +#define CYREG_B0_P5_U1_PLD_IT5 0x40010a94 +#define CYREG_B0_P5_U1_PLD_IT6 0x40010a98 +#define CYREG_B0_P5_U1_PLD_IT7 0x40010a9c +#define CYREG_B0_P5_U1_PLD_IT8 0x40010aa0 +#define CYREG_B0_P5_U1_PLD_IT9 0x40010aa4 +#define CYREG_B0_P5_U1_PLD_IT10 0x40010aa8 +#define CYREG_B0_P5_U1_PLD_IT11 0x40010aac +#define CYREG_B0_P5_U1_PLD_ORT0 0x40010ab0 +#define CYREG_B0_P5_U1_PLD_ORT1 0x40010ab2 +#define CYREG_B0_P5_U1_PLD_ORT2 0x40010ab4 +#define CYREG_B0_P5_U1_PLD_ORT3 0x40010ab6 +#define CYREG_B0_P5_U1_MC_CFG_CEN_CONST 0x40010ab8 +#define CYREG_B0_P5_U1_MC_CFG_XORFB 0x40010aba +#define CYREG_B0_P5_U1_MC_CFG_SET_RESET 0x40010abc +#define CYREG_B0_P5_U1_MC_CFG_BYPASS 0x40010abe +#define CYREG_B0_P5_U1_CFG0 0x40010ac0 +#define CYREG_B0_P5_U1_CFG1 0x40010ac1 +#define CYREG_B0_P5_U1_CFG2 0x40010ac2 +#define CYREG_B0_P5_U1_CFG3 0x40010ac3 +#define CYREG_B0_P5_U1_CFG4 0x40010ac4 +#define CYREG_B0_P5_U1_CFG5 0x40010ac5 +#define CYREG_B0_P5_U1_CFG6 0x40010ac6 +#define CYREG_B0_P5_U1_CFG7 0x40010ac7 +#define CYREG_B0_P5_U1_CFG8 0x40010ac8 +#define CYREG_B0_P5_U1_CFG9 0x40010ac9 +#define CYREG_B0_P5_U1_CFG10 0x40010aca +#define CYREG_B0_P5_U1_CFG11 0x40010acb +#define CYREG_B0_P5_U1_CFG12 0x40010acc +#define CYREG_B0_P5_U1_CFG13 0x40010acd +#define CYREG_B0_P5_U1_CFG14 0x40010ace +#define CYREG_B0_P5_U1_CFG15 0x40010acf +#define CYREG_B0_P5_U1_CFG16 0x40010ad0 +#define CYREG_B0_P5_U1_CFG17 0x40010ad1 +#define CYREG_B0_P5_U1_CFG18 0x40010ad2 +#define CYREG_B0_P5_U1_CFG19 0x40010ad3 +#define CYREG_B0_P5_U1_CFG20 0x40010ad4 +#define CYREG_B0_P5_U1_CFG21 0x40010ad5 +#define CYREG_B0_P5_U1_CFG22 0x40010ad6 +#define CYREG_B0_P5_U1_CFG23 0x40010ad7 +#define CYREG_B0_P5_U1_CFG24 0x40010ad8 +#define CYREG_B0_P5_U1_CFG25 0x40010ad9 +#define CYREG_B0_P5_U1_CFG26 0x40010ada +#define CYREG_B0_P5_U1_CFG27 0x40010adb +#define CYREG_B0_P5_U1_CFG28 0x40010adc +#define CYREG_B0_P5_U1_CFG29 0x40010add +#define CYREG_B0_P5_U1_CFG30 0x40010ade +#define CYREG_B0_P5_U1_CFG31 0x40010adf +#define CYREG_B0_P5_U1_DCFG0 0x40010ae0 +#define CYREG_B0_P5_U1_DCFG1 0x40010ae2 +#define CYREG_B0_P5_U1_DCFG2 0x40010ae4 +#define CYREG_B0_P5_U1_DCFG3 0x40010ae6 +#define CYREG_B0_P5_U1_DCFG4 0x40010ae8 +#define CYREG_B0_P5_U1_DCFG5 0x40010aea +#define CYREG_B0_P5_U1_DCFG6 0x40010aec +#define CYREG_B0_P5_U1_DCFG7 0x40010aee +#define CYDEV_UCFG_B0_P5_ROUTE_BASE 0x40010b00 +#define CYDEV_UCFG_B0_P5_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P6_BASE 0x40010c00 +#define CYDEV_UCFG_B0_P6_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P6_U0_BASE 0x40010c00 +#define CYDEV_UCFG_B0_P6_U0_SIZE 0x00000070 +#define CYREG_B0_P6_U0_PLD_IT0 0x40010c00 +#define CYREG_B0_P6_U0_PLD_IT1 0x40010c04 +#define CYREG_B0_P6_U0_PLD_IT2 0x40010c08 +#define CYREG_B0_P6_U0_PLD_IT3 0x40010c0c +#define CYREG_B0_P6_U0_PLD_IT4 0x40010c10 +#define CYREG_B0_P6_U0_PLD_IT5 0x40010c14 +#define CYREG_B0_P6_U0_PLD_IT6 0x40010c18 +#define CYREG_B0_P6_U0_PLD_IT7 0x40010c1c +#define CYREG_B0_P6_U0_PLD_IT8 0x40010c20 +#define CYREG_B0_P6_U0_PLD_IT9 0x40010c24 +#define CYREG_B0_P6_U0_PLD_IT10 0x40010c28 +#define CYREG_B0_P6_U0_PLD_IT11 0x40010c2c +#define CYREG_B0_P6_U0_PLD_ORT0 0x40010c30 +#define CYREG_B0_P6_U0_PLD_ORT1 0x40010c32 +#define CYREG_B0_P6_U0_PLD_ORT2 0x40010c34 +#define CYREG_B0_P6_U0_PLD_ORT3 0x40010c36 +#define CYREG_B0_P6_U0_MC_CFG_CEN_CONST 0x40010c38 +#define CYREG_B0_P6_U0_MC_CFG_XORFB 0x40010c3a +#define CYREG_B0_P6_U0_MC_CFG_SET_RESET 0x40010c3c +#define CYREG_B0_P6_U0_MC_CFG_BYPASS 0x40010c3e +#define CYREG_B0_P6_U0_CFG0 0x40010c40 +#define CYREG_B0_P6_U0_CFG1 0x40010c41 +#define CYREG_B0_P6_U0_CFG2 0x40010c42 +#define CYREG_B0_P6_U0_CFG3 0x40010c43 +#define CYREG_B0_P6_U0_CFG4 0x40010c44 +#define CYREG_B0_P6_U0_CFG5 0x40010c45 +#define CYREG_B0_P6_U0_CFG6 0x40010c46 +#define CYREG_B0_P6_U0_CFG7 0x40010c47 +#define CYREG_B0_P6_U0_CFG8 0x40010c48 +#define CYREG_B0_P6_U0_CFG9 0x40010c49 +#define CYREG_B0_P6_U0_CFG10 0x40010c4a +#define CYREG_B0_P6_U0_CFG11 0x40010c4b +#define CYREG_B0_P6_U0_CFG12 0x40010c4c +#define CYREG_B0_P6_U0_CFG13 0x40010c4d +#define CYREG_B0_P6_U0_CFG14 0x40010c4e +#define CYREG_B0_P6_U0_CFG15 0x40010c4f +#define CYREG_B0_P6_U0_CFG16 0x40010c50 +#define CYREG_B0_P6_U0_CFG17 0x40010c51 +#define CYREG_B0_P6_U0_CFG18 0x40010c52 +#define CYREG_B0_P6_U0_CFG19 0x40010c53 +#define CYREG_B0_P6_U0_CFG20 0x40010c54 +#define CYREG_B0_P6_U0_CFG21 0x40010c55 +#define CYREG_B0_P6_U0_CFG22 0x40010c56 +#define CYREG_B0_P6_U0_CFG23 0x40010c57 +#define CYREG_B0_P6_U0_CFG24 0x40010c58 +#define CYREG_B0_P6_U0_CFG25 0x40010c59 +#define CYREG_B0_P6_U0_CFG26 0x40010c5a +#define CYREG_B0_P6_U0_CFG27 0x40010c5b +#define CYREG_B0_P6_U0_CFG28 0x40010c5c +#define CYREG_B0_P6_U0_CFG29 0x40010c5d +#define CYREG_B0_P6_U0_CFG30 0x40010c5e +#define CYREG_B0_P6_U0_CFG31 0x40010c5f +#define CYREG_B0_P6_U0_DCFG0 0x40010c60 +#define CYREG_B0_P6_U0_DCFG1 0x40010c62 +#define CYREG_B0_P6_U0_DCFG2 0x40010c64 +#define CYREG_B0_P6_U0_DCFG3 0x40010c66 +#define CYREG_B0_P6_U0_DCFG4 0x40010c68 +#define CYREG_B0_P6_U0_DCFG5 0x40010c6a +#define CYREG_B0_P6_U0_DCFG6 0x40010c6c +#define CYREG_B0_P6_U0_DCFG7 0x40010c6e +#define CYDEV_UCFG_B0_P6_U1_BASE 0x40010c80 +#define CYDEV_UCFG_B0_P6_U1_SIZE 0x00000070 +#define CYREG_B0_P6_U1_PLD_IT0 0x40010c80 +#define CYREG_B0_P6_U1_PLD_IT1 0x40010c84 +#define CYREG_B0_P6_U1_PLD_IT2 0x40010c88 +#define CYREG_B0_P6_U1_PLD_IT3 0x40010c8c +#define CYREG_B0_P6_U1_PLD_IT4 0x40010c90 +#define CYREG_B0_P6_U1_PLD_IT5 0x40010c94 +#define CYREG_B0_P6_U1_PLD_IT6 0x40010c98 +#define CYREG_B0_P6_U1_PLD_IT7 0x40010c9c +#define CYREG_B0_P6_U1_PLD_IT8 0x40010ca0 +#define CYREG_B0_P6_U1_PLD_IT9 0x40010ca4 +#define CYREG_B0_P6_U1_PLD_IT10 0x40010ca8 +#define CYREG_B0_P6_U1_PLD_IT11 0x40010cac +#define CYREG_B0_P6_U1_PLD_ORT0 0x40010cb0 +#define CYREG_B0_P6_U1_PLD_ORT1 0x40010cb2 +#define CYREG_B0_P6_U1_PLD_ORT2 0x40010cb4 +#define CYREG_B0_P6_U1_PLD_ORT3 0x40010cb6 +#define CYREG_B0_P6_U1_MC_CFG_CEN_CONST 0x40010cb8 +#define CYREG_B0_P6_U1_MC_CFG_XORFB 0x40010cba +#define CYREG_B0_P6_U1_MC_CFG_SET_RESET 0x40010cbc +#define CYREG_B0_P6_U1_MC_CFG_BYPASS 0x40010cbe +#define CYREG_B0_P6_U1_CFG0 0x40010cc0 +#define CYREG_B0_P6_U1_CFG1 0x40010cc1 +#define CYREG_B0_P6_U1_CFG2 0x40010cc2 +#define CYREG_B0_P6_U1_CFG3 0x40010cc3 +#define CYREG_B0_P6_U1_CFG4 0x40010cc4 +#define CYREG_B0_P6_U1_CFG5 0x40010cc5 +#define CYREG_B0_P6_U1_CFG6 0x40010cc6 +#define CYREG_B0_P6_U1_CFG7 0x40010cc7 +#define CYREG_B0_P6_U1_CFG8 0x40010cc8 +#define CYREG_B0_P6_U1_CFG9 0x40010cc9 +#define CYREG_B0_P6_U1_CFG10 0x40010cca +#define CYREG_B0_P6_U1_CFG11 0x40010ccb +#define CYREG_B0_P6_U1_CFG12 0x40010ccc +#define CYREG_B0_P6_U1_CFG13 0x40010ccd +#define CYREG_B0_P6_U1_CFG14 0x40010cce +#define CYREG_B0_P6_U1_CFG15 0x40010ccf +#define CYREG_B0_P6_U1_CFG16 0x40010cd0 +#define CYREG_B0_P6_U1_CFG17 0x40010cd1 +#define CYREG_B0_P6_U1_CFG18 0x40010cd2 +#define CYREG_B0_P6_U1_CFG19 0x40010cd3 +#define CYREG_B0_P6_U1_CFG20 0x40010cd4 +#define CYREG_B0_P6_U1_CFG21 0x40010cd5 +#define CYREG_B0_P6_U1_CFG22 0x40010cd6 +#define CYREG_B0_P6_U1_CFG23 0x40010cd7 +#define CYREG_B0_P6_U1_CFG24 0x40010cd8 +#define CYREG_B0_P6_U1_CFG25 0x40010cd9 +#define CYREG_B0_P6_U1_CFG26 0x40010cda +#define CYREG_B0_P6_U1_CFG27 0x40010cdb +#define CYREG_B0_P6_U1_CFG28 0x40010cdc +#define CYREG_B0_P6_U1_CFG29 0x40010cdd +#define CYREG_B0_P6_U1_CFG30 0x40010cde +#define CYREG_B0_P6_U1_CFG31 0x40010cdf +#define CYREG_B0_P6_U1_DCFG0 0x40010ce0 +#define CYREG_B0_P6_U1_DCFG1 0x40010ce2 +#define CYREG_B0_P6_U1_DCFG2 0x40010ce4 +#define CYREG_B0_P6_U1_DCFG3 0x40010ce6 +#define CYREG_B0_P6_U1_DCFG4 0x40010ce8 +#define CYREG_B0_P6_U1_DCFG5 0x40010cea +#define CYREG_B0_P6_U1_DCFG6 0x40010cec +#define CYREG_B0_P6_U1_DCFG7 0x40010cee +#define CYDEV_UCFG_B0_P6_ROUTE_BASE 0x40010d00 +#define CYDEV_UCFG_B0_P6_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P7_BASE 0x40010e00 +#define CYDEV_UCFG_B0_P7_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P7_U0_BASE 0x40010e00 +#define CYDEV_UCFG_B0_P7_U0_SIZE 0x00000070 +#define CYREG_B0_P7_U0_PLD_IT0 0x40010e00 +#define CYREG_B0_P7_U0_PLD_IT1 0x40010e04 +#define CYREG_B0_P7_U0_PLD_IT2 0x40010e08 +#define CYREG_B0_P7_U0_PLD_IT3 0x40010e0c +#define CYREG_B0_P7_U0_PLD_IT4 0x40010e10 +#define CYREG_B0_P7_U0_PLD_IT5 0x40010e14 +#define CYREG_B0_P7_U0_PLD_IT6 0x40010e18 +#define CYREG_B0_P7_U0_PLD_IT7 0x40010e1c +#define CYREG_B0_P7_U0_PLD_IT8 0x40010e20 +#define CYREG_B0_P7_U0_PLD_IT9 0x40010e24 +#define CYREG_B0_P7_U0_PLD_IT10 0x40010e28 +#define CYREG_B0_P7_U0_PLD_IT11 0x40010e2c +#define CYREG_B0_P7_U0_PLD_ORT0 0x40010e30 +#define CYREG_B0_P7_U0_PLD_ORT1 0x40010e32 +#define CYREG_B0_P7_U0_PLD_ORT2 0x40010e34 +#define CYREG_B0_P7_U0_PLD_ORT3 0x40010e36 +#define CYREG_B0_P7_U0_MC_CFG_CEN_CONST 0x40010e38 +#define CYREG_B0_P7_U0_MC_CFG_XORFB 0x40010e3a +#define CYREG_B0_P7_U0_MC_CFG_SET_RESET 0x40010e3c +#define CYREG_B0_P7_U0_MC_CFG_BYPASS 0x40010e3e +#define CYREG_B0_P7_U0_CFG0 0x40010e40 +#define CYREG_B0_P7_U0_CFG1 0x40010e41 +#define CYREG_B0_P7_U0_CFG2 0x40010e42 +#define CYREG_B0_P7_U0_CFG3 0x40010e43 +#define CYREG_B0_P7_U0_CFG4 0x40010e44 +#define CYREG_B0_P7_U0_CFG5 0x40010e45 +#define CYREG_B0_P7_U0_CFG6 0x40010e46 +#define CYREG_B0_P7_U0_CFG7 0x40010e47 +#define CYREG_B0_P7_U0_CFG8 0x40010e48 +#define CYREG_B0_P7_U0_CFG9 0x40010e49 +#define CYREG_B0_P7_U0_CFG10 0x40010e4a +#define CYREG_B0_P7_U0_CFG11 0x40010e4b +#define CYREG_B0_P7_U0_CFG12 0x40010e4c +#define CYREG_B0_P7_U0_CFG13 0x40010e4d +#define CYREG_B0_P7_U0_CFG14 0x40010e4e +#define CYREG_B0_P7_U0_CFG15 0x40010e4f +#define CYREG_B0_P7_U0_CFG16 0x40010e50 +#define CYREG_B0_P7_U0_CFG17 0x40010e51 +#define CYREG_B0_P7_U0_CFG18 0x40010e52 +#define CYREG_B0_P7_U0_CFG19 0x40010e53 +#define CYREG_B0_P7_U0_CFG20 0x40010e54 +#define CYREG_B0_P7_U0_CFG21 0x40010e55 +#define CYREG_B0_P7_U0_CFG22 0x40010e56 +#define CYREG_B0_P7_U0_CFG23 0x40010e57 +#define CYREG_B0_P7_U0_CFG24 0x40010e58 +#define CYREG_B0_P7_U0_CFG25 0x40010e59 +#define CYREG_B0_P7_U0_CFG26 0x40010e5a +#define CYREG_B0_P7_U0_CFG27 0x40010e5b +#define CYREG_B0_P7_U0_CFG28 0x40010e5c +#define CYREG_B0_P7_U0_CFG29 0x40010e5d +#define CYREG_B0_P7_U0_CFG30 0x40010e5e +#define CYREG_B0_P7_U0_CFG31 0x40010e5f +#define CYREG_B0_P7_U0_DCFG0 0x40010e60 +#define CYREG_B0_P7_U0_DCFG1 0x40010e62 +#define CYREG_B0_P7_U0_DCFG2 0x40010e64 +#define CYREG_B0_P7_U0_DCFG3 0x40010e66 +#define CYREG_B0_P7_U0_DCFG4 0x40010e68 +#define CYREG_B0_P7_U0_DCFG5 0x40010e6a +#define CYREG_B0_P7_U0_DCFG6 0x40010e6c +#define CYREG_B0_P7_U0_DCFG7 0x40010e6e +#define CYDEV_UCFG_B0_P7_U1_BASE 0x40010e80 +#define CYDEV_UCFG_B0_P7_U1_SIZE 0x00000070 +#define CYREG_B0_P7_U1_PLD_IT0 0x40010e80 +#define CYREG_B0_P7_U1_PLD_IT1 0x40010e84 +#define CYREG_B0_P7_U1_PLD_IT2 0x40010e88 +#define CYREG_B0_P7_U1_PLD_IT3 0x40010e8c +#define CYREG_B0_P7_U1_PLD_IT4 0x40010e90 +#define CYREG_B0_P7_U1_PLD_IT5 0x40010e94 +#define CYREG_B0_P7_U1_PLD_IT6 0x40010e98 +#define CYREG_B0_P7_U1_PLD_IT7 0x40010e9c +#define CYREG_B0_P7_U1_PLD_IT8 0x40010ea0 +#define CYREG_B0_P7_U1_PLD_IT9 0x40010ea4 +#define CYREG_B0_P7_U1_PLD_IT10 0x40010ea8 +#define CYREG_B0_P7_U1_PLD_IT11 0x40010eac +#define CYREG_B0_P7_U1_PLD_ORT0 0x40010eb0 +#define CYREG_B0_P7_U1_PLD_ORT1 0x40010eb2 +#define CYREG_B0_P7_U1_PLD_ORT2 0x40010eb4 +#define CYREG_B0_P7_U1_PLD_ORT3 0x40010eb6 +#define CYREG_B0_P7_U1_MC_CFG_CEN_CONST 0x40010eb8 +#define CYREG_B0_P7_U1_MC_CFG_XORFB 0x40010eba +#define CYREG_B0_P7_U1_MC_CFG_SET_RESET 0x40010ebc +#define CYREG_B0_P7_U1_MC_CFG_BYPASS 0x40010ebe +#define CYREG_B0_P7_U1_CFG0 0x40010ec0 +#define CYREG_B0_P7_U1_CFG1 0x40010ec1 +#define CYREG_B0_P7_U1_CFG2 0x40010ec2 +#define CYREG_B0_P7_U1_CFG3 0x40010ec3 +#define CYREG_B0_P7_U1_CFG4 0x40010ec4 +#define CYREG_B0_P7_U1_CFG5 0x40010ec5 +#define CYREG_B0_P7_U1_CFG6 0x40010ec6 +#define CYREG_B0_P7_U1_CFG7 0x40010ec7 +#define CYREG_B0_P7_U1_CFG8 0x40010ec8 +#define CYREG_B0_P7_U1_CFG9 0x40010ec9 +#define CYREG_B0_P7_U1_CFG10 0x40010eca +#define CYREG_B0_P7_U1_CFG11 0x40010ecb +#define CYREG_B0_P7_U1_CFG12 0x40010ecc +#define CYREG_B0_P7_U1_CFG13 0x40010ecd +#define CYREG_B0_P7_U1_CFG14 0x40010ece +#define CYREG_B0_P7_U1_CFG15 0x40010ecf +#define CYREG_B0_P7_U1_CFG16 0x40010ed0 +#define CYREG_B0_P7_U1_CFG17 0x40010ed1 +#define CYREG_B0_P7_U1_CFG18 0x40010ed2 +#define CYREG_B0_P7_U1_CFG19 0x40010ed3 +#define CYREG_B0_P7_U1_CFG20 0x40010ed4 +#define CYREG_B0_P7_U1_CFG21 0x40010ed5 +#define CYREG_B0_P7_U1_CFG22 0x40010ed6 +#define CYREG_B0_P7_U1_CFG23 0x40010ed7 +#define CYREG_B0_P7_U1_CFG24 0x40010ed8 +#define CYREG_B0_P7_U1_CFG25 0x40010ed9 +#define CYREG_B0_P7_U1_CFG26 0x40010eda +#define CYREG_B0_P7_U1_CFG27 0x40010edb +#define CYREG_B0_P7_U1_CFG28 0x40010edc +#define CYREG_B0_P7_U1_CFG29 0x40010edd +#define CYREG_B0_P7_U1_CFG30 0x40010ede +#define CYREG_B0_P7_U1_CFG31 0x40010edf +#define CYREG_B0_P7_U1_DCFG0 0x40010ee0 +#define CYREG_B0_P7_U1_DCFG1 0x40010ee2 +#define CYREG_B0_P7_U1_DCFG2 0x40010ee4 +#define CYREG_B0_P7_U1_DCFG3 0x40010ee6 +#define CYREG_B0_P7_U1_DCFG4 0x40010ee8 +#define CYREG_B0_P7_U1_DCFG5 0x40010eea +#define CYREG_B0_P7_U1_DCFG6 0x40010eec +#define CYREG_B0_P7_U1_DCFG7 0x40010eee +#define CYDEV_UCFG_B0_P7_ROUTE_BASE 0x40010f00 +#define CYDEV_UCFG_B0_P7_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B1_BASE 0x40011000 +#define CYDEV_UCFG_B1_SIZE 0x00000fef +#define CYDEV_UCFG_B1_P2_BASE 0x40011400 +#define CYDEV_UCFG_B1_P2_SIZE 0x000001ef +#define CYDEV_UCFG_B1_P2_U0_BASE 0x40011400 +#define CYDEV_UCFG_B1_P2_U0_SIZE 0x00000070 +#define CYREG_B1_P2_U0_PLD_IT0 0x40011400 +#define CYREG_B1_P2_U0_PLD_IT1 0x40011404 +#define CYREG_B1_P2_U0_PLD_IT2 0x40011408 +#define CYREG_B1_P2_U0_PLD_IT3 0x4001140c +#define CYREG_B1_P2_U0_PLD_IT4 0x40011410 +#define CYREG_B1_P2_U0_PLD_IT5 0x40011414 +#define CYREG_B1_P2_U0_PLD_IT6 0x40011418 +#define CYREG_B1_P2_U0_PLD_IT7 0x4001141c +#define CYREG_B1_P2_U0_PLD_IT8 0x40011420 +#define CYREG_B1_P2_U0_PLD_IT9 0x40011424 +#define CYREG_B1_P2_U0_PLD_IT10 0x40011428 +#define CYREG_B1_P2_U0_PLD_IT11 0x4001142c +#define CYREG_B1_P2_U0_PLD_ORT0 0x40011430 +#define CYREG_B1_P2_U0_PLD_ORT1 0x40011432 +#define CYREG_B1_P2_U0_PLD_ORT2 0x40011434 +#define CYREG_B1_P2_U0_PLD_ORT3 0x40011436 +#define CYREG_B1_P2_U0_MC_CFG_CEN_CONST 0x40011438 +#define CYREG_B1_P2_U0_MC_CFG_XORFB 0x4001143a +#define CYREG_B1_P2_U0_MC_CFG_SET_RESET 0x4001143c +#define CYREG_B1_P2_U0_MC_CFG_BYPASS 0x4001143e +#define CYREG_B1_P2_U0_CFG0 0x40011440 +#define CYREG_B1_P2_U0_CFG1 0x40011441 +#define CYREG_B1_P2_U0_CFG2 0x40011442 +#define CYREG_B1_P2_U0_CFG3 0x40011443 +#define CYREG_B1_P2_U0_CFG4 0x40011444 +#define CYREG_B1_P2_U0_CFG5 0x40011445 +#define CYREG_B1_P2_U0_CFG6 0x40011446 +#define CYREG_B1_P2_U0_CFG7 0x40011447 +#define CYREG_B1_P2_U0_CFG8 0x40011448 +#define CYREG_B1_P2_U0_CFG9 0x40011449 +#define CYREG_B1_P2_U0_CFG10 0x4001144a +#define CYREG_B1_P2_U0_CFG11 0x4001144b +#define CYREG_B1_P2_U0_CFG12 0x4001144c +#define CYREG_B1_P2_U0_CFG13 0x4001144d +#define CYREG_B1_P2_U0_CFG14 0x4001144e +#define CYREG_B1_P2_U0_CFG15 0x4001144f +#define CYREG_B1_P2_U0_CFG16 0x40011450 +#define CYREG_B1_P2_U0_CFG17 0x40011451 +#define CYREG_B1_P2_U0_CFG18 0x40011452 +#define CYREG_B1_P2_U0_CFG19 0x40011453 +#define CYREG_B1_P2_U0_CFG20 0x40011454 +#define CYREG_B1_P2_U0_CFG21 0x40011455 +#define CYREG_B1_P2_U0_CFG22 0x40011456 +#define CYREG_B1_P2_U0_CFG23 0x40011457 +#define CYREG_B1_P2_U0_CFG24 0x40011458 +#define CYREG_B1_P2_U0_CFG25 0x40011459 +#define CYREG_B1_P2_U0_CFG26 0x4001145a +#define CYREG_B1_P2_U0_CFG27 0x4001145b +#define CYREG_B1_P2_U0_CFG28 0x4001145c +#define CYREG_B1_P2_U0_CFG29 0x4001145d +#define CYREG_B1_P2_U0_CFG30 0x4001145e +#define CYREG_B1_P2_U0_CFG31 0x4001145f +#define CYREG_B1_P2_U0_DCFG0 0x40011460 +#define CYREG_B1_P2_U0_DCFG1 0x40011462 +#define CYREG_B1_P2_U0_DCFG2 0x40011464 +#define CYREG_B1_P2_U0_DCFG3 0x40011466 +#define CYREG_B1_P2_U0_DCFG4 0x40011468 +#define CYREG_B1_P2_U0_DCFG5 0x4001146a +#define CYREG_B1_P2_U0_DCFG6 0x4001146c +#define CYREG_B1_P2_U0_DCFG7 0x4001146e +#define CYDEV_UCFG_B1_P2_U1_BASE 0x40011480 +#define CYDEV_UCFG_B1_P2_U1_SIZE 0x00000070 +#define CYREG_B1_P2_U1_PLD_IT0 0x40011480 +#define CYREG_B1_P2_U1_PLD_IT1 0x40011484 +#define CYREG_B1_P2_U1_PLD_IT2 0x40011488 +#define CYREG_B1_P2_U1_PLD_IT3 0x4001148c +#define CYREG_B1_P2_U1_PLD_IT4 0x40011490 +#define CYREG_B1_P2_U1_PLD_IT5 0x40011494 +#define CYREG_B1_P2_U1_PLD_IT6 0x40011498 +#define CYREG_B1_P2_U1_PLD_IT7 0x4001149c +#define CYREG_B1_P2_U1_PLD_IT8 0x400114a0 +#define CYREG_B1_P2_U1_PLD_IT9 0x400114a4 +#define CYREG_B1_P2_U1_PLD_IT10 0x400114a8 +#define CYREG_B1_P2_U1_PLD_IT11 0x400114ac +#define CYREG_B1_P2_U1_PLD_ORT0 0x400114b0 +#define CYREG_B1_P2_U1_PLD_ORT1 0x400114b2 +#define CYREG_B1_P2_U1_PLD_ORT2 0x400114b4 +#define CYREG_B1_P2_U1_PLD_ORT3 0x400114b6 +#define CYREG_B1_P2_U1_MC_CFG_CEN_CONST 0x400114b8 +#define CYREG_B1_P2_U1_MC_CFG_XORFB 0x400114ba +#define CYREG_B1_P2_U1_MC_CFG_SET_RESET 0x400114bc +#define CYREG_B1_P2_U1_MC_CFG_BYPASS 0x400114be +#define CYREG_B1_P2_U1_CFG0 0x400114c0 +#define CYREG_B1_P2_U1_CFG1 0x400114c1 +#define CYREG_B1_P2_U1_CFG2 0x400114c2 +#define CYREG_B1_P2_U1_CFG3 0x400114c3 +#define CYREG_B1_P2_U1_CFG4 0x400114c4 +#define CYREG_B1_P2_U1_CFG5 0x400114c5 +#define CYREG_B1_P2_U1_CFG6 0x400114c6 +#define CYREG_B1_P2_U1_CFG7 0x400114c7 +#define CYREG_B1_P2_U1_CFG8 0x400114c8 +#define CYREG_B1_P2_U1_CFG9 0x400114c9 +#define CYREG_B1_P2_U1_CFG10 0x400114ca +#define CYREG_B1_P2_U1_CFG11 0x400114cb +#define CYREG_B1_P2_U1_CFG12 0x400114cc +#define CYREG_B1_P2_U1_CFG13 0x400114cd +#define CYREG_B1_P2_U1_CFG14 0x400114ce +#define CYREG_B1_P2_U1_CFG15 0x400114cf +#define CYREG_B1_P2_U1_CFG16 0x400114d0 +#define CYREG_B1_P2_U1_CFG17 0x400114d1 +#define CYREG_B1_P2_U1_CFG18 0x400114d2 +#define CYREG_B1_P2_U1_CFG19 0x400114d3 +#define CYREG_B1_P2_U1_CFG20 0x400114d4 +#define CYREG_B1_P2_U1_CFG21 0x400114d5 +#define CYREG_B1_P2_U1_CFG22 0x400114d6 +#define CYREG_B1_P2_U1_CFG23 0x400114d7 +#define CYREG_B1_P2_U1_CFG24 0x400114d8 +#define CYREG_B1_P2_U1_CFG25 0x400114d9 +#define CYREG_B1_P2_U1_CFG26 0x400114da +#define CYREG_B1_P2_U1_CFG27 0x400114db +#define CYREG_B1_P2_U1_CFG28 0x400114dc +#define CYREG_B1_P2_U1_CFG29 0x400114dd +#define CYREG_B1_P2_U1_CFG30 0x400114de +#define CYREG_B1_P2_U1_CFG31 0x400114df +#define CYREG_B1_P2_U1_DCFG0 0x400114e0 +#define CYREG_B1_P2_U1_DCFG1 0x400114e2 +#define CYREG_B1_P2_U1_DCFG2 0x400114e4 +#define CYREG_B1_P2_U1_DCFG3 0x400114e6 +#define CYREG_B1_P2_U1_DCFG4 0x400114e8 +#define CYREG_B1_P2_U1_DCFG5 0x400114ea +#define CYREG_B1_P2_U1_DCFG6 0x400114ec +#define CYREG_B1_P2_U1_DCFG7 0x400114ee +#define CYDEV_UCFG_B1_P2_ROUTE_BASE 0x40011500 +#define CYDEV_UCFG_B1_P2_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B1_P3_BASE 0x40011600 +#define CYDEV_UCFG_B1_P3_SIZE 0x000001ef +#define CYDEV_UCFG_B1_P3_U0_BASE 0x40011600 +#define CYDEV_UCFG_B1_P3_U0_SIZE 0x00000070 +#define CYREG_B1_P3_U0_PLD_IT0 0x40011600 +#define CYREG_B1_P3_U0_PLD_IT1 0x40011604 +#define CYREG_B1_P3_U0_PLD_IT2 0x40011608 +#define CYREG_B1_P3_U0_PLD_IT3 0x4001160c +#define CYREG_B1_P3_U0_PLD_IT4 0x40011610 +#define CYREG_B1_P3_U0_PLD_IT5 0x40011614 +#define CYREG_B1_P3_U0_PLD_IT6 0x40011618 +#define CYREG_B1_P3_U0_PLD_IT7 0x4001161c +#define CYREG_B1_P3_U0_PLD_IT8 0x40011620 +#define CYREG_B1_P3_U0_PLD_IT9 0x40011624 +#define CYREG_B1_P3_U0_PLD_IT10 0x40011628 +#define CYREG_B1_P3_U0_PLD_IT11 0x4001162c +#define CYREG_B1_P3_U0_PLD_ORT0 0x40011630 +#define CYREG_B1_P3_U0_PLD_ORT1 0x40011632 +#define CYREG_B1_P3_U0_PLD_ORT2 0x40011634 +#define CYREG_B1_P3_U0_PLD_ORT3 0x40011636 +#define CYREG_B1_P3_U0_MC_CFG_CEN_CONST 0x40011638 +#define CYREG_B1_P3_U0_MC_CFG_XORFB 0x4001163a +#define CYREG_B1_P3_U0_MC_CFG_SET_RESET 0x4001163c +#define CYREG_B1_P3_U0_MC_CFG_BYPASS 0x4001163e +#define CYREG_B1_P3_U0_CFG0 0x40011640 +#define CYREG_B1_P3_U0_CFG1 0x40011641 +#define CYREG_B1_P3_U0_CFG2 0x40011642 +#define CYREG_B1_P3_U0_CFG3 0x40011643 +#define CYREG_B1_P3_U0_CFG4 0x40011644 +#define CYREG_B1_P3_U0_CFG5 0x40011645 +#define CYREG_B1_P3_U0_CFG6 0x40011646 +#define CYREG_B1_P3_U0_CFG7 0x40011647 +#define CYREG_B1_P3_U0_CFG8 0x40011648 +#define CYREG_B1_P3_U0_CFG9 0x40011649 +#define CYREG_B1_P3_U0_CFG10 0x4001164a +#define CYREG_B1_P3_U0_CFG11 0x4001164b +#define CYREG_B1_P3_U0_CFG12 0x4001164c +#define CYREG_B1_P3_U0_CFG13 0x4001164d +#define CYREG_B1_P3_U0_CFG14 0x4001164e +#define CYREG_B1_P3_U0_CFG15 0x4001164f +#define CYREG_B1_P3_U0_CFG16 0x40011650 +#define CYREG_B1_P3_U0_CFG17 0x40011651 +#define CYREG_B1_P3_U0_CFG18 0x40011652 +#define CYREG_B1_P3_U0_CFG19 0x40011653 +#define CYREG_B1_P3_U0_CFG20 0x40011654 +#define CYREG_B1_P3_U0_CFG21 0x40011655 +#define CYREG_B1_P3_U0_CFG22 0x40011656 +#define CYREG_B1_P3_U0_CFG23 0x40011657 +#define CYREG_B1_P3_U0_CFG24 0x40011658 +#define CYREG_B1_P3_U0_CFG25 0x40011659 +#define CYREG_B1_P3_U0_CFG26 0x4001165a +#define CYREG_B1_P3_U0_CFG27 0x4001165b +#define CYREG_B1_P3_U0_CFG28 0x4001165c +#define CYREG_B1_P3_U0_CFG29 0x4001165d +#define CYREG_B1_P3_U0_CFG30 0x4001165e +#define CYREG_B1_P3_U0_CFG31 0x4001165f +#define CYREG_B1_P3_U0_DCFG0 0x40011660 +#define CYREG_B1_P3_U0_DCFG1 0x40011662 +#define CYREG_B1_P3_U0_DCFG2 0x40011664 +#define CYREG_B1_P3_U0_DCFG3 0x40011666 +#define CYREG_B1_P3_U0_DCFG4 0x40011668 +#define CYREG_B1_P3_U0_DCFG5 0x4001166a +#define CYREG_B1_P3_U0_DCFG6 0x4001166c +#define CYREG_B1_P3_U0_DCFG7 0x4001166e +#define CYDEV_UCFG_B1_P3_U1_BASE 0x40011680 +#define CYDEV_UCFG_B1_P3_U1_SIZE 0x00000070 +#define CYREG_B1_P3_U1_PLD_IT0 0x40011680 +#define CYREG_B1_P3_U1_PLD_IT1 0x40011684 +#define CYREG_B1_P3_U1_PLD_IT2 0x40011688 +#define CYREG_B1_P3_U1_PLD_IT3 0x4001168c +#define CYREG_B1_P3_U1_PLD_IT4 0x40011690 +#define CYREG_B1_P3_U1_PLD_IT5 0x40011694 +#define CYREG_B1_P3_U1_PLD_IT6 0x40011698 +#define CYREG_B1_P3_U1_PLD_IT7 0x4001169c +#define CYREG_B1_P3_U1_PLD_IT8 0x400116a0 +#define CYREG_B1_P3_U1_PLD_IT9 0x400116a4 +#define CYREG_B1_P3_U1_PLD_IT10 0x400116a8 +#define CYREG_B1_P3_U1_PLD_IT11 0x400116ac +#define CYREG_B1_P3_U1_PLD_ORT0 0x400116b0 +#define CYREG_B1_P3_U1_PLD_ORT1 0x400116b2 +#define CYREG_B1_P3_U1_PLD_ORT2 0x400116b4 +#define CYREG_B1_P3_U1_PLD_ORT3 0x400116b6 +#define CYREG_B1_P3_U1_MC_CFG_CEN_CONST 0x400116b8 +#define CYREG_B1_P3_U1_MC_CFG_XORFB 0x400116ba +#define CYREG_B1_P3_U1_MC_CFG_SET_RESET 0x400116bc +#define CYREG_B1_P3_U1_MC_CFG_BYPASS 0x400116be +#define CYREG_B1_P3_U1_CFG0 0x400116c0 +#define CYREG_B1_P3_U1_CFG1 0x400116c1 +#define CYREG_B1_P3_U1_CFG2 0x400116c2 +#define CYREG_B1_P3_U1_CFG3 0x400116c3 +#define CYREG_B1_P3_U1_CFG4 0x400116c4 +#define CYREG_B1_P3_U1_CFG5 0x400116c5 +#define CYREG_B1_P3_U1_CFG6 0x400116c6 +#define CYREG_B1_P3_U1_CFG7 0x400116c7 +#define CYREG_B1_P3_U1_CFG8 0x400116c8 +#define CYREG_B1_P3_U1_CFG9 0x400116c9 +#define CYREG_B1_P3_U1_CFG10 0x400116ca +#define CYREG_B1_P3_U1_CFG11 0x400116cb +#define CYREG_B1_P3_U1_CFG12 0x400116cc +#define CYREG_B1_P3_U1_CFG13 0x400116cd +#define CYREG_B1_P3_U1_CFG14 0x400116ce +#define CYREG_B1_P3_U1_CFG15 0x400116cf +#define CYREG_B1_P3_U1_CFG16 0x400116d0 +#define CYREG_B1_P3_U1_CFG17 0x400116d1 +#define CYREG_B1_P3_U1_CFG18 0x400116d2 +#define CYREG_B1_P3_U1_CFG19 0x400116d3 +#define CYREG_B1_P3_U1_CFG20 0x400116d4 +#define CYREG_B1_P3_U1_CFG21 0x400116d5 +#define CYREG_B1_P3_U1_CFG22 0x400116d6 +#define CYREG_B1_P3_U1_CFG23 0x400116d7 +#define CYREG_B1_P3_U1_CFG24 0x400116d8 +#define CYREG_B1_P3_U1_CFG25 0x400116d9 +#define CYREG_B1_P3_U1_CFG26 0x400116da +#define CYREG_B1_P3_U1_CFG27 0x400116db +#define CYREG_B1_P3_U1_CFG28 0x400116dc +#define CYREG_B1_P3_U1_CFG29 0x400116dd +#define CYREG_B1_P3_U1_CFG30 0x400116de +#define CYREG_B1_P3_U1_CFG31 0x400116df +#define CYREG_B1_P3_U1_DCFG0 0x400116e0 +#define CYREG_B1_P3_U1_DCFG1 0x400116e2 +#define CYREG_B1_P3_U1_DCFG2 0x400116e4 +#define CYREG_B1_P3_U1_DCFG3 0x400116e6 +#define CYREG_B1_P3_U1_DCFG4 0x400116e8 +#define CYREG_B1_P3_U1_DCFG5 0x400116ea +#define CYREG_B1_P3_U1_DCFG6 0x400116ec +#define CYREG_B1_P3_U1_DCFG7 0x400116ee +#define CYDEV_UCFG_B1_P3_ROUTE_BASE 0x40011700 +#define CYDEV_UCFG_B1_P3_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B1_P4_BASE 0x40011800 +#define CYDEV_UCFG_B1_P4_SIZE 0x000001ef +#define CYDEV_UCFG_B1_P4_U0_BASE 0x40011800 +#define CYDEV_UCFG_B1_P4_U0_SIZE 0x00000070 +#define CYREG_B1_P4_U0_PLD_IT0 0x40011800 +#define CYREG_B1_P4_U0_PLD_IT1 0x40011804 +#define CYREG_B1_P4_U0_PLD_IT2 0x40011808 +#define CYREG_B1_P4_U0_PLD_IT3 0x4001180c +#define CYREG_B1_P4_U0_PLD_IT4 0x40011810 +#define CYREG_B1_P4_U0_PLD_IT5 0x40011814 +#define CYREG_B1_P4_U0_PLD_IT6 0x40011818 +#define CYREG_B1_P4_U0_PLD_IT7 0x4001181c +#define CYREG_B1_P4_U0_PLD_IT8 0x40011820 +#define CYREG_B1_P4_U0_PLD_IT9 0x40011824 +#define CYREG_B1_P4_U0_PLD_IT10 0x40011828 +#define CYREG_B1_P4_U0_PLD_IT11 0x4001182c +#define CYREG_B1_P4_U0_PLD_ORT0 0x40011830 +#define CYREG_B1_P4_U0_PLD_ORT1 0x40011832 +#define CYREG_B1_P4_U0_PLD_ORT2 0x40011834 +#define CYREG_B1_P4_U0_PLD_ORT3 0x40011836 +#define CYREG_B1_P4_U0_MC_CFG_CEN_CONST 0x40011838 +#define CYREG_B1_P4_U0_MC_CFG_XORFB 0x4001183a +#define CYREG_B1_P4_U0_MC_CFG_SET_RESET 0x4001183c +#define CYREG_B1_P4_U0_MC_CFG_BYPASS 0x4001183e +#define CYREG_B1_P4_U0_CFG0 0x40011840 +#define CYREG_B1_P4_U0_CFG1 0x40011841 +#define CYREG_B1_P4_U0_CFG2 0x40011842 +#define CYREG_B1_P4_U0_CFG3 0x40011843 +#define CYREG_B1_P4_U0_CFG4 0x40011844 +#define CYREG_B1_P4_U0_CFG5 0x40011845 +#define CYREG_B1_P4_U0_CFG6 0x40011846 +#define CYREG_B1_P4_U0_CFG7 0x40011847 +#define CYREG_B1_P4_U0_CFG8 0x40011848 +#define CYREG_B1_P4_U0_CFG9 0x40011849 +#define CYREG_B1_P4_U0_CFG10 0x4001184a +#define CYREG_B1_P4_U0_CFG11 0x4001184b +#define CYREG_B1_P4_U0_CFG12 0x4001184c +#define CYREG_B1_P4_U0_CFG13 0x4001184d +#define CYREG_B1_P4_U0_CFG14 0x4001184e +#define CYREG_B1_P4_U0_CFG15 0x4001184f +#define CYREG_B1_P4_U0_CFG16 0x40011850 +#define CYREG_B1_P4_U0_CFG17 0x40011851 +#define CYREG_B1_P4_U0_CFG18 0x40011852 +#define CYREG_B1_P4_U0_CFG19 0x40011853 +#define CYREG_B1_P4_U0_CFG20 0x40011854 +#define CYREG_B1_P4_U0_CFG21 0x40011855 +#define CYREG_B1_P4_U0_CFG22 0x40011856 +#define CYREG_B1_P4_U0_CFG23 0x40011857 +#define CYREG_B1_P4_U0_CFG24 0x40011858 +#define CYREG_B1_P4_U0_CFG25 0x40011859 +#define CYREG_B1_P4_U0_CFG26 0x4001185a +#define CYREG_B1_P4_U0_CFG27 0x4001185b +#define CYREG_B1_P4_U0_CFG28 0x4001185c +#define CYREG_B1_P4_U0_CFG29 0x4001185d +#define CYREG_B1_P4_U0_CFG30 0x4001185e +#define CYREG_B1_P4_U0_CFG31 0x4001185f +#define CYREG_B1_P4_U0_DCFG0 0x40011860 +#define CYREG_B1_P4_U0_DCFG1 0x40011862 +#define CYREG_B1_P4_U0_DCFG2 0x40011864 +#define CYREG_B1_P4_U0_DCFG3 0x40011866 +#define CYREG_B1_P4_U0_DCFG4 0x40011868 +#define CYREG_B1_P4_U0_DCFG5 0x4001186a +#define CYREG_B1_P4_U0_DCFG6 0x4001186c +#define CYREG_B1_P4_U0_DCFG7 0x4001186e +#define CYDEV_UCFG_B1_P4_U1_BASE 0x40011880 +#define CYDEV_UCFG_B1_P4_U1_SIZE 0x00000070 +#define CYREG_B1_P4_U1_PLD_IT0 0x40011880 +#define CYREG_B1_P4_U1_PLD_IT1 0x40011884 +#define CYREG_B1_P4_U1_PLD_IT2 0x40011888 +#define CYREG_B1_P4_U1_PLD_IT3 0x4001188c +#define CYREG_B1_P4_U1_PLD_IT4 0x40011890 +#define CYREG_B1_P4_U1_PLD_IT5 0x40011894 +#define CYREG_B1_P4_U1_PLD_IT6 0x40011898 +#define CYREG_B1_P4_U1_PLD_IT7 0x4001189c +#define CYREG_B1_P4_U1_PLD_IT8 0x400118a0 +#define CYREG_B1_P4_U1_PLD_IT9 0x400118a4 +#define CYREG_B1_P4_U1_PLD_IT10 0x400118a8 +#define CYREG_B1_P4_U1_PLD_IT11 0x400118ac +#define CYREG_B1_P4_U1_PLD_ORT0 0x400118b0 +#define CYREG_B1_P4_U1_PLD_ORT1 0x400118b2 +#define CYREG_B1_P4_U1_PLD_ORT2 0x400118b4 +#define CYREG_B1_P4_U1_PLD_ORT3 0x400118b6 +#define CYREG_B1_P4_U1_MC_CFG_CEN_CONST 0x400118b8 +#define CYREG_B1_P4_U1_MC_CFG_XORFB 0x400118ba +#define CYREG_B1_P4_U1_MC_CFG_SET_RESET 0x400118bc +#define CYREG_B1_P4_U1_MC_CFG_BYPASS 0x400118be +#define CYREG_B1_P4_U1_CFG0 0x400118c0 +#define CYREG_B1_P4_U1_CFG1 0x400118c1 +#define CYREG_B1_P4_U1_CFG2 0x400118c2 +#define CYREG_B1_P4_U1_CFG3 0x400118c3 +#define CYREG_B1_P4_U1_CFG4 0x400118c4 +#define CYREG_B1_P4_U1_CFG5 0x400118c5 +#define CYREG_B1_P4_U1_CFG6 0x400118c6 +#define CYREG_B1_P4_U1_CFG7 0x400118c7 +#define CYREG_B1_P4_U1_CFG8 0x400118c8 +#define CYREG_B1_P4_U1_CFG9 0x400118c9 +#define CYREG_B1_P4_U1_CFG10 0x400118ca +#define CYREG_B1_P4_U1_CFG11 0x400118cb +#define CYREG_B1_P4_U1_CFG12 0x400118cc +#define CYREG_B1_P4_U1_CFG13 0x400118cd +#define CYREG_B1_P4_U1_CFG14 0x400118ce +#define CYREG_B1_P4_U1_CFG15 0x400118cf +#define CYREG_B1_P4_U1_CFG16 0x400118d0 +#define CYREG_B1_P4_U1_CFG17 0x400118d1 +#define CYREG_B1_P4_U1_CFG18 0x400118d2 +#define CYREG_B1_P4_U1_CFG19 0x400118d3 +#define CYREG_B1_P4_U1_CFG20 0x400118d4 +#define CYREG_B1_P4_U1_CFG21 0x400118d5 +#define CYREG_B1_P4_U1_CFG22 0x400118d6 +#define CYREG_B1_P4_U1_CFG23 0x400118d7 +#define CYREG_B1_P4_U1_CFG24 0x400118d8 +#define CYREG_B1_P4_U1_CFG25 0x400118d9 +#define CYREG_B1_P4_U1_CFG26 0x400118da +#define CYREG_B1_P4_U1_CFG27 0x400118db +#define CYREG_B1_P4_U1_CFG28 0x400118dc +#define CYREG_B1_P4_U1_CFG29 0x400118dd +#define CYREG_B1_P4_U1_CFG30 0x400118de +#define CYREG_B1_P4_U1_CFG31 0x400118df +#define CYREG_B1_P4_U1_DCFG0 0x400118e0 +#define CYREG_B1_P4_U1_DCFG1 0x400118e2 +#define CYREG_B1_P4_U1_DCFG2 0x400118e4 +#define CYREG_B1_P4_U1_DCFG3 0x400118e6 +#define CYREG_B1_P4_U1_DCFG4 0x400118e8 +#define CYREG_B1_P4_U1_DCFG5 0x400118ea +#define CYREG_B1_P4_U1_DCFG6 0x400118ec +#define CYREG_B1_P4_U1_DCFG7 0x400118ee +#define CYDEV_UCFG_B1_P4_ROUTE_BASE 0x40011900 +#define CYDEV_UCFG_B1_P4_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B1_P5_BASE 0x40011a00 +#define CYDEV_UCFG_B1_P5_SIZE 0x000001ef +#define CYDEV_UCFG_B1_P5_U0_BASE 0x40011a00 +#define CYDEV_UCFG_B1_P5_U0_SIZE 0x00000070 +#define CYREG_B1_P5_U0_PLD_IT0 0x40011a00 +#define CYREG_B1_P5_U0_PLD_IT1 0x40011a04 +#define CYREG_B1_P5_U0_PLD_IT2 0x40011a08 +#define CYREG_B1_P5_U0_PLD_IT3 0x40011a0c +#define CYREG_B1_P5_U0_PLD_IT4 0x40011a10 +#define CYREG_B1_P5_U0_PLD_IT5 0x40011a14 +#define CYREG_B1_P5_U0_PLD_IT6 0x40011a18 +#define CYREG_B1_P5_U0_PLD_IT7 0x40011a1c +#define CYREG_B1_P5_U0_PLD_IT8 0x40011a20 +#define CYREG_B1_P5_U0_PLD_IT9 0x40011a24 +#define CYREG_B1_P5_U0_PLD_IT10 0x40011a28 +#define CYREG_B1_P5_U0_PLD_IT11 0x40011a2c +#define CYREG_B1_P5_U0_PLD_ORT0 0x40011a30 +#define CYREG_B1_P5_U0_PLD_ORT1 0x40011a32 +#define CYREG_B1_P5_U0_PLD_ORT2 0x40011a34 +#define CYREG_B1_P5_U0_PLD_ORT3 0x40011a36 +#define CYREG_B1_P5_U0_MC_CFG_CEN_CONST 0x40011a38 +#define CYREG_B1_P5_U0_MC_CFG_XORFB 0x40011a3a +#define CYREG_B1_P5_U0_MC_CFG_SET_RESET 0x40011a3c +#define CYREG_B1_P5_U0_MC_CFG_BYPASS 0x40011a3e +#define CYREG_B1_P5_U0_CFG0 0x40011a40 +#define CYREG_B1_P5_U0_CFG1 0x40011a41 +#define CYREG_B1_P5_U0_CFG2 0x40011a42 +#define CYREG_B1_P5_U0_CFG3 0x40011a43 +#define CYREG_B1_P5_U0_CFG4 0x40011a44 +#define CYREG_B1_P5_U0_CFG5 0x40011a45 +#define CYREG_B1_P5_U0_CFG6 0x40011a46 +#define CYREG_B1_P5_U0_CFG7 0x40011a47 +#define CYREG_B1_P5_U0_CFG8 0x40011a48 +#define CYREG_B1_P5_U0_CFG9 0x40011a49 +#define CYREG_B1_P5_U0_CFG10 0x40011a4a +#define CYREG_B1_P5_U0_CFG11 0x40011a4b +#define CYREG_B1_P5_U0_CFG12 0x40011a4c +#define CYREG_B1_P5_U0_CFG13 0x40011a4d +#define CYREG_B1_P5_U0_CFG14 0x40011a4e +#define CYREG_B1_P5_U0_CFG15 0x40011a4f +#define CYREG_B1_P5_U0_CFG16 0x40011a50 +#define CYREG_B1_P5_U0_CFG17 0x40011a51 +#define CYREG_B1_P5_U0_CFG18 0x40011a52 +#define CYREG_B1_P5_U0_CFG19 0x40011a53 +#define CYREG_B1_P5_U0_CFG20 0x40011a54 +#define CYREG_B1_P5_U0_CFG21 0x40011a55 +#define CYREG_B1_P5_U0_CFG22 0x40011a56 +#define CYREG_B1_P5_U0_CFG23 0x40011a57 +#define CYREG_B1_P5_U0_CFG24 0x40011a58 +#define CYREG_B1_P5_U0_CFG25 0x40011a59 +#define CYREG_B1_P5_U0_CFG26 0x40011a5a +#define CYREG_B1_P5_U0_CFG27 0x40011a5b +#define CYREG_B1_P5_U0_CFG28 0x40011a5c +#define CYREG_B1_P5_U0_CFG29 0x40011a5d +#define CYREG_B1_P5_U0_CFG30 0x40011a5e +#define CYREG_B1_P5_U0_CFG31 0x40011a5f +#define CYREG_B1_P5_U0_DCFG0 0x40011a60 +#define CYREG_B1_P5_U0_DCFG1 0x40011a62 +#define CYREG_B1_P5_U0_DCFG2 0x40011a64 +#define CYREG_B1_P5_U0_DCFG3 0x40011a66 +#define CYREG_B1_P5_U0_DCFG4 0x40011a68 +#define CYREG_B1_P5_U0_DCFG5 0x40011a6a +#define CYREG_B1_P5_U0_DCFG6 0x40011a6c +#define CYREG_B1_P5_U0_DCFG7 0x40011a6e +#define CYDEV_UCFG_B1_P5_U1_BASE 0x40011a80 +#define CYDEV_UCFG_B1_P5_U1_SIZE 0x00000070 +#define CYREG_B1_P5_U1_PLD_IT0 0x40011a80 +#define CYREG_B1_P5_U1_PLD_IT1 0x40011a84 +#define CYREG_B1_P5_U1_PLD_IT2 0x40011a88 +#define CYREG_B1_P5_U1_PLD_IT3 0x40011a8c +#define CYREG_B1_P5_U1_PLD_IT4 0x40011a90 +#define CYREG_B1_P5_U1_PLD_IT5 0x40011a94 +#define CYREG_B1_P5_U1_PLD_IT6 0x40011a98 +#define CYREG_B1_P5_U1_PLD_IT7 0x40011a9c +#define CYREG_B1_P5_U1_PLD_IT8 0x40011aa0 +#define CYREG_B1_P5_U1_PLD_IT9 0x40011aa4 +#define CYREG_B1_P5_U1_PLD_IT10 0x40011aa8 +#define CYREG_B1_P5_U1_PLD_IT11 0x40011aac +#define CYREG_B1_P5_U1_PLD_ORT0 0x40011ab0 +#define CYREG_B1_P5_U1_PLD_ORT1 0x40011ab2 +#define CYREG_B1_P5_U1_PLD_ORT2 0x40011ab4 +#define CYREG_B1_P5_U1_PLD_ORT3 0x40011ab6 +#define CYREG_B1_P5_U1_MC_CFG_CEN_CONST 0x40011ab8 +#define CYREG_B1_P5_U1_MC_CFG_XORFB 0x40011aba +#define CYREG_B1_P5_U1_MC_CFG_SET_RESET 0x40011abc +#define CYREG_B1_P5_U1_MC_CFG_BYPASS 0x40011abe +#define CYREG_B1_P5_U1_CFG0 0x40011ac0 +#define CYREG_B1_P5_U1_CFG1 0x40011ac1 +#define CYREG_B1_P5_U1_CFG2 0x40011ac2 +#define CYREG_B1_P5_U1_CFG3 0x40011ac3 +#define CYREG_B1_P5_U1_CFG4 0x40011ac4 +#define CYREG_B1_P5_U1_CFG5 0x40011ac5 +#define CYREG_B1_P5_U1_CFG6 0x40011ac6 +#define CYREG_B1_P5_U1_CFG7 0x40011ac7 +#define CYREG_B1_P5_U1_CFG8 0x40011ac8 +#define CYREG_B1_P5_U1_CFG9 0x40011ac9 +#define CYREG_B1_P5_U1_CFG10 0x40011aca +#define CYREG_B1_P5_U1_CFG11 0x40011acb +#define CYREG_B1_P5_U1_CFG12 0x40011acc +#define CYREG_B1_P5_U1_CFG13 0x40011acd +#define CYREG_B1_P5_U1_CFG14 0x40011ace +#define CYREG_B1_P5_U1_CFG15 0x40011acf +#define CYREG_B1_P5_U1_CFG16 0x40011ad0 +#define CYREG_B1_P5_U1_CFG17 0x40011ad1 +#define CYREG_B1_P5_U1_CFG18 0x40011ad2 +#define CYREG_B1_P5_U1_CFG19 0x40011ad3 +#define CYREG_B1_P5_U1_CFG20 0x40011ad4 +#define CYREG_B1_P5_U1_CFG21 0x40011ad5 +#define CYREG_B1_P5_U1_CFG22 0x40011ad6 +#define CYREG_B1_P5_U1_CFG23 0x40011ad7 +#define CYREG_B1_P5_U1_CFG24 0x40011ad8 +#define CYREG_B1_P5_U1_CFG25 0x40011ad9 +#define CYREG_B1_P5_U1_CFG26 0x40011ada +#define CYREG_B1_P5_U1_CFG27 0x40011adb +#define CYREG_B1_P5_U1_CFG28 0x40011adc +#define CYREG_B1_P5_U1_CFG29 0x40011add +#define CYREG_B1_P5_U1_CFG30 0x40011ade +#define CYREG_B1_P5_U1_CFG31 0x40011adf +#define CYREG_B1_P5_U1_DCFG0 0x40011ae0 +#define CYREG_B1_P5_U1_DCFG1 0x40011ae2 +#define CYREG_B1_P5_U1_DCFG2 0x40011ae4 +#define CYREG_B1_P5_U1_DCFG3 0x40011ae6 +#define CYREG_B1_P5_U1_DCFG4 0x40011ae8 +#define CYREG_B1_P5_U1_DCFG5 0x40011aea +#define CYREG_B1_P5_U1_DCFG6 0x40011aec +#define CYREG_B1_P5_U1_DCFG7 0x40011aee +#define CYDEV_UCFG_B1_P5_ROUTE_BASE 0x40011b00 +#define CYDEV_UCFG_B1_P5_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_DSI0_BASE 0x40014000 +#define CYDEV_UCFG_DSI0_SIZE 0x000000ef +#define CYDEV_UCFG_DSI1_BASE 0x40014100 +#define CYDEV_UCFG_DSI1_SIZE 0x000000ef +#define CYDEV_UCFG_DSI2_BASE 0x40014200 +#define CYDEV_UCFG_DSI2_SIZE 0x000000ef +#define CYDEV_UCFG_DSI3_BASE 0x40014300 +#define CYDEV_UCFG_DSI3_SIZE 0x000000ef +#define CYDEV_UCFG_DSI4_BASE 0x40014400 +#define CYDEV_UCFG_DSI4_SIZE 0x000000ef +#define CYDEV_UCFG_DSI5_BASE 0x40014500 +#define CYDEV_UCFG_DSI5_SIZE 0x000000ef +#define CYDEV_UCFG_DSI6_BASE 0x40014600 +#define CYDEV_UCFG_DSI6_SIZE 0x000000ef +#define CYDEV_UCFG_DSI7_BASE 0x40014700 +#define CYDEV_UCFG_DSI7_SIZE 0x000000ef +#define CYDEV_UCFG_DSI8_BASE 0x40014800 +#define CYDEV_UCFG_DSI8_SIZE 0x000000ef +#define CYDEV_UCFG_DSI9_BASE 0x40014900 +#define CYDEV_UCFG_DSI9_SIZE 0x000000ef +#define CYDEV_UCFG_DSI12_BASE 0x40014c00 +#define CYDEV_UCFG_DSI12_SIZE 0x000000ef +#define CYDEV_UCFG_DSI13_BASE 0x40014d00 +#define CYDEV_UCFG_DSI13_SIZE 0x000000ef +#define CYDEV_UCFG_BCTL0_BASE 0x40015000 +#define CYDEV_UCFG_BCTL0_SIZE 0x00000010 +#define CYREG_BCTL0_MDCLK_EN 0x40015000 +#define CYREG_BCTL0_MBCLK_EN 0x40015001 +#define CYREG_BCTL0_WAIT_CFG 0x40015002 +#define CYREG_BCTL0_BANK_CTL 0x40015003 +#define CYREG_BCTL0_UDB_TEST_3 0x40015007 +#define CYREG_BCTL0_DCLK_EN0 0x40015008 +#define CYREG_BCTL0_BCLK_EN0 0x40015009 +#define CYREG_BCTL0_DCLK_EN1 0x4001500a +#define CYREG_BCTL0_BCLK_EN1 0x4001500b +#define CYREG_BCTL0_DCLK_EN2 0x4001500c +#define CYREG_BCTL0_BCLK_EN2 0x4001500d +#define CYREG_BCTL0_DCLK_EN3 0x4001500e +#define CYREG_BCTL0_BCLK_EN3 0x4001500f +#define CYDEV_UCFG_BCTL1_BASE 0x40015010 +#define CYDEV_UCFG_BCTL1_SIZE 0x00000010 +#define CYREG_BCTL1_MDCLK_EN 0x40015010 +#define CYREG_BCTL1_MBCLK_EN 0x40015011 +#define CYREG_BCTL1_WAIT_CFG 0x40015012 +#define CYREG_BCTL1_BANK_CTL 0x40015013 +#define CYREG_BCTL1_UDB_TEST_3 0x40015017 +#define CYREG_BCTL1_DCLK_EN0 0x40015018 +#define CYREG_BCTL1_BCLK_EN0 0x40015019 +#define CYREG_BCTL1_DCLK_EN1 0x4001501a +#define CYREG_BCTL1_BCLK_EN1 0x4001501b +#define CYREG_BCTL1_DCLK_EN2 0x4001501c +#define CYREG_BCTL1_BCLK_EN2 0x4001501d +#define CYREG_BCTL1_DCLK_EN3 0x4001501e +#define CYREG_BCTL1_BCLK_EN3 0x4001501f +#define CYDEV_IDMUX_BASE 0x40015100 +#define CYDEV_IDMUX_SIZE 0x00000016 +#define CYREG_IDMUX_IRQ_CTL0 0x40015100 +#define CYREG_IDMUX_IRQ_CTL1 0x40015101 +#define CYREG_IDMUX_IRQ_CTL2 0x40015102 +#define CYREG_IDMUX_IRQ_CTL3 0x40015103 +#define CYREG_IDMUX_IRQ_CTL4 0x40015104 +#define CYREG_IDMUX_IRQ_CTL5 0x40015105 +#define CYREG_IDMUX_IRQ_CTL6 0x40015106 +#define CYREG_IDMUX_IRQ_CTL7 0x40015107 +#define CYREG_IDMUX_DRQ_CTL0 0x40015110 +#define CYREG_IDMUX_DRQ_CTL1 0x40015111 +#define CYREG_IDMUX_DRQ_CTL2 0x40015112 +#define CYREG_IDMUX_DRQ_CTL3 0x40015113 +#define CYREG_IDMUX_DRQ_CTL4 0x40015114 +#define CYREG_IDMUX_DRQ_CTL5 0x40015115 +#define CYDEV_CACHERAM_BASE 0x40030000 +#define CYDEV_CACHERAM_SIZE 0x00000400 +#define CYREG_CACHERAM_DATA_MBASE 0x40030000 +#define CYREG_CACHERAM_DATA_MSIZE 0x00000400 +#define CYDEV_SFR_BASE 0x40050100 +#define CYDEV_SFR_SIZE 0x000000fb +#define CYREG_SFR_GPIO0 0x40050180 +#define CYREG_SFR_GPIRD0 0x40050189 +#define CYREG_SFR_GPIO0_SEL 0x4005018a +#define CYREG_SFR_GPIO1 0x40050190 +#define CYREG_SFR_GPIRD1 0x40050191 +#define CYREG_SFR_GPIO2 0x40050198 +#define CYREG_SFR_GPIRD2 0x40050199 +#define CYREG_SFR_GPIO2_SEL 0x4005019a +#define CYREG_SFR_GPIO1_SEL 0x400501a2 +#define CYREG_SFR_GPIO3 0x400501b0 +#define CYREG_SFR_GPIRD3 0x400501b1 +#define CYREG_SFR_GPIO3_SEL 0x400501b2 +#define CYREG_SFR_GPIO4 0x400501c0 +#define CYREG_SFR_GPIRD4 0x400501c1 +#define CYREG_SFR_GPIO4_SEL 0x400501c2 +#define CYREG_SFR_GPIO5 0x400501c8 +#define CYREG_SFR_GPIRD5 0x400501c9 +#define CYREG_SFR_GPIO5_SEL 0x400501ca +#define CYREG_SFR_GPIO6 0x400501d8 +#define CYREG_SFR_GPIRD6 0x400501d9 +#define CYREG_SFR_GPIO6_SEL 0x400501da +#define CYREG_SFR_GPIO12 0x400501e8 +#define CYREG_SFR_GPIRD12 0x400501e9 +#define CYREG_SFR_GPIO12_SEL 0x400501f2 +#define CYREG_SFR_GPIO15 0x400501f8 +#define CYREG_SFR_GPIRD15 0x400501f9 +#define CYREG_SFR_GPIO15_SEL 0x400501fa +#define CYDEV_P3BA_BASE 0x40050300 +#define CYDEV_P3BA_SIZE 0x0000002b +#define CYREG_P3BA_Y_START 0x40050300 +#define CYREG_P3BA_YROLL 0x40050301 +#define CYREG_P3BA_YCFG 0x40050302 +#define CYREG_P3BA_X_START1 0x40050303 +#define CYREG_P3BA_X_START2 0x40050304 +#define CYREG_P3BA_XROLL1 0x40050305 +#define CYREG_P3BA_XROLL2 0x40050306 +#define CYREG_P3BA_XINC 0x40050307 +#define CYREG_P3BA_XCFG 0x40050308 +#define CYREG_P3BA_OFFSETADDR1 0x40050309 +#define CYREG_P3BA_OFFSETADDR2 0x4005030a +#define CYREG_P3BA_OFFSETADDR3 0x4005030b +#define CYREG_P3BA_ABSADDR1 0x4005030c +#define CYREG_P3BA_ABSADDR2 0x4005030d +#define CYREG_P3BA_ABSADDR3 0x4005030e +#define CYREG_P3BA_ABSADDR4 0x4005030f +#define CYREG_P3BA_DATCFG1 0x40050310 +#define CYREG_P3BA_DATCFG2 0x40050311 +#define CYREG_P3BA_CMP_RSLT1 0x40050314 +#define CYREG_P3BA_CMP_RSLT2 0x40050315 +#define CYREG_P3BA_CMP_RSLT3 0x40050316 +#define CYREG_P3BA_CMP_RSLT4 0x40050317 +#define CYREG_P3BA_DATA_REG1 0x40050318 +#define CYREG_P3BA_DATA_REG2 0x40050319 +#define CYREG_P3BA_DATA_REG3 0x4005031a +#define CYREG_P3BA_DATA_REG4 0x4005031b +#define CYREG_P3BA_EXP_DATA1 0x4005031c +#define CYREG_P3BA_EXP_DATA2 0x4005031d +#define CYREG_P3BA_EXP_DATA3 0x4005031e +#define CYREG_P3BA_EXP_DATA4 0x4005031f +#define CYREG_P3BA_MSTR_HRDATA1 0x40050320 +#define CYREG_P3BA_MSTR_HRDATA2 0x40050321 +#define CYREG_P3BA_MSTR_HRDATA3 0x40050322 +#define CYREG_P3BA_MSTR_HRDATA4 0x40050323 +#define CYREG_P3BA_BIST_EN 0x40050324 +#define CYREG_P3BA_PHUB_MASTER_SSR 0x40050325 +#define CYREG_P3BA_SEQCFG1 0x40050326 +#define CYREG_P3BA_SEQCFG2 0x40050327 +#define CYREG_P3BA_Y_CURR 0x40050328 +#define CYREG_P3BA_X_CURR1 0x40050329 +#define CYREG_P3BA_X_CURR2 0x4005032a +#define CYDEV_PANTHER_BASE 0x40080000 +#define CYDEV_PANTHER_SIZE 0x00000020 +#define CYREG_PANTHER_STCALIB_CFG 0x40080000 +#define CYREG_PANTHER_WAITPIPE 0x40080004 +#define CYREG_PANTHER_TRACE_CFG 0x40080008 +#define CYREG_PANTHER_DBG_CFG 0x4008000c +#define CYREG_PANTHER_CM3_LCKRST_STAT 0x40080018 +#define CYREG_PANTHER_DEVICE_ID 0x4008001c +#define CYDEV_FLSECC_BASE 0x48000000 +#define CYDEV_FLSECC_SIZE 0x00008000 +#define CYREG_FLSECC_DATA_MBASE 0x48000000 +#define CYREG_FLSECC_DATA_MSIZE 0x00008000 +#define CYDEV_FLSHID_BASE 0x49000000 +#define CYDEV_FLSHID_SIZE 0x00000200 +#define CYREG_FLSHID_RSVD_MBASE 0x49000000 +#define CYREG_FLSHID_RSVD_MSIZE 0x00000080 +#define CYREG_FLSHID_CUST_MDATA_MBASE 0x49000080 +#define CYREG_FLSHID_CUST_MDATA_MSIZE 0x00000080 +#define CYDEV_FLSHID_CUST_TABLES_BASE 0x49000100 +#define CYDEV_FLSHID_CUST_TABLES_SIZE 0x00000040 +#define CYREG_FLSHID_CUST_TABLES_Y_LOC 0x49000100 +#define CYREG_FLSHID_CUST_TABLES_X_LOC 0x49000101 +#define CYREG_FLSHID_CUST_TABLES_WAFER_NUM 0x49000102 +#define CYREG_FLSHID_CUST_TABLES_LOT_LSB 0x49000103 +#define CYREG_FLSHID_CUST_TABLES_LOT_MSB 0x49000104 +#define CYREG_FLSHID_CUST_TABLES_WRK_WK 0x49000105 +#define CYREG_FLSHID_CUST_TABLES_FAB_YR 0x49000106 +#define CYREG_FLSHID_CUST_TABLES_MINOR 0x49000107 +#define CYREG_FLSHID_CUST_TABLES_IMO_3MHZ 0x49000108 +#define CYREG_FLSHID_CUST_TABLES_IMO_6MHZ 0x49000109 +#define CYREG_FLSHID_CUST_TABLES_IMO_12MHZ 0x4900010a +#define CYREG_FLSHID_CUST_TABLES_IMO_24MHZ 0x4900010b +#define CYREG_FLSHID_CUST_TABLES_IMO_67MHZ 0x4900010c +#define CYREG_FLSHID_CUST_TABLES_IMO_80MHZ 0x4900010d +#define CYREG_FLSHID_CUST_TABLES_IMO_92MHZ 0x4900010e +#define CYREG_FLSHID_CUST_TABLES_IMO_USB 0x4900010f +#define CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS 0x49000110 +#define CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS 0x49000111 +#define CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS 0x49000112 +#define CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS 0x49000113 +#define CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS 0x49000114 +#define CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS 0x49000115 +#define CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS 0x49000116 +#define CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS 0x49000117 +#define CYREG_FLSHID_CUST_TABLES_DEC_M1 0x49000118 +#define CYREG_FLSHID_CUST_TABLES_DEC_M2 0x49000119 +#define CYREG_FLSHID_CUST_TABLES_DEC_M3 0x4900011a +#define CYREG_FLSHID_CUST_TABLES_DEC_M4 0x4900011b +#define CYREG_FLSHID_CUST_TABLES_DEC_M5 0x4900011c +#define CYREG_FLSHID_CUST_TABLES_DEC_M6 0x4900011d +#define CYREG_FLSHID_CUST_TABLES_DEC_M7 0x4900011e +#define CYREG_FLSHID_CUST_TABLES_DEC_M8 0x4900011f +#define CYREG_FLSHID_CUST_TABLES_DAC0_M1 0x49000120 +#define CYREG_FLSHID_CUST_TABLES_DAC0_M2 0x49000121 +#define CYREG_FLSHID_CUST_TABLES_DAC0_M3 0x49000122 +#define CYREG_FLSHID_CUST_TABLES_DAC0_M4 0x49000123 +#define CYREG_FLSHID_CUST_TABLES_DAC0_M5 0x49000124 +#define CYREG_FLSHID_CUST_TABLES_DAC0_M6 0x49000125 +#define CYREG_FLSHID_CUST_TABLES_DAC0_M7 0x49000126 +#define CYREG_FLSHID_CUST_TABLES_DAC0_M8 0x49000127 +#define CYREG_FLSHID_CUST_TABLES_DAC2_M1 0x49000128 +#define CYREG_FLSHID_CUST_TABLES_DAC2_M2 0x49000129 +#define CYREG_FLSHID_CUST_TABLES_DAC2_M3 0x4900012a +#define CYREG_FLSHID_CUST_TABLES_DAC2_M4 0x4900012b +#define CYREG_FLSHID_CUST_TABLES_DAC2_M5 0x4900012c +#define CYREG_FLSHID_CUST_TABLES_DAC2_M6 0x4900012d +#define CYREG_FLSHID_CUST_TABLES_DAC2_M7 0x4900012e +#define CYREG_FLSHID_CUST_TABLES_DAC2_M8 0x4900012f +#define CYREG_FLSHID_CUST_TABLES_DAC1_M1 0x49000130 +#define CYREG_FLSHID_CUST_TABLES_DAC1_M2 0x49000131 +#define CYREG_FLSHID_CUST_TABLES_DAC1_M3 0x49000132 +#define CYREG_FLSHID_CUST_TABLES_DAC1_M4 0x49000133 +#define CYREG_FLSHID_CUST_TABLES_DAC1_M5 0x49000134 +#define CYREG_FLSHID_CUST_TABLES_DAC1_M6 0x49000135 +#define CYREG_FLSHID_CUST_TABLES_DAC1_M7 0x49000136 +#define CYREG_FLSHID_CUST_TABLES_DAC1_M8 0x49000137 +#define CYREG_FLSHID_CUST_TABLES_DAC3_M1 0x49000138 +#define CYREG_FLSHID_CUST_TABLES_DAC3_M2 0x49000139 +#define CYREG_FLSHID_CUST_TABLES_DAC3_M3 0x4900013a +#define CYREG_FLSHID_CUST_TABLES_DAC3_M4 0x4900013b +#define CYREG_FLSHID_CUST_TABLES_DAC3_M5 0x4900013c +#define CYREG_FLSHID_CUST_TABLES_DAC3_M6 0x4900013d +#define CYREG_FLSHID_CUST_TABLES_DAC3_M7 0x4900013e +#define CYREG_FLSHID_CUST_TABLES_DAC3_M8 0x4900013f +#define CYDEV_FLSHID_MFG_CFG_BASE 0x49000180 +#define CYDEV_FLSHID_MFG_CFG_SIZE 0x00000080 +#define CYREG_FLSHID_MFG_CFG_IMO_TR1 0x49000188 +#define CYREG_FLSHID_MFG_CFG_CMP0_TR0 0x490001ac +#define CYREG_FLSHID_MFG_CFG_CMP1_TR0 0x490001ae +#define CYREG_FLSHID_MFG_CFG_CMP2_TR0 0x490001b0 +#define CYREG_FLSHID_MFG_CFG_CMP3_TR0 0x490001b2 +#define CYREG_FLSHID_MFG_CFG_CMP0_TR1 0x490001b4 +#define CYREG_FLSHID_MFG_CFG_CMP1_TR1 0x490001b6 +#define CYREG_FLSHID_MFG_CFG_CMP2_TR1 0x490001b8 +#define CYREG_FLSHID_MFG_CFG_CMP3_TR1 0x490001ba +#define CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM 0x490001ce +#define CYDEV_EXTMEM_BASE 0x60000000 +#define CYDEV_EXTMEM_SIZE 0x00800000 +#define CYREG_EXTMEM_DATA_MBASE 0x60000000 +#define CYREG_EXTMEM_DATA_MSIZE 0x00800000 +#define CYDEV_ITM_BASE 0xe0000000 +#define CYDEV_ITM_SIZE 0x00001000 +#define CYREG_ITM_TRACE_EN 0xe0000e00 +#define CYREG_ITM_TRACE_PRIVILEGE 0xe0000e40 +#define CYREG_ITM_TRACE_CTRL 0xe0000e80 +#define CYREG_ITM_LOCK_ACCESS 0xe0000fb0 +#define CYREG_ITM_LOCK_STATUS 0xe0000fb4 +#define CYREG_ITM_PID4 0xe0000fd0 +#define CYREG_ITM_PID5 0xe0000fd4 +#define CYREG_ITM_PID6 0xe0000fd8 +#define CYREG_ITM_PID7 0xe0000fdc +#define CYREG_ITM_PID0 0xe0000fe0 +#define CYREG_ITM_PID1 0xe0000fe4 +#define CYREG_ITM_PID2 0xe0000fe8 +#define CYREG_ITM_PID3 0xe0000fec +#define CYREG_ITM_CID0 0xe0000ff0 +#define CYREG_ITM_CID1 0xe0000ff4 +#define CYREG_ITM_CID2 0xe0000ff8 +#define CYREG_ITM_CID3 0xe0000ffc +#define CYDEV_DWT_BASE 0xe0001000 +#define CYDEV_DWT_SIZE 0x0000005c +#define CYREG_DWT_CTRL 0xe0001000 +#define CYREG_DWT_CYCLE_COUNT 0xe0001004 +#define CYREG_DWT_CPI_COUNT 0xe0001008 +#define CYREG_DWT_EXC_OVHD_COUNT 0xe000100c +#define CYREG_DWT_SLEEP_COUNT 0xe0001010 +#define CYREG_DWT_LSU_COUNT 0xe0001014 +#define CYREG_DWT_FOLD_COUNT 0xe0001018 +#define CYREG_DWT_PC_SAMPLE 0xe000101c +#define CYREG_DWT_COMP_0 0xe0001020 +#define CYREG_DWT_MASK_0 0xe0001024 +#define CYREG_DWT_FUNCTION_0 0xe0001028 +#define CYREG_DWT_COMP_1 0xe0001030 +#define CYREG_DWT_MASK_1 0xe0001034 +#define CYREG_DWT_FUNCTION_1 0xe0001038 +#define CYREG_DWT_COMP_2 0xe0001040 +#define CYREG_DWT_MASK_2 0xe0001044 +#define CYREG_DWT_FUNCTION_2 0xe0001048 +#define CYREG_DWT_COMP_3 0xe0001050 +#define CYREG_DWT_MASK_3 0xe0001054 +#define CYREG_DWT_FUNCTION_3 0xe0001058 +#define CYDEV_FPB_BASE 0xe0002000 +#define CYDEV_FPB_SIZE 0x00001000 +#define CYREG_FPB_CTRL 0xe0002000 +#define CYREG_FPB_REMAP 0xe0002004 +#define CYREG_FPB_FP_COMP_0 0xe0002008 +#define CYREG_FPB_FP_COMP_1 0xe000200c +#define CYREG_FPB_FP_COMP_2 0xe0002010 +#define CYREG_FPB_FP_COMP_3 0xe0002014 +#define CYREG_FPB_FP_COMP_4 0xe0002018 +#define CYREG_FPB_FP_COMP_5 0xe000201c +#define CYREG_FPB_FP_COMP_6 0xe0002020 +#define CYREG_FPB_FP_COMP_7 0xe0002024 +#define CYREG_FPB_PID4 0xe0002fd0 +#define CYREG_FPB_PID5 0xe0002fd4 +#define CYREG_FPB_PID6 0xe0002fd8 +#define CYREG_FPB_PID7 0xe0002fdc +#define CYREG_FPB_PID0 0xe0002fe0 +#define CYREG_FPB_PID1 0xe0002fe4 +#define CYREG_FPB_PID2 0xe0002fe8 +#define CYREG_FPB_PID3 0xe0002fec +#define CYREG_FPB_CID0 0xe0002ff0 +#define CYREG_FPB_CID1 0xe0002ff4 +#define CYREG_FPB_CID2 0xe0002ff8 +#define CYREG_FPB_CID3 0xe0002ffc +#define CYDEV_NVIC_BASE 0xe000e000 +#define CYDEV_NVIC_SIZE 0x00000d3c +#define CYREG_NVIC_INT_CTL_TYPE 0xe000e004 +#define CYREG_NVIC_SYSTICK_CTL 0xe000e010 +#define CYREG_NVIC_SYSTICK_RELOAD 0xe000e014 +#define CYREG_NVIC_SYSTICK_CURRENT 0xe000e018 +#define CYREG_NVIC_SYSTICK_CAL 0xe000e01c +#define CYREG_NVIC_SETENA0 0xe000e100 +#define CYREG_NVIC_CLRENA0 0xe000e180 +#define CYREG_NVIC_SETPEND0 0xe000e200 +#define CYREG_NVIC_CLRPEND0 0xe000e280 +#define CYREG_NVIC_ACTIVE0 0xe000e300 +#define CYREG_NVIC_PRI_0 0xe000e400 +#define CYREG_NVIC_PRI_1 0xe000e401 +#define CYREG_NVIC_PRI_2 0xe000e402 +#define CYREG_NVIC_PRI_3 0xe000e403 +#define CYREG_NVIC_PRI_4 0xe000e404 +#define CYREG_NVIC_PRI_5 0xe000e405 +#define CYREG_NVIC_PRI_6 0xe000e406 +#define CYREG_NVIC_PRI_7 0xe000e407 +#define CYREG_NVIC_PRI_8 0xe000e408 +#define CYREG_NVIC_PRI_9 0xe000e409 +#define CYREG_NVIC_PRI_10 0xe000e40a +#define CYREG_NVIC_PRI_11 0xe000e40b +#define CYREG_NVIC_PRI_12 0xe000e40c +#define CYREG_NVIC_PRI_13 0xe000e40d +#define CYREG_NVIC_PRI_14 0xe000e40e +#define CYREG_NVIC_PRI_15 0xe000e40f +#define CYREG_NVIC_PRI_16 0xe000e410 +#define CYREG_NVIC_PRI_17 0xe000e411 +#define CYREG_NVIC_PRI_18 0xe000e412 +#define CYREG_NVIC_PRI_19 0xe000e413 +#define CYREG_NVIC_PRI_20 0xe000e414 +#define CYREG_NVIC_PRI_21 0xe000e415 +#define CYREG_NVIC_PRI_22 0xe000e416 +#define CYREG_NVIC_PRI_23 0xe000e417 +#define CYREG_NVIC_PRI_24 0xe000e418 +#define CYREG_NVIC_PRI_25 0xe000e419 +#define CYREG_NVIC_PRI_26 0xe000e41a +#define CYREG_NVIC_PRI_27 0xe000e41b +#define CYREG_NVIC_PRI_28 0xe000e41c +#define CYREG_NVIC_PRI_29 0xe000e41d +#define CYREG_NVIC_PRI_30 0xe000e41e +#define CYREG_NVIC_PRI_31 0xe000e41f +#define CYREG_NVIC_CPUID_BASE 0xe000ed00 +#define CYREG_NVIC_INTR_CTRL_STATE 0xe000ed04 +#define CYREG_NVIC_VECT_OFFSET 0xe000ed08 +#define CYREG_NVIC_APPLN_INTR 0xe000ed0c +#define CYREG_NVIC_SYSTEM_CONTROL 0xe000ed10 +#define CYREG_NVIC_CFG_CONTROL 0xe000ed14 +#define CYREG_NVIC_SYS_PRIO_HANDLER_4_7 0xe000ed18 +#define CYREG_NVIC_SYS_PRIO_HANDLER_8_11 0xe000ed1c +#define CYREG_NVIC_SYS_PRIO_HANDLER_12_15 0xe000ed20 +#define CYREG_NVIC_SYS_HANDLER_CSR 0xe000ed24 +#define CYREG_NVIC_MEMMAN_FAULT_STATUS 0xe000ed28 +#define CYREG_NVIC_BUS_FAULT_STATUS 0xe000ed29 +#define CYREG_NVIC_USAGE_FAULT_STATUS 0xe000ed2a +#define CYREG_NVIC_HARD_FAULT_STATUS 0xe000ed2c +#define CYREG_NVIC_DEBUG_FAULT_STATUS 0xe000ed30 +#define CYREG_NVIC_MEMMAN_FAULT_ADD 0xe000ed34 +#define CYREG_NVIC_BUS_FAULT_ADD 0xe000ed38 +#define CYDEV_CORE_DBG_BASE 0xe000edf0 +#define CYDEV_CORE_DBG_SIZE 0x00000010 +#define CYREG_CORE_DBG_DBG_HLT_CS 0xe000edf0 +#define CYREG_CORE_DBG_DBG_REG_SEL 0xe000edf4 +#define CYREG_CORE_DBG_DBG_REG_DATA 0xe000edf8 +#define CYREG_CORE_DBG_EXC_MON_CTL 0xe000edfc +#define CYDEV_TPIU_BASE 0xe0040000 +#define CYDEV_TPIU_SIZE 0x00001000 +#define CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ 0xe0040000 +#define CYREG_TPIU_CURRENT_SYNC_PRT_SZ 0xe0040004 +#define CYREG_TPIU_ASYNC_CLK_PRESCALER 0xe0040010 +#define CYREG_TPIU_PROTOCOL 0xe00400f0 +#define CYREG_TPIU_FORM_FLUSH_STAT 0xe0040300 +#define CYREG_TPIU_FORM_FLUSH_CTRL 0xe0040304 +#define CYREG_TPIU_TRIGGER 0xe0040ee8 +#define CYREG_TPIU_ITETMDATA 0xe0040eec +#define CYREG_TPIU_ITATBCTR2 0xe0040ef0 +#define CYREG_TPIU_ITATBCTR0 0xe0040ef8 +#define CYREG_TPIU_ITITMDATA 0xe0040efc +#define CYREG_TPIU_ITCTRL 0xe0040f00 +#define CYREG_TPIU_DEVID 0xe0040fc8 +#define CYREG_TPIU_DEVTYPE 0xe0040fcc +#define CYREG_TPIU_PID4 0xe0040fd0 +#define CYREG_TPIU_PID5 0xe0040fd4 +#define CYREG_TPIU_PID6 0xe0040fd8 +#define CYREG_TPIU_PID7 0xe0040fdc +#define CYREG_TPIU_PID0 0xe0040fe0 +#define CYREG_TPIU_PID1 0xe0040fe4 +#define CYREG_TPIU_PID2 0xe0040fe8 +#define CYREG_TPIU_PID3 0xe0040fec +#define CYREG_TPIU_CID0 0xe0040ff0 +#define CYREG_TPIU_CID1 0xe0040ff4 +#define CYREG_TPIU_CID2 0xe0040ff8 +#define CYREG_TPIU_CID3 0xe0040ffc +#define CYDEV_ETM_BASE 0xe0041000 +#define CYDEV_ETM_SIZE 0x00001000 +#define CYREG_ETM_CTL 0xe0041000 +#define CYREG_ETM_CFG_CODE 0xe0041004 +#define CYREG_ETM_TRIG_EVENT 0xe0041008 +#define CYREG_ETM_STATUS 0xe0041010 +#define CYREG_ETM_SYS_CFG 0xe0041014 +#define CYREG_ETM_TRACE_ENB_EVENT 0xe0041020 +#define CYREG_ETM_TRACE_EN_CTRL1 0xe0041024 +#define CYREG_ETM_FIFOFULL_LEVEL 0xe004102c +#define CYREG_ETM_SYNC_FREQ 0xe00411e0 +#define CYREG_ETM_ETM_ID 0xe00411e4 +#define CYREG_ETM_CFG_CODE_EXT 0xe00411e8 +#define CYREG_ETM_TR_SS_EMBICE_CTRL 0xe00411f0 +#define CYREG_ETM_CS_TRACE_ID 0xe0041200 +#define CYREG_ETM_OS_LOCK_ACCESS 0xe0041300 +#define CYREG_ETM_OS_LOCK_STATUS 0xe0041304 +#define CYREG_ETM_PDSR 0xe0041314 +#define CYREG_ETM_ITMISCIN 0xe0041ee0 +#define CYREG_ETM_ITTRIGOUT 0xe0041ee8 +#define CYREG_ETM_ITATBCTR2 0xe0041ef0 +#define CYREG_ETM_ITATBCTR0 0xe0041ef8 +#define CYREG_ETM_INT_MODE_CTRL 0xe0041f00 +#define CYREG_ETM_CLM_TAG_SET 0xe0041fa0 +#define CYREG_ETM_CLM_TAG_CLR 0xe0041fa4 +#define CYREG_ETM_LOCK_ACCESS 0xe0041fb0 +#define CYREG_ETM_LOCK_STATUS 0xe0041fb4 +#define CYREG_ETM_AUTH_STATUS 0xe0041fb8 +#define CYREG_ETM_DEV_TYPE 0xe0041fcc +#define CYREG_ETM_PID4 0xe0041fd0 +#define CYREG_ETM_PID5 0xe0041fd4 +#define CYREG_ETM_PID6 0xe0041fd8 +#define CYREG_ETM_PID7 0xe0041fdc +#define CYREG_ETM_PID0 0xe0041fe0 +#define CYREG_ETM_PID1 0xe0041fe4 +#define CYREG_ETM_PID2 0xe0041fe8 +#define CYREG_ETM_PID3 0xe0041fec +#define CYREG_ETM_CID0 0xe0041ff0 +#define CYREG_ETM_CID1 0xe0041ff4 +#define CYREG_ETM_CID2 0xe0041ff8 +#define CYREG_ETM_CID3 0xe0041ffc +#define CYDEV_ROM_TABLE_BASE 0xe00ff000 +#define CYDEV_ROM_TABLE_SIZE 0x00001000 +#define CYREG_ROM_TABLE_NVIC 0xe00ff000 +#define CYREG_ROM_TABLE_DWT 0xe00ff004 +#define CYREG_ROM_TABLE_FPB 0xe00ff008 +#define CYREG_ROM_TABLE_ITM 0xe00ff00c +#define CYREG_ROM_TABLE_TPIU 0xe00ff010 +#define CYREG_ROM_TABLE_ETM 0xe00ff014 +#define CYREG_ROM_TABLE_END 0xe00ff018 +#define CYREG_ROM_TABLE_MEMTYPE 0xe00fffcc +#define CYREG_ROM_TABLE_PID4 0xe00fffd0 +#define CYREG_ROM_TABLE_PID5 0xe00fffd4 +#define CYREG_ROM_TABLE_PID6 0xe00fffd8 +#define CYREG_ROM_TABLE_PID7 0xe00fffdc +#define CYREG_ROM_TABLE_PID0 0xe00fffe0 +#define CYREG_ROM_TABLE_PID1 0xe00fffe4 +#define CYREG_ROM_TABLE_PID2 0xe00fffe8 +#define CYREG_ROM_TABLE_PID3 0xe00fffec +#define CYREG_ROM_TABLE_CID0 0xe00ffff0 +#define CYREG_ROM_TABLE_CID1 0xe00ffff4 +#define CYREG_ROM_TABLE_CID2 0xe00ffff8 +#define CYREG_ROM_TABLE_CID3 0xe00ffffc +#define CYDEV_FLS_SIZE CYDEV_FLASH_SIZE +#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE +#define CYDEV_FLS_SECTOR_SIZE 0x00010000 +#define CYDEV_FLS_ROW_SIZE 0x00000100 +#define CYDEV_ECC_SECTOR_SIZE 0x00002000 +#define CYDEV_ECC_ROW_SIZE 0x00000020 +#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400 +#define CYDEV_EEPROM_ROW_SIZE 0x00000010 +#define CYDEV_PERIPH_BASE CYDEV_CLKDIST_BASE +#define CYCLK_LD_DISABLE 0x00000004 +#define CYCLK_LD_SYNC_EN 0x00000002 +#define CYCLK_LD_LOAD 0x00000001 +#define CYCLK_PIPE 0x00000080 +#define CYCLK_SSS 0x00000040 +#define CYCLK_EARLY 0x00000020 +#define CYCLK_DUTY 0x00000010 +#define CYCLK_SYNC 0x00000008 +#define CYCLK_SRC_SEL_CLK_SYNC_D 0 +#define CYCLK_SRC_SEL_SYNC_DIG 0 +#define CYCLK_SRC_SEL_IMO 1 +#define CYCLK_SRC_SEL_XTAL_MHZ 2 +#define CYCLK_SRC_SEL_XTALM 2 +#define CYCLK_SRC_SEL_ILO 3 +#define CYCLK_SRC_SEL_PLL 4 +#define CYCLK_SRC_SEL_XTAL_KHZ 5 +#define CYCLK_SRC_SEL_XTALK 5 +#define CYCLK_SRC_SEL_DSI_G 6 +#define CYCLK_SRC_SEL_DSI_D 7 +#define CYCLK_SRC_SEL_CLK_SYNC_A 0 +#define CYCLK_SRC_SEL_DSI_A 7 diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydevicerv.inc b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydevicerv.inc new file mode 100755 index 00000000..b5f7a51f --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydevicerv.inc @@ -0,0 +1,16039 @@ +; +; FILENAME: cydevicerv.inc +; OBSOLETE: Do not use this file. Use the _trm version instead. +; PSoC Creator 3.0 Component Pack 7 +; +; DESCRIPTION: +; This file provides all of the address values for the entire PSoC device. +; +;------------------------------------------------------------------------------- +; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + + IF :LNOT::DEF:CYDEV_FLASH_BASE +CYDEV_FLASH_BASE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLASH_SIZE +CYDEV_FLASH_SIZE EQU 0x00020000 + ENDIF + IF :LNOT::DEF:CYDEV_FLASH_DATA_MBASE +CYDEV_FLASH_DATA_MBASE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLASH_DATA_MSIZE +CYDEV_FLASH_DATA_MSIZE EQU 0x00020000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_BASE +CYDEV_SRAM_BASE EQU 0x1fffc000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_SIZE +CYDEV_SRAM_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE64K_MBASE +CYDEV_SRAM_CODE64K_MBASE EQU 0x1fff8000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE64K_MSIZE +CYDEV_SRAM_CODE64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE32K_MBASE +CYDEV_SRAM_CODE32K_MBASE EQU 0x1fffc000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE32K_MSIZE +CYDEV_SRAM_CODE32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE16K_MBASE +CYDEV_SRAM_CODE16K_MBASE EQU 0x1fffe000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE16K_MSIZE +CYDEV_SRAM_CODE16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE_MBASE +CYDEV_SRAM_CODE_MBASE EQU 0x1fffc000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE_MSIZE +CYDEV_SRAM_CODE_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA_MBASE +CYDEV_SRAM_DATA_MBASE EQU 0x20000000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA_MSIZE +CYDEV_SRAM_DATA_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA16K_MBASE +CYDEV_SRAM_DATA16K_MBASE EQU 0x20001000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA16K_MSIZE +CYDEV_SRAM_DATA16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA32K_MBASE +CYDEV_SRAM_DATA32K_MBASE EQU 0x20002000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA32K_MSIZE +CYDEV_SRAM_DATA32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA64K_MBASE +CYDEV_SRAM_DATA64K_MBASE EQU 0x20004000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA64K_MSIZE +CYDEV_SRAM_DATA64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_BASE +CYDEV_DMA_BASE EQU 0x20008000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SIZE +CYDEV_DMA_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM64K_MBASE +CYDEV_DMA_SRAM64K_MBASE EQU 0x20008000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM64K_MSIZE +CYDEV_DMA_SRAM64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM32K_MBASE +CYDEV_DMA_SRAM32K_MBASE EQU 0x2000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM32K_MSIZE +CYDEV_DMA_SRAM32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM16K_MBASE +CYDEV_DMA_SRAM16K_MBASE EQU 0x2000e000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM16K_MSIZE +CYDEV_DMA_SRAM16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM_MBASE +CYDEV_DMA_SRAM_MBASE EQU 0x2000f000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM_MSIZE +CYDEV_DMA_SRAM_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_BASE +CYDEV_CLKDIST_BASE EQU 0x40004000 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_SIZE +CYDEV_CLKDIST_SIZE EQU 0x00000110 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_CR +CYDEV_CLKDIST_CR EQU 0x40004000 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_LD +CYDEV_CLKDIST_LD EQU 0x40004001 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_WRK0 +CYDEV_CLKDIST_WRK0 EQU 0x40004002 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_WRK1 +CYDEV_CLKDIST_WRK1 EQU 0x40004003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_MSTR0 +CYDEV_CLKDIST_MSTR0 EQU 0x40004004 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_MSTR1 +CYDEV_CLKDIST_MSTR1 EQU 0x40004005 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_BCFG0 +CYDEV_CLKDIST_BCFG0 EQU 0x40004006 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_BCFG1 +CYDEV_CLKDIST_BCFG1 EQU 0x40004007 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_BCFG2 +CYDEV_CLKDIST_BCFG2 EQU 0x40004008 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_UCFG +CYDEV_CLKDIST_UCFG EQU 0x40004009 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DLY0 +CYDEV_CLKDIST_DLY0 EQU 0x4000400a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DLY1 +CYDEV_CLKDIST_DLY1 EQU 0x4000400b + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DMASK +CYDEV_CLKDIST_DMASK EQU 0x40004010 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_AMASK +CYDEV_CLKDIST_AMASK EQU 0x40004014 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_BASE +CYDEV_CLKDIST_DCFG0_BASE EQU 0x40004080 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_SIZE +CYDEV_CLKDIST_DCFG0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_CFG0 +CYDEV_CLKDIST_DCFG0_CFG0 EQU 0x40004080 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_CFG1 +CYDEV_CLKDIST_DCFG0_CFG1 EQU 0x40004081 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_CFG2 +CYDEV_CLKDIST_DCFG0_CFG2 EQU 0x40004082 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_BASE +CYDEV_CLKDIST_DCFG1_BASE EQU 0x40004084 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_SIZE +CYDEV_CLKDIST_DCFG1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_CFG0 +CYDEV_CLKDIST_DCFG1_CFG0 EQU 0x40004084 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_CFG1 +CYDEV_CLKDIST_DCFG1_CFG1 EQU 0x40004085 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_CFG2 +CYDEV_CLKDIST_DCFG1_CFG2 EQU 0x40004086 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_BASE +CYDEV_CLKDIST_DCFG2_BASE EQU 0x40004088 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_SIZE +CYDEV_CLKDIST_DCFG2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_CFG0 +CYDEV_CLKDIST_DCFG2_CFG0 EQU 0x40004088 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_CFG1 +CYDEV_CLKDIST_DCFG2_CFG1 EQU 0x40004089 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_CFG2 +CYDEV_CLKDIST_DCFG2_CFG2 EQU 0x4000408a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_BASE +CYDEV_CLKDIST_DCFG3_BASE EQU 0x4000408c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_SIZE +CYDEV_CLKDIST_DCFG3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_CFG0 +CYDEV_CLKDIST_DCFG3_CFG0 EQU 0x4000408c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_CFG1 +CYDEV_CLKDIST_DCFG3_CFG1 EQU 0x4000408d + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_CFG2 +CYDEV_CLKDIST_DCFG3_CFG2 EQU 0x4000408e + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_BASE +CYDEV_CLKDIST_DCFG4_BASE EQU 0x40004090 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_SIZE +CYDEV_CLKDIST_DCFG4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_CFG0 +CYDEV_CLKDIST_DCFG4_CFG0 EQU 0x40004090 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_CFG1 +CYDEV_CLKDIST_DCFG4_CFG1 EQU 0x40004091 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_CFG2 +CYDEV_CLKDIST_DCFG4_CFG2 EQU 0x40004092 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_BASE +CYDEV_CLKDIST_DCFG5_BASE EQU 0x40004094 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_SIZE +CYDEV_CLKDIST_DCFG5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_CFG0 +CYDEV_CLKDIST_DCFG5_CFG0 EQU 0x40004094 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_CFG1 +CYDEV_CLKDIST_DCFG5_CFG1 EQU 0x40004095 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_CFG2 +CYDEV_CLKDIST_DCFG5_CFG2 EQU 0x40004096 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_BASE +CYDEV_CLKDIST_DCFG6_BASE EQU 0x40004098 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_SIZE +CYDEV_CLKDIST_DCFG6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_CFG0 +CYDEV_CLKDIST_DCFG6_CFG0 EQU 0x40004098 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_CFG1 +CYDEV_CLKDIST_DCFG6_CFG1 EQU 0x40004099 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_CFG2 +CYDEV_CLKDIST_DCFG6_CFG2 EQU 0x4000409a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_BASE +CYDEV_CLKDIST_DCFG7_BASE EQU 0x4000409c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_SIZE +CYDEV_CLKDIST_DCFG7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_CFG0 +CYDEV_CLKDIST_DCFG7_CFG0 EQU 0x4000409c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_CFG1 +CYDEV_CLKDIST_DCFG7_CFG1 EQU 0x4000409d + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_CFG2 +CYDEV_CLKDIST_DCFG7_CFG2 EQU 0x4000409e + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_BASE +CYDEV_CLKDIST_ACFG0_BASE EQU 0x40004100 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_SIZE +CYDEV_CLKDIST_ACFG0_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_CFG0 +CYDEV_CLKDIST_ACFG0_CFG0 EQU 0x40004100 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_CFG1 +CYDEV_CLKDIST_ACFG0_CFG1 EQU 0x40004101 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_CFG2 +CYDEV_CLKDIST_ACFG0_CFG2 EQU 0x40004102 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_CFG3 +CYDEV_CLKDIST_ACFG0_CFG3 EQU 0x40004103 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_BASE +CYDEV_CLKDIST_ACFG1_BASE EQU 0x40004104 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_SIZE +CYDEV_CLKDIST_ACFG1_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_CFG0 +CYDEV_CLKDIST_ACFG1_CFG0 EQU 0x40004104 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_CFG1 +CYDEV_CLKDIST_ACFG1_CFG1 EQU 0x40004105 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_CFG2 +CYDEV_CLKDIST_ACFG1_CFG2 EQU 0x40004106 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_CFG3 +CYDEV_CLKDIST_ACFG1_CFG3 EQU 0x40004107 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_BASE +CYDEV_CLKDIST_ACFG2_BASE EQU 0x40004108 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_SIZE +CYDEV_CLKDIST_ACFG2_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_CFG0 +CYDEV_CLKDIST_ACFG2_CFG0 EQU 0x40004108 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_CFG1 +CYDEV_CLKDIST_ACFG2_CFG1 EQU 0x40004109 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_CFG2 +CYDEV_CLKDIST_ACFG2_CFG2 EQU 0x4000410a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_CFG3 +CYDEV_CLKDIST_ACFG2_CFG3 EQU 0x4000410b + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_BASE +CYDEV_CLKDIST_ACFG3_BASE EQU 0x4000410c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_SIZE +CYDEV_CLKDIST_ACFG3_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_CFG0 +CYDEV_CLKDIST_ACFG3_CFG0 EQU 0x4000410c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_CFG1 +CYDEV_CLKDIST_ACFG3_CFG1 EQU 0x4000410d + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_CFG2 +CYDEV_CLKDIST_ACFG3_CFG2 EQU 0x4000410e + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_CFG3 +CYDEV_CLKDIST_ACFG3_CFG3 EQU 0x4000410f + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_BASE +CYDEV_FASTCLK_BASE EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_SIZE +CYDEV_FASTCLK_SIZE EQU 0x00000026 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_IMO_BASE +CYDEV_FASTCLK_IMO_BASE EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_IMO_SIZE +CYDEV_FASTCLK_IMO_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_IMO_CR +CYDEV_FASTCLK_IMO_CR EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_BASE +CYDEV_FASTCLK_XMHZ_BASE EQU 0x40004210 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_SIZE +CYDEV_FASTCLK_XMHZ_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_CSR +CYDEV_FASTCLK_XMHZ_CSR EQU 0x40004210 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_CFG0 +CYDEV_FASTCLK_XMHZ_CFG0 EQU 0x40004212 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_CFG1 +CYDEV_FASTCLK_XMHZ_CFG1 EQU 0x40004213 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_BASE +CYDEV_FASTCLK_PLL_BASE EQU 0x40004220 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_SIZE +CYDEV_FASTCLK_PLL_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_CFG0 +CYDEV_FASTCLK_PLL_CFG0 EQU 0x40004220 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_CFG1 +CYDEV_FASTCLK_PLL_CFG1 EQU 0x40004221 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_P +CYDEV_FASTCLK_PLL_P EQU 0x40004222 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_Q +CYDEV_FASTCLK_PLL_Q EQU 0x40004223 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_SR +CYDEV_FASTCLK_PLL_SR EQU 0x40004225 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_BASE +CYDEV_SLOWCLK_BASE EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_SIZE +CYDEV_SLOWCLK_SIZE EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_BASE +CYDEV_SLOWCLK_ILO_BASE EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_SIZE +CYDEV_SLOWCLK_ILO_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_CR0 +CYDEV_SLOWCLK_ILO_CR0 EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_CR1 +CYDEV_SLOWCLK_ILO_CR1 EQU 0x40004301 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_BASE +CYDEV_SLOWCLK_X32_BASE EQU 0x40004308 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_SIZE +CYDEV_SLOWCLK_X32_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_CR +CYDEV_SLOWCLK_X32_CR EQU 0x40004308 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_CFG +CYDEV_SLOWCLK_X32_CFG EQU 0x40004309 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_TST +CYDEV_SLOWCLK_X32_TST EQU 0x4000430a + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_BASE +CYDEV_BOOST_BASE EQU 0x40004320 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_SIZE +CYDEV_BOOST_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_CR0 +CYDEV_BOOST_CR0 EQU 0x40004320 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_CR1 +CYDEV_BOOST_CR1 EQU 0x40004321 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_CR2 +CYDEV_BOOST_CR2 EQU 0x40004322 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_CR3 +CYDEV_BOOST_CR3 EQU 0x40004323 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_SR +CYDEV_BOOST_SR EQU 0x40004324 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_CR4 +CYDEV_BOOST_CR4 EQU 0x40004325 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_SR2 +CYDEV_BOOST_SR2 EQU 0x40004326 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_BASE +CYDEV_PWRSYS_BASE EQU 0x40004330 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_SIZE +CYDEV_PWRSYS_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_CR0 +CYDEV_PWRSYS_CR0 EQU 0x40004330 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_CR1 +CYDEV_PWRSYS_CR1 EQU 0x40004331 + ENDIF + IF :LNOT::DEF:CYDEV_PM_BASE +CYDEV_PM_BASE EQU 0x40004380 + ENDIF + IF :LNOT::DEF:CYDEV_PM_SIZE +CYDEV_PM_SIZE EQU 0x00000057 + ENDIF + IF :LNOT::DEF:CYDEV_PM_TW_CFG0 +CYDEV_PM_TW_CFG0 EQU 0x40004380 + ENDIF + IF :LNOT::DEF:CYDEV_PM_TW_CFG1 +CYDEV_PM_TW_CFG1 EQU 0x40004381 + ENDIF + IF :LNOT::DEF:CYDEV_PM_TW_CFG2 +CYDEV_PM_TW_CFG2 EQU 0x40004382 + ENDIF + IF :LNOT::DEF:CYDEV_PM_WDT_CFG +CYDEV_PM_WDT_CFG EQU 0x40004383 + ENDIF + IF :LNOT::DEF:CYDEV_PM_WDT_CR +CYDEV_PM_WDT_CR EQU 0x40004384 + ENDIF + IF :LNOT::DEF:CYDEV_PM_INT_SR +CYDEV_PM_INT_SR EQU 0x40004390 + ENDIF + IF :LNOT::DEF:CYDEV_PM_MODE_CFG0 +CYDEV_PM_MODE_CFG0 EQU 0x40004391 + ENDIF + IF :LNOT::DEF:CYDEV_PM_MODE_CFG1 +CYDEV_PM_MODE_CFG1 EQU 0x40004392 + ENDIF + IF :LNOT::DEF:CYDEV_PM_MODE_CSR +CYDEV_PM_MODE_CSR EQU 0x40004393 + ENDIF + IF :LNOT::DEF:CYDEV_PM_USB_CR0 +CYDEV_PM_USB_CR0 EQU 0x40004394 + ENDIF + IF :LNOT::DEF:CYDEV_PM_WAKEUP_CFG0 +CYDEV_PM_WAKEUP_CFG0 EQU 0x40004398 + ENDIF + IF :LNOT::DEF:CYDEV_PM_WAKEUP_CFG1 +CYDEV_PM_WAKEUP_CFG1 EQU 0x40004399 + ENDIF + IF :LNOT::DEF:CYDEV_PM_WAKEUP_CFG2 +CYDEV_PM_WAKEUP_CFG2 EQU 0x4000439a + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_BASE +CYDEV_PM_ACT_BASE EQU 0x400043a0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_SIZE +CYDEV_PM_ACT_SIZE EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG0 +CYDEV_PM_ACT_CFG0 EQU 0x400043a0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG1 +CYDEV_PM_ACT_CFG1 EQU 0x400043a1 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG2 +CYDEV_PM_ACT_CFG2 EQU 0x400043a2 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG3 +CYDEV_PM_ACT_CFG3 EQU 0x400043a3 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG4 +CYDEV_PM_ACT_CFG4 EQU 0x400043a4 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG5 +CYDEV_PM_ACT_CFG5 EQU 0x400043a5 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG6 +CYDEV_PM_ACT_CFG6 EQU 0x400043a6 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG7 +CYDEV_PM_ACT_CFG7 EQU 0x400043a7 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG8 +CYDEV_PM_ACT_CFG8 EQU 0x400043a8 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG9 +CYDEV_PM_ACT_CFG9 EQU 0x400043a9 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG10 +CYDEV_PM_ACT_CFG10 EQU 0x400043aa + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG11 +CYDEV_PM_ACT_CFG11 EQU 0x400043ab + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG12 +CYDEV_PM_ACT_CFG12 EQU 0x400043ac + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG13 +CYDEV_PM_ACT_CFG13 EQU 0x400043ad + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_BASE +CYDEV_PM_STBY_BASE EQU 0x400043b0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_SIZE +CYDEV_PM_STBY_SIZE EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG0 +CYDEV_PM_STBY_CFG0 EQU 0x400043b0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG1 +CYDEV_PM_STBY_CFG1 EQU 0x400043b1 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG2 +CYDEV_PM_STBY_CFG2 EQU 0x400043b2 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG3 +CYDEV_PM_STBY_CFG3 EQU 0x400043b3 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG4 +CYDEV_PM_STBY_CFG4 EQU 0x400043b4 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG5 +CYDEV_PM_STBY_CFG5 EQU 0x400043b5 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG6 +CYDEV_PM_STBY_CFG6 EQU 0x400043b6 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG7 +CYDEV_PM_STBY_CFG7 EQU 0x400043b7 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG8 +CYDEV_PM_STBY_CFG8 EQU 0x400043b8 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG9 +CYDEV_PM_STBY_CFG9 EQU 0x400043b9 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG10 +CYDEV_PM_STBY_CFG10 EQU 0x400043ba + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG11 +CYDEV_PM_STBY_CFG11 EQU 0x400043bb + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG12 +CYDEV_PM_STBY_CFG12 EQU 0x400043bc + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG13 +CYDEV_PM_STBY_CFG13 EQU 0x400043bd + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_BASE +CYDEV_PM_AVAIL_BASE EQU 0x400043c0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SIZE +CYDEV_PM_AVAIL_SIZE EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR0 +CYDEV_PM_AVAIL_CR0 EQU 0x400043c0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR1 +CYDEV_PM_AVAIL_CR1 EQU 0x400043c1 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR2 +CYDEV_PM_AVAIL_CR2 EQU 0x400043c2 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR3 +CYDEV_PM_AVAIL_CR3 EQU 0x400043c3 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR4 +CYDEV_PM_AVAIL_CR4 EQU 0x400043c4 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR5 +CYDEV_PM_AVAIL_CR5 EQU 0x400043c5 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR6 +CYDEV_PM_AVAIL_CR6 EQU 0x400043c6 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR0 +CYDEV_PM_AVAIL_SR0 EQU 0x400043d0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR1 +CYDEV_PM_AVAIL_SR1 EQU 0x400043d1 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR2 +CYDEV_PM_AVAIL_SR2 EQU 0x400043d2 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR3 +CYDEV_PM_AVAIL_SR3 EQU 0x400043d3 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR4 +CYDEV_PM_AVAIL_SR4 EQU 0x400043d4 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR5 +CYDEV_PM_AVAIL_SR5 EQU 0x400043d5 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR6 +CYDEV_PM_AVAIL_SR6 EQU 0x400043d6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_BASE +CYDEV_PICU_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SIZE +CYDEV_PICU_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_BASE +CYDEV_PICU_INTTYPE_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_SIZE +CYDEV_PICU_INTTYPE_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_BASE +CYDEV_PICU_INTTYPE_PICU0_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_SIZE +CYDEV_PICU_INTTYPE_PICU0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE0 EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE1 EQU 0x40004501 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE2 EQU 0x40004502 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE3 EQU 0x40004503 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE4 EQU 0x40004504 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE5 EQU 0x40004505 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE6 EQU 0x40004506 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE7 EQU 0x40004507 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_BASE +CYDEV_PICU_INTTYPE_PICU1_BASE EQU 0x40004508 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_SIZE +CYDEV_PICU_INTTYPE_PICU1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE0 EQU 0x40004508 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE1 EQU 0x40004509 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE2 EQU 0x4000450a + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE3 EQU 0x4000450b + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE4 EQU 0x4000450c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE5 EQU 0x4000450d + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE6 EQU 0x4000450e + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE7 EQU 0x4000450f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_BASE +CYDEV_PICU_INTTYPE_PICU2_BASE EQU 0x40004510 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_SIZE +CYDEV_PICU_INTTYPE_PICU2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE0 EQU 0x40004510 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE1 EQU 0x40004511 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE2 EQU 0x40004512 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE3 EQU 0x40004513 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE4 EQU 0x40004514 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE5 EQU 0x40004515 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE6 EQU 0x40004516 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE7 EQU 0x40004517 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_BASE +CYDEV_PICU_INTTYPE_PICU3_BASE EQU 0x40004518 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_SIZE +CYDEV_PICU_INTTYPE_PICU3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE0 EQU 0x40004518 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE1 EQU 0x40004519 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE2 EQU 0x4000451a + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE3 EQU 0x4000451b + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE4 EQU 0x4000451c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE5 EQU 0x4000451d + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE6 EQU 0x4000451e + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE7 EQU 0x4000451f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_BASE +CYDEV_PICU_INTTYPE_PICU4_BASE EQU 0x40004520 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_SIZE +CYDEV_PICU_INTTYPE_PICU4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE0 EQU 0x40004520 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE1 EQU 0x40004521 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE2 EQU 0x40004522 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE3 EQU 0x40004523 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE4 EQU 0x40004524 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE5 EQU 0x40004525 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE6 EQU 0x40004526 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE7 EQU 0x40004527 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_BASE +CYDEV_PICU_INTTYPE_PICU5_BASE EQU 0x40004528 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_SIZE +CYDEV_PICU_INTTYPE_PICU5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE0 EQU 0x40004528 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE1 EQU 0x40004529 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE2 EQU 0x4000452a + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE3 EQU 0x4000452b + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE4 EQU 0x4000452c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE5 EQU 0x4000452d + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE6 EQU 0x4000452e + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE7 EQU 0x4000452f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_BASE +CYDEV_PICU_INTTYPE_PICU6_BASE EQU 0x40004530 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_SIZE +CYDEV_PICU_INTTYPE_PICU6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE0 EQU 0x40004530 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE1 EQU 0x40004531 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE2 EQU 0x40004532 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE3 EQU 0x40004533 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE4 EQU 0x40004534 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE5 EQU 0x40004535 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE6 EQU 0x40004536 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE7 EQU 0x40004537 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_BASE +CYDEV_PICU_INTTYPE_PICU12_BASE EQU 0x40004560 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_SIZE +CYDEV_PICU_INTTYPE_PICU12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE0 EQU 0x40004560 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE1 EQU 0x40004561 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE2 EQU 0x40004562 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE3 EQU 0x40004563 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE4 EQU 0x40004564 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE5 EQU 0x40004565 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE6 EQU 0x40004566 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE7 EQU 0x40004567 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_BASE +CYDEV_PICU_INTTYPE_PICU15_BASE EQU 0x40004578 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_SIZE +CYDEV_PICU_INTTYPE_PICU15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE0 EQU 0x40004578 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE1 EQU 0x40004579 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE2 EQU 0x4000457a + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE3 EQU 0x4000457b + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE4 EQU 0x4000457c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE5 EQU 0x4000457d + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE6 EQU 0x4000457e + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE7 EQU 0x4000457f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_BASE +CYDEV_PICU_STAT_BASE EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_SIZE +CYDEV_PICU_STAT_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_BASE +CYDEV_PICU_STAT_PICU0_BASE EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_SIZE +CYDEV_PICU_STAT_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_INTSTAT +CYDEV_PICU_STAT_PICU0_INTSTAT EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_BASE +CYDEV_PICU_STAT_PICU1_BASE EQU 0x40004581 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_SIZE +CYDEV_PICU_STAT_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_INTSTAT +CYDEV_PICU_STAT_PICU1_INTSTAT EQU 0x40004581 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_BASE +CYDEV_PICU_STAT_PICU2_BASE EQU 0x40004582 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_SIZE +CYDEV_PICU_STAT_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_INTSTAT +CYDEV_PICU_STAT_PICU2_INTSTAT EQU 0x40004582 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_BASE +CYDEV_PICU_STAT_PICU3_BASE EQU 0x40004583 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_SIZE +CYDEV_PICU_STAT_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_INTSTAT +CYDEV_PICU_STAT_PICU3_INTSTAT EQU 0x40004583 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_BASE +CYDEV_PICU_STAT_PICU4_BASE EQU 0x40004584 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_SIZE +CYDEV_PICU_STAT_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_INTSTAT +CYDEV_PICU_STAT_PICU4_INTSTAT EQU 0x40004584 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_BASE +CYDEV_PICU_STAT_PICU5_BASE EQU 0x40004585 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_SIZE +CYDEV_PICU_STAT_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_INTSTAT +CYDEV_PICU_STAT_PICU5_INTSTAT EQU 0x40004585 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_BASE +CYDEV_PICU_STAT_PICU6_BASE EQU 0x40004586 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_SIZE +CYDEV_PICU_STAT_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_INTSTAT +CYDEV_PICU_STAT_PICU6_INTSTAT EQU 0x40004586 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_BASE +CYDEV_PICU_STAT_PICU12_BASE EQU 0x4000458c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_SIZE +CYDEV_PICU_STAT_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_INTSTAT +CYDEV_PICU_STAT_PICU12_INTSTAT EQU 0x4000458c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_BASE +CYDEV_PICU_STAT_PICU15_BASE EQU 0x4000458f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_SIZE +CYDEV_PICU_STAT_PICU15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_INTSTAT +CYDEV_PICU_STAT_PICU15_INTSTAT EQU 0x4000458f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_BASE +CYDEV_PICU_SNAP_BASE EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_SIZE +CYDEV_PICU_SNAP_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_BASE +CYDEV_PICU_SNAP_PICU0_BASE EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_SIZE +CYDEV_PICU_SNAP_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_SNAP +CYDEV_PICU_SNAP_PICU0_SNAP EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_BASE +CYDEV_PICU_SNAP_PICU1_BASE EQU 0x40004591 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_SIZE +CYDEV_PICU_SNAP_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_SNAP +CYDEV_PICU_SNAP_PICU1_SNAP EQU 0x40004591 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_BASE +CYDEV_PICU_SNAP_PICU2_BASE EQU 0x40004592 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_SIZE +CYDEV_PICU_SNAP_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_SNAP +CYDEV_PICU_SNAP_PICU2_SNAP EQU 0x40004592 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_BASE +CYDEV_PICU_SNAP_PICU3_BASE EQU 0x40004593 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_SIZE +CYDEV_PICU_SNAP_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_SNAP +CYDEV_PICU_SNAP_PICU3_SNAP EQU 0x40004593 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_BASE +CYDEV_PICU_SNAP_PICU4_BASE EQU 0x40004594 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_SIZE +CYDEV_PICU_SNAP_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_SNAP +CYDEV_PICU_SNAP_PICU4_SNAP EQU 0x40004594 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_BASE +CYDEV_PICU_SNAP_PICU5_BASE EQU 0x40004595 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_SIZE +CYDEV_PICU_SNAP_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_SNAP +CYDEV_PICU_SNAP_PICU5_SNAP EQU 0x40004595 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_BASE +CYDEV_PICU_SNAP_PICU6_BASE EQU 0x40004596 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_SIZE +CYDEV_PICU_SNAP_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_SNAP +CYDEV_PICU_SNAP_PICU6_SNAP EQU 0x40004596 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_BASE +CYDEV_PICU_SNAP_PICU12_BASE EQU 0x4000459c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_SIZE +CYDEV_PICU_SNAP_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_SNAP +CYDEV_PICU_SNAP_PICU12_SNAP EQU 0x4000459c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_BASE +CYDEV_PICU_SNAP_PICU_15_BASE EQU 0x4000459f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_SIZE +CYDEV_PICU_SNAP_PICU_15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_SNAP_15 +CYDEV_PICU_SNAP_PICU_15_SNAP_15 EQU 0x4000459f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_BASE +CYDEV_PICU_DISABLE_COR_BASE EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_SIZE +CYDEV_PICU_DISABLE_COR_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_BASE +CYDEV_PICU_DISABLE_COR_PICU0_BASE EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_SIZE +CYDEV_PICU_DISABLE_COR_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_BASE +CYDEV_PICU_DISABLE_COR_PICU1_BASE EQU 0x400045a1 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_SIZE +CYDEV_PICU_DISABLE_COR_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR EQU 0x400045a1 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_BASE +CYDEV_PICU_DISABLE_COR_PICU2_BASE EQU 0x400045a2 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_SIZE +CYDEV_PICU_DISABLE_COR_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR EQU 0x400045a2 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_BASE +CYDEV_PICU_DISABLE_COR_PICU3_BASE EQU 0x400045a3 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_SIZE +CYDEV_PICU_DISABLE_COR_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR EQU 0x400045a3 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_BASE +CYDEV_PICU_DISABLE_COR_PICU4_BASE EQU 0x400045a4 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_SIZE +CYDEV_PICU_DISABLE_COR_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR EQU 0x400045a4 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_BASE +CYDEV_PICU_DISABLE_COR_PICU5_BASE EQU 0x400045a5 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_SIZE +CYDEV_PICU_DISABLE_COR_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR EQU 0x400045a5 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_BASE +CYDEV_PICU_DISABLE_COR_PICU6_BASE EQU 0x400045a6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_SIZE +CYDEV_PICU_DISABLE_COR_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR EQU 0x400045a6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_BASE +CYDEV_PICU_DISABLE_COR_PICU12_BASE EQU 0x400045ac + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_SIZE +CYDEV_PICU_DISABLE_COR_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR EQU 0x400045ac + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_BASE +CYDEV_PICU_DISABLE_COR_PICU15_BASE EQU 0x400045af + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_SIZE +CYDEV_PICU_DISABLE_COR_PICU15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR EQU 0x400045af + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_BASE +CYDEV_MFGCFG_BASE EQU 0x40004600 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_SIZE +CYDEV_MFGCFG_SIZE EQU 0x000000ed + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_BASE +CYDEV_MFGCFG_ANAIF_BASE EQU 0x40004600 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SIZE +CYDEV_MFGCFG_ANAIF_SIZE EQU 0x00000038 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_BASE +CYDEV_MFGCFG_ANAIF_DAC0_BASE EQU 0x40004608 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_SIZE +CYDEV_MFGCFG_ANAIF_DAC0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_TR +CYDEV_MFGCFG_ANAIF_DAC0_TR EQU 0x40004608 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_BASE +CYDEV_MFGCFG_ANAIF_DAC1_BASE EQU 0x40004609 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_SIZE +CYDEV_MFGCFG_ANAIF_DAC1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_TR +CYDEV_MFGCFG_ANAIF_DAC1_TR EQU 0x40004609 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_BASE +CYDEV_MFGCFG_ANAIF_DAC2_BASE EQU 0x4000460a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_SIZE +CYDEV_MFGCFG_ANAIF_DAC2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_TR +CYDEV_MFGCFG_ANAIF_DAC2_TR EQU 0x4000460a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_BASE +CYDEV_MFGCFG_ANAIF_DAC3_BASE EQU 0x4000460b + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_SIZE +CYDEV_MFGCFG_ANAIF_DAC3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_TR +CYDEV_MFGCFG_ANAIF_DAC3_TR EQU 0x4000460b + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE EQU 0x40004610 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0 +CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0 EQU 0x40004610 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE EQU 0x40004611 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0 +CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0 EQU 0x40004611 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE EQU 0x40004612 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0 +CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0 EQU 0x40004612 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_BASE +CYDEV_MFGCFG_ANAIF_SAR0_BASE EQU 0x40004614 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_SIZE +CYDEV_MFGCFG_ANAIF_SAR0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_TR0 +CYDEV_MFGCFG_ANAIF_SAR0_TR0 EQU 0x40004614 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_BASE +CYDEV_MFGCFG_ANAIF_SAR1_BASE EQU 0x40004616 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_SIZE +CYDEV_MFGCFG_ANAIF_SAR1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_TR0 +CYDEV_MFGCFG_ANAIF_SAR1_TR0 EQU 0x40004616 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_BASE +CYDEV_MFGCFG_ANAIF_OPAMP0_BASE EQU 0x40004620 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_TR0 +CYDEV_MFGCFG_ANAIF_OPAMP0_TR0 EQU 0x40004620 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_TR1 +CYDEV_MFGCFG_ANAIF_OPAMP0_TR1 EQU 0x40004621 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_BASE +CYDEV_MFGCFG_ANAIF_OPAMP1_BASE EQU 0x40004622 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_TR0 +CYDEV_MFGCFG_ANAIF_OPAMP1_TR0 EQU 0x40004622 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_TR1 +CYDEV_MFGCFG_ANAIF_OPAMP1_TR1 EQU 0x40004623 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_BASE +CYDEV_MFGCFG_ANAIF_OPAMP2_BASE EQU 0x40004624 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_TR0 +CYDEV_MFGCFG_ANAIF_OPAMP2_TR0 EQU 0x40004624 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_TR1 +CYDEV_MFGCFG_ANAIF_OPAMP2_TR1 EQU 0x40004625 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_BASE +CYDEV_MFGCFG_ANAIF_OPAMP3_BASE EQU 0x40004626 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_TR0 +CYDEV_MFGCFG_ANAIF_OPAMP3_TR0 EQU 0x40004626 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_TR1 +CYDEV_MFGCFG_ANAIF_OPAMP3_TR1 EQU 0x40004627 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_BASE +CYDEV_MFGCFG_ANAIF_CMP0_BASE EQU 0x40004630 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_SIZE +CYDEV_MFGCFG_ANAIF_CMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_TR0 +CYDEV_MFGCFG_ANAIF_CMP0_TR0 EQU 0x40004630 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_TR1 +CYDEV_MFGCFG_ANAIF_CMP0_TR1 EQU 0x40004631 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_BASE +CYDEV_MFGCFG_ANAIF_CMP1_BASE EQU 0x40004632 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_SIZE +CYDEV_MFGCFG_ANAIF_CMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_TR0 +CYDEV_MFGCFG_ANAIF_CMP1_TR0 EQU 0x40004632 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_TR1 +CYDEV_MFGCFG_ANAIF_CMP1_TR1 EQU 0x40004633 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_BASE +CYDEV_MFGCFG_ANAIF_CMP2_BASE EQU 0x40004634 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_SIZE +CYDEV_MFGCFG_ANAIF_CMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_TR0 +CYDEV_MFGCFG_ANAIF_CMP2_TR0 EQU 0x40004634 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_TR1 +CYDEV_MFGCFG_ANAIF_CMP2_TR1 EQU 0x40004635 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_BASE +CYDEV_MFGCFG_ANAIF_CMP3_BASE EQU 0x40004636 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_SIZE +CYDEV_MFGCFG_ANAIF_CMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_TR0 +CYDEV_MFGCFG_ANAIF_CMP3_TR0 EQU 0x40004636 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_TR1 +CYDEV_MFGCFG_ANAIF_CMP3_TR1 EQU 0x40004637 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BASE +CYDEV_MFGCFG_PWRSYS_BASE EQU 0x40004680 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_SIZE +CYDEV_MFGCFG_PWRSYS_SIZE EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_HIB_TR0 +CYDEV_MFGCFG_PWRSYS_HIB_TR0 EQU 0x40004680 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_HIB_TR1 +CYDEV_MFGCFG_PWRSYS_HIB_TR1 EQU 0x40004681 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_I2C_TR +CYDEV_MFGCFG_PWRSYS_I2C_TR EQU 0x40004682 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_SLP_TR +CYDEV_MFGCFG_PWRSYS_SLP_TR EQU 0x40004683 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BUZZ_TR +CYDEV_MFGCFG_PWRSYS_BUZZ_TR EQU 0x40004684 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_WAKE_TR0 +CYDEV_MFGCFG_PWRSYS_WAKE_TR0 EQU 0x40004685 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_WAKE_TR1 +CYDEV_MFGCFG_PWRSYS_WAKE_TR1 EQU 0x40004686 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BREF_TR +CYDEV_MFGCFG_PWRSYS_BREF_TR EQU 0x40004687 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BG_TR +CYDEV_MFGCFG_PWRSYS_BG_TR EQU 0x40004688 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_WAKE_TR2 +CYDEV_MFGCFG_PWRSYS_WAKE_TR2 EQU 0x40004689 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_WAKE_TR3 +CYDEV_MFGCFG_PWRSYS_WAKE_TR3 EQU 0x4000468a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_BASE +CYDEV_MFGCFG_ILO_BASE EQU 0x40004690 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_SIZE +CYDEV_MFGCFG_ILO_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_TR0 +CYDEV_MFGCFG_ILO_TR0 EQU 0x40004690 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_TR1 +CYDEV_MFGCFG_ILO_TR1 EQU 0x40004691 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_X32_BASE +CYDEV_MFGCFG_X32_BASE EQU 0x40004698 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_X32_SIZE +CYDEV_MFGCFG_X32_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_X32_TR +CYDEV_MFGCFG_X32_TR EQU 0x40004698 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_BASE +CYDEV_MFGCFG_IMO_BASE EQU 0x400046a0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_SIZE +CYDEV_MFGCFG_IMO_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_TR0 +CYDEV_MFGCFG_IMO_TR0 EQU 0x400046a0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_TR1 +CYDEV_MFGCFG_IMO_TR1 EQU 0x400046a1 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_GAIN +CYDEV_MFGCFG_IMO_GAIN EQU 0x400046a2 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_C36M +CYDEV_MFGCFG_IMO_C36M EQU 0x400046a3 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_TR2 +CYDEV_MFGCFG_IMO_TR2 EQU 0x400046a4 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_BASE +CYDEV_MFGCFG_XMHZ_BASE EQU 0x400046a8 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_SIZE +CYDEV_MFGCFG_XMHZ_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_TR +CYDEV_MFGCFG_XMHZ_TR EQU 0x400046a8 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_DLY +CYDEV_MFGCFG_DLY EQU 0x400046c0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_BASE +CYDEV_MFGCFG_MLOGIC_BASE EQU 0x400046e0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SIZE +CYDEV_MFGCFG_MLOGIC_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_DMPSTR +CYDEV_MFGCFG_MLOGIC_DMPSTR EQU 0x400046e2 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_BASE +CYDEV_MFGCFG_MLOGIC_SEG_BASE EQU 0x400046e4 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_SIZE +CYDEV_MFGCFG_MLOGIC_SEG_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_CR +CYDEV_MFGCFG_MLOGIC_SEG_CR EQU 0x400046e4 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_CFG0 +CYDEV_MFGCFG_MLOGIC_SEG_CFG0 EQU 0x400046e5 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_DEBUG +CYDEV_MFGCFG_MLOGIC_DEBUG EQU 0x400046e8 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE +CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE EQU 0x400046ea + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE +CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR +CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR EQU 0x400046ea + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_REV_ID +CYDEV_MFGCFG_MLOGIC_REV_ID EQU 0x400046ec + ENDIF + IF :LNOT::DEF:CYDEV_RESET_BASE +CYDEV_RESET_BASE EQU 0x400046f0 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SIZE +CYDEV_RESET_SIZE EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYDEV_RESET_IPOR_CR0 +CYDEV_RESET_IPOR_CR0 EQU 0x400046f0 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_IPOR_CR1 +CYDEV_RESET_IPOR_CR1 EQU 0x400046f1 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_IPOR_CR2 +CYDEV_RESET_IPOR_CR2 EQU 0x400046f2 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_IPOR_CR3 +CYDEV_RESET_IPOR_CR3 EQU 0x400046f3 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR0 +CYDEV_RESET_CR0 EQU 0x400046f4 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR1 +CYDEV_RESET_CR1 EQU 0x400046f5 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR2 +CYDEV_RESET_CR2 EQU 0x400046f6 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR3 +CYDEV_RESET_CR3 EQU 0x400046f7 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR4 +CYDEV_RESET_CR4 EQU 0x400046f8 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR5 +CYDEV_RESET_CR5 EQU 0x400046f9 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SR0 +CYDEV_RESET_SR0 EQU 0x400046fa + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SR1 +CYDEV_RESET_SR1 EQU 0x400046fb + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SR2 +CYDEV_RESET_SR2 EQU 0x400046fc + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SR3 +CYDEV_RESET_SR3 EQU 0x400046fd + ENDIF + IF :LNOT::DEF:CYDEV_RESET_TR +CYDEV_RESET_TR EQU 0x400046fe + ENDIF + IF :LNOT::DEF:CYDEV_SPC_BASE +CYDEV_SPC_BASE EQU 0x40004700 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_SIZE +CYDEV_SPC_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_FM_EE_CR +CYDEV_SPC_FM_EE_CR EQU 0x40004700 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_FM_EE_WAKE_CNT +CYDEV_SPC_FM_EE_WAKE_CNT EQU 0x40004701 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_EE_SCR +CYDEV_SPC_EE_SCR EQU 0x40004702 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_EE_ERR +CYDEV_SPC_EE_ERR EQU 0x40004703 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_CPU_DATA +CYDEV_SPC_CPU_DATA EQU 0x40004720 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMA_DATA +CYDEV_SPC_DMA_DATA EQU 0x40004721 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_SR +CYDEV_SPC_SR EQU 0x40004722 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_CR +CYDEV_SPC_CR EQU 0x40004723 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_BASE +CYDEV_SPC_DMM_MAP_BASE EQU 0x40004780 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_SIZE +CYDEV_SPC_DMM_MAP_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_SRAM_MBASE +CYDEV_SPC_DMM_MAP_SRAM_MBASE EQU 0x40004780 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_SRAM_MSIZE +CYDEV_SPC_DMM_MAP_SRAM_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_BASE +CYDEV_CACHE_BASE EQU 0x40004800 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_SIZE +CYDEV_CACHE_SIZE EQU 0x0000009c + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_CC_CTL +CYDEV_CACHE_CC_CTL EQU 0x40004800 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_ECC_CORR +CYDEV_CACHE_ECC_CORR EQU 0x40004880 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_ECC_ERR +CYDEV_CACHE_ECC_ERR EQU 0x40004888 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_FLASH_ERR +CYDEV_CACHE_FLASH_ERR EQU 0x40004890 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_HITMISS +CYDEV_CACHE_HITMISS EQU 0x40004898 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_BASE +CYDEV_I2C_BASE EQU 0x40004900 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_SIZE +CYDEV_I2C_SIZE EQU 0x000000e1 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_XCFG +CYDEV_I2C_XCFG EQU 0x400049c8 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_ADR +CYDEV_I2C_ADR EQU 0x400049ca + ENDIF + IF :LNOT::DEF:CYDEV_I2C_CFG +CYDEV_I2C_CFG EQU 0x400049d6 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_CSR +CYDEV_I2C_CSR EQU 0x400049d7 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_D +CYDEV_I2C_D EQU 0x400049d8 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_MCSR +CYDEV_I2C_MCSR EQU 0x400049d9 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_CLK_DIV1 +CYDEV_I2C_CLK_DIV1 EQU 0x400049db + ENDIF + IF :LNOT::DEF:CYDEV_I2C_CLK_DIV2 +CYDEV_I2C_CLK_DIV2 EQU 0x400049dc + ENDIF + IF :LNOT::DEF:CYDEV_I2C_TMOUT_CSR +CYDEV_I2C_TMOUT_CSR EQU 0x400049dd + ENDIF + IF :LNOT::DEF:CYDEV_I2C_TMOUT_SR +CYDEV_I2C_TMOUT_SR EQU 0x400049de + ENDIF + IF :LNOT::DEF:CYDEV_I2C_TMOUT_CFG0 +CYDEV_I2C_TMOUT_CFG0 EQU 0x400049df + ENDIF + IF :LNOT::DEF:CYDEV_I2C_TMOUT_CFG1 +CYDEV_I2C_TMOUT_CFG1 EQU 0x400049e0 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_BASE +CYDEV_DEC_BASE EQU 0x40004e00 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_SIZE +CYDEV_DEC_SIZE EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_CR +CYDEV_DEC_CR EQU 0x40004e00 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_SR +CYDEV_DEC_SR EQU 0x40004e01 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_SHIFT1 +CYDEV_DEC_SHIFT1 EQU 0x40004e02 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_SHIFT2 +CYDEV_DEC_SHIFT2 EQU 0x40004e03 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_DR2 +CYDEV_DEC_DR2 EQU 0x40004e04 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_DR2H +CYDEV_DEC_DR2H EQU 0x40004e05 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_DR1 +CYDEV_DEC_DR1 EQU 0x40004e06 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OCOR +CYDEV_DEC_OCOR EQU 0x40004e08 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OCORM +CYDEV_DEC_OCORM EQU 0x40004e09 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OCORH +CYDEV_DEC_OCORH EQU 0x40004e0a + ENDIF + IF :LNOT::DEF:CYDEV_DEC_GCOR +CYDEV_DEC_GCOR EQU 0x40004e0c + ENDIF + IF :LNOT::DEF:CYDEV_DEC_GCORH +CYDEV_DEC_GCORH EQU 0x40004e0d + ENDIF + IF :LNOT::DEF:CYDEV_DEC_GVAL +CYDEV_DEC_GVAL EQU 0x40004e0e + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OUTSAMP +CYDEV_DEC_OUTSAMP EQU 0x40004e10 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OUTSAMPM +CYDEV_DEC_OUTSAMPM EQU 0x40004e11 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OUTSAMPH +CYDEV_DEC_OUTSAMPH EQU 0x40004e12 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OUTSAMPS +CYDEV_DEC_OUTSAMPS EQU 0x40004e13 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_COHER +CYDEV_DEC_COHER EQU 0x40004e14 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_BASE +CYDEV_TMR0_BASE EQU 0x40004f00 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_SIZE +CYDEV_TMR0_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CFG0 +CYDEV_TMR0_CFG0 EQU 0x40004f00 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CFG1 +CYDEV_TMR0_CFG1 EQU 0x40004f01 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CFG2 +CYDEV_TMR0_CFG2 EQU 0x40004f02 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_SR0 +CYDEV_TMR0_SR0 EQU 0x40004f03 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_PER0 +CYDEV_TMR0_PER0 EQU 0x40004f04 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_PER1 +CYDEV_TMR0_PER1 EQU 0x40004f05 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CNT_CMP0 +CYDEV_TMR0_CNT_CMP0 EQU 0x40004f06 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CNT_CMP1 +CYDEV_TMR0_CNT_CMP1 EQU 0x40004f07 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CAP0 +CYDEV_TMR0_CAP0 EQU 0x40004f08 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CAP1 +CYDEV_TMR0_CAP1 EQU 0x40004f09 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_RT0 +CYDEV_TMR0_RT0 EQU 0x40004f0a + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_RT1 +CYDEV_TMR0_RT1 EQU 0x40004f0b + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_BASE +CYDEV_TMR1_BASE EQU 0x40004f0c + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_SIZE +CYDEV_TMR1_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CFG0 +CYDEV_TMR1_CFG0 EQU 0x40004f0c + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CFG1 +CYDEV_TMR1_CFG1 EQU 0x40004f0d + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CFG2 +CYDEV_TMR1_CFG2 EQU 0x40004f0e + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_SR0 +CYDEV_TMR1_SR0 EQU 0x40004f0f + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_PER0 +CYDEV_TMR1_PER0 EQU 0x40004f10 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_PER1 +CYDEV_TMR1_PER1 EQU 0x40004f11 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CNT_CMP0 +CYDEV_TMR1_CNT_CMP0 EQU 0x40004f12 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CNT_CMP1 +CYDEV_TMR1_CNT_CMP1 EQU 0x40004f13 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CAP0 +CYDEV_TMR1_CAP0 EQU 0x40004f14 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CAP1 +CYDEV_TMR1_CAP1 EQU 0x40004f15 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_RT0 +CYDEV_TMR1_RT0 EQU 0x40004f16 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_RT1 +CYDEV_TMR1_RT1 EQU 0x40004f17 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_BASE +CYDEV_TMR2_BASE EQU 0x40004f18 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_SIZE +CYDEV_TMR2_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CFG0 +CYDEV_TMR2_CFG0 EQU 0x40004f18 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CFG1 +CYDEV_TMR2_CFG1 EQU 0x40004f19 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CFG2 +CYDEV_TMR2_CFG2 EQU 0x40004f1a + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_SR0 +CYDEV_TMR2_SR0 EQU 0x40004f1b + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_PER0 +CYDEV_TMR2_PER0 EQU 0x40004f1c + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_PER1 +CYDEV_TMR2_PER1 EQU 0x40004f1d + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CNT_CMP0 +CYDEV_TMR2_CNT_CMP0 EQU 0x40004f1e + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CNT_CMP1 +CYDEV_TMR2_CNT_CMP1 EQU 0x40004f1f + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CAP0 +CYDEV_TMR2_CAP0 EQU 0x40004f20 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CAP1 +CYDEV_TMR2_CAP1 EQU 0x40004f21 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_RT0 +CYDEV_TMR2_RT0 EQU 0x40004f22 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_RT1 +CYDEV_TMR2_RT1 EQU 0x40004f23 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_BASE +CYDEV_TMR3_BASE EQU 0x40004f24 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_SIZE +CYDEV_TMR3_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CFG0 +CYDEV_TMR3_CFG0 EQU 0x40004f24 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CFG1 +CYDEV_TMR3_CFG1 EQU 0x40004f25 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CFG2 +CYDEV_TMR3_CFG2 EQU 0x40004f26 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_SR0 +CYDEV_TMR3_SR0 EQU 0x40004f27 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_PER0 +CYDEV_TMR3_PER0 EQU 0x40004f28 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_PER1 +CYDEV_TMR3_PER1 EQU 0x40004f29 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CNT_CMP0 +CYDEV_TMR3_CNT_CMP0 EQU 0x40004f2a + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CNT_CMP1 +CYDEV_TMR3_CNT_CMP1 EQU 0x40004f2b + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CAP0 +CYDEV_TMR3_CAP0 EQU 0x40004f2c + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CAP1 +CYDEV_TMR3_CAP1 EQU 0x40004f2d + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_RT0 +CYDEV_TMR3_RT0 EQU 0x40004f2e + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_RT1 +CYDEV_TMR3_RT1 EQU 0x40004f2f + ENDIF + IF :LNOT::DEF:CYDEV_IO_BASE +CYDEV_IO_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_SIZE +CYDEV_IO_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_BASE +CYDEV_IO_PC_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_SIZE +CYDEV_IO_PC_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_BASE +CYDEV_IO_PC_PRT0_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_SIZE +CYDEV_IO_PC_PRT0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC0 +CYDEV_IO_PC_PRT0_PC0 EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC1 +CYDEV_IO_PC_PRT0_PC1 EQU 0x40005001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC2 +CYDEV_IO_PC_PRT0_PC2 EQU 0x40005002 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC3 +CYDEV_IO_PC_PRT0_PC3 EQU 0x40005003 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC4 +CYDEV_IO_PC_PRT0_PC4 EQU 0x40005004 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC5 +CYDEV_IO_PC_PRT0_PC5 EQU 0x40005005 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC6 +CYDEV_IO_PC_PRT0_PC6 EQU 0x40005006 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC7 +CYDEV_IO_PC_PRT0_PC7 EQU 0x40005007 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_BASE +CYDEV_IO_PC_PRT1_BASE EQU 0x40005008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_SIZE +CYDEV_IO_PC_PRT1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC0 +CYDEV_IO_PC_PRT1_PC0 EQU 0x40005008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC1 +CYDEV_IO_PC_PRT1_PC1 EQU 0x40005009 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC2 +CYDEV_IO_PC_PRT1_PC2 EQU 0x4000500a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC3 +CYDEV_IO_PC_PRT1_PC3 EQU 0x4000500b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC4 +CYDEV_IO_PC_PRT1_PC4 EQU 0x4000500c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC5 +CYDEV_IO_PC_PRT1_PC5 EQU 0x4000500d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC6 +CYDEV_IO_PC_PRT1_PC6 EQU 0x4000500e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC7 +CYDEV_IO_PC_PRT1_PC7 EQU 0x4000500f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_BASE +CYDEV_IO_PC_PRT2_BASE EQU 0x40005010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_SIZE +CYDEV_IO_PC_PRT2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC0 +CYDEV_IO_PC_PRT2_PC0 EQU 0x40005010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC1 +CYDEV_IO_PC_PRT2_PC1 EQU 0x40005011 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC2 +CYDEV_IO_PC_PRT2_PC2 EQU 0x40005012 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC3 +CYDEV_IO_PC_PRT2_PC3 EQU 0x40005013 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC4 +CYDEV_IO_PC_PRT2_PC4 EQU 0x40005014 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC5 +CYDEV_IO_PC_PRT2_PC5 EQU 0x40005015 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC6 +CYDEV_IO_PC_PRT2_PC6 EQU 0x40005016 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC7 +CYDEV_IO_PC_PRT2_PC7 EQU 0x40005017 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_BASE +CYDEV_IO_PC_PRT3_BASE EQU 0x40005018 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_SIZE +CYDEV_IO_PC_PRT3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC0 +CYDEV_IO_PC_PRT3_PC0 EQU 0x40005018 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC1 +CYDEV_IO_PC_PRT3_PC1 EQU 0x40005019 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC2 +CYDEV_IO_PC_PRT3_PC2 EQU 0x4000501a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC3 +CYDEV_IO_PC_PRT3_PC3 EQU 0x4000501b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC4 +CYDEV_IO_PC_PRT3_PC4 EQU 0x4000501c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC5 +CYDEV_IO_PC_PRT3_PC5 EQU 0x4000501d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC6 +CYDEV_IO_PC_PRT3_PC6 EQU 0x4000501e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC7 +CYDEV_IO_PC_PRT3_PC7 EQU 0x4000501f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_BASE +CYDEV_IO_PC_PRT4_BASE EQU 0x40005020 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_SIZE +CYDEV_IO_PC_PRT4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC0 +CYDEV_IO_PC_PRT4_PC0 EQU 0x40005020 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC1 +CYDEV_IO_PC_PRT4_PC1 EQU 0x40005021 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC2 +CYDEV_IO_PC_PRT4_PC2 EQU 0x40005022 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC3 +CYDEV_IO_PC_PRT4_PC3 EQU 0x40005023 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC4 +CYDEV_IO_PC_PRT4_PC4 EQU 0x40005024 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC5 +CYDEV_IO_PC_PRT4_PC5 EQU 0x40005025 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC6 +CYDEV_IO_PC_PRT4_PC6 EQU 0x40005026 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC7 +CYDEV_IO_PC_PRT4_PC7 EQU 0x40005027 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_BASE +CYDEV_IO_PC_PRT5_BASE EQU 0x40005028 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_SIZE +CYDEV_IO_PC_PRT5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC0 +CYDEV_IO_PC_PRT5_PC0 EQU 0x40005028 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC1 +CYDEV_IO_PC_PRT5_PC1 EQU 0x40005029 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC2 +CYDEV_IO_PC_PRT5_PC2 EQU 0x4000502a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC3 +CYDEV_IO_PC_PRT5_PC3 EQU 0x4000502b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC4 +CYDEV_IO_PC_PRT5_PC4 EQU 0x4000502c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC5 +CYDEV_IO_PC_PRT5_PC5 EQU 0x4000502d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC6 +CYDEV_IO_PC_PRT5_PC6 EQU 0x4000502e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC7 +CYDEV_IO_PC_PRT5_PC7 EQU 0x4000502f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_BASE +CYDEV_IO_PC_PRT6_BASE EQU 0x40005030 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_SIZE +CYDEV_IO_PC_PRT6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC0 +CYDEV_IO_PC_PRT6_PC0 EQU 0x40005030 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC1 +CYDEV_IO_PC_PRT6_PC1 EQU 0x40005031 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC2 +CYDEV_IO_PC_PRT6_PC2 EQU 0x40005032 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC3 +CYDEV_IO_PC_PRT6_PC3 EQU 0x40005033 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC4 +CYDEV_IO_PC_PRT6_PC4 EQU 0x40005034 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC5 +CYDEV_IO_PC_PRT6_PC5 EQU 0x40005035 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC6 +CYDEV_IO_PC_PRT6_PC6 EQU 0x40005036 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC7 +CYDEV_IO_PC_PRT6_PC7 EQU 0x40005037 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_BASE +CYDEV_IO_PC_PRT12_BASE EQU 0x40005060 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_SIZE +CYDEV_IO_PC_PRT12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC0 +CYDEV_IO_PC_PRT12_PC0 EQU 0x40005060 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC1 +CYDEV_IO_PC_PRT12_PC1 EQU 0x40005061 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC2 +CYDEV_IO_PC_PRT12_PC2 EQU 0x40005062 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC3 +CYDEV_IO_PC_PRT12_PC3 EQU 0x40005063 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC4 +CYDEV_IO_PC_PRT12_PC4 EQU 0x40005064 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC5 +CYDEV_IO_PC_PRT12_PC5 EQU 0x40005065 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC6 +CYDEV_IO_PC_PRT12_PC6 EQU 0x40005066 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC7 +CYDEV_IO_PC_PRT12_PC7 EQU 0x40005067 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_BASE +CYDEV_IO_PC_PRT15_BASE EQU 0x40005078 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_SIZE +CYDEV_IO_PC_PRT15_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC0 +CYDEV_IO_PC_PRT15_PC0 EQU 0x40005078 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC1 +CYDEV_IO_PC_PRT15_PC1 EQU 0x40005079 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC2 +CYDEV_IO_PC_PRT15_PC2 EQU 0x4000507a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC3 +CYDEV_IO_PC_PRT15_PC3 EQU 0x4000507b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC4 +CYDEV_IO_PC_PRT15_PC4 EQU 0x4000507c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC5 +CYDEV_IO_PC_PRT15_PC5 EQU 0x4000507d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_BASE +CYDEV_IO_PC_PRT15_7_6_BASE EQU 0x4000507e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_SIZE +CYDEV_IO_PC_PRT15_7_6_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_PC0 +CYDEV_IO_PC_PRT15_7_6_PC0 EQU 0x4000507e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_PC1 +CYDEV_IO_PC_PRT15_7_6_PC1 EQU 0x4000507f + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_BASE +CYDEV_IO_DR_BASE EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_SIZE +CYDEV_IO_DR_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT0_BASE +CYDEV_IO_DR_PRT0_BASE EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT0_SIZE +CYDEV_IO_DR_PRT0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT0_DR_ALIAS +CYDEV_IO_DR_PRT0_DR_ALIAS EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT1_BASE +CYDEV_IO_DR_PRT1_BASE EQU 0x40005081 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT1_SIZE +CYDEV_IO_DR_PRT1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT1_DR_ALIAS +CYDEV_IO_DR_PRT1_DR_ALIAS EQU 0x40005081 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT2_BASE +CYDEV_IO_DR_PRT2_BASE EQU 0x40005082 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT2_SIZE +CYDEV_IO_DR_PRT2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT2_DR_ALIAS +CYDEV_IO_DR_PRT2_DR_ALIAS EQU 0x40005082 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT3_BASE +CYDEV_IO_DR_PRT3_BASE EQU 0x40005083 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT3_SIZE +CYDEV_IO_DR_PRT3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT3_DR_ALIAS +CYDEV_IO_DR_PRT3_DR_ALIAS EQU 0x40005083 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT4_BASE +CYDEV_IO_DR_PRT4_BASE EQU 0x40005084 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT4_SIZE +CYDEV_IO_DR_PRT4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT4_DR_ALIAS +CYDEV_IO_DR_PRT4_DR_ALIAS EQU 0x40005084 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT5_BASE +CYDEV_IO_DR_PRT5_BASE EQU 0x40005085 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT5_SIZE +CYDEV_IO_DR_PRT5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT5_DR_ALIAS +CYDEV_IO_DR_PRT5_DR_ALIAS EQU 0x40005085 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT6_BASE +CYDEV_IO_DR_PRT6_BASE EQU 0x40005086 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT6_SIZE +CYDEV_IO_DR_PRT6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT6_DR_ALIAS +CYDEV_IO_DR_PRT6_DR_ALIAS EQU 0x40005086 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT12_BASE +CYDEV_IO_DR_PRT12_BASE EQU 0x4000508c + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT12_SIZE +CYDEV_IO_DR_PRT12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT12_DR_ALIAS +CYDEV_IO_DR_PRT12_DR_ALIAS EQU 0x4000508c + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT15_BASE +CYDEV_IO_DR_PRT15_BASE EQU 0x4000508f + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT15_SIZE +CYDEV_IO_DR_PRT15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT15_DR_15_ALIAS +CYDEV_IO_DR_PRT15_DR_15_ALIAS EQU 0x4000508f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_BASE +CYDEV_IO_PS_BASE EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_SIZE +CYDEV_IO_PS_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT0_BASE +CYDEV_IO_PS_PRT0_BASE EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT0_SIZE +CYDEV_IO_PS_PRT0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT0_PS_ALIAS +CYDEV_IO_PS_PRT0_PS_ALIAS EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT1_BASE +CYDEV_IO_PS_PRT1_BASE EQU 0x40005091 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT1_SIZE +CYDEV_IO_PS_PRT1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT1_PS_ALIAS +CYDEV_IO_PS_PRT1_PS_ALIAS EQU 0x40005091 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT2_BASE +CYDEV_IO_PS_PRT2_BASE EQU 0x40005092 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT2_SIZE +CYDEV_IO_PS_PRT2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT2_PS_ALIAS +CYDEV_IO_PS_PRT2_PS_ALIAS EQU 0x40005092 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT3_BASE +CYDEV_IO_PS_PRT3_BASE EQU 0x40005093 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT3_SIZE +CYDEV_IO_PS_PRT3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT3_PS_ALIAS +CYDEV_IO_PS_PRT3_PS_ALIAS EQU 0x40005093 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT4_BASE +CYDEV_IO_PS_PRT4_BASE EQU 0x40005094 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT4_SIZE +CYDEV_IO_PS_PRT4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT4_PS_ALIAS +CYDEV_IO_PS_PRT4_PS_ALIAS EQU 0x40005094 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT5_BASE +CYDEV_IO_PS_PRT5_BASE EQU 0x40005095 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT5_SIZE +CYDEV_IO_PS_PRT5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT5_PS_ALIAS +CYDEV_IO_PS_PRT5_PS_ALIAS EQU 0x40005095 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT6_BASE +CYDEV_IO_PS_PRT6_BASE EQU 0x40005096 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT6_SIZE +CYDEV_IO_PS_PRT6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT6_PS_ALIAS +CYDEV_IO_PS_PRT6_PS_ALIAS EQU 0x40005096 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT12_BASE +CYDEV_IO_PS_PRT12_BASE EQU 0x4000509c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT12_SIZE +CYDEV_IO_PS_PRT12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT12_PS_ALIAS +CYDEV_IO_PS_PRT12_PS_ALIAS EQU 0x4000509c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT15_BASE +CYDEV_IO_PS_PRT15_BASE EQU 0x4000509f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT15_SIZE +CYDEV_IO_PS_PRT15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT15_PS15_ALIAS +CYDEV_IO_PS_PRT15_PS15_ALIAS EQU 0x4000509f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_BASE +CYDEV_IO_PRT_BASE EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_SIZE +CYDEV_IO_PRT_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BASE +CYDEV_IO_PRT_PRT0_BASE EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_SIZE +CYDEV_IO_PRT_PRT0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_DR +CYDEV_IO_PRT_PRT0_DR EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_PS +CYDEV_IO_PRT_PRT0_PS EQU 0x40005101 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_DM0 +CYDEV_IO_PRT_PRT0_DM0 EQU 0x40005102 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_DM1 +CYDEV_IO_PRT_PRT0_DM1 EQU 0x40005103 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_DM2 +CYDEV_IO_PRT_PRT0_DM2 EQU 0x40005104 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_SLW +CYDEV_IO_PRT_PRT0_SLW EQU 0x40005105 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BYP +CYDEV_IO_PRT_PRT0_BYP EQU 0x40005106 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BIE +CYDEV_IO_PRT_PRT0_BIE EQU 0x40005107 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_INP_DIS +CYDEV_IO_PRT_PRT0_INP_DIS EQU 0x40005108 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_CTL +CYDEV_IO_PRT_PRT0_CTL EQU 0x40005109 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_PRT +CYDEV_IO_PRT_PRT0_PRT EQU 0x4000510a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BIT_MASK +CYDEV_IO_PRT_PRT0_BIT_MASK EQU 0x4000510b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_AMUX +CYDEV_IO_PRT_PRT0_AMUX EQU 0x4000510c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_AG +CYDEV_IO_PRT_PRT0_AG EQU 0x4000510d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_LCD_COM_SEG +CYDEV_IO_PRT_PRT0_LCD_COM_SEG EQU 0x4000510e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_LCD_EN +CYDEV_IO_PRT_PRT0_LCD_EN EQU 0x4000510f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BASE +CYDEV_IO_PRT_PRT1_BASE EQU 0x40005110 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_SIZE +CYDEV_IO_PRT_PRT1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_DR +CYDEV_IO_PRT_PRT1_DR EQU 0x40005110 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_PS +CYDEV_IO_PRT_PRT1_PS EQU 0x40005111 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_DM0 +CYDEV_IO_PRT_PRT1_DM0 EQU 0x40005112 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_DM1 +CYDEV_IO_PRT_PRT1_DM1 EQU 0x40005113 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_DM2 +CYDEV_IO_PRT_PRT1_DM2 EQU 0x40005114 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_SLW +CYDEV_IO_PRT_PRT1_SLW EQU 0x40005115 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BYP +CYDEV_IO_PRT_PRT1_BYP EQU 0x40005116 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BIE +CYDEV_IO_PRT_PRT1_BIE EQU 0x40005117 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_INP_DIS +CYDEV_IO_PRT_PRT1_INP_DIS EQU 0x40005118 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_CTL +CYDEV_IO_PRT_PRT1_CTL EQU 0x40005119 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_PRT +CYDEV_IO_PRT_PRT1_PRT EQU 0x4000511a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BIT_MASK +CYDEV_IO_PRT_PRT1_BIT_MASK EQU 0x4000511b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_AMUX +CYDEV_IO_PRT_PRT1_AMUX EQU 0x4000511c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_AG +CYDEV_IO_PRT_PRT1_AG EQU 0x4000511d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_LCD_COM_SEG +CYDEV_IO_PRT_PRT1_LCD_COM_SEG EQU 0x4000511e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_LCD_EN +CYDEV_IO_PRT_PRT1_LCD_EN EQU 0x4000511f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BASE +CYDEV_IO_PRT_PRT2_BASE EQU 0x40005120 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_SIZE +CYDEV_IO_PRT_PRT2_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_DR +CYDEV_IO_PRT_PRT2_DR EQU 0x40005120 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_PS +CYDEV_IO_PRT_PRT2_PS EQU 0x40005121 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_DM0 +CYDEV_IO_PRT_PRT2_DM0 EQU 0x40005122 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_DM1 +CYDEV_IO_PRT_PRT2_DM1 EQU 0x40005123 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_DM2 +CYDEV_IO_PRT_PRT2_DM2 EQU 0x40005124 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_SLW +CYDEV_IO_PRT_PRT2_SLW EQU 0x40005125 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BYP +CYDEV_IO_PRT_PRT2_BYP EQU 0x40005126 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BIE +CYDEV_IO_PRT_PRT2_BIE EQU 0x40005127 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_INP_DIS +CYDEV_IO_PRT_PRT2_INP_DIS EQU 0x40005128 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_CTL +CYDEV_IO_PRT_PRT2_CTL EQU 0x40005129 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_PRT +CYDEV_IO_PRT_PRT2_PRT EQU 0x4000512a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BIT_MASK +CYDEV_IO_PRT_PRT2_BIT_MASK EQU 0x4000512b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_AMUX +CYDEV_IO_PRT_PRT2_AMUX EQU 0x4000512c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_AG +CYDEV_IO_PRT_PRT2_AG EQU 0x4000512d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_LCD_COM_SEG +CYDEV_IO_PRT_PRT2_LCD_COM_SEG EQU 0x4000512e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_LCD_EN +CYDEV_IO_PRT_PRT2_LCD_EN EQU 0x4000512f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BASE +CYDEV_IO_PRT_PRT3_BASE EQU 0x40005130 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_SIZE +CYDEV_IO_PRT_PRT3_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_DR +CYDEV_IO_PRT_PRT3_DR EQU 0x40005130 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_PS +CYDEV_IO_PRT_PRT3_PS EQU 0x40005131 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_DM0 +CYDEV_IO_PRT_PRT3_DM0 EQU 0x40005132 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_DM1 +CYDEV_IO_PRT_PRT3_DM1 EQU 0x40005133 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_DM2 +CYDEV_IO_PRT_PRT3_DM2 EQU 0x40005134 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_SLW +CYDEV_IO_PRT_PRT3_SLW EQU 0x40005135 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BYP +CYDEV_IO_PRT_PRT3_BYP EQU 0x40005136 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BIE +CYDEV_IO_PRT_PRT3_BIE EQU 0x40005137 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_INP_DIS +CYDEV_IO_PRT_PRT3_INP_DIS EQU 0x40005138 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_CTL +CYDEV_IO_PRT_PRT3_CTL EQU 0x40005139 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_PRT +CYDEV_IO_PRT_PRT3_PRT EQU 0x4000513a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BIT_MASK +CYDEV_IO_PRT_PRT3_BIT_MASK EQU 0x4000513b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_AMUX +CYDEV_IO_PRT_PRT3_AMUX EQU 0x4000513c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_AG +CYDEV_IO_PRT_PRT3_AG EQU 0x4000513d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_LCD_COM_SEG +CYDEV_IO_PRT_PRT3_LCD_COM_SEG EQU 0x4000513e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_LCD_EN +CYDEV_IO_PRT_PRT3_LCD_EN EQU 0x4000513f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BASE +CYDEV_IO_PRT_PRT4_BASE EQU 0x40005140 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_SIZE +CYDEV_IO_PRT_PRT4_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_DR +CYDEV_IO_PRT_PRT4_DR EQU 0x40005140 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_PS +CYDEV_IO_PRT_PRT4_PS EQU 0x40005141 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_DM0 +CYDEV_IO_PRT_PRT4_DM0 EQU 0x40005142 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_DM1 +CYDEV_IO_PRT_PRT4_DM1 EQU 0x40005143 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_DM2 +CYDEV_IO_PRT_PRT4_DM2 EQU 0x40005144 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_SLW +CYDEV_IO_PRT_PRT4_SLW EQU 0x40005145 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BYP +CYDEV_IO_PRT_PRT4_BYP EQU 0x40005146 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BIE +CYDEV_IO_PRT_PRT4_BIE EQU 0x40005147 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_INP_DIS +CYDEV_IO_PRT_PRT4_INP_DIS EQU 0x40005148 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_CTL +CYDEV_IO_PRT_PRT4_CTL EQU 0x40005149 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_PRT +CYDEV_IO_PRT_PRT4_PRT EQU 0x4000514a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BIT_MASK +CYDEV_IO_PRT_PRT4_BIT_MASK EQU 0x4000514b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_AMUX +CYDEV_IO_PRT_PRT4_AMUX EQU 0x4000514c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_AG +CYDEV_IO_PRT_PRT4_AG EQU 0x4000514d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_LCD_COM_SEG +CYDEV_IO_PRT_PRT4_LCD_COM_SEG EQU 0x4000514e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_LCD_EN +CYDEV_IO_PRT_PRT4_LCD_EN EQU 0x4000514f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BASE +CYDEV_IO_PRT_PRT5_BASE EQU 0x40005150 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_SIZE +CYDEV_IO_PRT_PRT5_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_DR +CYDEV_IO_PRT_PRT5_DR EQU 0x40005150 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_PS +CYDEV_IO_PRT_PRT5_PS EQU 0x40005151 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_DM0 +CYDEV_IO_PRT_PRT5_DM0 EQU 0x40005152 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_DM1 +CYDEV_IO_PRT_PRT5_DM1 EQU 0x40005153 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_DM2 +CYDEV_IO_PRT_PRT5_DM2 EQU 0x40005154 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_SLW +CYDEV_IO_PRT_PRT5_SLW EQU 0x40005155 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BYP +CYDEV_IO_PRT_PRT5_BYP EQU 0x40005156 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BIE +CYDEV_IO_PRT_PRT5_BIE EQU 0x40005157 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_INP_DIS +CYDEV_IO_PRT_PRT5_INP_DIS EQU 0x40005158 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_CTL +CYDEV_IO_PRT_PRT5_CTL EQU 0x40005159 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_PRT +CYDEV_IO_PRT_PRT5_PRT EQU 0x4000515a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BIT_MASK +CYDEV_IO_PRT_PRT5_BIT_MASK EQU 0x4000515b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_AMUX +CYDEV_IO_PRT_PRT5_AMUX EQU 0x4000515c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_AG +CYDEV_IO_PRT_PRT5_AG EQU 0x4000515d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_LCD_COM_SEG +CYDEV_IO_PRT_PRT5_LCD_COM_SEG EQU 0x4000515e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_LCD_EN +CYDEV_IO_PRT_PRT5_LCD_EN EQU 0x4000515f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BASE +CYDEV_IO_PRT_PRT6_BASE EQU 0x40005160 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_SIZE +CYDEV_IO_PRT_PRT6_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_DR +CYDEV_IO_PRT_PRT6_DR EQU 0x40005160 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_PS +CYDEV_IO_PRT_PRT6_PS EQU 0x40005161 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_DM0 +CYDEV_IO_PRT_PRT6_DM0 EQU 0x40005162 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_DM1 +CYDEV_IO_PRT_PRT6_DM1 EQU 0x40005163 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_DM2 +CYDEV_IO_PRT_PRT6_DM2 EQU 0x40005164 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_SLW +CYDEV_IO_PRT_PRT6_SLW EQU 0x40005165 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BYP +CYDEV_IO_PRT_PRT6_BYP EQU 0x40005166 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BIE +CYDEV_IO_PRT_PRT6_BIE EQU 0x40005167 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_INP_DIS +CYDEV_IO_PRT_PRT6_INP_DIS EQU 0x40005168 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_CTL +CYDEV_IO_PRT_PRT6_CTL EQU 0x40005169 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_PRT +CYDEV_IO_PRT_PRT6_PRT EQU 0x4000516a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BIT_MASK +CYDEV_IO_PRT_PRT6_BIT_MASK EQU 0x4000516b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_AMUX +CYDEV_IO_PRT_PRT6_AMUX EQU 0x4000516c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_AG +CYDEV_IO_PRT_PRT6_AG EQU 0x4000516d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_LCD_COM_SEG +CYDEV_IO_PRT_PRT6_LCD_COM_SEG EQU 0x4000516e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_LCD_EN +CYDEV_IO_PRT_PRT6_LCD_EN EQU 0x4000516f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BASE +CYDEV_IO_PRT_PRT12_BASE EQU 0x400051c0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIZE +CYDEV_IO_PRT_PRT12_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_DR +CYDEV_IO_PRT_PRT12_DR EQU 0x400051c0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_PS +CYDEV_IO_PRT_PRT12_PS EQU 0x400051c1 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_DM0 +CYDEV_IO_PRT_PRT12_DM0 EQU 0x400051c2 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_DM1 +CYDEV_IO_PRT_PRT12_DM1 EQU 0x400051c3 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_DM2 +CYDEV_IO_PRT_PRT12_DM2 EQU 0x400051c4 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SLW +CYDEV_IO_PRT_PRT12_SLW EQU 0x400051c5 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BYP +CYDEV_IO_PRT_PRT12_BYP EQU 0x400051c6 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BIE +CYDEV_IO_PRT_PRT12_BIE EQU 0x400051c7 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_INP_DIS +CYDEV_IO_PRT_PRT12_INP_DIS EQU 0x400051c8 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIO_HYST_EN +CYDEV_IO_PRT_PRT12_SIO_HYST_EN EQU 0x400051c9 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_PRT +CYDEV_IO_PRT_PRT12_PRT EQU 0x400051ca + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BIT_MASK +CYDEV_IO_PRT_PRT12_BIT_MASK EQU 0x400051cb + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ +CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ EQU 0x400051cc + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_AG +CYDEV_IO_PRT_PRT12_AG EQU 0x400051cd + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIO_CFG +CYDEV_IO_PRT_PRT12_SIO_CFG EQU 0x400051ce + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIO_DIFF +CYDEV_IO_PRT_PRT12_SIO_DIFF EQU 0x400051cf + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BASE +CYDEV_IO_PRT_PRT15_BASE EQU 0x400051f0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_SIZE +CYDEV_IO_PRT_PRT15_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_DR +CYDEV_IO_PRT_PRT15_DR EQU 0x400051f0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_PS +CYDEV_IO_PRT_PRT15_PS EQU 0x400051f1 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_DM0 +CYDEV_IO_PRT_PRT15_DM0 EQU 0x400051f2 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_DM1 +CYDEV_IO_PRT_PRT15_DM1 EQU 0x400051f3 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_DM2 +CYDEV_IO_PRT_PRT15_DM2 EQU 0x400051f4 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_SLW +CYDEV_IO_PRT_PRT15_SLW EQU 0x400051f5 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BYP +CYDEV_IO_PRT_PRT15_BYP EQU 0x400051f6 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BIE +CYDEV_IO_PRT_PRT15_BIE EQU 0x400051f7 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_INP_DIS +CYDEV_IO_PRT_PRT15_INP_DIS EQU 0x400051f8 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_CTL +CYDEV_IO_PRT_PRT15_CTL EQU 0x400051f9 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_PRT +CYDEV_IO_PRT_PRT15_PRT EQU 0x400051fa + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BIT_MASK +CYDEV_IO_PRT_PRT15_BIT_MASK EQU 0x400051fb + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_AMUX +CYDEV_IO_PRT_PRT15_AMUX EQU 0x400051fc + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_AG +CYDEV_IO_PRT_PRT15_AG EQU 0x400051fd + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_LCD_COM_SEG +CYDEV_IO_PRT_PRT15_LCD_COM_SEG EQU 0x400051fe + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_LCD_EN +CYDEV_IO_PRT_PRT15_LCD_EN EQU 0x400051ff + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_BASE +CYDEV_PRTDSI_BASE EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_SIZE +CYDEV_PRTDSI_SIZE EQU 0x0000007f + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_BASE +CYDEV_PRTDSI_PRT0_BASE EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_SIZE +CYDEV_PRTDSI_PRT0_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_OUT_SEL0 +CYDEV_PRTDSI_PRT0_OUT_SEL0 EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_OUT_SEL1 +CYDEV_PRTDSI_PRT0_OUT_SEL1 EQU 0x40005201 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_OE_SEL0 +CYDEV_PRTDSI_PRT0_OE_SEL0 EQU 0x40005202 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_OE_SEL1 +CYDEV_PRTDSI_PRT0_OE_SEL1 EQU 0x40005203 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_DBL_SYNC_IN +CYDEV_PRTDSI_PRT0_DBL_SYNC_IN EQU 0x40005204 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_SYNC_OUT +CYDEV_PRTDSI_PRT0_SYNC_OUT EQU 0x40005205 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_CAPS_SEL +CYDEV_PRTDSI_PRT0_CAPS_SEL EQU 0x40005206 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_BASE +CYDEV_PRTDSI_PRT1_BASE EQU 0x40005208 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_SIZE +CYDEV_PRTDSI_PRT1_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_OUT_SEL0 +CYDEV_PRTDSI_PRT1_OUT_SEL0 EQU 0x40005208 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_OUT_SEL1 +CYDEV_PRTDSI_PRT1_OUT_SEL1 EQU 0x40005209 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_OE_SEL0 +CYDEV_PRTDSI_PRT1_OE_SEL0 EQU 0x4000520a + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_OE_SEL1 +CYDEV_PRTDSI_PRT1_OE_SEL1 EQU 0x4000520b + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_DBL_SYNC_IN +CYDEV_PRTDSI_PRT1_DBL_SYNC_IN EQU 0x4000520c + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_SYNC_OUT +CYDEV_PRTDSI_PRT1_SYNC_OUT EQU 0x4000520d + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_CAPS_SEL +CYDEV_PRTDSI_PRT1_CAPS_SEL EQU 0x4000520e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_BASE +CYDEV_PRTDSI_PRT2_BASE EQU 0x40005210 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_SIZE +CYDEV_PRTDSI_PRT2_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_OUT_SEL0 +CYDEV_PRTDSI_PRT2_OUT_SEL0 EQU 0x40005210 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_OUT_SEL1 +CYDEV_PRTDSI_PRT2_OUT_SEL1 EQU 0x40005211 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_OE_SEL0 +CYDEV_PRTDSI_PRT2_OE_SEL0 EQU 0x40005212 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_OE_SEL1 +CYDEV_PRTDSI_PRT2_OE_SEL1 EQU 0x40005213 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_DBL_SYNC_IN +CYDEV_PRTDSI_PRT2_DBL_SYNC_IN EQU 0x40005214 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_SYNC_OUT +CYDEV_PRTDSI_PRT2_SYNC_OUT EQU 0x40005215 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_CAPS_SEL +CYDEV_PRTDSI_PRT2_CAPS_SEL EQU 0x40005216 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_BASE +CYDEV_PRTDSI_PRT3_BASE EQU 0x40005218 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_SIZE +CYDEV_PRTDSI_PRT3_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_OUT_SEL0 +CYDEV_PRTDSI_PRT3_OUT_SEL0 EQU 0x40005218 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_OUT_SEL1 +CYDEV_PRTDSI_PRT3_OUT_SEL1 EQU 0x40005219 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_OE_SEL0 +CYDEV_PRTDSI_PRT3_OE_SEL0 EQU 0x4000521a + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_OE_SEL1 +CYDEV_PRTDSI_PRT3_OE_SEL1 EQU 0x4000521b + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_DBL_SYNC_IN +CYDEV_PRTDSI_PRT3_DBL_SYNC_IN EQU 0x4000521c + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_SYNC_OUT +CYDEV_PRTDSI_PRT3_SYNC_OUT EQU 0x4000521d + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_CAPS_SEL +CYDEV_PRTDSI_PRT3_CAPS_SEL EQU 0x4000521e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_BASE +CYDEV_PRTDSI_PRT4_BASE EQU 0x40005220 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_SIZE +CYDEV_PRTDSI_PRT4_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_OUT_SEL0 +CYDEV_PRTDSI_PRT4_OUT_SEL0 EQU 0x40005220 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_OUT_SEL1 +CYDEV_PRTDSI_PRT4_OUT_SEL1 EQU 0x40005221 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_OE_SEL0 +CYDEV_PRTDSI_PRT4_OE_SEL0 EQU 0x40005222 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_OE_SEL1 +CYDEV_PRTDSI_PRT4_OE_SEL1 EQU 0x40005223 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_DBL_SYNC_IN +CYDEV_PRTDSI_PRT4_DBL_SYNC_IN EQU 0x40005224 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_SYNC_OUT +CYDEV_PRTDSI_PRT4_SYNC_OUT EQU 0x40005225 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_CAPS_SEL +CYDEV_PRTDSI_PRT4_CAPS_SEL EQU 0x40005226 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_BASE +CYDEV_PRTDSI_PRT5_BASE EQU 0x40005228 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_SIZE +CYDEV_PRTDSI_PRT5_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_OUT_SEL0 +CYDEV_PRTDSI_PRT5_OUT_SEL0 EQU 0x40005228 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_OUT_SEL1 +CYDEV_PRTDSI_PRT5_OUT_SEL1 EQU 0x40005229 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_OE_SEL0 +CYDEV_PRTDSI_PRT5_OE_SEL0 EQU 0x4000522a + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_OE_SEL1 +CYDEV_PRTDSI_PRT5_OE_SEL1 EQU 0x4000522b + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_DBL_SYNC_IN +CYDEV_PRTDSI_PRT5_DBL_SYNC_IN EQU 0x4000522c + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_SYNC_OUT +CYDEV_PRTDSI_PRT5_SYNC_OUT EQU 0x4000522d + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_CAPS_SEL +CYDEV_PRTDSI_PRT5_CAPS_SEL EQU 0x4000522e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_BASE +CYDEV_PRTDSI_PRT6_BASE EQU 0x40005230 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_SIZE +CYDEV_PRTDSI_PRT6_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_OUT_SEL0 +CYDEV_PRTDSI_PRT6_OUT_SEL0 EQU 0x40005230 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_OUT_SEL1 +CYDEV_PRTDSI_PRT6_OUT_SEL1 EQU 0x40005231 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_OE_SEL0 +CYDEV_PRTDSI_PRT6_OE_SEL0 EQU 0x40005232 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_OE_SEL1 +CYDEV_PRTDSI_PRT6_OE_SEL1 EQU 0x40005233 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_DBL_SYNC_IN +CYDEV_PRTDSI_PRT6_DBL_SYNC_IN EQU 0x40005234 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_SYNC_OUT +CYDEV_PRTDSI_PRT6_SYNC_OUT EQU 0x40005235 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_CAPS_SEL +CYDEV_PRTDSI_PRT6_CAPS_SEL EQU 0x40005236 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_BASE +CYDEV_PRTDSI_PRT12_BASE EQU 0x40005260 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_SIZE +CYDEV_PRTDSI_PRT12_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_OUT_SEL0 +CYDEV_PRTDSI_PRT12_OUT_SEL0 EQU 0x40005260 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_OUT_SEL1 +CYDEV_PRTDSI_PRT12_OUT_SEL1 EQU 0x40005261 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_OE_SEL0 +CYDEV_PRTDSI_PRT12_OE_SEL0 EQU 0x40005262 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_OE_SEL1 +CYDEV_PRTDSI_PRT12_OE_SEL1 EQU 0x40005263 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_DBL_SYNC_IN +CYDEV_PRTDSI_PRT12_DBL_SYNC_IN EQU 0x40005264 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_SYNC_OUT +CYDEV_PRTDSI_PRT12_SYNC_OUT EQU 0x40005265 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_BASE +CYDEV_PRTDSI_PRT15_BASE EQU 0x40005278 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_SIZE +CYDEV_PRTDSI_PRT15_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_OUT_SEL0 +CYDEV_PRTDSI_PRT15_OUT_SEL0 EQU 0x40005278 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_OUT_SEL1 +CYDEV_PRTDSI_PRT15_OUT_SEL1 EQU 0x40005279 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_OE_SEL0 +CYDEV_PRTDSI_PRT15_OE_SEL0 EQU 0x4000527a + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_OE_SEL1 +CYDEV_PRTDSI_PRT15_OE_SEL1 EQU 0x4000527b + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_DBL_SYNC_IN +CYDEV_PRTDSI_PRT15_DBL_SYNC_IN EQU 0x4000527c + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_SYNC_OUT +CYDEV_PRTDSI_PRT15_SYNC_OUT EQU 0x4000527d + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_CAPS_SEL +CYDEV_PRTDSI_PRT15_CAPS_SEL EQU 0x4000527e + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_BASE +CYDEV_EMIF_BASE EQU 0x40005400 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_SIZE +CYDEV_EMIF_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_NO_UDB +CYDEV_EMIF_NO_UDB EQU 0x40005400 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_RP_WAIT_STATES +CYDEV_EMIF_RP_WAIT_STATES EQU 0x40005401 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_MEM_DWN +CYDEV_EMIF_MEM_DWN EQU 0x40005402 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_MEMCLK_DIV +CYDEV_EMIF_MEMCLK_DIV EQU 0x40005403 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_CLOCK_EN +CYDEV_EMIF_CLOCK_EN EQU 0x40005404 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_EM_TYPE +CYDEV_EMIF_EM_TYPE EQU 0x40005405 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_WP_WAIT_STATES +CYDEV_EMIF_WP_WAIT_STATES EQU 0x40005406 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_BASE +CYDEV_ANAIF_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_SIZE +CYDEV_ANAIF_SIZE EQU 0x000003a9 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BASE +CYDEV_ANAIF_CFG_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SIZE +CYDEV_ANAIF_CFG_SIZE EQU 0x0000010f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_BASE +CYDEV_ANAIF_CFG_SC0_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_SIZE +CYDEV_ANAIF_CFG_SC0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_CR0 +CYDEV_ANAIF_CFG_SC0_CR0 EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_CR1 +CYDEV_ANAIF_CFG_SC0_CR1 EQU 0x40005801 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_CR2 +CYDEV_ANAIF_CFG_SC0_CR2 EQU 0x40005802 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_BASE +CYDEV_ANAIF_CFG_SC1_BASE EQU 0x40005804 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_SIZE +CYDEV_ANAIF_CFG_SC1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_CR0 +CYDEV_ANAIF_CFG_SC1_CR0 EQU 0x40005804 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_CR1 +CYDEV_ANAIF_CFG_SC1_CR1 EQU 0x40005805 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_CR2 +CYDEV_ANAIF_CFG_SC1_CR2 EQU 0x40005806 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_BASE +CYDEV_ANAIF_CFG_SC2_BASE EQU 0x40005808 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_SIZE +CYDEV_ANAIF_CFG_SC2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_CR0 +CYDEV_ANAIF_CFG_SC2_CR0 EQU 0x40005808 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_CR1 +CYDEV_ANAIF_CFG_SC2_CR1 EQU 0x40005809 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_CR2 +CYDEV_ANAIF_CFG_SC2_CR2 EQU 0x4000580a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_BASE +CYDEV_ANAIF_CFG_SC3_BASE EQU 0x4000580c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_SIZE +CYDEV_ANAIF_CFG_SC3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_CR0 +CYDEV_ANAIF_CFG_SC3_CR0 EQU 0x4000580c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_CR1 +CYDEV_ANAIF_CFG_SC3_CR1 EQU 0x4000580d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_CR2 +CYDEV_ANAIF_CFG_SC3_CR2 EQU 0x4000580e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_BASE +CYDEV_ANAIF_CFG_DAC0_BASE EQU 0x40005820 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_SIZE +CYDEV_ANAIF_CFG_DAC0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_CR0 +CYDEV_ANAIF_CFG_DAC0_CR0 EQU 0x40005820 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_CR1 +CYDEV_ANAIF_CFG_DAC0_CR1 EQU 0x40005821 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_TST +CYDEV_ANAIF_CFG_DAC0_TST EQU 0x40005822 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_BASE +CYDEV_ANAIF_CFG_DAC1_BASE EQU 0x40005824 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_SIZE +CYDEV_ANAIF_CFG_DAC1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_CR0 +CYDEV_ANAIF_CFG_DAC1_CR0 EQU 0x40005824 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_CR1 +CYDEV_ANAIF_CFG_DAC1_CR1 EQU 0x40005825 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_TST +CYDEV_ANAIF_CFG_DAC1_TST EQU 0x40005826 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_BASE +CYDEV_ANAIF_CFG_DAC2_BASE EQU 0x40005828 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_SIZE +CYDEV_ANAIF_CFG_DAC2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_CR0 +CYDEV_ANAIF_CFG_DAC2_CR0 EQU 0x40005828 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_CR1 +CYDEV_ANAIF_CFG_DAC2_CR1 EQU 0x40005829 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_TST +CYDEV_ANAIF_CFG_DAC2_TST EQU 0x4000582a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_BASE +CYDEV_ANAIF_CFG_DAC3_BASE EQU 0x4000582c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_SIZE +CYDEV_ANAIF_CFG_DAC3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_CR0 +CYDEV_ANAIF_CFG_DAC3_CR0 EQU 0x4000582c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_CR1 +CYDEV_ANAIF_CFG_DAC3_CR1 EQU 0x4000582d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_TST +CYDEV_ANAIF_CFG_DAC3_TST EQU 0x4000582e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_BASE +CYDEV_ANAIF_CFG_CMP0_BASE EQU 0x40005840 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_SIZE +CYDEV_ANAIF_CFG_CMP0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_CR +CYDEV_ANAIF_CFG_CMP0_CR EQU 0x40005840 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_BASE +CYDEV_ANAIF_CFG_CMP1_BASE EQU 0x40005841 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_SIZE +CYDEV_ANAIF_CFG_CMP1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_CR +CYDEV_ANAIF_CFG_CMP1_CR EQU 0x40005841 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_BASE +CYDEV_ANAIF_CFG_CMP2_BASE EQU 0x40005842 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_SIZE +CYDEV_ANAIF_CFG_CMP2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_CR +CYDEV_ANAIF_CFG_CMP2_CR EQU 0x40005842 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_BASE +CYDEV_ANAIF_CFG_CMP3_BASE EQU 0x40005843 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_SIZE +CYDEV_ANAIF_CFG_CMP3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_CR +CYDEV_ANAIF_CFG_CMP3_CR EQU 0x40005843 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_BASE +CYDEV_ANAIF_CFG_LUT0_BASE EQU 0x40005848 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_SIZE +CYDEV_ANAIF_CFG_LUT0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_CR +CYDEV_ANAIF_CFG_LUT0_CR EQU 0x40005848 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_MX +CYDEV_ANAIF_CFG_LUT0_MX EQU 0x40005849 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_BASE +CYDEV_ANAIF_CFG_LUT1_BASE EQU 0x4000584a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_SIZE +CYDEV_ANAIF_CFG_LUT1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_CR +CYDEV_ANAIF_CFG_LUT1_CR EQU 0x4000584a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_MX +CYDEV_ANAIF_CFG_LUT1_MX EQU 0x4000584b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_BASE +CYDEV_ANAIF_CFG_LUT2_BASE EQU 0x4000584c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_SIZE +CYDEV_ANAIF_CFG_LUT2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_CR +CYDEV_ANAIF_CFG_LUT2_CR EQU 0x4000584c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_MX +CYDEV_ANAIF_CFG_LUT2_MX EQU 0x4000584d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_BASE +CYDEV_ANAIF_CFG_LUT3_BASE EQU 0x4000584e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_SIZE +CYDEV_ANAIF_CFG_LUT3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_CR +CYDEV_ANAIF_CFG_LUT3_CR EQU 0x4000584e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_MX +CYDEV_ANAIF_CFG_LUT3_MX EQU 0x4000584f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_BASE +CYDEV_ANAIF_CFG_OPAMP0_BASE EQU 0x40005858 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_SIZE +CYDEV_ANAIF_CFG_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_CR +CYDEV_ANAIF_CFG_OPAMP0_CR EQU 0x40005858 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_RSVD +CYDEV_ANAIF_CFG_OPAMP0_RSVD EQU 0x40005859 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_BASE +CYDEV_ANAIF_CFG_OPAMP1_BASE EQU 0x4000585a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_SIZE +CYDEV_ANAIF_CFG_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_CR +CYDEV_ANAIF_CFG_OPAMP1_CR EQU 0x4000585a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_RSVD +CYDEV_ANAIF_CFG_OPAMP1_RSVD EQU 0x4000585b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_BASE +CYDEV_ANAIF_CFG_OPAMP2_BASE EQU 0x4000585c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_SIZE +CYDEV_ANAIF_CFG_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_CR +CYDEV_ANAIF_CFG_OPAMP2_CR EQU 0x4000585c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_RSVD +CYDEV_ANAIF_CFG_OPAMP2_RSVD EQU 0x4000585d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_BASE +CYDEV_ANAIF_CFG_OPAMP3_BASE EQU 0x4000585e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_SIZE +CYDEV_ANAIF_CFG_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_CR +CYDEV_ANAIF_CFG_OPAMP3_CR EQU 0x4000585e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_RSVD +CYDEV_ANAIF_CFG_OPAMP3_RSVD EQU 0x4000585f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_BASE +CYDEV_ANAIF_CFG_LCDDAC_BASE EQU 0x40005868 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_SIZE +CYDEV_ANAIF_CFG_LCDDAC_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_CR0 +CYDEV_ANAIF_CFG_LCDDAC_CR0 EQU 0x40005868 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_CR1 +CYDEV_ANAIF_CFG_LCDDAC_CR1 EQU 0x40005869 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_BASE +CYDEV_ANAIF_CFG_LCDDRV_BASE EQU 0x4000586a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_SIZE +CYDEV_ANAIF_CFG_LCDDRV_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_CR +CYDEV_ANAIF_CFG_LCDDRV_CR EQU 0x4000586a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_BASE +CYDEV_ANAIF_CFG_LCDTMR_BASE EQU 0x4000586b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_SIZE +CYDEV_ANAIF_CFG_LCDTMR_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_CFG +CYDEV_ANAIF_CFG_LCDTMR_CFG EQU 0x4000586b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_BASE +CYDEV_ANAIF_CFG_BG_BASE EQU 0x4000586c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_SIZE +CYDEV_ANAIF_CFG_BG_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_CR0 +CYDEV_ANAIF_CFG_BG_CR0 EQU 0x4000586c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_RSVD +CYDEV_ANAIF_CFG_BG_RSVD EQU 0x4000586d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_DFT0 +CYDEV_ANAIF_CFG_BG_DFT0 EQU 0x4000586e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_DFT1 +CYDEV_ANAIF_CFG_BG_DFT1 EQU 0x4000586f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_BASE +CYDEV_ANAIF_CFG_CAPSL_BASE EQU 0x40005870 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_SIZE +CYDEV_ANAIF_CFG_CAPSL_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_CFG0 +CYDEV_ANAIF_CFG_CAPSL_CFG0 EQU 0x40005870 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_CFG1 +CYDEV_ANAIF_CFG_CAPSL_CFG1 EQU 0x40005871 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_BASE +CYDEV_ANAIF_CFG_CAPSR_BASE EQU 0x40005872 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_SIZE +CYDEV_ANAIF_CFG_CAPSR_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_CFG0 +CYDEV_ANAIF_CFG_CAPSR_CFG0 EQU 0x40005872 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_CFG1 +CYDEV_ANAIF_CFG_CAPSR_CFG1 EQU 0x40005873 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_BASE +CYDEV_ANAIF_CFG_PUMP_BASE EQU 0x40005876 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_SIZE +CYDEV_ANAIF_CFG_PUMP_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_CR0 +CYDEV_ANAIF_CFG_PUMP_CR0 EQU 0x40005876 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_CR1 +CYDEV_ANAIF_CFG_PUMP_CR1 EQU 0x40005877 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_BASE +CYDEV_ANAIF_CFG_LPF0_BASE EQU 0x40005878 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_SIZE +CYDEV_ANAIF_CFG_LPF0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_CR0 +CYDEV_ANAIF_CFG_LPF0_CR0 EQU 0x40005878 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_RSVD +CYDEV_ANAIF_CFG_LPF0_RSVD EQU 0x40005879 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_BASE +CYDEV_ANAIF_CFG_LPF1_BASE EQU 0x4000587a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_SIZE +CYDEV_ANAIF_CFG_LPF1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_CR0 +CYDEV_ANAIF_CFG_LPF1_CR0 EQU 0x4000587a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_RSVD +CYDEV_ANAIF_CFG_LPF1_RSVD EQU 0x4000587b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_BASE +CYDEV_ANAIF_CFG_MISC_BASE EQU 0x4000587c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_SIZE +CYDEV_ANAIF_CFG_MISC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_CR0 +CYDEV_ANAIF_CFG_MISC_CR0 EQU 0x4000587c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BASE +CYDEV_ANAIF_CFG_DSM0_BASE EQU 0x40005880 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_SIZE +CYDEV_ANAIF_CFG_DSM0_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR0 +CYDEV_ANAIF_CFG_DSM0_CR0 EQU 0x40005880 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR1 +CYDEV_ANAIF_CFG_DSM0_CR1 EQU 0x40005881 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR2 +CYDEV_ANAIF_CFG_DSM0_CR2 EQU 0x40005882 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR3 +CYDEV_ANAIF_CFG_DSM0_CR3 EQU 0x40005883 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR4 +CYDEV_ANAIF_CFG_DSM0_CR4 EQU 0x40005884 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR5 +CYDEV_ANAIF_CFG_DSM0_CR5 EQU 0x40005885 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR6 +CYDEV_ANAIF_CFG_DSM0_CR6 EQU 0x40005886 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR7 +CYDEV_ANAIF_CFG_DSM0_CR7 EQU 0x40005887 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR8 +CYDEV_ANAIF_CFG_DSM0_CR8 EQU 0x40005888 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR9 +CYDEV_ANAIF_CFG_DSM0_CR9 EQU 0x40005889 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR10 +CYDEV_ANAIF_CFG_DSM0_CR10 EQU 0x4000588a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR11 +CYDEV_ANAIF_CFG_DSM0_CR11 EQU 0x4000588b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR12 +CYDEV_ANAIF_CFG_DSM0_CR12 EQU 0x4000588c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR13 +CYDEV_ANAIF_CFG_DSM0_CR13 EQU 0x4000588d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR14 +CYDEV_ANAIF_CFG_DSM0_CR14 EQU 0x4000588e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR15 +CYDEV_ANAIF_CFG_DSM0_CR15 EQU 0x4000588f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR16 +CYDEV_ANAIF_CFG_DSM0_CR16 EQU 0x40005890 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR17 +CYDEV_ANAIF_CFG_DSM0_CR17 EQU 0x40005891 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_REF0 +CYDEV_ANAIF_CFG_DSM0_REF0 EQU 0x40005892 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_REF1 +CYDEV_ANAIF_CFG_DSM0_REF1 EQU 0x40005893 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_REF2 +CYDEV_ANAIF_CFG_DSM0_REF2 EQU 0x40005894 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_REF3 +CYDEV_ANAIF_CFG_DSM0_REF3 EQU 0x40005895 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_DEM0 +CYDEV_ANAIF_CFG_DSM0_DEM0 EQU 0x40005896 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_DEM1 +CYDEV_ANAIF_CFG_DSM0_DEM1 EQU 0x40005897 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_TST0 +CYDEV_ANAIF_CFG_DSM0_TST0 EQU 0x40005898 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_TST1 +CYDEV_ANAIF_CFG_DSM0_TST1 EQU 0x40005899 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BUF0 +CYDEV_ANAIF_CFG_DSM0_BUF0 EQU 0x4000589a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BUF1 +CYDEV_ANAIF_CFG_DSM0_BUF1 EQU 0x4000589b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BUF2 +CYDEV_ANAIF_CFG_DSM0_BUF2 EQU 0x4000589c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BUF3 +CYDEV_ANAIF_CFG_DSM0_BUF3 EQU 0x4000589d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_MISC +CYDEV_ANAIF_CFG_DSM0_MISC EQU 0x4000589e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_RSVD1 +CYDEV_ANAIF_CFG_DSM0_RSVD1 EQU 0x4000589f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_BASE +CYDEV_ANAIF_CFG_SAR0_BASE EQU 0x40005900 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_SIZE +CYDEV_ANAIF_CFG_SAR0_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR0 +CYDEV_ANAIF_CFG_SAR0_CSR0 EQU 0x40005900 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR1 +CYDEV_ANAIF_CFG_SAR0_CSR1 EQU 0x40005901 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR2 +CYDEV_ANAIF_CFG_SAR0_CSR2 EQU 0x40005902 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR3 +CYDEV_ANAIF_CFG_SAR0_CSR3 EQU 0x40005903 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR4 +CYDEV_ANAIF_CFG_SAR0_CSR4 EQU 0x40005904 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR5 +CYDEV_ANAIF_CFG_SAR0_CSR5 EQU 0x40005905 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR6 +CYDEV_ANAIF_CFG_SAR0_CSR6 EQU 0x40005906 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_BASE +CYDEV_ANAIF_CFG_SAR1_BASE EQU 0x40005908 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_SIZE +CYDEV_ANAIF_CFG_SAR1_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR0 +CYDEV_ANAIF_CFG_SAR1_CSR0 EQU 0x40005908 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR1 +CYDEV_ANAIF_CFG_SAR1_CSR1 EQU 0x40005909 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR2 +CYDEV_ANAIF_CFG_SAR1_CSR2 EQU 0x4000590a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR3 +CYDEV_ANAIF_CFG_SAR1_CSR3 EQU 0x4000590b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR4 +CYDEV_ANAIF_CFG_SAR1_CSR4 EQU 0x4000590c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR5 +CYDEV_ANAIF_CFG_SAR1_CSR5 EQU 0x4000590d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR6 +CYDEV_ANAIF_CFG_SAR1_CSR6 EQU 0x4000590e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BASE +CYDEV_ANAIF_RT_BASE EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SIZE +CYDEV_ANAIF_RT_SIZE EQU 0x00000162 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_BASE +CYDEV_ANAIF_RT_SC0_BASE EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SIZE +CYDEV_ANAIF_RT_SC0_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW0 +CYDEV_ANAIF_RT_SC0_SW0 EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW2 +CYDEV_ANAIF_RT_SC0_SW2 EQU 0x40005a02 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW3 +CYDEV_ANAIF_RT_SC0_SW3 EQU 0x40005a03 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW4 +CYDEV_ANAIF_RT_SC0_SW4 EQU 0x40005a04 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW6 +CYDEV_ANAIF_RT_SC0_SW6 EQU 0x40005a06 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW7 +CYDEV_ANAIF_RT_SC0_SW7 EQU 0x40005a07 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW8 +CYDEV_ANAIF_RT_SC0_SW8 EQU 0x40005a08 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW10 +CYDEV_ANAIF_RT_SC0_SW10 EQU 0x40005a0a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_CLK +CYDEV_ANAIF_RT_SC0_CLK EQU 0x40005a0b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_BST +CYDEV_ANAIF_RT_SC0_BST EQU 0x40005a0c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_BASE +CYDEV_ANAIF_RT_SC1_BASE EQU 0x40005a10 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SIZE +CYDEV_ANAIF_RT_SC1_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW0 +CYDEV_ANAIF_RT_SC1_SW0 EQU 0x40005a10 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW2 +CYDEV_ANAIF_RT_SC1_SW2 EQU 0x40005a12 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW3 +CYDEV_ANAIF_RT_SC1_SW3 EQU 0x40005a13 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW4 +CYDEV_ANAIF_RT_SC1_SW4 EQU 0x40005a14 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW6 +CYDEV_ANAIF_RT_SC1_SW6 EQU 0x40005a16 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW7 +CYDEV_ANAIF_RT_SC1_SW7 EQU 0x40005a17 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW8 +CYDEV_ANAIF_RT_SC1_SW8 EQU 0x40005a18 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW10 +CYDEV_ANAIF_RT_SC1_SW10 EQU 0x40005a1a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_CLK +CYDEV_ANAIF_RT_SC1_CLK EQU 0x40005a1b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_BST +CYDEV_ANAIF_RT_SC1_BST EQU 0x40005a1c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_BASE +CYDEV_ANAIF_RT_SC2_BASE EQU 0x40005a20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SIZE +CYDEV_ANAIF_RT_SC2_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW0 +CYDEV_ANAIF_RT_SC2_SW0 EQU 0x40005a20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW2 +CYDEV_ANAIF_RT_SC2_SW2 EQU 0x40005a22 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW3 +CYDEV_ANAIF_RT_SC2_SW3 EQU 0x40005a23 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW4 +CYDEV_ANAIF_RT_SC2_SW4 EQU 0x40005a24 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW6 +CYDEV_ANAIF_RT_SC2_SW6 EQU 0x40005a26 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW7 +CYDEV_ANAIF_RT_SC2_SW7 EQU 0x40005a27 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW8 +CYDEV_ANAIF_RT_SC2_SW8 EQU 0x40005a28 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW10 +CYDEV_ANAIF_RT_SC2_SW10 EQU 0x40005a2a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_CLK +CYDEV_ANAIF_RT_SC2_CLK EQU 0x40005a2b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_BST +CYDEV_ANAIF_RT_SC2_BST EQU 0x40005a2c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_BASE +CYDEV_ANAIF_RT_SC3_BASE EQU 0x40005a30 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SIZE +CYDEV_ANAIF_RT_SC3_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW0 +CYDEV_ANAIF_RT_SC3_SW0 EQU 0x40005a30 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW2 +CYDEV_ANAIF_RT_SC3_SW2 EQU 0x40005a32 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW3 +CYDEV_ANAIF_RT_SC3_SW3 EQU 0x40005a33 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW4 +CYDEV_ANAIF_RT_SC3_SW4 EQU 0x40005a34 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW6 +CYDEV_ANAIF_RT_SC3_SW6 EQU 0x40005a36 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW7 +CYDEV_ANAIF_RT_SC3_SW7 EQU 0x40005a37 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW8 +CYDEV_ANAIF_RT_SC3_SW8 EQU 0x40005a38 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW10 +CYDEV_ANAIF_RT_SC3_SW10 EQU 0x40005a3a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_CLK +CYDEV_ANAIF_RT_SC3_CLK EQU 0x40005a3b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_BST +CYDEV_ANAIF_RT_SC3_BST EQU 0x40005a3c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_BASE +CYDEV_ANAIF_RT_DAC0_BASE EQU 0x40005a80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SIZE +CYDEV_ANAIF_RT_DAC0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SW0 +CYDEV_ANAIF_RT_DAC0_SW0 EQU 0x40005a80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SW2 +CYDEV_ANAIF_RT_DAC0_SW2 EQU 0x40005a82 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SW3 +CYDEV_ANAIF_RT_DAC0_SW3 EQU 0x40005a83 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SW4 +CYDEV_ANAIF_RT_DAC0_SW4 EQU 0x40005a84 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_STROBE +CYDEV_ANAIF_RT_DAC0_STROBE EQU 0x40005a87 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_BASE +CYDEV_ANAIF_RT_DAC1_BASE EQU 0x40005a88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SIZE +CYDEV_ANAIF_RT_DAC1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SW0 +CYDEV_ANAIF_RT_DAC1_SW0 EQU 0x40005a88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SW2 +CYDEV_ANAIF_RT_DAC1_SW2 EQU 0x40005a8a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SW3 +CYDEV_ANAIF_RT_DAC1_SW3 EQU 0x40005a8b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SW4 +CYDEV_ANAIF_RT_DAC1_SW4 EQU 0x40005a8c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_STROBE +CYDEV_ANAIF_RT_DAC1_STROBE EQU 0x40005a8f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_BASE +CYDEV_ANAIF_RT_DAC2_BASE EQU 0x40005a90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SIZE +CYDEV_ANAIF_RT_DAC2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SW0 +CYDEV_ANAIF_RT_DAC2_SW0 EQU 0x40005a90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SW2 +CYDEV_ANAIF_RT_DAC2_SW2 EQU 0x40005a92 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SW3 +CYDEV_ANAIF_RT_DAC2_SW3 EQU 0x40005a93 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SW4 +CYDEV_ANAIF_RT_DAC2_SW4 EQU 0x40005a94 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_STROBE +CYDEV_ANAIF_RT_DAC2_STROBE EQU 0x40005a97 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_BASE +CYDEV_ANAIF_RT_DAC3_BASE EQU 0x40005a98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SIZE +CYDEV_ANAIF_RT_DAC3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SW0 +CYDEV_ANAIF_RT_DAC3_SW0 EQU 0x40005a98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SW2 +CYDEV_ANAIF_RT_DAC3_SW2 EQU 0x40005a9a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SW3 +CYDEV_ANAIF_RT_DAC3_SW3 EQU 0x40005a9b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SW4 +CYDEV_ANAIF_RT_DAC3_SW4 EQU 0x40005a9c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_STROBE +CYDEV_ANAIF_RT_DAC3_STROBE EQU 0x40005a9f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_BASE +CYDEV_ANAIF_RT_CMP0_BASE EQU 0x40005ac0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SIZE +CYDEV_ANAIF_RT_CMP0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW0 +CYDEV_ANAIF_RT_CMP0_SW0 EQU 0x40005ac0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW2 +CYDEV_ANAIF_RT_CMP0_SW2 EQU 0x40005ac2 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW3 +CYDEV_ANAIF_RT_CMP0_SW3 EQU 0x40005ac3 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW4 +CYDEV_ANAIF_RT_CMP0_SW4 EQU 0x40005ac4 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW6 +CYDEV_ANAIF_RT_CMP0_SW6 EQU 0x40005ac6 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_CLK +CYDEV_ANAIF_RT_CMP0_CLK EQU 0x40005ac7 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_BASE +CYDEV_ANAIF_RT_CMP1_BASE EQU 0x40005ac8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SIZE +CYDEV_ANAIF_RT_CMP1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW0 +CYDEV_ANAIF_RT_CMP1_SW0 EQU 0x40005ac8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW2 +CYDEV_ANAIF_RT_CMP1_SW2 EQU 0x40005aca + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW3 +CYDEV_ANAIF_RT_CMP1_SW3 EQU 0x40005acb + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW4 +CYDEV_ANAIF_RT_CMP1_SW4 EQU 0x40005acc + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW6 +CYDEV_ANAIF_RT_CMP1_SW6 EQU 0x40005ace + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_CLK +CYDEV_ANAIF_RT_CMP1_CLK EQU 0x40005acf + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_BASE +CYDEV_ANAIF_RT_CMP2_BASE EQU 0x40005ad0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SIZE +CYDEV_ANAIF_RT_CMP2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW0 +CYDEV_ANAIF_RT_CMP2_SW0 EQU 0x40005ad0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW2 +CYDEV_ANAIF_RT_CMP2_SW2 EQU 0x40005ad2 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW3 +CYDEV_ANAIF_RT_CMP2_SW3 EQU 0x40005ad3 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW4 +CYDEV_ANAIF_RT_CMP2_SW4 EQU 0x40005ad4 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW6 +CYDEV_ANAIF_RT_CMP2_SW6 EQU 0x40005ad6 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_CLK +CYDEV_ANAIF_RT_CMP2_CLK EQU 0x40005ad7 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_BASE +CYDEV_ANAIF_RT_CMP3_BASE EQU 0x40005ad8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SIZE +CYDEV_ANAIF_RT_CMP3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW0 +CYDEV_ANAIF_RT_CMP3_SW0 EQU 0x40005ad8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW2 +CYDEV_ANAIF_RT_CMP3_SW2 EQU 0x40005ada + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW3 +CYDEV_ANAIF_RT_CMP3_SW3 EQU 0x40005adb + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW4 +CYDEV_ANAIF_RT_CMP3_SW4 EQU 0x40005adc + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW6 +CYDEV_ANAIF_RT_CMP3_SW6 EQU 0x40005ade + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_CLK +CYDEV_ANAIF_RT_CMP3_CLK EQU 0x40005adf + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_BASE +CYDEV_ANAIF_RT_DSM0_BASE EQU 0x40005b00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SIZE +CYDEV_ANAIF_RT_DSM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW0 +CYDEV_ANAIF_RT_DSM0_SW0 EQU 0x40005b00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW2 +CYDEV_ANAIF_RT_DSM0_SW2 EQU 0x40005b02 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW3 +CYDEV_ANAIF_RT_DSM0_SW3 EQU 0x40005b03 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW4 +CYDEV_ANAIF_RT_DSM0_SW4 EQU 0x40005b04 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW6 +CYDEV_ANAIF_RT_DSM0_SW6 EQU 0x40005b06 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_CLK +CYDEV_ANAIF_RT_DSM0_CLK EQU 0x40005b07 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_BASE +CYDEV_ANAIF_RT_SAR0_BASE EQU 0x40005b20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SIZE +CYDEV_ANAIF_RT_SAR0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW0 +CYDEV_ANAIF_RT_SAR0_SW0 EQU 0x40005b20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW2 +CYDEV_ANAIF_RT_SAR0_SW2 EQU 0x40005b22 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW3 +CYDEV_ANAIF_RT_SAR0_SW3 EQU 0x40005b23 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW4 +CYDEV_ANAIF_RT_SAR0_SW4 EQU 0x40005b24 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW6 +CYDEV_ANAIF_RT_SAR0_SW6 EQU 0x40005b26 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_CLK +CYDEV_ANAIF_RT_SAR0_CLK EQU 0x40005b27 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_BASE +CYDEV_ANAIF_RT_SAR1_BASE EQU 0x40005b28 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SIZE +CYDEV_ANAIF_RT_SAR1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW0 +CYDEV_ANAIF_RT_SAR1_SW0 EQU 0x40005b28 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW2 +CYDEV_ANAIF_RT_SAR1_SW2 EQU 0x40005b2a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW3 +CYDEV_ANAIF_RT_SAR1_SW3 EQU 0x40005b2b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW4 +CYDEV_ANAIF_RT_SAR1_SW4 EQU 0x40005b2c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW6 +CYDEV_ANAIF_RT_SAR1_SW6 EQU 0x40005b2e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_CLK +CYDEV_ANAIF_RT_SAR1_CLK EQU 0x40005b2f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_BASE +CYDEV_ANAIF_RT_OPAMP0_BASE EQU 0x40005b40 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_SIZE +CYDEV_ANAIF_RT_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_MX +CYDEV_ANAIF_RT_OPAMP0_MX EQU 0x40005b40 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_SW +CYDEV_ANAIF_RT_OPAMP0_SW EQU 0x40005b41 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_BASE +CYDEV_ANAIF_RT_OPAMP1_BASE EQU 0x40005b42 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_SIZE +CYDEV_ANAIF_RT_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_MX +CYDEV_ANAIF_RT_OPAMP1_MX EQU 0x40005b42 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_SW +CYDEV_ANAIF_RT_OPAMP1_SW EQU 0x40005b43 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_BASE +CYDEV_ANAIF_RT_OPAMP2_BASE EQU 0x40005b44 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_SIZE +CYDEV_ANAIF_RT_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_MX +CYDEV_ANAIF_RT_OPAMP2_MX EQU 0x40005b44 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_SW +CYDEV_ANAIF_RT_OPAMP2_SW EQU 0x40005b45 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_BASE +CYDEV_ANAIF_RT_OPAMP3_BASE EQU 0x40005b46 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_SIZE +CYDEV_ANAIF_RT_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_MX +CYDEV_ANAIF_RT_OPAMP3_MX EQU 0x40005b46 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_SW +CYDEV_ANAIF_RT_OPAMP3_SW EQU 0x40005b47 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_BASE +CYDEV_ANAIF_RT_LCDDAC_BASE EQU 0x40005b50 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SIZE +CYDEV_ANAIF_RT_LCDDAC_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW0 +CYDEV_ANAIF_RT_LCDDAC_SW0 EQU 0x40005b50 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW1 +CYDEV_ANAIF_RT_LCDDAC_SW1 EQU 0x40005b51 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW2 +CYDEV_ANAIF_RT_LCDDAC_SW2 EQU 0x40005b52 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW3 +CYDEV_ANAIF_RT_LCDDAC_SW3 EQU 0x40005b53 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW4 +CYDEV_ANAIF_RT_LCDDAC_SW4 EQU 0x40005b54 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_BASE +CYDEV_ANAIF_RT_SC_BASE EQU 0x40005b56 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_SIZE +CYDEV_ANAIF_RT_SC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_MISC +CYDEV_ANAIF_RT_SC_MISC EQU 0x40005b56 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_BASE +CYDEV_ANAIF_RT_BUS_BASE EQU 0x40005b58 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SIZE +CYDEV_ANAIF_RT_BUS_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SW0 +CYDEV_ANAIF_RT_BUS_SW0 EQU 0x40005b58 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SW2 +CYDEV_ANAIF_RT_BUS_SW2 EQU 0x40005b5a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SW3 +CYDEV_ANAIF_RT_BUS_SW3 EQU 0x40005b5b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_BASE +CYDEV_ANAIF_RT_DFT_BASE EQU 0x40005b5c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_SIZE +CYDEV_ANAIF_RT_DFT_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR0 +CYDEV_ANAIF_RT_DFT_CR0 EQU 0x40005b5c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR1 +CYDEV_ANAIF_RT_DFT_CR1 EQU 0x40005b5d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR2 +CYDEV_ANAIF_RT_DFT_CR2 EQU 0x40005b5e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR3 +CYDEV_ANAIF_RT_DFT_CR3 EQU 0x40005b5f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR4 +CYDEV_ANAIF_RT_DFT_CR4 EQU 0x40005b60 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR5 +CYDEV_ANAIF_RT_DFT_CR5 EQU 0x40005b61 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_BASE +CYDEV_ANAIF_WRK_BASE EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SIZE +CYDEV_ANAIF_WRK_SIZE EQU 0x00000029 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_BASE +CYDEV_ANAIF_WRK_DAC0_BASE EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_SIZE +CYDEV_ANAIF_WRK_DAC0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_D +CYDEV_ANAIF_WRK_DAC0_D EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_BASE +CYDEV_ANAIF_WRK_DAC1_BASE EQU 0x40005b81 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_SIZE +CYDEV_ANAIF_WRK_DAC1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_D +CYDEV_ANAIF_WRK_DAC1_D EQU 0x40005b81 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_BASE +CYDEV_ANAIF_WRK_DAC2_BASE EQU 0x40005b82 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_SIZE +CYDEV_ANAIF_WRK_DAC2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_D +CYDEV_ANAIF_WRK_DAC2_D EQU 0x40005b82 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_BASE +CYDEV_ANAIF_WRK_DAC3_BASE EQU 0x40005b83 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_SIZE +CYDEV_ANAIF_WRK_DAC3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_D +CYDEV_ANAIF_WRK_DAC3_D EQU 0x40005b83 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_BASE +CYDEV_ANAIF_WRK_DSM0_BASE EQU 0x40005b88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_SIZE +CYDEV_ANAIF_WRK_DSM0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_OUT0 +CYDEV_ANAIF_WRK_DSM0_OUT0 EQU 0x40005b88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_OUT1 +CYDEV_ANAIF_WRK_DSM0_OUT1 EQU 0x40005b89 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_BASE +CYDEV_ANAIF_WRK_LUT_BASE EQU 0x40005b90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_SIZE +CYDEV_ANAIF_WRK_LUT_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_SR +CYDEV_ANAIF_WRK_LUT_SR EQU 0x40005b90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_WRK1 +CYDEV_ANAIF_WRK_LUT_WRK1 EQU 0x40005b91 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_MSK +CYDEV_ANAIF_WRK_LUT_MSK EQU 0x40005b92 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_CLK +CYDEV_ANAIF_WRK_LUT_CLK EQU 0x40005b93 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_CPTR +CYDEV_ANAIF_WRK_LUT_CPTR EQU 0x40005b94 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_BASE +CYDEV_ANAIF_WRK_CMP_BASE EQU 0x40005b96 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_SIZE +CYDEV_ANAIF_WRK_CMP_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_WRK +CYDEV_ANAIF_WRK_CMP_WRK EQU 0x40005b96 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_TST +CYDEV_ANAIF_WRK_CMP_TST EQU 0x40005b97 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_BASE +CYDEV_ANAIF_WRK_SC_BASE EQU 0x40005b98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_SIZE +CYDEV_ANAIF_WRK_SC_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_SR +CYDEV_ANAIF_WRK_SC_SR EQU 0x40005b98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_WRK1 +CYDEV_ANAIF_WRK_SC_WRK1 EQU 0x40005b99 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_MSK +CYDEV_ANAIF_WRK_SC_MSK EQU 0x40005b9a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_CMPINV +CYDEV_ANAIF_WRK_SC_CMPINV EQU 0x40005b9b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_CPTR +CYDEV_ANAIF_WRK_SC_CPTR EQU 0x40005b9c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_BASE +CYDEV_ANAIF_WRK_SAR0_BASE EQU 0x40005ba0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_SIZE +CYDEV_ANAIF_WRK_SAR0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_WRK0 +CYDEV_ANAIF_WRK_SAR0_WRK0 EQU 0x40005ba0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_WRK1 +CYDEV_ANAIF_WRK_SAR0_WRK1 EQU 0x40005ba1 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_BASE +CYDEV_ANAIF_WRK_SAR1_BASE EQU 0x40005ba2 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_SIZE +CYDEV_ANAIF_WRK_SAR1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_WRK0 +CYDEV_ANAIF_WRK_SAR1_WRK0 EQU 0x40005ba2 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_WRK1 +CYDEV_ANAIF_WRK_SAR1_WRK1 EQU 0x40005ba3 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_BASE +CYDEV_ANAIF_WRK_SARS_BASE EQU 0x40005ba8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_SIZE +CYDEV_ANAIF_WRK_SARS_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_SOF +CYDEV_ANAIF_WRK_SARS_SOF EQU 0x40005ba8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_BASE +CYDEV_USB_BASE EQU 0x40006000 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIZE +CYDEV_USB_SIZE EQU 0x00000300 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR0 +CYDEV_USB_EP0_DR0 EQU 0x40006000 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR1 +CYDEV_USB_EP0_DR1 EQU 0x40006001 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR2 +CYDEV_USB_EP0_DR2 EQU 0x40006002 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR3 +CYDEV_USB_EP0_DR3 EQU 0x40006003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR4 +CYDEV_USB_EP0_DR4 EQU 0x40006004 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR5 +CYDEV_USB_EP0_DR5 EQU 0x40006005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR6 +CYDEV_USB_EP0_DR6 EQU 0x40006006 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR7 +CYDEV_USB_EP0_DR7 EQU 0x40006007 + ENDIF + IF :LNOT::DEF:CYDEV_USB_CR0 +CYDEV_USB_CR0 EQU 0x40006008 + ENDIF + IF :LNOT::DEF:CYDEV_USB_CR1 +CYDEV_USB_CR1 EQU 0x40006009 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP_INT_EN +CYDEV_USB_SIE_EP_INT_EN EQU 0x4000600a + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP_INT_SR +CYDEV_USB_SIE_EP_INT_SR EQU 0x4000600b + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_BASE +CYDEV_USB_SIE_EP1_BASE EQU 0x4000600c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_SIZE +CYDEV_USB_SIE_EP1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_CNT0 +CYDEV_USB_SIE_EP1_CNT0 EQU 0x4000600c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_CNT1 +CYDEV_USB_SIE_EP1_CNT1 EQU 0x4000600d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_CR0 +CYDEV_USB_SIE_EP1_CR0 EQU 0x4000600e + ENDIF + IF :LNOT::DEF:CYDEV_USB_USBIO_CR0 +CYDEV_USB_USBIO_CR0 EQU 0x40006010 + ENDIF + IF :LNOT::DEF:CYDEV_USB_USBIO_CR1 +CYDEV_USB_USBIO_CR1 EQU 0x40006012 + ENDIF + IF :LNOT::DEF:CYDEV_USB_DYN_RECONFIG +CYDEV_USB_DYN_RECONFIG EQU 0x40006014 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SOF0 +CYDEV_USB_SOF0 EQU 0x40006018 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SOF1 +CYDEV_USB_SOF1 EQU 0x40006019 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_BASE +CYDEV_USB_SIE_EP2_BASE EQU 0x4000601c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_SIZE +CYDEV_USB_SIE_EP2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_CNT0 +CYDEV_USB_SIE_EP2_CNT0 EQU 0x4000601c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_CNT1 +CYDEV_USB_SIE_EP2_CNT1 EQU 0x4000601d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_CR0 +CYDEV_USB_SIE_EP2_CR0 EQU 0x4000601e + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_CR +CYDEV_USB_EP0_CR EQU 0x40006028 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_CNT +CYDEV_USB_EP0_CNT EQU 0x40006029 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_BASE +CYDEV_USB_SIE_EP3_BASE EQU 0x4000602c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_SIZE +CYDEV_USB_SIE_EP3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_CNT0 +CYDEV_USB_SIE_EP3_CNT0 EQU 0x4000602c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_CNT1 +CYDEV_USB_SIE_EP3_CNT1 EQU 0x4000602d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_CR0 +CYDEV_USB_SIE_EP3_CR0 EQU 0x4000602e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_BASE +CYDEV_USB_SIE_EP4_BASE EQU 0x4000603c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_SIZE +CYDEV_USB_SIE_EP4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_CNT0 +CYDEV_USB_SIE_EP4_CNT0 EQU 0x4000603c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_CNT1 +CYDEV_USB_SIE_EP4_CNT1 EQU 0x4000603d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_CR0 +CYDEV_USB_SIE_EP4_CR0 EQU 0x4000603e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_BASE +CYDEV_USB_SIE_EP5_BASE EQU 0x4000604c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_SIZE +CYDEV_USB_SIE_EP5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_CNT0 +CYDEV_USB_SIE_EP5_CNT0 EQU 0x4000604c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_CNT1 +CYDEV_USB_SIE_EP5_CNT1 EQU 0x4000604d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_CR0 +CYDEV_USB_SIE_EP5_CR0 EQU 0x4000604e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_BASE +CYDEV_USB_SIE_EP6_BASE EQU 0x4000605c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_SIZE +CYDEV_USB_SIE_EP6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_CNT0 +CYDEV_USB_SIE_EP6_CNT0 EQU 0x4000605c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_CNT1 +CYDEV_USB_SIE_EP6_CNT1 EQU 0x4000605d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_CR0 +CYDEV_USB_SIE_EP6_CR0 EQU 0x4000605e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_BASE +CYDEV_USB_SIE_EP7_BASE EQU 0x4000606c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_SIZE +CYDEV_USB_SIE_EP7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_CNT0 +CYDEV_USB_SIE_EP7_CNT0 EQU 0x4000606c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_CNT1 +CYDEV_USB_SIE_EP7_CNT1 EQU 0x4000606d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_CR0 +CYDEV_USB_SIE_EP7_CR0 EQU 0x4000606e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_BASE +CYDEV_USB_SIE_EP8_BASE EQU 0x4000607c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_SIZE +CYDEV_USB_SIE_EP8_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_CNT0 +CYDEV_USB_SIE_EP8_CNT0 EQU 0x4000607c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_CNT1 +CYDEV_USB_SIE_EP8_CNT1 EQU 0x4000607d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_CR0 +CYDEV_USB_SIE_EP8_CR0 EQU 0x4000607e + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_BASE +CYDEV_USB_ARB_EP1_BASE EQU 0x40006080 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_SIZE +CYDEV_USB_ARB_EP1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_CFG +CYDEV_USB_ARB_EP1_CFG EQU 0x40006080 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_INT_EN +CYDEV_USB_ARB_EP1_INT_EN EQU 0x40006081 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_SR +CYDEV_USB_ARB_EP1_SR EQU 0x40006082 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_BASE +CYDEV_USB_ARB_RW1_BASE EQU 0x40006084 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_SIZE +CYDEV_USB_ARB_RW1_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_WA +CYDEV_USB_ARB_RW1_WA EQU 0x40006084 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_WA_MSB +CYDEV_USB_ARB_RW1_WA_MSB EQU 0x40006085 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_RA +CYDEV_USB_ARB_RW1_RA EQU 0x40006086 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_RA_MSB +CYDEV_USB_ARB_RW1_RA_MSB EQU 0x40006087 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_DR +CYDEV_USB_ARB_RW1_DR EQU 0x40006088 + ENDIF + IF :LNOT::DEF:CYDEV_USB_BUF_SIZE +CYDEV_USB_BUF_SIZE EQU 0x4000608c + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP_ACTIVE +CYDEV_USB_EP_ACTIVE EQU 0x4000608e + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP_TYPE +CYDEV_USB_EP_TYPE EQU 0x4000608f + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_BASE +CYDEV_USB_ARB_EP2_BASE EQU 0x40006090 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_SIZE +CYDEV_USB_ARB_EP2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_CFG +CYDEV_USB_ARB_EP2_CFG EQU 0x40006090 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_INT_EN +CYDEV_USB_ARB_EP2_INT_EN EQU 0x40006091 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_SR +CYDEV_USB_ARB_EP2_SR EQU 0x40006092 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_BASE +CYDEV_USB_ARB_RW2_BASE EQU 0x40006094 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_SIZE +CYDEV_USB_ARB_RW2_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_WA +CYDEV_USB_ARB_RW2_WA EQU 0x40006094 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_WA_MSB +CYDEV_USB_ARB_RW2_WA_MSB EQU 0x40006095 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_RA +CYDEV_USB_ARB_RW2_RA EQU 0x40006096 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_RA_MSB +CYDEV_USB_ARB_RW2_RA_MSB EQU 0x40006097 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_DR +CYDEV_USB_ARB_RW2_DR EQU 0x40006098 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_CFG +CYDEV_USB_ARB_CFG EQU 0x4000609c + ENDIF + IF :LNOT::DEF:CYDEV_USB_USB_CLK_EN +CYDEV_USB_USB_CLK_EN EQU 0x4000609d + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_INT_EN +CYDEV_USB_ARB_INT_EN EQU 0x4000609e + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_INT_SR +CYDEV_USB_ARB_INT_SR EQU 0x4000609f + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_BASE +CYDEV_USB_ARB_EP3_BASE EQU 0x400060a0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_SIZE +CYDEV_USB_ARB_EP3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_CFG +CYDEV_USB_ARB_EP3_CFG EQU 0x400060a0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_INT_EN +CYDEV_USB_ARB_EP3_INT_EN EQU 0x400060a1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_SR +CYDEV_USB_ARB_EP3_SR EQU 0x400060a2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_BASE +CYDEV_USB_ARB_RW3_BASE EQU 0x400060a4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_SIZE +CYDEV_USB_ARB_RW3_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_WA +CYDEV_USB_ARB_RW3_WA EQU 0x400060a4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_WA_MSB +CYDEV_USB_ARB_RW3_WA_MSB EQU 0x400060a5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_RA +CYDEV_USB_ARB_RW3_RA EQU 0x400060a6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_RA_MSB +CYDEV_USB_ARB_RW3_RA_MSB EQU 0x400060a7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_DR +CYDEV_USB_ARB_RW3_DR EQU 0x400060a8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_CWA +CYDEV_USB_CWA EQU 0x400060ac + ENDIF + IF :LNOT::DEF:CYDEV_USB_CWA_MSB +CYDEV_USB_CWA_MSB EQU 0x400060ad + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_BASE +CYDEV_USB_ARB_EP4_BASE EQU 0x400060b0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_SIZE +CYDEV_USB_ARB_EP4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_CFG +CYDEV_USB_ARB_EP4_CFG EQU 0x400060b0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_INT_EN +CYDEV_USB_ARB_EP4_INT_EN EQU 0x400060b1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_SR +CYDEV_USB_ARB_EP4_SR EQU 0x400060b2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_BASE +CYDEV_USB_ARB_RW4_BASE EQU 0x400060b4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_SIZE +CYDEV_USB_ARB_RW4_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_WA +CYDEV_USB_ARB_RW4_WA EQU 0x400060b4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_WA_MSB +CYDEV_USB_ARB_RW4_WA_MSB EQU 0x400060b5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_RA +CYDEV_USB_ARB_RW4_RA EQU 0x400060b6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_RA_MSB +CYDEV_USB_ARB_RW4_RA_MSB EQU 0x400060b7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_DR +CYDEV_USB_ARB_RW4_DR EQU 0x400060b8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_DMA_THRES +CYDEV_USB_DMA_THRES EQU 0x400060bc + ENDIF + IF :LNOT::DEF:CYDEV_USB_DMA_THRES_MSB +CYDEV_USB_DMA_THRES_MSB EQU 0x400060bd + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_BASE +CYDEV_USB_ARB_EP5_BASE EQU 0x400060c0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_SIZE +CYDEV_USB_ARB_EP5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_CFG +CYDEV_USB_ARB_EP5_CFG EQU 0x400060c0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_INT_EN +CYDEV_USB_ARB_EP5_INT_EN EQU 0x400060c1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_SR +CYDEV_USB_ARB_EP5_SR EQU 0x400060c2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_BASE +CYDEV_USB_ARB_RW5_BASE EQU 0x400060c4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_SIZE +CYDEV_USB_ARB_RW5_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_WA +CYDEV_USB_ARB_RW5_WA EQU 0x400060c4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_WA_MSB +CYDEV_USB_ARB_RW5_WA_MSB EQU 0x400060c5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_RA +CYDEV_USB_ARB_RW5_RA EQU 0x400060c6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_RA_MSB +CYDEV_USB_ARB_RW5_RA_MSB EQU 0x400060c7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_DR +CYDEV_USB_ARB_RW5_DR EQU 0x400060c8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_BUS_RST_CNT +CYDEV_USB_BUS_RST_CNT EQU 0x400060cc + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_BASE +CYDEV_USB_ARB_EP6_BASE EQU 0x400060d0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_SIZE +CYDEV_USB_ARB_EP6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_CFG +CYDEV_USB_ARB_EP6_CFG EQU 0x400060d0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_INT_EN +CYDEV_USB_ARB_EP6_INT_EN EQU 0x400060d1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_SR +CYDEV_USB_ARB_EP6_SR EQU 0x400060d2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_BASE +CYDEV_USB_ARB_RW6_BASE EQU 0x400060d4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_SIZE +CYDEV_USB_ARB_RW6_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_WA +CYDEV_USB_ARB_RW6_WA EQU 0x400060d4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_WA_MSB +CYDEV_USB_ARB_RW6_WA_MSB EQU 0x400060d5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_RA +CYDEV_USB_ARB_RW6_RA EQU 0x400060d6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_RA_MSB +CYDEV_USB_ARB_RW6_RA_MSB EQU 0x400060d7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_DR +CYDEV_USB_ARB_RW6_DR EQU 0x400060d8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_BASE +CYDEV_USB_ARB_EP7_BASE EQU 0x400060e0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_SIZE +CYDEV_USB_ARB_EP7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_CFG +CYDEV_USB_ARB_EP7_CFG EQU 0x400060e0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_INT_EN +CYDEV_USB_ARB_EP7_INT_EN EQU 0x400060e1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_SR +CYDEV_USB_ARB_EP7_SR EQU 0x400060e2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_BASE +CYDEV_USB_ARB_RW7_BASE EQU 0x400060e4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_SIZE +CYDEV_USB_ARB_RW7_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_WA +CYDEV_USB_ARB_RW7_WA EQU 0x400060e4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_WA_MSB +CYDEV_USB_ARB_RW7_WA_MSB EQU 0x400060e5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_RA +CYDEV_USB_ARB_RW7_RA EQU 0x400060e6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_RA_MSB +CYDEV_USB_ARB_RW7_RA_MSB EQU 0x400060e7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_DR +CYDEV_USB_ARB_RW7_DR EQU 0x400060e8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_BASE +CYDEV_USB_ARB_EP8_BASE EQU 0x400060f0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_SIZE +CYDEV_USB_ARB_EP8_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_CFG +CYDEV_USB_ARB_EP8_CFG EQU 0x400060f0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_INT_EN +CYDEV_USB_ARB_EP8_INT_EN EQU 0x400060f1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_SR +CYDEV_USB_ARB_EP8_SR EQU 0x400060f2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_BASE +CYDEV_USB_ARB_RW8_BASE EQU 0x400060f4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_SIZE +CYDEV_USB_ARB_RW8_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_WA +CYDEV_USB_ARB_RW8_WA EQU 0x400060f4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_WA_MSB +CYDEV_USB_ARB_RW8_WA_MSB EQU 0x400060f5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_RA +CYDEV_USB_ARB_RW8_RA EQU 0x400060f6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_RA_MSB +CYDEV_USB_ARB_RW8_RA_MSB EQU 0x400060f7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_DR +CYDEV_USB_ARB_RW8_DR EQU 0x400060f8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_BASE +CYDEV_USB_MEM_BASE EQU 0x40006100 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_SIZE +CYDEV_USB_MEM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_DATA_MBASE +CYDEV_USB_MEM_DATA_MBASE EQU 0x40006100 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_DATA_MSIZE +CYDEV_USB_MEM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_BASE +CYDEV_UWRK_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_SIZE +CYDEV_UWRK_SIZE EQU 0x00000b60 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_BASE +CYDEV_UWRK_UWRK8_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_SIZE +CYDEV_UWRK_UWRK8_SIZE EQU 0x000003b0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_BASE +CYDEV_UWRK_UWRK8_B0_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_SIZE +CYDEV_UWRK_UWRK8_B0_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_A0 +CYDEV_UWRK_UWRK8_B0_UDB00_A0 EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_A0 +CYDEV_UWRK_UWRK8_B0_UDB01_A0 EQU 0x40006401 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_A0 +CYDEV_UWRK_UWRK8_B0_UDB02_A0 EQU 0x40006402 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_A0 +CYDEV_UWRK_UWRK8_B0_UDB03_A0 EQU 0x40006403 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_A0 +CYDEV_UWRK_UWRK8_B0_UDB04_A0 EQU 0x40006404 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_A0 +CYDEV_UWRK_UWRK8_B0_UDB05_A0 EQU 0x40006405 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_A0 +CYDEV_UWRK_UWRK8_B0_UDB06_A0 EQU 0x40006406 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_A0 +CYDEV_UWRK_UWRK8_B0_UDB07_A0 EQU 0x40006407 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_A0 +CYDEV_UWRK_UWRK8_B0_UDB08_A0 EQU 0x40006408 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_A0 +CYDEV_UWRK_UWRK8_B0_UDB09_A0 EQU 0x40006409 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_A0 +CYDEV_UWRK_UWRK8_B0_UDB10_A0 EQU 0x4000640a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_A0 +CYDEV_UWRK_UWRK8_B0_UDB11_A0 EQU 0x4000640b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_A0 +CYDEV_UWRK_UWRK8_B0_UDB12_A0 EQU 0x4000640c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_A0 +CYDEV_UWRK_UWRK8_B0_UDB13_A0 EQU 0x4000640d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_A0 +CYDEV_UWRK_UWRK8_B0_UDB14_A0 EQU 0x4000640e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_A0 +CYDEV_UWRK_UWRK8_B0_UDB15_A0 EQU 0x4000640f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_A1 +CYDEV_UWRK_UWRK8_B0_UDB00_A1 EQU 0x40006410 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_A1 +CYDEV_UWRK_UWRK8_B0_UDB01_A1 EQU 0x40006411 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_A1 +CYDEV_UWRK_UWRK8_B0_UDB02_A1 EQU 0x40006412 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_A1 +CYDEV_UWRK_UWRK8_B0_UDB03_A1 EQU 0x40006413 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_A1 +CYDEV_UWRK_UWRK8_B0_UDB04_A1 EQU 0x40006414 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_A1 +CYDEV_UWRK_UWRK8_B0_UDB05_A1 EQU 0x40006415 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_A1 +CYDEV_UWRK_UWRK8_B0_UDB06_A1 EQU 0x40006416 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_A1 +CYDEV_UWRK_UWRK8_B0_UDB07_A1 EQU 0x40006417 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_A1 +CYDEV_UWRK_UWRK8_B0_UDB08_A1 EQU 0x40006418 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_A1 +CYDEV_UWRK_UWRK8_B0_UDB09_A1 EQU 0x40006419 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_A1 +CYDEV_UWRK_UWRK8_B0_UDB10_A1 EQU 0x4000641a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_A1 +CYDEV_UWRK_UWRK8_B0_UDB11_A1 EQU 0x4000641b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_A1 +CYDEV_UWRK_UWRK8_B0_UDB12_A1 EQU 0x4000641c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_A1 +CYDEV_UWRK_UWRK8_B0_UDB13_A1 EQU 0x4000641d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_A1 +CYDEV_UWRK_UWRK8_B0_UDB14_A1 EQU 0x4000641e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_A1 +CYDEV_UWRK_UWRK8_B0_UDB15_A1 EQU 0x4000641f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_D0 +CYDEV_UWRK_UWRK8_B0_UDB00_D0 EQU 0x40006420 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_D0 +CYDEV_UWRK_UWRK8_B0_UDB01_D0 EQU 0x40006421 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_D0 +CYDEV_UWRK_UWRK8_B0_UDB02_D0 EQU 0x40006422 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_D0 +CYDEV_UWRK_UWRK8_B0_UDB03_D0 EQU 0x40006423 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_D0 +CYDEV_UWRK_UWRK8_B0_UDB04_D0 EQU 0x40006424 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_D0 +CYDEV_UWRK_UWRK8_B0_UDB05_D0 EQU 0x40006425 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_D0 +CYDEV_UWRK_UWRK8_B0_UDB06_D0 EQU 0x40006426 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_D0 +CYDEV_UWRK_UWRK8_B0_UDB07_D0 EQU 0x40006427 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_D0 +CYDEV_UWRK_UWRK8_B0_UDB08_D0 EQU 0x40006428 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_D0 +CYDEV_UWRK_UWRK8_B0_UDB09_D0 EQU 0x40006429 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_D0 +CYDEV_UWRK_UWRK8_B0_UDB10_D0 EQU 0x4000642a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_D0 +CYDEV_UWRK_UWRK8_B0_UDB11_D0 EQU 0x4000642b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_D0 +CYDEV_UWRK_UWRK8_B0_UDB12_D0 EQU 0x4000642c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_D0 +CYDEV_UWRK_UWRK8_B0_UDB13_D0 EQU 0x4000642d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_D0 +CYDEV_UWRK_UWRK8_B0_UDB14_D0 EQU 0x4000642e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_D0 +CYDEV_UWRK_UWRK8_B0_UDB15_D0 EQU 0x4000642f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_D1 +CYDEV_UWRK_UWRK8_B0_UDB00_D1 EQU 0x40006430 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_D1 +CYDEV_UWRK_UWRK8_B0_UDB01_D1 EQU 0x40006431 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_D1 +CYDEV_UWRK_UWRK8_B0_UDB02_D1 EQU 0x40006432 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_D1 +CYDEV_UWRK_UWRK8_B0_UDB03_D1 EQU 0x40006433 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_D1 +CYDEV_UWRK_UWRK8_B0_UDB04_D1 EQU 0x40006434 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_D1 +CYDEV_UWRK_UWRK8_B0_UDB05_D1 EQU 0x40006435 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_D1 +CYDEV_UWRK_UWRK8_B0_UDB06_D1 EQU 0x40006436 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_D1 +CYDEV_UWRK_UWRK8_B0_UDB07_D1 EQU 0x40006437 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_D1 +CYDEV_UWRK_UWRK8_B0_UDB08_D1 EQU 0x40006438 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_D1 +CYDEV_UWRK_UWRK8_B0_UDB09_D1 EQU 0x40006439 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_D1 +CYDEV_UWRK_UWRK8_B0_UDB10_D1 EQU 0x4000643a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_D1 +CYDEV_UWRK_UWRK8_B0_UDB11_D1 EQU 0x4000643b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_D1 +CYDEV_UWRK_UWRK8_B0_UDB12_D1 EQU 0x4000643c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_D1 +CYDEV_UWRK_UWRK8_B0_UDB13_D1 EQU 0x4000643d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_D1 +CYDEV_UWRK_UWRK8_B0_UDB14_D1 EQU 0x4000643e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_D1 +CYDEV_UWRK_UWRK8_B0_UDB15_D1 EQU 0x4000643f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_F0 +CYDEV_UWRK_UWRK8_B0_UDB00_F0 EQU 0x40006440 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_F0 +CYDEV_UWRK_UWRK8_B0_UDB01_F0 EQU 0x40006441 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_F0 +CYDEV_UWRK_UWRK8_B0_UDB02_F0 EQU 0x40006442 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_F0 +CYDEV_UWRK_UWRK8_B0_UDB03_F0 EQU 0x40006443 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_F0 +CYDEV_UWRK_UWRK8_B0_UDB04_F0 EQU 0x40006444 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_F0 +CYDEV_UWRK_UWRK8_B0_UDB05_F0 EQU 0x40006445 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_F0 +CYDEV_UWRK_UWRK8_B0_UDB06_F0 EQU 0x40006446 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_F0 +CYDEV_UWRK_UWRK8_B0_UDB07_F0 EQU 0x40006447 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_F0 +CYDEV_UWRK_UWRK8_B0_UDB08_F0 EQU 0x40006448 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_F0 +CYDEV_UWRK_UWRK8_B0_UDB09_F0 EQU 0x40006449 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_F0 +CYDEV_UWRK_UWRK8_B0_UDB10_F0 EQU 0x4000644a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_F0 +CYDEV_UWRK_UWRK8_B0_UDB11_F0 EQU 0x4000644b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_F0 +CYDEV_UWRK_UWRK8_B0_UDB12_F0 EQU 0x4000644c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_F0 +CYDEV_UWRK_UWRK8_B0_UDB13_F0 EQU 0x4000644d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_F0 +CYDEV_UWRK_UWRK8_B0_UDB14_F0 EQU 0x4000644e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_F0 +CYDEV_UWRK_UWRK8_B0_UDB15_F0 EQU 0x4000644f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_F1 +CYDEV_UWRK_UWRK8_B0_UDB00_F1 EQU 0x40006450 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_F1 +CYDEV_UWRK_UWRK8_B0_UDB01_F1 EQU 0x40006451 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_F1 +CYDEV_UWRK_UWRK8_B0_UDB02_F1 EQU 0x40006452 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_F1 +CYDEV_UWRK_UWRK8_B0_UDB03_F1 EQU 0x40006453 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_F1 +CYDEV_UWRK_UWRK8_B0_UDB04_F1 EQU 0x40006454 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_F1 +CYDEV_UWRK_UWRK8_B0_UDB05_F1 EQU 0x40006455 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_F1 +CYDEV_UWRK_UWRK8_B0_UDB06_F1 EQU 0x40006456 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_F1 +CYDEV_UWRK_UWRK8_B0_UDB07_F1 EQU 0x40006457 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_F1 +CYDEV_UWRK_UWRK8_B0_UDB08_F1 EQU 0x40006458 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_F1 +CYDEV_UWRK_UWRK8_B0_UDB09_F1 EQU 0x40006459 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_F1 +CYDEV_UWRK_UWRK8_B0_UDB10_F1 EQU 0x4000645a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_F1 +CYDEV_UWRK_UWRK8_B0_UDB11_F1 EQU 0x4000645b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_F1 +CYDEV_UWRK_UWRK8_B0_UDB12_F1 EQU 0x4000645c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_F1 +CYDEV_UWRK_UWRK8_B0_UDB13_F1 EQU 0x4000645d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_F1 +CYDEV_UWRK_UWRK8_B0_UDB14_F1 EQU 0x4000645e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_F1 +CYDEV_UWRK_UWRK8_B0_UDB15_F1 EQU 0x4000645f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_ST +CYDEV_UWRK_UWRK8_B0_UDB00_ST EQU 0x40006460 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_ST +CYDEV_UWRK_UWRK8_B0_UDB01_ST EQU 0x40006461 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_ST +CYDEV_UWRK_UWRK8_B0_UDB02_ST EQU 0x40006462 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_ST +CYDEV_UWRK_UWRK8_B0_UDB03_ST EQU 0x40006463 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_ST +CYDEV_UWRK_UWRK8_B0_UDB04_ST EQU 0x40006464 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_ST +CYDEV_UWRK_UWRK8_B0_UDB05_ST EQU 0x40006465 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_ST +CYDEV_UWRK_UWRK8_B0_UDB06_ST EQU 0x40006466 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_ST +CYDEV_UWRK_UWRK8_B0_UDB07_ST EQU 0x40006467 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_ST +CYDEV_UWRK_UWRK8_B0_UDB08_ST EQU 0x40006468 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_ST +CYDEV_UWRK_UWRK8_B0_UDB09_ST EQU 0x40006469 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_ST +CYDEV_UWRK_UWRK8_B0_UDB10_ST EQU 0x4000646a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_ST +CYDEV_UWRK_UWRK8_B0_UDB11_ST EQU 0x4000646b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_ST +CYDEV_UWRK_UWRK8_B0_UDB12_ST EQU 0x4000646c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_ST +CYDEV_UWRK_UWRK8_B0_UDB13_ST EQU 0x4000646d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_ST +CYDEV_UWRK_UWRK8_B0_UDB14_ST EQU 0x4000646e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_ST +CYDEV_UWRK_UWRK8_B0_UDB15_ST EQU 0x4000646f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_CTL +CYDEV_UWRK_UWRK8_B0_UDB00_CTL EQU 0x40006470 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_CTL +CYDEV_UWRK_UWRK8_B0_UDB01_CTL EQU 0x40006471 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_CTL +CYDEV_UWRK_UWRK8_B0_UDB02_CTL EQU 0x40006472 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_CTL +CYDEV_UWRK_UWRK8_B0_UDB03_CTL EQU 0x40006473 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_CTL +CYDEV_UWRK_UWRK8_B0_UDB04_CTL EQU 0x40006474 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_CTL +CYDEV_UWRK_UWRK8_B0_UDB05_CTL EQU 0x40006475 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_CTL +CYDEV_UWRK_UWRK8_B0_UDB06_CTL EQU 0x40006476 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_CTL +CYDEV_UWRK_UWRK8_B0_UDB07_CTL EQU 0x40006477 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_CTL +CYDEV_UWRK_UWRK8_B0_UDB08_CTL EQU 0x40006478 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_CTL +CYDEV_UWRK_UWRK8_B0_UDB09_CTL EQU 0x40006479 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_CTL +CYDEV_UWRK_UWRK8_B0_UDB10_CTL EQU 0x4000647a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_CTL +CYDEV_UWRK_UWRK8_B0_UDB11_CTL EQU 0x4000647b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_CTL +CYDEV_UWRK_UWRK8_B0_UDB12_CTL EQU 0x4000647c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_CTL +CYDEV_UWRK_UWRK8_B0_UDB13_CTL EQU 0x4000647d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_CTL +CYDEV_UWRK_UWRK8_B0_UDB14_CTL EQU 0x4000647e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_CTL +CYDEV_UWRK_UWRK8_B0_UDB15_CTL EQU 0x4000647f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_MSK +CYDEV_UWRK_UWRK8_B0_UDB00_MSK EQU 0x40006480 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_MSK +CYDEV_UWRK_UWRK8_B0_UDB01_MSK EQU 0x40006481 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_MSK +CYDEV_UWRK_UWRK8_B0_UDB02_MSK EQU 0x40006482 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_MSK +CYDEV_UWRK_UWRK8_B0_UDB03_MSK EQU 0x40006483 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_MSK +CYDEV_UWRK_UWRK8_B0_UDB04_MSK EQU 0x40006484 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_MSK +CYDEV_UWRK_UWRK8_B0_UDB05_MSK EQU 0x40006485 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_MSK +CYDEV_UWRK_UWRK8_B0_UDB06_MSK EQU 0x40006486 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_MSK +CYDEV_UWRK_UWRK8_B0_UDB07_MSK EQU 0x40006487 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_MSK +CYDEV_UWRK_UWRK8_B0_UDB08_MSK EQU 0x40006488 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_MSK +CYDEV_UWRK_UWRK8_B0_UDB09_MSK EQU 0x40006489 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_MSK +CYDEV_UWRK_UWRK8_B0_UDB10_MSK EQU 0x4000648a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_MSK +CYDEV_UWRK_UWRK8_B0_UDB11_MSK EQU 0x4000648b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_MSK +CYDEV_UWRK_UWRK8_B0_UDB12_MSK EQU 0x4000648c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_MSK +CYDEV_UWRK_UWRK8_B0_UDB13_MSK EQU 0x4000648d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_MSK +CYDEV_UWRK_UWRK8_B0_UDB14_MSK EQU 0x4000648e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_MSK +CYDEV_UWRK_UWRK8_B0_UDB15_MSK EQU 0x4000648f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_ACTL +CYDEV_UWRK_UWRK8_B0_UDB00_ACTL EQU 0x40006490 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_ACTL +CYDEV_UWRK_UWRK8_B0_UDB01_ACTL EQU 0x40006491 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_ACTL +CYDEV_UWRK_UWRK8_B0_UDB02_ACTL EQU 0x40006492 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_ACTL +CYDEV_UWRK_UWRK8_B0_UDB03_ACTL EQU 0x40006493 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_ACTL +CYDEV_UWRK_UWRK8_B0_UDB04_ACTL EQU 0x40006494 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_ACTL +CYDEV_UWRK_UWRK8_B0_UDB05_ACTL EQU 0x40006495 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_ACTL +CYDEV_UWRK_UWRK8_B0_UDB06_ACTL EQU 0x40006496 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_ACTL +CYDEV_UWRK_UWRK8_B0_UDB07_ACTL EQU 0x40006497 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_ACTL +CYDEV_UWRK_UWRK8_B0_UDB08_ACTL EQU 0x40006498 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_ACTL +CYDEV_UWRK_UWRK8_B0_UDB09_ACTL EQU 0x40006499 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_ACTL +CYDEV_UWRK_UWRK8_B0_UDB10_ACTL EQU 0x4000649a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_ACTL +CYDEV_UWRK_UWRK8_B0_UDB11_ACTL EQU 0x4000649b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_ACTL +CYDEV_UWRK_UWRK8_B0_UDB12_ACTL EQU 0x4000649c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_ACTL +CYDEV_UWRK_UWRK8_B0_UDB13_ACTL EQU 0x4000649d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_ACTL +CYDEV_UWRK_UWRK8_B0_UDB14_ACTL EQU 0x4000649e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_ACTL +CYDEV_UWRK_UWRK8_B0_UDB15_ACTL EQU 0x4000649f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_MC +CYDEV_UWRK_UWRK8_B0_UDB00_MC EQU 0x400064a0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_MC +CYDEV_UWRK_UWRK8_B0_UDB01_MC EQU 0x400064a1 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_MC +CYDEV_UWRK_UWRK8_B0_UDB02_MC EQU 0x400064a2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_MC +CYDEV_UWRK_UWRK8_B0_UDB03_MC EQU 0x400064a3 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_MC +CYDEV_UWRK_UWRK8_B0_UDB04_MC EQU 0x400064a4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_MC +CYDEV_UWRK_UWRK8_B0_UDB05_MC EQU 0x400064a5 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_MC +CYDEV_UWRK_UWRK8_B0_UDB06_MC EQU 0x400064a6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_MC +CYDEV_UWRK_UWRK8_B0_UDB07_MC EQU 0x400064a7 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_MC +CYDEV_UWRK_UWRK8_B0_UDB08_MC EQU 0x400064a8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_MC +CYDEV_UWRK_UWRK8_B0_UDB09_MC EQU 0x400064a9 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_MC +CYDEV_UWRK_UWRK8_B0_UDB10_MC EQU 0x400064aa + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_MC +CYDEV_UWRK_UWRK8_B0_UDB11_MC EQU 0x400064ab + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_MC +CYDEV_UWRK_UWRK8_B0_UDB12_MC EQU 0x400064ac + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_MC +CYDEV_UWRK_UWRK8_B0_UDB13_MC EQU 0x400064ad + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_MC +CYDEV_UWRK_UWRK8_B0_UDB14_MC EQU 0x400064ae + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_MC +CYDEV_UWRK_UWRK8_B0_UDB15_MC EQU 0x400064af + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_BASE +CYDEV_UWRK_UWRK8_B1_BASE EQU 0x40006500 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_SIZE +CYDEV_UWRK_UWRK8_B1_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_A0 +CYDEV_UWRK_UWRK8_B1_UDB04_A0 EQU 0x40006504 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_A0 +CYDEV_UWRK_UWRK8_B1_UDB05_A0 EQU 0x40006505 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_A0 +CYDEV_UWRK_UWRK8_B1_UDB06_A0 EQU 0x40006506 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_A0 +CYDEV_UWRK_UWRK8_B1_UDB07_A0 EQU 0x40006507 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_A0 +CYDEV_UWRK_UWRK8_B1_UDB08_A0 EQU 0x40006508 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_A0 +CYDEV_UWRK_UWRK8_B1_UDB09_A0 EQU 0x40006509 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_A0 +CYDEV_UWRK_UWRK8_B1_UDB10_A0 EQU 0x4000650a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_A0 +CYDEV_UWRK_UWRK8_B1_UDB11_A0 EQU 0x4000650b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_A1 +CYDEV_UWRK_UWRK8_B1_UDB04_A1 EQU 0x40006514 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_A1 +CYDEV_UWRK_UWRK8_B1_UDB05_A1 EQU 0x40006515 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_A1 +CYDEV_UWRK_UWRK8_B1_UDB06_A1 EQU 0x40006516 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_A1 +CYDEV_UWRK_UWRK8_B1_UDB07_A1 EQU 0x40006517 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_A1 +CYDEV_UWRK_UWRK8_B1_UDB08_A1 EQU 0x40006518 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_A1 +CYDEV_UWRK_UWRK8_B1_UDB09_A1 EQU 0x40006519 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_A1 +CYDEV_UWRK_UWRK8_B1_UDB10_A1 EQU 0x4000651a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_A1 +CYDEV_UWRK_UWRK8_B1_UDB11_A1 EQU 0x4000651b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_D0 +CYDEV_UWRK_UWRK8_B1_UDB04_D0 EQU 0x40006524 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_D0 +CYDEV_UWRK_UWRK8_B1_UDB05_D0 EQU 0x40006525 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_D0 +CYDEV_UWRK_UWRK8_B1_UDB06_D0 EQU 0x40006526 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_D0 +CYDEV_UWRK_UWRK8_B1_UDB07_D0 EQU 0x40006527 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_D0 +CYDEV_UWRK_UWRK8_B1_UDB08_D0 EQU 0x40006528 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_D0 +CYDEV_UWRK_UWRK8_B1_UDB09_D0 EQU 0x40006529 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_D0 +CYDEV_UWRK_UWRK8_B1_UDB10_D0 EQU 0x4000652a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_D0 +CYDEV_UWRK_UWRK8_B1_UDB11_D0 EQU 0x4000652b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_D1 +CYDEV_UWRK_UWRK8_B1_UDB04_D1 EQU 0x40006534 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_D1 +CYDEV_UWRK_UWRK8_B1_UDB05_D1 EQU 0x40006535 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_D1 +CYDEV_UWRK_UWRK8_B1_UDB06_D1 EQU 0x40006536 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_D1 +CYDEV_UWRK_UWRK8_B1_UDB07_D1 EQU 0x40006537 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_D1 +CYDEV_UWRK_UWRK8_B1_UDB08_D1 EQU 0x40006538 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_D1 +CYDEV_UWRK_UWRK8_B1_UDB09_D1 EQU 0x40006539 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_D1 +CYDEV_UWRK_UWRK8_B1_UDB10_D1 EQU 0x4000653a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_D1 +CYDEV_UWRK_UWRK8_B1_UDB11_D1 EQU 0x4000653b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_F0 +CYDEV_UWRK_UWRK8_B1_UDB04_F0 EQU 0x40006544 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_F0 +CYDEV_UWRK_UWRK8_B1_UDB05_F0 EQU 0x40006545 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_F0 +CYDEV_UWRK_UWRK8_B1_UDB06_F0 EQU 0x40006546 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_F0 +CYDEV_UWRK_UWRK8_B1_UDB07_F0 EQU 0x40006547 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_F0 +CYDEV_UWRK_UWRK8_B1_UDB08_F0 EQU 0x40006548 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_F0 +CYDEV_UWRK_UWRK8_B1_UDB09_F0 EQU 0x40006549 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_F0 +CYDEV_UWRK_UWRK8_B1_UDB10_F0 EQU 0x4000654a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_F0 +CYDEV_UWRK_UWRK8_B1_UDB11_F0 EQU 0x4000654b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_F1 +CYDEV_UWRK_UWRK8_B1_UDB04_F1 EQU 0x40006554 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_F1 +CYDEV_UWRK_UWRK8_B1_UDB05_F1 EQU 0x40006555 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_F1 +CYDEV_UWRK_UWRK8_B1_UDB06_F1 EQU 0x40006556 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_F1 +CYDEV_UWRK_UWRK8_B1_UDB07_F1 EQU 0x40006557 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_F1 +CYDEV_UWRK_UWRK8_B1_UDB08_F1 EQU 0x40006558 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_F1 +CYDEV_UWRK_UWRK8_B1_UDB09_F1 EQU 0x40006559 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_F1 +CYDEV_UWRK_UWRK8_B1_UDB10_F1 EQU 0x4000655a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_F1 +CYDEV_UWRK_UWRK8_B1_UDB11_F1 EQU 0x4000655b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_ST +CYDEV_UWRK_UWRK8_B1_UDB04_ST EQU 0x40006564 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_ST +CYDEV_UWRK_UWRK8_B1_UDB05_ST EQU 0x40006565 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_ST +CYDEV_UWRK_UWRK8_B1_UDB06_ST EQU 0x40006566 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_ST +CYDEV_UWRK_UWRK8_B1_UDB07_ST EQU 0x40006567 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_ST +CYDEV_UWRK_UWRK8_B1_UDB08_ST EQU 0x40006568 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_ST +CYDEV_UWRK_UWRK8_B1_UDB09_ST EQU 0x40006569 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_ST +CYDEV_UWRK_UWRK8_B1_UDB10_ST EQU 0x4000656a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_ST +CYDEV_UWRK_UWRK8_B1_UDB11_ST EQU 0x4000656b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_CTL +CYDEV_UWRK_UWRK8_B1_UDB04_CTL EQU 0x40006574 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_CTL +CYDEV_UWRK_UWRK8_B1_UDB05_CTL EQU 0x40006575 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_CTL +CYDEV_UWRK_UWRK8_B1_UDB06_CTL EQU 0x40006576 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_CTL +CYDEV_UWRK_UWRK8_B1_UDB07_CTL EQU 0x40006577 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_CTL +CYDEV_UWRK_UWRK8_B1_UDB08_CTL EQU 0x40006578 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_CTL +CYDEV_UWRK_UWRK8_B1_UDB09_CTL EQU 0x40006579 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_CTL +CYDEV_UWRK_UWRK8_B1_UDB10_CTL EQU 0x4000657a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_CTL +CYDEV_UWRK_UWRK8_B1_UDB11_CTL EQU 0x4000657b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_MSK +CYDEV_UWRK_UWRK8_B1_UDB04_MSK EQU 0x40006584 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_MSK +CYDEV_UWRK_UWRK8_B1_UDB05_MSK EQU 0x40006585 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_MSK +CYDEV_UWRK_UWRK8_B1_UDB06_MSK EQU 0x40006586 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_MSK +CYDEV_UWRK_UWRK8_B1_UDB07_MSK EQU 0x40006587 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_MSK +CYDEV_UWRK_UWRK8_B1_UDB08_MSK EQU 0x40006588 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_MSK +CYDEV_UWRK_UWRK8_B1_UDB09_MSK EQU 0x40006589 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_MSK +CYDEV_UWRK_UWRK8_B1_UDB10_MSK EQU 0x4000658a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_MSK +CYDEV_UWRK_UWRK8_B1_UDB11_MSK EQU 0x4000658b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_ACTL +CYDEV_UWRK_UWRK8_B1_UDB04_ACTL EQU 0x40006594 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_ACTL +CYDEV_UWRK_UWRK8_B1_UDB05_ACTL EQU 0x40006595 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_ACTL +CYDEV_UWRK_UWRK8_B1_UDB06_ACTL EQU 0x40006596 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_ACTL +CYDEV_UWRK_UWRK8_B1_UDB07_ACTL EQU 0x40006597 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_ACTL +CYDEV_UWRK_UWRK8_B1_UDB08_ACTL EQU 0x40006598 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_ACTL +CYDEV_UWRK_UWRK8_B1_UDB09_ACTL EQU 0x40006599 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_ACTL +CYDEV_UWRK_UWRK8_B1_UDB10_ACTL EQU 0x4000659a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_ACTL +CYDEV_UWRK_UWRK8_B1_UDB11_ACTL EQU 0x4000659b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_MC +CYDEV_UWRK_UWRK8_B1_UDB04_MC EQU 0x400065a4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_MC +CYDEV_UWRK_UWRK8_B1_UDB05_MC EQU 0x400065a5 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_MC +CYDEV_UWRK_UWRK8_B1_UDB06_MC EQU 0x400065a6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_MC +CYDEV_UWRK_UWRK8_B1_UDB07_MC EQU 0x400065a7 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_MC +CYDEV_UWRK_UWRK8_B1_UDB08_MC EQU 0x400065a8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_MC +CYDEV_UWRK_UWRK8_B1_UDB09_MC EQU 0x400065a9 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_MC +CYDEV_UWRK_UWRK8_B1_UDB10_MC EQU 0x400065aa + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_MC +CYDEV_UWRK_UWRK8_B1_UDB11_MC EQU 0x400065ab + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_BASE +CYDEV_UWRK_UWRK16_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_SIZE +CYDEV_UWRK_UWRK16_SIZE EQU 0x00000760 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_BASE +CYDEV_UWRK_UWRK16_CAT_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_SIZE +CYDEV_UWRK_UWRK16_CAT_SIZE EQU 0x00000760 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_BASE +CYDEV_UWRK_UWRK16_CAT_B0_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_SIZE +CYDEV_UWRK_UWRK16_CAT_B0_SIZE EQU 0x00000160 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1 EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1 EQU 0x40006802 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1 EQU 0x40006804 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1 EQU 0x40006806 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1 EQU 0x40006808 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1 EQU 0x4000680a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1 EQU 0x4000680c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1 EQU 0x4000680e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1 EQU 0x40006810 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1 EQU 0x40006812 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1 EQU 0x40006814 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1 EQU 0x40006816 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1 EQU 0x40006818 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1 EQU 0x4000681a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1 EQU 0x4000681c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1 EQU 0x4000681e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1 EQU 0x40006840 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1 EQU 0x40006842 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1 EQU 0x40006844 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1 EQU 0x40006846 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1 EQU 0x40006848 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1 EQU 0x4000684a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1 EQU 0x4000684c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1 EQU 0x4000684e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1 EQU 0x40006850 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1 EQU 0x40006852 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1 EQU 0x40006854 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1 EQU 0x40006856 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1 EQU 0x40006858 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1 EQU 0x4000685a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1 EQU 0x4000685c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1 EQU 0x4000685e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1 EQU 0x40006880 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1 EQU 0x40006882 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1 EQU 0x40006884 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1 EQU 0x40006886 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1 EQU 0x40006888 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1 EQU 0x4000688a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1 EQU 0x4000688c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1 EQU 0x4000688e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1 EQU 0x40006890 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1 EQU 0x40006892 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1 EQU 0x40006894 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1 EQU 0x40006896 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1 EQU 0x40006898 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1 EQU 0x4000689a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1 EQU 0x4000689c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1 EQU 0x4000689e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL EQU 0x400068c0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL EQU 0x400068c2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL EQU 0x400068c4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL EQU 0x400068c6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL EQU 0x400068c8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL EQU 0x400068ca + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL EQU 0x400068cc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL EQU 0x400068ce + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL EQU 0x400068d0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL EQU 0x400068d2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL EQU 0x400068d4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL EQU 0x400068d6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL EQU 0x400068d8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL EQU 0x400068da + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL EQU 0x400068dc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL EQU 0x400068de + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL EQU 0x40006900 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL EQU 0x40006902 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL EQU 0x40006904 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL EQU 0x40006906 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL EQU 0x40006908 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL EQU 0x4000690a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL EQU 0x4000690c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL EQU 0x4000690e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL EQU 0x40006910 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL EQU 0x40006912 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL EQU 0x40006914 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL EQU 0x40006916 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL EQU 0x40006918 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL EQU 0x4000691a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL EQU 0x4000691c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL EQU 0x4000691e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00 EQU 0x40006940 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00 EQU 0x40006942 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00 EQU 0x40006944 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00 EQU 0x40006946 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00 EQU 0x40006948 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00 EQU 0x4000694a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00 EQU 0x4000694c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00 EQU 0x4000694e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00 EQU 0x40006950 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00 EQU 0x40006952 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00 EQU 0x40006954 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00 EQU 0x40006956 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00 EQU 0x40006958 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00 EQU 0x4000695a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00 EQU 0x4000695c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00 EQU 0x4000695e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_BASE +CYDEV_UWRK_UWRK16_CAT_B1_BASE EQU 0x40006a00 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_SIZE +CYDEV_UWRK_UWRK16_CAT_B1_SIZE EQU 0x00000160 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1 EQU 0x40006a08 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1 EQU 0x40006a0a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1 EQU 0x40006a0c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1 EQU 0x40006a0e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1 EQU 0x40006a10 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1 EQU 0x40006a12 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1 EQU 0x40006a14 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1 EQU 0x40006a16 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1 EQU 0x40006a48 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1 EQU 0x40006a4a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1 EQU 0x40006a4c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1 EQU 0x40006a4e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1 EQU 0x40006a50 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1 EQU 0x40006a52 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1 EQU 0x40006a54 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1 EQU 0x40006a56 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1 EQU 0x40006a88 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1 EQU 0x40006a8a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1 EQU 0x40006a8c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1 EQU 0x40006a8e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1 EQU 0x40006a90 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1 EQU 0x40006a92 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1 EQU 0x40006a94 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1 EQU 0x40006a96 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL EQU 0x40006ac8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL EQU 0x40006aca + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL EQU 0x40006acc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL EQU 0x40006ace + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL EQU 0x40006ad0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL EQU 0x40006ad2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL EQU 0x40006ad4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL EQU 0x40006ad6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL EQU 0x40006b08 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL EQU 0x40006b0a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL EQU 0x40006b0c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL EQU 0x40006b0e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL EQU 0x40006b10 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL EQU 0x40006b12 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL EQU 0x40006b14 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL EQU 0x40006b16 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00 EQU 0x40006b48 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00 EQU 0x40006b4a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00 EQU 0x40006b4c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00 EQU 0x40006b4e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00 EQU 0x40006b50 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00 EQU 0x40006b52 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00 EQU 0x40006b54 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00 EQU 0x40006b56 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_BASE +CYDEV_UWRK_UWRK16_DEF_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_SIZE +CYDEV_UWRK_UWRK16_DEF_SIZE EQU 0x0000075e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_BASE +CYDEV_UWRK_UWRK16_DEF_B0_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_SIZE +CYDEV_UWRK_UWRK16_DEF_B0_SIZE EQU 0x0000015e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0 EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0 EQU 0x40006802 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0 EQU 0x40006804 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0 EQU 0x40006806 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0 EQU 0x40006808 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0 EQU 0x4000680a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0 EQU 0x4000680c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0 EQU 0x4000680e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0 EQU 0x40006810 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0 EQU 0x40006812 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0 EQU 0x40006814 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0 EQU 0x40006816 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0 EQU 0x40006818 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0 EQU 0x4000681a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0 EQU 0x4000681c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1 EQU 0x40006820 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1 EQU 0x40006822 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1 EQU 0x40006824 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1 EQU 0x40006826 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1 EQU 0x40006828 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1 EQU 0x4000682a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1 EQU 0x4000682c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1 EQU 0x4000682e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1 EQU 0x40006830 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1 EQU 0x40006832 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1 EQU 0x40006834 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1 EQU 0x40006836 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1 EQU 0x40006838 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1 EQU 0x4000683a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1 EQU 0x4000683c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0 EQU 0x40006840 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0 EQU 0x40006842 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0 EQU 0x40006844 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0 EQU 0x40006846 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0 EQU 0x40006848 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0 EQU 0x4000684a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0 EQU 0x4000684c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0 EQU 0x4000684e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0 EQU 0x40006850 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0 EQU 0x40006852 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0 EQU 0x40006854 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0 EQU 0x40006856 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0 EQU 0x40006858 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0 EQU 0x4000685a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0 EQU 0x4000685c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1 EQU 0x40006860 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1 EQU 0x40006862 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1 EQU 0x40006864 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1 EQU 0x40006866 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1 EQU 0x40006868 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1 EQU 0x4000686a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1 EQU 0x4000686c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1 EQU 0x4000686e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1 EQU 0x40006870 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1 EQU 0x40006872 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1 EQU 0x40006874 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1 EQU 0x40006876 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1 EQU 0x40006878 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1 EQU 0x4000687a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1 EQU 0x4000687c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0 EQU 0x40006880 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0 EQU 0x40006882 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0 EQU 0x40006884 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0 EQU 0x40006886 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0 EQU 0x40006888 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0 EQU 0x4000688a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0 EQU 0x4000688c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0 EQU 0x4000688e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0 EQU 0x40006890 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0 EQU 0x40006892 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0 EQU 0x40006894 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0 EQU 0x40006896 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0 EQU 0x40006898 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0 EQU 0x4000689a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0 EQU 0x4000689c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1 EQU 0x400068a0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1 EQU 0x400068a2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1 EQU 0x400068a4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1 EQU 0x400068a6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1 EQU 0x400068a8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1 EQU 0x400068aa + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1 EQU 0x400068ac + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1 EQU 0x400068ae + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1 EQU 0x400068b0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1 EQU 0x400068b2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1 EQU 0x400068b4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1 EQU 0x400068b6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1 EQU 0x400068b8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1 EQU 0x400068ba + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1 EQU 0x400068bc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST EQU 0x400068c0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST EQU 0x400068c2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST EQU 0x400068c4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST EQU 0x400068c6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST EQU 0x400068c8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST EQU 0x400068ca + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST EQU 0x400068cc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST EQU 0x400068ce + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST EQU 0x400068d0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST EQU 0x400068d2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST EQU 0x400068d4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST EQU 0x400068d6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST EQU 0x400068d8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST EQU 0x400068da + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST EQU 0x400068dc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL EQU 0x400068e0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL EQU 0x400068e2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL EQU 0x400068e4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL EQU 0x400068e6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL EQU 0x400068e8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL EQU 0x400068ea + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL EQU 0x400068ec + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL EQU 0x400068ee + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL EQU 0x400068f0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL EQU 0x400068f2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL EQU 0x400068f4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL EQU 0x400068f6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL EQU 0x400068f8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL EQU 0x400068fa + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL EQU 0x400068fc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK EQU 0x40006900 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK EQU 0x40006902 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK EQU 0x40006904 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK EQU 0x40006906 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK EQU 0x40006908 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK EQU 0x4000690a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK EQU 0x4000690c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK EQU 0x4000690e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK EQU 0x40006910 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK EQU 0x40006912 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK EQU 0x40006914 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK EQU 0x40006916 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK EQU 0x40006918 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK EQU 0x4000691a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK EQU 0x4000691c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL EQU 0x40006920 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL EQU 0x40006922 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL EQU 0x40006924 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL EQU 0x40006926 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL EQU 0x40006928 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL EQU 0x4000692a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL EQU 0x4000692c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL EQU 0x4000692e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL EQU 0x40006930 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL EQU 0x40006932 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL EQU 0x40006934 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL EQU 0x40006936 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL EQU 0x40006938 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL EQU 0x4000693a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL EQU 0x4000693c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC EQU 0x40006940 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC EQU 0x40006942 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC EQU 0x40006944 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC EQU 0x40006946 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC EQU 0x40006948 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC EQU 0x4000694a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC EQU 0x4000694c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC EQU 0x4000694e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC EQU 0x40006950 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC EQU 0x40006952 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC EQU 0x40006954 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC EQU 0x40006956 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC EQU 0x40006958 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC EQU 0x4000695a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC EQU 0x4000695c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_BASE +CYDEV_UWRK_UWRK16_DEF_B1_BASE EQU 0x40006a00 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_SIZE +CYDEV_UWRK_UWRK16_DEF_B1_SIZE EQU 0x0000015e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0 EQU 0x40006a08 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0 EQU 0x40006a0a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0 EQU 0x40006a0c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0 EQU 0x40006a0e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0 EQU 0x40006a10 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0 EQU 0x40006a12 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0 EQU 0x40006a14 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0 EQU 0x40006a16 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1 EQU 0x40006a28 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1 EQU 0x40006a2a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1 EQU 0x40006a2c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1 EQU 0x40006a2e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1 EQU 0x40006a30 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1 EQU 0x40006a32 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1 EQU 0x40006a34 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1 EQU 0x40006a36 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0 EQU 0x40006a48 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0 EQU 0x40006a4a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0 EQU 0x40006a4c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0 EQU 0x40006a4e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0 EQU 0x40006a50 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0 EQU 0x40006a52 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0 EQU 0x40006a54 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0 EQU 0x40006a56 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1 EQU 0x40006a68 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1 EQU 0x40006a6a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1 EQU 0x40006a6c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1 EQU 0x40006a6e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1 EQU 0x40006a70 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1 EQU 0x40006a72 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1 EQU 0x40006a74 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1 EQU 0x40006a76 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0 EQU 0x40006a88 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0 EQU 0x40006a8a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0 EQU 0x40006a8c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0 EQU 0x40006a8e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0 EQU 0x40006a90 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0 EQU 0x40006a92 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0 EQU 0x40006a94 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0 EQU 0x40006a96 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1 EQU 0x40006aa8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1 EQU 0x40006aaa + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1 EQU 0x40006aac + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1 EQU 0x40006aae + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1 EQU 0x40006ab0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1 EQU 0x40006ab2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1 EQU 0x40006ab4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1 EQU 0x40006ab6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST EQU 0x40006ac8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST EQU 0x40006aca + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST EQU 0x40006acc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST EQU 0x40006ace + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST EQU 0x40006ad0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST EQU 0x40006ad2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST EQU 0x40006ad4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST EQU 0x40006ad6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL EQU 0x40006ae8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL EQU 0x40006aea + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL EQU 0x40006aec + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL EQU 0x40006aee + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL EQU 0x40006af0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL EQU 0x40006af2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL EQU 0x40006af4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL EQU 0x40006af6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK EQU 0x40006b08 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK EQU 0x40006b0a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK EQU 0x40006b0c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK EQU 0x40006b0e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK EQU 0x40006b10 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK EQU 0x40006b12 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK EQU 0x40006b14 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK EQU 0x40006b16 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL EQU 0x40006b28 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL EQU 0x40006b2a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL EQU 0x40006b2c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL EQU 0x40006b2e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL EQU 0x40006b30 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL EQU 0x40006b32 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL EQU 0x40006b34 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL EQU 0x40006b36 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC EQU 0x40006b48 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC EQU 0x40006b4a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC EQU 0x40006b4c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC EQU 0x40006b4e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC EQU 0x40006b50 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC EQU 0x40006b52 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC EQU 0x40006b54 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC EQU 0x40006b56 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_BASE +CYDEV_PHUB_BASE EQU 0x40007000 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_SIZE +CYDEV_PHUB_SIZE EQU 0x00000c00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFG +CYDEV_PHUB_CFG EQU 0x40007000 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_ERR +CYDEV_PHUB_ERR EQU 0x40007004 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_ERR_ADR +CYDEV_PHUB_ERR_ADR EQU 0x40007008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_BASE +CYDEV_PHUB_CH0_BASE EQU 0x40007010 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_SIZE +CYDEV_PHUB_CH0_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_BASIC_CFG +CYDEV_PHUB_CH0_BASIC_CFG EQU 0x40007010 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_ACTION +CYDEV_PHUB_CH0_ACTION EQU 0x40007014 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_BASIC_STATUS +CYDEV_PHUB_CH0_BASIC_STATUS EQU 0x40007018 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_BASE +CYDEV_PHUB_CH1_BASE EQU 0x40007020 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_SIZE +CYDEV_PHUB_CH1_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_BASIC_CFG +CYDEV_PHUB_CH1_BASIC_CFG EQU 0x40007020 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_ACTION +CYDEV_PHUB_CH1_ACTION EQU 0x40007024 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_BASIC_STATUS +CYDEV_PHUB_CH1_BASIC_STATUS EQU 0x40007028 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_BASE +CYDEV_PHUB_CH2_BASE EQU 0x40007030 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_SIZE +CYDEV_PHUB_CH2_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_BASIC_CFG +CYDEV_PHUB_CH2_BASIC_CFG EQU 0x40007030 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_ACTION +CYDEV_PHUB_CH2_ACTION EQU 0x40007034 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_BASIC_STATUS +CYDEV_PHUB_CH2_BASIC_STATUS EQU 0x40007038 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_BASE +CYDEV_PHUB_CH3_BASE EQU 0x40007040 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_SIZE +CYDEV_PHUB_CH3_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_BASIC_CFG +CYDEV_PHUB_CH3_BASIC_CFG EQU 0x40007040 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_ACTION +CYDEV_PHUB_CH3_ACTION EQU 0x40007044 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_BASIC_STATUS +CYDEV_PHUB_CH3_BASIC_STATUS EQU 0x40007048 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_BASE +CYDEV_PHUB_CH4_BASE EQU 0x40007050 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_SIZE +CYDEV_PHUB_CH4_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_BASIC_CFG +CYDEV_PHUB_CH4_BASIC_CFG EQU 0x40007050 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_ACTION +CYDEV_PHUB_CH4_ACTION EQU 0x40007054 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_BASIC_STATUS +CYDEV_PHUB_CH4_BASIC_STATUS EQU 0x40007058 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_BASE +CYDEV_PHUB_CH5_BASE EQU 0x40007060 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_SIZE +CYDEV_PHUB_CH5_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_BASIC_CFG +CYDEV_PHUB_CH5_BASIC_CFG EQU 0x40007060 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_ACTION +CYDEV_PHUB_CH5_ACTION EQU 0x40007064 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_BASIC_STATUS +CYDEV_PHUB_CH5_BASIC_STATUS EQU 0x40007068 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_BASE +CYDEV_PHUB_CH6_BASE EQU 0x40007070 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_SIZE +CYDEV_PHUB_CH6_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_BASIC_CFG +CYDEV_PHUB_CH6_BASIC_CFG EQU 0x40007070 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_ACTION +CYDEV_PHUB_CH6_ACTION EQU 0x40007074 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_BASIC_STATUS +CYDEV_PHUB_CH6_BASIC_STATUS EQU 0x40007078 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_BASE +CYDEV_PHUB_CH7_BASE EQU 0x40007080 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_SIZE +CYDEV_PHUB_CH7_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_BASIC_CFG +CYDEV_PHUB_CH7_BASIC_CFG EQU 0x40007080 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_ACTION +CYDEV_PHUB_CH7_ACTION EQU 0x40007084 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_BASIC_STATUS +CYDEV_PHUB_CH7_BASIC_STATUS EQU 0x40007088 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_BASE +CYDEV_PHUB_CH8_BASE EQU 0x40007090 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_SIZE +CYDEV_PHUB_CH8_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_BASIC_CFG +CYDEV_PHUB_CH8_BASIC_CFG EQU 0x40007090 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_ACTION +CYDEV_PHUB_CH8_ACTION EQU 0x40007094 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_BASIC_STATUS +CYDEV_PHUB_CH8_BASIC_STATUS EQU 0x40007098 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_BASE +CYDEV_PHUB_CH9_BASE EQU 0x400070a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_SIZE +CYDEV_PHUB_CH9_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_BASIC_CFG +CYDEV_PHUB_CH9_BASIC_CFG EQU 0x400070a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_ACTION +CYDEV_PHUB_CH9_ACTION EQU 0x400070a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_BASIC_STATUS +CYDEV_PHUB_CH9_BASIC_STATUS EQU 0x400070a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_BASE +CYDEV_PHUB_CH10_BASE EQU 0x400070b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_SIZE +CYDEV_PHUB_CH10_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_BASIC_CFG +CYDEV_PHUB_CH10_BASIC_CFG EQU 0x400070b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_ACTION +CYDEV_PHUB_CH10_ACTION EQU 0x400070b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_BASIC_STATUS +CYDEV_PHUB_CH10_BASIC_STATUS EQU 0x400070b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_BASE +CYDEV_PHUB_CH11_BASE EQU 0x400070c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_SIZE +CYDEV_PHUB_CH11_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_BASIC_CFG +CYDEV_PHUB_CH11_BASIC_CFG EQU 0x400070c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_ACTION +CYDEV_PHUB_CH11_ACTION EQU 0x400070c4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_BASIC_STATUS +CYDEV_PHUB_CH11_BASIC_STATUS EQU 0x400070c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_BASE +CYDEV_PHUB_CH12_BASE EQU 0x400070d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_SIZE +CYDEV_PHUB_CH12_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_BASIC_CFG +CYDEV_PHUB_CH12_BASIC_CFG EQU 0x400070d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_ACTION +CYDEV_PHUB_CH12_ACTION EQU 0x400070d4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_BASIC_STATUS +CYDEV_PHUB_CH12_BASIC_STATUS EQU 0x400070d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_BASE +CYDEV_PHUB_CH13_BASE EQU 0x400070e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_SIZE +CYDEV_PHUB_CH13_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_BASIC_CFG +CYDEV_PHUB_CH13_BASIC_CFG EQU 0x400070e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_ACTION +CYDEV_PHUB_CH13_ACTION EQU 0x400070e4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_BASIC_STATUS +CYDEV_PHUB_CH13_BASIC_STATUS EQU 0x400070e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_BASE +CYDEV_PHUB_CH14_BASE EQU 0x400070f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_SIZE +CYDEV_PHUB_CH14_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_BASIC_CFG +CYDEV_PHUB_CH14_BASIC_CFG EQU 0x400070f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_ACTION +CYDEV_PHUB_CH14_ACTION EQU 0x400070f4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_BASIC_STATUS +CYDEV_PHUB_CH14_BASIC_STATUS EQU 0x400070f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_BASE +CYDEV_PHUB_CH15_BASE EQU 0x40007100 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_SIZE +CYDEV_PHUB_CH15_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_BASIC_CFG +CYDEV_PHUB_CH15_BASIC_CFG EQU 0x40007100 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_ACTION +CYDEV_PHUB_CH15_ACTION EQU 0x40007104 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_BASIC_STATUS +CYDEV_PHUB_CH15_BASIC_STATUS EQU 0x40007108 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_BASE +CYDEV_PHUB_CH16_BASE EQU 0x40007110 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_SIZE +CYDEV_PHUB_CH16_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_BASIC_CFG +CYDEV_PHUB_CH16_BASIC_CFG EQU 0x40007110 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_ACTION +CYDEV_PHUB_CH16_ACTION EQU 0x40007114 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_BASIC_STATUS +CYDEV_PHUB_CH16_BASIC_STATUS EQU 0x40007118 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_BASE +CYDEV_PHUB_CH17_BASE EQU 0x40007120 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_SIZE +CYDEV_PHUB_CH17_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_BASIC_CFG +CYDEV_PHUB_CH17_BASIC_CFG EQU 0x40007120 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_ACTION +CYDEV_PHUB_CH17_ACTION EQU 0x40007124 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_BASIC_STATUS +CYDEV_PHUB_CH17_BASIC_STATUS EQU 0x40007128 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_BASE +CYDEV_PHUB_CH18_BASE EQU 0x40007130 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_SIZE +CYDEV_PHUB_CH18_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_BASIC_CFG +CYDEV_PHUB_CH18_BASIC_CFG EQU 0x40007130 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_ACTION +CYDEV_PHUB_CH18_ACTION EQU 0x40007134 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_BASIC_STATUS +CYDEV_PHUB_CH18_BASIC_STATUS EQU 0x40007138 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_BASE +CYDEV_PHUB_CH19_BASE EQU 0x40007140 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_SIZE +CYDEV_PHUB_CH19_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_BASIC_CFG +CYDEV_PHUB_CH19_BASIC_CFG EQU 0x40007140 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_ACTION +CYDEV_PHUB_CH19_ACTION EQU 0x40007144 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_BASIC_STATUS +CYDEV_PHUB_CH19_BASIC_STATUS EQU 0x40007148 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_BASE +CYDEV_PHUB_CH20_BASE EQU 0x40007150 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_SIZE +CYDEV_PHUB_CH20_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_BASIC_CFG +CYDEV_PHUB_CH20_BASIC_CFG EQU 0x40007150 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_ACTION +CYDEV_PHUB_CH20_ACTION EQU 0x40007154 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_BASIC_STATUS +CYDEV_PHUB_CH20_BASIC_STATUS EQU 0x40007158 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_BASE +CYDEV_PHUB_CH21_BASE EQU 0x40007160 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_SIZE +CYDEV_PHUB_CH21_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_BASIC_CFG +CYDEV_PHUB_CH21_BASIC_CFG EQU 0x40007160 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_ACTION +CYDEV_PHUB_CH21_ACTION EQU 0x40007164 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_BASIC_STATUS +CYDEV_PHUB_CH21_BASIC_STATUS EQU 0x40007168 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_BASE +CYDEV_PHUB_CH22_BASE EQU 0x40007170 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_SIZE +CYDEV_PHUB_CH22_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_BASIC_CFG +CYDEV_PHUB_CH22_BASIC_CFG EQU 0x40007170 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_ACTION +CYDEV_PHUB_CH22_ACTION EQU 0x40007174 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_BASIC_STATUS +CYDEV_PHUB_CH22_BASIC_STATUS EQU 0x40007178 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_BASE +CYDEV_PHUB_CH23_BASE EQU 0x40007180 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_SIZE +CYDEV_PHUB_CH23_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_BASIC_CFG +CYDEV_PHUB_CH23_BASIC_CFG EQU 0x40007180 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_ACTION +CYDEV_PHUB_CH23_ACTION EQU 0x40007184 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_BASIC_STATUS +CYDEV_PHUB_CH23_BASIC_STATUS EQU 0x40007188 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_BASE +CYDEV_PHUB_CFGMEM0_BASE EQU 0x40007600 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_SIZE +CYDEV_PHUB_CFGMEM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_CFG0 +CYDEV_PHUB_CFGMEM0_CFG0 EQU 0x40007600 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_CFG1 +CYDEV_PHUB_CFGMEM0_CFG1 EQU 0x40007604 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_BASE +CYDEV_PHUB_CFGMEM1_BASE EQU 0x40007608 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_SIZE +CYDEV_PHUB_CFGMEM1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_CFG0 +CYDEV_PHUB_CFGMEM1_CFG0 EQU 0x40007608 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_CFG1 +CYDEV_PHUB_CFGMEM1_CFG1 EQU 0x4000760c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_BASE +CYDEV_PHUB_CFGMEM2_BASE EQU 0x40007610 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_SIZE +CYDEV_PHUB_CFGMEM2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_CFG0 +CYDEV_PHUB_CFGMEM2_CFG0 EQU 0x40007610 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_CFG1 +CYDEV_PHUB_CFGMEM2_CFG1 EQU 0x40007614 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_BASE +CYDEV_PHUB_CFGMEM3_BASE EQU 0x40007618 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_SIZE +CYDEV_PHUB_CFGMEM3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_CFG0 +CYDEV_PHUB_CFGMEM3_CFG0 EQU 0x40007618 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_CFG1 +CYDEV_PHUB_CFGMEM3_CFG1 EQU 0x4000761c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_BASE +CYDEV_PHUB_CFGMEM4_BASE EQU 0x40007620 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_SIZE +CYDEV_PHUB_CFGMEM4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_CFG0 +CYDEV_PHUB_CFGMEM4_CFG0 EQU 0x40007620 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_CFG1 +CYDEV_PHUB_CFGMEM4_CFG1 EQU 0x40007624 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_BASE +CYDEV_PHUB_CFGMEM5_BASE EQU 0x40007628 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_SIZE +CYDEV_PHUB_CFGMEM5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_CFG0 +CYDEV_PHUB_CFGMEM5_CFG0 EQU 0x40007628 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_CFG1 +CYDEV_PHUB_CFGMEM5_CFG1 EQU 0x4000762c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_BASE +CYDEV_PHUB_CFGMEM6_BASE EQU 0x40007630 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_SIZE +CYDEV_PHUB_CFGMEM6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_CFG0 +CYDEV_PHUB_CFGMEM6_CFG0 EQU 0x40007630 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_CFG1 +CYDEV_PHUB_CFGMEM6_CFG1 EQU 0x40007634 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_BASE +CYDEV_PHUB_CFGMEM7_BASE EQU 0x40007638 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_SIZE +CYDEV_PHUB_CFGMEM7_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_CFG0 +CYDEV_PHUB_CFGMEM7_CFG0 EQU 0x40007638 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_CFG1 +CYDEV_PHUB_CFGMEM7_CFG1 EQU 0x4000763c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_BASE +CYDEV_PHUB_CFGMEM8_BASE EQU 0x40007640 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_SIZE +CYDEV_PHUB_CFGMEM8_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_CFG0 +CYDEV_PHUB_CFGMEM8_CFG0 EQU 0x40007640 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_CFG1 +CYDEV_PHUB_CFGMEM8_CFG1 EQU 0x40007644 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_BASE +CYDEV_PHUB_CFGMEM9_BASE EQU 0x40007648 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_SIZE +CYDEV_PHUB_CFGMEM9_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_CFG0 +CYDEV_PHUB_CFGMEM9_CFG0 EQU 0x40007648 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_CFG1 +CYDEV_PHUB_CFGMEM9_CFG1 EQU 0x4000764c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_BASE +CYDEV_PHUB_CFGMEM10_BASE EQU 0x40007650 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_SIZE +CYDEV_PHUB_CFGMEM10_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_CFG0 +CYDEV_PHUB_CFGMEM10_CFG0 EQU 0x40007650 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_CFG1 +CYDEV_PHUB_CFGMEM10_CFG1 EQU 0x40007654 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_BASE +CYDEV_PHUB_CFGMEM11_BASE EQU 0x40007658 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_SIZE +CYDEV_PHUB_CFGMEM11_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_CFG0 +CYDEV_PHUB_CFGMEM11_CFG0 EQU 0x40007658 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_CFG1 +CYDEV_PHUB_CFGMEM11_CFG1 EQU 0x4000765c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_BASE +CYDEV_PHUB_CFGMEM12_BASE EQU 0x40007660 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_SIZE +CYDEV_PHUB_CFGMEM12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_CFG0 +CYDEV_PHUB_CFGMEM12_CFG0 EQU 0x40007660 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_CFG1 +CYDEV_PHUB_CFGMEM12_CFG1 EQU 0x40007664 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_BASE +CYDEV_PHUB_CFGMEM13_BASE EQU 0x40007668 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_SIZE +CYDEV_PHUB_CFGMEM13_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_CFG0 +CYDEV_PHUB_CFGMEM13_CFG0 EQU 0x40007668 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_CFG1 +CYDEV_PHUB_CFGMEM13_CFG1 EQU 0x4000766c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_BASE +CYDEV_PHUB_CFGMEM14_BASE EQU 0x40007670 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_SIZE +CYDEV_PHUB_CFGMEM14_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_CFG0 +CYDEV_PHUB_CFGMEM14_CFG0 EQU 0x40007670 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_CFG1 +CYDEV_PHUB_CFGMEM14_CFG1 EQU 0x40007674 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_BASE +CYDEV_PHUB_CFGMEM15_BASE EQU 0x40007678 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_SIZE +CYDEV_PHUB_CFGMEM15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_CFG0 +CYDEV_PHUB_CFGMEM15_CFG0 EQU 0x40007678 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_CFG1 +CYDEV_PHUB_CFGMEM15_CFG1 EQU 0x4000767c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_BASE +CYDEV_PHUB_CFGMEM16_BASE EQU 0x40007680 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_SIZE +CYDEV_PHUB_CFGMEM16_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_CFG0 +CYDEV_PHUB_CFGMEM16_CFG0 EQU 0x40007680 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_CFG1 +CYDEV_PHUB_CFGMEM16_CFG1 EQU 0x40007684 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_BASE +CYDEV_PHUB_CFGMEM17_BASE EQU 0x40007688 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_SIZE +CYDEV_PHUB_CFGMEM17_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_CFG0 +CYDEV_PHUB_CFGMEM17_CFG0 EQU 0x40007688 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_CFG1 +CYDEV_PHUB_CFGMEM17_CFG1 EQU 0x4000768c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_BASE +CYDEV_PHUB_CFGMEM18_BASE EQU 0x40007690 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_SIZE +CYDEV_PHUB_CFGMEM18_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_CFG0 +CYDEV_PHUB_CFGMEM18_CFG0 EQU 0x40007690 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_CFG1 +CYDEV_PHUB_CFGMEM18_CFG1 EQU 0x40007694 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_BASE +CYDEV_PHUB_CFGMEM19_BASE EQU 0x40007698 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_SIZE +CYDEV_PHUB_CFGMEM19_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_CFG0 +CYDEV_PHUB_CFGMEM19_CFG0 EQU 0x40007698 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_CFG1 +CYDEV_PHUB_CFGMEM19_CFG1 EQU 0x4000769c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_BASE +CYDEV_PHUB_CFGMEM20_BASE EQU 0x400076a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_SIZE +CYDEV_PHUB_CFGMEM20_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_CFG0 +CYDEV_PHUB_CFGMEM20_CFG0 EQU 0x400076a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_CFG1 +CYDEV_PHUB_CFGMEM20_CFG1 EQU 0x400076a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_BASE +CYDEV_PHUB_CFGMEM21_BASE EQU 0x400076a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_SIZE +CYDEV_PHUB_CFGMEM21_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_CFG0 +CYDEV_PHUB_CFGMEM21_CFG0 EQU 0x400076a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_CFG1 +CYDEV_PHUB_CFGMEM21_CFG1 EQU 0x400076ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_BASE +CYDEV_PHUB_CFGMEM22_BASE EQU 0x400076b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_SIZE +CYDEV_PHUB_CFGMEM22_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_CFG0 +CYDEV_PHUB_CFGMEM22_CFG0 EQU 0x400076b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_CFG1 +CYDEV_PHUB_CFGMEM22_CFG1 EQU 0x400076b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_BASE +CYDEV_PHUB_CFGMEM23_BASE EQU 0x400076b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_SIZE +CYDEV_PHUB_CFGMEM23_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_CFG0 +CYDEV_PHUB_CFGMEM23_CFG0 EQU 0x400076b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_CFG1 +CYDEV_PHUB_CFGMEM23_CFG1 EQU 0x400076bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_BASE +CYDEV_PHUB_TDMEM0_BASE EQU 0x40007800 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_SIZE +CYDEV_PHUB_TDMEM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_ORIG_TD0 +CYDEV_PHUB_TDMEM0_ORIG_TD0 EQU 0x40007800 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_ORIG_TD1 +CYDEV_PHUB_TDMEM0_ORIG_TD1 EQU 0x40007804 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_BASE +CYDEV_PHUB_TDMEM1_BASE EQU 0x40007808 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_SIZE +CYDEV_PHUB_TDMEM1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_ORIG_TD0 +CYDEV_PHUB_TDMEM1_ORIG_TD0 EQU 0x40007808 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_ORIG_TD1 +CYDEV_PHUB_TDMEM1_ORIG_TD1 EQU 0x4000780c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_BASE +CYDEV_PHUB_TDMEM2_BASE EQU 0x40007810 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_SIZE +CYDEV_PHUB_TDMEM2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_ORIG_TD0 +CYDEV_PHUB_TDMEM2_ORIG_TD0 EQU 0x40007810 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_ORIG_TD1 +CYDEV_PHUB_TDMEM2_ORIG_TD1 EQU 0x40007814 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_BASE +CYDEV_PHUB_TDMEM3_BASE EQU 0x40007818 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_SIZE +CYDEV_PHUB_TDMEM3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_ORIG_TD0 +CYDEV_PHUB_TDMEM3_ORIG_TD0 EQU 0x40007818 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_ORIG_TD1 +CYDEV_PHUB_TDMEM3_ORIG_TD1 EQU 0x4000781c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_BASE +CYDEV_PHUB_TDMEM4_BASE EQU 0x40007820 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_SIZE +CYDEV_PHUB_TDMEM4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_ORIG_TD0 +CYDEV_PHUB_TDMEM4_ORIG_TD0 EQU 0x40007820 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_ORIG_TD1 +CYDEV_PHUB_TDMEM4_ORIG_TD1 EQU 0x40007824 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_BASE +CYDEV_PHUB_TDMEM5_BASE EQU 0x40007828 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_SIZE +CYDEV_PHUB_TDMEM5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_ORIG_TD0 +CYDEV_PHUB_TDMEM5_ORIG_TD0 EQU 0x40007828 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_ORIG_TD1 +CYDEV_PHUB_TDMEM5_ORIG_TD1 EQU 0x4000782c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_BASE +CYDEV_PHUB_TDMEM6_BASE EQU 0x40007830 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_SIZE +CYDEV_PHUB_TDMEM6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_ORIG_TD0 +CYDEV_PHUB_TDMEM6_ORIG_TD0 EQU 0x40007830 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_ORIG_TD1 +CYDEV_PHUB_TDMEM6_ORIG_TD1 EQU 0x40007834 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_BASE +CYDEV_PHUB_TDMEM7_BASE EQU 0x40007838 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_SIZE +CYDEV_PHUB_TDMEM7_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_ORIG_TD0 +CYDEV_PHUB_TDMEM7_ORIG_TD0 EQU 0x40007838 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_ORIG_TD1 +CYDEV_PHUB_TDMEM7_ORIG_TD1 EQU 0x4000783c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_BASE +CYDEV_PHUB_TDMEM8_BASE EQU 0x40007840 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_SIZE +CYDEV_PHUB_TDMEM8_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_ORIG_TD0 +CYDEV_PHUB_TDMEM8_ORIG_TD0 EQU 0x40007840 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_ORIG_TD1 +CYDEV_PHUB_TDMEM8_ORIG_TD1 EQU 0x40007844 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_BASE +CYDEV_PHUB_TDMEM9_BASE EQU 0x40007848 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_SIZE +CYDEV_PHUB_TDMEM9_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_ORIG_TD0 +CYDEV_PHUB_TDMEM9_ORIG_TD0 EQU 0x40007848 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_ORIG_TD1 +CYDEV_PHUB_TDMEM9_ORIG_TD1 EQU 0x4000784c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_BASE +CYDEV_PHUB_TDMEM10_BASE EQU 0x40007850 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_SIZE +CYDEV_PHUB_TDMEM10_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_ORIG_TD0 +CYDEV_PHUB_TDMEM10_ORIG_TD0 EQU 0x40007850 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_ORIG_TD1 +CYDEV_PHUB_TDMEM10_ORIG_TD1 EQU 0x40007854 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_BASE +CYDEV_PHUB_TDMEM11_BASE EQU 0x40007858 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_SIZE +CYDEV_PHUB_TDMEM11_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_ORIG_TD0 +CYDEV_PHUB_TDMEM11_ORIG_TD0 EQU 0x40007858 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_ORIG_TD1 +CYDEV_PHUB_TDMEM11_ORIG_TD1 EQU 0x4000785c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_BASE +CYDEV_PHUB_TDMEM12_BASE EQU 0x40007860 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_SIZE +CYDEV_PHUB_TDMEM12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_ORIG_TD0 +CYDEV_PHUB_TDMEM12_ORIG_TD0 EQU 0x40007860 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_ORIG_TD1 +CYDEV_PHUB_TDMEM12_ORIG_TD1 EQU 0x40007864 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_BASE +CYDEV_PHUB_TDMEM13_BASE EQU 0x40007868 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_SIZE +CYDEV_PHUB_TDMEM13_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_ORIG_TD0 +CYDEV_PHUB_TDMEM13_ORIG_TD0 EQU 0x40007868 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_ORIG_TD1 +CYDEV_PHUB_TDMEM13_ORIG_TD1 EQU 0x4000786c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_BASE +CYDEV_PHUB_TDMEM14_BASE EQU 0x40007870 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_SIZE +CYDEV_PHUB_TDMEM14_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_ORIG_TD0 +CYDEV_PHUB_TDMEM14_ORIG_TD0 EQU 0x40007870 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_ORIG_TD1 +CYDEV_PHUB_TDMEM14_ORIG_TD1 EQU 0x40007874 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_BASE +CYDEV_PHUB_TDMEM15_BASE EQU 0x40007878 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_SIZE +CYDEV_PHUB_TDMEM15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_ORIG_TD0 +CYDEV_PHUB_TDMEM15_ORIG_TD0 EQU 0x40007878 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_ORIG_TD1 +CYDEV_PHUB_TDMEM15_ORIG_TD1 EQU 0x4000787c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_BASE +CYDEV_PHUB_TDMEM16_BASE EQU 0x40007880 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_SIZE +CYDEV_PHUB_TDMEM16_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_ORIG_TD0 +CYDEV_PHUB_TDMEM16_ORIG_TD0 EQU 0x40007880 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_ORIG_TD1 +CYDEV_PHUB_TDMEM16_ORIG_TD1 EQU 0x40007884 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_BASE +CYDEV_PHUB_TDMEM17_BASE EQU 0x40007888 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_SIZE +CYDEV_PHUB_TDMEM17_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_ORIG_TD0 +CYDEV_PHUB_TDMEM17_ORIG_TD0 EQU 0x40007888 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_ORIG_TD1 +CYDEV_PHUB_TDMEM17_ORIG_TD1 EQU 0x4000788c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_BASE +CYDEV_PHUB_TDMEM18_BASE EQU 0x40007890 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_SIZE +CYDEV_PHUB_TDMEM18_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_ORIG_TD0 +CYDEV_PHUB_TDMEM18_ORIG_TD0 EQU 0x40007890 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_ORIG_TD1 +CYDEV_PHUB_TDMEM18_ORIG_TD1 EQU 0x40007894 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_BASE +CYDEV_PHUB_TDMEM19_BASE EQU 0x40007898 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_SIZE +CYDEV_PHUB_TDMEM19_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_ORIG_TD0 +CYDEV_PHUB_TDMEM19_ORIG_TD0 EQU 0x40007898 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_ORIG_TD1 +CYDEV_PHUB_TDMEM19_ORIG_TD1 EQU 0x4000789c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_BASE +CYDEV_PHUB_TDMEM20_BASE EQU 0x400078a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_SIZE +CYDEV_PHUB_TDMEM20_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_ORIG_TD0 +CYDEV_PHUB_TDMEM20_ORIG_TD0 EQU 0x400078a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_ORIG_TD1 +CYDEV_PHUB_TDMEM20_ORIG_TD1 EQU 0x400078a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_BASE +CYDEV_PHUB_TDMEM21_BASE EQU 0x400078a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_SIZE +CYDEV_PHUB_TDMEM21_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_ORIG_TD0 +CYDEV_PHUB_TDMEM21_ORIG_TD0 EQU 0x400078a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_ORIG_TD1 +CYDEV_PHUB_TDMEM21_ORIG_TD1 EQU 0x400078ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_BASE +CYDEV_PHUB_TDMEM22_BASE EQU 0x400078b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_SIZE +CYDEV_PHUB_TDMEM22_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_ORIG_TD0 +CYDEV_PHUB_TDMEM22_ORIG_TD0 EQU 0x400078b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_ORIG_TD1 +CYDEV_PHUB_TDMEM22_ORIG_TD1 EQU 0x400078b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_BASE +CYDEV_PHUB_TDMEM23_BASE EQU 0x400078b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_SIZE +CYDEV_PHUB_TDMEM23_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_ORIG_TD0 +CYDEV_PHUB_TDMEM23_ORIG_TD0 EQU 0x400078b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_ORIG_TD1 +CYDEV_PHUB_TDMEM23_ORIG_TD1 EQU 0x400078bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_BASE +CYDEV_PHUB_TDMEM24_BASE EQU 0x400078c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_SIZE +CYDEV_PHUB_TDMEM24_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_ORIG_TD0 +CYDEV_PHUB_TDMEM24_ORIG_TD0 EQU 0x400078c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_ORIG_TD1 +CYDEV_PHUB_TDMEM24_ORIG_TD1 EQU 0x400078c4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_BASE +CYDEV_PHUB_TDMEM25_BASE EQU 0x400078c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_SIZE +CYDEV_PHUB_TDMEM25_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_ORIG_TD0 +CYDEV_PHUB_TDMEM25_ORIG_TD0 EQU 0x400078c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_ORIG_TD1 +CYDEV_PHUB_TDMEM25_ORIG_TD1 EQU 0x400078cc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_BASE +CYDEV_PHUB_TDMEM26_BASE EQU 0x400078d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_SIZE +CYDEV_PHUB_TDMEM26_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_ORIG_TD0 +CYDEV_PHUB_TDMEM26_ORIG_TD0 EQU 0x400078d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_ORIG_TD1 +CYDEV_PHUB_TDMEM26_ORIG_TD1 EQU 0x400078d4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_BASE +CYDEV_PHUB_TDMEM27_BASE EQU 0x400078d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_SIZE +CYDEV_PHUB_TDMEM27_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_ORIG_TD0 +CYDEV_PHUB_TDMEM27_ORIG_TD0 EQU 0x400078d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_ORIG_TD1 +CYDEV_PHUB_TDMEM27_ORIG_TD1 EQU 0x400078dc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_BASE +CYDEV_PHUB_TDMEM28_BASE EQU 0x400078e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_SIZE +CYDEV_PHUB_TDMEM28_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_ORIG_TD0 +CYDEV_PHUB_TDMEM28_ORIG_TD0 EQU 0x400078e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_ORIG_TD1 +CYDEV_PHUB_TDMEM28_ORIG_TD1 EQU 0x400078e4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_BASE +CYDEV_PHUB_TDMEM29_BASE EQU 0x400078e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_SIZE +CYDEV_PHUB_TDMEM29_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_ORIG_TD0 +CYDEV_PHUB_TDMEM29_ORIG_TD0 EQU 0x400078e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_ORIG_TD1 +CYDEV_PHUB_TDMEM29_ORIG_TD1 EQU 0x400078ec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_BASE +CYDEV_PHUB_TDMEM30_BASE EQU 0x400078f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_SIZE +CYDEV_PHUB_TDMEM30_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_ORIG_TD0 +CYDEV_PHUB_TDMEM30_ORIG_TD0 EQU 0x400078f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_ORIG_TD1 +CYDEV_PHUB_TDMEM30_ORIG_TD1 EQU 0x400078f4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_BASE +CYDEV_PHUB_TDMEM31_BASE EQU 0x400078f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_SIZE +CYDEV_PHUB_TDMEM31_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_ORIG_TD0 +CYDEV_PHUB_TDMEM31_ORIG_TD0 EQU 0x400078f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_ORIG_TD1 +CYDEV_PHUB_TDMEM31_ORIG_TD1 EQU 0x400078fc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_BASE +CYDEV_PHUB_TDMEM32_BASE EQU 0x40007900 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_SIZE +CYDEV_PHUB_TDMEM32_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_ORIG_TD0 +CYDEV_PHUB_TDMEM32_ORIG_TD0 EQU 0x40007900 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_ORIG_TD1 +CYDEV_PHUB_TDMEM32_ORIG_TD1 EQU 0x40007904 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_BASE +CYDEV_PHUB_TDMEM33_BASE EQU 0x40007908 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_SIZE +CYDEV_PHUB_TDMEM33_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_ORIG_TD0 +CYDEV_PHUB_TDMEM33_ORIG_TD0 EQU 0x40007908 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_ORIG_TD1 +CYDEV_PHUB_TDMEM33_ORIG_TD1 EQU 0x4000790c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_BASE +CYDEV_PHUB_TDMEM34_BASE EQU 0x40007910 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_SIZE +CYDEV_PHUB_TDMEM34_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_ORIG_TD0 +CYDEV_PHUB_TDMEM34_ORIG_TD0 EQU 0x40007910 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_ORIG_TD1 +CYDEV_PHUB_TDMEM34_ORIG_TD1 EQU 0x40007914 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_BASE +CYDEV_PHUB_TDMEM35_BASE EQU 0x40007918 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_SIZE +CYDEV_PHUB_TDMEM35_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_ORIG_TD0 +CYDEV_PHUB_TDMEM35_ORIG_TD0 EQU 0x40007918 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_ORIG_TD1 +CYDEV_PHUB_TDMEM35_ORIG_TD1 EQU 0x4000791c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_BASE +CYDEV_PHUB_TDMEM36_BASE EQU 0x40007920 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_SIZE +CYDEV_PHUB_TDMEM36_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_ORIG_TD0 +CYDEV_PHUB_TDMEM36_ORIG_TD0 EQU 0x40007920 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_ORIG_TD1 +CYDEV_PHUB_TDMEM36_ORIG_TD1 EQU 0x40007924 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_BASE +CYDEV_PHUB_TDMEM37_BASE EQU 0x40007928 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_SIZE +CYDEV_PHUB_TDMEM37_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_ORIG_TD0 +CYDEV_PHUB_TDMEM37_ORIG_TD0 EQU 0x40007928 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_ORIG_TD1 +CYDEV_PHUB_TDMEM37_ORIG_TD1 EQU 0x4000792c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_BASE +CYDEV_PHUB_TDMEM38_BASE EQU 0x40007930 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_SIZE +CYDEV_PHUB_TDMEM38_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_ORIG_TD0 +CYDEV_PHUB_TDMEM38_ORIG_TD0 EQU 0x40007930 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_ORIG_TD1 +CYDEV_PHUB_TDMEM38_ORIG_TD1 EQU 0x40007934 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_BASE +CYDEV_PHUB_TDMEM39_BASE EQU 0x40007938 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_SIZE +CYDEV_PHUB_TDMEM39_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_ORIG_TD0 +CYDEV_PHUB_TDMEM39_ORIG_TD0 EQU 0x40007938 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_ORIG_TD1 +CYDEV_PHUB_TDMEM39_ORIG_TD1 EQU 0x4000793c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_BASE +CYDEV_PHUB_TDMEM40_BASE EQU 0x40007940 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_SIZE +CYDEV_PHUB_TDMEM40_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_ORIG_TD0 +CYDEV_PHUB_TDMEM40_ORIG_TD0 EQU 0x40007940 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_ORIG_TD1 +CYDEV_PHUB_TDMEM40_ORIG_TD1 EQU 0x40007944 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_BASE +CYDEV_PHUB_TDMEM41_BASE EQU 0x40007948 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_SIZE +CYDEV_PHUB_TDMEM41_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_ORIG_TD0 +CYDEV_PHUB_TDMEM41_ORIG_TD0 EQU 0x40007948 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_ORIG_TD1 +CYDEV_PHUB_TDMEM41_ORIG_TD1 EQU 0x4000794c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_BASE +CYDEV_PHUB_TDMEM42_BASE EQU 0x40007950 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_SIZE +CYDEV_PHUB_TDMEM42_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_ORIG_TD0 +CYDEV_PHUB_TDMEM42_ORIG_TD0 EQU 0x40007950 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_ORIG_TD1 +CYDEV_PHUB_TDMEM42_ORIG_TD1 EQU 0x40007954 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_BASE +CYDEV_PHUB_TDMEM43_BASE EQU 0x40007958 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_SIZE +CYDEV_PHUB_TDMEM43_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_ORIG_TD0 +CYDEV_PHUB_TDMEM43_ORIG_TD0 EQU 0x40007958 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_ORIG_TD1 +CYDEV_PHUB_TDMEM43_ORIG_TD1 EQU 0x4000795c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_BASE +CYDEV_PHUB_TDMEM44_BASE EQU 0x40007960 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_SIZE +CYDEV_PHUB_TDMEM44_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_ORIG_TD0 +CYDEV_PHUB_TDMEM44_ORIG_TD0 EQU 0x40007960 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_ORIG_TD1 +CYDEV_PHUB_TDMEM44_ORIG_TD1 EQU 0x40007964 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_BASE +CYDEV_PHUB_TDMEM45_BASE EQU 0x40007968 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_SIZE +CYDEV_PHUB_TDMEM45_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_ORIG_TD0 +CYDEV_PHUB_TDMEM45_ORIG_TD0 EQU 0x40007968 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_ORIG_TD1 +CYDEV_PHUB_TDMEM45_ORIG_TD1 EQU 0x4000796c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_BASE +CYDEV_PHUB_TDMEM46_BASE EQU 0x40007970 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_SIZE +CYDEV_PHUB_TDMEM46_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_ORIG_TD0 +CYDEV_PHUB_TDMEM46_ORIG_TD0 EQU 0x40007970 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_ORIG_TD1 +CYDEV_PHUB_TDMEM46_ORIG_TD1 EQU 0x40007974 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_BASE +CYDEV_PHUB_TDMEM47_BASE EQU 0x40007978 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_SIZE +CYDEV_PHUB_TDMEM47_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_ORIG_TD0 +CYDEV_PHUB_TDMEM47_ORIG_TD0 EQU 0x40007978 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_ORIG_TD1 +CYDEV_PHUB_TDMEM47_ORIG_TD1 EQU 0x4000797c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_BASE +CYDEV_PHUB_TDMEM48_BASE EQU 0x40007980 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_SIZE +CYDEV_PHUB_TDMEM48_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_ORIG_TD0 +CYDEV_PHUB_TDMEM48_ORIG_TD0 EQU 0x40007980 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_ORIG_TD1 +CYDEV_PHUB_TDMEM48_ORIG_TD1 EQU 0x40007984 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_BASE +CYDEV_PHUB_TDMEM49_BASE EQU 0x40007988 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_SIZE +CYDEV_PHUB_TDMEM49_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_ORIG_TD0 +CYDEV_PHUB_TDMEM49_ORIG_TD0 EQU 0x40007988 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_ORIG_TD1 +CYDEV_PHUB_TDMEM49_ORIG_TD1 EQU 0x4000798c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_BASE +CYDEV_PHUB_TDMEM50_BASE EQU 0x40007990 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_SIZE +CYDEV_PHUB_TDMEM50_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_ORIG_TD0 +CYDEV_PHUB_TDMEM50_ORIG_TD0 EQU 0x40007990 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_ORIG_TD1 +CYDEV_PHUB_TDMEM50_ORIG_TD1 EQU 0x40007994 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_BASE +CYDEV_PHUB_TDMEM51_BASE EQU 0x40007998 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_SIZE +CYDEV_PHUB_TDMEM51_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_ORIG_TD0 +CYDEV_PHUB_TDMEM51_ORIG_TD0 EQU 0x40007998 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_ORIG_TD1 +CYDEV_PHUB_TDMEM51_ORIG_TD1 EQU 0x4000799c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_BASE +CYDEV_PHUB_TDMEM52_BASE EQU 0x400079a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_SIZE +CYDEV_PHUB_TDMEM52_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_ORIG_TD0 +CYDEV_PHUB_TDMEM52_ORIG_TD0 EQU 0x400079a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_ORIG_TD1 +CYDEV_PHUB_TDMEM52_ORIG_TD1 EQU 0x400079a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_BASE +CYDEV_PHUB_TDMEM53_BASE EQU 0x400079a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_SIZE +CYDEV_PHUB_TDMEM53_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_ORIG_TD0 +CYDEV_PHUB_TDMEM53_ORIG_TD0 EQU 0x400079a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_ORIG_TD1 +CYDEV_PHUB_TDMEM53_ORIG_TD1 EQU 0x400079ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_BASE +CYDEV_PHUB_TDMEM54_BASE EQU 0x400079b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_SIZE +CYDEV_PHUB_TDMEM54_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_ORIG_TD0 +CYDEV_PHUB_TDMEM54_ORIG_TD0 EQU 0x400079b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_ORIG_TD1 +CYDEV_PHUB_TDMEM54_ORIG_TD1 EQU 0x400079b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_BASE +CYDEV_PHUB_TDMEM55_BASE EQU 0x400079b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_SIZE +CYDEV_PHUB_TDMEM55_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_ORIG_TD0 +CYDEV_PHUB_TDMEM55_ORIG_TD0 EQU 0x400079b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_ORIG_TD1 +CYDEV_PHUB_TDMEM55_ORIG_TD1 EQU 0x400079bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_BASE +CYDEV_PHUB_TDMEM56_BASE EQU 0x400079c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_SIZE +CYDEV_PHUB_TDMEM56_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_ORIG_TD0 +CYDEV_PHUB_TDMEM56_ORIG_TD0 EQU 0x400079c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_ORIG_TD1 +CYDEV_PHUB_TDMEM56_ORIG_TD1 EQU 0x400079c4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_BASE +CYDEV_PHUB_TDMEM57_BASE EQU 0x400079c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_SIZE +CYDEV_PHUB_TDMEM57_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_ORIG_TD0 +CYDEV_PHUB_TDMEM57_ORIG_TD0 EQU 0x400079c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_ORIG_TD1 +CYDEV_PHUB_TDMEM57_ORIG_TD1 EQU 0x400079cc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_BASE +CYDEV_PHUB_TDMEM58_BASE EQU 0x400079d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_SIZE +CYDEV_PHUB_TDMEM58_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_ORIG_TD0 +CYDEV_PHUB_TDMEM58_ORIG_TD0 EQU 0x400079d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_ORIG_TD1 +CYDEV_PHUB_TDMEM58_ORIG_TD1 EQU 0x400079d4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_BASE +CYDEV_PHUB_TDMEM59_BASE EQU 0x400079d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_SIZE +CYDEV_PHUB_TDMEM59_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_ORIG_TD0 +CYDEV_PHUB_TDMEM59_ORIG_TD0 EQU 0x400079d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_ORIG_TD1 +CYDEV_PHUB_TDMEM59_ORIG_TD1 EQU 0x400079dc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_BASE +CYDEV_PHUB_TDMEM60_BASE EQU 0x400079e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_SIZE +CYDEV_PHUB_TDMEM60_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_ORIG_TD0 +CYDEV_PHUB_TDMEM60_ORIG_TD0 EQU 0x400079e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_ORIG_TD1 +CYDEV_PHUB_TDMEM60_ORIG_TD1 EQU 0x400079e4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_BASE +CYDEV_PHUB_TDMEM61_BASE EQU 0x400079e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_SIZE +CYDEV_PHUB_TDMEM61_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_ORIG_TD0 +CYDEV_PHUB_TDMEM61_ORIG_TD0 EQU 0x400079e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_ORIG_TD1 +CYDEV_PHUB_TDMEM61_ORIG_TD1 EQU 0x400079ec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_BASE +CYDEV_PHUB_TDMEM62_BASE EQU 0x400079f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_SIZE +CYDEV_PHUB_TDMEM62_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_ORIG_TD0 +CYDEV_PHUB_TDMEM62_ORIG_TD0 EQU 0x400079f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_ORIG_TD1 +CYDEV_PHUB_TDMEM62_ORIG_TD1 EQU 0x400079f4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_BASE +CYDEV_PHUB_TDMEM63_BASE EQU 0x400079f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_SIZE +CYDEV_PHUB_TDMEM63_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_ORIG_TD0 +CYDEV_PHUB_TDMEM63_ORIG_TD0 EQU 0x400079f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_ORIG_TD1 +CYDEV_PHUB_TDMEM63_ORIG_TD1 EQU 0x400079fc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_BASE +CYDEV_PHUB_TDMEM64_BASE EQU 0x40007a00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_SIZE +CYDEV_PHUB_TDMEM64_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_ORIG_TD0 +CYDEV_PHUB_TDMEM64_ORIG_TD0 EQU 0x40007a00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_ORIG_TD1 +CYDEV_PHUB_TDMEM64_ORIG_TD1 EQU 0x40007a04 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_BASE +CYDEV_PHUB_TDMEM65_BASE EQU 0x40007a08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_SIZE +CYDEV_PHUB_TDMEM65_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_ORIG_TD0 +CYDEV_PHUB_TDMEM65_ORIG_TD0 EQU 0x40007a08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_ORIG_TD1 +CYDEV_PHUB_TDMEM65_ORIG_TD1 EQU 0x40007a0c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_BASE +CYDEV_PHUB_TDMEM66_BASE EQU 0x40007a10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_SIZE +CYDEV_PHUB_TDMEM66_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_ORIG_TD0 +CYDEV_PHUB_TDMEM66_ORIG_TD0 EQU 0x40007a10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_ORIG_TD1 +CYDEV_PHUB_TDMEM66_ORIG_TD1 EQU 0x40007a14 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_BASE +CYDEV_PHUB_TDMEM67_BASE EQU 0x40007a18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_SIZE +CYDEV_PHUB_TDMEM67_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_ORIG_TD0 +CYDEV_PHUB_TDMEM67_ORIG_TD0 EQU 0x40007a18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_ORIG_TD1 +CYDEV_PHUB_TDMEM67_ORIG_TD1 EQU 0x40007a1c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_BASE +CYDEV_PHUB_TDMEM68_BASE EQU 0x40007a20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_SIZE +CYDEV_PHUB_TDMEM68_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_ORIG_TD0 +CYDEV_PHUB_TDMEM68_ORIG_TD0 EQU 0x40007a20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_ORIG_TD1 +CYDEV_PHUB_TDMEM68_ORIG_TD1 EQU 0x40007a24 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_BASE +CYDEV_PHUB_TDMEM69_BASE EQU 0x40007a28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_SIZE +CYDEV_PHUB_TDMEM69_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_ORIG_TD0 +CYDEV_PHUB_TDMEM69_ORIG_TD0 EQU 0x40007a28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_ORIG_TD1 +CYDEV_PHUB_TDMEM69_ORIG_TD1 EQU 0x40007a2c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_BASE +CYDEV_PHUB_TDMEM70_BASE EQU 0x40007a30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_SIZE +CYDEV_PHUB_TDMEM70_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_ORIG_TD0 +CYDEV_PHUB_TDMEM70_ORIG_TD0 EQU 0x40007a30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_ORIG_TD1 +CYDEV_PHUB_TDMEM70_ORIG_TD1 EQU 0x40007a34 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_BASE +CYDEV_PHUB_TDMEM71_BASE EQU 0x40007a38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_SIZE +CYDEV_PHUB_TDMEM71_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_ORIG_TD0 +CYDEV_PHUB_TDMEM71_ORIG_TD0 EQU 0x40007a38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_ORIG_TD1 +CYDEV_PHUB_TDMEM71_ORIG_TD1 EQU 0x40007a3c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_BASE +CYDEV_PHUB_TDMEM72_BASE EQU 0x40007a40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_SIZE +CYDEV_PHUB_TDMEM72_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_ORIG_TD0 +CYDEV_PHUB_TDMEM72_ORIG_TD0 EQU 0x40007a40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_ORIG_TD1 +CYDEV_PHUB_TDMEM72_ORIG_TD1 EQU 0x40007a44 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_BASE +CYDEV_PHUB_TDMEM73_BASE EQU 0x40007a48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_SIZE +CYDEV_PHUB_TDMEM73_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_ORIG_TD0 +CYDEV_PHUB_TDMEM73_ORIG_TD0 EQU 0x40007a48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_ORIG_TD1 +CYDEV_PHUB_TDMEM73_ORIG_TD1 EQU 0x40007a4c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_BASE +CYDEV_PHUB_TDMEM74_BASE EQU 0x40007a50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_SIZE +CYDEV_PHUB_TDMEM74_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_ORIG_TD0 +CYDEV_PHUB_TDMEM74_ORIG_TD0 EQU 0x40007a50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_ORIG_TD1 +CYDEV_PHUB_TDMEM74_ORIG_TD1 EQU 0x40007a54 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_BASE +CYDEV_PHUB_TDMEM75_BASE EQU 0x40007a58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_SIZE +CYDEV_PHUB_TDMEM75_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_ORIG_TD0 +CYDEV_PHUB_TDMEM75_ORIG_TD0 EQU 0x40007a58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_ORIG_TD1 +CYDEV_PHUB_TDMEM75_ORIG_TD1 EQU 0x40007a5c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_BASE +CYDEV_PHUB_TDMEM76_BASE EQU 0x40007a60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_SIZE +CYDEV_PHUB_TDMEM76_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_ORIG_TD0 +CYDEV_PHUB_TDMEM76_ORIG_TD0 EQU 0x40007a60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_ORIG_TD1 +CYDEV_PHUB_TDMEM76_ORIG_TD1 EQU 0x40007a64 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_BASE +CYDEV_PHUB_TDMEM77_BASE EQU 0x40007a68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_SIZE +CYDEV_PHUB_TDMEM77_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_ORIG_TD0 +CYDEV_PHUB_TDMEM77_ORIG_TD0 EQU 0x40007a68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_ORIG_TD1 +CYDEV_PHUB_TDMEM77_ORIG_TD1 EQU 0x40007a6c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_BASE +CYDEV_PHUB_TDMEM78_BASE EQU 0x40007a70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_SIZE +CYDEV_PHUB_TDMEM78_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_ORIG_TD0 +CYDEV_PHUB_TDMEM78_ORIG_TD0 EQU 0x40007a70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_ORIG_TD1 +CYDEV_PHUB_TDMEM78_ORIG_TD1 EQU 0x40007a74 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_BASE +CYDEV_PHUB_TDMEM79_BASE EQU 0x40007a78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_SIZE +CYDEV_PHUB_TDMEM79_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_ORIG_TD0 +CYDEV_PHUB_TDMEM79_ORIG_TD0 EQU 0x40007a78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_ORIG_TD1 +CYDEV_PHUB_TDMEM79_ORIG_TD1 EQU 0x40007a7c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_BASE +CYDEV_PHUB_TDMEM80_BASE EQU 0x40007a80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_SIZE +CYDEV_PHUB_TDMEM80_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_ORIG_TD0 +CYDEV_PHUB_TDMEM80_ORIG_TD0 EQU 0x40007a80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_ORIG_TD1 +CYDEV_PHUB_TDMEM80_ORIG_TD1 EQU 0x40007a84 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_BASE +CYDEV_PHUB_TDMEM81_BASE EQU 0x40007a88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_SIZE +CYDEV_PHUB_TDMEM81_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_ORIG_TD0 +CYDEV_PHUB_TDMEM81_ORIG_TD0 EQU 0x40007a88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_ORIG_TD1 +CYDEV_PHUB_TDMEM81_ORIG_TD1 EQU 0x40007a8c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_BASE +CYDEV_PHUB_TDMEM82_BASE EQU 0x40007a90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_SIZE +CYDEV_PHUB_TDMEM82_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_ORIG_TD0 +CYDEV_PHUB_TDMEM82_ORIG_TD0 EQU 0x40007a90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_ORIG_TD1 +CYDEV_PHUB_TDMEM82_ORIG_TD1 EQU 0x40007a94 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_BASE +CYDEV_PHUB_TDMEM83_BASE EQU 0x40007a98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_SIZE +CYDEV_PHUB_TDMEM83_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_ORIG_TD0 +CYDEV_PHUB_TDMEM83_ORIG_TD0 EQU 0x40007a98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_ORIG_TD1 +CYDEV_PHUB_TDMEM83_ORIG_TD1 EQU 0x40007a9c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_BASE +CYDEV_PHUB_TDMEM84_BASE EQU 0x40007aa0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_SIZE +CYDEV_PHUB_TDMEM84_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_ORIG_TD0 +CYDEV_PHUB_TDMEM84_ORIG_TD0 EQU 0x40007aa0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_ORIG_TD1 +CYDEV_PHUB_TDMEM84_ORIG_TD1 EQU 0x40007aa4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_BASE +CYDEV_PHUB_TDMEM85_BASE EQU 0x40007aa8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_SIZE +CYDEV_PHUB_TDMEM85_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_ORIG_TD0 +CYDEV_PHUB_TDMEM85_ORIG_TD0 EQU 0x40007aa8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_ORIG_TD1 +CYDEV_PHUB_TDMEM85_ORIG_TD1 EQU 0x40007aac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_BASE +CYDEV_PHUB_TDMEM86_BASE EQU 0x40007ab0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_SIZE +CYDEV_PHUB_TDMEM86_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_ORIG_TD0 +CYDEV_PHUB_TDMEM86_ORIG_TD0 EQU 0x40007ab0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_ORIG_TD1 +CYDEV_PHUB_TDMEM86_ORIG_TD1 EQU 0x40007ab4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_BASE +CYDEV_PHUB_TDMEM87_BASE EQU 0x40007ab8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_SIZE +CYDEV_PHUB_TDMEM87_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_ORIG_TD0 +CYDEV_PHUB_TDMEM87_ORIG_TD0 EQU 0x40007ab8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_ORIG_TD1 +CYDEV_PHUB_TDMEM87_ORIG_TD1 EQU 0x40007abc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_BASE +CYDEV_PHUB_TDMEM88_BASE EQU 0x40007ac0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_SIZE +CYDEV_PHUB_TDMEM88_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_ORIG_TD0 +CYDEV_PHUB_TDMEM88_ORIG_TD0 EQU 0x40007ac0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_ORIG_TD1 +CYDEV_PHUB_TDMEM88_ORIG_TD1 EQU 0x40007ac4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_BASE +CYDEV_PHUB_TDMEM89_BASE EQU 0x40007ac8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_SIZE +CYDEV_PHUB_TDMEM89_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_ORIG_TD0 +CYDEV_PHUB_TDMEM89_ORIG_TD0 EQU 0x40007ac8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_ORIG_TD1 +CYDEV_PHUB_TDMEM89_ORIG_TD1 EQU 0x40007acc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_BASE +CYDEV_PHUB_TDMEM90_BASE EQU 0x40007ad0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_SIZE +CYDEV_PHUB_TDMEM90_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_ORIG_TD0 +CYDEV_PHUB_TDMEM90_ORIG_TD0 EQU 0x40007ad0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_ORIG_TD1 +CYDEV_PHUB_TDMEM90_ORIG_TD1 EQU 0x40007ad4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_BASE +CYDEV_PHUB_TDMEM91_BASE EQU 0x40007ad8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_SIZE +CYDEV_PHUB_TDMEM91_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_ORIG_TD0 +CYDEV_PHUB_TDMEM91_ORIG_TD0 EQU 0x40007ad8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_ORIG_TD1 +CYDEV_PHUB_TDMEM91_ORIG_TD1 EQU 0x40007adc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_BASE +CYDEV_PHUB_TDMEM92_BASE EQU 0x40007ae0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_SIZE +CYDEV_PHUB_TDMEM92_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_ORIG_TD0 +CYDEV_PHUB_TDMEM92_ORIG_TD0 EQU 0x40007ae0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_ORIG_TD1 +CYDEV_PHUB_TDMEM92_ORIG_TD1 EQU 0x40007ae4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_BASE +CYDEV_PHUB_TDMEM93_BASE EQU 0x40007ae8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_SIZE +CYDEV_PHUB_TDMEM93_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_ORIG_TD0 +CYDEV_PHUB_TDMEM93_ORIG_TD0 EQU 0x40007ae8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_ORIG_TD1 +CYDEV_PHUB_TDMEM93_ORIG_TD1 EQU 0x40007aec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_BASE +CYDEV_PHUB_TDMEM94_BASE EQU 0x40007af0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_SIZE +CYDEV_PHUB_TDMEM94_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_ORIG_TD0 +CYDEV_PHUB_TDMEM94_ORIG_TD0 EQU 0x40007af0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_ORIG_TD1 +CYDEV_PHUB_TDMEM94_ORIG_TD1 EQU 0x40007af4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_BASE +CYDEV_PHUB_TDMEM95_BASE EQU 0x40007af8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_SIZE +CYDEV_PHUB_TDMEM95_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_ORIG_TD0 +CYDEV_PHUB_TDMEM95_ORIG_TD0 EQU 0x40007af8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_ORIG_TD1 +CYDEV_PHUB_TDMEM95_ORIG_TD1 EQU 0x40007afc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_BASE +CYDEV_PHUB_TDMEM96_BASE EQU 0x40007b00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_SIZE +CYDEV_PHUB_TDMEM96_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_ORIG_TD0 +CYDEV_PHUB_TDMEM96_ORIG_TD0 EQU 0x40007b00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_ORIG_TD1 +CYDEV_PHUB_TDMEM96_ORIG_TD1 EQU 0x40007b04 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_BASE +CYDEV_PHUB_TDMEM97_BASE EQU 0x40007b08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_SIZE +CYDEV_PHUB_TDMEM97_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_ORIG_TD0 +CYDEV_PHUB_TDMEM97_ORIG_TD0 EQU 0x40007b08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_ORIG_TD1 +CYDEV_PHUB_TDMEM97_ORIG_TD1 EQU 0x40007b0c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_BASE +CYDEV_PHUB_TDMEM98_BASE EQU 0x40007b10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_SIZE +CYDEV_PHUB_TDMEM98_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_ORIG_TD0 +CYDEV_PHUB_TDMEM98_ORIG_TD0 EQU 0x40007b10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_ORIG_TD1 +CYDEV_PHUB_TDMEM98_ORIG_TD1 EQU 0x40007b14 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_BASE +CYDEV_PHUB_TDMEM99_BASE EQU 0x40007b18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_SIZE +CYDEV_PHUB_TDMEM99_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_ORIG_TD0 +CYDEV_PHUB_TDMEM99_ORIG_TD0 EQU 0x40007b18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_ORIG_TD1 +CYDEV_PHUB_TDMEM99_ORIG_TD1 EQU 0x40007b1c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_BASE +CYDEV_PHUB_TDMEM100_BASE EQU 0x40007b20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_SIZE +CYDEV_PHUB_TDMEM100_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_ORIG_TD0 +CYDEV_PHUB_TDMEM100_ORIG_TD0 EQU 0x40007b20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_ORIG_TD1 +CYDEV_PHUB_TDMEM100_ORIG_TD1 EQU 0x40007b24 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_BASE +CYDEV_PHUB_TDMEM101_BASE EQU 0x40007b28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_SIZE +CYDEV_PHUB_TDMEM101_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_ORIG_TD0 +CYDEV_PHUB_TDMEM101_ORIG_TD0 EQU 0x40007b28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_ORIG_TD1 +CYDEV_PHUB_TDMEM101_ORIG_TD1 EQU 0x40007b2c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_BASE +CYDEV_PHUB_TDMEM102_BASE EQU 0x40007b30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_SIZE +CYDEV_PHUB_TDMEM102_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_ORIG_TD0 +CYDEV_PHUB_TDMEM102_ORIG_TD0 EQU 0x40007b30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_ORIG_TD1 +CYDEV_PHUB_TDMEM102_ORIG_TD1 EQU 0x40007b34 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_BASE +CYDEV_PHUB_TDMEM103_BASE EQU 0x40007b38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_SIZE +CYDEV_PHUB_TDMEM103_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_ORIG_TD0 +CYDEV_PHUB_TDMEM103_ORIG_TD0 EQU 0x40007b38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_ORIG_TD1 +CYDEV_PHUB_TDMEM103_ORIG_TD1 EQU 0x40007b3c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_BASE +CYDEV_PHUB_TDMEM104_BASE EQU 0x40007b40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_SIZE +CYDEV_PHUB_TDMEM104_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_ORIG_TD0 +CYDEV_PHUB_TDMEM104_ORIG_TD0 EQU 0x40007b40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_ORIG_TD1 +CYDEV_PHUB_TDMEM104_ORIG_TD1 EQU 0x40007b44 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_BASE +CYDEV_PHUB_TDMEM105_BASE EQU 0x40007b48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_SIZE +CYDEV_PHUB_TDMEM105_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_ORIG_TD0 +CYDEV_PHUB_TDMEM105_ORIG_TD0 EQU 0x40007b48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_ORIG_TD1 +CYDEV_PHUB_TDMEM105_ORIG_TD1 EQU 0x40007b4c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_BASE +CYDEV_PHUB_TDMEM106_BASE EQU 0x40007b50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_SIZE +CYDEV_PHUB_TDMEM106_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_ORIG_TD0 +CYDEV_PHUB_TDMEM106_ORIG_TD0 EQU 0x40007b50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_ORIG_TD1 +CYDEV_PHUB_TDMEM106_ORIG_TD1 EQU 0x40007b54 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_BASE +CYDEV_PHUB_TDMEM107_BASE EQU 0x40007b58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_SIZE +CYDEV_PHUB_TDMEM107_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_ORIG_TD0 +CYDEV_PHUB_TDMEM107_ORIG_TD0 EQU 0x40007b58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_ORIG_TD1 +CYDEV_PHUB_TDMEM107_ORIG_TD1 EQU 0x40007b5c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_BASE +CYDEV_PHUB_TDMEM108_BASE EQU 0x40007b60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_SIZE +CYDEV_PHUB_TDMEM108_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_ORIG_TD0 +CYDEV_PHUB_TDMEM108_ORIG_TD0 EQU 0x40007b60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_ORIG_TD1 +CYDEV_PHUB_TDMEM108_ORIG_TD1 EQU 0x40007b64 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_BASE +CYDEV_PHUB_TDMEM109_BASE EQU 0x40007b68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_SIZE +CYDEV_PHUB_TDMEM109_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_ORIG_TD0 +CYDEV_PHUB_TDMEM109_ORIG_TD0 EQU 0x40007b68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_ORIG_TD1 +CYDEV_PHUB_TDMEM109_ORIG_TD1 EQU 0x40007b6c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_BASE +CYDEV_PHUB_TDMEM110_BASE EQU 0x40007b70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_SIZE +CYDEV_PHUB_TDMEM110_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_ORIG_TD0 +CYDEV_PHUB_TDMEM110_ORIG_TD0 EQU 0x40007b70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_ORIG_TD1 +CYDEV_PHUB_TDMEM110_ORIG_TD1 EQU 0x40007b74 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_BASE +CYDEV_PHUB_TDMEM111_BASE EQU 0x40007b78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_SIZE +CYDEV_PHUB_TDMEM111_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_ORIG_TD0 +CYDEV_PHUB_TDMEM111_ORIG_TD0 EQU 0x40007b78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_ORIG_TD1 +CYDEV_PHUB_TDMEM111_ORIG_TD1 EQU 0x40007b7c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_BASE +CYDEV_PHUB_TDMEM112_BASE EQU 0x40007b80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_SIZE +CYDEV_PHUB_TDMEM112_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_ORIG_TD0 +CYDEV_PHUB_TDMEM112_ORIG_TD0 EQU 0x40007b80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_ORIG_TD1 +CYDEV_PHUB_TDMEM112_ORIG_TD1 EQU 0x40007b84 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_BASE +CYDEV_PHUB_TDMEM113_BASE EQU 0x40007b88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_SIZE +CYDEV_PHUB_TDMEM113_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_ORIG_TD0 +CYDEV_PHUB_TDMEM113_ORIG_TD0 EQU 0x40007b88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_ORIG_TD1 +CYDEV_PHUB_TDMEM113_ORIG_TD1 EQU 0x40007b8c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_BASE +CYDEV_PHUB_TDMEM114_BASE EQU 0x40007b90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_SIZE +CYDEV_PHUB_TDMEM114_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_ORIG_TD0 +CYDEV_PHUB_TDMEM114_ORIG_TD0 EQU 0x40007b90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_ORIG_TD1 +CYDEV_PHUB_TDMEM114_ORIG_TD1 EQU 0x40007b94 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_BASE +CYDEV_PHUB_TDMEM115_BASE EQU 0x40007b98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_SIZE +CYDEV_PHUB_TDMEM115_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_ORIG_TD0 +CYDEV_PHUB_TDMEM115_ORIG_TD0 EQU 0x40007b98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_ORIG_TD1 +CYDEV_PHUB_TDMEM115_ORIG_TD1 EQU 0x40007b9c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_BASE +CYDEV_PHUB_TDMEM116_BASE EQU 0x40007ba0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_SIZE +CYDEV_PHUB_TDMEM116_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_ORIG_TD0 +CYDEV_PHUB_TDMEM116_ORIG_TD0 EQU 0x40007ba0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_ORIG_TD1 +CYDEV_PHUB_TDMEM116_ORIG_TD1 EQU 0x40007ba4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_BASE +CYDEV_PHUB_TDMEM117_BASE EQU 0x40007ba8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_SIZE +CYDEV_PHUB_TDMEM117_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_ORIG_TD0 +CYDEV_PHUB_TDMEM117_ORIG_TD0 EQU 0x40007ba8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_ORIG_TD1 +CYDEV_PHUB_TDMEM117_ORIG_TD1 EQU 0x40007bac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_BASE +CYDEV_PHUB_TDMEM118_BASE EQU 0x40007bb0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_SIZE +CYDEV_PHUB_TDMEM118_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_ORIG_TD0 +CYDEV_PHUB_TDMEM118_ORIG_TD0 EQU 0x40007bb0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_ORIG_TD1 +CYDEV_PHUB_TDMEM118_ORIG_TD1 EQU 0x40007bb4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_BASE +CYDEV_PHUB_TDMEM119_BASE EQU 0x40007bb8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_SIZE +CYDEV_PHUB_TDMEM119_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_ORIG_TD0 +CYDEV_PHUB_TDMEM119_ORIG_TD0 EQU 0x40007bb8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_ORIG_TD1 +CYDEV_PHUB_TDMEM119_ORIG_TD1 EQU 0x40007bbc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_BASE +CYDEV_PHUB_TDMEM120_BASE EQU 0x40007bc0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_SIZE +CYDEV_PHUB_TDMEM120_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_ORIG_TD0 +CYDEV_PHUB_TDMEM120_ORIG_TD0 EQU 0x40007bc0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_ORIG_TD1 +CYDEV_PHUB_TDMEM120_ORIG_TD1 EQU 0x40007bc4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_BASE +CYDEV_PHUB_TDMEM121_BASE EQU 0x40007bc8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_SIZE +CYDEV_PHUB_TDMEM121_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_ORIG_TD0 +CYDEV_PHUB_TDMEM121_ORIG_TD0 EQU 0x40007bc8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_ORIG_TD1 +CYDEV_PHUB_TDMEM121_ORIG_TD1 EQU 0x40007bcc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_BASE +CYDEV_PHUB_TDMEM122_BASE EQU 0x40007bd0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_SIZE +CYDEV_PHUB_TDMEM122_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_ORIG_TD0 +CYDEV_PHUB_TDMEM122_ORIG_TD0 EQU 0x40007bd0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_ORIG_TD1 +CYDEV_PHUB_TDMEM122_ORIG_TD1 EQU 0x40007bd4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_BASE +CYDEV_PHUB_TDMEM123_BASE EQU 0x40007bd8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_SIZE +CYDEV_PHUB_TDMEM123_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_ORIG_TD0 +CYDEV_PHUB_TDMEM123_ORIG_TD0 EQU 0x40007bd8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_ORIG_TD1 +CYDEV_PHUB_TDMEM123_ORIG_TD1 EQU 0x40007bdc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_BASE +CYDEV_PHUB_TDMEM124_BASE EQU 0x40007be0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_SIZE +CYDEV_PHUB_TDMEM124_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_ORIG_TD0 +CYDEV_PHUB_TDMEM124_ORIG_TD0 EQU 0x40007be0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_ORIG_TD1 +CYDEV_PHUB_TDMEM124_ORIG_TD1 EQU 0x40007be4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_BASE +CYDEV_PHUB_TDMEM125_BASE EQU 0x40007be8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_SIZE +CYDEV_PHUB_TDMEM125_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_ORIG_TD0 +CYDEV_PHUB_TDMEM125_ORIG_TD0 EQU 0x40007be8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_ORIG_TD1 +CYDEV_PHUB_TDMEM125_ORIG_TD1 EQU 0x40007bec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_BASE +CYDEV_PHUB_TDMEM126_BASE EQU 0x40007bf0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_SIZE +CYDEV_PHUB_TDMEM126_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_ORIG_TD0 +CYDEV_PHUB_TDMEM126_ORIG_TD0 EQU 0x40007bf0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_ORIG_TD1 +CYDEV_PHUB_TDMEM126_ORIG_TD1 EQU 0x40007bf4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_BASE +CYDEV_PHUB_TDMEM127_BASE EQU 0x40007bf8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_SIZE +CYDEV_PHUB_TDMEM127_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_ORIG_TD0 +CYDEV_PHUB_TDMEM127_ORIG_TD0 EQU 0x40007bf8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_ORIG_TD1 +CYDEV_PHUB_TDMEM127_ORIG_TD1 EQU 0x40007bfc + ENDIF + IF :LNOT::DEF:CYDEV_EE_BASE +CYDEV_EE_BASE EQU 0x40008000 + ENDIF + IF :LNOT::DEF:CYDEV_EE_SIZE +CYDEV_EE_SIZE EQU 0x00000800 + ENDIF + IF :LNOT::DEF:CYDEV_EE_DATA_MBASE +CYDEV_EE_DATA_MBASE EQU 0x40008000 + ENDIF + IF :LNOT::DEF:CYDEV_EE_DATA_MSIZE +CYDEV_EE_DATA_MSIZE EQU 0x00000800 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_BASE +CYDEV_CAN0_BASE EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_SIZE +CYDEV_CAN0_SIZE EQU 0x000002a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_BASE +CYDEV_CAN0_CSR_BASE EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_SIZE +CYDEV_CAN0_CSR_SIZE EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_INT_SR +CYDEV_CAN0_CSR_INT_SR EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_INT_EN +CYDEV_CAN0_CSR_INT_EN EQU 0x4000a004 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_BUF_SR +CYDEV_CAN0_CSR_BUF_SR EQU 0x4000a008 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_ERR_SR +CYDEV_CAN0_CSR_ERR_SR EQU 0x4000a00c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_CMD +CYDEV_CAN0_CSR_CMD EQU 0x4000a010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_CFG +CYDEV_CAN0_CSR_CFG EQU 0x4000a014 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_BASE +CYDEV_CAN0_TX0_BASE EQU 0x4000a020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_SIZE +CYDEV_CAN0_TX0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_CMD +CYDEV_CAN0_TX0_CMD EQU 0x4000a020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_ID +CYDEV_CAN0_TX0_ID EQU 0x4000a024 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_DH +CYDEV_CAN0_TX0_DH EQU 0x4000a028 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_DL +CYDEV_CAN0_TX0_DL EQU 0x4000a02c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_BASE +CYDEV_CAN0_TX1_BASE EQU 0x4000a030 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_SIZE +CYDEV_CAN0_TX1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_CMD +CYDEV_CAN0_TX1_CMD EQU 0x4000a030 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_ID +CYDEV_CAN0_TX1_ID EQU 0x4000a034 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_DH +CYDEV_CAN0_TX1_DH EQU 0x4000a038 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_DL +CYDEV_CAN0_TX1_DL EQU 0x4000a03c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_BASE +CYDEV_CAN0_TX2_BASE EQU 0x4000a040 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_SIZE +CYDEV_CAN0_TX2_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_CMD +CYDEV_CAN0_TX2_CMD EQU 0x4000a040 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_ID +CYDEV_CAN0_TX2_ID EQU 0x4000a044 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_DH +CYDEV_CAN0_TX2_DH EQU 0x4000a048 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_DL +CYDEV_CAN0_TX2_DL EQU 0x4000a04c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_BASE +CYDEV_CAN0_TX3_BASE EQU 0x4000a050 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_SIZE +CYDEV_CAN0_TX3_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_CMD +CYDEV_CAN0_TX3_CMD EQU 0x4000a050 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_ID +CYDEV_CAN0_TX3_ID EQU 0x4000a054 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_DH +CYDEV_CAN0_TX3_DH EQU 0x4000a058 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_DL +CYDEV_CAN0_TX3_DL EQU 0x4000a05c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_BASE +CYDEV_CAN0_TX4_BASE EQU 0x4000a060 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_SIZE +CYDEV_CAN0_TX4_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_CMD +CYDEV_CAN0_TX4_CMD EQU 0x4000a060 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_ID +CYDEV_CAN0_TX4_ID EQU 0x4000a064 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_DH +CYDEV_CAN0_TX4_DH EQU 0x4000a068 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_DL +CYDEV_CAN0_TX4_DL EQU 0x4000a06c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_BASE +CYDEV_CAN0_TX5_BASE EQU 0x4000a070 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_SIZE +CYDEV_CAN0_TX5_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_CMD +CYDEV_CAN0_TX5_CMD EQU 0x4000a070 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_ID +CYDEV_CAN0_TX5_ID EQU 0x4000a074 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_DH +CYDEV_CAN0_TX5_DH EQU 0x4000a078 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_DL +CYDEV_CAN0_TX5_DL EQU 0x4000a07c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_BASE +CYDEV_CAN0_TX6_BASE EQU 0x4000a080 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_SIZE +CYDEV_CAN0_TX6_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_CMD +CYDEV_CAN0_TX6_CMD EQU 0x4000a080 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_ID +CYDEV_CAN0_TX6_ID EQU 0x4000a084 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_DH +CYDEV_CAN0_TX6_DH EQU 0x4000a088 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_DL +CYDEV_CAN0_TX6_DL EQU 0x4000a08c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_BASE +CYDEV_CAN0_TX7_BASE EQU 0x4000a090 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_SIZE +CYDEV_CAN0_TX7_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_CMD +CYDEV_CAN0_TX7_CMD EQU 0x4000a090 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_ID +CYDEV_CAN0_TX7_ID EQU 0x4000a094 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_DH +CYDEV_CAN0_TX7_DH EQU 0x4000a098 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_DL +CYDEV_CAN0_TX7_DL EQU 0x4000a09c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_BASE +CYDEV_CAN0_RX0_BASE EQU 0x4000a0a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_SIZE +CYDEV_CAN0_RX0_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_CMD +CYDEV_CAN0_RX0_CMD EQU 0x4000a0a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_ID +CYDEV_CAN0_RX0_ID EQU 0x4000a0a4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_DH +CYDEV_CAN0_RX0_DH EQU 0x4000a0a8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_DL +CYDEV_CAN0_RX0_DL EQU 0x4000a0ac + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_AMR +CYDEV_CAN0_RX0_AMR EQU 0x4000a0b0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_ACR +CYDEV_CAN0_RX0_ACR EQU 0x4000a0b4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_AMRD +CYDEV_CAN0_RX0_AMRD EQU 0x4000a0b8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_ACRD +CYDEV_CAN0_RX0_ACRD EQU 0x4000a0bc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_BASE +CYDEV_CAN0_RX1_BASE EQU 0x4000a0c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_SIZE +CYDEV_CAN0_RX1_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_CMD +CYDEV_CAN0_RX1_CMD EQU 0x4000a0c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_ID +CYDEV_CAN0_RX1_ID EQU 0x4000a0c4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_DH +CYDEV_CAN0_RX1_DH EQU 0x4000a0c8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_DL +CYDEV_CAN0_RX1_DL EQU 0x4000a0cc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_AMR +CYDEV_CAN0_RX1_AMR EQU 0x4000a0d0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_ACR +CYDEV_CAN0_RX1_ACR EQU 0x4000a0d4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_AMRD +CYDEV_CAN0_RX1_AMRD EQU 0x4000a0d8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_ACRD +CYDEV_CAN0_RX1_ACRD EQU 0x4000a0dc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_BASE +CYDEV_CAN0_RX2_BASE EQU 0x4000a0e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_SIZE +CYDEV_CAN0_RX2_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_CMD +CYDEV_CAN0_RX2_CMD EQU 0x4000a0e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_ID +CYDEV_CAN0_RX2_ID EQU 0x4000a0e4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_DH +CYDEV_CAN0_RX2_DH EQU 0x4000a0e8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_DL +CYDEV_CAN0_RX2_DL EQU 0x4000a0ec + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_AMR +CYDEV_CAN0_RX2_AMR EQU 0x4000a0f0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_ACR +CYDEV_CAN0_RX2_ACR EQU 0x4000a0f4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_AMRD +CYDEV_CAN0_RX2_AMRD EQU 0x4000a0f8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_ACRD +CYDEV_CAN0_RX2_ACRD EQU 0x4000a0fc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_BASE +CYDEV_CAN0_RX3_BASE EQU 0x4000a100 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_SIZE +CYDEV_CAN0_RX3_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_CMD +CYDEV_CAN0_RX3_CMD EQU 0x4000a100 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_ID +CYDEV_CAN0_RX3_ID EQU 0x4000a104 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_DH +CYDEV_CAN0_RX3_DH EQU 0x4000a108 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_DL +CYDEV_CAN0_RX3_DL EQU 0x4000a10c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_AMR +CYDEV_CAN0_RX3_AMR EQU 0x4000a110 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_ACR +CYDEV_CAN0_RX3_ACR EQU 0x4000a114 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_AMRD +CYDEV_CAN0_RX3_AMRD EQU 0x4000a118 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_ACRD +CYDEV_CAN0_RX3_ACRD EQU 0x4000a11c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_BASE +CYDEV_CAN0_RX4_BASE EQU 0x4000a120 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_SIZE +CYDEV_CAN0_RX4_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_CMD +CYDEV_CAN0_RX4_CMD EQU 0x4000a120 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_ID +CYDEV_CAN0_RX4_ID EQU 0x4000a124 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_DH +CYDEV_CAN0_RX4_DH EQU 0x4000a128 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_DL +CYDEV_CAN0_RX4_DL EQU 0x4000a12c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_AMR +CYDEV_CAN0_RX4_AMR EQU 0x4000a130 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_ACR +CYDEV_CAN0_RX4_ACR EQU 0x4000a134 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_AMRD +CYDEV_CAN0_RX4_AMRD EQU 0x4000a138 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_ACRD +CYDEV_CAN0_RX4_ACRD EQU 0x4000a13c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_BASE +CYDEV_CAN0_RX5_BASE EQU 0x4000a140 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_SIZE +CYDEV_CAN0_RX5_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_CMD +CYDEV_CAN0_RX5_CMD EQU 0x4000a140 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_ID +CYDEV_CAN0_RX5_ID EQU 0x4000a144 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_DH +CYDEV_CAN0_RX5_DH EQU 0x4000a148 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_DL +CYDEV_CAN0_RX5_DL EQU 0x4000a14c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_AMR +CYDEV_CAN0_RX5_AMR EQU 0x4000a150 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_ACR +CYDEV_CAN0_RX5_ACR EQU 0x4000a154 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_AMRD +CYDEV_CAN0_RX5_AMRD EQU 0x4000a158 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_ACRD +CYDEV_CAN0_RX5_ACRD EQU 0x4000a15c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_BASE +CYDEV_CAN0_RX6_BASE EQU 0x4000a160 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_SIZE +CYDEV_CAN0_RX6_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_CMD +CYDEV_CAN0_RX6_CMD EQU 0x4000a160 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_ID +CYDEV_CAN0_RX6_ID EQU 0x4000a164 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_DH +CYDEV_CAN0_RX6_DH EQU 0x4000a168 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_DL +CYDEV_CAN0_RX6_DL EQU 0x4000a16c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_AMR +CYDEV_CAN0_RX6_AMR EQU 0x4000a170 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_ACR +CYDEV_CAN0_RX6_ACR EQU 0x4000a174 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_AMRD +CYDEV_CAN0_RX6_AMRD EQU 0x4000a178 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_ACRD +CYDEV_CAN0_RX6_ACRD EQU 0x4000a17c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_BASE +CYDEV_CAN0_RX7_BASE EQU 0x4000a180 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_SIZE +CYDEV_CAN0_RX7_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_CMD +CYDEV_CAN0_RX7_CMD EQU 0x4000a180 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_ID +CYDEV_CAN0_RX7_ID EQU 0x4000a184 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_DH +CYDEV_CAN0_RX7_DH EQU 0x4000a188 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_DL +CYDEV_CAN0_RX7_DL EQU 0x4000a18c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_AMR +CYDEV_CAN0_RX7_AMR EQU 0x4000a190 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_ACR +CYDEV_CAN0_RX7_ACR EQU 0x4000a194 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_AMRD +CYDEV_CAN0_RX7_AMRD EQU 0x4000a198 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_ACRD +CYDEV_CAN0_RX7_ACRD EQU 0x4000a19c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_BASE +CYDEV_CAN0_RX8_BASE EQU 0x4000a1a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_SIZE +CYDEV_CAN0_RX8_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_CMD +CYDEV_CAN0_RX8_CMD EQU 0x4000a1a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_ID +CYDEV_CAN0_RX8_ID EQU 0x4000a1a4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_DH +CYDEV_CAN0_RX8_DH EQU 0x4000a1a8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_DL +CYDEV_CAN0_RX8_DL EQU 0x4000a1ac + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_AMR +CYDEV_CAN0_RX8_AMR EQU 0x4000a1b0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_ACR +CYDEV_CAN0_RX8_ACR EQU 0x4000a1b4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_AMRD +CYDEV_CAN0_RX8_AMRD EQU 0x4000a1b8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_ACRD +CYDEV_CAN0_RX8_ACRD EQU 0x4000a1bc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_BASE +CYDEV_CAN0_RX9_BASE EQU 0x4000a1c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_SIZE +CYDEV_CAN0_RX9_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_CMD +CYDEV_CAN0_RX9_CMD EQU 0x4000a1c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_ID +CYDEV_CAN0_RX9_ID EQU 0x4000a1c4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_DH +CYDEV_CAN0_RX9_DH EQU 0x4000a1c8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_DL +CYDEV_CAN0_RX9_DL EQU 0x4000a1cc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_AMR +CYDEV_CAN0_RX9_AMR EQU 0x4000a1d0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_ACR +CYDEV_CAN0_RX9_ACR EQU 0x4000a1d4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_AMRD +CYDEV_CAN0_RX9_AMRD EQU 0x4000a1d8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_ACRD +CYDEV_CAN0_RX9_ACRD EQU 0x4000a1dc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_BASE +CYDEV_CAN0_RX10_BASE EQU 0x4000a1e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_SIZE +CYDEV_CAN0_RX10_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_CMD +CYDEV_CAN0_RX10_CMD EQU 0x4000a1e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_ID +CYDEV_CAN0_RX10_ID EQU 0x4000a1e4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_DH +CYDEV_CAN0_RX10_DH EQU 0x4000a1e8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_DL +CYDEV_CAN0_RX10_DL EQU 0x4000a1ec + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_AMR +CYDEV_CAN0_RX10_AMR EQU 0x4000a1f0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_ACR +CYDEV_CAN0_RX10_ACR EQU 0x4000a1f4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_AMRD +CYDEV_CAN0_RX10_AMRD EQU 0x4000a1f8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_ACRD +CYDEV_CAN0_RX10_ACRD EQU 0x4000a1fc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_BASE +CYDEV_CAN0_RX11_BASE EQU 0x4000a200 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_SIZE +CYDEV_CAN0_RX11_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_CMD +CYDEV_CAN0_RX11_CMD EQU 0x4000a200 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_ID +CYDEV_CAN0_RX11_ID EQU 0x4000a204 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_DH +CYDEV_CAN0_RX11_DH EQU 0x4000a208 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_DL +CYDEV_CAN0_RX11_DL EQU 0x4000a20c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_AMR +CYDEV_CAN0_RX11_AMR EQU 0x4000a210 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_ACR +CYDEV_CAN0_RX11_ACR EQU 0x4000a214 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_AMRD +CYDEV_CAN0_RX11_AMRD EQU 0x4000a218 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_ACRD +CYDEV_CAN0_RX11_ACRD EQU 0x4000a21c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_BASE +CYDEV_CAN0_RX12_BASE EQU 0x4000a220 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_SIZE +CYDEV_CAN0_RX12_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_CMD +CYDEV_CAN0_RX12_CMD EQU 0x4000a220 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_ID +CYDEV_CAN0_RX12_ID EQU 0x4000a224 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_DH +CYDEV_CAN0_RX12_DH EQU 0x4000a228 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_DL +CYDEV_CAN0_RX12_DL EQU 0x4000a22c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_AMR +CYDEV_CAN0_RX12_AMR EQU 0x4000a230 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_ACR +CYDEV_CAN0_RX12_ACR EQU 0x4000a234 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_AMRD +CYDEV_CAN0_RX12_AMRD EQU 0x4000a238 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_ACRD +CYDEV_CAN0_RX12_ACRD EQU 0x4000a23c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_BASE +CYDEV_CAN0_RX13_BASE EQU 0x4000a240 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_SIZE +CYDEV_CAN0_RX13_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_CMD +CYDEV_CAN0_RX13_CMD EQU 0x4000a240 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_ID +CYDEV_CAN0_RX13_ID EQU 0x4000a244 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_DH +CYDEV_CAN0_RX13_DH EQU 0x4000a248 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_DL +CYDEV_CAN0_RX13_DL EQU 0x4000a24c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_AMR +CYDEV_CAN0_RX13_AMR EQU 0x4000a250 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_ACR +CYDEV_CAN0_RX13_ACR EQU 0x4000a254 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_AMRD +CYDEV_CAN0_RX13_AMRD EQU 0x4000a258 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_ACRD +CYDEV_CAN0_RX13_ACRD EQU 0x4000a25c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_BASE +CYDEV_CAN0_RX14_BASE EQU 0x4000a260 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_SIZE +CYDEV_CAN0_RX14_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_CMD +CYDEV_CAN0_RX14_CMD EQU 0x4000a260 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_ID +CYDEV_CAN0_RX14_ID EQU 0x4000a264 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_DH +CYDEV_CAN0_RX14_DH EQU 0x4000a268 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_DL +CYDEV_CAN0_RX14_DL EQU 0x4000a26c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_AMR +CYDEV_CAN0_RX14_AMR EQU 0x4000a270 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_ACR +CYDEV_CAN0_RX14_ACR EQU 0x4000a274 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_AMRD +CYDEV_CAN0_RX14_AMRD EQU 0x4000a278 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_ACRD +CYDEV_CAN0_RX14_ACRD EQU 0x4000a27c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_BASE +CYDEV_CAN0_RX15_BASE EQU 0x4000a280 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_SIZE +CYDEV_CAN0_RX15_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_CMD +CYDEV_CAN0_RX15_CMD EQU 0x4000a280 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_ID +CYDEV_CAN0_RX15_ID EQU 0x4000a284 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_DH +CYDEV_CAN0_RX15_DH EQU 0x4000a288 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_DL +CYDEV_CAN0_RX15_DL EQU 0x4000a28c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_AMR +CYDEV_CAN0_RX15_AMR EQU 0x4000a290 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_ACR +CYDEV_CAN0_RX15_ACR EQU 0x4000a294 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_AMRD +CYDEV_CAN0_RX15_AMRD EQU 0x4000a298 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_ACRD +CYDEV_CAN0_RX15_ACRD EQU 0x4000a29c + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_BASE +CYDEV_DFB0_BASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_SIZE +CYDEV_DFB0_SIZE EQU 0x000007b5 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_BASE +CYDEV_DFB0_DPA_SRAM_BASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_SIZE +CYDEV_DFB0_DPA_SRAM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_DATA_MBASE +CYDEV_DFB0_DPA_SRAM_DATA_MBASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_DATA_MSIZE +CYDEV_DFB0_DPA_SRAM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_BASE +CYDEV_DFB0_DPB_SRAM_BASE EQU 0x4000c200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_SIZE +CYDEV_DFB0_DPB_SRAM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_DATA_MBASE +CYDEV_DFB0_DPB_SRAM_DATA_MBASE EQU 0x4000c200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_DATA_MSIZE +CYDEV_DFB0_DPB_SRAM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_BASE +CYDEV_DFB0_CSA_SRAM_BASE EQU 0x4000c400 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_SIZE +CYDEV_DFB0_CSA_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_DATA_MBASE +CYDEV_DFB0_CSA_SRAM_DATA_MBASE EQU 0x4000c400 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_DATA_MSIZE +CYDEV_DFB0_CSA_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_BASE +CYDEV_DFB0_CSB_SRAM_BASE EQU 0x4000c500 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_SIZE +CYDEV_DFB0_CSB_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_DATA_MBASE +CYDEV_DFB0_CSB_SRAM_DATA_MBASE EQU 0x4000c500 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_DATA_MSIZE +CYDEV_DFB0_CSB_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_BASE +CYDEV_DFB0_FSM_SRAM_BASE EQU 0x4000c600 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_SIZE +CYDEV_DFB0_FSM_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_DATA_MBASE +CYDEV_DFB0_FSM_SRAM_DATA_MBASE EQU 0x4000c600 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_DATA_MSIZE +CYDEV_DFB0_FSM_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_BASE +CYDEV_DFB0_ACU_SRAM_BASE EQU 0x4000c700 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_SIZE +CYDEV_DFB0_ACU_SRAM_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_DATA_MBASE +CYDEV_DFB0_ACU_SRAM_DATA_MBASE EQU 0x4000c700 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_DATA_MSIZE +CYDEV_DFB0_ACU_SRAM_DATA_MSIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CR +CYDEV_DFB0_CR EQU 0x4000c780 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_SR +CYDEV_DFB0_SR EQU 0x4000c784 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_RAM_EN +CYDEV_DFB0_RAM_EN EQU 0x4000c788 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_RAM_DIR +CYDEV_DFB0_RAM_DIR EQU 0x4000c78c + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_SEMA +CYDEV_DFB0_SEMA EQU 0x4000c790 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DSI_CTRL +CYDEV_DFB0_DSI_CTRL EQU 0x4000c794 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_INT_CTRL +CYDEV_DFB0_INT_CTRL EQU 0x4000c798 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DMA_CTRL +CYDEV_DFB0_DMA_CTRL EQU 0x4000c79c + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEA +CYDEV_DFB0_STAGEA EQU 0x4000c7a0 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEAM +CYDEV_DFB0_STAGEAM EQU 0x4000c7a1 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEAH +CYDEV_DFB0_STAGEAH EQU 0x4000c7a2 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEB +CYDEV_DFB0_STAGEB EQU 0x4000c7a4 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEBM +CYDEV_DFB0_STAGEBM EQU 0x4000c7a5 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEBH +CYDEV_DFB0_STAGEBH EQU 0x4000c7a6 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDA +CYDEV_DFB0_HOLDA EQU 0x4000c7a8 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDAM +CYDEV_DFB0_HOLDAM EQU 0x4000c7a9 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDAH +CYDEV_DFB0_HOLDAH EQU 0x4000c7aa + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDAS +CYDEV_DFB0_HOLDAS EQU 0x4000c7ab + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDB +CYDEV_DFB0_HOLDB EQU 0x4000c7ac + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDBM +CYDEV_DFB0_HOLDBM EQU 0x4000c7ad + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDBH +CYDEV_DFB0_HOLDBH EQU 0x4000c7ae + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDBS +CYDEV_DFB0_HOLDBS EQU 0x4000c7af + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_COHER +CYDEV_DFB0_COHER EQU 0x4000c7b0 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DALIGN +CYDEV_DFB0_DALIGN EQU 0x4000c7b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BASE +CYDEV_UCFG_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_SIZE +CYDEV_UCFG_SIZE EQU 0x00005040 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_BASE +CYDEV_UCFG_B0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_SIZE +CYDEV_UCFG_B0_SIZE EQU 0x00000fef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_BASE +CYDEV_UCFG_B0_P0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_SIZE +CYDEV_UCFG_B0_P0_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_BASE +CYDEV_UCFG_B0_P0_U0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_SIZE +CYDEV_UCFG_B0_P0_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT0 +CYDEV_UCFG_B0_P0_U0_PLD_IT0 EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT1 +CYDEV_UCFG_B0_P0_U0_PLD_IT1 EQU 0x40010004 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT2 +CYDEV_UCFG_B0_P0_U0_PLD_IT2 EQU 0x40010008 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT3 +CYDEV_UCFG_B0_P0_U0_PLD_IT3 EQU 0x4001000c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT4 +CYDEV_UCFG_B0_P0_U0_PLD_IT4 EQU 0x40010010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT5 +CYDEV_UCFG_B0_P0_U0_PLD_IT5 EQU 0x40010014 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT6 +CYDEV_UCFG_B0_P0_U0_PLD_IT6 EQU 0x40010018 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT7 +CYDEV_UCFG_B0_P0_U0_PLD_IT7 EQU 0x4001001c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT8 +CYDEV_UCFG_B0_P0_U0_PLD_IT8 EQU 0x40010020 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT9 +CYDEV_UCFG_B0_P0_U0_PLD_IT9 EQU 0x40010024 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT10 +CYDEV_UCFG_B0_P0_U0_PLD_IT10 EQU 0x40010028 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT11 +CYDEV_UCFG_B0_P0_U0_PLD_IT11 EQU 0x4001002c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_ORT0 +CYDEV_UCFG_B0_P0_U0_PLD_ORT0 EQU 0x40010030 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_ORT1 +CYDEV_UCFG_B0_P0_U0_PLD_ORT1 EQU 0x40010032 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_ORT2 +CYDEV_UCFG_B0_P0_U0_PLD_ORT2 EQU 0x40010034 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_ORT3 +CYDEV_UCFG_B0_P0_U0_PLD_ORT3 EQU 0x40010036 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST EQU 0x40010038 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB EQU 0x4001003a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET EQU 0x4001003c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS EQU 0x4001003e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG0 +CYDEV_UCFG_B0_P0_U0_CFG0 EQU 0x40010040 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG1 +CYDEV_UCFG_B0_P0_U0_CFG1 EQU 0x40010041 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG2 +CYDEV_UCFG_B0_P0_U0_CFG2 EQU 0x40010042 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG3 +CYDEV_UCFG_B0_P0_U0_CFG3 EQU 0x40010043 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG4 +CYDEV_UCFG_B0_P0_U0_CFG4 EQU 0x40010044 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG5 +CYDEV_UCFG_B0_P0_U0_CFG5 EQU 0x40010045 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG6 +CYDEV_UCFG_B0_P0_U0_CFG6 EQU 0x40010046 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG7 +CYDEV_UCFG_B0_P0_U0_CFG7 EQU 0x40010047 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG8 +CYDEV_UCFG_B0_P0_U0_CFG8 EQU 0x40010048 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG9 +CYDEV_UCFG_B0_P0_U0_CFG9 EQU 0x40010049 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG10 +CYDEV_UCFG_B0_P0_U0_CFG10 EQU 0x4001004a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG11 +CYDEV_UCFG_B0_P0_U0_CFG11 EQU 0x4001004b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG12 +CYDEV_UCFG_B0_P0_U0_CFG12 EQU 0x4001004c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG13 +CYDEV_UCFG_B0_P0_U0_CFG13 EQU 0x4001004d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG14 +CYDEV_UCFG_B0_P0_U0_CFG14 EQU 0x4001004e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG15 +CYDEV_UCFG_B0_P0_U0_CFG15 EQU 0x4001004f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG16 +CYDEV_UCFG_B0_P0_U0_CFG16 EQU 0x40010050 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG17 +CYDEV_UCFG_B0_P0_U0_CFG17 EQU 0x40010051 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG18 +CYDEV_UCFG_B0_P0_U0_CFG18 EQU 0x40010052 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG19 +CYDEV_UCFG_B0_P0_U0_CFG19 EQU 0x40010053 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG20 +CYDEV_UCFG_B0_P0_U0_CFG20 EQU 0x40010054 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG21 +CYDEV_UCFG_B0_P0_U0_CFG21 EQU 0x40010055 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG22 +CYDEV_UCFG_B0_P0_U0_CFG22 EQU 0x40010056 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG23 +CYDEV_UCFG_B0_P0_U0_CFG23 EQU 0x40010057 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG24 +CYDEV_UCFG_B0_P0_U0_CFG24 EQU 0x40010058 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG25 +CYDEV_UCFG_B0_P0_U0_CFG25 EQU 0x40010059 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG26 +CYDEV_UCFG_B0_P0_U0_CFG26 EQU 0x4001005a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG27 +CYDEV_UCFG_B0_P0_U0_CFG27 EQU 0x4001005b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG28 +CYDEV_UCFG_B0_P0_U0_CFG28 EQU 0x4001005c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG29 +CYDEV_UCFG_B0_P0_U0_CFG29 EQU 0x4001005d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG30 +CYDEV_UCFG_B0_P0_U0_CFG30 EQU 0x4001005e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG31 +CYDEV_UCFG_B0_P0_U0_CFG31 EQU 0x4001005f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG0 +CYDEV_UCFG_B0_P0_U0_DCFG0 EQU 0x40010060 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG1 +CYDEV_UCFG_B0_P0_U0_DCFG1 EQU 0x40010062 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG2 +CYDEV_UCFG_B0_P0_U0_DCFG2 EQU 0x40010064 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG3 +CYDEV_UCFG_B0_P0_U0_DCFG3 EQU 0x40010066 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG4 +CYDEV_UCFG_B0_P0_U0_DCFG4 EQU 0x40010068 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG5 +CYDEV_UCFG_B0_P0_U0_DCFG5 EQU 0x4001006a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG6 +CYDEV_UCFG_B0_P0_U0_DCFG6 EQU 0x4001006c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG7 +CYDEV_UCFG_B0_P0_U0_DCFG7 EQU 0x4001006e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_BASE +CYDEV_UCFG_B0_P0_U1_BASE EQU 0x40010080 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_SIZE +CYDEV_UCFG_B0_P0_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT0 +CYDEV_UCFG_B0_P0_U1_PLD_IT0 EQU 0x40010080 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT1 +CYDEV_UCFG_B0_P0_U1_PLD_IT1 EQU 0x40010084 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT2 +CYDEV_UCFG_B0_P0_U1_PLD_IT2 EQU 0x40010088 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT3 +CYDEV_UCFG_B0_P0_U1_PLD_IT3 EQU 0x4001008c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT4 +CYDEV_UCFG_B0_P0_U1_PLD_IT4 EQU 0x40010090 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT5 +CYDEV_UCFG_B0_P0_U1_PLD_IT5 EQU 0x40010094 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT6 +CYDEV_UCFG_B0_P0_U1_PLD_IT6 EQU 0x40010098 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT7 +CYDEV_UCFG_B0_P0_U1_PLD_IT7 EQU 0x4001009c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT8 +CYDEV_UCFG_B0_P0_U1_PLD_IT8 EQU 0x400100a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT9 +CYDEV_UCFG_B0_P0_U1_PLD_IT9 EQU 0x400100a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT10 +CYDEV_UCFG_B0_P0_U1_PLD_IT10 EQU 0x400100a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT11 +CYDEV_UCFG_B0_P0_U1_PLD_IT11 EQU 0x400100ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_ORT0 +CYDEV_UCFG_B0_P0_U1_PLD_ORT0 EQU 0x400100b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_ORT1 +CYDEV_UCFG_B0_P0_U1_PLD_ORT1 EQU 0x400100b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_ORT2 +CYDEV_UCFG_B0_P0_U1_PLD_ORT2 EQU 0x400100b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_ORT3 +CYDEV_UCFG_B0_P0_U1_PLD_ORT3 EQU 0x400100b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST EQU 0x400100b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB EQU 0x400100ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET EQU 0x400100bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS EQU 0x400100be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG0 +CYDEV_UCFG_B0_P0_U1_CFG0 EQU 0x400100c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG1 +CYDEV_UCFG_B0_P0_U1_CFG1 EQU 0x400100c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG2 +CYDEV_UCFG_B0_P0_U1_CFG2 EQU 0x400100c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG3 +CYDEV_UCFG_B0_P0_U1_CFG3 EQU 0x400100c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG4 +CYDEV_UCFG_B0_P0_U1_CFG4 EQU 0x400100c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG5 +CYDEV_UCFG_B0_P0_U1_CFG5 EQU 0x400100c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG6 +CYDEV_UCFG_B0_P0_U1_CFG6 EQU 0x400100c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG7 +CYDEV_UCFG_B0_P0_U1_CFG7 EQU 0x400100c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG8 +CYDEV_UCFG_B0_P0_U1_CFG8 EQU 0x400100c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG9 +CYDEV_UCFG_B0_P0_U1_CFG9 EQU 0x400100c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG10 +CYDEV_UCFG_B0_P0_U1_CFG10 EQU 0x400100ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG11 +CYDEV_UCFG_B0_P0_U1_CFG11 EQU 0x400100cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG12 +CYDEV_UCFG_B0_P0_U1_CFG12 EQU 0x400100cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG13 +CYDEV_UCFG_B0_P0_U1_CFG13 EQU 0x400100cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG14 +CYDEV_UCFG_B0_P0_U1_CFG14 EQU 0x400100ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG15 +CYDEV_UCFG_B0_P0_U1_CFG15 EQU 0x400100cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG16 +CYDEV_UCFG_B0_P0_U1_CFG16 EQU 0x400100d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG17 +CYDEV_UCFG_B0_P0_U1_CFG17 EQU 0x400100d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG18 +CYDEV_UCFG_B0_P0_U1_CFG18 EQU 0x400100d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG19 +CYDEV_UCFG_B0_P0_U1_CFG19 EQU 0x400100d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG20 +CYDEV_UCFG_B0_P0_U1_CFG20 EQU 0x400100d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG21 +CYDEV_UCFG_B0_P0_U1_CFG21 EQU 0x400100d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG22 +CYDEV_UCFG_B0_P0_U1_CFG22 EQU 0x400100d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG23 +CYDEV_UCFG_B0_P0_U1_CFG23 EQU 0x400100d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG24 +CYDEV_UCFG_B0_P0_U1_CFG24 EQU 0x400100d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG25 +CYDEV_UCFG_B0_P0_U1_CFG25 EQU 0x400100d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG26 +CYDEV_UCFG_B0_P0_U1_CFG26 EQU 0x400100da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG27 +CYDEV_UCFG_B0_P0_U1_CFG27 EQU 0x400100db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG28 +CYDEV_UCFG_B0_P0_U1_CFG28 EQU 0x400100dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG29 +CYDEV_UCFG_B0_P0_U1_CFG29 EQU 0x400100dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG30 +CYDEV_UCFG_B0_P0_U1_CFG30 EQU 0x400100de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG31 +CYDEV_UCFG_B0_P0_U1_CFG31 EQU 0x400100df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG0 +CYDEV_UCFG_B0_P0_U1_DCFG0 EQU 0x400100e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG1 +CYDEV_UCFG_B0_P0_U1_DCFG1 EQU 0x400100e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG2 +CYDEV_UCFG_B0_P0_U1_DCFG2 EQU 0x400100e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG3 +CYDEV_UCFG_B0_P0_U1_DCFG3 EQU 0x400100e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG4 +CYDEV_UCFG_B0_P0_U1_DCFG4 EQU 0x400100e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG5 +CYDEV_UCFG_B0_P0_U1_DCFG5 EQU 0x400100ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG6 +CYDEV_UCFG_B0_P0_U1_DCFG6 EQU 0x400100ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG7 +CYDEV_UCFG_B0_P0_U1_DCFG7 EQU 0x400100ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_ROUTE_BASE +CYDEV_UCFG_B0_P0_ROUTE_BASE EQU 0x40010100 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_ROUTE_SIZE +CYDEV_UCFG_B0_P0_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_BASE +CYDEV_UCFG_B0_P1_BASE EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_SIZE +CYDEV_UCFG_B0_P1_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_BASE +CYDEV_UCFG_B0_P1_U0_BASE EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_SIZE +CYDEV_UCFG_B0_P1_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT0 +CYDEV_UCFG_B0_P1_U0_PLD_IT0 EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT1 +CYDEV_UCFG_B0_P1_U0_PLD_IT1 EQU 0x40010204 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT2 +CYDEV_UCFG_B0_P1_U0_PLD_IT2 EQU 0x40010208 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT3 +CYDEV_UCFG_B0_P1_U0_PLD_IT3 EQU 0x4001020c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT4 +CYDEV_UCFG_B0_P1_U0_PLD_IT4 EQU 0x40010210 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT5 +CYDEV_UCFG_B0_P1_U0_PLD_IT5 EQU 0x40010214 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT6 +CYDEV_UCFG_B0_P1_U0_PLD_IT6 EQU 0x40010218 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT7 +CYDEV_UCFG_B0_P1_U0_PLD_IT7 EQU 0x4001021c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT8 +CYDEV_UCFG_B0_P1_U0_PLD_IT8 EQU 0x40010220 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT9 +CYDEV_UCFG_B0_P1_U0_PLD_IT9 EQU 0x40010224 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT10 +CYDEV_UCFG_B0_P1_U0_PLD_IT10 EQU 0x40010228 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT11 +CYDEV_UCFG_B0_P1_U0_PLD_IT11 EQU 0x4001022c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_ORT0 +CYDEV_UCFG_B0_P1_U0_PLD_ORT0 EQU 0x40010230 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_ORT1 +CYDEV_UCFG_B0_P1_U0_PLD_ORT1 EQU 0x40010232 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_ORT2 +CYDEV_UCFG_B0_P1_U0_PLD_ORT2 EQU 0x40010234 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_ORT3 +CYDEV_UCFG_B0_P1_U0_PLD_ORT3 EQU 0x40010236 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST EQU 0x40010238 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB EQU 0x4001023a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET EQU 0x4001023c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS EQU 0x4001023e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG0 +CYDEV_UCFG_B0_P1_U0_CFG0 EQU 0x40010240 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG1 +CYDEV_UCFG_B0_P1_U0_CFG1 EQU 0x40010241 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG2 +CYDEV_UCFG_B0_P1_U0_CFG2 EQU 0x40010242 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG3 +CYDEV_UCFG_B0_P1_U0_CFG3 EQU 0x40010243 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG4 +CYDEV_UCFG_B0_P1_U0_CFG4 EQU 0x40010244 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG5 +CYDEV_UCFG_B0_P1_U0_CFG5 EQU 0x40010245 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG6 +CYDEV_UCFG_B0_P1_U0_CFG6 EQU 0x40010246 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG7 +CYDEV_UCFG_B0_P1_U0_CFG7 EQU 0x40010247 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG8 +CYDEV_UCFG_B0_P1_U0_CFG8 EQU 0x40010248 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG9 +CYDEV_UCFG_B0_P1_U0_CFG9 EQU 0x40010249 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG10 +CYDEV_UCFG_B0_P1_U0_CFG10 EQU 0x4001024a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG11 +CYDEV_UCFG_B0_P1_U0_CFG11 EQU 0x4001024b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG12 +CYDEV_UCFG_B0_P1_U0_CFG12 EQU 0x4001024c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG13 +CYDEV_UCFG_B0_P1_U0_CFG13 EQU 0x4001024d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG14 +CYDEV_UCFG_B0_P1_U0_CFG14 EQU 0x4001024e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG15 +CYDEV_UCFG_B0_P1_U0_CFG15 EQU 0x4001024f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG16 +CYDEV_UCFG_B0_P1_U0_CFG16 EQU 0x40010250 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG17 +CYDEV_UCFG_B0_P1_U0_CFG17 EQU 0x40010251 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG18 +CYDEV_UCFG_B0_P1_U0_CFG18 EQU 0x40010252 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG19 +CYDEV_UCFG_B0_P1_U0_CFG19 EQU 0x40010253 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG20 +CYDEV_UCFG_B0_P1_U0_CFG20 EQU 0x40010254 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG21 +CYDEV_UCFG_B0_P1_U0_CFG21 EQU 0x40010255 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG22 +CYDEV_UCFG_B0_P1_U0_CFG22 EQU 0x40010256 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG23 +CYDEV_UCFG_B0_P1_U0_CFG23 EQU 0x40010257 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG24 +CYDEV_UCFG_B0_P1_U0_CFG24 EQU 0x40010258 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG25 +CYDEV_UCFG_B0_P1_U0_CFG25 EQU 0x40010259 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG26 +CYDEV_UCFG_B0_P1_U0_CFG26 EQU 0x4001025a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG27 +CYDEV_UCFG_B0_P1_U0_CFG27 EQU 0x4001025b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG28 +CYDEV_UCFG_B0_P1_U0_CFG28 EQU 0x4001025c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG29 +CYDEV_UCFG_B0_P1_U0_CFG29 EQU 0x4001025d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG30 +CYDEV_UCFG_B0_P1_U0_CFG30 EQU 0x4001025e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG31 +CYDEV_UCFG_B0_P1_U0_CFG31 EQU 0x4001025f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG0 +CYDEV_UCFG_B0_P1_U0_DCFG0 EQU 0x40010260 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG1 +CYDEV_UCFG_B0_P1_U0_DCFG1 EQU 0x40010262 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG2 +CYDEV_UCFG_B0_P1_U0_DCFG2 EQU 0x40010264 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG3 +CYDEV_UCFG_B0_P1_U0_DCFG3 EQU 0x40010266 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG4 +CYDEV_UCFG_B0_P1_U0_DCFG4 EQU 0x40010268 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG5 +CYDEV_UCFG_B0_P1_U0_DCFG5 EQU 0x4001026a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG6 +CYDEV_UCFG_B0_P1_U0_DCFG6 EQU 0x4001026c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG7 +CYDEV_UCFG_B0_P1_U0_DCFG7 EQU 0x4001026e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_BASE +CYDEV_UCFG_B0_P1_U1_BASE EQU 0x40010280 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_SIZE +CYDEV_UCFG_B0_P1_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT0 +CYDEV_UCFG_B0_P1_U1_PLD_IT0 EQU 0x40010280 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT1 +CYDEV_UCFG_B0_P1_U1_PLD_IT1 EQU 0x40010284 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT2 +CYDEV_UCFG_B0_P1_U1_PLD_IT2 EQU 0x40010288 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT3 +CYDEV_UCFG_B0_P1_U1_PLD_IT3 EQU 0x4001028c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT4 +CYDEV_UCFG_B0_P1_U1_PLD_IT4 EQU 0x40010290 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT5 +CYDEV_UCFG_B0_P1_U1_PLD_IT5 EQU 0x40010294 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT6 +CYDEV_UCFG_B0_P1_U1_PLD_IT6 EQU 0x40010298 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT7 +CYDEV_UCFG_B0_P1_U1_PLD_IT7 EQU 0x4001029c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT8 +CYDEV_UCFG_B0_P1_U1_PLD_IT8 EQU 0x400102a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT9 +CYDEV_UCFG_B0_P1_U1_PLD_IT9 EQU 0x400102a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT10 +CYDEV_UCFG_B0_P1_U1_PLD_IT10 EQU 0x400102a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT11 +CYDEV_UCFG_B0_P1_U1_PLD_IT11 EQU 0x400102ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_ORT0 +CYDEV_UCFG_B0_P1_U1_PLD_ORT0 EQU 0x400102b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_ORT1 +CYDEV_UCFG_B0_P1_U1_PLD_ORT1 EQU 0x400102b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_ORT2 +CYDEV_UCFG_B0_P1_U1_PLD_ORT2 EQU 0x400102b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_ORT3 +CYDEV_UCFG_B0_P1_U1_PLD_ORT3 EQU 0x400102b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST EQU 0x400102b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB EQU 0x400102ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET EQU 0x400102bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS EQU 0x400102be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG0 +CYDEV_UCFG_B0_P1_U1_CFG0 EQU 0x400102c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG1 +CYDEV_UCFG_B0_P1_U1_CFG1 EQU 0x400102c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG2 +CYDEV_UCFG_B0_P1_U1_CFG2 EQU 0x400102c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG3 +CYDEV_UCFG_B0_P1_U1_CFG3 EQU 0x400102c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG4 +CYDEV_UCFG_B0_P1_U1_CFG4 EQU 0x400102c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG5 +CYDEV_UCFG_B0_P1_U1_CFG5 EQU 0x400102c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG6 +CYDEV_UCFG_B0_P1_U1_CFG6 EQU 0x400102c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG7 +CYDEV_UCFG_B0_P1_U1_CFG7 EQU 0x400102c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG8 +CYDEV_UCFG_B0_P1_U1_CFG8 EQU 0x400102c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG9 +CYDEV_UCFG_B0_P1_U1_CFG9 EQU 0x400102c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG10 +CYDEV_UCFG_B0_P1_U1_CFG10 EQU 0x400102ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG11 +CYDEV_UCFG_B0_P1_U1_CFG11 EQU 0x400102cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG12 +CYDEV_UCFG_B0_P1_U1_CFG12 EQU 0x400102cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG13 +CYDEV_UCFG_B0_P1_U1_CFG13 EQU 0x400102cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG14 +CYDEV_UCFG_B0_P1_U1_CFG14 EQU 0x400102ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG15 +CYDEV_UCFG_B0_P1_U1_CFG15 EQU 0x400102cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG16 +CYDEV_UCFG_B0_P1_U1_CFG16 EQU 0x400102d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG17 +CYDEV_UCFG_B0_P1_U1_CFG17 EQU 0x400102d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG18 +CYDEV_UCFG_B0_P1_U1_CFG18 EQU 0x400102d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG19 +CYDEV_UCFG_B0_P1_U1_CFG19 EQU 0x400102d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG20 +CYDEV_UCFG_B0_P1_U1_CFG20 EQU 0x400102d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG21 +CYDEV_UCFG_B0_P1_U1_CFG21 EQU 0x400102d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG22 +CYDEV_UCFG_B0_P1_U1_CFG22 EQU 0x400102d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG23 +CYDEV_UCFG_B0_P1_U1_CFG23 EQU 0x400102d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG24 +CYDEV_UCFG_B0_P1_U1_CFG24 EQU 0x400102d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG25 +CYDEV_UCFG_B0_P1_U1_CFG25 EQU 0x400102d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG26 +CYDEV_UCFG_B0_P1_U1_CFG26 EQU 0x400102da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG27 +CYDEV_UCFG_B0_P1_U1_CFG27 EQU 0x400102db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG28 +CYDEV_UCFG_B0_P1_U1_CFG28 EQU 0x400102dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG29 +CYDEV_UCFG_B0_P1_U1_CFG29 EQU 0x400102dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG30 +CYDEV_UCFG_B0_P1_U1_CFG30 EQU 0x400102de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG31 +CYDEV_UCFG_B0_P1_U1_CFG31 EQU 0x400102df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG0 +CYDEV_UCFG_B0_P1_U1_DCFG0 EQU 0x400102e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG1 +CYDEV_UCFG_B0_P1_U1_DCFG1 EQU 0x400102e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG2 +CYDEV_UCFG_B0_P1_U1_DCFG2 EQU 0x400102e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG3 +CYDEV_UCFG_B0_P1_U1_DCFG3 EQU 0x400102e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG4 +CYDEV_UCFG_B0_P1_U1_DCFG4 EQU 0x400102e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG5 +CYDEV_UCFG_B0_P1_U1_DCFG5 EQU 0x400102ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG6 +CYDEV_UCFG_B0_P1_U1_DCFG6 EQU 0x400102ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG7 +CYDEV_UCFG_B0_P1_U1_DCFG7 EQU 0x400102ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_ROUTE_BASE +CYDEV_UCFG_B0_P1_ROUTE_BASE EQU 0x40010300 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_ROUTE_SIZE +CYDEV_UCFG_B0_P1_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_BASE +CYDEV_UCFG_B0_P2_BASE EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_SIZE +CYDEV_UCFG_B0_P2_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_BASE +CYDEV_UCFG_B0_P2_U0_BASE EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_SIZE +CYDEV_UCFG_B0_P2_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT0 +CYDEV_UCFG_B0_P2_U0_PLD_IT0 EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT1 +CYDEV_UCFG_B0_P2_U0_PLD_IT1 EQU 0x40010404 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT2 +CYDEV_UCFG_B0_P2_U0_PLD_IT2 EQU 0x40010408 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT3 +CYDEV_UCFG_B0_P2_U0_PLD_IT3 EQU 0x4001040c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT4 +CYDEV_UCFG_B0_P2_U0_PLD_IT4 EQU 0x40010410 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT5 +CYDEV_UCFG_B0_P2_U0_PLD_IT5 EQU 0x40010414 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT6 +CYDEV_UCFG_B0_P2_U0_PLD_IT6 EQU 0x40010418 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT7 +CYDEV_UCFG_B0_P2_U0_PLD_IT7 EQU 0x4001041c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT8 +CYDEV_UCFG_B0_P2_U0_PLD_IT8 EQU 0x40010420 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT9 +CYDEV_UCFG_B0_P2_U0_PLD_IT9 EQU 0x40010424 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT10 +CYDEV_UCFG_B0_P2_U0_PLD_IT10 EQU 0x40010428 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT11 +CYDEV_UCFG_B0_P2_U0_PLD_IT11 EQU 0x4001042c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_ORT0 +CYDEV_UCFG_B0_P2_U0_PLD_ORT0 EQU 0x40010430 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_ORT1 +CYDEV_UCFG_B0_P2_U0_PLD_ORT1 EQU 0x40010432 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_ORT2 +CYDEV_UCFG_B0_P2_U0_PLD_ORT2 EQU 0x40010434 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_ORT3 +CYDEV_UCFG_B0_P2_U0_PLD_ORT3 EQU 0x40010436 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST EQU 0x40010438 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB EQU 0x4001043a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET EQU 0x4001043c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS EQU 0x4001043e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG0 +CYDEV_UCFG_B0_P2_U0_CFG0 EQU 0x40010440 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG1 +CYDEV_UCFG_B0_P2_U0_CFG1 EQU 0x40010441 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG2 +CYDEV_UCFG_B0_P2_U0_CFG2 EQU 0x40010442 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG3 +CYDEV_UCFG_B0_P2_U0_CFG3 EQU 0x40010443 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG4 +CYDEV_UCFG_B0_P2_U0_CFG4 EQU 0x40010444 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG5 +CYDEV_UCFG_B0_P2_U0_CFG5 EQU 0x40010445 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG6 +CYDEV_UCFG_B0_P2_U0_CFG6 EQU 0x40010446 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG7 +CYDEV_UCFG_B0_P2_U0_CFG7 EQU 0x40010447 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG8 +CYDEV_UCFG_B0_P2_U0_CFG8 EQU 0x40010448 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG9 +CYDEV_UCFG_B0_P2_U0_CFG9 EQU 0x40010449 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG10 +CYDEV_UCFG_B0_P2_U0_CFG10 EQU 0x4001044a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG11 +CYDEV_UCFG_B0_P2_U0_CFG11 EQU 0x4001044b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG12 +CYDEV_UCFG_B0_P2_U0_CFG12 EQU 0x4001044c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG13 +CYDEV_UCFG_B0_P2_U0_CFG13 EQU 0x4001044d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG14 +CYDEV_UCFG_B0_P2_U0_CFG14 EQU 0x4001044e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG15 +CYDEV_UCFG_B0_P2_U0_CFG15 EQU 0x4001044f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG16 +CYDEV_UCFG_B0_P2_U0_CFG16 EQU 0x40010450 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG17 +CYDEV_UCFG_B0_P2_U0_CFG17 EQU 0x40010451 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG18 +CYDEV_UCFG_B0_P2_U0_CFG18 EQU 0x40010452 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG19 +CYDEV_UCFG_B0_P2_U0_CFG19 EQU 0x40010453 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG20 +CYDEV_UCFG_B0_P2_U0_CFG20 EQU 0x40010454 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG21 +CYDEV_UCFG_B0_P2_U0_CFG21 EQU 0x40010455 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG22 +CYDEV_UCFG_B0_P2_U0_CFG22 EQU 0x40010456 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG23 +CYDEV_UCFG_B0_P2_U0_CFG23 EQU 0x40010457 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG24 +CYDEV_UCFG_B0_P2_U0_CFG24 EQU 0x40010458 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG25 +CYDEV_UCFG_B0_P2_U0_CFG25 EQU 0x40010459 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG26 +CYDEV_UCFG_B0_P2_U0_CFG26 EQU 0x4001045a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG27 +CYDEV_UCFG_B0_P2_U0_CFG27 EQU 0x4001045b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG28 +CYDEV_UCFG_B0_P2_U0_CFG28 EQU 0x4001045c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG29 +CYDEV_UCFG_B0_P2_U0_CFG29 EQU 0x4001045d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG30 +CYDEV_UCFG_B0_P2_U0_CFG30 EQU 0x4001045e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG31 +CYDEV_UCFG_B0_P2_U0_CFG31 EQU 0x4001045f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG0 +CYDEV_UCFG_B0_P2_U0_DCFG0 EQU 0x40010460 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG1 +CYDEV_UCFG_B0_P2_U0_DCFG1 EQU 0x40010462 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG2 +CYDEV_UCFG_B0_P2_U0_DCFG2 EQU 0x40010464 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG3 +CYDEV_UCFG_B0_P2_U0_DCFG3 EQU 0x40010466 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG4 +CYDEV_UCFG_B0_P2_U0_DCFG4 EQU 0x40010468 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG5 +CYDEV_UCFG_B0_P2_U0_DCFG5 EQU 0x4001046a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG6 +CYDEV_UCFG_B0_P2_U0_DCFG6 EQU 0x4001046c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG7 +CYDEV_UCFG_B0_P2_U0_DCFG7 EQU 0x4001046e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_BASE +CYDEV_UCFG_B0_P2_U1_BASE EQU 0x40010480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_SIZE +CYDEV_UCFG_B0_P2_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT0 +CYDEV_UCFG_B0_P2_U1_PLD_IT0 EQU 0x40010480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT1 +CYDEV_UCFG_B0_P2_U1_PLD_IT1 EQU 0x40010484 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT2 +CYDEV_UCFG_B0_P2_U1_PLD_IT2 EQU 0x40010488 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT3 +CYDEV_UCFG_B0_P2_U1_PLD_IT3 EQU 0x4001048c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT4 +CYDEV_UCFG_B0_P2_U1_PLD_IT4 EQU 0x40010490 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT5 +CYDEV_UCFG_B0_P2_U1_PLD_IT5 EQU 0x40010494 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT6 +CYDEV_UCFG_B0_P2_U1_PLD_IT6 EQU 0x40010498 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT7 +CYDEV_UCFG_B0_P2_U1_PLD_IT7 EQU 0x4001049c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT8 +CYDEV_UCFG_B0_P2_U1_PLD_IT8 EQU 0x400104a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT9 +CYDEV_UCFG_B0_P2_U1_PLD_IT9 EQU 0x400104a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT10 +CYDEV_UCFG_B0_P2_U1_PLD_IT10 EQU 0x400104a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT11 +CYDEV_UCFG_B0_P2_U1_PLD_IT11 EQU 0x400104ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_ORT0 +CYDEV_UCFG_B0_P2_U1_PLD_ORT0 EQU 0x400104b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_ORT1 +CYDEV_UCFG_B0_P2_U1_PLD_ORT1 EQU 0x400104b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_ORT2 +CYDEV_UCFG_B0_P2_U1_PLD_ORT2 EQU 0x400104b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_ORT3 +CYDEV_UCFG_B0_P2_U1_PLD_ORT3 EQU 0x400104b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST EQU 0x400104b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB EQU 0x400104ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET EQU 0x400104bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS EQU 0x400104be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG0 +CYDEV_UCFG_B0_P2_U1_CFG0 EQU 0x400104c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG1 +CYDEV_UCFG_B0_P2_U1_CFG1 EQU 0x400104c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG2 +CYDEV_UCFG_B0_P2_U1_CFG2 EQU 0x400104c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG3 +CYDEV_UCFG_B0_P2_U1_CFG3 EQU 0x400104c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG4 +CYDEV_UCFG_B0_P2_U1_CFG4 EQU 0x400104c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG5 +CYDEV_UCFG_B0_P2_U1_CFG5 EQU 0x400104c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG6 +CYDEV_UCFG_B0_P2_U1_CFG6 EQU 0x400104c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG7 +CYDEV_UCFG_B0_P2_U1_CFG7 EQU 0x400104c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG8 +CYDEV_UCFG_B0_P2_U1_CFG8 EQU 0x400104c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG9 +CYDEV_UCFG_B0_P2_U1_CFG9 EQU 0x400104c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG10 +CYDEV_UCFG_B0_P2_U1_CFG10 EQU 0x400104ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG11 +CYDEV_UCFG_B0_P2_U1_CFG11 EQU 0x400104cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG12 +CYDEV_UCFG_B0_P2_U1_CFG12 EQU 0x400104cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG13 +CYDEV_UCFG_B0_P2_U1_CFG13 EQU 0x400104cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG14 +CYDEV_UCFG_B0_P2_U1_CFG14 EQU 0x400104ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG15 +CYDEV_UCFG_B0_P2_U1_CFG15 EQU 0x400104cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG16 +CYDEV_UCFG_B0_P2_U1_CFG16 EQU 0x400104d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG17 +CYDEV_UCFG_B0_P2_U1_CFG17 EQU 0x400104d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG18 +CYDEV_UCFG_B0_P2_U1_CFG18 EQU 0x400104d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG19 +CYDEV_UCFG_B0_P2_U1_CFG19 EQU 0x400104d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG20 +CYDEV_UCFG_B0_P2_U1_CFG20 EQU 0x400104d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG21 +CYDEV_UCFG_B0_P2_U1_CFG21 EQU 0x400104d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG22 +CYDEV_UCFG_B0_P2_U1_CFG22 EQU 0x400104d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG23 +CYDEV_UCFG_B0_P2_U1_CFG23 EQU 0x400104d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG24 +CYDEV_UCFG_B0_P2_U1_CFG24 EQU 0x400104d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG25 +CYDEV_UCFG_B0_P2_U1_CFG25 EQU 0x400104d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG26 +CYDEV_UCFG_B0_P2_U1_CFG26 EQU 0x400104da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG27 +CYDEV_UCFG_B0_P2_U1_CFG27 EQU 0x400104db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG28 +CYDEV_UCFG_B0_P2_U1_CFG28 EQU 0x400104dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG29 +CYDEV_UCFG_B0_P2_U1_CFG29 EQU 0x400104dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG30 +CYDEV_UCFG_B0_P2_U1_CFG30 EQU 0x400104de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG31 +CYDEV_UCFG_B0_P2_U1_CFG31 EQU 0x400104df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG0 +CYDEV_UCFG_B0_P2_U1_DCFG0 EQU 0x400104e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG1 +CYDEV_UCFG_B0_P2_U1_DCFG1 EQU 0x400104e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG2 +CYDEV_UCFG_B0_P2_U1_DCFG2 EQU 0x400104e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG3 +CYDEV_UCFG_B0_P2_U1_DCFG3 EQU 0x400104e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG4 +CYDEV_UCFG_B0_P2_U1_DCFG4 EQU 0x400104e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG5 +CYDEV_UCFG_B0_P2_U1_DCFG5 EQU 0x400104ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG6 +CYDEV_UCFG_B0_P2_U1_DCFG6 EQU 0x400104ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG7 +CYDEV_UCFG_B0_P2_U1_DCFG7 EQU 0x400104ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_ROUTE_BASE +CYDEV_UCFG_B0_P2_ROUTE_BASE EQU 0x40010500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_ROUTE_SIZE +CYDEV_UCFG_B0_P2_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_BASE +CYDEV_UCFG_B0_P3_BASE EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_SIZE +CYDEV_UCFG_B0_P3_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_BASE +CYDEV_UCFG_B0_P3_U0_BASE EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_SIZE +CYDEV_UCFG_B0_P3_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT0 +CYDEV_UCFG_B0_P3_U0_PLD_IT0 EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT1 +CYDEV_UCFG_B0_P3_U0_PLD_IT1 EQU 0x40010604 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT2 +CYDEV_UCFG_B0_P3_U0_PLD_IT2 EQU 0x40010608 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT3 +CYDEV_UCFG_B0_P3_U0_PLD_IT3 EQU 0x4001060c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT4 +CYDEV_UCFG_B0_P3_U0_PLD_IT4 EQU 0x40010610 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT5 +CYDEV_UCFG_B0_P3_U0_PLD_IT5 EQU 0x40010614 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT6 +CYDEV_UCFG_B0_P3_U0_PLD_IT6 EQU 0x40010618 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT7 +CYDEV_UCFG_B0_P3_U0_PLD_IT7 EQU 0x4001061c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT8 +CYDEV_UCFG_B0_P3_U0_PLD_IT8 EQU 0x40010620 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT9 +CYDEV_UCFG_B0_P3_U0_PLD_IT9 EQU 0x40010624 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT10 +CYDEV_UCFG_B0_P3_U0_PLD_IT10 EQU 0x40010628 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT11 +CYDEV_UCFG_B0_P3_U0_PLD_IT11 EQU 0x4001062c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_ORT0 +CYDEV_UCFG_B0_P3_U0_PLD_ORT0 EQU 0x40010630 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_ORT1 +CYDEV_UCFG_B0_P3_U0_PLD_ORT1 EQU 0x40010632 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_ORT2 +CYDEV_UCFG_B0_P3_U0_PLD_ORT2 EQU 0x40010634 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_ORT3 +CYDEV_UCFG_B0_P3_U0_PLD_ORT3 EQU 0x40010636 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST EQU 0x40010638 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB EQU 0x4001063a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET EQU 0x4001063c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS EQU 0x4001063e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG0 +CYDEV_UCFG_B0_P3_U0_CFG0 EQU 0x40010640 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG1 +CYDEV_UCFG_B0_P3_U0_CFG1 EQU 0x40010641 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG2 +CYDEV_UCFG_B0_P3_U0_CFG2 EQU 0x40010642 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG3 +CYDEV_UCFG_B0_P3_U0_CFG3 EQU 0x40010643 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG4 +CYDEV_UCFG_B0_P3_U0_CFG4 EQU 0x40010644 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG5 +CYDEV_UCFG_B0_P3_U0_CFG5 EQU 0x40010645 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG6 +CYDEV_UCFG_B0_P3_U0_CFG6 EQU 0x40010646 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG7 +CYDEV_UCFG_B0_P3_U0_CFG7 EQU 0x40010647 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG8 +CYDEV_UCFG_B0_P3_U0_CFG8 EQU 0x40010648 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG9 +CYDEV_UCFG_B0_P3_U0_CFG9 EQU 0x40010649 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG10 +CYDEV_UCFG_B0_P3_U0_CFG10 EQU 0x4001064a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG11 +CYDEV_UCFG_B0_P3_U0_CFG11 EQU 0x4001064b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG12 +CYDEV_UCFG_B0_P3_U0_CFG12 EQU 0x4001064c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG13 +CYDEV_UCFG_B0_P3_U0_CFG13 EQU 0x4001064d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG14 +CYDEV_UCFG_B0_P3_U0_CFG14 EQU 0x4001064e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG15 +CYDEV_UCFG_B0_P3_U0_CFG15 EQU 0x4001064f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG16 +CYDEV_UCFG_B0_P3_U0_CFG16 EQU 0x40010650 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG17 +CYDEV_UCFG_B0_P3_U0_CFG17 EQU 0x40010651 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG18 +CYDEV_UCFG_B0_P3_U0_CFG18 EQU 0x40010652 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG19 +CYDEV_UCFG_B0_P3_U0_CFG19 EQU 0x40010653 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG20 +CYDEV_UCFG_B0_P3_U0_CFG20 EQU 0x40010654 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG21 +CYDEV_UCFG_B0_P3_U0_CFG21 EQU 0x40010655 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG22 +CYDEV_UCFG_B0_P3_U0_CFG22 EQU 0x40010656 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG23 +CYDEV_UCFG_B0_P3_U0_CFG23 EQU 0x40010657 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG24 +CYDEV_UCFG_B0_P3_U0_CFG24 EQU 0x40010658 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG25 +CYDEV_UCFG_B0_P3_U0_CFG25 EQU 0x40010659 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG26 +CYDEV_UCFG_B0_P3_U0_CFG26 EQU 0x4001065a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG27 +CYDEV_UCFG_B0_P3_U0_CFG27 EQU 0x4001065b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG28 +CYDEV_UCFG_B0_P3_U0_CFG28 EQU 0x4001065c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG29 +CYDEV_UCFG_B0_P3_U0_CFG29 EQU 0x4001065d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG30 +CYDEV_UCFG_B0_P3_U0_CFG30 EQU 0x4001065e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG31 +CYDEV_UCFG_B0_P3_U0_CFG31 EQU 0x4001065f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG0 +CYDEV_UCFG_B0_P3_U0_DCFG0 EQU 0x40010660 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG1 +CYDEV_UCFG_B0_P3_U0_DCFG1 EQU 0x40010662 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG2 +CYDEV_UCFG_B0_P3_U0_DCFG2 EQU 0x40010664 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG3 +CYDEV_UCFG_B0_P3_U0_DCFG3 EQU 0x40010666 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG4 +CYDEV_UCFG_B0_P3_U0_DCFG4 EQU 0x40010668 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG5 +CYDEV_UCFG_B0_P3_U0_DCFG5 EQU 0x4001066a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG6 +CYDEV_UCFG_B0_P3_U0_DCFG6 EQU 0x4001066c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG7 +CYDEV_UCFG_B0_P3_U0_DCFG7 EQU 0x4001066e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_BASE +CYDEV_UCFG_B0_P3_U1_BASE EQU 0x40010680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_SIZE +CYDEV_UCFG_B0_P3_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT0 +CYDEV_UCFG_B0_P3_U1_PLD_IT0 EQU 0x40010680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT1 +CYDEV_UCFG_B0_P3_U1_PLD_IT1 EQU 0x40010684 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT2 +CYDEV_UCFG_B0_P3_U1_PLD_IT2 EQU 0x40010688 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT3 +CYDEV_UCFG_B0_P3_U1_PLD_IT3 EQU 0x4001068c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT4 +CYDEV_UCFG_B0_P3_U1_PLD_IT4 EQU 0x40010690 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT5 +CYDEV_UCFG_B0_P3_U1_PLD_IT5 EQU 0x40010694 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT6 +CYDEV_UCFG_B0_P3_U1_PLD_IT6 EQU 0x40010698 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT7 +CYDEV_UCFG_B0_P3_U1_PLD_IT7 EQU 0x4001069c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT8 +CYDEV_UCFG_B0_P3_U1_PLD_IT8 EQU 0x400106a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT9 +CYDEV_UCFG_B0_P3_U1_PLD_IT9 EQU 0x400106a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT10 +CYDEV_UCFG_B0_P3_U1_PLD_IT10 EQU 0x400106a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT11 +CYDEV_UCFG_B0_P3_U1_PLD_IT11 EQU 0x400106ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_ORT0 +CYDEV_UCFG_B0_P3_U1_PLD_ORT0 EQU 0x400106b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_ORT1 +CYDEV_UCFG_B0_P3_U1_PLD_ORT1 EQU 0x400106b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_ORT2 +CYDEV_UCFG_B0_P3_U1_PLD_ORT2 EQU 0x400106b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_ORT3 +CYDEV_UCFG_B0_P3_U1_PLD_ORT3 EQU 0x400106b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST EQU 0x400106b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB EQU 0x400106ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET EQU 0x400106bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS EQU 0x400106be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG0 +CYDEV_UCFG_B0_P3_U1_CFG0 EQU 0x400106c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG1 +CYDEV_UCFG_B0_P3_U1_CFG1 EQU 0x400106c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG2 +CYDEV_UCFG_B0_P3_U1_CFG2 EQU 0x400106c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG3 +CYDEV_UCFG_B0_P3_U1_CFG3 EQU 0x400106c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG4 +CYDEV_UCFG_B0_P3_U1_CFG4 EQU 0x400106c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG5 +CYDEV_UCFG_B0_P3_U1_CFG5 EQU 0x400106c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG6 +CYDEV_UCFG_B0_P3_U1_CFG6 EQU 0x400106c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG7 +CYDEV_UCFG_B0_P3_U1_CFG7 EQU 0x400106c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG8 +CYDEV_UCFG_B0_P3_U1_CFG8 EQU 0x400106c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG9 +CYDEV_UCFG_B0_P3_U1_CFG9 EQU 0x400106c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG10 +CYDEV_UCFG_B0_P3_U1_CFG10 EQU 0x400106ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG11 +CYDEV_UCFG_B0_P3_U1_CFG11 EQU 0x400106cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG12 +CYDEV_UCFG_B0_P3_U1_CFG12 EQU 0x400106cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG13 +CYDEV_UCFG_B0_P3_U1_CFG13 EQU 0x400106cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG14 +CYDEV_UCFG_B0_P3_U1_CFG14 EQU 0x400106ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG15 +CYDEV_UCFG_B0_P3_U1_CFG15 EQU 0x400106cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG16 +CYDEV_UCFG_B0_P3_U1_CFG16 EQU 0x400106d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG17 +CYDEV_UCFG_B0_P3_U1_CFG17 EQU 0x400106d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG18 +CYDEV_UCFG_B0_P3_U1_CFG18 EQU 0x400106d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG19 +CYDEV_UCFG_B0_P3_U1_CFG19 EQU 0x400106d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG20 +CYDEV_UCFG_B0_P3_U1_CFG20 EQU 0x400106d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG21 +CYDEV_UCFG_B0_P3_U1_CFG21 EQU 0x400106d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG22 +CYDEV_UCFG_B0_P3_U1_CFG22 EQU 0x400106d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG23 +CYDEV_UCFG_B0_P3_U1_CFG23 EQU 0x400106d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG24 +CYDEV_UCFG_B0_P3_U1_CFG24 EQU 0x400106d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG25 +CYDEV_UCFG_B0_P3_U1_CFG25 EQU 0x400106d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG26 +CYDEV_UCFG_B0_P3_U1_CFG26 EQU 0x400106da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG27 +CYDEV_UCFG_B0_P3_U1_CFG27 EQU 0x400106db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG28 +CYDEV_UCFG_B0_P3_U1_CFG28 EQU 0x400106dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG29 +CYDEV_UCFG_B0_P3_U1_CFG29 EQU 0x400106dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG30 +CYDEV_UCFG_B0_P3_U1_CFG30 EQU 0x400106de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG31 +CYDEV_UCFG_B0_P3_U1_CFG31 EQU 0x400106df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG0 +CYDEV_UCFG_B0_P3_U1_DCFG0 EQU 0x400106e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG1 +CYDEV_UCFG_B0_P3_U1_DCFG1 EQU 0x400106e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG2 +CYDEV_UCFG_B0_P3_U1_DCFG2 EQU 0x400106e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG3 +CYDEV_UCFG_B0_P3_U1_DCFG3 EQU 0x400106e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG4 +CYDEV_UCFG_B0_P3_U1_DCFG4 EQU 0x400106e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG5 +CYDEV_UCFG_B0_P3_U1_DCFG5 EQU 0x400106ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG6 +CYDEV_UCFG_B0_P3_U1_DCFG6 EQU 0x400106ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG7 +CYDEV_UCFG_B0_P3_U1_DCFG7 EQU 0x400106ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_ROUTE_BASE +CYDEV_UCFG_B0_P3_ROUTE_BASE EQU 0x40010700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_ROUTE_SIZE +CYDEV_UCFG_B0_P3_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_BASE +CYDEV_UCFG_B0_P4_BASE EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_SIZE +CYDEV_UCFG_B0_P4_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_BASE +CYDEV_UCFG_B0_P4_U0_BASE EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_SIZE +CYDEV_UCFG_B0_P4_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT0 +CYDEV_UCFG_B0_P4_U0_PLD_IT0 EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT1 +CYDEV_UCFG_B0_P4_U0_PLD_IT1 EQU 0x40010804 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT2 +CYDEV_UCFG_B0_P4_U0_PLD_IT2 EQU 0x40010808 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT3 +CYDEV_UCFG_B0_P4_U0_PLD_IT3 EQU 0x4001080c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT4 +CYDEV_UCFG_B0_P4_U0_PLD_IT4 EQU 0x40010810 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT5 +CYDEV_UCFG_B0_P4_U0_PLD_IT5 EQU 0x40010814 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT6 +CYDEV_UCFG_B0_P4_U0_PLD_IT6 EQU 0x40010818 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT7 +CYDEV_UCFG_B0_P4_U0_PLD_IT7 EQU 0x4001081c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT8 +CYDEV_UCFG_B0_P4_U0_PLD_IT8 EQU 0x40010820 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT9 +CYDEV_UCFG_B0_P4_U0_PLD_IT9 EQU 0x40010824 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT10 +CYDEV_UCFG_B0_P4_U0_PLD_IT10 EQU 0x40010828 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT11 +CYDEV_UCFG_B0_P4_U0_PLD_IT11 EQU 0x4001082c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_ORT0 +CYDEV_UCFG_B0_P4_U0_PLD_ORT0 EQU 0x40010830 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_ORT1 +CYDEV_UCFG_B0_P4_U0_PLD_ORT1 EQU 0x40010832 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_ORT2 +CYDEV_UCFG_B0_P4_U0_PLD_ORT2 EQU 0x40010834 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_ORT3 +CYDEV_UCFG_B0_P4_U0_PLD_ORT3 EQU 0x40010836 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST EQU 0x40010838 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB EQU 0x4001083a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET EQU 0x4001083c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS EQU 0x4001083e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG0 +CYDEV_UCFG_B0_P4_U0_CFG0 EQU 0x40010840 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG1 +CYDEV_UCFG_B0_P4_U0_CFG1 EQU 0x40010841 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG2 +CYDEV_UCFG_B0_P4_U0_CFG2 EQU 0x40010842 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG3 +CYDEV_UCFG_B0_P4_U0_CFG3 EQU 0x40010843 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG4 +CYDEV_UCFG_B0_P4_U0_CFG4 EQU 0x40010844 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG5 +CYDEV_UCFG_B0_P4_U0_CFG5 EQU 0x40010845 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG6 +CYDEV_UCFG_B0_P4_U0_CFG6 EQU 0x40010846 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG7 +CYDEV_UCFG_B0_P4_U0_CFG7 EQU 0x40010847 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG8 +CYDEV_UCFG_B0_P4_U0_CFG8 EQU 0x40010848 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG9 +CYDEV_UCFG_B0_P4_U0_CFG9 EQU 0x40010849 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG10 +CYDEV_UCFG_B0_P4_U0_CFG10 EQU 0x4001084a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG11 +CYDEV_UCFG_B0_P4_U0_CFG11 EQU 0x4001084b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG12 +CYDEV_UCFG_B0_P4_U0_CFG12 EQU 0x4001084c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG13 +CYDEV_UCFG_B0_P4_U0_CFG13 EQU 0x4001084d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG14 +CYDEV_UCFG_B0_P4_U0_CFG14 EQU 0x4001084e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG15 +CYDEV_UCFG_B0_P4_U0_CFG15 EQU 0x4001084f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG16 +CYDEV_UCFG_B0_P4_U0_CFG16 EQU 0x40010850 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG17 +CYDEV_UCFG_B0_P4_U0_CFG17 EQU 0x40010851 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG18 +CYDEV_UCFG_B0_P4_U0_CFG18 EQU 0x40010852 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG19 +CYDEV_UCFG_B0_P4_U0_CFG19 EQU 0x40010853 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG20 +CYDEV_UCFG_B0_P4_U0_CFG20 EQU 0x40010854 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG21 +CYDEV_UCFG_B0_P4_U0_CFG21 EQU 0x40010855 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG22 +CYDEV_UCFG_B0_P4_U0_CFG22 EQU 0x40010856 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG23 +CYDEV_UCFG_B0_P4_U0_CFG23 EQU 0x40010857 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG24 +CYDEV_UCFG_B0_P4_U0_CFG24 EQU 0x40010858 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG25 +CYDEV_UCFG_B0_P4_U0_CFG25 EQU 0x40010859 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG26 +CYDEV_UCFG_B0_P4_U0_CFG26 EQU 0x4001085a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG27 +CYDEV_UCFG_B0_P4_U0_CFG27 EQU 0x4001085b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG28 +CYDEV_UCFG_B0_P4_U0_CFG28 EQU 0x4001085c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG29 +CYDEV_UCFG_B0_P4_U0_CFG29 EQU 0x4001085d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG30 +CYDEV_UCFG_B0_P4_U0_CFG30 EQU 0x4001085e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG31 +CYDEV_UCFG_B0_P4_U0_CFG31 EQU 0x4001085f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG0 +CYDEV_UCFG_B0_P4_U0_DCFG0 EQU 0x40010860 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG1 +CYDEV_UCFG_B0_P4_U0_DCFG1 EQU 0x40010862 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG2 +CYDEV_UCFG_B0_P4_U0_DCFG2 EQU 0x40010864 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG3 +CYDEV_UCFG_B0_P4_U0_DCFG3 EQU 0x40010866 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG4 +CYDEV_UCFG_B0_P4_U0_DCFG4 EQU 0x40010868 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG5 +CYDEV_UCFG_B0_P4_U0_DCFG5 EQU 0x4001086a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG6 +CYDEV_UCFG_B0_P4_U0_DCFG6 EQU 0x4001086c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG7 +CYDEV_UCFG_B0_P4_U0_DCFG7 EQU 0x4001086e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_BASE +CYDEV_UCFG_B0_P4_U1_BASE EQU 0x40010880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_SIZE +CYDEV_UCFG_B0_P4_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT0 +CYDEV_UCFG_B0_P4_U1_PLD_IT0 EQU 0x40010880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT1 +CYDEV_UCFG_B0_P4_U1_PLD_IT1 EQU 0x40010884 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT2 +CYDEV_UCFG_B0_P4_U1_PLD_IT2 EQU 0x40010888 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT3 +CYDEV_UCFG_B0_P4_U1_PLD_IT3 EQU 0x4001088c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT4 +CYDEV_UCFG_B0_P4_U1_PLD_IT4 EQU 0x40010890 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT5 +CYDEV_UCFG_B0_P4_U1_PLD_IT5 EQU 0x40010894 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT6 +CYDEV_UCFG_B0_P4_U1_PLD_IT6 EQU 0x40010898 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT7 +CYDEV_UCFG_B0_P4_U1_PLD_IT7 EQU 0x4001089c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT8 +CYDEV_UCFG_B0_P4_U1_PLD_IT8 EQU 0x400108a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT9 +CYDEV_UCFG_B0_P4_U1_PLD_IT9 EQU 0x400108a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT10 +CYDEV_UCFG_B0_P4_U1_PLD_IT10 EQU 0x400108a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT11 +CYDEV_UCFG_B0_P4_U1_PLD_IT11 EQU 0x400108ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_ORT0 +CYDEV_UCFG_B0_P4_U1_PLD_ORT0 EQU 0x400108b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_ORT1 +CYDEV_UCFG_B0_P4_U1_PLD_ORT1 EQU 0x400108b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_ORT2 +CYDEV_UCFG_B0_P4_U1_PLD_ORT2 EQU 0x400108b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_ORT3 +CYDEV_UCFG_B0_P4_U1_PLD_ORT3 EQU 0x400108b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST EQU 0x400108b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB EQU 0x400108ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET EQU 0x400108bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS EQU 0x400108be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG0 +CYDEV_UCFG_B0_P4_U1_CFG0 EQU 0x400108c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG1 +CYDEV_UCFG_B0_P4_U1_CFG1 EQU 0x400108c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG2 +CYDEV_UCFG_B0_P4_U1_CFG2 EQU 0x400108c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG3 +CYDEV_UCFG_B0_P4_U1_CFG3 EQU 0x400108c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG4 +CYDEV_UCFG_B0_P4_U1_CFG4 EQU 0x400108c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG5 +CYDEV_UCFG_B0_P4_U1_CFG5 EQU 0x400108c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG6 +CYDEV_UCFG_B0_P4_U1_CFG6 EQU 0x400108c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG7 +CYDEV_UCFG_B0_P4_U1_CFG7 EQU 0x400108c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG8 +CYDEV_UCFG_B0_P4_U1_CFG8 EQU 0x400108c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG9 +CYDEV_UCFG_B0_P4_U1_CFG9 EQU 0x400108c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG10 +CYDEV_UCFG_B0_P4_U1_CFG10 EQU 0x400108ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG11 +CYDEV_UCFG_B0_P4_U1_CFG11 EQU 0x400108cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG12 +CYDEV_UCFG_B0_P4_U1_CFG12 EQU 0x400108cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG13 +CYDEV_UCFG_B0_P4_U1_CFG13 EQU 0x400108cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG14 +CYDEV_UCFG_B0_P4_U1_CFG14 EQU 0x400108ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG15 +CYDEV_UCFG_B0_P4_U1_CFG15 EQU 0x400108cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG16 +CYDEV_UCFG_B0_P4_U1_CFG16 EQU 0x400108d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG17 +CYDEV_UCFG_B0_P4_U1_CFG17 EQU 0x400108d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG18 +CYDEV_UCFG_B0_P4_U1_CFG18 EQU 0x400108d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG19 +CYDEV_UCFG_B0_P4_U1_CFG19 EQU 0x400108d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG20 +CYDEV_UCFG_B0_P4_U1_CFG20 EQU 0x400108d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG21 +CYDEV_UCFG_B0_P4_U1_CFG21 EQU 0x400108d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG22 +CYDEV_UCFG_B0_P4_U1_CFG22 EQU 0x400108d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG23 +CYDEV_UCFG_B0_P4_U1_CFG23 EQU 0x400108d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG24 +CYDEV_UCFG_B0_P4_U1_CFG24 EQU 0x400108d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG25 +CYDEV_UCFG_B0_P4_U1_CFG25 EQU 0x400108d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG26 +CYDEV_UCFG_B0_P4_U1_CFG26 EQU 0x400108da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG27 +CYDEV_UCFG_B0_P4_U1_CFG27 EQU 0x400108db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG28 +CYDEV_UCFG_B0_P4_U1_CFG28 EQU 0x400108dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG29 +CYDEV_UCFG_B0_P4_U1_CFG29 EQU 0x400108dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG30 +CYDEV_UCFG_B0_P4_U1_CFG30 EQU 0x400108de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG31 +CYDEV_UCFG_B0_P4_U1_CFG31 EQU 0x400108df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG0 +CYDEV_UCFG_B0_P4_U1_DCFG0 EQU 0x400108e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG1 +CYDEV_UCFG_B0_P4_U1_DCFG1 EQU 0x400108e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG2 +CYDEV_UCFG_B0_P4_U1_DCFG2 EQU 0x400108e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG3 +CYDEV_UCFG_B0_P4_U1_DCFG3 EQU 0x400108e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG4 +CYDEV_UCFG_B0_P4_U1_DCFG4 EQU 0x400108e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG5 +CYDEV_UCFG_B0_P4_U1_DCFG5 EQU 0x400108ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG6 +CYDEV_UCFG_B0_P4_U1_DCFG6 EQU 0x400108ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG7 +CYDEV_UCFG_B0_P4_U1_DCFG7 EQU 0x400108ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_ROUTE_BASE +CYDEV_UCFG_B0_P4_ROUTE_BASE EQU 0x40010900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_ROUTE_SIZE +CYDEV_UCFG_B0_P4_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_BASE +CYDEV_UCFG_B0_P5_BASE EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_SIZE +CYDEV_UCFG_B0_P5_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_BASE +CYDEV_UCFG_B0_P5_U0_BASE EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_SIZE +CYDEV_UCFG_B0_P5_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT0 +CYDEV_UCFG_B0_P5_U0_PLD_IT0 EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT1 +CYDEV_UCFG_B0_P5_U0_PLD_IT1 EQU 0x40010a04 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT2 +CYDEV_UCFG_B0_P5_U0_PLD_IT2 EQU 0x40010a08 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT3 +CYDEV_UCFG_B0_P5_U0_PLD_IT3 EQU 0x40010a0c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT4 +CYDEV_UCFG_B0_P5_U0_PLD_IT4 EQU 0x40010a10 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT5 +CYDEV_UCFG_B0_P5_U0_PLD_IT5 EQU 0x40010a14 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT6 +CYDEV_UCFG_B0_P5_U0_PLD_IT6 EQU 0x40010a18 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT7 +CYDEV_UCFG_B0_P5_U0_PLD_IT7 EQU 0x40010a1c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT8 +CYDEV_UCFG_B0_P5_U0_PLD_IT8 EQU 0x40010a20 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT9 +CYDEV_UCFG_B0_P5_U0_PLD_IT9 EQU 0x40010a24 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT10 +CYDEV_UCFG_B0_P5_U0_PLD_IT10 EQU 0x40010a28 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT11 +CYDEV_UCFG_B0_P5_U0_PLD_IT11 EQU 0x40010a2c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_ORT0 +CYDEV_UCFG_B0_P5_U0_PLD_ORT0 EQU 0x40010a30 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_ORT1 +CYDEV_UCFG_B0_P5_U0_PLD_ORT1 EQU 0x40010a32 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_ORT2 +CYDEV_UCFG_B0_P5_U0_PLD_ORT2 EQU 0x40010a34 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_ORT3 +CYDEV_UCFG_B0_P5_U0_PLD_ORT3 EQU 0x40010a36 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST EQU 0x40010a38 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB EQU 0x40010a3a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET EQU 0x40010a3c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS EQU 0x40010a3e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG0 +CYDEV_UCFG_B0_P5_U0_CFG0 EQU 0x40010a40 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG1 +CYDEV_UCFG_B0_P5_U0_CFG1 EQU 0x40010a41 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG2 +CYDEV_UCFG_B0_P5_U0_CFG2 EQU 0x40010a42 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG3 +CYDEV_UCFG_B0_P5_U0_CFG3 EQU 0x40010a43 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG4 +CYDEV_UCFG_B0_P5_U0_CFG4 EQU 0x40010a44 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG5 +CYDEV_UCFG_B0_P5_U0_CFG5 EQU 0x40010a45 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG6 +CYDEV_UCFG_B0_P5_U0_CFG6 EQU 0x40010a46 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG7 +CYDEV_UCFG_B0_P5_U0_CFG7 EQU 0x40010a47 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG8 +CYDEV_UCFG_B0_P5_U0_CFG8 EQU 0x40010a48 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG9 +CYDEV_UCFG_B0_P5_U0_CFG9 EQU 0x40010a49 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG10 +CYDEV_UCFG_B0_P5_U0_CFG10 EQU 0x40010a4a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG11 +CYDEV_UCFG_B0_P5_U0_CFG11 EQU 0x40010a4b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG12 +CYDEV_UCFG_B0_P5_U0_CFG12 EQU 0x40010a4c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG13 +CYDEV_UCFG_B0_P5_U0_CFG13 EQU 0x40010a4d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG14 +CYDEV_UCFG_B0_P5_U0_CFG14 EQU 0x40010a4e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG15 +CYDEV_UCFG_B0_P5_U0_CFG15 EQU 0x40010a4f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG16 +CYDEV_UCFG_B0_P5_U0_CFG16 EQU 0x40010a50 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG17 +CYDEV_UCFG_B0_P5_U0_CFG17 EQU 0x40010a51 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG18 +CYDEV_UCFG_B0_P5_U0_CFG18 EQU 0x40010a52 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG19 +CYDEV_UCFG_B0_P5_U0_CFG19 EQU 0x40010a53 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG20 +CYDEV_UCFG_B0_P5_U0_CFG20 EQU 0x40010a54 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG21 +CYDEV_UCFG_B0_P5_U0_CFG21 EQU 0x40010a55 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG22 +CYDEV_UCFG_B0_P5_U0_CFG22 EQU 0x40010a56 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG23 +CYDEV_UCFG_B0_P5_U0_CFG23 EQU 0x40010a57 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG24 +CYDEV_UCFG_B0_P5_U0_CFG24 EQU 0x40010a58 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG25 +CYDEV_UCFG_B0_P5_U0_CFG25 EQU 0x40010a59 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG26 +CYDEV_UCFG_B0_P5_U0_CFG26 EQU 0x40010a5a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG27 +CYDEV_UCFG_B0_P5_U0_CFG27 EQU 0x40010a5b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG28 +CYDEV_UCFG_B0_P5_U0_CFG28 EQU 0x40010a5c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG29 +CYDEV_UCFG_B0_P5_U0_CFG29 EQU 0x40010a5d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG30 +CYDEV_UCFG_B0_P5_U0_CFG30 EQU 0x40010a5e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG31 +CYDEV_UCFG_B0_P5_U0_CFG31 EQU 0x40010a5f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG0 +CYDEV_UCFG_B0_P5_U0_DCFG0 EQU 0x40010a60 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG1 +CYDEV_UCFG_B0_P5_U0_DCFG1 EQU 0x40010a62 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG2 +CYDEV_UCFG_B0_P5_U0_DCFG2 EQU 0x40010a64 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG3 +CYDEV_UCFG_B0_P5_U0_DCFG3 EQU 0x40010a66 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG4 +CYDEV_UCFG_B0_P5_U0_DCFG4 EQU 0x40010a68 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG5 +CYDEV_UCFG_B0_P5_U0_DCFG5 EQU 0x40010a6a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG6 +CYDEV_UCFG_B0_P5_U0_DCFG6 EQU 0x40010a6c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG7 +CYDEV_UCFG_B0_P5_U0_DCFG7 EQU 0x40010a6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_BASE +CYDEV_UCFG_B0_P5_U1_BASE EQU 0x40010a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_SIZE +CYDEV_UCFG_B0_P5_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT0 +CYDEV_UCFG_B0_P5_U1_PLD_IT0 EQU 0x40010a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT1 +CYDEV_UCFG_B0_P5_U1_PLD_IT1 EQU 0x40010a84 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT2 +CYDEV_UCFG_B0_P5_U1_PLD_IT2 EQU 0x40010a88 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT3 +CYDEV_UCFG_B0_P5_U1_PLD_IT3 EQU 0x40010a8c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT4 +CYDEV_UCFG_B0_P5_U1_PLD_IT4 EQU 0x40010a90 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT5 +CYDEV_UCFG_B0_P5_U1_PLD_IT5 EQU 0x40010a94 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT6 +CYDEV_UCFG_B0_P5_U1_PLD_IT6 EQU 0x40010a98 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT7 +CYDEV_UCFG_B0_P5_U1_PLD_IT7 EQU 0x40010a9c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT8 +CYDEV_UCFG_B0_P5_U1_PLD_IT8 EQU 0x40010aa0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT9 +CYDEV_UCFG_B0_P5_U1_PLD_IT9 EQU 0x40010aa4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT10 +CYDEV_UCFG_B0_P5_U1_PLD_IT10 EQU 0x40010aa8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT11 +CYDEV_UCFG_B0_P5_U1_PLD_IT11 EQU 0x40010aac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_ORT0 +CYDEV_UCFG_B0_P5_U1_PLD_ORT0 EQU 0x40010ab0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_ORT1 +CYDEV_UCFG_B0_P5_U1_PLD_ORT1 EQU 0x40010ab2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_ORT2 +CYDEV_UCFG_B0_P5_U1_PLD_ORT2 EQU 0x40010ab4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_ORT3 +CYDEV_UCFG_B0_P5_U1_PLD_ORT3 EQU 0x40010ab6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST EQU 0x40010ab8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB EQU 0x40010aba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET EQU 0x40010abc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS EQU 0x40010abe + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG0 +CYDEV_UCFG_B0_P5_U1_CFG0 EQU 0x40010ac0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG1 +CYDEV_UCFG_B0_P5_U1_CFG1 EQU 0x40010ac1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG2 +CYDEV_UCFG_B0_P5_U1_CFG2 EQU 0x40010ac2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG3 +CYDEV_UCFG_B0_P5_U1_CFG3 EQU 0x40010ac3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG4 +CYDEV_UCFG_B0_P5_U1_CFG4 EQU 0x40010ac4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG5 +CYDEV_UCFG_B0_P5_U1_CFG5 EQU 0x40010ac5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG6 +CYDEV_UCFG_B0_P5_U1_CFG6 EQU 0x40010ac6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG7 +CYDEV_UCFG_B0_P5_U1_CFG7 EQU 0x40010ac7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG8 +CYDEV_UCFG_B0_P5_U1_CFG8 EQU 0x40010ac8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG9 +CYDEV_UCFG_B0_P5_U1_CFG9 EQU 0x40010ac9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG10 +CYDEV_UCFG_B0_P5_U1_CFG10 EQU 0x40010aca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG11 +CYDEV_UCFG_B0_P5_U1_CFG11 EQU 0x40010acb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG12 +CYDEV_UCFG_B0_P5_U1_CFG12 EQU 0x40010acc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG13 +CYDEV_UCFG_B0_P5_U1_CFG13 EQU 0x40010acd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG14 +CYDEV_UCFG_B0_P5_U1_CFG14 EQU 0x40010ace + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG15 +CYDEV_UCFG_B0_P5_U1_CFG15 EQU 0x40010acf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG16 +CYDEV_UCFG_B0_P5_U1_CFG16 EQU 0x40010ad0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG17 +CYDEV_UCFG_B0_P5_U1_CFG17 EQU 0x40010ad1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG18 +CYDEV_UCFG_B0_P5_U1_CFG18 EQU 0x40010ad2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG19 +CYDEV_UCFG_B0_P5_U1_CFG19 EQU 0x40010ad3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG20 +CYDEV_UCFG_B0_P5_U1_CFG20 EQU 0x40010ad4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG21 +CYDEV_UCFG_B0_P5_U1_CFG21 EQU 0x40010ad5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG22 +CYDEV_UCFG_B0_P5_U1_CFG22 EQU 0x40010ad6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG23 +CYDEV_UCFG_B0_P5_U1_CFG23 EQU 0x40010ad7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG24 +CYDEV_UCFG_B0_P5_U1_CFG24 EQU 0x40010ad8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG25 +CYDEV_UCFG_B0_P5_U1_CFG25 EQU 0x40010ad9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG26 +CYDEV_UCFG_B0_P5_U1_CFG26 EQU 0x40010ada + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG27 +CYDEV_UCFG_B0_P5_U1_CFG27 EQU 0x40010adb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG28 +CYDEV_UCFG_B0_P5_U1_CFG28 EQU 0x40010adc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG29 +CYDEV_UCFG_B0_P5_U1_CFG29 EQU 0x40010add + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG30 +CYDEV_UCFG_B0_P5_U1_CFG30 EQU 0x40010ade + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG31 +CYDEV_UCFG_B0_P5_U1_CFG31 EQU 0x40010adf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG0 +CYDEV_UCFG_B0_P5_U1_DCFG0 EQU 0x40010ae0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG1 +CYDEV_UCFG_B0_P5_U1_DCFG1 EQU 0x40010ae2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG2 +CYDEV_UCFG_B0_P5_U1_DCFG2 EQU 0x40010ae4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG3 +CYDEV_UCFG_B0_P5_U1_DCFG3 EQU 0x40010ae6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG4 +CYDEV_UCFG_B0_P5_U1_DCFG4 EQU 0x40010ae8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG5 +CYDEV_UCFG_B0_P5_U1_DCFG5 EQU 0x40010aea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG6 +CYDEV_UCFG_B0_P5_U1_DCFG6 EQU 0x40010aec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG7 +CYDEV_UCFG_B0_P5_U1_DCFG7 EQU 0x40010aee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_ROUTE_BASE +CYDEV_UCFG_B0_P5_ROUTE_BASE EQU 0x40010b00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_ROUTE_SIZE +CYDEV_UCFG_B0_P5_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_BASE +CYDEV_UCFG_B0_P6_BASE EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_SIZE +CYDEV_UCFG_B0_P6_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_BASE +CYDEV_UCFG_B0_P6_U0_BASE EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_SIZE +CYDEV_UCFG_B0_P6_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT0 +CYDEV_UCFG_B0_P6_U0_PLD_IT0 EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT1 +CYDEV_UCFG_B0_P6_U0_PLD_IT1 EQU 0x40010c04 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT2 +CYDEV_UCFG_B0_P6_U0_PLD_IT2 EQU 0x40010c08 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT3 +CYDEV_UCFG_B0_P6_U0_PLD_IT3 EQU 0x40010c0c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT4 +CYDEV_UCFG_B0_P6_U0_PLD_IT4 EQU 0x40010c10 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT5 +CYDEV_UCFG_B0_P6_U0_PLD_IT5 EQU 0x40010c14 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT6 +CYDEV_UCFG_B0_P6_U0_PLD_IT6 EQU 0x40010c18 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT7 +CYDEV_UCFG_B0_P6_U0_PLD_IT7 EQU 0x40010c1c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT8 +CYDEV_UCFG_B0_P6_U0_PLD_IT8 EQU 0x40010c20 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT9 +CYDEV_UCFG_B0_P6_U0_PLD_IT9 EQU 0x40010c24 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT10 +CYDEV_UCFG_B0_P6_U0_PLD_IT10 EQU 0x40010c28 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT11 +CYDEV_UCFG_B0_P6_U0_PLD_IT11 EQU 0x40010c2c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_ORT0 +CYDEV_UCFG_B0_P6_U0_PLD_ORT0 EQU 0x40010c30 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_ORT1 +CYDEV_UCFG_B0_P6_U0_PLD_ORT1 EQU 0x40010c32 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_ORT2 +CYDEV_UCFG_B0_P6_U0_PLD_ORT2 EQU 0x40010c34 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_ORT3 +CYDEV_UCFG_B0_P6_U0_PLD_ORT3 EQU 0x40010c36 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST EQU 0x40010c38 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB EQU 0x40010c3a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET EQU 0x40010c3c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS EQU 0x40010c3e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG0 +CYDEV_UCFG_B0_P6_U0_CFG0 EQU 0x40010c40 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG1 +CYDEV_UCFG_B0_P6_U0_CFG1 EQU 0x40010c41 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG2 +CYDEV_UCFG_B0_P6_U0_CFG2 EQU 0x40010c42 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG3 +CYDEV_UCFG_B0_P6_U0_CFG3 EQU 0x40010c43 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG4 +CYDEV_UCFG_B0_P6_U0_CFG4 EQU 0x40010c44 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG5 +CYDEV_UCFG_B0_P6_U0_CFG5 EQU 0x40010c45 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG6 +CYDEV_UCFG_B0_P6_U0_CFG6 EQU 0x40010c46 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG7 +CYDEV_UCFG_B0_P6_U0_CFG7 EQU 0x40010c47 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG8 +CYDEV_UCFG_B0_P6_U0_CFG8 EQU 0x40010c48 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG9 +CYDEV_UCFG_B0_P6_U0_CFG9 EQU 0x40010c49 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG10 +CYDEV_UCFG_B0_P6_U0_CFG10 EQU 0x40010c4a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG11 +CYDEV_UCFG_B0_P6_U0_CFG11 EQU 0x40010c4b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG12 +CYDEV_UCFG_B0_P6_U0_CFG12 EQU 0x40010c4c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG13 +CYDEV_UCFG_B0_P6_U0_CFG13 EQU 0x40010c4d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG14 +CYDEV_UCFG_B0_P6_U0_CFG14 EQU 0x40010c4e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG15 +CYDEV_UCFG_B0_P6_U0_CFG15 EQU 0x40010c4f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG16 +CYDEV_UCFG_B0_P6_U0_CFG16 EQU 0x40010c50 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG17 +CYDEV_UCFG_B0_P6_U0_CFG17 EQU 0x40010c51 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG18 +CYDEV_UCFG_B0_P6_U0_CFG18 EQU 0x40010c52 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG19 +CYDEV_UCFG_B0_P6_U0_CFG19 EQU 0x40010c53 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG20 +CYDEV_UCFG_B0_P6_U0_CFG20 EQU 0x40010c54 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG21 +CYDEV_UCFG_B0_P6_U0_CFG21 EQU 0x40010c55 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG22 +CYDEV_UCFG_B0_P6_U0_CFG22 EQU 0x40010c56 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG23 +CYDEV_UCFG_B0_P6_U0_CFG23 EQU 0x40010c57 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG24 +CYDEV_UCFG_B0_P6_U0_CFG24 EQU 0x40010c58 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG25 +CYDEV_UCFG_B0_P6_U0_CFG25 EQU 0x40010c59 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG26 +CYDEV_UCFG_B0_P6_U0_CFG26 EQU 0x40010c5a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG27 +CYDEV_UCFG_B0_P6_U0_CFG27 EQU 0x40010c5b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG28 +CYDEV_UCFG_B0_P6_U0_CFG28 EQU 0x40010c5c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG29 +CYDEV_UCFG_B0_P6_U0_CFG29 EQU 0x40010c5d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG30 +CYDEV_UCFG_B0_P6_U0_CFG30 EQU 0x40010c5e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG31 +CYDEV_UCFG_B0_P6_U0_CFG31 EQU 0x40010c5f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG0 +CYDEV_UCFG_B0_P6_U0_DCFG0 EQU 0x40010c60 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG1 +CYDEV_UCFG_B0_P6_U0_DCFG1 EQU 0x40010c62 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG2 +CYDEV_UCFG_B0_P6_U0_DCFG2 EQU 0x40010c64 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG3 +CYDEV_UCFG_B0_P6_U0_DCFG3 EQU 0x40010c66 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG4 +CYDEV_UCFG_B0_P6_U0_DCFG4 EQU 0x40010c68 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG5 +CYDEV_UCFG_B0_P6_U0_DCFG5 EQU 0x40010c6a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG6 +CYDEV_UCFG_B0_P6_U0_DCFG6 EQU 0x40010c6c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG7 +CYDEV_UCFG_B0_P6_U0_DCFG7 EQU 0x40010c6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_BASE +CYDEV_UCFG_B0_P6_U1_BASE EQU 0x40010c80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_SIZE +CYDEV_UCFG_B0_P6_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT0 +CYDEV_UCFG_B0_P6_U1_PLD_IT0 EQU 0x40010c80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT1 +CYDEV_UCFG_B0_P6_U1_PLD_IT1 EQU 0x40010c84 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT2 +CYDEV_UCFG_B0_P6_U1_PLD_IT2 EQU 0x40010c88 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT3 +CYDEV_UCFG_B0_P6_U1_PLD_IT3 EQU 0x40010c8c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT4 +CYDEV_UCFG_B0_P6_U1_PLD_IT4 EQU 0x40010c90 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT5 +CYDEV_UCFG_B0_P6_U1_PLD_IT5 EQU 0x40010c94 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT6 +CYDEV_UCFG_B0_P6_U1_PLD_IT6 EQU 0x40010c98 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT7 +CYDEV_UCFG_B0_P6_U1_PLD_IT7 EQU 0x40010c9c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT8 +CYDEV_UCFG_B0_P6_U1_PLD_IT8 EQU 0x40010ca0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT9 +CYDEV_UCFG_B0_P6_U1_PLD_IT9 EQU 0x40010ca4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT10 +CYDEV_UCFG_B0_P6_U1_PLD_IT10 EQU 0x40010ca8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT11 +CYDEV_UCFG_B0_P6_U1_PLD_IT11 EQU 0x40010cac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_ORT0 +CYDEV_UCFG_B0_P6_U1_PLD_ORT0 EQU 0x40010cb0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_ORT1 +CYDEV_UCFG_B0_P6_U1_PLD_ORT1 EQU 0x40010cb2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_ORT2 +CYDEV_UCFG_B0_P6_U1_PLD_ORT2 EQU 0x40010cb4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_ORT3 +CYDEV_UCFG_B0_P6_U1_PLD_ORT3 EQU 0x40010cb6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST EQU 0x40010cb8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB EQU 0x40010cba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET EQU 0x40010cbc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS EQU 0x40010cbe + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG0 +CYDEV_UCFG_B0_P6_U1_CFG0 EQU 0x40010cc0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG1 +CYDEV_UCFG_B0_P6_U1_CFG1 EQU 0x40010cc1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG2 +CYDEV_UCFG_B0_P6_U1_CFG2 EQU 0x40010cc2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG3 +CYDEV_UCFG_B0_P6_U1_CFG3 EQU 0x40010cc3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG4 +CYDEV_UCFG_B0_P6_U1_CFG4 EQU 0x40010cc4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG5 +CYDEV_UCFG_B0_P6_U1_CFG5 EQU 0x40010cc5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG6 +CYDEV_UCFG_B0_P6_U1_CFG6 EQU 0x40010cc6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG7 +CYDEV_UCFG_B0_P6_U1_CFG7 EQU 0x40010cc7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG8 +CYDEV_UCFG_B0_P6_U1_CFG8 EQU 0x40010cc8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG9 +CYDEV_UCFG_B0_P6_U1_CFG9 EQU 0x40010cc9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG10 +CYDEV_UCFG_B0_P6_U1_CFG10 EQU 0x40010cca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG11 +CYDEV_UCFG_B0_P6_U1_CFG11 EQU 0x40010ccb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG12 +CYDEV_UCFG_B0_P6_U1_CFG12 EQU 0x40010ccc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG13 +CYDEV_UCFG_B0_P6_U1_CFG13 EQU 0x40010ccd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG14 +CYDEV_UCFG_B0_P6_U1_CFG14 EQU 0x40010cce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG15 +CYDEV_UCFG_B0_P6_U1_CFG15 EQU 0x40010ccf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG16 +CYDEV_UCFG_B0_P6_U1_CFG16 EQU 0x40010cd0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG17 +CYDEV_UCFG_B0_P6_U1_CFG17 EQU 0x40010cd1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG18 +CYDEV_UCFG_B0_P6_U1_CFG18 EQU 0x40010cd2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG19 +CYDEV_UCFG_B0_P6_U1_CFG19 EQU 0x40010cd3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG20 +CYDEV_UCFG_B0_P6_U1_CFG20 EQU 0x40010cd4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG21 +CYDEV_UCFG_B0_P6_U1_CFG21 EQU 0x40010cd5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG22 +CYDEV_UCFG_B0_P6_U1_CFG22 EQU 0x40010cd6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG23 +CYDEV_UCFG_B0_P6_U1_CFG23 EQU 0x40010cd7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG24 +CYDEV_UCFG_B0_P6_U1_CFG24 EQU 0x40010cd8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG25 +CYDEV_UCFG_B0_P6_U1_CFG25 EQU 0x40010cd9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG26 +CYDEV_UCFG_B0_P6_U1_CFG26 EQU 0x40010cda + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG27 +CYDEV_UCFG_B0_P6_U1_CFG27 EQU 0x40010cdb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG28 +CYDEV_UCFG_B0_P6_U1_CFG28 EQU 0x40010cdc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG29 +CYDEV_UCFG_B0_P6_U1_CFG29 EQU 0x40010cdd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG30 +CYDEV_UCFG_B0_P6_U1_CFG30 EQU 0x40010cde + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG31 +CYDEV_UCFG_B0_P6_U1_CFG31 EQU 0x40010cdf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG0 +CYDEV_UCFG_B0_P6_U1_DCFG0 EQU 0x40010ce0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG1 +CYDEV_UCFG_B0_P6_U1_DCFG1 EQU 0x40010ce2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG2 +CYDEV_UCFG_B0_P6_U1_DCFG2 EQU 0x40010ce4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG3 +CYDEV_UCFG_B0_P6_U1_DCFG3 EQU 0x40010ce6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG4 +CYDEV_UCFG_B0_P6_U1_DCFG4 EQU 0x40010ce8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG5 +CYDEV_UCFG_B0_P6_U1_DCFG5 EQU 0x40010cea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG6 +CYDEV_UCFG_B0_P6_U1_DCFG6 EQU 0x40010cec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG7 +CYDEV_UCFG_B0_P6_U1_DCFG7 EQU 0x40010cee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_ROUTE_BASE +CYDEV_UCFG_B0_P6_ROUTE_BASE EQU 0x40010d00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_ROUTE_SIZE +CYDEV_UCFG_B0_P6_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_BASE +CYDEV_UCFG_B0_P7_BASE EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_SIZE +CYDEV_UCFG_B0_P7_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_BASE +CYDEV_UCFG_B0_P7_U0_BASE EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_SIZE +CYDEV_UCFG_B0_P7_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT0 +CYDEV_UCFG_B0_P7_U0_PLD_IT0 EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT1 +CYDEV_UCFG_B0_P7_U0_PLD_IT1 EQU 0x40010e04 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT2 +CYDEV_UCFG_B0_P7_U0_PLD_IT2 EQU 0x40010e08 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT3 +CYDEV_UCFG_B0_P7_U0_PLD_IT3 EQU 0x40010e0c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT4 +CYDEV_UCFG_B0_P7_U0_PLD_IT4 EQU 0x40010e10 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT5 +CYDEV_UCFG_B0_P7_U0_PLD_IT5 EQU 0x40010e14 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT6 +CYDEV_UCFG_B0_P7_U0_PLD_IT6 EQU 0x40010e18 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT7 +CYDEV_UCFG_B0_P7_U0_PLD_IT7 EQU 0x40010e1c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT8 +CYDEV_UCFG_B0_P7_U0_PLD_IT8 EQU 0x40010e20 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT9 +CYDEV_UCFG_B0_P7_U0_PLD_IT9 EQU 0x40010e24 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT10 +CYDEV_UCFG_B0_P7_U0_PLD_IT10 EQU 0x40010e28 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT11 +CYDEV_UCFG_B0_P7_U0_PLD_IT11 EQU 0x40010e2c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_ORT0 +CYDEV_UCFG_B0_P7_U0_PLD_ORT0 EQU 0x40010e30 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_ORT1 +CYDEV_UCFG_B0_P7_U0_PLD_ORT1 EQU 0x40010e32 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_ORT2 +CYDEV_UCFG_B0_P7_U0_PLD_ORT2 EQU 0x40010e34 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_ORT3 +CYDEV_UCFG_B0_P7_U0_PLD_ORT3 EQU 0x40010e36 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST EQU 0x40010e38 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB EQU 0x40010e3a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET EQU 0x40010e3c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS EQU 0x40010e3e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG0 +CYDEV_UCFG_B0_P7_U0_CFG0 EQU 0x40010e40 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG1 +CYDEV_UCFG_B0_P7_U0_CFG1 EQU 0x40010e41 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG2 +CYDEV_UCFG_B0_P7_U0_CFG2 EQU 0x40010e42 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG3 +CYDEV_UCFG_B0_P7_U0_CFG3 EQU 0x40010e43 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG4 +CYDEV_UCFG_B0_P7_U0_CFG4 EQU 0x40010e44 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG5 +CYDEV_UCFG_B0_P7_U0_CFG5 EQU 0x40010e45 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG6 +CYDEV_UCFG_B0_P7_U0_CFG6 EQU 0x40010e46 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG7 +CYDEV_UCFG_B0_P7_U0_CFG7 EQU 0x40010e47 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG8 +CYDEV_UCFG_B0_P7_U0_CFG8 EQU 0x40010e48 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG9 +CYDEV_UCFG_B0_P7_U0_CFG9 EQU 0x40010e49 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG10 +CYDEV_UCFG_B0_P7_U0_CFG10 EQU 0x40010e4a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG11 +CYDEV_UCFG_B0_P7_U0_CFG11 EQU 0x40010e4b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG12 +CYDEV_UCFG_B0_P7_U0_CFG12 EQU 0x40010e4c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG13 +CYDEV_UCFG_B0_P7_U0_CFG13 EQU 0x40010e4d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG14 +CYDEV_UCFG_B0_P7_U0_CFG14 EQU 0x40010e4e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG15 +CYDEV_UCFG_B0_P7_U0_CFG15 EQU 0x40010e4f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG16 +CYDEV_UCFG_B0_P7_U0_CFG16 EQU 0x40010e50 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG17 +CYDEV_UCFG_B0_P7_U0_CFG17 EQU 0x40010e51 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG18 +CYDEV_UCFG_B0_P7_U0_CFG18 EQU 0x40010e52 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG19 +CYDEV_UCFG_B0_P7_U0_CFG19 EQU 0x40010e53 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG20 +CYDEV_UCFG_B0_P7_U0_CFG20 EQU 0x40010e54 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG21 +CYDEV_UCFG_B0_P7_U0_CFG21 EQU 0x40010e55 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG22 +CYDEV_UCFG_B0_P7_U0_CFG22 EQU 0x40010e56 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG23 +CYDEV_UCFG_B0_P7_U0_CFG23 EQU 0x40010e57 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG24 +CYDEV_UCFG_B0_P7_U0_CFG24 EQU 0x40010e58 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG25 +CYDEV_UCFG_B0_P7_U0_CFG25 EQU 0x40010e59 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG26 +CYDEV_UCFG_B0_P7_U0_CFG26 EQU 0x40010e5a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG27 +CYDEV_UCFG_B0_P7_U0_CFG27 EQU 0x40010e5b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG28 +CYDEV_UCFG_B0_P7_U0_CFG28 EQU 0x40010e5c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG29 +CYDEV_UCFG_B0_P7_U0_CFG29 EQU 0x40010e5d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG30 +CYDEV_UCFG_B0_P7_U0_CFG30 EQU 0x40010e5e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG31 +CYDEV_UCFG_B0_P7_U0_CFG31 EQU 0x40010e5f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG0 +CYDEV_UCFG_B0_P7_U0_DCFG0 EQU 0x40010e60 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG1 +CYDEV_UCFG_B0_P7_U0_DCFG1 EQU 0x40010e62 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG2 +CYDEV_UCFG_B0_P7_U0_DCFG2 EQU 0x40010e64 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG3 +CYDEV_UCFG_B0_P7_U0_DCFG3 EQU 0x40010e66 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG4 +CYDEV_UCFG_B0_P7_U0_DCFG4 EQU 0x40010e68 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG5 +CYDEV_UCFG_B0_P7_U0_DCFG5 EQU 0x40010e6a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG6 +CYDEV_UCFG_B0_P7_U0_DCFG6 EQU 0x40010e6c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG7 +CYDEV_UCFG_B0_P7_U0_DCFG7 EQU 0x40010e6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_BASE +CYDEV_UCFG_B0_P7_U1_BASE EQU 0x40010e80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_SIZE +CYDEV_UCFG_B0_P7_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT0 +CYDEV_UCFG_B0_P7_U1_PLD_IT0 EQU 0x40010e80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT1 +CYDEV_UCFG_B0_P7_U1_PLD_IT1 EQU 0x40010e84 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT2 +CYDEV_UCFG_B0_P7_U1_PLD_IT2 EQU 0x40010e88 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT3 +CYDEV_UCFG_B0_P7_U1_PLD_IT3 EQU 0x40010e8c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT4 +CYDEV_UCFG_B0_P7_U1_PLD_IT4 EQU 0x40010e90 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT5 +CYDEV_UCFG_B0_P7_U1_PLD_IT5 EQU 0x40010e94 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT6 +CYDEV_UCFG_B0_P7_U1_PLD_IT6 EQU 0x40010e98 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT7 +CYDEV_UCFG_B0_P7_U1_PLD_IT7 EQU 0x40010e9c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT8 +CYDEV_UCFG_B0_P7_U1_PLD_IT8 EQU 0x40010ea0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT9 +CYDEV_UCFG_B0_P7_U1_PLD_IT9 EQU 0x40010ea4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT10 +CYDEV_UCFG_B0_P7_U1_PLD_IT10 EQU 0x40010ea8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT11 +CYDEV_UCFG_B0_P7_U1_PLD_IT11 EQU 0x40010eac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_ORT0 +CYDEV_UCFG_B0_P7_U1_PLD_ORT0 EQU 0x40010eb0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_ORT1 +CYDEV_UCFG_B0_P7_U1_PLD_ORT1 EQU 0x40010eb2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_ORT2 +CYDEV_UCFG_B0_P7_U1_PLD_ORT2 EQU 0x40010eb4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_ORT3 +CYDEV_UCFG_B0_P7_U1_PLD_ORT3 EQU 0x40010eb6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST EQU 0x40010eb8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB EQU 0x40010eba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET EQU 0x40010ebc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS EQU 0x40010ebe + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG0 +CYDEV_UCFG_B0_P7_U1_CFG0 EQU 0x40010ec0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG1 +CYDEV_UCFG_B0_P7_U1_CFG1 EQU 0x40010ec1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG2 +CYDEV_UCFG_B0_P7_U1_CFG2 EQU 0x40010ec2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG3 +CYDEV_UCFG_B0_P7_U1_CFG3 EQU 0x40010ec3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG4 +CYDEV_UCFG_B0_P7_U1_CFG4 EQU 0x40010ec4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG5 +CYDEV_UCFG_B0_P7_U1_CFG5 EQU 0x40010ec5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG6 +CYDEV_UCFG_B0_P7_U1_CFG6 EQU 0x40010ec6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG7 +CYDEV_UCFG_B0_P7_U1_CFG7 EQU 0x40010ec7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG8 +CYDEV_UCFG_B0_P7_U1_CFG8 EQU 0x40010ec8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG9 +CYDEV_UCFG_B0_P7_U1_CFG9 EQU 0x40010ec9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG10 +CYDEV_UCFG_B0_P7_U1_CFG10 EQU 0x40010eca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG11 +CYDEV_UCFG_B0_P7_U1_CFG11 EQU 0x40010ecb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG12 +CYDEV_UCFG_B0_P7_U1_CFG12 EQU 0x40010ecc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG13 +CYDEV_UCFG_B0_P7_U1_CFG13 EQU 0x40010ecd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG14 +CYDEV_UCFG_B0_P7_U1_CFG14 EQU 0x40010ece + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG15 +CYDEV_UCFG_B0_P7_U1_CFG15 EQU 0x40010ecf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG16 +CYDEV_UCFG_B0_P7_U1_CFG16 EQU 0x40010ed0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG17 +CYDEV_UCFG_B0_P7_U1_CFG17 EQU 0x40010ed1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG18 +CYDEV_UCFG_B0_P7_U1_CFG18 EQU 0x40010ed2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG19 +CYDEV_UCFG_B0_P7_U1_CFG19 EQU 0x40010ed3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG20 +CYDEV_UCFG_B0_P7_U1_CFG20 EQU 0x40010ed4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG21 +CYDEV_UCFG_B0_P7_U1_CFG21 EQU 0x40010ed5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG22 +CYDEV_UCFG_B0_P7_U1_CFG22 EQU 0x40010ed6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG23 +CYDEV_UCFG_B0_P7_U1_CFG23 EQU 0x40010ed7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG24 +CYDEV_UCFG_B0_P7_U1_CFG24 EQU 0x40010ed8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG25 +CYDEV_UCFG_B0_P7_U1_CFG25 EQU 0x40010ed9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG26 +CYDEV_UCFG_B0_P7_U1_CFG26 EQU 0x40010eda + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG27 +CYDEV_UCFG_B0_P7_U1_CFG27 EQU 0x40010edb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG28 +CYDEV_UCFG_B0_P7_U1_CFG28 EQU 0x40010edc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG29 +CYDEV_UCFG_B0_P7_U1_CFG29 EQU 0x40010edd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG30 +CYDEV_UCFG_B0_P7_U1_CFG30 EQU 0x40010ede + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG31 +CYDEV_UCFG_B0_P7_U1_CFG31 EQU 0x40010edf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG0 +CYDEV_UCFG_B0_P7_U1_DCFG0 EQU 0x40010ee0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG1 +CYDEV_UCFG_B0_P7_U1_DCFG1 EQU 0x40010ee2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG2 +CYDEV_UCFG_B0_P7_U1_DCFG2 EQU 0x40010ee4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG3 +CYDEV_UCFG_B0_P7_U1_DCFG3 EQU 0x40010ee6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG4 +CYDEV_UCFG_B0_P7_U1_DCFG4 EQU 0x40010ee8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG5 +CYDEV_UCFG_B0_P7_U1_DCFG5 EQU 0x40010eea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG6 +CYDEV_UCFG_B0_P7_U1_DCFG6 EQU 0x40010eec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG7 +CYDEV_UCFG_B0_P7_U1_DCFG7 EQU 0x40010eee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_ROUTE_BASE +CYDEV_UCFG_B0_P7_ROUTE_BASE EQU 0x40010f00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_ROUTE_SIZE +CYDEV_UCFG_B0_P7_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_BASE +CYDEV_UCFG_B1_BASE EQU 0x40011000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_SIZE +CYDEV_UCFG_B1_SIZE EQU 0x00000fef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_BASE +CYDEV_UCFG_B1_P2_BASE EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_SIZE +CYDEV_UCFG_B1_P2_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_BASE +CYDEV_UCFG_B1_P2_U0_BASE EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_SIZE +CYDEV_UCFG_B1_P2_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT0 +CYDEV_UCFG_B1_P2_U0_PLD_IT0 EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT1 +CYDEV_UCFG_B1_P2_U0_PLD_IT1 EQU 0x40011404 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT2 +CYDEV_UCFG_B1_P2_U0_PLD_IT2 EQU 0x40011408 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT3 +CYDEV_UCFG_B1_P2_U0_PLD_IT3 EQU 0x4001140c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT4 +CYDEV_UCFG_B1_P2_U0_PLD_IT4 EQU 0x40011410 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT5 +CYDEV_UCFG_B1_P2_U0_PLD_IT5 EQU 0x40011414 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT6 +CYDEV_UCFG_B1_P2_U0_PLD_IT6 EQU 0x40011418 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT7 +CYDEV_UCFG_B1_P2_U0_PLD_IT7 EQU 0x4001141c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT8 +CYDEV_UCFG_B1_P2_U0_PLD_IT8 EQU 0x40011420 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT9 +CYDEV_UCFG_B1_P2_U0_PLD_IT9 EQU 0x40011424 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT10 +CYDEV_UCFG_B1_P2_U0_PLD_IT10 EQU 0x40011428 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT11 +CYDEV_UCFG_B1_P2_U0_PLD_IT11 EQU 0x4001142c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_ORT0 +CYDEV_UCFG_B1_P2_U0_PLD_ORT0 EQU 0x40011430 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_ORT1 +CYDEV_UCFG_B1_P2_U0_PLD_ORT1 EQU 0x40011432 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_ORT2 +CYDEV_UCFG_B1_P2_U0_PLD_ORT2 EQU 0x40011434 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_ORT3 +CYDEV_UCFG_B1_P2_U0_PLD_ORT3 EQU 0x40011436 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST EQU 0x40011438 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB +CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB EQU 0x4001143a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET EQU 0x4001143c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS +CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS EQU 0x4001143e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG0 +CYDEV_UCFG_B1_P2_U0_CFG0 EQU 0x40011440 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG1 +CYDEV_UCFG_B1_P2_U0_CFG1 EQU 0x40011441 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG2 +CYDEV_UCFG_B1_P2_U0_CFG2 EQU 0x40011442 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG3 +CYDEV_UCFG_B1_P2_U0_CFG3 EQU 0x40011443 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG4 +CYDEV_UCFG_B1_P2_U0_CFG4 EQU 0x40011444 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG5 +CYDEV_UCFG_B1_P2_U0_CFG5 EQU 0x40011445 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG6 +CYDEV_UCFG_B1_P2_U0_CFG6 EQU 0x40011446 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG7 +CYDEV_UCFG_B1_P2_U0_CFG7 EQU 0x40011447 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG8 +CYDEV_UCFG_B1_P2_U0_CFG8 EQU 0x40011448 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG9 +CYDEV_UCFG_B1_P2_U0_CFG9 EQU 0x40011449 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG10 +CYDEV_UCFG_B1_P2_U0_CFG10 EQU 0x4001144a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG11 +CYDEV_UCFG_B1_P2_U0_CFG11 EQU 0x4001144b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG12 +CYDEV_UCFG_B1_P2_U0_CFG12 EQU 0x4001144c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG13 +CYDEV_UCFG_B1_P2_U0_CFG13 EQU 0x4001144d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG14 +CYDEV_UCFG_B1_P2_U0_CFG14 EQU 0x4001144e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG15 +CYDEV_UCFG_B1_P2_U0_CFG15 EQU 0x4001144f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG16 +CYDEV_UCFG_B1_P2_U0_CFG16 EQU 0x40011450 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG17 +CYDEV_UCFG_B1_P2_U0_CFG17 EQU 0x40011451 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG18 +CYDEV_UCFG_B1_P2_U0_CFG18 EQU 0x40011452 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG19 +CYDEV_UCFG_B1_P2_U0_CFG19 EQU 0x40011453 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG20 +CYDEV_UCFG_B1_P2_U0_CFG20 EQU 0x40011454 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG21 +CYDEV_UCFG_B1_P2_U0_CFG21 EQU 0x40011455 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG22 +CYDEV_UCFG_B1_P2_U0_CFG22 EQU 0x40011456 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG23 +CYDEV_UCFG_B1_P2_U0_CFG23 EQU 0x40011457 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG24 +CYDEV_UCFG_B1_P2_U0_CFG24 EQU 0x40011458 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG25 +CYDEV_UCFG_B1_P2_U0_CFG25 EQU 0x40011459 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG26 +CYDEV_UCFG_B1_P2_U0_CFG26 EQU 0x4001145a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG27 +CYDEV_UCFG_B1_P2_U0_CFG27 EQU 0x4001145b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG28 +CYDEV_UCFG_B1_P2_U0_CFG28 EQU 0x4001145c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG29 +CYDEV_UCFG_B1_P2_U0_CFG29 EQU 0x4001145d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG30 +CYDEV_UCFG_B1_P2_U0_CFG30 EQU 0x4001145e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG31 +CYDEV_UCFG_B1_P2_U0_CFG31 EQU 0x4001145f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG0 +CYDEV_UCFG_B1_P2_U0_DCFG0 EQU 0x40011460 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG1 +CYDEV_UCFG_B1_P2_U0_DCFG1 EQU 0x40011462 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG2 +CYDEV_UCFG_B1_P2_U0_DCFG2 EQU 0x40011464 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG3 +CYDEV_UCFG_B1_P2_U0_DCFG3 EQU 0x40011466 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG4 +CYDEV_UCFG_B1_P2_U0_DCFG4 EQU 0x40011468 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG5 +CYDEV_UCFG_B1_P2_U0_DCFG5 EQU 0x4001146a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG6 +CYDEV_UCFG_B1_P2_U0_DCFG6 EQU 0x4001146c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG7 +CYDEV_UCFG_B1_P2_U0_DCFG7 EQU 0x4001146e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_BASE +CYDEV_UCFG_B1_P2_U1_BASE EQU 0x40011480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_SIZE +CYDEV_UCFG_B1_P2_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT0 +CYDEV_UCFG_B1_P2_U1_PLD_IT0 EQU 0x40011480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT1 +CYDEV_UCFG_B1_P2_U1_PLD_IT1 EQU 0x40011484 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT2 +CYDEV_UCFG_B1_P2_U1_PLD_IT2 EQU 0x40011488 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT3 +CYDEV_UCFG_B1_P2_U1_PLD_IT3 EQU 0x4001148c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT4 +CYDEV_UCFG_B1_P2_U1_PLD_IT4 EQU 0x40011490 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT5 +CYDEV_UCFG_B1_P2_U1_PLD_IT5 EQU 0x40011494 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT6 +CYDEV_UCFG_B1_P2_U1_PLD_IT6 EQU 0x40011498 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT7 +CYDEV_UCFG_B1_P2_U1_PLD_IT7 EQU 0x4001149c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT8 +CYDEV_UCFG_B1_P2_U1_PLD_IT8 EQU 0x400114a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT9 +CYDEV_UCFG_B1_P2_U1_PLD_IT9 EQU 0x400114a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT10 +CYDEV_UCFG_B1_P2_U1_PLD_IT10 EQU 0x400114a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT11 +CYDEV_UCFG_B1_P2_U1_PLD_IT11 EQU 0x400114ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_ORT0 +CYDEV_UCFG_B1_P2_U1_PLD_ORT0 EQU 0x400114b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_ORT1 +CYDEV_UCFG_B1_P2_U1_PLD_ORT1 EQU 0x400114b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_ORT2 +CYDEV_UCFG_B1_P2_U1_PLD_ORT2 EQU 0x400114b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_ORT3 +CYDEV_UCFG_B1_P2_U1_PLD_ORT3 EQU 0x400114b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST EQU 0x400114b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB +CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB EQU 0x400114ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET EQU 0x400114bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS +CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS EQU 0x400114be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG0 +CYDEV_UCFG_B1_P2_U1_CFG0 EQU 0x400114c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG1 +CYDEV_UCFG_B1_P2_U1_CFG1 EQU 0x400114c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG2 +CYDEV_UCFG_B1_P2_U1_CFG2 EQU 0x400114c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG3 +CYDEV_UCFG_B1_P2_U1_CFG3 EQU 0x400114c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG4 +CYDEV_UCFG_B1_P2_U1_CFG4 EQU 0x400114c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG5 +CYDEV_UCFG_B1_P2_U1_CFG5 EQU 0x400114c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG6 +CYDEV_UCFG_B1_P2_U1_CFG6 EQU 0x400114c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG7 +CYDEV_UCFG_B1_P2_U1_CFG7 EQU 0x400114c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG8 +CYDEV_UCFG_B1_P2_U1_CFG8 EQU 0x400114c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG9 +CYDEV_UCFG_B1_P2_U1_CFG9 EQU 0x400114c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG10 +CYDEV_UCFG_B1_P2_U1_CFG10 EQU 0x400114ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG11 +CYDEV_UCFG_B1_P2_U1_CFG11 EQU 0x400114cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG12 +CYDEV_UCFG_B1_P2_U1_CFG12 EQU 0x400114cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG13 +CYDEV_UCFG_B1_P2_U1_CFG13 EQU 0x400114cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG14 +CYDEV_UCFG_B1_P2_U1_CFG14 EQU 0x400114ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG15 +CYDEV_UCFG_B1_P2_U1_CFG15 EQU 0x400114cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG16 +CYDEV_UCFG_B1_P2_U1_CFG16 EQU 0x400114d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG17 +CYDEV_UCFG_B1_P2_U1_CFG17 EQU 0x400114d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG18 +CYDEV_UCFG_B1_P2_U1_CFG18 EQU 0x400114d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG19 +CYDEV_UCFG_B1_P2_U1_CFG19 EQU 0x400114d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG20 +CYDEV_UCFG_B1_P2_U1_CFG20 EQU 0x400114d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG21 +CYDEV_UCFG_B1_P2_U1_CFG21 EQU 0x400114d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG22 +CYDEV_UCFG_B1_P2_U1_CFG22 EQU 0x400114d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG23 +CYDEV_UCFG_B1_P2_U1_CFG23 EQU 0x400114d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG24 +CYDEV_UCFG_B1_P2_U1_CFG24 EQU 0x400114d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG25 +CYDEV_UCFG_B1_P2_U1_CFG25 EQU 0x400114d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG26 +CYDEV_UCFG_B1_P2_U1_CFG26 EQU 0x400114da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG27 +CYDEV_UCFG_B1_P2_U1_CFG27 EQU 0x400114db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG28 +CYDEV_UCFG_B1_P2_U1_CFG28 EQU 0x400114dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG29 +CYDEV_UCFG_B1_P2_U1_CFG29 EQU 0x400114dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG30 +CYDEV_UCFG_B1_P2_U1_CFG30 EQU 0x400114de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG31 +CYDEV_UCFG_B1_P2_U1_CFG31 EQU 0x400114df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG0 +CYDEV_UCFG_B1_P2_U1_DCFG0 EQU 0x400114e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG1 +CYDEV_UCFG_B1_P2_U1_DCFG1 EQU 0x400114e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG2 +CYDEV_UCFG_B1_P2_U1_DCFG2 EQU 0x400114e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG3 +CYDEV_UCFG_B1_P2_U1_DCFG3 EQU 0x400114e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG4 +CYDEV_UCFG_B1_P2_U1_DCFG4 EQU 0x400114e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG5 +CYDEV_UCFG_B1_P2_U1_DCFG5 EQU 0x400114ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG6 +CYDEV_UCFG_B1_P2_U1_DCFG6 EQU 0x400114ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG7 +CYDEV_UCFG_B1_P2_U1_DCFG7 EQU 0x400114ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_ROUTE_BASE +CYDEV_UCFG_B1_P2_ROUTE_BASE EQU 0x40011500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_ROUTE_SIZE +CYDEV_UCFG_B1_P2_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_BASE +CYDEV_UCFG_B1_P3_BASE EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_SIZE +CYDEV_UCFG_B1_P3_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_BASE +CYDEV_UCFG_B1_P3_U0_BASE EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_SIZE +CYDEV_UCFG_B1_P3_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT0 +CYDEV_UCFG_B1_P3_U0_PLD_IT0 EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT1 +CYDEV_UCFG_B1_P3_U0_PLD_IT1 EQU 0x40011604 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT2 +CYDEV_UCFG_B1_P3_U0_PLD_IT2 EQU 0x40011608 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT3 +CYDEV_UCFG_B1_P3_U0_PLD_IT3 EQU 0x4001160c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT4 +CYDEV_UCFG_B1_P3_U0_PLD_IT4 EQU 0x40011610 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT5 +CYDEV_UCFG_B1_P3_U0_PLD_IT5 EQU 0x40011614 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT6 +CYDEV_UCFG_B1_P3_U0_PLD_IT6 EQU 0x40011618 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT7 +CYDEV_UCFG_B1_P3_U0_PLD_IT7 EQU 0x4001161c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT8 +CYDEV_UCFG_B1_P3_U0_PLD_IT8 EQU 0x40011620 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT9 +CYDEV_UCFG_B1_P3_U0_PLD_IT9 EQU 0x40011624 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT10 +CYDEV_UCFG_B1_P3_U0_PLD_IT10 EQU 0x40011628 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT11 +CYDEV_UCFG_B1_P3_U0_PLD_IT11 EQU 0x4001162c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_ORT0 +CYDEV_UCFG_B1_P3_U0_PLD_ORT0 EQU 0x40011630 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_ORT1 +CYDEV_UCFG_B1_P3_U0_PLD_ORT1 EQU 0x40011632 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_ORT2 +CYDEV_UCFG_B1_P3_U0_PLD_ORT2 EQU 0x40011634 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_ORT3 +CYDEV_UCFG_B1_P3_U0_PLD_ORT3 EQU 0x40011636 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST EQU 0x40011638 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB +CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB EQU 0x4001163a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET EQU 0x4001163c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS +CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS EQU 0x4001163e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG0 +CYDEV_UCFG_B1_P3_U0_CFG0 EQU 0x40011640 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG1 +CYDEV_UCFG_B1_P3_U0_CFG1 EQU 0x40011641 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG2 +CYDEV_UCFG_B1_P3_U0_CFG2 EQU 0x40011642 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG3 +CYDEV_UCFG_B1_P3_U0_CFG3 EQU 0x40011643 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG4 +CYDEV_UCFG_B1_P3_U0_CFG4 EQU 0x40011644 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG5 +CYDEV_UCFG_B1_P3_U0_CFG5 EQU 0x40011645 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG6 +CYDEV_UCFG_B1_P3_U0_CFG6 EQU 0x40011646 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG7 +CYDEV_UCFG_B1_P3_U0_CFG7 EQU 0x40011647 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG8 +CYDEV_UCFG_B1_P3_U0_CFG8 EQU 0x40011648 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG9 +CYDEV_UCFG_B1_P3_U0_CFG9 EQU 0x40011649 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG10 +CYDEV_UCFG_B1_P3_U0_CFG10 EQU 0x4001164a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG11 +CYDEV_UCFG_B1_P3_U0_CFG11 EQU 0x4001164b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG12 +CYDEV_UCFG_B1_P3_U0_CFG12 EQU 0x4001164c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG13 +CYDEV_UCFG_B1_P3_U0_CFG13 EQU 0x4001164d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG14 +CYDEV_UCFG_B1_P3_U0_CFG14 EQU 0x4001164e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG15 +CYDEV_UCFG_B1_P3_U0_CFG15 EQU 0x4001164f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG16 +CYDEV_UCFG_B1_P3_U0_CFG16 EQU 0x40011650 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG17 +CYDEV_UCFG_B1_P3_U0_CFG17 EQU 0x40011651 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG18 +CYDEV_UCFG_B1_P3_U0_CFG18 EQU 0x40011652 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG19 +CYDEV_UCFG_B1_P3_U0_CFG19 EQU 0x40011653 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG20 +CYDEV_UCFG_B1_P3_U0_CFG20 EQU 0x40011654 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG21 +CYDEV_UCFG_B1_P3_U0_CFG21 EQU 0x40011655 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG22 +CYDEV_UCFG_B1_P3_U0_CFG22 EQU 0x40011656 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG23 +CYDEV_UCFG_B1_P3_U0_CFG23 EQU 0x40011657 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG24 +CYDEV_UCFG_B1_P3_U0_CFG24 EQU 0x40011658 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG25 +CYDEV_UCFG_B1_P3_U0_CFG25 EQU 0x40011659 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG26 +CYDEV_UCFG_B1_P3_U0_CFG26 EQU 0x4001165a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG27 +CYDEV_UCFG_B1_P3_U0_CFG27 EQU 0x4001165b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG28 +CYDEV_UCFG_B1_P3_U0_CFG28 EQU 0x4001165c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG29 +CYDEV_UCFG_B1_P3_U0_CFG29 EQU 0x4001165d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG30 +CYDEV_UCFG_B1_P3_U0_CFG30 EQU 0x4001165e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG31 +CYDEV_UCFG_B1_P3_U0_CFG31 EQU 0x4001165f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG0 +CYDEV_UCFG_B1_P3_U0_DCFG0 EQU 0x40011660 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG1 +CYDEV_UCFG_B1_P3_U0_DCFG1 EQU 0x40011662 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG2 +CYDEV_UCFG_B1_P3_U0_DCFG2 EQU 0x40011664 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG3 +CYDEV_UCFG_B1_P3_U0_DCFG3 EQU 0x40011666 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG4 +CYDEV_UCFG_B1_P3_U0_DCFG4 EQU 0x40011668 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG5 +CYDEV_UCFG_B1_P3_U0_DCFG5 EQU 0x4001166a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG6 +CYDEV_UCFG_B1_P3_U0_DCFG6 EQU 0x4001166c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG7 +CYDEV_UCFG_B1_P3_U0_DCFG7 EQU 0x4001166e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_BASE +CYDEV_UCFG_B1_P3_U1_BASE EQU 0x40011680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_SIZE +CYDEV_UCFG_B1_P3_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT0 +CYDEV_UCFG_B1_P3_U1_PLD_IT0 EQU 0x40011680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT1 +CYDEV_UCFG_B1_P3_U1_PLD_IT1 EQU 0x40011684 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT2 +CYDEV_UCFG_B1_P3_U1_PLD_IT2 EQU 0x40011688 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT3 +CYDEV_UCFG_B1_P3_U1_PLD_IT3 EQU 0x4001168c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT4 +CYDEV_UCFG_B1_P3_U1_PLD_IT4 EQU 0x40011690 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT5 +CYDEV_UCFG_B1_P3_U1_PLD_IT5 EQU 0x40011694 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT6 +CYDEV_UCFG_B1_P3_U1_PLD_IT6 EQU 0x40011698 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT7 +CYDEV_UCFG_B1_P3_U1_PLD_IT7 EQU 0x4001169c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT8 +CYDEV_UCFG_B1_P3_U1_PLD_IT8 EQU 0x400116a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT9 +CYDEV_UCFG_B1_P3_U1_PLD_IT9 EQU 0x400116a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT10 +CYDEV_UCFG_B1_P3_U1_PLD_IT10 EQU 0x400116a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT11 +CYDEV_UCFG_B1_P3_U1_PLD_IT11 EQU 0x400116ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_ORT0 +CYDEV_UCFG_B1_P3_U1_PLD_ORT0 EQU 0x400116b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_ORT1 +CYDEV_UCFG_B1_P3_U1_PLD_ORT1 EQU 0x400116b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_ORT2 +CYDEV_UCFG_B1_P3_U1_PLD_ORT2 EQU 0x400116b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_ORT3 +CYDEV_UCFG_B1_P3_U1_PLD_ORT3 EQU 0x400116b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST EQU 0x400116b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB +CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB EQU 0x400116ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET EQU 0x400116bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS +CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS EQU 0x400116be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG0 +CYDEV_UCFG_B1_P3_U1_CFG0 EQU 0x400116c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG1 +CYDEV_UCFG_B1_P3_U1_CFG1 EQU 0x400116c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG2 +CYDEV_UCFG_B1_P3_U1_CFG2 EQU 0x400116c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG3 +CYDEV_UCFG_B1_P3_U1_CFG3 EQU 0x400116c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG4 +CYDEV_UCFG_B1_P3_U1_CFG4 EQU 0x400116c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG5 +CYDEV_UCFG_B1_P3_U1_CFG5 EQU 0x400116c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG6 +CYDEV_UCFG_B1_P3_U1_CFG6 EQU 0x400116c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG7 +CYDEV_UCFG_B1_P3_U1_CFG7 EQU 0x400116c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG8 +CYDEV_UCFG_B1_P3_U1_CFG8 EQU 0x400116c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG9 +CYDEV_UCFG_B1_P3_U1_CFG9 EQU 0x400116c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG10 +CYDEV_UCFG_B1_P3_U1_CFG10 EQU 0x400116ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG11 +CYDEV_UCFG_B1_P3_U1_CFG11 EQU 0x400116cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG12 +CYDEV_UCFG_B1_P3_U1_CFG12 EQU 0x400116cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG13 +CYDEV_UCFG_B1_P3_U1_CFG13 EQU 0x400116cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG14 +CYDEV_UCFG_B1_P3_U1_CFG14 EQU 0x400116ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG15 +CYDEV_UCFG_B1_P3_U1_CFG15 EQU 0x400116cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG16 +CYDEV_UCFG_B1_P3_U1_CFG16 EQU 0x400116d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG17 +CYDEV_UCFG_B1_P3_U1_CFG17 EQU 0x400116d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG18 +CYDEV_UCFG_B1_P3_U1_CFG18 EQU 0x400116d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG19 +CYDEV_UCFG_B1_P3_U1_CFG19 EQU 0x400116d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG20 +CYDEV_UCFG_B1_P3_U1_CFG20 EQU 0x400116d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG21 +CYDEV_UCFG_B1_P3_U1_CFG21 EQU 0x400116d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG22 +CYDEV_UCFG_B1_P3_U1_CFG22 EQU 0x400116d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG23 +CYDEV_UCFG_B1_P3_U1_CFG23 EQU 0x400116d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG24 +CYDEV_UCFG_B1_P3_U1_CFG24 EQU 0x400116d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG25 +CYDEV_UCFG_B1_P3_U1_CFG25 EQU 0x400116d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG26 +CYDEV_UCFG_B1_P3_U1_CFG26 EQU 0x400116da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG27 +CYDEV_UCFG_B1_P3_U1_CFG27 EQU 0x400116db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG28 +CYDEV_UCFG_B1_P3_U1_CFG28 EQU 0x400116dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG29 +CYDEV_UCFG_B1_P3_U1_CFG29 EQU 0x400116dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG30 +CYDEV_UCFG_B1_P3_U1_CFG30 EQU 0x400116de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG31 +CYDEV_UCFG_B1_P3_U1_CFG31 EQU 0x400116df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG0 +CYDEV_UCFG_B1_P3_U1_DCFG0 EQU 0x400116e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG1 +CYDEV_UCFG_B1_P3_U1_DCFG1 EQU 0x400116e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG2 +CYDEV_UCFG_B1_P3_U1_DCFG2 EQU 0x400116e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG3 +CYDEV_UCFG_B1_P3_U1_DCFG3 EQU 0x400116e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG4 +CYDEV_UCFG_B1_P3_U1_DCFG4 EQU 0x400116e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG5 +CYDEV_UCFG_B1_P3_U1_DCFG5 EQU 0x400116ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG6 +CYDEV_UCFG_B1_P3_U1_DCFG6 EQU 0x400116ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG7 +CYDEV_UCFG_B1_P3_U1_DCFG7 EQU 0x400116ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_ROUTE_BASE +CYDEV_UCFG_B1_P3_ROUTE_BASE EQU 0x40011700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_ROUTE_SIZE +CYDEV_UCFG_B1_P3_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_BASE +CYDEV_UCFG_B1_P4_BASE EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_SIZE +CYDEV_UCFG_B1_P4_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_BASE +CYDEV_UCFG_B1_P4_U0_BASE EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_SIZE +CYDEV_UCFG_B1_P4_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT0 +CYDEV_UCFG_B1_P4_U0_PLD_IT0 EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT1 +CYDEV_UCFG_B1_P4_U0_PLD_IT1 EQU 0x40011804 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT2 +CYDEV_UCFG_B1_P4_U0_PLD_IT2 EQU 0x40011808 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT3 +CYDEV_UCFG_B1_P4_U0_PLD_IT3 EQU 0x4001180c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT4 +CYDEV_UCFG_B1_P4_U0_PLD_IT4 EQU 0x40011810 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT5 +CYDEV_UCFG_B1_P4_U0_PLD_IT5 EQU 0x40011814 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT6 +CYDEV_UCFG_B1_P4_U0_PLD_IT6 EQU 0x40011818 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT7 +CYDEV_UCFG_B1_P4_U0_PLD_IT7 EQU 0x4001181c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT8 +CYDEV_UCFG_B1_P4_U0_PLD_IT8 EQU 0x40011820 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT9 +CYDEV_UCFG_B1_P4_U0_PLD_IT9 EQU 0x40011824 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT10 +CYDEV_UCFG_B1_P4_U0_PLD_IT10 EQU 0x40011828 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT11 +CYDEV_UCFG_B1_P4_U0_PLD_IT11 EQU 0x4001182c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_ORT0 +CYDEV_UCFG_B1_P4_U0_PLD_ORT0 EQU 0x40011830 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_ORT1 +CYDEV_UCFG_B1_P4_U0_PLD_ORT1 EQU 0x40011832 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_ORT2 +CYDEV_UCFG_B1_P4_U0_PLD_ORT2 EQU 0x40011834 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_ORT3 +CYDEV_UCFG_B1_P4_U0_PLD_ORT3 EQU 0x40011836 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST EQU 0x40011838 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB +CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB EQU 0x4001183a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET EQU 0x4001183c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS +CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS EQU 0x4001183e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG0 +CYDEV_UCFG_B1_P4_U0_CFG0 EQU 0x40011840 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG1 +CYDEV_UCFG_B1_P4_U0_CFG1 EQU 0x40011841 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG2 +CYDEV_UCFG_B1_P4_U0_CFG2 EQU 0x40011842 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG3 +CYDEV_UCFG_B1_P4_U0_CFG3 EQU 0x40011843 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG4 +CYDEV_UCFG_B1_P4_U0_CFG4 EQU 0x40011844 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG5 +CYDEV_UCFG_B1_P4_U0_CFG5 EQU 0x40011845 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG6 +CYDEV_UCFG_B1_P4_U0_CFG6 EQU 0x40011846 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG7 +CYDEV_UCFG_B1_P4_U0_CFG7 EQU 0x40011847 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG8 +CYDEV_UCFG_B1_P4_U0_CFG8 EQU 0x40011848 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG9 +CYDEV_UCFG_B1_P4_U0_CFG9 EQU 0x40011849 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG10 +CYDEV_UCFG_B1_P4_U0_CFG10 EQU 0x4001184a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG11 +CYDEV_UCFG_B1_P4_U0_CFG11 EQU 0x4001184b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG12 +CYDEV_UCFG_B1_P4_U0_CFG12 EQU 0x4001184c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG13 +CYDEV_UCFG_B1_P4_U0_CFG13 EQU 0x4001184d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG14 +CYDEV_UCFG_B1_P4_U0_CFG14 EQU 0x4001184e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG15 +CYDEV_UCFG_B1_P4_U0_CFG15 EQU 0x4001184f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG16 +CYDEV_UCFG_B1_P4_U0_CFG16 EQU 0x40011850 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG17 +CYDEV_UCFG_B1_P4_U0_CFG17 EQU 0x40011851 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG18 +CYDEV_UCFG_B1_P4_U0_CFG18 EQU 0x40011852 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG19 +CYDEV_UCFG_B1_P4_U0_CFG19 EQU 0x40011853 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG20 +CYDEV_UCFG_B1_P4_U0_CFG20 EQU 0x40011854 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG21 +CYDEV_UCFG_B1_P4_U0_CFG21 EQU 0x40011855 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG22 +CYDEV_UCFG_B1_P4_U0_CFG22 EQU 0x40011856 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG23 +CYDEV_UCFG_B1_P4_U0_CFG23 EQU 0x40011857 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG24 +CYDEV_UCFG_B1_P4_U0_CFG24 EQU 0x40011858 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG25 +CYDEV_UCFG_B1_P4_U0_CFG25 EQU 0x40011859 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG26 +CYDEV_UCFG_B1_P4_U0_CFG26 EQU 0x4001185a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG27 +CYDEV_UCFG_B1_P4_U0_CFG27 EQU 0x4001185b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG28 +CYDEV_UCFG_B1_P4_U0_CFG28 EQU 0x4001185c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG29 +CYDEV_UCFG_B1_P4_U0_CFG29 EQU 0x4001185d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG30 +CYDEV_UCFG_B1_P4_U0_CFG30 EQU 0x4001185e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG31 +CYDEV_UCFG_B1_P4_U0_CFG31 EQU 0x4001185f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG0 +CYDEV_UCFG_B1_P4_U0_DCFG0 EQU 0x40011860 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG1 +CYDEV_UCFG_B1_P4_U0_DCFG1 EQU 0x40011862 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG2 +CYDEV_UCFG_B1_P4_U0_DCFG2 EQU 0x40011864 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG3 +CYDEV_UCFG_B1_P4_U0_DCFG3 EQU 0x40011866 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG4 +CYDEV_UCFG_B1_P4_U0_DCFG4 EQU 0x40011868 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG5 +CYDEV_UCFG_B1_P4_U0_DCFG5 EQU 0x4001186a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG6 +CYDEV_UCFG_B1_P4_U0_DCFG6 EQU 0x4001186c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG7 +CYDEV_UCFG_B1_P4_U0_DCFG7 EQU 0x4001186e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_BASE +CYDEV_UCFG_B1_P4_U1_BASE EQU 0x40011880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_SIZE +CYDEV_UCFG_B1_P4_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT0 +CYDEV_UCFG_B1_P4_U1_PLD_IT0 EQU 0x40011880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT1 +CYDEV_UCFG_B1_P4_U1_PLD_IT1 EQU 0x40011884 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT2 +CYDEV_UCFG_B1_P4_U1_PLD_IT2 EQU 0x40011888 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT3 +CYDEV_UCFG_B1_P4_U1_PLD_IT3 EQU 0x4001188c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT4 +CYDEV_UCFG_B1_P4_U1_PLD_IT4 EQU 0x40011890 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT5 +CYDEV_UCFG_B1_P4_U1_PLD_IT5 EQU 0x40011894 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT6 +CYDEV_UCFG_B1_P4_U1_PLD_IT6 EQU 0x40011898 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT7 +CYDEV_UCFG_B1_P4_U1_PLD_IT7 EQU 0x4001189c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT8 +CYDEV_UCFG_B1_P4_U1_PLD_IT8 EQU 0x400118a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT9 +CYDEV_UCFG_B1_P4_U1_PLD_IT9 EQU 0x400118a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT10 +CYDEV_UCFG_B1_P4_U1_PLD_IT10 EQU 0x400118a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT11 +CYDEV_UCFG_B1_P4_U1_PLD_IT11 EQU 0x400118ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_ORT0 +CYDEV_UCFG_B1_P4_U1_PLD_ORT0 EQU 0x400118b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_ORT1 +CYDEV_UCFG_B1_P4_U1_PLD_ORT1 EQU 0x400118b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_ORT2 +CYDEV_UCFG_B1_P4_U1_PLD_ORT2 EQU 0x400118b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_ORT3 +CYDEV_UCFG_B1_P4_U1_PLD_ORT3 EQU 0x400118b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST EQU 0x400118b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB +CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB EQU 0x400118ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET EQU 0x400118bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS +CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS EQU 0x400118be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG0 +CYDEV_UCFG_B1_P4_U1_CFG0 EQU 0x400118c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG1 +CYDEV_UCFG_B1_P4_U1_CFG1 EQU 0x400118c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG2 +CYDEV_UCFG_B1_P4_U1_CFG2 EQU 0x400118c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG3 +CYDEV_UCFG_B1_P4_U1_CFG3 EQU 0x400118c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG4 +CYDEV_UCFG_B1_P4_U1_CFG4 EQU 0x400118c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG5 +CYDEV_UCFG_B1_P4_U1_CFG5 EQU 0x400118c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG6 +CYDEV_UCFG_B1_P4_U1_CFG6 EQU 0x400118c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG7 +CYDEV_UCFG_B1_P4_U1_CFG7 EQU 0x400118c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG8 +CYDEV_UCFG_B1_P4_U1_CFG8 EQU 0x400118c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG9 +CYDEV_UCFG_B1_P4_U1_CFG9 EQU 0x400118c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG10 +CYDEV_UCFG_B1_P4_U1_CFG10 EQU 0x400118ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG11 +CYDEV_UCFG_B1_P4_U1_CFG11 EQU 0x400118cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG12 +CYDEV_UCFG_B1_P4_U1_CFG12 EQU 0x400118cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG13 +CYDEV_UCFG_B1_P4_U1_CFG13 EQU 0x400118cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG14 +CYDEV_UCFG_B1_P4_U1_CFG14 EQU 0x400118ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG15 +CYDEV_UCFG_B1_P4_U1_CFG15 EQU 0x400118cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG16 +CYDEV_UCFG_B1_P4_U1_CFG16 EQU 0x400118d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG17 +CYDEV_UCFG_B1_P4_U1_CFG17 EQU 0x400118d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG18 +CYDEV_UCFG_B1_P4_U1_CFG18 EQU 0x400118d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG19 +CYDEV_UCFG_B1_P4_U1_CFG19 EQU 0x400118d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG20 +CYDEV_UCFG_B1_P4_U1_CFG20 EQU 0x400118d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG21 +CYDEV_UCFG_B1_P4_U1_CFG21 EQU 0x400118d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG22 +CYDEV_UCFG_B1_P4_U1_CFG22 EQU 0x400118d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG23 +CYDEV_UCFG_B1_P4_U1_CFG23 EQU 0x400118d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG24 +CYDEV_UCFG_B1_P4_U1_CFG24 EQU 0x400118d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG25 +CYDEV_UCFG_B1_P4_U1_CFG25 EQU 0x400118d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG26 +CYDEV_UCFG_B1_P4_U1_CFG26 EQU 0x400118da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG27 +CYDEV_UCFG_B1_P4_U1_CFG27 EQU 0x400118db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG28 +CYDEV_UCFG_B1_P4_U1_CFG28 EQU 0x400118dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG29 +CYDEV_UCFG_B1_P4_U1_CFG29 EQU 0x400118dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG30 +CYDEV_UCFG_B1_P4_U1_CFG30 EQU 0x400118de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG31 +CYDEV_UCFG_B1_P4_U1_CFG31 EQU 0x400118df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG0 +CYDEV_UCFG_B1_P4_U1_DCFG0 EQU 0x400118e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG1 +CYDEV_UCFG_B1_P4_U1_DCFG1 EQU 0x400118e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG2 +CYDEV_UCFG_B1_P4_U1_DCFG2 EQU 0x400118e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG3 +CYDEV_UCFG_B1_P4_U1_DCFG3 EQU 0x400118e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG4 +CYDEV_UCFG_B1_P4_U1_DCFG4 EQU 0x400118e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG5 +CYDEV_UCFG_B1_P4_U1_DCFG5 EQU 0x400118ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG6 +CYDEV_UCFG_B1_P4_U1_DCFG6 EQU 0x400118ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG7 +CYDEV_UCFG_B1_P4_U1_DCFG7 EQU 0x400118ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_ROUTE_BASE +CYDEV_UCFG_B1_P4_ROUTE_BASE EQU 0x40011900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_ROUTE_SIZE +CYDEV_UCFG_B1_P4_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_BASE +CYDEV_UCFG_B1_P5_BASE EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_SIZE +CYDEV_UCFG_B1_P5_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_BASE +CYDEV_UCFG_B1_P5_U0_BASE EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_SIZE +CYDEV_UCFG_B1_P5_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT0 +CYDEV_UCFG_B1_P5_U0_PLD_IT0 EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT1 +CYDEV_UCFG_B1_P5_U0_PLD_IT1 EQU 0x40011a04 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT2 +CYDEV_UCFG_B1_P5_U0_PLD_IT2 EQU 0x40011a08 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT3 +CYDEV_UCFG_B1_P5_U0_PLD_IT3 EQU 0x40011a0c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT4 +CYDEV_UCFG_B1_P5_U0_PLD_IT4 EQU 0x40011a10 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT5 +CYDEV_UCFG_B1_P5_U0_PLD_IT5 EQU 0x40011a14 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT6 +CYDEV_UCFG_B1_P5_U0_PLD_IT6 EQU 0x40011a18 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT7 +CYDEV_UCFG_B1_P5_U0_PLD_IT7 EQU 0x40011a1c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT8 +CYDEV_UCFG_B1_P5_U0_PLD_IT8 EQU 0x40011a20 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT9 +CYDEV_UCFG_B1_P5_U0_PLD_IT9 EQU 0x40011a24 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT10 +CYDEV_UCFG_B1_P5_U0_PLD_IT10 EQU 0x40011a28 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT11 +CYDEV_UCFG_B1_P5_U0_PLD_IT11 EQU 0x40011a2c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_ORT0 +CYDEV_UCFG_B1_P5_U0_PLD_ORT0 EQU 0x40011a30 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_ORT1 +CYDEV_UCFG_B1_P5_U0_PLD_ORT1 EQU 0x40011a32 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_ORT2 +CYDEV_UCFG_B1_P5_U0_PLD_ORT2 EQU 0x40011a34 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_ORT3 +CYDEV_UCFG_B1_P5_U0_PLD_ORT3 EQU 0x40011a36 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST EQU 0x40011a38 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB +CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB EQU 0x40011a3a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET EQU 0x40011a3c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS +CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS EQU 0x40011a3e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG0 +CYDEV_UCFG_B1_P5_U0_CFG0 EQU 0x40011a40 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG1 +CYDEV_UCFG_B1_P5_U0_CFG1 EQU 0x40011a41 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG2 +CYDEV_UCFG_B1_P5_U0_CFG2 EQU 0x40011a42 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG3 +CYDEV_UCFG_B1_P5_U0_CFG3 EQU 0x40011a43 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG4 +CYDEV_UCFG_B1_P5_U0_CFG4 EQU 0x40011a44 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG5 +CYDEV_UCFG_B1_P5_U0_CFG5 EQU 0x40011a45 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG6 +CYDEV_UCFG_B1_P5_U0_CFG6 EQU 0x40011a46 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG7 +CYDEV_UCFG_B1_P5_U0_CFG7 EQU 0x40011a47 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG8 +CYDEV_UCFG_B1_P5_U0_CFG8 EQU 0x40011a48 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG9 +CYDEV_UCFG_B1_P5_U0_CFG9 EQU 0x40011a49 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG10 +CYDEV_UCFG_B1_P5_U0_CFG10 EQU 0x40011a4a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG11 +CYDEV_UCFG_B1_P5_U0_CFG11 EQU 0x40011a4b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG12 +CYDEV_UCFG_B1_P5_U0_CFG12 EQU 0x40011a4c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG13 +CYDEV_UCFG_B1_P5_U0_CFG13 EQU 0x40011a4d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG14 +CYDEV_UCFG_B1_P5_U0_CFG14 EQU 0x40011a4e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG15 +CYDEV_UCFG_B1_P5_U0_CFG15 EQU 0x40011a4f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG16 +CYDEV_UCFG_B1_P5_U0_CFG16 EQU 0x40011a50 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG17 +CYDEV_UCFG_B1_P5_U0_CFG17 EQU 0x40011a51 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG18 +CYDEV_UCFG_B1_P5_U0_CFG18 EQU 0x40011a52 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG19 +CYDEV_UCFG_B1_P5_U0_CFG19 EQU 0x40011a53 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG20 +CYDEV_UCFG_B1_P5_U0_CFG20 EQU 0x40011a54 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG21 +CYDEV_UCFG_B1_P5_U0_CFG21 EQU 0x40011a55 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG22 +CYDEV_UCFG_B1_P5_U0_CFG22 EQU 0x40011a56 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG23 +CYDEV_UCFG_B1_P5_U0_CFG23 EQU 0x40011a57 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG24 +CYDEV_UCFG_B1_P5_U0_CFG24 EQU 0x40011a58 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG25 +CYDEV_UCFG_B1_P5_U0_CFG25 EQU 0x40011a59 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG26 +CYDEV_UCFG_B1_P5_U0_CFG26 EQU 0x40011a5a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG27 +CYDEV_UCFG_B1_P5_U0_CFG27 EQU 0x40011a5b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG28 +CYDEV_UCFG_B1_P5_U0_CFG28 EQU 0x40011a5c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG29 +CYDEV_UCFG_B1_P5_U0_CFG29 EQU 0x40011a5d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG30 +CYDEV_UCFG_B1_P5_U0_CFG30 EQU 0x40011a5e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG31 +CYDEV_UCFG_B1_P5_U0_CFG31 EQU 0x40011a5f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG0 +CYDEV_UCFG_B1_P5_U0_DCFG0 EQU 0x40011a60 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG1 +CYDEV_UCFG_B1_P5_U0_DCFG1 EQU 0x40011a62 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG2 +CYDEV_UCFG_B1_P5_U0_DCFG2 EQU 0x40011a64 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG3 +CYDEV_UCFG_B1_P5_U0_DCFG3 EQU 0x40011a66 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG4 +CYDEV_UCFG_B1_P5_U0_DCFG4 EQU 0x40011a68 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG5 +CYDEV_UCFG_B1_P5_U0_DCFG5 EQU 0x40011a6a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG6 +CYDEV_UCFG_B1_P5_U0_DCFG6 EQU 0x40011a6c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG7 +CYDEV_UCFG_B1_P5_U0_DCFG7 EQU 0x40011a6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_BASE +CYDEV_UCFG_B1_P5_U1_BASE EQU 0x40011a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_SIZE +CYDEV_UCFG_B1_P5_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT0 +CYDEV_UCFG_B1_P5_U1_PLD_IT0 EQU 0x40011a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT1 +CYDEV_UCFG_B1_P5_U1_PLD_IT1 EQU 0x40011a84 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT2 +CYDEV_UCFG_B1_P5_U1_PLD_IT2 EQU 0x40011a88 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT3 +CYDEV_UCFG_B1_P5_U1_PLD_IT3 EQU 0x40011a8c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT4 +CYDEV_UCFG_B1_P5_U1_PLD_IT4 EQU 0x40011a90 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT5 +CYDEV_UCFG_B1_P5_U1_PLD_IT5 EQU 0x40011a94 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT6 +CYDEV_UCFG_B1_P5_U1_PLD_IT6 EQU 0x40011a98 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT7 +CYDEV_UCFG_B1_P5_U1_PLD_IT7 EQU 0x40011a9c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT8 +CYDEV_UCFG_B1_P5_U1_PLD_IT8 EQU 0x40011aa0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT9 +CYDEV_UCFG_B1_P5_U1_PLD_IT9 EQU 0x40011aa4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT10 +CYDEV_UCFG_B1_P5_U1_PLD_IT10 EQU 0x40011aa8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT11 +CYDEV_UCFG_B1_P5_U1_PLD_IT11 EQU 0x40011aac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_ORT0 +CYDEV_UCFG_B1_P5_U1_PLD_ORT0 EQU 0x40011ab0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_ORT1 +CYDEV_UCFG_B1_P5_U1_PLD_ORT1 EQU 0x40011ab2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_ORT2 +CYDEV_UCFG_B1_P5_U1_PLD_ORT2 EQU 0x40011ab4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_ORT3 +CYDEV_UCFG_B1_P5_U1_PLD_ORT3 EQU 0x40011ab6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST EQU 0x40011ab8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB +CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB EQU 0x40011aba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET EQU 0x40011abc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS +CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS EQU 0x40011abe + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG0 +CYDEV_UCFG_B1_P5_U1_CFG0 EQU 0x40011ac0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG1 +CYDEV_UCFG_B1_P5_U1_CFG1 EQU 0x40011ac1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG2 +CYDEV_UCFG_B1_P5_U1_CFG2 EQU 0x40011ac2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG3 +CYDEV_UCFG_B1_P5_U1_CFG3 EQU 0x40011ac3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG4 +CYDEV_UCFG_B1_P5_U1_CFG4 EQU 0x40011ac4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG5 +CYDEV_UCFG_B1_P5_U1_CFG5 EQU 0x40011ac5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG6 +CYDEV_UCFG_B1_P5_U1_CFG6 EQU 0x40011ac6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG7 +CYDEV_UCFG_B1_P5_U1_CFG7 EQU 0x40011ac7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG8 +CYDEV_UCFG_B1_P5_U1_CFG8 EQU 0x40011ac8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG9 +CYDEV_UCFG_B1_P5_U1_CFG9 EQU 0x40011ac9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG10 +CYDEV_UCFG_B1_P5_U1_CFG10 EQU 0x40011aca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG11 +CYDEV_UCFG_B1_P5_U1_CFG11 EQU 0x40011acb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG12 +CYDEV_UCFG_B1_P5_U1_CFG12 EQU 0x40011acc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG13 +CYDEV_UCFG_B1_P5_U1_CFG13 EQU 0x40011acd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG14 +CYDEV_UCFG_B1_P5_U1_CFG14 EQU 0x40011ace + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG15 +CYDEV_UCFG_B1_P5_U1_CFG15 EQU 0x40011acf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG16 +CYDEV_UCFG_B1_P5_U1_CFG16 EQU 0x40011ad0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG17 +CYDEV_UCFG_B1_P5_U1_CFG17 EQU 0x40011ad1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG18 +CYDEV_UCFG_B1_P5_U1_CFG18 EQU 0x40011ad2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG19 +CYDEV_UCFG_B1_P5_U1_CFG19 EQU 0x40011ad3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG20 +CYDEV_UCFG_B1_P5_U1_CFG20 EQU 0x40011ad4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG21 +CYDEV_UCFG_B1_P5_U1_CFG21 EQU 0x40011ad5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG22 +CYDEV_UCFG_B1_P5_U1_CFG22 EQU 0x40011ad6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG23 +CYDEV_UCFG_B1_P5_U1_CFG23 EQU 0x40011ad7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG24 +CYDEV_UCFG_B1_P5_U1_CFG24 EQU 0x40011ad8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG25 +CYDEV_UCFG_B1_P5_U1_CFG25 EQU 0x40011ad9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG26 +CYDEV_UCFG_B1_P5_U1_CFG26 EQU 0x40011ada + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG27 +CYDEV_UCFG_B1_P5_U1_CFG27 EQU 0x40011adb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG28 +CYDEV_UCFG_B1_P5_U1_CFG28 EQU 0x40011adc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG29 +CYDEV_UCFG_B1_P5_U1_CFG29 EQU 0x40011add + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG30 +CYDEV_UCFG_B1_P5_U1_CFG30 EQU 0x40011ade + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG31 +CYDEV_UCFG_B1_P5_U1_CFG31 EQU 0x40011adf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG0 +CYDEV_UCFG_B1_P5_U1_DCFG0 EQU 0x40011ae0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG1 +CYDEV_UCFG_B1_P5_U1_DCFG1 EQU 0x40011ae2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG2 +CYDEV_UCFG_B1_P5_U1_DCFG2 EQU 0x40011ae4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG3 +CYDEV_UCFG_B1_P5_U1_DCFG3 EQU 0x40011ae6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG4 +CYDEV_UCFG_B1_P5_U1_DCFG4 EQU 0x40011ae8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG5 +CYDEV_UCFG_B1_P5_U1_DCFG5 EQU 0x40011aea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG6 +CYDEV_UCFG_B1_P5_U1_DCFG6 EQU 0x40011aec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG7 +CYDEV_UCFG_B1_P5_U1_DCFG7 EQU 0x40011aee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_ROUTE_BASE +CYDEV_UCFG_B1_P5_ROUTE_BASE EQU 0x40011b00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_ROUTE_SIZE +CYDEV_UCFG_B1_P5_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI0_BASE +CYDEV_UCFG_DSI0_BASE EQU 0x40014000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI0_SIZE +CYDEV_UCFG_DSI0_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI1_BASE +CYDEV_UCFG_DSI1_BASE EQU 0x40014100 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI1_SIZE +CYDEV_UCFG_DSI1_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI2_BASE +CYDEV_UCFG_DSI2_BASE EQU 0x40014200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI2_SIZE +CYDEV_UCFG_DSI2_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI3_BASE +CYDEV_UCFG_DSI3_BASE EQU 0x40014300 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI3_SIZE +CYDEV_UCFG_DSI3_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI4_BASE +CYDEV_UCFG_DSI4_BASE EQU 0x40014400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI4_SIZE +CYDEV_UCFG_DSI4_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI5_BASE +CYDEV_UCFG_DSI5_BASE EQU 0x40014500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI5_SIZE +CYDEV_UCFG_DSI5_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI6_BASE +CYDEV_UCFG_DSI6_BASE EQU 0x40014600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI6_SIZE +CYDEV_UCFG_DSI6_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI7_BASE +CYDEV_UCFG_DSI7_BASE EQU 0x40014700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI7_SIZE +CYDEV_UCFG_DSI7_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI8_BASE +CYDEV_UCFG_DSI8_BASE EQU 0x40014800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI8_SIZE +CYDEV_UCFG_DSI8_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI9_BASE +CYDEV_UCFG_DSI9_BASE EQU 0x40014900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI9_SIZE +CYDEV_UCFG_DSI9_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI12_BASE +CYDEV_UCFG_DSI12_BASE EQU 0x40014c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI12_SIZE +CYDEV_UCFG_DSI12_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI13_BASE +CYDEV_UCFG_DSI13_BASE EQU 0x40014d00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI13_SIZE +CYDEV_UCFG_DSI13_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BASE +CYDEV_UCFG_BCTL0_BASE EQU 0x40015000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_SIZE +CYDEV_UCFG_BCTL0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_MDCLK_EN +CYDEV_UCFG_BCTL0_MDCLK_EN EQU 0x40015000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_MBCLK_EN +CYDEV_UCFG_BCTL0_MBCLK_EN EQU 0x40015001 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_WAIT_CFG +CYDEV_UCFG_BCTL0_WAIT_CFG EQU 0x40015002 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BANK_CTL +CYDEV_UCFG_BCTL0_BANK_CTL EQU 0x40015003 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_UDB_TEST_3 +CYDEV_UCFG_BCTL0_UDB_TEST_3 EQU 0x40015007 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_DCLK_EN0 +CYDEV_UCFG_BCTL0_DCLK_EN0 EQU 0x40015008 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BCLK_EN0 +CYDEV_UCFG_BCTL0_BCLK_EN0 EQU 0x40015009 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_DCLK_EN1 +CYDEV_UCFG_BCTL0_DCLK_EN1 EQU 0x4001500a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BCLK_EN1 +CYDEV_UCFG_BCTL0_BCLK_EN1 EQU 0x4001500b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_DCLK_EN2 +CYDEV_UCFG_BCTL0_DCLK_EN2 EQU 0x4001500c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BCLK_EN2 +CYDEV_UCFG_BCTL0_BCLK_EN2 EQU 0x4001500d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_DCLK_EN3 +CYDEV_UCFG_BCTL0_DCLK_EN3 EQU 0x4001500e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BCLK_EN3 +CYDEV_UCFG_BCTL0_BCLK_EN3 EQU 0x4001500f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BASE +CYDEV_UCFG_BCTL1_BASE EQU 0x40015010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_SIZE +CYDEV_UCFG_BCTL1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_MDCLK_EN +CYDEV_UCFG_BCTL1_MDCLK_EN EQU 0x40015010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_MBCLK_EN +CYDEV_UCFG_BCTL1_MBCLK_EN EQU 0x40015011 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_WAIT_CFG +CYDEV_UCFG_BCTL1_WAIT_CFG EQU 0x40015012 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BANK_CTL +CYDEV_UCFG_BCTL1_BANK_CTL EQU 0x40015013 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_UDB_TEST_3 +CYDEV_UCFG_BCTL1_UDB_TEST_3 EQU 0x40015017 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_DCLK_EN0 +CYDEV_UCFG_BCTL1_DCLK_EN0 EQU 0x40015018 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BCLK_EN0 +CYDEV_UCFG_BCTL1_BCLK_EN0 EQU 0x40015019 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_DCLK_EN1 +CYDEV_UCFG_BCTL1_DCLK_EN1 EQU 0x4001501a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BCLK_EN1 +CYDEV_UCFG_BCTL1_BCLK_EN1 EQU 0x4001501b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_DCLK_EN2 +CYDEV_UCFG_BCTL1_DCLK_EN2 EQU 0x4001501c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BCLK_EN2 +CYDEV_UCFG_BCTL1_BCLK_EN2 EQU 0x4001501d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_DCLK_EN3 +CYDEV_UCFG_BCTL1_DCLK_EN3 EQU 0x4001501e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BCLK_EN3 +CYDEV_UCFG_BCTL1_BCLK_EN3 EQU 0x4001501f + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_BASE +CYDEV_IDMUX_BASE EQU 0x40015100 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_SIZE +CYDEV_IDMUX_SIZE EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL0 +CYDEV_IDMUX_IRQ_CTL0 EQU 0x40015100 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL1 +CYDEV_IDMUX_IRQ_CTL1 EQU 0x40015101 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL2 +CYDEV_IDMUX_IRQ_CTL2 EQU 0x40015102 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL3 +CYDEV_IDMUX_IRQ_CTL3 EQU 0x40015103 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL4 +CYDEV_IDMUX_IRQ_CTL4 EQU 0x40015104 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL5 +CYDEV_IDMUX_IRQ_CTL5 EQU 0x40015105 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL6 +CYDEV_IDMUX_IRQ_CTL6 EQU 0x40015106 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL7 +CYDEV_IDMUX_IRQ_CTL7 EQU 0x40015107 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL0 +CYDEV_IDMUX_DRQ_CTL0 EQU 0x40015110 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL1 +CYDEV_IDMUX_DRQ_CTL1 EQU 0x40015111 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL2 +CYDEV_IDMUX_DRQ_CTL2 EQU 0x40015112 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL3 +CYDEV_IDMUX_DRQ_CTL3 EQU 0x40015113 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL4 +CYDEV_IDMUX_DRQ_CTL4 EQU 0x40015114 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL5 +CYDEV_IDMUX_DRQ_CTL5 EQU 0x40015115 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_BASE +CYDEV_CACHERAM_BASE EQU 0x40030000 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_SIZE +CYDEV_CACHERAM_SIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_DATA_MBASE +CYDEV_CACHERAM_DATA_MBASE EQU 0x40030000 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_DATA_MSIZE +CYDEV_CACHERAM_DATA_MSIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_BASE +CYDEV_SFR_BASE EQU 0x40050100 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_SIZE +CYDEV_SFR_SIZE EQU 0x000000fb + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO0 +CYDEV_SFR_GPIO0 EQU 0x40050180 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD0 +CYDEV_SFR_GPIRD0 EQU 0x40050189 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO0_SEL +CYDEV_SFR_GPIO0_SEL EQU 0x4005018a + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO1 +CYDEV_SFR_GPIO1 EQU 0x40050190 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD1 +CYDEV_SFR_GPIRD1 EQU 0x40050191 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO2 +CYDEV_SFR_GPIO2 EQU 0x40050198 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD2 +CYDEV_SFR_GPIRD2 EQU 0x40050199 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO2_SEL +CYDEV_SFR_GPIO2_SEL EQU 0x4005019a + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO1_SEL +CYDEV_SFR_GPIO1_SEL EQU 0x400501a2 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO3 +CYDEV_SFR_GPIO3 EQU 0x400501b0 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD3 +CYDEV_SFR_GPIRD3 EQU 0x400501b1 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO3_SEL +CYDEV_SFR_GPIO3_SEL EQU 0x400501b2 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO4 +CYDEV_SFR_GPIO4 EQU 0x400501c0 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD4 +CYDEV_SFR_GPIRD4 EQU 0x400501c1 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO4_SEL +CYDEV_SFR_GPIO4_SEL EQU 0x400501c2 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO5 +CYDEV_SFR_GPIO5 EQU 0x400501c8 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD5 +CYDEV_SFR_GPIRD5 EQU 0x400501c9 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO5_SEL +CYDEV_SFR_GPIO5_SEL EQU 0x400501ca + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO6 +CYDEV_SFR_GPIO6 EQU 0x400501d8 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD6 +CYDEV_SFR_GPIRD6 EQU 0x400501d9 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO6_SEL +CYDEV_SFR_GPIO6_SEL EQU 0x400501da + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO12 +CYDEV_SFR_GPIO12 EQU 0x400501e8 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD12 +CYDEV_SFR_GPIRD12 EQU 0x400501e9 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO12_SEL +CYDEV_SFR_GPIO12_SEL EQU 0x400501f2 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO15 +CYDEV_SFR_GPIO15 EQU 0x400501f8 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD15 +CYDEV_SFR_GPIRD15 EQU 0x400501f9 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO15_SEL +CYDEV_SFR_GPIO15_SEL EQU 0x400501fa + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_BASE +CYDEV_P3BA_BASE EQU 0x40050300 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_SIZE +CYDEV_P3BA_SIZE EQU 0x0000002b + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_Y_START +CYDEV_P3BA_Y_START EQU 0x40050300 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_YROLL +CYDEV_P3BA_YROLL EQU 0x40050301 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_YCFG +CYDEV_P3BA_YCFG EQU 0x40050302 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_X_START1 +CYDEV_P3BA_X_START1 EQU 0x40050303 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_X_START2 +CYDEV_P3BA_X_START2 EQU 0x40050304 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_XROLL1 +CYDEV_P3BA_XROLL1 EQU 0x40050305 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_XROLL2 +CYDEV_P3BA_XROLL2 EQU 0x40050306 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_XINC +CYDEV_P3BA_XINC EQU 0x40050307 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_XCFG +CYDEV_P3BA_XCFG EQU 0x40050308 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_OFFSETADDR1 +CYDEV_P3BA_OFFSETADDR1 EQU 0x40050309 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_OFFSETADDR2 +CYDEV_P3BA_OFFSETADDR2 EQU 0x4005030a + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_OFFSETADDR3 +CYDEV_P3BA_OFFSETADDR3 EQU 0x4005030b + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_ABSADDR1 +CYDEV_P3BA_ABSADDR1 EQU 0x4005030c + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_ABSADDR2 +CYDEV_P3BA_ABSADDR2 EQU 0x4005030d + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_ABSADDR3 +CYDEV_P3BA_ABSADDR3 EQU 0x4005030e + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_ABSADDR4 +CYDEV_P3BA_ABSADDR4 EQU 0x4005030f + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATCFG1 +CYDEV_P3BA_DATCFG1 EQU 0x40050310 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATCFG2 +CYDEV_P3BA_DATCFG2 EQU 0x40050311 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_CMP_RSLT1 +CYDEV_P3BA_CMP_RSLT1 EQU 0x40050314 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_CMP_RSLT2 +CYDEV_P3BA_CMP_RSLT2 EQU 0x40050315 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_CMP_RSLT3 +CYDEV_P3BA_CMP_RSLT3 EQU 0x40050316 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_CMP_RSLT4 +CYDEV_P3BA_CMP_RSLT4 EQU 0x40050317 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATA_REG1 +CYDEV_P3BA_DATA_REG1 EQU 0x40050318 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATA_REG2 +CYDEV_P3BA_DATA_REG2 EQU 0x40050319 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATA_REG3 +CYDEV_P3BA_DATA_REG3 EQU 0x4005031a + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATA_REG4 +CYDEV_P3BA_DATA_REG4 EQU 0x4005031b + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_EXP_DATA1 +CYDEV_P3BA_EXP_DATA1 EQU 0x4005031c + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_EXP_DATA2 +CYDEV_P3BA_EXP_DATA2 EQU 0x4005031d + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_EXP_DATA3 +CYDEV_P3BA_EXP_DATA3 EQU 0x4005031e + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_EXP_DATA4 +CYDEV_P3BA_EXP_DATA4 EQU 0x4005031f + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_MSTR_HRDATA1 +CYDEV_P3BA_MSTR_HRDATA1 EQU 0x40050320 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_MSTR_HRDATA2 +CYDEV_P3BA_MSTR_HRDATA2 EQU 0x40050321 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_MSTR_HRDATA3 +CYDEV_P3BA_MSTR_HRDATA3 EQU 0x40050322 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_MSTR_HRDATA4 +CYDEV_P3BA_MSTR_HRDATA4 EQU 0x40050323 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_BIST_EN +CYDEV_P3BA_BIST_EN EQU 0x40050324 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_PHUB_MASTER_SSR +CYDEV_P3BA_PHUB_MASTER_SSR EQU 0x40050325 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_SEQCFG1 +CYDEV_P3BA_SEQCFG1 EQU 0x40050326 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_SEQCFG2 +CYDEV_P3BA_SEQCFG2 EQU 0x40050327 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_Y_CURR +CYDEV_P3BA_Y_CURR EQU 0x40050328 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_X_CURR1 +CYDEV_P3BA_X_CURR1 EQU 0x40050329 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_X_CURR2 +CYDEV_P3BA_X_CURR2 EQU 0x4005032a + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_BASE +CYDEV_PANTHER_BASE EQU 0x40080000 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_SIZE +CYDEV_PANTHER_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_STCALIB_CFG +CYDEV_PANTHER_STCALIB_CFG EQU 0x40080000 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_WAITPIPE +CYDEV_PANTHER_WAITPIPE EQU 0x40080004 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_TRACE_CFG +CYDEV_PANTHER_TRACE_CFG EQU 0x40080008 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_DBG_CFG +CYDEV_PANTHER_DBG_CFG EQU 0x4008000c + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_CM3_LCKRST_STAT +CYDEV_PANTHER_CM3_LCKRST_STAT EQU 0x40080018 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_DEVICE_ID +CYDEV_PANTHER_DEVICE_ID EQU 0x4008001c + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_BASE +CYDEV_FLSECC_BASE EQU 0x48000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_SIZE +CYDEV_FLSECC_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_DATA_MBASE +CYDEV_FLSECC_DATA_MBASE EQU 0x48000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_DATA_MSIZE +CYDEV_FLSECC_DATA_MSIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_BASE +CYDEV_FLSHID_BASE EQU 0x49000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_SIZE +CYDEV_FLSHID_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_RSVD_MBASE +CYDEV_FLSHID_RSVD_MBASE EQU 0x49000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_RSVD_MSIZE +CYDEV_FLSHID_RSVD_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_MDATA_MBASE +CYDEV_FLSHID_CUST_MDATA_MBASE EQU 0x49000080 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_MDATA_MSIZE +CYDEV_FLSHID_CUST_MDATA_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_BASE +CYDEV_FLSHID_CUST_TABLES_BASE EQU 0x49000100 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_SIZE +CYDEV_FLSHID_CUST_TABLES_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_Y_LOC +CYDEV_FLSHID_CUST_TABLES_Y_LOC EQU 0x49000100 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_X_LOC +CYDEV_FLSHID_CUST_TABLES_X_LOC EQU 0x49000101 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_WAFER_NUM +CYDEV_FLSHID_CUST_TABLES_WAFER_NUM EQU 0x49000102 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_LOT_LSB +CYDEV_FLSHID_CUST_TABLES_LOT_LSB EQU 0x49000103 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_LOT_MSB +CYDEV_FLSHID_CUST_TABLES_LOT_MSB EQU 0x49000104 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_WRK_WK +CYDEV_FLSHID_CUST_TABLES_WRK_WK EQU 0x49000105 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_FAB_YR +CYDEV_FLSHID_CUST_TABLES_FAB_YR EQU 0x49000106 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_MINOR +CYDEV_FLSHID_CUST_TABLES_MINOR EQU 0x49000107 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ EQU 0x49000108 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ EQU 0x49000109 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ EQU 0x4900010a + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ EQU 0x4900010b + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ EQU 0x4900010c + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ EQU 0x4900010d + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ EQU 0x4900010e + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_USB +CYDEV_FLSHID_CUST_TABLES_IMO_USB EQU 0x4900010f + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS +CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS EQU 0x49000110 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS +CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS EQU 0x49000111 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS +CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS EQU 0x49000112 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS +CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS EQU 0x49000113 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS +CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS EQU 0x49000114 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS +CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS EQU 0x49000115 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS +CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS EQU 0x49000116 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS +CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS EQU 0x49000117 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M1 +CYDEV_FLSHID_CUST_TABLES_DEC_M1 EQU 0x49000118 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M2 +CYDEV_FLSHID_CUST_TABLES_DEC_M2 EQU 0x49000119 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M3 +CYDEV_FLSHID_CUST_TABLES_DEC_M3 EQU 0x4900011a + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M4 +CYDEV_FLSHID_CUST_TABLES_DEC_M4 EQU 0x4900011b + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M5 +CYDEV_FLSHID_CUST_TABLES_DEC_M5 EQU 0x4900011c + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M6 +CYDEV_FLSHID_CUST_TABLES_DEC_M6 EQU 0x4900011d + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M7 +CYDEV_FLSHID_CUST_TABLES_DEC_M7 EQU 0x4900011e + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M8 +CYDEV_FLSHID_CUST_TABLES_DEC_M8 EQU 0x4900011f + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M1 +CYDEV_FLSHID_CUST_TABLES_DAC0_M1 EQU 0x49000120 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M2 +CYDEV_FLSHID_CUST_TABLES_DAC0_M2 EQU 0x49000121 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M3 +CYDEV_FLSHID_CUST_TABLES_DAC0_M3 EQU 0x49000122 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M4 +CYDEV_FLSHID_CUST_TABLES_DAC0_M4 EQU 0x49000123 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M5 +CYDEV_FLSHID_CUST_TABLES_DAC0_M5 EQU 0x49000124 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M6 +CYDEV_FLSHID_CUST_TABLES_DAC0_M6 EQU 0x49000125 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M7 +CYDEV_FLSHID_CUST_TABLES_DAC0_M7 EQU 0x49000126 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M8 +CYDEV_FLSHID_CUST_TABLES_DAC0_M8 EQU 0x49000127 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M1 +CYDEV_FLSHID_CUST_TABLES_DAC2_M1 EQU 0x49000128 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M2 +CYDEV_FLSHID_CUST_TABLES_DAC2_M2 EQU 0x49000129 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M3 +CYDEV_FLSHID_CUST_TABLES_DAC2_M3 EQU 0x4900012a + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M4 +CYDEV_FLSHID_CUST_TABLES_DAC2_M4 EQU 0x4900012b + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M5 +CYDEV_FLSHID_CUST_TABLES_DAC2_M5 EQU 0x4900012c + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M6 +CYDEV_FLSHID_CUST_TABLES_DAC2_M6 EQU 0x4900012d + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M7 +CYDEV_FLSHID_CUST_TABLES_DAC2_M7 EQU 0x4900012e + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M8 +CYDEV_FLSHID_CUST_TABLES_DAC2_M8 EQU 0x4900012f + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M1 +CYDEV_FLSHID_CUST_TABLES_DAC1_M1 EQU 0x49000130 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M2 +CYDEV_FLSHID_CUST_TABLES_DAC1_M2 EQU 0x49000131 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M3 +CYDEV_FLSHID_CUST_TABLES_DAC1_M3 EQU 0x49000132 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M4 +CYDEV_FLSHID_CUST_TABLES_DAC1_M4 EQU 0x49000133 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M5 +CYDEV_FLSHID_CUST_TABLES_DAC1_M5 EQU 0x49000134 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M6 +CYDEV_FLSHID_CUST_TABLES_DAC1_M6 EQU 0x49000135 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M7 +CYDEV_FLSHID_CUST_TABLES_DAC1_M7 EQU 0x49000136 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M8 +CYDEV_FLSHID_CUST_TABLES_DAC1_M8 EQU 0x49000137 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M1 +CYDEV_FLSHID_CUST_TABLES_DAC3_M1 EQU 0x49000138 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M2 +CYDEV_FLSHID_CUST_TABLES_DAC3_M2 EQU 0x49000139 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M3 +CYDEV_FLSHID_CUST_TABLES_DAC3_M3 EQU 0x4900013a + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M4 +CYDEV_FLSHID_CUST_TABLES_DAC3_M4 EQU 0x4900013b + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M5 +CYDEV_FLSHID_CUST_TABLES_DAC3_M5 EQU 0x4900013c + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M6 +CYDEV_FLSHID_CUST_TABLES_DAC3_M6 EQU 0x4900013d + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M7 +CYDEV_FLSHID_CUST_TABLES_DAC3_M7 EQU 0x4900013e + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M8 +CYDEV_FLSHID_CUST_TABLES_DAC3_M8 EQU 0x4900013f + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_BASE +CYDEV_FLSHID_MFG_CFG_BASE EQU 0x49000180 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_SIZE +CYDEV_FLSHID_MFG_CFG_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_IMO_TR1 +CYDEV_FLSHID_MFG_CFG_IMO_TR1 EQU 0x49000188 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP0_TR0 +CYDEV_FLSHID_MFG_CFG_CMP0_TR0 EQU 0x490001ac + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP1_TR0 +CYDEV_FLSHID_MFG_CFG_CMP1_TR0 EQU 0x490001ae + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP2_TR0 +CYDEV_FLSHID_MFG_CFG_CMP2_TR0 EQU 0x490001b0 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP3_TR0 +CYDEV_FLSHID_MFG_CFG_CMP3_TR0 EQU 0x490001b2 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP0_TR1 +CYDEV_FLSHID_MFG_CFG_CMP0_TR1 EQU 0x490001b4 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP1_TR1 +CYDEV_FLSHID_MFG_CFG_CMP1_TR1 EQU 0x490001b6 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP2_TR1 +CYDEV_FLSHID_MFG_CFG_CMP2_TR1 EQU 0x490001b8 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP3_TR1 +CYDEV_FLSHID_MFG_CFG_CMP3_TR1 EQU 0x490001ba + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM +CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM EQU 0x490001ce + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_BASE +CYDEV_EXTMEM_BASE EQU 0x60000000 + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_SIZE +CYDEV_EXTMEM_SIZE EQU 0x00800000 + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_DATA_MBASE +CYDEV_EXTMEM_DATA_MBASE EQU 0x60000000 + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_DATA_MSIZE +CYDEV_EXTMEM_DATA_MSIZE EQU 0x00800000 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_BASE +CYDEV_ITM_BASE EQU 0xe0000000 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_SIZE +CYDEV_ITM_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_TRACE_EN +CYDEV_ITM_TRACE_EN EQU 0xe0000e00 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_TRACE_PRIVILEGE +CYDEV_ITM_TRACE_PRIVILEGE EQU 0xe0000e40 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_TRACE_CTRL +CYDEV_ITM_TRACE_CTRL EQU 0xe0000e80 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_LOCK_ACCESS +CYDEV_ITM_LOCK_ACCESS EQU 0xe0000fb0 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_LOCK_STATUS +CYDEV_ITM_LOCK_STATUS EQU 0xe0000fb4 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID4 +CYDEV_ITM_PID4 EQU 0xe0000fd0 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID5 +CYDEV_ITM_PID5 EQU 0xe0000fd4 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID6 +CYDEV_ITM_PID6 EQU 0xe0000fd8 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID7 +CYDEV_ITM_PID7 EQU 0xe0000fdc + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID0 +CYDEV_ITM_PID0 EQU 0xe0000fe0 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID1 +CYDEV_ITM_PID1 EQU 0xe0000fe4 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID2 +CYDEV_ITM_PID2 EQU 0xe0000fe8 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID3 +CYDEV_ITM_PID3 EQU 0xe0000fec + ENDIF + IF :LNOT::DEF:CYDEV_ITM_CID0 +CYDEV_ITM_CID0 EQU 0xe0000ff0 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_CID1 +CYDEV_ITM_CID1 EQU 0xe0000ff4 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_CID2 +CYDEV_ITM_CID2 EQU 0xe0000ff8 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_CID3 +CYDEV_ITM_CID3 EQU 0xe0000ffc + ENDIF + IF :LNOT::DEF:CYDEV_DWT_BASE +CYDEV_DWT_BASE EQU 0xe0001000 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_SIZE +CYDEV_DWT_SIZE EQU 0x0000005c + ENDIF + IF :LNOT::DEF:CYDEV_DWT_CTRL +CYDEV_DWT_CTRL EQU 0xe0001000 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_CYCLE_COUNT +CYDEV_DWT_CYCLE_COUNT EQU 0xe0001004 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_CPI_COUNT +CYDEV_DWT_CPI_COUNT EQU 0xe0001008 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_EXC_OVHD_COUNT +CYDEV_DWT_EXC_OVHD_COUNT EQU 0xe000100c + ENDIF + IF :LNOT::DEF:CYDEV_DWT_SLEEP_COUNT +CYDEV_DWT_SLEEP_COUNT EQU 0xe0001010 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_LSU_COUNT +CYDEV_DWT_LSU_COUNT EQU 0xe0001014 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_FOLD_COUNT +CYDEV_DWT_FOLD_COUNT EQU 0xe0001018 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_PC_SAMPLE +CYDEV_DWT_PC_SAMPLE EQU 0xe000101c + ENDIF + IF :LNOT::DEF:CYDEV_DWT_COMP_0 +CYDEV_DWT_COMP_0 EQU 0xe0001020 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_MASK_0 +CYDEV_DWT_MASK_0 EQU 0xe0001024 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_FUNCTION_0 +CYDEV_DWT_FUNCTION_0 EQU 0xe0001028 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_COMP_1 +CYDEV_DWT_COMP_1 EQU 0xe0001030 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_MASK_1 +CYDEV_DWT_MASK_1 EQU 0xe0001034 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_FUNCTION_1 +CYDEV_DWT_FUNCTION_1 EQU 0xe0001038 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_COMP_2 +CYDEV_DWT_COMP_2 EQU 0xe0001040 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_MASK_2 +CYDEV_DWT_MASK_2 EQU 0xe0001044 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_FUNCTION_2 +CYDEV_DWT_FUNCTION_2 EQU 0xe0001048 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_COMP_3 +CYDEV_DWT_COMP_3 EQU 0xe0001050 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_MASK_3 +CYDEV_DWT_MASK_3 EQU 0xe0001054 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_FUNCTION_3 +CYDEV_DWT_FUNCTION_3 EQU 0xe0001058 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_BASE +CYDEV_FPB_BASE EQU 0xe0002000 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_SIZE +CYDEV_FPB_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_CTRL +CYDEV_FPB_CTRL EQU 0xe0002000 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_REMAP +CYDEV_FPB_REMAP EQU 0xe0002004 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_0 +CYDEV_FPB_FP_COMP_0 EQU 0xe0002008 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_1 +CYDEV_FPB_FP_COMP_1 EQU 0xe000200c + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_2 +CYDEV_FPB_FP_COMP_2 EQU 0xe0002010 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_3 +CYDEV_FPB_FP_COMP_3 EQU 0xe0002014 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_4 +CYDEV_FPB_FP_COMP_4 EQU 0xe0002018 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_5 +CYDEV_FPB_FP_COMP_5 EQU 0xe000201c + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_6 +CYDEV_FPB_FP_COMP_6 EQU 0xe0002020 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_7 +CYDEV_FPB_FP_COMP_7 EQU 0xe0002024 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID4 +CYDEV_FPB_PID4 EQU 0xe0002fd0 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID5 +CYDEV_FPB_PID5 EQU 0xe0002fd4 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID6 +CYDEV_FPB_PID6 EQU 0xe0002fd8 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID7 +CYDEV_FPB_PID7 EQU 0xe0002fdc + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID0 +CYDEV_FPB_PID0 EQU 0xe0002fe0 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID1 +CYDEV_FPB_PID1 EQU 0xe0002fe4 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID2 +CYDEV_FPB_PID2 EQU 0xe0002fe8 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID3 +CYDEV_FPB_PID3 EQU 0xe0002fec + ENDIF + IF :LNOT::DEF:CYDEV_FPB_CID0 +CYDEV_FPB_CID0 EQU 0xe0002ff0 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_CID1 +CYDEV_FPB_CID1 EQU 0xe0002ff4 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_CID2 +CYDEV_FPB_CID2 EQU 0xe0002ff8 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_CID3 +CYDEV_FPB_CID3 EQU 0xe0002ffc + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_BASE +CYDEV_NVIC_BASE EQU 0xe000e000 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SIZE +CYDEV_NVIC_SIZE EQU 0x00000d3c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_INT_CTL_TYPE +CYDEV_NVIC_INT_CTL_TYPE EQU 0xe000e004 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYSTICK_CTL +CYDEV_NVIC_SYSTICK_CTL EQU 0xe000e010 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYSTICK_RELOAD +CYDEV_NVIC_SYSTICK_RELOAD EQU 0xe000e014 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYSTICK_CURRENT +CYDEV_NVIC_SYSTICK_CURRENT EQU 0xe000e018 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYSTICK_CAL +CYDEV_NVIC_SYSTICK_CAL EQU 0xe000e01c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SETENA0 +CYDEV_NVIC_SETENA0 EQU 0xe000e100 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_CLRENA0 +CYDEV_NVIC_CLRENA0 EQU 0xe000e180 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SETPEND0 +CYDEV_NVIC_SETPEND0 EQU 0xe000e200 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_CLRPEND0 +CYDEV_NVIC_CLRPEND0 EQU 0xe000e280 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_ACTIVE0 +CYDEV_NVIC_ACTIVE0 EQU 0xe000e300 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_0 +CYDEV_NVIC_PRI_0 EQU 0xe000e400 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_1 +CYDEV_NVIC_PRI_1 EQU 0xe000e401 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_2 +CYDEV_NVIC_PRI_2 EQU 0xe000e402 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_3 +CYDEV_NVIC_PRI_3 EQU 0xe000e403 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_4 +CYDEV_NVIC_PRI_4 EQU 0xe000e404 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_5 +CYDEV_NVIC_PRI_5 EQU 0xe000e405 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_6 +CYDEV_NVIC_PRI_6 EQU 0xe000e406 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_7 +CYDEV_NVIC_PRI_7 EQU 0xe000e407 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_8 +CYDEV_NVIC_PRI_8 EQU 0xe000e408 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_9 +CYDEV_NVIC_PRI_9 EQU 0xe000e409 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_10 +CYDEV_NVIC_PRI_10 EQU 0xe000e40a + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_11 +CYDEV_NVIC_PRI_11 EQU 0xe000e40b + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_12 +CYDEV_NVIC_PRI_12 EQU 0xe000e40c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_13 +CYDEV_NVIC_PRI_13 EQU 0xe000e40d + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_14 +CYDEV_NVIC_PRI_14 EQU 0xe000e40e + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_15 +CYDEV_NVIC_PRI_15 EQU 0xe000e40f + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_16 +CYDEV_NVIC_PRI_16 EQU 0xe000e410 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_17 +CYDEV_NVIC_PRI_17 EQU 0xe000e411 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_18 +CYDEV_NVIC_PRI_18 EQU 0xe000e412 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_19 +CYDEV_NVIC_PRI_19 EQU 0xe000e413 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_20 +CYDEV_NVIC_PRI_20 EQU 0xe000e414 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_21 +CYDEV_NVIC_PRI_21 EQU 0xe000e415 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_22 +CYDEV_NVIC_PRI_22 EQU 0xe000e416 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_23 +CYDEV_NVIC_PRI_23 EQU 0xe000e417 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_24 +CYDEV_NVIC_PRI_24 EQU 0xe000e418 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_25 +CYDEV_NVIC_PRI_25 EQU 0xe000e419 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_26 +CYDEV_NVIC_PRI_26 EQU 0xe000e41a + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_27 +CYDEV_NVIC_PRI_27 EQU 0xe000e41b + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_28 +CYDEV_NVIC_PRI_28 EQU 0xe000e41c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_29 +CYDEV_NVIC_PRI_29 EQU 0xe000e41d + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_30 +CYDEV_NVIC_PRI_30 EQU 0xe000e41e + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_31 +CYDEV_NVIC_PRI_31 EQU 0xe000e41f + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_CPUID_BASE +CYDEV_NVIC_CPUID_BASE EQU 0xe000ed00 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_INTR_CTRL_STATE +CYDEV_NVIC_INTR_CTRL_STATE EQU 0xe000ed04 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_VECT_OFFSET +CYDEV_NVIC_VECT_OFFSET EQU 0xe000ed08 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_APPLN_INTR +CYDEV_NVIC_APPLN_INTR EQU 0xe000ed0c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYSTEM_CONTROL +CYDEV_NVIC_SYSTEM_CONTROL EQU 0xe000ed10 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_CFG_CONTROL +CYDEV_NVIC_CFG_CONTROL EQU 0xe000ed14 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYS_PRIO_HANDLER_4_7 +CYDEV_NVIC_SYS_PRIO_HANDLER_4_7 EQU 0xe000ed18 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYS_PRIO_HANDLER_8_11 +CYDEV_NVIC_SYS_PRIO_HANDLER_8_11 EQU 0xe000ed1c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYS_PRIO_HANDLER_12_15 +CYDEV_NVIC_SYS_PRIO_HANDLER_12_15 EQU 0xe000ed20 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYS_HANDLER_CSR +CYDEV_NVIC_SYS_HANDLER_CSR EQU 0xe000ed24 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_MEMMAN_FAULT_STATUS +CYDEV_NVIC_MEMMAN_FAULT_STATUS EQU 0xe000ed28 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_BUS_FAULT_STATUS +CYDEV_NVIC_BUS_FAULT_STATUS EQU 0xe000ed29 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_USAGE_FAULT_STATUS +CYDEV_NVIC_USAGE_FAULT_STATUS EQU 0xe000ed2a + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_HARD_FAULT_STATUS +CYDEV_NVIC_HARD_FAULT_STATUS EQU 0xe000ed2c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_DEBUG_FAULT_STATUS +CYDEV_NVIC_DEBUG_FAULT_STATUS EQU 0xe000ed30 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_MEMMAN_FAULT_ADD +CYDEV_NVIC_MEMMAN_FAULT_ADD EQU 0xe000ed34 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_BUS_FAULT_ADD +CYDEV_NVIC_BUS_FAULT_ADD EQU 0xe000ed38 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_BASE +CYDEV_CORE_DBG_BASE EQU 0xe000edf0 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_SIZE +CYDEV_CORE_DBG_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_DBG_HLT_CS +CYDEV_CORE_DBG_DBG_HLT_CS EQU 0xe000edf0 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_DBG_REG_SEL +CYDEV_CORE_DBG_DBG_REG_SEL EQU 0xe000edf4 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_DBG_REG_DATA +CYDEV_CORE_DBG_DBG_REG_DATA EQU 0xe000edf8 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_EXC_MON_CTL +CYDEV_CORE_DBG_EXC_MON_CTL EQU 0xe000edfc + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_BASE +CYDEV_TPIU_BASE EQU 0xe0040000 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_SIZE +CYDEV_TPIU_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ +CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ EQU 0xe0040000 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_CURRENT_SYNC_PRT_SZ +CYDEV_TPIU_CURRENT_SYNC_PRT_SZ EQU 0xe0040004 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ASYNC_CLK_PRESCALER +CYDEV_TPIU_ASYNC_CLK_PRESCALER EQU 0xe0040010 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PROTOCOL +CYDEV_TPIU_PROTOCOL EQU 0xe00400f0 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_FORM_FLUSH_STAT +CYDEV_TPIU_FORM_FLUSH_STAT EQU 0xe0040300 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_FORM_FLUSH_CTRL +CYDEV_TPIU_FORM_FLUSH_CTRL EQU 0xe0040304 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_TRIGGER +CYDEV_TPIU_TRIGGER EQU 0xe0040ee8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ITETMDATA +CYDEV_TPIU_ITETMDATA EQU 0xe0040eec + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ITATBCTR2 +CYDEV_TPIU_ITATBCTR2 EQU 0xe0040ef0 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ITATBCTR0 +CYDEV_TPIU_ITATBCTR0 EQU 0xe0040ef8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ITITMDATA +CYDEV_TPIU_ITITMDATA EQU 0xe0040efc + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ITCTRL +CYDEV_TPIU_ITCTRL EQU 0xe0040f00 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_DEVID +CYDEV_TPIU_DEVID EQU 0xe0040fc8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_DEVTYPE +CYDEV_TPIU_DEVTYPE EQU 0xe0040fcc + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID4 +CYDEV_TPIU_PID4 EQU 0xe0040fd0 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID5 +CYDEV_TPIU_PID5 EQU 0xe0040fd4 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID6 +CYDEV_TPIU_PID6 EQU 0xe0040fd8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID7 +CYDEV_TPIU_PID7 EQU 0xe0040fdc + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID0 +CYDEV_TPIU_PID0 EQU 0xe0040fe0 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID1 +CYDEV_TPIU_PID1 EQU 0xe0040fe4 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID2 +CYDEV_TPIU_PID2 EQU 0xe0040fe8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID3 +CYDEV_TPIU_PID3 EQU 0xe0040fec + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_CID0 +CYDEV_TPIU_CID0 EQU 0xe0040ff0 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_CID1 +CYDEV_TPIU_CID1 EQU 0xe0040ff4 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_CID2 +CYDEV_TPIU_CID2 EQU 0xe0040ff8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_CID3 +CYDEV_TPIU_CID3 EQU 0xe0040ffc + ENDIF + IF :LNOT::DEF:CYDEV_ETM_BASE +CYDEV_ETM_BASE EQU 0xe0041000 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_SIZE +CYDEV_ETM_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CTL +CYDEV_ETM_CTL EQU 0xe0041000 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CFG_CODE +CYDEV_ETM_CFG_CODE EQU 0xe0041004 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_TRIG_EVENT +CYDEV_ETM_TRIG_EVENT EQU 0xe0041008 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_STATUS +CYDEV_ETM_STATUS EQU 0xe0041010 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_SYS_CFG +CYDEV_ETM_SYS_CFG EQU 0xe0041014 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_TRACE_ENB_EVENT +CYDEV_ETM_TRACE_ENB_EVENT EQU 0xe0041020 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_TRACE_EN_CTRL1 +CYDEV_ETM_TRACE_EN_CTRL1 EQU 0xe0041024 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_FIFOFULL_LEVEL +CYDEV_ETM_FIFOFULL_LEVEL EQU 0xe004102c + ENDIF + IF :LNOT::DEF:CYDEV_ETM_SYNC_FREQ +CYDEV_ETM_SYNC_FREQ EQU 0xe00411e0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_ETM_ID +CYDEV_ETM_ETM_ID EQU 0xe00411e4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CFG_CODE_EXT +CYDEV_ETM_CFG_CODE_EXT EQU 0xe00411e8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_TR_SS_EMBICE_CTRL +CYDEV_ETM_TR_SS_EMBICE_CTRL EQU 0xe00411f0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CS_TRACE_ID +CYDEV_ETM_CS_TRACE_ID EQU 0xe0041200 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_OS_LOCK_ACCESS +CYDEV_ETM_OS_LOCK_ACCESS EQU 0xe0041300 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_OS_LOCK_STATUS +CYDEV_ETM_OS_LOCK_STATUS EQU 0xe0041304 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PDSR +CYDEV_ETM_PDSR EQU 0xe0041314 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_ITMISCIN +CYDEV_ETM_ITMISCIN EQU 0xe0041ee0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_ITTRIGOUT +CYDEV_ETM_ITTRIGOUT EQU 0xe0041ee8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_ITATBCTR2 +CYDEV_ETM_ITATBCTR2 EQU 0xe0041ef0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_ITATBCTR0 +CYDEV_ETM_ITATBCTR0 EQU 0xe0041ef8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_INT_MODE_CTRL +CYDEV_ETM_INT_MODE_CTRL EQU 0xe0041f00 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CLM_TAG_SET +CYDEV_ETM_CLM_TAG_SET EQU 0xe0041fa0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CLM_TAG_CLR +CYDEV_ETM_CLM_TAG_CLR EQU 0xe0041fa4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_LOCK_ACCESS +CYDEV_ETM_LOCK_ACCESS EQU 0xe0041fb0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_LOCK_STATUS +CYDEV_ETM_LOCK_STATUS EQU 0xe0041fb4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_AUTH_STATUS +CYDEV_ETM_AUTH_STATUS EQU 0xe0041fb8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_DEV_TYPE +CYDEV_ETM_DEV_TYPE EQU 0xe0041fcc + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID4 +CYDEV_ETM_PID4 EQU 0xe0041fd0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID5 +CYDEV_ETM_PID5 EQU 0xe0041fd4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID6 +CYDEV_ETM_PID6 EQU 0xe0041fd8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID7 +CYDEV_ETM_PID7 EQU 0xe0041fdc + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID0 +CYDEV_ETM_PID0 EQU 0xe0041fe0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID1 +CYDEV_ETM_PID1 EQU 0xe0041fe4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID2 +CYDEV_ETM_PID2 EQU 0xe0041fe8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID3 +CYDEV_ETM_PID3 EQU 0xe0041fec + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CID0 +CYDEV_ETM_CID0 EQU 0xe0041ff0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CID1 +CYDEV_ETM_CID1 EQU 0xe0041ff4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CID2 +CYDEV_ETM_CID2 EQU 0xe0041ff8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CID3 +CYDEV_ETM_CID3 EQU 0xe0041ffc + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_BASE +CYDEV_ROM_TABLE_BASE EQU 0xe00ff000 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_SIZE +CYDEV_ROM_TABLE_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_NVIC +CYDEV_ROM_TABLE_NVIC EQU 0xe00ff000 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_DWT +CYDEV_ROM_TABLE_DWT EQU 0xe00ff004 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_FPB +CYDEV_ROM_TABLE_FPB EQU 0xe00ff008 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_ITM +CYDEV_ROM_TABLE_ITM EQU 0xe00ff00c + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_TPIU +CYDEV_ROM_TABLE_TPIU EQU 0xe00ff010 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_ETM +CYDEV_ROM_TABLE_ETM EQU 0xe00ff014 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_END +CYDEV_ROM_TABLE_END EQU 0xe00ff018 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_MEMTYPE +CYDEV_ROM_TABLE_MEMTYPE EQU 0xe00fffcc + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID4 +CYDEV_ROM_TABLE_PID4 EQU 0xe00fffd0 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID5 +CYDEV_ROM_TABLE_PID5 EQU 0xe00fffd4 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID6 +CYDEV_ROM_TABLE_PID6 EQU 0xe00fffd8 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID7 +CYDEV_ROM_TABLE_PID7 EQU 0xe00fffdc + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID0 +CYDEV_ROM_TABLE_PID0 EQU 0xe00fffe0 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID1 +CYDEV_ROM_TABLE_PID1 EQU 0xe00fffe4 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID2 +CYDEV_ROM_TABLE_PID2 EQU 0xe00fffe8 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID3 +CYDEV_ROM_TABLE_PID3 EQU 0xe00fffec + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_CID0 +CYDEV_ROM_TABLE_CID0 EQU 0xe00ffff0 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_CID1 +CYDEV_ROM_TABLE_CID1 EQU 0xe00ffff4 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_CID2 +CYDEV_ROM_TABLE_CID2 EQU 0xe00ffff8 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_CID3 +CYDEV_ROM_TABLE_CID3 EQU 0xe00ffffc + ENDIF + IF :LNOT::DEF:CYDEV_FLS_SIZE +CYDEV_FLS_SIZE EQU CYDEV_FLASH_SIZE + ENDIF + IF :LNOT::DEF:CYDEV_ECC_BASE +CYDEV_ECC_BASE EQU CYDEV_FLSECC_BASE + ENDIF + IF :LNOT::DEF:CYDEV_FLS_SECTOR_SIZE +CYDEV_FLS_SECTOR_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYDEV_FLS_ROW_SIZE +CYDEV_FLS_ROW_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_ECC_SECTOR_SIZE +CYDEV_ECC_SECTOR_SIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYDEV_ECC_ROW_SIZE +CYDEV_ECC_ROW_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_EEPROM_SECTOR_SIZE +CYDEV_EEPROM_SECTOR_SIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYDEV_EEPROM_ROW_SIZE +CYDEV_EEPROM_ROW_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PERIPH_BASE +CYDEV_PERIPH_BASE EQU CYDEV_CLKDIST_BASE + ENDIF + IF :LNOT::DEF:CYCLK_LD_DISABLE +CYCLK_LD_DISABLE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYCLK_LD_SYNC_EN +CYCLK_LD_SYNC_EN EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYCLK_LD_LOAD +CYCLK_LD_LOAD EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYCLK_PIPE +CYCLK_PIPE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYCLK_SSS +CYCLK_SSS EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYCLK_EARLY +CYCLK_EARLY EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYCLK_DUTY +CYCLK_DUTY EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYCLK_SYNC +CYCLK_SYNC EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_CLK_SYNC_D +CYCLK_SRC_SEL_CLK_SYNC_D EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_SYNC_DIG +CYCLK_SRC_SEL_SYNC_DIG EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_IMO +CYCLK_SRC_SEL_IMO EQU 1 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTAL_MHZ +CYCLK_SRC_SEL_XTAL_MHZ EQU 2 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTALM +CYCLK_SRC_SEL_XTALM EQU 2 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_ILO +CYCLK_SRC_SEL_ILO EQU 3 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_PLL +CYCLK_SRC_SEL_PLL EQU 4 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTAL_KHZ +CYCLK_SRC_SEL_XTAL_KHZ EQU 5 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTALK +CYCLK_SRC_SEL_XTALK EQU 5 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_G +CYCLK_SRC_SEL_DSI_G EQU 6 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_D +CYCLK_SRC_SEL_DSI_D EQU 7 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_CLK_SYNC_A +CYCLK_SRC_SEL_CLK_SYNC_A EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_A +CYCLK_SRC_SEL_DSI_A EQU 7 + ENDIF + END diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc new file mode 100755 index 00000000..790c65b5 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc @@ -0,0 +1,16039 @@ +; +; FILENAME: cydevicerv_trm.inc +; +; PSoC Creator 3.0 Component Pack 7 +; +; DESCRIPTION: +; This file provides all of the address values for the entire PSoC device. +; +;------------------------------------------------------------------------------- +; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + + IF :LNOT::DEF:CYDEV_FLASH_BASE +CYDEV_FLASH_BASE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLASH_SIZE +CYDEV_FLASH_SIZE EQU 0x00020000 + ENDIF + IF :LNOT::DEF:CYREG_FLASH_DATA_MBASE +CYREG_FLASH_DATA_MBASE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYREG_FLASH_DATA_MSIZE +CYREG_FLASH_DATA_MSIZE EQU 0x00020000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_BASE +CYDEV_SRAM_BASE EQU 0x1fffc000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_SIZE +CYDEV_SRAM_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE64K_MBASE +CYREG_SRAM_CODE64K_MBASE EQU 0x1fff8000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE64K_MSIZE +CYREG_SRAM_CODE64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE32K_MBASE +CYREG_SRAM_CODE32K_MBASE EQU 0x1fffc000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE32K_MSIZE +CYREG_SRAM_CODE32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE16K_MBASE +CYREG_SRAM_CODE16K_MBASE EQU 0x1fffe000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE16K_MSIZE +CYREG_SRAM_CODE16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE_MBASE +CYREG_SRAM_CODE_MBASE EQU 0x1fffc000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE_MSIZE +CYREG_SRAM_CODE_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA_MBASE +CYREG_SRAM_DATA_MBASE EQU 0x20000000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA_MSIZE +CYREG_SRAM_DATA_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA16K_MBASE +CYREG_SRAM_DATA16K_MBASE EQU 0x20001000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA16K_MSIZE +CYREG_SRAM_DATA16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA32K_MBASE +CYREG_SRAM_DATA32K_MBASE EQU 0x20002000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA32K_MSIZE +CYREG_SRAM_DATA32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA64K_MBASE +CYREG_SRAM_DATA64K_MBASE EQU 0x20004000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA64K_MSIZE +CYREG_SRAM_DATA64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_BASE +CYDEV_DMA_BASE EQU 0x20008000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SIZE +CYDEV_DMA_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM64K_MBASE +CYREG_DMA_SRAM64K_MBASE EQU 0x20008000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM64K_MSIZE +CYREG_DMA_SRAM64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM32K_MBASE +CYREG_DMA_SRAM32K_MBASE EQU 0x2000c000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM32K_MSIZE +CYREG_DMA_SRAM32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM16K_MBASE +CYREG_DMA_SRAM16K_MBASE EQU 0x2000e000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM16K_MSIZE +CYREG_DMA_SRAM16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM_MBASE +CYREG_DMA_SRAM_MBASE EQU 0x2000f000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM_MSIZE +CYREG_DMA_SRAM_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_BASE +CYDEV_CLKDIST_BASE EQU 0x40004000 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_SIZE +CYDEV_CLKDIST_SIZE EQU 0x00000110 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_CR +CYREG_CLKDIST_CR EQU 0x40004000 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_LD +CYREG_CLKDIST_LD EQU 0x40004001 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_WRK0 +CYREG_CLKDIST_WRK0 EQU 0x40004002 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_WRK1 +CYREG_CLKDIST_WRK1 EQU 0x40004003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_MSTR0 +CYREG_CLKDIST_MSTR0 EQU 0x40004004 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_MSTR1 +CYREG_CLKDIST_MSTR1 EQU 0x40004005 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_BCFG0 +CYREG_CLKDIST_BCFG0 EQU 0x40004006 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_BCFG1 +CYREG_CLKDIST_BCFG1 EQU 0x40004007 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_BCFG2 +CYREG_CLKDIST_BCFG2 EQU 0x40004008 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_UCFG +CYREG_CLKDIST_UCFG EQU 0x40004009 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DLY0 +CYREG_CLKDIST_DLY0 EQU 0x4000400a + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DLY1 +CYREG_CLKDIST_DLY1 EQU 0x4000400b + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DMASK +CYREG_CLKDIST_DMASK EQU 0x40004010 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_AMASK +CYREG_CLKDIST_AMASK EQU 0x40004014 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_BASE +CYDEV_CLKDIST_DCFG0_BASE EQU 0x40004080 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_SIZE +CYDEV_CLKDIST_DCFG0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG0_CFG0 +CYREG_CLKDIST_DCFG0_CFG0 EQU 0x40004080 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG0_CFG1 +CYREG_CLKDIST_DCFG0_CFG1 EQU 0x40004081 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG0_CFG2 +CYREG_CLKDIST_DCFG0_CFG2 EQU 0x40004082 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_BASE +CYDEV_CLKDIST_DCFG1_BASE EQU 0x40004084 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_SIZE +CYDEV_CLKDIST_DCFG1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG1_CFG0 +CYREG_CLKDIST_DCFG1_CFG0 EQU 0x40004084 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG1_CFG1 +CYREG_CLKDIST_DCFG1_CFG1 EQU 0x40004085 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG1_CFG2 +CYREG_CLKDIST_DCFG1_CFG2 EQU 0x40004086 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_BASE +CYDEV_CLKDIST_DCFG2_BASE EQU 0x40004088 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_SIZE +CYDEV_CLKDIST_DCFG2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG2_CFG0 +CYREG_CLKDIST_DCFG2_CFG0 EQU 0x40004088 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG2_CFG1 +CYREG_CLKDIST_DCFG2_CFG1 EQU 0x40004089 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG2_CFG2 +CYREG_CLKDIST_DCFG2_CFG2 EQU 0x4000408a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_BASE +CYDEV_CLKDIST_DCFG3_BASE EQU 0x4000408c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_SIZE +CYDEV_CLKDIST_DCFG3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG3_CFG0 +CYREG_CLKDIST_DCFG3_CFG0 EQU 0x4000408c + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG3_CFG1 +CYREG_CLKDIST_DCFG3_CFG1 EQU 0x4000408d + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG3_CFG2 +CYREG_CLKDIST_DCFG3_CFG2 EQU 0x4000408e + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_BASE +CYDEV_CLKDIST_DCFG4_BASE EQU 0x40004090 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_SIZE +CYDEV_CLKDIST_DCFG4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG4_CFG0 +CYREG_CLKDIST_DCFG4_CFG0 EQU 0x40004090 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG4_CFG1 +CYREG_CLKDIST_DCFG4_CFG1 EQU 0x40004091 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG4_CFG2 +CYREG_CLKDIST_DCFG4_CFG2 EQU 0x40004092 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_BASE +CYDEV_CLKDIST_DCFG5_BASE EQU 0x40004094 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_SIZE +CYDEV_CLKDIST_DCFG5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG5_CFG0 +CYREG_CLKDIST_DCFG5_CFG0 EQU 0x40004094 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG5_CFG1 +CYREG_CLKDIST_DCFG5_CFG1 EQU 0x40004095 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG5_CFG2 +CYREG_CLKDIST_DCFG5_CFG2 EQU 0x40004096 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_BASE +CYDEV_CLKDIST_DCFG6_BASE EQU 0x40004098 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_SIZE +CYDEV_CLKDIST_DCFG6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG6_CFG0 +CYREG_CLKDIST_DCFG6_CFG0 EQU 0x40004098 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG6_CFG1 +CYREG_CLKDIST_DCFG6_CFG1 EQU 0x40004099 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG6_CFG2 +CYREG_CLKDIST_DCFG6_CFG2 EQU 0x4000409a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_BASE +CYDEV_CLKDIST_DCFG7_BASE EQU 0x4000409c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_SIZE +CYDEV_CLKDIST_DCFG7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG7_CFG0 +CYREG_CLKDIST_DCFG7_CFG0 EQU 0x4000409c + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG7_CFG1 +CYREG_CLKDIST_DCFG7_CFG1 EQU 0x4000409d + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG7_CFG2 +CYREG_CLKDIST_DCFG7_CFG2 EQU 0x4000409e + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_BASE +CYDEV_CLKDIST_ACFG0_BASE EQU 0x40004100 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_SIZE +CYDEV_CLKDIST_ACFG0_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG0_CFG0 +CYREG_CLKDIST_ACFG0_CFG0 EQU 0x40004100 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG0_CFG1 +CYREG_CLKDIST_ACFG0_CFG1 EQU 0x40004101 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG0_CFG2 +CYREG_CLKDIST_ACFG0_CFG2 EQU 0x40004102 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG0_CFG3 +CYREG_CLKDIST_ACFG0_CFG3 EQU 0x40004103 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_BASE +CYDEV_CLKDIST_ACFG1_BASE EQU 0x40004104 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_SIZE +CYDEV_CLKDIST_ACFG1_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG1_CFG0 +CYREG_CLKDIST_ACFG1_CFG0 EQU 0x40004104 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG1_CFG1 +CYREG_CLKDIST_ACFG1_CFG1 EQU 0x40004105 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG1_CFG2 +CYREG_CLKDIST_ACFG1_CFG2 EQU 0x40004106 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG1_CFG3 +CYREG_CLKDIST_ACFG1_CFG3 EQU 0x40004107 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_BASE +CYDEV_CLKDIST_ACFG2_BASE EQU 0x40004108 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_SIZE +CYDEV_CLKDIST_ACFG2_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG2_CFG0 +CYREG_CLKDIST_ACFG2_CFG0 EQU 0x40004108 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG2_CFG1 +CYREG_CLKDIST_ACFG2_CFG1 EQU 0x40004109 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG2_CFG2 +CYREG_CLKDIST_ACFG2_CFG2 EQU 0x4000410a + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG2_CFG3 +CYREG_CLKDIST_ACFG2_CFG3 EQU 0x4000410b + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_BASE +CYDEV_CLKDIST_ACFG3_BASE EQU 0x4000410c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_SIZE +CYDEV_CLKDIST_ACFG3_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG3_CFG0 +CYREG_CLKDIST_ACFG3_CFG0 EQU 0x4000410c + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG3_CFG1 +CYREG_CLKDIST_ACFG3_CFG1 EQU 0x4000410d + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG3_CFG2 +CYREG_CLKDIST_ACFG3_CFG2 EQU 0x4000410e + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG3_CFG3 +CYREG_CLKDIST_ACFG3_CFG3 EQU 0x4000410f + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_BASE +CYDEV_FASTCLK_BASE EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_SIZE +CYDEV_FASTCLK_SIZE EQU 0x00000026 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_IMO_BASE +CYDEV_FASTCLK_IMO_BASE EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_IMO_SIZE +CYDEV_FASTCLK_IMO_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_IMO_CR +CYREG_FASTCLK_IMO_CR EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_BASE +CYDEV_FASTCLK_XMHZ_BASE EQU 0x40004210 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_SIZE +CYDEV_FASTCLK_XMHZ_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_XMHZ_CSR +CYREG_FASTCLK_XMHZ_CSR EQU 0x40004210 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_XMHZ_CFG0 +CYREG_FASTCLK_XMHZ_CFG0 EQU 0x40004212 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_XMHZ_CFG1 +CYREG_FASTCLK_XMHZ_CFG1 EQU 0x40004213 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_BASE +CYDEV_FASTCLK_PLL_BASE EQU 0x40004220 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_SIZE +CYDEV_FASTCLK_PLL_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_PLL_CFG0 +CYREG_FASTCLK_PLL_CFG0 EQU 0x40004220 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_PLL_CFG1 +CYREG_FASTCLK_PLL_CFG1 EQU 0x40004221 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_PLL_P +CYREG_FASTCLK_PLL_P EQU 0x40004222 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_PLL_Q +CYREG_FASTCLK_PLL_Q EQU 0x40004223 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_PLL_SR +CYREG_FASTCLK_PLL_SR EQU 0x40004225 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_BASE +CYDEV_SLOWCLK_BASE EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_SIZE +CYDEV_SLOWCLK_SIZE EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_BASE +CYDEV_SLOWCLK_ILO_BASE EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_SIZE +CYDEV_SLOWCLK_ILO_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_SLOWCLK_ILO_CR0 +CYREG_SLOWCLK_ILO_CR0 EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYREG_SLOWCLK_ILO_CR1 +CYREG_SLOWCLK_ILO_CR1 EQU 0x40004301 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_BASE +CYDEV_SLOWCLK_X32_BASE EQU 0x40004308 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_SIZE +CYDEV_SLOWCLK_X32_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SLOWCLK_X32_CR +CYREG_SLOWCLK_X32_CR EQU 0x40004308 + ENDIF + IF :LNOT::DEF:CYREG_SLOWCLK_X32_CFG +CYREG_SLOWCLK_X32_CFG EQU 0x40004309 + ENDIF + IF :LNOT::DEF:CYREG_SLOWCLK_X32_TST +CYREG_SLOWCLK_X32_TST EQU 0x4000430a + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_BASE +CYDEV_BOOST_BASE EQU 0x40004320 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_SIZE +CYDEV_BOOST_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_CR0 +CYREG_BOOST_CR0 EQU 0x40004320 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_CR1 +CYREG_BOOST_CR1 EQU 0x40004321 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_CR2 +CYREG_BOOST_CR2 EQU 0x40004322 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_CR3 +CYREG_BOOST_CR3 EQU 0x40004323 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_SR +CYREG_BOOST_SR EQU 0x40004324 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_CR4 +CYREG_BOOST_CR4 EQU 0x40004325 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_SR2 +CYREG_BOOST_SR2 EQU 0x40004326 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_BASE +CYDEV_PWRSYS_BASE EQU 0x40004330 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_SIZE +CYDEV_PWRSYS_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_CR0 +CYREG_PWRSYS_CR0 EQU 0x40004330 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_CR1 +CYREG_PWRSYS_CR1 EQU 0x40004331 + ENDIF + IF :LNOT::DEF:CYDEV_PM_BASE +CYDEV_PM_BASE EQU 0x40004380 + ENDIF + IF :LNOT::DEF:CYDEV_PM_SIZE +CYDEV_PM_SIZE EQU 0x00000057 + ENDIF + IF :LNOT::DEF:CYREG_PM_TW_CFG0 +CYREG_PM_TW_CFG0 EQU 0x40004380 + ENDIF + IF :LNOT::DEF:CYREG_PM_TW_CFG1 +CYREG_PM_TW_CFG1 EQU 0x40004381 + ENDIF + IF :LNOT::DEF:CYREG_PM_TW_CFG2 +CYREG_PM_TW_CFG2 EQU 0x40004382 + ENDIF + IF :LNOT::DEF:CYREG_PM_WDT_CFG +CYREG_PM_WDT_CFG EQU 0x40004383 + ENDIF + IF :LNOT::DEF:CYREG_PM_WDT_CR +CYREG_PM_WDT_CR EQU 0x40004384 + ENDIF + IF :LNOT::DEF:CYREG_PM_INT_SR +CYREG_PM_INT_SR EQU 0x40004390 + ENDIF + IF :LNOT::DEF:CYREG_PM_MODE_CFG0 +CYREG_PM_MODE_CFG0 EQU 0x40004391 + ENDIF + IF :LNOT::DEF:CYREG_PM_MODE_CFG1 +CYREG_PM_MODE_CFG1 EQU 0x40004392 + ENDIF + IF :LNOT::DEF:CYREG_PM_MODE_CSR +CYREG_PM_MODE_CSR EQU 0x40004393 + ENDIF + IF :LNOT::DEF:CYREG_PM_USB_CR0 +CYREG_PM_USB_CR0 EQU 0x40004394 + ENDIF + IF :LNOT::DEF:CYREG_PM_WAKEUP_CFG0 +CYREG_PM_WAKEUP_CFG0 EQU 0x40004398 + ENDIF + IF :LNOT::DEF:CYREG_PM_WAKEUP_CFG1 +CYREG_PM_WAKEUP_CFG1 EQU 0x40004399 + ENDIF + IF :LNOT::DEF:CYREG_PM_WAKEUP_CFG2 +CYREG_PM_WAKEUP_CFG2 EQU 0x4000439a + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_BASE +CYDEV_PM_ACT_BASE EQU 0x400043a0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_SIZE +CYDEV_PM_ACT_SIZE EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG0 +CYREG_PM_ACT_CFG0 EQU 0x400043a0 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG1 +CYREG_PM_ACT_CFG1 EQU 0x400043a1 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG2 +CYREG_PM_ACT_CFG2 EQU 0x400043a2 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG3 +CYREG_PM_ACT_CFG3 EQU 0x400043a3 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG4 +CYREG_PM_ACT_CFG4 EQU 0x400043a4 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG5 +CYREG_PM_ACT_CFG5 EQU 0x400043a5 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG6 +CYREG_PM_ACT_CFG6 EQU 0x400043a6 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG7 +CYREG_PM_ACT_CFG7 EQU 0x400043a7 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG8 +CYREG_PM_ACT_CFG8 EQU 0x400043a8 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG9 +CYREG_PM_ACT_CFG9 EQU 0x400043a9 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG10 +CYREG_PM_ACT_CFG10 EQU 0x400043aa + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG11 +CYREG_PM_ACT_CFG11 EQU 0x400043ab + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG12 +CYREG_PM_ACT_CFG12 EQU 0x400043ac + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG13 +CYREG_PM_ACT_CFG13 EQU 0x400043ad + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_BASE +CYDEV_PM_STBY_BASE EQU 0x400043b0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_SIZE +CYDEV_PM_STBY_SIZE EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG0 +CYREG_PM_STBY_CFG0 EQU 0x400043b0 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG1 +CYREG_PM_STBY_CFG1 EQU 0x400043b1 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG2 +CYREG_PM_STBY_CFG2 EQU 0x400043b2 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG3 +CYREG_PM_STBY_CFG3 EQU 0x400043b3 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG4 +CYREG_PM_STBY_CFG4 EQU 0x400043b4 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG5 +CYREG_PM_STBY_CFG5 EQU 0x400043b5 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG6 +CYREG_PM_STBY_CFG6 EQU 0x400043b6 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG7 +CYREG_PM_STBY_CFG7 EQU 0x400043b7 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG8 +CYREG_PM_STBY_CFG8 EQU 0x400043b8 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG9 +CYREG_PM_STBY_CFG9 EQU 0x400043b9 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG10 +CYREG_PM_STBY_CFG10 EQU 0x400043ba + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG11 +CYREG_PM_STBY_CFG11 EQU 0x400043bb + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG12 +CYREG_PM_STBY_CFG12 EQU 0x400043bc + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG13 +CYREG_PM_STBY_CFG13 EQU 0x400043bd + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_BASE +CYDEV_PM_AVAIL_BASE EQU 0x400043c0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SIZE +CYDEV_PM_AVAIL_SIZE EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR0 +CYREG_PM_AVAIL_CR0 EQU 0x400043c0 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR1 +CYREG_PM_AVAIL_CR1 EQU 0x400043c1 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR2 +CYREG_PM_AVAIL_CR2 EQU 0x400043c2 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR3 +CYREG_PM_AVAIL_CR3 EQU 0x400043c3 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR4 +CYREG_PM_AVAIL_CR4 EQU 0x400043c4 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR5 +CYREG_PM_AVAIL_CR5 EQU 0x400043c5 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR6 +CYREG_PM_AVAIL_CR6 EQU 0x400043c6 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR0 +CYREG_PM_AVAIL_SR0 EQU 0x400043d0 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR1 +CYREG_PM_AVAIL_SR1 EQU 0x400043d1 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR2 +CYREG_PM_AVAIL_SR2 EQU 0x400043d2 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR3 +CYREG_PM_AVAIL_SR3 EQU 0x400043d3 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR4 +CYREG_PM_AVAIL_SR4 EQU 0x400043d4 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR5 +CYREG_PM_AVAIL_SR5 EQU 0x400043d5 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR6 +CYREG_PM_AVAIL_SR6 EQU 0x400043d6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_BASE +CYDEV_PICU_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SIZE +CYDEV_PICU_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_BASE +CYDEV_PICU_INTTYPE_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_SIZE +CYDEV_PICU_INTTYPE_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_BASE +CYDEV_PICU_INTTYPE_PICU0_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_SIZE +CYDEV_PICU_INTTYPE_PICU0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE0 +CYREG_PICU0_INTTYPE0 EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE1 +CYREG_PICU0_INTTYPE1 EQU 0x40004501 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE2 +CYREG_PICU0_INTTYPE2 EQU 0x40004502 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE3 +CYREG_PICU0_INTTYPE3 EQU 0x40004503 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE4 +CYREG_PICU0_INTTYPE4 EQU 0x40004504 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE5 +CYREG_PICU0_INTTYPE5 EQU 0x40004505 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE6 +CYREG_PICU0_INTTYPE6 EQU 0x40004506 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE7 +CYREG_PICU0_INTTYPE7 EQU 0x40004507 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_BASE +CYDEV_PICU_INTTYPE_PICU1_BASE EQU 0x40004508 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_SIZE +CYDEV_PICU_INTTYPE_PICU1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE0 +CYREG_PICU1_INTTYPE0 EQU 0x40004508 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE1 +CYREG_PICU1_INTTYPE1 EQU 0x40004509 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE2 +CYREG_PICU1_INTTYPE2 EQU 0x4000450a + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE3 +CYREG_PICU1_INTTYPE3 EQU 0x4000450b + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE4 +CYREG_PICU1_INTTYPE4 EQU 0x4000450c + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE5 +CYREG_PICU1_INTTYPE5 EQU 0x4000450d + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE6 +CYREG_PICU1_INTTYPE6 EQU 0x4000450e + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE7 +CYREG_PICU1_INTTYPE7 EQU 0x4000450f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_BASE +CYDEV_PICU_INTTYPE_PICU2_BASE EQU 0x40004510 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_SIZE +CYDEV_PICU_INTTYPE_PICU2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE0 +CYREG_PICU2_INTTYPE0 EQU 0x40004510 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE1 +CYREG_PICU2_INTTYPE1 EQU 0x40004511 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE2 +CYREG_PICU2_INTTYPE2 EQU 0x40004512 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE3 +CYREG_PICU2_INTTYPE3 EQU 0x40004513 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE4 +CYREG_PICU2_INTTYPE4 EQU 0x40004514 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE5 +CYREG_PICU2_INTTYPE5 EQU 0x40004515 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE6 +CYREG_PICU2_INTTYPE6 EQU 0x40004516 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE7 +CYREG_PICU2_INTTYPE7 EQU 0x40004517 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_BASE +CYDEV_PICU_INTTYPE_PICU3_BASE EQU 0x40004518 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_SIZE +CYDEV_PICU_INTTYPE_PICU3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE0 +CYREG_PICU3_INTTYPE0 EQU 0x40004518 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE1 +CYREG_PICU3_INTTYPE1 EQU 0x40004519 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE2 +CYREG_PICU3_INTTYPE2 EQU 0x4000451a + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE3 +CYREG_PICU3_INTTYPE3 EQU 0x4000451b + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE4 +CYREG_PICU3_INTTYPE4 EQU 0x4000451c + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE5 +CYREG_PICU3_INTTYPE5 EQU 0x4000451d + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE6 +CYREG_PICU3_INTTYPE6 EQU 0x4000451e + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE7 +CYREG_PICU3_INTTYPE7 EQU 0x4000451f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_BASE +CYDEV_PICU_INTTYPE_PICU4_BASE EQU 0x40004520 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_SIZE +CYDEV_PICU_INTTYPE_PICU4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE0 +CYREG_PICU4_INTTYPE0 EQU 0x40004520 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE1 +CYREG_PICU4_INTTYPE1 EQU 0x40004521 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE2 +CYREG_PICU4_INTTYPE2 EQU 0x40004522 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE3 +CYREG_PICU4_INTTYPE3 EQU 0x40004523 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE4 +CYREG_PICU4_INTTYPE4 EQU 0x40004524 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE5 +CYREG_PICU4_INTTYPE5 EQU 0x40004525 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE6 +CYREG_PICU4_INTTYPE6 EQU 0x40004526 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE7 +CYREG_PICU4_INTTYPE7 EQU 0x40004527 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_BASE +CYDEV_PICU_INTTYPE_PICU5_BASE EQU 0x40004528 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_SIZE +CYDEV_PICU_INTTYPE_PICU5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE0 +CYREG_PICU5_INTTYPE0 EQU 0x40004528 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE1 +CYREG_PICU5_INTTYPE1 EQU 0x40004529 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE2 +CYREG_PICU5_INTTYPE2 EQU 0x4000452a + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE3 +CYREG_PICU5_INTTYPE3 EQU 0x4000452b + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE4 +CYREG_PICU5_INTTYPE4 EQU 0x4000452c + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE5 +CYREG_PICU5_INTTYPE5 EQU 0x4000452d + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE6 +CYREG_PICU5_INTTYPE6 EQU 0x4000452e + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE7 +CYREG_PICU5_INTTYPE7 EQU 0x4000452f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_BASE +CYDEV_PICU_INTTYPE_PICU6_BASE EQU 0x40004530 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_SIZE +CYDEV_PICU_INTTYPE_PICU6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE0 +CYREG_PICU6_INTTYPE0 EQU 0x40004530 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE1 +CYREG_PICU6_INTTYPE1 EQU 0x40004531 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE2 +CYREG_PICU6_INTTYPE2 EQU 0x40004532 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE3 +CYREG_PICU6_INTTYPE3 EQU 0x40004533 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE4 +CYREG_PICU6_INTTYPE4 EQU 0x40004534 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE5 +CYREG_PICU6_INTTYPE5 EQU 0x40004535 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE6 +CYREG_PICU6_INTTYPE6 EQU 0x40004536 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE7 +CYREG_PICU6_INTTYPE7 EQU 0x40004537 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_BASE +CYDEV_PICU_INTTYPE_PICU12_BASE EQU 0x40004560 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_SIZE +CYDEV_PICU_INTTYPE_PICU12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE0 +CYREG_PICU12_INTTYPE0 EQU 0x40004560 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE1 +CYREG_PICU12_INTTYPE1 EQU 0x40004561 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE2 +CYREG_PICU12_INTTYPE2 EQU 0x40004562 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE3 +CYREG_PICU12_INTTYPE3 EQU 0x40004563 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE4 +CYREG_PICU12_INTTYPE4 EQU 0x40004564 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE5 +CYREG_PICU12_INTTYPE5 EQU 0x40004565 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE6 +CYREG_PICU12_INTTYPE6 EQU 0x40004566 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE7 +CYREG_PICU12_INTTYPE7 EQU 0x40004567 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_BASE +CYDEV_PICU_INTTYPE_PICU15_BASE EQU 0x40004578 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_SIZE +CYDEV_PICU_INTTYPE_PICU15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE0 +CYREG_PICU15_INTTYPE0 EQU 0x40004578 + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE1 +CYREG_PICU15_INTTYPE1 EQU 0x40004579 + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE2 +CYREG_PICU15_INTTYPE2 EQU 0x4000457a + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE3 +CYREG_PICU15_INTTYPE3 EQU 0x4000457b + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE4 +CYREG_PICU15_INTTYPE4 EQU 0x4000457c + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE5 +CYREG_PICU15_INTTYPE5 EQU 0x4000457d + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE6 +CYREG_PICU15_INTTYPE6 EQU 0x4000457e + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE7 +CYREG_PICU15_INTTYPE7 EQU 0x4000457f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_BASE +CYDEV_PICU_STAT_BASE EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_SIZE +CYDEV_PICU_STAT_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_BASE +CYDEV_PICU_STAT_PICU0_BASE EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_SIZE +CYDEV_PICU_STAT_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTSTAT +CYREG_PICU0_INTSTAT EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_BASE +CYDEV_PICU_STAT_PICU1_BASE EQU 0x40004581 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_SIZE +CYDEV_PICU_STAT_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTSTAT +CYREG_PICU1_INTSTAT EQU 0x40004581 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_BASE +CYDEV_PICU_STAT_PICU2_BASE EQU 0x40004582 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_SIZE +CYDEV_PICU_STAT_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTSTAT +CYREG_PICU2_INTSTAT EQU 0x40004582 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_BASE +CYDEV_PICU_STAT_PICU3_BASE EQU 0x40004583 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_SIZE +CYDEV_PICU_STAT_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTSTAT +CYREG_PICU3_INTSTAT EQU 0x40004583 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_BASE +CYDEV_PICU_STAT_PICU4_BASE EQU 0x40004584 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_SIZE +CYDEV_PICU_STAT_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTSTAT +CYREG_PICU4_INTSTAT EQU 0x40004584 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_BASE +CYDEV_PICU_STAT_PICU5_BASE EQU 0x40004585 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_SIZE +CYDEV_PICU_STAT_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTSTAT +CYREG_PICU5_INTSTAT EQU 0x40004585 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_BASE +CYDEV_PICU_STAT_PICU6_BASE EQU 0x40004586 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_SIZE +CYDEV_PICU_STAT_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTSTAT +CYREG_PICU6_INTSTAT EQU 0x40004586 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_BASE +CYDEV_PICU_STAT_PICU12_BASE EQU 0x4000458c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_SIZE +CYDEV_PICU_STAT_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTSTAT +CYREG_PICU12_INTSTAT EQU 0x4000458c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_BASE +CYDEV_PICU_STAT_PICU15_BASE EQU 0x4000458f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_SIZE +CYDEV_PICU_STAT_PICU15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTSTAT +CYREG_PICU15_INTSTAT EQU 0x4000458f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_BASE +CYDEV_PICU_SNAP_BASE EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_SIZE +CYDEV_PICU_SNAP_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_BASE +CYDEV_PICU_SNAP_PICU0_BASE EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_SIZE +CYDEV_PICU_SNAP_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_SNAP +CYREG_PICU0_SNAP EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_BASE +CYDEV_PICU_SNAP_PICU1_BASE EQU 0x40004591 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_SIZE +CYDEV_PICU_SNAP_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_SNAP +CYREG_PICU1_SNAP EQU 0x40004591 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_BASE +CYDEV_PICU_SNAP_PICU2_BASE EQU 0x40004592 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_SIZE +CYDEV_PICU_SNAP_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_SNAP +CYREG_PICU2_SNAP EQU 0x40004592 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_BASE +CYDEV_PICU_SNAP_PICU3_BASE EQU 0x40004593 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_SIZE +CYDEV_PICU_SNAP_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_SNAP +CYREG_PICU3_SNAP EQU 0x40004593 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_BASE +CYDEV_PICU_SNAP_PICU4_BASE EQU 0x40004594 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_SIZE +CYDEV_PICU_SNAP_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_SNAP +CYREG_PICU4_SNAP EQU 0x40004594 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_BASE +CYDEV_PICU_SNAP_PICU5_BASE EQU 0x40004595 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_SIZE +CYDEV_PICU_SNAP_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_SNAP +CYREG_PICU5_SNAP EQU 0x40004595 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_BASE +CYDEV_PICU_SNAP_PICU6_BASE EQU 0x40004596 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_SIZE +CYDEV_PICU_SNAP_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_SNAP +CYREG_PICU6_SNAP EQU 0x40004596 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_BASE +CYDEV_PICU_SNAP_PICU12_BASE EQU 0x4000459c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_SIZE +CYDEV_PICU_SNAP_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_SNAP +CYREG_PICU12_SNAP EQU 0x4000459c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_BASE +CYDEV_PICU_SNAP_PICU_15_BASE EQU 0x4000459f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_SIZE +CYDEV_PICU_SNAP_PICU_15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU_15_SNAP_15 +CYREG_PICU_15_SNAP_15 EQU 0x4000459f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_BASE +CYDEV_PICU_DISABLE_COR_BASE EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_SIZE +CYDEV_PICU_DISABLE_COR_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_BASE +CYDEV_PICU_DISABLE_COR_PICU0_BASE EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_SIZE +CYDEV_PICU_DISABLE_COR_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_DISABLE_COR +CYREG_PICU0_DISABLE_COR EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_BASE +CYDEV_PICU_DISABLE_COR_PICU1_BASE EQU 0x400045a1 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_SIZE +CYDEV_PICU_DISABLE_COR_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_DISABLE_COR +CYREG_PICU1_DISABLE_COR EQU 0x400045a1 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_BASE +CYDEV_PICU_DISABLE_COR_PICU2_BASE EQU 0x400045a2 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_SIZE +CYDEV_PICU_DISABLE_COR_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_DISABLE_COR +CYREG_PICU2_DISABLE_COR EQU 0x400045a2 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_BASE +CYDEV_PICU_DISABLE_COR_PICU3_BASE EQU 0x400045a3 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_SIZE +CYDEV_PICU_DISABLE_COR_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_DISABLE_COR +CYREG_PICU3_DISABLE_COR EQU 0x400045a3 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_BASE +CYDEV_PICU_DISABLE_COR_PICU4_BASE EQU 0x400045a4 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_SIZE +CYDEV_PICU_DISABLE_COR_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_DISABLE_COR +CYREG_PICU4_DISABLE_COR EQU 0x400045a4 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_BASE +CYDEV_PICU_DISABLE_COR_PICU5_BASE EQU 0x400045a5 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_SIZE +CYDEV_PICU_DISABLE_COR_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_DISABLE_COR +CYREG_PICU5_DISABLE_COR EQU 0x400045a5 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_BASE +CYDEV_PICU_DISABLE_COR_PICU6_BASE EQU 0x400045a6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_SIZE +CYDEV_PICU_DISABLE_COR_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_DISABLE_COR +CYREG_PICU6_DISABLE_COR EQU 0x400045a6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_BASE +CYDEV_PICU_DISABLE_COR_PICU12_BASE EQU 0x400045ac + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_SIZE +CYDEV_PICU_DISABLE_COR_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_DISABLE_COR +CYREG_PICU12_DISABLE_COR EQU 0x400045ac + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_BASE +CYDEV_PICU_DISABLE_COR_PICU15_BASE EQU 0x400045af + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_SIZE +CYDEV_PICU_DISABLE_COR_PICU15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU15_DISABLE_COR +CYREG_PICU15_DISABLE_COR EQU 0x400045af + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_BASE +CYDEV_MFGCFG_BASE EQU 0x40004600 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_SIZE +CYDEV_MFGCFG_SIZE EQU 0x000000ed + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_BASE +CYDEV_MFGCFG_ANAIF_BASE EQU 0x40004600 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SIZE +CYDEV_MFGCFG_ANAIF_SIZE EQU 0x00000038 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_BASE +CYDEV_MFGCFG_ANAIF_DAC0_BASE EQU 0x40004608 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_SIZE +CYDEV_MFGCFG_ANAIF_DAC0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_TR +CYREG_DAC0_TR EQU 0x40004608 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_BASE +CYDEV_MFGCFG_ANAIF_DAC1_BASE EQU 0x40004609 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_SIZE +CYDEV_MFGCFG_ANAIF_DAC1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_TR +CYREG_DAC1_TR EQU 0x40004609 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_BASE +CYDEV_MFGCFG_ANAIF_DAC2_BASE EQU 0x4000460a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_SIZE +CYDEV_MFGCFG_ANAIF_DAC2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_TR +CYREG_DAC2_TR EQU 0x4000460a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_BASE +CYDEV_MFGCFG_ANAIF_DAC3_BASE EQU 0x4000460b + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_SIZE +CYDEV_MFGCFG_ANAIF_DAC3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC3_TR +CYREG_DAC3_TR EQU 0x4000460b + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE EQU 0x40004610 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_NPUMP_DSM_TR0 +CYREG_NPUMP_DSM_TR0 EQU 0x40004610 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE EQU 0x40004611 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_NPUMP_SC_TR0 +CYREG_NPUMP_SC_TR0 EQU 0x40004611 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE EQU 0x40004612 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_NPUMP_OPAMP_TR0 +CYREG_NPUMP_OPAMP_TR0 EQU 0x40004612 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_BASE +CYDEV_MFGCFG_ANAIF_SAR0_BASE EQU 0x40004614 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_SIZE +CYDEV_MFGCFG_ANAIF_SAR0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_TR0 +CYREG_SAR0_TR0 EQU 0x40004614 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_BASE +CYDEV_MFGCFG_ANAIF_SAR1_BASE EQU 0x40004616 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_SIZE +CYDEV_MFGCFG_ANAIF_SAR1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_TR0 +CYREG_SAR1_TR0 EQU 0x40004616 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_BASE +CYDEV_MFGCFG_ANAIF_OPAMP0_BASE EQU 0x40004620 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_TR0 +CYREG_OPAMP0_TR0 EQU 0x40004620 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_TR1 +CYREG_OPAMP0_TR1 EQU 0x40004621 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_BASE +CYDEV_MFGCFG_ANAIF_OPAMP1_BASE EQU 0x40004622 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_TR0 +CYREG_OPAMP1_TR0 EQU 0x40004622 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_TR1 +CYREG_OPAMP1_TR1 EQU 0x40004623 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_BASE +CYDEV_MFGCFG_ANAIF_OPAMP2_BASE EQU 0x40004624 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_TR0 +CYREG_OPAMP2_TR0 EQU 0x40004624 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_TR1 +CYREG_OPAMP2_TR1 EQU 0x40004625 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_BASE +CYDEV_MFGCFG_ANAIF_OPAMP3_BASE EQU 0x40004626 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_TR0 +CYREG_OPAMP3_TR0 EQU 0x40004626 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_TR1 +CYREG_OPAMP3_TR1 EQU 0x40004627 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_BASE +CYDEV_MFGCFG_ANAIF_CMP0_BASE EQU 0x40004630 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_SIZE +CYDEV_MFGCFG_ANAIF_CMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_TR0 +CYREG_CMP0_TR0 EQU 0x40004630 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_TR1 +CYREG_CMP0_TR1 EQU 0x40004631 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_BASE +CYDEV_MFGCFG_ANAIF_CMP1_BASE EQU 0x40004632 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_SIZE +CYDEV_MFGCFG_ANAIF_CMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CMP1_TR0 +CYREG_CMP1_TR0 EQU 0x40004632 + ENDIF + IF :LNOT::DEF:CYREG_CMP1_TR1 +CYREG_CMP1_TR1 EQU 0x40004633 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_BASE +CYDEV_MFGCFG_ANAIF_CMP2_BASE EQU 0x40004634 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_SIZE +CYDEV_MFGCFG_ANAIF_CMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_TR0 +CYREG_CMP2_TR0 EQU 0x40004634 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_TR1 +CYREG_CMP2_TR1 EQU 0x40004635 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_BASE +CYDEV_MFGCFG_ANAIF_CMP3_BASE EQU 0x40004636 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_SIZE +CYDEV_MFGCFG_ANAIF_CMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CMP3_TR0 +CYREG_CMP3_TR0 EQU 0x40004636 + ENDIF + IF :LNOT::DEF:CYREG_CMP3_TR1 +CYREG_CMP3_TR1 EQU 0x40004637 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BASE +CYDEV_MFGCFG_PWRSYS_BASE EQU 0x40004680 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_SIZE +CYDEV_MFGCFG_PWRSYS_SIZE EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_HIB_TR0 +CYREG_PWRSYS_HIB_TR0 EQU 0x40004680 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_HIB_TR1 +CYREG_PWRSYS_HIB_TR1 EQU 0x40004681 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_I2C_TR +CYREG_PWRSYS_I2C_TR EQU 0x40004682 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_SLP_TR +CYREG_PWRSYS_SLP_TR EQU 0x40004683 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_BUZZ_TR +CYREG_PWRSYS_BUZZ_TR EQU 0x40004684 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_WAKE_TR0 +CYREG_PWRSYS_WAKE_TR0 EQU 0x40004685 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_WAKE_TR1 +CYREG_PWRSYS_WAKE_TR1 EQU 0x40004686 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_BREF_TR +CYREG_PWRSYS_BREF_TR EQU 0x40004687 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_BG_TR +CYREG_PWRSYS_BG_TR EQU 0x40004688 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_WAKE_TR2 +CYREG_PWRSYS_WAKE_TR2 EQU 0x40004689 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_WAKE_TR3 +CYREG_PWRSYS_WAKE_TR3 EQU 0x4000468a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_BASE +CYDEV_MFGCFG_ILO_BASE EQU 0x40004690 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_SIZE +CYDEV_MFGCFG_ILO_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_ILO_TR0 +CYREG_ILO_TR0 EQU 0x40004690 + ENDIF + IF :LNOT::DEF:CYREG_ILO_TR1 +CYREG_ILO_TR1 EQU 0x40004691 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_X32_BASE +CYDEV_MFGCFG_X32_BASE EQU 0x40004698 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_X32_SIZE +CYDEV_MFGCFG_X32_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_X32_TR +CYREG_X32_TR EQU 0x40004698 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_BASE +CYDEV_MFGCFG_IMO_BASE EQU 0x400046a0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_SIZE +CYDEV_MFGCFG_IMO_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_IMO_TR0 +CYREG_IMO_TR0 EQU 0x400046a0 + ENDIF + IF :LNOT::DEF:CYREG_IMO_TR1 +CYREG_IMO_TR1 EQU 0x400046a1 + ENDIF + IF :LNOT::DEF:CYREG_IMO_GAIN +CYREG_IMO_GAIN EQU 0x400046a2 + ENDIF + IF :LNOT::DEF:CYREG_IMO_C36M +CYREG_IMO_C36M EQU 0x400046a3 + ENDIF + IF :LNOT::DEF:CYREG_IMO_TR2 +CYREG_IMO_TR2 EQU 0x400046a4 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_BASE +CYDEV_MFGCFG_XMHZ_BASE EQU 0x400046a8 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_SIZE +CYDEV_MFGCFG_XMHZ_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_XMHZ_TR +CYREG_XMHZ_TR EQU 0x400046a8 + ENDIF + IF :LNOT::DEF:CYREG_MFGCFG_DLY +CYREG_MFGCFG_DLY EQU 0x400046c0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_BASE +CYDEV_MFGCFG_MLOGIC_BASE EQU 0x400046e0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SIZE +CYDEV_MFGCFG_MLOGIC_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_DMPSTR +CYREG_MLOGIC_DMPSTR EQU 0x400046e2 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_BASE +CYDEV_MFGCFG_MLOGIC_SEG_BASE EQU 0x400046e4 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_SIZE +CYDEV_MFGCFG_MLOGIC_SEG_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_SEG_CR +CYREG_MLOGIC_SEG_CR EQU 0x400046e4 + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_SEG_CFG0 +CYREG_MLOGIC_SEG_CFG0 EQU 0x400046e5 + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_DEBUG +CYREG_MLOGIC_DEBUG EQU 0x400046e8 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE +CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE EQU 0x400046ea + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE +CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_CPU_SCR_CPU_SCR +CYREG_MLOGIC_CPU_SCR_CPU_SCR EQU 0x400046ea + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_REV_ID +CYREG_MLOGIC_REV_ID EQU 0x400046ec + ENDIF + IF :LNOT::DEF:CYDEV_RESET_BASE +CYDEV_RESET_BASE EQU 0x400046f0 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SIZE +CYDEV_RESET_SIZE EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYREG_RESET_IPOR_CR0 +CYREG_RESET_IPOR_CR0 EQU 0x400046f0 + ENDIF + IF :LNOT::DEF:CYREG_RESET_IPOR_CR1 +CYREG_RESET_IPOR_CR1 EQU 0x400046f1 + ENDIF + IF :LNOT::DEF:CYREG_RESET_IPOR_CR2 +CYREG_RESET_IPOR_CR2 EQU 0x400046f2 + ENDIF + IF :LNOT::DEF:CYREG_RESET_IPOR_CR3 +CYREG_RESET_IPOR_CR3 EQU 0x400046f3 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR0 +CYREG_RESET_CR0 EQU 0x400046f4 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR1 +CYREG_RESET_CR1 EQU 0x400046f5 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR2 +CYREG_RESET_CR2 EQU 0x400046f6 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR3 +CYREG_RESET_CR3 EQU 0x400046f7 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR4 +CYREG_RESET_CR4 EQU 0x400046f8 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR5 +CYREG_RESET_CR5 EQU 0x400046f9 + ENDIF + IF :LNOT::DEF:CYREG_RESET_SR0 +CYREG_RESET_SR0 EQU 0x400046fa + ENDIF + IF :LNOT::DEF:CYREG_RESET_SR1 +CYREG_RESET_SR1 EQU 0x400046fb + ENDIF + IF :LNOT::DEF:CYREG_RESET_SR2 +CYREG_RESET_SR2 EQU 0x400046fc + ENDIF + IF :LNOT::DEF:CYREG_RESET_SR3 +CYREG_RESET_SR3 EQU 0x400046fd + ENDIF + IF :LNOT::DEF:CYREG_RESET_TR +CYREG_RESET_TR EQU 0x400046fe + ENDIF + IF :LNOT::DEF:CYDEV_SPC_BASE +CYDEV_SPC_BASE EQU 0x40004700 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_SIZE +CYDEV_SPC_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_SPC_FM_EE_CR +CYREG_SPC_FM_EE_CR EQU 0x40004700 + ENDIF + IF :LNOT::DEF:CYREG_SPC_FM_EE_WAKE_CNT +CYREG_SPC_FM_EE_WAKE_CNT EQU 0x40004701 + ENDIF + IF :LNOT::DEF:CYREG_SPC_EE_SCR +CYREG_SPC_EE_SCR EQU 0x40004702 + ENDIF + IF :LNOT::DEF:CYREG_SPC_EE_ERR +CYREG_SPC_EE_ERR EQU 0x40004703 + ENDIF + IF :LNOT::DEF:CYREG_SPC_CPU_DATA +CYREG_SPC_CPU_DATA EQU 0x40004720 + ENDIF + IF :LNOT::DEF:CYREG_SPC_DMA_DATA +CYREG_SPC_DMA_DATA EQU 0x40004721 + ENDIF + IF :LNOT::DEF:CYREG_SPC_SR +CYREG_SPC_SR EQU 0x40004722 + ENDIF + IF :LNOT::DEF:CYREG_SPC_CR +CYREG_SPC_CR EQU 0x40004723 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_BASE +CYDEV_SPC_DMM_MAP_BASE EQU 0x40004780 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_SIZE +CYDEV_SPC_DMM_MAP_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYREG_SPC_DMM_MAP_SRAM_MBASE +CYREG_SPC_DMM_MAP_SRAM_MBASE EQU 0x40004780 + ENDIF + IF :LNOT::DEF:CYREG_SPC_DMM_MAP_SRAM_MSIZE +CYREG_SPC_DMM_MAP_SRAM_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_BASE +CYDEV_CACHE_BASE EQU 0x40004800 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_SIZE +CYDEV_CACHE_SIZE EQU 0x0000009c + ENDIF + IF :LNOT::DEF:CYREG_CACHE_CC_CTL +CYREG_CACHE_CC_CTL EQU 0x40004800 + ENDIF + IF :LNOT::DEF:CYREG_CACHE_ECC_CORR +CYREG_CACHE_ECC_CORR EQU 0x40004880 + ENDIF + IF :LNOT::DEF:CYREG_CACHE_ECC_ERR +CYREG_CACHE_ECC_ERR EQU 0x40004888 + ENDIF + IF :LNOT::DEF:CYREG_CACHE_FLASH_ERR +CYREG_CACHE_FLASH_ERR EQU 0x40004890 + ENDIF + IF :LNOT::DEF:CYREG_CACHE_HITMISS +CYREG_CACHE_HITMISS EQU 0x40004898 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_BASE +CYDEV_I2C_BASE EQU 0x40004900 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_SIZE +CYDEV_I2C_SIZE EQU 0x000000e1 + ENDIF + IF :LNOT::DEF:CYREG_I2C_XCFG +CYREG_I2C_XCFG EQU 0x400049c8 + ENDIF + IF :LNOT::DEF:CYREG_I2C_ADR +CYREG_I2C_ADR EQU 0x400049ca + ENDIF + IF :LNOT::DEF:CYREG_I2C_CFG +CYREG_I2C_CFG EQU 0x400049d6 + ENDIF + IF :LNOT::DEF:CYREG_I2C_CSR +CYREG_I2C_CSR EQU 0x400049d7 + ENDIF + IF :LNOT::DEF:CYREG_I2C_D +CYREG_I2C_D EQU 0x400049d8 + ENDIF + IF :LNOT::DEF:CYREG_I2C_MCSR +CYREG_I2C_MCSR EQU 0x400049d9 + ENDIF + IF :LNOT::DEF:CYREG_I2C_CLK_DIV1 +CYREG_I2C_CLK_DIV1 EQU 0x400049db + ENDIF + IF :LNOT::DEF:CYREG_I2C_CLK_DIV2 +CYREG_I2C_CLK_DIV2 EQU 0x400049dc + ENDIF + IF :LNOT::DEF:CYREG_I2C_TMOUT_CSR +CYREG_I2C_TMOUT_CSR EQU 0x400049dd + ENDIF + IF :LNOT::DEF:CYREG_I2C_TMOUT_SR +CYREG_I2C_TMOUT_SR EQU 0x400049de + ENDIF + IF :LNOT::DEF:CYREG_I2C_TMOUT_CFG0 +CYREG_I2C_TMOUT_CFG0 EQU 0x400049df + ENDIF + IF :LNOT::DEF:CYREG_I2C_TMOUT_CFG1 +CYREG_I2C_TMOUT_CFG1 EQU 0x400049e0 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_BASE +CYDEV_DEC_BASE EQU 0x40004e00 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_SIZE +CYDEV_DEC_SIZE EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYREG_DEC_CR +CYREG_DEC_CR EQU 0x40004e00 + ENDIF + IF :LNOT::DEF:CYREG_DEC_SR +CYREG_DEC_SR EQU 0x40004e01 + ENDIF + IF :LNOT::DEF:CYREG_DEC_SHIFT1 +CYREG_DEC_SHIFT1 EQU 0x40004e02 + ENDIF + IF :LNOT::DEF:CYREG_DEC_SHIFT2 +CYREG_DEC_SHIFT2 EQU 0x40004e03 + ENDIF + IF :LNOT::DEF:CYREG_DEC_DR2 +CYREG_DEC_DR2 EQU 0x40004e04 + ENDIF + IF :LNOT::DEF:CYREG_DEC_DR2H +CYREG_DEC_DR2H EQU 0x40004e05 + ENDIF + IF :LNOT::DEF:CYREG_DEC_DR1 +CYREG_DEC_DR1 EQU 0x40004e06 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OCOR +CYREG_DEC_OCOR EQU 0x40004e08 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OCORM +CYREG_DEC_OCORM EQU 0x40004e09 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OCORH +CYREG_DEC_OCORH EQU 0x40004e0a + ENDIF + IF :LNOT::DEF:CYREG_DEC_GCOR +CYREG_DEC_GCOR EQU 0x40004e0c + ENDIF + IF :LNOT::DEF:CYREG_DEC_GCORH +CYREG_DEC_GCORH EQU 0x40004e0d + ENDIF + IF :LNOT::DEF:CYREG_DEC_GVAL +CYREG_DEC_GVAL EQU 0x40004e0e + ENDIF + IF :LNOT::DEF:CYREG_DEC_OUTSAMP +CYREG_DEC_OUTSAMP EQU 0x40004e10 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OUTSAMPM +CYREG_DEC_OUTSAMPM EQU 0x40004e11 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OUTSAMPH +CYREG_DEC_OUTSAMPH EQU 0x40004e12 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OUTSAMPS +CYREG_DEC_OUTSAMPS EQU 0x40004e13 + ENDIF + IF :LNOT::DEF:CYREG_DEC_COHER +CYREG_DEC_COHER EQU 0x40004e14 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_BASE +CYDEV_TMR0_BASE EQU 0x40004f00 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_SIZE +CYDEV_TMR0_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CFG0 +CYREG_TMR0_CFG0 EQU 0x40004f00 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CFG1 +CYREG_TMR0_CFG1 EQU 0x40004f01 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CFG2 +CYREG_TMR0_CFG2 EQU 0x40004f02 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_SR0 +CYREG_TMR0_SR0 EQU 0x40004f03 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_PER0 +CYREG_TMR0_PER0 EQU 0x40004f04 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_PER1 +CYREG_TMR0_PER1 EQU 0x40004f05 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CNT_CMP0 +CYREG_TMR0_CNT_CMP0 EQU 0x40004f06 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CNT_CMP1 +CYREG_TMR0_CNT_CMP1 EQU 0x40004f07 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CAP0 +CYREG_TMR0_CAP0 EQU 0x40004f08 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CAP1 +CYREG_TMR0_CAP1 EQU 0x40004f09 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_RT0 +CYREG_TMR0_RT0 EQU 0x40004f0a + ENDIF + IF :LNOT::DEF:CYREG_TMR0_RT1 +CYREG_TMR0_RT1 EQU 0x40004f0b + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_BASE +CYDEV_TMR1_BASE EQU 0x40004f0c + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_SIZE +CYDEV_TMR1_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CFG0 +CYREG_TMR1_CFG0 EQU 0x40004f0c + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CFG1 +CYREG_TMR1_CFG1 EQU 0x40004f0d + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CFG2 +CYREG_TMR1_CFG2 EQU 0x40004f0e + ENDIF + IF :LNOT::DEF:CYREG_TMR1_SR0 +CYREG_TMR1_SR0 EQU 0x40004f0f + ENDIF + IF :LNOT::DEF:CYREG_TMR1_PER0 +CYREG_TMR1_PER0 EQU 0x40004f10 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_PER1 +CYREG_TMR1_PER1 EQU 0x40004f11 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CNT_CMP0 +CYREG_TMR1_CNT_CMP0 EQU 0x40004f12 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CNT_CMP1 +CYREG_TMR1_CNT_CMP1 EQU 0x40004f13 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CAP0 +CYREG_TMR1_CAP0 EQU 0x40004f14 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CAP1 +CYREG_TMR1_CAP1 EQU 0x40004f15 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_RT0 +CYREG_TMR1_RT0 EQU 0x40004f16 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_RT1 +CYREG_TMR1_RT1 EQU 0x40004f17 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_BASE +CYDEV_TMR2_BASE EQU 0x40004f18 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_SIZE +CYDEV_TMR2_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CFG0 +CYREG_TMR2_CFG0 EQU 0x40004f18 + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CFG1 +CYREG_TMR2_CFG1 EQU 0x40004f19 + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CFG2 +CYREG_TMR2_CFG2 EQU 0x40004f1a + ENDIF + IF :LNOT::DEF:CYREG_TMR2_SR0 +CYREG_TMR2_SR0 EQU 0x40004f1b + ENDIF + IF :LNOT::DEF:CYREG_TMR2_PER0 +CYREG_TMR2_PER0 EQU 0x40004f1c + ENDIF + IF :LNOT::DEF:CYREG_TMR2_PER1 +CYREG_TMR2_PER1 EQU 0x40004f1d + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CNT_CMP0 +CYREG_TMR2_CNT_CMP0 EQU 0x40004f1e + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CNT_CMP1 +CYREG_TMR2_CNT_CMP1 EQU 0x40004f1f + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CAP0 +CYREG_TMR2_CAP0 EQU 0x40004f20 + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CAP1 +CYREG_TMR2_CAP1 EQU 0x40004f21 + ENDIF + IF :LNOT::DEF:CYREG_TMR2_RT0 +CYREG_TMR2_RT0 EQU 0x40004f22 + ENDIF + IF :LNOT::DEF:CYREG_TMR2_RT1 +CYREG_TMR2_RT1 EQU 0x40004f23 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_BASE +CYDEV_TMR3_BASE EQU 0x40004f24 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_SIZE +CYDEV_TMR3_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CFG0 +CYREG_TMR3_CFG0 EQU 0x40004f24 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CFG1 +CYREG_TMR3_CFG1 EQU 0x40004f25 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CFG2 +CYREG_TMR3_CFG2 EQU 0x40004f26 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_SR0 +CYREG_TMR3_SR0 EQU 0x40004f27 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_PER0 +CYREG_TMR3_PER0 EQU 0x40004f28 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_PER1 +CYREG_TMR3_PER1 EQU 0x40004f29 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CNT_CMP0 +CYREG_TMR3_CNT_CMP0 EQU 0x40004f2a + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CNT_CMP1 +CYREG_TMR3_CNT_CMP1 EQU 0x40004f2b + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CAP0 +CYREG_TMR3_CAP0 EQU 0x40004f2c + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CAP1 +CYREG_TMR3_CAP1 EQU 0x40004f2d + ENDIF + IF :LNOT::DEF:CYREG_TMR3_RT0 +CYREG_TMR3_RT0 EQU 0x40004f2e + ENDIF + IF :LNOT::DEF:CYREG_TMR3_RT1 +CYREG_TMR3_RT1 EQU 0x40004f2f + ENDIF + IF :LNOT::DEF:CYDEV_IO_BASE +CYDEV_IO_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_SIZE +CYDEV_IO_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_BASE +CYDEV_IO_PC_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_SIZE +CYDEV_IO_PC_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_BASE +CYDEV_IO_PC_PRT0_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_SIZE +CYDEV_IO_PC_PRT0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC0 +CYREG_PRT0_PC0 EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC1 +CYREG_PRT0_PC1 EQU 0x40005001 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC2 +CYREG_PRT0_PC2 EQU 0x40005002 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC3 +CYREG_PRT0_PC3 EQU 0x40005003 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC4 +CYREG_PRT0_PC4 EQU 0x40005004 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC5 +CYREG_PRT0_PC5 EQU 0x40005005 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC6 +CYREG_PRT0_PC6 EQU 0x40005006 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC7 +CYREG_PRT0_PC7 EQU 0x40005007 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_BASE +CYDEV_IO_PC_PRT1_BASE EQU 0x40005008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_SIZE +CYDEV_IO_PC_PRT1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC0 +CYREG_PRT1_PC0 EQU 0x40005008 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC1 +CYREG_PRT1_PC1 EQU 0x40005009 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC2 +CYREG_PRT1_PC2 EQU 0x4000500a + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC3 +CYREG_PRT1_PC3 EQU 0x4000500b + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC4 +CYREG_PRT1_PC4 EQU 0x4000500c + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC5 +CYREG_PRT1_PC5 EQU 0x4000500d + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC6 +CYREG_PRT1_PC6 EQU 0x4000500e + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC7 +CYREG_PRT1_PC7 EQU 0x4000500f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_BASE +CYDEV_IO_PC_PRT2_BASE EQU 0x40005010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_SIZE +CYDEV_IO_PC_PRT2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC0 +CYREG_PRT2_PC0 EQU 0x40005010 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC1 +CYREG_PRT2_PC1 EQU 0x40005011 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC2 +CYREG_PRT2_PC2 EQU 0x40005012 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC3 +CYREG_PRT2_PC3 EQU 0x40005013 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC4 +CYREG_PRT2_PC4 EQU 0x40005014 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC5 +CYREG_PRT2_PC5 EQU 0x40005015 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC6 +CYREG_PRT2_PC6 EQU 0x40005016 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC7 +CYREG_PRT2_PC7 EQU 0x40005017 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_BASE +CYDEV_IO_PC_PRT3_BASE EQU 0x40005018 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_SIZE +CYDEV_IO_PC_PRT3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC0 +CYREG_PRT3_PC0 EQU 0x40005018 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC1 +CYREG_PRT3_PC1 EQU 0x40005019 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC2 +CYREG_PRT3_PC2 EQU 0x4000501a + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC3 +CYREG_PRT3_PC3 EQU 0x4000501b + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC4 +CYREG_PRT3_PC4 EQU 0x4000501c + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC5 +CYREG_PRT3_PC5 EQU 0x4000501d + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC6 +CYREG_PRT3_PC6 EQU 0x4000501e + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC7 +CYREG_PRT3_PC7 EQU 0x4000501f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_BASE +CYDEV_IO_PC_PRT4_BASE EQU 0x40005020 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_SIZE +CYDEV_IO_PC_PRT4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC0 +CYREG_PRT4_PC0 EQU 0x40005020 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC1 +CYREG_PRT4_PC1 EQU 0x40005021 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC2 +CYREG_PRT4_PC2 EQU 0x40005022 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC3 +CYREG_PRT4_PC3 EQU 0x40005023 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC4 +CYREG_PRT4_PC4 EQU 0x40005024 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC5 +CYREG_PRT4_PC5 EQU 0x40005025 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC6 +CYREG_PRT4_PC6 EQU 0x40005026 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC7 +CYREG_PRT4_PC7 EQU 0x40005027 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_BASE +CYDEV_IO_PC_PRT5_BASE EQU 0x40005028 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_SIZE +CYDEV_IO_PC_PRT5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC0 +CYREG_PRT5_PC0 EQU 0x40005028 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC1 +CYREG_PRT5_PC1 EQU 0x40005029 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC2 +CYREG_PRT5_PC2 EQU 0x4000502a + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC3 +CYREG_PRT5_PC3 EQU 0x4000502b + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC4 +CYREG_PRT5_PC4 EQU 0x4000502c + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC5 +CYREG_PRT5_PC5 EQU 0x4000502d + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC6 +CYREG_PRT5_PC6 EQU 0x4000502e + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC7 +CYREG_PRT5_PC7 EQU 0x4000502f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_BASE +CYDEV_IO_PC_PRT6_BASE EQU 0x40005030 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_SIZE +CYDEV_IO_PC_PRT6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC0 +CYREG_PRT6_PC0 EQU 0x40005030 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC1 +CYREG_PRT6_PC1 EQU 0x40005031 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC2 +CYREG_PRT6_PC2 EQU 0x40005032 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC3 +CYREG_PRT6_PC3 EQU 0x40005033 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC4 +CYREG_PRT6_PC4 EQU 0x40005034 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC5 +CYREG_PRT6_PC5 EQU 0x40005035 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC6 +CYREG_PRT6_PC6 EQU 0x40005036 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC7 +CYREG_PRT6_PC7 EQU 0x40005037 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_BASE +CYDEV_IO_PC_PRT12_BASE EQU 0x40005060 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_SIZE +CYDEV_IO_PC_PRT12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC0 +CYREG_PRT12_PC0 EQU 0x40005060 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC1 +CYREG_PRT12_PC1 EQU 0x40005061 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC2 +CYREG_PRT12_PC2 EQU 0x40005062 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC3 +CYREG_PRT12_PC3 EQU 0x40005063 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC4 +CYREG_PRT12_PC4 EQU 0x40005064 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC5 +CYREG_PRT12_PC5 EQU 0x40005065 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC6 +CYREG_PRT12_PC6 EQU 0x40005066 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC7 +CYREG_PRT12_PC7 EQU 0x40005067 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_BASE +CYDEV_IO_PC_PRT15_BASE EQU 0x40005078 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_SIZE +CYDEV_IO_PC_PRT15_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC0 +CYREG_IO_PC_PRT15_PC0 EQU 0x40005078 + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC1 +CYREG_IO_PC_PRT15_PC1 EQU 0x40005079 + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC2 +CYREG_IO_PC_PRT15_PC2 EQU 0x4000507a + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC3 +CYREG_IO_PC_PRT15_PC3 EQU 0x4000507b + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC4 +CYREG_IO_PC_PRT15_PC4 EQU 0x4000507c + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC5 +CYREG_IO_PC_PRT15_PC5 EQU 0x4000507d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_BASE +CYDEV_IO_PC_PRT15_7_6_BASE EQU 0x4000507e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_SIZE +CYDEV_IO_PC_PRT15_7_6_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_7_6_PC0 +CYREG_IO_PC_PRT15_7_6_PC0 EQU 0x4000507e + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_7_6_PC1 +CYREG_IO_PC_PRT15_7_6_PC1 EQU 0x4000507f + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_BASE +CYDEV_IO_DR_BASE EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_SIZE +CYDEV_IO_DR_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT0_BASE +CYDEV_IO_DR_PRT0_BASE EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT0_SIZE +CYDEV_IO_DR_PRT0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DR_ALIAS +CYREG_PRT0_DR_ALIAS EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT1_BASE +CYDEV_IO_DR_PRT1_BASE EQU 0x40005081 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT1_SIZE +CYDEV_IO_DR_PRT1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DR_ALIAS +CYREG_PRT1_DR_ALIAS EQU 0x40005081 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT2_BASE +CYDEV_IO_DR_PRT2_BASE EQU 0x40005082 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT2_SIZE +CYDEV_IO_DR_PRT2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DR_ALIAS +CYREG_PRT2_DR_ALIAS EQU 0x40005082 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT3_BASE +CYDEV_IO_DR_PRT3_BASE EQU 0x40005083 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT3_SIZE +CYDEV_IO_DR_PRT3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DR_ALIAS +CYREG_PRT3_DR_ALIAS EQU 0x40005083 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT4_BASE +CYDEV_IO_DR_PRT4_BASE EQU 0x40005084 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT4_SIZE +CYDEV_IO_DR_PRT4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DR_ALIAS +CYREG_PRT4_DR_ALIAS EQU 0x40005084 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT5_BASE +CYDEV_IO_DR_PRT5_BASE EQU 0x40005085 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT5_SIZE +CYDEV_IO_DR_PRT5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DR_ALIAS +CYREG_PRT5_DR_ALIAS EQU 0x40005085 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT6_BASE +CYDEV_IO_DR_PRT6_BASE EQU 0x40005086 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT6_SIZE +CYDEV_IO_DR_PRT6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DR_ALIAS +CYREG_PRT6_DR_ALIAS EQU 0x40005086 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT12_BASE +CYDEV_IO_DR_PRT12_BASE EQU 0x4000508c + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT12_SIZE +CYDEV_IO_DR_PRT12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DR_ALIAS +CYREG_PRT12_DR_ALIAS EQU 0x4000508c + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT15_BASE +CYDEV_IO_DR_PRT15_BASE EQU 0x4000508f + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT15_SIZE +CYDEV_IO_DR_PRT15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DR_15_ALIAS +CYREG_PRT15_DR_15_ALIAS EQU 0x4000508f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_BASE +CYDEV_IO_PS_BASE EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_SIZE +CYDEV_IO_PS_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT0_BASE +CYDEV_IO_PS_PRT0_BASE EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT0_SIZE +CYDEV_IO_PS_PRT0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PS_ALIAS +CYREG_PRT0_PS_ALIAS EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT1_BASE +CYDEV_IO_PS_PRT1_BASE EQU 0x40005091 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT1_SIZE +CYDEV_IO_PS_PRT1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PS_ALIAS +CYREG_PRT1_PS_ALIAS EQU 0x40005091 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT2_BASE +CYDEV_IO_PS_PRT2_BASE EQU 0x40005092 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT2_SIZE +CYDEV_IO_PS_PRT2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PS_ALIAS +CYREG_PRT2_PS_ALIAS EQU 0x40005092 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT3_BASE +CYDEV_IO_PS_PRT3_BASE EQU 0x40005093 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT3_SIZE +CYDEV_IO_PS_PRT3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PS_ALIAS +CYREG_PRT3_PS_ALIAS EQU 0x40005093 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT4_BASE +CYDEV_IO_PS_PRT4_BASE EQU 0x40005094 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT4_SIZE +CYDEV_IO_PS_PRT4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PS_ALIAS +CYREG_PRT4_PS_ALIAS EQU 0x40005094 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT5_BASE +CYDEV_IO_PS_PRT5_BASE EQU 0x40005095 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT5_SIZE +CYDEV_IO_PS_PRT5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PS_ALIAS +CYREG_PRT5_PS_ALIAS EQU 0x40005095 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT6_BASE +CYDEV_IO_PS_PRT6_BASE EQU 0x40005096 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT6_SIZE +CYDEV_IO_PS_PRT6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PS_ALIAS +CYREG_PRT6_PS_ALIAS EQU 0x40005096 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT12_BASE +CYDEV_IO_PS_PRT12_BASE EQU 0x4000509c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT12_SIZE +CYDEV_IO_PS_PRT12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PS_ALIAS +CYREG_PRT12_PS_ALIAS EQU 0x4000509c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT15_BASE +CYDEV_IO_PS_PRT15_BASE EQU 0x4000509f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT15_SIZE +CYDEV_IO_PS_PRT15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_PS15_ALIAS +CYREG_PRT15_PS15_ALIAS EQU 0x4000509f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_BASE +CYDEV_IO_PRT_BASE EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_SIZE +CYDEV_IO_PRT_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BASE +CYDEV_IO_PRT_PRT0_BASE EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_SIZE +CYDEV_IO_PRT_PRT0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DR +CYREG_PRT0_DR EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PS +CYREG_PRT0_PS EQU 0x40005101 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DM0 +CYREG_PRT0_DM0 EQU 0x40005102 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DM1 +CYREG_PRT0_DM1 EQU 0x40005103 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DM2 +CYREG_PRT0_DM2 EQU 0x40005104 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_SLW +CYREG_PRT0_SLW EQU 0x40005105 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_BYP +CYREG_PRT0_BYP EQU 0x40005106 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_BIE +CYREG_PRT0_BIE EQU 0x40005107 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_INP_DIS +CYREG_PRT0_INP_DIS EQU 0x40005108 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_CTL +CYREG_PRT0_CTL EQU 0x40005109 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PRT +CYREG_PRT0_PRT EQU 0x4000510a + ENDIF + IF :LNOT::DEF:CYREG_PRT0_BIT_MASK +CYREG_PRT0_BIT_MASK EQU 0x4000510b + ENDIF + IF :LNOT::DEF:CYREG_PRT0_AMUX +CYREG_PRT0_AMUX EQU 0x4000510c + ENDIF + IF :LNOT::DEF:CYREG_PRT0_AG +CYREG_PRT0_AG EQU 0x4000510d + ENDIF + IF :LNOT::DEF:CYREG_PRT0_LCD_COM_SEG +CYREG_PRT0_LCD_COM_SEG EQU 0x4000510e + ENDIF + IF :LNOT::DEF:CYREG_PRT0_LCD_EN +CYREG_PRT0_LCD_EN EQU 0x4000510f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BASE +CYDEV_IO_PRT_PRT1_BASE EQU 0x40005110 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_SIZE +CYDEV_IO_PRT_PRT1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DR +CYREG_PRT1_DR EQU 0x40005110 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PS +CYREG_PRT1_PS EQU 0x40005111 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DM0 +CYREG_PRT1_DM0 EQU 0x40005112 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DM1 +CYREG_PRT1_DM1 EQU 0x40005113 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DM2 +CYREG_PRT1_DM2 EQU 0x40005114 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_SLW +CYREG_PRT1_SLW EQU 0x40005115 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_BYP +CYREG_PRT1_BYP EQU 0x40005116 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_BIE +CYREG_PRT1_BIE EQU 0x40005117 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_INP_DIS +CYREG_PRT1_INP_DIS EQU 0x40005118 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_CTL +CYREG_PRT1_CTL EQU 0x40005119 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PRT +CYREG_PRT1_PRT EQU 0x4000511a + ENDIF + IF :LNOT::DEF:CYREG_PRT1_BIT_MASK +CYREG_PRT1_BIT_MASK EQU 0x4000511b + ENDIF + IF :LNOT::DEF:CYREG_PRT1_AMUX +CYREG_PRT1_AMUX EQU 0x4000511c + ENDIF + IF :LNOT::DEF:CYREG_PRT1_AG +CYREG_PRT1_AG EQU 0x4000511d + ENDIF + IF :LNOT::DEF:CYREG_PRT1_LCD_COM_SEG +CYREG_PRT1_LCD_COM_SEG EQU 0x4000511e + ENDIF + IF :LNOT::DEF:CYREG_PRT1_LCD_EN +CYREG_PRT1_LCD_EN EQU 0x4000511f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BASE +CYDEV_IO_PRT_PRT2_BASE EQU 0x40005120 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_SIZE +CYDEV_IO_PRT_PRT2_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DR +CYREG_PRT2_DR EQU 0x40005120 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PS +CYREG_PRT2_PS EQU 0x40005121 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DM0 +CYREG_PRT2_DM0 EQU 0x40005122 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DM1 +CYREG_PRT2_DM1 EQU 0x40005123 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DM2 +CYREG_PRT2_DM2 EQU 0x40005124 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_SLW +CYREG_PRT2_SLW EQU 0x40005125 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_BYP +CYREG_PRT2_BYP EQU 0x40005126 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_BIE +CYREG_PRT2_BIE EQU 0x40005127 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_INP_DIS +CYREG_PRT2_INP_DIS EQU 0x40005128 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_CTL +CYREG_PRT2_CTL EQU 0x40005129 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PRT +CYREG_PRT2_PRT EQU 0x4000512a + ENDIF + IF :LNOT::DEF:CYREG_PRT2_BIT_MASK +CYREG_PRT2_BIT_MASK EQU 0x4000512b + ENDIF + IF :LNOT::DEF:CYREG_PRT2_AMUX +CYREG_PRT2_AMUX EQU 0x4000512c + ENDIF + IF :LNOT::DEF:CYREG_PRT2_AG +CYREG_PRT2_AG EQU 0x4000512d + ENDIF + IF :LNOT::DEF:CYREG_PRT2_LCD_COM_SEG +CYREG_PRT2_LCD_COM_SEG EQU 0x4000512e + ENDIF + IF :LNOT::DEF:CYREG_PRT2_LCD_EN +CYREG_PRT2_LCD_EN EQU 0x4000512f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BASE +CYDEV_IO_PRT_PRT3_BASE EQU 0x40005130 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_SIZE +CYDEV_IO_PRT_PRT3_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DR +CYREG_PRT3_DR EQU 0x40005130 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PS +CYREG_PRT3_PS EQU 0x40005131 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DM0 +CYREG_PRT3_DM0 EQU 0x40005132 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DM1 +CYREG_PRT3_DM1 EQU 0x40005133 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DM2 +CYREG_PRT3_DM2 EQU 0x40005134 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_SLW +CYREG_PRT3_SLW EQU 0x40005135 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_BYP +CYREG_PRT3_BYP EQU 0x40005136 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_BIE +CYREG_PRT3_BIE EQU 0x40005137 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_INP_DIS +CYREG_PRT3_INP_DIS EQU 0x40005138 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_CTL +CYREG_PRT3_CTL EQU 0x40005139 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PRT +CYREG_PRT3_PRT EQU 0x4000513a + ENDIF + IF :LNOT::DEF:CYREG_PRT3_BIT_MASK +CYREG_PRT3_BIT_MASK EQU 0x4000513b + ENDIF + IF :LNOT::DEF:CYREG_PRT3_AMUX +CYREG_PRT3_AMUX EQU 0x4000513c + ENDIF + IF :LNOT::DEF:CYREG_PRT3_AG +CYREG_PRT3_AG EQU 0x4000513d + ENDIF + IF :LNOT::DEF:CYREG_PRT3_LCD_COM_SEG +CYREG_PRT3_LCD_COM_SEG EQU 0x4000513e + ENDIF + IF :LNOT::DEF:CYREG_PRT3_LCD_EN +CYREG_PRT3_LCD_EN EQU 0x4000513f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BASE +CYDEV_IO_PRT_PRT4_BASE EQU 0x40005140 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_SIZE +CYDEV_IO_PRT_PRT4_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DR +CYREG_PRT4_DR EQU 0x40005140 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PS +CYREG_PRT4_PS EQU 0x40005141 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DM0 +CYREG_PRT4_DM0 EQU 0x40005142 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DM1 +CYREG_PRT4_DM1 EQU 0x40005143 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DM2 +CYREG_PRT4_DM2 EQU 0x40005144 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_SLW +CYREG_PRT4_SLW EQU 0x40005145 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_BYP +CYREG_PRT4_BYP EQU 0x40005146 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_BIE +CYREG_PRT4_BIE EQU 0x40005147 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_INP_DIS +CYREG_PRT4_INP_DIS EQU 0x40005148 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_CTL +CYREG_PRT4_CTL EQU 0x40005149 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PRT +CYREG_PRT4_PRT EQU 0x4000514a + ENDIF + IF :LNOT::DEF:CYREG_PRT4_BIT_MASK +CYREG_PRT4_BIT_MASK EQU 0x4000514b + ENDIF + IF :LNOT::DEF:CYREG_PRT4_AMUX +CYREG_PRT4_AMUX EQU 0x4000514c + ENDIF + IF :LNOT::DEF:CYREG_PRT4_AG +CYREG_PRT4_AG EQU 0x4000514d + ENDIF + IF :LNOT::DEF:CYREG_PRT4_LCD_COM_SEG +CYREG_PRT4_LCD_COM_SEG EQU 0x4000514e + ENDIF + IF :LNOT::DEF:CYREG_PRT4_LCD_EN +CYREG_PRT4_LCD_EN EQU 0x4000514f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BASE +CYDEV_IO_PRT_PRT5_BASE EQU 0x40005150 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_SIZE +CYDEV_IO_PRT_PRT5_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DR +CYREG_PRT5_DR EQU 0x40005150 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PS +CYREG_PRT5_PS EQU 0x40005151 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DM0 +CYREG_PRT5_DM0 EQU 0x40005152 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DM1 +CYREG_PRT5_DM1 EQU 0x40005153 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DM2 +CYREG_PRT5_DM2 EQU 0x40005154 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_SLW +CYREG_PRT5_SLW EQU 0x40005155 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_BYP +CYREG_PRT5_BYP EQU 0x40005156 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_BIE +CYREG_PRT5_BIE EQU 0x40005157 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_INP_DIS +CYREG_PRT5_INP_DIS EQU 0x40005158 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_CTL +CYREG_PRT5_CTL EQU 0x40005159 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PRT +CYREG_PRT5_PRT EQU 0x4000515a + ENDIF + IF :LNOT::DEF:CYREG_PRT5_BIT_MASK +CYREG_PRT5_BIT_MASK EQU 0x4000515b + ENDIF + IF :LNOT::DEF:CYREG_PRT5_AMUX +CYREG_PRT5_AMUX EQU 0x4000515c + ENDIF + IF :LNOT::DEF:CYREG_PRT5_AG +CYREG_PRT5_AG EQU 0x4000515d + ENDIF + IF :LNOT::DEF:CYREG_PRT5_LCD_COM_SEG +CYREG_PRT5_LCD_COM_SEG EQU 0x4000515e + ENDIF + IF :LNOT::DEF:CYREG_PRT5_LCD_EN +CYREG_PRT5_LCD_EN EQU 0x4000515f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BASE +CYDEV_IO_PRT_PRT6_BASE EQU 0x40005160 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_SIZE +CYDEV_IO_PRT_PRT6_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DR +CYREG_PRT6_DR EQU 0x40005160 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PS +CYREG_PRT6_PS EQU 0x40005161 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DM0 +CYREG_PRT6_DM0 EQU 0x40005162 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DM1 +CYREG_PRT6_DM1 EQU 0x40005163 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DM2 +CYREG_PRT6_DM2 EQU 0x40005164 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_SLW +CYREG_PRT6_SLW EQU 0x40005165 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_BYP +CYREG_PRT6_BYP EQU 0x40005166 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_BIE +CYREG_PRT6_BIE EQU 0x40005167 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_INP_DIS +CYREG_PRT6_INP_DIS EQU 0x40005168 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_CTL +CYREG_PRT6_CTL EQU 0x40005169 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PRT +CYREG_PRT6_PRT EQU 0x4000516a + ENDIF + IF :LNOT::DEF:CYREG_PRT6_BIT_MASK +CYREG_PRT6_BIT_MASK EQU 0x4000516b + ENDIF + IF :LNOT::DEF:CYREG_PRT6_AMUX +CYREG_PRT6_AMUX EQU 0x4000516c + ENDIF + IF :LNOT::DEF:CYREG_PRT6_AG +CYREG_PRT6_AG EQU 0x4000516d + ENDIF + IF :LNOT::DEF:CYREG_PRT6_LCD_COM_SEG +CYREG_PRT6_LCD_COM_SEG EQU 0x4000516e + ENDIF + IF :LNOT::DEF:CYREG_PRT6_LCD_EN +CYREG_PRT6_LCD_EN EQU 0x4000516f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BASE +CYDEV_IO_PRT_PRT12_BASE EQU 0x400051c0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIZE +CYDEV_IO_PRT_PRT12_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DR +CYREG_PRT12_DR EQU 0x400051c0 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PS +CYREG_PRT12_PS EQU 0x400051c1 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DM0 +CYREG_PRT12_DM0 EQU 0x400051c2 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DM1 +CYREG_PRT12_DM1 EQU 0x400051c3 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DM2 +CYREG_PRT12_DM2 EQU 0x400051c4 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SLW +CYREG_PRT12_SLW EQU 0x400051c5 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_BYP +CYREG_PRT12_BYP EQU 0x400051c6 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_BIE +CYREG_PRT12_BIE EQU 0x400051c7 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_INP_DIS +CYREG_PRT12_INP_DIS EQU 0x400051c8 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SIO_HYST_EN +CYREG_PRT12_SIO_HYST_EN EQU 0x400051c9 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PRT +CYREG_PRT12_PRT EQU 0x400051ca + ENDIF + IF :LNOT::DEF:CYREG_PRT12_BIT_MASK +CYREG_PRT12_BIT_MASK EQU 0x400051cb + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SIO_REG_HIFREQ +CYREG_PRT12_SIO_REG_HIFREQ EQU 0x400051cc + ENDIF + IF :LNOT::DEF:CYREG_PRT12_AG +CYREG_PRT12_AG EQU 0x400051cd + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SIO_CFG +CYREG_PRT12_SIO_CFG EQU 0x400051ce + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SIO_DIFF +CYREG_PRT12_SIO_DIFF EQU 0x400051cf + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BASE +CYDEV_IO_PRT_PRT15_BASE EQU 0x400051f0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_SIZE +CYDEV_IO_PRT_PRT15_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DR +CYREG_PRT15_DR EQU 0x400051f0 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_PS +CYREG_PRT15_PS EQU 0x400051f1 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DM0 +CYREG_PRT15_DM0 EQU 0x400051f2 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DM1 +CYREG_PRT15_DM1 EQU 0x400051f3 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DM2 +CYREG_PRT15_DM2 EQU 0x400051f4 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_SLW +CYREG_PRT15_SLW EQU 0x400051f5 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_BYP +CYREG_PRT15_BYP EQU 0x400051f6 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_BIE +CYREG_PRT15_BIE EQU 0x400051f7 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_INP_DIS +CYREG_PRT15_INP_DIS EQU 0x400051f8 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_CTL +CYREG_PRT15_CTL EQU 0x400051f9 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_PRT +CYREG_PRT15_PRT EQU 0x400051fa + ENDIF + IF :LNOT::DEF:CYREG_PRT15_BIT_MASK +CYREG_PRT15_BIT_MASK EQU 0x400051fb + ENDIF + IF :LNOT::DEF:CYREG_PRT15_AMUX +CYREG_PRT15_AMUX EQU 0x400051fc + ENDIF + IF :LNOT::DEF:CYREG_PRT15_AG +CYREG_PRT15_AG EQU 0x400051fd + ENDIF + IF :LNOT::DEF:CYREG_PRT15_LCD_COM_SEG +CYREG_PRT15_LCD_COM_SEG EQU 0x400051fe + ENDIF + IF :LNOT::DEF:CYREG_PRT15_LCD_EN +CYREG_PRT15_LCD_EN EQU 0x400051ff + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_BASE +CYDEV_PRTDSI_BASE EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_SIZE +CYDEV_PRTDSI_SIZE EQU 0x0000007f + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_BASE +CYDEV_PRTDSI_PRT0_BASE EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_SIZE +CYDEV_PRTDSI_PRT0_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_OUT_SEL0 +CYREG_PRT0_OUT_SEL0 EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_OUT_SEL1 +CYREG_PRT0_OUT_SEL1 EQU 0x40005201 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_OE_SEL0 +CYREG_PRT0_OE_SEL0 EQU 0x40005202 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_OE_SEL1 +CYREG_PRT0_OE_SEL1 EQU 0x40005203 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DBL_SYNC_IN +CYREG_PRT0_DBL_SYNC_IN EQU 0x40005204 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_SYNC_OUT +CYREG_PRT0_SYNC_OUT EQU 0x40005205 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_CAPS_SEL +CYREG_PRT0_CAPS_SEL EQU 0x40005206 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_BASE +CYDEV_PRTDSI_PRT1_BASE EQU 0x40005208 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_SIZE +CYDEV_PRTDSI_PRT1_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_OUT_SEL0 +CYREG_PRT1_OUT_SEL0 EQU 0x40005208 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_OUT_SEL1 +CYREG_PRT1_OUT_SEL1 EQU 0x40005209 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_OE_SEL0 +CYREG_PRT1_OE_SEL0 EQU 0x4000520a + ENDIF + IF :LNOT::DEF:CYREG_PRT1_OE_SEL1 +CYREG_PRT1_OE_SEL1 EQU 0x4000520b + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DBL_SYNC_IN +CYREG_PRT1_DBL_SYNC_IN EQU 0x4000520c + ENDIF + IF :LNOT::DEF:CYREG_PRT1_SYNC_OUT +CYREG_PRT1_SYNC_OUT EQU 0x4000520d + ENDIF + IF :LNOT::DEF:CYREG_PRT1_CAPS_SEL +CYREG_PRT1_CAPS_SEL EQU 0x4000520e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_BASE +CYDEV_PRTDSI_PRT2_BASE EQU 0x40005210 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_SIZE +CYDEV_PRTDSI_PRT2_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_OUT_SEL0 +CYREG_PRT2_OUT_SEL0 EQU 0x40005210 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_OUT_SEL1 +CYREG_PRT2_OUT_SEL1 EQU 0x40005211 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_OE_SEL0 +CYREG_PRT2_OE_SEL0 EQU 0x40005212 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_OE_SEL1 +CYREG_PRT2_OE_SEL1 EQU 0x40005213 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DBL_SYNC_IN +CYREG_PRT2_DBL_SYNC_IN EQU 0x40005214 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_SYNC_OUT +CYREG_PRT2_SYNC_OUT EQU 0x40005215 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_CAPS_SEL +CYREG_PRT2_CAPS_SEL EQU 0x40005216 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_BASE +CYDEV_PRTDSI_PRT3_BASE EQU 0x40005218 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_SIZE +CYDEV_PRTDSI_PRT3_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_OUT_SEL0 +CYREG_PRT3_OUT_SEL0 EQU 0x40005218 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_OUT_SEL1 +CYREG_PRT3_OUT_SEL1 EQU 0x40005219 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_OE_SEL0 +CYREG_PRT3_OE_SEL0 EQU 0x4000521a + ENDIF + IF :LNOT::DEF:CYREG_PRT3_OE_SEL1 +CYREG_PRT3_OE_SEL1 EQU 0x4000521b + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DBL_SYNC_IN +CYREG_PRT3_DBL_SYNC_IN EQU 0x4000521c + ENDIF + IF :LNOT::DEF:CYREG_PRT3_SYNC_OUT +CYREG_PRT3_SYNC_OUT EQU 0x4000521d + ENDIF + IF :LNOT::DEF:CYREG_PRT3_CAPS_SEL +CYREG_PRT3_CAPS_SEL EQU 0x4000521e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_BASE +CYDEV_PRTDSI_PRT4_BASE EQU 0x40005220 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_SIZE +CYDEV_PRTDSI_PRT4_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_OUT_SEL0 +CYREG_PRT4_OUT_SEL0 EQU 0x40005220 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_OUT_SEL1 +CYREG_PRT4_OUT_SEL1 EQU 0x40005221 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_OE_SEL0 +CYREG_PRT4_OE_SEL0 EQU 0x40005222 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_OE_SEL1 +CYREG_PRT4_OE_SEL1 EQU 0x40005223 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DBL_SYNC_IN +CYREG_PRT4_DBL_SYNC_IN EQU 0x40005224 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_SYNC_OUT +CYREG_PRT4_SYNC_OUT EQU 0x40005225 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_CAPS_SEL +CYREG_PRT4_CAPS_SEL EQU 0x40005226 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_BASE +CYDEV_PRTDSI_PRT5_BASE EQU 0x40005228 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_SIZE +CYDEV_PRTDSI_PRT5_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_OUT_SEL0 +CYREG_PRT5_OUT_SEL0 EQU 0x40005228 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_OUT_SEL1 +CYREG_PRT5_OUT_SEL1 EQU 0x40005229 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_OE_SEL0 +CYREG_PRT5_OE_SEL0 EQU 0x4000522a + ENDIF + IF :LNOT::DEF:CYREG_PRT5_OE_SEL1 +CYREG_PRT5_OE_SEL1 EQU 0x4000522b + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DBL_SYNC_IN +CYREG_PRT5_DBL_SYNC_IN EQU 0x4000522c + ENDIF + IF :LNOT::DEF:CYREG_PRT5_SYNC_OUT +CYREG_PRT5_SYNC_OUT EQU 0x4000522d + ENDIF + IF :LNOT::DEF:CYREG_PRT5_CAPS_SEL +CYREG_PRT5_CAPS_SEL EQU 0x4000522e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_BASE +CYDEV_PRTDSI_PRT6_BASE EQU 0x40005230 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_SIZE +CYDEV_PRTDSI_PRT6_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_OUT_SEL0 +CYREG_PRT6_OUT_SEL0 EQU 0x40005230 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_OUT_SEL1 +CYREG_PRT6_OUT_SEL1 EQU 0x40005231 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_OE_SEL0 +CYREG_PRT6_OE_SEL0 EQU 0x40005232 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_OE_SEL1 +CYREG_PRT6_OE_SEL1 EQU 0x40005233 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DBL_SYNC_IN +CYREG_PRT6_DBL_SYNC_IN EQU 0x40005234 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_SYNC_OUT +CYREG_PRT6_SYNC_OUT EQU 0x40005235 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_CAPS_SEL +CYREG_PRT6_CAPS_SEL EQU 0x40005236 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_BASE +CYDEV_PRTDSI_PRT12_BASE EQU 0x40005260 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_SIZE +CYDEV_PRTDSI_PRT12_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_OUT_SEL0 +CYREG_PRT12_OUT_SEL0 EQU 0x40005260 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_OUT_SEL1 +CYREG_PRT12_OUT_SEL1 EQU 0x40005261 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_OE_SEL0 +CYREG_PRT12_OE_SEL0 EQU 0x40005262 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_OE_SEL1 +CYREG_PRT12_OE_SEL1 EQU 0x40005263 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DBL_SYNC_IN +CYREG_PRT12_DBL_SYNC_IN EQU 0x40005264 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SYNC_OUT +CYREG_PRT12_SYNC_OUT EQU 0x40005265 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_BASE +CYDEV_PRTDSI_PRT15_BASE EQU 0x40005278 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_SIZE +CYDEV_PRTDSI_PRT15_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_OUT_SEL0 +CYREG_PRT15_OUT_SEL0 EQU 0x40005278 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_OUT_SEL1 +CYREG_PRT15_OUT_SEL1 EQU 0x40005279 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_OE_SEL0 +CYREG_PRT15_OE_SEL0 EQU 0x4000527a + ENDIF + IF :LNOT::DEF:CYREG_PRT15_OE_SEL1 +CYREG_PRT15_OE_SEL1 EQU 0x4000527b + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DBL_SYNC_IN +CYREG_PRT15_DBL_SYNC_IN EQU 0x4000527c + ENDIF + IF :LNOT::DEF:CYREG_PRT15_SYNC_OUT +CYREG_PRT15_SYNC_OUT EQU 0x4000527d + ENDIF + IF :LNOT::DEF:CYREG_PRT15_CAPS_SEL +CYREG_PRT15_CAPS_SEL EQU 0x4000527e + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_BASE +CYDEV_EMIF_BASE EQU 0x40005400 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_SIZE +CYDEV_EMIF_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_NO_UDB +CYREG_EMIF_NO_UDB EQU 0x40005400 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_RP_WAIT_STATES +CYREG_EMIF_RP_WAIT_STATES EQU 0x40005401 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_MEM_DWN +CYREG_EMIF_MEM_DWN EQU 0x40005402 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_MEMCLK_DIV +CYREG_EMIF_MEMCLK_DIV EQU 0x40005403 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_CLOCK_EN +CYREG_EMIF_CLOCK_EN EQU 0x40005404 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_EM_TYPE +CYREG_EMIF_EM_TYPE EQU 0x40005405 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_WP_WAIT_STATES +CYREG_EMIF_WP_WAIT_STATES EQU 0x40005406 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_BASE +CYDEV_ANAIF_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_SIZE +CYDEV_ANAIF_SIZE EQU 0x000003a9 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BASE +CYDEV_ANAIF_CFG_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SIZE +CYDEV_ANAIF_CFG_SIZE EQU 0x0000010f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_BASE +CYDEV_ANAIF_CFG_SC0_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_SIZE +CYDEV_ANAIF_CFG_SC0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SC0_CR0 +CYREG_SC0_CR0 EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYREG_SC0_CR1 +CYREG_SC0_CR1 EQU 0x40005801 + ENDIF + IF :LNOT::DEF:CYREG_SC0_CR2 +CYREG_SC0_CR2 EQU 0x40005802 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_BASE +CYDEV_ANAIF_CFG_SC1_BASE EQU 0x40005804 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_SIZE +CYDEV_ANAIF_CFG_SC1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SC1_CR0 +CYREG_SC1_CR0 EQU 0x40005804 + ENDIF + IF :LNOT::DEF:CYREG_SC1_CR1 +CYREG_SC1_CR1 EQU 0x40005805 + ENDIF + IF :LNOT::DEF:CYREG_SC1_CR2 +CYREG_SC1_CR2 EQU 0x40005806 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_BASE +CYDEV_ANAIF_CFG_SC2_BASE EQU 0x40005808 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_SIZE +CYDEV_ANAIF_CFG_SC2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SC2_CR0 +CYREG_SC2_CR0 EQU 0x40005808 + ENDIF + IF :LNOT::DEF:CYREG_SC2_CR1 +CYREG_SC2_CR1 EQU 0x40005809 + ENDIF + IF :LNOT::DEF:CYREG_SC2_CR2 +CYREG_SC2_CR2 EQU 0x4000580a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_BASE +CYDEV_ANAIF_CFG_SC3_BASE EQU 0x4000580c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_SIZE +CYDEV_ANAIF_CFG_SC3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SC3_CR0 +CYREG_SC3_CR0 EQU 0x4000580c + ENDIF + IF :LNOT::DEF:CYREG_SC3_CR1 +CYREG_SC3_CR1 EQU 0x4000580d + ENDIF + IF :LNOT::DEF:CYREG_SC3_CR2 +CYREG_SC3_CR2 EQU 0x4000580e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_BASE +CYDEV_ANAIF_CFG_DAC0_BASE EQU 0x40005820 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_SIZE +CYDEV_ANAIF_CFG_DAC0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_CR0 +CYREG_DAC0_CR0 EQU 0x40005820 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_CR1 +CYREG_DAC0_CR1 EQU 0x40005821 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_TST +CYREG_DAC0_TST EQU 0x40005822 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_BASE +CYDEV_ANAIF_CFG_DAC1_BASE EQU 0x40005824 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_SIZE +CYDEV_ANAIF_CFG_DAC1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_CR0 +CYREG_DAC1_CR0 EQU 0x40005824 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_CR1 +CYREG_DAC1_CR1 EQU 0x40005825 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_TST +CYREG_DAC1_TST EQU 0x40005826 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_BASE +CYDEV_ANAIF_CFG_DAC2_BASE EQU 0x40005828 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_SIZE +CYDEV_ANAIF_CFG_DAC2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_CR0 +CYREG_DAC2_CR0 EQU 0x40005828 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_CR1 +CYREG_DAC2_CR1 EQU 0x40005829 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_TST +CYREG_DAC2_TST EQU 0x4000582a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_BASE +CYDEV_ANAIF_CFG_DAC3_BASE EQU 0x4000582c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_SIZE +CYDEV_ANAIF_CFG_DAC3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_DAC3_CR0 +CYREG_DAC3_CR0 EQU 0x4000582c + ENDIF + IF :LNOT::DEF:CYREG_DAC3_CR1 +CYREG_DAC3_CR1 EQU 0x4000582d + ENDIF + IF :LNOT::DEF:CYREG_DAC3_TST +CYREG_DAC3_TST EQU 0x4000582e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_BASE +CYDEV_ANAIF_CFG_CMP0_BASE EQU 0x40005840 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_SIZE +CYDEV_ANAIF_CFG_CMP0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_CR +CYREG_CMP0_CR EQU 0x40005840 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_BASE +CYDEV_ANAIF_CFG_CMP1_BASE EQU 0x40005841 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_SIZE +CYDEV_ANAIF_CFG_CMP1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CMP1_CR +CYREG_CMP1_CR EQU 0x40005841 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_BASE +CYDEV_ANAIF_CFG_CMP2_BASE EQU 0x40005842 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_SIZE +CYDEV_ANAIF_CFG_CMP2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_CR +CYREG_CMP2_CR EQU 0x40005842 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_BASE +CYDEV_ANAIF_CFG_CMP3_BASE EQU 0x40005843 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_SIZE +CYDEV_ANAIF_CFG_CMP3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CMP3_CR +CYREG_CMP3_CR EQU 0x40005843 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_BASE +CYDEV_ANAIF_CFG_LUT0_BASE EQU 0x40005848 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_SIZE +CYDEV_ANAIF_CFG_LUT0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LUT0_CR +CYREG_LUT0_CR EQU 0x40005848 + ENDIF + IF :LNOT::DEF:CYREG_LUT0_MX +CYREG_LUT0_MX EQU 0x40005849 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_BASE +CYDEV_ANAIF_CFG_LUT1_BASE EQU 0x4000584a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_SIZE +CYDEV_ANAIF_CFG_LUT1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LUT1_CR +CYREG_LUT1_CR EQU 0x4000584a + ENDIF + IF :LNOT::DEF:CYREG_LUT1_MX +CYREG_LUT1_MX EQU 0x4000584b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_BASE +CYDEV_ANAIF_CFG_LUT2_BASE EQU 0x4000584c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_SIZE +CYDEV_ANAIF_CFG_LUT2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LUT2_CR +CYREG_LUT2_CR EQU 0x4000584c + ENDIF + IF :LNOT::DEF:CYREG_LUT2_MX +CYREG_LUT2_MX EQU 0x4000584d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_BASE +CYDEV_ANAIF_CFG_LUT3_BASE EQU 0x4000584e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_SIZE +CYDEV_ANAIF_CFG_LUT3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LUT3_CR +CYREG_LUT3_CR EQU 0x4000584e + ENDIF + IF :LNOT::DEF:CYREG_LUT3_MX +CYREG_LUT3_MX EQU 0x4000584f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_BASE +CYDEV_ANAIF_CFG_OPAMP0_BASE EQU 0x40005858 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_SIZE +CYDEV_ANAIF_CFG_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_CR +CYREG_OPAMP0_CR EQU 0x40005858 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_RSVD +CYREG_OPAMP0_RSVD EQU 0x40005859 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_BASE +CYDEV_ANAIF_CFG_OPAMP1_BASE EQU 0x4000585a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_SIZE +CYDEV_ANAIF_CFG_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_CR +CYREG_OPAMP1_CR EQU 0x4000585a + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_RSVD +CYREG_OPAMP1_RSVD EQU 0x4000585b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_BASE +CYDEV_ANAIF_CFG_OPAMP2_BASE EQU 0x4000585c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_SIZE +CYDEV_ANAIF_CFG_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_CR +CYREG_OPAMP2_CR EQU 0x4000585c + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_RSVD +CYREG_OPAMP2_RSVD EQU 0x4000585d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_BASE +CYDEV_ANAIF_CFG_OPAMP3_BASE EQU 0x4000585e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_SIZE +CYDEV_ANAIF_CFG_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_CR +CYREG_OPAMP3_CR EQU 0x4000585e + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_RSVD +CYREG_OPAMP3_RSVD EQU 0x4000585f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_BASE +CYDEV_ANAIF_CFG_LCDDAC_BASE EQU 0x40005868 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_SIZE +CYDEV_ANAIF_CFG_LCDDAC_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_CR0 +CYREG_LCDDAC_CR0 EQU 0x40005868 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_CR1 +CYREG_LCDDAC_CR1 EQU 0x40005869 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_BASE +CYDEV_ANAIF_CFG_LCDDRV_BASE EQU 0x4000586a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_SIZE +CYDEV_ANAIF_CFG_LCDDRV_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_LCDDRV_CR +CYREG_LCDDRV_CR EQU 0x4000586a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_BASE +CYDEV_ANAIF_CFG_LCDTMR_BASE EQU 0x4000586b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_SIZE +CYDEV_ANAIF_CFG_LCDTMR_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_LCDTMR_CFG +CYREG_LCDTMR_CFG EQU 0x4000586b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_BASE +CYDEV_ANAIF_CFG_BG_BASE EQU 0x4000586c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_SIZE +CYDEV_ANAIF_CFG_BG_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_BG_CR0 +CYREG_BG_CR0 EQU 0x4000586c + ENDIF + IF :LNOT::DEF:CYREG_BG_RSVD +CYREG_BG_RSVD EQU 0x4000586d + ENDIF + IF :LNOT::DEF:CYREG_BG_DFT0 +CYREG_BG_DFT0 EQU 0x4000586e + ENDIF + IF :LNOT::DEF:CYREG_BG_DFT1 +CYREG_BG_DFT1 EQU 0x4000586f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_BASE +CYDEV_ANAIF_CFG_CAPSL_BASE EQU 0x40005870 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_SIZE +CYDEV_ANAIF_CFG_CAPSL_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CAPSL_CFG0 +CYREG_CAPSL_CFG0 EQU 0x40005870 + ENDIF + IF :LNOT::DEF:CYREG_CAPSL_CFG1 +CYREG_CAPSL_CFG1 EQU 0x40005871 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_BASE +CYDEV_ANAIF_CFG_CAPSR_BASE EQU 0x40005872 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_SIZE +CYDEV_ANAIF_CFG_CAPSR_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CAPSR_CFG0 +CYREG_CAPSR_CFG0 EQU 0x40005872 + ENDIF + IF :LNOT::DEF:CYREG_CAPSR_CFG1 +CYREG_CAPSR_CFG1 EQU 0x40005873 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_BASE +CYDEV_ANAIF_CFG_PUMP_BASE EQU 0x40005876 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_SIZE +CYDEV_ANAIF_CFG_PUMP_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_PUMP_CR0 +CYREG_PUMP_CR0 EQU 0x40005876 + ENDIF + IF :LNOT::DEF:CYREG_PUMP_CR1 +CYREG_PUMP_CR1 EQU 0x40005877 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_BASE +CYDEV_ANAIF_CFG_LPF0_BASE EQU 0x40005878 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_SIZE +CYDEV_ANAIF_CFG_LPF0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LPF0_CR0 +CYREG_LPF0_CR0 EQU 0x40005878 + ENDIF + IF :LNOT::DEF:CYREG_LPF0_RSVD +CYREG_LPF0_RSVD EQU 0x40005879 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_BASE +CYDEV_ANAIF_CFG_LPF1_BASE EQU 0x4000587a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_SIZE +CYDEV_ANAIF_CFG_LPF1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LPF1_CR0 +CYREG_LPF1_CR0 EQU 0x4000587a + ENDIF + IF :LNOT::DEF:CYREG_LPF1_RSVD +CYREG_LPF1_RSVD EQU 0x4000587b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_BASE +CYDEV_ANAIF_CFG_MISC_BASE EQU 0x4000587c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_SIZE +CYDEV_ANAIF_CFG_MISC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_ANAIF_CFG_MISC_CR0 +CYREG_ANAIF_CFG_MISC_CR0 EQU 0x4000587c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BASE +CYDEV_ANAIF_CFG_DSM0_BASE EQU 0x40005880 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_SIZE +CYDEV_ANAIF_CFG_DSM0_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR0 +CYREG_DSM0_CR0 EQU 0x40005880 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR1 +CYREG_DSM0_CR1 EQU 0x40005881 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR2 +CYREG_DSM0_CR2 EQU 0x40005882 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR3 +CYREG_DSM0_CR3 EQU 0x40005883 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR4 +CYREG_DSM0_CR4 EQU 0x40005884 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR5 +CYREG_DSM0_CR5 EQU 0x40005885 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR6 +CYREG_DSM0_CR6 EQU 0x40005886 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR7 +CYREG_DSM0_CR7 EQU 0x40005887 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR8 +CYREG_DSM0_CR8 EQU 0x40005888 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR9 +CYREG_DSM0_CR9 EQU 0x40005889 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR10 +CYREG_DSM0_CR10 EQU 0x4000588a + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR11 +CYREG_DSM0_CR11 EQU 0x4000588b + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR12 +CYREG_DSM0_CR12 EQU 0x4000588c + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR13 +CYREG_DSM0_CR13 EQU 0x4000588d + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR14 +CYREG_DSM0_CR14 EQU 0x4000588e + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR15 +CYREG_DSM0_CR15 EQU 0x4000588f + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR16 +CYREG_DSM0_CR16 EQU 0x40005890 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR17 +CYREG_DSM0_CR17 EQU 0x40005891 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_REF0 +CYREG_DSM0_REF0 EQU 0x40005892 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_REF1 +CYREG_DSM0_REF1 EQU 0x40005893 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_REF2 +CYREG_DSM0_REF2 EQU 0x40005894 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_REF3 +CYREG_DSM0_REF3 EQU 0x40005895 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_DEM0 +CYREG_DSM0_DEM0 EQU 0x40005896 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_DEM1 +CYREG_DSM0_DEM1 EQU 0x40005897 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_TST0 +CYREG_DSM0_TST0 EQU 0x40005898 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_TST1 +CYREG_DSM0_TST1 EQU 0x40005899 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_BUF0 +CYREG_DSM0_BUF0 EQU 0x4000589a + ENDIF + IF :LNOT::DEF:CYREG_DSM0_BUF1 +CYREG_DSM0_BUF1 EQU 0x4000589b + ENDIF + IF :LNOT::DEF:CYREG_DSM0_BUF2 +CYREG_DSM0_BUF2 EQU 0x4000589c + ENDIF + IF :LNOT::DEF:CYREG_DSM0_BUF3 +CYREG_DSM0_BUF3 EQU 0x4000589d + ENDIF + IF :LNOT::DEF:CYREG_DSM0_MISC +CYREG_DSM0_MISC EQU 0x4000589e + ENDIF + IF :LNOT::DEF:CYREG_DSM0_RSVD1 +CYREG_DSM0_RSVD1 EQU 0x4000589f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_BASE +CYDEV_ANAIF_CFG_SAR0_BASE EQU 0x40005900 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_SIZE +CYDEV_ANAIF_CFG_SAR0_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR0 +CYREG_SAR0_CSR0 EQU 0x40005900 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR1 +CYREG_SAR0_CSR1 EQU 0x40005901 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR2 +CYREG_SAR0_CSR2 EQU 0x40005902 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR3 +CYREG_SAR0_CSR3 EQU 0x40005903 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR4 +CYREG_SAR0_CSR4 EQU 0x40005904 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR5 +CYREG_SAR0_CSR5 EQU 0x40005905 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR6 +CYREG_SAR0_CSR6 EQU 0x40005906 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_BASE +CYDEV_ANAIF_CFG_SAR1_BASE EQU 0x40005908 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_SIZE +CYDEV_ANAIF_CFG_SAR1_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR0 +CYREG_SAR1_CSR0 EQU 0x40005908 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR1 +CYREG_SAR1_CSR1 EQU 0x40005909 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR2 +CYREG_SAR1_CSR2 EQU 0x4000590a + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR3 +CYREG_SAR1_CSR3 EQU 0x4000590b + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR4 +CYREG_SAR1_CSR4 EQU 0x4000590c + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR5 +CYREG_SAR1_CSR5 EQU 0x4000590d + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR6 +CYREG_SAR1_CSR6 EQU 0x4000590e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BASE +CYDEV_ANAIF_RT_BASE EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SIZE +CYDEV_ANAIF_RT_SIZE EQU 0x00000162 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_BASE +CYDEV_ANAIF_RT_SC0_BASE EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SIZE +CYDEV_ANAIF_RT_SC0_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW0 +CYREG_SC0_SW0 EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW2 +CYREG_SC0_SW2 EQU 0x40005a02 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW3 +CYREG_SC0_SW3 EQU 0x40005a03 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW4 +CYREG_SC0_SW4 EQU 0x40005a04 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW6 +CYREG_SC0_SW6 EQU 0x40005a06 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW7 +CYREG_SC0_SW7 EQU 0x40005a07 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW8 +CYREG_SC0_SW8 EQU 0x40005a08 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW10 +CYREG_SC0_SW10 EQU 0x40005a0a + ENDIF + IF :LNOT::DEF:CYREG_SC0_CLK +CYREG_SC0_CLK EQU 0x40005a0b + ENDIF + IF :LNOT::DEF:CYREG_SC0_BST +CYREG_SC0_BST EQU 0x40005a0c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_BASE +CYDEV_ANAIF_RT_SC1_BASE EQU 0x40005a10 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SIZE +CYDEV_ANAIF_RT_SC1_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW0 +CYREG_SC1_SW0 EQU 0x40005a10 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW2 +CYREG_SC1_SW2 EQU 0x40005a12 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW3 +CYREG_SC1_SW3 EQU 0x40005a13 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW4 +CYREG_SC1_SW4 EQU 0x40005a14 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW6 +CYREG_SC1_SW6 EQU 0x40005a16 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW7 +CYREG_SC1_SW7 EQU 0x40005a17 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW8 +CYREG_SC1_SW8 EQU 0x40005a18 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW10 +CYREG_SC1_SW10 EQU 0x40005a1a + ENDIF + IF :LNOT::DEF:CYREG_SC1_CLK +CYREG_SC1_CLK EQU 0x40005a1b + ENDIF + IF :LNOT::DEF:CYREG_SC1_BST +CYREG_SC1_BST EQU 0x40005a1c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_BASE +CYDEV_ANAIF_RT_SC2_BASE EQU 0x40005a20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SIZE +CYDEV_ANAIF_RT_SC2_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW0 +CYREG_SC2_SW0 EQU 0x40005a20 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW2 +CYREG_SC2_SW2 EQU 0x40005a22 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW3 +CYREG_SC2_SW3 EQU 0x40005a23 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW4 +CYREG_SC2_SW4 EQU 0x40005a24 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW6 +CYREG_SC2_SW6 EQU 0x40005a26 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW7 +CYREG_SC2_SW7 EQU 0x40005a27 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW8 +CYREG_SC2_SW8 EQU 0x40005a28 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW10 +CYREG_SC2_SW10 EQU 0x40005a2a + ENDIF + IF :LNOT::DEF:CYREG_SC2_CLK +CYREG_SC2_CLK EQU 0x40005a2b + ENDIF + IF :LNOT::DEF:CYREG_SC2_BST +CYREG_SC2_BST EQU 0x40005a2c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_BASE +CYDEV_ANAIF_RT_SC3_BASE EQU 0x40005a30 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SIZE +CYDEV_ANAIF_RT_SC3_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW0 +CYREG_SC3_SW0 EQU 0x40005a30 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW2 +CYREG_SC3_SW2 EQU 0x40005a32 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW3 +CYREG_SC3_SW3 EQU 0x40005a33 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW4 +CYREG_SC3_SW4 EQU 0x40005a34 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW6 +CYREG_SC3_SW6 EQU 0x40005a36 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW7 +CYREG_SC3_SW7 EQU 0x40005a37 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW8 +CYREG_SC3_SW8 EQU 0x40005a38 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW10 +CYREG_SC3_SW10 EQU 0x40005a3a + ENDIF + IF :LNOT::DEF:CYREG_SC3_CLK +CYREG_SC3_CLK EQU 0x40005a3b + ENDIF + IF :LNOT::DEF:CYREG_SC3_BST +CYREG_SC3_BST EQU 0x40005a3c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_BASE +CYDEV_ANAIF_RT_DAC0_BASE EQU 0x40005a80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SIZE +CYDEV_ANAIF_RT_DAC0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_SW0 +CYREG_DAC0_SW0 EQU 0x40005a80 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_SW2 +CYREG_DAC0_SW2 EQU 0x40005a82 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_SW3 +CYREG_DAC0_SW3 EQU 0x40005a83 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_SW4 +CYREG_DAC0_SW4 EQU 0x40005a84 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_STROBE +CYREG_DAC0_STROBE EQU 0x40005a87 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_BASE +CYDEV_ANAIF_RT_DAC1_BASE EQU 0x40005a88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SIZE +CYDEV_ANAIF_RT_DAC1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_SW0 +CYREG_DAC1_SW0 EQU 0x40005a88 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_SW2 +CYREG_DAC1_SW2 EQU 0x40005a8a + ENDIF + IF :LNOT::DEF:CYREG_DAC1_SW3 +CYREG_DAC1_SW3 EQU 0x40005a8b + ENDIF + IF :LNOT::DEF:CYREG_DAC1_SW4 +CYREG_DAC1_SW4 EQU 0x40005a8c + ENDIF + IF :LNOT::DEF:CYREG_DAC1_STROBE +CYREG_DAC1_STROBE EQU 0x40005a8f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_BASE +CYDEV_ANAIF_RT_DAC2_BASE EQU 0x40005a90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SIZE +CYDEV_ANAIF_RT_DAC2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_SW0 +CYREG_DAC2_SW0 EQU 0x40005a90 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_SW2 +CYREG_DAC2_SW2 EQU 0x40005a92 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_SW3 +CYREG_DAC2_SW3 EQU 0x40005a93 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_SW4 +CYREG_DAC2_SW4 EQU 0x40005a94 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_STROBE +CYREG_DAC2_STROBE EQU 0x40005a97 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_BASE +CYDEV_ANAIF_RT_DAC3_BASE EQU 0x40005a98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SIZE +CYDEV_ANAIF_RT_DAC3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_DAC3_SW0 +CYREG_DAC3_SW0 EQU 0x40005a98 + ENDIF + IF :LNOT::DEF:CYREG_DAC3_SW2 +CYREG_DAC3_SW2 EQU 0x40005a9a + ENDIF + IF :LNOT::DEF:CYREG_DAC3_SW3 +CYREG_DAC3_SW3 EQU 0x40005a9b + ENDIF + IF :LNOT::DEF:CYREG_DAC3_SW4 +CYREG_DAC3_SW4 EQU 0x40005a9c + ENDIF + IF :LNOT::DEF:CYREG_DAC3_STROBE +CYREG_DAC3_STROBE EQU 0x40005a9f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_BASE +CYDEV_ANAIF_RT_CMP0_BASE EQU 0x40005ac0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SIZE +CYDEV_ANAIF_RT_CMP0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_SW0 +CYREG_CMP0_SW0 EQU 0x40005ac0 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_SW2 +CYREG_CMP0_SW2 EQU 0x40005ac2 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_SW3 +CYREG_CMP0_SW3 EQU 0x40005ac3 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_SW4 +CYREG_CMP0_SW4 EQU 0x40005ac4 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_SW6 +CYREG_CMP0_SW6 EQU 0x40005ac6 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_CLK +CYREG_CMP0_CLK EQU 0x40005ac7 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_BASE +CYDEV_ANAIF_RT_CMP1_BASE EQU 0x40005ac8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SIZE +CYDEV_ANAIF_RT_CMP1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CMP1_SW0 +CYREG_CMP1_SW0 EQU 0x40005ac8 + ENDIF + IF :LNOT::DEF:CYREG_CMP1_SW2 +CYREG_CMP1_SW2 EQU 0x40005aca + ENDIF + IF :LNOT::DEF:CYREG_CMP1_SW3 +CYREG_CMP1_SW3 EQU 0x40005acb + ENDIF + IF :LNOT::DEF:CYREG_CMP1_SW4 +CYREG_CMP1_SW4 EQU 0x40005acc + ENDIF + IF :LNOT::DEF:CYREG_CMP1_SW6 +CYREG_CMP1_SW6 EQU 0x40005ace + ENDIF + IF :LNOT::DEF:CYREG_CMP1_CLK +CYREG_CMP1_CLK EQU 0x40005acf + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_BASE +CYDEV_ANAIF_RT_CMP2_BASE EQU 0x40005ad0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SIZE +CYDEV_ANAIF_RT_CMP2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_SW0 +CYREG_CMP2_SW0 EQU 0x40005ad0 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_SW2 +CYREG_CMP2_SW2 EQU 0x40005ad2 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_SW3 +CYREG_CMP2_SW3 EQU 0x40005ad3 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_SW4 +CYREG_CMP2_SW4 EQU 0x40005ad4 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_SW6 +CYREG_CMP2_SW6 EQU 0x40005ad6 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_CLK +CYREG_CMP2_CLK EQU 0x40005ad7 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_BASE +CYDEV_ANAIF_RT_CMP3_BASE EQU 0x40005ad8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SIZE +CYDEV_ANAIF_RT_CMP3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CMP3_SW0 +CYREG_CMP3_SW0 EQU 0x40005ad8 + ENDIF + IF :LNOT::DEF:CYREG_CMP3_SW2 +CYREG_CMP3_SW2 EQU 0x40005ada + ENDIF + IF :LNOT::DEF:CYREG_CMP3_SW3 +CYREG_CMP3_SW3 EQU 0x40005adb + ENDIF + IF :LNOT::DEF:CYREG_CMP3_SW4 +CYREG_CMP3_SW4 EQU 0x40005adc + ENDIF + IF :LNOT::DEF:CYREG_CMP3_SW6 +CYREG_CMP3_SW6 EQU 0x40005ade + ENDIF + IF :LNOT::DEF:CYREG_CMP3_CLK +CYREG_CMP3_CLK EQU 0x40005adf + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_BASE +CYDEV_ANAIF_RT_DSM0_BASE EQU 0x40005b00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SIZE +CYDEV_ANAIF_RT_DSM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_SW0 +CYREG_DSM0_SW0 EQU 0x40005b00 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_SW2 +CYREG_DSM0_SW2 EQU 0x40005b02 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_SW3 +CYREG_DSM0_SW3 EQU 0x40005b03 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_SW4 +CYREG_DSM0_SW4 EQU 0x40005b04 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_SW6 +CYREG_DSM0_SW6 EQU 0x40005b06 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CLK +CYREG_DSM0_CLK EQU 0x40005b07 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_BASE +CYDEV_ANAIF_RT_SAR0_BASE EQU 0x40005b20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SIZE +CYDEV_ANAIF_RT_SAR0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_SW0 +CYREG_SAR0_SW0 EQU 0x40005b20 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_SW2 +CYREG_SAR0_SW2 EQU 0x40005b22 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_SW3 +CYREG_SAR0_SW3 EQU 0x40005b23 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_SW4 +CYREG_SAR0_SW4 EQU 0x40005b24 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_SW6 +CYREG_SAR0_SW6 EQU 0x40005b26 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CLK +CYREG_SAR0_CLK EQU 0x40005b27 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_BASE +CYDEV_ANAIF_RT_SAR1_BASE EQU 0x40005b28 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SIZE +CYDEV_ANAIF_RT_SAR1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_SW0 +CYREG_SAR1_SW0 EQU 0x40005b28 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_SW2 +CYREG_SAR1_SW2 EQU 0x40005b2a + ENDIF + IF :LNOT::DEF:CYREG_SAR1_SW3 +CYREG_SAR1_SW3 EQU 0x40005b2b + ENDIF + IF :LNOT::DEF:CYREG_SAR1_SW4 +CYREG_SAR1_SW4 EQU 0x40005b2c + ENDIF + IF :LNOT::DEF:CYREG_SAR1_SW6 +CYREG_SAR1_SW6 EQU 0x40005b2e + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CLK +CYREG_SAR1_CLK EQU 0x40005b2f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_BASE +CYDEV_ANAIF_RT_OPAMP0_BASE EQU 0x40005b40 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_SIZE +CYDEV_ANAIF_RT_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_MX +CYREG_OPAMP0_MX EQU 0x40005b40 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_SW +CYREG_OPAMP0_SW EQU 0x40005b41 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_BASE +CYDEV_ANAIF_RT_OPAMP1_BASE EQU 0x40005b42 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_SIZE +CYDEV_ANAIF_RT_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_MX +CYREG_OPAMP1_MX EQU 0x40005b42 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_SW +CYREG_OPAMP1_SW EQU 0x40005b43 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_BASE +CYDEV_ANAIF_RT_OPAMP2_BASE EQU 0x40005b44 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_SIZE +CYDEV_ANAIF_RT_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_MX +CYREG_OPAMP2_MX EQU 0x40005b44 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_SW +CYREG_OPAMP2_SW EQU 0x40005b45 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_BASE +CYDEV_ANAIF_RT_OPAMP3_BASE EQU 0x40005b46 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_SIZE +CYDEV_ANAIF_RT_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_MX +CYREG_OPAMP3_MX EQU 0x40005b46 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_SW +CYREG_OPAMP3_SW EQU 0x40005b47 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_BASE +CYDEV_ANAIF_RT_LCDDAC_BASE EQU 0x40005b50 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SIZE +CYDEV_ANAIF_RT_LCDDAC_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_SW0 +CYREG_LCDDAC_SW0 EQU 0x40005b50 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_SW1 +CYREG_LCDDAC_SW1 EQU 0x40005b51 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_SW2 +CYREG_LCDDAC_SW2 EQU 0x40005b52 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_SW3 +CYREG_LCDDAC_SW3 EQU 0x40005b53 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_SW4 +CYREG_LCDDAC_SW4 EQU 0x40005b54 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_BASE +CYDEV_ANAIF_RT_SC_BASE EQU 0x40005b56 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_SIZE +CYDEV_ANAIF_RT_SC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SC_MISC +CYREG_SC_MISC EQU 0x40005b56 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_BASE +CYDEV_ANAIF_RT_BUS_BASE EQU 0x40005b58 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SIZE +CYDEV_ANAIF_RT_BUS_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_BUS_SW0 +CYREG_BUS_SW0 EQU 0x40005b58 + ENDIF + IF :LNOT::DEF:CYREG_BUS_SW2 +CYREG_BUS_SW2 EQU 0x40005b5a + ENDIF + IF :LNOT::DEF:CYREG_BUS_SW3 +CYREG_BUS_SW3 EQU 0x40005b5b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_BASE +CYDEV_ANAIF_RT_DFT_BASE EQU 0x40005b5c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_SIZE +CYDEV_ANAIF_RT_DFT_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR0 +CYREG_DFT_CR0 EQU 0x40005b5c + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR1 +CYREG_DFT_CR1 EQU 0x40005b5d + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR2 +CYREG_DFT_CR2 EQU 0x40005b5e + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR3 +CYREG_DFT_CR3 EQU 0x40005b5f + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR4 +CYREG_DFT_CR4 EQU 0x40005b60 + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR5 +CYREG_DFT_CR5 EQU 0x40005b61 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_BASE +CYDEV_ANAIF_WRK_BASE EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SIZE +CYDEV_ANAIF_WRK_SIZE EQU 0x00000029 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_BASE +CYDEV_ANAIF_WRK_DAC0_BASE EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_SIZE +CYDEV_ANAIF_WRK_DAC0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_D +CYREG_DAC0_D EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_BASE +CYDEV_ANAIF_WRK_DAC1_BASE EQU 0x40005b81 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_SIZE +CYDEV_ANAIF_WRK_DAC1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_D +CYREG_DAC1_D EQU 0x40005b81 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_BASE +CYDEV_ANAIF_WRK_DAC2_BASE EQU 0x40005b82 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_SIZE +CYDEV_ANAIF_WRK_DAC2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_D +CYREG_DAC2_D EQU 0x40005b82 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_BASE +CYDEV_ANAIF_WRK_DAC3_BASE EQU 0x40005b83 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_SIZE +CYDEV_ANAIF_WRK_DAC3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC3_D +CYREG_DAC3_D EQU 0x40005b83 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_BASE +CYDEV_ANAIF_WRK_DSM0_BASE EQU 0x40005b88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_SIZE +CYDEV_ANAIF_WRK_DSM0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_OUT0 +CYREG_DSM0_OUT0 EQU 0x40005b88 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_OUT1 +CYREG_DSM0_OUT1 EQU 0x40005b89 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_BASE +CYDEV_ANAIF_WRK_LUT_BASE EQU 0x40005b90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_SIZE +CYDEV_ANAIF_WRK_LUT_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_LUT_SR +CYREG_LUT_SR EQU 0x40005b90 + ENDIF + IF :LNOT::DEF:CYREG_LUT_WRK1 +CYREG_LUT_WRK1 EQU 0x40005b91 + ENDIF + IF :LNOT::DEF:CYREG_LUT_MSK +CYREG_LUT_MSK EQU 0x40005b92 + ENDIF + IF :LNOT::DEF:CYREG_LUT_CLK +CYREG_LUT_CLK EQU 0x40005b93 + ENDIF + IF :LNOT::DEF:CYREG_LUT_CPTR +CYREG_LUT_CPTR EQU 0x40005b94 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_BASE +CYDEV_ANAIF_WRK_CMP_BASE EQU 0x40005b96 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_SIZE +CYDEV_ANAIF_WRK_CMP_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CMP_WRK +CYREG_CMP_WRK EQU 0x40005b96 + ENDIF + IF :LNOT::DEF:CYREG_CMP_TST +CYREG_CMP_TST EQU 0x40005b97 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_BASE +CYDEV_ANAIF_WRK_SC_BASE EQU 0x40005b98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_SIZE +CYDEV_ANAIF_WRK_SC_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_SC_SR +CYREG_SC_SR EQU 0x40005b98 + ENDIF + IF :LNOT::DEF:CYREG_SC_WRK1 +CYREG_SC_WRK1 EQU 0x40005b99 + ENDIF + IF :LNOT::DEF:CYREG_SC_MSK +CYREG_SC_MSK EQU 0x40005b9a + ENDIF + IF :LNOT::DEF:CYREG_SC_CMPINV +CYREG_SC_CMPINV EQU 0x40005b9b + ENDIF + IF :LNOT::DEF:CYREG_SC_CPTR +CYREG_SC_CPTR EQU 0x40005b9c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_BASE +CYDEV_ANAIF_WRK_SAR0_BASE EQU 0x40005ba0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_SIZE +CYDEV_ANAIF_WRK_SAR0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_WRK0 +CYREG_SAR0_WRK0 EQU 0x40005ba0 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_WRK1 +CYREG_SAR0_WRK1 EQU 0x40005ba1 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_BASE +CYDEV_ANAIF_WRK_SAR1_BASE EQU 0x40005ba2 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_SIZE +CYDEV_ANAIF_WRK_SAR1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_WRK0 +CYREG_SAR1_WRK0 EQU 0x40005ba2 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_WRK1 +CYREG_SAR1_WRK1 EQU 0x40005ba3 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_BASE +CYDEV_ANAIF_WRK_SARS_BASE EQU 0x40005ba8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_SIZE +CYDEV_ANAIF_WRK_SARS_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_ANAIF_WRK_SARS_SOF +CYREG_ANAIF_WRK_SARS_SOF EQU 0x40005ba8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_BASE +CYDEV_USB_BASE EQU 0x40006000 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIZE +CYDEV_USB_SIZE EQU 0x00000300 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR0 +CYREG_USB_EP0_DR0 EQU 0x40006000 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR1 +CYREG_USB_EP0_DR1 EQU 0x40006001 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR2 +CYREG_USB_EP0_DR2 EQU 0x40006002 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR3 +CYREG_USB_EP0_DR3 EQU 0x40006003 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR4 +CYREG_USB_EP0_DR4 EQU 0x40006004 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR5 +CYREG_USB_EP0_DR5 EQU 0x40006005 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR6 +CYREG_USB_EP0_DR6 EQU 0x40006006 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR7 +CYREG_USB_EP0_DR7 EQU 0x40006007 + ENDIF + IF :LNOT::DEF:CYREG_USB_CR0 +CYREG_USB_CR0 EQU 0x40006008 + ENDIF + IF :LNOT::DEF:CYREG_USB_CR1 +CYREG_USB_CR1 EQU 0x40006009 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP_INT_EN +CYREG_USB_SIE_EP_INT_EN EQU 0x4000600a + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP_INT_SR +CYREG_USB_SIE_EP_INT_SR EQU 0x4000600b + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_BASE +CYDEV_USB_SIE_EP1_BASE EQU 0x4000600c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_SIZE +CYDEV_USB_SIE_EP1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP1_CNT0 +CYREG_USB_SIE_EP1_CNT0 EQU 0x4000600c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP1_CNT1 +CYREG_USB_SIE_EP1_CNT1 EQU 0x4000600d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP1_CR0 +CYREG_USB_SIE_EP1_CR0 EQU 0x4000600e + ENDIF + IF :LNOT::DEF:CYREG_USB_USBIO_CR0 +CYREG_USB_USBIO_CR0 EQU 0x40006010 + ENDIF + IF :LNOT::DEF:CYREG_USB_USBIO_CR1 +CYREG_USB_USBIO_CR1 EQU 0x40006012 + ENDIF + IF :LNOT::DEF:CYREG_USB_DYN_RECONFIG +CYREG_USB_DYN_RECONFIG EQU 0x40006014 + ENDIF + IF :LNOT::DEF:CYREG_USB_SOF0 +CYREG_USB_SOF0 EQU 0x40006018 + ENDIF + IF :LNOT::DEF:CYREG_USB_SOF1 +CYREG_USB_SOF1 EQU 0x40006019 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_BASE +CYDEV_USB_SIE_EP2_BASE EQU 0x4000601c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_SIZE +CYDEV_USB_SIE_EP2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP2_CNT0 +CYREG_USB_SIE_EP2_CNT0 EQU 0x4000601c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP2_CNT1 +CYREG_USB_SIE_EP2_CNT1 EQU 0x4000601d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP2_CR0 +CYREG_USB_SIE_EP2_CR0 EQU 0x4000601e + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_CR +CYREG_USB_EP0_CR EQU 0x40006028 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_CNT +CYREG_USB_EP0_CNT EQU 0x40006029 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_BASE +CYDEV_USB_SIE_EP3_BASE EQU 0x4000602c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_SIZE +CYDEV_USB_SIE_EP3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP3_CNT0 +CYREG_USB_SIE_EP3_CNT0 EQU 0x4000602c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP3_CNT1 +CYREG_USB_SIE_EP3_CNT1 EQU 0x4000602d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP3_CR0 +CYREG_USB_SIE_EP3_CR0 EQU 0x4000602e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_BASE +CYDEV_USB_SIE_EP4_BASE EQU 0x4000603c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_SIZE +CYDEV_USB_SIE_EP4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP4_CNT0 +CYREG_USB_SIE_EP4_CNT0 EQU 0x4000603c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP4_CNT1 +CYREG_USB_SIE_EP4_CNT1 EQU 0x4000603d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP4_CR0 +CYREG_USB_SIE_EP4_CR0 EQU 0x4000603e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_BASE +CYDEV_USB_SIE_EP5_BASE EQU 0x4000604c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_SIZE +CYDEV_USB_SIE_EP5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP5_CNT0 +CYREG_USB_SIE_EP5_CNT0 EQU 0x4000604c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP5_CNT1 +CYREG_USB_SIE_EP5_CNT1 EQU 0x4000604d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP5_CR0 +CYREG_USB_SIE_EP5_CR0 EQU 0x4000604e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_BASE +CYDEV_USB_SIE_EP6_BASE EQU 0x4000605c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_SIZE +CYDEV_USB_SIE_EP6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP6_CNT0 +CYREG_USB_SIE_EP6_CNT0 EQU 0x4000605c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP6_CNT1 +CYREG_USB_SIE_EP6_CNT1 EQU 0x4000605d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP6_CR0 +CYREG_USB_SIE_EP6_CR0 EQU 0x4000605e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_BASE +CYDEV_USB_SIE_EP7_BASE EQU 0x4000606c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_SIZE +CYDEV_USB_SIE_EP7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP7_CNT0 +CYREG_USB_SIE_EP7_CNT0 EQU 0x4000606c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP7_CNT1 +CYREG_USB_SIE_EP7_CNT1 EQU 0x4000606d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP7_CR0 +CYREG_USB_SIE_EP7_CR0 EQU 0x4000606e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_BASE +CYDEV_USB_SIE_EP8_BASE EQU 0x4000607c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_SIZE +CYDEV_USB_SIE_EP8_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP8_CNT0 +CYREG_USB_SIE_EP8_CNT0 EQU 0x4000607c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP8_CNT1 +CYREG_USB_SIE_EP8_CNT1 EQU 0x4000607d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP8_CR0 +CYREG_USB_SIE_EP8_CR0 EQU 0x4000607e + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_BASE +CYDEV_USB_ARB_EP1_BASE EQU 0x40006080 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_SIZE +CYDEV_USB_ARB_EP1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP1_CFG +CYREG_USB_ARB_EP1_CFG EQU 0x40006080 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP1_INT_EN +CYREG_USB_ARB_EP1_INT_EN EQU 0x40006081 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP1_SR +CYREG_USB_ARB_EP1_SR EQU 0x40006082 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_BASE +CYDEV_USB_ARB_RW1_BASE EQU 0x40006084 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_SIZE +CYDEV_USB_ARB_RW1_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW1_WA +CYREG_USB_ARB_RW1_WA EQU 0x40006084 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW1_WA_MSB +CYREG_USB_ARB_RW1_WA_MSB EQU 0x40006085 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW1_RA +CYREG_USB_ARB_RW1_RA EQU 0x40006086 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW1_RA_MSB +CYREG_USB_ARB_RW1_RA_MSB EQU 0x40006087 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW1_DR +CYREG_USB_ARB_RW1_DR EQU 0x40006088 + ENDIF + IF :LNOT::DEF:CYREG_USB_BUF_SIZE +CYREG_USB_BUF_SIZE EQU 0x4000608c + ENDIF + IF :LNOT::DEF:CYREG_USB_EP_ACTIVE +CYREG_USB_EP_ACTIVE EQU 0x4000608e + ENDIF + IF :LNOT::DEF:CYREG_USB_EP_TYPE +CYREG_USB_EP_TYPE EQU 0x4000608f + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_BASE +CYDEV_USB_ARB_EP2_BASE EQU 0x40006090 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_SIZE +CYDEV_USB_ARB_EP2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP2_CFG +CYREG_USB_ARB_EP2_CFG EQU 0x40006090 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP2_INT_EN +CYREG_USB_ARB_EP2_INT_EN EQU 0x40006091 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP2_SR +CYREG_USB_ARB_EP2_SR EQU 0x40006092 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_BASE +CYDEV_USB_ARB_RW2_BASE EQU 0x40006094 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_SIZE +CYDEV_USB_ARB_RW2_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW2_WA +CYREG_USB_ARB_RW2_WA EQU 0x40006094 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW2_WA_MSB +CYREG_USB_ARB_RW2_WA_MSB EQU 0x40006095 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW2_RA +CYREG_USB_ARB_RW2_RA EQU 0x40006096 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW2_RA_MSB +CYREG_USB_ARB_RW2_RA_MSB EQU 0x40006097 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW2_DR +CYREG_USB_ARB_RW2_DR EQU 0x40006098 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_CFG +CYREG_USB_ARB_CFG EQU 0x4000609c + ENDIF + IF :LNOT::DEF:CYREG_USB_USB_CLK_EN +CYREG_USB_USB_CLK_EN EQU 0x4000609d + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_INT_EN +CYREG_USB_ARB_INT_EN EQU 0x4000609e + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_INT_SR +CYREG_USB_ARB_INT_SR EQU 0x4000609f + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_BASE +CYDEV_USB_ARB_EP3_BASE EQU 0x400060a0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_SIZE +CYDEV_USB_ARB_EP3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP3_CFG +CYREG_USB_ARB_EP3_CFG EQU 0x400060a0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP3_INT_EN +CYREG_USB_ARB_EP3_INT_EN EQU 0x400060a1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP3_SR +CYREG_USB_ARB_EP3_SR EQU 0x400060a2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_BASE +CYDEV_USB_ARB_RW3_BASE EQU 0x400060a4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_SIZE +CYDEV_USB_ARB_RW3_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW3_WA +CYREG_USB_ARB_RW3_WA EQU 0x400060a4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW3_WA_MSB +CYREG_USB_ARB_RW3_WA_MSB EQU 0x400060a5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW3_RA +CYREG_USB_ARB_RW3_RA EQU 0x400060a6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW3_RA_MSB +CYREG_USB_ARB_RW3_RA_MSB EQU 0x400060a7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW3_DR +CYREG_USB_ARB_RW3_DR EQU 0x400060a8 + ENDIF + IF :LNOT::DEF:CYREG_USB_CWA +CYREG_USB_CWA EQU 0x400060ac + ENDIF + IF :LNOT::DEF:CYREG_USB_CWA_MSB +CYREG_USB_CWA_MSB EQU 0x400060ad + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_BASE +CYDEV_USB_ARB_EP4_BASE EQU 0x400060b0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_SIZE +CYDEV_USB_ARB_EP4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP4_CFG +CYREG_USB_ARB_EP4_CFG EQU 0x400060b0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP4_INT_EN +CYREG_USB_ARB_EP4_INT_EN EQU 0x400060b1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP4_SR +CYREG_USB_ARB_EP4_SR EQU 0x400060b2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_BASE +CYDEV_USB_ARB_RW4_BASE EQU 0x400060b4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_SIZE +CYDEV_USB_ARB_RW4_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW4_WA +CYREG_USB_ARB_RW4_WA EQU 0x400060b4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW4_WA_MSB +CYREG_USB_ARB_RW4_WA_MSB EQU 0x400060b5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW4_RA +CYREG_USB_ARB_RW4_RA EQU 0x400060b6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW4_RA_MSB +CYREG_USB_ARB_RW4_RA_MSB EQU 0x400060b7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW4_DR +CYREG_USB_ARB_RW4_DR EQU 0x400060b8 + ENDIF + IF :LNOT::DEF:CYREG_USB_DMA_THRES +CYREG_USB_DMA_THRES EQU 0x400060bc + ENDIF + IF :LNOT::DEF:CYREG_USB_DMA_THRES_MSB +CYREG_USB_DMA_THRES_MSB EQU 0x400060bd + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_BASE +CYDEV_USB_ARB_EP5_BASE EQU 0x400060c0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_SIZE +CYDEV_USB_ARB_EP5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP5_CFG +CYREG_USB_ARB_EP5_CFG EQU 0x400060c0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP5_INT_EN +CYREG_USB_ARB_EP5_INT_EN EQU 0x400060c1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP5_SR +CYREG_USB_ARB_EP5_SR EQU 0x400060c2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_BASE +CYDEV_USB_ARB_RW5_BASE EQU 0x400060c4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_SIZE +CYDEV_USB_ARB_RW5_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW5_WA +CYREG_USB_ARB_RW5_WA EQU 0x400060c4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW5_WA_MSB +CYREG_USB_ARB_RW5_WA_MSB EQU 0x400060c5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW5_RA +CYREG_USB_ARB_RW5_RA EQU 0x400060c6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW5_RA_MSB +CYREG_USB_ARB_RW5_RA_MSB EQU 0x400060c7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW5_DR +CYREG_USB_ARB_RW5_DR EQU 0x400060c8 + ENDIF + IF :LNOT::DEF:CYREG_USB_BUS_RST_CNT +CYREG_USB_BUS_RST_CNT EQU 0x400060cc + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_BASE +CYDEV_USB_ARB_EP6_BASE EQU 0x400060d0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_SIZE +CYDEV_USB_ARB_EP6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP6_CFG +CYREG_USB_ARB_EP6_CFG EQU 0x400060d0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP6_INT_EN +CYREG_USB_ARB_EP6_INT_EN EQU 0x400060d1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP6_SR +CYREG_USB_ARB_EP6_SR EQU 0x400060d2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_BASE +CYDEV_USB_ARB_RW6_BASE EQU 0x400060d4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_SIZE +CYDEV_USB_ARB_RW6_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW6_WA +CYREG_USB_ARB_RW6_WA EQU 0x400060d4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW6_WA_MSB +CYREG_USB_ARB_RW6_WA_MSB EQU 0x400060d5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW6_RA +CYREG_USB_ARB_RW6_RA EQU 0x400060d6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW6_RA_MSB +CYREG_USB_ARB_RW6_RA_MSB EQU 0x400060d7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW6_DR +CYREG_USB_ARB_RW6_DR EQU 0x400060d8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_BASE +CYDEV_USB_ARB_EP7_BASE EQU 0x400060e0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_SIZE +CYDEV_USB_ARB_EP7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP7_CFG +CYREG_USB_ARB_EP7_CFG EQU 0x400060e0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP7_INT_EN +CYREG_USB_ARB_EP7_INT_EN EQU 0x400060e1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP7_SR +CYREG_USB_ARB_EP7_SR EQU 0x400060e2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_BASE +CYDEV_USB_ARB_RW7_BASE EQU 0x400060e4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_SIZE +CYDEV_USB_ARB_RW7_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW7_WA +CYREG_USB_ARB_RW7_WA EQU 0x400060e4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW7_WA_MSB +CYREG_USB_ARB_RW7_WA_MSB EQU 0x400060e5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW7_RA +CYREG_USB_ARB_RW7_RA EQU 0x400060e6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW7_RA_MSB +CYREG_USB_ARB_RW7_RA_MSB EQU 0x400060e7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW7_DR +CYREG_USB_ARB_RW7_DR EQU 0x400060e8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_BASE +CYDEV_USB_ARB_EP8_BASE EQU 0x400060f0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_SIZE +CYDEV_USB_ARB_EP8_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP8_CFG +CYREG_USB_ARB_EP8_CFG EQU 0x400060f0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP8_INT_EN +CYREG_USB_ARB_EP8_INT_EN EQU 0x400060f1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP8_SR +CYREG_USB_ARB_EP8_SR EQU 0x400060f2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_BASE +CYDEV_USB_ARB_RW8_BASE EQU 0x400060f4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_SIZE +CYDEV_USB_ARB_RW8_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW8_WA +CYREG_USB_ARB_RW8_WA EQU 0x400060f4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW8_WA_MSB +CYREG_USB_ARB_RW8_WA_MSB EQU 0x400060f5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW8_RA +CYREG_USB_ARB_RW8_RA EQU 0x400060f6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW8_RA_MSB +CYREG_USB_ARB_RW8_RA_MSB EQU 0x400060f7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW8_DR +CYREG_USB_ARB_RW8_DR EQU 0x400060f8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_BASE +CYDEV_USB_MEM_BASE EQU 0x40006100 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_SIZE +CYDEV_USB_MEM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYREG_USB_MEM_DATA_MBASE +CYREG_USB_MEM_DATA_MBASE EQU 0x40006100 + ENDIF + IF :LNOT::DEF:CYREG_USB_MEM_DATA_MSIZE +CYREG_USB_MEM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_BASE +CYDEV_UWRK_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_SIZE +CYDEV_UWRK_SIZE EQU 0x00000b60 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_BASE +CYDEV_UWRK_UWRK8_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_SIZE +CYDEV_UWRK_UWRK8_SIZE EQU 0x000003b0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_BASE +CYDEV_UWRK_UWRK8_B0_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_SIZE +CYDEV_UWRK_UWRK8_B0_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_A0 +CYREG_B0_UDB00_A0 EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_A0 +CYREG_B0_UDB01_A0 EQU 0x40006401 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_A0 +CYREG_B0_UDB02_A0 EQU 0x40006402 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_A0 +CYREG_B0_UDB03_A0 EQU 0x40006403 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_A0 +CYREG_B0_UDB04_A0 EQU 0x40006404 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_A0 +CYREG_B0_UDB05_A0 EQU 0x40006405 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_A0 +CYREG_B0_UDB06_A0 EQU 0x40006406 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_A0 +CYREG_B0_UDB07_A0 EQU 0x40006407 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_A0 +CYREG_B0_UDB08_A0 EQU 0x40006408 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_A0 +CYREG_B0_UDB09_A0 EQU 0x40006409 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_A0 +CYREG_B0_UDB10_A0 EQU 0x4000640a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_A0 +CYREG_B0_UDB11_A0 EQU 0x4000640b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_A0 +CYREG_B0_UDB12_A0 EQU 0x4000640c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_A0 +CYREG_B0_UDB13_A0 EQU 0x4000640d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_A0 +CYREG_B0_UDB14_A0 EQU 0x4000640e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_A0 +CYREG_B0_UDB15_A0 EQU 0x4000640f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_A1 +CYREG_B0_UDB00_A1 EQU 0x40006410 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_A1 +CYREG_B0_UDB01_A1 EQU 0x40006411 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_A1 +CYREG_B0_UDB02_A1 EQU 0x40006412 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_A1 +CYREG_B0_UDB03_A1 EQU 0x40006413 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_A1 +CYREG_B0_UDB04_A1 EQU 0x40006414 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_A1 +CYREG_B0_UDB05_A1 EQU 0x40006415 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_A1 +CYREG_B0_UDB06_A1 EQU 0x40006416 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_A1 +CYREG_B0_UDB07_A1 EQU 0x40006417 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_A1 +CYREG_B0_UDB08_A1 EQU 0x40006418 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_A1 +CYREG_B0_UDB09_A1 EQU 0x40006419 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_A1 +CYREG_B0_UDB10_A1 EQU 0x4000641a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_A1 +CYREG_B0_UDB11_A1 EQU 0x4000641b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_A1 +CYREG_B0_UDB12_A1 EQU 0x4000641c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_A1 +CYREG_B0_UDB13_A1 EQU 0x4000641d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_A1 +CYREG_B0_UDB14_A1 EQU 0x4000641e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_A1 +CYREG_B0_UDB15_A1 EQU 0x4000641f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_D0 +CYREG_B0_UDB00_D0 EQU 0x40006420 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_D0 +CYREG_B0_UDB01_D0 EQU 0x40006421 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_D0 +CYREG_B0_UDB02_D0 EQU 0x40006422 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_D0 +CYREG_B0_UDB03_D0 EQU 0x40006423 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_D0 +CYREG_B0_UDB04_D0 EQU 0x40006424 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_D0 +CYREG_B0_UDB05_D0 EQU 0x40006425 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_D0 +CYREG_B0_UDB06_D0 EQU 0x40006426 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_D0 +CYREG_B0_UDB07_D0 EQU 0x40006427 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_D0 +CYREG_B0_UDB08_D0 EQU 0x40006428 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_D0 +CYREG_B0_UDB09_D0 EQU 0x40006429 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_D0 +CYREG_B0_UDB10_D0 EQU 0x4000642a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_D0 +CYREG_B0_UDB11_D0 EQU 0x4000642b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_D0 +CYREG_B0_UDB12_D0 EQU 0x4000642c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_D0 +CYREG_B0_UDB13_D0 EQU 0x4000642d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_D0 +CYREG_B0_UDB14_D0 EQU 0x4000642e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_D0 +CYREG_B0_UDB15_D0 EQU 0x4000642f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_D1 +CYREG_B0_UDB00_D1 EQU 0x40006430 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_D1 +CYREG_B0_UDB01_D1 EQU 0x40006431 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_D1 +CYREG_B0_UDB02_D1 EQU 0x40006432 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_D1 +CYREG_B0_UDB03_D1 EQU 0x40006433 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_D1 +CYREG_B0_UDB04_D1 EQU 0x40006434 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_D1 +CYREG_B0_UDB05_D1 EQU 0x40006435 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_D1 +CYREG_B0_UDB06_D1 EQU 0x40006436 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_D1 +CYREG_B0_UDB07_D1 EQU 0x40006437 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_D1 +CYREG_B0_UDB08_D1 EQU 0x40006438 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_D1 +CYREG_B0_UDB09_D1 EQU 0x40006439 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_D1 +CYREG_B0_UDB10_D1 EQU 0x4000643a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_D1 +CYREG_B0_UDB11_D1 EQU 0x4000643b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_D1 +CYREG_B0_UDB12_D1 EQU 0x4000643c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_D1 +CYREG_B0_UDB13_D1 EQU 0x4000643d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_D1 +CYREG_B0_UDB14_D1 EQU 0x4000643e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_D1 +CYREG_B0_UDB15_D1 EQU 0x4000643f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_F0 +CYREG_B0_UDB00_F0 EQU 0x40006440 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_F0 +CYREG_B0_UDB01_F0 EQU 0x40006441 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_F0 +CYREG_B0_UDB02_F0 EQU 0x40006442 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_F0 +CYREG_B0_UDB03_F0 EQU 0x40006443 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_F0 +CYREG_B0_UDB04_F0 EQU 0x40006444 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_F0 +CYREG_B0_UDB05_F0 EQU 0x40006445 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_F0 +CYREG_B0_UDB06_F0 EQU 0x40006446 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_F0 +CYREG_B0_UDB07_F0 EQU 0x40006447 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_F0 +CYREG_B0_UDB08_F0 EQU 0x40006448 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_F0 +CYREG_B0_UDB09_F0 EQU 0x40006449 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_F0 +CYREG_B0_UDB10_F0 EQU 0x4000644a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_F0 +CYREG_B0_UDB11_F0 EQU 0x4000644b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_F0 +CYREG_B0_UDB12_F0 EQU 0x4000644c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_F0 +CYREG_B0_UDB13_F0 EQU 0x4000644d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_F0 +CYREG_B0_UDB14_F0 EQU 0x4000644e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_F0 +CYREG_B0_UDB15_F0 EQU 0x4000644f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_F1 +CYREG_B0_UDB00_F1 EQU 0x40006450 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_F1 +CYREG_B0_UDB01_F1 EQU 0x40006451 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_F1 +CYREG_B0_UDB02_F1 EQU 0x40006452 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_F1 +CYREG_B0_UDB03_F1 EQU 0x40006453 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_F1 +CYREG_B0_UDB04_F1 EQU 0x40006454 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_F1 +CYREG_B0_UDB05_F1 EQU 0x40006455 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_F1 +CYREG_B0_UDB06_F1 EQU 0x40006456 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_F1 +CYREG_B0_UDB07_F1 EQU 0x40006457 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_F1 +CYREG_B0_UDB08_F1 EQU 0x40006458 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_F1 +CYREG_B0_UDB09_F1 EQU 0x40006459 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_F1 +CYREG_B0_UDB10_F1 EQU 0x4000645a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_F1 +CYREG_B0_UDB11_F1 EQU 0x4000645b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_F1 +CYREG_B0_UDB12_F1 EQU 0x4000645c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_F1 +CYREG_B0_UDB13_F1 EQU 0x4000645d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_F1 +CYREG_B0_UDB14_F1 EQU 0x4000645e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_F1 +CYREG_B0_UDB15_F1 EQU 0x4000645f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_ST +CYREG_B0_UDB00_ST EQU 0x40006460 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_ST +CYREG_B0_UDB01_ST EQU 0x40006461 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_ST +CYREG_B0_UDB02_ST EQU 0x40006462 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_ST +CYREG_B0_UDB03_ST EQU 0x40006463 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_ST +CYREG_B0_UDB04_ST EQU 0x40006464 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_ST +CYREG_B0_UDB05_ST EQU 0x40006465 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_ST +CYREG_B0_UDB06_ST EQU 0x40006466 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_ST +CYREG_B0_UDB07_ST EQU 0x40006467 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_ST +CYREG_B0_UDB08_ST EQU 0x40006468 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_ST +CYREG_B0_UDB09_ST EQU 0x40006469 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_ST +CYREG_B0_UDB10_ST EQU 0x4000646a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_ST +CYREG_B0_UDB11_ST EQU 0x4000646b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_ST +CYREG_B0_UDB12_ST EQU 0x4000646c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_ST +CYREG_B0_UDB13_ST EQU 0x4000646d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_ST +CYREG_B0_UDB14_ST EQU 0x4000646e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_ST +CYREG_B0_UDB15_ST EQU 0x4000646f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_CTL +CYREG_B0_UDB00_CTL EQU 0x40006470 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_CTL +CYREG_B0_UDB01_CTL EQU 0x40006471 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_CTL +CYREG_B0_UDB02_CTL EQU 0x40006472 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_CTL +CYREG_B0_UDB03_CTL EQU 0x40006473 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_CTL +CYREG_B0_UDB04_CTL EQU 0x40006474 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_CTL +CYREG_B0_UDB05_CTL EQU 0x40006475 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_CTL +CYREG_B0_UDB06_CTL EQU 0x40006476 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_CTL +CYREG_B0_UDB07_CTL EQU 0x40006477 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_CTL +CYREG_B0_UDB08_CTL EQU 0x40006478 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_CTL +CYREG_B0_UDB09_CTL EQU 0x40006479 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_CTL +CYREG_B0_UDB10_CTL EQU 0x4000647a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_CTL +CYREG_B0_UDB11_CTL EQU 0x4000647b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_CTL +CYREG_B0_UDB12_CTL EQU 0x4000647c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_CTL +CYREG_B0_UDB13_CTL EQU 0x4000647d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_CTL +CYREG_B0_UDB14_CTL EQU 0x4000647e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_CTL +CYREG_B0_UDB15_CTL EQU 0x4000647f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_MSK +CYREG_B0_UDB00_MSK EQU 0x40006480 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_MSK +CYREG_B0_UDB01_MSK EQU 0x40006481 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_MSK +CYREG_B0_UDB02_MSK EQU 0x40006482 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_MSK +CYREG_B0_UDB03_MSK EQU 0x40006483 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_MSK +CYREG_B0_UDB04_MSK EQU 0x40006484 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_MSK +CYREG_B0_UDB05_MSK EQU 0x40006485 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_MSK +CYREG_B0_UDB06_MSK EQU 0x40006486 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_MSK +CYREG_B0_UDB07_MSK EQU 0x40006487 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_MSK +CYREG_B0_UDB08_MSK EQU 0x40006488 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_MSK +CYREG_B0_UDB09_MSK EQU 0x40006489 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_MSK +CYREG_B0_UDB10_MSK EQU 0x4000648a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_MSK +CYREG_B0_UDB11_MSK EQU 0x4000648b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_MSK +CYREG_B0_UDB12_MSK EQU 0x4000648c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_MSK +CYREG_B0_UDB13_MSK EQU 0x4000648d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_MSK +CYREG_B0_UDB14_MSK EQU 0x4000648e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_MSK +CYREG_B0_UDB15_MSK EQU 0x4000648f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_ACTL +CYREG_B0_UDB00_ACTL EQU 0x40006490 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_ACTL +CYREG_B0_UDB01_ACTL EQU 0x40006491 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_ACTL +CYREG_B0_UDB02_ACTL EQU 0x40006492 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_ACTL +CYREG_B0_UDB03_ACTL EQU 0x40006493 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_ACTL +CYREG_B0_UDB04_ACTL EQU 0x40006494 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_ACTL +CYREG_B0_UDB05_ACTL EQU 0x40006495 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_ACTL +CYREG_B0_UDB06_ACTL EQU 0x40006496 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_ACTL +CYREG_B0_UDB07_ACTL EQU 0x40006497 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_ACTL +CYREG_B0_UDB08_ACTL EQU 0x40006498 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_ACTL +CYREG_B0_UDB09_ACTL EQU 0x40006499 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_ACTL +CYREG_B0_UDB10_ACTL EQU 0x4000649a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_ACTL +CYREG_B0_UDB11_ACTL EQU 0x4000649b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_ACTL +CYREG_B0_UDB12_ACTL EQU 0x4000649c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_ACTL +CYREG_B0_UDB13_ACTL EQU 0x4000649d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_ACTL +CYREG_B0_UDB14_ACTL EQU 0x4000649e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_ACTL +CYREG_B0_UDB15_ACTL EQU 0x4000649f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_MC +CYREG_B0_UDB00_MC EQU 0x400064a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_MC +CYREG_B0_UDB01_MC EQU 0x400064a1 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_MC +CYREG_B0_UDB02_MC EQU 0x400064a2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_MC +CYREG_B0_UDB03_MC EQU 0x400064a3 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_MC +CYREG_B0_UDB04_MC EQU 0x400064a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_MC +CYREG_B0_UDB05_MC EQU 0x400064a5 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_MC +CYREG_B0_UDB06_MC EQU 0x400064a6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_MC +CYREG_B0_UDB07_MC EQU 0x400064a7 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_MC +CYREG_B0_UDB08_MC EQU 0x400064a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_MC +CYREG_B0_UDB09_MC EQU 0x400064a9 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_MC +CYREG_B0_UDB10_MC EQU 0x400064aa + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_MC +CYREG_B0_UDB11_MC EQU 0x400064ab + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_MC +CYREG_B0_UDB12_MC EQU 0x400064ac + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_MC +CYREG_B0_UDB13_MC EQU 0x400064ad + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_MC +CYREG_B0_UDB14_MC EQU 0x400064ae + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_MC +CYREG_B0_UDB15_MC EQU 0x400064af + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_BASE +CYDEV_UWRK_UWRK8_B1_BASE EQU 0x40006500 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_SIZE +CYDEV_UWRK_UWRK8_B1_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_A0 +CYREG_B1_UDB04_A0 EQU 0x40006504 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_A0 +CYREG_B1_UDB05_A0 EQU 0x40006505 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_A0 +CYREG_B1_UDB06_A0 EQU 0x40006506 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_A0 +CYREG_B1_UDB07_A0 EQU 0x40006507 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_A0 +CYREG_B1_UDB08_A0 EQU 0x40006508 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_A0 +CYREG_B1_UDB09_A0 EQU 0x40006509 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_A0 +CYREG_B1_UDB10_A0 EQU 0x4000650a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_A0 +CYREG_B1_UDB11_A0 EQU 0x4000650b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_A1 +CYREG_B1_UDB04_A1 EQU 0x40006514 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_A1 +CYREG_B1_UDB05_A1 EQU 0x40006515 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_A1 +CYREG_B1_UDB06_A1 EQU 0x40006516 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_A1 +CYREG_B1_UDB07_A1 EQU 0x40006517 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_A1 +CYREG_B1_UDB08_A1 EQU 0x40006518 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_A1 +CYREG_B1_UDB09_A1 EQU 0x40006519 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_A1 +CYREG_B1_UDB10_A1 EQU 0x4000651a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_A1 +CYREG_B1_UDB11_A1 EQU 0x4000651b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_D0 +CYREG_B1_UDB04_D0 EQU 0x40006524 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_D0 +CYREG_B1_UDB05_D0 EQU 0x40006525 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_D0 +CYREG_B1_UDB06_D0 EQU 0x40006526 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_D0 +CYREG_B1_UDB07_D0 EQU 0x40006527 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_D0 +CYREG_B1_UDB08_D0 EQU 0x40006528 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_D0 +CYREG_B1_UDB09_D0 EQU 0x40006529 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_D0 +CYREG_B1_UDB10_D0 EQU 0x4000652a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_D0 +CYREG_B1_UDB11_D0 EQU 0x4000652b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_D1 +CYREG_B1_UDB04_D1 EQU 0x40006534 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_D1 +CYREG_B1_UDB05_D1 EQU 0x40006535 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_D1 +CYREG_B1_UDB06_D1 EQU 0x40006536 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_D1 +CYREG_B1_UDB07_D1 EQU 0x40006537 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_D1 +CYREG_B1_UDB08_D1 EQU 0x40006538 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_D1 +CYREG_B1_UDB09_D1 EQU 0x40006539 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_D1 +CYREG_B1_UDB10_D1 EQU 0x4000653a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_D1 +CYREG_B1_UDB11_D1 EQU 0x4000653b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_F0 +CYREG_B1_UDB04_F0 EQU 0x40006544 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_F0 +CYREG_B1_UDB05_F0 EQU 0x40006545 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_F0 +CYREG_B1_UDB06_F0 EQU 0x40006546 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_F0 +CYREG_B1_UDB07_F0 EQU 0x40006547 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_F0 +CYREG_B1_UDB08_F0 EQU 0x40006548 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_F0 +CYREG_B1_UDB09_F0 EQU 0x40006549 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_F0 +CYREG_B1_UDB10_F0 EQU 0x4000654a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_F0 +CYREG_B1_UDB11_F0 EQU 0x4000654b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_F1 +CYREG_B1_UDB04_F1 EQU 0x40006554 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_F1 +CYREG_B1_UDB05_F1 EQU 0x40006555 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_F1 +CYREG_B1_UDB06_F1 EQU 0x40006556 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_F1 +CYREG_B1_UDB07_F1 EQU 0x40006557 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_F1 +CYREG_B1_UDB08_F1 EQU 0x40006558 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_F1 +CYREG_B1_UDB09_F1 EQU 0x40006559 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_F1 +CYREG_B1_UDB10_F1 EQU 0x4000655a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_F1 +CYREG_B1_UDB11_F1 EQU 0x4000655b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_ST +CYREG_B1_UDB04_ST EQU 0x40006564 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_ST +CYREG_B1_UDB05_ST EQU 0x40006565 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_ST +CYREG_B1_UDB06_ST EQU 0x40006566 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_ST +CYREG_B1_UDB07_ST EQU 0x40006567 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_ST +CYREG_B1_UDB08_ST EQU 0x40006568 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_ST +CYREG_B1_UDB09_ST EQU 0x40006569 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_ST +CYREG_B1_UDB10_ST EQU 0x4000656a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_ST +CYREG_B1_UDB11_ST EQU 0x4000656b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_CTL +CYREG_B1_UDB04_CTL EQU 0x40006574 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_CTL +CYREG_B1_UDB05_CTL EQU 0x40006575 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_CTL +CYREG_B1_UDB06_CTL EQU 0x40006576 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_CTL +CYREG_B1_UDB07_CTL EQU 0x40006577 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_CTL +CYREG_B1_UDB08_CTL EQU 0x40006578 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_CTL +CYREG_B1_UDB09_CTL EQU 0x40006579 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_CTL +CYREG_B1_UDB10_CTL EQU 0x4000657a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_CTL +CYREG_B1_UDB11_CTL EQU 0x4000657b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_MSK +CYREG_B1_UDB04_MSK EQU 0x40006584 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_MSK +CYREG_B1_UDB05_MSK EQU 0x40006585 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_MSK +CYREG_B1_UDB06_MSK EQU 0x40006586 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_MSK +CYREG_B1_UDB07_MSK EQU 0x40006587 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_MSK +CYREG_B1_UDB08_MSK EQU 0x40006588 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_MSK +CYREG_B1_UDB09_MSK EQU 0x40006589 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_MSK +CYREG_B1_UDB10_MSK EQU 0x4000658a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_MSK +CYREG_B1_UDB11_MSK EQU 0x4000658b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_ACTL +CYREG_B1_UDB04_ACTL EQU 0x40006594 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_ACTL +CYREG_B1_UDB05_ACTL EQU 0x40006595 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_ACTL +CYREG_B1_UDB06_ACTL EQU 0x40006596 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_ACTL +CYREG_B1_UDB07_ACTL EQU 0x40006597 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_ACTL +CYREG_B1_UDB08_ACTL EQU 0x40006598 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_ACTL +CYREG_B1_UDB09_ACTL EQU 0x40006599 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_ACTL +CYREG_B1_UDB10_ACTL EQU 0x4000659a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_ACTL +CYREG_B1_UDB11_ACTL EQU 0x4000659b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_MC +CYREG_B1_UDB04_MC EQU 0x400065a4 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_MC +CYREG_B1_UDB05_MC EQU 0x400065a5 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_MC +CYREG_B1_UDB06_MC EQU 0x400065a6 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_MC +CYREG_B1_UDB07_MC EQU 0x400065a7 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_MC +CYREG_B1_UDB08_MC EQU 0x400065a8 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_MC +CYREG_B1_UDB09_MC EQU 0x400065a9 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_MC +CYREG_B1_UDB10_MC EQU 0x400065aa + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_MC +CYREG_B1_UDB11_MC EQU 0x400065ab + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_BASE +CYDEV_UWRK_UWRK16_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_SIZE +CYDEV_UWRK_UWRK16_SIZE EQU 0x00000760 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_BASE +CYDEV_UWRK_UWRK16_CAT_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_SIZE +CYDEV_UWRK_UWRK16_CAT_SIZE EQU 0x00000760 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_BASE +CYDEV_UWRK_UWRK16_CAT_B0_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_SIZE +CYDEV_UWRK_UWRK16_CAT_B0_SIZE EQU 0x00000160 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_A0_A1 +CYREG_B0_UDB00_A0_A1 EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_A0_A1 +CYREG_B0_UDB01_A0_A1 EQU 0x40006802 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_A0_A1 +CYREG_B0_UDB02_A0_A1 EQU 0x40006804 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_A0_A1 +CYREG_B0_UDB03_A0_A1 EQU 0x40006806 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_A0_A1 +CYREG_B0_UDB04_A0_A1 EQU 0x40006808 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_A0_A1 +CYREG_B0_UDB05_A0_A1 EQU 0x4000680a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_A0_A1 +CYREG_B0_UDB06_A0_A1 EQU 0x4000680c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_A0_A1 +CYREG_B0_UDB07_A0_A1 EQU 0x4000680e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_A0_A1 +CYREG_B0_UDB08_A0_A1 EQU 0x40006810 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_A0_A1 +CYREG_B0_UDB09_A0_A1 EQU 0x40006812 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_A0_A1 +CYREG_B0_UDB10_A0_A1 EQU 0x40006814 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_A0_A1 +CYREG_B0_UDB11_A0_A1 EQU 0x40006816 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_A0_A1 +CYREG_B0_UDB12_A0_A1 EQU 0x40006818 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_A0_A1 +CYREG_B0_UDB13_A0_A1 EQU 0x4000681a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_A0_A1 +CYREG_B0_UDB14_A0_A1 EQU 0x4000681c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_A0_A1 +CYREG_B0_UDB15_A0_A1 EQU 0x4000681e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_D0_D1 +CYREG_B0_UDB00_D0_D1 EQU 0x40006840 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_D0_D1 +CYREG_B0_UDB01_D0_D1 EQU 0x40006842 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_D0_D1 +CYREG_B0_UDB02_D0_D1 EQU 0x40006844 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_D0_D1 +CYREG_B0_UDB03_D0_D1 EQU 0x40006846 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_D0_D1 +CYREG_B0_UDB04_D0_D1 EQU 0x40006848 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_D0_D1 +CYREG_B0_UDB05_D0_D1 EQU 0x4000684a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_D0_D1 +CYREG_B0_UDB06_D0_D1 EQU 0x4000684c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_D0_D1 +CYREG_B0_UDB07_D0_D1 EQU 0x4000684e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_D0_D1 +CYREG_B0_UDB08_D0_D1 EQU 0x40006850 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_D0_D1 +CYREG_B0_UDB09_D0_D1 EQU 0x40006852 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_D0_D1 +CYREG_B0_UDB10_D0_D1 EQU 0x40006854 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_D0_D1 +CYREG_B0_UDB11_D0_D1 EQU 0x40006856 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_D0_D1 +CYREG_B0_UDB12_D0_D1 EQU 0x40006858 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_D0_D1 +CYREG_B0_UDB13_D0_D1 EQU 0x4000685a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_D0_D1 +CYREG_B0_UDB14_D0_D1 EQU 0x4000685c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_D0_D1 +CYREG_B0_UDB15_D0_D1 EQU 0x4000685e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_F0_F1 +CYREG_B0_UDB00_F0_F1 EQU 0x40006880 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_F0_F1 +CYREG_B0_UDB01_F0_F1 EQU 0x40006882 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_F0_F1 +CYREG_B0_UDB02_F0_F1 EQU 0x40006884 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_F0_F1 +CYREG_B0_UDB03_F0_F1 EQU 0x40006886 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_F0_F1 +CYREG_B0_UDB04_F0_F1 EQU 0x40006888 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_F0_F1 +CYREG_B0_UDB05_F0_F1 EQU 0x4000688a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_F0_F1 +CYREG_B0_UDB06_F0_F1 EQU 0x4000688c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_F0_F1 +CYREG_B0_UDB07_F0_F1 EQU 0x4000688e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_F0_F1 +CYREG_B0_UDB08_F0_F1 EQU 0x40006890 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_F0_F1 +CYREG_B0_UDB09_F0_F1 EQU 0x40006892 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_F0_F1 +CYREG_B0_UDB10_F0_F1 EQU 0x40006894 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_F0_F1 +CYREG_B0_UDB11_F0_F1 EQU 0x40006896 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_F0_F1 +CYREG_B0_UDB12_F0_F1 EQU 0x40006898 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_F0_F1 +CYREG_B0_UDB13_F0_F1 EQU 0x4000689a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_F0_F1 +CYREG_B0_UDB14_F0_F1 EQU 0x4000689c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_F0_F1 +CYREG_B0_UDB15_F0_F1 EQU 0x4000689e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_ST_CTL +CYREG_B0_UDB00_ST_CTL EQU 0x400068c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_ST_CTL +CYREG_B0_UDB01_ST_CTL EQU 0x400068c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_ST_CTL +CYREG_B0_UDB02_ST_CTL EQU 0x400068c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_ST_CTL +CYREG_B0_UDB03_ST_CTL EQU 0x400068c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_ST_CTL +CYREG_B0_UDB04_ST_CTL EQU 0x400068c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_ST_CTL +CYREG_B0_UDB05_ST_CTL EQU 0x400068ca + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_ST_CTL +CYREG_B0_UDB06_ST_CTL EQU 0x400068cc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_ST_CTL +CYREG_B0_UDB07_ST_CTL EQU 0x400068ce + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_ST_CTL +CYREG_B0_UDB08_ST_CTL EQU 0x400068d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_ST_CTL +CYREG_B0_UDB09_ST_CTL EQU 0x400068d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_ST_CTL +CYREG_B0_UDB10_ST_CTL EQU 0x400068d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_ST_CTL +CYREG_B0_UDB11_ST_CTL EQU 0x400068d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_ST_CTL +CYREG_B0_UDB12_ST_CTL EQU 0x400068d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_ST_CTL +CYREG_B0_UDB13_ST_CTL EQU 0x400068da + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_ST_CTL +CYREG_B0_UDB14_ST_CTL EQU 0x400068dc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_ST_CTL +CYREG_B0_UDB15_ST_CTL EQU 0x400068de + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_MSK_ACTL +CYREG_B0_UDB00_MSK_ACTL EQU 0x40006900 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_MSK_ACTL +CYREG_B0_UDB01_MSK_ACTL EQU 0x40006902 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_MSK_ACTL +CYREG_B0_UDB02_MSK_ACTL EQU 0x40006904 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_MSK_ACTL +CYREG_B0_UDB03_MSK_ACTL EQU 0x40006906 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_MSK_ACTL +CYREG_B0_UDB04_MSK_ACTL EQU 0x40006908 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_MSK_ACTL +CYREG_B0_UDB05_MSK_ACTL EQU 0x4000690a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_MSK_ACTL +CYREG_B0_UDB06_MSK_ACTL EQU 0x4000690c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_MSK_ACTL +CYREG_B0_UDB07_MSK_ACTL EQU 0x4000690e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_MSK_ACTL +CYREG_B0_UDB08_MSK_ACTL EQU 0x40006910 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_MSK_ACTL +CYREG_B0_UDB09_MSK_ACTL EQU 0x40006912 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_MSK_ACTL +CYREG_B0_UDB10_MSK_ACTL EQU 0x40006914 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_MSK_ACTL +CYREG_B0_UDB11_MSK_ACTL EQU 0x40006916 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_MSK_ACTL +CYREG_B0_UDB12_MSK_ACTL EQU 0x40006918 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_MSK_ACTL +CYREG_B0_UDB13_MSK_ACTL EQU 0x4000691a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_MSK_ACTL +CYREG_B0_UDB14_MSK_ACTL EQU 0x4000691c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_MSK_ACTL +CYREG_B0_UDB15_MSK_ACTL EQU 0x4000691e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_MC_00 +CYREG_B0_UDB00_MC_00 EQU 0x40006940 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_MC_00 +CYREG_B0_UDB01_MC_00 EQU 0x40006942 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_MC_00 +CYREG_B0_UDB02_MC_00 EQU 0x40006944 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_MC_00 +CYREG_B0_UDB03_MC_00 EQU 0x40006946 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_MC_00 +CYREG_B0_UDB04_MC_00 EQU 0x40006948 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_MC_00 +CYREG_B0_UDB05_MC_00 EQU 0x4000694a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_MC_00 +CYREG_B0_UDB06_MC_00 EQU 0x4000694c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_MC_00 +CYREG_B0_UDB07_MC_00 EQU 0x4000694e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_MC_00 +CYREG_B0_UDB08_MC_00 EQU 0x40006950 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_MC_00 +CYREG_B0_UDB09_MC_00 EQU 0x40006952 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_MC_00 +CYREG_B0_UDB10_MC_00 EQU 0x40006954 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_MC_00 +CYREG_B0_UDB11_MC_00 EQU 0x40006956 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_MC_00 +CYREG_B0_UDB12_MC_00 EQU 0x40006958 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_MC_00 +CYREG_B0_UDB13_MC_00 EQU 0x4000695a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_MC_00 +CYREG_B0_UDB14_MC_00 EQU 0x4000695c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_MC_00 +CYREG_B0_UDB15_MC_00 EQU 0x4000695e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_BASE +CYDEV_UWRK_UWRK16_CAT_B1_BASE EQU 0x40006a00 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_SIZE +CYDEV_UWRK_UWRK16_CAT_B1_SIZE EQU 0x00000160 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_A0_A1 +CYREG_B1_UDB04_A0_A1 EQU 0x40006a08 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_A0_A1 +CYREG_B1_UDB05_A0_A1 EQU 0x40006a0a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_A0_A1 +CYREG_B1_UDB06_A0_A1 EQU 0x40006a0c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_A0_A1 +CYREG_B1_UDB07_A0_A1 EQU 0x40006a0e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_A0_A1 +CYREG_B1_UDB08_A0_A1 EQU 0x40006a10 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_A0_A1 +CYREG_B1_UDB09_A0_A1 EQU 0x40006a12 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_A0_A1 +CYREG_B1_UDB10_A0_A1 EQU 0x40006a14 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_A0_A1 +CYREG_B1_UDB11_A0_A1 EQU 0x40006a16 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_D0_D1 +CYREG_B1_UDB04_D0_D1 EQU 0x40006a48 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_D0_D1 +CYREG_B1_UDB05_D0_D1 EQU 0x40006a4a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_D0_D1 +CYREG_B1_UDB06_D0_D1 EQU 0x40006a4c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_D0_D1 +CYREG_B1_UDB07_D0_D1 EQU 0x40006a4e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_D0_D1 +CYREG_B1_UDB08_D0_D1 EQU 0x40006a50 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_D0_D1 +CYREG_B1_UDB09_D0_D1 EQU 0x40006a52 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_D0_D1 +CYREG_B1_UDB10_D0_D1 EQU 0x40006a54 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_D0_D1 +CYREG_B1_UDB11_D0_D1 EQU 0x40006a56 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_F0_F1 +CYREG_B1_UDB04_F0_F1 EQU 0x40006a88 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_F0_F1 +CYREG_B1_UDB05_F0_F1 EQU 0x40006a8a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_F0_F1 +CYREG_B1_UDB06_F0_F1 EQU 0x40006a8c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_F0_F1 +CYREG_B1_UDB07_F0_F1 EQU 0x40006a8e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_F0_F1 +CYREG_B1_UDB08_F0_F1 EQU 0x40006a90 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_F0_F1 +CYREG_B1_UDB09_F0_F1 EQU 0x40006a92 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_F0_F1 +CYREG_B1_UDB10_F0_F1 EQU 0x40006a94 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_F0_F1 +CYREG_B1_UDB11_F0_F1 EQU 0x40006a96 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_ST_CTL +CYREG_B1_UDB04_ST_CTL EQU 0x40006ac8 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_ST_CTL +CYREG_B1_UDB05_ST_CTL EQU 0x40006aca + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_ST_CTL +CYREG_B1_UDB06_ST_CTL EQU 0x40006acc + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_ST_CTL +CYREG_B1_UDB07_ST_CTL EQU 0x40006ace + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_ST_CTL +CYREG_B1_UDB08_ST_CTL EQU 0x40006ad0 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_ST_CTL +CYREG_B1_UDB09_ST_CTL EQU 0x40006ad2 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_ST_CTL +CYREG_B1_UDB10_ST_CTL EQU 0x40006ad4 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_ST_CTL +CYREG_B1_UDB11_ST_CTL EQU 0x40006ad6 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_MSK_ACTL +CYREG_B1_UDB04_MSK_ACTL EQU 0x40006b08 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_MSK_ACTL +CYREG_B1_UDB05_MSK_ACTL EQU 0x40006b0a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_MSK_ACTL +CYREG_B1_UDB06_MSK_ACTL EQU 0x40006b0c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_MSK_ACTL +CYREG_B1_UDB07_MSK_ACTL EQU 0x40006b0e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_MSK_ACTL +CYREG_B1_UDB08_MSK_ACTL EQU 0x40006b10 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_MSK_ACTL +CYREG_B1_UDB09_MSK_ACTL EQU 0x40006b12 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_MSK_ACTL +CYREG_B1_UDB10_MSK_ACTL EQU 0x40006b14 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_MSK_ACTL +CYREG_B1_UDB11_MSK_ACTL EQU 0x40006b16 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_MC_00 +CYREG_B1_UDB04_MC_00 EQU 0x40006b48 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_MC_00 +CYREG_B1_UDB05_MC_00 EQU 0x40006b4a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_MC_00 +CYREG_B1_UDB06_MC_00 EQU 0x40006b4c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_MC_00 +CYREG_B1_UDB07_MC_00 EQU 0x40006b4e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_MC_00 +CYREG_B1_UDB08_MC_00 EQU 0x40006b50 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_MC_00 +CYREG_B1_UDB09_MC_00 EQU 0x40006b52 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_MC_00 +CYREG_B1_UDB10_MC_00 EQU 0x40006b54 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_MC_00 +CYREG_B1_UDB11_MC_00 EQU 0x40006b56 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_BASE +CYDEV_UWRK_UWRK16_DEF_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_SIZE +CYDEV_UWRK_UWRK16_DEF_SIZE EQU 0x0000075e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_BASE +CYDEV_UWRK_UWRK16_DEF_B0_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_SIZE +CYDEV_UWRK_UWRK16_DEF_B0_SIZE EQU 0x0000015e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_A0 +CYREG_B0_UDB00_01_A0 EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_A0 +CYREG_B0_UDB01_02_A0 EQU 0x40006802 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_A0 +CYREG_B0_UDB02_03_A0 EQU 0x40006804 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_A0 +CYREG_B0_UDB03_04_A0 EQU 0x40006806 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_A0 +CYREG_B0_UDB04_05_A0 EQU 0x40006808 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_A0 +CYREG_B0_UDB05_06_A0 EQU 0x4000680a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_A0 +CYREG_B0_UDB06_07_A0 EQU 0x4000680c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_A0 +CYREG_B0_UDB07_08_A0 EQU 0x4000680e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_A0 +CYREG_B0_UDB08_09_A0 EQU 0x40006810 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_A0 +CYREG_B0_UDB09_10_A0 EQU 0x40006812 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_A0 +CYREG_B0_UDB10_11_A0 EQU 0x40006814 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_A0 +CYREG_B0_UDB11_12_A0 EQU 0x40006816 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_A0 +CYREG_B0_UDB12_13_A0 EQU 0x40006818 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_A0 +CYREG_B0_UDB13_14_A0 EQU 0x4000681a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_A0 +CYREG_B0_UDB14_15_A0 EQU 0x4000681c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_A1 +CYREG_B0_UDB00_01_A1 EQU 0x40006820 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_A1 +CYREG_B0_UDB01_02_A1 EQU 0x40006822 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_A1 +CYREG_B0_UDB02_03_A1 EQU 0x40006824 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_A1 +CYREG_B0_UDB03_04_A1 EQU 0x40006826 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_A1 +CYREG_B0_UDB04_05_A1 EQU 0x40006828 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_A1 +CYREG_B0_UDB05_06_A1 EQU 0x4000682a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_A1 +CYREG_B0_UDB06_07_A1 EQU 0x4000682c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_A1 +CYREG_B0_UDB07_08_A1 EQU 0x4000682e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_A1 +CYREG_B0_UDB08_09_A1 EQU 0x40006830 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_A1 +CYREG_B0_UDB09_10_A1 EQU 0x40006832 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_A1 +CYREG_B0_UDB10_11_A1 EQU 0x40006834 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_A1 +CYREG_B0_UDB11_12_A1 EQU 0x40006836 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_A1 +CYREG_B0_UDB12_13_A1 EQU 0x40006838 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_A1 +CYREG_B0_UDB13_14_A1 EQU 0x4000683a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_A1 +CYREG_B0_UDB14_15_A1 EQU 0x4000683c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_D0 +CYREG_B0_UDB00_01_D0 EQU 0x40006840 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_D0 +CYREG_B0_UDB01_02_D0 EQU 0x40006842 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_D0 +CYREG_B0_UDB02_03_D0 EQU 0x40006844 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_D0 +CYREG_B0_UDB03_04_D0 EQU 0x40006846 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_D0 +CYREG_B0_UDB04_05_D0 EQU 0x40006848 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_D0 +CYREG_B0_UDB05_06_D0 EQU 0x4000684a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_D0 +CYREG_B0_UDB06_07_D0 EQU 0x4000684c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_D0 +CYREG_B0_UDB07_08_D0 EQU 0x4000684e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_D0 +CYREG_B0_UDB08_09_D0 EQU 0x40006850 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_D0 +CYREG_B0_UDB09_10_D0 EQU 0x40006852 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_D0 +CYREG_B0_UDB10_11_D0 EQU 0x40006854 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_D0 +CYREG_B0_UDB11_12_D0 EQU 0x40006856 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_D0 +CYREG_B0_UDB12_13_D0 EQU 0x40006858 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_D0 +CYREG_B0_UDB13_14_D0 EQU 0x4000685a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_D0 +CYREG_B0_UDB14_15_D0 EQU 0x4000685c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_D1 +CYREG_B0_UDB00_01_D1 EQU 0x40006860 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_D1 +CYREG_B0_UDB01_02_D1 EQU 0x40006862 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_D1 +CYREG_B0_UDB02_03_D1 EQU 0x40006864 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_D1 +CYREG_B0_UDB03_04_D1 EQU 0x40006866 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_D1 +CYREG_B0_UDB04_05_D1 EQU 0x40006868 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_D1 +CYREG_B0_UDB05_06_D1 EQU 0x4000686a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_D1 +CYREG_B0_UDB06_07_D1 EQU 0x4000686c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_D1 +CYREG_B0_UDB07_08_D1 EQU 0x4000686e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_D1 +CYREG_B0_UDB08_09_D1 EQU 0x40006870 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_D1 +CYREG_B0_UDB09_10_D1 EQU 0x40006872 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_D1 +CYREG_B0_UDB10_11_D1 EQU 0x40006874 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_D1 +CYREG_B0_UDB11_12_D1 EQU 0x40006876 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_D1 +CYREG_B0_UDB12_13_D1 EQU 0x40006878 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_D1 +CYREG_B0_UDB13_14_D1 EQU 0x4000687a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_D1 +CYREG_B0_UDB14_15_D1 EQU 0x4000687c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_F0 +CYREG_B0_UDB00_01_F0 EQU 0x40006880 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_F0 +CYREG_B0_UDB01_02_F0 EQU 0x40006882 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_F0 +CYREG_B0_UDB02_03_F0 EQU 0x40006884 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_F0 +CYREG_B0_UDB03_04_F0 EQU 0x40006886 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_F0 +CYREG_B0_UDB04_05_F0 EQU 0x40006888 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_F0 +CYREG_B0_UDB05_06_F0 EQU 0x4000688a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_F0 +CYREG_B0_UDB06_07_F0 EQU 0x4000688c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_F0 +CYREG_B0_UDB07_08_F0 EQU 0x4000688e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_F0 +CYREG_B0_UDB08_09_F0 EQU 0x40006890 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_F0 +CYREG_B0_UDB09_10_F0 EQU 0x40006892 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_F0 +CYREG_B0_UDB10_11_F0 EQU 0x40006894 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_F0 +CYREG_B0_UDB11_12_F0 EQU 0x40006896 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_F0 +CYREG_B0_UDB12_13_F0 EQU 0x40006898 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_F0 +CYREG_B0_UDB13_14_F0 EQU 0x4000689a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_F0 +CYREG_B0_UDB14_15_F0 EQU 0x4000689c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_F1 +CYREG_B0_UDB00_01_F1 EQU 0x400068a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_F1 +CYREG_B0_UDB01_02_F1 EQU 0x400068a2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_F1 +CYREG_B0_UDB02_03_F1 EQU 0x400068a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_F1 +CYREG_B0_UDB03_04_F1 EQU 0x400068a6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_F1 +CYREG_B0_UDB04_05_F1 EQU 0x400068a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_F1 +CYREG_B0_UDB05_06_F1 EQU 0x400068aa + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_F1 +CYREG_B0_UDB06_07_F1 EQU 0x400068ac + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_F1 +CYREG_B0_UDB07_08_F1 EQU 0x400068ae + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_F1 +CYREG_B0_UDB08_09_F1 EQU 0x400068b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_F1 +CYREG_B0_UDB09_10_F1 EQU 0x400068b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_F1 +CYREG_B0_UDB10_11_F1 EQU 0x400068b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_F1 +CYREG_B0_UDB11_12_F1 EQU 0x400068b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_F1 +CYREG_B0_UDB12_13_F1 EQU 0x400068b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_F1 +CYREG_B0_UDB13_14_F1 EQU 0x400068ba + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_F1 +CYREG_B0_UDB14_15_F1 EQU 0x400068bc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_ST +CYREG_B0_UDB00_01_ST EQU 0x400068c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_ST +CYREG_B0_UDB01_02_ST EQU 0x400068c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_ST +CYREG_B0_UDB02_03_ST EQU 0x400068c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_ST +CYREG_B0_UDB03_04_ST EQU 0x400068c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_ST +CYREG_B0_UDB04_05_ST EQU 0x400068c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_ST +CYREG_B0_UDB05_06_ST EQU 0x400068ca + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_ST +CYREG_B0_UDB06_07_ST EQU 0x400068cc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_ST +CYREG_B0_UDB07_08_ST EQU 0x400068ce + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_ST +CYREG_B0_UDB08_09_ST EQU 0x400068d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_ST +CYREG_B0_UDB09_10_ST EQU 0x400068d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_ST +CYREG_B0_UDB10_11_ST EQU 0x400068d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_ST +CYREG_B0_UDB11_12_ST EQU 0x400068d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_ST +CYREG_B0_UDB12_13_ST EQU 0x400068d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_ST +CYREG_B0_UDB13_14_ST EQU 0x400068da + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_ST +CYREG_B0_UDB14_15_ST EQU 0x400068dc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_CTL +CYREG_B0_UDB00_01_CTL EQU 0x400068e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_CTL +CYREG_B0_UDB01_02_CTL EQU 0x400068e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_CTL +CYREG_B0_UDB02_03_CTL EQU 0x400068e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_CTL +CYREG_B0_UDB03_04_CTL EQU 0x400068e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_CTL +CYREG_B0_UDB04_05_CTL EQU 0x400068e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_CTL +CYREG_B0_UDB05_06_CTL EQU 0x400068ea + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_CTL +CYREG_B0_UDB06_07_CTL EQU 0x400068ec + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_CTL +CYREG_B0_UDB07_08_CTL EQU 0x400068ee + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_CTL +CYREG_B0_UDB08_09_CTL EQU 0x400068f0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_CTL +CYREG_B0_UDB09_10_CTL EQU 0x400068f2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_CTL +CYREG_B0_UDB10_11_CTL EQU 0x400068f4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_CTL +CYREG_B0_UDB11_12_CTL EQU 0x400068f6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_CTL +CYREG_B0_UDB12_13_CTL EQU 0x400068f8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_CTL +CYREG_B0_UDB13_14_CTL EQU 0x400068fa + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_CTL +CYREG_B0_UDB14_15_CTL EQU 0x400068fc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_MSK +CYREG_B0_UDB00_01_MSK EQU 0x40006900 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_MSK +CYREG_B0_UDB01_02_MSK EQU 0x40006902 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_MSK +CYREG_B0_UDB02_03_MSK EQU 0x40006904 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_MSK +CYREG_B0_UDB03_04_MSK EQU 0x40006906 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_MSK +CYREG_B0_UDB04_05_MSK EQU 0x40006908 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_MSK +CYREG_B0_UDB05_06_MSK EQU 0x4000690a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_MSK +CYREG_B0_UDB06_07_MSK EQU 0x4000690c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_MSK +CYREG_B0_UDB07_08_MSK EQU 0x4000690e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_MSK +CYREG_B0_UDB08_09_MSK EQU 0x40006910 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_MSK +CYREG_B0_UDB09_10_MSK EQU 0x40006912 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_MSK +CYREG_B0_UDB10_11_MSK EQU 0x40006914 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_MSK +CYREG_B0_UDB11_12_MSK EQU 0x40006916 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_MSK +CYREG_B0_UDB12_13_MSK EQU 0x40006918 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_MSK +CYREG_B0_UDB13_14_MSK EQU 0x4000691a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_MSK +CYREG_B0_UDB14_15_MSK EQU 0x4000691c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_ACTL +CYREG_B0_UDB00_01_ACTL EQU 0x40006920 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_ACTL +CYREG_B0_UDB01_02_ACTL EQU 0x40006922 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_ACTL +CYREG_B0_UDB02_03_ACTL EQU 0x40006924 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_ACTL +CYREG_B0_UDB03_04_ACTL EQU 0x40006926 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_ACTL +CYREG_B0_UDB04_05_ACTL EQU 0x40006928 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_ACTL +CYREG_B0_UDB05_06_ACTL EQU 0x4000692a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_ACTL +CYREG_B0_UDB06_07_ACTL EQU 0x4000692c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_ACTL +CYREG_B0_UDB07_08_ACTL EQU 0x4000692e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_ACTL +CYREG_B0_UDB08_09_ACTL EQU 0x40006930 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_ACTL +CYREG_B0_UDB09_10_ACTL EQU 0x40006932 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_ACTL +CYREG_B0_UDB10_11_ACTL EQU 0x40006934 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_ACTL +CYREG_B0_UDB11_12_ACTL EQU 0x40006936 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_ACTL +CYREG_B0_UDB12_13_ACTL EQU 0x40006938 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_ACTL +CYREG_B0_UDB13_14_ACTL EQU 0x4000693a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_ACTL +CYREG_B0_UDB14_15_ACTL EQU 0x4000693c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_MC +CYREG_B0_UDB00_01_MC EQU 0x40006940 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_MC +CYREG_B0_UDB01_02_MC EQU 0x40006942 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_MC +CYREG_B0_UDB02_03_MC EQU 0x40006944 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_MC +CYREG_B0_UDB03_04_MC EQU 0x40006946 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_MC +CYREG_B0_UDB04_05_MC EQU 0x40006948 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_MC +CYREG_B0_UDB05_06_MC EQU 0x4000694a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_MC +CYREG_B0_UDB06_07_MC EQU 0x4000694c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_MC +CYREG_B0_UDB07_08_MC EQU 0x4000694e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_MC +CYREG_B0_UDB08_09_MC EQU 0x40006950 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_MC +CYREG_B0_UDB09_10_MC EQU 0x40006952 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_MC +CYREG_B0_UDB10_11_MC EQU 0x40006954 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_MC +CYREG_B0_UDB11_12_MC EQU 0x40006956 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_MC +CYREG_B0_UDB12_13_MC EQU 0x40006958 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_MC +CYREG_B0_UDB13_14_MC EQU 0x4000695a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_MC +CYREG_B0_UDB14_15_MC EQU 0x4000695c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_BASE +CYDEV_UWRK_UWRK16_DEF_B1_BASE EQU 0x40006a00 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_SIZE +CYDEV_UWRK_UWRK16_DEF_B1_SIZE EQU 0x0000015e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_A0 +CYREG_B1_UDB04_05_A0 EQU 0x40006a08 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_A0 +CYREG_B1_UDB05_06_A0 EQU 0x40006a0a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_A0 +CYREG_B1_UDB06_07_A0 EQU 0x40006a0c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_A0 +CYREG_B1_UDB07_08_A0 EQU 0x40006a0e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_A0 +CYREG_B1_UDB08_09_A0 EQU 0x40006a10 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_A0 +CYREG_B1_UDB09_10_A0 EQU 0x40006a12 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_A0 +CYREG_B1_UDB10_11_A0 EQU 0x40006a14 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_A0 +CYREG_B1_UDB11_12_A0 EQU 0x40006a16 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_A1 +CYREG_B1_UDB04_05_A1 EQU 0x40006a28 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_A1 +CYREG_B1_UDB05_06_A1 EQU 0x40006a2a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_A1 +CYREG_B1_UDB06_07_A1 EQU 0x40006a2c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_A1 +CYREG_B1_UDB07_08_A1 EQU 0x40006a2e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_A1 +CYREG_B1_UDB08_09_A1 EQU 0x40006a30 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_A1 +CYREG_B1_UDB09_10_A1 EQU 0x40006a32 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_A1 +CYREG_B1_UDB10_11_A1 EQU 0x40006a34 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_A1 +CYREG_B1_UDB11_12_A1 EQU 0x40006a36 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_D0 +CYREG_B1_UDB04_05_D0 EQU 0x40006a48 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_D0 +CYREG_B1_UDB05_06_D0 EQU 0x40006a4a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_D0 +CYREG_B1_UDB06_07_D0 EQU 0x40006a4c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_D0 +CYREG_B1_UDB07_08_D0 EQU 0x40006a4e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_D0 +CYREG_B1_UDB08_09_D0 EQU 0x40006a50 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_D0 +CYREG_B1_UDB09_10_D0 EQU 0x40006a52 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_D0 +CYREG_B1_UDB10_11_D0 EQU 0x40006a54 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_D0 +CYREG_B1_UDB11_12_D0 EQU 0x40006a56 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_D1 +CYREG_B1_UDB04_05_D1 EQU 0x40006a68 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_D1 +CYREG_B1_UDB05_06_D1 EQU 0x40006a6a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_D1 +CYREG_B1_UDB06_07_D1 EQU 0x40006a6c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_D1 +CYREG_B1_UDB07_08_D1 EQU 0x40006a6e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_D1 +CYREG_B1_UDB08_09_D1 EQU 0x40006a70 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_D1 +CYREG_B1_UDB09_10_D1 EQU 0x40006a72 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_D1 +CYREG_B1_UDB10_11_D1 EQU 0x40006a74 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_D1 +CYREG_B1_UDB11_12_D1 EQU 0x40006a76 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_F0 +CYREG_B1_UDB04_05_F0 EQU 0x40006a88 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_F0 +CYREG_B1_UDB05_06_F0 EQU 0x40006a8a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_F0 +CYREG_B1_UDB06_07_F0 EQU 0x40006a8c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_F0 +CYREG_B1_UDB07_08_F0 EQU 0x40006a8e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_F0 +CYREG_B1_UDB08_09_F0 EQU 0x40006a90 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_F0 +CYREG_B1_UDB09_10_F0 EQU 0x40006a92 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_F0 +CYREG_B1_UDB10_11_F0 EQU 0x40006a94 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_F0 +CYREG_B1_UDB11_12_F0 EQU 0x40006a96 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_F1 +CYREG_B1_UDB04_05_F1 EQU 0x40006aa8 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_F1 +CYREG_B1_UDB05_06_F1 EQU 0x40006aaa + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_F1 +CYREG_B1_UDB06_07_F1 EQU 0x40006aac + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_F1 +CYREG_B1_UDB07_08_F1 EQU 0x40006aae + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_F1 +CYREG_B1_UDB08_09_F1 EQU 0x40006ab0 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_F1 +CYREG_B1_UDB09_10_F1 EQU 0x40006ab2 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_F1 +CYREG_B1_UDB10_11_F1 EQU 0x40006ab4 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_F1 +CYREG_B1_UDB11_12_F1 EQU 0x40006ab6 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_ST +CYREG_B1_UDB04_05_ST EQU 0x40006ac8 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_ST +CYREG_B1_UDB05_06_ST EQU 0x40006aca + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_ST +CYREG_B1_UDB06_07_ST EQU 0x40006acc + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_ST +CYREG_B1_UDB07_08_ST EQU 0x40006ace + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_ST +CYREG_B1_UDB08_09_ST EQU 0x40006ad0 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_ST +CYREG_B1_UDB09_10_ST EQU 0x40006ad2 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_ST +CYREG_B1_UDB10_11_ST EQU 0x40006ad4 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_ST +CYREG_B1_UDB11_12_ST EQU 0x40006ad6 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_CTL +CYREG_B1_UDB04_05_CTL EQU 0x40006ae8 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_CTL +CYREG_B1_UDB05_06_CTL EQU 0x40006aea + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_CTL +CYREG_B1_UDB06_07_CTL EQU 0x40006aec + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_CTL +CYREG_B1_UDB07_08_CTL EQU 0x40006aee + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_CTL +CYREG_B1_UDB08_09_CTL EQU 0x40006af0 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_CTL +CYREG_B1_UDB09_10_CTL EQU 0x40006af2 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_CTL +CYREG_B1_UDB10_11_CTL EQU 0x40006af4 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_CTL +CYREG_B1_UDB11_12_CTL EQU 0x40006af6 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_MSK +CYREG_B1_UDB04_05_MSK EQU 0x40006b08 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_MSK +CYREG_B1_UDB05_06_MSK EQU 0x40006b0a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_MSK +CYREG_B1_UDB06_07_MSK EQU 0x40006b0c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_MSK +CYREG_B1_UDB07_08_MSK EQU 0x40006b0e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_MSK +CYREG_B1_UDB08_09_MSK EQU 0x40006b10 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_MSK +CYREG_B1_UDB09_10_MSK EQU 0x40006b12 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_MSK +CYREG_B1_UDB10_11_MSK EQU 0x40006b14 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_MSK +CYREG_B1_UDB11_12_MSK EQU 0x40006b16 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_ACTL +CYREG_B1_UDB04_05_ACTL EQU 0x40006b28 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_ACTL +CYREG_B1_UDB05_06_ACTL EQU 0x40006b2a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_ACTL +CYREG_B1_UDB06_07_ACTL EQU 0x40006b2c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_ACTL +CYREG_B1_UDB07_08_ACTL EQU 0x40006b2e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_ACTL +CYREG_B1_UDB08_09_ACTL EQU 0x40006b30 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_ACTL +CYREG_B1_UDB09_10_ACTL EQU 0x40006b32 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_ACTL +CYREG_B1_UDB10_11_ACTL EQU 0x40006b34 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_ACTL +CYREG_B1_UDB11_12_ACTL EQU 0x40006b36 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_MC +CYREG_B1_UDB04_05_MC EQU 0x40006b48 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_MC +CYREG_B1_UDB05_06_MC EQU 0x40006b4a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_MC +CYREG_B1_UDB06_07_MC EQU 0x40006b4c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_MC +CYREG_B1_UDB07_08_MC EQU 0x40006b4e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_MC +CYREG_B1_UDB08_09_MC EQU 0x40006b50 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_MC +CYREG_B1_UDB09_10_MC EQU 0x40006b52 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_MC +CYREG_B1_UDB10_11_MC EQU 0x40006b54 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_MC +CYREG_B1_UDB11_12_MC EQU 0x40006b56 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_BASE +CYDEV_PHUB_BASE EQU 0x40007000 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_SIZE +CYDEV_PHUB_SIZE EQU 0x00000c00 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFG +CYREG_PHUB_CFG EQU 0x40007000 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_ERR +CYREG_PHUB_ERR EQU 0x40007004 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_ERR_ADR +CYREG_PHUB_ERR_ADR EQU 0x40007008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_BASE +CYDEV_PHUB_CH0_BASE EQU 0x40007010 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_SIZE +CYDEV_PHUB_CH0_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH0_BASIC_CFG +CYREG_PHUB_CH0_BASIC_CFG EQU 0x40007010 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH0_ACTION +CYREG_PHUB_CH0_ACTION EQU 0x40007014 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH0_BASIC_STATUS +CYREG_PHUB_CH0_BASIC_STATUS EQU 0x40007018 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_BASE +CYDEV_PHUB_CH1_BASE EQU 0x40007020 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_SIZE +CYDEV_PHUB_CH1_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH1_BASIC_CFG +CYREG_PHUB_CH1_BASIC_CFG EQU 0x40007020 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH1_ACTION +CYREG_PHUB_CH1_ACTION EQU 0x40007024 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH1_BASIC_STATUS +CYREG_PHUB_CH1_BASIC_STATUS EQU 0x40007028 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_BASE +CYDEV_PHUB_CH2_BASE EQU 0x40007030 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_SIZE +CYDEV_PHUB_CH2_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH2_BASIC_CFG +CYREG_PHUB_CH2_BASIC_CFG EQU 0x40007030 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH2_ACTION +CYREG_PHUB_CH2_ACTION EQU 0x40007034 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH2_BASIC_STATUS +CYREG_PHUB_CH2_BASIC_STATUS EQU 0x40007038 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_BASE +CYDEV_PHUB_CH3_BASE EQU 0x40007040 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_SIZE +CYDEV_PHUB_CH3_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH3_BASIC_CFG +CYREG_PHUB_CH3_BASIC_CFG EQU 0x40007040 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH3_ACTION +CYREG_PHUB_CH3_ACTION EQU 0x40007044 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH3_BASIC_STATUS +CYREG_PHUB_CH3_BASIC_STATUS EQU 0x40007048 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_BASE +CYDEV_PHUB_CH4_BASE EQU 0x40007050 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_SIZE +CYDEV_PHUB_CH4_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH4_BASIC_CFG +CYREG_PHUB_CH4_BASIC_CFG EQU 0x40007050 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH4_ACTION +CYREG_PHUB_CH4_ACTION EQU 0x40007054 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH4_BASIC_STATUS +CYREG_PHUB_CH4_BASIC_STATUS EQU 0x40007058 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_BASE +CYDEV_PHUB_CH5_BASE EQU 0x40007060 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_SIZE +CYDEV_PHUB_CH5_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH5_BASIC_CFG +CYREG_PHUB_CH5_BASIC_CFG EQU 0x40007060 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH5_ACTION +CYREG_PHUB_CH5_ACTION EQU 0x40007064 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH5_BASIC_STATUS +CYREG_PHUB_CH5_BASIC_STATUS EQU 0x40007068 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_BASE +CYDEV_PHUB_CH6_BASE EQU 0x40007070 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_SIZE +CYDEV_PHUB_CH6_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH6_BASIC_CFG +CYREG_PHUB_CH6_BASIC_CFG EQU 0x40007070 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH6_ACTION +CYREG_PHUB_CH6_ACTION EQU 0x40007074 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH6_BASIC_STATUS +CYREG_PHUB_CH6_BASIC_STATUS EQU 0x40007078 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_BASE +CYDEV_PHUB_CH7_BASE EQU 0x40007080 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_SIZE +CYDEV_PHUB_CH7_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH7_BASIC_CFG +CYREG_PHUB_CH7_BASIC_CFG EQU 0x40007080 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH7_ACTION +CYREG_PHUB_CH7_ACTION EQU 0x40007084 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH7_BASIC_STATUS +CYREG_PHUB_CH7_BASIC_STATUS EQU 0x40007088 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_BASE +CYDEV_PHUB_CH8_BASE EQU 0x40007090 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_SIZE +CYDEV_PHUB_CH8_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH8_BASIC_CFG +CYREG_PHUB_CH8_BASIC_CFG EQU 0x40007090 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH8_ACTION +CYREG_PHUB_CH8_ACTION EQU 0x40007094 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH8_BASIC_STATUS +CYREG_PHUB_CH8_BASIC_STATUS EQU 0x40007098 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_BASE +CYDEV_PHUB_CH9_BASE EQU 0x400070a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_SIZE +CYDEV_PHUB_CH9_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH9_BASIC_CFG +CYREG_PHUB_CH9_BASIC_CFG EQU 0x400070a0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH9_ACTION +CYREG_PHUB_CH9_ACTION EQU 0x400070a4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH9_BASIC_STATUS +CYREG_PHUB_CH9_BASIC_STATUS EQU 0x400070a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_BASE +CYDEV_PHUB_CH10_BASE EQU 0x400070b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_SIZE +CYDEV_PHUB_CH10_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH10_BASIC_CFG +CYREG_PHUB_CH10_BASIC_CFG EQU 0x400070b0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH10_ACTION +CYREG_PHUB_CH10_ACTION EQU 0x400070b4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH10_BASIC_STATUS +CYREG_PHUB_CH10_BASIC_STATUS EQU 0x400070b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_BASE +CYDEV_PHUB_CH11_BASE EQU 0x400070c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_SIZE +CYDEV_PHUB_CH11_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH11_BASIC_CFG +CYREG_PHUB_CH11_BASIC_CFG EQU 0x400070c0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH11_ACTION +CYREG_PHUB_CH11_ACTION EQU 0x400070c4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH11_BASIC_STATUS +CYREG_PHUB_CH11_BASIC_STATUS EQU 0x400070c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_BASE +CYDEV_PHUB_CH12_BASE EQU 0x400070d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_SIZE +CYDEV_PHUB_CH12_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH12_BASIC_CFG +CYREG_PHUB_CH12_BASIC_CFG EQU 0x400070d0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH12_ACTION +CYREG_PHUB_CH12_ACTION EQU 0x400070d4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH12_BASIC_STATUS +CYREG_PHUB_CH12_BASIC_STATUS EQU 0x400070d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_BASE +CYDEV_PHUB_CH13_BASE EQU 0x400070e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_SIZE +CYDEV_PHUB_CH13_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH13_BASIC_CFG +CYREG_PHUB_CH13_BASIC_CFG EQU 0x400070e0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH13_ACTION +CYREG_PHUB_CH13_ACTION EQU 0x400070e4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH13_BASIC_STATUS +CYREG_PHUB_CH13_BASIC_STATUS EQU 0x400070e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_BASE +CYDEV_PHUB_CH14_BASE EQU 0x400070f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_SIZE +CYDEV_PHUB_CH14_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH14_BASIC_CFG +CYREG_PHUB_CH14_BASIC_CFG EQU 0x400070f0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH14_ACTION +CYREG_PHUB_CH14_ACTION EQU 0x400070f4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH14_BASIC_STATUS +CYREG_PHUB_CH14_BASIC_STATUS EQU 0x400070f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_BASE +CYDEV_PHUB_CH15_BASE EQU 0x40007100 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_SIZE +CYDEV_PHUB_CH15_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH15_BASIC_CFG +CYREG_PHUB_CH15_BASIC_CFG EQU 0x40007100 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH15_ACTION +CYREG_PHUB_CH15_ACTION EQU 0x40007104 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH15_BASIC_STATUS +CYREG_PHUB_CH15_BASIC_STATUS EQU 0x40007108 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_BASE +CYDEV_PHUB_CH16_BASE EQU 0x40007110 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_SIZE +CYDEV_PHUB_CH16_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH16_BASIC_CFG +CYREG_PHUB_CH16_BASIC_CFG EQU 0x40007110 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH16_ACTION +CYREG_PHUB_CH16_ACTION EQU 0x40007114 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH16_BASIC_STATUS +CYREG_PHUB_CH16_BASIC_STATUS EQU 0x40007118 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_BASE +CYDEV_PHUB_CH17_BASE EQU 0x40007120 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_SIZE +CYDEV_PHUB_CH17_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH17_BASIC_CFG +CYREG_PHUB_CH17_BASIC_CFG EQU 0x40007120 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH17_ACTION +CYREG_PHUB_CH17_ACTION EQU 0x40007124 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH17_BASIC_STATUS +CYREG_PHUB_CH17_BASIC_STATUS EQU 0x40007128 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_BASE +CYDEV_PHUB_CH18_BASE EQU 0x40007130 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_SIZE +CYDEV_PHUB_CH18_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH18_BASIC_CFG +CYREG_PHUB_CH18_BASIC_CFG EQU 0x40007130 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH18_ACTION +CYREG_PHUB_CH18_ACTION EQU 0x40007134 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH18_BASIC_STATUS +CYREG_PHUB_CH18_BASIC_STATUS EQU 0x40007138 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_BASE +CYDEV_PHUB_CH19_BASE EQU 0x40007140 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_SIZE +CYDEV_PHUB_CH19_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH19_BASIC_CFG +CYREG_PHUB_CH19_BASIC_CFG EQU 0x40007140 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH19_ACTION +CYREG_PHUB_CH19_ACTION EQU 0x40007144 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH19_BASIC_STATUS +CYREG_PHUB_CH19_BASIC_STATUS EQU 0x40007148 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_BASE +CYDEV_PHUB_CH20_BASE EQU 0x40007150 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_SIZE +CYDEV_PHUB_CH20_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH20_BASIC_CFG +CYREG_PHUB_CH20_BASIC_CFG EQU 0x40007150 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH20_ACTION +CYREG_PHUB_CH20_ACTION EQU 0x40007154 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH20_BASIC_STATUS +CYREG_PHUB_CH20_BASIC_STATUS EQU 0x40007158 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_BASE +CYDEV_PHUB_CH21_BASE EQU 0x40007160 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_SIZE +CYDEV_PHUB_CH21_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH21_BASIC_CFG +CYREG_PHUB_CH21_BASIC_CFG EQU 0x40007160 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH21_ACTION +CYREG_PHUB_CH21_ACTION EQU 0x40007164 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH21_BASIC_STATUS +CYREG_PHUB_CH21_BASIC_STATUS EQU 0x40007168 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_BASE +CYDEV_PHUB_CH22_BASE EQU 0x40007170 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_SIZE +CYDEV_PHUB_CH22_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH22_BASIC_CFG +CYREG_PHUB_CH22_BASIC_CFG EQU 0x40007170 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH22_ACTION +CYREG_PHUB_CH22_ACTION EQU 0x40007174 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH22_BASIC_STATUS +CYREG_PHUB_CH22_BASIC_STATUS EQU 0x40007178 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_BASE +CYDEV_PHUB_CH23_BASE EQU 0x40007180 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_SIZE +CYDEV_PHUB_CH23_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH23_BASIC_CFG +CYREG_PHUB_CH23_BASIC_CFG EQU 0x40007180 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH23_ACTION +CYREG_PHUB_CH23_ACTION EQU 0x40007184 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH23_BASIC_STATUS +CYREG_PHUB_CH23_BASIC_STATUS EQU 0x40007188 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_BASE +CYDEV_PHUB_CFGMEM0_BASE EQU 0x40007600 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_SIZE +CYDEV_PHUB_CFGMEM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM0_CFG0 +CYREG_PHUB_CFGMEM0_CFG0 EQU 0x40007600 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM0_CFG1 +CYREG_PHUB_CFGMEM0_CFG1 EQU 0x40007604 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_BASE +CYDEV_PHUB_CFGMEM1_BASE EQU 0x40007608 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_SIZE +CYDEV_PHUB_CFGMEM1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM1_CFG0 +CYREG_PHUB_CFGMEM1_CFG0 EQU 0x40007608 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM1_CFG1 +CYREG_PHUB_CFGMEM1_CFG1 EQU 0x4000760c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_BASE +CYDEV_PHUB_CFGMEM2_BASE EQU 0x40007610 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_SIZE +CYDEV_PHUB_CFGMEM2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM2_CFG0 +CYREG_PHUB_CFGMEM2_CFG0 EQU 0x40007610 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM2_CFG1 +CYREG_PHUB_CFGMEM2_CFG1 EQU 0x40007614 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_BASE +CYDEV_PHUB_CFGMEM3_BASE EQU 0x40007618 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_SIZE +CYDEV_PHUB_CFGMEM3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM3_CFG0 +CYREG_PHUB_CFGMEM3_CFG0 EQU 0x40007618 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM3_CFG1 +CYREG_PHUB_CFGMEM3_CFG1 EQU 0x4000761c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_BASE +CYDEV_PHUB_CFGMEM4_BASE EQU 0x40007620 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_SIZE +CYDEV_PHUB_CFGMEM4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM4_CFG0 +CYREG_PHUB_CFGMEM4_CFG0 EQU 0x40007620 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM4_CFG1 +CYREG_PHUB_CFGMEM4_CFG1 EQU 0x40007624 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_BASE +CYDEV_PHUB_CFGMEM5_BASE EQU 0x40007628 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_SIZE +CYDEV_PHUB_CFGMEM5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM5_CFG0 +CYREG_PHUB_CFGMEM5_CFG0 EQU 0x40007628 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM5_CFG1 +CYREG_PHUB_CFGMEM5_CFG1 EQU 0x4000762c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_BASE +CYDEV_PHUB_CFGMEM6_BASE EQU 0x40007630 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_SIZE +CYDEV_PHUB_CFGMEM6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM6_CFG0 +CYREG_PHUB_CFGMEM6_CFG0 EQU 0x40007630 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM6_CFG1 +CYREG_PHUB_CFGMEM6_CFG1 EQU 0x40007634 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_BASE +CYDEV_PHUB_CFGMEM7_BASE EQU 0x40007638 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_SIZE +CYDEV_PHUB_CFGMEM7_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM7_CFG0 +CYREG_PHUB_CFGMEM7_CFG0 EQU 0x40007638 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM7_CFG1 +CYREG_PHUB_CFGMEM7_CFG1 EQU 0x4000763c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_BASE +CYDEV_PHUB_CFGMEM8_BASE EQU 0x40007640 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_SIZE +CYDEV_PHUB_CFGMEM8_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM8_CFG0 +CYREG_PHUB_CFGMEM8_CFG0 EQU 0x40007640 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM8_CFG1 +CYREG_PHUB_CFGMEM8_CFG1 EQU 0x40007644 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_BASE +CYDEV_PHUB_CFGMEM9_BASE EQU 0x40007648 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_SIZE +CYDEV_PHUB_CFGMEM9_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM9_CFG0 +CYREG_PHUB_CFGMEM9_CFG0 EQU 0x40007648 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM9_CFG1 +CYREG_PHUB_CFGMEM9_CFG1 EQU 0x4000764c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_BASE +CYDEV_PHUB_CFGMEM10_BASE EQU 0x40007650 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_SIZE +CYDEV_PHUB_CFGMEM10_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM10_CFG0 +CYREG_PHUB_CFGMEM10_CFG0 EQU 0x40007650 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM10_CFG1 +CYREG_PHUB_CFGMEM10_CFG1 EQU 0x40007654 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_BASE +CYDEV_PHUB_CFGMEM11_BASE EQU 0x40007658 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_SIZE +CYDEV_PHUB_CFGMEM11_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM11_CFG0 +CYREG_PHUB_CFGMEM11_CFG0 EQU 0x40007658 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM11_CFG1 +CYREG_PHUB_CFGMEM11_CFG1 EQU 0x4000765c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_BASE +CYDEV_PHUB_CFGMEM12_BASE EQU 0x40007660 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_SIZE +CYDEV_PHUB_CFGMEM12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM12_CFG0 +CYREG_PHUB_CFGMEM12_CFG0 EQU 0x40007660 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM12_CFG1 +CYREG_PHUB_CFGMEM12_CFG1 EQU 0x40007664 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_BASE +CYDEV_PHUB_CFGMEM13_BASE EQU 0x40007668 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_SIZE +CYDEV_PHUB_CFGMEM13_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM13_CFG0 +CYREG_PHUB_CFGMEM13_CFG0 EQU 0x40007668 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM13_CFG1 +CYREG_PHUB_CFGMEM13_CFG1 EQU 0x4000766c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_BASE +CYDEV_PHUB_CFGMEM14_BASE EQU 0x40007670 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_SIZE +CYDEV_PHUB_CFGMEM14_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM14_CFG0 +CYREG_PHUB_CFGMEM14_CFG0 EQU 0x40007670 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM14_CFG1 +CYREG_PHUB_CFGMEM14_CFG1 EQU 0x40007674 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_BASE +CYDEV_PHUB_CFGMEM15_BASE EQU 0x40007678 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_SIZE +CYDEV_PHUB_CFGMEM15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM15_CFG0 +CYREG_PHUB_CFGMEM15_CFG0 EQU 0x40007678 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM15_CFG1 +CYREG_PHUB_CFGMEM15_CFG1 EQU 0x4000767c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_BASE +CYDEV_PHUB_CFGMEM16_BASE EQU 0x40007680 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_SIZE +CYDEV_PHUB_CFGMEM16_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM16_CFG0 +CYREG_PHUB_CFGMEM16_CFG0 EQU 0x40007680 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM16_CFG1 +CYREG_PHUB_CFGMEM16_CFG1 EQU 0x40007684 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_BASE +CYDEV_PHUB_CFGMEM17_BASE EQU 0x40007688 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_SIZE +CYDEV_PHUB_CFGMEM17_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM17_CFG0 +CYREG_PHUB_CFGMEM17_CFG0 EQU 0x40007688 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM17_CFG1 +CYREG_PHUB_CFGMEM17_CFG1 EQU 0x4000768c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_BASE +CYDEV_PHUB_CFGMEM18_BASE EQU 0x40007690 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_SIZE +CYDEV_PHUB_CFGMEM18_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM18_CFG0 +CYREG_PHUB_CFGMEM18_CFG0 EQU 0x40007690 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM18_CFG1 +CYREG_PHUB_CFGMEM18_CFG1 EQU 0x40007694 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_BASE +CYDEV_PHUB_CFGMEM19_BASE EQU 0x40007698 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_SIZE +CYDEV_PHUB_CFGMEM19_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM19_CFG0 +CYREG_PHUB_CFGMEM19_CFG0 EQU 0x40007698 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM19_CFG1 +CYREG_PHUB_CFGMEM19_CFG1 EQU 0x4000769c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_BASE +CYDEV_PHUB_CFGMEM20_BASE EQU 0x400076a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_SIZE +CYDEV_PHUB_CFGMEM20_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM20_CFG0 +CYREG_PHUB_CFGMEM20_CFG0 EQU 0x400076a0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM20_CFG1 +CYREG_PHUB_CFGMEM20_CFG1 EQU 0x400076a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_BASE +CYDEV_PHUB_CFGMEM21_BASE EQU 0x400076a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_SIZE +CYDEV_PHUB_CFGMEM21_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM21_CFG0 +CYREG_PHUB_CFGMEM21_CFG0 EQU 0x400076a8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM21_CFG1 +CYREG_PHUB_CFGMEM21_CFG1 EQU 0x400076ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_BASE +CYDEV_PHUB_CFGMEM22_BASE EQU 0x400076b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_SIZE +CYDEV_PHUB_CFGMEM22_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM22_CFG0 +CYREG_PHUB_CFGMEM22_CFG0 EQU 0x400076b0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM22_CFG1 +CYREG_PHUB_CFGMEM22_CFG1 EQU 0x400076b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_BASE +CYDEV_PHUB_CFGMEM23_BASE EQU 0x400076b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_SIZE +CYDEV_PHUB_CFGMEM23_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM23_CFG0 +CYREG_PHUB_CFGMEM23_CFG0 EQU 0x400076b8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM23_CFG1 +CYREG_PHUB_CFGMEM23_CFG1 EQU 0x400076bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_BASE +CYDEV_PHUB_TDMEM0_BASE EQU 0x40007800 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_SIZE +CYDEV_PHUB_TDMEM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM0_ORIG_TD0 +CYREG_PHUB_TDMEM0_ORIG_TD0 EQU 0x40007800 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM0_ORIG_TD1 +CYREG_PHUB_TDMEM0_ORIG_TD1 EQU 0x40007804 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_BASE +CYDEV_PHUB_TDMEM1_BASE EQU 0x40007808 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_SIZE +CYDEV_PHUB_TDMEM1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM1_ORIG_TD0 +CYREG_PHUB_TDMEM1_ORIG_TD0 EQU 0x40007808 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM1_ORIG_TD1 +CYREG_PHUB_TDMEM1_ORIG_TD1 EQU 0x4000780c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_BASE +CYDEV_PHUB_TDMEM2_BASE EQU 0x40007810 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_SIZE +CYDEV_PHUB_TDMEM2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM2_ORIG_TD0 +CYREG_PHUB_TDMEM2_ORIG_TD0 EQU 0x40007810 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM2_ORIG_TD1 +CYREG_PHUB_TDMEM2_ORIG_TD1 EQU 0x40007814 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_BASE +CYDEV_PHUB_TDMEM3_BASE EQU 0x40007818 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_SIZE +CYDEV_PHUB_TDMEM3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM3_ORIG_TD0 +CYREG_PHUB_TDMEM3_ORIG_TD0 EQU 0x40007818 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM3_ORIG_TD1 +CYREG_PHUB_TDMEM3_ORIG_TD1 EQU 0x4000781c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_BASE +CYDEV_PHUB_TDMEM4_BASE EQU 0x40007820 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_SIZE +CYDEV_PHUB_TDMEM4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM4_ORIG_TD0 +CYREG_PHUB_TDMEM4_ORIG_TD0 EQU 0x40007820 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM4_ORIG_TD1 +CYREG_PHUB_TDMEM4_ORIG_TD1 EQU 0x40007824 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_BASE +CYDEV_PHUB_TDMEM5_BASE EQU 0x40007828 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_SIZE +CYDEV_PHUB_TDMEM5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM5_ORIG_TD0 +CYREG_PHUB_TDMEM5_ORIG_TD0 EQU 0x40007828 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM5_ORIG_TD1 +CYREG_PHUB_TDMEM5_ORIG_TD1 EQU 0x4000782c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_BASE +CYDEV_PHUB_TDMEM6_BASE EQU 0x40007830 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_SIZE +CYDEV_PHUB_TDMEM6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM6_ORIG_TD0 +CYREG_PHUB_TDMEM6_ORIG_TD0 EQU 0x40007830 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM6_ORIG_TD1 +CYREG_PHUB_TDMEM6_ORIG_TD1 EQU 0x40007834 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_BASE +CYDEV_PHUB_TDMEM7_BASE EQU 0x40007838 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_SIZE +CYDEV_PHUB_TDMEM7_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM7_ORIG_TD0 +CYREG_PHUB_TDMEM7_ORIG_TD0 EQU 0x40007838 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM7_ORIG_TD1 +CYREG_PHUB_TDMEM7_ORIG_TD1 EQU 0x4000783c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_BASE +CYDEV_PHUB_TDMEM8_BASE EQU 0x40007840 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_SIZE +CYDEV_PHUB_TDMEM8_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM8_ORIG_TD0 +CYREG_PHUB_TDMEM8_ORIG_TD0 EQU 0x40007840 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM8_ORIG_TD1 +CYREG_PHUB_TDMEM8_ORIG_TD1 EQU 0x40007844 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_BASE +CYDEV_PHUB_TDMEM9_BASE EQU 0x40007848 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_SIZE +CYDEV_PHUB_TDMEM9_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM9_ORIG_TD0 +CYREG_PHUB_TDMEM9_ORIG_TD0 EQU 0x40007848 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM9_ORIG_TD1 +CYREG_PHUB_TDMEM9_ORIG_TD1 EQU 0x4000784c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_BASE +CYDEV_PHUB_TDMEM10_BASE EQU 0x40007850 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_SIZE +CYDEV_PHUB_TDMEM10_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM10_ORIG_TD0 +CYREG_PHUB_TDMEM10_ORIG_TD0 EQU 0x40007850 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM10_ORIG_TD1 +CYREG_PHUB_TDMEM10_ORIG_TD1 EQU 0x40007854 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_BASE +CYDEV_PHUB_TDMEM11_BASE EQU 0x40007858 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_SIZE +CYDEV_PHUB_TDMEM11_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM11_ORIG_TD0 +CYREG_PHUB_TDMEM11_ORIG_TD0 EQU 0x40007858 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM11_ORIG_TD1 +CYREG_PHUB_TDMEM11_ORIG_TD1 EQU 0x4000785c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_BASE +CYDEV_PHUB_TDMEM12_BASE EQU 0x40007860 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_SIZE +CYDEV_PHUB_TDMEM12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM12_ORIG_TD0 +CYREG_PHUB_TDMEM12_ORIG_TD0 EQU 0x40007860 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM12_ORIG_TD1 +CYREG_PHUB_TDMEM12_ORIG_TD1 EQU 0x40007864 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_BASE +CYDEV_PHUB_TDMEM13_BASE EQU 0x40007868 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_SIZE +CYDEV_PHUB_TDMEM13_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM13_ORIG_TD0 +CYREG_PHUB_TDMEM13_ORIG_TD0 EQU 0x40007868 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM13_ORIG_TD1 +CYREG_PHUB_TDMEM13_ORIG_TD1 EQU 0x4000786c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_BASE +CYDEV_PHUB_TDMEM14_BASE EQU 0x40007870 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_SIZE +CYDEV_PHUB_TDMEM14_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM14_ORIG_TD0 +CYREG_PHUB_TDMEM14_ORIG_TD0 EQU 0x40007870 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM14_ORIG_TD1 +CYREG_PHUB_TDMEM14_ORIG_TD1 EQU 0x40007874 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_BASE +CYDEV_PHUB_TDMEM15_BASE EQU 0x40007878 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_SIZE +CYDEV_PHUB_TDMEM15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM15_ORIG_TD0 +CYREG_PHUB_TDMEM15_ORIG_TD0 EQU 0x40007878 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM15_ORIG_TD1 +CYREG_PHUB_TDMEM15_ORIG_TD1 EQU 0x4000787c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_BASE +CYDEV_PHUB_TDMEM16_BASE EQU 0x40007880 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_SIZE +CYDEV_PHUB_TDMEM16_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM16_ORIG_TD0 +CYREG_PHUB_TDMEM16_ORIG_TD0 EQU 0x40007880 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM16_ORIG_TD1 +CYREG_PHUB_TDMEM16_ORIG_TD1 EQU 0x40007884 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_BASE +CYDEV_PHUB_TDMEM17_BASE EQU 0x40007888 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_SIZE +CYDEV_PHUB_TDMEM17_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM17_ORIG_TD0 +CYREG_PHUB_TDMEM17_ORIG_TD0 EQU 0x40007888 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM17_ORIG_TD1 +CYREG_PHUB_TDMEM17_ORIG_TD1 EQU 0x4000788c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_BASE +CYDEV_PHUB_TDMEM18_BASE EQU 0x40007890 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_SIZE +CYDEV_PHUB_TDMEM18_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM18_ORIG_TD0 +CYREG_PHUB_TDMEM18_ORIG_TD0 EQU 0x40007890 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM18_ORIG_TD1 +CYREG_PHUB_TDMEM18_ORIG_TD1 EQU 0x40007894 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_BASE +CYDEV_PHUB_TDMEM19_BASE EQU 0x40007898 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_SIZE +CYDEV_PHUB_TDMEM19_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM19_ORIG_TD0 +CYREG_PHUB_TDMEM19_ORIG_TD0 EQU 0x40007898 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM19_ORIG_TD1 +CYREG_PHUB_TDMEM19_ORIG_TD1 EQU 0x4000789c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_BASE +CYDEV_PHUB_TDMEM20_BASE EQU 0x400078a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_SIZE +CYDEV_PHUB_TDMEM20_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM20_ORIG_TD0 +CYREG_PHUB_TDMEM20_ORIG_TD0 EQU 0x400078a0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM20_ORIG_TD1 +CYREG_PHUB_TDMEM20_ORIG_TD1 EQU 0x400078a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_BASE +CYDEV_PHUB_TDMEM21_BASE EQU 0x400078a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_SIZE +CYDEV_PHUB_TDMEM21_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM21_ORIG_TD0 +CYREG_PHUB_TDMEM21_ORIG_TD0 EQU 0x400078a8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM21_ORIG_TD1 +CYREG_PHUB_TDMEM21_ORIG_TD1 EQU 0x400078ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_BASE +CYDEV_PHUB_TDMEM22_BASE EQU 0x400078b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_SIZE +CYDEV_PHUB_TDMEM22_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM22_ORIG_TD0 +CYREG_PHUB_TDMEM22_ORIG_TD0 EQU 0x400078b0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM22_ORIG_TD1 +CYREG_PHUB_TDMEM22_ORIG_TD1 EQU 0x400078b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_BASE +CYDEV_PHUB_TDMEM23_BASE EQU 0x400078b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_SIZE +CYDEV_PHUB_TDMEM23_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM23_ORIG_TD0 +CYREG_PHUB_TDMEM23_ORIG_TD0 EQU 0x400078b8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM23_ORIG_TD1 +CYREG_PHUB_TDMEM23_ORIG_TD1 EQU 0x400078bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_BASE +CYDEV_PHUB_TDMEM24_BASE EQU 0x400078c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_SIZE +CYDEV_PHUB_TDMEM24_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM24_ORIG_TD0 +CYREG_PHUB_TDMEM24_ORIG_TD0 EQU 0x400078c0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM24_ORIG_TD1 +CYREG_PHUB_TDMEM24_ORIG_TD1 EQU 0x400078c4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_BASE +CYDEV_PHUB_TDMEM25_BASE EQU 0x400078c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_SIZE +CYDEV_PHUB_TDMEM25_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM25_ORIG_TD0 +CYREG_PHUB_TDMEM25_ORIG_TD0 EQU 0x400078c8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM25_ORIG_TD1 +CYREG_PHUB_TDMEM25_ORIG_TD1 EQU 0x400078cc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_BASE +CYDEV_PHUB_TDMEM26_BASE EQU 0x400078d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_SIZE +CYDEV_PHUB_TDMEM26_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM26_ORIG_TD0 +CYREG_PHUB_TDMEM26_ORIG_TD0 EQU 0x400078d0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM26_ORIG_TD1 +CYREG_PHUB_TDMEM26_ORIG_TD1 EQU 0x400078d4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_BASE +CYDEV_PHUB_TDMEM27_BASE EQU 0x400078d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_SIZE +CYDEV_PHUB_TDMEM27_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM27_ORIG_TD0 +CYREG_PHUB_TDMEM27_ORIG_TD0 EQU 0x400078d8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM27_ORIG_TD1 +CYREG_PHUB_TDMEM27_ORIG_TD1 EQU 0x400078dc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_BASE +CYDEV_PHUB_TDMEM28_BASE EQU 0x400078e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_SIZE +CYDEV_PHUB_TDMEM28_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM28_ORIG_TD0 +CYREG_PHUB_TDMEM28_ORIG_TD0 EQU 0x400078e0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM28_ORIG_TD1 +CYREG_PHUB_TDMEM28_ORIG_TD1 EQU 0x400078e4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_BASE +CYDEV_PHUB_TDMEM29_BASE EQU 0x400078e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_SIZE +CYDEV_PHUB_TDMEM29_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM29_ORIG_TD0 +CYREG_PHUB_TDMEM29_ORIG_TD0 EQU 0x400078e8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM29_ORIG_TD1 +CYREG_PHUB_TDMEM29_ORIG_TD1 EQU 0x400078ec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_BASE +CYDEV_PHUB_TDMEM30_BASE EQU 0x400078f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_SIZE +CYDEV_PHUB_TDMEM30_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM30_ORIG_TD0 +CYREG_PHUB_TDMEM30_ORIG_TD0 EQU 0x400078f0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM30_ORIG_TD1 +CYREG_PHUB_TDMEM30_ORIG_TD1 EQU 0x400078f4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_BASE +CYDEV_PHUB_TDMEM31_BASE EQU 0x400078f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_SIZE +CYDEV_PHUB_TDMEM31_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM31_ORIG_TD0 +CYREG_PHUB_TDMEM31_ORIG_TD0 EQU 0x400078f8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM31_ORIG_TD1 +CYREG_PHUB_TDMEM31_ORIG_TD1 EQU 0x400078fc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_BASE +CYDEV_PHUB_TDMEM32_BASE EQU 0x40007900 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_SIZE +CYDEV_PHUB_TDMEM32_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM32_ORIG_TD0 +CYREG_PHUB_TDMEM32_ORIG_TD0 EQU 0x40007900 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM32_ORIG_TD1 +CYREG_PHUB_TDMEM32_ORIG_TD1 EQU 0x40007904 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_BASE +CYDEV_PHUB_TDMEM33_BASE EQU 0x40007908 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_SIZE +CYDEV_PHUB_TDMEM33_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM33_ORIG_TD0 +CYREG_PHUB_TDMEM33_ORIG_TD0 EQU 0x40007908 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM33_ORIG_TD1 +CYREG_PHUB_TDMEM33_ORIG_TD1 EQU 0x4000790c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_BASE +CYDEV_PHUB_TDMEM34_BASE EQU 0x40007910 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_SIZE +CYDEV_PHUB_TDMEM34_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM34_ORIG_TD0 +CYREG_PHUB_TDMEM34_ORIG_TD0 EQU 0x40007910 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM34_ORIG_TD1 +CYREG_PHUB_TDMEM34_ORIG_TD1 EQU 0x40007914 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_BASE +CYDEV_PHUB_TDMEM35_BASE EQU 0x40007918 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_SIZE +CYDEV_PHUB_TDMEM35_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM35_ORIG_TD0 +CYREG_PHUB_TDMEM35_ORIG_TD0 EQU 0x40007918 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM35_ORIG_TD1 +CYREG_PHUB_TDMEM35_ORIG_TD1 EQU 0x4000791c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_BASE +CYDEV_PHUB_TDMEM36_BASE EQU 0x40007920 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_SIZE +CYDEV_PHUB_TDMEM36_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM36_ORIG_TD0 +CYREG_PHUB_TDMEM36_ORIG_TD0 EQU 0x40007920 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM36_ORIG_TD1 +CYREG_PHUB_TDMEM36_ORIG_TD1 EQU 0x40007924 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_BASE +CYDEV_PHUB_TDMEM37_BASE EQU 0x40007928 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_SIZE +CYDEV_PHUB_TDMEM37_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM37_ORIG_TD0 +CYREG_PHUB_TDMEM37_ORIG_TD0 EQU 0x40007928 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM37_ORIG_TD1 +CYREG_PHUB_TDMEM37_ORIG_TD1 EQU 0x4000792c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_BASE +CYDEV_PHUB_TDMEM38_BASE EQU 0x40007930 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_SIZE +CYDEV_PHUB_TDMEM38_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM38_ORIG_TD0 +CYREG_PHUB_TDMEM38_ORIG_TD0 EQU 0x40007930 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM38_ORIG_TD1 +CYREG_PHUB_TDMEM38_ORIG_TD1 EQU 0x40007934 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_BASE +CYDEV_PHUB_TDMEM39_BASE EQU 0x40007938 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_SIZE +CYDEV_PHUB_TDMEM39_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM39_ORIG_TD0 +CYREG_PHUB_TDMEM39_ORIG_TD0 EQU 0x40007938 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM39_ORIG_TD1 +CYREG_PHUB_TDMEM39_ORIG_TD1 EQU 0x4000793c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_BASE +CYDEV_PHUB_TDMEM40_BASE EQU 0x40007940 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_SIZE +CYDEV_PHUB_TDMEM40_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM40_ORIG_TD0 +CYREG_PHUB_TDMEM40_ORIG_TD0 EQU 0x40007940 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM40_ORIG_TD1 +CYREG_PHUB_TDMEM40_ORIG_TD1 EQU 0x40007944 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_BASE +CYDEV_PHUB_TDMEM41_BASE EQU 0x40007948 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_SIZE +CYDEV_PHUB_TDMEM41_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM41_ORIG_TD0 +CYREG_PHUB_TDMEM41_ORIG_TD0 EQU 0x40007948 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM41_ORIG_TD1 +CYREG_PHUB_TDMEM41_ORIG_TD1 EQU 0x4000794c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_BASE +CYDEV_PHUB_TDMEM42_BASE EQU 0x40007950 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_SIZE +CYDEV_PHUB_TDMEM42_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM42_ORIG_TD0 +CYREG_PHUB_TDMEM42_ORIG_TD0 EQU 0x40007950 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM42_ORIG_TD1 +CYREG_PHUB_TDMEM42_ORIG_TD1 EQU 0x40007954 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_BASE +CYDEV_PHUB_TDMEM43_BASE EQU 0x40007958 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_SIZE +CYDEV_PHUB_TDMEM43_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM43_ORIG_TD0 +CYREG_PHUB_TDMEM43_ORIG_TD0 EQU 0x40007958 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM43_ORIG_TD1 +CYREG_PHUB_TDMEM43_ORIG_TD1 EQU 0x4000795c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_BASE +CYDEV_PHUB_TDMEM44_BASE EQU 0x40007960 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_SIZE +CYDEV_PHUB_TDMEM44_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM44_ORIG_TD0 +CYREG_PHUB_TDMEM44_ORIG_TD0 EQU 0x40007960 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM44_ORIG_TD1 +CYREG_PHUB_TDMEM44_ORIG_TD1 EQU 0x40007964 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_BASE +CYDEV_PHUB_TDMEM45_BASE EQU 0x40007968 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_SIZE +CYDEV_PHUB_TDMEM45_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM45_ORIG_TD0 +CYREG_PHUB_TDMEM45_ORIG_TD0 EQU 0x40007968 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM45_ORIG_TD1 +CYREG_PHUB_TDMEM45_ORIG_TD1 EQU 0x4000796c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_BASE +CYDEV_PHUB_TDMEM46_BASE EQU 0x40007970 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_SIZE +CYDEV_PHUB_TDMEM46_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM46_ORIG_TD0 +CYREG_PHUB_TDMEM46_ORIG_TD0 EQU 0x40007970 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM46_ORIG_TD1 +CYREG_PHUB_TDMEM46_ORIG_TD1 EQU 0x40007974 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_BASE +CYDEV_PHUB_TDMEM47_BASE EQU 0x40007978 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_SIZE +CYDEV_PHUB_TDMEM47_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM47_ORIG_TD0 +CYREG_PHUB_TDMEM47_ORIG_TD0 EQU 0x40007978 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM47_ORIG_TD1 +CYREG_PHUB_TDMEM47_ORIG_TD1 EQU 0x4000797c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_BASE +CYDEV_PHUB_TDMEM48_BASE EQU 0x40007980 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_SIZE +CYDEV_PHUB_TDMEM48_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM48_ORIG_TD0 +CYREG_PHUB_TDMEM48_ORIG_TD0 EQU 0x40007980 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM48_ORIG_TD1 +CYREG_PHUB_TDMEM48_ORIG_TD1 EQU 0x40007984 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_BASE +CYDEV_PHUB_TDMEM49_BASE EQU 0x40007988 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_SIZE +CYDEV_PHUB_TDMEM49_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM49_ORIG_TD0 +CYREG_PHUB_TDMEM49_ORIG_TD0 EQU 0x40007988 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM49_ORIG_TD1 +CYREG_PHUB_TDMEM49_ORIG_TD1 EQU 0x4000798c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_BASE +CYDEV_PHUB_TDMEM50_BASE EQU 0x40007990 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_SIZE +CYDEV_PHUB_TDMEM50_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM50_ORIG_TD0 +CYREG_PHUB_TDMEM50_ORIG_TD0 EQU 0x40007990 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM50_ORIG_TD1 +CYREG_PHUB_TDMEM50_ORIG_TD1 EQU 0x40007994 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_BASE +CYDEV_PHUB_TDMEM51_BASE EQU 0x40007998 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_SIZE +CYDEV_PHUB_TDMEM51_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM51_ORIG_TD0 +CYREG_PHUB_TDMEM51_ORIG_TD0 EQU 0x40007998 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM51_ORIG_TD1 +CYREG_PHUB_TDMEM51_ORIG_TD1 EQU 0x4000799c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_BASE +CYDEV_PHUB_TDMEM52_BASE EQU 0x400079a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_SIZE +CYDEV_PHUB_TDMEM52_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM52_ORIG_TD0 +CYREG_PHUB_TDMEM52_ORIG_TD0 EQU 0x400079a0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM52_ORIG_TD1 +CYREG_PHUB_TDMEM52_ORIG_TD1 EQU 0x400079a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_BASE +CYDEV_PHUB_TDMEM53_BASE EQU 0x400079a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_SIZE +CYDEV_PHUB_TDMEM53_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM53_ORIG_TD0 +CYREG_PHUB_TDMEM53_ORIG_TD0 EQU 0x400079a8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM53_ORIG_TD1 +CYREG_PHUB_TDMEM53_ORIG_TD1 EQU 0x400079ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_BASE +CYDEV_PHUB_TDMEM54_BASE EQU 0x400079b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_SIZE +CYDEV_PHUB_TDMEM54_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM54_ORIG_TD0 +CYREG_PHUB_TDMEM54_ORIG_TD0 EQU 0x400079b0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM54_ORIG_TD1 +CYREG_PHUB_TDMEM54_ORIG_TD1 EQU 0x400079b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_BASE +CYDEV_PHUB_TDMEM55_BASE EQU 0x400079b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_SIZE +CYDEV_PHUB_TDMEM55_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM55_ORIG_TD0 +CYREG_PHUB_TDMEM55_ORIG_TD0 EQU 0x400079b8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM55_ORIG_TD1 +CYREG_PHUB_TDMEM55_ORIG_TD1 EQU 0x400079bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_BASE +CYDEV_PHUB_TDMEM56_BASE EQU 0x400079c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_SIZE +CYDEV_PHUB_TDMEM56_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM56_ORIG_TD0 +CYREG_PHUB_TDMEM56_ORIG_TD0 EQU 0x400079c0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM56_ORIG_TD1 +CYREG_PHUB_TDMEM56_ORIG_TD1 EQU 0x400079c4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_BASE +CYDEV_PHUB_TDMEM57_BASE EQU 0x400079c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_SIZE +CYDEV_PHUB_TDMEM57_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM57_ORIG_TD0 +CYREG_PHUB_TDMEM57_ORIG_TD0 EQU 0x400079c8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM57_ORIG_TD1 +CYREG_PHUB_TDMEM57_ORIG_TD1 EQU 0x400079cc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_BASE +CYDEV_PHUB_TDMEM58_BASE EQU 0x400079d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_SIZE +CYDEV_PHUB_TDMEM58_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM58_ORIG_TD0 +CYREG_PHUB_TDMEM58_ORIG_TD0 EQU 0x400079d0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM58_ORIG_TD1 +CYREG_PHUB_TDMEM58_ORIG_TD1 EQU 0x400079d4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_BASE +CYDEV_PHUB_TDMEM59_BASE EQU 0x400079d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_SIZE +CYDEV_PHUB_TDMEM59_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM59_ORIG_TD0 +CYREG_PHUB_TDMEM59_ORIG_TD0 EQU 0x400079d8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM59_ORIG_TD1 +CYREG_PHUB_TDMEM59_ORIG_TD1 EQU 0x400079dc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_BASE +CYDEV_PHUB_TDMEM60_BASE EQU 0x400079e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_SIZE +CYDEV_PHUB_TDMEM60_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM60_ORIG_TD0 +CYREG_PHUB_TDMEM60_ORIG_TD0 EQU 0x400079e0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM60_ORIG_TD1 +CYREG_PHUB_TDMEM60_ORIG_TD1 EQU 0x400079e4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_BASE +CYDEV_PHUB_TDMEM61_BASE EQU 0x400079e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_SIZE +CYDEV_PHUB_TDMEM61_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM61_ORIG_TD0 +CYREG_PHUB_TDMEM61_ORIG_TD0 EQU 0x400079e8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM61_ORIG_TD1 +CYREG_PHUB_TDMEM61_ORIG_TD1 EQU 0x400079ec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_BASE +CYDEV_PHUB_TDMEM62_BASE EQU 0x400079f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_SIZE +CYDEV_PHUB_TDMEM62_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM62_ORIG_TD0 +CYREG_PHUB_TDMEM62_ORIG_TD0 EQU 0x400079f0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM62_ORIG_TD1 +CYREG_PHUB_TDMEM62_ORIG_TD1 EQU 0x400079f4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_BASE +CYDEV_PHUB_TDMEM63_BASE EQU 0x400079f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_SIZE +CYDEV_PHUB_TDMEM63_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM63_ORIG_TD0 +CYREG_PHUB_TDMEM63_ORIG_TD0 EQU 0x400079f8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM63_ORIG_TD1 +CYREG_PHUB_TDMEM63_ORIG_TD1 EQU 0x400079fc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_BASE +CYDEV_PHUB_TDMEM64_BASE EQU 0x40007a00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_SIZE +CYDEV_PHUB_TDMEM64_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM64_ORIG_TD0 +CYREG_PHUB_TDMEM64_ORIG_TD0 EQU 0x40007a00 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM64_ORIG_TD1 +CYREG_PHUB_TDMEM64_ORIG_TD1 EQU 0x40007a04 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_BASE +CYDEV_PHUB_TDMEM65_BASE EQU 0x40007a08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_SIZE +CYDEV_PHUB_TDMEM65_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM65_ORIG_TD0 +CYREG_PHUB_TDMEM65_ORIG_TD0 EQU 0x40007a08 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM65_ORIG_TD1 +CYREG_PHUB_TDMEM65_ORIG_TD1 EQU 0x40007a0c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_BASE +CYDEV_PHUB_TDMEM66_BASE EQU 0x40007a10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_SIZE +CYDEV_PHUB_TDMEM66_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM66_ORIG_TD0 +CYREG_PHUB_TDMEM66_ORIG_TD0 EQU 0x40007a10 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM66_ORIG_TD1 +CYREG_PHUB_TDMEM66_ORIG_TD1 EQU 0x40007a14 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_BASE +CYDEV_PHUB_TDMEM67_BASE EQU 0x40007a18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_SIZE +CYDEV_PHUB_TDMEM67_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM67_ORIG_TD0 +CYREG_PHUB_TDMEM67_ORIG_TD0 EQU 0x40007a18 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM67_ORIG_TD1 +CYREG_PHUB_TDMEM67_ORIG_TD1 EQU 0x40007a1c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_BASE +CYDEV_PHUB_TDMEM68_BASE EQU 0x40007a20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_SIZE +CYDEV_PHUB_TDMEM68_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM68_ORIG_TD0 +CYREG_PHUB_TDMEM68_ORIG_TD0 EQU 0x40007a20 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM68_ORIG_TD1 +CYREG_PHUB_TDMEM68_ORIG_TD1 EQU 0x40007a24 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_BASE +CYDEV_PHUB_TDMEM69_BASE EQU 0x40007a28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_SIZE +CYDEV_PHUB_TDMEM69_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM69_ORIG_TD0 +CYREG_PHUB_TDMEM69_ORIG_TD0 EQU 0x40007a28 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM69_ORIG_TD1 +CYREG_PHUB_TDMEM69_ORIG_TD1 EQU 0x40007a2c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_BASE +CYDEV_PHUB_TDMEM70_BASE EQU 0x40007a30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_SIZE +CYDEV_PHUB_TDMEM70_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM70_ORIG_TD0 +CYREG_PHUB_TDMEM70_ORIG_TD0 EQU 0x40007a30 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM70_ORIG_TD1 +CYREG_PHUB_TDMEM70_ORIG_TD1 EQU 0x40007a34 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_BASE +CYDEV_PHUB_TDMEM71_BASE EQU 0x40007a38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_SIZE +CYDEV_PHUB_TDMEM71_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM71_ORIG_TD0 +CYREG_PHUB_TDMEM71_ORIG_TD0 EQU 0x40007a38 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM71_ORIG_TD1 +CYREG_PHUB_TDMEM71_ORIG_TD1 EQU 0x40007a3c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_BASE +CYDEV_PHUB_TDMEM72_BASE EQU 0x40007a40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_SIZE +CYDEV_PHUB_TDMEM72_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM72_ORIG_TD0 +CYREG_PHUB_TDMEM72_ORIG_TD0 EQU 0x40007a40 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM72_ORIG_TD1 +CYREG_PHUB_TDMEM72_ORIG_TD1 EQU 0x40007a44 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_BASE +CYDEV_PHUB_TDMEM73_BASE EQU 0x40007a48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_SIZE +CYDEV_PHUB_TDMEM73_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM73_ORIG_TD0 +CYREG_PHUB_TDMEM73_ORIG_TD0 EQU 0x40007a48 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM73_ORIG_TD1 +CYREG_PHUB_TDMEM73_ORIG_TD1 EQU 0x40007a4c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_BASE +CYDEV_PHUB_TDMEM74_BASE EQU 0x40007a50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_SIZE +CYDEV_PHUB_TDMEM74_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM74_ORIG_TD0 +CYREG_PHUB_TDMEM74_ORIG_TD0 EQU 0x40007a50 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM74_ORIG_TD1 +CYREG_PHUB_TDMEM74_ORIG_TD1 EQU 0x40007a54 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_BASE +CYDEV_PHUB_TDMEM75_BASE EQU 0x40007a58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_SIZE +CYDEV_PHUB_TDMEM75_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM75_ORIG_TD0 +CYREG_PHUB_TDMEM75_ORIG_TD0 EQU 0x40007a58 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM75_ORIG_TD1 +CYREG_PHUB_TDMEM75_ORIG_TD1 EQU 0x40007a5c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_BASE +CYDEV_PHUB_TDMEM76_BASE EQU 0x40007a60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_SIZE +CYDEV_PHUB_TDMEM76_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM76_ORIG_TD0 +CYREG_PHUB_TDMEM76_ORIG_TD0 EQU 0x40007a60 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM76_ORIG_TD1 +CYREG_PHUB_TDMEM76_ORIG_TD1 EQU 0x40007a64 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_BASE +CYDEV_PHUB_TDMEM77_BASE EQU 0x40007a68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_SIZE +CYDEV_PHUB_TDMEM77_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM77_ORIG_TD0 +CYREG_PHUB_TDMEM77_ORIG_TD0 EQU 0x40007a68 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM77_ORIG_TD1 +CYREG_PHUB_TDMEM77_ORIG_TD1 EQU 0x40007a6c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_BASE +CYDEV_PHUB_TDMEM78_BASE EQU 0x40007a70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_SIZE +CYDEV_PHUB_TDMEM78_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM78_ORIG_TD0 +CYREG_PHUB_TDMEM78_ORIG_TD0 EQU 0x40007a70 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM78_ORIG_TD1 +CYREG_PHUB_TDMEM78_ORIG_TD1 EQU 0x40007a74 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_BASE +CYDEV_PHUB_TDMEM79_BASE EQU 0x40007a78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_SIZE +CYDEV_PHUB_TDMEM79_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM79_ORIG_TD0 +CYREG_PHUB_TDMEM79_ORIG_TD0 EQU 0x40007a78 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM79_ORIG_TD1 +CYREG_PHUB_TDMEM79_ORIG_TD1 EQU 0x40007a7c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_BASE +CYDEV_PHUB_TDMEM80_BASE EQU 0x40007a80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_SIZE +CYDEV_PHUB_TDMEM80_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM80_ORIG_TD0 +CYREG_PHUB_TDMEM80_ORIG_TD0 EQU 0x40007a80 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM80_ORIG_TD1 +CYREG_PHUB_TDMEM80_ORIG_TD1 EQU 0x40007a84 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_BASE +CYDEV_PHUB_TDMEM81_BASE EQU 0x40007a88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_SIZE +CYDEV_PHUB_TDMEM81_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM81_ORIG_TD0 +CYREG_PHUB_TDMEM81_ORIG_TD0 EQU 0x40007a88 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM81_ORIG_TD1 +CYREG_PHUB_TDMEM81_ORIG_TD1 EQU 0x40007a8c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_BASE +CYDEV_PHUB_TDMEM82_BASE EQU 0x40007a90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_SIZE +CYDEV_PHUB_TDMEM82_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM82_ORIG_TD0 +CYREG_PHUB_TDMEM82_ORIG_TD0 EQU 0x40007a90 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM82_ORIG_TD1 +CYREG_PHUB_TDMEM82_ORIG_TD1 EQU 0x40007a94 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_BASE +CYDEV_PHUB_TDMEM83_BASE EQU 0x40007a98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_SIZE +CYDEV_PHUB_TDMEM83_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM83_ORIG_TD0 +CYREG_PHUB_TDMEM83_ORIG_TD0 EQU 0x40007a98 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM83_ORIG_TD1 +CYREG_PHUB_TDMEM83_ORIG_TD1 EQU 0x40007a9c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_BASE +CYDEV_PHUB_TDMEM84_BASE EQU 0x40007aa0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_SIZE +CYDEV_PHUB_TDMEM84_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM84_ORIG_TD0 +CYREG_PHUB_TDMEM84_ORIG_TD0 EQU 0x40007aa0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM84_ORIG_TD1 +CYREG_PHUB_TDMEM84_ORIG_TD1 EQU 0x40007aa4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_BASE +CYDEV_PHUB_TDMEM85_BASE EQU 0x40007aa8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_SIZE +CYDEV_PHUB_TDMEM85_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM85_ORIG_TD0 +CYREG_PHUB_TDMEM85_ORIG_TD0 EQU 0x40007aa8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM85_ORIG_TD1 +CYREG_PHUB_TDMEM85_ORIG_TD1 EQU 0x40007aac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_BASE +CYDEV_PHUB_TDMEM86_BASE EQU 0x40007ab0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_SIZE +CYDEV_PHUB_TDMEM86_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM86_ORIG_TD0 +CYREG_PHUB_TDMEM86_ORIG_TD0 EQU 0x40007ab0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM86_ORIG_TD1 +CYREG_PHUB_TDMEM86_ORIG_TD1 EQU 0x40007ab4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_BASE +CYDEV_PHUB_TDMEM87_BASE EQU 0x40007ab8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_SIZE +CYDEV_PHUB_TDMEM87_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM87_ORIG_TD0 +CYREG_PHUB_TDMEM87_ORIG_TD0 EQU 0x40007ab8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM87_ORIG_TD1 +CYREG_PHUB_TDMEM87_ORIG_TD1 EQU 0x40007abc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_BASE +CYDEV_PHUB_TDMEM88_BASE EQU 0x40007ac0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_SIZE +CYDEV_PHUB_TDMEM88_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM88_ORIG_TD0 +CYREG_PHUB_TDMEM88_ORIG_TD0 EQU 0x40007ac0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM88_ORIG_TD1 +CYREG_PHUB_TDMEM88_ORIG_TD1 EQU 0x40007ac4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_BASE +CYDEV_PHUB_TDMEM89_BASE EQU 0x40007ac8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_SIZE +CYDEV_PHUB_TDMEM89_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM89_ORIG_TD0 +CYREG_PHUB_TDMEM89_ORIG_TD0 EQU 0x40007ac8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM89_ORIG_TD1 +CYREG_PHUB_TDMEM89_ORIG_TD1 EQU 0x40007acc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_BASE +CYDEV_PHUB_TDMEM90_BASE EQU 0x40007ad0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_SIZE +CYDEV_PHUB_TDMEM90_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM90_ORIG_TD0 +CYREG_PHUB_TDMEM90_ORIG_TD0 EQU 0x40007ad0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM90_ORIG_TD1 +CYREG_PHUB_TDMEM90_ORIG_TD1 EQU 0x40007ad4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_BASE +CYDEV_PHUB_TDMEM91_BASE EQU 0x40007ad8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_SIZE +CYDEV_PHUB_TDMEM91_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM91_ORIG_TD0 +CYREG_PHUB_TDMEM91_ORIG_TD0 EQU 0x40007ad8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM91_ORIG_TD1 +CYREG_PHUB_TDMEM91_ORIG_TD1 EQU 0x40007adc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_BASE +CYDEV_PHUB_TDMEM92_BASE EQU 0x40007ae0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_SIZE +CYDEV_PHUB_TDMEM92_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM92_ORIG_TD0 +CYREG_PHUB_TDMEM92_ORIG_TD0 EQU 0x40007ae0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM92_ORIG_TD1 +CYREG_PHUB_TDMEM92_ORIG_TD1 EQU 0x40007ae4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_BASE +CYDEV_PHUB_TDMEM93_BASE EQU 0x40007ae8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_SIZE +CYDEV_PHUB_TDMEM93_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM93_ORIG_TD0 +CYREG_PHUB_TDMEM93_ORIG_TD0 EQU 0x40007ae8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM93_ORIG_TD1 +CYREG_PHUB_TDMEM93_ORIG_TD1 EQU 0x40007aec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_BASE +CYDEV_PHUB_TDMEM94_BASE EQU 0x40007af0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_SIZE +CYDEV_PHUB_TDMEM94_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM94_ORIG_TD0 +CYREG_PHUB_TDMEM94_ORIG_TD0 EQU 0x40007af0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM94_ORIG_TD1 +CYREG_PHUB_TDMEM94_ORIG_TD1 EQU 0x40007af4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_BASE +CYDEV_PHUB_TDMEM95_BASE EQU 0x40007af8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_SIZE +CYDEV_PHUB_TDMEM95_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM95_ORIG_TD0 +CYREG_PHUB_TDMEM95_ORIG_TD0 EQU 0x40007af8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM95_ORIG_TD1 +CYREG_PHUB_TDMEM95_ORIG_TD1 EQU 0x40007afc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_BASE +CYDEV_PHUB_TDMEM96_BASE EQU 0x40007b00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_SIZE +CYDEV_PHUB_TDMEM96_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM96_ORIG_TD0 +CYREG_PHUB_TDMEM96_ORIG_TD0 EQU 0x40007b00 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM96_ORIG_TD1 +CYREG_PHUB_TDMEM96_ORIG_TD1 EQU 0x40007b04 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_BASE +CYDEV_PHUB_TDMEM97_BASE EQU 0x40007b08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_SIZE +CYDEV_PHUB_TDMEM97_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM97_ORIG_TD0 +CYREG_PHUB_TDMEM97_ORIG_TD0 EQU 0x40007b08 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM97_ORIG_TD1 +CYREG_PHUB_TDMEM97_ORIG_TD1 EQU 0x40007b0c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_BASE +CYDEV_PHUB_TDMEM98_BASE EQU 0x40007b10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_SIZE +CYDEV_PHUB_TDMEM98_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM98_ORIG_TD0 +CYREG_PHUB_TDMEM98_ORIG_TD0 EQU 0x40007b10 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM98_ORIG_TD1 +CYREG_PHUB_TDMEM98_ORIG_TD1 EQU 0x40007b14 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_BASE +CYDEV_PHUB_TDMEM99_BASE EQU 0x40007b18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_SIZE +CYDEV_PHUB_TDMEM99_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM99_ORIG_TD0 +CYREG_PHUB_TDMEM99_ORIG_TD0 EQU 0x40007b18 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM99_ORIG_TD1 +CYREG_PHUB_TDMEM99_ORIG_TD1 EQU 0x40007b1c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_BASE +CYDEV_PHUB_TDMEM100_BASE EQU 0x40007b20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_SIZE +CYDEV_PHUB_TDMEM100_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM100_ORIG_TD0 +CYREG_PHUB_TDMEM100_ORIG_TD0 EQU 0x40007b20 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM100_ORIG_TD1 +CYREG_PHUB_TDMEM100_ORIG_TD1 EQU 0x40007b24 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_BASE +CYDEV_PHUB_TDMEM101_BASE EQU 0x40007b28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_SIZE +CYDEV_PHUB_TDMEM101_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM101_ORIG_TD0 +CYREG_PHUB_TDMEM101_ORIG_TD0 EQU 0x40007b28 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM101_ORIG_TD1 +CYREG_PHUB_TDMEM101_ORIG_TD1 EQU 0x40007b2c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_BASE +CYDEV_PHUB_TDMEM102_BASE EQU 0x40007b30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_SIZE +CYDEV_PHUB_TDMEM102_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM102_ORIG_TD0 +CYREG_PHUB_TDMEM102_ORIG_TD0 EQU 0x40007b30 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM102_ORIG_TD1 +CYREG_PHUB_TDMEM102_ORIG_TD1 EQU 0x40007b34 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_BASE +CYDEV_PHUB_TDMEM103_BASE EQU 0x40007b38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_SIZE +CYDEV_PHUB_TDMEM103_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM103_ORIG_TD0 +CYREG_PHUB_TDMEM103_ORIG_TD0 EQU 0x40007b38 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM103_ORIG_TD1 +CYREG_PHUB_TDMEM103_ORIG_TD1 EQU 0x40007b3c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_BASE +CYDEV_PHUB_TDMEM104_BASE EQU 0x40007b40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_SIZE +CYDEV_PHUB_TDMEM104_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM104_ORIG_TD0 +CYREG_PHUB_TDMEM104_ORIG_TD0 EQU 0x40007b40 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM104_ORIG_TD1 +CYREG_PHUB_TDMEM104_ORIG_TD1 EQU 0x40007b44 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_BASE +CYDEV_PHUB_TDMEM105_BASE EQU 0x40007b48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_SIZE +CYDEV_PHUB_TDMEM105_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM105_ORIG_TD0 +CYREG_PHUB_TDMEM105_ORIG_TD0 EQU 0x40007b48 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM105_ORIG_TD1 +CYREG_PHUB_TDMEM105_ORIG_TD1 EQU 0x40007b4c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_BASE +CYDEV_PHUB_TDMEM106_BASE EQU 0x40007b50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_SIZE +CYDEV_PHUB_TDMEM106_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM106_ORIG_TD0 +CYREG_PHUB_TDMEM106_ORIG_TD0 EQU 0x40007b50 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM106_ORIG_TD1 +CYREG_PHUB_TDMEM106_ORIG_TD1 EQU 0x40007b54 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_BASE +CYDEV_PHUB_TDMEM107_BASE EQU 0x40007b58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_SIZE +CYDEV_PHUB_TDMEM107_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM107_ORIG_TD0 +CYREG_PHUB_TDMEM107_ORIG_TD0 EQU 0x40007b58 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM107_ORIG_TD1 +CYREG_PHUB_TDMEM107_ORIG_TD1 EQU 0x40007b5c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_BASE +CYDEV_PHUB_TDMEM108_BASE EQU 0x40007b60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_SIZE +CYDEV_PHUB_TDMEM108_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM108_ORIG_TD0 +CYREG_PHUB_TDMEM108_ORIG_TD0 EQU 0x40007b60 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM108_ORIG_TD1 +CYREG_PHUB_TDMEM108_ORIG_TD1 EQU 0x40007b64 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_BASE +CYDEV_PHUB_TDMEM109_BASE EQU 0x40007b68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_SIZE +CYDEV_PHUB_TDMEM109_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM109_ORIG_TD0 +CYREG_PHUB_TDMEM109_ORIG_TD0 EQU 0x40007b68 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM109_ORIG_TD1 +CYREG_PHUB_TDMEM109_ORIG_TD1 EQU 0x40007b6c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_BASE +CYDEV_PHUB_TDMEM110_BASE EQU 0x40007b70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_SIZE +CYDEV_PHUB_TDMEM110_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM110_ORIG_TD0 +CYREG_PHUB_TDMEM110_ORIG_TD0 EQU 0x40007b70 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM110_ORIG_TD1 +CYREG_PHUB_TDMEM110_ORIG_TD1 EQU 0x40007b74 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_BASE +CYDEV_PHUB_TDMEM111_BASE EQU 0x40007b78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_SIZE +CYDEV_PHUB_TDMEM111_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM111_ORIG_TD0 +CYREG_PHUB_TDMEM111_ORIG_TD0 EQU 0x40007b78 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM111_ORIG_TD1 +CYREG_PHUB_TDMEM111_ORIG_TD1 EQU 0x40007b7c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_BASE +CYDEV_PHUB_TDMEM112_BASE EQU 0x40007b80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_SIZE +CYDEV_PHUB_TDMEM112_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM112_ORIG_TD0 +CYREG_PHUB_TDMEM112_ORIG_TD0 EQU 0x40007b80 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM112_ORIG_TD1 +CYREG_PHUB_TDMEM112_ORIG_TD1 EQU 0x40007b84 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_BASE +CYDEV_PHUB_TDMEM113_BASE EQU 0x40007b88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_SIZE +CYDEV_PHUB_TDMEM113_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM113_ORIG_TD0 +CYREG_PHUB_TDMEM113_ORIG_TD0 EQU 0x40007b88 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM113_ORIG_TD1 +CYREG_PHUB_TDMEM113_ORIG_TD1 EQU 0x40007b8c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_BASE +CYDEV_PHUB_TDMEM114_BASE EQU 0x40007b90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_SIZE +CYDEV_PHUB_TDMEM114_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM114_ORIG_TD0 +CYREG_PHUB_TDMEM114_ORIG_TD0 EQU 0x40007b90 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM114_ORIG_TD1 +CYREG_PHUB_TDMEM114_ORIG_TD1 EQU 0x40007b94 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_BASE +CYDEV_PHUB_TDMEM115_BASE EQU 0x40007b98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_SIZE +CYDEV_PHUB_TDMEM115_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM115_ORIG_TD0 +CYREG_PHUB_TDMEM115_ORIG_TD0 EQU 0x40007b98 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM115_ORIG_TD1 +CYREG_PHUB_TDMEM115_ORIG_TD1 EQU 0x40007b9c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_BASE +CYDEV_PHUB_TDMEM116_BASE EQU 0x40007ba0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_SIZE +CYDEV_PHUB_TDMEM116_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM116_ORIG_TD0 +CYREG_PHUB_TDMEM116_ORIG_TD0 EQU 0x40007ba0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM116_ORIG_TD1 +CYREG_PHUB_TDMEM116_ORIG_TD1 EQU 0x40007ba4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_BASE +CYDEV_PHUB_TDMEM117_BASE EQU 0x40007ba8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_SIZE +CYDEV_PHUB_TDMEM117_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM117_ORIG_TD0 +CYREG_PHUB_TDMEM117_ORIG_TD0 EQU 0x40007ba8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM117_ORIG_TD1 +CYREG_PHUB_TDMEM117_ORIG_TD1 EQU 0x40007bac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_BASE +CYDEV_PHUB_TDMEM118_BASE EQU 0x40007bb0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_SIZE +CYDEV_PHUB_TDMEM118_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM118_ORIG_TD0 +CYREG_PHUB_TDMEM118_ORIG_TD0 EQU 0x40007bb0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM118_ORIG_TD1 +CYREG_PHUB_TDMEM118_ORIG_TD1 EQU 0x40007bb4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_BASE +CYDEV_PHUB_TDMEM119_BASE EQU 0x40007bb8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_SIZE +CYDEV_PHUB_TDMEM119_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM119_ORIG_TD0 +CYREG_PHUB_TDMEM119_ORIG_TD0 EQU 0x40007bb8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM119_ORIG_TD1 +CYREG_PHUB_TDMEM119_ORIG_TD1 EQU 0x40007bbc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_BASE +CYDEV_PHUB_TDMEM120_BASE EQU 0x40007bc0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_SIZE +CYDEV_PHUB_TDMEM120_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM120_ORIG_TD0 +CYREG_PHUB_TDMEM120_ORIG_TD0 EQU 0x40007bc0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM120_ORIG_TD1 +CYREG_PHUB_TDMEM120_ORIG_TD1 EQU 0x40007bc4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_BASE +CYDEV_PHUB_TDMEM121_BASE EQU 0x40007bc8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_SIZE +CYDEV_PHUB_TDMEM121_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM121_ORIG_TD0 +CYREG_PHUB_TDMEM121_ORIG_TD0 EQU 0x40007bc8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM121_ORIG_TD1 +CYREG_PHUB_TDMEM121_ORIG_TD1 EQU 0x40007bcc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_BASE +CYDEV_PHUB_TDMEM122_BASE EQU 0x40007bd0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_SIZE +CYDEV_PHUB_TDMEM122_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM122_ORIG_TD0 +CYREG_PHUB_TDMEM122_ORIG_TD0 EQU 0x40007bd0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM122_ORIG_TD1 +CYREG_PHUB_TDMEM122_ORIG_TD1 EQU 0x40007bd4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_BASE +CYDEV_PHUB_TDMEM123_BASE EQU 0x40007bd8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_SIZE +CYDEV_PHUB_TDMEM123_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM123_ORIG_TD0 +CYREG_PHUB_TDMEM123_ORIG_TD0 EQU 0x40007bd8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM123_ORIG_TD1 +CYREG_PHUB_TDMEM123_ORIG_TD1 EQU 0x40007bdc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_BASE +CYDEV_PHUB_TDMEM124_BASE EQU 0x40007be0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_SIZE +CYDEV_PHUB_TDMEM124_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM124_ORIG_TD0 +CYREG_PHUB_TDMEM124_ORIG_TD0 EQU 0x40007be0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM124_ORIG_TD1 +CYREG_PHUB_TDMEM124_ORIG_TD1 EQU 0x40007be4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_BASE +CYDEV_PHUB_TDMEM125_BASE EQU 0x40007be8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_SIZE +CYDEV_PHUB_TDMEM125_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM125_ORIG_TD0 +CYREG_PHUB_TDMEM125_ORIG_TD0 EQU 0x40007be8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM125_ORIG_TD1 +CYREG_PHUB_TDMEM125_ORIG_TD1 EQU 0x40007bec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_BASE +CYDEV_PHUB_TDMEM126_BASE EQU 0x40007bf0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_SIZE +CYDEV_PHUB_TDMEM126_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM126_ORIG_TD0 +CYREG_PHUB_TDMEM126_ORIG_TD0 EQU 0x40007bf0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM126_ORIG_TD1 +CYREG_PHUB_TDMEM126_ORIG_TD1 EQU 0x40007bf4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_BASE +CYDEV_PHUB_TDMEM127_BASE EQU 0x40007bf8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_SIZE +CYDEV_PHUB_TDMEM127_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM127_ORIG_TD0 +CYREG_PHUB_TDMEM127_ORIG_TD0 EQU 0x40007bf8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM127_ORIG_TD1 +CYREG_PHUB_TDMEM127_ORIG_TD1 EQU 0x40007bfc + ENDIF + IF :LNOT::DEF:CYDEV_EE_BASE +CYDEV_EE_BASE EQU 0x40008000 + ENDIF + IF :LNOT::DEF:CYDEV_EE_SIZE +CYDEV_EE_SIZE EQU 0x00000800 + ENDIF + IF :LNOT::DEF:CYREG_EE_DATA_MBASE +CYREG_EE_DATA_MBASE EQU 0x40008000 + ENDIF + IF :LNOT::DEF:CYREG_EE_DATA_MSIZE +CYREG_EE_DATA_MSIZE EQU 0x00000800 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_BASE +CYDEV_CAN0_BASE EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_SIZE +CYDEV_CAN0_SIZE EQU 0x000002a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_BASE +CYDEV_CAN0_CSR_BASE EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_SIZE +CYDEV_CAN0_CSR_SIZE EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_INT_SR +CYREG_CAN0_CSR_INT_SR EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_INT_EN +CYREG_CAN0_CSR_INT_EN EQU 0x4000a004 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_BUF_SR +CYREG_CAN0_CSR_BUF_SR EQU 0x4000a008 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_ERR_SR +CYREG_CAN0_CSR_ERR_SR EQU 0x4000a00c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_CMD +CYREG_CAN0_CSR_CMD EQU 0x4000a010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_CFG +CYREG_CAN0_CSR_CFG EQU 0x4000a014 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_BASE +CYDEV_CAN0_TX0_BASE EQU 0x4000a020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_SIZE +CYDEV_CAN0_TX0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX0_CMD +CYREG_CAN0_TX0_CMD EQU 0x4000a020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX0_ID +CYREG_CAN0_TX0_ID EQU 0x4000a024 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX0_DH +CYREG_CAN0_TX0_DH EQU 0x4000a028 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX0_DL +CYREG_CAN0_TX0_DL EQU 0x4000a02c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_BASE +CYDEV_CAN0_TX1_BASE EQU 0x4000a030 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_SIZE +CYDEV_CAN0_TX1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX1_CMD +CYREG_CAN0_TX1_CMD EQU 0x4000a030 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX1_ID +CYREG_CAN0_TX1_ID EQU 0x4000a034 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX1_DH +CYREG_CAN0_TX1_DH EQU 0x4000a038 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX1_DL +CYREG_CAN0_TX1_DL EQU 0x4000a03c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_BASE +CYDEV_CAN0_TX2_BASE EQU 0x4000a040 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_SIZE +CYDEV_CAN0_TX2_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX2_CMD +CYREG_CAN0_TX2_CMD EQU 0x4000a040 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX2_ID +CYREG_CAN0_TX2_ID EQU 0x4000a044 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX2_DH +CYREG_CAN0_TX2_DH EQU 0x4000a048 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX2_DL +CYREG_CAN0_TX2_DL EQU 0x4000a04c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_BASE +CYDEV_CAN0_TX3_BASE EQU 0x4000a050 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_SIZE +CYDEV_CAN0_TX3_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX3_CMD +CYREG_CAN0_TX3_CMD EQU 0x4000a050 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX3_ID +CYREG_CAN0_TX3_ID EQU 0x4000a054 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX3_DH +CYREG_CAN0_TX3_DH EQU 0x4000a058 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX3_DL +CYREG_CAN0_TX3_DL EQU 0x4000a05c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_BASE +CYDEV_CAN0_TX4_BASE EQU 0x4000a060 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_SIZE +CYDEV_CAN0_TX4_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX4_CMD +CYREG_CAN0_TX4_CMD EQU 0x4000a060 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX4_ID +CYREG_CAN0_TX4_ID EQU 0x4000a064 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX4_DH +CYREG_CAN0_TX4_DH EQU 0x4000a068 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX4_DL +CYREG_CAN0_TX4_DL EQU 0x4000a06c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_BASE +CYDEV_CAN0_TX5_BASE EQU 0x4000a070 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_SIZE +CYDEV_CAN0_TX5_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX5_CMD +CYREG_CAN0_TX5_CMD EQU 0x4000a070 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX5_ID +CYREG_CAN0_TX5_ID EQU 0x4000a074 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX5_DH +CYREG_CAN0_TX5_DH EQU 0x4000a078 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX5_DL +CYREG_CAN0_TX5_DL EQU 0x4000a07c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_BASE +CYDEV_CAN0_TX6_BASE EQU 0x4000a080 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_SIZE +CYDEV_CAN0_TX6_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX6_CMD +CYREG_CAN0_TX6_CMD EQU 0x4000a080 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX6_ID +CYREG_CAN0_TX6_ID EQU 0x4000a084 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX6_DH +CYREG_CAN0_TX6_DH EQU 0x4000a088 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX6_DL +CYREG_CAN0_TX6_DL EQU 0x4000a08c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_BASE +CYDEV_CAN0_TX7_BASE EQU 0x4000a090 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_SIZE +CYDEV_CAN0_TX7_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX7_CMD +CYREG_CAN0_TX7_CMD EQU 0x4000a090 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX7_ID +CYREG_CAN0_TX7_ID EQU 0x4000a094 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX7_DH +CYREG_CAN0_TX7_DH EQU 0x4000a098 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX7_DL +CYREG_CAN0_TX7_DL EQU 0x4000a09c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_BASE +CYDEV_CAN0_RX0_BASE EQU 0x4000a0a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_SIZE +CYDEV_CAN0_RX0_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_CMD +CYREG_CAN0_RX0_CMD EQU 0x4000a0a0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_ID +CYREG_CAN0_RX0_ID EQU 0x4000a0a4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_DH +CYREG_CAN0_RX0_DH EQU 0x4000a0a8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_DL +CYREG_CAN0_RX0_DL EQU 0x4000a0ac + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_AMR +CYREG_CAN0_RX0_AMR EQU 0x4000a0b0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_ACR +CYREG_CAN0_RX0_ACR EQU 0x4000a0b4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_AMRD +CYREG_CAN0_RX0_AMRD EQU 0x4000a0b8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_ACRD +CYREG_CAN0_RX0_ACRD EQU 0x4000a0bc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_BASE +CYDEV_CAN0_RX1_BASE EQU 0x4000a0c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_SIZE +CYDEV_CAN0_RX1_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_CMD +CYREG_CAN0_RX1_CMD EQU 0x4000a0c0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_ID +CYREG_CAN0_RX1_ID EQU 0x4000a0c4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_DH +CYREG_CAN0_RX1_DH EQU 0x4000a0c8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_DL +CYREG_CAN0_RX1_DL EQU 0x4000a0cc + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_AMR +CYREG_CAN0_RX1_AMR EQU 0x4000a0d0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_ACR +CYREG_CAN0_RX1_ACR EQU 0x4000a0d4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_AMRD +CYREG_CAN0_RX1_AMRD EQU 0x4000a0d8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_ACRD +CYREG_CAN0_RX1_ACRD EQU 0x4000a0dc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_BASE +CYDEV_CAN0_RX2_BASE EQU 0x4000a0e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_SIZE +CYDEV_CAN0_RX2_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_CMD +CYREG_CAN0_RX2_CMD EQU 0x4000a0e0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_ID +CYREG_CAN0_RX2_ID EQU 0x4000a0e4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_DH +CYREG_CAN0_RX2_DH EQU 0x4000a0e8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_DL +CYREG_CAN0_RX2_DL EQU 0x4000a0ec + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_AMR +CYREG_CAN0_RX2_AMR EQU 0x4000a0f0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_ACR +CYREG_CAN0_RX2_ACR EQU 0x4000a0f4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_AMRD +CYREG_CAN0_RX2_AMRD EQU 0x4000a0f8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_ACRD +CYREG_CAN0_RX2_ACRD EQU 0x4000a0fc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_BASE +CYDEV_CAN0_RX3_BASE EQU 0x4000a100 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_SIZE +CYDEV_CAN0_RX3_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_CMD +CYREG_CAN0_RX3_CMD EQU 0x4000a100 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_ID +CYREG_CAN0_RX3_ID EQU 0x4000a104 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_DH +CYREG_CAN0_RX3_DH EQU 0x4000a108 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_DL +CYREG_CAN0_RX3_DL EQU 0x4000a10c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_AMR +CYREG_CAN0_RX3_AMR EQU 0x4000a110 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_ACR +CYREG_CAN0_RX3_ACR EQU 0x4000a114 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_AMRD +CYREG_CAN0_RX3_AMRD EQU 0x4000a118 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_ACRD +CYREG_CAN0_RX3_ACRD EQU 0x4000a11c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_BASE +CYDEV_CAN0_RX4_BASE EQU 0x4000a120 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_SIZE +CYDEV_CAN0_RX4_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_CMD +CYREG_CAN0_RX4_CMD EQU 0x4000a120 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_ID +CYREG_CAN0_RX4_ID EQU 0x4000a124 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_DH +CYREG_CAN0_RX4_DH EQU 0x4000a128 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_DL +CYREG_CAN0_RX4_DL EQU 0x4000a12c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_AMR +CYREG_CAN0_RX4_AMR EQU 0x4000a130 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_ACR +CYREG_CAN0_RX4_ACR EQU 0x4000a134 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_AMRD +CYREG_CAN0_RX4_AMRD EQU 0x4000a138 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_ACRD +CYREG_CAN0_RX4_ACRD EQU 0x4000a13c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_BASE +CYDEV_CAN0_RX5_BASE EQU 0x4000a140 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_SIZE +CYDEV_CAN0_RX5_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_CMD +CYREG_CAN0_RX5_CMD EQU 0x4000a140 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_ID +CYREG_CAN0_RX5_ID EQU 0x4000a144 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_DH +CYREG_CAN0_RX5_DH EQU 0x4000a148 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_DL +CYREG_CAN0_RX5_DL EQU 0x4000a14c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_AMR +CYREG_CAN0_RX5_AMR EQU 0x4000a150 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_ACR +CYREG_CAN0_RX5_ACR EQU 0x4000a154 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_AMRD +CYREG_CAN0_RX5_AMRD EQU 0x4000a158 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_ACRD +CYREG_CAN0_RX5_ACRD EQU 0x4000a15c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_BASE +CYDEV_CAN0_RX6_BASE EQU 0x4000a160 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_SIZE +CYDEV_CAN0_RX6_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_CMD +CYREG_CAN0_RX6_CMD EQU 0x4000a160 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_ID +CYREG_CAN0_RX6_ID EQU 0x4000a164 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_DH +CYREG_CAN0_RX6_DH EQU 0x4000a168 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_DL +CYREG_CAN0_RX6_DL EQU 0x4000a16c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_AMR +CYREG_CAN0_RX6_AMR EQU 0x4000a170 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_ACR +CYREG_CAN0_RX6_ACR EQU 0x4000a174 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_AMRD +CYREG_CAN0_RX6_AMRD EQU 0x4000a178 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_ACRD +CYREG_CAN0_RX6_ACRD EQU 0x4000a17c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_BASE +CYDEV_CAN0_RX7_BASE EQU 0x4000a180 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_SIZE +CYDEV_CAN0_RX7_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_CMD +CYREG_CAN0_RX7_CMD EQU 0x4000a180 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_ID +CYREG_CAN0_RX7_ID EQU 0x4000a184 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_DH +CYREG_CAN0_RX7_DH EQU 0x4000a188 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_DL +CYREG_CAN0_RX7_DL EQU 0x4000a18c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_AMR +CYREG_CAN0_RX7_AMR EQU 0x4000a190 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_ACR +CYREG_CAN0_RX7_ACR EQU 0x4000a194 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_AMRD +CYREG_CAN0_RX7_AMRD EQU 0x4000a198 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_ACRD +CYREG_CAN0_RX7_ACRD EQU 0x4000a19c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_BASE +CYDEV_CAN0_RX8_BASE EQU 0x4000a1a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_SIZE +CYDEV_CAN0_RX8_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_CMD +CYREG_CAN0_RX8_CMD EQU 0x4000a1a0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_ID +CYREG_CAN0_RX8_ID EQU 0x4000a1a4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_DH +CYREG_CAN0_RX8_DH EQU 0x4000a1a8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_DL +CYREG_CAN0_RX8_DL EQU 0x4000a1ac + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_AMR +CYREG_CAN0_RX8_AMR EQU 0x4000a1b0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_ACR +CYREG_CAN0_RX8_ACR EQU 0x4000a1b4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_AMRD +CYREG_CAN0_RX8_AMRD EQU 0x4000a1b8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_ACRD +CYREG_CAN0_RX8_ACRD EQU 0x4000a1bc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_BASE +CYDEV_CAN0_RX9_BASE EQU 0x4000a1c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_SIZE +CYDEV_CAN0_RX9_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_CMD +CYREG_CAN0_RX9_CMD EQU 0x4000a1c0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_ID +CYREG_CAN0_RX9_ID EQU 0x4000a1c4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_DH +CYREG_CAN0_RX9_DH EQU 0x4000a1c8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_DL +CYREG_CAN0_RX9_DL EQU 0x4000a1cc + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_AMR +CYREG_CAN0_RX9_AMR EQU 0x4000a1d0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_ACR +CYREG_CAN0_RX9_ACR EQU 0x4000a1d4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_AMRD +CYREG_CAN0_RX9_AMRD EQU 0x4000a1d8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_ACRD +CYREG_CAN0_RX9_ACRD EQU 0x4000a1dc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_BASE +CYDEV_CAN0_RX10_BASE EQU 0x4000a1e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_SIZE +CYDEV_CAN0_RX10_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_CMD +CYREG_CAN0_RX10_CMD EQU 0x4000a1e0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_ID +CYREG_CAN0_RX10_ID EQU 0x4000a1e4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_DH +CYREG_CAN0_RX10_DH EQU 0x4000a1e8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_DL +CYREG_CAN0_RX10_DL EQU 0x4000a1ec + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_AMR +CYREG_CAN0_RX10_AMR EQU 0x4000a1f0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_ACR +CYREG_CAN0_RX10_ACR EQU 0x4000a1f4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_AMRD +CYREG_CAN0_RX10_AMRD EQU 0x4000a1f8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_ACRD +CYREG_CAN0_RX10_ACRD EQU 0x4000a1fc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_BASE +CYDEV_CAN0_RX11_BASE EQU 0x4000a200 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_SIZE +CYDEV_CAN0_RX11_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_CMD +CYREG_CAN0_RX11_CMD EQU 0x4000a200 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_ID +CYREG_CAN0_RX11_ID EQU 0x4000a204 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_DH +CYREG_CAN0_RX11_DH EQU 0x4000a208 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_DL +CYREG_CAN0_RX11_DL EQU 0x4000a20c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_AMR +CYREG_CAN0_RX11_AMR EQU 0x4000a210 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_ACR +CYREG_CAN0_RX11_ACR EQU 0x4000a214 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_AMRD +CYREG_CAN0_RX11_AMRD EQU 0x4000a218 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_ACRD +CYREG_CAN0_RX11_ACRD EQU 0x4000a21c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_BASE +CYDEV_CAN0_RX12_BASE EQU 0x4000a220 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_SIZE +CYDEV_CAN0_RX12_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_CMD +CYREG_CAN0_RX12_CMD EQU 0x4000a220 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_ID +CYREG_CAN0_RX12_ID EQU 0x4000a224 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_DH +CYREG_CAN0_RX12_DH EQU 0x4000a228 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_DL +CYREG_CAN0_RX12_DL EQU 0x4000a22c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_AMR +CYREG_CAN0_RX12_AMR EQU 0x4000a230 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_ACR +CYREG_CAN0_RX12_ACR EQU 0x4000a234 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_AMRD +CYREG_CAN0_RX12_AMRD EQU 0x4000a238 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_ACRD +CYREG_CAN0_RX12_ACRD EQU 0x4000a23c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_BASE +CYDEV_CAN0_RX13_BASE EQU 0x4000a240 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_SIZE +CYDEV_CAN0_RX13_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_CMD +CYREG_CAN0_RX13_CMD EQU 0x4000a240 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_ID +CYREG_CAN0_RX13_ID EQU 0x4000a244 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_DH +CYREG_CAN0_RX13_DH EQU 0x4000a248 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_DL +CYREG_CAN0_RX13_DL EQU 0x4000a24c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_AMR +CYREG_CAN0_RX13_AMR EQU 0x4000a250 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_ACR +CYREG_CAN0_RX13_ACR EQU 0x4000a254 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_AMRD +CYREG_CAN0_RX13_AMRD EQU 0x4000a258 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_ACRD +CYREG_CAN0_RX13_ACRD EQU 0x4000a25c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_BASE +CYDEV_CAN0_RX14_BASE EQU 0x4000a260 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_SIZE +CYDEV_CAN0_RX14_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_CMD +CYREG_CAN0_RX14_CMD EQU 0x4000a260 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_ID +CYREG_CAN0_RX14_ID EQU 0x4000a264 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_DH +CYREG_CAN0_RX14_DH EQU 0x4000a268 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_DL +CYREG_CAN0_RX14_DL EQU 0x4000a26c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_AMR +CYREG_CAN0_RX14_AMR EQU 0x4000a270 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_ACR +CYREG_CAN0_RX14_ACR EQU 0x4000a274 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_AMRD +CYREG_CAN0_RX14_AMRD EQU 0x4000a278 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_ACRD +CYREG_CAN0_RX14_ACRD EQU 0x4000a27c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_BASE +CYDEV_CAN0_RX15_BASE EQU 0x4000a280 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_SIZE +CYDEV_CAN0_RX15_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_CMD +CYREG_CAN0_RX15_CMD EQU 0x4000a280 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_ID +CYREG_CAN0_RX15_ID EQU 0x4000a284 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_DH +CYREG_CAN0_RX15_DH EQU 0x4000a288 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_DL +CYREG_CAN0_RX15_DL EQU 0x4000a28c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_AMR +CYREG_CAN0_RX15_AMR EQU 0x4000a290 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_ACR +CYREG_CAN0_RX15_ACR EQU 0x4000a294 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_AMRD +CYREG_CAN0_RX15_AMRD EQU 0x4000a298 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_ACRD +CYREG_CAN0_RX15_ACRD EQU 0x4000a29c + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_BASE +CYDEV_DFB0_BASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_SIZE +CYDEV_DFB0_SIZE EQU 0x000007b5 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_BASE +CYDEV_DFB0_DPA_SRAM_BASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_SIZE +CYDEV_DFB0_DPA_SRAM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DPA_SRAM_DATA_MBASE +CYREG_DFB0_DPA_SRAM_DATA_MBASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DPA_SRAM_DATA_MSIZE +CYREG_DFB0_DPA_SRAM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_BASE +CYDEV_DFB0_DPB_SRAM_BASE EQU 0x4000c200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_SIZE +CYDEV_DFB0_DPB_SRAM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DPB_SRAM_DATA_MBASE +CYREG_DFB0_DPB_SRAM_DATA_MBASE EQU 0x4000c200 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DPB_SRAM_DATA_MSIZE +CYREG_DFB0_DPB_SRAM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_BASE +CYDEV_DFB0_CSA_SRAM_BASE EQU 0x4000c400 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_SIZE +CYDEV_DFB0_CSA_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_CSA_SRAM_DATA_MBASE +CYREG_DFB0_CSA_SRAM_DATA_MBASE EQU 0x4000c400 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_CSA_SRAM_DATA_MSIZE +CYREG_DFB0_CSA_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_BASE +CYDEV_DFB0_CSB_SRAM_BASE EQU 0x4000c500 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_SIZE +CYDEV_DFB0_CSB_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_CSB_SRAM_DATA_MBASE +CYREG_DFB0_CSB_SRAM_DATA_MBASE EQU 0x4000c500 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_CSB_SRAM_DATA_MSIZE +CYREG_DFB0_CSB_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_BASE +CYDEV_DFB0_FSM_SRAM_BASE EQU 0x4000c600 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_SIZE +CYDEV_DFB0_FSM_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_FSM_SRAM_DATA_MBASE +CYREG_DFB0_FSM_SRAM_DATA_MBASE EQU 0x4000c600 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_FSM_SRAM_DATA_MSIZE +CYREG_DFB0_FSM_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_BASE +CYDEV_DFB0_ACU_SRAM_BASE EQU 0x4000c700 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_SIZE +CYDEV_DFB0_ACU_SRAM_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_ACU_SRAM_DATA_MBASE +CYREG_DFB0_ACU_SRAM_DATA_MBASE EQU 0x4000c700 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_ACU_SRAM_DATA_MSIZE +CYREG_DFB0_ACU_SRAM_DATA_MSIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_CR +CYREG_DFB0_CR EQU 0x4000c780 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_SR +CYREG_DFB0_SR EQU 0x4000c784 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_RAM_EN +CYREG_DFB0_RAM_EN EQU 0x4000c788 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_RAM_DIR +CYREG_DFB0_RAM_DIR EQU 0x4000c78c + ENDIF + IF :LNOT::DEF:CYREG_DFB0_SEMA +CYREG_DFB0_SEMA EQU 0x4000c790 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DSI_CTRL +CYREG_DFB0_DSI_CTRL EQU 0x4000c794 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_INT_CTRL +CYREG_DFB0_INT_CTRL EQU 0x4000c798 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DMA_CTRL +CYREG_DFB0_DMA_CTRL EQU 0x4000c79c + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEA +CYREG_DFB0_STAGEA EQU 0x4000c7a0 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEAM +CYREG_DFB0_STAGEAM EQU 0x4000c7a1 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEAH +CYREG_DFB0_STAGEAH EQU 0x4000c7a2 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEB +CYREG_DFB0_STAGEB EQU 0x4000c7a4 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEBM +CYREG_DFB0_STAGEBM EQU 0x4000c7a5 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEBH +CYREG_DFB0_STAGEBH EQU 0x4000c7a6 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDA +CYREG_DFB0_HOLDA EQU 0x4000c7a8 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDAM +CYREG_DFB0_HOLDAM EQU 0x4000c7a9 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDAH +CYREG_DFB0_HOLDAH EQU 0x4000c7aa + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDAS +CYREG_DFB0_HOLDAS EQU 0x4000c7ab + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDB +CYREG_DFB0_HOLDB EQU 0x4000c7ac + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDBM +CYREG_DFB0_HOLDBM EQU 0x4000c7ad + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDBH +CYREG_DFB0_HOLDBH EQU 0x4000c7ae + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDBS +CYREG_DFB0_HOLDBS EQU 0x4000c7af + ENDIF + IF :LNOT::DEF:CYREG_DFB0_COHER +CYREG_DFB0_COHER EQU 0x4000c7b0 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DALIGN +CYREG_DFB0_DALIGN EQU 0x4000c7b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BASE +CYDEV_UCFG_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_SIZE +CYDEV_UCFG_SIZE EQU 0x00005040 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_BASE +CYDEV_UCFG_B0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_SIZE +CYDEV_UCFG_B0_SIZE EQU 0x00000fef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_BASE +CYDEV_UCFG_B0_P0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_SIZE +CYDEV_UCFG_B0_P0_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_BASE +CYDEV_UCFG_B0_P0_U0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_SIZE +CYDEV_UCFG_B0_P0_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT0 +CYREG_B0_P0_U0_PLD_IT0 EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT1 +CYREG_B0_P0_U0_PLD_IT1 EQU 0x40010004 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT2 +CYREG_B0_P0_U0_PLD_IT2 EQU 0x40010008 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT3 +CYREG_B0_P0_U0_PLD_IT3 EQU 0x4001000c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT4 +CYREG_B0_P0_U0_PLD_IT4 EQU 0x40010010 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT5 +CYREG_B0_P0_U0_PLD_IT5 EQU 0x40010014 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT6 +CYREG_B0_P0_U0_PLD_IT6 EQU 0x40010018 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT7 +CYREG_B0_P0_U0_PLD_IT7 EQU 0x4001001c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT8 +CYREG_B0_P0_U0_PLD_IT8 EQU 0x40010020 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT9 +CYREG_B0_P0_U0_PLD_IT9 EQU 0x40010024 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT10 +CYREG_B0_P0_U0_PLD_IT10 EQU 0x40010028 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT11 +CYREG_B0_P0_U0_PLD_IT11 EQU 0x4001002c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_ORT0 +CYREG_B0_P0_U0_PLD_ORT0 EQU 0x40010030 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_ORT1 +CYREG_B0_P0_U0_PLD_ORT1 EQU 0x40010032 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_ORT2 +CYREG_B0_P0_U0_PLD_ORT2 EQU 0x40010034 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_ORT3 +CYREG_B0_P0_U0_PLD_ORT3 EQU 0x40010036 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_MC_CFG_CEN_CONST +CYREG_B0_P0_U0_MC_CFG_CEN_CONST EQU 0x40010038 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_MC_CFG_XORFB +CYREG_B0_P0_U0_MC_CFG_XORFB EQU 0x4001003a + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_MC_CFG_SET_RESET +CYREG_B0_P0_U0_MC_CFG_SET_RESET EQU 0x4001003c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_MC_CFG_BYPASS +CYREG_B0_P0_U0_MC_CFG_BYPASS EQU 0x4001003e + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG0 +CYREG_B0_P0_U0_CFG0 EQU 0x40010040 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG1 +CYREG_B0_P0_U0_CFG1 EQU 0x40010041 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG2 +CYREG_B0_P0_U0_CFG2 EQU 0x40010042 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG3 +CYREG_B0_P0_U0_CFG3 EQU 0x40010043 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG4 +CYREG_B0_P0_U0_CFG4 EQU 0x40010044 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG5 +CYREG_B0_P0_U0_CFG5 EQU 0x40010045 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG6 +CYREG_B0_P0_U0_CFG6 EQU 0x40010046 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG7 +CYREG_B0_P0_U0_CFG7 EQU 0x40010047 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG8 +CYREG_B0_P0_U0_CFG8 EQU 0x40010048 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG9 +CYREG_B0_P0_U0_CFG9 EQU 0x40010049 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG10 +CYREG_B0_P0_U0_CFG10 EQU 0x4001004a + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG11 +CYREG_B0_P0_U0_CFG11 EQU 0x4001004b + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG12 +CYREG_B0_P0_U0_CFG12 EQU 0x4001004c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG13 +CYREG_B0_P0_U0_CFG13 EQU 0x4001004d + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG14 +CYREG_B0_P0_U0_CFG14 EQU 0x4001004e + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG15 +CYREG_B0_P0_U0_CFG15 EQU 0x4001004f + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG16 +CYREG_B0_P0_U0_CFG16 EQU 0x40010050 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG17 +CYREG_B0_P0_U0_CFG17 EQU 0x40010051 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG18 +CYREG_B0_P0_U0_CFG18 EQU 0x40010052 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG19 +CYREG_B0_P0_U0_CFG19 EQU 0x40010053 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG20 +CYREG_B0_P0_U0_CFG20 EQU 0x40010054 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG21 +CYREG_B0_P0_U0_CFG21 EQU 0x40010055 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG22 +CYREG_B0_P0_U0_CFG22 EQU 0x40010056 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG23 +CYREG_B0_P0_U0_CFG23 EQU 0x40010057 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG24 +CYREG_B0_P0_U0_CFG24 EQU 0x40010058 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG25 +CYREG_B0_P0_U0_CFG25 EQU 0x40010059 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG26 +CYREG_B0_P0_U0_CFG26 EQU 0x4001005a + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG27 +CYREG_B0_P0_U0_CFG27 EQU 0x4001005b + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG28 +CYREG_B0_P0_U0_CFG28 EQU 0x4001005c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG29 +CYREG_B0_P0_U0_CFG29 EQU 0x4001005d + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG30 +CYREG_B0_P0_U0_CFG30 EQU 0x4001005e + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG31 +CYREG_B0_P0_U0_CFG31 EQU 0x4001005f + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG0 +CYREG_B0_P0_U0_DCFG0 EQU 0x40010060 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG1 +CYREG_B0_P0_U0_DCFG1 EQU 0x40010062 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG2 +CYREG_B0_P0_U0_DCFG2 EQU 0x40010064 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG3 +CYREG_B0_P0_U0_DCFG3 EQU 0x40010066 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG4 +CYREG_B0_P0_U0_DCFG4 EQU 0x40010068 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG5 +CYREG_B0_P0_U0_DCFG5 EQU 0x4001006a + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG6 +CYREG_B0_P0_U0_DCFG6 EQU 0x4001006c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG7 +CYREG_B0_P0_U0_DCFG7 EQU 0x4001006e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_BASE +CYDEV_UCFG_B0_P0_U1_BASE EQU 0x40010080 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_SIZE +CYDEV_UCFG_B0_P0_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT0 +CYREG_B0_P0_U1_PLD_IT0 EQU 0x40010080 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT1 +CYREG_B0_P0_U1_PLD_IT1 EQU 0x40010084 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT2 +CYREG_B0_P0_U1_PLD_IT2 EQU 0x40010088 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT3 +CYREG_B0_P0_U1_PLD_IT3 EQU 0x4001008c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT4 +CYREG_B0_P0_U1_PLD_IT4 EQU 0x40010090 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT5 +CYREG_B0_P0_U1_PLD_IT5 EQU 0x40010094 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT6 +CYREG_B0_P0_U1_PLD_IT6 EQU 0x40010098 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT7 +CYREG_B0_P0_U1_PLD_IT7 EQU 0x4001009c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT8 +CYREG_B0_P0_U1_PLD_IT8 EQU 0x400100a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT9 +CYREG_B0_P0_U1_PLD_IT9 EQU 0x400100a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT10 +CYREG_B0_P0_U1_PLD_IT10 EQU 0x400100a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT11 +CYREG_B0_P0_U1_PLD_IT11 EQU 0x400100ac + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_ORT0 +CYREG_B0_P0_U1_PLD_ORT0 EQU 0x400100b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_ORT1 +CYREG_B0_P0_U1_PLD_ORT1 EQU 0x400100b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_ORT2 +CYREG_B0_P0_U1_PLD_ORT2 EQU 0x400100b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_ORT3 +CYREG_B0_P0_U1_PLD_ORT3 EQU 0x400100b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_MC_CFG_CEN_CONST +CYREG_B0_P0_U1_MC_CFG_CEN_CONST EQU 0x400100b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_MC_CFG_XORFB +CYREG_B0_P0_U1_MC_CFG_XORFB EQU 0x400100ba + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_MC_CFG_SET_RESET +CYREG_B0_P0_U1_MC_CFG_SET_RESET EQU 0x400100bc + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_MC_CFG_BYPASS +CYREG_B0_P0_U1_MC_CFG_BYPASS EQU 0x400100be + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG0 +CYREG_B0_P0_U1_CFG0 EQU 0x400100c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG1 +CYREG_B0_P0_U1_CFG1 EQU 0x400100c1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG2 +CYREG_B0_P0_U1_CFG2 EQU 0x400100c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG3 +CYREG_B0_P0_U1_CFG3 EQU 0x400100c3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG4 +CYREG_B0_P0_U1_CFG4 EQU 0x400100c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG5 +CYREG_B0_P0_U1_CFG5 EQU 0x400100c5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG6 +CYREG_B0_P0_U1_CFG6 EQU 0x400100c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG7 +CYREG_B0_P0_U1_CFG7 EQU 0x400100c7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG8 +CYREG_B0_P0_U1_CFG8 EQU 0x400100c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG9 +CYREG_B0_P0_U1_CFG9 EQU 0x400100c9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG10 +CYREG_B0_P0_U1_CFG10 EQU 0x400100ca + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG11 +CYREG_B0_P0_U1_CFG11 EQU 0x400100cb + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG12 +CYREG_B0_P0_U1_CFG12 EQU 0x400100cc + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG13 +CYREG_B0_P0_U1_CFG13 EQU 0x400100cd + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG14 +CYREG_B0_P0_U1_CFG14 EQU 0x400100ce + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG15 +CYREG_B0_P0_U1_CFG15 EQU 0x400100cf + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG16 +CYREG_B0_P0_U1_CFG16 EQU 0x400100d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG17 +CYREG_B0_P0_U1_CFG17 EQU 0x400100d1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG18 +CYREG_B0_P0_U1_CFG18 EQU 0x400100d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG19 +CYREG_B0_P0_U1_CFG19 EQU 0x400100d3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG20 +CYREG_B0_P0_U1_CFG20 EQU 0x400100d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG21 +CYREG_B0_P0_U1_CFG21 EQU 0x400100d5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG22 +CYREG_B0_P0_U1_CFG22 EQU 0x400100d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG23 +CYREG_B0_P0_U1_CFG23 EQU 0x400100d7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG24 +CYREG_B0_P0_U1_CFG24 EQU 0x400100d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG25 +CYREG_B0_P0_U1_CFG25 EQU 0x400100d9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG26 +CYREG_B0_P0_U1_CFG26 EQU 0x400100da + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG27 +CYREG_B0_P0_U1_CFG27 EQU 0x400100db + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG28 +CYREG_B0_P0_U1_CFG28 EQU 0x400100dc + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG29 +CYREG_B0_P0_U1_CFG29 EQU 0x400100dd + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG30 +CYREG_B0_P0_U1_CFG30 EQU 0x400100de + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG31 +CYREG_B0_P0_U1_CFG31 EQU 0x400100df + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG0 +CYREG_B0_P0_U1_DCFG0 EQU 0x400100e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG1 +CYREG_B0_P0_U1_DCFG1 EQU 0x400100e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG2 +CYREG_B0_P0_U1_DCFG2 EQU 0x400100e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG3 +CYREG_B0_P0_U1_DCFG3 EQU 0x400100e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG4 +CYREG_B0_P0_U1_DCFG4 EQU 0x400100e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG5 +CYREG_B0_P0_U1_DCFG5 EQU 0x400100ea + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG6 +CYREG_B0_P0_U1_DCFG6 EQU 0x400100ec + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG7 +CYREG_B0_P0_U1_DCFG7 EQU 0x400100ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_ROUTE_BASE +CYDEV_UCFG_B0_P0_ROUTE_BASE EQU 0x40010100 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_ROUTE_SIZE +CYDEV_UCFG_B0_P0_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_BASE +CYDEV_UCFG_B0_P1_BASE EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_SIZE +CYDEV_UCFG_B0_P1_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_BASE +CYDEV_UCFG_B0_P1_U0_BASE EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_SIZE +CYDEV_UCFG_B0_P1_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT0 +CYREG_B0_P1_U0_PLD_IT0 EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT1 +CYREG_B0_P1_U0_PLD_IT1 EQU 0x40010204 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT2 +CYREG_B0_P1_U0_PLD_IT2 EQU 0x40010208 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT3 +CYREG_B0_P1_U0_PLD_IT3 EQU 0x4001020c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT4 +CYREG_B0_P1_U0_PLD_IT4 EQU 0x40010210 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT5 +CYREG_B0_P1_U0_PLD_IT5 EQU 0x40010214 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT6 +CYREG_B0_P1_U0_PLD_IT6 EQU 0x40010218 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT7 +CYREG_B0_P1_U0_PLD_IT7 EQU 0x4001021c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT8 +CYREG_B0_P1_U0_PLD_IT8 EQU 0x40010220 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT9 +CYREG_B0_P1_U0_PLD_IT9 EQU 0x40010224 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT10 +CYREG_B0_P1_U0_PLD_IT10 EQU 0x40010228 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT11 +CYREG_B0_P1_U0_PLD_IT11 EQU 0x4001022c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_ORT0 +CYREG_B0_P1_U0_PLD_ORT0 EQU 0x40010230 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_ORT1 +CYREG_B0_P1_U0_PLD_ORT1 EQU 0x40010232 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_ORT2 +CYREG_B0_P1_U0_PLD_ORT2 EQU 0x40010234 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_ORT3 +CYREG_B0_P1_U0_PLD_ORT3 EQU 0x40010236 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_MC_CFG_CEN_CONST +CYREG_B0_P1_U0_MC_CFG_CEN_CONST EQU 0x40010238 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_MC_CFG_XORFB +CYREG_B0_P1_U0_MC_CFG_XORFB EQU 0x4001023a + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_MC_CFG_SET_RESET +CYREG_B0_P1_U0_MC_CFG_SET_RESET EQU 0x4001023c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_MC_CFG_BYPASS +CYREG_B0_P1_U0_MC_CFG_BYPASS EQU 0x4001023e + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG0 +CYREG_B0_P1_U0_CFG0 EQU 0x40010240 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG1 +CYREG_B0_P1_U0_CFG1 EQU 0x40010241 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG2 +CYREG_B0_P1_U0_CFG2 EQU 0x40010242 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG3 +CYREG_B0_P1_U0_CFG3 EQU 0x40010243 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG4 +CYREG_B0_P1_U0_CFG4 EQU 0x40010244 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG5 +CYREG_B0_P1_U0_CFG5 EQU 0x40010245 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG6 +CYREG_B0_P1_U0_CFG6 EQU 0x40010246 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG7 +CYREG_B0_P1_U0_CFG7 EQU 0x40010247 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG8 +CYREG_B0_P1_U0_CFG8 EQU 0x40010248 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG9 +CYREG_B0_P1_U0_CFG9 EQU 0x40010249 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG10 +CYREG_B0_P1_U0_CFG10 EQU 0x4001024a + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG11 +CYREG_B0_P1_U0_CFG11 EQU 0x4001024b + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG12 +CYREG_B0_P1_U0_CFG12 EQU 0x4001024c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG13 +CYREG_B0_P1_U0_CFG13 EQU 0x4001024d + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG14 +CYREG_B0_P1_U0_CFG14 EQU 0x4001024e + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG15 +CYREG_B0_P1_U0_CFG15 EQU 0x4001024f + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG16 +CYREG_B0_P1_U0_CFG16 EQU 0x40010250 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG17 +CYREG_B0_P1_U0_CFG17 EQU 0x40010251 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG18 +CYREG_B0_P1_U0_CFG18 EQU 0x40010252 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG19 +CYREG_B0_P1_U0_CFG19 EQU 0x40010253 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG20 +CYREG_B0_P1_U0_CFG20 EQU 0x40010254 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG21 +CYREG_B0_P1_U0_CFG21 EQU 0x40010255 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG22 +CYREG_B0_P1_U0_CFG22 EQU 0x40010256 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG23 +CYREG_B0_P1_U0_CFG23 EQU 0x40010257 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG24 +CYREG_B0_P1_U0_CFG24 EQU 0x40010258 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG25 +CYREG_B0_P1_U0_CFG25 EQU 0x40010259 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG26 +CYREG_B0_P1_U0_CFG26 EQU 0x4001025a + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG27 +CYREG_B0_P1_U0_CFG27 EQU 0x4001025b + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG28 +CYREG_B0_P1_U0_CFG28 EQU 0x4001025c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG29 +CYREG_B0_P1_U0_CFG29 EQU 0x4001025d + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG30 +CYREG_B0_P1_U0_CFG30 EQU 0x4001025e + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG31 +CYREG_B0_P1_U0_CFG31 EQU 0x4001025f + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG0 +CYREG_B0_P1_U0_DCFG0 EQU 0x40010260 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG1 +CYREG_B0_P1_U0_DCFG1 EQU 0x40010262 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG2 +CYREG_B0_P1_U0_DCFG2 EQU 0x40010264 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG3 +CYREG_B0_P1_U0_DCFG3 EQU 0x40010266 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG4 +CYREG_B0_P1_U0_DCFG4 EQU 0x40010268 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG5 +CYREG_B0_P1_U0_DCFG5 EQU 0x4001026a + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG6 +CYREG_B0_P1_U0_DCFG6 EQU 0x4001026c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG7 +CYREG_B0_P1_U0_DCFG7 EQU 0x4001026e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_BASE +CYDEV_UCFG_B0_P1_U1_BASE EQU 0x40010280 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_SIZE +CYDEV_UCFG_B0_P1_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT0 +CYREG_B0_P1_U1_PLD_IT0 EQU 0x40010280 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT1 +CYREG_B0_P1_U1_PLD_IT1 EQU 0x40010284 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT2 +CYREG_B0_P1_U1_PLD_IT2 EQU 0x40010288 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT3 +CYREG_B0_P1_U1_PLD_IT3 EQU 0x4001028c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT4 +CYREG_B0_P1_U1_PLD_IT4 EQU 0x40010290 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT5 +CYREG_B0_P1_U1_PLD_IT5 EQU 0x40010294 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT6 +CYREG_B0_P1_U1_PLD_IT6 EQU 0x40010298 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT7 +CYREG_B0_P1_U1_PLD_IT7 EQU 0x4001029c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT8 +CYREG_B0_P1_U1_PLD_IT8 EQU 0x400102a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT9 +CYREG_B0_P1_U1_PLD_IT9 EQU 0x400102a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT10 +CYREG_B0_P1_U1_PLD_IT10 EQU 0x400102a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT11 +CYREG_B0_P1_U1_PLD_IT11 EQU 0x400102ac + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_ORT0 +CYREG_B0_P1_U1_PLD_ORT0 EQU 0x400102b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_ORT1 +CYREG_B0_P1_U1_PLD_ORT1 EQU 0x400102b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_ORT2 +CYREG_B0_P1_U1_PLD_ORT2 EQU 0x400102b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_ORT3 +CYREG_B0_P1_U1_PLD_ORT3 EQU 0x400102b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_MC_CFG_CEN_CONST +CYREG_B0_P1_U1_MC_CFG_CEN_CONST EQU 0x400102b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_MC_CFG_XORFB +CYREG_B0_P1_U1_MC_CFG_XORFB EQU 0x400102ba + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_MC_CFG_SET_RESET +CYREG_B0_P1_U1_MC_CFG_SET_RESET EQU 0x400102bc + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_MC_CFG_BYPASS +CYREG_B0_P1_U1_MC_CFG_BYPASS EQU 0x400102be + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG0 +CYREG_B0_P1_U1_CFG0 EQU 0x400102c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG1 +CYREG_B0_P1_U1_CFG1 EQU 0x400102c1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG2 +CYREG_B0_P1_U1_CFG2 EQU 0x400102c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG3 +CYREG_B0_P1_U1_CFG3 EQU 0x400102c3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG4 +CYREG_B0_P1_U1_CFG4 EQU 0x400102c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG5 +CYREG_B0_P1_U1_CFG5 EQU 0x400102c5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG6 +CYREG_B0_P1_U1_CFG6 EQU 0x400102c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG7 +CYREG_B0_P1_U1_CFG7 EQU 0x400102c7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG8 +CYREG_B0_P1_U1_CFG8 EQU 0x400102c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG9 +CYREG_B0_P1_U1_CFG9 EQU 0x400102c9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG10 +CYREG_B0_P1_U1_CFG10 EQU 0x400102ca + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG11 +CYREG_B0_P1_U1_CFG11 EQU 0x400102cb + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG12 +CYREG_B0_P1_U1_CFG12 EQU 0x400102cc + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG13 +CYREG_B0_P1_U1_CFG13 EQU 0x400102cd + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG14 +CYREG_B0_P1_U1_CFG14 EQU 0x400102ce + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG15 +CYREG_B0_P1_U1_CFG15 EQU 0x400102cf + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG16 +CYREG_B0_P1_U1_CFG16 EQU 0x400102d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG17 +CYREG_B0_P1_U1_CFG17 EQU 0x400102d1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG18 +CYREG_B0_P1_U1_CFG18 EQU 0x400102d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG19 +CYREG_B0_P1_U1_CFG19 EQU 0x400102d3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG20 +CYREG_B0_P1_U1_CFG20 EQU 0x400102d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG21 +CYREG_B0_P1_U1_CFG21 EQU 0x400102d5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG22 +CYREG_B0_P1_U1_CFG22 EQU 0x400102d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG23 +CYREG_B0_P1_U1_CFG23 EQU 0x400102d7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG24 +CYREG_B0_P1_U1_CFG24 EQU 0x400102d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG25 +CYREG_B0_P1_U1_CFG25 EQU 0x400102d9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG26 +CYREG_B0_P1_U1_CFG26 EQU 0x400102da + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG27 +CYREG_B0_P1_U1_CFG27 EQU 0x400102db + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG28 +CYREG_B0_P1_U1_CFG28 EQU 0x400102dc + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG29 +CYREG_B0_P1_U1_CFG29 EQU 0x400102dd + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG30 +CYREG_B0_P1_U1_CFG30 EQU 0x400102de + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG31 +CYREG_B0_P1_U1_CFG31 EQU 0x400102df + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG0 +CYREG_B0_P1_U1_DCFG0 EQU 0x400102e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG1 +CYREG_B0_P1_U1_DCFG1 EQU 0x400102e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG2 +CYREG_B0_P1_U1_DCFG2 EQU 0x400102e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG3 +CYREG_B0_P1_U1_DCFG3 EQU 0x400102e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG4 +CYREG_B0_P1_U1_DCFG4 EQU 0x400102e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG5 +CYREG_B0_P1_U1_DCFG5 EQU 0x400102ea + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG6 +CYREG_B0_P1_U1_DCFG6 EQU 0x400102ec + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG7 +CYREG_B0_P1_U1_DCFG7 EQU 0x400102ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_ROUTE_BASE +CYDEV_UCFG_B0_P1_ROUTE_BASE EQU 0x40010300 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_ROUTE_SIZE +CYDEV_UCFG_B0_P1_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_BASE +CYDEV_UCFG_B0_P2_BASE EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_SIZE +CYDEV_UCFG_B0_P2_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_BASE +CYDEV_UCFG_B0_P2_U0_BASE EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_SIZE +CYDEV_UCFG_B0_P2_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT0 +CYREG_B0_P2_U0_PLD_IT0 EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT1 +CYREG_B0_P2_U0_PLD_IT1 EQU 0x40010404 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT2 +CYREG_B0_P2_U0_PLD_IT2 EQU 0x40010408 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT3 +CYREG_B0_P2_U0_PLD_IT3 EQU 0x4001040c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT4 +CYREG_B0_P2_U0_PLD_IT4 EQU 0x40010410 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT5 +CYREG_B0_P2_U0_PLD_IT5 EQU 0x40010414 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT6 +CYREG_B0_P2_U0_PLD_IT6 EQU 0x40010418 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT7 +CYREG_B0_P2_U0_PLD_IT7 EQU 0x4001041c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT8 +CYREG_B0_P2_U0_PLD_IT8 EQU 0x40010420 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT9 +CYREG_B0_P2_U0_PLD_IT9 EQU 0x40010424 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT10 +CYREG_B0_P2_U0_PLD_IT10 EQU 0x40010428 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT11 +CYREG_B0_P2_U0_PLD_IT11 EQU 0x4001042c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_ORT0 +CYREG_B0_P2_U0_PLD_ORT0 EQU 0x40010430 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_ORT1 +CYREG_B0_P2_U0_PLD_ORT1 EQU 0x40010432 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_ORT2 +CYREG_B0_P2_U0_PLD_ORT2 EQU 0x40010434 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_ORT3 +CYREG_B0_P2_U0_PLD_ORT3 EQU 0x40010436 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_MC_CFG_CEN_CONST +CYREG_B0_P2_U0_MC_CFG_CEN_CONST EQU 0x40010438 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_MC_CFG_XORFB +CYREG_B0_P2_U0_MC_CFG_XORFB EQU 0x4001043a + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_MC_CFG_SET_RESET +CYREG_B0_P2_U0_MC_CFG_SET_RESET EQU 0x4001043c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_MC_CFG_BYPASS +CYREG_B0_P2_U0_MC_CFG_BYPASS EQU 0x4001043e + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG0 +CYREG_B0_P2_U0_CFG0 EQU 0x40010440 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG1 +CYREG_B0_P2_U0_CFG1 EQU 0x40010441 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG2 +CYREG_B0_P2_U0_CFG2 EQU 0x40010442 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG3 +CYREG_B0_P2_U0_CFG3 EQU 0x40010443 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG4 +CYREG_B0_P2_U0_CFG4 EQU 0x40010444 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG5 +CYREG_B0_P2_U0_CFG5 EQU 0x40010445 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG6 +CYREG_B0_P2_U0_CFG6 EQU 0x40010446 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG7 +CYREG_B0_P2_U0_CFG7 EQU 0x40010447 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG8 +CYREG_B0_P2_U0_CFG8 EQU 0x40010448 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG9 +CYREG_B0_P2_U0_CFG9 EQU 0x40010449 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG10 +CYREG_B0_P2_U0_CFG10 EQU 0x4001044a + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG11 +CYREG_B0_P2_U0_CFG11 EQU 0x4001044b + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG12 +CYREG_B0_P2_U0_CFG12 EQU 0x4001044c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG13 +CYREG_B0_P2_U0_CFG13 EQU 0x4001044d + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG14 +CYREG_B0_P2_U0_CFG14 EQU 0x4001044e + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG15 +CYREG_B0_P2_U0_CFG15 EQU 0x4001044f + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG16 +CYREG_B0_P2_U0_CFG16 EQU 0x40010450 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG17 +CYREG_B0_P2_U0_CFG17 EQU 0x40010451 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG18 +CYREG_B0_P2_U0_CFG18 EQU 0x40010452 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG19 +CYREG_B0_P2_U0_CFG19 EQU 0x40010453 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG20 +CYREG_B0_P2_U0_CFG20 EQU 0x40010454 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG21 +CYREG_B0_P2_U0_CFG21 EQU 0x40010455 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG22 +CYREG_B0_P2_U0_CFG22 EQU 0x40010456 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG23 +CYREG_B0_P2_U0_CFG23 EQU 0x40010457 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG24 +CYREG_B0_P2_U0_CFG24 EQU 0x40010458 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG25 +CYREG_B0_P2_U0_CFG25 EQU 0x40010459 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG26 +CYREG_B0_P2_U0_CFG26 EQU 0x4001045a + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG27 +CYREG_B0_P2_U0_CFG27 EQU 0x4001045b + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG28 +CYREG_B0_P2_U0_CFG28 EQU 0x4001045c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG29 +CYREG_B0_P2_U0_CFG29 EQU 0x4001045d + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG30 +CYREG_B0_P2_U0_CFG30 EQU 0x4001045e + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG31 +CYREG_B0_P2_U0_CFG31 EQU 0x4001045f + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG0 +CYREG_B0_P2_U0_DCFG0 EQU 0x40010460 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG1 +CYREG_B0_P2_U0_DCFG1 EQU 0x40010462 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG2 +CYREG_B0_P2_U0_DCFG2 EQU 0x40010464 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG3 +CYREG_B0_P2_U0_DCFG3 EQU 0x40010466 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG4 +CYREG_B0_P2_U0_DCFG4 EQU 0x40010468 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG5 +CYREG_B0_P2_U0_DCFG5 EQU 0x4001046a + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG6 +CYREG_B0_P2_U0_DCFG6 EQU 0x4001046c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG7 +CYREG_B0_P2_U0_DCFG7 EQU 0x4001046e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_BASE +CYDEV_UCFG_B0_P2_U1_BASE EQU 0x40010480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_SIZE +CYDEV_UCFG_B0_P2_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT0 +CYREG_B0_P2_U1_PLD_IT0 EQU 0x40010480 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT1 +CYREG_B0_P2_U1_PLD_IT1 EQU 0x40010484 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT2 +CYREG_B0_P2_U1_PLD_IT2 EQU 0x40010488 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT3 +CYREG_B0_P2_U1_PLD_IT3 EQU 0x4001048c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT4 +CYREG_B0_P2_U1_PLD_IT4 EQU 0x40010490 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT5 +CYREG_B0_P2_U1_PLD_IT5 EQU 0x40010494 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT6 +CYREG_B0_P2_U1_PLD_IT6 EQU 0x40010498 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT7 +CYREG_B0_P2_U1_PLD_IT7 EQU 0x4001049c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT8 +CYREG_B0_P2_U1_PLD_IT8 EQU 0x400104a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT9 +CYREG_B0_P2_U1_PLD_IT9 EQU 0x400104a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT10 +CYREG_B0_P2_U1_PLD_IT10 EQU 0x400104a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT11 +CYREG_B0_P2_U1_PLD_IT11 EQU 0x400104ac + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_ORT0 +CYREG_B0_P2_U1_PLD_ORT0 EQU 0x400104b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_ORT1 +CYREG_B0_P2_U1_PLD_ORT1 EQU 0x400104b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_ORT2 +CYREG_B0_P2_U1_PLD_ORT2 EQU 0x400104b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_ORT3 +CYREG_B0_P2_U1_PLD_ORT3 EQU 0x400104b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_MC_CFG_CEN_CONST +CYREG_B0_P2_U1_MC_CFG_CEN_CONST EQU 0x400104b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_MC_CFG_XORFB +CYREG_B0_P2_U1_MC_CFG_XORFB EQU 0x400104ba + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_MC_CFG_SET_RESET +CYREG_B0_P2_U1_MC_CFG_SET_RESET EQU 0x400104bc + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_MC_CFG_BYPASS +CYREG_B0_P2_U1_MC_CFG_BYPASS EQU 0x400104be + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG0 +CYREG_B0_P2_U1_CFG0 EQU 0x400104c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG1 +CYREG_B0_P2_U1_CFG1 EQU 0x400104c1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG2 +CYREG_B0_P2_U1_CFG2 EQU 0x400104c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG3 +CYREG_B0_P2_U1_CFG3 EQU 0x400104c3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG4 +CYREG_B0_P2_U1_CFG4 EQU 0x400104c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG5 +CYREG_B0_P2_U1_CFG5 EQU 0x400104c5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG6 +CYREG_B0_P2_U1_CFG6 EQU 0x400104c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG7 +CYREG_B0_P2_U1_CFG7 EQU 0x400104c7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG8 +CYREG_B0_P2_U1_CFG8 EQU 0x400104c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG9 +CYREG_B0_P2_U1_CFG9 EQU 0x400104c9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG10 +CYREG_B0_P2_U1_CFG10 EQU 0x400104ca + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG11 +CYREG_B0_P2_U1_CFG11 EQU 0x400104cb + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG12 +CYREG_B0_P2_U1_CFG12 EQU 0x400104cc + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG13 +CYREG_B0_P2_U1_CFG13 EQU 0x400104cd + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG14 +CYREG_B0_P2_U1_CFG14 EQU 0x400104ce + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG15 +CYREG_B0_P2_U1_CFG15 EQU 0x400104cf + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG16 +CYREG_B0_P2_U1_CFG16 EQU 0x400104d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG17 +CYREG_B0_P2_U1_CFG17 EQU 0x400104d1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG18 +CYREG_B0_P2_U1_CFG18 EQU 0x400104d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG19 +CYREG_B0_P2_U1_CFG19 EQU 0x400104d3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG20 +CYREG_B0_P2_U1_CFG20 EQU 0x400104d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG21 +CYREG_B0_P2_U1_CFG21 EQU 0x400104d5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG22 +CYREG_B0_P2_U1_CFG22 EQU 0x400104d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG23 +CYREG_B0_P2_U1_CFG23 EQU 0x400104d7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG24 +CYREG_B0_P2_U1_CFG24 EQU 0x400104d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG25 +CYREG_B0_P2_U1_CFG25 EQU 0x400104d9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG26 +CYREG_B0_P2_U1_CFG26 EQU 0x400104da + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG27 +CYREG_B0_P2_U1_CFG27 EQU 0x400104db + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG28 +CYREG_B0_P2_U1_CFG28 EQU 0x400104dc + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG29 +CYREG_B0_P2_U1_CFG29 EQU 0x400104dd + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG30 +CYREG_B0_P2_U1_CFG30 EQU 0x400104de + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG31 +CYREG_B0_P2_U1_CFG31 EQU 0x400104df + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG0 +CYREG_B0_P2_U1_DCFG0 EQU 0x400104e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG1 +CYREG_B0_P2_U1_DCFG1 EQU 0x400104e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG2 +CYREG_B0_P2_U1_DCFG2 EQU 0x400104e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG3 +CYREG_B0_P2_U1_DCFG3 EQU 0x400104e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG4 +CYREG_B0_P2_U1_DCFG4 EQU 0x400104e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG5 +CYREG_B0_P2_U1_DCFG5 EQU 0x400104ea + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG6 +CYREG_B0_P2_U1_DCFG6 EQU 0x400104ec + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG7 +CYREG_B0_P2_U1_DCFG7 EQU 0x400104ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_ROUTE_BASE +CYDEV_UCFG_B0_P2_ROUTE_BASE EQU 0x40010500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_ROUTE_SIZE +CYDEV_UCFG_B0_P2_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_BASE +CYDEV_UCFG_B0_P3_BASE EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_SIZE +CYDEV_UCFG_B0_P3_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_BASE +CYDEV_UCFG_B0_P3_U0_BASE EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_SIZE +CYDEV_UCFG_B0_P3_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT0 +CYREG_B0_P3_U0_PLD_IT0 EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT1 +CYREG_B0_P3_U0_PLD_IT1 EQU 0x40010604 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT2 +CYREG_B0_P3_U0_PLD_IT2 EQU 0x40010608 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT3 +CYREG_B0_P3_U0_PLD_IT3 EQU 0x4001060c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT4 +CYREG_B0_P3_U0_PLD_IT4 EQU 0x40010610 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT5 +CYREG_B0_P3_U0_PLD_IT5 EQU 0x40010614 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT6 +CYREG_B0_P3_U0_PLD_IT6 EQU 0x40010618 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT7 +CYREG_B0_P3_U0_PLD_IT7 EQU 0x4001061c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT8 +CYREG_B0_P3_U0_PLD_IT8 EQU 0x40010620 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT9 +CYREG_B0_P3_U0_PLD_IT9 EQU 0x40010624 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT10 +CYREG_B0_P3_U0_PLD_IT10 EQU 0x40010628 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT11 +CYREG_B0_P3_U0_PLD_IT11 EQU 0x4001062c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_ORT0 +CYREG_B0_P3_U0_PLD_ORT0 EQU 0x40010630 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_ORT1 +CYREG_B0_P3_U0_PLD_ORT1 EQU 0x40010632 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_ORT2 +CYREG_B0_P3_U0_PLD_ORT2 EQU 0x40010634 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_ORT3 +CYREG_B0_P3_U0_PLD_ORT3 EQU 0x40010636 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_MC_CFG_CEN_CONST +CYREG_B0_P3_U0_MC_CFG_CEN_CONST EQU 0x40010638 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_MC_CFG_XORFB +CYREG_B0_P3_U0_MC_CFG_XORFB EQU 0x4001063a + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_MC_CFG_SET_RESET +CYREG_B0_P3_U0_MC_CFG_SET_RESET EQU 0x4001063c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_MC_CFG_BYPASS +CYREG_B0_P3_U0_MC_CFG_BYPASS EQU 0x4001063e + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG0 +CYREG_B0_P3_U0_CFG0 EQU 0x40010640 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG1 +CYREG_B0_P3_U0_CFG1 EQU 0x40010641 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG2 +CYREG_B0_P3_U0_CFG2 EQU 0x40010642 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG3 +CYREG_B0_P3_U0_CFG3 EQU 0x40010643 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG4 +CYREG_B0_P3_U0_CFG4 EQU 0x40010644 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG5 +CYREG_B0_P3_U0_CFG5 EQU 0x40010645 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG6 +CYREG_B0_P3_U0_CFG6 EQU 0x40010646 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG7 +CYREG_B0_P3_U0_CFG7 EQU 0x40010647 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG8 +CYREG_B0_P3_U0_CFG8 EQU 0x40010648 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG9 +CYREG_B0_P3_U0_CFG9 EQU 0x40010649 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG10 +CYREG_B0_P3_U0_CFG10 EQU 0x4001064a + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG11 +CYREG_B0_P3_U0_CFG11 EQU 0x4001064b + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG12 +CYREG_B0_P3_U0_CFG12 EQU 0x4001064c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG13 +CYREG_B0_P3_U0_CFG13 EQU 0x4001064d + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG14 +CYREG_B0_P3_U0_CFG14 EQU 0x4001064e + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG15 +CYREG_B0_P3_U0_CFG15 EQU 0x4001064f + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG16 +CYREG_B0_P3_U0_CFG16 EQU 0x40010650 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG17 +CYREG_B0_P3_U0_CFG17 EQU 0x40010651 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG18 +CYREG_B0_P3_U0_CFG18 EQU 0x40010652 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG19 +CYREG_B0_P3_U0_CFG19 EQU 0x40010653 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG20 +CYREG_B0_P3_U0_CFG20 EQU 0x40010654 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG21 +CYREG_B0_P3_U0_CFG21 EQU 0x40010655 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG22 +CYREG_B0_P3_U0_CFG22 EQU 0x40010656 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG23 +CYREG_B0_P3_U0_CFG23 EQU 0x40010657 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG24 +CYREG_B0_P3_U0_CFG24 EQU 0x40010658 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG25 +CYREG_B0_P3_U0_CFG25 EQU 0x40010659 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG26 +CYREG_B0_P3_U0_CFG26 EQU 0x4001065a + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG27 +CYREG_B0_P3_U0_CFG27 EQU 0x4001065b + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG28 +CYREG_B0_P3_U0_CFG28 EQU 0x4001065c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG29 +CYREG_B0_P3_U0_CFG29 EQU 0x4001065d + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG30 +CYREG_B0_P3_U0_CFG30 EQU 0x4001065e + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG31 +CYREG_B0_P3_U0_CFG31 EQU 0x4001065f + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG0 +CYREG_B0_P3_U0_DCFG0 EQU 0x40010660 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG1 +CYREG_B0_P3_U0_DCFG1 EQU 0x40010662 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG2 +CYREG_B0_P3_U0_DCFG2 EQU 0x40010664 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG3 +CYREG_B0_P3_U0_DCFG3 EQU 0x40010666 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG4 +CYREG_B0_P3_U0_DCFG4 EQU 0x40010668 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG5 +CYREG_B0_P3_U0_DCFG5 EQU 0x4001066a + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG6 +CYREG_B0_P3_U0_DCFG6 EQU 0x4001066c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG7 +CYREG_B0_P3_U0_DCFG7 EQU 0x4001066e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_BASE +CYDEV_UCFG_B0_P3_U1_BASE EQU 0x40010680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_SIZE +CYDEV_UCFG_B0_P3_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT0 +CYREG_B0_P3_U1_PLD_IT0 EQU 0x40010680 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT1 +CYREG_B0_P3_U1_PLD_IT1 EQU 0x40010684 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT2 +CYREG_B0_P3_U1_PLD_IT2 EQU 0x40010688 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT3 +CYREG_B0_P3_U1_PLD_IT3 EQU 0x4001068c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT4 +CYREG_B0_P3_U1_PLD_IT4 EQU 0x40010690 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT5 +CYREG_B0_P3_U1_PLD_IT5 EQU 0x40010694 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT6 +CYREG_B0_P3_U1_PLD_IT6 EQU 0x40010698 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT7 +CYREG_B0_P3_U1_PLD_IT7 EQU 0x4001069c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT8 +CYREG_B0_P3_U1_PLD_IT8 EQU 0x400106a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT9 +CYREG_B0_P3_U1_PLD_IT9 EQU 0x400106a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT10 +CYREG_B0_P3_U1_PLD_IT10 EQU 0x400106a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT11 +CYREG_B0_P3_U1_PLD_IT11 EQU 0x400106ac + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_ORT0 +CYREG_B0_P3_U1_PLD_ORT0 EQU 0x400106b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_ORT1 +CYREG_B0_P3_U1_PLD_ORT1 EQU 0x400106b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_ORT2 +CYREG_B0_P3_U1_PLD_ORT2 EQU 0x400106b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_ORT3 +CYREG_B0_P3_U1_PLD_ORT3 EQU 0x400106b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_MC_CFG_CEN_CONST +CYREG_B0_P3_U1_MC_CFG_CEN_CONST EQU 0x400106b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_MC_CFG_XORFB +CYREG_B0_P3_U1_MC_CFG_XORFB EQU 0x400106ba + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_MC_CFG_SET_RESET +CYREG_B0_P3_U1_MC_CFG_SET_RESET EQU 0x400106bc + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_MC_CFG_BYPASS +CYREG_B0_P3_U1_MC_CFG_BYPASS EQU 0x400106be + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG0 +CYREG_B0_P3_U1_CFG0 EQU 0x400106c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG1 +CYREG_B0_P3_U1_CFG1 EQU 0x400106c1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG2 +CYREG_B0_P3_U1_CFG2 EQU 0x400106c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG3 +CYREG_B0_P3_U1_CFG3 EQU 0x400106c3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG4 +CYREG_B0_P3_U1_CFG4 EQU 0x400106c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG5 +CYREG_B0_P3_U1_CFG5 EQU 0x400106c5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG6 +CYREG_B0_P3_U1_CFG6 EQU 0x400106c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG7 +CYREG_B0_P3_U1_CFG7 EQU 0x400106c7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG8 +CYREG_B0_P3_U1_CFG8 EQU 0x400106c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG9 +CYREG_B0_P3_U1_CFG9 EQU 0x400106c9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG10 +CYREG_B0_P3_U1_CFG10 EQU 0x400106ca + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG11 +CYREG_B0_P3_U1_CFG11 EQU 0x400106cb + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG12 +CYREG_B0_P3_U1_CFG12 EQU 0x400106cc + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG13 +CYREG_B0_P3_U1_CFG13 EQU 0x400106cd + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG14 +CYREG_B0_P3_U1_CFG14 EQU 0x400106ce + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG15 +CYREG_B0_P3_U1_CFG15 EQU 0x400106cf + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG16 +CYREG_B0_P3_U1_CFG16 EQU 0x400106d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG17 +CYREG_B0_P3_U1_CFG17 EQU 0x400106d1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG18 +CYREG_B0_P3_U1_CFG18 EQU 0x400106d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG19 +CYREG_B0_P3_U1_CFG19 EQU 0x400106d3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG20 +CYREG_B0_P3_U1_CFG20 EQU 0x400106d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG21 +CYREG_B0_P3_U1_CFG21 EQU 0x400106d5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG22 +CYREG_B0_P3_U1_CFG22 EQU 0x400106d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG23 +CYREG_B0_P3_U1_CFG23 EQU 0x400106d7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG24 +CYREG_B0_P3_U1_CFG24 EQU 0x400106d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG25 +CYREG_B0_P3_U1_CFG25 EQU 0x400106d9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG26 +CYREG_B0_P3_U1_CFG26 EQU 0x400106da + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG27 +CYREG_B0_P3_U1_CFG27 EQU 0x400106db + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG28 +CYREG_B0_P3_U1_CFG28 EQU 0x400106dc + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG29 +CYREG_B0_P3_U1_CFG29 EQU 0x400106dd + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG30 +CYREG_B0_P3_U1_CFG30 EQU 0x400106de + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG31 +CYREG_B0_P3_U1_CFG31 EQU 0x400106df + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG0 +CYREG_B0_P3_U1_DCFG0 EQU 0x400106e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG1 +CYREG_B0_P3_U1_DCFG1 EQU 0x400106e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG2 +CYREG_B0_P3_U1_DCFG2 EQU 0x400106e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG3 +CYREG_B0_P3_U1_DCFG3 EQU 0x400106e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG4 +CYREG_B0_P3_U1_DCFG4 EQU 0x400106e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG5 +CYREG_B0_P3_U1_DCFG5 EQU 0x400106ea + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG6 +CYREG_B0_P3_U1_DCFG6 EQU 0x400106ec + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG7 +CYREG_B0_P3_U1_DCFG7 EQU 0x400106ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_ROUTE_BASE +CYDEV_UCFG_B0_P3_ROUTE_BASE EQU 0x40010700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_ROUTE_SIZE +CYDEV_UCFG_B0_P3_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_BASE +CYDEV_UCFG_B0_P4_BASE EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_SIZE +CYDEV_UCFG_B0_P4_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_BASE +CYDEV_UCFG_B0_P4_U0_BASE EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_SIZE +CYDEV_UCFG_B0_P4_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT0 +CYREG_B0_P4_U0_PLD_IT0 EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT1 +CYREG_B0_P4_U0_PLD_IT1 EQU 0x40010804 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT2 +CYREG_B0_P4_U0_PLD_IT2 EQU 0x40010808 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT3 +CYREG_B0_P4_U0_PLD_IT3 EQU 0x4001080c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT4 +CYREG_B0_P4_U0_PLD_IT4 EQU 0x40010810 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT5 +CYREG_B0_P4_U0_PLD_IT5 EQU 0x40010814 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT6 +CYREG_B0_P4_U0_PLD_IT6 EQU 0x40010818 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT7 +CYREG_B0_P4_U0_PLD_IT7 EQU 0x4001081c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT8 +CYREG_B0_P4_U0_PLD_IT8 EQU 0x40010820 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT9 +CYREG_B0_P4_U0_PLD_IT9 EQU 0x40010824 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT10 +CYREG_B0_P4_U0_PLD_IT10 EQU 0x40010828 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT11 +CYREG_B0_P4_U0_PLD_IT11 EQU 0x4001082c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_ORT0 +CYREG_B0_P4_U0_PLD_ORT0 EQU 0x40010830 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_ORT1 +CYREG_B0_P4_U0_PLD_ORT1 EQU 0x40010832 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_ORT2 +CYREG_B0_P4_U0_PLD_ORT2 EQU 0x40010834 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_ORT3 +CYREG_B0_P4_U0_PLD_ORT3 EQU 0x40010836 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_MC_CFG_CEN_CONST +CYREG_B0_P4_U0_MC_CFG_CEN_CONST EQU 0x40010838 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_MC_CFG_XORFB +CYREG_B0_P4_U0_MC_CFG_XORFB EQU 0x4001083a + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_MC_CFG_SET_RESET +CYREG_B0_P4_U0_MC_CFG_SET_RESET EQU 0x4001083c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_MC_CFG_BYPASS +CYREG_B0_P4_U0_MC_CFG_BYPASS EQU 0x4001083e + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG0 +CYREG_B0_P4_U0_CFG0 EQU 0x40010840 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG1 +CYREG_B0_P4_U0_CFG1 EQU 0x40010841 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG2 +CYREG_B0_P4_U0_CFG2 EQU 0x40010842 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG3 +CYREG_B0_P4_U0_CFG3 EQU 0x40010843 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG4 +CYREG_B0_P4_U0_CFG4 EQU 0x40010844 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG5 +CYREG_B0_P4_U0_CFG5 EQU 0x40010845 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG6 +CYREG_B0_P4_U0_CFG6 EQU 0x40010846 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG7 +CYREG_B0_P4_U0_CFG7 EQU 0x40010847 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG8 +CYREG_B0_P4_U0_CFG8 EQU 0x40010848 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG9 +CYREG_B0_P4_U0_CFG9 EQU 0x40010849 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG10 +CYREG_B0_P4_U0_CFG10 EQU 0x4001084a + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG11 +CYREG_B0_P4_U0_CFG11 EQU 0x4001084b + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG12 +CYREG_B0_P4_U0_CFG12 EQU 0x4001084c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG13 +CYREG_B0_P4_U0_CFG13 EQU 0x4001084d + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG14 +CYREG_B0_P4_U0_CFG14 EQU 0x4001084e + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG15 +CYREG_B0_P4_U0_CFG15 EQU 0x4001084f + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG16 +CYREG_B0_P4_U0_CFG16 EQU 0x40010850 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG17 +CYREG_B0_P4_U0_CFG17 EQU 0x40010851 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG18 +CYREG_B0_P4_U0_CFG18 EQU 0x40010852 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG19 +CYREG_B0_P4_U0_CFG19 EQU 0x40010853 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG20 +CYREG_B0_P4_U0_CFG20 EQU 0x40010854 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG21 +CYREG_B0_P4_U0_CFG21 EQU 0x40010855 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG22 +CYREG_B0_P4_U0_CFG22 EQU 0x40010856 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG23 +CYREG_B0_P4_U0_CFG23 EQU 0x40010857 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG24 +CYREG_B0_P4_U0_CFG24 EQU 0x40010858 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG25 +CYREG_B0_P4_U0_CFG25 EQU 0x40010859 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG26 +CYREG_B0_P4_U0_CFG26 EQU 0x4001085a + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG27 +CYREG_B0_P4_U0_CFG27 EQU 0x4001085b + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG28 +CYREG_B0_P4_U0_CFG28 EQU 0x4001085c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG29 +CYREG_B0_P4_U0_CFG29 EQU 0x4001085d + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG30 +CYREG_B0_P4_U0_CFG30 EQU 0x4001085e + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG31 +CYREG_B0_P4_U0_CFG31 EQU 0x4001085f + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG0 +CYREG_B0_P4_U0_DCFG0 EQU 0x40010860 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG1 +CYREG_B0_P4_U0_DCFG1 EQU 0x40010862 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG2 +CYREG_B0_P4_U0_DCFG2 EQU 0x40010864 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG3 +CYREG_B0_P4_U0_DCFG3 EQU 0x40010866 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG4 +CYREG_B0_P4_U0_DCFG4 EQU 0x40010868 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG5 +CYREG_B0_P4_U0_DCFG5 EQU 0x4001086a + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG6 +CYREG_B0_P4_U0_DCFG6 EQU 0x4001086c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG7 +CYREG_B0_P4_U0_DCFG7 EQU 0x4001086e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_BASE +CYDEV_UCFG_B0_P4_U1_BASE EQU 0x40010880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_SIZE +CYDEV_UCFG_B0_P4_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT0 +CYREG_B0_P4_U1_PLD_IT0 EQU 0x40010880 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT1 +CYREG_B0_P4_U1_PLD_IT1 EQU 0x40010884 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT2 +CYREG_B0_P4_U1_PLD_IT2 EQU 0x40010888 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT3 +CYREG_B0_P4_U1_PLD_IT3 EQU 0x4001088c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT4 +CYREG_B0_P4_U1_PLD_IT4 EQU 0x40010890 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT5 +CYREG_B0_P4_U1_PLD_IT5 EQU 0x40010894 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT6 +CYREG_B0_P4_U1_PLD_IT6 EQU 0x40010898 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT7 +CYREG_B0_P4_U1_PLD_IT7 EQU 0x4001089c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT8 +CYREG_B0_P4_U1_PLD_IT8 EQU 0x400108a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT9 +CYREG_B0_P4_U1_PLD_IT9 EQU 0x400108a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT10 +CYREG_B0_P4_U1_PLD_IT10 EQU 0x400108a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT11 +CYREG_B0_P4_U1_PLD_IT11 EQU 0x400108ac + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_ORT0 +CYREG_B0_P4_U1_PLD_ORT0 EQU 0x400108b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_ORT1 +CYREG_B0_P4_U1_PLD_ORT1 EQU 0x400108b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_ORT2 +CYREG_B0_P4_U1_PLD_ORT2 EQU 0x400108b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_ORT3 +CYREG_B0_P4_U1_PLD_ORT3 EQU 0x400108b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_MC_CFG_CEN_CONST +CYREG_B0_P4_U1_MC_CFG_CEN_CONST EQU 0x400108b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_MC_CFG_XORFB +CYREG_B0_P4_U1_MC_CFG_XORFB EQU 0x400108ba + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_MC_CFG_SET_RESET +CYREG_B0_P4_U1_MC_CFG_SET_RESET EQU 0x400108bc + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_MC_CFG_BYPASS +CYREG_B0_P4_U1_MC_CFG_BYPASS EQU 0x400108be + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG0 +CYREG_B0_P4_U1_CFG0 EQU 0x400108c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG1 +CYREG_B0_P4_U1_CFG1 EQU 0x400108c1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG2 +CYREG_B0_P4_U1_CFG2 EQU 0x400108c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG3 +CYREG_B0_P4_U1_CFG3 EQU 0x400108c3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG4 +CYREG_B0_P4_U1_CFG4 EQU 0x400108c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG5 +CYREG_B0_P4_U1_CFG5 EQU 0x400108c5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG6 +CYREG_B0_P4_U1_CFG6 EQU 0x400108c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG7 +CYREG_B0_P4_U1_CFG7 EQU 0x400108c7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG8 +CYREG_B0_P4_U1_CFG8 EQU 0x400108c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG9 +CYREG_B0_P4_U1_CFG9 EQU 0x400108c9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG10 +CYREG_B0_P4_U1_CFG10 EQU 0x400108ca + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG11 +CYREG_B0_P4_U1_CFG11 EQU 0x400108cb + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG12 +CYREG_B0_P4_U1_CFG12 EQU 0x400108cc + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG13 +CYREG_B0_P4_U1_CFG13 EQU 0x400108cd + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG14 +CYREG_B0_P4_U1_CFG14 EQU 0x400108ce + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG15 +CYREG_B0_P4_U1_CFG15 EQU 0x400108cf + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG16 +CYREG_B0_P4_U1_CFG16 EQU 0x400108d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG17 +CYREG_B0_P4_U1_CFG17 EQU 0x400108d1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG18 +CYREG_B0_P4_U1_CFG18 EQU 0x400108d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG19 +CYREG_B0_P4_U1_CFG19 EQU 0x400108d3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG20 +CYREG_B0_P4_U1_CFG20 EQU 0x400108d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG21 +CYREG_B0_P4_U1_CFG21 EQU 0x400108d5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG22 +CYREG_B0_P4_U1_CFG22 EQU 0x400108d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG23 +CYREG_B0_P4_U1_CFG23 EQU 0x400108d7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG24 +CYREG_B0_P4_U1_CFG24 EQU 0x400108d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG25 +CYREG_B0_P4_U1_CFG25 EQU 0x400108d9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG26 +CYREG_B0_P4_U1_CFG26 EQU 0x400108da + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG27 +CYREG_B0_P4_U1_CFG27 EQU 0x400108db + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG28 +CYREG_B0_P4_U1_CFG28 EQU 0x400108dc + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG29 +CYREG_B0_P4_U1_CFG29 EQU 0x400108dd + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG30 +CYREG_B0_P4_U1_CFG30 EQU 0x400108de + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG31 +CYREG_B0_P4_U1_CFG31 EQU 0x400108df + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG0 +CYREG_B0_P4_U1_DCFG0 EQU 0x400108e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG1 +CYREG_B0_P4_U1_DCFG1 EQU 0x400108e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG2 +CYREG_B0_P4_U1_DCFG2 EQU 0x400108e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG3 +CYREG_B0_P4_U1_DCFG3 EQU 0x400108e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG4 +CYREG_B0_P4_U1_DCFG4 EQU 0x400108e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG5 +CYREG_B0_P4_U1_DCFG5 EQU 0x400108ea + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG6 +CYREG_B0_P4_U1_DCFG6 EQU 0x400108ec + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG7 +CYREG_B0_P4_U1_DCFG7 EQU 0x400108ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_ROUTE_BASE +CYDEV_UCFG_B0_P4_ROUTE_BASE EQU 0x40010900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_ROUTE_SIZE +CYDEV_UCFG_B0_P4_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_BASE +CYDEV_UCFG_B0_P5_BASE EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_SIZE +CYDEV_UCFG_B0_P5_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_BASE +CYDEV_UCFG_B0_P5_U0_BASE EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_SIZE +CYDEV_UCFG_B0_P5_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT0 +CYREG_B0_P5_U0_PLD_IT0 EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT1 +CYREG_B0_P5_U0_PLD_IT1 EQU 0x40010a04 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT2 +CYREG_B0_P5_U0_PLD_IT2 EQU 0x40010a08 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT3 +CYREG_B0_P5_U0_PLD_IT3 EQU 0x40010a0c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT4 +CYREG_B0_P5_U0_PLD_IT4 EQU 0x40010a10 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT5 +CYREG_B0_P5_U0_PLD_IT5 EQU 0x40010a14 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT6 +CYREG_B0_P5_U0_PLD_IT6 EQU 0x40010a18 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT7 +CYREG_B0_P5_U0_PLD_IT7 EQU 0x40010a1c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT8 +CYREG_B0_P5_U0_PLD_IT8 EQU 0x40010a20 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT9 +CYREG_B0_P5_U0_PLD_IT9 EQU 0x40010a24 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT10 +CYREG_B0_P5_U0_PLD_IT10 EQU 0x40010a28 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT11 +CYREG_B0_P5_U0_PLD_IT11 EQU 0x40010a2c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_ORT0 +CYREG_B0_P5_U0_PLD_ORT0 EQU 0x40010a30 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_ORT1 +CYREG_B0_P5_U0_PLD_ORT1 EQU 0x40010a32 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_ORT2 +CYREG_B0_P5_U0_PLD_ORT2 EQU 0x40010a34 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_ORT3 +CYREG_B0_P5_U0_PLD_ORT3 EQU 0x40010a36 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_MC_CFG_CEN_CONST +CYREG_B0_P5_U0_MC_CFG_CEN_CONST EQU 0x40010a38 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_MC_CFG_XORFB +CYREG_B0_P5_U0_MC_CFG_XORFB EQU 0x40010a3a + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_MC_CFG_SET_RESET +CYREG_B0_P5_U0_MC_CFG_SET_RESET EQU 0x40010a3c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_MC_CFG_BYPASS +CYREG_B0_P5_U0_MC_CFG_BYPASS EQU 0x40010a3e + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG0 +CYREG_B0_P5_U0_CFG0 EQU 0x40010a40 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG1 +CYREG_B0_P5_U0_CFG1 EQU 0x40010a41 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG2 +CYREG_B0_P5_U0_CFG2 EQU 0x40010a42 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG3 +CYREG_B0_P5_U0_CFG3 EQU 0x40010a43 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG4 +CYREG_B0_P5_U0_CFG4 EQU 0x40010a44 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG5 +CYREG_B0_P5_U0_CFG5 EQU 0x40010a45 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG6 +CYREG_B0_P5_U0_CFG6 EQU 0x40010a46 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG7 +CYREG_B0_P5_U0_CFG7 EQU 0x40010a47 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG8 +CYREG_B0_P5_U0_CFG8 EQU 0x40010a48 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG9 +CYREG_B0_P5_U0_CFG9 EQU 0x40010a49 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG10 +CYREG_B0_P5_U0_CFG10 EQU 0x40010a4a + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG11 +CYREG_B0_P5_U0_CFG11 EQU 0x40010a4b + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG12 +CYREG_B0_P5_U0_CFG12 EQU 0x40010a4c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG13 +CYREG_B0_P5_U0_CFG13 EQU 0x40010a4d + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG14 +CYREG_B0_P5_U0_CFG14 EQU 0x40010a4e + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG15 +CYREG_B0_P5_U0_CFG15 EQU 0x40010a4f + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG16 +CYREG_B0_P5_U0_CFG16 EQU 0x40010a50 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG17 +CYREG_B0_P5_U0_CFG17 EQU 0x40010a51 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG18 +CYREG_B0_P5_U0_CFG18 EQU 0x40010a52 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG19 +CYREG_B0_P5_U0_CFG19 EQU 0x40010a53 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG20 +CYREG_B0_P5_U0_CFG20 EQU 0x40010a54 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG21 +CYREG_B0_P5_U0_CFG21 EQU 0x40010a55 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG22 +CYREG_B0_P5_U0_CFG22 EQU 0x40010a56 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG23 +CYREG_B0_P5_U0_CFG23 EQU 0x40010a57 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG24 +CYREG_B0_P5_U0_CFG24 EQU 0x40010a58 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG25 +CYREG_B0_P5_U0_CFG25 EQU 0x40010a59 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG26 +CYREG_B0_P5_U0_CFG26 EQU 0x40010a5a + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG27 +CYREG_B0_P5_U0_CFG27 EQU 0x40010a5b + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG28 +CYREG_B0_P5_U0_CFG28 EQU 0x40010a5c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG29 +CYREG_B0_P5_U0_CFG29 EQU 0x40010a5d + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG30 +CYREG_B0_P5_U0_CFG30 EQU 0x40010a5e + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG31 +CYREG_B0_P5_U0_CFG31 EQU 0x40010a5f + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG0 +CYREG_B0_P5_U0_DCFG0 EQU 0x40010a60 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG1 +CYREG_B0_P5_U0_DCFG1 EQU 0x40010a62 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG2 +CYREG_B0_P5_U0_DCFG2 EQU 0x40010a64 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG3 +CYREG_B0_P5_U0_DCFG3 EQU 0x40010a66 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG4 +CYREG_B0_P5_U0_DCFG4 EQU 0x40010a68 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG5 +CYREG_B0_P5_U0_DCFG5 EQU 0x40010a6a + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG6 +CYREG_B0_P5_U0_DCFG6 EQU 0x40010a6c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG7 +CYREG_B0_P5_U0_DCFG7 EQU 0x40010a6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_BASE +CYDEV_UCFG_B0_P5_U1_BASE EQU 0x40010a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_SIZE +CYDEV_UCFG_B0_P5_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT0 +CYREG_B0_P5_U1_PLD_IT0 EQU 0x40010a80 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT1 +CYREG_B0_P5_U1_PLD_IT1 EQU 0x40010a84 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT2 +CYREG_B0_P5_U1_PLD_IT2 EQU 0x40010a88 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT3 +CYREG_B0_P5_U1_PLD_IT3 EQU 0x40010a8c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT4 +CYREG_B0_P5_U1_PLD_IT4 EQU 0x40010a90 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT5 +CYREG_B0_P5_U1_PLD_IT5 EQU 0x40010a94 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT6 +CYREG_B0_P5_U1_PLD_IT6 EQU 0x40010a98 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT7 +CYREG_B0_P5_U1_PLD_IT7 EQU 0x40010a9c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT8 +CYREG_B0_P5_U1_PLD_IT8 EQU 0x40010aa0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT9 +CYREG_B0_P5_U1_PLD_IT9 EQU 0x40010aa4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT10 +CYREG_B0_P5_U1_PLD_IT10 EQU 0x40010aa8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT11 +CYREG_B0_P5_U1_PLD_IT11 EQU 0x40010aac + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_ORT0 +CYREG_B0_P5_U1_PLD_ORT0 EQU 0x40010ab0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_ORT1 +CYREG_B0_P5_U1_PLD_ORT1 EQU 0x40010ab2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_ORT2 +CYREG_B0_P5_U1_PLD_ORT2 EQU 0x40010ab4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_ORT3 +CYREG_B0_P5_U1_PLD_ORT3 EQU 0x40010ab6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_MC_CFG_CEN_CONST +CYREG_B0_P5_U1_MC_CFG_CEN_CONST EQU 0x40010ab8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_MC_CFG_XORFB +CYREG_B0_P5_U1_MC_CFG_XORFB EQU 0x40010aba + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_MC_CFG_SET_RESET +CYREG_B0_P5_U1_MC_CFG_SET_RESET EQU 0x40010abc + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_MC_CFG_BYPASS +CYREG_B0_P5_U1_MC_CFG_BYPASS EQU 0x40010abe + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG0 +CYREG_B0_P5_U1_CFG0 EQU 0x40010ac0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG1 +CYREG_B0_P5_U1_CFG1 EQU 0x40010ac1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG2 +CYREG_B0_P5_U1_CFG2 EQU 0x40010ac2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG3 +CYREG_B0_P5_U1_CFG3 EQU 0x40010ac3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG4 +CYREG_B0_P5_U1_CFG4 EQU 0x40010ac4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG5 +CYREG_B0_P5_U1_CFG5 EQU 0x40010ac5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG6 +CYREG_B0_P5_U1_CFG6 EQU 0x40010ac6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG7 +CYREG_B0_P5_U1_CFG7 EQU 0x40010ac7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG8 +CYREG_B0_P5_U1_CFG8 EQU 0x40010ac8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG9 +CYREG_B0_P5_U1_CFG9 EQU 0x40010ac9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG10 +CYREG_B0_P5_U1_CFG10 EQU 0x40010aca + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG11 +CYREG_B0_P5_U1_CFG11 EQU 0x40010acb + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG12 +CYREG_B0_P5_U1_CFG12 EQU 0x40010acc + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG13 +CYREG_B0_P5_U1_CFG13 EQU 0x40010acd + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG14 +CYREG_B0_P5_U1_CFG14 EQU 0x40010ace + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG15 +CYREG_B0_P5_U1_CFG15 EQU 0x40010acf + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG16 +CYREG_B0_P5_U1_CFG16 EQU 0x40010ad0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG17 +CYREG_B0_P5_U1_CFG17 EQU 0x40010ad1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG18 +CYREG_B0_P5_U1_CFG18 EQU 0x40010ad2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG19 +CYREG_B0_P5_U1_CFG19 EQU 0x40010ad3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG20 +CYREG_B0_P5_U1_CFG20 EQU 0x40010ad4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG21 +CYREG_B0_P5_U1_CFG21 EQU 0x40010ad5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG22 +CYREG_B0_P5_U1_CFG22 EQU 0x40010ad6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG23 +CYREG_B0_P5_U1_CFG23 EQU 0x40010ad7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG24 +CYREG_B0_P5_U1_CFG24 EQU 0x40010ad8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG25 +CYREG_B0_P5_U1_CFG25 EQU 0x40010ad9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG26 +CYREG_B0_P5_U1_CFG26 EQU 0x40010ada + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG27 +CYREG_B0_P5_U1_CFG27 EQU 0x40010adb + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG28 +CYREG_B0_P5_U1_CFG28 EQU 0x40010adc + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG29 +CYREG_B0_P5_U1_CFG29 EQU 0x40010add + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG30 +CYREG_B0_P5_U1_CFG30 EQU 0x40010ade + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG31 +CYREG_B0_P5_U1_CFG31 EQU 0x40010adf + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG0 +CYREG_B0_P5_U1_DCFG0 EQU 0x40010ae0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG1 +CYREG_B0_P5_U1_DCFG1 EQU 0x40010ae2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG2 +CYREG_B0_P5_U1_DCFG2 EQU 0x40010ae4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG3 +CYREG_B0_P5_U1_DCFG3 EQU 0x40010ae6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG4 +CYREG_B0_P5_U1_DCFG4 EQU 0x40010ae8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG5 +CYREG_B0_P5_U1_DCFG5 EQU 0x40010aea + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG6 +CYREG_B0_P5_U1_DCFG6 EQU 0x40010aec + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG7 +CYREG_B0_P5_U1_DCFG7 EQU 0x40010aee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_ROUTE_BASE +CYDEV_UCFG_B0_P5_ROUTE_BASE EQU 0x40010b00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_ROUTE_SIZE +CYDEV_UCFG_B0_P5_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_BASE +CYDEV_UCFG_B0_P6_BASE EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_SIZE +CYDEV_UCFG_B0_P6_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_BASE +CYDEV_UCFG_B0_P6_U0_BASE EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_SIZE +CYDEV_UCFG_B0_P6_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT0 +CYREG_B0_P6_U0_PLD_IT0 EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT1 +CYREG_B0_P6_U0_PLD_IT1 EQU 0x40010c04 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT2 +CYREG_B0_P6_U0_PLD_IT2 EQU 0x40010c08 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT3 +CYREG_B0_P6_U0_PLD_IT3 EQU 0x40010c0c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT4 +CYREG_B0_P6_U0_PLD_IT4 EQU 0x40010c10 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT5 +CYREG_B0_P6_U0_PLD_IT5 EQU 0x40010c14 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT6 +CYREG_B0_P6_U0_PLD_IT6 EQU 0x40010c18 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT7 +CYREG_B0_P6_U0_PLD_IT7 EQU 0x40010c1c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT8 +CYREG_B0_P6_U0_PLD_IT8 EQU 0x40010c20 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT9 +CYREG_B0_P6_U0_PLD_IT9 EQU 0x40010c24 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT10 +CYREG_B0_P6_U0_PLD_IT10 EQU 0x40010c28 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT11 +CYREG_B0_P6_U0_PLD_IT11 EQU 0x40010c2c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_ORT0 +CYREG_B0_P6_U0_PLD_ORT0 EQU 0x40010c30 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_ORT1 +CYREG_B0_P6_U0_PLD_ORT1 EQU 0x40010c32 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_ORT2 +CYREG_B0_P6_U0_PLD_ORT2 EQU 0x40010c34 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_ORT3 +CYREG_B0_P6_U0_PLD_ORT3 EQU 0x40010c36 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_MC_CFG_CEN_CONST +CYREG_B0_P6_U0_MC_CFG_CEN_CONST EQU 0x40010c38 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_MC_CFG_XORFB +CYREG_B0_P6_U0_MC_CFG_XORFB EQU 0x40010c3a + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_MC_CFG_SET_RESET +CYREG_B0_P6_U0_MC_CFG_SET_RESET EQU 0x40010c3c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_MC_CFG_BYPASS +CYREG_B0_P6_U0_MC_CFG_BYPASS EQU 0x40010c3e + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG0 +CYREG_B0_P6_U0_CFG0 EQU 0x40010c40 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG1 +CYREG_B0_P6_U0_CFG1 EQU 0x40010c41 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG2 +CYREG_B0_P6_U0_CFG2 EQU 0x40010c42 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG3 +CYREG_B0_P6_U0_CFG3 EQU 0x40010c43 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG4 +CYREG_B0_P6_U0_CFG4 EQU 0x40010c44 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG5 +CYREG_B0_P6_U0_CFG5 EQU 0x40010c45 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG6 +CYREG_B0_P6_U0_CFG6 EQU 0x40010c46 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG7 +CYREG_B0_P6_U0_CFG7 EQU 0x40010c47 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG8 +CYREG_B0_P6_U0_CFG8 EQU 0x40010c48 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG9 +CYREG_B0_P6_U0_CFG9 EQU 0x40010c49 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG10 +CYREG_B0_P6_U0_CFG10 EQU 0x40010c4a + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG11 +CYREG_B0_P6_U0_CFG11 EQU 0x40010c4b + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG12 +CYREG_B0_P6_U0_CFG12 EQU 0x40010c4c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG13 +CYREG_B0_P6_U0_CFG13 EQU 0x40010c4d + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG14 +CYREG_B0_P6_U0_CFG14 EQU 0x40010c4e + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG15 +CYREG_B0_P6_U0_CFG15 EQU 0x40010c4f + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG16 +CYREG_B0_P6_U0_CFG16 EQU 0x40010c50 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG17 +CYREG_B0_P6_U0_CFG17 EQU 0x40010c51 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG18 +CYREG_B0_P6_U0_CFG18 EQU 0x40010c52 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG19 +CYREG_B0_P6_U0_CFG19 EQU 0x40010c53 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG20 +CYREG_B0_P6_U0_CFG20 EQU 0x40010c54 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG21 +CYREG_B0_P6_U0_CFG21 EQU 0x40010c55 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG22 +CYREG_B0_P6_U0_CFG22 EQU 0x40010c56 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG23 +CYREG_B0_P6_U0_CFG23 EQU 0x40010c57 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG24 +CYREG_B0_P6_U0_CFG24 EQU 0x40010c58 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG25 +CYREG_B0_P6_U0_CFG25 EQU 0x40010c59 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG26 +CYREG_B0_P6_U0_CFG26 EQU 0x40010c5a + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG27 +CYREG_B0_P6_U0_CFG27 EQU 0x40010c5b + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG28 +CYREG_B0_P6_U0_CFG28 EQU 0x40010c5c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG29 +CYREG_B0_P6_U0_CFG29 EQU 0x40010c5d + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG30 +CYREG_B0_P6_U0_CFG30 EQU 0x40010c5e + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG31 +CYREG_B0_P6_U0_CFG31 EQU 0x40010c5f + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG0 +CYREG_B0_P6_U0_DCFG0 EQU 0x40010c60 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG1 +CYREG_B0_P6_U0_DCFG1 EQU 0x40010c62 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG2 +CYREG_B0_P6_U0_DCFG2 EQU 0x40010c64 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG3 +CYREG_B0_P6_U0_DCFG3 EQU 0x40010c66 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG4 +CYREG_B0_P6_U0_DCFG4 EQU 0x40010c68 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG5 +CYREG_B0_P6_U0_DCFG5 EQU 0x40010c6a + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG6 +CYREG_B0_P6_U0_DCFG6 EQU 0x40010c6c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG7 +CYREG_B0_P6_U0_DCFG7 EQU 0x40010c6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_BASE +CYDEV_UCFG_B0_P6_U1_BASE EQU 0x40010c80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_SIZE +CYDEV_UCFG_B0_P6_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT0 +CYREG_B0_P6_U1_PLD_IT0 EQU 0x40010c80 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT1 +CYREG_B0_P6_U1_PLD_IT1 EQU 0x40010c84 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT2 +CYREG_B0_P6_U1_PLD_IT2 EQU 0x40010c88 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT3 +CYREG_B0_P6_U1_PLD_IT3 EQU 0x40010c8c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT4 +CYREG_B0_P6_U1_PLD_IT4 EQU 0x40010c90 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT5 +CYREG_B0_P6_U1_PLD_IT5 EQU 0x40010c94 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT6 +CYREG_B0_P6_U1_PLD_IT6 EQU 0x40010c98 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT7 +CYREG_B0_P6_U1_PLD_IT7 EQU 0x40010c9c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT8 +CYREG_B0_P6_U1_PLD_IT8 EQU 0x40010ca0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT9 +CYREG_B0_P6_U1_PLD_IT9 EQU 0x40010ca4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT10 +CYREG_B0_P6_U1_PLD_IT10 EQU 0x40010ca8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT11 +CYREG_B0_P6_U1_PLD_IT11 EQU 0x40010cac + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_ORT0 +CYREG_B0_P6_U1_PLD_ORT0 EQU 0x40010cb0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_ORT1 +CYREG_B0_P6_U1_PLD_ORT1 EQU 0x40010cb2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_ORT2 +CYREG_B0_P6_U1_PLD_ORT2 EQU 0x40010cb4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_ORT3 +CYREG_B0_P6_U1_PLD_ORT3 EQU 0x40010cb6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_MC_CFG_CEN_CONST +CYREG_B0_P6_U1_MC_CFG_CEN_CONST EQU 0x40010cb8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_MC_CFG_XORFB +CYREG_B0_P6_U1_MC_CFG_XORFB EQU 0x40010cba + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_MC_CFG_SET_RESET +CYREG_B0_P6_U1_MC_CFG_SET_RESET EQU 0x40010cbc + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_MC_CFG_BYPASS +CYREG_B0_P6_U1_MC_CFG_BYPASS EQU 0x40010cbe + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG0 +CYREG_B0_P6_U1_CFG0 EQU 0x40010cc0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG1 +CYREG_B0_P6_U1_CFG1 EQU 0x40010cc1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG2 +CYREG_B0_P6_U1_CFG2 EQU 0x40010cc2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG3 +CYREG_B0_P6_U1_CFG3 EQU 0x40010cc3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG4 +CYREG_B0_P6_U1_CFG4 EQU 0x40010cc4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG5 +CYREG_B0_P6_U1_CFG5 EQU 0x40010cc5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG6 +CYREG_B0_P6_U1_CFG6 EQU 0x40010cc6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG7 +CYREG_B0_P6_U1_CFG7 EQU 0x40010cc7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG8 +CYREG_B0_P6_U1_CFG8 EQU 0x40010cc8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG9 +CYREG_B0_P6_U1_CFG9 EQU 0x40010cc9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG10 +CYREG_B0_P6_U1_CFG10 EQU 0x40010cca + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG11 +CYREG_B0_P6_U1_CFG11 EQU 0x40010ccb + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG12 +CYREG_B0_P6_U1_CFG12 EQU 0x40010ccc + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG13 +CYREG_B0_P6_U1_CFG13 EQU 0x40010ccd + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG14 +CYREG_B0_P6_U1_CFG14 EQU 0x40010cce + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG15 +CYREG_B0_P6_U1_CFG15 EQU 0x40010ccf + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG16 +CYREG_B0_P6_U1_CFG16 EQU 0x40010cd0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG17 +CYREG_B0_P6_U1_CFG17 EQU 0x40010cd1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG18 +CYREG_B0_P6_U1_CFG18 EQU 0x40010cd2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG19 +CYREG_B0_P6_U1_CFG19 EQU 0x40010cd3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG20 +CYREG_B0_P6_U1_CFG20 EQU 0x40010cd4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG21 +CYREG_B0_P6_U1_CFG21 EQU 0x40010cd5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG22 +CYREG_B0_P6_U1_CFG22 EQU 0x40010cd6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG23 +CYREG_B0_P6_U1_CFG23 EQU 0x40010cd7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG24 +CYREG_B0_P6_U1_CFG24 EQU 0x40010cd8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG25 +CYREG_B0_P6_U1_CFG25 EQU 0x40010cd9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG26 +CYREG_B0_P6_U1_CFG26 EQU 0x40010cda + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG27 +CYREG_B0_P6_U1_CFG27 EQU 0x40010cdb + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG28 +CYREG_B0_P6_U1_CFG28 EQU 0x40010cdc + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG29 +CYREG_B0_P6_U1_CFG29 EQU 0x40010cdd + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG30 +CYREG_B0_P6_U1_CFG30 EQU 0x40010cde + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG31 +CYREG_B0_P6_U1_CFG31 EQU 0x40010cdf + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG0 +CYREG_B0_P6_U1_DCFG0 EQU 0x40010ce0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG1 +CYREG_B0_P6_U1_DCFG1 EQU 0x40010ce2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG2 +CYREG_B0_P6_U1_DCFG2 EQU 0x40010ce4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG3 +CYREG_B0_P6_U1_DCFG3 EQU 0x40010ce6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG4 +CYREG_B0_P6_U1_DCFG4 EQU 0x40010ce8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG5 +CYREG_B0_P6_U1_DCFG5 EQU 0x40010cea + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG6 +CYREG_B0_P6_U1_DCFG6 EQU 0x40010cec + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG7 +CYREG_B0_P6_U1_DCFG7 EQU 0x40010cee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_ROUTE_BASE +CYDEV_UCFG_B0_P6_ROUTE_BASE EQU 0x40010d00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_ROUTE_SIZE +CYDEV_UCFG_B0_P6_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_BASE +CYDEV_UCFG_B0_P7_BASE EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_SIZE +CYDEV_UCFG_B0_P7_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_BASE +CYDEV_UCFG_B0_P7_U0_BASE EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_SIZE +CYDEV_UCFG_B0_P7_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT0 +CYREG_B0_P7_U0_PLD_IT0 EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT1 +CYREG_B0_P7_U0_PLD_IT1 EQU 0x40010e04 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT2 +CYREG_B0_P7_U0_PLD_IT2 EQU 0x40010e08 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT3 +CYREG_B0_P7_U0_PLD_IT3 EQU 0x40010e0c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT4 +CYREG_B0_P7_U0_PLD_IT4 EQU 0x40010e10 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT5 +CYREG_B0_P7_U0_PLD_IT5 EQU 0x40010e14 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT6 +CYREG_B0_P7_U0_PLD_IT6 EQU 0x40010e18 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT7 +CYREG_B0_P7_U0_PLD_IT7 EQU 0x40010e1c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT8 +CYREG_B0_P7_U0_PLD_IT8 EQU 0x40010e20 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT9 +CYREG_B0_P7_U0_PLD_IT9 EQU 0x40010e24 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT10 +CYREG_B0_P7_U0_PLD_IT10 EQU 0x40010e28 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT11 +CYREG_B0_P7_U0_PLD_IT11 EQU 0x40010e2c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_ORT0 +CYREG_B0_P7_U0_PLD_ORT0 EQU 0x40010e30 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_ORT1 +CYREG_B0_P7_U0_PLD_ORT1 EQU 0x40010e32 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_ORT2 +CYREG_B0_P7_U0_PLD_ORT2 EQU 0x40010e34 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_ORT3 +CYREG_B0_P7_U0_PLD_ORT3 EQU 0x40010e36 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_MC_CFG_CEN_CONST +CYREG_B0_P7_U0_MC_CFG_CEN_CONST EQU 0x40010e38 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_MC_CFG_XORFB +CYREG_B0_P7_U0_MC_CFG_XORFB EQU 0x40010e3a + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_MC_CFG_SET_RESET +CYREG_B0_P7_U0_MC_CFG_SET_RESET EQU 0x40010e3c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_MC_CFG_BYPASS +CYREG_B0_P7_U0_MC_CFG_BYPASS EQU 0x40010e3e + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG0 +CYREG_B0_P7_U0_CFG0 EQU 0x40010e40 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG1 +CYREG_B0_P7_U0_CFG1 EQU 0x40010e41 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG2 +CYREG_B0_P7_U0_CFG2 EQU 0x40010e42 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG3 +CYREG_B0_P7_U0_CFG3 EQU 0x40010e43 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG4 +CYREG_B0_P7_U0_CFG4 EQU 0x40010e44 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG5 +CYREG_B0_P7_U0_CFG5 EQU 0x40010e45 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG6 +CYREG_B0_P7_U0_CFG6 EQU 0x40010e46 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG7 +CYREG_B0_P7_U0_CFG7 EQU 0x40010e47 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG8 +CYREG_B0_P7_U0_CFG8 EQU 0x40010e48 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG9 +CYREG_B0_P7_U0_CFG9 EQU 0x40010e49 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG10 +CYREG_B0_P7_U0_CFG10 EQU 0x40010e4a + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG11 +CYREG_B0_P7_U0_CFG11 EQU 0x40010e4b + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG12 +CYREG_B0_P7_U0_CFG12 EQU 0x40010e4c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG13 +CYREG_B0_P7_U0_CFG13 EQU 0x40010e4d + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG14 +CYREG_B0_P7_U0_CFG14 EQU 0x40010e4e + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG15 +CYREG_B0_P7_U0_CFG15 EQU 0x40010e4f + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG16 +CYREG_B0_P7_U0_CFG16 EQU 0x40010e50 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG17 +CYREG_B0_P7_U0_CFG17 EQU 0x40010e51 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG18 +CYREG_B0_P7_U0_CFG18 EQU 0x40010e52 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG19 +CYREG_B0_P7_U0_CFG19 EQU 0x40010e53 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG20 +CYREG_B0_P7_U0_CFG20 EQU 0x40010e54 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG21 +CYREG_B0_P7_U0_CFG21 EQU 0x40010e55 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG22 +CYREG_B0_P7_U0_CFG22 EQU 0x40010e56 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG23 +CYREG_B0_P7_U0_CFG23 EQU 0x40010e57 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG24 +CYREG_B0_P7_U0_CFG24 EQU 0x40010e58 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG25 +CYREG_B0_P7_U0_CFG25 EQU 0x40010e59 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG26 +CYREG_B0_P7_U0_CFG26 EQU 0x40010e5a + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG27 +CYREG_B0_P7_U0_CFG27 EQU 0x40010e5b + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG28 +CYREG_B0_P7_U0_CFG28 EQU 0x40010e5c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG29 +CYREG_B0_P7_U0_CFG29 EQU 0x40010e5d + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG30 +CYREG_B0_P7_U0_CFG30 EQU 0x40010e5e + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG31 +CYREG_B0_P7_U0_CFG31 EQU 0x40010e5f + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG0 +CYREG_B0_P7_U0_DCFG0 EQU 0x40010e60 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG1 +CYREG_B0_P7_U0_DCFG1 EQU 0x40010e62 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG2 +CYREG_B0_P7_U0_DCFG2 EQU 0x40010e64 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG3 +CYREG_B0_P7_U0_DCFG3 EQU 0x40010e66 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG4 +CYREG_B0_P7_U0_DCFG4 EQU 0x40010e68 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG5 +CYREG_B0_P7_U0_DCFG5 EQU 0x40010e6a + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG6 +CYREG_B0_P7_U0_DCFG6 EQU 0x40010e6c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG7 +CYREG_B0_P7_U0_DCFG7 EQU 0x40010e6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_BASE +CYDEV_UCFG_B0_P7_U1_BASE EQU 0x40010e80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_SIZE +CYDEV_UCFG_B0_P7_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT0 +CYREG_B0_P7_U1_PLD_IT0 EQU 0x40010e80 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT1 +CYREG_B0_P7_U1_PLD_IT1 EQU 0x40010e84 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT2 +CYREG_B0_P7_U1_PLD_IT2 EQU 0x40010e88 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT3 +CYREG_B0_P7_U1_PLD_IT3 EQU 0x40010e8c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT4 +CYREG_B0_P7_U1_PLD_IT4 EQU 0x40010e90 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT5 +CYREG_B0_P7_U1_PLD_IT5 EQU 0x40010e94 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT6 +CYREG_B0_P7_U1_PLD_IT6 EQU 0x40010e98 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT7 +CYREG_B0_P7_U1_PLD_IT7 EQU 0x40010e9c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT8 +CYREG_B0_P7_U1_PLD_IT8 EQU 0x40010ea0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT9 +CYREG_B0_P7_U1_PLD_IT9 EQU 0x40010ea4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT10 +CYREG_B0_P7_U1_PLD_IT10 EQU 0x40010ea8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT11 +CYREG_B0_P7_U1_PLD_IT11 EQU 0x40010eac + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_ORT0 +CYREG_B0_P7_U1_PLD_ORT0 EQU 0x40010eb0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_ORT1 +CYREG_B0_P7_U1_PLD_ORT1 EQU 0x40010eb2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_ORT2 +CYREG_B0_P7_U1_PLD_ORT2 EQU 0x40010eb4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_ORT3 +CYREG_B0_P7_U1_PLD_ORT3 EQU 0x40010eb6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_MC_CFG_CEN_CONST +CYREG_B0_P7_U1_MC_CFG_CEN_CONST EQU 0x40010eb8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_MC_CFG_XORFB +CYREG_B0_P7_U1_MC_CFG_XORFB EQU 0x40010eba + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_MC_CFG_SET_RESET +CYREG_B0_P7_U1_MC_CFG_SET_RESET EQU 0x40010ebc + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_MC_CFG_BYPASS +CYREG_B0_P7_U1_MC_CFG_BYPASS EQU 0x40010ebe + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG0 +CYREG_B0_P7_U1_CFG0 EQU 0x40010ec0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG1 +CYREG_B0_P7_U1_CFG1 EQU 0x40010ec1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG2 +CYREG_B0_P7_U1_CFG2 EQU 0x40010ec2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG3 +CYREG_B0_P7_U1_CFG3 EQU 0x40010ec3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG4 +CYREG_B0_P7_U1_CFG4 EQU 0x40010ec4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG5 +CYREG_B0_P7_U1_CFG5 EQU 0x40010ec5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG6 +CYREG_B0_P7_U1_CFG6 EQU 0x40010ec6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG7 +CYREG_B0_P7_U1_CFG7 EQU 0x40010ec7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG8 +CYREG_B0_P7_U1_CFG8 EQU 0x40010ec8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG9 +CYREG_B0_P7_U1_CFG9 EQU 0x40010ec9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG10 +CYREG_B0_P7_U1_CFG10 EQU 0x40010eca + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG11 +CYREG_B0_P7_U1_CFG11 EQU 0x40010ecb + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG12 +CYREG_B0_P7_U1_CFG12 EQU 0x40010ecc + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG13 +CYREG_B0_P7_U1_CFG13 EQU 0x40010ecd + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG14 +CYREG_B0_P7_U1_CFG14 EQU 0x40010ece + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG15 +CYREG_B0_P7_U1_CFG15 EQU 0x40010ecf + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG16 +CYREG_B0_P7_U1_CFG16 EQU 0x40010ed0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG17 +CYREG_B0_P7_U1_CFG17 EQU 0x40010ed1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG18 +CYREG_B0_P7_U1_CFG18 EQU 0x40010ed2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG19 +CYREG_B0_P7_U1_CFG19 EQU 0x40010ed3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG20 +CYREG_B0_P7_U1_CFG20 EQU 0x40010ed4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG21 +CYREG_B0_P7_U1_CFG21 EQU 0x40010ed5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG22 +CYREG_B0_P7_U1_CFG22 EQU 0x40010ed6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG23 +CYREG_B0_P7_U1_CFG23 EQU 0x40010ed7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG24 +CYREG_B0_P7_U1_CFG24 EQU 0x40010ed8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG25 +CYREG_B0_P7_U1_CFG25 EQU 0x40010ed9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG26 +CYREG_B0_P7_U1_CFG26 EQU 0x40010eda + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG27 +CYREG_B0_P7_U1_CFG27 EQU 0x40010edb + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG28 +CYREG_B0_P7_U1_CFG28 EQU 0x40010edc + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG29 +CYREG_B0_P7_U1_CFG29 EQU 0x40010edd + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG30 +CYREG_B0_P7_U1_CFG30 EQU 0x40010ede + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG31 +CYREG_B0_P7_U1_CFG31 EQU 0x40010edf + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG0 +CYREG_B0_P7_U1_DCFG0 EQU 0x40010ee0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG1 +CYREG_B0_P7_U1_DCFG1 EQU 0x40010ee2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG2 +CYREG_B0_P7_U1_DCFG2 EQU 0x40010ee4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG3 +CYREG_B0_P7_U1_DCFG3 EQU 0x40010ee6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG4 +CYREG_B0_P7_U1_DCFG4 EQU 0x40010ee8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG5 +CYREG_B0_P7_U1_DCFG5 EQU 0x40010eea + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG6 +CYREG_B0_P7_U1_DCFG6 EQU 0x40010eec + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG7 +CYREG_B0_P7_U1_DCFG7 EQU 0x40010eee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_ROUTE_BASE +CYDEV_UCFG_B0_P7_ROUTE_BASE EQU 0x40010f00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_ROUTE_SIZE +CYDEV_UCFG_B0_P7_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_BASE +CYDEV_UCFG_B1_BASE EQU 0x40011000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_SIZE +CYDEV_UCFG_B1_SIZE EQU 0x00000fef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_BASE +CYDEV_UCFG_B1_P2_BASE EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_SIZE +CYDEV_UCFG_B1_P2_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_BASE +CYDEV_UCFG_B1_P2_U0_BASE EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_SIZE +CYDEV_UCFG_B1_P2_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT0 +CYREG_B1_P2_U0_PLD_IT0 EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT1 +CYREG_B1_P2_U0_PLD_IT1 EQU 0x40011404 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT2 +CYREG_B1_P2_U0_PLD_IT2 EQU 0x40011408 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT3 +CYREG_B1_P2_U0_PLD_IT3 EQU 0x4001140c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT4 +CYREG_B1_P2_U0_PLD_IT4 EQU 0x40011410 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT5 +CYREG_B1_P2_U0_PLD_IT5 EQU 0x40011414 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT6 +CYREG_B1_P2_U0_PLD_IT6 EQU 0x40011418 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT7 +CYREG_B1_P2_U0_PLD_IT7 EQU 0x4001141c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT8 +CYREG_B1_P2_U0_PLD_IT8 EQU 0x40011420 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT9 +CYREG_B1_P2_U0_PLD_IT9 EQU 0x40011424 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT10 +CYREG_B1_P2_U0_PLD_IT10 EQU 0x40011428 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT11 +CYREG_B1_P2_U0_PLD_IT11 EQU 0x4001142c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_ORT0 +CYREG_B1_P2_U0_PLD_ORT0 EQU 0x40011430 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_ORT1 +CYREG_B1_P2_U0_PLD_ORT1 EQU 0x40011432 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_ORT2 +CYREG_B1_P2_U0_PLD_ORT2 EQU 0x40011434 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_ORT3 +CYREG_B1_P2_U0_PLD_ORT3 EQU 0x40011436 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_MC_CFG_CEN_CONST +CYREG_B1_P2_U0_MC_CFG_CEN_CONST EQU 0x40011438 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_MC_CFG_XORFB +CYREG_B1_P2_U0_MC_CFG_XORFB EQU 0x4001143a + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_MC_CFG_SET_RESET +CYREG_B1_P2_U0_MC_CFG_SET_RESET EQU 0x4001143c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_MC_CFG_BYPASS +CYREG_B1_P2_U0_MC_CFG_BYPASS EQU 0x4001143e + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG0 +CYREG_B1_P2_U0_CFG0 EQU 0x40011440 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG1 +CYREG_B1_P2_U0_CFG1 EQU 0x40011441 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG2 +CYREG_B1_P2_U0_CFG2 EQU 0x40011442 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG3 +CYREG_B1_P2_U0_CFG3 EQU 0x40011443 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG4 +CYREG_B1_P2_U0_CFG4 EQU 0x40011444 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG5 +CYREG_B1_P2_U0_CFG5 EQU 0x40011445 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG6 +CYREG_B1_P2_U0_CFG6 EQU 0x40011446 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG7 +CYREG_B1_P2_U0_CFG7 EQU 0x40011447 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG8 +CYREG_B1_P2_U0_CFG8 EQU 0x40011448 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG9 +CYREG_B1_P2_U0_CFG9 EQU 0x40011449 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG10 +CYREG_B1_P2_U0_CFG10 EQU 0x4001144a + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG11 +CYREG_B1_P2_U0_CFG11 EQU 0x4001144b + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG12 +CYREG_B1_P2_U0_CFG12 EQU 0x4001144c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG13 +CYREG_B1_P2_U0_CFG13 EQU 0x4001144d + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG14 +CYREG_B1_P2_U0_CFG14 EQU 0x4001144e + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG15 +CYREG_B1_P2_U0_CFG15 EQU 0x4001144f + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG16 +CYREG_B1_P2_U0_CFG16 EQU 0x40011450 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG17 +CYREG_B1_P2_U0_CFG17 EQU 0x40011451 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG18 +CYREG_B1_P2_U0_CFG18 EQU 0x40011452 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG19 +CYREG_B1_P2_U0_CFG19 EQU 0x40011453 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG20 +CYREG_B1_P2_U0_CFG20 EQU 0x40011454 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG21 +CYREG_B1_P2_U0_CFG21 EQU 0x40011455 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG22 +CYREG_B1_P2_U0_CFG22 EQU 0x40011456 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG23 +CYREG_B1_P2_U0_CFG23 EQU 0x40011457 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG24 +CYREG_B1_P2_U0_CFG24 EQU 0x40011458 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG25 +CYREG_B1_P2_U0_CFG25 EQU 0x40011459 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG26 +CYREG_B1_P2_U0_CFG26 EQU 0x4001145a + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG27 +CYREG_B1_P2_U0_CFG27 EQU 0x4001145b + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG28 +CYREG_B1_P2_U0_CFG28 EQU 0x4001145c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG29 +CYREG_B1_P2_U0_CFG29 EQU 0x4001145d + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG30 +CYREG_B1_P2_U0_CFG30 EQU 0x4001145e + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG31 +CYREG_B1_P2_U0_CFG31 EQU 0x4001145f + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG0 +CYREG_B1_P2_U0_DCFG0 EQU 0x40011460 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG1 +CYREG_B1_P2_U0_DCFG1 EQU 0x40011462 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG2 +CYREG_B1_P2_U0_DCFG2 EQU 0x40011464 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG3 +CYREG_B1_P2_U0_DCFG3 EQU 0x40011466 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG4 +CYREG_B1_P2_U0_DCFG4 EQU 0x40011468 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG5 +CYREG_B1_P2_U0_DCFG5 EQU 0x4001146a + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG6 +CYREG_B1_P2_U0_DCFG6 EQU 0x4001146c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG7 +CYREG_B1_P2_U0_DCFG7 EQU 0x4001146e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_BASE +CYDEV_UCFG_B1_P2_U1_BASE EQU 0x40011480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_SIZE +CYDEV_UCFG_B1_P2_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT0 +CYREG_B1_P2_U1_PLD_IT0 EQU 0x40011480 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT1 +CYREG_B1_P2_U1_PLD_IT1 EQU 0x40011484 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT2 +CYREG_B1_P2_U1_PLD_IT2 EQU 0x40011488 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT3 +CYREG_B1_P2_U1_PLD_IT3 EQU 0x4001148c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT4 +CYREG_B1_P2_U1_PLD_IT4 EQU 0x40011490 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT5 +CYREG_B1_P2_U1_PLD_IT5 EQU 0x40011494 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT6 +CYREG_B1_P2_U1_PLD_IT6 EQU 0x40011498 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT7 +CYREG_B1_P2_U1_PLD_IT7 EQU 0x4001149c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT8 +CYREG_B1_P2_U1_PLD_IT8 EQU 0x400114a0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT9 +CYREG_B1_P2_U1_PLD_IT9 EQU 0x400114a4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT10 +CYREG_B1_P2_U1_PLD_IT10 EQU 0x400114a8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT11 +CYREG_B1_P2_U1_PLD_IT11 EQU 0x400114ac + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_ORT0 +CYREG_B1_P2_U1_PLD_ORT0 EQU 0x400114b0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_ORT1 +CYREG_B1_P2_U1_PLD_ORT1 EQU 0x400114b2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_ORT2 +CYREG_B1_P2_U1_PLD_ORT2 EQU 0x400114b4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_ORT3 +CYREG_B1_P2_U1_PLD_ORT3 EQU 0x400114b6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_MC_CFG_CEN_CONST +CYREG_B1_P2_U1_MC_CFG_CEN_CONST EQU 0x400114b8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_MC_CFG_XORFB +CYREG_B1_P2_U1_MC_CFG_XORFB EQU 0x400114ba + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_MC_CFG_SET_RESET +CYREG_B1_P2_U1_MC_CFG_SET_RESET EQU 0x400114bc + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_MC_CFG_BYPASS +CYREG_B1_P2_U1_MC_CFG_BYPASS EQU 0x400114be + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG0 +CYREG_B1_P2_U1_CFG0 EQU 0x400114c0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG1 +CYREG_B1_P2_U1_CFG1 EQU 0x400114c1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG2 +CYREG_B1_P2_U1_CFG2 EQU 0x400114c2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG3 +CYREG_B1_P2_U1_CFG3 EQU 0x400114c3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG4 +CYREG_B1_P2_U1_CFG4 EQU 0x400114c4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG5 +CYREG_B1_P2_U1_CFG5 EQU 0x400114c5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG6 +CYREG_B1_P2_U1_CFG6 EQU 0x400114c6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG7 +CYREG_B1_P2_U1_CFG7 EQU 0x400114c7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG8 +CYREG_B1_P2_U1_CFG8 EQU 0x400114c8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG9 +CYREG_B1_P2_U1_CFG9 EQU 0x400114c9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG10 +CYREG_B1_P2_U1_CFG10 EQU 0x400114ca + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG11 +CYREG_B1_P2_U1_CFG11 EQU 0x400114cb + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG12 +CYREG_B1_P2_U1_CFG12 EQU 0x400114cc + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG13 +CYREG_B1_P2_U1_CFG13 EQU 0x400114cd + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG14 +CYREG_B1_P2_U1_CFG14 EQU 0x400114ce + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG15 +CYREG_B1_P2_U1_CFG15 EQU 0x400114cf + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG16 +CYREG_B1_P2_U1_CFG16 EQU 0x400114d0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG17 +CYREG_B1_P2_U1_CFG17 EQU 0x400114d1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG18 +CYREG_B1_P2_U1_CFG18 EQU 0x400114d2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG19 +CYREG_B1_P2_U1_CFG19 EQU 0x400114d3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG20 +CYREG_B1_P2_U1_CFG20 EQU 0x400114d4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG21 +CYREG_B1_P2_U1_CFG21 EQU 0x400114d5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG22 +CYREG_B1_P2_U1_CFG22 EQU 0x400114d6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG23 +CYREG_B1_P2_U1_CFG23 EQU 0x400114d7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG24 +CYREG_B1_P2_U1_CFG24 EQU 0x400114d8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG25 +CYREG_B1_P2_U1_CFG25 EQU 0x400114d9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG26 +CYREG_B1_P2_U1_CFG26 EQU 0x400114da + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG27 +CYREG_B1_P2_U1_CFG27 EQU 0x400114db + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG28 +CYREG_B1_P2_U1_CFG28 EQU 0x400114dc + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG29 +CYREG_B1_P2_U1_CFG29 EQU 0x400114dd + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG30 +CYREG_B1_P2_U1_CFG30 EQU 0x400114de + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG31 +CYREG_B1_P2_U1_CFG31 EQU 0x400114df + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG0 +CYREG_B1_P2_U1_DCFG0 EQU 0x400114e0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG1 +CYREG_B1_P2_U1_DCFG1 EQU 0x400114e2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG2 +CYREG_B1_P2_U1_DCFG2 EQU 0x400114e4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG3 +CYREG_B1_P2_U1_DCFG3 EQU 0x400114e6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG4 +CYREG_B1_P2_U1_DCFG4 EQU 0x400114e8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG5 +CYREG_B1_P2_U1_DCFG5 EQU 0x400114ea + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG6 +CYREG_B1_P2_U1_DCFG6 EQU 0x400114ec + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG7 +CYREG_B1_P2_U1_DCFG7 EQU 0x400114ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_ROUTE_BASE +CYDEV_UCFG_B1_P2_ROUTE_BASE EQU 0x40011500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_ROUTE_SIZE +CYDEV_UCFG_B1_P2_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_BASE +CYDEV_UCFG_B1_P3_BASE EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_SIZE +CYDEV_UCFG_B1_P3_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_BASE +CYDEV_UCFG_B1_P3_U0_BASE EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_SIZE +CYDEV_UCFG_B1_P3_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT0 +CYREG_B1_P3_U0_PLD_IT0 EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT1 +CYREG_B1_P3_U0_PLD_IT1 EQU 0x40011604 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT2 +CYREG_B1_P3_U0_PLD_IT2 EQU 0x40011608 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT3 +CYREG_B1_P3_U0_PLD_IT3 EQU 0x4001160c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT4 +CYREG_B1_P3_U0_PLD_IT4 EQU 0x40011610 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT5 +CYREG_B1_P3_U0_PLD_IT5 EQU 0x40011614 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT6 +CYREG_B1_P3_U0_PLD_IT6 EQU 0x40011618 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT7 +CYREG_B1_P3_U0_PLD_IT7 EQU 0x4001161c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT8 +CYREG_B1_P3_U0_PLD_IT8 EQU 0x40011620 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT9 +CYREG_B1_P3_U0_PLD_IT9 EQU 0x40011624 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT10 +CYREG_B1_P3_U0_PLD_IT10 EQU 0x40011628 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT11 +CYREG_B1_P3_U0_PLD_IT11 EQU 0x4001162c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_ORT0 +CYREG_B1_P3_U0_PLD_ORT0 EQU 0x40011630 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_ORT1 +CYREG_B1_P3_U0_PLD_ORT1 EQU 0x40011632 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_ORT2 +CYREG_B1_P3_U0_PLD_ORT2 EQU 0x40011634 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_ORT3 +CYREG_B1_P3_U0_PLD_ORT3 EQU 0x40011636 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_MC_CFG_CEN_CONST +CYREG_B1_P3_U0_MC_CFG_CEN_CONST EQU 0x40011638 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_MC_CFG_XORFB +CYREG_B1_P3_U0_MC_CFG_XORFB EQU 0x4001163a + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_MC_CFG_SET_RESET +CYREG_B1_P3_U0_MC_CFG_SET_RESET EQU 0x4001163c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_MC_CFG_BYPASS +CYREG_B1_P3_U0_MC_CFG_BYPASS EQU 0x4001163e + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG0 +CYREG_B1_P3_U0_CFG0 EQU 0x40011640 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG1 +CYREG_B1_P3_U0_CFG1 EQU 0x40011641 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG2 +CYREG_B1_P3_U0_CFG2 EQU 0x40011642 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG3 +CYREG_B1_P3_U0_CFG3 EQU 0x40011643 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG4 +CYREG_B1_P3_U0_CFG4 EQU 0x40011644 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG5 +CYREG_B1_P3_U0_CFG5 EQU 0x40011645 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG6 +CYREG_B1_P3_U0_CFG6 EQU 0x40011646 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG7 +CYREG_B1_P3_U0_CFG7 EQU 0x40011647 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG8 +CYREG_B1_P3_U0_CFG8 EQU 0x40011648 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG9 +CYREG_B1_P3_U0_CFG9 EQU 0x40011649 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG10 +CYREG_B1_P3_U0_CFG10 EQU 0x4001164a + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG11 +CYREG_B1_P3_U0_CFG11 EQU 0x4001164b + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG12 +CYREG_B1_P3_U0_CFG12 EQU 0x4001164c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG13 +CYREG_B1_P3_U0_CFG13 EQU 0x4001164d + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG14 +CYREG_B1_P3_U0_CFG14 EQU 0x4001164e + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG15 +CYREG_B1_P3_U0_CFG15 EQU 0x4001164f + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG16 +CYREG_B1_P3_U0_CFG16 EQU 0x40011650 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG17 +CYREG_B1_P3_U0_CFG17 EQU 0x40011651 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG18 +CYREG_B1_P3_U0_CFG18 EQU 0x40011652 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG19 +CYREG_B1_P3_U0_CFG19 EQU 0x40011653 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG20 +CYREG_B1_P3_U0_CFG20 EQU 0x40011654 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG21 +CYREG_B1_P3_U0_CFG21 EQU 0x40011655 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG22 +CYREG_B1_P3_U0_CFG22 EQU 0x40011656 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG23 +CYREG_B1_P3_U0_CFG23 EQU 0x40011657 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG24 +CYREG_B1_P3_U0_CFG24 EQU 0x40011658 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG25 +CYREG_B1_P3_U0_CFG25 EQU 0x40011659 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG26 +CYREG_B1_P3_U0_CFG26 EQU 0x4001165a + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG27 +CYREG_B1_P3_U0_CFG27 EQU 0x4001165b + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG28 +CYREG_B1_P3_U0_CFG28 EQU 0x4001165c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG29 +CYREG_B1_P3_U0_CFG29 EQU 0x4001165d + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG30 +CYREG_B1_P3_U0_CFG30 EQU 0x4001165e + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG31 +CYREG_B1_P3_U0_CFG31 EQU 0x4001165f + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG0 +CYREG_B1_P3_U0_DCFG0 EQU 0x40011660 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG1 +CYREG_B1_P3_U0_DCFG1 EQU 0x40011662 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG2 +CYREG_B1_P3_U0_DCFG2 EQU 0x40011664 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG3 +CYREG_B1_P3_U0_DCFG3 EQU 0x40011666 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG4 +CYREG_B1_P3_U0_DCFG4 EQU 0x40011668 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG5 +CYREG_B1_P3_U0_DCFG5 EQU 0x4001166a + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG6 +CYREG_B1_P3_U0_DCFG6 EQU 0x4001166c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG7 +CYREG_B1_P3_U0_DCFG7 EQU 0x4001166e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_BASE +CYDEV_UCFG_B1_P3_U1_BASE EQU 0x40011680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_SIZE +CYDEV_UCFG_B1_P3_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT0 +CYREG_B1_P3_U1_PLD_IT0 EQU 0x40011680 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT1 +CYREG_B1_P3_U1_PLD_IT1 EQU 0x40011684 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT2 +CYREG_B1_P3_U1_PLD_IT2 EQU 0x40011688 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT3 +CYREG_B1_P3_U1_PLD_IT3 EQU 0x4001168c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT4 +CYREG_B1_P3_U1_PLD_IT4 EQU 0x40011690 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT5 +CYREG_B1_P3_U1_PLD_IT5 EQU 0x40011694 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT6 +CYREG_B1_P3_U1_PLD_IT6 EQU 0x40011698 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT7 +CYREG_B1_P3_U1_PLD_IT7 EQU 0x4001169c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT8 +CYREG_B1_P3_U1_PLD_IT8 EQU 0x400116a0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT9 +CYREG_B1_P3_U1_PLD_IT9 EQU 0x400116a4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT10 +CYREG_B1_P3_U1_PLD_IT10 EQU 0x400116a8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT11 +CYREG_B1_P3_U1_PLD_IT11 EQU 0x400116ac + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_ORT0 +CYREG_B1_P3_U1_PLD_ORT0 EQU 0x400116b0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_ORT1 +CYREG_B1_P3_U1_PLD_ORT1 EQU 0x400116b2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_ORT2 +CYREG_B1_P3_U1_PLD_ORT2 EQU 0x400116b4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_ORT3 +CYREG_B1_P3_U1_PLD_ORT3 EQU 0x400116b6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_MC_CFG_CEN_CONST +CYREG_B1_P3_U1_MC_CFG_CEN_CONST EQU 0x400116b8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_MC_CFG_XORFB +CYREG_B1_P3_U1_MC_CFG_XORFB EQU 0x400116ba + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_MC_CFG_SET_RESET +CYREG_B1_P3_U1_MC_CFG_SET_RESET EQU 0x400116bc + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_MC_CFG_BYPASS +CYREG_B1_P3_U1_MC_CFG_BYPASS EQU 0x400116be + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG0 +CYREG_B1_P3_U1_CFG0 EQU 0x400116c0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG1 +CYREG_B1_P3_U1_CFG1 EQU 0x400116c1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG2 +CYREG_B1_P3_U1_CFG2 EQU 0x400116c2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG3 +CYREG_B1_P3_U1_CFG3 EQU 0x400116c3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG4 +CYREG_B1_P3_U1_CFG4 EQU 0x400116c4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG5 +CYREG_B1_P3_U1_CFG5 EQU 0x400116c5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG6 +CYREG_B1_P3_U1_CFG6 EQU 0x400116c6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG7 +CYREG_B1_P3_U1_CFG7 EQU 0x400116c7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG8 +CYREG_B1_P3_U1_CFG8 EQU 0x400116c8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG9 +CYREG_B1_P3_U1_CFG9 EQU 0x400116c9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG10 +CYREG_B1_P3_U1_CFG10 EQU 0x400116ca + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG11 +CYREG_B1_P3_U1_CFG11 EQU 0x400116cb + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG12 +CYREG_B1_P3_U1_CFG12 EQU 0x400116cc + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG13 +CYREG_B1_P3_U1_CFG13 EQU 0x400116cd + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG14 +CYREG_B1_P3_U1_CFG14 EQU 0x400116ce + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG15 +CYREG_B1_P3_U1_CFG15 EQU 0x400116cf + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG16 +CYREG_B1_P3_U1_CFG16 EQU 0x400116d0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG17 +CYREG_B1_P3_U1_CFG17 EQU 0x400116d1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG18 +CYREG_B1_P3_U1_CFG18 EQU 0x400116d2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG19 +CYREG_B1_P3_U1_CFG19 EQU 0x400116d3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG20 +CYREG_B1_P3_U1_CFG20 EQU 0x400116d4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG21 +CYREG_B1_P3_U1_CFG21 EQU 0x400116d5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG22 +CYREG_B1_P3_U1_CFG22 EQU 0x400116d6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG23 +CYREG_B1_P3_U1_CFG23 EQU 0x400116d7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG24 +CYREG_B1_P3_U1_CFG24 EQU 0x400116d8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG25 +CYREG_B1_P3_U1_CFG25 EQU 0x400116d9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG26 +CYREG_B1_P3_U1_CFG26 EQU 0x400116da + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG27 +CYREG_B1_P3_U1_CFG27 EQU 0x400116db + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG28 +CYREG_B1_P3_U1_CFG28 EQU 0x400116dc + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG29 +CYREG_B1_P3_U1_CFG29 EQU 0x400116dd + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG30 +CYREG_B1_P3_U1_CFG30 EQU 0x400116de + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG31 +CYREG_B1_P3_U1_CFG31 EQU 0x400116df + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG0 +CYREG_B1_P3_U1_DCFG0 EQU 0x400116e0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG1 +CYREG_B1_P3_U1_DCFG1 EQU 0x400116e2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG2 +CYREG_B1_P3_U1_DCFG2 EQU 0x400116e4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG3 +CYREG_B1_P3_U1_DCFG3 EQU 0x400116e6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG4 +CYREG_B1_P3_U1_DCFG4 EQU 0x400116e8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG5 +CYREG_B1_P3_U1_DCFG5 EQU 0x400116ea + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG6 +CYREG_B1_P3_U1_DCFG6 EQU 0x400116ec + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG7 +CYREG_B1_P3_U1_DCFG7 EQU 0x400116ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_ROUTE_BASE +CYDEV_UCFG_B1_P3_ROUTE_BASE EQU 0x40011700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_ROUTE_SIZE +CYDEV_UCFG_B1_P3_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_BASE +CYDEV_UCFG_B1_P4_BASE EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_SIZE +CYDEV_UCFG_B1_P4_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_BASE +CYDEV_UCFG_B1_P4_U0_BASE EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_SIZE +CYDEV_UCFG_B1_P4_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT0 +CYREG_B1_P4_U0_PLD_IT0 EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT1 +CYREG_B1_P4_U0_PLD_IT1 EQU 0x40011804 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT2 +CYREG_B1_P4_U0_PLD_IT2 EQU 0x40011808 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT3 +CYREG_B1_P4_U0_PLD_IT3 EQU 0x4001180c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT4 +CYREG_B1_P4_U0_PLD_IT4 EQU 0x40011810 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT5 +CYREG_B1_P4_U0_PLD_IT5 EQU 0x40011814 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT6 +CYREG_B1_P4_U0_PLD_IT6 EQU 0x40011818 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT7 +CYREG_B1_P4_U0_PLD_IT7 EQU 0x4001181c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT8 +CYREG_B1_P4_U0_PLD_IT8 EQU 0x40011820 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT9 +CYREG_B1_P4_U0_PLD_IT9 EQU 0x40011824 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT10 +CYREG_B1_P4_U0_PLD_IT10 EQU 0x40011828 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT11 +CYREG_B1_P4_U0_PLD_IT11 EQU 0x4001182c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_ORT0 +CYREG_B1_P4_U0_PLD_ORT0 EQU 0x40011830 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_ORT1 +CYREG_B1_P4_U0_PLD_ORT1 EQU 0x40011832 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_ORT2 +CYREG_B1_P4_U0_PLD_ORT2 EQU 0x40011834 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_ORT3 +CYREG_B1_P4_U0_PLD_ORT3 EQU 0x40011836 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_MC_CFG_CEN_CONST +CYREG_B1_P4_U0_MC_CFG_CEN_CONST EQU 0x40011838 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_MC_CFG_XORFB +CYREG_B1_P4_U0_MC_CFG_XORFB EQU 0x4001183a + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_MC_CFG_SET_RESET +CYREG_B1_P4_U0_MC_CFG_SET_RESET EQU 0x4001183c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_MC_CFG_BYPASS +CYREG_B1_P4_U0_MC_CFG_BYPASS EQU 0x4001183e + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG0 +CYREG_B1_P4_U0_CFG0 EQU 0x40011840 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG1 +CYREG_B1_P4_U0_CFG1 EQU 0x40011841 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG2 +CYREG_B1_P4_U0_CFG2 EQU 0x40011842 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG3 +CYREG_B1_P4_U0_CFG3 EQU 0x40011843 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG4 +CYREG_B1_P4_U0_CFG4 EQU 0x40011844 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG5 +CYREG_B1_P4_U0_CFG5 EQU 0x40011845 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG6 +CYREG_B1_P4_U0_CFG6 EQU 0x40011846 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG7 +CYREG_B1_P4_U0_CFG7 EQU 0x40011847 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG8 +CYREG_B1_P4_U0_CFG8 EQU 0x40011848 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG9 +CYREG_B1_P4_U0_CFG9 EQU 0x40011849 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG10 +CYREG_B1_P4_U0_CFG10 EQU 0x4001184a + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG11 +CYREG_B1_P4_U0_CFG11 EQU 0x4001184b + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG12 +CYREG_B1_P4_U0_CFG12 EQU 0x4001184c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG13 +CYREG_B1_P4_U0_CFG13 EQU 0x4001184d + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG14 +CYREG_B1_P4_U0_CFG14 EQU 0x4001184e + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG15 +CYREG_B1_P4_U0_CFG15 EQU 0x4001184f + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG16 +CYREG_B1_P4_U0_CFG16 EQU 0x40011850 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG17 +CYREG_B1_P4_U0_CFG17 EQU 0x40011851 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG18 +CYREG_B1_P4_U0_CFG18 EQU 0x40011852 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG19 +CYREG_B1_P4_U0_CFG19 EQU 0x40011853 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG20 +CYREG_B1_P4_U0_CFG20 EQU 0x40011854 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG21 +CYREG_B1_P4_U0_CFG21 EQU 0x40011855 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG22 +CYREG_B1_P4_U0_CFG22 EQU 0x40011856 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG23 +CYREG_B1_P4_U0_CFG23 EQU 0x40011857 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG24 +CYREG_B1_P4_U0_CFG24 EQU 0x40011858 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG25 +CYREG_B1_P4_U0_CFG25 EQU 0x40011859 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG26 +CYREG_B1_P4_U0_CFG26 EQU 0x4001185a + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG27 +CYREG_B1_P4_U0_CFG27 EQU 0x4001185b + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG28 +CYREG_B1_P4_U0_CFG28 EQU 0x4001185c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG29 +CYREG_B1_P4_U0_CFG29 EQU 0x4001185d + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG30 +CYREG_B1_P4_U0_CFG30 EQU 0x4001185e + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG31 +CYREG_B1_P4_U0_CFG31 EQU 0x4001185f + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG0 +CYREG_B1_P4_U0_DCFG0 EQU 0x40011860 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG1 +CYREG_B1_P4_U0_DCFG1 EQU 0x40011862 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG2 +CYREG_B1_P4_U0_DCFG2 EQU 0x40011864 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG3 +CYREG_B1_P4_U0_DCFG3 EQU 0x40011866 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG4 +CYREG_B1_P4_U0_DCFG4 EQU 0x40011868 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG5 +CYREG_B1_P4_U0_DCFG5 EQU 0x4001186a + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG6 +CYREG_B1_P4_U0_DCFG6 EQU 0x4001186c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG7 +CYREG_B1_P4_U0_DCFG7 EQU 0x4001186e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_BASE +CYDEV_UCFG_B1_P4_U1_BASE EQU 0x40011880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_SIZE +CYDEV_UCFG_B1_P4_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT0 +CYREG_B1_P4_U1_PLD_IT0 EQU 0x40011880 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT1 +CYREG_B1_P4_U1_PLD_IT1 EQU 0x40011884 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT2 +CYREG_B1_P4_U1_PLD_IT2 EQU 0x40011888 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT3 +CYREG_B1_P4_U1_PLD_IT3 EQU 0x4001188c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT4 +CYREG_B1_P4_U1_PLD_IT4 EQU 0x40011890 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT5 +CYREG_B1_P4_U1_PLD_IT5 EQU 0x40011894 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT6 +CYREG_B1_P4_U1_PLD_IT6 EQU 0x40011898 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT7 +CYREG_B1_P4_U1_PLD_IT7 EQU 0x4001189c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT8 +CYREG_B1_P4_U1_PLD_IT8 EQU 0x400118a0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT9 +CYREG_B1_P4_U1_PLD_IT9 EQU 0x400118a4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT10 +CYREG_B1_P4_U1_PLD_IT10 EQU 0x400118a8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT11 +CYREG_B1_P4_U1_PLD_IT11 EQU 0x400118ac + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_ORT0 +CYREG_B1_P4_U1_PLD_ORT0 EQU 0x400118b0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_ORT1 +CYREG_B1_P4_U1_PLD_ORT1 EQU 0x400118b2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_ORT2 +CYREG_B1_P4_U1_PLD_ORT2 EQU 0x400118b4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_ORT3 +CYREG_B1_P4_U1_PLD_ORT3 EQU 0x400118b6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_MC_CFG_CEN_CONST +CYREG_B1_P4_U1_MC_CFG_CEN_CONST EQU 0x400118b8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_MC_CFG_XORFB +CYREG_B1_P4_U1_MC_CFG_XORFB EQU 0x400118ba + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_MC_CFG_SET_RESET +CYREG_B1_P4_U1_MC_CFG_SET_RESET EQU 0x400118bc + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_MC_CFG_BYPASS +CYREG_B1_P4_U1_MC_CFG_BYPASS EQU 0x400118be + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG0 +CYREG_B1_P4_U1_CFG0 EQU 0x400118c0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG1 +CYREG_B1_P4_U1_CFG1 EQU 0x400118c1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG2 +CYREG_B1_P4_U1_CFG2 EQU 0x400118c2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG3 +CYREG_B1_P4_U1_CFG3 EQU 0x400118c3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG4 +CYREG_B1_P4_U1_CFG4 EQU 0x400118c4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG5 +CYREG_B1_P4_U1_CFG5 EQU 0x400118c5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG6 +CYREG_B1_P4_U1_CFG6 EQU 0x400118c6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG7 +CYREG_B1_P4_U1_CFG7 EQU 0x400118c7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG8 +CYREG_B1_P4_U1_CFG8 EQU 0x400118c8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG9 +CYREG_B1_P4_U1_CFG9 EQU 0x400118c9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG10 +CYREG_B1_P4_U1_CFG10 EQU 0x400118ca + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG11 +CYREG_B1_P4_U1_CFG11 EQU 0x400118cb + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG12 +CYREG_B1_P4_U1_CFG12 EQU 0x400118cc + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG13 +CYREG_B1_P4_U1_CFG13 EQU 0x400118cd + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG14 +CYREG_B1_P4_U1_CFG14 EQU 0x400118ce + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG15 +CYREG_B1_P4_U1_CFG15 EQU 0x400118cf + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG16 +CYREG_B1_P4_U1_CFG16 EQU 0x400118d0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG17 +CYREG_B1_P4_U1_CFG17 EQU 0x400118d1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG18 +CYREG_B1_P4_U1_CFG18 EQU 0x400118d2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG19 +CYREG_B1_P4_U1_CFG19 EQU 0x400118d3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG20 +CYREG_B1_P4_U1_CFG20 EQU 0x400118d4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG21 +CYREG_B1_P4_U1_CFG21 EQU 0x400118d5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG22 +CYREG_B1_P4_U1_CFG22 EQU 0x400118d6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG23 +CYREG_B1_P4_U1_CFG23 EQU 0x400118d7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG24 +CYREG_B1_P4_U1_CFG24 EQU 0x400118d8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG25 +CYREG_B1_P4_U1_CFG25 EQU 0x400118d9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG26 +CYREG_B1_P4_U1_CFG26 EQU 0x400118da + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG27 +CYREG_B1_P4_U1_CFG27 EQU 0x400118db + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG28 +CYREG_B1_P4_U1_CFG28 EQU 0x400118dc + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG29 +CYREG_B1_P4_U1_CFG29 EQU 0x400118dd + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG30 +CYREG_B1_P4_U1_CFG30 EQU 0x400118de + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG31 +CYREG_B1_P4_U1_CFG31 EQU 0x400118df + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG0 +CYREG_B1_P4_U1_DCFG0 EQU 0x400118e0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG1 +CYREG_B1_P4_U1_DCFG1 EQU 0x400118e2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG2 +CYREG_B1_P4_U1_DCFG2 EQU 0x400118e4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG3 +CYREG_B1_P4_U1_DCFG3 EQU 0x400118e6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG4 +CYREG_B1_P4_U1_DCFG4 EQU 0x400118e8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG5 +CYREG_B1_P4_U1_DCFG5 EQU 0x400118ea + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG6 +CYREG_B1_P4_U1_DCFG6 EQU 0x400118ec + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG7 +CYREG_B1_P4_U1_DCFG7 EQU 0x400118ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_ROUTE_BASE +CYDEV_UCFG_B1_P4_ROUTE_BASE EQU 0x40011900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_ROUTE_SIZE +CYDEV_UCFG_B1_P4_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_BASE +CYDEV_UCFG_B1_P5_BASE EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_SIZE +CYDEV_UCFG_B1_P5_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_BASE +CYDEV_UCFG_B1_P5_U0_BASE EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_SIZE +CYDEV_UCFG_B1_P5_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT0 +CYREG_B1_P5_U0_PLD_IT0 EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT1 +CYREG_B1_P5_U0_PLD_IT1 EQU 0x40011a04 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT2 +CYREG_B1_P5_U0_PLD_IT2 EQU 0x40011a08 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT3 +CYREG_B1_P5_U0_PLD_IT3 EQU 0x40011a0c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT4 +CYREG_B1_P5_U0_PLD_IT4 EQU 0x40011a10 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT5 +CYREG_B1_P5_U0_PLD_IT5 EQU 0x40011a14 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT6 +CYREG_B1_P5_U0_PLD_IT6 EQU 0x40011a18 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT7 +CYREG_B1_P5_U0_PLD_IT7 EQU 0x40011a1c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT8 +CYREG_B1_P5_U0_PLD_IT8 EQU 0x40011a20 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT9 +CYREG_B1_P5_U0_PLD_IT9 EQU 0x40011a24 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT10 +CYREG_B1_P5_U0_PLD_IT10 EQU 0x40011a28 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT11 +CYREG_B1_P5_U0_PLD_IT11 EQU 0x40011a2c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_ORT0 +CYREG_B1_P5_U0_PLD_ORT0 EQU 0x40011a30 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_ORT1 +CYREG_B1_P5_U0_PLD_ORT1 EQU 0x40011a32 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_ORT2 +CYREG_B1_P5_U0_PLD_ORT2 EQU 0x40011a34 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_ORT3 +CYREG_B1_P5_U0_PLD_ORT3 EQU 0x40011a36 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_MC_CFG_CEN_CONST +CYREG_B1_P5_U0_MC_CFG_CEN_CONST EQU 0x40011a38 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_MC_CFG_XORFB +CYREG_B1_P5_U0_MC_CFG_XORFB EQU 0x40011a3a + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_MC_CFG_SET_RESET +CYREG_B1_P5_U0_MC_CFG_SET_RESET EQU 0x40011a3c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_MC_CFG_BYPASS +CYREG_B1_P5_U0_MC_CFG_BYPASS EQU 0x40011a3e + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG0 +CYREG_B1_P5_U0_CFG0 EQU 0x40011a40 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG1 +CYREG_B1_P5_U0_CFG1 EQU 0x40011a41 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG2 +CYREG_B1_P5_U0_CFG2 EQU 0x40011a42 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG3 +CYREG_B1_P5_U0_CFG3 EQU 0x40011a43 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG4 +CYREG_B1_P5_U0_CFG4 EQU 0x40011a44 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG5 +CYREG_B1_P5_U0_CFG5 EQU 0x40011a45 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG6 +CYREG_B1_P5_U0_CFG6 EQU 0x40011a46 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG7 +CYREG_B1_P5_U0_CFG7 EQU 0x40011a47 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG8 +CYREG_B1_P5_U0_CFG8 EQU 0x40011a48 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG9 +CYREG_B1_P5_U0_CFG9 EQU 0x40011a49 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG10 +CYREG_B1_P5_U0_CFG10 EQU 0x40011a4a + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG11 +CYREG_B1_P5_U0_CFG11 EQU 0x40011a4b + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG12 +CYREG_B1_P5_U0_CFG12 EQU 0x40011a4c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG13 +CYREG_B1_P5_U0_CFG13 EQU 0x40011a4d + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG14 +CYREG_B1_P5_U0_CFG14 EQU 0x40011a4e + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG15 +CYREG_B1_P5_U0_CFG15 EQU 0x40011a4f + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG16 +CYREG_B1_P5_U0_CFG16 EQU 0x40011a50 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG17 +CYREG_B1_P5_U0_CFG17 EQU 0x40011a51 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG18 +CYREG_B1_P5_U0_CFG18 EQU 0x40011a52 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG19 +CYREG_B1_P5_U0_CFG19 EQU 0x40011a53 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG20 +CYREG_B1_P5_U0_CFG20 EQU 0x40011a54 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG21 +CYREG_B1_P5_U0_CFG21 EQU 0x40011a55 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG22 +CYREG_B1_P5_U0_CFG22 EQU 0x40011a56 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG23 +CYREG_B1_P5_U0_CFG23 EQU 0x40011a57 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG24 +CYREG_B1_P5_U0_CFG24 EQU 0x40011a58 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG25 +CYREG_B1_P5_U0_CFG25 EQU 0x40011a59 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG26 +CYREG_B1_P5_U0_CFG26 EQU 0x40011a5a + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG27 +CYREG_B1_P5_U0_CFG27 EQU 0x40011a5b + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG28 +CYREG_B1_P5_U0_CFG28 EQU 0x40011a5c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG29 +CYREG_B1_P5_U0_CFG29 EQU 0x40011a5d + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG30 +CYREG_B1_P5_U0_CFG30 EQU 0x40011a5e + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG31 +CYREG_B1_P5_U0_CFG31 EQU 0x40011a5f + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG0 +CYREG_B1_P5_U0_DCFG0 EQU 0x40011a60 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG1 +CYREG_B1_P5_U0_DCFG1 EQU 0x40011a62 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG2 +CYREG_B1_P5_U0_DCFG2 EQU 0x40011a64 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG3 +CYREG_B1_P5_U0_DCFG3 EQU 0x40011a66 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG4 +CYREG_B1_P5_U0_DCFG4 EQU 0x40011a68 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG5 +CYREG_B1_P5_U0_DCFG5 EQU 0x40011a6a + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG6 +CYREG_B1_P5_U0_DCFG6 EQU 0x40011a6c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG7 +CYREG_B1_P5_U0_DCFG7 EQU 0x40011a6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_BASE +CYDEV_UCFG_B1_P5_U1_BASE EQU 0x40011a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_SIZE +CYDEV_UCFG_B1_P5_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT0 +CYREG_B1_P5_U1_PLD_IT0 EQU 0x40011a80 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT1 +CYREG_B1_P5_U1_PLD_IT1 EQU 0x40011a84 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT2 +CYREG_B1_P5_U1_PLD_IT2 EQU 0x40011a88 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT3 +CYREG_B1_P5_U1_PLD_IT3 EQU 0x40011a8c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT4 +CYREG_B1_P5_U1_PLD_IT4 EQU 0x40011a90 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT5 +CYREG_B1_P5_U1_PLD_IT5 EQU 0x40011a94 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT6 +CYREG_B1_P5_U1_PLD_IT6 EQU 0x40011a98 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT7 +CYREG_B1_P5_U1_PLD_IT7 EQU 0x40011a9c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT8 +CYREG_B1_P5_U1_PLD_IT8 EQU 0x40011aa0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT9 +CYREG_B1_P5_U1_PLD_IT9 EQU 0x40011aa4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT10 +CYREG_B1_P5_U1_PLD_IT10 EQU 0x40011aa8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT11 +CYREG_B1_P5_U1_PLD_IT11 EQU 0x40011aac + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_ORT0 +CYREG_B1_P5_U1_PLD_ORT0 EQU 0x40011ab0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_ORT1 +CYREG_B1_P5_U1_PLD_ORT1 EQU 0x40011ab2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_ORT2 +CYREG_B1_P5_U1_PLD_ORT2 EQU 0x40011ab4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_ORT3 +CYREG_B1_P5_U1_PLD_ORT3 EQU 0x40011ab6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_MC_CFG_CEN_CONST +CYREG_B1_P5_U1_MC_CFG_CEN_CONST EQU 0x40011ab8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_MC_CFG_XORFB +CYREG_B1_P5_U1_MC_CFG_XORFB EQU 0x40011aba + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_MC_CFG_SET_RESET +CYREG_B1_P5_U1_MC_CFG_SET_RESET EQU 0x40011abc + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_MC_CFG_BYPASS +CYREG_B1_P5_U1_MC_CFG_BYPASS EQU 0x40011abe + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG0 +CYREG_B1_P5_U1_CFG0 EQU 0x40011ac0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG1 +CYREG_B1_P5_U1_CFG1 EQU 0x40011ac1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG2 +CYREG_B1_P5_U1_CFG2 EQU 0x40011ac2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG3 +CYREG_B1_P5_U1_CFG3 EQU 0x40011ac3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG4 +CYREG_B1_P5_U1_CFG4 EQU 0x40011ac4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG5 +CYREG_B1_P5_U1_CFG5 EQU 0x40011ac5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG6 +CYREG_B1_P5_U1_CFG6 EQU 0x40011ac6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG7 +CYREG_B1_P5_U1_CFG7 EQU 0x40011ac7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG8 +CYREG_B1_P5_U1_CFG8 EQU 0x40011ac8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG9 +CYREG_B1_P5_U1_CFG9 EQU 0x40011ac9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG10 +CYREG_B1_P5_U1_CFG10 EQU 0x40011aca + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG11 +CYREG_B1_P5_U1_CFG11 EQU 0x40011acb + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG12 +CYREG_B1_P5_U1_CFG12 EQU 0x40011acc + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG13 +CYREG_B1_P5_U1_CFG13 EQU 0x40011acd + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG14 +CYREG_B1_P5_U1_CFG14 EQU 0x40011ace + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG15 +CYREG_B1_P5_U1_CFG15 EQU 0x40011acf + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG16 +CYREG_B1_P5_U1_CFG16 EQU 0x40011ad0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG17 +CYREG_B1_P5_U1_CFG17 EQU 0x40011ad1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG18 +CYREG_B1_P5_U1_CFG18 EQU 0x40011ad2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG19 +CYREG_B1_P5_U1_CFG19 EQU 0x40011ad3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG20 +CYREG_B1_P5_U1_CFG20 EQU 0x40011ad4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG21 +CYREG_B1_P5_U1_CFG21 EQU 0x40011ad5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG22 +CYREG_B1_P5_U1_CFG22 EQU 0x40011ad6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG23 +CYREG_B1_P5_U1_CFG23 EQU 0x40011ad7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG24 +CYREG_B1_P5_U1_CFG24 EQU 0x40011ad8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG25 +CYREG_B1_P5_U1_CFG25 EQU 0x40011ad9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG26 +CYREG_B1_P5_U1_CFG26 EQU 0x40011ada + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG27 +CYREG_B1_P5_U1_CFG27 EQU 0x40011adb + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG28 +CYREG_B1_P5_U1_CFG28 EQU 0x40011adc + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG29 +CYREG_B1_P5_U1_CFG29 EQU 0x40011add + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG30 +CYREG_B1_P5_U1_CFG30 EQU 0x40011ade + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG31 +CYREG_B1_P5_U1_CFG31 EQU 0x40011adf + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG0 +CYREG_B1_P5_U1_DCFG0 EQU 0x40011ae0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG1 +CYREG_B1_P5_U1_DCFG1 EQU 0x40011ae2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG2 +CYREG_B1_P5_U1_DCFG2 EQU 0x40011ae4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG3 +CYREG_B1_P5_U1_DCFG3 EQU 0x40011ae6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG4 +CYREG_B1_P5_U1_DCFG4 EQU 0x40011ae8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG5 +CYREG_B1_P5_U1_DCFG5 EQU 0x40011aea + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG6 +CYREG_B1_P5_U1_DCFG6 EQU 0x40011aec + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG7 +CYREG_B1_P5_U1_DCFG7 EQU 0x40011aee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_ROUTE_BASE +CYDEV_UCFG_B1_P5_ROUTE_BASE EQU 0x40011b00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_ROUTE_SIZE +CYDEV_UCFG_B1_P5_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI0_BASE +CYDEV_UCFG_DSI0_BASE EQU 0x40014000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI0_SIZE +CYDEV_UCFG_DSI0_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI1_BASE +CYDEV_UCFG_DSI1_BASE EQU 0x40014100 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI1_SIZE +CYDEV_UCFG_DSI1_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI2_BASE +CYDEV_UCFG_DSI2_BASE EQU 0x40014200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI2_SIZE +CYDEV_UCFG_DSI2_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI3_BASE +CYDEV_UCFG_DSI3_BASE EQU 0x40014300 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI3_SIZE +CYDEV_UCFG_DSI3_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI4_BASE +CYDEV_UCFG_DSI4_BASE EQU 0x40014400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI4_SIZE +CYDEV_UCFG_DSI4_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI5_BASE +CYDEV_UCFG_DSI5_BASE EQU 0x40014500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI5_SIZE +CYDEV_UCFG_DSI5_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI6_BASE +CYDEV_UCFG_DSI6_BASE EQU 0x40014600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI6_SIZE +CYDEV_UCFG_DSI6_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI7_BASE +CYDEV_UCFG_DSI7_BASE EQU 0x40014700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI7_SIZE +CYDEV_UCFG_DSI7_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI8_BASE +CYDEV_UCFG_DSI8_BASE EQU 0x40014800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI8_SIZE +CYDEV_UCFG_DSI8_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI9_BASE +CYDEV_UCFG_DSI9_BASE EQU 0x40014900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI9_SIZE +CYDEV_UCFG_DSI9_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI12_BASE +CYDEV_UCFG_DSI12_BASE EQU 0x40014c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI12_SIZE +CYDEV_UCFG_DSI12_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI13_BASE +CYDEV_UCFG_DSI13_BASE EQU 0x40014d00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI13_SIZE +CYDEV_UCFG_DSI13_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BASE +CYDEV_UCFG_BCTL0_BASE EQU 0x40015000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_SIZE +CYDEV_UCFG_BCTL0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_MDCLK_EN +CYREG_BCTL0_MDCLK_EN EQU 0x40015000 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_MBCLK_EN +CYREG_BCTL0_MBCLK_EN EQU 0x40015001 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_WAIT_CFG +CYREG_BCTL0_WAIT_CFG EQU 0x40015002 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_BANK_CTL +CYREG_BCTL0_BANK_CTL EQU 0x40015003 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_UDB_TEST_3 +CYREG_BCTL0_UDB_TEST_3 EQU 0x40015007 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_DCLK_EN0 +CYREG_BCTL0_DCLK_EN0 EQU 0x40015008 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_BCLK_EN0 +CYREG_BCTL0_BCLK_EN0 EQU 0x40015009 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_DCLK_EN1 +CYREG_BCTL0_DCLK_EN1 EQU 0x4001500a + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_BCLK_EN1 +CYREG_BCTL0_BCLK_EN1 EQU 0x4001500b + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_DCLK_EN2 +CYREG_BCTL0_DCLK_EN2 EQU 0x4001500c + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_BCLK_EN2 +CYREG_BCTL0_BCLK_EN2 EQU 0x4001500d + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_DCLK_EN3 +CYREG_BCTL0_DCLK_EN3 EQU 0x4001500e + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_BCLK_EN3 +CYREG_BCTL0_BCLK_EN3 EQU 0x4001500f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BASE +CYDEV_UCFG_BCTL1_BASE EQU 0x40015010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_SIZE +CYDEV_UCFG_BCTL1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_MDCLK_EN +CYREG_BCTL1_MDCLK_EN EQU 0x40015010 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_MBCLK_EN +CYREG_BCTL1_MBCLK_EN EQU 0x40015011 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_WAIT_CFG +CYREG_BCTL1_WAIT_CFG EQU 0x40015012 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_BANK_CTL +CYREG_BCTL1_BANK_CTL EQU 0x40015013 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_UDB_TEST_3 +CYREG_BCTL1_UDB_TEST_3 EQU 0x40015017 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_DCLK_EN0 +CYREG_BCTL1_DCLK_EN0 EQU 0x40015018 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_BCLK_EN0 +CYREG_BCTL1_BCLK_EN0 EQU 0x40015019 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_DCLK_EN1 +CYREG_BCTL1_DCLK_EN1 EQU 0x4001501a + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_BCLK_EN1 +CYREG_BCTL1_BCLK_EN1 EQU 0x4001501b + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_DCLK_EN2 +CYREG_BCTL1_DCLK_EN2 EQU 0x4001501c + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_BCLK_EN2 +CYREG_BCTL1_BCLK_EN2 EQU 0x4001501d + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_DCLK_EN3 +CYREG_BCTL1_DCLK_EN3 EQU 0x4001501e + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_BCLK_EN3 +CYREG_BCTL1_BCLK_EN3 EQU 0x4001501f + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_BASE +CYDEV_IDMUX_BASE EQU 0x40015100 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_SIZE +CYDEV_IDMUX_SIZE EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL0 +CYREG_IDMUX_IRQ_CTL0 EQU 0x40015100 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL1 +CYREG_IDMUX_IRQ_CTL1 EQU 0x40015101 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL2 +CYREG_IDMUX_IRQ_CTL2 EQU 0x40015102 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL3 +CYREG_IDMUX_IRQ_CTL3 EQU 0x40015103 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL4 +CYREG_IDMUX_IRQ_CTL4 EQU 0x40015104 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL5 +CYREG_IDMUX_IRQ_CTL5 EQU 0x40015105 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL6 +CYREG_IDMUX_IRQ_CTL6 EQU 0x40015106 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL7 +CYREG_IDMUX_IRQ_CTL7 EQU 0x40015107 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL0 +CYREG_IDMUX_DRQ_CTL0 EQU 0x40015110 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL1 +CYREG_IDMUX_DRQ_CTL1 EQU 0x40015111 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL2 +CYREG_IDMUX_DRQ_CTL2 EQU 0x40015112 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL3 +CYREG_IDMUX_DRQ_CTL3 EQU 0x40015113 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL4 +CYREG_IDMUX_DRQ_CTL4 EQU 0x40015114 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL5 +CYREG_IDMUX_DRQ_CTL5 EQU 0x40015115 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_BASE +CYDEV_CACHERAM_BASE EQU 0x40030000 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_SIZE +CYDEV_CACHERAM_SIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYREG_CACHERAM_DATA_MBASE +CYREG_CACHERAM_DATA_MBASE EQU 0x40030000 + ENDIF + IF :LNOT::DEF:CYREG_CACHERAM_DATA_MSIZE +CYREG_CACHERAM_DATA_MSIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_BASE +CYDEV_SFR_BASE EQU 0x40050100 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_SIZE +CYDEV_SFR_SIZE EQU 0x000000fb + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO0 +CYREG_SFR_GPIO0 EQU 0x40050180 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD0 +CYREG_SFR_GPIRD0 EQU 0x40050189 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO0_SEL +CYREG_SFR_GPIO0_SEL EQU 0x4005018a + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO1 +CYREG_SFR_GPIO1 EQU 0x40050190 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD1 +CYREG_SFR_GPIRD1 EQU 0x40050191 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO2 +CYREG_SFR_GPIO2 EQU 0x40050198 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD2 +CYREG_SFR_GPIRD2 EQU 0x40050199 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO2_SEL +CYREG_SFR_GPIO2_SEL EQU 0x4005019a + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO1_SEL +CYREG_SFR_GPIO1_SEL EQU 0x400501a2 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO3 +CYREG_SFR_GPIO3 EQU 0x400501b0 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD3 +CYREG_SFR_GPIRD3 EQU 0x400501b1 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO3_SEL +CYREG_SFR_GPIO3_SEL EQU 0x400501b2 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO4 +CYREG_SFR_GPIO4 EQU 0x400501c0 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD4 +CYREG_SFR_GPIRD4 EQU 0x400501c1 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO4_SEL +CYREG_SFR_GPIO4_SEL EQU 0x400501c2 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO5 +CYREG_SFR_GPIO5 EQU 0x400501c8 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD5 +CYREG_SFR_GPIRD5 EQU 0x400501c9 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO5_SEL +CYREG_SFR_GPIO5_SEL EQU 0x400501ca + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO6 +CYREG_SFR_GPIO6 EQU 0x400501d8 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD6 +CYREG_SFR_GPIRD6 EQU 0x400501d9 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO6_SEL +CYREG_SFR_GPIO6_SEL EQU 0x400501da + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO12 +CYREG_SFR_GPIO12 EQU 0x400501e8 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD12 +CYREG_SFR_GPIRD12 EQU 0x400501e9 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO12_SEL +CYREG_SFR_GPIO12_SEL EQU 0x400501f2 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO15 +CYREG_SFR_GPIO15 EQU 0x400501f8 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD15 +CYREG_SFR_GPIRD15 EQU 0x400501f9 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO15_SEL +CYREG_SFR_GPIO15_SEL EQU 0x400501fa + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_BASE +CYDEV_P3BA_BASE EQU 0x40050300 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_SIZE +CYDEV_P3BA_SIZE EQU 0x0000002b + ENDIF + IF :LNOT::DEF:CYREG_P3BA_Y_START +CYREG_P3BA_Y_START EQU 0x40050300 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_YROLL +CYREG_P3BA_YROLL EQU 0x40050301 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_YCFG +CYREG_P3BA_YCFG EQU 0x40050302 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_X_START1 +CYREG_P3BA_X_START1 EQU 0x40050303 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_X_START2 +CYREG_P3BA_X_START2 EQU 0x40050304 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_XROLL1 +CYREG_P3BA_XROLL1 EQU 0x40050305 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_XROLL2 +CYREG_P3BA_XROLL2 EQU 0x40050306 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_XINC +CYREG_P3BA_XINC EQU 0x40050307 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_XCFG +CYREG_P3BA_XCFG EQU 0x40050308 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_OFFSETADDR1 +CYREG_P3BA_OFFSETADDR1 EQU 0x40050309 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_OFFSETADDR2 +CYREG_P3BA_OFFSETADDR2 EQU 0x4005030a + ENDIF + IF :LNOT::DEF:CYREG_P3BA_OFFSETADDR3 +CYREG_P3BA_OFFSETADDR3 EQU 0x4005030b + ENDIF + IF :LNOT::DEF:CYREG_P3BA_ABSADDR1 +CYREG_P3BA_ABSADDR1 EQU 0x4005030c + ENDIF + IF :LNOT::DEF:CYREG_P3BA_ABSADDR2 +CYREG_P3BA_ABSADDR2 EQU 0x4005030d + ENDIF + IF :LNOT::DEF:CYREG_P3BA_ABSADDR3 +CYREG_P3BA_ABSADDR3 EQU 0x4005030e + ENDIF + IF :LNOT::DEF:CYREG_P3BA_ABSADDR4 +CYREG_P3BA_ABSADDR4 EQU 0x4005030f + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATCFG1 +CYREG_P3BA_DATCFG1 EQU 0x40050310 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATCFG2 +CYREG_P3BA_DATCFG2 EQU 0x40050311 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_CMP_RSLT1 +CYREG_P3BA_CMP_RSLT1 EQU 0x40050314 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_CMP_RSLT2 +CYREG_P3BA_CMP_RSLT2 EQU 0x40050315 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_CMP_RSLT3 +CYREG_P3BA_CMP_RSLT3 EQU 0x40050316 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_CMP_RSLT4 +CYREG_P3BA_CMP_RSLT4 EQU 0x40050317 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATA_REG1 +CYREG_P3BA_DATA_REG1 EQU 0x40050318 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATA_REG2 +CYREG_P3BA_DATA_REG2 EQU 0x40050319 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATA_REG3 +CYREG_P3BA_DATA_REG3 EQU 0x4005031a + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATA_REG4 +CYREG_P3BA_DATA_REG4 EQU 0x4005031b + ENDIF + IF :LNOT::DEF:CYREG_P3BA_EXP_DATA1 +CYREG_P3BA_EXP_DATA1 EQU 0x4005031c + ENDIF + IF :LNOT::DEF:CYREG_P3BA_EXP_DATA2 +CYREG_P3BA_EXP_DATA2 EQU 0x4005031d + ENDIF + IF :LNOT::DEF:CYREG_P3BA_EXP_DATA3 +CYREG_P3BA_EXP_DATA3 EQU 0x4005031e + ENDIF + IF :LNOT::DEF:CYREG_P3BA_EXP_DATA4 +CYREG_P3BA_EXP_DATA4 EQU 0x4005031f + ENDIF + IF :LNOT::DEF:CYREG_P3BA_MSTR_HRDATA1 +CYREG_P3BA_MSTR_HRDATA1 EQU 0x40050320 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_MSTR_HRDATA2 +CYREG_P3BA_MSTR_HRDATA2 EQU 0x40050321 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_MSTR_HRDATA3 +CYREG_P3BA_MSTR_HRDATA3 EQU 0x40050322 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_MSTR_HRDATA4 +CYREG_P3BA_MSTR_HRDATA4 EQU 0x40050323 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_BIST_EN +CYREG_P3BA_BIST_EN EQU 0x40050324 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_PHUB_MASTER_SSR +CYREG_P3BA_PHUB_MASTER_SSR EQU 0x40050325 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_SEQCFG1 +CYREG_P3BA_SEQCFG1 EQU 0x40050326 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_SEQCFG2 +CYREG_P3BA_SEQCFG2 EQU 0x40050327 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_Y_CURR +CYREG_P3BA_Y_CURR EQU 0x40050328 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_X_CURR1 +CYREG_P3BA_X_CURR1 EQU 0x40050329 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_X_CURR2 +CYREG_P3BA_X_CURR2 EQU 0x4005032a + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_BASE +CYDEV_PANTHER_BASE EQU 0x40080000 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_SIZE +CYDEV_PANTHER_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_STCALIB_CFG +CYREG_PANTHER_STCALIB_CFG EQU 0x40080000 + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_WAITPIPE +CYREG_PANTHER_WAITPIPE EQU 0x40080004 + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_TRACE_CFG +CYREG_PANTHER_TRACE_CFG EQU 0x40080008 + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_DBG_CFG +CYREG_PANTHER_DBG_CFG EQU 0x4008000c + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_CM3_LCKRST_STAT +CYREG_PANTHER_CM3_LCKRST_STAT EQU 0x40080018 + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_DEVICE_ID +CYREG_PANTHER_DEVICE_ID EQU 0x4008001c + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_BASE +CYDEV_FLSECC_BASE EQU 0x48000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_SIZE +CYDEV_FLSECC_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYREG_FLSECC_DATA_MBASE +CYREG_FLSECC_DATA_MBASE EQU 0x48000000 + ENDIF + IF :LNOT::DEF:CYREG_FLSECC_DATA_MSIZE +CYREG_FLSECC_DATA_MSIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_BASE +CYDEV_FLSHID_BASE EQU 0x49000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_SIZE +CYDEV_FLSHID_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_RSVD_MBASE +CYREG_FLSHID_RSVD_MBASE EQU 0x49000000 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_RSVD_MSIZE +CYREG_FLSHID_RSVD_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_MDATA_MBASE +CYREG_FLSHID_CUST_MDATA_MBASE EQU 0x49000080 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_MDATA_MSIZE +CYREG_FLSHID_CUST_MDATA_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_BASE +CYDEV_FLSHID_CUST_TABLES_BASE EQU 0x49000100 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_SIZE +CYDEV_FLSHID_CUST_TABLES_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_Y_LOC +CYREG_FLSHID_CUST_TABLES_Y_LOC EQU 0x49000100 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_X_LOC +CYREG_FLSHID_CUST_TABLES_X_LOC EQU 0x49000101 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_WAFER_NUM +CYREG_FLSHID_CUST_TABLES_WAFER_NUM EQU 0x49000102 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_LOT_LSB +CYREG_FLSHID_CUST_TABLES_LOT_LSB EQU 0x49000103 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_LOT_MSB +CYREG_FLSHID_CUST_TABLES_LOT_MSB EQU 0x49000104 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_WRK_WK +CYREG_FLSHID_CUST_TABLES_WRK_WK EQU 0x49000105 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_FAB_YR +CYREG_FLSHID_CUST_TABLES_FAB_YR EQU 0x49000106 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_MINOR +CYREG_FLSHID_CUST_TABLES_MINOR EQU 0x49000107 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_3MHZ +CYREG_FLSHID_CUST_TABLES_IMO_3MHZ EQU 0x49000108 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_6MHZ +CYREG_FLSHID_CUST_TABLES_IMO_6MHZ EQU 0x49000109 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_12MHZ +CYREG_FLSHID_CUST_TABLES_IMO_12MHZ EQU 0x4900010a + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_24MHZ +CYREG_FLSHID_CUST_TABLES_IMO_24MHZ EQU 0x4900010b + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_67MHZ +CYREG_FLSHID_CUST_TABLES_IMO_67MHZ EQU 0x4900010c + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_80MHZ +CYREG_FLSHID_CUST_TABLES_IMO_80MHZ EQU 0x4900010d + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_92MHZ +CYREG_FLSHID_CUST_TABLES_IMO_92MHZ EQU 0x4900010e + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_USB +CYREG_FLSHID_CUST_TABLES_IMO_USB EQU 0x4900010f + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS +CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS EQU 0x49000110 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS +CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS EQU 0x49000111 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS +CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS EQU 0x49000112 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS +CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS EQU 0x49000113 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS +CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS EQU 0x49000114 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS +CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS EQU 0x49000115 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS +CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS EQU 0x49000116 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS +CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS EQU 0x49000117 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M1 +CYREG_FLSHID_CUST_TABLES_DEC_M1 EQU 0x49000118 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M2 +CYREG_FLSHID_CUST_TABLES_DEC_M2 EQU 0x49000119 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M3 +CYREG_FLSHID_CUST_TABLES_DEC_M3 EQU 0x4900011a + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M4 +CYREG_FLSHID_CUST_TABLES_DEC_M4 EQU 0x4900011b + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M5 +CYREG_FLSHID_CUST_TABLES_DEC_M5 EQU 0x4900011c + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M6 +CYREG_FLSHID_CUST_TABLES_DEC_M6 EQU 0x4900011d + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M7 +CYREG_FLSHID_CUST_TABLES_DEC_M7 EQU 0x4900011e + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M8 +CYREG_FLSHID_CUST_TABLES_DEC_M8 EQU 0x4900011f + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M1 +CYREG_FLSHID_CUST_TABLES_DAC0_M1 EQU 0x49000120 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M2 +CYREG_FLSHID_CUST_TABLES_DAC0_M2 EQU 0x49000121 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M3 +CYREG_FLSHID_CUST_TABLES_DAC0_M3 EQU 0x49000122 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M4 +CYREG_FLSHID_CUST_TABLES_DAC0_M4 EQU 0x49000123 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M5 +CYREG_FLSHID_CUST_TABLES_DAC0_M5 EQU 0x49000124 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M6 +CYREG_FLSHID_CUST_TABLES_DAC0_M6 EQU 0x49000125 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M7 +CYREG_FLSHID_CUST_TABLES_DAC0_M7 EQU 0x49000126 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M8 +CYREG_FLSHID_CUST_TABLES_DAC0_M8 EQU 0x49000127 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M1 +CYREG_FLSHID_CUST_TABLES_DAC2_M1 EQU 0x49000128 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M2 +CYREG_FLSHID_CUST_TABLES_DAC2_M2 EQU 0x49000129 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M3 +CYREG_FLSHID_CUST_TABLES_DAC2_M3 EQU 0x4900012a + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M4 +CYREG_FLSHID_CUST_TABLES_DAC2_M4 EQU 0x4900012b + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M5 +CYREG_FLSHID_CUST_TABLES_DAC2_M5 EQU 0x4900012c + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M6 +CYREG_FLSHID_CUST_TABLES_DAC2_M6 EQU 0x4900012d + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M7 +CYREG_FLSHID_CUST_TABLES_DAC2_M7 EQU 0x4900012e + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M8 +CYREG_FLSHID_CUST_TABLES_DAC2_M8 EQU 0x4900012f + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M1 +CYREG_FLSHID_CUST_TABLES_DAC1_M1 EQU 0x49000130 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M2 +CYREG_FLSHID_CUST_TABLES_DAC1_M2 EQU 0x49000131 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M3 +CYREG_FLSHID_CUST_TABLES_DAC1_M3 EQU 0x49000132 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M4 +CYREG_FLSHID_CUST_TABLES_DAC1_M4 EQU 0x49000133 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M5 +CYREG_FLSHID_CUST_TABLES_DAC1_M5 EQU 0x49000134 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M6 +CYREG_FLSHID_CUST_TABLES_DAC1_M6 EQU 0x49000135 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M7 +CYREG_FLSHID_CUST_TABLES_DAC1_M7 EQU 0x49000136 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M8 +CYREG_FLSHID_CUST_TABLES_DAC1_M8 EQU 0x49000137 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M1 +CYREG_FLSHID_CUST_TABLES_DAC3_M1 EQU 0x49000138 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M2 +CYREG_FLSHID_CUST_TABLES_DAC3_M2 EQU 0x49000139 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M3 +CYREG_FLSHID_CUST_TABLES_DAC3_M3 EQU 0x4900013a + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M4 +CYREG_FLSHID_CUST_TABLES_DAC3_M4 EQU 0x4900013b + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M5 +CYREG_FLSHID_CUST_TABLES_DAC3_M5 EQU 0x4900013c + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M6 +CYREG_FLSHID_CUST_TABLES_DAC3_M6 EQU 0x4900013d + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M7 +CYREG_FLSHID_CUST_TABLES_DAC3_M7 EQU 0x4900013e + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M8 +CYREG_FLSHID_CUST_TABLES_DAC3_M8 EQU 0x4900013f + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_BASE +CYDEV_FLSHID_MFG_CFG_BASE EQU 0x49000180 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_SIZE +CYDEV_FLSHID_MFG_CFG_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_IMO_TR1 +CYREG_FLSHID_MFG_CFG_IMO_TR1 EQU 0x49000188 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP0_TR0 +CYREG_FLSHID_MFG_CFG_CMP0_TR0 EQU 0x490001ac + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP1_TR0 +CYREG_FLSHID_MFG_CFG_CMP1_TR0 EQU 0x490001ae + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP2_TR0 +CYREG_FLSHID_MFG_CFG_CMP2_TR0 EQU 0x490001b0 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP3_TR0 +CYREG_FLSHID_MFG_CFG_CMP3_TR0 EQU 0x490001b2 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP0_TR1 +CYREG_FLSHID_MFG_CFG_CMP0_TR1 EQU 0x490001b4 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP1_TR1 +CYREG_FLSHID_MFG_CFG_CMP1_TR1 EQU 0x490001b6 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP2_TR1 +CYREG_FLSHID_MFG_CFG_CMP2_TR1 EQU 0x490001b8 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP3_TR1 +CYREG_FLSHID_MFG_CFG_CMP3_TR1 EQU 0x490001ba + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM +CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM EQU 0x490001ce + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_BASE +CYDEV_EXTMEM_BASE EQU 0x60000000 + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_SIZE +CYDEV_EXTMEM_SIZE EQU 0x00800000 + ENDIF + IF :LNOT::DEF:CYREG_EXTMEM_DATA_MBASE +CYREG_EXTMEM_DATA_MBASE EQU 0x60000000 + ENDIF + IF :LNOT::DEF:CYREG_EXTMEM_DATA_MSIZE +CYREG_EXTMEM_DATA_MSIZE EQU 0x00800000 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_BASE +CYDEV_ITM_BASE EQU 0xe0000000 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_SIZE +CYDEV_ITM_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_ITM_TRACE_EN +CYREG_ITM_TRACE_EN EQU 0xe0000e00 + ENDIF + IF :LNOT::DEF:CYREG_ITM_TRACE_PRIVILEGE +CYREG_ITM_TRACE_PRIVILEGE EQU 0xe0000e40 + ENDIF + IF :LNOT::DEF:CYREG_ITM_TRACE_CTRL +CYREG_ITM_TRACE_CTRL EQU 0xe0000e80 + ENDIF + IF :LNOT::DEF:CYREG_ITM_LOCK_ACCESS +CYREG_ITM_LOCK_ACCESS EQU 0xe0000fb0 + ENDIF + IF :LNOT::DEF:CYREG_ITM_LOCK_STATUS +CYREG_ITM_LOCK_STATUS EQU 0xe0000fb4 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID4 +CYREG_ITM_PID4 EQU 0xe0000fd0 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID5 +CYREG_ITM_PID5 EQU 0xe0000fd4 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID6 +CYREG_ITM_PID6 EQU 0xe0000fd8 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID7 +CYREG_ITM_PID7 EQU 0xe0000fdc + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID0 +CYREG_ITM_PID0 EQU 0xe0000fe0 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID1 +CYREG_ITM_PID1 EQU 0xe0000fe4 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID2 +CYREG_ITM_PID2 EQU 0xe0000fe8 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID3 +CYREG_ITM_PID3 EQU 0xe0000fec + ENDIF + IF :LNOT::DEF:CYREG_ITM_CID0 +CYREG_ITM_CID0 EQU 0xe0000ff0 + ENDIF + IF :LNOT::DEF:CYREG_ITM_CID1 +CYREG_ITM_CID1 EQU 0xe0000ff4 + ENDIF + IF :LNOT::DEF:CYREG_ITM_CID2 +CYREG_ITM_CID2 EQU 0xe0000ff8 + ENDIF + IF :LNOT::DEF:CYREG_ITM_CID3 +CYREG_ITM_CID3 EQU 0xe0000ffc + ENDIF + IF :LNOT::DEF:CYDEV_DWT_BASE +CYDEV_DWT_BASE EQU 0xe0001000 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_SIZE +CYDEV_DWT_SIZE EQU 0x0000005c + ENDIF + IF :LNOT::DEF:CYREG_DWT_CTRL +CYREG_DWT_CTRL EQU 0xe0001000 + ENDIF + IF :LNOT::DEF:CYREG_DWT_CYCLE_COUNT +CYREG_DWT_CYCLE_COUNT EQU 0xe0001004 + ENDIF + IF :LNOT::DEF:CYREG_DWT_CPI_COUNT +CYREG_DWT_CPI_COUNT EQU 0xe0001008 + ENDIF + IF :LNOT::DEF:CYREG_DWT_EXC_OVHD_COUNT +CYREG_DWT_EXC_OVHD_COUNT EQU 0xe000100c + ENDIF + IF :LNOT::DEF:CYREG_DWT_SLEEP_COUNT +CYREG_DWT_SLEEP_COUNT EQU 0xe0001010 + ENDIF + IF :LNOT::DEF:CYREG_DWT_LSU_COUNT +CYREG_DWT_LSU_COUNT EQU 0xe0001014 + ENDIF + IF :LNOT::DEF:CYREG_DWT_FOLD_COUNT +CYREG_DWT_FOLD_COUNT EQU 0xe0001018 + ENDIF + IF :LNOT::DEF:CYREG_DWT_PC_SAMPLE +CYREG_DWT_PC_SAMPLE EQU 0xe000101c + ENDIF + IF :LNOT::DEF:CYREG_DWT_COMP_0 +CYREG_DWT_COMP_0 EQU 0xe0001020 + ENDIF + IF :LNOT::DEF:CYREG_DWT_MASK_0 +CYREG_DWT_MASK_0 EQU 0xe0001024 + ENDIF + IF :LNOT::DEF:CYREG_DWT_FUNCTION_0 +CYREG_DWT_FUNCTION_0 EQU 0xe0001028 + ENDIF + IF :LNOT::DEF:CYREG_DWT_COMP_1 +CYREG_DWT_COMP_1 EQU 0xe0001030 + ENDIF + IF :LNOT::DEF:CYREG_DWT_MASK_1 +CYREG_DWT_MASK_1 EQU 0xe0001034 + ENDIF + IF :LNOT::DEF:CYREG_DWT_FUNCTION_1 +CYREG_DWT_FUNCTION_1 EQU 0xe0001038 + ENDIF + IF :LNOT::DEF:CYREG_DWT_COMP_2 +CYREG_DWT_COMP_2 EQU 0xe0001040 + ENDIF + IF :LNOT::DEF:CYREG_DWT_MASK_2 +CYREG_DWT_MASK_2 EQU 0xe0001044 + ENDIF + IF :LNOT::DEF:CYREG_DWT_FUNCTION_2 +CYREG_DWT_FUNCTION_2 EQU 0xe0001048 + ENDIF + IF :LNOT::DEF:CYREG_DWT_COMP_3 +CYREG_DWT_COMP_3 EQU 0xe0001050 + ENDIF + IF :LNOT::DEF:CYREG_DWT_MASK_3 +CYREG_DWT_MASK_3 EQU 0xe0001054 + ENDIF + IF :LNOT::DEF:CYREG_DWT_FUNCTION_3 +CYREG_DWT_FUNCTION_3 EQU 0xe0001058 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_BASE +CYDEV_FPB_BASE EQU 0xe0002000 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_SIZE +CYDEV_FPB_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_FPB_CTRL +CYREG_FPB_CTRL EQU 0xe0002000 + ENDIF + IF :LNOT::DEF:CYREG_FPB_REMAP +CYREG_FPB_REMAP EQU 0xe0002004 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_0 +CYREG_FPB_FP_COMP_0 EQU 0xe0002008 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_1 +CYREG_FPB_FP_COMP_1 EQU 0xe000200c + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_2 +CYREG_FPB_FP_COMP_2 EQU 0xe0002010 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_3 +CYREG_FPB_FP_COMP_3 EQU 0xe0002014 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_4 +CYREG_FPB_FP_COMP_4 EQU 0xe0002018 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_5 +CYREG_FPB_FP_COMP_5 EQU 0xe000201c + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_6 +CYREG_FPB_FP_COMP_6 EQU 0xe0002020 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_7 +CYREG_FPB_FP_COMP_7 EQU 0xe0002024 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID4 +CYREG_FPB_PID4 EQU 0xe0002fd0 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID5 +CYREG_FPB_PID5 EQU 0xe0002fd4 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID6 +CYREG_FPB_PID6 EQU 0xe0002fd8 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID7 +CYREG_FPB_PID7 EQU 0xe0002fdc + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID0 +CYREG_FPB_PID0 EQU 0xe0002fe0 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID1 +CYREG_FPB_PID1 EQU 0xe0002fe4 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID2 +CYREG_FPB_PID2 EQU 0xe0002fe8 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID3 +CYREG_FPB_PID3 EQU 0xe0002fec + ENDIF + IF :LNOT::DEF:CYREG_FPB_CID0 +CYREG_FPB_CID0 EQU 0xe0002ff0 + ENDIF + IF :LNOT::DEF:CYREG_FPB_CID1 +CYREG_FPB_CID1 EQU 0xe0002ff4 + ENDIF + IF :LNOT::DEF:CYREG_FPB_CID2 +CYREG_FPB_CID2 EQU 0xe0002ff8 + ENDIF + IF :LNOT::DEF:CYREG_FPB_CID3 +CYREG_FPB_CID3 EQU 0xe0002ffc + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_BASE +CYDEV_NVIC_BASE EQU 0xe000e000 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SIZE +CYDEV_NVIC_SIZE EQU 0x00000d3c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_INT_CTL_TYPE +CYREG_NVIC_INT_CTL_TYPE EQU 0xe000e004 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYSTICK_CTL +CYREG_NVIC_SYSTICK_CTL EQU 0xe000e010 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYSTICK_RELOAD +CYREG_NVIC_SYSTICK_RELOAD EQU 0xe000e014 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYSTICK_CURRENT +CYREG_NVIC_SYSTICK_CURRENT EQU 0xe000e018 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYSTICK_CAL +CYREG_NVIC_SYSTICK_CAL EQU 0xe000e01c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SETENA0 +CYREG_NVIC_SETENA0 EQU 0xe000e100 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_CLRENA0 +CYREG_NVIC_CLRENA0 EQU 0xe000e180 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SETPEND0 +CYREG_NVIC_SETPEND0 EQU 0xe000e200 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_CLRPEND0 +CYREG_NVIC_CLRPEND0 EQU 0xe000e280 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_ACTIVE0 +CYREG_NVIC_ACTIVE0 EQU 0xe000e300 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_0 +CYREG_NVIC_PRI_0 EQU 0xe000e400 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_1 +CYREG_NVIC_PRI_1 EQU 0xe000e401 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_2 +CYREG_NVIC_PRI_2 EQU 0xe000e402 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_3 +CYREG_NVIC_PRI_3 EQU 0xe000e403 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_4 +CYREG_NVIC_PRI_4 EQU 0xe000e404 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_5 +CYREG_NVIC_PRI_5 EQU 0xe000e405 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_6 +CYREG_NVIC_PRI_6 EQU 0xe000e406 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_7 +CYREG_NVIC_PRI_7 EQU 0xe000e407 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_8 +CYREG_NVIC_PRI_8 EQU 0xe000e408 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_9 +CYREG_NVIC_PRI_9 EQU 0xe000e409 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_10 +CYREG_NVIC_PRI_10 EQU 0xe000e40a + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_11 +CYREG_NVIC_PRI_11 EQU 0xe000e40b + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_12 +CYREG_NVIC_PRI_12 EQU 0xe000e40c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_13 +CYREG_NVIC_PRI_13 EQU 0xe000e40d + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_14 +CYREG_NVIC_PRI_14 EQU 0xe000e40e + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_15 +CYREG_NVIC_PRI_15 EQU 0xe000e40f + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_16 +CYREG_NVIC_PRI_16 EQU 0xe000e410 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_17 +CYREG_NVIC_PRI_17 EQU 0xe000e411 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_18 +CYREG_NVIC_PRI_18 EQU 0xe000e412 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_19 +CYREG_NVIC_PRI_19 EQU 0xe000e413 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_20 +CYREG_NVIC_PRI_20 EQU 0xe000e414 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_21 +CYREG_NVIC_PRI_21 EQU 0xe000e415 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_22 +CYREG_NVIC_PRI_22 EQU 0xe000e416 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_23 +CYREG_NVIC_PRI_23 EQU 0xe000e417 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_24 +CYREG_NVIC_PRI_24 EQU 0xe000e418 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_25 +CYREG_NVIC_PRI_25 EQU 0xe000e419 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_26 +CYREG_NVIC_PRI_26 EQU 0xe000e41a + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_27 +CYREG_NVIC_PRI_27 EQU 0xe000e41b + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_28 +CYREG_NVIC_PRI_28 EQU 0xe000e41c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_29 +CYREG_NVIC_PRI_29 EQU 0xe000e41d + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_30 +CYREG_NVIC_PRI_30 EQU 0xe000e41e + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_31 +CYREG_NVIC_PRI_31 EQU 0xe000e41f + ENDIF + IF :LNOT::DEF:CYREG_NVIC_CPUID_BASE +CYREG_NVIC_CPUID_BASE EQU 0xe000ed00 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_INTR_CTRL_STATE +CYREG_NVIC_INTR_CTRL_STATE EQU 0xe000ed04 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_VECT_OFFSET +CYREG_NVIC_VECT_OFFSET EQU 0xe000ed08 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_APPLN_INTR +CYREG_NVIC_APPLN_INTR EQU 0xe000ed0c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYSTEM_CONTROL +CYREG_NVIC_SYSTEM_CONTROL EQU 0xe000ed10 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_CFG_CONTROL +CYREG_NVIC_CFG_CONTROL EQU 0xe000ed14 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYS_PRIO_HANDLER_4_7 +CYREG_NVIC_SYS_PRIO_HANDLER_4_7 EQU 0xe000ed18 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYS_PRIO_HANDLER_8_11 +CYREG_NVIC_SYS_PRIO_HANDLER_8_11 EQU 0xe000ed1c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYS_PRIO_HANDLER_12_15 +CYREG_NVIC_SYS_PRIO_HANDLER_12_15 EQU 0xe000ed20 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYS_HANDLER_CSR +CYREG_NVIC_SYS_HANDLER_CSR EQU 0xe000ed24 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_MEMMAN_FAULT_STATUS +CYREG_NVIC_MEMMAN_FAULT_STATUS EQU 0xe000ed28 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_BUS_FAULT_STATUS +CYREG_NVIC_BUS_FAULT_STATUS EQU 0xe000ed29 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_USAGE_FAULT_STATUS +CYREG_NVIC_USAGE_FAULT_STATUS EQU 0xe000ed2a + ENDIF + IF :LNOT::DEF:CYREG_NVIC_HARD_FAULT_STATUS +CYREG_NVIC_HARD_FAULT_STATUS EQU 0xe000ed2c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_DEBUG_FAULT_STATUS +CYREG_NVIC_DEBUG_FAULT_STATUS EQU 0xe000ed30 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_MEMMAN_FAULT_ADD +CYREG_NVIC_MEMMAN_FAULT_ADD EQU 0xe000ed34 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_BUS_FAULT_ADD +CYREG_NVIC_BUS_FAULT_ADD EQU 0xe000ed38 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_BASE +CYDEV_CORE_DBG_BASE EQU 0xe000edf0 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_SIZE +CYDEV_CORE_DBG_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CORE_DBG_DBG_HLT_CS +CYREG_CORE_DBG_DBG_HLT_CS EQU 0xe000edf0 + ENDIF + IF :LNOT::DEF:CYREG_CORE_DBG_DBG_REG_SEL +CYREG_CORE_DBG_DBG_REG_SEL EQU 0xe000edf4 + ENDIF + IF :LNOT::DEF:CYREG_CORE_DBG_DBG_REG_DATA +CYREG_CORE_DBG_DBG_REG_DATA EQU 0xe000edf8 + ENDIF + IF :LNOT::DEF:CYREG_CORE_DBG_EXC_MON_CTL +CYREG_CORE_DBG_EXC_MON_CTL EQU 0xe000edfc + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_BASE +CYDEV_TPIU_BASE EQU 0xe0040000 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_SIZE +CYDEV_TPIU_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ +CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ EQU 0xe0040000 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_CURRENT_SYNC_PRT_SZ +CYREG_TPIU_CURRENT_SYNC_PRT_SZ EQU 0xe0040004 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ASYNC_CLK_PRESCALER +CYREG_TPIU_ASYNC_CLK_PRESCALER EQU 0xe0040010 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PROTOCOL +CYREG_TPIU_PROTOCOL EQU 0xe00400f0 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_FORM_FLUSH_STAT +CYREG_TPIU_FORM_FLUSH_STAT EQU 0xe0040300 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_FORM_FLUSH_CTRL +CYREG_TPIU_FORM_FLUSH_CTRL EQU 0xe0040304 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_TRIGGER +CYREG_TPIU_TRIGGER EQU 0xe0040ee8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ITETMDATA +CYREG_TPIU_ITETMDATA EQU 0xe0040eec + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ITATBCTR2 +CYREG_TPIU_ITATBCTR2 EQU 0xe0040ef0 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ITATBCTR0 +CYREG_TPIU_ITATBCTR0 EQU 0xe0040ef8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ITITMDATA +CYREG_TPIU_ITITMDATA EQU 0xe0040efc + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ITCTRL +CYREG_TPIU_ITCTRL EQU 0xe0040f00 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_DEVID +CYREG_TPIU_DEVID EQU 0xe0040fc8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_DEVTYPE +CYREG_TPIU_DEVTYPE EQU 0xe0040fcc + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID4 +CYREG_TPIU_PID4 EQU 0xe0040fd0 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID5 +CYREG_TPIU_PID5 EQU 0xe0040fd4 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID6 +CYREG_TPIU_PID6 EQU 0xe0040fd8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID7 +CYREG_TPIU_PID7 EQU 0xe0040fdc + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID0 +CYREG_TPIU_PID0 EQU 0xe0040fe0 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID1 +CYREG_TPIU_PID1 EQU 0xe0040fe4 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID2 +CYREG_TPIU_PID2 EQU 0xe0040fe8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID3 +CYREG_TPIU_PID3 EQU 0xe0040fec + ENDIF + IF :LNOT::DEF:CYREG_TPIU_CID0 +CYREG_TPIU_CID0 EQU 0xe0040ff0 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_CID1 +CYREG_TPIU_CID1 EQU 0xe0040ff4 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_CID2 +CYREG_TPIU_CID2 EQU 0xe0040ff8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_CID3 +CYREG_TPIU_CID3 EQU 0xe0040ffc + ENDIF + IF :LNOT::DEF:CYDEV_ETM_BASE +CYDEV_ETM_BASE EQU 0xe0041000 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_SIZE +CYDEV_ETM_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CTL +CYREG_ETM_CTL EQU 0xe0041000 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CFG_CODE +CYREG_ETM_CFG_CODE EQU 0xe0041004 + ENDIF + IF :LNOT::DEF:CYREG_ETM_TRIG_EVENT +CYREG_ETM_TRIG_EVENT EQU 0xe0041008 + ENDIF + IF :LNOT::DEF:CYREG_ETM_STATUS +CYREG_ETM_STATUS EQU 0xe0041010 + ENDIF + IF :LNOT::DEF:CYREG_ETM_SYS_CFG +CYREG_ETM_SYS_CFG EQU 0xe0041014 + ENDIF + IF :LNOT::DEF:CYREG_ETM_TRACE_ENB_EVENT +CYREG_ETM_TRACE_ENB_EVENT EQU 0xe0041020 + ENDIF + IF :LNOT::DEF:CYREG_ETM_TRACE_EN_CTRL1 +CYREG_ETM_TRACE_EN_CTRL1 EQU 0xe0041024 + ENDIF + IF :LNOT::DEF:CYREG_ETM_FIFOFULL_LEVEL +CYREG_ETM_FIFOFULL_LEVEL EQU 0xe004102c + ENDIF + IF :LNOT::DEF:CYREG_ETM_SYNC_FREQ +CYREG_ETM_SYNC_FREQ EQU 0xe00411e0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_ETM_ID +CYREG_ETM_ETM_ID EQU 0xe00411e4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CFG_CODE_EXT +CYREG_ETM_CFG_CODE_EXT EQU 0xe00411e8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_TR_SS_EMBICE_CTRL +CYREG_ETM_TR_SS_EMBICE_CTRL EQU 0xe00411f0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CS_TRACE_ID +CYREG_ETM_CS_TRACE_ID EQU 0xe0041200 + ENDIF + IF :LNOT::DEF:CYREG_ETM_OS_LOCK_ACCESS +CYREG_ETM_OS_LOCK_ACCESS EQU 0xe0041300 + ENDIF + IF :LNOT::DEF:CYREG_ETM_OS_LOCK_STATUS +CYREG_ETM_OS_LOCK_STATUS EQU 0xe0041304 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PDSR +CYREG_ETM_PDSR EQU 0xe0041314 + ENDIF + IF :LNOT::DEF:CYREG_ETM_ITMISCIN +CYREG_ETM_ITMISCIN EQU 0xe0041ee0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_ITTRIGOUT +CYREG_ETM_ITTRIGOUT EQU 0xe0041ee8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_ITATBCTR2 +CYREG_ETM_ITATBCTR2 EQU 0xe0041ef0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_ITATBCTR0 +CYREG_ETM_ITATBCTR0 EQU 0xe0041ef8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_INT_MODE_CTRL +CYREG_ETM_INT_MODE_CTRL EQU 0xe0041f00 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CLM_TAG_SET +CYREG_ETM_CLM_TAG_SET EQU 0xe0041fa0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CLM_TAG_CLR +CYREG_ETM_CLM_TAG_CLR EQU 0xe0041fa4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_LOCK_ACCESS +CYREG_ETM_LOCK_ACCESS EQU 0xe0041fb0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_LOCK_STATUS +CYREG_ETM_LOCK_STATUS EQU 0xe0041fb4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_AUTH_STATUS +CYREG_ETM_AUTH_STATUS EQU 0xe0041fb8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_DEV_TYPE +CYREG_ETM_DEV_TYPE EQU 0xe0041fcc + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID4 +CYREG_ETM_PID4 EQU 0xe0041fd0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID5 +CYREG_ETM_PID5 EQU 0xe0041fd4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID6 +CYREG_ETM_PID6 EQU 0xe0041fd8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID7 +CYREG_ETM_PID7 EQU 0xe0041fdc + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID0 +CYREG_ETM_PID0 EQU 0xe0041fe0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID1 +CYREG_ETM_PID1 EQU 0xe0041fe4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID2 +CYREG_ETM_PID2 EQU 0xe0041fe8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID3 +CYREG_ETM_PID3 EQU 0xe0041fec + ENDIF + IF :LNOT::DEF:CYREG_ETM_CID0 +CYREG_ETM_CID0 EQU 0xe0041ff0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CID1 +CYREG_ETM_CID1 EQU 0xe0041ff4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CID2 +CYREG_ETM_CID2 EQU 0xe0041ff8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CID3 +CYREG_ETM_CID3 EQU 0xe0041ffc + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_BASE +CYDEV_ROM_TABLE_BASE EQU 0xe00ff000 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_SIZE +CYDEV_ROM_TABLE_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_NVIC +CYREG_ROM_TABLE_NVIC EQU 0xe00ff000 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_DWT +CYREG_ROM_TABLE_DWT EQU 0xe00ff004 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_FPB +CYREG_ROM_TABLE_FPB EQU 0xe00ff008 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_ITM +CYREG_ROM_TABLE_ITM EQU 0xe00ff00c + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_TPIU +CYREG_ROM_TABLE_TPIU EQU 0xe00ff010 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_ETM +CYREG_ROM_TABLE_ETM EQU 0xe00ff014 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_END +CYREG_ROM_TABLE_END EQU 0xe00ff018 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_MEMTYPE +CYREG_ROM_TABLE_MEMTYPE EQU 0xe00fffcc + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID4 +CYREG_ROM_TABLE_PID4 EQU 0xe00fffd0 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID5 +CYREG_ROM_TABLE_PID5 EQU 0xe00fffd4 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID6 +CYREG_ROM_TABLE_PID6 EQU 0xe00fffd8 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID7 +CYREG_ROM_TABLE_PID7 EQU 0xe00fffdc + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID0 +CYREG_ROM_TABLE_PID0 EQU 0xe00fffe0 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID1 +CYREG_ROM_TABLE_PID1 EQU 0xe00fffe4 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID2 +CYREG_ROM_TABLE_PID2 EQU 0xe00fffe8 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID3 +CYREG_ROM_TABLE_PID3 EQU 0xe00fffec + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_CID0 +CYREG_ROM_TABLE_CID0 EQU 0xe00ffff0 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_CID1 +CYREG_ROM_TABLE_CID1 EQU 0xe00ffff4 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_CID2 +CYREG_ROM_TABLE_CID2 EQU 0xe00ffff8 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_CID3 +CYREG_ROM_TABLE_CID3 EQU 0xe00ffffc + ENDIF + IF :LNOT::DEF:CYDEV_FLS_SIZE +CYDEV_FLS_SIZE EQU CYDEV_FLASH_SIZE + ENDIF + IF :LNOT::DEF:CYDEV_ECC_BASE +CYDEV_ECC_BASE EQU CYDEV_FLSECC_BASE + ENDIF + IF :LNOT::DEF:CYDEV_FLS_SECTOR_SIZE +CYDEV_FLS_SECTOR_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYDEV_FLS_ROW_SIZE +CYDEV_FLS_ROW_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_ECC_SECTOR_SIZE +CYDEV_ECC_SECTOR_SIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYDEV_ECC_ROW_SIZE +CYDEV_ECC_ROW_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_EEPROM_SECTOR_SIZE +CYDEV_EEPROM_SECTOR_SIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYDEV_EEPROM_ROW_SIZE +CYDEV_EEPROM_ROW_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PERIPH_BASE +CYDEV_PERIPH_BASE EQU CYDEV_CLKDIST_BASE + ENDIF + IF :LNOT::DEF:CYCLK_LD_DISABLE +CYCLK_LD_DISABLE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYCLK_LD_SYNC_EN +CYCLK_LD_SYNC_EN EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYCLK_LD_LOAD +CYCLK_LD_LOAD EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYCLK_PIPE +CYCLK_PIPE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYCLK_SSS +CYCLK_SSS EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYCLK_EARLY +CYCLK_EARLY EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYCLK_DUTY +CYCLK_DUTY EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYCLK_SYNC +CYCLK_SYNC EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_CLK_SYNC_D +CYCLK_SRC_SEL_CLK_SYNC_D EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_SYNC_DIG +CYCLK_SRC_SEL_SYNC_DIG EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_IMO +CYCLK_SRC_SEL_IMO EQU 1 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTAL_MHZ +CYCLK_SRC_SEL_XTAL_MHZ EQU 2 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTALM +CYCLK_SRC_SEL_XTALM EQU 2 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_ILO +CYCLK_SRC_SEL_ILO EQU 3 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_PLL +CYCLK_SRC_SEL_PLL EQU 4 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTAL_KHZ +CYCLK_SRC_SEL_XTAL_KHZ EQU 5 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTALK +CYCLK_SRC_SEL_XTALK EQU 5 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_G +CYCLK_SRC_SEL_DSI_G EQU 6 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_D +CYCLK_SRC_SEL_DSI_D EQU 7 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_CLK_SYNC_A +CYCLK_SRC_SEL_CLK_SYNC_A EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_A +CYCLK_SRC_SEL_DSI_A EQU 7 + ENDIF + END diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydisabledsheets.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydisabledsheets.h new file mode 100755 index 00000000..81788739 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cydisabledsheets.h @@ -0,0 +1,5 @@ +#ifndef INCLUDED_CYDISABLEDSHEETS_H +#define INCLUDED_CYDISABLEDSHEETS_H + + +#endif /* INCLUDED_CYDISABLEDSHEETS_H */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyfitter.h new file mode 100755 index 00000000..a666b96c --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -0,0 +1,2684 @@ +#ifndef INCLUDED_CYFITTER_H +#define INCLUDED_CYFITTER_H +#include +#include + +/* USBFS_bus_reset */ +#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_bus_reset__INTC_MASK 0x800000u +#define USBFS_bus_reset__INTC_NUMBER 23u +#define USBFS_bus_reset__INTC_PRIOR_NUM 7u +#define USBFS_bus_reset__INTC_PRIOR_REG CYREG_NVIC_PRI_23 +#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* USBFS_arb_int */ +#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_arb_int__INTC_MASK 0x400000u +#define USBFS_arb_int__INTC_NUMBER 22u +#define USBFS_arb_int__INTC_PRIOR_NUM 7u +#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22 +#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* USBFS_sof_int */ +#define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_sof_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_sof_int__INTC_MASK 0x200000u +#define USBFS_sof_int__INTC_NUMBER 21u +#define USBFS_sof_int__INTC_PRIOR_NUM 7u +#define USBFS_sof_int__INTC_PRIOR_REG CYREG_NVIC_PRI_21 +#define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SCSI_Out_DBx */ +#define SCSI_Out_DBx__0__AG CYREG_PRT5_AG +#define SCSI_Out_DBx__0__AMUX CYREG_PRT5_AMUX +#define SCSI_Out_DBx__0__BIE CYREG_PRT5_BIE +#define SCSI_Out_DBx__0__BIT_MASK CYREG_PRT5_BIT_MASK +#define SCSI_Out_DBx__0__BYP CYREG_PRT5_BYP +#define SCSI_Out_DBx__0__CTL CYREG_PRT5_CTL +#define SCSI_Out_DBx__0__DM0 CYREG_PRT5_DM0 +#define SCSI_Out_DBx__0__DM1 CYREG_PRT5_DM1 +#define SCSI_Out_DBx__0__DM2 CYREG_PRT5_DM2 +#define SCSI_Out_DBx__0__DR CYREG_PRT5_DR +#define SCSI_Out_DBx__0__INP_DIS CYREG_PRT5_INP_DIS +#define SCSI_Out_DBx__0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG +#define SCSI_Out_DBx__0__LCD_EN CYREG_PRT5_LCD_EN +#define SCSI_Out_DBx__0__MASK 0x02u +#define SCSI_Out_DBx__0__PC CYREG_PRT5_PC1 +#define SCSI_Out_DBx__0__PORT 5u +#define SCSI_Out_DBx__0__PRT CYREG_PRT5_PRT +#define SCSI_Out_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL +#define SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN +#define SCSI_Out_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 +#define SCSI_Out_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 +#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 +#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 +#define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT +#define SCSI_Out_DBx__0__PS CYREG_PRT5_PS +#define SCSI_Out_DBx__0__SHIFT 1 +#define SCSI_Out_DBx__0__SLW CYREG_PRT5_SLW +#define SCSI_Out_DBx__1__AG CYREG_PRT5_AG +#define SCSI_Out_DBx__1__AMUX CYREG_PRT5_AMUX +#define SCSI_Out_DBx__1__BIE CYREG_PRT5_BIE +#define SCSI_Out_DBx__1__BIT_MASK CYREG_PRT5_BIT_MASK +#define SCSI_Out_DBx__1__BYP CYREG_PRT5_BYP +#define SCSI_Out_DBx__1__CTL CYREG_PRT5_CTL +#define SCSI_Out_DBx__1__DM0 CYREG_PRT5_DM0 +#define SCSI_Out_DBx__1__DM1 CYREG_PRT5_DM1 +#define SCSI_Out_DBx__1__DM2 CYREG_PRT5_DM2 +#define SCSI_Out_DBx__1__DR CYREG_PRT5_DR +#define SCSI_Out_DBx__1__INP_DIS CYREG_PRT5_INP_DIS +#define SCSI_Out_DBx__1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG +#define SCSI_Out_DBx__1__LCD_EN CYREG_PRT5_LCD_EN +#define SCSI_Out_DBx__1__MASK 0x01u +#define SCSI_Out_DBx__1__PC CYREG_PRT5_PC0 +#define SCSI_Out_DBx__1__PORT 5u +#define SCSI_Out_DBx__1__PRT CYREG_PRT5_PRT +#define SCSI_Out_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL +#define SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN +#define SCSI_Out_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 +#define SCSI_Out_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 +#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 +#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 +#define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT +#define SCSI_Out_DBx__1__PS CYREG_PRT5_PS +#define SCSI_Out_DBx__1__SHIFT 0 +#define SCSI_Out_DBx__1__SLW CYREG_PRT5_SLW +#define SCSI_Out_DBx__2__AG CYREG_PRT6_AG +#define SCSI_Out_DBx__2__AMUX CYREG_PRT6_AMUX +#define SCSI_Out_DBx__2__BIE CYREG_PRT6_BIE +#define SCSI_Out_DBx__2__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out_DBx__2__BYP CYREG_PRT6_BYP +#define SCSI_Out_DBx__2__CTL CYREG_PRT6_CTL +#define SCSI_Out_DBx__2__DM0 CYREG_PRT6_DM0 +#define SCSI_Out_DBx__2__DM1 CYREG_PRT6_DM1 +#define SCSI_Out_DBx__2__DM2 CYREG_PRT6_DM2 +#define SCSI_Out_DBx__2__DR CYREG_PRT6_DR +#define SCSI_Out_DBx__2__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out_DBx__2__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out_DBx__2__MASK 0x20u +#define SCSI_Out_DBx__2__PC CYREG_PRT6_PC5 +#define SCSI_Out_DBx__2__PORT 6u +#define SCSI_Out_DBx__2__PRT CYREG_PRT6_PRT +#define SCSI_Out_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out_DBx__2__PS CYREG_PRT6_PS +#define SCSI_Out_DBx__2__SHIFT 5 +#define SCSI_Out_DBx__2__SLW CYREG_PRT6_SLW +#define SCSI_Out_DBx__3__AG CYREG_PRT6_AG +#define SCSI_Out_DBx__3__AMUX CYREG_PRT6_AMUX +#define SCSI_Out_DBx__3__BIE CYREG_PRT6_BIE +#define SCSI_Out_DBx__3__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out_DBx__3__BYP CYREG_PRT6_BYP +#define SCSI_Out_DBx__3__CTL CYREG_PRT6_CTL +#define SCSI_Out_DBx__3__DM0 CYREG_PRT6_DM0 +#define SCSI_Out_DBx__3__DM1 CYREG_PRT6_DM1 +#define SCSI_Out_DBx__3__DM2 CYREG_PRT6_DM2 +#define SCSI_Out_DBx__3__DR CYREG_PRT6_DR +#define SCSI_Out_DBx__3__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out_DBx__3__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out_DBx__3__MASK 0x10u +#define SCSI_Out_DBx__3__PC CYREG_PRT6_PC4 +#define SCSI_Out_DBx__3__PORT 6u +#define SCSI_Out_DBx__3__PRT CYREG_PRT6_PRT +#define SCSI_Out_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out_DBx__3__PS CYREG_PRT6_PS +#define SCSI_Out_DBx__3__SHIFT 4 +#define SCSI_Out_DBx__3__SLW CYREG_PRT6_SLW +#define SCSI_Out_DBx__4__AG CYREG_PRT2_AG +#define SCSI_Out_DBx__4__AMUX CYREG_PRT2_AMUX +#define SCSI_Out_DBx__4__BIE CYREG_PRT2_BIE +#define SCSI_Out_DBx__4__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Out_DBx__4__BYP CYREG_PRT2_BYP +#define SCSI_Out_DBx__4__CTL CYREG_PRT2_CTL +#define SCSI_Out_DBx__4__DM0 CYREG_PRT2_DM0 +#define SCSI_Out_DBx__4__DM1 CYREG_PRT2_DM1 +#define SCSI_Out_DBx__4__DM2 CYREG_PRT2_DM2 +#define SCSI_Out_DBx__4__DR CYREG_PRT2_DR +#define SCSI_Out_DBx__4__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Out_DBx__4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Out_DBx__4__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Out_DBx__4__MASK 0x80u +#define SCSI_Out_DBx__4__PC CYREG_PRT2_PC7 +#define SCSI_Out_DBx__4__PORT 2u +#define SCSI_Out_DBx__4__PRT CYREG_PRT2_PRT +#define SCSI_Out_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Out_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Out_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Out_DBx__4__PS CYREG_PRT2_PS +#define SCSI_Out_DBx__4__SHIFT 7 +#define SCSI_Out_DBx__4__SLW CYREG_PRT2_SLW +#define SCSI_Out_DBx__5__AG CYREG_PRT2_AG +#define SCSI_Out_DBx__5__AMUX CYREG_PRT2_AMUX +#define SCSI_Out_DBx__5__BIE CYREG_PRT2_BIE +#define SCSI_Out_DBx__5__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Out_DBx__5__BYP CYREG_PRT2_BYP +#define SCSI_Out_DBx__5__CTL CYREG_PRT2_CTL +#define SCSI_Out_DBx__5__DM0 CYREG_PRT2_DM0 +#define SCSI_Out_DBx__5__DM1 CYREG_PRT2_DM1 +#define SCSI_Out_DBx__5__DM2 CYREG_PRT2_DM2 +#define SCSI_Out_DBx__5__DR CYREG_PRT2_DR +#define SCSI_Out_DBx__5__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Out_DBx__5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Out_DBx__5__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Out_DBx__5__MASK 0x40u +#define SCSI_Out_DBx__5__PC CYREG_PRT2_PC6 +#define SCSI_Out_DBx__5__PORT 2u +#define SCSI_Out_DBx__5__PRT CYREG_PRT2_PRT +#define SCSI_Out_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Out_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Out_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Out_DBx__5__PS CYREG_PRT2_PS +#define SCSI_Out_DBx__5__SHIFT 6 +#define SCSI_Out_DBx__5__SLW CYREG_PRT2_SLW +#define SCSI_Out_DBx__6__AG CYREG_PRT2_AG +#define SCSI_Out_DBx__6__AMUX CYREG_PRT2_AMUX +#define SCSI_Out_DBx__6__BIE CYREG_PRT2_BIE +#define SCSI_Out_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Out_DBx__6__BYP CYREG_PRT2_BYP +#define SCSI_Out_DBx__6__CTL CYREG_PRT2_CTL +#define SCSI_Out_DBx__6__DM0 CYREG_PRT2_DM0 +#define SCSI_Out_DBx__6__DM1 CYREG_PRT2_DM1 +#define SCSI_Out_DBx__6__DM2 CYREG_PRT2_DM2 +#define SCSI_Out_DBx__6__DR CYREG_PRT2_DR +#define SCSI_Out_DBx__6__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Out_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Out_DBx__6__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Out_DBx__6__MASK 0x08u +#define SCSI_Out_DBx__6__PC CYREG_PRT2_PC3 +#define SCSI_Out_DBx__6__PORT 2u +#define SCSI_Out_DBx__6__PRT CYREG_PRT2_PRT +#define SCSI_Out_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Out_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Out_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Out_DBx__6__PS CYREG_PRT2_PS +#define SCSI_Out_DBx__6__SHIFT 3 +#define SCSI_Out_DBx__6__SLW CYREG_PRT2_SLW +#define SCSI_Out_DBx__7__AG CYREG_PRT2_AG +#define SCSI_Out_DBx__7__AMUX CYREG_PRT2_AMUX +#define SCSI_Out_DBx__7__BIE CYREG_PRT2_BIE +#define SCSI_Out_DBx__7__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Out_DBx__7__BYP CYREG_PRT2_BYP +#define SCSI_Out_DBx__7__CTL CYREG_PRT2_CTL +#define SCSI_Out_DBx__7__DM0 CYREG_PRT2_DM0 +#define SCSI_Out_DBx__7__DM1 CYREG_PRT2_DM1 +#define SCSI_Out_DBx__7__DM2 CYREG_PRT2_DM2 +#define SCSI_Out_DBx__7__DR CYREG_PRT2_DR +#define SCSI_Out_DBx__7__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Out_DBx__7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Out_DBx__7__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Out_DBx__7__MASK 0x04u +#define SCSI_Out_DBx__7__PC CYREG_PRT2_PC2 +#define SCSI_Out_DBx__7__PORT 2u +#define SCSI_Out_DBx__7__PRT CYREG_PRT2_PRT +#define SCSI_Out_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Out_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Out_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Out_DBx__7__PS CYREG_PRT2_PS +#define SCSI_Out_DBx__7__SHIFT 2 +#define SCSI_Out_DBx__7__SLW CYREG_PRT2_SLW +#define SCSI_Out_DBx__DB0__AG CYREG_PRT5_AG +#define SCSI_Out_DBx__DB0__AMUX CYREG_PRT5_AMUX +#define SCSI_Out_DBx__DB0__BIE CYREG_PRT5_BIE +#define SCSI_Out_DBx__DB0__BIT_MASK CYREG_PRT5_BIT_MASK +#define SCSI_Out_DBx__DB0__BYP CYREG_PRT5_BYP +#define SCSI_Out_DBx__DB0__CTL CYREG_PRT5_CTL +#define SCSI_Out_DBx__DB0__DM0 CYREG_PRT5_DM0 +#define SCSI_Out_DBx__DB0__DM1 CYREG_PRT5_DM1 +#define SCSI_Out_DBx__DB0__DM2 CYREG_PRT5_DM2 +#define SCSI_Out_DBx__DB0__DR CYREG_PRT5_DR +#define SCSI_Out_DBx__DB0__INP_DIS CYREG_PRT5_INP_DIS +#define SCSI_Out_DBx__DB0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG +#define SCSI_Out_DBx__DB0__LCD_EN CYREG_PRT5_LCD_EN +#define SCSI_Out_DBx__DB0__MASK 0x02u +#define SCSI_Out_DBx__DB0__PC CYREG_PRT5_PC1 +#define SCSI_Out_DBx__DB0__PORT 5u +#define SCSI_Out_DBx__DB0__PRT CYREG_PRT5_PRT +#define SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL +#define SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN +#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 +#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 +#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 +#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 +#define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT +#define SCSI_Out_DBx__DB0__PS CYREG_PRT5_PS +#define SCSI_Out_DBx__DB0__SHIFT 1 +#define SCSI_Out_DBx__DB0__SLW CYREG_PRT5_SLW +#define SCSI_Out_DBx__DB1__AG CYREG_PRT5_AG +#define SCSI_Out_DBx__DB1__AMUX CYREG_PRT5_AMUX +#define SCSI_Out_DBx__DB1__BIE CYREG_PRT5_BIE +#define SCSI_Out_DBx__DB1__BIT_MASK CYREG_PRT5_BIT_MASK +#define SCSI_Out_DBx__DB1__BYP CYREG_PRT5_BYP +#define SCSI_Out_DBx__DB1__CTL CYREG_PRT5_CTL +#define SCSI_Out_DBx__DB1__DM0 CYREG_PRT5_DM0 +#define SCSI_Out_DBx__DB1__DM1 CYREG_PRT5_DM1 +#define SCSI_Out_DBx__DB1__DM2 CYREG_PRT5_DM2 +#define SCSI_Out_DBx__DB1__DR CYREG_PRT5_DR +#define SCSI_Out_DBx__DB1__INP_DIS CYREG_PRT5_INP_DIS +#define SCSI_Out_DBx__DB1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG +#define SCSI_Out_DBx__DB1__LCD_EN CYREG_PRT5_LCD_EN +#define SCSI_Out_DBx__DB1__MASK 0x01u +#define SCSI_Out_DBx__DB1__PC CYREG_PRT5_PC0 +#define SCSI_Out_DBx__DB1__PORT 5u +#define SCSI_Out_DBx__DB1__PRT CYREG_PRT5_PRT +#define SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL +#define SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN +#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 +#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 +#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 +#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 +#define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT +#define SCSI_Out_DBx__DB1__PS CYREG_PRT5_PS +#define SCSI_Out_DBx__DB1__SHIFT 0 +#define SCSI_Out_DBx__DB1__SLW CYREG_PRT5_SLW +#define SCSI_Out_DBx__DB2__AG CYREG_PRT6_AG +#define SCSI_Out_DBx__DB2__AMUX CYREG_PRT6_AMUX +#define SCSI_Out_DBx__DB2__BIE CYREG_PRT6_BIE +#define SCSI_Out_DBx__DB2__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out_DBx__DB2__BYP CYREG_PRT6_BYP +#define SCSI_Out_DBx__DB2__CTL CYREG_PRT6_CTL +#define SCSI_Out_DBx__DB2__DM0 CYREG_PRT6_DM0 +#define SCSI_Out_DBx__DB2__DM1 CYREG_PRT6_DM1 +#define SCSI_Out_DBx__DB2__DM2 CYREG_PRT6_DM2 +#define SCSI_Out_DBx__DB2__DR CYREG_PRT6_DR +#define SCSI_Out_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out_DBx__DB2__MASK 0x20u +#define SCSI_Out_DBx__DB2__PC CYREG_PRT6_PC5 +#define SCSI_Out_DBx__DB2__PORT 6u +#define SCSI_Out_DBx__DB2__PRT CYREG_PRT6_PRT +#define SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out_DBx__DB2__PS CYREG_PRT6_PS +#define SCSI_Out_DBx__DB2__SHIFT 5 +#define SCSI_Out_DBx__DB2__SLW CYREG_PRT6_SLW +#define SCSI_Out_DBx__DB3__AG CYREG_PRT6_AG +#define SCSI_Out_DBx__DB3__AMUX CYREG_PRT6_AMUX +#define SCSI_Out_DBx__DB3__BIE CYREG_PRT6_BIE +#define SCSI_Out_DBx__DB3__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out_DBx__DB3__BYP CYREG_PRT6_BYP +#define SCSI_Out_DBx__DB3__CTL CYREG_PRT6_CTL +#define SCSI_Out_DBx__DB3__DM0 CYREG_PRT6_DM0 +#define SCSI_Out_DBx__DB3__DM1 CYREG_PRT6_DM1 +#define SCSI_Out_DBx__DB3__DM2 CYREG_PRT6_DM2 +#define SCSI_Out_DBx__DB3__DR CYREG_PRT6_DR +#define SCSI_Out_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out_DBx__DB3__MASK 0x10u +#define SCSI_Out_DBx__DB3__PC CYREG_PRT6_PC4 +#define SCSI_Out_DBx__DB3__PORT 6u +#define SCSI_Out_DBx__DB3__PRT CYREG_PRT6_PRT +#define SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out_DBx__DB3__PS CYREG_PRT6_PS +#define SCSI_Out_DBx__DB3__SHIFT 4 +#define SCSI_Out_DBx__DB3__SLW CYREG_PRT6_SLW +#define SCSI_Out_DBx__DB4__AG CYREG_PRT2_AG +#define SCSI_Out_DBx__DB4__AMUX CYREG_PRT2_AMUX +#define SCSI_Out_DBx__DB4__BIE CYREG_PRT2_BIE +#define SCSI_Out_DBx__DB4__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Out_DBx__DB4__BYP CYREG_PRT2_BYP +#define SCSI_Out_DBx__DB4__CTL CYREG_PRT2_CTL +#define SCSI_Out_DBx__DB4__DM0 CYREG_PRT2_DM0 +#define SCSI_Out_DBx__DB4__DM1 CYREG_PRT2_DM1 +#define SCSI_Out_DBx__DB4__DM2 CYREG_PRT2_DM2 +#define SCSI_Out_DBx__DB4__DR CYREG_PRT2_DR +#define SCSI_Out_DBx__DB4__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Out_DBx__DB4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Out_DBx__DB4__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Out_DBx__DB4__MASK 0x80u +#define SCSI_Out_DBx__DB4__PC CYREG_PRT2_PC7 +#define SCSI_Out_DBx__DB4__PORT 2u +#define SCSI_Out_DBx__DB4__PRT CYREG_PRT2_PRT +#define SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Out_DBx__DB4__PS CYREG_PRT2_PS +#define SCSI_Out_DBx__DB4__SHIFT 7 +#define SCSI_Out_DBx__DB4__SLW CYREG_PRT2_SLW +#define SCSI_Out_DBx__DB5__AG CYREG_PRT2_AG +#define SCSI_Out_DBx__DB5__AMUX CYREG_PRT2_AMUX +#define SCSI_Out_DBx__DB5__BIE CYREG_PRT2_BIE +#define SCSI_Out_DBx__DB5__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Out_DBx__DB5__BYP CYREG_PRT2_BYP +#define SCSI_Out_DBx__DB5__CTL CYREG_PRT2_CTL +#define SCSI_Out_DBx__DB5__DM0 CYREG_PRT2_DM0 +#define SCSI_Out_DBx__DB5__DM1 CYREG_PRT2_DM1 +#define SCSI_Out_DBx__DB5__DM2 CYREG_PRT2_DM2 +#define SCSI_Out_DBx__DB5__DR CYREG_PRT2_DR +#define SCSI_Out_DBx__DB5__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Out_DBx__DB5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Out_DBx__DB5__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Out_DBx__DB5__MASK 0x40u +#define SCSI_Out_DBx__DB5__PC CYREG_PRT2_PC6 +#define SCSI_Out_DBx__DB5__PORT 2u +#define SCSI_Out_DBx__DB5__PRT CYREG_PRT2_PRT +#define SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Out_DBx__DB5__PS CYREG_PRT2_PS +#define SCSI_Out_DBx__DB5__SHIFT 6 +#define SCSI_Out_DBx__DB5__SLW CYREG_PRT2_SLW +#define SCSI_Out_DBx__DB6__AG CYREG_PRT2_AG +#define SCSI_Out_DBx__DB6__AMUX CYREG_PRT2_AMUX +#define SCSI_Out_DBx__DB6__BIE CYREG_PRT2_BIE +#define SCSI_Out_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Out_DBx__DB6__BYP CYREG_PRT2_BYP +#define SCSI_Out_DBx__DB6__CTL CYREG_PRT2_CTL +#define SCSI_Out_DBx__DB6__DM0 CYREG_PRT2_DM0 +#define SCSI_Out_DBx__DB6__DM1 CYREG_PRT2_DM1 +#define SCSI_Out_DBx__DB6__DM2 CYREG_PRT2_DM2 +#define SCSI_Out_DBx__DB6__DR CYREG_PRT2_DR +#define SCSI_Out_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Out_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Out_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Out_DBx__DB6__MASK 0x08u +#define SCSI_Out_DBx__DB6__PC CYREG_PRT2_PC3 +#define SCSI_Out_DBx__DB6__PORT 2u +#define SCSI_Out_DBx__DB6__PRT CYREG_PRT2_PRT +#define SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Out_DBx__DB6__PS CYREG_PRT2_PS +#define SCSI_Out_DBx__DB6__SHIFT 3 +#define SCSI_Out_DBx__DB6__SLW CYREG_PRT2_SLW +#define SCSI_Out_DBx__DB7__AG CYREG_PRT2_AG +#define SCSI_Out_DBx__DB7__AMUX CYREG_PRT2_AMUX +#define SCSI_Out_DBx__DB7__BIE CYREG_PRT2_BIE +#define SCSI_Out_DBx__DB7__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Out_DBx__DB7__BYP CYREG_PRT2_BYP +#define SCSI_Out_DBx__DB7__CTL CYREG_PRT2_CTL +#define SCSI_Out_DBx__DB7__DM0 CYREG_PRT2_DM0 +#define SCSI_Out_DBx__DB7__DM1 CYREG_PRT2_DM1 +#define SCSI_Out_DBx__DB7__DM2 CYREG_PRT2_DM2 +#define SCSI_Out_DBx__DB7__DR CYREG_PRT2_DR +#define SCSI_Out_DBx__DB7__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Out_DBx__DB7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Out_DBx__DB7__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Out_DBx__DB7__MASK 0x04u +#define SCSI_Out_DBx__DB7__PC CYREG_PRT2_PC2 +#define SCSI_Out_DBx__DB7__PORT 2u +#define SCSI_Out_DBx__DB7__PRT CYREG_PRT2_PRT +#define SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Out_DBx__DB7__PS CYREG_PRT2_PS +#define SCSI_Out_DBx__DB7__SHIFT 2 +#define SCSI_Out_DBx__DB7__SLW CYREG_PRT2_SLW + +/* SCSI_RST_ISR */ +#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SCSI_RST_ISR__INTC_MASK 0x100u +#define SCSI_RST_ISR__INTC_NUMBER 8u +#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u +#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_8 +#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SDCard_BSPIM */ +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST +#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB06_MSK +#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB06_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB06_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB06_ST +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL +#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK +#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK +#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL +#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB06_CTL +#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL +#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB06_CTL +#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL +#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB06_MSK +#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST +#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u +#define SDCard_BSPIM_RxStsReg__4__POS 4 +#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u +#define SDCard_BSPIM_RxStsReg__5__POS 5 +#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u +#define SDCard_BSPIM_RxStsReg__6__POS 6 +#define SDCard_BSPIM_RxStsReg__MASK 0x70u +#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK +#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL +#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST +#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u +#define SDCard_BSPIM_TxStsReg__0__POS 0 +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST +#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u +#define SDCard_BSPIM_TxStsReg__1__POS 1 +#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u +#define SDCard_BSPIM_TxStsReg__2__POS 2 +#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u +#define SDCard_BSPIM_TxStsReg__3__POS 3 +#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u +#define SDCard_BSPIM_TxStsReg__4__POS 4 +#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu +#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB05_MSK +#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL +#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB05_ST +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB06_07_A0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB06_07_A1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB06_07_D0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB06_07_D1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB06_07_F0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB06_07_F1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB06_A0_A1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB06_A0 +#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB06_A1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB06_D0_D1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB06_D0 +#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB06_D1 +#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB06_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB06_F0_F1 +#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB06_F0 +#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB06_F1 + +/* USBFS_dp_int */ +#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_dp_int__INTC_MASK 0x1000u +#define USBFS_dp_int__INTC_NUMBER 12u +#define USBFS_dp_int__INTC_PRIOR_NUM 7u +#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12 +#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SCSI_CTL_IO */ +#define SCSI_CTL_IO_Sync_ctrl_reg__0__MASK 0x01u +#define SCSI_CTL_IO_Sync_ctrl_reg__0__POS 0 +#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB15_ACTL +#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB15_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB15_ST_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB15_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB15_ST_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__MASK 0x01u +#define SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL +#define SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB15_MSK +#define SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL + +/* SCSI_In_DBx */ +#define SCSI_In_DBx__0__AG CYREG_PRT5_AG +#define SCSI_In_DBx__0__AMUX CYREG_PRT5_AMUX +#define SCSI_In_DBx__0__BIE CYREG_PRT5_BIE +#define SCSI_In_DBx__0__BIT_MASK CYREG_PRT5_BIT_MASK +#define SCSI_In_DBx__0__BYP CYREG_PRT5_BYP +#define SCSI_In_DBx__0__CTL CYREG_PRT5_CTL +#define SCSI_In_DBx__0__DM0 CYREG_PRT5_DM0 +#define SCSI_In_DBx__0__DM1 CYREG_PRT5_DM1 +#define SCSI_In_DBx__0__DM2 CYREG_PRT5_DM2 +#define SCSI_In_DBx__0__DR CYREG_PRT5_DR +#define SCSI_In_DBx__0__INP_DIS CYREG_PRT5_INP_DIS +#define SCSI_In_DBx__0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG +#define SCSI_In_DBx__0__LCD_EN CYREG_PRT5_LCD_EN +#define SCSI_In_DBx__0__MASK 0x08u +#define SCSI_In_DBx__0__PC CYREG_PRT5_PC3 +#define SCSI_In_DBx__0__PORT 5u +#define SCSI_In_DBx__0__PRT CYREG_PRT5_PRT +#define SCSI_In_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL +#define SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN +#define SCSI_In_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 +#define SCSI_In_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 +#define SCSI_In_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 +#define SCSI_In_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 +#define SCSI_In_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT +#define SCSI_In_DBx__0__PS CYREG_PRT5_PS +#define SCSI_In_DBx__0__SHIFT 3 +#define SCSI_In_DBx__0__SLW CYREG_PRT5_SLW +#define SCSI_In_DBx__1__AG CYREG_PRT5_AG +#define SCSI_In_DBx__1__AMUX CYREG_PRT5_AMUX +#define SCSI_In_DBx__1__BIE CYREG_PRT5_BIE +#define SCSI_In_DBx__1__BIT_MASK CYREG_PRT5_BIT_MASK +#define SCSI_In_DBx__1__BYP CYREG_PRT5_BYP +#define SCSI_In_DBx__1__CTL CYREG_PRT5_CTL +#define SCSI_In_DBx__1__DM0 CYREG_PRT5_DM0 +#define SCSI_In_DBx__1__DM1 CYREG_PRT5_DM1 +#define SCSI_In_DBx__1__DM2 CYREG_PRT5_DM2 +#define SCSI_In_DBx__1__DR CYREG_PRT5_DR +#define SCSI_In_DBx__1__INP_DIS CYREG_PRT5_INP_DIS +#define SCSI_In_DBx__1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG +#define SCSI_In_DBx__1__LCD_EN CYREG_PRT5_LCD_EN +#define SCSI_In_DBx__1__MASK 0x04u +#define SCSI_In_DBx__1__PC CYREG_PRT5_PC2 +#define SCSI_In_DBx__1__PORT 5u +#define SCSI_In_DBx__1__PRT CYREG_PRT5_PRT +#define SCSI_In_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL +#define SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN +#define SCSI_In_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 +#define SCSI_In_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 +#define SCSI_In_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 +#define SCSI_In_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 +#define SCSI_In_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT +#define SCSI_In_DBx__1__PS CYREG_PRT5_PS +#define SCSI_In_DBx__1__SHIFT 2 +#define SCSI_In_DBx__1__SLW CYREG_PRT5_SLW +#define SCSI_In_DBx__2__AG CYREG_PRT6_AG +#define SCSI_In_DBx__2__AMUX CYREG_PRT6_AMUX +#define SCSI_In_DBx__2__BIE CYREG_PRT6_BIE +#define SCSI_In_DBx__2__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_In_DBx__2__BYP CYREG_PRT6_BYP +#define SCSI_In_DBx__2__CTL CYREG_PRT6_CTL +#define SCSI_In_DBx__2__DM0 CYREG_PRT6_DM0 +#define SCSI_In_DBx__2__DM1 CYREG_PRT6_DM1 +#define SCSI_In_DBx__2__DM2 CYREG_PRT6_DM2 +#define SCSI_In_DBx__2__DR CYREG_PRT6_DR +#define SCSI_In_DBx__2__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_In_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_In_DBx__2__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_In_DBx__2__MASK 0x80u +#define SCSI_In_DBx__2__PC CYREG_PRT6_PC7 +#define SCSI_In_DBx__2__PORT 6u +#define SCSI_In_DBx__2__PRT CYREG_PRT6_PRT +#define SCSI_In_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_In_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_In_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_In_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_In_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_In_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_In_DBx__2__PS CYREG_PRT6_PS +#define SCSI_In_DBx__2__SHIFT 7 +#define SCSI_In_DBx__2__SLW CYREG_PRT6_SLW +#define SCSI_In_DBx__3__AG CYREG_PRT6_AG +#define SCSI_In_DBx__3__AMUX CYREG_PRT6_AMUX +#define SCSI_In_DBx__3__BIE CYREG_PRT6_BIE +#define SCSI_In_DBx__3__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_In_DBx__3__BYP CYREG_PRT6_BYP +#define SCSI_In_DBx__3__CTL CYREG_PRT6_CTL +#define SCSI_In_DBx__3__DM0 CYREG_PRT6_DM0 +#define SCSI_In_DBx__3__DM1 CYREG_PRT6_DM1 +#define SCSI_In_DBx__3__DM2 CYREG_PRT6_DM2 +#define SCSI_In_DBx__3__DR CYREG_PRT6_DR +#define SCSI_In_DBx__3__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_In_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_In_DBx__3__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_In_DBx__3__MASK 0x40u +#define SCSI_In_DBx__3__PC CYREG_PRT6_PC6 +#define SCSI_In_DBx__3__PORT 6u +#define SCSI_In_DBx__3__PRT CYREG_PRT6_PRT +#define SCSI_In_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_In_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_In_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_In_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_In_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_In_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_In_DBx__3__PS CYREG_PRT6_PS +#define SCSI_In_DBx__3__SHIFT 6 +#define SCSI_In_DBx__3__SLW CYREG_PRT6_SLW +#define SCSI_In_DBx__4__AG CYREG_PRT12_AG +#define SCSI_In_DBx__4__BIE CYREG_PRT12_BIE +#define SCSI_In_DBx__4__BIT_MASK CYREG_PRT12_BIT_MASK +#define SCSI_In_DBx__4__BYP CYREG_PRT12_BYP +#define SCSI_In_DBx__4__DM0 CYREG_PRT12_DM0 +#define SCSI_In_DBx__4__DM1 CYREG_PRT12_DM1 +#define SCSI_In_DBx__4__DM2 CYREG_PRT12_DM2 +#define SCSI_In_DBx__4__DR CYREG_PRT12_DR +#define SCSI_In_DBx__4__INP_DIS CYREG_PRT12_INP_DIS +#define SCSI_In_DBx__4__MASK 0x20u +#define SCSI_In_DBx__4__PC CYREG_PRT12_PC5 +#define SCSI_In_DBx__4__PORT 12u +#define SCSI_In_DBx__4__PRT CYREG_PRT12_PRT +#define SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN +#define SCSI_In_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 +#define SCSI_In_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 +#define SCSI_In_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 +#define SCSI_In_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 +#define SCSI_In_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT +#define SCSI_In_DBx__4__PS CYREG_PRT12_PS +#define SCSI_In_DBx__4__SHIFT 5 +#define SCSI_In_DBx__4__SIO_CFG CYREG_PRT12_SIO_CFG +#define SCSI_In_DBx__4__SIO_DIFF CYREG_PRT12_SIO_DIFF +#define SCSI_In_DBx__4__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN +#define SCSI_In_DBx__4__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ +#define SCSI_In_DBx__4__SLW CYREG_PRT12_SLW +#define SCSI_In_DBx__5__AG CYREG_PRT12_AG +#define SCSI_In_DBx__5__BIE CYREG_PRT12_BIE +#define SCSI_In_DBx__5__BIT_MASK CYREG_PRT12_BIT_MASK +#define SCSI_In_DBx__5__BYP CYREG_PRT12_BYP +#define SCSI_In_DBx__5__DM0 CYREG_PRT12_DM0 +#define SCSI_In_DBx__5__DM1 CYREG_PRT12_DM1 +#define SCSI_In_DBx__5__DM2 CYREG_PRT12_DM2 +#define SCSI_In_DBx__5__DR CYREG_PRT12_DR +#define SCSI_In_DBx__5__INP_DIS CYREG_PRT12_INP_DIS +#define SCSI_In_DBx__5__MASK 0x10u +#define SCSI_In_DBx__5__PC CYREG_PRT12_PC4 +#define SCSI_In_DBx__5__PORT 12u +#define SCSI_In_DBx__5__PRT CYREG_PRT12_PRT +#define SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN +#define SCSI_In_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 +#define SCSI_In_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 +#define SCSI_In_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 +#define SCSI_In_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 +#define SCSI_In_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT +#define SCSI_In_DBx__5__PS CYREG_PRT12_PS +#define SCSI_In_DBx__5__SHIFT 4 +#define SCSI_In_DBx__5__SIO_CFG CYREG_PRT12_SIO_CFG +#define SCSI_In_DBx__5__SIO_DIFF CYREG_PRT12_SIO_DIFF +#define SCSI_In_DBx__5__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN +#define SCSI_In_DBx__5__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ +#define SCSI_In_DBx__5__SLW CYREG_PRT12_SLW +#define SCSI_In_DBx__6__AG CYREG_PRT2_AG +#define SCSI_In_DBx__6__AMUX CYREG_PRT2_AMUX +#define SCSI_In_DBx__6__BIE CYREG_PRT2_BIE +#define SCSI_In_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_In_DBx__6__BYP CYREG_PRT2_BYP +#define SCSI_In_DBx__6__CTL CYREG_PRT2_CTL +#define SCSI_In_DBx__6__DM0 CYREG_PRT2_DM0 +#define SCSI_In_DBx__6__DM1 CYREG_PRT2_DM1 +#define SCSI_In_DBx__6__DM2 CYREG_PRT2_DM2 +#define SCSI_In_DBx__6__DR CYREG_PRT2_DR +#define SCSI_In_DBx__6__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_In_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_In_DBx__6__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_In_DBx__6__MASK 0x20u +#define SCSI_In_DBx__6__PC CYREG_PRT2_PC5 +#define SCSI_In_DBx__6__PORT 2u +#define SCSI_In_DBx__6__PRT CYREG_PRT2_PRT +#define SCSI_In_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_In_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_In_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_In_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_In_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_In_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_In_DBx__6__PS CYREG_PRT2_PS +#define SCSI_In_DBx__6__SHIFT 5 +#define SCSI_In_DBx__6__SLW CYREG_PRT2_SLW +#define SCSI_In_DBx__7__AG CYREG_PRT2_AG +#define SCSI_In_DBx__7__AMUX CYREG_PRT2_AMUX +#define SCSI_In_DBx__7__BIE CYREG_PRT2_BIE +#define SCSI_In_DBx__7__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_In_DBx__7__BYP CYREG_PRT2_BYP +#define SCSI_In_DBx__7__CTL CYREG_PRT2_CTL +#define SCSI_In_DBx__7__DM0 CYREG_PRT2_DM0 +#define SCSI_In_DBx__7__DM1 CYREG_PRT2_DM1 +#define SCSI_In_DBx__7__DM2 CYREG_PRT2_DM2 +#define SCSI_In_DBx__7__DR CYREG_PRT2_DR +#define SCSI_In_DBx__7__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_In_DBx__7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_In_DBx__7__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_In_DBx__7__MASK 0x10u +#define SCSI_In_DBx__7__PC CYREG_PRT2_PC4 +#define SCSI_In_DBx__7__PORT 2u +#define SCSI_In_DBx__7__PRT CYREG_PRT2_PRT +#define SCSI_In_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_In_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_In_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_In_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_In_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_In_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_In_DBx__7__PS CYREG_PRT2_PS +#define SCSI_In_DBx__7__SHIFT 4 +#define SCSI_In_DBx__7__SLW CYREG_PRT2_SLW +#define SCSI_In_DBx__DB0__AG CYREG_PRT5_AG +#define SCSI_In_DBx__DB0__AMUX CYREG_PRT5_AMUX +#define SCSI_In_DBx__DB0__BIE CYREG_PRT5_BIE +#define SCSI_In_DBx__DB0__BIT_MASK CYREG_PRT5_BIT_MASK +#define SCSI_In_DBx__DB0__BYP CYREG_PRT5_BYP +#define SCSI_In_DBx__DB0__CTL CYREG_PRT5_CTL +#define SCSI_In_DBx__DB0__DM0 CYREG_PRT5_DM0 +#define SCSI_In_DBx__DB0__DM1 CYREG_PRT5_DM1 +#define SCSI_In_DBx__DB0__DM2 CYREG_PRT5_DM2 +#define SCSI_In_DBx__DB0__DR CYREG_PRT5_DR +#define SCSI_In_DBx__DB0__INP_DIS CYREG_PRT5_INP_DIS +#define SCSI_In_DBx__DB0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG +#define SCSI_In_DBx__DB0__LCD_EN CYREG_PRT5_LCD_EN +#define SCSI_In_DBx__DB0__MASK 0x08u +#define SCSI_In_DBx__DB0__PC CYREG_PRT5_PC3 +#define SCSI_In_DBx__DB0__PORT 5u +#define SCSI_In_DBx__DB0__PRT CYREG_PRT5_PRT +#define SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL +#define SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN +#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 +#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 +#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 +#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 +#define SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT +#define SCSI_In_DBx__DB0__PS CYREG_PRT5_PS +#define SCSI_In_DBx__DB0__SHIFT 3 +#define SCSI_In_DBx__DB0__SLW CYREG_PRT5_SLW +#define SCSI_In_DBx__DB1__AG CYREG_PRT5_AG +#define SCSI_In_DBx__DB1__AMUX CYREG_PRT5_AMUX +#define SCSI_In_DBx__DB1__BIE CYREG_PRT5_BIE +#define SCSI_In_DBx__DB1__BIT_MASK CYREG_PRT5_BIT_MASK +#define SCSI_In_DBx__DB1__BYP CYREG_PRT5_BYP +#define SCSI_In_DBx__DB1__CTL CYREG_PRT5_CTL +#define SCSI_In_DBx__DB1__DM0 CYREG_PRT5_DM0 +#define SCSI_In_DBx__DB1__DM1 CYREG_PRT5_DM1 +#define SCSI_In_DBx__DB1__DM2 CYREG_PRT5_DM2 +#define SCSI_In_DBx__DB1__DR CYREG_PRT5_DR +#define SCSI_In_DBx__DB1__INP_DIS CYREG_PRT5_INP_DIS +#define SCSI_In_DBx__DB1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG +#define SCSI_In_DBx__DB1__LCD_EN CYREG_PRT5_LCD_EN +#define SCSI_In_DBx__DB1__MASK 0x04u +#define SCSI_In_DBx__DB1__PC CYREG_PRT5_PC2 +#define SCSI_In_DBx__DB1__PORT 5u +#define SCSI_In_DBx__DB1__PRT CYREG_PRT5_PRT +#define SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL +#define SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN +#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 +#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 +#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 +#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 +#define SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT +#define SCSI_In_DBx__DB1__PS CYREG_PRT5_PS +#define SCSI_In_DBx__DB1__SHIFT 2 +#define SCSI_In_DBx__DB1__SLW CYREG_PRT5_SLW +#define SCSI_In_DBx__DB2__AG CYREG_PRT6_AG +#define SCSI_In_DBx__DB2__AMUX CYREG_PRT6_AMUX +#define SCSI_In_DBx__DB2__BIE CYREG_PRT6_BIE +#define SCSI_In_DBx__DB2__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_In_DBx__DB2__BYP CYREG_PRT6_BYP +#define SCSI_In_DBx__DB2__CTL CYREG_PRT6_CTL +#define SCSI_In_DBx__DB2__DM0 CYREG_PRT6_DM0 +#define SCSI_In_DBx__DB2__DM1 CYREG_PRT6_DM1 +#define SCSI_In_DBx__DB2__DM2 CYREG_PRT6_DM2 +#define SCSI_In_DBx__DB2__DR CYREG_PRT6_DR +#define SCSI_In_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_In_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_In_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_In_DBx__DB2__MASK 0x80u +#define SCSI_In_DBx__DB2__PC CYREG_PRT6_PC7 +#define SCSI_In_DBx__DB2__PORT 6u +#define SCSI_In_DBx__DB2__PRT CYREG_PRT6_PRT +#define SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_In_DBx__DB2__PS CYREG_PRT6_PS +#define SCSI_In_DBx__DB2__SHIFT 7 +#define SCSI_In_DBx__DB2__SLW CYREG_PRT6_SLW +#define SCSI_In_DBx__DB3__AG CYREG_PRT6_AG +#define SCSI_In_DBx__DB3__AMUX CYREG_PRT6_AMUX +#define SCSI_In_DBx__DB3__BIE CYREG_PRT6_BIE +#define SCSI_In_DBx__DB3__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_In_DBx__DB3__BYP CYREG_PRT6_BYP +#define SCSI_In_DBx__DB3__CTL CYREG_PRT6_CTL +#define SCSI_In_DBx__DB3__DM0 CYREG_PRT6_DM0 +#define SCSI_In_DBx__DB3__DM1 CYREG_PRT6_DM1 +#define SCSI_In_DBx__DB3__DM2 CYREG_PRT6_DM2 +#define SCSI_In_DBx__DB3__DR CYREG_PRT6_DR +#define SCSI_In_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_In_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_In_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_In_DBx__DB3__MASK 0x40u +#define SCSI_In_DBx__DB3__PC CYREG_PRT6_PC6 +#define SCSI_In_DBx__DB3__PORT 6u +#define SCSI_In_DBx__DB3__PRT CYREG_PRT6_PRT +#define SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_In_DBx__DB3__PS CYREG_PRT6_PS +#define SCSI_In_DBx__DB3__SHIFT 6 +#define SCSI_In_DBx__DB3__SLW CYREG_PRT6_SLW +#define SCSI_In_DBx__DB4__AG CYREG_PRT12_AG +#define SCSI_In_DBx__DB4__BIE CYREG_PRT12_BIE +#define SCSI_In_DBx__DB4__BIT_MASK CYREG_PRT12_BIT_MASK +#define SCSI_In_DBx__DB4__BYP CYREG_PRT12_BYP +#define SCSI_In_DBx__DB4__DM0 CYREG_PRT12_DM0 +#define SCSI_In_DBx__DB4__DM1 CYREG_PRT12_DM1 +#define SCSI_In_DBx__DB4__DM2 CYREG_PRT12_DM2 +#define SCSI_In_DBx__DB4__DR CYREG_PRT12_DR +#define SCSI_In_DBx__DB4__INP_DIS CYREG_PRT12_INP_DIS +#define SCSI_In_DBx__DB4__MASK 0x20u +#define SCSI_In_DBx__DB4__PC CYREG_PRT12_PC5 +#define SCSI_In_DBx__DB4__PORT 12u +#define SCSI_In_DBx__DB4__PRT CYREG_PRT12_PRT +#define SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN +#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 +#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 +#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 +#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 +#define SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT +#define SCSI_In_DBx__DB4__PS CYREG_PRT12_PS +#define SCSI_In_DBx__DB4__SHIFT 5 +#define SCSI_In_DBx__DB4__SIO_CFG CYREG_PRT12_SIO_CFG +#define SCSI_In_DBx__DB4__SIO_DIFF CYREG_PRT12_SIO_DIFF +#define SCSI_In_DBx__DB4__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN +#define SCSI_In_DBx__DB4__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ +#define SCSI_In_DBx__DB4__SLW CYREG_PRT12_SLW +#define SCSI_In_DBx__DB5__AG CYREG_PRT12_AG +#define SCSI_In_DBx__DB5__BIE CYREG_PRT12_BIE +#define SCSI_In_DBx__DB5__BIT_MASK CYREG_PRT12_BIT_MASK +#define SCSI_In_DBx__DB5__BYP CYREG_PRT12_BYP +#define SCSI_In_DBx__DB5__DM0 CYREG_PRT12_DM0 +#define SCSI_In_DBx__DB5__DM1 CYREG_PRT12_DM1 +#define SCSI_In_DBx__DB5__DM2 CYREG_PRT12_DM2 +#define SCSI_In_DBx__DB5__DR CYREG_PRT12_DR +#define SCSI_In_DBx__DB5__INP_DIS CYREG_PRT12_INP_DIS +#define SCSI_In_DBx__DB5__MASK 0x10u +#define SCSI_In_DBx__DB5__PC CYREG_PRT12_PC4 +#define SCSI_In_DBx__DB5__PORT 12u +#define SCSI_In_DBx__DB5__PRT CYREG_PRT12_PRT +#define SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN +#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 +#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 +#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 +#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 +#define SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT +#define SCSI_In_DBx__DB5__PS CYREG_PRT12_PS +#define SCSI_In_DBx__DB5__SHIFT 4 +#define SCSI_In_DBx__DB5__SIO_CFG CYREG_PRT12_SIO_CFG +#define SCSI_In_DBx__DB5__SIO_DIFF CYREG_PRT12_SIO_DIFF +#define SCSI_In_DBx__DB5__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN +#define SCSI_In_DBx__DB5__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ +#define SCSI_In_DBx__DB5__SLW CYREG_PRT12_SLW +#define SCSI_In_DBx__DB6__AG CYREG_PRT2_AG +#define SCSI_In_DBx__DB6__AMUX CYREG_PRT2_AMUX +#define SCSI_In_DBx__DB6__BIE CYREG_PRT2_BIE +#define SCSI_In_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_In_DBx__DB6__BYP CYREG_PRT2_BYP +#define SCSI_In_DBx__DB6__CTL CYREG_PRT2_CTL +#define SCSI_In_DBx__DB6__DM0 CYREG_PRT2_DM0 +#define SCSI_In_DBx__DB6__DM1 CYREG_PRT2_DM1 +#define SCSI_In_DBx__DB6__DM2 CYREG_PRT2_DM2 +#define SCSI_In_DBx__DB6__DR CYREG_PRT2_DR +#define SCSI_In_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_In_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_In_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_In_DBx__DB6__MASK 0x20u +#define SCSI_In_DBx__DB6__PC CYREG_PRT2_PC5 +#define SCSI_In_DBx__DB6__PORT 2u +#define SCSI_In_DBx__DB6__PRT CYREG_PRT2_PRT +#define SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_In_DBx__DB6__PS CYREG_PRT2_PS +#define SCSI_In_DBx__DB6__SHIFT 5 +#define SCSI_In_DBx__DB6__SLW CYREG_PRT2_SLW +#define SCSI_In_DBx__DB7__AG CYREG_PRT2_AG +#define SCSI_In_DBx__DB7__AMUX CYREG_PRT2_AMUX +#define SCSI_In_DBx__DB7__BIE CYREG_PRT2_BIE +#define SCSI_In_DBx__DB7__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_In_DBx__DB7__BYP CYREG_PRT2_BYP +#define SCSI_In_DBx__DB7__CTL CYREG_PRT2_CTL +#define SCSI_In_DBx__DB7__DM0 CYREG_PRT2_DM0 +#define SCSI_In_DBx__DB7__DM1 CYREG_PRT2_DM1 +#define SCSI_In_DBx__DB7__DM2 CYREG_PRT2_DM2 +#define SCSI_In_DBx__DB7__DR CYREG_PRT2_DR +#define SCSI_In_DBx__DB7__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_In_DBx__DB7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_In_DBx__DB7__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_In_DBx__DB7__MASK 0x10u +#define SCSI_In_DBx__DB7__PC CYREG_PRT2_PC4 +#define SCSI_In_DBx__DB7__PORT 2u +#define SCSI_In_DBx__DB7__PRT CYREG_PRT2_PRT +#define SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_In_DBx__DB7__PS CYREG_PRT2_PS +#define SCSI_In_DBx__DB7__SHIFT 4 +#define SCSI_In_DBx__DB7__SLW CYREG_PRT2_SLW + +/* SD_Data_Clk */ +#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0 +#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1 +#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2 +#define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u +#define SD_Data_Clk__INDEX 0x00u +#define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2 +#define SD_Data_Clk__PM_ACT_MSK 0x01u +#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2 +#define SD_Data_Clk__PM_STBY_MSK 0x01u + +/* SD_Init_Clk */ +#define SD_Init_Clk__CFG0 CYREG_CLKDIST_DCFG1_CFG0 +#define SD_Init_Clk__CFG1 CYREG_CLKDIST_DCFG1_CFG1 +#define SD_Init_Clk__CFG2 CYREG_CLKDIST_DCFG1_CFG2 +#define SD_Init_Clk__CFG2_SRC_SEL_MASK 0x07u +#define SD_Init_Clk__INDEX 0x01u +#define SD_Init_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2 +#define SD_Init_Clk__PM_ACT_MSK 0x02u +#define SD_Init_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2 +#define SD_Init_Clk__PM_STBY_MSK 0x02u + +/* scsiTarget */ +#define scsiTarget_StatusReg__0__MASK 0x01u +#define scsiTarget_StatusReg__0__POS 0 +#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL +#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB13_14_ST +#define scsiTarget_StatusReg__1__MASK 0x02u +#define scsiTarget_StatusReg__1__POS 1 +#define scsiTarget_StatusReg__2__MASK 0x04u +#define scsiTarget_StatusReg__2__POS 2 +#define scsiTarget_StatusReg__3__MASK 0x08u +#define scsiTarget_StatusReg__3__POS 3 +#define scsiTarget_StatusReg__MASK 0x0Fu +#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB13_MSK +#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB13_ACTL +#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB13_ST +#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL +#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB10_11_ST +#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB10_MSK +#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL +#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL +#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB10_ACTL +#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB10_ST_CTL +#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB10_ST_CTL +#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB10_ST +#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL +#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL +#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL +#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL +#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL +#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK +#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK +#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK +#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK +#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL +#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB10_CTL +#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL +#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB10_CTL +#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL +#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL +#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB10_MSK +#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL +#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB10_11_A0 +#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB10_11_A1 +#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB10_11_D0 +#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB10_11_D1 +#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL +#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB10_11_F0 +#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB10_11_F1 +#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB10_A0_A1 +#define scsiTarget_datapath__A0_REG CYREG_B0_UDB10_A0 +#define scsiTarget_datapath__A1_REG CYREG_B0_UDB10_A1 +#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB10_D0_D1 +#define scsiTarget_datapath__D0_REG CYREG_B0_UDB10_D0 +#define scsiTarget_datapath__D1_REG CYREG_B0_UDB10_D1 +#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB10_ACTL +#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB10_F0_F1 +#define scsiTarget_datapath__F0_REG CYREG_B0_UDB10_F0 +#define scsiTarget_datapath__F1_REG CYREG_B0_UDB10_F1 +#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL +#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL + +/* SD_Clk_Ctl */ +#define SD_Clk_Ctl_Sync_ctrl_reg__0__MASK 0x01u +#define SD_Clk_Ctl_Sync_ctrl_reg__0__POS 0 +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK +#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL +#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__MASK 0x01u +#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL +#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK +#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL + +/* USBFS_ep_0 */ +#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_0__INTC_MASK 0x1000000u +#define USBFS_ep_0__INTC_NUMBER 24u +#define USBFS_ep_0__INTC_PRIOR_NUM 7u +#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24 +#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* USBFS_ep_1 */ +#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_1__INTC_MASK 0x01u +#define USBFS_ep_1__INTC_NUMBER 0u +#define USBFS_ep_1__INTC_PRIOR_NUM 7u +#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_0 +#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* USBFS_ep_2 */ +#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_2__INTC_MASK 0x02u +#define USBFS_ep_2__INTC_NUMBER 1u +#define USBFS_ep_2__INTC_PRIOR_NUM 7u +#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_1 +#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* USBFS_USB */ +#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG +#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG +#define USBFS_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN +#define USBFS_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR +#define USBFS_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG +#define USBFS_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN +#define USBFS_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR +#define USBFS_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG +#define USBFS_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN +#define USBFS_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR +#define USBFS_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG +#define USBFS_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN +#define USBFS_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR +#define USBFS_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG +#define USBFS_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN +#define USBFS_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR +#define USBFS_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG +#define USBFS_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN +#define USBFS_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR +#define USBFS_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG +#define USBFS_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN +#define USBFS_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR +#define USBFS_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG +#define USBFS_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN +#define USBFS_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR +#define USBFS_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN +#define USBFS_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR +#define USBFS_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR +#define USBFS_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA +#define USBFS_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB +#define USBFS_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA +#define USBFS_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB +#define USBFS_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR +#define USBFS_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA +#define USBFS_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB +#define USBFS_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA +#define USBFS_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB +#define USBFS_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR +#define USBFS_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA +#define USBFS_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB +#define USBFS_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA +#define USBFS_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB +#define USBFS_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR +#define USBFS_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA +#define USBFS_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB +#define USBFS_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA +#define USBFS_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB +#define USBFS_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR +#define USBFS_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA +#define USBFS_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB +#define USBFS_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA +#define USBFS_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB +#define USBFS_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR +#define USBFS_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA +#define USBFS_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB +#define USBFS_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA +#define USBFS_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB +#define USBFS_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR +#define USBFS_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA +#define USBFS_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB +#define USBFS_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA +#define USBFS_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB +#define USBFS_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR +#define USBFS_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA +#define USBFS_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB +#define USBFS_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA +#define USBFS_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB +#define USBFS_USB__BUF_SIZE CYREG_USB_BUF_SIZE +#define USBFS_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT +#define USBFS_USB__CR0 CYREG_USB_CR0 +#define USBFS_USB__CR1 CYREG_USB_CR1 +#define USBFS_USB__CWA CYREG_USB_CWA +#define USBFS_USB__CWA_MSB CYREG_USB_CWA_MSB +#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES +#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB +#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG +#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT +#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR +#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0 +#define USBFS_USB__EP0_DR1 CYREG_USB_EP0_DR1 +#define USBFS_USB__EP0_DR2 CYREG_USB_EP0_DR2 +#define USBFS_USB__EP0_DR3 CYREG_USB_EP0_DR3 +#define USBFS_USB__EP0_DR4 CYREG_USB_EP0_DR4 +#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5 +#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6 +#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7 +#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE +#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE +#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE +#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5 +#define USBFS_USB__PM_ACT_MSK 0x01u +#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5 +#define USBFS_USB__PM_STBY_MSK 0x01u +#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0 +#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1 +#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0 +#define USBFS_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0 +#define USBFS_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1 +#define USBFS_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0 +#define USBFS_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0 +#define USBFS_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1 +#define USBFS_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0 +#define USBFS_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0 +#define USBFS_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1 +#define USBFS_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0 +#define USBFS_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0 +#define USBFS_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1 +#define USBFS_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0 +#define USBFS_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0 +#define USBFS_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1 +#define USBFS_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0 +#define USBFS_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0 +#define USBFS_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1 +#define USBFS_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0 +#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0 +#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1 +#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0 +#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN +#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR +#define USBFS_USB__SOF0 CYREG_USB_SOF0 +#define USBFS_USB__SOF1 CYREG_USB_SOF1 +#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0 +#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1 +#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN + +/* SCSI_ATN */ +#define SCSI_ATN__0__MASK 0x01u +#define SCSI_ATN__0__PC CYREG_PRT2_PC0 +#define SCSI_ATN__0__PORT 2u +#define SCSI_ATN__0__SHIFT 0 +#define SCSI_ATN__AG CYREG_PRT2_AG +#define SCSI_ATN__AMUX CYREG_PRT2_AMUX +#define SCSI_ATN__BIE CYREG_PRT2_BIE +#define SCSI_ATN__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_ATN__BYP CYREG_PRT2_BYP +#define SCSI_ATN__CTL CYREG_PRT2_CTL +#define SCSI_ATN__DM0 CYREG_PRT2_DM0 +#define SCSI_ATN__DM1 CYREG_PRT2_DM1 +#define SCSI_ATN__DM2 CYREG_PRT2_DM2 +#define SCSI_ATN__DR CYREG_PRT2_DR +#define SCSI_ATN__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_ATN__INT__MASK 0x01u +#define SCSI_ATN__INT__PC CYREG_PRT2_PC0 +#define SCSI_ATN__INT__PORT 2u +#define SCSI_ATN__INT__SHIFT 0 +#define SCSI_ATN__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_ATN__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_ATN__MASK 0x01u +#define SCSI_ATN__PORT 2u +#define SCSI_ATN__PRT CYREG_PRT2_PRT +#define SCSI_ATN__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_ATN__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_ATN__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_ATN__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_ATN__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_ATN__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_ATN__PS CYREG_PRT2_PS +#define SCSI_ATN__SHIFT 0 +#define SCSI_ATN__SLW CYREG_PRT2_SLW + +/* SCSI_Out */ +#define SCSI_Out__0__AG CYREG_PRT15_AG +#define SCSI_Out__0__AMUX CYREG_PRT15_AMUX +#define SCSI_Out__0__BIE CYREG_PRT15_BIE +#define SCSI_Out__0__BIT_MASK CYREG_PRT15_BIT_MASK +#define SCSI_Out__0__BYP CYREG_PRT15_BYP +#define SCSI_Out__0__CTL CYREG_PRT15_CTL +#define SCSI_Out__0__DM0 CYREG_PRT15_DM0 +#define SCSI_Out__0__DM1 CYREG_PRT15_DM1 +#define SCSI_Out__0__DM2 CYREG_PRT15_DM2 +#define SCSI_Out__0__DR CYREG_PRT15_DR +#define SCSI_Out__0__INP_DIS CYREG_PRT15_INP_DIS +#define SCSI_Out__0__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define SCSI_Out__0__LCD_EN CYREG_PRT15_LCD_EN +#define SCSI_Out__0__MASK 0x20u +#define SCSI_Out__0__PC CYREG_IO_PC_PRT15_PC5 +#define SCSI_Out__0__PORT 15u +#define SCSI_Out__0__PRT CYREG_PRT15_PRT +#define SCSI_Out__0__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define SCSI_Out__0__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define SCSI_Out__0__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define SCSI_Out__0__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define SCSI_Out__0__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define SCSI_Out__0__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define SCSI_Out__0__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define SCSI_Out__0__PS CYREG_PRT15_PS +#define SCSI_Out__0__SHIFT 5 +#define SCSI_Out__0__SLW CYREG_PRT15_SLW +#define SCSI_Out__1__AG CYREG_PRT15_AG +#define SCSI_Out__1__AMUX CYREG_PRT15_AMUX +#define SCSI_Out__1__BIE CYREG_PRT15_BIE +#define SCSI_Out__1__BIT_MASK CYREG_PRT15_BIT_MASK +#define SCSI_Out__1__BYP CYREG_PRT15_BYP +#define SCSI_Out__1__CTL CYREG_PRT15_CTL +#define SCSI_Out__1__DM0 CYREG_PRT15_DM0 +#define SCSI_Out__1__DM1 CYREG_PRT15_DM1 +#define SCSI_Out__1__DM2 CYREG_PRT15_DM2 +#define SCSI_Out__1__DR CYREG_PRT15_DR +#define SCSI_Out__1__INP_DIS CYREG_PRT15_INP_DIS +#define SCSI_Out__1__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define SCSI_Out__1__LCD_EN CYREG_PRT15_LCD_EN +#define SCSI_Out__1__MASK 0x10u +#define SCSI_Out__1__PC CYREG_IO_PC_PRT15_PC4 +#define SCSI_Out__1__PORT 15u +#define SCSI_Out__1__PRT CYREG_PRT15_PRT +#define SCSI_Out__1__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define SCSI_Out__1__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define SCSI_Out__1__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define SCSI_Out__1__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define SCSI_Out__1__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define SCSI_Out__1__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define SCSI_Out__1__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define SCSI_Out__1__PS CYREG_PRT15_PS +#define SCSI_Out__1__SHIFT 4 +#define SCSI_Out__1__SLW CYREG_PRT15_SLW +#define SCSI_Out__2__AG CYREG_PRT6_AG +#define SCSI_Out__2__AMUX CYREG_PRT6_AMUX +#define SCSI_Out__2__BIE CYREG_PRT6_BIE +#define SCSI_Out__2__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out__2__BYP CYREG_PRT6_BYP +#define SCSI_Out__2__CTL CYREG_PRT6_CTL +#define SCSI_Out__2__DM0 CYREG_PRT6_DM0 +#define SCSI_Out__2__DM1 CYREG_PRT6_DM1 +#define SCSI_Out__2__DM2 CYREG_PRT6_DM2 +#define SCSI_Out__2__DR CYREG_PRT6_DR +#define SCSI_Out__2__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out__2__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out__2__MASK 0x02u +#define SCSI_Out__2__PC CYREG_PRT6_PC1 +#define SCSI_Out__2__PORT 6u +#define SCSI_Out__2__PRT CYREG_PRT6_PRT +#define SCSI_Out__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out__2__PS CYREG_PRT6_PS +#define SCSI_Out__2__SHIFT 1 +#define SCSI_Out__2__SLW CYREG_PRT6_SLW +#define SCSI_Out__3__AG CYREG_PRT6_AG +#define SCSI_Out__3__AMUX CYREG_PRT6_AMUX +#define SCSI_Out__3__BIE CYREG_PRT6_BIE +#define SCSI_Out__3__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out__3__BYP CYREG_PRT6_BYP +#define SCSI_Out__3__CTL CYREG_PRT6_CTL +#define SCSI_Out__3__DM0 CYREG_PRT6_DM0 +#define SCSI_Out__3__DM1 CYREG_PRT6_DM1 +#define SCSI_Out__3__DM2 CYREG_PRT6_DM2 +#define SCSI_Out__3__DR CYREG_PRT6_DR +#define SCSI_Out__3__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out__3__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out__3__MASK 0x01u +#define SCSI_Out__3__PC CYREG_PRT6_PC0 +#define SCSI_Out__3__PORT 6u +#define SCSI_Out__3__PRT CYREG_PRT6_PRT +#define SCSI_Out__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out__3__PS CYREG_PRT6_PS +#define SCSI_Out__3__SHIFT 0 +#define SCSI_Out__3__SLW CYREG_PRT6_SLW +#define SCSI_Out__4__AG CYREG_PRT4_AG +#define SCSI_Out__4__AMUX CYREG_PRT4_AMUX +#define SCSI_Out__4__BIE CYREG_PRT4_BIE +#define SCSI_Out__4__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Out__4__BYP CYREG_PRT4_BYP +#define SCSI_Out__4__CTL CYREG_PRT4_CTL +#define SCSI_Out__4__DM0 CYREG_PRT4_DM0 +#define SCSI_Out__4__DM1 CYREG_PRT4_DM1 +#define SCSI_Out__4__DM2 CYREG_PRT4_DM2 +#define SCSI_Out__4__DR CYREG_PRT4_DR +#define SCSI_Out__4__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Out__4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Out__4__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Out__4__MASK 0x20u +#define SCSI_Out__4__PC CYREG_PRT4_PC5 +#define SCSI_Out__4__PORT 4u +#define SCSI_Out__4__PRT CYREG_PRT4_PRT +#define SCSI_Out__4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Out__4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Out__4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Out__4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Out__4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Out__4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Out__4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Out__4__PS CYREG_PRT4_PS +#define SCSI_Out__4__SHIFT 5 +#define SCSI_Out__4__SLW CYREG_PRT4_SLW +#define SCSI_Out__5__AG CYREG_PRT4_AG +#define SCSI_Out__5__AMUX CYREG_PRT4_AMUX +#define SCSI_Out__5__BIE CYREG_PRT4_BIE +#define SCSI_Out__5__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Out__5__BYP CYREG_PRT4_BYP +#define SCSI_Out__5__CTL CYREG_PRT4_CTL +#define SCSI_Out__5__DM0 CYREG_PRT4_DM0 +#define SCSI_Out__5__DM1 CYREG_PRT4_DM1 +#define SCSI_Out__5__DM2 CYREG_PRT4_DM2 +#define SCSI_Out__5__DR CYREG_PRT4_DR +#define SCSI_Out__5__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Out__5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Out__5__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Out__5__MASK 0x10u +#define SCSI_Out__5__PC CYREG_PRT4_PC4 +#define SCSI_Out__5__PORT 4u +#define SCSI_Out__5__PRT CYREG_PRT4_PRT +#define SCSI_Out__5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Out__5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Out__5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Out__5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Out__5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Out__5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Out__5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Out__5__PS CYREG_PRT4_PS +#define SCSI_Out__5__SHIFT 4 +#define SCSI_Out__5__SLW CYREG_PRT4_SLW +#define SCSI_Out__6__AG CYREG_PRT0_AG +#define SCSI_Out__6__AMUX CYREG_PRT0_AMUX +#define SCSI_Out__6__BIE CYREG_PRT0_BIE +#define SCSI_Out__6__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Out__6__BYP CYREG_PRT0_BYP +#define SCSI_Out__6__CTL CYREG_PRT0_CTL +#define SCSI_Out__6__DM0 CYREG_PRT0_DM0 +#define SCSI_Out__6__DM1 CYREG_PRT0_DM1 +#define SCSI_Out__6__DM2 CYREG_PRT0_DM2 +#define SCSI_Out__6__DR CYREG_PRT0_DR +#define SCSI_Out__6__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Out__6__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Out__6__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Out__6__MASK 0x80u +#define SCSI_Out__6__PC CYREG_PRT0_PC7 +#define SCSI_Out__6__PORT 0u +#define SCSI_Out__6__PRT CYREG_PRT0_PRT +#define SCSI_Out__6__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Out__6__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Out__6__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Out__6__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Out__6__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Out__6__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Out__6__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Out__6__PS CYREG_PRT0_PS +#define SCSI_Out__6__SHIFT 7 +#define SCSI_Out__6__SLW CYREG_PRT0_SLW +#define SCSI_Out__7__AG CYREG_PRT0_AG +#define SCSI_Out__7__AMUX CYREG_PRT0_AMUX +#define SCSI_Out__7__BIE CYREG_PRT0_BIE +#define SCSI_Out__7__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Out__7__BYP CYREG_PRT0_BYP +#define SCSI_Out__7__CTL CYREG_PRT0_CTL +#define SCSI_Out__7__DM0 CYREG_PRT0_DM0 +#define SCSI_Out__7__DM1 CYREG_PRT0_DM1 +#define SCSI_Out__7__DM2 CYREG_PRT0_DM2 +#define SCSI_Out__7__DR CYREG_PRT0_DR +#define SCSI_Out__7__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Out__7__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Out__7__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Out__7__MASK 0x40u +#define SCSI_Out__7__PC CYREG_PRT0_PC6 +#define SCSI_Out__7__PORT 0u +#define SCSI_Out__7__PRT CYREG_PRT0_PRT +#define SCSI_Out__7__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Out__7__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Out__7__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Out__7__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Out__7__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Out__7__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Out__7__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Out__7__PS CYREG_PRT0_PS +#define SCSI_Out__7__SHIFT 6 +#define SCSI_Out__7__SLW CYREG_PRT0_SLW +#define SCSI_Out__8__AG CYREG_PRT0_AG +#define SCSI_Out__8__AMUX CYREG_PRT0_AMUX +#define SCSI_Out__8__BIE CYREG_PRT0_BIE +#define SCSI_Out__8__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Out__8__BYP CYREG_PRT0_BYP +#define SCSI_Out__8__CTL CYREG_PRT0_CTL +#define SCSI_Out__8__DM0 CYREG_PRT0_DM0 +#define SCSI_Out__8__DM1 CYREG_PRT0_DM1 +#define SCSI_Out__8__DM2 CYREG_PRT0_DM2 +#define SCSI_Out__8__DR CYREG_PRT0_DR +#define SCSI_Out__8__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Out__8__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Out__8__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Out__8__MASK 0x08u +#define SCSI_Out__8__PC CYREG_PRT0_PC3 +#define SCSI_Out__8__PORT 0u +#define SCSI_Out__8__PRT CYREG_PRT0_PRT +#define SCSI_Out__8__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Out__8__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Out__8__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Out__8__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Out__8__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Out__8__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Out__8__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Out__8__PS CYREG_PRT0_PS +#define SCSI_Out__8__SHIFT 3 +#define SCSI_Out__8__SLW CYREG_PRT0_SLW +#define SCSI_Out__9__AG CYREG_PRT0_AG +#define SCSI_Out__9__AMUX CYREG_PRT0_AMUX +#define SCSI_Out__9__BIE CYREG_PRT0_BIE +#define SCSI_Out__9__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Out__9__BYP CYREG_PRT0_BYP +#define SCSI_Out__9__CTL CYREG_PRT0_CTL +#define SCSI_Out__9__DM0 CYREG_PRT0_DM0 +#define SCSI_Out__9__DM1 CYREG_PRT0_DM1 +#define SCSI_Out__9__DM2 CYREG_PRT0_DM2 +#define SCSI_Out__9__DR CYREG_PRT0_DR +#define SCSI_Out__9__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Out__9__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Out__9__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Out__9__MASK 0x04u +#define SCSI_Out__9__PC CYREG_PRT0_PC2 +#define SCSI_Out__9__PORT 0u +#define SCSI_Out__9__PRT CYREG_PRT0_PRT +#define SCSI_Out__9__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Out__9__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Out__9__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Out__9__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Out__9__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Out__9__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Out__9__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Out__9__PS CYREG_PRT0_PS +#define SCSI_Out__9__SHIFT 2 +#define SCSI_Out__9__SLW CYREG_PRT0_SLW +#define SCSI_Out__ACK__AG CYREG_PRT6_AG +#define SCSI_Out__ACK__AMUX CYREG_PRT6_AMUX +#define SCSI_Out__ACK__BIE CYREG_PRT6_BIE +#define SCSI_Out__ACK__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out__ACK__BYP CYREG_PRT6_BYP +#define SCSI_Out__ACK__CTL CYREG_PRT6_CTL +#define SCSI_Out__ACK__DM0 CYREG_PRT6_DM0 +#define SCSI_Out__ACK__DM1 CYREG_PRT6_DM1 +#define SCSI_Out__ACK__DM2 CYREG_PRT6_DM2 +#define SCSI_Out__ACK__DR CYREG_PRT6_DR +#define SCSI_Out__ACK__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out__ACK__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out__ACK__MASK 0x01u +#define SCSI_Out__ACK__PC CYREG_PRT6_PC0 +#define SCSI_Out__ACK__PORT 6u +#define SCSI_Out__ACK__PRT CYREG_PRT6_PRT +#define SCSI_Out__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out__ACK__PS CYREG_PRT6_PS +#define SCSI_Out__ACK__SHIFT 0 +#define SCSI_Out__ACK__SLW CYREG_PRT6_SLW +#define SCSI_Out__ATN__AG CYREG_PRT15_AG +#define SCSI_Out__ATN__AMUX CYREG_PRT15_AMUX +#define SCSI_Out__ATN__BIE CYREG_PRT15_BIE +#define SCSI_Out__ATN__BIT_MASK CYREG_PRT15_BIT_MASK +#define SCSI_Out__ATN__BYP CYREG_PRT15_BYP +#define SCSI_Out__ATN__CTL CYREG_PRT15_CTL +#define SCSI_Out__ATN__DM0 CYREG_PRT15_DM0 +#define SCSI_Out__ATN__DM1 CYREG_PRT15_DM1 +#define SCSI_Out__ATN__DM2 CYREG_PRT15_DM2 +#define SCSI_Out__ATN__DR CYREG_PRT15_DR +#define SCSI_Out__ATN__INP_DIS CYREG_PRT15_INP_DIS +#define SCSI_Out__ATN__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define SCSI_Out__ATN__LCD_EN CYREG_PRT15_LCD_EN +#define SCSI_Out__ATN__MASK 0x10u +#define SCSI_Out__ATN__PC CYREG_IO_PC_PRT15_PC4 +#define SCSI_Out__ATN__PORT 15u +#define SCSI_Out__ATN__PRT CYREG_PRT15_PRT +#define SCSI_Out__ATN__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define SCSI_Out__ATN__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define SCSI_Out__ATN__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define SCSI_Out__ATN__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define SCSI_Out__ATN__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define SCSI_Out__ATN__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define SCSI_Out__ATN__PS CYREG_PRT15_PS +#define SCSI_Out__ATN__SHIFT 4 +#define SCSI_Out__ATN__SLW CYREG_PRT15_SLW +#define SCSI_Out__BSY__AG CYREG_PRT6_AG +#define SCSI_Out__BSY__AMUX CYREG_PRT6_AMUX +#define SCSI_Out__BSY__BIE CYREG_PRT6_BIE +#define SCSI_Out__BSY__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out__BSY__BYP CYREG_PRT6_BYP +#define SCSI_Out__BSY__CTL CYREG_PRT6_CTL +#define SCSI_Out__BSY__DM0 CYREG_PRT6_DM0 +#define SCSI_Out__BSY__DM1 CYREG_PRT6_DM1 +#define SCSI_Out__BSY__DM2 CYREG_PRT6_DM2 +#define SCSI_Out__BSY__DR CYREG_PRT6_DR +#define SCSI_Out__BSY__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out__BSY__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out__BSY__MASK 0x02u +#define SCSI_Out__BSY__PC CYREG_PRT6_PC1 +#define SCSI_Out__BSY__PORT 6u +#define SCSI_Out__BSY__PRT CYREG_PRT6_PRT +#define SCSI_Out__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out__BSY__PS CYREG_PRT6_PS +#define SCSI_Out__BSY__SHIFT 1 +#define SCSI_Out__BSY__SLW CYREG_PRT6_SLW +#define SCSI_Out__CD__AG CYREG_PRT0_AG +#define SCSI_Out__CD__AMUX CYREG_PRT0_AMUX +#define SCSI_Out__CD__BIE CYREG_PRT0_BIE +#define SCSI_Out__CD__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Out__CD__BYP CYREG_PRT0_BYP +#define SCSI_Out__CD__CTL CYREG_PRT0_CTL +#define SCSI_Out__CD__DM0 CYREG_PRT0_DM0 +#define SCSI_Out__CD__DM1 CYREG_PRT0_DM1 +#define SCSI_Out__CD__DM2 CYREG_PRT0_DM2 +#define SCSI_Out__CD__DR CYREG_PRT0_DR +#define SCSI_Out__CD__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Out__CD__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Out__CD__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Out__CD__MASK 0x40u +#define SCSI_Out__CD__PC CYREG_PRT0_PC6 +#define SCSI_Out__CD__PORT 0u +#define SCSI_Out__CD__PRT CYREG_PRT0_PRT +#define SCSI_Out__CD__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Out__CD__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Out__CD__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Out__CD__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Out__CD__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Out__CD__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Out__CD__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Out__CD__PS CYREG_PRT0_PS +#define SCSI_Out__CD__SHIFT 6 +#define SCSI_Out__CD__SLW CYREG_PRT0_SLW +#define SCSI_Out__DBP_raw__AG CYREG_PRT15_AG +#define SCSI_Out__DBP_raw__AMUX CYREG_PRT15_AMUX +#define SCSI_Out__DBP_raw__BIE CYREG_PRT15_BIE +#define SCSI_Out__DBP_raw__BIT_MASK CYREG_PRT15_BIT_MASK +#define SCSI_Out__DBP_raw__BYP CYREG_PRT15_BYP +#define SCSI_Out__DBP_raw__CTL CYREG_PRT15_CTL +#define SCSI_Out__DBP_raw__DM0 CYREG_PRT15_DM0 +#define SCSI_Out__DBP_raw__DM1 CYREG_PRT15_DM1 +#define SCSI_Out__DBP_raw__DM2 CYREG_PRT15_DM2 +#define SCSI_Out__DBP_raw__DR CYREG_PRT15_DR +#define SCSI_Out__DBP_raw__INP_DIS CYREG_PRT15_INP_DIS +#define SCSI_Out__DBP_raw__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define SCSI_Out__DBP_raw__LCD_EN CYREG_PRT15_LCD_EN +#define SCSI_Out__DBP_raw__MASK 0x20u +#define SCSI_Out__DBP_raw__PC CYREG_IO_PC_PRT15_PC5 +#define SCSI_Out__DBP_raw__PORT 15u +#define SCSI_Out__DBP_raw__PRT CYREG_PRT15_PRT +#define SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define SCSI_Out__DBP_raw__PS CYREG_PRT15_PS +#define SCSI_Out__DBP_raw__SHIFT 5 +#define SCSI_Out__DBP_raw__SLW CYREG_PRT15_SLW +#define SCSI_Out__IO_raw__AG CYREG_PRT0_AG +#define SCSI_Out__IO_raw__AMUX CYREG_PRT0_AMUX +#define SCSI_Out__IO_raw__BIE CYREG_PRT0_BIE +#define SCSI_Out__IO_raw__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Out__IO_raw__BYP CYREG_PRT0_BYP +#define SCSI_Out__IO_raw__CTL CYREG_PRT0_CTL +#define SCSI_Out__IO_raw__DM0 CYREG_PRT0_DM0 +#define SCSI_Out__IO_raw__DM1 CYREG_PRT0_DM1 +#define SCSI_Out__IO_raw__DM2 CYREG_PRT0_DM2 +#define SCSI_Out__IO_raw__DR CYREG_PRT0_DR +#define SCSI_Out__IO_raw__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Out__IO_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Out__IO_raw__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Out__IO_raw__MASK 0x04u +#define SCSI_Out__IO_raw__PC CYREG_PRT0_PC2 +#define SCSI_Out__IO_raw__PORT 0u +#define SCSI_Out__IO_raw__PRT CYREG_PRT0_PRT +#define SCSI_Out__IO_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Out__IO_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Out__IO_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Out__IO_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Out__IO_raw__PS CYREG_PRT0_PS +#define SCSI_Out__IO_raw__SHIFT 2 +#define SCSI_Out__IO_raw__SLW CYREG_PRT0_SLW +#define SCSI_Out__MSG__AG CYREG_PRT4_AG +#define SCSI_Out__MSG__AMUX CYREG_PRT4_AMUX +#define SCSI_Out__MSG__BIE CYREG_PRT4_BIE +#define SCSI_Out__MSG__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Out__MSG__BYP CYREG_PRT4_BYP +#define SCSI_Out__MSG__CTL CYREG_PRT4_CTL +#define SCSI_Out__MSG__DM0 CYREG_PRT4_DM0 +#define SCSI_Out__MSG__DM1 CYREG_PRT4_DM1 +#define SCSI_Out__MSG__DM2 CYREG_PRT4_DM2 +#define SCSI_Out__MSG__DR CYREG_PRT4_DR +#define SCSI_Out__MSG__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Out__MSG__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Out__MSG__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Out__MSG__MASK 0x10u +#define SCSI_Out__MSG__PC CYREG_PRT4_PC4 +#define SCSI_Out__MSG__PORT 4u +#define SCSI_Out__MSG__PRT CYREG_PRT4_PRT +#define SCSI_Out__MSG__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Out__MSG__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Out__MSG__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Out__MSG__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Out__MSG__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Out__MSG__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Out__MSG__PS CYREG_PRT4_PS +#define SCSI_Out__MSG__SHIFT 4 +#define SCSI_Out__MSG__SLW CYREG_PRT4_SLW +#define SCSI_Out__REQ__AG CYREG_PRT0_AG +#define SCSI_Out__REQ__AMUX CYREG_PRT0_AMUX +#define SCSI_Out__REQ__BIE CYREG_PRT0_BIE +#define SCSI_Out__REQ__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Out__REQ__BYP CYREG_PRT0_BYP +#define SCSI_Out__REQ__CTL CYREG_PRT0_CTL +#define SCSI_Out__REQ__DM0 CYREG_PRT0_DM0 +#define SCSI_Out__REQ__DM1 CYREG_PRT0_DM1 +#define SCSI_Out__REQ__DM2 CYREG_PRT0_DM2 +#define SCSI_Out__REQ__DR CYREG_PRT0_DR +#define SCSI_Out__REQ__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Out__REQ__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Out__REQ__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Out__REQ__MASK 0x08u +#define SCSI_Out__REQ__PC CYREG_PRT0_PC3 +#define SCSI_Out__REQ__PORT 0u +#define SCSI_Out__REQ__PRT CYREG_PRT0_PRT +#define SCSI_Out__REQ__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Out__REQ__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Out__REQ__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Out__REQ__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Out__REQ__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Out__REQ__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Out__REQ__PS CYREG_PRT0_PS +#define SCSI_Out__REQ__SHIFT 3 +#define SCSI_Out__REQ__SLW CYREG_PRT0_SLW +#define SCSI_Out__RST__AG CYREG_PRT4_AG +#define SCSI_Out__RST__AMUX CYREG_PRT4_AMUX +#define SCSI_Out__RST__BIE CYREG_PRT4_BIE +#define SCSI_Out__RST__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Out__RST__BYP CYREG_PRT4_BYP +#define SCSI_Out__RST__CTL CYREG_PRT4_CTL +#define SCSI_Out__RST__DM0 CYREG_PRT4_DM0 +#define SCSI_Out__RST__DM1 CYREG_PRT4_DM1 +#define SCSI_Out__RST__DM2 CYREG_PRT4_DM2 +#define SCSI_Out__RST__DR CYREG_PRT4_DR +#define SCSI_Out__RST__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Out__RST__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Out__RST__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Out__RST__MASK 0x20u +#define SCSI_Out__RST__PC CYREG_PRT4_PC5 +#define SCSI_Out__RST__PORT 4u +#define SCSI_Out__RST__PRT CYREG_PRT4_PRT +#define SCSI_Out__RST__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Out__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Out__RST__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Out__RST__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Out__RST__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Out__RST__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Out__RST__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Out__RST__PS CYREG_PRT4_PS +#define SCSI_Out__RST__SHIFT 5 +#define SCSI_Out__RST__SLW CYREG_PRT4_SLW +#define SCSI_Out__SEL__AG CYREG_PRT0_AG +#define SCSI_Out__SEL__AMUX CYREG_PRT0_AMUX +#define SCSI_Out__SEL__BIE CYREG_PRT0_BIE +#define SCSI_Out__SEL__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Out__SEL__BYP CYREG_PRT0_BYP +#define SCSI_Out__SEL__CTL CYREG_PRT0_CTL +#define SCSI_Out__SEL__DM0 CYREG_PRT0_DM0 +#define SCSI_Out__SEL__DM1 CYREG_PRT0_DM1 +#define SCSI_Out__SEL__DM2 CYREG_PRT0_DM2 +#define SCSI_Out__SEL__DR CYREG_PRT0_DR +#define SCSI_Out__SEL__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Out__SEL__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Out__SEL__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Out__SEL__MASK 0x80u +#define SCSI_Out__SEL__PC CYREG_PRT0_PC7 +#define SCSI_Out__SEL__PORT 0u +#define SCSI_Out__SEL__PRT CYREG_PRT0_PRT +#define SCSI_Out__SEL__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Out__SEL__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Out__SEL__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Out__SEL__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Out__SEL__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Out__SEL__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Out__SEL__PS CYREG_PRT0_PS +#define SCSI_Out__SEL__SHIFT 7 +#define SCSI_Out__SEL__SLW CYREG_PRT0_SLW + +/* SCSI_RST */ +#define SCSI_RST__0__MASK 0x80u +#define SCSI_RST__0__PC CYREG_PRT4_PC7 +#define SCSI_RST__0__PORT 4u +#define SCSI_RST__0__SHIFT 7 +#define SCSI_RST__AG CYREG_PRT4_AG +#define SCSI_RST__AMUX CYREG_PRT4_AMUX +#define SCSI_RST__BIE CYREG_PRT4_BIE +#define SCSI_RST__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_RST__BYP CYREG_PRT4_BYP +#define SCSI_RST__CTL CYREG_PRT4_CTL +#define SCSI_RST__DM0 CYREG_PRT4_DM0 +#define SCSI_RST__DM1 CYREG_PRT4_DM1 +#define SCSI_RST__DM2 CYREG_PRT4_DM2 +#define SCSI_RST__DR CYREG_PRT4_DR +#define SCSI_RST__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_RST__INTSTAT CYREG_PICU4_INTSTAT +#define SCSI_RST__INT__MASK 0x80u +#define SCSI_RST__INT__PC CYREG_PRT4_PC7 +#define SCSI_RST__INT__PORT 4u +#define SCSI_RST__INT__SHIFT 7 +#define SCSI_RST__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_RST__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_RST__MASK 0x80u +#define SCSI_RST__PORT 4u +#define SCSI_RST__PRT CYREG_PRT4_PRT +#define SCSI_RST__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_RST__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_RST__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_RST__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_RST__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_RST__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_RST__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_RST__PS CYREG_PRT4_PS +#define SCSI_RST__SHIFT 7 +#define SCSI_RST__SLW CYREG_PRT4_SLW +#define SCSI_RST__SNAP CYREG_PICU4_SNAP + +/* USBFS_Dm */ +#define USBFS_Dm__0__MASK 0x80u +#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1 +#define USBFS_Dm__0__PORT 15u +#define USBFS_Dm__0__SHIFT 7 +#define USBFS_Dm__AG CYREG_PRT15_AG +#define USBFS_Dm__AMUX CYREG_PRT15_AMUX +#define USBFS_Dm__BIE CYREG_PRT15_BIE +#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK +#define USBFS_Dm__BYP CYREG_PRT15_BYP +#define USBFS_Dm__CTL CYREG_PRT15_CTL +#define USBFS_Dm__DM0 CYREG_PRT15_DM0 +#define USBFS_Dm__DM1 CYREG_PRT15_DM1 +#define USBFS_Dm__DM2 CYREG_PRT15_DM2 +#define USBFS_Dm__DR CYREG_PRT15_DR +#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS +#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN +#define USBFS_Dm__MASK 0x80u +#define USBFS_Dm__PORT 15u +#define USBFS_Dm__PRT CYREG_PRT15_PRT +#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define USBFS_Dm__PS CYREG_PRT15_PS +#define USBFS_Dm__SHIFT 7 +#define USBFS_Dm__SLW CYREG_PRT15_SLW + +/* USBFS_Dp */ +#define USBFS_Dp__0__MASK 0x40u +#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0 +#define USBFS_Dp__0__PORT 15u +#define USBFS_Dp__0__SHIFT 6 +#define USBFS_Dp__AG CYREG_PRT15_AG +#define USBFS_Dp__AMUX CYREG_PRT15_AMUX +#define USBFS_Dp__BIE CYREG_PRT15_BIE +#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK +#define USBFS_Dp__BYP CYREG_PRT15_BYP +#define USBFS_Dp__CTL CYREG_PRT15_CTL +#define USBFS_Dp__DM0 CYREG_PRT15_DM0 +#define USBFS_Dp__DM1 CYREG_PRT15_DM1 +#define USBFS_Dp__DM2 CYREG_PRT15_DM2 +#define USBFS_Dp__DR CYREG_PRT15_DR +#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS +#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT +#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN +#define USBFS_Dp__MASK 0x40u +#define USBFS_Dp__PORT 15u +#define USBFS_Dp__PRT CYREG_PRT15_PRT +#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define USBFS_Dp__PS CYREG_PRT15_PS +#define USBFS_Dp__SHIFT 6 +#define USBFS_Dp__SLW CYREG_PRT15_SLW +#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15 + +/* SCSI_In */ +#define SCSI_In__0__AG CYREG_PRT2_AG +#define SCSI_In__0__AMUX CYREG_PRT2_AMUX +#define SCSI_In__0__BIE CYREG_PRT2_BIE +#define SCSI_In__0__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_In__0__BYP CYREG_PRT2_BYP +#define SCSI_In__0__CTL CYREG_PRT2_CTL +#define SCSI_In__0__DM0 CYREG_PRT2_DM0 +#define SCSI_In__0__DM1 CYREG_PRT2_DM1 +#define SCSI_In__0__DM2 CYREG_PRT2_DM2 +#define SCSI_In__0__DR CYREG_PRT2_DR +#define SCSI_In__0__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_In__0__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_In__0__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_In__0__MASK 0x02u +#define SCSI_In__0__PC CYREG_PRT2_PC1 +#define SCSI_In__0__PORT 2u +#define SCSI_In__0__PRT CYREG_PRT2_PRT +#define SCSI_In__0__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_In__0__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_In__0__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_In__0__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_In__0__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_In__0__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_In__0__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_In__0__PS CYREG_PRT2_PS +#define SCSI_In__0__SHIFT 1 +#define SCSI_In__0__SLW CYREG_PRT2_SLW +#define SCSI_In__1__AG CYREG_PRT6_AG +#define SCSI_In__1__AMUX CYREG_PRT6_AMUX +#define SCSI_In__1__BIE CYREG_PRT6_BIE +#define SCSI_In__1__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_In__1__BYP CYREG_PRT6_BYP +#define SCSI_In__1__CTL CYREG_PRT6_CTL +#define SCSI_In__1__DM0 CYREG_PRT6_DM0 +#define SCSI_In__1__DM1 CYREG_PRT6_DM1 +#define SCSI_In__1__DM2 CYREG_PRT6_DM2 +#define SCSI_In__1__DR CYREG_PRT6_DR +#define SCSI_In__1__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_In__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_In__1__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_In__1__MASK 0x08u +#define SCSI_In__1__PC CYREG_PRT6_PC3 +#define SCSI_In__1__PORT 6u +#define SCSI_In__1__PRT CYREG_PRT6_PRT +#define SCSI_In__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_In__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_In__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_In__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_In__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_In__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_In__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_In__1__PS CYREG_PRT6_PS +#define SCSI_In__1__SHIFT 3 +#define SCSI_In__1__SLW CYREG_PRT6_SLW +#define SCSI_In__2__AG CYREG_PRT6_AG +#define SCSI_In__2__AMUX CYREG_PRT6_AMUX +#define SCSI_In__2__BIE CYREG_PRT6_BIE +#define SCSI_In__2__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_In__2__BYP CYREG_PRT6_BYP +#define SCSI_In__2__CTL CYREG_PRT6_CTL +#define SCSI_In__2__DM0 CYREG_PRT6_DM0 +#define SCSI_In__2__DM1 CYREG_PRT6_DM1 +#define SCSI_In__2__DM2 CYREG_PRT6_DM2 +#define SCSI_In__2__DR CYREG_PRT6_DR +#define SCSI_In__2__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_In__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_In__2__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_In__2__MASK 0x04u +#define SCSI_In__2__PC CYREG_PRT6_PC2 +#define SCSI_In__2__PORT 6u +#define SCSI_In__2__PRT CYREG_PRT6_PRT +#define SCSI_In__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_In__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_In__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_In__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_In__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_In__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_In__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_In__2__PS CYREG_PRT6_PS +#define SCSI_In__2__SHIFT 2 +#define SCSI_In__2__SLW CYREG_PRT6_SLW +#define SCSI_In__3__AG CYREG_PRT4_AG +#define SCSI_In__3__AMUX CYREG_PRT4_AMUX +#define SCSI_In__3__BIE CYREG_PRT4_BIE +#define SCSI_In__3__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_In__3__BYP CYREG_PRT4_BYP +#define SCSI_In__3__CTL CYREG_PRT4_CTL +#define SCSI_In__3__DM0 CYREG_PRT4_DM0 +#define SCSI_In__3__DM1 CYREG_PRT4_DM1 +#define SCSI_In__3__DM2 CYREG_PRT4_DM2 +#define SCSI_In__3__DR CYREG_PRT4_DR +#define SCSI_In__3__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_In__3__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_In__3__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_In__3__MASK 0x40u +#define SCSI_In__3__PC CYREG_PRT4_PC6 +#define SCSI_In__3__PORT 4u +#define SCSI_In__3__PRT CYREG_PRT4_PRT +#define SCSI_In__3__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_In__3__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_In__3__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_In__3__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_In__3__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_In__3__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_In__3__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_In__3__PS CYREG_PRT4_PS +#define SCSI_In__3__SHIFT 6 +#define SCSI_In__3__SLW CYREG_PRT4_SLW +#define SCSI_In__4__AG CYREG_PRT4_AG +#define SCSI_In__4__AMUX CYREG_PRT4_AMUX +#define SCSI_In__4__BIE CYREG_PRT4_BIE +#define SCSI_In__4__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_In__4__BYP CYREG_PRT4_BYP +#define SCSI_In__4__CTL CYREG_PRT4_CTL +#define SCSI_In__4__DM0 CYREG_PRT4_DM0 +#define SCSI_In__4__DM1 CYREG_PRT4_DM1 +#define SCSI_In__4__DM2 CYREG_PRT4_DM2 +#define SCSI_In__4__DR CYREG_PRT4_DR +#define SCSI_In__4__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_In__4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_In__4__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_In__4__MASK 0x08u +#define SCSI_In__4__PC CYREG_PRT4_PC3 +#define SCSI_In__4__PORT 4u +#define SCSI_In__4__PRT CYREG_PRT4_PRT +#define SCSI_In__4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_In__4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_In__4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_In__4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_In__4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_In__4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_In__4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_In__4__PS CYREG_PRT4_PS +#define SCSI_In__4__SHIFT 3 +#define SCSI_In__4__SLW CYREG_PRT4_SLW +#define SCSI_In__5__AG CYREG_PRT4_AG +#define SCSI_In__5__AMUX CYREG_PRT4_AMUX +#define SCSI_In__5__BIE CYREG_PRT4_BIE +#define SCSI_In__5__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_In__5__BYP CYREG_PRT4_BYP +#define SCSI_In__5__CTL CYREG_PRT4_CTL +#define SCSI_In__5__DM0 CYREG_PRT4_DM0 +#define SCSI_In__5__DM1 CYREG_PRT4_DM1 +#define SCSI_In__5__DM2 CYREG_PRT4_DM2 +#define SCSI_In__5__DR CYREG_PRT4_DR +#define SCSI_In__5__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_In__5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_In__5__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_In__5__MASK 0x04u +#define SCSI_In__5__PC CYREG_PRT4_PC2 +#define SCSI_In__5__PORT 4u +#define SCSI_In__5__PRT CYREG_PRT4_PRT +#define SCSI_In__5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_In__5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_In__5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_In__5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_In__5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_In__5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_In__5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_In__5__PS CYREG_PRT4_PS +#define SCSI_In__5__SHIFT 2 +#define SCSI_In__5__SLW CYREG_PRT4_SLW +#define SCSI_In__6__AG CYREG_PRT0_AG +#define SCSI_In__6__AMUX CYREG_PRT0_AMUX +#define SCSI_In__6__BIE CYREG_PRT0_BIE +#define SCSI_In__6__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_In__6__BYP CYREG_PRT0_BYP +#define SCSI_In__6__CTL CYREG_PRT0_CTL +#define SCSI_In__6__DM0 CYREG_PRT0_DM0 +#define SCSI_In__6__DM1 CYREG_PRT0_DM1 +#define SCSI_In__6__DM2 CYREG_PRT0_DM2 +#define SCSI_In__6__DR CYREG_PRT0_DR +#define SCSI_In__6__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_In__6__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_In__6__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_In__6__MASK 0x20u +#define SCSI_In__6__PC CYREG_PRT0_PC5 +#define SCSI_In__6__PORT 0u +#define SCSI_In__6__PRT CYREG_PRT0_PRT +#define SCSI_In__6__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_In__6__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_In__6__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_In__6__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_In__6__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_In__6__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_In__6__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_In__6__PS CYREG_PRT0_PS +#define SCSI_In__6__SHIFT 5 +#define SCSI_In__6__SLW CYREG_PRT0_SLW +#define SCSI_In__7__AG CYREG_PRT0_AG +#define SCSI_In__7__AMUX CYREG_PRT0_AMUX +#define SCSI_In__7__BIE CYREG_PRT0_BIE +#define SCSI_In__7__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_In__7__BYP CYREG_PRT0_BYP +#define SCSI_In__7__CTL CYREG_PRT0_CTL +#define SCSI_In__7__DM0 CYREG_PRT0_DM0 +#define SCSI_In__7__DM1 CYREG_PRT0_DM1 +#define SCSI_In__7__DM2 CYREG_PRT0_DM2 +#define SCSI_In__7__DR CYREG_PRT0_DR +#define SCSI_In__7__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_In__7__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_In__7__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_In__7__MASK 0x10u +#define SCSI_In__7__PC CYREG_PRT0_PC4 +#define SCSI_In__7__PORT 0u +#define SCSI_In__7__PRT CYREG_PRT0_PRT +#define SCSI_In__7__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_In__7__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_In__7__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_In__7__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_In__7__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_In__7__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_In__7__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_In__7__PS CYREG_PRT0_PS +#define SCSI_In__7__SHIFT 4 +#define SCSI_In__7__SLW CYREG_PRT0_SLW +#define SCSI_In__ACK__AG CYREG_PRT6_AG +#define SCSI_In__ACK__AMUX CYREG_PRT6_AMUX +#define SCSI_In__ACK__BIE CYREG_PRT6_BIE +#define SCSI_In__ACK__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_In__ACK__BYP CYREG_PRT6_BYP +#define SCSI_In__ACK__CTL CYREG_PRT6_CTL +#define SCSI_In__ACK__DM0 CYREG_PRT6_DM0 +#define SCSI_In__ACK__DM1 CYREG_PRT6_DM1 +#define SCSI_In__ACK__DM2 CYREG_PRT6_DM2 +#define SCSI_In__ACK__DR CYREG_PRT6_DR +#define SCSI_In__ACK__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_In__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_In__ACK__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_In__ACK__MASK 0x04u +#define SCSI_In__ACK__PC CYREG_PRT6_PC2 +#define SCSI_In__ACK__PORT 6u +#define SCSI_In__ACK__PRT CYREG_PRT6_PRT +#define SCSI_In__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_In__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_In__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_In__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_In__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_In__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_In__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_In__ACK__PS CYREG_PRT6_PS +#define SCSI_In__ACK__SHIFT 2 +#define SCSI_In__ACK__SLW CYREG_PRT6_SLW +#define SCSI_In__BSY__AG CYREG_PRT6_AG +#define SCSI_In__BSY__AMUX CYREG_PRT6_AMUX +#define SCSI_In__BSY__BIE CYREG_PRT6_BIE +#define SCSI_In__BSY__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_In__BSY__BYP CYREG_PRT6_BYP +#define SCSI_In__BSY__CTL CYREG_PRT6_CTL +#define SCSI_In__BSY__DM0 CYREG_PRT6_DM0 +#define SCSI_In__BSY__DM1 CYREG_PRT6_DM1 +#define SCSI_In__BSY__DM2 CYREG_PRT6_DM2 +#define SCSI_In__BSY__DR CYREG_PRT6_DR +#define SCSI_In__BSY__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_In__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_In__BSY__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_In__BSY__MASK 0x08u +#define SCSI_In__BSY__PC CYREG_PRT6_PC3 +#define SCSI_In__BSY__PORT 6u +#define SCSI_In__BSY__PRT CYREG_PRT6_PRT +#define SCSI_In__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_In__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_In__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_In__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_In__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_In__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_In__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_In__BSY__PS CYREG_PRT6_PS +#define SCSI_In__BSY__SHIFT 3 +#define SCSI_In__BSY__SLW CYREG_PRT6_SLW +#define SCSI_In__CD__AG CYREG_PRT4_AG +#define SCSI_In__CD__AMUX CYREG_PRT4_AMUX +#define SCSI_In__CD__BIE CYREG_PRT4_BIE +#define SCSI_In__CD__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_In__CD__BYP CYREG_PRT4_BYP +#define SCSI_In__CD__CTL CYREG_PRT4_CTL +#define SCSI_In__CD__DM0 CYREG_PRT4_DM0 +#define SCSI_In__CD__DM1 CYREG_PRT4_DM1 +#define SCSI_In__CD__DM2 CYREG_PRT4_DM2 +#define SCSI_In__CD__DR CYREG_PRT4_DR +#define SCSI_In__CD__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_In__CD__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_In__CD__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_In__CD__MASK 0x04u +#define SCSI_In__CD__PC CYREG_PRT4_PC2 +#define SCSI_In__CD__PORT 4u +#define SCSI_In__CD__PRT CYREG_PRT4_PRT +#define SCSI_In__CD__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_In__CD__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_In__CD__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_In__CD__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_In__CD__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_In__CD__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_In__CD__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_In__CD__PS CYREG_PRT4_PS +#define SCSI_In__CD__SHIFT 2 +#define SCSI_In__CD__SLW CYREG_PRT4_SLW +#define SCSI_In__DBP__AG CYREG_PRT2_AG +#define SCSI_In__DBP__AMUX CYREG_PRT2_AMUX +#define SCSI_In__DBP__BIE CYREG_PRT2_BIE +#define SCSI_In__DBP__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_In__DBP__BYP CYREG_PRT2_BYP +#define SCSI_In__DBP__CTL CYREG_PRT2_CTL +#define SCSI_In__DBP__DM0 CYREG_PRT2_DM0 +#define SCSI_In__DBP__DM1 CYREG_PRT2_DM1 +#define SCSI_In__DBP__DM2 CYREG_PRT2_DM2 +#define SCSI_In__DBP__DR CYREG_PRT2_DR +#define SCSI_In__DBP__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_In__DBP__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_In__DBP__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_In__DBP__MASK 0x02u +#define SCSI_In__DBP__PC CYREG_PRT2_PC1 +#define SCSI_In__DBP__PORT 2u +#define SCSI_In__DBP__PRT CYREG_PRT2_PRT +#define SCSI_In__DBP__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_In__DBP__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_In__DBP__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_In__DBP__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_In__DBP__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_In__DBP__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_In__DBP__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_In__DBP__PS CYREG_PRT2_PS +#define SCSI_In__DBP__SHIFT 1 +#define SCSI_In__DBP__SLW CYREG_PRT2_SLW +#define SCSI_In__IO__AG CYREG_PRT0_AG +#define SCSI_In__IO__AMUX CYREG_PRT0_AMUX +#define SCSI_In__IO__BIE CYREG_PRT0_BIE +#define SCSI_In__IO__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_In__IO__BYP CYREG_PRT0_BYP +#define SCSI_In__IO__CTL CYREG_PRT0_CTL +#define SCSI_In__IO__DM0 CYREG_PRT0_DM0 +#define SCSI_In__IO__DM1 CYREG_PRT0_DM1 +#define SCSI_In__IO__DM2 CYREG_PRT0_DM2 +#define SCSI_In__IO__DR CYREG_PRT0_DR +#define SCSI_In__IO__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_In__IO__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_In__IO__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_In__IO__MASK 0x10u +#define SCSI_In__IO__PC CYREG_PRT0_PC4 +#define SCSI_In__IO__PORT 0u +#define SCSI_In__IO__PRT CYREG_PRT0_PRT +#define SCSI_In__IO__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_In__IO__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_In__IO__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_In__IO__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_In__IO__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_In__IO__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_In__IO__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_In__IO__PS CYREG_PRT0_PS +#define SCSI_In__IO__SHIFT 4 +#define SCSI_In__IO__SLW CYREG_PRT0_SLW +#define SCSI_In__MSG__AG CYREG_PRT4_AG +#define SCSI_In__MSG__AMUX CYREG_PRT4_AMUX +#define SCSI_In__MSG__BIE CYREG_PRT4_BIE +#define SCSI_In__MSG__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_In__MSG__BYP CYREG_PRT4_BYP +#define SCSI_In__MSG__CTL CYREG_PRT4_CTL +#define SCSI_In__MSG__DM0 CYREG_PRT4_DM0 +#define SCSI_In__MSG__DM1 CYREG_PRT4_DM1 +#define SCSI_In__MSG__DM2 CYREG_PRT4_DM2 +#define SCSI_In__MSG__DR CYREG_PRT4_DR +#define SCSI_In__MSG__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_In__MSG__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_In__MSG__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_In__MSG__MASK 0x40u +#define SCSI_In__MSG__PC CYREG_PRT4_PC6 +#define SCSI_In__MSG__PORT 4u +#define SCSI_In__MSG__PRT CYREG_PRT4_PRT +#define SCSI_In__MSG__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_In__MSG__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_In__MSG__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_In__MSG__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_In__MSG__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_In__MSG__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_In__MSG__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_In__MSG__PS CYREG_PRT4_PS +#define SCSI_In__MSG__SHIFT 6 +#define SCSI_In__MSG__SLW CYREG_PRT4_SLW +#define SCSI_In__REQ__AG CYREG_PRT0_AG +#define SCSI_In__REQ__AMUX CYREG_PRT0_AMUX +#define SCSI_In__REQ__BIE CYREG_PRT0_BIE +#define SCSI_In__REQ__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_In__REQ__BYP CYREG_PRT0_BYP +#define SCSI_In__REQ__CTL CYREG_PRT0_CTL +#define SCSI_In__REQ__DM0 CYREG_PRT0_DM0 +#define SCSI_In__REQ__DM1 CYREG_PRT0_DM1 +#define SCSI_In__REQ__DM2 CYREG_PRT0_DM2 +#define SCSI_In__REQ__DR CYREG_PRT0_DR +#define SCSI_In__REQ__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_In__REQ__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_In__REQ__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_In__REQ__MASK 0x20u +#define SCSI_In__REQ__PC CYREG_PRT0_PC5 +#define SCSI_In__REQ__PORT 0u +#define SCSI_In__REQ__PRT CYREG_PRT0_PRT +#define SCSI_In__REQ__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_In__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_In__REQ__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_In__REQ__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_In__REQ__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_In__REQ__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_In__REQ__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_In__REQ__PS CYREG_PRT0_PS +#define SCSI_In__REQ__SHIFT 5 +#define SCSI_In__REQ__SLW CYREG_PRT0_SLW +#define SCSI_In__SEL__AG CYREG_PRT4_AG +#define SCSI_In__SEL__AMUX CYREG_PRT4_AMUX +#define SCSI_In__SEL__BIE CYREG_PRT4_BIE +#define SCSI_In__SEL__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_In__SEL__BYP CYREG_PRT4_BYP +#define SCSI_In__SEL__CTL CYREG_PRT4_CTL +#define SCSI_In__SEL__DM0 CYREG_PRT4_DM0 +#define SCSI_In__SEL__DM1 CYREG_PRT4_DM1 +#define SCSI_In__SEL__DM2 CYREG_PRT4_DM2 +#define SCSI_In__SEL__DR CYREG_PRT4_DR +#define SCSI_In__SEL__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_In__SEL__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_In__SEL__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_In__SEL__MASK 0x08u +#define SCSI_In__SEL__PC CYREG_PRT4_PC3 +#define SCSI_In__SEL__PORT 4u +#define SCSI_In__SEL__PRT CYREG_PRT4_PRT +#define SCSI_In__SEL__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_In__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_In__SEL__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_In__SEL__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_In__SEL__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_In__SEL__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_In__SEL__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_In__SEL__PS CYREG_PRT4_PS +#define SCSI_In__SEL__SHIFT 3 +#define SCSI_In__SEL__SLW CYREG_PRT4_SLW + +/* SD_MISO */ +#define SD_MISO__0__MASK 0x02u +#define SD_MISO__0__PC CYREG_PRT3_PC1 +#define SD_MISO__0__PORT 3u +#define SD_MISO__0__SHIFT 1 +#define SD_MISO__AG CYREG_PRT3_AG +#define SD_MISO__AMUX CYREG_PRT3_AMUX +#define SD_MISO__BIE CYREG_PRT3_BIE +#define SD_MISO__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_MISO__BYP CYREG_PRT3_BYP +#define SD_MISO__CTL CYREG_PRT3_CTL +#define SD_MISO__DM0 CYREG_PRT3_DM0 +#define SD_MISO__DM1 CYREG_PRT3_DM1 +#define SD_MISO__DM2 CYREG_PRT3_DM2 +#define SD_MISO__DR CYREG_PRT3_DR +#define SD_MISO__INP_DIS CYREG_PRT3_INP_DIS +#define SD_MISO__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_MISO__LCD_EN CYREG_PRT3_LCD_EN +#define SD_MISO__MASK 0x02u +#define SD_MISO__PORT 3u +#define SD_MISO__PRT CYREG_PRT3_PRT +#define SD_MISO__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_MISO__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_MISO__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_MISO__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_MISO__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_MISO__PS CYREG_PRT3_PS +#define SD_MISO__SHIFT 1 +#define SD_MISO__SLW CYREG_PRT3_SLW + +/* SD_MOSI */ +#define SD_MOSI__0__MASK 0x08u +#define SD_MOSI__0__PC CYREG_PRT3_PC3 +#define SD_MOSI__0__PORT 3u +#define SD_MOSI__0__SHIFT 3 +#define SD_MOSI__AG CYREG_PRT3_AG +#define SD_MOSI__AMUX CYREG_PRT3_AMUX +#define SD_MOSI__BIE CYREG_PRT3_BIE +#define SD_MOSI__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_MOSI__BYP CYREG_PRT3_BYP +#define SD_MOSI__CTL CYREG_PRT3_CTL +#define SD_MOSI__DM0 CYREG_PRT3_DM0 +#define SD_MOSI__DM1 CYREG_PRT3_DM1 +#define SD_MOSI__DM2 CYREG_PRT3_DM2 +#define SD_MOSI__DR CYREG_PRT3_DR +#define SD_MOSI__INP_DIS CYREG_PRT3_INP_DIS +#define SD_MOSI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_MOSI__LCD_EN CYREG_PRT3_LCD_EN +#define SD_MOSI__MASK 0x08u +#define SD_MOSI__PORT 3u +#define SD_MOSI__PRT CYREG_PRT3_PRT +#define SD_MOSI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_MOSI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_MOSI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_MOSI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_MOSI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_MOSI__PS CYREG_PRT3_PS +#define SD_MOSI__SHIFT 3 +#define SD_MOSI__SLW CYREG_PRT3_SLW + +/* SD_SCK */ +#define SD_SCK__0__MASK 0x04u +#define SD_SCK__0__PC CYREG_PRT3_PC2 +#define SD_SCK__0__PORT 3u +#define SD_SCK__0__SHIFT 2 +#define SD_SCK__AG CYREG_PRT3_AG +#define SD_SCK__AMUX CYREG_PRT3_AMUX +#define SD_SCK__BIE CYREG_PRT3_BIE +#define SD_SCK__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_SCK__BYP CYREG_PRT3_BYP +#define SD_SCK__CTL CYREG_PRT3_CTL +#define SD_SCK__DM0 CYREG_PRT3_DM0 +#define SD_SCK__DM1 CYREG_PRT3_DM1 +#define SD_SCK__DM2 CYREG_PRT3_DM2 +#define SD_SCK__DR CYREG_PRT3_DR +#define SD_SCK__INP_DIS CYREG_PRT3_INP_DIS +#define SD_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_SCK__LCD_EN CYREG_PRT3_LCD_EN +#define SD_SCK__MASK 0x04u +#define SD_SCK__PORT 3u +#define SD_SCK__PRT CYREG_PRT3_PRT +#define SD_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_SCK__PS CYREG_PRT3_PS +#define SD_SCK__SHIFT 2 +#define SD_SCK__SLW CYREG_PRT3_SLW + +/* SD_CD */ +#define SD_CD__0__MASK 0x20u +#define SD_CD__0__PC CYREG_PRT3_PC5 +#define SD_CD__0__PORT 3u +#define SD_CD__0__SHIFT 5 +#define SD_CD__AG CYREG_PRT3_AG +#define SD_CD__AMUX CYREG_PRT3_AMUX +#define SD_CD__BIE CYREG_PRT3_BIE +#define SD_CD__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_CD__BYP CYREG_PRT3_BYP +#define SD_CD__CTL CYREG_PRT3_CTL +#define SD_CD__DM0 CYREG_PRT3_DM0 +#define SD_CD__DM1 CYREG_PRT3_DM1 +#define SD_CD__DM2 CYREG_PRT3_DM2 +#define SD_CD__DR CYREG_PRT3_DR +#define SD_CD__INP_DIS CYREG_PRT3_INP_DIS +#define SD_CD__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_CD__LCD_EN CYREG_PRT3_LCD_EN +#define SD_CD__MASK 0x20u +#define SD_CD__PORT 3u +#define SD_CD__PRT CYREG_PRT3_PRT +#define SD_CD__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_CD__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_CD__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_CD__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_CD__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_CD__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_CD__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_CD__PS CYREG_PRT3_PS +#define SD_CD__SHIFT 5 +#define SD_CD__SLW CYREG_PRT3_SLW + +/* SD_CS */ +#define SD_CS__0__MASK 0x10u +#define SD_CS__0__PC CYREG_PRT3_PC4 +#define SD_CS__0__PORT 3u +#define SD_CS__0__SHIFT 4 +#define SD_CS__AG CYREG_PRT3_AG +#define SD_CS__AMUX CYREG_PRT3_AMUX +#define SD_CS__BIE CYREG_PRT3_BIE +#define SD_CS__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_CS__BYP CYREG_PRT3_BYP +#define SD_CS__CTL CYREG_PRT3_CTL +#define SD_CS__DM0 CYREG_PRT3_DM0 +#define SD_CS__DM1 CYREG_PRT3_DM1 +#define SD_CS__DM2 CYREG_PRT3_DM2 +#define SD_CS__DR CYREG_PRT3_DR +#define SD_CS__INP_DIS CYREG_PRT3_INP_DIS +#define SD_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_CS__LCD_EN CYREG_PRT3_LCD_EN +#define SD_CS__MASK 0x10u +#define SD_CS__PORT 3u +#define SD_CS__PRT CYREG_PRT3_PRT +#define SD_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_CS__PS CYREG_PRT3_PS +#define SD_CS__SHIFT 4 +#define SD_CS__SLW CYREG_PRT3_SLW + +/* LED1 */ +#define LED1__0__MASK 0x02u +#define LED1__0__PC CYREG_PRT0_PC1 +#define LED1__0__PORT 0u +#define LED1__0__SHIFT 1 +#define LED1__AG CYREG_PRT0_AG +#define LED1__AMUX CYREG_PRT0_AMUX +#define LED1__BIE CYREG_PRT0_BIE +#define LED1__BIT_MASK CYREG_PRT0_BIT_MASK +#define LED1__BYP CYREG_PRT0_BYP +#define LED1__CTL CYREG_PRT0_CTL +#define LED1__DM0 CYREG_PRT0_DM0 +#define LED1__DM1 CYREG_PRT0_DM1 +#define LED1__DM2 CYREG_PRT0_DM2 +#define LED1__DR CYREG_PRT0_DR +#define LED1__INP_DIS CYREG_PRT0_INP_DIS +#define LED1__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define LED1__LCD_EN CYREG_PRT0_LCD_EN +#define LED1__MASK 0x02u +#define LED1__PORT 0u +#define LED1__PRT CYREG_PRT0_PRT +#define LED1__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define LED1__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define LED1__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define LED1__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define LED1__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define LED1__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define LED1__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define LED1__PS CYREG_PRT0_PS +#define LED1__SHIFT 1 +#define LED1__SLW CYREG_PRT0_SLW + +/* Miscellaneous */ +/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */ +#define CYDEV_DEBUGGING_DPS_SWD_SWV 6 +#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0 +#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0 +#define CYDEV_CONFIG_FASTBOOT_ENABLED 1 +#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u +#define CYDEV_CHIP_MEMBER_5B 4u +#define CYDEV_CHIP_FAMILY_PSOC5 3u +#define CYDEV_CHIP_DIE_PSOC5LP 4u +#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_DIE_PSOC5LP +#define BCLK__BUS_CLK__HZ 60000000U +#define BCLK__BUS_CLK__KHZ 60000U +#define BCLK__BUS_CLK__MHZ 60U +#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT +#define CYDEV_CHIP_DIE_LEOPARD 1u +#define CYDEV_CHIP_DIE_PANTHER 3u +#define CYDEV_CHIP_DIE_PSOC4A 2u +#define CYDEV_CHIP_DIE_UNKNOWN 0u +#define CYDEV_CHIP_FAMILY_PSOC3 1u +#define CYDEV_CHIP_FAMILY_PSOC4 2u +#define CYDEV_CHIP_FAMILY_UNKNOWN 0u +#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5 +#define CYDEV_CHIP_JTAG_ID 0x2E133069u +#define CYDEV_CHIP_MEMBER_3A 1u +#define CYDEV_CHIP_MEMBER_4A 2u +#define CYDEV_CHIP_MEMBER_5A 3u +#define CYDEV_CHIP_MEMBER_UNKNOWN 0u +#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B +#define CYDEV_CHIP_REVISION_3A_ES1 0u +#define CYDEV_CHIP_REVISION_3A_ES2 1u +#define CYDEV_CHIP_REVISION_3A_ES3 3u +#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u +#define CYDEV_CHIP_REVISION_4A_ES0 17u +#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u +#define CYDEV_CHIP_REVISION_5A_ES0 0u +#define CYDEV_CHIP_REVISION_5A_ES1 1u +#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u +#define CYDEV_CHIP_REVISION_5B_ES0 0u +#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_5B_PRODUCTION +#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REV_PSOC5LP_PRODUCTION +#define CYDEV_CHIP_REV_LEOPARD_ES1 0u +#define CYDEV_CHIP_REV_LEOPARD_ES2 1u +#define CYDEV_CHIP_REV_LEOPARD_ES3 3u +#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u +#define CYDEV_CHIP_REV_PANTHER_ES0 0u +#define CYDEV_CHIP_REV_PANTHER_ES1 1u +#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u +#define CYDEV_CHIP_REV_PSOC4A_ES0 17u +#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u +#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u +#define CYDEV_CONFIGURATION_COMPRESSED 1 +#define CYDEV_CONFIGURATION_DMA 0 +#define CYDEV_CONFIGURATION_ECC 0 +#define CYDEV_CONFIGURATION_IMOENABLED CYDEV_CONFIG_FASTBOOT_ENABLED +#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED +#define CYDEV_CONFIGURATION_MODE_DMA 2 +#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1 +#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn +#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1 +#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2 +#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD_SWV +#define CYDEV_DEBUGGING_DPS_Disable 3 +#define CYDEV_DEBUGGING_DPS_JTAG_4 1 +#define CYDEV_DEBUGGING_DPS_JTAG_5 0 +#define CYDEV_DEBUGGING_DPS_SWD 2 +#define CYDEV_DEBUGGING_ENABLE 1 +#define CYDEV_DEBUGGING_XRES 0 +#define CYDEV_DEBUG_ENABLE_MASK 0x20u +#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG +#define CYDEV_DMA_CHANNELS_AVAILABLE 24u +#define CYDEV_ECC_ENABLE 0 +#define CYDEV_HEAP_SIZE 0x1000 +#define CYDEV_INSTRUCT_CACHE_ENABLED 1 +#define CYDEV_INTR_RISING 0x00000000u +#define CYDEV_PROJ_TYPE 2 +#define CYDEV_PROJ_TYPE_BOOTLOADER 1 +#define CYDEV_PROJ_TYPE_LOADABLE 2 +#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3 +#define CYDEV_PROJ_TYPE_STANDARD 0 +#define CYDEV_PROTECTION_ENABLE 0 +#define CYDEV_STACK_SIZE 0x4000 +#define CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP +#define CYDEV_USE_BUNDLED_CMSIS 1 +#define CYDEV_VARIABLE_VDDA 0 +#define CYDEV_VDDA 5.0 +#define CYDEV_VDDA_MV 5000 +#define CYDEV_VDDD 5.0 +#define CYDEV_VDDD_MV 5000 +#define CYDEV_VDDIO0 5.0 +#define CYDEV_VDDIO0_MV 5000 +#define CYDEV_VDDIO1 5.0 +#define CYDEV_VDDIO1_MV 5000 +#define CYDEV_VDDIO2 5.0 +#define CYDEV_VDDIO2_MV 5000 +#define CYDEV_VDDIO3 3.3 +#define CYDEV_VDDIO3_MV 3300 +#define CYDEV_VIO0 5 +#define CYDEV_VIO0_MV 5000 +#define CYDEV_VIO1 5 +#define CYDEV_VIO1_MV 5000 +#define CYDEV_VIO2 5 +#define CYDEV_VIO2_MV 5000 +#define CYDEV_VIO3 3.3 +#define CYDEV_VIO3_MV 3300 +#define DMA_CHANNELS_USED__MASK0 0x00000000u +#define CYDEV_BOOTLOADER_ENABLE 0 + +#endif /* INCLUDED_CYFITTER_H */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c new file mode 100755 index 00000000..0a7fae95 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -0,0 +1,1359 @@ +/******************************************************************************* +* FILENAME: cyfitter_cfg.c +* PSoC Creator 3.0 Component Pack 7 +* +* Description: +* This file is automatically generated by PSoC Creator with device +* initialization code. Except for the user defined sections in +* CyClockStartupError(), this file should not be modified. +* +******************************************************************************** +* Copyright 2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#define CY_NEED_CYCLOCKSTARTUPERROR 1 + + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) + #define CYPACKED + #define CYPACKED_ATTR __attribute__ ((packed)) + #define CYALIGNED __attribute__ ((aligned)) + #define CY_CFG_UNUSED __attribute__ ((unused)) + #define CY_CFG_SECTION __attribute__ ((section(".psocinit"))) + + #if defined(__ARMCC_VERSION) + #define CY_CFG_MEMORY_BARRIER() __memory_changed() + #else + #define CY_CFG_MEMORY_BARRIER() __sync_synchronize() + #endif + +#elif defined(__ICCARM__) + #include + + #define CYPACKED __packed + #define CYPACKED_ATTR + #define CYALIGNED _Pragma("data_alignment=4") + #define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177") + #define CY_CFG_SECTION _Pragma("location=\".psocinit\"") + + #define CY_CFG_MEMORY_BARRIER() __DMB() + +#else + #error Unsupported toolchain +#endif + + +CY_CFG_UNUSED +static void CYMEMZERO(void *s, size_t n); +CY_CFG_UNUSED +static void CYMEMZERO(void *s, size_t n) +{ + (void)memset(s, 0, n); +} +CY_CFG_UNUSED +static void CYCONFIGCPY(void *dest, const void *src, size_t n); +CY_CFG_UNUSED +static void CYCONFIGCPY(void *dest, const void *src, size_t n) +{ + (void)memcpy(dest, src, n); +} +CY_CFG_UNUSED +static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n); +CY_CFG_UNUSED +static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n) +{ + (void)memcpy(dest, src, n); +} + + + +/* Clock startup error codes */ +#define CYCLOCKSTART_NO_ERROR 0u +#define CYCLOCKSTART_XTAL_ERROR 1u +#define CYCLOCKSTART_32KHZ_ERROR 2u +#define CYCLOCKSTART_PLL_ERROR 3u + +#ifdef CY_NEED_CYCLOCKSTARTUPERROR +/******************************************************************************* +* Function Name: CyClockStartupError +******************************************************************************** +* Summary: +* If an error is encountered during clock configuration (crystal startup error, +* PLL lock error, etc.), the system will end up here. Unless reimplemented by +* the customer, this function will stop in an infinite loop. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +CY_CFG_UNUSED +static void CyClockStartupError(uint8 errorCode); +CY_CFG_UNUSED +static void CyClockStartupError(uint8 errorCode) +{ + /* To remove the compiler warning if errorCode not used. */ + errorCode = errorCode; + + /* `#START CyClockStartupError` */ + + /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */ + /* we will end up here to allow the customer to implement something to */ + /* deal with the clock condition. */ + + /* `#END` */ + + /* If nothing else, stop here since the clocks have not started */ + /* correctly. */ + while(1) {} +} +#endif + +#define CY_CFG_BASE_ADDR_COUNT 32u +CYPACKED typedef struct +{ + uint8 offset; + uint8 value; +} CYPACKED_ATTR cy_cfg_addrvalue_t; + + + +/******************************************************************************* +* Function Name: cfg_write_bytes32 +******************************************************************************** +* Summary: +* This function is used for setting up the chip configuration areas that +* contain relatively sparse data. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]); +static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]) +{ + /* For 32-bit little-endian architectures */ + uint32 i, j = 0u; + for (i = 0u; i < CY_CFG_BASE_ADDR_COUNT; i++) + { + uint32 baseAddr = addr_table[i]; + uint8 count = (uint8)baseAddr; + baseAddr &= 0xFFFFFF00u; + while (count != 0u) + { + CY_SET_XTND_REG8((void CYFAR *)(baseAddr + data_table[j].offset), data_table[j].value); + j++; + count--; + } + } +} + +/******************************************************************************* +* Function Name: ClockSetup +******************************************************************************** +* +* Summary: +* Performs the initialization of all of the clocks in the device based on the +* settings in the Clock tab of the DWR. This includes enabling the requested +* clocks and setting the necessary dividers to produce the desired frequency. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +static void ClockSetup(void); +static void ClockSetup(void) +{ + uint32 timeout; + uint8 pllLock; + + + /* Configure Digital Clocks based on settings from Clock DWR */ + CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0), 0x0001u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x10u); + CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x001Du); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x19u); + + /* Configure ILO based on settings from Clock DWR */ + CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u); + + /* Configure IMO based on settings from Clock DWR */ + CY_SET_XTND_REG8((void CYFAR *)(CYREG_FASTCLK_IMO_CR), 0x52u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_TABLES_IMO_USB))); + + /* Configure PLL based on settings from Clock DWR */ + CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0919u); + CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1251u); + /* Wait up to 250us for the PLL to lock */ + pllLock = 0u; + for (timeout = 250u / 10u; (timeout > 0u) && (pllLock != 0x03u); timeout--) + { + pllLock = 0x03u & ((uint8)((uint8)pllLock << 1) | ((CY_GET_XTND_REG8((void CYFAR *)CYREG_FASTCLK_PLL_SR) & 0x01u) >> 0)); + CyDelayCycles(10u * 48u); /* Delay 10us based on 48MHz clock */ + } + /* If we ran out of time the PLL didn't lock so go to the error function */ + if (timeout == 0u) + { + CyClockStartupError(CYCLOCKSTART_PLL_ERROR); + } + + /* Configure Bus/Master Clock based on settings from Clock DWR */ + CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x0100u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x07u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG0), 0x00u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG2), 0x48u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x00u); + + /* Configure USB Clock based on settings from Clock DWR */ + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_UCFG), 0x00u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u); + + CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x02u))); +} + + +/* Analog API Functions */ + + +/******************************************************************************* +* Function Name: AnalogSetDefault +******************************************************************************** +* +* Summary: +* Sets up the analog portions of the chip to default values based on chip +* configuration options from the project. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +static void AnalogSetDefault(void); +static void AnalogSetDefault(void) +{ + uint8 bg_xover_inl_trim = CY_GET_XTND_REG8((void CYFAR *)(CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM + 1u)); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT0), (bg_xover_inl_trim & 0x07u)); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT1), ((bg_xover_inl_trim >> 4) & 0x0Fu)); + CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, 0x44u); +} + + +/******************************************************************************* +* Function Name: SetAnalogRoutingPumps +******************************************************************************** +* +* Summary: +* Enables or disables the analog pumps feeding analog routing switches. +* Intended to be called at startup, based on the Vdda system configuration; +* may be called during operation when the user informs us that the Vdda voltage +* crossed the pump threshold. +* +* Parameters: +* enabled - 1 to enable the pumps, 0 to disable the pumps +* +* Return: +* void +* +*******************************************************************************/ +void SetAnalogRoutingPumps(uint8 enabled) +{ + uint8 regValue = CY_GET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0); + if (enabled != 0u) + { + regValue |= 0x00u; + } + else + { + regValue &= (uint8)~0x00u; + } + CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, regValue); +} + +#define CY_AMUX_UNUSED CYREG_BOOST_SR + + +/******************************************************************************* +* Function Name: cyfitter_cfg +******************************************************************************** +* Summary: +* This function is called by the start-up code for the selected device. It +* performs all of the necessary device configuration based on the design +* settings. This includes settings from the Design Wide Resources (DWR) such +* as Clocks and Pins as well as any component configuration that is necessary. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ + +void cyfitter_cfg(void) +{ + /* IOPINS0_0 Address: CYREG_PRT0_DR Size (bytes): 10 */ + static const uint8 CYCODE BS_IOPINS0_0_VAL[] = { + 0x02u, 0x00u, 0x30u, 0xCCu, 0xCEu, 0x00u, 0x0Cu, 0x00u, 0x00u, 0x01u}; + + /* IOPINS0_7 Address: CYREG_PRT12_DM0 Size (bytes): 8 */ + static const uint8 CYCODE BS_IOPINS0_7_VAL[] = { + 0x30u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + + /* IOPINS1_7 Address: CYREG_PRT12_DM0 + 0x00000009u Size (bytes): 5 */ + static const uint8 CYCODE BS_IOPINS1_7_VAL[] = { + 0x00u, 0x00u, 0x00u, 0x00u, 0x10u}; + + /* IOPINS0_8 Address: CYREG_PRT15_DR Size (bytes): 10 */ + static const uint8 CYCODE BS_IOPINS0_8_VAL[] = { + 0x00u, 0x00u, 0x00u, 0x30u, 0x30u, 0x00u, 0x20u, 0x00u, 0xC0u, 0x00u}; + + /* IOPINS0_2 Address: CYREG_PRT2_DM0 Size (bytes): 8 */ + static const uint8 CYCODE BS_IOPINS0_2_VAL[] = { + 0x33u, 0xCCu, 0xCCu, 0x00u, 0xCCu, 0x00u, 0x00u, 0x01u}; + + /* IOPINS0_3 Address: CYREG_PRT3_DM0 Size (bytes): 8 */ + static const uint8 CYCODE BS_IOPINS0_3_VAL[] = { + 0x00u, 0x3Eu, 0x00u, 0x00u, 0x0Cu, 0x00u, 0x00u, 0x00u}; + + /* IOPINS0_4 Address: CYREG_PRT4_DM0 Size (bytes): 8 */ + static const uint8 CYCODE BS_IOPINS0_4_VAL[] = { + 0xCCu, 0x30u, 0x30u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u}; + + /* IOPINS0_5 Address: CYREG_PRT5_DM0 Size (bytes): 8 */ + static const uint8 CYCODE BS_IOPINS0_5_VAL[] = { + 0x0Cu, 0x03u, 0x03u, 0x00u, 0x03u, 0x00u, 0x00u, 0x01u}; + + /* IOPINS0_6 Address: CYREG_PRT6_DM0 Size (bytes): 8 */ + static const uint8 CYCODE BS_IOPINS0_6_VAL[] = { + 0xCCu, 0x33u, 0x33u, 0x00u, 0x30u, 0x00u, 0x00u, 0x01u}; + +#ifdef CYGlobalIntDisable + /* Disable interrupts by default. Let user enable if/when they want. */ + CYGlobalIntDisable +#endif + + + /* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */ + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x01u : 0x00u)); + /* Setup clocks based on selections from Clock DWR */ + ClockSetup(); + /* Enable/Disable Debug functionality based on settings from System DWR */ + CY_SET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG, (CY_GET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG) | 0x04u)); + + { + static const uint32 CYCODE cy_cfg_addr_table[] = { + 0x40004502u, /* Base address: 0x40004500 Count: 2 */ + 0x4000520Au, /* Base address: 0x40005200 Count: 10 */ + 0x40006402u, /* Base address: 0x40006400 Count: 2 */ + 0x40010442u, /* Base address: 0x40010400 Count: 66 */ + 0x40010534u, /* Base address: 0x40010500 Count: 52 */ + 0x40010648u, /* Base address: 0x40010600 Count: 72 */ + 0x40010740u, /* Base address: 0x40010700 Count: 64 */ + 0x40010908u, /* Base address: 0x40010900 Count: 8 */ + 0x40010A38u, /* Base address: 0x40010A00 Count: 56 */ + 0x40010B53u, /* Base address: 0x40010B00 Count: 83 */ + 0x40010C40u, /* Base address: 0x40010C00 Count: 64 */ + 0x40010D3Eu, /* Base address: 0x40010D00 Count: 62 */ + 0x40010E47u, /* Base address: 0x40010E00 Count: 71 */ + 0x40010F29u, /* Base address: 0x40010F00 Count: 41 */ + 0x40011503u, /* Base address: 0x40011500 Count: 3 */ + 0x4001160Cu, /* Base address: 0x40011600 Count: 12 */ + 0x40011749u, /* Base address: 0x40011700 Count: 73 */ + 0x40011903u, /* Base address: 0x40011900 Count: 3 */ + 0x40014005u, /* Base address: 0x40014000 Count: 5 */ + 0x40014107u, /* Base address: 0x40014100 Count: 7 */ + 0x40014208u, /* Base address: 0x40014200 Count: 8 */ + 0x40014302u, /* Base address: 0x40014300 Count: 2 */ + 0x4001440Eu, /* Base address: 0x40014400 Count: 14 */ + 0x40014517u, /* Base address: 0x40014500 Count: 23 */ + 0x4001460Au, /* Base address: 0x40014600 Count: 10 */ + 0x4001470Au, /* Base address: 0x40014700 Count: 10 */ + 0x40014809u, /* Base address: 0x40014800 Count: 9 */ + 0x4001490Bu, /* Base address: 0x40014900 Count: 11 */ + 0x40014C07u, /* Base address: 0x40014C00 Count: 7 */ + 0x40014D0Au, /* Base address: 0x40014D00 Count: 10 */ + 0x40015006u, /* Base address: 0x40015000 Count: 6 */ + 0x40015101u, /* Base address: 0x40015100 Count: 1 */ + }; + + static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { + {0x27u, 0x02u}, + {0x7Eu, 0x02u}, + {0x00u, 0x04u}, + {0x01u, 0x0Cu}, + {0x10u, 0x0Cu}, + {0x11u, 0x84u}, + {0x18u, 0x04u}, + {0x1Cu, 0x20u}, + {0x29u, 0x02u}, + {0x31u, 0x10u}, + {0x78u, 0x20u}, + {0x7Cu, 0x40u}, + {0x3Au, 0x03u}, + {0x86u, 0x0Fu}, + {0x03u, 0x04u}, + {0x04u, 0x01u}, + {0x05u, 0x04u}, + {0x07u, 0x02u}, + {0x09u, 0x04u}, + {0x0Bu, 0x01u}, + {0x13u, 0x03u}, + {0x17u, 0x04u}, + {0x24u, 0x01u}, + {0x31u, 0x07u}, + {0x32u, 0x01u}, + {0x38u, 0x08u}, + {0x58u, 0x0Bu}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x99u}, + {0x5Fu, 0x01u}, + {0x80u, 0x17u}, + {0x81u, 0x01u}, + {0x82u, 0x28u}, + {0x84u, 0x20u}, + {0x86u, 0xD0u}, + {0x88u, 0x29u}, + {0x89u, 0x01u}, + {0x8Au, 0x46u}, + {0x8Du, 0x01u}, + {0x90u, 0xD6u}, + {0x91u, 0x01u}, + {0x94u, 0x02u}, + {0x95u, 0x01u}, + {0x98u, 0xD2u}, + {0x99u, 0x22u}, + {0x9Au, 0x04u}, + {0x9Bu, 0x08u}, + {0x9Cu, 0x04u}, + {0x9Du, 0x07u}, + {0x9Fu, 0x18u}, + {0xA0u, 0xD6u}, + {0xA1u, 0x10u}, + {0xA3u, 0x40u}, + {0xA4u, 0xD0u}, + {0xA5u, 0x08u}, + {0xA6u, 0x06u}, + {0xA7u, 0x21u}, + {0xA8u, 0x21u}, + {0xA9u, 0x04u}, + {0xAAu, 0x8Eu}, + {0xACu, 0xD6u}, + {0xB0u, 0x01u}, + {0xB2u, 0xF0u}, + {0xB4u, 0x0Fu}, + {0xB5u, 0x3Fu}, + {0xB6u, 0x08u}, + {0xB7u, 0x40u}, + {0xB8u, 0x20u}, + {0xB9u, 0x20u}, + {0xBAu, 0x08u}, + {0xBEu, 0x41u}, + {0xBFu, 0x10u}, + {0xD4u, 0x09u}, + {0xD8u, 0x0Bu}, + {0xD9u, 0x0Bu}, + {0xDBu, 0x0Bu}, + {0xDCu, 0x99u}, + {0xDDu, 0x90u}, + {0xDFu, 0x01u}, + {0x00u, 0x04u}, + {0x05u, 0x14u}, + {0x07u, 0x40u}, + {0x0Cu, 0x01u}, + {0x0Eu, 0x28u}, + {0x0Fu, 0x02u}, + {0x12u, 0x20u}, + {0x16u, 0x02u}, + {0x17u, 0x25u}, + {0x19u, 0x08u}, + {0x1Bu, 0x08u}, + {0x1Du, 0x14u}, + {0x1Fu, 0x61u}, + {0x21u, 0x02u}, + {0x25u, 0x80u}, + {0x26u, 0x20u}, + {0x2Fu, 0xA8u}, + {0x31u, 0x0Au}, + {0x34u, 0x01u}, + {0x36u, 0x05u}, + {0x37u, 0x60u}, + {0x38u, 0x20u}, + {0x39u, 0x04u}, + {0x3Au, 0x01u}, + {0x3Du, 0xA0u}, + {0x3Eu, 0x02u}, + {0x4Bu, 0xC0u}, + {0x5Cu, 0x01u}, + {0x5Du, 0x10u}, + {0x5Fu, 0x44u}, + {0x67u, 0x02u}, + {0x69u, 0x40u}, + {0x7Au, 0x80u}, + {0x7Eu, 0x80u}, + {0x80u, 0x40u}, + {0x85u, 0x0Cu}, + {0x8Cu, 0x10u}, + {0x8Du, 0x02u}, + {0x8Fu, 0x04u}, + {0xC0u, 0x74u}, + {0xC2u, 0xF0u}, + {0xC4u, 0xF4u}, + {0xCAu, 0xE0u}, + {0xCCu, 0xF3u}, + {0xCEu, 0xB7u}, + {0xD6u, 0xF0u}, + {0xD8u, 0x10u}, + {0xDEu, 0x81u}, + {0xE0u, 0x20u}, + {0xE2u, 0x42u}, + {0xE6u, 0x06u}, + {0xEEu, 0x02u}, + {0x01u, 0x08u}, + {0x02u, 0x9Fu}, + {0x03u, 0x20u}, + {0x05u, 0xD4u}, + {0x06u, 0x60u}, + {0x07u, 0x08u}, + {0x09u, 0x90u}, + {0x0Au, 0xFFu}, + {0x0Bu, 0x4Cu}, + {0x0Cu, 0xC0u}, + {0x0Du, 0xDCu}, + {0x0Eu, 0x01u}, + {0x10u, 0x1Fu}, + {0x11u, 0xDCu}, + {0x12u, 0x20u}, + {0x14u, 0x80u}, + {0x15u, 0x44u}, + {0x18u, 0xC0u}, + {0x1Au, 0x04u}, + {0x1Bu, 0x4Fu}, + {0x1Cu, 0xC0u}, + {0x1Du, 0x61u}, + {0x1Eu, 0x02u}, + {0x1Fu, 0x02u}, + {0x20u, 0x90u}, + {0x22u, 0x40u}, + {0x24u, 0xC0u}, + {0x25u, 0x21u}, + {0x26u, 0x08u}, + {0x27u, 0x0Eu}, + {0x28u, 0x7Fu}, + {0x2Au, 0x80u}, + {0x2Bu, 0x10u}, + {0x2Du, 0x4Cu}, + {0x2Fu, 0x90u}, + {0x31u, 0x0Fu}, + {0x33u, 0x61u}, + {0x34u, 0xFFu}, + {0x35u, 0x10u}, + {0x37u, 0x80u}, + {0x3Bu, 0x0Cu}, + {0x3Eu, 0x10u}, + {0x3Fu, 0x50u}, + {0x56u, 0x02u}, + {0x57u, 0x28u}, + {0x58u, 0x04u}, + {0x59u, 0x0Bu}, + {0x5Bu, 0x0Bu}, + {0x5Cu, 0x90u}, + {0x5Du, 0x90u}, + {0x5Fu, 0x01u}, + {0x85u, 0x04u}, + {0x87u, 0x02u}, + {0x89u, 0x04u}, + {0x8Bu, 0x01u}, + {0x8Eu, 0x02u}, + {0x8Fu, 0x04u}, + {0x92u, 0x01u}, + {0x97u, 0x03u}, + {0xA3u, 0x04u}, + {0xACu, 0x01u}, + {0xAEu, 0x02u}, + {0xB3u, 0x07u}, + {0xB6u, 0x03u}, + {0xBEu, 0x40u}, + {0xD6u, 0x08u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x90u}, + {0xDDu, 0x90u}, + {0xDFu, 0x01u}, + {0x01u, 0x80u}, + {0x05u, 0x38u}, + {0x06u, 0x82u}, + {0x08u, 0x21u}, + {0x09u, 0x20u}, + {0x0Cu, 0x04u}, + {0x0Du, 0x02u}, + {0x0Eu, 0x2Au}, + {0x11u, 0x40u}, + {0x17u, 0x25u}, + {0x19u, 0x40u}, + {0x1Cu, 0x04u}, + {0x21u, 0x08u}, + {0x24u, 0x03u}, + {0x25u, 0x22u}, + {0x27u, 0x60u}, + {0x2Au, 0x01u}, + {0x2Fu, 0x2Au}, + {0x31u, 0x08u}, + {0x34u, 0x04u}, + {0x36u, 0x01u}, + {0x37u, 0x60u}, + {0x38u, 0x60u}, + {0x39u, 0x04u}, + {0x3Au, 0x10u}, + {0x3Cu, 0x80u}, + {0x3Eu, 0x14u}, + {0x3Fu, 0x02u}, + {0x59u, 0x40u}, + {0x62u, 0x80u}, + {0x67u, 0x20u}, + {0x6Cu, 0x80u}, + {0x6Du, 0x80u}, + {0x6Eu, 0x1Eu}, + {0x6Fu, 0x07u}, + {0x74u, 0x40u}, + {0x76u, 0x02u}, + {0x7Eu, 0x80u}, + {0x90u, 0x60u}, + {0x91u, 0x44u}, + {0x94u, 0x05u}, + {0x97u, 0x04u}, + {0x99u, 0x18u}, + {0x9Au, 0x01u}, + {0x9Eu, 0x02u}, + {0x9Fu, 0x65u}, + {0xA1u, 0x80u}, + {0xA3u, 0x20u}, + {0xA5u, 0x50u}, + {0xA6u, 0x95u}, + {0xA7u, 0x85u}, + {0xAAu, 0x01u}, + {0xB1u, 0x10u}, + {0xB3u, 0x01u}, + {0xC0u, 0xF1u}, + {0xC2u, 0xF8u}, + {0xC4u, 0x71u}, + {0xCAu, 0x71u}, + {0xCCu, 0xF2u}, + {0xCEu, 0xFEu}, + {0xD6u, 0x08u}, + {0xD8u, 0x48u}, + {0xDEu, 0x80u}, + {0xEAu, 0x04u}, + {0x9Eu, 0x80u}, + {0xAAu, 0x40u}, + {0xAEu, 0xC0u}, + {0xB2u, 0x20u}, + {0xB6u, 0x10u}, + {0xB7u, 0x80u}, + {0xEAu, 0x08u}, + {0xEEu, 0x08u}, + {0x00u, 0x01u}, + {0x04u, 0xC4u}, + {0x06u, 0x12u}, + {0x08u, 0xF8u}, + {0x09u, 0x01u}, + {0x0Au, 0x06u}, + {0x0Cu, 0x40u}, + {0x10u, 0x04u}, + {0x12u, 0xAAu}, + {0x1Au, 0xFCu}, + {0x1Cu, 0x40u}, + {0x20u, 0x20u}, + {0x22u, 0x40u}, + {0x26u, 0x10u}, + {0x30u, 0x1Cu}, + {0x31u, 0x01u}, + {0x32u, 0x02u}, + {0x34u, 0xE0u}, + {0x36u, 0x01u}, + {0x3Eu, 0x44u}, + {0x3Fu, 0x01u}, + {0x40u, 0x46u}, + {0x41u, 0x02u}, + {0x42u, 0x30u}, + {0x45u, 0xD2u}, + {0x46u, 0xECu}, + {0x47u, 0x0Fu}, + {0x48u, 0x1Fu}, + {0x49u, 0xFFu}, + {0x4Au, 0xFFu}, + {0x4Bu, 0xFFu}, + {0x4Fu, 0x2Cu}, + {0x56u, 0x01u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Au, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x09u}, + {0x5Du, 0x09u}, + {0x5Fu, 0x01u}, + {0x62u, 0xC0u}, + {0x66u, 0x80u}, + {0x68u, 0x40u}, + {0x69u, 0x40u}, + {0x6Eu, 0x08u}, + {0x8Fu, 0x02u}, + {0x99u, 0x03u}, + {0x9Bu, 0x04u}, + {0x9Du, 0x01u}, + {0xA7u, 0x07u}, + {0xA9u, 0x04u}, + {0xABu, 0x03u}, + {0xB3u, 0x07u}, + {0xD9u, 0x04u}, + {0xDCu, 0x90u}, + {0xDFu, 0x01u}, + {0x00u, 0x80u}, + {0x01u, 0x20u}, + {0x02u, 0x80u}, + {0x03u, 0x10u}, + {0x08u, 0x50u}, + {0x09u, 0x80u}, + {0x0Au, 0x40u}, + {0x12u, 0x20u}, + {0x13u, 0x02u}, + {0x19u, 0xA0u}, + {0x1Au, 0x54u}, + {0x1Bu, 0x11u}, + {0x22u, 0x02u}, + {0x27u, 0x10u}, + {0x2Cu, 0x10u}, + {0x2Du, 0x20u}, + {0x36u, 0x40u}, + {0x37u, 0x10u}, + {0x3Au, 0x20u}, + {0x3Eu, 0x40u}, + {0x42u, 0x50u}, + {0x43u, 0x10u}, + {0x48u, 0x40u}, + {0x49u, 0x21u}, + {0x4Au, 0x20u}, + {0x50u, 0x10u}, + {0x51u, 0x80u}, + {0x53u, 0x08u}, + {0x59u, 0x90u}, + {0x5Au, 0x0Au}, + {0x61u, 0x04u}, + {0x62u, 0x02u}, + {0x63u, 0x05u}, + {0x68u, 0x80u}, + {0x69u, 0x40u}, + {0x6Au, 0x20u}, + {0x6Bu, 0x20u}, + {0x70u, 0x48u}, + {0x72u, 0x08u}, + {0x73u, 0x80u}, + {0x78u, 0x20u}, + {0x7Bu, 0x08u}, + {0x81u, 0x40u}, + {0x83u, 0x02u}, + {0x85u, 0x20u}, + {0x87u, 0x20u}, + {0x88u, 0x10u}, + {0x8Du, 0x40u}, + {0x8Fu, 0x10u}, + {0x92u, 0x0Au}, + {0x93u, 0x05u}, + {0x94u, 0xA0u}, + {0x95u, 0x80u}, + {0x96u, 0x44u}, + {0x99u, 0x14u}, + {0x9Cu, 0x60u}, + {0x9Du, 0x01u}, + {0x9Eu, 0xC8u}, + {0x9Fu, 0x90u}, + {0xA2u, 0x40u}, + {0xA4u, 0x88u}, + {0xA7u, 0x91u}, + {0xA8u, 0x10u}, + {0xA9u, 0x80u}, + {0xAEu, 0x41u}, + {0xB0u, 0x48u}, + {0xB1u, 0x01u}, + {0xB2u, 0x02u}, + {0xB3u, 0x02u}, + {0xC0u, 0x0Fu}, + {0xC2u, 0x0Bu}, + {0xC4u, 0x0Cu}, + {0xCAu, 0x60u}, + {0xCCu, 0x30u}, + {0xCEu, 0x14u}, + {0xD0u, 0x07u}, + {0xD2u, 0x04u}, + {0xD6u, 0x0Fu}, + {0xD8u, 0x0Fu}, + {0xE0u, 0x20u}, + {0xE4u, 0x10u}, + {0xE6u, 0x41u}, + {0xE8u, 0x08u}, + {0x00u, 0x69u}, + {0x02u, 0x96u}, + {0x08u, 0x33u}, + {0x0Au, 0xCCu}, + {0x11u, 0x96u}, + {0x12u, 0xFFu}, + {0x13u, 0x69u}, + {0x17u, 0xFFu}, + {0x19u, 0xFFu}, + {0x1Au, 0xFFu}, + {0x1Fu, 0xFFu}, + {0x20u, 0x55u}, + {0x21u, 0x0Fu}, + {0x22u, 0xAAu}, + {0x23u, 0xF0u}, + {0x29u, 0x33u}, + {0x2Au, 0xFFu}, + {0x2Bu, 0xCCu}, + {0x2Cu, 0x0Fu}, + {0x2Du, 0x55u}, + {0x2Eu, 0xF0u}, + {0x2Fu, 0xAAu}, + {0x32u, 0xFFu}, + {0x35u, 0xFFu}, + {0x3Eu, 0x04u}, + {0x3Fu, 0x10u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Fu, 0x01u}, + {0x84u, 0x24u}, + {0x86u, 0x09u}, + {0x87u, 0x40u}, + {0x8Bu, 0x03u}, + {0x8Eu, 0x03u}, + {0x92u, 0x24u}, + {0x93u, 0x30u}, + {0x94u, 0x40u}, + {0x95u, 0x08u}, + {0x98u, 0x24u}, + {0x99u, 0x44u}, + {0x9Au, 0x12u}, + {0x9Bu, 0x11u}, + {0x9Eu, 0x18u}, + {0x9Fu, 0x04u}, + {0xA0u, 0x80u}, + {0xA5u, 0x44u}, + {0xA7u, 0x22u}, + {0xAAu, 0x04u}, + {0xAEu, 0x20u}, + {0xAFu, 0x44u}, + {0xB0u, 0x07u}, + {0xB1u, 0x70u}, + {0xB2u, 0x40u}, + {0xB3u, 0x08u}, + {0xB4u, 0x80u}, + {0xB5u, 0x07u}, + {0xB6u, 0x38u}, + {0xBEu, 0x14u}, + {0xBFu, 0x04u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x99u}, + {0xDFu, 0x01u}, + {0x03u, 0x12u}, + {0x05u, 0x22u}, + {0x08u, 0x04u}, + {0x0Au, 0x45u}, + {0x0Du, 0x10u}, + {0x0Eu, 0x80u}, + {0x10u, 0x08u}, + {0x12u, 0x40u}, + {0x13u, 0x80u}, + {0x15u, 0x80u}, + {0x16u, 0x82u}, + {0x17u, 0x20u}, + {0x19u, 0x14u}, + {0x1Au, 0x01u}, + {0x1Bu, 0x02u}, + {0x1Eu, 0x10u}, + {0x21u, 0x10u}, + {0x22u, 0x06u}, + {0x23u, 0x08u}, + {0x26u, 0x20u}, + {0x2Bu, 0x11u}, + {0x2Du, 0x20u}, + {0x2Eu, 0x82u}, + {0x30u, 0x80u}, + {0x31u, 0x08u}, + {0x32u, 0x02u}, + {0x33u, 0x10u}, + {0x35u, 0x02u}, + {0x36u, 0x40u}, + {0x37u, 0x28u}, + {0x39u, 0x20u}, + {0x3Au, 0x08u}, + {0x58u, 0x28u}, + {0x59u, 0x81u}, + {0x81u, 0x08u}, + {0x84u, 0x04u}, + {0x89u, 0x20u}, + {0x8Bu, 0x20u}, + {0x92u, 0x02u}, + {0x93u, 0x05u}, + {0x94u, 0x80u}, + {0x95u, 0x01u}, + {0x96u, 0x51u}, + {0x99u, 0x22u}, + {0x9Bu, 0x20u}, + {0x9Eu, 0x82u}, + {0x9Fu, 0x18u}, + {0xA2u, 0x40u}, + {0xA6u, 0x22u}, + {0xA7u, 0x91u}, + {0xB2u, 0x20u}, + {0xB3u, 0x01u}, + {0xB6u, 0x04u}, + {0xB7u, 0x40u}, + {0xC0u, 0x55u}, + {0xC2u, 0x5Fu}, + {0xC4u, 0xDBu}, + {0xCAu, 0xBAu}, + {0xCCu, 0xFFu}, + {0xCEu, 0x06u}, + {0xD6u, 0x0Fu}, + {0xE2u, 0x09u}, + {0x02u, 0x04u}, + {0x04u, 0x04u}, + {0x05u, 0x10u}, + {0x06u, 0x01u}, + {0x09u, 0x20u}, + {0x0Au, 0x03u}, + {0x0Cu, 0x80u}, + {0x0Fu, 0x08u}, + {0x11u, 0x01u}, + {0x12u, 0x04u}, + {0x14u, 0x80u}, + {0x17u, 0x06u}, + {0x18u, 0x04u}, + {0x19u, 0x08u}, + {0x1Au, 0x02u}, + {0x1Bu, 0x02u}, + {0x1Cu, 0x18u}, + {0x1Eu, 0x60u}, + {0x20u, 0x28u}, + {0x22u, 0x50u}, + {0x24u, 0x80u}, + {0x25u, 0x08u}, + {0x27u, 0x04u}, + {0x28u, 0x80u}, + {0x2Cu, 0x30u}, + {0x2Eu, 0x48u}, + {0x2Fu, 0x08u}, + {0x30u, 0x78u}, + {0x31u, 0x01u}, + {0x33u, 0x0Eu}, + {0x34u, 0x07u}, + {0x35u, 0x20u}, + {0x36u, 0x80u}, + {0x37u, 0x10u}, + {0x38u, 0x80u}, + {0x3Eu, 0x41u}, + {0x3Fu, 0x51u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Cu, 0x99u}, + {0x5Fu, 0x01u}, + {0x80u, 0x69u}, + {0x81u, 0x0Fu}, + {0x82u, 0x96u}, + {0x83u, 0xF0u}, + {0x88u, 0x33u}, + {0x8Au, 0xCCu}, + {0x8Cu, 0x0Fu}, + {0x8Du, 0x55u}, + {0x8Eu, 0xF0u}, + {0x8Fu, 0xAAu}, + {0x91u, 0x96u}, + {0x93u, 0x69u}, + {0x95u, 0xFFu}, + {0x9Bu, 0xFFu}, + {0x9Fu, 0xFFu}, + {0xA0u, 0x55u}, + {0xA2u, 0xAAu}, + {0xA4u, 0xFFu}, + {0xA8u, 0xFFu}, + {0xA9u, 0x33u}, + {0xABu, 0xCCu}, + {0xAEu, 0xFFu}, + {0xB0u, 0xFFu}, + {0xB5u, 0xFFu}, + {0xBEu, 0x01u}, + {0xBFu, 0x10u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDFu, 0x01u}, + {0x01u, 0x20u}, + {0x03u, 0x92u}, + {0x05u, 0x22u}, + {0x06u, 0x02u}, + {0x08u, 0x10u}, + {0x0Au, 0x51u}, + {0x11u, 0x21u}, + {0x12u, 0x22u}, + {0x15u, 0x40u}, + {0x16u, 0x80u}, + {0x17u, 0x28u}, + {0x19u, 0x22u}, + {0x1Bu, 0x40u}, + {0x1Fu, 0x02u}, + {0x21u, 0x08u}, + {0x22u, 0x01u}, + {0x23u, 0x25u}, + {0x25u, 0x10u}, + {0x28u, 0x10u}, + {0x2Bu, 0x11u}, + {0x2Du, 0x20u}, + {0x31u, 0x08u}, + {0x33u, 0x11u}, + {0x35u, 0x02u}, + {0x36u, 0x40u}, + {0x37u, 0x28u}, + {0x38u, 0x80u}, + {0x3Au, 0x24u}, + {0x3Eu, 0x82u}, + {0x6Du, 0x40u}, + {0x6Eu, 0x80u}, + {0x83u, 0x08u}, + {0x86u, 0x02u}, + {0xC0u, 0xDFu}, + {0xC2u, 0x0Fu}, + {0xC4u, 0xFFu}, + {0xCAu, 0x2Au}, + {0xCCu, 0xF7u}, + {0xCEu, 0x9Eu}, + {0xE0u, 0x04u}, + {0xE4u, 0x08u}, + {0xA8u, 0x10u}, + {0xB0u, 0x01u}, + {0xECu, 0x20u}, + {0x82u, 0x06u}, + {0x86u, 0x01u}, + {0x8Au, 0x0Au}, + {0x9Eu, 0x02u}, + {0xA8u, 0x0Cu}, + {0xAEu, 0x01u}, + {0xB2u, 0x01u}, + {0xB6u, 0x0Eu}, + {0xBEu, 0x04u}, + {0xD8u, 0x0Bu}, + {0xDCu, 0x09u}, + {0xDFu, 0x01u}, + {0x01u, 0x20u}, + {0x02u, 0x10u}, + {0x03u, 0x40u}, + {0x04u, 0x04u}, + {0x05u, 0x20u}, + {0x06u, 0x80u}, + {0x0Au, 0x01u}, + {0x0Du, 0x88u}, + {0x12u, 0x01u}, + {0x13u, 0x20u}, + {0x17u, 0x60u}, + {0x1Au, 0x01u}, + {0x1Bu, 0x04u}, + {0x1Cu, 0x04u}, + {0x1Du, 0x08u}, + {0x1Fu, 0x14u}, + {0x24u, 0x20u}, + {0x25u, 0x50u}, + {0x26u, 0x10u}, + {0x27u, 0x04u}, + {0x2Cu, 0x80u}, + {0x2Fu, 0x26u}, + {0x37u, 0x64u}, + {0x3Du, 0x80u}, + {0x3Eu, 0x16u}, + {0x44u, 0x80u}, + {0x47u, 0x60u}, + {0x4Cu, 0x01u}, + {0x4Du, 0x20u}, + {0x4Fu, 0x05u}, + {0x56u, 0xA0u}, + {0x57u, 0x89u}, + {0x64u, 0x20u}, + {0x66u, 0x20u}, + {0x67u, 0x01u}, + {0x7Au, 0x80u}, + {0x7Eu, 0x80u}, + {0x8Au, 0x01u}, + {0x8Cu, 0x80u}, + {0x8Du, 0x80u}, + {0x90u, 0x02u}, + {0x92u, 0x14u}, + {0x97u, 0x24u}, + {0x98u, 0x20u}, + {0x99u, 0x20u}, + {0x9Au, 0x13u}, + {0x9Bu, 0x60u}, + {0x9Cu, 0x01u}, + {0x9Du, 0x80u}, + {0x9Eu, 0x80u}, + {0xA0u, 0x80u}, + {0xA1u, 0x80u}, + {0xA2u, 0x80u}, + {0xA3u, 0x22u}, + {0xA5u, 0x10u}, + {0xA6u, 0x10u}, + {0xA7u, 0x8Du}, + {0xA9u, 0x08u}, + {0xC0u, 0x7Eu}, + {0xC2u, 0xA1u}, + {0xC4u, 0xC3u}, + {0xCAu, 0xF0u}, + {0xCCu, 0x70u}, + {0xCEu, 0xF0u}, + {0xD0u, 0xB0u}, + {0xD2u, 0x30u}, + {0xD8u, 0x70u}, + {0xDEu, 0x81u}, + {0xE0u, 0x10u}, + {0xE4u, 0x40u}, + {0xE6u, 0x80u}, + {0xE8u, 0x01u}, + {0xEEu, 0x0Au}, + {0xAAu, 0x80u}, + {0xE8u, 0x01u}, + {0xEEu, 0x0Au}, + {0x0Du, 0x80u}, + {0x33u, 0x80u}, + {0x36u, 0x40u}, + {0xC2u, 0x80u}, + {0xCCu, 0x30u}, + {0x53u, 0x01u}, + {0x5Du, 0x20u}, + {0xA1u, 0x80u}, + {0xA6u, 0x40u}, + {0xA7u, 0x80u}, + {0xD4u, 0x80u}, + {0xD6u, 0x20u}, + {0x89u, 0x80u}, + {0x8Fu, 0x01u}, + {0x97u, 0x02u}, + {0xA1u, 0x80u}, + {0xA6u, 0x40u}, + {0xA7u, 0x80u}, + {0xADu, 0x20u}, + {0xEEu, 0x40u}, + {0xA6u, 0x40u}, + {0xA7u, 0x80u}, + {0x00u, 0x10u}, + {0x09u, 0x40u}, + {0x0Fu, 0x01u}, + {0x11u, 0x01u}, + {0x17u, 0x04u}, + {0x61u, 0x20u}, + {0x63u, 0x02u}, + {0x81u, 0x20u}, + {0x87u, 0x01u}, + {0xC0u, 0x02u}, + {0xC2u, 0x03u}, + {0xC4u, 0x0Cu}, + {0xD6u, 0x02u}, + {0xD8u, 0x02u}, + {0x08u, 0x04u}, + {0x0Cu, 0x02u}, + {0x56u, 0x20u}, + {0x5Au, 0x04u}, + {0x5Fu, 0x10u}, + {0x62u, 0x02u}, + {0x83u, 0x01u}, + {0x84u, 0x02u}, + {0x8Au, 0x22u}, + {0x90u, 0x10u}, + {0x93u, 0x01u}, + {0xA0u, 0x80u}, + {0xB1u, 0x41u}, + {0xB4u, 0x80u}, + {0xB7u, 0x04u}, + {0xC2u, 0x0Cu}, + {0xD4u, 0x02u}, + {0xD6u, 0x06u}, + {0xD8u, 0x02u}, + {0xE0u, 0x04u}, + {0xE4u, 0x04u}, + {0xECu, 0x02u}, + {0xEEu, 0x0Du}, + {0x54u, 0x80u}, + {0x80u, 0x10u}, + {0x90u, 0x10u}, + {0x98u, 0x04u}, + {0xA0u, 0x80u}, + {0xA2u, 0x20u}, + {0xAFu, 0x10u}, + {0xB2u, 0x24u}, + {0xD4u, 0x02u}, + {0xECu, 0x05u}, + {0x08u, 0x08u}, + {0x0Fu, 0x40u}, + {0x9Eu, 0x02u}, + {0xA2u, 0x20u}, + {0xA4u, 0x10u}, + {0xACu, 0x10u}, + {0xAEu, 0x02u}, + {0xB0u, 0x04u}, + {0xC2u, 0x0Cu}, + {0xEEu, 0x01u}, + {0x23u, 0x20u}, + {0x24u, 0x04u}, + {0x8Au, 0x40u}, + {0x8Cu, 0x04u}, + {0x8Du, 0x04u}, + {0xAEu, 0x40u}, + {0xAFu, 0x80u}, + {0xC8u, 0x60u}, + {0xEEu, 0x50u}, + {0x05u, 0x04u}, + {0x51u, 0x20u}, + {0x56u, 0x40u}, + {0x9Au, 0x40u}, + {0x9Du, 0x04u}, + {0xA1u, 0x20u}, + {0xA9u, 0x20u}, + {0xB3u, 0x20u}, + {0xC0u, 0x20u}, + {0xD4u, 0x60u}, + {0xEAu, 0x20u}, + {0x9Bu, 0x80u}, + {0x9Eu, 0x02u}, + {0xA2u, 0x20u}, + {0xA4u, 0x10u}, + {0xABu, 0x80u}, + {0xACu, 0x08u}, + {0xAFu, 0x40u}, + {0x00u, 0x20u}, + {0x06u, 0x02u}, + {0x52u, 0x20u}, + {0x5Bu, 0x80u}, + {0x9Bu, 0x80u}, + {0x9Eu, 0x02u}, + {0xA2u, 0x20u}, + {0xA4u, 0x10u}, + {0xC0u, 0x03u}, + {0xD4u, 0x05u}, + {0x01u, 0x01u}, + {0x0Bu, 0x01u}, + {0x0Du, 0x01u}, + {0x0Fu, 0x01u}, + {0x11u, 0x01u}, + {0x1Bu, 0x01u}, + {0x00u, 0x0Au}, + }; + + + + CYPACKED typedef struct { + void CYFAR *address; + uint16 size; + } CYPACKED_ATTR cfg_memset_t; + + + CYPACKED typedef struct { + void CYFAR *dest; + const void CYCODE *src; + uint16 size; + } CYPACKED_ATTR cfg_memcpy_t; + + static const cfg_memset_t CYCODE cfg_memset_list [] = { + /* address, size */ + {(void CYFAR *)(CYREG_PRT1_DR), 16u}, + {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u}, + {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 512u}, + {(void CYFAR *)(CYDEV_UCFG_B1_P3_U1_BASE), 1408u}, + {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u}, + {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u}, + {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u}, + }; + + /* UDB_1_1_1_CONFIG Address: CYDEV_UCFG_B1_P3_U0_BASE Size (bytes): 128 */ + static const uint8 CYCODE BS_UDB_1_1_1_CONFIG_VAL[] = { + 0x00u, 0x01u, 0x02u, 0x00u, 0x40u, 0x01u, 0x30u, 0x00u, 0x34u, 0x01u, 0x43u, 0x00u, 0x00u, 0xF8u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x0Cu, 0x01u, 0x00u, 0x8Bu, 0x00u, 0x04u, 0x00u, 0x25u, 0x01u, 0x0Au, + 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x06u, 0x00u, 0x51u, 0x58u, 0x00u, 0x23u, 0xE0u, 0x11u, 0x00u, 0x62u, 0x01u, + 0x00u, 0x00u, 0x0Fu, 0xE0u, 0x70u, 0x03u, 0x00u, 0x1Cu, 0x00u, 0x80u, 0x20u, 0x20u, 0x00u, 0x00u, 0x00u, 0x04u, + 0x62u, 0x01u, 0x50u, 0x00u, 0x04u, 0xDEu, 0xFBu, 0xCDu, 0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, + 0x04u, 0x00u, 0x00u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x0Bu, 0x0Bu, 0x0Bu, 0x0Bu, 0x99u, 0x99u, 0x00u, 0x01u, + 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + + static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { + /* dest, src, size */ + {(void CYFAR *)(CYDEV_UCFG_B1_P3_U0_BASE), BS_UDB_1_1_1_CONFIG_VAL, 128u}, + }; + + uint8 CYDATA i; + + /* Zero out critical memory blocks before beginning configuration */ + for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) + { + const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; + CYMEMZERO(ms->address, (uint32)(ms->size)); + } + + /* Copy device configuration data into registers */ + for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++) + { + const cfg_memcpy_t CYCODE * CYDATA mc = &cfg_memcpy_list[i]; + void * CYDATA destPtr = mc->dest; + const void CYCODE * CYDATA srcPtr = mc->src; + uint16 CYDATA numBytes = mc->size; + CYCONFIGCPYCODE(destPtr, srcPtr, numBytes); + } + + cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); + + /* Enable digital routing */ + CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL) | 0x02u); + CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL) | 0x02u); + + /* Enable UDB array */ + CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0) | 0x40u); + CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2) | 0x10u); + } + + /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT0_DR), (const void CYCODE *)(BS_IOPINS0_0_VAL), 10u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT12_DM0), (const void CYCODE *)(BS_IOPINS0_7_VAL), 8u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT12_DM0 + 0x00000009u), (const void CYCODE *)(BS_IOPINS1_7_VAL), 5u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT15_DR), (const void CYCODE *)(BS_IOPINS0_8_VAL), 10u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT2_DM0), (const void CYCODE *)(BS_IOPINS0_2_VAL), 8u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT3_DM0), (const void CYCODE *)(BS_IOPINS0_3_VAL), 8u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT4_DM0), (const void CYCODE *)(BS_IOPINS0_4_VAL), 8u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT5_DM0), (const void CYCODE *)(BS_IOPINS0_5_VAL), 8u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT6_DM0), (const void CYCODE *)(BS_IOPINS0_6_VAL), 8u); + + /* Switch Boost to the precision bandgap reference from its internal reference */ + CY_SET_REG8((void CYXDATA *)CYREG_BOOST_CR2, (CY_GET_REG8((void CYXDATA *)CYREG_BOOST_CR2) | 0x08u)); + + /* Perform basic analog initialization to defaults */ + AnalogSetDefault(); + + /* Configure alternate active mode */ + CYCONFIGCPY((void CYFAR *)CYDEV_PM_STBY_BASE, (const void CYFAR *)CYDEV_PM_ACT_BASE, 14u); +} diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h new file mode 100755 index 00000000..191ee788 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h @@ -0,0 +1,28 @@ +/******************************************************************************* +* FILENAME: cyfitter_cfg.h +* PSoC Creator 3.0 Component Pack 7 +* +* Description: +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright 2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#ifndef CYFITTER_CFG_H +#define CYFITTER_CFG_H + +#include + +extern void cyfitter_cfg(void); + +/* Analog Set/Unset methods */ +extern void SetAnalogRoutingPumps(uint8 enabled); + + +#endif /* CYFITTER_CFG_H */ + +/*[]*/ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyfittergnu.inc new file mode 100755 index 00000000..f4ad5e66 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -0,0 +1,2676 @@ +.ifndef INCLUDED_CYFITTERGNU_INC +.set INCLUDED_CYFITTERGNU_INC, 1 +.include "cydevicegnu.inc" +.include "cydevicegnu_trm.inc" + +/* USBFS_bus_reset */ +.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_bus_reset__INTC_MASK, 0x800000 +.set USBFS_bus_reset__INTC_NUMBER, 23 +.set USBFS_bus_reset__INTC_PRIOR_NUM, 7 +.set USBFS_bus_reset__INTC_PRIOR_REG, CYREG_NVIC_PRI_23 +.set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* USBFS_arb_int */ +.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_arb_int__INTC_MASK, 0x400000 +.set USBFS_arb_int__INTC_NUMBER, 22 +.set USBFS_arb_int__INTC_PRIOR_NUM, 7 +.set USBFS_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22 +.set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* USBFS_sof_int */ +.set USBFS_sof_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_sof_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_sof_int__INTC_MASK, 0x200000 +.set USBFS_sof_int__INTC_NUMBER, 21 +.set USBFS_sof_int__INTC_PRIOR_NUM, 7 +.set USBFS_sof_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_21 +.set USBFS_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SCSI_Out_DBx */ +.set SCSI_Out_DBx__0__AG, CYREG_PRT5_AG +.set SCSI_Out_DBx__0__AMUX, CYREG_PRT5_AMUX +.set SCSI_Out_DBx__0__BIE, CYREG_PRT5_BIE +.set SCSI_Out_DBx__0__BIT_MASK, CYREG_PRT5_BIT_MASK +.set SCSI_Out_DBx__0__BYP, CYREG_PRT5_BYP +.set SCSI_Out_DBx__0__CTL, CYREG_PRT5_CTL +.set SCSI_Out_DBx__0__DM0, CYREG_PRT5_DM0 +.set SCSI_Out_DBx__0__DM1, CYREG_PRT5_DM1 +.set SCSI_Out_DBx__0__DM2, CYREG_PRT5_DM2 +.set SCSI_Out_DBx__0__DR, CYREG_PRT5_DR +.set SCSI_Out_DBx__0__INP_DIS, CYREG_PRT5_INP_DIS +.set SCSI_Out_DBx__0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG +.set SCSI_Out_DBx__0__LCD_EN, CYREG_PRT5_LCD_EN +.set SCSI_Out_DBx__0__MASK, 0x02 +.set SCSI_Out_DBx__0__PC, CYREG_PRT5_PC1 +.set SCSI_Out_DBx__0__PORT, 5 +.set SCSI_Out_DBx__0__PRT, CYREG_PRT5_PRT +.set SCSI_Out_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL +.set SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN +.set SCSI_Out_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 +.set SCSI_Out_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 +.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 +.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 +.set SCSI_Out_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT +.set SCSI_Out_DBx__0__PS, CYREG_PRT5_PS +.set SCSI_Out_DBx__0__SHIFT, 1 +.set SCSI_Out_DBx__0__SLW, CYREG_PRT5_SLW +.set SCSI_Out_DBx__1__AG, CYREG_PRT5_AG +.set SCSI_Out_DBx__1__AMUX, CYREG_PRT5_AMUX +.set SCSI_Out_DBx__1__BIE, CYREG_PRT5_BIE +.set SCSI_Out_DBx__1__BIT_MASK, CYREG_PRT5_BIT_MASK +.set SCSI_Out_DBx__1__BYP, CYREG_PRT5_BYP +.set SCSI_Out_DBx__1__CTL, CYREG_PRT5_CTL +.set SCSI_Out_DBx__1__DM0, CYREG_PRT5_DM0 +.set SCSI_Out_DBx__1__DM1, CYREG_PRT5_DM1 +.set SCSI_Out_DBx__1__DM2, CYREG_PRT5_DM2 +.set SCSI_Out_DBx__1__DR, CYREG_PRT5_DR +.set SCSI_Out_DBx__1__INP_DIS, CYREG_PRT5_INP_DIS +.set SCSI_Out_DBx__1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG +.set SCSI_Out_DBx__1__LCD_EN, CYREG_PRT5_LCD_EN +.set SCSI_Out_DBx__1__MASK, 0x01 +.set SCSI_Out_DBx__1__PC, CYREG_PRT5_PC0 +.set SCSI_Out_DBx__1__PORT, 5 +.set SCSI_Out_DBx__1__PRT, CYREG_PRT5_PRT +.set SCSI_Out_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL +.set SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN +.set SCSI_Out_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 +.set SCSI_Out_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 +.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 +.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 +.set SCSI_Out_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT +.set SCSI_Out_DBx__1__PS, CYREG_PRT5_PS +.set SCSI_Out_DBx__1__SHIFT, 0 +.set SCSI_Out_DBx__1__SLW, CYREG_PRT5_SLW +.set SCSI_Out_DBx__2__AG, CYREG_PRT6_AG +.set SCSI_Out_DBx__2__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out_DBx__2__BIE, CYREG_PRT6_BIE +.set SCSI_Out_DBx__2__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out_DBx__2__BYP, CYREG_PRT6_BYP +.set SCSI_Out_DBx__2__CTL, CYREG_PRT6_CTL +.set SCSI_Out_DBx__2__DM0, CYREG_PRT6_DM0 +.set SCSI_Out_DBx__2__DM1, CYREG_PRT6_DM1 +.set SCSI_Out_DBx__2__DM2, CYREG_PRT6_DM2 +.set SCSI_Out_DBx__2__DR, CYREG_PRT6_DR +.set SCSI_Out_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out_DBx__2__MASK, 0x20 +.set SCSI_Out_DBx__2__PC, CYREG_PRT6_PC5 +.set SCSI_Out_DBx__2__PORT, 6 +.set SCSI_Out_DBx__2__PRT, CYREG_PRT6_PRT +.set SCSI_Out_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out_DBx__2__PS, CYREG_PRT6_PS +.set SCSI_Out_DBx__2__SHIFT, 5 +.set SCSI_Out_DBx__2__SLW, CYREG_PRT6_SLW +.set SCSI_Out_DBx__3__AG, CYREG_PRT6_AG +.set SCSI_Out_DBx__3__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out_DBx__3__BIE, CYREG_PRT6_BIE +.set SCSI_Out_DBx__3__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out_DBx__3__BYP, CYREG_PRT6_BYP +.set SCSI_Out_DBx__3__CTL, CYREG_PRT6_CTL +.set SCSI_Out_DBx__3__DM0, CYREG_PRT6_DM0 +.set SCSI_Out_DBx__3__DM1, CYREG_PRT6_DM1 +.set SCSI_Out_DBx__3__DM2, CYREG_PRT6_DM2 +.set SCSI_Out_DBx__3__DR, CYREG_PRT6_DR +.set SCSI_Out_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out_DBx__3__MASK, 0x10 +.set SCSI_Out_DBx__3__PC, CYREG_PRT6_PC4 +.set SCSI_Out_DBx__3__PORT, 6 +.set SCSI_Out_DBx__3__PRT, CYREG_PRT6_PRT +.set SCSI_Out_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out_DBx__3__PS, CYREG_PRT6_PS +.set SCSI_Out_DBx__3__SHIFT, 4 +.set SCSI_Out_DBx__3__SLW, CYREG_PRT6_SLW +.set SCSI_Out_DBx__4__AG, CYREG_PRT2_AG +.set SCSI_Out_DBx__4__AMUX, CYREG_PRT2_AMUX +.set SCSI_Out_DBx__4__BIE, CYREG_PRT2_BIE +.set SCSI_Out_DBx__4__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Out_DBx__4__BYP, CYREG_PRT2_BYP +.set SCSI_Out_DBx__4__CTL, CYREG_PRT2_CTL +.set SCSI_Out_DBx__4__DM0, CYREG_PRT2_DM0 +.set SCSI_Out_DBx__4__DM1, CYREG_PRT2_DM1 +.set SCSI_Out_DBx__4__DM2, CYREG_PRT2_DM2 +.set SCSI_Out_DBx__4__DR, CYREG_PRT2_DR +.set SCSI_Out_DBx__4__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Out_DBx__4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Out_DBx__4__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Out_DBx__4__MASK, 0x80 +.set SCSI_Out_DBx__4__PC, CYREG_PRT2_PC7 +.set SCSI_Out_DBx__4__PORT, 2 +.set SCSI_Out_DBx__4__PRT, CYREG_PRT2_PRT +.set SCSI_Out_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Out_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Out_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Out_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Out_DBx__4__PS, CYREG_PRT2_PS +.set SCSI_Out_DBx__4__SHIFT, 7 +.set SCSI_Out_DBx__4__SLW, CYREG_PRT2_SLW +.set SCSI_Out_DBx__5__AG, CYREG_PRT2_AG +.set SCSI_Out_DBx__5__AMUX, CYREG_PRT2_AMUX +.set SCSI_Out_DBx__5__BIE, CYREG_PRT2_BIE +.set SCSI_Out_DBx__5__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Out_DBx__5__BYP, CYREG_PRT2_BYP +.set SCSI_Out_DBx__5__CTL, CYREG_PRT2_CTL +.set SCSI_Out_DBx__5__DM0, CYREG_PRT2_DM0 +.set SCSI_Out_DBx__5__DM1, CYREG_PRT2_DM1 +.set SCSI_Out_DBx__5__DM2, CYREG_PRT2_DM2 +.set SCSI_Out_DBx__5__DR, CYREG_PRT2_DR +.set SCSI_Out_DBx__5__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Out_DBx__5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Out_DBx__5__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Out_DBx__5__MASK, 0x40 +.set SCSI_Out_DBx__5__PC, CYREG_PRT2_PC6 +.set SCSI_Out_DBx__5__PORT, 2 +.set SCSI_Out_DBx__5__PRT, CYREG_PRT2_PRT +.set SCSI_Out_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Out_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Out_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Out_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Out_DBx__5__PS, CYREG_PRT2_PS +.set SCSI_Out_DBx__5__SHIFT, 6 +.set SCSI_Out_DBx__5__SLW, CYREG_PRT2_SLW +.set SCSI_Out_DBx__6__AG, CYREG_PRT2_AG +.set SCSI_Out_DBx__6__AMUX, CYREG_PRT2_AMUX +.set SCSI_Out_DBx__6__BIE, CYREG_PRT2_BIE +.set SCSI_Out_DBx__6__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Out_DBx__6__BYP, CYREG_PRT2_BYP +.set SCSI_Out_DBx__6__CTL, CYREG_PRT2_CTL +.set SCSI_Out_DBx__6__DM0, CYREG_PRT2_DM0 +.set SCSI_Out_DBx__6__DM1, CYREG_PRT2_DM1 +.set SCSI_Out_DBx__6__DM2, CYREG_PRT2_DM2 +.set SCSI_Out_DBx__6__DR, CYREG_PRT2_DR +.set SCSI_Out_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Out_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Out_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Out_DBx__6__MASK, 0x08 +.set SCSI_Out_DBx__6__PC, CYREG_PRT2_PC3 +.set SCSI_Out_DBx__6__PORT, 2 +.set SCSI_Out_DBx__6__PRT, CYREG_PRT2_PRT +.set SCSI_Out_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Out_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Out_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Out_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Out_DBx__6__PS, CYREG_PRT2_PS +.set SCSI_Out_DBx__6__SHIFT, 3 +.set SCSI_Out_DBx__6__SLW, CYREG_PRT2_SLW +.set SCSI_Out_DBx__7__AG, CYREG_PRT2_AG +.set SCSI_Out_DBx__7__AMUX, CYREG_PRT2_AMUX +.set SCSI_Out_DBx__7__BIE, CYREG_PRT2_BIE +.set SCSI_Out_DBx__7__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Out_DBx__7__BYP, CYREG_PRT2_BYP +.set SCSI_Out_DBx__7__CTL, CYREG_PRT2_CTL +.set SCSI_Out_DBx__7__DM0, CYREG_PRT2_DM0 +.set SCSI_Out_DBx__7__DM1, CYREG_PRT2_DM1 +.set SCSI_Out_DBx__7__DM2, CYREG_PRT2_DM2 +.set SCSI_Out_DBx__7__DR, CYREG_PRT2_DR +.set SCSI_Out_DBx__7__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Out_DBx__7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Out_DBx__7__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Out_DBx__7__MASK, 0x04 +.set SCSI_Out_DBx__7__PC, CYREG_PRT2_PC2 +.set SCSI_Out_DBx__7__PORT, 2 +.set SCSI_Out_DBx__7__PRT, CYREG_PRT2_PRT +.set SCSI_Out_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Out_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Out_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Out_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Out_DBx__7__PS, CYREG_PRT2_PS +.set SCSI_Out_DBx__7__SHIFT, 2 +.set SCSI_Out_DBx__7__SLW, CYREG_PRT2_SLW +.set SCSI_Out_DBx__DB0__AG, CYREG_PRT5_AG +.set SCSI_Out_DBx__DB0__AMUX, CYREG_PRT5_AMUX +.set SCSI_Out_DBx__DB0__BIE, CYREG_PRT5_BIE +.set SCSI_Out_DBx__DB0__BIT_MASK, CYREG_PRT5_BIT_MASK +.set SCSI_Out_DBx__DB0__BYP, CYREG_PRT5_BYP +.set SCSI_Out_DBx__DB0__CTL, CYREG_PRT5_CTL +.set SCSI_Out_DBx__DB0__DM0, CYREG_PRT5_DM0 +.set SCSI_Out_DBx__DB0__DM1, CYREG_PRT5_DM1 +.set SCSI_Out_DBx__DB0__DM2, CYREG_PRT5_DM2 +.set SCSI_Out_DBx__DB0__DR, CYREG_PRT5_DR +.set SCSI_Out_DBx__DB0__INP_DIS, CYREG_PRT5_INP_DIS +.set SCSI_Out_DBx__DB0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG +.set SCSI_Out_DBx__DB0__LCD_EN, CYREG_PRT5_LCD_EN +.set SCSI_Out_DBx__DB0__MASK, 0x02 +.set SCSI_Out_DBx__DB0__PC, CYREG_PRT5_PC1 +.set SCSI_Out_DBx__DB0__PORT, 5 +.set SCSI_Out_DBx__DB0__PRT, CYREG_PRT5_PRT +.set SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL +.set SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN +.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 +.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 +.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 +.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 +.set SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT +.set SCSI_Out_DBx__DB0__PS, CYREG_PRT5_PS +.set SCSI_Out_DBx__DB0__SHIFT, 1 +.set SCSI_Out_DBx__DB0__SLW, CYREG_PRT5_SLW +.set SCSI_Out_DBx__DB1__AG, CYREG_PRT5_AG +.set SCSI_Out_DBx__DB1__AMUX, CYREG_PRT5_AMUX +.set SCSI_Out_DBx__DB1__BIE, CYREG_PRT5_BIE +.set SCSI_Out_DBx__DB1__BIT_MASK, CYREG_PRT5_BIT_MASK +.set SCSI_Out_DBx__DB1__BYP, CYREG_PRT5_BYP +.set SCSI_Out_DBx__DB1__CTL, CYREG_PRT5_CTL +.set SCSI_Out_DBx__DB1__DM0, CYREG_PRT5_DM0 +.set SCSI_Out_DBx__DB1__DM1, CYREG_PRT5_DM1 +.set SCSI_Out_DBx__DB1__DM2, CYREG_PRT5_DM2 +.set SCSI_Out_DBx__DB1__DR, CYREG_PRT5_DR +.set SCSI_Out_DBx__DB1__INP_DIS, CYREG_PRT5_INP_DIS +.set SCSI_Out_DBx__DB1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG +.set SCSI_Out_DBx__DB1__LCD_EN, CYREG_PRT5_LCD_EN +.set SCSI_Out_DBx__DB1__MASK, 0x01 +.set SCSI_Out_DBx__DB1__PC, CYREG_PRT5_PC0 +.set SCSI_Out_DBx__DB1__PORT, 5 +.set SCSI_Out_DBx__DB1__PRT, CYREG_PRT5_PRT +.set SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL +.set SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN +.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 +.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 +.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 +.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 +.set SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT +.set SCSI_Out_DBx__DB1__PS, CYREG_PRT5_PS +.set SCSI_Out_DBx__DB1__SHIFT, 0 +.set SCSI_Out_DBx__DB1__SLW, CYREG_PRT5_SLW +.set SCSI_Out_DBx__DB2__AG, CYREG_PRT6_AG +.set SCSI_Out_DBx__DB2__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out_DBx__DB2__BIE, CYREG_PRT6_BIE +.set SCSI_Out_DBx__DB2__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out_DBx__DB2__BYP, CYREG_PRT6_BYP +.set SCSI_Out_DBx__DB2__CTL, CYREG_PRT6_CTL +.set SCSI_Out_DBx__DB2__DM0, CYREG_PRT6_DM0 +.set SCSI_Out_DBx__DB2__DM1, CYREG_PRT6_DM1 +.set SCSI_Out_DBx__DB2__DM2, CYREG_PRT6_DM2 +.set SCSI_Out_DBx__DB2__DR, CYREG_PRT6_DR +.set SCSI_Out_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out_DBx__DB2__MASK, 0x20 +.set SCSI_Out_DBx__DB2__PC, CYREG_PRT6_PC5 +.set SCSI_Out_DBx__DB2__PORT, 6 +.set SCSI_Out_DBx__DB2__PRT, CYREG_PRT6_PRT +.set SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out_DBx__DB2__PS, CYREG_PRT6_PS +.set SCSI_Out_DBx__DB2__SHIFT, 5 +.set SCSI_Out_DBx__DB2__SLW, CYREG_PRT6_SLW +.set SCSI_Out_DBx__DB3__AG, CYREG_PRT6_AG +.set SCSI_Out_DBx__DB3__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out_DBx__DB3__BIE, CYREG_PRT6_BIE +.set SCSI_Out_DBx__DB3__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out_DBx__DB3__BYP, CYREG_PRT6_BYP +.set SCSI_Out_DBx__DB3__CTL, CYREG_PRT6_CTL +.set SCSI_Out_DBx__DB3__DM0, CYREG_PRT6_DM0 +.set SCSI_Out_DBx__DB3__DM1, CYREG_PRT6_DM1 +.set SCSI_Out_DBx__DB3__DM2, CYREG_PRT6_DM2 +.set SCSI_Out_DBx__DB3__DR, CYREG_PRT6_DR +.set SCSI_Out_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out_DBx__DB3__MASK, 0x10 +.set SCSI_Out_DBx__DB3__PC, CYREG_PRT6_PC4 +.set SCSI_Out_DBx__DB3__PORT, 6 +.set SCSI_Out_DBx__DB3__PRT, CYREG_PRT6_PRT +.set SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out_DBx__DB3__PS, CYREG_PRT6_PS +.set SCSI_Out_DBx__DB3__SHIFT, 4 +.set SCSI_Out_DBx__DB3__SLW, CYREG_PRT6_SLW +.set SCSI_Out_DBx__DB4__AG, CYREG_PRT2_AG +.set SCSI_Out_DBx__DB4__AMUX, CYREG_PRT2_AMUX +.set SCSI_Out_DBx__DB4__BIE, CYREG_PRT2_BIE +.set SCSI_Out_DBx__DB4__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Out_DBx__DB4__BYP, CYREG_PRT2_BYP +.set SCSI_Out_DBx__DB4__CTL, CYREG_PRT2_CTL +.set SCSI_Out_DBx__DB4__DM0, CYREG_PRT2_DM0 +.set SCSI_Out_DBx__DB4__DM1, CYREG_PRT2_DM1 +.set SCSI_Out_DBx__DB4__DM2, CYREG_PRT2_DM2 +.set SCSI_Out_DBx__DB4__DR, CYREG_PRT2_DR +.set SCSI_Out_DBx__DB4__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Out_DBx__DB4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Out_DBx__DB4__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Out_DBx__DB4__MASK, 0x80 +.set SCSI_Out_DBx__DB4__PC, CYREG_PRT2_PC7 +.set SCSI_Out_DBx__DB4__PORT, 2 +.set SCSI_Out_DBx__DB4__PRT, CYREG_PRT2_PRT +.set SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Out_DBx__DB4__PS, CYREG_PRT2_PS +.set SCSI_Out_DBx__DB4__SHIFT, 7 +.set SCSI_Out_DBx__DB4__SLW, CYREG_PRT2_SLW +.set SCSI_Out_DBx__DB5__AG, CYREG_PRT2_AG +.set SCSI_Out_DBx__DB5__AMUX, CYREG_PRT2_AMUX +.set SCSI_Out_DBx__DB5__BIE, CYREG_PRT2_BIE +.set SCSI_Out_DBx__DB5__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Out_DBx__DB5__BYP, CYREG_PRT2_BYP +.set SCSI_Out_DBx__DB5__CTL, CYREG_PRT2_CTL +.set SCSI_Out_DBx__DB5__DM0, CYREG_PRT2_DM0 +.set SCSI_Out_DBx__DB5__DM1, CYREG_PRT2_DM1 +.set SCSI_Out_DBx__DB5__DM2, CYREG_PRT2_DM2 +.set SCSI_Out_DBx__DB5__DR, CYREG_PRT2_DR +.set SCSI_Out_DBx__DB5__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Out_DBx__DB5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Out_DBx__DB5__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Out_DBx__DB5__MASK, 0x40 +.set SCSI_Out_DBx__DB5__PC, CYREG_PRT2_PC6 +.set SCSI_Out_DBx__DB5__PORT, 2 +.set SCSI_Out_DBx__DB5__PRT, CYREG_PRT2_PRT +.set SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Out_DBx__DB5__PS, CYREG_PRT2_PS +.set SCSI_Out_DBx__DB5__SHIFT, 6 +.set SCSI_Out_DBx__DB5__SLW, CYREG_PRT2_SLW +.set SCSI_Out_DBx__DB6__AG, CYREG_PRT2_AG +.set SCSI_Out_DBx__DB6__AMUX, CYREG_PRT2_AMUX +.set SCSI_Out_DBx__DB6__BIE, CYREG_PRT2_BIE +.set SCSI_Out_DBx__DB6__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Out_DBx__DB6__BYP, CYREG_PRT2_BYP +.set SCSI_Out_DBx__DB6__CTL, CYREG_PRT2_CTL +.set SCSI_Out_DBx__DB6__DM0, CYREG_PRT2_DM0 +.set SCSI_Out_DBx__DB6__DM1, CYREG_PRT2_DM1 +.set SCSI_Out_DBx__DB6__DM2, CYREG_PRT2_DM2 +.set SCSI_Out_DBx__DB6__DR, CYREG_PRT2_DR +.set SCSI_Out_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Out_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Out_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Out_DBx__DB6__MASK, 0x08 +.set SCSI_Out_DBx__DB6__PC, CYREG_PRT2_PC3 +.set SCSI_Out_DBx__DB6__PORT, 2 +.set SCSI_Out_DBx__DB6__PRT, CYREG_PRT2_PRT +.set SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Out_DBx__DB6__PS, CYREG_PRT2_PS +.set SCSI_Out_DBx__DB6__SHIFT, 3 +.set SCSI_Out_DBx__DB6__SLW, CYREG_PRT2_SLW +.set SCSI_Out_DBx__DB7__AG, CYREG_PRT2_AG +.set SCSI_Out_DBx__DB7__AMUX, CYREG_PRT2_AMUX +.set SCSI_Out_DBx__DB7__BIE, CYREG_PRT2_BIE +.set SCSI_Out_DBx__DB7__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Out_DBx__DB7__BYP, CYREG_PRT2_BYP +.set SCSI_Out_DBx__DB7__CTL, CYREG_PRT2_CTL +.set SCSI_Out_DBx__DB7__DM0, CYREG_PRT2_DM0 +.set SCSI_Out_DBx__DB7__DM1, CYREG_PRT2_DM1 +.set SCSI_Out_DBx__DB7__DM2, CYREG_PRT2_DM2 +.set SCSI_Out_DBx__DB7__DR, CYREG_PRT2_DR +.set SCSI_Out_DBx__DB7__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Out_DBx__DB7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Out_DBx__DB7__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Out_DBx__DB7__MASK, 0x04 +.set SCSI_Out_DBx__DB7__PC, CYREG_PRT2_PC2 +.set SCSI_Out_DBx__DB7__PORT, 2 +.set SCSI_Out_DBx__DB7__PRT, CYREG_PRT2_PRT +.set SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Out_DBx__DB7__PS, CYREG_PRT2_PS +.set SCSI_Out_DBx__DB7__SHIFT, 2 +.set SCSI_Out_DBx__DB7__SLW, CYREG_PRT2_SLW + +/* SCSI_RST_ISR */ +.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SCSI_RST_ISR__INTC_MASK, 0x100 +.set SCSI_RST_ISR__INTC_NUMBER, 8 +.set SCSI_RST_ISR__INTC_PRIOR_NUM, 7 +.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_8 +.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SDCard_BSPIM */ +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST +.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB06_MSK +.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB06_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB06_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB06_ST +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL +.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK +.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK +.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL +.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB06_CTL +.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL +.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB06_CTL +.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL +.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB06_MSK +.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST +.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 +.set SDCard_BSPIM_RxStsReg__4__POS, 4 +.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20 +.set SDCard_BSPIM_RxStsReg__5__POS, 5 +.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40 +.set SDCard_BSPIM_RxStsReg__6__POS, 6 +.set SDCard_BSPIM_RxStsReg__MASK, 0x70 +.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB06_MSK +.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL +.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB06_ST +.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01 +.set SDCard_BSPIM_TxStsReg__0__POS, 0 +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST +.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 +.set SDCard_BSPIM_TxStsReg__1__POS, 1 +.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 +.set SDCard_BSPIM_TxStsReg__2__POS, 2 +.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08 +.set SDCard_BSPIM_TxStsReg__3__POS, 3 +.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 +.set SDCard_BSPIM_TxStsReg__4__POS, 4 +.set SDCard_BSPIM_TxStsReg__MASK, 0x1F +.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB05_MSK +.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL +.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB05_ST +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB06_07_A0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB06_07_A1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB06_07_D0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB06_07_D1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB06_07_F0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB06_07_F1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB06_A0_A1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB06_A0 +.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB06_A1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB06_D0_D1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB06_D0 +.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB06_D1 +.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB06_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB06_F0_F1 +.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB06_F0 +.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB06_F1 + +/* USBFS_dp_int */ +.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_dp_int__INTC_MASK, 0x1000 +.set USBFS_dp_int__INTC_NUMBER, 12 +.set USBFS_dp_int__INTC_PRIOR_NUM, 7 +.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12 +.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SCSI_CTL_IO */ +.set SCSI_CTL_IO_Sync_ctrl_reg__0__MASK, 0x01 +.set SCSI_CTL_IO_Sync_ctrl_reg__0__POS, 0 +.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB15_ACTL +.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB15_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB15_ST_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB15_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB15_ST_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__MASK, 0x01 +.set SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL +.set SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB15_MSK +.set SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL + +/* SCSI_In_DBx */ +.set SCSI_In_DBx__0__AG, CYREG_PRT5_AG +.set SCSI_In_DBx__0__AMUX, CYREG_PRT5_AMUX +.set SCSI_In_DBx__0__BIE, CYREG_PRT5_BIE +.set SCSI_In_DBx__0__BIT_MASK, CYREG_PRT5_BIT_MASK +.set SCSI_In_DBx__0__BYP, CYREG_PRT5_BYP +.set SCSI_In_DBx__0__CTL, CYREG_PRT5_CTL +.set SCSI_In_DBx__0__DM0, CYREG_PRT5_DM0 +.set SCSI_In_DBx__0__DM1, CYREG_PRT5_DM1 +.set SCSI_In_DBx__0__DM2, CYREG_PRT5_DM2 +.set SCSI_In_DBx__0__DR, CYREG_PRT5_DR +.set SCSI_In_DBx__0__INP_DIS, CYREG_PRT5_INP_DIS +.set SCSI_In_DBx__0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG +.set SCSI_In_DBx__0__LCD_EN, CYREG_PRT5_LCD_EN +.set SCSI_In_DBx__0__MASK, 0x08 +.set SCSI_In_DBx__0__PC, CYREG_PRT5_PC3 +.set SCSI_In_DBx__0__PORT, 5 +.set SCSI_In_DBx__0__PRT, CYREG_PRT5_PRT +.set SCSI_In_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL +.set SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN +.set SCSI_In_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 +.set SCSI_In_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 +.set SCSI_In_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 +.set SCSI_In_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 +.set SCSI_In_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT +.set SCSI_In_DBx__0__PS, CYREG_PRT5_PS +.set SCSI_In_DBx__0__SHIFT, 3 +.set SCSI_In_DBx__0__SLW, CYREG_PRT5_SLW +.set SCSI_In_DBx__1__AG, CYREG_PRT5_AG +.set SCSI_In_DBx__1__AMUX, CYREG_PRT5_AMUX +.set SCSI_In_DBx__1__BIE, CYREG_PRT5_BIE +.set SCSI_In_DBx__1__BIT_MASK, CYREG_PRT5_BIT_MASK +.set SCSI_In_DBx__1__BYP, CYREG_PRT5_BYP +.set SCSI_In_DBx__1__CTL, CYREG_PRT5_CTL +.set SCSI_In_DBx__1__DM0, CYREG_PRT5_DM0 +.set SCSI_In_DBx__1__DM1, CYREG_PRT5_DM1 +.set SCSI_In_DBx__1__DM2, CYREG_PRT5_DM2 +.set SCSI_In_DBx__1__DR, CYREG_PRT5_DR +.set SCSI_In_DBx__1__INP_DIS, CYREG_PRT5_INP_DIS +.set SCSI_In_DBx__1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG +.set SCSI_In_DBx__1__LCD_EN, CYREG_PRT5_LCD_EN +.set SCSI_In_DBx__1__MASK, 0x04 +.set SCSI_In_DBx__1__PC, CYREG_PRT5_PC2 +.set SCSI_In_DBx__1__PORT, 5 +.set SCSI_In_DBx__1__PRT, CYREG_PRT5_PRT +.set SCSI_In_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL +.set SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN +.set SCSI_In_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 +.set SCSI_In_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 +.set SCSI_In_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 +.set SCSI_In_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 +.set SCSI_In_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT +.set SCSI_In_DBx__1__PS, CYREG_PRT5_PS +.set SCSI_In_DBx__1__SHIFT, 2 +.set SCSI_In_DBx__1__SLW, CYREG_PRT5_SLW +.set SCSI_In_DBx__2__AG, CYREG_PRT6_AG +.set SCSI_In_DBx__2__AMUX, CYREG_PRT6_AMUX +.set SCSI_In_DBx__2__BIE, CYREG_PRT6_BIE +.set SCSI_In_DBx__2__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_In_DBx__2__BYP, CYREG_PRT6_BYP +.set SCSI_In_DBx__2__CTL, CYREG_PRT6_CTL +.set SCSI_In_DBx__2__DM0, CYREG_PRT6_DM0 +.set SCSI_In_DBx__2__DM1, CYREG_PRT6_DM1 +.set SCSI_In_DBx__2__DM2, CYREG_PRT6_DM2 +.set SCSI_In_DBx__2__DR, CYREG_PRT6_DR +.set SCSI_In_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_In_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_In_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_In_DBx__2__MASK, 0x80 +.set SCSI_In_DBx__2__PC, CYREG_PRT6_PC7 +.set SCSI_In_DBx__2__PORT, 6 +.set SCSI_In_DBx__2__PRT, CYREG_PRT6_PRT +.set SCSI_In_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_In_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_In_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_In_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_In_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_In_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_In_DBx__2__PS, CYREG_PRT6_PS +.set SCSI_In_DBx__2__SHIFT, 7 +.set SCSI_In_DBx__2__SLW, CYREG_PRT6_SLW +.set SCSI_In_DBx__3__AG, CYREG_PRT6_AG +.set SCSI_In_DBx__3__AMUX, CYREG_PRT6_AMUX +.set SCSI_In_DBx__3__BIE, CYREG_PRT6_BIE +.set SCSI_In_DBx__3__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_In_DBx__3__BYP, CYREG_PRT6_BYP +.set SCSI_In_DBx__3__CTL, CYREG_PRT6_CTL +.set SCSI_In_DBx__3__DM0, CYREG_PRT6_DM0 +.set SCSI_In_DBx__3__DM1, CYREG_PRT6_DM1 +.set SCSI_In_DBx__3__DM2, CYREG_PRT6_DM2 +.set SCSI_In_DBx__3__DR, CYREG_PRT6_DR +.set SCSI_In_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_In_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_In_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_In_DBx__3__MASK, 0x40 +.set SCSI_In_DBx__3__PC, CYREG_PRT6_PC6 +.set SCSI_In_DBx__3__PORT, 6 +.set SCSI_In_DBx__3__PRT, CYREG_PRT6_PRT +.set SCSI_In_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_In_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_In_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_In_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_In_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_In_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_In_DBx__3__PS, CYREG_PRT6_PS +.set SCSI_In_DBx__3__SHIFT, 6 +.set SCSI_In_DBx__3__SLW, CYREG_PRT6_SLW +.set SCSI_In_DBx__4__AG, CYREG_PRT12_AG +.set SCSI_In_DBx__4__BIE, CYREG_PRT12_BIE +.set SCSI_In_DBx__4__BIT_MASK, CYREG_PRT12_BIT_MASK +.set SCSI_In_DBx__4__BYP, CYREG_PRT12_BYP +.set SCSI_In_DBx__4__DM0, CYREG_PRT12_DM0 +.set SCSI_In_DBx__4__DM1, CYREG_PRT12_DM1 +.set SCSI_In_DBx__4__DM2, CYREG_PRT12_DM2 +.set SCSI_In_DBx__4__DR, CYREG_PRT12_DR +.set SCSI_In_DBx__4__INP_DIS, CYREG_PRT12_INP_DIS +.set SCSI_In_DBx__4__MASK, 0x20 +.set SCSI_In_DBx__4__PC, CYREG_PRT12_PC5 +.set SCSI_In_DBx__4__PORT, 12 +.set SCSI_In_DBx__4__PRT, CYREG_PRT12_PRT +.set SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN +.set SCSI_In_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0 +.set SCSI_In_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1 +.set SCSI_In_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0 +.set SCSI_In_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1 +.set SCSI_In_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT +.set SCSI_In_DBx__4__PS, CYREG_PRT12_PS +.set SCSI_In_DBx__4__SHIFT, 5 +.set SCSI_In_DBx__4__SIO_CFG, CYREG_PRT12_SIO_CFG +.set SCSI_In_DBx__4__SIO_DIFF, CYREG_PRT12_SIO_DIFF +.set SCSI_In_DBx__4__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN +.set SCSI_In_DBx__4__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ +.set SCSI_In_DBx__4__SLW, CYREG_PRT12_SLW +.set SCSI_In_DBx__5__AG, CYREG_PRT12_AG +.set SCSI_In_DBx__5__BIE, CYREG_PRT12_BIE +.set SCSI_In_DBx__5__BIT_MASK, CYREG_PRT12_BIT_MASK +.set SCSI_In_DBx__5__BYP, CYREG_PRT12_BYP +.set SCSI_In_DBx__5__DM0, CYREG_PRT12_DM0 +.set SCSI_In_DBx__5__DM1, CYREG_PRT12_DM1 +.set SCSI_In_DBx__5__DM2, CYREG_PRT12_DM2 +.set SCSI_In_DBx__5__DR, CYREG_PRT12_DR +.set SCSI_In_DBx__5__INP_DIS, CYREG_PRT12_INP_DIS +.set SCSI_In_DBx__5__MASK, 0x10 +.set SCSI_In_DBx__5__PC, CYREG_PRT12_PC4 +.set SCSI_In_DBx__5__PORT, 12 +.set SCSI_In_DBx__5__PRT, CYREG_PRT12_PRT +.set SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN +.set SCSI_In_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0 +.set SCSI_In_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1 +.set SCSI_In_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0 +.set SCSI_In_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1 +.set SCSI_In_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT +.set SCSI_In_DBx__5__PS, CYREG_PRT12_PS +.set SCSI_In_DBx__5__SHIFT, 4 +.set SCSI_In_DBx__5__SIO_CFG, CYREG_PRT12_SIO_CFG +.set SCSI_In_DBx__5__SIO_DIFF, CYREG_PRT12_SIO_DIFF +.set SCSI_In_DBx__5__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN +.set SCSI_In_DBx__5__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ +.set SCSI_In_DBx__5__SLW, CYREG_PRT12_SLW +.set SCSI_In_DBx__6__AG, CYREG_PRT2_AG +.set SCSI_In_DBx__6__AMUX, CYREG_PRT2_AMUX +.set SCSI_In_DBx__6__BIE, CYREG_PRT2_BIE +.set SCSI_In_DBx__6__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_In_DBx__6__BYP, CYREG_PRT2_BYP +.set SCSI_In_DBx__6__CTL, CYREG_PRT2_CTL +.set SCSI_In_DBx__6__DM0, CYREG_PRT2_DM0 +.set SCSI_In_DBx__6__DM1, CYREG_PRT2_DM1 +.set SCSI_In_DBx__6__DM2, CYREG_PRT2_DM2 +.set SCSI_In_DBx__6__DR, CYREG_PRT2_DR +.set SCSI_In_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_In_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_In_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_In_DBx__6__MASK, 0x20 +.set SCSI_In_DBx__6__PC, CYREG_PRT2_PC5 +.set SCSI_In_DBx__6__PORT, 2 +.set SCSI_In_DBx__6__PRT, CYREG_PRT2_PRT +.set SCSI_In_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_In_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_In_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_In_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_In_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_In_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_In_DBx__6__PS, CYREG_PRT2_PS +.set SCSI_In_DBx__6__SHIFT, 5 +.set SCSI_In_DBx__6__SLW, CYREG_PRT2_SLW +.set SCSI_In_DBx__7__AG, CYREG_PRT2_AG +.set SCSI_In_DBx__7__AMUX, CYREG_PRT2_AMUX +.set SCSI_In_DBx__7__BIE, CYREG_PRT2_BIE +.set SCSI_In_DBx__7__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_In_DBx__7__BYP, CYREG_PRT2_BYP +.set SCSI_In_DBx__7__CTL, CYREG_PRT2_CTL +.set SCSI_In_DBx__7__DM0, CYREG_PRT2_DM0 +.set SCSI_In_DBx__7__DM1, CYREG_PRT2_DM1 +.set SCSI_In_DBx__7__DM2, CYREG_PRT2_DM2 +.set SCSI_In_DBx__7__DR, CYREG_PRT2_DR +.set SCSI_In_DBx__7__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_In_DBx__7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_In_DBx__7__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_In_DBx__7__MASK, 0x10 +.set SCSI_In_DBx__7__PC, CYREG_PRT2_PC4 +.set SCSI_In_DBx__7__PORT, 2 +.set SCSI_In_DBx__7__PRT, CYREG_PRT2_PRT +.set SCSI_In_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_In_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_In_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_In_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_In_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_In_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_In_DBx__7__PS, CYREG_PRT2_PS +.set SCSI_In_DBx__7__SHIFT, 4 +.set SCSI_In_DBx__7__SLW, CYREG_PRT2_SLW +.set SCSI_In_DBx__DB0__AG, CYREG_PRT5_AG +.set SCSI_In_DBx__DB0__AMUX, CYREG_PRT5_AMUX +.set SCSI_In_DBx__DB0__BIE, CYREG_PRT5_BIE +.set SCSI_In_DBx__DB0__BIT_MASK, CYREG_PRT5_BIT_MASK +.set SCSI_In_DBx__DB0__BYP, CYREG_PRT5_BYP +.set SCSI_In_DBx__DB0__CTL, CYREG_PRT5_CTL +.set SCSI_In_DBx__DB0__DM0, CYREG_PRT5_DM0 +.set SCSI_In_DBx__DB0__DM1, CYREG_PRT5_DM1 +.set SCSI_In_DBx__DB0__DM2, CYREG_PRT5_DM2 +.set SCSI_In_DBx__DB0__DR, CYREG_PRT5_DR +.set SCSI_In_DBx__DB0__INP_DIS, CYREG_PRT5_INP_DIS +.set SCSI_In_DBx__DB0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG +.set SCSI_In_DBx__DB0__LCD_EN, CYREG_PRT5_LCD_EN +.set SCSI_In_DBx__DB0__MASK, 0x08 +.set SCSI_In_DBx__DB0__PC, CYREG_PRT5_PC3 +.set SCSI_In_DBx__DB0__PORT, 5 +.set SCSI_In_DBx__DB0__PRT, CYREG_PRT5_PRT +.set SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL +.set SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN +.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 +.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 +.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 +.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 +.set SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT +.set SCSI_In_DBx__DB0__PS, CYREG_PRT5_PS +.set SCSI_In_DBx__DB0__SHIFT, 3 +.set SCSI_In_DBx__DB0__SLW, CYREG_PRT5_SLW +.set SCSI_In_DBx__DB1__AG, CYREG_PRT5_AG +.set SCSI_In_DBx__DB1__AMUX, CYREG_PRT5_AMUX +.set SCSI_In_DBx__DB1__BIE, CYREG_PRT5_BIE +.set SCSI_In_DBx__DB1__BIT_MASK, CYREG_PRT5_BIT_MASK +.set SCSI_In_DBx__DB1__BYP, CYREG_PRT5_BYP +.set SCSI_In_DBx__DB1__CTL, CYREG_PRT5_CTL +.set SCSI_In_DBx__DB1__DM0, CYREG_PRT5_DM0 +.set SCSI_In_DBx__DB1__DM1, CYREG_PRT5_DM1 +.set SCSI_In_DBx__DB1__DM2, CYREG_PRT5_DM2 +.set SCSI_In_DBx__DB1__DR, CYREG_PRT5_DR +.set SCSI_In_DBx__DB1__INP_DIS, CYREG_PRT5_INP_DIS +.set SCSI_In_DBx__DB1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG +.set SCSI_In_DBx__DB1__LCD_EN, CYREG_PRT5_LCD_EN +.set SCSI_In_DBx__DB1__MASK, 0x04 +.set SCSI_In_DBx__DB1__PC, CYREG_PRT5_PC2 +.set SCSI_In_DBx__DB1__PORT, 5 +.set SCSI_In_DBx__DB1__PRT, CYREG_PRT5_PRT +.set SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL +.set SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN +.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 +.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 +.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 +.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 +.set SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT +.set SCSI_In_DBx__DB1__PS, CYREG_PRT5_PS +.set SCSI_In_DBx__DB1__SHIFT, 2 +.set SCSI_In_DBx__DB1__SLW, CYREG_PRT5_SLW +.set SCSI_In_DBx__DB2__AG, CYREG_PRT6_AG +.set SCSI_In_DBx__DB2__AMUX, CYREG_PRT6_AMUX +.set SCSI_In_DBx__DB2__BIE, CYREG_PRT6_BIE +.set SCSI_In_DBx__DB2__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_In_DBx__DB2__BYP, CYREG_PRT6_BYP +.set SCSI_In_DBx__DB2__CTL, CYREG_PRT6_CTL +.set SCSI_In_DBx__DB2__DM0, CYREG_PRT6_DM0 +.set SCSI_In_DBx__DB2__DM1, CYREG_PRT6_DM1 +.set SCSI_In_DBx__DB2__DM2, CYREG_PRT6_DM2 +.set SCSI_In_DBx__DB2__DR, CYREG_PRT6_DR +.set SCSI_In_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_In_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_In_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_In_DBx__DB2__MASK, 0x80 +.set SCSI_In_DBx__DB2__PC, CYREG_PRT6_PC7 +.set SCSI_In_DBx__DB2__PORT, 6 +.set SCSI_In_DBx__DB2__PRT, CYREG_PRT6_PRT +.set SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_In_DBx__DB2__PS, CYREG_PRT6_PS +.set SCSI_In_DBx__DB2__SHIFT, 7 +.set SCSI_In_DBx__DB2__SLW, CYREG_PRT6_SLW +.set SCSI_In_DBx__DB3__AG, CYREG_PRT6_AG +.set SCSI_In_DBx__DB3__AMUX, CYREG_PRT6_AMUX +.set SCSI_In_DBx__DB3__BIE, CYREG_PRT6_BIE +.set SCSI_In_DBx__DB3__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_In_DBx__DB3__BYP, CYREG_PRT6_BYP +.set SCSI_In_DBx__DB3__CTL, CYREG_PRT6_CTL +.set SCSI_In_DBx__DB3__DM0, CYREG_PRT6_DM0 +.set SCSI_In_DBx__DB3__DM1, CYREG_PRT6_DM1 +.set SCSI_In_DBx__DB3__DM2, CYREG_PRT6_DM2 +.set SCSI_In_DBx__DB3__DR, CYREG_PRT6_DR +.set SCSI_In_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_In_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_In_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_In_DBx__DB3__MASK, 0x40 +.set SCSI_In_DBx__DB3__PC, CYREG_PRT6_PC6 +.set SCSI_In_DBx__DB3__PORT, 6 +.set SCSI_In_DBx__DB3__PRT, CYREG_PRT6_PRT +.set SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_In_DBx__DB3__PS, CYREG_PRT6_PS +.set SCSI_In_DBx__DB3__SHIFT, 6 +.set SCSI_In_DBx__DB3__SLW, CYREG_PRT6_SLW +.set SCSI_In_DBx__DB4__AG, CYREG_PRT12_AG +.set SCSI_In_DBx__DB4__BIE, CYREG_PRT12_BIE +.set SCSI_In_DBx__DB4__BIT_MASK, CYREG_PRT12_BIT_MASK +.set SCSI_In_DBx__DB4__BYP, CYREG_PRT12_BYP +.set SCSI_In_DBx__DB4__DM0, CYREG_PRT12_DM0 +.set SCSI_In_DBx__DB4__DM1, CYREG_PRT12_DM1 +.set SCSI_In_DBx__DB4__DM2, CYREG_PRT12_DM2 +.set SCSI_In_DBx__DB4__DR, CYREG_PRT12_DR +.set SCSI_In_DBx__DB4__INP_DIS, CYREG_PRT12_INP_DIS +.set SCSI_In_DBx__DB4__MASK, 0x20 +.set SCSI_In_DBx__DB4__PC, CYREG_PRT12_PC5 +.set SCSI_In_DBx__DB4__PORT, 12 +.set SCSI_In_DBx__DB4__PRT, CYREG_PRT12_PRT +.set SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN +.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0 +.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1 +.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0 +.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1 +.set SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT +.set SCSI_In_DBx__DB4__PS, CYREG_PRT12_PS +.set SCSI_In_DBx__DB4__SHIFT, 5 +.set SCSI_In_DBx__DB4__SIO_CFG, CYREG_PRT12_SIO_CFG +.set SCSI_In_DBx__DB4__SIO_DIFF, CYREG_PRT12_SIO_DIFF +.set SCSI_In_DBx__DB4__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN +.set SCSI_In_DBx__DB4__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ +.set SCSI_In_DBx__DB4__SLW, CYREG_PRT12_SLW +.set SCSI_In_DBx__DB5__AG, CYREG_PRT12_AG +.set SCSI_In_DBx__DB5__BIE, CYREG_PRT12_BIE +.set SCSI_In_DBx__DB5__BIT_MASK, CYREG_PRT12_BIT_MASK +.set SCSI_In_DBx__DB5__BYP, CYREG_PRT12_BYP +.set SCSI_In_DBx__DB5__DM0, CYREG_PRT12_DM0 +.set SCSI_In_DBx__DB5__DM1, CYREG_PRT12_DM1 +.set SCSI_In_DBx__DB5__DM2, CYREG_PRT12_DM2 +.set SCSI_In_DBx__DB5__DR, CYREG_PRT12_DR +.set SCSI_In_DBx__DB5__INP_DIS, CYREG_PRT12_INP_DIS +.set SCSI_In_DBx__DB5__MASK, 0x10 +.set SCSI_In_DBx__DB5__PC, CYREG_PRT12_PC4 +.set SCSI_In_DBx__DB5__PORT, 12 +.set SCSI_In_DBx__DB5__PRT, CYREG_PRT12_PRT +.set SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN +.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0 +.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1 +.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0 +.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1 +.set SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT +.set SCSI_In_DBx__DB5__PS, CYREG_PRT12_PS +.set SCSI_In_DBx__DB5__SHIFT, 4 +.set SCSI_In_DBx__DB5__SIO_CFG, CYREG_PRT12_SIO_CFG +.set SCSI_In_DBx__DB5__SIO_DIFF, CYREG_PRT12_SIO_DIFF +.set SCSI_In_DBx__DB5__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN +.set SCSI_In_DBx__DB5__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ +.set SCSI_In_DBx__DB5__SLW, CYREG_PRT12_SLW +.set SCSI_In_DBx__DB6__AG, CYREG_PRT2_AG +.set SCSI_In_DBx__DB6__AMUX, CYREG_PRT2_AMUX +.set SCSI_In_DBx__DB6__BIE, CYREG_PRT2_BIE +.set SCSI_In_DBx__DB6__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_In_DBx__DB6__BYP, CYREG_PRT2_BYP +.set SCSI_In_DBx__DB6__CTL, CYREG_PRT2_CTL +.set SCSI_In_DBx__DB6__DM0, CYREG_PRT2_DM0 +.set SCSI_In_DBx__DB6__DM1, CYREG_PRT2_DM1 +.set SCSI_In_DBx__DB6__DM2, CYREG_PRT2_DM2 +.set SCSI_In_DBx__DB6__DR, CYREG_PRT2_DR +.set SCSI_In_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_In_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_In_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_In_DBx__DB6__MASK, 0x20 +.set SCSI_In_DBx__DB6__PC, CYREG_PRT2_PC5 +.set SCSI_In_DBx__DB6__PORT, 2 +.set SCSI_In_DBx__DB6__PRT, CYREG_PRT2_PRT +.set SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_In_DBx__DB6__PS, CYREG_PRT2_PS +.set SCSI_In_DBx__DB6__SHIFT, 5 +.set SCSI_In_DBx__DB6__SLW, CYREG_PRT2_SLW +.set SCSI_In_DBx__DB7__AG, CYREG_PRT2_AG +.set SCSI_In_DBx__DB7__AMUX, CYREG_PRT2_AMUX +.set SCSI_In_DBx__DB7__BIE, CYREG_PRT2_BIE +.set SCSI_In_DBx__DB7__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_In_DBx__DB7__BYP, CYREG_PRT2_BYP +.set SCSI_In_DBx__DB7__CTL, CYREG_PRT2_CTL +.set SCSI_In_DBx__DB7__DM0, CYREG_PRT2_DM0 +.set SCSI_In_DBx__DB7__DM1, CYREG_PRT2_DM1 +.set SCSI_In_DBx__DB7__DM2, CYREG_PRT2_DM2 +.set SCSI_In_DBx__DB7__DR, CYREG_PRT2_DR +.set SCSI_In_DBx__DB7__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_In_DBx__DB7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_In_DBx__DB7__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_In_DBx__DB7__MASK, 0x10 +.set SCSI_In_DBx__DB7__PC, CYREG_PRT2_PC4 +.set SCSI_In_DBx__DB7__PORT, 2 +.set SCSI_In_DBx__DB7__PRT, CYREG_PRT2_PRT +.set SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_In_DBx__DB7__PS, CYREG_PRT2_PS +.set SCSI_In_DBx__DB7__SHIFT, 4 +.set SCSI_In_DBx__DB7__SLW, CYREG_PRT2_SLW + +/* SD_Data_Clk */ +.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0 +.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1 +.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG0_CFG2 +.set SD_Data_Clk__CFG2_SRC_SEL_MASK, 0x07 +.set SD_Data_Clk__INDEX, 0x00 +.set SD_Data_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2 +.set SD_Data_Clk__PM_ACT_MSK, 0x01 +.set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2 +.set SD_Data_Clk__PM_STBY_MSK, 0x01 + +/* SD_Init_Clk */ +.set SD_Init_Clk__CFG0, CYREG_CLKDIST_DCFG1_CFG0 +.set SD_Init_Clk__CFG1, CYREG_CLKDIST_DCFG1_CFG1 +.set SD_Init_Clk__CFG2, CYREG_CLKDIST_DCFG1_CFG2 +.set SD_Init_Clk__CFG2_SRC_SEL_MASK, 0x07 +.set SD_Init_Clk__INDEX, 0x01 +.set SD_Init_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2 +.set SD_Init_Clk__PM_ACT_MSK, 0x02 +.set SD_Init_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2 +.set SD_Init_Clk__PM_STBY_MSK, 0x02 + +/* scsiTarget */ +.set scsiTarget_StatusReg__0__MASK, 0x01 +.set scsiTarget_StatusReg__0__POS, 0 +.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL +.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB13_14_ST +.set scsiTarget_StatusReg__1__MASK, 0x02 +.set scsiTarget_StatusReg__1__POS, 1 +.set scsiTarget_StatusReg__2__MASK, 0x04 +.set scsiTarget_StatusReg__2__POS, 2 +.set scsiTarget_StatusReg__3__MASK, 0x08 +.set scsiTarget_StatusReg__3__POS, 3 +.set scsiTarget_StatusReg__MASK, 0x0F +.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB13_MSK +.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB13_ACTL +.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB13_ST +.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL +.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB10_11_ST +.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB10_MSK +.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL +.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL +.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB10_ACTL +.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB10_ST_CTL +.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB10_ST_CTL +.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB10_ST +.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL +.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL +.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL +.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL +.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL +.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK +.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK +.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK +.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK +.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL +.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB10_CTL +.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL +.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB10_CTL +.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL +.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL +.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB10_MSK +.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL +.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB10_11_A0 +.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB10_11_A1 +.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB10_11_D0 +.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB10_11_D1 +.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL +.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB10_11_F0 +.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB10_11_F1 +.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB10_A0_A1 +.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB10_A0 +.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB10_A1 +.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB10_D0_D1 +.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB10_D0 +.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB10_D1 +.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB10_ACTL +.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB10_F0_F1 +.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB10_F0 +.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB10_F1 +.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL +.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL + +/* SD_Clk_Ctl */ +.set SD_Clk_Ctl_Sync_ctrl_reg__0__MASK, 0x01 +.set SD_Clk_Ctl_Sync_ctrl_reg__0__POS, 0 +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK +.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL +.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__MASK, 0x01 +.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL +.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK +.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL + +/* USBFS_ep_0 */ +.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_0__INTC_MASK, 0x1000000 +.set USBFS_ep_0__INTC_NUMBER, 24 +.set USBFS_ep_0__INTC_PRIOR_NUM, 7 +.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24 +.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* USBFS_ep_1 */ +.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_1__INTC_MASK, 0x01 +.set USBFS_ep_1__INTC_NUMBER, 0 +.set USBFS_ep_1__INTC_PRIOR_NUM, 7 +.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_0 +.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* USBFS_ep_2 */ +.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_2__INTC_MASK, 0x02 +.set USBFS_ep_2__INTC_NUMBER, 1 +.set USBFS_ep_2__INTC_PRIOR_NUM, 7 +.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_1 +.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* USBFS_USB */ +.set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG +.set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG +.set USBFS_USB__ARB_EP1_INT_EN, CYREG_USB_ARB_EP1_INT_EN +.set USBFS_USB__ARB_EP1_SR, CYREG_USB_ARB_EP1_SR +.set USBFS_USB__ARB_EP2_CFG, CYREG_USB_ARB_EP2_CFG +.set USBFS_USB__ARB_EP2_INT_EN, CYREG_USB_ARB_EP2_INT_EN +.set USBFS_USB__ARB_EP2_SR, CYREG_USB_ARB_EP2_SR +.set USBFS_USB__ARB_EP3_CFG, CYREG_USB_ARB_EP3_CFG +.set USBFS_USB__ARB_EP3_INT_EN, CYREG_USB_ARB_EP3_INT_EN +.set USBFS_USB__ARB_EP3_SR, CYREG_USB_ARB_EP3_SR +.set USBFS_USB__ARB_EP4_CFG, CYREG_USB_ARB_EP4_CFG +.set USBFS_USB__ARB_EP4_INT_EN, CYREG_USB_ARB_EP4_INT_EN +.set USBFS_USB__ARB_EP4_SR, CYREG_USB_ARB_EP4_SR +.set USBFS_USB__ARB_EP5_CFG, CYREG_USB_ARB_EP5_CFG +.set USBFS_USB__ARB_EP5_INT_EN, CYREG_USB_ARB_EP5_INT_EN +.set USBFS_USB__ARB_EP5_SR, CYREG_USB_ARB_EP5_SR +.set USBFS_USB__ARB_EP6_CFG, CYREG_USB_ARB_EP6_CFG +.set USBFS_USB__ARB_EP6_INT_EN, CYREG_USB_ARB_EP6_INT_EN +.set USBFS_USB__ARB_EP6_SR, CYREG_USB_ARB_EP6_SR +.set USBFS_USB__ARB_EP7_CFG, CYREG_USB_ARB_EP7_CFG +.set USBFS_USB__ARB_EP7_INT_EN, CYREG_USB_ARB_EP7_INT_EN +.set USBFS_USB__ARB_EP7_SR, CYREG_USB_ARB_EP7_SR +.set USBFS_USB__ARB_EP8_CFG, CYREG_USB_ARB_EP8_CFG +.set USBFS_USB__ARB_EP8_INT_EN, CYREG_USB_ARB_EP8_INT_EN +.set USBFS_USB__ARB_EP8_SR, CYREG_USB_ARB_EP8_SR +.set USBFS_USB__ARB_INT_EN, CYREG_USB_ARB_INT_EN +.set USBFS_USB__ARB_INT_SR, CYREG_USB_ARB_INT_SR +.set USBFS_USB__ARB_RW1_DR, CYREG_USB_ARB_RW1_DR +.set USBFS_USB__ARB_RW1_RA, CYREG_USB_ARB_RW1_RA +.set USBFS_USB__ARB_RW1_RA_MSB, CYREG_USB_ARB_RW1_RA_MSB +.set USBFS_USB__ARB_RW1_WA, CYREG_USB_ARB_RW1_WA +.set USBFS_USB__ARB_RW1_WA_MSB, CYREG_USB_ARB_RW1_WA_MSB +.set USBFS_USB__ARB_RW2_DR, CYREG_USB_ARB_RW2_DR +.set USBFS_USB__ARB_RW2_RA, CYREG_USB_ARB_RW2_RA +.set USBFS_USB__ARB_RW2_RA_MSB, CYREG_USB_ARB_RW2_RA_MSB +.set USBFS_USB__ARB_RW2_WA, CYREG_USB_ARB_RW2_WA +.set USBFS_USB__ARB_RW2_WA_MSB, CYREG_USB_ARB_RW2_WA_MSB +.set USBFS_USB__ARB_RW3_DR, CYREG_USB_ARB_RW3_DR +.set USBFS_USB__ARB_RW3_RA, CYREG_USB_ARB_RW3_RA +.set USBFS_USB__ARB_RW3_RA_MSB, CYREG_USB_ARB_RW3_RA_MSB +.set USBFS_USB__ARB_RW3_WA, CYREG_USB_ARB_RW3_WA +.set USBFS_USB__ARB_RW3_WA_MSB, CYREG_USB_ARB_RW3_WA_MSB +.set USBFS_USB__ARB_RW4_DR, CYREG_USB_ARB_RW4_DR +.set USBFS_USB__ARB_RW4_RA, CYREG_USB_ARB_RW4_RA +.set USBFS_USB__ARB_RW4_RA_MSB, CYREG_USB_ARB_RW4_RA_MSB +.set USBFS_USB__ARB_RW4_WA, CYREG_USB_ARB_RW4_WA +.set USBFS_USB__ARB_RW4_WA_MSB, CYREG_USB_ARB_RW4_WA_MSB +.set USBFS_USB__ARB_RW5_DR, CYREG_USB_ARB_RW5_DR +.set USBFS_USB__ARB_RW5_RA, CYREG_USB_ARB_RW5_RA +.set USBFS_USB__ARB_RW5_RA_MSB, CYREG_USB_ARB_RW5_RA_MSB +.set USBFS_USB__ARB_RW5_WA, CYREG_USB_ARB_RW5_WA +.set USBFS_USB__ARB_RW5_WA_MSB, CYREG_USB_ARB_RW5_WA_MSB +.set USBFS_USB__ARB_RW6_DR, CYREG_USB_ARB_RW6_DR +.set USBFS_USB__ARB_RW6_RA, CYREG_USB_ARB_RW6_RA +.set USBFS_USB__ARB_RW6_RA_MSB, CYREG_USB_ARB_RW6_RA_MSB +.set USBFS_USB__ARB_RW6_WA, CYREG_USB_ARB_RW6_WA +.set USBFS_USB__ARB_RW6_WA_MSB, CYREG_USB_ARB_RW6_WA_MSB +.set USBFS_USB__ARB_RW7_DR, CYREG_USB_ARB_RW7_DR +.set USBFS_USB__ARB_RW7_RA, CYREG_USB_ARB_RW7_RA +.set USBFS_USB__ARB_RW7_RA_MSB, CYREG_USB_ARB_RW7_RA_MSB +.set USBFS_USB__ARB_RW7_WA, CYREG_USB_ARB_RW7_WA +.set USBFS_USB__ARB_RW7_WA_MSB, CYREG_USB_ARB_RW7_WA_MSB +.set USBFS_USB__ARB_RW8_DR, CYREG_USB_ARB_RW8_DR +.set USBFS_USB__ARB_RW8_RA, CYREG_USB_ARB_RW8_RA +.set USBFS_USB__ARB_RW8_RA_MSB, CYREG_USB_ARB_RW8_RA_MSB +.set USBFS_USB__ARB_RW8_WA, CYREG_USB_ARB_RW8_WA +.set USBFS_USB__ARB_RW8_WA_MSB, CYREG_USB_ARB_RW8_WA_MSB +.set USBFS_USB__BUF_SIZE, CYREG_USB_BUF_SIZE +.set USBFS_USB__BUS_RST_CNT, CYREG_USB_BUS_RST_CNT +.set USBFS_USB__CR0, CYREG_USB_CR0 +.set USBFS_USB__CR1, CYREG_USB_CR1 +.set USBFS_USB__CWA, CYREG_USB_CWA +.set USBFS_USB__CWA_MSB, CYREG_USB_CWA_MSB +.set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES +.set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB +.set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG +.set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT +.set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR +.set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0 +.set USBFS_USB__EP0_DR1, CYREG_USB_EP0_DR1 +.set USBFS_USB__EP0_DR2, CYREG_USB_EP0_DR2 +.set USBFS_USB__EP0_DR3, CYREG_USB_EP0_DR3 +.set USBFS_USB__EP0_DR4, CYREG_USB_EP0_DR4 +.set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5 +.set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6 +.set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7 +.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE +.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE +.set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE +.set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5 +.set USBFS_USB__PM_ACT_MSK, 0x01 +.set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5 +.set USBFS_USB__PM_STBY_MSK, 0x01 +.set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0 +.set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1 +.set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0 +.set USBFS_USB__SIE_EP2_CNT0, CYREG_USB_SIE_EP2_CNT0 +.set USBFS_USB__SIE_EP2_CNT1, CYREG_USB_SIE_EP2_CNT1 +.set USBFS_USB__SIE_EP2_CR0, CYREG_USB_SIE_EP2_CR0 +.set USBFS_USB__SIE_EP3_CNT0, CYREG_USB_SIE_EP3_CNT0 +.set USBFS_USB__SIE_EP3_CNT1, CYREG_USB_SIE_EP3_CNT1 +.set USBFS_USB__SIE_EP3_CR0, CYREG_USB_SIE_EP3_CR0 +.set USBFS_USB__SIE_EP4_CNT0, CYREG_USB_SIE_EP4_CNT0 +.set USBFS_USB__SIE_EP4_CNT1, CYREG_USB_SIE_EP4_CNT1 +.set USBFS_USB__SIE_EP4_CR0, CYREG_USB_SIE_EP4_CR0 +.set USBFS_USB__SIE_EP5_CNT0, CYREG_USB_SIE_EP5_CNT0 +.set USBFS_USB__SIE_EP5_CNT1, CYREG_USB_SIE_EP5_CNT1 +.set USBFS_USB__SIE_EP5_CR0, CYREG_USB_SIE_EP5_CR0 +.set USBFS_USB__SIE_EP6_CNT0, CYREG_USB_SIE_EP6_CNT0 +.set USBFS_USB__SIE_EP6_CNT1, CYREG_USB_SIE_EP6_CNT1 +.set USBFS_USB__SIE_EP6_CR0, CYREG_USB_SIE_EP6_CR0 +.set USBFS_USB__SIE_EP7_CNT0, CYREG_USB_SIE_EP7_CNT0 +.set USBFS_USB__SIE_EP7_CNT1, CYREG_USB_SIE_EP7_CNT1 +.set USBFS_USB__SIE_EP7_CR0, CYREG_USB_SIE_EP7_CR0 +.set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0 +.set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1 +.set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0 +.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN +.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR +.set USBFS_USB__SOF0, CYREG_USB_SOF0 +.set USBFS_USB__SOF1, CYREG_USB_SOF1 +.set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0 +.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1 +.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN + +/* SCSI_ATN */ +.set SCSI_ATN__0__MASK, 0x01 +.set SCSI_ATN__0__PC, CYREG_PRT2_PC0 +.set SCSI_ATN__0__PORT, 2 +.set SCSI_ATN__0__SHIFT, 0 +.set SCSI_ATN__AG, CYREG_PRT2_AG +.set SCSI_ATN__AMUX, CYREG_PRT2_AMUX +.set SCSI_ATN__BIE, CYREG_PRT2_BIE +.set SCSI_ATN__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_ATN__BYP, CYREG_PRT2_BYP +.set SCSI_ATN__CTL, CYREG_PRT2_CTL +.set SCSI_ATN__DM0, CYREG_PRT2_DM0 +.set SCSI_ATN__DM1, CYREG_PRT2_DM1 +.set SCSI_ATN__DM2, CYREG_PRT2_DM2 +.set SCSI_ATN__DR, CYREG_PRT2_DR +.set SCSI_ATN__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_ATN__INT__MASK, 0x01 +.set SCSI_ATN__INT__PC, CYREG_PRT2_PC0 +.set SCSI_ATN__INT__PORT, 2 +.set SCSI_ATN__INT__SHIFT, 0 +.set SCSI_ATN__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_ATN__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_ATN__MASK, 0x01 +.set SCSI_ATN__PORT, 2 +.set SCSI_ATN__PRT, CYREG_PRT2_PRT +.set SCSI_ATN__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_ATN__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_ATN__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_ATN__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_ATN__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_ATN__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_ATN__PS, CYREG_PRT2_PS +.set SCSI_ATN__SHIFT, 0 +.set SCSI_ATN__SLW, CYREG_PRT2_SLW + +/* SCSI_Out */ +.set SCSI_Out__0__AG, CYREG_PRT15_AG +.set SCSI_Out__0__AMUX, CYREG_PRT15_AMUX +.set SCSI_Out__0__BIE, CYREG_PRT15_BIE +.set SCSI_Out__0__BIT_MASK, CYREG_PRT15_BIT_MASK +.set SCSI_Out__0__BYP, CYREG_PRT15_BYP +.set SCSI_Out__0__CTL, CYREG_PRT15_CTL +.set SCSI_Out__0__DM0, CYREG_PRT15_DM0 +.set SCSI_Out__0__DM1, CYREG_PRT15_DM1 +.set SCSI_Out__0__DM2, CYREG_PRT15_DM2 +.set SCSI_Out__0__DR, CYREG_PRT15_DR +.set SCSI_Out__0__INP_DIS, CYREG_PRT15_INP_DIS +.set SCSI_Out__0__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG +.set SCSI_Out__0__LCD_EN, CYREG_PRT15_LCD_EN +.set SCSI_Out__0__MASK, 0x20 +.set SCSI_Out__0__PC, CYREG_IO_PC_PRT15_PC5 +.set SCSI_Out__0__PORT, 15 +.set SCSI_Out__0__PRT, CYREG_PRT15_PRT +.set SCSI_Out__0__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL +.set SCSI_Out__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN +.set SCSI_Out__0__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 +.set SCSI_Out__0__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 +.set SCSI_Out__0__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 +.set SCSI_Out__0__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 +.set SCSI_Out__0__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT +.set SCSI_Out__0__PS, CYREG_PRT15_PS +.set SCSI_Out__0__SHIFT, 5 +.set SCSI_Out__0__SLW, CYREG_PRT15_SLW +.set SCSI_Out__1__AG, CYREG_PRT15_AG +.set SCSI_Out__1__AMUX, CYREG_PRT15_AMUX +.set SCSI_Out__1__BIE, CYREG_PRT15_BIE +.set SCSI_Out__1__BIT_MASK, CYREG_PRT15_BIT_MASK +.set SCSI_Out__1__BYP, CYREG_PRT15_BYP +.set SCSI_Out__1__CTL, CYREG_PRT15_CTL +.set SCSI_Out__1__DM0, CYREG_PRT15_DM0 +.set SCSI_Out__1__DM1, CYREG_PRT15_DM1 +.set SCSI_Out__1__DM2, CYREG_PRT15_DM2 +.set SCSI_Out__1__DR, CYREG_PRT15_DR +.set SCSI_Out__1__INP_DIS, CYREG_PRT15_INP_DIS +.set SCSI_Out__1__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG +.set SCSI_Out__1__LCD_EN, CYREG_PRT15_LCD_EN +.set SCSI_Out__1__MASK, 0x10 +.set SCSI_Out__1__PC, CYREG_IO_PC_PRT15_PC4 +.set SCSI_Out__1__PORT, 15 +.set SCSI_Out__1__PRT, CYREG_PRT15_PRT +.set SCSI_Out__1__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL +.set SCSI_Out__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN +.set SCSI_Out__1__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 +.set SCSI_Out__1__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 +.set SCSI_Out__1__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 +.set SCSI_Out__1__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 +.set SCSI_Out__1__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT +.set SCSI_Out__1__PS, CYREG_PRT15_PS +.set SCSI_Out__1__SHIFT, 4 +.set SCSI_Out__1__SLW, CYREG_PRT15_SLW +.set SCSI_Out__2__AG, CYREG_PRT6_AG +.set SCSI_Out__2__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out__2__BIE, CYREG_PRT6_BIE +.set SCSI_Out__2__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out__2__BYP, CYREG_PRT6_BYP +.set SCSI_Out__2__CTL, CYREG_PRT6_CTL +.set SCSI_Out__2__DM0, CYREG_PRT6_DM0 +.set SCSI_Out__2__DM1, CYREG_PRT6_DM1 +.set SCSI_Out__2__DM2, CYREG_PRT6_DM2 +.set SCSI_Out__2__DR, CYREG_PRT6_DR +.set SCSI_Out__2__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out__2__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out__2__MASK, 0x02 +.set SCSI_Out__2__PC, CYREG_PRT6_PC1 +.set SCSI_Out__2__PORT, 6 +.set SCSI_Out__2__PRT, CYREG_PRT6_PRT +.set SCSI_Out__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out__2__PS, CYREG_PRT6_PS +.set SCSI_Out__2__SHIFT, 1 +.set SCSI_Out__2__SLW, CYREG_PRT6_SLW +.set SCSI_Out__3__AG, CYREG_PRT6_AG +.set SCSI_Out__3__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out__3__BIE, CYREG_PRT6_BIE +.set SCSI_Out__3__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out__3__BYP, CYREG_PRT6_BYP +.set SCSI_Out__3__CTL, CYREG_PRT6_CTL +.set SCSI_Out__3__DM0, CYREG_PRT6_DM0 +.set SCSI_Out__3__DM1, CYREG_PRT6_DM1 +.set SCSI_Out__3__DM2, CYREG_PRT6_DM2 +.set SCSI_Out__3__DR, CYREG_PRT6_DR +.set SCSI_Out__3__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out__3__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out__3__MASK, 0x01 +.set SCSI_Out__3__PC, CYREG_PRT6_PC0 +.set SCSI_Out__3__PORT, 6 +.set SCSI_Out__3__PRT, CYREG_PRT6_PRT +.set SCSI_Out__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out__3__PS, CYREG_PRT6_PS +.set SCSI_Out__3__SHIFT, 0 +.set SCSI_Out__3__SLW, CYREG_PRT6_SLW +.set SCSI_Out__4__AG, CYREG_PRT4_AG +.set SCSI_Out__4__AMUX, CYREG_PRT4_AMUX +.set SCSI_Out__4__BIE, CYREG_PRT4_BIE +.set SCSI_Out__4__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Out__4__BYP, CYREG_PRT4_BYP +.set SCSI_Out__4__CTL, CYREG_PRT4_CTL +.set SCSI_Out__4__DM0, CYREG_PRT4_DM0 +.set SCSI_Out__4__DM1, CYREG_PRT4_DM1 +.set SCSI_Out__4__DM2, CYREG_PRT4_DM2 +.set SCSI_Out__4__DR, CYREG_PRT4_DR +.set SCSI_Out__4__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Out__4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Out__4__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Out__4__MASK, 0x20 +.set SCSI_Out__4__PC, CYREG_PRT4_PC5 +.set SCSI_Out__4__PORT, 4 +.set SCSI_Out__4__PRT, CYREG_PRT4_PRT +.set SCSI_Out__4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Out__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Out__4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Out__4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Out__4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Out__4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Out__4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Out__4__PS, CYREG_PRT4_PS +.set SCSI_Out__4__SHIFT, 5 +.set SCSI_Out__4__SLW, CYREG_PRT4_SLW +.set SCSI_Out__5__AG, CYREG_PRT4_AG +.set SCSI_Out__5__AMUX, CYREG_PRT4_AMUX +.set SCSI_Out__5__BIE, CYREG_PRT4_BIE +.set SCSI_Out__5__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Out__5__BYP, CYREG_PRT4_BYP +.set SCSI_Out__5__CTL, CYREG_PRT4_CTL +.set SCSI_Out__5__DM0, CYREG_PRT4_DM0 +.set SCSI_Out__5__DM1, CYREG_PRT4_DM1 +.set SCSI_Out__5__DM2, CYREG_PRT4_DM2 +.set SCSI_Out__5__DR, CYREG_PRT4_DR +.set SCSI_Out__5__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Out__5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Out__5__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Out__5__MASK, 0x10 +.set SCSI_Out__5__PC, CYREG_PRT4_PC4 +.set SCSI_Out__5__PORT, 4 +.set SCSI_Out__5__PRT, CYREG_PRT4_PRT +.set SCSI_Out__5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Out__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Out__5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Out__5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Out__5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Out__5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Out__5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Out__5__PS, CYREG_PRT4_PS +.set SCSI_Out__5__SHIFT, 4 +.set SCSI_Out__5__SLW, CYREG_PRT4_SLW +.set SCSI_Out__6__AG, CYREG_PRT0_AG +.set SCSI_Out__6__AMUX, CYREG_PRT0_AMUX +.set SCSI_Out__6__BIE, CYREG_PRT0_BIE +.set SCSI_Out__6__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Out__6__BYP, CYREG_PRT0_BYP +.set SCSI_Out__6__CTL, CYREG_PRT0_CTL +.set SCSI_Out__6__DM0, CYREG_PRT0_DM0 +.set SCSI_Out__6__DM1, CYREG_PRT0_DM1 +.set SCSI_Out__6__DM2, CYREG_PRT0_DM2 +.set SCSI_Out__6__DR, CYREG_PRT0_DR +.set SCSI_Out__6__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Out__6__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Out__6__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Out__6__MASK, 0x80 +.set SCSI_Out__6__PC, CYREG_PRT0_PC7 +.set SCSI_Out__6__PORT, 0 +.set SCSI_Out__6__PRT, CYREG_PRT0_PRT +.set SCSI_Out__6__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Out__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Out__6__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Out__6__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Out__6__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Out__6__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Out__6__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Out__6__PS, CYREG_PRT0_PS +.set SCSI_Out__6__SHIFT, 7 +.set SCSI_Out__6__SLW, CYREG_PRT0_SLW +.set SCSI_Out__7__AG, CYREG_PRT0_AG +.set SCSI_Out__7__AMUX, CYREG_PRT0_AMUX +.set SCSI_Out__7__BIE, CYREG_PRT0_BIE +.set SCSI_Out__7__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Out__7__BYP, CYREG_PRT0_BYP +.set SCSI_Out__7__CTL, CYREG_PRT0_CTL +.set SCSI_Out__7__DM0, CYREG_PRT0_DM0 +.set SCSI_Out__7__DM1, CYREG_PRT0_DM1 +.set SCSI_Out__7__DM2, CYREG_PRT0_DM2 +.set SCSI_Out__7__DR, CYREG_PRT0_DR +.set SCSI_Out__7__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Out__7__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Out__7__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Out__7__MASK, 0x40 +.set SCSI_Out__7__PC, CYREG_PRT0_PC6 +.set SCSI_Out__7__PORT, 0 +.set SCSI_Out__7__PRT, CYREG_PRT0_PRT +.set SCSI_Out__7__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Out__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Out__7__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Out__7__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Out__7__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Out__7__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Out__7__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Out__7__PS, CYREG_PRT0_PS +.set SCSI_Out__7__SHIFT, 6 +.set SCSI_Out__7__SLW, CYREG_PRT0_SLW +.set SCSI_Out__8__AG, CYREG_PRT0_AG +.set SCSI_Out__8__AMUX, CYREG_PRT0_AMUX +.set SCSI_Out__8__BIE, CYREG_PRT0_BIE +.set SCSI_Out__8__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Out__8__BYP, CYREG_PRT0_BYP +.set SCSI_Out__8__CTL, CYREG_PRT0_CTL +.set SCSI_Out__8__DM0, CYREG_PRT0_DM0 +.set SCSI_Out__8__DM1, CYREG_PRT0_DM1 +.set SCSI_Out__8__DM2, CYREG_PRT0_DM2 +.set SCSI_Out__8__DR, CYREG_PRT0_DR +.set SCSI_Out__8__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Out__8__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Out__8__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Out__8__MASK, 0x08 +.set SCSI_Out__8__PC, CYREG_PRT0_PC3 +.set SCSI_Out__8__PORT, 0 +.set SCSI_Out__8__PRT, CYREG_PRT0_PRT +.set SCSI_Out__8__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Out__8__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Out__8__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Out__8__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Out__8__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Out__8__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Out__8__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Out__8__PS, CYREG_PRT0_PS +.set SCSI_Out__8__SHIFT, 3 +.set SCSI_Out__8__SLW, CYREG_PRT0_SLW +.set SCSI_Out__9__AG, CYREG_PRT0_AG +.set SCSI_Out__9__AMUX, CYREG_PRT0_AMUX +.set SCSI_Out__9__BIE, CYREG_PRT0_BIE +.set SCSI_Out__9__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Out__9__BYP, CYREG_PRT0_BYP +.set SCSI_Out__9__CTL, CYREG_PRT0_CTL +.set SCSI_Out__9__DM0, CYREG_PRT0_DM0 +.set SCSI_Out__9__DM1, CYREG_PRT0_DM1 +.set SCSI_Out__9__DM2, CYREG_PRT0_DM2 +.set SCSI_Out__9__DR, CYREG_PRT0_DR +.set SCSI_Out__9__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Out__9__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Out__9__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Out__9__MASK, 0x04 +.set SCSI_Out__9__PC, CYREG_PRT0_PC2 +.set SCSI_Out__9__PORT, 0 +.set SCSI_Out__9__PRT, CYREG_PRT0_PRT +.set SCSI_Out__9__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Out__9__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Out__9__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Out__9__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Out__9__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Out__9__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Out__9__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Out__9__PS, CYREG_PRT0_PS +.set SCSI_Out__9__SHIFT, 2 +.set SCSI_Out__9__SLW, CYREG_PRT0_SLW +.set SCSI_Out__ACK__AG, CYREG_PRT6_AG +.set SCSI_Out__ACK__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out__ACK__BIE, CYREG_PRT6_BIE +.set SCSI_Out__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out__ACK__BYP, CYREG_PRT6_BYP +.set SCSI_Out__ACK__CTL, CYREG_PRT6_CTL +.set SCSI_Out__ACK__DM0, CYREG_PRT6_DM0 +.set SCSI_Out__ACK__DM1, CYREG_PRT6_DM1 +.set SCSI_Out__ACK__DM2, CYREG_PRT6_DM2 +.set SCSI_Out__ACK__DR, CYREG_PRT6_DR +.set SCSI_Out__ACK__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out__ACK__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out__ACK__MASK, 0x01 +.set SCSI_Out__ACK__PC, CYREG_PRT6_PC0 +.set SCSI_Out__ACK__PORT, 6 +.set SCSI_Out__ACK__PRT, CYREG_PRT6_PRT +.set SCSI_Out__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out__ACK__PS, CYREG_PRT6_PS +.set SCSI_Out__ACK__SHIFT, 0 +.set SCSI_Out__ACK__SLW, CYREG_PRT6_SLW +.set SCSI_Out__ATN__AG, CYREG_PRT15_AG +.set SCSI_Out__ATN__AMUX, CYREG_PRT15_AMUX +.set SCSI_Out__ATN__BIE, CYREG_PRT15_BIE +.set SCSI_Out__ATN__BIT_MASK, CYREG_PRT15_BIT_MASK +.set SCSI_Out__ATN__BYP, CYREG_PRT15_BYP +.set SCSI_Out__ATN__CTL, CYREG_PRT15_CTL +.set SCSI_Out__ATN__DM0, CYREG_PRT15_DM0 +.set SCSI_Out__ATN__DM1, CYREG_PRT15_DM1 +.set SCSI_Out__ATN__DM2, CYREG_PRT15_DM2 +.set SCSI_Out__ATN__DR, CYREG_PRT15_DR +.set SCSI_Out__ATN__INP_DIS, CYREG_PRT15_INP_DIS +.set SCSI_Out__ATN__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG +.set SCSI_Out__ATN__LCD_EN, CYREG_PRT15_LCD_EN +.set SCSI_Out__ATN__MASK, 0x10 +.set SCSI_Out__ATN__PC, CYREG_IO_PC_PRT15_PC4 +.set SCSI_Out__ATN__PORT, 15 +.set SCSI_Out__ATN__PRT, CYREG_PRT15_PRT +.set SCSI_Out__ATN__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL +.set SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN +.set SCSI_Out__ATN__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 +.set SCSI_Out__ATN__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 +.set SCSI_Out__ATN__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 +.set SCSI_Out__ATN__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 +.set SCSI_Out__ATN__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT +.set SCSI_Out__ATN__PS, CYREG_PRT15_PS +.set SCSI_Out__ATN__SHIFT, 4 +.set SCSI_Out__ATN__SLW, CYREG_PRT15_SLW +.set SCSI_Out__BSY__AG, CYREG_PRT6_AG +.set SCSI_Out__BSY__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out__BSY__BIE, CYREG_PRT6_BIE +.set SCSI_Out__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out__BSY__BYP, CYREG_PRT6_BYP +.set SCSI_Out__BSY__CTL, CYREG_PRT6_CTL +.set SCSI_Out__BSY__DM0, CYREG_PRT6_DM0 +.set SCSI_Out__BSY__DM1, CYREG_PRT6_DM1 +.set SCSI_Out__BSY__DM2, CYREG_PRT6_DM2 +.set SCSI_Out__BSY__DR, CYREG_PRT6_DR +.set SCSI_Out__BSY__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out__BSY__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out__BSY__MASK, 0x02 +.set SCSI_Out__BSY__PC, CYREG_PRT6_PC1 +.set SCSI_Out__BSY__PORT, 6 +.set SCSI_Out__BSY__PRT, CYREG_PRT6_PRT +.set SCSI_Out__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out__BSY__PS, CYREG_PRT6_PS +.set SCSI_Out__BSY__SHIFT, 1 +.set SCSI_Out__BSY__SLW, CYREG_PRT6_SLW +.set SCSI_Out__CD__AG, CYREG_PRT0_AG +.set SCSI_Out__CD__AMUX, CYREG_PRT0_AMUX +.set SCSI_Out__CD__BIE, CYREG_PRT0_BIE +.set SCSI_Out__CD__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Out__CD__BYP, CYREG_PRT0_BYP +.set SCSI_Out__CD__CTL, CYREG_PRT0_CTL +.set SCSI_Out__CD__DM0, CYREG_PRT0_DM0 +.set SCSI_Out__CD__DM1, CYREG_PRT0_DM1 +.set SCSI_Out__CD__DM2, CYREG_PRT0_DM2 +.set SCSI_Out__CD__DR, CYREG_PRT0_DR +.set SCSI_Out__CD__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Out__CD__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Out__CD__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Out__CD__MASK, 0x40 +.set SCSI_Out__CD__PC, CYREG_PRT0_PC6 +.set SCSI_Out__CD__PORT, 0 +.set SCSI_Out__CD__PRT, CYREG_PRT0_PRT +.set SCSI_Out__CD__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Out__CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Out__CD__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Out__CD__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Out__CD__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Out__CD__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Out__CD__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Out__CD__PS, CYREG_PRT0_PS +.set SCSI_Out__CD__SHIFT, 6 +.set SCSI_Out__CD__SLW, CYREG_PRT0_SLW +.set SCSI_Out__DBP_raw__AG, CYREG_PRT15_AG +.set SCSI_Out__DBP_raw__AMUX, CYREG_PRT15_AMUX +.set SCSI_Out__DBP_raw__BIE, CYREG_PRT15_BIE +.set SCSI_Out__DBP_raw__BIT_MASK, CYREG_PRT15_BIT_MASK +.set SCSI_Out__DBP_raw__BYP, CYREG_PRT15_BYP +.set SCSI_Out__DBP_raw__CTL, CYREG_PRT15_CTL +.set SCSI_Out__DBP_raw__DM0, CYREG_PRT15_DM0 +.set SCSI_Out__DBP_raw__DM1, CYREG_PRT15_DM1 +.set SCSI_Out__DBP_raw__DM2, CYREG_PRT15_DM2 +.set SCSI_Out__DBP_raw__DR, CYREG_PRT15_DR +.set SCSI_Out__DBP_raw__INP_DIS, CYREG_PRT15_INP_DIS +.set SCSI_Out__DBP_raw__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG +.set SCSI_Out__DBP_raw__LCD_EN, CYREG_PRT15_LCD_EN +.set SCSI_Out__DBP_raw__MASK, 0x20 +.set SCSI_Out__DBP_raw__PC, CYREG_IO_PC_PRT15_PC5 +.set SCSI_Out__DBP_raw__PORT, 15 +.set SCSI_Out__DBP_raw__PRT, CYREG_PRT15_PRT +.set SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL +.set SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN +.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 +.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 +.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 +.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 +.set SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT +.set SCSI_Out__DBP_raw__PS, CYREG_PRT15_PS +.set SCSI_Out__DBP_raw__SHIFT, 5 +.set SCSI_Out__DBP_raw__SLW, CYREG_PRT15_SLW +.set SCSI_Out__IO_raw__AG, CYREG_PRT0_AG +.set SCSI_Out__IO_raw__AMUX, CYREG_PRT0_AMUX +.set SCSI_Out__IO_raw__BIE, CYREG_PRT0_BIE +.set SCSI_Out__IO_raw__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Out__IO_raw__BYP, CYREG_PRT0_BYP +.set SCSI_Out__IO_raw__CTL, CYREG_PRT0_CTL +.set SCSI_Out__IO_raw__DM0, CYREG_PRT0_DM0 +.set SCSI_Out__IO_raw__DM1, CYREG_PRT0_DM1 +.set SCSI_Out__IO_raw__DM2, CYREG_PRT0_DM2 +.set SCSI_Out__IO_raw__DR, CYREG_PRT0_DR +.set SCSI_Out__IO_raw__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Out__IO_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Out__IO_raw__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Out__IO_raw__MASK, 0x04 +.set SCSI_Out__IO_raw__PC, CYREG_PRT0_PC2 +.set SCSI_Out__IO_raw__PORT, 0 +.set SCSI_Out__IO_raw__PRT, CYREG_PRT0_PRT +.set SCSI_Out__IO_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Out__IO_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Out__IO_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Out__IO_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Out__IO_raw__PS, CYREG_PRT0_PS +.set SCSI_Out__IO_raw__SHIFT, 2 +.set SCSI_Out__IO_raw__SLW, CYREG_PRT0_SLW +.set SCSI_Out__MSG__AG, CYREG_PRT4_AG +.set SCSI_Out__MSG__AMUX, CYREG_PRT4_AMUX +.set SCSI_Out__MSG__BIE, CYREG_PRT4_BIE +.set SCSI_Out__MSG__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Out__MSG__BYP, CYREG_PRT4_BYP +.set SCSI_Out__MSG__CTL, CYREG_PRT4_CTL +.set SCSI_Out__MSG__DM0, CYREG_PRT4_DM0 +.set SCSI_Out__MSG__DM1, CYREG_PRT4_DM1 +.set SCSI_Out__MSG__DM2, CYREG_PRT4_DM2 +.set SCSI_Out__MSG__DR, CYREG_PRT4_DR +.set SCSI_Out__MSG__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Out__MSG__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Out__MSG__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Out__MSG__MASK, 0x10 +.set SCSI_Out__MSG__PC, CYREG_PRT4_PC4 +.set SCSI_Out__MSG__PORT, 4 +.set SCSI_Out__MSG__PRT, CYREG_PRT4_PRT +.set SCSI_Out__MSG__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Out__MSG__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Out__MSG__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Out__MSG__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Out__MSG__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Out__MSG__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Out__MSG__PS, CYREG_PRT4_PS +.set SCSI_Out__MSG__SHIFT, 4 +.set SCSI_Out__MSG__SLW, CYREG_PRT4_SLW +.set SCSI_Out__REQ__AG, CYREG_PRT0_AG +.set SCSI_Out__REQ__AMUX, CYREG_PRT0_AMUX +.set SCSI_Out__REQ__BIE, CYREG_PRT0_BIE +.set SCSI_Out__REQ__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Out__REQ__BYP, CYREG_PRT0_BYP +.set SCSI_Out__REQ__CTL, CYREG_PRT0_CTL +.set SCSI_Out__REQ__DM0, CYREG_PRT0_DM0 +.set SCSI_Out__REQ__DM1, CYREG_PRT0_DM1 +.set SCSI_Out__REQ__DM2, CYREG_PRT0_DM2 +.set SCSI_Out__REQ__DR, CYREG_PRT0_DR +.set SCSI_Out__REQ__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Out__REQ__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Out__REQ__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Out__REQ__MASK, 0x08 +.set SCSI_Out__REQ__PC, CYREG_PRT0_PC3 +.set SCSI_Out__REQ__PORT, 0 +.set SCSI_Out__REQ__PRT, CYREG_PRT0_PRT +.set SCSI_Out__REQ__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Out__REQ__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Out__REQ__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Out__REQ__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Out__REQ__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Out__REQ__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Out__REQ__PS, CYREG_PRT0_PS +.set SCSI_Out__REQ__SHIFT, 3 +.set SCSI_Out__REQ__SLW, CYREG_PRT0_SLW +.set SCSI_Out__RST__AG, CYREG_PRT4_AG +.set SCSI_Out__RST__AMUX, CYREG_PRT4_AMUX +.set SCSI_Out__RST__BIE, CYREG_PRT4_BIE +.set SCSI_Out__RST__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Out__RST__BYP, CYREG_PRT4_BYP +.set SCSI_Out__RST__CTL, CYREG_PRT4_CTL +.set SCSI_Out__RST__DM0, CYREG_PRT4_DM0 +.set SCSI_Out__RST__DM1, CYREG_PRT4_DM1 +.set SCSI_Out__RST__DM2, CYREG_PRT4_DM2 +.set SCSI_Out__RST__DR, CYREG_PRT4_DR +.set SCSI_Out__RST__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Out__RST__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Out__RST__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Out__RST__MASK, 0x20 +.set SCSI_Out__RST__PC, CYREG_PRT4_PC5 +.set SCSI_Out__RST__PORT, 4 +.set SCSI_Out__RST__PRT, CYREG_PRT4_PRT +.set SCSI_Out__RST__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Out__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Out__RST__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Out__RST__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Out__RST__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Out__RST__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Out__RST__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Out__RST__PS, CYREG_PRT4_PS +.set SCSI_Out__RST__SHIFT, 5 +.set SCSI_Out__RST__SLW, CYREG_PRT4_SLW +.set SCSI_Out__SEL__AG, CYREG_PRT0_AG +.set SCSI_Out__SEL__AMUX, CYREG_PRT0_AMUX +.set SCSI_Out__SEL__BIE, CYREG_PRT0_BIE +.set SCSI_Out__SEL__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Out__SEL__BYP, CYREG_PRT0_BYP +.set SCSI_Out__SEL__CTL, CYREG_PRT0_CTL +.set SCSI_Out__SEL__DM0, CYREG_PRT0_DM0 +.set SCSI_Out__SEL__DM1, CYREG_PRT0_DM1 +.set SCSI_Out__SEL__DM2, CYREG_PRT0_DM2 +.set SCSI_Out__SEL__DR, CYREG_PRT0_DR +.set SCSI_Out__SEL__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Out__SEL__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Out__SEL__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Out__SEL__MASK, 0x80 +.set SCSI_Out__SEL__PC, CYREG_PRT0_PC7 +.set SCSI_Out__SEL__PORT, 0 +.set SCSI_Out__SEL__PRT, CYREG_PRT0_PRT +.set SCSI_Out__SEL__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Out__SEL__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Out__SEL__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Out__SEL__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Out__SEL__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Out__SEL__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Out__SEL__PS, CYREG_PRT0_PS +.set SCSI_Out__SEL__SHIFT, 7 +.set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW + +/* SCSI_RST */ +.set SCSI_RST__0__MASK, 0x80 +.set SCSI_RST__0__PC, CYREG_PRT4_PC7 +.set SCSI_RST__0__PORT, 4 +.set SCSI_RST__0__SHIFT, 7 +.set SCSI_RST__AG, CYREG_PRT4_AG +.set SCSI_RST__AMUX, CYREG_PRT4_AMUX +.set SCSI_RST__BIE, CYREG_PRT4_BIE +.set SCSI_RST__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_RST__BYP, CYREG_PRT4_BYP +.set SCSI_RST__CTL, CYREG_PRT4_CTL +.set SCSI_RST__DM0, CYREG_PRT4_DM0 +.set SCSI_RST__DM1, CYREG_PRT4_DM1 +.set SCSI_RST__DM2, CYREG_PRT4_DM2 +.set SCSI_RST__DR, CYREG_PRT4_DR +.set SCSI_RST__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_RST__INTSTAT, CYREG_PICU4_INTSTAT +.set SCSI_RST__INT__MASK, 0x80 +.set SCSI_RST__INT__PC, CYREG_PRT4_PC7 +.set SCSI_RST__INT__PORT, 4 +.set SCSI_RST__INT__SHIFT, 7 +.set SCSI_RST__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_RST__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_RST__MASK, 0x80 +.set SCSI_RST__PORT, 4 +.set SCSI_RST__PRT, CYREG_PRT4_PRT +.set SCSI_RST__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_RST__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_RST__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_RST__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_RST__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_RST__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_RST__PS, CYREG_PRT4_PS +.set SCSI_RST__SHIFT, 7 +.set SCSI_RST__SLW, CYREG_PRT4_SLW +.set SCSI_RST__SNAP, CYREG_PICU4_SNAP + +/* USBFS_Dm */ +.set USBFS_Dm__0__MASK, 0x80 +.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1 +.set USBFS_Dm__0__PORT, 15 +.set USBFS_Dm__0__SHIFT, 7 +.set USBFS_Dm__AG, CYREG_PRT15_AG +.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX +.set USBFS_Dm__BIE, CYREG_PRT15_BIE +.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK +.set USBFS_Dm__BYP, CYREG_PRT15_BYP +.set USBFS_Dm__CTL, CYREG_PRT15_CTL +.set USBFS_Dm__DM0, CYREG_PRT15_DM0 +.set USBFS_Dm__DM1, CYREG_PRT15_DM1 +.set USBFS_Dm__DM2, CYREG_PRT15_DM2 +.set USBFS_Dm__DR, CYREG_PRT15_DR +.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS +.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG +.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN +.set USBFS_Dm__MASK, 0x80 +.set USBFS_Dm__PORT, 15 +.set USBFS_Dm__PRT, CYREG_PRT15_PRT +.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL +.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN +.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 +.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 +.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 +.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 +.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT +.set USBFS_Dm__PS, CYREG_PRT15_PS +.set USBFS_Dm__SHIFT, 7 +.set USBFS_Dm__SLW, CYREG_PRT15_SLW + +/* USBFS_Dp */ +.set USBFS_Dp__0__MASK, 0x40 +.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0 +.set USBFS_Dp__0__PORT, 15 +.set USBFS_Dp__0__SHIFT, 6 +.set USBFS_Dp__AG, CYREG_PRT15_AG +.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX +.set USBFS_Dp__BIE, CYREG_PRT15_BIE +.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK +.set USBFS_Dp__BYP, CYREG_PRT15_BYP +.set USBFS_Dp__CTL, CYREG_PRT15_CTL +.set USBFS_Dp__DM0, CYREG_PRT15_DM0 +.set USBFS_Dp__DM1, CYREG_PRT15_DM1 +.set USBFS_Dp__DM2, CYREG_PRT15_DM2 +.set USBFS_Dp__DR, CYREG_PRT15_DR +.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS +.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT +.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG +.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN +.set USBFS_Dp__MASK, 0x40 +.set USBFS_Dp__PORT, 15 +.set USBFS_Dp__PRT, CYREG_PRT15_PRT +.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL +.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN +.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 +.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 +.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 +.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 +.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT +.set USBFS_Dp__PS, CYREG_PRT15_PS +.set USBFS_Dp__SHIFT, 6 +.set USBFS_Dp__SLW, CYREG_PRT15_SLW +.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15 + +/* SCSI_In */ +.set SCSI_In__0__AG, CYREG_PRT2_AG +.set SCSI_In__0__AMUX, CYREG_PRT2_AMUX +.set SCSI_In__0__BIE, CYREG_PRT2_BIE +.set SCSI_In__0__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_In__0__BYP, CYREG_PRT2_BYP +.set SCSI_In__0__CTL, CYREG_PRT2_CTL +.set SCSI_In__0__DM0, CYREG_PRT2_DM0 +.set SCSI_In__0__DM1, CYREG_PRT2_DM1 +.set SCSI_In__0__DM2, CYREG_PRT2_DM2 +.set SCSI_In__0__DR, CYREG_PRT2_DR +.set SCSI_In__0__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_In__0__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_In__0__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_In__0__MASK, 0x02 +.set SCSI_In__0__PC, CYREG_PRT2_PC1 +.set SCSI_In__0__PORT, 2 +.set SCSI_In__0__PRT, CYREG_PRT2_PRT +.set SCSI_In__0__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_In__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_In__0__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_In__0__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_In__0__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_In__0__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_In__0__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_In__0__PS, CYREG_PRT2_PS +.set SCSI_In__0__SHIFT, 1 +.set SCSI_In__0__SLW, CYREG_PRT2_SLW +.set SCSI_In__1__AG, CYREG_PRT6_AG +.set SCSI_In__1__AMUX, CYREG_PRT6_AMUX +.set SCSI_In__1__BIE, CYREG_PRT6_BIE +.set SCSI_In__1__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_In__1__BYP, CYREG_PRT6_BYP +.set SCSI_In__1__CTL, CYREG_PRT6_CTL +.set SCSI_In__1__DM0, CYREG_PRT6_DM0 +.set SCSI_In__1__DM1, CYREG_PRT6_DM1 +.set SCSI_In__1__DM2, CYREG_PRT6_DM2 +.set SCSI_In__1__DR, CYREG_PRT6_DR +.set SCSI_In__1__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_In__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_In__1__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_In__1__MASK, 0x08 +.set SCSI_In__1__PC, CYREG_PRT6_PC3 +.set SCSI_In__1__PORT, 6 +.set SCSI_In__1__PRT, CYREG_PRT6_PRT +.set SCSI_In__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_In__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_In__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_In__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_In__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_In__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_In__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_In__1__PS, CYREG_PRT6_PS +.set SCSI_In__1__SHIFT, 3 +.set SCSI_In__1__SLW, CYREG_PRT6_SLW +.set SCSI_In__2__AG, CYREG_PRT6_AG +.set SCSI_In__2__AMUX, CYREG_PRT6_AMUX +.set SCSI_In__2__BIE, CYREG_PRT6_BIE +.set SCSI_In__2__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_In__2__BYP, CYREG_PRT6_BYP +.set SCSI_In__2__CTL, CYREG_PRT6_CTL +.set SCSI_In__2__DM0, CYREG_PRT6_DM0 +.set SCSI_In__2__DM1, CYREG_PRT6_DM1 +.set SCSI_In__2__DM2, CYREG_PRT6_DM2 +.set SCSI_In__2__DR, CYREG_PRT6_DR +.set SCSI_In__2__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_In__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_In__2__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_In__2__MASK, 0x04 +.set SCSI_In__2__PC, CYREG_PRT6_PC2 +.set SCSI_In__2__PORT, 6 +.set SCSI_In__2__PRT, CYREG_PRT6_PRT +.set SCSI_In__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_In__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_In__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_In__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_In__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_In__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_In__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_In__2__PS, CYREG_PRT6_PS +.set SCSI_In__2__SHIFT, 2 +.set SCSI_In__2__SLW, CYREG_PRT6_SLW +.set SCSI_In__3__AG, CYREG_PRT4_AG +.set SCSI_In__3__AMUX, CYREG_PRT4_AMUX +.set SCSI_In__3__BIE, CYREG_PRT4_BIE +.set SCSI_In__3__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_In__3__BYP, CYREG_PRT4_BYP +.set SCSI_In__3__CTL, CYREG_PRT4_CTL +.set SCSI_In__3__DM0, CYREG_PRT4_DM0 +.set SCSI_In__3__DM1, CYREG_PRT4_DM1 +.set SCSI_In__3__DM2, CYREG_PRT4_DM2 +.set SCSI_In__3__DR, CYREG_PRT4_DR +.set SCSI_In__3__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_In__3__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_In__3__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_In__3__MASK, 0x40 +.set SCSI_In__3__PC, CYREG_PRT4_PC6 +.set SCSI_In__3__PORT, 4 +.set SCSI_In__3__PRT, CYREG_PRT4_PRT +.set SCSI_In__3__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_In__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_In__3__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_In__3__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_In__3__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_In__3__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_In__3__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_In__3__PS, CYREG_PRT4_PS +.set SCSI_In__3__SHIFT, 6 +.set SCSI_In__3__SLW, CYREG_PRT4_SLW +.set SCSI_In__4__AG, CYREG_PRT4_AG +.set SCSI_In__4__AMUX, CYREG_PRT4_AMUX +.set SCSI_In__4__BIE, CYREG_PRT4_BIE +.set SCSI_In__4__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_In__4__BYP, CYREG_PRT4_BYP +.set SCSI_In__4__CTL, CYREG_PRT4_CTL +.set SCSI_In__4__DM0, CYREG_PRT4_DM0 +.set SCSI_In__4__DM1, CYREG_PRT4_DM1 +.set SCSI_In__4__DM2, CYREG_PRT4_DM2 +.set SCSI_In__4__DR, CYREG_PRT4_DR +.set SCSI_In__4__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_In__4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_In__4__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_In__4__MASK, 0x08 +.set SCSI_In__4__PC, CYREG_PRT4_PC3 +.set SCSI_In__4__PORT, 4 +.set SCSI_In__4__PRT, CYREG_PRT4_PRT +.set SCSI_In__4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_In__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_In__4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_In__4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_In__4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_In__4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_In__4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_In__4__PS, CYREG_PRT4_PS +.set SCSI_In__4__SHIFT, 3 +.set SCSI_In__4__SLW, CYREG_PRT4_SLW +.set SCSI_In__5__AG, CYREG_PRT4_AG +.set SCSI_In__5__AMUX, CYREG_PRT4_AMUX +.set SCSI_In__5__BIE, CYREG_PRT4_BIE +.set SCSI_In__5__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_In__5__BYP, CYREG_PRT4_BYP +.set SCSI_In__5__CTL, CYREG_PRT4_CTL +.set SCSI_In__5__DM0, CYREG_PRT4_DM0 +.set SCSI_In__5__DM1, CYREG_PRT4_DM1 +.set SCSI_In__5__DM2, CYREG_PRT4_DM2 +.set SCSI_In__5__DR, CYREG_PRT4_DR +.set SCSI_In__5__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_In__5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_In__5__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_In__5__MASK, 0x04 +.set SCSI_In__5__PC, CYREG_PRT4_PC2 +.set SCSI_In__5__PORT, 4 +.set SCSI_In__5__PRT, CYREG_PRT4_PRT +.set SCSI_In__5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_In__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_In__5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_In__5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_In__5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_In__5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_In__5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_In__5__PS, CYREG_PRT4_PS +.set SCSI_In__5__SHIFT, 2 +.set SCSI_In__5__SLW, CYREG_PRT4_SLW +.set SCSI_In__6__AG, CYREG_PRT0_AG +.set SCSI_In__6__AMUX, CYREG_PRT0_AMUX +.set SCSI_In__6__BIE, CYREG_PRT0_BIE +.set SCSI_In__6__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_In__6__BYP, CYREG_PRT0_BYP +.set SCSI_In__6__CTL, CYREG_PRT0_CTL +.set SCSI_In__6__DM0, CYREG_PRT0_DM0 +.set SCSI_In__6__DM1, CYREG_PRT0_DM1 +.set SCSI_In__6__DM2, CYREG_PRT0_DM2 +.set SCSI_In__6__DR, CYREG_PRT0_DR +.set SCSI_In__6__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_In__6__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_In__6__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_In__6__MASK, 0x20 +.set SCSI_In__6__PC, CYREG_PRT0_PC5 +.set SCSI_In__6__PORT, 0 +.set SCSI_In__6__PRT, CYREG_PRT0_PRT +.set SCSI_In__6__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_In__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_In__6__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_In__6__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_In__6__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_In__6__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_In__6__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_In__6__PS, CYREG_PRT0_PS +.set SCSI_In__6__SHIFT, 5 +.set SCSI_In__6__SLW, CYREG_PRT0_SLW +.set SCSI_In__7__AG, CYREG_PRT0_AG +.set SCSI_In__7__AMUX, CYREG_PRT0_AMUX +.set SCSI_In__7__BIE, CYREG_PRT0_BIE +.set SCSI_In__7__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_In__7__BYP, CYREG_PRT0_BYP +.set SCSI_In__7__CTL, CYREG_PRT0_CTL +.set SCSI_In__7__DM0, CYREG_PRT0_DM0 +.set SCSI_In__7__DM1, CYREG_PRT0_DM1 +.set SCSI_In__7__DM2, CYREG_PRT0_DM2 +.set SCSI_In__7__DR, CYREG_PRT0_DR +.set SCSI_In__7__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_In__7__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_In__7__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_In__7__MASK, 0x10 +.set SCSI_In__7__PC, CYREG_PRT0_PC4 +.set SCSI_In__7__PORT, 0 +.set SCSI_In__7__PRT, CYREG_PRT0_PRT +.set SCSI_In__7__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_In__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_In__7__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_In__7__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_In__7__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_In__7__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_In__7__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_In__7__PS, CYREG_PRT0_PS +.set SCSI_In__7__SHIFT, 4 +.set SCSI_In__7__SLW, CYREG_PRT0_SLW +.set SCSI_In__ACK__AG, CYREG_PRT6_AG +.set SCSI_In__ACK__AMUX, CYREG_PRT6_AMUX +.set SCSI_In__ACK__BIE, CYREG_PRT6_BIE +.set SCSI_In__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_In__ACK__BYP, CYREG_PRT6_BYP +.set SCSI_In__ACK__CTL, CYREG_PRT6_CTL +.set SCSI_In__ACK__DM0, CYREG_PRT6_DM0 +.set SCSI_In__ACK__DM1, CYREG_PRT6_DM1 +.set SCSI_In__ACK__DM2, CYREG_PRT6_DM2 +.set SCSI_In__ACK__DR, CYREG_PRT6_DR +.set SCSI_In__ACK__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_In__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_In__ACK__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_In__ACK__MASK, 0x04 +.set SCSI_In__ACK__PC, CYREG_PRT6_PC2 +.set SCSI_In__ACK__PORT, 6 +.set SCSI_In__ACK__PRT, CYREG_PRT6_PRT +.set SCSI_In__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_In__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_In__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_In__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_In__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_In__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_In__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_In__ACK__PS, CYREG_PRT6_PS +.set SCSI_In__ACK__SHIFT, 2 +.set SCSI_In__ACK__SLW, CYREG_PRT6_SLW +.set SCSI_In__BSY__AG, CYREG_PRT6_AG +.set SCSI_In__BSY__AMUX, CYREG_PRT6_AMUX +.set SCSI_In__BSY__BIE, CYREG_PRT6_BIE +.set SCSI_In__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_In__BSY__BYP, CYREG_PRT6_BYP +.set SCSI_In__BSY__CTL, CYREG_PRT6_CTL +.set SCSI_In__BSY__DM0, CYREG_PRT6_DM0 +.set SCSI_In__BSY__DM1, CYREG_PRT6_DM1 +.set SCSI_In__BSY__DM2, CYREG_PRT6_DM2 +.set SCSI_In__BSY__DR, CYREG_PRT6_DR +.set SCSI_In__BSY__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_In__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_In__BSY__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_In__BSY__MASK, 0x08 +.set SCSI_In__BSY__PC, CYREG_PRT6_PC3 +.set SCSI_In__BSY__PORT, 6 +.set SCSI_In__BSY__PRT, CYREG_PRT6_PRT +.set SCSI_In__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_In__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_In__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_In__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_In__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_In__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_In__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_In__BSY__PS, CYREG_PRT6_PS +.set SCSI_In__BSY__SHIFT, 3 +.set SCSI_In__BSY__SLW, CYREG_PRT6_SLW +.set SCSI_In__CD__AG, CYREG_PRT4_AG +.set SCSI_In__CD__AMUX, CYREG_PRT4_AMUX +.set SCSI_In__CD__BIE, CYREG_PRT4_BIE +.set SCSI_In__CD__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_In__CD__BYP, CYREG_PRT4_BYP +.set SCSI_In__CD__CTL, CYREG_PRT4_CTL +.set SCSI_In__CD__DM0, CYREG_PRT4_DM0 +.set SCSI_In__CD__DM1, CYREG_PRT4_DM1 +.set SCSI_In__CD__DM2, CYREG_PRT4_DM2 +.set SCSI_In__CD__DR, CYREG_PRT4_DR +.set SCSI_In__CD__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_In__CD__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_In__CD__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_In__CD__MASK, 0x04 +.set SCSI_In__CD__PC, CYREG_PRT4_PC2 +.set SCSI_In__CD__PORT, 4 +.set SCSI_In__CD__PRT, CYREG_PRT4_PRT +.set SCSI_In__CD__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_In__CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_In__CD__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_In__CD__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_In__CD__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_In__CD__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_In__CD__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_In__CD__PS, CYREG_PRT4_PS +.set SCSI_In__CD__SHIFT, 2 +.set SCSI_In__CD__SLW, CYREG_PRT4_SLW +.set SCSI_In__DBP__AG, CYREG_PRT2_AG +.set SCSI_In__DBP__AMUX, CYREG_PRT2_AMUX +.set SCSI_In__DBP__BIE, CYREG_PRT2_BIE +.set SCSI_In__DBP__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_In__DBP__BYP, CYREG_PRT2_BYP +.set SCSI_In__DBP__CTL, CYREG_PRT2_CTL +.set SCSI_In__DBP__DM0, CYREG_PRT2_DM0 +.set SCSI_In__DBP__DM1, CYREG_PRT2_DM1 +.set SCSI_In__DBP__DM2, CYREG_PRT2_DM2 +.set SCSI_In__DBP__DR, CYREG_PRT2_DR +.set SCSI_In__DBP__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_In__DBP__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_In__DBP__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_In__DBP__MASK, 0x02 +.set SCSI_In__DBP__PC, CYREG_PRT2_PC1 +.set SCSI_In__DBP__PORT, 2 +.set SCSI_In__DBP__PRT, CYREG_PRT2_PRT +.set SCSI_In__DBP__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_In__DBP__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_In__DBP__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_In__DBP__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_In__DBP__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_In__DBP__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_In__DBP__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_In__DBP__PS, CYREG_PRT2_PS +.set SCSI_In__DBP__SHIFT, 1 +.set SCSI_In__DBP__SLW, CYREG_PRT2_SLW +.set SCSI_In__IO__AG, CYREG_PRT0_AG +.set SCSI_In__IO__AMUX, CYREG_PRT0_AMUX +.set SCSI_In__IO__BIE, CYREG_PRT0_BIE +.set SCSI_In__IO__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_In__IO__BYP, CYREG_PRT0_BYP +.set SCSI_In__IO__CTL, CYREG_PRT0_CTL +.set SCSI_In__IO__DM0, CYREG_PRT0_DM0 +.set SCSI_In__IO__DM1, CYREG_PRT0_DM1 +.set SCSI_In__IO__DM2, CYREG_PRT0_DM2 +.set SCSI_In__IO__DR, CYREG_PRT0_DR +.set SCSI_In__IO__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_In__IO__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_In__IO__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_In__IO__MASK, 0x10 +.set SCSI_In__IO__PC, CYREG_PRT0_PC4 +.set SCSI_In__IO__PORT, 0 +.set SCSI_In__IO__PRT, CYREG_PRT0_PRT +.set SCSI_In__IO__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_In__IO__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_In__IO__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_In__IO__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_In__IO__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_In__IO__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_In__IO__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_In__IO__PS, CYREG_PRT0_PS +.set SCSI_In__IO__SHIFT, 4 +.set SCSI_In__IO__SLW, CYREG_PRT0_SLW +.set SCSI_In__MSG__AG, CYREG_PRT4_AG +.set SCSI_In__MSG__AMUX, CYREG_PRT4_AMUX +.set SCSI_In__MSG__BIE, CYREG_PRT4_BIE +.set SCSI_In__MSG__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_In__MSG__BYP, CYREG_PRT4_BYP +.set SCSI_In__MSG__CTL, CYREG_PRT4_CTL +.set SCSI_In__MSG__DM0, CYREG_PRT4_DM0 +.set SCSI_In__MSG__DM1, CYREG_PRT4_DM1 +.set SCSI_In__MSG__DM2, CYREG_PRT4_DM2 +.set SCSI_In__MSG__DR, CYREG_PRT4_DR +.set SCSI_In__MSG__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_In__MSG__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_In__MSG__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_In__MSG__MASK, 0x40 +.set SCSI_In__MSG__PC, CYREG_PRT4_PC6 +.set SCSI_In__MSG__PORT, 4 +.set SCSI_In__MSG__PRT, CYREG_PRT4_PRT +.set SCSI_In__MSG__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_In__MSG__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_In__MSG__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_In__MSG__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_In__MSG__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_In__MSG__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_In__MSG__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_In__MSG__PS, CYREG_PRT4_PS +.set SCSI_In__MSG__SHIFT, 6 +.set SCSI_In__MSG__SLW, CYREG_PRT4_SLW +.set SCSI_In__REQ__AG, CYREG_PRT0_AG +.set SCSI_In__REQ__AMUX, CYREG_PRT0_AMUX +.set SCSI_In__REQ__BIE, CYREG_PRT0_BIE +.set SCSI_In__REQ__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_In__REQ__BYP, CYREG_PRT0_BYP +.set SCSI_In__REQ__CTL, CYREG_PRT0_CTL +.set SCSI_In__REQ__DM0, CYREG_PRT0_DM0 +.set SCSI_In__REQ__DM1, CYREG_PRT0_DM1 +.set SCSI_In__REQ__DM2, CYREG_PRT0_DM2 +.set SCSI_In__REQ__DR, CYREG_PRT0_DR +.set SCSI_In__REQ__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_In__REQ__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_In__REQ__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_In__REQ__MASK, 0x20 +.set SCSI_In__REQ__PC, CYREG_PRT0_PC5 +.set SCSI_In__REQ__PORT, 0 +.set SCSI_In__REQ__PRT, CYREG_PRT0_PRT +.set SCSI_In__REQ__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_In__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_In__REQ__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_In__REQ__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_In__REQ__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_In__REQ__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_In__REQ__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_In__REQ__PS, CYREG_PRT0_PS +.set SCSI_In__REQ__SHIFT, 5 +.set SCSI_In__REQ__SLW, CYREG_PRT0_SLW +.set SCSI_In__SEL__AG, CYREG_PRT4_AG +.set SCSI_In__SEL__AMUX, CYREG_PRT4_AMUX +.set SCSI_In__SEL__BIE, CYREG_PRT4_BIE +.set SCSI_In__SEL__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_In__SEL__BYP, CYREG_PRT4_BYP +.set SCSI_In__SEL__CTL, CYREG_PRT4_CTL +.set SCSI_In__SEL__DM0, CYREG_PRT4_DM0 +.set SCSI_In__SEL__DM1, CYREG_PRT4_DM1 +.set SCSI_In__SEL__DM2, CYREG_PRT4_DM2 +.set SCSI_In__SEL__DR, CYREG_PRT4_DR +.set SCSI_In__SEL__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_In__SEL__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_In__SEL__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_In__SEL__MASK, 0x08 +.set SCSI_In__SEL__PC, CYREG_PRT4_PC3 +.set SCSI_In__SEL__PORT, 4 +.set SCSI_In__SEL__PRT, CYREG_PRT4_PRT +.set SCSI_In__SEL__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_In__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_In__SEL__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_In__SEL__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_In__SEL__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_In__SEL__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_In__SEL__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_In__SEL__PS, CYREG_PRT4_PS +.set SCSI_In__SEL__SHIFT, 3 +.set SCSI_In__SEL__SLW, CYREG_PRT4_SLW + +/* SD_MISO */ +.set SD_MISO__0__MASK, 0x02 +.set SD_MISO__0__PC, CYREG_PRT3_PC1 +.set SD_MISO__0__PORT, 3 +.set SD_MISO__0__SHIFT, 1 +.set SD_MISO__AG, CYREG_PRT3_AG +.set SD_MISO__AMUX, CYREG_PRT3_AMUX +.set SD_MISO__BIE, CYREG_PRT3_BIE +.set SD_MISO__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_MISO__BYP, CYREG_PRT3_BYP +.set SD_MISO__CTL, CYREG_PRT3_CTL +.set SD_MISO__DM0, CYREG_PRT3_DM0 +.set SD_MISO__DM1, CYREG_PRT3_DM1 +.set SD_MISO__DM2, CYREG_PRT3_DM2 +.set SD_MISO__DR, CYREG_PRT3_DR +.set SD_MISO__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_MISO__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_MISO__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_MISO__MASK, 0x02 +.set SD_MISO__PORT, 3 +.set SD_MISO__PRT, CYREG_PRT3_PRT +.set SD_MISO__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_MISO__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_MISO__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_MISO__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_MISO__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_MISO__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_MISO__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_MISO__PS, CYREG_PRT3_PS +.set SD_MISO__SHIFT, 1 +.set SD_MISO__SLW, CYREG_PRT3_SLW + +/* SD_MOSI */ +.set SD_MOSI__0__MASK, 0x08 +.set SD_MOSI__0__PC, CYREG_PRT3_PC3 +.set SD_MOSI__0__PORT, 3 +.set SD_MOSI__0__SHIFT, 3 +.set SD_MOSI__AG, CYREG_PRT3_AG +.set SD_MOSI__AMUX, CYREG_PRT3_AMUX +.set SD_MOSI__BIE, CYREG_PRT3_BIE +.set SD_MOSI__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_MOSI__BYP, CYREG_PRT3_BYP +.set SD_MOSI__CTL, CYREG_PRT3_CTL +.set SD_MOSI__DM0, CYREG_PRT3_DM0 +.set SD_MOSI__DM1, CYREG_PRT3_DM1 +.set SD_MOSI__DM2, CYREG_PRT3_DM2 +.set SD_MOSI__DR, CYREG_PRT3_DR +.set SD_MOSI__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_MOSI__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_MOSI__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_MOSI__MASK, 0x08 +.set SD_MOSI__PORT, 3 +.set SD_MOSI__PRT, CYREG_PRT3_PRT +.set SD_MOSI__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_MOSI__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_MOSI__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_MOSI__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_MOSI__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_MOSI__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_MOSI__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_MOSI__PS, CYREG_PRT3_PS +.set SD_MOSI__SHIFT, 3 +.set SD_MOSI__SLW, CYREG_PRT3_SLW + +/* SD_SCK */ +.set SD_SCK__0__MASK, 0x04 +.set SD_SCK__0__PC, CYREG_PRT3_PC2 +.set SD_SCK__0__PORT, 3 +.set SD_SCK__0__SHIFT, 2 +.set SD_SCK__AG, CYREG_PRT3_AG +.set SD_SCK__AMUX, CYREG_PRT3_AMUX +.set SD_SCK__BIE, CYREG_PRT3_BIE +.set SD_SCK__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_SCK__BYP, CYREG_PRT3_BYP +.set SD_SCK__CTL, CYREG_PRT3_CTL +.set SD_SCK__DM0, CYREG_PRT3_DM0 +.set SD_SCK__DM1, CYREG_PRT3_DM1 +.set SD_SCK__DM2, CYREG_PRT3_DM2 +.set SD_SCK__DR, CYREG_PRT3_DR +.set SD_SCK__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_SCK__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_SCK__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_SCK__MASK, 0x04 +.set SD_SCK__PORT, 3 +.set SD_SCK__PRT, CYREG_PRT3_PRT +.set SD_SCK__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_SCK__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_SCK__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_SCK__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_SCK__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_SCK__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_SCK__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_SCK__PS, CYREG_PRT3_PS +.set SD_SCK__SHIFT, 2 +.set SD_SCK__SLW, CYREG_PRT3_SLW + +/* SD_CD */ +.set SD_CD__0__MASK, 0x20 +.set SD_CD__0__PC, CYREG_PRT3_PC5 +.set SD_CD__0__PORT, 3 +.set SD_CD__0__SHIFT, 5 +.set SD_CD__AG, CYREG_PRT3_AG +.set SD_CD__AMUX, CYREG_PRT3_AMUX +.set SD_CD__BIE, CYREG_PRT3_BIE +.set SD_CD__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_CD__BYP, CYREG_PRT3_BYP +.set SD_CD__CTL, CYREG_PRT3_CTL +.set SD_CD__DM0, CYREG_PRT3_DM0 +.set SD_CD__DM1, CYREG_PRT3_DM1 +.set SD_CD__DM2, CYREG_PRT3_DM2 +.set SD_CD__DR, CYREG_PRT3_DR +.set SD_CD__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_CD__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_CD__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_CD__MASK, 0x20 +.set SD_CD__PORT, 3 +.set SD_CD__PRT, CYREG_PRT3_PRT +.set SD_CD__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_CD__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_CD__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_CD__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_CD__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_CD__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_CD__PS, CYREG_PRT3_PS +.set SD_CD__SHIFT, 5 +.set SD_CD__SLW, CYREG_PRT3_SLW + +/* SD_CS */ +.set SD_CS__0__MASK, 0x10 +.set SD_CS__0__PC, CYREG_PRT3_PC4 +.set SD_CS__0__PORT, 3 +.set SD_CS__0__SHIFT, 4 +.set SD_CS__AG, CYREG_PRT3_AG +.set SD_CS__AMUX, CYREG_PRT3_AMUX +.set SD_CS__BIE, CYREG_PRT3_BIE +.set SD_CS__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_CS__BYP, CYREG_PRT3_BYP +.set SD_CS__CTL, CYREG_PRT3_CTL +.set SD_CS__DM0, CYREG_PRT3_DM0 +.set SD_CS__DM1, CYREG_PRT3_DM1 +.set SD_CS__DM2, CYREG_PRT3_DM2 +.set SD_CS__DR, CYREG_PRT3_DR +.set SD_CS__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_CS__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_CS__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_CS__MASK, 0x10 +.set SD_CS__PORT, 3 +.set SD_CS__PRT, CYREG_PRT3_PRT +.set SD_CS__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_CS__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_CS__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_CS__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_CS__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_CS__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_CS__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_CS__PS, CYREG_PRT3_PS +.set SD_CS__SHIFT, 4 +.set SD_CS__SLW, CYREG_PRT3_SLW + +/* LED1 */ +.set LED1__0__MASK, 0x02 +.set LED1__0__PC, CYREG_PRT0_PC1 +.set LED1__0__PORT, 0 +.set LED1__0__SHIFT, 1 +.set LED1__AG, CYREG_PRT0_AG +.set LED1__AMUX, CYREG_PRT0_AMUX +.set LED1__BIE, CYREG_PRT0_BIE +.set LED1__BIT_MASK, CYREG_PRT0_BIT_MASK +.set LED1__BYP, CYREG_PRT0_BYP +.set LED1__CTL, CYREG_PRT0_CTL +.set LED1__DM0, CYREG_PRT0_DM0 +.set LED1__DM1, CYREG_PRT0_DM1 +.set LED1__DM2, CYREG_PRT0_DM2 +.set LED1__DR, CYREG_PRT0_DR +.set LED1__INP_DIS, CYREG_PRT0_INP_DIS +.set LED1__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set LED1__LCD_EN, CYREG_PRT0_LCD_EN +.set LED1__MASK, 0x02 +.set LED1__PORT, 0 +.set LED1__PRT, CYREG_PRT0_PRT +.set LED1__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set LED1__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set LED1__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set LED1__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set LED1__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set LED1__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set LED1__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set LED1__PS, CYREG_PRT0_PS +.set LED1__SHIFT, 1 +.set LED1__SLW, CYREG_PRT0_SLW + +/* Miscellaneous */ +/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */ +.set CYDEV_DEBUGGING_DPS_SWD_SWV, 6 +.set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0 +.set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0 +.set CYDEV_CONFIG_FASTBOOT_ENABLED, 1 +.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0 +.set CYDEV_CHIP_MEMBER_5B, 4 +.set CYDEV_CHIP_FAMILY_PSOC5, 3 +.set CYDEV_CHIP_DIE_PSOC5LP, 4 +.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_DIE_PSOC5LP +.set BCLK__BUS_CLK__HZ, 60000000 +.set BCLK__BUS_CLK__KHZ, 60000 +.set BCLK__BUS_CLK__MHZ, 60 +.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT +.set CYDEV_CHIP_DIE_LEOPARD, 1 +.set CYDEV_CHIP_DIE_PANTHER, 3 +.set CYDEV_CHIP_DIE_PSOC4A, 2 +.set CYDEV_CHIP_DIE_UNKNOWN, 0 +.set CYDEV_CHIP_FAMILY_PSOC3, 1 +.set CYDEV_CHIP_FAMILY_PSOC4, 2 +.set CYDEV_CHIP_FAMILY_UNKNOWN, 0 +.set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5 +.set CYDEV_CHIP_JTAG_ID, 0x2E133069 +.set CYDEV_CHIP_MEMBER_3A, 1 +.set CYDEV_CHIP_MEMBER_4A, 2 +.set CYDEV_CHIP_MEMBER_5A, 3 +.set CYDEV_CHIP_MEMBER_UNKNOWN, 0 +.set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B +.set CYDEV_CHIP_REVISION_3A_ES1, 0 +.set CYDEV_CHIP_REVISION_3A_ES2, 1 +.set CYDEV_CHIP_REVISION_3A_ES3, 3 +.set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3 +.set CYDEV_CHIP_REVISION_4A_ES0, 17 +.set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17 +.set CYDEV_CHIP_REVISION_5A_ES0, 0 +.set CYDEV_CHIP_REVISION_5A_ES1, 1 +.set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1 +.set CYDEV_CHIP_REVISION_5B_ES0, 0 +.set CYDEV_CHIP_REVISION_USED, CYDEV_CHIP_REVISION_5B_PRODUCTION +.set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REV_PSOC5LP_PRODUCTION +.set CYDEV_CHIP_REV_LEOPARD_ES1, 0 +.set CYDEV_CHIP_REV_LEOPARD_ES2, 1 +.set CYDEV_CHIP_REV_LEOPARD_ES3, 3 +.set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3 +.set CYDEV_CHIP_REV_PANTHER_ES0, 0 +.set CYDEV_CHIP_REV_PANTHER_ES1, 1 +.set CYDEV_CHIP_REV_PANTHER_PRODUCTION, 1 +.set CYDEV_CHIP_REV_PSOC4A_ES0, 17 +.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17 +.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0 +.set CYDEV_CONFIGURATION_COMPRESSED, 1 +.set CYDEV_CONFIGURATION_DMA, 0 +.set CYDEV_CONFIGURATION_ECC, 0 +.set CYDEV_CONFIGURATION_IMOENABLED, CYDEV_CONFIG_FASTBOOT_ENABLED +.set CYDEV_CONFIGURATION_MODE, CYDEV_CONFIGURATION_MODE_COMPRESSED +.set CYDEV_CONFIGURATION_MODE_DMA, 2 +.set CYDEV_CONFIGURATION_MODE_UNCOMPRESSED, 1 +.set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_AllowButWarn +.set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1 +.set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2 +.set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD_SWV +.set CYDEV_DEBUGGING_DPS_Disable, 3 +.set CYDEV_DEBUGGING_DPS_JTAG_4, 1 +.set CYDEV_DEBUGGING_DPS_JTAG_5, 0 +.set CYDEV_DEBUGGING_DPS_SWD, 2 +.set CYDEV_DEBUGGING_ENABLE, 1 +.set CYDEV_DEBUGGING_XRES, 0 +.set CYDEV_DEBUG_ENABLE_MASK, 0x20 +.set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG +.set CYDEV_DMA_CHANNELS_AVAILABLE, 24 +.set CYDEV_ECC_ENABLE, 0 +.set CYDEV_HEAP_SIZE, 0x1000 +.set CYDEV_INSTRUCT_CACHE_ENABLED, 1 +.set CYDEV_INTR_RISING, 0x00000000 +.set CYDEV_PROJ_TYPE, 2 +.set CYDEV_PROJ_TYPE_BOOTLOADER, 1 +.set CYDEV_PROJ_TYPE_LOADABLE, 2 +.set CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER, 3 +.set CYDEV_PROJ_TYPE_STANDARD, 0 +.set CYDEV_PROTECTION_ENABLE, 0 +.set CYDEV_STACK_SIZE, 0x4000 +.set CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP, 1 +.set CYDEV_USE_BUNDLED_CMSIS, 1 +.set CYDEV_VARIABLE_VDDA, 0 +.set CYDEV_VDDA_MV, 5000 +.set CYDEV_VDDD_MV, 5000 +.set CYDEV_VDDIO0_MV, 5000 +.set CYDEV_VDDIO1_MV, 5000 +.set CYDEV_VDDIO2_MV, 5000 +.set CYDEV_VDDIO3_MV, 3300 +.set CYDEV_VIO0, 5 +.set CYDEV_VIO0_MV, 5000 +.set CYDEV_VIO1, 5 +.set CYDEV_VIO1_MV, 5000 +.set CYDEV_VIO2, 5 +.set CYDEV_VIO2_MV, 5000 +.set CYDEV_VIO3_MV, 3300 +.set DMA_CHANNELS_USED__MASK0, 0x00000000 +.set CYDEV_BOOTLOADER_ENABLE, 0 +.endif diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyfitteriar.inc new file mode 100755 index 00000000..3bc1da72 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyfitteriar.inc @@ -0,0 +1,2677 @@ +#ifndef INCLUDED_CYFITTERIAR_INC +#define INCLUDED_CYFITTERIAR_INC + INCLUDE cydeviceiar.inc + INCLUDE cydeviceiar_trm.inc + +/* USBFS_bus_reset */ +USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_bus_reset__INTC_MASK EQU 0x800000 +USBFS_bus_reset__INTC_NUMBER EQU 23 +USBFS_bus_reset__INTC_PRIOR_NUM EQU 7 +USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23 +USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* USBFS_arb_int */ +USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_arb_int__INTC_MASK EQU 0x400000 +USBFS_arb_int__INTC_NUMBER EQU 22 +USBFS_arb_int__INTC_PRIOR_NUM EQU 7 +USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22 +USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* USBFS_sof_int */ +USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_sof_int__INTC_MASK EQU 0x200000 +USBFS_sof_int__INTC_NUMBER EQU 21 +USBFS_sof_int__INTC_PRIOR_NUM EQU 7 +USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21 +USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* SCSI_Out_DBx */ +SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG +SCSI_Out_DBx__0__AMUX EQU CYREG_PRT5_AMUX +SCSI_Out_DBx__0__BIE EQU CYREG_PRT5_BIE +SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_Out_DBx__0__BYP EQU CYREG_PRT5_BYP +SCSI_Out_DBx__0__CTL EQU CYREG_PRT5_CTL +SCSI_Out_DBx__0__DM0 EQU CYREG_PRT5_DM0 +SCSI_Out_DBx__0__DM1 EQU CYREG_PRT5_DM1 +SCSI_Out_DBx__0__DM2 EQU CYREG_PRT5_DM2 +SCSI_Out_DBx__0__DR EQU CYREG_PRT5_DR +SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_Out_DBx__0__MASK EQU 0x02 +SCSI_Out_DBx__0__PC EQU CYREG_PRT5_PC1 +SCSI_Out_DBx__0__PORT EQU 5 +SCSI_Out_DBx__0__PRT EQU CYREG_PRT5_PRT +SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_Out_DBx__0__PS EQU CYREG_PRT5_PS +SCSI_Out_DBx__0__SHIFT EQU 1 +SCSI_Out_DBx__0__SLW EQU CYREG_PRT5_SLW +SCSI_Out_DBx__1__AG EQU CYREG_PRT5_AG +SCSI_Out_DBx__1__AMUX EQU CYREG_PRT5_AMUX +SCSI_Out_DBx__1__BIE EQU CYREG_PRT5_BIE +SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_Out_DBx__1__BYP EQU CYREG_PRT5_BYP +SCSI_Out_DBx__1__CTL EQU CYREG_PRT5_CTL +SCSI_Out_DBx__1__DM0 EQU CYREG_PRT5_DM0 +SCSI_Out_DBx__1__DM1 EQU CYREG_PRT5_DM1 +SCSI_Out_DBx__1__DM2 EQU CYREG_PRT5_DM2 +SCSI_Out_DBx__1__DR EQU CYREG_PRT5_DR +SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_Out_DBx__1__MASK EQU 0x01 +SCSI_Out_DBx__1__PC EQU CYREG_PRT5_PC0 +SCSI_Out_DBx__1__PORT EQU 5 +SCSI_Out_DBx__1__PRT EQU CYREG_PRT5_PRT +SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_Out_DBx__1__PS EQU CYREG_PRT5_PS +SCSI_Out_DBx__1__SHIFT EQU 0 +SCSI_Out_DBx__1__SLW EQU CYREG_PRT5_SLW +SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG +SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE +SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP +SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL +SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR +SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out_DBx__2__MASK EQU 0x20 +SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC5 +SCSI_Out_DBx__2__PORT EQU 6 +SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT +SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS +SCSI_Out_DBx__2__SHIFT EQU 5 +SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW +SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG +SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE +SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP +SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL +SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR +SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out_DBx__3__MASK EQU 0x10 +SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC4 +SCSI_Out_DBx__3__PORT EQU 6 +SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT +SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS +SCSI_Out_DBx__3__SHIFT EQU 4 +SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW +SCSI_Out_DBx__4__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__4__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__4__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__4__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__4__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__4__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__4__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__4__MASK EQU 0x80 +SCSI_Out_DBx__4__PC EQU CYREG_PRT2_PC7 +SCSI_Out_DBx__4__PORT EQU 2 +SCSI_Out_DBx__4__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__4__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__4__SHIFT EQU 7 +SCSI_Out_DBx__4__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__5__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__5__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__5__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__5__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__5__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__5__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__5__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__5__MASK EQU 0x40 +SCSI_Out_DBx__5__PC EQU CYREG_PRT2_PC6 +SCSI_Out_DBx__5__PORT EQU 2 +SCSI_Out_DBx__5__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__5__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__5__SHIFT EQU 6 +SCSI_Out_DBx__5__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__6__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__6__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__6__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__6__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__6__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__6__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__6__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__6__MASK EQU 0x08 +SCSI_Out_DBx__6__PC EQU CYREG_PRT2_PC3 +SCSI_Out_DBx__6__PORT EQU 2 +SCSI_Out_DBx__6__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__6__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__6__SHIFT EQU 3 +SCSI_Out_DBx__6__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__7__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__7__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__7__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__7__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__7__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__7__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__7__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__7__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__7__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__7__MASK EQU 0x04 +SCSI_Out_DBx__7__PC EQU CYREG_PRT2_PC2 +SCSI_Out_DBx__7__PORT EQU 2 +SCSI_Out_DBx__7__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__7__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__7__SHIFT EQU 2 +SCSI_Out_DBx__7__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__DB0__AG EQU CYREG_PRT5_AG +SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX +SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT5_BIE +SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT5_BYP +SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT5_CTL +SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT5_DM0 +SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT5_DM1 +SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT5_DM2 +SCSI_Out_DBx__DB0__DR EQU CYREG_PRT5_DR +SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_Out_DBx__DB0__MASK EQU 0x02 +SCSI_Out_DBx__DB0__PC EQU CYREG_PRT5_PC1 +SCSI_Out_DBx__DB0__PORT EQU 5 +SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT5_PRT +SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_Out_DBx__DB0__PS EQU CYREG_PRT5_PS +SCSI_Out_DBx__DB0__SHIFT EQU 1 +SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT5_SLW +SCSI_Out_DBx__DB1__AG EQU CYREG_PRT5_AG +SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX +SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT5_BIE +SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT5_BYP +SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT5_CTL +SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT5_DM0 +SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT5_DM1 +SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT5_DM2 +SCSI_Out_DBx__DB1__DR EQU CYREG_PRT5_DR +SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_Out_DBx__DB1__MASK EQU 0x01 +SCSI_Out_DBx__DB1__PC EQU CYREG_PRT5_PC0 +SCSI_Out_DBx__DB1__PORT EQU 5 +SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT5_PRT +SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_Out_DBx__DB1__PS EQU CYREG_PRT5_PS +SCSI_Out_DBx__DB1__SHIFT EQU 0 +SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT5_SLW +SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG +SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE +SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP +SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL +SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR +SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out_DBx__DB2__MASK EQU 0x20 +SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC5 +SCSI_Out_DBx__DB2__PORT EQU 6 +SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT +SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS +SCSI_Out_DBx__DB2__SHIFT EQU 5 +SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW +SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG +SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE +SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP +SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL +SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR +SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out_DBx__DB3__MASK EQU 0x10 +SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC4 +SCSI_Out_DBx__DB3__PORT EQU 6 +SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT +SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS +SCSI_Out_DBx__DB3__SHIFT EQU 4 +SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW +SCSI_Out_DBx__DB4__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__DB4__MASK EQU 0x80 +SCSI_Out_DBx__DB4__PC EQU CYREG_PRT2_PC7 +SCSI_Out_DBx__DB4__PORT EQU 2 +SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__DB4__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__DB4__SHIFT EQU 7 +SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__DB5__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__DB5__MASK EQU 0x40 +SCSI_Out_DBx__DB5__PC EQU CYREG_PRT2_PC6 +SCSI_Out_DBx__DB5__PORT EQU 2 +SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__DB5__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__DB5__SHIFT EQU 6 +SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__DB6__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__DB6__MASK EQU 0x08 +SCSI_Out_DBx__DB6__PC EQU CYREG_PRT2_PC3 +SCSI_Out_DBx__DB6__PORT EQU 2 +SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__DB6__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__DB6__SHIFT EQU 3 +SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__DB7__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__DB7__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__DB7__MASK EQU 0x04 +SCSI_Out_DBx__DB7__PC EQU CYREG_PRT2_PC2 +SCSI_Out_DBx__DB7__PORT EQU 2 +SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__DB7__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__DB7__SHIFT EQU 2 +SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT2_SLW + +/* SCSI_RST_ISR */ +SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_RST_ISR__INTC_MASK EQU 0x100 +SCSI_RST_ISR__INTC_NUMBER EQU 8 +SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7 +SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 +SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* SDCard_BSPIM */ +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST +SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 +SDCard_BSPIM_RxStsReg__4__POS EQU 4 +SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 +SDCard_BSPIM_RxStsReg__5__POS EQU 5 +SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 +SDCard_BSPIM_RxStsReg__6__POS EQU 6 +SDCard_BSPIM_RxStsReg__MASK EQU 0x70 +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST +SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 +SDCard_BSPIM_TxStsReg__0__POS EQU 0 +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST +SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 +SDCard_BSPIM_TxStsReg__1__POS EQU 1 +SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 +SDCard_BSPIM_TxStsReg__2__POS EQU 2 +SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 +SDCard_BSPIM_TxStsReg__3__POS EQU 3 +SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 +SDCard_BSPIM_TxStsReg__4__POS EQU 4 +SDCard_BSPIM_TxStsReg__MASK EQU 0x1F +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB06_07_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB06_07_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB06_07_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB06_07_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB06_07_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB06_07_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB06_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB06_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB06_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB06_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB06_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB06_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB06_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB06_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB06_F1 + +/* USBFS_dp_int */ +USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_dp_int__INTC_MASK EQU 0x1000 +USBFS_dp_int__INTC_NUMBER EQU 12 +USBFS_dp_int__INTC_PRIOR_NUM EQU 7 +USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12 +USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* SCSI_CTL_IO */ +SCSI_CTL_IO_Sync_ctrl_reg__0__MASK EQU 0x01 +SCSI_CTL_IO_Sync_ctrl_reg__0__POS EQU 0 +SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL +SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL +SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL +SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL +SCSI_CTL_IO_Sync_ctrl_reg__MASK EQU 0x01 +SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK +SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL + +/* SCSI_In_DBx */ +SCSI_In_DBx__0__AG EQU CYREG_PRT5_AG +SCSI_In_DBx__0__AMUX EQU CYREG_PRT5_AMUX +SCSI_In_DBx__0__BIE EQU CYREG_PRT5_BIE +SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_In_DBx__0__BYP EQU CYREG_PRT5_BYP +SCSI_In_DBx__0__CTL EQU CYREG_PRT5_CTL +SCSI_In_DBx__0__DM0 EQU CYREG_PRT5_DM0 +SCSI_In_DBx__0__DM1 EQU CYREG_PRT5_DM1 +SCSI_In_DBx__0__DM2 EQU CYREG_PRT5_DM2 +SCSI_In_DBx__0__DR EQU CYREG_PRT5_DR +SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_In_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_In_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_In_DBx__0__MASK EQU 0x08 +SCSI_In_DBx__0__PC EQU CYREG_PRT5_PC3 +SCSI_In_DBx__0__PORT EQU 5 +SCSI_In_DBx__0__PRT EQU CYREG_PRT5_PRT +SCSI_In_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_In_DBx__0__PS EQU CYREG_PRT5_PS +SCSI_In_DBx__0__SHIFT EQU 3 +SCSI_In_DBx__0__SLW EQU CYREG_PRT5_SLW +SCSI_In_DBx__1__AG EQU CYREG_PRT5_AG +SCSI_In_DBx__1__AMUX EQU CYREG_PRT5_AMUX +SCSI_In_DBx__1__BIE EQU CYREG_PRT5_BIE +SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_In_DBx__1__BYP EQU CYREG_PRT5_BYP +SCSI_In_DBx__1__CTL EQU CYREG_PRT5_CTL +SCSI_In_DBx__1__DM0 EQU CYREG_PRT5_DM0 +SCSI_In_DBx__1__DM1 EQU CYREG_PRT5_DM1 +SCSI_In_DBx__1__DM2 EQU CYREG_PRT5_DM2 +SCSI_In_DBx__1__DR EQU CYREG_PRT5_DR +SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_In_DBx__1__MASK EQU 0x04 +SCSI_In_DBx__1__PC EQU CYREG_PRT5_PC2 +SCSI_In_DBx__1__PORT EQU 5 +SCSI_In_DBx__1__PRT EQU CYREG_PRT5_PRT +SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_In_DBx__1__PS EQU CYREG_PRT5_PS +SCSI_In_DBx__1__SHIFT EQU 2 +SCSI_In_DBx__1__SLW EQU CYREG_PRT5_SLW +SCSI_In_DBx__2__AG EQU CYREG_PRT6_AG +SCSI_In_DBx__2__AMUX EQU CYREG_PRT6_AMUX +SCSI_In_DBx__2__BIE EQU CYREG_PRT6_BIE +SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In_DBx__2__BYP EQU CYREG_PRT6_BYP +SCSI_In_DBx__2__CTL EQU CYREG_PRT6_CTL +SCSI_In_DBx__2__DM0 EQU CYREG_PRT6_DM0 +SCSI_In_DBx__2__DM1 EQU CYREG_PRT6_DM1 +SCSI_In_DBx__2__DM2 EQU CYREG_PRT6_DM2 +SCSI_In_DBx__2__DR EQU CYREG_PRT6_DR +SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In_DBx__2__MASK EQU 0x80 +SCSI_In_DBx__2__PC EQU CYREG_PRT6_PC7 +SCSI_In_DBx__2__PORT EQU 6 +SCSI_In_DBx__2__PRT EQU CYREG_PRT6_PRT +SCSI_In_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In_DBx__2__PS EQU CYREG_PRT6_PS +SCSI_In_DBx__2__SHIFT EQU 7 +SCSI_In_DBx__2__SLW EQU CYREG_PRT6_SLW +SCSI_In_DBx__3__AG EQU CYREG_PRT6_AG +SCSI_In_DBx__3__AMUX EQU CYREG_PRT6_AMUX +SCSI_In_DBx__3__BIE EQU CYREG_PRT6_BIE +SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In_DBx__3__BYP EQU CYREG_PRT6_BYP +SCSI_In_DBx__3__CTL EQU CYREG_PRT6_CTL +SCSI_In_DBx__3__DM0 EQU CYREG_PRT6_DM0 +SCSI_In_DBx__3__DM1 EQU CYREG_PRT6_DM1 +SCSI_In_DBx__3__DM2 EQU CYREG_PRT6_DM2 +SCSI_In_DBx__3__DR EQU CYREG_PRT6_DR +SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In_DBx__3__MASK EQU 0x40 +SCSI_In_DBx__3__PC EQU CYREG_PRT6_PC6 +SCSI_In_DBx__3__PORT EQU 6 +SCSI_In_DBx__3__PRT EQU CYREG_PRT6_PRT +SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In_DBx__3__PS EQU CYREG_PRT6_PS +SCSI_In_DBx__3__SHIFT EQU 6 +SCSI_In_DBx__3__SLW EQU CYREG_PRT6_SLW +SCSI_In_DBx__4__AG EQU CYREG_PRT12_AG +SCSI_In_DBx__4__BIE EQU CYREG_PRT12_BIE +SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_In_DBx__4__BYP EQU CYREG_PRT12_BYP +SCSI_In_DBx__4__DM0 EQU CYREG_PRT12_DM0 +SCSI_In_DBx__4__DM1 EQU CYREG_PRT12_DM1 +SCSI_In_DBx__4__DM2 EQU CYREG_PRT12_DM2 +SCSI_In_DBx__4__DR EQU CYREG_PRT12_DR +SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_In_DBx__4__MASK EQU 0x20 +SCSI_In_DBx__4__PC EQU CYREG_PRT12_PC5 +SCSI_In_DBx__4__PORT EQU 12 +SCSI_In_DBx__4__PRT EQU CYREG_PRT12_PRT +SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_In_DBx__4__PS EQU CYREG_PRT12_PS +SCSI_In_DBx__4__SHIFT EQU 5 +SCSI_In_DBx__4__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_In_DBx__4__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_In_DBx__4__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_In_DBx__4__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_In_DBx__4__SLW EQU CYREG_PRT12_SLW +SCSI_In_DBx__5__AG EQU CYREG_PRT12_AG +SCSI_In_DBx__5__BIE EQU CYREG_PRT12_BIE +SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_In_DBx__5__BYP EQU CYREG_PRT12_BYP +SCSI_In_DBx__5__DM0 EQU CYREG_PRT12_DM0 +SCSI_In_DBx__5__DM1 EQU CYREG_PRT12_DM1 +SCSI_In_DBx__5__DM2 EQU CYREG_PRT12_DM2 +SCSI_In_DBx__5__DR EQU CYREG_PRT12_DR +SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_In_DBx__5__MASK EQU 0x10 +SCSI_In_DBx__5__PC EQU CYREG_PRT12_PC4 +SCSI_In_DBx__5__PORT EQU 12 +SCSI_In_DBx__5__PRT EQU CYREG_PRT12_PRT +SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_In_DBx__5__PS EQU CYREG_PRT12_PS +SCSI_In_DBx__5__SHIFT EQU 4 +SCSI_In_DBx__5__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_In_DBx__5__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_In_DBx__5__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_In_DBx__5__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_In_DBx__5__SLW EQU CYREG_PRT12_SLW +SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG +SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX +SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE +SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP +SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL +SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0 +SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1 +SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2 +SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR +SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_In_DBx__6__MASK EQU 0x20 +SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC5 +SCSI_In_DBx__6__PORT EQU 2 +SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT +SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS +SCSI_In_DBx__6__SHIFT EQU 5 +SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW +SCSI_In_DBx__7__AG EQU CYREG_PRT2_AG +SCSI_In_DBx__7__AMUX EQU CYREG_PRT2_AMUX +SCSI_In_DBx__7__BIE EQU CYREG_PRT2_BIE +SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_In_DBx__7__BYP EQU CYREG_PRT2_BYP +SCSI_In_DBx__7__CTL EQU CYREG_PRT2_CTL +SCSI_In_DBx__7__DM0 EQU CYREG_PRT2_DM0 +SCSI_In_DBx__7__DM1 EQU CYREG_PRT2_DM1 +SCSI_In_DBx__7__DM2 EQU CYREG_PRT2_DM2 +SCSI_In_DBx__7__DR EQU CYREG_PRT2_DR +SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_In_DBx__7__MASK EQU 0x10 +SCSI_In_DBx__7__PC EQU CYREG_PRT2_PC4 +SCSI_In_DBx__7__PORT EQU 2 +SCSI_In_DBx__7__PRT EQU CYREG_PRT2_PRT +SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_In_DBx__7__PS EQU CYREG_PRT2_PS +SCSI_In_DBx__7__SHIFT EQU 4 +SCSI_In_DBx__7__SLW EQU CYREG_PRT2_SLW +SCSI_In_DBx__DB0__AG EQU CYREG_PRT5_AG +SCSI_In_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX +SCSI_In_DBx__DB0__BIE EQU CYREG_PRT5_BIE +SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_In_DBx__DB0__BYP EQU CYREG_PRT5_BYP +SCSI_In_DBx__DB0__CTL EQU CYREG_PRT5_CTL +SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT5_DM0 +SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT5_DM1 +SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT5_DM2 +SCSI_In_DBx__DB0__DR EQU CYREG_PRT5_DR +SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_In_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_In_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_In_DBx__DB0__MASK EQU 0x08 +SCSI_In_DBx__DB0__PC EQU CYREG_PRT5_PC3 +SCSI_In_DBx__DB0__PORT EQU 5 +SCSI_In_DBx__DB0__PRT EQU CYREG_PRT5_PRT +SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_In_DBx__DB0__PS EQU CYREG_PRT5_PS +SCSI_In_DBx__DB0__SHIFT EQU 3 +SCSI_In_DBx__DB0__SLW EQU CYREG_PRT5_SLW +SCSI_In_DBx__DB1__AG EQU CYREG_PRT5_AG +SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX +SCSI_In_DBx__DB1__BIE EQU CYREG_PRT5_BIE +SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_In_DBx__DB1__BYP EQU CYREG_PRT5_BYP +SCSI_In_DBx__DB1__CTL EQU CYREG_PRT5_CTL +SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT5_DM0 +SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT5_DM1 +SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT5_DM2 +SCSI_In_DBx__DB1__DR EQU CYREG_PRT5_DR +SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_In_DBx__DB1__MASK EQU 0x04 +SCSI_In_DBx__DB1__PC EQU CYREG_PRT5_PC2 +SCSI_In_DBx__DB1__PORT EQU 5 +SCSI_In_DBx__DB1__PRT EQU CYREG_PRT5_PRT +SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_In_DBx__DB1__PS EQU CYREG_PRT5_PS +SCSI_In_DBx__DB1__SHIFT EQU 2 +SCSI_In_DBx__DB1__SLW EQU CYREG_PRT5_SLW +SCSI_In_DBx__DB2__AG EQU CYREG_PRT6_AG +SCSI_In_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX +SCSI_In_DBx__DB2__BIE EQU CYREG_PRT6_BIE +SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In_DBx__DB2__BYP EQU CYREG_PRT6_BYP +SCSI_In_DBx__DB2__CTL EQU CYREG_PRT6_CTL +SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT6_DM0 +SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT6_DM1 +SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT6_DM2 +SCSI_In_DBx__DB2__DR EQU CYREG_PRT6_DR +SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In_DBx__DB2__MASK EQU 0x80 +SCSI_In_DBx__DB2__PC EQU CYREG_PRT6_PC7 +SCSI_In_DBx__DB2__PORT EQU 6 +SCSI_In_DBx__DB2__PRT EQU CYREG_PRT6_PRT +SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In_DBx__DB2__PS EQU CYREG_PRT6_PS +SCSI_In_DBx__DB2__SHIFT EQU 7 +SCSI_In_DBx__DB2__SLW EQU CYREG_PRT6_SLW +SCSI_In_DBx__DB3__AG EQU CYREG_PRT6_AG +SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX +SCSI_In_DBx__DB3__BIE EQU CYREG_PRT6_BIE +SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In_DBx__DB3__BYP EQU CYREG_PRT6_BYP +SCSI_In_DBx__DB3__CTL EQU CYREG_PRT6_CTL +SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT6_DM0 +SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT6_DM1 +SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT6_DM2 +SCSI_In_DBx__DB3__DR EQU CYREG_PRT6_DR +SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In_DBx__DB3__MASK EQU 0x40 +SCSI_In_DBx__DB3__PC EQU CYREG_PRT6_PC6 +SCSI_In_DBx__DB3__PORT EQU 6 +SCSI_In_DBx__DB3__PRT EQU CYREG_PRT6_PRT +SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In_DBx__DB3__PS EQU CYREG_PRT6_PS +SCSI_In_DBx__DB3__SHIFT EQU 6 +SCSI_In_DBx__DB3__SLW EQU CYREG_PRT6_SLW +SCSI_In_DBx__DB4__AG EQU CYREG_PRT12_AG +SCSI_In_DBx__DB4__BIE EQU CYREG_PRT12_BIE +SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_In_DBx__DB4__BYP EQU CYREG_PRT12_BYP +SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT12_DM0 +SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT12_DM1 +SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT12_DM2 +SCSI_In_DBx__DB4__DR EQU CYREG_PRT12_DR +SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_In_DBx__DB4__MASK EQU 0x20 +SCSI_In_DBx__DB4__PC EQU CYREG_PRT12_PC5 +SCSI_In_DBx__DB4__PORT EQU 12 +SCSI_In_DBx__DB4__PRT EQU CYREG_PRT12_PRT +SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_In_DBx__DB4__PS EQU CYREG_PRT12_PS +SCSI_In_DBx__DB4__SHIFT EQU 5 +SCSI_In_DBx__DB4__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_In_DBx__DB4__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_In_DBx__DB4__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_In_DBx__DB4__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_In_DBx__DB4__SLW EQU CYREG_PRT12_SLW +SCSI_In_DBx__DB5__AG EQU CYREG_PRT12_AG +SCSI_In_DBx__DB5__BIE EQU CYREG_PRT12_BIE +SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_In_DBx__DB5__BYP EQU CYREG_PRT12_BYP +SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT12_DM0 +SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT12_DM1 +SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT12_DM2 +SCSI_In_DBx__DB5__DR EQU CYREG_PRT12_DR +SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_In_DBx__DB5__MASK EQU 0x10 +SCSI_In_DBx__DB5__PC EQU CYREG_PRT12_PC4 +SCSI_In_DBx__DB5__PORT EQU 12 +SCSI_In_DBx__DB5__PRT EQU CYREG_PRT12_PRT +SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_In_DBx__DB5__PS EQU CYREG_PRT12_PS +SCSI_In_DBx__DB5__SHIFT EQU 4 +SCSI_In_DBx__DB5__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_In_DBx__DB5__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_In_DBx__DB5__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_In_DBx__DB5__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_In_DBx__DB5__SLW EQU CYREG_PRT12_SLW +SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG +SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX +SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE +SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP +SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL +SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0 +SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1 +SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2 +SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR +SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_In_DBx__DB6__MASK EQU 0x20 +SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC5 +SCSI_In_DBx__DB6__PORT EQU 2 +SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT +SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS +SCSI_In_DBx__DB6__SHIFT EQU 5 +SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW +SCSI_In_DBx__DB7__AG EQU CYREG_PRT2_AG +SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX +SCSI_In_DBx__DB7__BIE EQU CYREG_PRT2_BIE +SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_In_DBx__DB7__BYP EQU CYREG_PRT2_BYP +SCSI_In_DBx__DB7__CTL EQU CYREG_PRT2_CTL +SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT2_DM0 +SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT2_DM1 +SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT2_DM2 +SCSI_In_DBx__DB7__DR EQU CYREG_PRT2_DR +SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_In_DBx__DB7__MASK EQU 0x10 +SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC4 +SCSI_In_DBx__DB7__PORT EQU 2 +SCSI_In_DBx__DB7__PRT EQU CYREG_PRT2_PRT +SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS +SCSI_In_DBx__DB7__SHIFT EQU 4 +SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW + +/* SD_Data_Clk */ +SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0 +SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1 +SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2 +SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07 +SD_Data_Clk__INDEX EQU 0x00 +SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +SD_Data_Clk__PM_ACT_MSK EQU 0x01 +SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +SD_Data_Clk__PM_STBY_MSK EQU 0x01 + +/* SD_Init_Clk */ +SD_Init_Clk__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 +SD_Init_Clk__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 +SD_Init_Clk__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 +SD_Init_Clk__CFG2_SRC_SEL_MASK EQU 0x07 +SD_Init_Clk__INDEX EQU 0x01 +SD_Init_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +SD_Init_Clk__PM_ACT_MSK EQU 0x02 +SD_Init_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +SD_Init_Clk__PM_STBY_MSK EQU 0x02 + +/* scsiTarget */ +scsiTarget_StatusReg__0__MASK EQU 0x01 +scsiTarget_StatusReg__0__POS EQU 0 +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST +scsiTarget_StatusReg__1__MASK EQU 0x02 +scsiTarget_StatusReg__1__POS EQU 1 +scsiTarget_StatusReg__2__MASK EQU 0x04 +scsiTarget_StatusReg__2__POS EQU 2 +scsiTarget_StatusReg__3__MASK EQU 0x08 +scsiTarget_StatusReg__3__POS EQU 3 +scsiTarget_StatusReg__MASK EQU 0x0F +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB13_MSK +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB13_ST +scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL +scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB10_11_ST +scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB10_MSK +scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL +scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB10_ST_CTL +scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB10_ST_CTL +scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB10_ST +scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL +scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL +scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL +scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL +scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL +scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK +scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK +scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL +scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB10_CTL +scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL +scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB10_CTL +scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL +scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB10_MSK +scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB10_11_A0 +scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB10_11_A1 +scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB10_11_D0 +scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB10_11_D1 +scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL +scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB10_11_F0 +scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB10_11_F1 +scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB10_A0_A1 +scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB10_A0 +scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB10_A1 +scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB10_D0_D1 +scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB10_D0 +scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB10_D1 +scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL +scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB10_F0_F1 +scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB10_F0 +scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB10_F1 +scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL + +/* SD_Clk_Ctl */ +SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 +SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0 +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK +SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL +SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL +SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL +SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL +SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01 +SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK +SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL + +/* USBFS_ep_0 */ +USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_0__INTC_MASK EQU 0x1000000 +USBFS_ep_0__INTC_NUMBER EQU 24 +USBFS_ep_0__INTC_PRIOR_NUM EQU 7 +USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24 +USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* USBFS_ep_1 */ +USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_1__INTC_MASK EQU 0x01 +USBFS_ep_1__INTC_NUMBER EQU 0 +USBFS_ep_1__INTC_PRIOR_NUM EQU 7 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 +USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* USBFS_ep_2 */ +USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_2__INTC_MASK EQU 0x02 +USBFS_ep_2__INTC_NUMBER EQU 1 +USBFS_ep_2__INTC_PRIOR_NUM EQU 7 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 +USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* USBFS_USB */ +USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG +USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG +USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN +USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR +USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG +USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN +USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR +USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG +USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN +USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR +USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG +USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN +USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR +USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG +USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN +USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR +USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG +USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN +USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR +USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG +USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN +USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR +USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG +USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN +USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR +USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN +USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR +USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR +USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA +USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB +USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA +USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB +USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR +USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA +USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB +USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA +USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB +USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR +USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA +USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB +USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA +USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB +USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR +USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA +USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB +USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA +USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB +USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR +USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA +USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB +USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA +USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB +USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR +USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA +USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB +USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA +USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB +USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR +USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA +USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB +USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA +USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB +USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR +USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA +USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB +USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA +USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB +USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE +USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT +USBFS_USB__CR0 EQU CYREG_USB_CR0 +USBFS_USB__CR1 EQU CYREG_USB_CR1 +USBFS_USB__CWA EQU CYREG_USB_CWA +USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB +USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES +USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB +USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG +USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT +USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR +USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0 +USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1 +USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2 +USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3 +USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4 +USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5 +USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6 +USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7 +USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE +USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE +USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE +USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5 +USBFS_USB__PM_ACT_MSK EQU 0x01 +USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5 +USBFS_USB__PM_STBY_MSK EQU 0x01 +USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0 +USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1 +USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0 +USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0 +USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1 +USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0 +USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0 +USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1 +USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0 +USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0 +USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1 +USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0 +USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0 +USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1 +USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0 +USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0 +USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1 +USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0 +USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0 +USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1 +USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0 +USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0 +USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1 +USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0 +USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN +USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR +USBFS_USB__SOF0 EQU CYREG_USB_SOF0 +USBFS_USB__SOF1 EQU CYREG_USB_SOF1 +USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 +USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 +USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN + +/* SCSI_ATN */ +SCSI_ATN__0__MASK EQU 0x01 +SCSI_ATN__0__PC EQU CYREG_PRT2_PC0 +SCSI_ATN__0__PORT EQU 2 +SCSI_ATN__0__SHIFT EQU 0 +SCSI_ATN__AG EQU CYREG_PRT2_AG +SCSI_ATN__AMUX EQU CYREG_PRT2_AMUX +SCSI_ATN__BIE EQU CYREG_PRT2_BIE +SCSI_ATN__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_ATN__BYP EQU CYREG_PRT2_BYP +SCSI_ATN__CTL EQU CYREG_PRT2_CTL +SCSI_ATN__DM0 EQU CYREG_PRT2_DM0 +SCSI_ATN__DM1 EQU CYREG_PRT2_DM1 +SCSI_ATN__DM2 EQU CYREG_PRT2_DM2 +SCSI_ATN__DR EQU CYREG_PRT2_DR +SCSI_ATN__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_ATN__INT__MASK EQU 0x01 +SCSI_ATN__INT__PC EQU CYREG_PRT2_PC0 +SCSI_ATN__INT__PORT EQU 2 +SCSI_ATN__INT__SHIFT EQU 0 +SCSI_ATN__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_ATN__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_ATN__MASK EQU 0x01 +SCSI_ATN__PORT EQU 2 +SCSI_ATN__PRT EQU CYREG_PRT2_PRT +SCSI_ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_ATN__PS EQU CYREG_PRT2_PS +SCSI_ATN__SHIFT EQU 0 +SCSI_ATN__SLW EQU CYREG_PRT2_SLW + +/* SCSI_Out */ +SCSI_Out__0__AG EQU CYREG_PRT15_AG +SCSI_Out__0__AMUX EQU CYREG_PRT15_AMUX +SCSI_Out__0__BIE EQU CYREG_PRT15_BIE +SCSI_Out__0__BIT_MASK EQU CYREG_PRT15_BIT_MASK +SCSI_Out__0__BYP EQU CYREG_PRT15_BYP +SCSI_Out__0__CTL EQU CYREG_PRT15_CTL +SCSI_Out__0__DM0 EQU CYREG_PRT15_DM0 +SCSI_Out__0__DM1 EQU CYREG_PRT15_DM1 +SCSI_Out__0__DM2 EQU CYREG_PRT15_DM2 +SCSI_Out__0__DR EQU CYREG_PRT15_DR +SCSI_Out__0__INP_DIS EQU CYREG_PRT15_INP_DIS +SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +SCSI_Out__0__LCD_EN EQU CYREG_PRT15_LCD_EN +SCSI_Out__0__MASK EQU 0x20 +SCSI_Out__0__PC EQU CYREG_IO_PC_PRT15_PC5 +SCSI_Out__0__PORT EQU 15 +SCSI_Out__0__PRT EQU CYREG_PRT15_PRT +SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +SCSI_Out__0__PS EQU CYREG_PRT15_PS +SCSI_Out__0__SHIFT EQU 5 +SCSI_Out__0__SLW EQU CYREG_PRT15_SLW +SCSI_Out__1__AG EQU CYREG_PRT15_AG +SCSI_Out__1__AMUX EQU CYREG_PRT15_AMUX +SCSI_Out__1__BIE EQU CYREG_PRT15_BIE +SCSI_Out__1__BIT_MASK EQU CYREG_PRT15_BIT_MASK +SCSI_Out__1__BYP EQU CYREG_PRT15_BYP +SCSI_Out__1__CTL EQU CYREG_PRT15_CTL +SCSI_Out__1__DM0 EQU CYREG_PRT15_DM0 +SCSI_Out__1__DM1 EQU CYREG_PRT15_DM1 +SCSI_Out__1__DM2 EQU CYREG_PRT15_DM2 +SCSI_Out__1__DR EQU CYREG_PRT15_DR +SCSI_Out__1__INP_DIS EQU CYREG_PRT15_INP_DIS +SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +SCSI_Out__1__LCD_EN EQU CYREG_PRT15_LCD_EN +SCSI_Out__1__MASK EQU 0x10 +SCSI_Out__1__PC EQU CYREG_IO_PC_PRT15_PC4 +SCSI_Out__1__PORT EQU 15 +SCSI_Out__1__PRT EQU CYREG_PRT15_PRT +SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +SCSI_Out__1__PS EQU CYREG_PRT15_PS +SCSI_Out__1__SHIFT EQU 4 +SCSI_Out__1__SLW EQU CYREG_PRT15_SLW +SCSI_Out__2__AG EQU CYREG_PRT6_AG +SCSI_Out__2__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out__2__BIE EQU CYREG_PRT6_BIE +SCSI_Out__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out__2__BYP EQU CYREG_PRT6_BYP +SCSI_Out__2__CTL EQU CYREG_PRT6_CTL +SCSI_Out__2__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out__2__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out__2__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out__2__DR EQU CYREG_PRT6_DR +SCSI_Out__2__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out__2__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out__2__MASK EQU 0x02 +SCSI_Out__2__PC EQU CYREG_PRT6_PC1 +SCSI_Out__2__PORT EQU 6 +SCSI_Out__2__PRT EQU CYREG_PRT6_PRT +SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out__2__PS EQU CYREG_PRT6_PS +SCSI_Out__2__SHIFT EQU 1 +SCSI_Out__2__SLW EQU CYREG_PRT6_SLW +SCSI_Out__3__AG EQU CYREG_PRT6_AG +SCSI_Out__3__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out__3__BIE EQU CYREG_PRT6_BIE +SCSI_Out__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out__3__BYP EQU CYREG_PRT6_BYP +SCSI_Out__3__CTL EQU CYREG_PRT6_CTL +SCSI_Out__3__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out__3__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out__3__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out__3__DR EQU CYREG_PRT6_DR +SCSI_Out__3__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out__3__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out__3__MASK EQU 0x01 +SCSI_Out__3__PC EQU CYREG_PRT6_PC0 +SCSI_Out__3__PORT EQU 6 +SCSI_Out__3__PRT EQU CYREG_PRT6_PRT +SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out__3__PS EQU CYREG_PRT6_PS +SCSI_Out__3__SHIFT EQU 0 +SCSI_Out__3__SLW EQU CYREG_PRT6_SLW +SCSI_Out__4__AG EQU CYREG_PRT4_AG +SCSI_Out__4__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__4__BIE EQU CYREG_PRT4_BIE +SCSI_Out__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__4__BYP EQU CYREG_PRT4_BYP +SCSI_Out__4__CTL EQU CYREG_PRT4_CTL +SCSI_Out__4__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__4__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__4__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__4__DR EQU CYREG_PRT4_DR +SCSI_Out__4__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__4__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__4__MASK EQU 0x20 +SCSI_Out__4__PC EQU CYREG_PRT4_PC5 +SCSI_Out__4__PORT EQU 4 +SCSI_Out__4__PRT EQU CYREG_PRT4_PRT +SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__4__PS EQU CYREG_PRT4_PS +SCSI_Out__4__SHIFT EQU 5 +SCSI_Out__4__SLW EQU CYREG_PRT4_SLW +SCSI_Out__5__AG EQU CYREG_PRT4_AG +SCSI_Out__5__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__5__BIE EQU CYREG_PRT4_BIE +SCSI_Out__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__5__BYP EQU CYREG_PRT4_BYP +SCSI_Out__5__CTL EQU CYREG_PRT4_CTL +SCSI_Out__5__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__5__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__5__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__5__DR EQU CYREG_PRT4_DR +SCSI_Out__5__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__5__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__5__MASK EQU 0x10 +SCSI_Out__5__PC EQU CYREG_PRT4_PC4 +SCSI_Out__5__PORT EQU 4 +SCSI_Out__5__PRT EQU CYREG_PRT4_PRT +SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__5__PS EQU CYREG_PRT4_PS +SCSI_Out__5__SHIFT EQU 4 +SCSI_Out__5__SLW EQU CYREG_PRT4_SLW +SCSI_Out__6__AG EQU CYREG_PRT0_AG +SCSI_Out__6__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__6__BIE EQU CYREG_PRT0_BIE +SCSI_Out__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__6__BYP EQU CYREG_PRT0_BYP +SCSI_Out__6__CTL EQU CYREG_PRT0_CTL +SCSI_Out__6__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__6__DR EQU CYREG_PRT0_DR +SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__6__MASK EQU 0x80 +SCSI_Out__6__PC EQU CYREG_PRT0_PC7 +SCSI_Out__6__PORT EQU 0 +SCSI_Out__6__PRT EQU CYREG_PRT0_PRT +SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__6__PS EQU CYREG_PRT0_PS +SCSI_Out__6__SHIFT EQU 7 +SCSI_Out__6__SLW EQU CYREG_PRT0_SLW +SCSI_Out__7__AG EQU CYREG_PRT0_AG +SCSI_Out__7__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__7__BIE EQU CYREG_PRT0_BIE +SCSI_Out__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__7__BYP EQU CYREG_PRT0_BYP +SCSI_Out__7__CTL EQU CYREG_PRT0_CTL +SCSI_Out__7__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__7__DR EQU CYREG_PRT0_DR +SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__7__MASK EQU 0x40 +SCSI_Out__7__PC EQU CYREG_PRT0_PC6 +SCSI_Out__7__PORT EQU 0 +SCSI_Out__7__PRT EQU CYREG_PRT0_PRT +SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__7__PS EQU CYREG_PRT0_PS +SCSI_Out__7__SHIFT EQU 6 +SCSI_Out__7__SLW EQU CYREG_PRT0_SLW +SCSI_Out__8__AG EQU CYREG_PRT0_AG +SCSI_Out__8__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__8__BIE EQU CYREG_PRT0_BIE +SCSI_Out__8__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__8__BYP EQU CYREG_PRT0_BYP +SCSI_Out__8__CTL EQU CYREG_PRT0_CTL +SCSI_Out__8__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__8__DR EQU CYREG_PRT0_DR +SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__8__MASK EQU 0x08 +SCSI_Out__8__PC EQU CYREG_PRT0_PC3 +SCSI_Out__8__PORT EQU 0 +SCSI_Out__8__PRT EQU CYREG_PRT0_PRT +SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__8__PS EQU CYREG_PRT0_PS +SCSI_Out__8__SHIFT EQU 3 +SCSI_Out__8__SLW EQU CYREG_PRT0_SLW +SCSI_Out__9__AG EQU CYREG_PRT0_AG +SCSI_Out__9__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__9__BIE EQU CYREG_PRT0_BIE +SCSI_Out__9__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__9__BYP EQU CYREG_PRT0_BYP +SCSI_Out__9__CTL EQU CYREG_PRT0_CTL +SCSI_Out__9__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__9__DR EQU CYREG_PRT0_DR +SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__9__MASK EQU 0x04 +SCSI_Out__9__PC EQU CYREG_PRT0_PC2 +SCSI_Out__9__PORT EQU 0 +SCSI_Out__9__PRT EQU CYREG_PRT0_PRT +SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__9__PS EQU CYREG_PRT0_PS +SCSI_Out__9__SHIFT EQU 2 +SCSI_Out__9__SLW EQU CYREG_PRT0_SLW +SCSI_Out__ACK__AG EQU CYREG_PRT6_AG +SCSI_Out__ACK__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out__ACK__BIE EQU CYREG_PRT6_BIE +SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out__ACK__BYP EQU CYREG_PRT6_BYP +SCSI_Out__ACK__CTL EQU CYREG_PRT6_CTL +SCSI_Out__ACK__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out__ACK__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out__ACK__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out__ACK__DR EQU CYREG_PRT6_DR +SCSI_Out__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out__ACK__MASK EQU 0x01 +SCSI_Out__ACK__PC EQU CYREG_PRT6_PC0 +SCSI_Out__ACK__PORT EQU 6 +SCSI_Out__ACK__PRT EQU CYREG_PRT6_PRT +SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out__ACK__PS EQU CYREG_PRT6_PS +SCSI_Out__ACK__SHIFT EQU 0 +SCSI_Out__ACK__SLW EQU CYREG_PRT6_SLW +SCSI_Out__ATN__AG EQU CYREG_PRT15_AG +SCSI_Out__ATN__AMUX EQU CYREG_PRT15_AMUX +SCSI_Out__ATN__BIE EQU CYREG_PRT15_BIE +SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT15_BIT_MASK +SCSI_Out__ATN__BYP EQU CYREG_PRT15_BYP +SCSI_Out__ATN__CTL EQU CYREG_PRT15_CTL +SCSI_Out__ATN__DM0 EQU CYREG_PRT15_DM0 +SCSI_Out__ATN__DM1 EQU CYREG_PRT15_DM1 +SCSI_Out__ATN__DM2 EQU CYREG_PRT15_DM2 +SCSI_Out__ATN__DR EQU CYREG_PRT15_DR +SCSI_Out__ATN__INP_DIS EQU CYREG_PRT15_INP_DIS +SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +SCSI_Out__ATN__LCD_EN EQU CYREG_PRT15_LCD_EN +SCSI_Out__ATN__MASK EQU 0x10 +SCSI_Out__ATN__PC EQU CYREG_IO_PC_PRT15_PC4 +SCSI_Out__ATN__PORT EQU 15 +SCSI_Out__ATN__PRT EQU CYREG_PRT15_PRT +SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +SCSI_Out__ATN__PS EQU CYREG_PRT15_PS +SCSI_Out__ATN__SHIFT EQU 4 +SCSI_Out__ATN__SLW EQU CYREG_PRT15_SLW +SCSI_Out__BSY__AG EQU CYREG_PRT6_AG +SCSI_Out__BSY__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out__BSY__BIE EQU CYREG_PRT6_BIE +SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out__BSY__BYP EQU CYREG_PRT6_BYP +SCSI_Out__BSY__CTL EQU CYREG_PRT6_CTL +SCSI_Out__BSY__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out__BSY__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out__BSY__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out__BSY__DR EQU CYREG_PRT6_DR +SCSI_Out__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out__BSY__MASK EQU 0x02 +SCSI_Out__BSY__PC EQU CYREG_PRT6_PC1 +SCSI_Out__BSY__PORT EQU 6 +SCSI_Out__BSY__PRT EQU CYREG_PRT6_PRT +SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out__BSY__PS EQU CYREG_PRT6_PS +SCSI_Out__BSY__SHIFT EQU 1 +SCSI_Out__BSY__SLW EQU CYREG_PRT6_SLW +SCSI_Out__CD__AG EQU CYREG_PRT0_AG +SCSI_Out__CD__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__CD__BIE EQU CYREG_PRT0_BIE +SCSI_Out__CD__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__CD__BYP EQU CYREG_PRT0_BYP +SCSI_Out__CD__CTL EQU CYREG_PRT0_CTL +SCSI_Out__CD__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__CD__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__CD__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__CD__DR EQU CYREG_PRT0_DR +SCSI_Out__CD__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__CD__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__CD__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__CD__MASK EQU 0x40 +SCSI_Out__CD__PC EQU CYREG_PRT0_PC6 +SCSI_Out__CD__PORT EQU 0 +SCSI_Out__CD__PRT EQU CYREG_PRT0_PRT +SCSI_Out__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__CD__PS EQU CYREG_PRT0_PS +SCSI_Out__CD__SHIFT EQU 6 +SCSI_Out__CD__SLW EQU CYREG_PRT0_SLW +SCSI_Out__DBP_raw__AG EQU CYREG_PRT15_AG +SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT15_AMUX +SCSI_Out__DBP_raw__BIE EQU CYREG_PRT15_BIE +SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT15_BIT_MASK +SCSI_Out__DBP_raw__BYP EQU CYREG_PRT15_BYP +SCSI_Out__DBP_raw__CTL EQU CYREG_PRT15_CTL +SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT15_DM0 +SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT15_DM1 +SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT15_DM2 +SCSI_Out__DBP_raw__DR EQU CYREG_PRT15_DR +SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT15_INP_DIS +SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT15_LCD_EN +SCSI_Out__DBP_raw__MASK EQU 0x20 +SCSI_Out__DBP_raw__PC EQU CYREG_IO_PC_PRT15_PC5 +SCSI_Out__DBP_raw__PORT EQU 15 +SCSI_Out__DBP_raw__PRT EQU CYREG_PRT15_PRT +SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +SCSI_Out__DBP_raw__PS EQU CYREG_PRT15_PS +SCSI_Out__DBP_raw__SHIFT EQU 5 +SCSI_Out__DBP_raw__SLW EQU CYREG_PRT15_SLW +SCSI_Out__IO_raw__AG EQU CYREG_PRT0_AG +SCSI_Out__IO_raw__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__IO_raw__BIE EQU CYREG_PRT0_BIE +SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__IO_raw__BYP EQU CYREG_PRT0_BYP +SCSI_Out__IO_raw__CTL EQU CYREG_PRT0_CTL +SCSI_Out__IO_raw__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR +SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__IO_raw__MASK EQU 0x04 +SCSI_Out__IO_raw__PC EQU CYREG_PRT0_PC2 +SCSI_Out__IO_raw__PORT EQU 0 +SCSI_Out__IO_raw__PRT EQU CYREG_PRT0_PRT +SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS +SCSI_Out__IO_raw__SHIFT EQU 2 +SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW +SCSI_Out__MSG__AG EQU CYREG_PRT4_AG +SCSI_Out__MSG__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__MSG__BIE EQU CYREG_PRT4_BIE +SCSI_Out__MSG__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__MSG__BYP EQU CYREG_PRT4_BYP +SCSI_Out__MSG__CTL EQU CYREG_PRT4_CTL +SCSI_Out__MSG__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__MSG__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__MSG__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__MSG__DR EQU CYREG_PRT4_DR +SCSI_Out__MSG__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__MSG__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__MSG__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__MSG__MASK EQU 0x10 +SCSI_Out__MSG__PC EQU CYREG_PRT4_PC4 +SCSI_Out__MSG__PORT EQU 4 +SCSI_Out__MSG__PRT EQU CYREG_PRT4_PRT +SCSI_Out__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__MSG__PS EQU CYREG_PRT4_PS +SCSI_Out__MSG__SHIFT EQU 4 +SCSI_Out__MSG__SLW EQU CYREG_PRT4_SLW +SCSI_Out__REQ__AG EQU CYREG_PRT0_AG +SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE +SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__REQ__BYP EQU CYREG_PRT0_BYP +SCSI_Out__REQ__CTL EQU CYREG_PRT0_CTL +SCSI_Out__REQ__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__REQ__DR EQU CYREG_PRT0_DR +SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__REQ__MASK EQU 0x08 +SCSI_Out__REQ__PC EQU CYREG_PRT0_PC3 +SCSI_Out__REQ__PORT EQU 0 +SCSI_Out__REQ__PRT EQU CYREG_PRT0_PRT +SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__REQ__PS EQU CYREG_PRT0_PS +SCSI_Out__REQ__SHIFT EQU 3 +SCSI_Out__REQ__SLW EQU CYREG_PRT0_SLW +SCSI_Out__RST__AG EQU CYREG_PRT4_AG +SCSI_Out__RST__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__RST__BIE EQU CYREG_PRT4_BIE +SCSI_Out__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__RST__BYP EQU CYREG_PRT4_BYP +SCSI_Out__RST__CTL EQU CYREG_PRT4_CTL +SCSI_Out__RST__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__RST__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__RST__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__RST__DR EQU CYREG_PRT4_DR +SCSI_Out__RST__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__RST__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__RST__MASK EQU 0x20 +SCSI_Out__RST__PC EQU CYREG_PRT4_PC5 +SCSI_Out__RST__PORT EQU 4 +SCSI_Out__RST__PRT EQU CYREG_PRT4_PRT +SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__RST__PS EQU CYREG_PRT4_PS +SCSI_Out__RST__SHIFT EQU 5 +SCSI_Out__RST__SLW EQU CYREG_PRT4_SLW +SCSI_Out__SEL__AG EQU CYREG_PRT0_AG +SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE +SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP +SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL +SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__SEL__DR EQU CYREG_PRT0_DR +SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__SEL__MASK EQU 0x80 +SCSI_Out__SEL__PC EQU CYREG_PRT0_PC7 +SCSI_Out__SEL__PORT EQU 0 +SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT +SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__SEL__PS EQU CYREG_PRT0_PS +SCSI_Out__SEL__SHIFT EQU 7 +SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW + +/* SCSI_RST */ +SCSI_RST__0__MASK EQU 0x80 +SCSI_RST__0__PC EQU CYREG_PRT4_PC7 +SCSI_RST__0__PORT EQU 4 +SCSI_RST__0__SHIFT EQU 7 +SCSI_RST__AG EQU CYREG_PRT4_AG +SCSI_RST__AMUX EQU CYREG_PRT4_AMUX +SCSI_RST__BIE EQU CYREG_PRT4_BIE +SCSI_RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_RST__BYP EQU CYREG_PRT4_BYP +SCSI_RST__CTL EQU CYREG_PRT4_CTL +SCSI_RST__DM0 EQU CYREG_PRT4_DM0 +SCSI_RST__DM1 EQU CYREG_PRT4_DM1 +SCSI_RST__DM2 EQU CYREG_PRT4_DM2 +SCSI_RST__DR EQU CYREG_PRT4_DR +SCSI_RST__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_RST__INTSTAT EQU CYREG_PICU4_INTSTAT +SCSI_RST__INT__MASK EQU 0x80 +SCSI_RST__INT__PC EQU CYREG_PRT4_PC7 +SCSI_RST__INT__PORT EQU 4 +SCSI_RST__INT__SHIFT EQU 7 +SCSI_RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_RST__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_RST__MASK EQU 0x80 +SCSI_RST__PORT EQU 4 +SCSI_RST__PRT EQU CYREG_PRT4_PRT +SCSI_RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_RST__PS EQU CYREG_PRT4_PS +SCSI_RST__SHIFT EQU 7 +SCSI_RST__SLW EQU CYREG_PRT4_SLW +SCSI_RST__SNAP EQU CYREG_PICU4_SNAP + +/* USBFS_Dm */ +USBFS_Dm__0__MASK EQU 0x80 +USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 +USBFS_Dm__0__PORT EQU 15 +USBFS_Dm__0__SHIFT EQU 7 +USBFS_Dm__AG EQU CYREG_PRT15_AG +USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dm__BIE EQU CYREG_PRT15_BIE +USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dm__BYP EQU CYREG_PRT15_BYP +USBFS_Dm__CTL EQU CYREG_PRT15_CTL +USBFS_Dm__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dm__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dm__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dm__DR EQU CYREG_PRT15_DR +USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dm__MASK EQU 0x80 +USBFS_Dm__PORT EQU 15 +USBFS_Dm__PRT EQU CYREG_PRT15_PRT +USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dm__PS EQU CYREG_PRT15_PS +USBFS_Dm__SHIFT EQU 7 +USBFS_Dm__SLW EQU CYREG_PRT15_SLW + +/* USBFS_Dp */ +USBFS_Dp__0__MASK EQU 0x40 +USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0 +USBFS_Dp__0__PORT EQU 15 +USBFS_Dp__0__SHIFT EQU 6 +USBFS_Dp__AG EQU CYREG_PRT15_AG +USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dp__BIE EQU CYREG_PRT15_BIE +USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dp__BYP EQU CYREG_PRT15_BYP +USBFS_Dp__CTL EQU CYREG_PRT15_CTL +USBFS_Dp__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dp__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dp__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dp__DR EQU CYREG_PRT15_DR +USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT +USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dp__MASK EQU 0x40 +USBFS_Dp__PORT EQU 15 +USBFS_Dp__PRT EQU CYREG_PRT15_PRT +USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dp__PS EQU CYREG_PRT15_PS +USBFS_Dp__SHIFT EQU 6 +USBFS_Dp__SLW EQU CYREG_PRT15_SLW +USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15 + +/* SCSI_In */ +SCSI_In__0__AG EQU CYREG_PRT2_AG +SCSI_In__0__AMUX EQU CYREG_PRT2_AMUX +SCSI_In__0__BIE EQU CYREG_PRT2_BIE +SCSI_In__0__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_In__0__BYP EQU CYREG_PRT2_BYP +SCSI_In__0__CTL EQU CYREG_PRT2_CTL +SCSI_In__0__DM0 EQU CYREG_PRT2_DM0 +SCSI_In__0__DM1 EQU CYREG_PRT2_DM1 +SCSI_In__0__DM2 EQU CYREG_PRT2_DM2 +SCSI_In__0__DR EQU CYREG_PRT2_DR +SCSI_In__0__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_In__0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_In__0__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_In__0__MASK EQU 0x02 +SCSI_In__0__PC EQU CYREG_PRT2_PC1 +SCSI_In__0__PORT EQU 2 +SCSI_In__0__PRT EQU CYREG_PRT2_PRT +SCSI_In__0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_In__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_In__0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_In__0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_In__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_In__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_In__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_In__0__PS EQU CYREG_PRT2_PS +SCSI_In__0__SHIFT EQU 1 +SCSI_In__0__SLW EQU CYREG_PRT2_SLW +SCSI_In__1__AG EQU CYREG_PRT6_AG +SCSI_In__1__AMUX EQU CYREG_PRT6_AMUX +SCSI_In__1__BIE EQU CYREG_PRT6_BIE +SCSI_In__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In__1__BYP EQU CYREG_PRT6_BYP +SCSI_In__1__CTL EQU CYREG_PRT6_CTL +SCSI_In__1__DM0 EQU CYREG_PRT6_DM0 +SCSI_In__1__DM1 EQU CYREG_PRT6_DM1 +SCSI_In__1__DM2 EQU CYREG_PRT6_DM2 +SCSI_In__1__DR EQU CYREG_PRT6_DR +SCSI_In__1__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In__1__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In__1__MASK EQU 0x08 +SCSI_In__1__PC EQU CYREG_PRT6_PC3 +SCSI_In__1__PORT EQU 6 +SCSI_In__1__PRT EQU CYREG_PRT6_PRT +SCSI_In__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In__1__PS EQU CYREG_PRT6_PS +SCSI_In__1__SHIFT EQU 3 +SCSI_In__1__SLW EQU CYREG_PRT6_SLW +SCSI_In__2__AG EQU CYREG_PRT6_AG +SCSI_In__2__AMUX EQU CYREG_PRT6_AMUX +SCSI_In__2__BIE EQU CYREG_PRT6_BIE +SCSI_In__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In__2__BYP EQU CYREG_PRT6_BYP +SCSI_In__2__CTL EQU CYREG_PRT6_CTL +SCSI_In__2__DM0 EQU CYREG_PRT6_DM0 +SCSI_In__2__DM1 EQU CYREG_PRT6_DM1 +SCSI_In__2__DM2 EQU CYREG_PRT6_DM2 +SCSI_In__2__DR EQU CYREG_PRT6_DR +SCSI_In__2__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In__2__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In__2__MASK EQU 0x04 +SCSI_In__2__PC EQU CYREG_PRT6_PC2 +SCSI_In__2__PORT EQU 6 +SCSI_In__2__PRT EQU CYREG_PRT6_PRT +SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In__2__PS EQU CYREG_PRT6_PS +SCSI_In__2__SHIFT EQU 2 +SCSI_In__2__SLW EQU CYREG_PRT6_SLW +SCSI_In__3__AG EQU CYREG_PRT4_AG +SCSI_In__3__AMUX EQU CYREG_PRT4_AMUX +SCSI_In__3__BIE EQU CYREG_PRT4_BIE +SCSI_In__3__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_In__3__BYP EQU CYREG_PRT4_BYP +SCSI_In__3__CTL EQU CYREG_PRT4_CTL +SCSI_In__3__DM0 EQU CYREG_PRT4_DM0 +SCSI_In__3__DM1 EQU CYREG_PRT4_DM1 +SCSI_In__3__DM2 EQU CYREG_PRT4_DM2 +SCSI_In__3__DR EQU CYREG_PRT4_DR +SCSI_In__3__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_In__3__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_In__3__MASK EQU 0x40 +SCSI_In__3__PC EQU CYREG_PRT4_PC6 +SCSI_In__3__PORT EQU 4 +SCSI_In__3__PRT EQU CYREG_PRT4_PRT +SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_In__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_In__3__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_In__3__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_In__3__PS EQU CYREG_PRT4_PS +SCSI_In__3__SHIFT EQU 6 +SCSI_In__3__SLW EQU CYREG_PRT4_SLW +SCSI_In__4__AG EQU CYREG_PRT4_AG +SCSI_In__4__AMUX EQU CYREG_PRT4_AMUX +SCSI_In__4__BIE EQU CYREG_PRT4_BIE +SCSI_In__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_In__4__BYP EQU CYREG_PRT4_BYP +SCSI_In__4__CTL EQU CYREG_PRT4_CTL +SCSI_In__4__DM0 EQU CYREG_PRT4_DM0 +SCSI_In__4__DM1 EQU CYREG_PRT4_DM1 +SCSI_In__4__DM2 EQU CYREG_PRT4_DM2 +SCSI_In__4__DR EQU CYREG_PRT4_DR +SCSI_In__4__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_In__4__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_In__4__MASK EQU 0x08 +SCSI_In__4__PC EQU CYREG_PRT4_PC3 +SCSI_In__4__PORT EQU 4 +SCSI_In__4__PRT EQU CYREG_PRT4_PRT +SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_In__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_In__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_In__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_In__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_In__4__PS EQU CYREG_PRT4_PS +SCSI_In__4__SHIFT EQU 3 +SCSI_In__4__SLW EQU CYREG_PRT4_SLW +SCSI_In__5__AG EQU CYREG_PRT4_AG +SCSI_In__5__AMUX EQU CYREG_PRT4_AMUX +SCSI_In__5__BIE EQU CYREG_PRT4_BIE +SCSI_In__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_In__5__BYP EQU CYREG_PRT4_BYP +SCSI_In__5__CTL EQU CYREG_PRT4_CTL +SCSI_In__5__DM0 EQU CYREG_PRT4_DM0 +SCSI_In__5__DM1 EQU CYREG_PRT4_DM1 +SCSI_In__5__DM2 EQU CYREG_PRT4_DM2 +SCSI_In__5__DR EQU CYREG_PRT4_DR +SCSI_In__5__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_In__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_In__5__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_In__5__MASK EQU 0x04 +SCSI_In__5__PC EQU CYREG_PRT4_PC2 +SCSI_In__5__PORT EQU 4 +SCSI_In__5__PRT EQU CYREG_PRT4_PRT +SCSI_In__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_In__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_In__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_In__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_In__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_In__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_In__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_In__5__PS EQU CYREG_PRT4_PS +SCSI_In__5__SHIFT EQU 2 +SCSI_In__5__SLW EQU CYREG_PRT4_SLW +SCSI_In__6__AG EQU CYREG_PRT0_AG +SCSI_In__6__AMUX EQU CYREG_PRT0_AMUX +SCSI_In__6__BIE EQU CYREG_PRT0_BIE +SCSI_In__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_In__6__BYP EQU CYREG_PRT0_BYP +SCSI_In__6__CTL EQU CYREG_PRT0_CTL +SCSI_In__6__DM0 EQU CYREG_PRT0_DM0 +SCSI_In__6__DM1 EQU CYREG_PRT0_DM1 +SCSI_In__6__DM2 EQU CYREG_PRT0_DM2 +SCSI_In__6__DR EQU CYREG_PRT0_DR +SCSI_In__6__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_In__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_In__6__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_In__6__MASK EQU 0x20 +SCSI_In__6__PC EQU CYREG_PRT0_PC5 +SCSI_In__6__PORT EQU 0 +SCSI_In__6__PRT EQU CYREG_PRT0_PRT +SCSI_In__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_In__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_In__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_In__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_In__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_In__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_In__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_In__6__PS EQU CYREG_PRT0_PS +SCSI_In__6__SHIFT EQU 5 +SCSI_In__6__SLW EQU CYREG_PRT0_SLW +SCSI_In__7__AG EQU CYREG_PRT0_AG +SCSI_In__7__AMUX EQU CYREG_PRT0_AMUX +SCSI_In__7__BIE EQU CYREG_PRT0_BIE +SCSI_In__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_In__7__BYP EQU CYREG_PRT0_BYP +SCSI_In__7__CTL EQU CYREG_PRT0_CTL +SCSI_In__7__DM0 EQU CYREG_PRT0_DM0 +SCSI_In__7__DM1 EQU CYREG_PRT0_DM1 +SCSI_In__7__DM2 EQU CYREG_PRT0_DM2 +SCSI_In__7__DR EQU CYREG_PRT0_DR +SCSI_In__7__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_In__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_In__7__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_In__7__MASK EQU 0x10 +SCSI_In__7__PC EQU CYREG_PRT0_PC4 +SCSI_In__7__PORT EQU 0 +SCSI_In__7__PRT EQU CYREG_PRT0_PRT +SCSI_In__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_In__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_In__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_In__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_In__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_In__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_In__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_In__7__PS EQU CYREG_PRT0_PS +SCSI_In__7__SHIFT EQU 4 +SCSI_In__7__SLW EQU CYREG_PRT0_SLW +SCSI_In__ACK__AG EQU CYREG_PRT6_AG +SCSI_In__ACK__AMUX EQU CYREG_PRT6_AMUX +SCSI_In__ACK__BIE EQU CYREG_PRT6_BIE +SCSI_In__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In__ACK__BYP EQU CYREG_PRT6_BYP +SCSI_In__ACK__CTL EQU CYREG_PRT6_CTL +SCSI_In__ACK__DM0 EQU CYREG_PRT6_DM0 +SCSI_In__ACK__DM1 EQU CYREG_PRT6_DM1 +SCSI_In__ACK__DM2 EQU CYREG_PRT6_DM2 +SCSI_In__ACK__DR EQU CYREG_PRT6_DR +SCSI_In__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In__ACK__MASK EQU 0x04 +SCSI_In__ACK__PC EQU CYREG_PRT6_PC2 +SCSI_In__ACK__PORT EQU 6 +SCSI_In__ACK__PRT EQU CYREG_PRT6_PRT +SCSI_In__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In__ACK__PS EQU CYREG_PRT6_PS +SCSI_In__ACK__SHIFT EQU 2 +SCSI_In__ACK__SLW EQU CYREG_PRT6_SLW +SCSI_In__BSY__AG EQU CYREG_PRT6_AG +SCSI_In__BSY__AMUX EQU CYREG_PRT6_AMUX +SCSI_In__BSY__BIE EQU CYREG_PRT6_BIE +SCSI_In__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In__BSY__BYP EQU CYREG_PRT6_BYP +SCSI_In__BSY__CTL EQU CYREG_PRT6_CTL +SCSI_In__BSY__DM0 EQU CYREG_PRT6_DM0 +SCSI_In__BSY__DM1 EQU CYREG_PRT6_DM1 +SCSI_In__BSY__DM2 EQU CYREG_PRT6_DM2 +SCSI_In__BSY__DR EQU CYREG_PRT6_DR +SCSI_In__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In__BSY__MASK EQU 0x08 +SCSI_In__BSY__PC EQU CYREG_PRT6_PC3 +SCSI_In__BSY__PORT EQU 6 +SCSI_In__BSY__PRT EQU CYREG_PRT6_PRT +SCSI_In__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In__BSY__PS EQU CYREG_PRT6_PS +SCSI_In__BSY__SHIFT EQU 3 +SCSI_In__BSY__SLW EQU CYREG_PRT6_SLW +SCSI_In__CD__AG EQU CYREG_PRT4_AG +SCSI_In__CD__AMUX EQU CYREG_PRT4_AMUX +SCSI_In__CD__BIE EQU CYREG_PRT4_BIE +SCSI_In__CD__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_In__CD__BYP EQU CYREG_PRT4_BYP +SCSI_In__CD__CTL EQU CYREG_PRT4_CTL +SCSI_In__CD__DM0 EQU CYREG_PRT4_DM0 +SCSI_In__CD__DM1 EQU CYREG_PRT4_DM1 +SCSI_In__CD__DM2 EQU CYREG_PRT4_DM2 +SCSI_In__CD__DR EQU CYREG_PRT4_DR +SCSI_In__CD__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_In__CD__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_In__CD__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_In__CD__MASK EQU 0x04 +SCSI_In__CD__PC EQU CYREG_PRT4_PC2 +SCSI_In__CD__PORT EQU 4 +SCSI_In__CD__PRT EQU CYREG_PRT4_PRT +SCSI_In__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_In__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_In__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_In__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_In__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_In__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_In__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_In__CD__PS EQU CYREG_PRT4_PS +SCSI_In__CD__SHIFT EQU 2 +SCSI_In__CD__SLW EQU CYREG_PRT4_SLW +SCSI_In__DBP__AG EQU CYREG_PRT2_AG +SCSI_In__DBP__AMUX EQU CYREG_PRT2_AMUX +SCSI_In__DBP__BIE EQU CYREG_PRT2_BIE +SCSI_In__DBP__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_In__DBP__BYP EQU CYREG_PRT2_BYP +SCSI_In__DBP__CTL EQU CYREG_PRT2_CTL +SCSI_In__DBP__DM0 EQU CYREG_PRT2_DM0 +SCSI_In__DBP__DM1 EQU CYREG_PRT2_DM1 +SCSI_In__DBP__DM2 EQU CYREG_PRT2_DM2 +SCSI_In__DBP__DR EQU CYREG_PRT2_DR +SCSI_In__DBP__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_In__DBP__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_In__DBP__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_In__DBP__MASK EQU 0x02 +SCSI_In__DBP__PC EQU CYREG_PRT2_PC1 +SCSI_In__DBP__PORT EQU 2 +SCSI_In__DBP__PRT EQU CYREG_PRT2_PRT +SCSI_In__DBP__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_In__DBP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_In__DBP__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_In__DBP__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_In__DBP__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_In__DBP__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_In__DBP__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_In__DBP__PS EQU CYREG_PRT2_PS +SCSI_In__DBP__SHIFT EQU 1 +SCSI_In__DBP__SLW EQU CYREG_PRT2_SLW +SCSI_In__IO__AG EQU CYREG_PRT0_AG +SCSI_In__IO__AMUX EQU CYREG_PRT0_AMUX +SCSI_In__IO__BIE EQU CYREG_PRT0_BIE +SCSI_In__IO__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_In__IO__BYP EQU CYREG_PRT0_BYP +SCSI_In__IO__CTL EQU CYREG_PRT0_CTL +SCSI_In__IO__DM0 EQU CYREG_PRT0_DM0 +SCSI_In__IO__DM1 EQU CYREG_PRT0_DM1 +SCSI_In__IO__DM2 EQU CYREG_PRT0_DM2 +SCSI_In__IO__DR EQU CYREG_PRT0_DR +SCSI_In__IO__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_In__IO__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_In__IO__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_In__IO__MASK EQU 0x10 +SCSI_In__IO__PC EQU CYREG_PRT0_PC4 +SCSI_In__IO__PORT EQU 0 +SCSI_In__IO__PRT EQU CYREG_PRT0_PRT +SCSI_In__IO__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_In__IO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_In__IO__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_In__IO__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_In__IO__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_In__IO__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_In__IO__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_In__IO__PS EQU CYREG_PRT0_PS +SCSI_In__IO__SHIFT EQU 4 +SCSI_In__IO__SLW EQU CYREG_PRT0_SLW +SCSI_In__MSG__AG EQU CYREG_PRT4_AG +SCSI_In__MSG__AMUX EQU CYREG_PRT4_AMUX +SCSI_In__MSG__BIE EQU CYREG_PRT4_BIE +SCSI_In__MSG__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_In__MSG__BYP EQU CYREG_PRT4_BYP +SCSI_In__MSG__CTL EQU CYREG_PRT4_CTL +SCSI_In__MSG__DM0 EQU CYREG_PRT4_DM0 +SCSI_In__MSG__DM1 EQU CYREG_PRT4_DM1 +SCSI_In__MSG__DM2 EQU CYREG_PRT4_DM2 +SCSI_In__MSG__DR EQU CYREG_PRT4_DR +SCSI_In__MSG__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_In__MSG__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_In__MSG__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_In__MSG__MASK EQU 0x40 +SCSI_In__MSG__PC EQU CYREG_PRT4_PC6 +SCSI_In__MSG__PORT EQU 4 +SCSI_In__MSG__PRT EQU CYREG_PRT4_PRT +SCSI_In__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_In__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_In__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_In__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_In__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_In__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_In__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_In__MSG__PS EQU CYREG_PRT4_PS +SCSI_In__MSG__SHIFT EQU 6 +SCSI_In__MSG__SLW EQU CYREG_PRT4_SLW +SCSI_In__REQ__AG EQU CYREG_PRT0_AG +SCSI_In__REQ__AMUX EQU CYREG_PRT0_AMUX +SCSI_In__REQ__BIE EQU CYREG_PRT0_BIE +SCSI_In__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_In__REQ__BYP EQU CYREG_PRT0_BYP +SCSI_In__REQ__CTL EQU CYREG_PRT0_CTL +SCSI_In__REQ__DM0 EQU CYREG_PRT0_DM0 +SCSI_In__REQ__DM1 EQU CYREG_PRT0_DM1 +SCSI_In__REQ__DM2 EQU CYREG_PRT0_DM2 +SCSI_In__REQ__DR EQU CYREG_PRT0_DR +SCSI_In__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_In__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_In__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_In__REQ__MASK EQU 0x20 +SCSI_In__REQ__PC EQU CYREG_PRT0_PC5 +SCSI_In__REQ__PORT EQU 0 +SCSI_In__REQ__PRT EQU CYREG_PRT0_PRT +SCSI_In__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_In__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_In__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_In__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_In__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_In__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_In__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_In__REQ__PS EQU CYREG_PRT0_PS +SCSI_In__REQ__SHIFT EQU 5 +SCSI_In__REQ__SLW EQU CYREG_PRT0_SLW +SCSI_In__SEL__AG EQU CYREG_PRT4_AG +SCSI_In__SEL__AMUX EQU CYREG_PRT4_AMUX +SCSI_In__SEL__BIE EQU CYREG_PRT4_BIE +SCSI_In__SEL__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_In__SEL__BYP EQU CYREG_PRT4_BYP +SCSI_In__SEL__CTL EQU CYREG_PRT4_CTL +SCSI_In__SEL__DM0 EQU CYREG_PRT4_DM0 +SCSI_In__SEL__DM1 EQU CYREG_PRT4_DM1 +SCSI_In__SEL__DM2 EQU CYREG_PRT4_DM2 +SCSI_In__SEL__DR EQU CYREG_PRT4_DR +SCSI_In__SEL__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_In__SEL__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_In__SEL__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_In__SEL__MASK EQU 0x08 +SCSI_In__SEL__PC EQU CYREG_PRT4_PC3 +SCSI_In__SEL__PORT EQU 4 +SCSI_In__SEL__PRT EQU CYREG_PRT4_PRT +SCSI_In__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_In__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_In__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_In__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_In__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_In__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_In__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_In__SEL__PS EQU CYREG_PRT4_PS +SCSI_In__SEL__SHIFT EQU 3 +SCSI_In__SEL__SLW EQU CYREG_PRT4_SLW + +/* SD_MISO */ +SD_MISO__0__MASK EQU 0x02 +SD_MISO__0__PC EQU CYREG_PRT3_PC1 +SD_MISO__0__PORT EQU 3 +SD_MISO__0__SHIFT EQU 1 +SD_MISO__AG EQU CYREG_PRT3_AG +SD_MISO__AMUX EQU CYREG_PRT3_AMUX +SD_MISO__BIE EQU CYREG_PRT3_BIE +SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_MISO__BYP EQU CYREG_PRT3_BYP +SD_MISO__CTL EQU CYREG_PRT3_CTL +SD_MISO__DM0 EQU CYREG_PRT3_DM0 +SD_MISO__DM1 EQU CYREG_PRT3_DM1 +SD_MISO__DM2 EQU CYREG_PRT3_DM2 +SD_MISO__DR EQU CYREG_PRT3_DR +SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_MISO__MASK EQU 0x02 +SD_MISO__PORT EQU 3 +SD_MISO__PRT EQU CYREG_PRT3_PRT +SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_MISO__PS EQU CYREG_PRT3_PS +SD_MISO__SHIFT EQU 1 +SD_MISO__SLW EQU CYREG_PRT3_SLW + +/* SD_MOSI */ +SD_MOSI__0__MASK EQU 0x08 +SD_MOSI__0__PC EQU CYREG_PRT3_PC3 +SD_MOSI__0__PORT EQU 3 +SD_MOSI__0__SHIFT EQU 3 +SD_MOSI__AG EQU CYREG_PRT3_AG +SD_MOSI__AMUX EQU CYREG_PRT3_AMUX +SD_MOSI__BIE EQU CYREG_PRT3_BIE +SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_MOSI__BYP EQU CYREG_PRT3_BYP +SD_MOSI__CTL EQU CYREG_PRT3_CTL +SD_MOSI__DM0 EQU CYREG_PRT3_DM0 +SD_MOSI__DM1 EQU CYREG_PRT3_DM1 +SD_MOSI__DM2 EQU CYREG_PRT3_DM2 +SD_MOSI__DR EQU CYREG_PRT3_DR +SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_MOSI__MASK EQU 0x08 +SD_MOSI__PORT EQU 3 +SD_MOSI__PRT EQU CYREG_PRT3_PRT +SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_MOSI__PS EQU CYREG_PRT3_PS +SD_MOSI__SHIFT EQU 3 +SD_MOSI__SLW EQU CYREG_PRT3_SLW + +/* SD_SCK */ +SD_SCK__0__MASK EQU 0x04 +SD_SCK__0__PC EQU CYREG_PRT3_PC2 +SD_SCK__0__PORT EQU 3 +SD_SCK__0__SHIFT EQU 2 +SD_SCK__AG EQU CYREG_PRT3_AG +SD_SCK__AMUX EQU CYREG_PRT3_AMUX +SD_SCK__BIE EQU CYREG_PRT3_BIE +SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_SCK__BYP EQU CYREG_PRT3_BYP +SD_SCK__CTL EQU CYREG_PRT3_CTL +SD_SCK__DM0 EQU CYREG_PRT3_DM0 +SD_SCK__DM1 EQU CYREG_PRT3_DM1 +SD_SCK__DM2 EQU CYREG_PRT3_DM2 +SD_SCK__DR EQU CYREG_PRT3_DR +SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_SCK__MASK EQU 0x04 +SD_SCK__PORT EQU 3 +SD_SCK__PRT EQU CYREG_PRT3_PRT +SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_SCK__PS EQU CYREG_PRT3_PS +SD_SCK__SHIFT EQU 2 +SD_SCK__SLW EQU CYREG_PRT3_SLW + +/* SD_CD */ +SD_CD__0__MASK EQU 0x20 +SD_CD__0__PC EQU CYREG_PRT3_PC5 +SD_CD__0__PORT EQU 3 +SD_CD__0__SHIFT EQU 5 +SD_CD__AG EQU CYREG_PRT3_AG +SD_CD__AMUX EQU CYREG_PRT3_AMUX +SD_CD__BIE EQU CYREG_PRT3_BIE +SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_CD__BYP EQU CYREG_PRT3_BYP +SD_CD__CTL EQU CYREG_PRT3_CTL +SD_CD__DM0 EQU CYREG_PRT3_DM0 +SD_CD__DM1 EQU CYREG_PRT3_DM1 +SD_CD__DM2 EQU CYREG_PRT3_DM2 +SD_CD__DR EQU CYREG_PRT3_DR +SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_CD__MASK EQU 0x20 +SD_CD__PORT EQU 3 +SD_CD__PRT EQU CYREG_PRT3_PRT +SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_CD__PS EQU CYREG_PRT3_PS +SD_CD__SHIFT EQU 5 +SD_CD__SLW EQU CYREG_PRT3_SLW + +/* SD_CS */ +SD_CS__0__MASK EQU 0x10 +SD_CS__0__PC EQU CYREG_PRT3_PC4 +SD_CS__0__PORT EQU 3 +SD_CS__0__SHIFT EQU 4 +SD_CS__AG EQU CYREG_PRT3_AG +SD_CS__AMUX EQU CYREG_PRT3_AMUX +SD_CS__BIE EQU CYREG_PRT3_BIE +SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_CS__BYP EQU CYREG_PRT3_BYP +SD_CS__CTL EQU CYREG_PRT3_CTL +SD_CS__DM0 EQU CYREG_PRT3_DM0 +SD_CS__DM1 EQU CYREG_PRT3_DM1 +SD_CS__DM2 EQU CYREG_PRT3_DM2 +SD_CS__DR EQU CYREG_PRT3_DR +SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_CS__MASK EQU 0x10 +SD_CS__PORT EQU 3 +SD_CS__PRT EQU CYREG_PRT3_PRT +SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_CS__PS EQU CYREG_PRT3_PS +SD_CS__SHIFT EQU 4 +SD_CS__SLW EQU CYREG_PRT3_SLW + +/* LED1 */ +LED1__0__MASK EQU 0x02 +LED1__0__PC EQU CYREG_PRT0_PC1 +LED1__0__PORT EQU 0 +LED1__0__SHIFT EQU 1 +LED1__AG EQU CYREG_PRT0_AG +LED1__AMUX EQU CYREG_PRT0_AMUX +LED1__BIE EQU CYREG_PRT0_BIE +LED1__BIT_MASK EQU CYREG_PRT0_BIT_MASK +LED1__BYP EQU CYREG_PRT0_BYP +LED1__CTL EQU CYREG_PRT0_CTL +LED1__DM0 EQU CYREG_PRT0_DM0 +LED1__DM1 EQU CYREG_PRT0_DM1 +LED1__DM2 EQU CYREG_PRT0_DM2 +LED1__DR EQU CYREG_PRT0_DR +LED1__INP_DIS EQU CYREG_PRT0_INP_DIS +LED1__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +LED1__LCD_EN EQU CYREG_PRT0_LCD_EN +LED1__MASK EQU 0x02 +LED1__PORT EQU 0 +LED1__PRT EQU CYREG_PRT0_PRT +LED1__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +LED1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +LED1__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +LED1__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +LED1__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +LED1__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +LED1__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +LED1__PS EQU CYREG_PRT0_PS +LED1__SHIFT EQU 1 +LED1__SLW EQU CYREG_PRT0_SLW + +/* Miscellaneous */ +/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */ +CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6 +CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0 +CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0 +CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1 +CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0 +CYDEV_CHIP_MEMBER_5B EQU 4 +CYDEV_CHIP_FAMILY_PSOC5 EQU 3 +CYDEV_CHIP_DIE_PSOC5LP EQU 4 +CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP +BCLK__BUS_CLK__HZ EQU 60000000 +BCLK__BUS_CLK__KHZ EQU 60000 +BCLK__BUS_CLK__MHZ EQU 60 +CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT +CYDEV_CHIP_DIE_LEOPARD EQU 1 +CYDEV_CHIP_DIE_PANTHER EQU 3 +CYDEV_CHIP_DIE_PSOC4A EQU 2 +CYDEV_CHIP_DIE_UNKNOWN EQU 0 +CYDEV_CHIP_FAMILY_PSOC3 EQU 1 +CYDEV_CHIP_FAMILY_PSOC4 EQU 2 +CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 +CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5 +CYDEV_CHIP_JTAG_ID EQU 0x2E133069 +CYDEV_CHIP_MEMBER_3A EQU 1 +CYDEV_CHIP_MEMBER_4A EQU 2 +CYDEV_CHIP_MEMBER_5A EQU 3 +CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 +CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B +CYDEV_CHIP_REVISION_3A_ES1 EQU 0 +CYDEV_CHIP_REVISION_3A_ES2 EQU 1 +CYDEV_CHIP_REVISION_3A_ES3 EQU 3 +CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3 +CYDEV_CHIP_REVISION_4A_ES0 EQU 17 +CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_5A_ES0 EQU 0 +CYDEV_CHIP_REVISION_5A_ES1 EQU 1 +CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 +CYDEV_CHIP_REVISION_5B_ES0 EQU 0 +CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION +CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REV_PSOC5LP_PRODUCTION +CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0 +CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1 +CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3 +CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3 +CYDEV_CHIP_REV_PANTHER_ES0 EQU 0 +CYDEV_CHIP_REV_PANTHER_ES1 EQU 1 +CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1 +CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17 +CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17 +CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0 +CYDEV_CONFIGURATION_COMPRESSED EQU 1 +CYDEV_CONFIGURATION_DMA EQU 0 +CYDEV_CONFIGURATION_ECC EQU 0 +CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED +CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED +CYDEV_CONFIGURATION_MODE_DMA EQU 2 +CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1 +CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn +CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1 +CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2 +CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV +CYDEV_DEBUGGING_DPS_Disable EQU 3 +CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1 +CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0 +CYDEV_DEBUGGING_DPS_SWD EQU 2 +CYDEV_DEBUGGING_ENABLE EQU 1 +CYDEV_DEBUGGING_XRES EQU 0 +CYDEV_DEBUG_ENABLE_MASK EQU 0x20 +CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG +CYDEV_DMA_CHANNELS_AVAILABLE EQU 24 +CYDEV_ECC_ENABLE EQU 0 +CYDEV_HEAP_SIZE EQU 0x1000 +CYDEV_INSTRUCT_CACHE_ENABLED EQU 1 +CYDEV_INTR_RISING EQU 0x00000000 +CYDEV_PROJ_TYPE EQU 2 +CYDEV_PROJ_TYPE_BOOTLOADER EQU 1 +CYDEV_PROJ_TYPE_LOADABLE EQU 2 +CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3 +CYDEV_PROJ_TYPE_STANDARD EQU 0 +CYDEV_PROTECTION_ENABLE EQU 0 +CYDEV_STACK_SIZE EQU 0x4000 +CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP EQU 1 +CYDEV_USE_BUNDLED_CMSIS EQU 1 +CYDEV_VARIABLE_VDDA EQU 0 +CYDEV_VDDA_MV EQU 5000 +CYDEV_VDDD_MV EQU 5000 +CYDEV_VDDIO0_MV EQU 5000 +CYDEV_VDDIO1_MV EQU 5000 +CYDEV_VDDIO2_MV EQU 5000 +CYDEV_VDDIO3_MV EQU 3300 +CYDEV_VIO0 EQU 5 +CYDEV_VIO0_MV EQU 5000 +CYDEV_VIO1 EQU 5 +CYDEV_VIO1_MV EQU 5000 +CYDEV_VIO2 EQU 5 +CYDEV_VIO2_MV EQU 5000 +CYDEV_VIO3_MV EQU 3300 +DMA_CHANNELS_USED__MASK0 EQU 0x00000000 +CYDEV_BOOTLOADER_ENABLE EQU 0 + +#endif /* INCLUDED_CYFITTERIAR_INC */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyfitterrv.inc new file mode 100755 index 00000000..54871aef --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -0,0 +1,2677 @@ + IF :LNOT::DEF:INCLUDED_CYFITTERRV_INC +INCLUDED_CYFITTERRV_INC EQU 1 + GET cydevicerv.inc + GET cydevicerv_trm.inc + +; USBFS_bus_reset +USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_bus_reset__INTC_MASK EQU 0x800000 +USBFS_bus_reset__INTC_NUMBER EQU 23 +USBFS_bus_reset__INTC_PRIOR_NUM EQU 7 +USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23 +USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; USBFS_arb_int +USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_arb_int__INTC_MASK EQU 0x400000 +USBFS_arb_int__INTC_NUMBER EQU 22 +USBFS_arb_int__INTC_PRIOR_NUM EQU 7 +USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22 +USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; USBFS_sof_int +USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_sof_int__INTC_MASK EQU 0x200000 +USBFS_sof_int__INTC_NUMBER EQU 21 +USBFS_sof_int__INTC_PRIOR_NUM EQU 7 +USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21 +USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SCSI_Out_DBx +SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG +SCSI_Out_DBx__0__AMUX EQU CYREG_PRT5_AMUX +SCSI_Out_DBx__0__BIE EQU CYREG_PRT5_BIE +SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_Out_DBx__0__BYP EQU CYREG_PRT5_BYP +SCSI_Out_DBx__0__CTL EQU CYREG_PRT5_CTL +SCSI_Out_DBx__0__DM0 EQU CYREG_PRT5_DM0 +SCSI_Out_DBx__0__DM1 EQU CYREG_PRT5_DM1 +SCSI_Out_DBx__0__DM2 EQU CYREG_PRT5_DM2 +SCSI_Out_DBx__0__DR EQU CYREG_PRT5_DR +SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_Out_DBx__0__MASK EQU 0x02 +SCSI_Out_DBx__0__PC EQU CYREG_PRT5_PC1 +SCSI_Out_DBx__0__PORT EQU 5 +SCSI_Out_DBx__0__PRT EQU CYREG_PRT5_PRT +SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_Out_DBx__0__PS EQU CYREG_PRT5_PS +SCSI_Out_DBx__0__SHIFT EQU 1 +SCSI_Out_DBx__0__SLW EQU CYREG_PRT5_SLW +SCSI_Out_DBx__1__AG EQU CYREG_PRT5_AG +SCSI_Out_DBx__1__AMUX EQU CYREG_PRT5_AMUX +SCSI_Out_DBx__1__BIE EQU CYREG_PRT5_BIE +SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_Out_DBx__1__BYP EQU CYREG_PRT5_BYP +SCSI_Out_DBx__1__CTL EQU CYREG_PRT5_CTL +SCSI_Out_DBx__1__DM0 EQU CYREG_PRT5_DM0 +SCSI_Out_DBx__1__DM1 EQU CYREG_PRT5_DM1 +SCSI_Out_DBx__1__DM2 EQU CYREG_PRT5_DM2 +SCSI_Out_DBx__1__DR EQU CYREG_PRT5_DR +SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_Out_DBx__1__MASK EQU 0x01 +SCSI_Out_DBx__1__PC EQU CYREG_PRT5_PC0 +SCSI_Out_DBx__1__PORT EQU 5 +SCSI_Out_DBx__1__PRT EQU CYREG_PRT5_PRT +SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_Out_DBx__1__PS EQU CYREG_PRT5_PS +SCSI_Out_DBx__1__SHIFT EQU 0 +SCSI_Out_DBx__1__SLW EQU CYREG_PRT5_SLW +SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG +SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE +SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP +SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL +SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR +SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out_DBx__2__MASK EQU 0x20 +SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC5 +SCSI_Out_DBx__2__PORT EQU 6 +SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT +SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS +SCSI_Out_DBx__2__SHIFT EQU 5 +SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW +SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG +SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE +SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP +SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL +SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR +SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out_DBx__3__MASK EQU 0x10 +SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC4 +SCSI_Out_DBx__3__PORT EQU 6 +SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT +SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS +SCSI_Out_DBx__3__SHIFT EQU 4 +SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW +SCSI_Out_DBx__4__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__4__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__4__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__4__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__4__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__4__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__4__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__4__MASK EQU 0x80 +SCSI_Out_DBx__4__PC EQU CYREG_PRT2_PC7 +SCSI_Out_DBx__4__PORT EQU 2 +SCSI_Out_DBx__4__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__4__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__4__SHIFT EQU 7 +SCSI_Out_DBx__4__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__5__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__5__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__5__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__5__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__5__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__5__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__5__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__5__MASK EQU 0x40 +SCSI_Out_DBx__5__PC EQU CYREG_PRT2_PC6 +SCSI_Out_DBx__5__PORT EQU 2 +SCSI_Out_DBx__5__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__5__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__5__SHIFT EQU 6 +SCSI_Out_DBx__5__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__6__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__6__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__6__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__6__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__6__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__6__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__6__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__6__MASK EQU 0x08 +SCSI_Out_DBx__6__PC EQU CYREG_PRT2_PC3 +SCSI_Out_DBx__6__PORT EQU 2 +SCSI_Out_DBx__6__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__6__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__6__SHIFT EQU 3 +SCSI_Out_DBx__6__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__7__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__7__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__7__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__7__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__7__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__7__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__7__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__7__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__7__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__7__MASK EQU 0x04 +SCSI_Out_DBx__7__PC EQU CYREG_PRT2_PC2 +SCSI_Out_DBx__7__PORT EQU 2 +SCSI_Out_DBx__7__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__7__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__7__SHIFT EQU 2 +SCSI_Out_DBx__7__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__DB0__AG EQU CYREG_PRT5_AG +SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX +SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT5_BIE +SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT5_BYP +SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT5_CTL +SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT5_DM0 +SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT5_DM1 +SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT5_DM2 +SCSI_Out_DBx__DB0__DR EQU CYREG_PRT5_DR +SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_Out_DBx__DB0__MASK EQU 0x02 +SCSI_Out_DBx__DB0__PC EQU CYREG_PRT5_PC1 +SCSI_Out_DBx__DB0__PORT EQU 5 +SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT5_PRT +SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_Out_DBx__DB0__PS EQU CYREG_PRT5_PS +SCSI_Out_DBx__DB0__SHIFT EQU 1 +SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT5_SLW +SCSI_Out_DBx__DB1__AG EQU CYREG_PRT5_AG +SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX +SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT5_BIE +SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT5_BYP +SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT5_CTL +SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT5_DM0 +SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT5_DM1 +SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT5_DM2 +SCSI_Out_DBx__DB1__DR EQU CYREG_PRT5_DR +SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_Out_DBx__DB1__MASK EQU 0x01 +SCSI_Out_DBx__DB1__PC EQU CYREG_PRT5_PC0 +SCSI_Out_DBx__DB1__PORT EQU 5 +SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT5_PRT +SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_Out_DBx__DB1__PS EQU CYREG_PRT5_PS +SCSI_Out_DBx__DB1__SHIFT EQU 0 +SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT5_SLW +SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG +SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE +SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP +SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL +SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR +SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out_DBx__DB2__MASK EQU 0x20 +SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC5 +SCSI_Out_DBx__DB2__PORT EQU 6 +SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT +SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS +SCSI_Out_DBx__DB2__SHIFT EQU 5 +SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW +SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG +SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE +SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP +SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL +SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR +SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out_DBx__DB3__MASK EQU 0x10 +SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC4 +SCSI_Out_DBx__DB3__PORT EQU 6 +SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT +SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS +SCSI_Out_DBx__DB3__SHIFT EQU 4 +SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW +SCSI_Out_DBx__DB4__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__DB4__MASK EQU 0x80 +SCSI_Out_DBx__DB4__PC EQU CYREG_PRT2_PC7 +SCSI_Out_DBx__DB4__PORT EQU 2 +SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__DB4__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__DB4__SHIFT EQU 7 +SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__DB5__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__DB5__MASK EQU 0x40 +SCSI_Out_DBx__DB5__PC EQU CYREG_PRT2_PC6 +SCSI_Out_DBx__DB5__PORT EQU 2 +SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__DB5__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__DB5__SHIFT EQU 6 +SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__DB6__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__DB6__MASK EQU 0x08 +SCSI_Out_DBx__DB6__PC EQU CYREG_PRT2_PC3 +SCSI_Out_DBx__DB6__PORT EQU 2 +SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__DB6__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__DB6__SHIFT EQU 3 +SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__DB7__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__DB7__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__DB7__MASK EQU 0x04 +SCSI_Out_DBx__DB7__PC EQU CYREG_PRT2_PC2 +SCSI_Out_DBx__DB7__PORT EQU 2 +SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__DB7__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__DB7__SHIFT EQU 2 +SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT2_SLW + +; SCSI_RST_ISR +SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_RST_ISR__INTC_MASK EQU 0x100 +SCSI_RST_ISR__INTC_NUMBER EQU 8 +SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7 +SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 +SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SDCard_BSPIM +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST +SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 +SDCard_BSPIM_RxStsReg__4__POS EQU 4 +SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 +SDCard_BSPIM_RxStsReg__5__POS EQU 5 +SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 +SDCard_BSPIM_RxStsReg__6__POS EQU 6 +SDCard_BSPIM_RxStsReg__MASK EQU 0x70 +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST +SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 +SDCard_BSPIM_TxStsReg__0__POS EQU 0 +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST +SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 +SDCard_BSPIM_TxStsReg__1__POS EQU 1 +SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 +SDCard_BSPIM_TxStsReg__2__POS EQU 2 +SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 +SDCard_BSPIM_TxStsReg__3__POS EQU 3 +SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 +SDCard_BSPIM_TxStsReg__4__POS EQU 4 +SDCard_BSPIM_TxStsReg__MASK EQU 0x1F +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB06_07_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB06_07_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB06_07_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB06_07_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB06_07_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB06_07_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB06_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB06_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB06_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB06_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB06_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB06_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB06_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB06_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB06_F1 + +; USBFS_dp_int +USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_dp_int__INTC_MASK EQU 0x1000 +USBFS_dp_int__INTC_NUMBER EQU 12 +USBFS_dp_int__INTC_PRIOR_NUM EQU 7 +USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12 +USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SCSI_CTL_IO +SCSI_CTL_IO_Sync_ctrl_reg__0__MASK EQU 0x01 +SCSI_CTL_IO_Sync_ctrl_reg__0__POS EQU 0 +SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL +SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL +SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL +SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL +SCSI_CTL_IO_Sync_ctrl_reg__MASK EQU 0x01 +SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK +SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL + +; SCSI_In_DBx +SCSI_In_DBx__0__AG EQU CYREG_PRT5_AG +SCSI_In_DBx__0__AMUX EQU CYREG_PRT5_AMUX +SCSI_In_DBx__0__BIE EQU CYREG_PRT5_BIE +SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_In_DBx__0__BYP EQU CYREG_PRT5_BYP +SCSI_In_DBx__0__CTL EQU CYREG_PRT5_CTL +SCSI_In_DBx__0__DM0 EQU CYREG_PRT5_DM0 +SCSI_In_DBx__0__DM1 EQU CYREG_PRT5_DM1 +SCSI_In_DBx__0__DM2 EQU CYREG_PRT5_DM2 +SCSI_In_DBx__0__DR EQU CYREG_PRT5_DR +SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_In_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_In_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_In_DBx__0__MASK EQU 0x08 +SCSI_In_DBx__0__PC EQU CYREG_PRT5_PC3 +SCSI_In_DBx__0__PORT EQU 5 +SCSI_In_DBx__0__PRT EQU CYREG_PRT5_PRT +SCSI_In_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_In_DBx__0__PS EQU CYREG_PRT5_PS +SCSI_In_DBx__0__SHIFT EQU 3 +SCSI_In_DBx__0__SLW EQU CYREG_PRT5_SLW +SCSI_In_DBx__1__AG EQU CYREG_PRT5_AG +SCSI_In_DBx__1__AMUX EQU CYREG_PRT5_AMUX +SCSI_In_DBx__1__BIE EQU CYREG_PRT5_BIE +SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_In_DBx__1__BYP EQU CYREG_PRT5_BYP +SCSI_In_DBx__1__CTL EQU CYREG_PRT5_CTL +SCSI_In_DBx__1__DM0 EQU CYREG_PRT5_DM0 +SCSI_In_DBx__1__DM1 EQU CYREG_PRT5_DM1 +SCSI_In_DBx__1__DM2 EQU CYREG_PRT5_DM2 +SCSI_In_DBx__1__DR EQU CYREG_PRT5_DR +SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_In_DBx__1__MASK EQU 0x04 +SCSI_In_DBx__1__PC EQU CYREG_PRT5_PC2 +SCSI_In_DBx__1__PORT EQU 5 +SCSI_In_DBx__1__PRT EQU CYREG_PRT5_PRT +SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_In_DBx__1__PS EQU CYREG_PRT5_PS +SCSI_In_DBx__1__SHIFT EQU 2 +SCSI_In_DBx__1__SLW EQU CYREG_PRT5_SLW +SCSI_In_DBx__2__AG EQU CYREG_PRT6_AG +SCSI_In_DBx__2__AMUX EQU CYREG_PRT6_AMUX +SCSI_In_DBx__2__BIE EQU CYREG_PRT6_BIE +SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In_DBx__2__BYP EQU CYREG_PRT6_BYP +SCSI_In_DBx__2__CTL EQU CYREG_PRT6_CTL +SCSI_In_DBx__2__DM0 EQU CYREG_PRT6_DM0 +SCSI_In_DBx__2__DM1 EQU CYREG_PRT6_DM1 +SCSI_In_DBx__2__DM2 EQU CYREG_PRT6_DM2 +SCSI_In_DBx__2__DR EQU CYREG_PRT6_DR +SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In_DBx__2__MASK EQU 0x80 +SCSI_In_DBx__2__PC EQU CYREG_PRT6_PC7 +SCSI_In_DBx__2__PORT EQU 6 +SCSI_In_DBx__2__PRT EQU CYREG_PRT6_PRT +SCSI_In_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In_DBx__2__PS EQU CYREG_PRT6_PS +SCSI_In_DBx__2__SHIFT EQU 7 +SCSI_In_DBx__2__SLW EQU CYREG_PRT6_SLW +SCSI_In_DBx__3__AG EQU CYREG_PRT6_AG +SCSI_In_DBx__3__AMUX EQU CYREG_PRT6_AMUX +SCSI_In_DBx__3__BIE EQU CYREG_PRT6_BIE +SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In_DBx__3__BYP EQU CYREG_PRT6_BYP +SCSI_In_DBx__3__CTL EQU CYREG_PRT6_CTL +SCSI_In_DBx__3__DM0 EQU CYREG_PRT6_DM0 +SCSI_In_DBx__3__DM1 EQU CYREG_PRT6_DM1 +SCSI_In_DBx__3__DM2 EQU CYREG_PRT6_DM2 +SCSI_In_DBx__3__DR EQU CYREG_PRT6_DR +SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In_DBx__3__MASK EQU 0x40 +SCSI_In_DBx__3__PC EQU CYREG_PRT6_PC6 +SCSI_In_DBx__3__PORT EQU 6 +SCSI_In_DBx__3__PRT EQU CYREG_PRT6_PRT +SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In_DBx__3__PS EQU CYREG_PRT6_PS +SCSI_In_DBx__3__SHIFT EQU 6 +SCSI_In_DBx__3__SLW EQU CYREG_PRT6_SLW +SCSI_In_DBx__4__AG EQU CYREG_PRT12_AG +SCSI_In_DBx__4__BIE EQU CYREG_PRT12_BIE +SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_In_DBx__4__BYP EQU CYREG_PRT12_BYP +SCSI_In_DBx__4__DM0 EQU CYREG_PRT12_DM0 +SCSI_In_DBx__4__DM1 EQU CYREG_PRT12_DM1 +SCSI_In_DBx__4__DM2 EQU CYREG_PRT12_DM2 +SCSI_In_DBx__4__DR EQU CYREG_PRT12_DR +SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_In_DBx__4__MASK EQU 0x20 +SCSI_In_DBx__4__PC EQU CYREG_PRT12_PC5 +SCSI_In_DBx__4__PORT EQU 12 +SCSI_In_DBx__4__PRT EQU CYREG_PRT12_PRT +SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_In_DBx__4__PS EQU CYREG_PRT12_PS +SCSI_In_DBx__4__SHIFT EQU 5 +SCSI_In_DBx__4__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_In_DBx__4__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_In_DBx__4__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_In_DBx__4__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_In_DBx__4__SLW EQU CYREG_PRT12_SLW +SCSI_In_DBx__5__AG EQU CYREG_PRT12_AG +SCSI_In_DBx__5__BIE EQU CYREG_PRT12_BIE +SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_In_DBx__5__BYP EQU CYREG_PRT12_BYP +SCSI_In_DBx__5__DM0 EQU CYREG_PRT12_DM0 +SCSI_In_DBx__5__DM1 EQU CYREG_PRT12_DM1 +SCSI_In_DBx__5__DM2 EQU CYREG_PRT12_DM2 +SCSI_In_DBx__5__DR EQU CYREG_PRT12_DR +SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_In_DBx__5__MASK EQU 0x10 +SCSI_In_DBx__5__PC EQU CYREG_PRT12_PC4 +SCSI_In_DBx__5__PORT EQU 12 +SCSI_In_DBx__5__PRT EQU CYREG_PRT12_PRT +SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_In_DBx__5__PS EQU CYREG_PRT12_PS +SCSI_In_DBx__5__SHIFT EQU 4 +SCSI_In_DBx__5__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_In_DBx__5__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_In_DBx__5__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_In_DBx__5__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_In_DBx__5__SLW EQU CYREG_PRT12_SLW +SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG +SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX +SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE +SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP +SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL +SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0 +SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1 +SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2 +SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR +SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_In_DBx__6__MASK EQU 0x20 +SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC5 +SCSI_In_DBx__6__PORT EQU 2 +SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT +SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS +SCSI_In_DBx__6__SHIFT EQU 5 +SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW +SCSI_In_DBx__7__AG EQU CYREG_PRT2_AG +SCSI_In_DBx__7__AMUX EQU CYREG_PRT2_AMUX +SCSI_In_DBx__7__BIE EQU CYREG_PRT2_BIE +SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_In_DBx__7__BYP EQU CYREG_PRT2_BYP +SCSI_In_DBx__7__CTL EQU CYREG_PRT2_CTL +SCSI_In_DBx__7__DM0 EQU CYREG_PRT2_DM0 +SCSI_In_DBx__7__DM1 EQU CYREG_PRT2_DM1 +SCSI_In_DBx__7__DM2 EQU CYREG_PRT2_DM2 +SCSI_In_DBx__7__DR EQU CYREG_PRT2_DR +SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_In_DBx__7__MASK EQU 0x10 +SCSI_In_DBx__7__PC EQU CYREG_PRT2_PC4 +SCSI_In_DBx__7__PORT EQU 2 +SCSI_In_DBx__7__PRT EQU CYREG_PRT2_PRT +SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_In_DBx__7__PS EQU CYREG_PRT2_PS +SCSI_In_DBx__7__SHIFT EQU 4 +SCSI_In_DBx__7__SLW EQU CYREG_PRT2_SLW +SCSI_In_DBx__DB0__AG EQU CYREG_PRT5_AG +SCSI_In_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX +SCSI_In_DBx__DB0__BIE EQU CYREG_PRT5_BIE +SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_In_DBx__DB0__BYP EQU CYREG_PRT5_BYP +SCSI_In_DBx__DB0__CTL EQU CYREG_PRT5_CTL +SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT5_DM0 +SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT5_DM1 +SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT5_DM2 +SCSI_In_DBx__DB0__DR EQU CYREG_PRT5_DR +SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_In_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_In_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_In_DBx__DB0__MASK EQU 0x08 +SCSI_In_DBx__DB0__PC EQU CYREG_PRT5_PC3 +SCSI_In_DBx__DB0__PORT EQU 5 +SCSI_In_DBx__DB0__PRT EQU CYREG_PRT5_PRT +SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_In_DBx__DB0__PS EQU CYREG_PRT5_PS +SCSI_In_DBx__DB0__SHIFT EQU 3 +SCSI_In_DBx__DB0__SLW EQU CYREG_PRT5_SLW +SCSI_In_DBx__DB1__AG EQU CYREG_PRT5_AG +SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX +SCSI_In_DBx__DB1__BIE EQU CYREG_PRT5_BIE +SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_In_DBx__DB1__BYP EQU CYREG_PRT5_BYP +SCSI_In_DBx__DB1__CTL EQU CYREG_PRT5_CTL +SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT5_DM0 +SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT5_DM1 +SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT5_DM2 +SCSI_In_DBx__DB1__DR EQU CYREG_PRT5_DR +SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_In_DBx__DB1__MASK EQU 0x04 +SCSI_In_DBx__DB1__PC EQU CYREG_PRT5_PC2 +SCSI_In_DBx__DB1__PORT EQU 5 +SCSI_In_DBx__DB1__PRT EQU CYREG_PRT5_PRT +SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_In_DBx__DB1__PS EQU CYREG_PRT5_PS +SCSI_In_DBx__DB1__SHIFT EQU 2 +SCSI_In_DBx__DB1__SLW EQU CYREG_PRT5_SLW +SCSI_In_DBx__DB2__AG EQU CYREG_PRT6_AG +SCSI_In_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX +SCSI_In_DBx__DB2__BIE EQU CYREG_PRT6_BIE +SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In_DBx__DB2__BYP EQU CYREG_PRT6_BYP +SCSI_In_DBx__DB2__CTL EQU CYREG_PRT6_CTL +SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT6_DM0 +SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT6_DM1 +SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT6_DM2 +SCSI_In_DBx__DB2__DR EQU CYREG_PRT6_DR +SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In_DBx__DB2__MASK EQU 0x80 +SCSI_In_DBx__DB2__PC EQU CYREG_PRT6_PC7 +SCSI_In_DBx__DB2__PORT EQU 6 +SCSI_In_DBx__DB2__PRT EQU CYREG_PRT6_PRT +SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In_DBx__DB2__PS EQU CYREG_PRT6_PS +SCSI_In_DBx__DB2__SHIFT EQU 7 +SCSI_In_DBx__DB2__SLW EQU CYREG_PRT6_SLW +SCSI_In_DBx__DB3__AG EQU CYREG_PRT6_AG +SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX +SCSI_In_DBx__DB3__BIE EQU CYREG_PRT6_BIE +SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In_DBx__DB3__BYP EQU CYREG_PRT6_BYP +SCSI_In_DBx__DB3__CTL EQU CYREG_PRT6_CTL +SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT6_DM0 +SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT6_DM1 +SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT6_DM2 +SCSI_In_DBx__DB3__DR EQU CYREG_PRT6_DR +SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In_DBx__DB3__MASK EQU 0x40 +SCSI_In_DBx__DB3__PC EQU CYREG_PRT6_PC6 +SCSI_In_DBx__DB3__PORT EQU 6 +SCSI_In_DBx__DB3__PRT EQU CYREG_PRT6_PRT +SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In_DBx__DB3__PS EQU CYREG_PRT6_PS +SCSI_In_DBx__DB3__SHIFT EQU 6 +SCSI_In_DBx__DB3__SLW EQU CYREG_PRT6_SLW +SCSI_In_DBx__DB4__AG EQU CYREG_PRT12_AG +SCSI_In_DBx__DB4__BIE EQU CYREG_PRT12_BIE +SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_In_DBx__DB4__BYP EQU CYREG_PRT12_BYP +SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT12_DM0 +SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT12_DM1 +SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT12_DM2 +SCSI_In_DBx__DB4__DR EQU CYREG_PRT12_DR +SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_In_DBx__DB4__MASK EQU 0x20 +SCSI_In_DBx__DB4__PC EQU CYREG_PRT12_PC5 +SCSI_In_DBx__DB4__PORT EQU 12 +SCSI_In_DBx__DB4__PRT EQU CYREG_PRT12_PRT +SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_In_DBx__DB4__PS EQU CYREG_PRT12_PS +SCSI_In_DBx__DB4__SHIFT EQU 5 +SCSI_In_DBx__DB4__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_In_DBx__DB4__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_In_DBx__DB4__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_In_DBx__DB4__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_In_DBx__DB4__SLW EQU CYREG_PRT12_SLW +SCSI_In_DBx__DB5__AG EQU CYREG_PRT12_AG +SCSI_In_DBx__DB5__BIE EQU CYREG_PRT12_BIE +SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_In_DBx__DB5__BYP EQU CYREG_PRT12_BYP +SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT12_DM0 +SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT12_DM1 +SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT12_DM2 +SCSI_In_DBx__DB5__DR EQU CYREG_PRT12_DR +SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_In_DBx__DB5__MASK EQU 0x10 +SCSI_In_DBx__DB5__PC EQU CYREG_PRT12_PC4 +SCSI_In_DBx__DB5__PORT EQU 12 +SCSI_In_DBx__DB5__PRT EQU CYREG_PRT12_PRT +SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_In_DBx__DB5__PS EQU CYREG_PRT12_PS +SCSI_In_DBx__DB5__SHIFT EQU 4 +SCSI_In_DBx__DB5__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_In_DBx__DB5__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_In_DBx__DB5__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_In_DBx__DB5__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_In_DBx__DB5__SLW EQU CYREG_PRT12_SLW +SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG +SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX +SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE +SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP +SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL +SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0 +SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1 +SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2 +SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR +SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_In_DBx__DB6__MASK EQU 0x20 +SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC5 +SCSI_In_DBx__DB6__PORT EQU 2 +SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT +SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS +SCSI_In_DBx__DB6__SHIFT EQU 5 +SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW +SCSI_In_DBx__DB7__AG EQU CYREG_PRT2_AG +SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX +SCSI_In_DBx__DB7__BIE EQU CYREG_PRT2_BIE +SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_In_DBx__DB7__BYP EQU CYREG_PRT2_BYP +SCSI_In_DBx__DB7__CTL EQU CYREG_PRT2_CTL +SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT2_DM0 +SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT2_DM1 +SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT2_DM2 +SCSI_In_DBx__DB7__DR EQU CYREG_PRT2_DR +SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_In_DBx__DB7__MASK EQU 0x10 +SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC4 +SCSI_In_DBx__DB7__PORT EQU 2 +SCSI_In_DBx__DB7__PRT EQU CYREG_PRT2_PRT +SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS +SCSI_In_DBx__DB7__SHIFT EQU 4 +SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW + +; SD_Data_Clk +SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0 +SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1 +SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2 +SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07 +SD_Data_Clk__INDEX EQU 0x00 +SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +SD_Data_Clk__PM_ACT_MSK EQU 0x01 +SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +SD_Data_Clk__PM_STBY_MSK EQU 0x01 + +; SD_Init_Clk +SD_Init_Clk__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 +SD_Init_Clk__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 +SD_Init_Clk__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 +SD_Init_Clk__CFG2_SRC_SEL_MASK EQU 0x07 +SD_Init_Clk__INDEX EQU 0x01 +SD_Init_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +SD_Init_Clk__PM_ACT_MSK EQU 0x02 +SD_Init_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +SD_Init_Clk__PM_STBY_MSK EQU 0x02 + +; scsiTarget +scsiTarget_StatusReg__0__MASK EQU 0x01 +scsiTarget_StatusReg__0__POS EQU 0 +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST +scsiTarget_StatusReg__1__MASK EQU 0x02 +scsiTarget_StatusReg__1__POS EQU 1 +scsiTarget_StatusReg__2__MASK EQU 0x04 +scsiTarget_StatusReg__2__POS EQU 2 +scsiTarget_StatusReg__3__MASK EQU 0x08 +scsiTarget_StatusReg__3__POS EQU 3 +scsiTarget_StatusReg__MASK EQU 0x0F +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB13_MSK +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB13_ST +scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL +scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB10_11_ST +scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB10_MSK +scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL +scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB10_ST_CTL +scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB10_ST_CTL +scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB10_ST +scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL +scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL +scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL +scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL +scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL +scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK +scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK +scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL +scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB10_CTL +scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL +scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB10_CTL +scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL +scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB10_MSK +scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB10_11_A0 +scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB10_11_A1 +scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB10_11_D0 +scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB10_11_D1 +scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL +scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB10_11_F0 +scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB10_11_F1 +scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB10_A0_A1 +scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB10_A0 +scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB10_A1 +scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB10_D0_D1 +scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB10_D0 +scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB10_D1 +scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL +scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB10_F0_F1 +scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB10_F0 +scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB10_F1 +scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL + +; SD_Clk_Ctl +SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 +SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0 +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK +SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL +SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL +SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL +SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL +SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01 +SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK +SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL + +; USBFS_ep_0 +USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_0__INTC_MASK EQU 0x1000000 +USBFS_ep_0__INTC_NUMBER EQU 24 +USBFS_ep_0__INTC_PRIOR_NUM EQU 7 +USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24 +USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; USBFS_ep_1 +USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_1__INTC_MASK EQU 0x01 +USBFS_ep_1__INTC_NUMBER EQU 0 +USBFS_ep_1__INTC_PRIOR_NUM EQU 7 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 +USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; USBFS_ep_2 +USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_2__INTC_MASK EQU 0x02 +USBFS_ep_2__INTC_NUMBER EQU 1 +USBFS_ep_2__INTC_PRIOR_NUM EQU 7 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 +USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; USBFS_USB +USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG +USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG +USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN +USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR +USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG +USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN +USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR +USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG +USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN +USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR +USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG +USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN +USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR +USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG +USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN +USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR +USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG +USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN +USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR +USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG +USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN +USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR +USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG +USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN +USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR +USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN +USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR +USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR +USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA +USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB +USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA +USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB +USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR +USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA +USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB +USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA +USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB +USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR +USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA +USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB +USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA +USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB +USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR +USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA +USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB +USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA +USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB +USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR +USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA +USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB +USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA +USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB +USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR +USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA +USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB +USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA +USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB +USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR +USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA +USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB +USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA +USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB +USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR +USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA +USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB +USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA +USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB +USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE +USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT +USBFS_USB__CR0 EQU CYREG_USB_CR0 +USBFS_USB__CR1 EQU CYREG_USB_CR1 +USBFS_USB__CWA EQU CYREG_USB_CWA +USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB +USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES +USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB +USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG +USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT +USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR +USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0 +USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1 +USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2 +USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3 +USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4 +USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5 +USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6 +USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7 +USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE +USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE +USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE +USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5 +USBFS_USB__PM_ACT_MSK EQU 0x01 +USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5 +USBFS_USB__PM_STBY_MSK EQU 0x01 +USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0 +USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1 +USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0 +USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0 +USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1 +USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0 +USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0 +USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1 +USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0 +USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0 +USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1 +USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0 +USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0 +USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1 +USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0 +USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0 +USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1 +USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0 +USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0 +USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1 +USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0 +USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0 +USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1 +USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0 +USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN +USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR +USBFS_USB__SOF0 EQU CYREG_USB_SOF0 +USBFS_USB__SOF1 EQU CYREG_USB_SOF1 +USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 +USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 +USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN + +; SCSI_ATN +SCSI_ATN__0__MASK EQU 0x01 +SCSI_ATN__0__PC EQU CYREG_PRT2_PC0 +SCSI_ATN__0__PORT EQU 2 +SCSI_ATN__0__SHIFT EQU 0 +SCSI_ATN__AG EQU CYREG_PRT2_AG +SCSI_ATN__AMUX EQU CYREG_PRT2_AMUX +SCSI_ATN__BIE EQU CYREG_PRT2_BIE +SCSI_ATN__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_ATN__BYP EQU CYREG_PRT2_BYP +SCSI_ATN__CTL EQU CYREG_PRT2_CTL +SCSI_ATN__DM0 EQU CYREG_PRT2_DM0 +SCSI_ATN__DM1 EQU CYREG_PRT2_DM1 +SCSI_ATN__DM2 EQU CYREG_PRT2_DM2 +SCSI_ATN__DR EQU CYREG_PRT2_DR +SCSI_ATN__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_ATN__INT__MASK EQU 0x01 +SCSI_ATN__INT__PC EQU CYREG_PRT2_PC0 +SCSI_ATN__INT__PORT EQU 2 +SCSI_ATN__INT__SHIFT EQU 0 +SCSI_ATN__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_ATN__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_ATN__MASK EQU 0x01 +SCSI_ATN__PORT EQU 2 +SCSI_ATN__PRT EQU CYREG_PRT2_PRT +SCSI_ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_ATN__PS EQU CYREG_PRT2_PS +SCSI_ATN__SHIFT EQU 0 +SCSI_ATN__SLW EQU CYREG_PRT2_SLW + +; SCSI_Out +SCSI_Out__0__AG EQU CYREG_PRT15_AG +SCSI_Out__0__AMUX EQU CYREG_PRT15_AMUX +SCSI_Out__0__BIE EQU CYREG_PRT15_BIE +SCSI_Out__0__BIT_MASK EQU CYREG_PRT15_BIT_MASK +SCSI_Out__0__BYP EQU CYREG_PRT15_BYP +SCSI_Out__0__CTL EQU CYREG_PRT15_CTL +SCSI_Out__0__DM0 EQU CYREG_PRT15_DM0 +SCSI_Out__0__DM1 EQU CYREG_PRT15_DM1 +SCSI_Out__0__DM2 EQU CYREG_PRT15_DM2 +SCSI_Out__0__DR EQU CYREG_PRT15_DR +SCSI_Out__0__INP_DIS EQU CYREG_PRT15_INP_DIS +SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +SCSI_Out__0__LCD_EN EQU CYREG_PRT15_LCD_EN +SCSI_Out__0__MASK EQU 0x20 +SCSI_Out__0__PC EQU CYREG_IO_PC_PRT15_PC5 +SCSI_Out__0__PORT EQU 15 +SCSI_Out__0__PRT EQU CYREG_PRT15_PRT +SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +SCSI_Out__0__PS EQU CYREG_PRT15_PS +SCSI_Out__0__SHIFT EQU 5 +SCSI_Out__0__SLW EQU CYREG_PRT15_SLW +SCSI_Out__1__AG EQU CYREG_PRT15_AG +SCSI_Out__1__AMUX EQU CYREG_PRT15_AMUX +SCSI_Out__1__BIE EQU CYREG_PRT15_BIE +SCSI_Out__1__BIT_MASK EQU CYREG_PRT15_BIT_MASK +SCSI_Out__1__BYP EQU CYREG_PRT15_BYP +SCSI_Out__1__CTL EQU CYREG_PRT15_CTL +SCSI_Out__1__DM0 EQU CYREG_PRT15_DM0 +SCSI_Out__1__DM1 EQU CYREG_PRT15_DM1 +SCSI_Out__1__DM2 EQU CYREG_PRT15_DM2 +SCSI_Out__1__DR EQU CYREG_PRT15_DR +SCSI_Out__1__INP_DIS EQU CYREG_PRT15_INP_DIS +SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +SCSI_Out__1__LCD_EN EQU CYREG_PRT15_LCD_EN +SCSI_Out__1__MASK EQU 0x10 +SCSI_Out__1__PC EQU CYREG_IO_PC_PRT15_PC4 +SCSI_Out__1__PORT EQU 15 +SCSI_Out__1__PRT EQU CYREG_PRT15_PRT +SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +SCSI_Out__1__PS EQU CYREG_PRT15_PS +SCSI_Out__1__SHIFT EQU 4 +SCSI_Out__1__SLW EQU CYREG_PRT15_SLW +SCSI_Out__2__AG EQU CYREG_PRT6_AG +SCSI_Out__2__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out__2__BIE EQU CYREG_PRT6_BIE +SCSI_Out__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out__2__BYP EQU CYREG_PRT6_BYP +SCSI_Out__2__CTL EQU CYREG_PRT6_CTL +SCSI_Out__2__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out__2__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out__2__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out__2__DR EQU CYREG_PRT6_DR +SCSI_Out__2__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out__2__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out__2__MASK EQU 0x02 +SCSI_Out__2__PC EQU CYREG_PRT6_PC1 +SCSI_Out__2__PORT EQU 6 +SCSI_Out__2__PRT EQU CYREG_PRT6_PRT +SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out__2__PS EQU CYREG_PRT6_PS +SCSI_Out__2__SHIFT EQU 1 +SCSI_Out__2__SLW EQU CYREG_PRT6_SLW +SCSI_Out__3__AG EQU CYREG_PRT6_AG +SCSI_Out__3__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out__3__BIE EQU CYREG_PRT6_BIE +SCSI_Out__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out__3__BYP EQU CYREG_PRT6_BYP +SCSI_Out__3__CTL EQU CYREG_PRT6_CTL +SCSI_Out__3__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out__3__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out__3__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out__3__DR EQU CYREG_PRT6_DR +SCSI_Out__3__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out__3__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out__3__MASK EQU 0x01 +SCSI_Out__3__PC EQU CYREG_PRT6_PC0 +SCSI_Out__3__PORT EQU 6 +SCSI_Out__3__PRT EQU CYREG_PRT6_PRT +SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out__3__PS EQU CYREG_PRT6_PS +SCSI_Out__3__SHIFT EQU 0 +SCSI_Out__3__SLW EQU CYREG_PRT6_SLW +SCSI_Out__4__AG EQU CYREG_PRT4_AG +SCSI_Out__4__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__4__BIE EQU CYREG_PRT4_BIE +SCSI_Out__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__4__BYP EQU CYREG_PRT4_BYP +SCSI_Out__4__CTL EQU CYREG_PRT4_CTL +SCSI_Out__4__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__4__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__4__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__4__DR EQU CYREG_PRT4_DR +SCSI_Out__4__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__4__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__4__MASK EQU 0x20 +SCSI_Out__4__PC EQU CYREG_PRT4_PC5 +SCSI_Out__4__PORT EQU 4 +SCSI_Out__4__PRT EQU CYREG_PRT4_PRT +SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__4__PS EQU CYREG_PRT4_PS +SCSI_Out__4__SHIFT EQU 5 +SCSI_Out__4__SLW EQU CYREG_PRT4_SLW +SCSI_Out__5__AG EQU CYREG_PRT4_AG +SCSI_Out__5__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__5__BIE EQU CYREG_PRT4_BIE +SCSI_Out__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__5__BYP EQU CYREG_PRT4_BYP +SCSI_Out__5__CTL EQU CYREG_PRT4_CTL +SCSI_Out__5__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__5__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__5__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__5__DR EQU CYREG_PRT4_DR +SCSI_Out__5__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__5__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__5__MASK EQU 0x10 +SCSI_Out__5__PC EQU CYREG_PRT4_PC4 +SCSI_Out__5__PORT EQU 4 +SCSI_Out__5__PRT EQU CYREG_PRT4_PRT +SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__5__PS EQU CYREG_PRT4_PS +SCSI_Out__5__SHIFT EQU 4 +SCSI_Out__5__SLW EQU CYREG_PRT4_SLW +SCSI_Out__6__AG EQU CYREG_PRT0_AG +SCSI_Out__6__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__6__BIE EQU CYREG_PRT0_BIE +SCSI_Out__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__6__BYP EQU CYREG_PRT0_BYP +SCSI_Out__6__CTL EQU CYREG_PRT0_CTL +SCSI_Out__6__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__6__DR EQU CYREG_PRT0_DR +SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__6__MASK EQU 0x80 +SCSI_Out__6__PC EQU CYREG_PRT0_PC7 +SCSI_Out__6__PORT EQU 0 +SCSI_Out__6__PRT EQU CYREG_PRT0_PRT +SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__6__PS EQU CYREG_PRT0_PS +SCSI_Out__6__SHIFT EQU 7 +SCSI_Out__6__SLW EQU CYREG_PRT0_SLW +SCSI_Out__7__AG EQU CYREG_PRT0_AG +SCSI_Out__7__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__7__BIE EQU CYREG_PRT0_BIE +SCSI_Out__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__7__BYP EQU CYREG_PRT0_BYP +SCSI_Out__7__CTL EQU CYREG_PRT0_CTL +SCSI_Out__7__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__7__DR EQU CYREG_PRT0_DR +SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__7__MASK EQU 0x40 +SCSI_Out__7__PC EQU CYREG_PRT0_PC6 +SCSI_Out__7__PORT EQU 0 +SCSI_Out__7__PRT EQU CYREG_PRT0_PRT +SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__7__PS EQU CYREG_PRT0_PS +SCSI_Out__7__SHIFT EQU 6 +SCSI_Out__7__SLW EQU CYREG_PRT0_SLW +SCSI_Out__8__AG EQU CYREG_PRT0_AG +SCSI_Out__8__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__8__BIE EQU CYREG_PRT0_BIE +SCSI_Out__8__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__8__BYP EQU CYREG_PRT0_BYP +SCSI_Out__8__CTL EQU CYREG_PRT0_CTL +SCSI_Out__8__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__8__DR EQU CYREG_PRT0_DR +SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__8__MASK EQU 0x08 +SCSI_Out__8__PC EQU CYREG_PRT0_PC3 +SCSI_Out__8__PORT EQU 0 +SCSI_Out__8__PRT EQU CYREG_PRT0_PRT +SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__8__PS EQU CYREG_PRT0_PS +SCSI_Out__8__SHIFT EQU 3 +SCSI_Out__8__SLW EQU CYREG_PRT0_SLW +SCSI_Out__9__AG EQU CYREG_PRT0_AG +SCSI_Out__9__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__9__BIE EQU CYREG_PRT0_BIE +SCSI_Out__9__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__9__BYP EQU CYREG_PRT0_BYP +SCSI_Out__9__CTL EQU CYREG_PRT0_CTL +SCSI_Out__9__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__9__DR EQU CYREG_PRT0_DR +SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__9__MASK EQU 0x04 +SCSI_Out__9__PC EQU CYREG_PRT0_PC2 +SCSI_Out__9__PORT EQU 0 +SCSI_Out__9__PRT EQU CYREG_PRT0_PRT +SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__9__PS EQU CYREG_PRT0_PS +SCSI_Out__9__SHIFT EQU 2 +SCSI_Out__9__SLW EQU CYREG_PRT0_SLW +SCSI_Out__ACK__AG EQU CYREG_PRT6_AG +SCSI_Out__ACK__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out__ACK__BIE EQU CYREG_PRT6_BIE +SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out__ACK__BYP EQU CYREG_PRT6_BYP +SCSI_Out__ACK__CTL EQU CYREG_PRT6_CTL +SCSI_Out__ACK__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out__ACK__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out__ACK__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out__ACK__DR EQU CYREG_PRT6_DR +SCSI_Out__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out__ACK__MASK EQU 0x01 +SCSI_Out__ACK__PC EQU CYREG_PRT6_PC0 +SCSI_Out__ACK__PORT EQU 6 +SCSI_Out__ACK__PRT EQU CYREG_PRT6_PRT +SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out__ACK__PS EQU CYREG_PRT6_PS +SCSI_Out__ACK__SHIFT EQU 0 +SCSI_Out__ACK__SLW EQU CYREG_PRT6_SLW +SCSI_Out__ATN__AG EQU CYREG_PRT15_AG +SCSI_Out__ATN__AMUX EQU CYREG_PRT15_AMUX +SCSI_Out__ATN__BIE EQU CYREG_PRT15_BIE +SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT15_BIT_MASK +SCSI_Out__ATN__BYP EQU CYREG_PRT15_BYP +SCSI_Out__ATN__CTL EQU CYREG_PRT15_CTL +SCSI_Out__ATN__DM0 EQU CYREG_PRT15_DM0 +SCSI_Out__ATN__DM1 EQU CYREG_PRT15_DM1 +SCSI_Out__ATN__DM2 EQU CYREG_PRT15_DM2 +SCSI_Out__ATN__DR EQU CYREG_PRT15_DR +SCSI_Out__ATN__INP_DIS EQU CYREG_PRT15_INP_DIS +SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +SCSI_Out__ATN__LCD_EN EQU CYREG_PRT15_LCD_EN +SCSI_Out__ATN__MASK EQU 0x10 +SCSI_Out__ATN__PC EQU CYREG_IO_PC_PRT15_PC4 +SCSI_Out__ATN__PORT EQU 15 +SCSI_Out__ATN__PRT EQU CYREG_PRT15_PRT +SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +SCSI_Out__ATN__PS EQU CYREG_PRT15_PS +SCSI_Out__ATN__SHIFT EQU 4 +SCSI_Out__ATN__SLW EQU CYREG_PRT15_SLW +SCSI_Out__BSY__AG EQU CYREG_PRT6_AG +SCSI_Out__BSY__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out__BSY__BIE EQU CYREG_PRT6_BIE +SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out__BSY__BYP EQU CYREG_PRT6_BYP +SCSI_Out__BSY__CTL EQU CYREG_PRT6_CTL +SCSI_Out__BSY__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out__BSY__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out__BSY__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out__BSY__DR EQU CYREG_PRT6_DR +SCSI_Out__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out__BSY__MASK EQU 0x02 +SCSI_Out__BSY__PC EQU CYREG_PRT6_PC1 +SCSI_Out__BSY__PORT EQU 6 +SCSI_Out__BSY__PRT EQU CYREG_PRT6_PRT +SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out__BSY__PS EQU CYREG_PRT6_PS +SCSI_Out__BSY__SHIFT EQU 1 +SCSI_Out__BSY__SLW EQU CYREG_PRT6_SLW +SCSI_Out__CD__AG EQU CYREG_PRT0_AG +SCSI_Out__CD__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__CD__BIE EQU CYREG_PRT0_BIE +SCSI_Out__CD__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__CD__BYP EQU CYREG_PRT0_BYP +SCSI_Out__CD__CTL EQU CYREG_PRT0_CTL +SCSI_Out__CD__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__CD__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__CD__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__CD__DR EQU CYREG_PRT0_DR +SCSI_Out__CD__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__CD__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__CD__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__CD__MASK EQU 0x40 +SCSI_Out__CD__PC EQU CYREG_PRT0_PC6 +SCSI_Out__CD__PORT EQU 0 +SCSI_Out__CD__PRT EQU CYREG_PRT0_PRT +SCSI_Out__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__CD__PS EQU CYREG_PRT0_PS +SCSI_Out__CD__SHIFT EQU 6 +SCSI_Out__CD__SLW EQU CYREG_PRT0_SLW +SCSI_Out__DBP_raw__AG EQU CYREG_PRT15_AG +SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT15_AMUX +SCSI_Out__DBP_raw__BIE EQU CYREG_PRT15_BIE +SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT15_BIT_MASK +SCSI_Out__DBP_raw__BYP EQU CYREG_PRT15_BYP +SCSI_Out__DBP_raw__CTL EQU CYREG_PRT15_CTL +SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT15_DM0 +SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT15_DM1 +SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT15_DM2 +SCSI_Out__DBP_raw__DR EQU CYREG_PRT15_DR +SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT15_INP_DIS +SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT15_LCD_EN +SCSI_Out__DBP_raw__MASK EQU 0x20 +SCSI_Out__DBP_raw__PC EQU CYREG_IO_PC_PRT15_PC5 +SCSI_Out__DBP_raw__PORT EQU 15 +SCSI_Out__DBP_raw__PRT EQU CYREG_PRT15_PRT +SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +SCSI_Out__DBP_raw__PS EQU CYREG_PRT15_PS +SCSI_Out__DBP_raw__SHIFT EQU 5 +SCSI_Out__DBP_raw__SLW EQU CYREG_PRT15_SLW +SCSI_Out__IO_raw__AG EQU CYREG_PRT0_AG +SCSI_Out__IO_raw__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__IO_raw__BIE EQU CYREG_PRT0_BIE +SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__IO_raw__BYP EQU CYREG_PRT0_BYP +SCSI_Out__IO_raw__CTL EQU CYREG_PRT0_CTL +SCSI_Out__IO_raw__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR +SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__IO_raw__MASK EQU 0x04 +SCSI_Out__IO_raw__PC EQU CYREG_PRT0_PC2 +SCSI_Out__IO_raw__PORT EQU 0 +SCSI_Out__IO_raw__PRT EQU CYREG_PRT0_PRT +SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS +SCSI_Out__IO_raw__SHIFT EQU 2 +SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW +SCSI_Out__MSG__AG EQU CYREG_PRT4_AG +SCSI_Out__MSG__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__MSG__BIE EQU CYREG_PRT4_BIE +SCSI_Out__MSG__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__MSG__BYP EQU CYREG_PRT4_BYP +SCSI_Out__MSG__CTL EQU CYREG_PRT4_CTL +SCSI_Out__MSG__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__MSG__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__MSG__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__MSG__DR EQU CYREG_PRT4_DR +SCSI_Out__MSG__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__MSG__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__MSG__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__MSG__MASK EQU 0x10 +SCSI_Out__MSG__PC EQU CYREG_PRT4_PC4 +SCSI_Out__MSG__PORT EQU 4 +SCSI_Out__MSG__PRT EQU CYREG_PRT4_PRT +SCSI_Out__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__MSG__PS EQU CYREG_PRT4_PS +SCSI_Out__MSG__SHIFT EQU 4 +SCSI_Out__MSG__SLW EQU CYREG_PRT4_SLW +SCSI_Out__REQ__AG EQU CYREG_PRT0_AG +SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE +SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__REQ__BYP EQU CYREG_PRT0_BYP +SCSI_Out__REQ__CTL EQU CYREG_PRT0_CTL +SCSI_Out__REQ__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__REQ__DR EQU CYREG_PRT0_DR +SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__REQ__MASK EQU 0x08 +SCSI_Out__REQ__PC EQU CYREG_PRT0_PC3 +SCSI_Out__REQ__PORT EQU 0 +SCSI_Out__REQ__PRT EQU CYREG_PRT0_PRT +SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__REQ__PS EQU CYREG_PRT0_PS +SCSI_Out__REQ__SHIFT EQU 3 +SCSI_Out__REQ__SLW EQU CYREG_PRT0_SLW +SCSI_Out__RST__AG EQU CYREG_PRT4_AG +SCSI_Out__RST__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__RST__BIE EQU CYREG_PRT4_BIE +SCSI_Out__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__RST__BYP EQU CYREG_PRT4_BYP +SCSI_Out__RST__CTL EQU CYREG_PRT4_CTL +SCSI_Out__RST__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__RST__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__RST__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__RST__DR EQU CYREG_PRT4_DR +SCSI_Out__RST__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__RST__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__RST__MASK EQU 0x20 +SCSI_Out__RST__PC EQU CYREG_PRT4_PC5 +SCSI_Out__RST__PORT EQU 4 +SCSI_Out__RST__PRT EQU CYREG_PRT4_PRT +SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__RST__PS EQU CYREG_PRT4_PS +SCSI_Out__RST__SHIFT EQU 5 +SCSI_Out__RST__SLW EQU CYREG_PRT4_SLW +SCSI_Out__SEL__AG EQU CYREG_PRT0_AG +SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE +SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP +SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL +SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__SEL__DR EQU CYREG_PRT0_DR +SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__SEL__MASK EQU 0x80 +SCSI_Out__SEL__PC EQU CYREG_PRT0_PC7 +SCSI_Out__SEL__PORT EQU 0 +SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT +SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__SEL__PS EQU CYREG_PRT0_PS +SCSI_Out__SEL__SHIFT EQU 7 +SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW + +; SCSI_RST +SCSI_RST__0__MASK EQU 0x80 +SCSI_RST__0__PC EQU CYREG_PRT4_PC7 +SCSI_RST__0__PORT EQU 4 +SCSI_RST__0__SHIFT EQU 7 +SCSI_RST__AG EQU CYREG_PRT4_AG +SCSI_RST__AMUX EQU CYREG_PRT4_AMUX +SCSI_RST__BIE EQU CYREG_PRT4_BIE +SCSI_RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_RST__BYP EQU CYREG_PRT4_BYP +SCSI_RST__CTL EQU CYREG_PRT4_CTL +SCSI_RST__DM0 EQU CYREG_PRT4_DM0 +SCSI_RST__DM1 EQU CYREG_PRT4_DM1 +SCSI_RST__DM2 EQU CYREG_PRT4_DM2 +SCSI_RST__DR EQU CYREG_PRT4_DR +SCSI_RST__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_RST__INTSTAT EQU CYREG_PICU4_INTSTAT +SCSI_RST__INT__MASK EQU 0x80 +SCSI_RST__INT__PC EQU CYREG_PRT4_PC7 +SCSI_RST__INT__PORT EQU 4 +SCSI_RST__INT__SHIFT EQU 7 +SCSI_RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_RST__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_RST__MASK EQU 0x80 +SCSI_RST__PORT EQU 4 +SCSI_RST__PRT EQU CYREG_PRT4_PRT +SCSI_RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_RST__PS EQU CYREG_PRT4_PS +SCSI_RST__SHIFT EQU 7 +SCSI_RST__SLW EQU CYREG_PRT4_SLW +SCSI_RST__SNAP EQU CYREG_PICU4_SNAP + +; USBFS_Dm +USBFS_Dm__0__MASK EQU 0x80 +USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 +USBFS_Dm__0__PORT EQU 15 +USBFS_Dm__0__SHIFT EQU 7 +USBFS_Dm__AG EQU CYREG_PRT15_AG +USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dm__BIE EQU CYREG_PRT15_BIE +USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dm__BYP EQU CYREG_PRT15_BYP +USBFS_Dm__CTL EQU CYREG_PRT15_CTL +USBFS_Dm__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dm__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dm__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dm__DR EQU CYREG_PRT15_DR +USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dm__MASK EQU 0x80 +USBFS_Dm__PORT EQU 15 +USBFS_Dm__PRT EQU CYREG_PRT15_PRT +USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dm__PS EQU CYREG_PRT15_PS +USBFS_Dm__SHIFT EQU 7 +USBFS_Dm__SLW EQU CYREG_PRT15_SLW + +; USBFS_Dp +USBFS_Dp__0__MASK EQU 0x40 +USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0 +USBFS_Dp__0__PORT EQU 15 +USBFS_Dp__0__SHIFT EQU 6 +USBFS_Dp__AG EQU CYREG_PRT15_AG +USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dp__BIE EQU CYREG_PRT15_BIE +USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dp__BYP EQU CYREG_PRT15_BYP +USBFS_Dp__CTL EQU CYREG_PRT15_CTL +USBFS_Dp__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dp__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dp__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dp__DR EQU CYREG_PRT15_DR +USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT +USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dp__MASK EQU 0x40 +USBFS_Dp__PORT EQU 15 +USBFS_Dp__PRT EQU CYREG_PRT15_PRT +USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dp__PS EQU CYREG_PRT15_PS +USBFS_Dp__SHIFT EQU 6 +USBFS_Dp__SLW EQU CYREG_PRT15_SLW +USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15 + +; SCSI_In +SCSI_In__0__AG EQU CYREG_PRT2_AG +SCSI_In__0__AMUX EQU CYREG_PRT2_AMUX +SCSI_In__0__BIE EQU CYREG_PRT2_BIE +SCSI_In__0__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_In__0__BYP EQU CYREG_PRT2_BYP +SCSI_In__0__CTL EQU CYREG_PRT2_CTL +SCSI_In__0__DM0 EQU CYREG_PRT2_DM0 +SCSI_In__0__DM1 EQU CYREG_PRT2_DM1 +SCSI_In__0__DM2 EQU CYREG_PRT2_DM2 +SCSI_In__0__DR EQU CYREG_PRT2_DR +SCSI_In__0__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_In__0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_In__0__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_In__0__MASK EQU 0x02 +SCSI_In__0__PC EQU CYREG_PRT2_PC1 +SCSI_In__0__PORT EQU 2 +SCSI_In__0__PRT EQU CYREG_PRT2_PRT +SCSI_In__0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_In__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_In__0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_In__0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_In__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_In__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_In__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_In__0__PS EQU CYREG_PRT2_PS +SCSI_In__0__SHIFT EQU 1 +SCSI_In__0__SLW EQU CYREG_PRT2_SLW +SCSI_In__1__AG EQU CYREG_PRT6_AG +SCSI_In__1__AMUX EQU CYREG_PRT6_AMUX +SCSI_In__1__BIE EQU CYREG_PRT6_BIE +SCSI_In__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In__1__BYP EQU CYREG_PRT6_BYP +SCSI_In__1__CTL EQU CYREG_PRT6_CTL +SCSI_In__1__DM0 EQU CYREG_PRT6_DM0 +SCSI_In__1__DM1 EQU CYREG_PRT6_DM1 +SCSI_In__1__DM2 EQU CYREG_PRT6_DM2 +SCSI_In__1__DR EQU CYREG_PRT6_DR +SCSI_In__1__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In__1__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In__1__MASK EQU 0x08 +SCSI_In__1__PC EQU CYREG_PRT6_PC3 +SCSI_In__1__PORT EQU 6 +SCSI_In__1__PRT EQU CYREG_PRT6_PRT +SCSI_In__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In__1__PS EQU CYREG_PRT6_PS +SCSI_In__1__SHIFT EQU 3 +SCSI_In__1__SLW EQU CYREG_PRT6_SLW +SCSI_In__2__AG EQU CYREG_PRT6_AG +SCSI_In__2__AMUX EQU CYREG_PRT6_AMUX +SCSI_In__2__BIE EQU CYREG_PRT6_BIE +SCSI_In__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In__2__BYP EQU CYREG_PRT6_BYP +SCSI_In__2__CTL EQU CYREG_PRT6_CTL +SCSI_In__2__DM0 EQU CYREG_PRT6_DM0 +SCSI_In__2__DM1 EQU CYREG_PRT6_DM1 +SCSI_In__2__DM2 EQU CYREG_PRT6_DM2 +SCSI_In__2__DR EQU CYREG_PRT6_DR +SCSI_In__2__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In__2__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In__2__MASK EQU 0x04 +SCSI_In__2__PC EQU CYREG_PRT6_PC2 +SCSI_In__2__PORT EQU 6 +SCSI_In__2__PRT EQU CYREG_PRT6_PRT +SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In__2__PS EQU CYREG_PRT6_PS +SCSI_In__2__SHIFT EQU 2 +SCSI_In__2__SLW EQU CYREG_PRT6_SLW +SCSI_In__3__AG EQU CYREG_PRT4_AG +SCSI_In__3__AMUX EQU CYREG_PRT4_AMUX +SCSI_In__3__BIE EQU CYREG_PRT4_BIE +SCSI_In__3__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_In__3__BYP EQU CYREG_PRT4_BYP +SCSI_In__3__CTL EQU CYREG_PRT4_CTL +SCSI_In__3__DM0 EQU CYREG_PRT4_DM0 +SCSI_In__3__DM1 EQU CYREG_PRT4_DM1 +SCSI_In__3__DM2 EQU CYREG_PRT4_DM2 +SCSI_In__3__DR EQU CYREG_PRT4_DR +SCSI_In__3__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_In__3__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_In__3__MASK EQU 0x40 +SCSI_In__3__PC EQU CYREG_PRT4_PC6 +SCSI_In__3__PORT EQU 4 +SCSI_In__3__PRT EQU CYREG_PRT4_PRT +SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_In__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_In__3__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_In__3__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_In__3__PS EQU CYREG_PRT4_PS +SCSI_In__3__SHIFT EQU 6 +SCSI_In__3__SLW EQU CYREG_PRT4_SLW +SCSI_In__4__AG EQU CYREG_PRT4_AG +SCSI_In__4__AMUX EQU CYREG_PRT4_AMUX +SCSI_In__4__BIE EQU CYREG_PRT4_BIE +SCSI_In__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_In__4__BYP EQU CYREG_PRT4_BYP +SCSI_In__4__CTL EQU CYREG_PRT4_CTL +SCSI_In__4__DM0 EQU CYREG_PRT4_DM0 +SCSI_In__4__DM1 EQU CYREG_PRT4_DM1 +SCSI_In__4__DM2 EQU CYREG_PRT4_DM2 +SCSI_In__4__DR EQU CYREG_PRT4_DR +SCSI_In__4__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_In__4__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_In__4__MASK EQU 0x08 +SCSI_In__4__PC EQU CYREG_PRT4_PC3 +SCSI_In__4__PORT EQU 4 +SCSI_In__4__PRT EQU CYREG_PRT4_PRT +SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_In__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_In__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_In__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_In__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_In__4__PS EQU CYREG_PRT4_PS +SCSI_In__4__SHIFT EQU 3 +SCSI_In__4__SLW EQU CYREG_PRT4_SLW +SCSI_In__5__AG EQU CYREG_PRT4_AG +SCSI_In__5__AMUX EQU CYREG_PRT4_AMUX +SCSI_In__5__BIE EQU CYREG_PRT4_BIE +SCSI_In__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_In__5__BYP EQU CYREG_PRT4_BYP +SCSI_In__5__CTL EQU CYREG_PRT4_CTL +SCSI_In__5__DM0 EQU CYREG_PRT4_DM0 +SCSI_In__5__DM1 EQU CYREG_PRT4_DM1 +SCSI_In__5__DM2 EQU CYREG_PRT4_DM2 +SCSI_In__5__DR EQU CYREG_PRT4_DR +SCSI_In__5__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_In__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_In__5__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_In__5__MASK EQU 0x04 +SCSI_In__5__PC EQU CYREG_PRT4_PC2 +SCSI_In__5__PORT EQU 4 +SCSI_In__5__PRT EQU CYREG_PRT4_PRT +SCSI_In__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_In__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_In__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_In__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_In__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_In__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_In__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_In__5__PS EQU CYREG_PRT4_PS +SCSI_In__5__SHIFT EQU 2 +SCSI_In__5__SLW EQU CYREG_PRT4_SLW +SCSI_In__6__AG EQU CYREG_PRT0_AG +SCSI_In__6__AMUX EQU CYREG_PRT0_AMUX +SCSI_In__6__BIE EQU CYREG_PRT0_BIE +SCSI_In__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_In__6__BYP EQU CYREG_PRT0_BYP +SCSI_In__6__CTL EQU CYREG_PRT0_CTL +SCSI_In__6__DM0 EQU CYREG_PRT0_DM0 +SCSI_In__6__DM1 EQU CYREG_PRT0_DM1 +SCSI_In__6__DM2 EQU CYREG_PRT0_DM2 +SCSI_In__6__DR EQU CYREG_PRT0_DR +SCSI_In__6__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_In__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_In__6__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_In__6__MASK EQU 0x20 +SCSI_In__6__PC EQU CYREG_PRT0_PC5 +SCSI_In__6__PORT EQU 0 +SCSI_In__6__PRT EQU CYREG_PRT0_PRT +SCSI_In__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_In__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_In__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_In__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_In__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_In__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_In__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_In__6__PS EQU CYREG_PRT0_PS +SCSI_In__6__SHIFT EQU 5 +SCSI_In__6__SLW EQU CYREG_PRT0_SLW +SCSI_In__7__AG EQU CYREG_PRT0_AG +SCSI_In__7__AMUX EQU CYREG_PRT0_AMUX +SCSI_In__7__BIE EQU CYREG_PRT0_BIE +SCSI_In__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_In__7__BYP EQU CYREG_PRT0_BYP +SCSI_In__7__CTL EQU CYREG_PRT0_CTL +SCSI_In__7__DM0 EQU CYREG_PRT0_DM0 +SCSI_In__7__DM1 EQU CYREG_PRT0_DM1 +SCSI_In__7__DM2 EQU CYREG_PRT0_DM2 +SCSI_In__7__DR EQU CYREG_PRT0_DR +SCSI_In__7__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_In__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_In__7__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_In__7__MASK EQU 0x10 +SCSI_In__7__PC EQU CYREG_PRT0_PC4 +SCSI_In__7__PORT EQU 0 +SCSI_In__7__PRT EQU CYREG_PRT0_PRT +SCSI_In__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_In__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_In__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_In__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_In__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_In__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_In__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_In__7__PS EQU CYREG_PRT0_PS +SCSI_In__7__SHIFT EQU 4 +SCSI_In__7__SLW EQU CYREG_PRT0_SLW +SCSI_In__ACK__AG EQU CYREG_PRT6_AG +SCSI_In__ACK__AMUX EQU CYREG_PRT6_AMUX +SCSI_In__ACK__BIE EQU CYREG_PRT6_BIE +SCSI_In__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In__ACK__BYP EQU CYREG_PRT6_BYP +SCSI_In__ACK__CTL EQU CYREG_PRT6_CTL +SCSI_In__ACK__DM0 EQU CYREG_PRT6_DM0 +SCSI_In__ACK__DM1 EQU CYREG_PRT6_DM1 +SCSI_In__ACK__DM2 EQU CYREG_PRT6_DM2 +SCSI_In__ACK__DR EQU CYREG_PRT6_DR +SCSI_In__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In__ACK__MASK EQU 0x04 +SCSI_In__ACK__PC EQU CYREG_PRT6_PC2 +SCSI_In__ACK__PORT EQU 6 +SCSI_In__ACK__PRT EQU CYREG_PRT6_PRT +SCSI_In__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In__ACK__PS EQU CYREG_PRT6_PS +SCSI_In__ACK__SHIFT EQU 2 +SCSI_In__ACK__SLW EQU CYREG_PRT6_SLW +SCSI_In__BSY__AG EQU CYREG_PRT6_AG +SCSI_In__BSY__AMUX EQU CYREG_PRT6_AMUX +SCSI_In__BSY__BIE EQU CYREG_PRT6_BIE +SCSI_In__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In__BSY__BYP EQU CYREG_PRT6_BYP +SCSI_In__BSY__CTL EQU CYREG_PRT6_CTL +SCSI_In__BSY__DM0 EQU CYREG_PRT6_DM0 +SCSI_In__BSY__DM1 EQU CYREG_PRT6_DM1 +SCSI_In__BSY__DM2 EQU CYREG_PRT6_DM2 +SCSI_In__BSY__DR EQU CYREG_PRT6_DR +SCSI_In__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In__BSY__MASK EQU 0x08 +SCSI_In__BSY__PC EQU CYREG_PRT6_PC3 +SCSI_In__BSY__PORT EQU 6 +SCSI_In__BSY__PRT EQU CYREG_PRT6_PRT +SCSI_In__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In__BSY__PS EQU CYREG_PRT6_PS +SCSI_In__BSY__SHIFT EQU 3 +SCSI_In__BSY__SLW EQU CYREG_PRT6_SLW +SCSI_In__CD__AG EQU CYREG_PRT4_AG +SCSI_In__CD__AMUX EQU CYREG_PRT4_AMUX +SCSI_In__CD__BIE EQU CYREG_PRT4_BIE +SCSI_In__CD__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_In__CD__BYP EQU CYREG_PRT4_BYP +SCSI_In__CD__CTL EQU CYREG_PRT4_CTL +SCSI_In__CD__DM0 EQU CYREG_PRT4_DM0 +SCSI_In__CD__DM1 EQU CYREG_PRT4_DM1 +SCSI_In__CD__DM2 EQU CYREG_PRT4_DM2 +SCSI_In__CD__DR EQU CYREG_PRT4_DR +SCSI_In__CD__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_In__CD__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_In__CD__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_In__CD__MASK EQU 0x04 +SCSI_In__CD__PC EQU CYREG_PRT4_PC2 +SCSI_In__CD__PORT EQU 4 +SCSI_In__CD__PRT EQU CYREG_PRT4_PRT +SCSI_In__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_In__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_In__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_In__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_In__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_In__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_In__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_In__CD__PS EQU CYREG_PRT4_PS +SCSI_In__CD__SHIFT EQU 2 +SCSI_In__CD__SLW EQU CYREG_PRT4_SLW +SCSI_In__DBP__AG EQU CYREG_PRT2_AG +SCSI_In__DBP__AMUX EQU CYREG_PRT2_AMUX +SCSI_In__DBP__BIE EQU CYREG_PRT2_BIE +SCSI_In__DBP__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_In__DBP__BYP EQU CYREG_PRT2_BYP +SCSI_In__DBP__CTL EQU CYREG_PRT2_CTL +SCSI_In__DBP__DM0 EQU CYREG_PRT2_DM0 +SCSI_In__DBP__DM1 EQU CYREG_PRT2_DM1 +SCSI_In__DBP__DM2 EQU CYREG_PRT2_DM2 +SCSI_In__DBP__DR EQU CYREG_PRT2_DR +SCSI_In__DBP__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_In__DBP__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_In__DBP__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_In__DBP__MASK EQU 0x02 +SCSI_In__DBP__PC EQU CYREG_PRT2_PC1 +SCSI_In__DBP__PORT EQU 2 +SCSI_In__DBP__PRT EQU CYREG_PRT2_PRT +SCSI_In__DBP__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_In__DBP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_In__DBP__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_In__DBP__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_In__DBP__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_In__DBP__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_In__DBP__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_In__DBP__PS EQU CYREG_PRT2_PS +SCSI_In__DBP__SHIFT EQU 1 +SCSI_In__DBP__SLW EQU CYREG_PRT2_SLW +SCSI_In__IO__AG EQU CYREG_PRT0_AG +SCSI_In__IO__AMUX EQU CYREG_PRT0_AMUX +SCSI_In__IO__BIE EQU CYREG_PRT0_BIE +SCSI_In__IO__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_In__IO__BYP EQU CYREG_PRT0_BYP +SCSI_In__IO__CTL EQU CYREG_PRT0_CTL +SCSI_In__IO__DM0 EQU CYREG_PRT0_DM0 +SCSI_In__IO__DM1 EQU CYREG_PRT0_DM1 +SCSI_In__IO__DM2 EQU CYREG_PRT0_DM2 +SCSI_In__IO__DR EQU CYREG_PRT0_DR +SCSI_In__IO__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_In__IO__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_In__IO__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_In__IO__MASK EQU 0x10 +SCSI_In__IO__PC EQU CYREG_PRT0_PC4 +SCSI_In__IO__PORT EQU 0 +SCSI_In__IO__PRT EQU CYREG_PRT0_PRT +SCSI_In__IO__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_In__IO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_In__IO__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_In__IO__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_In__IO__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_In__IO__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_In__IO__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_In__IO__PS EQU CYREG_PRT0_PS +SCSI_In__IO__SHIFT EQU 4 +SCSI_In__IO__SLW EQU CYREG_PRT0_SLW +SCSI_In__MSG__AG EQU CYREG_PRT4_AG +SCSI_In__MSG__AMUX EQU CYREG_PRT4_AMUX +SCSI_In__MSG__BIE EQU CYREG_PRT4_BIE +SCSI_In__MSG__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_In__MSG__BYP EQU CYREG_PRT4_BYP +SCSI_In__MSG__CTL EQU CYREG_PRT4_CTL +SCSI_In__MSG__DM0 EQU CYREG_PRT4_DM0 +SCSI_In__MSG__DM1 EQU CYREG_PRT4_DM1 +SCSI_In__MSG__DM2 EQU CYREG_PRT4_DM2 +SCSI_In__MSG__DR EQU CYREG_PRT4_DR +SCSI_In__MSG__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_In__MSG__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_In__MSG__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_In__MSG__MASK EQU 0x40 +SCSI_In__MSG__PC EQU CYREG_PRT4_PC6 +SCSI_In__MSG__PORT EQU 4 +SCSI_In__MSG__PRT EQU CYREG_PRT4_PRT +SCSI_In__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_In__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_In__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_In__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_In__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_In__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_In__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_In__MSG__PS EQU CYREG_PRT4_PS +SCSI_In__MSG__SHIFT EQU 6 +SCSI_In__MSG__SLW EQU CYREG_PRT4_SLW +SCSI_In__REQ__AG EQU CYREG_PRT0_AG +SCSI_In__REQ__AMUX EQU CYREG_PRT0_AMUX +SCSI_In__REQ__BIE EQU CYREG_PRT0_BIE +SCSI_In__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_In__REQ__BYP EQU CYREG_PRT0_BYP +SCSI_In__REQ__CTL EQU CYREG_PRT0_CTL +SCSI_In__REQ__DM0 EQU CYREG_PRT0_DM0 +SCSI_In__REQ__DM1 EQU CYREG_PRT0_DM1 +SCSI_In__REQ__DM2 EQU CYREG_PRT0_DM2 +SCSI_In__REQ__DR EQU CYREG_PRT0_DR +SCSI_In__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_In__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_In__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_In__REQ__MASK EQU 0x20 +SCSI_In__REQ__PC EQU CYREG_PRT0_PC5 +SCSI_In__REQ__PORT EQU 0 +SCSI_In__REQ__PRT EQU CYREG_PRT0_PRT +SCSI_In__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_In__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_In__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_In__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_In__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_In__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_In__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_In__REQ__PS EQU CYREG_PRT0_PS +SCSI_In__REQ__SHIFT EQU 5 +SCSI_In__REQ__SLW EQU CYREG_PRT0_SLW +SCSI_In__SEL__AG EQU CYREG_PRT4_AG +SCSI_In__SEL__AMUX EQU CYREG_PRT4_AMUX +SCSI_In__SEL__BIE EQU CYREG_PRT4_BIE +SCSI_In__SEL__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_In__SEL__BYP EQU CYREG_PRT4_BYP +SCSI_In__SEL__CTL EQU CYREG_PRT4_CTL +SCSI_In__SEL__DM0 EQU CYREG_PRT4_DM0 +SCSI_In__SEL__DM1 EQU CYREG_PRT4_DM1 +SCSI_In__SEL__DM2 EQU CYREG_PRT4_DM2 +SCSI_In__SEL__DR EQU CYREG_PRT4_DR +SCSI_In__SEL__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_In__SEL__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_In__SEL__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_In__SEL__MASK EQU 0x08 +SCSI_In__SEL__PC EQU CYREG_PRT4_PC3 +SCSI_In__SEL__PORT EQU 4 +SCSI_In__SEL__PRT EQU CYREG_PRT4_PRT +SCSI_In__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_In__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_In__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_In__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_In__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_In__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_In__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_In__SEL__PS EQU CYREG_PRT4_PS +SCSI_In__SEL__SHIFT EQU 3 +SCSI_In__SEL__SLW EQU CYREG_PRT4_SLW + +; SD_MISO +SD_MISO__0__MASK EQU 0x02 +SD_MISO__0__PC EQU CYREG_PRT3_PC1 +SD_MISO__0__PORT EQU 3 +SD_MISO__0__SHIFT EQU 1 +SD_MISO__AG EQU CYREG_PRT3_AG +SD_MISO__AMUX EQU CYREG_PRT3_AMUX +SD_MISO__BIE EQU CYREG_PRT3_BIE +SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_MISO__BYP EQU CYREG_PRT3_BYP +SD_MISO__CTL EQU CYREG_PRT3_CTL +SD_MISO__DM0 EQU CYREG_PRT3_DM0 +SD_MISO__DM1 EQU CYREG_PRT3_DM1 +SD_MISO__DM2 EQU CYREG_PRT3_DM2 +SD_MISO__DR EQU CYREG_PRT3_DR +SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_MISO__MASK EQU 0x02 +SD_MISO__PORT EQU 3 +SD_MISO__PRT EQU CYREG_PRT3_PRT +SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_MISO__PS EQU CYREG_PRT3_PS +SD_MISO__SHIFT EQU 1 +SD_MISO__SLW EQU CYREG_PRT3_SLW + +; SD_MOSI +SD_MOSI__0__MASK EQU 0x08 +SD_MOSI__0__PC EQU CYREG_PRT3_PC3 +SD_MOSI__0__PORT EQU 3 +SD_MOSI__0__SHIFT EQU 3 +SD_MOSI__AG EQU CYREG_PRT3_AG +SD_MOSI__AMUX EQU CYREG_PRT3_AMUX +SD_MOSI__BIE EQU CYREG_PRT3_BIE +SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_MOSI__BYP EQU CYREG_PRT3_BYP +SD_MOSI__CTL EQU CYREG_PRT3_CTL +SD_MOSI__DM0 EQU CYREG_PRT3_DM0 +SD_MOSI__DM1 EQU CYREG_PRT3_DM1 +SD_MOSI__DM2 EQU CYREG_PRT3_DM2 +SD_MOSI__DR EQU CYREG_PRT3_DR +SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_MOSI__MASK EQU 0x08 +SD_MOSI__PORT EQU 3 +SD_MOSI__PRT EQU CYREG_PRT3_PRT +SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_MOSI__PS EQU CYREG_PRT3_PS +SD_MOSI__SHIFT EQU 3 +SD_MOSI__SLW EQU CYREG_PRT3_SLW + +; SD_SCK +SD_SCK__0__MASK EQU 0x04 +SD_SCK__0__PC EQU CYREG_PRT3_PC2 +SD_SCK__0__PORT EQU 3 +SD_SCK__0__SHIFT EQU 2 +SD_SCK__AG EQU CYREG_PRT3_AG +SD_SCK__AMUX EQU CYREG_PRT3_AMUX +SD_SCK__BIE EQU CYREG_PRT3_BIE +SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_SCK__BYP EQU CYREG_PRT3_BYP +SD_SCK__CTL EQU CYREG_PRT3_CTL +SD_SCK__DM0 EQU CYREG_PRT3_DM0 +SD_SCK__DM1 EQU CYREG_PRT3_DM1 +SD_SCK__DM2 EQU CYREG_PRT3_DM2 +SD_SCK__DR EQU CYREG_PRT3_DR +SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_SCK__MASK EQU 0x04 +SD_SCK__PORT EQU 3 +SD_SCK__PRT EQU CYREG_PRT3_PRT +SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_SCK__PS EQU CYREG_PRT3_PS +SD_SCK__SHIFT EQU 2 +SD_SCK__SLW EQU CYREG_PRT3_SLW + +; SD_CD +SD_CD__0__MASK EQU 0x20 +SD_CD__0__PC EQU CYREG_PRT3_PC5 +SD_CD__0__PORT EQU 3 +SD_CD__0__SHIFT EQU 5 +SD_CD__AG EQU CYREG_PRT3_AG +SD_CD__AMUX EQU CYREG_PRT3_AMUX +SD_CD__BIE EQU CYREG_PRT3_BIE +SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_CD__BYP EQU CYREG_PRT3_BYP +SD_CD__CTL EQU CYREG_PRT3_CTL +SD_CD__DM0 EQU CYREG_PRT3_DM0 +SD_CD__DM1 EQU CYREG_PRT3_DM1 +SD_CD__DM2 EQU CYREG_PRT3_DM2 +SD_CD__DR EQU CYREG_PRT3_DR +SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_CD__MASK EQU 0x20 +SD_CD__PORT EQU 3 +SD_CD__PRT EQU CYREG_PRT3_PRT +SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_CD__PS EQU CYREG_PRT3_PS +SD_CD__SHIFT EQU 5 +SD_CD__SLW EQU CYREG_PRT3_SLW + +; SD_CS +SD_CS__0__MASK EQU 0x10 +SD_CS__0__PC EQU CYREG_PRT3_PC4 +SD_CS__0__PORT EQU 3 +SD_CS__0__SHIFT EQU 4 +SD_CS__AG EQU CYREG_PRT3_AG +SD_CS__AMUX EQU CYREG_PRT3_AMUX +SD_CS__BIE EQU CYREG_PRT3_BIE +SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_CS__BYP EQU CYREG_PRT3_BYP +SD_CS__CTL EQU CYREG_PRT3_CTL +SD_CS__DM0 EQU CYREG_PRT3_DM0 +SD_CS__DM1 EQU CYREG_PRT3_DM1 +SD_CS__DM2 EQU CYREG_PRT3_DM2 +SD_CS__DR EQU CYREG_PRT3_DR +SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_CS__MASK EQU 0x10 +SD_CS__PORT EQU 3 +SD_CS__PRT EQU CYREG_PRT3_PRT +SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_CS__PS EQU CYREG_PRT3_PS +SD_CS__SHIFT EQU 4 +SD_CS__SLW EQU CYREG_PRT3_SLW + +; LED1 +LED1__0__MASK EQU 0x02 +LED1__0__PC EQU CYREG_PRT0_PC1 +LED1__0__PORT EQU 0 +LED1__0__SHIFT EQU 1 +LED1__AG EQU CYREG_PRT0_AG +LED1__AMUX EQU CYREG_PRT0_AMUX +LED1__BIE EQU CYREG_PRT0_BIE +LED1__BIT_MASK EQU CYREG_PRT0_BIT_MASK +LED1__BYP EQU CYREG_PRT0_BYP +LED1__CTL EQU CYREG_PRT0_CTL +LED1__DM0 EQU CYREG_PRT0_DM0 +LED1__DM1 EQU CYREG_PRT0_DM1 +LED1__DM2 EQU CYREG_PRT0_DM2 +LED1__DR EQU CYREG_PRT0_DR +LED1__INP_DIS EQU CYREG_PRT0_INP_DIS +LED1__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +LED1__LCD_EN EQU CYREG_PRT0_LCD_EN +LED1__MASK EQU 0x02 +LED1__PORT EQU 0 +LED1__PRT EQU CYREG_PRT0_PRT +LED1__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +LED1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +LED1__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +LED1__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +LED1__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +LED1__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +LED1__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +LED1__PS EQU CYREG_PRT0_PS +LED1__SHIFT EQU 1 +LED1__SLW EQU CYREG_PRT0_SLW + +; Miscellaneous +; -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release +CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6 +CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0 +CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0 +CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1 +CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0 +CYDEV_CHIP_MEMBER_5B EQU 4 +CYDEV_CHIP_FAMILY_PSOC5 EQU 3 +CYDEV_CHIP_DIE_PSOC5LP EQU 4 +CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP +BCLK__BUS_CLK__HZ EQU 60000000 +BCLK__BUS_CLK__KHZ EQU 60000 +BCLK__BUS_CLK__MHZ EQU 60 +CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT +CYDEV_CHIP_DIE_LEOPARD EQU 1 +CYDEV_CHIP_DIE_PANTHER EQU 3 +CYDEV_CHIP_DIE_PSOC4A EQU 2 +CYDEV_CHIP_DIE_UNKNOWN EQU 0 +CYDEV_CHIP_FAMILY_PSOC3 EQU 1 +CYDEV_CHIP_FAMILY_PSOC4 EQU 2 +CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 +CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5 +CYDEV_CHIP_JTAG_ID EQU 0x2E133069 +CYDEV_CHIP_MEMBER_3A EQU 1 +CYDEV_CHIP_MEMBER_4A EQU 2 +CYDEV_CHIP_MEMBER_5A EQU 3 +CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 +CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B +CYDEV_CHIP_REVISION_3A_ES1 EQU 0 +CYDEV_CHIP_REVISION_3A_ES2 EQU 1 +CYDEV_CHIP_REVISION_3A_ES3 EQU 3 +CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3 +CYDEV_CHIP_REVISION_4A_ES0 EQU 17 +CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_5A_ES0 EQU 0 +CYDEV_CHIP_REVISION_5A_ES1 EQU 1 +CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 +CYDEV_CHIP_REVISION_5B_ES0 EQU 0 +CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION +CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REV_PSOC5LP_PRODUCTION +CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0 +CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1 +CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3 +CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3 +CYDEV_CHIP_REV_PANTHER_ES0 EQU 0 +CYDEV_CHIP_REV_PANTHER_ES1 EQU 1 +CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1 +CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17 +CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17 +CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0 +CYDEV_CONFIGURATION_COMPRESSED EQU 1 +CYDEV_CONFIGURATION_DMA EQU 0 +CYDEV_CONFIGURATION_ECC EQU 0 +CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED +CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED +CYDEV_CONFIGURATION_MODE_DMA EQU 2 +CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1 +CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn +CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1 +CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2 +CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV +CYDEV_DEBUGGING_DPS_Disable EQU 3 +CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1 +CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0 +CYDEV_DEBUGGING_DPS_SWD EQU 2 +CYDEV_DEBUGGING_ENABLE EQU 1 +CYDEV_DEBUGGING_XRES EQU 0 +CYDEV_DEBUG_ENABLE_MASK EQU 0x20 +CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG +CYDEV_DMA_CHANNELS_AVAILABLE EQU 24 +CYDEV_ECC_ENABLE EQU 0 +CYDEV_HEAP_SIZE EQU 0x1000 +CYDEV_INSTRUCT_CACHE_ENABLED EQU 1 +CYDEV_INTR_RISING EQU 0x00000000 +CYDEV_PROJ_TYPE EQU 2 +CYDEV_PROJ_TYPE_BOOTLOADER EQU 1 +CYDEV_PROJ_TYPE_LOADABLE EQU 2 +CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3 +CYDEV_PROJ_TYPE_STANDARD EQU 0 +CYDEV_PROTECTION_ENABLE EQU 0 +CYDEV_STACK_SIZE EQU 0x4000 +CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP EQU 1 +CYDEV_USE_BUNDLED_CMSIS EQU 1 +CYDEV_VARIABLE_VDDA EQU 0 +CYDEV_VDDA_MV EQU 5000 +CYDEV_VDDD_MV EQU 5000 +CYDEV_VDDIO0_MV EQU 5000 +CYDEV_VDDIO1_MV EQU 5000 +CYDEV_VDDIO2_MV EQU 5000 +CYDEV_VDDIO3_MV EQU 3300 +CYDEV_VIO0 EQU 5 +CYDEV_VIO0_MV EQU 5000 +CYDEV_VIO1 EQU 5 +CYDEV_VIO1_MV EQU 5000 +CYDEV_VIO2 EQU 5 +CYDEV_VIO2_MV EQU 5000 +CYDEV_VIO3_MV EQU 3300 +DMA_CHANNELS_USED__MASK0 EQU 0x00000000 +CYDEV_BOOTLOADER_ENABLE EQU 0 + ENDIF + END diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cymetadata.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cymetadata.c new file mode 100755 index 00000000..1875d37c --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cymetadata.c @@ -0,0 +1,48 @@ +/******************************************************************************* +* FILENAME: cymetadata.c +* +* PSoC Creator 3.0 Component Pack 7 +* +* DESCRIPTION: +* This file defines all extra memory spaces that need to be included. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + + +#include "cytypes.h" + + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +__attribute__ ((__section__(".cyloadablemeta"), used)) +#elif defined(__ICCARM__) +#pragma location=".cyloadablemeta" +#else +#error "Unsupported toolchain" +#endif +const uint8 cy_meta_loadable[] = { + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x01u, 0x00u, + 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u +}; + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +__attribute__ ((__section__(".cyconfigecc"), used)) +#elif defined(__ICCARM__) +#pragma location=".cyconfigecc" +#else +#error "Unsupported toolchain" +#endif +const uint8 cy_meta_configecc[] = { + 0x00u +}; diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cypins.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cypins.h new file mode 100755 index 00000000..6caced2f --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cypins.h @@ -0,0 +1,295 @@ +/******************************************************************************* +* File Name: cypins.h +* Version 4.0 +* +* Description: +* This file contains the function prototypes and constants used for port/pin +* in access and control. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYPINS_H) +#define CY_BOOT_CYPINS_H + +#include "cyfitter.h" +#include "cytypes.h" + + +/************************************** +* API Parameter Constants +**************************************/ + +#define CY_PINS_PC_DRIVE_MODE_SHIFT (0x01u) +#define CY_PINS_PC_DRIVE_MODE_MASK ((uint8)(0x07u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_0 ((uint8)(0x00u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_1 ((uint8)(0x01u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_2 ((uint8)(0x02u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_3 ((uint8)(0x03u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_4 ((uint8)(0x04u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_5 ((uint8)(0x05u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_6 ((uint8)(0x06u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_7 ((uint8)(0x07u << CY_PINS_PC_DRIVE_MODE_SHIFT)) + + +/* SetPinDriveMode */ +#define CY_PINS_DM_ALG_HIZ (CY_PINS_PC_DRIVE_MODE_0) +#define CY_PINS_DM_DIG_HIZ (CY_PINS_PC_DRIVE_MODE_1) +#define CY_PINS_DM_RES_UP (CY_PINS_PC_DRIVE_MODE_2) +#define CY_PINS_DM_RES_DWN (CY_PINS_PC_DRIVE_MODE_3) +#define CY_PINS_DM_OD_LO (CY_PINS_PC_DRIVE_MODE_4) +#define CY_PINS_DM_OD_HI (CY_PINS_PC_DRIVE_MODE_5) +#define CY_PINS_DM_STRONG (CY_PINS_PC_DRIVE_MODE_6) +#define CY_PINS_DM_RES_UPDWN (CY_PINS_PC_DRIVE_MODE_7) + + +/************************************** +* Register Constants +**************************************/ + +/* Port Pin Configuration Register */ +#define CY_PINS_PC_DATAOUT (0x01u) +#define CY_PINS_PC_PIN_FASTSLEW (0xBFu) +#define CY_PINS_PC_PIN_SLOWSLEW (0x40u) +#define CY_PINS_PC_PIN_STATE (0x10u) +#define CY_PINS_PC_BIDIR_EN (0x20u) +#define CY_PINS_PC_SLEW (0x40u) +#define CY_PINS_PC_BYPASS (0x80u) + + +/************************************** +* Pin API Macros +**************************************/ + +/******************************************************************************* +* Macro Name: CyPins_ReadPin +******************************************************************************** +* +* Summary: +* Reads the current value on the pin (pin state, PS). +* +* Parameters: +* pinPC: Port pin configuration register (uint16). +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* Return: +* Pin state +* 0: Logic low value +* Non-0: Logic high value +* +*******************************************************************************/ +#define CyPins_ReadPin(pinPC) ( *(reg8 *)(pinPC) & CY_PINS_PC_PIN_STATE ) + + +/******************************************************************************* +* Macro Name: CyPins_SetPin +******************************************************************************** +* +* Summary: +* Set the output value for the pin (data register, DR) to a logic high. +* +* Note that this only has an effect for pins configured as software pins that +* are not driven by hardware. +* +* Parameters: +* pinPC: Port pin configuration register (uint16). +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* Return: +* None +* +*******************************************************************************/ +#define CyPins_SetPin(pinPC) ( *(reg8 *)(pinPC) |= CY_PINS_PC_DATAOUT) + + +/******************************************************************************* +* Macro Name: CyPins_ClearPin +******************************************************************************** +* +* Summary: +* This macro sets the state of the specified pin to 0 +* +* Parameters: +* pinPC: address of a Pin Configuration register. +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* Return: +* None +* +*******************************************************************************/ +#define CyPins_ClearPin(pinPC) ( *(reg8 *)(pinPC) &= ((uint8)(~CY_PINS_PC_DATAOUT))) + + +/******************************************************************************* +* Macro Name: CyPins_SetPinDriveMode +******************************************************************************** +* +* Summary: +* Sets the drive mode for the pin (DM). +* +* Parameters: +* pinPC: Port pin configuration register (uint16) +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* mode: Desired drive mode +* +* Define Source +* PIN_DM_ALG_HIZ Analog HiZ +* PIN_DM_DIG_HIZ Digital HiZ +* PIN_DM_RES_UP Resistive pull up +* PIN_DM_RES_DWN Resistive pull down +* PIN_DM_OD_LO Open drain - drive low +* PIN_DM_OD_HI Open drain - drive high +* PIN_DM_STRONG Strong CMOS Output +* PIN_DM_RES_UPDWN Resistive pull up/down +* +* Return: +* None +* +*******************************************************************************/ +#define CyPins_SetPinDriveMode(pinPC, mode) \ + ( *(reg8 *)(pinPC) = (*(reg8 *)(pinPC) & ((uint8)(~CY_PINS_PC_DRIVE_MODE_MASK))) | \ + ((mode) & CY_PINS_PC_DRIVE_MODE_MASK)) + + +/******************************************************************************* +* Macro Name: CyPins_ReadPinDriveMode +******************************************************************************** +* +* Summary: +* Reads the drive mode for the pin (DM). +* +* Parameters: +* pinPC: Port pin configuration register (uint16) +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* +* Return: +* mode: Current drive mode for the pin +* +* Define Source +* PIN_DM_ALG_HIZ Analog HiZ +* PIN_DM_DIG_HIZ Digital HiZ +* PIN_DM_RES_UP Resistive pull up +* PIN_DM_RES_DWN Resistive pull down +* PIN_DM_OD_LO Open drain - drive low +* PIN_DM_OD_HI Open drain - drive high +* PIN_DM_STRONG Strong CMOS Output +* PIN_DM_RES_UPDWN Resistive pull up/down +* +*******************************************************************************/ +#define CyPins_ReadPinDriveMode(pinPC) (*(reg8 *)(pinPC) & CY_PINS_PC_DRIVE_MODE_MASK) + + +/******************************************************************************* +* Macro Name: CyPins_FastSlew +******************************************************************************** +* +* Summary: +* Set the slew rate for the pin to fast edge rate. +* Note that this only applies for pins in strong output drive modes, +* not to resistive drive modes. +* +* Parameters: +* pinPC: address of a Pin Configuration register. +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* +* Return: +* None +* +*******************************************************************************/ +#define CyPins_FastSlew(pinPC) (*(reg8 *)(pinPC) = (*(reg8 *)(pinPC) & CY_PINS_PC_PIN_FASTSLEW)) + + +/******************************************************************************* +* Macro Name: CyPins_SlowSlew +******************************************************************************** +* +* Summary: +* Set the slew rate for the pin to slow edge rate. +* Note that this only applies for pins in strong output drive modes, +* not to resistive drive modes. +* +* Parameters: +* pinPC: address of a Pin Configuration register. +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* Return: +* None +* +*******************************************************************************/ +#define CyPins_SlowSlew(pinPC) (*(reg8 *)(pinPC) = (*(reg8 *)(pinPC) | CY_PINS_PC_PIN_SLOWSLEW)) + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from cy_boot 3.30 +*******************************************************************************/ +#define PC_DRIVE_MODE_SHIFT (CY_PINS_PC_DRIVE_MODE_SHIFT) +#define PC_DRIVE_MODE_MASK (CY_PINS_PC_DRIVE_MODE_MASK) +#define PC_DRIVE_MODE_0 (CY_PINS_PC_DRIVE_MODE_0) +#define PC_DRIVE_MODE_1 (CY_PINS_PC_DRIVE_MODE_1) +#define PC_DRIVE_MODE_2 (CY_PINS_PC_DRIVE_MODE_2) +#define PC_DRIVE_MODE_3 (CY_PINS_PC_DRIVE_MODE_3) +#define PC_DRIVE_MODE_4 (CY_PINS_PC_DRIVE_MODE_4) +#define PC_DRIVE_MODE_5 (CY_PINS_PC_DRIVE_MODE_5) +#define PC_DRIVE_MODE_6 (CY_PINS_PC_DRIVE_MODE_6) +#define PC_DRIVE_MODE_7 (CY_PINS_PC_DRIVE_MODE_7) + +#define PIN_DM_ALG_HIZ (CY_PINS_DM_ALG_HIZ) +#define PIN_DM_DIG_HIZ (CY_PINS_DM_DIG_HIZ) +#define PIN_DM_RES_UP (CY_PINS_DM_RES_UP) +#define PIN_DM_RES_DWN (CY_PINS_DM_RES_DWN) +#define PIN_DM_OD_LO (CY_PINS_DM_OD_LO) +#define PIN_DM_OD_HI (CY_PINS_DM_OD_HI) +#define PIN_DM_STRONG (CY_PINS_DM_STRONG) +#define PIN_DM_RES_UPDWN (CY_PINS_DM_RES_UPDWN) + +#define PC_DATAOUT (CY_PINS_PC_DATAOUT) +#define PC_PIN_FASTSLEW (CY_PINS_PC_PIN_FASTSLEW) +#define PC_PIN_SLOWSLEW (CY_PINS_PC_PIN_SLOWSLEW) +#define PC_PIN_STATE (CY_PINS_PC_PIN_STATE) +#define PC_BIDIR_EN (CY_PINS_PC_BIDIR_EN) +#define PC_SLEW (CY_PINS_PC_SLEW) +#define PC_BYPASS (CY_PINS_PC_BYPASS) + +#endif /* (CY_BOOT_CYPINS_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cytypes.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cytypes.h new file mode 100755 index 00000000..24db0621 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cytypes.h @@ -0,0 +1,438 @@ +/******************************************************************************* +* FILENAME: cytypes.h +* Version 4.0 +* +* Description: +* CyTypes provides register access macros and approved types for use in +* firmware. +* +* Note: +* Due to endiannesses of the hardware and some compilers, the register +* access macros for big endian compilers use some library calls to arrange +* data the correct way. +* +* Register Access macros and functions perform their operations on an +* input of type pointer to void. The arguments passed to it should be +* pointers to the type associated with the register size. +* (i.e. a "uint8 *" shouldn't be passed to obtain a 16-bit register value) +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYTYPES_H) +#define CY_BOOT_CYTYPES_H + +#if defined(__C51__) + #include +#endif /* (__C51__) */ + +/* ARM and C99 or later */ +#if defined(__GNUC__) || defined(__ARMCC_VERSION) || (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) + #include +#endif /* (__GNUC__) || defined(__ARMCC_VERSION) || (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) */ + +#include "cyfitter.h" + + +#if defined( __ICCARM__ ) + /* Suppress warning for multiple volatile variables in an expression. */ + /* This is common in component code and the usage is not order dependent. */ + #pragma diag_suppress=Pa082 +#endif /* defined( __ICCARM__ ) */ + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ + + +/******************************************************************************* +* FAMILY encodes the overall architectural family +*******************************************************************************/ +#define CY_PSOC3 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) +#define CY_PSOC4 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) +#define CY_PSOC5 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5) + + +/******************************************************************************* +* MEMBER encodes both the family and the detailed architecture +*******************************************************************************/ +#define CY_PSOC4A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A) +#ifdef CYDEV_CHIP_MEMBER_4D + #define CY_PSOC4D (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D) + #define CY_PSOC4SF (CY_PSOC4D) +#else + #define CY_PSOC4D (0u != 0u) + #define CY_PSOC4SF (CY_PSOC4D) +#endif /* CYDEV_CHIP_MEMBER_4D */ + +#define CY_PSOC5A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A) +#ifdef CYDEV_CHIP_MEMBER_5B + #define CY_PSOC5LP (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5B) +#else + #define CY_PSOC5LP (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_5B */ + + +/******************************************************************************* +* UDB revisions +*******************************************************************************/ +#define CY_UDB_V0 (CY_PSOC5A) +#define CY_UDB_V1 (!CY_UDB_V0) + + +/******************************************************************************* +* Base Types. Acceptable types from MISRA-C specifying signedness and size. +*******************************************************************************/ +typedef unsigned char uint8; +typedef unsigned short uint16; +typedef unsigned long uint32; +typedef signed char int8; +typedef signed short int16; +typedef signed long int32; +typedef float float32; + +#if(!CY_PSOC3) + + typedef double float64; + typedef long long int64; + typedef unsigned long long uint64; + +#endif /* (!CY_PSOC3) */ + +/* Signed or unsigned depending on the compiler selection */ +typedef char char8; + + +/******************************************************************************* +* Memory address functions prototypes +*******************************************************************************/ +#if(CY_PSOC3) + + /*************************************************************************** + * Prototypes for absolute memory address functions (cymem.a51) with built-in + * endian conversion. These functions should be called through the + * CY_GET_XTND_REGxx and CY_SET_XTND_REGxx macros. + ***************************************************************************/ + extern uint8 cyread8 (const volatile void far *addr); + extern void cywrite8 (volatile void far *addr, uint8 value); + + extern uint16 cyread16 (const volatile void far *addr); + extern uint16 cyread16_nodpx(const volatile void far *addr); + + extern void cywrite16 (volatile void far *addr, uint16 value); + extern void cywrite16_nodpx(volatile void far *addr, uint16 value); + + extern uint32 cyread24 (const volatile void far *addr); + extern uint32 cyread24_nodpx(const volatile void far *addr); + + extern void cywrite24 (volatile void far *addr, uint32 value); + extern void cywrite24_nodpx(volatile void far *addr, uint32 value); + + extern uint32 cyread32 (const volatile void far *addr); + extern uint32 cyread32_nodpx(const volatile void far *addr); + + extern void cywrite32 (volatile void far *addr, uint32 value); + extern void cywrite32_nodpx(volatile void far *addr, uint32 value); + + + /*************************************************************************** + * Memory access routines from cymem.a51 for the generated device + * configuration code. These functions may be subject to change in future + * revisions of the cy_boot component and they are not available for all + * devices. Most code should use memset or memcpy instead. + ***************************************************************************/ + void cymemzero(void far *addr, uint16 size); + void cyconfigcpy(uint16 size, const void far *src, void far *dest) large; + void cyconfigcpycode(uint16 size, const void code *src, void far *dest); + + #define CYCONFIGCPY_DECLARED (1) + +#else + + /* Prototype for function to set a 24-bit register. Located at cyutils.c */ + extern void CySetReg24(uint32 volatile * addr, uint32 value); + + #if(CY_PSOC4) + + extern uint32 CyGetReg24(uint32 const volatile * addr); + + #endif /* (CY_PSOC4) */ + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Memory model definitions. To allow code to be 8051-ARM agnostic. +*******************************************************************************/ +#if(CY_PSOC3) + + #define CYBDATA bdata + #define CYBIT bit + #define CYCODE code + #define CYCOMPACT compact + #define CYDATA data + #define CYFAR far + #define CYIDATA idata + #define CYLARGE large + #define CYPDATA pdata + #define CYREENTRANT reentrant + #define CYSMALL small + #define CYXDATA xdata + #define XDATA xdata + + #define CY_NOINIT + +#else + + #define CYBDATA + #define CYBIT uint8 + #define CYCODE + #define CYCOMPACT + #define CYDATA + #define CYFAR + #define CYIDATA + #define CYLARGE + #define CYPDATA + #define CYREENTRANT + #define CYSMALL + #define CYXDATA + #define XDATA + + #if defined(__ARMCC_VERSION) + #define CY_NOINIT __attribute__ ((section(".noinit"), zero_init)) + #define CY_NORETURN __attribute__ ((noreturn)) + #define CY_SECTION(name) __attribute__ ((section(name))) + #define CY_ALIGN(align) __align(align) + #elif defined (__GNUC__) + #define CY_NOINIT __attribute__ ((section(".noinit"))) + #define CY_NORETURN __attribute__ ((noreturn)) + #define CY_SECTION(name) __attribute__ ((section(name))) + #define CY_ALIGN(align) __attribute__ ((aligned(align))) + #elif defined (__ICCARM__) + #define CY_NOINIT __no_init + #define CY_NORETURN __noreturn + #endif /* (__ARMCC_VERSION) */ + +#endif /* (CY_PSOC3) */ + + +#if(CY_PSOC3) + + /* 8051 naturally returns an 8 bit value. */ + typedef unsigned char cystatus; + +#else + + /* ARM naturally returns a 32 bit value. */ + typedef unsigned long cystatus; + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Hardware Register Types. +*******************************************************************************/ +typedef volatile uint8 CYXDATA reg8; +typedef volatile uint16 CYXDATA reg16; +typedef volatile uint32 CYXDATA reg32; + + +/******************************************************************************* +* Interrupt Types and Macros +*******************************************************************************/ +#if(CY_PSOC3) + + #define CY_ISR(FuncName) void FuncName (void) interrupt 0 + #define CY_ISR_PROTO(FuncName) void FuncName (void) + typedef void (CYCODE * cyisraddress)(void); + +#else + + #define CY_ISR(FuncName) void FuncName (void) + #define CY_ISR_PROTO(FuncName) void FuncName (void) + typedef void (* cyisraddress)(void); + + #if defined (__ICCARM__) + typedef union { cyisraddress __fun; void * __ptr; } intvec_elem; + #endif /* defined (__ICCARM__) */ + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Register Access +*******************************************************************************/ +#if(CY_PSOC3) + + + /******************************************************************************* + * KEIL for the 8051 is a big endian compiler This causes problems as the on chip + * registers are little endian. Byte swapping for two and four byte registers is + * implemented in the functions below. This will require conditional compilation + * of function prototypes in code. + *******************************************************************************/ + + /* Access macros for 8, 16, 24 and 32-bit registers, IN THE FIRST 64K OF XDATA */ + + #define CY_GET_REG8(addr) (*((const reg8 *)(addr))) + #define CY_SET_REG8(addr, value) (*((reg8 *)(addr)) = (uint8)(value)) + + #define CY_GET_REG16(addr) cyread16_nodpx ((const volatile void far *)(const reg16 *)(addr)) + #define CY_SET_REG16(addr, value) cywrite16_nodpx((volatile void far *)(reg16 *)(addr), value) + + #define CY_GET_REG24(addr) cyread24_nodpx ((const volatile void far *)(const reg32 *)(addr)) + #define CY_SET_REG24(addr, value) cywrite24_nodpx((volatile void far *)(reg32 *)(addr),value) + + #define CY_GET_REG32(addr) cyread32_nodpx ((const volatile void far *)(const reg32 *)(addr)) + #define CY_SET_REG32(addr, value) cywrite32_nodpx((volatile void far *)(reg32 *)(addr), value) + + /* Access 8, 16, 24 and 32-bit registers, ABOVE THE FIRST 64K OF XDATA */ + #define CY_GET_XTND_REG8(addr) cyread8((const volatile void far *)(addr)) + #define CY_SET_XTND_REG8(addr, value) cywrite8((volatile void far *)(addr), value) + + #define CY_GET_XTND_REG16(addr) cyread16((const volatile void far *)(addr)) + #define CY_SET_XTND_REG16(addr, value) cywrite16((volatile void far *)(addr), value) + + #define CY_GET_XTND_REG24(addr) cyread24((const volatile void far *)(addr)) + #define CY_SET_XTND_REG24(addr, value) cywrite24((volatile void far *)(addr), value) + + #define CY_GET_XTND_REG32(addr) cyread32((const volatile void far *)(addr)) + #define CY_SET_XTND_REG32(addr, value) cywrite32((volatile void far *)(addr), value) + +#else + + /* 8, 16, 24 and 32-bit register access macros */ + #define CY_GET_REG8(addr) (*((const reg8 *)(addr))) + #define CY_SET_REG8(addr, value) (*((reg8 *)(addr)) = (uint8)(value)) + + #define CY_GET_REG16(addr) (*((const reg16 *)(addr))) + #define CY_SET_REG16(addr, value) (*((reg16 *)(addr)) = (uint16)(value)) + + + #define CY_SET_REG24(addr, value) CySetReg24((reg32 *) (addr), (value)) + #if(CY_PSOC4) + #define CY_GET_REG24(addr) CyGetReg24((const reg32 *) (addr)) + #else + #define CY_GET_REG24(addr) (*((const reg32 *)(addr)) & 0x00FFFFFFu) + #endif /* (CY_PSOC4) */ + + + #define CY_GET_REG32(addr) (*((const reg32 *)(addr))) + #define CY_SET_REG32(addr, value) (*((reg32 *)(addr)) = (uint32)(value)) + + + /* To allow code to be 8051-ARM agnostic. */ + #define CY_GET_XTND_REG8(addr) CY_GET_REG8(addr) + #define CY_SET_XTND_REG8(addr, value) CY_SET_REG8(addr, value) + + #define CY_GET_XTND_REG16(addr) CY_GET_REG16(addr) + #define CY_SET_XTND_REG16(addr, value) CY_SET_REG16(addr, value) + + #define CY_GET_XTND_REG24(addr) CY_GET_REG24(addr) + #define CY_SET_XTND_REG24(addr, value) CY_SET_REG24(addr, value) + + #define CY_GET_XTND_REG32(addr) CY_GET_REG32(addr) + #define CY_SET_XTND_REG32(addr, value) CY_SET_REG32(addr, value) + +#endif /* (CY_PSOC3) */ + + + +/******************************************************************************* +* Data manipulation defines +*******************************************************************************/ + +/* Get 8 bits of a 16 bit value. */ +#define LO8(x) ((uint8) ((x) & 0xFFu)) +#define HI8(x) ((uint8) ((uint16)(x) >> 8)) + +/* Get 16 bits of a 32 bit value. */ +#define LO16(x) ((uint16) ((x) & 0xFFFFu)) +#define HI16(x) ((uint16) ((uint32)(x) >> 16)) + +/* Swap the byte ordering of a 32 bit value */ +#define CYSWAP_ENDIAN32(x) \ + ((uint32)(((x) >> 24) | (((x) & 0x00FF0000u) >> 8) | (((x) & 0x0000FF00u) << 8) | ((x) << 24))) + +/* Swap the byte ordering of a 16 bit value */ +#define CYSWAP_ENDIAN16(x) ((uint16)(((x) << 8) | ((x) >> 8))) + + +/******************************************************************************* +* Defines the standard return values used PSoC content. A function is +* not limited to these return values but can use them when returning standard +* error values. Return values can be overloaded if documented in the function +* header. On the 8051 a function can use a larger return type but still use the +* defined return codes. +* +* Zero is successful, all other values indicate some form of failure. 1 - 0x7F - +* standard defined values; 0x80 - ... - user or content defined values. +*******************************************************************************/ +#define CYRET_SUCCESS (0x00u) /* Successful */ +#define CYRET_BAD_PARAM (0x01u) /* One or more invalid parameters */ +#define CYRET_INVALID_OBJECT (0x02u) /* Invalid object specified */ +#define CYRET_MEMORY (0x03u) /* Memory related failure */ +#define CYRET_LOCKED (0x04u) /* Resource lock failure */ +#define CYRET_EMPTY (0x05u) /* No more objects available */ +#define CYRET_BAD_DATA (0x06u) /* Bad data received (CRC or other error check) */ +#define CYRET_STARTED (0x07u) /* Operation started, but not necessarily completed yet */ +#define CYRET_FINISHED (0x08u) /* Operation completed */ +#define CYRET_CANCELED (0x09u) /* Operation canceled */ +#define CYRET_TIMEOUT (0x10u) /* Operation timed out */ +#define CYRET_INVALID_STATE (0x11u) /* Operation not setup or is in an improper state */ +#define CYRET_UNKNOWN ((cystatus) 0xFFFFFFFFu) /* Unknown failure */ + + +/******************************************************************************* +* Intrinsic Defines: Processor NOP instruction +*******************************************************************************/ +#if(CY_PSOC3) + + #define CY_NOP _nop_() + +#else + + #if defined(__ARMCC_VERSION) + + /* RealView */ + #define CY_NOP __nop() + + #else + + /* GCC */ + #define CY_NOP __asm("NOP\n") + + #endif /* defined(__ARMCC_VERSION) */ + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Following code are OBSOLETE and must not be used starting from cy_boot 3.10 +*******************************************************************************/ + +/* Device is PSoC 3 and the revision is ES2 or earlier */ +#define CY_PSOC3_ES2 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \ + (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_3A_ES2)) + +/* Device is PSoC 3 and the revision is ES3 or later */ +#define CY_PSOC3_ES3 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \ + (CYDEV_CHIP_REVISION_USED >= CYDEV_CHIP_REVISION_3A_ES3)) + +/* Device is PSoC 5 and the revision is ES1 or earlier */ +#define CY_PSOC5_ES1 (CY_PSOC5A && \ + (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_5A_ES1)) + +/* Device is PSoC 5 and the revision is ES2 or later */ +#define CY_PSOC5_ES2 (CY_PSOC5A && \ + (CYDEV_CHIP_REVISION_USED > CYDEV_CHIP_REVISION_5A_ES1)) + +#endif /* CY_BOOT_CYTYPES_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyutils.c b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyutils.c new file mode 100755 index 00000000..6d42579a --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/cyutils.c @@ -0,0 +1,87 @@ +/******************************************************************************* +* FILENAME: cyutils.c +* Version 4.0 +* +* Description: +* CyUtils provides function to handle 24-bit value writes. +* +******************************************************************************** +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" + +#if (!CY_PSOC3) + + /*************************************************************************** + * Function Name: CySetReg24 + **************************************************************************** + * + * Summary: + * Writes the 24-bit value to the specified register. + * + * Parameters: + * addr : adress where data must be written + * value: data that must be written + * + * Return: + * None + * + * Reentrant: + * No + * + ***************************************************************************/ + void CySetReg24(uint32 volatile * addr, uint32 value) + { + uint8 volatile *tmpAddr; + + tmpAddr = (uint8 volatile *) addr; + + tmpAddr[0u] = (uint8) value; + tmpAddr[1u] = (uint8) (value >> 8u); + tmpAddr[2u] = (uint8) (value >> 16u); + } + + + #if(CY_PSOC4) + + /*************************************************************************** + * Function Name: CyGetReg24 + **************************************************************************** + * + * Summary: + * Reads the 24-bit value from the specified register. + * + * Parameters: + * addr : adress where data must be read + * + * Return: + * None + * + * Reentrant: + * No + * + ***************************************************************************/ + uint32 CyGetReg24(uint32 const volatile * addr) + { + uint8 const volatile *tmpAddr; + uint32 value; + + tmpAddr = (uint8 const volatile *) addr; + + value = (uint32) tmpAddr[0u]; + value |= ((uint32) tmpAddr[1u] << 8u ); + value |= ((uint32) tmpAddr[2u] << 16u); + + return(value); + } + + #endif /*(CY_PSOC4)*/ + +#endif /* (!CY_PSOC3) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/eeprom.hex b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/eeprom.hex new file mode 100755 index 00000000..e69de29b diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/project.h new file mode 100755 index 00000000..93cd634a --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/project.h @@ -0,0 +1,74 @@ +/******************************************************************************* + * File Name: project.h + * PSoC Creator 3.0 Component Pack 7 + * + * Description: + * This file is automatically generated by PSoC Creator and should not + * be edited by hand. + * + * + ******************************************************************************** + * Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. + * You may use this file only in accordance with the license, terms, conditions, + * disclaimers, and limitations in the end user license agreement accompanying + * the software package with which this file was provided. + ********************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/*[]*/ + diff --git a/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/protect.hex b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/protect.hex new file mode 100755 index 00000000..deab42f1 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/Generated_Source/PSoC5/protect.hex @@ -0,0 +1,3 @@ +:4000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C0 +:400040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080 +:00000001FF diff --git a/software/SCSI2SD/pbook/pbook.cydsn/OddParityGen b/software/SCSI2SD/pbook/pbook.cydsn/OddParityGen new file mode 120000 index 00000000..f6713f11 --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/OddParityGen @@ -0,0 +1 @@ +../../SCSI2SD.cydsn/OddParityGen/ \ No newline at end of file diff --git a/software/SCSI2SD/pbook/pbook.cydsn/TopDesign/TopDesign.cysch b/software/SCSI2SD/pbook/pbook.cydsn/TopDesign/TopDesign.cysch new file mode 100755 index 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/software/SCSI2SD/pbook/pbook.cydsn/pbook.svd b/software/SCSI2SD/pbook/pbook.cydsn/pbook.svd new file mode 100755 index 00000000..156f748f --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/pbook.svd @@ -0,0 +1,536 @@ + + + CY8C5267AXI_LP051 + 0.1 + CY8C52LP + 8 + 32 + + + USBFS + USBFS + 0x40004394 + + 0 + 0x1D0A + registers + + + + USBFS_PM_USB_CR0 + USB Power Mode Control Register 0 + 0x0 + 8 + read-write + 0 + 0 + + + fsusbio_ref_en + No description available + 0 + 0 + read-write + + + fsusbio_pd_n + No description available + 1 + 1 + read-write + + + fsusbio_pd_pullup_n + No description available + 2 + 2 + read-write + + + + + USBFS_PM_ACT_CFG + Active Power Mode Configuration Register + 0x11 + 8 + read-write + 0 + 0 + + + USBFS_PM_STBY_CFG + Standby Power Mode Configuration Register + 0x21 + 8 + read-write + 0 + 0 + + + USBFS_PRT_PS + Port Pin State Register + 0xE5D + 8 + read-write + 0 + 0 + + + PinState_DP + No description available + 6 + 6 + read-only + + + PinState_DM + No description available + 7 + 7 + read-only + + + + + USBFS_PRT_DM0 + Port Drive Mode Register + 0xE5E + 8 + read-write + 0 + 0 + + + DriveMode_DP + No description available + 6 + 6 + read-write + + + DriveMode_DM + No description available + 7 + 7 + read-write + + + + + USBFS_PRT_DM1 + Port Drive Mode Register + 0xE5F + 8 + read-write + 0 + 0 + + + PullUp_en_DP + No description available + 6 + 6 + read-write + + + PullUp_en_DM + No description available + 7 + 7 + read-write + + + + + USBFS_PRT_INP_DIS + Input buffer disable override + 0xE64 + 8 + read-write + 0 + 0 + + + seinput_dis_dp + No description available + 6 + 6 + read-write + + + seinput_dis_dm + No description available + 7 + 7 + read-write + + + + + USBFS_EP0_DR0 + bmRequestType + 0x1C6C + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR1 + bRequest + 0x1C6D + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR2 + wValueLo + 0x1C6E + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR3 + wValueHi + 0x1C6F + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR4 + wIndexLo + 0x1C70 + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR5 + wIndexHi + 0x1C71 + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR6 + lengthLo + 0x1C72 + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR7 + lengthHi + 0x1C73 + 8 + read-write + 0 + 0 + + + USBFS_CR0 + USB Control Register 0 + 0x1C74 + 8 + read-write + 0 + 0 + + + device_address + No description available + 6 + 0 + read-only + + + usb_enable + No description available + 7 + 7 + read-write + + + + + USBFS_CR1 + USB Control Register 1 + 0x1C75 + 8 + read-write + 0 + 0 + + + reg_enable + No description available + 0 + 0 + read-write + + + enable_lock + No description available + 1 + 1 + read-write + + + bus_activity + No description available + 2 + 2 + read-write + + + trim_offset_msb + No description available + 3 + 3 + read-write + + + + + USBFS_SIE_EP1_CR0 + The Endpoint1 Control Register + 0x1C7A + 8 + read-write + 0 + 0 + + + USBFS_USBIO_CR0 + USBIO Control Register 0 + 0x1C7C + 8 + read-write + 0 + 0 + + + rd + No description available + 0 + 0 + read-only + + + td + No description available + 5 + 5 + read-write + + + tse0 + No description available + 6 + 6 + read-write + + + ten + No description available + 7 + 7 + read-write + + + + + USBFS_USBIO_CR1 + USBIO Control Register 1 + 0x1C7E + 8 + read-write + 0 + 0 + + + dmo + No description available + 0 + 0 + read-only + + + dpo + No description available + 1 + 1 + read-only + + + usbpuen + No description available + 2 + 2 + read-write + + + iomode + No description available + 5 + 5 + read-write + + + + + USBFS_SIE_EP2_CR0 + The Endpoint2 Control Register + 0x1C8A + 8 + read-write + 0 + 0 + + + USBFS_SIE_EP3_CR0 + The Endpoint3 Control Register + 0x1C9A + 8 + read-write + 0 + 0 + + + USBFS_SIE_EP4_CR0 + The Endpoint4 Control Register + 0x1CAA + 8 + read-write + 0 + 0 + + + USBFS_SIE_EP5_CR0 + The Endpoint5 Control Register + 0x1CBA + 8 + read-write + 0 + 0 + + + USBFS_SIE_EP6_CR0 + The Endpoint6 Control Register + 0x1CCA + 8 + read-write + 0 + 0 + + + USBFS_SIE_EP7_CR0 + The Endpoint7 Control Register + 0x1CDA + 8 + read-write + 0 + 0 + + + USBFS_SIE_EP8_CR0 + The Endpoint8 Control Register + 0x1CEA + 8 + read-write + 0 + 0 + + + USBFS_BUF_SIZE + Dedicated Endpoint Buffer Size Register + 0x1CF8 + 8 + read-write + 0 + 0 + + + USBFS_EP_ACTIVE + Endpoint Active Indication Register + 0x1CFA + 8 + read-write + 0 + 0 + + + USBFS_EP_TYPE + Endpoint Type (IN/OUT) Indication + 0x1CFB + 8 + read-write + 0 + 0 + + + USBFS_USB_CLK_EN + USB Block Clock Enable Register + 0x1D09 + 8 + read-write + 0 + 0 + + + + + SD_Clk_Ctl + No description available + 0x40006474 + + 0 + 0x1 + registers + + + + SD_Clk_Ctl_CONTROL_REG + No description available + 0x0 + 8 + read-write + 0 + 0 + + + + + SCSI_CTL_IO + No description available + 0x4000647F + + 0 + 0x1 + registers + + + + SCSI_CTL_IO_CONTROL_REG + No description available + 0x0 + 8 + read-write + 0 + 0 + + + + + \ No newline at end of file diff --git a/software/SCSI2SD/pbook/pbook.cydsn/scsiTarget b/software/SCSI2SD/pbook/pbook.cydsn/scsiTarget new file mode 120000 index 00000000..9cc2389a --- /dev/null +++ b/software/SCSI2SD/pbook/pbook.cydsn/scsiTarget @@ -0,0 +1 @@ +../../SCSI2SD.cydsn/scsiTarget/ \ No newline at end of file diff --git a/software/SCSI2SD/SCSI2SD.cydsn/bits.c b/software/SCSI2SD/src/bits.c similarity index 100% rename from software/SCSI2SD/SCSI2SD.cydsn/bits.c rename to software/SCSI2SD/src/bits.c diff --git a/software/SCSI2SD/SCSI2SD.cydsn/bits.h b/software/SCSI2SD/src/bits.h similarity index 100% rename from software/SCSI2SD/SCSI2SD.cydsn/bits.h rename to software/SCSI2SD/src/bits.h diff --git a/software/SCSI2SD/SCSI2SD.cydsn/config.c b/software/SCSI2SD/src/config.c similarity index 100% rename from software/SCSI2SD/SCSI2SD.cydsn/config.c rename to software/SCSI2SD/src/config.c diff --git a/software/SCSI2SD/SCSI2SD.cydsn/config.h b/software/SCSI2SD/src/config.h similarity index 100% rename from software/SCSI2SD/SCSI2SD.cydsn/config.h rename to software/SCSI2SD/src/config.h diff --git a/software/SCSI2SD/SCSI2SD.cydsn/diagnostic.c b/software/SCSI2SD/src/diagnostic.c similarity index 100% rename from software/SCSI2SD/SCSI2SD.cydsn/diagnostic.c rename to software/SCSI2SD/src/diagnostic.c diff --git a/software/SCSI2SD/SCSI2SD.cydsn/diagnostic.h b/software/SCSI2SD/src/diagnostic.h similarity index 100% rename from software/SCSI2SD/SCSI2SD.cydsn/diagnostic.h rename to software/SCSI2SD/src/diagnostic.h diff --git a/software/SCSI2SD/SCSI2SD.cydsn/disk.c b/software/SCSI2SD/src/disk.c similarity index 100% rename from software/SCSI2SD/SCSI2SD.cydsn/disk.c rename to software/SCSI2SD/src/disk.c diff --git a/software/SCSI2SD/SCSI2SD.cydsn/disk.h b/software/SCSI2SD/src/disk.h similarity index 100% rename from software/SCSI2SD/SCSI2SD.cydsn/disk.h rename to software/SCSI2SD/src/disk.h diff --git a/software/SCSI2SD/SCSI2SD.cydsn/geometry.c b/software/SCSI2SD/src/geometry.c similarity index 100% rename from software/SCSI2SD/SCSI2SD.cydsn/geometry.c rename to software/SCSI2SD/src/geometry.c diff --git a/software/SCSI2SD/SCSI2SD.cydsn/geometry.h b/software/SCSI2SD/src/geometry.h similarity index 100% rename from software/SCSI2SD/SCSI2SD.cydsn/geometry.h rename to software/SCSI2SD/src/geometry.h diff --git a/software/SCSI2SD/SCSI2SD.cydsn/inquiry.c b/software/SCSI2SD/src/inquiry.c similarity index 95% rename from software/SCSI2SD/SCSI2SD.cydsn/inquiry.c rename to software/SCSI2SD/src/inquiry.c index d5a3d85f..da03eba8 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/inquiry.c +++ b/software/SCSI2SD/src/inquiry.c @@ -29,8 +29,8 @@ static uint8 StandardResponse[] = 0x02, // Complies with ANSI SCSI-2. 0x01, // Response format is compatible with the old CCS format. 0x1f, // standard length. -0, 0, //Reserved -0 // We don't support anything at all +0, 0, // Reserved +0x08 // Enable linked commands }; // Vendor set by config 'c','o','d','e','s','r','c',' ', // prodId set by config'S','C','S','I','2','S','D',' ',' ',' ',' ',' ',' ',' ',' ',' ', diff --git a/software/SCSI2SD/SCSI2SD.cydsn/inquiry.h b/software/SCSI2SD/src/inquiry.h similarity index 100% rename from software/SCSI2SD/SCSI2SD.cydsn/inquiry.h rename to software/SCSI2SD/src/inquiry.h diff --git a/software/SCSI2SD/SCSI2SD.cydsn/led.h b/software/SCSI2SD/src/led.h similarity index 100% rename from software/SCSI2SD/SCSI2SD.cydsn/led.h rename to software/SCSI2SD/src/led.h diff --git a/software/SCSI2SD/SCSI2SD.cydsn/main.c b/software/SCSI2SD/src/main.c similarity index 100% rename from software/SCSI2SD/SCSI2SD.cydsn/main.c rename to software/SCSI2SD/src/main.c diff --git a/software/SCSI2SD/SCSI2SD.cydsn/mode.c b/software/SCSI2SD/src/mode.c similarity index 100% rename from software/SCSI2SD/SCSI2SD.cydsn/mode.c rename to software/SCSI2SD/src/mode.c diff --git a/software/SCSI2SD/SCSI2SD.cydsn/mode.h b/software/SCSI2SD/src/mode.h similarity index 100% rename from software/SCSI2SD/SCSI2SD.cydsn/mode.h rename to software/SCSI2SD/src/mode.h diff --git a/software/SCSI2SD/SCSI2SD.cydsn/scsi.c b/software/SCSI2SD/src/scsi.c similarity index 89% rename from software/SCSI2SD/SCSI2SD.cydsn/scsi.c rename to software/SCSI2SD/src/scsi.c index 2dbcd364..af7af329 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/scsi.c +++ b/software/SCSI2SD/src/scsi.c @@ -46,23 +46,8 @@ static void process_Command(void); static void doReserveRelease(void); -static uint8_t CmdTimerComplete = 0; -CY_ISR(CommandTimerISR) -{ - CmdTimerComplete = 1; -} - static void enter_BusFree() { - // Spin until the 10us timer has stopped. - // Required for Akai MPC3000, and possibly other broken controllers. - // 1,2us: Cannot see SCSI device. - // 5us: Can see SCSI device, format fails - // 10us: Format succeeds. - // 25us: Format fails. - while (!CmdTimerComplete) {} - SCSI_CMD_TIMER_Stop(); - SCSI_ClearPin(SCSI_Out_BSY); // We now have a Bus Clear Delay of 800ns to release remaining signals. SCSI_ClearPin(SCSI_Out_MSG); @@ -94,6 +79,19 @@ static void process_MessageIn() // back to MESSAGE_OUT first, get out parity error message, then come // back here. } + else if ((scsiDev.msgIn == MSG_LINKED_COMMAND_COMPLETE) || + (scsiDev.msgIn == MSG_LINKED_COMMAND_COMPLETE_WITH_FLAG)) + { + // Go back to the command phase and start again. + scsiDev.phase = COMMAND; + scsiDev.parityError = 0; + scsiDev.dataPtr = 0; + scsiDev.savedDataPtr = 0; + scsiDev.dataLen = 0; + scsiDev.status = GOOD; + transfer.blocks = 0; + transfer.currentBlock = 0; + } else /*if (scsiDev.msgIn == MSG_COMMAND_COMPLETE)*/ { enter_BusFree(); @@ -121,6 +119,27 @@ static void enter_Status(uint8 status) static void process_Status() { scsiEnterPhase(STATUS); + + uint8 message; + + uint8 control = scsiDev.cdb[scsiDev.cdbLen - 1]; + if ((scsiDev.status == GOOD) && (control & 0x01)) + { + // Linked command. + scsiDev.status = INTERMEDIATE; + if (control & 0x02) + { + message = MSG_LINKED_COMMAND_COMPLETE_WITH_FLAG; + } + else + { + message = MSG_LINKED_COMMAND_COMPLETE; + } + } + else + { + message = MSG_COMMAND_COMPLETE; + } scsiWriteByte(scsiDev.status); #ifdef MM_DEBUG @@ -130,7 +149,7 @@ static void process_Status() // Command Complete occurs AFTER a valid status has been // sent. then we go bus-free. - enter_MessageIn(MSG_COMMAND_COMPLETE); + enter_MessageIn(message); } static void enter_DataIn(int len) @@ -201,9 +220,9 @@ static const uint8 CmdGroupBytes[8] = {6, 10, 10, 6, 6, 12, 6, 6}; static void process_Command() { int group; - int cmdSize; uint8 command; uint8 lun; + uint8 control; scsiEnterPhase(COMMAND); scsiDev.parityError = 0; @@ -212,11 +231,12 @@ static void process_Command() scsiDev.cdb[0] = scsiReadByte(); group = scsiDev.cdb[0] >> 5; - cmdSize = CmdGroupBytes[group]; - scsiRead(scsiDev.cdb + 1, cmdSize - 1); + scsiDev.cdbLen = CmdGroupBytes[group]; + scsiRead(scsiDev.cdb + 1, scsiDev.cdbLen - 1); command = scsiDev.cdb[0]; lun = scsiDev.cdb[1] >> 5; + control = scsiDev.cdb[scsiDev.cdbLen - 1]; #ifdef MM_DEBUG scsiDev.cmdCount++; @@ -237,6 +257,13 @@ static void process_Command() scsiDev.sense.asc = SCSI_PARITY_ERROR; enter_Status(CHECK_CONDITION); } + else if ((control & 0x02) && ((control & 0x01) == 0)) + { + // FLAG set without LINK flag. + scsiDev.sense.code = ILLEGAL_REQUEST; + scsiDev.sense.asc = INVALID_FIELD_IN_CDB; + enter_Status(CHECK_CONDITION); + } else if (command == 0x12) { scsiInquiry(); @@ -411,8 +438,6 @@ static void scsiReset() scsiDev.sense.code = NO_SENSE; scsiDev.sense.asc = NO_ADDITIONAL_SENSE_INFORMATION; scsiDiskReset(); - - SCSI_CMD_TIMER_Stop(); // Sleep to allow the bus to settle down a bit. // We must be ready again within the "Reset to selection time" of @@ -468,11 +493,6 @@ static void process_SelectionPhase() // for our BSY response, which is actually a very generous 250ms) SCSI_SetPin(SCSI_Out_BSY); ledOn(); - - // Used in enter_BusFree() to ensure each command takes at least 10us. - // as required by some old SCSI controllers (MPC3000). - CmdTimerComplete = 0; - SCSI_CMD_TIMER_Enable(); #ifdef MM_DEBUG scsiDev.selCount++; @@ -771,9 +791,6 @@ void scsiPoll(void) void scsiInit() { - SCSI_CMD_TIMER_Init(); // config but don't start the timeout counter - SCSI_CMD_TIMER_ISR_StartEx(CommandTimerISR); // setup timer interrupt sub-routine - scsiDev.scsiIdMask = 1 << (config->scsiId); scsiDev.atnFlag = 0; diff --git a/software/SCSI2SD/SCSI2SD.cydsn/scsi.h b/software/SCSI2SD/src/scsi.h similarity index 90% rename from software/SCSI2SD/SCSI2SD.cydsn/scsi.h rename to software/SCSI2SD/src/scsi.h index 3e72396e..4ef24995 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/scsi.h +++ b/software/SCSI2SD/src/scsi.h @@ -17,14 +17,6 @@ #ifndef SCSI_H #define SCSI_H -// SCSI documentation goes here -// SCSI-2. -// Single LUN -// No tagged-queuing support - single command at a time. -// All read/write commands disconnect. State SD card latency. -// Fixed 512 byte sector size. -// 2TB limit, based on 32bit LBA (read16/write16 not supported) - // Set this to true to log SCSI commands and status information via // USB HID packets. The can be captured and viewed in wireshark. // For windows users, capture using USBPcap http://desowin.org/usbpcap/ @@ -58,14 +50,16 @@ typedef enum GOOD = 0, CHECK_CONDITION = 2, BUSY = 0x8, + INTERMEDIATE = 0x10, CONFLICT = 0x18 } SCSI_STATUS; typedef enum { MSG_COMMAND_COMPLETE = 0, - MSG_REJECT = 0x7 - + MSG_REJECT = 0x7, + MSG_LINKED_COMMAND_COMPLETE = 0x0A, + MSG_LINKED_COMMAND_COMPLETE_WITH_FLAG = 0x0B } SCSI_MESSAGE; typedef struct @@ -90,6 +84,7 @@ typedef struct int dataLen; uint8 cdb[12]; // command descriptor block + uint8 cdbLen; // 6, 10, or 12 byte message. // Only let the reserved initiator talk to us. // A 3rd party may be sending the RESERVE/RELEASE commands diff --git a/software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.c b/software/SCSI2SD/src/scsiPhy.c similarity index 90% rename from software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.c rename to software/SCSI2SD/src/scsiPhy.c index dfb4d887..6a8052f6 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.c +++ b/software/SCSI2SD/src/scsiPhy.c @@ -49,6 +49,9 @@ uint8 scsiReadByte(void) CY_SET_REG8(scsiTarget_datapath__F0_REG, 0); while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 2) && !scsiDev.resetFlag) {} + + while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {} + return CY_GET_REG8(scsiTarget_datapath__F1_REG); } @@ -70,6 +73,8 @@ void scsiRead(uint8* data, uint32 count) ++i; } } + while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {} + } void scsiWriteByte(uint8 value) @@ -82,7 +87,9 @@ void scsiWriteByte(uint8 value) //while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 4)) {} while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 2) && !scsiDev.resetFlag) {} - value = CY_GET_REG8(scsiTarget_datapath__F1_REG); + value = CY_GET_REG8(scsiTarget_datapath__F1_REG); + + while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {} } void scsiWrite(uint8* data, uint32 count) @@ -103,6 +110,8 @@ void scsiWrite(uint8* data, uint32 count) ++i; } } + + while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {} } static void busSettleDelay(void) diff --git a/software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.h b/software/SCSI2SD/src/scsiPhy.h similarity index 100% rename from software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.h rename to software/SCSI2SD/src/scsiPhy.h diff --git a/software/SCSI2SD/SCSI2SD.cydsn/sd.c b/software/SCSI2SD/src/sd.c similarity index 93% rename from software/SCSI2SD/SCSI2SD.cydsn/sd.c rename to software/SCSI2SD/src/sd.c index 95016883..28980c69 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/sd.c +++ b/software/SCSI2SD/src/sd.c @@ -243,6 +243,8 @@ static void doReadSector() sdSpiByte(0xFF); // CRC scsiDev.dataLen = SCSI_BLOCK_SIZE; scsiDev.dataPtr = SCSI_BLOCK_SIZE; + + while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {} } void sdReadSectorSingle() @@ -431,6 +433,8 @@ int sdWriteSector() result = 1; } + while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {} + return result; } @@ -632,6 +636,12 @@ int sdInit() // So we run the MASTER_CLK and BUS_CLK at 60MHz, and run the SPI clock at 30MHz // (15MHz SPI transfer clock). SDCard_Stop(); + + // We can't run at full-speed with the pullup resistors enabled. + SD_MISO_SetDriveMode(SD_MISO_DM_DIG_HIZ); + SD_MOSI_SetDriveMode(SD_MOSI_DM_STRONG); + SD_SCK_SetDriveMode(SD_SCK_DM_STRONG); + SD_Data_Clk_Start(); // Turn on the fast clock SD_Clk_Ctl_Write(1); // Select the fast clock source. SD_Init_Clk_Stop(); // Stop the slow clock. diff --git a/software/SCSI2SD/SCSI2SD.cydsn/sd.h b/software/SCSI2SD/src/sd.h similarity index 100% rename from software/SCSI2SD/SCSI2SD.cydsn/sd.h rename to software/SCSI2SD/src/sd.h diff --git a/software/SCSI2SD/SCSI2SD.cydsn/sense.h b/software/SCSI2SD/src/sense.h similarity index 100% rename from software/SCSI2SD/SCSI2SD.cydsn/sense.h rename to software/SCSI2SD/src/sense.h diff --git a/software/bootloaderhost/main.c b/software/bootloaderhost/main.c index c42f41f2..f09f7915 100644 --- a/software/bootloaderhost/main.c +++ b/software/bootloaderhost/main.c @@ -82,7 +82,8 @@ static void ProgressUpdate(unsigned char arrayId, unsigned short rowNum) static void usage() { - printf("Usage: bootloaderhost [-v UsbVendorId] [-p UsbProductId] /path/to/firmware.cyacd\n"); + printf("Usage: bootloaderhost [-v UsbVendorId] [-p UsbProductId] [-f] /path/to/firmware.cyacd\n"); + printf("\t-f\tForce, even if the firmware doesn't match the target board.\n"); printf("\n\n"); } @@ -102,10 +103,11 @@ int main(int argc, char* argv[]) uint16_t vendorId = 0x04B4; // Cypress uint16_t productId = 0xB71D; // Default PSoC3/5LP Bootloader + int force = 0; opterr = 0; int c; - while ((c = getopt(argc, argv, "v:p:")) != -1) + while ((c = getopt(argc, argv, "v:p:f")) != -1) { switch (c) { @@ -115,6 +117,9 @@ int main(int argc, char* argv[]) case 'p': sscanf(optarg, "%hx", &productId); break; + case 'f': + force = 1; + break; case '?': usage(); exit(1); @@ -157,7 +162,43 @@ int main(int argc, char* argv[]) printf("\n"); printf(" Manufacturer: %ls\n", dev->manufacturer_string); printf(" Product: %ls\n", dev->product_string); + + int fileMismatch = 0; + const char* expectedName = NULL; + switch (dev->release_number) + { + case 0x3001: + printf(" Release: 3.5\" SCSI2SD\n"); + expectedName = "SCSI2SD.cyacd"; + if (!strstr(filename, expectedName)) + { + fileMismatch = 1; + } + break; + case 0x3002: + printf(" Release: 2.5\" SCSI2SD for Apple Powerbook\n"); + expectedName = "pbook.cyacd"; + if (!strstr(filename, expectedName)) + { + fileMismatch = 1; + } + break; + default: + printf(" Release: Unknown hardware\n"); + expectedName = "unknown"; + fileMismatch = 1; + } printf("\n"); + + if (fileMismatch && !force) + { + fprintf(stderr, "ERROR: Unexpected firmware file. Expected: \"%s\"\n" + "Using firmware design for a different board may destroy your " + "hardware.\n" + "If you still wish to proceed, try again with the \"-f\" flag.\n", + expectedName); + exit(1); + } //hid_free_enumeration(devs); // Open the device using the VID, PID, -- 2.38.5

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W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cm3.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cmFunc.h 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W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cm3.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cmFunc.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cmInstr.h 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W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_std.c + +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_std.c : + +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_vnd.o : W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h 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W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c + +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c : + +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/cymetadata.o : W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c + +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c : + +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/cyutils.o : W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyutils.c + +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyutils.c : diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/.deps/C_FILE.P b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/.deps/C_FILE.P index df2efd72..aa6db687 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/.deps/C_FILE.P +++ b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/.deps/C_FILE.P @@ -1,66 +1,70 @@ -W:/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/main.o : W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL_PVT.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cm3.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cmFunc.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cmInstr.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydisabledsheets.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cypins.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/project.h W:/SCSI2SD/USB_Bootloader.cydsn/main.c +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/main.o : W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL_PVT.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP_aliases.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cm3.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cmFunc.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cmInstr.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydisabledsheets.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cypins.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/project.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/main.c -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL.h : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL.h : -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL_PVT.h : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL_PVT.h : -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h : -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h : -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h : -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h : -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h : -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h : -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.h : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.h : -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.h : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP_aliases.h : -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.h : -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.h : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.h : -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h : -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.h : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.h : -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.h : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h : -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.h : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.h : -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.h : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.h : -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.h : -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cm3.h : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.h : -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h : -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cmFunc.h : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cm3.h : -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cmInstr.h : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h : -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cmFunc.h : -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cmInstr.h : -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h : -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydisabledsheets.h : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h : -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h : -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydisabledsheets.h : -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cypins.h : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h : -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h : -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/project.h : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cypins.h : -W:/SCSI2SD/USB_Bootloader.cydsn/main.c : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h : + +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/project.h : + +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/main.c : diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/.deps/GNU_ARM_ASM_FILE.P b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/.deps/GNU_ARM_ASM_FILE.P index 0695d221..75956332 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/.deps/GNU_ARM_ASM_FILE.P +++ b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/.deps/GNU_ARM_ASM_FILE.P @@ -1,10 +1,10 @@ -W:/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyBootAsmGnu.o : W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu.inc W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfittergnu.inc W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyBootAsmGnu.o : W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu.inc W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfittergnu.inc W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu.inc : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu.inc : -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc : -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfittergnu.inc : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfittergnu.inc : -W:/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s : +W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s : diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/BL.lst b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/BL.lst index 0039c49c..5fc2a5b8 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/BL.lst +++ b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/BL.lst @@ -1,4 +1,4 @@ -ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 +ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 1 1 .syntax unified @@ -58,7 +58,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 30:.\Generated_Source\PSoC5/BL.c **** * proper values at runtime. 31:.\Generated_Source\PSoC5/BL.c **** *******************************************************************************/ 32:.\Generated_Source\PSoC5/BL.c **** #if defined(__ARMCC_VERSION) || defined (__GNUC__) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 2 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 2 33:.\Generated_Source\PSoC5/BL.c **** __attribute__((section (".bootloader"))) @@ -118,7 +118,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 87:.\Generated_Source\PSoC5/BL.c **** /* Implementation for the PSoC 3 resides in a BL_psoc3.a51 file. */ 88:.\Generated_Source\PSoC5/BL.c **** static void BL_LaunchBootloadable(uint32 appAddr); 89:.\Generated_Source\PSoC5/BL.c **** #endif /* (!CY_PSOC3) */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 3 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 3 90:.\Generated_Source\PSoC5/BL.c **** @@ -178,7 +178,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 144:.\Generated_Source\PSoC5/BL.c **** size--; 145:.\Generated_Source\PSoC5/BL.c **** } 146:.\Generated_Source\PSoC5/BL.c **** while(0u != size); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 4 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 4 147:.\Generated_Source\PSoC5/BL.c **** @@ -238,7 +238,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 201:.\Generated_Source\PSoC5/BL.c **** } 202:.\Generated_Source\PSoC5/BL.c **** 203:.\Generated_Source\PSoC5/BL.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 5 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 5 204:.\Generated_Source\PSoC5/BL.c **** #if(!CY_PSOC4) @@ -298,7 +298,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 258:.\Generated_Source\PSoC5/BL.c **** * - Schedule bootloadable and reset device 259:.\Generated_Source\PSoC5/BL.c **** * 260:.\Generated_Source\PSoC5/BL.c **** * Parameters: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 6 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 6 261:.\Generated_Source\PSoC5/BL.c **** * None @@ -358,7 +358,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 315:.\Generated_Source\PSoC5/BL.c **** #endif /* (CY_PSOC4) */ 316:.\Generated_Source\PSoC5/BL.c **** 317:.\Generated_Source\PSoC5/BL.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 7 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 7 318:.\Generated_Source\PSoC5/BL.c **** /*********************************************************************** @@ -418,7 +418,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 372:.\Generated_Source\PSoC5/BL.c **** 373:.\Generated_Source\PSoC5/BL.c **** 374:.\Generated_Source\PSoC5/BL.c **** /* Schedule bootloadable application and perform software reset */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 8 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 8 375:.\Generated_Source\PSoC5/BL.c **** BL_LaunchApplication(); @@ -478,7 +478,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 429:.\Generated_Source\PSoC5/BL.c **** if (0u == (BL_RES_CAUSE_REG & BL_RES_CAUSE_RESET_SOFT)) 430:.\Generated_Source\PSoC5/BL.c **** { 431:.\Generated_Source\PSoC5/BL.c **** cyBtldrRunType = 0u; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 9 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 9 432:.\Generated_Source\PSoC5/BL.c **** } @@ -538,7 +538,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 38 .thumb 39 .cfi_endproc 40 .LFE62: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 10 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 10 41 .size BL_LaunchBootloadable, .-BL_LaunchBootloadable @@ -598,7 +598,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 520:.\Generated_Source\PSoC5/BL.c **** 521:.\Generated_Source\PSoC5/BL.c **** #endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ 522:.\Generated_Source\PSoC5/BL.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 11 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 11 523:.\Generated_Source\PSoC5/BL.c **** @@ -658,7 +658,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 577:.\Generated_Source\PSoC5/BL.c **** { 578:.\Generated_Source\PSoC5/BL.c **** return(CYRET_BAD_DATA); 579:.\Generated_Source\PSoC5/BL.c **** } - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 12 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 12 580:.\Generated_Source\PSoC5/BL.c **** @@ -718,7 +718,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 634:.\Generated_Source\PSoC5/BL.c **** /* Enable global interrupts */ 635:.\Generated_Source\PSoC5/BL.c **** CyGlobalIntEnable; 636:.\Generated_Source\PSoC5/BL.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 13 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 13 637:.\Generated_Source\PSoC5/BL.c **** do @@ -778,7 +778,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 691:.\Generated_Source\PSoC5/BL.c **** 692:.\Generated_Source\PSoC5/BL.c **** rspSize = 0u; 693:.\Generated_Source\PSoC5/BL.c **** if(ackCode == CYRET_SUCCESS) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 14 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 14 694:.\Generated_Source\PSoC5/BL.c **** { @@ -838,7 +838,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 748:.\Generated_Source\PSoC5/BL.c **** rspSize = 1u; 749:.\Generated_Source\PSoC5/BL.c **** ackCode = CYRET_SUCCESS; 750:.\Generated_Source\PSoC5/BL.c **** } - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 15 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 15 751:.\Generated_Source\PSoC5/BL.c **** break; @@ -898,7 +898,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 805:.\Generated_Source\PSoC5/BL.c **** rspSize = 2u; 806:.\Generated_Source\PSoC5/BL.c **** ackCode = CYRET_SUCCESS; 807:.\Generated_Source\PSoC5/BL.c **** } - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 16 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 16 808:.\Generated_Source\PSoC5/BL.c **** break; @@ -958,7 +958,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 862:.\Generated_Source\PSoC5/BL.c **** { 863:.\Generated_Source\PSoC5/BL.c **** 864:.\Generated_Source\PSoC5/BL.c **** /* The command may be sent along with the last block of data, to program the ro - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 17 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 17 865:.\Generated_Source\PSoC5/BL.c **** #if(CY_PSOC3) @@ -1018,7 +1018,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 919:.\Generated_Source\PSoC5/BL.c **** (void) memset(erase, (char8) 0, (int16) BL_FROW_SIZE); 920:.\Generated_Source\PSoC5/BL.c **** #else 921:.\Generated_Source\PSoC5/BL.c **** (void) memset(erase, 0, BL_FROW_SIZE); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 18 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 18 922:.\Generated_Source\PSoC5/BL.c **** #endif /* (CY_PSOC3) */ @@ -1078,7 +1078,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 976:.\Generated_Source\PSoC5/BL.c **** * refuse to program as it would corrupt the active app. 977:.\Generated_Source\PSoC5/BL.c **** ******************************************************************* 978:.\Generated_Source\PSoC5/BL.c **** if(((row >= firstRow) && (row <= lastRow)) || - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 19 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 19 979:.\Generated_Source\PSoC5/BL.c **** ((btldrData == BL_MD_FLASH_ARRAY_NUM) && @@ -1138,7 +1138,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1033:.\Generated_Source\PSoC5/BL.c **** } 1034:.\Generated_Source\PSoC5/BL.c **** break; 1035:.\Generated_Source\PSoC5/BL.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 20 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 20 1036:.\Generated_Source\PSoC5/BL.c **** #endif /* (0u != BL_CMD_SYNC_BOOTLOADER_AVAIL) */ @@ -1198,7 +1198,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1090:.\Generated_Source\PSoC5/BL.c **** &packetBuffer[BL_DATA_ADDR], 1091:.\Generated_Source\PSoC5/BL.c **** pktSize); 1092:.\Generated_Source\PSoC5/BL.c **** #endif /* (CY_PSOC3) */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 21 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 21 1093:.\Generated_Source\PSoC5/BL.c **** @@ -1258,7 +1258,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1147:.\Generated_Source\PSoC5/BL.c **** ***************************************************************************/ 1148:.\Generated_Source\PSoC5/BL.c **** case BL_COMMAND_VERIFY: 1149:.\Generated_Source\PSoC5/BL.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 22 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 22 1150:.\Generated_Source\PSoC5/BL.c **** if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 3u)) @@ -1318,7 +1318,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1204:.\Generated_Source\PSoC5/BL.c **** 1205:.\Generated_Source\PSoC5/BL.c **** #endif /* (!CY_PSOC4) && (CYDEV_ECC_ENABLE == 0u) */ 1206:.\Generated_Source\PSoC5/BL.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 23 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 23 1207:.\Generated_Source\PSoC5/BL.c **** @@ -1378,7 +1378,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1261:.\Generated_Source\PSoC5/BL.c **** ******************************************************************************** 1262:.\Generated_Source\PSoC5/BL.c **** * 1263:.\Generated_Source\PSoC5/BL.c **** * Summary: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 24 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 24 1264:.\Generated_Source\PSoC5/BL.c **** * Creates a bootloader responce packet and transmits it back to the bootloader @@ -1438,7 +1438,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1318:.\Generated_Source\PSoC5/BL.c **** * None 1319:.\Generated_Source\PSoC5/BL.c **** * 1320:.\Generated_Source\PSoC5/BL.c **** *******************************************************************************/ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 25 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 25 1321:.\Generated_Source\PSoC5/BL.c **** void BL_SetFlashByte(uint32 address, uint8 runType) @@ -1498,7 +1498,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 49 .loc 1 1374 0 50 .cfi_startproc 51 @ args = 0, pretend = 0, frame = 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 26 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 26 52 @ frame_needed = 0, uses_anonymous_args = 0 @@ -1558,7 +1558,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 86 001c 1BE0 b .L6 87 .L8: 88 .LVL4: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 27 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 27 1393:.\Generated_Source\PSoC5/BL.c **** #if(!CY_PSOC3) @@ -1618,7 +1618,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1424:.\Generated_Source\PSoC5/BL.c **** 1425:.\Generated_Source\PSoC5/BL.c **** /* Read all fields as big-endian */ 1426:.\Generated_Source\PSoC5/BL.c **** if (2u == fieldSize) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 28 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 28 1427:.\Generated_Source\PSoC5/BL.c **** { @@ -1678,7 +1678,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 145 .loc 1 1403 0 146 0054 0C4B ldr r3, .L26+24 147 .L6: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 29 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 29 148 .LVL18: @@ -1738,7 +1738,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 180 007c D4FF0100 .word 131028 181 0080 C5FF0100 .word 131013 182 0084 D8FF0100 .word 131032 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 30 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 30 183 0088 C9FF0100 .word 131017 @@ -1798,7 +1798,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 229 .loc 1 510 0 230 0022 2546 mov r5, r4 231 .LVL32: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 31 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 31 232 .L29: @@ -1858,7 +1858,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 276 .LVL41: 277 .L39: 278 0052 4FF48046 mov r6, #16384 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 32 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 32 279 .LVL42: @@ -1918,7 +1918,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 321 007e 70BD pop {r4, r5, r6, pc} 322 .L47: 323 .align 2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 33 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 33 324 .L46: @@ -1978,7 +1978,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 371 0014 4FF00A09 mov r9, #10 618:.\Generated_Source\PSoC5/BL.c **** uint16 CYDATA dataOffset = 0u; 372 .loc 1 618 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 34 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 34 373 0018 3746 mov r7, r6 @@ -2038,7 +2038,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 418 .loc 1 660 0 is_stmt 0 discriminator 1 419 005a 9DF82831 ldrb r3, [sp, #296] @ zero_extendqisi2 420 005e 012B cmp r3, #1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 35 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 35 421 0060 40F07681 bne .L90 @@ -2098,7 +2098,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 461 .loc 1 161 0 462 0090 0DF22714 addw r4, sp, #295 463 0094 E45C ldrb r4, [r4, r3] @ zero_extendqisi2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 36 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 36 162:.\Generated_Source\PSoC5/BL.c **** size--; @@ -2158,7 +2158,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 508 00ca 8DF82C41 strb r4, [sp, #300] 773:.\Generated_Source\PSoC5/BL.c **** packetBuffer[BL_DATA_ADDR + 1u] = HI8(startRow); 509 .loc 1 773 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 37 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 37 510 00ce 8DF82D41 strb r4, [sp, #301] @@ -2218,7 +2218,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 162:.\Generated_Source\PSoC5/BL.c **** size--; 551 .loc 1 162 0 552 0100 013B subs r3, r3, #1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 38 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 38 161:.\Generated_Source\PSoC5/BL.c **** sum += buffer[size - 1u]; @@ -2278,7 +2278,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 593 0130 FFF7FEFF bl USBFS_CyBtldrCommWrite 594 .LVL78: 595 .L55: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 39 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 39 596 .LBE33: @@ -2338,7 +2338,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 642 .loc 1 743 0 is_stmt 0 discriminator 1 643 0192 002D cmp r5, #0 644 0194 40F0DC80 bne .L90 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 40 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 40 746:.\Generated_Source\PSoC5/BL.c **** (uint8)(BL_ValidateBootloadable(BL_activeApp) == CYRET_SUCCESS); @@ -2398,7 +2398,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 870:.\Generated_Source\PSoC5/BL.c **** (void) memcpy(&dataBuffer[dataOffset], 690 .loc 1 870 0 is_stmt 1 691 01e0 033D subs r5, r5, #3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 41 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 41 692 .LVL91: @@ -2458,7 +2458,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 733 .loc 1 906 0 734 021e 11D8 bhi .L68 912:.\Generated_Source\PSoC5/BL.c **** if(0u == clearedMetaData) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 42 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 42 735 .loc 1 912 0 @@ -2518,7 +2518,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 781 0262 002E cmp r6, #0 782 0264 74D0 beq .L90 1080:.\Generated_Source\PSoC5/BL.c **** if((dataOffset + pktSize) <= BL_SIZEOF_COMMAND_BUFFER) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 43 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 43 783 .loc 1 1080 0 @@ -2578,7 +2578,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 827 0298 21E7 b .L61 828 .LVL113: 829 .L73: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 44 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 44 830 .LBE25: @@ -2638,7 +2638,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 871 .LVL118: 229:.\Generated_Source\PSoC5/BL.c **** while (size > 0u) 872 .loc 1 229 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 45 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 45 873 02c8 F8D1 bne .L75 @@ -2698,7 +2698,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 917 .loc 1 1201 0 discriminator 2 918 02f4 545C ldrb r4, [r2, r1] @ zero_extendqisi2 919 02f6 0132 adds r2, r2, #1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 46 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 46 920 02f8 1B19 adds r3, r3, r4 @@ -2758,7 +2758,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 962 .L80: 963 .LBE26: 1232:.\Generated_Source\PSoC5/BL.c **** if(CYRET_SUCCESS == BL_ValidateBootloadable(BL_activeApp)) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 47 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 47 964 .loc 1 1232 0 @@ -2818,7 +2818,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1010 034e FBE7 b .L131 1011 .L90: 663:.\Generated_Source\PSoC5/BL.c **** ackCode = BL_ERR_DATA; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 48 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 48 1012 .loc 1 663 0 @@ -2878,7 +2878,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1061 0000 10B5 push {r4, lr} 1062 .LCFI4: 1063 .cfi_def_cfa_offset 8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 49 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 49 1064 .cfi_offset 4, -8 @@ -2938,7 +2938,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1109 .LVL156: 1110 0032 F9E7 b .L143 1111 .L161: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 50 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 50 1112 .LBE42: @@ -2998,7 +2998,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1154 .loc 1 369 0 1155 0064 1420 movs r0, #20 1156 0066 FFF7FEFF bl BL_HostLink - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 51 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 51 1157 .LVL163: @@ -3058,7 +3058,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 447:.\Generated_Source\PSoC5/BL.c **** if(0u != BL_GetMetadata(BL_GET_METADATA_BTLDB_ADDR, BL_activeApp)) 1205 .loc 1 447 0 1206 0012 0120 movs r0, #1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 52 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 52 1207 0014 FFF7FEFF bl BL_GetMetadata.constprop.1 @@ -3118,7 +3118,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1254 .loc 1 1327 0 1255 0008 C0F30744 ubfx r4, r0, #16, #8 1256 .LVL169: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 53 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 53 1331:.\Generated_Source\PSoC5/BL.c **** uint32 baseAddr = address - (address % CYDEV_FLS_ROW_SIZE); @@ -3178,7 +3178,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1305 .size BL_SizeBytes, 4 1306 BL_SizeBytes: 1307 0000 FFFFFFFF .word -1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 54 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 54 1308 .type BL_Checksum, %object @@ -3212,10 +3212,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1336 0006 00000000 .4byte .Ldebug_abbrev0 1337 000a 04 .byte 0x4 1338 000b 01 .uleb128 0x1 - 1339 000c F9010000 .4byte .LASF92 + 1339 000c 0A020000 .4byte .LASF92 1340 0010 01 .byte 0x1 - 1341 0011 42020000 .4byte .LASF93 - 1342 0015 E3000000 .4byte .LASF94 + 1341 0011 53020000 .4byte .LASF93 + 1342 0015 13010000 .4byte .LASF94 1343 0019 18000000 .4byte .Ldebug_ranges0+0x18 1344 001d 00000000 .4byte 0 1345 0021 00000000 .4byte 0 @@ -3223,11 +3223,11 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1347 0029 02 .uleb128 0x2 1348 002a 01 .byte 0x1 1349 002b 06 .byte 0x6 - 1350 002c 5E010000 .4byte .LASF0 + 1350 002c 6F010000 .4byte .LASF0 1351 0030 02 .uleb128 0x2 1352 0031 01 .byte 0x1 1353 0032 08 .byte 0x8 - 1354 0033 9F020000 .4byte .LASF1 + 1354 0033 B0020000 .4byte .LASF1 1355 0037 02 .uleb128 0x2 1356 0038 02 .byte 0x2 1357 0039 05 .byte 0x5 @@ -3235,10 +3235,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1359 003e 02 .uleb128 0x2 1360 003f 02 .byte 0x2 1361 0040 07 .byte 0x7 - 1362 0041 A9030000 .4byte .LASF3 + 1362 0041 BA030000 .4byte .LASF3 1363 0045 03 .uleb128 0x3 - 1364 0046 CE020000 .4byte .LASF9 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 55 + 1364 0046 DF020000 .4byte .LASF9 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 55 1365 004a 02 .byte 0x2 @@ -3247,19 +3247,19 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1368 0050 02 .uleb128 0x2 1369 0051 04 .byte 0x4 1370 0052 05 .byte 0x5 - 1371 0053 88030000 .4byte .LASF4 + 1371 0053 99030000 .4byte .LASF4 1372 0057 02 .uleb128 0x2 1373 0058 04 .byte 0x4 1374 0059 07 .byte 0x7 - 1375 005a 16040000 .4byte .LASF5 + 1375 005a 27040000 .4byte .LASF5 1376 005e 02 .uleb128 0x2 1377 005f 08 .byte 0x8 1378 0060 05 .byte 0x5 - 1379 0061 70010000 .4byte .LASF6 + 1379 0061 81010000 .4byte .LASF6 1380 0065 02 .uleb128 0x2 1381 0066 08 .byte 0x8 1382 0067 07 .byte 0x7 - 1383 0068 D6020000 .4byte .LASF7 + 1383 0068 E7020000 .4byte .LASF7 1384 006c 04 .uleb128 0x4 1385 006d 04 .byte 0x4 1386 006e 05 .byte 0x5 @@ -3267,44 +3267,44 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1388 0073 02 .uleb128 0x2 1389 0074 04 .byte 0x4 1390 0075 07 .byte 0x7 - 1391 0076 A9040000 .4byte .LASF8 + 1391 0076 BA040000 .4byte .LASF8 1392 007a 03 .uleb128 0x3 - 1393 007b 33010000 .4byte .LASF10 + 1393 007b 44010000 .4byte .LASF10 1394 007f 03 .byte 0x3 1395 0080 5B .byte 0x5b 1396 0081 30000000 .4byte 0x30 1397 0085 03 .uleb128 0x3 - 1398 0086 0B010000 .4byte .LASF11 + 1398 0086 EB000000 .4byte .LASF11 1399 008a 03 .byte 0x3 1400 008b 5C .byte 0x5c 1401 008c 3E000000 .4byte 0x3e 1402 0090 03 .uleb128 0x3 - 1403 0091 0A040000 .4byte .LASF12 + 1403 0091 1B040000 .4byte .LASF12 1404 0095 03 .byte 0x3 1405 0096 5D .byte 0x5d 1406 0097 57000000 .4byte 0x57 1407 009b 02 .uleb128 0x2 1408 009c 04 .byte 0x4 1409 009d 04 .byte 0x4 - 1410 009e 6A010000 .4byte .LASF13 + 1410 009e 7B010000 .4byte .LASF13 1411 00a2 02 .uleb128 0x2 1412 00a3 08 .byte 0x8 1413 00a4 04 .byte 0x4 - 1414 00a5 30040000 .4byte .LASF14 + 1414 00a5 41040000 .4byte .LASF14 1415 00a9 02 .uleb128 0x2 1416 00aa 01 .byte 0x1 1417 00ab 08 .byte 0x8 - 1418 00ac 85010000 .4byte .LASF15 + 1418 00ac 96010000 .4byte .LASF15 1419 00b0 03 .uleb128 0x3 - 1420 00b1 0D030000 .4byte .LASF16 + 1420 00b1 1E030000 .4byte .LASF16 1421 00b5 03 .byte 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 56 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 56 1422 00b6 E8 .byte 0xe8 1423 00b7 57000000 .4byte 0x57 1424 00bb 03 .uleb128 0x3 - 1425 00bc 11040000 .4byte .LASF17 + 1425 00bc 22040000 .4byte .LASF17 1426 00c0 03 .byte 0x3 1427 00c1 F0 .byte 0xf0 1428 00c2 C6000000 .4byte 0xc6 @@ -3316,7 +3316,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1434 00ce 15 .byte 0x15 1435 00cf FE000000 .4byte 0xfe 1436 00d3 07 .uleb128 0x7 - 1437 00d4 CC030000 .4byte .LASF18 + 1437 00d4 DD030000 .4byte .LASF18 1438 00d8 04 .byte 0x4 1439 00d9 17 .byte 0x17 1440 00da 90000000 .4byte 0x90 @@ -3324,7 +3324,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1442 00df 23 .byte 0x23 1443 00e0 00 .uleb128 0 1444 00e1 07 .uleb128 0x7 - 1445 00e2 93040000 .4byte .LASF19 + 1445 00e2 A4040000 .4byte .LASF19 1446 00e6 04 .byte 0x4 1447 00e7 18 .byte 0x18 1448 00e8 7A000000 .4byte 0x7a @@ -3332,7 +3332,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1450 00ed 23 .byte 0x23 1451 00ee 04 .uleb128 0x4 1452 00ef 07 .uleb128 0x7 - 1453 00f0 4C010000 .4byte .LASF20 + 1453 00f0 5D010000 .4byte .LASF20 1454 00f4 04 .byte 0x4 1455 00f5 19 .byte 0x19 1456 00f6 FE000000 .4byte 0xfe @@ -3352,13 +3352,13 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1470 0110 07 .byte 0x7 1471 0111 7E000000 .4byte .LASF21 1472 0115 03 .uleb128 0x3 - 1473 0116 8A040000 .4byte .LASF22 + 1473 0116 9B040000 .4byte .LASF22 1474 011a 04 .byte 0x4 1475 011b 1B .byte 0x1b 1476 011c CB000000 .4byte 0xcb 1477 0120 0A .uleb128 0xa 1478 0121 04 .byte 0x4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 57 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 57 1479 0122 0B .uleb128 0xb @@ -3366,7 +3366,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1481 0124 28010000 .4byte 0x128 1482 0128 0C .uleb128 0xc 1483 0129 0D .uleb128 0xd - 1484 012a 8A010000 .4byte .LASF25 + 1484 012a 9B010000 .4byte .LASF25 1485 012e 01 .byte 0x1 1486 012f E0 .byte 0xe0 1487 0130 01 .byte 0x1 @@ -3374,12 +3374,12 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1489 0135 01 .byte 0x1 1490 0136 5C010000 .4byte 0x15c 1491 013a 0E .uleb128 0xe - 1492 013b 99020000 .4byte .LASF23 + 1492 013b AA020000 .4byte .LASF23 1493 013f 01 .byte 0x1 1494 0140 E0 .byte 0xe0 1495 0141 90000000 .4byte 0x90 1496 0145 0E .uleb128 0xe - 1497 0146 43040000 .4byte .LASF24 + 1497 0146 54040000 .4byte .LASF24 1498 014a 01 .byte 0x1 1499 014b E0 .byte 0xe0 1500 014c 90000000 .4byte 0x90 @@ -3390,7 +3390,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1505 0157 7A000000 .4byte 0x7a 1506 015b 00 .byte 0 1507 015c 10 .uleb128 0x10 - 1508 015d 9A030000 .4byte .LASF26 + 1508 015d AB030000 .4byte .LASF26 1509 0161 01 .byte 0x1 1510 0162 5E05 .2byte 0x55e 1511 0164 01 .byte 0x1 @@ -3398,7 +3398,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1513 0169 01 .byte 0x1 1514 016a AB010000 .4byte 0x1ab 1515 016e 11 .uleb128 0x11 - 1516 016f C5040000 .4byte .LASF27 + 1516 016f D6040000 .4byte .LASF27 1517 0173 01 .byte 0x1 1518 0174 5E05 .2byte 0x55e 1519 0176 7A000000 .4byte 0x7a @@ -3408,17 +3408,17 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1523 0180 5E05 .2byte 0x55e 1524 0182 7A000000 .4byte 0x7a 1525 0186 12 .uleb128 0x12 - 1526 0187 70020000 .4byte .LASF29 + 1526 0187 81020000 .4byte .LASF29 1527 018b 01 .byte 0x1 1528 018c 6005 .2byte 0x560 1529 018e 90000000 .4byte 0x90 1530 0192 12 .uleb128 0x12 - 1531 0193 42030000 .4byte .LASF30 + 1531 0193 53030000 .4byte .LASF30 1532 0197 01 .byte 0x1 1533 0198 6105 .2byte 0x561 1534 019a 7A000000 .4byte 0x7a 1535 019e 12 .uleb128 0x12 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 58 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 58 1536 019f 1B000000 .4byte .LASF31 @@ -3427,7 +3427,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1539 01a6 90000000 .4byte 0x90 1540 01aa 00 .byte 0 1541 01ab 10 .uleb128 0x10 - 1542 01ac 1B010000 .4byte .LASF32 + 1542 01ac FB000000 .4byte .LASF32 1543 01b0 01 .byte 0x1 1544 01b1 F501 .2byte 0x1f5 1545 01b3 01 .byte 0x1 @@ -3455,20 +3455,20 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1567 01e7 FE01 .2byte 0x1fe 1568 01e9 7A000000 .4byte 0x7a 1569 01ed 12 .uleb128 0x12 - 1570 01ee CB010000 .4byte .LASF34 + 1570 01ee DC010000 .4byte .LASF34 1571 01f2 01 .byte 0x1 1572 01f3 FF01 .2byte 0x1ff 1573 01f5 7A000000 .4byte 0x7a 1574 01f9 14 .uleb128 0x14 1575 01fa 12 .uleb128 0x12 - 1576 01fb AF010000 .4byte .LASF35 + 1576 01fb C0010000 .4byte .LASF35 1577 01ff 01 .byte 0x1 1578 0200 1902 .2byte 0x219 1579 0202 7A000000 .4byte 0x7a 1580 0206 00 .byte 0 1581 0207 00 .byte 0 1582 0208 15 .uleb128 0x15 - 1583 0209 16030000 .4byte .LASF42 + 1583 0209 27030000 .4byte .LASF42 1584 020d 01 .byte 0x1 1585 020e D601 .2byte 0x1d6 1586 0210 01 .byte 0x1 @@ -3478,7 +3478,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1590 021a 7D .byte 0x7d 1591 021b 00 .sleb128 0 1592 021c 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 59 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 59 1593 021d 30020000 .4byte 0x230 @@ -3538,7 +3538,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1647 02b1 1B .uleb128 0x1b 1648 02b2 28000000 .4byte .LBB3 1649 02b6 3C000000 .4byte .LBE3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 60 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 60 1650 02ba C8020000 .4byte 0x2c8 @@ -3587,7 +3587,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1693 030f 00 .byte 0 1694 0310 00 .byte 0 1695 0311 0D .uleb128 0xd - 1696 0312 2C030000 .4byte .LASF36 + 1696 0312 3D030000 .4byte .LASF36 1697 0316 01 .byte 0x1 1698 0317 6E .byte 0x6e 1699 0318 01 .byte 0x1 @@ -3595,15 +3595,15 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1701 031d 01 .byte 0x1 1702 031e 44030000 .4byte 0x344 1703 0322 0E .uleb128 0xe - 1704 0323 EC030000 .4byte .LASF37 + 1704 0323 FD030000 .4byte .LASF37 1705 0327 01 .byte 0x1 1706 0328 6E .byte 0x6e - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 61 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 61 1707 0329 44030000 .4byte 0x344 1708 032d 0E .uleb128 0xe - 1709 032e 43040000 .4byte .LASF24 + 1709 032e 54040000 .4byte .LASF24 1710 0332 01 .byte 0x1 1711 0333 6E .byte 0x6e 1712 0334 85000000 .4byte 0x85 @@ -3619,7 +3619,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1722 034a 1F .uleb128 0x1f 1723 034b 7A000000 .4byte 0x7a 1724 034f 0D .uleb128 0xd - 1725 0350 67030000 .4byte .LASF38 + 1725 0350 78030000 .4byte .LASF38 1726 0354 01 .byte 0x1 1727 0355 BD .byte 0xbd 1728 0356 01 .byte 0x1 @@ -3627,12 +3627,12 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1730 035b 01 .byte 0x1 1731 035c 82030000 .4byte 0x382 1732 0360 0E .uleb128 0xe - 1733 0361 99020000 .4byte .LASF23 + 1733 0361 AA020000 .4byte .LASF23 1734 0365 01 .byte 0x1 1735 0366 BD .byte 0xbd 1736 0367 90000000 .4byte 0x90 1737 036b 0E .uleb128 0xe - 1738 036c 43040000 .4byte .LASF24 + 1738 036c 54040000 .4byte .LASF24 1739 0370 01 .byte 0x1 1740 0371 BD .byte 0xbd 1741 0372 90000000 .4byte 0x90 @@ -3651,25 +3651,25 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1754 038f 01 .byte 0x1 1755 0390 C5030000 .4byte 0x3c5 1756 0394 11 .uleb128 0x11 - 1757 0395 4C030000 .4byte .LASF40 + 1757 0395 5D030000 .4byte .LASF40 1758 0399 01 .byte 0x1 1759 039a 0005 .2byte 0x500 1760 039c 7A000000 .4byte 0x7a 1761 03a0 11 .uleb128 0x11 - 1762 03a1 EC030000 .4byte .LASF37 + 1762 03a1 FD030000 .4byte .LASF37 1763 03a5 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 62 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 62 1764 03a6 0005 .2byte 0x500 1765 03a8 C5030000 .4byte 0x3c5 1766 03ac 11 .uleb128 0x11 - 1767 03ad 43040000 .4byte .LASF24 + 1767 03ad 54040000 .4byte .LASF24 1768 03b1 01 .byte 0x1 1769 03b2 0005 .2byte 0x500 1770 03b4 85000000 .4byte 0x85 1771 03b8 12 .uleb128 0x12 - 1772 03b9 12010000 .4byte .LASF41 + 1772 03b9 F2000000 .4byte .LASF41 1773 03bd 01 .byte 0x1 1774 03be 0305 .2byte 0x503 1775 03c0 85000000 .4byte 0x85 @@ -3678,7 +3678,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1778 03c6 04 .byte 0x4 1779 03c7 7A000000 .4byte 0x7a 1780 03cb 20 .uleb128 0x20 - 1781 03cc DA010000 .4byte .LASF43 + 1781 03cc EB010000 .4byte .LASF43 1782 03d0 01 .byte 0x1 1783 03d1 6202 .2byte 0x262 1784 03d3 01 .byte 0x1 @@ -3688,13 +3688,13 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1788 03e0 01 .byte 0x1 1789 03e1 F3070000 .4byte 0x7f3 1790 03e5 21 .uleb128 0x21 - 1791 03e6 BC030000 .4byte .LASF45 + 1791 03e6 CD030000 .4byte .LASF45 1792 03ea 01 .byte 0x1 1793 03eb 6202 .2byte 0x262 1794 03ed 7A000000 .4byte 0x7a 1795 03f1 B4020000 .4byte .LLST12 1796 03f5 22 .uleb128 0x22 - 1797 03f6 C0010000 .4byte .LASF46 + 1797 03f6 D1010000 .4byte .LASF46 1798 03fa 01 .byte 0x1 1799 03fb 6402 .2byte 0x264 1800 03fd 85000000 .4byte 0x85 @@ -3702,7 +3702,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1802 0402 91 .byte 0x91 1803 0403 DC78 .sleb128 -932 1804 0405 23 .uleb128 0x23 - 1805 0406 C4030000 .4byte .LASF47 + 1805 0406 D5030000 .4byte .LASF47 1806 040a 01 .byte 0x1 1807 040b 6502 .2byte 0x265 1808 040d 85000000 .4byte 0x85 @@ -3714,16 +3714,16 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1814 041d 7A000000 .4byte 0x7a 1815 0421 60030000 .4byte .LLST14 1816 0425 23 .uleb128 0x23 - 1817 0426 ED020000 .4byte .LASF49 + 1817 0426 FE020000 .4byte .LASF49 1818 042a 01 .byte 0x1 1819 042b 6702 .2byte 0x267 1820 042d 85000000 .4byte 0x85 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 63 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 63 1821 0431 1A040000 .4byte .LLST15 1822 0435 23 .uleb128 0x23 - 1823 0436 91030000 .4byte .LASF50 + 1823 0436 A2030000 .4byte .LASF50 1824 043a 01 .byte 0x1 1825 043b 6802 .2byte 0x268 1826 043d B0000000 .4byte 0xb0 @@ -3741,25 +3741,25 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1838 045d 85000000 .4byte 0x85 1839 0461 6E080000 .4byte .LLST18 1840 0465 23 .uleb128 0x23 - 1841 0466 79020000 .4byte .LASF53 + 1841 0466 8A020000 .4byte .LASF53 1842 046a 01 .byte 0x1 1843 046b 6B02 .2byte 0x26b 1844 046d 7A000000 .4byte 0x7a 1845 0471 17090000 .4byte .LLST19 1846 0475 23 .uleb128 0x23 - 1847 0476 60020000 .4byte .LASF54 + 1847 0476 71020000 .4byte .LASF54 1848 047a 01 .byte 0x1 1849 047b 6E02 .2byte 0x26e 1850 047d 7A000000 .4byte 0x7a 1851 0481 4C090000 .4byte .LLST20 1852 0485 23 .uleb128 0x23 - 1853 0486 E6010000 .4byte .LASF55 + 1853 0486 F7010000 .4byte .LASF55 1854 048a 01 .byte 0x1 1855 048b 7102 .2byte 0x271 1856 048d 7A000000 .4byte 0x7a 1857 0491 98090000 .4byte .LLST21 1858 0495 22 .uleb128 0x22 - 1859 0496 5A030000 .4byte .LASF56 + 1859 0496 6B030000 .4byte .LASF56 1860 049a 01 .byte 0x1 1861 049b 7302 .2byte 0x273 1862 049d F3070000 .4byte 0x7f3 @@ -3767,7 +3767,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1864 04a2 91 .byte 0x91 1865 04a3 807B .sleb128 -640 1866 04a5 22 .uleb128 0x22 - 1867 04a6 AD020000 .4byte .LASF57 + 1867 04a6 BE020000 .4byte .LASF57 1868 04aa 01 .byte 0x1 1869 04ab 7402 .2byte 0x274 1870 04ad F3070000 .4byte 0x7f3 @@ -3778,7 +3778,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1875 04b6 11030000 .4byte 0x311 1876 04ba 8E000000 .4byte .LBB20 1877 04be A2000000 .4byte .LBE20 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 64 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 64 1878 04c2 01 .byte 0x1 @@ -3823,7 +3823,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1917 052b 44020000 .4byte .LBE24 1918 052f 89050000 .4byte 0x589 1919 0533 22 .uleb128 0x22 - 1920 0534 84040000 .4byte .LASF60 + 1920 0534 95040000 .4byte .LASF60 1921 0538 01 .byte 0x1 1922 0539 9403 .2byte 0x394 1923 053b 04080000 .4byte 0x804 @@ -3838,7 +3838,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1932 0551 01 .byte 0x1 1933 0552 52 .byte 0x52 1934 0553 03 .byte 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 65 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 65 1935 0554 0A .byte 0xa @@ -3898,26 +3898,26 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 1989 05a4 E078 .sleb128 -928 1990 05a6 00 .byte 0 1991 05a7 1B .uleb128 0x1b - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 66 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 66 1992 05a8 A2020000 .4byte .LBB26 1993 05ac 26030000 .4byte .LBE26 1994 05b0 6F060000 .4byte 0x66f 1995 05b4 23 .uleb128 0x23 - 1996 05b5 53030000 .4byte .LASF62 + 1996 05b5 64030000 .4byte .LASF62 1997 05b9 01 .byte 0x1 1998 05ba 8104 .2byte 0x481 1999 05bc 85000000 .4byte 0x85 2000 05c0 B10B0000 .4byte .LLST27 2001 05c4 23 .uleb128 0x23 - 2002 05c5 28040000 .4byte .LASF63 + 2002 05c5 39040000 .4byte .LASF63 2003 05c9 01 .byte 0x1 2004 05ca 8604 .2byte 0x486 2005 05cc 90000000 .4byte 0x90 2006 05d0 1D0C0000 .4byte .LLST28 2007 05d4 23 .uleb128 0x23 - 2008 05d5 12010000 .4byte .LASF41 + 2008 05d5 F2000000 .4byte .LASF41 2009 05d9 01 .byte 0x1 2010 05da 8704 .2byte 0x487 2011 05dc 7A000000 .4byte 0x7a @@ -3958,7 +3958,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 2046 0640 340D0000 .4byte .LLST34 2047 0644 25 .uleb128 0x25 2048 0645 D8020000 .4byte .LBB30 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 67 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 67 2049 0649 E4020000 .4byte .LBE30 @@ -3971,7 +3971,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 2056 0659 EA020000 .4byte .LBB31 2057 065d 00030000 .4byte .LBE31 2058 0661 12 .uleb128 0x12 - 2059 0662 B7010000 .4byte .LASF64 + 2059 0662 C8010000 .4byte .LASF64 2060 0666 01 .byte 0x1 2061 0667 AA04 .2byte 0x4aa 2062 0669 85000000 .4byte 0x85 @@ -4018,7 +4018,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 2103 06ae 03 .byte 0x3 2104 06af 91 .byte 0x91 2105 06b0 877B .sleb128 -633 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 68 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 68 2106 06b2 1D .uleb128 0x1d @@ -4078,7 +4078,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 2160 0702 00 .sleb128 0 2161 0703 1D .uleb128 0x1d 2162 0704 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 69 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 69 2163 0705 51 .byte 0x51 @@ -4138,7 +4138,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 2217 0778 0C05 .2byte 0x50c 2218 077a A4070000 .4byte 0x7a4 2219 077e 18 .uleb128 0x18 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 70 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 70 2220 077f 2D030000 .4byte 0x32d @@ -4198,7 +4198,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 2274 07e1 DC78 .sleb128 -932 2275 07e3 1D .uleb128 0x1d 2276 07e4 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 71 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 71 2277 07e5 51 .byte 0x51 @@ -4228,14 +4228,14 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 2301 0812 1F01 .2byte 0x11f 2302 0814 00 .byte 0 2303 0815 2B .uleb128 0x2b - 2304 0816 84020000 .4byte .LASF95 + 2304 0816 95020000 .4byte .LASF95 2305 081a 01 .byte 0x1 2306 081b 8901 .2byte 0x189 2307 081d 01 .byte 0x1 2308 081e 01 .byte 0x1 2309 081f 2C .uleb128 0x2c 2310 0820 01 .byte 0x1 - 2311 0821 43010000 .4byte .LASF67 + 2311 0821 54010000 .4byte .LASF67 2312 0825 01 .byte 0x1 2313 0826 1001 .2byte 0x110 2314 0828 01 .byte 0x1 @@ -4245,7 +4245,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 2318 0835 01 .byte 0x1 2319 0836 41090000 .4byte 0x941 2320 083a 23 .uleb128 0x23 - 2321 083b CB010000 .4byte .LASF34 + 2321 083b DC010000 .4byte .LASF34 2322 083f 01 .byte 0x1 2323 0840 1301 .2byte 0x113 2324 0842 7A000000 .4byte 0x7a @@ -4258,7 +4258,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 2331 0856 03 .byte 0x3 2332 0857 91 .byte 0x91 2333 0858 D87D .sleb128 -296 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 72 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 72 2334 085a 23 .uleb128 0x23 @@ -4318,7 +4318,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 2388 08e4 EF080000 .4byte 0x8ef 2389 08e8 1D .uleb128 0x1d 2390 08e9 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 73 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 73 2391 08ea 50 .byte 0x50 @@ -4371,14 +4371,14 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 2438 0940 00 .byte 0 2439 0941 2C .uleb128 0x2c 2440 0942 01 .byte 0x1 - 2441 0943 F9020000 .4byte .LASF68 + 2441 0943 0A030000 .4byte .LASF68 2442 0947 01 .byte 0x1 2443 0948 A301 .2byte 0x1a3 2444 094a 01 .byte 0x1 2445 094b 00000000 .4byte .LFB61 2446 094f 30000000 .4byte .LFE61 2447 0953 CC0E0000 .4byte .LLST46 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 74 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 74 2448 0957 01 .byte 0x1 @@ -4410,7 +4410,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 2474 098c 00 .byte 0 2475 098d 2C .uleb128 0x2c 2476 098e 01 .byte 0x1 - 2477 098f CF040000 .4byte .LASF69 + 2477 098f E0040000 .4byte .LASF69 2478 0993 01 .byte 0x1 2479 0994 2905 .2byte 0x529 2480 0996 01 .byte 0x1 @@ -4420,25 +4420,25 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 2484 09a3 01 .byte 0x1 2485 09a4 480A0000 .4byte 0xa48 2486 09a8 21 .uleb128 0x21 - 2487 09a9 A7010000 .4byte .LASF70 + 2487 09a9 B8010000 .4byte .LASF70 2488 09ad 01 .byte 0x1 2489 09ae 2905 .2byte 0x529 2490 09b0 90000000 .4byte 0x90 2491 09b4 190F0000 .4byte .LLST48 2492 09b8 21 .uleb128 0x21 - 2493 09b9 03010000 .4byte .LASF71 + 2493 09b9 E3000000 .4byte .LASF71 2494 09bd 01 .byte 0x1 2495 09be 2905 .2byte 0x529 2496 09c0 7A000000 .4byte 0x7a 2497 09c4 3A0F0000 .4byte .LLST49 2498 09c8 23 .uleb128 0x23 - 2499 09c9 9F010000 .4byte .LASF72 + 2499 09c9 B0010000 .4byte .LASF72 2500 09cd 01 .byte 0x1 2501 09ce 2B05 .2byte 0x52b 2502 09d0 90000000 .4byte 0x90 2503 09d4 190F0000 .4byte .LLST48 2504 09d8 22 .uleb128 0x22 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 75 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 75 2505 09d9 55000000 .4byte .LASF73 @@ -4449,14 +4449,14 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 2510 09e5 91 .byte 0x91 2511 09e6 F07D .sleb128 -272 2512 09e8 22 .uleb128 0x22 - 2513 09e9 7C040000 .4byte .LASF74 + 2513 09e9 8D040000 .4byte .LASF74 2514 09ed 01 .byte 0x1 2515 09ee 2F05 .2byte 0x52f 2516 09f0 7A000000 .4byte 0x7a 2517 09f4 01 .byte 0x1 2518 09f5 54 .byte 0x54 2519 09f6 23 .uleb128 0x23 - 2520 09f7 53030000 .4byte .LASF62 + 2520 09f7 64030000 .4byte .LASF62 2521 09fb 01 .byte 0x1 2522 09fc 3205 .2byte 0x532 2523 09fe 85000000 .4byte 0x85 @@ -4498,7 +4498,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 2559 0a3f 25 .byte 0x25 2560 0a40 1D .uleb128 0x1d 2561 0a41 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 76 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 76 2562 0a42 50 .byte 0x50 @@ -4515,7 +4515,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 2573 0a56 FF .byte 0xff 2574 0a57 00 .byte 0 2575 0a58 2F .uleb128 0x2f - 2576 0a59 37040000 .4byte .LASF76 + 2576 0a59 48040000 .4byte .LASF76 2577 0a5d 01 .byte 0x1 2578 0a5e 26 .byte 0x26 2579 0a5f 4A030000 .4byte 0x34a @@ -4524,7 +4524,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 2582 0a65 03 .byte 0x3 2583 0a66 00000000 .4byte BL_Checksum 2584 0a6a 2F .uleb128 0x2f - 2585 0a6b 5B040000 .4byte .LASF77 + 2585 0a6b 6C040000 .4byte .LASF77 2586 0a6f 01 .byte 0x1 2587 0a70 27 .byte 0x27 2588 0a71 44030000 .4byte 0x344 @@ -4533,7 +4533,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 2591 0a77 03 .byte 0x3 2592 0a78 00000000 .4byte BL_ChecksumAccess 2593 0a7c 2F .uleb128 0x2f - 2594 0a7d 7B030000 .4byte .LASF78 + 2594 0a7d 8C030000 .4byte .LASF78 2595 0a81 01 .byte 0x1 2596 0a82 2F .byte 0x2f 2597 0a83 8E0A0000 .4byte 0xa8e @@ -4556,9 +4556,9 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 2614 0aa6 04 .byte 0x4 2615 0aa7 8E0A0000 .4byte 0xa8e 2616 0aab 30 .uleb128 0x30 - 2617 0aac 9C040000 .4byte .LASF80 + 2617 0aac AD040000 .4byte .LASF80 2618 0ab0 05 .byte 0x5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 77 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 77 2619 0ab1 1606 .2byte 0x616 @@ -4569,7 +4569,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 2624 0aba 45000000 .4byte 0x45 2625 0abe 31 .uleb128 0x31 2626 0abf 01 .byte 0x1 - 2627 0ac0 7E010000 .4byte .LASF81 + 2627 0ac0 8F010000 .4byte .LASF81 2628 0ac4 01 .byte 0x1 2629 0ac5 20010000 .4byte 0x120 2630 0ac9 01 .byte 0x1 @@ -4584,7 +4584,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 2639 0ade 00 .byte 0 2640 0adf 33 .uleb128 0x33 2641 0ae0 01 .byte 0x1 - 2642 0ae1 B6040000 .4byte .LASF85 + 2642 0ae1 C7040000 .4byte .LASF85 2643 0ae5 06 .byte 0x6 2644 0ae6 42 .byte 0x42 2645 0ae7 01 .byte 0x1 @@ -4617,8 +4617,8 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 2672 0b26 00 .byte 0 2673 0b27 34 .uleb128 0x34 2674 0b28 01 .byte 0x1 - 2675 0b29 B8020000 .4byte .LASF83 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 78 + 2675 0b29 C9020000 .4byte .LASF83 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 78 2676 0b2d 06 .byte 0x6 @@ -4655,14 +4655,14 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 2707 0b64 85000000 .4byte 0x85 2708 0b68 34 .uleb128 0x34 2709 0b69 01 .byte 0x1 - 2710 0b6a F3030000 .4byte .LASF87 + 2710 0b6a 04040000 .4byte .LASF87 2711 0b6e 08 .byte 0x8 2712 0b6f E3 .byte 0xe3 2713 0b70 01 .byte 0x1 2714 0b71 01 .byte 0x1 2715 0b72 33 .uleb128 0x33 2716 0b73 01 .byte 0x1 - 2717 0b74 D6030000 .4byte .LASF88 + 2717 0b74 E7030000 .4byte .LASF88 2718 0b78 08 .byte 0x8 2719 0b79 E8 .byte 0xe8 2720 0b7a 01 .byte 0x1 @@ -4678,12 +4678,12 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 2730 0b93 32 .uleb128 0x32 2731 0b94 7A000000 .4byte 0x7a 2732 0b98 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 79 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 79 2733 0b99 35 .uleb128 0x35 2734 0b9a 01 .byte 0x1 - 2735 0b9b 39010000 .4byte .LASF96 + 2735 0b9b 4A010000 .4byte .LASF96 2736 0b9f 06 .byte 0x6 2737 0ba0 40 .byte 0x40 2738 0ba1 01 .byte 0x1 @@ -4691,7 +4691,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 2740 0ba6 01 .byte 0x1 2741 0ba7 36 .uleb128 0x36 2742 0ba8 01 .byte 0x1 - 2743 0ba9 C7020000 .4byte .LASF89 + 2743 0ba9 D8020000 .4byte .LASF89 2744 0bad 07 .byte 0x7 2745 0bae 80 .byte 0x80 2746 0baf 01 .byte 0x1 @@ -4702,7 +4702,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 2751 0bba 00 .byte 0 2752 0bbb 33 .uleb128 0x33 2753 0bbc 01 .byte 0x1 - 2754 0bbd 48040000 .4byte .LASF90 + 2754 0bbd 59040000 .4byte .LASF90 2755 0bc1 06 .byte 0x6 2756 0bc2 41 .byte 0x41 2757 0bc3 01 .byte 0x1 @@ -4714,7 +4714,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 2763 0bd2 00 .byte 0 2764 0bd3 37 .uleb128 0x37 2765 0bd4 01 .byte 0x1 - 2766 0bd5 6D040000 .4byte .LASF91 + 2766 0bd5 7E040000 .4byte .LASF91 2767 0bd9 06 .byte 0x6 2768 0bda 44 .byte 0x44 2769 0bdb 01 .byte 0x1 @@ -4738,7 +4738,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 2787 0005 13 .uleb128 0x13 2788 0006 0B .uleb128 0xb 2789 0007 03 .uleb128 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 80 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 80 2790 0008 0E .uleb128 0xe @@ -4798,7 +4798,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 2844 003e 00 .byte 0 2845 003f 06 .uleb128 0x6 2846 0040 13 .uleb128 0x13 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 81 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 81 2847 0041 01 .byte 0x1 @@ -4858,7 +4858,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 2901 0077 0B .uleb128 0xb 2902 0078 0B .uleb128 0xb 2903 0079 49 .uleb128 0x49 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 82 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 82 2904 007a 13 .uleb128 0x13 @@ -4918,7 +4918,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 2958 00b0 2E .uleb128 0x2e 2959 00b1 01 .byte 0x1 2960 00b2 03 .uleb128 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 83 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 83 2961 00b3 0E .uleb128 0xe @@ -4978,7 +4978,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 3015 00e9 14 .uleb128 0x14 3016 00ea 0B .uleb128 0xb 3017 00eb 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 84 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 84 3018 00ec 00 .byte 0 @@ -5038,7 +5038,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 3072 0124 13 .uleb128 0x13 3073 0125 00 .byte 0 3074 0126 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 85 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 85 3075 0127 18 .uleb128 0x18 @@ -5098,7 +5098,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 3129 0161 9142 .uleb128 0x2111 3130 0163 0A .uleb128 0xa 3131 0164 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 86 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 86 3132 0165 00 .byte 0 @@ -5158,7 +5158,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 3186 019e 00 .byte 0 3187 019f 22 .uleb128 0x22 3188 01a0 34 .uleb128 0x34 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 87 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 87 3189 01a1 00 .byte 0 @@ -5218,7 +5218,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 3243 01d7 26 .uleb128 0x26 3244 01d8 0B .uleb128 0xb 3245 01d9 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 88 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 88 3246 01da 55 .uleb128 0x55 @@ -5278,7 +5278,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 3300 0212 0B .uleb128 0xb 3301 0213 00 .byte 0 3302 0214 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 89 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 89 3303 0215 2C .uleb128 0x2c @@ -5338,7 +5338,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 3357 024f 03 .uleb128 0x3 3358 0250 0E .uleb128 0xe 3359 0251 3A .uleb128 0x3a - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 90 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 90 3360 0252 0B .uleb128 0xb @@ -5398,7 +5398,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 3414 0288 33 .uleb128 0x33 3415 0289 2E .uleb128 0x2e 3416 028a 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 91 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 91 3417 028b 3F .uleb128 0x3f @@ -5458,7 +5458,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 3471 02c1 36 .uleb128 0x36 3472 02c2 2E .uleb128 0x2e 3473 02c3 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 92 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 92 3474 02c4 3F .uleb128 0x3f @@ -5518,7 +5518,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 3528 0028 0100 .2byte 0x1 3529 002a 50 .byte 0x50 3530 002b 18000000 .4byte .LVL2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 93 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 93 3531 002f 1A000000 .4byte .LVL3 @@ -5578,7 +5578,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 3585 00a8 58000000 .4byte .LVL19 3586 00ac 8C000000 .4byte .LFE69 3587 00b0 0400 .2byte 0x4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 94 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 94 3588 00b2 F3 .byte 0xf3 @@ -5638,7 +5638,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 3642 013b 0100 .2byte 0x1 3643 013d 50 .byte 0x50 3644 013e 58000000 .4byte .LVL19 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 95 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 95 3645 0142 5A000000 .4byte .LVL20 @@ -5698,7 +5698,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 3699 01a4 7D .byte 0x7d 3700 01a5 10 .sleb128 16 3701 01a6 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 96 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 96 3702 01aa 00000000 .4byte 0 @@ -5758,7 +5758,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 3756 0237 54 .byte 0x54 3757 0238 3A000000 .4byte .LVL36 3758 023c 66000000 .4byte .LVL44 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 97 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 97 3759 0240 0100 .2byte 0x1 @@ -5818,7 +5818,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 3813 02bf 0D000000 .4byte .LVL49-1 3814 02c3 84030000 .4byte .LFE64 3815 02c7 0400 .2byte 0x4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 98 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 98 3816 02c9 F3 .byte 0xf3 @@ -5878,7 +5878,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 3870 034a 30 .byte 0x30 3871 034b 9F .byte 0x9f 3872 034c 56030000 .4byte .LVL146 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 99 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 99 3873 0350 66030000 .4byte .LVL148 @@ -5938,7 +5938,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 3927 03d5 30 .byte 0x30 3928 03d6 9F .byte 0x9f 3929 03d7 9A020000 .4byte .LVL113 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 100 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 100 3930 03db 20030000 .4byte .LVL131 @@ -5998,7 +5998,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 3984 0445 94 .byte 0x94 3985 0446 01 .byte 0x1 3986 0447 08 .byte 0x8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 101 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 101 3987 0448 FF .byte 0xff @@ -6058,7 +6058,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 4041 048f 38 .byte 0x38 4042 0490 24 .byte 0x24 4043 0491 91 .byte 0x91 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 102 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 102 4044 0492 827B .sleb128 -638 @@ -6118,7 +6118,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 4098 04d4 00 .sleb128 0 4099 04d5 75 .byte 0x75 4100 04d6 00 .sleb128 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 103 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 103 4101 04d7 22 .byte 0x22 @@ -6178,7 +6178,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 4155 0518 08 .byte 0x8 4156 0519 FF .byte 0xff 4157 051a 1A .byte 0x1a - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 104 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 104 4158 051b 21 .byte 0x21 @@ -6238,7 +6238,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 4212 0562 00 .sleb128 0 4213 0563 75 .byte 0x75 4214 0564 00 .sleb128 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 105 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 105 4215 0565 22 .byte 0x22 @@ -6298,7 +6298,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 4269 05ad 38 .byte 0x38 4270 05ae 24 .byte 0x24 4271 05af 91 .byte 0x91 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 106 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 106 4272 05b0 827B .sleb128 -638 @@ -6358,7 +6358,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 4326 05f2 00 .sleb128 0 4327 05f3 75 .byte 0x75 4328 05f4 00 .sleb128 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 107 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 107 4329 05f5 22 .byte 0x22 @@ -6418,7 +6418,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 4383 0636 08 .byte 0x8 4384 0637 FF .byte 0xff 4385 0638 1A .byte 0x1a - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 108 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 108 4386 0639 21 .byte 0x21 @@ -6478,7 +6478,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 4440 067b 22 .byte 0x22 4441 067c 0A .byte 0xa 4442 067d 7C02 .2byte 0x27c - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 109 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 109 4443 067f 1C .byte 0x1c @@ -6538,7 +6538,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 4497 06c6 08 .byte 0x8 4498 06c7 FF .byte 0xff 4499 06c8 1A .byte 0x1a - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 110 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 110 4500 06c9 38 .byte 0x38 @@ -6598,7 +6598,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 4554 070b 08 .byte 0x8 4555 070c FF .byte 0xff 4556 070d 1A .byte 0x1a - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 111 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 111 4557 070e 38 .byte 0x38 @@ -6658,7 +6658,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 4611 074f 21 .byte 0x21 4612 0750 9F .byte 0x9f 4613 0751 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 112 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 112 4614 0755 00000000 .4byte 0 @@ -6718,7 +6718,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 4668 07c5 04020000 .4byte .LVL95 4669 07c9 08020000 .4byte .LVL96 4670 07cd 0300 .2byte 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 113 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 113 4671 07cf 75 .byte 0x75 @@ -6778,7 +6778,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 4725 0839 38 .byte 0x38 4726 083a 24 .byte 0x24 4727 083b 91 .byte 0x91 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 114 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 114 4728 083c 827B .sleb128 -638 @@ -6838,7 +6838,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 4782 08c4 0100 .2byte 0x1 4783 08c6 55 .byte 0x55 4784 08c7 7C020000 .4byte .LVL107 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 115 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 115 4785 08cb 80020000 .4byte .LVL108 @@ -6898,7 +6898,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 4839 0954 0200 .2byte 0x2 4840 0956 30 .byte 0x30 4841 0957 9F .byte 0x9f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 116 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 116 4842 0958 DE000000 .4byte .LVL72 @@ -6958,7 +6958,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 4896 09e5 98000000 .4byte .LVL61 4897 09e9 9E000000 .4byte .LVL64 4898 09ed 0300 .2byte 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 117 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 117 4899 09ef 73 .byte 0x73 @@ -7018,7 +7018,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 4953 0a77 0400 .2byte 0x4 4954 0a79 72 .byte 0x72 4955 0a7a 00 .sleb128 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 118 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 118 4956 0a7b 1F .byte 0x1f @@ -7078,7 +7078,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 5010 0b00 91 .byte 0x91 5011 0b01 847B .sleb128 -636 5012 0b03 76020000 .4byte .LVL105 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 119 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 119 5013 0b07 79020000 .4byte .LVL106-1 @@ -7138,7 +7138,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 5067 0b93 847B .sleb128 -636 5068 0b95 00000000 .4byte 0 5069 0b99 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 120 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 120 5070 .LLST26: @@ -7198,7 +7198,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 5124 0c04 94 .byte 0x94 5125 0c05 01 .byte 0x1 5126 0c06 08 .byte 0x8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 121 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 121 5127 0c07 FF .byte 0xff @@ -7258,7 +7258,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 5181 0c67 857B .sleb128 -635 5182 0c69 94 .byte 0x94 5183 0c6a 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 122 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 122 5184 0c6b 08 .byte 0x8 @@ -7318,7 +7318,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 5238 0ceb BC020000 .4byte .LVL116 5239 0cef 0200 .2byte 0x2 5240 0cf1 40 .byte 0x40 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 123 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 123 5241 0cf2 9F .byte 0x9f @@ -7378,7 +7378,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 5295 0d65 38 .byte 0x38 5296 0d66 24 .byte 0x24 5297 0d67 91 .byte 0x91 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 124 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 124 5298 0d68 857B .sleb128 -635 @@ -7438,7 +7438,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 5352 0ddd 00000000 .4byte 0 5353 .LLST38: 5354 0de1 08010000 .4byte .LVL74 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 125 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 125 5355 0de5 18010000 .4byte .LVL76 @@ -7498,7 +7498,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 5409 0e6e 00 .sleb128 0 5410 0e6f 70 .byte 0x70 5411 0e70 00 .sleb128 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 126 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 126 5412 0e71 1C .byte 0x1c @@ -7558,7 +7558,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 5466 0ef8 02000000 .4byte .LCFI7 5467 0efc 08000000 .4byte .LCFI8 5468 0f00 0200 .2byte 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 127 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 127 5469 0f02 7D .byte 0x7d @@ -7618,7 +7618,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 5523 0f7d 2F000000 .4byte .LVL176-1 5524 0f81 0100 .2byte 0x1 5525 0f83 51 .byte 0x51 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 128 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 128 5526 0f84 2F000000 .4byte .LVL176-1 @@ -7678,7 +7678,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 5580 0014 00000000 .4byte 0 5581 0018 00000000 .4byte .LFB62 5582 001c 02000000 .4byte .LFE62 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 129 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 129 5583 0020 00000000 .4byte .LFB69 @@ -7738,7 +7738,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 5618 .LASF73: 5619 0055 726F7744 .ascii "rowData\000" 5619 61746100 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 130 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 130 5620 .LASF2: @@ -7789,358 +7789,359 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 1 5640 .LASF82: 5641 00dc 6D656D63 .ascii "memcpy\000" 5641 707900 - 5642 .LASF94: - 5643 00e3 573A5C53 .ascii "W:\\SCSI2SD\\USB_Bootloader.cydsn\000" - 5643 43534932 - 5643 53445C55 - 5643 53425F42 - 5643 6F6F746C - 5644 .LASF71: - 5645 0103 72756E54 .ascii "runType\000" - 5645 79706500 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 131 - - - 5646 .LASF11: - 5647 010b 75696E74 .ascii "uint16\000" - 5647 313600 - 5648 .LASF41: - 5649 0112 63686563 .ascii "checksum\000" - 5649 6B73756D - 5649 00 - 5650 .LASF32: - 5651 011b 424C5F56 .ascii "BL_ValidateBootloadable\000" - 5651 616C6964 - 5651 61746542 - 5651 6F6F746C - 5651 6F616461 - 5652 .LASF10: - 5653 0133 75696E74 .ascii "uint8\000" - 5653 3800 - 5654 .LASF96: - 5655 0139 43795365 .ascii "CySetTemp\000" - 5655 7454656D - 5655 7000 - 5656 .LASF67: - 5657 0143 424C5F53 .ascii "BL_Start\000" - 5657 74617274 - 5657 00 - 5658 .LASF20: - 5659 014c 426F6F74 .ascii "BootLoaderVersion\000" - 5659 4C6F6164 - 5659 65725665 - 5659 7273696F - 5659 6E00 - 5660 .LASF0: - 5661 015e 7369676E .ascii "signed char\000" - 5661 65642063 - 5661 68617200 - 5662 .LASF13: - 5663 016a 666C6F61 .ascii "float\000" - 5663 7400 - 5664 .LASF6: - 5665 0170 6C6F6E67 .ascii "long long int\000" - 5665 206C6F6E - 5665 6720696E - 5665 7400 - 5666 .LASF81: - 5667 017e 6D656D73 .ascii "memset\000" - 5667 657400 - 5668 .LASF15: - 5669 0185 63686172 .ascii "char\000" - 5669 00 - 5670 .LASF25: - 5671 018a 424C5F43 .ascii "BL_Calc8BitEepromSum\000" - 5671 616C6338 - 5671 42697445 - 5671 6570726F - 5671 6D53756D - 5672 .LASF72: - 5673 019f 666C7341 .ascii "flsAddr\000" - 5673 64647200 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 132 - - - 5674 .LASF70: - 5675 01a7 61646472 .ascii "address\000" - 5675 65737300 - 5676 .LASF35: - 5677 01af 63757242 .ascii "curByte\000" - 5677 79746500 - 5678 .LASF64: - 5679 01b7 746D7049 .ascii "tmpIndex\000" - 5679 6E646578 - 5679 00 - 5680 .LASF46: - 5681 01c0 6E756D62 .ascii "numberRead\000" - 5681 65725265 - 5681 616400 - 5682 .LASF34: - 5683 01cb 63616C63 .ascii "calcedChecksum\000" - 5683 65644368 - 5683 65636B73 - 5683 756D00 - 5684 .LASF43: - 5685 01da 424C5F48 .ascii "BL_HostLink\000" - 5685 6F73744C - 5685 696E6B00 - 5686 .LASF55: - 5687 01e6 636F6D6D .ascii "communicationState\000" - 5687 756E6963 - 5687 6174696F - 5687 6E537461 - 5687 746500 - 5688 .LASF92: - 5689 01f9 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 5689 4320342E - 5689 372E3320 - 5689 32303133 - 5689 30333132 - 5690 022c 616E6368 .ascii "anch revision 196615]\000" - 5690 20726576 - 5690 6973696F - 5690 6E203139 - 5690 36363135 - 5691 .LASF93: - 5692 0242 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\BL.c\000" - 5692 6E657261 - 5692 7465645F - 5692 536F7572 - 5692 63655C50 - 5693 .LASF54: - 5694 0260 636C6561 .ascii "clearedMetaData\000" - 5694 7265644D - 5694 65746144 - 5694 61746100 - 5695 .LASF29: - 5696 0270 6669656C .ascii "fieldPtr\000" - 5696 64507472 - 5696 00 - 5697 .LASF53: - 5698 0279 74696D65 .ascii "timeOutCnt\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 133 - - - 5698 4F757443 - 5698 6E7400 - 5699 .LASF95: - 5700 0284 424C5F4C .ascii "BL_LaunchApplication\000" - 5700 61756E63 - 5700 68417070 - 5700 6C696361 - 5700 74696F6E - 5701 .LASF23: - 5702 0299 73746172 .ascii "start\000" - 5702 7400 - 5703 .LASF1: - 5704 029f 756E7369 .ascii "unsigned char\000" - 5704 676E6564 - 5704 20636861 - 5704 7200 - 5705 .LASF57: - 5706 02ad 64617461 .ascii "dataBuffer\000" - 5706 42756666 - 5706 657200 - 5707 .LASF83: - 5708 02b8 43794545 .ascii "CyEEPROM_Start\000" - 5708 50524F4D - 5708 5F537461 - 5708 727400 - 5709 .LASF89: - 5710 02c7 43794861 .ascii "CyHalt\000" - 5710 6C7400 - 5711 .LASF9: - 5712 02ce 696E7433 .ascii "int32_t\000" - 5712 325F7400 - 5713 .LASF7: - 5714 02d6 6C6F6E67 .ascii "long long unsigned int\000" - 5714 206C6F6E - 5714 6720756E - 5714 7369676E - 5714 65642069 - 5715 .LASF49: - 5716 02ed 706B7443 .ascii "pktChecksum\000" - 5716 6865636B - 5716 73756D00 - 5717 .LASF68: - 5718 02f9 43794274 .ascii "CyBtldr_CheckLaunch\000" - 5718 6C64725F - 5718 43686563 - 5718 6B4C6175 - 5718 6E636800 - 5719 .LASF16: - 5720 030d 63797374 .ascii "cystatus\000" - 5720 61747573 - 5720 00 - 5721 .LASF42: - 5722 0316 424C5F4C .ascii "BL_LaunchBootloadable\000" - 5722 61756E63 - 5722 68426F6F - 5722 746C6F61 - 5722 6461626C - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 134 - - - 5723 .LASF36: - 5724 032c 424C5F43 .ascii "BL_CalcPacketChecksum\000" - 5724 616C6350 - 5724 61636B65 - 5724 74436865 - 5724 636B7375 - 5725 .LASF30: - 5726 0342 6669656C .ascii "fieldSize\000" - 5726 6453697A - 5726 6500 - 5727 .LASF40: - 5728 034c 73746174 .ascii "status\000" - 5728 757300 - 5729 .LASF62: - 5730 0353 726F774E .ascii "rowNum\000" - 5730 756D00 - 5731 .LASF56: - 5732 035a 7061636B .ascii "packetBuffer\000" - 5732 65744275 - 5732 66666572 - 5732 00 - 5733 .LASF38: - 5734 0367 424C5F43 .ascii "BL_Calc8BitFlashSum\000" - 5734 616C6338 - 5734 42697446 - 5734 6C617368 - 5734 53756D00 - 5735 .LASF78: - 5736 037b 424C5F53 .ascii "BL_SizeBytes\000" - 5736 697A6542 - 5736 79746573 - 5736 00 - 5737 .LASF4: - 5738 0388 6C6F6E67 .ascii "long int\000" - 5738 20696E74 - 5738 00 - 5739 .LASF50: - 5740 0391 72656164 .ascii "readStat\000" - 5740 53746174 - 5740 00 - 5741 .LASF26: - 5742 039a 424C5F47 .ascii "BL_GetMetadata\000" - 5742 65744D65 - 5742 74616461 - 5742 746100 - 5743 .LASF3: - 5744 03a9 73686F72 .ascii "short unsigned int\000" - 5744 7420756E - 5744 7369676E - 5744 65642069 - 5744 6E7400 - 5745 .LASF45: - 5746 03bc 74696D65 .ascii "timeOut\000" - 5746 4F757400 - 5747 .LASF47: - 5748 03c4 72737053 .ascii "rspSize\000" - 5748 697A6500 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 135 - - - 5749 .LASF18: - 5750 03cc 53696C69 .ascii "SiliconId\000" - 5750 636F6E49 - 5750 6400 - 5751 .LASF88: - 5752 03d6 55534246 .ascii "USBFS_CyBtldrCommRead\000" - 5752 535F4379 - 5752 42746C64 - 5752 72436F6D - 5752 6D526561 - 5753 .LASF37: - 5754 03ec 62756666 .ascii "buffer\000" - 5754 657200 - 5755 .LASF87: - 5756 03f3 55534246 .ascii "USBFS_CyBtldrCommStart\000" - 5756 535F4379 - 5756 42746C64 - 5756 72436F6D - 5756 6D537461 - 5757 .LASF12: - 5758 040a 75696E74 .ascii "uint32\000" - 5758 333200 - 5759 .LASF17: - 5760 0411 72656738 .ascii "reg8\000" - 5760 00 - 5761 .LASF5: - 5762 0416 6C6F6E67 .ascii "long unsigned int\000" - 5762 20756E73 - 5762 69676E65 - 5762 6420696E - 5762 7400 - 5763 .LASF63: - 5764 0428 726F7741 .ascii "rowAddr\000" - 5764 64647200 - 5765 .LASF14: - 5766 0430 646F7562 .ascii "double\000" - 5766 6C6500 - 5767 .LASF76: - 5768 0437 424C5F43 .ascii "BL_Checksum\000" - 5768 6865636B - 5768 73756D00 - 5769 .LASF24: - 5770 0443 73697A65 .ascii "size\000" - 5770 00 - 5771 .LASF90: - 5772 0448 43795365 .ascii "CySetFlashEEBuffer\000" - 5772 74466C61 - 5772 73684545 - 5772 42756666 - 5772 657200 - 5773 .LASF77: - 5774 045b 424C5F43 .ascii "BL_ChecksumAccess\000" - 5774 6865636B - 5774 73756D41 - 5774 63636573 - 5774 7300 - 5775 .LASF91: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccX8T6Q1.s page 136 - - - 5776 046d 43795772 .ascii "CyWriteRowData\000" - 5776 69746552 - 5776 6F774461 - 5776 746100 - 5777 .LASF74: - 5778 047c 61727261 .ascii "arrayId\000" - 5778 79496400 - 5779 .LASF60: - 5780 0484 65726173 .ascii "erase\000" - 5780 6500 - 5781 .LASF22: - 5782 048a 424C5F45 .ascii "BL_ENTER\000" - 5782 4E544552 - 5782 00 - 5783 .LASF19: - 5784 0493 52657669 .ascii "Revision\000" - 5784 73696F6E - 5784 00 - 5785 .LASF80: - 5786 049c 49544D5F .ascii "ITM_RxBuffer\000" - 5786 52784275 - 5786 66666572 - 5786 00 - 5787 .LASF8: - 5788 04a9 756E7369 .ascii "unsigned int\000" - 5788 676E6564 - 5788 20696E74 - 5788 00 - 5789 .LASF85: - 5790 04b6 43795772 .ascii "CyWriteRowFull\000" - 5790 69746552 - 5790 6F774675 - 5790 6C6C00 - 5791 .LASF27: - 5792 04c5 6669656C .ascii "fieldName\000" - 5792 644E616D - 5792 6500 - 5793 .LASF69: - 5794 04cf 424C5F53 .ascii "BL_SetFlashByte\000" - 5794 6574466C - 5794 61736842 - 5794 79746500 - 5795 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br + 5642 .LASF71: + 5643 00e3 72756E54 .ascii "runType\000" + 5643 79706500 + 5644 .LASF11: + 5645 00eb 75696E74 .ascii "uint16\000" + 5645 313600 + 5646 .LASF41: + 5647 00f2 63686563 .ascii "checksum\000" + 5647 6B73756D + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 131 + + + 5647 00 + 5648 .LASF32: + 5649 00fb 424C5F56 .ascii "BL_ValidateBootloadable\000" + 5649 616C6964 + 5649 61746542 + 5649 6F6F746C + 5649 6F616461 + 5650 .LASF94: + 5651 0113 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" + 5651 43534932 + 5651 53445C73 + 5651 6F667477 + 5651 6172655C + 5652 0142 6E00 .ascii "n\000" + 5653 .LASF10: + 5654 0144 75696E74 .ascii "uint8\000" + 5654 3800 + 5655 .LASF96: + 5656 014a 43795365 .ascii "CySetTemp\000" + 5656 7454656D + 5656 7000 + 5657 .LASF67: + 5658 0154 424C5F53 .ascii "BL_Start\000" + 5658 74617274 + 5658 00 + 5659 .LASF20: + 5660 015d 426F6F74 .ascii "BootLoaderVersion\000" + 5660 4C6F6164 + 5660 65725665 + 5660 7273696F + 5660 6E00 + 5661 .LASF0: + 5662 016f 7369676E .ascii "signed char\000" + 5662 65642063 + 5662 68617200 + 5663 .LASF13: + 5664 017b 666C6F61 .ascii "float\000" + 5664 7400 + 5665 .LASF6: + 5666 0181 6C6F6E67 .ascii "long long int\000" + 5666 206C6F6E + 5666 6720696E + 5666 7400 + 5667 .LASF81: + 5668 018f 6D656D73 .ascii "memset\000" + 5668 657400 + 5669 .LASF15: + 5670 0196 63686172 .ascii "char\000" + 5670 00 + 5671 .LASF25: + 5672 019b 424C5F43 .ascii "BL_Calc8BitEepromSum\000" + 5672 616C6338 + 5672 42697445 + 5672 6570726F + 5672 6D53756D + 5673 .LASF72: + 5674 01b0 666C7341 .ascii "flsAddr\000" + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 132 + + + 5674 64647200 + 5675 .LASF70: + 5676 01b8 61646472 .ascii "address\000" + 5676 65737300 + 5677 .LASF35: + 5678 01c0 63757242 .ascii "curByte\000" + 5678 79746500 + 5679 .LASF64: + 5680 01c8 746D7049 .ascii "tmpIndex\000" + 5680 6E646578 + 5680 00 + 5681 .LASF46: + 5682 01d1 6E756D62 .ascii "numberRead\000" + 5682 65725265 + 5682 616400 + 5683 .LASF34: + 5684 01dc 63616C63 .ascii "calcedChecksum\000" + 5684 65644368 + 5684 65636B73 + 5684 756D00 + 5685 .LASF43: + 5686 01eb 424C5F48 .ascii "BL_HostLink\000" + 5686 6F73744C + 5686 696E6B00 + 5687 .LASF55: + 5688 01f7 636F6D6D .ascii "communicationState\000" + 5688 756E6963 + 5688 6174696F + 5688 6E537461 + 5688 746500 + 5689 .LASF92: + 5690 020a 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" + 5690 4320342E + 5690 372E3320 + 5690 32303133 + 5690 30333132 + 5691 023d 616E6368 .ascii "anch revision 196615]\000" + 5691 20726576 + 5691 6973696F + 5691 6E203139 + 5691 36363135 + 5692 .LASF93: + 5693 0253 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\BL.c\000" + 5693 6E657261 + 5693 7465645F + 5693 536F7572 + 5693 63655C50 + 5694 .LASF54: + 5695 0271 636C6561 .ascii "clearedMetaData\000" + 5695 7265644D + 5695 65746144 + 5695 61746100 + 5696 .LASF29: + 5697 0281 6669656C .ascii "fieldPtr\000" + 5697 64507472 + 5697 00 + 5698 .LASF53: + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 133 + + + 5699 028a 74696D65 .ascii "timeOutCnt\000" + 5699 4F757443 + 5699 6E7400 + 5700 .LASF95: + 5701 0295 424C5F4C .ascii "BL_LaunchApplication\000" + 5701 61756E63 + 5701 68417070 + 5701 6C696361 + 5701 74696F6E + 5702 .LASF23: + 5703 02aa 73746172 .ascii "start\000" + 5703 7400 + 5704 .LASF1: + 5705 02b0 756E7369 .ascii "unsigned char\000" + 5705 676E6564 + 5705 20636861 + 5705 7200 + 5706 .LASF57: + 5707 02be 64617461 .ascii "dataBuffer\000" + 5707 42756666 + 5707 657200 + 5708 .LASF83: + 5709 02c9 43794545 .ascii "CyEEPROM_Start\000" + 5709 50524F4D + 5709 5F537461 + 5709 727400 + 5710 .LASF89: + 5711 02d8 43794861 .ascii "CyHalt\000" + 5711 6C7400 + 5712 .LASF9: + 5713 02df 696E7433 .ascii "int32_t\000" + 5713 325F7400 + 5714 .LASF7: + 5715 02e7 6C6F6E67 .ascii "long long unsigned int\000" + 5715 206C6F6E + 5715 6720756E + 5715 7369676E + 5715 65642069 + 5716 .LASF49: + 5717 02fe 706B7443 .ascii "pktChecksum\000" + 5717 6865636B + 5717 73756D00 + 5718 .LASF68: + 5719 030a 43794274 .ascii "CyBtldr_CheckLaunch\000" + 5719 6C64725F + 5719 43686563 + 5719 6B4C6175 + 5719 6E636800 + 5720 .LASF16: + 5721 031e 63797374 .ascii "cystatus\000" + 5721 61747573 + 5721 00 + 5722 .LASF42: + 5723 0327 424C5F4C .ascii "BL_LaunchBootloadable\000" + 5723 61756E63 + 5723 68426F6F + 5723 746C6F61 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 134 + + + 5723 6461626C + 5724 .LASF36: + 5725 033d 424C5F43 .ascii "BL_CalcPacketChecksum\000" + 5725 616C6350 + 5725 61636B65 + 5725 74436865 + 5725 636B7375 + 5726 .LASF30: + 5727 0353 6669656C .ascii "fieldSize\000" + 5727 6453697A + 5727 6500 + 5728 .LASF40: + 5729 035d 73746174 .ascii "status\000" + 5729 757300 + 5730 .LASF62: + 5731 0364 726F774E .ascii "rowNum\000" + 5731 756D00 + 5732 .LASF56: + 5733 036b 7061636B .ascii "packetBuffer\000" + 5733 65744275 + 5733 66666572 + 5733 00 + 5734 .LASF38: + 5735 0378 424C5F43 .ascii "BL_Calc8BitFlashSum\000" + 5735 616C6338 + 5735 42697446 + 5735 6C617368 + 5735 53756D00 + 5736 .LASF78: + 5737 038c 424C5F53 .ascii "BL_SizeBytes\000" + 5737 697A6542 + 5737 79746573 + 5737 00 + 5738 .LASF4: + 5739 0399 6C6F6E67 .ascii "long int\000" + 5739 20696E74 + 5739 00 + 5740 .LASF50: + 5741 03a2 72656164 .ascii "readStat\000" + 5741 53746174 + 5741 00 + 5742 .LASF26: + 5743 03ab 424C5F47 .ascii "BL_GetMetadata\000" + 5743 65744D65 + 5743 74616461 + 5743 746100 + 5744 .LASF3: + 5745 03ba 73686F72 .ascii "short unsigned int\000" + 5745 7420756E + 5745 7369676E + 5745 65642069 + 5745 6E7400 + 5746 .LASF45: + 5747 03cd 74696D65 .ascii "timeOut\000" + 5747 4F757400 + 5748 .LASF47: + 5749 03d5 72737053 .ascii "rspSize\000" + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 135 + + + 5749 697A6500 + 5750 .LASF18: + 5751 03dd 53696C69 .ascii "SiliconId\000" + 5751 636F6E49 + 5751 6400 + 5752 .LASF88: + 5753 03e7 55534246 .ascii "USBFS_CyBtldrCommRead\000" + 5753 535F4379 + 5753 42746C64 + 5753 72436F6D + 5753 6D526561 + 5754 .LASF37: + 5755 03fd 62756666 .ascii "buffer\000" + 5755 657200 + 5756 .LASF87: + 5757 0404 55534246 .ascii "USBFS_CyBtldrCommStart\000" + 5757 535F4379 + 5757 42746C64 + 5757 72436F6D + 5757 6D537461 + 5758 .LASF12: + 5759 041b 75696E74 .ascii "uint32\000" + 5759 333200 + 5760 .LASF17: + 5761 0422 72656738 .ascii "reg8\000" + 5761 00 + 5762 .LASF5: + 5763 0427 6C6F6E67 .ascii "long unsigned int\000" + 5763 20756E73 + 5763 69676E65 + 5763 6420696E + 5763 7400 + 5764 .LASF63: + 5765 0439 726F7741 .ascii "rowAddr\000" + 5765 64647200 + 5766 .LASF14: + 5767 0441 646F7562 .ascii "double\000" + 5767 6C6500 + 5768 .LASF76: + 5769 0448 424C5F43 .ascii "BL_Checksum\000" + 5769 6865636B + 5769 73756D00 + 5770 .LASF24: + 5771 0454 73697A65 .ascii "size\000" + 5771 00 + 5772 .LASF90: + 5773 0459 43795365 .ascii "CySetFlashEEBuffer\000" + 5773 74466C61 + 5773 73684545 + 5773 42756666 + 5773 657200 + 5774 .LASF77: + 5775 046c 424C5F43 .ascii "BL_ChecksumAccess\000" + 5775 6865636B + 5775 73756D41 + 5775 63636573 + 5775 7300 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 136 + + + 5776 .LASF91: + 5777 047e 43795772 .ascii "CyWriteRowData\000" + 5777 69746552 + 5777 6F774461 + 5777 746100 + 5778 .LASF74: + 5779 048d 61727261 .ascii "arrayId\000" + 5779 79496400 + 5780 .LASF60: + 5781 0495 65726173 .ascii "erase\000" + 5781 6500 + 5782 .LASF22: + 5783 049b 424C5F45 .ascii "BL_ENTER\000" + 5783 4E544552 + 5783 00 + 5784 .LASF19: + 5785 04a4 52657669 .ascii "Revision\000" + 5785 73696F6E + 5785 00 + 5786 .LASF80: + 5787 04ad 49544D5F .ascii "ITM_RxBuffer\000" + 5787 52784275 + 5787 66666572 + 5787 00 + 5788 .LASF8: + 5789 04ba 756E7369 .ascii "unsigned int\000" + 5789 676E6564 + 5789 20696E74 + 5789 00 + 5790 .LASF85: + 5791 04c7 43795772 .ascii "CyWriteRowFull\000" + 5791 69746552 + 5791 6F774675 + 5791 6C6C00 + 5792 .LASF27: + 5793 04d6 6669656C .ascii "fieldName\000" + 5793 644E616D + 5793 6500 + 5794 .LASF69: + 5795 04e0 424C5F53 .ascii "BL_SetFlashByte\000" + 5795 6574466C + 5795 61736842 + 5795 79746500 + 5796 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/BL.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/BL.o index 5e6551dbb11c9da0a05a71bd1e0e7154c7c0a046..c420772b029253f8deb02bc8a7d3d4a4e5ee490a 100755 GIT binary patch delta 1211 zcmX|9TWC~Q6g~UibLUQG;$&v*XwsON%+!q2h)E`yh!!P7<12_`nGuyvN|pG+l3)9oc3Nt7t5odw>!rzl3dk=2mZQ|Z%2?@Lrdg+9MT@*Y zqN5T6A46bAp&h#@q4Sx5$Ezc+pd)lFxc$AQ7SIz~YLOHCf9C(MvF~Byl@@wo+^%VQ8 zvjmmeEBbG6i|4LV)z@LT&TM)@$mk6yJ1iL4{UbYLw@_bi@>`bTk)m+u6`D61>P;CN zJHoGv>eAnW-C~TU774o*d8f&jA%6kmttS6T^5_;AZ?mw3-QT?{`Wtuo_R#>p^mRu& zQ0viH;<#UW=i+u>YrI26vE<{55Ba~N%Z1wF0@Vy)QZEtBq8x?<$=tJB)Xf3O(-=Qe z&;ge$pUsm>+BT2EFyR+PPMhrHX`vyk(oA>dIoxidGxBmt z^9MH48tL$)Cloiq?~ru%_^sFj~7?6kguAqm=V4sQd;n z#yusBHeQ91SJ>Tyrm%NS6vnu_hW4R0E;T1B6=!p+G&xbEgKLmRP};J|TA3GZvuTAD ztqUKAtPBHxg~0Klo&Q==_n?GO*d+g!xA%=m%;GbW>WuPORHhOFoiW}3Ukoj6I}NUS zM!1NHng;PLEjuld<_JO>lstA$cBVPl#QM10tLQo}zO>aPP&6SDe_DKmL64sVTg(%C z(7MfqFwx6{UZt)ke$DG%GJ_%a?T|%@j{&MQx|K>+1mAmMs%gfMAv!J;t(81>+Y&bI z<3GZ+H9J9EE-rcu3cKj#e;3V_G#nX#qIf92ZCCEJP<|iQRW7^}2@H2^uA&Azq<#jq zLrYX@MD!=|6?Z+QYA?ZXhu!ouA=6i&d``p2Da;5K{P!T6cL z#5~dqn#;=9@A?jgjjq*oi0(FY{Si5j58%*f|8G^fV5f+2iYoC_4xDuF^70ve0lO6;oXYRMR6l? z9~EgEy~(5T6n)Mg#vh|E`1g2s^se-UZxCha8n5>29$6tfg}UhztkOwWP|MGt}=iYM_P&KTJJ-h4mv&3yJww$TmU%RN6t z$2ZV4`ZR3?V_?+<1d2k_1OywT387kK3Ss1#Np*xhX*^~YR7>myjpOv_QdOpX_R_@U zPY#^kODOv}bfum4|^<@SlE9Br__{*VmiY4}LD&Q7u-;5A8xTqO(w_1+~lgv4Y& zf&O`t$2y7dhVOJ-rOr-xH%N-K4FONbvqka5guv&D<`l=lv?0;T3zV=G10Rc)96{KjQjs(VeP{V=Fw0dm@8@ac{OfHGyN1 zx6OfQScff`i4|Z7ZxH733*lw#ix*%XYw`Q=05@54l(}sc2-gVnn6?XW53kuf;U+$_ mQ?P&^?OtI-@sGWOih2^g@CtK;&+!7`cU&Yq*nE)~4*dhXYk9o@ delta 600 zcmY+AL1+_E6h-I$`9GO-GNnl-A}VP$XpI)Ji&&yDAnGDg%_5~LDjIFUNNl7|ktk9H zyQsK`yowYGBCbS`mUN{EB4`o25h;kSiVG1pb)&fRJ+g9`IrHAV_g{vYDcmVEd(gG8 z`KOwE0n6gsvTP;%|56AIvaH}dU_&W0&rzkqgR*Ip6;Fqs%jTGA@tp7;e%abo#{%&- z@upWKaB4SGCna>IeO}+StQa5Bf5nIMP_j2@&h9>2mYBjjHo|(D>43{_u^J(%*}RycqYXN}?z?EGIlvKlZd&lLN@abd zbCd;ag!IRzEPAE~aFo93!}v-W(+5Mtra%6gUF5Dajm@yu7iiYxaDqOWUHKG&heP$qGWGmjG`<}YTR4)`V9qx=3&H0YI|#uTmkz3R6|9m#E6)Sv9dBAsN; R({1Kwddl41`j|Wz`3FA|a4Y}- diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyBootAsmGnu.lst b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyBootAsmGnu.lst index 86d52f0e..190593b0 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyBootAsmGnu.lst +++ b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyBootAsmGnu.lst @@ -22,7 +22,7 @@ ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 1 1 /******************************************************************************* 2 * FILENAME: cydevicegnu.inc 3 * OBSOLETE: Do not use this file. Use the _trm version instead. - 4 * PSoC Creator 3.0 + 4 * PSoC Creator 3.0 Component Pack 7 5 * 6 * DESCRIPTION: 7 * This file provides all of the address values for the entire PSoC device. @@ -5662,7 +5662,7 @@ ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 1 1 /******************************************************************************* 2 * FILENAME: cydevicegnu_trm.inc 3 * - 4 * PSoC Creator 3.0 + 4 * PSoC Creator 3.0 Component Pack 7 5 * 6 * DESCRIPTION: 7 * This file provides all of the address values for the entire PSoC device. @@ -11830,897 +11830,945 @@ ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 1 507 .set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 508 .set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 509 - 510 /* USBFS_USB */ - 511 .set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG - 512 .set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG - 513 .set USBFS_USB__ARB_EP1_INT_EN, CYREG_USB_ARB_EP1_INT_EN - 514 .set USBFS_USB__ARB_EP1_SR, CYREG_USB_ARB_EP1_SR - 515 .set USBFS_USB__ARB_EP2_CFG, CYREG_USB_ARB_EP2_CFG - 516 .set USBFS_USB__ARB_EP2_INT_EN, CYREG_USB_ARB_EP2_INT_EN - 517 .set USBFS_USB__ARB_EP2_SR, CYREG_USB_ARB_EP2_SR - 518 .set USBFS_USB__ARB_EP3_CFG, CYREG_USB_ARB_EP3_CFG - 519 .set USBFS_USB__ARB_EP3_INT_EN, CYREG_USB_ARB_EP3_INT_EN - 520 .set USBFS_USB__ARB_EP3_SR, CYREG_USB_ARB_EP3_SR - 521 .set USBFS_USB__ARB_EP4_CFG, CYREG_USB_ARB_EP4_CFG - 522 .set USBFS_USB__ARB_EP4_INT_EN, CYREG_USB_ARB_EP4_INT_EN - 523 .set USBFS_USB__ARB_EP4_SR, CYREG_USB_ARB_EP4_SR - 524 .set USBFS_USB__ARB_EP5_CFG, CYREG_USB_ARB_EP5_CFG - 525 .set USBFS_USB__ARB_EP5_INT_EN, CYREG_USB_ARB_EP5_INT_EN - 526 .set USBFS_USB__ARB_EP5_SR, CYREG_USB_ARB_EP5_SR - 527 .set USBFS_USB__ARB_EP6_CFG, CYREG_USB_ARB_EP6_CFG - 528 .set USBFS_USB__ARB_EP6_INT_EN, CYREG_USB_ARB_EP6_INT_EN - 529 .set USBFS_USB__ARB_EP6_SR, CYREG_USB_ARB_EP6_SR - 530 .set USBFS_USB__ARB_EP7_CFG, CYREG_USB_ARB_EP7_CFG - 531 .set USBFS_USB__ARB_EP7_INT_EN, CYREG_USB_ARB_EP7_INT_EN - 532 .set USBFS_USB__ARB_EP7_SR, CYREG_USB_ARB_EP7_SR - 533 .set USBFS_USB__ARB_EP8_CFG, CYREG_USB_ARB_EP8_CFG - 534 .set USBFS_USB__ARB_EP8_INT_EN, CYREG_USB_ARB_EP8_INT_EN - 535 .set USBFS_USB__ARB_EP8_SR, CYREG_USB_ARB_EP8_SR - 536 .set USBFS_USB__ARB_INT_EN, CYREG_USB_ARB_INT_EN - 537 .set USBFS_USB__ARB_INT_SR, CYREG_USB_ARB_INT_SR - 538 .set USBFS_USB__ARB_RW1_DR, CYREG_USB_ARB_RW1_DR - 539 .set USBFS_USB__ARB_RW1_RA, CYREG_USB_ARB_RW1_RA - 540 .set USBFS_USB__ARB_RW1_RA_MSB, CYREG_USB_ARB_RW1_RA_MSB - 541 .set USBFS_USB__ARB_RW1_WA, CYREG_USB_ARB_RW1_WA - 542 .set USBFS_USB__ARB_RW1_WA_MSB, CYREG_USB_ARB_RW1_WA_MSB - 543 .set USBFS_USB__ARB_RW2_DR, CYREG_USB_ARB_RW2_DR - 544 .set USBFS_USB__ARB_RW2_RA, CYREG_USB_ARB_RW2_RA - 545 .set USBFS_USB__ARB_RW2_RA_MSB, CYREG_USB_ARB_RW2_RA_MSB - 546 .set USBFS_USB__ARB_RW2_WA, CYREG_USB_ARB_RW2_WA - 547 .set USBFS_USB__ARB_RW2_WA_MSB, CYREG_USB_ARB_RW2_WA_MSB - 548 .set USBFS_USB__ARB_RW3_DR, CYREG_USB_ARB_RW3_DR - 549 .set USBFS_USB__ARB_RW3_RA, CYREG_USB_ARB_RW3_RA - 550 .set USBFS_USB__ARB_RW3_RA_MSB, CYREG_USB_ARB_RW3_RA_MSB - 551 .set USBFS_USB__ARB_RW3_WA, CYREG_USB_ARB_RW3_WA - 552 .set USBFS_USB__ARB_RW3_WA_MSB, CYREG_USB_ARB_RW3_WA_MSB - 553 .set USBFS_USB__ARB_RW4_DR, CYREG_USB_ARB_RW4_DR - 554 .set USBFS_USB__ARB_RW4_RA, CYREG_USB_ARB_RW4_RA - 555 .set USBFS_USB__ARB_RW4_RA_MSB, CYREG_USB_ARB_RW4_RA_MSB - 556 .set USBFS_USB__ARB_RW4_WA, CYREG_USB_ARB_RW4_WA - 557 .set USBFS_USB__ARB_RW4_WA_MSB, CYREG_USB_ARB_RW4_WA_MSB + 510 /* SD_PULLUP */ + 511 .set SD_PULLUP__0__MASK, 0x02 + 512 .set SD_PULLUP__0__PC, CYREG_PRT3_PC1 + 513 .set SD_PULLUP__0__PORT, 3 + 514 .set SD_PULLUP__0__SHIFT, 1 + 515 .set SD_PULLUP__1__MASK, 0x04 + 516 .set SD_PULLUP__1__PC, CYREG_PRT3_PC2 + 517 .set SD_PULLUP__1__PORT, 3 + 518 .set SD_PULLUP__1__SHIFT, 2 + 519 .set SD_PULLUP__2__MASK, 0x08 + 520 .set SD_PULLUP__2__PC, CYREG_PRT3_PC3 + 521 .set SD_PULLUP__2__PORT, 3 + 522 .set SD_PULLUP__2__SHIFT, 3 + 523 .set SD_PULLUP__3__MASK, 0x10 + 524 .set SD_PULLUP__3__PC, CYREG_PRT3_PC4 + 525 .set SD_PULLUP__3__PORT, 3 + 526 .set SD_PULLUP__3__SHIFT, 4 + 527 .set SD_PULLUP__4__MASK, 0x20 + 528 .set SD_PULLUP__4__PC, CYREG_PRT3_PC5 + 529 .set SD_PULLUP__4__PORT, 3 + 530 .set SD_PULLUP__4__SHIFT, 5 + 531 .set SD_PULLUP__AG, CYREG_PRT3_AG + 532 .set SD_PULLUP__AMUX, CYREG_PRT3_AMUX + 533 .set SD_PULLUP__BIE, CYREG_PRT3_BIE + 534 .set SD_PULLUP__BIT_MASK, CYREG_PRT3_BIT_MASK + 535 .set SD_PULLUP__BYP, CYREG_PRT3_BYP + 536 .set SD_PULLUP__CTL, CYREG_PRT3_CTL + 537 .set SD_PULLUP__DM0, CYREG_PRT3_DM0 + 538 .set SD_PULLUP__DM1, CYREG_PRT3_DM1 + 539 .set SD_PULLUP__DM2, CYREG_PRT3_DM2 + 540 .set SD_PULLUP__DR, CYREG_PRT3_DR + 541 .set SD_PULLUP__INP_DIS, CYREG_PRT3_INP_DIS + 542 .set SD_PULLUP__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG + 543 .set SD_PULLUP__LCD_EN, CYREG_PRT3_LCD_EN + 544 .set SD_PULLUP__MASK, 0x3E + 545 .set SD_PULLUP__PORT, 3 + 546 .set SD_PULLUP__PRT, CYREG_PRT3_PRT + 547 .set SD_PULLUP__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL + 548 .set SD_PULLUP__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN + 549 .set SD_PULLUP__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 + 550 .set SD_PULLUP__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 + 551 .set SD_PULLUP__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 + 552 .set SD_PULLUP__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 + 553 .set SD_PULLUP__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT + 554 .set SD_PULLUP__PS, CYREG_PRT3_PS + 555 .set SD_PULLUP__SHIFT, 1 + 556 .set SD_PULLUP__SLW, CYREG_PRT3_SLW + 557 ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 199 - 558 .set USBFS_USB__ARB_RW5_DR, CYREG_USB_ARB_RW5_DR - 559 .set USBFS_USB__ARB_RW5_RA, CYREG_USB_ARB_RW5_RA - 560 .set USBFS_USB__ARB_RW5_RA_MSB, CYREG_USB_ARB_RW5_RA_MSB - 561 .set USBFS_USB__ARB_RW5_WA, CYREG_USB_ARB_RW5_WA - 562 .set USBFS_USB__ARB_RW5_WA_MSB, CYREG_USB_ARB_RW5_WA_MSB - 563 .set USBFS_USB__ARB_RW6_DR, CYREG_USB_ARB_RW6_DR - 564 .set USBFS_USB__ARB_RW6_RA, CYREG_USB_ARB_RW6_RA - 565 .set USBFS_USB__ARB_RW6_RA_MSB, CYREG_USB_ARB_RW6_RA_MSB - 566 .set USBFS_USB__ARB_RW6_WA, CYREG_USB_ARB_RW6_WA - 567 .set USBFS_USB__ARB_RW6_WA_MSB, CYREG_USB_ARB_RW6_WA_MSB - 568 .set USBFS_USB__ARB_RW7_DR, CYREG_USB_ARB_RW7_DR - 569 .set USBFS_USB__ARB_RW7_RA, CYREG_USB_ARB_RW7_RA - 570 .set USBFS_USB__ARB_RW7_RA_MSB, CYREG_USB_ARB_RW7_RA_MSB - 571 .set USBFS_USB__ARB_RW7_WA, CYREG_USB_ARB_RW7_WA - 572 .set USBFS_USB__ARB_RW7_WA_MSB, CYREG_USB_ARB_RW7_WA_MSB - 573 .set USBFS_USB__ARB_RW8_DR, CYREG_USB_ARB_RW8_DR - 574 .set USBFS_USB__ARB_RW8_RA, CYREG_USB_ARB_RW8_RA - 575 .set USBFS_USB__ARB_RW8_RA_MSB, CYREG_USB_ARB_RW8_RA_MSB - 576 .set USBFS_USB__ARB_RW8_WA, CYREG_USB_ARB_RW8_WA - 577 .set USBFS_USB__ARB_RW8_WA_MSB, CYREG_USB_ARB_RW8_WA_MSB - 578 .set USBFS_USB__BUF_SIZE, CYREG_USB_BUF_SIZE - 579 .set USBFS_USB__BUS_RST_CNT, CYREG_USB_BUS_RST_CNT - 580 .set USBFS_USB__CR0, CYREG_USB_CR0 - 581 .set USBFS_USB__CR1, CYREG_USB_CR1 - 582 .set USBFS_USB__CWA, CYREG_USB_CWA - 583 .set USBFS_USB__CWA_MSB, CYREG_USB_CWA_MSB - 584 .set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES - 585 .set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB - 586 .set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG - 587 .set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT - 588 .set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR - 589 .set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0 - 590 .set USBFS_USB__EP0_DR1, CYREG_USB_EP0_DR1 - 591 .set USBFS_USB__EP0_DR2, CYREG_USB_EP0_DR2 - 592 .set USBFS_USB__EP0_DR3, CYREG_USB_EP0_DR3 - 593 .set USBFS_USB__EP0_DR4, CYREG_USB_EP0_DR4 - 594 .set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5 - 595 .set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6 - 596 .set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7 - 597 .set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE - 598 .set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE - 599 .set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE - 600 .set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5 - 601 .set USBFS_USB__PM_ACT_MSK, 0x01 - 602 .set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5 - 603 .set USBFS_USB__PM_STBY_MSK, 0x01 - 604 .set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0 - 605 .set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1 - 606 .set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0 - 607 .set USBFS_USB__SIE_EP2_CNT0, CYREG_USB_SIE_EP2_CNT0 - 608 .set USBFS_USB__SIE_EP2_CNT1, CYREG_USB_SIE_EP2_CNT1 - 609 .set USBFS_USB__SIE_EP2_CR0, CYREG_USB_SIE_EP2_CR0 - 610 .set USBFS_USB__SIE_EP3_CNT0, CYREG_USB_SIE_EP3_CNT0 - 611 .set USBFS_USB__SIE_EP3_CNT1, CYREG_USB_SIE_EP3_CNT1 - 612 .set USBFS_USB__SIE_EP3_CR0, CYREG_USB_SIE_EP3_CR0 - 613 .set USBFS_USB__SIE_EP4_CNT0, CYREG_USB_SIE_EP4_CNT0 - 614 .set USBFS_USB__SIE_EP4_CNT1, CYREG_USB_SIE_EP4_CNT1 + 558 /* USBFS_USB */ + 559 .set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG + 560 .set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG + 561 .set USBFS_USB__ARB_EP1_INT_EN, CYREG_USB_ARB_EP1_INT_EN + 562 .set USBFS_USB__ARB_EP1_SR, CYREG_USB_ARB_EP1_SR + 563 .set USBFS_USB__ARB_EP2_CFG, CYREG_USB_ARB_EP2_CFG + 564 .set USBFS_USB__ARB_EP2_INT_EN, CYREG_USB_ARB_EP2_INT_EN + 565 .set USBFS_USB__ARB_EP2_SR, CYREG_USB_ARB_EP2_SR + 566 .set USBFS_USB__ARB_EP3_CFG, CYREG_USB_ARB_EP3_CFG + 567 .set USBFS_USB__ARB_EP3_INT_EN, CYREG_USB_ARB_EP3_INT_EN + 568 .set USBFS_USB__ARB_EP3_SR, CYREG_USB_ARB_EP3_SR + 569 .set USBFS_USB__ARB_EP4_CFG, CYREG_USB_ARB_EP4_CFG + 570 .set USBFS_USB__ARB_EP4_INT_EN, CYREG_USB_ARB_EP4_INT_EN + 571 .set USBFS_USB__ARB_EP4_SR, CYREG_USB_ARB_EP4_SR + 572 .set USBFS_USB__ARB_EP5_CFG, CYREG_USB_ARB_EP5_CFG + 573 .set USBFS_USB__ARB_EP5_INT_EN, CYREG_USB_ARB_EP5_INT_EN + 574 .set USBFS_USB__ARB_EP5_SR, CYREG_USB_ARB_EP5_SR + 575 .set USBFS_USB__ARB_EP6_CFG, CYREG_USB_ARB_EP6_CFG + 576 .set USBFS_USB__ARB_EP6_INT_EN, CYREG_USB_ARB_EP6_INT_EN + 577 .set USBFS_USB__ARB_EP6_SR, CYREG_USB_ARB_EP6_SR + 578 .set USBFS_USB__ARB_EP7_CFG, CYREG_USB_ARB_EP7_CFG + 579 .set USBFS_USB__ARB_EP7_INT_EN, CYREG_USB_ARB_EP7_INT_EN + 580 .set USBFS_USB__ARB_EP7_SR, CYREG_USB_ARB_EP7_SR + 581 .set USBFS_USB__ARB_EP8_CFG, CYREG_USB_ARB_EP8_CFG + 582 .set USBFS_USB__ARB_EP8_INT_EN, CYREG_USB_ARB_EP8_INT_EN + 583 .set USBFS_USB__ARB_EP8_SR, CYREG_USB_ARB_EP8_SR + 584 .set USBFS_USB__ARB_INT_EN, CYREG_USB_ARB_INT_EN + 585 .set USBFS_USB__ARB_INT_SR, CYREG_USB_ARB_INT_SR + 586 .set USBFS_USB__ARB_RW1_DR, CYREG_USB_ARB_RW1_DR + 587 .set USBFS_USB__ARB_RW1_RA, CYREG_USB_ARB_RW1_RA + 588 .set USBFS_USB__ARB_RW1_RA_MSB, CYREG_USB_ARB_RW1_RA_MSB + 589 .set USBFS_USB__ARB_RW1_WA, CYREG_USB_ARB_RW1_WA + 590 .set USBFS_USB__ARB_RW1_WA_MSB, CYREG_USB_ARB_RW1_WA_MSB + 591 .set USBFS_USB__ARB_RW2_DR, CYREG_USB_ARB_RW2_DR + 592 .set USBFS_USB__ARB_RW2_RA, CYREG_USB_ARB_RW2_RA + 593 .set USBFS_USB__ARB_RW2_RA_MSB, CYREG_USB_ARB_RW2_RA_MSB + 594 .set USBFS_USB__ARB_RW2_WA, CYREG_USB_ARB_RW2_WA + 595 .set USBFS_USB__ARB_RW2_WA_MSB, CYREG_USB_ARB_RW2_WA_MSB + 596 .set USBFS_USB__ARB_RW3_DR, CYREG_USB_ARB_RW3_DR + 597 .set USBFS_USB__ARB_RW3_RA, CYREG_USB_ARB_RW3_RA + 598 .set USBFS_USB__ARB_RW3_RA_MSB, CYREG_USB_ARB_RW3_RA_MSB + 599 .set USBFS_USB__ARB_RW3_WA, CYREG_USB_ARB_RW3_WA + 600 .set USBFS_USB__ARB_RW3_WA_MSB, CYREG_USB_ARB_RW3_WA_MSB + 601 .set USBFS_USB__ARB_RW4_DR, CYREG_USB_ARB_RW4_DR + 602 .set USBFS_USB__ARB_RW4_RA, CYREG_USB_ARB_RW4_RA + 603 .set USBFS_USB__ARB_RW4_RA_MSB, CYREG_USB_ARB_RW4_RA_MSB + 604 .set USBFS_USB__ARB_RW4_WA, CYREG_USB_ARB_RW4_WA + 605 .set USBFS_USB__ARB_RW4_WA_MSB, CYREG_USB_ARB_RW4_WA_MSB + 606 .set USBFS_USB__ARB_RW5_DR, CYREG_USB_ARB_RW5_DR + 607 .set USBFS_USB__ARB_RW5_RA, CYREG_USB_ARB_RW5_RA + 608 .set USBFS_USB__ARB_RW5_RA_MSB, CYREG_USB_ARB_RW5_RA_MSB + 609 .set USBFS_USB__ARB_RW5_WA, CYREG_USB_ARB_RW5_WA + 610 .set USBFS_USB__ARB_RW5_WA_MSB, CYREG_USB_ARB_RW5_WA_MSB + 611 .set USBFS_USB__ARB_RW6_DR, CYREG_USB_ARB_RW6_DR + 612 .set USBFS_USB__ARB_RW6_RA, CYREG_USB_ARB_RW6_RA + 613 .set USBFS_USB__ARB_RW6_RA_MSB, CYREG_USB_ARB_RW6_RA_MSB + 614 .set USBFS_USB__ARB_RW6_WA, CYREG_USB_ARB_RW6_WA ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 200 - 615 .set USBFS_USB__SIE_EP4_CR0, CYREG_USB_SIE_EP4_CR0 - 616 .set USBFS_USB__SIE_EP5_CNT0, CYREG_USB_SIE_EP5_CNT0 - 617 .set USBFS_USB__SIE_EP5_CNT1, CYREG_USB_SIE_EP5_CNT1 - 618 .set USBFS_USB__SIE_EP5_CR0, CYREG_USB_SIE_EP5_CR0 - 619 .set USBFS_USB__SIE_EP6_CNT0, CYREG_USB_SIE_EP6_CNT0 - 620 .set USBFS_USB__SIE_EP6_CNT1, CYREG_USB_SIE_EP6_CNT1 - 621 .set USBFS_USB__SIE_EP6_CR0, CYREG_USB_SIE_EP6_CR0 - 622 .set USBFS_USB__SIE_EP7_CNT0, CYREG_USB_SIE_EP7_CNT0 - 623 .set USBFS_USB__SIE_EP7_CNT1, CYREG_USB_SIE_EP7_CNT1 - 624 .set USBFS_USB__SIE_EP7_CR0, CYREG_USB_SIE_EP7_CR0 - 625 .set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0 - 626 .set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1 - 627 .set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0 - 628 .set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN - 629 .set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR - 630 .set USBFS_USB__SOF0, CYREG_USB_SOF0 - 631 .set USBFS_USB__SOF1, CYREG_USB_SOF1 - 632 .set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0 - 633 .set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1 - 634 .set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN - 635 - 636 /* SCSI_Out */ - 637 .set SCSI_Out__0__AG, CYREG_PRT4_AG - 638 .set SCSI_Out__0__AMUX, CYREG_PRT4_AMUX - 639 .set SCSI_Out__0__BIE, CYREG_PRT4_BIE - 640 .set SCSI_Out__0__BIT_MASK, CYREG_PRT4_BIT_MASK - 641 .set SCSI_Out__0__BYP, CYREG_PRT4_BYP - 642 .set SCSI_Out__0__CTL, CYREG_PRT4_CTL - 643 .set SCSI_Out__0__DM0, CYREG_PRT4_DM0 - 644 .set SCSI_Out__0__DM1, CYREG_PRT4_DM1 - 645 .set SCSI_Out__0__DM2, CYREG_PRT4_DM2 - 646 .set SCSI_Out__0__DR, CYREG_PRT4_DR - 647 .set SCSI_Out__0__INP_DIS, CYREG_PRT4_INP_DIS - 648 .set SCSI_Out__0__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG - 649 .set SCSI_Out__0__LCD_EN, CYREG_PRT4_LCD_EN - 650 .set SCSI_Out__0__MASK, 0x08 - 651 .set SCSI_Out__0__PC, CYREG_PRT4_PC3 - 652 .set SCSI_Out__0__PORT, 4 - 653 .set SCSI_Out__0__PRT, CYREG_PRT4_PRT - 654 .set SCSI_Out__0__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL - 655 .set SCSI_Out__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN - 656 .set SCSI_Out__0__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 - 657 .set SCSI_Out__0__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 - 658 .set SCSI_Out__0__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 - 659 .set SCSI_Out__0__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 - 660 .set SCSI_Out__0__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT - 661 .set SCSI_Out__0__PS, CYREG_PRT4_PS - 662 .set SCSI_Out__0__SHIFT, 3 - 663 .set SCSI_Out__0__SLW, CYREG_PRT4_SLW - 664 .set SCSI_Out__1__AG, CYREG_PRT4_AG - 665 .set SCSI_Out__1__AMUX, CYREG_PRT4_AMUX - 666 .set SCSI_Out__1__BIE, CYREG_PRT4_BIE - 667 .set SCSI_Out__1__BIT_MASK, CYREG_PRT4_BIT_MASK - 668 .set SCSI_Out__1__BYP, CYREG_PRT4_BYP - 669 .set SCSI_Out__1__CTL, CYREG_PRT4_CTL - 670 .set SCSI_Out__1__DM0, CYREG_PRT4_DM0 - 671 .set SCSI_Out__1__DM1, CYREG_PRT4_DM1 + 615 .set USBFS_USB__ARB_RW6_WA_MSB, CYREG_USB_ARB_RW6_WA_MSB + 616 .set USBFS_USB__ARB_RW7_DR, CYREG_USB_ARB_RW7_DR + 617 .set USBFS_USB__ARB_RW7_RA, CYREG_USB_ARB_RW7_RA + 618 .set USBFS_USB__ARB_RW7_RA_MSB, CYREG_USB_ARB_RW7_RA_MSB + 619 .set USBFS_USB__ARB_RW7_WA, CYREG_USB_ARB_RW7_WA + 620 .set USBFS_USB__ARB_RW7_WA_MSB, CYREG_USB_ARB_RW7_WA_MSB + 621 .set USBFS_USB__ARB_RW8_DR, CYREG_USB_ARB_RW8_DR + 622 .set USBFS_USB__ARB_RW8_RA, CYREG_USB_ARB_RW8_RA + 623 .set USBFS_USB__ARB_RW8_RA_MSB, CYREG_USB_ARB_RW8_RA_MSB + 624 .set USBFS_USB__ARB_RW8_WA, CYREG_USB_ARB_RW8_WA + 625 .set USBFS_USB__ARB_RW8_WA_MSB, CYREG_USB_ARB_RW8_WA_MSB + 626 .set USBFS_USB__BUF_SIZE, CYREG_USB_BUF_SIZE + 627 .set USBFS_USB__BUS_RST_CNT, CYREG_USB_BUS_RST_CNT + 628 .set USBFS_USB__CR0, CYREG_USB_CR0 + 629 .set USBFS_USB__CR1, CYREG_USB_CR1 + 630 .set USBFS_USB__CWA, CYREG_USB_CWA + 631 .set USBFS_USB__CWA_MSB, CYREG_USB_CWA_MSB + 632 .set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES + 633 .set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB + 634 .set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG + 635 .set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT + 636 .set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR + 637 .set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0 + 638 .set USBFS_USB__EP0_DR1, CYREG_USB_EP0_DR1 + 639 .set USBFS_USB__EP0_DR2, CYREG_USB_EP0_DR2 + 640 .set USBFS_USB__EP0_DR3, CYREG_USB_EP0_DR3 + 641 .set USBFS_USB__EP0_DR4, CYREG_USB_EP0_DR4 + 642 .set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5 + 643 .set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6 + 644 .set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7 + 645 .set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE + 646 .set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE + 647 .set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE + 648 .set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5 + 649 .set USBFS_USB__PM_ACT_MSK, 0x01 + 650 .set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5 + 651 .set USBFS_USB__PM_STBY_MSK, 0x01 + 652 .set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0 + 653 .set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1 + 654 .set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0 + 655 .set USBFS_USB__SIE_EP2_CNT0, CYREG_USB_SIE_EP2_CNT0 + 656 .set USBFS_USB__SIE_EP2_CNT1, CYREG_USB_SIE_EP2_CNT1 + 657 .set USBFS_USB__SIE_EP2_CR0, CYREG_USB_SIE_EP2_CR0 + 658 .set USBFS_USB__SIE_EP3_CNT0, CYREG_USB_SIE_EP3_CNT0 + 659 .set USBFS_USB__SIE_EP3_CNT1, CYREG_USB_SIE_EP3_CNT1 + 660 .set USBFS_USB__SIE_EP3_CR0, CYREG_USB_SIE_EP3_CR0 + 661 .set USBFS_USB__SIE_EP4_CNT0, CYREG_USB_SIE_EP4_CNT0 + 662 .set USBFS_USB__SIE_EP4_CNT1, CYREG_USB_SIE_EP4_CNT1 + 663 .set USBFS_USB__SIE_EP4_CR0, CYREG_USB_SIE_EP4_CR0 + 664 .set USBFS_USB__SIE_EP5_CNT0, CYREG_USB_SIE_EP5_CNT0 + 665 .set USBFS_USB__SIE_EP5_CNT1, CYREG_USB_SIE_EP5_CNT1 + 666 .set USBFS_USB__SIE_EP5_CR0, CYREG_USB_SIE_EP5_CR0 + 667 .set USBFS_USB__SIE_EP6_CNT0, CYREG_USB_SIE_EP6_CNT0 + 668 .set USBFS_USB__SIE_EP6_CNT1, CYREG_USB_SIE_EP6_CNT1 + 669 .set USBFS_USB__SIE_EP6_CR0, CYREG_USB_SIE_EP6_CR0 + 670 .set USBFS_USB__SIE_EP7_CNT0, CYREG_USB_SIE_EP7_CNT0 + 671 .set USBFS_USB__SIE_EP7_CNT1, CYREG_USB_SIE_EP7_CNT1 ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 201 - 672 .set SCSI_Out__1__DM2, CYREG_PRT4_DM2 - 673 .set SCSI_Out__1__DR, CYREG_PRT4_DR - 674 .set SCSI_Out__1__INP_DIS, CYREG_PRT4_INP_DIS - 675 .set SCSI_Out__1__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG - 676 .set SCSI_Out__1__LCD_EN, CYREG_PRT4_LCD_EN - 677 .set SCSI_Out__1__MASK, 0x04 - 678 .set SCSI_Out__1__PC, CYREG_PRT4_PC2 - 679 .set SCSI_Out__1__PORT, 4 - 680 .set SCSI_Out__1__PRT, CYREG_PRT4_PRT - 681 .set SCSI_Out__1__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL - 682 .set SCSI_Out__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN - 683 .set SCSI_Out__1__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 - 684 .set SCSI_Out__1__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 - 685 .set SCSI_Out__1__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 - 686 .set SCSI_Out__1__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 - 687 .set SCSI_Out__1__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT - 688 .set SCSI_Out__1__PS, CYREG_PRT4_PS - 689 .set SCSI_Out__1__SHIFT, 2 - 690 .set SCSI_Out__1__SLW, CYREG_PRT4_SLW - 691 .set SCSI_Out__2__AG, CYREG_PRT0_AG - 692 .set SCSI_Out__2__AMUX, CYREG_PRT0_AMUX - 693 .set SCSI_Out__2__BIE, CYREG_PRT0_BIE - 694 .set SCSI_Out__2__BIT_MASK, CYREG_PRT0_BIT_MASK - 695 .set SCSI_Out__2__BYP, CYREG_PRT0_BYP - 696 .set SCSI_Out__2__CTL, CYREG_PRT0_CTL - 697 .set SCSI_Out__2__DM0, CYREG_PRT0_DM0 - 698 .set SCSI_Out__2__DM1, CYREG_PRT0_DM1 - 699 .set SCSI_Out__2__DM2, CYREG_PRT0_DM2 - 700 .set SCSI_Out__2__DR, CYREG_PRT0_DR - 701 .set SCSI_Out__2__INP_DIS, CYREG_PRT0_INP_DIS - 702 .set SCSI_Out__2__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG - 703 .set SCSI_Out__2__LCD_EN, CYREG_PRT0_LCD_EN - 704 .set SCSI_Out__2__MASK, 0x80 - 705 .set SCSI_Out__2__PC, CYREG_PRT0_PC7 - 706 .set SCSI_Out__2__PORT, 0 - 707 .set SCSI_Out__2__PRT, CYREG_PRT0_PRT - 708 .set SCSI_Out__2__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL - 709 .set SCSI_Out__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN - 710 .set SCSI_Out__2__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 - 711 .set SCSI_Out__2__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 - 712 .set SCSI_Out__2__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 - 713 .set SCSI_Out__2__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 - 714 .set SCSI_Out__2__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT - 715 .set SCSI_Out__2__PS, CYREG_PRT0_PS - 716 .set SCSI_Out__2__SHIFT, 7 - 717 .set SCSI_Out__2__SLW, CYREG_PRT0_SLW - 718 .set SCSI_Out__3__AG, CYREG_PRT0_AG - 719 .set SCSI_Out__3__AMUX, CYREG_PRT0_AMUX - 720 .set SCSI_Out__3__BIE, CYREG_PRT0_BIE - 721 .set SCSI_Out__3__BIT_MASK, CYREG_PRT0_BIT_MASK - 722 .set SCSI_Out__3__BYP, CYREG_PRT0_BYP - 723 .set SCSI_Out__3__CTL, CYREG_PRT0_CTL - 724 .set SCSI_Out__3__DM0, CYREG_PRT0_DM0 - 725 .set SCSI_Out__3__DM1, CYREG_PRT0_DM1 - 726 .set SCSI_Out__3__DM2, CYREG_PRT0_DM2 - 727 .set SCSI_Out__3__DR, CYREG_PRT0_DR - 728 .set SCSI_Out__3__INP_DIS, CYREG_PRT0_INP_DIS + 672 .set USBFS_USB__SIE_EP7_CR0, CYREG_USB_SIE_EP7_CR0 + 673 .set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0 + 674 .set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1 + 675 .set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0 + 676 .set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN + 677 .set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR + 678 .set USBFS_USB__SOF0, CYREG_USB_SOF0 + 679 .set USBFS_USB__SOF1, CYREG_USB_SOF1 + 680 .set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0 + 681 .set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1 + 682 .set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN + 683 + 684 /* SCSI_Out */ + 685 .set SCSI_Out__0__AG, CYREG_PRT4_AG + 686 .set SCSI_Out__0__AMUX, CYREG_PRT4_AMUX + 687 .set SCSI_Out__0__BIE, CYREG_PRT4_BIE + 688 .set SCSI_Out__0__BIT_MASK, CYREG_PRT4_BIT_MASK + 689 .set SCSI_Out__0__BYP, CYREG_PRT4_BYP + 690 .set SCSI_Out__0__CTL, CYREG_PRT4_CTL + 691 .set SCSI_Out__0__DM0, CYREG_PRT4_DM0 + 692 .set SCSI_Out__0__DM1, CYREG_PRT4_DM1 + 693 .set SCSI_Out__0__DM2, CYREG_PRT4_DM2 + 694 .set SCSI_Out__0__DR, CYREG_PRT4_DR + 695 .set SCSI_Out__0__INP_DIS, CYREG_PRT4_INP_DIS + 696 .set SCSI_Out__0__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG + 697 .set SCSI_Out__0__LCD_EN, CYREG_PRT4_LCD_EN + 698 .set SCSI_Out__0__MASK, 0x08 + 699 .set SCSI_Out__0__PC, CYREG_PRT4_PC3 + 700 .set SCSI_Out__0__PORT, 4 + 701 .set SCSI_Out__0__PRT, CYREG_PRT4_PRT + 702 .set SCSI_Out__0__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL + 703 .set SCSI_Out__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN + 704 .set SCSI_Out__0__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 + 705 .set SCSI_Out__0__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 + 706 .set SCSI_Out__0__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 + 707 .set SCSI_Out__0__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 + 708 .set SCSI_Out__0__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT + 709 .set SCSI_Out__0__PS, CYREG_PRT4_PS + 710 .set SCSI_Out__0__SHIFT, 3 + 711 .set SCSI_Out__0__SLW, CYREG_PRT4_SLW + 712 .set SCSI_Out__1__AG, CYREG_PRT4_AG + 713 .set SCSI_Out__1__AMUX, CYREG_PRT4_AMUX + 714 .set SCSI_Out__1__BIE, CYREG_PRT4_BIE + 715 .set SCSI_Out__1__BIT_MASK, CYREG_PRT4_BIT_MASK + 716 .set SCSI_Out__1__BYP, CYREG_PRT4_BYP + 717 .set SCSI_Out__1__CTL, CYREG_PRT4_CTL + 718 .set SCSI_Out__1__DM0, CYREG_PRT4_DM0 + 719 .set SCSI_Out__1__DM1, CYREG_PRT4_DM1 + 720 .set SCSI_Out__1__DM2, CYREG_PRT4_DM2 + 721 .set SCSI_Out__1__DR, CYREG_PRT4_DR + 722 .set SCSI_Out__1__INP_DIS, CYREG_PRT4_INP_DIS + 723 .set SCSI_Out__1__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG + 724 .set SCSI_Out__1__LCD_EN, CYREG_PRT4_LCD_EN + 725 .set SCSI_Out__1__MASK, 0x04 + 726 .set SCSI_Out__1__PC, CYREG_PRT4_PC2 + 727 .set SCSI_Out__1__PORT, 4 + 728 .set SCSI_Out__1__PRT, CYREG_PRT4_PRT ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 202 - 729 .set SCSI_Out__3__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG - 730 .set SCSI_Out__3__LCD_EN, CYREG_PRT0_LCD_EN - 731 .set SCSI_Out__3__MASK, 0x40 - 732 .set SCSI_Out__3__PC, CYREG_PRT0_PC6 - 733 .set SCSI_Out__3__PORT, 0 - 734 .set SCSI_Out__3__PRT, CYREG_PRT0_PRT - 735 .set SCSI_Out__3__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL - 736 .set SCSI_Out__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN - 737 .set SCSI_Out__3__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 - 738 .set SCSI_Out__3__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 - 739 .set SCSI_Out__3__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 - 740 .set SCSI_Out__3__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 - 741 .set SCSI_Out__3__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT - 742 .set SCSI_Out__3__PS, CYREG_PRT0_PS - 743 .set SCSI_Out__3__SHIFT, 6 - 744 .set SCSI_Out__3__SLW, CYREG_PRT0_SLW - 745 .set SCSI_Out__4__AG, CYREG_PRT0_AG - 746 .set SCSI_Out__4__AMUX, CYREG_PRT0_AMUX - 747 .set SCSI_Out__4__BIE, CYREG_PRT0_BIE - 748 .set SCSI_Out__4__BIT_MASK, CYREG_PRT0_BIT_MASK - 749 .set SCSI_Out__4__BYP, CYREG_PRT0_BYP - 750 .set SCSI_Out__4__CTL, CYREG_PRT0_CTL - 751 .set SCSI_Out__4__DM0, CYREG_PRT0_DM0 - 752 .set SCSI_Out__4__DM1, CYREG_PRT0_DM1 - 753 .set SCSI_Out__4__DM2, CYREG_PRT0_DM2 - 754 .set SCSI_Out__4__DR, CYREG_PRT0_DR - 755 .set SCSI_Out__4__INP_DIS, CYREG_PRT0_INP_DIS - 756 .set SCSI_Out__4__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG - 757 .set SCSI_Out__4__LCD_EN, CYREG_PRT0_LCD_EN - 758 .set SCSI_Out__4__MASK, 0x20 - 759 .set SCSI_Out__4__PC, CYREG_PRT0_PC5 - 760 .set SCSI_Out__4__PORT, 0 - 761 .set SCSI_Out__4__PRT, CYREG_PRT0_PRT - 762 .set SCSI_Out__4__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL - 763 .set SCSI_Out__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN - 764 .set SCSI_Out__4__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 - 765 .set SCSI_Out__4__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 - 766 .set SCSI_Out__4__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 - 767 .set SCSI_Out__4__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 - 768 .set SCSI_Out__4__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT - 769 .set SCSI_Out__4__PS, CYREG_PRT0_PS - 770 .set SCSI_Out__4__SHIFT, 5 - 771 .set SCSI_Out__4__SLW, CYREG_PRT0_SLW - 772 .set SCSI_Out__5__AG, CYREG_PRT0_AG - 773 .set SCSI_Out__5__AMUX, CYREG_PRT0_AMUX - 774 .set SCSI_Out__5__BIE, CYREG_PRT0_BIE - 775 .set SCSI_Out__5__BIT_MASK, CYREG_PRT0_BIT_MASK - 776 .set SCSI_Out__5__BYP, CYREG_PRT0_BYP - 777 .set SCSI_Out__5__CTL, CYREG_PRT0_CTL - 778 .set SCSI_Out__5__DM0, CYREG_PRT0_DM0 - 779 .set SCSI_Out__5__DM1, CYREG_PRT0_DM1 - 780 .set SCSI_Out__5__DM2, CYREG_PRT0_DM2 - 781 .set SCSI_Out__5__DR, CYREG_PRT0_DR - 782 .set SCSI_Out__5__INP_DIS, CYREG_PRT0_INP_DIS - 783 .set SCSI_Out__5__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG - 784 .set SCSI_Out__5__LCD_EN, CYREG_PRT0_LCD_EN - 785 .set SCSI_Out__5__MASK, 0x10 + 729 .set SCSI_Out__1__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL + 730 .set SCSI_Out__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN + 731 .set SCSI_Out__1__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 + 732 .set SCSI_Out__1__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 + 733 .set SCSI_Out__1__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 + 734 .set SCSI_Out__1__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 + 735 .set SCSI_Out__1__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT + 736 .set SCSI_Out__1__PS, CYREG_PRT4_PS + 737 .set SCSI_Out__1__SHIFT, 2 + 738 .set SCSI_Out__1__SLW, CYREG_PRT4_SLW + 739 .set SCSI_Out__2__AG, CYREG_PRT0_AG + 740 .set SCSI_Out__2__AMUX, CYREG_PRT0_AMUX + 741 .set SCSI_Out__2__BIE, CYREG_PRT0_BIE + 742 .set SCSI_Out__2__BIT_MASK, CYREG_PRT0_BIT_MASK + 743 .set SCSI_Out__2__BYP, CYREG_PRT0_BYP + 744 .set SCSI_Out__2__CTL, CYREG_PRT0_CTL + 745 .set SCSI_Out__2__DM0, CYREG_PRT0_DM0 + 746 .set SCSI_Out__2__DM1, CYREG_PRT0_DM1 + 747 .set SCSI_Out__2__DM2, CYREG_PRT0_DM2 + 748 .set SCSI_Out__2__DR, CYREG_PRT0_DR + 749 .set SCSI_Out__2__INP_DIS, CYREG_PRT0_INP_DIS + 750 .set SCSI_Out__2__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG + 751 .set SCSI_Out__2__LCD_EN, CYREG_PRT0_LCD_EN + 752 .set SCSI_Out__2__MASK, 0x80 + 753 .set SCSI_Out__2__PC, CYREG_PRT0_PC7 + 754 .set SCSI_Out__2__PORT, 0 + 755 .set SCSI_Out__2__PRT, CYREG_PRT0_PRT + 756 .set SCSI_Out__2__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL + 757 .set SCSI_Out__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN + 758 .set SCSI_Out__2__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 + 759 .set SCSI_Out__2__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 + 760 .set SCSI_Out__2__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 + 761 .set SCSI_Out__2__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 + 762 .set SCSI_Out__2__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT + 763 .set SCSI_Out__2__PS, CYREG_PRT0_PS + 764 .set SCSI_Out__2__SHIFT, 7 + 765 .set SCSI_Out__2__SLW, CYREG_PRT0_SLW + 766 .set SCSI_Out__3__AG, CYREG_PRT0_AG + 767 .set SCSI_Out__3__AMUX, CYREG_PRT0_AMUX + 768 .set SCSI_Out__3__BIE, CYREG_PRT0_BIE + 769 .set SCSI_Out__3__BIT_MASK, CYREG_PRT0_BIT_MASK + 770 .set SCSI_Out__3__BYP, CYREG_PRT0_BYP + 771 .set SCSI_Out__3__CTL, CYREG_PRT0_CTL + 772 .set SCSI_Out__3__DM0, CYREG_PRT0_DM0 + 773 .set SCSI_Out__3__DM1, CYREG_PRT0_DM1 + 774 .set SCSI_Out__3__DM2, CYREG_PRT0_DM2 + 775 .set SCSI_Out__3__DR, CYREG_PRT0_DR + 776 .set SCSI_Out__3__INP_DIS, CYREG_PRT0_INP_DIS + 777 .set SCSI_Out__3__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG + 778 .set SCSI_Out__3__LCD_EN, CYREG_PRT0_LCD_EN + 779 .set SCSI_Out__3__MASK, 0x40 + 780 .set SCSI_Out__3__PC, CYREG_PRT0_PC6 + 781 .set SCSI_Out__3__PORT, 0 + 782 .set SCSI_Out__3__PRT, CYREG_PRT0_PRT + 783 .set SCSI_Out__3__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL + 784 .set SCSI_Out__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN + 785 .set SCSI_Out__3__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 203 - 786 .set SCSI_Out__5__PC, CYREG_PRT0_PC4 - 787 .set SCSI_Out__5__PORT, 0 - 788 .set SCSI_Out__5__PRT, CYREG_PRT0_PRT - 789 .set SCSI_Out__5__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL - 790 .set SCSI_Out__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN - 791 .set SCSI_Out__5__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 - 792 .set SCSI_Out__5__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 - 793 .set SCSI_Out__5__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 - 794 .set SCSI_Out__5__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 - 795 .set SCSI_Out__5__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT - 796 .set SCSI_Out__5__PS, CYREG_PRT0_PS - 797 .set SCSI_Out__5__SHIFT, 4 - 798 .set SCSI_Out__5__SLW, CYREG_PRT0_SLW - 799 .set SCSI_Out__6__AG, CYREG_PRT0_AG - 800 .set SCSI_Out__6__AMUX, CYREG_PRT0_AMUX - 801 .set SCSI_Out__6__BIE, CYREG_PRT0_BIE - 802 .set SCSI_Out__6__BIT_MASK, CYREG_PRT0_BIT_MASK - 803 .set SCSI_Out__6__BYP, CYREG_PRT0_BYP - 804 .set SCSI_Out__6__CTL, CYREG_PRT0_CTL - 805 .set SCSI_Out__6__DM0, CYREG_PRT0_DM0 - 806 .set SCSI_Out__6__DM1, CYREG_PRT0_DM1 - 807 .set SCSI_Out__6__DM2, CYREG_PRT0_DM2 - 808 .set SCSI_Out__6__DR, CYREG_PRT0_DR - 809 .set SCSI_Out__6__INP_DIS, CYREG_PRT0_INP_DIS - 810 .set SCSI_Out__6__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG - 811 .set SCSI_Out__6__LCD_EN, CYREG_PRT0_LCD_EN - 812 .set SCSI_Out__6__MASK, 0x08 - 813 .set SCSI_Out__6__PC, CYREG_PRT0_PC3 - 814 .set SCSI_Out__6__PORT, 0 - 815 .set SCSI_Out__6__PRT, CYREG_PRT0_PRT - 816 .set SCSI_Out__6__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL - 817 .set SCSI_Out__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN - 818 .set SCSI_Out__6__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 - 819 .set SCSI_Out__6__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 - 820 .set SCSI_Out__6__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 - 821 .set SCSI_Out__6__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 - 822 .set SCSI_Out__6__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT - 823 .set SCSI_Out__6__PS, CYREG_PRT0_PS - 824 .set SCSI_Out__6__SHIFT, 3 - 825 .set SCSI_Out__6__SLW, CYREG_PRT0_SLW - 826 .set SCSI_Out__7__AG, CYREG_PRT0_AG - 827 .set SCSI_Out__7__AMUX, CYREG_PRT0_AMUX - 828 .set SCSI_Out__7__BIE, CYREG_PRT0_BIE - 829 .set SCSI_Out__7__BIT_MASK, CYREG_PRT0_BIT_MASK - 830 .set SCSI_Out__7__BYP, CYREG_PRT0_BYP - 831 .set SCSI_Out__7__CTL, CYREG_PRT0_CTL - 832 .set SCSI_Out__7__DM0, CYREG_PRT0_DM0 - 833 .set SCSI_Out__7__DM1, CYREG_PRT0_DM1 - 834 .set SCSI_Out__7__DM2, CYREG_PRT0_DM2 - 835 .set SCSI_Out__7__DR, CYREG_PRT0_DR - 836 .set SCSI_Out__7__INP_DIS, CYREG_PRT0_INP_DIS - 837 .set SCSI_Out__7__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG - 838 .set SCSI_Out__7__LCD_EN, CYREG_PRT0_LCD_EN - 839 .set SCSI_Out__7__MASK, 0x04 - 840 .set SCSI_Out__7__PC, CYREG_PRT0_PC2 - 841 .set SCSI_Out__7__PORT, 0 - 842 .set SCSI_Out__7__PRT, CYREG_PRT0_PRT + 786 .set SCSI_Out__3__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 + 787 .set SCSI_Out__3__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 + 788 .set SCSI_Out__3__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 + 789 .set SCSI_Out__3__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT + 790 .set SCSI_Out__3__PS, CYREG_PRT0_PS + 791 .set SCSI_Out__3__SHIFT, 6 + 792 .set SCSI_Out__3__SLW, CYREG_PRT0_SLW + 793 .set SCSI_Out__4__AG, CYREG_PRT0_AG + 794 .set SCSI_Out__4__AMUX, CYREG_PRT0_AMUX + 795 .set SCSI_Out__4__BIE, CYREG_PRT0_BIE + 796 .set SCSI_Out__4__BIT_MASK, CYREG_PRT0_BIT_MASK + 797 .set SCSI_Out__4__BYP, CYREG_PRT0_BYP + 798 .set SCSI_Out__4__CTL, CYREG_PRT0_CTL + 799 .set SCSI_Out__4__DM0, CYREG_PRT0_DM0 + 800 .set SCSI_Out__4__DM1, CYREG_PRT0_DM1 + 801 .set SCSI_Out__4__DM2, CYREG_PRT0_DM2 + 802 .set SCSI_Out__4__DR, CYREG_PRT0_DR + 803 .set SCSI_Out__4__INP_DIS, CYREG_PRT0_INP_DIS + 804 .set SCSI_Out__4__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG + 805 .set SCSI_Out__4__LCD_EN, CYREG_PRT0_LCD_EN + 806 .set SCSI_Out__4__MASK, 0x20 + 807 .set SCSI_Out__4__PC, CYREG_PRT0_PC5 + 808 .set SCSI_Out__4__PORT, 0 + 809 .set SCSI_Out__4__PRT, CYREG_PRT0_PRT + 810 .set SCSI_Out__4__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL + 811 .set SCSI_Out__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN + 812 .set SCSI_Out__4__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 + 813 .set SCSI_Out__4__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 + 814 .set SCSI_Out__4__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 + 815 .set SCSI_Out__4__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 + 816 .set SCSI_Out__4__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT + 817 .set SCSI_Out__4__PS, CYREG_PRT0_PS + 818 .set SCSI_Out__4__SHIFT, 5 + 819 .set SCSI_Out__4__SLW, CYREG_PRT0_SLW + 820 .set SCSI_Out__5__AG, CYREG_PRT0_AG + 821 .set SCSI_Out__5__AMUX, CYREG_PRT0_AMUX + 822 .set SCSI_Out__5__BIE, CYREG_PRT0_BIE + 823 .set SCSI_Out__5__BIT_MASK, CYREG_PRT0_BIT_MASK + 824 .set SCSI_Out__5__BYP, CYREG_PRT0_BYP + 825 .set SCSI_Out__5__CTL, CYREG_PRT0_CTL + 826 .set SCSI_Out__5__DM0, CYREG_PRT0_DM0 + 827 .set SCSI_Out__5__DM1, CYREG_PRT0_DM1 + 828 .set SCSI_Out__5__DM2, CYREG_PRT0_DM2 + 829 .set SCSI_Out__5__DR, CYREG_PRT0_DR + 830 .set SCSI_Out__5__INP_DIS, CYREG_PRT0_INP_DIS + 831 .set SCSI_Out__5__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG + 832 .set SCSI_Out__5__LCD_EN, CYREG_PRT0_LCD_EN + 833 .set SCSI_Out__5__MASK, 0x10 + 834 .set SCSI_Out__5__PC, CYREG_PRT0_PC4 + 835 .set SCSI_Out__5__PORT, 0 + 836 .set SCSI_Out__5__PRT, CYREG_PRT0_PRT + 837 .set SCSI_Out__5__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL + 838 .set SCSI_Out__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN + 839 .set SCSI_Out__5__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 + 840 .set SCSI_Out__5__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 + 841 .set SCSI_Out__5__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 + 842 .set SCSI_Out__5__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 204 - 843 .set SCSI_Out__7__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL - 844 .set SCSI_Out__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN - 845 .set SCSI_Out__7__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 - 846 .set SCSI_Out__7__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 - 847 .set SCSI_Out__7__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 - 848 .set SCSI_Out__7__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 - 849 .set SCSI_Out__7__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT - 850 .set SCSI_Out__7__PS, CYREG_PRT0_PS - 851 .set SCSI_Out__7__SHIFT, 2 - 852 .set SCSI_Out__7__SLW, CYREG_PRT0_SLW - 853 .set SCSI_Out__8__AG, CYREG_PRT0_AG - 854 .set SCSI_Out__8__AMUX, CYREG_PRT0_AMUX - 855 .set SCSI_Out__8__BIE, CYREG_PRT0_BIE - 856 .set SCSI_Out__8__BIT_MASK, CYREG_PRT0_BIT_MASK - 857 .set SCSI_Out__8__BYP, CYREG_PRT0_BYP - 858 .set SCSI_Out__8__CTL, CYREG_PRT0_CTL - 859 .set SCSI_Out__8__DM0, CYREG_PRT0_DM0 - 860 .set SCSI_Out__8__DM1, CYREG_PRT0_DM1 - 861 .set SCSI_Out__8__DM2, CYREG_PRT0_DM2 - 862 .set SCSI_Out__8__DR, CYREG_PRT0_DR - 863 .set SCSI_Out__8__INP_DIS, CYREG_PRT0_INP_DIS - 864 .set SCSI_Out__8__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG - 865 .set SCSI_Out__8__LCD_EN, CYREG_PRT0_LCD_EN - 866 .set SCSI_Out__8__MASK, 0x02 - 867 .set SCSI_Out__8__PC, CYREG_PRT0_PC1 - 868 .set SCSI_Out__8__PORT, 0 - 869 .set SCSI_Out__8__PRT, CYREG_PRT0_PRT - 870 .set SCSI_Out__8__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL - 871 .set SCSI_Out__8__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN - 872 .set SCSI_Out__8__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 - 873 .set SCSI_Out__8__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 - 874 .set SCSI_Out__8__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 - 875 .set SCSI_Out__8__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 - 876 .set SCSI_Out__8__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT - 877 .set SCSI_Out__8__PS, CYREG_PRT0_PS - 878 .set SCSI_Out__8__SHIFT, 1 - 879 .set SCSI_Out__8__SLW, CYREG_PRT0_SLW - 880 .set SCSI_Out__9__AG, CYREG_PRT0_AG - 881 .set SCSI_Out__9__AMUX, CYREG_PRT0_AMUX - 882 .set SCSI_Out__9__BIE, CYREG_PRT0_BIE - 883 .set SCSI_Out__9__BIT_MASK, CYREG_PRT0_BIT_MASK - 884 .set SCSI_Out__9__BYP, CYREG_PRT0_BYP - 885 .set SCSI_Out__9__CTL, CYREG_PRT0_CTL - 886 .set SCSI_Out__9__DM0, CYREG_PRT0_DM0 - 887 .set SCSI_Out__9__DM1, CYREG_PRT0_DM1 - 888 .set SCSI_Out__9__DM2, CYREG_PRT0_DM2 - 889 .set SCSI_Out__9__DR, CYREG_PRT0_DR - 890 .set SCSI_Out__9__INP_DIS, CYREG_PRT0_INP_DIS - 891 .set SCSI_Out__9__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG - 892 .set SCSI_Out__9__LCD_EN, CYREG_PRT0_LCD_EN - 893 .set SCSI_Out__9__MASK, 0x01 - 894 .set SCSI_Out__9__PC, CYREG_PRT0_PC0 - 895 .set SCSI_Out__9__PORT, 0 - 896 .set SCSI_Out__9__PRT, CYREG_PRT0_PRT - 897 .set SCSI_Out__9__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL - 898 .set SCSI_Out__9__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN - 899 .set SCSI_Out__9__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 + 843 .set SCSI_Out__5__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT + 844 .set SCSI_Out__5__PS, CYREG_PRT0_PS + 845 .set SCSI_Out__5__SHIFT, 4 + 846 .set SCSI_Out__5__SLW, CYREG_PRT0_SLW + 847 .set SCSI_Out__6__AG, CYREG_PRT0_AG + 848 .set SCSI_Out__6__AMUX, CYREG_PRT0_AMUX + 849 .set SCSI_Out__6__BIE, CYREG_PRT0_BIE + 850 .set SCSI_Out__6__BIT_MASK, CYREG_PRT0_BIT_MASK + 851 .set SCSI_Out__6__BYP, CYREG_PRT0_BYP + 852 .set SCSI_Out__6__CTL, CYREG_PRT0_CTL + 853 .set SCSI_Out__6__DM0, CYREG_PRT0_DM0 + 854 .set SCSI_Out__6__DM1, CYREG_PRT0_DM1 + 855 .set SCSI_Out__6__DM2, CYREG_PRT0_DM2 + 856 .set SCSI_Out__6__DR, CYREG_PRT0_DR + 857 .set SCSI_Out__6__INP_DIS, CYREG_PRT0_INP_DIS + 858 .set SCSI_Out__6__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG + 859 .set SCSI_Out__6__LCD_EN, CYREG_PRT0_LCD_EN + 860 .set SCSI_Out__6__MASK, 0x08 + 861 .set SCSI_Out__6__PC, CYREG_PRT0_PC3 + 862 .set SCSI_Out__6__PORT, 0 + 863 .set SCSI_Out__6__PRT, CYREG_PRT0_PRT + 864 .set SCSI_Out__6__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL + 865 .set SCSI_Out__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN + 866 .set SCSI_Out__6__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 + 867 .set SCSI_Out__6__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 + 868 .set SCSI_Out__6__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 + 869 .set SCSI_Out__6__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 + 870 .set SCSI_Out__6__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT + 871 .set SCSI_Out__6__PS, CYREG_PRT0_PS + 872 .set SCSI_Out__6__SHIFT, 3 + 873 .set SCSI_Out__6__SLW, CYREG_PRT0_SLW + 874 .set SCSI_Out__7__AG, CYREG_PRT0_AG + 875 .set SCSI_Out__7__AMUX, CYREG_PRT0_AMUX + 876 .set SCSI_Out__7__BIE, CYREG_PRT0_BIE + 877 .set SCSI_Out__7__BIT_MASK, CYREG_PRT0_BIT_MASK + 878 .set SCSI_Out__7__BYP, CYREG_PRT0_BYP + 879 .set SCSI_Out__7__CTL, CYREG_PRT0_CTL + 880 .set SCSI_Out__7__DM0, CYREG_PRT0_DM0 + 881 .set SCSI_Out__7__DM1, CYREG_PRT0_DM1 + 882 .set SCSI_Out__7__DM2, CYREG_PRT0_DM2 + 883 .set SCSI_Out__7__DR, CYREG_PRT0_DR + 884 .set SCSI_Out__7__INP_DIS, CYREG_PRT0_INP_DIS + 885 .set SCSI_Out__7__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG + 886 .set SCSI_Out__7__LCD_EN, CYREG_PRT0_LCD_EN + 887 .set SCSI_Out__7__MASK, 0x04 + 888 .set SCSI_Out__7__PC, CYREG_PRT0_PC2 + 889 .set SCSI_Out__7__PORT, 0 + 890 .set SCSI_Out__7__PRT, CYREG_PRT0_PRT + 891 .set SCSI_Out__7__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL + 892 .set SCSI_Out__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN + 893 .set SCSI_Out__7__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 + 894 .set SCSI_Out__7__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 + 895 .set SCSI_Out__7__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 + 896 .set SCSI_Out__7__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 + 897 .set SCSI_Out__7__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT + 898 .set SCSI_Out__7__PS, CYREG_PRT0_PS + 899 .set SCSI_Out__7__SHIFT, 2 ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 205 - 900 .set SCSI_Out__9__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 - 901 .set SCSI_Out__9__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 - 902 .set SCSI_Out__9__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 - 903 .set SCSI_Out__9__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT - 904 .set SCSI_Out__9__PS, CYREG_PRT0_PS - 905 .set SCSI_Out__9__SHIFT, 0 - 906 .set SCSI_Out__9__SLW, CYREG_PRT0_SLW - 907 .set SCSI_Out__ACK__AG, CYREG_PRT0_AG - 908 .set SCSI_Out__ACK__AMUX, CYREG_PRT0_AMUX - 909 .set SCSI_Out__ACK__BIE, CYREG_PRT0_BIE - 910 .set SCSI_Out__ACK__BIT_MASK, CYREG_PRT0_BIT_MASK - 911 .set SCSI_Out__ACK__BYP, CYREG_PRT0_BYP - 912 .set SCSI_Out__ACK__CTL, CYREG_PRT0_CTL - 913 .set SCSI_Out__ACK__DM0, CYREG_PRT0_DM0 - 914 .set SCSI_Out__ACK__DM1, CYREG_PRT0_DM1 - 915 .set SCSI_Out__ACK__DM2, CYREG_PRT0_DM2 - 916 .set SCSI_Out__ACK__DR, CYREG_PRT0_DR - 917 .set SCSI_Out__ACK__INP_DIS, CYREG_PRT0_INP_DIS - 918 .set SCSI_Out__ACK__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG - 919 .set SCSI_Out__ACK__LCD_EN, CYREG_PRT0_LCD_EN - 920 .set SCSI_Out__ACK__MASK, 0x40 - 921 .set SCSI_Out__ACK__PC, CYREG_PRT0_PC6 - 922 .set SCSI_Out__ACK__PORT, 0 - 923 .set SCSI_Out__ACK__PRT, CYREG_PRT0_PRT - 924 .set SCSI_Out__ACK__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL - 925 .set SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN - 926 .set SCSI_Out__ACK__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 - 927 .set SCSI_Out__ACK__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 - 928 .set SCSI_Out__ACK__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 - 929 .set SCSI_Out__ACK__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 - 930 .set SCSI_Out__ACK__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT - 931 .set SCSI_Out__ACK__PS, CYREG_PRT0_PS - 932 .set SCSI_Out__ACK__SHIFT, 6 - 933 .set SCSI_Out__ACK__SLW, CYREG_PRT0_SLW - 934 .set SCSI_Out__ATN__AG, CYREG_PRT4_AG - 935 .set SCSI_Out__ATN__AMUX, CYREG_PRT4_AMUX - 936 .set SCSI_Out__ATN__BIE, CYREG_PRT4_BIE - 937 .set SCSI_Out__ATN__BIT_MASK, CYREG_PRT4_BIT_MASK - 938 .set SCSI_Out__ATN__BYP, CYREG_PRT4_BYP - 939 .set SCSI_Out__ATN__CTL, CYREG_PRT4_CTL - 940 .set SCSI_Out__ATN__DM0, CYREG_PRT4_DM0 - 941 .set SCSI_Out__ATN__DM1, CYREG_PRT4_DM1 - 942 .set SCSI_Out__ATN__DM2, CYREG_PRT4_DM2 - 943 .set SCSI_Out__ATN__DR, CYREG_PRT4_DR - 944 .set SCSI_Out__ATN__INP_DIS, CYREG_PRT4_INP_DIS - 945 .set SCSI_Out__ATN__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG - 946 .set SCSI_Out__ATN__LCD_EN, CYREG_PRT4_LCD_EN - 947 .set SCSI_Out__ATN__MASK, 0x04 - 948 .set SCSI_Out__ATN__PC, CYREG_PRT4_PC2 - 949 .set SCSI_Out__ATN__PORT, 4 - 950 .set SCSI_Out__ATN__PRT, CYREG_PRT4_PRT - 951 .set SCSI_Out__ATN__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL - 952 .set SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN - 953 .set SCSI_Out__ATN__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 - 954 .set SCSI_Out__ATN__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 - 955 .set SCSI_Out__ATN__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 - 956 .set SCSI_Out__ATN__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 + 900 .set SCSI_Out__7__SLW, CYREG_PRT0_SLW + 901 .set SCSI_Out__8__AG, CYREG_PRT0_AG + 902 .set SCSI_Out__8__AMUX, CYREG_PRT0_AMUX + 903 .set SCSI_Out__8__BIE, CYREG_PRT0_BIE + 904 .set SCSI_Out__8__BIT_MASK, CYREG_PRT0_BIT_MASK + 905 .set SCSI_Out__8__BYP, CYREG_PRT0_BYP + 906 .set SCSI_Out__8__CTL, CYREG_PRT0_CTL + 907 .set SCSI_Out__8__DM0, CYREG_PRT0_DM0 + 908 .set SCSI_Out__8__DM1, CYREG_PRT0_DM1 + 909 .set SCSI_Out__8__DM2, CYREG_PRT0_DM2 + 910 .set SCSI_Out__8__DR, CYREG_PRT0_DR + 911 .set SCSI_Out__8__INP_DIS, CYREG_PRT0_INP_DIS + 912 .set SCSI_Out__8__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG + 913 .set SCSI_Out__8__LCD_EN, CYREG_PRT0_LCD_EN + 914 .set SCSI_Out__8__MASK, 0x02 + 915 .set SCSI_Out__8__PC, CYREG_PRT0_PC1 + 916 .set SCSI_Out__8__PORT, 0 + 917 .set SCSI_Out__8__PRT, CYREG_PRT0_PRT + 918 .set SCSI_Out__8__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL + 919 .set SCSI_Out__8__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN + 920 .set SCSI_Out__8__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 + 921 .set SCSI_Out__8__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 + 922 .set SCSI_Out__8__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 + 923 .set SCSI_Out__8__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 + 924 .set SCSI_Out__8__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT + 925 .set SCSI_Out__8__PS, CYREG_PRT0_PS + 926 .set SCSI_Out__8__SHIFT, 1 + 927 .set SCSI_Out__8__SLW, CYREG_PRT0_SLW + 928 .set SCSI_Out__9__AG, CYREG_PRT0_AG + 929 .set SCSI_Out__9__AMUX, CYREG_PRT0_AMUX + 930 .set SCSI_Out__9__BIE, CYREG_PRT0_BIE + 931 .set SCSI_Out__9__BIT_MASK, CYREG_PRT0_BIT_MASK + 932 .set SCSI_Out__9__BYP, CYREG_PRT0_BYP + 933 .set SCSI_Out__9__CTL, CYREG_PRT0_CTL + 934 .set SCSI_Out__9__DM0, CYREG_PRT0_DM0 + 935 .set SCSI_Out__9__DM1, CYREG_PRT0_DM1 + 936 .set SCSI_Out__9__DM2, CYREG_PRT0_DM2 + 937 .set SCSI_Out__9__DR, CYREG_PRT0_DR + 938 .set SCSI_Out__9__INP_DIS, CYREG_PRT0_INP_DIS + 939 .set SCSI_Out__9__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG + 940 .set SCSI_Out__9__LCD_EN, CYREG_PRT0_LCD_EN + 941 .set SCSI_Out__9__MASK, 0x01 + 942 .set SCSI_Out__9__PC, CYREG_PRT0_PC0 + 943 .set SCSI_Out__9__PORT, 0 + 944 .set SCSI_Out__9__PRT, CYREG_PRT0_PRT + 945 .set SCSI_Out__9__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL + 946 .set SCSI_Out__9__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN + 947 .set SCSI_Out__9__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 + 948 .set SCSI_Out__9__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 + 949 .set SCSI_Out__9__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 + 950 .set SCSI_Out__9__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 + 951 .set SCSI_Out__9__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT + 952 .set SCSI_Out__9__PS, CYREG_PRT0_PS + 953 .set SCSI_Out__9__SHIFT, 0 + 954 .set SCSI_Out__9__SLW, CYREG_PRT0_SLW + 955 .set SCSI_Out__ACK__AG, CYREG_PRT0_AG + 956 .set SCSI_Out__ACK__AMUX, CYREG_PRT0_AMUX ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 206 - 957 .set SCSI_Out__ATN__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT - 958 .set SCSI_Out__ATN__PS, CYREG_PRT4_PS - 959 .set SCSI_Out__ATN__SHIFT, 2 - 960 .set SCSI_Out__ATN__SLW, CYREG_PRT4_SLW - 961 .set SCSI_Out__BSY__AG, CYREG_PRT0_AG - 962 .set SCSI_Out__BSY__AMUX, CYREG_PRT0_AMUX - 963 .set SCSI_Out__BSY__BIE, CYREG_PRT0_BIE - 964 .set SCSI_Out__BSY__BIT_MASK, CYREG_PRT0_BIT_MASK - 965 .set SCSI_Out__BSY__BYP, CYREG_PRT0_BYP - 966 .set SCSI_Out__BSY__CTL, CYREG_PRT0_CTL - 967 .set SCSI_Out__BSY__DM0, CYREG_PRT0_DM0 - 968 .set SCSI_Out__BSY__DM1, CYREG_PRT0_DM1 - 969 .set SCSI_Out__BSY__DM2, CYREG_PRT0_DM2 - 970 .set SCSI_Out__BSY__DR, CYREG_PRT0_DR - 971 .set SCSI_Out__BSY__INP_DIS, CYREG_PRT0_INP_DIS - 972 .set SCSI_Out__BSY__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG - 973 .set SCSI_Out__BSY__LCD_EN, CYREG_PRT0_LCD_EN - 974 .set SCSI_Out__BSY__MASK, 0x80 - 975 .set SCSI_Out__BSY__PC, CYREG_PRT0_PC7 - 976 .set SCSI_Out__BSY__PORT, 0 - 977 .set SCSI_Out__BSY__PRT, CYREG_PRT0_PRT - 978 .set SCSI_Out__BSY__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL - 979 .set SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN - 980 .set SCSI_Out__BSY__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 - 981 .set SCSI_Out__BSY__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 - 982 .set SCSI_Out__BSY__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 - 983 .set SCSI_Out__BSY__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 - 984 .set SCSI_Out__BSY__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT - 985 .set SCSI_Out__BSY__PS, CYREG_PRT0_PS - 986 .set SCSI_Out__BSY__SHIFT, 7 - 987 .set SCSI_Out__BSY__SLW, CYREG_PRT0_SLW - 988 .set SCSI_Out__CD__AG, CYREG_PRT0_AG - 989 .set SCSI_Out__CD__AMUX, CYREG_PRT0_AMUX - 990 .set SCSI_Out__CD__BIE, CYREG_PRT0_BIE - 991 .set SCSI_Out__CD__BIT_MASK, CYREG_PRT0_BIT_MASK - 992 .set SCSI_Out__CD__BYP, CYREG_PRT0_BYP - 993 .set SCSI_Out__CD__CTL, CYREG_PRT0_CTL - 994 .set SCSI_Out__CD__DM0, CYREG_PRT0_DM0 - 995 .set SCSI_Out__CD__DM1, CYREG_PRT0_DM1 - 996 .set SCSI_Out__CD__DM2, CYREG_PRT0_DM2 - 997 .set SCSI_Out__CD__DR, CYREG_PRT0_DR - 998 .set SCSI_Out__CD__INP_DIS, CYREG_PRT0_INP_DIS - 999 .set SCSI_Out__CD__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG - 1000 .set SCSI_Out__CD__LCD_EN, CYREG_PRT0_LCD_EN - 1001 .set SCSI_Out__CD__MASK, 0x04 - 1002 .set SCSI_Out__CD__PC, CYREG_PRT0_PC2 - 1003 .set SCSI_Out__CD__PORT, 0 - 1004 .set SCSI_Out__CD__PRT, CYREG_PRT0_PRT - 1005 .set SCSI_Out__CD__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL - 1006 .set SCSI_Out__CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN - 1007 .set SCSI_Out__CD__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 - 1008 .set SCSI_Out__CD__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 - 1009 .set SCSI_Out__CD__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 - 1010 .set SCSI_Out__CD__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 - 1011 .set SCSI_Out__CD__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT - 1012 .set SCSI_Out__CD__PS, CYREG_PRT0_PS - 1013 .set SCSI_Out__CD__SHIFT, 2 + 957 .set SCSI_Out__ACK__BIE, CYREG_PRT0_BIE + 958 .set SCSI_Out__ACK__BIT_MASK, CYREG_PRT0_BIT_MASK + 959 .set SCSI_Out__ACK__BYP, CYREG_PRT0_BYP + 960 .set SCSI_Out__ACK__CTL, CYREG_PRT0_CTL + 961 .set SCSI_Out__ACK__DM0, CYREG_PRT0_DM0 + 962 .set SCSI_Out__ACK__DM1, CYREG_PRT0_DM1 + 963 .set SCSI_Out__ACK__DM2, CYREG_PRT0_DM2 + 964 .set SCSI_Out__ACK__DR, CYREG_PRT0_DR + 965 .set SCSI_Out__ACK__INP_DIS, CYREG_PRT0_INP_DIS + 966 .set SCSI_Out__ACK__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG + 967 .set SCSI_Out__ACK__LCD_EN, CYREG_PRT0_LCD_EN + 968 .set SCSI_Out__ACK__MASK, 0x40 + 969 .set SCSI_Out__ACK__PC, CYREG_PRT0_PC6 + 970 .set SCSI_Out__ACK__PORT, 0 + 971 .set SCSI_Out__ACK__PRT, CYREG_PRT0_PRT + 972 .set SCSI_Out__ACK__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL + 973 .set SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN + 974 .set SCSI_Out__ACK__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 + 975 .set SCSI_Out__ACK__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 + 976 .set SCSI_Out__ACK__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 + 977 .set SCSI_Out__ACK__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 + 978 .set SCSI_Out__ACK__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT + 979 .set SCSI_Out__ACK__PS, CYREG_PRT0_PS + 980 .set SCSI_Out__ACK__SHIFT, 6 + 981 .set SCSI_Out__ACK__SLW, CYREG_PRT0_SLW + 982 .set SCSI_Out__ATN__AG, CYREG_PRT4_AG + 983 .set SCSI_Out__ATN__AMUX, CYREG_PRT4_AMUX + 984 .set SCSI_Out__ATN__BIE, CYREG_PRT4_BIE + 985 .set SCSI_Out__ATN__BIT_MASK, CYREG_PRT4_BIT_MASK + 986 .set SCSI_Out__ATN__BYP, CYREG_PRT4_BYP + 987 .set SCSI_Out__ATN__CTL, CYREG_PRT4_CTL + 988 .set SCSI_Out__ATN__DM0, CYREG_PRT4_DM0 + 989 .set SCSI_Out__ATN__DM1, CYREG_PRT4_DM1 + 990 .set SCSI_Out__ATN__DM2, CYREG_PRT4_DM2 + 991 .set SCSI_Out__ATN__DR, CYREG_PRT4_DR + 992 .set SCSI_Out__ATN__INP_DIS, CYREG_PRT4_INP_DIS + 993 .set SCSI_Out__ATN__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG + 994 .set SCSI_Out__ATN__LCD_EN, CYREG_PRT4_LCD_EN + 995 .set SCSI_Out__ATN__MASK, 0x04 + 996 .set SCSI_Out__ATN__PC, CYREG_PRT4_PC2 + 997 .set SCSI_Out__ATN__PORT, 4 + 998 .set SCSI_Out__ATN__PRT, CYREG_PRT4_PRT + 999 .set SCSI_Out__ATN__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL + 1000 .set SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN + 1001 .set SCSI_Out__ATN__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 + 1002 .set SCSI_Out__ATN__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 + 1003 .set SCSI_Out__ATN__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 + 1004 .set SCSI_Out__ATN__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 + 1005 .set SCSI_Out__ATN__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT + 1006 .set SCSI_Out__ATN__PS, CYREG_PRT4_PS + 1007 .set SCSI_Out__ATN__SHIFT, 2 + 1008 .set SCSI_Out__ATN__SLW, CYREG_PRT4_SLW + 1009 .set SCSI_Out__BSY__AG, CYREG_PRT0_AG + 1010 .set SCSI_Out__BSY__AMUX, CYREG_PRT0_AMUX + 1011 .set SCSI_Out__BSY__BIE, CYREG_PRT0_BIE + 1012 .set SCSI_Out__BSY__BIT_MASK, CYREG_PRT0_BIT_MASK + 1013 .set SCSI_Out__BSY__BYP, CYREG_PRT0_BYP ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 207 - 1014 .set SCSI_Out__CD__SLW, CYREG_PRT0_SLW - 1015 .set SCSI_Out__DBP_raw__AG, CYREG_PRT4_AG - 1016 .set SCSI_Out__DBP_raw__AMUX, CYREG_PRT4_AMUX - 1017 .set SCSI_Out__DBP_raw__BIE, CYREG_PRT4_BIE - 1018 .set SCSI_Out__DBP_raw__BIT_MASK, CYREG_PRT4_BIT_MASK - 1019 .set SCSI_Out__DBP_raw__BYP, CYREG_PRT4_BYP - 1020 .set SCSI_Out__DBP_raw__CTL, CYREG_PRT4_CTL - 1021 .set SCSI_Out__DBP_raw__DM0, CYREG_PRT4_DM0 - 1022 .set SCSI_Out__DBP_raw__DM1, CYREG_PRT4_DM1 - 1023 .set SCSI_Out__DBP_raw__DM2, CYREG_PRT4_DM2 - 1024 .set SCSI_Out__DBP_raw__DR, CYREG_PRT4_DR - 1025 .set SCSI_Out__DBP_raw__INP_DIS, CYREG_PRT4_INP_DIS - 1026 .set SCSI_Out__DBP_raw__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG - 1027 .set SCSI_Out__DBP_raw__LCD_EN, CYREG_PRT4_LCD_EN - 1028 .set SCSI_Out__DBP_raw__MASK, 0x08 - 1029 .set SCSI_Out__DBP_raw__PC, CYREG_PRT4_PC3 - 1030 .set SCSI_Out__DBP_raw__PORT, 4 - 1031 .set SCSI_Out__DBP_raw__PRT, CYREG_PRT4_PRT - 1032 .set SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL - 1033 .set SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN - 1034 .set SCSI_Out__DBP_raw__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 - 1035 .set SCSI_Out__DBP_raw__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 - 1036 .set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 - 1037 .set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 - 1038 .set SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT - 1039 .set SCSI_Out__DBP_raw__PS, CYREG_PRT4_PS - 1040 .set SCSI_Out__DBP_raw__SHIFT, 3 - 1041 .set SCSI_Out__DBP_raw__SLW, CYREG_PRT4_SLW - 1042 .set SCSI_Out__IO_raw__AG, CYREG_PRT0_AG - 1043 .set SCSI_Out__IO_raw__AMUX, CYREG_PRT0_AMUX - 1044 .set SCSI_Out__IO_raw__BIE, CYREG_PRT0_BIE - 1045 .set SCSI_Out__IO_raw__BIT_MASK, CYREG_PRT0_BIT_MASK - 1046 .set SCSI_Out__IO_raw__BYP, CYREG_PRT0_BYP - 1047 .set SCSI_Out__IO_raw__CTL, CYREG_PRT0_CTL - 1048 .set SCSI_Out__IO_raw__DM0, CYREG_PRT0_DM0 - 1049 .set SCSI_Out__IO_raw__DM1, CYREG_PRT0_DM1 - 1050 .set SCSI_Out__IO_raw__DM2, CYREG_PRT0_DM2 - 1051 .set SCSI_Out__IO_raw__DR, CYREG_PRT0_DR - 1052 .set SCSI_Out__IO_raw__INP_DIS, CYREG_PRT0_INP_DIS - 1053 .set SCSI_Out__IO_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG - 1054 .set SCSI_Out__IO_raw__LCD_EN, CYREG_PRT0_LCD_EN - 1055 .set SCSI_Out__IO_raw__MASK, 0x01 - 1056 .set SCSI_Out__IO_raw__PC, CYREG_PRT0_PC0 - 1057 .set SCSI_Out__IO_raw__PORT, 0 - 1058 .set SCSI_Out__IO_raw__PRT, CYREG_PRT0_PRT - 1059 .set SCSI_Out__IO_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL - 1060 .set SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN - 1061 .set SCSI_Out__IO_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 - 1062 .set SCSI_Out__IO_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 - 1063 .set SCSI_Out__IO_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 - 1064 .set SCSI_Out__IO_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 - 1065 .set SCSI_Out__IO_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT - 1066 .set SCSI_Out__IO_raw__PS, CYREG_PRT0_PS - 1067 .set SCSI_Out__IO_raw__SHIFT, 0 - 1068 .set SCSI_Out__IO_raw__SLW, CYREG_PRT0_SLW - 1069 .set SCSI_Out__MSG__AG, CYREG_PRT0_AG - 1070 .set SCSI_Out__MSG__AMUX, CYREG_PRT0_AMUX + 1014 .set SCSI_Out__BSY__CTL, CYREG_PRT0_CTL + 1015 .set SCSI_Out__BSY__DM0, CYREG_PRT0_DM0 + 1016 .set SCSI_Out__BSY__DM1, CYREG_PRT0_DM1 + 1017 .set SCSI_Out__BSY__DM2, CYREG_PRT0_DM2 + 1018 .set SCSI_Out__BSY__DR, CYREG_PRT0_DR + 1019 .set SCSI_Out__BSY__INP_DIS, CYREG_PRT0_INP_DIS + 1020 .set SCSI_Out__BSY__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG + 1021 .set SCSI_Out__BSY__LCD_EN, CYREG_PRT0_LCD_EN + 1022 .set SCSI_Out__BSY__MASK, 0x80 + 1023 .set SCSI_Out__BSY__PC, CYREG_PRT0_PC7 + 1024 .set SCSI_Out__BSY__PORT, 0 + 1025 .set SCSI_Out__BSY__PRT, CYREG_PRT0_PRT + 1026 .set SCSI_Out__BSY__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL + 1027 .set SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN + 1028 .set SCSI_Out__BSY__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 + 1029 .set SCSI_Out__BSY__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 + 1030 .set SCSI_Out__BSY__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 + 1031 .set SCSI_Out__BSY__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 + 1032 .set SCSI_Out__BSY__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT + 1033 .set SCSI_Out__BSY__PS, CYREG_PRT0_PS + 1034 .set SCSI_Out__BSY__SHIFT, 7 + 1035 .set SCSI_Out__BSY__SLW, CYREG_PRT0_SLW + 1036 .set SCSI_Out__CD__AG, CYREG_PRT0_AG + 1037 .set SCSI_Out__CD__AMUX, CYREG_PRT0_AMUX + 1038 .set SCSI_Out__CD__BIE, CYREG_PRT0_BIE + 1039 .set SCSI_Out__CD__BIT_MASK, CYREG_PRT0_BIT_MASK + 1040 .set SCSI_Out__CD__BYP, CYREG_PRT0_BYP + 1041 .set SCSI_Out__CD__CTL, CYREG_PRT0_CTL + 1042 .set SCSI_Out__CD__DM0, CYREG_PRT0_DM0 + 1043 .set SCSI_Out__CD__DM1, CYREG_PRT0_DM1 + 1044 .set SCSI_Out__CD__DM2, CYREG_PRT0_DM2 + 1045 .set SCSI_Out__CD__DR, CYREG_PRT0_DR + 1046 .set SCSI_Out__CD__INP_DIS, CYREG_PRT0_INP_DIS + 1047 .set SCSI_Out__CD__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG + 1048 .set SCSI_Out__CD__LCD_EN, CYREG_PRT0_LCD_EN + 1049 .set SCSI_Out__CD__MASK, 0x04 + 1050 .set SCSI_Out__CD__PC, CYREG_PRT0_PC2 + 1051 .set SCSI_Out__CD__PORT, 0 + 1052 .set SCSI_Out__CD__PRT, CYREG_PRT0_PRT + 1053 .set SCSI_Out__CD__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL + 1054 .set SCSI_Out__CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN + 1055 .set SCSI_Out__CD__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 + 1056 .set SCSI_Out__CD__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 + 1057 .set SCSI_Out__CD__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 + 1058 .set SCSI_Out__CD__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 + 1059 .set SCSI_Out__CD__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT + 1060 .set SCSI_Out__CD__PS, CYREG_PRT0_PS + 1061 .set SCSI_Out__CD__SHIFT, 2 + 1062 .set SCSI_Out__CD__SLW, CYREG_PRT0_SLW + 1063 .set SCSI_Out__DBP_raw__AG, CYREG_PRT4_AG + 1064 .set SCSI_Out__DBP_raw__AMUX, CYREG_PRT4_AMUX + 1065 .set SCSI_Out__DBP_raw__BIE, CYREG_PRT4_BIE + 1066 .set SCSI_Out__DBP_raw__BIT_MASK, CYREG_PRT4_BIT_MASK + 1067 .set SCSI_Out__DBP_raw__BYP, CYREG_PRT4_BYP + 1068 .set SCSI_Out__DBP_raw__CTL, CYREG_PRT4_CTL + 1069 .set SCSI_Out__DBP_raw__DM0, CYREG_PRT4_DM0 + 1070 .set SCSI_Out__DBP_raw__DM1, CYREG_PRT4_DM1 ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 208 - 1071 .set SCSI_Out__MSG__BIE, CYREG_PRT0_BIE - 1072 .set SCSI_Out__MSG__BIT_MASK, CYREG_PRT0_BIT_MASK - 1073 .set SCSI_Out__MSG__BYP, CYREG_PRT0_BYP - 1074 .set SCSI_Out__MSG__CTL, CYREG_PRT0_CTL - 1075 .set SCSI_Out__MSG__DM0, CYREG_PRT0_DM0 - 1076 .set SCSI_Out__MSG__DM1, CYREG_PRT0_DM1 - 1077 .set SCSI_Out__MSG__DM2, CYREG_PRT0_DM2 - 1078 .set SCSI_Out__MSG__DR, CYREG_PRT0_DR - 1079 .set SCSI_Out__MSG__INP_DIS, CYREG_PRT0_INP_DIS - 1080 .set SCSI_Out__MSG__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG - 1081 .set SCSI_Out__MSG__LCD_EN, CYREG_PRT0_LCD_EN - 1082 .set SCSI_Out__MSG__MASK, 0x10 - 1083 .set SCSI_Out__MSG__PC, CYREG_PRT0_PC4 - 1084 .set SCSI_Out__MSG__PORT, 0 - 1085 .set SCSI_Out__MSG__PRT, CYREG_PRT0_PRT - 1086 .set SCSI_Out__MSG__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL - 1087 .set SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN - 1088 .set SCSI_Out__MSG__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 - 1089 .set SCSI_Out__MSG__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 - 1090 .set SCSI_Out__MSG__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 - 1091 .set SCSI_Out__MSG__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 - 1092 .set SCSI_Out__MSG__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT - 1093 .set SCSI_Out__MSG__PS, CYREG_PRT0_PS - 1094 .set SCSI_Out__MSG__SHIFT, 4 - 1095 .set SCSI_Out__MSG__SLW, CYREG_PRT0_SLW - 1096 .set SCSI_Out__REQ__AG, CYREG_PRT0_AG - 1097 .set SCSI_Out__REQ__AMUX, CYREG_PRT0_AMUX - 1098 .set SCSI_Out__REQ__BIE, CYREG_PRT0_BIE - 1099 .set SCSI_Out__REQ__BIT_MASK, CYREG_PRT0_BIT_MASK - 1100 .set SCSI_Out__REQ__BYP, CYREG_PRT0_BYP - 1101 .set SCSI_Out__REQ__CTL, CYREG_PRT0_CTL - 1102 .set SCSI_Out__REQ__DM0, CYREG_PRT0_DM0 - 1103 .set SCSI_Out__REQ__DM1, CYREG_PRT0_DM1 - 1104 .set SCSI_Out__REQ__DM2, CYREG_PRT0_DM2 - 1105 .set SCSI_Out__REQ__DR, CYREG_PRT0_DR - 1106 .set SCSI_Out__REQ__INP_DIS, CYREG_PRT0_INP_DIS - 1107 .set SCSI_Out__REQ__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG - 1108 .set SCSI_Out__REQ__LCD_EN, CYREG_PRT0_LCD_EN - 1109 .set SCSI_Out__REQ__MASK, 0x02 - 1110 .set SCSI_Out__REQ__PC, CYREG_PRT0_PC1 - 1111 .set SCSI_Out__REQ__PORT, 0 - 1112 .set SCSI_Out__REQ__PRT, CYREG_PRT0_PRT - 1113 .set SCSI_Out__REQ__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL - 1114 .set SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN - 1115 .set SCSI_Out__REQ__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 - 1116 .set SCSI_Out__REQ__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 - 1117 .set SCSI_Out__REQ__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 - 1118 .set SCSI_Out__REQ__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 - 1119 .set SCSI_Out__REQ__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT - 1120 .set SCSI_Out__REQ__PS, CYREG_PRT0_PS - 1121 .set SCSI_Out__REQ__SHIFT, 1 - 1122 .set SCSI_Out__REQ__SLW, CYREG_PRT0_SLW - 1123 .set SCSI_Out__RST__AG, CYREG_PRT0_AG - 1124 .set SCSI_Out__RST__AMUX, CYREG_PRT0_AMUX - 1125 .set SCSI_Out__RST__BIE, CYREG_PRT0_BIE - 1126 .set SCSI_Out__RST__BIT_MASK, CYREG_PRT0_BIT_MASK - 1127 .set SCSI_Out__RST__BYP, CYREG_PRT0_BYP + 1071 .set SCSI_Out__DBP_raw__DM2, CYREG_PRT4_DM2 + 1072 .set SCSI_Out__DBP_raw__DR, CYREG_PRT4_DR + 1073 .set SCSI_Out__DBP_raw__INP_DIS, CYREG_PRT4_INP_DIS + 1074 .set SCSI_Out__DBP_raw__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG + 1075 .set SCSI_Out__DBP_raw__LCD_EN, CYREG_PRT4_LCD_EN + 1076 .set SCSI_Out__DBP_raw__MASK, 0x08 + 1077 .set SCSI_Out__DBP_raw__PC, CYREG_PRT4_PC3 + 1078 .set SCSI_Out__DBP_raw__PORT, 4 + 1079 .set SCSI_Out__DBP_raw__PRT, CYREG_PRT4_PRT + 1080 .set SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL + 1081 .set SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN + 1082 .set SCSI_Out__DBP_raw__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 + 1083 .set SCSI_Out__DBP_raw__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 + 1084 .set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 + 1085 .set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 + 1086 .set SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT + 1087 .set SCSI_Out__DBP_raw__PS, CYREG_PRT4_PS + 1088 .set SCSI_Out__DBP_raw__SHIFT, 3 + 1089 .set SCSI_Out__DBP_raw__SLW, CYREG_PRT4_SLW + 1090 .set SCSI_Out__IO_raw__AG, CYREG_PRT0_AG + 1091 .set SCSI_Out__IO_raw__AMUX, CYREG_PRT0_AMUX + 1092 .set SCSI_Out__IO_raw__BIE, CYREG_PRT0_BIE + 1093 .set SCSI_Out__IO_raw__BIT_MASK, CYREG_PRT0_BIT_MASK + 1094 .set SCSI_Out__IO_raw__BYP, CYREG_PRT0_BYP + 1095 .set SCSI_Out__IO_raw__CTL, CYREG_PRT0_CTL + 1096 .set SCSI_Out__IO_raw__DM0, CYREG_PRT0_DM0 + 1097 .set SCSI_Out__IO_raw__DM1, CYREG_PRT0_DM1 + 1098 .set SCSI_Out__IO_raw__DM2, CYREG_PRT0_DM2 + 1099 .set SCSI_Out__IO_raw__DR, CYREG_PRT0_DR + 1100 .set SCSI_Out__IO_raw__INP_DIS, CYREG_PRT0_INP_DIS + 1101 .set SCSI_Out__IO_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG + 1102 .set SCSI_Out__IO_raw__LCD_EN, CYREG_PRT0_LCD_EN + 1103 .set SCSI_Out__IO_raw__MASK, 0x01 + 1104 .set SCSI_Out__IO_raw__PC, CYREG_PRT0_PC0 + 1105 .set SCSI_Out__IO_raw__PORT, 0 + 1106 .set SCSI_Out__IO_raw__PRT, CYREG_PRT0_PRT + 1107 .set SCSI_Out__IO_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL + 1108 .set SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN + 1109 .set SCSI_Out__IO_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 + 1110 .set SCSI_Out__IO_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 + 1111 .set SCSI_Out__IO_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 + 1112 .set SCSI_Out__IO_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 + 1113 .set SCSI_Out__IO_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT + 1114 .set SCSI_Out__IO_raw__PS, CYREG_PRT0_PS + 1115 .set SCSI_Out__IO_raw__SHIFT, 0 + 1116 .set SCSI_Out__IO_raw__SLW, CYREG_PRT0_SLW + 1117 .set SCSI_Out__MSG__AG, CYREG_PRT0_AG + 1118 .set SCSI_Out__MSG__AMUX, CYREG_PRT0_AMUX + 1119 .set SCSI_Out__MSG__BIE, CYREG_PRT0_BIE + 1120 .set SCSI_Out__MSG__BIT_MASK, CYREG_PRT0_BIT_MASK + 1121 .set SCSI_Out__MSG__BYP, CYREG_PRT0_BYP + 1122 .set SCSI_Out__MSG__CTL, CYREG_PRT0_CTL + 1123 .set SCSI_Out__MSG__DM0, CYREG_PRT0_DM0 + 1124 .set SCSI_Out__MSG__DM1, CYREG_PRT0_DM1 + 1125 .set SCSI_Out__MSG__DM2, CYREG_PRT0_DM2 + 1126 .set SCSI_Out__MSG__DR, CYREG_PRT0_DR + 1127 .set SCSI_Out__MSG__INP_DIS, CYREG_PRT0_INP_DIS ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 209 - 1128 .set SCSI_Out__RST__CTL, CYREG_PRT0_CTL - 1129 .set SCSI_Out__RST__DM0, CYREG_PRT0_DM0 - 1130 .set SCSI_Out__RST__DM1, CYREG_PRT0_DM1 - 1131 .set SCSI_Out__RST__DM2, CYREG_PRT0_DM2 - 1132 .set SCSI_Out__RST__DR, CYREG_PRT0_DR - 1133 .set SCSI_Out__RST__INP_DIS, CYREG_PRT0_INP_DIS - 1134 .set SCSI_Out__RST__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG - 1135 .set SCSI_Out__RST__LCD_EN, CYREG_PRT0_LCD_EN - 1136 .set SCSI_Out__RST__MASK, 0x20 - 1137 .set SCSI_Out__RST__PC, CYREG_PRT0_PC5 - 1138 .set SCSI_Out__RST__PORT, 0 - 1139 .set SCSI_Out__RST__PRT, CYREG_PRT0_PRT - 1140 .set SCSI_Out__RST__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL - 1141 .set SCSI_Out__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN - 1142 .set SCSI_Out__RST__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 - 1143 .set SCSI_Out__RST__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 - 1144 .set SCSI_Out__RST__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 - 1145 .set SCSI_Out__RST__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 - 1146 .set SCSI_Out__RST__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT - 1147 .set SCSI_Out__RST__PS, CYREG_PRT0_PS - 1148 .set SCSI_Out__RST__SHIFT, 5 - 1149 .set SCSI_Out__RST__SLW, CYREG_PRT0_SLW - 1150 .set SCSI_Out__SEL__AG, CYREG_PRT0_AG - 1151 .set SCSI_Out__SEL__AMUX, CYREG_PRT0_AMUX - 1152 .set SCSI_Out__SEL__BIE, CYREG_PRT0_BIE - 1153 .set SCSI_Out__SEL__BIT_MASK, CYREG_PRT0_BIT_MASK - 1154 .set SCSI_Out__SEL__BYP, CYREG_PRT0_BYP - 1155 .set SCSI_Out__SEL__CTL, CYREG_PRT0_CTL - 1156 .set SCSI_Out__SEL__DM0, CYREG_PRT0_DM0 - 1157 .set SCSI_Out__SEL__DM1, CYREG_PRT0_DM1 - 1158 .set SCSI_Out__SEL__DM2, CYREG_PRT0_DM2 - 1159 .set SCSI_Out__SEL__DR, CYREG_PRT0_DR - 1160 .set SCSI_Out__SEL__INP_DIS, CYREG_PRT0_INP_DIS - 1161 .set SCSI_Out__SEL__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG - 1162 .set SCSI_Out__SEL__LCD_EN, CYREG_PRT0_LCD_EN - 1163 .set SCSI_Out__SEL__MASK, 0x08 - 1164 .set SCSI_Out__SEL__PC, CYREG_PRT0_PC3 - 1165 .set SCSI_Out__SEL__PORT, 0 - 1166 .set SCSI_Out__SEL__PRT, CYREG_PRT0_PRT - 1167 .set SCSI_Out__SEL__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL - 1168 .set SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN - 1169 .set SCSI_Out__SEL__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 - 1170 .set SCSI_Out__SEL__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 - 1171 .set SCSI_Out__SEL__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 - 1172 .set SCSI_Out__SEL__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 - 1173 .set SCSI_Out__SEL__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT - 1174 .set SCSI_Out__SEL__PS, CYREG_PRT0_PS - 1175 .set SCSI_Out__SEL__SHIFT, 3 - 1176 .set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW - 1177 - 1178 /* USBFS_Dm */ - 1179 .set USBFS_Dm__0__MASK, 0x80 - 1180 .set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1 - 1181 .set USBFS_Dm__0__PORT, 15 - 1182 .set USBFS_Dm__0__SHIFT, 7 - 1183 .set USBFS_Dm__AG, CYREG_PRT15_AG - 1184 .set USBFS_Dm__AMUX, CYREG_PRT15_AMUX + 1128 .set SCSI_Out__MSG__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG + 1129 .set SCSI_Out__MSG__LCD_EN, CYREG_PRT0_LCD_EN + 1130 .set SCSI_Out__MSG__MASK, 0x10 + 1131 .set SCSI_Out__MSG__PC, CYREG_PRT0_PC4 + 1132 .set SCSI_Out__MSG__PORT, 0 + 1133 .set SCSI_Out__MSG__PRT, CYREG_PRT0_PRT + 1134 .set SCSI_Out__MSG__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL + 1135 .set SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN + 1136 .set SCSI_Out__MSG__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 + 1137 .set SCSI_Out__MSG__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 + 1138 .set SCSI_Out__MSG__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 + 1139 .set SCSI_Out__MSG__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 + 1140 .set SCSI_Out__MSG__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT + 1141 .set SCSI_Out__MSG__PS, CYREG_PRT0_PS + 1142 .set SCSI_Out__MSG__SHIFT, 4 + 1143 .set SCSI_Out__MSG__SLW, CYREG_PRT0_SLW + 1144 .set SCSI_Out__REQ__AG, CYREG_PRT0_AG + 1145 .set SCSI_Out__REQ__AMUX, CYREG_PRT0_AMUX + 1146 .set SCSI_Out__REQ__BIE, CYREG_PRT0_BIE + 1147 .set SCSI_Out__REQ__BIT_MASK, CYREG_PRT0_BIT_MASK + 1148 .set SCSI_Out__REQ__BYP, CYREG_PRT0_BYP + 1149 .set SCSI_Out__REQ__CTL, CYREG_PRT0_CTL + 1150 .set SCSI_Out__REQ__DM0, CYREG_PRT0_DM0 + 1151 .set SCSI_Out__REQ__DM1, CYREG_PRT0_DM1 + 1152 .set SCSI_Out__REQ__DM2, CYREG_PRT0_DM2 + 1153 .set SCSI_Out__REQ__DR, CYREG_PRT0_DR + 1154 .set SCSI_Out__REQ__INP_DIS, CYREG_PRT0_INP_DIS + 1155 .set SCSI_Out__REQ__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG + 1156 .set SCSI_Out__REQ__LCD_EN, CYREG_PRT0_LCD_EN + 1157 .set SCSI_Out__REQ__MASK, 0x02 + 1158 .set SCSI_Out__REQ__PC, CYREG_PRT0_PC1 + 1159 .set SCSI_Out__REQ__PORT, 0 + 1160 .set SCSI_Out__REQ__PRT, CYREG_PRT0_PRT + 1161 .set SCSI_Out__REQ__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL + 1162 .set SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN + 1163 .set SCSI_Out__REQ__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 + 1164 .set SCSI_Out__REQ__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 + 1165 .set SCSI_Out__REQ__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 + 1166 .set SCSI_Out__REQ__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 + 1167 .set SCSI_Out__REQ__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT + 1168 .set SCSI_Out__REQ__PS, CYREG_PRT0_PS + 1169 .set SCSI_Out__REQ__SHIFT, 1 + 1170 .set SCSI_Out__REQ__SLW, CYREG_PRT0_SLW + 1171 .set SCSI_Out__RST__AG, CYREG_PRT0_AG + 1172 .set SCSI_Out__RST__AMUX, CYREG_PRT0_AMUX + 1173 .set SCSI_Out__RST__BIE, CYREG_PRT0_BIE + 1174 .set SCSI_Out__RST__BIT_MASK, CYREG_PRT0_BIT_MASK + 1175 .set SCSI_Out__RST__BYP, CYREG_PRT0_BYP + 1176 .set SCSI_Out__RST__CTL, CYREG_PRT0_CTL + 1177 .set SCSI_Out__RST__DM0, CYREG_PRT0_DM0 + 1178 .set SCSI_Out__RST__DM1, CYREG_PRT0_DM1 + 1179 .set SCSI_Out__RST__DM2, CYREG_PRT0_DM2 + 1180 .set SCSI_Out__RST__DR, CYREG_PRT0_DR + 1181 .set SCSI_Out__RST__INP_DIS, CYREG_PRT0_INP_DIS + 1182 .set SCSI_Out__RST__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG + 1183 .set SCSI_Out__RST__LCD_EN, CYREG_PRT0_LCD_EN + 1184 .set SCSI_Out__RST__MASK, 0x20 ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 210 - 1185 .set USBFS_Dm__BIE, CYREG_PRT15_BIE - 1186 .set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK - 1187 .set USBFS_Dm__BYP, CYREG_PRT15_BYP - 1188 .set USBFS_Dm__CTL, CYREG_PRT15_CTL - 1189 .set USBFS_Dm__DM0, CYREG_PRT15_DM0 - 1190 .set USBFS_Dm__DM1, CYREG_PRT15_DM1 - 1191 .set USBFS_Dm__DM2, CYREG_PRT15_DM2 - 1192 .set USBFS_Dm__DR, CYREG_PRT15_DR - 1193 .set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS - 1194 .set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG - 1195 .set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN - 1196 .set USBFS_Dm__MASK, 0x80 - 1197 .set USBFS_Dm__PORT, 15 - 1198 .set USBFS_Dm__PRT, CYREG_PRT15_PRT - 1199 .set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL - 1200 .set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN - 1201 .set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 - 1202 .set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 - 1203 .set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 - 1204 .set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 - 1205 .set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT - 1206 .set USBFS_Dm__PS, CYREG_PRT15_PS - 1207 .set USBFS_Dm__SHIFT, 7 - 1208 .set USBFS_Dm__SLW, CYREG_PRT15_SLW - 1209 - 1210 /* USBFS_Dp */ - 1211 .set USBFS_Dp__0__MASK, 0x40 - 1212 .set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0 - 1213 .set USBFS_Dp__0__PORT, 15 - 1214 .set USBFS_Dp__0__SHIFT, 6 - 1215 .set USBFS_Dp__AG, CYREG_PRT15_AG - 1216 .set USBFS_Dp__AMUX, CYREG_PRT15_AMUX - 1217 .set USBFS_Dp__BIE, CYREG_PRT15_BIE - 1218 .set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK - 1219 .set USBFS_Dp__BYP, CYREG_PRT15_BYP - 1220 .set USBFS_Dp__CTL, CYREG_PRT15_CTL - 1221 .set USBFS_Dp__DM0, CYREG_PRT15_DM0 - 1222 .set USBFS_Dp__DM1, CYREG_PRT15_DM1 - 1223 .set USBFS_Dp__DM2, CYREG_PRT15_DM2 - 1224 .set USBFS_Dp__DR, CYREG_PRT15_DR - 1225 .set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS - 1226 .set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT - 1227 .set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG - 1228 .set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN - 1229 .set USBFS_Dp__MASK, 0x40 - 1230 .set USBFS_Dp__PORT, 15 - 1231 .set USBFS_Dp__PRT, CYREG_PRT15_PRT - 1232 .set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL - 1233 .set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN - 1234 .set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 - 1235 .set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 - 1236 .set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 - 1237 .set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 - 1238 .set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT - 1239 .set USBFS_Dp__PS, CYREG_PRT15_PS - 1240 .set USBFS_Dp__SHIFT, 6 - 1241 .set USBFS_Dp__SLW, CYREG_PRT15_SLW + 1185 .set SCSI_Out__RST__PC, CYREG_PRT0_PC5 + 1186 .set SCSI_Out__RST__PORT, 0 + 1187 .set SCSI_Out__RST__PRT, CYREG_PRT0_PRT + 1188 .set SCSI_Out__RST__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL + 1189 .set SCSI_Out__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN + 1190 .set SCSI_Out__RST__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 + 1191 .set SCSI_Out__RST__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 + 1192 .set SCSI_Out__RST__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 + 1193 .set SCSI_Out__RST__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 + 1194 .set SCSI_Out__RST__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT + 1195 .set SCSI_Out__RST__PS, CYREG_PRT0_PS + 1196 .set SCSI_Out__RST__SHIFT, 5 + 1197 .set SCSI_Out__RST__SLW, CYREG_PRT0_SLW + 1198 .set SCSI_Out__SEL__AG, CYREG_PRT0_AG + 1199 .set SCSI_Out__SEL__AMUX, CYREG_PRT0_AMUX + 1200 .set SCSI_Out__SEL__BIE, CYREG_PRT0_BIE + 1201 .set SCSI_Out__SEL__BIT_MASK, CYREG_PRT0_BIT_MASK + 1202 .set SCSI_Out__SEL__BYP, CYREG_PRT0_BYP + 1203 .set SCSI_Out__SEL__CTL, CYREG_PRT0_CTL + 1204 .set SCSI_Out__SEL__DM0, CYREG_PRT0_DM0 + 1205 .set SCSI_Out__SEL__DM1, CYREG_PRT0_DM1 + 1206 .set SCSI_Out__SEL__DM2, CYREG_PRT0_DM2 + 1207 .set SCSI_Out__SEL__DR, CYREG_PRT0_DR + 1208 .set SCSI_Out__SEL__INP_DIS, CYREG_PRT0_INP_DIS + 1209 .set SCSI_Out__SEL__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG + 1210 .set SCSI_Out__SEL__LCD_EN, CYREG_PRT0_LCD_EN + 1211 .set SCSI_Out__SEL__MASK, 0x08 + 1212 .set SCSI_Out__SEL__PC, CYREG_PRT0_PC3 + 1213 .set SCSI_Out__SEL__PORT, 0 + 1214 .set SCSI_Out__SEL__PRT, CYREG_PRT0_PRT + 1215 .set SCSI_Out__SEL__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL + 1216 .set SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN + 1217 .set SCSI_Out__SEL__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 + 1218 .set SCSI_Out__SEL__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 + 1219 .set SCSI_Out__SEL__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 + 1220 .set SCSI_Out__SEL__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 + 1221 .set SCSI_Out__SEL__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT + 1222 .set SCSI_Out__SEL__PS, CYREG_PRT0_PS + 1223 .set SCSI_Out__SEL__SHIFT, 3 + 1224 .set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW + 1225 + 1226 /* USBFS_Dm */ + 1227 .set USBFS_Dm__0__MASK, 0x80 + 1228 .set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1 + 1229 .set USBFS_Dm__0__PORT, 15 + 1230 .set USBFS_Dm__0__SHIFT, 7 + 1231 .set USBFS_Dm__AG, CYREG_PRT15_AG + 1232 .set USBFS_Dm__AMUX, CYREG_PRT15_AMUX + 1233 .set USBFS_Dm__BIE, CYREG_PRT15_BIE + 1234 .set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK + 1235 .set USBFS_Dm__BYP, CYREG_PRT15_BYP + 1236 .set USBFS_Dm__CTL, CYREG_PRT15_CTL + 1237 .set USBFS_Dm__DM0, CYREG_PRT15_DM0 + 1238 .set USBFS_Dm__DM1, CYREG_PRT15_DM1 + 1239 .set USBFS_Dm__DM2, CYREG_PRT15_DM2 + 1240 .set USBFS_Dm__DR, CYREG_PRT15_DR + 1241 .set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 211 - 1242 .set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15 - 1243 - 1244 /* Miscellaneous */ - 1245 /* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a f - 1246 .set CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO, 0 - 1247 .set CYDEV_DEBUGGING_DPS_SWD_SWV, 6 - 1248 .set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0 - 1249 .set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0 - 1250 .set CYDEV_CONFIG_FASTBOOT_ENABLED, 1 - 1251 .set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0 - 1252 .set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0 - 1253 .set CYDEV_CHIP_MEMBER_5B, 4 - 1254 .set CYDEV_CHIP_FAMILY_PSOC5, 3 - 1255 .set CYDEV_CHIP_DIE_PSOC5LP, 4 - 1256 .set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_DIE_PSOC5LP - 1257 .set CYDEV_BOOTLOADER_IO_COMP_USBFS, 1 - 1258 .set BCLK__BUS_CLK__HZ, 64000000 - 1259 .set BCLK__BUS_CLK__KHZ, 64000 - 1260 .set BCLK__BUS_CLK__MHZ, 64 - 1261 .set CYDEV_BOOTLOADER_APPLICATIONS, 1 - 1262 .set CYDEV_BOOTLOADER_CHECKSUM_BASIC, 0 - 1263 .set CYDEV_BOOTLOADER_CHECKSUM_CRC, 1 - 1264 .set CYDEV_BOOTLOADER_IO_COMP, CYDEV_BOOTLOADER_IO_COMP_USBFS - 1265 .set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT - 1266 .set CYDEV_CHIP_DIE_LEOPARD, 1 - 1267 .set CYDEV_CHIP_DIE_PANTHER, 3 - 1268 .set CYDEV_CHIP_DIE_PSOC4A, 2 - 1269 .set CYDEV_CHIP_DIE_UNKNOWN, 0 - 1270 .set CYDEV_CHIP_FAMILY_PSOC3, 1 - 1271 .set CYDEV_CHIP_FAMILY_PSOC4, 2 - 1272 .set CYDEV_CHIP_FAMILY_UNKNOWN, 0 - 1273 .set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5 - 1274 .set CYDEV_CHIP_JTAG_ID, 0x2E133069 - 1275 .set CYDEV_CHIP_MEMBER_3A, 1 - 1276 .set CYDEV_CHIP_MEMBER_4A, 2 - 1277 .set CYDEV_CHIP_MEMBER_5A, 3 - 1278 .set CYDEV_CHIP_MEMBER_UNKNOWN, 0 - 1279 .set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B - 1280 .set CYDEV_CHIP_REVISION_3A_ES1, 0 - 1281 .set CYDEV_CHIP_REVISION_3A_ES2, 1 - 1282 .set CYDEV_CHIP_REVISION_3A_ES3, 3 - 1283 .set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3 - 1284 .set CYDEV_CHIP_REVISION_4A_ES0, 17 - 1285 .set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17 - 1286 .set CYDEV_CHIP_REVISION_5A_ES0, 0 - 1287 .set CYDEV_CHIP_REVISION_5A_ES1, 1 - 1288 .set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1 - 1289 .set CYDEV_CHIP_REVISION_5B_ES0, 0 - 1290 .set CYDEV_CHIP_REVISION_USED, CYDEV_CHIP_REVISION_5B_PRODUCTION - 1291 .set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REV_PSOC5LP_PRODUCTION - 1292 .set CYDEV_CHIP_REV_LEOPARD_ES1, 0 - 1293 .set CYDEV_CHIP_REV_LEOPARD_ES2, 1 - 1294 .set CYDEV_CHIP_REV_LEOPARD_ES3, 3 - 1295 .set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3 - 1296 .set CYDEV_CHIP_REV_PANTHER_ES0, 0 - 1297 .set CYDEV_CHIP_REV_PANTHER_ES1, 1 - 1298 .set CYDEV_CHIP_REV_PANTHER_PRODUCTION, 1 + 1242 .set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG + 1243 .set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN + 1244 .set USBFS_Dm__MASK, 0x80 + 1245 .set USBFS_Dm__PORT, 15 + 1246 .set USBFS_Dm__PRT, CYREG_PRT15_PRT + 1247 .set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL + 1248 .set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN + 1249 .set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 + 1250 .set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 + 1251 .set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 + 1252 .set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 + 1253 .set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT + 1254 .set USBFS_Dm__PS, CYREG_PRT15_PS + 1255 .set USBFS_Dm__SHIFT, 7 + 1256 .set USBFS_Dm__SLW, CYREG_PRT15_SLW + 1257 + 1258 /* USBFS_Dp */ + 1259 .set USBFS_Dp__0__MASK, 0x40 + 1260 .set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0 + 1261 .set USBFS_Dp__0__PORT, 15 + 1262 .set USBFS_Dp__0__SHIFT, 6 + 1263 .set USBFS_Dp__AG, CYREG_PRT15_AG + 1264 .set USBFS_Dp__AMUX, CYREG_PRT15_AMUX + 1265 .set USBFS_Dp__BIE, CYREG_PRT15_BIE + 1266 .set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK + 1267 .set USBFS_Dp__BYP, CYREG_PRT15_BYP + 1268 .set USBFS_Dp__CTL, CYREG_PRT15_CTL + 1269 .set USBFS_Dp__DM0, CYREG_PRT15_DM0 + 1270 .set USBFS_Dp__DM1, CYREG_PRT15_DM1 + 1271 .set USBFS_Dp__DM2, CYREG_PRT15_DM2 + 1272 .set USBFS_Dp__DR, CYREG_PRT15_DR + 1273 .set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS + 1274 .set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT + 1275 .set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG + 1276 .set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN + 1277 .set USBFS_Dp__MASK, 0x40 + 1278 .set USBFS_Dp__PORT, 15 + 1279 .set USBFS_Dp__PRT, CYREG_PRT15_PRT + 1280 .set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL + 1281 .set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN + 1282 .set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 + 1283 .set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 + 1284 .set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 + 1285 .set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 + 1286 .set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT + 1287 .set USBFS_Dp__PS, CYREG_PRT15_PS + 1288 .set USBFS_Dp__SHIFT, 6 + 1289 .set USBFS_Dp__SLW, CYREG_PRT15_SLW + 1290 .set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15 + 1291 + 1292 /* Miscellaneous */ + 1293 /* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a f + 1294 .set CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO, 0 + 1295 .set CYDEV_DEBUGGING_DPS_SWD_SWV, 6 + 1296 .set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0 + 1297 .set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0 + 1298 .set CYDEV_CONFIG_FASTBOOT_ENABLED, 1 ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 212 - 1299 .set CYDEV_CHIP_REV_PSOC4A_ES0, 17 - 1300 .set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17 - 1301 .set CYDEV_CHIP_REV_PSOC5LP_ES0, 0 - 1302 .set CYDEV_CONFIGURATION_COMPRESSED, 1 - 1303 .set CYDEV_CONFIGURATION_DMA, 0 - 1304 .set CYDEV_CONFIGURATION_ECC, 0 - 1305 .set CYDEV_CONFIGURATION_IMOENABLED, CYDEV_CONFIG_FASTBOOT_ENABLED - 1306 .set CYDEV_CONFIGURATION_MODE, CYDEV_CONFIGURATION_MODE_COMPRESSED - 1307 .set CYDEV_CONFIGURATION_MODE_DMA, 2 - 1308 .set CYDEV_CONFIGURATION_MODE_UNCOMPRESSED, 1 - 1309 .set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_AllowButWarn - 1310 .set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1 - 1311 .set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2 - 1312 .set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD_SWV - 1313 .set CYDEV_DEBUGGING_DPS_Disable, 3 - 1314 .set CYDEV_DEBUGGING_DPS_JTAG_4, 1 - 1315 .set CYDEV_DEBUGGING_DPS_JTAG_5, 0 - 1316 .set CYDEV_DEBUGGING_DPS_SWD, 2 - 1317 .set CYDEV_DEBUGGING_ENABLE, 1 - 1318 .set CYDEV_DEBUGGING_XRES, 0 - 1319 .set CYDEV_DEBUG_ENABLE_MASK, 0x20 - 1320 .set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG - 1321 .set CYDEV_DMA_CHANNELS_AVAILABLE, 24 - 1322 .set CYDEV_ECC_ENABLE, 0 - 1323 .set CYDEV_HEAP_SIZE, 0x0800 - 1324 .set CYDEV_INSTRUCT_CACHE_ENABLED, 1 - 1325 .set CYDEV_INTR_RISING, 0x00000000 - 1326 .set CYDEV_PROJ_TYPE, 1 - 1327 .set CYDEV_PROJ_TYPE_BOOTLOADER, 1 - 1328 .set CYDEV_PROJ_TYPE_LOADABLE, 2 - 1329 .set CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER, 3 - 1330 .set CYDEV_PROJ_TYPE_STANDARD, 0 - 1331 .set CYDEV_PROTECTION_ENABLE, 0 - 1332 .set CYDEV_STACK_SIZE, 0x2000 - 1333 .set CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP, 1 - 1334 .set CYDEV_USE_BUNDLED_CMSIS, 1 - 1335 .set CYDEV_VARIABLE_VDDA, 0 - 1336 .set CYDEV_VDDA_MV, 5000 - 1337 .set CYDEV_VDDD_MV, 5000 - 1338 .set CYDEV_VDDIO0_MV, 5000 - 1339 .set CYDEV_VDDIO1_MV, 5000 - 1340 .set CYDEV_VDDIO2_MV, 5000 - 1341 .set CYDEV_VDDIO3_MV, 5000 - 1342 .set CYDEV_VIO0, 5 - 1343 .set CYDEV_VIO0_MV, 5000 - 1344 .set CYDEV_VIO1, 5 - 1345 .set CYDEV_VIO1_MV, 5000 - 1346 .set CYDEV_VIO2, 5 - 1347 .set CYDEV_VIO2_MV, 5000 - 1348 .set CYDEV_VIO3, 5 - 1349 .set CYDEV_VIO3_MV, 5000 - 1350 .set CyBtldr_Custom_Interface, CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO - 1351 .set CyBtldr_USBFS, CYDEV_BOOTLOADER_IO_COMP_USBFS - 1352 .set DMA_CHANNELS_USED__MASK0, 0x00000000 - 1353 .set CYDEV_BOOTLOADER_ENABLE, 1 - 1354 .endif - 16 + 1299 .set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0 + 1300 .set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0 + 1301 .set CYDEV_CHIP_MEMBER_5B, 4 + 1302 .set CYDEV_CHIP_FAMILY_PSOC5, 3 + 1303 .set CYDEV_CHIP_DIE_PSOC5LP, 4 + 1304 .set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_DIE_PSOC5LP + 1305 .set CYDEV_BOOTLOADER_IO_COMP_USBFS, 1 + 1306 .set BCLK__BUS_CLK__HZ, 64000000 + 1307 .set BCLK__BUS_CLK__KHZ, 64000 + 1308 .set BCLK__BUS_CLK__MHZ, 64 + 1309 .set CYDEV_BOOTLOADER_APPLICATIONS, 1 + 1310 .set CYDEV_BOOTLOADER_CHECKSUM_BASIC, 0 + 1311 .set CYDEV_BOOTLOADER_CHECKSUM_CRC, 1 + 1312 .set CYDEV_BOOTLOADER_IO_COMP, CYDEV_BOOTLOADER_IO_COMP_USBFS + 1313 .set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT + 1314 .set CYDEV_CHIP_DIE_LEOPARD, 1 + 1315 .set CYDEV_CHIP_DIE_PANTHER, 3 + 1316 .set CYDEV_CHIP_DIE_PSOC4A, 2 + 1317 .set CYDEV_CHIP_DIE_UNKNOWN, 0 + 1318 .set CYDEV_CHIP_FAMILY_PSOC3, 1 + 1319 .set CYDEV_CHIP_FAMILY_PSOC4, 2 + 1320 .set CYDEV_CHIP_FAMILY_UNKNOWN, 0 + 1321 .set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5 + 1322 .set CYDEV_CHIP_JTAG_ID, 0x2E133069 + 1323 .set CYDEV_CHIP_MEMBER_3A, 1 + 1324 .set CYDEV_CHIP_MEMBER_4A, 2 + 1325 .set CYDEV_CHIP_MEMBER_5A, 3 + 1326 .set CYDEV_CHIP_MEMBER_UNKNOWN, 0 + 1327 .set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B + 1328 .set CYDEV_CHIP_REVISION_3A_ES1, 0 + 1329 .set CYDEV_CHIP_REVISION_3A_ES2, 1 + 1330 .set CYDEV_CHIP_REVISION_3A_ES3, 3 + 1331 .set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3 + 1332 .set CYDEV_CHIP_REVISION_4A_ES0, 17 + 1333 .set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17 + 1334 .set CYDEV_CHIP_REVISION_5A_ES0, 0 + 1335 .set CYDEV_CHIP_REVISION_5A_ES1, 1 + 1336 .set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1 + 1337 .set CYDEV_CHIP_REVISION_5B_ES0, 0 + 1338 .set CYDEV_CHIP_REVISION_USED, CYDEV_CHIP_REVISION_5B_PRODUCTION + 1339 .set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REV_PSOC5LP_PRODUCTION + 1340 .set CYDEV_CHIP_REV_LEOPARD_ES1, 0 + 1341 .set CYDEV_CHIP_REV_LEOPARD_ES2, 1 + 1342 .set CYDEV_CHIP_REV_LEOPARD_ES3, 3 + 1343 .set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3 + 1344 .set CYDEV_CHIP_REV_PANTHER_ES0, 0 + 1345 .set CYDEV_CHIP_REV_PANTHER_ES1, 1 + 1346 .set CYDEV_CHIP_REV_PANTHER_PRODUCTION, 1 + 1347 .set CYDEV_CHIP_REV_PSOC4A_ES0, 17 + 1348 .set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17 + 1349 .set CYDEV_CHIP_REV_PSOC5LP_ES0, 0 + 1350 .set CYDEV_CONFIGURATION_COMPRESSED, 1 + 1351 .set CYDEV_CONFIGURATION_DMA, 0 + 1352 .set CYDEV_CONFIGURATION_ECC, 0 + 1353 .set CYDEV_CONFIGURATION_IMOENABLED, CYDEV_CONFIG_FASTBOOT_ENABLED + 1354 .set CYDEV_CONFIGURATION_MODE, CYDEV_CONFIGURATION_MODE_COMPRESSED + 1355 .set CYDEV_CONFIGURATION_MODE_DMA, 2 ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 213 + 1356 .set CYDEV_CONFIGURATION_MODE_UNCOMPRESSED, 1 + 1357 .set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_AllowButWarn + 1358 .set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1 + 1359 .set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2 + 1360 .set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD_SWV + 1361 .set CYDEV_DEBUGGING_DPS_Disable, 3 + 1362 .set CYDEV_DEBUGGING_DPS_JTAG_4, 1 + 1363 .set CYDEV_DEBUGGING_DPS_JTAG_5, 0 + 1364 .set CYDEV_DEBUGGING_DPS_SWD, 2 + 1365 .set CYDEV_DEBUGGING_ENABLE, 1 + 1366 .set CYDEV_DEBUGGING_XRES, 0 + 1367 .set CYDEV_DEBUG_ENABLE_MASK, 0x20 + 1368 .set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG + 1369 .set CYDEV_DMA_CHANNELS_AVAILABLE, 24 + 1370 .set CYDEV_ECC_ENABLE, 0 + 1371 .set CYDEV_HEAP_SIZE, 0x0800 + 1372 .set CYDEV_INSTRUCT_CACHE_ENABLED, 1 + 1373 .set CYDEV_INTR_RISING, 0x00000000 + 1374 .set CYDEV_PROJ_TYPE, 1 + 1375 .set CYDEV_PROJ_TYPE_BOOTLOADER, 1 + 1376 .set CYDEV_PROJ_TYPE_LOADABLE, 2 + 1377 .set CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER, 3 + 1378 .set CYDEV_PROJ_TYPE_STANDARD, 0 + 1379 .set CYDEV_PROTECTION_ENABLE, 0 + 1380 .set CYDEV_STACK_SIZE, 0x2000 + 1381 .set CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP, 1 + 1382 .set CYDEV_USE_BUNDLED_CMSIS, 1 + 1383 .set CYDEV_VARIABLE_VDDA, 0 + 1384 .set CYDEV_VDDA_MV, 5000 + 1385 .set CYDEV_VDDD_MV, 5000 + 1386 .set CYDEV_VDDIO0_MV, 5000 + 1387 .set CYDEV_VDDIO1_MV, 5000 + 1388 .set CYDEV_VDDIO2_MV, 5000 + 1389 .set CYDEV_VDDIO3_MV, 5000 + 1390 .set CYDEV_VIO0, 5 + 1391 .set CYDEV_VIO0_MV, 5000 + 1392 .set CYDEV_VIO1, 5 + 1393 .set CYDEV_VIO1_MV, 5000 + 1394 .set CYDEV_VIO2, 5 + 1395 .set CYDEV_VIO2_MV, 5000 + 1396 .set CYDEV_VIO3, 5 + 1397 .set CYDEV_VIO3_MV, 5000 + 1398 .set CyBtldr_Custom_Interface, CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO + 1399 .set CyBtldr_USBFS, CYDEV_BOOTLOADER_IO_COMP_USBFS + 1400 .set DMA_CHANNELS_USED__MASK0, 0x00000000 + 1401 .set CYDEV_BOOTLOADER_ENABLE, 1 + 1402 .endif + 16 17 .syntax unified 18 .text 19 .thumb @@ -12730,6 +12778,9 @@ ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 1 23 * Function Name: CyDelayCycles 24 ******************************************************************************** 25 * + ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 214 + + 26 * Summary: 27 * Delays for the specified number of cycles. 28 * @@ -12778,9 +12829,6 @@ ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 1 71 LSRS r1, r1, #6 /* 1 2 */ 72 PUSH {r2} /* 1 2 PUSH r2 to stack */ 73 LDR r2, =cy_flash_cycles /* 2 2 */ - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 214 - - 74 LDRB r1, [r2, r1] /* 2 2 */ 75 76 POP {r2} /* 2 2 POP r2 from stack */ @@ -12790,6 +12838,9 @@ ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 1 80 81 CyDelayCycles_loop: 82 SBCS r0, r0, r1 /* 1 2 */ + ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 215 + + 83 BPL CyDelayCycles_loop /* 3 2 */ 84 NOP /* 1 2 Loop alignment padding */ 85 NOP /* 1 2 Loop alignment padding */ @@ -12838,9 +12889,6 @@ ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 1 128 * Returns 0 if interrupts were previously enabled or 1 if interrupts 129 * were previously disabled. 130 * - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 215 - - 131 *******************************************************************************/ 132 /* uint8 CyEnterCriticalSection(void) */ 133 .global CyEnterCriticalSection @@ -12850,6 +12898,9 @@ ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 1 137 CyEnterCriticalSection: 138 0014 EFF31080 MRS r0, PRIMASK /* Save and return interrupt state */ 139 0018 72B6 CPSID I /* Disable interrupts */ + ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 216 + + 140 001a 7047 BX lr 141 .endfunc 142 diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyBootAsmGnu.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyBootAsmGnu.o index 78f434420c6f09cc5c6b01e470d38b3fedabe6fe..b15745c8c0ea74018f9e19396ba4617e1d2984b2 100755 GIT binary patch delta 15275 zcmZYF3!F{m{>SmP_a0*?cSUYz5K85U(nT~F!!R?(xcpN(gLEn{e?tFrgi3Lcj*?Vz&`n4dl5~0gpJ(scdwtikUazUw`?sF;tY@w7ex9}WwzqGo zHGg-lshN??Y4vwTo|tx`OU8(ye|+rE{f9p|PI8k$ejf|bqCe|?e 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z*%R)M{oMMM`42cfqBzVvo^4}B*@VSqekJn&{?8R<<5mC3rdy5uj0fQKh~g0*PqvN8 zWha=8y@Wi0(^K#(!#)9z--gp8id%n`y`iqyH*^#(9<)sq52etlSiu+IPmV7(EjNgF z*Z93ULGt)TiA!(CqId=N1wSa8zbze4+BS-FQT72Hu^Z+voZd6PW{%T?UlS|y-xGH# z&fwb}>>FBDa^tcQ#T&{_(15RLpPry%Th?vLyly`7Z2b1J@mXc#i*R!MuJLaoSVO@t(Ys9(isKDsp<@U)P(lD*%{M_I!hcjM0e>?uGKi;ire&S&bSC5;Y<4>MHl}pCWZ}!QY uX*Zl!Rkfu4jH+7(95Il&IZlu?Ms8$}VCUq2NA+m@ek7@P@c4yk{r>^_6cLR8 diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyDmac.lst b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyDmac.lst index bb456938..adf14086 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyDmac.lst +++ b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyDmac.lst @@ -1,4 +1,4 @@ -ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 +ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 1 1 .syntax unified @@ -58,7 +58,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 29:.\Generated_Source\PSoC5/CyDmac.c **** 30:.\Generated_Source\PSoC5/CyDmac.c **** #include "CyDmac.h" 31:.\Generated_Source\PSoC5/CyDmac.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 2 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 2 32:.\Generated_Source\PSoC5/CyDmac.c **** @@ -118,7 +118,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 44 .LVL1: 45 .L2: 46 000e 531E subs r3, r2, #1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 3 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 3 68:.\Generated_Source\PSoC5/CyDmac.c **** @@ -178,7 +178,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 93:.\Generated_Source\PSoC5/CyDmac.c **** * DMAC_PERIPH_ERR: 94:.\Generated_Source\PSoC5/CyDmac.c **** * Set to 1 when a peripheral responds to a bus transaction with an error 95:.\Generated_Source\PSoC5/CyDmac.c **** * response. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 4 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 4 96:.\Generated_Source\PSoC5/CyDmac.c **** * @@ -238,7 +238,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 124:.\Generated_Source\PSoC5/CyDmac.c **** * Clears the error bits in the DMAC error register. 125:.\Generated_Source\PSoC5/CyDmac.c **** * 126:.\Generated_Source\PSoC5/CyDmac.c **** * DMAC_PERIPH_ERR: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 5 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 5 127:.\Generated_Source\PSoC5/CyDmac.c **** * Set to 1 when a peripheral responds to a bus transaction with an error @@ -298,7 +298,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 154:.\Generated_Source\PSoC5/CyDmac.c **** * 155:.\Generated_Source\PSoC5/CyDmac.c **** * Summary: 156:.\Generated_Source\PSoC5/CyDmac.c **** * When an DMAC_BUS_TIMEOUT, DMAC_UNPOP_ACC and DMAC_PERIPH_ERR occurs the - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 6 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 6 157:.\Generated_Source\PSoC5/CyDmac.c **** * address of the error is written to the error address register and can be read @@ -358,7 +358,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 186:.\Generated_Source\PSoC5/CyDmac.c **** * Return: 187:.\Generated_Source\PSoC5/CyDmac.c **** * The allocated channel number. Zero is a valid channel number. 188:.\Generated_Source\PSoC5/CyDmac.c **** * DMA_INVALID_CHANNEL is returned if there are no channels available. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 7 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 7 189:.\Generated_Source\PSoC5/CyDmac.c **** * @@ -418,7 +418,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 185 .loc 1 202 0 186 001c 0134 adds r4, r4, #1 187 001e E4B2 uxtb r4, r4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 8 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 8 208:.\Generated_Source\PSoC5/CyDmac.c **** break; @@ -478,7 +478,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 230:.\Generated_Source\PSoC5/CyDmac.c **** * Summary: 231:.\Generated_Source\PSoC5/CyDmac.c **** * Frees a channel allocated by DmaChAlloc(). 232:.\Generated_Source\PSoC5/CyDmac.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 9 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 9 233:.\Generated_Source\PSoC5/CyDmac.c **** * Parameters: @@ -538,7 +538,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 254:.\Generated_Source\PSoC5/CyDmac.c **** 255:.\Generated_Source\PSoC5/CyDmac.c **** /* Exit critical section */ 256:.\Generated_Source\PSoC5/CyDmac.c **** CyExitCriticalSection(interruptState); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 10 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 10 249 .loc 1 256 0 @@ -598,7 +598,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 282:.\Generated_Source\PSoC5/CyDmac.c **** * 283:.\Generated_Source\PSoC5/CyDmac.c **** * 1 - When a TD is completed, the DMAC restores the original configuration 284:.\Generated_Source\PSoC5/CyDmac.c **** * values of the TD. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 11 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 11 285:.\Generated_Source\PSoC5/CyDmac.c **** * @@ -658,7 +658,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 319:.\Generated_Source\PSoC5/CyDmac.c **** /* Store the intermediate and final TD states on top of the original TD chain */ 320:.\Generated_Source\PSoC5/CyDmac.c **** CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_CH_BASIC_CFG_WORK_SEP); 297 .loc 1 320 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 12 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 12 298 0012 D15C ldrb r1, [r2, r3] @ zero_extendqisi2 @@ -718,7 +718,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 336:.\Generated_Source\PSoC5/CyDmac.c **** * 337:.\Generated_Source\PSoC5/CyDmac.c **** * Summary: 338:.\Generated_Source\PSoC5/CyDmac.c **** * Disables the DMA channel. Once this function is called, CyDmaChStatus() may - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 13 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 13 339:.\Generated_Source\PSoC5/CyDmac.c **** * be called to determine when the channel is disabled and which TDs were being @@ -778,7 +778,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 358 0018 0020 movs r0, #0 359 001a 7047 bx lr 360 .LVL26: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 14 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 14 361 .L38: @@ -838,7 +838,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 397:.\Generated_Source\PSoC5/CyDmac.c **** if(chHandle < CY_DMA_NUMBEROF_CHANNELS) 388 .loc 1 397 0 389 0000 1728 cmp r0, #23 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 15 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 15 390 0002 0CD8 bhi .L43 @@ -898,7 +898,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 412:.\Generated_Source\PSoC5/CyDmac.c **** * Summary: 413:.\Generated_Source\PSoC5/CyDmac.c **** * Sets the priority of a DMA channel. You can use this function when you want 414:.\Generated_Source\PSoC5/CyDmac.c **** * to change the priority at run time. If the priority remains the same for a - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 16 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 16 415:.\Generated_Source\PSoC5/CyDmac.c **** * DMA channel, then you can configure the priority in the .cydwr file. @@ -958,7 +958,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 456 001a 7047 bx lr 457 .LVL39: 458 .L48: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 17 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 17 432:.\Generated_Source\PSoC5/CyDmac.c **** cystatus status = CYRET_BAD_PARAM; @@ -1018,7 +1018,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 480 .cfi_startproc 481 @ args = 0, pretend = 0, frame = 0 482 @ frame_needed = 0, uses_anonymous_args = 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 18 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 18 483 @ link register save eliminated. @@ -1078,7 +1078,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 509 .loc 1 500 0 510 0024 C280 strh r2, [r0, #6] @ movhi 511 .LVL47: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 19 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 19 501:.\Generated_Source\PSoC5/CyDmac.c **** status = CYRET_SUCCESS; @@ -1138,7 +1138,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 535 .cfi_startproc 536 @ args = 0, pretend = 0, frame = 0 537 @ frame_needed = 0, uses_anonymous_args = 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 20 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 20 538 @ link register save eliminated. @@ -1198,7 +1198,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 547:.\Generated_Source\PSoC5/CyDmac.c **** * Summary: 548:.\Generated_Source\PSoC5/CyDmac.c **** * Allows the caller to terminate a chain of TDs, terminate one TD, or create a 549:.\Generated_Source\PSoC5/CyDmac.c **** * direct request to start the DMA channel. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 21 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 21 550:.\Generated_Source\PSoC5/CyDmac.c **** * @@ -1258,7 +1258,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 575:.\Generated_Source\PSoC5/CyDmac.c **** } 576:.\Generated_Source\PSoC5/CyDmac.c **** 577:.\Generated_Source\PSoC5/CyDmac.c **** return(status); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 22 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 22 578:.\Generated_Source\PSoC5/CyDmac.c **** } @@ -1318,7 +1318,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 606:.\Generated_Source\PSoC5/CyDmac.c **** status = (cystatus) ((uint32)CY_DMA_CH_STRUCT_PTR[chHandle].action[0u] & 629 .loc 1 606 0 630 0004 044B ldr r3, .L71 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 23 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 23 631 0006 0001 lsls r0, r0, #4 @@ -1378,7 +1378,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 631:.\Generated_Source\PSoC5/CyDmac.c **** * not needed. 632:.\Generated_Source\PSoC5/CyDmac.c **** * 633:.\Generated_Source\PSoC5/CyDmac.c **** * STATUS_TD_ACTIVE - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 24 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 24 634:.\Generated_Source\PSoC5/CyDmac.c **** * 0: Channel is not currently being serviced by DMAC @@ -1438,7 +1438,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 685 .loc 1 661 0 686 0016 22B1 cbz r2, .L81 662:.\Generated_Source\PSoC5/CyDmac.c **** { - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 25 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 25 663:.\Generated_Source\PSoC5/CyDmac.c **** *state= CY_DMA_CH_STRUCT_PTR[chHandle].basic_status[0]; @@ -1498,7 +1498,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 683:.\Generated_Source\PSoC5/CyDmac.c **** * 684:.\Generated_Source\PSoC5/CyDmac.c **** * uint8 burstCount: 685:.\Generated_Source\PSoC5/CyDmac.c **** * Specifies the size of bursts (1 to 127) the data transfer should be divided - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 26 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 26 686:.\Generated_Source\PSoC5/CyDmac.c **** * into. If this value is zero then the whole transfer is done in one burst. @@ -1558,7 +1558,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 735 .loc 1 723 0 736 0006 01F07F01 and r1, r1, #127 737 .LVL73: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 27 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 27 738 000a C400 lsls r4, r0, #3 @@ -1618,7 +1618,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 777 003e 10BD pop {r4, pc} 778 .cfi_endproc 779 .LFE15: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 28 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 28 780 .size CyDmaChSetConfiguration, .-CyDmaChSetConfiguration @@ -1678,7 +1678,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 806 000c 0AD9 bls .L89 761:.\Generated_Source\PSoC5/CyDmac.c **** { 762:.\Generated_Source\PSoC5/CyDmac.c **** /* Get pointer to the Next available. */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 29 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 29 763:.\Generated_Source\PSoC5/CyDmac.c **** element = CyDmaTdFreeIndex; @@ -1738,7 +1738,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 845 .thumb_func 846 .type CyDmaTdFree, %function 847 CyDmaTdFree: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 30 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 30 848 .LFB17: @@ -1798,7 +1798,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 874 0014 01F5F042 add r2, r1, #30720 875 0018 1978 ldrb r1, [r3, #0] @ zero_extendqisi2 803:.\Generated_Source\PSoC5/CyDmac.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 31 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 31 804:.\Generated_Source\PSoC5/CyDmac.c **** /* Set new Next Available. */ @@ -1858,7 +1858,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 823:.\Generated_Source\PSoC5/CyDmac.c **** * Parameters: 824:.\Generated_Source\PSoC5/CyDmac.c **** * None 825:.\Generated_Source\PSoC5/CyDmac.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 32 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 32 826:.\Generated_Source\PSoC5/CyDmac.c **** * Return: @@ -1918,7 +1918,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 853:.\Generated_Source\PSoC5/CyDmac.c **** * Zero based index of the next Transfer Descriptor in the TD chain. Zero is a 854:.\Generated_Source\PSoC5/CyDmac.c **** * valid pointer to the next TD; DMA_END_CHAIN_TD is the end of the chain. 855:.\Generated_Source\PSoC5/CyDmac.c **** * DMA_DISABLE_TD indicates an end to the chain and the DMA is disabled. No - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 33 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 33 856:.\Generated_Source\PSoC5/CyDmac.c **** * further TDs are fetched. DMA_DISABLE_TD is only supported on PSoC3 and @@ -1978,7 +1978,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 948 .cfi_offset 5, -8 949 .cfi_offset 14, -4 950 .loc 1 896 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 34 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 34 951 0006 0CD1 bne .L102 @@ -2038,7 +2038,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 986 .thumb 987 .thumb_func 988 .type CyDmaTdGetConfiguration, %function - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 35 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 35 989 CyDmaTdGetConfiguration: @@ -2098,7 +2098,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 998 .loc 1 953 0 999 0004 10B5 push {r4, lr} 1000 .LCFI7: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 36 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 36 1001 .cfi_def_cfa_offset 8 @@ -2158,7 +2158,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1034 .loc 1 977 0 1035 002e C000 lsls r0, r0, #3 1036 .LVL100: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 37 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 37 1037 0030 00F18042 add r2, r0, #1073741824 @@ -2218,7 +2218,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1005:.\Generated_Source\PSoC5/CyDmac.c **** * Return: 1006:.\Generated_Source\PSoC5/CyDmac.c **** * CYRET_SUCCESS if successful. 1007:.\Generated_Source\PSoC5/CyDmac.c **** * CYRET_BAD_PARAM if tdHandle is invalid. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 38 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 38 1008:.\Generated_Source\PSoC5/CyDmac.c **** * @@ -2278,7 +2278,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1094 0018 7047 bx lr 1095 .cfi_endproc 1096 .LFE21: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 39 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 39 1097 .size CyDmaTdSetAddress, .-CyDmaTdSetAddress @@ -2338,7 +2338,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1066:.\Generated_Source\PSoC5/CyDmac.c **** if(NULL != source) 1115 .loc 1 1066 0 1116 0004 31B1 cbz r1, .L121 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 40 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 40 1067:.\Generated_Source\PSoC5/CyDmac.c **** { @@ -2398,7 +2398,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1155 .align 1 1156 .global CyDmaChRoundRobin 1157 .thumb - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 41 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 41 1158 .thumb_func @@ -2458,7 +2458,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1176 000a D05C ldrb r0, [r2, r3] @ zero_extendqisi2 1177 .LVL123: 1178 000c 40F01001 orr r1, r0, #16 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 42 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 42 1179 .LVL124: @@ -2518,7 +2518,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1220 .set .LANCHOR1,. + 0 1221 .type CyDmaChannels, %object 1222 .size CyDmaChannels, 4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 43 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 43 1223 CyDmaChannels: @@ -2535,10 +2535,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1234 0006 00000000 .4byte .Ldebug_abbrev0 1235 000a 04 .byte 0x4 1236 000b 01 .uleb128 0x1 - 1237 000c FA020000 .4byte .LASF85 + 1237 000c 0B030000 .4byte .LASF85 1238 0010 01 .byte 0x1 - 1239 0011 CE010000 .4byte .LASF86 - 1240 0015 4A010000 .4byte .LASF87 + 1239 0011 AE010000 .4byte .LASF86 + 1240 0015 5E020000 .4byte .LASF87 1241 0019 18000000 .4byte .Ldebug_ranges0+0x18 1242 001d 00000000 .4byte 0 1243 0021 00000000 .4byte 0 @@ -2550,15 +2550,15 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1249 0030 02 .uleb128 0x2 1250 0031 01 .byte 0x1 1251 0032 08 .byte 0x8 - 1252 0033 83030000 .4byte .LASF1 + 1252 0033 94030000 .4byte .LASF1 1253 0037 02 .uleb128 0x2 1254 0038 02 .byte 0x2 1255 0039 05 .byte 0x5 - 1256 003a 91030000 .4byte .LASF2 + 1256 003a A2030000 .4byte .LASF2 1257 003e 02 .uleb128 0x2 1258 003f 02 .byte 0x2 1259 0040 07 .byte 0x7 - 1260 0041 29020000 .4byte .LASF3 + 1260 0041 09020000 .4byte .LASF3 1261 0045 02 .uleb128 0x2 1262 0046 04 .byte 0x4 1263 0047 05 .byte 0x5 @@ -2566,7 +2566,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1265 004c 02 .uleb128 0x2 1266 004d 04 .byte 0x4 1267 004e 07 .byte 0x7 - 1268 004f A9010000 .4byte .LASF5 + 1268 004f 89010000 .4byte .LASF5 1269 0053 02 .uleb128 0x2 1270 0054 08 .byte 0x8 1271 0055 05 .byte 0x5 @@ -2578,14 +2578,14 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1277 0061 03 .uleb128 0x3 1278 0062 04 .byte 0x4 1279 0063 05 .byte 0x5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 44 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 44 1280 0064 696E7400 .ascii "int\000" 1281 0068 02 .uleb128 0x2 1282 0069 04 .byte 0x4 1283 006a 07 .byte 0x7 - 1284 006b 9C010000 .4byte .LASF8 + 1284 006b 7C010000 .4byte .LASF8 1285 006f 04 .uleb128 0x4 1286 0070 28010000 .4byte .LASF9 1287 0074 02 .byte 0x2 @@ -2604,7 +2604,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1300 0090 02 .uleb128 0x2 1301 0091 04 .byte 0x4 1302 0092 04 .byte 0x4 - 1303 0093 EE020000 .4byte .LASF12 + 1303 0093 FF020000 .4byte .LASF12 1304 0097 02 .uleb128 0x2 1305 0098 08 .byte 0x8 1306 0099 04 .byte 0x4 @@ -2612,9 +2612,9 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1308 009e 02 .uleb128 0x2 1309 009f 01 .byte 0x1 1310 00a0 08 .byte 0x8 - 1311 00a1 E7030000 .4byte .LASF14 + 1311 00a1 F8030000 .4byte .LASF14 1312 00a5 04 .uleb128 0x4 - 1313 00a6 A4040000 .4byte .LASF15 + 1313 00a6 B5040000 .4byte .LASF15 1314 00aa 02 .byte 0x2 1315 00ab E8 .byte 0xe8 1316 00ac 4C000000 .4byte 0x4c @@ -2626,7 +2626,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1322 00bb 05 .uleb128 0x5 1323 00bc 7A000000 .4byte 0x7a 1324 00c0 04 .uleb128 0x4 - 1325 00c1 7E020000 .4byte .LASF17 + 1325 00c1 8F020000 .4byte .LASF17 1326 00c5 02 .byte 0x2 1327 00c6 F2 .byte 0xf2 1328 00c7 CB000000 .4byte 0xcb @@ -2635,10 +2635,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1331 00d0 02 .uleb128 0x2 1332 00d1 04 .byte 0x4 1333 00d2 07 .byte 0x7 - 1334 00d3 98020000 .4byte .LASF18 + 1334 00d3 A9020000 .4byte .LASF18 1335 00d7 06 .uleb128 0x6 - 1336 00d8 74030000 .4byte .LASF24 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 45 + 1336 00d8 85030000 .4byte .LASF24 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 45 1337 00dc 10 .byte 0x10 @@ -2646,7 +2646,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1339 00de 48 .byte 0x48 1340 00df 1C010000 .4byte 0x11c 1341 00e3 07 .uleb128 0x7 - 1342 00e4 1F020000 .4byte .LASF19 + 1342 00e4 FF010000 .4byte .LASF19 1343 00e8 03 .byte 0x3 1344 00e9 4A .byte 0x4a 1345 00ea 2C010000 .4byte 0x12c @@ -2654,7 +2654,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1347 00ef 23 .byte 0x23 1348 00f0 00 .uleb128 0 1349 00f1 07 .uleb128 0x7 - 1350 00f2 6A010000 .4byte .LASF20 + 1350 00f2 4A010000 .4byte .LASF20 1351 00f6 03 .byte 0x3 1352 00f7 4B .byte 0x4b 1353 00f8 31010000 .4byte 0x131 @@ -2662,7 +2662,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1355 00fd 23 .byte 0x23 1356 00fe 04 .uleb128 0x4 1357 00ff 07 .uleb128 0x7 - 1358 0100 8B020000 .4byte .LASF21 + 1358 0100 9C020000 .4byte .LASF21 1359 0104 03 .byte 0x3 1360 0105 4C .byte 0x4c 1361 0106 36010000 .4byte 0x136 @@ -2670,7 +2670,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1363 010b 23 .byte 0x23 1364 010c 08 .uleb128 0x8 1365 010d 07 .uleb128 0x7 - 1366 010e 71010000 .4byte .LASF22 + 1366 010e 51010000 .4byte .LASF22 1367 0112 03 .byte 0x3 1368 0113 4D .byte 0x4d 1369 0114 3B010000 .4byte 0x13b @@ -2694,21 +2694,21 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1387 013b 05 .uleb128 0x5 1388 013c 1C010000 .4byte 0x11c 1389 0140 04 .uleb128 0x4 - 1390 0141 07040000 .4byte .LASF23 + 1390 0141 18040000 .4byte .LASF23 1391 0145 03 .byte 0x3 1392 0146 4F .byte 0x4f 1393 0147 D7000000 .4byte 0xd7 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 46 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 46 1394 014b 06 .uleb128 0x6 - 1395 014c BB010000 .4byte .LASF25 + 1395 014c 9B010000 .4byte .LASF25 1396 0150 08 .byte 0x8 1397 0151 03 .byte 0x3 1398 0152 52 .byte 0x52 1399 0153 74010000 .4byte 0x174 1400 0157 07 .uleb128 0x7 - 1401 0158 65040000 .4byte .LASF26 + 1401 0158 76040000 .4byte .LASF26 1402 015c 03 .byte 0x3 1403 015d 54 .byte 0x54 1404 015e 74010000 .4byte 0x174 @@ -2716,7 +2716,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1406 0163 23 .byte 0x23 1407 0164 00 .uleb128 0 1408 0165 07 .uleb128 0x7 - 1409 0166 6A040000 .4byte .LASF27 + 1409 0166 7B040000 .4byte .LASF27 1410 016a 03 .byte 0x3 1411 016b 55 .byte 0x55 1412 016c 79010000 .4byte 0x179 @@ -2758,13 +2758,13 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1448 01b1 00 .byte 0 1449 01b2 05 .uleb128 0x5 1450 01b3 1C010000 .4byte 0x11c - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 47 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 47 1451 01b7 05 .uleb128 0x5 1452 01b8 1C010000 .4byte 0x11c 1453 01bc 04 .uleb128 0x4 - 1454 01bd 33040000 .4byte .LASF30 + 1454 01bd 44040000 .4byte .LASF30 1455 01c1 03 .byte 0x3 1456 01c2 5F .byte 0x5f 1457 01c3 89010000 .4byte 0x189 @@ -2782,7 +2782,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1469 01db 01 .byte 0x1 1470 01dc F0010000 .4byte 0x1f0 1471 01e0 0C .uleb128 0xc - 1472 01e1 C5020000 .4byte .LASF35 + 1472 01e1 D6020000 .4byte .LASF35 1473 01e5 01 .byte 0x1 1474 01e6 3F .byte 0x3f 1475 01e7 6F000000 .4byte 0x6f @@ -2790,7 +2790,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1477 01ef 00 .byte 0 1478 01f0 0D .uleb128 0xd 1479 01f1 01 .byte 0x1 - 1480 01f2 4A020000 .4byte .LASF33 + 1480 01f2 2A020000 .4byte .LASF33 1481 01f6 01 .byte 0x1 1482 01f7 6D .byte 0x6d 1483 01f8 01 .byte 0x1 @@ -2803,7 +2803,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1490 0208 01 .byte 0x1 1491 0209 0B .uleb128 0xb 1492 020a 01 .byte 0x1 - 1493 020b 6D020000 .4byte .LASF32 + 1493 020b 4D020000 .4byte .LASF32 1494 020f 01 .byte 0x1 1495 0210 91 .byte 0x91 1496 0211 01 .byte 0x1 @@ -2815,10 +2815,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1502 021d 01 .byte 0x1 1503 021e 32020000 .4byte 0x232 1504 0222 0E .uleb128 0xe - 1505 0223 F4020000 .4byte .LASF40 + 1505 0223 05030000 .4byte .LASF40 1506 0227 01 .byte 0x1 1507 0228 91 .byte 0x91 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 48 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 48 1508 0229 6F000000 .4byte 0x6f @@ -2839,7 +2839,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1523 024a 01 .byte 0x1 1524 024b 0F .uleb128 0xf 1525 024c 01 .byte 0x1 - 1526 024d D0030000 .4byte .LASF38 + 1526 024d E1030000 .4byte .LASF38 1527 0251 01 .byte 0x1 1528 0252 BF .byte 0xbf 1529 0253 01 .byte 0x1 @@ -2856,13 +2856,13 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1540 0270 6F000000 .4byte 0x6f 1541 0274 56000000 .4byte .LLST3 1542 0278 0C .uleb128 0xc - 1543 0279 C5020000 .4byte .LASF35 + 1543 0279 D6020000 .4byte .LASF35 1544 027d 01 .byte 0x1 1545 027e C2 .byte 0xc2 1546 027f 6F000000 .4byte 0x6f 1547 0283 69000000 .4byte .LLST4 1548 0287 0C .uleb128 0xc - 1549 0288 AB030000 .4byte .LASF37 + 1549 0288 BC030000 .4byte .LASF37 1550 028c 01 .byte 0x1 1551 028d C3 .byte 0xc3 1552 028e 85000000 .4byte 0x85 @@ -2876,9 +2876,9 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1560 02a8 00 .byte 0 1561 02a9 0F .uleb128 0xf 1562 02aa 01 .byte 0x1 - 1563 02ab CD040000 .4byte .LASF39 + 1563 02ab DE040000 .4byte .LASF39 1564 02af 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 49 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 49 1565 02b0 F2 .byte 0xf2 @@ -2890,13 +2890,13 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1571 02c2 01 .byte 0x1 1572 02c3 07030000 .4byte 0x307 1573 02c7 0E .uleb128 0xe - 1574 02c8 A2030000 .4byte .LASF41 + 1574 02c8 B3030000 .4byte .LASF41 1575 02cc 01 .byte 0x1 1576 02cd F2 .byte 0xf2 1577 02ce 6F000000 .4byte 0x6f 1578 02d2 C7000000 .4byte .LLST7 1579 02d6 0C .uleb128 0xc - 1580 02d7 6F040000 .4byte .LASF42 + 1580 02d7 80040000 .4byte .LASF42 1581 02db 01 .byte 0x1 1582 02dc F4 .byte 0xf4 1583 02dd A5000000 .4byte 0xa5 @@ -2929,22 +2929,22 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1610 0320 01 .byte 0x1 1611 0321 56030000 .4byte 0x356 1612 0325 12 .uleb128 0x12 - 1613 0326 A2030000 .4byte .LASF41 + 1613 0326 B3030000 .4byte .LASF41 1614 032a 01 .byte 0x1 1615 032b 3001 .2byte 0x130 1616 032d 6F000000 .4byte 0x6f 1617 0331 4B010000 .4byte .LLST10 1618 0335 12 .uleb128 0x12 - 1619 0336 1F040000 .4byte .LASF44 + 1619 0336 30040000 .4byte .LASF44 1620 033a 01 .byte 0x1 1621 033b 3001 .2byte 0x130 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 50 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 50 1622 033d 6F000000 .4byte 0x6f 1623 0341 85010000 .4byte .LLST11 1624 0345 13 .uleb128 0x13 - 1625 0346 6F040000 .4byte .LASF42 + 1625 0346 80040000 .4byte .LASF42 1626 034a 01 .byte 0x1 1627 034b 3201 .2byte 0x132 1628 034d A5000000 .4byte 0xa5 @@ -2952,7 +2952,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1630 0355 00 .byte 0 1631 0356 11 .uleb128 0x11 1632 0357 01 .byte 0x1 - 1633 0358 C1030000 .4byte .LASF45 + 1633 0358 D2030000 .4byte .LASF45 1634 035c 01 .byte 0x1 1635 035d 6201 .2byte 0x162 1636 035f 01 .byte 0x1 @@ -2965,13 +2965,13 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1643 036f 01 .byte 0x1 1644 0370 95030000 .4byte 0x395 1645 0374 12 .uleb128 0x12 - 1646 0375 A2030000 .4byte .LASF41 + 1646 0375 B3030000 .4byte .LASF41 1647 0379 01 .byte 0x1 1648 037a 6201 .2byte 0x162 1649 037c 6F000000 .4byte 0x6f 1650 0380 01020000 .4byte .LLST13 1651 0384 13 .uleb128 0x13 - 1652 0385 6F040000 .4byte .LASF42 + 1652 0385 80040000 .4byte .LASF42 1653 0389 01 .byte 0x1 1654 038a 6401 .2byte 0x164 1655 038c A5000000 .4byte 0xa5 @@ -2979,7 +2979,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1657 0394 00 .byte 0 1658 0395 11 .uleb128 0x11 1659 0396 01 .byte 0x1 - 1660 0397 CE020000 .4byte .LASF46 + 1660 0397 DF020000 .4byte .LASF46 1661 039b 01 .byte 0x1 1662 039c 8901 .2byte 0x189 1663 039e 01 .byte 0x1 @@ -2992,16 +2992,16 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1670 03ae 01 .byte 0x1 1671 03af D4030000 .4byte 0x3d4 1672 03b3 12 .uleb128 0x12 - 1673 03b4 A2030000 .4byte .LASF41 + 1673 03b4 B3030000 .4byte .LASF41 1674 03b8 01 .byte 0x1 1675 03b9 8901 .2byte 0x189 1676 03bb 6F000000 .4byte 0x6f 1677 03bf 72020000 .4byte .LLST15 1678 03c3 13 .uleb128 0x13 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 51 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 51 - 1679 03c4 6F040000 .4byte .LASF42 + 1679 03c4 80040000 .4byte .LASF42 1680 03c8 01 .byte 0x1 1681 03c9 8B01 .2byte 0x18b 1682 03cb A5000000 .4byte 0xa5 @@ -3009,7 +3009,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1684 03d3 00 .byte 0 1685 03d4 11 .uleb128 0x11 1686 03d5 01 .byte 0x1 - 1687 03d6 8C010000 .4byte .LASF47 + 1687 03d6 6C010000 .4byte .LASF47 1688 03da 01 .byte 0x1 1689 03db AD01 .2byte 0x1ad 1690 03dd 01 .byte 0x1 @@ -3022,25 +3022,25 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1697 03ed 01 .byte 0x1 1698 03ee 33040000 .4byte 0x433 1699 03f2 12 .uleb128 0x12 - 1700 03f3 A2030000 .4byte .LASF41 + 1700 03f3 B3030000 .4byte .LASF41 1701 03f7 01 .byte 0x1 1702 03f8 AD01 .2byte 0x1ad 1703 03fa 6F000000 .4byte 0x6f 1704 03fe E3020000 .4byte .LLST17 1705 0402 12 .uleb128 0x12 - 1706 0403 EC030000 .4byte .LASF48 + 1706 0403 FD030000 .4byte .LASF48 1707 0407 01 .byte 0x1 1708 0408 AD01 .2byte 0x1ad 1709 040a 6F000000 .4byte 0x6f 1710 040e 1D030000 .4byte .LLST18 1711 0412 13 .uleb128 0x13 - 1712 0413 7A010000 .4byte .LASF49 + 1712 0413 5A010000 .4byte .LASF49 1713 0417 01 .byte 0x1 1714 0418 AF01 .2byte 0x1af 1715 041a 6F000000 .4byte 0x6f 1716 041e 49030000 .4byte .LLST19 1717 0422 13 .uleb128 0x13 - 1718 0423 6F040000 .4byte .LASF42 + 1718 0423 80040000 .4byte .LASF42 1719 0427 01 .byte 0x1 1720 0428 B001 .2byte 0x1b0 1721 042a A5000000 .4byte 0xa5 @@ -3048,7 +3048,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1723 0432 00 .byte 0 1724 0433 11 .uleb128 0x11 1725 0434 01 .byte 0x1 - 1726 0435 F0010000 .4byte .LASF50 + 1726 0435 D0010000 .4byte .LASF50 1727 0439 01 .byte 0x1 1728 043a D601 .2byte 0x1d6 1729 043c 01 .byte 0x1 @@ -3058,37 +3058,37 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1733 0449 02 .byte 0x2 1734 044a 7D .byte 0x7d 1735 044b 00 .sleb128 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 52 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 52 1736 044c 01 .byte 0x1 1737 044d A2040000 .4byte 0x4a2 1738 0451 12 .uleb128 0x12 - 1739 0452 A2030000 .4byte .LASF41 + 1739 0452 B3030000 .4byte .LASF41 1740 0456 01 .byte 0x1 1741 0457 D601 .2byte 0x1d6 1742 0459 6F000000 .4byte 0x6f 1743 045d 98030000 .4byte .LLST21 1744 0461 12 .uleb128 0x12 - 1745 0462 84020000 .4byte .LASF51 + 1745 0462 95020000 .4byte .LASF51 1746 0466 01 .byte 0x1 1747 0467 D601 .2byte 0x1d6 1748 0469 7A000000 .4byte 0x7a 1749 046d D2030000 .4byte .LLST22 1750 0471 12 .uleb128 0x12 - 1751 0472 80010000 .4byte .LASF52 + 1751 0472 60010000 .4byte .LASF52 1752 0476 01 .byte 0x1 1753 0477 D601 .2byte 0x1d6 1754 0479 7A000000 .4byte 0x7a 1755 047d E5030000 .4byte .LLST23 1756 0481 13 .uleb128 0x13 - 1757 0482 6F040000 .4byte .LASF42 + 1757 0482 80040000 .4byte .LASF42 1758 0486 01 .byte 0x1 1759 0487 D901 .2byte 0x1d9 1760 0489 A5000000 .4byte 0xa5 1761 048d F8030000 .4byte .LLST24 1762 0491 13 .uleb128 0x13 - 1763 0492 2B040000 .4byte .LASF53 + 1763 0492 3C040000 .4byte .LASF53 1764 0496 01 .byte 0x1 1765 0497 DA01 .2byte 0x1da 1766 0499 A2040000 .4byte 0x4a2 @@ -3099,7 +3099,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1771 04a4 B0000000 .4byte 0xb0 1772 04a8 11 .uleb128 0x11 1773 04a9 01 .byte 0x1 - 1774 04aa 90040000 .4byte .LASF54 + 1774 04aa A1040000 .4byte .LASF54 1775 04ae 01 .byte 0x1 1776 04af 1102 .2byte 0x211 1777 04b1 01 .byte 0x1 @@ -3112,23 +3112,23 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1784 04c1 01 .byte 0x1 1785 04c2 F5040000 .4byte 0x4f5 1786 04c6 12 .uleb128 0x12 - 1787 04c7 A2030000 .4byte .LASF41 + 1787 04c7 B3030000 .4byte .LASF41 1788 04cb 01 .byte 0x1 1789 04cc 1102 .2byte 0x211 1790 04ce 6F000000 .4byte 0x6f 1791 04d2 60040000 .4byte .LLST26 1792 04d6 15 .uleb128 0x15 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 53 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 53 - 1793 04d7 3E040000 .4byte .LASF55 + 1793 04d7 4F040000 .4byte .LASF55 1794 04db 01 .byte 0x1 1795 04dc 1102 .2byte 0x211 1796 04de 6F000000 .4byte 0x6f 1797 04e2 01 .byte 0x1 1798 04e3 51 .byte 0x51 1799 04e4 13 .uleb128 0x13 - 1800 04e5 6F040000 .4byte .LASF42 + 1800 04e5 80040000 .4byte .LASF42 1801 04e9 01 .byte 0x1 1802 04ea 1302 .2byte 0x213 1803 04ec A5000000 .4byte 0xa5 @@ -3136,7 +3136,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1805 04f4 00 .byte 0 1806 04f5 11 .uleb128 0x11 1807 04f6 01 .byte 0x1 - 1808 04f7 62030000 .4byte .LASF56 + 1808 04f7 73030000 .4byte .LASF56 1809 04fb 01 .byte 0x1 1810 04fc 3702 .2byte 0x237 1811 04fe 01 .byte 0x1 @@ -3149,19 +3149,19 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1818 050e 01 .byte 0x1 1819 050f 44050000 .4byte 0x544 1820 0513 12 .uleb128 0x12 - 1821 0514 A2030000 .4byte .LASF41 + 1821 0514 B3030000 .4byte .LASF41 1822 0518 01 .byte 0x1 1823 0519 3702 .2byte 0x237 1824 051b 6F000000 .4byte 0x6f 1825 051f D1040000 .4byte .LLST28 1826 0523 12 .uleb128 0x12 - 1827 0524 88040000 .4byte .LASF57 + 1827 0524 99040000 .4byte .LASF57 1828 0528 01 .byte 0x1 1829 0529 3702 .2byte 0x237 1830 052b 6F000000 .4byte 0x6f 1831 052f 0B050000 .4byte .LLST29 1832 0533 13 .uleb128 0x13 - 1833 0534 6F040000 .4byte .LASF42 + 1833 0534 80040000 .4byte .LASF42 1834 0538 01 .byte 0x1 1835 0539 3902 .2byte 0x239 1836 053b A5000000 .4byte 0xa5 @@ -3169,7 +3169,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1838 0543 00 .byte 0 1839 0544 11 .uleb128 0x11 1840 0545 01 .byte 0x1 - 1841 0546 76040000 .4byte .LASF58 + 1841 0546 87040000 .4byte .LASF58 1842 054a 01 .byte 0x1 1843 054b 5802 .2byte 0x258 1844 054d 01 .byte 0x1 @@ -3178,20 +3178,20 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1847 0556 1C000000 .4byte .LFE13 1848 055a 02 .byte 0x2 1849 055b 7D .byte 0x7d - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 54 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 54 1850 055c 00 .sleb128 0 1851 055d 01 .byte 0x1 1852 055e 83050000 .4byte 0x583 1853 0562 12 .uleb128 0x12 - 1854 0563 A2030000 .4byte .LASF41 + 1854 0563 B3030000 .4byte .LASF41 1855 0567 01 .byte 0x1 1856 0568 5802 .2byte 0x258 1857 056a 6F000000 .4byte 0x6f 1858 056e 6E050000 .4byte .LLST31 1859 0572 13 .uleb128 0x13 - 1860 0573 6F040000 .4byte .LASF42 + 1860 0573 80040000 .4byte .LASF42 1861 0577 01 .byte 0x1 1862 0578 5A02 .2byte 0x25a 1863 057a A5000000 .4byte 0xa5 @@ -3199,7 +3199,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1865 0582 00 .byte 0 1866 0583 16 .uleb128 0x16 1867 0584 01 .byte 0x1 - 1868 0585 B3030000 .4byte .LASF59 + 1868 0585 C4030000 .4byte .LASF59 1869 0589 01 .byte 0x1 1870 058a 8A02 .2byte 0x28a 1871 058c 01 .byte 0x1 @@ -3210,13 +3210,13 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1876 059d 01 .byte 0x1 1877 059e DE050000 .4byte 0x5de 1878 05a2 12 .uleb128 0x12 - 1879 05a3 A2030000 .4byte .LASF41 + 1879 05a3 B3030000 .4byte .LASF41 1880 05a7 01 .byte 0x1 1881 05a8 8A02 .2byte 0x28a 1882 05aa 6F000000 .4byte 0x6f 1883 05ae 00060000 .4byte .LLST34 1884 05b2 12 .uleb128 0x12 - 1885 05b3 DD030000 .4byte .LASF60 + 1885 05b3 EE030000 .4byte .LASF60 1886 05b7 01 .byte 0x1 1887 05b8 8A02 .2byte 0x28a 1888 05ba DE050000 .4byte 0x5de @@ -3229,7 +3229,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1895 05ce 01 .byte 0x1 1896 05cf 52 .byte 0x52 1897 05d0 17 .uleb128 0x17 - 1898 05d1 6F040000 .4byte .LASF42 + 1898 05d1 80040000 .4byte .LASF42 1899 05d5 01 .byte 0x1 1900 05d6 8C02 .2byte 0x28c 1901 05d8 A5000000 .4byte 0xa5 @@ -3238,12 +3238,12 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1904 05de 14 .uleb128 0x14 1905 05df 04 .byte 0x4 1906 05e0 6F000000 .4byte 0x6f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 55 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 55 1907 05e4 16 .uleb128 0x16 1908 05e5 01 .byte 0x1 - 1909 05e6 AD040000 .4byte .LASF62 + 1909 05e6 BE040000 .4byte .LASF62 1910 05ea 01 .byte 0x1 1911 05eb CC02 .2byte 0x2cc 1912 05ed 01 .byte 0x1 @@ -3254,19 +3254,19 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1917 05fe 01 .byte 0x1 1918 05ff 72060000 .4byte 0x672 1919 0603 12 .uleb128 0x12 - 1920 0604 A2030000 .4byte .LASF41 + 1920 0604 B3030000 .4byte .LASF41 1921 0608 01 .byte 0x1 1922 0609 CC02 .2byte 0x2cc 1923 060b 6F000000 .4byte 0x6f 1924 060f 86060000 .4byte .LLST37 1925 0613 12 .uleb128 0x12 - 1926 0614 E3020000 .4byte .LASF63 + 1926 0614 F4020000 .4byte .LASF63 1927 0618 01 .byte 0x1 1928 0619 CC02 .2byte 0x2cc 1929 061b 6F000000 .4byte 0x6f 1930 061f C0060000 .4byte .LLST38 1931 0623 12 .uleb128 0x12 - 1932 0624 0F040000 .4byte .LASF64 + 1932 0624 20040000 .4byte .LASF64 1933 0628 01 .byte 0x1 1934 0629 CC02 .2byte 0x2cc 1935 062b 6F000000 .4byte 0x6f @@ -3286,7 +3286,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1949 0650 91 .byte 0x91 1950 0651 00 .sleb128 0 1951 0652 15 .uleb128 0x15 - 1952 0653 9B030000 .4byte .LASF67 + 1952 0653 AC030000 .4byte .LASF67 1953 0657 01 .byte 0x1 1954 0658 CD02 .2byte 0x2cd 1955 065a 6F000000 .4byte 0x6f @@ -3294,11 +3294,11 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1957 065f 91 .byte 0x91 1958 0660 04 .sleb128 4 1959 0661 13 .uleb128 0x13 - 1960 0662 6F040000 .4byte .LASF42 + 1960 0662 80040000 .4byte .LASF42 1961 0666 01 .byte 0x1 1962 0667 CF02 .2byte 0x2cf 1963 0669 A5000000 .4byte 0xa5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 56 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 56 1964 066d 44070000 .4byte .LLST41 @@ -3322,7 +3322,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 1982 0699 6F000000 .4byte 0x6f 1983 069d 9B070000 .4byte .LLST43 1984 06a1 13 .uleb128 0x13 - 1985 06a2 C5040000 .4byte .LASF69 + 1985 06a2 D6040000 .4byte .LASF69 1986 06a6 01 .byte 0x1 1987 06a7 F302 .2byte 0x2f3 1988 06a9 6F000000 .4byte 0x6f @@ -3358,7 +3358,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 2018 06f9 01 .byte 0x1 2019 06fa 1F03 .2byte 0x31f 2020 06fc 6F000000 .4byte 0x6f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 57 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 57 2021 0700 36080000 .4byte .LLST47 @@ -3403,22 +3403,22 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 2060 075a 6F000000 .4byte 0x6f 2061 075e 69080000 .4byte .LLST49 2062 0762 15 .uleb128 0x15 - 2063 0763 57040000 .4byte .LASF74 + 2063 0763 68040000 .4byte .LASF74 2064 0767 01 .byte 0x1 2065 0768 7B03 .2byte 0x37b 2066 076a 7A000000 .4byte 0x7a 2067 076e 01 .byte 0x1 2068 076f 51 .byte 0x51 2069 0770 15 .uleb128 0x15 - 2070 0771 5B030000 .4byte .LASF75 + 2070 0771 6C030000 .4byte .LASF75 2071 0775 01 .byte 0x1 2072 0776 7B03 .2byte 0x37b 2073 0778 6F000000 .4byte 0x6f 2074 077c 01 .byte 0x1 2075 077d 52 .byte 0x52 2076 077e 15 .uleb128 0x15 - 2077 077f 3C020000 .4byte .LASF76 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 58 + 2077 077f 1C020000 .4byte .LASF76 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 58 2078 0783 01 .byte 0x1 @@ -3427,7 +3427,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 2081 078a 01 .byte 0x1 2082 078b 53 .byte 0x53 2083 078c 13 .uleb128 0x13 - 2084 078d 6F040000 .4byte .LASF42 + 2084 078d 80040000 .4byte .LASF42 2085 0791 01 .byte 0x1 2086 0792 7E03 .2byte 0x37e 2087 0794 A5000000 .4byte 0xa5 @@ -3436,7 +3436,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 2090 079d 0E000000 .4byte .LBB4 2091 07a1 22000000 .4byte .LBE4 2092 07a5 13 .uleb128 0x13 - 2093 07a6 2B040000 .4byte .LASF53 + 2093 07a6 3C040000 .4byte .LASF53 2094 07aa 01 .byte 0x1 2095 07ab 8303 .2byte 0x383 2096 07ad A2040000 .4byte 0x4a2 @@ -3445,7 +3445,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 2099 07b6 00 .byte 0 2100 07b7 16 .uleb128 0x16 2101 07b8 01 .byte 0x1 - 2102 07b9 43030000 .4byte .LASF77 + 2102 07b9 54030000 .4byte .LASF77 2103 07bd 01 .byte 0x1 2104 07be B703 .2byte 0x3b7 2105 07c0 01 .byte 0x1 @@ -3462,29 +3462,29 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 2116 07de 6F000000 .4byte 0x6f 2117 07e2 0D090000 .4byte .LLST53 2118 07e6 12 .uleb128 0x12 - 2119 07e7 57040000 .4byte .LASF74 + 2119 07e7 68040000 .4byte .LASF74 2120 07eb 01 .byte 0x1 2121 07ec B703 .2byte 0x3b7 2122 07ee 3C080000 .4byte 0x83c 2123 07f2 47090000 .4byte .LLST54 2124 07f6 12 .uleb128 0x12 - 2125 07f7 5B030000 .4byte .LASF75 + 2125 07f7 6C030000 .4byte .LASF75 2126 07fb 01 .byte 0x1 2127 07fc B703 .2byte 0x3b7 2128 07fe DE050000 .4byte 0x5de 2129 0802 73090000 .4byte .LLST55 2130 0806 15 .uleb128 0x15 - 2131 0807 3C020000 .4byte .LASF76 + 2131 0807 1C020000 .4byte .LASF76 2132 080b 01 .byte 0x1 2133 080c B703 .2byte 0x3b7 2134 080e DE050000 .4byte 0x5de - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 59 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 59 2135 0812 01 .byte 0x1 2136 0813 53 .byte 0x53 2137 0814 17 .uleb128 0x17 - 2138 0815 6F040000 .4byte .LASF42 + 2138 0815 80040000 .4byte .LASF42 2139 0819 01 .byte 0x1 2140 081a BA03 .2byte 0x3ba 2141 081c A5000000 .4byte 0xa5 @@ -3493,7 +3493,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 2144 0822 0A000000 .4byte .LBB5 2145 0826 1C000000 .4byte .LBE5 2146 082a 13 .uleb128 0x13 - 2147 082b 2B040000 .4byte .LASF53 + 2147 082b 3C040000 .4byte .LASF53 2148 082f 01 .byte 0x1 2149 0830 C203 .2byte 0x3c2 2150 0832 A2040000 .4byte 0x4a2 @@ -3505,7 +3505,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 2156 083e 7A000000 .4byte 0x7a 2157 0842 11 .uleb128 0x11 2158 0843 01 .byte 0x1 - 2159 0844 B3020000 .4byte .LASF78 + 2159 0844 C4020000 .4byte .LASF78 2160 0848 01 .byte 0x1 2161 0849 F203 .2byte 0x3f2 2162 084b 01 .byte 0x1 @@ -3524,30 +3524,30 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 2175 0868 6F000000 .4byte 0x6f 2176 086c C7090000 .4byte .LLST57 2177 0870 15 .uleb128 0x15 - 2178 0871 84020000 .4byte .LASF51 + 2178 0871 95020000 .4byte .LASF51 2179 0875 01 .byte 0x1 2180 0876 F203 .2byte 0x3f2 2181 0878 7A000000 .4byte 0x7a 2182 087c 01 .byte 0x1 2183 087d 51 .byte 0x51 2184 087e 15 .uleb128 0x15 - 2185 087f 80010000 .4byte .LASF52 + 2185 087f 60010000 .4byte .LASF52 2186 0883 01 .byte 0x1 2187 0884 F203 .2byte 0x3f2 2188 0886 7A000000 .4byte 0x7a 2189 088a 01 .byte 0x1 2190 088b 52 .byte 0x52 2191 088c 13 .uleb128 0x13 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 60 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 60 - 2192 088d 6F040000 .4byte .LASF42 + 2192 088d 80040000 .4byte .LASF42 2193 0891 01 .byte 0x1 2194 0892 F403 .2byte 0x3f4 2195 0894 A5000000 .4byte 0xa5 2196 0898 010A0000 .4byte .LLST58 2197 089c 13 .uleb128 0x13 - 2198 089d 2B040000 .4byte .LASF53 + 2198 089d 3C040000 .4byte .LASF53 2199 08a1 01 .byte 0x1 2200 08a2 F503 .2byte 0x3f5 2201 08a4 A2040000 .4byte 0x4a2 @@ -3555,7 +3555,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 2203 08ac 00 .byte 0 2204 08ad 11 .uleb128 0x11 2205 08ae 01 .byte 0x1 - 2206 08af F5030000 .4byte .LASF79 + 2206 08af 06040000 .4byte .LASF79 2207 08b3 01 .byte 0x1 2208 08b4 2204 .2byte 0x422 2209 08b6 01 .byte 0x1 @@ -3574,37 +3574,37 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 2222 08d3 6F000000 .4byte 0x6f 2223 08d7 690A0000 .4byte .LLST60 2224 08db 12 .uleb128 0x12 - 2225 08dc 84020000 .4byte .LASF51 + 2225 08dc 95020000 .4byte .LASF51 2226 08e0 01 .byte 0x1 2227 08e1 2204 .2byte 0x422 2228 08e3 3C080000 .4byte 0x83c 2229 08e7 A30A0000 .4byte .LLST61 2230 08eb 15 .uleb128 0x15 - 2231 08ec 80010000 .4byte .LASF52 + 2231 08ec 60010000 .4byte .LASF52 2232 08f0 01 .byte 0x1 2233 08f1 2204 .2byte 0x422 2234 08f3 3C080000 .4byte 0x83c 2235 08f7 01 .byte 0x1 2236 08f8 52 .byte 0x52 2237 08f9 17 .uleb128 0x17 - 2238 08fa 6F040000 .4byte .LASF42 + 2238 08fa 80040000 .4byte .LASF42 2239 08fe 01 .byte 0x1 2240 08ff 2404 .2byte 0x424 2241 0901 A5000000 .4byte 0xa5 2242 0905 01 .byte 0x1 2243 0906 13 .uleb128 0x13 - 2244 0907 2B040000 .4byte .LASF53 + 2244 0907 3C040000 .4byte .LASF53 2245 090b 01 .byte 0x1 2246 090c 2504 .2byte 0x425 2247 090e A2040000 .4byte 0x4a2 2248 0912 CF0A0000 .4byte .LLST62 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 61 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 61 2249 0916 00 .byte 0 2250 0917 11 .uleb128 0x11 2251 0918 01 .byte 0x1 - 2252 0919 A1020000 .4byte .LASF80 + 2252 0919 B2020000 .4byte .LASF80 2253 091d 01 .byte 0x1 2254 091e 5504 .2byte 0x455 2255 0920 01 .byte 0x1 @@ -3617,7 +3617,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 2262 0930 01 .byte 0x1 2263 0931 66090000 .4byte 0x966 2264 0935 12 .uleb128 0x12 - 2265 0936 A2030000 .4byte .LASF41 + 2265 0936 B3030000 .4byte .LASF41 2266 093a 01 .byte 0x1 2267 093b 5504 .2byte 0x455 2268 093d 6F000000 .4byte 0x6f @@ -3629,14 +3629,14 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 2274 094d 6F000000 .4byte 0x6f 2275 0951 590B0000 .4byte .LLST64 2276 0955 13 .uleb128 0x13 - 2277 0956 6F040000 .4byte .LASF42 + 2277 0956 80040000 .4byte .LASF42 2278 095a 01 .byte 0x1 2279 095b 5704 .2byte 0x457 2280 095d A5000000 .4byte 0xa5 2281 0961 9E0B0000 .4byte .LLST65 2282 0965 00 .byte 0 2283 0966 1D .uleb128 0x1d - 2284 0967 0A020000 .4byte .LASF82 + 2284 0967 EA010000 .4byte .LASF82 2285 096b 01 .byte 0x1 2286 096c 28 .byte 0x28 2287 096d 6F000000 .4byte 0x6f @@ -3644,7 +3644,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 2289 0972 03 .byte 0x3 2290 0973 01000000 .4byte CyDmaTdCurrentNumber 2291 0977 1D .uleb128 0x1d - 2292 0978 46040000 .4byte .LASF83 + 2292 0978 57040000 .4byte .LASF83 2293 097c 01 .byte 0x1 2294 097d 29 .byte 0x29 2295 097e 6F000000 .4byte 0x6f @@ -3658,13 +3658,13 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 2303 098f 85000000 .4byte 0x85 2304 0993 05 .byte 0x5 2305 0994 03 .byte 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 62 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 62 2306 0995 00000000 .4byte CyDmaChannels 2307 0999 1E .uleb128 0x1e 2308 099a 01 .byte 0x1 - 2309 099b 56020000 .4byte .LASF88 + 2309 099b 36020000 .4byte .LASF88 2310 099f 04 .byte 0x4 2311 09a0 7E .byte 0x7e 2312 09a1 01 .byte 0x1 @@ -3718,7 +3718,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 2360 0020 03 .uleb128 0x3 2361 0021 24 .uleb128 0x24 2362 0022 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 63 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 63 2363 0023 0B .uleb128 0xb @@ -3778,7 +3778,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 2417 0059 38 .uleb128 0x38 2418 005a 0A .uleb128 0xa 2419 005b 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 64 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 64 2420 005c 00 .byte 0 @@ -3838,7 +3838,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 2474 0093 0C .uleb128 0xc 2475 0094 01 .uleb128 0x1 2476 0095 13 .uleb128 0x13 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 65 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 65 2477 0096 00 .byte 0 @@ -3898,7 +3898,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 2531 00cd 06 .uleb128 0x6 2532 00ce 00 .byte 0 2533 00cf 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 66 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 66 2534 00d0 0F .uleb128 0xf @@ -3958,7 +3958,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 2588 0109 01 .uleb128 0x1 2589 010a 40 .uleb128 0x40 2590 010b 0A .uleb128 0xa - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 67 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 67 2591 010c 9742 .uleb128 0x2117 @@ -4018,7 +4018,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 2645 0143 49 .uleb128 0x49 2646 0144 13 .uleb128 0x13 2647 0145 02 .uleb128 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 68 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 68 2648 0146 0A .uleb128 0xa @@ -4078,7 +4078,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 2702 017d 3B .uleb128 0x3b 2703 017e 05 .uleb128 0x5 2704 017f 27 .uleb128 0x27 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 69 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 69 2705 0180 0C .uleb128 0xc @@ -4138,7 +4138,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 2759 01bb 00 .byte 0 2760 01bc 00 .byte 0 2761 01bd 1C .uleb128 0x1c - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 70 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 70 2762 01be 0B .uleb128 0xb @@ -4198,7 +4198,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 2816 01f4 0C .uleb128 0xc 2817 01f5 3C .uleb128 0x3c 2818 01f6 0C .uleb128 0xc - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 71 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 71 2819 01f7 00 .byte 0 @@ -4258,7 +4258,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 2873 0065 00000000 .4byte 0 2874 .LLST4: 2875 0069 06000000 .4byte .LVL5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 72 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 72 2876 006d 0E000000 .4byte .LVL6 @@ -4318,7 +4318,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 2930 00f5 F3 .byte 0xf3 2931 00f6 01 .uleb128 0x1 2932 00f7 50 .byte 0x50 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 73 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 73 2933 00f8 9F .byte 0x9f @@ -4378,7 +4378,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 2987 017c 9F .byte 0x9f 2988 017d 00000000 .4byte 0 2989 0181 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 74 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 74 2990 .LLST11: @@ -4438,7 +4438,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 3044 0209 0100 .2byte 0x1 3045 020b 50 .byte 0x50 3046 020c 08000000 .4byte .LVL24 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 75 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 75 3047 0210 1C000000 .4byte .LVL26 @@ -4498,7 +4498,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 3101 028f 20000000 .4byte .LVL32 3102 0293 0100 .2byte 0x1 3103 0295 50 .byte 0x50 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 76 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 76 3104 0296 20000000 .4byte .LVL32 @@ -4558,7 +4558,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 3158 0315 00000000 .4byte 0 3159 0319 00000000 .4byte 0 3160 .LLST18: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 77 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 77 3161 031d 00000000 .4byte .LVL33 @@ -4618,7 +4618,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 3215 03a0 0100 .2byte 0x1 3216 03a2 50 .byte 0x50 3217 03a3 1A000000 .4byte .LVL44 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 78 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 78 3218 03a7 2A000000 .4byte .LVL49 @@ -4678,7 +4678,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 3272 042b 00000000 .4byte 0 3273 .LLST25: 3274 042f 22000000 .4byte .LVL45 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 79 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 79 3275 0433 24000000 .4byte .LVL46 @@ -4738,7 +4738,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 3329 04b1 9F .byte 0x9f 3330 04b2 10000000 .4byte .LVL54 3331 04b6 12000000 .4byte .LVL55 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 80 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 80 3332 04ba 0200 .2byte 0x2 @@ -4798,7 +4798,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 3386 053b 16000000 .4byte .LVL59 3387 053f 0200 .2byte 0x2 3388 0541 31 .byte 0x31 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 81 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 81 3389 0542 9F .byte 0x9f @@ -4858,7 +4858,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 3443 05c4 14000000 .4byte .LVL66 3444 05c8 0300 .2byte 0x3 3445 05ca 08 .byte 0x8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 82 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 82 3446 05cb FF .byte 0xff @@ -4918,7 +4918,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 3500 064f F3 .byte 0xf3 3501 0650 01 .uleb128 0x1 3502 0651 51 .byte 0x51 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 83 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 83 3503 0652 9F .byte 0x9f @@ -4978,7 +4978,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 3557 06d6 01 .uleb128 0x1 3558 06d7 51 .byte 0x51 3559 06d8 9F .byte 0x9f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 84 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 84 3560 06d9 3C000000 .4byte .LVL78 @@ -5038,7 +5038,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 3614 0760 3E000000 .4byte .LVL79 3615 0764 0200 .2byte 0x2 3616 0766 31 .byte 0x31 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 85 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 85 3617 0767 9F .byte 0x9f @@ -5098,7 +5098,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 3671 07f2 0200 .2byte 0x2 3672 07f4 7D .byte 0x7d 3673 07f5 00 .sleb128 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 86 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 86 3674 07f6 04000000 .4byte .LCFI5 @@ -5158,7 +5158,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 3728 087f 01 .uleb128 0x1 3729 0880 50 .byte 0x50 3730 0881 9F .byte 0x9f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 87 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 87 3731 0882 22000000 .4byte .LVL93 @@ -5218,7 +5218,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 3785 0909 00000000 .4byte 0 3786 .LLST53: 3787 090d 00000000 .4byte .LVL95 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 88 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 88 3788 0911 30000000 .4byte .LVL100 @@ -5278,7 +5278,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 3842 0990 44000000 .4byte .LFE20 3843 0994 0100 .2byte 0x1 3844 0996 52 .byte 0x52 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 89 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 89 3845 0997 00000000 .4byte 0 @@ -5338,7 +5338,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 3898 0a17 30 .byte 0x30 3899 0a18 9F .byte 0x9f 3900 0a19 16000000 .4byte .LVL110 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 90 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 90 3901 0a1d 18000000 .4byte .LVL111 @@ -5398,7 +5398,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 3955 0a9b 00000000 .4byte 0 3956 0a9f 00000000 .4byte 0 3957 .LLST61: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 91 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 91 3958 0aa3 00000000 .4byte .LVL112 @@ -5458,7 +5458,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 4011 0b1e 9F .byte 0x9f 4012 0b1f 16000000 .4byte .LVL125 4013 0b23 18000000 .4byte .LVL126 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 92 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 92 4014 0b27 0100 .2byte 0x1 @@ -5518,7 +5518,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 4068 0ba6 0200 .2byte 0x2 4069 0ba8 31 .byte 0x31 4070 0ba9 9F .byte 0x9f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 93 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 93 4071 0baa 22000000 .4byte .LVL129 @@ -5578,7 +5578,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 4125 00b0 00000000 .4byte .LFB20 4126 00b4 44000000 .4byte .LFE20-.LFB20 4127 00b8 00000000 .4byte .LFB21 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 94 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 94 4128 00bc 1A000000 .4byte .LFE21-.LFB21 @@ -5638,7 +5638,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 4182 00b4 26000000 .4byte .LFE19 4183 00b8 00000000 .4byte .LFB20 4184 00bc 44000000 .4byte .LFE20 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 95 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 95 4185 00c0 00000000 .4byte .LFB21 @@ -5698,7 +5698,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 4212 .LASF31: 4213 0077 4379446D .ascii "CyDmacConfigure\000" 4213 6163436F - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 96 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 96 4213 6E666967 @@ -5758,7 +5758,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 4237 6E653100 4238 .LASF16: 4239 0122 72656731 .ascii "reg16\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 97 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 97 4239 3600 @@ -5776,313 +5776,314 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 1 4246 .LASF11: 4247 0143 75696E74 .ascii "uint32\000" 4247 333200 - 4248 .LASF87: - 4249 014a 573A5C53 .ascii "W:\\SCSI2SD\\USB_Bootloader.cydsn\000" - 4249 43534932 - 4249 53445C55 - 4249 53425F42 - 4249 6F6F746C - 4250 .LASF20: - 4251 016a 61637469 .ascii "action\000" - 4251 6F6E00 - 4252 .LASF22: - 4253 0171 72657365 .ascii "reserved\000" - 4253 72766564 - 4253 00 - 4254 .LASF49: - 4255 017a 76616C75 .ascii "value\000" - 4255 6500 - 4256 .LASF52: - 4257 0180 64657374 .ascii "destination\000" - 4257 696E6174 - 4257 696F6E00 - 4258 .LASF47: - 4259 018c 4379446D .ascii "CyDmaChPriority\000" - 4259 61436850 - 4259 72696F72 - 4259 69747900 - 4260 .LASF8: - 4261 019c 756E7369 .ascii "unsigned int\000" - 4261 676E6564 - 4261 20696E74 - 4261 00 - 4262 .LASF5: - 4263 01a9 6C6F6E67 .ascii "long unsigned int\000" - 4263 20756E73 - 4263 69676E65 - 4263 6420696E - 4263 7400 - 4264 .LASF25: - 4265 01bb 646D6163 .ascii "dmac_cfgmem_struct\000" - 4265 5F636667 - 4265 6D656D5F - 4265 73747275 - 4265 637400 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 98 - - - 4266 .LASF86: - 4267 01ce 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\CyDmac.c\000" - 4267 6E657261 - 4267 7465645F - 4267 536F7572 - 4267 63655C50 - 4268 .LASF50: - 4269 01f0 4379446D .ascii "CyDmaChSetExtendedAddress\000" - 4269 61436853 - 4269 65744578 - 4269 74656E64 - 4269 65644164 - 4270 .LASF82: - 4271 020a 4379446D .ascii "CyDmaTdCurrentNumber\000" - 4271 61546443 - 4271 75727265 - 4271 6E744E75 - 4271 6D626572 - 4272 .LASF19: - 4273 021f 62617369 .ascii "basic_cfg\000" - 4273 635F6366 - 4273 6700 - 4274 .LASF3: - 4275 0229 73686F72 .ascii "short unsigned int\000" - 4275 7420756E - 4275 7369676E - 4275 65642069 - 4275 6E7400 - 4276 .LASF76: - 4277 023c 636F6E66 .ascii "configuration\000" - 4277 69677572 - 4277 6174696F - 4277 6E00 - 4278 .LASF33: - 4279 024a 4379446D .ascii "CyDmacError\000" - 4279 61634572 - 4279 726F7200 - 4280 .LASF88: - 4281 0256 4379456E .ascii "CyEnterCriticalSection\000" - 4281 74657243 - 4281 72697469 - 4281 63616C53 - 4281 65637469 - 4282 .LASF32: - 4283 026d 4379446D .ascii "CyDmacClearError\000" - 4283 6163436C - 4283 65617245 - 4283 72726F72 - 4283 00 - 4284 .LASF17: - 4285 027e 72656733 .ascii "reg32\000" - 4285 3200 - 4286 .LASF51: - 4287 0284 736F7572 .ascii "source\000" - 4287 636500 - 4288 .LASF21: - 4289 028b 62617369 .ascii "basic_status\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 99 - - - 4289 635F7374 - 4289 61747573 - 4289 00 - 4290 .LASF18: - 4291 0298 73697A65 .ascii "sizetype\000" - 4291 74797065 - 4291 00 - 4292 .LASF80: - 4293 02a1 4379446D .ascii "CyDmaChRoundRobin\000" - 4293 61436852 - 4293 6F756E64 - 4293 526F6269 - 4293 6E00 - 4294 .LASF78: - 4295 02b3 4379446D .ascii "CyDmaTdSetAddress\000" - 4295 61546453 - 4295 65744164 - 4295 64726573 - 4295 7300 - 4296 .LASF35: - 4297 02c5 646D6149 .ascii "dmaIndex\000" - 4297 6E646578 - 4297 00 - 4298 .LASF46: - 4299 02ce 4379446D .ascii "CyDmaClearPendingDrq\000" - 4299 61436C65 - 4299 61725065 - 4299 6E64696E - 4299 67447271 - 4300 .LASF63: - 4301 02e3 62757273 .ascii "burstCount\000" - 4301 74436F75 - 4301 6E7400 - 4302 .LASF12: - 4303 02ee 666C6F61 .ascii "float\000" - 4303 7400 - 4304 .LASF40: - 4305 02f4 6572726F .ascii "error\000" - 4305 7200 - 4306 .LASF85: - 4307 02fa 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 4307 4320342E - 4307 372E3320 - 4307 32303133 - 4307 30333132 - 4308 032d 616E6368 .ascii "anch revision 196615]\000" - 4308 20726576 - 4308 6973696F - 4308 6E203139 - 4308 36363135 - 4309 .LASF77: - 4310 0343 4379446D .ascii "CyDmaTdGetConfiguration\000" - 4310 61546447 - 4310 6574436F - 4310 6E666967 - 4310 75726174 - 4311 .LASF75: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 100 - - - 4312 035b 6E657874 .ascii "nextTd\000" - 4312 546400 - 4313 .LASF56: - 4314 0362 4379446D .ascii "CyDmaChSetRequest\000" - 4314 61436853 - 4314 65745265 - 4314 71756573 - 4314 7400 - 4315 .LASF24: - 4316 0374 646D6163 .ascii "dmac_ch_struct\000" - 4316 5F63685F - 4316 73747275 - 4316 637400 - 4317 .LASF1: - 4318 0383 756E7369 .ascii "unsigned char\000" - 4318 676E6564 - 4318 20636861 - 4318 7200 - 4319 .LASF2: - 4320 0391 73686F72 .ascii "short int\000" - 4320 7420696E - 4320 7400 - 4321 .LASF67: - 4322 039b 74645374 .ascii "tdStop\000" - 4322 6F7000 - 4323 .LASF41: - 4324 03a2 63684861 .ascii "chHandle\000" - 4324 6E646C65 - 4324 00 - 4325 .LASF37: - 4326 03ab 6368616E .ascii "channel\000" - 4326 6E656C00 - 4327 .LASF59: - 4328 03b3 4379446D .ascii "CyDmaChStatus\000" - 4328 61436853 - 4328 74617475 - 4328 7300 - 4329 .LASF45: - 4330 03c1 4379446D .ascii "CyDmaChDisable\000" - 4330 61436844 - 4330 69736162 - 4330 6C6500 - 4331 .LASF38: - 4332 03d0 4379446D .ascii "CyDmaChAlloc\000" - 4332 61436841 - 4332 6C6C6F63 - 4332 00 - 4333 .LASF60: - 4334 03dd 63757272 .ascii "currentTd\000" - 4334 656E7454 - 4334 6400 - 4335 .LASF14: - 4336 03e7 63686172 .ascii "char\000" - 4336 00 - 4337 .LASF48: - 4338 03ec 7072696F .ascii "priority\000" - 4338 72697479 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 101 - - - 4338 00 - 4339 .LASF79: - 4340 03f5 4379446D .ascii "CyDmaTdGetAddress\000" - 4340 61546447 - 4340 65744164 - 4340 64726573 - 4340 7300 - 4341 .LASF23: - 4342 0407 646D6163 .ascii "dmac_ch\000" - 4342 5F636800 - 4343 .LASF64: - 4344 040f 72657175 .ascii "requestPerBurst\000" - 4344 65737450 - 4344 65724275 - 4344 72737400 - 4345 .LASF44: - 4346 041f 70726573 .ascii "preserveTds\000" - 4346 65727665 - 4346 54647300 - 4347 .LASF53: - 4348 042b 636F6E76 .ascii "convert\000" - 4348 65727400 - 4349 .LASF30: - 4350 0433 646D6163 .ascii "dmac_tdmem\000" - 4350 5F74646D - 4350 656D00 - 4351 .LASF55: - 4352 043e 73746172 .ascii "startTd\000" - 4352 74546400 - 4353 .LASF83: - 4354 0446 4379446D .ascii "CyDmaTdFreeIndex\000" - 4354 61546446 - 4354 72656549 - 4354 6E646578 - 4354 00 - 4355 .LASF74: - 4356 0457 7472616E .ascii "transferCount\000" - 4356 73666572 - 4356 436F756E - 4356 7400 - 4357 .LASF26: - 4358 0465 43464730 .ascii "CFG0\000" - 4358 00 - 4359 .LASF27: - 4360 046a 43464731 .ascii "CFG1\000" - 4360 00 - 4361 .LASF42: - 4362 046f 73746174 .ascii "status\000" - 4362 757300 - 4363 .LASF58: - 4364 0476 4379446D .ascii "CyDmaChGetRequest\000" - 4364 61436847 - 4364 65745265 - 4364 71756573 - 4364 7400 - 4365 .LASF57: - 4366 0488 72657175 .ascii "request\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyzPvW2.s page 102 - - - 4366 65737400 - 4367 .LASF54: - 4368 0490 4379446D .ascii "CyDmaChSetInitialTd\000" - 4368 61436853 - 4368 6574496E - 4368 69746961 - 4368 6C546400 - 4369 .LASF15: - 4370 04a4 63797374 .ascii "cystatus\000" - 4370 61747573 - 4370 00 - 4371 .LASF62: - 4372 04ad 4379446D .ascii "CyDmaChSetConfiguration\000" - 4372 61436853 - 4372 6574436F - 4372 6E666967 - 4372 75726174 - 4373 .LASF69: - 4374 04c5 656C656D .ascii "element\000" - 4374 656E7400 - 4375 .LASF39: - 4376 04cd 4379446D .ascii "CyDmaChFree\000" - 4376 61436846 - 4376 72656500 - 4377 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br + 4248 .LASF20: + 4249 014a 61637469 .ascii "action\000" + 4249 6F6E00 + 4250 .LASF22: + 4251 0151 72657365 .ascii "reserved\000" + 4251 72766564 + 4251 00 + 4252 .LASF49: + 4253 015a 76616C75 .ascii "value\000" + 4253 6500 + 4254 .LASF52: + 4255 0160 64657374 .ascii "destination\000" + 4255 696E6174 + 4255 696F6E00 + 4256 .LASF47: + 4257 016c 4379446D .ascii "CyDmaChPriority\000" + 4257 61436850 + 4257 72696F72 + 4257 69747900 + 4258 .LASF8: + 4259 017c 756E7369 .ascii "unsigned int\000" + 4259 676E6564 + 4259 20696E74 + 4259 00 + 4260 .LASF5: + 4261 0189 6C6F6E67 .ascii "long unsigned int\000" + 4261 20756E73 + 4261 69676E65 + 4261 6420696E + 4261 7400 + 4262 .LASF25: + 4263 019b 646D6163 .ascii "dmac_cfgmem_struct\000" + 4263 5F636667 + 4263 6D656D5F + 4263 73747275 + 4263 637400 + 4264 .LASF86: + 4265 01ae 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\CyDmac.c\000" + 4265 6E657261 + 4265 7465645F + 4265 536F7572 + 4265 63655C50 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 98 + + + 4266 .LASF50: + 4267 01d0 4379446D .ascii "CyDmaChSetExtendedAddress\000" + 4267 61436853 + 4267 65744578 + 4267 74656E64 + 4267 65644164 + 4268 .LASF82: + 4269 01ea 4379446D .ascii "CyDmaTdCurrentNumber\000" + 4269 61546443 + 4269 75727265 + 4269 6E744E75 + 4269 6D626572 + 4270 .LASF19: + 4271 01ff 62617369 .ascii "basic_cfg\000" + 4271 635F6366 + 4271 6700 + 4272 .LASF3: + 4273 0209 73686F72 .ascii "short unsigned int\000" + 4273 7420756E + 4273 7369676E + 4273 65642069 + 4273 6E7400 + 4274 .LASF76: + 4275 021c 636F6E66 .ascii "configuration\000" + 4275 69677572 + 4275 6174696F + 4275 6E00 + 4276 .LASF33: + 4277 022a 4379446D .ascii "CyDmacError\000" + 4277 61634572 + 4277 726F7200 + 4278 .LASF88: + 4279 0236 4379456E .ascii "CyEnterCriticalSection\000" + 4279 74657243 + 4279 72697469 + 4279 63616C53 + 4279 65637469 + 4280 .LASF32: + 4281 024d 4379446D .ascii "CyDmacClearError\000" + 4281 6163436C + 4281 65617245 + 4281 72726F72 + 4281 00 + 4282 .LASF87: + 4283 025e 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" + 4283 43534932 + 4283 53445C73 + 4283 6F667477 + 4283 6172655C + 4284 028d 6E00 .ascii "n\000" + 4285 .LASF17: + 4286 028f 72656733 .ascii "reg32\000" + 4286 3200 + 4287 .LASF51: + 4288 0295 736F7572 .ascii "source\000" + 4288 636500 + 4289 .LASF21: + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 99 + + + 4290 029c 62617369 .ascii "basic_status\000" + 4290 635F7374 + 4290 61747573 + 4290 00 + 4291 .LASF18: + 4292 02a9 73697A65 .ascii "sizetype\000" + 4292 74797065 + 4292 00 + 4293 .LASF80: + 4294 02b2 4379446D .ascii "CyDmaChRoundRobin\000" + 4294 61436852 + 4294 6F756E64 + 4294 526F6269 + 4294 6E00 + 4295 .LASF78: + 4296 02c4 4379446D .ascii "CyDmaTdSetAddress\000" + 4296 61546453 + 4296 65744164 + 4296 64726573 + 4296 7300 + 4297 .LASF35: + 4298 02d6 646D6149 .ascii "dmaIndex\000" + 4298 6E646578 + 4298 00 + 4299 .LASF46: + 4300 02df 4379446D .ascii "CyDmaClearPendingDrq\000" + 4300 61436C65 + 4300 61725065 + 4300 6E64696E + 4300 67447271 + 4301 .LASF63: + 4302 02f4 62757273 .ascii "burstCount\000" + 4302 74436F75 + 4302 6E7400 + 4303 .LASF12: + 4304 02ff 666C6F61 .ascii "float\000" + 4304 7400 + 4305 .LASF40: + 4306 0305 6572726F .ascii "error\000" + 4306 7200 + 4307 .LASF85: + 4308 030b 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" + 4308 4320342E + 4308 372E3320 + 4308 32303133 + 4308 30333132 + 4309 033e 616E6368 .ascii "anch revision 196615]\000" + 4309 20726576 + 4309 6973696F + 4309 6E203139 + 4309 36363135 + 4310 .LASF77: + 4311 0354 4379446D .ascii "CyDmaTdGetConfiguration\000" + 4311 61546447 + 4311 6574436F + 4311 6E666967 + 4311 75726174 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 100 + + + 4312 .LASF75: + 4313 036c 6E657874 .ascii "nextTd\000" + 4313 546400 + 4314 .LASF56: + 4315 0373 4379446D .ascii "CyDmaChSetRequest\000" + 4315 61436853 + 4315 65745265 + 4315 71756573 + 4315 7400 + 4316 .LASF24: + 4317 0385 646D6163 .ascii "dmac_ch_struct\000" + 4317 5F63685F + 4317 73747275 + 4317 637400 + 4318 .LASF1: + 4319 0394 756E7369 .ascii "unsigned char\000" + 4319 676E6564 + 4319 20636861 + 4319 7200 + 4320 .LASF2: + 4321 03a2 73686F72 .ascii "short int\000" + 4321 7420696E + 4321 7400 + 4322 .LASF67: + 4323 03ac 74645374 .ascii "tdStop\000" + 4323 6F7000 + 4324 .LASF41: + 4325 03b3 63684861 .ascii "chHandle\000" + 4325 6E646C65 + 4325 00 + 4326 .LASF37: + 4327 03bc 6368616E .ascii "channel\000" + 4327 6E656C00 + 4328 .LASF59: + 4329 03c4 4379446D .ascii "CyDmaChStatus\000" + 4329 61436853 + 4329 74617475 + 4329 7300 + 4330 .LASF45: + 4331 03d2 4379446D .ascii "CyDmaChDisable\000" + 4331 61436844 + 4331 69736162 + 4331 6C6500 + 4332 .LASF38: + 4333 03e1 4379446D .ascii "CyDmaChAlloc\000" + 4333 61436841 + 4333 6C6C6F63 + 4333 00 + 4334 .LASF60: + 4335 03ee 63757272 .ascii "currentTd\000" + 4335 656E7454 + 4335 6400 + 4336 .LASF14: + 4337 03f8 63686172 .ascii "char\000" + 4337 00 + 4338 .LASF48: + 4339 03fd 7072696F .ascii "priority\000" + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 101 + + + 4339 72697479 + 4339 00 + 4340 .LASF79: + 4341 0406 4379446D .ascii "CyDmaTdGetAddress\000" + 4341 61546447 + 4341 65744164 + 4341 64726573 + 4341 7300 + 4342 .LASF23: + 4343 0418 646D6163 .ascii "dmac_ch\000" + 4343 5F636800 + 4344 .LASF64: + 4345 0420 72657175 .ascii "requestPerBurst\000" + 4345 65737450 + 4345 65724275 + 4345 72737400 + 4346 .LASF44: + 4347 0430 70726573 .ascii "preserveTds\000" + 4347 65727665 + 4347 54647300 + 4348 .LASF53: + 4349 043c 636F6E76 .ascii "convert\000" + 4349 65727400 + 4350 .LASF30: + 4351 0444 646D6163 .ascii "dmac_tdmem\000" + 4351 5F74646D + 4351 656D00 + 4352 .LASF55: + 4353 044f 73746172 .ascii "startTd\000" + 4353 74546400 + 4354 .LASF83: + 4355 0457 4379446D .ascii "CyDmaTdFreeIndex\000" + 4355 61546446 + 4355 72656549 + 4355 6E646578 + 4355 00 + 4356 .LASF74: + 4357 0468 7472616E .ascii "transferCount\000" + 4357 73666572 + 4357 436F756E + 4357 7400 + 4358 .LASF26: + 4359 0476 43464730 .ascii "CFG0\000" + 4359 00 + 4360 .LASF27: + 4361 047b 43464731 .ascii "CFG1\000" + 4361 00 + 4362 .LASF42: + 4363 0480 73746174 .ascii "status\000" + 4363 757300 + 4364 .LASF58: + 4365 0487 4379446D .ascii "CyDmaChGetRequest\000" + 4365 61436847 + 4365 65745265 + 4365 71756573 + 4365 7400 + 4366 .LASF57: + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 102 + + + 4367 0499 72657175 .ascii "request\000" + 4367 65737400 + 4368 .LASF54: + 4369 04a1 4379446D .ascii "CyDmaChSetInitialTd\000" + 4369 61436853 + 4369 6574496E + 4369 69746961 + 4369 6C546400 + 4370 .LASF15: + 4371 04b5 63797374 .ascii "cystatus\000" + 4371 61747573 + 4371 00 + 4372 .LASF62: + 4373 04be 4379446D .ascii "CyDmaChSetConfiguration\000" + 4373 61436853 + 4373 6574436F + 4373 6E666967 + 4373 75726174 + 4374 .LASF69: + 4375 04d6 656C656D .ascii "element\000" + 4375 656E7400 + 4376 .LASF39: + 4377 04de 4379446D .ascii "CyDmaChFree\000" + 4377 61436846 + 4377 72656500 + 4378 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyDmac.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyDmac.o index 0ac3530d267824212d21d92113d46a2e980a3cd5..16efbe71f9129df434c66450e6d591d1d40ea518 100755 GIT binary patch delta 1454 zcmX|AZD<@-6rDTs<}14^yV-0K>Z~@qrm1d>yDPMbrdDXBAJMGIR->VnRID`84{1^h zCY6AVp;l?+T3A0QG$o)AwK_;aixyF;wo)w^wMZKge^^i?wonj__uiLeVcwf_?>T4A zyEA)W3Mx}Dz7#6&H=MU35z8>(T`-KtO#H_R+Fm7Wn)ZZju5S`jwoiRixd(ak>`x8e z+%eiLW%utIL>_O?wdrm?q4CubGz_wRa{oDs8;%c+?+S4;aS~-w7Ji4c@y8V z%@B6j55roVu(P>oGJ(~*Ng%%%+{T5SuuzFp+1zhH1RlV@>^jr7(07)@FIaSPaS?yU z)PB06r*Nl}flD~<1o4m#0khmX!>tiK<#gUD#k_cTP?qXE#R82-2`5Jw7h#eVUlTSG zZ~<4jK~{8+iw-EB<~tqi zX}V4J(!=3B>2F{xxlV}BR>JhWZ*hqiJSslZ!mCid`Usi9G(1a`3yk~NN8{fXeSQ)j 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zWVtSWVHG1oa{CB9giR3+{iFQFs?!)>v}bxZ<=UbFR4Rp#=N9M`Z`cQ;f6-II2?9-A zgPLYJb{gUYn#g+r;ZSB))`F*V2| zv4m&FqvY+`eOMbm3w+i+NpWtvbChB?QK3n`2CVTr;4<$>R_HBPfgkyG@&~o~X=;v2 zyenM+|1xla-vHZeX7<8=es$xg+ysvEhfLm_?o-O)&*>fxXS*?Tvw1q_ J9nF4={sUgVeR%)? diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyLib.lst b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyLib.lst index 037ffc50..840e0b9f 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyLib.lst +++ b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyLib.lst @@ -1,4 +1,4 @@ -ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 +ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 1 1 .syntax unified @@ -58,7 +58,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 30:.\Generated_Source\PSoC5/CyLib.c **** 31:.\Generated_Source\PSoC5/CyLib.c **** 32:.\Generated_Source\PSoC5/CyLib.c **** /* Variable Vdda */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 2 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 2 33:.\Generated_Source\PSoC5/CyLib.c **** #if(CYDEV_VARIABLE_VDDA == 1) @@ -118,7 +118,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 87:.\Generated_Source\PSoC5/CyLib.c **** * 88:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ 89:.\Generated_Source\PSoC5/CyLib.c **** cystatus CyPLL_OUT_Start(uint8 wait) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 3 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 3 90:.\Generated_Source\PSoC5/CyLib.c **** { @@ -178,7 +178,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 144:.\Generated_Source\PSoC5/CyLib.c **** * Disables the PLL. 145:.\Generated_Source\PSoC5/CyLib.c **** * 146:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 4 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 4 147:.\Generated_Source\PSoC5/CyLib.c **** * None @@ -238,7 +238,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 201:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_PLL_P_REG = pDiv; 202:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_PLL_Q_REG = ((uint8)(qDiv - 1u)); 203:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_PLL_CFG1_REG = (CY_CLK_PLL_CFG1_REG & CY_CLK_PLL_CURRENT_MASK) | - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 5 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 5 204:.\Generated_Source\PSoC5/CyLib.c **** ((uint8)(((uint8)(current - 1u)) << CY_CLK_PLL_CURRENT_POSITION)); @@ -298,7 +298,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 258:.\Generated_Source\PSoC5/CyLib.c **** 259:.\Generated_Source\PSoC5/CyLib.c **** default: 260:.\Generated_Source\PSoC5/CyLib.c **** CYASSERT(0u != 0u); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 6 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 6 261:.\Generated_Source\PSoC5/CyLib.c **** break; @@ -358,7 +358,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 315:.\Generated_Source\PSoC5/CyLib.c **** while (0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT))) 316:.\Generated_Source\PSoC5/CyLib.c **** { 317:.\Generated_Source\PSoC5/CyLib.c **** /* Wait for the interrupt status */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 7 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 7 318:.\Generated_Source\PSoC5/CyLib.c **** } @@ -418,7 +418,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 372:.\Generated_Source\PSoC5/CyLib.c **** (0u != (CY_LIB_PM_ACT_CFG5_REG & CY_ACT_USB_ENABLED ))) || 373:.\Generated_Source\PSoC5/CyLib.c **** (((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ALT_ACT) && 374:.\Generated_Source\PSoC5/CyLib.c **** (0u != (CY_LIB_PM_STBY_CFG5_REG & CY_ALT_ACT_USB_ENABLED)))) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 8 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 8 375:.\Generated_Source\PSoC5/CyLib.c **** { @@ -478,7 +478,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 51 0018 012B cmp r3, #1 52 001a 05D1 bne .L15 374:.\Generated_Source\PSoC5/CyLib.c **** (0u != (CY_LIB_PM_STBY_CFG5_REG & CY_ALT_ACT_USB_ENABLED)))) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 9 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 9 53 .loc 1 374 0 @@ -538,7 +538,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 89 0042 08E0 b .L17 90 .L8: 415:.\Generated_Source\PSoC5/CyLib.c **** break; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 10 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 10 416:.\Generated_Source\PSoC5/CyLib.c **** @@ -598,7 +598,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 441:.\Generated_Source\PSoC5/CyLib.c **** 442:.\Generated_Source\PSoC5/CyLib.c **** /* If USB is powered */ 443:.\Generated_Source\PSoC5/CyLib.c **** if(usbPowerOn == 1u) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 11 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 11 120 .loc 1 443 0 @@ -658,7 +658,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 450:.\Generated_Source\PSoC5/CyLib.c **** default: 451:.\Generated_Source\PSoC5/CyLib.c **** CYASSERT(0u != 0u); 452:.\Generated_Source\PSoC5/CyLib.c **** break; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 12 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 12 453:.\Generated_Source\PSoC5/CyLib.c **** } @@ -718,7 +718,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 507:.\Generated_Source\PSoC5/CyLib.c **** nextFreq = (freq == CY_IMO_FREQ_USB) ? CY_IMO_FREQ_24MHZ : freq; 508:.\Generated_Source\PSoC5/CyLib.c **** 509:.\Generated_Source\PSoC5/CyLib.c **** switch (currentFreq) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 13 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 13 510:.\Generated_Source\PSoC5/CyLib.c **** { @@ -778,7 +778,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 564:.\Generated_Source\PSoC5/CyLib.c **** 565:.\Generated_Source\PSoC5/CyLib.c **** case CY_IMO_FREQ_12MHZ: 566:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 14 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 14 567:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_IMO_12MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); @@ -838,7 +838,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 621:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyIMO_SetSource 622:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** 623:.\Generated_Source\PSoC5/CyLib.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 15 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 15 624:.\Generated_Source\PSoC5/CyLib.c **** * Summary: @@ -898,7 +898,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 678:.\Generated_Source\PSoC5/CyLib.c **** * Enables the IMO doubler. The 2x frequency clock is used to convert a 24 MHz 679:.\Generated_Source\PSoC5/CyLib.c **** * input to a 48 MHz output for use by the USB block. 680:.\Generated_Source\PSoC5/CyLib.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 16 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 16 681:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: @@ -958,7 +958,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 735:.\Generated_Source\PSoC5/CyLib.c **** * 736:.\Generated_Source\PSoC5/CyLib.c **** * If as result of this function execution the CPU clock frequency is increased 737:.\Generated_Source\PSoC5/CyLib.c **** * then the number of clock cycles the cache will wait before it samples data - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 17 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 17 738:.\Generated_Source\PSoC5/CyLib.c **** * coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() @@ -1018,7 +1018,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 792:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: 793:.\Generated_Source\PSoC5/CyLib.c **** * divider: Valid range [0-65535]. 794:.\Generated_Source\PSoC5/CyLib.c **** * The clock will be divided by this value + 1. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 18 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 18 795:.\Generated_Source\PSoC5/CyLib.c **** * For example to divide by 2 this parameter should be set to 1. @@ -1078,7 +1078,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 816:.\Generated_Source\PSoC5/CyLib.c **** * Copy shadow value defined in Shadow Divider Value Register 817:.\Generated_Source\PSoC5/CyLib.c **** * (CY_LIB_CLKDIST_WRK_LSB_REG and CY_LIB_CLKDIST_WRK_MSB_REG) to all 818:.\Generated_Source\PSoC5/CyLib.c **** * dividers selected in Analog and Digital Clock Mask Registers - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 19 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 19 819:.\Generated_Source\PSoC5/CyLib.c **** * (CY_LIB_CLKDIST_AMASK_REG and CY_LIB_CLKDIST_DMASK_REG). @@ -1138,7 +1138,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 245 @ args = 0, pretend = 0, frame = 0 246 @ frame_needed = 0, uses_anonymous_args = 0 247 @ link register save eliminated. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 20 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 20 248 .LVL7: @@ -1198,7 +1198,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 290 .cfi_endproc 291 .LFE2: 292 .size CyPLL_OUT_SetPQ, .-CyPLL_OUT_SetPQ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 21 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 21 293 .section .text.CyPLL_OUT_SetSource,"ax",%progbits @@ -1258,7 +1258,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 341 000a 197C ldrb r1, [r3, #16] @ zero_extendqisi2 342 000c 01F0EF02 and r2, r1, #239 343 0010 1A74 strb r2, [r3, #16] - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 22 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 22 344 0012 7047 bx lr @@ -1318,7 +1318,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 392 002e 7047 bx lr 393 .LVL18: 394 .L45: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 23 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 23 662:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_LIB_FASTCLK_IMO_IMO)); @@ -1378,7 +1378,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 445 .cfi_startproc 446 @ args = 0, pretend = 0, frame = 0 447 @ frame_needed = 0, uses_anonymous_args = 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 24 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 24 448 @ link register save eliminated. @@ -1438,7 +1438,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 495 .LVL21: 509:.\Generated_Source\PSoC5/CyLib.c **** switch (currentFreq) 496 .loc 1 509 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 25 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 25 497 0014 022D cmp r5, #2 @@ -1498,7 +1498,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 544 0045 00 .align 1 545 .L65: 556:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 26 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 26 546 .loc 1 556 0 @@ -1558,7 +1558,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 589:.\Generated_Source\PSoC5/CyLib.c **** break; 594 .loc 1 589 0 595 00a4 0CE0 b .L76 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 27 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 27 596 .L72: @@ -1618,7 +1618,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 642 .type CyMasterClk_SetSource, %function 643 CyMasterClk_SetSource: 644 .LFB12: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 28 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 28 745:.\Generated_Source\PSoC5/CyLib.c **** { @@ -1678,7 +1678,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 695 .thumb 696 .thumb_func 697 .type CyBusClk_SetDivider, %function - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 29 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 29 698 CyBusClk_SetDivider: @@ -1738,7 +1738,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 855:.\Generated_Source\PSoC5/CyLib.c **** 856:.\Generated_Source\PSoC5/CyLib.c **** /* Work around to set the bus clock divider value */ 857:.\Generated_Source\PSoC5/CyLib.c **** busClkDiv = (uint16)((uint16)CY_LIB_CLKDIST_BCFG_MSB_REG << 8u); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 30 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 30 719 .loc 1 857 0 @@ -1798,7 +1798,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 866:.\Generated_Source\PSoC5/CyLib.c **** { 867:.\Generated_Source\PSoC5/CyLib.c **** /* Set master clock divider to 7 */ 868:.\Generated_Source\PSoC5/CyLib.c **** CyMasterClk_SetDivider(CY_LIB_CLKDIST_MASTERCLK_DIV); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 31 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 31 869:.\Generated_Source\PSoC5/CyLib.c **** } @@ -1858,7 +1858,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 885:.\Generated_Source\PSoC5/CyLib.c **** } 886:.\Generated_Source\PSoC5/CyLib.c **** else 887:.\Generated_Source\PSoC5/CyLib.c **** { - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 32 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 32 888:.\Generated_Source\PSoC5/CyLib.c **** CyBusClk_Internal_SetDivider(divider); @@ -1918,7 +1918,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 912:.\Generated_Source\PSoC5/CyLib.c **** * Side Effects: 913:.\Generated_Source\PSoC5/CyLib.c **** * If as result of this function execution the CPU clock frequency is increased 914:.\Generated_Source\PSoC5/CyLib.c **** * then the number of clock cycles the cache will wait before it samples data - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 33 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 33 915:.\Generated_Source\PSoC5/CyLib.c **** * coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() @@ -1978,7 +1978,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 844 0014 09400040 .word 1073758217 845 .cfi_endproc 846 .LFE16: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 34 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 34 847 .size CyUsbClk_SetSource, .-CyUsbClk_SetSource @@ -2038,7 +2038,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 875 .align 1 876 .global CyILO_Stop1K 877 .thumb - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 35 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 35 878 .thumb_func @@ -2098,7 +2098,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 904 .thumb_func 905 .type CyILO_Start100K, %function 906 CyILO_Start100K: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 36 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 36 907 .LFB19: @@ -2158,7 +2158,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1032:.\Generated_Source\PSoC5/CyLib.c **** * Summary: 1033:.\Generated_Source\PSoC5/CyLib.c **** * Disables the ILO 100 KHz oscillator. 1034:.\Generated_Source\PSoC5/CyLib.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 37 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 37 1035:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: @@ -2218,7 +2218,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 976 000a 1970 strb r1, [r3, #0] 304:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_PM_STBY_CFG0_REG |= CY_LIB_PM_STBY_CFG0_IMO_EN; 977 .loc 1 304 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 38 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 38 978 000c 1A7C ldrb r2, [r3, #16] @ zero_extendqisi2 @@ -2278,7 +2278,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1020 .LVL63: 1021 .L117: 1022 0046 70BD pop {r4, r5, r6, pc} - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 39 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 39 1023 .L129: @@ -2338,7 +2338,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1070 001c 1820 movs r0, #24 1071 .LVL67: 106:.\Generated_Source\PSoC5/CyLib.c **** pmTwCfg2State = CY_LIB_PM_TW_CFG2_REG; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 40 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 40 1072 .loc 1 106 0 @@ -2398,7 +2398,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1116 .LVL73: 1117 .L136: 91:.\Generated_Source\PSoC5/CyLib.c **** cystatus status = CYRET_SUCCESS; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 41 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 41 1118 .loc 1 91 0 @@ -2458,7 +2458,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1147 .loc 1 1068 0 1148 0000 024B ldr r3, .L148 1149 0002 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 42 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 42 1150 0004 42F02000 orr r0, r2, #32 @@ -2518,7 +2518,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1181 .L151: 1182 000c 00430040 .word 1073758976 1183 .cfi_endproc - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 43 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 43 1184 .LFE22: @@ -2578,7 +2578,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1212 .cfi_endproc 1213 .LFE23: 1214 .size CyILO_SetSource, .-CyILO_SetSource - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 44 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 44 1215 .section .text.CyILO_SetPowerMode,"ax",%progbits @@ -2638,7 +2638,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1238 .L155: 1148:.\Generated_Source\PSoC5/CyLib.c **** } 1149:.\Generated_Source\PSoC5/CyLib.c **** else - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 45 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 45 1150:.\Generated_Source\PSoC5/CyLib.c **** { @@ -2698,7 +2698,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1181:.\Generated_Source\PSoC5/CyLib.c **** 1182:.\Generated_Source\PSoC5/CyLib.c **** #if(CY_PSOC3) 1183:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_PDBEN; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 46 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 46 1184:.\Generated_Source\PSoC5/CyLib.c **** #endif /* (CY_PSOC3) */ @@ -2758,7 +2758,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1277 000a 094B ldr r3, .L161+8 1220:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_POWERDOWN; 1278 .loc 1 1220 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 47 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 47 1279 000c 0870 strb r0, [r1, #0] @@ -2818,7 +2818,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1248:.\Generated_Source\PSoC5/CyLib.c **** uint8 CyXTAL_32KHZ_ReadStatus(void) 1249:.\Generated_Source\PSoC5/CyLib.c **** { 1307 .loc 1 1249 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 48 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 48 1308 .cfi_startproc @@ -2878,7 +2878,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1279:.\Generated_Source\PSoC5/CyLib.c **** { 1280:.\Generated_Source\PSoC5/CyLib.c **** /* Low power mode during Sleep */ 1281:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_LOW_POWER; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 49 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 49 1282:.\Generated_Source\PSoC5/CyLib.c **** CyDelayUs(10u); @@ -2938,7 +2938,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1336:.\Generated_Source\PSoC5/CyLib.c **** * 1337:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ 1338:.\Generated_Source\PSoC5/CyLib.c **** cystatus CyXTAL_Start(uint8 wait) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 50 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 50 1339:.\Generated_Source\PSoC5/CyLib.c **** { @@ -2998,7 +2998,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1363 .loc 1 1355 0 1364 0014 93F8F070 ldrb r7, [r3, #240] @ zero_extendqisi2 1365 .LVL83: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 51 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 51 1356:.\Generated_Source\PSoC5/CyLib.c **** pmTwCfg0Tmp = CY_LIB_PM_TW_CFG0_REG; @@ -3058,7 +3058,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1404 0044 9DF80720 ldrb r2, [sp, #7] @ zero_extendqisi2 1405 .LVL93: 1406 0048 511E subs r1, r2, #1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 52 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 52 1407 004a C8B2 uxtb r0, r1 @@ -3118,7 +3118,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1437 .LVL100: 1438 .L173: 1395:.\Generated_Source\PSoC5/CyLib.c **** } - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 53 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 53 1396:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_PM_TW_CFG0_REG = pmTwCfg0Tmp; @@ -3178,7 +3178,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1417:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ 1418:.\Generated_Source\PSoC5/CyLib.c **** void CyXTAL_Stop(void) 1419:.\Generated_Source\PSoC5/CyLib.c **** { - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 54 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 54 1471 .loc 1 1419 0 @@ -3238,7 +3238,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1443:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XMHZ_CSR_REG &= ((uint8)(~CY_CLK_XMHZ_CSR_XFB)); 1502 .loc 1 1443 0 1503 0000 024B ldr r3, .L190 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 55 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 55 1504 0002 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 @@ -3298,7 +3298,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1536 .L193: 1537 000c 10420040 .word 1073758736 1538 .cfi_endproc - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 56 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 56 1539 .LFE32: @@ -3358,7 +3358,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1565 .LFE33: 1566 .size CyXTAL_ReadStatus, .-CyXTAL_ReadStatus 1567 .section .text.CyXTAL_EnableFaultRecovery,"ax",%progbits - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 57 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 57 1568 .align 1 @@ -3418,7 +3418,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1600 .LFB35: 1516:.\Generated_Source\PSoC5/CyLib.c **** } 1517:.\Generated_Source\PSoC5/CyLib.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 58 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 58 1518:.\Generated_Source\PSoC5/CyLib.c **** @@ -3478,7 +3478,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1546:.\Generated_Source\PSoC5/CyLib.c **** * Sets the startup settings for the crystal. Logic model outputs a frequency 1547:.\Generated_Source\PSoC5/CyLib.c **** * (setting + 4) MHz when enabled. 1548:.\Generated_Source\PSoC5/CyLib.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 59 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 59 1549:.\Generated_Source\PSoC5/CyLib.c **** * This is artificial as the actual frequency is determined by an attached @@ -3538,7 +3538,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1573:.\Generated_Source\PSoC5/CyLib.c **** * Summary: 1574:.\Generated_Source\PSoC5/CyLib.c **** * Sets the feedback reference voltage to use for the crystal circuit. 1575:.\Generated_Source\PSoC5/CyLib.c **** * This function is only available for PSoC3 and PSoC 5LP. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 60 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 60 1576:.\Generated_Source\PSoC5/CyLib.c **** * @@ -3598,7 +3598,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1600:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: 1601:.\Generated_Source\PSoC5/CyLib.c **** * setting: Valid range [0-7]. 1602:.\Generated_Source\PSoC5/CyLib.c **** * Refer to the device TRM and datasheet for more information. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 61 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 61 1603:.\Generated_Source\PSoC5/CyLib.c **** * @@ -3658,7 +3658,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1623:.\Generated_Source\PSoC5/CyLib.c **** * uint8 reason: Value to be used during debugging. 1624:.\Generated_Source\PSoC5/CyLib.c **** * 1625:.\Generated_Source\PSoC5/CyLib.c **** * Return: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 62 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 62 1626:.\Generated_Source\PSoC5/CyLib.c **** * None @@ -3718,7 +3718,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1657:.\Generated_Source\PSoC5/CyLib.c **** * None 1658:.\Generated_Source\PSoC5/CyLib.c **** * 1659:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 63 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 63 1660:.\Generated_Source\PSoC5/CyLib.c **** void CySoftwareReset(void) @@ -3778,7 +3778,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1769 .loc 1 1687 0 1770 .cfi_startproc 1771 @ args = 0, pretend = 0, frame = 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 64 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 64 1772 @ frame_needed = 0, uses_anonymous_args = 0 @@ -3838,7 +3838,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1813 .global CyDelayUs 1814 .thumb 1815 .thumb_func - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 65 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 65 1816 .type CyDelayUs, %function @@ -3898,7 +3898,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1737:.\Generated_Source\PSoC5/CyLib.c **** CyDelayCycles((uint32)microseconds * cydelay_freq_mhz); 1831 .loc 1 1737 0 1832 0006 FFF7FEBF b CyDelayCycles - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 66 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 66 1833 .LVL118: @@ -3958,7 +3958,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1878 .loc 1 1278 0 1879 0016 10D1 bne .L227 1281:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_LOW_POWER; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 67 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 67 1880 .loc 1 1281 0 @@ -4018,7 +4018,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1923 0058 3046 mov r0, r6 1924 005a 70BD pop {r4, r5, r6, pc} 1925 .L231: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 68 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 68 1926 .align 2 @@ -4078,7 +4078,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1187:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_EN; 1972 .loc 1 1187 0 1973 001c 13F8012C ldrb r2, [r3, #-1] @ zero_extendqisi2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 69 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 69 1974 0020 42F00100 orr r0, r2, #1 @@ -4138,7 +4138,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 2020 005e 00BF .align 2 2021 .L238: 2022 0060 0A430040 .word 1073758986 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 70 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 70 2023 0064 98460040 .word 1073759896 @@ -4198,7 +4198,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 2050 .loc 1 1765 0 2051 0008 0B4A ldr r2, .L243+4 2052 000a DA60 str r2, [r3, #12] - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 71 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 71 2053 .L242: @@ -4258,7 +4258,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1776:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** 1777:.\Generated_Source\PSoC5/CyLib.c **** * 1778:.\Generated_Source\PSoC5/CyLib.c **** * Summary: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 72 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 72 1779:.\Generated_Source\PSoC5/CyLib.c **** * Enables the watchdog timer. @@ -4318,7 +4318,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 2103 .LVL137: 2104 0006 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 1824:.\Generated_Source\PSoC5/CyLib.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 73 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 73 1825:.\Generated_Source\PSoC5/CyLib.c **** /* Reset CTW to ensure that first watchdog period is full */ @@ -4378,7 +4378,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 2145 CyWdtClear: 2146 .LFB45: 1835:.\Generated_Source\PSoC5/CyLib.c **** } - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 74 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 74 1836:.\Generated_Source\PSoC5/CyLib.c **** @@ -4438,7 +4438,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1865:.\Generated_Source\PSoC5/CyLib.c **** * archives specified threshold and optionally resets device. 1866:.\Generated_Source\PSoC5/CyLib.c **** * 1867:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 75 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 75 1868:.\Generated_Source\PSoC5/CyLib.c **** * reset: Option to reset device at a specified Vddd threshold: @@ -4498,7 +4498,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 2203 0018 104A ldr r2, .L255+8 2204 001a 1078 ldrb r0, [r2, #0] @ zero_extendqisi2 1886:.\Generated_Source\PSoC5/CyLib.c **** CY_VD_LVI_TRIP_REG = (threshold & CY_VD_LVI_TRIP_LVID_MASK) | - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 76 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 76 2205 .loc 1 1886 0 @@ -4558,7 +4558,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 2238 .loc 1 1904 0 2239 004c 1860 str r0, [r3, #0] 2240 .loc 1 1905 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 77 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 77 2241 004e 1060 str r0, [r2, #0] @@ -4618,7 +4618,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 2269 .cfi_def_cfa_offset 16 2270 .cfi_offset 3, -16 2271 .cfi_offset 4, -12 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 78 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 78 2272 .cfi_offset 5, -8 @@ -4678,7 +4678,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1944:.\Generated_Source\PSoC5/CyLib.c **** if(0u != reset) 2309 .loc 1 1944 0 2310 0038 15B1 cbz r5, .L258 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 79 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 79 2311 .loc 1 1946 0 @@ -4738,7 +4738,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 1961:.\Generated_Source\PSoC5/CyLib.c **** * 1962:.\Generated_Source\PSoC5/CyLib.c **** * Summary: 1963:.\Generated_Source\PSoC5/CyLib.c **** * Disables the digital low voltage monitor (interrupt and device reset are - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 80 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 80 1964:.\Generated_Source\PSoC5/CyLib.c **** * disabled). @@ -4798,7 +4798,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 2383 .thumb_func 2384 .type CyVdLvAnalogDisable, %function 2385 CyVdLvAnalogDisable: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 81 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 81 2386 .LFB49: @@ -4858,7 +4858,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 2412 001c F5460040 .word 1073759989 2413 0020 FA460040 .word 1073759994 2414 .cfi_endproc - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 82 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 82 2415 .LFE49: @@ -4918,7 +4918,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 2035:.\Generated_Source\PSoC5/CyLib.c **** CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_HVIA_EN; 2445 .loc 1 2035 0 2446 0012 10F8023C ldrb r3, [r0, #-2] @ zero_extendqisi2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 83 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 83 2447 0016 43F00402 orr r2, r3, #4 @@ -4978,7 +4978,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 2052:.\Generated_Source\PSoC5/CyLib.c **** * Disables the analog low voltage monitor 2053:.\Generated_Source\PSoC5/CyLib.c **** * (interrupt and device reset are disabled). 2054:.\Generated_Source\PSoC5/CyLib.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 84 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 84 2055:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: @@ -5038,7 +5038,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 2083:.\Generated_Source\PSoC5/CyLib.c **** * 2084:.\Generated_Source\PSoC5/CyLib.c **** * Return: 2085:.\Generated_Source\PSoC5/CyLib.c **** * Status. Same enumerated bit values as used for the mask parameter. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 85 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 85 2086:.\Generated_Source\PSoC5/CyLib.c **** * @@ -5098,7 +5098,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 2107:.\Generated_Source\PSoC5/CyLib.c **** * None 2108:.\Generated_Source\PSoC5/CyLib.c **** * 2109:.\Generated_Source\PSoC5/CyLib.c **** * Return: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 86 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 86 2110:.\Generated_Source\PSoC5/CyLib.c **** * Status: @@ -5158,7 +5158,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 2578 .LFB54: 2128:.\Generated_Source\PSoC5/CyLib.c **** 2129:.\Generated_Source\PSoC5/CyLib.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 87 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 87 2130:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* @@ -5218,7 +5218,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 2170:.\Generated_Source\PSoC5/CyLib.c **** 2171:.\Generated_Source\PSoC5/CyLib.c **** /* Disable all of the interrupts. */ 2172:.\Generated_Source\PSoC5/CyLib.c **** CY_SET_REG32(CY_INT_CLEAR_PTR, 0xFFFFFFFFu); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 88 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 88 2593 .loc 1 2172 0 @@ -5278,7 +5278,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 2621 .loc 1 2197 0 2622 .cfi_startproc 2623 @ args = 0, pretend = 0, frame = 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 89 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 89 2624 @ frame_needed = 0, uses_anonymous_args = 0 @@ -5338,7 +5338,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 2655 .thumb_func 2656 .type CyFlushCache, %function 2657 CyFlushCache: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 90 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 90 2658 .LFB56: @@ -5398,7 +5398,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 2685 @ 0 "" 2 2247:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; 2686 .loc 1 2247 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 91 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 91 2687 @ 2247 ".\Generated_Source\PSoC5\CyLib.c" 1 @@ -5458,7 +5458,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 2732 @ 2256 ".\Generated_Source\PSoC5\CyLib.c" 1 2733 001e 00BF NOP 2734 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 92 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 92 2735 @ 0 "" 2 @@ -5518,7 +5518,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 2273:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; 2773 .loc 1 2273 0 2774 @ 2273 ".\Generated_Source\PSoC5\CyLib.c" 1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 93 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 93 2775 0038 00BF NOP @@ -5578,7 +5578,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 2820 004a 00BF NOP 2821 2822 @ 0 "" 2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 94 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 94 2283:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; @@ -5638,7 +5638,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 2300:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: 2301:.\Generated_Source\PSoC5/CyLib.c **** * number: Interrupt number, valid range [0-15]. 2302:.\Generated_Source\PSoC5/CyLib.c **** address: Pointer to an interrupt service routine. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 95 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 95 2303:.\Generated_Source\PSoC5/CyLib.c **** * @@ -5698,7 +5698,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 2324:.\Generated_Source\PSoC5/CyLib.c **** 2325:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* 2326:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyIntGetSysVector - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 96 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 96 2327:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** @@ -5758,7 +5758,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 2351:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyIntSetVector 2352:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** 2353:.\Generated_Source\PSoC5/CyLib.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 97 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 97 2354:.\Generated_Source\PSoC5/CyLib.c **** * Summary: @@ -5818,7 +5818,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 2950 .align 1 2951 .global CyIntGetVector 2952 .thumb - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 98 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 98 2953 .thumb_func @@ -5878,7 +5878,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 2984 .thumb_func 2985 .type CyIntSetPriority, %function 2986 CyIntSetPriority: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 99 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 99 2987 .LFB61: @@ -5938,7 +5938,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 2429:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyIntGetPriority 2430:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** 2431:.\Generated_Source\PSoC5/CyLib.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 100 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 100 2432:.\Generated_Source\PSoC5/CyLib.c **** * Summary: @@ -5998,7 +5998,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 2459:.\Generated_Source\PSoC5/CyLib.c **** * Gets the enable state of the specified interrupt number. 2460:.\Generated_Source\PSoC5/CyLib.c **** * 2461:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 101 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 101 2462:.\Generated_Source\PSoC5/CyLib.c **** * number: Valid range [0-31]. Interrupt number. @@ -6058,7 +6058,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3078 cydelay_freq_khz: 3079 0004 00FA0000 .word 64000 3080 .type cydelay_freq_mhz, %object - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 102 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 102 3081 .size cydelay_freq_mhz, 1 @@ -6086,10 +6086,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3103 0006 00000000 .4byte .Ldebug_abbrev0 3104 000a 04 .byte 0x4 3105 000b 01 .uleb128 0x1 - 3106 000c 41050000 .4byte .LASF134 + 3106 000c 52050000 .4byte .LASF134 3107 0010 01 .byte 0x1 - 3108 0011 71040000 .4byte .LASF135 - 3109 0015 F1010000 .4byte .LASF136 + 3108 0011 82040000 .4byte .LASF135 + 3109 0015 A0030000 .4byte .LASF136 3110 0019 00000000 .4byte .Ldebug_ranges0+0 3111 001d 00000000 .4byte 0 3112 0021 00000000 .4byte 0 @@ -6101,15 +6101,15 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3118 0030 02 .uleb128 0x2 3119 0031 01 .byte 0x1 3120 0032 08 .byte 0x8 - 3121 0033 B4050000 .4byte .LASF1 + 3121 0033 C5050000 .4byte .LASF1 3122 0037 02 .uleb128 0x2 3123 0038 02 .byte 0x2 3124 0039 05 .byte 0x5 - 3125 003a D0050000 .4byte .LASF2 + 3125 003a E1050000 .4byte .LASF2 3126 003e 02 .uleb128 0x2 3127 003f 02 .byte 0x2 3128 0040 07 .byte 0x7 - 3129 0041 E7020000 .4byte .LASF3 + 3129 0041 C7020000 .4byte .LASF3 3130 0045 03 .uleb128 0x3 3131 0046 04 .byte 0x4 3132 0047 05 .byte 0x5 @@ -6117,8 +6117,8 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3134 004c 02 .uleb128 0x2 3135 004d 04 .byte 0x4 3136 004e 07 .byte 0x7 - 3137 004f 3F020000 .4byte .LASF4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 103 + 3137 004f 1F020000 .4byte .LASF4 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 103 3138 0053 02 .uleb128 0x2 @@ -6136,11 +6136,11 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3150 0068 02 .uleb128 0x2 3151 0069 04 .byte 0x4 3152 006a 07 .byte 0x7 - 3153 006b FD030000 .4byte .LASF8 + 3153 006b 0E040000 .4byte .LASF8 3154 006f 02 .uleb128 0x2 3155 0070 04 .byte 0x4 3156 0071 07 .byte 0x7 - 3157 0072 79020000 .4byte .LASF9 + 3157 0072 59020000 .4byte .LASF9 3158 0076 04 .uleb128 0x4 3159 0077 01 .byte 0x1 3160 0078 05 .uleb128 0x5 @@ -6149,7 +6149,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3163 007e 02 .uleb128 0x2 3164 007f 01 .byte 0x1 3165 0080 08 .byte 0x8 - 3166 0081 74060000 .4byte .LASF10 + 3166 0081 85060000 .4byte .LASF10 3167 0085 06 .uleb128 0x6 3168 0086 8D010000 .4byte .LASF11 3169 008a 02 .byte 0x2 @@ -6168,21 +6168,21 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3182 00a6 02 .uleb128 0x2 3183 00a7 04 .byte 0x4 3184 00a8 04 .byte 0x4 - 3185 00a9 B1040000 .4byte .LASF14 + 3185 00a9 C2040000 .4byte .LASF14 3186 00ad 02 .uleb128 0x2 3187 00ae 08 .byte 0x8 3188 00af 04 .byte 0x4 3189 00b0 AD010000 .4byte .LASF15 3190 00b4 06 .uleb128 0x6 - 3191 00b5 95070000 .4byte .LASF16 + 3191 00b5 A6070000 .4byte .LASF16 3192 00b9 02 .byte 0x2 3193 00ba E8 .byte 0xe8 3194 00bb 6F000000 .4byte 0x6f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 104 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 104 3195 00bf 06 .uleb128 0x6 - 3196 00c0 8A050000 .4byte .LASF17 + 3196 00c0 9B050000 .4byte .LASF17 3197 00c4 02 .byte 0x2 3198 00c5 F0 .byte 0xf0 3199 00c6 CA000000 .4byte 0xca @@ -6196,41 +6196,41 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3207 00da 07 .uleb128 0x7 3208 00db 90000000 .4byte 0x90 3209 00df 06 .uleb128 0x6 - 3210 00e0 CD030000 .4byte .LASF19 + 3210 00e0 DE030000 .4byte .LASF19 3211 00e4 02 .byte 0x2 3212 00e5 F2 .byte 0xf2 3213 00e6 EA000000 .4byte 0xea 3214 00ea 07 .uleb128 0x7 3215 00eb 9B000000 .4byte 0x9b 3216 00ef 08 .uleb128 0x8 - 3217 00f0 7E060000 .4byte .LASF20 + 3217 00f0 8F060000 .4byte .LASF20 3218 00f4 02 .byte 0x2 3219 00f5 0201 .2byte 0x102 3220 00f7 78000000 .4byte 0x78 3221 00fb 09 .uleb128 0x9 3222 00fc 01 .byte 0x1 - 3223 00fd 92040000 .4byte .LASF131 + 3223 00fd A3040000 .4byte .LASF131 3224 0101 01 .byte 0x1 3225 0102 0B03 .2byte 0x30b 3226 0104 01 .byte 0x1 3227 0105 01 .byte 0x1 3228 0106 17010000 .4byte 0x117 3229 010a 0A .uleb128 0xa - 3230 010b 8D070000 .4byte .LASF24 + 3230 010b 9E070000 .4byte .LASF24 3231 010f 01 .byte 0x1 3232 0110 0B03 .2byte 0x30b 3233 0112 85000000 .4byte 0x85 3234 0116 00 .byte 0 3235 0117 0B .uleb128 0xb 3236 0118 01 .byte 0x1 - 3237 0119 69070000 .4byte .LASF129 + 3237 0119 7A070000 .4byte .LASF129 3238 011d 01 .byte 0x1 3239 011e E004 .2byte 0x4e0 3240 0120 01 .byte 0x1 3241 0121 85000000 .4byte 0x85 3242 0125 01 .byte 0x1 3243 0126 0C .uleb128 0xc - 3244 0127 66020000 .4byte .LASF137 + 3244 0127 46020000 .4byte .LASF137 3245 012b 01 .byte 0x1 3246 012c 6E01 .2byte 0x16e 3247 012e 01 .byte 0x1 @@ -6238,10 +6238,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3249 0133 01 .byte 0x1 3250 0134 45010000 .4byte 0x145 3251 0138 0D .uleb128 0xd - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 105 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 105 - 3252 0139 16060000 .4byte .LASF138 + 3252 0139 27060000 .4byte .LASF138 3253 013d 01 .byte 0x1 3254 013e 7001 .2byte 0x170 3255 0140 85000000 .4byte 0x85 @@ -6265,7 +6265,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3273 0166 85000000 .4byte 0x85 3274 016a 00000000 .4byte .LLST0 3275 016e 10 .uleb128 0x10 - 3276 016f 58040000 .4byte .LASF37 + 3276 016f 69040000 .4byte .LASF37 3277 0173 01 .byte 0x1 3278 0174 8F01 .2byte 0x18f 3279 0176 85000000 .4byte 0x85 @@ -6287,7 +6287,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3295 019f 00 .byte 0 3296 01a0 00 .byte 0 3297 01a1 0E .uleb128 0xe - 3298 01a2 91030000 .4byte .LASF22 + 3298 01a2 71030000 .4byte .LASF22 3299 01a6 01 .byte 0x1 3300 01a7 2103 .2byte 0x321 3301 01a9 01 .byte 0x1 @@ -6298,11 +6298,11 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3306 01b4 00 .sleb128 0 3307 01b5 01 .byte 0x1 3308 01b6 CB010000 .4byte 0x1cb - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 106 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 106 3309 01ba 0F .uleb128 0xf - 3310 01bb 8D070000 .4byte .LASF24 + 3310 01bb 9E070000 .4byte .LASF24 3311 01bf 01 .byte 0x1 3312 01c0 2103 .2byte 0x321 3313 01c2 90000000 .4byte 0x90 @@ -6310,7 +6310,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3315 01ca 00 .byte 0 3316 01cb 14 .uleb128 0x14 3317 01cc 01 .byte 0x1 - 3318 01cd 26040000 .4byte .LASF31 + 3318 01cd 37040000 .4byte .LASF31 3319 01d1 01 .byte 0x1 3320 01d2 99 .byte 0x99 3321 01d3 01 .byte 0x1 @@ -6334,19 +6334,19 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3339 01f4 01 .byte 0x1 3340 01f5 27020000 .4byte 0x227 3341 01f9 16 .uleb128 0x16 - 3342 01fa 56070000 .4byte .LASF25 + 3342 01fa 67070000 .4byte .LASF25 3343 01fe 01 .byte 0x1 3344 01ff BF .byte 0xbf 3345 0200 85000000 .4byte 0x85 3346 0204 7B000000 .4byte .LLST3 3347 0208 16 .uleb128 0x16 - 3348 0209 C7060000 .4byte .LASF26 + 3348 0209 D8060000 .4byte .LASF26 3349 020d 01 .byte 0x1 3350 020e BF .byte 0xbf 3351 020f 85000000 .4byte 0x85 3352 0213 A8000000 .4byte .LLST4 3353 0217 16 .uleb128 0x16 - 3354 0218 A9040000 .4byte .LASF27 + 3354 0218 BA040000 .4byte .LASF27 3355 021c 01 .byte 0x1 3356 021d BF .byte 0xbf 3357 021e 85000000 .4byte 0x85 @@ -6358,7 +6358,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3363 022d 01 .byte 0x1 3364 022e F6 .byte 0xf6 3365 022f 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 107 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 107 3366 0230 00000000 .4byte .LFB3 @@ -6369,7 +6369,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3371 023b 01 .byte 0x1 3372 023c 50020000 .4byte 0x250 3373 0240 16 .uleb128 0x16 - 3374 0241 F6030000 .4byte .LASF30 + 3374 0241 07040000 .4byte .LASF30 3375 0245 01 .byte 0x1 3376 0246 F6 .byte 0xf6 3377 0247 85000000 .4byte 0x85 @@ -6377,7 +6377,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3379 024f 00 .byte 0 3380 0250 17 .uleb128 0x17 3381 0251 01 .byte 0x1 - 3382 0252 DC020000 .4byte .LASF32 + 3382 0252 BC020000 .4byte .LASF32 3383 0256 01 .byte 0x1 3384 0257 5901 .2byte 0x159 3385 0259 01 .byte 0x1 @@ -6389,7 +6389,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3391 0265 01 .byte 0x1 3392 0266 18 .uleb128 0x18 3393 0267 01 .byte 0x1 - 3394 0268 4C020000 .4byte .LASF33 + 3394 0268 2C020000 .4byte .LASF33 3395 026c 01 .byte 0x1 3396 026d 8702 .2byte 0x287 3397 026f 01 .byte 0x1 @@ -6401,7 +6401,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3403 027b 01 .byte 0x1 3404 027c 91020000 .4byte 0x291 3405 0280 0F .uleb128 0xf - 3406 0281 F6030000 .4byte .LASF30 + 3406 0281 07040000 .4byte .LASF30 3407 0285 01 .byte 0x1 3408 0286 8702 .2byte 0x287 3409 0288 85000000 .4byte 0x85 @@ -6418,13 +6418,13 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3420 02a3 02 .byte 0x2 3421 02a4 7D .byte 0x7d 3422 02a5 00 .sleb128 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 108 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 108 3423 02a6 01 .byte 0x1 3424 02a7 17 .uleb128 0x17 3425 02a8 01 .byte 0x1 - 3426 02a9 8B060000 .4byte .LASF35 + 3426 02a9 9C060000 .4byte .LASF35 3427 02ad 01 .byte 0x1 3428 02ae C502 .2byte 0x2c5 3429 02b0 01 .byte 0x1 @@ -6436,7 +6436,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3435 02bc 01 .byte 0x1 3436 02bd 19 .uleb128 0x19 3437 02be 01 .byte 0x1 - 3438 02bf 5B070000 .4byte .LASF36 + 3438 02bf 6C070000 .4byte .LASF36 3439 02c3 01 .byte 0x1 3440 02c4 EC01 .2byte 0x1ec 3441 02c6 01 .byte 0x1 @@ -6452,13 +6452,13 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3451 02e0 85000000 .4byte 0x85 3452 02e4 7E010000 .4byte .LLST9 3453 02e8 1A .uleb128 0x1a - 3454 02e9 FB060000 .4byte .LASF38 + 3454 02e9 0C070000 .4byte .LASF38 3455 02ed 01 .byte 0x1 3456 02ee EE01 .2byte 0x1ee 3457 02f0 85000000 .4byte 0x85 3458 02f4 9F010000 .4byte .LLST10 3459 02f8 10 .uleb128 0x10 - 3460 02f9 64060000 .4byte .LASF39 + 3460 02f9 75060000 .4byte .LASF39 3461 02fd 01 .byte 0x1 3462 02fe EF01 .2byte 0x1ef 3463 0300 85000000 .4byte 0x85 @@ -6478,7 +6478,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3477 031a 1D .uleb128 0x1d 3478 031b BE000000 .4byte .LVL29 3479 031f 91020000 .4byte 0x291 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 109 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 109 3480 0323 1D .uleb128 0x1d @@ -6498,7 +6498,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3494 033d 00 .byte 0 3495 033e 18 .uleb128 0x18 3496 033f 01 .byte 0x1 - 3497 0340 28030000 .4byte .LASF40 + 3497 0340 08030000 .4byte .LASF40 3498 0344 01 .byte 0x1 3499 0345 E802 .2byte 0x2e8 3500 0347 01 .byte 0x1 @@ -6510,7 +6510,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3506 0353 01 .byte 0x1 3507 0354 69030000 .4byte 0x369 3508 0358 0F .uleb128 0xf - 3509 0359 F6030000 .4byte .LASF30 + 3509 0359 07040000 .4byte .LASF30 3510 035d 01 .byte 0x1 3511 035e E802 .2byte 0x2e8 3512 0360 85000000 .4byte 0x85 @@ -6532,32 +6532,32 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3528 0385 00 .byte 0 3529 0386 19 .uleb128 0x19 3530 0387 01 .byte 0x1 - 3531 0388 0F070000 .4byte .LASF41 + 3531 0388 20070000 .4byte .LASF41 3532 038c 01 .byte 0x1 3533 038d 5003 .2byte 0x350 3534 038f 01 .byte 0x1 3535 0390 00000000 .4byte .LFB15 3536 0394 6C000000 .4byte .LFE15 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 110 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 110 3537 0398 EA010000 .4byte .LLST12 3538 039c 01 .byte 0x1 3539 039d 74040000 .4byte 0x474 3540 03a1 0F .uleb128 0xf - 3541 03a2 8D070000 .4byte .LASF24 + 3541 03a2 9E070000 .4byte .LASF24 3542 03a6 01 .byte 0x1 3543 03a7 5003 .2byte 0x350 3544 03a9 90000000 .4byte 0x90 3545 03ad 0A020000 .4byte .LLST13 3546 03b1 1A .uleb128 0x1a - 3547 03b2 34050000 .4byte .LASF42 + 3547 03b2 45050000 .4byte .LASF42 3548 03b6 01 .byte 0x1 3549 03b7 5203 .2byte 0x352 3550 03b9 85000000 .4byte 0x85 3551 03bd 2B020000 .4byte .LLST14 3552 03c1 1A .uleb128 0x1a - 3553 03c2 5C020000 .4byte .LASF43 + 3553 03c2 3C020000 .4byte .LASF43 3554 03c6 01 .byte 0x1 3555 03c7 5303 .2byte 0x353 3556 03c9 90000000 .4byte 0x90 @@ -6598,7 +6598,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3591 042b A1010000 .4byte 0x1a1 3592 042f 3A040000 .4byte 0x43a 3593 0433 1C .uleb128 0x1c - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 111 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 111 3594 0434 01 .byte 0x1 @@ -6643,7 +6643,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3633 0473 00 .byte 0 3634 0474 18 .uleb128 0x18 3635 0475 01 .byte 0x1 - 3636 0476 D9060000 .4byte .LASF45 + 3636 0476 EA060000 .4byte .LASF45 3637 047a 01 .byte 0x1 3638 047b B403 .2byte 0x3b4 3639 047d 01 .byte 0x1 @@ -6655,10 +6655,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3645 0489 01 .byte 0x1 3646 048a 9F040000 .4byte 0x49f 3647 048e 0F .uleb128 0xf - 3648 048f F6030000 .4byte .LASF30 + 3648 048f 07040000 .4byte .LASF30 3649 0493 01 .byte 0x1 3650 0494 B403 .2byte 0x3b4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 112 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 112 3651 0496 85000000 .4byte 0x85 @@ -6690,7 +6690,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3677 04ca 01 .byte 0x1 3678 04cb 17 .uleb128 0x17 3679 04cc 01 .byte 0x1 - 3680 04cd 48040000 .4byte .LASF48 + 3680 04cd 59040000 .4byte .LASF48 3681 04d1 01 .byte 0x1 3682 04d2 FE03 .2byte 0x3fe 3683 04d4 01 .byte 0x1 @@ -6718,7 +6718,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3705 04fd 01 .byte 0x1 3706 04fe 2801 .2byte 0x128 3707 0500 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 113 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 113 3708 0501 00000000 .4byte .LFB4 @@ -6733,13 +6733,13 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3717 051a 85000000 .4byte 0x85 3718 051e 19030000 .4byte .LLST21 3719 0522 1A .uleb128 0x1a - 3720 0523 57060000 .4byte .LASF52 + 3720 0523 68060000 .4byte .LASF52 3721 0527 01 .byte 0x1 3722 0528 2A01 .2byte 0x12a 3723 052a 85000000 .4byte 0x85 3724 052e 3A030000 .4byte .LLST22 3725 0532 1A .uleb128 0x1a - 3726 0533 A6070000 .4byte .LASF53 + 3726 0533 B7070000 .4byte .LASF53 3727 0537 01 .byte 0x1 3728 0538 2B01 .2byte 0x12b 3729 053a 85000000 .4byte 0x85 @@ -6778,7 +6778,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3762 0583 01 .byte 0x1 3763 0584 93010000 .4byte .LASF62 3764 0588 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 114 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 114 3765 0589 59 .byte 0x59 @@ -6796,13 +6796,13 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3777 05a7 85000000 .4byte 0x85 3778 05ab 9E030000 .4byte .LLST26 3779 05af 24 .uleb128 0x24 - 3780 05b0 3F070000 .4byte .LASF55 + 3780 05b0 50070000 .4byte .LASF55 3781 05b4 01 .byte 0x1 3782 05b5 5B .byte 0x5b 3783 05b6 B4000000 .4byte 0xb4 3784 05ba D8030000 .4byte .LLST27 3785 05be 24 .uleb128 0x24 - 3786 05bf DA050000 .4byte .LASF56 + 3786 05bf EB050000 .4byte .LASF56 3787 05c3 01 .byte 0x1 3788 05c4 5D .byte 0x5d 3789 05c5 85000000 .4byte 0x85 @@ -6814,7 +6814,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3795 05d4 85000000 .4byte 0x85 3796 05d8 38040000 .4byte .LLST29 3797 05dc 24 .uleb128 0x24 - 3798 05dd C2050000 .4byte .LASF58 + 3798 05dd D3050000 .4byte .LASF58 3799 05e1 01 .byte 0x1 3800 05e2 5F .byte 0x5f 3801 05e3 85000000 .4byte 0x85 @@ -6838,7 +6838,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3819 060d 50 .byte 0x50 3820 060e 01 .byte 0x1 3821 060f 31 .byte 0x31 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 115 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 115 3822 0610 00 .byte 0 @@ -6848,7 +6848,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3826 061a 00 .byte 0 3827 061b 17 .uleb128 0x17 3828 061c 01 .byte 0x1 - 3829 061d E7040000 .4byte .LASF59 + 3829 061d F8040000 .4byte .LASF59 3830 0621 01 .byte 0x1 3831 0622 2904 .2byte 0x429 3832 0624 01 .byte 0x1 @@ -6860,7 +6860,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3838 0630 01 .byte 0x1 3839 0631 17 .uleb128 0x17 3840 0632 01 .byte 0x1 - 3841 0633 13050000 .4byte .LASF60 + 3841 0633 24050000 .4byte .LASF60 3842 0637 01 .byte 0x1 3843 0638 4104 .2byte 0x441 3844 063a 01 .byte 0x1 @@ -6872,7 +6872,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3850 0646 01 .byte 0x1 3851 0647 18 .uleb128 0x18 3852 0648 01 .byte 0x1 - 3853 0649 46070000 .4byte .LASF61 + 3853 0649 57070000 .4byte .LASF61 3854 064d 01 .byte 0x1 3855 064e 5904 .2byte 0x459 3856 0650 01 .byte 0x1 @@ -6884,7 +6884,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3862 065c 01 .byte 0x1 3863 065d 72060000 .4byte 0x672 3864 0661 0F .uleb128 0xf - 3865 0662 F6030000 .4byte .LASF30 + 3865 0662 07040000 .4byte .LASF30 3866 0666 01 .byte 0x1 3867 0667 5904 .2byte 0x459 3868 0669 85000000 .4byte 0x85 @@ -6892,13 +6892,13 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3870 0671 00 .byte 0 3871 0672 25 .uleb128 0x25 3872 0673 01 .byte 0x1 - 3873 0674 C9020000 .4byte .LASF63 + 3873 0674 A9020000 .4byte .LASF63 3874 0678 01 .byte 0x1 3875 0679 7104 .2byte 0x471 3876 067b 01 .byte 0x1 3877 067c 85000000 .4byte 0x85 3878 0680 00000000 .4byte .LFB24 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 116 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 116 3879 0684 1C000000 .4byte .LFE24 @@ -6908,7 +6908,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3883 068b 01 .byte 0x1 3884 068c AF060000 .4byte 0x6af 3885 0690 0F .uleb128 0xf - 3886 0691 79060000 .4byte .LASF64 + 3886 0691 8A060000 .4byte .LASF64 3887 0695 01 .byte 0x1 3888 0696 7104 .2byte 0x471 3889 0698 85000000 .4byte 0x85 @@ -6923,7 +6923,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3898 06ae 00 .byte 0 3899 06af 17 .uleb128 0x17 3900 06b0 01 .byte 0x1 - 3901 06b1 B7020000 .4byte .LASF66 + 3901 06b1 97020000 .4byte .LASF66 3902 06b5 01 .byte 0x1 3903 06b6 C104 .2byte 0x4c1 3904 06b8 01 .byte 0x1 @@ -6943,7 +6943,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3918 06d5 01 .byte 0x1 3919 06d6 27 .uleb128 0x27 3920 06d7 01 .byte 0x1 - 3921 06d8 C0030000 .4byte .LASF67 + 3921 06d8 D1030000 .4byte .LASF67 3922 06dc 01 .byte 0x1 3923 06dd 3A05 .2byte 0x53a 3924 06df 01 .byte 0x1 @@ -6958,18 +6958,18 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3933 06fa 01 .byte 0x1 3934 06fb 3A05 .2byte 0x53a 3935 06fd 85000000 .4byte 0x85 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 117 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 117 3936 0701 C0040000 .4byte .LLST34 3937 0705 1A .uleb128 0x1a - 3938 0706 3F070000 .4byte .LASF55 + 3938 0706 50070000 .4byte .LASF55 3939 070a 01 .byte 0x1 3940 070b 3C05 .2byte 0x53c 3941 070d B4000000 .4byte 0xb4 3942 0711 F6040000 .4byte .LLST35 3943 0715 1A .uleb128 0x1a - 3944 0716 8B020000 .4byte .LASF68 + 3944 0716 6B020000 .4byte .LASF68 3945 071a 01 .byte 0x1 3946 071b 3D05 .2byte 0x53d 3947 071d CA000000 .4byte 0xca @@ -6981,7 +6981,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3953 072d CA000000 .4byte 0xca 3954 0731 A6050000 .4byte .LLST37 3955 0735 1A .uleb128 0x1a - 3956 0736 DA050000 .4byte .LASF56 + 3956 0736 EB050000 .4byte .LASF56 3957 073a 01 .byte 0x1 3958 073b 3F05 .2byte 0x53f 3959 073d 85000000 .4byte 0x85 @@ -6993,7 +6993,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3965 074d 85000000 .4byte 0x85 3966 0751 E2050000 .4byte .LLST39 3967 0755 1A .uleb128 0x1a - 3968 0756 81070000 .4byte .LASF71 + 3968 0756 92070000 .4byte .LASF71 3969 075a 01 .byte 0x1 3970 075b 4105 .2byte 0x541 3971 075d 85000000 .4byte 0x85 @@ -7018,7 +7018,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3990 0788 01 .byte 0x1 3991 0789 31 .byte 0x31 3992 078a 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 118 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 118 3993 078b 1D .uleb128 0x1d @@ -7027,7 +7027,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 3996 0794 00 .byte 0 3997 0795 17 .uleb128 0x17 3998 0796 01 .byte 0x1 - 3999 0797 E5070000 .4byte .LASF72 + 3999 0797 F6070000 .4byte .LASF72 4000 079b 01 .byte 0x1 4001 079c 8A05 .2byte 0x58a 4002 079e 01 .byte 0x1 @@ -7039,7 +7039,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4008 07aa 01 .byte 0x1 4009 07ab 17 .uleb128 0x17 4010 07ac 01 .byte 0x1 - 4011 07ad E9050000 .4byte .LASF73 + 4011 07ad FA050000 .4byte .LASF73 4012 07b1 01 .byte 0x1 4013 07b2 A005 .2byte 0x5a0 4014 07b4 01 .byte 0x1 @@ -7063,7 +7063,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4032 07d6 01 .byte 0x1 4033 07d7 28 .uleb128 0x28 4034 07d8 01 .byte 0x1 - 4035 07d9 D3030000 .4byte .LASF139 + 4035 07d9 E4030000 .4byte .LASF139 4036 07dd 01 .byte 0x1 4037 07de CE05 .2byte 0x5ce 4038 07e0 01 .byte 0x1 @@ -7076,9 +7076,9 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4045 07f0 01 .byte 0x1 4046 07f1 17 .uleb128 0x17 4047 07f2 01 .byte 0x1 - 4048 07f3 65030000 .4byte .LASF75 + 4048 07f3 45030000 .4byte .LASF75 4049 07f7 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 119 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 119 4050 07f8 E905 .2byte 0x5e9 @@ -7091,7 +7091,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4057 0806 01 .byte 0x1 4058 0807 17 .uleb128 0x17 4059 0808 01 .byte 0x1 - 4060 0809 20060000 .4byte .LASF76 + 4060 0809 31060000 .4byte .LASF76 4061 080d 01 .byte 0x1 4062 080e FF05 .2byte 0x5ff 4063 0810 01 .byte 0x1 @@ -7103,7 +7103,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4069 081c 01 .byte 0x1 4070 081d 18 .uleb128 0x18 4071 081e 01 .byte 0x1 - 4072 081f 06040000 .4byte .LASF77 + 4072 081f 17040000 .4byte .LASF77 4073 0823 01 .byte 0x1 4074 0824 1906 .2byte 0x619 4075 0826 01 .byte 0x1 @@ -7115,7 +7115,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4081 0832 01 .byte 0x1 4082 0833 48080000 .4byte 0x848 4083 0837 0F .uleb128 0xf - 4084 0838 9E070000 .4byte .LASF78 + 4084 0838 AF070000 .4byte .LASF78 4085 083c 01 .byte 0x1 4086 083d 1906 .2byte 0x619 4087 083f 85000000 .4byte 0x85 @@ -7123,7 +7123,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4089 0847 00 .byte 0 4090 0848 18 .uleb128 0x18 4091 0849 01 .byte 0x1 - 4092 084a 43060000 .4byte .LASF79 + 4092 084a 54060000 .4byte .LASF79 4093 084e 01 .byte 0x1 4094 084f 3106 .2byte 0x631 4095 0851 01 .byte 0x1 @@ -7135,10 +7135,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4101 085d 01 .byte 0x1 4102 085e 73080000 .4byte 0x873 4103 0862 0F .uleb128 0xf - 4104 0863 9E070000 .4byte .LASF78 + 4104 0863 AF070000 .4byte .LASF78 4105 0867 01 .byte 0x1 4106 0868 3106 .2byte 0x631 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 120 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 120 4107 086a 85000000 .4byte 0x85 @@ -7146,7 +7146,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4109 0872 00 .byte 0 4110 0873 18 .uleb128 0x18 4111 0874 01 .byte 0x1 - 4112 0875 A0050000 .4byte .LASF80 + 4112 0875 B1050000 .4byte .LASF80 4113 0879 01 .byte 0x1 4114 087a 4806 .2byte 0x648 4115 087c 01 .byte 0x1 @@ -7158,7 +7158,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4121 0888 01 .byte 0x1 4122 0889 9E080000 .4byte 0x89e 4123 088d 0F .uleb128 0xf - 4124 088e 9E070000 .4byte .LASF78 + 4124 088e AF070000 .4byte .LASF78 4125 0892 01 .byte 0x1 4126 0893 4806 .2byte 0x648 4127 0895 85000000 .4byte 0x85 @@ -7166,7 +7166,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4129 089d 00 .byte 0 4130 089e 18 .uleb128 0x18 4131 089f 01 .byte 0x1 - 4132 08a0 99050000 .4byte .LASF81 + 4132 08a0 AA050000 .4byte .LASF81 4133 08a4 01 .byte 0x1 4134 08a5 5D06 .2byte 0x65d 4135 08a7 01 .byte 0x1 @@ -7178,7 +7178,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4141 08b3 01 .byte 0x1 4142 08b4 C7080000 .4byte 0x8c7 4143 08b8 29 .uleb128 0x29 - 4144 08b9 3C060000 .4byte .LASF82 + 4144 08b9 4D060000 .4byte .LASF82 4145 08bd 01 .byte 0x1 4146 08be 5D06 .2byte 0x65d 4147 08c0 85000000 .4byte 0x85 @@ -7198,11 +7198,11 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4161 08db 00 .sleb128 0 4162 08dc 01 .byte 0x1 4163 08dd 19 .uleb128 0x19 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 121 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 121 4164 08de 01 .byte 0x1 - 4165 08df 07070000 .4byte .LASF84 + 4165 08df 18070000 .4byte .LASF84 4166 08e3 01 .byte 0x1 4167 08e4 9606 .2byte 0x696 4168 08e6 01 .byte 0x1 @@ -7212,7 +7212,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4172 08f3 01 .byte 0x1 4173 08f4 1C090000 .4byte 0x91c 4174 08f8 0F .uleb128 0xf - 4175 08f9 06050000 .4byte .LASF85 + 4175 08f9 17050000 .4byte .LASF85 4176 08fd 01 .byte 0x1 4177 08fe 9606 .2byte 0x696 4178 0900 9B000000 .4byte 0x9b @@ -7239,7 +7239,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4199 0931 01 .byte 0x1 4200 0932 51090000 .4byte 0x951 4201 0936 0F .uleb128 0xf - 4202 0937 B3070000 .4byte .LASF87 + 4202 0937 C4070000 .4byte .LASF87 4203 093b 01 .byte 0x1 4204 093c C706 .2byte 0x6c7 4205 093e 90000000 .4byte 0x90 @@ -7251,21 +7251,21 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4211 0950 00 .byte 0 4212 0951 27 .uleb128 0x27 4213 0952 01 .byte 0x1 - 4214 0953 B7040000 .4byte .LASF88 + 4214 0953 C8040000 .4byte .LASF88 4215 0957 01 .byte 0x1 4216 0958 F804 .2byte 0x4f8 4217 095a 01 .byte 0x1 4218 095b 85000000 .4byte 0x85 4219 095f 00000000 .4byte .LFB28 4220 0963 6C000000 .4byte .LFE28 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 122 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 122 4221 0967 CA060000 .4byte .LLST47 4222 096b 01 .byte 0x1 4223 096c C4090000 .4byte 0x9c4 4224 0970 0F .uleb128 0xf - 4225 0971 79060000 .4byte .LASF64 + 4225 0971 8A060000 .4byte .LASF64 4226 0975 01 .byte 0x1 4227 0976 F804 .2byte 0x4f8 4228 0978 85000000 .4byte 0x85 @@ -7318,7 +7318,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4275 09d6 30070000 .4byte .LLST49 4276 09da 01 .byte 0x1 4277 09db 200A0000 .4byte 0xa20 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 123 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 123 4278 09df 2C .uleb128 0x2c @@ -7375,10 +7375,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4329 0a4a 00 .byte 0 4330 0a4b 18 .uleb128 0x18 4331 0a4c 01 .byte 0x1 - 4332 0a4d FA020000 .4byte .LASF91 + 4332 0a4d DA020000 .4byte .LASF91 4333 0a51 01 .byte 0x1 4334 0a52 1C07 .2byte 0x71c - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 124 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 124 4335 0a54 01 .byte 0x1 @@ -7390,13 +7390,13 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4341 0a60 01 .byte 0x1 4342 0a61 860A0000 .4byte 0xa86 4343 0a65 0F .uleb128 0xf - 4344 0a66 18040000 .4byte .LASF92 + 4344 0a66 29040000 .4byte .LASF92 4345 0a6a 01 .byte 0x1 4346 0a6b 1C07 .2byte 0x71c 4347 0a6d 85000000 .4byte 0x85 4348 0a71 A7070000 .4byte .LLST52 4349 0a75 0F .uleb128 0xf - 4350 0a76 6D060000 .4byte .LASF93 + 4350 0a76 7E060000 .4byte .LASF93 4351 0a7a 01 .byte 0x1 4352 0a7b 1C07 .2byte 0x71c 4353 0a7d 85000000 .4byte 0x85 @@ -7416,7 +7416,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4367 0a9b 01 .byte 0x1 4368 0a9c 19 .uleb128 0x19 4369 0a9d 01 .byte 0x1 - 4370 0a9e D3070000 .4byte .LASF95 + 4370 0a9e E4070000 .4byte .LASF95 4371 0aa2 01 .byte 0x1 4372 0aa3 5807 .2byte 0x758 4373 0aa5 01 .byte 0x1 @@ -7426,19 +7426,19 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4377 0ab2 01 .byte 0x1 4378 0ab3 E70A0000 .4byte 0xae7 4379 0ab7 0F .uleb128 0xf - 4380 0ab8 16020000 .4byte .LASF96 + 4380 0ab8 F6010000 .4byte .LASF96 4381 0abc 01 .byte 0x1 4382 0abd 5807 .2byte 0x758 4383 0abf 85000000 .4byte 0x85 4384 0ac3 09080000 .4byte .LLST55 4385 0ac7 0F .uleb128 0xf - 4386 0ac8 8F050000 .4byte .LASF97 + 4386 0ac8 A0050000 .4byte .LASF97 4387 0acc 01 .byte 0x1 4388 0acd 5807 .2byte 0x758 4389 0acf 85000000 .4byte 0x85 4390 0ad3 2A080000 .4byte .LLST56 4391 0ad7 2B .uleb128 0x2b - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 125 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 125 4392 0ad8 30000000 .4byte .LVL142 @@ -7452,7 +7452,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4400 0ae6 00 .byte 0 4401 0ae7 19 .uleb128 0x19 4402 0ae8 01 .byte 0x1 - 4403 0ae9 93020000 .4byte .LASF98 + 4403 0ae9 73020000 .4byte .LASF98 4404 0aed 01 .byte 0x1 4405 0aee 8A07 .2byte 0x78a 4406 0af0 01 .byte 0x1 @@ -7462,13 +7462,13 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4410 0afd 01 .byte 0x1 4411 0afe 320B0000 .4byte 0xb32 4412 0b02 0F .uleb128 0xf - 4413 0b03 16020000 .4byte .LASF96 + 4413 0b03 F6010000 .4byte .LASF96 4414 0b07 01 .byte 0x1 4415 0b08 8A07 .2byte 0x78a 4416 0b0a 85000000 .4byte 0x85 4417 0b0e 6B080000 .4byte .LLST58 4418 0b12 0F .uleb128 0xf - 4419 0b13 8F050000 .4byte .LASF97 + 4419 0b13 A0050000 .4byte .LASF97 4420 0b17 01 .byte 0x1 4421 0b18 8A07 .2byte 0x78a 4422 0b1a 85000000 .4byte 0x85 @@ -7485,7 +7485,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4433 0b31 00 .byte 0 4434 0b32 17 .uleb128 0x17 4435 0b33 01 .byte 0x1 - 4436 0b34 A0060000 .4byte .LASF99 + 4436 0b34 B1060000 .4byte .LASF99 4437 0b38 01 .byte 0x1 4438 0b39 B507 .2byte 0x7b5 4439 0b3b 01 .byte 0x1 @@ -7497,8 +7497,8 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4445 0b47 01 .byte 0x1 4446 0b48 17 .uleb128 0x17 4447 0b49 01 .byte 0x1 - 4448 0b4a B3060000 .4byte .LASF100 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 126 + 4448 0b4a C4060000 .4byte .LASF100 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 126 4449 0b4e 01 .byte 0x1 @@ -7512,7 +7512,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4457 0b5d 01 .byte 0x1 4458 0b5e 19 .uleb128 0x19 4459 0b5f 01 .byte 0x1 - 4460 0b60 C0070000 .4byte .LASF101 + 4460 0b60 D1070000 .4byte .LASF101 4461 0b64 01 .byte 0x1 4462 0b65 ED07 .2byte 0x7ed 4463 0b67 01 .byte 0x1 @@ -7534,7 +7534,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4479 0b89 00 .byte 0 4480 0b8a 17 .uleb128 0x17 4481 0b8b 01 .byte 0x1 - 4482 0b8c 14030000 .4byte .LASF102 + 4482 0b8c F4020000 .4byte .LASF102 4483 0b90 01 .byte 0x1 4484 0b91 0E08 .2byte 0x80e 4485 0b93 01 .byte 0x1 @@ -7546,7 +7546,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4491 0b9f 01 .byte 0x1 4492 0ba0 25 .uleb128 0x25 4493 0ba1 01 .byte 0x1 - 4494 0ba2 A6020000 .4byte .LASF103 + 4494 0ba2 86020000 .4byte .LASF103 4495 0ba6 01 .byte 0x1 4496 0ba7 2808 .2byte 0x828 4497 0ba9 01 .byte 0x1 @@ -7558,17 +7558,17 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4503 0bb8 00 .sleb128 0 4504 0bb9 01 .byte 0x1 4505 0bba DD0B0000 .4byte 0xbdd - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 127 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 127 4506 0bbe 0F .uleb128 0xf - 4507 0bbf 11020000 .4byte .LASF104 + 4507 0bbf F1010000 .4byte .LASF104 4508 0bc3 01 .byte 0x1 4509 0bc4 2808 .2byte 0x828 4510 0bc6 85000000 .4byte 0x85 4511 0bca CD080000 .4byte .LLST61 4512 0bce 10 .uleb128 0x10 - 4513 0bcf 3F070000 .4byte .LASF55 + 4513 0bcf 50070000 .4byte .LASF55 4514 0bd3 01 .byte 0x1 4515 0bd4 2A08 .2byte 0x82a 4516 0bd6 85000000 .4byte 0x85 @@ -7577,7 +7577,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4519 0bdc 00 .byte 0 4520 0bdd 27 .uleb128 0x27 4521 0bde 01 .byte 0x1 - 4522 0bdf 35040000 .4byte .LASF105 + 4522 0bdf 46040000 .4byte .LASF105 4523 0be3 01 .byte 0x1 4524 0be4 4508 .2byte 0x845 4525 0be6 01 .byte 0x1 @@ -7594,7 +7594,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4536 0c04 85000000 .4byte 0x85 4537 0c08 0E090000 .4byte .LLST63 4538 0c0c 10 .uleb128 0x10 - 4539 0c0d 32070000 .4byte .LASF106 + 4539 0c0d 43070000 .4byte .LASF106 4540 0c11 01 .byte 0x1 4541 0c12 4808 .2byte 0x848 4542 0c14 85000000 .4byte 0x85 @@ -7618,7 +7618,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4560 0c3f 1C000000 .4byte .LFE54 4561 0c43 21090000 .4byte .LLST64 4562 0c47 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 128 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 128 4563 0c48 7D0C0000 .4byte 0xc7d @@ -7644,7 +7644,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4583 0c7c 00 .byte 0 4584 0c7d 19 .uleb128 0x19 4585 0c7e 01 .byte 0x1 - 4586 0c7f CC060000 .4byte .LASF109 + 4586 0c7f DD060000 .4byte .LASF109 4587 0c83 01 .byte 0x1 4588 0c84 9408 .2byte 0x894 4589 0c86 01 .byte 0x1 @@ -7654,7 +7654,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4593 0c93 01 .byte 0x1 4594 0c94 CC0C0000 .4byte 0xccc 4595 0c98 0F .uleb128 0xf - 4596 0c99 11020000 .4byte .LASF104 + 4596 0c99 F1010000 .4byte .LASF104 4597 0c9d 01 .byte 0x1 4598 0c9e 9408 .2byte 0x894 4599 0ca0 9B000000 .4byte 0x9b @@ -7675,10 +7675,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4614 0ccb 00 .byte 0 4615 0ccc 19 .uleb128 0x19 4616 0ccd 01 .byte 0x1 - 4617 0cce 00060000 .4byte .LASF110 + 4617 0cce 11060000 .4byte .LASF110 4618 0cd2 01 .byte 0x1 4619 0cd3 BC08 .2byte 0x8bc - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 129 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 129 4620 0cd5 01 .byte 0x1 @@ -7703,7 +7703,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4639 0d0a 00 .byte 0 4640 0d0b 25 .uleb128 0x25 4641 0d0c 01 .byte 0x1 - 4642 0d0d AE030000 .4byte .LASF111 + 4642 0d0d 8E030000 .4byte .LASF111 4643 0d11 01 .byte 0x1 4644 0d12 0409 .2byte 0x904 4645 0d14 01 .byte 0x1 @@ -7716,13 +7716,13 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4652 0d24 01 .byte 0x1 4653 0d25 660D0000 .4byte 0xd66 4654 0d29 0F .uleb128 0xf - 4655 0d2a 3E030000 .4byte .LASF112 + 4655 0d2a 1E030000 .4byte .LASF112 4656 0d2e 01 .byte 0x1 4657 0d2f 0409 .2byte 0x904 4658 0d31 85000000 .4byte 0x85 4659 0d35 D8090000 .4byte .LLST71 4660 0d39 29 .uleb128 0x29 - 4661 0d3a 1E040000 .4byte .LASF113 + 4661 0d3a 2F040000 .4byte .LASF113 4662 0d3e 01 .byte 0x1 4663 0d3f 0409 .2byte 0x904 4664 0d41 EF000000 .4byte 0xef @@ -7738,7 +7738,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4674 0d55 1A .uleb128 0x1a 4675 0d56 00000000 .4byte .LASF115 4676 0d5a 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 130 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 130 4677 0d5b 0709 .2byte 0x907 @@ -7750,7 +7750,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4683 0d68 EF000000 .4byte 0xef 4684 0d6c 25 .uleb128 0x25 4685 0d6d 01 .byte 0x1 - 4686 0d6e 2D020000 .4byte .LASF116 + 4686 0d6e 0D020000 .4byte .LASF116 4687 0d72 01 .byte 0x1 4688 0d73 2509 .2byte 0x925 4689 0d75 01 .byte 0x1 @@ -7763,7 +7763,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4696 0d85 01 .byte 0x1 4697 0d86 AB0D0000 .4byte 0xdab 4698 0d8a 0F .uleb128 0xf - 4699 0d8b 3E030000 .4byte .LASF112 + 4699 0d8b 1E030000 .4byte .LASF112 4700 0d8f 01 .byte 0x1 4701 0d90 2509 .2byte 0x925 4702 0d92 85000000 .4byte 0x85 @@ -7777,7 +7777,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4710 0daa 00 .byte 0 4711 0dab 25 .uleb128 0x25 4712 0dac 01 .byte 0x1 - 4713 0dad 05030000 .4byte .LASF117 + 4713 0dad E5020000 .4byte .LASF117 4714 0db1 01 .byte 0x1 4715 0db2 3D09 .2byte 0x93d 4716 0db4 01 .byte 0x1 @@ -7790,15 +7790,15 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4723 0dc4 01 .byte 0x1 4724 0dc5 060E0000 .4byte 0xe06 4725 0dc9 0F .uleb128 0xf - 4726 0dca 3E030000 .4byte .LASF112 + 4726 0dca 1E030000 .4byte .LASF112 4727 0dce 01 .byte 0x1 4728 0dcf 3D09 .2byte 0x93d 4729 0dd1 85000000 .4byte 0x85 4730 0dd5 6D0A0000 .4byte .LLST75 4731 0dd9 29 .uleb128 0x29 - 4732 0dda 1E040000 .4byte .LASF113 + 4732 0dda 2F040000 .4byte .LASF113 4733 0dde 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 131 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 131 4734 0ddf 3D09 .2byte 0x93d @@ -7821,7 +7821,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4751 0e05 00 .byte 0 4752 0e06 25 .uleb128 0x25 4753 0e07 01 .byte 0x1 - 4754 0e08 F7040000 .4byte .LASF118 + 4754 0e08 08050000 .4byte .LASF118 4755 0e0c 01 .byte 0x1 4756 0e0d 5C09 .2byte 0x95c 4757 0e0f 01 .byte 0x1 @@ -7834,7 +7834,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4764 0e1f 01 .byte 0x1 4765 0e20 450E0000 .4byte 0xe45 4766 0e24 0F .uleb128 0xf - 4767 0e25 3E030000 .4byte .LASF112 + 4767 0e25 1E030000 .4byte .LASF112 4768 0e29 01 .byte 0x1 4769 0e2a 5C09 .2byte 0x95c 4770 0e2c 85000000 .4byte 0x85 @@ -7848,7 +7848,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4778 0e44 00 .byte 0 4779 0e45 18 .uleb128 0x18 4780 0e46 01 .byte 0x1 - 4781 0e47 80030000 .4byte .LASF119 + 4781 0e47 60030000 .4byte .LASF119 4782 0e4b 01 .byte 0x1 4783 0e4c 7409 .2byte 0x974 4784 0e4e 01 .byte 0x1 @@ -7858,18 +7858,18 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4788 0e58 7D .byte 0x7d 4789 0e59 00 .sleb128 0 4790 0e5a 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 132 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 132 4791 0e5b 800E0000 .4byte 0xe80 4792 0e5f 0F .uleb128 0xf - 4793 0e60 3E030000 .4byte .LASF112 + 4793 0e60 1E030000 .4byte .LASF112 4794 0e64 01 .byte 0x1 4795 0e65 7409 .2byte 0x974 4796 0e67 85000000 .4byte 0x85 4797 0e6b 020B0000 .4byte .LLST79 4798 0e6f 0F .uleb128 0xf - 4799 0e70 5C030000 .4byte .LASF120 + 4799 0e70 3C030000 .4byte .LASF120 4800 0e74 01 .byte 0x1 4801 0e75 7409 .2byte 0x974 4802 0e77 85000000 .4byte 0x85 @@ -7877,7 +7877,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4804 0e7f 00 .byte 0 4805 0e80 25 .uleb128 0x25 4806 0e81 01 .byte 0x1 - 4807 0e82 1C020000 .4byte .LASF121 + 4807 0e82 FC010000 .4byte .LASF121 4808 0e86 01 .byte 0x1 4809 0e87 8A09 .2byte 0x98a 4810 0e89 01 .byte 0x1 @@ -7890,13 +7890,13 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4817 0e99 01 .byte 0x1 4818 0e9a C10E0000 .4byte 0xec1 4819 0e9e 0F .uleb128 0xf - 4820 0e9f 3E030000 .4byte .LASF112 + 4820 0e9f 1E030000 .4byte .LASF112 4821 0ea3 01 .byte 0x1 4822 0ea4 8A09 .2byte 0x98a 4823 0ea6 85000000 .4byte 0x85 4824 0eaa 440B0000 .4byte .LLST81 4825 0eae 10 .uleb128 0x10 - 4826 0eaf 5C030000 .4byte .LASF120 + 4826 0eaf 3C030000 .4byte .LASF120 4827 0eb3 01 .byte 0x1 4828 0eb4 8C09 .2byte 0x98c 4829 0eb6 85000000 .4byte 0x85 @@ -7918,20 +7918,20 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4845 0ed3 18000000 .4byte .LFE63 4846 0ed7 02 .byte 0x2 4847 0ed8 7D .byte 0x7d - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 133 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 133 4848 0ed9 00 .sleb128 0 4849 0eda 01 .byte 0x1 4850 0edb 010F0000 .4byte 0xf01 4851 0edf 0F .uleb128 0xf - 4852 0ee0 3E030000 .4byte .LASF112 + 4852 0ee0 1E030000 .4byte .LASF112 4853 0ee4 01 .byte 0x1 4854 0ee5 A409 .2byte 0x9a4 4855 0ee7 85000000 .4byte 0x85 4856 0eeb 650B0000 .4byte .LLST82 4857 0eef 2E .uleb128 0x2e - 4858 0ef0 0D060000 .4byte .LASF123 + 4858 0ef0 1E060000 .4byte .LASF123 4859 0ef4 01 .byte 0x1 4860 0ef5 A609 .2byte 0x9a6 4861 0ef7 010F0000 .4byte 0xf01 @@ -7942,7 +7942,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4865 0f02 04 .byte 0x4 4866 0f03 DF000000 .4byte 0xdf 4867 0f07 2F .uleb128 0x2f - 4868 0f08 63040000 .4byte .LASF124 + 4868 0f08 74040000 .4byte .LASF124 4869 0f0c 01 .byte 0x1 4870 0f0d 1D .byte 0x1d 4871 0f0e 85000000 .4byte 0x85 @@ -7951,7 +7951,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4874 0f14 03 .byte 0x3 4875 0f15 00000000 .4byte CyResetStatus 4876 0f19 2F .uleb128 0x2f - 4877 0f1a 24050000 .4byte .LASF125 + 4877 0f1a 35050000 .4byte .LASF125 4878 0f1e 01 .byte 0x1 4879 0f1f 29 .byte 0x29 4880 0f20 9B000000 .4byte 0x9b @@ -7960,7 +7960,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4883 0f26 03 .byte 0x3 4884 0f27 00000000 .4byte cydelay_freq_hz 4885 0f2b 2F .uleb128 0x2f - 4886 0f2c E5030000 .4byte .LASF126 + 4886 0f2c F6030000 .4byte .LASF126 4887 0f30 01 .byte 0x1 4888 0f31 2A .byte 0x2a 4889 0f32 9B000000 .4byte 0x9b @@ -7978,10 +7978,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4901 0f4a 03 .byte 0x3 4902 0f4b 00000000 .4byte cydelay_freq_mhz 4903 0f4f 2F .uleb128 0x2f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 134 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 134 - 4904 0f50 23070000 .4byte .LASF128 + 4904 0f50 34070000 .4byte .LASF128 4905 0f54 01 .byte 0x1 4906 0f55 2C .byte 0x2c 4907 0f56 9B000000 .4byte 0x9b @@ -7991,7 +7991,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4911 0f5d 00000000 .4byte cydelay_32k_ms 4912 0f61 30 .uleb128 0x30 4913 0f62 01 .byte 0x1 - 4914 0f63 45030000 .4byte .LASF130 + 4914 0f63 25030000 .4byte .LASF130 4915 0f67 03 .byte 0x3 4916 0f68 7E .byte 0x7e 4917 0f69 01 .byte 0x1 @@ -7999,7 +7999,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4919 0f6e 01 .byte 0x1 4920 0f6f 31 .uleb128 0x31 4921 0f70 01 .byte 0x1 - 4922 0f71 D1040000 .4byte .LASF132 + 4922 0f71 E2040000 .4byte .LASF132 4923 0f75 03 .byte 0x3 4924 0f76 7F .byte 0x7f 4925 0f77 01 .byte 0x1 @@ -8010,7 +8010,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4930 0f82 00 .byte 0 4931 0f83 31 .uleb128 0x31 4932 0f84 01 .byte 0x1 - 4933 0f85 F1070000 .4byte .LASF133 + 4933 0f85 02080000 .4byte .LASF133 4934 0f89 04 .byte 0x4 4935 0f8a 2A .byte 0x2a 4936 0f8b 01 .byte 0x1 @@ -8021,7 +8021,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4941 0f96 00 .byte 0 4942 0f97 33 .uleb128 0x33 4943 0f98 01 .byte 0x1 - 4944 0f99 EC060000 .4byte .LASF140 + 4944 0f99 FD060000 .4byte .LASF140 4945 0f9d 04 .byte 0x4 4946 0f9e 26 .byte 0x26 4947 0f9f 01 .byte 0x1 @@ -8038,7 +8038,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 4958 0fb6 7A .byte 0x7a 4959 0fb7 01 .byte 0x1 4960 0fb8 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 135 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 135 4961 0fb9 32 .uleb128 0x32 @@ -8098,7 +8098,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 5015 0030 00 .byte 0 5016 0031 00 .byte 0 5017 0032 05 .uleb128 0x5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 136 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 136 5018 0033 0F .uleb128 0xf @@ -8158,7 +8158,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 5072 0069 20 .uleb128 0x20 5073 006a 0B .uleb128 0xb 5074 006b 01 .uleb128 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 137 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 137 5075 006c 13 .uleb128 0x13 @@ -8218,7 +8218,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 5129 00a2 0D .uleb128 0xd 5130 00a3 34 .uleb128 0x34 5131 00a4 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 138 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 138 5132 00a5 03 .uleb128 0x3 @@ -8278,7 +8278,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 5186 00dc 0B .uleb128 0xb 5187 00dd 3B .uleb128 0x3b 5188 00de 05 .uleb128 0x5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 139 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 139 5189 00df 49 .uleb128 0x49 @@ -8338,7 +8338,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 5243 0115 12 .uleb128 0x12 5244 0116 01 .uleb128 0x1 5245 0117 40 .uleb128 0x40 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 140 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 140 5246 0118 0A .uleb128 0xa @@ -8398,7 +8398,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 5300 0150 3B .uleb128 0x3b 5301 0151 05 .uleb128 0x5 5302 0152 27 .uleb128 0x27 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 141 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 141 5303 0153 0C .uleb128 0xc @@ -8458,7 +8458,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 5357 018b 06 .uleb128 0x6 5358 018c 9742 .uleb128 0x2117 5359 018e 0C .uleb128 0xc - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 142 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 142 5360 018f 01 .uleb128 0x1 @@ -8518,7 +8518,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 5414 01cf 0C .uleb128 0xc 5415 01d0 31 .uleb128 0x31 5416 01d1 13 .uleb128 0x13 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 143 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 143 5417 01d2 00 .byte 0 @@ -8578,7 +8578,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 5471 0209 23 .uleb128 0x23 5472 020a 2E .uleb128 0x2e 5473 020b 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 144 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 144 5474 020c 3F .uleb128 0x3f @@ -8638,7 +8638,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 5528 0243 11 .uleb128 0x11 5529 0244 01 .uleb128 0x1 5530 0245 12 .uleb128 0x12 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 145 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 145 5531 0246 01 .uleb128 0x1 @@ -8698,7 +8698,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 5585 027f 3F .uleb128 0x3f 5586 0280 0C .uleb128 0xc 5587 0281 03 .uleb128 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 146 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 146 5588 0282 0E .uleb128 0xe @@ -8758,7 +8758,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 5642 02be 2C .uleb128 0x2c 5643 02bf 34 .uleb128 0x34 5644 02c0 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 147 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 147 5645 02c1 03 .uleb128 0x3 @@ -8818,7 +8818,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 5699 02f7 0C .uleb128 0xc 5700 02f8 02 .uleb128 0x2 5701 02f9 0A .uleb128 0xa - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 148 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 148 5702 02fa 00 .byte 0 @@ -8878,7 +8878,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 5756 0330 3A .uleb128 0x3a 5757 0331 0B .uleb128 0xb 5758 0332 3B .uleb128 0x3b - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 149 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 149 5759 0333 0B .uleb128 0xb @@ -8938,7 +8938,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 5813 0032 00000000 .4byte 0 5814 0036 00000000 .4byte 0 5815 .LLST1: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 150 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 150 5816 003a 00000000 .4byte .LVL0 @@ -8998,7 +8998,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 5870 00be 01 .uleb128 0x1 5871 00bf 51 .byte 0x51 5872 00c0 9F .byte 0x9f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 151 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 151 5873 00c1 00000000 .4byte 0 @@ -9058,7 +9058,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 5927 0141 34000000 .4byte .LVL19 5928 0145 0100 .2byte 0x1 5929 0147 50 .byte 0x50 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 152 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 152 5930 0148 34000000 .4byte .LVL19 @@ -9118,7 +9118,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 5984 01cd 06000000 .4byte .LVL33 5985 01d1 0100 .2byte 0x1 5986 01d3 50 .byte 0x50 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 153 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 153 5987 01d4 06000000 .4byte .LVL33 @@ -9178,7 +9178,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 6041 0256 FF .byte 0xff 6042 0257 1A .byte 0x1a 6043 0258 38 .byte 0x38 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 154 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 154 6044 0259 24 .byte 0x24 @@ -9238,7 +9238,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 6098 02bc 9F .byte 0x9f 6099 02bd 00000000 .4byte 0 6100 02c1 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 155 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 155 6101 .LLST18: @@ -9298,7 +9298,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 6155 0349 00000000 .4byte 0 6156 .LLST23: 6157 034d 26000000 .4byte .LVL57 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 156 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 156 6158 0351 46000000 .4byte .LVL63 @@ -9358,7 +9358,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 6212 .LLST27: 6213 03d8 00000000 .4byte .LVL64 6214 03dc 26000000 .4byte .LVL69 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 157 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 157 6215 03e0 0200 .2byte 0x2 @@ -9418,7 +9418,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 6269 046d 18000000 .4byte .LFE23 6270 0471 0400 .2byte 0x4 6271 0473 F3 .byte 0xf3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 158 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 158 6272 0474 01 .uleb128 0x1 @@ -9478,7 +9478,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 6326 04f6 00000000 .4byte .LVL80 6327 04fa 24000000 .4byte .LVL86 6328 04fe 0200 .2byte 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 159 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 159 6329 0500 30 .byte 0x30 @@ -9538,7 +9538,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 6383 058b 7E000000 .4byte .LVL103 6384 058f 0100 .2byte 0x1 6385 0591 50 .byte 0x50 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 160 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 160 6386 0592 7E000000 .4byte .LVL103 @@ -9598,7 +9598,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 6440 0620 9F .byte 0x9f 6441 0621 00000000 .4byte 0 6442 0625 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 161 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 161 6443 .LLST42: @@ -9658,7 +9658,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 6497 06ad 06000000 .4byte .LVL117 6498 06b1 0100 .2byte 0x1 6499 06b3 50 .byte 0x50 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 162 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 162 6500 06b4 06000000 .4byte .LVL117 @@ -9718,7 +9718,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 6554 0734 02000000 .4byte .LCFI7 6555 0738 0200 .2byte 0x2 6556 073a 7D .byte 0x7d - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 163 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 163 6557 073b 00 .sleb128 0 @@ -9778,7 +9778,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 6611 07bf 9F .byte 0x9f 6612 07c0 00000000 .4byte 0 6613 07c4 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 164 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 164 6614 .LLST53: @@ -9838,7 +9838,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 6668 0847 00000000 .4byte 0 6669 .LLST57: 6670 084b 00000000 .4byte .LFB47 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 165 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 165 6671 084f 02000000 .4byte .LCFI9 @@ -9898,7 +9898,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 6725 08d1 0A000000 .4byte .LVL150 6726 08d5 0100 .2byte 0x1 6727 08d7 50 .byte 0x50 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 166 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 166 6728 08d8 0A000000 .4byte .LVL150 @@ -9958,7 +9958,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 6782 095f 00 .sleb128 0 6783 0960 02000000 .4byte .LCFI13 6784 0964 18000000 .4byte .LFE55 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 167 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 167 6785 0968 0200 .2byte 0x2 @@ -10018,7 +10018,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 6839 09f0 9F .byte 0x9f 6840 09f1 00000000 .4byte 0 6841 09f5 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 168 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 168 6842 .LLST72: @@ -10078,7 +10078,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 6894 0a82 F3 .byte 0xf3 6895 0a83 01 .uleb128 0x1 6896 0a84 50 .byte 0x50 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 169 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 169 6897 0a85 9F .byte 0x9f @@ -10138,7 +10138,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 6949 0b0d 04000000 .4byte .LVL178 6950 0b11 14000000 .4byte .LFE61 6951 0b15 0400 .2byte 0x4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 170 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 170 6952 0b17 F3 .byte 0xf3 @@ -10198,7 +10198,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 7006 000c 0000 .2byte 0 7007 000e 0000 .2byte 0 7008 0010 00000000 .4byte .LFB7 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 171 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 171 7009 0014 B8000000 .4byte .LFE7-.LFB7 @@ -10258,7 +10258,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 7063 00ec 10000000 .4byte .LFE30-.LFB30 7064 00f0 00000000 .4byte .LFB31 7065 00f4 10000000 .4byte .LFE31-.LFB31 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 172 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 172 7066 00f8 00000000 .4byte .LFB32 @@ -10318,7 +10318,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 7120 01d0 00000000 .4byte .LFB57 7121 01d4 18000000 .4byte .LFE57-.LFB57 7122 01d8 00000000 .4byte .LFB58 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 173 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 173 7123 01dc 14000000 .4byte .LFE58-.LFB58 @@ -10378,7 +10378,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 7177 009c 68000000 .4byte .LFE0 7178 00a0 00000000 .4byte .LFB21 7179 00a4 10000000 .4byte .LFE21 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 174 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 174 7180 00a8 00000000 .4byte .LFB22 @@ -10438,7 +10438,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 7234 0180 00000000 .4byte .LFB49 7235 0184 24000000 .4byte .LFE49 7236 0188 00000000 .4byte .LFB50 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 175 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 175 7237 018c 44000000 .4byte .LFE50 @@ -10498,7 +10498,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 7278 7A456E61 7278 626C6500 7279 .LASF74: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 176 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 176 7280 0035 43795854 .ascii "CyXTAL_DisableErrStatus\000" @@ -10558,7 +10558,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 7300 6D56616C 7300 756500 7301 .LASF127: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 177 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 177 7302 00ec 63796465 .ascii "cydelay_freq_mhz\000" @@ -10618,7 +10618,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 7326 74536F75 7326 72636500 7327 .LASF18: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 178 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 178 7328 0187 72656731 .ascii "reg16\000" @@ -10660,532 +10660,533 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 1 7346 6C617943 7346 79636C65 7346 7300 - 7347 .LASF136: - 7348 01f1 573A5C53 .ascii "W:\\SCSI2SD\\USB_Bootloader.cydsn\000" - 7348 43534932 - 7348 53445C55 - 7348 53425F42 - 7348 6F6F746C - 7349 .LASF104: - 7350 0211 6D61736B .ascii "mask\000" - 7350 00 - 7351 .LASF96: - 7352 0216 72657365 .ascii "reset\000" - 7352 7400 - 7353 .LASF121: - 7354 021c 4379496E .ascii "CyIntGetPriority\000" + 7347 .LASF104: + 7348 01f1 6D61736B .ascii "mask\000" + 7348 00 + 7349 .LASF96: + 7350 01f6 72657365 .ascii "reset\000" + 7350 7400 + 7351 .LASF121: + 7352 01fc 4379496E .ascii "CyIntGetPriority\000" + 7352 74476574 + 7352 5072696F + 7352 72697479 + 7352 00 + 7353 .LASF116: + 7354 020d 4379496E .ascii "CyIntGetSysVector\000" 7354 74476574 - 7354 5072696F - 7354 72697479 - 7354 00 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 179 - - - 7355 .LASF116: - 7356 022d 4379496E .ascii "CyIntGetSysVector\000" - 7356 74476574 - 7356 53797356 - 7356 6563746F - 7356 7200 - 7357 .LASF4: - 7358 023f 756E7369 .ascii "unsigned int\000" - 7358 676E6564 - 7358 20696E74 - 7358 00 - 7359 .LASF33: - 7360 024c 4379494D .ascii "CyIMO_SetSource\000" - 7360 4F5F5365 - 7360 74536F75 - 7360 72636500 - 7361 .LASF43: - 7362 025c 62757343 .ascii "busClkDiv\000" - 7362 6C6B4469 - 7362 7600 - 7363 .LASF137: - 7364 0266 43795553 .ascii "CyUSB_PowerOnCheck\000" - 7364 425F506F - 7364 7765724F - 7364 6E436865 - 7364 636B00 - 7365 .LASF9: - 7366 0279 6C6F6E67 .ascii "long unsigned int\000" - 7366 20756E73 - 7366 69676E65 - 7366 6420696E - 7366 7400 - 7367 .LASF68: - 7368 028b 74696D65 .ascii "timeout\000" - 7368 6F757400 - 7369 .LASF98: - 7370 0293 43795664 .ascii "CyVdLvAnalogEnable\000" - 7370 4C76416E - 7370 616C6F67 - 7370 456E6162 - 7370 6C6500 - 7371 .LASF103: - 7372 02a6 43795664 .ascii "CyVdStickyStatus\000" - 7372 53746963 - 7372 6B795374 - 7372 61747573 - 7372 00 - 7373 .LASF66: - 7374 02b7 43795854 .ascii "CyXTAL_32KHZ_Stop\000" - 7374 414C5F33 - 7374 324B485A - 7374 5F53746F - 7374 7000 - 7375 .LASF63: - 7376 02c9 4379494C .ascii "CyILO_SetPowerMode\000" - 7376 4F5F5365 - 7376 74506F77 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 180 - - - 7376 65724D6F - 7376 646500 - 7377 .LASF32: - 7378 02dc 4379494D .ascii "CyIMO_Stop\000" - 7378 4F5F5374 - 7378 6F7000 - 7379 .LASF3: - 7380 02e7 73686F72 .ascii "short unsigned int\000" - 7380 7420756E - 7380 7369676E - 7380 65642069 - 7380 6E7400 - 7381 .LASF91: - 7382 02fa 43795764 .ascii "CyWdtStart\000" - 7382 74537461 - 7382 727400 - 7383 .LASF117: - 7384 0305 4379496E .ascii "CyIntSetVector\000" - 7384 74536574 - 7384 56656374 - 7384 6F7200 - 7385 .LASF102: - 7386 0314 43795664 .ascii "CyVdHvAnalogDisable\000" - 7386 4876416E - 7386 616C6F67 - 7386 44697361 - 7386 626C6500 - 7387 .LASF40: - 7388 0328 43794D61 .ascii "CyMasterClk_SetSource\000" - 7388 73746572 - 7388 436C6B5F - 7388 53657453 - 7388 6F757263 - 7389 .LASF112: - 7390 033e 6E756D62 .ascii "number\000" - 7390 657200 - 7391 .LASF130: - 7392 0345 4379456E .ascii "CyEnterCriticalSection\000" - 7392 74657243 - 7392 72697469 - 7392 63616C53 - 7392 65637469 - 7393 .LASF120: - 7394 035c 7072696F .ascii "priority\000" - 7394 72697479 - 7394 00 - 7395 .LASF75: - 7396 0365 43795854 .ascii "CyXTAL_EnableFaultRecovery\000" - 7396 414C5F45 - 7396 6E61626C - 7396 65466175 - 7396 6C745265 - 7397 .LASF119: - 7398 0380 4379496E .ascii "CyIntSetPriority\000" - 7398 74536574 - 7398 5072696F - 7398 72697479 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 181 - - - 7398 00 - 7399 .LASF22: - 7400 0391 43794275 .ascii "CyBusClk_Internal_SetDivider\000" - 7400 73436C6B - 7400 5F496E74 - 7400 65726E61 - 7400 6C5F5365 - 7401 .LASF111: - 7402 03ae 4379496E .ascii "CyIntSetSysVector\000" - 7402 74536574 - 7402 53797356 - 7402 6563746F - 7402 7200 - 7403 .LASF67: - 7404 03c0 43795854 .ascii "CyXTAL_Start\000" - 7404 414C5F53 - 7404 74617274 - 7404 00 - 7405 .LASF19: - 7406 03cd 72656733 .ascii "reg32\000" - 7406 3200 - 7407 .LASF139: - 7408 03d3 43795854 .ascii "CyXTAL_ReadStatus\000" - 7408 414C5F52 - 7408 65616453 - 7408 74617475 - 7408 7300 - 7409 .LASF126: - 7410 03e5 63796465 .ascii "cydelay_freq_khz\000" - 7410 6C61795F - 7410 66726571 - 7410 5F6B687A - 7410 00 - 7411 .LASF30: - 7412 03f6 736F7572 .ascii "source\000" - 7412 636500 - 7413 .LASF8: - 7414 03fd 73697A65 .ascii "sizetype\000" - 7414 74797065 - 7414 00 - 7415 .LASF77: - 7416 0406 43795854 .ascii "CyXTAL_SetStartup\000" - 7416 414C5F53 - 7416 65745374 - 7416 61727475 - 7416 7000 - 7417 .LASF92: - 7418 0418 7469636B .ascii "ticks\000" - 7418 7300 - 7419 .LASF113: - 7420 041e 61646472 .ascii "address\000" - 7420 65737300 - 7421 .LASF31: - 7422 0426 4379504C .ascii "CyPLL_OUT_Stop\000" - 7422 4C5F4F55 - 7422 545F5374 - 7422 6F7000 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 182 - - - 7423 .LASF105: - 7424 0435 43795664 .ascii "CyVdRealTimeStatus\000" - 7424 5265616C - 7424 54696D65 - 7424 53746174 - 7424 757300 - 7425 .LASF48: - 7426 0448 4379494C .ascii "CyILO_Start100K\000" - 7426 4F5F5374 - 7426 61727431 - 7426 30304B00 - 7427 .LASF37: - 7428 0458 75736250 .ascii "usbPowerOn\000" - 7428 6F776572 - 7428 4F6E00 - 7429 .LASF124: - 7430 0463 43795265 .ascii "CyResetStatus\000" - 7430 73657453 - 7430 74617475 - 7430 7300 - 7431 .LASF135: - 7432 0471 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\CyLib.c\000" - 7432 6E657261 - 7432 7465645F - 7432 536F7572 - 7432 63655C50 - 7433 .LASF131: - 7434 0492 43794D61 .ascii "CyMasterClk_SetDivider\000" - 7434 73746572 - 7434 436C6B5F - 7434 53657444 - 7434 69766964 - 7435 .LASF27: - 7436 04a9 63757272 .ascii "current\000" - 7436 656E7400 - 7437 .LASF14: - 7438 04b1 666C6F61 .ascii "float\000" - 7438 7400 - 7439 .LASF88: - 7440 04b7 43795854 .ascii "CyXTAL_32KHZ_SetPowerMode\000" - 7440 414C5F33 - 7440 324B485A - 7440 5F536574 - 7440 506F7765 - 7441 .LASF132: - 7442 04d1 43794578 .ascii "CyExitCriticalSection\000" - 7442 69744372 - 7442 69746963 - 7442 616C5365 - 7442 6374696F - 7443 .LASF59: - 7444 04e7 4379494C .ascii "CyILO_Enable33K\000" - 7444 4F5F456E - 7444 61626C65 - 7444 33334B00 - 7445 .LASF118: - 7446 04f7 4379496E .ascii "CyIntGetVector\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 183 - - - 7446 74476574 - 7446 56656374 - 7446 6F7200 - 7447 .LASF85: - 7448 0506 6D696C6C .ascii "milliseconds\000" - 7448 69736563 - 7448 6F6E6473 - 7448 00 - 7449 .LASF60: - 7450 0513 4379494C .ascii "CyILO_Disable33K\000" - 7450 4F5F4469 - 7450 7361626C - 7450 6533334B - 7450 00 - 7451 .LASF125: - 7452 0524 63796465 .ascii "cydelay_freq_hz\000" - 7452 6C61795F - 7452 66726571 - 7452 5F687A00 - 7453 .LASF42: - 7454 0534 6D617374 .ascii "masterClkDiv\000" - 7454 6572436C - 7454 6B446976 - 7454 00 - 7455 .LASF134: - 7456 0541 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 7456 4320342E - 7456 372E3320 - 7456 32303133 - 7456 30333132 - 7457 0574 616E6368 .ascii "anch revision 196615]\000" - 7457 20726576 - 7457 6973696F - 7457 6E203139 - 7457 36363135 - 7458 .LASF17: - 7459 058a 72656738 .ascii "reg8\000" - 7459 00 - 7460 .LASF97: - 7461 058f 74687265 .ascii "threshold\000" - 7461 73686F6C - 7461 6400 - 7462 .LASF81: - 7463 0599 43794861 .ascii "CyHalt\000" - 7463 6C7400 - 7464 .LASF80: - 7465 05a0 43795854 .ascii "CyXTAL_SetWdVoltage\000" - 7465 414C5F53 - 7465 65745764 - 7465 566F6C74 - 7465 61676500 - 7466 .LASF1: - 7467 05b4 756E7369 .ascii "unsigned char\000" - 7467 676E6564 - 7467 20636861 - 7467 7200 - 7468 .LASF58: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 184 - - - 7469 05c2 706D5477 .ascii "pmTwCfg2State\000" - 7469 43666732 - 7469 53746174 - 7469 6500 - 7470 .LASF2: - 7471 05d0 73686F72 .ascii "short int\000" - 7471 7420696E - 7471 7400 - 7472 .LASF56: - 7473 05da 696C6F45 .ascii "iloEnableState\000" - 7473 6E61626C - 7473 65537461 - 7473 746500 - 7474 .LASF73: - 7475 05e9 43795854 .ascii "CyXTAL_EnableErrStatus\000" - 7475 414C5F45 - 7475 6E61626C - 7475 65457272 - 7475 53746174 - 7476 .LASF110: - 7477 0600 4379466C .ascii "CyFlushCache\000" - 7477 75736843 - 7477 61636865 - 7477 00 - 7478 .LASF123: - 7479 060d 73746174 .ascii "stateReg\000" - 7479 65526567 - 7479 00 - 7480 .LASF138: - 7481 0616 706F7765 .ascii "poweredOn\000" - 7481 7265644F - 7481 6E00 - 7482 .LASF76: - 7483 0620 43795854 .ascii "CyXTAL_DisableFaultRecovery\000" - 7483 414C5F44 - 7483 69736162 - 7483 6C654661 - 7483 756C7452 - 7484 .LASF82: - 7485 063c 72656173 .ascii "reason\000" - 7485 6F6E00 - 7486 .LASF79: - 7487 0643 43795854 .ascii "CyXTAL_SetFbVoltage\000" - 7487 414C5F53 - 7487 65744662 - 7487 566F6C74 - 7487 61676500 - 7488 .LASF52: - 7489 0657 706D4674 .ascii "pmFtwCfg2Reg\000" - 7489 77436667 - 7489 32526567 - 7489 00 - 7490 .LASF39: - 7491 0664 6E657874 .ascii "nextFreq\000" - 7491 46726571 - 7491 00 - 7492 .LASF93: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAOLfnb.s page 185 - - - 7493 066d 6C704D6F .ascii "lpMode\000" - 7493 646500 - 7494 .LASF10: - 7495 0674 63686172 .ascii "char\000" - 7495 00 - 7496 .LASF64: - 7497 0679 6D6F6465 .ascii "mode\000" - 7497 00 - 7498 .LASF20: - 7499 067e 63796973 .ascii "cyisraddress\000" - 7499 72616464 - 7499 72657373 - 7499 00 - 7500 .LASF35: - 7501 068b 4379494D .ascii "CyIMO_DisableDoubler\000" - 7501 4F5F4469 - 7501 7361626C - 7501 65446F75 - 7501 626C6572 - 7502 .LASF99: - 7503 06a0 43795664 .ascii "CyVdLvDigitDisable\000" - 7503 4C764469 - 7503 67697444 - 7503 69736162 - 7503 6C6500 - 7504 .LASF100: - 7505 06b3 43795664 .ascii "CyVdLvAnalogDisable\000" - 7505 4C76416E - 7505 616C6F67 - 7505 44697361 - 7505 626C6500 - 7506 .LASF26: - 7507 06c7 71446976 .ascii "qDiv\000" - 7507 00 - 7508 .LASF109: - 7509 06cc 4379456E .ascii "CyEnableInts\000" - 7509 61626C65 - 7509 496E7473 - 7509 00 - 7510 .LASF45: - 7511 06d9 43795573 .ascii "CyUsbClk_SetSource\000" - 7511 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7548 .LASF95: - 7549 07d3 43795664 .ascii "CyVdLvDigitEnable\000" - 7549 4C764469 - 7549 67697445 - 7549 6E61626C - 7549 6500 - 7550 .LASF72: - 7551 07e5 43795854 .ascii "CyXTAL_Stop\000" - 7551 414C5F53 - 7551 746F7000 - 7552 .LASF133: - 7553 07f1 4379506D .ascii "CyPmFtwSetInterval\000" - 7553 46747753 - 7553 6574496E - 7553 74657276 - 7553 616C00 - 7554 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br + 7354 53797356 + 7354 6563746F + 7354 7200 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 179 + + + 7355 .LASF4: + 7356 021f 756E7369 .ascii "unsigned int\000" + 7356 676E6564 + 7356 20696E74 + 7356 00 + 7357 .LASF33: + 7358 022c 4379494D .ascii "CyIMO_SetSource\000" + 7358 4F5F5365 + 7358 74536F75 + 7358 72636500 + 7359 .LASF43: + 7360 023c 62757343 .ascii "busClkDiv\000" + 7360 6C6B4469 + 7360 7600 + 7361 .LASF137: + 7362 0246 43795553 .ascii "CyUSB_PowerOnCheck\000" + 7362 425F506F + 7362 7765724F + 7362 6E436865 + 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"CyIntSetPriority\000" + 7396 74536574 + 7396 5072696F + 7396 72697479 + 7396 00 + 7397 .LASF22: + 7398 0371 43794275 .ascii "CyBusClk_Internal_SetDivider\000" + 7398 73436C6B + 7398 5F496E74 + 7398 65726E61 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 181 + + + 7398 6C5F5365 + 7399 .LASF111: + 7400 038e 4379496E .ascii "CyIntSetSysVector\000" + 7400 74536574 + 7400 53797356 + 7400 6563746F + 7400 7200 + 7401 .LASF136: + 7402 03a0 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" + 7402 43534932 + 7402 53445C73 + 7402 6F667477 + 7402 6172655C + 7403 03cf 6E00 .ascii "n\000" + 7404 .LASF67: + 7405 03d1 43795854 .ascii "CyXTAL_Start\000" + 7405 414C5F53 + 7405 74617274 + 7405 00 + 7406 .LASF19: + 7407 03de 72656733 .ascii "reg32\000" + 7407 3200 + 7408 .LASF139: + 7409 03e4 43795854 .ascii "CyXTAL_ReadStatus\000" + 7409 414C5F52 + 7409 65616453 + 7409 74617475 + 7409 7300 + 7410 .LASF126: + 7411 03f6 63796465 .ascii "cydelay_freq_khz\000" + 7411 6C61795F + 7411 66726571 + 7411 5F6B687A + 7411 00 + 7412 .LASF30: + 7413 0407 736F7572 .ascii "source\000" + 7413 636500 + 7414 .LASF8: + 7415 040e 73697A65 .ascii "sizetype\000" + 7415 74797065 + 7415 00 + 7416 .LASF77: + 7417 0417 43795854 .ascii "CyXTAL_SetStartup\000" + 7417 414C5F53 + 7417 65745374 + 7417 61727475 + 7417 7000 + 7418 .LASF92: + 7419 0429 7469636B .ascii "ticks\000" + 7419 7300 + 7420 .LASF113: + 7421 042f 61646472 .ascii "address\000" + 7421 65737300 + 7422 .LASF31: + 7423 0437 4379504C .ascii "CyPLL_OUT_Stop\000" + 7423 4C5F4F55 + 7423 545F5374 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 182 + + + 7423 6F7000 + 7424 .LASF105: + 7425 0446 43795664 .ascii "CyVdRealTimeStatus\000" + 7425 5265616C + 7425 54696D65 + 7425 53746174 + 7425 757300 + 7426 .LASF48: + 7427 0459 4379494C .ascii "CyILO_Start100K\000" + 7427 4F5F5374 + 7427 61727431 + 7427 30304B00 + 7428 .LASF37: + 7429 0469 75736250 .ascii "usbPowerOn\000" + 7429 6F776572 + 7429 4F6E00 + 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C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 183 + + + 7447 0508 4379496E .ascii "CyIntGetVector\000" + 7447 74476574 + 7447 56656374 + 7447 6F7200 + 7448 .LASF85: + 7449 0517 6D696C6C .ascii "milliseconds\000" + 7449 69736563 + 7449 6F6E6473 + 7449 00 + 7450 .LASF60: + 7451 0524 4379494C .ascii "CyILO_Disable33K\000" + 7451 4F5F4469 + 7451 7361626C + 7451 6533334B + 7451 00 + 7452 .LASF125: + 7453 0535 63796465 .ascii "cydelay_freq_hz\000" + 7453 6C61795F + 7453 66726571 + 7453 5F687A00 + 7454 .LASF42: + 7455 0545 6D617374 .ascii "masterClkDiv\000" + 7455 6572436C + 7455 6B446976 + 7455 00 + 7456 .LASF134: + 7457 0552 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" + 7457 4320342E + 7457 372E3320 + 7457 32303133 + 7457 30333132 + 7458 0585 616E6368 .ascii "anch revision 196615]\000" + 7458 20726576 + 7458 6973696F + 7458 6E203139 + 7458 36363135 + 7459 .LASF17: + 7460 059b 72656738 .ascii "reg8\000" + 7460 00 + 7461 .LASF97: + 7462 05a0 74687265 .ascii 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061e 73746174 .ascii "stateReg\000" + 7480 65526567 + 7480 00 + 7481 .LASF138: + 7482 0627 706F7765 .ascii "poweredOn\000" + 7482 7265644F + 7482 6E00 + 7483 .LASF76: + 7484 0631 43795854 .ascii "CyXTAL_DisableFaultRecovery\000" + 7484 414C5F44 + 7484 69736162 + 7484 6C654661 + 7484 756C7452 + 7485 .LASF82: + 7486 064d 72656173 .ascii "reason\000" + 7486 6F6E00 + 7487 .LASF79: + 7488 0654 43795854 .ascii "CyXTAL_SetFbVoltage\000" + 7488 414C5F53 + 7488 65744662 + 7488 566F6C74 + 7488 61676500 + 7489 .LASF52: + 7490 0668 706D4674 .ascii "pmFtwCfg2Reg\000" + 7490 77436667 + 7490 32526567 + 7490 00 + 7491 .LASF39: + 7492 0675 6E657874 .ascii "nextFreq\000" + 7492 46726571 + 7492 00 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 185 + + + 7493 .LASF93: + 7494 067e 6C704D6F .ascii "lpMode\000" + 7494 646500 + 7495 .LASF10: + 7496 0685 63686172 .ascii "char\000" + 7496 00 + 7497 .LASF64: + 7498 068a 6D6F6465 .ascii "mode\000" + 7498 00 + 7499 .LASF20: + 7500 068f 63796973 .ascii "cyisraddress\000" + 7500 72616464 + 7500 72657373 + 7500 00 + 7501 .LASF35: + 7502 069c 4379494D .ascii "CyIMO_DisableDoubler\000" + 7502 4F5F4469 + 7502 7361626C + 7502 65446F75 + 7502 626C6572 + 7503 .LASF99: + 7504 06b1 43795664 .ascii "CyVdLvDigitDisable\000" + 7504 4C764469 + 7504 67697444 + 7504 69736162 + 7504 6C6500 + 7505 .LASF100: + 7506 06c4 43795664 .ascii "CyVdLvAnalogDisable\000" + 7506 4C76416E + 7506 616C6F67 + 7506 44697361 + 7506 626C6500 + 7507 .LASF26: + 7508 06d8 71446976 .ascii "qDiv\000" + 7508 00 + 7509 .LASF109: + 7510 06dd 4379456E .ascii "CyEnableInts\000" + 7510 61626C65 + 7510 496E7473 + 7510 00 + 7511 .LASF45: + 7512 06ea 43795573 .ascii "CyUsbClk_SetSource\000" + 7512 62436C6B + 7512 5F536574 + 7512 536F7572 + 7512 636500 + 7513 .LASF140: + 7514 06fd 4379506D .ascii "CyPmReadStatus\000" + 7514 52656164 + 7514 53746174 + 7514 757300 + 7515 .LASF38: + 7516 070c 63757272 .ascii "currentFreq\000" + 7516 656E7446 + 7516 72657100 + 7517 .LASF84: + 7518 0718 43794465 .ascii "CyDelay\000" + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 186 + + + 7518 6C617900 + 7519 .LASF41: + 7520 0720 43794275 .ascii "CyBusClk_SetDivider\000" + 7520 73436C6B + 7520 5F536574 + 7520 44697669 + 7520 64657200 + 7521 .LASF128: + 7522 0734 63796465 .ascii "cydelay_32k_ms\000" + 7522 6C61795F + 7522 33326B5F + 7522 6D7300 + 7523 .LASF106: + 7524 0743 7664466C .ascii "vdFlagsState\000" + 7524 61677353 + 7524 74617465 + 7524 00 + 7525 .LASF55: + 7526 0750 73746174 .ascii "status\000" + 7526 757300 + 7527 .LASF61: + 7528 0757 4379494C .ascii "CyILO_SetSource\000" + 7528 4F5F5365 + 7528 74536F75 + 7528 72636500 + 7529 .LASF25: + 7530 0767 70446976 .ascii "pDiv\000" + 7530 00 + 7531 .LASF36: + 7532 076c 4379494D .ascii "CyIMO_SetFreq\000" + 7532 4F5F5365 + 7532 74467265 + 7532 7100 + 7533 .LASF129: + 7534 077a 43795854 .ascii "CyXTAL_32KHZ_ReadStatus\000" + 7534 414C5F33 + 7534 324B485A + 7534 5F526561 + 7534 64537461 + 7535 .LASF71: + 7536 0792 706D5477 .ascii "pmTwCfg2Tmp\000" + 7536 43666732 + 7536 546D7000 + 7537 .LASF24: + 7538 079e 64697669 .ascii "divider\000" + 7538 64657200 + 7539 .LASF16: + 7540 07a6 63797374 .ascii "cystatus\000" + 7540 61747573 + 7540 00 + 7541 .LASF78: + 7542 07af 73657474 .ascii "setting\000" + 7542 696E6700 + 7543 .LASF53: + 7544 07b7 706D4674 .ascii "pmFtwCfg0Reg\000" + 7544 77436667 + 7544 30526567 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 187 + + + 7544 00 + 7545 .LASF87: + 7546 07c4 6D696372 .ascii "microseconds\000" + 7546 6F736563 + 7546 6F6E6473 + 7546 00 + 7547 .LASF101: + 7548 07d1 43795664 .ascii "CyVdHvAnalogEnable\000" + 7548 4876416E + 7548 616C6F67 + 7548 456E6162 + 7548 6C6500 + 7549 .LASF95: + 7550 07e4 43795664 .ascii "CyVdLvDigitEnable\000" + 7550 4C764469 + 7550 67697445 + 7550 6E61626C + 7550 6500 + 7551 .LASF72: + 7552 07f6 43795854 .ascii "CyXTAL_Stop\000" + 7552 414C5F53 + 7552 746F7000 + 7553 .LASF133: + 7554 0802 4379506D .ascii "CyPmFtwSetInterval\000" + 7554 46747753 + 7554 6574496E + 7554 74657276 + 7554 616C00 + 7555 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyLib.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyLib.o index c821c2123af8ec928d72a1c5b4ac926b32911ed0..61d6a5b1dde81348c47ad72cf4d1ae10f838b14b 100755 GIT binary patch delta 1851 zcmZ8hdu&r>6u;;8-nCob>$-cpb&rOPu3NV;W&>F|fw0Z-vU@={1jIjvn-eB7oKYBy zWD8jc5Y8edJhlYH$6|m~BT>l=5iu$OLrkVlL^I=nsDYRT&4`}!T?URO{l0t7`JLbI z_kE|mr$^*ZN8|&!u<}gcbc(e>l_Ypgk)&Z0j;Huz7buox^=Gk}FUpc+Qq=Y>U6QPr zb10H6ss_B7Pe`;W>T?_^W(QHw)T(ci=^ubC)u=O!i0hiS3wPoh|cm+3hfj#DRCO#rN!a*TQ@>Z6img;zMbt^kK%t07_7 z0!CC#XnPR-ZHyW99Ag+jD~STjDvznwcu>e$Lt?~~^-O6J{Sw)K3n z3_4@p$MgUjI9$l#RXpxmRD73DA5w%*7nS(18su^3lG#}u;^=hi9&ukS3iE8BW+@-u z!3wt@1~BfGZ}QHGaOykTNMo1qs88d`g>U&H&`^m0?h`z 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zQkcM_83BJA_wmNVh&()>;Vm<>_JDatkKsDtpVk8GxRJ$BQf0LDa^KT%{Ps3n8KTQLO~m;G2^JG z8d7-IlTGajWX_^i&CC405EEGKDaN8-2l$#`VHh);CU^ZZYQ)VMCKt43+qvFA5bn;oBNK$CY{w9{!k? zQ%B&OgH&oVuJ_Lc348qu%0J|CiVc1z2>+(PyA4i4E-->z?-Hd)a*pV8bD}Jw@Igi< zMR_D6A_E)sP`S!^)ej)k12(5mlUCc9bTc(El7j_ullFA&u` z1yHtA;u>Z(?0mB6{SV6cL?Bxez-|FtOab>A+!mN!FT8`o+eY4UCpTos1};h3duHF> zE=g5>B9=#<;i1oBIl#KfQ=rmwgm2Sn&o#Uq$X}YzgD?A^e>T)ohN;WAHRr&$L}l6o zu#aj~FrzdFZc&m_0`S&--(0wvdMc|eTTWKtfq6NpFDg$!YH;2pef7r<#nM5?!%L6C z{8V(AA7DM!)+Jy^s;{mFpeJ>)-Xg;={*Xw}>k@59zy;h*>m-ghB;-3CnA6x#gZ;cQ zfx$)x>P@})8SS4m^%84+a{}v{9XQ;)7~iG+4(&Ia9jW;8SAg#M@fF)4jI}KZxP*OT zy+-SoSeYyZ1)oml!*{qpSxoofaawobMOw%3Zn9W?evu@7jat%!u~s)l>RXE;nA+C5 GtolFjEl45& diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CySpc.lst b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CySpc.lst index cf3922f8..0e416d9a 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CySpc.lst +++ b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CySpc.lst @@ -1,4 +1,4 @@ -ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 +ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 1 1 .syntax unified @@ -58,7 +58,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 29:.\Generated_Source\PSoC5/CySpc.c **** #define CY_SPC_CMD_WR_USER_NVL (0x06u) 30:.\Generated_Source\PSoC5/CySpc.c **** #define CY_SPC_CMD_PRG_ROW (0x07u) 31:.\Generated_Source\PSoC5/CySpc.c **** #define CY_SPC_CMD_ER_SECTOR (0x08u) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 2 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 2 32:.\Generated_Source\PSoC5/CySpc.c **** #define CY_SPC_CMD_ER_ALL (0x09u) @@ -118,7 +118,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 33 .cfi_def_cfa_offset 8 34 .cfi_offset 3, -8 35 .cfi_offset 14, -4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 3 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 3 80:.\Generated_Source\PSoC5/CySpc.c **** /* Save current global interrupt enable and disable it */ @@ -178,7 +178,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 101:.\Generated_Source\PSoC5/CySpc.c **** * None 102:.\Generated_Source\PSoC5/CySpc.c **** * 103:.\Generated_Source\PSoC5/CySpc.c **** *******************************************************************************/ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 4 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 4 104:.\Generated_Source\PSoC5/CySpc.c **** void CySpcStop(void) @@ -238,7 +238,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 116:.\Generated_Source\PSoC5/CySpc.c **** 117:.\Generated_Source\PSoC5/CySpc.c **** /******************************************************************************* 118:.\Generated_Source\PSoC5/CySpc.c **** * Function Name: CySpcReadData - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 5 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 5 119:.\Generated_Source\PSoC5/CySpc.c **** ******************************************************************************** @@ -298,7 +298,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 143:.\Generated_Source\PSoC5/CySpc.c **** CyDelayUs(1u); 139 .loc 1 143 0 140 0016 0120 movs r0, #1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 6 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 6 141 0018 FFF7FEFF bl CyDelayUs @@ -358,7 +358,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 168:.\Generated_Source\PSoC5/CySpc.c **** * uint16 number: 169:.\Generated_Source\PSoC5/CySpc.c **** * Number bytes to load. 170:.\Generated_Source\PSoC5/CySpc.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 7 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 7 171:.\Generated_Source\PSoC5/CySpc.c **** * Return: @@ -418,7 +418,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 203 001a E4B2 uxtb r4, r4 204 001c 0CB3 cbz r4, .L25 192:.\Generated_Source\PSoC5/CySpc.c **** { - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 8 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 8 193:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; @@ -478,7 +478,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 205:.\Generated_Source\PSoC5/CySpc.c **** { 206:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_DATA_REG = buffer[i]; 246 .loc 1 206 0 is_stmt 1 discriminator 2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 9 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 9 247 0050 545C ldrb r4, [r2, r1] @ zero_extendqisi2 @@ -538,7 +538,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 279 .L30: 280 006c 22470040 .word 1073760034 281 0070 20470040 .word 1073760032 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 10 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 10 282 .cfi_endproc @@ -598,7 +598,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 258:.\Generated_Source\PSoC5/CySpc.c **** /* Make sure the SPC is ready to accept command */ 259:.\Generated_Source\PSoC5/CySpc.c **** if(CY_SPC_IDLE) 304 .loc 1 259 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 11 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 11 305 0002 104B ldr r3, .L39 @@ -658,7 +658,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 345 0038 30BD pop {r4, r5, pc} 346 .LVL24: 347 .L36: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 12 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 12 273:.\Generated_Source\PSoC5/CySpc.c **** } @@ -718,7 +718,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 299:.\Generated_Source\PSoC5/CySpc.c **** * uint16 address: 300:.\Generated_Source\PSoC5/CySpc.c **** * flash/eeprom addrress 301:.\Generated_Source\PSoC5/CySpc.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 13 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 13 302:.\Generated_Source\PSoC5/CySpc.c **** * uint8 tempPolarity: @@ -778,7 +778,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 328:.\Generated_Source\PSoC5/CySpc.c **** /* Make sure the command was accepted */ 329:.\Generated_Source\PSoC5/CySpc.c **** if(CY_SPC_BUSY) 403 .loc 1 329 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 14 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 14 404 001c 2D78 ldrb r5, [r5, #0] @ zero_extendqisi2 @@ -838,7 +838,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 347:.\Generated_Source\PSoC5/CySpc.c **** return(status); 348:.\Generated_Source\PSoC5/CySpc.c **** } 438 .loc 1 348 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 15 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 15 439 003e 70BD pop {r4, r5, r6, pc} @@ -898,7 +898,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 466 .loc 1 375 0 467 0002 0D4A ldr r2, .L51 468 0004 1378 ldrb r3, [r2, #0] @ zero_extendqisi2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 16 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 16 469 0006 03F00203 and r3, r3, #2 @@ -958,7 +958,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 389:.\Generated_Source\PSoC5/CySpc.c **** status = CYRET_CANCELED; 503 .loc 1 389 0 504 0032 0920 movs r0, #9 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 17 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 17 505 .LVL40: @@ -1018,7 +1018,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 527 @ frame_needed = 0, uses_anonymous_args = 0 528 @ link register save eliminated. 529 .LVL41: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 18 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 18 427:.\Generated_Source\PSoC5/CySpc.c **** cystatus status = CYRET_STARTED; @@ -1078,7 +1078,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 561 .LVL44: 562 002c 7047 bx lr 563 .LVL45: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 19 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 19 564 .L56: @@ -1138,7 +1138,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 594 .cfi_offset 3, -16 595 .cfi_offset 4, -12 596 .cfi_offset 5, -8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 20 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 20 597 .cfi_offset 14, -4 @@ -1198,7 +1198,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 629 @ 0 "" 2 493:.\Generated_Source\PSoC5/CySpc.c **** CY_NOP; 630 .loc 1 493 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 21 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 21 631 @ 493 ".\Generated_Source\PSoC5\CySpc.c" 1 @@ -1258,7 +1258,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 508:.\Generated_Source\PSoC5/CySpc.c **** /******************************************************************************* 509:.\Generated_Source\PSoC5/CySpc.c **** * Function Name: CySpcUnlock 510:.\Generated_Source\PSoC5/CySpc.c **** ******************************************************************************** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 22 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 22 511:.\Generated_Source\PSoC5/CySpc.c **** * Summary: @@ -1318,7 +1318,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 695 001a 0C60 str r4, [r1, #0] 538:.\Generated_Source\PSoC5/CySpc.c **** 539:.\Generated_Source\PSoC5/CySpc.c **** /* At least 2 NOP instructions are recommended */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 23 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 23 540:.\Generated_Source\PSoC5/CySpc.c **** CY_NOP; @@ -1378,7 +1378,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 737 .type spcWaitPipeBypass, %object 738 .size spcWaitPipeBypass, 4 739 spcWaitPipeBypass: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 24 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 24 740 0004 00000000 .space 4 @@ -1393,10 +1393,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 749 0006 00000000 .4byte .Ldebug_abbrev0 750 000a 04 .byte 0x4 751 000b 01 .uleb128 0x1 - 752 000c 46020000 .4byte .LASF40 + 752 000c 57020000 .4byte .LASF40 753 0010 01 .byte 0x1 - 754 0011 5B000000 .4byte .LASF41 - 755 0015 FF010000 .4byte .LASF42 + 754 0011 45000000 .4byte .LASF41 + 755 0015 CA000000 .4byte .LASF42 756 0019 00000000 .4byte .Ldebug_ranges0+0 757 001d 00000000 .4byte 0 758 0021 00000000 .4byte 0 @@ -1404,80 +1404,80 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 760 0029 02 .uleb128 0x2 761 002a 01 .byte 0x1 762 002b 06 .byte 0x6 - 763 002c 3A020000 .4byte .LASF0 + 763 002c 4B020000 .4byte .LASF0 764 0030 02 .uleb128 0x2 765 0031 01 .byte 0x1 766 0032 08 .byte 0x8 - 767 0033 06010000 .4byte .LASF1 + 767 0033 21010000 .4byte .LASF1 768 0037 02 .uleb128 0x2 769 0038 02 .byte 0x2 770 0039 05 .byte 0x5 - 771 003a E1010000 .4byte .LASF2 + 771 003a FC010000 .4byte .LASF2 772 003e 02 .uleb128 0x2 773 003f 02 .byte 0x2 774 0040 07 .byte 0x7 - 775 0041 7C000000 .4byte .LASF3 + 775 0041 66000000 .4byte .LASF3 776 0045 02 .uleb128 0x2 777 0046 04 .byte 0x4 778 0047 05 .byte 0x5 - 779 0048 1F020000 .4byte .LASF4 + 779 0048 30020000 .4byte .LASF4 780 004c 02 .uleb128 0x2 781 004d 04 .byte 0x4 782 004e 07 .byte 0x7 - 783 004f CE000000 .4byte .LASF5 + 783 004f B8000000 .4byte .LASF5 784 0053 02 .uleb128 0x2 785 0054 08 .byte 0x8 786 0055 05 .byte 0x5 - 787 0056 C4010000 .4byte .LASF6 + 787 0056 DF010000 .4byte .LASF6 788 005a 02 .uleb128 0x2 789 005b 08 .byte 0x8 790 005c 07 .byte 0x7 - 791 005d 6C010000 .4byte .LASF7 + 791 005d 87010000 .4byte .LASF7 792 0061 03 .uleb128 0x3 793 0062 04 .byte 0x4 794 0063 05 .byte 0x5 795 0064 696E7400 .ascii "int\000" 796 0068 02 .uleb128 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 25 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 25 797 0069 04 .byte 0x4 798 006a 07 .byte 0x7 - 799 006b 57010000 .4byte .LASF8 + 799 006b 72010000 .4byte .LASF8 800 006f 04 .uleb128 0x4 - 801 0070 E0000000 .4byte .LASF9 + 801 0070 FB000000 .4byte .LASF9 802 0074 02 .byte 0x2 803 0075 5B .byte 0x5b 804 0076 30000000 .4byte 0x30 805 007a 04 .uleb128 0x4 - 806 007b 28010000 .4byte .LASF10 + 806 007b 43010000 .4byte .LASF10 807 007f 02 .byte 0x2 808 0080 5C .byte 0x5c 809 0081 3E000000 .4byte 0x3e 810 0085 04 .uleb128 0x4 - 811 0086 39010000 .4byte .LASF11 + 811 0086 54010000 .4byte .LASF11 812 008a 02 .byte 0x2 813 008b 5D .byte 0x5d 814 008c 4C000000 .4byte 0x4c 815 0090 02 .uleb128 0x2 816 0091 04 .byte 0x4 817 0092 04 .byte 0x4 - 818 0093 A4000000 .4byte .LASF12 + 818 0093 8E000000 .4byte .LASF12 819 0097 02 .uleb128 0x2 820 0098 08 .byte 0x8 821 0099 04 .byte 0x4 - 822 009a 14010000 .4byte .LASF13 + 822 009a 2F010000 .4byte .LASF13 823 009e 02 .uleb128 0x2 824 009f 01 .byte 0x1 825 00a0 08 .byte 0x8 - 826 00a1 DC010000 .4byte .LASF14 + 826 00a1 F7010000 .4byte .LASF14 827 00a5 04 .uleb128 0x4 828 00a6 13000000 .4byte .LASF15 829 00aa 02 .byte 0x2 830 00ab E8 .byte 0xe8 831 00ac 4C000000 .4byte 0x4c 832 00b0 04 .uleb128 0x4 - 833 00b1 BA000000 .4byte .LASF16 + 833 00b1 A4000000 .4byte .LASF16 834 00b5 02 .byte 0x2 835 00b6 F0 .byte 0xf0 836 00b7 BB000000 .4byte 0xbb @@ -1493,12 +1493,12 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 846 00d0 02 .uleb128 0x2 847 00d1 04 .byte 0x4 848 00d2 07 .byte 0x7 - 849 00d3 9E010000 .4byte .LASF18 + 849 00d3 B9010000 .4byte .LASF18 850 00d7 06 .uleb128 0x6 851 00d8 01 .byte 0x1 852 00d9 22000000 .4byte .LASF19 853 00dd 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 26 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 26 854 00de 4E .byte 0x4e @@ -1509,7 +1509,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 859 00ec 01 .byte 0x1 860 00ed 14010000 .4byte 0x114 861 00f1 07 .uleb128 0x7 - 862 00f2 BF000000 .4byte .LASF21 + 862 00f2 A9000000 .4byte .LASF21 863 00f6 01 .byte 0x1 864 00f7 51 .byte 0x51 865 00f8 6F000000 .4byte 0x6f @@ -1524,7 +1524,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 874 0113 00 .byte 0 875 0114 06 .uleb128 0x6 876 0115 01 .byte 0x1 - 877 0116 51000000 .4byte .LASF20 + 877 0116 3B000000 .4byte .LASF20 878 011a 01 .byte 0x1 879 011b 68 .byte 0x68 880 011c 01 .byte 0x1 @@ -1534,7 +1534,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 884 0129 01 .byte 0x1 885 012a 51010000 .4byte 0x151 886 012e 07 .uleb128 0x7 - 887 012f BF000000 .4byte .LASF21 + 887 012f A9000000 .4byte .LASF21 888 0133 01 .byte 0x1 889 0134 6B .byte 0x6b 890 0135 6F000000 .4byte 0x6f @@ -1549,7 +1549,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 899 0150 00 .byte 0 900 0151 0A .uleb128 0xa 901 0152 01 .byte 0x1 - 902 0153 8F000000 .4byte .LASF24 + 902 0153 79000000 .4byte .LASF24 903 0157 01 .byte 0x1 904 0158 87 .byte 0x87 905 0159 01 .byte 0x1 @@ -1558,18 +1558,18 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 908 0162 34000000 .4byte .LFE2 909 0166 66000000 .4byte .LLST4 910 016a 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 27 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 27 911 016b AA010000 .4byte 0x1aa 912 016f 0B .uleb128 0xb - 913 0170 EB010000 .4byte .LASF22 + 913 0170 06020000 .4byte .LASF22 914 0174 01 .byte 0x1 915 0175 87 .byte 0x87 916 0176 AA010000 .4byte 0x1aa 917 017a 86000000 .4byte .LLST5 918 017e 0B .uleb128 0xb - 919 017f B5000000 .4byte .LASF23 + 919 017f 9F000000 .4byte .LASF23 920 0183 01 .byte 0x1 921 0184 87 .byte 0x87 922 0185 6F000000 .4byte 0x6f @@ -1606,36 +1606,36 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 953 01c9 01 .byte 0x1 954 01ca 23020000 .4byte 0x223 955 01ce 0B .uleb128 0xb - 956 01cf 00010000 .4byte .LASF26 + 956 01cf 1B010000 .4byte .LASF26 957 01d3 01 .byte 0x1 958 01d4 B2 .byte 0xb2 959 01d5 6F000000 .4byte 0x6f 960 01d9 F9000000 .4byte .LLST9 961 01dd 0B .uleb128 0xb - 962 01de 64010000 .4byte .LASF27 + 962 01de 7F010000 .4byte .LASF27 963 01e2 01 .byte 0x1 964 01e3 B2 .byte 0xb2 965 01e4 7A000000 .4byte 0x7a 966 01e8 8D010000 .4byte .LLST10 967 01ec 10 .uleb128 0x10 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 28 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 28 - 968 01ed EB010000 .4byte .LASF22 + 968 01ed 06020000 .4byte .LASF22 969 01f1 01 .byte 0x1 970 01f2 B2 .byte 0xb2 971 01f3 23020000 .4byte 0x223 972 01f7 01 .byte 0x1 973 01f8 52 .byte 0x52 974 01f9 10 .uleb128 0x10 - 975 01fa B5000000 .4byte .LASF23 + 975 01fa 9F000000 .4byte .LASF23 976 01fe 01 .byte 0x1 977 01ff B2 .byte 0xb2 978 0200 6F000000 .4byte 0x6f 979 0204 01 .byte 0x1 980 0205 53 .byte 0x53 981 0206 07 .uleb128 0x7 - 982 0207 9D000000 .4byte .LASF28 + 982 0207 87000000 .4byte .LASF28 983 020b 01 .byte 0x1 984 020c B5 .byte 0xb5 985 020d A5000000 .4byte 0xa5 @@ -1654,7 +1654,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 998 022a 6F000000 .4byte 0x6f 999 022e 0A .uleb128 0xa 1000 022f 01 .byte 0x1 - 1001 0230 91010000 .4byte .LASF29 + 1001 0230 AC010000 .4byte .LASF29 1002 0234 01 .byte 0x1 1003 0235 FD .byte 0xfd 1004 0236 01 .byte 0x1 @@ -1665,30 +1665,30 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 1009 0247 01 .byte 0x1 1010 0248 8F020000 .4byte 0x28f 1011 024c 0B .uleb128 0xb - 1012 024d 00010000 .4byte .LASF26 + 1012 024d 1B010000 .4byte .LASF26 1013 0251 01 .byte 0x1 1014 0252 FD .byte 0xfd 1015 0253 6F000000 .4byte 0x6f 1016 0257 0C020000 .4byte .LLST14 1017 025b 10 .uleb128 0x10 - 1018 025c EB010000 .4byte .LASF22 + 1018 025c 06020000 .4byte .LASF22 1019 0260 01 .byte 0x1 1020 0261 FD .byte 0xfd 1021 0262 23020000 .4byte 0x223 1022 0266 01 .byte 0x1 1023 0267 51 .byte 0x51 1024 0268 10 .uleb128 0x10 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 29 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 29 - 1025 0269 B5000000 .4byte .LASF23 + 1025 0269 9F000000 .4byte .LASF23 1026 026d 01 .byte 0x1 1027 026e FD .byte 0xfd 1028 026f 7A000000 .4byte 0x7a 1029 0273 01 .byte 0x1 1030 0274 52 .byte 0x52 1031 0275 07 .uleb128 0x7 - 1032 0276 9D000000 .4byte .LASF28 + 1032 0276 87000000 .4byte .LASF28 1033 027a 01 .byte 0x1 1034 027b FF .byte 0xff 1035 027c A5000000 .4byte 0xa5 @@ -1712,36 +1712,36 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 1053 02a9 01 .byte 0x1 1054 02aa FB020000 .4byte 0x2fb 1055 02ae 14 .uleb128 0x14 - 1056 02af 00010000 .4byte .LASF26 + 1056 02af 1B010000 .4byte .LASF26 1057 02b3 01 .byte 0x1 1058 02b4 3C01 .2byte 0x13c 1059 02b6 6F000000 .4byte 0x6f 1060 02ba BA020000 .4byte .LLST17 1061 02be 14 .uleb128 0x14 - 1062 02bf 64010000 .4byte .LASF27 + 1062 02bf 7F010000 .4byte .LASF27 1063 02c3 01 .byte 0x1 1064 02c4 3C01 .2byte 0x13c 1065 02c6 7A000000 .4byte 0x7a 1066 02ca 0B030000 .4byte .LLST18 1067 02ce 15 .uleb128 0x15 - 1068 02cf F3000000 .4byte .LASF31 + 1068 02cf 0E010000 .4byte .LASF31 1069 02d3 01 .byte 0x1 1070 02d4 3C01 .2byte 0x13c 1071 02d6 6F000000 .4byte 0x6f 1072 02da 01 .byte 0x1 1073 02db 52 .byte 0x52 1074 02dc 15 .uleb128 0x15 - 1075 02dd 83010000 .4byte .LASF32 + 1075 02dd 9E010000 .4byte .LASF32 1076 02e1 01 .byte 0x1 1077 02e2 3C01 .2byte 0x13c 1078 02e4 6F000000 .4byte 0x6f 1079 02e8 01 .byte 0x1 1080 02e9 53 .byte 0x53 1081 02ea 16 .uleb128 0x16 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 30 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 30 - 1082 02eb 9D000000 .4byte .LASF28 + 1082 02eb 87000000 .4byte .LASF28 1083 02ef 01 .byte 0x1 1084 02f0 3F01 .2byte 0x13f 1085 02f2 A5000000 .4byte 0xa5 @@ -1749,7 +1749,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 1087 02fa 00 .byte 0 1088 02fb 13 .uleb128 0x13 1089 02fc 01 .byte 0x1 - 1090 02fd B3010000 .4byte .LASF33 + 1090 02fd CE010000 .4byte .LASF33 1091 0301 01 .byte 0x1 1092 0302 7201 .2byte 0x172 1093 0304 01 .byte 0x1 @@ -1760,20 +1760,20 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 1098 0315 01 .byte 0x1 1099 0316 49030000 .4byte 0x349 1100 031a 14 .uleb128 0x14 - 1101 031b 00010000 .4byte .LASF26 + 1101 031b 1B010000 .4byte .LASF26 1102 031f 01 .byte 0x1 1103 0320 7201 .2byte 0x172 1104 0322 6F000000 .4byte 0x6f 1105 0326 76030000 .4byte .LLST21 1106 032a 15 .uleb128 0x15 - 1107 032b F2010000 .4byte .LASF34 + 1107 032b 0D020000 .4byte .LASF34 1108 032f 01 .byte 0x1 1109 0330 7201 .2byte 0x172 1110 0332 6F000000 .4byte 0x6f 1111 0336 01 .byte 0x1 1112 0337 51 .byte 0x51 1113 0338 16 .uleb128 0x16 - 1114 0339 9D000000 .4byte .LASF28 + 1114 0339 87000000 .4byte .LASF28 1115 033d 01 .byte 0x1 1116 033e 7401 .2byte 0x174 1117 0340 A5000000 .4byte 0xa5 @@ -1781,7 +1781,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 1119 0348 00 .byte 0 1120 0349 17 .uleb128 0x17 1121 034a 01 .byte 0x1 - 1122 034b 1B010000 .4byte .LASF35 + 1122 034b 36010000 .4byte .LASF35 1123 034f 01 .byte 0x1 1124 0350 A901 .2byte 0x1a9 1125 0352 01 .byte 0x1 @@ -1794,16 +1794,16 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 1132 0362 01 .byte 0x1 1133 0363 88030000 .4byte 0x388 1134 0367 14 .uleb128 0x14 - 1135 0368 AA000000 .4byte .LASF36 + 1135 0368 94000000 .4byte .LASF36 1136 036c 01 .byte 0x1 1137 036d A901 .2byte 0x1a9 1138 036f 6F000000 .4byte 0x6f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 31 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 31 1139 0373 E6030000 .4byte .LLST23 1140 0377 16 .uleb128 0x16 - 1141 0378 9D000000 .4byte .LASF28 + 1141 0378 87000000 .4byte .LASF28 1142 037c 01 .byte 0x1 1143 037d AB01 .2byte 0x1ab 1144 037f A5000000 .4byte 0xa5 @@ -1811,7 +1811,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 1146 0387 00 .byte 0 1147 0388 13 .uleb128 0x13 1148 0389 01 .byte 0x1 - 1149 038a 2F010000 .4byte .LASF37 + 1149 038a 4A010000 .4byte .LASF37 1150 038e 01 .byte 0x1 1151 038f D601 .2byte 0x1d6 1152 0391 01 .byte 0x1 @@ -1822,13 +1822,13 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 1157 03a2 01 .byte 0x1 1158 03a3 DA030000 .4byte 0x3da 1159 03a7 16 .uleb128 0x16 - 1160 03a8 9D000000 .4byte .LASF28 + 1160 03a8 87000000 .4byte .LASF28 1161 03ac 01 .byte 0x1 1162 03ad D801 .2byte 0x1d8 1163 03af A5000000 .4byte 0xa5 1164 03b3 76040000 .4byte .LLST26 1165 03b7 16 .uleb128 0x16 - 1166 03b8 BF000000 .4byte .LASF21 + 1166 03b8 A9000000 .4byte .LASF21 1167 03bc 01 .byte 0x1 1168 03bd D901 .2byte 0x1d9 1169 03bf 6F000000 .4byte 0x6f @@ -1842,7 +1842,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 1177 03d9 00 .byte 0 1178 03da 18 .uleb128 0x18 1179 03db 01 .byte 0x1 - 1180 03dc A7010000 .4byte .LASF38 + 1180 03dc C2010000 .4byte .LASF38 1181 03e0 01 .byte 0x1 1182 03e1 0A02 .2byte 0x20a 1183 03e3 01 .byte 0x1 @@ -1852,13 +1852,13 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 1187 03f0 01 .byte 0x1 1188 03f1 19040000 .4byte 0x419 1189 03f5 16 .uleb128 0x16 - 1190 03f6 BF000000 .4byte .LASF21 + 1190 03f6 A9000000 .4byte .LASF21 1191 03fa 01 .byte 0x1 1192 03fb 0C02 .2byte 0x20c 1193 03fd 6F000000 .4byte 0x6f 1194 0401 E0040000 .4byte .LLST29 1195 0405 08 .uleb128 0x8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 32 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 32 1196 0406 06000000 .4byte .LVL53 @@ -1869,7 +1869,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 1201 0414 4A040000 .4byte 0x44a 1202 0418 00 .byte 0 1203 0419 19 .uleb128 0x19 - 1204 041a 28020000 .4byte .LASF39 + 1204 041a 39020000 .4byte .LASF39 1205 041e 01 .byte 0x1 1206 041f 3C .byte 0x3c 1207 0420 85000000 .4byte 0x85 @@ -1877,7 +1877,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 1209 0425 03 .byte 0x3 1210 0426 04000000 .4byte spcWaitPipeBypass 1211 042a 1A .uleb128 0x1a - 1212 042b E6000000 .4byte .LASF43 + 1212 042b 01010000 .4byte .LASF43 1213 042f 01 .byte 0x1 1214 0430 30 .byte 0x30 1215 0431 6F000000 .4byte 0x6f @@ -1887,7 +1887,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 1219 0438 00000000 .4byte SpcLockState 1220 043c 1B .uleb128 0x1b 1221 043d 01 .byte 0x1 - 1222 043e 40010000 .4byte .LASF44 + 1222 043e 5B010000 .4byte .LASF44 1223 0442 03 .byte 0x3 1224 0443 7E .byte 0x7e 1225 0444 01 .byte 0x1 @@ -1895,7 +1895,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 1227 0449 01 .byte 0x1 1228 044a 1C .uleb128 0x1c 1229 044b 01 .byte 0x1 - 1230 044c 3B000000 .4byte .LASF45 + 1230 044c 1A020000 .4byte .LASF45 1231 0450 03 .byte 0x3 1232 0451 7F .byte 0x7f 1233 0452 01 .byte 0x1 @@ -1906,7 +1906,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 1238 045d 00 .byte 0 1239 045e 1E .uleb128 0x1e 1240 045f 01 .byte 0x1 - 1241 0460 D2010000 .4byte .LASF46 + 1241 0460 ED010000 .4byte .LASF46 1242 0464 03 .byte 0x3 1243 0465 78 .byte 0x78 1244 0466 01 .byte 0x1 @@ -1918,7 +1918,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 1250 .section .debug_abbrev,"",%progbits 1251 .Ldebug_abbrev0: 1252 0000 01 .uleb128 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 33 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 33 1253 0001 11 .uleb128 0x11 @@ -1978,7 +1978,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 1307 0037 00 .byte 0 1308 0038 05 .uleb128 0x5 1309 0039 35 .uleb128 0x35 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 34 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 34 1310 003a 00 .byte 0 @@ -2038,7 +2038,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 1364 0073 09 .uleb128 0x9 1365 0074 898201 .uleb128 0x4109 1366 0077 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 35 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 35 1367 0078 11 .uleb128 0x11 @@ -2098,7 +2098,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 1421 00b0 08 .uleb128 0x8 1422 00b1 3A .uleb128 0x3a 1423 00b2 0B .uleb128 0xb - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 36 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 36 1424 00b3 3B .uleb128 0x3b @@ -2158,7 +2158,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 1478 00ee 13 .uleb128 0x13 1479 00ef 00 .byte 0 1480 00f0 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 37 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 37 1481 00f1 12 .uleb128 0x12 @@ -2218,7 +2218,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 1535 0128 00 .byte 0 1536 0129 15 .uleb128 0x15 1537 012a 05 .uleb128 0x5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 38 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 38 1538 012b 00 .byte 0 @@ -2278,7 +2278,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 1592 0162 00 .byte 0 1593 0163 18 .uleb128 0x18 1594 0164 2E .uleb128 0x2e - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 39 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 39 1595 0165 01 .byte 0x1 @@ -2338,7 +2338,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 1649 019c 00 .byte 0 1650 019d 1B .uleb128 0x1b 1651 019e 2E .uleb128 0x2e - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 40 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 40 1652 019f 00 .byte 0 @@ -2398,7 +2398,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 1706 01d5 27 .uleb128 0x27 1707 01d6 0C .uleb128 0xc 1708 01d7 3C .uleb128 0x3c - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 41 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 41 1709 01d8 0C .uleb128 0xc @@ -2458,7 +2458,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 1763 007a 0200 .2byte 0x2 1764 007c 7D .byte 0x7d 1765 007d 10 .sleb128 16 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 42 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 42 1766 007e 00000000 .4byte 0 @@ -2518,7 +2518,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 1820 0108 4A000000 .4byte .LVL11 1821 010c 0200 .2byte 0x2 1822 010e 74 .byte 0x74 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 43 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 43 1823 010f 00 .sleb128 0 @@ -2578,7 +2578,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 1877 0195 0100 .2byte 0x1 1878 0197 51 .byte 0x51 1879 0198 40000000 .4byte .LVL9 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 44 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 44 1880 019c 5E000000 .4byte .LVL14 @@ -2638,7 +2638,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 1934 0222 20470040 .4byte 0x40004720 1935 0226 30000000 .4byte .LVL22 1936 022a 36000000 .4byte .LVL23 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 45 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 45 1937 022e 0200 .2byte 0x2 @@ -2698,7 +2698,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 1991 02b1 10 .sleb128 16 1992 02b2 00000000 .4byte 0 1993 02b6 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 46 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 46 1994 .LLST17: @@ -2758,7 +2758,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 2048 033b 3E000000 .4byte .LVL34 2049 033f 0200 .2byte 0x2 2050 0341 37 .byte 0x37 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 47 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 47 2051 0342 9F .byte 0x9f @@ -2818,7 +2818,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 2105 .LLST22: 2106 03c7 00000000 .4byte .LVL35 2107 03cb 34000000 .4byte .LVL40 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 48 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 48 2108 03cf 0200 .2byte 0x2 @@ -2878,7 +2878,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 2162 0452 00000000 .4byte 0 2163 .LLST25: 2164 0456 00000000 .4byte .LFB8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 49 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 49 2165 045a 02000000 .4byte .LCFI7 @@ -2938,7 +2938,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 2219 04e0 06000000 .4byte .LVL53 2220 04e4 2B000000 .4byte .LVL54-1 2221 04e8 0100 .2byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 50 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 50 2222 04ea 50 .byte 0x50 @@ -2998,7 +2998,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 2276 004c 34000000 .4byte .LFE9 2277 0050 00000000 .4byte 0 2278 0054 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 51 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 51 2279 .section .debug_line,"",%progbits @@ -3030,205 +3030,206 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 1 2291 63577269 2291 7465526F 2291 7700 - 2292 .LASF45: - 2293 003b 43794578 .ascii "CyExitCriticalSection\000" - 2293 69744372 - 2293 69746963 - 2293 616C5365 - 2293 6374696F - 2294 .LASF20: - 2295 0051 43795370 .ascii "CySpcStop\000" - 2295 6353746F - 2295 7000 - 2296 .LASF41: - 2297 005b 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\CySpc.c\000" - 2297 6E657261 - 2297 7465645F - 2297 536F7572 - 2297 63655C50 - 2298 .LASF3: - 2299 007c 73686F72 .ascii "short unsigned int\000" - 2299 7420756E - 2299 7369676E - 2299 65642069 - 2299 6E7400 - 2300 .LASF24: - 2301 008f 43795370 .ascii "CySpcReadData\000" - 2301 63526561 - 2301 64446174 - 2301 6100 - 2302 .LASF28: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 52 - - - 2303 009d 73746174 .ascii "status\000" - 2303 757300 - 2304 .LASF12: - 2305 00a4 666C6F61 .ascii "float\000" - 2305 7400 - 2306 .LASF36: - 2307 00aa 6E756D53 .ascii "numSamples\000" - 2307 616D706C - 2307 657300 - 2308 .LASF23: - 2309 00b5 73697A65 .ascii "size\000" + 2292 .LASF20: + 2293 003b 43795370 .ascii "CySpcStop\000" + 2293 6353746F + 2293 7000 + 2294 .LASF41: + 2295 0045 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\CySpc.c\000" + 2295 6E657261 + 2295 7465645F + 2295 536F7572 + 2295 63655C50 + 2296 .LASF3: + 2297 0066 73686F72 .ascii "short unsigned int\000" + 2297 7420756E + 2297 7369676E + 2297 65642069 + 2297 6E7400 + 2298 .LASF24: + 2299 0079 43795370 .ascii "CySpcReadData\000" + 2299 63526561 + 2299 64446174 + 2299 6100 + 2300 .LASF28: + 2301 0087 73746174 .ascii "status\000" + 2301 757300 + 2302 .LASF12: + 2303 008e 666C6F61 .ascii "float\000" + 2303 7400 + 2304 .LASF36: + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 52 + + + 2305 0094 6E756D53 .ascii "numSamples\000" + 2305 616D706C + 2305 657300 + 2306 .LASF23: + 2307 009f 73697A65 .ascii "size\000" + 2307 00 + 2308 .LASF16: + 2309 00a4 72656738 .ascii "reg8\000" 2309 00 - 2310 .LASF16: - 2311 00ba 72656738 .ascii "reg8\000" - 2311 00 - 2312 .LASF21: - 2313 00bf 696E7465 .ascii "interruptState\000" - 2313 72727570 - 2313 74537461 - 2313 746500 - 2314 .LASF5: - 2315 00ce 6C6F6E67 .ascii "long unsigned int\000" - 2315 20756E73 - 2315 69676E65 - 2315 6420696E - 2315 7400 - 2316 .LASF9: - 2317 00e0 75696E74 .ascii "uint8\000" - 2317 3800 - 2318 .LASF43: - 2319 00e6 5370634C .ascii "SpcLockState\000" - 2319 6F636B53 - 2319 74617465 - 2319 00 - 2320 .LASF31: - 2321 00f3 74656D70 .ascii "tempPolarity\000" - 2321 506F6C61 - 2321 72697479 - 2321 00 - 2322 .LASF26: - 2323 0100 61727261 .ascii "array\000" - 2323 7900 - 2324 .LASF1: - 2325 0106 756E7369 .ascii "unsigned char\000" - 2325 676E6564 - 2325 20636861 - 2325 7200 - 2326 .LASF13: - 2327 0114 646F7562 .ascii "double\000" - 2327 6C6500 - 2328 .LASF35: - 2329 011b 43795370 .ascii "CySpcGetTemp\000" - 2329 63476574 - 2329 54656D70 - 2329 00 - 2330 .LASF10: - 2331 0128 75696E74 .ascii "uint16\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 53 - - - 2331 313600 - 2332 .LASF37: - 2333 012f 43795370 .ascii "CySpcLock\000" - 2333 634C6F63 - 2333 6B00 - 2334 .LASF11: - 2335 0139 75696E74 .ascii "uint32\000" - 2335 333200 - 2336 .LASF44: - 2337 0140 4379456E .ascii "CyEnterCriticalSection\000" - 2337 74657243 - 2337 72697469 - 2337 63616C53 - 2337 65637469 - 2338 .LASF8: - 2339 0157 756E7369 .ascii "unsigned int\000" - 2339 676E6564 - 2339 20696E74 - 2339 00 - 2340 .LASF27: - 2341 0164 61646472 .ascii "address\000" - 2341 65737300 - 2342 .LASF7: - 2343 016c 6C6F6E67 .ascii "long long unsigned int\000" - 2343 206C6F6E - 2343 6720756E - 2343 7369676E - 2343 65642069 - 2344 .LASF32: - 2345 0183 74656D70 .ascii "tempMagnitude\000" - 2345 4D61676E - 2345 69747564 - 2345 6500 - 2346 .LASF29: - 2347 0191 43795370 .ascii "CySpcLoadRow\000" - 2347 634C6F61 - 2347 64526F77 - 2347 00 - 2348 .LASF18: - 2349 019e 73697A65 .ascii "sizetype\000" - 2349 74797065 - 2349 00 - 2350 .LASF38: - 2351 01a7 43795370 .ascii "CySpcUnlock\000" - 2351 63556E6C - 2351 6F636B00 - 2352 .LASF33: - 2353 01b3 43795370 .ascii "CySpcEraseSector\000" - 2353 63457261 - 2353 73655365 - 2353 63746F72 - 2353 00 - 2354 .LASF6: - 2355 01c4 6C6F6E67 .ascii "long long int\000" - 2355 206C6F6E - 2355 6720696E - 2355 7400 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccXJOjZh.s page 54 - - - 2356 .LASF46: - 2357 01d2 43794465 .ascii "CyDelayUs\000" - 2357 6C617955 - 2357 7300 - 2358 .LASF14: - 2359 01dc 63686172 .ascii "char\000" - 2359 00 - 2360 .LASF2: - 2361 01e1 73686F72 .ascii "short int\000" - 2361 7420696E - 2361 7400 - 2362 .LASF22: - 2363 01eb 62756666 .ascii "buffer\000" - 2363 657200 - 2364 .LASF34: - 2365 01f2 73656374 .ascii "sectorNumber\000" - 2365 6F724E75 - 2365 6D626572 - 2365 00 - 2366 .LASF42: - 2367 01ff 573A5C53 .ascii "W:\\SCSI2SD\\USB_Bootloader.cydsn\000" - 2367 43534932 - 2367 53445C55 - 2367 53425F42 - 2367 6F6F746C - 2368 .LASF4: - 2369 021f 6C6F6E67 .ascii "long int\000" - 2369 20696E74 - 2369 00 - 2370 .LASF39: - 2371 0228 73706357 .ascii "spcWaitPipeBypass\000" - 2371 61697450 - 2371 69706542 - 2371 79706173 - 2371 7300 - 2372 .LASF0: - 2373 023a 7369676E .ascii "signed char\000" - 2373 65642063 - 2373 68617200 - 2374 .LASF40: - 2375 0246 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 2375 4320342E - 2375 372E3320 - 2375 32303133 - 2375 30333132 - 2376 0279 616E6368 .ascii "anch revision 196615]\000" - 2376 20726576 - 2376 6973696F - 2376 6E203139 - 2376 36363135 - 2377 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br + 2310 .LASF21: + 2311 00a9 696E7465 .ascii "interruptState\000" + 2311 72727570 + 2311 74537461 + 2311 746500 + 2312 .LASF5: + 2313 00b8 6C6F6E67 .ascii "long unsigned int\000" + 2313 20756E73 + 2313 69676E65 + 2313 6420696E + 2313 7400 + 2314 .LASF42: + 2315 00ca 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" + 2315 43534932 + 2315 53445C73 + 2315 6F667477 + 2315 6172655C + 2316 00f9 6E00 .ascii "n\000" + 2317 .LASF9: + 2318 00fb 75696E74 .ascii "uint8\000" + 2318 3800 + 2319 .LASF43: + 2320 0101 5370634C .ascii "SpcLockState\000" + 2320 6F636B53 + 2320 74617465 + 2320 00 + 2321 .LASF31: + 2322 010e 74656D70 .ascii "tempPolarity\000" + 2322 506F6C61 + 2322 72697479 + 2322 00 + 2323 .LASF26: + 2324 011b 61727261 .ascii "array\000" + 2324 7900 + 2325 .LASF1: + 2326 0121 756E7369 .ascii "unsigned char\000" + 2326 676E6564 + 2326 20636861 + 2326 7200 + 2327 .LASF13: + 2328 012f 646F7562 .ascii "double\000" + 2328 6C6500 + 2329 .LASF35: + 2330 0136 43795370 .ascii "CySpcGetTemp\000" + 2330 63476574 + 2330 54656D70 + 2330 00 + 2331 .LASF10: + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 53 + + + 2332 0143 75696E74 .ascii "uint16\000" + 2332 313600 + 2333 .LASF37: + 2334 014a 43795370 .ascii "CySpcLock\000" + 2334 634C6F63 + 2334 6B00 + 2335 .LASF11: + 2336 0154 75696E74 .ascii "uint32\000" + 2336 333200 + 2337 .LASF44: + 2338 015b 4379456E .ascii "CyEnterCriticalSection\000" + 2338 74657243 + 2338 72697469 + 2338 63616C53 + 2338 65637469 + 2339 .LASF8: + 2340 0172 756E7369 .ascii "unsigned int\000" + 2340 676E6564 + 2340 20696E74 + 2340 00 + 2341 .LASF27: + 2342 017f 61646472 .ascii "address\000" + 2342 65737300 + 2343 .LASF7: + 2344 0187 6C6F6E67 .ascii "long long unsigned int\000" + 2344 206C6F6E + 2344 6720756E + 2344 7369676E + 2344 65642069 + 2345 .LASF32: + 2346 019e 74656D70 .ascii "tempMagnitude\000" + 2346 4D61676E + 2346 69747564 + 2346 6500 + 2347 .LASF29: + 2348 01ac 43795370 .ascii "CySpcLoadRow\000" + 2348 634C6F61 + 2348 64526F77 + 2348 00 + 2349 .LASF18: + 2350 01b9 73697A65 .ascii "sizetype\000" + 2350 74797065 + 2350 00 + 2351 .LASF38: + 2352 01c2 43795370 .ascii "CySpcUnlock\000" + 2352 63556E6C + 2352 6F636B00 + 2353 .LASF33: + 2354 01ce 43795370 .ascii "CySpcEraseSector\000" + 2354 63457261 + 2354 73655365 + 2354 63746F72 + 2354 00 + 2355 .LASF6: + 2356 01df 6C6F6E67 .ascii "long long int\000" + 2356 206C6F6E + 2356 6720696E + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 54 + + + 2356 7400 + 2357 .LASF46: + 2358 01ed 43794465 .ascii "CyDelayUs\000" + 2358 6C617955 + 2358 7300 + 2359 .LASF14: + 2360 01f7 63686172 .ascii "char\000" + 2360 00 + 2361 .LASF2: + 2362 01fc 73686F72 .ascii "short int\000" + 2362 7420696E + 2362 7400 + 2363 .LASF22: + 2364 0206 62756666 .ascii "buffer\000" + 2364 657200 + 2365 .LASF34: + 2366 020d 73656374 .ascii "sectorNumber\000" + 2366 6F724E75 + 2366 6D626572 + 2366 00 + 2367 .LASF45: + 2368 021a 43794578 .ascii "CyExitCriticalSection\000" + 2368 69744372 + 2368 69746963 + 2368 616C5365 + 2368 6374696F + 2369 .LASF4: + 2370 0230 6C6F6E67 .ascii "long int\000" + 2370 20696E74 + 2370 00 + 2371 .LASF39: + 2372 0239 73706357 .ascii "spcWaitPipeBypass\000" + 2372 61697450 + 2372 69706542 + 2372 79706173 + 2372 7300 + 2373 .LASF0: + 2374 024b 7369676E .ascii "signed char\000" + 2374 65642063 + 2374 68617200 + 2375 .LASF40: + 2376 0257 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" + 2376 4320342E + 2376 372E3320 + 2376 32303133 + 2376 30333132 + 2377 028a 616E6368 .ascii "anch revision 196615]\000" + 2377 20726576 + 2377 6973696F + 2377 6E203139 + 2377 36363135 + 2378 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CySpc.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CySpc.o index d65dff7605e7c32f5afd67f2beda68a8a504684d..cf97e1cffa42d3be22c5cb83835bd3fbe0b04fdc 100755 GIT binary patch delta 930 zcmYjNTSyd97(V~ZncejkTcf+Wv)L{SDFwAe7p<*CyIH}ilZv?&ix&#ik#*6GY9p}i z#R&c)p-3MR+UmjFmkJ{5rRX6DO01XOA_5;HB8C2c2DFFyFW>E)GgBQi9XCVJ_cV-3 zVY?y(927#l$D~isDBwCqhytE4P*b!eySaNwp-3&toOD0q&7*x|&g0HfQ>AupAkAEg zHu;wYol&Z?fklaZJf7h3)N$sdyur;Qw=xEv-|W&wAuT^xARpjKH4M-3qFM<#ysJiF z557{%XZ*)c71AheKagI1HV=H#}Sk8w- zvlExLy>B_r4?8(7w;C5CRJkPJI;Y)YSI#znr`@qXc5Wky)8Q!F=U44@gtid{Usv?S z3$|gHP+ty{u88r5O@#_oA-2;u$A$`rpL9hI*Yf|5jS-`%go*&LA!@%t<7*28ItfxQ zJMRiYfE;QD;55nCvrbgPV!ptAr@&(lcA05wP~ht|L$AFGYh8Gf860Fi7@RQ-YX&8Ok zjauNKCIpNKA^re1wMey}dJX(OprjdVDw)&7Ytl$DC(U=<`HdCk{N{N|x-`yRm}G8< zI{AeKBRv#ljzy#Uxa{Nd!~kVaCA!nOz}<%x^4^%XnPxhDSK9C!vWC^$e7- zsmG{ZrTPy3)*b5ync(Ik#T#S^G%zQNeS*QIiv;{)@U&{LPQ^_;6cp#L?lrnm&N}dPSFOxp3cIJUK0bPj5PZoPT zlq1*qqJQ0BXN|f2Fi&X@X+;QJ<|jZw1c(AX6{6rUg|ON+p>|F2>l60+W-In diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS.lst b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS.lst index 05d7374b..a309a10a 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS.lst +++ b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS.lst @@ -1,4 +1,4 @@ -ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 +ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 1 1 .syntax unified @@ -58,7 +58,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 29:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_DMA2_REMOVE */ 30:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_DMA3_REMOVE == 0u) 31:.\Generated_Source\PSoC5/USBFS.c **** #include "USBFS_ep3_dma.h" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 2 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 2 32:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_DMA3_REMOVE */ @@ -118,7 +118,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 86:.\Generated_Source\PSoC5/USBFS.c **** * None. 87:.\Generated_Source\PSoC5/USBFS.c **** * 88:.\Generated_Source\PSoC5/USBFS.c **** * Global variables: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 3 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 3 89:.\Generated_Source\PSoC5/USBFS.c **** * The USBFS_intiVar variable is used to indicate initial @@ -178,7 +178,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 33 .cfi_def_cfa_offset 24 34 .cfi_offset 3, -24 35 .cfi_offset 4, -20 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 4 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 4 36 .cfi_offset 5, -16 @@ -238,7 +238,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 157:.\Generated_Source\PSoC5/USBFS.c **** CyDelayUs(0u); /*~50ns delay */ 158:.\Generated_Source\PSoC5/USBFS.c **** /* Disable the USBIO by asserting PM.USB_CR0.fsusbio_pd_n(Inverted) 159:.\Generated_Source\PSoC5/USBFS.c **** * high. This will have been set low by the power manger out of reset. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 5 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 5 160:.\Generated_Source\PSoC5/USBFS.c **** * Also confirm USBIO pull-up disabled @@ -298,7 +298,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 173:.\Generated_Source\PSoC5/USBFS.c **** CyDelayUs(40u); 100 .loc 1 173 0 101 0058 2820 movs r0, #40 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 6 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 6 102 005a FFF7FEFF bl CyDelayUs @@ -358,7 +358,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 132 008a 3846 mov r0, r7 186:.\Generated_Source\PSoC5/USBFS.c **** CY_SET_REG8(USBFS_ARB_RW1_WA_MSB_PTR, 0u); 133 .loc 1 186 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 7 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 7 134 008c 5470 strb r4, [r2, #1] @@ -418,7 +418,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 169 00c2 2046 mov r0, r4 170 00c4 1149 ldr r1, .L2+36 171 00c6 FFF7FEFF bl CyIntSetVector - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 8 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 8 172 .LVL14: @@ -478,7 +478,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 256:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP8_ISR_REMOVE == 0u) 257:.\Generated_Source\PSoC5/USBFS.c **** (void) CyIntSetVector(USBFS_EP_8_VECT_NUM, &USBFS_EP_8_ISR); 258:.\Generated_Source\PSoC5/USBFS.c **** CyIntSetPriority(USBFS_EP_8_VECT_NUM, USBFS_EP_8_PRIOR); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 9 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 9 259:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP8_ISR_REMOVE */ @@ -538,7 +538,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 282:.\Generated_Source\PSoC5/USBFS.c **** * in the "Device Number" field. 283:.\Generated_Source\PSoC5/USBFS.c **** * mode: The operating voltage. This determines whether the voltage regulator 284:.\Generated_Source\PSoC5/USBFS.c **** * is enabled for 5V operation or if pass through mode is used for 3.3V - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 10 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 10 285:.\Generated_Source\PSoC5/USBFS.c **** * operation. Symbolic names and their associated values are given in the @@ -598,7 +598,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 221 .loc 1 333 0 222 0000 184B ldr r3, .L11 223 0002 0122 movs r2, #1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 11 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 11 323:.\Generated_Source\PSoC5/USBFS.c **** { @@ -658,7 +658,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 366:.\Generated_Source\PSoC5/USBFS.c **** USBFS_ARB_INT_EN_REG = USBFS_ARB_INT_MASK; 367:.\Generated_Source\PSoC5/USBFS.c **** CyIntEnable(USBFS_ARB_VECT_NUM); 368:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 12 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 12 369:.\Generated_Source\PSoC5/USBFS.c **** @@ -718,7 +718,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 260 002c 124B ldr r3, .L11+20 403:.\Generated_Source\PSoC5/USBFS.c **** USBFS_device = device; 261 .loc 1 403 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 13 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 13 262 002e 0870 strb r0, [r1, #0] @@ -778,7 +778,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 419:.\Generated_Source\PSoC5/USBFS.c **** 420:.\Generated_Source\PSoC5/USBFS.c **** /* Workaround for PSOC5LP */ 421:.\Generated_Source\PSoC5/USBFS.c **** CyDelayCycles(1u); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 14 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 14 296 .loc 1 421 0 @@ -838,7 +838,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 345 .cfi_offset 6, -8 346 .cfi_offset 14, -4 109:.\Generated_Source\PSoC5/USBFS.c **** if(USBFS_initVar == 0u) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 15 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 15 347 .loc 1 109 0 @@ -898,7 +898,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 430:.\Generated_Source\PSoC5/USBFS.c **** ******************************************************************************** 431:.\Generated_Source\PSoC5/USBFS.c **** * 432:.\Generated_Source\PSoC5/USBFS.c **** * Summary: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 16 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 16 433:.\Generated_Source\PSoC5/USBFS.c **** * This function reinitialize the component configuration and is @@ -958,7 +958,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 478:.\Generated_Source\PSoC5/USBFS.c **** } 479:.\Generated_Source\PSoC5/USBFS.c **** #endif /* USBFS_ENABLE_HID_CLASS */ 480:.\Generated_Source\PSoC5/USBFS.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 17 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 17 481:.\Generated_Source\PSoC5/USBFS.c **** USBFS_transferState = USBFS_TRANS_STATE_IDLE; @@ -1018,7 +1018,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 490:.\Generated_Source\PSoC5/USBFS.c **** USBFS_lastPacketSize = 0u; 429 .loc 1 490 0 430 0024 0870 strb r0, [r1, #0] - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 18 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 18 495:.\Generated_Source\PSoC5/USBFS.c **** @@ -1078,7 +1078,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 517:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_configuration: Contains current configuration number 518:.\Generated_Source\PSoC5/USBFS.c **** * which is set by the Host using SET_CONFIGURATION request. 519:.\Generated_Source\PSoC5/USBFS.c **** * Initialized to zero in this API. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 19 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 19 520:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_deviceAddress: Contains current device address. This @@ -1138,7 +1138,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 547:.\Generated_Source\PSoC5/USBFS.c **** USBFS_PM_STBY_CFG_REG &= (uint8)(~USBFS_PM_STBY_EN_FSUSB); 485 .loc 1 547 0 486 0022 02F0FE00 and r0, r2, #254 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 20 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 20 487 0026 1874 strb r0, [r3, #16] @@ -1198,7 +1198,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 580:.\Generated_Source\PSoC5/USBFS.c **** USBFS_configurationChanged = 0u; 508 .loc 1 580 0 509 003e 0B49 ldr r1, .L21+20 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 21 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 21 578:.\Generated_Source\PSoC5/USBFS.c **** USBFS_configuration = 0u; @@ -1258,7 +1258,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 586:.\Generated_Source\PSoC5/USBFS.c **** 587:.\Generated_Source\PSoC5/USBFS.c **** 588:.\Generated_Source\PSoC5/USBFS.c **** /******************************************************************************* - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 22 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 22 589:.\Generated_Source\PSoC5/USBFS.c **** * Function Name: USBFS_CheckActivity @@ -1318,7 +1318,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 584 .LFB6: 613:.\Generated_Source\PSoC5/USBFS.c **** 614:.\Generated_Source\PSoC5/USBFS.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 23 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 23 615:.\Generated_Source\PSoC5/USBFS.c **** /******************************************************************************* @@ -1378,7 +1378,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 644:.\Generated_Source\PSoC5/USBFS.c **** * None. 645:.\Generated_Source\PSoC5/USBFS.c **** * 646:.\Generated_Source\PSoC5/USBFS.c **** * Return: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 24 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 24 647:.\Generated_Source\PSoC5/USBFS.c **** * Not zero value when new configuration has been changed, otherwise zero is @@ -1438,7 +1438,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 643 .type USBFS_GetInterfaceSetting, %function 644 USBFS_GetInterfaceSetting: 645 .LFB8: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 25 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 25 667:.\Generated_Source\PSoC5/USBFS.c **** @@ -1498,7 +1498,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 694:.\Generated_Source\PSoC5/USBFS.c **** * Summary: 695:.\Generated_Source\PSoC5/USBFS.c **** * Returned the state of the requested endpoint. 696:.\Generated_Source\PSoC5/USBFS.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 26 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 26 697:.\Generated_Source\PSoC5/USBFS.c **** * Parameters: @@ -1558,7 +1558,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 722:.\Generated_Source\PSoC5/USBFS.c **** * Valid values are between 1 and 8. 723:.\Generated_Source\PSoC5/USBFS.c **** * 724:.\Generated_Source\PSoC5/USBFS.c **** * Return: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 27 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 27 725:.\Generated_Source\PSoC5/USBFS.c **** * Returns the current byte count from the specified endpoint or 0 for an @@ -1618,7 +1618,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 738 .LVL46: 742:.\Generated_Source\PSoC5/USBFS.c **** } 743:.\Generated_Source\PSoC5/USBFS.c **** return(result); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 28 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 28 744:.\Generated_Source\PSoC5/USBFS.c **** } @@ -1678,7 +1678,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 781:.\Generated_Source\PSoC5/USBFS.c **** if((USBFS_EP[epNumber].addr & USBFS_DIR_IN) != 0u ) 782:.\Generated_Source\PSoC5/USBFS.c **** { /* for the IN EP source is the SRAM memory buffer */ 783:.\Generated_Source\PSoC5/USBFS.c **** src = HI16(pData); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 29 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 29 784:.\Generated_Source\PSoC5/USBFS.c **** dst = HI16(CYDEV_PERIPH_BASE); @@ -1738,7 +1738,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 838:.\Generated_Source\PSoC5/USBFS.c **** USBFS_DmaChan[epNumber] = USBFS_ep8_DmaInitialize( 839:.\Generated_Source\PSoC5/USBFS.c **** USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); 840:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_DMA8_REMOVE */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 30 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 30 841:.\Generated_Source\PSoC5/USBFS.c **** break; @@ -1798,7 +1798,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 895:.\Generated_Source\PSoC5/USBFS.c **** * transfer. 896:.\Generated_Source\PSoC5/USBFS.c **** * 897:.\Generated_Source\PSoC5/USBFS.c **** * Parameters: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 31 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 31 898:.\Generated_Source\PSoC5/USBFS.c **** * epNumber: Contains the data endpoint number. @@ -1858,7 +1858,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 778 000a 184E ldr r6, .L52 923:.\Generated_Source\PSoC5/USBFS.c **** ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); 779 .loc 1 923 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 32 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 32 780 000c 1C01 lsls r4, r3, #4 @@ -1918,7 +1918,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 819 0044 49B9 cbnz r1, .L51 820 .L50: 941:.\Generated_Source\PSoC5/USBFS.c **** { - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 33 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 33 942:.\Generated_Source\PSoC5/USBFS.c **** /* Copy the data using the arbiter data register */ @@ -1978,7 +1978,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 863 .section .text.USBFS_EnableOutEP,"ax",%progbits 864 .align 1 865 .global USBFS_EnableOutEP - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 34 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 34 866 .thumb @@ -2038,7 +2038,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1000:.\Generated_Source\PSoC5/USBFS.c **** if(length > 0u) 1001:.\Generated_Source\PSoC5/USBFS.c **** { 1002:.\Generated_Source\PSoC5/USBFS.c **** /* Set Data ready status, This will generate DMA request */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 35 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 35 1003:.\Generated_Source\PSoC5/USBFS.c **** * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY; @@ -2098,7 +2098,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1057:.\Generated_Source\PSoC5/USBFS.c **** ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); 1058:.\Generated_Source\PSoC5/USBFS.c **** p = (reg8 *)(USBFS_ARB_RW1_DR_IND + ri); 1059:.\Generated_Source\PSoC5/USBFS.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 36 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 36 1060:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) @@ -2158,7 +2158,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1114:.\Generated_Source\PSoC5/USBFS.c **** /* Out EP will be (re)armed in arb ISR after transfer complete */ 1115:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ 1116:.\Generated_Source\PSoC5/USBFS.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 37 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 37 1117:.\Generated_Source\PSoC5/USBFS.c **** } @@ -2218,7 +2218,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 885 000a 0C21 movs r1, #12 886 000c 01FB0020 mla r0, r1, r0, r2 887 .LVL60: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 38 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 38 888 0010 0021 movs r1, #0 @@ -2278,7 +2278,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 935 0006 D9B2 uxtb r1, r3 936 .LVL63: 937 0008 0729 cmp r1, #7 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 39 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 39 1045:.\Generated_Source\PSoC5/USBFS.c **** { @@ -2338,7 +2338,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 982 003c 02E0 b .L59 983 .LVL72: 984 .L62: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 40 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 40 1120:.\Generated_Source\PSoC5/USBFS.c **** length = 0u; @@ -2398,7 +2398,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1015 .LVL74: 1181:.\Generated_Source\PSoC5/USBFS.c **** uint8 ri ; 1182:.\Generated_Source\PSoC5/USBFS.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 41 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 41 1183:.\Generated_Source\PSoC5/USBFS.c **** if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) @@ -2458,7 +2458,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1205:.\Generated_Source\PSoC5/USBFS.c **** * 1206:.\Generated_Source\PSoC5/USBFS.c **** * Return: 1207:.\Generated_Source\PSoC5/USBFS.c **** * None. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 42 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 42 1208:.\Generated_Source\PSoC5/USBFS.c **** * @@ -2518,7 +2518,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1077 @ link register save eliminated. 1078 .LVL79: 1233:.\Generated_Source\PSoC5/USBFS.c **** uint8 ri; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 43 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 43 1234:.\Generated_Source\PSoC5/USBFS.c **** uint8 cr = 0u; @@ -2578,7 +2578,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1247:.\Generated_Source\PSoC5/USBFS.c **** * Function Name: USBFS_SetPowerStatus 1248:.\Generated_Source\PSoC5/USBFS.c **** ******************************************************************************** 1249:.\Generated_Source\PSoC5/USBFS.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 44 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 44 1250:.\Generated_Source\PSoC5/USBFS.c **** * Summary: @@ -2638,7 +2638,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1145 0014 00000000 .word USBFS_deviceStatus 1146 .cfi_endproc 1147 .LFE17: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 45 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 45 1148 .size USBFS_SetPowerStatus, .-USBFS_SetPowerStatus @@ -2698,7 +2698,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1322:.\Generated_Source\PSoC5/USBFS.c **** *******************************************************************************/ 1323:.\Generated_Source\PSoC5/USBFS.c **** uint8 USBFS_RWUEnabled(void) 1324:.\Generated_Source\PSoC5/USBFS.c **** { - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 46 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 46 1157 .loc 1 1324 0 @@ -2750,15 +2750,15 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1195 0006 00000000 .4byte .Ldebug_abbrev0 1196 000a 04 .byte 0x4 1197 000b 01 .uleb128 0x1 - 1198 000c E5020000 .4byte .LASF72 + 1198 000c F6020000 .4byte .LASF72 1199 0010 01 .byte 0x1 1200 0011 B3000000 .4byte .LASF73 - 1201 0015 B9010000 .4byte .LASF74 + 1201 0015 61020000 .4byte .LASF74 1202 0019 00000000 .4byte .Ldebug_ranges0+0 1203 001d 00000000 .4byte 0 1204 0021 00000000 .4byte 0 1205 0025 00000000 .4byte .Ldebug_line0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 47 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 47 1206 0029 02 .uleb128 0x2 @@ -2768,15 +2768,15 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1210 0030 02 .uleb128 0x2 1211 0031 01 .byte 0x1 1212 0032 08 .byte 0x8 - 1213 0033 47030000 .4byte .LASF1 + 1213 0033 58030000 .4byte .LASF1 1214 0037 02 .uleb128 0x2 1215 0038 02 .byte 0x2 1216 0039 05 .byte 0x5 - 1217 003a 55030000 .4byte .LASF2 + 1217 003a 66030000 .4byte .LASF2 1218 003e 02 .uleb128 0x2 1219 003f 02 .byte 0x2 1220 0040 07 .byte 0x7 - 1221 0041 3A020000 .4byte .LASF3 + 1221 0041 1A020000 .4byte .LASF3 1222 0045 02 .uleb128 0x2 1223 0046 04 .byte 0x4 1224 0047 05 .byte 0x5 @@ -2784,7 +2784,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1226 004c 02 .uleb128 0x2 1227 004d 04 .byte 0x4 1228 004e 07 .byte 0x7 - 1229 004f 11020000 .4byte .LASF5 + 1229 004f F1010000 .4byte .LASF5 1230 0053 02 .uleb128 0x2 1231 0054 08 .byte 0x8 1232 0055 05 .byte 0x5 @@ -2800,7 +2800,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1242 0068 02 .uleb128 0x2 1243 0069 04 .byte 0x4 1244 006a 07 .byte 0x7 - 1245 006b 04020000 .4byte .LASF8 + 1245 006b E4010000 .4byte .LASF8 1246 006f 04 .uleb128 0x4 1247 0070 6C010000 .4byte .LASF9 1248 0074 02 .byte 0x2 @@ -2818,11 +2818,11 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1260 008c 4C000000 .4byte 0x4c 1261 0090 02 .uleb128 0x2 1262 0091 04 .byte 0x4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 48 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 48 1263 0092 04 .byte 0x4 - 1264 0093 BD020000 .4byte .LASF12 + 1264 0093 CE020000 .4byte .LASF12 1265 0097 02 .uleb128 0x2 1266 0098 08 .byte 0x8 1267 0099 04 .byte 0x4 @@ -2830,23 +2830,23 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1269 009e 02 .uleb128 0x2 1270 009f 01 .byte 0x1 1271 00a0 08 .byte 0x8 - 1272 00a1 CD030000 .4byte .LASF14 + 1272 00a1 DE030000 .4byte .LASF14 1273 00a5 04 .uleb128 0x4 - 1274 00a6 2E030000 .4byte .LASF15 + 1274 00a6 3F030000 .4byte .LASF15 1275 00aa 02 .byte 0x2 1276 00ab F0 .byte 0xf0 1277 00ac B0000000 .4byte 0xb0 1278 00b0 05 .uleb128 0x5 1279 00b1 6F000000 .4byte 0x6f 1280 00b5 04 .uleb128 0x4 - 1281 00b6 81020000 .4byte .LASF16 + 1281 00b6 92020000 .4byte .LASF16 1282 00ba 02 .byte 0x2 1283 00bb F2 .byte 0xf2 1284 00bc C0000000 .4byte 0xc0 1285 00c0 05 .uleb128 0x5 1286 00c1 85000000 .4byte 0x85 1287 00c5 06 .uleb128 0x6 - 1288 00c6 D7030000 .4byte .LASF17 + 1288 00c6 E8030000 .4byte .LASF17 1289 00ca 02 .byte 0x2 1290 00cb 0201 .2byte 0x102 1291 00cd D1000000 .4byte 0xd1 @@ -2858,14 +2858,14 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1297 00d9 02 .uleb128 0x2 1298 00da 04 .byte 0x4 1299 00db 07 .byte 0x7 - 1300 00dc 91020000 .4byte .LASF18 + 1300 00dc A2020000 .4byte .LASF18 1301 00e0 09 .uleb128 0x9 1302 00e1 0C .byte 0xc 1303 00e2 03 .byte 0x3 1304 00e3 79 .byte 0x79 1305 00e4 67010000 .4byte 0x167 1306 00e8 0A .uleb128 0xa - 1307 00e9 9A020000 .4byte .LASF19 + 1307 00e9 AB020000 .4byte .LASF19 1308 00ed 03 .byte 0x3 1309 00ee 7B .byte 0x7b 1310 00ef 6F000000 .4byte 0x6f @@ -2873,18 +2873,18 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1312 00f4 23 .byte 0x23 1313 00f5 00 .uleb128 0 1314 00f6 0A .uleb128 0xa - 1315 00f7 C3020000 .4byte .LASF20 + 1315 00f7 D4020000 .4byte .LASF20 1316 00fb 03 .byte 0x3 1317 00fc 7C .byte 0x7c 1318 00fd 6F000000 .4byte 0x6f 1319 0101 02 .byte 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 49 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 49 1320 0102 23 .byte 0x23 1321 0103 01 .uleb128 0x1 1322 0104 0A .uleb128 0xa - 1323 0105 87020000 .4byte .LASF21 + 1323 0105 98020000 .4byte .LASF21 1324 0109 03 .byte 0x3 1325 010a 7D .byte 0x7d 1326 010b 6F000000 .4byte 0x6f @@ -2908,7 +2908,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1344 012c 23 .byte 0x23 1345 012d 04 .uleb128 0x4 1346 012e 0A .uleb128 0xa - 1347 012f ED010000 .4byte .LASF24 + 1347 012f CD010000 .4byte .LASF24 1348 0133 03 .byte 0x3 1349 0134 80 .byte 0x80 1350 0135 6F000000 .4byte 0x6f @@ -2916,7 +2916,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1352 013a 23 .byte 0x23 1353 013b 05 .uleb128 0x5 1354 013c 0A .uleb128 0xa - 1355 013d FB030000 .4byte .LASF25 + 1355 013d 0C040000 .4byte .LASF25 1356 0141 03 .byte 0x3 1357 0142 81 .byte 0x81 1358 0143 7A000000 .4byte 0x7a @@ -2924,7 +2924,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1360 0148 23 .byte 0x23 1361 0149 06 .uleb128 0x6 1362 014a 0A .uleb128 0xa - 1363 014b E4030000 .4byte .LASF26 + 1363 014b F5030000 .4byte .LASF26 1364 014f 03 .byte 0x3 1365 0150 82 .byte 0x82 1366 0151 7A000000 .4byte 0x7a @@ -2932,25 +2932,25 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1368 0156 23 .byte 0x23 1369 0157 08 .uleb128 0x8 1370 0158 0A .uleb128 0xa - 1371 0159 5C020000 .4byte .LASF27 + 1371 0159 3C020000 .4byte .LASF27 1372 015d 03 .byte 0x3 1373 015e 83 .byte 0x83 1374 015f 6F000000 .4byte 0x6f 1375 0163 02 .byte 0x2 1376 0164 23 .byte 0x23 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 50 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 50 1377 0165 0A .uleb128 0xa 1378 0166 00 .byte 0 1379 0167 04 .uleb128 0x4 - 1380 0168 9D030000 .4byte .LASF28 + 1380 0168 AE030000 .4byte .LASF28 1381 016c 03 .byte 0x3 1382 016d 84 .byte 0x84 1383 016e E0000000 .4byte 0xe0 1384 0172 0B .uleb128 0xb 1385 0173 01 .byte 0x1 - 1386 0174 B2020000 .4byte .LASF29 + 1386 0174 C3020000 .4byte .LASF29 1387 0178 01 .byte 0x1 1388 0179 87 .byte 0x87 1389 017a 01 .byte 0x1 @@ -2960,7 +2960,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1393 0187 01 .byte 0x1 1394 0188 E0020000 .4byte 0x2e0 1395 018c 0C .uleb128 0xc - 1396 018d 40040000 .4byte .LASF33 + 1396 018d 51040000 .4byte .LASF33 1397 0191 01 .byte 0x1 1398 0192 89 .byte 0x89 1399 0193 6F000000 .4byte 0x6f @@ -2998,7 +2998,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1431 01da 50 .byte 0x50 1432 01db 02 .byte 0x2 1433 01dc 08 .byte 0x8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 51 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 51 1434 01dd 28 .byte 0x28 @@ -3058,7 +3058,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1488 0240 01 .byte 0x1 1489 0241 50 .byte 0x50 1490 0242 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 52 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 52 1491 0243 45 .byte 0x45 @@ -3118,7 +3118,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1545 029d D2000000 .4byte .LVL15 1546 02a1 99080000 .4byte 0x899 1547 02a5 B5020000 .4byte 0x2b5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 53 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 53 1548 02a9 0F .uleb128 0xf @@ -3178,11 +3178,11 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1602 0301 4201 .2byte 0x142 1603 0303 6F000000 .4byte 0x6f 1604 0307 5E000000 .4byte .LLST3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 54 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 54 1605 030b 12 .uleb128 0x12 - 1606 030c D2030000 .4byte .LASF32 + 1606 030c E3030000 .4byte .LASF32 1607 0310 01 .byte 0x1 1608 0311 4201 .2byte 0x142 1609 0313 6F000000 .4byte 0x6f @@ -3205,7 +3205,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1626 0338 00 .byte 0 1627 0339 0B .uleb128 0xb 1628 033a 01 .byte 0x1 - 1629 033b EF030000 .4byte .LASF34 + 1629 033b 00040000 .4byte .LASF34 1630 033f 01 .byte 0x1 1631 0340 6A .byte 0x6a 1632 0341 01 .byte 0x1 @@ -3221,7 +3221,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1642 035a 6F000000 .4byte 0x6f 1643 035e EC000000 .4byte .LLST7 1644 0362 15 .uleb128 0x15 - 1645 0363 D2030000 .4byte .LASF32 + 1645 0363 E3030000 .4byte .LASF32 1646 0367 01 .byte 0x1 1647 0368 6A .byte 0x6a 1648 0369 6F000000 .4byte 0x6f @@ -3238,7 +3238,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1659 0386 51 .byte 0x51 1660 0387 02 .byte 0x2 1661 0388 75 .byte 0x75 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 55 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 55 1662 0389 00 .sleb128 0 @@ -3252,7 +3252,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1670 0391 00 .byte 0 1671 0392 16 .uleb128 0x16 1672 0393 01 .byte 0x1 - 1673 0394 2A040000 .4byte .LASF35 + 1673 0394 3B040000 .4byte .LASF35 1674 0398 01 .byte 0x1 1675 0399 D301 .2byte 0x1d3 1676 039b 01 .byte 0x1 @@ -3284,7 +3284,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1702 03d0 01 .byte 0x1 1703 03d1 18 .uleb128 0x18 1704 03d2 01 .byte 0x1 - 1705 03d3 51040000 .4byte .LASF36 + 1705 03d3 62040000 .4byte .LASF36 1706 03d7 01 .byte 0x1 1707 03d8 5C02 .2byte 0x25c 1708 03da 01 .byte 0x1 @@ -3298,7 +3298,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1716 03eb FE030000 .4byte 0x3fe 1717 03ef 13 .uleb128 0x13 1718 03f0 7200 .ascii "r\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 56 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 56 1719 03f2 01 .byte 0x1 @@ -3342,7 +3342,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1757 0446 00 .byte 0 1758 0447 18 .uleb128 0x18 1759 0448 01 .byte 0x1 - 1760 0449 91040000 .4byte .LASF38 + 1760 0449 A2040000 .4byte .LASF38 1761 044d 01 .byte 0x1 1762 044e AB02 .2byte 0x2ab 1763 0450 01 .byte 0x1 @@ -3358,7 +3358,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1773 0466 79000000 .4byte .LASF39 1774 046a 01 .byte 0x1 1775 046b AB02 .2byte 0x2ab - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 57 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 57 1776 046d 6F000000 .4byte 0x6f @@ -3366,7 +3366,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1778 0475 00 .byte 0 1779 0476 18 .uleb128 0x18 1780 0477 01 .byte 0x1 - 1781 0478 19040000 .4byte .LASF40 + 1781 0478 2A040000 .4byte .LASF40 1782 047c 01 .byte 0x1 1783 047d C002 .2byte 0x2c0 1784 047f 01 .byte 0x1 @@ -3387,7 +3387,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1799 04a4 00 .byte 0 1800 04a5 18 .uleb128 0x18 1801 04a6 01 .byte 0x1 - 1802 04a7 AB040000 .4byte .LASF42 + 1802 04a7 BC040000 .4byte .LASF42 1803 04ab 01 .byte 0x1 1804 04ac D902 .2byte 0x2d9 1805 04ae 01 .byte 0x1 @@ -3412,18 +3412,18 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1824 04da 6F000000 .4byte 0x6f 1825 04de E3010000 .4byte .LLST15 1826 04e2 1A .uleb128 0x1a - 1827 04e3 BC040000 .4byte .LASF43 + 1827 04e3 CD040000 .4byte .LASF43 1828 04e7 01 .byte 0x1 1829 04e8 DC02 .2byte 0x2dc 1830 04ea 7A000000 .4byte 0x7a 1831 04ee 09020000 .4byte .LLST16 1832 04f2 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 58 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 58 1833 04f3 11 .uleb128 0x11 1834 04f4 01 .byte 0x1 - 1835 04f5 82040000 .4byte .LASF44 + 1835 04f5 93040000 .4byte .LASF44 1836 04f9 01 .byte 0x1 1837 04fa 9003 .2byte 0x390 1838 04fc 01 .byte 0x1 @@ -3445,7 +3445,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1854 0526 66050000 .4byte 0x566 1855 052a A8020000 .4byte .LLST19 1856 052e 12 .uleb128 0x12 - 1857 052f C6030000 .4byte .LASF46 + 1857 052f D7030000 .4byte .LASF46 1858 0533 01 .byte 0x1 1859 0534 9003 .2byte 0x390 1860 0536 7A000000 .4byte 0x7a @@ -3478,10 +3478,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1887 0573 A5000000 .4byte 0xa5 1888 0577 16 .uleb128 0x16 1889 0578 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 59 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 59 - 1890 0579 5F030000 .4byte .LASF47 + 1890 0579 70030000 .4byte .LASF47 1891 057d 01 .byte 0x1 1892 057e 7D04 .2byte 0x47d 1893 0580 01 .byte 0x1 @@ -3507,7 +3507,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1913 05b0 00 .byte 0 1914 05b1 1D .uleb128 0x1d 1915 05b2 01 .byte 0x1 - 1916 05b3 F4010000 .4byte .LASF48 + 1916 05b3 D4010000 .4byte .LASF48 1917 05b7 01 .byte 0x1 1918 05b8 1304 .2byte 0x413 1919 05ba 01 .byte 0x1 @@ -3530,7 +3530,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1936 05e8 60060000 .4byte 0x660 1937 05ec E5030000 .4byte .LLST27 1938 05f0 12 .uleb128 0x12 - 1939 05f1 C6030000 .4byte .LASF46 + 1939 05f1 D7030000 .4byte .LASF46 1940 05f5 01 .byte 0x1 1941 05f6 1304 .2byte 0x413 1942 05f8 7A000000 .4byte 0x7a @@ -3538,7 +3538,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1944 0600 13 .uleb128 0x13 1945 0601 726900 .ascii "ri\000" 1946 0604 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 60 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 60 1947 0605 1604 .2byte 0x416 @@ -3557,7 +3557,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1960 0623 7A000000 .4byte 0x7a 1961 0627 89040000 .4byte .LLST31 1962 062b 1A .uleb128 0x1a - 1963 062c 65040000 .4byte .LASF49 + 1963 062c 76040000 .4byte .LASF49 1964 0630 01 .byte 0x1 1965 0631 1C04 .2byte 0x41c 1966 0633 7A000000 .4byte 0x7a @@ -3589,7 +3589,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 1992 0662 6F000000 .4byte 0x6f 1993 0666 16 .uleb128 0x16 1994 0667 01 .byte 0x1 - 1995 0668 6F040000 .4byte .LASF50 + 1995 0668 80040000 .4byte .LASF50 1996 066c 01 .byte 0x1 1997 066d 9B04 .2byte 0x49b 1998 066f 01 .byte 0x1 @@ -3598,7 +3598,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 2001 0678 02 .byte 0x2 2002 0679 7D .byte 0x7d 2003 067a 00 .sleb128 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 61 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 61 2004 067b 01 .byte 0x1 @@ -3630,7 +3630,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 2030 06b5 01 .byte 0x1 2031 06b6 C9060000 .4byte 0x6c9 2032 06ba 1E .uleb128 0x1e - 2033 06bb BF030000 .4byte .LASF52 + 2033 06bb D0030000 .4byte .LASF52 2034 06bf 01 .byte 0x1 2035 06c0 BA04 .2byte 0x4ba 2036 06c2 6F000000 .4byte 0x6f @@ -3658,7 +3658,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 2058 06ef 6F000000 .4byte 0x6f 2059 06f3 E8040000 .4byte .LLST35 2060 06f7 13 .uleb128 0x13 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 62 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 62 2061 06f8 726900 .ascii "ri\000" @@ -3708,7 +3708,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 2105 075a 01 .byte 0x1 2106 075b 70070000 .4byte 0x770 2107 075f 1A .uleb128 0x1a - 2108 0760 BC040000 .4byte .LASF43 + 2108 0760 CD040000 .4byte .LASF43 2109 0764 01 .byte 0x1 2110 0765 2D05 .2byte 0x52d 2111 0767 6F000000 .4byte 0x6f @@ -3718,7 +3718,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 2115 0771 1D000000 .4byte .LASF57 2116 0775 01 .byte 0x1 2117 0776 36 .byte 0x36 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 63 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 63 2118 0777 6F000000 .4byte 0x6f @@ -3727,35 +3727,35 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 2121 077d 03 .byte 0x3 2122 077e 00000000 .4byte USBFS_initVar 2123 0782 20 .uleb128 0x20 - 2124 0783 B2030000 .4byte .LASF58 + 2124 0783 C3030000 .4byte .LASF58 2125 0787 03 .byte 0x3 2126 0788 1802 .2byte 0x218 2127 078a B0000000 .4byte 0xb0 2128 078e 01 .byte 0x1 2129 078f 01 .byte 0x1 2130 0790 20 .uleb128 0x20 - 2131 0791 33030000 .4byte .LASF59 + 2131 0791 44030000 .4byte .LASF59 2132 0795 03 .byte 0x3 2133 0796 1902 .2byte 0x219 2134 0798 B0000000 .4byte 0xb0 2135 079c 01 .byte 0x1 2136 079d 01 .byte 0x1 2137 079e 20 .uleb128 0x20 - 2138 079f D9010000 .4byte .LASF60 + 2138 079f B9010000 .4byte .LASF60 2139 07a3 03 .byte 0x3 2140 07a4 1A02 .2byte 0x21a 2141 07a6 B0000000 .4byte 0xb0 2142 07aa 01 .byte 0x1 2143 07ab 01 .byte 0x1 2144 07ac 20 .uleb128 0x20 - 2145 07ad 66020000 .4byte .LASF61 + 2145 07ad 46020000 .4byte .LASF61 2146 07b1 03 .byte 0x3 2147 07b2 1B02 .2byte 0x21b 2148 07b4 B0000000 .4byte 0xb0 2149 07b8 01 .byte 0x1 2150 07b9 01 .byte 0x1 2151 07ba 20 .uleb128 0x20 - 2152 07bb 06040000 .4byte .LASF62 + 2152 07bb 17040000 .4byte .LASF62 2153 07bf 03 .byte 0x3 2154 07c0 1C02 .2byte 0x21c 2155 07c2 B0000000 .4byte 0xb0 @@ -3778,7 +3778,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 2172 07e6 05 .uleb128 0x5 2173 07e7 C8070000 .4byte 0x7c8 2174 07eb 23 .uleb128 0x23 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 64 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 64 2175 07ec 05010000 .4byte .LASF64 @@ -3788,7 +3788,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 2179 07f6 01 .byte 0x1 2180 07f7 01 .byte 0x1 2181 07f8 23 .uleb128 0x23 - 2182 07f9 86030000 .4byte .LASF65 + 2182 07f9 97030000 .4byte .LASF65 2183 07fd 04 .byte 0x4 2184 07fe 39 .byte 0x39 2185 07ff 05080000 .4byte 0x805 @@ -3811,7 +3811,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 2202 0825 08 .byte 0x8 2203 0826 00 .byte 0 2204 0827 23 .uleb128 0x23 - 2205 0828 CE020000 .4byte .LASF67 + 2205 0828 DF020000 .4byte .LASF67 2206 082c 04 .byte 0x4 2207 082d 3F .byte 0x3f 2208 082e 34080000 .4byte 0x834 @@ -3820,7 +3820,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 2211 0834 05 .uleb128 0x5 2212 0835 17080000 .4byte 0x817 2213 0839 23 .uleb128 0x23 - 2214 083a 71030000 .4byte .LASF68 + 2214 083a 82030000 .4byte .LASF68 2215 083e 04 .byte 0x4 2216 083f 48 .byte 0x48 2217 0840 B0000000 .4byte 0xb0 @@ -3828,7 +3828,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 2219 0845 01 .byte 0x1 2220 0846 24 .uleb128 0x24 2221 0847 01 .byte 0x1 - 2222 0848 23020000 .4byte .LASF77 + 2222 0848 03020000 .4byte .LASF77 2223 084c 05 .byte 0x5 2224 084d 7E .byte 0x7e 2225 084e 01 .byte 0x1 @@ -3838,7 +3838,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 2229 0855 01 .byte 0x1 2230 0856 7B010000 .4byte .LASF69 2231 085a 05 .byte 0x5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 65 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 65 2232 085b 78 .byte 0x78 @@ -3861,7 +3861,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 2249 087b 00 .byte 0 2250 087c 27 .uleb128 0x27 2251 087d 01 .byte 0x1 - 2252 087e 4D020000 .4byte .LASF78 + 2252 087e 2D020000 .4byte .LASF78 2253 0882 05 .byte 0x5 2254 0883 89 .byte 0x89 2255 0884 01 .byte 0x1 @@ -3875,7 +3875,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 2263 0898 00 .byte 0 2264 0899 25 .uleb128 0x25 2265 089a 01 .byte 0x1 - 2266 089b A1020000 .4byte .LASF71 + 2266 089b B2020000 .4byte .LASF71 2267 089f 05 .byte 0x5 2268 08a0 8C .byte 0x8c 2269 08a1 01 .byte 0x1 @@ -3888,7 +3888,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 2276 08b1 00 .byte 0 2277 08b2 28 .uleb128 0x28 2278 08b3 01 .byte 0x1 - 2279 08b4 D7020000 .4byte .LASF79 + 2279 08b4 E8020000 .4byte .LASF79 2280 08b8 05 .byte 0x5 2281 08b9 7A .byte 0x7a 2282 08ba 01 .byte 0x1 @@ -3898,7 +3898,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 2286 08c1 00 .byte 0 2287 08c2 00 .byte 0 2288 .section .debug_abbrev,"",%progbits - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 66 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 66 2289 .Ldebug_abbrev0: @@ -3958,7 +3958,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 2343 0035 13 .uleb128 0x13 2344 0036 00 .byte 0 2345 0037 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 67 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 67 2346 0038 05 .uleb128 0x5 @@ -4018,7 +4018,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 2400 006e 3A .uleb128 0x3a 2401 006f 0B .uleb128 0xb 2402 0070 3B .uleb128 0x3b - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 68 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 68 2403 0071 0B .uleb128 0xb @@ -4078,7 +4078,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 2457 00aa 00 .byte 0 2458 00ab 00 .byte 0 2459 00ac 0E .uleb128 0xe - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 69 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 69 2460 00ad 898201 .uleb128 0x4109 @@ -4138,7 +4138,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 2514 00ec 00 .byte 0 2515 00ed 12 .uleb128 0x12 2516 00ee 05 .uleb128 0x5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 70 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 70 2517 00ef 00 .byte 0 @@ -4198,7 +4198,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 2571 0127 01 .byte 0x1 2572 0128 3F .uleb128 0x3f 2573 0129 0C .uleb128 0xc - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 71 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 71 2574 012a 03 .uleb128 0x3 @@ -4258,7 +4258,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 2628 0162 27 .uleb128 0x27 2629 0163 0C .uleb128 0xc 2630 0164 49 .uleb128 0x49 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 72 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 72 2631 0165 13 .uleb128 0x13 @@ -4318,7 +4318,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 2685 019d 34 .uleb128 0x34 2686 019e 00 .byte 0 2687 019f 03 .uleb128 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 73 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 73 2688 01a0 08 .uleb128 0x8 @@ -4378,7 +4378,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 2742 01d7 02 .uleb128 0x2 2743 01d8 0A .uleb128 0xa 2744 01d9 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 74 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 74 2745 01da 00 .byte 0 @@ -4438,7 +4438,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 2799 0210 34 .uleb128 0x34 2800 0211 00 .byte 0 2801 0212 03 .uleb128 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 75 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 75 2802 0213 0E .uleb128 0xe @@ -4498,7 +4498,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 2856 0249 49 .uleb128 0x49 2857 024a 13 .uleb128 0x13 2858 024b 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 76 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 76 2859 024c 00 .byte 0 @@ -4558,7 +4558,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 2913 001c 00000000 .4byte 0 2914 .LLST1: 2915 0020 0A000000 .4byte .LVL1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 77 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 77 2916 0024 12000000 .4byte .LVL2 @@ -4618,7 +4618,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 2970 00a8 00000000 .4byte 0 2971 .LLST5: 2972 00ac 00000000 .4byte .LVL18 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 78 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 78 2973 00b0 08000000 .4byte .LVL19 @@ -4678,7 +4678,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 3027 0132 08000000 .4byte .LVL28 3028 0136 0200 .2byte 0x2 3029 0138 30 .byte 0x30 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 79 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 79 3030 0139 9F .byte 0x9f @@ -4738,7 +4738,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 3084 01be 00000000 .4byte 0 3085 .LLST14: 3086 01c2 00000000 .4byte .LVL38 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 80 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 80 3087 01c6 02000000 .4byte .LVL39 @@ -4798,7 +4798,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 3141 023a 0100 .2byte 0x1 3142 023c 51 .byte 0x51 3143 023d 22000000 .4byte .LVL45 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 81 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 81 3144 0241 24000000 .4byte .LVL46 @@ -4858,7 +4858,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 3198 02c5 7C000000 .4byte .LFE11 3199 02c9 0100 .2byte 0x1 3200 02cb 51 .byte 0x51 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 82 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 82 3201 02cc 00000000 .4byte 0 @@ -4918,7 +4918,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 3255 0348 0100 .2byte 0x1 3256 034a 55 .byte 0x55 3257 034b 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 83 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 83 3258 034f 00000000 .4byte 0 @@ -4978,7 +4978,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 3312 03ce 50 .byte 0x50 3313 03cf 44000000 .4byte .LVL73 3314 03d3 4C000000 .4byte .LFE12 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 84 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 84 3315 03d7 0400 .2byte 0x4 @@ -5038,7 +5038,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 3369 045c 34 .byte 0x34 3370 045d 24 .byte 0x24 3371 045e 9F .byte 0x9f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 85 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 85 3372 045f 1D000000 .4byte .LVL67-1 @@ -5098,7 +5098,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 3426 04df 9F .byte 0x9f 3427 04e0 00000000 .4byte 0 3428 04e4 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 86 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 86 3429 .LLST35: @@ -5158,7 +5158,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 3483 056b F3 .byte 0xf3 3484 056c 01 .uleb128 0x1 3485 056d 50 .byte 0x50 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 87 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 87 3486 056e 9F .byte 0x9f @@ -5218,7 +5218,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 3540 0040 00000000 .4byte .LFB6 3541 0044 0C000000 .4byte .LFE6-.LFB6 3542 0048 00000000 .4byte .LFB7 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 88 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 88 3543 004c 14000000 .4byte .LFE7-.LFB7 @@ -5278,7 +5278,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 3597 006c 4C000000 .4byte .LFE12 3598 0070 00000000 .4byte .LFB14 3599 0074 18000000 .4byte .LFE14 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 89 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 89 3600 0078 00000000 .4byte .LFB15 @@ -5338,7 +5338,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 3628 0074 61646472 .ascii "addr\000" 3628 00 3629 .LASF39: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 90 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 90 3630 0079 696E7465 .ascii "interfaceNumber\000" @@ -5398,7 +5398,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 3650 65725374 3650 61747573 3651 .LASF75: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 91 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 91 3652 0141 55534246 .ascii "USBFS_Stop\000" @@ -5444,264 +5444,265 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 1 3671 .LASF45: 3672 01b3 70446174 .ascii "pData\000" 3672 6100 - 3673 .LASF74: - 3674 01b9 573A5C53 .ascii "W:\\SCSI2SD\\USB_Bootloader.cydsn\000" - 3674 43534932 - 3674 53445C55 - 3674 53425F42 - 3674 6F6F746C - 3675 .LASF60: - 3676 01d9 55534246 .ascii "USBFS_configuration\000" - 3676 535F636F - 3676 6E666967 - 3676 75726174 - 3676 696F6E00 - 3677 .LASF24: - 3678 01ed 65704D6F .ascii "epMode\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 92 - - - 3678 646500 - 3679 .LASF48: - 3680 01f4 55534246 .ascii "USBFS_ReadOutEP\000" - 3680 535F5265 - 3680 61644F75 - 3680 74455000 - 3681 .LASF8: - 3682 0204 756E7369 .ascii "unsigned int\000" - 3682 676E6564 - 3682 20696E74 - 3682 00 - 3683 .LASF5: - 3684 0211 6C6F6E67 .ascii "long unsigned int\000" - 3684 20756E73 - 3684 69676E65 - 3684 6420696E - 3684 7400 - 3685 .LASF77: - 3686 0223 4379456E .ascii "CyEnterCriticalSection\000" - 3686 74657243 - 3686 72697469 - 3686 63616C53 - 3686 65637469 - 3687 .LASF3: - 3688 023a 73686F72 .ascii "short unsigned int\000" - 3688 7420756E - 3688 7369676E - 3688 65642069 - 3688 6E7400 - 3689 .LASF78: - 3690 024d 4379496E .ascii "CyIntSetVector\000" - 3690 74536574 - 3690 56656374 - 3690 6F7200 - 3691 .LASF27: - 3692 025c 696E7465 .ascii "interface\000" - 3692 72666163 - 3692 6500 - 3693 .LASF61: - 3694 0266 55534246 .ascii "USBFS_configurationChanged\000" - 3694 535F636F - 3694 6E666967 - 3694 75726174 - 3694 696F6E43 - 3695 .LASF16: - 3696 0281 72656733 .ascii "reg32\000" - 3696 3200 - 3697 .LASF21: - 3698 0287 68774570 .ascii "hwEpState\000" - 3698 53746174 - 3698 6500 - 3699 .LASF18: - 3700 0291 73697A65 .ascii "sizetype\000" - 3700 74797065 - 3700 00 - 3701 .LASF19: - 3702 029a 61747472 .ascii "attrib\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 93 - - - 3702 696200 - 3703 .LASF71: - 3704 02a1 4379496E .ascii "CyIntSetPriority\000" - 3704 74536574 - 3704 5072696F - 3704 72697479 - 3704 00 - 3705 .LASF29: - 3706 02b2 55534246 .ascii "USBFS_Init\000" - 3706 535F496E - 3706 697400 - 3707 .LASF12: - 3708 02bd 666C6F61 .ascii "float\000" - 3708 7400 - 3709 .LASF20: - 3710 02c3 61706945 .ascii "apiEpState\000" - 3710 70537461 - 3710 746500 - 3711 .LASF67: - 3712 02ce 55534246 .ascii "USBFS_EP\000" - 3712 535F4550 - 3712 00 - 3713 .LASF79: - 3714 02d7 43794465 .ascii "CyDelayCycles\000" - 3714 6C617943 - 3714 79636C65 - 3714 7300 - 3715 .LASF72: - 3716 02e5 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 3716 4320342E - 3716 372E3320 - 3716 32303133 - 3716 30333132 - 3717 0318 616E6368 .ascii "anch revision 196615]\000" - 3717 20726576 - 3717 6973696F - 3717 6E203139 - 3717 36363135 - 3718 .LASF15: - 3719 032e 72656738 .ascii "reg8\000" - 3719 00 - 3720 .LASF59: - 3721 0333 55534246 .ascii "USBFS_transferState\000" - 3721 535F7472 - 3721 616E7366 - 3721 65725374 - 3721 61746500 - 3722 .LASF1: - 3723 0347 756E7369 .ascii "unsigned char\000" - 3723 676E6564 - 3723 20636861 - 3723 7200 - 3724 .LASF2: - 3725 0355 73686F72 .ascii "short int\000" - 3725 7420696E - 3725 7400 - 3726 .LASF47: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 94 - - - 3727 035f 55534246 .ascii "USBFS_EnableOutEP\000" - 3727 535F456E - 3727 61626C65 - 3727 4F757445 - 3727 5000 - 3728 .LASF68: - 3729 0371 55534246 .ascii "USBFS_lastPacketSize\000" - 3729 535F6C61 - 3729 73745061 - 3729 636B6574 - 3729 53697A65 - 3730 .LASF65: - 3731 0386 55534246 .ascii "USBFS_interfaceSetting\000" - 3731 535F696E - 3731 74657266 - 3731 61636553 - 3731 65747469 - 3732 .LASF28: - 3733 039d 545F5553 .ascii "T_USBFS_EP_CTL_BLOCK\000" - 3733 4246535F - 3733 45505F43 - 3733 544C5F42 - 3733 4C4F434B - 3734 .LASF58: - 3735 03b2 55534246 .ascii "USBFS_device\000" - 3735 535F6465 - 3735 76696365 - 3735 00 - 3736 .LASF52: - 3737 03bf 62537461 .ascii "bState\000" - 3737 746500 - 3738 .LASF46: - 3739 03c6 6C656E67 .ascii "length\000" - 3739 746800 - 3740 .LASF14: - 3741 03cd 63686172 .ascii "char\000" - 3741 00 - 3742 .LASF32: - 3743 03d2 6D6F6465 .ascii "mode\000" - 3743 00 - 3744 .LASF17: - 3745 03d7 63796973 .ascii "cyisraddress\000" - 3745 72616464 - 3745 72657373 - 3745 00 - 3746 .LASF26: - 3747 03e4 62756666 .ascii "bufferSize\000" - 3747 65725369 - 3747 7A6500 - 3748 .LASF34: - 3749 03ef 55534246 .ascii "USBFS_Start\000" - 3749 535F5374 - 3749 61727400 - 3750 .LASF25: - 3751 03fb 62756666 .ascii "buffOffset\000" - 3751 4F666673 - 3751 657400 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 95 - - - 3752 .LASF62: - 3753 0406 55534246 .ascii "USBFS_deviceStatus\000" - 3753 535F6465 - 3753 76696365 - 3753 53746174 - 3753 757300 - 3754 .LASF40: - 3755 0419 55534246 .ascii "USBFS_GetEPState\000" - 3755 535F4765 - 3755 74455053 - 3755 74617465 - 3755 00 - 3756 .LASF35: - 3757 042a 55534246 .ascii "USBFS_ReInitComponent\000" - 3757 535F5265 - 3757 496E6974 - 3757 436F6D70 - 3757 6F6E656E - 3758 .LASF33: - 3759 0440 656E6162 .ascii "enableInterrupts\000" - 3759 6C65496E - 3759 74657272 - 3759 75707473 - 3759 00 - 3760 .LASF36: - 3761 0451 55534246 .ascii "USBFS_CheckActivity\000" - 3761 535F4368 - 3761 65636B41 - 3761 63746976 - 3761 69747900 - 3762 .LASF49: - 3763 0465 78666572 .ascii "xferCount\000" - 3763 436F756E - 3763 7400 - 3764 .LASF50: - 3765 046f 55534246 .ascii "USBFS_DisableOutEP\000" - 3765 535F4469 - 3765 7361626C - 3765 654F7574 - 3765 455000 - 3766 .LASF44: - 3767 0482 55534246 .ascii "USBFS_LoadInEP\000" - 3767 535F4C6F - 3767 6164496E - 3767 455000 - 3768 .LASF38: - 3769 0491 55534246 .ascii "USBFS_GetInterfaceSetting\000" - 3769 535F4765 - 3769 74496E74 - 3769 65726661 - 3769 63655365 - 3770 .LASF42: - 3771 04ab 55534246 .ascii "USBFS_GetEPCount\000" - 3771 535F4765 - 3771 74455043 - 3771 6F756E74 - 3771 00 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccbOK9oc.s page 96 - - - 3772 .LASF43: - 3773 04bc 72657375 .ascii "result\000" - 3773 6C7400 - 3774 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br + 3673 .LASF60: + 3674 01b9 55534246 .ascii "USBFS_configuration\000" + 3674 535F636F + 3674 6E666967 + 3674 75726174 + 3674 696F6E00 + 3675 .LASF24: + 3676 01cd 65704D6F .ascii "epMode\000" + 3676 646500 + 3677 .LASF48: + 3678 01d4 55534246 .ascii "USBFS_ReadOutEP\000" + 3678 535F5265 + 3678 61644F75 + 3678 74455000 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 92 + + + 3679 .LASF8: + 3680 01e4 756E7369 .ascii "unsigned int\000" + 3680 676E6564 + 3680 20696E74 + 3680 00 + 3681 .LASF5: + 3682 01f1 6C6F6E67 .ascii "long unsigned int\000" + 3682 20756E73 + 3682 69676E65 + 3682 6420696E + 3682 7400 + 3683 .LASF77: + 3684 0203 4379456E .ascii "CyEnterCriticalSection\000" + 3684 74657243 + 3684 72697469 + 3684 63616C53 + 3684 65637469 + 3685 .LASF3: + 3686 021a 73686F72 .ascii "short unsigned int\000" + 3686 7420756E + 3686 7369676E + 3686 65642069 + 3686 6E7400 + 3687 .LASF78: + 3688 022d 4379496E .ascii "CyIntSetVector\000" + 3688 74536574 + 3688 56656374 + 3688 6F7200 + 3689 .LASF27: + 3690 023c 696E7465 .ascii "interface\000" + 3690 72666163 + 3690 6500 + 3691 .LASF61: + 3692 0246 55534246 .ascii "USBFS_configurationChanged\000" + 3692 535F636F + 3692 6E666967 + 3692 75726174 + 3692 696F6E43 + 3693 .LASF74: + 3694 0261 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" + 3694 43534932 + 3694 53445C73 + 3694 6F667477 + 3694 6172655C + 3695 0290 6E00 .ascii "n\000" + 3696 .LASF16: + 3697 0292 72656733 .ascii "reg32\000" + 3697 3200 + 3698 .LASF21: + 3699 0298 68774570 .ascii "hwEpState\000" + 3699 53746174 + 3699 6500 + 3700 .LASF18: + 3701 02a2 73697A65 .ascii "sizetype\000" + 3701 74797065 + 3701 00 + 3702 .LASF19: + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 93 + + + 3703 02ab 61747472 .ascii "attrib\000" + 3703 696200 + 3704 .LASF71: + 3705 02b2 4379496E .ascii "CyIntSetPriority\000" + 3705 74536574 + 3705 5072696F + 3705 72697479 + 3705 00 + 3706 .LASF29: + 3707 02c3 55534246 .ascii "USBFS_Init\000" + 3707 535F496E + 3707 697400 + 3708 .LASF12: + 3709 02ce 666C6F61 .ascii "float\000" + 3709 7400 + 3710 .LASF20: + 3711 02d4 61706945 .ascii "apiEpState\000" + 3711 70537461 + 3711 746500 + 3712 .LASF67: + 3713 02df 55534246 .ascii "USBFS_EP\000" + 3713 535F4550 + 3713 00 + 3714 .LASF79: + 3715 02e8 43794465 .ascii "CyDelayCycles\000" + 3715 6C617943 + 3715 79636C65 + 3715 7300 + 3716 .LASF72: + 3717 02f6 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" + 3717 4320342E + 3717 372E3320 + 3717 32303133 + 3717 30333132 + 3718 0329 616E6368 .ascii "anch revision 196615]\000" + 3718 20726576 + 3718 6973696F + 3718 6E203139 + 3718 36363135 + 3719 .LASF15: + 3720 033f 72656738 .ascii "reg8\000" + 3720 00 + 3721 .LASF59: + 3722 0344 55534246 .ascii "USBFS_transferState\000" + 3722 535F7472 + 3722 616E7366 + 3722 65725374 + 3722 61746500 + 3723 .LASF1: + 3724 0358 756E7369 .ascii "unsigned char\000" + 3724 676E6564 + 3724 20636861 + 3724 7200 + 3725 .LASF2: + 3726 0366 73686F72 .ascii "short int\000" + 3726 7420696E + 3726 7400 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 94 + + + 3727 .LASF47: + 3728 0370 55534246 .ascii "USBFS_EnableOutEP\000" + 3728 535F456E + 3728 61626C65 + 3728 4F757445 + 3728 5000 + 3729 .LASF68: + 3730 0382 55534246 .ascii "USBFS_lastPacketSize\000" + 3730 535F6C61 + 3730 73745061 + 3730 636B6574 + 3730 53697A65 + 3731 .LASF65: + 3732 0397 55534246 .ascii "USBFS_interfaceSetting\000" + 3732 535F696E + 3732 74657266 + 3732 61636553 + 3732 65747469 + 3733 .LASF28: + 3734 03ae 545F5553 .ascii "T_USBFS_EP_CTL_BLOCK\000" + 3734 4246535F + 3734 45505F43 + 3734 544C5F42 + 3734 4C4F434B + 3735 .LASF58: + 3736 03c3 55534246 .ascii "USBFS_device\000" + 3736 535F6465 + 3736 76696365 + 3736 00 + 3737 .LASF52: + 3738 03d0 62537461 .ascii "bState\000" + 3738 746500 + 3739 .LASF46: + 3740 03d7 6C656E67 .ascii "length\000" + 3740 746800 + 3741 .LASF14: + 3742 03de 63686172 .ascii "char\000" + 3742 00 + 3743 .LASF32: + 3744 03e3 6D6F6465 .ascii "mode\000" + 3744 00 + 3745 .LASF17: + 3746 03e8 63796973 .ascii "cyisraddress\000" + 3746 72616464 + 3746 72657373 + 3746 00 + 3747 .LASF26: + 3748 03f5 62756666 .ascii "bufferSize\000" + 3748 65725369 + 3748 7A6500 + 3749 .LASF34: + 3750 0400 55534246 .ascii "USBFS_Start\000" + 3750 535F5374 + 3750 61727400 + 3751 .LASF25: + 3752 040c 62756666 .ascii "buffOffset\000" + 3752 4F666673 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 95 + + + 3752 657400 + 3753 .LASF62: + 3754 0417 55534246 .ascii "USBFS_deviceStatus\000" + 3754 535F6465 + 3754 76696365 + 3754 53746174 + 3754 757300 + 3755 .LASF40: + 3756 042a 55534246 .ascii "USBFS_GetEPState\000" + 3756 535F4765 + 3756 74455053 + 3756 74617465 + 3756 00 + 3757 .LASF35: + 3758 043b 55534246 .ascii "USBFS_ReInitComponent\000" + 3758 535F5265 + 3758 496E6974 + 3758 436F6D70 + 3758 6F6E656E + 3759 .LASF33: + 3760 0451 656E6162 .ascii "enableInterrupts\000" + 3760 6C65496E + 3760 74657272 + 3760 75707473 + 3760 00 + 3761 .LASF36: + 3762 0462 55534246 .ascii "USBFS_CheckActivity\000" + 3762 535F4368 + 3762 65636B41 + 3762 63746976 + 3762 69747900 + 3763 .LASF49: + 3764 0476 78666572 .ascii "xferCount\000" + 3764 436F756E + 3764 7400 + 3765 .LASF50: + 3766 0480 55534246 .ascii "USBFS_DisableOutEP\000" + 3766 535F4469 + 3766 7361626C + 3766 654F7574 + 3766 455000 + 3767 .LASF44: + 3768 0493 55534246 .ascii "USBFS_LoadInEP\000" + 3768 535F4C6F + 3768 6164496E + 3768 455000 + 3769 .LASF38: + 3770 04a2 55534246 .ascii "USBFS_GetInterfaceSetting\000" + 3770 535F4765 + 3770 74496E74 + 3770 65726661 + 3770 63655365 + 3771 .LASF42: + 3772 04bc 55534246 .ascii "USBFS_GetEPCount\000" + 3772 535F4765 + 3772 74455043 + 3772 6F756E74 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 96 + + + 3772 00 + 3773 .LASF43: + 3774 04cd 72657375 .ascii "result\000" + 3774 6C7400 + 3775 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS.o index 1e57c17d7446ad88e397925b8c2346d04171f834..753aea9bcbeed1db93101dc6000b4012ac250f1d 100755 GIT binary patch delta 833 zcmZ8dT}YEr7(VaWceZbz-y~7+A2sKu-)u##3;)ZeBn&=kNL~!Y+U#bvP-|LNW=dCO z^a=%eQKAVYQH?GFg~-4wBVpl#?dUP?YnU|mn8!ZPh`$_k+h6gx>%cHJ^?l9IGXL@XDi zo0l^!DcN9}fp$l-i)qI3l_>69B8z1xtq4t5h+R3K@>;c@beLs0%~Y*kdatG@HKsh4 z&5<=4&42}J!8J-^EGLCT*GSWkBpR)k06yWo&C8jB8#Wh_9CZ)WVT;-b$8khG3zPU; z^@4#_b}!6fhrKR)iS7ZbTpn$w9F_%$59~Ftf@}6RID>{(14#^P4WvwJwQvsKYjrS$ z`58yyEk-k@UhU!jOq<=8z1W4vX9hJ zntZB^5V=&!hbc!noDOw@1%K)LVHfUp6u~nLIPzdU5piT@;(cEZ&J>RCIaV7A9tyVY z4f;d9vF^TjS5M@h&>n2=Y>vhHqOq=Uq{n+=Al!R8QCswdC!8e*1WaJWX@Vc06ON;( zFku$k3BTfWMI7f`I##;;sJnIScln_j=UpcF(BY0lJ&wAi^BrLTD=HTugd3G6gt4K@ zgeYFGio+lZ!=%Y}!d09$Os==$reV<6mU+tI2DW(Iu!W~QZs99o>>eI;X5*}92Tb8S fX~|N?7IE3g#y_Nm&{6Fc6Z;t3l3F5A-Cy_@@h-a8 delta 795 zcmZ9IPe@cz6vpql^WMyx=Tj6%^3RysjPrD6nhJHHrWGg^j695_7J{3mHUrW^?2l7v znj697b5#izQBa$7a1kg)T5dEb0t*Zb3ffo_ZTd%@JA<3v;yd?u&iTIg?t3#%OXGCC zlE!ALZffnHq!5%ALOdpx{~k&1``nUb9CmS$dRL}+n%E>YJ}toq1ess1NXWu2muZF;9}Ub;=E)$Pi*$&IAdLf7!XidDVj ziFTmgP!akLE`hV0qaDeH1}T6aRs(flPp+SCBc5AKYw1L8UYzJ$VCkwkn4*8G@If#ZVybZNsfNPDN#0uAG zyA6KZ!j|1e`_WLdOmY0Fap*WYY8~pvRBb;cQ51G4iUjKl=E9Er-41soOpDkT2~Y}M z5u3gs6|wbTg%H!|3>IQOl24OZ<=#@I5X<-wE`$}$=lJrdt&i0S@mKZI-O+Pp{{S$p Bs~i9T diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_Dm.lst b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_Dm.lst index 4b30ab98..df9af69b 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_Dm.lst +++ b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_Dm.lst @@ -1,4 +1,4 @@ -ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccc12yfW.s page 1 +ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccmaaXQv.s page 1 1 .syntax unified @@ -58,7 +58,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccc12yfW.s page 1 29:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Summary: 30:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Assign a new value to the digital port's data output register. 31:.\Generated_Source\PSoC5/USBFS_Dm.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccc12yfW.s page 2 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccmaaXQv.s page 2 32:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Parameters: @@ -118,7 +118,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccc12yfW.s page 1 53:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Parameters: 54:.\Generated_Source\PSoC5/USBFS_Dm.c **** * mode: Change the pins to this drive mode. 55:.\Generated_Source\PSoC5/USBFS_Dm.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccc12yfW.s page 3 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccmaaXQv.s page 3 56:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Return: @@ -178,7 +178,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccc12yfW.s page 1 80:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Note: 81:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Macro USBFS_Dm_ReadPS calls this function. 82:.\Generated_Source\PSoC5/USBFS_Dm.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccc12yfW.s page 4 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccmaaXQv.s page 4 83:.\Generated_Source\PSoC5/USBFS_Dm.c **** *******************************************************************************/ @@ -238,7 +238,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccc12yfW.s page 1 106:.\Generated_Source\PSoC5/USBFS_Dm.c **** return (USBFS_Dm_DR & USBFS_Dm_MASK) >> USBFS_Dm_SHIFT; 121 .loc 1 106 0 122 0000 014B ldr r3, .L11 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccc12yfW.s page 5 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccmaaXQv.s page 5 123 0002 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 @@ -263,10 +263,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccc12yfW.s page 1 141 0006 00000000 .4byte .Ldebug_abbrev0 142 000a 04 .byte 0x4 143 000b 01 .uleb128 0x1 - 144 000c 0E010000 .4byte .LASF20 + 144 000c 3F010000 .4byte .LASF20 145 0010 01 .byte 0x1 - 146 0011 89000000 .4byte .LASF21 - 147 0015 57010000 .4byte .LASF22 + 146 0011 BA000000 .4byte .LASF21 + 147 0015 76000000 .4byte .LASF22 148 0019 00000000 .4byte .Ldebug_ranges0+0 149 001d 00000000 .4byte 0 150 0021 00000000 .4byte 0 @@ -274,7 +274,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccc12yfW.s page 1 152 0029 02 .uleb128 0x2 153 002a 01 .byte 0x1 154 002b 06 .byte 0x6 - 155 002c 80010000 .4byte .LASF0 + 155 002c 91010000 .4byte .LASF0 156 0030 02 .uleb128 0x2 157 0031 01 .byte 0x1 158 0032 08 .byte 0x8 @@ -282,15 +282,15 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccc12yfW.s page 1 160 0037 02 .uleb128 0x2 161 0038 02 .byte 0x2 162 0039 05 .byte 0x5 - 163 003a FE000000 .4byte .LASF2 + 163 003a 2F010000 .4byte .LASF2 164 003e 02 .uleb128 0x2 165 003f 02 .byte 0x2 166 0040 07 .byte 0x7 - 167 0041 76000000 .4byte .LASF3 + 167 0041 A7000000 .4byte .LASF3 168 0045 02 .uleb128 0x2 169 0046 04 .byte 0x4 170 0047 05 .byte 0x5 - 171 0048 77010000 .4byte .LASF4 + 171 0048 88010000 .4byte .LASF4 172 004c 02 .uleb128 0x2 173 004d 04 .byte 0x4 174 004e 07 .byte 0x7 @@ -298,14 +298,14 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccc12yfW.s page 1 176 0053 02 .uleb128 0x2 177 0054 08 .byte 0x8 178 0055 05 .byte 0x5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccc12yfW.s page 6 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccmaaXQv.s page 6 - 179 0056 EB000000 .4byte .LASF6 + 179 0056 1C010000 .4byte .LASF6 180 005a 02 .uleb128 0x2 181 005b 08 .byte 0x8 182 005c 07 .byte 0x7 - 183 005d CF000000 .4byte .LASF7 + 183 005d 00010000 .4byte .LASF7 184 0061 03 .uleb128 0x3 185 0062 04 .byte 0x4 186 0063 05 .byte 0x5 @@ -313,9 +313,9 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccc12yfW.s page 1 188 0068 02 .uleb128 0x2 189 0069 04 .byte 0x4 190 006a 07 .byte 0x7 - 191 006b C2000000 .4byte .LASF8 + 191 006b F3000000 .4byte .LASF8 192 006f 04 .uleb128 0x4 - 193 0070 08010000 .4byte .LASF12 + 193 0070 39010000 .4byte .LASF12 194 0074 02 .byte 0x2 195 0075 5B .byte 0x5b 196 0076 30000000 .4byte 0x30 @@ -330,7 +330,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccc12yfW.s page 1 205 0088 02 .uleb128 0x2 206 0089 01 .byte 0x1 207 008a 08 .byte 0x8 - 208 008b F9000000 .4byte .LASF11 + 208 008b 2A010000 .4byte .LASF11 209 008f 04 .uleb128 0x4 210 0090 5F000000 .4byte .LASF13 211 0094 02 .byte 0x2 @@ -358,7 +358,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccc12yfW.s page 1 233 00bf 6F000000 .4byte 0x6f 234 00c3 00000000 .4byte .LLST0 235 00c7 08 .uleb128 0x8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccc12yfW.s page 7 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccmaaXQv.s page 7 236 00c8 23000000 .4byte .LASF23 @@ -381,7 +381,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccc12yfW.s page 1 253 00eb 01 .byte 0x1 254 00ec 00010000 .4byte 0x100 255 00f0 07 .uleb128 0x7 - 256 00f1 E6000000 .4byte .LASF17 + 256 00f1 17010000 .4byte .LASF17 257 00f5 01 .byte 0x1 258 00f6 3C .byte 0x3c 259 00f7 6F000000 .4byte 0x6f @@ -402,7 +402,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccc12yfW.s page 1 274 0118 01 .byte 0x1 275 0119 09 .uleb128 0x9 276 011a 01 .byte 0x1 - 277 011b AD000000 .4byte .LASF19 + 277 011b DE000000 .4byte .LASF19 278 011f 01 .byte 0x1 279 0120 68 .byte 0x68 280 0121 01 .byte 0x1 @@ -418,7 +418,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccc12yfW.s page 1 290 .Ldebug_abbrev0: 291 0000 01 .uleb128 0x1 292 0001 11 .uleb128 0x11 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccc12yfW.s page 8 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccmaaXQv.s page 8 293 0002 01 .byte 0x1 @@ -478,7 +478,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccc12yfW.s page 1 347 0038 05 .uleb128 0x5 348 0039 35 .uleb128 0x35 349 003a 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccc12yfW.s page 9 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccmaaXQv.s page 9 350 003b 49 .uleb128 0x49 @@ -538,7 +538,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccc12yfW.s page 1 404 0072 13 .uleb128 0x13 405 0073 02 .uleb128 0x2 406 0074 06 .uleb128 0x6 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccc12yfW.s page 10 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccmaaXQv.s page 10 407 0075 00 .byte 0 @@ -598,7 +598,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccc12yfW.s page 1 461 0031 00000000 .4byte 0 462 0035 00000000 .4byte 0 463 .LLST2: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccc12yfW.s page 11 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccmaaXQv.s page 11 464 0039 00000000 .4byte .LVL4 @@ -658,7 +658,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccc12yfW.s page 1 511 746500 512 .LASF18: 513 000f 55534246 .ascii "USBFS_Dm_Read\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccc12yfW.s page 12 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccmaaXQv.s page 12 513 535F446D @@ -697,79 +697,80 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccc12yfW.s page 1 529 69676E65 529 6420696E 529 7400 - 530 .LASF3: - 531 0076 73686F72 .ascii "short unsigned int\000" - 531 7420756E - 531 7369676E - 531 65642069 - 531 6E7400 - 532 .LASF21: - 533 0089 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\USBFS_Dm.c\000" - 533 6E657261 - 533 7465645F - 533 536F7572 - 533 63655C50 - 534 .LASF19: - 535 00ad 55534246 .ascii "USBFS_Dm_ReadDataReg\000" - 535 535F446D - 535 5F526561 - 535 64446174 - 535 61526567 - 536 .LASF8: - 537 00c2 756E7369 .ascii "unsigned int\000" - 537 676E6564 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccc12yfW.s page 13 + 530 .LASF22: + 531 0076 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" + 531 43534932 + 531 53445C73 + 531 6F667477 + 531 6172655C + 532 00a5 6E00 .ascii "n\000" + 533 .LASF3: + 534 00a7 73686F72 .ascii "short unsigned int\000" + 534 7420756E + 534 7369676E + 534 65642069 + 534 6E7400 + 535 .LASF21: + 536 00ba 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\USBFS_Dm.c\000" + 536 6E657261 + 536 7465645F + 536 536F7572 + 536 63655C50 + 537 .LASF19: + 538 00de 55534246 .ascii "USBFS_Dm_ReadDataReg\000" + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccmaaXQv.s page 13 - 537 20696E74 - 537 00 - 538 .LASF7: - 539 00cf 6C6F6E67 .ascii "long long unsigned int\000" - 539 206C6F6E - 539 6720756E - 539 7369676E - 539 65642069 - 540 .LASF17: - 541 00e6 6D6F6465 .ascii "mode\000" - 541 00 - 542 .LASF6: - 543 00eb 6C6F6E67 .ascii "long long int\000" - 543 206C6F6E - 543 6720696E - 543 7400 - 544 .LASF11: - 545 00f9 63686172 .ascii "char\000" - 545 00 - 546 .LASF2: - 547 00fe 73686F72 .ascii "short int\000" - 547 7420696E - 547 7400 - 548 .LASF12: - 549 0108 75696E74 .ascii "uint8\000" - 549 3800 - 550 .LASF20: - 551 010e 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 551 4320342E - 551 372E3320 - 551 32303133 - 551 30333132 - 552 0141 616E6368 .ascii "anch revision 196615]\000" - 552 20726576 - 552 6973696F - 552 6E203139 - 552 36363135 - 553 .LASF22: - 554 0157 573A5C53 .ascii "W:\\SCSI2SD\\USB_Bootloader.cydsn\000" - 554 43534932 - 554 53445C55 - 554 53425F42 - 554 6F6F746C - 555 .LASF4: - 556 0177 6C6F6E67 .ascii "long int\000" - 556 20696E74 - 556 00 - 557 .LASF0: - 558 0180 7369676E .ascii "signed char\000" - 558 65642063 - 558 68617200 - 559 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br + 538 535F446D + 538 5F526561 + 538 64446174 + 538 61526567 + 539 .LASF8: + 540 00f3 756E7369 .ascii "unsigned int\000" + 540 676E6564 + 540 20696E74 + 540 00 + 541 .LASF7: + 542 0100 6C6F6E67 .ascii "long long unsigned int\000" + 542 206C6F6E + 542 6720756E + 542 7369676E + 542 65642069 + 543 .LASF17: + 544 0117 6D6F6465 .ascii "mode\000" + 544 00 + 545 .LASF6: + 546 011c 6C6F6E67 .ascii "long long int\000" + 546 206C6F6E + 546 6720696E + 546 7400 + 547 .LASF11: + 548 012a 63686172 .ascii "char\000" + 548 00 + 549 .LASF2: + 550 012f 73686F72 .ascii "short int\000" + 550 7420696E + 550 7400 + 551 .LASF12: + 552 0139 75696E74 .ascii "uint8\000" + 552 3800 + 553 .LASF20: + 554 013f 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" + 554 4320342E + 554 372E3320 + 554 32303133 + 554 30333132 + 555 0172 616E6368 .ascii "anch revision 196615]\000" + 555 20726576 + 555 6973696F + 555 6E203139 + 555 36363135 + 556 .LASF4: + 557 0188 6C6F6E67 .ascii "long int\000" + 557 20696E74 + 557 00 + 558 .LASF0: + 559 0191 7369676E .ascii "signed char\000" + 559 65642063 + 559 68617200 + 560 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_Dm.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_Dm.o index e66e6fc9de522a49212272e629866f2311474efa..0faf2149b36b0e88622eef82d857b28e3dec0563 100755 GIT binary patch delta 240 zcmbQDutZ^k0;9)7#dI!vMg|7PT?`BiWs@D*g*})U*(L%-m>4+%fnrQdtok4x6Z>)y zkA<}Z#A9Jk0r5CkWk5U*b_O8D%)*+PR|1mz43uNBocLCXNsDnZCu0heIOF7eMh(V$ zn`bcQGYN-V#RNMCdm071#1!YJm6RtIrA~guA~%_x<>6!w*4>+ru)bkpyfb+tM>!J@ z|70yrKgO8Jm7M;JEt5|I$s>~`xwIMQPIl!|X4IRU$)(OXfAT~id1dlWAo*nSLm;U# TnUhy_*F9(ttQa delta 237 zcmZ3YFhya40;9!5#q?A@Mg|7PP6h^sa3BL6Ffp<<0EL+tIRb%FOiZl*z!ZBKh+<(a z2g$Lpr+|1Itgpco`*|S6%)*+PR|1kd1mv-BOnfWF^pjySCu0iJGlt3ej2etn@b5i~~t diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_Dp.lst b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_Dp.lst index dd2f8c68..ac6a4364 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_Dp.lst +++ b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_Dp.lst @@ -1,4 +1,4 @@ -ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 1 +ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccENAnU1.s page 1 1 .syntax unified @@ -58,7 +58,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 1 29:.\Generated_Source\PSoC5/USBFS_Dp.c **** * Summary: 30:.\Generated_Source\PSoC5/USBFS_Dp.c **** * Assign a new value to the digital port's data output register. 31:.\Generated_Source\PSoC5/USBFS_Dp.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 2 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccENAnU1.s page 2 32:.\Generated_Source\PSoC5/USBFS_Dp.c **** * Parameters: @@ -118,7 +118,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 1 46:.\Generated_Source\PSoC5/USBFS_Dp.c **** /******************************************************************************* 47:.\Generated_Source\PSoC5/USBFS_Dp.c **** * Function Name: USBFS_Dp_SetDriveMode 48:.\Generated_Source\PSoC5/USBFS_Dp.c **** ******************************************************************************** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 3 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccENAnU1.s page 3 49:.\Generated_Source\PSoC5/USBFS_Dp.c **** * @@ -178,7 +178,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 1 73:.\Generated_Source\PSoC5/USBFS_Dp.c **** * 74:.\Generated_Source\PSoC5/USBFS_Dp.c **** * Parameters: 75:.\Generated_Source\PSoC5/USBFS_Dp.c **** * None - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 4 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccENAnU1.s page 4 76:.\Generated_Source\PSoC5/USBFS_Dp.c **** * @@ -238,7 +238,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 1 104:.\Generated_Source\PSoC5/USBFS_Dp.c **** uint8 USBFS_Dp_ReadDataReg(void) 105:.\Generated_Source\PSoC5/USBFS_Dp.c **** { 121 .loc 1 105 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 5 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccENAnU1.s page 5 122 .cfi_startproc @@ -298,7 +298,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 1 152 .loc 1 129 0 153 0000 024B ldr r3, .L14 154 0002 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 6 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccENAnU1.s page 6 130:.\Generated_Source\PSoC5/USBFS_Dp.c **** } @@ -322,10 +322,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 1 172 0006 00000000 .4byte .Ldebug_abbrev0 173 000a 04 .byte 0x4 174 000b 01 .uleb128 0x1 - 175 000c 10010000 .4byte .LASF21 + 175 000c 41010000 .4byte .LASF21 176 0010 01 .byte 0x1 - 177 0011 7C000000 .4byte .LASF22 - 178 0015 59010000 .4byte .LASF23 + 177 0011 AD000000 .4byte .LASF22 + 178 0015 62000000 .4byte .LASF23 179 0019 00000000 .4byte .Ldebug_ranges0+0 180 001d 00000000 .4byte 0 181 0021 00000000 .4byte 0 @@ -333,7 +333,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 1 183 0029 02 .uleb128 0x2 184 002a 01 .byte 0x1 185 002b 06 .byte 0x6 - 186 002c 98010000 .4byte .LASF0 + 186 002c A9010000 .4byte .LASF0 187 0030 02 .uleb128 0x2 188 0031 01 .byte 0x1 189 0032 08 .byte 0x8 @@ -341,15 +341,15 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 1 191 0037 02 .uleb128 0x2 192 0038 02 .byte 0x2 193 0039 05 .byte 0x5 - 194 003a 00010000 .4byte .LASF2 + 194 003a 31010000 .4byte .LASF2 195 003e 02 .uleb128 0x2 196 003f 02 .byte 0x2 197 0040 07 .byte 0x7 - 198 0041 62000000 .4byte .LASF3 + 198 0041 93000000 .4byte .LASF3 199 0045 02 .uleb128 0x2 200 0046 04 .byte 0x4 201 0047 05 .byte 0x5 - 202 0048 79010000 .4byte .LASF4 + 202 0048 8A010000 .4byte .LASF4 203 004c 02 .uleb128 0x2 204 004d 04 .byte 0x4 205 004e 07 .byte 0x7 @@ -357,14 +357,14 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 1 207 0053 02 .uleb128 0x2 208 0054 08 .byte 0x8 209 0055 05 .byte 0x5 - 210 0056 ED000000 .4byte .LASF6 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 7 + 210 0056 1E010000 .4byte .LASF6 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccENAnU1.s page 7 211 005a 02 .uleb128 0x2 212 005b 08 .byte 0x8 213 005c 07 .byte 0x7 - 214 005d BC000000 .4byte .LASF7 + 214 005d ED000000 .4byte .LASF7 215 0061 03 .uleb128 0x3 216 0062 04 .byte 0x4 217 0063 05 .byte 0x5 @@ -372,9 +372,9 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 1 219 0068 02 .uleb128 0x2 220 0069 04 .byte 0x4 221 006a 07 .byte 0x7 - 222 006b AF000000 .4byte .LASF8 + 222 006b E0000000 .4byte .LASF8 223 006f 04 .uleb128 0x4 - 224 0070 0A010000 .4byte .LASF12 + 224 0070 3B010000 .4byte .LASF12 225 0074 02 .byte 0x2 226 0075 5B .byte 0x5b 227 0076 30000000 .4byte 0x30 @@ -385,11 +385,11 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 1 232 0081 02 .uleb128 0x2 233 0082 08 .byte 0x8 234 0083 04 .byte 0x4 - 235 0084 75000000 .4byte .LASF10 + 235 0084 A6000000 .4byte .LASF10 236 0088 02 .uleb128 0x2 237 0089 01 .byte 0x1 238 008a 08 .byte 0x8 - 239 008b FB000000 .4byte .LASF11 + 239 008b 2C010000 .4byte .LASF11 240 008f 04 .uleb128 0x4 241 0090 4B000000 .4byte .LASF13 242 0094 02 .byte 0x2 @@ -399,7 +399,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 1 246 009b 6F000000 .4byte 0x6f 247 009f 06 .uleb128 0x6 248 00a0 01 .byte 0x1 - 249 00a1 A0000000 .4byte .LASF14 + 249 00a1 D1000000 .4byte .LASF14 250 00a5 01 .byte 0x1 251 00a6 27 .byte 0x27 252 00a7 01 .byte 0x1 @@ -418,7 +418,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 1 265 00c3 00000000 .4byte .LLST0 266 00c7 08 .uleb128 0x8 267 00c8 14000000 .4byte .LASF24 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 8 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccENAnU1.s page 8 268 00cc 01 .byte 0x1 @@ -428,7 +428,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 1 272 00d6 00 .byte 0 273 00d7 06 .uleb128 0x6 274 00d8 01 .byte 0x1 - 275 00d9 82010000 .4byte .LASF15 + 275 00d9 93010000 .4byte .LASF15 276 00dd 01 .byte 0x1 277 00de 3C .byte 0x3c 278 00df 01 .byte 0x1 @@ -440,7 +440,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 1 284 00eb 01 .byte 0x1 285 00ec 00010000 .4byte 0x100 286 00f0 07 .uleb128 0x7 - 287 00f1 E8000000 .4byte .LASF17 + 287 00f1 19010000 .4byte .LASF17 288 00f5 01 .byte 0x1 289 00f6 3C .byte 0x3c 290 00f7 6F000000 .4byte 0x6f @@ -461,7 +461,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 1 305 0118 01 .byte 0x1 306 0119 09 .uleb128 0x9 307 011a 01 .byte 0x1 - 308 011b D3000000 .4byte .LASF19 + 308 011b 04010000 .4byte .LASF19 309 011f 01 .byte 0x1 310 0120 68 .byte 0x68 311 0121 01 .byte 0x1 @@ -478,7 +478,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 1 322 0138 01 .byte 0x1 323 0139 7F .byte 0x7f 324 013a 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 9 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccENAnU1.s page 9 325 013b 6F000000 .4byte 0x6f @@ -538,7 +538,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 1 379 002c 16 .uleb128 0x16 380 002d 00 .byte 0 381 002e 03 .uleb128 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 10 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccENAnU1.s page 10 382 002f 0E .uleb128 0xe @@ -598,7 +598,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 1 436 0066 00 .byte 0 437 0067 00 .byte 0 438 0068 08 .uleb128 0x8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 11 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccENAnU1.s page 11 439 0069 34 .uleb128 0x34 @@ -658,7 +658,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 1 493 0019 00000000 .4byte 0 494 001d 00000000 .4byte 0 495 .LLST1: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 12 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccENAnU1.s page 12 496 0021 06000000 .4byte .LVL2 @@ -718,7 +718,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 1 550 001c 10000000 .4byte .LFE3 551 0020 00000000 .4byte .LFB4 552 0024 10000000 .4byte .LFE4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 13 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccENAnU1.s page 13 553 0028 00000000 .4byte 0 @@ -765,96 +765,97 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 1 573 69676E65 573 6420696E 573 7400 - 574 .LASF3: - 575 0062 73686F72 .ascii "short unsigned int\000" - 575 7420756E - 575 7369676E - 575 65642069 - 575 6E7400 - 576 .LASF10: - 577 0075 646F7562 .ascii "double\000" - 577 6C6500 - 578 .LASF22: - 579 007c 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\USBFS_Dp.c\000" - 579 6E657261 - 579 7465645F - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 14 + 574 .LASF23: + 575 0062 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" + 575 43534932 + 575 53445C73 + 575 6F667477 + 575 6172655C + 576 0091 6E00 .ascii "n\000" + 577 .LASF3: + 578 0093 73686F72 .ascii "short unsigned int\000" + 578 7420756E + 578 7369676E + 578 65642069 + 578 6E7400 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccENAnU1.s page 14 - 579 536F7572 - 579 63655C50 - 580 .LASF14: - 581 00a0 55534246 .ascii "USBFS_Dp_Write\000" - 581 535F4470 - 581 5F577269 - 581 746500 - 582 .LASF8: - 583 00af 756E7369 .ascii "unsigned int\000" - 583 676E6564 - 583 20696E74 - 583 00 - 584 .LASF7: - 585 00bc 6C6F6E67 .ascii "long long unsigned int\000" - 585 206C6F6E - 585 6720756E - 585 7369676E - 585 65642069 - 586 .LASF19: - 587 00d3 55534246 .ascii "USBFS_Dp_ReadDataReg\000" - 587 535F4470 - 587 5F526561 - 587 64446174 - 587 61526567 - 588 .LASF17: - 589 00e8 6D6F6465 .ascii "mode\000" - 589 00 - 590 .LASF6: - 591 00ed 6C6F6E67 .ascii "long long int\000" - 591 206C6F6E - 591 6720696E - 591 7400 - 592 .LASF11: - 593 00fb 63686172 .ascii "char\000" - 593 00 - 594 .LASF2: - 595 0100 73686F72 .ascii "short int\000" - 595 7420696E - 595 7400 - 596 .LASF12: - 597 010a 75696E74 .ascii "uint8\000" - 597 3800 - 598 .LASF21: - 599 0110 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 599 4320342E - 599 372E3320 - 599 32303133 - 599 30333132 - 600 0143 616E6368 .ascii "anch revision 196615]\000" - 600 20726576 - 600 6973696F - 600 6E203139 - 600 36363135 - 601 .LASF23: - 602 0159 573A5C53 .ascii "W:\\SCSI2SD\\USB_Bootloader.cydsn\000" - 602 43534932 - 602 53445C55 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAFwykg.s page 15 + 579 .LASF10: + 580 00a6 646F7562 .ascii "double\000" + 580 6C6500 + 581 .LASF22: + 582 00ad 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\USBFS_Dp.c\000" + 582 6E657261 + 582 7465645F + 582 536F7572 + 582 63655C50 + 583 .LASF14: + 584 00d1 55534246 .ascii "USBFS_Dp_Write\000" + 584 535F4470 + 584 5F577269 + 584 746500 + 585 .LASF8: + 586 00e0 756E7369 .ascii "unsigned int\000" + 586 676E6564 + 586 20696E74 + 586 00 + 587 .LASF7: + 588 00ed 6C6F6E67 .ascii "long long unsigned int\000" + 588 206C6F6E + 588 6720756E + 588 7369676E + 588 65642069 + 589 .LASF19: + 590 0104 55534246 .ascii "USBFS_Dp_ReadDataReg\000" + 590 535F4470 + 590 5F526561 + 590 64446174 + 590 61526567 + 591 .LASF17: + 592 0119 6D6F6465 .ascii "mode\000" + 592 00 + 593 .LASF6: + 594 011e 6C6F6E67 .ascii "long long int\000" + 594 206C6F6E + 594 6720696E + 594 7400 + 595 .LASF11: + 596 012c 63686172 .ascii "char\000" + 596 00 + 597 .LASF2: + 598 0131 73686F72 .ascii "short int\000" + 598 7420696E + 598 7400 + 599 .LASF12: + 600 013b 75696E74 .ascii "uint8\000" + 600 3800 + 601 .LASF21: + 602 0141 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" + 602 4320342E + 602 372E3320 + 602 32303133 + 602 30333132 + 603 0174 616E6368 .ascii "anch revision 196615]\000" + 603 20726576 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccENAnU1.s page 15 - 602 53425F42 - 602 6F6F746C - 603 .LASF4: - 604 0179 6C6F6E67 .ascii "long int\000" - 604 20696E74 - 604 00 - 605 .LASF15: - 606 0182 55534246 .ascii "USBFS_Dp_SetDriveMode\000" - 606 535F4470 - 606 5F536574 - 606 44726976 - 606 654D6F64 - 607 .LASF0: - 608 0198 7369676E .ascii "signed char\000" - 608 65642063 - 608 68617200 - 609 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br + 603 6973696F + 603 6E203139 + 603 36363135 + 604 .LASF4: + 605 018a 6C6F6E67 .ascii "long int\000" + 605 20696E74 + 605 00 + 606 .LASF15: + 607 0193 55534246 .ascii "USBFS_Dp_SetDriveMode\000" + 607 535F4470 + 607 5F536574 + 607 44726976 + 607 654D6F64 + 608 .LASF0: + 609 01a9 7369676E .ascii "signed char\000" + 609 65642063 + 609 68617200 + 610 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_Dp.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_Dp.o index e9f736c9556a10c246a4733347f3b878680a3cb8..00aec8596344368822d1b7262cd1932c559320e6 100755 GIT binary patch delta 318 zcmWlQJxc>Y5Qg{N+r8af6u~snA{tXf(83cdKOn(?5yc2sh$M|d1RDb;Cu#@})(<^8tf`zjT^UOT+?*2`+bL~ldbh1}L5klZa2(eECle&=byL^$b zD}0kuht8xSXG&i?Q)b(l)fs2je6o2;A0D+__Rgl3TvDCmRVp>%hE-2)z|L}{Hr)R8 zz|;+fk3JK5PyyjM@e3?7gh+GCa{(@4#y~fimI`qX_cFD!Sc_Jp_4%k&Yc>vAr+deB zTGJWYQa@DJZytY*7yObZ#R#1xPEe-rLKh{wWO z3F5J^2Y`4StZ%^-`yL?0%)*+PR|1k-59G0Mfz(ACfaFvWwccyTw$%!m-lgn7oZ}wnwVP<;6H@T0qjL~E=E0;fG%j8fXxn=TFAjvZME0;Fo zlF5qP%8U~xyK<{DGEUCrR%bO~V_-;_ypTh9@)}@J=uF-Vl$kR5DUh_7%*&(BTEWM_ PP&7G^M|^Vtj{_?JSqM74 diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_audio.lst b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_audio.lst index d968ae3c..8c0639fb 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_audio.lst +++ b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_audio.lst @@ -1,4 +1,4 @@ -ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccRSBt5d.s page 1 +ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNAvcMf.s page 1 1 .syntax unified @@ -58,7 +58,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccRSBt5d.s page 1 55 0047 02 .uleb128 0x2 56 0048 08 .byte 0x8 57 0049 05 .byte 0x5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccRSBt5d.s page 2 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNAvcMf.s page 2 58 004a 00000000 .4byte .LASF6 @@ -89,7 +89,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccRSBt5d.s page 1 83 0078 02 .uleb128 0x2 84 0079 04 .byte 0x4 85 007a 07 .byte 0x7 - 86 007b 26010000 .4byte .LASF12 + 86 007b 37010000 .4byte .LASF12 87 007f 00 .byte 0 88 .section .debug_abbrev,"",%progbits 89 .Ldebug_abbrev0: @@ -118,7 +118,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccRSBt5d.s page 1 112 0016 03 .uleb128 0x3 113 0017 0E .uleb128 0xe 114 0018 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccRSBt5d.s page 3 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNAvcMf.s page 3 115 0019 00 .byte 0 @@ -178,7 +178,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccRSBt5d.s page 1 149 69676E65 149 6420696E 149 7400 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccRSBt5d.s page 4 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNAvcMf.s page 4 150 .LASF7: @@ -226,13 +226,14 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccRSBt5d.s page 1 169 7420696E 169 7400 170 .LASF15: - 171 0106 573A5C53 .ascii "W:\\SCSI2SD\\USB_Bootloader.cydsn\000" + 171 0106 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" 171 43534932 - 171 53445C55 - 171 53425F42 - 171 6F6F746C - 172 .LASF12: - 173 0126 73697A65 .ascii "sizetype\000" - 173 74797065 - 173 00 - 174 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br + 171 53445C73 + 171 6F667477 + 171 6172655C + 172 0135 6E00 .ascii "n\000" + 173 .LASF12: + 174 0137 73697A65 .ascii "sizetype\000" + 174 74797065 + 174 00 + 175 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_audio.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_audio.o index 3f69ba09738b204fd0ee12361fe8a168fc84432c..a597323319500c5613238c8992cd3b847a7a6f62 100755 GIT binary patch delta 85 zcmcb?_kwSN0%OBO#Xd&!jT;IWIg0bsO3D+9Qa6h;H84(|!MuU-!emdDa>j(o2U&s{ p9VUyiDl_^|wq#XjJTN&CNPeE&$*Ru8z&3dks~Y2h%{N)=83F8t8|nZ6 delta 76 zcmV-S0JHz-4%iNmAOUcZA&vniv9NFfvoQj90h6Z#u>ru7Sp;_hP?OOFQvolNB?Th^ iK9flWCjqaMaRny<;**&LCj#&Vlfnfi0kE^_1%CnJLK$)Z diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_boot.lst b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_boot.lst index 5ae2e353..ea4473fa 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_boot.lst +++ b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_boot.lst @@ -1,4 +1,4 @@ -ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 +ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 1 1 .syntax unified @@ -58,7 +58,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 29:.\Generated_Source\PSoC5/USBFS_boot.c **** 30:.\Generated_Source\PSoC5/USBFS_boot.c **** #define USBFS_BTLDR_OUT_EP (0x01u) 31:.\Generated_Source\PSoC5/USBFS_boot.c **** #define USBFS_BTLDR_IN_EP (0x02u) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 2 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 2 32:.\Generated_Source\PSoC5/USBFS_boot.c **** @@ -118,7 +118,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 45 .LVL0: 68:.\Generated_Source\PSoC5/USBFS_boot.c **** 69:.\Generated_Source\PSoC5/USBFS_boot.c **** /* USB component started, the correct enumeration will be checked in first Read operation */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 3 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 3 70:.\Generated_Source\PSoC5/USBFS_boot.c **** USBFS_started = 1u; @@ -178,7 +178,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 76 .LFE1: 77 .size USBFS_CyBtldrCommStop, .-USBFS_CyBtldrCommStop 78 .section .text.USBFS_CyBtldrCommReset,"ax",%progbits - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 4 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 4 79 .align 1 @@ -238,7 +238,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 117:.\Generated_Source\PSoC5/USBFS_boot.c **** 118:.\Generated_Source\PSoC5/USBFS_boot.c **** /******************************************************************************* 119:.\Generated_Source\PSoC5/USBFS_boot.c **** * Function Name: USBFS_CyBtldrCommWrite. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 5 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 5 120:.\Generated_Source\PSoC5/USBFS_boot.c **** ******************************************************************************** @@ -298,7 +298,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 132 .LVL5: 133 000c 4022 movs r2, #64 134 .LVL6: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 6 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 6 143:.\Generated_Source\PSoC5/USBFS_boot.c **** { @@ -358,7 +358,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 158:.\Generated_Source\PSoC5/USBFS_boot.c **** } 159:.\Generated_Source\PSoC5/USBFS_boot.c **** 160:.\Generated_Source\PSoC5/USBFS_boot.c **** if (USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 7 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 7 176 .loc 1 160 0 @@ -418,7 +418,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 181:.\Generated_Source\PSoC5/USBFS_boot.c **** * host device. 182:.\Generated_Source\PSoC5/USBFS_boot.c **** * 183:.\Generated_Source\PSoC5/USBFS_boot.c **** * Parameters: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 8 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 8 184:.\Generated_Source\PSoC5/USBFS_boot.c **** * pData: A pointer to the area to store the block of data received @@ -478,7 +478,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 211:.\Generated_Source\PSoC5/USBFS_boot.c **** 212:.\Generated_Source\PSoC5/USBFS_boot.c **** /* Wait on enumeration in first time */ 213:.\Generated_Source\PSoC5/USBFS_boot.c **** if(USBFS_started) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 9 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 9 235 .loc 1 213 0 @@ -538,7 +538,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 224:.\Generated_Source\PSoC5/USBFS_boot.c **** USBFS_CyBtldrCommReset(); 277 .loc 1 224 0 278 0040 FFF7FEFF bl USBFS_CyBtldrCommReset - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 10 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 10 279 .LVL29: @@ -598,7 +598,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 315 .LVL35: 239:.\Generated_Source\PSoC5/USBFS_boot.c **** while((USBFS_GetEPState(USBFS_BTLDR_OUT_EP) != USBFS_OUT_BUFFER_FULL) && \ 316 .loc 1 239 0 discriminator 2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 11 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 11 317 006c A142 cmp r1, r4 @@ -658,7 +658,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 251:.\Generated_Source\PSoC5/USBFS_boot.c **** else 252:.\Generated_Source\PSoC5/USBFS_boot.c **** { 253:.\Generated_Source\PSoC5/USBFS_boot.c **** *count = 0u; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 12 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 12 358 .loc 1 253 0 @@ -705,10 +705,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 395 0006 00000000 .4byte .Ldebug_abbrev0 396 000a 04 .byte 0x4 397 000b 01 .uleb128 0x1 - 398 000c 86010000 .4byte .LASF37 + 398 000c B7010000 .4byte .LASF37 399 0010 01 .byte 0x1 - 400 0011 55020000 .4byte .LASF38 - 401 0015 CF010000 .4byte .LASF39 + 400 0011 66020000 .4byte .LASF38 + 401 0015 91000000 .4byte .LASF39 402 0019 00000000 .4byte .Ldebug_ranges0+0 403 001d 00000000 .4byte 0 404 0021 00000000 .4byte 0 @@ -716,18 +716,18 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 406 0029 02 .uleb128 0x2 407 002a 01 .byte 0x1 408 002b 06 .byte 0x6 - 409 002c 1F020000 .4byte .LASF0 + 409 002c 30020000 .4byte .LASF0 410 0030 02 .uleb128 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 13 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 13 411 0031 01 .byte 0x1 412 0032 08 .byte 0x8 - 413 0033 97000000 .4byte .LASF1 + 413 0033 C8000000 .4byte .LASF1 414 0037 02 .uleb128 0x2 415 0038 02 .byte 0x2 416 0039 05 .byte 0x5 - 417 003a 7C010000 .4byte .LASF2 + 417 003a AD010000 .4byte .LASF2 418 003e 02 .uleb128 0x2 419 003f 02 .byte 0x2 420 0040 07 .byte 0x7 @@ -735,7 +735,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 422 0045 02 .uleb128 0x2 423 0046 04 .byte 0x4 424 0047 05 .byte 0x5 - 425 0048 00020000 .4byte .LASF4 + 425 0048 11020000 .4byte .LASF4 426 004c 02 .uleb128 0x2 427 004d 04 .byte 0x4 428 004e 07 .byte 0x7 @@ -743,11 +743,11 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 430 0053 02 .uleb128 0x2 431 0054 08 .byte 0x8 432 0055 05 .byte 0x5 - 433 0056 5A010000 .4byte .LASF6 + 433 0056 8B010000 .4byte .LASF6 434 005a 02 .uleb128 0x2 435 005b 08 .byte 0x8 436 005c 07 .byte 0x7 - 437 005d 05010000 .4byte .LASF7 + 437 005d 36010000 .4byte .LASF7 438 0061 03 .uleb128 0x3 439 0062 04 .byte 0x4 440 0063 05 .byte 0x5 @@ -755,19 +755,19 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 442 0068 02 .uleb128 0x2 443 0069 04 .byte 0x4 444 006a 07 .byte 0x7 - 445 006b F8000000 .4byte .LASF8 + 445 006b 29010000 .4byte .LASF8 446 006f 04 .uleb128 0x4 - 447 0070 91000000 .4byte .LASF9 + 447 0070 C2000000 .4byte .LASF9 448 0074 02 .byte 0x2 449 0075 5B .byte 0x5b 450 0076 30000000 .4byte 0x30 451 007a 04 .uleb128 0x4 - 452 007b D3000000 .4byte .LASF10 + 452 007b 04010000 .4byte .LASF10 453 007f 02 .byte 0x2 454 0080 5C .byte 0x5c 455 0081 3E000000 .4byte 0x3e 456 0085 04 .uleb128 0x4 - 457 0086 DA000000 .4byte .LASF11 + 457 0086 0B010000 .4byte .LASF11 458 008a 02 .byte 0x2 459 008b 5D .byte 0x5d 460 008c 4C000000 .4byte 0x4c @@ -778,14 +778,14 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 465 0097 02 .uleb128 0x2 466 0098 08 .byte 0x8 467 0099 04 .byte 0x4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 14 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 14 - 468 009a A5000000 .4byte .LASF13 + 468 009a D6000000 .4byte .LASF13 469 009e 02 .uleb128 0x2 470 009f 01 .byte 0x1 471 00a0 08 .byte 0x8 - 472 00a1 68010000 .4byte .LASF14 + 472 00a1 99010000 .4byte .LASF14 473 00a5 04 .uleb128 0x4 474 00a6 00000000 .4byte .LASF15 475 00aa 02 .byte 0x2 @@ -794,7 +794,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 478 00b0 02 .uleb128 0x2 479 00b1 04 .byte 0x4 480 00b2 07 .byte 0x7 - 481 00b3 51010000 .4byte .LASF16 + 481 00b3 82010000 .4byte .LASF16 482 00b7 05 .uleb128 0x5 483 00b8 01 .byte 0x1 484 00b9 52000000 .4byte .LASF17 @@ -823,7 +823,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 507 00e5 00 .byte 0 508 00e6 08 .uleb128 0x8 509 00e7 01 .byte 0x1 - 510 00e8 09020000 .4byte .LASF18 + 510 00e8 1A020000 .4byte .LASF18 511 00ec 01 .byte 0x1 512 00ed 59 .byte 0x59 513 00ee 01 .byte 0x1 @@ -838,7 +838,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 522 0100 04000000 .4byte .LVL1 523 0104 01 .byte 0x1 524 0105 61030000 .4byte 0x361 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 15 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 15 525 0109 00 .byte 0 @@ -868,7 +868,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 549 0133 00 .byte 0 550 0134 0B .uleb128 0xb 551 0135 01 .byte 0x1 - 552 0136 BC000000 .4byte .LASF26 + 552 0136 ED000000 .4byte .LASF26 553 013a 01 .byte 0x1 554 013b 8D .byte 0x8d 555 013c 01 .byte 0x1 @@ -897,8 +897,8 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 578 0177 07020000 .4byte 0x207 579 017b 8D000000 .4byte .LLST4 580 017f 0C .uleb128 0xc - 581 0180 44010000 .4byte .LASF23 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 16 + 581 0180 75010000 .4byte .LASF23 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 16 582 0184 01 .byte 0x1 @@ -906,7 +906,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 584 0186 6F000000 .4byte 0x6f 585 018a AB000000 .4byte .LLST5 586 018e 0D .uleb128 0xd - 587 018f 4C010000 .4byte .LASF24 + 587 018f 7D010000 .4byte .LASF24 588 0193 01 .byte 0x1 589 0194 90 .byte 0x90 590 0195 7A000000 .4byte 0x7a @@ -958,7 +958,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 636 01ed 50 .byte 0x50 637 01ee 01 .byte 0x1 638 01ef 31 .byte 0x31 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 17 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 17 639 01f0 00 .byte 0 @@ -980,7 +980,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 655 0209 7A000000 .4byte 0x7a 656 020d 0B .uleb128 0xb 657 020e 01 .byte 0x1 - 658 020f 2E010000 .4byte .LASF27 + 658 020f 5F010000 .4byte .LASF27 659 0213 01 .byte 0x1 660 0214 C7 .byte 0xc7 661 0215 01 .byte 0x1 @@ -1009,7 +1009,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 684 0250 07020000 .4byte 0x207 685 0254 FC010000 .4byte .LLST11 686 0258 0C .uleb128 0xc - 687 0259 44010000 .4byte .LASF23 + 687 0259 75010000 .4byte .LASF23 688 025d 01 .byte 0x1 689 025e C7 .byte 0xc7 690 025f 6F000000 .4byte 0x6f @@ -1018,13 +1018,13 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 693 0268 09000000 .4byte .LASF25 694 026c 01 .byte 0x1 695 026d CA .byte 0xca - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 18 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 18 696 026e A5000000 .4byte 0xa5 697 0272 3B020000 .4byte .LLST13 698 0276 0D .uleb128 0xd - 699 0277 4C010000 .4byte .LASF24 + 699 0277 7D010000 .4byte .LASF24 700 027b 01 .byte 0x1 701 027c CB .byte 0xcb 702 027d 7A000000 .4byte 0x7a @@ -1078,7 +1078,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 750 02f8 A8030000 .4byte 0x3a8 751 02fc 06 .uleb128 0x6 752 02fd 9A000000 .4byte .LVL41 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 19 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 19 753 0301 F0030000 .4byte 0x3f0 @@ -1115,7 +1115,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 784 0324 00 .byte 0 785 0325 00 .byte 0 786 0326 11 .uleb128 0x11 - 787 0327 39020000 .4byte .LASF28 + 787 0327 4A020000 .4byte .LASF28 788 032b 01 .byte 0x1 789 032c 26 .byte 0x26 790 032d 7A000000 .4byte 0x7a @@ -1123,7 +1123,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 792 0332 03 .byte 0x3 793 0333 02000000 .4byte USBFS_universalTime 794 0337 11 .uleb128 0x11 - 795 0338 2B020000 .4byte .LASF29 + 795 0338 3C020000 .4byte .LASF29 796 033c 01 .byte 0x1 797 033d 27 .byte 0x27 798 033e 6F000000 .4byte 0x6f @@ -1138,7 +1138,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 807 0350 01 .byte 0x1 808 0351 01 .byte 0x1 809 0352 61030000 .4byte 0x361 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 20 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 20 810 0356 13 .uleb128 0x13 @@ -1155,7 +1155,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 821 036a 01 .byte 0x1 822 036b 12 .uleb128 0x12 823 036c 01 .byte 0x1 - 824 036d 1C010000 .4byte .LASF31 + 824 036d 4D010000 .4byte .LASF31 825 0371 03 .byte 0x3 826 0372 CE .byte 0xce 827 0373 01 .byte 0x1 @@ -1166,7 +1166,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 832 037e 00 .byte 0 833 037f 12 .uleb128 0x12 834 0380 01 .byte 0x1 - 835 0381 6D010000 .4byte .LASF32 + 835 0381 9E010000 .4byte .LASF32 836 0385 03 .byte 0x3 837 0386 CA .byte 0xca 838 0387 01 .byte 0x1 @@ -1186,7 +1186,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 852 03a4 6F000000 .4byte 0x6f 853 03a8 16 .uleb128 0x16 854 03a9 01 .byte 0x1 - 855 03aa EF010000 .4byte .LASF41 + 855 03aa 00020000 .4byte .LASF41 856 03ae 03 .byte 0x3 857 03af C8 .byte 0xc8 858 03b0 01 .byte 0x1 @@ -1198,10 +1198,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 864 03bf 00 .byte 0 865 03c0 12 .uleb128 0x12 866 03c1 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 21 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 21 - 867 03c2 4D020000 .4byte .LASF33 + 867 03c2 5E020000 .4byte .LASF33 868 03c6 04 .byte 0x4 869 03c7 77 .byte 0x77 870 03c8 01 .byte 0x1 @@ -1212,7 +1212,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 875 03d3 00 .byte 0 876 03d4 17 .uleb128 0x17 877 03d5 01 .byte 0x1 - 878 03d6 E1000000 .4byte .LASF34 + 878 03d6 12010000 .4byte .LASF34 879 03da 03 .byte 0x3 880 03db C4 .byte 0xc4 881 03dc 01 .byte 0x1 @@ -1220,7 +1220,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 883 03e1 01 .byte 0x1 884 03e2 17 .uleb128 0x17 885 03e3 01 .byte 0x1 - 886 03e4 7B020000 .4byte .LASF35 + 886 03e4 8C020000 .4byte .LASF35 887 03e8 03 .byte 0x3 888 03e9 C5 .byte 0xc5 889 03ea 01 .byte 0x1 @@ -1228,7 +1228,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 891 03ef 01 .byte 0x1 892 03f0 18 .uleb128 0x18 893 03f1 01 .byte 0x1 - 894 03f2 AC000000 .4byte .LASF36 + 894 03f2 DD000000 .4byte .LASF36 895 03f6 03 .byte 0x3 896 03f7 CC .byte 0xcc 897 03f8 01 .byte 0x1 @@ -1258,7 +1258,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 921 000b 55 .uleb128 0x55 922 000c 06 .uleb128 0x6 923 000d 11 .uleb128 0x11 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 22 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 22 924 000e 01 .uleb128 0x1 @@ -1318,7 +1318,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 978 0044 0C .uleb128 0xc 979 0045 11 .uleb128 0x11 980 0046 01 .uleb128 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 23 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 23 981 0047 12 .uleb128 0x12 @@ -1378,7 +1378,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 1035 0084 898201 .uleb128 0x4109 1036 0087 00 .byte 0 1037 0088 11 .uleb128 0x11 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 24 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 24 1038 0089 01 .uleb128 0x1 @@ -1438,7 +1438,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 1092 00c4 49 .uleb128 0x49 1093 00c5 13 .uleb128 0x13 1094 00c6 02 .uleb128 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 25 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 25 1095 00c7 06 .uleb128 0x6 @@ -1498,7 +1498,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 1149 0101 3B .uleb128 0x3b 1150 0102 0B .uleb128 0xb 1151 0103 49 .uleb128 0x49 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 26 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 26 1152 0104 13 .uleb128 0x13 @@ -1558,7 +1558,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 1206 013a 00 .byte 0 1207 013b 16 .uleb128 0x16 1208 013c 2E .uleb128 0x2e - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 27 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 27 1209 013d 01 .byte 0x1 @@ -1618,7 +1618,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 1263 0173 0C .uleb128 0xc 1264 0174 00 .byte 0 1265 0175 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 28 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 28 1266 0176 00 .byte 0 @@ -1678,7 +1678,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 1320 007f 0400 .2byte 0x4 1321 0081 F3 .byte 0xf3 1322 0082 01 .uleb128 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 29 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 29 1323 0083 51 .byte 0x51 @@ -1738,7 +1738,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 1377 010c 50 .byte 0x50 1378 010d 00000000 .4byte 0 1379 0111 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 30 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 30 1380 .LLST8: @@ -1798,7 +1798,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 1434 018e 28 .byte 0x28 1435 018f 0100 .2byte 0x1 1436 0191 16 .byte 0x16 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 31 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 31 1437 0192 13 .byte 0x13 @@ -1858,7 +1858,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 1491 01e4 1A .byte 0x1a 1492 01e5 08 .byte 0x8 1493 01e6 40 .byte 0x40 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 32 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 32 1494 01e7 16 .byte 0x16 @@ -1918,7 +1918,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 1548 0262 00000000 .4byte 0 1549 .LLST14: 1550 0266 14000000 .4byte .LVL21 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 33 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 33 1551 026a 18000000 .4byte .LVL22 @@ -1978,7 +1978,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 1605 003c 00000000 .4byte 0 1606 .section .debug_ranges,"",%progbits 1607 .Ldebug_ranges0: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 34 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 34 1608 0000 00000000 .4byte .LFB0 @@ -2038,7 +2038,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 1639 .LASF12: 1640 0069 666C6F61 .ascii "float\000" 1640 7400 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 35 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 35 1641 .LASF40: @@ -2054,157 +2054,158 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 1 1646 69676E65 1646 6420696E 1646 7400 - 1647 .LASF9: - 1648 0091 75696E74 .ascii "uint8\000" - 1648 3800 - 1649 .LASF1: - 1650 0097 756E7369 .ascii "unsigned char\000" - 1650 676E6564 - 1650 20636861 - 1650 7200 - 1651 .LASF13: - 1652 00a5 646F7562 .ascii "double\000" - 1652 6C6500 - 1653 .LASF36: - 1654 00ac 55534246 .ascii "USBFS_ReadOutEP\000" - 1654 535F5265 - 1654 61644F75 - 1654 74455000 - 1655 .LASF26: - 1656 00bc 55534246 .ascii "USBFS_CyBtldrCommWrite\000" - 1656 535F4379 - 1656 42746C64 - 1656 72436F6D - 1656 6D577269 - 1657 .LASF10: - 1658 00d3 75696E74 .ascii "uint16\000" - 1658 313600 - 1659 .LASF11: - 1660 00da 75696E74 .ascii "uint32\000" - 1660 333200 - 1661 .LASF34: - 1662 00e1 55534246 .ascii "USBFS_GetConfiguration\000" - 1662 535F4765 - 1662 74436F6E - 1662 66696775 - 1662 72617469 - 1663 .LASF8: - 1664 00f8 756E7369 .ascii "unsigned int\000" - 1664 676E6564 - 1664 20696E74 - 1664 00 - 1665 .LASF7: - 1666 0105 6C6F6E67 .ascii "long long unsigned int\000" - 1666 206C6F6E - 1666 6720756E - 1666 7369676E - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 36 - - - 1666 65642069 - 1667 .LASF31: - 1668 011c 55534246 .ascii "USBFS_EnableOutEP\000" - 1668 535F456E - 1668 61626C65 - 1668 4F757445 - 1668 5000 - 1669 .LASF27: - 1670 012e 55534246 .ascii "USBFS_CyBtldrCommRead\000" - 1670 535F4379 - 1670 42746C64 - 1670 72436F6D - 1670 6D526561 - 1671 .LASF23: - 1672 0144 74696D65 .ascii "timeOut\000" - 1672 4F757400 - 1673 .LASF24: - 1674 014c 74696D65 .ascii "time\000" - 1674 00 - 1675 .LASF16: - 1676 0151 73697A65 .ascii "sizetype\000" - 1676 74797065 - 1676 00 - 1677 .LASF6: - 1678 015a 6C6F6E67 .ascii "long long int\000" - 1678 206C6F6E - 1678 6720696E - 1678 7400 - 1679 .LASF14: - 1680 0168 63686172 .ascii "char\000" - 1680 00 - 1681 .LASF32: - 1682 016d 55534246 .ascii "USBFS_LoadInEP\000" - 1682 535F4C6F - 1682 6164496E - 1682 455000 - 1683 .LASF2: - 1684 017c 73686F72 .ascii "short int\000" - 1684 7420696E - 1684 7400 - 1685 .LASF37: - 1686 0186 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 1686 4320342E - 1686 372E3320 - 1686 32303133 - 1686 30333132 - 1687 01b9 616E6368 .ascii "anch revision 196615]\000" - 1687 20726576 - 1687 6973696F - 1687 6E203139 - 1687 36363135 - 1688 .LASF39: - 1689 01cf 573A5C53 .ascii "W:\\SCSI2SD\\USB_Bootloader.cydsn\000" - 1689 43534932 - 1689 53445C55 - 1689 53425F42 - 1689 6F6F746C - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccghD6Qq.s page 37 - - - 1690 .LASF41: - 1691 01ef 55534246 .ascii "USBFS_GetEPState\000" - 1691 535F4765 - 1691 74455053 - 1691 74617465 - 1691 00 - 1692 .LASF4: - 1693 0200 6C6F6E67 .ascii "long int\000" - 1693 20696E74 - 1693 00 - 1694 .LASF18: - 1695 0209 55534246 .ascii "USBFS_CyBtldrCommStop\000" - 1695 535F4379 - 1695 42746C64 - 1695 72436F6D - 1695 6D53746F - 1696 .LASF0: - 1697 021f 7369676E .ascii "signed char\000" - 1697 65642063 - 1697 68617200 - 1698 .LASF29: - 1699 022b 55534246 .ascii "USBFS_started\000" - 1699 535F7374 - 1699 61727465 - 1699 6400 - 1700 .LASF28: - 1701 0239 55534246 .ascii "USBFS_universalTime\000" - 1701 535F756E - 1701 69766572 - 1701 73616C54 - 1701 696D6500 - 1702 .LASF33: - 1703 024d 43794465 .ascii "CyDelay\000" - 1703 6C617900 - 1704 .LASF38: - 1705 0255 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\USBFS_boot.c\000" - 1705 6E657261 - 1705 7465645F - 1705 536F7572 - 1705 63655C50 - 1706 .LASF35: - 1707 027b 55534246 .ascii "USBFS_IsConfigurationChanged\000" - 1707 535F4973 - 1707 436F6E66 - 1707 69677572 - 1707 6174696F - 1708 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br + 1647 .LASF39: + 1648 0091 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" + 1648 43534932 + 1648 53445C73 + 1648 6F667477 + 1648 6172655C + 1649 00c0 6E00 .ascii "n\000" + 1650 .LASF9: + 1651 00c2 75696E74 .ascii "uint8\000" + 1651 3800 + 1652 .LASF1: + 1653 00c8 756E7369 .ascii "unsigned char\000" + 1653 676E6564 + 1653 20636861 + 1653 7200 + 1654 .LASF13: + 1655 00d6 646F7562 .ascii "double\000" + 1655 6C6500 + 1656 .LASF36: + 1657 00dd 55534246 .ascii "USBFS_ReadOutEP\000" + 1657 535F5265 + 1657 61644F75 + 1657 74455000 + 1658 .LASF26: + 1659 00ed 55534246 .ascii "USBFS_CyBtldrCommWrite\000" + 1659 535F4379 + 1659 42746C64 + 1659 72436F6D + 1659 6D577269 + 1660 .LASF10: + 1661 0104 75696E74 .ascii "uint16\000" + 1661 313600 + 1662 .LASF11: + 1663 010b 75696E74 .ascii "uint32\000" + 1663 333200 + 1664 .LASF34: + 1665 0112 55534246 .ascii "USBFS_GetConfiguration\000" + 1665 535F4765 + 1665 74436F6E + 1665 66696775 + 1665 72617469 + 1666 .LASF8: + 1667 0129 756E7369 .ascii "unsigned int\000" + 1667 676E6564 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 36 + + + 1667 20696E74 + 1667 00 + 1668 .LASF7: + 1669 0136 6C6F6E67 .ascii "long long unsigned int\000" + 1669 206C6F6E + 1669 6720756E + 1669 7369676E + 1669 65642069 + 1670 .LASF31: + 1671 014d 55534246 .ascii "USBFS_EnableOutEP\000" + 1671 535F456E + 1671 61626C65 + 1671 4F757445 + 1671 5000 + 1672 .LASF27: + 1673 015f 55534246 .ascii "USBFS_CyBtldrCommRead\000" + 1673 535F4379 + 1673 42746C64 + 1673 72436F6D + 1673 6D526561 + 1674 .LASF23: + 1675 0175 74696D65 .ascii "timeOut\000" + 1675 4F757400 + 1676 .LASF24: + 1677 017d 74696D65 .ascii "time\000" + 1677 00 + 1678 .LASF16: + 1679 0182 73697A65 .ascii "sizetype\000" + 1679 74797065 + 1679 00 + 1680 .LASF6: + 1681 018b 6C6F6E67 .ascii "long long int\000" + 1681 206C6F6E + 1681 6720696E + 1681 7400 + 1682 .LASF14: + 1683 0199 63686172 .ascii "char\000" + 1683 00 + 1684 .LASF32: + 1685 019e 55534246 .ascii "USBFS_LoadInEP\000" + 1685 535F4C6F + 1685 6164496E + 1685 455000 + 1686 .LASF2: + 1687 01ad 73686F72 .ascii "short int\000" + 1687 7420696E + 1687 7400 + 1688 .LASF37: + 1689 01b7 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" + 1689 4320342E + 1689 372E3320 + 1689 32303133 + 1689 30333132 + 1690 01ea 616E6368 .ascii "anch revision 196615]\000" + 1690 20726576 + 1690 6973696F + 1690 6E203139 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 37 + + + 1690 36363135 + 1691 .LASF41: + 1692 0200 55534246 .ascii "USBFS_GetEPState\000" + 1692 535F4765 + 1692 74455053 + 1692 74617465 + 1692 00 + 1693 .LASF4: + 1694 0211 6C6F6E67 .ascii "long int\000" + 1694 20696E74 + 1694 00 + 1695 .LASF18: + 1696 021a 55534246 .ascii "USBFS_CyBtldrCommStop\000" + 1696 535F4379 + 1696 42746C64 + 1696 72436F6D + 1696 6D53746F + 1697 .LASF0: + 1698 0230 7369676E .ascii "signed char\000" + 1698 65642063 + 1698 68617200 + 1699 .LASF29: + 1700 023c 55534246 .ascii "USBFS_started\000" + 1700 535F7374 + 1700 61727465 + 1700 6400 + 1701 .LASF28: + 1702 024a 55534246 .ascii "USBFS_universalTime\000" + 1702 535F756E + 1702 69766572 + 1702 73616C54 + 1702 696D6500 + 1703 .LASF33: + 1704 025e 43794465 .ascii "CyDelay\000" + 1704 6C617900 + 1705 .LASF38: + 1706 0266 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\USBFS_boot.c\000" + 1706 6E657261 + 1706 7465645F + 1706 536F7572 + 1706 63655C50 + 1707 .LASF35: + 1708 028c 55534246 .ascii "USBFS_IsConfigurationChanged\000" + 1708 535F4973 + 1708 436F6E66 + 1708 69677572 + 1708 6174696F + 1709 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_boot.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_boot.o index 991d904076a045e1545a76419a417afacd2c2534..f6a244146da5190db00db15e2f18f2d8182e7454 100755 GIT binary patch delta 528 zcmYjLJxE(&6#ee^zGq&I33)$JE7B^0Kez-54s8+qDJ3QHgcLd$6$gcY_!|ip&bfRSZMSW6Rj|EL{Q-)% zKnNI=Ld@ev#P%c<#Yjjnjs*>={~=$>Kq)Jwo9wB8$I8%W*fRpnG&H4WhO_K7kW%{` z=#CL8#i4Wy(;(BHBzsC_co^y*4=@(FB}55{n?fM)6(ceZ75H9u!X2VaL?$T&KS!wX zi(Y6NZ>0x)IHVanC0eSL6yU$@9Jws z_UAY0RC_AXl1 zI0y+xv4t+umI@VA9&Qc}irPUf%@nj$$Y3Gh>Qd-AW+`5{-}%n@efMztQ$MC!XYt}q z_6nL0p%iAcQs3D8e>6fFMjFmDMq1nVIiz)XSUO`XVJ6&^&ar2OIboZNW$ar0wy?j< zOj`nT<6?KkUYiu#6tV=SMCH`=Xvg)jO4(!s>$H;e zah(oWpU_0gM~@z*idd$%sZo6xqi!mPIw76sXn{3KRn|*%hxI!>XMG)fNw1wa0`enb AMF0Q* diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_cdc.lst b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_cdc.lst index afe74768..c6936755 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_cdc.lst +++ b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_cdc.lst @@ -1,4 +1,4 @@ -ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccSehHjb.s page 1 +ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc3vPMDe.s page 1 1 .syntax unified @@ -58,7 +58,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccSehHjb.s page 1 55 0047 02 .uleb128 0x2 56 0048 08 .byte 0x8 57 0049 05 .byte 0x5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccSehHjb.s page 2 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc3vPMDe.s page 2 58 004a 00000000 .4byte .LASF6 @@ -89,7 +89,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccSehHjb.s page 1 83 0078 02 .uleb128 0x2 84 0079 04 .byte 0x4 85 007a 07 .byte 0x7 - 86 007b 24010000 .4byte .LASF12 + 86 007b 35010000 .4byte .LASF12 87 007f 00 .byte 0 88 .section .debug_abbrev,"",%progbits 89 .Ldebug_abbrev0: @@ -118,7 +118,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccSehHjb.s page 1 112 0016 03 .uleb128 0x3 113 0017 0E .uleb128 0xe 114 0018 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccSehHjb.s page 3 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc3vPMDe.s page 3 115 0019 00 .byte 0 @@ -178,7 +178,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccSehHjb.s page 1 149 69676E65 149 6420696E 149 7400 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccSehHjb.s page 4 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc3vPMDe.s page 4 150 .LASF7: @@ -226,13 +226,14 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccSehHjb.s page 1 169 7420696E 169 7400 170 .LASF15: - 171 0104 573A5C53 .ascii "W:\\SCSI2SD\\USB_Bootloader.cydsn\000" + 171 0104 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" 171 43534932 - 171 53445C55 - 171 53425F42 - 171 6F6F746C - 172 .LASF12: - 173 0124 73697A65 .ascii "sizetype\000" - 173 74797065 - 173 00 - 174 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br + 171 53445C73 + 171 6F667477 + 171 6172655C + 172 0133 6E00 .ascii "n\000" + 173 .LASF12: + 174 0135 73697A65 .ascii "sizetype\000" + 174 74797065 + 174 00 + 175 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_cdc.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_cdc.o index d34fd2c8f7bd02577aae783a5bbf9e32536710a2..5ce9e729e4451a4d6f1b584d119e033015b3386b 100755 GIT binary patch delta 85 zcmcb?_kwSN0%OBO#Xd&UjT`b9Ig0bsO3D+9Qa6h-H8D<}!MuU-!emdDa>j(o2U&s{ p?Iw$|Dl_^{wq#Xj+&4K9NPe8$$*Ru8z&3dks~Y2h%{N)=83F2p8{Pl_ delta 76 zcmV-S0JHz-4%iNmAOUcZA&vngv9N9dvo8X90h6Z#u>ru7Sp;_hP?OOFQvofLB?Th^ iJd;TUCjqUKaRny<;FFmJCj#&Vlfnfi0kE^_1%CnHWEo}v diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_cls.lst b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_cls.lst index 186e3912..338358c2 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_cls.lst +++ b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_cls.lst @@ -1,4 +1,4 @@ -ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 1 +ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccfm3BeD.s page 1 1 .syntax unified @@ -58,7 +58,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 1 29:.\Generated_Source\PSoC5/USBFS_cls.c **** /* `#END` */ 30:.\Generated_Source\PSoC5/USBFS_cls.c **** 31:.\Generated_Source\PSoC5/USBFS_cls.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 2 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccfm3BeD.s page 2 32:.\Generated_Source\PSoC5/USBFS_cls.c **** /******************************************************************************* @@ -118,7 +118,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 1 49 .loc 1 61 0 50 0018 00F07F03 and r3, r0, #127 60:.\Generated_Source\PSoC5/USBFS_cls.c **** interfaceNumber = - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 3 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccfm3BeD.s page 3 51 .loc 1 60 0 @@ -178,7 +178,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 1 86:.\Generated_Source\PSoC5/USBFS_cls.c **** } 87:.\Generated_Source\PSoC5/USBFS_cls.c **** 88:.\Generated_Source\PSoC5/USBFS_cls.c **** /* `#START USER_DEFINED_CLASS_CODE` Place your Class request here */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 4 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccfm3BeD.s page 4 89:.\Generated_Source\PSoC5/USBFS_cls.c **** @@ -217,10 +217,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 1 105 0006 00000000 .4byte .Ldebug_abbrev0 106 000a 04 .byte 0x4 107 000b 01 .uleb128 0x1 - 108 000c 68010000 .4byte .LASF30 + 108 000c 99010000 .4byte .LASF30 109 0010 01 .byte 0x1 - 110 0011 F0010000 .4byte .LASF31 - 111 0015 B1010000 .4byte .LASF32 + 110 0011 01020000 .4byte .LASF31 + 111 0015 A5000000 .4byte .LASF32 112 0019 00000000 .4byte .Ldebug_ranges0+0 113 001d 00000000 .4byte 0 114 0021 00000000 .4byte 0 @@ -228,17 +228,17 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 1 116 0029 02 .uleb128 0x2 117 002a 01 .byte 0x1 118 002b 06 .byte 0x6 - 119 002c E4010000 .4byte .LASF0 + 119 002c F5010000 .4byte .LASF0 120 0030 02 .uleb128 0x2 121 0031 01 .byte 0x1 122 0032 08 .byte 0x8 - 123 0033 C3000000 .4byte .LASF1 + 123 0033 F4000000 .4byte .LASF1 124 0037 02 .uleb128 0x2 125 0038 02 .byte 0x2 126 0039 05 .byte 0x5 - 127 003a 58010000 .4byte .LASF2 + 127 003a 89010000 .4byte .LASF2 128 003e 02 .uleb128 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 5 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccfm3BeD.s page 5 129 003f 02 .byte 0x2 @@ -247,7 +247,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 1 132 0045 02 .uleb128 0x2 133 0046 04 .byte 0x4 134 0047 05 .byte 0x5 - 135 0048 DB010000 .4byte .LASF4 + 135 0048 EC010000 .4byte .LASF4 136 004c 02 .uleb128 0x2 137 004d 04 .byte 0x4 138 004e 07 .byte 0x7 @@ -255,11 +255,11 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 1 140 0053 02 .uleb128 0x2 141 0054 08 .byte 0x8 142 0055 05 .byte 0x5 - 143 0056 3A010000 .4byte .LASF6 + 143 0056 6B010000 .4byte .LASF6 144 005a 02 .uleb128 0x2 145 005b 08 .byte 0x8 146 005c 07 .byte 0x7 - 147 005d 09010000 .4byte .LASF7 + 147 005d 3A010000 .4byte .LASF7 148 0061 03 .uleb128 0x3 149 0062 04 .byte 0x4 150 0063 05 .byte 0x5 @@ -267,14 +267,14 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 1 152 0068 02 .uleb128 0x2 153 0069 04 .byte 0x4 154 006a 07 .byte 0x7 - 155 006b FC000000 .4byte .LASF8 + 155 006b 2D010000 .4byte .LASF8 156 006f 04 .uleb128 0x4 - 157 0070 62010000 .4byte .LASF9 + 157 0070 93010000 .4byte .LASF9 158 0074 02 .byte 0x2 159 0075 5B .byte 0x5b 160 0076 30000000 .4byte 0x30 161 007a 04 .uleb128 0x4 - 162 007b EA000000 .4byte .LASF10 + 162 007b 1B010000 .4byte .LASF10 163 007f 02 .byte 0x2 164 0080 5C .byte 0x5c 165 0081 3E000000 .4byte 0x3e @@ -285,11 +285,11 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 1 170 008c 02 .uleb128 0x2 171 008d 08 .byte 0x8 172 008e 04 .byte 0x4 - 173 008f D1000000 .4byte .LASF12 + 173 008f 02010000 .4byte .LASF12 174 0093 02 .uleb128 0x2 175 0094 01 .byte 0x1 176 0095 08 .byte 0x8 - 177 0096 48010000 .4byte .LASF13 + 177 0096 79010000 .4byte .LASF13 178 009a 04 .uleb128 0x4 179 009b 76000000 .4byte .LASF14 180 009f 02 .byte 0x2 @@ -298,19 +298,19 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 1 183 00a5 05 .uleb128 0x5 184 00a6 6F000000 .4byte 0x6f 185 00aa 02 .uleb128 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 6 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccfm3BeD.s page 6 186 00ab 04 .byte 0x4 187 00ac 07 .byte 0x7 - 188 00ad 2A010000 .4byte .LASF15 + 188 00ad 5B010000 .4byte .LASF15 189 00b1 06 .uleb128 0x6 190 00b2 0C .byte 0xc 191 00b3 03 .byte 0x3 192 00b4 79 .byte 0x79 193 00b5 38010000 .4byte 0x138 194 00b9 07 .uleb128 0x7 - 195 00ba D8000000 .4byte .LASF16 + 195 00ba 09010000 .4byte .LASF16 196 00be 03 .byte 0x3 197 00bf 7B .byte 0x7b 198 00c0 6F000000 .4byte 0x6f @@ -318,7 +318,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 1 200 00c5 23 .byte 0x23 201 00c6 00 .uleb128 0 202 00c7 07 .uleb128 0x7 - 203 00c8 F1000000 .4byte .LASF17 + 203 00c8 22010000 .4byte .LASF17 204 00cc 03 .byte 0x3 205 00cd 7C .byte 0x7c 206 00ce 6F000000 .4byte 0x6f @@ -326,7 +326,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 1 208 00d3 23 .byte 0x23 209 00d4 01 .uleb128 0x1 210 00d5 07 .uleb128 0x7 - 211 00d6 20010000 .4byte .LASF18 + 211 00d6 51010000 .4byte .LASF18 212 00da 03 .byte 0x3 213 00db 7D .byte 0x7d 214 00dc 6F000000 .4byte 0x6f @@ -342,7 +342,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 1 224 00ef 23 .byte 0x23 225 00f0 03 .uleb128 0x3 226 00f1 07 .uleb128 0x7 - 227 00f2 A5000000 .4byte .LASF20 + 227 00f2 D6000000 .4byte .LASF20 228 00f6 03 .byte 0x3 229 00f7 7F .byte 0x7f 230 00f8 6F000000 .4byte 0x6f @@ -350,7 +350,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 1 232 00fd 23 .byte 0x23 233 00fe 04 .uleb128 0x4 234 00ff 07 .uleb128 0x7 - 235 0100 33010000 .4byte .LASF21 + 235 0100 64010000 .4byte .LASF21 236 0104 03 .byte 0x3 237 0105 80 .byte 0x80 238 0106 6F000000 .4byte 0x6f @@ -358,10 +358,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 1 240 010b 23 .byte 0x23 241 010c 05 .uleb128 0x5 242 010d 07 .uleb128 0x7 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 7 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccfm3BeD.s page 7 - 243 010e DF000000 .4byte .LASF22 + 243 010e 10010000 .4byte .LASF22 244 0112 03 .byte 0x3 245 0113 81 .byte 0x81 246 0114 7A000000 .4byte 0x7a @@ -369,7 +369,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 1 248 0119 23 .byte 0x23 249 011a 06 .uleb128 0x6 250 011b 07 .uleb128 0x7 - 251 011c 4D010000 .4byte .LASF23 + 251 011c 7E010000 .4byte .LASF23 252 0120 03 .byte 0x3 253 0121 82 .byte 0x82 254 0122 7A000000 .4byte 0x7a @@ -377,7 +377,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 1 256 0127 23 .byte 0x23 257 0128 08 .uleb128 0x8 258 0129 07 .uleb128 0x7 - 259 012a D1010000 .4byte .LASF24 + 259 012a E2010000 .4byte .LASF24 260 012e 03 .byte 0x3 261 012f 83 .byte 0x83 262 0130 6F000000 .4byte 0x6f @@ -411,14 +411,14 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 1 290 0167 6F000000 .4byte 0x6f 291 016b 00 .byte 0 292 016c 0A .uleb128 0xa - 293 016d AA000000 .4byte .LASF27 + 293 016d DB000000 .4byte .LASF27 294 0171 01 .byte 0x1 295 0172 33 .byte 0x33 296 0173 6F000000 .4byte 0x6f 297 0177 00000000 .4byte .LLST0 298 017b 0B .uleb128 0xb 299 017c 3C000000 .4byte .LVL6 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 8 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccfm3BeD.s page 8 300 0180 01 .byte 0x1 @@ -444,7 +444,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 1 320 01ac 08 .byte 0x8 321 01ad 00 .byte 0 322 01ae 0C .uleb128 0xc - 323 01af BA000000 .4byte .LASF29 + 323 01af EB000000 .4byte .LASF29 324 01b3 04 .byte 0x4 325 01b4 3F .byte 0x3f 326 01b5 BB010000 .4byte 0x1bb @@ -478,7 +478,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 1 354 000c 06 .uleb128 0x6 355 000d 11 .uleb128 0x11 356 000e 01 .uleb128 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 9 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccfm3BeD.s page 9 357 000f 52 .uleb128 0x52 @@ -538,7 +538,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 1 411 0045 0B .uleb128 0xb 412 0046 3B .uleb128 0x3b 413 0047 0B .uleb128 0xb - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 10 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccfm3BeD.s page 10 414 0048 01 .uleb128 0x1 @@ -598,7 +598,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 1 468 007f 0B .uleb128 0xb 469 0080 49 .uleb128 0x49 470 0081 13 .uleb128 0x13 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 11 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccfm3BeD.s page 11 471 0082 1C .uleb128 0x1c @@ -658,7 +658,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 1 525 00bb 00 .byte 0 526 00bc 00 .byte 0 527 00bd 0E .uleb128 0xe - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 12 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccfm3BeD.s page 12 528 00be 26 .uleb128 0x26 @@ -718,7 +718,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 1 582 0014 0100 .2byte 0x1 583 0016 53 .byte 0x53 584 0017 26000000 .4byte .LVL2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 13 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccfm3BeD.s page 13 585 001b 2A000000 .4byte .LVL3 @@ -778,7 +778,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 1 631 .LASF25: 632 0013 545F5553 .ascii "T_USBFS_EP_CTL_BLOCK\000" 632 4246535F - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 14 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccfm3BeD.s page 14 632 45505F43 @@ -823,120 +823,121 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 1 648 69676E65 648 6420696E 648 7400 - 649 .LASF20: - 650 00a5 61646472 .ascii "addr\000" - 650 00 - 651 .LASF27: - 652 00aa 696E7465 .ascii "interfaceNumber\000" - 652 72666163 - 652 654E756D - 652 62657200 - 653 .LASF29: - 654 00ba 55534246 .ascii "USBFS_EP\000" - 654 535F4550 - 654 00 - 655 .LASF1: - 656 00c3 756E7369 .ascii "unsigned char\000" - 656 676E6564 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 15 - - - 656 20636861 - 656 7200 - 657 .LASF12: - 658 00d1 646F7562 .ascii "double\000" - 658 6C6500 - 659 .LASF16: - 660 00d8 61747472 .ascii "attrib\000" - 660 696200 - 661 .LASF22: - 662 00df 62756666 .ascii "buffOffset\000" - 662 4F666673 - 662 657400 - 663 .LASF10: - 664 00ea 75696E74 .ascii "uint16\000" - 664 313600 - 665 .LASF17: - 666 00f1 61706945 .ascii "apiEpState\000" - 666 70537461 - 666 746500 - 667 .LASF8: - 668 00fc 756E7369 .ascii "unsigned int\000" - 668 676E6564 - 668 20696E74 - 668 00 - 669 .LASF7: - 670 0109 6C6F6E67 .ascii "long long unsigned int\000" - 670 206C6F6E - 670 6720756E - 670 7369676E - 670 65642069 - 671 .LASF18: - 672 0120 68774570 .ascii "hwEpState\000" - 672 53746174 - 672 6500 - 673 .LASF15: - 674 012a 73697A65 .ascii "sizetype\000" - 674 74797065 - 674 00 - 675 .LASF21: - 676 0133 65704D6F .ascii "epMode\000" - 676 646500 - 677 .LASF6: - 678 013a 6C6F6E67 .ascii "long long int\000" - 678 206C6F6E - 678 6720696E - 678 7400 - 679 .LASF13: - 680 0148 63686172 .ascii "char\000" - 680 00 - 681 .LASF23: - 682 014d 62756666 .ascii "bufferSize\000" - 682 65725369 - 682 7A6500 - 683 .LASF2: - 684 0158 73686F72 .ascii "short int\000" - 684 7420696E - 684 7400 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5apSsq.s page 16 - - - 685 .LASF9: - 686 0162 75696E74 .ascii "uint8\000" - 686 3800 - 687 .LASF30: - 688 0168 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 688 4320342E - 688 372E3320 - 688 32303133 - 688 30333132 - 689 019b 616E6368 .ascii "anch revision 196615]\000" - 689 20726576 - 689 6973696F - 689 6E203139 - 689 36363135 - 690 .LASF32: - 691 01b1 573A5C53 .ascii "W:\\SCSI2SD\\USB_Bootloader.cydsn\000" - 691 43534932 - 691 53445C55 - 691 53425F42 - 691 6F6F746C - 692 .LASF24: - 693 01d1 696E7465 .ascii "interface\000" - 693 72666163 - 693 6500 - 694 .LASF4: - 695 01db 6C6F6E67 .ascii "long int\000" - 695 20696E74 - 695 00 - 696 .LASF0: - 697 01e4 7369676E .ascii "signed char\000" - 697 65642063 - 697 68617200 - 698 .LASF31: - 699 01f0 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\USBFS_cls.c\000" - 699 6E657261 - 699 7465645F - 699 536F7572 - 699 63655C50 - 700 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br + 649 .LASF32: + 650 00a5 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" + 650 43534932 + 650 53445C73 + 650 6F667477 + 650 6172655C + 651 00d4 6E00 .ascii "n\000" + 652 .LASF20: + 653 00d6 61646472 .ascii "addr\000" + 653 00 + 654 .LASF27: + 655 00db 696E7465 .ascii "interfaceNumber\000" + 655 72666163 + 655 654E756D + 655 62657200 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccfm3BeD.s page 15 + + + 656 .LASF29: + 657 00eb 55534246 .ascii "USBFS_EP\000" + 657 535F4550 + 657 00 + 658 .LASF1: + 659 00f4 756E7369 .ascii "unsigned char\000" + 659 676E6564 + 659 20636861 + 659 7200 + 660 .LASF12: + 661 0102 646F7562 .ascii "double\000" + 661 6C6500 + 662 .LASF16: + 663 0109 61747472 .ascii "attrib\000" + 663 696200 + 664 .LASF22: + 665 0110 62756666 .ascii "buffOffset\000" + 665 4F666673 + 665 657400 + 666 .LASF10: + 667 011b 75696E74 .ascii "uint16\000" + 667 313600 + 668 .LASF17: + 669 0122 61706945 .ascii "apiEpState\000" + 669 70537461 + 669 746500 + 670 .LASF8: + 671 012d 756E7369 .ascii "unsigned int\000" + 671 676E6564 + 671 20696E74 + 671 00 + 672 .LASF7: + 673 013a 6C6F6E67 .ascii "long long unsigned int\000" + 673 206C6F6E + 673 6720756E + 673 7369676E + 673 65642069 + 674 .LASF18: + 675 0151 68774570 .ascii "hwEpState\000" + 675 53746174 + 675 6500 + 676 .LASF15: + 677 015b 73697A65 .ascii "sizetype\000" + 677 74797065 + 677 00 + 678 .LASF21: + 679 0164 65704D6F .ascii "epMode\000" + 679 646500 + 680 .LASF6: + 681 016b 6C6F6E67 .ascii "long long int\000" + 681 206C6F6E + 681 6720696E + 681 7400 + 682 .LASF13: + 683 0179 63686172 .ascii "char\000" + 683 00 + 684 .LASF23: + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccfm3BeD.s page 16 + + + 685 017e 62756666 .ascii "bufferSize\000" + 685 65725369 + 685 7A6500 + 686 .LASF2: + 687 0189 73686F72 .ascii "short int\000" + 687 7420696E + 687 7400 + 688 .LASF9: + 689 0193 75696E74 .ascii "uint8\000" + 689 3800 + 690 .LASF30: + 691 0199 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" + 691 4320342E + 691 372E3320 + 691 32303133 + 691 30333132 + 692 01cc 616E6368 .ascii "anch revision 196615]\000" + 692 20726576 + 692 6973696F + 692 6E203139 + 692 36363135 + 693 .LASF24: + 694 01e2 696E7465 .ascii "interface\000" + 694 72666163 + 694 6500 + 695 .LASF4: + 696 01ec 6C6F6E67 .ascii "long int\000" + 696 20696E74 + 696 00 + 697 .LASF0: + 698 01f5 7369676E .ascii "signed char\000" + 698 65642063 + 698 68617200 + 699 .LASF31: + 700 0201 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\USBFS_cls.c\000" + 700 6E657261 + 700 7465645F + 700 536F7572 + 700 63655C50 + 701 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_cls.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_cls.o index d932047b97fd59e4d2d52816cf5389edd36b2213..6a62d977efa47a52109421925046196a274aed92 100755 GIT binary patch delta 416 zcmXAhPbkA-7{}k|{k`w+efQgFH3zjavoeJ&99UBRBo10kIcyFJCFNJlG-T$)jh>T( z#ImAUDijtP$}|lpOqV;sXQdszH3quraBBAGziojrXV={L^mtn@Pt}1iK7Nd zTD{>ljKd37VGKS>gZzO97USvUL~^D-Iho#e*D|}yTdUY?x7|n| zV2@q4=ufFdy#iFQrW0H=5QlH}_HOTDECj6-l8{1C5FaT_5YcF%paeWbF#(AWP>`ID5Qqvs9>Rj5N%E2Os;cbznO1-GxgAW=rjx+XA!rw4w?ovLYe;mC%}B8 zu>k9iA|Z?gHlcV=NaKl3DrB>a1e>L7D!Mc_a(T|`l*wgI(tX^1@@{5?DdnuDP1A|2 zu!1#7YqG$7?VM=1jV;wpV>751hp4J5&Gh|764lf<+ktPO!kC8kIG^ezelv=)0E_9?4ZcuBL^$3jZ)gDZEYm6i-SKi9!XM? z++3K8ql=uii{eHp2Pe&ec;0X2IXu7T_xyg(ujfAS6ezSn?PY5UR*$)+!MCnyVW!!| z!0}5v2F4w2854fRn5+i^E?IU2TaqQ39R^!36P2&n#Tp|SdWvn>x{t{pb-P(%y7Z|}wi4>r$7PKm z+^%R2jbBg}%O8>G;H=O=hw@AL_bLueIt8AwO#Qj?o!U=Pp25$_SYYQG1$jWcNR)`>NcSPKixi>y`ByT;{f$V PoTL7NyQ&v&JRai@HT_&v delta 448 zcmX9&O(;ZB6u#%abLT!k<0%V?LQl;Gqah2S{4FR^FIgBQBZ+2;i6miT;V(H^uwjy& z1q~Z3Qc_YDma-EIENqlg&V6$i=R4o|zVqGl9KH*0mw`AdpMj-G6awxoAFEatA6n5ML#?(TK@LJTNgf zzVM8{xGiF@8ucZ8#C^b)t3OQj6IIIMXos<_`MN9hpV?i{FiU^4U2eq9u8SHJ<7P$+ z2wX7Y);@~?l-nU*)NkhUos2{1U!)^BTbMMylz)_q!p38EX5%H*SS?UY(^j|qkaTS& zp^NHq5nMXQS{R~tu9`|z3{vS8wQQv$SqWL%-w^fMyv~T%9_{m5hg%bg_z(mgB+=RXHJ5mn%dqrGf=C<>bRSEjl51 Mq+?Ul4~}F115dJ8NB{r; diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_drv.lst b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_drv.lst index 6e929e05..f6fc75b5 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_drv.lst +++ b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_drv.lst @@ -1,4 +1,4 @@ -ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 +ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 1 1 .syntax unified @@ -58,7 +58,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 29:.\Generated_Source\PSoC5/USBFS_drv.c **** volatile uint8 USBFS_deviceAddress; 30:.\Generated_Source\PSoC5/USBFS_drv.c **** volatile uint8 USBFS_deviceStatus; 31:.\Generated_Source\PSoC5/USBFS_drv.c **** volatile uint8 USBFS_interfaceSetting[USBFS_MAX_INTERFACES_NUMBER]; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 2 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 2 32:.\Generated_Source\PSoC5/USBFS_drv.c **** volatile uint8 USBFS_interfaceSetting_last[USBFS_MAX_INTERFACES_NUMBER]; @@ -118,7 +118,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 86:.\Generated_Source\PSoC5/USBFS_drv.c **** { 87:.\Generated_Source\PSoC5/USBFS_drv.c **** modifyReg = 0u; /* if SETUP bit set -> exit without mod 88:.\Generated_Source\PSoC5/USBFS_drv.c **** } - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 3 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 3 89:.\Generated_Source\PSoC5/USBFS_drv.c **** @@ -178,7 +178,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 143:.\Generated_Source\PSoC5/USBFS_drv.c **** * 144:.\Generated_Source\PSoC5/USBFS_drv.c **** * Return: 145:.\Generated_Source\PSoC5/USBFS_drv.c **** * None. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 4 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 4 146:.\Generated_Source\PSoC5/USBFS_drv.c **** * @@ -238,7 +238,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 200:.\Generated_Source\PSoC5/USBFS_drv.c **** * Return: 201:.\Generated_Source\PSoC5/USBFS_drv.c **** * None. 202:.\Generated_Source\PSoC5/USBFS_drv.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 5 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 5 203:.\Generated_Source\PSoC5/USBFS_drv.c **** * Reentrant: @@ -298,7 +298,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 257:.\Generated_Source\PSoC5/USBFS_drv.c **** case USBFS_TRANS_STATE_NO_DATA_CONTROL: 258:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Update the completion block */ 259:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_UpdateStatusBlock(USBFS_XFER_ERROR); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 6 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 6 260:.\Generated_Source\PSoC5/USBFS_drv.c **** /* We expect no more data, so stall INs and OUTs */ @@ -358,7 +358,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 32 .LVL0: 309:.\Generated_Source\PSoC5/USBFS_drv.c **** uint8 ep0Count = 0u; 310:.\Generated_Source\PSoC5/USBFS_drv.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 7 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 7 311:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Update the transfer byte count from the last transaction */ @@ -418,7 +418,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 74 .loc 1 322 0 75 003a 0E49 ldr r1, .L16+4 76 003c 0B78 ldrb r3, [r1, #0] @ zero_extendqisi2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 8 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 8 77 003e 082B cmp r3, #8 @@ -478,7 +478,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 340:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_lastPacketSize = ep0Count; 111 .loc 1 340 0 112 0066 0349 ldr r1, .L16+4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 9 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 9 341:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Count = ep0Count; @@ -538,7 +538,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 364:.\Generated_Source\PSoC5/USBFS_drv.c **** * 365:.\Generated_Source\PSoC5/USBFS_drv.c **** * Reentrant: 366:.\Generated_Source\PSoC5/USBFS_drv.c **** * No. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 10 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 10 367:.\Generated_Source\PSoC5/USBFS_drv.c **** * @@ -598,7 +598,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 421:.\Generated_Source\PSoC5/USBFS_drv.c **** uint8 USBFS_InitZeroLengthControlTransfer(void) 422:.\Generated_Source\PSoC5/USBFS_drv.c **** 423:.\Generated_Source\PSoC5/USBFS_drv.c **** { - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 11 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 11 143 .loc 1 423 0 @@ -658,7 +658,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 182 002c 00000000 .word USBFS_lastPacketSize 183 0030 00000000 .word USBFS_ep0Count 184 .cfi_endproc - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 12 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 12 185 .LFE6: @@ -718,7 +718,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 214 .LFB10: 460:.\Generated_Source\PSoC5/USBFS_drv.c **** 461:.\Generated_Source\PSoC5/USBFS_drv.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 13 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 13 462:.\Generated_Source\PSoC5/USBFS_drv.c **** /******************************************************************************* @@ -778,7 +778,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 516:.\Generated_Source\PSoC5/USBFS_drv.c **** * No. 517:.\Generated_Source\PSoC5/USBFS_drv.c **** * 518:.\Generated_Source\PSoC5/USBFS_drv.c **** *******************************************************************************/ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 14 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 14 519:.\Generated_Source\PSoC5/USBFS_drv.c **** uint8 USBFS_InitControlWrite(void) @@ -838,7 +838,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 573:.\Generated_Source\PSoC5/USBFS_drv.c **** *******************************************************************************/ 574:.\Generated_Source\PSoC5/USBFS_drv.c **** void USBFS_ControlWriteDataStage(void) 575:.\Generated_Source\PSoC5/USBFS_drv.c **** { - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 15 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 15 215 .loc 1 575 0 @@ -898,7 +898,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 586:.\Generated_Source\PSoC5/USBFS_drv.c **** *USBFS_currentTD.pData = CY_GET_REG8((reg8 *)(USBFS_EP0_DR0_IND + regIndex)); 256 .loc 1 586 0 is_stmt 1 257 0024 5868 ldr r0, [r3, #4] - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 16 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 16 258 0026 11F8014B ldrb r4, [r1], #1 @ zero_extendqisi2 @@ -958,7 +958,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 297 0054 10BD pop {r4, pc} 298 .L30: 299 0056 00BF .align 2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 17 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 17 300 .L29: @@ -1018,7 +1018,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 632:.\Generated_Source\PSoC5/USBFS_drv.c **** /******************************************************************************* 633:.\Generated_Source\PSoC5/USBFS_drv.c **** * Function Name: USBFS_InitNoDataControlTransfer 634:.\Generated_Source\PSoC5/USBFS_drv.c **** ******************************************************************************** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 18 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 18 635:.\Generated_Source\PSoC5/USBFS_drv.c **** * @@ -1078,7 +1078,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 344 0014 0270 strb r2, [r0, #0] 661:.\Generated_Source\PSoC5/USBFS_drv.c **** 662:.\Generated_Source\PSoC5/USBFS_drv.c **** return(USBFS_TRUE); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 19 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 19 663:.\Generated_Source\PSoC5/USBFS_drv.c **** } @@ -1138,7 +1138,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 696:.\Generated_Source\PSoC5/USBFS_drv.c **** CY_SET_REG8(USBFS_CR0_PTR, USBFS_deviceAddress | USBFS_CR0_ENABLE); 697:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_deviceAddress = 0u; 698:.\Generated_Source\PSoC5/USBFS_drv.c **** } - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 20 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 20 699:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Go Idle */ @@ -1198,7 +1198,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 737:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_currentTD.pStatusBlock->status = completionCode; 380 .loc 1 737 0 381 000a 0870 strb r0, [r1, #0] - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 21 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 21 382 .loc 1 738 0 @@ -1258,7 +1258,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 697:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_deviceAddress = 0u; 430 .loc 1 697 0 431 0014 1970 strb r1, [r3, #0] - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 22 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 22 432 .L42: @@ -1318,7 +1318,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 479 0008 1A70 strb r2, [r3, #0] 626:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK); 480 .loc 1 626 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 23 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 23 481 000a FFF7FEFF bl USBFS_UpdateStatusBlock @@ -1378,7 +1378,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 528 .loc 1 217 0 529 0014 FFF7FEBF b USBFS_ControlWriteStatusStage 530 .LVL17: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 24 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 24 531 .L55: @@ -1438,7 +1438,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 578 .loc 1 493 0 579 001c 0449 ldr r1, .L60+12 580 001e 0322 movs r2, #3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 25 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 25 581 0020 0A70 strb r2, [r1, #0] @@ -1498,7 +1498,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 629 .LVL21: 630 .L66: 259:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_UpdateStatusBlock(USBFS_XFER_ERROR); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 26 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 26 631 .loc 1 259 0 @@ -1558,7 +1558,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 678 .loc 1 160 0 679 000e 0F4B ldr r3, .L77+4 680 0010 1870 strb r0, [r3, #0] - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 27 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 27 681 0012 08BD pop {r3, pc} @@ -1618,7 +1618,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 726 0046 00BF .align 2 727 .L77: 728 0048 28600040 .word 1073766440 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 28 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 28 729 004c 00000000 .word USBFS_ep0Mode @@ -1678,7 +1678,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 776 0028 0006 lsls r0, r0, #24 777 002a 0DD5 bpl .L84 778 002c 08BD pop {r3, pc} - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 29 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 29 779 .LVL36: @@ -1738,7 +1738,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 824 .L92: 116:.\Generated_Source\PSoC5/USBFS_drv.c **** modifyReg = USBFS_ep0Mode; /* Init temporary variable */ 825 .loc 1 116 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 30 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 30 826 0066 0A49 ldr r1, .L95+4 @@ -1798,7 +1798,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 873 .thumb_func 874 .type USBFS_InitializeStatusBlock, %function 875 USBFS_InitializeStatusBlock: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 31 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 31 876 .LFB15: @@ -1858,7 +1858,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 893 .loc 1 776 0 894 0010 9068 ldr r0, [r2, #8] 895 0012 4380 strh r3, [r0, #2] @ movhi - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 32 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 32 896 .L97: @@ -1918,7 +1918,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 941 .loc 1 532 0 942 0018 094B ldr r3, .L106+12 530:.\Generated_Source\PSoC5/USBFS_drv.c **** xferCount = (((uint16)CY_GET_REG8(USBFS_lengthHi) << 8u) | (CY_GET_REG8(USBFS_lengthLo))); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 33 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 33 943 .loc 1 530 0 @@ -1978,7 +1978,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 990 .cfi_offset 4, -8 991 .cfi_offset 14, -4 372:.\Generated_Source\PSoC5/USBFS_drv.c **** if(USBFS_currentTD.count == 0u) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 34 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 34 992 .loc 1 372 0 @@ -2038,7 +2038,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1034 .L110: 394:.\Generated_Source\PSoC5/USBFS_drv.c **** } 1035 .loc 1 394 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 35 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 35 1036 003a 0120 movs r0, #1 @@ -2083,10 +2083,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1075 0006 00000000 .4byte .Ldebug_abbrev0 1076 000a 04 .byte 0x4 1077 000b 01 .uleb128 0x1 - 1078 000c F8020000 .4byte .LASF74 + 1078 000c 09030000 .4byte .LASF74 1079 0010 01 .byte 0x1 1080 0011 FA000000 .4byte .LASF75 - 1081 0015 35010000 .4byte .LASF76 + 1081 0015 31020000 .4byte .LASF76 1082 0019 00000000 .4byte .Ldebug_ranges0+0 1083 001d 00000000 .4byte 0 1084 0021 00000000 .4byte 0 @@ -2098,18 +2098,18 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1090 0030 02 .uleb128 0x2 1091 0031 01 .byte 0x1 1092 0032 08 .byte 0x8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 36 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 36 - 1093 0033 5A030000 .4byte .LASF1 + 1093 0033 6B030000 .4byte .LASF1 1094 0037 02 .uleb128 0x2 1095 0038 02 .byte 0x2 1096 0039 05 .byte 0x5 - 1097 003a 84030000 .4byte .LASF2 + 1097 003a 95030000 .4byte .LASF2 1098 003e 02 .uleb128 0x2 1099 003f 02 .byte 0x2 1100 0040 07 .byte 0x7 - 1101 0041 E9010000 .4byte .LASF3 + 1101 0041 C9010000 .4byte .LASF3 1102 0045 02 .uleb128 0x2 1103 0046 04 .byte 0x4 1104 0047 05 .byte 0x5 @@ -2117,7 +2117,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1106 004c 02 .uleb128 0x2 1107 004d 04 .byte 0x4 1108 004e 07 .byte 0x7 - 1109 004f C9010000 .4byte .LASF5 + 1109 004f A9010000 .4byte .LASF5 1110 0053 02 .uleb128 0x2 1111 0054 08 .byte 0x8 1112 0055 05 .byte 0x5 @@ -2133,7 +2133,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1122 0068 02 .uleb128 0x2 1123 0069 04 .byte 0x4 1124 006a 07 .byte 0x7 - 1125 006b A4010000 .4byte .LASF8 + 1125 006b 84010000 .4byte .LASF8 1126 006f 04 .uleb128 0x4 1127 0070 EB000000 .4byte .LASF9 1128 0074 02 .byte 0x2 @@ -2147,7 +2147,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1136 0085 02 .uleb128 0x2 1137 0086 04 .byte 0x4 1138 0087 04 .byte 0x4 - 1139 0088 DE020000 .4byte .LASF11 + 1139 0088 EF020000 .4byte .LASF11 1140 008c 02 .uleb128 0x2 1141 008d 08 .byte 0x8 1142 008e 04 .byte 0x4 @@ -2155,10 +2155,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1144 0093 02 .uleb128 0x2 1145 0094 01 .byte 0x1 1146 0095 08 .byte 0x8 - 1147 0096 59040000 .4byte .LASF13 + 1147 0096 6A040000 .4byte .LASF13 1148 009a 04 .uleb128 0x4 - 1149 009b 41030000 .4byte .LASF14 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 37 + 1149 009b 52030000 .4byte .LASF14 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 37 1150 009f 02 .byte 0x2 @@ -2171,14 +2171,14 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1157 00af 02 .uleb128 0x2 1158 00b0 04 .byte 0x4 1159 00b1 07 .byte 0x7 - 1160 00b2 70020000 .4byte .LASF15 + 1160 00b2 81020000 .4byte .LASF15 1161 00b6 06 .uleb128 0x6 1162 00b7 0C .byte 0xc 1163 00b8 03 .byte 0x3 1164 00b9 79 .byte 0x79 1165 00ba 3D010000 .4byte 0x13d 1166 00be 07 .uleb128 0x7 - 1167 00bf 97020000 .4byte .LASF16 + 1167 00bf A8020000 .4byte .LASF16 1168 00c3 03 .byte 0x3 1169 00c4 7B .byte 0x7b 1170 00c5 6F000000 .4byte 0x6f @@ -2186,7 +2186,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1172 00ca 23 .byte 0x23 1173 00cb 00 .uleb128 0 1174 00cc 07 .uleb128 0x7 - 1175 00cd E4020000 .4byte .LASF17 + 1175 00cd F5020000 .4byte .LASF17 1176 00d1 03 .byte 0x3 1177 00d2 7C .byte 0x7c 1178 00d3 6F000000 .4byte 0x6f @@ -2194,7 +2194,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1180 00d8 23 .byte 0x23 1181 00d9 01 .uleb128 0x1 1182 00da 07 .uleb128 0x7 - 1183 00db 66020000 .4byte .LASF18 + 1183 00db 77020000 .4byte .LASF18 1184 00df 03 .byte 0x3 1185 00e0 7D .byte 0x7d 1186 00e1 6F000000 .4byte 0x6f @@ -2218,10 +2218,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1204 0102 23 .byte 0x23 1205 0103 04 .uleb128 0x4 1206 0104 07 .uleb128 0x7 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 38 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 38 - 1207 0105 69010000 .4byte .LASF21 + 1207 0105 49010000 .4byte .LASF21 1208 0109 03 .byte 0x3 1209 010a 80 .byte 0x80 1210 010b 6F000000 .4byte 0x6f @@ -2229,7 +2229,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1212 0110 23 .byte 0x23 1213 0111 05 .uleb128 0x5 1214 0112 07 .uleb128 0x7 - 1215 0113 78040000 .4byte .LASF22 + 1215 0113 89040000 .4byte .LASF22 1216 0117 03 .byte 0x3 1217 0118 81 .byte 0x81 1218 0119 7A000000 .4byte 0x7a @@ -2237,7 +2237,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1220 011e 23 .byte 0x23 1221 011f 06 .uleb128 0x6 1222 0120 07 .uleb128 0x7 - 1223 0121 5E040000 .4byte .LASF23 + 1223 0121 6F040000 .4byte .LASF23 1224 0125 03 .byte 0x3 1225 0126 82 .byte 0x82 1226 0127 7A000000 .4byte 0x7a @@ -2245,7 +2245,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1228 012c 23 .byte 0x23 1229 012d 08 .uleb128 0x8 1230 012e 07 .uleb128 0x7 - 1231 012f 2C020000 .4byte .LASF24 + 1231 012f 0C020000 .4byte .LASF24 1232 0133 03 .byte 0x3 1233 0134 83 .byte 0x83 1234 0135 6F000000 .4byte 0x6f @@ -2254,7 +2254,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1237 013b 0A .uleb128 0xa 1238 013c 00 .byte 0 1239 013d 04 .uleb128 0x4 - 1240 013e C5030000 .4byte .LASF25 + 1240 013e D6030000 .4byte .LASF25 1241 0142 03 .byte 0x3 1242 0143 84 .byte 0x84 1243 0144 B6000000 .4byte 0xb6 @@ -2264,7 +2264,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1247 014b 90 .byte 0x90 1248 014c 6D010000 .4byte 0x16d 1249 0150 07 .uleb128 0x7 - 1250 0151 CE040000 .4byte .LASF26 + 1250 0151 DF040000 .4byte .LASF26 1251 0155 03 .byte 0x3 1252 0156 92 .byte 0x92 1253 0157 6F000000 .4byte 0x6f @@ -2272,19 +2272,19 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1255 015c 23 .byte 0x23 1256 015d 00 .uleb128 0 1257 015e 07 .uleb128 0x7 - 1258 015f 52040000 .4byte .LASF27 + 1258 015f 63040000 .4byte .LASF27 1259 0163 03 .byte 0x3 1260 0164 93 .byte 0x93 1261 0165 7A000000 .4byte 0x7a 1262 0169 02 .byte 0x2 1263 016a 23 .byte 0x23 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 39 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 39 1264 016b 02 .uleb128 0x2 1265 016c 00 .byte 0 1266 016d 04 .uleb128 0x4 - 1267 016e AD020000 .4byte .LASF28 + 1267 016e BE020000 .4byte .LASF28 1268 0172 03 .byte 0x3 1269 0173 94 .byte 0x94 1270 0174 48010000 .4byte 0x148 @@ -2325,7 +2325,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1305 01b2 04 .byte 0x4 1306 01b3 6D010000 .4byte 0x16d 1307 01b7 04 .uleb128 0x4 - 1308 01b8 8E030000 .4byte .LASF32 + 1308 01b8 9F030000 .4byte .LASF32 1309 01bc 03 .byte 0x3 1310 01bd 9B .byte 0x9b 1311 01be 78010000 .4byte 0x178 @@ -2338,10 +2338,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1318 01cc 01 .byte 0x1 1319 01cd 0A .uleb128 0xa 1320 01ce 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 40 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 40 - 1321 01cf DB010000 .4byte .LASF33 + 1321 01cf BB010000 .4byte .LASF33 1322 01d3 01 .byte 0x1 1323 01d4 3301 .2byte 0x133 1324 01d6 01 .byte 0x1 @@ -2353,7 +2353,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1330 01e2 01 .byte 0x1 1331 01e3 F8010000 .4byte 0x1f8 1332 01e7 0B .uleb128 0xb - 1333 01e8 0B020000 .4byte .LASF35 + 1333 01e8 EB010000 .4byte .LASF35 1334 01ec 01 .byte 0x1 1335 01ed 3501 .2byte 0x135 1336 01ef 6F000000 .4byte 0x6f @@ -2361,7 +2361,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1338 01f7 00 .byte 0 1339 01f8 0C .uleb128 0xc 1340 01f9 01 .byte 0x1 - 1341 01fa 26050000 .4byte .LASF37 + 1341 01fa 37050000 .4byte .LASF37 1342 01fe 01 .byte 0x1 1343 01ff A501 .2byte 0x1a5 1344 0201 01 .byte 0x1 @@ -2388,7 +2388,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1365 0231 00 .byte 0 1366 0232 0F .uleb128 0xf 1367 0233 01 .byte 0x1 - 1368 0234 36040000 .4byte .LASF34 + 1368 0234 47040000 .4byte .LASF34 1369 0238 01 .byte 0x1 1370 0239 3E02 .2byte 0x23e 1371 023b 01 .byte 0x1 @@ -2398,10 +2398,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1375 0248 01 .byte 0x1 1376 0249 6E020000 .4byte 0x26e 1377 024d 0B .uleb128 0xb - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 41 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 41 - 1378 024e 0B020000 .4byte .LASF35 + 1378 024e EB010000 .4byte .LASF35 1379 0252 01 .byte 0x1 1380 0253 4002 .2byte 0x240 1381 0255 6F000000 .4byte 0x6f @@ -2415,7 +2415,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1389 026d 00 .byte 0 1390 026e 0C .uleb128 0xc 1391 026f 01 .byte 0x1 - 1392 0270 F9030000 .4byte .LASF38 + 1392 0270 0A040000 .4byte .LASF38 1393 0274 01 .byte 0x1 1394 0275 8F02 .2byte 0x28f 1395 0277 01 .byte 0x1 @@ -2428,7 +2428,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1402 0287 01 .byte 0x1 1403 0288 0A .uleb128 0xa 1404 0289 01 .byte 0x1 - 1405 028a B1010000 .4byte .LASF39 + 1405 028a 91010000 .4byte .LASF39 1406 028e 01 .byte 0x1 1407 028f DD02 .2byte 0x2dd 1408 0291 01 .byte 0x1 @@ -2448,7 +2448,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1422 02b2 00 .byte 0 1423 02b3 0F .uleb128 0xf 1424 02b4 01 .byte 0x1 - 1425 02b5 DA030000 .4byte .LASF40 + 1425 02b5 EB030000 .4byte .LASF40 1426 02b9 01 .byte 0x1 1427 02ba B302 .2byte 0x2b3 1428 02bc 01 .byte 0x1 @@ -2458,7 +2458,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1432 02c9 01 .byte 0x1 1433 02ca DE020000 .4byte 0x2de 1434 02ce 11 .uleb128 0x11 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 42 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 42 1435 02cf 22000000 .4byte .LVL14 @@ -2472,7 +2472,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1443 02dd 00 .byte 0 1444 02de 0F .uleb128 0xf 1445 02df 01 .byte 0x1 - 1446 02e0 4A050000 .4byte .LASF41 + 1446 02e0 5B050000 .4byte .LASF41 1447 02e4 01 .byte 0x1 1448 02e5 6D02 .2byte 0x26d 1449 02e7 01 .byte 0x1 @@ -2493,7 +2493,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1464 0308 00 .byte 0 1465 0309 13 .uleb128 0x13 1466 030a 01 .byte 0x1 - 1467 030b FC010000 .4byte .LASF42 + 1467 030b DC010000 .4byte .LASF42 1468 030f 01 .byte 0x1 1469 0310 CF .byte 0xcf 1470 0311 01 .byte 0x1 @@ -2518,7 +2518,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1489 033f 00 .byte 0 1490 0340 0E .uleb128 0xe 1491 0341 18000000 .4byte .LVL17 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 43 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 43 1492 0345 01 .byte 0x1 @@ -2530,7 +2530,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1498 0354 00 .byte 0 1499 0355 0F .uleb128 0xf 1500 0356 01 .byte 0x1 - 1501 0357 87010000 .4byte .LASF43 + 1501 0357 67010000 .4byte .LASF43 1502 035b 01 .byte 0x1 1503 035c E401 .2byte 0x1e4 1504 035e 01 .byte 0x1 @@ -2551,7 +2551,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1519 037f 00 .byte 0 1520 0380 15 .uleb128 0x15 1521 0381 01 .byte 0x1 - 1522 0382 79020000 .4byte .LASF44 + 1522 0382 8A020000 .4byte .LASF44 1523 0386 01 .byte 0x1 1524 0387 F5 .byte 0xf5 1525 0388 01 .byte 0x1 @@ -2578,12 +2578,12 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1546 03bb 33 .byte 0x33 1547 03bc 00 .byte 0 1548 03bd 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 44 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 44 1549 03be 15 .uleb128 0x15 1550 03bf 01 .byte 0x1 - 1551 03c0 BC040000 .4byte .LASF45 + 1551 03c0 CD040000 .4byte .LASF45 1552 03c4 01 .byte 0x1 1553 03c5 97 .byte 0x97 1554 03c6 01 .byte 0x1 @@ -2593,7 +2593,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1558 03d3 01 .byte 0x1 1559 03d4 16040000 .4byte 0x416 1560 03d8 16 .uleb128 0x16 - 1561 03d9 69040000 .4byte .LASF46 + 1561 03d9 7A040000 .4byte .LASF46 1562 03dd 01 .byte 0x1 1563 03de 99 .byte 0x99 1564 03df 6F000000 .4byte 0x6f @@ -2636,9 +2636,9 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1601 0437 6F000000 .4byte 0x6f 1602 043b AA010000 .4byte .LLST12 1603 043f 16 .uleb128 0x16 - 1604 0440 B2040000 .4byte .LASF49 + 1604 0440 C3040000 .4byte .LASF49 1605 0444 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 45 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 45 1606 0445 45 .byte 0x45 @@ -2656,7 +2656,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1618 0469 00 .byte 0 1619 046a 19 .uleb128 0x19 1620 046b 01 .byte 0x1 - 1621 046c 68030000 .4byte .LASF79 + 1621 046c 79030000 .4byte .LASF79 1622 0470 01 .byte 0x1 1623 0471 0203 .2byte 0x302 1624 0473 01 .byte 0x1 @@ -2668,7 +2668,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1630 047f 01 .byte 0x1 1631 0480 1A .uleb128 0x1a 1632 0481 01 .byte 0x1 - 1633 0482 C7020000 .4byte .LASF51 + 1633 0482 D8020000 .4byte .LASF51 1634 0486 01 .byte 0x1 1635 0487 0702 .2byte 0x207 1636 0489 01 .byte 0x1 @@ -2679,7 +2679,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1641 049a 01 .byte 0x1 1642 049b B9040000 .4byte 0x4b9 1643 049f 0B .uleb128 0xb - 1644 04a0 ED040000 .4byte .LASF50 + 1644 04a0 FE040000 .4byte .LASF50 1645 04a4 01 .byte 0x1 1646 04a5 0902 .2byte 0x209 1647 04a7 7A000000 .4byte 0x7a @@ -2698,13 +2698,13 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1660 04c7 00000000 .4byte .LFB5 1661 04cb 50000000 .4byte .LFE5 1662 04cf 56020000 .4byte .LLST16 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 46 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 46 1663 04d3 01 .byte 0x1 1664 04d4 04050000 .4byte 0x504 1665 04d8 0B .uleb128 0xb - 1666 04d9 ED040000 .4byte .LASF50 + 1666 04d9 FE040000 .4byte .LASF50 1667 04dd 01 .byte 0x1 1668 04de 7301 .2byte 0x173 1669 04e0 7A000000 .4byte 0x7a @@ -2720,7 +2720,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1679 04ff CD010000 .4byte 0x1cd 1680 0503 00 .byte 0 1681 0504 1B .uleb128 0x1b - 1682 0505 19040000 .4byte .LASF53 + 1682 0505 2A040000 .4byte .LASF53 1683 0509 01 .byte 0x1 1684 050a 22 .byte 0x22 1685 050b A5000000 .4byte 0xa5 @@ -2729,7 +2729,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1688 0511 03 .byte 0x3 1689 0512 00000000 .4byte USBFS_device 1690 0516 1B .uleb128 0x1b - 1691 0517 46030000 .4byte .LASF54 + 1691 0517 57030000 .4byte .LASF54 1692 051b 01 .byte 0x1 1693 051c 2C .byte 0x2c 1694 051d A5000000 .4byte 0xa5 @@ -2738,7 +2738,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1697 0523 03 .byte 0x3 1698 0524 00000000 .4byte USBFS_transferState 1699 0528 1B .uleb128 0x1b - 1700 0529 55010000 .4byte .LASF55 + 1700 0529 35010000 .4byte .LASF55 1701 052d 01 .byte 0x1 1702 052e 1A .byte 0x1a 1703 052f A5000000 .4byte 0xa5 @@ -2747,7 +2747,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1706 0535 03 .byte 0x3 1707 0536 00000000 .4byte USBFS_configuration 1708 053a 1B .uleb128 0x1b - 1709 053b 36020000 .4byte .LASF56 + 1709 053b 16020000 .4byte .LASF56 1710 053f 01 .byte 0x1 1711 0540 1C .byte 0x1c 1712 0541 A5000000 .4byte 0xa5 @@ -2756,9 +2756,9 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1715 0547 03 .byte 0x3 1716 0548 00000000 .4byte USBFS_configurationChanged 1717 054c 1B .uleb128 0x1b - 1718 054d 83040000 .4byte .LASF57 + 1718 054d 94040000 .4byte .LASF57 1719 0551 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 47 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 47 1720 0552 1E .byte 0x1e @@ -2784,7 +2784,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1740 057e 00 .byte 0 1741 057f 00 .byte 0 1742 0580 1B .uleb128 0x1b - 1743 0581 AE030000 .4byte .LASF59 + 1743 0581 BF030000 .4byte .LASF59 1744 0585 01 .byte 0x1 1745 0586 1F .byte 0x1f 1746 0587 92050000 .4byte 0x592 @@ -2795,7 +2795,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1751 0592 05 .uleb128 0x5 1752 0593 70050000 .4byte 0x570 1753 0597 1B .uleb128 0x1b - 1754 0598 96040000 .4byte .LASF60 + 1754 0598 A7040000 .4byte .LASF60 1755 059c 01 .byte 0x1 1756 059d 20 .byte 0x20 1757 059e A9050000 .4byte 0x5a9 @@ -2815,10 +2815,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1771 05bb 03 .byte 0x3 1772 05bc 00000000 .4byte USBFS_deviceAddress 1773 05c0 1B .uleb128 0x1b - 1774 05c1 F7040000 .4byte .LASF62 + 1774 05c1 08050000 .4byte .LASF62 1775 05c5 01 .byte 0x1 1776 05c6 21 .byte 0x21 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 48 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 48 1777 05c7 D2050000 .4byte 0x5d2 @@ -2829,7 +2829,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1782 05d2 05 .uleb128 0x5 1783 05d3 70050000 .4byte 0x570 1784 05d7 1B .uleb128 0x1b - 1785 05d8 51020000 .4byte .LASF63 + 1785 05d8 62020000 .4byte .LASF63 1786 05dc 01 .byte 0x1 1787 05dd 23 .byte 0x23 1788 05de E9050000 .4byte 0x5e9 @@ -2850,7 +2850,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1803 0602 08 .byte 0x8 1804 0603 00 .byte 0 1805 0604 1B .uleb128 0x1b - 1806 0605 EF020000 .4byte .LASF64 + 1806 0605 00030000 .4byte .LASF64 1807 0609 01 .byte 0x1 1808 060a 19 .byte 0x19 1809 060b 16060000 .4byte 0x616 @@ -2872,19 +2872,19 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1825 062d 05 .uleb128 0x5 1826 062e B7010000 .4byte 0x1b7 1827 0632 1B .uleb128 0x1b - 1828 0633 26040000 .4byte .LASF66 + 1828 0633 37040000 .4byte .LASF66 1829 0637 01 .byte 0x1 1830 0638 2A .byte 0x2a 1831 0639 A5000000 .4byte 0xa5 1832 063d 01 .byte 0x1 1833 063e 05 .byte 0x5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 49 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 49 1834 063f 03 .byte 0x3 1835 0640 00000000 .4byte USBFS_ep0Toggle 1836 0644 1B .uleb128 0x1b - 1837 0645 99030000 .4byte .LASF67 + 1837 0645 AA030000 .4byte .LASF67 1838 0649 01 .byte 0x1 1839 064a 2B .byte 0x2b 1840 064b A5000000 .4byte 0xa5 @@ -2893,7 +2893,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1843 0651 03 .byte 0x3 1844 0652 00000000 .4byte USBFS_lastPacketSize 1845 0656 1B .uleb128 0x1b - 1846 0657 89020000 .4byte .LASF68 + 1846 0657 9A020000 .4byte .LASF68 1847 065b 01 .byte 0x1 1848 065c 2E .byte 0x2e 1849 065d A5000000 .4byte 0xa5 @@ -2902,7 +2902,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1852 0663 03 .byte 0x3 1853 0664 00000000 .4byte USBFS_ep0Mode 1854 0668 1B .uleb128 0x1b - 1855 0669 9E020000 .4byte .LASF69 + 1855 0669 AF020000 .4byte .LASF69 1856 066d 01 .byte 0x1 1857 066e 2F .byte 0x2f 1858 066f A5000000 .4byte 0xa5 @@ -2911,7 +2911,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1861 0675 03 .byte 0x3 1862 0676 00000000 .4byte USBFS_ep0Count 1863 067a 1B .uleb128 0x1b - 1864 067b 14020000 .4byte .LASF70 + 1864 067b F4010000 .4byte .LASF70 1865 067f 01 .byte 0x1 1866 0680 30 .byte 0x30 1867 0681 AA000000 .4byte 0xaa @@ -2921,7 +2921,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1871 0688 00000000 .4byte USBFS_transferByteCount 1872 068c 1F .uleb128 0x1f 1873 068d 01 .byte 0x1 - 1874 068e 0D050000 .4byte .LASF71 + 1874 068e 1E050000 .4byte .LASF71 1875 0692 04 .byte 0x4 1876 0693 B1 .byte 0xb1 1877 0694 01 .byte 0x1 @@ -2929,7 +2929,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1879 0699 01 .byte 0x1 1880 069a 1F .uleb128 0x1f 1881 069b 01 .byte 0x1 - 1882 069c D5040000 .4byte .LASF72 + 1882 069c E6040000 .4byte .LASF72 1883 06a0 04 .byte 0x4 1884 06a1 B2 .byte 0xb2 1885 06a2 01 .byte 0x1 @@ -2937,8 +2937,8 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1887 06a7 01 .byte 0x1 1888 06a8 1F .uleb128 0x1f 1889 06a9 01 .byte 0x1 - 1890 06aa 70010000 .4byte .LASF73 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 50 + 1890 06aa 50010000 .4byte .LASF73 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 50 1891 06ae 04 .byte 0x4 @@ -2998,7 +2998,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 1945 002e 03 .uleb128 0x3 1946 002f 0E .uleb128 0xe 1947 0030 3A .uleb128 0x3a - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 51 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 51 1948 0031 0B .uleb128 0xb @@ -3058,7 +3058,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 2002 0067 3F .uleb128 0x3f 2003 0068 0C .uleb128 0xc 2004 0069 03 .uleb128 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 52 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 52 2005 006a 0E .uleb128 0xe @@ -3118,7 +3118,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 2059 00a1 3F .uleb128 0x3f 2060 00a2 0C .uleb128 0xc 2061 00a3 03 .uleb128 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 53 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 53 2062 00a4 0E .uleb128 0xe @@ -3178,7 +3178,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 2116 00df 3A .uleb128 0x3a 2117 00e0 0B .uleb128 0xb 2118 00e1 3B .uleb128 0x3b - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 54 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 54 2119 00e2 05 .uleb128 0x5 @@ -3238,7 +3238,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 2173 011e 0E .uleb128 0xe 2174 011f 3A .uleb128 0x3a 2175 0120 0B .uleb128 0xb - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 55 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 55 2176 0121 3B .uleb128 0x3b @@ -3298,7 +3298,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 2230 0159 01 .uleb128 0x1 2231 015a 13 .uleb128 0x13 2232 015b 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 56 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 56 2233 015c 00 .byte 0 @@ -3358,7 +3358,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 2287 0196 0A .uleb128 0xa 2288 0197 9742 .uleb128 0x2117 2289 0199 0C .uleb128 0xc - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 57 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 57 2290 019a 00 .byte 0 @@ -3418,7 +3418,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 2344 01d1 00 .byte 0 2345 01d2 1D .uleb128 0x1d 2346 01d3 21 .uleb128 0x21 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 58 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 58 2347 01d4 00 .byte 0 @@ -3478,7 +3478,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 2401 002b 08 .sleb128 8 2402 002c 00000000 .4byte 0 2403 0030 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 59 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 59 2404 .LLST2: @@ -3538,7 +3538,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 2458 00b7 02000000 .4byte .LCFI1 2459 00bb 3C000000 .4byte .LFE13 2460 00bf 0200 .2byte 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 60 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 60 2461 00c1 7D .byte 0x7d @@ -3598,7 +3598,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 2515 0143 00000000 .4byte 0 2516 0147 00000000 .4byte 0 2517 .LLST10: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 61 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 61 2518 014b 06000000 .4byte .LVL23 @@ -3658,7 +3658,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 2572 01de 0100 .2byte 0x1 2573 01e0 53 .byte 0x53 2574 01e1 6E000000 .4byte .LVL46 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 62 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 62 2575 01e5 72000000 .4byte .LVL47 @@ -3718,7 +3718,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 2629 026a 0200 .2byte 0x2 2630 026c 7D .byte 0x7d 2631 026d 08 .sleb128 8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 63 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 63 2632 026e 00000000 .4byte 0 @@ -3778,7 +3778,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 2686 0004 94000000 .4byte .LFE4 2687 0008 00000000 .4byte .LFB6 2688 000c 34000000 .4byte .LFE6 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 64 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 64 2689 0010 00000000 .4byte .LFB7 @@ -3838,7 +3838,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 2731 0029 55534246 .ascii "USBFS_currentTD\000" 2731 535F6375 2731 7272656E - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 65 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 65 2731 74544400 @@ -3898,7 +3898,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 2753 20696E74 2753 00 2754 .LASF9: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 66 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 66 2755 00eb 75696E74 .ascii "uint8\000" @@ -3923,317 +3923,318 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 1 2764 .LASF30: 2765 012f 70446174 .ascii "pData\000" 2765 6100 - 2766 .LASF76: - 2767 0135 573A5C53 .ascii "W:\\SCSI2SD\\USB_Bootloader.cydsn\000" - 2767 43534932 - 2767 53445C55 - 2767 53425F42 - 2767 6F6F746C - 2768 .LASF55: - 2769 0155 55534246 .ascii "USBFS_configuration\000" - 2769 535F636F - 2769 6E666967 - 2769 75726174 - 2769 696F6E00 - 2770 .LASF21: - 2771 0169 65704D6F .ascii "epMode\000" - 2771 646500 - 2772 .LASF73: - 2773 0170 55534246 .ascii "USBFS_HandleVendorRqst\000" - 2773 535F4861 - 2773 6E646C65 - 2773 56656E64 - 2773 6F725271 - 2774 .LASF43: - 2775 0187 55534246 .ascii "USBFS_ControlReadStatusStage\000" - 2775 535F436F - 2775 6E74726F - 2775 6C526561 - 2775 64537461 - 2776 .LASF8: - 2777 01a4 756E7369 .ascii "unsigned int\000" - 2777 676E6564 - 2777 20696E74 - 2777 00 - 2778 .LASF39: - 2779 01b1 55534246 .ascii "USBFS_UpdateStatusBlock\000" - 2779 535F5570 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 67 - - - 2779 64617465 - 2779 53746174 - 2779 7573426C - 2780 .LASF5: - 2781 01c9 6C6F6E67 .ascii "long unsigned int\000" - 2781 20756E73 - 2781 69676E65 - 2781 6420696E - 2781 7400 - 2782 .LASF33: - 2783 01db 55534246 .ascii "USBFS_LoadEP0\000" - 2783 535F4C6F - 2783 61644550 - 2783 3000 - 2784 .LASF3: - 2785 01e9 73686F72 .ascii "short unsigned int\000" - 2785 7420756E - 2785 7369676E - 2785 65642069 - 2785 6E7400 - 2786 .LASF42: - 2787 01fc 55534246 .ascii "USBFS_HandleIN\000" - 2787 535F4861 - 2787 6E646C65 - 2787 494E00 - 2788 .LASF35: - 2789 020b 65703043 .ascii "ep0Count\000" - 2789 6F756E74 - 2789 00 - 2790 .LASF70: - 2791 0214 55534246 .ascii "USBFS_transferByteCount\000" - 2791 535F7472 - 2791 616E7366 - 2791 65724279 - 2791 7465436F - 2792 .LASF24: - 2793 022c 696E7465 .ascii "interface\000" - 2793 72666163 - 2793 6500 - 2794 .LASF56: - 2795 0236 55534246 .ascii "USBFS_configurationChanged\000" - 2795 535F636F - 2795 6E666967 - 2795 75726174 - 2795 696F6E43 - 2796 .LASF63: - 2797 0251 55534246 .ascii "USBFS_interfaceClass\000" - 2797 535F696E - 2797 74657266 - 2797 61636543 - 2797 6C617373 - 2798 .LASF18: - 2799 0266 68774570 .ascii "hwEpState\000" - 2799 53746174 - 2799 6500 - 2800 .LASF15: - 2801 0270 73697A65 .ascii "sizetype\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 68 - - - 2801 74797065 - 2801 00 - 2802 .LASF44: - 2803 0279 55534246 .ascii "USBFS_HandleOUT\000" - 2803 535F4861 - 2803 6E646C65 - 2803 4F555400 - 2804 .LASF68: - 2805 0289 55534246 .ascii "USBFS_ep0Mode\000" - 2805 535F6570 - 2805 304D6F64 - 2805 6500 - 2806 .LASF16: - 2807 0297 61747472 .ascii "attrib\000" - 2807 696200 - 2808 .LASF69: - 2809 029e 55534246 .ascii "USBFS_ep0Count\000" - 2809 535F6570 - 2809 30436F75 - 2809 6E7400 - 2810 .LASF28: - 2811 02ad 545F5553 .ascii "T_USBFS_XFER_STATUS_BLOCK\000" - 2811 4246535F - 2811 58464552 - 2811 5F535441 - 2811 5455535F - 2812 .LASF51: - 2813 02c7 55534246 .ascii "USBFS_InitControlWrite\000" - 2813 535F496E - 2813 6974436F - 2813 6E74726F - 2813 6C577269 - 2814 .LASF11: - 2815 02de 666C6F61 .ascii "float\000" - 2815 7400 - 2816 .LASF17: - 2817 02e4 61706945 .ascii "apiEpState\000" - 2817 70537461 - 2817 746500 - 2818 .LASF64: - 2819 02ef 55534246 .ascii "USBFS_EP\000" - 2819 535F4550 - 2819 00 - 2820 .LASF74: - 2821 02f8 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 2821 4320342E - 2821 372E3320 - 2821 32303133 - 2821 30333132 - 2822 032b 616E6368 .ascii "anch revision 196615]\000" - 2822 20726576 - 2822 6973696F - 2822 6E203139 - 2822 36363135 - 2823 .LASF14: - 2824 0341 72656738 .ascii "reg8\000" - 2824 00 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 69 - - - 2825 .LASF54: - 2826 0346 55534246 .ascii "USBFS_transferState\000" - 2826 535F7472 - 2826 616E7366 - 2826 65725374 - 2826 61746500 - 2827 .LASF1: - 2828 035a 756E7369 .ascii "unsigned char\000" - 2828 676E6564 - 2828 20636861 - 2828 7200 - 2829 .LASF79: - 2830 0368 55534246 .ascii "USBFS_InitializeStatusBlock\000" - 2830 535F496E - 2830 69746961 - 2830 6C697A65 - 2830 53746174 - 2831 .LASF2: - 2832 0384 73686F72 .ascii "short int\000" - 2832 7420696E - 2832 7400 - 2833 .LASF32: - 2834 038e 545F5553 .ascii "T_USBFS_TD\000" - 2834 4246535F - 2834 544400 - 2835 .LASF67: - 2836 0399 55534246 .ascii "USBFS_lastPacketSize\000" - 2836 535F6C61 - 2836 73745061 - 2836 636B6574 - 2836 53697A65 - 2837 .LASF59: - 2838 03ae 55534246 .ascii "USBFS_interfaceSetting\000" - 2838 535F696E - 2838 74657266 - 2838 61636553 - 2838 65747469 - 2839 .LASF25: - 2840 03c5 545F5553 .ascii "T_USBFS_EP_CTL_BLOCK\000" - 2840 4246535F - 2840 45505F43 - 2840 544C5F42 - 2840 4C4F434B - 2841 .LASF40: - 2842 03da 55534246 .ascii "USBFS_NoDataControlStatusStage\000" - 2842 535F4E6F - 2842 44617461 - 2842 436F6E74 - 2842 726F6C53 - 2843 .LASF38: - 2844 03f9 55534246 .ascii "USBFS_InitNoDataControlTransfer\000" - 2844 535F496E - 2844 69744E6F - 2844 44617461 - 2844 436F6E74 - 2845 .LASF53: - 2846 0419 55534246 .ascii "USBFS_device\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 70 - - - 2846 535F6465 - 2846 76696365 - 2846 00 - 2847 .LASF66: - 2848 0426 55534246 .ascii "USBFS_ep0Toggle\000" - 2848 535F6570 - 2848 30546F67 - 2848 676C6500 - 2849 .LASF34: - 2850 0436 55534246 .ascii "USBFS_ControlWriteDataStage\000" - 2850 535F436F - 2850 6E74726F - 2850 6C577269 - 2850 74654461 - 2851 .LASF27: - 2852 0452 6C656E67 .ascii "length\000" - 2852 746800 - 2853 .LASF13: - 2854 0459 63686172 .ascii "char\000" - 2854 00 - 2855 .LASF23: - 2856 045e 62756666 .ascii "bufferSize\000" - 2856 65725369 - 2856 7A6500 - 2857 .LASF46: - 2858 0469 72657175 .ascii "requestHandled\000" - 2858 65737448 - 2858 616E646C - 2858 656400 - 2859 .LASF22: - 2860 0478 62756666 .ascii "buffOffset\000" - 2860 4F666673 - 2860 657400 - 2861 .LASF57: - 2862 0483 55534246 .ascii "USBFS_deviceStatus\000" - 2862 535F6465 - 2862 76696365 - 2862 53746174 - 2862 757300 - 2863 .LASF60: - 2864 0496 55534246 .ascii "USBFS_interfaceSetting_last\000" - 2864 535F696E - 2864 74657266 - 2864 61636553 - 2864 65747469 - 2865 .LASF49: - 2866 04b2 6D6F6469 .ascii "modifyReg\000" - 2866 66795265 - 2866 6700 - 2867 .LASF45: - 2868 04bc 55534246 .ascii "USBFS_HandleSetup\000" - 2868 535F4861 - 2868 6E646C65 - 2868 53657475 - 2868 7000 - 2869 .LASF26: - 2870 04ce 73746174 .ascii "status\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccU0u4Ba.s page 71 - - - 2870 757300 - 2871 .LASF72: - 2872 04d5 55534246 .ascii "USBFS_DispatchClassRqst\000" - 2872 535F4469 - 2872 73706174 - 2872 6368436C - 2872 61737352 - 2873 .LASF50: - 2874 04ed 78666572 .ascii "xferCount\000" - 2874 436F756E - 2874 7400 - 2875 .LASF62: - 2876 04f7 55534246 .ascii "USBFS_interfaceStatus\000" - 2876 535F696E - 2876 74657266 - 2876 61636553 - 2876 74617475 - 2877 .LASF71: - 2878 050d 55534246 .ascii "USBFS_HandleStandardRqst\000" - 2878 535F4861 - 2878 6E646C65 - 2878 5374616E - 2878 64617264 - 2879 .LASF37: - 2880 0526 55534246 .ascii "USBFS_InitZeroLengthControlTransfer\000" - 2880 535F496E - 2880 69745A65 - 2880 726F4C65 - 2880 6E677468 - 2881 .LASF41: - 2882 054a 55534246 .ascii "USBFS_ControlWriteStatusStage\000" - 2882 535F436F - 2882 6E74726F - 2882 6C577269 - 2882 74655374 - 2883 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br + 2766 .LASF55: + 2767 0135 55534246 .ascii "USBFS_configuration\000" + 2767 535F636F + 2767 6E666967 + 2767 75726174 + 2767 696F6E00 + 2768 .LASF21: + 2769 0149 65704D6F .ascii "epMode\000" + 2769 646500 + 2770 .LASF73: + 2771 0150 55534246 .ascii "USBFS_HandleVendorRqst\000" + 2771 535F4861 + 2771 6E646C65 + 2771 56656E64 + 2771 6F725271 + 2772 .LASF43: + 2773 0167 55534246 .ascii "USBFS_ControlReadStatusStage\000" + 2773 535F436F + 2773 6E74726F + 2773 6C526561 + 2773 64537461 + 2774 .LASF8: + 2775 0184 756E7369 .ascii "unsigned int\000" + 2775 676E6564 + 2775 20696E74 + 2775 00 + 2776 .LASF39: + 2777 0191 55534246 .ascii "USBFS_UpdateStatusBlock\000" + 2777 535F5570 + 2777 64617465 + 2777 53746174 + 2777 7573426C + 2778 .LASF5: + 2779 01a9 6C6F6E67 .ascii "long unsigned int\000" + 2779 20756E73 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 67 + + + 2779 69676E65 + 2779 6420696E + 2779 7400 + 2780 .LASF33: + 2781 01bb 55534246 .ascii "USBFS_LoadEP0\000" + 2781 535F4C6F + 2781 61644550 + 2781 3000 + 2782 .LASF3: + 2783 01c9 73686F72 .ascii "short unsigned int\000" + 2783 7420756E + 2783 7369676E + 2783 65642069 + 2783 6E7400 + 2784 .LASF42: + 2785 01dc 55534246 .ascii "USBFS_HandleIN\000" + 2785 535F4861 + 2785 6E646C65 + 2785 494E00 + 2786 .LASF35: + 2787 01eb 65703043 .ascii "ep0Count\000" + 2787 6F756E74 + 2787 00 + 2788 .LASF70: + 2789 01f4 55534246 .ascii "USBFS_transferByteCount\000" + 2789 535F7472 + 2789 616E7366 + 2789 65724279 + 2789 7465436F + 2790 .LASF24: + 2791 020c 696E7465 .ascii "interface\000" + 2791 72666163 + 2791 6500 + 2792 .LASF56: + 2793 0216 55534246 .ascii "USBFS_configurationChanged\000" + 2793 535F636F + 2793 6E666967 + 2793 75726174 + 2793 696F6E43 + 2794 .LASF76: + 2795 0231 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" + 2795 43534932 + 2795 53445C73 + 2795 6F667477 + 2795 6172655C + 2796 0260 6E00 .ascii "n\000" + 2797 .LASF63: + 2798 0262 55534246 .ascii "USBFS_interfaceClass\000" + 2798 535F696E + 2798 74657266 + 2798 61636543 + 2798 6C617373 + 2799 .LASF18: + 2800 0277 68774570 .ascii "hwEpState\000" + 2800 53746174 + 2800 6500 + 2801 .LASF15: + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 68 + + + 2802 0281 73697A65 .ascii "sizetype\000" + 2802 74797065 + 2802 00 + 2803 .LASF44: + 2804 028a 55534246 .ascii "USBFS_HandleOUT\000" + 2804 535F4861 + 2804 6E646C65 + 2804 4F555400 + 2805 .LASF68: + 2806 029a 55534246 .ascii "USBFS_ep0Mode\000" + 2806 535F6570 + 2806 304D6F64 + 2806 6500 + 2807 .LASF16: + 2808 02a8 61747472 .ascii "attrib\000" + 2808 696200 + 2809 .LASF69: + 2810 02af 55534246 .ascii "USBFS_ep0Count\000" + 2810 535F6570 + 2810 30436F75 + 2810 6E7400 + 2811 .LASF28: + 2812 02be 545F5553 .ascii "T_USBFS_XFER_STATUS_BLOCK\000" + 2812 4246535F + 2812 58464552 + 2812 5F535441 + 2812 5455535F + 2813 .LASF51: + 2814 02d8 55534246 .ascii "USBFS_InitControlWrite\000" + 2814 535F496E + 2814 6974436F + 2814 6E74726F + 2814 6C577269 + 2815 .LASF11: + 2816 02ef 666C6F61 .ascii "float\000" + 2816 7400 + 2817 .LASF17: + 2818 02f5 61706945 .ascii "apiEpState\000" + 2818 70537461 + 2818 746500 + 2819 .LASF64: + 2820 0300 55534246 .ascii "USBFS_EP\000" + 2820 535F4550 + 2820 00 + 2821 .LASF74: + 2822 0309 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" + 2822 4320342E + 2822 372E3320 + 2822 32303133 + 2822 30333132 + 2823 033c 616E6368 .ascii "anch revision 196615]\000" + 2823 20726576 + 2823 6973696F + 2823 6E203139 + 2823 36363135 + 2824 .LASF14: + 2825 0352 72656738 .ascii "reg8\000" + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 69 + + + 2825 00 + 2826 .LASF54: + 2827 0357 55534246 .ascii "USBFS_transferState\000" + 2827 535F7472 + 2827 616E7366 + 2827 65725374 + 2827 61746500 + 2828 .LASF1: + 2829 036b 756E7369 .ascii "unsigned char\000" + 2829 676E6564 + 2829 20636861 + 2829 7200 + 2830 .LASF79: + 2831 0379 55534246 .ascii "USBFS_InitializeStatusBlock\000" + 2831 535F496E + 2831 69746961 + 2831 6C697A65 + 2831 53746174 + 2832 .LASF2: + 2833 0395 73686F72 .ascii "short int\000" + 2833 7420696E + 2833 7400 + 2834 .LASF32: + 2835 039f 545F5553 .ascii "T_USBFS_TD\000" + 2835 4246535F + 2835 544400 + 2836 .LASF67: + 2837 03aa 55534246 .ascii "USBFS_lastPacketSize\000" + 2837 535F6C61 + 2837 73745061 + 2837 636B6574 + 2837 53697A65 + 2838 .LASF59: + 2839 03bf 55534246 .ascii "USBFS_interfaceSetting\000" + 2839 535F696E + 2839 74657266 + 2839 61636553 + 2839 65747469 + 2840 .LASF25: + 2841 03d6 545F5553 .ascii "T_USBFS_EP_CTL_BLOCK\000" + 2841 4246535F + 2841 45505F43 + 2841 544C5F42 + 2841 4C4F434B + 2842 .LASF40: + 2843 03eb 55534246 .ascii "USBFS_NoDataControlStatusStage\000" + 2843 535F4E6F + 2843 44617461 + 2843 436F6E74 + 2843 726F6C53 + 2844 .LASF38: + 2845 040a 55534246 .ascii "USBFS_InitNoDataControlTransfer\000" + 2845 535F496E + 2845 69744E6F + 2845 44617461 + 2845 436F6E74 + 2846 .LASF53: + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 70 + + + 2847 042a 55534246 .ascii "USBFS_device\000" + 2847 535F6465 + 2847 76696365 + 2847 00 + 2848 .LASF66: + 2849 0437 55534246 .ascii "USBFS_ep0Toggle\000" + 2849 535F6570 + 2849 30546F67 + 2849 676C6500 + 2850 .LASF34: + 2851 0447 55534246 .ascii "USBFS_ControlWriteDataStage\000" + 2851 535F436F + 2851 6E74726F + 2851 6C577269 + 2851 74654461 + 2852 .LASF27: + 2853 0463 6C656E67 .ascii "length\000" + 2853 746800 + 2854 .LASF13: + 2855 046a 63686172 .ascii "char\000" + 2855 00 + 2856 .LASF23: + 2857 046f 62756666 .ascii "bufferSize\000" + 2857 65725369 + 2857 7A6500 + 2858 .LASF46: + 2859 047a 72657175 .ascii "requestHandled\000" + 2859 65737448 + 2859 616E646C + 2859 656400 + 2860 .LASF22: + 2861 0489 62756666 .ascii "buffOffset\000" + 2861 4F666673 + 2861 657400 + 2862 .LASF57: + 2863 0494 55534246 .ascii "USBFS_deviceStatus\000" + 2863 535F6465 + 2863 76696365 + 2863 53746174 + 2863 757300 + 2864 .LASF60: + 2865 04a7 55534246 .ascii "USBFS_interfaceSetting_last\000" + 2865 535F696E + 2865 74657266 + 2865 61636553 + 2865 65747469 + 2866 .LASF49: + 2867 04c3 6D6F6469 .ascii "modifyReg\000" + 2867 66795265 + 2867 6700 + 2868 .LASF45: + 2869 04cd 55534246 .ascii "USBFS_HandleSetup\000" + 2869 535F4861 + 2869 6E646C65 + 2869 53657475 + 2869 7000 + 2870 .LASF26: + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 71 + + + 2871 04df 73746174 .ascii "status\000" + 2871 757300 + 2872 .LASF72: + 2873 04e6 55534246 .ascii "USBFS_DispatchClassRqst\000" + 2873 535F4469 + 2873 73706174 + 2873 6368436C + 2873 61737352 + 2874 .LASF50: + 2875 04fe 78666572 .ascii "xferCount\000" + 2875 436F756E + 2875 7400 + 2876 .LASF62: + 2877 0508 55534246 .ascii "USBFS_interfaceStatus\000" + 2877 535F696E + 2877 74657266 + 2877 61636553 + 2877 74617475 + 2878 .LASF71: + 2879 051e 55534246 .ascii "USBFS_HandleStandardRqst\000" + 2879 535F4861 + 2879 6E646C65 + 2879 5374616E + 2879 64617264 + 2880 .LASF37: + 2881 0537 55534246 .ascii "USBFS_InitZeroLengthControlTransfer\000" + 2881 535F496E + 2881 69745A65 + 2881 726F4C65 + 2881 6E677468 + 2882 .LASF41: + 2883 055b 55534246 .ascii "USBFS_ControlWriteStatusStage\000" + 2883 535F436F + 2883 6E74726F + 2883 6C577269 + 2883 74655374 + 2884 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_drv.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_drv.o index fedff10b8a2f8e9c4e4a41bcf4187b65e506b8a4..789579ad707e366aae935e1d8e1a614bc79a57b7 100755 GIT binary patch delta 1043 zcmZ8fT}YE*6n@Y5v+vu~D5h)vZn`aN8>Le*L%UHaiC8$p3ymoMsHjCLGBeDwi^9k} zvnZ&pEVH6)*iC;I;YCmvMMa?yR0gr40;L};I%mroeHYL7KF@j1bI#sxZ$mSo0XuY$ zA%rNDFsNkp>>w^l>QL;ZJpf{g`kLyJqFrL9tLK>MS{uD&McuZmoojtm zQ=(jHC?HhKd~96Js3@N#?oe#p5Bhe6>a{%J^Dx!bAVXKoskwW}YDktt739@Mh{*f6 zE;)oY%d9)jKiKfAE>95O6R!%U%34CL4LlhTiZfL+V z!YORl)z>6S`o$p0F_-;Md#tX(G>pkwZ4XT9k zG<7$fGcV#7<5H{6a_*D=i(9eKd+O%;wqNkUu5XR~pKRm=C!Wo<PMM0aKiuvnhsGogN6` tOQ(aBpU!-B+A2g5KF&5{xoaU_HtHY@<5|K~oFJ@=d~|)a{07VzzW@LL delta 1032 zcmZ8fT}YE*6n@Y5z2DC^*AKcm|Jrn$);7}oBO{B@qCXgw68+glW(t~K6tyy}oJ1Fu zcuWzZtBfd(bkvpICDBD)MBbzXm0d_i1%(;~owH?)cJX}g^PK0L=e*y(Z;|Opw+EU> za;v0mUJ(L*2qDSN#=*2-`u?lb~zWYtsDNF{lVej@5w zt}9+)OfzdwFfbahR9n^2L^kz&Leq@XG+Dh6ALZ4JI%XFW%rrvW-I;J&g&e1RHTsA~ z>r(A*;j|a*?^#US%?uOWijc$H-n*52v|Zml_S=QPDXkQ);&R;?nj{HIfKZ5D-uRq= zd15vjbwU~N-1sjA@^Oz|0p)l_&roa%-qAf-3$zYgQ~tU_WaSA~7{T{?0AAw~BLLg6 zg77ES8#~||1CymO?G1?XS>)ce{mPCv4)h-3LdtGI`Y{QNFF@EBZJAxWe#7RtlVU!Fj+}s zrReUzYq`O$(T6w^f9K$a2?~;!@qC}YqXv)b}4%HDOj(c!~%haIcZX0WbsX{^~X zMDH@@%2=;K6l+(6VGIWer|~=CEN*s(Aq}q+mf{D(YAo}Fp&q*k+i`;M2KsZu@B~j1 z&f+*>8andWd6cjQ9}>2s<_*IT)_PAt2%pn=3UhosrzMV$eL-l%8J`!9pxs}fy>bar hf^TzDai@P7n0UxvKpS-tMsb)>;sjxJ?3aJe`5U|bx8(o; diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_episr.lst b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_episr.lst index 9a7fd8dd..bca12e6b 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_episr.lst +++ b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_episr.lst @@ -1,4 +1,4 @@ -ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 +ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 1 1 .syntax unified @@ -58,7 +58,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 29:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#END` */ 30:.\Generated_Source\PSoC5/USBFS_episr.c **** 31:.\Generated_Source\PSoC5/USBFS_episr.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 2 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 2 32:.\Generated_Source\PSoC5/USBFS_episr.c **** #if(USBFS_EP1_ISR_REMOVE == 0u) @@ -118,7 +118,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 69:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_EP[USBFS_EP1].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; 43 .loc 1 69 0 44 0010 C37B ldrb r3, [r0, #15] @ zero_extendqisi2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 3 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 3 45 0012 83F08002 eor r2, r3, #128 @@ -178,7 +178,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 95:.\Generated_Source\PSoC5/USBFS_episr.c **** 96:.\Generated_Source\PSoC5/USBFS_episr.c **** /******************************************************************************* 97:.\Generated_Source\PSoC5/USBFS_episr.c **** * Function Name: USBFS_EP_2_ISR - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 4 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 4 98:.\Generated_Source\PSoC5/USBFS_episr.c **** ******************************************************************************** @@ -238,7 +238,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 94 .L10: 131:.\Generated_Source\PSoC5/USBFS_episr.c **** } 132:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_EP[USBFS_EP2].apiEpState = USBFS_EVENT_PENDING; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 5 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 5 95 .loc 1 132 0 @@ -298,7 +298,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 161:.\Generated_Source\PSoC5/USBFS_episr.c **** * Summary: 162:.\Generated_Source\PSoC5/USBFS_episr.c **** * Endpoint 3 Interrupt Service Routine 163:.\Generated_Source\PSoC5/USBFS_episr.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 6 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 6 164:.\Generated_Source\PSoC5/USBFS_episr.c **** * Parameters: @@ -358,7 +358,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 218:.\Generated_Source\PSoC5/USBFS_episr.c **** /******************************************************************************* 219:.\Generated_Source\PSoC5/USBFS_episr.c **** * Function Name: USBFS_EP_4_ISR 220:.\Generated_Source\PSoC5/USBFS_episr.c **** ******************************************************************************** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 7 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 7 221:.\Generated_Source\PSoC5/USBFS_episr.c **** * @@ -418,7 +418,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 275:.\Generated_Source\PSoC5/USBFS_episr.c **** 276:.\Generated_Source\PSoC5/USBFS_episr.c **** 277:.\Generated_Source\PSoC5/USBFS_episr.c **** #if(USBFS_EP5_ISR_REMOVE == 0u) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 8 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 8 278:.\Generated_Source\PSoC5/USBFS_episr.c **** @@ -478,7 +478,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 332:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ 333:.\Generated_Source\PSoC5/USBFS_episr.c **** } 334:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* End USBFS_EP5_ISR_REMOVE */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 9 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 9 335:.\Generated_Source\PSoC5/USBFS_episr.c **** @@ -538,7 +538,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 389:.\Generated_Source\PSoC5/USBFS_episr.c **** 390:.\Generated_Source\PSoC5/USBFS_episr.c **** #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) 391:.\Generated_Source\PSoC5/USBFS_episr.c **** EA = int_en; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 10 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 10 392:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ @@ -598,7 +598,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 446:.\Generated_Source\PSoC5/USBFS_episr.c **** 447:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#START EP7_END_USER_CODE` Place your code here */ 448:.\Generated_Source\PSoC5/USBFS_episr.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 11 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 11 449:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#END` */ @@ -658,7 +658,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 503:.\Generated_Source\PSoC5/USBFS_episr.c **** { 504:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_MIDI_OUT_EP_Service(); 505:.\Generated_Source\PSoC5/USBFS_episr.c **** } - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 12 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 12 506:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */ @@ -718,7 +718,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 543:.\Generated_Source\PSoC5/USBFS_episr.c **** * Function Name: USBFS_BUS_RESET_ISR 544:.\Generated_Source\PSoC5/USBFS_episr.c **** ******************************************************************************** 545:.\Generated_Source\PSoC5/USBFS_episr.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 13 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 13 546:.\Generated_Source\PSoC5/USBFS_episr.c **** * Summary: @@ -765,10 +765,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 159 0006 00000000 .4byte .Ldebug_abbrev0 160 000a 04 .byte 0x4 161 000b 01 .uleb128 0x1 - 162 000c 6F010000 .4byte .LASF29 + 162 000c A0010000 .4byte .LASF29 163 0010 01 .byte 0x1 164 0011 6F000000 .4byte .LASF30 - 165 0015 B8010000 .4byte .LASF31 + 165 0015 AD000000 .4byte .LASF31 166 0019 00000000 .4byte .Ldebug_ranges0+0 167 001d 00000000 .4byte 0 168 0021 00000000 .4byte 0 @@ -776,9 +776,9 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 170 0029 02 .uleb128 0x2 171 002a 01 .byte 0x1 172 002b 06 .byte 0x6 - 173 002c FA010000 .4byte .LASF0 + 173 002c 0B020000 .4byte .LASF0 174 0030 02 .uleb128 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 14 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 14 175 0031 01 .byte 0x1 @@ -787,7 +787,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 178 0037 02 .uleb128 0x2 179 0038 02 .byte 0x2 180 0039 05 .byte 0x5 - 181 003a 5F010000 .4byte .LASF2 + 181 003a 90010000 .4byte .LASF2 182 003e 02 .uleb128 0x2 183 003f 02 .byte 0x2 184 0040 07 .byte 0x7 @@ -795,7 +795,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 186 0045 02 .uleb128 0x2 187 0046 04 .byte 0x4 188 0047 05 .byte 0x5 - 189 0048 E2010000 .4byte .LASF4 + 189 0048 F3010000 .4byte .LASF4 190 004c 02 .uleb128 0x2 191 004d 04 .byte 0x4 192 004e 07 .byte 0x7 @@ -803,11 +803,11 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 194 0053 02 .uleb128 0x2 195 0054 08 .byte 0x8 196 0055 05 .byte 0x5 - 197 0056 41010000 .4byte .LASF6 + 197 0056 72010000 .4byte .LASF6 198 005a 02 .uleb128 0x2 199 005b 08 .byte 0x8 200 005c 07 .byte 0x7 - 201 005d 01010000 .4byte .LASF7 + 201 005d 32010000 .4byte .LASF7 202 0061 03 .uleb128 0x3 203 0062 04 .byte 0x4 204 0063 05 .byte 0x5 @@ -815,14 +815,14 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 206 0068 02 .uleb128 0x2 207 0069 04 .byte 0x4 208 006a 07 .byte 0x7 - 209 006b F4000000 .4byte .LASF8 + 209 006b 25010000 .4byte .LASF8 210 006f 04 .uleb128 0x4 - 211 0070 69010000 .4byte .LASF9 + 211 0070 9A010000 .4byte .LASF9 212 0074 02 .byte 0x2 213 0075 5B .byte 0x5b 214 0076 30000000 .4byte 0x30 215 007a 04 .uleb128 0x4 - 216 007b E2000000 .4byte .LASF10 + 216 007b 13010000 .4byte .LASF10 217 007f 02 .byte 0x2 218 0080 5C .byte 0x5c 219 0081 3E000000 .4byte 0x3e @@ -833,12 +833,12 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 224 008c 02 .uleb128 0x2 225 008d 08 .byte 0x8 226 008e 04 .byte 0x4 - 227 008f C9000000 .4byte .LASF12 + 227 008f FA000000 .4byte .LASF12 228 0093 02 .uleb128 0x2 229 0094 01 .byte 0x1 230 0095 08 .byte 0x8 - 231 0096 4F010000 .4byte .LASF13 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 15 + 231 0096 80010000 .4byte .LASF13 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 15 232 009a 04 .uleb128 0x4 @@ -851,14 +851,14 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 239 00aa 02 .uleb128 0x2 240 00ab 04 .byte 0x4 241 00ac 07 .byte 0x7 - 242 00ad 31010000 .4byte .LASF15 + 242 00ad 62010000 .4byte .LASF15 243 00b1 06 .uleb128 0x6 244 00b2 0C .byte 0xc 245 00b3 03 .byte 0x3 246 00b4 79 .byte 0x79 247 00b5 38010000 .4byte 0x138 248 00b9 07 .uleb128 0x7 - 249 00ba D0000000 .4byte .LASF16 + 249 00ba 01010000 .4byte .LASF16 250 00be 03 .byte 0x3 251 00bf 7B .byte 0x7b 252 00c0 6F000000 .4byte 0x6f @@ -866,7 +866,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 254 00c5 23 .byte 0x23 255 00c6 00 .uleb128 0 256 00c7 07 .uleb128 0x7 - 257 00c8 E9000000 .4byte .LASF17 + 257 00c8 1A010000 .4byte .LASF17 258 00cc 03 .byte 0x3 259 00cd 7C .byte 0x7c 260 00ce 6F000000 .4byte 0x6f @@ -874,7 +874,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 262 00d3 23 .byte 0x23 263 00d4 01 .uleb128 0x1 264 00d5 07 .uleb128 0x7 - 265 00d6 18010000 .4byte .LASF18 + 265 00d6 49010000 .4byte .LASF18 266 00da 03 .byte 0x3 267 00db 7D .byte 0x7d 268 00dc 6F000000 .4byte 0x6f @@ -890,7 +890,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 278 00ef 23 .byte 0x23 279 00f0 03 .uleb128 0x3 280 00f1 07 .uleb128 0x7 - 281 00f2 AD000000 .4byte .LASF20 + 281 00f2 DE000000 .4byte .LASF20 282 00f6 03 .byte 0x3 283 00f7 7F .byte 0x7f 284 00f8 6F000000 .4byte 0x6f @@ -898,10 +898,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 286 00fd 23 .byte 0x23 287 00fe 04 .uleb128 0x4 288 00ff 07 .uleb128 0x7 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 16 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 16 - 289 0100 3A010000 .4byte .LASF21 + 289 0100 6B010000 .4byte .LASF21 290 0104 03 .byte 0x3 291 0105 80 .byte 0x80 292 0106 6F000000 .4byte 0x6f @@ -909,7 +909,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 294 010b 23 .byte 0x23 295 010c 05 .uleb128 0x5 296 010d 07 .uleb128 0x7 - 297 010e D7000000 .4byte .LASF22 + 297 010e 08010000 .4byte .LASF22 298 0112 03 .byte 0x3 299 0113 81 .byte 0x81 300 0114 7A000000 .4byte 0x7a @@ -917,7 +917,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 302 0119 23 .byte 0x23 303 011a 06 .uleb128 0x6 304 011b 07 .uleb128 0x7 - 305 011c 54010000 .4byte .LASF23 + 305 011c 85010000 .4byte .LASF23 306 0120 03 .byte 0x3 307 0121 82 .byte 0x82 308 0122 7A000000 .4byte 0x7a @@ -925,7 +925,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 310 0127 23 .byte 0x23 311 0128 08 .uleb128 0x8 312 0129 07 .uleb128 0x7 - 313 012a D8010000 .4byte .LASF24 + 313 012a E9010000 .4byte .LASF24 314 012e 03 .byte 0x3 315 012f 83 .byte 0x83 316 0130 6F000000 .4byte 0x6f @@ -940,7 +940,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 325 013f B1000000 .4byte 0xb1 326 0143 08 .uleb128 0x8 327 0144 01 .byte 0x1 - 328 0145 22010000 .4byte .LASF26 + 328 0145 53010000 .4byte .LASF26 329 0149 01 .byte 0x1 330 014a 31 .byte 0x31 331 014b 01 .byte 0x1 @@ -952,13 +952,13 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 337 0157 01 .byte 0x1 338 0158 08 .uleb128 0x8 339 0159 01 .byte 0x1 - 340 015a EB010000 .4byte .LASF27 + 340 015a FC010000 .4byte .LASF27 341 015e 01 .byte 0x1 342 015f 6E .byte 0x6e 343 0160 01 .byte 0x1 344 0161 00000000 .4byte .LFB1 345 0165 34000000 .4byte .LFE1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 17 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 17 346 0169 02 .byte 0x2 @@ -967,7 +967,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 349 016c 01 .byte 0x1 350 016d 09 .uleb128 0x9 351 016e 01 .byte 0x1 - 352 016f B2000000 .4byte .LASF28 + 352 016f E3000000 .4byte .LASF28 353 0173 01 .byte 0x1 354 0174 1602 .2byte 0x216 355 0176 01 .byte 0x1 @@ -1003,7 +1003,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 385 01b6 08 .byte 0x8 386 01b7 00 .byte 0 387 01b8 0E .uleb128 0xe - 388 01b9 C0000000 .4byte .LASF33 + 388 01b9 F1000000 .4byte .LASF33 389 01bd 04 .byte 0x4 390 01be 3F .byte 0x3f 391 01bf C5010000 .4byte 0x1c5 @@ -1018,7 +1018,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 400 01d1 51 .byte 0x51 401 01d2 01 .byte 0x1 402 01d3 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 18 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 18 403 01d4 00 .byte 0 @@ -1078,7 +1078,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 457 0033 0B .uleb128 0xb 458 0034 49 .uleb128 0x49 459 0035 13 .uleb128 0x13 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 19 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 19 460 0036 00 .byte 0 @@ -1138,7 +1138,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 514 006c 40 .uleb128 0x40 515 006d 0A .uleb128 0xa 516 006e 9742 .uleb128 0x2117 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 20 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 20 517 0070 0C .uleb128 0xc @@ -1198,7 +1198,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 571 00aa 11 .uleb128 0x11 572 00ab 01 .uleb128 0x1 573 00ac 9542 .uleb128 0x2115 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 21 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 21 574 00ae 0C .uleb128 0xc @@ -1258,7 +1258,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 628 00e4 0C .uleb128 0xc 629 00e5 00 .byte 0 630 00e6 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 22 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 22 631 00e7 00 .byte 0 @@ -1318,7 +1318,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 670 544C5F42 670 4C4F434B 671 .LASF32: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 23 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 23 672 003e 55534246 .ascii "USBFS_BUS_RESET_ISR\000" @@ -1353,119 +1353,120 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 1 684 69676E65 684 6420696E 684 7400 - 685 .LASF20: - 686 00ad 61646472 .ascii "addr\000" - 686 00 - 687 .LASF28: - 688 00b2 55534246 .ascii "USBFS_SOF_ISR\000" - 688 535F534F - 688 465F4953 - 688 5200 - 689 .LASF33: - 690 00c0 55534246 .ascii "USBFS_EP\000" - 690 535F4550 - 690 00 - 691 .LASF12: - 692 00c9 646F7562 .ascii "double\000" - 692 6C6500 - 693 .LASF16: - 694 00d0 61747472 .ascii "attrib\000" - 694 696200 - 695 .LASF22: - 696 00d7 62756666 .ascii "buffOffset\000" - 696 4F666673 - 696 657400 - 697 .LASF10: - 698 00e2 75696E74 .ascii "uint16\000" - 698 313600 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 24 + 685 .LASF31: + 686 00ad 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" + 686 43534932 + 686 53445C73 + 686 6F667477 + 686 6172655C + 687 00dc 6E00 .ascii "n\000" + 688 .LASF20: + 689 00de 61646472 .ascii "addr\000" + 689 00 + 690 .LASF28: + 691 00e3 55534246 .ascii "USBFS_SOF_ISR\000" + 691 535F534F + 691 465F4953 + 691 5200 + 692 .LASF33: + 693 00f1 55534246 .ascii "USBFS_EP\000" + 693 535F4550 + 693 00 + 694 .LASF12: + 695 00fa 646F7562 .ascii "double\000" + 695 6C6500 + 696 .LASF16: + 697 0101 61747472 .ascii "attrib\000" + 697 696200 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 24 - 699 .LASF17: - 700 00e9 61706945 .ascii "apiEpState\000" - 700 70537461 - 700 746500 - 701 .LASF8: - 702 00f4 756E7369 .ascii "unsigned int\000" - 702 676E6564 - 702 20696E74 - 702 00 - 703 .LASF7: - 704 0101 6C6F6E67 .ascii "long long unsigned int\000" - 704 206C6F6E - 704 6720756E - 704 7369676E - 704 65642069 - 705 .LASF18: - 706 0118 68774570 .ascii "hwEpState\000" - 706 53746174 - 706 6500 - 707 .LASF26: - 708 0122 55534246 .ascii "USBFS_EP_1_ISR\000" - 708 535F4550 - 708 5F315F49 - 708 535200 - 709 .LASF15: - 710 0131 73697A65 .ascii "sizetype\000" - 710 74797065 - 710 00 - 711 .LASF21: - 712 013a 65704D6F .ascii "epMode\000" - 712 646500 - 713 .LASF6: - 714 0141 6C6F6E67 .ascii "long long int\000" - 714 206C6F6E - 714 6720696E - 714 7400 - 715 .LASF13: - 716 014f 63686172 .ascii "char\000" - 716 00 - 717 .LASF23: - 718 0154 62756666 .ascii "bufferSize\000" - 718 65725369 - 718 7A6500 - 719 .LASF2: - 720 015f 73686F72 .ascii "short int\000" - 720 7420696E - 720 7400 - 721 .LASF9: - 722 0169 75696E74 .ascii "uint8\000" - 722 3800 - 723 .LASF29: - 724 016f 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 724 4320342E - 724 372E3320 - 724 32303133 - 724 30333132 - 725 01a2 616E6368 .ascii "anch revision 196615]\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccP1x52T.s page 25 + 698 .LASF22: + 699 0108 62756666 .ascii "buffOffset\000" + 699 4F666673 + 699 657400 + 700 .LASF10: + 701 0113 75696E74 .ascii "uint16\000" + 701 313600 + 702 .LASF17: + 703 011a 61706945 .ascii "apiEpState\000" + 703 70537461 + 703 746500 + 704 .LASF8: + 705 0125 756E7369 .ascii "unsigned int\000" + 705 676E6564 + 705 20696E74 + 705 00 + 706 .LASF7: + 707 0132 6C6F6E67 .ascii "long long unsigned int\000" + 707 206C6F6E + 707 6720756E + 707 7369676E + 707 65642069 + 708 .LASF18: + 709 0149 68774570 .ascii "hwEpState\000" + 709 53746174 + 709 6500 + 710 .LASF26: + 711 0153 55534246 .ascii "USBFS_EP_1_ISR\000" + 711 535F4550 + 711 5F315F49 + 711 535200 + 712 .LASF15: + 713 0162 73697A65 .ascii "sizetype\000" + 713 74797065 + 713 00 + 714 .LASF21: + 715 016b 65704D6F .ascii "epMode\000" + 715 646500 + 716 .LASF6: + 717 0172 6C6F6E67 .ascii "long long int\000" + 717 206C6F6E + 717 6720696E + 717 7400 + 718 .LASF13: + 719 0180 63686172 .ascii "char\000" + 719 00 + 720 .LASF23: + 721 0185 62756666 .ascii "bufferSize\000" + 721 65725369 + 721 7A6500 + 722 .LASF2: + 723 0190 73686F72 .ascii "short int\000" + 723 7420696E + 723 7400 + 724 .LASF9: + 725 019a 75696E74 .ascii "uint8\000" + 725 3800 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 25 - 725 20726576 - 725 6973696F - 725 6E203139 - 725 36363135 - 726 .LASF31: - 727 01b8 573A5C53 .ascii "W:\\SCSI2SD\\USB_Bootloader.cydsn\000" - 727 43534932 - 727 53445C55 - 727 53425F42 - 727 6F6F746C - 728 .LASF24: - 729 01d8 696E7465 .ascii "interface\000" - 729 72666163 - 729 6500 - 730 .LASF4: - 731 01e2 6C6F6E67 .ascii "long int\000" - 731 20696E74 - 731 00 - 732 .LASF27: - 733 01eb 55534246 .ascii "USBFS_EP_2_ISR\000" - 733 535F4550 - 733 5F325F49 - 733 535200 - 734 .LASF0: - 735 01fa 7369676E .ascii "signed char\000" - 735 65642063 - 735 68617200 - 736 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br + 726 .LASF29: + 727 01a0 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" + 727 4320342E + 727 372E3320 + 727 32303133 + 727 30333132 + 728 01d3 616E6368 .ascii "anch revision 196615]\000" + 728 20726576 + 728 6973696F + 728 6E203139 + 728 36363135 + 729 .LASF24: + 730 01e9 696E7465 .ascii "interface\000" + 730 72666163 + 730 6500 + 731 .LASF4: + 732 01f3 6C6F6E67 .ascii "long int\000" + 732 20696E74 + 732 00 + 733 .LASF27: + 734 01fc 55534246 .ascii "USBFS_EP_2_ISR\000" + 734 535F4550 + 734 5F325F49 + 734 535200 + 735 .LASF0: + 736 020b 7369676E .ascii "signed char\000" + 736 65642063 + 736 68617200 + 737 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_episr.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_episr.o index 453e72bac765514d6de32738a009130cc025de44..9995c86fe65c4aa77f3dd967aa00865e617c5897 100755 GIT binary patch delta 461 zcmY+8PbkA-7{}k|-TV8!@AmsCSy5BkTI_%@6hey24qDlPvV$oi*)*$}KN+=~)$|la zisGo$uiTWYgM)VF;^d%+gG70s?d0-2-_Q5?e(Sjk-Uds4INuKxJ*U7Jq!?qDc&5DD z988Nd#z7^t$GK6`cg|%!kuW}pgghovMw&>;uwE`(E-rS?!y)E7zyD1U+0E^dS#2=_A^#637VVpt1i+-(1^O zPsk-oEezt29n!ryJ@>F^hq$Q0Yr6$L JokzPY{s0_HQv(11 delta 460 zcmZ9GPbfrD6vpql@7{Oc^PUnVQNk;;7z+~%hGfb{(M(d5@ozaBENB`={w(Yi9c*N2 zspM@et(1kLSztR^kd(!gQp!2rio5vE`F-Cx_ui}EJlJc2gZ@Ttcm=Ghh zqHY+$Nz<4*;{M~5RP(RsiUirVZxwo|nmh8WwcjKV=9Q@!5ts%nKvVA-dmE9bOp=zY z&4{#l;B0G^R0g&g=WIJ7$2{UKG{)P=1AbA6ZXR0~;J_Q33x7-(F0fV(!&R7-_cEN( z9>|F#4(evi*`=`0q$Et@x|@bMymj+fbbZWJ4Z#u~R^{OZtGzVT;52Cl&%8L;_~Zq! qgWq0Ef7(KHVZyD$e!m7faMX{{-U?|EPyCpy_;~HN!*lrVm(&mMCQpp_list; 390:.\Generated_Source\PSoC5/USBFS_hid.c **** /* Validate reportType to comply with "7.2.1 Get_Report Request" */ 391:.\Generated_Source\PSoC5/USBFS_hid.c **** if((reportType >= USBFS_HID_GET_REPORT_INPUT) && - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 13 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 13 284 .loc 1 391 0 @@ -778,7 +778,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 402:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_currentTD.pData = pTD->pData; /* Buffer pointer */ 323 .loc 1 402 0 324 004e 5868 ldr r0, [r3, #4] - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 14 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 14 325 .LVL39: @@ -838,7 +838,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 372 0004 3A4A ldr r2, .L57+4 124:.\Generated_Source\PSoC5/USBFS_hid.c **** interfaceNumber = CY_GET_REG8(USBFS_wIndexLo); 373 .loc 1 124 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 15 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 15 374 0006 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 @@ -898,7 +898,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 152:.\Generated_Source\PSoC5/USBFS_hid.c **** if (USBFS_currentTD.count != 0u) 421 .loc 1 152 0 422 0040 2D49 ldr r1, .L57+12 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 16 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 16 423 0042 0B88 ldrh r3, [r1, #0] @@ -958,7 +958,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 465 .loc 1 174 0 466 0074 2349 ldr r1, .L57+24 467 0076 F3E7 b .L52 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 17 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 17 468 .LVL52: @@ -1018,7 +1018,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 512 00b4 124A ldr r2, .L57+20 513 00b6 1370 strb r3, [r2, #0] 207:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_hidIdleTimer[interfaceNumber]) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 18 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 18 514 .loc 1 207 0 @@ -1078,7 +1078,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 555 00e6 F2E7 b .L50 556 .L23: 557 .LVL58: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 19 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 19 250:.\Generated_Source\PSoC5/USBFS_hid.c **** } @@ -1115,10 +1115,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 588 0006 00000000 .4byte .Ldebug_abbrev0 589 000a 04 .byte 0x4 590 000b 01 .uleb128 0x1 - 591 000c 84020000 .4byte .LASF48 + 591 000c B5020000 .4byte .LASF48 592 0010 01 .byte 0x1 593 0011 0D000000 .4byte .LASF49 - 594 0015 CD020000 .4byte .LASF50 + 594 0015 1D010000 .4byte .LASF50 595 0019 00000000 .4byte .Ldebug_ranges0+0 596 001d 00000000 .4byte 0 597 0021 00000000 .4byte 0 @@ -1126,7 +1126,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 599 0029 02 .uleb128 0x2 600 002a 01 .byte 0x1 601 002b 06 .byte 0x6 - 602 002c 00030000 .4byte .LASF0 + 602 002c 11030000 .4byte .LASF0 603 0030 02 .uleb128 0x2 604 0031 01 .byte 0x1 605 0032 08 .byte 0x8 @@ -1134,18 +1134,18 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 607 0037 02 .uleb128 0x2 608 0038 02 .byte 0x2 609 0039 05 .byte 0x5 - 610 003a 81010000 .4byte .LASF2 + 610 003a B2010000 .4byte .LASF2 611 003e 02 .uleb128 0x2 612 003f 02 .byte 0x2 613 0040 07 .byte 0x7 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 20 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 20 614 0041 67000000 .4byte .LASF3 615 0045 02 .uleb128 0x2 616 0046 04 .byte 0x4 617 0047 05 .byte 0x5 - 618 0048 F7020000 .4byte .LASF4 + 618 0048 08030000 .4byte .LASF4 619 004c 02 .uleb128 0x2 620 004d 04 .byte 0x4 621 004e 07 .byte 0x7 @@ -1153,11 +1153,11 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 623 0053 02 .uleb128 0x2 624 0054 08 .byte 0x8 625 0055 05 .byte 0x5 - 626 0056 22020000 .4byte .LASF6 + 626 0056 53020000 .4byte .LASF6 627 005a 02 .uleb128 0x2 628 005b 08 .byte 0x8 629 005c 07 .byte 0x7 - 630 005d D9010000 .4byte .LASF7 + 630 005d 0A020000 .4byte .LASF7 631 0061 03 .uleb128 0x3 632 0062 04 .byte 0x4 633 0063 05 .byte 0x5 @@ -1165,14 +1165,14 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 635 0068 02 .uleb128 0x2 636 0069 04 .byte 0x4 637 006a 07 .byte 0x7 - 638 006b B1010000 .4byte .LASF8 + 638 006b E2010000 .4byte .LASF8 639 006f 04 .uleb128 0x4 - 640 0070 1D010000 .4byte .LASF9 + 640 0070 4E010000 .4byte .LASF9 641 0074 02 .byte 0x2 642 0075 5B .byte 0x5b 643 0076 30000000 .4byte 0x30 644 007a 04 .uleb128 0x4 - 645 007b 8B010000 .4byte .LASF10 + 645 007b BC010000 .4byte .LASF10 646 007f 02 .byte 0x2 647 0080 5C .byte 0x5c 648 0081 3E000000 .4byte 0x3e @@ -1183,11 +1183,11 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 653 008c 02 .uleb128 0x2 654 008d 08 .byte 0x8 655 008e 04 .byte 0x4 - 656 008f 64010000 .4byte .LASF12 + 656 008f 95010000 .4byte .LASF12 657 0093 02 .uleb128 0x2 658 0094 01 .byte 0x1 659 0095 08 .byte 0x8 - 660 0096 3C020000 .4byte .LASF13 + 660 0096 6D020000 .4byte .LASF13 661 009a 04 .uleb128 0x4 662 009b EC000000 .4byte .LASF14 663 009f 02 .byte 0x2 @@ -1198,10 +1198,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 668 00aa 02 .uleb128 0x2 669 00ab 04 .byte 0x4 670 00ac 07 .byte 0x7 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 21 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 21 - 671 00ad 19020000 .4byte .LASF15 + 671 00ad 4A020000 .4byte .LASF15 672 00b1 06 .uleb128 0x6 673 00b2 04 .byte 0x4 674 00b3 03 .byte 0x3 @@ -1216,7 +1216,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 683 00c5 23 .byte 0x23 684 00c6 00 .uleb128 0 685 00c7 07 .uleb128 0x7 - 686 00c8 31030000 .4byte .LASF17 + 686 00c8 42030000 .4byte .LASF17 687 00cc 03 .byte 0x3 688 00cd 93 .byte 0x93 689 00ce 7A000000 .4byte 0x7a @@ -1258,7 +1258,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 725 0110 02 .byte 0x2 726 0111 23 .byte 0x23 727 0112 08 .uleb128 0x8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 22 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 22 728 0113 00 .byte 0 @@ -1287,7 +1287,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 751 013d 23 .byte 0x23 752 013e 00 .uleb128 0 753 013f 07 .uleb128 0x7 - 754 0140 F0010000 .4byte .LASF23 + 754 0140 21020000 .4byte .LASF23 755 0144 03 .byte 0x3 756 0145 A1 .byte 0xa1 757 0146 4E010000 .4byte 0x14e @@ -1300,13 +1300,13 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 764 0150 54010000 .4byte 0x154 765 0154 0A .uleb128 0xa 766 0155 04 .uleb128 0x4 - 767 0156 30020000 .4byte .LASF24 + 767 0156 61020000 .4byte .LASF24 768 015a 03 .byte 0x3 769 015b A2 .byte 0xa2 770 015c 2B010000 .4byte 0x12b 771 0160 0B .uleb128 0xb 772 0161 01 .byte 0x1 - 773 0162 6F020000 .4byte .LASF25 + 773 0162 A0020000 .4byte .LASF25 774 0166 01 .byte 0x1 775 0167 3C .byte 0x3c 776 0168 01 .byte 0x1 @@ -1318,11 +1318,11 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 782 0177 00 .sleb128 0 783 0178 01 .byte 0x1 784 0179 9C010000 .4byte 0x19c - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 23 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 23 785 017d 0C .uleb128 0xc - 786 017e ED020000 .4byte .LASF27 + 786 017e FE020000 .4byte .LASF27 787 0182 01 .byte 0x1 788 0183 3C .byte 0x3c 789 0184 6F000000 .4byte 0x6f @@ -1336,7 +1336,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 797 019b 00 .byte 0 798 019c 0B .uleb128 0xb 799 019d 01 .byte 0x1 - 800 019e 07020000 .4byte .LASF26 + 800 019e 38020000 .4byte .LASF26 801 01a2 01 .byte 0x1 802 01a3 60 .byte 0x60 803 01a4 01 .byte 0x1 @@ -1349,7 +1349,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 810 01b4 01 .byte 0x1 811 01b5 C9010000 .4byte 0x1c9 812 01b9 0C .uleb128 0xc - 813 01ba ED020000 .4byte .LASF27 + 813 01ba FE020000 .4byte .LASF27 814 01be 01 .byte 0x1 815 01bf 60 .byte 0x60 816 01c0 6F000000 .4byte 0x6f @@ -1367,18 +1367,18 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 828 01df 01 .byte 0x1 829 01e0 1C020000 .4byte 0x21c 830 01e4 0F .uleb128 0xf - 831 01e5 41020000 .4byte .LASF29 + 831 01e5 72020000 .4byte .LASF29 832 01e9 01 .byte 0x1 833 01ea 1301 .2byte 0x113 834 01ec 1C020000 .4byte 0x21c 835 01f0 E3000000 .4byte .LLST4 836 01f4 10 .uleb128 0x10 - 837 01f5 AA010000 .4byte .LASF30 + 837 01f5 DB010000 .4byte .LASF30 838 01f9 01 .byte 0x1 839 01fa 1401 .2byte 0x114 840 01fc 14010000 .4byte 0x114 841 0200 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 24 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 24 842 0201 50 .byte 0x50 @@ -1409,13 +1409,13 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 867 023d 01 .byte 0x1 868 023e 7C020000 .4byte 0x27c 869 0242 0F .uleb128 0xf - 870 0243 41020000 .4byte .LASF29 + 870 0243 72020000 .4byte .LASF29 871 0247 01 .byte 0x1 872 0248 4101 .2byte 0x141 873 024a 1C020000 .4byte 0x21c 874 024e 51010000 .4byte .LLST7 875 0252 0F .uleb128 0xf - 876 0253 AA010000 .4byte .LASF30 + 876 0253 DB010000 .4byte .LASF30 877 0257 01 .byte 0x1 878 0258 4201 .2byte 0x142 879 025a 14010000 .4byte 0x114 @@ -1432,20 +1432,20 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 890 027b 00 .byte 0 891 027c 0E .uleb128 0xe 892 027d 01 .byte 0x1 - 893 027e 53010000 .4byte .LASF34 + 893 027e 84010000 .4byte .LASF34 894 0282 01 .byte 0x1 895 0283 6D01 .2byte 0x16d 896 0285 01 .byte 0x1 897 0286 00000000 .4byte .LFB5 898 028a 74000000 .4byte .LFE5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 25 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 25 899 028e B2010000 .4byte .LLST10 900 0292 01 .byte 0x1 901 0293 E1020000 .4byte 0x2e1 902 0297 0F .uleb128 0xf - 903 0298 41020000 .4byte .LASF29 + 903 0298 72020000 .4byte .LASF29 904 029c 01 .byte 0x1 905 029d 6F01 .2byte 0x16f 906 029f 1C020000 .4byte 0x21c @@ -1477,7 +1477,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 932 02e3 20010000 .4byte 0x120 933 02e7 14 .uleb128 0x14 934 02e8 01 .byte 0x1 - 935 02e9 BE010000 .4byte .LASF36 + 935 02e9 EF010000 .4byte .LASF36 936 02ed 01 .byte 0x1 937 02ee 77 .byte 0x77 938 02ef 01 .byte 0x1 @@ -1494,11 +1494,11 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 949 030c 6F000000 .4byte 0x6f 950 0310 77020000 .4byte .LLST16 951 0314 0D .uleb128 0xd - 952 0315 23010000 .4byte .LASF38 + 952 0315 54010000 .4byte .LASF38 953 0319 01 .byte 0x1 954 031a 7A .byte 0x7a 955 031b 6F000000 .4byte 0x6f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 26 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 26 956 031f 8B020000 .4byte .LLST17 @@ -1542,7 +1542,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 994 0382 00 .byte 0 995 0383 00 .byte 0 996 0384 19 .uleb128 0x19 - 997 0385 5D020000 .4byte .LASF40 + 997 0385 8E020000 .4byte .LASF40 998 0389 01 .byte 0x1 999 038a 1D .byte 0x1d 1000 038b 96030000 .4byte 0x396 @@ -1553,12 +1553,12 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 1005 0396 05 .uleb128 0x5 1006 0397 74030000 .4byte 0x374 1007 039b 19 .uleb128 0x19 - 1008 039c 0C030000 .4byte .LASF41 + 1008 039c 1D030000 .4byte .LASF41 1009 03a0 01 .byte 0x1 1010 03a1 1E .byte 0x1e 1011 03a2 AD030000 .4byte 0x3ad 1012 03a6 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 27 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 27 1013 03a7 05 .byte 0x5 @@ -1567,7 +1567,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 1016 03ad 05 .uleb128 0x5 1017 03ae 74030000 .4byte 0x374 1018 03b2 19 .uleb128 0x19 - 1019 03b3 1E030000 .4byte .LASF42 + 1019 03b3 2F030000 .4byte .LASF42 1020 03b7 01 .byte 0x1 1021 03b8 1F .byte 0x1f 1022 03b9 C4030000 .4byte 0x3c4 @@ -1578,7 +1578,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 1027 03c4 05 .uleb128 0x5 1028 03c5 74030000 .4byte 0x374 1029 03c9 1A .uleb128 0x1a - 1030 03ca 46020000 .4byte .LASF43 + 1030 03ca 77020000 .4byte .LASF43 1031 03ce 04 .byte 0x4 1032 03cf 39 .byte 0x39 1033 03d0 D6030000 .4byte 0x3d6 @@ -1587,7 +1587,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 1036 03d6 05 .uleb128 0x5 1037 03d7 74030000 .4byte 0x374 1038 03db 1A .uleb128 0x1a - 1039 03dc F7010000 .4byte .LASF44 + 1039 03dc 28020000 .4byte .LASF44 1040 03e0 04 .byte 0x4 1041 03e1 40 .byte 0x40 1042 03e2 E8030000 .4byte 0x3e8 @@ -1597,7 +1597,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 1046 03e9 20010000 .4byte 0x120 1047 03ed 1B .uleb128 0x1b 1048 03ee 01 .byte 0x1 - 1049 03ef 92010000 .4byte .LASF51 + 1049 03ef C3010000 .4byte .LASF51 1050 03f3 04 .byte 0x4 1051 03f4 6D .byte 0x6d 1052 03f5 01 .byte 0x1 @@ -1609,7 +1609,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 1058 0404 00 .byte 0 1059 0405 1D .uleb128 0x1d 1060 0406 01 .byte 0x1 - 1061 0407 6B010000 .4byte .LASF45 + 1061 0407 9C010000 .4byte .LASF45 1062 040b 04 .byte 0x4 1063 040c 56 .byte 0x56 1064 040d 01 .byte 0x1 @@ -1617,8 +1617,8 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 1066 0412 01 .byte 0x1 1067 0413 1D .uleb128 0x1d 1068 0414 01 .byte 0x1 - 1069 0415 38030000 .4byte .LASF46 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 28 + 1069 0415 49030000 .4byte .LASF46 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 28 1070 0419 04 .byte 0x4 @@ -1628,7 +1628,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 1074 0420 01 .byte 0x1 1075 0421 1D .uleb128 0x1d 1076 0422 01 .byte 0x1 - 1077 0423 33010000 .4byte .LASF47 + 1077 0423 64010000 .4byte .LASF47 1078 0427 04 .byte 0x4 1079 0428 63 .byte 0x63 1080 0429 01 .byte 0x1 @@ -1678,7 +1678,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 1124 0026 0B .uleb128 0xb 1125 0027 03 .uleb128 0x3 1126 0028 08 .uleb128 0x8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 29 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 29 1127 0029 00 .byte 0 @@ -1738,7 +1738,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 1181 005f 0B .uleb128 0xb 1182 0060 49 .uleb128 0x49 1183 0061 13 .uleb128 0x13 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 30 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 30 1184 0062 00 .byte 0 @@ -1798,7 +1798,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 1238 0099 3A .uleb128 0x3a 1239 009a 0B .uleb128 0xb 1240 009b 3B .uleb128 0x3b - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 31 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 31 1241 009c 0B .uleb128 0xb @@ -1858,7 +1858,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 1295 00d3 3B .uleb128 0x3b 1296 00d4 05 .uleb128 0x5 1297 00d5 49 .uleb128 0x49 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 32 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 32 1298 00d6 13 .uleb128 0x13 @@ -1918,7 +1918,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 1352 010e 3F .uleb128 0x3f 1353 010f 0C .uleb128 0xc 1354 0110 03 .uleb128 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 33 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 33 1355 0111 0E .uleb128 0xe @@ -1978,7 +1978,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 1409 014b 01 .uleb128 0x1 1410 014c 13 .uleb128 0x13 1411 014d 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 34 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 34 1412 014e 00 .byte 0 @@ -2038,7 +2038,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 1466 0184 0B .uleb128 0xb 1467 0185 27 .uleb128 0x27 1468 0186 0C .uleb128 0xc - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 35 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 35 1469 0187 49 .uleb128 0x49 @@ -2098,7 +2098,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 1523 0028 20000000 .4byte .LVL6 1524 002c 0400 .2byte 0x4 1525 002e F3 .byte 0xf3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 36 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 36 1526 002f 01 .uleb128 0x1 @@ -2158,7 +2158,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 1580 00b1 0C000000 .4byte .LFE1 1581 00b5 0400 .2byte 0x4 1582 00b7 F3 .byte 0xf3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 37 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 37 1583 00b8 01 .uleb128 0x1 @@ -2218,7 +2218,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 1637 0139 0200 .2byte 0x2 1638 013b 7D .byte 0x7d 1639 013c 00 .sleb128 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 38 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 38 1640 013d 02000000 .4byte .LCFI1 @@ -2278,7 +2278,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 1694 01c2 74000000 .4byte .LFE5 1695 01c6 0200 .2byte 0x2 1696 01c8 7D .byte 0x7d - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 39 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 39 1697 01c9 08 .sleb128 8 @@ -2338,7 +2338,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 1751 0257 00000000 .4byte .LFB2 1752 025b 02000000 .4byte .LCFI3 1753 025f 0200 .2byte 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 40 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 40 1754 0261 7D .byte 0x7d @@ -2398,7 +2398,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 1808 000c 0000 .2byte 0 1809 000e 0000 .2byte 0 1810 0010 00000000 .4byte .LFB0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 41 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 41 1811 0014 2C000000 .4byte .LFE0-.LFB0 @@ -2458,7 +2458,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 1850 656400 1851 .LASF19: 1852 0046 636F756E .ascii "count\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 42 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 42 1852 7400 @@ -2518,7 +2518,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 1877 .LASF18: 1878 00f1 545F5553 .ascii "T_USBFS_XFER_STATUS_BLOCK\000" 1878 4246535F - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 43 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 43 1878 58464552 @@ -2530,176 +2530,177 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 1 1880 69676E65 1880 6420696E 1880 7400 - 1881 .LASF9: - 1882 011d 75696E74 .ascii "uint8\000" - 1882 3800 - 1883 .LASF38: - 1884 0123 696E7465 .ascii "interfaceNumber\000" - 1884 72666163 - 1884 654E756D - 1884 62657200 - 1885 .LASF47: - 1886 0133 55534246 .ascii "USBFS_InitNoDataControlTransfer\000" - 1886 535F496E - 1886 69744E6F - 1886 44617461 - 1886 436F6E74 - 1887 .LASF34: - 1888 0153 55534246 .ascii "USBFS_FindReport\000" - 1888 535F4669 - 1888 6E645265 - 1888 706F7274 - 1888 00 - 1889 .LASF12: - 1890 0164 646F7562 .ascii "double\000" - 1890 6C6500 - 1891 .LASF45: - 1892 016b 55534246 .ascii "USBFS_InitControlRead\000" - 1892 535F496E - 1892 6974436F - 1892 6E74726F - 1892 6C526561 - 1893 .LASF2: - 1894 0181 73686F72 .ascii "short int\000" - 1894 7420696E - 1894 7400 - 1895 .LASF10: - 1896 018b 75696E74 .ascii "uint16\000" - 1896 313600 - 1897 .LASF51: - 1898 0192 55534246 .ascii "USBFS_GetConfigTablePtr\000" - 1898 535F4765 - 1898 74436F6E - 1898 66696754 - 1898 61626C65 - 1899 .LASF30: - 1900 01aa 70446573 .ascii "pDescr\000" - 1900 637200 - 1901 .LASF8: - 1902 01b1 756E7369 .ascii "unsigned int\000" - 1902 676E6564 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 44 - - - 1902 20696E74 - 1902 00 - 1903 .LASF36: - 1904 01be 55534246 .ascii "USBFS_DispatchHIDClassRqst\000" - 1904 535F4469 - 1904 73706174 - 1904 63684849 - 1904 44436C61 - 1905 .LASF7: - 1906 01d9 6C6F6E67 .ascii "long long unsigned int\000" - 1906 206C6F6E - 1906 6720756E - 1906 7369676E - 1906 65642069 - 1907 .LASF23: - 1908 01f0 705F6C69 .ascii "p_list\000" - 1908 737400 - 1909 .LASF44: - 1910 01f7 55534246 .ascii "USBFS_currentTD\000" - 1910 535F6375 - 1910 7272656E - 1910 74544400 - 1911 .LASF26: - 1912 0207 55534246 .ascii "USBFS_GetProtocol\000" - 1912 535F4765 - 1912 7450726F - 1912 746F636F - 1912 6C00 - 1913 .LASF15: - 1914 0219 73697A65 .ascii "sizetype\000" - 1914 74797065 - 1914 00 - 1915 .LASF6: - 1916 0222 6C6F6E67 .ascii "long long int\000" - 1916 206C6F6E - 1916 6720696E - 1916 7400 - 1917 .LASF24: - 1918 0230 545F5553 .ascii "T_USBFS_LUT\000" - 1918 4246535F - 1918 4C555400 - 1919 .LASF13: - 1920 023c 63686172 .ascii "char\000" - 1920 00 - 1921 .LASF29: - 1922 0241 70546D70 .ascii "pTmp\000" - 1922 00 - 1923 .LASF43: - 1924 0246 55534246 .ascii "USBFS_interfaceSetting\000" - 1924 535F696E - 1924 74657266 - 1924 61636553 - 1924 65747469 - 1925 .LASF40: - 1926 025d 55534246 .ascii "USBFS_hidProtocol\000" - 1926 535F6869 - 1926 6450726F - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 45 - - - 1926 746F636F - 1926 6C00 - 1927 .LASF25: - 1928 026f 55534246 .ascii "USBFS_UpdateHIDTimer\000" - 1928 535F5570 - 1928 64617465 - 1928 48494454 - 1928 696D6572 - 1929 .LASF48: - 1930 0284 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 1930 4320342E - 1930 372E3320 - 1930 32303133 - 1930 30333132 - 1931 02b7 616E6368 .ascii "anch revision 196615]\000" - 1931 20726576 - 1931 6973696F - 1931 6E203139 - 1931 36363135 - 1932 .LASF50: - 1933 02cd 573A5C53 .ascii "W:\\SCSI2SD\\USB_Bootloader.cydsn\000" - 1933 43534932 - 1933 53445C55 - 1933 53425F42 - 1933 6F6F746C - 1934 .LASF27: - 1935 02ed 696E7465 .ascii "interface\000" - 1935 72666163 - 1935 6500 - 1936 .LASF4: - 1937 02f7 6C6F6E67 .ascii "long int\000" - 1937 20696E74 - 1937 00 - 1938 .LASF0: - 1939 0300 7369676E .ascii "signed char\000" - 1939 65642063 - 1939 68617200 - 1940 .LASF41: - 1941 030c 55534246 .ascii "USBFS_hidIdleRate\000" - 1941 535F6869 - 1941 6449646C - 1941 65526174 - 1941 6500 - 1942 .LASF42: - 1943 031e 55534246 .ascii "USBFS_hidIdleTimer\000" - 1943 535F6869 - 1943 6449646C - 1943 6554696D - 1943 657200 - 1944 .LASF17: - 1945 0331 6C656E67 .ascii "length\000" - 1945 746800 - 1946 .LASF46: - 1947 0338 55534246 .ascii "USBFS_InitControlWrite\000" - 1947 535F496E - 1947 6974436F - 1947 6E74726F - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8K7Q7i.s page 46 - - - 1947 6C577269 - 1948 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br + 1881 .LASF50: + 1882 011d 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" + 1882 43534932 + 1882 53445C73 + 1882 6F667477 + 1882 6172655C + 1883 014c 6E00 .ascii "n\000" + 1884 .LASF9: + 1885 014e 75696E74 .ascii "uint8\000" + 1885 3800 + 1886 .LASF38: + 1887 0154 696E7465 .ascii "interfaceNumber\000" + 1887 72666163 + 1887 654E756D + 1887 62657200 + 1888 .LASF47: + 1889 0164 55534246 .ascii "USBFS_InitNoDataControlTransfer\000" + 1889 535F496E + 1889 69744E6F + 1889 44617461 + 1889 436F6E74 + 1890 .LASF34: + 1891 0184 55534246 .ascii "USBFS_FindReport\000" + 1891 535F4669 + 1891 6E645265 + 1891 706F7274 + 1891 00 + 1892 .LASF12: + 1893 0195 646F7562 .ascii "double\000" + 1893 6C6500 + 1894 .LASF45: + 1895 019c 55534246 .ascii "USBFS_InitControlRead\000" + 1895 535F496E + 1895 6974436F + 1895 6E74726F + 1895 6C526561 + 1896 .LASF2: + 1897 01b2 73686F72 .ascii "short int\000" + 1897 7420696E + 1897 7400 + 1898 .LASF10: + 1899 01bc 75696E74 .ascii "uint16\000" + 1899 313600 + 1900 .LASF51: + 1901 01c3 55534246 .ascii "USBFS_GetConfigTablePtr\000" + 1901 535F4765 + 1901 74436F6E + 1901 66696754 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 44 + + + 1901 61626C65 + 1902 .LASF30: + 1903 01db 70446573 .ascii "pDescr\000" + 1903 637200 + 1904 .LASF8: + 1905 01e2 756E7369 .ascii "unsigned int\000" + 1905 676E6564 + 1905 20696E74 + 1905 00 + 1906 .LASF36: + 1907 01ef 55534246 .ascii "USBFS_DispatchHIDClassRqst\000" + 1907 535F4469 + 1907 73706174 + 1907 63684849 + 1907 44436C61 + 1908 .LASF7: + 1909 020a 6C6F6E67 .ascii "long long unsigned int\000" + 1909 206C6F6E + 1909 6720756E + 1909 7369676E + 1909 65642069 + 1910 .LASF23: + 1911 0221 705F6C69 .ascii "p_list\000" + 1911 737400 + 1912 .LASF44: + 1913 0228 55534246 .ascii "USBFS_currentTD\000" + 1913 535F6375 + 1913 7272656E + 1913 74544400 + 1914 .LASF26: + 1915 0238 55534246 .ascii "USBFS_GetProtocol\000" + 1915 535F4765 + 1915 7450726F + 1915 746F636F + 1915 6C00 + 1916 .LASF15: + 1917 024a 73697A65 .ascii "sizetype\000" + 1917 74797065 + 1917 00 + 1918 .LASF6: + 1919 0253 6C6F6E67 .ascii "long long int\000" + 1919 206C6F6E + 1919 6720696E + 1919 7400 + 1920 .LASF24: + 1921 0261 545F5553 .ascii "T_USBFS_LUT\000" + 1921 4246535F + 1921 4C555400 + 1922 .LASF13: + 1923 026d 63686172 .ascii "char\000" + 1923 00 + 1924 .LASF29: + 1925 0272 70546D70 .ascii "pTmp\000" + 1925 00 + 1926 .LASF43: + 1927 0277 55534246 .ascii "USBFS_interfaceSetting\000" + 1927 535F696E + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 45 + + + 1927 74657266 + 1927 61636553 + 1927 65747469 + 1928 .LASF40: + 1929 028e 55534246 .ascii "USBFS_hidProtocol\000" + 1929 535F6869 + 1929 6450726F + 1929 746F636F + 1929 6C00 + 1930 .LASF25: + 1931 02a0 55534246 .ascii "USBFS_UpdateHIDTimer\000" + 1931 535F5570 + 1931 64617465 + 1931 48494454 + 1931 696D6572 + 1932 .LASF48: + 1933 02b5 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" + 1933 4320342E + 1933 372E3320 + 1933 32303133 + 1933 30333132 + 1934 02e8 616E6368 .ascii "anch revision 196615]\000" + 1934 20726576 + 1934 6973696F + 1934 6E203139 + 1934 36363135 + 1935 .LASF27: + 1936 02fe 696E7465 .ascii "interface\000" + 1936 72666163 + 1936 6500 + 1937 .LASF4: + 1938 0308 6C6F6E67 .ascii "long int\000" + 1938 20696E74 + 1938 00 + 1939 .LASF0: + 1940 0311 7369676E .ascii "signed char\000" + 1940 65642063 + 1940 68617200 + 1941 .LASF41: + 1942 031d 55534246 .ascii "USBFS_hidIdleRate\000" + 1942 535F6869 + 1942 6449646C + 1942 65526174 + 1942 6500 + 1943 .LASF42: + 1944 032f 55534246 .ascii "USBFS_hidIdleTimer\000" + 1944 535F6869 + 1944 6449646C + 1944 6554696D + 1944 657200 + 1945 .LASF17: + 1946 0342 6C656E67 .ascii "length\000" + 1946 746800 + 1947 .LASF46: + 1948 0349 55534246 .ascii "USBFS_InitControlWrite\000" + 1948 535F496E + 1948 6974436F + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 46 + + + 1948 6E74726F + 1948 6C577269 + 1949 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_hid.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_hid.o index 23c4ba90c93e55c942cda6c8ed8675a2e9cdcbf4..1744134fa0f003234a0454d4bb4b7f4637c48238 100755 GIT binary patch delta 685 zcmZ9IPiPZS5XRr^zL#B_#AK=YW0SQlIixhGMK9_>n&`n=G?heqXvD@Qir8c!U5Orw z9_qnMjShl`9#rsHu!e#{J*iNk=TZn2)Jt!kL@x$sw&=ly_sx61`M%lRw?4i#-Wq`7 z%HWLVU)6+wpb)|ae5gfkTDlM#n4gJgntBafjO%=o%H*Cj{0vQ1prmFRJydk5Zq!}w zeWji}&xWZH3duFzmQH$k`Id_*pD+Wnh9NzgJWFw()LWa>GwzeGt5mNqZo6Bz?tJSvB+20MBo zN#z@L!yT;4bGtO_(F^1ab#OxtCl+W6H6RtjrN!3)Unm)Bprt0@J6=^8DB_}WU=h12 zde^2af&W=h!87&^F&W+2B?I)j1iUAeHSg0vNgMfPM7AKYi_gLsQv>N3%M&f$8l$! za;4fhG;^miS8tE*U4gb0_CY&tNgeK?y)O?ftdTy&ccgDH7|FvHUMBs8%cK+dJJKZ2 zt!N%z;YZRPjKuPA2CK0QOyi?i3KnoRmWCg=O*(`so`&0aFrHTHmJkmx8|%f{co;Tt Qo>(ABm(8rb77qmf0AQ7Xz5oCK delta 670 zcmZ9IPiPZC6vpT6%yd_in1q__wn>_{i$offYA;n(npy-Yx|V1?81YXdDm7VYBSo;N zU_lYJ^j$qzL6CxA%|$^yDO6~WmWm*V9(oCQ%SFWZws>)2zW2W0d~bGV*M^sdXFFkN zv1`l--7$oKh!A4Mz(+=6Tu31du)Yy741F88m>1b8-K4Cc%n(CMceAt1FXW`sm#a12 zTO_A495~fWL+U=ar31mddc(z1WoBUQ!>CNA+vt=QC1+P@&zvEVb3VshVeZ0$oN|9r zTFxKk8CMBQ9j9)y>ZLLHG*5j9eEcd?(7>k5W=!I67WfE$!nBNO0iP%sZeXA4i5EE0 z3TY}oXg9WiRdr;876Lj#+2{f;tDaPmTBrc25H(t_*ng+VXaVE;7`(^xIu9;B)IOZX zKRS6cOur90Ua)EsA#{yOTL**ehyQT;ei~7wP5*3P{c+1Pvp%uqC1g+TEfo(I5AQAxl};1~&kXv0?TUY{ zd|_he*!A*cwcZso>5BF3aV6m@?%3+VEu1F3iz}qhF_Z9M2`i-Q_>Ob{BgrYs%p^T{ zf}cs(aGUKxKVGx*;NiUO!X$pQbMO-zqz)#W99+WvPENm$3vmxe>{h(t#NaJHAoe>& Mf0tQ(*$GGf0x0WwxBvhE diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_midi.lst b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_midi.lst index cebf97b0..99e28d78 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_midi.lst +++ b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_midi.lst @@ -1,4 +1,4 @@ -ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccF9uT4s.s page 1 +ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccwPvd37.s page 1 1 .syntax unified @@ -58,7 +58,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccF9uT4s.s page 1 55 0047 02 .uleb128 0x2 56 0048 08 .byte 0x8 57 0049 05 .byte 0x5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccF9uT4s.s page 2 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccwPvd37.s page 2 58 004a 00000000 .4byte .LASF6 @@ -89,7 +89,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccF9uT4s.s page 1 83 0078 02 .uleb128 0x2 84 0079 04 .byte 0x4 85 007a 07 .byte 0x7 - 86 007b 25010000 .4byte .LASF12 + 86 007b 36010000 .4byte .LASF12 87 007f 00 .byte 0 88 .section .debug_abbrev,"",%progbits 89 .Ldebug_abbrev0: @@ -118,7 +118,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccF9uT4s.s page 1 112 0016 03 .uleb128 0x3 113 0017 0E .uleb128 0xe 114 0018 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccF9uT4s.s page 3 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccwPvd37.s page 3 115 0019 00 .byte 0 @@ -178,7 +178,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccF9uT4s.s page 1 149 69676E65 149 6420696E 149 7400 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccF9uT4s.s page 4 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccwPvd37.s page 4 150 .LASF7: @@ -226,13 +226,14 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccF9uT4s.s page 1 169 7420696E 169 7400 170 .LASF15: - 171 0105 573A5C53 .ascii "W:\\SCSI2SD\\USB_Bootloader.cydsn\000" + 171 0105 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" 171 43534932 - 171 53445C55 - 171 53425F42 - 171 6F6F746C - 172 .LASF12: - 173 0125 73697A65 .ascii "sizetype\000" - 173 74797065 - 173 00 - 174 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br + 171 53445C73 + 171 6F667477 + 171 6172655C + 172 0134 6E00 .ascii "n\000" + 173 .LASF12: + 174 0136 73697A65 .ascii "sizetype\000" + 174 74797065 + 174 00 + 175 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_midi.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_midi.o index 96eedfbe5c42bd7a164e2df67afc890f5f4467c7..dede5919bf0974cfc2c9952cb9e21485fc0e316e 100755 GIT binary patch delta 85 zcmcb?_kwSN0%OBO#Xd%}jT`bAIg0bsO3D+9Qa6h+H8M_~!MuU-!emdDa>j(o2U&s{ p?I(+}Dl_^`wq#Xj+&?)HNPe2!$*Ru8z&3dks~Y2h%{N)=83F5r8{_~0 delta 76 zcmV-S0JHz-4%iNmAOUcZA&vnhv9NCevoHd90h6Z#u>ru7Sp;_hP?OOFQvoiMB?Th^ iJ(EcVCjqXLaRny<;ggvKCj#&Vlfnfi0kE^_1%CnIQyFXk diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_pm.lst b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_pm.lst index 96c2cd61..aed170f6 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_pm.lst +++ b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_pm.lst @@ -1,4 +1,4 @@ -ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 +ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuoEjMf.s page 1 1 .syntax unified @@ -58,7 +58,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 29:.\Generated_Source\PSoC5/USBFS_pm.c **** 30:.\Generated_Source\PSoC5/USBFS_pm.c **** /*************************************** 31:.\Generated_Source\PSoC5/USBFS_pm.c **** * Local data allocation - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 2 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuoEjMf.s page 2 32:.\Generated_Source\PSoC5/USBFS_pm.c **** ***************************************/ @@ -118,7 +118,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 50 .LFB57: 63:.\Generated_Source\PSoC5/USBFS_pm.c **** } 64:.\Generated_Source\PSoC5/USBFS_pm.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 3 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuoEjMf.s page 3 65:.\Generated_Source\PSoC5/USBFS_pm.c **** #endif /* (USBFS_DP_ISR_REMOVE == 0u) */ @@ -178,7 +178,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 102:.\Generated_Source\PSoC5/USBFS_pm.c **** * None. 103:.\Generated_Source\PSoC5/USBFS_pm.c **** * 104:.\Generated_Source\PSoC5/USBFS_pm.c **** * Reentrant: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 4 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuoEjMf.s page 4 105:.\Generated_Source\PSoC5/USBFS_pm.c **** * No. @@ -238,7 +238,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 128:.\Generated_Source\PSoC5/USBFS_pm.c **** * None. 129:.\Generated_Source\PSoC5/USBFS_pm.c **** * 130:.\Generated_Source\PSoC5/USBFS_pm.c **** * Global variables: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 5 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuoEjMf.s page 5 131:.\Generated_Source\PSoC5/USBFS_pm.c **** * USBFS_backup.enable: modified. @@ -298,7 +298,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 129 001a 2E70 strb r6, [r5, #0] 130 .loc 1 151 0 131 001c 0A78 ldrb r2, [r1, #0] @ zero_extendqisi2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 6 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuoEjMf.s page 6 152:.\Generated_Source\PSoC5/USBFS_pm.c **** CyDelayUs(0u); /*~50ns delay */ @@ -358,7 +358,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 167 004e 01F0FE02 and r2, r1, #254 168 0052 1A70 strb r2, [r3, #0] 169 .loc 1 166 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 7 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuoEjMf.s page 7 170 0054 FFF7FEFF bl CyDelayUs @@ -418,7 +418,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 183:.\Generated_Source\PSoC5/USBFS_pm.c **** } 184:.\Generated_Source\PSoC5/USBFS_pm.c **** CyExitCriticalSection(enableInterrupts); 206 .loc 1 184 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 8 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuoEjMf.s page 8 207 0088 4046 mov r0, r8 @@ -478,7 +478,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 192:.\Generated_Source\PSoC5/USBFS_pm.c **** #endif /* (USBFS_DP_ISR_REMOVE == 0u) */ 193:.\Generated_Source\PSoC5/USBFS_pm.c **** 194:.\Generated_Source\PSoC5/USBFS_pm.c **** } - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 9 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuoEjMf.s page 9 195:.\Generated_Source\PSoC5/USBFS_pm.c **** @@ -538,7 +538,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 225:.\Generated_Source\PSoC5/USBFS_pm.c **** CyIntDisable(USBFS_DP_INTC_VECT_NUM); 276 .loc 1 225 0 277 0010 2248 ldr r0, .L20+4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 10 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuoEjMf.s page 10 278 .LVL15: @@ -598,7 +598,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 314 .loc 1 241 0 315 0050 0020 movs r0, #0 316 0052 FFF7FEFF bl CyDelayUs - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 11 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuoEjMf.s page 11 317 .LVL17: @@ -658,7 +658,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 344 .loc 1 265 0 345 007e 0120 movs r0, #1 346 0080 FFF7FEFF bl CyDelayCycles - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 12 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuoEjMf.s page 12 347 .LVL19: @@ -718,17 +718,17 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 391 .section .debug_info,"",%progbits 392 .Ldebug_info0: 393 0000 7D030000 .4byte 0x37d - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 13 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuoEjMf.s page 13 394 0004 0200 .2byte 0x2 395 0006 00000000 .4byte .Ldebug_abbrev0 396 000a 04 .byte 0x4 397 000b 01 .uleb128 0x1 - 398 000c E2010000 .4byte .LASF35 + 398 000c FD010000 .4byte .LASF35 399 0010 01 .byte 0x1 - 400 0011 B8010000 .4byte .LASF36 - 401 0015 2B020000 .4byte .LASF37 + 400 0011 D3010000 .4byte .LASF36 + 401 0015 93000000 .4byte .LASF37 402 0019 00000000 .4byte .Ldebug_ranges0+0 403 001d 00000000 .4byte 0 404 0021 00000000 .4byte 0 @@ -736,40 +736,40 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 406 0029 02 .uleb128 0x2 407 002a 01 .byte 0x1 408 002b 06 .byte 0x6 - 409 002c 6D020000 .4byte .LASF0 + 409 002c 7E020000 .4byte .LASF0 410 0030 02 .uleb128 0x2 411 0031 01 .byte 0x1 412 0032 08 .byte 0x8 - 413 0033 75000000 .4byte .LASF1 + 413 0033 6E000000 .4byte .LASF1 414 0037 02 .uleb128 0x2 415 0038 02 .byte 0x2 416 0039 05 .byte 0x5 - 417 003a AE010000 .4byte .LASF2 + 417 003a C9010000 .4byte .LASF2 418 003e 02 .uleb128 0x2 419 003f 02 .byte 0x2 420 0040 07 .byte 0x7 - 421 0041 38000000 .4byte .LASF3 + 421 0041 31000000 .4byte .LASF3 422 0045 03 .uleb128 0x3 - 423 0046 76010000 .4byte .LASF9 + 423 0046 91010000 .4byte .LASF9 424 004a 02 .byte 0x2 425 004b 4F .byte 0x4f 426 004c 50000000 .4byte 0x50 427 0050 02 .uleb128 0x2 428 0051 04 .byte 0x4 429 0052 05 .byte 0x5 - 430 0053 58020000 .4byte .LASF4 + 430 0053 69020000 .4byte .LASF4 431 0057 02 .uleb128 0x2 432 0058 04 .byte 0x4 433 0059 07 .byte 0x7 - 434 005a 88000000 .4byte .LASF5 + 434 005a 81000000 .4byte .LASF5 435 005e 02 .uleb128 0x2 436 005f 08 .byte 0x8 437 0060 05 .byte 0x5 - 438 0061 87010000 .4byte .LASF6 + 438 0061 A2010000 .4byte .LASF6 439 0065 02 .uleb128 0x2 440 0066 08 .byte 0x8 441 0067 07 .byte 0x7 - 442 0068 28010000 .4byte .LASF7 + 442 0068 43010000 .4byte .LASF7 443 006c 04 .uleb128 0x4 444 006d 04 .byte 0x4 445 006e 05 .byte 0x5 @@ -777,39 +777,39 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 447 0073 02 .uleb128 0x2 448 0074 04 .byte 0x4 449 0075 07 .byte 0x7 - 450 0076 1B010000 .4byte .LASF8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 14 + 450 0076 36010000 .4byte .LASF8 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuoEjMf.s page 14 451 007a 03 .uleb128 0x3 - 452 007b DC010000 .4byte .LASF10 + 452 007b F7010000 .4byte .LASF10 453 007f 03 .byte 0x3 454 0080 5B .byte 0x5b 455 0081 30000000 .4byte 0x30 456 0085 03 .uleb128 0x3 - 457 0086 CC000000 .4byte .LASF11 + 457 0086 F6000000 .4byte .LASF11 458 008a 03 .byte 0x3 459 008b 5C .byte 0x5c 460 008c 3E000000 .4byte 0x3e 461 0090 03 .uleb128 0x3 - 462 0091 EE000000 .4byte .LASF12 + 462 0091 18010000 .4byte .LASF12 463 0095 03 .byte 0x3 464 0096 5D .byte 0x5d 465 0097 57000000 .4byte 0x57 466 009b 02 .uleb128 0x2 467 009c 04 .byte 0x4 468 009d 04 .byte 0x4 - 469 009e 5B000000 .4byte .LASF13 + 469 009e 54000000 .4byte .LASF13 470 00a2 02 .uleb128 0x2 471 00a3 08 .byte 0x8 472 00a4 04 .byte 0x4 - 473 00a5 C5000000 .4byte .LASF14 + 473 00a5 EF000000 .4byte .LASF14 474 00a9 02 .uleb128 0x2 475 00aa 01 .byte 0x1 476 00ab 08 .byte 0x8 - 477 00ac 95010000 .4byte .LASF15 + 477 00ac B0010000 .4byte .LASF15 478 00b0 03 .uleb128 0x3 - 479 00b1 83000000 .4byte .LASF16 + 479 00b1 7C000000 .4byte .LASF16 480 00b5 03 .byte 0x3 481 00b6 F0 .byte 0xf0 482 00b7 BB000000 .4byte 0xbb @@ -823,7 +823,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 490 00cb 05 .uleb128 0x5 491 00cc 90000000 .4byte 0x90 492 00d0 06 .uleb128 0x6 - 493 00d1 69010000 .4byte .LASF18 + 493 00d1 84010000 .4byte .LASF18 494 00d5 03 .byte 0x3 495 00d6 0201 .2byte 0x102 496 00d8 DC000000 .4byte 0xdc @@ -835,17 +835,17 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 502 00e4 02 .uleb128 0x2 503 00e5 04 .byte 0x4 504 00e6 07 .byte 0x7 - 505 00e7 7E010000 .4byte .LASF19 + 505 00e7 99010000 .4byte .LASF19 506 00eb 09 .uleb128 0x9 507 00ec 02 .byte 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 15 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuoEjMf.s page 15 508 00ed 04 .byte 0x4 509 00ee A5 .byte 0xa5 510 00ef 10010000 .4byte 0x110 511 00f3 0A .uleb128 0xa - 512 00f4 61020000 .4byte .LASF20 + 512 00f4 72020000 .4byte .LASF20 513 00f8 04 .byte 0x4 514 00f9 A7 .byte 0xa7 515 00fa 7A000000 .4byte 0x7a @@ -853,7 +853,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 517 00ff 23 .byte 0x23 518 0100 00 .uleb128 0 519 0101 0A .uleb128 0xa - 520 0102 50010000 .4byte .LASF21 + 520 0102 6B010000 .4byte .LASF21 521 0106 04 .byte 0x4 522 0107 A8 .byte 0xa8 523 0108 7A000000 .4byte 0x7a @@ -862,13 +862,13 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 526 010e 01 .uleb128 0x1 527 010f 00 .byte 0 528 0110 03 .uleb128 0x3 - 529 0111 55010000 .4byte .LASF22 + 529 0111 70010000 .4byte .LASF22 530 0115 04 .byte 0x4 531 0116 A9 .byte 0xa9 532 0117 EB000000 .4byte 0xeb 533 011b 0B .uleb128 0xb 534 011c 01 .byte 0x1 - 535 011d 79020000 .4byte .LASF23 + 535 011d 8A020000 .4byte .LASF23 536 0121 01 .byte 0x1 537 0122 37 .byte 0x37 538 0123 01 .byte 0x1 @@ -880,7 +880,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 544 012f 01 .byte 0x1 545 0130 0B .uleb128 0xb 546 0131 01 .byte 0x1 - 547 0132 D3000000 .4byte .LASF24 + 547 0132 FD000000 .4byte .LASF24 548 0136 01 .byte 0x1 549 0137 55 .byte 0x55 550 0138 01 .byte 0x1 @@ -892,13 +892,13 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 556 0144 01 .byte 0x1 557 0145 0C .uleb128 0xc 558 0146 01 .byte 0x1 - 559 0147 9A010000 .4byte .LASF25 + 559 0147 B5010000 .4byte .LASF25 560 014b 01 .byte 0x1 561 014c 6C .byte 0x6c 562 014d 01 .byte 0x1 563 014e 00000000 .4byte .LFB58 564 0152 10000000 .4byte .LFE58 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 16 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuoEjMf.s page 16 565 0156 02 .byte 0x2 @@ -923,7 +923,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 584 017e 01 .byte 0x1 585 017f 2E020000 .4byte 0x22e 586 0183 0F .uleb128 0xf - 587 0184 B4000000 .4byte .LASF28 + 587 0184 DE000000 .4byte .LASF28 588 0188 01 .byte 0x1 589 0189 8B .byte 0x8b 590 018a 7A000000 .4byte 0x7a @@ -958,7 +958,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 619 01ce 12 .uleb128 0x12 620 01cf 01 .byte 0x1 621 01d0 50 .byte 0x50 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 17 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuoEjMf.s page 17 622 01d1 02 .byte 0x2 @@ -1018,12 +1018,12 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 676 022b 3C .byte 0x3c 677 022c 00 .byte 0 678 022d 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 18 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuoEjMf.s page 18 679 022e 0E .uleb128 0xe 680 022f 01 .byte 0x1 - 681 0230 4B020000 .4byte .LASF27 + 681 0230 5C020000 .4byte .LASF27 682 0234 01 .byte 0x1 683 0235 D9 .byte 0xd9 684 0236 01 .byte 0x1 @@ -1033,7 +1033,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 688 0243 01 .byte 0x1 689 0244 C8020000 .4byte 0x2c8 690 0248 0F .uleb128 0xf - 691 0249 B4000000 .4byte .LASF28 + 691 0249 DE000000 .4byte .LASF28 692 024d 01 .byte 0x1 693 024e DB .byte 0xdb 694 024f 7A000000 .4byte 0x7a @@ -1078,7 +1078,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 733 02a3 AD020000 .4byte 0x2ad 734 02a7 12 .uleb128 0x12 735 02a8 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 19 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuoEjMf.s page 19 736 02a9 50 .byte 0x50 @@ -1101,7 +1101,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 753 02c6 00 .byte 0 754 02c7 00 .byte 0 755 02c8 15 .uleb128 0x15 - 756 02c9 9A000000 .4byte .LASF29 + 756 02c9 C4000000 .4byte .LASF29 757 02cd 01 .byte 0x1 758 02ce 22 .byte 0x22 759 02cf 10010000 .4byte 0x110 @@ -1109,14 +1109,14 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 761 02d4 03 .byte 0x3 762 02d5 00000000 .4byte USBFS_backup 763 02d9 16 .uleb128 0x16 - 764 02da 61000000 .4byte .LASF30 + 764 02da 5A000000 .4byte .LASF30 765 02de 04 .byte 0x4 766 02df 1A02 .2byte 0x21a 767 02e1 BB000000 .4byte 0xbb 768 02e5 01 .byte 0x1 769 02e6 01 .byte 0x1 770 02e7 16 .uleb128 0x16 - 771 02e8 A7000000 .4byte .LASF31 + 771 02e8 D1000000 .4byte .LASF31 772 02ec 05 .byte 0x5 773 02ed 1606 .2byte 0x616 774 02ef F5020000 .4byte 0x2f5 @@ -1126,25 +1126,25 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 778 02f6 45000000 .4byte 0x45 779 02fa 17 .uleb128 0x17 780 02fb 01 .byte 0x1 - 781 02fc 4B000000 .4byte .LASF38 + 781 02fc 44000000 .4byte .LASF38 782 0300 07 .byte 0x7 783 0301 6B .byte 0x6b 784 0302 01 .byte 0x1 785 0303 01 .byte 0x1 786 0304 18 .uleb128 0x18 787 0305 01 .byte 0x1 - 788 0306 F5000000 .4byte .LASF39 + 788 0306 1F010000 .4byte .LASF39 789 030a 06 .byte 0x6 790 030b 7E .byte 0x7e 791 030c 01 .byte 0x1 792 030d 7A000000 .4byte 0x7a - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 20 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuoEjMf.s page 20 793 0311 01 .byte 0x1 794 0312 19 .uleb128 0x19 795 0313 01 .byte 0x1 - 796 0314 E4000000 .4byte .LASF32 + 796 0314 0E010000 .4byte .LASF32 797 0318 06 .byte 0x6 798 0319 78 .byte 0x78 799 031a 01 .byte 0x1 @@ -1155,7 +1155,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 804 0325 00 .byte 0 805 0326 19 .uleb128 0x19 806 0327 01 .byte 0x1 - 807 0328 22000000 .4byte .LASF33 + 807 0328 46020000 .4byte .LASF33 808 032c 06 .byte 0x6 809 032d 7F .byte 0x7f 810 032e 01 .byte 0x1 @@ -1166,7 +1166,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 815 0339 00 .byte 0 816 033a 1B .uleb128 0x1b 817 033b 01 .byte 0x1 - 818 033c 0C010000 .4byte .LASF40 + 818 033c 22000000 .4byte .LASF40 819 0340 06 .byte 0x6 820 0341 89 .byte 0x89 821 0342 01 .byte 0x1 @@ -1180,7 +1180,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 829 0356 00 .byte 0 830 0357 19 .uleb128 0x19 831 0358 01 .byte 0x1 - 832 0359 3F010000 .4byte .LASF34 + 832 0359 5A010000 .4byte .LASF34 833 035d 06 .byte 0x6 834 035e 8C .byte 0x8c 835 035f 01 .byte 0x1 @@ -1198,7 +1198,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 847 0377 7A .byte 0x7a 848 0378 01 .byte 0x1 849 0379 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 21 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuoEjMf.s page 21 850 037a 1A .uleb128 0x1a @@ -1258,7 +1258,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 904 0030 0B .uleb128 0xb 905 0031 0B .uleb128 0xb 906 0032 3E .uleb128 0x3e - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 22 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuoEjMf.s page 22 907 0033 0B .uleb128 0xb @@ -1318,7 +1318,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 961 0069 0A .uleb128 0xa 962 006a 0D .uleb128 0xd 963 006b 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 23 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuoEjMf.s page 23 964 006c 03 .uleb128 0x3 @@ -1378,7 +1378,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 1018 00a3 9742 .uleb128 0x2117 1019 00a5 0C .uleb128 0xc 1020 00a6 01 .uleb128 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 24 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuoEjMf.s page 24 1021 00a7 13 .uleb128 0x13 @@ -1438,7 +1438,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 1075 00e1 10 .uleb128 0x10 1076 00e2 898201 .uleb128 0x4109 1077 00e5 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 25 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuoEjMf.s page 25 1078 00e6 11 .uleb128 0x11 @@ -1498,7 +1498,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 1132 0126 0B .uleb128 0xb 1133 0127 49 .uleb128 0x49 1134 0128 13 .uleb128 0x13 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 26 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuoEjMf.s page 26 1135 0129 02 .uleb128 0x2 @@ -1558,7 +1558,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 1189 015f 0C .uleb128 0xc 1190 0160 00 .byte 0 1191 0161 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 27 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuoEjMf.s page 27 1192 0162 19 .uleb128 0x19 @@ -1618,7 +1618,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 1246 0198 3A .uleb128 0x3a 1247 0199 0B .uleb128 0xb 1248 019a 3B .uleb128 0x3b - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 28 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuoEjMf.s page 28 1249 019b 0B .uleb128 0xb @@ -1678,7 +1678,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 1303 0070 00000000 .4byte 0 1304 .LLST3: 1305 0074 0A000000 .4byte .LVL14 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 29 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuoEjMf.s page 29 1306 0078 12000000 .4byte .LVL15 @@ -1738,7 +1738,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 1353 7300 1354 .LASF17: 1355 000e 72656733 .ascii "reg32\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 30 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuoEjMf.s page 30 1355 3200 @@ -1747,203 +1747,204 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 1 1357 535F5375 1357 7370656E 1357 6400 - 1358 .LASF33: - 1359 0022 43794578 .ascii "CyExitCriticalSection\000" - 1359 69744372 - 1359 69746963 - 1359 616C5365 - 1359 6374696F + 1358 .LASF40: + 1359 0022 4379496E .ascii "CyIntSetVector\000" + 1359 74536574 + 1359 56656374 + 1359 6F7200 1360 .LASF3: - 1361 0038 73686F72 .ascii "short unsigned int\000" + 1361 0031 73686F72 .ascii "short unsigned int\000" 1361 7420756E 1361 7369676E 1361 65642069 1361 6E7400 1362 .LASF38: - 1363 004b 55534246 .ascii "USBFS_ConfigReg\000" + 1363 0044 55534246 .ascii "USBFS_ConfigReg\000" 1363 535F436F 1363 6E666967 1363 52656700 1364 .LASF13: - 1365 005b 666C6F61 .ascii "float\000" + 1365 0054 666C6F61 .ascii "float\000" 1365 7400 1366 .LASF30: - 1367 0061 55534246 .ascii "USBFS_configuration\000" + 1367 005a 55534246 .ascii "USBFS_configuration\000" 1367 535F636F 1367 6E666967 1367 75726174 1367 696F6E00 1368 .LASF1: - 1369 0075 756E7369 .ascii "unsigned char\000" + 1369 006e 756E7369 .ascii "unsigned char\000" 1369 676E6564 1369 20636861 1369 7200 1370 .LASF16: - 1371 0083 72656738 .ascii "reg8\000" + 1371 007c 72656738 .ascii "reg8\000" 1371 00 1372 .LASF5: - 1373 0088 6C6F6E67 .ascii "long unsigned int\000" + 1373 0081 6C6F6E67 .ascii "long unsigned int\000" 1373 20756E73 1373 69676E65 1373 6420696E 1373 7400 - 1374 .LASF29: - 1375 009a 55534246 .ascii "USBFS_backup\000" - 1375 535F6261 - 1375 636B7570 - 1375 00 - 1376 .LASF31: - 1377 00a7 49544D5F .ascii "ITM_RxBuffer\000" - 1377 52784275 - 1377 66666572 - 1377 00 - 1378 .LASF28: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 31 - - - 1379 00b4 656E6162 .ascii "enableInterrupts\000" - 1379 6C65496E - 1379 74657272 - 1379 75707473 - 1379 00 - 1380 .LASF14: - 1381 00c5 646F7562 .ascii "double\000" - 1381 6C6500 - 1382 .LASF11: - 1383 00cc 75696E74 .ascii "uint16\000" - 1383 313600 - 1384 .LASF24: - 1385 00d3 55534246 .ascii "USBFS_SaveConfig\000" - 1385 535F5361 - 1385 7665436F - 1385 6E666967 - 1385 00 - 1386 .LASF32: - 1387 00e4 43794465 .ascii "CyDelayUs\000" - 1387 6C617955 - 1387 7300 - 1388 .LASF12: - 1389 00ee 75696E74 .ascii "uint32\000" - 1389 333200 - 1390 .LASF39: - 1391 00f5 4379456E .ascii "CyEnterCriticalSection\000" - 1391 74657243 - 1391 72697469 - 1391 63616C53 - 1391 65637469 - 1392 .LASF40: - 1393 010c 4379496E .ascii "CyIntSetVector\000" - 1393 74536574 - 1393 56656374 - 1393 6F7200 - 1394 .LASF8: - 1395 011b 756E7369 .ascii "unsigned int\000" - 1395 676E6564 - 1395 20696E74 - 1395 00 - 1396 .LASF7: - 1397 0128 6C6F6E67 .ascii "long long unsigned int\000" - 1397 206C6F6E - 1397 6720756E - 1397 7369676E - 1397 65642069 - 1398 .LASF34: - 1399 013f 4379496E .ascii "CyIntSetPriority\000" - 1399 74536574 - 1399 5072696F - 1399 72697479 - 1399 00 - 1400 .LASF21: - 1401 0150 6D6F6465 .ascii "mode\000" - 1401 00 - 1402 .LASF22: - 1403 0155 55534246 .ascii "USBFS_BACKUP_STRUCT\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 32 - - - 1403 535F4241 - 1403 434B5550 - 1403 5F535452 - 1403 55435400 - 1404 .LASF18: - 1405 0169 63796973 .ascii "cyisraddress\000" - 1405 72616464 - 1405 72657373 - 1405 00 - 1406 .LASF9: - 1407 0176 696E7433 .ascii "int32_t\000" - 1407 325F7400 - 1408 .LASF19: - 1409 017e 73697A65 .ascii "sizetype\000" - 1409 74797065 - 1409 00 - 1410 .LASF6: - 1411 0187 6C6F6E67 .ascii "long long int\000" - 1411 206C6F6E - 1411 6720696E - 1411 7400 - 1412 .LASF15: - 1413 0195 63686172 .ascii "char\000" - 1413 00 - 1414 .LASF25: - 1415 019a 55534246 .ascii "USBFS_RestoreConfig\000" - 1415 535F5265 - 1415 73746F72 - 1415 65436F6E - 1415 66696700 - 1416 .LASF2: - 1417 01ae 73686F72 .ascii "short int\000" - 1417 7420696E - 1417 7400 - 1418 .LASF36: - 1419 01b8 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\USBFS_pm.c\000" - 1419 6E657261 - 1419 7465645F - 1419 536F7572 - 1419 63655C50 - 1420 .LASF10: - 1421 01dc 75696E74 .ascii "uint8\000" - 1421 3800 - 1422 .LASF35: - 1423 01e2 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 1423 4320342E - 1423 372E3320 - 1423 32303133 - 1423 30333132 - 1424 0215 616E6368 .ascii "anch revision 196615]\000" - 1424 20726576 - 1424 6973696F - 1424 6E203139 - 1424 36363135 - 1425 .LASF37: - 1426 022b 573A5C53 .ascii "W:\\SCSI2SD\\USB_Bootloader.cydsn\000" - 1426 43534932 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccTOK9dp.s page 33 - - - 1426 53445C55 - 1426 53425F42 - 1426 6F6F746C - 1427 .LASF27: - 1428 024b 55534246 .ascii "USBFS_Resume\000" - 1428 535F5265 - 1428 73756D65 - 1428 00 - 1429 .LASF4: - 1430 0258 6C6F6E67 .ascii "long int\000" - 1430 20696E74 - 1430 00 - 1431 .LASF20: - 1432 0261 656E6162 .ascii "enableState\000" - 1432 6C655374 - 1432 61746500 - 1433 .LASF0: - 1434 026d 7369676E .ascii "signed char\000" - 1434 65642063 - 1434 68617200 - 1435 .LASF23: - 1436 0279 55534246 .ascii "USBFS_DP_ISR\000" - 1436 535F4450 - 1436 5F495352 - 1436 00 - 1437 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br + 1374 .LASF37: + 1375 0093 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" + 1375 43534932 + 1375 53445C73 + 1375 6F667477 + 1375 6172655C + 1376 00c2 6E00 .ascii "n\000" + 1377 .LASF29: + 1378 00c4 55534246 .ascii "USBFS_backup\000" + 1378 535F6261 + 1378 636B7570 + 1378 00 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuoEjMf.s page 31 + + + 1379 .LASF31: + 1380 00d1 49544D5F .ascii "ITM_RxBuffer\000" + 1380 52784275 + 1380 66666572 + 1380 00 + 1381 .LASF28: + 1382 00de 656E6162 .ascii "enableInterrupts\000" + 1382 6C65496E + 1382 74657272 + 1382 75707473 + 1382 00 + 1383 .LASF14: + 1384 00ef 646F7562 .ascii "double\000" + 1384 6C6500 + 1385 .LASF11: + 1386 00f6 75696E74 .ascii "uint16\000" + 1386 313600 + 1387 .LASF24: + 1388 00fd 55534246 .ascii "USBFS_SaveConfig\000" + 1388 535F5361 + 1388 7665436F + 1388 6E666967 + 1388 00 + 1389 .LASF32: + 1390 010e 43794465 .ascii "CyDelayUs\000" + 1390 6C617955 + 1390 7300 + 1391 .LASF12: + 1392 0118 75696E74 .ascii "uint32\000" + 1392 333200 + 1393 .LASF39: + 1394 011f 4379456E .ascii "CyEnterCriticalSection\000" + 1394 74657243 + 1394 72697469 + 1394 63616C53 + 1394 65637469 + 1395 .LASF8: + 1396 0136 756E7369 .ascii "unsigned int\000" + 1396 676E6564 + 1396 20696E74 + 1396 00 + 1397 .LASF7: + 1398 0143 6C6F6E67 .ascii "long long unsigned int\000" + 1398 206C6F6E + 1398 6720756E + 1398 7369676E + 1398 65642069 + 1399 .LASF34: + 1400 015a 4379496E .ascii "CyIntSetPriority\000" + 1400 74536574 + 1400 5072696F + 1400 72697479 + 1400 00 + 1401 .LASF21: + 1402 016b 6D6F6465 .ascii "mode\000" + 1402 00 + 1403 .LASF22: + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuoEjMf.s page 32 + + + 1404 0170 55534246 .ascii "USBFS_BACKUP_STRUCT\000" + 1404 535F4241 + 1404 434B5550 + 1404 5F535452 + 1404 55435400 + 1405 .LASF18: + 1406 0184 63796973 .ascii "cyisraddress\000" + 1406 72616464 + 1406 72657373 + 1406 00 + 1407 .LASF9: + 1408 0191 696E7433 .ascii "int32_t\000" + 1408 325F7400 + 1409 .LASF19: + 1410 0199 73697A65 .ascii "sizetype\000" + 1410 74797065 + 1410 00 + 1411 .LASF6: + 1412 01a2 6C6F6E67 .ascii "long long int\000" + 1412 206C6F6E + 1412 6720696E + 1412 7400 + 1413 .LASF15: + 1414 01b0 63686172 .ascii "char\000" + 1414 00 + 1415 .LASF25: + 1416 01b5 55534246 .ascii "USBFS_RestoreConfig\000" + 1416 535F5265 + 1416 73746F72 + 1416 65436F6E + 1416 66696700 + 1417 .LASF2: + 1418 01c9 73686F72 .ascii "short int\000" + 1418 7420696E + 1418 7400 + 1419 .LASF36: + 1420 01d3 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\USBFS_pm.c\000" + 1420 6E657261 + 1420 7465645F + 1420 536F7572 + 1420 63655C50 + 1421 .LASF10: + 1422 01f7 75696E74 .ascii "uint8\000" + 1422 3800 + 1423 .LASF35: + 1424 01fd 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" + 1424 4320342E + 1424 372E3320 + 1424 32303133 + 1424 30333132 + 1425 0230 616E6368 .ascii "anch revision 196615]\000" + 1425 20726576 + 1425 6973696F + 1425 6E203139 + 1425 36363135 + 1426 .LASF33: + 1427 0246 43794578 .ascii "CyExitCriticalSection\000" + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccuoEjMf.s page 33 + + + 1427 69744372 + 1427 69746963 + 1427 616C5365 + 1427 6374696F + 1428 .LASF27: + 1429 025c 55534246 .ascii "USBFS_Resume\000" + 1429 535F5265 + 1429 73756D65 + 1429 00 + 1430 .LASF4: + 1431 0269 6C6F6E67 .ascii "long int\000" + 1431 20696E74 + 1431 00 + 1432 .LASF20: + 1433 0272 656E6162 .ascii "enableState\000" + 1433 6C655374 + 1433 61746500 + 1434 .LASF0: + 1435 027e 7369676E .ascii "signed char\000" + 1435 65642063 + 1435 68617200 + 1436 .LASF23: + 1437 028a 55534246 .ascii "USBFS_DP_ISR\000" + 1437 535F4450 + 1437 5F495352 + 1437 00 + 1438 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_pm.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_pm.o index 1dac6de57c1af68e4f011a24745fe26be3f4263b..4f089bf3f47434e583c587ecb94187c14085bc5d 100755 GIT binary patch delta 657 zcmXAkJ!n&56o$X|yWjosHpcvvnAXAmhz+`^gVrFTq!j`}gs81G4k1JcEs4Y{siM6K ziq+8gBPt{dxZi z{7oo@Hw>b+Xfo7rX0%coUR`m~_G^x`cK5Tg=ANoj?=BaG!LFG@fWfuM`DC?5Q#V;Io;XV)I5F4srMP&Sj zLKilljeSp3By-1JRoOnOEyvy4AZOS2Y}QX7dz$r zltZvbS#8G%)13s;*vV_o4CHO-K~&TBdxt&MgA=^ygg{n2nNvG3z;tG@$_13M z#@c2K(1ArOoxI_62bg<*k*ZoLQHn#1qC|Ns5pyqT49v)nv{&DT9! zNOqtU)*1a;{r70N*VxwZZ}CiP`-+2Fdu3M6ZRw*C85ny(V#d2K%D0O$^1TulV{ANC zmsvL}XIn6SO!hwtl1nG0{1i-#F|{${Qhf743j9a1aZl!ZZ<%&R+5>{$TcVo`Hpo~Ce@lQ_?PWuEu3T z7(EOPoe$4qlb(eUeEJpML4)ETI{o6H-nC%HxcFJISdhX4Qo diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_std.lst b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_std.lst index da519309..091ea626 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_std.lst +++ b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_std.lst @@ -1,4 +1,4 @@ -ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 +ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 1 1 .syntax unified @@ -58,7 +58,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 29:.\Generated_Source\PSoC5/USBFS_std.c **** #if defined(USBFS_ENABLE_FWSN_STRING) 30:.\Generated_Source\PSoC5/USBFS_std.c **** static volatile uint8 *USBFS_fwSerialNumberStringDescriptor; 31:.\Generated_Source\PSoC5/USBFS_std.c **** static volatile uint8 USBFS_snStringConfirm = USBFS_FALSE; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 2 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 2 32:.\Generated_Source\PSoC5/USBFS_std.c **** #endif /* USBFS_ENABLE_FWSN_STRING */ @@ -118,7 +118,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 86:.\Generated_Source\PSoC5/USBFS_std.c **** * No. 87:.\Generated_Source\PSoC5/USBFS_std.c **** * 88:.\Generated_Source\PSoC5/USBFS_std.c **** *******************************************************************************/ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 3 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 3 89:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 USBFS_HandleStandardRqst(void) @@ -178,7 +178,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 143:.\Generated_Source\PSoC5/USBFS_std.c **** #if defined(USBFS_ENABLE_MSOS_STRING) 144:.\Generated_Source\PSoC5/USBFS_std.c **** if( CY_GET_REG8(USBFS_wValueLo) == USBFS_STRING_MSOS ) 145:.\Generated_Source\PSoC5/USBFS_std.c **** { - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 4 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 4 146:.\Generated_Source\PSoC5/USBFS_std.c **** pStr = (volatile uint8 *)&USBFS_MSOS_DESCRIPTOR[0u]; @@ -238,7 +238,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 200:.\Generated_Source\PSoC5/USBFS_std.c **** default: /* requestHandled is initialized as FALSE by default */ 201:.\Generated_Source\PSoC5/USBFS_std.c **** break; 202:.\Generated_Source\PSoC5/USBFS_std.c **** } - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 5 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 5 203:.\Generated_Source\PSoC5/USBFS_std.c **** break; @@ -298,7 +298,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 257:.\Generated_Source\PSoC5/USBFS_std.c **** requestHandled = USBFS_ClearEndpointHalt(); 258:.\Generated_Source\PSoC5/USBFS_std.c **** } 259:.\Generated_Source\PSoC5/USBFS_std.c **** break; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 6 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 6 260:.\Generated_Source\PSoC5/USBFS_std.c **** case USBFS_RQST_RCPT_DEV: @@ -358,7 +358,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 314:.\Generated_Source\PSoC5/USBFS_std.c **** } 315:.\Generated_Source\PSoC5/USBFS_std.c **** return(requestHandled); 316:.\Generated_Source\PSoC5/USBFS_std.c **** } - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 7 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 7 317:.\Generated_Source\PSoC5/USBFS_std.c **** @@ -418,7 +418,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 371:.\Generated_Source\PSoC5/USBFS_std.c **** * This routine configures hardware registers from the variables. 372:.\Generated_Source\PSoC5/USBFS_std.c **** * It is called from USBFS_Config() function and from RestoreConfig 373:.\Generated_Source\PSoC5/USBFS_std.c **** * after Wakeup. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 8 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 8 374:.\Generated_Source\PSoC5/USBFS_std.c **** * @@ -478,7 +478,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 400:.\Generated_Source\PSoC5/USBFS_std.c **** #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ 401:.\Generated_Source\PSoC5/USBFS_std.c **** 402:.\Generated_Source\PSoC5/USBFS_std.c **** if(USBFS_EP[ep].epMode != USBFS_MODE_DISABLE) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 9 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 9 53 .loc 1 402 0 @@ -538,7 +538,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 84 003c 5818 adds r0, r3, r1 85 003e 1449 ldr r1, .L10 86 0040 04FB0211 mla r1, r4, r2, r1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 10 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 10 87 0044 0C89 ldrh r4, [r1, #8] @@ -598,7 +598,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 125 007e CB88 ldrh r3, [r1, #6] 126 0080 C3F30721 ubfx r1, r3, #8, #8 127 0084 0170 strb r1, [r0, #0] - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 11 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 11 128 0086 BDE7 b .L2 @@ -658,7 +658,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 455:.\Generated_Source\PSoC5/USBFS_std.c **** ******************************************************************************** 456:.\Generated_Source\PSoC5/USBFS_std.c **** * 457:.\Generated_Source\PSoC5/USBFS_std.c **** * Summary: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 12 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 12 458:.\Generated_Source\PSoC5/USBFS_std.c **** * This routine configures endpoints for the entire configuration by scanning @@ -718,7 +718,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 512:.\Generated_Source\PSoC5/USBFS_std.c **** /* Init Endpoints and Device Status if configured */ 513:.\Generated_Source\PSoC5/USBFS_std.c **** if(USBFS_configuration > 0u) 514:.\Generated_Source\PSoC5/USBFS_std.c **** { - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 13 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 13 515:.\Generated_Source\PSoC5/USBFS_std.c **** pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); @@ -778,7 +778,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 569:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ? 570:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT; 571:.\Generated_Source\PSoC5/USBFS_std.c **** #if defined(USBFS_ENABLE_CDC_CLASS) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 14 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 14 572:.\Generated_Source\PSoC5/USBFS_std.c **** if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) || @@ -838,7 +838,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 626:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_cdc_data_in_ep = i; 627:.\Generated_Source\PSoC5/USBFS_std.c **** } 628:.\Generated_Source\PSoC5/USBFS_std.c **** #endif /* End USBFS_ENABLE_CDC_CLASS*/ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 15 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 15 629:.\Generated_Source\PSoC5/USBFS_std.c **** #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \ @@ -898,7 +898,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 683:.\Generated_Source\PSoC5/USBFS_std.c **** /* Configure interface number for each EP*/ 684:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[pEP->addr & USBFS_DIR_UNUSED].interface = pEP->interface; 685:.\Generated_Source\PSoC5/USBFS_std.c **** pEP = &pEP[1u]; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 16 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 16 686:.\Generated_Source\PSoC5/USBFS_std.c **** } @@ -958,7 +958,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 740:.\Generated_Source\PSoC5/USBFS_std.c **** ep = pTmp->c; /* For this table, c is the number of endpoints configurations */ 741:.\Generated_Source\PSoC5/USBFS_std.c **** 742:.\Generated_Source\PSoC5/USBFS_std.c **** /* Do not touch EP which doesn't need reconfiguration */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 17 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 17 743:.\Generated_Source\PSoC5/USBFS_std.c **** /* When Alt setting changed, the only required endpoints need to be reconfigured */ @@ -1018,7 +1018,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 797:.\Generated_Source\PSoC5/USBFS_std.c **** /* Once dyn_config_rdy bit is set, FW can change the EP configuration. */ 798:.\Generated_Source\PSoC5/USBFS_std.c **** /* Change EP Type with new direction */ 799:.\Generated_Source\PSoC5/USBFS_std.c **** if((pEP->addr & USBFS_DIR_IN) == 0u) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 18 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 18 800:.\Generated_Source\PSoC5/USBFS_std.c **** { @@ -1078,7 +1078,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 162 @ args = 0, pretend = 0, frame = 0 163 @ frame_needed = 0, uses_anonymous_args = 0 164 @ link register save eliminated. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 19 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 19 165 .LVL8: @@ -1138,7 +1138,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 208 .cfi_offset 14, -4 736:.\Generated_Source\PSoC5/USBFS_std.c **** if(USBFS_configuration > 0u) 209 .loc 1 736 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 20 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 20 210 0002 3D4B ldr r3, .L28 @@ -1198,7 +1198,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 251 0032 13F8074C ldrb r4, [r3, #-7] @ zero_extendqisi2 252 0036 8C42 cmp r4, r1 253 0038 58D1 bne .L18 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 21 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 21 752:.\Generated_Source\PSoC5/USBFS_std.c **** (pEP->interface == CY_GET_REG8(USBFS_wIndexLo))) @@ -1258,7 +1258,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 296 0076 0027 movs r7, #0 297 0078 6770 strb r7, [r4, #1] 768:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ? - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 22 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 22 298 .loc 1 768 0 @@ -1318,7 +1318,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 342 .loc 1 818 0 343 00c0 D688 ldrh r6, [r2, #6] 344 00c2 154C ldr r4, .L28+32 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 23 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 23 345 00c4 F6B2 uxtb r6, r6 @@ -1378,7 +1378,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 395 .LFE3: 396 .size USBFS_ConfigAltChanged, .-USBFS_ConfigAltChanged 397 .section .text.USBFS_GetDeviceTablePtr,"ax",%progbits - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 24 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 24 398 .align 1 @@ -1438,7 +1438,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 430 .thumb_func 431 .type USBFS_GetInterfaceClassTablePtr, %function 432 USBFS_GetInterfaceClassTablePtr: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 25 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 25 433 .LFB6: @@ -1498,7 +1498,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 913:.\Generated_Source\PSoC5/USBFS_std.c **** } 458 .loc 1 913 0 459 0016 4069 ldr r0, [r0, #20] - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 26 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 26 460 0018 08BD pop {r3, pc} @@ -1558,7 +1558,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 507 .loc 1 497 0 discriminator 2 508 0016 02F10804 add r4, r2, #8 494:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_PENDING; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 27 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 27 509 .loc 1 494 0 discriminator 2 @@ -1618,7 +1618,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 550 004e 444B ldr r3, .L68+16 551 0050 1CB1 cbz r4, .L40 520:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_deviceStatus |= USBFS_DEVICE_STATUS_SELF_POWERED; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 28 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 28 552 .loc 1 520 0 @@ -1678,7 +1678,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 596 008c 1FFA8EFC uxth ip, lr 597 0090 BC45 cmp ip, r7 608:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[i].bufferSize = pEP->bufferSize; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 29 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 29 598 .loc 1 608 0 @@ -1738,7 +1738,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 642 .L65: 643 00d8 6E71 strb r6, [r5, #5] 662:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[i].addr = pEP->addr; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 30 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 30 644 .loc 1 662 0 @@ -1798,7 +1798,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 690 011e 8872 strb r0, [r1, #10] 681:.\Generated_Source\PSoC5/USBFS_std.c **** for (i = 0u; i < ep; i++) 691 .loc 1 681 0 discriminator 2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 31 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 31 692 0120 D2B2 uxtb r2, r2 @@ -1858,7 +1858,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 736 0158 00000000 .word USBFS_interfaceSetting_last 737 015c 00000000 .word USBFS_configuration 738 0160 00000000 .word USBFS_deviceStatus - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 32 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 32 739 0164 00000000 .word USBFS_interfaceClass @@ -1918,7 +1918,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 765 0008 0729 cmp r1, #7 766 000a 14D8 bhi .L70 939:.\Generated_Source\PSoC5/USBFS_std.c **** ri = ((ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 33 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 33 767 .loc 1 939 0 @@ -1978,7 +1978,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 804 .align 1 805 .global USBFS_SetEndpointHalt 806 .thumb - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 34 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 34 807 .thumb_func @@ -2038,7 +2038,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 828 000e 1AD8 bhi .L77 989:.\Generated_Source\PSoC5/USBFS_std.c **** ri = ((ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); 829 .loc 1 989 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 35 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 35 830 0010 0301 lsls r3, r0, #4 @@ -2098,7 +2098,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1012:.\Generated_Source\PSoC5/USBFS_std.c **** requestHandled = USBFS_InitNoDataControlTransfer(); 1013:.\Generated_Source\PSoC5/USBFS_std.c **** } 1014:.\Generated_Source\PSoC5/USBFS_std.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 36 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 36 1015:.\Generated_Source\PSoC5/USBFS_std.c **** return(requestHandled); @@ -2158,7 +2158,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 893 .LVL71: 894 0000 10B5 push {r4, lr} 895 .LCFI4: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 37 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 37 896 .cfi_def_cfa_offset 8 @@ -2218,7 +2218,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 931 002c 545C ldrb r4, [r2, r1] @ zero_extendqisi2 932 002e 04F07F04 and r4, r4, #127 933 0032 5454 strb r4, [r2, r1] - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 38 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 38 1055:.\Generated_Source\PSoC5/USBFS_std.c **** (reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri)) & (uint8)~USBFS_EPX_CNT_DATA_TOGGLE); @@ -2278,7 +2278,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1078:.\Generated_Source\PSoC5/USBFS_std.c **** else /* Mark endpoint as empty, so it will be reloaded */ 1079:.\Generated_Source\PSoC5/USBFS_std.c **** { 1080:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_ACK_OUT); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 39 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 39 964 .loc 1 1080 0 @@ -2338,7 +2338,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1102:.\Generated_Source\PSoC5/USBFS_std.c **** * 1103:.\Generated_Source\PSoC5/USBFS_std.c **** * Reentrant: 1104:.\Generated_Source\PSoC5/USBFS_std.c **** * No. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 40 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 40 1105:.\Generated_Source\PSoC5/USBFS_std.c **** * @@ -2398,7 +2398,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1126:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_interfaceSetting_last[interfaceNum] = USBFS_interfaceSetting[interfaceNum]; 1028 .loc 1 1126 0 is_stmt 1 1029 001c 074B ldr r3, .L96+8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 41 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 41 1030 .LVL81: @@ -2458,7 +2458,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1075 .LVL85: 1076 0000 10B5 push {r4, lr} 1077 .LCFI6: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 42 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 42 1078 .cfi_def_cfa_offset 8 @@ -2518,7 +2518,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1125 .loc 1 114 0 1126 004c 1223 movs r3, #18 113:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 43 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 43 1127 .loc 1 113 0 @@ -2578,7 +2578,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1172 .LVL90: 1173 .L108: 133:.\Generated_Source\PSoC5/USBFS_std.c **** while ( (CY_GET_REG8(USBFS_wValueLo) > nStr) && (*pStr != 0u) ) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 44 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 44 1174 .loc 1 133 0 discriminator 1 @@ -2638,7 +2638,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1218 .LVL97: 1219 .L112: 169:.\Generated_Source\PSoC5/USBFS_std.c **** if (*pStr != 0u) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 45 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 45 1220 .loc 1 169 0 @@ -2698,7 +2698,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1262 .loc 1 187 0 1263 00fa 1870 strb r0, [r3, #0] 1264 00fc 06E0 b .L146 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 46 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 46 1265 .L116: @@ -2758,7 +2758,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 221:.\Generated_Source\PSoC5/USBFS_std.c **** switch (CY_GET_REG8(USBFS_bRequest)) 1306 .loc 1 221 0 1307 012a 0378 ldrb r3, [r0, #0] @ zero_extendqisi2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 47 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 47 1308 012c 581E subs r0, r3, #1 @@ -2818,7 +2818,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 237:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_interfaceNumber = interfaceNumber; 1354 .loc 1 237 0 1355 0174 314A ldr r2, .L151+72 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 48 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 48 236:.\Generated_Source\PSoC5/USBFS_std.c **** interfaceNumber = CY_GET_REG8(USBFS_wIndexLo); @@ -2878,7 +2878,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1397 .LVL105: 1398 .L125: 262:.\Generated_Source\PSoC5/USBFS_std.c **** if (CY_GET_REG8(USBFS_wValueLo) == USBFS_DEVICE_REMOTE_WAKEUP) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 49 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 49 1399 .loc 1 262 0 @@ -2938,7 +2938,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1446 01f4 00000000 .word USBFS_currentTD 1447 01f8 00600040 .word 1073766400 1448 01fc 01600040 .word 1073766401 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 50 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 50 1449 0200 03600040 .word 1073766403 @@ -2998,7 +2998,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1494 0264 10BD pop {r4, pc} 1495 .L154: 1496 0266 00BF .align 2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 51 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 51 1497 .L153: @@ -3026,10 +3026,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1519 0006 00000000 .4byte .Ldebug_abbrev0 1520 000a 04 .byte 0x4 1521 000b 01 .uleb128 0x1 - 1522 000c 59030000 .4byte .LASF83 + 1522 000c 6A030000 .4byte .LASF83 1523 0010 01 .byte 0x1 - 1524 0011 E2030000 .4byte .LASF84 - 1525 0015 6A010000 .4byte .LASF85 + 1524 0011 F3030000 .4byte .LASF84 + 1525 0015 22020000 .4byte .LASF85 1526 0019 00000000 .4byte .Ldebug_ranges0+0 1527 001d 00000000 .4byte 0 1528 0021 00000000 .4byte 0 @@ -3041,15 +3041,15 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1534 0030 02 .uleb128 0x2 1535 0031 01 .byte 0x1 1536 0032 08 .byte 0x8 - 1537 0033 A7030000 .4byte .LASF1 + 1537 0033 B8030000 .4byte .LASF1 1538 0037 02 .uleb128 0x2 1539 0038 02 .byte 0x2 1540 0039 05 .byte 0x5 - 1541 003a B5030000 .4byte .LASF2 + 1541 003a C6030000 .4byte .LASF2 1542 003e 02 .uleb128 0x2 1543 003f 02 .byte 0x2 1544 0040 07 .byte 0x7 - 1545 0041 E4010000 .4byte .LASF3 + 1545 0041 C4010000 .4byte .LASF3 1546 0045 02 .uleb128 0x2 1547 0046 04 .byte 0x4 1548 0047 05 .byte 0x5 @@ -3057,8 +3057,8 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1550 004c 02 .uleb128 0x2 1551 004d 04 .byte 0x4 1552 004e 07 .byte 0x7 - 1553 004f B2010000 .4byte .LASF5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 52 + 1553 004f 92010000 .4byte .LASF5 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 52 1554 0053 02 .uleb128 0x2 @@ -3076,7 +3076,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1566 0068 02 .uleb128 0x2 1567 0069 04 .byte 0x4 1568 006a 07 .byte 0x7 - 1569 006b A5010000 .4byte .LASF8 + 1569 006b 85010000 .4byte .LASF8 1570 006f 04 .uleb128 0x4 1571 0070 1E010000 .4byte .LASF9 1572 0074 02 .byte 0x2 @@ -3090,7 +3090,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1580 0085 02 .uleb128 0x2 1581 0086 04 .byte 0x4 1582 0087 04 .byte 0x4 - 1583 0088 3A030000 .4byte .LASF11 + 1583 0088 4B030000 .4byte .LASF11 1584 008c 02 .uleb128 0x2 1585 008d 08 .byte 0x8 1586 008e 04 .byte 0x4 @@ -3098,9 +3098,9 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1588 0093 02 .uleb128 0x2 1589 0094 01 .byte 0x1 1590 0095 08 .byte 0x8 - 1591 0096 76040000 .4byte .LASF13 + 1591 0096 87040000 .4byte .LASF13 1592 009a 04 .uleb128 0x4 - 1593 009b A2030000 .4byte .LASF14 + 1593 009b B3030000 .4byte .LASF14 1594 009f 02 .byte 0x2 1595 00a0 F0 .byte 0xf0 1596 00a1 A5000000 .4byte 0xa5 @@ -3109,16 +3109,16 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1599 00aa 02 .uleb128 0x2 1600 00ab 04 .byte 0x4 1601 00ac 07 .byte 0x7 - 1602 00ad 86020000 .4byte .LASF15 + 1602 00ad 97020000 .4byte .LASF15 1603 00b1 06 .uleb128 0x6 1604 00b2 0C .byte 0xc 1605 00b3 03 .byte 0x3 1606 00b4 79 .byte 0x79 1607 00b5 38010000 .4byte 0x138 1608 00b9 07 .uleb128 0x7 - 1609 00ba A5020000 .4byte .LASF16 + 1609 00ba B6020000 .4byte .LASF16 1610 00be 03 .byte 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 53 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 53 1611 00bf 7B .byte 0x7b @@ -3127,7 +3127,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1614 00c5 23 .byte 0x23 1615 00c6 00 .uleb128 0 1616 00c7 07 .uleb128 0x7 - 1617 00c8 40030000 .4byte .LASF17 + 1617 00c8 51030000 .4byte .LASF17 1618 00cc 03 .byte 0x3 1619 00cd 7C .byte 0x7c 1620 00ce 6F000000 .4byte 0x6f @@ -3135,7 +3135,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1622 00d3 23 .byte 0x23 1623 00d4 01 .uleb128 0x1 1624 00d5 07 .uleb128 0x7 - 1625 00d6 70020000 .4byte .LASF18 + 1625 00d6 81020000 .4byte .LASF18 1626 00da 03 .byte 0x3 1627 00db 7D .byte 0x7d 1628 00dc 6F000000 .4byte 0x6f @@ -3159,7 +3159,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1646 00fd 23 .byte 0x23 1647 00fe 04 .uleb128 0x4 1648 00ff 07 .uleb128 0x7 - 1649 0100 9E010000 .4byte .LASF21 + 1649 0100 7E010000 .4byte .LASF21 1650 0104 03 .byte 0x3 1651 0105 80 .byte 0x80 1652 0106 6F000000 .4byte 0x6f @@ -3167,7 +3167,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1654 010b 23 .byte 0x23 1655 010c 05 .uleb128 0x5 1656 010d 07 .uleb128 0x7 - 1657 010e 95040000 .4byte .LASF22 + 1657 010e A6040000 .4byte .LASF22 1658 0112 03 .byte 0x3 1659 0113 81 .byte 0x81 1660 0114 7A000000 .4byte 0x7a @@ -3175,10 +3175,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1662 0119 23 .byte 0x23 1663 011a 06 .uleb128 0x6 1664 011b 07 .uleb128 0x7 - 1665 011c 7B040000 .4byte .LASF23 + 1665 011c 8C040000 .4byte .LASF23 1666 0120 03 .byte 0x3 1667 0121 82 .byte 0x82 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 54 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 54 1668 0122 7A000000 .4byte 0x7a @@ -3186,7 +3186,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1670 0127 23 .byte 0x23 1671 0128 08 .uleb128 0x8 1672 0129 07 .uleb128 0x7 - 1673 012a FE010000 .4byte .LASF24 + 1673 012a DE010000 .4byte .LASF24 1674 012e 03 .byte 0x3 1675 012f 83 .byte 0x83 1676 0130 6F000000 .4byte 0x6f @@ -3195,7 +3195,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1679 0136 0A .uleb128 0xa 1680 0137 00 .byte 0 1681 0138 04 .uleb128 0x4 - 1682 0139 1E040000 .4byte .LASF25 + 1682 0139 2F040000 .4byte .LASF25 1683 013d 03 .byte 0x3 1684 013e 84 .byte 0x84 1685 013f B1000000 .4byte 0xb1 @@ -3205,7 +3205,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1689 0146 86 .byte 0x86 1690 0147 A0010000 .4byte 0x1a0 1691 014b 07 .uleb128 0x7 - 1692 014c FE010000 .4byte .LASF24 + 1692 014c DE010000 .4byte .LASF24 1693 0150 03 .byte 0x3 1694 0151 88 .byte 0x88 1695 0152 6F000000 .4byte 0x6f @@ -3213,7 +3213,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1697 0157 23 .byte 0x23 1698 0158 00 .uleb128 0 1699 0159 07 .uleb128 0x7 - 1700 015a 6B040000 .4byte .LASF26 + 1700 015a 7C040000 .4byte .LASF26 1701 015e 03 .byte 0x3 1702 015f 89 .byte 0x89 1703 0160 6F000000 .4byte 0x6f @@ -3229,7 +3229,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1713 0173 23 .byte 0x23 1714 0174 02 .uleb128 0x2 1715 0175 07 .uleb128 0x7 - 1716 0176 60040000 .4byte .LASF27 + 1716 0176 71040000 .4byte .LASF27 1717 017a 03 .byte 0x3 1718 017b 8B .byte 0x8b 1719 017c 6F000000 .4byte 0x6f @@ -3237,8 +3237,8 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1721 0181 23 .byte 0x23 1722 0182 03 .uleb128 0x3 1723 0183 07 .uleb128 0x7 - 1724 0184 7B040000 .4byte .LASF23 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 55 + 1724 0184 8C040000 .4byte .LASF23 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 55 1725 0188 03 .byte 0x3 @@ -3248,7 +3248,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1729 018f 23 .byte 0x23 1730 0190 04 .uleb128 0x4 1731 0191 07 .uleb128 0x7 - 1732 0192 21050000 .4byte .LASF28 + 1732 0192 32050000 .4byte .LASF28 1733 0196 03 .byte 0x3 1734 0197 8D .byte 0x8d 1735 0198 6F000000 .4byte 0x6f @@ -3267,7 +3267,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1748 01ae 90 .byte 0x90 1749 01af D0010000 .4byte 0x1d0 1750 01b3 07 .uleb128 0x7 - 1751 01b4 02050000 .4byte .LASF30 + 1751 01b4 13050000 .4byte .LASF30 1752 01b8 03 .byte 0x3 1753 01b9 92 .byte 0x92 1754 01ba 6F000000 .4byte 0x6f @@ -3275,7 +3275,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1756 01bf 23 .byte 0x23 1757 01c0 00 .uleb128 0 1758 01c1 07 .uleb128 0x7 - 1759 01c2 E7040000 .4byte .LASF31 + 1759 01c2 F8040000 .4byte .LASF31 1760 01c6 03 .byte 0x3 1761 01c7 93 .byte 0x93 1762 01c8 7A000000 .4byte 0x7a @@ -3284,7 +3284,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1765 01ce 02 .uleb128 0x2 1766 01cf 00 .byte 0 1767 01d0 04 .uleb128 0x4 - 1768 01d1 FF020000 .4byte .LASF32 + 1768 01d1 10030000 .4byte .LASF32 1769 01d5 03 .byte 0x3 1770 01d6 94 .byte 0x94 1771 01d7 AB010000 .4byte 0x1ab @@ -3298,7 +3298,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1779 01e8 03 .byte 0x3 1780 01e9 98 .byte 0x98 1781 01ea 7A000000 .4byte 0x7a - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 56 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 56 1782 01ee 02 .byte 0x2 @@ -3328,7 +3328,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1806 0215 04 .byte 0x4 1807 0216 D0010000 .4byte 0x1d0 1808 021a 04 .uleb128 0x4 - 1809 021b BF030000 .4byte .LASF36 + 1809 021b D0030000 .4byte .LASF36 1810 021f 03 .byte 0x3 1811 0220 9B .byte 0x9b 1812 0221 DB010000 .4byte 0x1db @@ -3346,7 +3346,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1824 0237 23 .byte 0x23 1825 0238 00 .uleb128 0 1826 0239 07 .uleb128 0x7 - 1827 023a 94020000 .4byte .LASF37 + 1827 023a A5020000 .4byte .LASF37 1828 023e 03 .byte 0x3 1829 023f A1 .byte 0xa1 1830 0240 48020000 .4byte 0x248 @@ -3358,17 +3358,17 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1836 0249 04 .byte 0x4 1837 024a 4E020000 .4byte 0x24e 1838 024e 0A .uleb128 0xa - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 57 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 57 1839 024f 04 .uleb128 0x4 - 1840 0250 56050000 .4byte .LASF38 + 1840 0250 67050000 .4byte .LASF38 1841 0254 03 .byte 0x3 1842 0255 A2 .byte 0xa2 1843 0256 25020000 .4byte 0x225 1844 025a 0B .uleb128 0xb 1845 025b 01 .byte 0x1 - 1846 025c A0040000 .4byte .LASF79 + 1846 025c B1040000 .4byte .LASF79 1847 0260 01 .byte 0x1 1848 0261 6E03 .2byte 0x36e 1849 0263 01 .byte 0x1 @@ -3405,7 +3405,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1880 02ac 00 .byte 0 1881 02ad 0F .uleb128 0xf 1882 02ae 01 .byte 0x1 - 1883 02af CA030000 .4byte .LASF44 + 1883 02af DB030000 .4byte .LASF44 1884 02b3 01 .byte 0x1 1885 02b4 5103 .2byte 0x351 1886 02b6 01 .byte 0x1 @@ -3418,7 +3418,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1893 02c6 01 .byte 0x1 1894 02c7 EA020000 .4byte 0x2ea 1895 02cb 10 .uleb128 0x10 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 58 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 58 1896 02cc 6300 .ascii "c\000" @@ -3427,7 +3427,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1899 02d1 6F000000 .4byte 0x6f 1900 02d5 8C000000 .4byte .LLST3 1901 02d9 11 .uleb128 0x11 - 1902 02da 8F020000 .4byte .LASF39 + 1902 02da A0020000 .4byte .LASF39 1903 02de 01 .byte 0x1 1904 02df 5503 .2byte 0x355 1905 02e1 69020000 .4byte 0x269 @@ -3435,7 +3435,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1907 02e9 00 .byte 0 1908 02ea 0D .uleb128 0xd 1909 02eb 01 .byte 0x1 - 1910 02ec E8020000 .4byte .LASF41 + 1910 02ec F9020000 .4byte .LASF41 1911 02f0 01 .byte 0x1 1912 02f1 D302 .2byte 0x2d3 1913 02f3 01 .byte 0x1 @@ -3451,7 +3451,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1923 030c 6F000000 .4byte 0x6f 1924 0310 E6000000 .4byte .LLST6 1925 0314 11 .uleb128 0x11 - 1926 0315 FB040000 .4byte .LASF42 + 1926 0315 0C050000 .4byte .LASF42 1927 0319 01 .byte 0x1 1928 031a D602 .2byte 0x2d6 1929 031c 6F000000 .4byte 0x6f @@ -3463,7 +3463,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1935 032a 6F000000 .4byte 0x6f 1936 032e 2A010000 .4byte .LLST8 1937 0332 11 .uleb128 0x11 - 1938 0333 F3040000 .4byte .LASF43 + 1938 0333 04050000 .4byte .LASF43 1939 0337 01 .byte 0x1 1940 0338 D802 .2byte 0x2d8 1941 033a 6F000000 .4byte 0x6f @@ -3475,10 +3475,10 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1947 0349 6F000000 .4byte 0x6f 1948 034d A1010000 .4byte .LLST10 1949 0351 11 .uleb128 0x11 - 1950 0352 8F020000 .4byte .LASF39 + 1950 0352 A0020000 .4byte .LASF39 1951 0356 01 .byte 0x1 1952 0357 DB02 .2byte 0x2db - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 59 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 59 1953 0359 69020000 .4byte 0x269 @@ -3508,7 +3508,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1977 0396 01 .byte 0x1 1978 0397 14 .uleb128 0x14 1979 0398 01 .byte 0x1 - 1980 0399 C4010000 .4byte .LASF45 + 1980 0399 A4010000 .4byte .LASF45 1981 039d 01 .byte 0x1 1982 039e 8503 .2byte 0x385 1983 03a0 01 .byte 0x1 @@ -3519,13 +3519,13 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 1988 03b1 01 .byte 0x1 1989 03b2 E0030000 .4byte 0x3e0 1990 03b6 11 .uleb128 0x11 - 1991 03b7 8F020000 .4byte .LASF39 + 1991 03b7 A0020000 .4byte .LASF39 1992 03bb 01 .byte 0x1 1993 03bc 8803 .2byte 0x388 1994 03be 69020000 .4byte 0x269 1995 03c2 24020000 .4byte .LLST14 1996 03c6 11 .uleb128 0x11 - 1997 03c7 D3020000 .4byte .LASF46 + 1997 03c7 E4020000 .4byte .LASF46 1998 03cb 01 .byte 0x1 1999 03cc 8903 .2byte 0x389 2000 03ce 6F000000 .4byte 0x6f @@ -3538,7 +3538,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 2007 03e1 04 .byte 0x4 2008 03e2 E6030000 .4byte 0x3e6 2009 03e6 0C .uleb128 0xc - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 60 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 60 2010 03e7 6F000000 .4byte 0x6f @@ -3566,7 +3566,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 2032 041d 6F000000 .4byte 0x6f 2033 0421 AD020000 .4byte .LLST18 2034 0425 11 .uleb128 0x11 - 2035 0426 FB040000 .4byte .LASF42 + 2035 0426 0C050000 .4byte .LASF42 2036 042a 01 .byte 0x1 2037 042b DE01 .2byte 0x1de 2038 042d 6F000000 .4byte 0x6f @@ -3578,27 +3578,27 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 2044 043b 6F000000 .4byte 0x6f 2045 043f 1B030000 .4byte .LLST20 2046 0443 11 .uleb128 0x11 - 2047 0444 F3040000 .4byte .LASF43 + 2047 0444 04050000 .4byte .LASF43 2048 0448 01 .byte 0x1 2049 0449 E001 .2byte 0x1e0 2050 044b 6F000000 .4byte 0x6f 2051 044f 5E030000 .4byte .LLST21 2052 0453 11 .uleb128 0x11 - 2053 0454 F7010000 .4byte .LASF49 + 2053 0454 D7010000 .4byte .LASF49 2054 0458 01 .byte 0x1 2055 0459 E101 .2byte 0x1e1 2056 045b E0030000 .4byte 0x3e0 2057 045f 9E030000 .4byte .LLST22 2058 0463 11 .uleb128 0x11 - 2059 0464 9B020000 .4byte .LASF50 + 2059 0464 AC020000 .4byte .LASF50 2060 0468 01 .byte 0x1 2061 0469 E301 .2byte 0x1e3 2062 046b 7A000000 .4byte 0x7a 2063 046f B2030000 .4byte .LLST23 2064 0473 11 .uleb128 0x11 - 2065 0474 8F020000 .4byte .LASF39 + 2065 0474 A0020000 .4byte .LASF39 2066 0478 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 61 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 61 2067 0479 E601 .2byte 0x1e6 @@ -3658,7 +3658,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 2121 04f4 0F .uleb128 0xf 2122 04f5 01 .byte 0x1 2123 04f6 4E010000 .4byte .LASF52 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 62 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 62 2124 04fa 01 .byte 0x1 @@ -3685,7 +3685,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 2145 0528 6F000000 .4byte 0x6f 2146 052c 7F040000 .4byte .LLST29 2147 0530 1A .uleb128 0x1a - 2148 0531 86040000 .4byte .LASF53 + 2148 0531 97040000 .4byte .LASF53 2149 0535 01 .byte 0x1 2150 0536 D903 .2byte 0x3d9 2151 0538 6F000000 .4byte 0x6f @@ -3718,12 +3718,12 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 2178 057a 01 .byte 0x1 2179 057b 0F04 .2byte 0x40f 2180 057d 6F000000 .4byte 0x6f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 63 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 63 2181 0581 01050000 .4byte .LLST32 2182 0585 1A .uleb128 0x1a - 2183 0586 86040000 .4byte .LASF53 + 2183 0586 97040000 .4byte .LASF53 2184 058a 01 .byte 0x1 2185 058b 1004 .2byte 0x410 2186 058d 6F000000 .4byte 0x6f @@ -3735,7 +3735,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 2192 059c 00 .byte 0 2193 059d 14 .uleb128 0x14 2194 059e 01 .byte 0x1 - 2195 059f 08020000 .4byte .LASF55 + 2195 059f E8010000 .4byte .LASF55 2196 05a3 01 .byte 0x1 2197 05a4 5304 .2byte 0x453 2198 05a6 01 .byte 0x1 @@ -3746,26 +3746,26 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 2203 05b7 01 .byte 0x1 2204 05b8 04060000 .4byte 0x604 2205 05bc 11 .uleb128 0x11 - 2206 05bd 86040000 .4byte .LASF53 + 2206 05bd 97040000 .4byte .LASF53 2207 05c1 01 .byte 0x1 2208 05c2 5504 .2byte 0x455 2209 05c4 6F000000 .4byte 0x6f 2210 05c8 47050000 .4byte .LLST34 2211 05cc 1B .uleb128 0x1b - 2212 05cd 19030000 .4byte .LASF56 + 2212 05cd 2A030000 .4byte .LASF56 2213 05d1 01 .byte 0x1 2214 05d2 5604 .2byte 0x456 2215 05d4 6F000000 .4byte 0x6f 2216 05d8 01 .byte 0x1 2217 05d9 54 .byte 0x54 2218 05da 11 .uleb128 0x11 - 2219 05db 8F020000 .4byte .LASF39 + 2219 05db A0020000 .4byte .LASF39 2220 05df 01 .byte 0x1 2221 05e0 5704 .2byte 0x457 2222 05e2 69020000 .4byte 0x269 2223 05e6 66050000 .4byte .LLST35 2224 05ea 11 .uleb128 0x11 - 2225 05eb D3020000 .4byte .LASF46 + 2225 05eb E4020000 .4byte .LASF46 2226 05ef 01 .byte 0x1 2227 05f0 5804 .2byte 0x458 2228 05f2 6F000000 .4byte 0x6f @@ -3776,9 +3776,9 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 2233 0603 00 .byte 0 2234 0604 1C .uleb128 0x1c 2235 0605 01 .byte 0x1 - 2236 0606 3D050000 .4byte .LASF57 + 2236 0606 4E050000 .4byte .LASF57 2237 060a 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 64 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 64 2238 060b 59 .byte 0x59 @@ -3790,7 +3790,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 2244 061d 01 .byte 0x1 2245 061e FD060000 .4byte 0x6fd 2246 0622 1D .uleb128 0x1d - 2247 0623 86040000 .4byte .LASF53 + 2247 0623 97040000 .4byte .LASF53 2248 0627 01 .byte 0x1 2249 0628 5B .byte 0x5b 2250 0629 6F000000 .4byte 0x6f @@ -3802,19 +3802,19 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 2256 0638 6F000000 .4byte 0x6f 2257 063c E7050000 .4byte .LLST39 2258 0640 1D .uleb128 0x1d - 2259 0641 54030000 .4byte .LASF59 + 2259 0641 65030000 .4byte .LASF59 2260 0645 01 .byte 0x1 2261 0646 5E .byte 0x5e 2262 0647 0E020000 .4byte 0x20e 2263 064b FA050000 .4byte .LLST40 2264 064f 1D .uleb128 0x1d - 2265 0650 EE040000 .4byte .LASF60 + 2265 0650 FF040000 .4byte .LASF60 2266 0654 01 .byte 0x1 2267 0655 60 .byte 0x60 2268 0656 6F000000 .4byte 0x6f 2269 065a 3C060000 .4byte .LLST41 2270 065e 1D .uleb128 0x1d - 2271 065f 7A020000 .4byte .LASF61 + 2271 065f 8B020000 .4byte .LASF61 2272 0663 01 .byte 0x1 2273 0664 61 .byte 0x61 2274 0665 6F000000 .4byte 0x6f @@ -3828,7 +3828,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 2282 0679 03 .byte 0x3 2283 067a 00000000 .4byte USBFS_tBuffer.5008 2284 067e 1D .uleb128 0x1d - 2285 067f 8F020000 .4byte .LASF39 + 2285 067f A0020000 .4byte .LASF39 2286 0683 01 .byte 0x1 2287 0684 65 .byte 0x65 2288 0685 69020000 .4byte 0x269 @@ -3838,7 +3838,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 2292 0692 40000000 .4byte .LBB4 2293 0696 4A000000 .4byte .LBE4 2294 069a 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 65 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 65 2295 069b 70 .byte 0x70 @@ -3892,31 +3892,31 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 2343 070d 05 .uleb128 0x5 2344 070e FD060000 .4byte 0x6fd 2345 0712 22 .uleb128 0x22 - 2346 0713 53040000 .4byte .LASF63 + 2346 0713 64040000 .4byte .LASF63 2347 0717 03 .byte 0x3 2348 0718 1802 .2byte 0x218 2349 071a A5000000 .4byte 0xa5 2350 071e 01 .byte 0x1 2351 071f 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 66 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 66 2352 0720 22 .uleb128 0x22 - 2353 0721 8A010000 .4byte .LASF64 + 2353 0721 6A010000 .4byte .LASF64 2354 0725 03 .byte 0x3 2355 0726 1A02 .2byte 0x21a 2356 0728 A5000000 .4byte 0xa5 2357 072c 01 .byte 0x1 2358 072d 01 .byte 0x1 2359 072e 22 .uleb128 0x22 - 2360 072f 27020000 .4byte .LASF65 + 2360 072f 07020000 .4byte .LASF65 2361 0733 03 .byte 0x3 2362 0734 1B02 .2byte 0x21b 2363 0736 A5000000 .4byte 0xa5 2364 073a 01 .byte 0x1 2365 073b 01 .byte 0x1 2366 073c 22 .uleb128 0x22 - 2367 073d B8040000 .4byte .LASF66 + 2367 073d C9040000 .4byte .LASF66 2368 0741 03 .byte 0x3 2369 0742 1C02 .2byte 0x21c 2370 0744 A5000000 .4byte 0xa5 @@ -3930,7 +3930,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 2378 0758 11 .byte 0x11 2379 0759 00 .byte 0 2380 075a 23 .uleb128 0x23 - 2381 075b 26030000 .4byte .LASF67 + 2381 075b 37030000 .4byte .LASF67 2382 075f 04 .byte 0x4 2383 0760 1C .byte 0x1c 2384 0761 67070000 .4byte 0x767 @@ -3946,7 +3946,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 2394 077a 00 .byte 0 2395 077b 00 .byte 0 2396 077c 23 .uleb128 0x23 - 2397 077d AC020000 .4byte .LASF68 + 2397 077d BD020000 .4byte .LASF68 2398 0781 04 .byte 0x4 2399 0782 23 .byte 0x23 2400 0783 89070000 .4byte 0x789 @@ -3958,14 +3958,14 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 2406 078f 6F000000 .4byte 0x6f 2407 0793 9E070000 .4byte 0x79e 2408 0797 21 .uleb128 0x21 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 67 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 67 2409 0798 AA000000 .4byte 0xaa 2410 079c 09 .byte 0x9 2411 079d 00 .byte 0 2412 079e 23 .uleb128 0x23 - 2413 079f B8020000 .4byte .LASF69 + 2413 079f C9020000 .4byte .LASF69 2414 07a3 04 .byte 0x4 2415 07a4 24 .byte 0x24 2416 07a5 AB070000 .4byte 0x7ab @@ -3981,7 +3981,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 2426 07be 52 .byte 0x52 2427 07bf 00 .byte 0 2428 07c0 23 .uleb128 0x23 - 2429 07c1 57020000 .4byte .LASF70 + 2429 07c1 68020000 .4byte .LASF70 2430 07c5 04 .byte 0x4 2431 07c6 25 .byte 0x25 2432 07c7 CD070000 .4byte 0x7cd @@ -4004,7 +4004,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 2449 07ed 00 .byte 0 2450 07ee 00 .byte 0 2451 07ef 23 .uleb128 0x23 - 2452 07f0 07040000 .4byte .LASF72 + 2452 07f0 18040000 .4byte .LASF72 2453 07f4 04 .byte 0x4 2454 07f5 39 .byte 0x39 2455 07f6 FC070000 .4byte 0x7fc @@ -4013,12 +4013,12 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 2458 07fc 05 .uleb128 0x5 2459 07fd DF070000 .4byte 0x7df 2460 0801 23 .uleb128 0x23 - 2461 0802 CB040000 .4byte .LASF73 + 2461 0802 DC040000 .4byte .LASF73 2462 0806 04 .byte 0x4 2463 0807 3A .byte 0x3a 2464 0808 0E080000 .4byte 0x80e 2465 080c 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 68 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 68 2466 080d 01 .byte 0x1 @@ -4032,7 +4032,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 2474 081e 01 .byte 0x1 2475 081f 01 .byte 0x1 2476 0820 23 .uleb128 0x23 - 2477 0821 27050000 .4byte .LASF75 + 2477 0821 38050000 .4byte .LASF75 2478 0825 04 .byte 0x4 2479 0826 3C .byte 0x3c 2480 0827 2D080000 .4byte 0x82d @@ -4041,7 +4041,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 2483 082d 05 .uleb128 0x5 2484 082e DF070000 .4byte 0x7df 2485 0832 23 .uleb128 0x23 - 2486 0833 42020000 .4byte .LASF76 + 2486 0833 53020000 .4byte .LASF76 2487 0837 04 .byte 0x4 2488 0838 3D .byte 0x3d 2489 0839 E0030000 .4byte 0x3e0 @@ -4055,7 +4055,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 2497 084d 08 .byte 0x8 2498 084e 00 .byte 0 2499 084f 23 .uleb128 0x23 - 2500 0850 4B030000 .4byte .LASF77 + 2500 0850 5C030000 .4byte .LASF77 2501 0854 04 .byte 0x4 2502 0855 3F .byte 0x3f 2503 0856 5C080000 .4byte 0x85c @@ -4074,11 +4074,11 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 2516 086f 1A020000 .4byte 0x21a 2517 0873 24 .uleb128 0x24 2518 0874 01 .byte 0x1 - 2519 0875 33040000 .4byte .LASF80 + 2519 0875 44040000 .4byte .LASF80 2520 0879 04 .byte 0x4 2521 087a 63 .byte 0x63 2522 087b 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 69 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 69 2523 087c 6F000000 .4byte 0x6f @@ -4093,7 +4093,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 2532 088e 01 .byte 0x1 2533 088f 24 .uleb128 0x24 2534 0890 01 .byte 0x1 - 2535 0891 09050000 .4byte .LASF82 + 2535 0891 1A050000 .4byte .LASF82 2536 0895 04 .byte 0x4 2537 0896 B2 .byte 0xb2 2538 0897 01 .byte 0x1 @@ -4138,7 +4138,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 2577 0021 24 .uleb128 0x24 2578 0022 00 .byte 0 2579 0023 0B .uleb128 0xb - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 70 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 70 2580 0024 0B .uleb128 0xb @@ -4198,7 +4198,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 2634 005a 00 .byte 0 2635 005b 08 .uleb128 0x8 2636 005c 0F .uleb128 0xf - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 71 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 71 2637 005d 00 .byte 0 @@ -4258,7 +4258,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 2691 0093 2E .uleb128 0x2e 2692 0094 01 .byte 0x1 2693 0095 3F .uleb128 0x3f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 72 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 72 2694 0096 0C .uleb128 0xc @@ -4318,7 +4318,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 2748 00cd 01 .uleb128 0x1 2749 00ce 40 .uleb128 0x40 2750 00cf 0A .uleb128 0xa - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 73 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 73 2751 00d0 9742 .uleb128 0x2117 @@ -4378,7 +4378,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 2805 0109 40 .uleb128 0x40 2806 010a 0A .uleb128 0xa 2807 010b 9742 .uleb128 0x2117 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 74 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 74 2808 010d 0C .uleb128 0xc @@ -4438,7 +4438,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 2862 0146 00 .byte 0 2863 0147 00 .byte 0 2864 0148 17 .uleb128 0x17 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 75 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 75 2865 0149 8A8201 .uleb128 0x410a @@ -4498,7 +4498,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 2919 0186 13 .uleb128 0x13 2920 0187 1C .uleb128 0x1c 2921 0188 0B .uleb128 0xb - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 76 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 76 2922 0189 00 .byte 0 @@ -4558,7 +4558,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 2976 01c0 13 .uleb128 0x13 2977 01c1 02 .uleb128 0x2 2978 01c2 06 .uleb128 0x6 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 77 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 77 2979 01c3 00 .byte 0 @@ -4618,7 +4618,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 3033 01f9 0E .uleb128 0xe 3034 01fa 3A .uleb128 0x3a 3035 01fb 0B .uleb128 0xb - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 78 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 78 3036 01fc 3B .uleb128 0x3b @@ -4678,7 +4678,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 3090 000b 00 .sleb128 0 3091 000c 02000000 .4byte .LCFI0 3092 0010 B4000000 .4byte .LFE1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 79 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 79 3093 0014 0200 .2byte 0x2 @@ -4738,7 +4738,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 3147 009f 0400 .2byte 0x4 3148 00a1 F3 .byte 0xf3 3149 00a2 01 .uleb128 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 80 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 80 3150 00a3 50 .byte 0x50 @@ -4798,7 +4798,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 3204 011e 08 .byte 0x8 3205 011f 7F .byte 0x7f 3206 0120 1A .byte 0x1a - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 81 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 81 3207 0121 9F .byte 0x9f @@ -4858,7 +4858,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 3261 0199 00000000 .4byte 0 3262 019d 00000000 .4byte 0 3263 .LLST10: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 82 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 82 3264 01a1 50000000 .4byte .LVL17 @@ -4918,7 +4918,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 3317 022c 0100 .2byte 0x1 3318 022e 50 .byte 0x50 3319 022f 12000000 .4byte .LVL30 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 83 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 83 3320 0233 16000000 .4byte .LVL31 @@ -4978,7 +4978,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 3374 02a9 00000000 .4byte 0 3375 .LLST18: 3376 02ad 00000000 .4byte .LVL32 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 84 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 84 3377 02b1 04000000 .4byte .LVL33 @@ -5038,7 +5038,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 3431 0337 1E010000 .4byte .LVL52 3432 033b 0100 .2byte 0x1 3433 033d 52 .byte 0x52 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 85 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 85 3434 033e 1E010000 .4byte .LVL52 @@ -5098,7 +5098,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 3488 03ba 0200 .2byte 0x2 3489 03bc 30 .byte 0x30 3490 03bd 9F .byte 0x9f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 86 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 86 3491 03be 44010000 .4byte .LVL57 @@ -5158,7 +5158,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 3545 0447 34 .byte 0x34 3546 0448 24 .byte 0x24 3547 0449 9F .byte 0x9f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 87 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 87 3548 044a 14000000 .4byte .LVL62 @@ -5218,7 +5218,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 3602 04bb 00000000 .4byte 0 3603 04bf 00000000 .4byte 0 3604 .LLST30: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 88 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 88 3605 04c3 00000000 .4byte .LFB9 @@ -5278,7 +5278,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 3659 0543 00000000 .4byte 0 3660 .LLST34: 3661 0547 00000000 .4byte .LVL77 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 89 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 89 3662 054b 30000000 .4byte .LVL84 @@ -5338,7 +5338,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 3716 05cf 00000000 .4byte 0 3717 .LLST38: 3718 05d3 00000000 .4byte .LVL85 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 90 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 90 3719 05d7 62020000 .4byte .LVL111 @@ -5398,7 +5398,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 3773 .LLST42: 3774 0665 B0000000 .4byte .LVL94 3775 0669 B8000000 .4byte .LVL97 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 91 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 91 3776 066d 0100 .2byte 0x1 @@ -5458,7 +5458,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 3830 0024 20000000 .4byte .LFE6 3831 0028 00000000 .4byte .LFB2 3832 002c 68010000 .4byte .LFE2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 92 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 92 3833 0030 00000000 .4byte .LFB7 @@ -5518,7 +5518,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 3863 0069 61646472 .ascii "addr\000" 3863 00 3864 .LASF58: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 93 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 93 3865 006e 696E7465 .ascii "interfaceNumber\000" @@ -5578,7 +5578,7 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 3885 00 3886 .LASF9: 3887 011e 75696E74 .ascii "uint8\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 94 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 94 3887 3800 @@ -5604,310 +5604,311 @@ ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 1 3896 .LASF34: 3897 0164 70446174 .ascii "pData\000" 3897 6100 - 3898 .LASF85: - 3899 016a 573A5C53 .ascii "W:\\SCSI2SD\\USB_Bootloader.cydsn\000" - 3899 43534932 - 3899 53445C55 - 3899 53425F42 - 3899 6F6F746C - 3900 .LASF64: - 3901 018a 55534246 .ascii "USBFS_configuration\000" - 3901 535F636F - 3901 6E666967 - 3901 75726174 - 3901 696F6E00 - 3902 .LASF21: - 3903 019e 65704D6F .ascii "epMode\000" - 3903 646500 - 3904 .LASF8: - 3905 01a5 756E7369 .ascii "unsigned int\000" - 3905 676E6564 - 3905 20696E74 - 3905 00 - 3906 .LASF5: - 3907 01b2 6C6F6E67 .ascii "long unsigned int\000" - 3907 20756E73 - 3907 69676E65 - 3907 6420696E - 3907 7400 - 3908 .LASF45: - 3909 01c4 55534246 .ascii "USBFS_GetInterfaceClassTablePtr\000" - 3909 535F4765 - 3909 74496E74 - 3909 65726661 - 3909 6365436C - 3910 .LASF3: - 3911 01e4 73686F72 .ascii "short unsigned int\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 95 - - - 3911 7420756E - 3911 7369676E - 3911 65642069 - 3911 6E7400 - 3912 .LASF49: - 3913 01f7 70446573 .ascii "pDescr\000" - 3913 637200 - 3914 .LASF24: - 3915 01fe 696E7465 .ascii "interface\000" - 3915 72666163 - 3915 6500 - 3916 .LASF55: - 3917 0208 55534246 .ascii "USBFS_ValidateAlternateSetting\000" - 3917 535F5661 - 3917 6C696461 - 3917 7465416C - 3917 7465726E - 3918 .LASF65: - 3919 0227 55534246 .ascii "USBFS_configurationChanged\000" - 3919 535F636F - 3919 6E666967 - 3919 75726174 - 3919 696F6E43 - 3920 .LASF76: - 3921 0242 55534246 .ascii "USBFS_interfaceClass\000" - 3921 535F696E - 3921 74657266 - 3921 61636543 - 3921 6C617373 - 3922 .LASF70: - 3923 0257 55534246 .ascii "USBFS_STRING_DESCRIPTORS\000" - 3923 535F5354 - 3923 52494E47 - 3923 5F444553 - 3923 43524950 - 3924 .LASF18: - 3925 0270 68774570 .ascii "hwEpState\000" - 3925 53746174 - 3925 6500 - 3926 .LASF61: - 3927 027a 64657363 .ascii "descrLength\000" - 3927 724C656E - 3927 67746800 - 3928 .LASF15: - 3929 0286 73697A65 .ascii "sizetype\000" - 3929 74797065 - 3929 00 - 3930 .LASF39: - 3931 028f 70546D70 .ascii "pTmp\000" - 3931 00 - 3932 .LASF37: - 3933 0294 705F6C69 .ascii "p_list\000" - 3933 737400 - 3934 .LASF50: - 3935 029b 62756666 .ascii "buffCount\000" - 3935 436F756E - 3935 7400 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 96 - - - 3936 .LASF16: - 3937 02a5 61747472 .ascii "attrib\000" - 3937 696200 - 3938 .LASF68: - 3939 02ac 55534246 .ascii "USBFS_TABLE\000" - 3939 535F5441 - 3939 424C4500 - 3940 .LASF69: - 3941 02b8 55534246 .ascii "USBFS_SN_STRING_DESCRIPTOR\000" - 3941 535F534E - 3941 5F535452 - 3941 494E475F - 3941 44455343 - 3942 .LASF46: - 3943 02d3 63757272 .ascii "currentInterfacesNum\000" - 3943 656E7449 - 3943 6E746572 - 3943 66616365 - 3943 734E756D - 3944 .LASF41: - 3945 02e8 55534246 .ascii "USBFS_ConfigAltChanged\000" - 3945 535F436F - 3945 6E666967 - 3945 416C7443 - 3945 68616E67 - 3946 .LASF32: - 3947 02ff 545F5553 .ascii "T_USBFS_XFER_STATUS_BLOCK\000" - 3947 4246535F - 3947 58464552 - 3947 5F535441 - 3947 5455535F - 3948 .LASF56: - 3949 0319 696E7465 .ascii "interfaceNum\000" - 3949 72666163 - 3949 654E756D - 3949 00 - 3950 .LASF67: - 3951 0326 55534246 .ascii "USBFS_DEVICE0_DESCR\000" - 3951 535F4445 - 3951 56494345 - 3951 305F4445 - 3951 53435200 - 3952 .LASF11: - 3953 033a 666C6F61 .ascii "float\000" - 3953 7400 - 3954 .LASF17: - 3955 0340 61706945 .ascii "apiEpState\000" - 3955 70537461 - 3955 746500 - 3956 .LASF77: - 3957 034b 55534246 .ascii "USBFS_EP\000" - 3957 535F4550 - 3957 00 - 3958 .LASF59: - 3959 0354 70537472 .ascii "pStr\000" - 3959 00 - 3960 .LASF83: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 97 - - - 3961 0359 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 3961 4320342E - 3961 372E3320 - 3961 32303133 - 3961 30333132 - 3962 038c 616E6368 .ascii "anch revision 196615]\000" - 3962 20726576 - 3962 6973696F - 3962 6E203139 - 3962 36363135 - 3963 .LASF14: - 3964 03a2 72656738 .ascii "reg8\000" - 3964 00 - 3965 .LASF1: - 3966 03a7 756E7369 .ascii "unsigned char\000" - 3966 676E6564 - 3966 20636861 - 3966 7200 - 3967 .LASF2: - 3968 03b5 73686F72 .ascii "short int\000" - 3968 7420696E - 3968 7400 - 3969 .LASF36: - 3970 03bf 545F5553 .ascii "T_USBFS_TD\000" - 3970 4246535F - 3970 544400 - 3971 .LASF44: - 3972 03ca 55534246 .ascii "USBFS_GetConfigTablePtr\000" - 3972 535F4765 - 3972 74436F6E - 3972 66696754 - 3972 61626C65 - 3973 .LASF84: - 3974 03e2 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\USBFS_std.c\000" - 3974 6E657261 - 3974 7465645F - 3974 536F7572 - 3974 63655C50 - 3975 .LASF72: - 3976 0407 55534246 .ascii "USBFS_interfaceSetting\000" - 3976 535F696E - 3976 74657266 - 3976 61636553 - 3976 65747469 - 3977 .LASF25: - 3978 041e 545F5553 .ascii "T_USBFS_EP_CTL_BLOCK\000" - 3978 4246535F - 3978 45505F43 - 3978 544C5F42 - 3978 4C4F434B - 3979 .LASF80: - 3980 0433 55534246 .ascii "USBFS_InitNoDataControlTransfer\000" - 3980 535F496E - 3980 69744E6F - 3980 44617461 - 3980 436F6E74 - 3981 .LASF63: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 98 - - - 3982 0453 55534246 .ascii "USBFS_device\000" - 3982 535F6465 - 3982 76696365 - 3982 00 - 3983 .LASF27: - 3984 0460 61747472 .ascii "attributes\000" - 3984 69627574 - 3984 657300 - 3985 .LASF26: - 3986 046b 616C7453 .ascii "altSetting\000" - 3986 65747469 - 3986 6E6700 - 3987 .LASF13: - 3988 0476 63686172 .ascii "char\000" - 3988 00 - 3989 .LASF23: - 3990 047b 62756666 .ascii "bufferSize\000" - 3990 65725369 - 3990 7A6500 - 3991 .LASF53: - 3992 0486 72657175 .ascii "requestHandled\000" - 3992 65737448 - 3992 616E646C - 3992 656400 - 3993 .LASF22: - 3994 0495 62756666 .ascii "buffOffset\000" - 3994 4F666673 - 3994 657400 - 3995 .LASF79: - 3996 04a0 55534246 .ascii "USBFS_GetDeviceTablePtr\000" - 3996 535F4765 - 3996 74446576 - 3996 69636554 - 3996 61626C65 - 3997 .LASF66: - 3998 04b8 55534246 .ascii "USBFS_deviceStatus\000" - 3998 535F6465 - 3998 76696365 - 3998 53746174 - 3998 757300 - 3999 .LASF73: - 4000 04cb 55534246 .ascii "USBFS_interfaceSetting_last\000" - 4000 535F696E - 4000 74657266 - 4000 61636553 - 4000 65747469 - 4001 .LASF31: - 4002 04e7 6C656E67 .ascii "length\000" - 4002 746800 - 4003 .LASF60: - 4004 04ee 6E537472 .ascii "nStr\000" - 4004 00 - 4005 .LASF43: - 4006 04f3 65705F74 .ascii "ep_type\000" - 4006 79706500 - 4007 .LASF42: - 4008 04fb 6375725F .ascii "cur_ep\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccm5Lblu.s page 99 - - - 4008 657000 - 4009 .LASF30: - 4010 0502 73746174 .ascii "status\000" - 4010 757300 - 4011 .LASF82: - 4012 0509 55534246 .ascii "USBFS_DispatchClassRqst\000" - 4012 535F4469 - 4012 73706174 - 4012 6368436C - 4012 61737352 - 4013 .LASF28: - 4014 0521 624D6973 .ascii "bMisc\000" - 4014 6300 - 4015 .LASF75: - 4016 0527 55534246 .ascii "USBFS_interfaceStatus\000" - 4016 535F696E - 4016 74657266 - 4016 61636553 - 4016 74617475 - 4017 .LASF57: - 4018 053d 55534246 .ascii "USBFS_HandleStandardRqst\000" - 4018 535F4861 - 4018 6E646C65 - 4018 5374616E - 4018 64617264 - 4019 .LASF38: - 4020 0556 545F5553 .ascii "T_USBFS_LUT\000" - 4020 4246535F - 4020 4C555400 - 4021 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br + 3898 .LASF64: + 3899 016a 55534246 .ascii "USBFS_configuration\000" + 3899 535F636F + 3899 6E666967 + 3899 75726174 + 3899 696F6E00 + 3900 .LASF21: + 3901 017e 65704D6F .ascii "epMode\000" + 3901 646500 + 3902 .LASF8: + 3903 0185 756E7369 .ascii "unsigned int\000" + 3903 676E6564 + 3903 20696E74 + 3903 00 + 3904 .LASF5: + 3905 0192 6C6F6E67 .ascii "long unsigned int\000" + 3905 20756E73 + 3905 69676E65 + 3905 6420696E + 3905 7400 + 3906 .LASF45: + 3907 01a4 55534246 .ascii "USBFS_GetInterfaceClassTablePtr\000" + 3907 535F4765 + 3907 74496E74 + 3907 65726661 + 3907 6365436C + 3908 .LASF3: + 3909 01c4 73686F72 .ascii "short unsigned int\000" + 3909 7420756E + 3909 7369676E + 3909 65642069 + 3909 6E7400 + 3910 .LASF49: + 3911 01d7 70446573 .ascii "pDescr\000" + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 95 + + + 3911 637200 + 3912 .LASF24: + 3913 01de 696E7465 .ascii "interface\000" + 3913 72666163 + 3913 6500 + 3914 .LASF55: + 3915 01e8 55534246 .ascii "USBFS_ValidateAlternateSetting\000" + 3915 535F5661 + 3915 6C696461 + 3915 7465416C + 3915 7465726E + 3916 .LASF65: + 3917 0207 55534246 .ascii "USBFS_configurationChanged\000" + 3917 535F636F + 3917 6E666967 + 3917 75726174 + 3917 696F6E43 + 3918 .LASF85: + 3919 0222 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" + 3919 43534932 + 3919 53445C73 + 3919 6F667477 + 3919 6172655C + 3920 0251 6E00 .ascii "n\000" + 3921 .LASF76: + 3922 0253 55534246 .ascii "USBFS_interfaceClass\000" + 3922 535F696E + 3922 74657266 + 3922 61636543 + 3922 6C617373 + 3923 .LASF70: + 3924 0268 55534246 .ascii "USBFS_STRING_DESCRIPTORS\000" + 3924 535F5354 + 3924 52494E47 + 3924 5F444553 + 3924 43524950 + 3925 .LASF18: + 3926 0281 68774570 .ascii "hwEpState\000" + 3926 53746174 + 3926 6500 + 3927 .LASF61: + 3928 028b 64657363 .ascii "descrLength\000" + 3928 724C656E + 3928 67746800 + 3929 .LASF15: + 3930 0297 73697A65 .ascii "sizetype\000" + 3930 74797065 + 3930 00 + 3931 .LASF39: + 3932 02a0 70546D70 .ascii "pTmp\000" + 3932 00 + 3933 .LASF37: + 3934 02a5 705F6C69 .ascii "p_list\000" + 3934 737400 + 3935 .LASF50: + 3936 02ac 62756666 .ascii "buffCount\000" + 3936 436F756E + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 96 + + + 3936 7400 + 3937 .LASF16: + 3938 02b6 61747472 .ascii "attrib\000" + 3938 696200 + 3939 .LASF68: + 3940 02bd 55534246 .ascii "USBFS_TABLE\000" + 3940 535F5441 + 3940 424C4500 + 3941 .LASF69: + 3942 02c9 55534246 .ascii "USBFS_SN_STRING_DESCRIPTOR\000" + 3942 535F534E + 3942 5F535452 + 3942 494E475F + 3942 44455343 + 3943 .LASF46: + 3944 02e4 63757272 .ascii "currentInterfacesNum\000" + 3944 656E7449 + 3944 6E746572 + 3944 66616365 + 3944 734E756D + 3945 .LASF41: + 3946 02f9 55534246 .ascii "USBFS_ConfigAltChanged\000" + 3946 535F436F + 3946 6E666967 + 3946 416C7443 + 3946 68616E67 + 3947 .LASF32: + 3948 0310 545F5553 .ascii "T_USBFS_XFER_STATUS_BLOCK\000" + 3948 4246535F + 3948 58464552 + 3948 5F535441 + 3948 5455535F + 3949 .LASF56: + 3950 032a 696E7465 .ascii "interfaceNum\000" + 3950 72666163 + 3950 654E756D + 3950 00 + 3951 .LASF67: + 3952 0337 55534246 .ascii "USBFS_DEVICE0_DESCR\000" + 3952 535F4445 + 3952 56494345 + 3952 305F4445 + 3952 53435200 + 3953 .LASF11: + 3954 034b 666C6F61 .ascii "float\000" + 3954 7400 + 3955 .LASF17: + 3956 0351 61706945 .ascii "apiEpState\000" + 3956 70537461 + 3956 746500 + 3957 .LASF77: + 3958 035c 55534246 .ascii "USBFS_EP\000" + 3958 535F4550 + 3958 00 + 3959 .LASF59: + 3960 0365 70537472 .ascii "pStr\000" + 3960 00 + ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 97 + + + 3961 .LASF83: + 3962 036a 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" + 3962 4320342E + 3962 372E3320 + 3962 32303133 + 3962 30333132 + 3963 039d 616E6368 .ascii "anch revision 196615]\000" + 3963 20726576 + 3963 6973696F + 3963 6E203139 + 3963 36363135 + 3964 .LASF14: + 3965 03b3 72656738 .ascii "reg8\000" + 3965 00 + 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