Small compatibility improvements, and added scsi2sd-monitor test program
[SCSI2SD-V6.git] / software / SCSI2SD / v3 / SCSI2SD.cydsn / Generated_Source / PSoC5 / cyfitter.h
CommitLineData
75de1226
MM
1#ifndef INCLUDED_CYFITTER_H\r
2#define INCLUDED_CYFITTER_H\r
3#include <cydevice.h>\r
4#include <cydevice_trm.h>\r
5\r
70257ca8
MM
6/* LED1 */\r
7#define LED1__0__MASK 0x08u\r
8#define LED1__0__PC CYREG_PRT12_PC3\r
9#define LED1__0__PORT 12u\r
10#define LED1__0__SHIFT 3\r
11#define LED1__AG CYREG_PRT12_AG\r
12#define LED1__BIE CYREG_PRT12_BIE\r
13#define LED1__BIT_MASK CYREG_PRT12_BIT_MASK\r
14#define LED1__BYP CYREG_PRT12_BYP\r
15#define LED1__DM0 CYREG_PRT12_DM0\r
16#define LED1__DM1 CYREG_PRT12_DM1\r
17#define LED1__DM2 CYREG_PRT12_DM2\r
18#define LED1__DR CYREG_PRT12_DR\r
19#define LED1__INP_DIS CYREG_PRT12_INP_DIS\r
20#define LED1__MASK 0x08u\r
21#define LED1__PORT 12u\r
22#define LED1__PRT CYREG_PRT12_PRT\r
23#define LED1__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
24#define LED1__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
25#define LED1__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
26#define LED1__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
27#define LED1__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
28#define LED1__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
29#define LED1__PS CYREG_PRT12_PS\r
30#define LED1__SHIFT 3\r
31#define LED1__SIO_CFG CYREG_PRT12_SIO_CFG\r
32#define LED1__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
33#define LED1__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
34#define LED1__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
35#define LED1__SLW CYREG_PRT12_SLW\r
db9c3160 36\r
70257ca8
MM
37/* SD_CD */\r
38#define SD_CD__0__MASK 0x40u\r
39#define SD_CD__0__PC CYREG_PRT3_PC6\r
40#define SD_CD__0__PORT 3u\r
41#define SD_CD__0__SHIFT 6\r
42#define SD_CD__AG CYREG_PRT3_AG\r
43#define SD_CD__AMUX CYREG_PRT3_AMUX\r
44#define SD_CD__BIE CYREG_PRT3_BIE\r
45#define SD_CD__BIT_MASK CYREG_PRT3_BIT_MASK\r
46#define SD_CD__BYP CYREG_PRT3_BYP\r
47#define SD_CD__CTL CYREG_PRT3_CTL\r
48#define SD_CD__DM0 CYREG_PRT3_DM0\r
49#define SD_CD__DM1 CYREG_PRT3_DM1\r
50#define SD_CD__DM2 CYREG_PRT3_DM2\r
51#define SD_CD__DR CYREG_PRT3_DR\r
52#define SD_CD__INP_DIS CYREG_PRT3_INP_DIS\r
53#define SD_CD__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
54#define SD_CD__LCD_EN CYREG_PRT3_LCD_EN\r
55#define SD_CD__MASK 0x40u\r
56#define SD_CD__PORT 3u\r
57#define SD_CD__PRT CYREG_PRT3_PRT\r
58#define SD_CD__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
59#define SD_CD__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
60#define SD_CD__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
61#define SD_CD__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
62#define SD_CD__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
63#define SD_CD__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
64#define SD_CD__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
65#define SD_CD__PS CYREG_PRT3_PS\r
66#define SD_CD__SHIFT 6\r
67#define SD_CD__SLW CYREG_PRT3_SLW\r
5bcd0c3a 68\r
70257ca8
MM
69/* SD_CS */\r
70#define SD_CS__0__MASK 0x10u\r
71#define SD_CS__0__PC CYREG_PRT3_PC4\r
72#define SD_CS__0__PORT 3u\r
73#define SD_CS__0__SHIFT 4\r
74#define SD_CS__AG CYREG_PRT3_AG\r
75#define SD_CS__AMUX CYREG_PRT3_AMUX\r
76#define SD_CS__BIE CYREG_PRT3_BIE\r
77#define SD_CS__BIT_MASK CYREG_PRT3_BIT_MASK\r
78#define SD_CS__BYP CYREG_PRT3_BYP\r
79#define SD_CS__CTL CYREG_PRT3_CTL\r
80#define SD_CS__DM0 CYREG_PRT3_DM0\r
81#define SD_CS__DM1 CYREG_PRT3_DM1\r
82#define SD_CS__DM2 CYREG_PRT3_DM2\r
83#define SD_CS__DR CYREG_PRT3_DR\r
84#define SD_CS__INP_DIS CYREG_PRT3_INP_DIS\r
85#define SD_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
86#define SD_CS__LCD_EN CYREG_PRT3_LCD_EN\r
87#define SD_CS__MASK 0x10u\r
88#define SD_CS__PORT 3u\r
89#define SD_CS__PRT CYREG_PRT3_PRT\r
90#define SD_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
91#define SD_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
92#define SD_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
93#define SD_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
94#define SD_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
95#define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
96#define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
97#define SD_CS__PS CYREG_PRT3_PS\r
98#define SD_CS__SHIFT 4\r
99#define SD_CS__SLW CYREG_PRT3_SLW\r
5bcd0c3a 100\r
70257ca8
MM
101/* USBFS_arb_int */\r
102#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
103#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
104#define USBFS_arb_int__INTC_MASK 0x400000u\r
105#define USBFS_arb_int__INTC_NUMBER 22u\r
9ad7cc15 106#define USBFS_arb_int__INTC_PRIOR_NUM 6u\r
70257ca8
MM
107#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22\r
108#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
109#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
7db82a4e 110\r
7193c6f2
MM
111/* USBFS_bus_reset */\r
112#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
113#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
114#define USBFS_bus_reset__INTC_MASK 0x800000u\r
115#define USBFS_bus_reset__INTC_NUMBER 23u\r
116#define USBFS_bus_reset__INTC_PRIOR_NUM 7u\r
117#define USBFS_bus_reset__INTC_PRIOR_REG CYREG_NVIC_PRI_23\r
118#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
119#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
c693c7fa 120\r
70257ca8
MM
121/* USBFS_Dm */\r
122#define USBFS_Dm__0__MASK 0x80u\r
123#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1\r
124#define USBFS_Dm__0__PORT 15u\r
125#define USBFS_Dm__0__SHIFT 7\r
126#define USBFS_Dm__AG CYREG_PRT15_AG\r
127#define USBFS_Dm__AMUX CYREG_PRT15_AMUX\r
128#define USBFS_Dm__BIE CYREG_PRT15_BIE\r
129#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK\r
130#define USBFS_Dm__BYP CYREG_PRT15_BYP\r
131#define USBFS_Dm__CTL CYREG_PRT15_CTL\r
132#define USBFS_Dm__DM0 CYREG_PRT15_DM0\r
133#define USBFS_Dm__DM1 CYREG_PRT15_DM1\r
134#define USBFS_Dm__DM2 CYREG_PRT15_DM2\r
135#define USBFS_Dm__DR CYREG_PRT15_DR\r
136#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS\r
137#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG\r
138#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN\r
139#define USBFS_Dm__MASK 0x80u\r
140#define USBFS_Dm__PORT 15u\r
141#define USBFS_Dm__PRT CYREG_PRT15_PRT\r
142#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL\r
143#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN\r
144#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0\r
145#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1\r
146#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0\r
147#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1\r
148#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT\r
149#define USBFS_Dm__PS CYREG_PRT15_PS\r
150#define USBFS_Dm__SHIFT 7\r
151#define USBFS_Dm__SLW CYREG_PRT15_SLW\r
152\r
153/* USBFS_Dp */\r
154#define USBFS_Dp__0__MASK 0x40u\r
155#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0\r
156#define USBFS_Dp__0__PORT 15u\r
157#define USBFS_Dp__0__SHIFT 6\r
158#define USBFS_Dp__AG CYREG_PRT15_AG\r
159#define USBFS_Dp__AMUX CYREG_PRT15_AMUX\r
160#define USBFS_Dp__BIE CYREG_PRT15_BIE\r
161#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK\r
162#define USBFS_Dp__BYP CYREG_PRT15_BYP\r
163#define USBFS_Dp__CTL CYREG_PRT15_CTL\r
164#define USBFS_Dp__DM0 CYREG_PRT15_DM0\r
165#define USBFS_Dp__DM1 CYREG_PRT15_DM1\r
166#define USBFS_Dp__DM2 CYREG_PRT15_DM2\r
167#define USBFS_Dp__DR CYREG_PRT15_DR\r
168#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS\r
169#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT\r
170#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG\r
171#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN\r
172#define USBFS_Dp__MASK 0x40u\r
173#define USBFS_Dp__PORT 15u\r
174#define USBFS_Dp__PRT CYREG_PRT15_PRT\r
175#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL\r
176#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN\r
177#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0\r
178#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1\r
179#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0\r
180#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1\r
181#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT\r
182#define USBFS_Dp__PS CYREG_PRT15_PS\r
183#define USBFS_Dp__SHIFT 6\r
184#define USBFS_Dp__SLW CYREG_PRT15_SLW\r
185#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15\r
186\r
187/* USBFS_dp_int */\r
188#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
189#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
190#define USBFS_dp_int__INTC_MASK 0x1000u\r
191#define USBFS_dp_int__INTC_NUMBER 12u\r
192#define USBFS_dp_int__INTC_PRIOR_NUM 7u\r
193#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12\r
194#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
195#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
196\r
197/* USBFS_ep_0 */\r
198#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
199#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
200#define USBFS_ep_0__INTC_MASK 0x1000000u\r
201#define USBFS_ep_0__INTC_NUMBER 24u\r
202#define USBFS_ep_0__INTC_PRIOR_NUM 7u\r
203#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24\r
204#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
205#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
206\r
207/* USBFS_ep_1 */\r
208#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
209#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
210#define USBFS_ep_1__INTC_MASK 0x40u\r
211#define USBFS_ep_1__INTC_NUMBER 6u\r
212#define USBFS_ep_1__INTC_PRIOR_NUM 7u\r
213#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_6\r
214#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
215#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
216\r
217/* USBFS_ep_2 */\r
218#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
219#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
220#define USBFS_ep_2__INTC_MASK 0x80u\r
221#define USBFS_ep_2__INTC_NUMBER 7u\r
222#define USBFS_ep_2__INTC_PRIOR_NUM 7u\r
223#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_7\r
224#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
225#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
226\r
227/* USBFS_ep_3 */\r
228#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
229#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
230#define USBFS_ep_3__INTC_MASK 0x100u\r
231#define USBFS_ep_3__INTC_NUMBER 8u\r
232#define USBFS_ep_3__INTC_PRIOR_NUM 7u\r
233#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_8\r
234#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
235#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
236\r
237/* USBFS_ep_4 */\r
238#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
239#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
240#define USBFS_ep_4__INTC_MASK 0x200u\r
241#define USBFS_ep_4__INTC_NUMBER 9u\r
242#define USBFS_ep_4__INTC_PRIOR_NUM 7u\r
243#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_9\r
244#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
245#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
c693c7fa 246\r
7193c6f2
MM
247/* USBFS_sof_int */\r
248#define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
249#define USBFS_sof_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
250#define USBFS_sof_int__INTC_MASK 0x200000u\r
251#define USBFS_sof_int__INTC_NUMBER 21u\r
252#define USBFS_sof_int__INTC_PRIOR_NUM 7u\r
253#define USBFS_sof_int__INTC_PRIOR_REG CYREG_NVIC_PRI_21\r
254#define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
255#define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
c693c7fa 256\r
70257ca8
MM
257/* USBFS_USB */\r
258#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG\r
259#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG\r
260#define USBFS_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN\r
261#define USBFS_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR\r
262#define USBFS_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG\r
263#define USBFS_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN\r
264#define USBFS_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR\r
265#define USBFS_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG\r
266#define USBFS_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN\r
267#define USBFS_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR\r
268#define USBFS_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG\r
269#define USBFS_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN\r
270#define USBFS_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR\r
271#define USBFS_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG\r
272#define USBFS_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN\r
273#define USBFS_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR\r
274#define USBFS_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG\r
275#define USBFS_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN\r
276#define USBFS_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR\r
277#define USBFS_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG\r
278#define USBFS_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN\r
279#define USBFS_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR\r
280#define USBFS_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG\r
281#define USBFS_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN\r
282#define USBFS_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR\r
283#define USBFS_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN\r
284#define USBFS_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR\r
285#define USBFS_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR\r
286#define USBFS_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA\r
287#define USBFS_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB\r
288#define USBFS_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA\r
289#define USBFS_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB\r
290#define USBFS_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR\r
291#define USBFS_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA\r
292#define USBFS_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB\r
293#define USBFS_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA\r
294#define USBFS_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB\r
295#define USBFS_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR\r
296#define USBFS_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA\r
297#define USBFS_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB\r
298#define USBFS_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA\r
299#define USBFS_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB\r
300#define USBFS_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR\r
301#define USBFS_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA\r
302#define USBFS_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB\r
303#define USBFS_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA\r
304#define USBFS_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB\r
305#define USBFS_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR\r
306#define USBFS_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA\r
307#define USBFS_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB\r
308#define USBFS_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA\r
309#define USBFS_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB\r
310#define USBFS_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR\r
311#define USBFS_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA\r
312#define USBFS_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB\r
313#define USBFS_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA\r
314#define USBFS_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB\r
315#define USBFS_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR\r
316#define USBFS_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA\r
317#define USBFS_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB\r
318#define USBFS_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA\r
319#define USBFS_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB\r
320#define USBFS_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR\r
321#define USBFS_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA\r
322#define USBFS_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB\r
323#define USBFS_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA\r
324#define USBFS_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB\r
325#define USBFS_USB__BUF_SIZE CYREG_USB_BUF_SIZE\r
326#define USBFS_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT\r
327#define USBFS_USB__CR0 CYREG_USB_CR0\r
328#define USBFS_USB__CR1 CYREG_USB_CR1\r
329#define USBFS_USB__CWA CYREG_USB_CWA\r
330#define USBFS_USB__CWA_MSB CYREG_USB_CWA_MSB\r
331#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES\r
332#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB\r
333#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG\r
334#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE\r
335#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE\r
336#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT\r
337#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR\r
338#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0\r
339#define USBFS_USB__EP0_DR1 CYREG_USB_EP0_DR1\r
340#define USBFS_USB__EP0_DR2 CYREG_USB_EP0_DR2\r
341#define USBFS_USB__EP0_DR3 CYREG_USB_EP0_DR3\r
342#define USBFS_USB__EP0_DR4 CYREG_USB_EP0_DR4\r
343#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5\r
344#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6\r
345#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7\r
346#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE\r
347#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5\r
348#define USBFS_USB__PM_ACT_MSK 0x01u\r
349#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5\r
350#define USBFS_USB__PM_STBY_MSK 0x01u\r
351#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN\r
352#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR\r
353#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0\r
354#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1\r
355#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0\r
356#define USBFS_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0\r
357#define USBFS_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1\r
358#define USBFS_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0\r
359#define USBFS_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0\r
360#define USBFS_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1\r
361#define USBFS_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0\r
362#define USBFS_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0\r
363#define USBFS_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1\r
364#define USBFS_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0\r
365#define USBFS_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0\r
366#define USBFS_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1\r
367#define USBFS_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0\r
368#define USBFS_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0\r
369#define USBFS_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1\r
370#define USBFS_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0\r
371#define USBFS_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0\r
372#define USBFS_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1\r
373#define USBFS_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0\r
374#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0\r
375#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1\r
376#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0\r
377#define USBFS_USB__SOF0 CYREG_USB_SOF0\r
378#define USBFS_USB__SOF1 CYREG_USB_SOF1\r
379#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN\r
380#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0\r
381#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1\r
db9c3160 382\r
70257ca8 383/* SDCard_BSPIM */\r
95b51978
MM
384#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
385#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL\r
386#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL\r
387#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL\r
388#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL\r
389#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK\r
390#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK\r
391#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK\r
392#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK\r
393#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
394#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB06_CTL\r
395#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL\r
396#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB06_CTL\r
397#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL\r
398#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
399#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
400#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK\r
401#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
402#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST\r
403#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB06_MSK\r
404#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
405#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
406#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
407#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL\r
408#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL\r
409#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB06_ST\r
70257ca8
MM
410#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
411#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST\r
412#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
413#define SDCard_BSPIM_RxStsReg__4__POS 4\r
414#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
415#define SDCard_BSPIM_RxStsReg__5__POS 5\r
416#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
417#define SDCard_BSPIM_RxStsReg__6__POS 6\r
418#define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
419#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB07_MSK\r
420#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
421#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB07_ST\r
95b51978
MM
422#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0\r
423#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1\r
424#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0\r
425#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB04_05_D1\r
426#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
427#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB04_05_F0\r
428#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB04_05_F1\r
429#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB04_A0_A1\r
430#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB04_A0\r
431#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB04_A1\r
432#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB04_D0_D1\r
433#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB04_D0\r
434#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB04_D1\r
435#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
436#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1\r
437#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0\r
438#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1\r
70257ca8
MM
439#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u\r
440#define SDCard_BSPIM_TxStsReg__0__POS 0\r
441#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
442#define SDCard_BSPIM_TxStsReg__1__POS 1\r
95b51978
MM
443#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL\r
444#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST\r
70257ca8
MM
445#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u\r
446#define SDCard_BSPIM_TxStsReg__2__POS 2\r
447#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u\r
448#define SDCard_BSPIM_TxStsReg__3__POS 3\r
449#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u\r
450#define SDCard_BSPIM_TxStsReg__4__POS 4\r
451#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
95b51978
MM
452#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB05_MSK\r
453#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL\r
454#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB05_ST\r
7193c6f2 455\r
70257ca8
MM
456/* SD_SCK */\r
457#define SD_SCK__0__MASK 0x04u\r
458#define SD_SCK__0__PC CYREG_PRT3_PC2\r
459#define SD_SCK__0__PORT 3u\r
460#define SD_SCK__0__SHIFT 2\r
461#define SD_SCK__AG CYREG_PRT3_AG\r
462#define SD_SCK__AMUX CYREG_PRT3_AMUX\r
463#define SD_SCK__BIE CYREG_PRT3_BIE\r
464#define SD_SCK__BIT_MASK CYREG_PRT3_BIT_MASK\r
465#define SD_SCK__BYP CYREG_PRT3_BYP\r
466#define SD_SCK__CTL CYREG_PRT3_CTL\r
467#define SD_SCK__DM0 CYREG_PRT3_DM0\r
468#define SD_SCK__DM1 CYREG_PRT3_DM1\r
469#define SD_SCK__DM2 CYREG_PRT3_DM2\r
470#define SD_SCK__DR CYREG_PRT3_DR\r
471#define SD_SCK__INP_DIS CYREG_PRT3_INP_DIS\r
472#define SD_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
473#define SD_SCK__LCD_EN CYREG_PRT3_LCD_EN\r
474#define SD_SCK__MASK 0x04u\r
475#define SD_SCK__PORT 3u\r
476#define SD_SCK__PRT CYREG_PRT3_PRT\r
477#define SD_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
478#define SD_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
479#define SD_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
480#define SD_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
481#define SD_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
482#define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
483#define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
484#define SD_SCK__PS CYREG_PRT3_PS\r
485#define SD_SCK__SHIFT 2\r
486#define SD_SCK__SLW CYREG_PRT3_SLW\r
7193c6f2 487\r
75de1226 488/* SCSI_In */\r
c693c7fa
MM
489#define SCSI_In__0__AG CYREG_PRT2_AG\r
490#define SCSI_In__0__AMUX CYREG_PRT2_AMUX\r
491#define SCSI_In__0__BIE CYREG_PRT2_BIE\r
492#define SCSI_In__0__BIT_MASK CYREG_PRT2_BIT_MASK\r
493#define SCSI_In__0__BYP CYREG_PRT2_BYP\r
494#define SCSI_In__0__CTL CYREG_PRT2_CTL\r
495#define SCSI_In__0__DM0 CYREG_PRT2_DM0\r
496#define SCSI_In__0__DM1 CYREG_PRT2_DM1\r
497#define SCSI_In__0__DM2 CYREG_PRT2_DM2\r
498#define SCSI_In__0__DR CYREG_PRT2_DR\r
499#define SCSI_In__0__INP_DIS CYREG_PRT2_INP_DIS\r
500#define SCSI_In__0__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
501#define SCSI_In__0__LCD_EN CYREG_PRT2_LCD_EN\r
502#define SCSI_In__0__MASK 0x01u\r
503#define SCSI_In__0__PC CYREG_PRT2_PC0\r
504#define SCSI_In__0__PORT 2u\r
505#define SCSI_In__0__PRT CYREG_PRT2_PRT\r
506#define SCSI_In__0__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
507#define SCSI_In__0__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
508#define SCSI_In__0__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
509#define SCSI_In__0__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
510#define SCSI_In__0__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
511#define SCSI_In__0__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
512#define SCSI_In__0__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
513#define SCSI_In__0__PS CYREG_PRT2_PS\r
514#define SCSI_In__0__SHIFT 0\r
515#define SCSI_In__0__SLW CYREG_PRT2_SLW\r
cc6921e4
MM
516#define SCSI_In__1__AG CYREG_PRT6_AG\r
517#define SCSI_In__1__AMUX CYREG_PRT6_AMUX\r
518#define SCSI_In__1__BIE CYREG_PRT6_BIE\r
519#define SCSI_In__1__BIT_MASK CYREG_PRT6_BIT_MASK\r
520#define SCSI_In__1__BYP CYREG_PRT6_BYP\r
521#define SCSI_In__1__CTL CYREG_PRT6_CTL\r
522#define SCSI_In__1__DM0 CYREG_PRT6_DM0\r
523#define SCSI_In__1__DM1 CYREG_PRT6_DM1\r
524#define SCSI_In__1__DM2 CYREG_PRT6_DM2\r
525#define SCSI_In__1__DR CYREG_PRT6_DR\r
526#define SCSI_In__1__INP_DIS CYREG_PRT6_INP_DIS\r
527#define SCSI_In__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
528#define SCSI_In__1__LCD_EN CYREG_PRT6_LCD_EN\r
5456126c
MM
529#define SCSI_In__1__MASK 0x80u\r
530#define SCSI_In__1__PC CYREG_PRT6_PC7\r
cc6921e4
MM
531#define SCSI_In__1__PORT 6u\r
532#define SCSI_In__1__PRT CYREG_PRT6_PRT\r
533#define SCSI_In__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
534#define SCSI_In__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
535#define SCSI_In__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
536#define SCSI_In__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
537#define SCSI_In__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
538#define SCSI_In__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
539#define SCSI_In__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
540#define SCSI_In__1__PS CYREG_PRT6_PS\r
5456126c 541#define SCSI_In__1__SHIFT 7\r
cc6921e4 542#define SCSI_In__1__SLW CYREG_PRT6_SLW\r
5456126c
MM
543#define SCSI_In__2__AG CYREG_PRT5_AG\r
544#define SCSI_In__2__AMUX CYREG_PRT5_AMUX\r
545#define SCSI_In__2__BIE CYREG_PRT5_BIE\r
546#define SCSI_In__2__BIT_MASK CYREG_PRT5_BIT_MASK\r
547#define SCSI_In__2__BYP CYREG_PRT5_BYP\r
548#define SCSI_In__2__CTL CYREG_PRT5_CTL\r
549#define SCSI_In__2__DM0 CYREG_PRT5_DM0\r
550#define SCSI_In__2__DM1 CYREG_PRT5_DM1\r
551#define SCSI_In__2__DM2 CYREG_PRT5_DM2\r
552#define SCSI_In__2__DR CYREG_PRT5_DR\r
553#define SCSI_In__2__INP_DIS CYREG_PRT5_INP_DIS\r
554#define SCSI_In__2__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
555#define SCSI_In__2__LCD_EN CYREG_PRT5_LCD_EN\r
556#define SCSI_In__2__MASK 0x02u\r
557#define SCSI_In__2__PC CYREG_PRT5_PC1\r
558#define SCSI_In__2__PORT 5u\r
559#define SCSI_In__2__PRT CYREG_PRT5_PRT\r
560#define SCSI_In__2__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
561#define SCSI_In__2__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
562#define SCSI_In__2__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
563#define SCSI_In__2__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
564#define SCSI_In__2__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
565#define SCSI_In__2__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
566#define SCSI_In__2__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
567#define SCSI_In__2__PS CYREG_PRT5_PS\r
568#define SCSI_In__2__SHIFT 1\r
569#define SCSI_In__2__SLW CYREG_PRT5_SLW\r
570#define SCSI_In__3__AG CYREG_PRT5_AG\r
571#define SCSI_In__3__AMUX CYREG_PRT5_AMUX\r
572#define SCSI_In__3__BIE CYREG_PRT5_BIE\r
573#define SCSI_In__3__BIT_MASK CYREG_PRT5_BIT_MASK\r
574#define SCSI_In__3__BYP CYREG_PRT5_BYP\r
575#define SCSI_In__3__CTL CYREG_PRT5_CTL\r
576#define SCSI_In__3__DM0 CYREG_PRT5_DM0\r
577#define SCSI_In__3__DM1 CYREG_PRT5_DM1\r
578#define SCSI_In__3__DM2 CYREG_PRT5_DM2\r
579#define SCSI_In__3__DR CYREG_PRT5_DR\r
580#define SCSI_In__3__INP_DIS CYREG_PRT5_INP_DIS\r
581#define SCSI_In__3__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
582#define SCSI_In__3__LCD_EN CYREG_PRT5_LCD_EN\r
583#define SCSI_In__3__MASK 0x04u\r
584#define SCSI_In__3__PC CYREG_PRT5_PC2\r
585#define SCSI_In__3__PORT 5u\r
586#define SCSI_In__3__PRT CYREG_PRT5_PRT\r
587#define SCSI_In__3__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
588#define SCSI_In__3__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
589#define SCSI_In__3__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
590#define SCSI_In__3__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
591#define SCSI_In__3__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
592#define SCSI_In__3__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
593#define SCSI_In__3__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
594#define SCSI_In__3__PS CYREG_PRT5_PS\r
595#define SCSI_In__3__SHIFT 2\r
596#define SCSI_In__3__SLW CYREG_PRT5_SLW\r
cc6921e4
MM
597#define SCSI_In__4__AG CYREG_PRT5_AG\r
598#define SCSI_In__4__AMUX CYREG_PRT5_AMUX\r
599#define SCSI_In__4__BIE CYREG_PRT5_BIE\r
600#define SCSI_In__4__BIT_MASK CYREG_PRT5_BIT_MASK\r
601#define SCSI_In__4__BYP CYREG_PRT5_BYP\r
602#define SCSI_In__4__CTL CYREG_PRT5_CTL\r
603#define SCSI_In__4__DM0 CYREG_PRT5_DM0\r
604#define SCSI_In__4__DM1 CYREG_PRT5_DM1\r
605#define SCSI_In__4__DM2 CYREG_PRT5_DM2\r
606#define SCSI_In__4__DR CYREG_PRT5_DR\r
607#define SCSI_In__4__INP_DIS CYREG_PRT5_INP_DIS\r
608#define SCSI_In__4__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
609#define SCSI_In__4__LCD_EN CYREG_PRT5_LCD_EN\r
5456126c
MM
610#define SCSI_In__4__MASK 0x08u\r
611#define SCSI_In__4__PC CYREG_PRT5_PC3\r
cc6921e4
MM
612#define SCSI_In__4__PORT 5u\r
613#define SCSI_In__4__PRT CYREG_PRT5_PRT\r
614#define SCSI_In__4__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
615#define SCSI_In__4__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
616#define SCSI_In__4__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
617#define SCSI_In__4__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
618#define SCSI_In__4__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
619#define SCSI_In__4__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
620#define SCSI_In__4__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
621#define SCSI_In__4__PS CYREG_PRT5_PS\r
5456126c 622#define SCSI_In__4__SHIFT 3\r
cc6921e4 623#define SCSI_In__4__SLW CYREG_PRT5_SLW\r
75de1226
MM
624#define SCSI_In__CD__AG CYREG_PRT5_AG\r
625#define SCSI_In__CD__AMUX CYREG_PRT5_AMUX\r
626#define SCSI_In__CD__BIE CYREG_PRT5_BIE\r
627#define SCSI_In__CD__BIT_MASK CYREG_PRT5_BIT_MASK\r
628#define SCSI_In__CD__BYP CYREG_PRT5_BYP\r
629#define SCSI_In__CD__CTL CYREG_PRT5_CTL\r
630#define SCSI_In__CD__DM0 CYREG_PRT5_DM0\r
631#define SCSI_In__CD__DM1 CYREG_PRT5_DM1\r
632#define SCSI_In__CD__DM2 CYREG_PRT5_DM2\r
633#define SCSI_In__CD__DR CYREG_PRT5_DR\r
634#define SCSI_In__CD__INP_DIS CYREG_PRT5_INP_DIS\r
635#define SCSI_In__CD__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
636#define SCSI_In__CD__LCD_EN CYREG_PRT5_LCD_EN\r
637#define SCSI_In__CD__MASK 0x02u\r
638#define SCSI_In__CD__PC CYREG_PRT5_PC1\r
639#define SCSI_In__CD__PORT 5u\r
640#define SCSI_In__CD__PRT CYREG_PRT5_PRT\r
641#define SCSI_In__CD__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
642#define SCSI_In__CD__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
643#define SCSI_In__CD__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
644#define SCSI_In__CD__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
645#define SCSI_In__CD__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
646#define SCSI_In__CD__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
647#define SCSI_In__CD__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
648#define SCSI_In__CD__PS CYREG_PRT5_PS\r
649#define SCSI_In__CD__SHIFT 1\r
650#define SCSI_In__CD__SLW CYREG_PRT5_SLW\r
c693c7fa
MM
651#define SCSI_In__DBP__AG CYREG_PRT2_AG\r
652#define SCSI_In__DBP__AMUX CYREG_PRT2_AMUX\r
653#define SCSI_In__DBP__BIE CYREG_PRT2_BIE\r
654#define SCSI_In__DBP__BIT_MASK CYREG_PRT2_BIT_MASK\r
655#define SCSI_In__DBP__BYP CYREG_PRT2_BYP\r
656#define SCSI_In__DBP__CTL CYREG_PRT2_CTL\r
657#define SCSI_In__DBP__DM0 CYREG_PRT2_DM0\r
658#define SCSI_In__DBP__DM1 CYREG_PRT2_DM1\r
659#define SCSI_In__DBP__DM2 CYREG_PRT2_DM2\r
660#define SCSI_In__DBP__DR CYREG_PRT2_DR\r
661#define SCSI_In__DBP__INP_DIS CYREG_PRT2_INP_DIS\r
662#define SCSI_In__DBP__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
663#define SCSI_In__DBP__LCD_EN CYREG_PRT2_LCD_EN\r
664#define SCSI_In__DBP__MASK 0x01u\r
665#define SCSI_In__DBP__PC CYREG_PRT2_PC0\r
666#define SCSI_In__DBP__PORT 2u\r
667#define SCSI_In__DBP__PRT CYREG_PRT2_PRT\r
668#define SCSI_In__DBP__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
669#define SCSI_In__DBP__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
670#define SCSI_In__DBP__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
671#define SCSI_In__DBP__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
672#define SCSI_In__DBP__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
673#define SCSI_In__DBP__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
674#define SCSI_In__DBP__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
675#define SCSI_In__DBP__PS CYREG_PRT2_PS\r
676#define SCSI_In__DBP__SHIFT 0\r
677#define SCSI_In__DBP__SLW CYREG_PRT2_SLW\r
75de1226
MM
678#define SCSI_In__IO__AG CYREG_PRT5_AG\r
679#define SCSI_In__IO__AMUX CYREG_PRT5_AMUX\r
680#define SCSI_In__IO__BIE CYREG_PRT5_BIE\r
681#define SCSI_In__IO__BIT_MASK CYREG_PRT5_BIT_MASK\r
682#define SCSI_In__IO__BYP CYREG_PRT5_BYP\r
683#define SCSI_In__IO__CTL CYREG_PRT5_CTL\r
684#define SCSI_In__IO__DM0 CYREG_PRT5_DM0\r
685#define SCSI_In__IO__DM1 CYREG_PRT5_DM1\r
686#define SCSI_In__IO__DM2 CYREG_PRT5_DM2\r
687#define SCSI_In__IO__DR CYREG_PRT5_DR\r
688#define SCSI_In__IO__INP_DIS CYREG_PRT5_INP_DIS\r
689#define SCSI_In__IO__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
690#define SCSI_In__IO__LCD_EN CYREG_PRT5_LCD_EN\r
691#define SCSI_In__IO__MASK 0x08u\r
692#define SCSI_In__IO__PC CYREG_PRT5_PC3\r
693#define SCSI_In__IO__PORT 5u\r
694#define SCSI_In__IO__PRT CYREG_PRT5_PRT\r
695#define SCSI_In__IO__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
696#define SCSI_In__IO__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
697#define SCSI_In__IO__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
698#define SCSI_In__IO__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
699#define SCSI_In__IO__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
700#define SCSI_In__IO__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
701#define SCSI_In__IO__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
702#define SCSI_In__IO__PS CYREG_PRT5_PS\r
703#define SCSI_In__IO__SHIFT 3\r
704#define SCSI_In__IO__SLW CYREG_PRT5_SLW\r
705#define SCSI_In__MSG__AG CYREG_PRT6_AG\r
706#define SCSI_In__MSG__AMUX CYREG_PRT6_AMUX\r
707#define SCSI_In__MSG__BIE CYREG_PRT6_BIE\r
708#define SCSI_In__MSG__BIT_MASK CYREG_PRT6_BIT_MASK\r
709#define SCSI_In__MSG__BYP CYREG_PRT6_BYP\r
710#define SCSI_In__MSG__CTL CYREG_PRT6_CTL\r
711#define SCSI_In__MSG__DM0 CYREG_PRT6_DM0\r
712#define SCSI_In__MSG__DM1 CYREG_PRT6_DM1\r
713#define SCSI_In__MSG__DM2 CYREG_PRT6_DM2\r
714#define SCSI_In__MSG__DR CYREG_PRT6_DR\r
715#define SCSI_In__MSG__INP_DIS CYREG_PRT6_INP_DIS\r
716#define SCSI_In__MSG__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
717#define SCSI_In__MSG__LCD_EN CYREG_PRT6_LCD_EN\r
718#define SCSI_In__MSG__MASK 0x80u\r
719#define SCSI_In__MSG__PC CYREG_PRT6_PC7\r
720#define SCSI_In__MSG__PORT 6u\r
721#define SCSI_In__MSG__PRT CYREG_PRT6_PRT\r
722#define SCSI_In__MSG__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
723#define SCSI_In__MSG__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
724#define SCSI_In__MSG__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
725#define SCSI_In__MSG__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
726#define SCSI_In__MSG__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
727#define SCSI_In__MSG__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
728#define SCSI_In__MSG__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
729#define SCSI_In__MSG__PS CYREG_PRT6_PS\r
730#define SCSI_In__MSG__SHIFT 7\r
731#define SCSI_In__MSG__SLW CYREG_PRT6_SLW\r
732#define SCSI_In__REQ__AG CYREG_PRT5_AG\r
733#define SCSI_In__REQ__AMUX CYREG_PRT5_AMUX\r
734#define SCSI_In__REQ__BIE CYREG_PRT5_BIE\r
735#define SCSI_In__REQ__BIT_MASK CYREG_PRT5_BIT_MASK\r
736#define SCSI_In__REQ__BYP CYREG_PRT5_BYP\r
737#define SCSI_In__REQ__CTL CYREG_PRT5_CTL\r
738#define SCSI_In__REQ__DM0 CYREG_PRT5_DM0\r
739#define SCSI_In__REQ__DM1 CYREG_PRT5_DM1\r
740#define SCSI_In__REQ__DM2 CYREG_PRT5_DM2\r
741#define SCSI_In__REQ__DR CYREG_PRT5_DR\r
742#define SCSI_In__REQ__INP_DIS CYREG_PRT5_INP_DIS\r
743#define SCSI_In__REQ__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
744#define SCSI_In__REQ__LCD_EN CYREG_PRT5_LCD_EN\r
745#define SCSI_In__REQ__MASK 0x04u\r
746#define SCSI_In__REQ__PC CYREG_PRT5_PC2\r
747#define SCSI_In__REQ__PORT 5u\r
748#define SCSI_In__REQ__PRT CYREG_PRT5_PRT\r
749#define SCSI_In__REQ__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
750#define SCSI_In__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
751#define SCSI_In__REQ__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
752#define SCSI_In__REQ__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
753#define SCSI_In__REQ__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
754#define SCSI_In__REQ__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
755#define SCSI_In__REQ__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
756#define SCSI_In__REQ__PS CYREG_PRT5_PS\r
757#define SCSI_In__REQ__SHIFT 2\r
758#define SCSI_In__REQ__SLW CYREG_PRT5_SLW\r
75de1226 759\r
70257ca8
MM
760/* SCSI_In_DBx */\r
761#define SCSI_In_DBx__0__AG CYREG_PRT12_AG\r
762#define SCSI_In_DBx__0__BIE CYREG_PRT12_BIE\r
763#define SCSI_In_DBx__0__BIT_MASK CYREG_PRT12_BIT_MASK\r
764#define SCSI_In_DBx__0__BYP CYREG_PRT12_BYP\r
765#define SCSI_In_DBx__0__DM0 CYREG_PRT12_DM0\r
766#define SCSI_In_DBx__0__DM1 CYREG_PRT12_DM1\r
767#define SCSI_In_DBx__0__DM2 CYREG_PRT12_DM2\r
768#define SCSI_In_DBx__0__DR CYREG_PRT12_DR\r
769#define SCSI_In_DBx__0__INP_DIS CYREG_PRT12_INP_DIS\r
770#define SCSI_In_DBx__0__MASK 0x10u\r
771#define SCSI_In_DBx__0__PC CYREG_PRT12_PC4\r
772#define SCSI_In_DBx__0__PORT 12u\r
773#define SCSI_In_DBx__0__PRT CYREG_PRT12_PRT\r
774#define SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
775#define SCSI_In_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
776#define SCSI_In_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
777#define SCSI_In_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
778#define SCSI_In_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
779#define SCSI_In_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
780#define SCSI_In_DBx__0__PS CYREG_PRT12_PS\r
781#define SCSI_In_DBx__0__SHIFT 4\r
782#define SCSI_In_DBx__0__SIO_CFG CYREG_PRT12_SIO_CFG\r
783#define SCSI_In_DBx__0__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
784#define SCSI_In_DBx__0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
785#define SCSI_In_DBx__0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
786#define SCSI_In_DBx__0__SLW CYREG_PRT12_SLW\r
787#define SCSI_In_DBx__1__AG CYREG_PRT2_AG\r
788#define SCSI_In_DBx__1__AMUX CYREG_PRT2_AMUX\r
789#define SCSI_In_DBx__1__BIE CYREG_PRT2_BIE\r
790#define SCSI_In_DBx__1__BIT_MASK CYREG_PRT2_BIT_MASK\r
791#define SCSI_In_DBx__1__BYP CYREG_PRT2_BYP\r
792#define SCSI_In_DBx__1__CTL CYREG_PRT2_CTL\r
793#define SCSI_In_DBx__1__DM0 CYREG_PRT2_DM0\r
794#define SCSI_In_DBx__1__DM1 CYREG_PRT2_DM1\r
795#define SCSI_In_DBx__1__DM2 CYREG_PRT2_DM2\r
796#define SCSI_In_DBx__1__DR CYREG_PRT2_DR\r
797#define SCSI_In_DBx__1__INP_DIS CYREG_PRT2_INP_DIS\r
798#define SCSI_In_DBx__1__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
799#define SCSI_In_DBx__1__LCD_EN CYREG_PRT2_LCD_EN\r
800#define SCSI_In_DBx__1__MASK 0x80u\r
801#define SCSI_In_DBx__1__PC CYREG_PRT2_PC7\r
802#define SCSI_In_DBx__1__PORT 2u\r
803#define SCSI_In_DBx__1__PRT CYREG_PRT2_PRT\r
804#define SCSI_In_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
805#define SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
806#define SCSI_In_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
807#define SCSI_In_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
808#define SCSI_In_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
809#define SCSI_In_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
810#define SCSI_In_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
811#define SCSI_In_DBx__1__PS CYREG_PRT2_PS\r
812#define SCSI_In_DBx__1__SHIFT 7\r
813#define SCSI_In_DBx__1__SLW CYREG_PRT2_SLW\r
814#define SCSI_In_DBx__2__AG CYREG_PRT2_AG\r
815#define SCSI_In_DBx__2__AMUX CYREG_PRT2_AMUX\r
816#define SCSI_In_DBx__2__BIE CYREG_PRT2_BIE\r
817#define SCSI_In_DBx__2__BIT_MASK CYREG_PRT2_BIT_MASK\r
818#define SCSI_In_DBx__2__BYP CYREG_PRT2_BYP\r
819#define SCSI_In_DBx__2__CTL CYREG_PRT2_CTL\r
820#define SCSI_In_DBx__2__DM0 CYREG_PRT2_DM0\r
821#define SCSI_In_DBx__2__DM1 CYREG_PRT2_DM1\r
822#define SCSI_In_DBx__2__DM2 CYREG_PRT2_DM2\r
823#define SCSI_In_DBx__2__DR CYREG_PRT2_DR\r
824#define SCSI_In_DBx__2__INP_DIS CYREG_PRT2_INP_DIS\r
825#define SCSI_In_DBx__2__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
826#define SCSI_In_DBx__2__LCD_EN CYREG_PRT2_LCD_EN\r
827#define SCSI_In_DBx__2__MASK 0x40u\r
828#define SCSI_In_DBx__2__PC CYREG_PRT2_PC6\r
829#define SCSI_In_DBx__2__PORT 2u\r
830#define SCSI_In_DBx__2__PRT CYREG_PRT2_PRT\r
831#define SCSI_In_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
832#define SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
833#define SCSI_In_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
834#define SCSI_In_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
835#define SCSI_In_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
836#define SCSI_In_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
837#define SCSI_In_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
838#define SCSI_In_DBx__2__PS CYREG_PRT2_PS\r
839#define SCSI_In_DBx__2__SHIFT 6\r
840#define SCSI_In_DBx__2__SLW CYREG_PRT2_SLW\r
841#define SCSI_In_DBx__3__AG CYREG_PRT2_AG\r
842#define SCSI_In_DBx__3__AMUX CYREG_PRT2_AMUX\r
843#define SCSI_In_DBx__3__BIE CYREG_PRT2_BIE\r
844#define SCSI_In_DBx__3__BIT_MASK CYREG_PRT2_BIT_MASK\r
845#define SCSI_In_DBx__3__BYP CYREG_PRT2_BYP\r
846#define SCSI_In_DBx__3__CTL CYREG_PRT2_CTL\r
847#define SCSI_In_DBx__3__DM0 CYREG_PRT2_DM0\r
848#define SCSI_In_DBx__3__DM1 CYREG_PRT2_DM1\r
849#define SCSI_In_DBx__3__DM2 CYREG_PRT2_DM2\r
850#define SCSI_In_DBx__3__DR CYREG_PRT2_DR\r
851#define SCSI_In_DBx__3__INP_DIS CYREG_PRT2_INP_DIS\r
852#define SCSI_In_DBx__3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
853#define SCSI_In_DBx__3__LCD_EN CYREG_PRT2_LCD_EN\r
854#define SCSI_In_DBx__3__MASK 0x20u\r
855#define SCSI_In_DBx__3__PC CYREG_PRT2_PC5\r
856#define SCSI_In_DBx__3__PORT 2u\r
857#define SCSI_In_DBx__3__PRT CYREG_PRT2_PRT\r
858#define SCSI_In_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
859#define SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
860#define SCSI_In_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
861#define SCSI_In_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
862#define SCSI_In_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
863#define SCSI_In_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
864#define SCSI_In_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
865#define SCSI_In_DBx__3__PS CYREG_PRT2_PS\r
866#define SCSI_In_DBx__3__SHIFT 5\r
867#define SCSI_In_DBx__3__SLW CYREG_PRT2_SLW\r
868#define SCSI_In_DBx__4__AG CYREG_PRT2_AG\r
869#define SCSI_In_DBx__4__AMUX CYREG_PRT2_AMUX\r
870#define SCSI_In_DBx__4__BIE CYREG_PRT2_BIE\r
871#define SCSI_In_DBx__4__BIT_MASK CYREG_PRT2_BIT_MASK\r
872#define SCSI_In_DBx__4__BYP CYREG_PRT2_BYP\r
873#define SCSI_In_DBx__4__CTL CYREG_PRT2_CTL\r
874#define SCSI_In_DBx__4__DM0 CYREG_PRT2_DM0\r
875#define SCSI_In_DBx__4__DM1 CYREG_PRT2_DM1\r
876#define SCSI_In_DBx__4__DM2 CYREG_PRT2_DM2\r
877#define SCSI_In_DBx__4__DR CYREG_PRT2_DR\r
878#define SCSI_In_DBx__4__INP_DIS CYREG_PRT2_INP_DIS\r
879#define SCSI_In_DBx__4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
880#define SCSI_In_DBx__4__LCD_EN CYREG_PRT2_LCD_EN\r
881#define SCSI_In_DBx__4__MASK 0x10u\r
882#define SCSI_In_DBx__4__PC CYREG_PRT2_PC4\r
883#define SCSI_In_DBx__4__PORT 2u\r
884#define SCSI_In_DBx__4__PRT CYREG_PRT2_PRT\r
885#define SCSI_In_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
886#define SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
887#define SCSI_In_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
888#define SCSI_In_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
889#define SCSI_In_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
890#define SCSI_In_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
891#define SCSI_In_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
892#define SCSI_In_DBx__4__PS CYREG_PRT2_PS\r
893#define SCSI_In_DBx__4__SHIFT 4\r
894#define SCSI_In_DBx__4__SLW CYREG_PRT2_SLW\r
895#define SCSI_In_DBx__5__AG CYREG_PRT2_AG\r
896#define SCSI_In_DBx__5__AMUX CYREG_PRT2_AMUX\r
897#define SCSI_In_DBx__5__BIE CYREG_PRT2_BIE\r
898#define SCSI_In_DBx__5__BIT_MASK CYREG_PRT2_BIT_MASK\r
899#define SCSI_In_DBx__5__BYP CYREG_PRT2_BYP\r
900#define SCSI_In_DBx__5__CTL CYREG_PRT2_CTL\r
901#define SCSI_In_DBx__5__DM0 CYREG_PRT2_DM0\r
902#define SCSI_In_DBx__5__DM1 CYREG_PRT2_DM1\r
903#define SCSI_In_DBx__5__DM2 CYREG_PRT2_DM2\r
904#define SCSI_In_DBx__5__DR CYREG_PRT2_DR\r
905#define SCSI_In_DBx__5__INP_DIS CYREG_PRT2_INP_DIS\r
906#define SCSI_In_DBx__5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
907#define SCSI_In_DBx__5__LCD_EN CYREG_PRT2_LCD_EN\r
908#define SCSI_In_DBx__5__MASK 0x08u\r
909#define SCSI_In_DBx__5__PC CYREG_PRT2_PC3\r
910#define SCSI_In_DBx__5__PORT 2u\r
911#define SCSI_In_DBx__5__PRT CYREG_PRT2_PRT\r
912#define SCSI_In_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
913#define SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
914#define SCSI_In_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
915#define SCSI_In_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
916#define SCSI_In_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
917#define SCSI_In_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
918#define SCSI_In_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
919#define SCSI_In_DBx__5__PS CYREG_PRT2_PS\r
920#define SCSI_In_DBx__5__SHIFT 3\r
921#define SCSI_In_DBx__5__SLW CYREG_PRT2_SLW\r
922#define SCSI_In_DBx__6__AG CYREG_PRT2_AG\r
923#define SCSI_In_DBx__6__AMUX CYREG_PRT2_AMUX\r
924#define SCSI_In_DBx__6__BIE CYREG_PRT2_BIE\r
925#define SCSI_In_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK\r
926#define SCSI_In_DBx__6__BYP CYREG_PRT2_BYP\r
927#define SCSI_In_DBx__6__CTL CYREG_PRT2_CTL\r
928#define SCSI_In_DBx__6__DM0 CYREG_PRT2_DM0\r
929#define SCSI_In_DBx__6__DM1 CYREG_PRT2_DM1\r
930#define SCSI_In_DBx__6__DM2 CYREG_PRT2_DM2\r
931#define SCSI_In_DBx__6__DR CYREG_PRT2_DR\r
932#define SCSI_In_DBx__6__INP_DIS CYREG_PRT2_INP_DIS\r
933#define SCSI_In_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
934#define SCSI_In_DBx__6__LCD_EN CYREG_PRT2_LCD_EN\r
935#define SCSI_In_DBx__6__MASK 0x04u\r
936#define SCSI_In_DBx__6__PC CYREG_PRT2_PC2\r
937#define SCSI_In_DBx__6__PORT 2u\r
938#define SCSI_In_DBx__6__PRT CYREG_PRT2_PRT\r
939#define SCSI_In_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
940#define SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
941#define SCSI_In_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
942#define SCSI_In_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
943#define SCSI_In_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
944#define SCSI_In_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
945#define SCSI_In_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
946#define SCSI_In_DBx__6__PS CYREG_PRT2_PS\r
947#define SCSI_In_DBx__6__SHIFT 2\r
948#define SCSI_In_DBx__6__SLW CYREG_PRT2_SLW\r
949#define SCSI_In_DBx__7__AG CYREG_PRT2_AG\r
950#define SCSI_In_DBx__7__AMUX CYREG_PRT2_AMUX\r
951#define SCSI_In_DBx__7__BIE CYREG_PRT2_BIE\r
952#define SCSI_In_DBx__7__BIT_MASK CYREG_PRT2_BIT_MASK\r
953#define SCSI_In_DBx__7__BYP CYREG_PRT2_BYP\r
954#define SCSI_In_DBx__7__CTL CYREG_PRT2_CTL\r
955#define SCSI_In_DBx__7__DM0 CYREG_PRT2_DM0\r
956#define SCSI_In_DBx__7__DM1 CYREG_PRT2_DM1\r
957#define SCSI_In_DBx__7__DM2 CYREG_PRT2_DM2\r
958#define SCSI_In_DBx__7__DR CYREG_PRT2_DR\r
959#define SCSI_In_DBx__7__INP_DIS CYREG_PRT2_INP_DIS\r
960#define SCSI_In_DBx__7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
961#define SCSI_In_DBx__7__LCD_EN CYREG_PRT2_LCD_EN\r
962#define SCSI_In_DBx__7__MASK 0x02u\r
963#define SCSI_In_DBx__7__PC CYREG_PRT2_PC1\r
964#define SCSI_In_DBx__7__PORT 2u\r
965#define SCSI_In_DBx__7__PRT CYREG_PRT2_PRT\r
966#define SCSI_In_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
967#define SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
968#define SCSI_In_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
969#define SCSI_In_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
970#define SCSI_In_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
971#define SCSI_In_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
972#define SCSI_In_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
973#define SCSI_In_DBx__7__PS CYREG_PRT2_PS\r
974#define SCSI_In_DBx__7__SHIFT 1\r
975#define SCSI_In_DBx__7__SLW CYREG_PRT2_SLW\r
976#define SCSI_In_DBx__DB0__AG CYREG_PRT12_AG\r
977#define SCSI_In_DBx__DB0__BIE CYREG_PRT12_BIE\r
978#define SCSI_In_DBx__DB0__BIT_MASK CYREG_PRT12_BIT_MASK\r
979#define SCSI_In_DBx__DB0__BYP CYREG_PRT12_BYP\r
980#define SCSI_In_DBx__DB0__DM0 CYREG_PRT12_DM0\r
981#define SCSI_In_DBx__DB0__DM1 CYREG_PRT12_DM1\r
982#define SCSI_In_DBx__DB0__DM2 CYREG_PRT12_DM2\r
983#define SCSI_In_DBx__DB0__DR CYREG_PRT12_DR\r
984#define SCSI_In_DBx__DB0__INP_DIS CYREG_PRT12_INP_DIS\r
985#define SCSI_In_DBx__DB0__MASK 0x10u\r
986#define SCSI_In_DBx__DB0__PC CYREG_PRT12_PC4\r
987#define SCSI_In_DBx__DB0__PORT 12u\r
988#define SCSI_In_DBx__DB0__PRT CYREG_PRT12_PRT\r
989#define SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
990#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
991#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
992#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
993#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
994#define SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
995#define SCSI_In_DBx__DB0__PS CYREG_PRT12_PS\r
996#define SCSI_In_DBx__DB0__SHIFT 4\r
997#define SCSI_In_DBx__DB0__SIO_CFG CYREG_PRT12_SIO_CFG\r
998#define SCSI_In_DBx__DB0__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
999#define SCSI_In_DBx__DB0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
1000#define SCSI_In_DBx__DB0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
1001#define SCSI_In_DBx__DB0__SLW CYREG_PRT12_SLW\r
1002#define SCSI_In_DBx__DB1__AG CYREG_PRT2_AG\r
1003#define SCSI_In_DBx__DB1__AMUX CYREG_PRT2_AMUX\r
1004#define SCSI_In_DBx__DB1__BIE CYREG_PRT2_BIE\r
1005#define SCSI_In_DBx__DB1__BIT_MASK CYREG_PRT2_BIT_MASK\r
1006#define SCSI_In_DBx__DB1__BYP CYREG_PRT2_BYP\r
1007#define SCSI_In_DBx__DB1__CTL CYREG_PRT2_CTL\r
1008#define SCSI_In_DBx__DB1__DM0 CYREG_PRT2_DM0\r
1009#define SCSI_In_DBx__DB1__DM1 CYREG_PRT2_DM1\r
1010#define SCSI_In_DBx__DB1__DM2 CYREG_PRT2_DM2\r
1011#define SCSI_In_DBx__DB1__DR CYREG_PRT2_DR\r
1012#define SCSI_In_DBx__DB1__INP_DIS CYREG_PRT2_INP_DIS\r
1013#define SCSI_In_DBx__DB1__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
1014#define SCSI_In_DBx__DB1__LCD_EN CYREG_PRT2_LCD_EN\r
1015#define SCSI_In_DBx__DB1__MASK 0x80u\r
1016#define SCSI_In_DBx__DB1__PC CYREG_PRT2_PC7\r
1017#define SCSI_In_DBx__DB1__PORT 2u\r
1018#define SCSI_In_DBx__DB1__PRT CYREG_PRT2_PRT\r
1019#define SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
1020#define SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
1021#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
1022#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
1023#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
1024#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
1025#define SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
1026#define SCSI_In_DBx__DB1__PS CYREG_PRT2_PS\r
1027#define SCSI_In_DBx__DB1__SHIFT 7\r
1028#define SCSI_In_DBx__DB1__SLW CYREG_PRT2_SLW\r
1029#define SCSI_In_DBx__DB2__AG CYREG_PRT2_AG\r
1030#define SCSI_In_DBx__DB2__AMUX CYREG_PRT2_AMUX\r
1031#define SCSI_In_DBx__DB2__BIE CYREG_PRT2_BIE\r
1032#define SCSI_In_DBx__DB2__BIT_MASK CYREG_PRT2_BIT_MASK\r
1033#define SCSI_In_DBx__DB2__BYP CYREG_PRT2_BYP\r
1034#define SCSI_In_DBx__DB2__CTL CYREG_PRT2_CTL\r
1035#define SCSI_In_DBx__DB2__DM0 CYREG_PRT2_DM0\r
1036#define SCSI_In_DBx__DB2__DM1 CYREG_PRT2_DM1\r
1037#define SCSI_In_DBx__DB2__DM2 CYREG_PRT2_DM2\r
1038#define SCSI_In_DBx__DB2__DR CYREG_PRT2_DR\r
1039#define SCSI_In_DBx__DB2__INP_DIS CYREG_PRT2_INP_DIS\r
1040#define SCSI_In_DBx__DB2__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
1041#define SCSI_In_DBx__DB2__LCD_EN CYREG_PRT2_LCD_EN\r
1042#define SCSI_In_DBx__DB2__MASK 0x40u\r
1043#define SCSI_In_DBx__DB2__PC CYREG_PRT2_PC6\r
1044#define SCSI_In_DBx__DB2__PORT 2u\r
1045#define SCSI_In_DBx__DB2__PRT CYREG_PRT2_PRT\r
1046#define SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
1047#define SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
1048#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
1049#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
1050#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
1051#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
1052#define SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
1053#define SCSI_In_DBx__DB2__PS CYREG_PRT2_PS\r
1054#define SCSI_In_DBx__DB2__SHIFT 6\r
1055#define SCSI_In_DBx__DB2__SLW CYREG_PRT2_SLW\r
1056#define SCSI_In_DBx__DB3__AG CYREG_PRT2_AG\r
1057#define SCSI_In_DBx__DB3__AMUX CYREG_PRT2_AMUX\r
1058#define SCSI_In_DBx__DB3__BIE CYREG_PRT2_BIE\r
1059#define SCSI_In_DBx__DB3__BIT_MASK CYREG_PRT2_BIT_MASK\r
1060#define SCSI_In_DBx__DB3__BYP CYREG_PRT2_BYP\r
1061#define SCSI_In_DBx__DB3__CTL CYREG_PRT2_CTL\r
1062#define SCSI_In_DBx__DB3__DM0 CYREG_PRT2_DM0\r
1063#define SCSI_In_DBx__DB3__DM1 CYREG_PRT2_DM1\r
1064#define SCSI_In_DBx__DB3__DM2 CYREG_PRT2_DM2\r
1065#define SCSI_In_DBx__DB3__DR CYREG_PRT2_DR\r
1066#define SCSI_In_DBx__DB3__INP_DIS CYREG_PRT2_INP_DIS\r
1067#define SCSI_In_DBx__DB3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
1068#define SCSI_In_DBx__DB3__LCD_EN CYREG_PRT2_LCD_EN\r
1069#define SCSI_In_DBx__DB3__MASK 0x20u\r
1070#define SCSI_In_DBx__DB3__PC CYREG_PRT2_PC5\r
1071#define SCSI_In_DBx__DB3__PORT 2u\r
1072#define SCSI_In_DBx__DB3__PRT CYREG_PRT2_PRT\r
1073#define SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
1074#define SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
1075#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
1076#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
1077#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
1078#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
1079#define SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
1080#define SCSI_In_DBx__DB3__PS CYREG_PRT2_PS\r
1081#define SCSI_In_DBx__DB3__SHIFT 5\r
1082#define SCSI_In_DBx__DB3__SLW CYREG_PRT2_SLW\r
1083#define SCSI_In_DBx__DB4__AG CYREG_PRT2_AG\r
1084#define SCSI_In_DBx__DB4__AMUX CYREG_PRT2_AMUX\r
1085#define SCSI_In_DBx__DB4__BIE CYREG_PRT2_BIE\r
1086#define SCSI_In_DBx__DB4__BIT_MASK CYREG_PRT2_BIT_MASK\r
1087#define SCSI_In_DBx__DB4__BYP CYREG_PRT2_BYP\r
1088#define SCSI_In_DBx__DB4__CTL CYREG_PRT2_CTL\r
1089#define SCSI_In_DBx__DB4__DM0 CYREG_PRT2_DM0\r
1090#define SCSI_In_DBx__DB4__DM1 CYREG_PRT2_DM1\r
1091#define SCSI_In_DBx__DB4__DM2 CYREG_PRT2_DM2\r
1092#define SCSI_In_DBx__DB4__DR CYREG_PRT2_DR\r
1093#define SCSI_In_DBx__DB4__INP_DIS CYREG_PRT2_INP_DIS\r
1094#define SCSI_In_DBx__DB4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
1095#define SCSI_In_DBx__DB4__LCD_EN CYREG_PRT2_LCD_EN\r
1096#define SCSI_In_DBx__DB4__MASK 0x10u\r
1097#define SCSI_In_DBx__DB4__PC CYREG_PRT2_PC4\r
1098#define SCSI_In_DBx__DB4__PORT 2u\r
1099#define SCSI_In_DBx__DB4__PRT CYREG_PRT2_PRT\r
1100#define SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
1101#define SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
1102#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
1103#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
1104#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
1105#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
1106#define SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
1107#define SCSI_In_DBx__DB4__PS CYREG_PRT2_PS\r
1108#define SCSI_In_DBx__DB4__SHIFT 4\r
1109#define SCSI_In_DBx__DB4__SLW CYREG_PRT2_SLW\r
1110#define SCSI_In_DBx__DB5__AG CYREG_PRT2_AG\r
1111#define SCSI_In_DBx__DB5__AMUX CYREG_PRT2_AMUX\r
1112#define SCSI_In_DBx__DB5__BIE CYREG_PRT2_BIE\r
1113#define SCSI_In_DBx__DB5__BIT_MASK CYREG_PRT2_BIT_MASK\r
1114#define SCSI_In_DBx__DB5__BYP CYREG_PRT2_BYP\r
1115#define SCSI_In_DBx__DB5__CTL CYREG_PRT2_CTL\r
1116#define SCSI_In_DBx__DB5__DM0 CYREG_PRT2_DM0\r
1117#define SCSI_In_DBx__DB5__DM1 CYREG_PRT2_DM1\r
1118#define SCSI_In_DBx__DB5__DM2 CYREG_PRT2_DM2\r
1119#define SCSI_In_DBx__DB5__DR CYREG_PRT2_DR\r
1120#define SCSI_In_DBx__DB5__INP_DIS CYREG_PRT2_INP_DIS\r
1121#define SCSI_In_DBx__DB5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
1122#define SCSI_In_DBx__DB5__LCD_EN CYREG_PRT2_LCD_EN\r
1123#define SCSI_In_DBx__DB5__MASK 0x08u\r
1124#define SCSI_In_DBx__DB5__PC CYREG_PRT2_PC3\r
1125#define SCSI_In_DBx__DB5__PORT 2u\r
1126#define SCSI_In_DBx__DB5__PRT CYREG_PRT2_PRT\r
1127#define SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
1128#define SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
1129#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
1130#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
1131#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
1132#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
1133#define SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
1134#define SCSI_In_DBx__DB5__PS CYREG_PRT2_PS\r
1135#define SCSI_In_DBx__DB5__SHIFT 3\r
1136#define SCSI_In_DBx__DB5__SLW CYREG_PRT2_SLW\r
1137#define SCSI_In_DBx__DB6__AG CYREG_PRT2_AG\r
1138#define SCSI_In_DBx__DB6__AMUX CYREG_PRT2_AMUX\r
1139#define SCSI_In_DBx__DB6__BIE CYREG_PRT2_BIE\r
1140#define SCSI_In_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK\r
1141#define SCSI_In_DBx__DB6__BYP CYREG_PRT2_BYP\r
1142#define SCSI_In_DBx__DB6__CTL CYREG_PRT2_CTL\r
1143#define SCSI_In_DBx__DB6__DM0 CYREG_PRT2_DM0\r
1144#define SCSI_In_DBx__DB6__DM1 CYREG_PRT2_DM1\r
1145#define SCSI_In_DBx__DB6__DM2 CYREG_PRT2_DM2\r
1146#define SCSI_In_DBx__DB6__DR CYREG_PRT2_DR\r
1147#define SCSI_In_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS\r
1148#define SCSI_In_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
1149#define SCSI_In_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN\r
1150#define SCSI_In_DBx__DB6__MASK 0x04u\r
1151#define SCSI_In_DBx__DB6__PC CYREG_PRT2_PC2\r
1152#define SCSI_In_DBx__DB6__PORT 2u\r
1153#define SCSI_In_DBx__DB6__PRT CYREG_PRT2_PRT\r
1154#define SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
1155#define SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
1156#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
1157#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
1158#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
1159#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
1160#define SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
1161#define SCSI_In_DBx__DB6__PS CYREG_PRT2_PS\r
1162#define SCSI_In_DBx__DB6__SHIFT 2\r
1163#define SCSI_In_DBx__DB6__SLW CYREG_PRT2_SLW\r
1164#define SCSI_In_DBx__DB7__AG CYREG_PRT2_AG\r
1165#define SCSI_In_DBx__DB7__AMUX CYREG_PRT2_AMUX\r
1166#define SCSI_In_DBx__DB7__BIE CYREG_PRT2_BIE\r
1167#define SCSI_In_DBx__DB7__BIT_MASK CYREG_PRT2_BIT_MASK\r
1168#define SCSI_In_DBx__DB7__BYP CYREG_PRT2_BYP\r
1169#define SCSI_In_DBx__DB7__CTL CYREG_PRT2_CTL\r
1170#define SCSI_In_DBx__DB7__DM0 CYREG_PRT2_DM0\r
1171#define SCSI_In_DBx__DB7__DM1 CYREG_PRT2_DM1\r
1172#define SCSI_In_DBx__DB7__DM2 CYREG_PRT2_DM2\r
1173#define SCSI_In_DBx__DB7__DR CYREG_PRT2_DR\r
1174#define SCSI_In_DBx__DB7__INP_DIS CYREG_PRT2_INP_DIS\r
1175#define SCSI_In_DBx__DB7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
1176#define SCSI_In_DBx__DB7__LCD_EN CYREG_PRT2_LCD_EN\r
1177#define SCSI_In_DBx__DB7__MASK 0x02u\r
1178#define SCSI_In_DBx__DB7__PC CYREG_PRT2_PC1\r
1179#define SCSI_In_DBx__DB7__PORT 2u\r
1180#define SCSI_In_DBx__DB7__PRT CYREG_PRT2_PRT\r
1181#define SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
1182#define SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
1183#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
1184#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
1185#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
1186#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
1187#define SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
1188#define SCSI_In_DBx__DB7__PS CYREG_PRT2_PS\r
1189#define SCSI_In_DBx__DB7__SHIFT 1\r
1190#define SCSI_In_DBx__DB7__SLW CYREG_PRT2_SLW\r
1191\r
1192/* SD_DAT1 */\r
1193#define SD_DAT1__0__MASK 0x01u\r
1194#define SD_DAT1__0__PC CYREG_PRT3_PC0\r
1195#define SD_DAT1__0__PORT 3u\r
1196#define SD_DAT1__0__SHIFT 0\r
1197#define SD_DAT1__AG CYREG_PRT3_AG\r
1198#define SD_DAT1__AMUX CYREG_PRT3_AMUX\r
1199#define SD_DAT1__BIE CYREG_PRT3_BIE\r
1200#define SD_DAT1__BIT_MASK CYREG_PRT3_BIT_MASK\r
1201#define SD_DAT1__BYP CYREG_PRT3_BYP\r
1202#define SD_DAT1__CTL CYREG_PRT3_CTL\r
1203#define SD_DAT1__DM0 CYREG_PRT3_DM0\r
1204#define SD_DAT1__DM1 CYREG_PRT3_DM1\r
1205#define SD_DAT1__DM2 CYREG_PRT3_DM2\r
1206#define SD_DAT1__DR CYREG_PRT3_DR\r
1207#define SD_DAT1__INP_DIS CYREG_PRT3_INP_DIS\r
1208#define SD_DAT1__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
1209#define SD_DAT1__LCD_EN CYREG_PRT3_LCD_EN\r
1210#define SD_DAT1__MASK 0x01u\r
1211#define SD_DAT1__PORT 3u\r
1212#define SD_DAT1__PRT CYREG_PRT3_PRT\r
1213#define SD_DAT1__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
1214#define SD_DAT1__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
1215#define SD_DAT1__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
1216#define SD_DAT1__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
1217#define SD_DAT1__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
1218#define SD_DAT1__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
1219#define SD_DAT1__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
1220#define SD_DAT1__PS CYREG_PRT3_PS\r
1221#define SD_DAT1__SHIFT 0\r
1222#define SD_DAT1__SLW CYREG_PRT3_SLW\r
1223\r
1224/* SD_DAT2 */\r
1225#define SD_DAT2__0__MASK 0x20u\r
1226#define SD_DAT2__0__PC CYREG_PRT3_PC5\r
1227#define SD_DAT2__0__PORT 3u\r
1228#define SD_DAT2__0__SHIFT 5\r
1229#define SD_DAT2__AG CYREG_PRT3_AG\r
1230#define SD_DAT2__AMUX CYREG_PRT3_AMUX\r
1231#define SD_DAT2__BIE CYREG_PRT3_BIE\r
1232#define SD_DAT2__BIT_MASK CYREG_PRT3_BIT_MASK\r
1233#define SD_DAT2__BYP CYREG_PRT3_BYP\r
1234#define SD_DAT2__CTL CYREG_PRT3_CTL\r
1235#define SD_DAT2__DM0 CYREG_PRT3_DM0\r
1236#define SD_DAT2__DM1 CYREG_PRT3_DM1\r
1237#define SD_DAT2__DM2 CYREG_PRT3_DM2\r
1238#define SD_DAT2__DR CYREG_PRT3_DR\r
1239#define SD_DAT2__INP_DIS CYREG_PRT3_INP_DIS\r
1240#define SD_DAT2__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
1241#define SD_DAT2__LCD_EN CYREG_PRT3_LCD_EN\r
1242#define SD_DAT2__MASK 0x20u\r
1243#define SD_DAT2__PORT 3u\r
1244#define SD_DAT2__PRT CYREG_PRT3_PRT\r
1245#define SD_DAT2__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
1246#define SD_DAT2__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
1247#define SD_DAT2__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
1248#define SD_DAT2__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
1249#define SD_DAT2__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
1250#define SD_DAT2__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
1251#define SD_DAT2__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
1252#define SD_DAT2__PS CYREG_PRT3_PS\r
1253#define SD_DAT2__SHIFT 5\r
1254#define SD_DAT2__SLW CYREG_PRT3_SLW\r
1255\r
1256/* SD_MISO */\r
1257#define SD_MISO__0__MASK 0x02u\r
1258#define SD_MISO__0__PC CYREG_PRT3_PC1\r
1259#define SD_MISO__0__PORT 3u\r
1260#define SD_MISO__0__SHIFT 1\r
1261#define SD_MISO__AG CYREG_PRT3_AG\r
1262#define SD_MISO__AMUX CYREG_PRT3_AMUX\r
1263#define SD_MISO__BIE CYREG_PRT3_BIE\r
1264#define SD_MISO__BIT_MASK CYREG_PRT3_BIT_MASK\r
1265#define SD_MISO__BYP CYREG_PRT3_BYP\r
1266#define SD_MISO__CTL CYREG_PRT3_CTL\r
1267#define SD_MISO__DM0 CYREG_PRT3_DM0\r
1268#define SD_MISO__DM1 CYREG_PRT3_DM1\r
1269#define SD_MISO__DM2 CYREG_PRT3_DM2\r
1270#define SD_MISO__DR CYREG_PRT3_DR\r
1271#define SD_MISO__INP_DIS CYREG_PRT3_INP_DIS\r
1272#define SD_MISO__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
1273#define SD_MISO__LCD_EN CYREG_PRT3_LCD_EN\r
1274#define SD_MISO__MASK 0x02u\r
1275#define SD_MISO__PORT 3u\r
1276#define SD_MISO__PRT CYREG_PRT3_PRT\r
1277#define SD_MISO__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
1278#define SD_MISO__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
1279#define SD_MISO__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
1280#define SD_MISO__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
1281#define SD_MISO__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
1282#define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
1283#define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
1284#define SD_MISO__PS CYREG_PRT3_PS\r
1285#define SD_MISO__SHIFT 1\r
1286#define SD_MISO__SLW CYREG_PRT3_SLW\r
1287\r
1288/* SD_MOSI */\r
1289#define SD_MOSI__0__MASK 0x08u\r
1290#define SD_MOSI__0__PC CYREG_PRT3_PC3\r
1291#define SD_MOSI__0__PORT 3u\r
1292#define SD_MOSI__0__SHIFT 3\r
1293#define SD_MOSI__AG CYREG_PRT3_AG\r
1294#define SD_MOSI__AMUX CYREG_PRT3_AMUX\r
1295#define SD_MOSI__BIE CYREG_PRT3_BIE\r
1296#define SD_MOSI__BIT_MASK CYREG_PRT3_BIT_MASK\r
1297#define SD_MOSI__BYP CYREG_PRT3_BYP\r
1298#define SD_MOSI__CTL CYREG_PRT3_CTL\r
1299#define SD_MOSI__DM0 CYREG_PRT3_DM0\r
1300#define SD_MOSI__DM1 CYREG_PRT3_DM1\r
1301#define SD_MOSI__DM2 CYREG_PRT3_DM2\r
1302#define SD_MOSI__DR CYREG_PRT3_DR\r
1303#define SD_MOSI__INP_DIS CYREG_PRT3_INP_DIS\r
1304#define SD_MOSI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
1305#define SD_MOSI__LCD_EN CYREG_PRT3_LCD_EN\r
1306#define SD_MOSI__MASK 0x08u\r
1307#define SD_MOSI__PORT 3u\r
1308#define SD_MOSI__PRT CYREG_PRT3_PRT\r
1309#define SD_MOSI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
1310#define SD_MOSI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
1311#define SD_MOSI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
1312#define SD_MOSI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
1313#define SD_MOSI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
1314#define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
1315#define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
1316#define SD_MOSI__PS CYREG_PRT3_PS\r
1317#define SD_MOSI__SHIFT 3\r
1318#define SD_MOSI__SLW CYREG_PRT3_SLW\r
1319\r
1320/* SCSI_CLK */\r
1321#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0\r
1322#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1\r
1323#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2\r
1324#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u\r
1325#define SCSI_CLK__INDEX 0x01u\r
1326#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2\r
1327#define SCSI_CLK__PM_ACT_MSK 0x02u\r
1328#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
1329#define SCSI_CLK__PM_STBY_MSK 0x02u\r
1330\r
1331/* SCSI_Out */\r
1332#define SCSI_Out__0__AG CYREG_PRT4_AG\r
1333#define SCSI_Out__0__AMUX CYREG_PRT4_AMUX\r
1334#define SCSI_Out__0__BIE CYREG_PRT4_BIE\r
1335#define SCSI_Out__0__BIT_MASK CYREG_PRT4_BIT_MASK\r
1336#define SCSI_Out__0__BYP CYREG_PRT4_BYP\r
1337#define SCSI_Out__0__CTL CYREG_PRT4_CTL\r
1338#define SCSI_Out__0__DM0 CYREG_PRT4_DM0\r
1339#define SCSI_Out__0__DM1 CYREG_PRT4_DM1\r
1340#define SCSI_Out__0__DM2 CYREG_PRT4_DM2\r
1341#define SCSI_Out__0__DR CYREG_PRT4_DR\r
1342#define SCSI_Out__0__INP_DIS CYREG_PRT4_INP_DIS\r
1343#define SCSI_Out__0__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
1344#define SCSI_Out__0__LCD_EN CYREG_PRT4_LCD_EN\r
1345#define SCSI_Out__0__MASK 0x08u\r
1346#define SCSI_Out__0__PC CYREG_PRT4_PC3\r
1347#define SCSI_Out__0__PORT 4u\r
1348#define SCSI_Out__0__PRT CYREG_PRT4_PRT\r
1349#define SCSI_Out__0__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
1350#define SCSI_Out__0__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
1351#define SCSI_Out__0__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
1352#define SCSI_Out__0__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
1353#define SCSI_Out__0__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
1354#define SCSI_Out__0__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
1355#define SCSI_Out__0__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
1356#define SCSI_Out__0__PS CYREG_PRT4_PS\r
1357#define SCSI_Out__0__SHIFT 3\r
1358#define SCSI_Out__0__SLW CYREG_PRT4_SLW\r
1359#define SCSI_Out__1__AG CYREG_PRT4_AG\r
1360#define SCSI_Out__1__AMUX CYREG_PRT4_AMUX\r
1361#define SCSI_Out__1__BIE CYREG_PRT4_BIE\r
1362#define SCSI_Out__1__BIT_MASK CYREG_PRT4_BIT_MASK\r
1363#define SCSI_Out__1__BYP CYREG_PRT4_BYP\r
1364#define SCSI_Out__1__CTL CYREG_PRT4_CTL\r
1365#define SCSI_Out__1__DM0 CYREG_PRT4_DM0\r
1366#define SCSI_Out__1__DM1 CYREG_PRT4_DM1\r
1367#define SCSI_Out__1__DM2 CYREG_PRT4_DM2\r
1368#define SCSI_Out__1__DR CYREG_PRT4_DR\r
1369#define SCSI_Out__1__INP_DIS CYREG_PRT4_INP_DIS\r
1370#define SCSI_Out__1__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
1371#define SCSI_Out__1__LCD_EN CYREG_PRT4_LCD_EN\r
1372#define SCSI_Out__1__MASK 0x04u\r
1373#define SCSI_Out__1__PC CYREG_PRT4_PC2\r
1374#define SCSI_Out__1__PORT 4u\r
1375#define SCSI_Out__1__PRT CYREG_PRT4_PRT\r
1376#define SCSI_Out__1__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
1377#define SCSI_Out__1__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
1378#define SCSI_Out__1__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
1379#define SCSI_Out__1__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
1380#define SCSI_Out__1__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
1381#define SCSI_Out__1__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
1382#define SCSI_Out__1__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
1383#define SCSI_Out__1__PS CYREG_PRT4_PS\r
1384#define SCSI_Out__1__SHIFT 2\r
1385#define SCSI_Out__1__SLW CYREG_PRT4_SLW\r
1386#define SCSI_Out__2__AG CYREG_PRT0_AG\r
1387#define SCSI_Out__2__AMUX CYREG_PRT0_AMUX\r
1388#define SCSI_Out__2__BIE CYREG_PRT0_BIE\r
1389#define SCSI_Out__2__BIT_MASK CYREG_PRT0_BIT_MASK\r
1390#define SCSI_Out__2__BYP CYREG_PRT0_BYP\r
1391#define SCSI_Out__2__CTL CYREG_PRT0_CTL\r
1392#define SCSI_Out__2__DM0 CYREG_PRT0_DM0\r
1393#define SCSI_Out__2__DM1 CYREG_PRT0_DM1\r
1394#define SCSI_Out__2__DM2 CYREG_PRT0_DM2\r
1395#define SCSI_Out__2__DR CYREG_PRT0_DR\r
1396#define SCSI_Out__2__INP_DIS CYREG_PRT0_INP_DIS\r
1397#define SCSI_Out__2__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
1398#define SCSI_Out__2__LCD_EN CYREG_PRT0_LCD_EN\r
1399#define SCSI_Out__2__MASK 0x80u\r
1400#define SCSI_Out__2__PC CYREG_PRT0_PC7\r
1401#define SCSI_Out__2__PORT 0u\r
1402#define SCSI_Out__2__PRT CYREG_PRT0_PRT\r
1403#define SCSI_Out__2__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
1404#define SCSI_Out__2__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
1405#define SCSI_Out__2__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
1406#define SCSI_Out__2__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
1407#define SCSI_Out__2__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
1408#define SCSI_Out__2__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
1409#define SCSI_Out__2__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
1410#define SCSI_Out__2__PS CYREG_PRT0_PS\r
1411#define SCSI_Out__2__SHIFT 7\r
1412#define SCSI_Out__2__SLW CYREG_PRT0_SLW\r
1413#define SCSI_Out__3__AG CYREG_PRT0_AG\r
1414#define SCSI_Out__3__AMUX CYREG_PRT0_AMUX\r
1415#define SCSI_Out__3__BIE CYREG_PRT0_BIE\r
1416#define SCSI_Out__3__BIT_MASK CYREG_PRT0_BIT_MASK\r
1417#define SCSI_Out__3__BYP CYREG_PRT0_BYP\r
1418#define SCSI_Out__3__CTL CYREG_PRT0_CTL\r
1419#define SCSI_Out__3__DM0 CYREG_PRT0_DM0\r
1420#define SCSI_Out__3__DM1 CYREG_PRT0_DM1\r
1421#define SCSI_Out__3__DM2 CYREG_PRT0_DM2\r
1422#define SCSI_Out__3__DR CYREG_PRT0_DR\r
1423#define SCSI_Out__3__INP_DIS CYREG_PRT0_INP_DIS\r
1424#define SCSI_Out__3__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
1425#define SCSI_Out__3__LCD_EN CYREG_PRT0_LCD_EN\r
1426#define SCSI_Out__3__MASK 0x40u\r
1427#define SCSI_Out__3__PC CYREG_PRT0_PC6\r
1428#define SCSI_Out__3__PORT 0u\r
1429#define SCSI_Out__3__PRT CYREG_PRT0_PRT\r
1430#define SCSI_Out__3__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
1431#define SCSI_Out__3__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
1432#define SCSI_Out__3__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
1433#define SCSI_Out__3__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
1434#define SCSI_Out__3__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
1435#define SCSI_Out__3__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
1436#define SCSI_Out__3__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
1437#define SCSI_Out__3__PS CYREG_PRT0_PS\r
1438#define SCSI_Out__3__SHIFT 6\r
1439#define SCSI_Out__3__SLW CYREG_PRT0_SLW\r
1440#define SCSI_Out__4__AG CYREG_PRT0_AG\r
1441#define SCSI_Out__4__AMUX CYREG_PRT0_AMUX\r
1442#define SCSI_Out__4__BIE CYREG_PRT0_BIE\r
1443#define SCSI_Out__4__BIT_MASK CYREG_PRT0_BIT_MASK\r
1444#define SCSI_Out__4__BYP CYREG_PRT0_BYP\r
1445#define SCSI_Out__4__CTL CYREG_PRT0_CTL\r
1446#define SCSI_Out__4__DM0 CYREG_PRT0_DM0\r
1447#define SCSI_Out__4__DM1 CYREG_PRT0_DM1\r
1448#define SCSI_Out__4__DM2 CYREG_PRT0_DM2\r
1449#define SCSI_Out__4__DR CYREG_PRT0_DR\r
1450#define SCSI_Out__4__INP_DIS CYREG_PRT0_INP_DIS\r
1451#define SCSI_Out__4__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
1452#define SCSI_Out__4__LCD_EN CYREG_PRT0_LCD_EN\r
1453#define SCSI_Out__4__MASK 0x20u\r
1454#define SCSI_Out__4__PC CYREG_PRT0_PC5\r
1455#define SCSI_Out__4__PORT 0u\r
1456#define SCSI_Out__4__PRT CYREG_PRT0_PRT\r
1457#define SCSI_Out__4__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
1458#define SCSI_Out__4__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
1459#define SCSI_Out__4__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
1460#define SCSI_Out__4__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
1461#define SCSI_Out__4__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
1462#define SCSI_Out__4__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
1463#define SCSI_Out__4__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
1464#define SCSI_Out__4__PS CYREG_PRT0_PS\r
1465#define SCSI_Out__4__SHIFT 5\r
1466#define SCSI_Out__4__SLW CYREG_PRT0_SLW\r
1467#define SCSI_Out__5__AG CYREG_PRT0_AG\r
1468#define SCSI_Out__5__AMUX CYREG_PRT0_AMUX\r
1469#define SCSI_Out__5__BIE CYREG_PRT0_BIE\r
1470#define SCSI_Out__5__BIT_MASK CYREG_PRT0_BIT_MASK\r
1471#define SCSI_Out__5__BYP CYREG_PRT0_BYP\r
1472#define SCSI_Out__5__CTL CYREG_PRT0_CTL\r
1473#define SCSI_Out__5__DM0 CYREG_PRT0_DM0\r
1474#define SCSI_Out__5__DM1 CYREG_PRT0_DM1\r
1475#define SCSI_Out__5__DM2 CYREG_PRT0_DM2\r
1476#define SCSI_Out__5__DR CYREG_PRT0_DR\r
1477#define SCSI_Out__5__INP_DIS CYREG_PRT0_INP_DIS\r
1478#define SCSI_Out__5__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
1479#define SCSI_Out__5__LCD_EN CYREG_PRT0_LCD_EN\r
1480#define SCSI_Out__5__MASK 0x10u\r
1481#define SCSI_Out__5__PC CYREG_PRT0_PC4\r
1482#define SCSI_Out__5__PORT 0u\r
1483#define SCSI_Out__5__PRT CYREG_PRT0_PRT\r
1484#define SCSI_Out__5__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
1485#define SCSI_Out__5__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
1486#define SCSI_Out__5__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
1487#define SCSI_Out__5__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
1488#define SCSI_Out__5__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
1489#define SCSI_Out__5__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
1490#define SCSI_Out__5__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
1491#define SCSI_Out__5__PS CYREG_PRT0_PS\r
1492#define SCSI_Out__5__SHIFT 4\r
1493#define SCSI_Out__5__SLW CYREG_PRT0_SLW\r
1494#define SCSI_Out__6__AG CYREG_PRT0_AG\r
1495#define SCSI_Out__6__AMUX CYREG_PRT0_AMUX\r
1496#define SCSI_Out__6__BIE CYREG_PRT0_BIE\r
1497#define SCSI_Out__6__BIT_MASK CYREG_PRT0_BIT_MASK\r
1498#define SCSI_Out__6__BYP CYREG_PRT0_BYP\r
1499#define SCSI_Out__6__CTL CYREG_PRT0_CTL\r
1500#define SCSI_Out__6__DM0 CYREG_PRT0_DM0\r
1501#define SCSI_Out__6__DM1 CYREG_PRT0_DM1\r
1502#define SCSI_Out__6__DM2 CYREG_PRT0_DM2\r
1503#define SCSI_Out__6__DR CYREG_PRT0_DR\r
1504#define SCSI_Out__6__INP_DIS CYREG_PRT0_INP_DIS\r
1505#define SCSI_Out__6__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
1506#define SCSI_Out__6__LCD_EN CYREG_PRT0_LCD_EN\r
1507#define SCSI_Out__6__MASK 0x08u\r
1508#define SCSI_Out__6__PC CYREG_PRT0_PC3\r
1509#define SCSI_Out__6__PORT 0u\r
1510#define SCSI_Out__6__PRT CYREG_PRT0_PRT\r
1511#define SCSI_Out__6__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
1512#define SCSI_Out__6__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
1513#define SCSI_Out__6__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
1514#define SCSI_Out__6__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
1515#define SCSI_Out__6__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
1516#define SCSI_Out__6__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
1517#define SCSI_Out__6__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
1518#define SCSI_Out__6__PS CYREG_PRT0_PS\r
1519#define SCSI_Out__6__SHIFT 3\r
1520#define SCSI_Out__6__SLW CYREG_PRT0_SLW\r
1521#define SCSI_Out__7__AG CYREG_PRT0_AG\r
1522#define SCSI_Out__7__AMUX CYREG_PRT0_AMUX\r
1523#define SCSI_Out__7__BIE CYREG_PRT0_BIE\r
1524#define SCSI_Out__7__BIT_MASK CYREG_PRT0_BIT_MASK\r
1525#define SCSI_Out__7__BYP CYREG_PRT0_BYP\r
1526#define SCSI_Out__7__CTL CYREG_PRT0_CTL\r
1527#define SCSI_Out__7__DM0 CYREG_PRT0_DM0\r
1528#define SCSI_Out__7__DM1 CYREG_PRT0_DM1\r
1529#define SCSI_Out__7__DM2 CYREG_PRT0_DM2\r
1530#define SCSI_Out__7__DR CYREG_PRT0_DR\r
1531#define SCSI_Out__7__INP_DIS CYREG_PRT0_INP_DIS\r
1532#define SCSI_Out__7__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
1533#define SCSI_Out__7__LCD_EN CYREG_PRT0_LCD_EN\r
1534#define SCSI_Out__7__MASK 0x04u\r
1535#define SCSI_Out__7__PC CYREG_PRT0_PC2\r
1536#define SCSI_Out__7__PORT 0u\r
1537#define SCSI_Out__7__PRT CYREG_PRT0_PRT\r
1538#define SCSI_Out__7__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
1539#define SCSI_Out__7__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
1540#define SCSI_Out__7__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
1541#define SCSI_Out__7__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
1542#define SCSI_Out__7__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
1543#define SCSI_Out__7__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
1544#define SCSI_Out__7__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
1545#define SCSI_Out__7__PS CYREG_PRT0_PS\r
1546#define SCSI_Out__7__SHIFT 2\r
1547#define SCSI_Out__7__SLW CYREG_PRT0_SLW\r
1548#define SCSI_Out__8__AG CYREG_PRT0_AG\r
1549#define SCSI_Out__8__AMUX CYREG_PRT0_AMUX\r
1550#define SCSI_Out__8__BIE CYREG_PRT0_BIE\r
1551#define SCSI_Out__8__BIT_MASK CYREG_PRT0_BIT_MASK\r
1552#define SCSI_Out__8__BYP CYREG_PRT0_BYP\r
1553#define SCSI_Out__8__CTL CYREG_PRT0_CTL\r
1554#define SCSI_Out__8__DM0 CYREG_PRT0_DM0\r
1555#define SCSI_Out__8__DM1 CYREG_PRT0_DM1\r
1556#define SCSI_Out__8__DM2 CYREG_PRT0_DM2\r
1557#define SCSI_Out__8__DR CYREG_PRT0_DR\r
1558#define SCSI_Out__8__INP_DIS CYREG_PRT0_INP_DIS\r
1559#define SCSI_Out__8__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
1560#define SCSI_Out__8__LCD_EN CYREG_PRT0_LCD_EN\r
1561#define SCSI_Out__8__MASK 0x02u\r
1562#define SCSI_Out__8__PC CYREG_PRT0_PC1\r
1563#define SCSI_Out__8__PORT 0u\r
1564#define SCSI_Out__8__PRT CYREG_PRT0_PRT\r
1565#define SCSI_Out__8__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
1566#define SCSI_Out__8__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
1567#define SCSI_Out__8__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
1568#define SCSI_Out__8__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
1569#define SCSI_Out__8__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
1570#define SCSI_Out__8__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
1571#define SCSI_Out__8__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
1572#define SCSI_Out__8__PS CYREG_PRT0_PS\r
1573#define SCSI_Out__8__SHIFT 1\r
1574#define SCSI_Out__8__SLW CYREG_PRT0_SLW\r
1575#define SCSI_Out__9__AG CYREG_PRT0_AG\r
1576#define SCSI_Out__9__AMUX CYREG_PRT0_AMUX\r
1577#define SCSI_Out__9__BIE CYREG_PRT0_BIE\r
1578#define SCSI_Out__9__BIT_MASK CYREG_PRT0_BIT_MASK\r
1579#define SCSI_Out__9__BYP CYREG_PRT0_BYP\r
1580#define SCSI_Out__9__CTL CYREG_PRT0_CTL\r
1581#define SCSI_Out__9__DM0 CYREG_PRT0_DM0\r
1582#define SCSI_Out__9__DM1 CYREG_PRT0_DM1\r
1583#define SCSI_Out__9__DM2 CYREG_PRT0_DM2\r
1584#define SCSI_Out__9__DR CYREG_PRT0_DR\r
1585#define SCSI_Out__9__INP_DIS CYREG_PRT0_INP_DIS\r
1586#define SCSI_Out__9__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
1587#define SCSI_Out__9__LCD_EN CYREG_PRT0_LCD_EN\r
1588#define SCSI_Out__9__MASK 0x01u\r
1589#define SCSI_Out__9__PC CYREG_PRT0_PC0\r
1590#define SCSI_Out__9__PORT 0u\r
1591#define SCSI_Out__9__PRT CYREG_PRT0_PRT\r
1592#define SCSI_Out__9__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
1593#define SCSI_Out__9__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
1594#define SCSI_Out__9__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
1595#define SCSI_Out__9__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
1596#define SCSI_Out__9__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
1597#define SCSI_Out__9__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
1598#define SCSI_Out__9__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
1599#define SCSI_Out__9__PS CYREG_PRT0_PS\r
1600#define SCSI_Out__9__SHIFT 0\r
1601#define SCSI_Out__9__SLW CYREG_PRT0_SLW\r
1602#define SCSI_Out__ACK__AG CYREG_PRT0_AG\r
1603#define SCSI_Out__ACK__AMUX CYREG_PRT0_AMUX\r
1604#define SCSI_Out__ACK__BIE CYREG_PRT0_BIE\r
1605#define SCSI_Out__ACK__BIT_MASK CYREG_PRT0_BIT_MASK\r
1606#define SCSI_Out__ACK__BYP CYREG_PRT0_BYP\r
1607#define SCSI_Out__ACK__CTL CYREG_PRT0_CTL\r
1608#define SCSI_Out__ACK__DM0 CYREG_PRT0_DM0\r
1609#define SCSI_Out__ACK__DM1 CYREG_PRT0_DM1\r
1610#define SCSI_Out__ACK__DM2 CYREG_PRT0_DM2\r
1611#define SCSI_Out__ACK__DR CYREG_PRT0_DR\r
1612#define SCSI_Out__ACK__INP_DIS CYREG_PRT0_INP_DIS\r
1613#define SCSI_Out__ACK__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
1614#define SCSI_Out__ACK__LCD_EN CYREG_PRT0_LCD_EN\r
1615#define SCSI_Out__ACK__MASK 0x40u\r
1616#define SCSI_Out__ACK__PC CYREG_PRT0_PC6\r
1617#define SCSI_Out__ACK__PORT 0u\r
1618#define SCSI_Out__ACK__PRT CYREG_PRT0_PRT\r
1619#define SCSI_Out__ACK__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
1620#define SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
1621#define SCSI_Out__ACK__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
1622#define SCSI_Out__ACK__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
1623#define SCSI_Out__ACK__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
1624#define SCSI_Out__ACK__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
1625#define SCSI_Out__ACK__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
1626#define SCSI_Out__ACK__PS CYREG_PRT0_PS\r
1627#define SCSI_Out__ACK__SHIFT 6\r
1628#define SCSI_Out__ACK__SLW CYREG_PRT0_SLW\r
1629#define SCSI_Out__ATN__AG CYREG_PRT4_AG\r
1630#define SCSI_Out__ATN__AMUX CYREG_PRT4_AMUX\r
1631#define SCSI_Out__ATN__BIE CYREG_PRT4_BIE\r
1632#define SCSI_Out__ATN__BIT_MASK CYREG_PRT4_BIT_MASK\r
1633#define SCSI_Out__ATN__BYP CYREG_PRT4_BYP\r
1634#define SCSI_Out__ATN__CTL CYREG_PRT4_CTL\r
1635#define SCSI_Out__ATN__DM0 CYREG_PRT4_DM0\r
1636#define SCSI_Out__ATN__DM1 CYREG_PRT4_DM1\r
1637#define SCSI_Out__ATN__DM2 CYREG_PRT4_DM2\r
1638#define SCSI_Out__ATN__DR CYREG_PRT4_DR\r
1639#define SCSI_Out__ATN__INP_DIS CYREG_PRT4_INP_DIS\r
1640#define SCSI_Out__ATN__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
1641#define SCSI_Out__ATN__LCD_EN CYREG_PRT4_LCD_EN\r
1642#define SCSI_Out__ATN__MASK 0x04u\r
1643#define SCSI_Out__ATN__PC CYREG_PRT4_PC2\r
1644#define SCSI_Out__ATN__PORT 4u\r
1645#define SCSI_Out__ATN__PRT CYREG_PRT4_PRT\r
1646#define SCSI_Out__ATN__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
1647#define SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
1648#define SCSI_Out__ATN__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
1649#define SCSI_Out__ATN__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
1650#define SCSI_Out__ATN__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
1651#define SCSI_Out__ATN__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
1652#define SCSI_Out__ATN__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
1653#define SCSI_Out__ATN__PS CYREG_PRT4_PS\r
1654#define SCSI_Out__ATN__SHIFT 2\r
1655#define SCSI_Out__ATN__SLW CYREG_PRT4_SLW\r
1656#define SCSI_Out__BSY__AG CYREG_PRT0_AG\r
1657#define SCSI_Out__BSY__AMUX CYREG_PRT0_AMUX\r
1658#define SCSI_Out__BSY__BIE CYREG_PRT0_BIE\r
1659#define SCSI_Out__BSY__BIT_MASK CYREG_PRT0_BIT_MASK\r
1660#define SCSI_Out__BSY__BYP CYREG_PRT0_BYP\r
1661#define SCSI_Out__BSY__CTL CYREG_PRT0_CTL\r
1662#define SCSI_Out__BSY__DM0 CYREG_PRT0_DM0\r
1663#define SCSI_Out__BSY__DM1 CYREG_PRT0_DM1\r
1664#define SCSI_Out__BSY__DM2 CYREG_PRT0_DM2\r
1665#define SCSI_Out__BSY__DR CYREG_PRT0_DR\r
1666#define SCSI_Out__BSY__INP_DIS CYREG_PRT0_INP_DIS\r
1667#define SCSI_Out__BSY__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
1668#define SCSI_Out__BSY__LCD_EN CYREG_PRT0_LCD_EN\r
1669#define SCSI_Out__BSY__MASK 0x80u\r
1670#define SCSI_Out__BSY__PC CYREG_PRT0_PC7\r
1671#define SCSI_Out__BSY__PORT 0u\r
1672#define SCSI_Out__BSY__PRT CYREG_PRT0_PRT\r
1673#define SCSI_Out__BSY__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
1674#define SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
1675#define SCSI_Out__BSY__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
1676#define SCSI_Out__BSY__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
1677#define SCSI_Out__BSY__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
1678#define SCSI_Out__BSY__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
1679#define SCSI_Out__BSY__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
1680#define SCSI_Out__BSY__PS CYREG_PRT0_PS\r
1681#define SCSI_Out__BSY__SHIFT 7\r
1682#define SCSI_Out__BSY__SLW CYREG_PRT0_SLW\r
1683#define SCSI_Out__CD_raw__AG CYREG_PRT0_AG\r
1684#define SCSI_Out__CD_raw__AMUX CYREG_PRT0_AMUX\r
1685#define SCSI_Out__CD_raw__BIE CYREG_PRT0_BIE\r
1686#define SCSI_Out__CD_raw__BIT_MASK CYREG_PRT0_BIT_MASK\r
1687#define SCSI_Out__CD_raw__BYP CYREG_PRT0_BYP\r
1688#define SCSI_Out__CD_raw__CTL CYREG_PRT0_CTL\r
1689#define SCSI_Out__CD_raw__DM0 CYREG_PRT0_DM0\r
1690#define SCSI_Out__CD_raw__DM1 CYREG_PRT0_DM1\r
1691#define SCSI_Out__CD_raw__DM2 CYREG_PRT0_DM2\r
1692#define SCSI_Out__CD_raw__DR CYREG_PRT0_DR\r
1693#define SCSI_Out__CD_raw__INP_DIS CYREG_PRT0_INP_DIS\r
1694#define SCSI_Out__CD_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
1695#define SCSI_Out__CD_raw__LCD_EN CYREG_PRT0_LCD_EN\r
1696#define SCSI_Out__CD_raw__MASK 0x04u\r
1697#define SCSI_Out__CD_raw__PC CYREG_PRT0_PC2\r
1698#define SCSI_Out__CD_raw__PORT 0u\r
1699#define SCSI_Out__CD_raw__PRT CYREG_PRT0_PRT\r
1700#define SCSI_Out__CD_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
1701#define SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
1702#define SCSI_Out__CD_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
1703#define SCSI_Out__CD_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
1704#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
1705#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
1706#define SCSI_Out__CD_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
1707#define SCSI_Out__CD_raw__PS CYREG_PRT0_PS\r
1708#define SCSI_Out__CD_raw__SHIFT 2\r
1709#define SCSI_Out__CD_raw__SLW CYREG_PRT0_SLW\r
1710#define SCSI_Out__DBP_raw__AG CYREG_PRT4_AG\r
1711#define SCSI_Out__DBP_raw__AMUX CYREG_PRT4_AMUX\r
1712#define SCSI_Out__DBP_raw__BIE CYREG_PRT4_BIE\r
1713#define SCSI_Out__DBP_raw__BIT_MASK CYREG_PRT4_BIT_MASK\r
1714#define SCSI_Out__DBP_raw__BYP CYREG_PRT4_BYP\r
1715#define SCSI_Out__DBP_raw__CTL CYREG_PRT4_CTL\r
1716#define SCSI_Out__DBP_raw__DM0 CYREG_PRT4_DM0\r
1717#define SCSI_Out__DBP_raw__DM1 CYREG_PRT4_DM1\r
1718#define SCSI_Out__DBP_raw__DM2 CYREG_PRT4_DM2\r
1719#define SCSI_Out__DBP_raw__DR CYREG_PRT4_DR\r
1720#define SCSI_Out__DBP_raw__INP_DIS CYREG_PRT4_INP_DIS\r
1721#define SCSI_Out__DBP_raw__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
1722#define SCSI_Out__DBP_raw__LCD_EN CYREG_PRT4_LCD_EN\r
1723#define SCSI_Out__DBP_raw__MASK 0x08u\r
1724#define SCSI_Out__DBP_raw__PC CYREG_PRT4_PC3\r
1725#define SCSI_Out__DBP_raw__PORT 4u\r
1726#define SCSI_Out__DBP_raw__PRT CYREG_PRT4_PRT\r
1727#define SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
1728#define SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
1729#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
1730#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
1731#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
1732#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
1733#define SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
1734#define SCSI_Out__DBP_raw__PS CYREG_PRT4_PS\r
1735#define SCSI_Out__DBP_raw__SHIFT 3\r
1736#define SCSI_Out__DBP_raw__SLW CYREG_PRT4_SLW\r
1737#define SCSI_Out__IO_raw__AG CYREG_PRT0_AG\r
1738#define SCSI_Out__IO_raw__AMUX CYREG_PRT0_AMUX\r
1739#define SCSI_Out__IO_raw__BIE CYREG_PRT0_BIE\r
1740#define SCSI_Out__IO_raw__BIT_MASK CYREG_PRT0_BIT_MASK\r
1741#define SCSI_Out__IO_raw__BYP CYREG_PRT0_BYP\r
1742#define SCSI_Out__IO_raw__CTL CYREG_PRT0_CTL\r
1743#define SCSI_Out__IO_raw__DM0 CYREG_PRT0_DM0\r
1744#define SCSI_Out__IO_raw__DM1 CYREG_PRT0_DM1\r
1745#define SCSI_Out__IO_raw__DM2 CYREG_PRT0_DM2\r
1746#define SCSI_Out__IO_raw__DR CYREG_PRT0_DR\r
1747#define SCSI_Out__IO_raw__INP_DIS CYREG_PRT0_INP_DIS\r
1748#define SCSI_Out__IO_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
1749#define SCSI_Out__IO_raw__LCD_EN CYREG_PRT0_LCD_EN\r
1750#define SCSI_Out__IO_raw__MASK 0x01u\r
1751#define SCSI_Out__IO_raw__PC CYREG_PRT0_PC0\r
1752#define SCSI_Out__IO_raw__PORT 0u\r
1753#define SCSI_Out__IO_raw__PRT CYREG_PRT0_PRT\r
1754#define SCSI_Out__IO_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
1755#define SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
1756#define SCSI_Out__IO_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
1757#define SCSI_Out__IO_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
1758#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
1759#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
1760#define SCSI_Out__IO_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
1761#define SCSI_Out__IO_raw__PS CYREG_PRT0_PS\r
1762#define SCSI_Out__IO_raw__SHIFT 0\r
1763#define SCSI_Out__IO_raw__SLW CYREG_PRT0_SLW\r
1764#define SCSI_Out__MSG_raw__AG CYREG_PRT0_AG\r
1765#define SCSI_Out__MSG_raw__AMUX CYREG_PRT0_AMUX\r
1766#define SCSI_Out__MSG_raw__BIE CYREG_PRT0_BIE\r
1767#define SCSI_Out__MSG_raw__BIT_MASK CYREG_PRT0_BIT_MASK\r
1768#define SCSI_Out__MSG_raw__BYP CYREG_PRT0_BYP\r
1769#define SCSI_Out__MSG_raw__CTL CYREG_PRT0_CTL\r
1770#define SCSI_Out__MSG_raw__DM0 CYREG_PRT0_DM0\r
1771#define SCSI_Out__MSG_raw__DM1 CYREG_PRT0_DM1\r
1772#define SCSI_Out__MSG_raw__DM2 CYREG_PRT0_DM2\r
1773#define SCSI_Out__MSG_raw__DR CYREG_PRT0_DR\r
1774#define SCSI_Out__MSG_raw__INP_DIS CYREG_PRT0_INP_DIS\r
1775#define SCSI_Out__MSG_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
1776#define SCSI_Out__MSG_raw__LCD_EN CYREG_PRT0_LCD_EN\r
1777#define SCSI_Out__MSG_raw__MASK 0x10u\r
1778#define SCSI_Out__MSG_raw__PC CYREG_PRT0_PC4\r
1779#define SCSI_Out__MSG_raw__PORT 0u\r
1780#define SCSI_Out__MSG_raw__PRT CYREG_PRT0_PRT\r
1781#define SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
1782#define SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
1783#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
1784#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
1785#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
1786#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
1787#define SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
1788#define SCSI_Out__MSG_raw__PS CYREG_PRT0_PS\r
1789#define SCSI_Out__MSG_raw__SHIFT 4\r
1790#define SCSI_Out__MSG_raw__SLW CYREG_PRT0_SLW\r
1791#define SCSI_Out__REQ__AG CYREG_PRT0_AG\r
1792#define SCSI_Out__REQ__AMUX CYREG_PRT0_AMUX\r
1793#define SCSI_Out__REQ__BIE CYREG_PRT0_BIE\r
1794#define SCSI_Out__REQ__BIT_MASK CYREG_PRT0_BIT_MASK\r
1795#define SCSI_Out__REQ__BYP CYREG_PRT0_BYP\r
1796#define SCSI_Out__REQ__CTL CYREG_PRT0_CTL\r
1797#define SCSI_Out__REQ__DM0 CYREG_PRT0_DM0\r
1798#define SCSI_Out__REQ__DM1 CYREG_PRT0_DM1\r
1799#define SCSI_Out__REQ__DM2 CYREG_PRT0_DM2\r
1800#define SCSI_Out__REQ__DR CYREG_PRT0_DR\r
1801#define SCSI_Out__REQ__INP_DIS CYREG_PRT0_INP_DIS\r
1802#define SCSI_Out__REQ__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
1803#define SCSI_Out__REQ__LCD_EN CYREG_PRT0_LCD_EN\r
1804#define SCSI_Out__REQ__MASK 0x02u\r
1805#define SCSI_Out__REQ__PC CYREG_PRT0_PC1\r
1806#define SCSI_Out__REQ__PORT 0u\r
1807#define SCSI_Out__REQ__PRT CYREG_PRT0_PRT\r
1808#define SCSI_Out__REQ__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
1809#define SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
1810#define SCSI_Out__REQ__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
1811#define SCSI_Out__REQ__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
1812#define SCSI_Out__REQ__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
1813#define SCSI_Out__REQ__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
1814#define SCSI_Out__REQ__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
1815#define SCSI_Out__REQ__PS CYREG_PRT0_PS\r
1816#define SCSI_Out__REQ__SHIFT 1\r
1817#define SCSI_Out__REQ__SLW CYREG_PRT0_SLW\r
1818#define SCSI_Out__RST__AG CYREG_PRT0_AG\r
1819#define SCSI_Out__RST__AMUX CYREG_PRT0_AMUX\r
1820#define SCSI_Out__RST__BIE CYREG_PRT0_BIE\r
1821#define SCSI_Out__RST__BIT_MASK CYREG_PRT0_BIT_MASK\r
1822#define SCSI_Out__RST__BYP CYREG_PRT0_BYP\r
1823#define SCSI_Out__RST__CTL CYREG_PRT0_CTL\r
1824#define SCSI_Out__RST__DM0 CYREG_PRT0_DM0\r
1825#define SCSI_Out__RST__DM1 CYREG_PRT0_DM1\r
1826#define SCSI_Out__RST__DM2 CYREG_PRT0_DM2\r
1827#define SCSI_Out__RST__DR CYREG_PRT0_DR\r
1828#define SCSI_Out__RST__INP_DIS CYREG_PRT0_INP_DIS\r
1829#define SCSI_Out__RST__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
1830#define SCSI_Out__RST__LCD_EN CYREG_PRT0_LCD_EN\r
1831#define SCSI_Out__RST__MASK 0x20u\r
1832#define SCSI_Out__RST__PC CYREG_PRT0_PC5\r
1833#define SCSI_Out__RST__PORT 0u\r
1834#define SCSI_Out__RST__PRT CYREG_PRT0_PRT\r
1835#define SCSI_Out__RST__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
1836#define SCSI_Out__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
1837#define SCSI_Out__RST__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
1838#define SCSI_Out__RST__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
1839#define SCSI_Out__RST__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
1840#define SCSI_Out__RST__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
1841#define SCSI_Out__RST__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
1842#define SCSI_Out__RST__PS CYREG_PRT0_PS\r
1843#define SCSI_Out__RST__SHIFT 5\r
1844#define SCSI_Out__RST__SLW CYREG_PRT0_SLW\r
1845#define SCSI_Out__SEL__AG CYREG_PRT0_AG\r
1846#define SCSI_Out__SEL__AMUX CYREG_PRT0_AMUX\r
1847#define SCSI_Out__SEL__BIE CYREG_PRT0_BIE\r
1848#define SCSI_Out__SEL__BIT_MASK CYREG_PRT0_BIT_MASK\r
1849#define SCSI_Out__SEL__BYP CYREG_PRT0_BYP\r
1850#define SCSI_Out__SEL__CTL CYREG_PRT0_CTL\r
1851#define SCSI_Out__SEL__DM0 CYREG_PRT0_DM0\r
1852#define SCSI_Out__SEL__DM1 CYREG_PRT0_DM1\r
1853#define SCSI_Out__SEL__DM2 CYREG_PRT0_DM2\r
1854#define SCSI_Out__SEL__DR CYREG_PRT0_DR\r
1855#define SCSI_Out__SEL__INP_DIS CYREG_PRT0_INP_DIS\r
1856#define SCSI_Out__SEL__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
1857#define SCSI_Out__SEL__LCD_EN CYREG_PRT0_LCD_EN\r
1858#define SCSI_Out__SEL__MASK 0x08u\r
1859#define SCSI_Out__SEL__PC CYREG_PRT0_PC3\r
1860#define SCSI_Out__SEL__PORT 0u\r
1861#define SCSI_Out__SEL__PRT CYREG_PRT0_PRT\r
1862#define SCSI_Out__SEL__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
1863#define SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
1864#define SCSI_Out__SEL__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
1865#define SCSI_Out__SEL__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
1866#define SCSI_Out__SEL__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
1867#define SCSI_Out__SEL__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
1868#define SCSI_Out__SEL__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
1869#define SCSI_Out__SEL__PS CYREG_PRT0_PS\r
1870#define SCSI_Out__SEL__SHIFT 3\r
1871#define SCSI_Out__SEL__SLW CYREG_PRT0_SLW\r
1872\r
1873/* SCSI_Out_Bits */\r
1874#define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u\r
1875#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0\r
1876#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u\r
1877#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1\r
1878#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
1879#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
1880#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL\r
1881#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
1882#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL\r
1883#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK\r
1884#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
1885#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK\r
1886#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
1887#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u\r
1888#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2\r
1889#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u\r
1890#define SCSI_Out_Bits_Sync_ctrl_reg__3__POS 3\r
1891#define SCSI_Out_Bits_Sync_ctrl_reg__4__MASK 0x10u\r
1892#define SCSI_Out_Bits_Sync_ctrl_reg__4__POS 4\r
1893#define SCSI_Out_Bits_Sync_ctrl_reg__5__MASK 0x20u\r
1894#define SCSI_Out_Bits_Sync_ctrl_reg__5__POS 5\r
1895#define SCSI_Out_Bits_Sync_ctrl_reg__6__MASK 0x40u\r
1896#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6\r
1897#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u\r
1898#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7\r
1899#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
1900#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL\r
1901#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL\r
1902#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL\r
1903#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL\r
1904#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu\r
1905#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
1906#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
1907#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK\r
1908\r
1909/* SCSI_Out_Ctl */\r
1910#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
1911#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0\r
95b51978
MM
1912#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL\r
1913#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL\r
1914#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL\r
1915#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL\r
1916#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL\r
1917#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK\r
1918#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK\r
1919#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK\r
1920#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK\r
1921#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL\r
1922#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL\r
1923#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL\r
1924#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL\r
1925#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL\r
70257ca8 1926#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u\r
95b51978
MM
1927#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
1928#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
1929#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK\r
70257ca8
MM
1930\r
1931/* SCSI_Out_DBx */\r
1932#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG\r
1933#define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX\r
1934#define SCSI_Out_DBx__0__BIE CYREG_PRT6_BIE\r
1935#define SCSI_Out_DBx__0__BIT_MASK CYREG_PRT6_BIT_MASK\r
1936#define SCSI_Out_DBx__0__BYP CYREG_PRT6_BYP\r
1937#define SCSI_Out_DBx__0__CTL CYREG_PRT6_CTL\r
1938#define SCSI_Out_DBx__0__DM0 CYREG_PRT6_DM0\r
1939#define SCSI_Out_DBx__0__DM1 CYREG_PRT6_DM1\r
1940#define SCSI_Out_DBx__0__DM2 CYREG_PRT6_DM2\r
1941#define SCSI_Out_DBx__0__DR CYREG_PRT6_DR\r
1942#define SCSI_Out_DBx__0__INP_DIS CYREG_PRT6_INP_DIS\r
1943#define SCSI_Out_DBx__0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
1944#define SCSI_Out_DBx__0__LCD_EN CYREG_PRT6_LCD_EN\r
1945#define SCSI_Out_DBx__0__MASK 0x08u\r
1946#define SCSI_Out_DBx__0__PC CYREG_PRT6_PC3\r
1947#define SCSI_Out_DBx__0__PORT 6u\r
1948#define SCSI_Out_DBx__0__PRT CYREG_PRT6_PRT\r
1949#define SCSI_Out_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
1950#define SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
1951#define SCSI_Out_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
1952#define SCSI_Out_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
1953#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
1954#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
1955#define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
1956#define SCSI_Out_DBx__0__PS CYREG_PRT6_PS\r
1957#define SCSI_Out_DBx__0__SHIFT 3\r
1958#define SCSI_Out_DBx__0__SLW CYREG_PRT6_SLW\r
1959#define SCSI_Out_DBx__1__AG CYREG_PRT6_AG\r
1960#define SCSI_Out_DBx__1__AMUX CYREG_PRT6_AMUX\r
1961#define SCSI_Out_DBx__1__BIE CYREG_PRT6_BIE\r
1962#define SCSI_Out_DBx__1__BIT_MASK CYREG_PRT6_BIT_MASK\r
1963#define SCSI_Out_DBx__1__BYP CYREG_PRT6_BYP\r
1964#define SCSI_Out_DBx__1__CTL CYREG_PRT6_CTL\r
1965#define SCSI_Out_DBx__1__DM0 CYREG_PRT6_DM0\r
1966#define SCSI_Out_DBx__1__DM1 CYREG_PRT6_DM1\r
1967#define SCSI_Out_DBx__1__DM2 CYREG_PRT6_DM2\r
1968#define SCSI_Out_DBx__1__DR CYREG_PRT6_DR\r
1969#define SCSI_Out_DBx__1__INP_DIS CYREG_PRT6_INP_DIS\r
1970#define SCSI_Out_DBx__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
1971#define SCSI_Out_DBx__1__LCD_EN CYREG_PRT6_LCD_EN\r
1972#define SCSI_Out_DBx__1__MASK 0x04u\r
1973#define SCSI_Out_DBx__1__PC CYREG_PRT6_PC2\r
1974#define SCSI_Out_DBx__1__PORT 6u\r
1975#define SCSI_Out_DBx__1__PRT CYREG_PRT6_PRT\r
1976#define SCSI_Out_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
1977#define SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
1978#define SCSI_Out_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
1979#define SCSI_Out_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
1980#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
1981#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
1982#define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
1983#define SCSI_Out_DBx__1__PS CYREG_PRT6_PS\r
1984#define SCSI_Out_DBx__1__SHIFT 2\r
1985#define SCSI_Out_DBx__1__SLW CYREG_PRT6_SLW\r
1986#define SCSI_Out_DBx__2__AG CYREG_PRT6_AG\r
1987#define SCSI_Out_DBx__2__AMUX CYREG_PRT6_AMUX\r
1988#define SCSI_Out_DBx__2__BIE CYREG_PRT6_BIE\r
1989#define SCSI_Out_DBx__2__BIT_MASK CYREG_PRT6_BIT_MASK\r
1990#define SCSI_Out_DBx__2__BYP CYREG_PRT6_BYP\r
1991#define SCSI_Out_DBx__2__CTL CYREG_PRT6_CTL\r
1992#define SCSI_Out_DBx__2__DM0 CYREG_PRT6_DM0\r
1993#define SCSI_Out_DBx__2__DM1 CYREG_PRT6_DM1\r
1994#define SCSI_Out_DBx__2__DM2 CYREG_PRT6_DM2\r
1995#define SCSI_Out_DBx__2__DR CYREG_PRT6_DR\r
1996#define SCSI_Out_DBx__2__INP_DIS CYREG_PRT6_INP_DIS\r
1997#define SCSI_Out_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
1998#define SCSI_Out_DBx__2__LCD_EN CYREG_PRT6_LCD_EN\r
1999#define SCSI_Out_DBx__2__MASK 0x02u\r
2000#define SCSI_Out_DBx__2__PC CYREG_PRT6_PC1\r
2001#define SCSI_Out_DBx__2__PORT 6u\r
2002#define SCSI_Out_DBx__2__PRT CYREG_PRT6_PRT\r
2003#define SCSI_Out_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
2004#define SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
2005#define SCSI_Out_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
2006#define SCSI_Out_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
2007#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
2008#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
2009#define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
2010#define SCSI_Out_DBx__2__PS CYREG_PRT6_PS\r
2011#define SCSI_Out_DBx__2__SHIFT 1\r
2012#define SCSI_Out_DBx__2__SLW CYREG_PRT6_SLW\r
2013#define SCSI_Out_DBx__3__AG CYREG_PRT6_AG\r
2014#define SCSI_Out_DBx__3__AMUX CYREG_PRT6_AMUX\r
2015#define SCSI_Out_DBx__3__BIE CYREG_PRT6_BIE\r
2016#define SCSI_Out_DBx__3__BIT_MASK CYREG_PRT6_BIT_MASK\r
2017#define SCSI_Out_DBx__3__BYP CYREG_PRT6_BYP\r
2018#define SCSI_Out_DBx__3__CTL CYREG_PRT6_CTL\r
2019#define SCSI_Out_DBx__3__DM0 CYREG_PRT6_DM0\r
2020#define SCSI_Out_DBx__3__DM1 CYREG_PRT6_DM1\r
2021#define SCSI_Out_DBx__3__DM2 CYREG_PRT6_DM2\r
2022#define SCSI_Out_DBx__3__DR CYREG_PRT6_DR\r
2023#define SCSI_Out_DBx__3__INP_DIS CYREG_PRT6_INP_DIS\r
2024#define SCSI_Out_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
2025#define SCSI_Out_DBx__3__LCD_EN CYREG_PRT6_LCD_EN\r
2026#define SCSI_Out_DBx__3__MASK 0x01u\r
2027#define SCSI_Out_DBx__3__PC CYREG_PRT6_PC0\r
2028#define SCSI_Out_DBx__3__PORT 6u\r
2029#define SCSI_Out_DBx__3__PRT CYREG_PRT6_PRT\r
2030#define SCSI_Out_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
2031#define SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
2032#define SCSI_Out_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
2033#define SCSI_Out_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
2034#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
2035#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
2036#define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
2037#define SCSI_Out_DBx__3__PS CYREG_PRT6_PS\r
2038#define SCSI_Out_DBx__3__SHIFT 0\r
2039#define SCSI_Out_DBx__3__SLW CYREG_PRT6_SLW\r
2040#define SCSI_Out_DBx__4__AG CYREG_PRT4_AG\r
2041#define SCSI_Out_DBx__4__AMUX CYREG_PRT4_AMUX\r
2042#define SCSI_Out_DBx__4__BIE CYREG_PRT4_BIE\r
2043#define SCSI_Out_DBx__4__BIT_MASK CYREG_PRT4_BIT_MASK\r
2044#define SCSI_Out_DBx__4__BYP CYREG_PRT4_BYP\r
2045#define SCSI_Out_DBx__4__CTL CYREG_PRT4_CTL\r
2046#define SCSI_Out_DBx__4__DM0 CYREG_PRT4_DM0\r
2047#define SCSI_Out_DBx__4__DM1 CYREG_PRT4_DM1\r
2048#define SCSI_Out_DBx__4__DM2 CYREG_PRT4_DM2\r
2049#define SCSI_Out_DBx__4__DR CYREG_PRT4_DR\r
2050#define SCSI_Out_DBx__4__INP_DIS CYREG_PRT4_INP_DIS\r
2051#define SCSI_Out_DBx__4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
2052#define SCSI_Out_DBx__4__LCD_EN CYREG_PRT4_LCD_EN\r
2053#define SCSI_Out_DBx__4__MASK 0x80u\r
2054#define SCSI_Out_DBx__4__PC CYREG_PRT4_PC7\r
2055#define SCSI_Out_DBx__4__PORT 4u\r
2056#define SCSI_Out_DBx__4__PRT CYREG_PRT4_PRT\r
2057#define SCSI_Out_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
2058#define SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
2059#define SCSI_Out_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
2060#define SCSI_Out_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
2061#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
2062#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
2063#define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
2064#define SCSI_Out_DBx__4__PS CYREG_PRT4_PS\r
2065#define SCSI_Out_DBx__4__SHIFT 7\r
2066#define SCSI_Out_DBx__4__SLW CYREG_PRT4_SLW\r
2067#define SCSI_Out_DBx__5__AG CYREG_PRT4_AG\r
2068#define SCSI_Out_DBx__5__AMUX CYREG_PRT4_AMUX\r
2069#define SCSI_Out_DBx__5__BIE CYREG_PRT4_BIE\r
2070#define SCSI_Out_DBx__5__BIT_MASK CYREG_PRT4_BIT_MASK\r
2071#define SCSI_Out_DBx__5__BYP CYREG_PRT4_BYP\r
2072#define SCSI_Out_DBx__5__CTL CYREG_PRT4_CTL\r
2073#define SCSI_Out_DBx__5__DM0 CYREG_PRT4_DM0\r
2074#define SCSI_Out_DBx__5__DM1 CYREG_PRT4_DM1\r
2075#define SCSI_Out_DBx__5__DM2 CYREG_PRT4_DM2\r
2076#define SCSI_Out_DBx__5__DR CYREG_PRT4_DR\r
2077#define SCSI_Out_DBx__5__INP_DIS CYREG_PRT4_INP_DIS\r
2078#define SCSI_Out_DBx__5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
2079#define SCSI_Out_DBx__5__LCD_EN CYREG_PRT4_LCD_EN\r
2080#define SCSI_Out_DBx__5__MASK 0x40u\r
2081#define SCSI_Out_DBx__5__PC CYREG_PRT4_PC6\r
2082#define SCSI_Out_DBx__5__PORT 4u\r
2083#define SCSI_Out_DBx__5__PRT CYREG_PRT4_PRT\r
2084#define SCSI_Out_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
2085#define SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
2086#define SCSI_Out_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
2087#define SCSI_Out_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
2088#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
2089#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
2090#define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
2091#define SCSI_Out_DBx__5__PS CYREG_PRT4_PS\r
2092#define SCSI_Out_DBx__5__SHIFT 6\r
2093#define SCSI_Out_DBx__5__SLW CYREG_PRT4_SLW\r
2094#define SCSI_Out_DBx__6__AG CYREG_PRT4_AG\r
2095#define SCSI_Out_DBx__6__AMUX CYREG_PRT4_AMUX\r
2096#define SCSI_Out_DBx__6__BIE CYREG_PRT4_BIE\r
2097#define SCSI_Out_DBx__6__BIT_MASK CYREG_PRT4_BIT_MASK\r
2098#define SCSI_Out_DBx__6__BYP CYREG_PRT4_BYP\r
2099#define SCSI_Out_DBx__6__CTL CYREG_PRT4_CTL\r
2100#define SCSI_Out_DBx__6__DM0 CYREG_PRT4_DM0\r
2101#define SCSI_Out_DBx__6__DM1 CYREG_PRT4_DM1\r
2102#define SCSI_Out_DBx__6__DM2 CYREG_PRT4_DM2\r
2103#define SCSI_Out_DBx__6__DR CYREG_PRT4_DR\r
2104#define SCSI_Out_DBx__6__INP_DIS CYREG_PRT4_INP_DIS\r
2105#define SCSI_Out_DBx__6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
2106#define SCSI_Out_DBx__6__LCD_EN CYREG_PRT4_LCD_EN\r
2107#define SCSI_Out_DBx__6__MASK 0x20u\r
2108#define SCSI_Out_DBx__6__PC CYREG_PRT4_PC5\r
2109#define SCSI_Out_DBx__6__PORT 4u\r
2110#define SCSI_Out_DBx__6__PRT CYREG_PRT4_PRT\r
2111#define SCSI_Out_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
2112#define SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
2113#define SCSI_Out_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
2114#define SCSI_Out_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
2115#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
2116#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
2117#define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
2118#define SCSI_Out_DBx__6__PS CYREG_PRT4_PS\r
2119#define SCSI_Out_DBx__6__SHIFT 5\r
2120#define SCSI_Out_DBx__6__SLW CYREG_PRT4_SLW\r
2121#define SCSI_Out_DBx__7__AG CYREG_PRT4_AG\r
2122#define SCSI_Out_DBx__7__AMUX CYREG_PRT4_AMUX\r
2123#define SCSI_Out_DBx__7__BIE CYREG_PRT4_BIE\r
2124#define SCSI_Out_DBx__7__BIT_MASK CYREG_PRT4_BIT_MASK\r
2125#define SCSI_Out_DBx__7__BYP CYREG_PRT4_BYP\r
2126#define SCSI_Out_DBx__7__CTL CYREG_PRT4_CTL\r
2127#define SCSI_Out_DBx__7__DM0 CYREG_PRT4_DM0\r
2128#define SCSI_Out_DBx__7__DM1 CYREG_PRT4_DM1\r
2129#define SCSI_Out_DBx__7__DM2 CYREG_PRT4_DM2\r
2130#define SCSI_Out_DBx__7__DR CYREG_PRT4_DR\r
2131#define SCSI_Out_DBx__7__INP_DIS CYREG_PRT4_INP_DIS\r
2132#define SCSI_Out_DBx__7__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
2133#define SCSI_Out_DBx__7__LCD_EN CYREG_PRT4_LCD_EN\r
2134#define SCSI_Out_DBx__7__MASK 0x10u\r
2135#define SCSI_Out_DBx__7__PC CYREG_PRT4_PC4\r
2136#define SCSI_Out_DBx__7__PORT 4u\r
2137#define SCSI_Out_DBx__7__PRT CYREG_PRT4_PRT\r
2138#define SCSI_Out_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
2139#define SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
2140#define SCSI_Out_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
2141#define SCSI_Out_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
2142#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
2143#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
2144#define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
2145#define SCSI_Out_DBx__7__PS CYREG_PRT4_PS\r
2146#define SCSI_Out_DBx__7__SHIFT 4\r
2147#define SCSI_Out_DBx__7__SLW CYREG_PRT4_SLW\r
2148#define SCSI_Out_DBx__DB0__AG CYREG_PRT6_AG\r
2149#define SCSI_Out_DBx__DB0__AMUX CYREG_PRT6_AMUX\r
2150#define SCSI_Out_DBx__DB0__BIE CYREG_PRT6_BIE\r
2151#define SCSI_Out_DBx__DB0__BIT_MASK CYREG_PRT6_BIT_MASK\r
2152#define SCSI_Out_DBx__DB0__BYP CYREG_PRT6_BYP\r
2153#define SCSI_Out_DBx__DB0__CTL CYREG_PRT6_CTL\r
2154#define SCSI_Out_DBx__DB0__DM0 CYREG_PRT6_DM0\r
2155#define SCSI_Out_DBx__DB0__DM1 CYREG_PRT6_DM1\r
2156#define SCSI_Out_DBx__DB0__DM2 CYREG_PRT6_DM2\r
2157#define SCSI_Out_DBx__DB0__DR CYREG_PRT6_DR\r
2158#define SCSI_Out_DBx__DB0__INP_DIS CYREG_PRT6_INP_DIS\r
2159#define SCSI_Out_DBx__DB0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
2160#define SCSI_Out_DBx__DB0__LCD_EN CYREG_PRT6_LCD_EN\r
2161#define SCSI_Out_DBx__DB0__MASK 0x08u\r
2162#define SCSI_Out_DBx__DB0__PC CYREG_PRT6_PC3\r
2163#define SCSI_Out_DBx__DB0__PORT 6u\r
2164#define SCSI_Out_DBx__DB0__PRT CYREG_PRT6_PRT\r
2165#define SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
2166#define SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
2167#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
2168#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
2169#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
2170#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
2171#define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
2172#define SCSI_Out_DBx__DB0__PS CYREG_PRT6_PS\r
2173#define SCSI_Out_DBx__DB0__SHIFT 3\r
2174#define SCSI_Out_DBx__DB0__SLW CYREG_PRT6_SLW\r
2175#define SCSI_Out_DBx__DB1__AG CYREG_PRT6_AG\r
2176#define SCSI_Out_DBx__DB1__AMUX CYREG_PRT6_AMUX\r
2177#define SCSI_Out_DBx__DB1__BIE CYREG_PRT6_BIE\r
2178#define SCSI_Out_DBx__DB1__BIT_MASK CYREG_PRT6_BIT_MASK\r
2179#define SCSI_Out_DBx__DB1__BYP CYREG_PRT6_BYP\r
2180#define SCSI_Out_DBx__DB1__CTL CYREG_PRT6_CTL\r
2181#define SCSI_Out_DBx__DB1__DM0 CYREG_PRT6_DM0\r
2182#define SCSI_Out_DBx__DB1__DM1 CYREG_PRT6_DM1\r
2183#define SCSI_Out_DBx__DB1__DM2 CYREG_PRT6_DM2\r
2184#define SCSI_Out_DBx__DB1__DR CYREG_PRT6_DR\r
2185#define SCSI_Out_DBx__DB1__INP_DIS CYREG_PRT6_INP_DIS\r
2186#define SCSI_Out_DBx__DB1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
2187#define SCSI_Out_DBx__DB1__LCD_EN CYREG_PRT6_LCD_EN\r
2188#define SCSI_Out_DBx__DB1__MASK 0x04u\r
2189#define SCSI_Out_DBx__DB1__PC CYREG_PRT6_PC2\r
2190#define SCSI_Out_DBx__DB1__PORT 6u\r
2191#define SCSI_Out_DBx__DB1__PRT CYREG_PRT6_PRT\r
2192#define SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
2193#define SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
2194#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
2195#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
2196#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
2197#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
2198#define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
2199#define SCSI_Out_DBx__DB1__PS CYREG_PRT6_PS\r
2200#define SCSI_Out_DBx__DB1__SHIFT 2\r
2201#define SCSI_Out_DBx__DB1__SLW CYREG_PRT6_SLW\r
2202#define SCSI_Out_DBx__DB2__AG CYREG_PRT6_AG\r
2203#define SCSI_Out_DBx__DB2__AMUX CYREG_PRT6_AMUX\r
2204#define SCSI_Out_DBx__DB2__BIE CYREG_PRT6_BIE\r
2205#define SCSI_Out_DBx__DB2__BIT_MASK CYREG_PRT6_BIT_MASK\r
2206#define SCSI_Out_DBx__DB2__BYP CYREG_PRT6_BYP\r
2207#define SCSI_Out_DBx__DB2__CTL CYREG_PRT6_CTL\r
2208#define SCSI_Out_DBx__DB2__DM0 CYREG_PRT6_DM0\r
2209#define SCSI_Out_DBx__DB2__DM1 CYREG_PRT6_DM1\r
2210#define SCSI_Out_DBx__DB2__DM2 CYREG_PRT6_DM2\r
2211#define SCSI_Out_DBx__DB2__DR CYREG_PRT6_DR\r
2212#define SCSI_Out_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS\r
2213#define SCSI_Out_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
2214#define SCSI_Out_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN\r
2215#define SCSI_Out_DBx__DB2__MASK 0x02u\r
2216#define SCSI_Out_DBx__DB2__PC CYREG_PRT6_PC1\r
2217#define SCSI_Out_DBx__DB2__PORT 6u\r
2218#define SCSI_Out_DBx__DB2__PRT CYREG_PRT6_PRT\r
2219#define SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
2220#define SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
2221#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
2222#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
2223#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
2224#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
2225#define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
2226#define SCSI_Out_DBx__DB2__PS CYREG_PRT6_PS\r
2227#define SCSI_Out_DBx__DB2__SHIFT 1\r
2228#define SCSI_Out_DBx__DB2__SLW CYREG_PRT6_SLW\r
2229#define SCSI_Out_DBx__DB3__AG CYREG_PRT6_AG\r
2230#define SCSI_Out_DBx__DB3__AMUX CYREG_PRT6_AMUX\r
2231#define SCSI_Out_DBx__DB3__BIE CYREG_PRT6_BIE\r
2232#define SCSI_Out_DBx__DB3__BIT_MASK CYREG_PRT6_BIT_MASK\r
2233#define SCSI_Out_DBx__DB3__BYP CYREG_PRT6_BYP\r
2234#define SCSI_Out_DBx__DB3__CTL CYREG_PRT6_CTL\r
2235#define SCSI_Out_DBx__DB3__DM0 CYREG_PRT6_DM0\r
2236#define SCSI_Out_DBx__DB3__DM1 CYREG_PRT6_DM1\r
2237#define SCSI_Out_DBx__DB3__DM2 CYREG_PRT6_DM2\r
2238#define SCSI_Out_DBx__DB3__DR CYREG_PRT6_DR\r
2239#define SCSI_Out_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS\r
2240#define SCSI_Out_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
2241#define SCSI_Out_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN\r
2242#define SCSI_Out_DBx__DB3__MASK 0x01u\r
2243#define SCSI_Out_DBx__DB3__PC CYREG_PRT6_PC0\r
2244#define SCSI_Out_DBx__DB3__PORT 6u\r
2245#define SCSI_Out_DBx__DB3__PRT CYREG_PRT6_PRT\r
2246#define SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
2247#define SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
2248#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
2249#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
2250#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
2251#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
2252#define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
2253#define SCSI_Out_DBx__DB3__PS CYREG_PRT6_PS\r
2254#define SCSI_Out_DBx__DB3__SHIFT 0\r
2255#define SCSI_Out_DBx__DB3__SLW CYREG_PRT6_SLW\r
2256#define SCSI_Out_DBx__DB4__AG CYREG_PRT4_AG\r
2257#define SCSI_Out_DBx__DB4__AMUX CYREG_PRT4_AMUX\r
2258#define SCSI_Out_DBx__DB4__BIE CYREG_PRT4_BIE\r
2259#define SCSI_Out_DBx__DB4__BIT_MASK CYREG_PRT4_BIT_MASK\r
2260#define SCSI_Out_DBx__DB4__BYP CYREG_PRT4_BYP\r
2261#define SCSI_Out_DBx__DB4__CTL CYREG_PRT4_CTL\r
2262#define SCSI_Out_DBx__DB4__DM0 CYREG_PRT4_DM0\r
2263#define SCSI_Out_DBx__DB4__DM1 CYREG_PRT4_DM1\r
2264#define SCSI_Out_DBx__DB4__DM2 CYREG_PRT4_DM2\r
2265#define SCSI_Out_DBx__DB4__DR CYREG_PRT4_DR\r
2266#define SCSI_Out_DBx__DB4__INP_DIS CYREG_PRT4_INP_DIS\r
2267#define SCSI_Out_DBx__DB4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
2268#define SCSI_Out_DBx__DB4__LCD_EN CYREG_PRT4_LCD_EN\r
2269#define SCSI_Out_DBx__DB4__MASK 0x80u\r
2270#define SCSI_Out_DBx__DB4__PC CYREG_PRT4_PC7\r
2271#define SCSI_Out_DBx__DB4__PORT 4u\r
2272#define SCSI_Out_DBx__DB4__PRT CYREG_PRT4_PRT\r
2273#define SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
2274#define SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
2275#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
2276#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
2277#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
2278#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
2279#define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
2280#define SCSI_Out_DBx__DB4__PS CYREG_PRT4_PS\r
2281#define SCSI_Out_DBx__DB4__SHIFT 7\r
2282#define SCSI_Out_DBx__DB4__SLW CYREG_PRT4_SLW\r
2283#define SCSI_Out_DBx__DB5__AG CYREG_PRT4_AG\r
2284#define SCSI_Out_DBx__DB5__AMUX CYREG_PRT4_AMUX\r
2285#define SCSI_Out_DBx__DB5__BIE CYREG_PRT4_BIE\r
2286#define SCSI_Out_DBx__DB5__BIT_MASK CYREG_PRT4_BIT_MASK\r
2287#define SCSI_Out_DBx__DB5__BYP CYREG_PRT4_BYP\r
2288#define SCSI_Out_DBx__DB5__CTL CYREG_PRT4_CTL\r
2289#define SCSI_Out_DBx__DB5__DM0 CYREG_PRT4_DM0\r
2290#define SCSI_Out_DBx__DB5__DM1 CYREG_PRT4_DM1\r
2291#define SCSI_Out_DBx__DB5__DM2 CYREG_PRT4_DM2\r
2292#define SCSI_Out_DBx__DB5__DR CYREG_PRT4_DR\r
2293#define SCSI_Out_DBx__DB5__INP_DIS CYREG_PRT4_INP_DIS\r
2294#define SCSI_Out_DBx__DB5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
2295#define SCSI_Out_DBx__DB5__LCD_EN CYREG_PRT4_LCD_EN\r
2296#define SCSI_Out_DBx__DB5__MASK 0x40u\r
2297#define SCSI_Out_DBx__DB5__PC CYREG_PRT4_PC6\r
2298#define SCSI_Out_DBx__DB5__PORT 4u\r
2299#define SCSI_Out_DBx__DB5__PRT CYREG_PRT4_PRT\r
2300#define SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
2301#define SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
2302#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
2303#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
2304#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
2305#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
2306#define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
2307#define SCSI_Out_DBx__DB5__PS CYREG_PRT4_PS\r
2308#define SCSI_Out_DBx__DB5__SHIFT 6\r
2309#define SCSI_Out_DBx__DB5__SLW CYREG_PRT4_SLW\r
2310#define SCSI_Out_DBx__DB6__AG CYREG_PRT4_AG\r
2311#define SCSI_Out_DBx__DB6__AMUX CYREG_PRT4_AMUX\r
2312#define SCSI_Out_DBx__DB6__BIE CYREG_PRT4_BIE\r
2313#define SCSI_Out_DBx__DB6__BIT_MASK CYREG_PRT4_BIT_MASK\r
2314#define SCSI_Out_DBx__DB6__BYP CYREG_PRT4_BYP\r
2315#define SCSI_Out_DBx__DB6__CTL CYREG_PRT4_CTL\r
2316#define SCSI_Out_DBx__DB6__DM0 CYREG_PRT4_DM0\r
2317#define SCSI_Out_DBx__DB6__DM1 CYREG_PRT4_DM1\r
2318#define SCSI_Out_DBx__DB6__DM2 CYREG_PRT4_DM2\r
2319#define SCSI_Out_DBx__DB6__DR CYREG_PRT4_DR\r
2320#define SCSI_Out_DBx__DB6__INP_DIS CYREG_PRT4_INP_DIS\r
2321#define SCSI_Out_DBx__DB6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
2322#define SCSI_Out_DBx__DB6__LCD_EN CYREG_PRT4_LCD_EN\r
2323#define SCSI_Out_DBx__DB6__MASK 0x20u\r
2324#define SCSI_Out_DBx__DB6__PC CYREG_PRT4_PC5\r
2325#define SCSI_Out_DBx__DB6__PORT 4u\r
2326#define SCSI_Out_DBx__DB6__PRT CYREG_PRT4_PRT\r
2327#define SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
2328#define SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
2329#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
2330#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
2331#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
2332#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
2333#define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
2334#define SCSI_Out_DBx__DB6__PS CYREG_PRT4_PS\r
2335#define SCSI_Out_DBx__DB6__SHIFT 5\r
2336#define SCSI_Out_DBx__DB6__SLW CYREG_PRT4_SLW\r
2337#define SCSI_Out_DBx__DB7__AG CYREG_PRT4_AG\r
2338#define SCSI_Out_DBx__DB7__AMUX CYREG_PRT4_AMUX\r
2339#define SCSI_Out_DBx__DB7__BIE CYREG_PRT4_BIE\r
2340#define SCSI_Out_DBx__DB7__BIT_MASK CYREG_PRT4_BIT_MASK\r
2341#define SCSI_Out_DBx__DB7__BYP CYREG_PRT4_BYP\r
2342#define SCSI_Out_DBx__DB7__CTL CYREG_PRT4_CTL\r
2343#define SCSI_Out_DBx__DB7__DM0 CYREG_PRT4_DM0\r
2344#define SCSI_Out_DBx__DB7__DM1 CYREG_PRT4_DM1\r
2345#define SCSI_Out_DBx__DB7__DM2 CYREG_PRT4_DM2\r
2346#define SCSI_Out_DBx__DB7__DR CYREG_PRT4_DR\r
2347#define SCSI_Out_DBx__DB7__INP_DIS CYREG_PRT4_INP_DIS\r
2348#define SCSI_Out_DBx__DB7__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
2349#define SCSI_Out_DBx__DB7__LCD_EN CYREG_PRT4_LCD_EN\r
2350#define SCSI_Out_DBx__DB7__MASK 0x10u\r
2351#define SCSI_Out_DBx__DB7__PC CYREG_PRT4_PC4\r
2352#define SCSI_Out_DBx__DB7__PORT 4u\r
2353#define SCSI_Out_DBx__DB7__PRT CYREG_PRT4_PRT\r
2354#define SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
2355#define SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
2356#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
2357#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
2358#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
2359#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
2360#define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
2361#define SCSI_Out_DBx__DB7__PS CYREG_PRT4_PS\r
2362#define SCSI_Out_DBx__DB7__SHIFT 4\r
2363#define SCSI_Out_DBx__DB7__SLW CYREG_PRT4_SLW\r
2364\r
2365/* SD_RX_DMA */\r
2366#define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
2367#define SD_RX_DMA__DRQ_NUMBER 2u\r
2368#define SD_RX_DMA__NUMBEROF_TDS 0u\r
95b51978 2369#define SD_RX_DMA__PRIORITY 0u\r
70257ca8
MM
2370#define SD_RX_DMA__TERMIN_EN 0u\r
2371#define SD_RX_DMA__TERMIN_SEL 0u\r
2372#define SD_RX_DMA__TERMOUT0_EN 1u\r
2373#define SD_RX_DMA__TERMOUT0_SEL 2u\r
2374#define SD_RX_DMA__TERMOUT1_EN 0u\r
2375#define SD_RX_DMA__TERMOUT1_SEL 0u\r
2376\r
2377/* SD_RX_DMA_COMPLETE */\r
2378#define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
2379#define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
2380#define SD_RX_DMA_COMPLETE__INTC_MASK 0x10u\r
2381#define SD_RX_DMA_COMPLETE__INTC_NUMBER 4u\r
2382#define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
2383#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4\r
2384#define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
2385#define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
2386\r
2387/* SD_TX_DMA */\r
2388#define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
2389#define SD_TX_DMA__DRQ_NUMBER 3u\r
2390#define SD_TX_DMA__NUMBEROF_TDS 0u\r
95b51978 2391#define SD_TX_DMA__PRIORITY 1u\r
70257ca8
MM
2392#define SD_TX_DMA__TERMIN_EN 0u\r
2393#define SD_TX_DMA__TERMIN_SEL 0u\r
2394#define SD_TX_DMA__TERMOUT0_EN 1u\r
2395#define SD_TX_DMA__TERMOUT0_SEL 3u\r
2396#define SD_TX_DMA__TERMOUT1_EN 0u\r
2397#define SD_TX_DMA__TERMOUT1_SEL 0u\r
2398\r
2399/* SD_TX_DMA_COMPLETE */\r
2400#define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
2401#define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
2402#define SD_TX_DMA_COMPLETE__INTC_MASK 0x20u\r
2403#define SD_TX_DMA_COMPLETE__INTC_NUMBER 5u\r
2404#define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
2405#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5\r
2406#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
2407#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
2408\r
2409/* SCSI_Noise */\r
2410#define SCSI_Noise__0__AG CYREG_PRT12_AG\r
2411#define SCSI_Noise__0__BIE CYREG_PRT12_BIE\r
2412#define SCSI_Noise__0__BIT_MASK CYREG_PRT12_BIT_MASK\r
2413#define SCSI_Noise__0__BYP CYREG_PRT12_BYP\r
2414#define SCSI_Noise__0__DM0 CYREG_PRT12_DM0\r
2415#define SCSI_Noise__0__DM1 CYREG_PRT12_DM1\r
2416#define SCSI_Noise__0__DM2 CYREG_PRT12_DM2\r
2417#define SCSI_Noise__0__DR CYREG_PRT12_DR\r
2418#define SCSI_Noise__0__INP_DIS CYREG_PRT12_INP_DIS\r
2419#define SCSI_Noise__0__MASK 0x20u\r
2420#define SCSI_Noise__0__PC CYREG_PRT12_PC5\r
2421#define SCSI_Noise__0__PORT 12u\r
2422#define SCSI_Noise__0__PRT CYREG_PRT12_PRT\r
2423#define SCSI_Noise__0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
2424#define SCSI_Noise__0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
2425#define SCSI_Noise__0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
2426#define SCSI_Noise__0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
2427#define SCSI_Noise__0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
2428#define SCSI_Noise__0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
2429#define SCSI_Noise__0__PS CYREG_PRT12_PS\r
2430#define SCSI_Noise__0__SHIFT 5\r
2431#define SCSI_Noise__0__SIO_CFG CYREG_PRT12_SIO_CFG\r
2432#define SCSI_Noise__0__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
2433#define SCSI_Noise__0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
2434#define SCSI_Noise__0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
2435#define SCSI_Noise__0__SLW CYREG_PRT12_SLW\r
2436#define SCSI_Noise__1__AG CYREG_PRT6_AG\r
2437#define SCSI_Noise__1__AMUX CYREG_PRT6_AMUX\r
2438#define SCSI_Noise__1__BIE CYREG_PRT6_BIE\r
2439#define SCSI_Noise__1__BIT_MASK CYREG_PRT6_BIT_MASK\r
2440#define SCSI_Noise__1__BYP CYREG_PRT6_BYP\r
2441#define SCSI_Noise__1__CTL CYREG_PRT6_CTL\r
2442#define SCSI_Noise__1__DM0 CYREG_PRT6_DM0\r
2443#define SCSI_Noise__1__DM1 CYREG_PRT6_DM1\r
2444#define SCSI_Noise__1__DM2 CYREG_PRT6_DM2\r
2445#define SCSI_Noise__1__DR CYREG_PRT6_DR\r
2446#define SCSI_Noise__1__INP_DIS CYREG_PRT6_INP_DIS\r
2447#define SCSI_Noise__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
2448#define SCSI_Noise__1__LCD_EN CYREG_PRT6_LCD_EN\r
2449#define SCSI_Noise__1__MASK 0x10u\r
2450#define SCSI_Noise__1__PC CYREG_PRT6_PC4\r
2451#define SCSI_Noise__1__PORT 6u\r
2452#define SCSI_Noise__1__PRT CYREG_PRT6_PRT\r
2453#define SCSI_Noise__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
2454#define SCSI_Noise__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
2455#define SCSI_Noise__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
2456#define SCSI_Noise__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
2457#define SCSI_Noise__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
2458#define SCSI_Noise__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
2459#define SCSI_Noise__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
2460#define SCSI_Noise__1__PS CYREG_PRT6_PS\r
2461#define SCSI_Noise__1__SHIFT 4\r
2462#define SCSI_Noise__1__SLW CYREG_PRT6_SLW\r
2463#define SCSI_Noise__2__AG CYREG_PRT5_AG\r
2464#define SCSI_Noise__2__AMUX CYREG_PRT5_AMUX\r
2465#define SCSI_Noise__2__BIE CYREG_PRT5_BIE\r
2466#define SCSI_Noise__2__BIT_MASK CYREG_PRT5_BIT_MASK\r
2467#define SCSI_Noise__2__BYP CYREG_PRT5_BYP\r
2468#define SCSI_Noise__2__CTL CYREG_PRT5_CTL\r
2469#define SCSI_Noise__2__DM0 CYREG_PRT5_DM0\r
2470#define SCSI_Noise__2__DM1 CYREG_PRT5_DM1\r
2471#define SCSI_Noise__2__DM2 CYREG_PRT5_DM2\r
2472#define SCSI_Noise__2__DR CYREG_PRT5_DR\r
2473#define SCSI_Noise__2__INP_DIS CYREG_PRT5_INP_DIS\r
2474#define SCSI_Noise__2__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
2475#define SCSI_Noise__2__LCD_EN CYREG_PRT5_LCD_EN\r
2476#define SCSI_Noise__2__MASK 0x01u\r
2477#define SCSI_Noise__2__PC CYREG_PRT5_PC0\r
2478#define SCSI_Noise__2__PORT 5u\r
2479#define SCSI_Noise__2__PRT CYREG_PRT5_PRT\r
2480#define SCSI_Noise__2__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
2481#define SCSI_Noise__2__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
2482#define SCSI_Noise__2__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
2483#define SCSI_Noise__2__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
2484#define SCSI_Noise__2__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
2485#define SCSI_Noise__2__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
2486#define SCSI_Noise__2__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
2487#define SCSI_Noise__2__PS CYREG_PRT5_PS\r
2488#define SCSI_Noise__2__SHIFT 0\r
2489#define SCSI_Noise__2__SLW CYREG_PRT5_SLW\r
2490#define SCSI_Noise__3__AG CYREG_PRT6_AG\r
2491#define SCSI_Noise__3__AMUX CYREG_PRT6_AMUX\r
2492#define SCSI_Noise__3__BIE CYREG_PRT6_BIE\r
2493#define SCSI_Noise__3__BIT_MASK CYREG_PRT6_BIT_MASK\r
2494#define SCSI_Noise__3__BYP CYREG_PRT6_BYP\r
2495#define SCSI_Noise__3__CTL CYREG_PRT6_CTL\r
2496#define SCSI_Noise__3__DM0 CYREG_PRT6_DM0\r
2497#define SCSI_Noise__3__DM1 CYREG_PRT6_DM1\r
2498#define SCSI_Noise__3__DM2 CYREG_PRT6_DM2\r
2499#define SCSI_Noise__3__DR CYREG_PRT6_DR\r
2500#define SCSI_Noise__3__INP_DIS CYREG_PRT6_INP_DIS\r
2501#define SCSI_Noise__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
2502#define SCSI_Noise__3__LCD_EN CYREG_PRT6_LCD_EN\r
2503#define SCSI_Noise__3__MASK 0x40u\r
2504#define SCSI_Noise__3__PC CYREG_PRT6_PC6\r
2505#define SCSI_Noise__3__PORT 6u\r
2506#define SCSI_Noise__3__PRT CYREG_PRT6_PRT\r
2507#define SCSI_Noise__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
2508#define SCSI_Noise__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
2509#define SCSI_Noise__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
2510#define SCSI_Noise__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
2511#define SCSI_Noise__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
2512#define SCSI_Noise__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
2513#define SCSI_Noise__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
2514#define SCSI_Noise__3__PS CYREG_PRT6_PS\r
2515#define SCSI_Noise__3__SHIFT 6\r
2516#define SCSI_Noise__3__SLW CYREG_PRT6_SLW\r
2517#define SCSI_Noise__4__AG CYREG_PRT6_AG\r
2518#define SCSI_Noise__4__AMUX CYREG_PRT6_AMUX\r
2519#define SCSI_Noise__4__BIE CYREG_PRT6_BIE\r
2520#define SCSI_Noise__4__BIT_MASK CYREG_PRT6_BIT_MASK\r
2521#define SCSI_Noise__4__BYP CYREG_PRT6_BYP\r
2522#define SCSI_Noise__4__CTL CYREG_PRT6_CTL\r
2523#define SCSI_Noise__4__DM0 CYREG_PRT6_DM0\r
2524#define SCSI_Noise__4__DM1 CYREG_PRT6_DM1\r
2525#define SCSI_Noise__4__DM2 CYREG_PRT6_DM2\r
2526#define SCSI_Noise__4__DR CYREG_PRT6_DR\r
2527#define SCSI_Noise__4__INP_DIS CYREG_PRT6_INP_DIS\r
2528#define SCSI_Noise__4__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
2529#define SCSI_Noise__4__LCD_EN CYREG_PRT6_LCD_EN\r
2530#define SCSI_Noise__4__MASK 0x20u\r
2531#define SCSI_Noise__4__PC CYREG_PRT6_PC5\r
2532#define SCSI_Noise__4__PORT 6u\r
2533#define SCSI_Noise__4__PRT CYREG_PRT6_PRT\r
2534#define SCSI_Noise__4__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
2535#define SCSI_Noise__4__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
2536#define SCSI_Noise__4__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
2537#define SCSI_Noise__4__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
2538#define SCSI_Noise__4__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
2539#define SCSI_Noise__4__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
2540#define SCSI_Noise__4__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
2541#define SCSI_Noise__4__PS CYREG_PRT6_PS\r
2542#define SCSI_Noise__4__SHIFT 5\r
2543#define SCSI_Noise__4__SLW CYREG_PRT6_SLW\r
2544#define SCSI_Noise__ACK__AG CYREG_PRT6_AG\r
2545#define SCSI_Noise__ACK__AMUX CYREG_PRT6_AMUX\r
2546#define SCSI_Noise__ACK__BIE CYREG_PRT6_BIE\r
2547#define SCSI_Noise__ACK__BIT_MASK CYREG_PRT6_BIT_MASK\r
2548#define SCSI_Noise__ACK__BYP CYREG_PRT6_BYP\r
2549#define SCSI_Noise__ACK__CTL CYREG_PRT6_CTL\r
2550#define SCSI_Noise__ACK__DM0 CYREG_PRT6_DM0\r
2551#define SCSI_Noise__ACK__DM1 CYREG_PRT6_DM1\r
2552#define SCSI_Noise__ACK__DM2 CYREG_PRT6_DM2\r
2553#define SCSI_Noise__ACK__DR CYREG_PRT6_DR\r
2554#define SCSI_Noise__ACK__INP_DIS CYREG_PRT6_INP_DIS\r
2555#define SCSI_Noise__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
2556#define SCSI_Noise__ACK__LCD_EN CYREG_PRT6_LCD_EN\r
2557#define SCSI_Noise__ACK__MASK 0x20u\r
2558#define SCSI_Noise__ACK__PC CYREG_PRT6_PC5\r
2559#define SCSI_Noise__ACK__PORT 6u\r
2560#define SCSI_Noise__ACK__PRT CYREG_PRT6_PRT\r
2561#define SCSI_Noise__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
2562#define SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
2563#define SCSI_Noise__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
2564#define SCSI_Noise__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
2565#define SCSI_Noise__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
2566#define SCSI_Noise__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
2567#define SCSI_Noise__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
2568#define SCSI_Noise__ACK__PS CYREG_PRT6_PS\r
2569#define SCSI_Noise__ACK__SHIFT 5\r
2570#define SCSI_Noise__ACK__SLW CYREG_PRT6_SLW\r
2571#define SCSI_Noise__ATN__AG CYREG_PRT12_AG\r
2572#define SCSI_Noise__ATN__BIE CYREG_PRT12_BIE\r
2573#define SCSI_Noise__ATN__BIT_MASK CYREG_PRT12_BIT_MASK\r
2574#define SCSI_Noise__ATN__BYP CYREG_PRT12_BYP\r
2575#define SCSI_Noise__ATN__DM0 CYREG_PRT12_DM0\r
2576#define SCSI_Noise__ATN__DM1 CYREG_PRT12_DM1\r
2577#define SCSI_Noise__ATN__DM2 CYREG_PRT12_DM2\r
2578#define SCSI_Noise__ATN__DR CYREG_PRT12_DR\r
2579#define SCSI_Noise__ATN__INP_DIS CYREG_PRT12_INP_DIS\r
2580#define SCSI_Noise__ATN__MASK 0x20u\r
2581#define SCSI_Noise__ATN__PC CYREG_PRT12_PC5\r
2582#define SCSI_Noise__ATN__PORT 12u\r
2583#define SCSI_Noise__ATN__PRT CYREG_PRT12_PRT\r
2584#define SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
2585#define SCSI_Noise__ATN__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
2586#define SCSI_Noise__ATN__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
2587#define SCSI_Noise__ATN__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
2588#define SCSI_Noise__ATN__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
2589#define SCSI_Noise__ATN__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
2590#define SCSI_Noise__ATN__PS CYREG_PRT12_PS\r
2591#define SCSI_Noise__ATN__SHIFT 5\r
2592#define SCSI_Noise__ATN__SIO_CFG CYREG_PRT12_SIO_CFG\r
2593#define SCSI_Noise__ATN__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
2594#define SCSI_Noise__ATN__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
2595#define SCSI_Noise__ATN__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
2596#define SCSI_Noise__ATN__SLW CYREG_PRT12_SLW\r
2597#define SCSI_Noise__BSY__AG CYREG_PRT6_AG\r
2598#define SCSI_Noise__BSY__AMUX CYREG_PRT6_AMUX\r
2599#define SCSI_Noise__BSY__BIE CYREG_PRT6_BIE\r
2600#define SCSI_Noise__BSY__BIT_MASK CYREG_PRT6_BIT_MASK\r
2601#define SCSI_Noise__BSY__BYP CYREG_PRT6_BYP\r
2602#define SCSI_Noise__BSY__CTL CYREG_PRT6_CTL\r
2603#define SCSI_Noise__BSY__DM0 CYREG_PRT6_DM0\r
2604#define SCSI_Noise__BSY__DM1 CYREG_PRT6_DM1\r
2605#define SCSI_Noise__BSY__DM2 CYREG_PRT6_DM2\r
2606#define SCSI_Noise__BSY__DR CYREG_PRT6_DR\r
2607#define SCSI_Noise__BSY__INP_DIS CYREG_PRT6_INP_DIS\r
2608#define SCSI_Noise__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
2609#define SCSI_Noise__BSY__LCD_EN CYREG_PRT6_LCD_EN\r
2610#define SCSI_Noise__BSY__MASK 0x10u\r
2611#define SCSI_Noise__BSY__PC CYREG_PRT6_PC4\r
2612#define SCSI_Noise__BSY__PORT 6u\r
2613#define SCSI_Noise__BSY__PRT CYREG_PRT6_PRT\r
2614#define SCSI_Noise__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
2615#define SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
2616#define SCSI_Noise__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
2617#define SCSI_Noise__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
2618#define SCSI_Noise__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
2619#define SCSI_Noise__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
2620#define SCSI_Noise__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
2621#define SCSI_Noise__BSY__PS CYREG_PRT6_PS\r
2622#define SCSI_Noise__BSY__SHIFT 4\r
2623#define SCSI_Noise__BSY__SLW CYREG_PRT6_SLW\r
2624#define SCSI_Noise__RST__AG CYREG_PRT6_AG\r
2625#define SCSI_Noise__RST__AMUX CYREG_PRT6_AMUX\r
2626#define SCSI_Noise__RST__BIE CYREG_PRT6_BIE\r
2627#define SCSI_Noise__RST__BIT_MASK CYREG_PRT6_BIT_MASK\r
2628#define SCSI_Noise__RST__BYP CYREG_PRT6_BYP\r
2629#define SCSI_Noise__RST__CTL CYREG_PRT6_CTL\r
2630#define SCSI_Noise__RST__DM0 CYREG_PRT6_DM0\r
2631#define SCSI_Noise__RST__DM1 CYREG_PRT6_DM1\r
2632#define SCSI_Noise__RST__DM2 CYREG_PRT6_DM2\r
2633#define SCSI_Noise__RST__DR CYREG_PRT6_DR\r
2634#define SCSI_Noise__RST__INP_DIS CYREG_PRT6_INP_DIS\r
2635#define SCSI_Noise__RST__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
2636#define SCSI_Noise__RST__LCD_EN CYREG_PRT6_LCD_EN\r
2637#define SCSI_Noise__RST__MASK 0x40u\r
2638#define SCSI_Noise__RST__PC CYREG_PRT6_PC6\r
2639#define SCSI_Noise__RST__PORT 6u\r
2640#define SCSI_Noise__RST__PRT CYREG_PRT6_PRT\r
2641#define SCSI_Noise__RST__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
2642#define SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
2643#define SCSI_Noise__RST__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
2644#define SCSI_Noise__RST__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
2645#define SCSI_Noise__RST__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
2646#define SCSI_Noise__RST__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
2647#define SCSI_Noise__RST__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
2648#define SCSI_Noise__RST__PS CYREG_PRT6_PS\r
2649#define SCSI_Noise__RST__SHIFT 6\r
2650#define SCSI_Noise__RST__SLW CYREG_PRT6_SLW\r
2651#define SCSI_Noise__SEL__AG CYREG_PRT5_AG\r
2652#define SCSI_Noise__SEL__AMUX CYREG_PRT5_AMUX\r
2653#define SCSI_Noise__SEL__BIE CYREG_PRT5_BIE\r
2654#define SCSI_Noise__SEL__BIT_MASK CYREG_PRT5_BIT_MASK\r
2655#define SCSI_Noise__SEL__BYP CYREG_PRT5_BYP\r
2656#define SCSI_Noise__SEL__CTL CYREG_PRT5_CTL\r
2657#define SCSI_Noise__SEL__DM0 CYREG_PRT5_DM0\r
2658#define SCSI_Noise__SEL__DM1 CYREG_PRT5_DM1\r
2659#define SCSI_Noise__SEL__DM2 CYREG_PRT5_DM2\r
2660#define SCSI_Noise__SEL__DR CYREG_PRT5_DR\r
2661#define SCSI_Noise__SEL__INP_DIS CYREG_PRT5_INP_DIS\r
2662#define SCSI_Noise__SEL__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
2663#define SCSI_Noise__SEL__LCD_EN CYREG_PRT5_LCD_EN\r
2664#define SCSI_Noise__SEL__MASK 0x01u\r
2665#define SCSI_Noise__SEL__PC CYREG_PRT5_PC0\r
2666#define SCSI_Noise__SEL__PORT 5u\r
2667#define SCSI_Noise__SEL__PRT CYREG_PRT5_PRT\r
2668#define SCSI_Noise__SEL__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
2669#define SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
2670#define SCSI_Noise__SEL__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
2671#define SCSI_Noise__SEL__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
2672#define SCSI_Noise__SEL__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
2673#define SCSI_Noise__SEL__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
2674#define SCSI_Noise__SEL__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
2675#define SCSI_Noise__SEL__PS CYREG_PRT5_PS\r
2676#define SCSI_Noise__SEL__SHIFT 0\r
2677#define SCSI_Noise__SEL__SLW CYREG_PRT5_SLW\r
2678\r
2679/* scsiTarget */\r
95b51978
MM
2680#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB00_01_A0\r
2681#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB00_01_A1\r
2682#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB00_01_D0\r
2683#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB00_01_D1\r
2684#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL\r
2685#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB00_01_F0\r
2686#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB00_01_F1\r
2687#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB00_A0_A1\r
2688#define scsiTarget_datapath__A0_REG CYREG_B0_UDB00_A0\r
2689#define scsiTarget_datapath__A1_REG CYREG_B0_UDB00_A1\r
2690#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB00_D0_D1\r
2691#define scsiTarget_datapath__D0_REG CYREG_B0_UDB00_D0\r
2692#define scsiTarget_datapath__D1_REG CYREG_B0_UDB00_D1\r
2693#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB00_ACTL\r
2694#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB00_F0_F1\r
2695#define scsiTarget_datapath__F0_REG CYREG_B0_UDB00_F0\r
2696#define scsiTarget_datapath__F1_REG CYREG_B0_UDB00_F1\r
2697#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL\r
2698#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL\r
2699#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL\r
2700#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB00_01_ST\r
2701#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB00_MSK\r
2702#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL\r
2703#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL\r
2704#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB00_ACTL\r
2705#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB00_ST_CTL\r
2706#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB00_ST_CTL\r
2707#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB00_ST\r
2708#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL\r
2709#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB00_01_CTL\r
2710#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB00_01_CTL\r
2711#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB00_01_CTL\r
2712#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB00_01_CTL\r
2713#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB00_01_MSK\r
2714#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB00_01_MSK\r
2715#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB00_01_MSK\r
2716#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB00_01_MSK\r
2717#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB00_ACTL\r
2718#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB00_CTL\r
2719#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB00_ST_CTL\r
2720#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB00_CTL\r
2721#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB00_ST_CTL\r
2722#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL\r
2723#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL\r
2724#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB00_MSK\r
70257ca8
MM
2725#define scsiTarget_StatusReg__0__MASK 0x01u\r
2726#define scsiTarget_StatusReg__0__POS 0\r
2727#define scsiTarget_StatusReg__1__MASK 0x02u\r
2728#define scsiTarget_StatusReg__1__POS 1\r
95b51978
MM
2729#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
2730#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST\r
70257ca8
MM
2731#define scsiTarget_StatusReg__2__MASK 0x04u\r
2732#define scsiTarget_StatusReg__2__POS 2\r
2733#define scsiTarget_StatusReg__3__MASK 0x08u\r
2734#define scsiTarget_StatusReg__3__POS 3\r
2735#define scsiTarget_StatusReg__4__MASK 0x10u\r
2736#define scsiTarget_StatusReg__4__POS 4\r
2737#define scsiTarget_StatusReg__MASK 0x1Fu\r
95b51978
MM
2738#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB12_MSK\r
2739#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
2740#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB12_ST\r
75de1226 2741\r
70257ca8
MM
2742/* Debug_Timer_Interrupt */\r
2743#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
2744#define Debug_Timer_Interrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
2745#define Debug_Timer_Interrupt__INTC_MASK 0x02u\r
2746#define Debug_Timer_Interrupt__INTC_NUMBER 1u\r
2747#define Debug_Timer_Interrupt__INTC_PRIOR_NUM 7u\r
2748#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_1\r
2749#define Debug_Timer_Interrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
2750#define Debug_Timer_Interrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
75de1226 2751\r
70257ca8
MM
2752/* Debug_Timer_TimerHW */\r
2753#define Debug_Timer_TimerHW__CAP0 CYREG_TMR0_CAP0\r
2754#define Debug_Timer_TimerHW__CAP1 CYREG_TMR0_CAP1\r
2755#define Debug_Timer_TimerHW__CFG0 CYREG_TMR0_CFG0\r
2756#define Debug_Timer_TimerHW__CFG1 CYREG_TMR0_CFG1\r
2757#define Debug_Timer_TimerHW__CFG2 CYREG_TMR0_CFG2\r
2758#define Debug_Timer_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0\r
2759#define Debug_Timer_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1\r
2760#define Debug_Timer_TimerHW__PER0 CYREG_TMR0_PER0\r
2761#define Debug_Timer_TimerHW__PER1 CYREG_TMR0_PER1\r
2762#define Debug_Timer_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3\r
2763#define Debug_Timer_TimerHW__PM_ACT_MSK 0x01u\r
2764#define Debug_Timer_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3\r
2765#define Debug_Timer_TimerHW__PM_STBY_MSK 0x01u\r
2766#define Debug_Timer_TimerHW__RT0 CYREG_TMR0_RT0\r
2767#define Debug_Timer_TimerHW__RT1 CYREG_TMR0_RT1\r
2768#define Debug_Timer_TimerHW__SR0 CYREG_TMR0_SR0\r
2769\r
2770/* SCSI_RX_DMA */\r
2771#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
2772#define SCSI_RX_DMA__DRQ_NUMBER 0u\r
2773#define SCSI_RX_DMA__NUMBEROF_TDS 0u\r
2774#define SCSI_RX_DMA__PRIORITY 2u\r
2775#define SCSI_RX_DMA__TERMIN_EN 0u\r
2776#define SCSI_RX_DMA__TERMIN_SEL 0u\r
2777#define SCSI_RX_DMA__TERMOUT0_EN 1u\r
2778#define SCSI_RX_DMA__TERMOUT0_SEL 0u\r
2779#define SCSI_RX_DMA__TERMOUT1_EN 0u\r
2780#define SCSI_RX_DMA__TERMOUT1_SEL 0u\r
2781\r
2782/* SCSI_RX_DMA_COMPLETE */\r
2783#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
2784#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
2785#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x01u\r
2786#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 0u\r
2787#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
2788#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_0\r
2789#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
2790#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
2791\r
2792/* SCSI_TX_DMA */\r
2793#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
2794#define SCSI_TX_DMA__DRQ_NUMBER 1u\r
2795#define SCSI_TX_DMA__NUMBEROF_TDS 0u\r
2796#define SCSI_TX_DMA__PRIORITY 2u\r
2797#define SCSI_TX_DMA__TERMIN_EN 0u\r
2798#define SCSI_TX_DMA__TERMIN_SEL 0u\r
2799#define SCSI_TX_DMA__TERMOUT0_EN 1u\r
2800#define SCSI_TX_DMA__TERMOUT0_SEL 1u\r
2801#define SCSI_TX_DMA__TERMOUT1_EN 0u\r
2802#define SCSI_TX_DMA__TERMOUT1_SEL 0u\r
2803\r
2804/* SCSI_TX_DMA_COMPLETE */\r
2805#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
2806#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
2807#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x08u\r
2808#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 3u\r
2809#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
2810#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_3\r
2811#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
2812#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
2813\r
2814/* SD_Data_Clk */\r
2815#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0\r
2816#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1\r
2817#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2\r
2818#define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u\r
2819#define SD_Data_Clk__INDEX 0x00u\r
2820#define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2\r
2821#define SD_Data_Clk__PM_ACT_MSK 0x01u\r
2822#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
2823#define SD_Data_Clk__PM_STBY_MSK 0x01u\r
75de1226 2824\r
70257ca8
MM
2825/* timer_clock */\r
2826#define timer_clock__CFG0 CYREG_CLKDIST_DCFG2_CFG0\r
2827#define timer_clock__CFG1 CYREG_CLKDIST_DCFG2_CFG1\r
2828#define timer_clock__CFG2 CYREG_CLKDIST_DCFG2_CFG2\r
2829#define timer_clock__CFG2_SRC_SEL_MASK 0x07u\r
2830#define timer_clock__INDEX 0x02u\r
2831#define timer_clock__PM_ACT_CFG CYREG_PM_ACT_CFG2\r
2832#define timer_clock__PM_ACT_MSK 0x04u\r
2833#define timer_clock__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
2834#define timer_clock__PM_STBY_MSK 0x04u\r
75de1226 2835\r
70257ca8
MM
2836/* SCSI_RST_ISR */\r
2837#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
2838#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
2839#define SCSI_RST_ISR__INTC_MASK 0x04u\r
2840#define SCSI_RST_ISR__INTC_NUMBER 2u\r
2841#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u\r
2842#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_2\r
2843#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
2844#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
75de1226 2845\r
70257ca8
MM
2846/* SCSI_Filtered */\r
2847#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u\r
2848#define SCSI_Filtered_sts_sts_reg__0__POS 0\r
2849#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u\r
2850#define SCSI_Filtered_sts_sts_reg__1__POS 1\r
95b51978
MM
2851#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL\r
2852#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB13_14_ST\r
70257ca8
MM
2853#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u\r
2854#define SCSI_Filtered_sts_sts_reg__2__POS 2\r
2855#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u\r
2856#define SCSI_Filtered_sts_sts_reg__3__POS 3\r
2857#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u\r
2858#define SCSI_Filtered_sts_sts_reg__4__POS 4\r
2859#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu\r
95b51978
MM
2860#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB13_MSK\r
2861#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB13_ACTL\r
2862#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB13_ST\r
75de1226 2863\r
70257ca8
MM
2864/* SCSI_CTL_PHASE */\r
2865#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u\r
2866#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0\r
2867#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u\r
2868#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1\r
95b51978
MM
2869#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
2870#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
2871#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL\r
2872#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
2873#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL\r
2874#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK\r
2875#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
2876#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK\r
2877#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
70257ca8
MM
2878#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u\r
2879#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2\r
95b51978
MM
2880#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
2881#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL\r
2882#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL\r
2883#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL\r
2884#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL\r
70257ca8 2885#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u\r
95b51978
MM
2886#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
2887#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
2888#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK\r
75de1226 2889\r
70257ca8
MM
2890/* SCSI_Parity_Error */\r
2891#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u\r
2892#define SCSI_Parity_Error_sts_sts_reg__0__POS 0\r
95b51978
MM
2893#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
2894#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST\r
70257ca8 2895#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u\r
95b51978
MM
2896#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB05_MSK\r
2897#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
2898#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB05_ST\r
75de1226
MM
2899\r
2900/* Miscellaneous */\r
5bcd0c3a
MM
2901#define BCLK__BUS_CLK__HZ 50000000U\r
2902#define BCLK__BUS_CLK__KHZ 50000U\r
2903#define BCLK__BUS_CLK__MHZ 50U\r
70257ca8 2904#define CY_VERSION "PSoC Creator 3.1"\r
75de1226 2905#define CYDEV_CHIP_DIE_LEOPARD 1u\r
70257ca8
MM
2906#define CYDEV_CHIP_DIE_PANTHER 6u\r
2907#define CYDEV_CHIP_DIE_PSOC4A 3u\r
2908#define CYDEV_CHIP_DIE_PSOC5LP 5u\r
75de1226
MM
2909#define CYDEV_CHIP_DIE_UNKNOWN 0u\r
2910#define CYDEV_CHIP_FAMILY_PSOC3 1u\r
2911#define CYDEV_CHIP_FAMILY_PSOC4 2u\r
70257ca8 2912#define CYDEV_CHIP_FAMILY_PSOC5 3u\r
75de1226
MM
2913#define CYDEV_CHIP_FAMILY_UNKNOWN 0u\r
2914#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5\r
c693c7fa 2915#define CYDEV_CHIP_JTAG_ID 0x2E133069u\r
75de1226 2916#define CYDEV_CHIP_MEMBER_3A 1u\r
70257ca8
MM
2917#define CYDEV_CHIP_MEMBER_4A 3u\r
2918#define CYDEV_CHIP_MEMBER_4D 2u\r
2919#define CYDEV_CHIP_MEMBER_4F 4u\r
2920#define CYDEV_CHIP_MEMBER_5A 6u\r
2921#define CYDEV_CHIP_MEMBER_5B 5u\r
75de1226
MM
2922#define CYDEV_CHIP_MEMBER_UNKNOWN 0u\r
2923#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B\r
70257ca8
MM
2924#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED\r
2925#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT\r
2926#define CYDEV_CHIP_REV_LEOPARD_ES1 0u\r
2927#define CYDEV_CHIP_REV_LEOPARD_ES2 1u\r
2928#define CYDEV_CHIP_REV_LEOPARD_ES3 3u\r
2929#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u\r
2930#define CYDEV_CHIP_REV_PANTHER_ES0 0u\r
2931#define CYDEV_CHIP_REV_PANTHER_ES1 1u\r
2932#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u\r