software/SCSI2SD/src/scsiPhy.h

   1 //      Copyright (C) 2013 Michael McMaster <michael@codesrc.com>
   2 //
   3 //      This file is part of SCSI2SD.
   4 //
   5 //      SCSI2SD is free software: you can redistribute it and/or modify
   6 //      it under the terms of the GNU General Public License as published by
   7 //      the Free Software Foundation, either version 3 of the License, or
   8 //      (at your option) any later version.
   9 //
  10 //      SCSI2SD is distributed in the hope that it will be useful,
  11 //      but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 //      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 //      GNU General Public License for more details.
  14 //
  15 //      You should have received a copy of the GNU General Public License
  16 //      along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.
  17 #ifndef SCSIPHY_H
  18 #define SCSIPHY_H
  19
  20 // Definitions to match the scsiTarget status register.
  21 typedef enum
  22 {
  23         SCSI_PHY_TX_FIFO_NOT_FULL =  0x01,
  24         SCSI_PHY_RX_FIFO_NOT_EMPTY = 0x02,
  25
  26         // The TX FIFO is empty and the state machine is in the idle state
  27         SCSI_PHY_TX_COMPLETE = 0x10
  28 } SCSI_PHY_STATE;
  29
  30 #define scsiPhyStatus() CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG)
  31 #define scsiPhyTxFifoFull() ((scsiPhyStatus() & SCSI_PHY_TX_FIFO_NOT_FULL) == 0)
  32 #define scsiPhyRxFifoEmpty() ((scsiPhyStatus() & SCSI_PHY_RX_FIFO_NOT_EMPTY) == 0)
  33
  34 // Clear 4 byte fifo
  35 #define scsiPhyRxFifoClear() scsiPhyRx(); scsiPhyRx(); scsiPhyRx(); scsiPhyRx();
  36
  37 #define scsiPhyTx(val) CY_SET_REG8(scsiTarget_datapath__F0_REG, (val))
  38 #define scsiPhyRx() CY_GET_REG8(scsiTarget_datapath__F1_REG)
  39
  40 #define SCSI_SetPin(pin) \
  41         CyPins_SetPin((pin));
  42
  43 #define SCSI_ClearPin(pin) \
  44         CyPins_ClearPin((pin));
  45
  46 // Active low: we interpret a 0 as "true", and non-zero as "false"
  47 #define SCSI_ReadPin(pin) \
  48         (CyPins_ReadPin((pin)) == 0)
  49
  50 // These signals go through a glitch filter - we do not access the pin
  51 // directly
  52 enum FilteredInputs
  53 {
  54         SCSI_Filt_ATN = 0x01,
  55         SCSI_Filt_BSY = 0x02,
  56         SCSI_Filt_SEL = 0x04,
  57         SCSI_Filt_RST = 0x08,
  58         SCSI_Filt_ACK = 0x10
  59 };
  60 #define SCSI_ReadFilt(filt) \
  61         ((SCSI_Filtered_Read() & (filt)) == 0)
  62
  63 // SCSI delays, as referenced to the cpu clock
  64 #define CPU_CLK_PERIOD_NS (1000000000U / BCLK__BUS_CLK__HZ)
  65 #define scsiDeskewDelay() CyDelayCycles((55 / CPU_CLK_PERIOD_NS) + 1)
  66
  67 // Contains the odd-parity flag for a given 8-bit value.
  68 extern const uint8_t Lookup_OddParity[256];
  69
  70 extern volatile uint8_t scsiRxDMAComplete;
  71 extern volatile uint8_t scsiTxDMAComplete;
  72 #define scsiDMABusy() (!(scsiRxDMAComplete && scsiTxDMAComplete))
  73
  74 void scsiPhyReset(void);
  75 void scsiPhyInit(void);
  76
  77 uint8_t scsiReadByte(void);
  78 void scsiRead(uint8_t* data, uint32_t count);
  79 void scsiReadDMA(uint8_t* data, uint32_t count);
  80 int scsiReadDMAPoll();
  81
  82 void scsiWriteByte(uint8_t value);
  83 void scsiWrite(const uint8_t* data, uint32_t count);
  84 void scsiWriteDMA(const uint8_t* data, uint32_t count);
  85 int scsiWriteDMAPoll();
  86
  87 uint8_t scsiReadDBxPins(void);
  88
  89 void scsiEnterPhase(int phase);
  90
  91 #endif