Change default configuration to 2GB limit, no parity, no attention.
[SCSI2SD.git] / software / SCSI2SD / v4 / SCSI2SD.cydsn / SCSI2SD.cycdx
CommitLineData
abe0a5f5
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1<?xml version="1.0" encoding="utf-8"?>
2<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">
5456126c 3 <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
7db82a4e 4 <block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
5456126c
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5 <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
6 <block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
7 <block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
8 <block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />
9 <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
638c94ce 10 <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006473" bitWidth="8" desc="" />
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11 </block>
12 <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">
638c94ce 13 <register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006474" bitWidth="8" desc="" />
5456126c
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14 </block>
15 <block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true">
16 <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
17 <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
18 <block name="TimerHW" BASE="0x0" SIZE="0x0" desc="" visible="true" />
19 <block name="OneTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
20 <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
21 <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
22 <register name="Debug_Timer_GLOBAL_ENABLE" address="0x400043A3" bitWidth="8" desc="PM.ACT.CFG">
23 <field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." />
24 </register>
25 <register name="Debug_Timer_CONTROL" address="0x40004F00" bitWidth="8" desc="TMRx.CFG0">
26 <field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." />
27 <field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)">
28 <value name="Timer" value="0" desc="Timer mode. CNT/CMP register holds timer count value." />
29 <value name="Comparator" value="1" desc="Comparator mode. CNT/CMP register holds comparator threshold value." />
30 </field>
31 <field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." />
32 <field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." />
33 <field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" />
34 <field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.">
35 <value name="Timer" value="0" desc="CMP and TC are output." />
36 <value name="Deadband" value="1" desc="PHI1 (instead of CMP) and PHI2 (instead of TC) are output." />
37 </field>
38 <field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" />
39 </register>
40 <register name="Debug_Timer_CONTROL2" address="0x40004F01" bitWidth="8" desc="TMRx.CFG1">
41 <field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" />
42 <field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.">
43 <value name="Disable FTC" value="0" desc="Disable the single cycle pulse, which signifies the timer is starting." />
44 <value name="Enable FTC" value="1" desc="Enable the single cycle pulse, which signifies the timer is starting." />
45 </field>
46 <field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." />
47 <field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." />
48 <field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." />
49 <field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." />
50 </register>
51 <register name="Debug_Timer_CONTROL3_" address="0x40004F02" bitWidth="8" desc="TMRx.CFG2">
52 <field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ">
53 <value name="Continuous" value="0" desc="Timer runs while EN bit of CFG0 register is set to '1'." />
54 <value name="Pulsewidth" value="1" desc="Timer runs from positive to negative edge of TIMEREN." />
55 <value name="Period" value="10" desc="Timer runs from positive to positive edge of TIMEREN." />
56 <value name="Irq" value="11" desc="Timer runs until IRQ." />
57 </field>
58 <field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." />
59 <field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" />
60 <field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations">
61 <value name="Equal" value="0" desc="Compare Equal " />
62 <value name="Less than" value="1" desc="Compare Less Than " />
63 <value name="Less than or equal" value="10" desc="Compare Less Than or Equal ." />
64 <value name="Greater" value="11" desc="Compare Greater Than ." />
65 <value name="Greater than or equal" value="100" desc="Compare Greater Than or Equal " />
66 </field>
67 <field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." />
68 </register>
69 <register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" />
70 <register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" />
71 </block>
72 <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
73 <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />
5ede6f0d 74 <block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
5456126c
MM
75 <block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
76 <block name="Clock_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
77 <block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
78 <block name="EXTLED" BASE="0x0" SIZE="0x0" desc="" visible="true" />
79 <block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
80 <block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
81 <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
5ede6f0d 82 <block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
5456126c 83 <block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true">
638c94ce
MM
84 <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006465" bitWidth="8" desc="" />
85 <register name="SCSI_Parity_Error_MASK_REG" address="0x40006485" bitWidth="8" desc="" />
86 <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006495" bitWidth="8" desc="">
5456126c
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87 <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
88 <value name="ENABLED" value="1" desc="Enable counter" />
89 <value name="DISABLED" value="0" desc="Disable counter" />
90 </field>
91 <field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">
92 <value name="ENABLED" value="1" desc="Interrupt enabled" />
93 <value name="DISABLED" value="0" desc="Interrupt disabled" />
94 </field>
95 <field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">
96 <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
97 <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
98 </field>
99 <field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">
100 <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
101 <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
102 </field>
103 <field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">
104 <value name="ENABLED" value="1" desc="Clear FIFO state" />
105 <value name="DISABLED" value="0" desc="Normal FIFO operation" />
106 </field>
107 <field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">
108 <value name="ENABLED" value="1" desc="Clear FIFO state" />
109 <value name="DISABLED" value="0" desc="Normal FIFO operation" />
110 </field>
111 </register>
112 </block>
113 <block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
114 <block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true">
638c94ce
MM
115 <register name="SCSI_Filtered_STATUS_REG" address="0x40006460" bitWidth="8" desc="" />
116 <register name="SCSI_Filtered_MASK_REG" address="0x40006480" bitWidth="8" desc="" />
117 <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006490" bitWidth="8" desc="">
5456126c
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118 <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
119 <value name="ENABLED" value="1" desc="Enable counter" />
120 <value name="DISABLED" value="0" desc="Disable counter" />
121 </field>
122 <field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">
123 <value name="ENABLED" value="1" desc="Interrupt enabled" />
124 <value name="DISABLED" value="0" desc="Interrupt disabled" />
125 </field>
126 <field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">
127 <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
128 <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
129 </field>
130 <field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">
131 <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
132 <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
133 </field>
134 <field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">
135 <value name="ENABLED" value="1" desc="Clear FIFO state" />
136 <value name="DISABLED" value="0" desc="Normal FIFO operation" />
137 </field>
138 <field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">
139 <value name="ENABLED" value="1" desc="Clear FIFO state" />
140 <value name="DISABLED" value="0" desc="Normal FIFO operation" />
141 </field>
142 </register>
143 </block>
144 <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />
145 <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />
146 <block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
147 <block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
148 <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />
149 <block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
150 <block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
151 <block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
152 <block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />
153 <block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">
638c94ce 154 <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006471" bitWidth="8" desc="" />
5456126c
MM
155 </block>
156 <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />
157 <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />
158 <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />
7db82a4e
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159 <block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">
160 <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
161 <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
162 <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
163 <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
164 <block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
165 </block>
abe0a5f5
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166 <block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">
167 <block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />
168 <block name="ep_0" BASE="0x0" SIZE="0x0" desc="" visible="true" />
5ede6f0d 169 <block name="ep_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
abe0a5f5
MM
170 <block name="USB" BASE="0x0" SIZE="0x0" desc="" visible="true" />
171 <block name="sof_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
5ede6f0d
MM
172 <block name="arb_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
173 <block name="ep_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
174 <block name="Dp" BASE="0x0" SIZE="0x0" desc="" visible="true" />
abe0a5f5
MM
175 <block name="dp_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
176 <block name="Clock_vbus" BASE="0x0" SIZE="0x0" desc="" visible="true" />
5ede6f0d
MM
177 <block name="ep_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
178 <block name="ep_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />
abe0a5f5
MM
179 <block name="Dm" BASE="0x0" SIZE="0x0" desc="" visible="true" />
180 <register name="USBFS_PM_USB_CR0" address="0x40004394" bitWidth="8" desc="USB Power Mode Control Register 0">
181 <field name="fsusbio_ref_en" from="0" to="0" access="RW" resetVal="" desc="" />
182 <field name="fsusbio_pd_n" from="1" to="1" access="RW" resetVal="" desc="" />
183 <field name="fsusbio_pd_pullup_n" from="2" to="2" access="RW" resetVal="" desc="" />
184 </register>
185 <register name="USBFS_PM_ACT_CFG" address="0x400043A5" bitWidth="8" desc="Active Power Mode Configuration Register" />
186 <register name="USBFS_PM_STBY_CFG" address="0x400043B5" bitWidth="8" desc="Standby Power Mode Configuration Register" />
187 <register name="USBFS_PRT.PS" address="0x400051F1" bitWidth="8" desc="Port Pin State Register">
188 <field name="PinState_DP" from="6" to="6" access="R" resetVal="" desc="" />
189 <field name="PinState_DM" from="7" to="7" access="R" resetVal="" desc="" />
190 </register>
191 <register name="USBFS_PRT_DM0" address="0x400051F2" bitWidth="8" desc="Port Drive Mode Register">
192 <field name="DriveMode_DP" from="6" to="6" access="RW" resetVal="" desc="" />
193 <field name="DriveMode_DM" from="7" to="7" access="RW" resetVal="" desc="" />
194 </register>
195 <register name="USBFS_PRT_DM1" address="0x400051F3" bitWidth="8" desc="Port Drive Mode Register">
196 <field name="PullUp_en_DP" from="6" to="6" access="RW" resetVal="" desc="" />
197 <field name="PullUp_en_DM" from="7" to="7" access="RW" resetVal="" desc="" />
198 </register>
199 <register name="USBFS_PRT.INP_DIS" address="0x400051F8" bitWidth="8" desc="Input buffer disable override">
200 <field name="seinput_dis_dp" from="6" to="6" access="RW" resetVal="" desc="" />
201 <field name="seinput_dis_dm" from="7" to="7" access="RW" resetVal="" desc="" />
202 </register>
203 <register name="USBFS_EP0_DR0" address="0x40006000" bitWidth="8" desc="bmRequestType" />
204 <register name="USBFS_EP0_DR1" address="0x40006001" bitWidth="8" desc="bRequest" />
205 <register name="USBFS_EP0_DR2" address="0x40006002" bitWidth="8" desc="wValueLo" />
206 <register name="USBFS_EP0_DR3" address="0x40006003" bitWidth="8" desc="wValueHi" />
207 <register name="USBFS_EP0_DR4" address="0x40006004" bitWidth="8" desc="wIndexLo" />
208 <register name="USBFS_EP0_DR5" address="0x40006005" bitWidth="8" desc="wIndexHi" />
209 <register name="USBFS_EP0_DR6" address="0x40006006" bitWidth="8" desc="lengthLo" />
210 <register name="USBFS_EP0_DR7" address="0x40006007" bitWidth="8" desc="lengthHi" />
211 <register name="USBFS_CR0" address="0x40006008" bitWidth="8" desc="USB Control Register 0">
212 <field name="device_address" from="0" to="6" access="R" resetVal="" desc="" />
213 <field name="usb_enable" from="7" to="7" access="RW" resetVal="" desc="" />
214 </register>
215 <register name="USBFS_CR1" address="0x40006009" bitWidth="8" desc="USB Control Register 1">
216 <field name="reg_enable" from="0" to="0" access="RW" resetVal="" desc="" />
217 <field name="enable_lock" from="1" to="1" access="RW" resetVal="" desc="" />
218 <field name="bus_activity" from="2" to="2" access="RW" resetVal="" desc="" />
219 <field name="trim_offset_msb" from="3" to="3" access="RW" resetVal="" desc="" />
220 </register>
221 <register name="USBFS_SIE_EP1_CR0" address="0x4000600E" bitWidth="8" desc="The Endpoint1 Control Register" />
222 <register name="USBFS_USBIO_CR0" address="0x40006010" bitWidth="8" desc="USBIO Control Register 0">
223 <field name="rd" from="0" to="0" access="R" resetVal="" desc="" />
224 <field name="td" from="5" to="5" access="RW" resetVal="" desc="" />
225 <field name="tse0" from="6" to="6" access="RW" resetVal="" desc="" />
226 <field name="ten" from="7" to="7" access="RW" resetVal="" desc="" />
227 </register>
228 <register name="USBFS_USBIO_CR1" address="0x40006012" bitWidth="8" desc="USBIO Control Register 1">
229 <field name="dmo" from="0" to="0" access="R" resetVal="" desc="" />
230 <field name="dpo" from="1" to="1" access="R" resetVal="" desc="" />
231 <field name="usbpuen" from="2" to="2" access="RW" resetVal="" desc="" />
232 <field name="iomode" from="5" to="5" access="RW" resetVal="" desc="" />
233 </register>
234 <register name="USBFS_SIE_EP2_CR0" address="0x4000601E" bitWidth="8" desc="The Endpoint2 Control Register" />
235 <register name="USBFS_SIE_EP3_CR0" address="0x4000602E" bitWidth="8" desc="The Endpoint3 Control Register" />
236 <register name="USBFS_SIE_EP4_CR0" address="0x4000603E" bitWidth="8" desc="The Endpoint4 Control Register" />
237 <register name="USBFS_SIE_EP5_CR0" address="0x4000604E" bitWidth="8" desc="The Endpoint5 Control Register" />
238 <register name="USBFS_SIE_EP6_CR0" address="0x4000605E" bitWidth="8" desc="The Endpoint6 Control Register" />
239 <register name="USBFS_SIE_EP7_CR0" address="0x4000606E" bitWidth="8" desc="The Endpoint7 Control Register" />
240 <register name="USBFS_SIE_EP8_CR0" address="0x4000607E" bitWidth="8" desc="The Endpoint8 Control Register" />
241 <register name="USBFS_BUF_SIZE" address="0x4000608C" bitWidth="8" desc="Dedicated Endpoint Buffer Size Register" />
242 <register name="USBFS_EP_ACTIVE" address="0x4000608E" bitWidth="8" desc="Endpoint Active Indication Register" />
243 <register name="USBFS_EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" />
244 <register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" />
245 </block>
5456126c
MM
246 <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />
247 <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
248 <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
249 <block name="not_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
7db82a4e 250 <block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
5456126c
MM
251 <block name="SCSI_Noise" BASE="0x0" SIZE="0x0" desc="" visible="true" />
252 <block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />
5e0f1e33 253 <block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
abe0a5f5 254</blockRegMap>