Force unit-attention-condition off for pre-SCSI2 hosts

diff --git a/CHANGELOG b/CHANGELOG
index 0e6de11013ee6851b3a7cf8da1a478a5d6c45655..6c4b96fd15e7bbb44182dacbb68d1e2e78e349db 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,11 +1,13 @@
-20140???               3.3
+20140416               3.3
        - Fix to SCSI Reset handling to avoid lockups
        - Bug fixes to improve standards compatibility
        - Bug fix for Unit Attention Condition, which is now enabled by default.
-               - scsi2sd-config can be used to disable it for those systems that
+               scsi2sd-config can be used to disable it for those systems that
                truely require it (eg. Mac Plus).
        - Added Linked commands support.
        - Added support for configurable sector sizes between 64 and 2048 bytes.
+               The sector size can be set via the MODE SELECT command using a SCSI
+               format utility, or via scsi2sd-config
        - Powerbook firmware added
 
 20140214               3.2

diff --git a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit
index d6ca5042ce7d59f0d6b2238f54299bd1a22af9af..8b99a495e208a83252a2ec6616fe50b52abc36fb 100755 (executable)
Binary files a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit and b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit differ

diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cyfit b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cyfit
index 0ec8f5f1fcedbdf5203a385a7dede1ff38f8f47c..08bc6f0bee66dcac1b9b07e9db743e1d77b89353 100755 (executable)
Binary files a/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cyfit and b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cyfit differ

diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cyprj.Micha_000 b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cyprj.Micha_000
index 5f6a94463a18c7ce28668937d1cc3b8ef4540cf6..60d50ee9cbd588aa6c572c7a96eb9292d942d287 100755 (executable)
--- a/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cyprj.Micha_000
+++ b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cyprj.Micha_000
@@ -1663,14 +1663,14 @@
 <v>C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif</v>\r
 <v>C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif</v>\r
 </warp_dep>\r
-<deps_time v="130400487594237024" />\r
+<deps_time v="130421205782926169" />\r
 <top_block v="TopDesign" />\r
 <last_generation v="0" />\r
 </CyGuid_925cc1e1-309e-4e08-b0a1-09a83c35b157>\r
 </dataGuid>\r
 <dataGuid v="769d31ea-68b1-4f0c-b90a-7c10a43ee563">\r
 <CyGuid_769d31ea-68b1-4f0c-b90a-7c10a43ee563 type_name="CyDesigner.Common.ProjMgmt.Model.CyLinkCustomData" version="1">\r
-<deps_time v="130400487992691193" />\r
+<deps_time v="130421206235126109" />\r
 </CyGuid_769d31ea-68b1-4f0c-b90a-7c10a43ee563>\r
 </dataGuid>\r
 <dataGuid v="bf610382-39c6-441f-80b8-b04622ea7845">\r

diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.rpt b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.rpt
index 1536367d05126049d70cdae9d88f805e3cb420ce..3b14907b1477c17d3ee2af7e756ddb57cd2ce885 100755 (executable)
--- a/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.rpt
+++ b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.rpt
@@ -1,13 +1,13 @@
-Loading plugins phase: Elapsed time ==> 0s.499ms\r
-Initializing data phase: Elapsed time ==> 3s.703ms\r
+Loading plugins phase: Elapsed time ==> 0s.481ms\r
+Initializing data phase: Elapsed time ==> 3s.796ms\r
 <CYPRESSTAG name="CyDsfit arguments...">\r
 cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -p W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 -s W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\Generated_Source\PSoC5 -- -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE</CYPRESSTAG>\r
 <CYPRESSTAG name="Design elaboration results...">\r
 </CYPRESSTAG>\r
-Elaboration phase: Elapsed time ==> 7s.531ms\r
+Elaboration phase: Elapsed time ==> 7s.874ms\r
 <CYPRESSTAG name="HDL generation results...">\r
 </CYPRESSTAG>\r
-HDL generation phase: Elapsed time ==> 0s.109ms\r
+HDL generation phase: Elapsed time ==> 0s.173ms\r
 <CYPRESSTAG name="Synthesis results...">\r
 \r
      | | | | | | |\r
@@ -41,7 +41,7 @@ Options  :    -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\sof
 ======================================================================\r
 \r
 vlogfe V6.3 IR 41:  Verilog parser\r
-Sun Mar 23 21:45:41 2014\r
+Wed Apr 16 21:15:58 2014\r
 \r
 \r
 ======================================================================\r
@@ -51,7 +51,7 @@ Options  :    -yv2 -q10 USB_Bootloader.v
 ======================================================================\r
 \r
 vpp V6.3 IR 41:  Verilog Pre-Processor\r
-Sun Mar 23 21:45:41 2014\r
+Wed Apr 16 21:15:59 2014\r
 \r
 \r
 vpp:  No errors.\r
@@ -80,7 +80,7 @@ Options  :    -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\sof
 ======================================================================\r
 \r
 tovif V6.3 IR 41:  High-level synthesis\r
-Sun Mar 23 21:45:42 2014\r
+Wed Apr 16 21:15:59 2014\r
 \r
 Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'.\r
 Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'.\r
@@ -104,7 +104,7 @@ Options  :    -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\sof
 ======================================================================\r
 \r
 topld V6.3 IR 41:  Synthesis and optimization\r
-Sun Mar 23 21:45:42 2014\r
+Wed Apr 16 21:16:00 2014\r
 \r
 Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'.\r
 Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'.\r
@@ -204,10 +204,10 @@ CYPRESS_DIR    : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\wa
 Warp Program   : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe\r
 Warp Arguments : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog\r
 </CYPRESSTAG>\r
-Warp synthesis phase: Elapsed time ==> 1s.454ms\r
+Warp synthesis phase: Elapsed time ==> 2s.967ms\r
 <CYPRESSTAG name="Fitter results...">\r
 <CYPRESSTAG name="Fitter startup details...">\r
-cyp3fit: V3.0.0.1539, Family: PSoC3, Started at: Sunday, 23 March 2014 21:45:43\r
+cyp3fit: V3.0.0.1539, Family: PSoC3, Started at: Wednesday, 16 April 2014 21:16:01\r
 Options: -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 USB_Bootloader.v -verilog\r
 </CYPRESSTAG>\r
 <CYPRESSTAG name="Design parsing">\r
@@ -1314,7 +1314,7 @@ EMIF Fixed Blocks             :    0 :    1 :    1 :   0.00%
 LPF Fixed Blocks              :    0 :    2 :    2 :   0.00%\r
 SAR Fixed Blocks              :    0 :    1 :    1 :   0.00%\r
 </CYPRESSTAG>\r
-Technology Mapping: Elapsed time ==> 0s.031ms\r
+Technology Mapping: Elapsed time ==> 0s.015ms\r
 Tech mapping phase: Elapsed time ==> 0s.281ms\r
 </CYPRESSTAG>\r
 <CYPRESSTAG name="Analog Placement">\r
@@ -1345,7 +1345,7 @@ IO_5@[IOP=(3)][IoId=(5)] : SD_PULLUP(4) (fixed)
 IO_7@[IOP=(15)][IoId=(7)] : \USBFS:Dm(0)\ (fixed)\r
 IO_6@[IOP=(15)][IoId=(6)] : \USBFS:Dp(0)\ (fixed)\r
 USB[0]@[FFB(USB,0)] : \USBFS:USB\\r
-Analog Placement phase: Elapsed time ==> 0s.156ms\r
+Analog Placement phase: Elapsed time ==> 0s.109ms\r
 </CYPRESSTAG>\r
 <CYPRESSTAG name="Analog Routing">\r
 Analog Routing phase: Elapsed time ==> 0s.000ms\r
@@ -1363,12 +1363,12 @@ Dump of CyP35AnalogRoutingResultsDB
 IsVddaHalfUsedForComp = False\r
 IsVddaHalfUsedForSar0 = False\r
 IsVddaHalfUsedForSar1 = False\r
-Analog Code Generation phase: Elapsed time ==> 1s.187ms\r
+Analog Code Generation phase: Elapsed time ==> 1s.031ms\r
 </CYPRESSTAG>\r
 <CYPRESSTAG name="Digital Placement">\r
 <CYPRESSTAG name="Detailed placement messages">\r
 I2659: No Constrained paths were found. The placer will run in non-timing driven mode.\r
-I2076: Total run-time: 2.4 sec.\r
+I2076: Total run-time: 1.6 sec.\r
 \r
 </CYPRESSTAG>\r
 <CYPRESSTAG name="PLD Packing">\r
@@ -1382,7 +1382,7 @@ PLD Packing: Elapsed time ==> 0s.000ms
 Initial Partitioning Summary not displayed at this verbose level.</CYPRESSTAG>\r
 <CYPRESSTAG name="Final Partitioning Summary">\r
 Final Partitioning Summary not displayed at this verbose level.</CYPRESSTAG>\r
-Partitioning: Elapsed time ==> 0s.078ms\r
+Partitioning: Elapsed time ==> 0s.077ms\r
 </CYPRESSTAG>\r
 <CYPRESSTAG name="Simulated Annealing">\r
 Annealing: Elapsed time ==> 0s.000ms\r
@@ -2664,32 +2664,32 @@ Port | Pin | Fixed |      Type |       Drive Mode |            Name | Connection
 </CYPRESSTAG>\r
 </CYPRESSTAG>\r
 </CYPRESSTAG>\r
-Digital component placer commit/Report: Elapsed time ==> 0s.016ms\r
-Digital Placement phase: Elapsed time ==> 3s.031ms\r
+Digital component placer commit/Report: Elapsed time ==> 0s.017ms\r
+Digital Placement phase: Elapsed time ==> 2s.641ms\r
 </CYPRESSTAG>\r
 <CYPRESSTAG name="Digital Routing">\r
 Routing successful.\r
-Digital Routing phase: Elapsed time ==> 3s.046ms\r
+Digital Routing phase: Elapsed time ==> 3s.404ms\r
 </CYPRESSTAG>\r
 <CYPRESSTAG name="Bitstream and API generation">\r
-Bitstream and API generation phase: Elapsed time ==> 0s.718ms\r
+Bitstream and API generation phase: Elapsed time ==> 0s.796ms\r
 </CYPRESSTAG>\r
 <CYPRESSTAG name="Bitstream verification">\r
-Bitstream verification phase: Elapsed time ==> 0s.159ms\r
+Bitstream verification phase: Elapsed time ==> 0s.171ms\r
 </CYPRESSTAG>\r
 <CYPRESSTAG name="Static timing analysis">\r
 Timing report is in USB_Bootloader_timing.html.\r
-Static timing analysis phase: Elapsed time ==> 1s.074ms\r
+Static timing analysis phase: Elapsed time ==> 0s.812ms\r
 </CYPRESSTAG>\r
 <CYPRESSTAG name="Data reporting">\r
 Data reporting phase: Elapsed time ==> 0s.000ms\r
 </CYPRESSTAG>\r
 <CYPRESSTAG name="Database update...">\r
-Design database save phase: Elapsed time ==> 0s.374ms\r
+Design database save phase: Elapsed time ==> 0s.406ms\r
 </CYPRESSTAG>\r
-cydsfit: Elapsed time ==> 10s.140ms\r
+cydsfit: Elapsed time ==> 9s.781ms\r
 </CYPRESSTAG>\r
-Fitter phase: Elapsed time ==> 10s.233ms\r
-API generation phase: Elapsed time ==> 4s.062ms\r
-Dependency generation phase: Elapsed time ==> 0s.031ms\r
-Cleanup phase: Elapsed time ==> 0s.046ms\r
+Fitter phase: Elapsed time ==> 9s.859ms\r
+API generation phase: Elapsed time ==> 4s.706ms\r
+Dependency generation phase: Elapsed time ==> 0s.028ms\r
+Cleanup phase: Elapsed time ==> 0s.063ms\r

diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader_timing.html b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader_timing.html
index 5617ccc8a755b4e502ee3b92b38053227b6649e9..20322aeb9f14e31588d1037828735b1f83fdb2d6 100755 (executable)
--- a/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader_timing.html
+++ b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader_timing.html
@@ -539,7 +539,7 @@ function getElementsByClass(rootNode, elemName, className)
 <tr> <td class="prop"> Project :</td>\r
 <td class="proptext"> USB_Bootloader</td></tr>\r
 <tr> <td class="prop"> Build Time :</td>\r
-<td class="proptext"> 03/23/14 21:45:52</td></tr>\r
+<td class="proptext"> 04/16/14 21:16:10</td></tr>\r
 <tr> <td class="prop"> Device :</td>\r
 <td class="proptext"> CY8C5267AXI-LP051</td></tr>\r
 <tr> <td class="prop"> Temperature :</td>\r

diff --git a/software/SCSI2SD/src/scsi.c b/software/SCSI2SD/src/scsi.c
index 37518337241c38d211c1feb2407c87a84dc5959b..7a9d3590cc3d8e15255a29c94a627f6fbbcfe2fa 100755 (executable)
--- a/software/SCSI2SD/src/scsi.c
+++ b/software/SCSI2SD/src/scsi.c
@@ -48,6 +48,10 @@ static void doReserveRelease(void);
 \r
 static void enter_BusFree()\r
 {\r
+       // This delay probably isn't needed for most SCSI hosts, but it won't\r
+       // hurt either. It's possible some of the samplers needed this delay.\r
+       CyDelayUs(2);\r
+\r
        SCSI_ClearPin(SCSI_Out_BSY);\r
        // We now have a Bus Clear Delay of 800ns to release remaining signals.\r
        SCSI_ClearPin(SCSI_Out_MSG);\r
@@ -492,9 +496,16 @@ static void process_SelectionPhase()
                (goodParity || !config->enableParity) && (maskBitCount <= 2))\r
        {\r
                // Do we enter MESSAGE OUT immediately ? SCSI 1 and 2 standards says\r
-               // move to MESSAGE OUT if ATN is true before we release BSY.\r
-               // The initiate should assert ATN with SEL.\r
+               // move to MESSAGE OUT if ATN is true before we assert BSY.\r
+               // The initiator should assert ATN with SEL.\r
                scsiDev.atnFlag = SCSI_ReadPin(SCSI_ATN_INT);\r
+               \r
+               // Unit attention breaks many older SCSI hosts. Disable it completely for\r
+               // SCSI-1 (and older) hosts, regardless of our configured setting.\r
+               if (!scsiDev.atnFlag)\r
+               {\r
+                       scsiDev.unitAttention = 0;\r
+               }\r
 \r
                // We've been selected!\r
                // Assert BSY - Selection success!\r

diff --git a/software/SCSI2SD/src/scsi.h b/software/SCSI2SD/src/scsi.h
index dd0c33a391bba50029f695dbb79c6b8aeb6a9e7a..4ed618b83c0bbd704a62177ca6343701b7916984 100755 (executable)
--- a/software/SCSI2SD/src/scsi.h
+++ b/software/SCSI2SD/src/scsi.h
@@ -20,7 +20,7 @@
 // Set this to true to log SCSI commands and status information via
 // USB HID packets.  The can be captured and viewed in wireshark.
 // For windows users, capture using USBPcap http://desowin.org/usbpcap/
-#define MM_DEBUG 1
+#define MM_DEBUG 0
 
 #include "geometry.h"
 #include "sense.h"