+201404?? 3.4
+ - Fix to ensure SCSI phase bits are set atomically.
+ - Decreased (unused) heap and stack sizes to prepare for a memory
+ write cache
+
20140416 3.3
- Fix to SCSI Reset handling to avoid lockups
- Bug fixes to improve standards compatibility
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000 - (32768 / 2);\r
define symbol __ICFEDIT_region_RAM_end__ = 0x20000000 + (32768 / 2) - 1;\r
/*-Sizes-*/\r
-define symbol __ICFEDIT_size_cstack__ = 0x4000;\r
-define symbol __ICFEDIT_size_heap__ = 0x1000;\r
+define symbol __ICFEDIT_size_cstack__ = 0x2000;\r
+define symbol __ICFEDIT_size_heap__ = 0x0256;\r
/**** End of ICF editor section. ###ICF###*/\r
\r
\r
.ANY (+RW, +ZI)\r
}\r
\r
- ARM_LIB_HEAP (0x20000000 + (32768 / 2) - 0x1000 - 0x4000) EMPTY 0x1000\r
+ ARM_LIB_HEAP (0x20000000 + (32768 / 2) - 0x0256 - 0x2000) EMPTY 0x0256\r
{\r
}\r
\r
- ARM_LIB_STACK (0x20000000 + (32768 / 2)) EMPTY -0x4000\r
+ ARM_LIB_STACK (0x20000000 + (32768 / 2)) EMPTY -0x2000\r
{\r
}\r
}\r
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_CLK.c
+* Version 2.10
+*
+* Description:
+* This file provides the source code to the API for the clock component.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include <cydevice_trm.h>
+#include "SCSI_CLK.h"
+
+/* Clock Distribution registers. */
+#define CLK_DIST_LD (* (reg8 *) CYREG_CLKDIST_LD)
+#define CLK_DIST_BCFG2 (* (reg8 *) CYREG_CLKDIST_BCFG2)
+#define BCFG2_MASK (0x80u)
+#define CLK_DIST_DMASK (* (reg8 *) CYREG_CLKDIST_DMASK)
+#define CLK_DIST_AMASK (* (reg8 *) CYREG_CLKDIST_AMASK)
+
+#define HAS_CLKDIST_LD_DISABLE (CY_PSOC3 || CY_PSOC5LP)
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_Start
+********************************************************************************
+*
+* Summary:
+* Starts the clock. Note that on startup, clocks may be already running if the
+* "Start on Reset" option is enabled in the DWR.
+*
+* Parameters:
+* None
+*
+* Returns:
+* None
+*
+*******************************************************************************/
+void SCSI_CLK_Start(void)
+{
+ /* Set the bit to enable the clock. */
+ SCSI_CLK_CLKEN |= SCSI_CLK_CLKEN_MASK;
+ SCSI_CLK_CLKSTBY |= SCSI_CLK_CLKSTBY_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_Stop
+********************************************************************************
+*
+* Summary:
+* Stops the clock and returns immediately. This API does not require the
+* source clock to be running but may return before the hardware is actually
+* disabled. If the settings of the clock are changed after calling this
+* function, the clock may glitch when it is started. To avoid the clock
+* glitch, use the StopBlock function.
+*
+* Parameters:
+* None
+*
+* Returns:
+* None
+*
+*******************************************************************************/
+void SCSI_CLK_Stop(void)
+{
+ /* Clear the bit to disable the clock. */
+ SCSI_CLK_CLKEN &= (uint8)(~SCSI_CLK_CLKEN_MASK);
+ SCSI_CLK_CLKSTBY &= (uint8)(~SCSI_CLK_CLKSTBY_MASK);
+}
+
+
+#if(CY_PSOC3 || CY_PSOC5LP)
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_StopBlock
+********************************************************************************
+*
+* Summary:
+* Stops the clock and waits for the hardware to actually be disabled before
+* returning. This ensures that the clock is never truncated (high part of the
+* cycle will terminate before the clock is disabled and the API returns).
+* Note that the source clock must be running or this API will never return as
+* a stopped clock cannot be disabled.
+*
+* Parameters:
+* None
+*
+* Returns:
+* None
+*
+*******************************************************************************/
+void SCSI_CLK_StopBlock(void)
+{
+ if ((SCSI_CLK_CLKEN & SCSI_CLK_CLKEN_MASK) != 0u)
+ {
+#if HAS_CLKDIST_LD_DISABLE
+ uint16 oldDivider;
+
+ CLK_DIST_LD = 0u;
+
+ /* Clear all the mask bits except ours. */
+#if defined(SCSI_CLK__CFG3)
+ CLK_DIST_AMASK = SCSI_CLK_CLKEN_MASK;
+ CLK_DIST_DMASK = 0x00u;
+#else
+ CLK_DIST_DMASK = SCSI_CLK_CLKEN_MASK;
+ CLK_DIST_AMASK = 0x00u;
+#endif /* SCSI_CLK__CFG3 */
+
+ /* Clear mask of bus clock. */
+ CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);
+
+ oldDivider = CY_GET_REG16(SCSI_CLK_DIV_PTR);
+ CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);
+ CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD;
+
+ /* Wait for clock to be disabled */
+ while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
+#endif /* HAS_CLKDIST_LD_DISABLE */
+
+ /* Clear the bit to disable the clock. */
+ SCSI_CLK_CLKEN &= (uint8)(~SCSI_CLK_CLKEN_MASK);
+ SCSI_CLK_CLKSTBY &= (uint8)(~SCSI_CLK_CLKSTBY_MASK);
+
+#if HAS_CLKDIST_LD_DISABLE
+ /* Clear the disable bit */
+ CLK_DIST_LD = 0x00u;
+ CY_SET_REG16(SCSI_CLK_DIV_PTR, oldDivider);
+#endif /* HAS_CLKDIST_LD_DISABLE */
+ }
+}
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_StandbyPower
+********************************************************************************
+*
+* Summary:
+* Sets whether the clock is active in standby mode.
+*
+* Parameters:
+* state: 0 to disable clock during standby, nonzero to enable.
+*
+* Returns:
+* None
+*
+*******************************************************************************/
+void SCSI_CLK_StandbyPower(uint8 state)
+{
+ if(state == 0u)
+ {
+ SCSI_CLK_CLKSTBY &= (uint8)(~SCSI_CLK_CLKSTBY_MASK);
+ }
+ else
+ {
+ SCSI_CLK_CLKSTBY |= SCSI_CLK_CLKSTBY_MASK;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_SetDividerRegister
+********************************************************************************
+*
+* Summary:
+* Modifies the clock divider and, thus, the frequency. When the clock divider
+* register is set to zero or changed from zero, the clock will be temporarily
+* disabled in order to change the SSS mode bit. If the clock is enabled when
+* SetDividerRegister is called, then the source clock must be running.
+*
+* Parameters:
+* clkDivider: Divider register value (0-65,535). This value is NOT the
+* divider; the clock hardware divides by clkDivider plus one. For example,
+* to divide the clock by 2, this parameter should be set to 1.
+* restart: If nonzero, restarts the clock divider: the current clock cycle
+* will be truncated and the new divide value will take effect immediately. If
+* zero, the new divide value will take effect at the end of the current clock
+* cycle.
+*
+* Returns:
+* None
+*
+*******************************************************************************/
+void SCSI_CLK_SetDividerRegister(uint16 clkDivider, uint8 restart)
+
+{
+ uint8 enabled;
+
+ uint8 currSrc = SCSI_CLK_GetSourceRegister();
+ uint16 oldDivider = SCSI_CLK_GetDividerRegister();
+
+ if (clkDivider != oldDivider)
+ {
+ enabled = SCSI_CLK_CLKEN & SCSI_CLK_CLKEN_MASK;
+
+ if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u)))
+ {
+ /* Moving to/from SSS requires correct ordering to prevent halting the clock */
+ if (oldDivider == 0u)
+ {
+ /* Moving away from SSS, set the divider first so when SSS is cleared we */
+ /* don't halt the clock. Using the shadow load isn't required as the */
+ /* divider is ignored while SSS is set. */
+ CY_SET_REG16(SCSI_CLK_DIV_PTR, clkDivider);
+ SCSI_CLK_MOD_SRC &= (uint8)(~CYCLK_SSS);
+ }
+ else
+ {
+ /* Moving to SSS, set SSS which then ignores the divider and we can set */
+ /* it without bothering with the shadow load. */
+ SCSI_CLK_MOD_SRC |= CYCLK_SSS;
+ CY_SET_REG16(SCSI_CLK_DIV_PTR, clkDivider);
+ }
+ }
+ else
+ {
+
+ if (enabled != 0u)
+ {
+ CLK_DIST_LD = 0x00u;
+
+ /* Clear all the mask bits except ours. */
+#if defined(SCSI_CLK__CFG3)
+ CLK_DIST_AMASK = SCSI_CLK_CLKEN_MASK;
+ CLK_DIST_DMASK = 0x00u;
+#else
+ CLK_DIST_DMASK = SCSI_CLK_CLKEN_MASK;
+ CLK_DIST_AMASK = 0x00u;
+#endif /* SCSI_CLK__CFG3 */
+ /* Clear mask of bus clock. */
+ CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);
+
+ /* If clock is currently enabled, disable it if async or going from N-to-1*/
+ if (((SCSI_CLK_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u))
+ {
+#if HAS_CLKDIST_LD_DISABLE
+ CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);
+ CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD;
+
+ /* Wait for clock to be disabled */
+ while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
+#endif /* HAS_CLKDIST_LD_DISABLE */
+
+ SCSI_CLK_CLKEN &= (uint8)(~SCSI_CLK_CLKEN_MASK);
+
+#if HAS_CLKDIST_LD_DISABLE
+ /* Clear the disable bit */
+ CLK_DIST_LD = 0x00u;
+#endif /* HAS_CLKDIST_LD_DISABLE */
+ }
+ }
+
+ /* Load divide value. */
+ if ((SCSI_CLK_CLKEN & SCSI_CLK_CLKEN_MASK) != 0u)
+ {
+ /* If the clock is still enabled, use the shadow registers */
+ CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider);
+
+ CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u));
+ while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
+ }
+ else
+ {
+ /* If the clock is disabled, set the divider directly */
+ CY_SET_REG16(SCSI_CLK_DIV_PTR, clkDivider);
+ SCSI_CLK_CLKEN |= enabled;
+ }
+ }
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_GetDividerRegister
+********************************************************************************
+*
+* Summary:
+* Gets the clock divider register value.
+*
+* Parameters:
+* None
+*
+* Returns:
+* Divide value of the clock minus 1. For example, if the clock is set to
+* divide by 2, the return value will be 1.
+*
+*******************************************************************************/
+uint16 SCSI_CLK_GetDividerRegister(void)
+{
+ return CY_GET_REG16(SCSI_CLK_DIV_PTR);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_SetModeRegister
+********************************************************************************
+*
+* Summary:
+* Sets flags that control the operating mode of the clock. This function only
+* changes flags from 0 to 1; flags that are already 1 will remain unchanged.
+* To clear flags, use the ClearModeRegister function. The clock must be
+* disabled before changing the mode.
+*
+* Parameters:
+* clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5,
+* clkMode should be a set of the following optional bits or'ed together.
+* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will
+* occur when the divider count reaches half of the divide
+* value.
+* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock
+* is asserted for approximately half of its period. When
+* disabled, the output clock is asserted for one period of the
+* source clock.
+* - CYCLK_SYNC Enable output synchronization to master clock. This should
+* be enabled for all synchronous clocks.
+* See the Technical Reference Manual for details about setting the mode of
+* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.
+*
+* Returns:
+* None
+*
+*******************************************************************************/
+void SCSI_CLK_SetModeRegister(uint8 modeBitMask)
+{
+ SCSI_CLK_MOD_SRC |= modeBitMask & (uint8)SCSI_CLK_MODE_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_ClearModeRegister
+********************************************************************************
+*
+* Summary:
+* Clears flags that control the operating mode of the clock. This function
+* only changes flags from 1 to 0; flags that are already 0 will remain
+* unchanged. To set flags, use the SetModeRegister function. The clock must be
+* disabled before changing the mode.
+*
+* Parameters:
+* clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5,
+* clkMode should be a set of the following optional bits or'ed together.
+* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will
+* occur when the divider count reaches half of the divide
+* value.
+* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock
+* is asserted for approximately half of its period. When
+* disabled, the output clock is asserted for one period of the
+* source clock.
+* - CYCLK_SYNC Enable output synchronization to master clock. This should
+* be enabled for all synchronous clocks.
+* See the Technical Reference Manual for details about setting the mode of
+* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.
+*
+* Returns:
+* None
+*
+*******************************************************************************/
+void SCSI_CLK_ClearModeRegister(uint8 modeBitMask)
+{
+ SCSI_CLK_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(SCSI_CLK_MODE_MASK));
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_GetModeRegister
+********************************************************************************
+*
+* Summary:
+* Gets the clock mode register value.
+*
+* Parameters:
+* None
+*
+* Returns:
+* Bit mask representing the enabled mode bits. See the SetModeRegister and
+* ClearModeRegister descriptions for details about the mode bits.
+*
+*******************************************************************************/
+uint8 SCSI_CLK_GetModeRegister(void)
+{
+ return SCSI_CLK_MOD_SRC & (uint8)(SCSI_CLK_MODE_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_SetSourceRegister
+********************************************************************************
+*
+* Summary:
+* Sets the input source of the clock. The clock must be disabled before
+* changing the source. The old and new clock sources must be running.
+*
+* Parameters:
+* clkSource: For PSoC 3 and PSoC 5 devices, clkSource should be one of the
+* following input sources:
+* - CYCLK_SRC_SEL_SYNC_DIG
+* - CYCLK_SRC_SEL_IMO
+* - CYCLK_SRC_SEL_XTALM
+* - CYCLK_SRC_SEL_ILO
+* - CYCLK_SRC_SEL_PLL
+* - CYCLK_SRC_SEL_XTALK
+* - CYCLK_SRC_SEL_DSI_G
+* - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A
+* See the Technical Reference Manual for details on clock sources.
+*
+* Returns:
+* None
+*
+*******************************************************************************/
+void SCSI_CLK_SetSourceRegister(uint8 clkSource)
+{
+ uint16 currDiv = SCSI_CLK_GetDividerRegister();
+ uint8 oldSrc = SCSI_CLK_GetSourceRegister();
+
+ if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) &&
+ (clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))
+ {
+ /* Switching to Master and divider is 1, set SSS, which will output master, */
+ /* then set the source so we are consistent. */
+ SCSI_CLK_MOD_SRC |= CYCLK_SSS;
+ SCSI_CLK_MOD_SRC =
+ (SCSI_CLK_MOD_SRC & (uint8)(~SCSI_CLK_SRC_SEL_MSK)) | clkSource;
+ }
+ else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) &&
+ (clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))
+ {
+ /* Switching from Master to not and divider is 1, set source, so we don't */
+ /* lock when we clear SSS. */
+ SCSI_CLK_MOD_SRC =
+ (SCSI_CLK_MOD_SRC & (uint8)(~SCSI_CLK_SRC_SEL_MSK)) | clkSource;
+ SCSI_CLK_MOD_SRC &= (uint8)(~CYCLK_SSS);
+ }
+ else
+ {
+ SCSI_CLK_MOD_SRC =
+ (SCSI_CLK_MOD_SRC & (uint8)(~SCSI_CLK_SRC_SEL_MSK)) | clkSource;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_GetSourceRegister
+********************************************************************************
+*
+* Summary:
+* Gets the input source of the clock.
+*
+* Parameters:
+* None
+*
+* Returns:
+* The input source of the clock. See SetSourceRegister for details.
+*
+*******************************************************************************/
+uint8 SCSI_CLK_GetSourceRegister(void)
+{
+ return SCSI_CLK_MOD_SRC & SCSI_CLK_SRC_SEL_MSK;
+}
+
+
+#if defined(SCSI_CLK__CFG3)
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_SetPhaseRegister
+********************************************************************************
+*
+* Summary:
+* Sets the phase delay of the analog clock. This function is only available
+* for analog clocks. The clock must be disabled before changing the phase
+* delay to avoid glitches.
+*
+* Parameters:
+* clkPhase: Amount to delay the phase of the clock, in 1.0ns increments.
+* clkPhase must be from 1 to 11 inclusive. Other values, including 0,
+* disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11
+* produces a 10ns delay.
+*
+* Returns:
+* None
+*
+*******************************************************************************/
+void SCSI_CLK_SetPhaseRegister(uint8 clkPhase)
+{
+ SCSI_CLK_PHASE = clkPhase & SCSI_CLK_PHASE_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_GetPhase
+********************************************************************************
+*
+* Summary:
+* Gets the phase delay of the analog clock. This function is only available
+* for analog clocks.
+*
+* Parameters:
+* None
+*
+* Returns:
+* Phase of the analog clock. See SetPhaseRegister for details.
+*
+*******************************************************************************/
+uint8 SCSI_CLK_GetPhaseRegister(void)
+{
+ return SCSI_CLK_PHASE & SCSI_CLK_PHASE_MASK;
+}
+
+#endif /* SCSI_CLK__CFG3 */
+
+
+/* [] END OF FILE */
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_CLK.h
+* Version 2.10
+*
+* Description:
+* Provides the function and constant definitions for the clock component.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_CLOCK_SCSI_CLK_H)
+#define CY_CLOCK_SCSI_CLK_H
+
+#include <cytypes.h>
+#include <cyfitter.h>
+
+
+/***************************************
+* Conditional Compilation Parameters
+***************************************/
+
+/* Check to see if required defines such as CY_PSOC5LP are available */
+/* They are defined starting with cy_boot v3.0 */
+#if !defined (CY_PSOC5LP)
+ #error Component cy_clock_v2_10 requires cy_boot v3.0 or later
+#endif /* (CY_PSOC5LP) */
+
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+void SCSI_CLK_Start(void) ;
+void SCSI_CLK_Stop(void) ;
+
+#if(CY_PSOC3 || CY_PSOC5LP)
+void SCSI_CLK_StopBlock(void) ;
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */
+
+void SCSI_CLK_StandbyPower(uint8 state) ;
+void SCSI_CLK_SetDividerRegister(uint16 clkDivider, uint8 restart)
+ ;
+uint16 SCSI_CLK_GetDividerRegister(void) ;
+void SCSI_CLK_SetModeRegister(uint8 modeBitMask) ;
+void SCSI_CLK_ClearModeRegister(uint8 modeBitMask) ;
+uint8 SCSI_CLK_GetModeRegister(void) ;
+void SCSI_CLK_SetSourceRegister(uint8 clkSource) ;
+uint8 SCSI_CLK_GetSourceRegister(void) ;
+#if defined(SCSI_CLK__CFG3)
+void SCSI_CLK_SetPhaseRegister(uint8 clkPhase) ;
+uint8 SCSI_CLK_GetPhaseRegister(void) ;
+#endif /* defined(SCSI_CLK__CFG3) */
+
+#define SCSI_CLK_Enable() SCSI_CLK_Start()
+#define SCSI_CLK_Disable() SCSI_CLK_Stop()
+#define SCSI_CLK_SetDivider(clkDivider) SCSI_CLK_SetDividerRegister(clkDivider, 1u)
+#define SCSI_CLK_SetDividerValue(clkDivider) SCSI_CLK_SetDividerRegister((clkDivider) - 1u, 1u)
+#define SCSI_CLK_SetMode(clkMode) SCSI_CLK_SetModeRegister(clkMode)
+#define SCSI_CLK_SetSource(clkSource) SCSI_CLK_SetSourceRegister(clkSource)
+#if defined(SCSI_CLK__CFG3)
+#define SCSI_CLK_SetPhase(clkPhase) SCSI_CLK_SetPhaseRegister(clkPhase)
+#define SCSI_CLK_SetPhaseValue(clkPhase) SCSI_CLK_SetPhaseRegister((clkPhase) + 1u)
+#endif /* defined(SCSI_CLK__CFG3) */
+
+
+/***************************************
+* Registers
+***************************************/
+
+/* Register to enable or disable the clock */
+#define SCSI_CLK_CLKEN (* (reg8 *) SCSI_CLK__PM_ACT_CFG)
+#define SCSI_CLK_CLKEN_PTR ((reg8 *) SCSI_CLK__PM_ACT_CFG)
+
+/* Register to enable or disable the clock */
+#define SCSI_CLK_CLKSTBY (* (reg8 *) SCSI_CLK__PM_STBY_CFG)
+#define SCSI_CLK_CLKSTBY_PTR ((reg8 *) SCSI_CLK__PM_STBY_CFG)
+
+/* Clock LSB divider configuration register. */
+#define SCSI_CLK_DIV_LSB (* (reg8 *) SCSI_CLK__CFG0)
+#define SCSI_CLK_DIV_LSB_PTR ((reg8 *) SCSI_CLK__CFG0)
+#define SCSI_CLK_DIV_PTR ((reg16 *) SCSI_CLK__CFG0)
+
+/* Clock MSB divider configuration register. */
+#define SCSI_CLK_DIV_MSB (* (reg8 *) SCSI_CLK__CFG1)
+#define SCSI_CLK_DIV_MSB_PTR ((reg8 *) SCSI_CLK__CFG1)
+
+/* Mode and source configuration register */
+#define SCSI_CLK_MOD_SRC (* (reg8 *) SCSI_CLK__CFG2)
+#define SCSI_CLK_MOD_SRC_PTR ((reg8 *) SCSI_CLK__CFG2)
+
+#if defined(SCSI_CLK__CFG3)
+/* Analog clock phase configuration register */
+#define SCSI_CLK_PHASE (* (reg8 *) SCSI_CLK__CFG3)
+#define SCSI_CLK_PHASE_PTR ((reg8 *) SCSI_CLK__CFG3)
+#endif /* defined(SCSI_CLK__CFG3) */
+
+
+/**************************************
+* Register Constants
+**************************************/
+
+/* Power manager register masks */
+#define SCSI_CLK_CLKEN_MASK SCSI_CLK__PM_ACT_MSK
+#define SCSI_CLK_CLKSTBY_MASK SCSI_CLK__PM_STBY_MSK
+
+/* CFG2 field masks */
+#define SCSI_CLK_SRC_SEL_MSK SCSI_CLK__CFG2_SRC_SEL_MASK
+#define SCSI_CLK_MODE_MASK (~(SCSI_CLK_SRC_SEL_MSK))
+
+#if defined(SCSI_CLK__CFG3)
+/* CFG3 phase mask */
+#define SCSI_CLK_PHASE_MASK SCSI_CLK__CFG3_PHASE_DLY_MASK
+#endif /* defined(SCSI_CLK__CFG3) */
+
+#endif /* CY_CLOCK_SCSI_CLK_H */
+
+
+/* [] END OF FILE */
-/*******************************************************************************\r
-* File Name: SCSI_CTL_IO.c \r
-* Version 1.70\r
-*\r
-* Description:\r
-* This file contains API to enable firmware control of a Control Register.\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#include "SCSI_CTL_IO.h"\r
-\r
-#if !defined(SCSI_CTL_IO_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */\r
-\r
-/*******************************************************************************\r
-* Function Name: SCSI_CTL_IO_Write\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Write a byte to the Control Register.\r
-*\r
-* Parameters:\r
-* control: The value to be assigned to the Control Register.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-*******************************************************************************/\r
-void SCSI_CTL_IO_Write(uint8 control) \r
-{\r
- SCSI_CTL_IO_Control = control;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SCSI_CTL_IO_Read\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Reads the current value assigned to the Control Register.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* Returns the current value in the Control Register.\r
-*\r
-*******************************************************************************/\r
-uint8 SCSI_CTL_IO_Read(void) \r
-{\r
- return SCSI_CTL_IO_Control;\r
-}\r
-\r
-#endif /* End check for removal by optimization */\r
-\r
-\r
-/* [] END OF FILE */\r
+/*******************************************************************************
+* File Name: SCSI_CTL_PHASE.c
+* Version 1.70
+*
+* Description:
+* This file contains API to enable firmware control of a Control Register.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_CTL_PHASE.h"
+
+#if !defined(SCSI_CTL_PHASE_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */
+
+/*******************************************************************************
+* Function Name: SCSI_CTL_PHASE_Write
+********************************************************************************
+*
+* Summary:
+* Write a byte to the Control Register.
+*
+* Parameters:
+* control: The value to be assigned to the Control Register.
+*
+* Return:
+* None.
+*
+*******************************************************************************/
+void SCSI_CTL_PHASE_Write(uint8 control)
+{
+ SCSI_CTL_PHASE_Control = control;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CTL_PHASE_Read
+********************************************************************************
+*
+* Summary:
+* Reads the current value assigned to the Control Register.
+*
+* Parameters:
+* None.
+*
+* Return:
+* Returns the current value in the Control Register.
+*
+*******************************************************************************/
+uint8 SCSI_CTL_PHASE_Read(void)
+{
+ return SCSI_CTL_PHASE_Control;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */
-/*******************************************************************************\r
-* File Name: SCSI_CTL_IO.h \r
-* Version 1.70\r
-*\r
-* Description:\r
-* This file containts Control Register function prototypes and register defines\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#if !defined(CY_CONTROL_REG_SCSI_CTL_IO_H) /* CY_CONTROL_REG_SCSI_CTL_IO_H */\r
-#define CY_CONTROL_REG_SCSI_CTL_IO_H\r
-\r
-#include "cytypes.h"\r
-\r
-\r
-/***************************************\r
-* Function Prototypes \r
-***************************************/\r
-\r
-void SCSI_CTL_IO_Write(uint8 control) ;\r
-uint8 SCSI_CTL_IO_Read(void) ;\r
-\r
-\r
-/***************************************\r
-* Registers \r
-***************************************/\r
-\r
-/* Control Register */\r
-#define SCSI_CTL_IO_Control (* (reg8 *) SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG )\r
-#define SCSI_CTL_IO_Control_PTR ( (reg8 *) SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG )\r
-\r
-#endif /* End CY_CONTROL_REG_SCSI_CTL_IO_H */\r
-\r
-\r
-/* [] END OF FILE */\r
+/*******************************************************************************
+* File Name: SCSI_CTL_PHASE.h
+* Version 1.70
+*
+* Description:
+* This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_CONTROL_REG_SCSI_CTL_PHASE_H) /* CY_CONTROL_REG_SCSI_CTL_PHASE_H */
+#define CY_CONTROL_REG_SCSI_CTL_PHASE_H
+
+#include "cytypes.h"
+
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+void SCSI_CTL_PHASE_Write(uint8 control) ;
+uint8 SCSI_CTL_PHASE_Read(void) ;
+
+
+/***************************************
+* Registers
+***************************************/
+
+/* Control Register */
+#define SCSI_CTL_PHASE_Control (* (reg8 *) SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG )
+#define SCSI_CTL_PHASE_Control_PTR ( (reg8 *) SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG )
+
+#endif /* End CY_CONTROL_REG_SCSI_CTL_PHASE_H */
+
+
+/* [] END OF FILE */
#define SCSI_Out_BSY SCSI_Out__BSY__PC\r
#define SCSI_Out_ACK SCSI_Out__ACK__PC\r
#define SCSI_Out_RST SCSI_Out__RST__PC\r
-#define SCSI_Out_MSG SCSI_Out__MSG__PC\r
+#define SCSI_Out_MSG_raw SCSI_Out__MSG_raw__PC\r
#define SCSI_Out_SEL SCSI_Out__SEL__PC\r
-#define SCSI_Out_CD SCSI_Out__CD__PC\r
+#define SCSI_Out_CD_raw SCSI_Out__CD_raw__PC\r
#define SCSI_Out_REQ SCSI_Out__REQ__PC\r
#define SCSI_Out_IO_raw SCSI_Out__IO_raw__PC\r
\r
PROVIDE(__cy_heap_start = _end);\r
PROVIDE(__cy_region_num = (__cy_regions_end - __cy_regions) / 16);\r
PROVIDE(__cy_stack = ORIGIN(ram) + LENGTH(ram));\r
-PROVIDE(__cy_heap_end = __cy_stack - 0x4000);\r
+PROVIDE(__cy_heap_end = __cy_stack - 0x2000);\r
\r
\r
SECTIONS\r
.heap (NOLOAD) :\r
{\r
. = _end;\r
- . += 0x1000;\r
+ . += 0x0256;\r
__cy_heap_limit = .;\r
} >ram\r
\r
- .stack (__cy_stack - 0x4000) (NOLOAD) :\r
+ .stack (__cy_stack - 0x2000) (NOLOAD) :\r
{\r
__cy_stack_limit = .;\r
- . += 0x4000;\r
+ . += 0x2000;\r
} >ram\r
\r
/* Check if data + heap + stack exceeds RAM limit */\r
#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
+/* SCSI_CTL_PHASE */\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+\r
/* USBFS_arb_int */\r
#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
/* SDCard_BSPIM */\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB06_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB06_ST\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB06_CTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB06_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB06_MSK\r
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB07_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB07_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB07_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB07_ST\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK\r
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB07_CTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB07_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB07_MSK\r
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST\r
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_RxStsReg__4__POS 4\r
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
#define SDCard_BSPIM_RxStsReg__6__POS 6\r
#define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB07_MSK\r
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB07_ST\r
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB04_MSK\r
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB04_ST\r
#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u\r
#define SDCard_BSPIM_TxStsReg__0__POS 0\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
#define SDCard_BSPIM_TxStsReg__1__POS 1\r
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u\r
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_TxStsReg__4__POS 4\r
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB05_MSK\r
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB05_ST\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB06_07_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB06_07_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB06_07_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB06_07_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB06_07_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB06_07_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB06_A0_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB06_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB06_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB06_D0_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB06_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB06_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB06_F0_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB06_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB06_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK\r
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB07_08_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB07_08_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB07_08_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB07_08_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB07_08_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB07_08_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB07_A0_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB07_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB07_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB07_D0_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB07_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB07_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB07_F0_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB07_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB07_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
\r
/* USBFS_dp_int */\r
#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
-/* SCSI_CTL_IO */\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__0__MASK 0x01u\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
-\r
/* SCSI_In_DBx */\r
#define SCSI_In_DBx__0__AG CYREG_PRT12_AG\r
#define SCSI_In_DBx__0__BIE CYREG_PRT12_BIE\r
#define SD_Data_Clk__PM_STBY_MSK 0x01u\r
\r
/* SD_Init_Clk */\r
-#define SD_Init_Clk__CFG0 CYREG_CLKDIST_DCFG1_CFG0\r
-#define SD_Init_Clk__CFG1 CYREG_CLKDIST_DCFG1_CFG1\r
-#define SD_Init_Clk__CFG2 CYREG_CLKDIST_DCFG1_CFG2\r
+#define SD_Init_Clk__CFG0 CYREG_CLKDIST_DCFG2_CFG0\r
+#define SD_Init_Clk__CFG1 CYREG_CLKDIST_DCFG2_CFG1\r
+#define SD_Init_Clk__CFG2 CYREG_CLKDIST_DCFG2_CFG2\r
#define SD_Init_Clk__CFG2_SRC_SEL_MASK 0x07u\r
-#define SD_Init_Clk__INDEX 0x01u\r
+#define SD_Init_Clk__INDEX 0x02u\r
#define SD_Init_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2\r
-#define SD_Init_Clk__PM_ACT_MSK 0x02u\r
+#define SD_Init_Clk__PM_ACT_MSK 0x04u\r
#define SD_Init_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
-#define SD_Init_Clk__PM_STBY_MSK 0x02u\r
+#define SD_Init_Clk__PM_STBY_MSK 0x04u\r
\r
/* scsiTarget */\r
#define scsiTarget_StatusReg__0__MASK 0x01u\r
#define scsiTarget_StatusReg__0__POS 0\r
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL\r
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB14_15_ST\r
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST\r
#define scsiTarget_StatusReg__1__MASK 0x02u\r
#define scsiTarget_StatusReg__1__POS 1\r
#define scsiTarget_StatusReg__2__MASK 0x04u\r
#define scsiTarget_StatusReg__3__MASK 0x08u\r
#define scsiTarget_StatusReg__3__POS 3\r
#define scsiTarget_StatusReg__MASK 0x0Fu\r
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB14_MSK\r
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB14_ACTL\r
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB14_ST\r
-#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL\r
-#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB13_14_ST\r
-#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB13_MSK\r
-#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL\r
-#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL\r
-#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB13_ACTL\r
-#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB13_ST_CTL\r
-#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB13_ST_CTL\r
-#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB13_ST\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL\r
-#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL\r
-#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL\r
-#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK\r
-#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK\r
-#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK\r
-#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK\r
-#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL\r
-#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB13_CTL\r
-#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL\r
-#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB13_CTL\r
-#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL\r
-#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL\r
-#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB13_MSK\r
-#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL\r
-#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB13_14_A0\r
-#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB13_14_A1\r
-#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB13_14_D0\r
-#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB13_14_D1\r
-#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL\r
-#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB13_14_F0\r
-#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB13_14_F1\r
-#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB13_A0_A1\r
-#define scsiTarget_datapath__A0_REG CYREG_B0_UDB13_A0\r
-#define scsiTarget_datapath__A1_REG CYREG_B0_UDB13_A1\r
-#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB13_D0_D1\r
-#define scsiTarget_datapath__D0_REG CYREG_B0_UDB13_D0\r
-#define scsiTarget_datapath__D1_REG CYREG_B0_UDB13_D1\r
-#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB13_ACTL\r
-#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB13_F0_F1\r
-#define scsiTarget_datapath__F0_REG CYREG_B0_UDB13_F0\r
-#define scsiTarget_datapath__F1_REG CYREG_B0_UDB13_F1\r
-#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL\r
-#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL\r
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB12_MSK\r
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB12_ST\r
+#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
+#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST\r
+#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB03_MSK\r
+#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
+#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB03_ST_CTL\r
+#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB03_ST_CTL\r
+#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB03_ST\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL\r
+#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
+#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL\r
+#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK\r
+#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
+#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK\r
+#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
+#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
+#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB03_CTL\r
+#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL\r
+#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB03_CTL\r
+#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL\r
+#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB03_MSK\r
+#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB03_04_A0\r
+#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB03_04_A1\r
+#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB03_04_D0\r
+#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB03_04_D1\r
+#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
+#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB03_04_F0\r
+#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB03_04_F1\r
+#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB03_A0_A1\r
+#define scsiTarget_datapath__A0_REG CYREG_B0_UDB03_A0\r
+#define scsiTarget_datapath__A1_REG CYREG_B0_UDB03_A1\r
+#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB03_D0_D1\r
+#define scsiTarget_datapath__D0_REG CYREG_B0_UDB03_D0\r
+#define scsiTarget_datapath__D1_REG CYREG_B0_UDB03_D1\r
+#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
+#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB03_F0_F1\r
+#define scsiTarget_datapath__F0_REG CYREG_B0_UDB03_F0\r
+#define scsiTarget_datapath__F1_REG CYREG_B0_UDB03_F1\r
+#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
\r
/* SD_Clk_Ctl */\r
#define SD_Clk_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
#define SD_Clk_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL\r
#define SD_Clk_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL\r
\r
/* USBFS_ep_0 */\r
#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define SCSI_ATN__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
#define SCSI_ATN__SLW CYREG_PRT12_SLW\r
\r
+/* SCSI_CLK */\r
+#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0\r
+#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1\r
+#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2\r
+#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u\r
+#define SCSI_CLK__INDEX 0x01u\r
+#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2\r
+#define SCSI_CLK__PM_ACT_MSK 0x02u\r
+#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
+#define SCSI_CLK__PM_STBY_MSK 0x02u\r
+\r
/* SCSI_Out */\r
#define SCSI_Out__0__AG CYREG_PRT4_AG\r
#define SCSI_Out__0__AMUX CYREG_PRT4_AMUX\r
#define SCSI_Out__BSY__PS CYREG_PRT0_PS\r
#define SCSI_Out__BSY__SHIFT 7\r
#define SCSI_Out__BSY__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__CD__AG CYREG_PRT0_AG\r
-#define SCSI_Out__CD__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__CD__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__CD__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__CD__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__CD__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__CD__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__CD__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__CD__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__CD__DR CYREG_PRT0_DR\r
-#define SCSI_Out__CD__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__CD__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__CD__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__CD__MASK 0x04u\r
-#define SCSI_Out__CD__PC CYREG_PRT0_PC2\r
-#define SCSI_Out__CD__PORT 0u\r
-#define SCSI_Out__CD__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__CD__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__CD__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__CD__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__CD__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__CD__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__CD__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__CD__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__CD__PS CYREG_PRT0_PS\r
-#define SCSI_Out__CD__SHIFT 2\r
-#define SCSI_Out__CD__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__CD_raw__AG CYREG_PRT0_AG\r
+#define SCSI_Out__CD_raw__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__CD_raw__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__CD_raw__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__CD_raw__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__CD_raw__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__CD_raw__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__CD_raw__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__CD_raw__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__CD_raw__DR CYREG_PRT0_DR\r
+#define SCSI_Out__CD_raw__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__CD_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__CD_raw__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__CD_raw__MASK 0x04u\r
+#define SCSI_Out__CD_raw__PC CYREG_PRT0_PC2\r
+#define SCSI_Out__CD_raw__PORT 0u\r
+#define SCSI_Out__CD_raw__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__CD_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__CD_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__CD_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__CD_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__CD_raw__PS CYREG_PRT0_PS\r
+#define SCSI_Out__CD_raw__SHIFT 2\r
+#define SCSI_Out__CD_raw__SLW CYREG_PRT0_SLW\r
#define SCSI_Out__DBP_raw__AG CYREG_PRT4_AG\r
#define SCSI_Out__DBP_raw__AMUX CYREG_PRT4_AMUX\r
#define SCSI_Out__DBP_raw__BIE CYREG_PRT4_BIE\r
#define SCSI_Out__IO_raw__PS CYREG_PRT0_PS\r
#define SCSI_Out__IO_raw__SHIFT 0\r
#define SCSI_Out__IO_raw__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__MSG__AG CYREG_PRT0_AG\r
-#define SCSI_Out__MSG__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__MSG__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__MSG__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__MSG__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__MSG__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__MSG__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__MSG__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__MSG__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__MSG__DR CYREG_PRT0_DR\r
-#define SCSI_Out__MSG__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__MSG__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__MSG__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__MSG__MASK 0x10u\r
-#define SCSI_Out__MSG__PC CYREG_PRT0_PC4\r
-#define SCSI_Out__MSG__PORT 0u\r
-#define SCSI_Out__MSG__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__MSG__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__MSG__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__MSG__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__MSG__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__MSG__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__MSG__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__MSG__PS CYREG_PRT0_PS\r
-#define SCSI_Out__MSG__SHIFT 4\r
-#define SCSI_Out__MSG__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__MSG_raw__AG CYREG_PRT0_AG\r
+#define SCSI_Out__MSG_raw__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__MSG_raw__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__MSG_raw__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__MSG_raw__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__MSG_raw__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__MSG_raw__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__MSG_raw__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__MSG_raw__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__MSG_raw__DR CYREG_PRT0_DR\r
+#define SCSI_Out__MSG_raw__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__MSG_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__MSG_raw__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__MSG_raw__MASK 0x10u\r
+#define SCSI_Out__MSG_raw__PC CYREG_PRT0_PC4\r
+#define SCSI_Out__MSG_raw__PORT 0u\r
+#define SCSI_Out__MSG_raw__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__MSG_raw__PS CYREG_PRT0_PS\r
+#define SCSI_Out__MSG_raw__SHIFT 4\r
+#define SCSI_Out__MSG_raw__SLW CYREG_PRT0_SLW\r
#define SCSI_Out__REQ__AG CYREG_PRT0_AG\r
#define SCSI_Out__REQ__AMUX CYREG_PRT0_AMUX\r
#define SCSI_Out__REQ__BIE CYREG_PRT0_BIE\r
#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG\r
#define CYDEV_DMA_CHANNELS_AVAILABLE 24u\r
#define CYDEV_ECC_ENABLE 0\r
-#define CYDEV_HEAP_SIZE 0x1000\r
+#define CYDEV_HEAP_SIZE 0x0256\r
#define CYDEV_INSTRUCT_CACHE_ENABLED 1\r
#define CYDEV_INTR_RISING 0x00000000u\r
#define CYDEV_PROJ_TYPE 2\r
#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3\r
#define CYDEV_PROJ_TYPE_STANDARD 0\r
#define CYDEV_PROTECTION_ENABLE 0\r
-#define CYDEV_STACK_SIZE 0x4000\r
+#define CYDEV_STACK_SIZE 0x2000\r
#define CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP \r
#define CYDEV_USE_BUNDLED_CMSIS 1\r
#define CYDEV_VARIABLE_VDDA 0\r
/* Configure Digital Clocks based on settings from Clock DWR */\r
CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0), 0x0001u);\r
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x10u);\r
- CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x001Du);\r
- CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x19u);\r
+ CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0001u);\r
+ CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x18u);\r
+ CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x001Du);\r
+ CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x19u);\r
\r
/* Configure ILO based on settings from Clock DWR */\r
CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u);\r
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_UCFG), 0x00u);\r
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u);\r
\r
- CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x02u)));\r
+ CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x06u)));\r
}\r
\r
\r
{\r
/* IOPINS0_0 Address: CYREG_PRT0_DM0 Size (bytes): 8 */\r
static const uint8 CYCODE BS_IOPINS0_0_VAL[] = {\r
- 0x00u, 0xFFu, 0xFFu, 0x00u, 0x03u, 0x00u, 0x00u, 0x00u};\r
+ 0x00u, 0xFFu, 0xFFu, 0x00u, 0x17u, 0x00u, 0x00u, 0x00u};\r
\r
/* IOPINS0_7 Address: CYREG_PRT12_DR Size (bytes): 10 */\r
static const uint8 CYCODE BS_IOPINS0_7_VAL[] = {\r
0x40004502u, /* Base address: 0x40004500 Count: 2 */\r
0x4000520Au, /* Base address: 0x40005200 Count: 10 */\r
0x40006402u, /* Base address: 0x40006400 Count: 2 */\r
- 0x40010101u, /* Base address: 0x40010100 Count: 1 */\r
- 0x40010308u, /* Base address: 0x40010300 Count: 8 */\r
- 0x40010442u, /* Base address: 0x40010400 Count: 66 */\r
- 0x4001053Cu, /* Base address: 0x40010500 Count: 60 */\r
- 0x40010604u, /* Base address: 0x40010600 Count: 4 */\r
+ 0x40010048u, /* Base address: 0x40010000 Count: 72 */\r
+ 0x4001012Cu, /* Base address: 0x40010100 Count: 44 */\r
+ 0x40010235u, /* Base address: 0x40010200 Count: 53 */\r
+ 0x4001034Fu, /* Base address: 0x40010300 Count: 79 */\r
+ 0x40010448u, /* Base address: 0x40010400 Count: 72 */\r
+ 0x40010555u, /* Base address: 0x40010500 Count: 85 */\r
+ 0x40010606u, /* Base address: 0x40010600 Count: 6 */\r
0x40010747u, /* Base address: 0x40010700 Count: 71 */\r
- 0x40010908u, /* Base address: 0x40010900 Count: 8 */\r
- 0x40010A44u, /* Base address: 0x40010A00 Count: 68 */\r
- 0x40010B40u, /* Base address: 0x40010B00 Count: 64 */\r
- 0x40010C35u, /* Base address: 0x40010C00 Count: 53 */\r
- 0x40010D49u, /* Base address: 0x40010D00 Count: 73 */\r
- 0x40010E43u, /* Base address: 0x40010E00 Count: 67 */\r
- 0x40010F2Fu, /* Base address: 0x40010F00 Count: 47 */\r
+ 0x40010901u, /* Base address: 0x40010900 Count: 1 */\r
+ 0x40010B0Cu, /* Base address: 0x40010B00 Count: 12 */\r
+ 0x40010C3Bu, /* Base address: 0x40010C00 Count: 59 */\r
+ 0x40010D39u, /* Base address: 0x40010D00 Count: 57 */\r
+ 0x40010F04u, /* Base address: 0x40010F00 Count: 4 */\r
0x40011504u, /* Base address: 0x40011500 Count: 4 */\r
- 0x40011648u, /* Base address: 0x40011600 Count: 72 */\r
- 0x40011740u, /* Base address: 0x40011700 Count: 64 */\r
- 0x40011904u, /* Base address: 0x40011900 Count: 4 */\r
- 0x4001400Bu, /* Base address: 0x40014000 Count: 11 */\r
+ 0x4001164Du, /* Base address: 0x40011600 Count: 77 */\r
+ 0x4001173Fu, /* Base address: 0x40011700 Count: 63 */\r
+ 0x40011901u, /* Base address: 0x40011900 Count: 1 */\r
+ 0x4001400Cu, /* Base address: 0x40014000 Count: 12 */\r
0x4001410Fu, /* Base address: 0x40014100 Count: 15 */\r
- 0x40014207u, /* Base address: 0x40014200 Count: 7 */\r
- 0x40014303u, /* Base address: 0x40014300 Count: 3 */\r
- 0x4001440Cu, /* Base address: 0x40014400 Count: 12 */\r
- 0x40014516u, /* Base address: 0x40014500 Count: 22 */\r
- 0x40014608u, /* Base address: 0x40014600 Count: 8 */\r
- 0x40014708u, /* Base address: 0x40014700 Count: 8 */\r
- 0x4001480Au, /* Base address: 0x40014800 Count: 10 */\r
- 0x4001490Bu, /* Base address: 0x40014900 Count: 11 */\r
- 0x40014C01u, /* Base address: 0x40014C00 Count: 1 */\r
- 0x40015006u, /* Base address: 0x40015000 Count: 6 */\r
+ 0x4001420Bu, /* Base address: 0x40014200 Count: 11 */\r
+ 0x40014306u, /* Base address: 0x40014300 Count: 6 */\r
+ 0x4001440Eu, /* Base address: 0x40014400 Count: 14 */\r
+ 0x40014513u, /* Base address: 0x40014500 Count: 19 */\r
+ 0x4001460Au, /* Base address: 0x40014600 Count: 10 */\r
+ 0x40014703u, /* Base address: 0x40014700 Count: 3 */\r
+ 0x4001480Du, /* Base address: 0x40014800 Count: 13 */\r
+ 0x40014908u, /* Base address: 0x40014900 Count: 8 */\r
+ 0x40014C02u, /* Base address: 0x40014C00 Count: 2 */\r
+ 0x4001500Au, /* Base address: 0x40015000 Count: 10 */\r
0x40015101u, /* Base address: 0x40015100 Count: 1 */\r
};\r
\r
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {\r
{0x36u, 0x02u},\r
{0x7Eu, 0x02u},\r
- {0x00u, 0x01u},\r
- {0x01u, 0x03u},\r
+ {0x00u, 0x12u},\r
+ {0x01u, 0x01u},\r
{0x18u, 0x04u},\r
- {0x19u, 0x0Cu},\r
+ {0x19u, 0x08u},\r
{0x1Cu, 0x61u},\r
- {0x20u, 0x98u},\r
- {0x21u, 0x38u},\r
+ {0x20u, 0xA8u},\r
+ {0x21u, 0xC8u},\r
{0x30u, 0x03u},\r
- {0x31u, 0x05u},\r
+ {0x31u, 0x06u},\r
{0x7Cu, 0x40u},\r
- {0x3Du, 0x03u},\r
- {0x86u, 0x0Fu},\r
- {0xE2u, 0x80u},\r
- {0x81u, 0x40u},\r
- {0x85u, 0x04u},\r
- {0xA0u, 0x04u},\r
- {0xACu, 0x04u},\r
- {0xE2u, 0x08u},\r
- {0xE6u, 0x25u},\r
- {0xEAu, 0x01u},\r
- {0xEEu, 0x02u},\r
- {0x07u, 0x04u},\r
- {0x0Bu, 0x04u},\r
- {0x0Du, 0x04u},\r
- {0x0Fu, 0x02u},\r
- {0x13u, 0x03u},\r
- {0x19u, 0x04u},\r
- {0x1Bu, 0x01u},\r
- {0x31u, 0x07u},\r
- {0x56u, 0x08u},\r
- {0x59u, 0x04u},\r
- {0x5Bu, 0x04u},\r
- {0x5Cu, 0x90u},\r
- {0x5Du, 0x90u},\r
- {0x5Fu, 0x01u},\r
- {0x80u, 0xD6u},\r
- {0x81u, 0x2Cu},\r
- {0x84u, 0x17u},\r
- {0x86u, 0x28u},\r
- {0x88u, 0xD2u},\r
- {0x89u, 0x31u},\r
- {0x8Au, 0x04u},\r
- {0x8Bu, 0x42u},\r
- {0x8Cu, 0xD6u},\r
- {0x8Du, 0x2Cu},\r
- {0x91u, 0xC0u},\r
- {0x94u, 0x29u},\r
- {0x96u, 0x46u},\r
- {0x97u, 0x2Cu},\r
- {0x98u, 0x20u},\r
- {0x99u, 0x40u},\r
- {0x9Au, 0xD0u},\r
- {0x9Bu, 0x2Fu},\r
- {0x9Cu, 0x04u},\r
- {0x9Du, 0x24u},\r
- {0xA0u, 0xD6u},\r
- {0xA1u, 0x08u},\r
- {0xA3u, 0x10u},\r
- {0xA4u, 0xD0u},\r
- {0xA5u, 0x24u},\r
- {0xA6u, 0x06u},\r
- {0xA7u, 0x08u},\r
- {0xA8u, 0x21u},\r
- {0xA9u, 0x11u},\r
- {0xAAu, 0x8Eu},\r
- {0xABu, 0x8Eu},\r
- {0xACu, 0x02u},\r
- {0xADu, 0x2Cu},\r
- {0xB0u, 0x01u},\r
- {0xB1u, 0xC1u},\r
- {0xB2u, 0x0Fu},\r
- {0xB3u, 0x31u},\r
- {0xB4u, 0xF0u},\r
- {0xB5u, 0x0Fu},\r
- {0xB6u, 0x08u},\r
- {0xB8u, 0x08u},\r
- {0xB9u, 0x02u},\r
- {0xBAu, 0x20u},\r
- {0xBBu, 0x0Cu},\r
- {0xBEu, 0x41u},\r
- {0xD4u, 0x09u},\r
- {0xD8u, 0x0Bu},\r
- {0xD9u, 0x0Bu},\r
- {0xDBu, 0x0Bu},\r
- {0xDCu, 0x99u},\r
- {0xDDu, 0x90u},\r
- {0xDFu, 0x01u},\r
- {0x04u, 0x29u},\r
- {0x06u, 0x02u},\r
- {0x0Eu, 0x28u},\r
- {0x0Fu, 0x02u},\r
- {0x17u, 0x65u},\r
- {0x1Cu, 0x10u},\r
- {0x1Du, 0x48u},\r
- {0x1Eu, 0x28u},\r
- {0x1Fu, 0x09u},\r
- {0x21u, 0x02u},\r
- {0x23u, 0x40u},\r
- {0x24u, 0x08u},\r
- {0x25u, 0x10u},\r
- {0x26u, 0x02u},\r
- {0x27u, 0x38u},\r
- {0x29u, 0xC0u},\r
- {0x2Du, 0x02u},\r
- {0x2Fu, 0x2Au},\r
- {0x31u, 0x02u},\r
- {0x32u, 0x10u},\r
- {0x34u, 0x01u},\r
- {0x36u, 0x02u},\r
- {0x37u, 0x54u},\r
- {0x39u, 0x48u},\r
- {0x3Au, 0x10u},\r
- {0x3Cu, 0x81u},\r
- {0x3Du, 0x20u},\r
- {0x3Eu, 0x01u},\r
- {0x58u, 0x80u},\r
- {0x5Du, 0x98u},\r
- {0x5Eu, 0x02u},\r
- {0x60u, 0x02u},\r
- {0x62u, 0x80u},\r
- {0x65u, 0x08u},\r
- {0x66u, 0x04u},\r
- {0x67u, 0x02u},\r
- {0x7Eu, 0x80u},\r
- {0x89u, 0x02u},\r
- {0x8Cu, 0x20u},\r
- {0x91u, 0x48u},\r
- {0x92u, 0x20u},\r
- {0x9Au, 0x10u},\r
- {0xA0u, 0x04u},\r
- {0xA4u, 0x10u},\r
- {0xAEu, 0x10u},\r
- {0xB0u, 0x10u},\r
- {0xB6u, 0x10u},\r
- {0xC0u, 0xF0u},\r
- {0xC2u, 0xE0u},\r
- {0xC4u, 0xF0u},\r
- {0xCAu, 0xF0u},\r
- {0xCCu, 0xF5u},\r
- {0xCEu, 0xBEu},\r
- {0xD6u, 0xF8u},\r
- {0xD8u, 0x18u},\r
- {0xDEu, 0x80u},\r
- {0xE2u, 0x40u},\r
- {0xE6u, 0x20u},\r
- {0xEAu, 0x02u},\r
- {0xEEu, 0x08u},\r
- {0xD4u, 0x40u},\r
- {0xDBu, 0x0Bu},\r
- {0xDDu, 0x90u},\r
- {0xDFu, 0x01u},\r
- {0x04u, 0x20u},\r
- {0x06u, 0x02u},\r
- {0x07u, 0x60u},\r
- {0x0Eu, 0xA1u},\r
- {0x0Fu, 0x04u},\r
- {0x15u, 0x14u},\r
- {0x17u, 0x09u},\r
- {0x1Fu, 0x08u},\r
- {0x25u, 0x40u},\r
- {0x26u, 0x40u},\r
- {0x27u, 0x80u},\r
- {0x2Cu, 0x80u},\r
- {0x2Fu, 0x2Au},\r
- {0x36u, 0x02u},\r
- {0x37u, 0xA8u},\r
- {0x3Cu, 0x10u},\r
- {0x3Du, 0x80u},\r
- {0x3Eu, 0x01u},\r
- {0x3Fu, 0x04u},\r
- {0x45u, 0x88u},\r
- {0x46u, 0x40u},\r
- {0x47u, 0x20u},\r
- {0x4Cu, 0x04u},\r
- {0x4Du, 0x0Au},\r
- {0x4Fu, 0x06u},\r
- {0x55u, 0x20u},\r
- {0x56u, 0x84u},\r
- {0x61u, 0x20u},\r
- {0x62u, 0x08u},\r
- {0x63u, 0x01u},\r
- {0x65u, 0x80u},\r
- {0x6Cu, 0x10u},\r
- {0x6Du, 0x11u},\r
- {0x6Eu, 0x09u},\r
- {0x6Fu, 0x27u},\r
- {0x74u, 0xC0u},\r
- {0x76u, 0x02u},\r
- {0x78u, 0x02u},\r
- {0x7Eu, 0x80u},\r
- {0x81u, 0x48u},\r
- {0x90u, 0x18u},\r
- {0x92u, 0x80u},\r
- {0x93u, 0x40u},\r
- {0x94u, 0x20u},\r
- {0x96u, 0x01u},\r
- {0x98u, 0x23u},\r
- {0x9Bu, 0x38u},\r
- {0x9Du, 0x02u},\r
- {0x9Eu, 0x06u},\r
- {0x9Fu, 0x45u},\r
- {0xA0u, 0x04u},\r
- {0xA1u, 0x08u},\r
- {0xA2u, 0x90u},\r
- {0xA4u, 0x50u},\r
- {0xA6u, 0x01u},\r
- {0xA7u, 0x23u},\r
- {0xAAu, 0x40u},\r
- {0xACu, 0x80u},\r
- {0xB1u, 0x12u},\r
- {0xC0u, 0xF0u},\r
- {0xC2u, 0xF0u},\r
- {0xC4u, 0x70u},\r
- {0xCAu, 0xF0u},\r
- {0xCCu, 0xF0u},\r
- {0xCEu, 0xF0u},\r
- {0xD0u, 0xF0u},\r
- {0xD2u, 0x20u},\r
- {0xD8u, 0x1Eu},\r
- {0xDEu, 0x81u},\r
- {0xE8u, 0x40u},\r
- {0xEEu, 0x03u},\r
- {0x9Cu, 0x04u},\r
- {0xA7u, 0x40u},\r
- {0xAEu, 0x11u},\r
- {0xB0u, 0x80u},\r
- {0xB6u, 0x10u},\r
- {0xE8u, 0x40u},\r
- {0xEAu, 0x02u},\r
- {0xEEu, 0x01u},\r
- {0x04u, 0x24u},\r
- {0x06u, 0x12u},\r
- {0x07u, 0x03u},\r
- {0x0Au, 0x24u},\r
- {0x0Bu, 0x04u},\r
- {0x0Eu, 0x03u},\r
- {0x10u, 0x40u},\r
- {0x12u, 0x80u},\r
- {0x13u, 0x20u},\r
- {0x16u, 0x80u},\r
- {0x1Au, 0x18u},\r
- {0x1Bu, 0x24u},\r
- {0x1Fu, 0x18u},\r
- {0x21u, 0x40u},\r
- {0x22u, 0x20u},\r
- {0x25u, 0x24u},\r
- {0x26u, 0x04u},\r
- {0x27u, 0x12u},\r
- {0x29u, 0x80u},\r
- {0x2Au, 0x40u},\r
- {0x2Cu, 0x24u},\r
- {0x2Du, 0x24u},\r
- {0x2Eu, 0x09u},\r
- {0x2Fu, 0x09u},\r
- {0x30u, 0x07u},\r
- {0x31u, 0x80u},\r
- {0x33u, 0x40u},\r
- {0x34u, 0x38u},\r
- {0x35u, 0x07u},\r
- {0x36u, 0xC0u},\r
- {0x37u, 0x38u},\r
+ {0x33u, 0x01u},\r
+ {0x87u, 0x0Fu},\r
+ {0x03u, 0x08u},\r
+ {0x04u, 0x21u},\r
+ {0x06u, 0x42u},\r
+ {0x07u, 0x40u},\r
+ {0x08u, 0x42u},\r
+ {0x0Au, 0x28u},\r
+ {0x0Bu, 0x48u},\r
+ {0x0Cu, 0x0Du},\r
+ {0x0Fu, 0x06u},\r
+ {0x10u, 0x02u},\r
+ {0x11u, 0x01u},\r
+ {0x12u, 0x0Du},\r
+ {0x14u, 0x22u},\r
+ {0x15u, 0x48u},\r
+ {0x16u, 0x84u},\r
+ {0x17u, 0x12u},\r
+ {0x18u, 0xC0u},\r
+ {0x1Bu, 0x30u},\r
+ {0x1Cu, 0x0Du},\r
+ {0x1Du, 0x01u},\r
+ {0x20u, 0x0Du},\r
+ {0x21u, 0x48u},\r
+ {0x23u, 0x24u},\r
+ {0x24u, 0x0Du},\r
+ {0x25u, 0x01u},\r
+ {0x28u, 0x0Du},\r
+ {0x29u, 0x01u},\r
+ {0x2Cu, 0x10u},\r
+ {0x30u, 0x0Fu},\r
+ {0x33u, 0x01u},\r
+ {0x34u, 0xE0u},\r
+ {0x35u, 0x70u},\r
+ {0x36u, 0x10u},\r
+ {0x37u, 0x0Eu},\r
+ {0x38u, 0x20u},\r
+ {0x39u, 0x08u},\r
+ {0x3Au, 0x02u},\r
{0x3Eu, 0x40u},\r
- {0x3Fu, 0x05u},\r
- {0x58u, 0x04u},\r
+ {0x3Fu, 0x04u},\r
+ {0x58u, 0x0Bu},\r
{0x59u, 0x04u},\r
- {0x5Bu, 0x04u},\r
- {0x5Cu, 0x99u},\r
+ {0x5Cu, 0x19u},\r
{0x5Fu, 0x01u},\r
- {0x85u, 0x33u},\r
- {0x86u, 0xFFu},\r
- {0x87u, 0xCCu},\r
- {0x89u, 0xFFu},\r
- {0x8Du, 0x0Fu},\r
- {0x8Eu, 0xFFu},\r
- {0x8Fu, 0xF0u},\r
- {0x90u, 0x96u},\r
- {0x92u, 0x69u},\r
- {0x93u, 0xFFu},\r
- {0x94u, 0xFFu},\r
- {0x98u, 0x33u},\r
- {0x9Au, 0xCCu},\r
- {0x9Du, 0x96u},\r
- {0x9Fu, 0x69u},\r
- {0xA0u, 0x55u},\r
- {0xA1u, 0x55u},\r
- {0xA2u, 0xAAu},\r
- {0xA3u, 0xAAu},\r
- {0xA7u, 0xFFu},\r
- {0xACu, 0x0Fu},\r
- {0xAEu, 0xF0u},\r
- {0xB2u, 0xFFu},\r
- {0xB3u, 0xFFu},\r
- {0xBEu, 0x04u},\r
- {0xBFu, 0x04u},\r
+ {0x83u, 0x04u},\r
+ {0x84u, 0x02u},\r
+ {0x87u, 0x10u},\r
+ {0x8Cu, 0x01u},\r
+ {0x8Eu, 0x02u},\r
+ {0x8Fu, 0x08u},\r
+ {0x90u, 0x07u},\r
+ {0x95u, 0x01u},\r
+ {0x97u, 0x04u},\r
+ {0x99u, 0x01u},\r
+ {0x9Bu, 0x02u},\r
+ {0xA0u, 0x02u},\r
+ {0xA1u, 0x06u},\r
+ {0xA3u, 0x01u},\r
+ {0xA4u, 0x06u},\r
+ {0xAAu, 0x05u},\r
+ {0xABu, 0x07u},\r
+ {0xADu, 0x08u},\r
+ {0xAEu, 0x07u},\r
+ {0xAFu, 0x10u},\r
+ {0xB3u, 0x07u},\r
+ {0xB6u, 0x07u},\r
+ {0xB7u, 0x18u},\r
+ {0xBFu, 0x40u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
+ {0xDCu, 0x11u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x50u},\r
- {0x03u, 0x20u},\r
- {0x05u, 0x04u},\r
- {0x06u, 0x20u},\r
- {0x07u, 0x01u},\r
+ {0x00u, 0x20u},\r
+ {0x03u, 0x21u},\r
+ {0x05u, 0x08u},\r
+ {0x06u, 0x01u},\r
+ {0x08u, 0x40u},\r
{0x0Au, 0x64u},\r
- {0x0Eu, 0x80u},\r
- {0x0Fu, 0xA4u},\r
- {0x10u, 0xA5u},\r
- {0x13u, 0x40u},\r
- {0x14u, 0x40u},\r
- {0x15u, 0x40u},\r
- {0x18u, 0x40u},\r
- {0x1Au, 0x06u},\r
- {0x1Bu, 0x10u},\r
- {0x1Fu, 0x04u},\r
- {0x22u, 0x46u},\r
- {0x23u, 0x04u},\r
- {0x25u, 0x08u},\r
- {0x28u, 0x81u},\r
- {0x2Au, 0x10u},\r
- {0x2Bu, 0x20u},\r
- {0x2Cu, 0x40u},\r
- {0x2Eu, 0x04u},\r
- {0x30u, 0x42u},\r
+ {0x0Fu, 0x80u},\r
+ {0x10u, 0x88u},\r
+ {0x11u, 0x04u},\r
+ {0x12u, 0x02u},\r
+ {0x16u, 0x42u},\r
+ {0x17u, 0x24u},\r
+ {0x19u, 0x80u},\r
+ {0x1Au, 0x44u},\r
+ {0x1Fu, 0x80u},\r
+ {0x21u, 0x68u},\r
+ {0x24u, 0x20u},\r
+ {0x26u, 0x44u},\r
+ {0x27u, 0x20u},\r
+ {0x28u, 0x08u},\r
+ {0x2Au, 0x04u},\r
+ {0x2Bu, 0xC0u},\r
+ {0x2Du, 0x40u},\r
+ {0x2Fu, 0x84u},\r
+ {0x30u, 0x02u},\r
{0x31u, 0x20u},\r
- {0x32u, 0x40u},\r
- {0x36u, 0x40u},\r
- {0x37u, 0x01u},\r
- {0x39u, 0x10u},\r
- {0x3Bu, 0x04u},\r
- {0x3Du, 0x40u},\r
- {0x3Eu, 0x20u},\r
- {0x3Fu, 0x04u},\r
- {0x6Au, 0x40u},\r
- {0x6Fu, 0x01u},\r
- {0x8Cu, 0x40u},\r
- {0x90u, 0x10u},\r
- {0x91u, 0x50u},\r
- {0x93u, 0x40u},\r
- {0x96u, 0x08u},\r
- {0x97u, 0x0Cu},\r
- {0x99u, 0x04u},\r
- {0x9Cu, 0x40u},\r
- {0x9Fu, 0x01u},\r
- {0xA0u, 0xA2u},\r
- {0xA1u, 0x20u},\r
- {0xA3u, 0x20u},\r
- {0xA5u, 0x08u},\r
- {0xA6u, 0x02u},\r
- {0xA7u, 0x50u},\r
- {0xADu, 0x50u},\r
- {0xB2u, 0xC0u},\r
- {0xB3u, 0x08u},\r
- {0xB4u, 0x42u},\r
+ {0x33u, 0x44u},\r
+ {0x37u, 0x24u},\r
+ {0x38u, 0x20u},\r
+ {0x39u, 0x89u},\r
+ {0x3Du, 0x80u},\r
+ {0x3Fu, 0x09u},\r
+ {0x6Du, 0x40u},\r
+ {0x78u, 0x01u},\r
+ {0x81u, 0x2Cu},\r
+ {0x8Eu, 0x05u},\r
{0xC0u, 0xA7u},\r
- {0xC2u, 0x7Eu},\r
- {0xC4u, 0x9Fu},\r
- {0xCAu, 0xCFu},\r
- {0xCCu, 0x9Du},\r
- {0xCEu, 0x76u},\r
- {0xE2u, 0x40u},\r
- {0xEAu, 0x40u},\r
- {0xECu, 0x80u},\r
- {0x80u, 0x10u},\r
- {0x84u, 0x0Eu},\r
- {0x89u, 0x01u},\r
- {0x8Au, 0x0Eu},\r
- {0x8Bu, 0x92u},\r
- {0x8Cu, 0x04u},\r
- {0x8Du, 0x19u},\r
- {0x8Fu, 0xA4u},\r
- {0x90u, 0x0Cu},\r
- {0x91u, 0x08u},\r
- {0x92u, 0x01u},\r
- {0x94u, 0x02u},\r
- {0x96u, 0x04u},\r
- {0x97u, 0x3Fu},\r
- {0x9Au, 0x0Bu},\r
- {0xA4u, 0x04u},\r
- {0xA7u, 0x04u},\r
- {0xA9u, 0x26u},\r
- {0xABu, 0x99u},\r
- {0xADu, 0x40u},\r
- {0xB0u, 0x10u},\r
+ {0xC2u, 0x1Fu},\r
+ {0xC4u, 0xFFu},\r
+ {0xCAu, 0xB7u},\r
+ {0xCCu, 0x6Fu},\r
+ {0xCEu, 0xDFu},\r
+ {0xDEu, 0x01u},\r
+ {0xE0u, 0x04u},\r
+ {0x05u, 0x01u},\r
+ {0x37u, 0x01u},\r
+ {0x3Fu, 0x40u},\r
+ {0x59u, 0x04u},\r
+ {0x5Bu, 0x04u},\r
+ {0x5Fu, 0x01u},\r
+ {0x80u, 0x01u},\r
+ {0x83u, 0x04u},\r
+ {0x85u, 0x80u},\r
+ {0x88u, 0x04u},\r
+ {0x8Bu, 0x24u},\r
+ {0x8Fu, 0x20u},\r
+ {0x93u, 0x18u},\r
+ {0x95u, 0x24u},\r
+ {0x97u, 0x09u},\r
+ {0x9Fu, 0x03u},\r
+ {0xA1u, 0x24u},\r
+ {0xA3u, 0x12u},\r
+ {0xA9u, 0x40u},\r
+ {0xACu, 0x02u},\r
+ {0xB0u, 0x01u},\r
{0xB1u, 0x38u},\r
{0xB3u, 0x40u},\r
- {0xB4u, 0x0Eu},\r
- {0xB5u, 0x07u},\r
- {0xB6u, 0x01u},\r
- {0xB7u, 0x80u},\r
- {0xBEu, 0x41u},\r
- {0xBFu, 0x44u},\r
- {0xC0u, 0x26u},\r
- {0xC1u, 0x04u},\r
- {0xC2u, 0x50u},\r
- {0xC5u, 0xD2u},\r
- {0xC6u, 0xCEu},\r
- {0xC7u, 0x0Fu},\r
- {0xC8u, 0x1Fu},\r
+ {0xB4u, 0x04u},\r
+ {0xB5u, 0x80u},\r
+ {0xB6u, 0x02u},\r
+ {0xB7u, 0x07u},\r
+ {0xBEu, 0x51u},\r
+ {0xBFu, 0x14u},\r
+ {0xC0u, 0x61u},\r
+ {0xC1u, 0x03u},\r
+ {0xC2u, 0x20u},\r
+ {0xC5u, 0x2Cu},\r
+ {0xC6u, 0x0Du},\r
+ {0xC7u, 0xFEu},\r
+ {0xC8u, 0x37u},\r
{0xC9u, 0xFFu},\r
{0xCAu, 0xFFu},\r
{0xCBu, 0xFFu},\r
{0xD9u, 0x04u},\r
{0xDAu, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x99u},\r
- {0xDDu, 0x09u},\r
+ {0xDCu, 0x10u},\r
+ {0xDDu, 0x01u},\r
{0xDFu, 0x01u},\r
{0xE2u, 0xC0u},\r
{0xE6u, 0x80u},\r
{0xE8u, 0x40u},\r
{0xE9u, 0x40u},\r
{0xEEu, 0x08u},\r
- {0x00u, 0x80u},\r
- {0x02u, 0x80u},\r
- {0x03u, 0x28u},\r
- {0x04u, 0x08u},\r
- {0x07u, 0x10u},\r
- {0x09u, 0x20u},\r
- {0x0Bu, 0x60u},\r
- {0x12u, 0x10u},\r
- {0x13u, 0x08u},\r
- {0x19u, 0x52u},\r
- {0x1Bu, 0x20u},\r
- {0x20u, 0x42u},\r
- {0x21u, 0x31u},\r
- {0x22u, 0x08u},\r
- {0x23u, 0x40u},\r
- {0x28u, 0x02u},\r
- {0x29u, 0x18u},\r
- {0x33u, 0x09u},\r
- {0x38u, 0x50u},\r
- {0x39u, 0x20u},\r
- {0x40u, 0x40u},\r
- {0x41u, 0x10u},\r
- {0x48u, 0x41u},\r
- {0x49u, 0x19u},\r
- {0x50u, 0x04u},\r
- {0x52u, 0x10u},\r
- {0x53u, 0x80u},\r
- {0x59u, 0x02u},\r
- {0x5Au, 0xA8u},\r
+ {0x01u, 0x02u},\r
+ {0x03u, 0x08u},\r
+ {0x12u, 0x02u},\r
+ {0x19u, 0x51u},\r
+ {0x21u, 0x09u},\r
+ {0x22u, 0x81u},\r
+ {0x23u, 0x08u},\r
+ {0x27u, 0x02u},\r
+ {0x2Au, 0x20u},\r
+ {0x2Bu, 0x80u},\r
+ {0x32u, 0x81u},\r
+ {0x33u, 0x04u},\r
+ {0x38u, 0x08u},\r
+ {0x39u, 0x40u},\r
+ {0x3Au, 0x02u},\r
+ {0x3Bu, 0x10u},\r
+ {0x3Eu, 0x08u},\r
+ {0x43u, 0x94u},\r
+ {0x49u, 0x08u},\r
+ {0x4Au, 0x04u},\r
+ {0x4Bu, 0x11u},\r
+ {0x51u, 0x02u},\r
+ {0x52u, 0x48u},\r
+ {0x59u, 0x90u},\r
+ {0x5Bu, 0x0Au},\r
{0x60u, 0x04u},\r
- {0x62u, 0x4Au},\r
- {0x68u, 0x82u},\r
- {0x69u, 0x14u},\r
- {0x70u, 0x20u},\r
- {0x72u, 0x80u},\r
- {0x73u, 0x12u},\r
- {0x81u, 0x10u},\r
- {0x84u, 0x01u},\r
- {0x87u, 0x10u},\r
- {0x8Bu, 0x11u},\r
- {0x90u, 0x04u},\r
- {0x91u, 0x40u},\r
- {0x92u, 0xA0u},\r
- {0x95u, 0x26u},\r
- {0x97u, 0x4Cu},\r
- {0x99u, 0x04u},\r
- {0x9Cu, 0x41u},\r
- {0x9Du, 0x11u},\r
- {0x9Eu, 0x80u},\r
- {0x9Fu, 0x1Bu},\r
- {0xA5u, 0x28u},\r
- {0xA7u, 0xF0u},\r
- {0xA8u, 0x40u},\r
- {0xAAu, 0x10u},\r
- {0xACu, 0x40u},\r
- {0xAEu, 0x01u},\r
+ {0x61u, 0x49u},\r
+ {0x69u, 0x59u},\r
+ {0x6Cu, 0x20u},\r
+ {0x6Eu, 0x20u},\r
+ {0x6Fu, 0x02u},\r
+ {0x72u, 0x92u},\r
+ {0x73u, 0x04u},\r
+ {0x81u, 0x0Au},\r
+ {0x82u, 0x28u},\r
+ {0x85u, 0x01u},\r
+ {0x86u, 0x10u},\r
+ {0x88u, 0x20u},\r
+ {0x89u, 0x02u},\r
+ {0x8Au, 0x40u},\r
+ {0x8Eu, 0x08u},\r
+ {0x8Fu, 0x40u},\r
+ {0x91u, 0x80u},\r
+ {0x92u, 0x04u},\r
+ {0x93u, 0x08u},\r
+ {0x95u, 0x0Du},\r
+ {0x96u, 0x20u},\r
+ {0x97u, 0x01u},\r
+ {0x99u, 0x80u},\r
+ {0x9Bu, 0x20u},\r
+ {0x9Cu, 0x49u},\r
+ {0x9Du, 0x0Cu},\r
+ {0x9Eu, 0x40u},\r
+ {0x9Fu, 0x45u},\r
+ {0xA2u, 0x44u},\r
+ {0xA3u, 0x80u},\r
+ {0xA4u, 0x98u},\r
+ {0xA5u, 0x41u},\r
+ {0xA7u, 0x24u},\r
+ {0xA8u, 0x02u},\r
+ {0xA9u, 0x01u},\r
+ {0xAEu, 0x02u},\r
{0xAFu, 0x04u},\r
{0xB2u, 0x02u},\r
- {0xB7u, 0x10u},\r
- {0xC0u, 0x0Fu},\r
- {0xC2u, 0x0Eu},\r
- {0xC4u, 0x04u},\r
- {0xCAu, 0x0Eu},\r
- {0xCCu, 0x03u},\r
- {0xCEu, 0x0Cu},\r
- {0xD0u, 0x05u},\r
- {0xD2u, 0x0Cu},\r
+ {0xC0u, 0x0Au},\r
+ {0xC4u, 0x01u},\r
+ {0xCAu, 0x05u},\r
+ {0xCCu, 0x0Bu},\r
+ {0xCEu, 0x4Fu},\r
+ {0xD0u, 0x0Eu},\r
+ {0xD2u, 0x04u},\r
{0xD6u, 0x0Fu},\r
{0xD8u, 0x0Fu},\r
- {0xE2u, 0x02u},\r
+ {0xE0u, 0x01u},\r
+ {0xE2u, 0x04u},\r
+ {0xE4u, 0x06u},\r
{0xE6u, 0x21u},\r
- {0xE8u, 0x02u},\r
- {0xECu, 0x0Cu},\r
- {0x01u, 0x04u},\r
- {0x03u, 0x01u},\r
- {0x04u, 0x24u},\r
- {0x05u, 0x10u},\r
- {0x06u, 0x12u},\r
- {0x0Bu, 0x04u},\r
- {0x0Eu, 0x18u},\r
- {0x0Fu, 0x04u},\r
- {0x10u, 0x40u},\r
- {0x13u, 0x03u},\r
- {0x15u, 0x10u},\r
- {0x16u, 0x03u},\r
- {0x19u, 0x04u},\r
- {0x1Au, 0x24u},\r
+ {0xEAu, 0x04u},\r
+ {0xEEu, 0x08u},\r
+ {0x01u, 0x01u},\r
+ {0x04u, 0x21u},\r
+ {0x05u, 0x01u},\r
+ {0x06u, 0x02u},\r
+ {0x0Au, 0x01u},\r
+ {0x0Bu, 0x08u},\r
+ {0x0Fu, 0x06u},\r
+ {0x13u, 0x01u},\r
+ {0x14u, 0x04u},\r
+ {0x15u, 0x01u},\r
+ {0x16u, 0x43u},\r
+ {0x18u, 0xE0u},\r
+ {0x19u, 0x08u},\r
{0x1Bu, 0x02u},\r
- {0x1Du, 0x10u},\r
- {0x21u, 0x20u},\r
- {0x22u, 0x04u},\r
+ {0x1Du, 0x01u},\r
+ {0x1Eu, 0xECu},\r
+ {0x21u, 0x08u},\r
+ {0x23u, 0x04u},\r
+ {0x27u, 0x01u},\r
+ {0x28u, 0x88u},\r
+ {0x2Au, 0x03u},\r
+ {0x2Bu, 0x08u},\r
+ {0x2Eu, 0x12u},\r
+ {0x30u, 0xE0u},\r
+ {0x33u, 0x01u},\r
+ {0x34u, 0x10u},\r
+ {0x36u, 0x0Fu},\r
+ {0x37u, 0x0Eu},\r
+ {0x3Eu, 0x01u},\r
+ {0x3Fu, 0x04u},\r
+ {0x54u, 0x40u},\r
+ {0x58u, 0x0Bu},\r
+ {0x59u, 0x04u},\r
+ {0x5Bu, 0x0Bu},\r
+ {0x5Cu, 0x19u},\r
+ {0x5Du, 0x90u},\r
+ {0x5Fu, 0x01u},\r
+ {0x80u, 0x18u},\r
+ {0x82u, 0x60u},\r
+ {0x83u, 0x30u},\r
+ {0x84u, 0x28u},\r
+ {0x86u, 0x53u},\r
+ {0x87u, 0x40u},\r
+ {0x8Cu, 0x30u},\r
+ {0x8Eu, 0x48u},\r
+ {0x95u, 0x43u},\r
+ {0x96u, 0x04u},\r
+ {0x97u, 0x1Cu},\r
+ {0x9Bu, 0x4Au},\r
+ {0xA0u, 0x04u},\r
+ {0xA1u, 0x44u},\r
+ {0xA2u, 0x02u},\r
+ {0xA3u, 0x2Bu},\r
+ {0xA4u, 0x04u},\r
+ {0xA5u, 0x01u},\r
+ {0xA6u, 0x01u},\r
+ {0xAAu, 0x04u},\r
+ {0xABu, 0x07u},\r
+ {0xB1u, 0x70u},\r
+ {0xB2u, 0x07u},\r
+ {0xB3u, 0x08u},\r
+ {0xB4u, 0x78u},\r
+ {0xB5u, 0x07u},\r
+ {0xBEu, 0x10u},\r
+ {0xBFu, 0x04u},\r
+ {0xD6u, 0x08u},\r
+ {0xD8u, 0x04u},\r
+ {0xD9u, 0x04u},\r
+ {0xDBu, 0x04u},\r
+ {0xDCu, 0x11u},\r
+ {0xDDu, 0x90u},\r
+ {0xDFu, 0x01u},\r
+ {0x01u, 0x20u},\r
+ {0x03u, 0x20u},\r
+ {0x04u, 0x80u},\r
+ {0x05u, 0x05u},\r
+ {0x0Au, 0x26u},\r
+ {0x0Eu, 0x10u},\r
+ {0x12u, 0x01u},\r
+ {0x13u, 0x10u},\r
+ {0x15u, 0x01u},\r
+ {0x17u, 0x24u},\r
+ {0x19u, 0x20u},\r
+ {0x1Au, 0x42u},\r
+ {0x1Cu, 0x08u},\r
+ {0x1Du, 0x04u},\r
+ {0x21u, 0x40u},\r
+ {0x22u, 0x08u},\r
+ {0x24u, 0x80u},\r
+ {0x25u, 0x01u},\r
{0x26u, 0x20u},\r
- {0x29u, 0x08u},\r
- {0x2Cu, 0x24u},\r
- {0x2Du, 0x10u},\r
- {0x2Eu, 0x09u},\r
- {0x30u, 0x38u},\r
- {0x31u, 0x07u},\r
- {0x32u, 0x07u},\r
- {0x33u, 0x10u},\r
- {0x34u, 0x40u},\r
- {0x35u, 0x08u},\r
- {0x37u, 0x20u},\r
- {0x39u, 0x08u},\r
- {0x3Eu, 0x10u},\r
- {0x3Fu, 0x54u},\r
+ {0x27u, 0x14u},\r
+ {0x29u, 0x10u},\r
+ {0x2Au, 0x04u},\r
+ {0x2Bu, 0x80u},\r
+ {0x2Cu, 0x20u},\r
+ {0x2Du, 0x01u},\r
+ {0x2Fu, 0x84u},\r
+ {0x30u, 0x48u},\r
+ {0x32u, 0x20u},\r
+ {0x33u, 0x41u},\r
+ {0x34u, 0x10u},\r
+ {0x35u, 0x10u},\r
+ {0x37u, 0x24u},\r
+ {0x39u, 0x94u},\r
+ {0x3Au, 0x02u},\r
+ {0x3Du, 0x02u},\r
+ {0x3Fu, 0x04u},\r
+ {0x5Eu, 0x80u},\r
+ {0x61u, 0x20u},\r
+ {0x62u, 0x08u},\r
+ {0x63u, 0x01u},\r
+ {0x64u, 0x01u},\r
+ {0x67u, 0x02u},\r
+ {0x78u, 0x01u},\r
+ {0x81u, 0x40u},\r
+ {0x82u, 0x40u},\r
+ {0x85u, 0x40u},\r
+ {0x8Du, 0x10u},\r
+ {0x91u, 0x10u},\r
+ {0x92u, 0x14u},\r
+ {0x93u, 0x0Cu},\r
+ {0x94u, 0x04u},\r
+ {0x95u, 0x04u},\r
+ {0x96u, 0x20u},\r
+ {0x9Au, 0x80u},\r
+ {0x9Bu, 0x20u},\r
+ {0x9Cu, 0x41u},\r
+ {0x9Du, 0x04u},\r
+ {0x9Fu, 0x15u},\r
+ {0xA0u, 0x20u},\r
+ {0xA2u, 0x40u},\r
+ {0xA3u, 0x80u},\r
+ {0xA4u, 0x98u},\r
+ {0xA5u, 0x41u},\r
+ {0xA7u, 0x24u},\r
+ {0xA9u, 0x40u},\r
+ {0xAAu, 0x80u},\r
+ {0xABu, 0x08u},\r
+ {0xACu, 0x08u},\r
+ {0xAEu, 0x02u},\r
+ {0xAFu, 0x02u},\r
+ {0xB4u, 0x04u},\r
+ {0xC0u, 0xB6u},\r
+ {0xC2u, 0x27u},\r
+ {0xC4u, 0x73u},\r
+ {0xCAu, 0xE7u},\r
+ {0xCCu, 0x6Fu},\r
+ {0xCEu, 0xCFu},\r
+ {0xD6u, 0x10u},\r
+ {0xD8u, 0x1Eu},\r
+ {0xDEu, 0x01u},\r
+ {0xE0u, 0x01u},\r
+ {0xE8u, 0x01u},\r
+ {0xEAu, 0x02u},\r
+ {0xECu, 0x04u},\r
+ {0xEEu, 0x09u},\r
+ {0x17u, 0x01u},\r
+ {0x1Bu, 0x01u},\r
+ {0x35u, 0x01u},\r
+ {0x3Fu, 0x10u},\r
+ {0x59u, 0x04u},\r
+ {0x5Fu, 0x01u},\r
+ {0x01u, 0x02u},\r
+ {0x03u, 0x29u},\r
+ {0x09u, 0x08u},\r
+ {0x0Au, 0x01u},\r
+ {0x0Bu, 0x04u},\r
+ {0x11u, 0x25u},\r
+ {0x12u, 0x01u},\r
+ {0x18u, 0x04u},\r
+ {0x19u, 0x80u},\r
+ {0x1Au, 0x80u},\r
+ {0x20u, 0x28u},\r
+ {0x21u, 0x09u},\r
+ {0x22u, 0x11u},\r
+ {0x23u, 0x14u},\r
+ {0x26u, 0x20u},\r
+ {0x2Au, 0x40u},\r
+ {0x2Bu, 0x28u},\r
+ {0x31u, 0x08u},\r
+ {0x32u, 0x10u},\r
+ {0x33u, 0x41u},\r
+ {0x34u, 0x10u},\r
+ {0x37u, 0x04u},\r
+ {0x38u, 0x80u},\r
+ {0x39u, 0x14u},\r
+ {0x41u, 0x09u},\r
+ {0x43u, 0x20u},\r
+ {0x48u, 0x04u},\r
+ {0x49u, 0x08u},\r
+ {0x4Bu, 0x80u},\r
+ {0x50u, 0x01u},\r
+ {0x51u, 0x20u},\r
+ {0x52u, 0x45u},\r
+ {0x61u, 0x10u},\r
+ {0x68u, 0x08u},\r
+ {0x69u, 0x15u},\r
+ {0x6Bu, 0x41u},\r
+ {0x70u, 0xC0u},\r
+ {0x72u, 0x03u},\r
+ {0x78u, 0x01u},\r
+ {0x8Eu, 0x20u},\r
+ {0x93u, 0x02u},\r
+ {0x94u, 0x04u},\r
+ {0x95u, 0x04u},\r
+ {0x96u, 0x20u},\r
+ {0x97u, 0x10u},\r
+ {0x98u, 0x11u},\r
+ {0x9Au, 0x80u},\r
+ {0x9Bu, 0x04u},\r
+ {0x9Eu, 0x07u},\r
+ {0x9Fu, 0x41u},\r
+ {0xA1u, 0x10u},\r
+ {0xA3u, 0x80u},\r
+ {0xA4u, 0x98u},\r
+ {0xA5u, 0x20u},\r
+ {0xA7u, 0x24u},\r
+ {0xAAu, 0x04u},\r
+ {0xABu, 0x01u},\r
+ {0xACu, 0x04u},\r
+ {0xB5u, 0x01u},\r
+ {0xC0u, 0x0Fu},\r
+ {0xC2u, 0x07u},\r
+ {0xC4u, 0x0Fu},\r
+ {0xCAu, 0x0Eu},\r
+ {0xCCu, 0x6Fu},\r
+ {0xCEu, 0x0Eu},\r
+ {0xD0u, 0x07u},\r
+ {0xD2u, 0x0Cu},\r
+ {0xD8u, 0x04u},\r
+ {0xDEu, 0x01u},\r
+ {0xE2u, 0x10u},\r
+ {0xECu, 0x42u},\r
+ {0xAFu, 0x08u},\r
+ {0x80u, 0x40u},\r
+ {0x94u, 0x80u},\r
+ {0xA7u, 0x08u},\r
+ {0xA8u, 0x28u},\r
+ {0xA9u, 0x18u},\r
+ {0xAAu, 0x02u},\r
+ {0xAFu, 0x80u},\r
+ {0xE0u, 0x01u},\r
+ {0xE6u, 0x10u},\r
+ {0xE8u, 0x01u},\r
+ {0xEAu, 0x12u},\r
+ {0xEEu, 0x01u},\r
+ {0x00u, 0x0Fu},\r
+ {0x02u, 0xF0u},\r
+ {0x0Bu, 0xFFu},\r
+ {0x0Cu, 0x33u},\r
+ {0x0Eu, 0xCCu},\r
+ {0x0Fu, 0xFFu},\r
+ {0x11u, 0x33u},\r
+ {0x13u, 0xCCu},\r
+ {0x14u, 0xFFu},\r
+ {0x18u, 0x96u},\r
+ {0x19u, 0x55u},\r
+ {0x1Au, 0x69u},\r
+ {0x1Bu, 0xAAu},\r
+ {0x1Cu, 0x55u},\r
+ {0x1Eu, 0xAAu},\r
+ {0x21u, 0xFFu},\r
+ {0x26u, 0xFFu},\r
+ {0x29u, 0x96u},\r
+ {0x2Au, 0xFFu},\r
+ {0x2Bu, 0x69u},\r
+ {0x2Du, 0x0Fu},\r
+ {0x2Fu, 0xF0u},\r
+ {0x35u, 0xFFu},\r
+ {0x36u, 0xFFu},\r
+ {0x3Eu, 0x40u},\r
+ {0x3Fu, 0x10u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x99u},\r
{0x5Fu, 0x01u},\r
- {0x85u, 0x33u},\r
- {0x86u, 0xFFu},\r
- {0x87u, 0xCCu},\r
- {0x89u, 0xFFu},\r
- {0x8Du, 0x0Fu},\r
- {0x8Eu, 0xFFu},\r
- {0x8Fu, 0xF0u},\r
- {0x90u, 0x69u},\r
- {0x92u, 0x96u},\r
- {0x93u, 0xFFu},\r
- {0x96u, 0xFFu},\r
- {0x98u, 0x33u},\r
- {0x9Au, 0xCCu},\r
- {0x9Du, 0x69u},\r
- {0x9Fu, 0x96u},\r
- {0xA0u, 0x55u},\r
- {0xA1u, 0x55u},\r
- {0xA2u, 0xAAu},\r
- {0xA3u, 0xAAu},\r
- {0xA9u, 0xFFu},\r
- {0xACu, 0x0Fu},\r
- {0xAEu, 0xF0u},\r
+ {0x84u, 0xFFu},\r
+ {0x88u, 0x69u},\r
+ {0x8Au, 0x96u},\r
+ {0x8Bu, 0xFFu},\r
+ {0x8Cu, 0x33u},\r
+ {0x8Du, 0x33u},\r
+ {0x8Eu, 0xCCu},\r
+ {0x8Fu, 0xCCu},\r
+ {0x91u, 0x0Fu},\r
+ {0x92u, 0xFFu},\r
+ {0x93u, 0xF0u},\r
+ {0x97u, 0xFFu},\r
+ {0x98u, 0xFFu},\r
+ {0x99u, 0x55u},\r
+ {0x9Bu, 0xAAu},\r
+ {0x9Cu, 0x0Fu},\r
+ {0x9Eu, 0xF0u},\r
+ {0xA3u, 0xFFu},\r
+ {0xA4u, 0x55u},\r
+ {0xA6u, 0xAAu},\r
+ {0xA9u, 0x69u},\r
+ {0xABu, 0x96u},\r
{0xB0u, 0xFFu},\r
{0xB7u, 0xFFu},\r
{0xBEu, 0x01u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x40u},\r
- {0x01u, 0x40u},\r
- {0x03u, 0x20u},\r
- {0x05u, 0x04u},\r
+ {0x01u, 0x08u},\r
+ {0x03u, 0x09u},\r
+ {0x04u, 0x80u},\r
+ {0x05u, 0x01u},\r
{0x07u, 0x01u},\r
- {0x08u, 0x01u},\r
- {0x09u, 0x20u},\r
- {0x0Au, 0x10u},\r
+ {0x09u, 0x12u},\r
+ {0x0Bu, 0x02u},\r
{0x0Cu, 0x08u},\r
- {0x0Eu, 0x80u},\r
- {0x0Fu, 0xA4u},\r
- {0x11u, 0x04u},\r
- {0x13u, 0x42u},\r
- {0x14u, 0x40u},\r
- {0x15u, 0x40u},\r
- {0x18u, 0x44u},\r
- {0x19u, 0x04u},\r
- {0x1Au, 0x10u},\r
- {0x1Fu, 0x02u},\r
- {0x22u, 0x55u},\r
- {0x26u, 0x80u},\r
- {0x2Au, 0x22u},\r
- {0x2Bu, 0x02u},\r
- {0x2Cu, 0x48u},\r
- {0x31u, 0x18u},\r
- {0x32u, 0x81u},\r
- {0x36u, 0x40u},\r
+ {0x0Du, 0x80u},\r
+ {0x0Fu, 0x08u},\r
+ {0x10u, 0x10u},\r
+ {0x14u, 0x20u},\r
+ {0x15u, 0x20u},\r
+ {0x1Au, 0x80u},\r
+ {0x1Fu, 0x80u},\r
+ {0x20u, 0x01u},\r
+ {0x25u, 0x20u},\r
+ {0x2Au, 0x02u},\r
+ {0x2Bu, 0x0Cu},\r
+ {0x2Cu, 0x02u},\r
+ {0x2Eu, 0x02u},\r
+ {0x2Fu, 0x09u},\r
+ {0x30u, 0x1Au},\r
+ {0x31u, 0x01u},\r
+ {0x34u, 0x10u},\r
{0x37u, 0x01u},\r
- {0x39u, 0x22u},\r
- {0x3Au, 0x80u},\r
- {0x3Bu, 0x08u},\r
- {0x3Cu, 0x40u},\r
- {0x3Eu, 0x10u},\r
- {0x3Fu, 0x04u},\r
- {0x43u, 0xC0u},\r
- {0x59u, 0x01u},\r
- {0x5Bu, 0x58u},\r
- {0x86u, 0x20u},\r
- {0x8Au, 0x04u},\r
- {0xC0u, 0xA5u},\r
- {0xC2u, 0x7Eu},\r
- {0xC4u, 0x9Du},\r
- {0xCAu, 0xADu},\r
- {0xCCu, 0x9Fu},\r
- {0xCEu, 0x7Fu},\r
- {0xD6u, 0x0Fu},\r
- {0xE2u, 0x88u},\r
- {0x80u, 0x01u},\r
- {0x90u, 0x02u},\r
- {0xB2u, 0x01u},\r
- {0xEAu, 0x20u},\r
- {0x01u, 0x05u},\r
- {0x02u, 0x01u},\r
- {0x05u, 0x09u},\r
- {0x06u, 0x0Cu},\r
- {0x07u, 0x02u},\r
- {0x08u, 0x01u},\r
- {0x0Au, 0x02u},\r
- {0x0Bu, 0x38u},\r
- {0x0Eu, 0x10u},\r
- {0x0Fu, 0x04u},\r
- {0x13u, 0x05u},\r
- {0x14u, 0x04u},\r
- {0x15u, 0x05u},\r
- {0x16u, 0x03u},\r
- {0x18u, 0x10u},\r
- {0x19u, 0x23u},\r
- {0x1Cu, 0x10u},\r
- {0x1Du, 0x02u},\r
- {0x1Fu, 0x01u},\r
- {0x20u, 0x10u},\r
- {0x21u, 0x05u},\r
- {0x24u, 0x10u},\r
- {0x25u, 0x05u},\r
- {0x28u, 0x08u},\r
- {0x29u, 0x02u},\r
- {0x2Au, 0x03u},\r
- {0x2Bu, 0x11u},\r
- {0x2Du, 0x38u},\r
- {0x2Eu, 0x22u},\r
- {0x30u, 0x20u},\r
- {0x31u, 0x03u},\r
- {0x32u, 0x0Fu},\r
- {0x33u, 0x04u},\r
- {0x36u, 0x10u},\r
- {0x37u, 0x38u},\r
- {0x3Bu, 0x02u},\r
- {0x3Eu, 0x40u},\r
- {0x3Fu, 0x44u},\r
- {0x58u, 0x0Bu},\r
- {0x59u, 0x0Bu},\r
- {0x5Cu, 0x99u},\r
+ {0x38u, 0x80u},\r
+ {0x39u, 0x20u},\r
+ {0x3Cu, 0x80u},\r
+ {0x3Du, 0x20u},\r
+ {0x5Cu, 0x08u},\r
+ {0x5Du, 0x80u},\r
+ {0x5Eu, 0x11u},\r
+ {0x80u, 0x08u},\r
+ {0x82u, 0x10u},\r
+ {0x84u, 0x10u},\r
+ {0x85u, 0x80u},\r
+ {0x88u, 0x40u},\r
+ {0x89u, 0x12u},\r
+ {0x8Au, 0x01u},\r
+ {0x8Du, 0x80u},\r
+ {0x8Eu, 0x40u},\r
+ {0x94u, 0x01u},\r
+ {0xA0u, 0x02u},\r
+ {0xA5u, 0x20u},\r
+ {0xA9u, 0x20u},\r
+ {0xC0u, 0x97u},\r
+ {0xC2u, 0xEBu},\r
+ {0xC4u, 0x64u},\r
+ {0xCAu, 0xB5u},\r
+ {0xCCu, 0xA7u},\r
+ {0xCEu, 0x3Cu},\r
+ {0xD6u, 0xF0u},\r
+ {0xE2u, 0x94u},\r
+ {0xE4u, 0xE2u},\r
+ {0xE6u, 0x01u},\r
+ {0xEEu, 0x28u},\r
+ {0x80u, 0x02u},\r
+ {0x8Cu, 0x01u},\r
+ {0xE0u, 0x04u},\r
+ {0xE6u, 0x50u},\r
+ {0x8Cu, 0x40u},\r
+ {0x90u, 0x40u},\r
+ {0xABu, 0x21u},\r
+ {0xE2u, 0x40u},\r
+ {0x04u, 0x08u},\r
+ {0x06u, 0x33u},\r
+ {0x08u, 0x20u},\r
+ {0x0Au, 0x18u},\r
+ {0x0Eu, 0x01u},\r
+ {0x14u, 0x2Eu},\r
+ {0x15u, 0x04u},\r
+ {0x16u, 0x10u},\r
+ {0x17u, 0x01u},\r
+ {0x18u, 0x18u},\r
+ {0x1Au, 0x25u},\r
+ {0x1Bu, 0x03u},\r
+ {0x21u, 0x04u},\r
+ {0x23u, 0x02u},\r
+ {0x27u, 0x04u},\r
+ {0x2Fu, 0x04u},\r
+ {0x30u, 0x07u},\r
+ {0x33u, 0x07u},\r
+ {0x34u, 0x38u},\r
+ {0x3Au, 0x20u},\r
+ {0x58u, 0x08u},\r
+ {0x59u, 0x04u},\r
+ {0x5Cu, 0x19u},\r
{0x5Fu, 0x01u},\r
- {0x84u, 0x18u},\r
- {0x86u, 0x60u},\r
- {0x87u, 0x06u},\r
- {0x8Cu, 0x04u},\r
- {0x8Eu, 0x03u},\r
- {0x93u, 0x02u},\r
- {0x94u, 0x03u},\r
- {0x96u, 0x04u},\r
- {0x97u, 0x0Au},\r
- {0x98u, 0x30u},\r
- {0x99u, 0x0Cu},\r
- {0x9Au, 0x48u},\r
- {0x9Du, 0x01u},\r
- {0xA4u, 0x01u},\r
- {0xA6u, 0x06u},\r
- {0xA8u, 0x05u},\r
- {0xAAu, 0x02u},\r
- {0xACu, 0x28u},\r
- {0xAEu, 0x50u},\r
- {0xB1u, 0x0Eu},\r
- {0xB3u, 0x01u},\r
- {0xB4u, 0x78u},\r
- {0xB6u, 0x07u},\r
- {0xBAu, 0x80u},\r
- {0xBEu, 0x10u},\r
- {0xBFu, 0x04u},\r
+ {0x80u, 0x2Cu},\r
+ {0x83u, 0x9Fu},\r
+ {0x84u, 0x24u},\r
+ {0x85u, 0xC0u},\r
+ {0x86u, 0x08u},\r
+ {0x87u, 0x04u},\r
+ {0x88u, 0x44u},\r
+ {0x89u, 0xC0u},\r
+ {0x8Au, 0x20u},\r
+ {0x8Bu, 0x08u},\r
+ {0x8Cu, 0x0Cu},\r
+ {0x8Du, 0xC0u},\r
+ {0x8Eu, 0x20u},\r
+ {0x8Fu, 0x01u},\r
+ {0x90u, 0x10u},\r
+ {0x91u, 0x90u},\r
+ {0x93u, 0x40u},\r
+ {0x94u, 0xE0u},\r
+ {0x95u, 0x7Fu},\r
+ {0x96u, 0x0Fu},\r
+ {0x97u, 0x80u},\r
+ {0x98u, 0xA1u},\r
+ {0x9Au, 0x42u},\r
+ {0x9Bu, 0xFFu},\r
+ {0x9Cu, 0x10u},\r
+ {0x9Du, 0xC0u},\r
+ {0x9Fu, 0x02u},\r
+ {0xA0u, 0x08u},\r
+ {0xA3u, 0x60u},\r
+ {0xA4u, 0xC1u},\r
+ {0xA5u, 0x1Fu},\r
+ {0xA6u, 0x2Eu},\r
+ {0xA7u, 0x20u},\r
+ {0xA8u, 0x20u},\r
+ {0xA9u, 0x80u},\r
+ {0xAAu, 0x0Cu},\r
+ {0xACu, 0x2Cu},\r
+ {0xB0u, 0x10u},\r
+ {0xB2u, 0x60u},\r
+ {0xB4u, 0x0Fu},\r
+ {0xB6u, 0x80u},\r
+ {0xB7u, 0xFFu},\r
+ {0xB8u, 0x02u},\r
+ {0xBAu, 0x08u},\r
+ {0xBEu, 0x40u},\r
+ {0xBFu, 0x40u},\r
+ {0xD4u, 0x09u},\r
{0xD8u, 0x0Bu},\r
- {0xD9u, 0x0Bu},\r
- {0xDCu, 0x99u},\r
+ {0xD9u, 0x04u},\r
+ {0xDBu, 0x0Bu},\r
+ {0xDCu, 0x09u},\r
+ {0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x08u},\r
- {0x01u, 0x80u},\r
- {0x05u, 0x05u},\r
- {0x06u, 0x20u},\r
- {0x07u, 0x09u},\r
- {0x08u, 0x20u},\r
- {0x09u, 0x08u},\r
- {0x0Cu, 0x80u},\r
- {0x0Eu, 0x28u},\r
- {0x11u, 0x04u},\r
- {0x13u, 0x60u},\r
- {0x15u, 0x41u},\r
- {0x17u, 0x14u},\r
- {0x18u, 0x04u},\r
- {0x19u, 0x80u},\r
- {0x1Du, 0x85u},\r
- {0x1Eu, 0x02u},\r
- {0x20u, 0x20u},\r
- {0x22u, 0x01u},\r
- {0x24u, 0x02u},\r
- {0x26u, 0x0Au},\r
- {0x27u, 0x40u},\r
- {0x2Cu, 0x81u},\r
- {0x2Fu, 0x28u},\r
+ {0x01u, 0x04u},\r
+ {0x03u, 0x49u},\r
+ {0x04u, 0x48u},\r
+ {0x05u, 0x10u},\r
+ {0x09u, 0x88u},\r
+ {0x0Au, 0x84u},\r
+ {0x0Du, 0x08u},\r
+ {0x0Fu, 0x04u},\r
+ {0x11u, 0x50u},\r
+ {0x12u, 0x40u},\r
+ {0x13u, 0x05u},\r
+ {0x18u, 0x08u},\r
+ {0x19u, 0x42u},\r
+ {0x1Au, 0x04u},\r
+ {0x1Bu, 0x28u},\r
+ {0x1Cu, 0x40u},\r
+ {0x1Du, 0x10u},\r
+ {0x21u, 0x80u},\r
+ {0x27u, 0x10u},\r
+ {0x29u, 0x02u},\r
+ {0x2Bu, 0x28u},\r
+ {0x2Cu, 0x10u},\r
+ {0x2Eu, 0x80u},\r
+ {0x2Fu, 0x80u},\r
{0x31u, 0x08u},\r
- {0x32u, 0x41u},\r
- {0x33u, 0x18u},\r
- {0x37u, 0x65u},\r
- {0x38u, 0x08u},\r
- {0x3Du, 0x05u},\r
- {0x3Eu, 0xA0u},\r
- {0x78u, 0x02u},\r
- {0x7Eu, 0x80u},\r
- {0x90u, 0x08u},\r
- {0x91u, 0x45u},\r
- {0x92u, 0x80u},\r
- {0x93u, 0x40u},\r
- {0x94u, 0x04u},\r
- {0x98u, 0x23u},\r
- {0x9Au, 0x80u},\r
- {0x9Bu, 0x3Du},\r
- {0x9Du, 0x80u},\r
- {0x9Fu, 0x40u},\r
- {0xA0u, 0x84u},\r
+ {0x32u, 0x10u},\r
+ {0x33u, 0x41u},\r
+ {0x37u, 0x14u},\r
+ {0x38u, 0x82u},\r
+ {0x39u, 0x54u},\r
+ {0x59u, 0x88u},\r
+ {0x5Au, 0x02u},\r
+ {0x5Bu, 0x20u},\r
+ {0x61u, 0x40u},\r
+ {0x78u, 0x01u},\r
+ {0x7Fu, 0x01u},\r
+ {0x83u, 0x10u},\r
+ {0x8Fu, 0x04u},\r
+ {0x90u, 0x82u},\r
+ {0x91u, 0x14u},\r
+ {0x92u, 0xA2u},\r
+ {0x93u, 0x06u},\r
+ {0x98u, 0x11u},\r
+ {0x99u, 0x88u},\r
+ {0x9Au, 0xC0u},\r
+ {0x9Bu, 0x45u},\r
+ {0x9Du, 0x12u},\r
{0xA1u, 0x08u},\r
- {0xA2u, 0x94u},\r
- {0xA3u, 0x20u},\r
- {0xA4u, 0x10u},\r
- {0xA5u, 0x80u},\r
- {0xA6u, 0x0Bu},\r
- {0xA8u, 0x04u},\r
- {0xAEu, 0x40u},\r
- {0xB6u, 0x80u},\r
- {0xB7u, 0x01u},\r
- {0xC0u, 0xF5u},\r
- {0xC2u, 0xE6u},\r
- {0xC4u, 0xF7u},\r
- {0xCAu, 0xF0u},\r
- {0xCCu, 0xFFu},\r
- {0xCEu, 0xF2u},\r
- {0xDEu, 0x81u},\r
- {0xE8u, 0x04u},\r
- {0xECu, 0x80u},\r
- {0xEEu, 0x02u},\r
- {0xABu, 0x40u},\r
- {0xB0u, 0x04u},\r
+ {0xA3u, 0x80u},\r
+ {0xA7u, 0x2Cu},\r
+ {0xB3u, 0x40u},\r
+ {0xC0u, 0xEFu},\r
+ {0xC2u, 0x6Fu},\r
+ {0xC4u, 0x0Fu},\r
+ {0xCAu, 0xD7u},\r
+ {0xCCu, 0x6Fu},\r
+ {0xCEu, 0x0Fu},\r
+ {0xD6u, 0x0Fu},\r
+ {0xD8u, 0x08u},\r
+ {0xDEu, 0x11u},\r
+ {0xE0u, 0x40u},\r
{0xECu, 0x80u},\r
- {0xEEu, 0x02u},\r
- {0x33u, 0x40u},\r
+ {0xEEu, 0x0Au},\r
+ {0xEEu, 0x0Au},\r
+ {0x33u, 0x80u},\r
{0x36u, 0x40u},\r
- {0x58u, 0x08u},\r
- {0x5Cu, 0x01u},\r
- {0x5Du, 0x10u},\r
- {0x61u, 0x08u},\r
- {0x64u, 0x10u},\r
- {0x89u, 0x10u},\r
+ {0x5Bu, 0x08u},\r
+ {0x5Fu, 0x22u},\r
+ {0x60u, 0x10u},\r
+ {0x64u, 0x20u},\r
+ {0x83u, 0x22u},\r
{0xCCu, 0x30u},\r
{0xD6u, 0xE0u},\r
{0xD8u, 0xC0u},\r
- {0x59u, 0x40u},\r
- {0x5Fu, 0x20u},\r
- {0x83u, 0x40u},\r
+ {0xE2u, 0x80u},\r
+ {0xE6u, 0x80u},\r
+ {0x52u, 0x80u},\r
+ {0x57u, 0x10u},\r
+ {0x5Bu, 0x20u},\r
+ {0x5Eu, 0x01u},\r
+ {0x86u, 0x80u},\r
{0x8Bu, 0x20u},\r
- {0x9Cu, 0x08u},\r
- {0x9Fu, 0x40u},\r
- {0xA5u, 0x08u},\r
+ {0x9Cu, 0x20u},\r
+ {0x9Fu, 0x08u},\r
{0xA6u, 0x40u},\r
- {0xA8u, 0x01u},\r
- {0xACu, 0x10u},\r
- {0xD4u, 0x80u},\r
- {0xD6u, 0x20u},\r
- {0xE6u, 0x80u},\r
- {0xEAu, 0x80u},\r
- {0xEEu, 0x40u},\r
- {0x89u, 0x08u},\r
- {0x8Cu, 0x08u},\r
- {0x9Cu, 0x08u},\r
- {0xA5u, 0x08u},\r
+ {0xA7u, 0x80u},\r
+ {0xA8u, 0x10u},\r
+ {0xD4u, 0xE0u},\r
+ {0xD6u, 0x80u},\r
+ {0xE6u, 0x10u},\r
+ {0xEEu, 0x80u},\r
+ {0x80u, 0x02u},\r
+ {0x87u, 0x20u},\r
+ {0x9Fu, 0x08u},\r
{0xA6u, 0x40u},\r
- {0xADu, 0x40u},\r
- {0xEEu, 0x10u},\r
- {0x94u, 0x02u},\r
+ {0xA7u, 0x90u},\r
+ {0xA8u, 0x20u},\r
+ {0xAEu, 0x01u},\r
+ {0xE0u, 0x40u},\r
+ {0xE2u, 0x20u},\r
+ {0xEAu, 0x10u},\r
+ {0xEEu, 0x20u},\r
+ {0x8Fu, 0x10u},\r
+ {0x9Fu, 0x28u},\r
+ {0xA0u, 0x02u},\r
{0xA6u, 0x40u},\r
- {0xB4u, 0x01u},\r
- {0x08u, 0x80u},\r
- {0x0Fu, 0x40u},\r
- {0x12u, 0x80u},\r
- {0x53u, 0x04u},\r
- {0x57u, 0x80u},\r
- {0x5Bu, 0x20u},\r
- {0x5Cu, 0x10u},\r
- {0x84u, 0x80u},\r
+ {0xA7u, 0x90u},\r
+ {0xB7u, 0x08u},\r
+ {0x0Bu, 0x08u},\r
+ {0x0Cu, 0x02u},\r
+ {0x12u, 0x10u},\r
+ {0x53u, 0x10u},\r
+ {0x55u, 0x08u},\r
+ {0x5Au, 0x10u},\r
+ {0x5Eu, 0x40u},\r
+ {0x82u, 0x40u},\r
+ {0x8Cu, 0x02u},\r
{0xC2u, 0x06u},\r
{0xC4u, 0x08u},\r
{0xD4u, 0x07u},\r
{0xD6u, 0x04u},\r
- {0x01u, 0x20u},\r
- {0x06u, 0x80u},\r
- {0x07u, 0x01u},\r
- {0x09u, 0x01u},\r
- {0x0Au, 0x02u},\r
- {0x0Cu, 0x80u},\r
- {0x0Eu, 0x20u},\r
- {0x82u, 0x40u},\r
- {0x87u, 0x01u},\r
- {0x8Bu, 0x40u},\r
- {0x93u, 0x40u},\r
- {0x98u, 0x80u},\r
- {0xA4u, 0x80u},\r
- {0xABu, 0x80u},\r
- {0xAFu, 0x24u},\r
- {0xB2u, 0x80u},\r
- {0xB4u, 0x10u},\r
+ {0xE6u, 0x02u},\r
+ {0x01u, 0x80u},\r
+ {0x04u, 0x80u},\r
+ {0x05u, 0x02u},\r
+ {0x08u, 0x81u},\r
+ {0x0Eu, 0x02u},\r
+ {0x0Fu, 0x20u},\r
+ {0x81u, 0x80u},\r
+ {0x83u, 0x10u},\r
+ {0x87u, 0x10u},\r
+ {0x89u, 0x02u},\r
+ {0x96u, 0x10u},\r
+ {0x97u, 0x20u},\r
+ {0xA5u, 0x08u},\r
+ {0xAFu, 0x04u},\r
+ {0xB2u, 0x10u},\r
{0xC0u, 0x07u},\r
{0xC2u, 0x0Fu},\r
- {0xE2u, 0x04u},\r
- {0xE8u, 0x08u},\r
- {0xEAu, 0x01u},\r
- {0x92u, 0x02u},\r
- {0x96u, 0x80u},\r
- {0x9Au, 0x80u},\r
- {0xA1u, 0x01u},\r
- {0xB0u, 0x80u},\r
- {0xB2u, 0x10u},\r
- {0xB5u, 0x20u},\r
- {0xEAu, 0x0Du},\r
- {0x0Au, 0x80u},\r
+ {0xE2u, 0x01u},\r
+ {0xEEu, 0x04u},\r
+ {0x82u, 0x10u},\r
+ {0x8Cu, 0x40u},\r
+ {0x90u, 0x80u},\r
+ {0x96u, 0x10u},\r
+ {0xA9u, 0x08u},\r
+ {0xAAu, 0x01u},\r
+ {0xACu, 0x01u},\r
+ {0xB4u, 0x80u},\r
+ {0xE6u, 0x08u},\r
+ {0xEAu, 0x08u},\r
+ {0x08u, 0x08u},\r
{0x0Fu, 0x40u},\r
- {0x96u, 0x80u},\r
- {0xA9u, 0x01u},\r
- {0xAEu, 0x80u},\r
- {0xB2u, 0x01u},\r
{0xC2u, 0x0Cu},\r
- {0xEAu, 0x04u},\r
- {0x22u, 0x08u},\r
- {0x24u, 0x02u},\r
- {0x94u, 0x02u},\r
- {0x9Eu, 0x20u},\r
- {0xA6u, 0x08u},\r
- {0xAEu, 0x60u},\r
- {0xB2u, 0x08u},\r
- {0xC8u, 0x60u},\r
- {0xE8u, 0x10u},\r
- {0xEEu, 0x40u},\r
- {0x06u, 0x20u},\r
- {0x53u, 0x01u},\r
- {0x5Du, 0x20u},\r
- {0x83u, 0x01u},\r
- {0x99u, 0x20u},\r
- {0x9Eu, 0x20u},\r
- {0xB1u, 0x20u},\r
+ {0x26u, 0x80u},\r
+ {0x27u, 0x20u},\r
+ {0x83u, 0x08u},\r
+ {0x8Eu, 0x80u},\r
+ {0x9Eu, 0x40u},\r
+ {0x9Fu, 0x28u},\r
+ {0xA0u, 0x02u},\r
+ {0xAEu, 0x40u},\r
+ {0xAFu, 0x80u},\r
+ {0xB2u, 0x40u},\r
+ {0xC8u, 0xA0u},\r
+ {0xE2u, 0x20u},\r
+ {0xEEu, 0x50u},\r
+ {0x06u, 0x40u},\r
+ {0x50u, 0x02u},\r
+ {0x57u, 0x80u},\r
+ {0x8Fu, 0x80u},\r
+ {0x9Eu, 0x40u},\r
+ {0xA0u, 0x02u},\r
{0xC0u, 0x20u},\r
- {0xD4u, 0x80u},\r
- {0xD6u, 0x20u},\r
- {0xE6u, 0x20u},\r
+ {0xD4u, 0xC0u},\r
+ {0xACu, 0x08u},\r
{0xAFu, 0x40u},\r
+ {0x00u, 0x02u},\r
{0x01u, 0x01u},\r
+ {0x08u, 0x02u},\r
+ {0x09u, 0x01u},\r
+ {0x0Au, 0x02u},\r
{0x0Bu, 0x01u},\r
- {0x0Du, 0x01u},\r
- {0x0Fu, 0x01u},\r
+ {0x10u, 0x02u},\r
{0x11u, 0x01u},\r
+ {0x1Au, 0x02u},\r
{0x1Bu, 0x01u},\r
{0x00u, 0x0Au},\r
};\r
static const cfg_memset_t CYCODE cfg_memset_list [] = {\r
/* address, size */\r
{(void CYFAR *)(CYREG_PRT1_DR), 16u},\r
- {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1536u},\r
- {(void CYFAR *)(CYDEV_UCFG_B0_P3_U1_BASE), 2432u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1664u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B0_P3_ROUTE_BASE), 2304u},\r
{(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},\r
{(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u},\r
};\r
\r
- /* UDB_1_2_1_CONFIG Address: CYDEV_UCFG_B0_P3_U0_BASE Size (bytes): 128 */\r
- static const uint8 CYCODE BS_UDB_1_2_1_CONFIG_VAL[] = {\r
- 0x80u, 0x01u, 0x00u, 0x00u, 0x7Fu, 0x10u, 0x80u, 0x00u, 0xC0u, 0x08u, 0x04u, 0x21u, 0xC0u, 0x04u, 0x01u, 0x00u, \r
- 0x00u, 0x01u, 0x60u, 0x00u, 0x00u, 0x07u, 0xFFu, 0x18u, 0x00u, 0x22u, 0x9Fu, 0x08u, 0xC0u, 0x40u, 0x02u, 0x00u, \r
- 0x90u, 0x01u, 0x40u, 0x00u, 0x1Fu, 0x01u, 0x20u, 0x00u, 0xC0u, 0x40u, 0x08u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, \r
- 0x00u, 0x3Fu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x40u, 0x00u, 0x82u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x01u, \r
- 0x32u, 0x06u, 0x10u, 0x00u, 0x04u, 0xCBu, 0xFDu, 0x0Eu, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
- 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x20u, 0x04u, 0x0Bu, 0x0Bu, 0x0Bu, 0x90u, 0x99u, 0x00u, 0x01u, \r
+ /* UDB_1_2_0_CONFIG Address: CYDEV_UCFG_B0_P3_U1_BASE Size (bytes): 128 */\r
+ static const uint8 CYCODE BS_UDB_1_2_0_CONFIG_VAL[] = {\r
+ 0x04u, 0x00u, 0x00u, 0x00u, 0x07u, 0xC2u, 0x18u, 0x04u, 0x01u, 0x80u, 0x00u, 0x46u, 0x01u, 0xC6u, 0x00u, 0x00u, \r
+ 0x00u, 0x46u, 0x00u, 0x80u, 0x22u, 0x01u, 0x08u, 0x5Eu, 0x08u, 0x39u, 0x21u, 0x06u, 0x01u, 0xC6u, 0x00u, 0x00u, \r
+ 0x01u, 0x00u, 0x00u, 0x00u, 0x01u, 0x77u, 0x00u, 0x08u, 0x40u, 0x42u, 0x00u, 0x00u, 0x10u, 0x04u, 0x00u, 0x20u, \r
+ 0x3Fu, 0x80u, 0x00u, 0x70u, 0x40u, 0x0Fu, 0x08u, 0x00u, 0x02u, 0x20u, 0x00u, 0x0Cu, 0x00u, 0x00u, 0x51u, 0x01u, \r
+ 0x63u, 0x02u, 0x40u, 0x00u, 0x05u, 0x0Eu, 0xFCu, 0xBDu, 0x3Du, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
+ 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x24u, 0x04u, 0x0Bu, 0x0Bu, 0x0Bu, 0x90u, 0x99u, 0x00u, 0x01u, \r
0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, \r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r
\r
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {\r
/* dest, src, size */\r
- {(void CYFAR *)(CYDEV_UCFG_B0_P3_U0_BASE), BS_UDB_1_2_1_CONFIG_VAL, 128u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B0_P3_U1_BASE), BS_UDB_1_2_0_CONFIG_VAL, 128u},\r
};\r
\r
uint8 CYDATA i;\r
.set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
+/* SCSI_CTL_PHASE */\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
+\r
/* USBFS_arb_int */\r
.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
/* SDCard_BSPIM */\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB06_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB06_ST\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB06_CTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB06_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB06_MSK\r
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB07_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB07_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB07_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB07_ST\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB07_08_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB07_08_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB07_08_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB07_08_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB07_08_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB07_08_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB07_08_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB07_08_MSK\r
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB07_CTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB07_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB07_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB07_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB07_MSK\r
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST\r
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_RxStsReg__4__POS, 4\r
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
.set SDCard_BSPIM_RxStsReg__6__POS, 6\r
.set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB07_MSK\r
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB07_ST\r
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB04_MSK\r
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB04_ST\r
.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01\r
.set SDCard_BSPIM_TxStsReg__0__POS, 0\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST\r
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02\r
.set SDCard_BSPIM_TxStsReg__1__POS, 1\r
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04\r
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_TxStsReg__4__POS, 4\r
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F\r
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB05_MSK\r
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB05_ST\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB06_07_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB06_07_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB06_07_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB06_07_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB06_07_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB06_07_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB06_A0_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB06_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB06_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB06_D0_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB06_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB06_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB06_F0_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB06_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB06_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK\r
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB07_08_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB07_08_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB07_08_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB07_08_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB07_08_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB07_08_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB07_A0_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB07_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB07_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB07_D0_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB07_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB07_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB07_F0_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB07_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB07_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
\r
/* USBFS_dp_int */\r
.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
-/* SCSI_CTL_IO */\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__0__MASK, 0x01\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
-\r
/* SCSI_In_DBx */\r
.set SCSI_In_DBx__0__AG, CYREG_PRT12_AG\r
.set SCSI_In_DBx__0__BIE, CYREG_PRT12_BIE\r
.set SD_Data_Clk__PM_STBY_MSK, 0x01\r
\r
/* SD_Init_Clk */\r
-.set SD_Init_Clk__CFG0, CYREG_CLKDIST_DCFG1_CFG0\r
-.set SD_Init_Clk__CFG1, CYREG_CLKDIST_DCFG1_CFG1\r
-.set SD_Init_Clk__CFG2, CYREG_CLKDIST_DCFG1_CFG2\r
+.set SD_Init_Clk__CFG0, CYREG_CLKDIST_DCFG2_CFG0\r
+.set SD_Init_Clk__CFG1, CYREG_CLKDIST_DCFG2_CFG1\r
+.set SD_Init_Clk__CFG2, CYREG_CLKDIST_DCFG2_CFG2\r
.set SD_Init_Clk__CFG2_SRC_SEL_MASK, 0x07\r
-.set SD_Init_Clk__INDEX, 0x01\r
+.set SD_Init_Clk__INDEX, 0x02\r
.set SD_Init_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2\r
-.set SD_Init_Clk__PM_ACT_MSK, 0x02\r
+.set SD_Init_Clk__PM_ACT_MSK, 0x04\r
.set SD_Init_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2\r
-.set SD_Init_Clk__PM_STBY_MSK, 0x02\r
+.set SD_Init_Clk__PM_STBY_MSK, 0x04\r
\r
/* scsiTarget */\r
.set scsiTarget_StatusReg__0__MASK, 0x01\r
.set scsiTarget_StatusReg__0__POS, 0\r
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL\r
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB14_15_ST\r
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST\r
.set scsiTarget_StatusReg__1__MASK, 0x02\r
.set scsiTarget_StatusReg__1__POS, 1\r
.set scsiTarget_StatusReg__2__MASK, 0x04\r
.set scsiTarget_StatusReg__3__MASK, 0x08\r
.set scsiTarget_StatusReg__3__POS, 3\r
.set scsiTarget_StatusReg__MASK, 0x0F\r
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB14_MSK\r
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB14_ACTL\r
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB14_ST\r
-.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL\r
-.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB13_14_ST\r
-.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB13_MSK\r
-.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL\r
-.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL\r
-.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB13_ACTL\r
-.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB13_ST_CTL\r
-.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB13_ST_CTL\r
-.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB13_ST\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB13_14_CTL\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB13_14_CTL\r
-.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB13_14_CTL\r
-.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB13_14_CTL\r
-.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB13_14_MSK\r
-.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB13_14_MSK\r
-.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB13_14_MSK\r
-.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB13_14_MSK\r
-.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_ACTL\r
-.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB13_CTL\r
-.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB13_ST_CTL\r
-.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB13_CTL\r
-.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB13_ST_CTL\r
-.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL\r
-.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB13_MSK\r
-.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL\r
-.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB13_14_A0\r
-.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB13_14_A1\r
-.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB13_14_D0\r
-.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB13_14_D1\r
-.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL\r
-.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB13_14_F0\r
-.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB13_14_F1\r
-.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB13_A0_A1\r
-.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB13_A0\r
-.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB13_A1\r
-.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB13_D0_D1\r
-.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB13_D0\r
-.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB13_D1\r
-.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB13_ACTL\r
-.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB13_F0_F1\r
-.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB13_F0\r
-.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB13_F1\r
-.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL\r
-.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL\r
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB12_MSK\r
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB12_ST\r
+.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
+.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST\r
+.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB03_MSK\r
+.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
+.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB03_ST_CTL\r
+.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB03_ST_CTL\r
+.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB03_ST\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
+.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
+.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
+.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK\r
+.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
+.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK\r
+.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
+.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
+.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB03_CTL\r
+.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL\r
+.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB03_CTL\r
+.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL\r
+.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB03_MSK\r
+.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB03_04_A0\r
+.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB03_04_A1\r
+.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB03_04_D0\r
+.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB03_04_D1\r
+.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
+.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB03_04_F0\r
+.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB03_04_F1\r
+.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB03_A0_A1\r
+.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB03_A0\r
+.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB03_A1\r
+.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB03_D0_D1\r
+.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB03_D0\r
+.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB03_D1\r
+.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
+.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB03_F0_F1\r
+.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB03_F0\r
+.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB03_F1\r
+.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
\r
/* SD_Clk_Ctl */\r
.set SD_Clk_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
.set SD_Clk_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL\r
.set SD_Clk_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL\r
\r
/* USBFS_ep_0 */\r
.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set SCSI_ATN__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
.set SCSI_ATN__SLW, CYREG_PRT12_SLW\r
\r
+/* SCSI_CLK */\r
+.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0\r
+.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1\r
+.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2\r
+.set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07\r
+.set SCSI_CLK__INDEX, 0x01\r
+.set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2\r
+.set SCSI_CLK__PM_ACT_MSK, 0x02\r
+.set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2\r
+.set SCSI_CLK__PM_STBY_MSK, 0x02\r
+\r
/* SCSI_Out */\r
.set SCSI_Out__0__AG, CYREG_PRT4_AG\r
.set SCSI_Out__0__AMUX, CYREG_PRT4_AMUX\r
.set SCSI_Out__BSY__PS, CYREG_PRT0_PS\r
.set SCSI_Out__BSY__SHIFT, 7\r
.set SCSI_Out__BSY__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__CD__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__CD__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__CD__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__CD__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__CD__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__CD__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__CD__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__CD__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__CD__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__CD__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__CD__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__CD__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__CD__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__CD__MASK, 0x04\r
-.set SCSI_Out__CD__PC, CYREG_PRT0_PC2\r
-.set SCSI_Out__CD__PORT, 0\r
-.set SCSI_Out__CD__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__CD__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__CD__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__CD__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__CD__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__CD__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__CD__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__CD__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__CD__SHIFT, 2\r
-.set SCSI_Out__CD__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__CD_raw__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__CD_raw__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__CD_raw__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__CD_raw__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__CD_raw__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__CD_raw__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__CD_raw__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__CD_raw__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__CD_raw__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__CD_raw__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__CD_raw__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__CD_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__CD_raw__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__CD_raw__MASK, 0x04\r
+.set SCSI_Out__CD_raw__PC, CYREG_PRT0_PC2\r
+.set SCSI_Out__CD_raw__PORT, 0\r
+.set SCSI_Out__CD_raw__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__CD_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__CD_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__CD_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__CD_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__CD_raw__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__CD_raw__SHIFT, 2\r
+.set SCSI_Out__CD_raw__SLW, CYREG_PRT0_SLW\r
.set SCSI_Out__DBP_raw__AG, CYREG_PRT4_AG\r
.set SCSI_Out__DBP_raw__AMUX, CYREG_PRT4_AMUX\r
.set SCSI_Out__DBP_raw__BIE, CYREG_PRT4_BIE\r
.set SCSI_Out__IO_raw__PS, CYREG_PRT0_PS\r
.set SCSI_Out__IO_raw__SHIFT, 0\r
.set SCSI_Out__IO_raw__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__MSG__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__MSG__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__MSG__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__MSG__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__MSG__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__MSG__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__MSG__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__MSG__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__MSG__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__MSG__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__MSG__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__MSG__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__MSG__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__MSG__MASK, 0x10\r
-.set SCSI_Out__MSG__PC, CYREG_PRT0_PC4\r
-.set SCSI_Out__MSG__PORT, 0\r
-.set SCSI_Out__MSG__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__MSG__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__MSG__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__MSG__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__MSG__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__MSG__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__MSG__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__MSG__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__MSG__SHIFT, 4\r
-.set SCSI_Out__MSG__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__MSG_raw__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__MSG_raw__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__MSG_raw__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__MSG_raw__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__MSG_raw__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__MSG_raw__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__MSG_raw__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__MSG_raw__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__MSG_raw__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__MSG_raw__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__MSG_raw__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__MSG_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__MSG_raw__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__MSG_raw__MASK, 0x10\r
+.set SCSI_Out__MSG_raw__PC, CYREG_PRT0_PC4\r
+.set SCSI_Out__MSG_raw__PORT, 0\r
+.set SCSI_Out__MSG_raw__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__MSG_raw__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__MSG_raw__SHIFT, 4\r
+.set SCSI_Out__MSG_raw__SLW, CYREG_PRT0_SLW\r
.set SCSI_Out__REQ__AG, CYREG_PRT0_AG\r
.set SCSI_Out__REQ__AMUX, CYREG_PRT0_AMUX\r
.set SCSI_Out__REQ__BIE, CYREG_PRT0_BIE\r
.set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG\r
.set CYDEV_DMA_CHANNELS_AVAILABLE, 24\r
.set CYDEV_ECC_ENABLE, 0\r
-.set CYDEV_HEAP_SIZE, 0x1000\r
+.set CYDEV_HEAP_SIZE, 0x0256\r
.set CYDEV_INSTRUCT_CACHE_ENABLED, 1\r
.set CYDEV_INTR_RISING, 0x00000000\r
.set CYDEV_PROJ_TYPE, 2\r
.set CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER, 3\r
.set CYDEV_PROJ_TYPE_STANDARD, 0\r
.set CYDEV_PROTECTION_ENABLE, 0\r
-.set CYDEV_STACK_SIZE, 0x4000\r
+.set CYDEV_STACK_SIZE, 0x2000\r
.set CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP, 1\r
.set CYDEV_USE_BUNDLED_CMSIS, 1\r
.set CYDEV_VARIABLE_VDDA, 0\r
USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
+/* SCSI_CTL_PHASE */\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+\r
/* USBFS_arb_int */\r
USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
/* SDCard_BSPIM */\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB07_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB07_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB07_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB07_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB07_MSK\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST\r
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0\r
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0\r
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1\r
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1\r
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0\r
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1\r
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB07_08_A0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB07_08_A1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB07_08_D0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB07_08_D1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB07_08_F0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB07_08_F1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB07_A0_A1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB07_A0\r
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB07_A1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB07_D0_D1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB07_D0\r
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB07_D1\r
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB07_F0_F1\r
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB07_F0\r
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB07_F1\r
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
\r
/* USBFS_dp_int */\r
USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
-/* SCSI_CTL_IO */\r
-SCSI_CTL_IO_Sync_ctrl_reg__0__MASK EQU 0x01\r
-SCSI_CTL_IO_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
-\r
/* SCSI_In_DBx */\r
SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG\r
SCSI_In_DBx__0__BIE EQU CYREG_PRT12_BIE\r
SD_Data_Clk__PM_STBY_MSK EQU 0x01\r
\r
/* SD_Init_Clk */\r
-SD_Init_Clk__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0\r
-SD_Init_Clk__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1\r
-SD_Init_Clk__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2\r
+SD_Init_Clk__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0\r
+SD_Init_Clk__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1\r
+SD_Init_Clk__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2\r
SD_Init_Clk__CFG2_SRC_SEL_MASK EQU 0x07\r
-SD_Init_Clk__INDEX EQU 0x01\r
+SD_Init_Clk__INDEX EQU 0x02\r
SD_Init_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
-SD_Init_Clk__PM_ACT_MSK EQU 0x02\r
+SD_Init_Clk__PM_ACT_MSK EQU 0x04\r
SD_Init_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
-SD_Init_Clk__PM_STBY_MSK EQU 0x02\r
+SD_Init_Clk__PM_STBY_MSK EQU 0x04\r
\r
/* scsiTarget */\r
scsiTarget_StatusReg__0__MASK EQU 0x01\r
scsiTarget_StatusReg__0__POS EQU 0\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST\r
scsiTarget_StatusReg__1__MASK EQU 0x02\r
scsiTarget_StatusReg__1__POS EQU 1\r
scsiTarget_StatusReg__2__MASK EQU 0x04\r
scsiTarget_StatusReg__3__MASK EQU 0x08\r
scsiTarget_StatusReg__3__POS EQU 3\r
scsiTarget_StatusReg__MASK EQU 0x0F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB14_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB14_ST\r
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST\r
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB13_MSK\r
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB13_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB13_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB13_ST\r
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL\r
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK\r
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK\r
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB13_CTL\r
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL\r
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB13_CTL\r
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL\r
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB13_MSK\r
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB13_14_A0\r
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB13_14_A1\r
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB13_14_D0\r
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB13_14_D1\r
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB13_14_F0\r
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB13_14_F1\r
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB13_A0_A1\r
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB13_A0\r
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB13_A1\r
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB13_D0_D1\r
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB13_D0\r
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB13_D1\r
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB13_F0_F1\r
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB13_F0\r
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB13_F1\r
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST\r
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST\r
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK\r
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB03_ST\r
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB03_CTL\r
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB03_CTL\r
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB03_MSK\r
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB03_04_A0\r
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB03_04_A1\r
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB03_04_D0\r
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB03_04_D1\r
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB03_04_F0\r
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB03_04_F1\r
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB03_A0_A1\r
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB03_A0\r
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB03_A1\r
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB03_D0_D1\r
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB03_D0\r
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB03_D1\r
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB03_F0_F1\r
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB03_F0\r
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB03_F1\r
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
\r
/* SD_Clk_Ctl */\r
SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
\r
/* USBFS_ep_0 */\r
USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SCSI_ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
SCSI_ATN__SLW EQU CYREG_PRT12_SLW\r
\r
+/* SCSI_CLK */\r
+SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0\r
+SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1\r
+SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2\r
+SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07\r
+SCSI_CLK__INDEX EQU 0x01\r
+SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
+SCSI_CLK__PM_ACT_MSK EQU 0x02\r
+SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
+SCSI_CLK__PM_STBY_MSK EQU 0x02\r
+\r
/* SCSI_Out */\r
SCSI_Out__0__AG EQU CYREG_PRT4_AG\r
SCSI_Out__0__AMUX EQU CYREG_PRT4_AMUX\r
SCSI_Out__BSY__PS EQU CYREG_PRT0_PS\r
SCSI_Out__BSY__SHIFT EQU 7\r
SCSI_Out__BSY__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__CD__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__CD__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__CD__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__CD__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__CD__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__CD__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__CD__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__CD__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__CD__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__CD__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__CD__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__CD__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__CD__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__CD__MASK EQU 0x04\r
-SCSI_Out__CD__PC EQU CYREG_PRT0_PC2\r
-SCSI_Out__CD__PORT EQU 0\r
-SCSI_Out__CD__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__CD__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__CD__SHIFT EQU 2\r
-SCSI_Out__CD__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__CD_raw__MASK EQU 0x04\r
+SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC2\r
+SCSI_Out__CD_raw__PORT EQU 0\r
+SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__CD_raw__SHIFT EQU 2\r
+SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW\r
SCSI_Out__DBP_raw__AG EQU CYREG_PRT4_AG\r
SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT4_AMUX\r
SCSI_Out__DBP_raw__BIE EQU CYREG_PRT4_BIE\r
SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS\r
SCSI_Out__IO_raw__SHIFT EQU 0\r
SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__MSG__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__MSG__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__MSG__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__MSG__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__MSG__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__MSG__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__MSG__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__MSG__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__MSG__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__MSG__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__MSG__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__MSG__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__MSG__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__MSG__MASK EQU 0x10\r
-SCSI_Out__MSG__PC EQU CYREG_PRT0_PC4\r
-SCSI_Out__MSG__PORT EQU 0\r
-SCSI_Out__MSG__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__MSG__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__MSG__SHIFT EQU 4\r
-SCSI_Out__MSG__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__MSG_raw__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__MSG_raw__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__MSG_raw__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__MSG_raw__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__MSG_raw__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__MSG_raw__MASK EQU 0x10\r
+SCSI_Out__MSG_raw__PC EQU CYREG_PRT0_PC4\r
+SCSI_Out__MSG_raw__PORT EQU 0\r
+SCSI_Out__MSG_raw__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__MSG_raw__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__MSG_raw__SHIFT EQU 4\r
+SCSI_Out__MSG_raw__SLW EQU CYREG_PRT0_SLW\r
SCSI_Out__REQ__AG EQU CYREG_PRT0_AG\r
SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX\r
SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE\r
CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG\r
CYDEV_DMA_CHANNELS_AVAILABLE EQU 24\r
CYDEV_ECC_ENABLE EQU 0\r
-CYDEV_HEAP_SIZE EQU 0x1000\r
+CYDEV_HEAP_SIZE EQU 0x0256\r
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1\r
CYDEV_INTR_RISING EQU 0x00000000\r
CYDEV_PROJ_TYPE EQU 2\r
CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3\r
CYDEV_PROJ_TYPE_STANDARD EQU 0\r
CYDEV_PROTECTION_ENABLE EQU 0\r
-CYDEV_STACK_SIZE EQU 0x4000\r
+CYDEV_STACK_SIZE EQU 0x2000\r
CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP EQU 1\r
CYDEV_USE_BUNDLED_CMSIS EQU 1\r
CYDEV_VARIABLE_VDDA EQU 0\r
USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
+; SCSI_CTL_PHASE\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+\r
; USBFS_arb_int\r
USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
; SDCard_BSPIM\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB07_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB07_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB07_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB07_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB07_MSK\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST\r
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0\r
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0\r
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1\r
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1\r
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0\r
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1\r
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB07_08_A0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB07_08_A1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB07_08_D0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB07_08_D1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB07_08_F0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB07_08_F1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB07_A0_A1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB07_A0\r
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB07_A1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB07_D0_D1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB07_D0\r
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB07_D1\r
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB07_F0_F1\r
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB07_F0\r
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB07_F1\r
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
\r
; USBFS_dp_int\r
USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
-; SCSI_CTL_IO\r
-SCSI_CTL_IO_Sync_ctrl_reg__0__MASK EQU 0x01\r
-SCSI_CTL_IO_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
-\r
; SCSI_In_DBx\r
SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG\r
SCSI_In_DBx__0__BIE EQU CYREG_PRT12_BIE\r
SD_Data_Clk__PM_STBY_MSK EQU 0x01\r
\r
; SD_Init_Clk\r
-SD_Init_Clk__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0\r
-SD_Init_Clk__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1\r
-SD_Init_Clk__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2\r
+SD_Init_Clk__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0\r
+SD_Init_Clk__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1\r
+SD_Init_Clk__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2\r
SD_Init_Clk__CFG2_SRC_SEL_MASK EQU 0x07\r
-SD_Init_Clk__INDEX EQU 0x01\r
+SD_Init_Clk__INDEX EQU 0x02\r
SD_Init_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
-SD_Init_Clk__PM_ACT_MSK EQU 0x02\r
+SD_Init_Clk__PM_ACT_MSK EQU 0x04\r
SD_Init_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
-SD_Init_Clk__PM_STBY_MSK EQU 0x02\r
+SD_Init_Clk__PM_STBY_MSK EQU 0x04\r
\r
; scsiTarget\r
scsiTarget_StatusReg__0__MASK EQU 0x01\r
scsiTarget_StatusReg__0__POS EQU 0\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST\r
scsiTarget_StatusReg__1__MASK EQU 0x02\r
scsiTarget_StatusReg__1__POS EQU 1\r
scsiTarget_StatusReg__2__MASK EQU 0x04\r
scsiTarget_StatusReg__3__MASK EQU 0x08\r
scsiTarget_StatusReg__3__POS EQU 3\r
scsiTarget_StatusReg__MASK EQU 0x0F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB14_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB14_ST\r
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST\r
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB13_MSK\r
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB13_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB13_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB13_ST\r
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL\r
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK\r
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK\r
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB13_CTL\r
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL\r
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB13_CTL\r
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL\r
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB13_MSK\r
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB13_14_A0\r
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB13_14_A1\r
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB13_14_D0\r
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB13_14_D1\r
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB13_14_F0\r
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB13_14_F1\r
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB13_A0_A1\r
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB13_A0\r
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB13_A1\r
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB13_D0_D1\r
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB13_D0\r
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB13_D1\r
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB13_F0_F1\r
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB13_F0\r
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB13_F1\r
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST\r
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST\r
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK\r
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB03_ST\r
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB03_CTL\r
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB03_CTL\r
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB03_MSK\r
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB03_04_A0\r
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB03_04_A1\r
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB03_04_D0\r
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB03_04_D1\r
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB03_04_F0\r
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB03_04_F1\r
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB03_A0_A1\r
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB03_A0\r
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB03_A1\r
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB03_D0_D1\r
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB03_D0\r
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB03_D1\r
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB03_F0_F1\r
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB03_F0\r
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB03_F1\r
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
\r
; SD_Clk_Ctl\r
SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
\r
; USBFS_ep_0\r
USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SCSI_ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
SCSI_ATN__SLW EQU CYREG_PRT12_SLW\r
\r
+; SCSI_CLK\r
+SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0\r
+SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1\r
+SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2\r
+SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07\r
+SCSI_CLK__INDEX EQU 0x01\r
+SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
+SCSI_CLK__PM_ACT_MSK EQU 0x02\r
+SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
+SCSI_CLK__PM_STBY_MSK EQU 0x02\r
+\r
; SCSI_Out\r
SCSI_Out__0__AG EQU CYREG_PRT4_AG\r
SCSI_Out__0__AMUX EQU CYREG_PRT4_AMUX\r
SCSI_Out__BSY__PS EQU CYREG_PRT0_PS\r
SCSI_Out__BSY__SHIFT EQU 7\r
SCSI_Out__BSY__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__CD__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__CD__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__CD__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__CD__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__CD__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__CD__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__CD__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__CD__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__CD__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__CD__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__CD__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__CD__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__CD__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__CD__MASK EQU 0x04\r
-SCSI_Out__CD__PC EQU CYREG_PRT0_PC2\r
-SCSI_Out__CD__PORT EQU 0\r
-SCSI_Out__CD__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__CD__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__CD__SHIFT EQU 2\r
-SCSI_Out__CD__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__CD_raw__MASK EQU 0x04\r
+SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC2\r
+SCSI_Out__CD_raw__PORT EQU 0\r
+SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__CD_raw__SHIFT EQU 2\r
+SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW\r
SCSI_Out__DBP_raw__AG EQU CYREG_PRT4_AG\r
SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT4_AMUX\r
SCSI_Out__DBP_raw__BIE EQU CYREG_PRT4_BIE\r
SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS\r
SCSI_Out__IO_raw__SHIFT EQU 0\r
SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__MSG__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__MSG__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__MSG__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__MSG__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__MSG__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__MSG__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__MSG__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__MSG__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__MSG__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__MSG__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__MSG__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__MSG__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__MSG__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__MSG__MASK EQU 0x10\r
-SCSI_Out__MSG__PC EQU CYREG_PRT0_PC4\r
-SCSI_Out__MSG__PORT EQU 0\r
-SCSI_Out__MSG__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__MSG__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__MSG__SHIFT EQU 4\r
-SCSI_Out__MSG__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__MSG_raw__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__MSG_raw__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__MSG_raw__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__MSG_raw__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__MSG_raw__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__MSG_raw__MASK EQU 0x10\r
+SCSI_Out__MSG_raw__PC EQU CYREG_PRT0_PC4\r
+SCSI_Out__MSG_raw__PORT EQU 0\r
+SCSI_Out__MSG_raw__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__MSG_raw__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__MSG_raw__SHIFT EQU 4\r
+SCSI_Out__MSG_raw__SLW EQU CYREG_PRT0_SLW\r
SCSI_Out__REQ__AG EQU CYREG_PRT0_AG\r
SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX\r
SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE\r
CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG\r
CYDEV_DMA_CHANNELS_AVAILABLE EQU 24\r
CYDEV_ECC_ENABLE EQU 0\r
-CYDEV_HEAP_SIZE EQU 0x1000\r
+CYDEV_HEAP_SIZE EQU 0x0256\r
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1\r
CYDEV_INTR_RISING EQU 0x00000000\r
CYDEV_PROJ_TYPE EQU 2\r
CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3\r
CYDEV_PROJ_TYPE_STANDARD EQU 0\r
CYDEV_PROTECTION_ENABLE EQU 0\r
-CYDEV_STACK_SIZE EQU 0x4000\r
+CYDEV_STACK_SIZE EQU 0x2000\r
CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP EQU 1\r
CYDEV_USE_BUNDLED_CMSIS EQU 1\r
CYDEV_VARIABLE_VDDA EQU 0\r
#include <SD_DAT2.h>\r
#include <SD_DAT1_aliases.h>\r
#include <SD_DAT1.h>\r
-#include <SCSI_CTL_IO.h>\r
+#include <SCSI_CTL_PHASE.h>\r
#include <SCSI_In_aliases.h>\r
#include <SCSI_Out_aliases.h>\r
#include <CFG_EEPROM.h>\r
#include <SD_SCK.h>\r
#include <SD_MOSI_aliases.h>\r
#include <SD_MOSI.h>\r
+#include <SCSI_CLK.h>\r
#include <SCSI_RST_aliases.h>\r
#include <SCSI_RST.h>\r
#include <SCSI_ATN_aliases.h>\r
<?xml version="1.0" encoding="utf-8"?>\r
<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">\r
- <block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_RST" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_ATN" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_Clk_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SD_Clk_Ctl_CONTROL_REG" address="0x4000647A" bitWidth="8" desc="" />\r
+ <register name="SD_Clk_Ctl_CONTROL_REG" address="0x40006471" bitWidth="8" desc="" />\r
</block>\r
<block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_CTL_IO" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SCSI_CTL_IO_CONTROL_REG" address="0x4000647B" bitWidth="8" desc="" />\r
+ <block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+ <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" />\r
</block>\r
</blockRegMap>
\ No newline at end of file
<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">\r
<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">\r
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CTL_IO" persistent="">\r
-<Hidden v="False" />\r
+<Hidden v="True" />\r
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">\r
<dependencies>\r
<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">\r
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CTL_IO.c" persistent=".\Generated_Source\PSoC5\SCSI_CTL_IO.c">\r
-<Hidden v="False" />\r
+<Hidden v="True" />\r
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
<build_action v="ARM_C_FILE" />\r
<PropertyDeltas />\r
<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">\r
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CTL_IO.h" persistent=".\Generated_Source\PSoC5\SCSI_CTL_IO.h">\r
-<Hidden v="False" />\r
+<Hidden v="True" />\r
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
<build_action v="NONE" />\r
<PropertyDeltas />\r
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
<filters />\r
</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">\r
+<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CTL_PHASE" persistent="">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">\r
+<dependencies>\r
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">\r
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CTL_PHASE.c" persistent=".\Generated_Source\PSoC5\SCSI_CTL_PHASE.c">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<build_action v="ARM_C_FILE" />\r
+<PropertyDeltas />\r
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>\r
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">\r
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CTL_PHASE.h" persistent=".\Generated_Source\PSoC5\SCSI_CTL_PHASE.h">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<build_action v="NONE" />\r
+<PropertyDeltas />\r
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>\r
+</dependencies>\r
+</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>\r
+</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
+<filters />\r
+</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">\r
+<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CLK" persistent="">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">\r
+<dependencies>\r
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">\r
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CLK.c" persistent=".\Generated_Source\PSoC5\SCSI_CLK.c">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<build_action v="ARM_C_FILE" />\r
+<PropertyDeltas />\r
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>\r
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">\r
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CLK.h" persistent=".\Generated_Source\PSoC5\SCSI_CLK.h">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<build_action v="NONE" />\r
+<PropertyDeltas />\r
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>\r
+</dependencies>\r
+</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>\r
+</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
+<filters />\r
+</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>\r
</dependencies>\r
</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>\r
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
<BootloaderTag hexFile="" elfFile="" />\r
<current_generation v="2" />\r
</CyGuid_fec8f9e8-2365-4bdb-96d3-a4380222e01b>\r
-</CyXmlSerializer>\r
+</CyXmlSerializer>
\ No newline at end of file
<peripheral>\r
<name>SD_Clk_Ctl</name>\r
<description>No description available</description>\r
- <baseAddress>0x4000647A</baseAddress>\r
+ <baseAddress>0x40006471</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x1</size>\r
</registers>\r
</peripheral>\r
<peripheral>\r
- <name>SCSI_CTL_IO</name>\r
+ <name>SCSI_CTL_PHASE</name>\r
<description>No description available</description>\r
- <baseAddress>0x4000647B</baseAddress>\r
+ <baseAddress>0x40006472</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x1</size>\r
</addressBlock>\r
<registers>\r
<register>\r
- <name>SCSI_CTL_IO_CONTROL_REG</name>\r
+ <name>SCSI_CTL_PHASE_CONTROL_REG</name>\r
<description>No description available</description>\r
<addressOffset>0x0</addressOffset>\r
<size>8</size>\r
// The data output is valid during the DESKEW_INIT phase as well,\r
// so we subtract 1.\r
// D1 = [0.000000055 / (1 / clk)] - 1\r
-cy_psoc3_dp #(.d1_init(3), \r
+cy_psoc3_dp #(.d1_init(1), \r
.cy_dpconfig(\r
{\r
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\r
#include <string.h>\r
\r
// CYDEV_EEPROM_ROW_SIZE == 16.\r
-static char magic[CYDEV_EEPROM_ROW_SIZE] = "codesrc_00000002";\r
+static const char magic[CYDEV_EEPROM_ROW_SIZE] = "codesrc_00000002";\r
\r
// Config shadow RAM (copy of EEPROM)\r
static Config shadow =\r
0, // SCSI ID\r
" codesrc", // vendor (68k Apple Drive Setup: Set to " SEAGATE")\r
" SCSI2SD", //prodId (68k Apple Drive Setup: Set to " ST225N")\r
- " 3.3", // revision (68k Apple Drive Setup: Set to "1.0 ")\r
+ " 3.4", // revision (68k Apple Drive Setup: Set to "1.0 ")\r
1, // enable parity\r
1, // enable unit attention,\r
0, // RESERVED\r
{\r
memcpy(&shadow, eeprom, sizeof(shadow));\r
}\r
+\r
config = &shadow;\r
CFG_EEPROM_Stop();\r
\r
\r
SCSI_ClearPin(SCSI_Out_BSY);\r
// We now have a Bus Clear Delay of 800ns to release remaining signals.\r
- SCSI_ClearPin(SCSI_Out_MSG);\r
- SCSI_ClearPin(SCSI_Out_CD);\r
- SCSI_CTL_IO_Write(0);\r
+ SCSI_CTL_PHASE_Write(0);\r
\r
// Wait for the initiator to cease driving signals\r
// Bus settle delay + bus clear delay = 1200ns\r
\r
void scsiEnterPhase(int phase)\r
{\r
- if (phase > 0)\r
+ int newPhase = phase > 0 ? phase : 0;\r
+ if (newPhase != SCSI_CTL_PHASE_Read())\r
{\r
- if (phase & __scsiphase_msg)\r
- {\r
- SCSI_SetPin(SCSI_Out_MSG);\r
- }\r
- else\r
- {\r
- SCSI_ClearPin(SCSI_Out_MSG);\r
- }\r
-\r
- if (phase & __scsiphase_cd)\r
- {\r
- SCSI_SetPin(SCSI_Out_CD);\r
- }\r
- else\r
- {\r
- SCSI_ClearPin(SCSI_Out_CD);\r
- }\r
-\r
- SCSI_CTL_IO_Write(phase & __scsiphase_io ? 1 : 0);\r
- }\r
- else\r
- {\r
- SCSI_ClearPin(SCSI_Out_MSG);\r
- SCSI_ClearPin(SCSI_Out_CD);\r
- SCSI_CTL_IO_Write(0);\r
+ SCSI_CTL_PHASE_Write(phase > 0 ? phase : 0);\r
+ busSettleDelay();\r
}\r
- busSettleDelay();\r
}\r
\r
void scsiPhyReset()\r
// duration.\r
SCSI_SetPin(SCSI_Out_RST);\r
\r
- SCSI_CTL_IO_Write(0);\r
+ SCSI_CTL_PHASE_Write(0);\r
SCSI_ClearPin(SCSI_Out_ATN);\r
SCSI_ClearPin(SCSI_Out_BSY);\r
SCSI_ClearPin(SCSI_Out_ACK);\r
SCSI_ClearPin(SCSI_Out_RST);\r
SCSI_ClearPin(SCSI_Out_SEL);\r
SCSI_ClearPin(SCSI_Out_REQ);\r
- SCSI_ClearPin(SCSI_Out_MSG);\r
- SCSI_ClearPin(SCSI_Out_CD);\r
\r
// Allow the FIFOs to fill up again.\r
SCSI_ClearPin(SCSI_Out_RST);\r
return;\r
}\r
\r
- // Don't do a bus settle delay if we're already in the correct phase.\r
- if (transfer.currentBlock == 0)\r
- {\r
- scsiEnterPhase(DATA_IN);\r
- }\r
+ scsiEnterPhase(DATA_IN);\r
\r
// Quickly seed the FIFO\r
prep = 4;\r
int result, maxWait;\r
uint8 dataToken;\r
\r
- // Don't do a bus settle delay if we're already in the correct phase.\r
- if (transfer.currentBlock == 0)\r
- {\r
- scsiEnterPhase(DATA_OUT);\r
- }\r
+ scsiEnterPhase(DATA_OUT);\r
\r
sdSpiByte(0xFC); // MULTIPLE byte start token\r
\r
projects / SCSI2SD.git / commitdiff