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[SCSI2SD-V6.git] / src / firmware / scsiPhy.c
1 // Copyright (C) 2013 Michael McMaster <michael@codesrc.com>
2 //
3 // This file is part of SCSI2SD.
4 //
5 // SCSI2SD is free software: you can redistribute it and/or modify
6 // it under the terms of the GNU General Public License as published by
7 // the Free Software Foundation, either version 3 of the License, or
8 // (at your option) any later version.
9 //
10 // SCSI2SD is distributed in the hope that it will be useful,
11 // but WITHOUT ANY WARRANTY; without even the implied warranty of
12 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 // GNU General Public License for more details.
14 //
15 // You should have received a copy of the GNU General Public License
16 // along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
17
18 #include "stm32f2xx.h"
19 #include "stm32f2xx_hal.h"
20 #include "stm32f2xx_hal_dma.h"
21
22 #include "scsi.h"
23 #include "scsiPhy.h"
24 #include "trace.h"
25 #include "time.h"
26 #include "fpga.h"
27 #include "led.h"
28
29 #include <string.h>
30
31 // Time until we consider ourselves selected
32 // 400ns at 108MHz
33 #define SCSI_DEFAULT_SELECTION 43
34 #define SCSI_FAST_SELECTION 5
35
36 // async.
37 // Assumes a 108MHz fpga clock.
38 // 2:0 Deskew count, 55ns
39 // 6:4 Hold count, 53ns
40 // 3:0 Assertion count, 80ns
41 #define SCSI_DEFAULT_DESKEW 0x6
42 #define SCSI_DEFAULT_TIMING ((0x6 << 4) | 0x9)
43
44 // 3.125MB/s (80 period) to < 10MB/s sync
45 // Assumes a 108MHz fpga clock. (9 ns)
46 // (((period * 4) / 2) * 0.8) / 9
47 // Done using 3 fixed point math.
48 // 2:0 Deskew count, 55ns normal, or 25ns if faster than 5.5MB/s
49 // 6:4 Hold count, 53ns normal, or 33ns if faster than 5.5MB/s
50 // 3:0 Assertion count, variable
51 #define SCSI_SYNC_DESKEW(period) (period < 45 ? SCSI_FAST10_DESKEW : SCSI_DEFAULT_DESKEW)
52 #define SCSI_SYNC_TIMING(period) (((period < 45 ? 0x4 : 0x6) << 4) | ((((((int)period) * 177) + 750)/1000) & 0xF))
53
54 // 10MB/s
55 // 2:0 Deskew count, 25ns
56 // 6:4 Hold count, 33ns
57 // 3:0 Assertion count, 30ns
58 // We want deskew + hold + assert + 3 to add up to 11 clocks
59 // the fpga code has 1 clock of overhead when transitioning from deskew to
60 // assert to hold
61 #define SCSI_FAST10_DESKEW 2
62 #define SCSI_FAST10_TIMING ((0x3 << 4) | 0x3)
63
64 // 20MB/s
65 // 2:0 Deskew count, 12ns
66 // 6:4 Hold count, 17ns
67 // 3:0 Assertion count, 15ns
68 #define SCSI_FAST20_DESKEW 1
69 #define SCSI_FAST20_TIMING ((0x2 << 4) | 0x2)
70
71 // Private DMA variables.
72 static int dmaInProgress = 0;
73
74 static DMA_HandleTypeDef memToFSMC;
75 static DMA_HandleTypeDef fsmcToMem;
76
77
78 volatile uint8_t scsiRxDMAComplete;
79 volatile uint8_t scsiTxDMAComplete;
80
81 uint8_t scsiPhyFifoSel = 0; // global
82
83 // scsi IRQ handler is initialised by the STM32 HAL. Connected to
84 // PE4
85 // Note: naming is important to ensure this function is listed in the
86 // vector table.
87 void EXTI4_IRQHandler()
88 {
89 traceIrq(trace_scsiResetISR);
90
91 // Make sure that interrupt flag is set
92 if (__HAL_GPIO_EXTI_GET_IT(GPIO_PIN_4) != RESET) {
93
94 // Clear interrupt flag
95 __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_4);
96
97 scsiDev.resetFlag = scsiDev.resetFlag || scsiStatusRST();
98
99 // selFlag is required for Philips P2000C which releases it after 600ns
100 // without waiting for BSY.
101 // Also required for some early Mac Plus roms
102 scsiDev.selFlag = *SCSI_STS_SELECTED;
103 }
104
105 __SEV(); // Set event. See corresponding __WFE() calls.
106 }
107
108 static void assertFail()
109 {
110 while (1)
111 {
112 s2s_ledOn();
113 s2s_delay_ms(100);
114 s2s_ledOff();
115 s2s_delay_ms(100);
116 }
117 }
118
119 void
120 scsiSetDataCount(uint32_t count)
121 {
122 *SCSI_DATA_CNT_HI = count >> 8;
123 *SCSI_DATA_CNT_LO = count & 0xff;
124 *SCSI_DATA_CNT_SET = 1;
125 }
126
127 uint8_t
128 scsiReadByte(void)
129 {
130 #if FIFODEBUG
131 if (!scsiPhyFifoAltEmpty()) {
132 // Force a lock-up.
133 assertFail();
134 }
135 #endif
136 scsiSetDataCount(1);
137
138 trace(trace_spinPhyRxFifo);
139 while (!scsiPhyComplete() && likely(!scsiDev.resetFlag))
140 {
141 __WFE(); // Wait for event
142 }
143 scsiPhyFifoFlip();
144 uint8_t val = scsiPhyRx();
145 // TODO scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read();
146
147 #if FIFODEBUG
148 if (!scsiPhyFifoEmpty()) {
149 int j = 0;
150 uint8_t k __attribute((unused));
151 while (!scsiPhyFifoEmpty()) { k = scsiPhyRx(); ++j; }
152
153 // Force a lock-up.
154 assertFail();
155 }
156 #endif
157 return val;
158 }
159
160
161 static void
162 scsiReadPIO(uint8_t* data, uint32_t count)
163 {
164 uint16_t* fifoData = (uint16_t*)data;
165
166 for (int i = 0; i < (count + 1) / 2; ++i)
167 {
168 fifoData[i] = scsiPhyRx(); // TODO ASSUMES LITTLE ENDIAN
169 }
170 }
171
172 void
173 scsiReadDMA(uint8_t* data, uint32_t count)
174 {
175 // Prepare DMA transfer
176 dmaInProgress = 1;
177 trace(trace_doRxSingleDMA);
178
179 scsiTxDMAComplete = 1; // TODO not used much
180 scsiRxDMAComplete = 0; // TODO not used much
181
182 HAL_DMA_Start(
183 &fsmcToMem,
184 (uint32_t) SCSI_FIFO_DATA,
185 (uint32_t) data,
186 (count + 1) / 2);
187 }
188
189 int
190 scsiReadDMAPoll()
191 {
192 int complete = __HAL_DMA_GET_COUNTER(&fsmcToMem) == 0;
193 complete = complete && (HAL_DMA_PollForTransfer(&fsmcToMem, HAL_DMA_FULL_TRANSFER, 0xffffffff) == HAL_OK);
194 if (complete)
195 {
196 scsiTxDMAComplete = 1; // TODO MM FIX IRQ
197 scsiRxDMAComplete = 1;
198
199 dmaInProgress = 0;
200 #if 0
201 // TODO MM scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read();
202 #endif
203 return 1;
204
205 }
206 else
207 {
208 return 0;
209 }
210 }
211
212 void
213 scsiRead(uint8_t* data, uint32_t count, int* parityError)
214 {
215 int i = 0;
216 *parityError = 0;
217
218
219 uint32_t chunk = ((count - i) > SCSI_FIFO_DEPTH)
220 ? SCSI_FIFO_DEPTH : (count - i);
221 #ifdef SCSI_FSMC_DMA
222 if (chunk >= 16)
223 {
224 // DMA is doing 32bit transfers.
225 chunk = chunk & 0xFFFFFFF8;
226 }
227 #endif
228 scsiSetDataCount(chunk);
229
230 while (i < count && likely(!scsiDev.resetFlag))
231 {
232 while (!scsiPhyComplete() && likely(!scsiDev.resetFlag))
233 {
234 __WFE(); // Wait for event
235 }
236 *parityError |= scsiParityError();
237 scsiPhyFifoFlip();
238
239 uint32_t nextChunk = ((count - i - chunk) > SCSI_FIFO_DEPTH)
240 ? SCSI_FIFO_DEPTH : (count - i - chunk);
241 #ifdef SCSI_FSMC_DMA
242 if (nextChunk >= 16)
243 {
244 nextChunk = nextChunk & 0xFFFFFFF8;
245 }
246 #endif
247 if (nextChunk > 0)
248 {
249 scsiSetDataCount(nextChunk);
250 }
251
252 #ifdef SCSI_FSMC_DMA
253 if (chunk < 16)
254 #endif
255 {
256 scsiReadPIO(data + i, chunk);
257 }
258 #ifdef SCSI_FSMC_DMA
259 else
260 {
261 scsiReadDMA(data + i, chunk);
262
263 trace(trace_spinReadDMAPoll);
264
265 while (!scsiReadDMAPoll() && likely(!scsiDev.resetFlag))
266 {
267 };
268 }
269 #endif
270
271
272 i += chunk;
273 chunk = nextChunk;
274 }
275 #if FIFODEBUG
276 if (!scsiPhyFifoEmpty() || !scsiPhyFifoAltEmpty()) {
277 int j = 0;
278 while (!scsiPhyFifoEmpty()) { scsiPhyRx(); ++j; }
279 scsiPhyFifoFlip();
280 int k = 0;
281 while (!scsiPhyFifoEmpty()) { scsiPhyRx(); ++k; }
282 // Force a lock-up.
283 assertFail();
284 }
285 #endif
286 }
287
288 void
289 scsiWriteByte(uint8_t value)
290 {
291 #if FIFODEBUG
292 if (!scsiPhyFifoEmpty()) {
293 // Force a lock-up.
294 assertFail();
295 }
296 #endif
297 trace(trace_spinPhyTxFifo);
298 scsiPhyTx(value);
299 scsiPhyFifoFlip();
300
301 scsiSetDataCount(1);
302
303 trace(trace_spinTxComplete);
304 while (!scsiPhyComplete() && likely(!scsiDev.resetFlag))
305 {
306 __WFE(); // Wait for event
307 }
308
309 #if FIFODEBUG
310 if (!scsiPhyFifoAltEmpty()) {
311 // Force a lock-up.
312 assertFail();
313 }
314 #endif
315 }
316
317 static void
318 scsiWritePIO(const uint8_t* data, uint32_t count)
319 {
320 uint16_t* fifoData = (uint16_t*)data;
321 for (int i = 0; i < (count + 1) / 2; ++i)
322 {
323 scsiPhyTx(fifoData[i]);
324 }
325 }
326
327 void
328 scsiWriteDMA(const uint8_t* data, uint32_t count)
329 {
330 // Prepare DMA transfer
331 dmaInProgress = 1;
332 trace(trace_doTxSingleDMA);
333
334 scsiTxDMAComplete = 0;
335 scsiRxDMAComplete = 1;
336
337 HAL_DMA_Start(
338 &memToFSMC,
339 (uint32_t) data,
340 (uint32_t) SCSI_FIFO_DATA,
341 count / 4);
342 }
343
344 int
345 scsiWriteDMAPoll()
346 {
347 int complete = __HAL_DMA_GET_COUNTER(&memToFSMC) == 0;
348 complete = complete && (HAL_DMA_PollForTransfer(&memToFSMC, HAL_DMA_FULL_TRANSFER, 0xffffffff) == HAL_OK);
349 if (complete)
350 {
351 scsiTxDMAComplete = 1; // TODO MM FIX IRQ
352 scsiRxDMAComplete = 1;
353
354 dmaInProgress = 0;
355 return 1;
356 }
357 else
358 {
359 return 0;
360 }
361 }
362
363 void
364 scsiWrite(const uint8_t* data, uint32_t count)
365 {
366 int i = 0;
367 while (i < count && likely(!scsiDev.resetFlag))
368 {
369 uint32_t chunk = ((count - i) > SCSI_FIFO_DEPTH)
370 ? SCSI_FIFO_DEPTH : (count - i);
371
372 #if FIFODEBUG
373 if (!scsiPhyFifoEmpty()) {
374 // Force a lock-up.
375 assertFail();
376 }
377 #endif
378
379 #ifdef SCSI_FSMC_DMA
380 if (chunk < 16)
381 #endif
382 {
383 scsiWritePIO(data + i, chunk);
384 }
385 #ifdef SCSI_FSMC_DMA
386 else
387 {
388 // DMA is doing 32bit transfers.
389 chunk = chunk & 0xFFFFFFF8;
390 scsiWriteDMA(data + i, chunk);
391
392 trace(trace_spinReadDMAPoll);
393
394 while (!scsiWriteDMAPoll() && likely(!scsiDev.resetFlag))
395 {
396 }
397 }
398 #endif
399
400 while (!scsiPhyComplete() && likely(!scsiDev.resetFlag))
401 {
402 __WFE(); // Wait for event
403 }
404
405 #if FIFODEBUG
406 if (!scsiPhyFifoAltEmpty()) {
407 // Force a lock-up.
408 assertFail();
409 }
410 #endif
411
412 scsiPhyFifoFlip();
413 scsiSetDataCount(chunk);
414 i += chunk;
415 }
416 while (!scsiPhyComplete() && likely(!scsiDev.resetFlag))
417 {
418 __WFE(); // Wait for event
419 }
420
421 #if FIFODEBUG
422 if (!scsiPhyFifoAltEmpty()) {
423 // Force a lock-up.
424 assertFail();
425 }
426 #endif
427 }
428
429 static inline void busSettleDelay(void)
430 {
431 // Data Release time (switching IO) = 400ns
432 // + Bus Settle time (switching phase) = 400ns.
433 s2s_delay_us(1); // Close enough.
434 }
435
436 void scsiEnterBusFree()
437 {
438 *SCSI_CTRL_BSY = 0x00;
439 // We now have a Bus Clear Delay of 800ns to release remaining signals.
440 *SCSI_CTRL_PHASE = 0;
441 }
442
443 void scsiEnterPhase(int phase)
444 {
445 // ANSI INCITS 362-2002 SPI-3 10.7.1:
446 // Phase changes are not allowed while REQ or ACK is asserted.
447 while (likely(!scsiDev.resetFlag) && scsiStatusACK()) {}
448
449 int newPhase = phase > 0 ? phase : 0;
450 int oldPhase = *SCSI_CTRL_PHASE;
451
452 if (!scsiDev.resetFlag && (!scsiPhyFifoEmpty() || !scsiPhyFifoAltEmpty())) {
453 // Force a lock-up.
454 assertFail();
455 }
456 if (newPhase != oldPhase)
457 {
458 if ((newPhase == DATA_IN || newPhase == DATA_OUT) &&
459 scsiDev.target->syncOffset)
460 {
461 if (scsiDev.target->syncPeriod == 12)
462 {
463 // SCSI2 FAST-20 Timing. 20MB/s.
464 *SCSI_CTRL_DESKEW = SCSI_FAST20_DESKEW;
465 *SCSI_CTRL_TIMING = SCSI_FAST20_TIMING;
466 }
467 else if (scsiDev.target->syncPeriod == 25)
468 {
469 // SCSI2 FAST Timing. 10MB/s.
470 *SCSI_CTRL_DESKEW = SCSI_FAST10_DESKEW;
471 *SCSI_CTRL_TIMING = SCSI_FAST10_TIMING;
472 }
473 else
474 {
475 *SCSI_CTRL_DESKEW = SCSI_SYNC_DESKEW(scsiDev.target->syncPeriod);
476 *SCSI_CTRL_TIMING = SCSI_SYNC_TIMING(scsiDev.target->syncPeriod);
477 }
478
479 *SCSI_CTRL_SYNC_OFFSET = scsiDev.target->syncOffset;
480 } else {
481 *SCSI_CTRL_SYNC_OFFSET = 0;
482
483 // 5MB/s Timing
484 *SCSI_CTRL_DESKEW = SCSI_DEFAULT_DESKEW;
485 *SCSI_CTRL_TIMING = SCSI_DEFAULT_TIMING;
486 }
487
488 *SCSI_CTRL_PHASE = newPhase;
489 busSettleDelay();
490
491 if (scsiDev.compatMode < COMPAT_SCSI2)
492 {
493 s2s_delay_us(100);
494 }
495
496 }
497 }
498
499 void scsiPhyReset()
500 {
501 trace(trace_scsiPhyReset);
502 if (dmaInProgress)
503 {
504 trace(trace_spinDMAReset);
505 HAL_DMA_Abort(&memToFSMC);
506 HAL_DMA_Abort(&fsmcToMem);
507
508 dmaInProgress = 0;
509 }
510
511 *SCSI_CTRL_PHASE = 0x00;
512 *SCSI_CTRL_BSY = 0x00;
513 s2s_fpgaReset(); // Clears fifos etc.
514
515 scsiPhyFifoSel = 0;
516 *SCSI_FIFO_SEL = 0;
517 *SCSI_CTRL_DBX = 0;
518
519 *SCSI_CTRL_SYNC_OFFSET = 0;
520 *SCSI_CTRL_DESKEW = SCSI_DEFAULT_DESKEW;
521 *SCSI_CTRL_TIMING = SCSI_DEFAULT_TIMING;
522
523 // DMA Benchmark code
524 // Currently 11MB/s.
525 #ifdef DMA_BENCHMARK
526 while(1)
527 {
528 s2s_ledOn();
529 // 100MB
530 for (int i = 0; i < (100LL * 1024 * 1024 / SCSI_FIFO_DEPTH); ++i)
531 {
532 HAL_DMA_Start(
533 &memToFSMC,
534 (uint32_t) &scsiDev.data[0],
535 (uint32_t) SCSI_FIFO_DATA,
536 SCSI_FIFO_DEPTH / 4);
537
538 HAL_DMA_PollForTransfer(
539 &memToFSMC,
540 HAL_DMA_FULL_TRANSFER,
541 0xffffffff);
542
543 s2s_fpgaReset();
544 }
545 s2s_ledOff();
546
547 for(int i = 0; i < 10; ++i) s2s_delay_ms(1000);
548 }
549 #endif
550
551 // FPGA comms test code
552 #ifdef FPGA_TEST
553 while(1)
554 {
555 for (int j = 0; j < SCSI_FIFO_DEPTH; ++j)
556 {
557 scsiDev.data[j] = j;
558 }
559
560 if (!scsiPhyFifoEmpty())
561 {
562 assertFail();
563 }
564
565 *SCSI_CTRL_PHASE = DATA_IN;
566 HAL_DMA_Start(
567 &memToFSMC,
568 (uint32_t) &scsiDev.data[0],
569 (uint32_t) SCSI_FIFO_DATA,
570 SCSI_FIFO_DEPTH / 4);
571
572 HAL_DMA_PollForTransfer(
573 &memToFSMC,
574 HAL_DMA_FULL_TRANSFER,
575 0xffffffff);
576
577 if (!scsiPhyFifoFull())
578 {
579 assertFail();
580 }
581
582 memset(&scsiDev.data[0], 0, SCSI_FIFO_DEPTH);
583
584 *SCSI_CTRL_PHASE = DATA_OUT;
585 HAL_DMA_Start(
586 &fsmcToMem,
587 (uint32_t) SCSI_FIFO_DATA,
588 (uint32_t) &scsiDev.data[0],
589 SCSI_FIFO_DEPTH / 2);
590
591 HAL_DMA_PollForTransfer(
592 &fsmcToMem,
593 HAL_DMA_FULL_TRANSFER,
594 0xffffffff);
595
596 if (!scsiPhyFifoEmpty())
597 {
598 assertFail();
599 }
600
601
602 for (int j = 0; j < SCSI_FIFO_DEPTH; ++j)
603 {
604 if (scsiDev.data[j] != (uint8_t) j)
605 {
606 assertFail();
607 }
608 }
609
610 s2s_fpgaReset();
611
612 }
613 #endif
614
615 #ifdef SCSI_FREQ_TEST
616 while(1)
617 {
618 *SCSI_CTRL_DBX = 0xAA;
619 *SCSI_CTRL_DBX = 0x55;
620 }
621 #endif
622
623 }
624
625 static void scsiPhyInitDMA()
626 {
627 // One-time init only.
628 static uint8_t init = 0;
629 if (init == 0)
630 {
631 init = 1;
632
633 // Memory to memory transfers can only be done using DMA2
634 __DMA2_CLK_ENABLE();
635
636 // Transmit SCSI data. The source data is treated as the
637 // peripheral (even though this is memory-to-memory)
638 memToFSMC.Instance = DMA2_Stream0;
639 memToFSMC.Init.Channel = DMA_CHANNEL_0;
640 memToFSMC.Init.Direction = DMA_MEMORY_TO_MEMORY;
641 memToFSMC.Init.PeriphInc = DMA_PINC_ENABLE;
642 memToFSMC.Init.MemInc = DMA_MINC_DISABLE;
643 memToFSMC.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
644 memToFSMC.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
645 memToFSMC.Init.Mode = DMA_NORMAL;
646 memToFSMC.Init.Priority = DMA_PRIORITY_LOW;
647 // FIFO mode is needed to allow conversion from 32bit words to the
648 // 16bit FSMC interface.
649 memToFSMC.Init.FIFOMode = DMA_FIFOMODE_ENABLE;
650
651 // We only use 1 word (4 bytes) in the fifo at a time. Normally it's
652 // better to let the DMA fifo fill up then do burst transfers, but
653 // bursting out the FSMC interface will be very slow and may starve
654 // other (faster) transfers. We don't want to risk the SDIO transfers
655 // from overrun/underrun conditions.
656 memToFSMC.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_1QUARTERFULL;
657 memToFSMC.Init.MemBurst = DMA_MBURST_SINGLE;
658 memToFSMC.Init.PeriphBurst = DMA_PBURST_SINGLE;
659 HAL_DMA_Init(&memToFSMC);
660
661 // Receive SCSI data. The source data (fsmc) is treated as the
662 // peripheral (even though this is memory-to-memory)
663 fsmcToMem.Instance = DMA2_Stream1;
664 fsmcToMem.Init.Channel = DMA_CHANNEL_0;
665 fsmcToMem.Init.Direction = DMA_MEMORY_TO_MEMORY;
666 fsmcToMem.Init.PeriphInc = DMA_PINC_DISABLE;
667 fsmcToMem.Init.MemInc = DMA_MINC_ENABLE;
668 fsmcToMem.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
669 fsmcToMem.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
670 fsmcToMem.Init.Mode = DMA_NORMAL;
671 fsmcToMem.Init.Priority = DMA_PRIORITY_LOW;
672 fsmcToMem.Init.FIFOMode = DMA_FIFOMODE_ENABLE;
673 fsmcToMem.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_1QUARTERFULL;
674 fsmcToMem.Init.MemBurst = DMA_MBURST_SINGLE;
675 fsmcToMem.Init.PeriphBurst = DMA_PBURST_SINGLE;
676 HAL_DMA_Init(&fsmcToMem);
677
678 // TODO configure IRQs
679 }
680 }
681
682
683 void scsiPhyInit()
684 {
685 scsiPhyInitDMA();
686
687 *SCSI_CTRL_IDMASK = 0x00; // Reset in scsiPhyConfig
688 *SCSI_CTRL_PHASE = 0x00;
689 *SCSI_CTRL_BSY = 0x00;
690 scsiPhyFifoSel = 0;
691 *SCSI_FIFO_SEL = 0;
692 *SCSI_CTRL_DBX = 0;
693
694 *SCSI_CTRL_SYNC_OFFSET = 0;
695 *SCSI_CTRL_DESKEW = SCSI_DEFAULT_DESKEW;
696 *SCSI_CTRL_TIMING = SCSI_DEFAULT_TIMING;
697
698 *SCSI_CTRL_SEL_TIMING = SCSI_DEFAULT_SELECTION;
699
700 }
701
702 void scsiPhyConfig()
703 {
704 if (scsiDev.boardCfg.flags6 & S2S_CFG_ENABLE_TERMINATOR)
705 {
706 HAL_GPIO_WritePin(nTERM_EN_GPIO_Port, nTERM_EN_Pin, GPIO_PIN_RESET);
707 }
708 else
709 {
710 HAL_GPIO_WritePin(nTERM_EN_GPIO_Port, nTERM_EN_Pin, GPIO_PIN_SET);
711 }
712
713
714 uint8_t idMask = 0;
715 for (int i = 0; i < 8; ++i)
716 {
717 const S2S_TargetCfg* cfg = s2s_getConfigById(i);
718 if (cfg && (cfg->scsiId & S2S_CFG_TARGET_ENABLED))
719 {
720 idMask |= (1 << i);
721 }
722 }
723 *SCSI_CTRL_IDMASK = idMask;
724
725 *SCSI_CTRL_FLAGS =
726 ((scsiDev.boardCfg.flags & S2S_CFG_DISABLE_GLITCH) ?
727 SCSI_CTRL_FLAGS_DISABLE_GLITCH : 0) |
728 ((scsiDev.boardCfg.flags & S2S_CFG_ENABLE_PARITY) ?
729 SCSI_CTRL_FLAGS_ENABLE_PARITY : 0);
730
731 *SCSI_CTRL_SEL_TIMING =
732 (scsiDev.boardCfg.flags & S2S_CFG_ENABLE_SEL_LATCH) ?
733 SCSI_FAST_SELECTION : SCSI_DEFAULT_SELECTION;
734 }
735
736
737 // 1 = DBx error
738 // 2 = Parity error
739 // 4 = MSG error
740 // 8 = CD error
741 // 16 = IO error
742 // 32 = other error
743 int scsiSelfTest()
744 {
745 if (scsiDev.phase != BUS_FREE)
746 {
747 return 32;
748 }
749
750 // Acquire the SCSI bus.
751 for (int i = 0; i < 100; ++i)
752 {
753 if (scsiStatusBSY())
754 {
755 s2s_delay_ms(1);
756 }
757 }
758 if (scsiStatusBSY())
759 {
760 // Error, couldn't acquire scsi bus
761 return 32;
762 }
763 *SCSI_CTRL_BSY = 1;
764 if (! scsiStatusBSY())
765 {
766 // Error, BSY doesn't work.
767 return 32;
768 }
769
770 // Should be safe to use the bus now.
771
772 int result = 0;
773
774 // TEST DBx
775 // TODO test DBp
776 int i;
777 for (i = 0; i < 256; ++i)
778 {
779 *SCSI_CTRL_DBX = i;
780 busSettleDelay();
781 if (*SCSI_STS_DBX != (i & 0xff))
782 {
783 result |= 1;
784 }
785 /*if (Lookup_OddParity[i & 0xff] != SCSI_ReadPin(SCSI_In_DBP))
786 {
787 result |= 2;
788 }*/
789 }
790 *SCSI_CTRL_DBX = 0;
791
792 // TEST MSG, CD, IO
793 /* TODO
794 for (i = 0; i < 8; ++i)
795 {
796 SCSI_CTL_PHASE_Write(i);
797 scsiDeskewDelay();
798
799 if (SCSI_ReadPin(SCSI_In_MSG) != !!(i & __scsiphase_msg))
800 {
801 result |= 4;
802 }
803 if (SCSI_ReadPin(SCSI_In_CD) != !!(i & __scsiphase_cd))
804 {
805 result |= 8;
806 }
807 if (SCSI_ReadPin(SCSI_In_IO) != !!(i & __scsiphase_io))
808 {
809 result |= 16;
810 }
811 }
812 SCSI_CTL_PHASE_Write(0);
813
814 uint32_t signalsOut[] = { SCSI_Out_ATN, SCSI_Out_BSY, SCSI_Out_RST, SCSI_Out_SEL };
815 uint32_t signalsIn[] = { SCSI_Filt_ATN, SCSI_Filt_BSY, SCSI_Filt_RST, SCSI_Filt_SEL };
816
817 for (i = 0; i < 4; ++i)
818 {
819 SCSI_SetPin(signalsOut[i]);
820 scsiDeskewDelay();
821
822 int j;
823 for (j = 0; j < 4; ++j)
824 {
825 if (i == j)
826 {
827 if (! SCSI_ReadFilt(signalsIn[j]))
828 {
829 result |= 32;
830 }
831 }
832 else
833 {
834 if (SCSI_ReadFilt(signalsIn[j]))
835 {
836 result |= 32;
837 }
838 }
839 }
840 SCSI_ClearPin(signalsOut[i]);
841 }
842 */
843
844 *SCSI_CTRL_BSY = 0;
845 return result;
846 }
847
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