}\r
}\r
\r
-static void assertFail()\r
-{\r
- while (1)\r
- {\r
- s2s_ledOn();\r
- s2s_delay_ms(100);\r
- s2s_ledOff();\r
- s2s_delay_ms(100);\r
- }\r
-}\r
-\r
void\r
scsiSetDataCount(uint32_t count)\r
{\r
// TODO Test DBP\r
*SCSI_CTRL_DBX = 0;\r
\r
- // FPGA comms test code\r
- for(i = 0; i < 10000; ++i)\r
- {\r
- for (int j = 0; j < SCSI_FIFO_DEPTH; ++j)\r
- {\r
- scsiDev.data[j] = j;\r
- }\r
-\r
- if (!scsiPhyFifoEmpty())\r
- {\r
- assertFail();\r
- }\r
-\r
- *SCSI_CTRL_PHASE = DATA_IN;\r
- HAL_DMA_Start(\r
- &memToFSMC,\r
- (uint32_t) &scsiDev.data[0],\r
- (uint32_t) SCSI_FIFO_DATA,\r
- SCSI_FIFO_DEPTH / 4);\r
-\r
- HAL_DMA_PollForTransfer(\r
- &memToFSMC,\r
- HAL_DMA_FULL_TRANSFER,\r
- 0xffffffff);\r
-\r
- if (!scsiPhyFifoFull())\r
- {\r
- assertFail();\r
- }\r
-\r
- memset(&scsiDev.data[0], 0, SCSI_FIFO_DEPTH);\r
-\r
- *SCSI_CTRL_PHASE = DATA_OUT;\r
- HAL_DMA_Start(\r
- &fsmcToMem,\r
- (uint32_t) SCSI_FIFO_DATA,\r
- (uint32_t) &scsiDev.data[0],\r
- SCSI_FIFO_DEPTH / 2);\r
-\r
- HAL_DMA_PollForTransfer(\r
- &fsmcToMem,\r
- HAL_DMA_FULL_TRANSFER,\r
- 0xffffffff);\r
-\r
- if (!scsiPhyFifoEmpty())\r
- {\r
- assertFail();\r
- }\r
-\r
-\r
- for (int j = 0; j < SCSI_FIFO_DEPTH; ++j)\r
- {\r
- if (scsiDev.data[j] != (uint8_t) j)\r
- {\r
- result |= 64;\r
- }\r
- }\r
-\r
- s2s_fpgaReset();\r
-\r
- }\r
-\r
*SCSI_CTRL_BSY = 0;\r
+\r
return result;\r
}\r
\r