More updates for V6 2020c hardware

diff --git a/rtl/fpga_bitmap.o b/rtl/fpga_bitmap.o
index 1f5749df3c5ce310b63b81b76500598a632c602c..ccfcd0dd19e229380b5d35ff7137c54ecb1f190b 100644 (file)
Binary files a/rtl/fpga_bitmap.o and b/rtl/fpga_bitmap.o differ

diff --git a/src/firmware/scsiPhy.c b/src/firmware/scsiPhy.c
index 2f27b1fda7fa25a40c00d2171c79043f2d136d90..8da0a098e83b4f50f5dd21d41f8b5fb29f980eeb 100755 (executable)
--- a/src/firmware/scsiPhy.c
+++ b/src/firmware/scsiPhy.c
@@ -943,25 +943,6 @@ int scsiSelfTest()
                result = 1;\r
        }\r
 \r
-       // TEST DBx\r
-       int i;\r
-       for (i = 0; i < 8; ++i)\r
-       {\r
-               uint8_t data = 1 << i;\r
-               *SCSI_CTRL_DBX = 0;\r
-               busSettleDelay();\r
-               *SCSI_CTRL_DBX = data;\r
-               busSettleDelay();\r
-               // STS_DBX is 16 bit!\r
-               if ((*SCSI_STS_DBX & 0xff) != data)\r
-               {\r
-                       result = i + 2;\r
-               }\r
-       }\r
-\r
-       // TODO Test DBP\r
-       *SCSI_CTRL_DBX = 0;\r
-\r
        *SCSI_CTRL_BSY = 0;\r
 \r
        return result;\r

diff --git a/src/firmware/scsiPhy.h b/src/firmware/scsiPhy.h
index 360d594cb347ae43b71a9811dba7c3709283ba35..8b54f161227f29254f1d276fd48282518f17f89e 100755 (executable)
--- a/src/firmware/scsiPhy.h
+++ b/src/firmware/scsiPhy.h
@@ -56,9 +56,6 @@
 // Replaced with method due to delays
 // #define scsiFifoReady() (HAL_GPIO_ReadPin(GPIOE, FPGA_GPIO3_Pin) != 0)
 
-#define scsiPhyFifoFull() ((*SCSI_STS_FIFO & 0x01) != 0)
-#define scsiPhyFifoEmpty() ((*SCSI_STS_FIFO & 0x02) != 0)
-
 #define scsiPhyTx(val) *SCSI_FIFO_DATA = (val)
 
 // little endian specific !. Also relies on the fsmc outputting the lower